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GSimas/EEL5105 | PROJETO-EEL5105/Projeto/map3.vhd | 1 | 953 | library ieee;
use ieee.std_logic_1164.all;
entity map3 is
port
(
F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13, F14, F15: out std_logic_vector(31 downto 0)
);
end map3;
architecture map3_struct of map3 is
begin
F0 <= "00000000000000000000110000000000";
F1 <= "00000001000000011000110000011000";
F2 <= "00000000100000000100000000011000";
F3 <= "00000000010000000000001100000100";
F4 <= "00000000000000001000000000000000";
F5 <= "00000000000000011000001000000010";
F6 <= "00000000000000111000000010001110";
F7 <= "00000000000000000000000000000000";
F8 <= "00000010000000000000010000000010";
F9 <= "00000000000000011000110001000110";
F10 <= "00000100000000001000000000110000";
F11 <= "00000000011000001000000000100000";
F12 <= "00000000011000000100000000000000";
F13 <= "00000010000000000000110000100000";
F14 <= "00000000010000000000000011011000";
F15 <= "00010000000010000100000000011000";
end map3_struct; | mit | 0383ad68f1ef1e9a739ebdb60bb5bb24 | 0.75341 | 3.391459 | false | false | false | false |
hoglet67/AtomFpga | src/common/AVR8/CommonPacks/std_library.vhd | 3 | 10,290 | -- *****************************************************************************************
-- Standard libraries
-- Version 0.2
-- Modified 02.12.2006
-- Designed by Ruslan Lepetenok
-- *****************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package std_library is
type log2array_type is array(0 to 1024) of integer;
constant fn_log2 : log2array_type := (
0,0,1,2,2,3,3,3,3,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,
6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,
7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
others => 10);
constant fn_log2x : log2array_type := (
0,1,1,2,2,3,3,3,3,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,
6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,
7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
others => 10);
-- *********************************************************************************
function fn_det_x(d : std_logic_vector) return boolean;
function fn_det_x(d : std_logic) return boolean;
function fn_xor_vect(vect : std_logic_vector) return std_logic;
function fn_or_vect(vect : std_logic_vector) return std_logic;
function fn_and_vect(vect : std_logic_vector) return std_logic;
function fn_to_integer(vect : std_logic_vector) return integer;
function fn_to_integer(d : std_logic) return integer;
function fn_to_std_logic_vector(int : integer; width : integer) return std_logic_vector;
function fn_to_std_logic_vector_signed(int : integer; width : integer) return std_logic_vector;
function fn_to_std_logic(b : boolean) return std_logic;
function fn_dcd(vect : std_logic_vector) return std_logic_vector;
function fn_mux(sel : std_logic_vector; vect : std_logic_vector) return std_logic;
function "+" (vect : std_logic_vector; int : integer) return std_logic_vector;
function "+" (vect : std_logic_vector; d : std_logic) return std_logic_vector;
function "+" (vect_a : std_logic_vector; vect_b : std_logic_vector) return std_logic_vector;
function "-" (vect : std_logic_vector; int : integer) return std_logic_vector;
function "-" (int : integer; vect : std_logic_vector) return std_logic_vector;
function "-" (vect : std_logic_vector; d : std_logic) return std_logic_vector;
function "-" (vect_a : std_logic_vector; vect_b : std_logic_vector) return std_logic_vector;
end std_library;
package body std_library is
function fn_det_x(d : std_logic_vector) return boolean is
variable result : boolean;
begin
result := FALSE;
-- pragma translate_off
result := is_x(d);
-- pragma translate_on
return (result);
end fn_det_x;
function fn_det_x(d : std_logic) return boolean is
variable result : boolean;
begin
result := FALSE;
-- pragma translate_off
result := is_x(d);
-- pragma translate_on
return (result);
end fn_det_x;
function fn_xor_vect(vect : std_logic_vector) return std_logic is
variable temp : std_logic;
begin
temp := '0';
for i in vect'range loop
temp := temp xor vect(i);
end loop;
return(temp);
end fn_xor_vect;
function fn_or_vect(vect : std_logic_vector) return std_logic is
variable temp : std_logic;
begin
temp := '0';
for i in vect'range loop
temp := temp or vect(i);
end loop;
return(temp);
end fn_or_vect;
function fn_and_vect(vect : std_logic_vector) return std_logic is
variable temp : std_logic;
begin
temp := '1';
for i in vect'range loop
temp := temp and vect(i);
end loop;
return(temp);
end fn_and_vect;
function fn_to_integer(vect : std_logic_vector) return integer is
begin
if (not fn_det_x(vect)) then
return(to_integer(unsigned(vect)));
else
return(0);
end if;
end fn_to_integer;
function fn_to_integer(d : std_logic) return integer is
begin
if (not fn_det_x(d)) then
if (d = '1') then
return(1);
else
return(0);
end if;
else
return(0);
end if;
end fn_to_integer;
function fn_to_std_logic_vector(int : integer; width : integer) return std_logic_vector is
variable temp : std_logic_vector(width-1 downto 0);
begin
temp := std_logic_vector(to_unsigned(int, width));
return(temp);
end fn_to_std_logic_vector;
function fn_to_std_logic_vector_signed(int : integer; width : integer) return std_logic_vector is
variable temp : std_logic_vector(width-1 downto 0);
begin
temp := std_logic_vector(to_signed(int, width));
return(temp);
end fn_to_std_logic_vector_signed;
function fn_to_std_logic(b : boolean) return std_logic is
begin
if (b) then
return('1');
else
return('0');
end if;
end fn_to_std_logic;
function fn_dcd(vect : std_logic_vector) return std_logic_vector is
variable result : std_logic_vector((2**vect'length)-1 downto 0);
variable i : integer range result'range;
begin
result := (others => '0');
i := 0;
if (not fn_det_x(vect)) then
i := to_integer(unsigned(vect));
end if;
result(i) := '1';
return(result);
end fn_dcd;
function fn_mux(sel : std_logic_vector; vect : std_logic_vector) return std_logic is
variable result : std_logic_vector(vect'length-1 downto 0);
variable i : integer range result'range;
begin
result := vect;
i := 0;
if (not fn_det_x(sel)) then
i := to_integer(unsigned(sel));
end if;
return(result(i));
end fn_mux;
-- >>>>
function "+" (vect_a : std_logic_vector; vect_b : std_logic_vector) return std_logic_vector is
variable tmp_a : std_logic_vector(vect_a'length-1 downto 0);
variable tmp_b : std_logic_vector(vect_b'length-1 downto 0);
begin
-- pragma translate_off
if (fn_det_x(vect_a) or fn_det_x(vect_b)) then
tmp_a := (others =>'X');
tmp_b := (others =>'X');
if (tmp_a'length > tmp_b'length) then
return(tmp_a);
else
return(tmp_b);
end if;
end if;
-- pragma translate_on
return(std_logic_vector(unsigned(vect_a) + unsigned(vect_b)));
end "+";
function "+" (vect : std_logic_vector; int : integer) return std_logic_vector is
variable temp : std_logic_vector(vect'length-1 downto 0);
begin
-- pragma translate_off
if (fn_det_x(vect)) then
temp := (others =>'X');
return(temp);
end if;
-- pragma translate_on
return(std_logic_vector(unsigned(vect) + int));
end "+";
function "+" (vect : std_logic_vector; d : std_logic) return std_logic_vector is
variable tmp_a : std_logic_vector(vect'length-1 downto 0);
variable tmp_b : std_logic_vector(0 downto 0);
begin
tmp_b(0) := d;
-- pragma translate_off
if (fn_det_x(vect) or fn_det_x(d)) then
tmp_b := (others =>'X');
return(tmp_b);
end if;
-- pragma translate_on
return(std_logic_vector(unsigned(vect) + unsigned(tmp_b)));
end "+";
function "-" (vect_a : std_logic_vector; vect_b : std_logic_vector) return std_logic_vector is
variable tmp_a : std_logic_vector(vect_a'length-1 downto 0);
variable tmp_b : std_logic_vector(vect_b'length-1 downto 0);
begin
-- pragma translate_off
if (fn_det_x(vect_a) or fn_det_x(vect_b)) then
tmp_a := (others =>'X'); tmp_b := (others =>'X');
if (tmp_a'length > tmp_b'length) then
return(tmp_a);
else
return(tmp_b);
end if;
end if;
-- pragma translate_on
return(std_logic_vector(unsigned(vect_a) - unsigned(vect_b)));
end "-";
function "-" (vect : std_logic_vector; int : integer) return std_logic_vector is
variable temp : std_logic_vector(vect'length-1 downto 0);
begin
-- pragma translate_off
if (fn_det_x(vect)) then
temp := (others =>'X');
return(temp);
end if;
-- pragma translate_on
return(std_logic_vector(unsigned(vect) - int));
end "-";
function "-" (int : integer; vect : std_logic_vector) return std_logic_vector is
variable temp : std_logic_vector(vect'length-1 downto 0);
begin
-- pragma translate_off
if (fn_det_x(vect)) then
temp := (others =>'X');
return(temp);
end if;
-- pragma translate_on
return(std_logic_vector(int - unsigned(vect)));
end "-";
function "-" (vect : std_logic_vector; d : std_logic) return std_logic_vector is
variable tmp_a : std_logic_vector(vect'length-1 downto 0);
variable tmp_b : std_logic_vector(0 downto 0);
begin
tmp_b(0) := d;
-- pragma translate_off
if (fn_det_x(vect) or fn_det_x(d)) then
tmp_a := (others =>'X');
return(tmp_a);
end if;
-- pragma translate_on
return(std_logic_vector(unsigned(vect) - unsigned(tmp_b)));
end "-";
end std_library;
| apache-2.0 | 36df54637f35136f34c6ba282e378670 | 0.600875 | 2.169056 | false | false | false | false |
tghaefli/ADD | EDK/IVK_Repos/IVK_IPLib/pcores/sg_xsvi_fanout_plbw_v1_01_a/hdl/vhdl/sg_xsvi_fanout_cw.vhd | 1 | 20,514 |
-------------------------------------------------------------------
-- System Generator version 13.2 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
-------------------------------------------------------------------
-- System Generator version 13.2 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
-- synopsys translate_off
library unisim;
use unisim.vcomponents.all;
-- synopsys translate_on
entity xlclockdriver is
generic (
period: integer := 2;
log_2_period: integer := 0;
pipeline_regs: integer := 5;
use_bufg: integer := 0
);
port (
sysclk: in std_logic;
sysclr: in std_logic;
sysce: in std_logic;
clk: out std_logic;
clr: out std_logic;
ce: out std_logic;
ce_logic: out std_logic
);
end xlclockdriver;
architecture behavior of xlclockdriver is
component bufg
port (
i: in std_logic;
o: out std_logic
);
end component;
component synth_reg_w_init
generic (
width: integer;
init_index: integer;
init_value: bit_vector;
latency: integer
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end component;
function size_of_uint(inp: integer; power_of_2: boolean)
return integer
is
constant inp_vec: std_logic_vector(31 downto 0) :=
integer_to_std_logic_vector(inp,32, xlUnsigned);
variable result: integer;
begin
result := 32;
for i in 0 to 31 loop
if inp_vec(i) = '1' then
result := i;
end if;
end loop;
if power_of_2 then
return result;
else
return result+1;
end if;
end;
function is_power_of_2(inp: std_logic_vector)
return boolean
is
constant width: integer := inp'length;
variable vec: std_logic_vector(width - 1 downto 0);
variable single_bit_set: boolean;
variable more_than_one_bit_set: boolean;
variable result: boolean;
begin
vec := inp;
single_bit_set := false;
more_than_one_bit_set := false;
-- synopsys translate_off
if (is_XorU(vec)) then
return false;
end if;
-- synopsys translate_on
if width > 0 then
for i in 0 to width - 1 loop
if vec(i) = '1' then
if single_bit_set then
more_than_one_bit_set := true;
end if;
single_bit_set := true;
end if;
end loop;
end if;
if (single_bit_set and not(more_than_one_bit_set)) then
result := true;
else
result := false;
end if;
return result;
end;
function ce_reg_init_val(index, period : integer)
return integer
is
variable result: integer;
begin
result := 0;
if ((index mod period) = 0) then
result := 1;
end if;
return result;
end;
function remaining_pipe_regs(num_pipeline_regs, period : integer)
return integer
is
variable factor, result: integer;
begin
factor := (num_pipeline_regs / period);
result := num_pipeline_regs - (period * factor) + 1;
return result;
end;
function sg_min(L, R: INTEGER) return INTEGER is
begin
if L < R then
return L;
else
return R;
end if;
end;
constant max_pipeline_regs : integer := 8;
constant pipe_regs : integer := 5;
constant num_pipeline_regs : integer := sg_min(pipeline_regs, max_pipeline_regs);
constant rem_pipeline_regs : integer := remaining_pipe_regs(num_pipeline_regs,period);
constant period_floor: integer := max(2, period);
constant power_of_2_counter: boolean :=
is_power_of_2(integer_to_std_logic_vector(period_floor,32, xlUnsigned));
constant cnt_width: integer :=
size_of_uint(period_floor, power_of_2_counter);
constant clk_for_ce_pulse_minus1: std_logic_vector(cnt_width - 1 downto 0) :=
integer_to_std_logic_vector((period_floor - 2),cnt_width, xlUnsigned);
constant clk_for_ce_pulse_minus2: std_logic_vector(cnt_width - 1 downto 0) :=
integer_to_std_logic_vector(max(0,period - 3),cnt_width, xlUnsigned);
constant clk_for_ce_pulse_minus_regs: std_logic_vector(cnt_width - 1 downto 0) :=
integer_to_std_logic_vector(max(0,period - rem_pipeline_regs),cnt_width, xlUnsigned);
signal clk_num: unsigned(cnt_width - 1 downto 0) := (others => '0');
signal ce_vec : std_logic_vector(num_pipeline_regs downto 0);
attribute MAX_FANOUT : string;
attribute MAX_FANOUT of ce_vec:signal is "REDUCE";
signal ce_vec_logic : std_logic_vector(num_pipeline_regs downto 0);
attribute MAX_FANOUT of ce_vec_logic:signal is "REDUCE";
signal internal_ce: std_logic_vector(0 downto 0);
signal internal_ce_logic: std_logic_vector(0 downto 0);
signal cnt_clr, cnt_clr_dly: std_logic_vector (0 downto 0);
begin
clk <= sysclk;
clr <= sysclr;
cntr_gen: process(sysclk)
begin
if sysclk'event and sysclk = '1' then
if (sysce = '1') then
if ((cnt_clr_dly(0) = '1') or (sysclr = '1')) then
clk_num <= (others => '0');
else
clk_num <= clk_num + 1;
end if;
end if;
end if;
end process;
clr_gen: process(clk_num, sysclr)
begin
if power_of_2_counter then
cnt_clr(0) <= sysclr;
else
if (unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus1
or sysclr = '1') then
cnt_clr(0) <= '1';
else
cnt_clr(0) <= '0';
end if;
end if;
end process;
clr_reg: synth_reg_w_init
generic map (
width => 1,
init_index => 0,
init_value => b"0000",
latency => 1
)
port map (
i => cnt_clr,
ce => sysce,
clr => sysclr,
clk => sysclk,
o => cnt_clr_dly
);
pipelined_ce : if period > 1 generate
ce_gen: process(clk_num)
begin
if unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus_regs then
ce_vec(num_pipeline_regs) <= '1';
else
ce_vec(num_pipeline_regs) <= '0';
end if;
end process;
ce_pipeline: for index in num_pipeline_regs downto 1 generate
ce_reg : synth_reg_w_init
generic map (
width => 1,
init_index => ce_reg_init_val(index, period),
init_value => b"0000",
latency => 1
)
port map (
i => ce_vec(index downto index),
ce => sysce,
clr => sysclr,
clk => sysclk,
o => ce_vec(index-1 downto index-1)
);
end generate;
internal_ce <= ce_vec(0 downto 0);
end generate;
pipelined_ce_logic: if period > 1 generate
ce_gen_logic: process(clk_num)
begin
if unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus_regs then
ce_vec_logic(num_pipeline_regs) <= '1';
else
ce_vec_logic(num_pipeline_regs) <= '0';
end if;
end process;
ce_logic_pipeline: for index in num_pipeline_regs downto 1 generate
ce_logic_reg : synth_reg_w_init
generic map (
width => 1,
init_index => ce_reg_init_val(index, period),
init_value => b"0000",
latency => 1
)
port map (
i => ce_vec_logic(index downto index),
ce => sysce,
clr => sysclr,
clk => sysclk,
o => ce_vec_logic(index-1 downto index-1)
);
end generate;
internal_ce_logic <= ce_vec_logic(0 downto 0);
end generate;
use_bufg_true: if period > 1 and use_bufg = 1 generate
ce_bufg_inst: bufg
port map (
i => internal_ce(0),
o => ce
);
ce_bufg_inst_logic: bufg
port map (
i => internal_ce_logic(0),
o => ce_logic
);
end generate;
use_bufg_false: if period > 1 and (use_bufg = 0) generate
ce <= internal_ce(0);
ce_logic <= internal_ce_logic(0);
end generate;
generate_system_clk: if period = 1 generate
ce <= sysce;
ce_logic <= sysce;
end generate;
end architecture behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity default_clock_driver is
port (
sysce: in std_logic;
sysce_clr: in std_logic;
sysclk: in std_logic;
ce_1: out std_logic;
clk_1: out std_logic
);
end default_clock_driver;
architecture structural of default_clock_driver is
attribute syn_noprune: boolean;
attribute syn_noprune of structural : architecture is true;
attribute optimize_primitives: boolean;
attribute optimize_primitives of structural : architecture is false;
attribute dont_touch: boolean;
attribute dont_touch of structural : architecture is true;
signal sysce_clr_x0: std_logic;
signal sysce_x0: std_logic;
signal sysclk_x0: std_logic;
signal xlclockdriver_1_ce: std_logic;
signal xlclockdriver_1_clk: std_logic;
begin
sysce_x0 <= sysce;
sysce_clr_x0 <= sysce_clr;
sysclk_x0 <= sysclk;
ce_1 <= xlclockdriver_1_ce;
clk_1 <= xlclockdriver_1_clk;
xlclockdriver_1: entity work.xlclockdriver
generic map (
log_2_period => 1,
period => 1,
use_bufg => 0
)
port map (
sysce => sysce_x0,
sysclk => sysclk_x0,
sysclr => sysce_clr_x0,
ce => xlclockdriver_1_ce,
clk => xlclockdriver_1_clk
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity plb_clock_driver is
port (
sysce: in std_logic;
sysce_clr: in std_logic;
sysclk: in std_logic;
plb_ce_1: out std_logic;
plb_clk_1: out std_logic
);
end plb_clock_driver;
architecture structural of plb_clock_driver is
attribute syn_noprune: boolean;
attribute syn_noprune of structural : architecture is true;
attribute optimize_primitives: boolean;
attribute optimize_primitives of structural : architecture is false;
attribute dont_touch: boolean;
attribute dont_touch of structural : architecture is true;
signal sysce_clr_x0: std_logic;
signal sysce_x0: std_logic;
signal sysclk_x0: std_logic;
signal xlclockdriver_1_ce: std_logic;
signal xlclockdriver_1_clk: std_logic;
begin
sysce_x0 <= sysce;
sysce_clr_x0 <= sysce_clr;
sysclk_x0 <= sysclk;
plb_ce_1 <= xlclockdriver_1_ce;
plb_clk_1 <= xlclockdriver_1_clk;
xlclockdriver_1: entity work.xlclockdriver
generic map (
log_2_period => 1,
period => 1,
use_bufg => 0
)
port map (
sysce => sysce_x0,
sysclk => sysclk_x0,
sysclr => sysce_clr_x0,
ce => xlclockdriver_1_ce,
clk => xlclockdriver_1_clk
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity sg_xsvi_fanout_cw is
port (
active_video_i: in std_logic;
ce: in std_logic := '1';
clk: in std_logic; -- clock period = 10.0 ns (100.0 Mhz)
hblank_i: in std_logic;
hsync_i: in std_logic;
plb_abus: in std_logic_vector(31 downto 0);
plb_pavalid: in std_logic;
plb_rnw: in std_logic;
plb_wrdbus: in std_logic_vector(31 downto 0);
sg_plb_addrpref: in std_logic_vector(19 downto 0);
splb_rst: in std_logic;
vblank_i: in std_logic;
video_data_i: in std_logic_vector(23 downto 0);
vsync_i: in std_logic;
xps_ce: in std_logic := '1';
xps_clk: in std_logic; -- clock period = 10.0 ns (100.0 Mhz)
active_video_o: out std_logic;
hblank_o: out std_logic;
hsync_o: out std_logic;
sl_addrack: out std_logic;
sl_rdcomp: out std_logic;
sl_rddack: out std_logic;
sl_rddbus: out std_logic_vector(31 downto 0);
sl_wait: out std_logic;
sl_wrcomp: out std_logic;
sl_wrdack: out std_logic;
vblank_o: out std_logic;
video_data_o: out std_logic_vector(23 downto 0);
vsync_o: out std_logic
);
end sg_xsvi_fanout_cw;
architecture structural of sg_xsvi_fanout_cw is
component xlpersistentdff
port (
clk: in std_logic;
d: in std_logic;
q: out std_logic
);
end component;
attribute syn_black_box: boolean;
attribute syn_black_box of xlpersistentdff: component is true;
attribute box_type: string;
attribute box_type of xlpersistentdff: component is "black_box";
attribute syn_noprune: boolean;
attribute optimize_primitives: boolean;
attribute dont_touch: boolean;
attribute syn_noprune of xlpersistentdff: component is true;
attribute optimize_primitives of xlpersistentdff: component is false;
attribute dont_touch of xlpersistentdff: component is true;
signal active_video_i_net: std_logic;
signal active_video_o_net: std_logic;
signal ce_1_sg_x0: std_logic;
attribute MAX_FANOUT: string;
attribute MAX_FANOUT of ce_1_sg_x0: signal is "REDUCE";
signal clkNet: std_logic;
signal clkNet_x0: std_logic;
signal clk_1_sg_x0: std_logic;
signal hblank_i_net: std_logic;
signal hblank_o_net: std_logic;
signal hsync_i_net: std_logic;
signal hsync_o_net: std_logic;
signal persistentdff_inst_q: std_logic;
attribute syn_keep: boolean;
attribute syn_keep of persistentdff_inst_q: signal is true;
attribute keep: boolean;
attribute keep of persistentdff_inst_q: signal is true;
attribute preserve_signal: boolean;
attribute preserve_signal of persistentdff_inst_q: signal is true;
signal plb_abus_net: std_logic_vector(31 downto 0);
signal plb_ce_1_sg_x1: std_logic;
attribute MAX_FANOUT of plb_ce_1_sg_x1: signal is "REDUCE";
signal plb_clk_1_sg_x1: std_logic;
signal plb_pavalid_net: std_logic;
signal plb_rnw_net: std_logic;
signal plb_wrdbus_net: std_logic_vector(31 downto 0);
signal sg_plb_addrpref_net: std_logic_vector(19 downto 0);
signal sl_addrack_net: std_logic;
signal sl_rdcomp_net: std_logic;
signal sl_rddack_net: std_logic;
signal sl_rddbus_net: std_logic_vector(31 downto 0);
signal sl_wait_net: std_logic;
signal sl_wrdack_x1: std_logic;
signal sl_wrdack_x2: std_logic;
signal splb_rst_net: std_logic;
signal vblank_i_net: std_logic;
signal vblank_o_net: std_logic;
signal video_data_i_net: std_logic_vector(23 downto 0);
signal video_data_o_net: std_logic_vector(23 downto 0);
signal vsync_i_net: std_logic;
signal vsync_o_net: std_logic;
begin
active_video_i_net <= active_video_i;
clkNet <= clk;
hblank_i_net <= hblank_i;
hsync_i_net <= hsync_i;
plb_abus_net <= plb_abus;
plb_pavalid_net <= plb_pavalid;
plb_rnw_net <= plb_rnw;
plb_wrdbus_net <= plb_wrdbus;
sg_plb_addrpref_net <= sg_plb_addrpref;
splb_rst_net <= splb_rst;
vblank_i_net <= vblank_i;
video_data_i_net <= video_data_i;
vsync_i_net <= vsync_i;
clkNet_x0 <= xps_clk;
active_video_o <= active_video_o_net;
hblank_o <= hblank_o_net;
hsync_o <= hsync_o_net;
sl_addrack <= sl_addrack_net;
sl_rdcomp <= sl_rdcomp_net;
sl_rddack <= sl_rddack_net;
sl_rddbus <= sl_rddbus_net;
sl_wait <= sl_wait_net;
sl_wrcomp <= sl_wrdack_x2;
sl_wrdack <= sl_wrdack_x1;
vblank_o <= vblank_o_net;
video_data_o <= video_data_o_net;
vsync_o <= vsync_o_net;
default_clock_driver_x0: entity work.default_clock_driver
port map (
sysce => '1',
sysce_clr => '0',
sysclk => clkNet,
ce_1 => ce_1_sg_x0,
clk_1 => clk_1_sg_x0
);
persistentdff_inst: xlpersistentdff
port map (
clk => clkNet,
d => persistentdff_inst_q,
q => persistentdff_inst_q
);
plb_clock_driver_x0: entity work.plb_clock_driver
port map (
sysce => '1',
sysce_clr => '0',
sysclk => clkNet_x0,
plb_ce_1 => plb_ce_1_sg_x1,
plb_clk_1 => plb_clk_1_sg_x1
);
sg_xsvi_fanout_x0: entity work.sg_xsvi_fanout
port map (
active_video_i => active_video_i_net,
ce_1 => ce_1_sg_x0,
clk_1 => clk_1_sg_x0,
hblank_i => hblank_i_net,
hsync_i => hsync_i_net,
plb_abus => plb_abus_net,
plb_ce_1 => plb_ce_1_sg_x1,
plb_clk_1 => plb_clk_1_sg_x1,
plb_pavalid => plb_pavalid_net,
plb_rnw => plb_rnw_net,
plb_wrdbus => plb_wrdbus_net,
sg_plb_addrpref => sg_plb_addrpref_net,
splb_rst => splb_rst_net,
vblank_i => vblank_i_net,
video_data_i => video_data_i_net,
vsync_i => vsync_i_net,
active_video_o => active_video_o_net,
hblank_o => hblank_o_net,
hsync_o => hsync_o_net,
sl_addrack => sl_addrack_net,
sl_rdcomp => sl_rdcomp_net,
sl_rddack => sl_rddack_net,
sl_rddbus => sl_rddbus_net,
sl_wait => sl_wait_net,
sl_wrcomp => sl_wrdack_x2,
sl_wrdack => sl_wrdack_x1,
vblank_o => vblank_o_net,
video_data_o => video_data_o_net,
vsync_o => vsync_o_net
);
end structural;
| gpl-3.0 | 03e3511790301c38aa61f142ee212308 | 0.632154 | 3.454117 | false | false | false | false |
hoglet67/AtomFpga | src/common/RAM/RAM_8K.vhd | 2 | 986 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity RAM_8K is
port (
clk : in std_logic;
we_uP : in std_logic;
ce : in std_logic;
addr_uP : in std_logic_vector (12 downto 0);
D_uP : in std_logic_vector (7 downto 0);
Q_uP : out std_logic_vector (7 downto 0));
end RAM_8K;
architecture BEHAVIORAL of RAM_8K is
type ram_type is array (8191 downto 0) of std_logic_vector (7 downto 0);
signal RAM : ram_type := (8191 downto 0 => X"ff");
attribute RAM_STYLE : string;
attribute RAM_STYLE of RAM : signal is "BLOCK";
begin
process (clk)
begin
if rising_edge(clk) then
if (we_UP = '1' and ce = '1') then
RAM(conv_integer(addr_uP(12 downto 0))) <= D_up;
end if;
Q_up <= RAM(conv_integer(addr_uP(12 downto 0)));
end if;
end process;
end BEHAVIORAL;
| apache-2.0 | 5ab38d4653e19317ff5842b1c9448ab2 | 0.541582 | 3.342373 | false | false | false | false |
tghaefli/ADD | EDK/IVK_Repos/IVK_IPLib/pcores/sg_cfa_gamma_plbw_v1_00_a/hdl/vhdl/sg_cfa_gamma_plbw.vhd | 1 | 9,997 | -------------------------------------------------------------------
-- System Generator version 11.1.00 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2007 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity plbaddrpref is
generic (
C_BASEADDR : std_logic_vector(31 downto 0) := X"80000000";
C_HIGHADDR : std_logic_vector(31 downto 0) := X"8000FFFF";
C_SPLB_DWIDTH : integer range 32 to 128 := 32;
C_SPLB_NATIVE_DWIDTH : integer range 32 to 32 := 32
);
port (
addrpref : out std_logic_vector(20-1 downto 0);
sl_rddbus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
plb_wrdbus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
sgsl_rddbus : in std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH-1);
sgplb_wrdbus : out std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH-1)
);
end plbaddrpref;
architecture behavior of plbaddrpref is
signal sl_rddbus_i : std_logic_vector(0 to C_SPLB_DWIDTH-1);
begin
addrpref <= C_BASEADDR(32-1 downto 12);
-------------------------------------------------------------------------------
-- Mux/Steer data/be's correctly for connect 32-bit slave to 128-bit plb
-------------------------------------------------------------------------------
GEN_128_TO_32_SLAVE : if C_SPLB_NATIVE_DWIDTH = 32 and C_SPLB_DWIDTH = 128 generate
begin
-----------------------------------------------------------------------
-- Map lower rd data to each quarter of the plb slave read bus
-----------------------------------------------------------------------
sl_rddbus_i(0 to 31) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
sl_rddbus_i(32 to 63) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
sl_rddbus_i(64 to 95) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
sl_rddbus_i(96 to 127) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
end generate GEN_128_TO_32_SLAVE;
-------------------------------------------------------------------------------
-- Mux/Steer data/be's correctly for connect 32-bit slave to 64-bit plb
-------------------------------------------------------------------------------
GEN_64_TO_32_SLAVE : if C_SPLB_NATIVE_DWIDTH = 32 and C_SPLB_DWIDTH = 64 generate
begin
---------------------------------------------------------------------------
-- Map lower rd data to upper and lower halves of plb slave read bus
---------------------------------------------------------------------------
sl_rddbus_i(0 to 31) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
sl_rddbus_i(32 to 63) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
end generate GEN_64_TO_32_SLAVE;
-------------------------------------------------------------------------------
-- IPIF DWidth = PLB DWidth
-- If IPIF Slave Data width is equal to the PLB Bus Data Width
-- Then BE and Read Data Bus map directly to eachother.
-------------------------------------------------------------------------------
GEN_FOR_EQUAL_SLAVE : if C_SPLB_NATIVE_DWIDTH = C_SPLB_DWIDTH generate
sl_rddbus_i <= sgsl_rddbus;
end generate GEN_FOR_EQUAL_SLAVE;
sl_rddbus <= sl_rddbus_i;
sgplb_wrdbus <= plb_wrdbus(0 to C_SPLB_NATIVE_DWIDTH-1);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity sg_cfa_gamma_plbw is
generic (
C_BASEADDR: std_logic_vector(31 downto 0) := X"80000000";
C_HIGHADDR: std_logic_vector(31 downto 0) := X"80000FFF";
C_SPLB_AWIDTH: integer := 0;
C_SPLB_DWIDTH: integer := 0;
C_SPLB_MID_WIDTH: integer := 0;
C_SPLB_NATIVE_DWIDTH: integer := 0;
C_SPLB_NUM_MASTERS: integer := 0;
C_SPLB_SUPPORT_BURSTS: integer := 0
);
port (
active_video_i: in std_logic;
hblank_i: in std_logic;
hsync_i: in std_logic;
plb_abus: in std_logic_vector(0 to 31);
plb_pavalid: in std_logic;
plb_rnw: in std_logic;
plb_wrdbus: in std_logic_vector(0 to C_SPLB_DWIDTH-1);
splb_clk: in std_logic;
splb_rst: in std_logic;
sysgen_clk: in std_logic;
vblank_i: in std_logic;
video_data_i: in std_logic_vector(0 to 7);
vsync_i: in std_logic;
active_video_o: out std_logic;
hblank_o: out std_logic;
hsync_o: out std_logic;
sl_addrack: out std_logic;
sl_rdcomp: out std_logic;
sl_rddack: out std_logic;
sl_rddbus: out std_logic_vector(0 to C_SPLB_DWIDTH-1);
sl_wait: out std_logic;
sl_wrcomp: out std_logic;
sl_wrdack: out std_logic;
vblank_o: out std_logic;
video_data_o: out std_logic_vector(0 to 23);
vsync_o: out std_logic
);
end sg_cfa_gamma_plbw;
architecture structural of sg_cfa_gamma_plbw is
signal active_video_i_x0: std_logic;
signal active_video_o_x0: std_logic;
signal clk: std_logic;
signal hblank_i_x0: std_logic;
signal hblank_o_x0: std_logic;
signal hsync_i_x0: std_logic;
signal hsync_o_x0: std_logic;
signal plb_abus_x0: std_logic_vector(31 downto 0);
signal plb_pavalid_x0: std_logic;
signal plb_rnw_x0: std_logic;
signal plbaddrpref_addrpref_net: std_logic_vector(19 downto 0);
signal plbaddrpref_plb_wrdbus_net: std_logic_vector(C_SPLB_DWIDTH-1 downto 0);
signal plbaddrpref_sgplb_wrdbus_net: std_logic_vector(31 downto 0);
signal plbaddrpref_sgsl_rddbus_net: std_logic_vector(31 downto 0);
signal plbaddrpref_sl_rddbus_net: std_logic_vector(C_SPLB_DWIDTH-1 downto 0);
signal sl_addrack_x0: std_logic;
signal sl_rdcomp_x0: std_logic;
signal sl_rddack_x0: std_logic;
signal sl_wait_x0: std_logic;
signal sl_wrcomp_x0: std_logic;
signal sl_wrdack_x0: std_logic;
signal splb_rst_x0: std_logic;
signal vblank_i_x0: std_logic;
signal vblank_o_x0: std_logic;
signal video_data_i_x0: std_logic_vector(7 downto 0);
signal video_data_o_x0: std_logic_vector(23 downto 0);
signal vsync_i_x0: std_logic;
signal vsync_o_x0: std_logic;
signal xps_clk: std_logic;
begin
active_video_i_x0 <= active_video_i;
hblank_i_x0 <= hblank_i;
hsync_i_x0 <= hsync_i;
plb_abus_x0 <= plb_abus;
plb_pavalid_x0 <= plb_pavalid;
plb_rnw_x0 <= plb_rnw;
plbaddrpref_plb_wrdbus_net <= plb_wrdbus;
xps_clk <= splb_clk;
splb_rst_x0 <= splb_rst;
clk <= sysgen_clk;
vblank_i_x0 <= vblank_i;
video_data_i_x0 <= video_data_i;
vsync_i_x0 <= vsync_i;
active_video_o <= active_video_o_x0;
hblank_o <= hblank_o_x0;
hsync_o <= hsync_o_x0;
sl_addrack <= sl_addrack_x0;
sl_rdcomp <= sl_rdcomp_x0;
sl_rddack <= sl_rddack_x0;
sl_rddbus <= plbaddrpref_sl_rddbus_net;
sl_wait <= sl_wait_x0;
sl_wrcomp <= sl_wrcomp_x0;
sl_wrdack <= sl_wrdack_x0;
vblank_o <= vblank_o_x0;
video_data_o <= video_data_o_x0;
vsync_o <= vsync_o_x0;
plbaddrpref_x0: entity work.plbaddrpref
generic map (
C_BASEADDR => C_BASEADDR,
C_HIGHADDR => C_HIGHADDR,
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_SPLB_NATIVE_DWIDTH => C_SPLB_NATIVE_DWIDTH
)
port map (
plb_wrdbus => plbaddrpref_plb_wrdbus_net,
sgsl_rddbus => plbaddrpref_sgsl_rddbus_net,
addrpref => plbaddrpref_addrpref_net,
sgplb_wrdbus => plbaddrpref_sgplb_wrdbus_net,
sl_rddbus => plbaddrpref_sl_rddbus_net
);
sysgen_dut: entity work.sg_cfa_gamma_cw
port map (
active_video_i => active_video_i_x0,
clk => clk,
hblank_i => hblank_i_x0,
hsync_i => hsync_i_x0,
plb_abus => plb_abus_x0,
plb_pavalid => plb_pavalid_x0,
plb_rnw => plb_rnw_x0,
plb_wrdbus => plbaddrpref_sgplb_wrdbus_net,
sg_plb_addrpref => plbaddrpref_addrpref_net,
splb_rst => splb_rst_x0,
vblank_i => vblank_i_x0,
video_data_i => video_data_i_x0,
vsync_i => vsync_i_x0,
xps_clk => xps_clk,
active_video_o => active_video_o_x0,
hblank_o => hblank_o_x0,
hsync_o => hsync_o_x0,
sl_addrack => sl_addrack_x0,
sl_rdcomp => sl_rdcomp_x0,
sl_rddack => sl_rddack_x0,
sl_rddbus => plbaddrpref_sgsl_rddbus_net,
sl_wait => sl_wait_x0,
sl_wrcomp => sl_wrcomp_x0,
sl_wrdack => sl_wrdack_x0,
vblank_o => vblank_o_x0,
video_data_o => video_data_o_x0,
vsync_o => vsync_o_x0
);
end structural;
| gpl-3.0 | 3cd9fd49a79758fc0db82bf5a446d1ef | 0.603181 | 3.323471 | false | false | false | false |
bertuccio/ARQ | Practica3/procesador_TB.vhd | 2 | 5,448 | ---------------------------------------------------------------------------------------------------
--
-- Title : Test Bench for procesador
-- Design : practica_1
-- Author : alumnoeps
-- Company : eps
--
---------------------------------------------------------------------------------------------------
--
-- File : $DSN\src\TestBench\procesador_TB.vhd
-- Generated : 15/03/2006, 15:43
-- From : $DSN\src\procesador.vhd
-- By : Active-HDL Built-in Test Bench Generator ver. 1.2s
--
---------------------------------------------------------------------------------------------------
--
-- Description : Automatically generated Test Bench for procesador_tb
--
---------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Add your library and packages declaration here ...
entity procesador_tb is
end procesador_tb;
architecture TB_ARCHITECTURE of procesador_tb is
-- Component declaration of the tested unit
component procesador
port(
Clk : in std_logic;
Reset : in std_logic;
-- Instruction memory
I_Addr : out std_logic_vector(31 downto 0);
I_RdStb : out std_logic;
I_WrStb : out std_logic;
I_AddrStb : out std_logic;
I_DataOut : out std_logic_vector(31 downto 0);
I_Rdy : in std_logic;
I_DataIn : in std_logic_vector(31 downto 0);
-- Data memory
D_Addr : out std_logic_vector(31 downto 0);
D_RdStb : out std_logic;
D_WrStb : out std_logic;
D_AddrStb : out std_logic;
D_DataOut : out std_logic_vector(31 downto 0);
D_Rdy : in std_logic;
D_DataIn : in std_logic_vector(31 downto 0)
);
end component;
component Memoria
generic (
C_ELF_FILENAME : string;
C_TARGET_SECTION : string;
C_BASE_ADDRESS : integer;
C_MEM_SIZE : integer;
C_WAIT_STATES : integer
);
port (
Clk : in std_logic;
Reset : in std_logic;
Addr : in std_logic_vector(31 downto 0);
AddrStb : in std_logic;
RdStb : in std_logic;
WrStb : in std_logic;
DataIn : in std_logic_vector(31 downto 0);
DataOut : out std_logic_vector(31 downto 0);
Rdy : out std_logic
);
end component;
signal Clk : std_logic;
signal Reset : std_logic;
-- Instruction memory
signal I_Addr : std_logic_vector(31 downto 0);
signal I_RdStb : std_logic;
signal I_WrStb : std_logic;
signal I_AddrStb : std_logic;
signal I_DataOut : std_logic_vector(31 downto 0);
signal I_Rdy : std_logic;
signal I_DataIn : std_logic_vector(31 downto 0);
-- Data memory
signal D_Addr : std_logic_vector(31 downto 0);
signal D_RdStb : std_logic;
signal D_WrStb : std_logic;
signal D_AddrStb : std_logic;
signal D_DataOut : std_logic_vector(31 downto 0);
signal D_Rdy : std_logic;
signal D_DataIn : std_logic_vector(31 downto 0);
constant tper_clk : time := 50 ns;
constant tdelay : time := 100 ns;
begin
-- Unit Under Test port map
UUT : procesador
port map (
Clk => Clk,
Reset => Reset,
-- Instruction memory
I_Addr => I_Addr,
I_RdStb => I_RdStb,
I_WrStb => I_WrStb,
I_AddrStb => I_AddrStb,
I_DataOut => I_DataOut,
I_Rdy => I_Rdy,
I_DataIn => I_DataIn,
-- Data memory
D_Addr => D_Addr,
D_RdStb => D_RdStb,
D_WrStb => D_WrStb,
D_AddrStb => D_AddrStb,
D_DataOut => D_DataOut,
D_Rdy => D_Rdy,
D_DataIn => D_DataIn
);
Inst_Mem_Instr : memoria
generic map (
C_ELF_FILENAME => "programa",
C_TARGET_SECTION => ".text",
C_BASE_ADDRESS => 16#00000000#,
C_MEM_SIZE => 1024,
C_WAIT_STATES => 0
)
port map (
Clk => Clk,
Reset => Reset,
Addr => I_Addr,
AddrStb => I_AddrStb,
RdStb => I_RdStb,
WrStb => I_WrStb,
DataIn => I_DataOut,
DataOut => I_DataIn,
Rdy => I_Rdy
);
Inst_Mem_Datos : memoria
generic map (
C_ELF_FILENAME => "datos",
C_TARGET_SECTION => ".data",
C_BASE_ADDRESS => 16#00000000#,
C_MEM_SIZE => 1024,
C_WAIT_STATES => 0
)
port map(
Clk => Clk,
Reset => Reset,
Addr => D_Addr,
AddrStb => D_AddrStb,
RdStb => D_RdStb,
WrStb => D_WrStb,
DataIn => D_DataOut,
DataOut => D_DataIn,
Rdy => D_Rdy
);
process
begin
Clk <= '0';
wait for tper_clk/2;
Clk <= '1';
wait for tper_clk/2;
end process;
process
begin
Reset <= '1';
wait for tdelay;
Reset <= '0';
wait;
end process;
end TB_ARCHITECTURE;
configuration TESTBENCH_FOR_procesador of procesador_tb is
for TB_ARCHITECTURE
for UUT : procesador
use entity work.procesador(procesador);
end for;
end for;
end TESTBENCH_FOR_procesador;
| mit | 47eabe26dde50ebd9afcc2e0481b622d | 0.489537 | 3.487836 | false | false | false | false |
Alabamajack/Garfield | FPGA_Design/ip_intern/PWM_Generator/pwm_generator_avalon.vhd | 1 | 3,428 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pwm_generator_avalon is
generic(
datawidth : natural := 32;
freq_core : natural := 100_000_000;
freq_pwm : natural := 10_000
);
port(
-- avalon clk interface, there is no need for a reset
clk : in std_logic;
reset : in std_logic;
-- avalon MM interface
address : in std_logic_vector(0 downto 0);
read, write, chipselect : in std_logic;
writedata : in std_logic_vector(datawidth - 1 downto 0);
readdata : out std_logic_vector(datawidth - 1 downto 0);
waitrequest : out std_logic;
-- avalon output interface
pwm_output_signal : out std_logic
);
end entity pwm_generator_avalon;
architecture RTL of pwm_generator_avalon is
----------------------------------------
-- constants
----------------------------------------
constant pwm_generator_bit_width : natural := 8;
----------------------------------------
-- signals
----------------------------------------
signal datavalid_write : boolean := false;
----------------------------------------
-- signals as registers
----------------------------------------
signal control_register : std_logic_vector(datawidth - 1 downto 0);
----------------------------------------
-- components
----------------------------------------
component pwm_generator
generic(
width : natural := 8;
freq_clock : integer := 50000000;
freq_pwm : integer := 1000
);
port(
clk : in std_logic;
pwmvalue : in std_logic_vector(width - 1 downto 0);
pwmout : out std_logic
);
end component pwm_generator;
begin
----------------------------------------
-- component instantiations
----------------------------------------
pwm_gen_inst : pwm_generator
generic map(
width => pwm_generator_bit_width,
freq_clock => freq_core,
freq_pwm => freq_pwm
)
port map(
clk => clk,
pwmvalue(pwm_generator_bit_width -1 downto 0) => control_register(pwm_generator_bit_width - 1 downto 0),
pwmout => pwm_output_signal
);
----------------------------------------
-- concurrent statements
----------------------------------------
waitrequest <= '1' when (write = '1' and chipselect = '1') and not datavalid_write else '0'; -- waitrequest must be asynchron and high until the data are taken
----------------------------------------
-- processes
----------------------------------------
--! @brief
write_proc : process(clk) is
begin
if rising_edge(clk) then
datavalid_write <= false;
if reset = '1' then
control_register <= (others => '0');
elsif chipselect = '1' then
if write = '1' then
case (address) is
when "0" =>
control_register(pwm_generator_bit_width - 1 downto 0) <= writedata(pwm_generator_bit_width - 1 downto 0);
when others =>
null;
end case;
datavalid_write <= true;
end if;
end if;
end if;
end process write_proc;
--! @brief
read_proc : process(chipselect, read, address, control_register) is
begin
if chipselect = '1' and read = '1' then
case address is
when "0" =>
readdata <= control_register;
when others =>
null;
end case;
end if;
end process read_proc;
end architecture RTL;
| gpl-3.0 | 50c8f0e30208d5ddf85bde5ec6c3da26 | 0.502917 | 3.94023 | false | false | false | false |
hoglet67/AtomFpga | src/common/AVR8/resync/rsnc_l_bit.vhd | 4 | 1,624 | --**********************************************************************************************
-- Resynchronizer (for bit) with latch
-- Version 0.1
-- Modified 10.01.2007
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
entity rsnc_l_bit is generic(
tech : integer := 0;
add_stgs_num : integer := 0
);
port(
clk : in std_logic;
di : in std_logic;
do : out std_logic
);
end rsnc_l_bit;
architecture rtl of rsnc_l_bit is
type rsnc_vect_type is array(add_stgs_num+1 downto 0) of std_logic;
signal rsnc_rg_current : rsnc_vect_type;
signal rsnc_rg_next : rsnc_vect_type;
begin
-- Latch
latch_prc:process(clk)
begin
if(clk='0') then -- Clock (falling edge)
rsnc_rg_current(rsnc_rg_current'low) <= rsnc_rg_next(rsnc_rg_next'low);
end if;
end process;
-- Latch
seq_re_prc:process(clk)
begin
if(clk='1' and clk'event) then -- Clock (rising edge)
rsnc_rg_current(rsnc_rg_current'high downto rsnc_rg_current'low+1) <= rsnc_rg_next(rsnc_rg_current'high downto rsnc_rg_current'low+1);
end if;
end process;
comb_prc:process(di,rsnc_rg_current)
begin
rsnc_rg_next(0) <= di;
for i in 1 to rsnc_rg_next'high loop
rsnc_rg_next(i) <= rsnc_rg_current(i-1);
end loop;
end process;
do <= rsnc_rg_current(rsnc_rg_current'high);
end rtl;
| apache-2.0 | cf3b7644df38499fd2934e1d981f5e31 | 0.503695 | 3.19057 | false | false | false | false |
hoglet67/AtomFpga | src/xilinx/DCM/dcm4.vhd | 1 | 2,350 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity dcm4 is
port (CLKIN_IN : in std_logic;
CLK0_OUT : out std_logic;
CLKFX_OUT : out std_logic);
end dcm4;
architecture BEHAVIORAL of dcm4 is
signal GND_BIT : std_logic;
signal CLKIN : std_logic;
signal CLKFX : std_logic;
signal CLKFX_BUF : std_logic;
signal CLK0 : std_logic;
signal CLK0_BUF : std_logic;
signal CLKFB : std_logic;
begin
GND_BIT <= '0';
-- CLK0 output buffer
CLK0_BUFG_INST : BUFG
port map (I => CLK0, O => CLK0_BUF);
CLK0_OUT <= CLK0_BUF;
-- CLKFX output buffer
CLKFX_BUFG_INST : BUFG
port map (I => CLKFX, O => CLKFX_BUF);
CLKFX_OUT <= CLKFX_BUF;
DCM_INST : DCM
generic map(CLK_FEEDBACK => "1X",
CLKDV_DIVIDE => 4.0, -- 25.175 = 32 * 11/14
CLKFX_DIVIDE => 14,
CLKFX_MULTIPLY => 11,
CLKIN_DIVIDE_BY_2 => false,
CLKIN_PERIOD => 31.250,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => true,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => false)
port map (CLKFB => CLK0_BUF,
CLKIN => CLKIN_IN,
DSSEN => GND_BIT,
PSCLK => GND_BIT,
PSEN => GND_BIT,
PSINCDEC => GND_BIT,
RST => GND_BIT,
CLKDV => open,
CLKFX => CLKFX,
CLKFX180 => open,
CLK0 => CLK0,
CLK2X => open,
CLK2X180 => open,
CLK90 => open,
CLK180 => open,
CLK270 => open,
LOCKED => open,
PSDONE => open,
STATUS => open);
end BEHAVIORAL;
| apache-2.0 | 4206cadc49aeae632c56d5c63a6231d4 | 0.414043 | 4.226619 | false | false | false | false |
bertuccio/ARQ | Practica5/procesador.vhd | 1 | 13,999 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity procesador is
port(
Clk : in std_logic;
Reset : in std_logic;
-- Instruction memory
I_Addr : out std_logic_vector(31 downto 0);
I_RdStb : out std_logic;
I_WrStb : out std_logic;
I_AddrStb : out std_logic;
I_DataOut : out std_logic_vector(31 downto 0);
I_Rdy : in std_logic;
I_DataIn : in std_logic_vector(31 downto 0);
-- Data memory
D_Addr : out std_logic_vector(31 downto 0);
D_RdStb : out std_logic;
D_WrStb : out std_logic;
D_AddrStb : out std_logic;
D_DataOut : out std_logic_vector(31 downto 0);
D_Rdy : in std_logic;
D_DataIn : in std_logic_vector(31 downto 0)
);
end procesador;
architecture procesador_arq of procesador is
------------------------
------COMPONENTES-------
------------------------
component tabla_registros PORT
( CLK : in STD_LOGIC;
Reset : in STD_LOGIC;
EscrReg : in STD_LOGIC;
reg_lec1 : in STD_LOGIC_VECTOR (4 downto 0);
reg_lec2 : in STD_LOGIC_VECTOR (4 downto 0);
reg_escr: in STD_LOGIC_VECTOR (4 downto 0);
dato_escr : in STD_LOGIC_VECTOR (31 downto 0);
dato_leido1 : out STD_LOGIC_VECTOR (31 downto 0);
dato_leido2 : out STD_LOGIC_VECTOR (31 downto 0));
end component;
component ALU PORT
( A : in STD_LOGIC_VECTOR (31 downto 0);
B : in STD_LOGIC_VECTOR (31 downto 0);
control : in STD_LOGIC_VECTOR (3 downto 0);
resultado : out STD_LOGIC_VECTOR (31 downto 0);
igual : out STD_LOGIC);
end component;
component ForwardingUnit Port
( ID_EX_RS : in STD_LOGIC_VECTOR (4 downto 0);
ID_EX_RT : in STD_LOGIC_VECTOR (4 downto 0);
EX_MEM_ESCREG : in STD_LOGIC;
MEM_WB_ESCREG : in STD_LOGIC;
EX_MEM_RD : in STD_LOGIC_VECTOR (4 downto 0);
MEM_WB_RD : in STD_LOGIC_VECTOR (4 downto 0);
AnticipaA : out STD_LOGIC_VECTOR (1 downto 0);
AnticipaB : out STD_LOGIC_VECTOR (1 downto 0));
end component;
component HAZARD
Port ( PC_Write : out STD_LOGIC;
IFID_Write : out STD_LOGIC;
IDEX_Memread : in STD_LOGIC;
MUX_sel : out STD_LOGIC;
IDEX_Rt : in STD_LOGIC_VECTOR (4 downto 0);
IFID_Rs : in STD_LOGIC_VECTOR (4 downto 0);
IFID_Rt : in STD_LOGIC_VECTOR (4 downto 0));
end component;
------------------
-----SEÑALES------
------------------
signal PC_IN : STD_LOGIC_VECTOR (31 downto 0);
signal PC_IN1 : STD_LOGIC_VECTOR (31 downto 0);
signal addResultIN : STD_LOGIC_VECTOR (31 downto 0);
signal addResultOUT : STD_LOGIC_VECTOR (31 downto 0);
signal MemMux1 : STD_LOGIC_VECTOR (31 downto 0);
signal MemMux2 : STD_LOGIC_VECTOR (31 downto 0);
-------ALU-----------------------------------------
signal OpA : STD_LOGIC_VECTOR (31 downto 0);
signal OpAPosible : STD_LOGIC_VECTOR (31 downto 0);
signal OpB : STD_LOGIC_VECTOR (31 downto 0);
signal mux1OpB: STD_LOGIC_VECTOR (31 downto 0);
signal mux1OpBPosible : STD_LOGIC_VECTOR (31 downto 0);
signal mux2OpB: STD_LOGIC_VECTOR (31 downto 0);
signal AluControl : STD_LOGIC_VECTOR (5 downto 0);
signal ALUctr : STD_LOGIC_VECTOR (3 downto 0);
signal Zero : STD_LOGIC;
signal AluResultIN : STD_LOGIC_VECTOR (31 downto 0);
signal AluResultOUT : STD_LOGIC_VECTOR (31 downto 0);
---------------------------------------------------
--------------CONTROL----------------------------
signal Control: STD_LOGIC_VECTOR (5 downto 0);
------EX------------
signal EXctr : std_logic_vector(3 downto 0);
signal EXHAZARD : std_logic_vector(3 downto 0);
signal RegDst: STD_LOGIC;
signal ALUOp: STD_LOGIC_VECTOR (1 downto 0);
signal AluSrc : STD_LOGIC;
-------M------------
signal Mctr : std_logic_vector(2 downto 0);
signal MHAZARD : std_logic_vector(2 downto 0);
signal Mctr1 : std_logic_vector(2 downto 0);
signal Mctr2 : std_logic_vector(2 downto 0);
signal PCSrc : STD_LOGIC;
------WB------------
signal WEctr : std_logic_vector(1 downto 0);
signal WEHAZARD : std_logic_vector(1 downto 0);
signal WEctr1 : std_logic_vector(1 downto 0);
signal WEctr2 : std_logic_vector(1 downto 0);
signal EscrReg : STD_LOGIC;
signal MemToReg : STD_LOGIC;
---------------------------------------------------
signal signo_extend: STD_LOGIC_VECTOR (31 downto 0);
signal reg_lect1IF : STD_LOGIC_VECTOR (4 downto 0);
signal reg_lect2IF : STD_LOGIC_VECTOR (4 downto 0);
signal rdInstCarg : STD_LOGIC_VECTOR (4 downto 0);
signal rdInstALU : STD_LOGIC_VECTOR (4 downto 0);
signal reg_escr: STD_LOGIC_VECTOR (4 downto 0);
signal reg_escrIN: STD_LOGIC_VECTOR (4 downto 0);
signal dato_leido1 : STD_LOGIC_VECTOR (31 downto 0);
signal dato_leido2 : STD_LOGIC_VECTOR (31 downto 0);
signal dato_escr : STD_LOGIC_VECTOR (31 downto 0);
signal RegEscribir1 : STD_LOGIC_VECTOR (4 downto 0);
signal RegEscribir2 : STD_LOGIC_VECTOR (4 downto 0);
signal mux_aux1 : STD_LOGIC_VECTOR (4 downto 0);
signal mux_aux2 : STD_LOGIC_VECTOR (4 downto 0);
---------FORWARDINGUNIT-----------
signal ID_EX_RS : STD_LOGIC_VECTOR (4 downto 0);
signal ID_EX_RT : STD_LOGIC_VECTOR (4 downto 0);
signal EX_MEM_ESCREG : STD_LOGIC;
signal MEM_WB_ESCREG : STD_LOGIC;
signal EX_MEM_RD : STD_LOGIC_VECTOR (4 downto 0);
signal MEM_WB_RD : STD_LOGIC_VECTOR (4 downto 0);
signal AnticipaA : STD_LOGIC_VECTOR (1 downto 0);
signal AnticipaB : STD_LOGIC_VECTOR (1 downto 0);
signal MUXPC_OUT: STD_LOGIC_VECTOR (31 downto 0);
signal PC_OUT: STD_LOGIC_VECTOR (31 downto 0);
signal Add4_OUT: STD_LOGIC_VECTOR (31 downto 0);
signal PC_Write : STD_LOGIC;
signal IFID_Write : STD_LOGIC;
signal IDEX_Memread : STD_LOGIC;
signal MUX_sel : STD_LOGIC;
signal IDEX_Rt : STD_LOGIC_VECTOR (4 downto 0);
signal IFID_Rs : STD_LOGIC_VECTOR (4 downto 0);
signal IFID_Rt : STD_LOGIC_VECTOR (4 downto 0);
begin
-----------------
----PORT-MAPS----
-----------------
--BANCO REGISTROS--
BANCO: tabla_registros port map(
CLK => Clk,
Reset => Reset,
EscrReg => EscrReg,
reg_lec1 => reg_lect1IF,
reg_lec2 => reg_lect2IF,
reg_escr => reg_escr,
dato_escr => dato_escr,
dato_leido1 => dato_leido1,
dato_leido2 => dato_leido2);
--ALU--
UAL : ALU port map(
A => OpA,
B => OpB,
control => ALUctr,
resultado => AluResultIN,
igual => Zero);
UnitForward: ForwardingUnit port map(
ID_EX_RS =>ID_EX_RS,
ID_EX_RT =>ID_EX_RT,
EX_MEM_ESCREG => EX_MEM_ESCREG,
MEM_WB_ESCREG =>MEM_WB_ESCREG,
EX_MEM_RD => EX_MEM_RD,
MEM_WB_RD => MEM_WB_RD,
AnticipaA => AnticipaA,
AnticipaB => AnticipaB);
HazardUnit: HAZARD port map(
PC_Write=>PC_Write,
IFID_Write=> IFID_Write,
IDEX_Memread=>IDEX_Memread,
MUX_sel=>MUX_sel,
IDEX_Rt=>IDEX_Rt,
IFID_Rs=>IFID_Rs,
IFID_Rt=>IFID_Rt);
I_RdStb<='1';
I_WrStb<='0';
I_AddrStb<='1';
D_AddrStb<='1';
I_DataOut<=x"00000000";
------------------------------
----CONTADOR DE PROGRAMA------
------------------------------
process(Clk,Reset)
begin
if Reset='1' then
PC_OUT<=x"00000000";
elsif rising_edge(Clk) then
if PC_Write='1' then
PC_OUT<=PC_IN;
end if;
end if;
end process;
-- Entrada del registro PC.
PC_IN <= MUXPC_OUT;
MUXPC_OUT <= addResultOUT when PCSrc='1' else Add4_OUT;
-- Salida del registro PC.
I_Addr <= PC_OUT;
Add4_OUT <= PC_OUT + 4;
-----------------------
---PRIMER PIPE (IF)----
-----------------------
process (Clk,Reset)
begin
if (Reset='1') then
PC_IN1<=x"00000000";
Control<= "000000";
reg_lect1IF<="00000";
reg_lect2IF<="00000";
rdInstCarg<= "00000";
rdInstALU<= "00000";
signo_extend<=x"00000000";
else
if rising_edge(Clk) then
if(PcSrc='1') then
PC_IN1<=x"00000000";
Control<= "000000";
reg_lect1IF<="00000";
reg_lect2IF<="00000";
rdInstCarg<= "00000";
rdInstALU<= "00000";
signo_extend<=x"00000000";
else if (IFID_Write='1') then
PC_IN1<=Add4_OUT;
Control <= I_DataIn(31 downto 26);
reg_lect1IF <=I_DataIn(25 downto 21);
reg_lect2IF <=I_DataIn(20 downto 16);
rdInstCarg <= I_DataIn(20 downto 16);
rdInstALU <= I_DataIn(15 downto 11);
if I_DataIn(15)='1' then
signo_extend<=x"FFFF"&I_DataIn(15 downto 0);
else
signo_extend<=x"0000"&I_DataIn(15 downto 0);
end if;
else
end if;
end if;
end if;
end if;
end process;
IFID_Rs<=reg_lect1IF;
IFID_Rt<=reg_lect2IF;
IDEX_Rt<=mux_aux1;
IDEX_Memread<=Mctr1(1);
-----------------------
---SEGUNDO PIPE (EX)--
-----------------------
process (Clk,Reset)
begin
if (Reset='1') then
WEctr1<="00";
Mctr1<="000";
ALUOp<="00";
ALUcontrol<="000000";
OpAPosible<=x"00000000";
mux1OpBPosible<=x"00000000";
mux2OpB<=x"00000000";
mux_aux1<="00000";
mux_aux2<="00000";
addResultIN<=x"00000000";
AluSrc<='0';
RegDst<='0';
ID_EX_RS<="00000";
ID_EX_RT<="00000";
else
if rising_edge(Clk) then
if (PcSrc='1') then
WEctr1<="00";
Mctr1<="000";
ALUOp<="00";
ALUcontrol<="000000";
OpAPosible<=x"00000000";
mux1OpBPosible<=x"00000000";
mux2OpB<=x"00000000";
mux_aux1<="00000";
mux_aux2<="00000";
addResultIN<=x"00000000";
AluSrc<='0';
RegDst<='0';
ID_EX_RS<="00000";
ID_EX_RT<="00000";
else
WEctr1<=WEctr;
Mctr1<=Mctr;
ALUcontrol<=signo_extend(5 downto 0);
mux2OpB<=signo_extend;
addResultIN<=signo_extend(29 downto 0)&"00"+PC_IN1;
OpAPosible<=dato_leido1;
mux1OpBPosible<=dato_leido2;
mux_aux1<=rdInstCarg;
mux_aux2<=rdInstALU;
RegDst<=EXctr(3);
ALUOp<=EXctr(2 downto 1);
AluSrc<=EXctr(0);
ID_EX_RS<=reg_lect1IF;
ID_EX_RT<=reg_lect2IF;
end if;
end if;
end if;
end process;
----------MULTIPLEXORES--------------
WITH AluSrc SELECT
OpB <=mux1OpB WHEN '0',
mux2OpB WHEN OTHERS;
WITH RegDst SELECT
regEscribir1 <=mux_aux1 WHEN '0',
mux_aux2 WHEN OTHERS;
WITH MemToReg SELECT
dato_escr <=MemMux2 WHEN '0',
MemMux1 WHEN OTHERS;
------------------------------------
--MULTIPLEXOR PARA ELEGIR LA ENTRADA A LA ALU DEL OPERANDO A
process (OpAPosible, AnticipaA, dato_escr, aluResultOUT)
begin
if( AnticipaA= "00" )then
OpA <= OpAPosible;
elsif( AnticipaA="01" ) then
OpA <= dato_escr;
elsif( AnticipaA="10" ) then
OpA <= aluResultOUT;--when AnticipaA="10"
end if;
end process;
--MULTIPLEXOR PARA ELEGIR LA ENTRADA POSIBLE DEL OPERANDO B
process (mux1OpBPosible, AnticipaB, dato_escr, aluResultOUT)
begin
if( AnticipaB= "00" )then
mux1OpB <= mux1OpBPosible;
elsif( AnticipaB="01" ) then
mux1OpB <= dato_escr;
elsif( AnticipaB="10" ) then
mux1OpB <= aluResultOUT;
end if;
end process;
-----------------------
---TERCER PIPE (MEM)--
-----------------------
process (Clk,Reset)
begin
if (Reset='1') then
addResultOUT<=x"00000000";
D_WrStb<='0';--memwrite
D_RdStb<='0';--memread
PCSrc<='0';
D_DataOut<=x"00000000";
aluResultOUT<=x"00000000";
WEctr2<="00";
regEscribir2<="00000";
D_Addr<=x"00000000";
EX_MEM_ESCREG<='0';
EX_MEM_RD<="00000";
else
if rising_edge(Clk) then
if (PcSrc='1') then
addResultOUT<=x"00000000";
D_WrStb<='0';--memwrite
D_RdStb<='0';--memread
PCSrc<='0';
D_DataOut<=x"00000000";
aluResultOUT<=x"00000000";
WEctr2<="00";
regEscribir2<="00000";
D_Addr<=x"00000000";
EX_MEM_ESCREG<='0';
EX_MEM_RD<="00000";
else
WEctr2<=WEctr1;
addResultOUT<=addResultIN;
D_WrStb<=Mctr1(0);--memwrite
D_RdStb<=Mctr1(1);--memread
PCSrc<=Mctr1(2) and Zero;
EX_MEM_RD<=regEscribir1;
D_Addr<=AluResultIN;
aluResultOUT<=AluResultIN;
D_DataOut<=mux1OpB;
regEscribir2<=regEscribir1;
EX_MEM_ESCREG<=WEctr1(1);
end if;
end if;
end if;
end process;
-------------------
----REGISTRO 4-----
-------------------
process (Clk,Reset) begin
if (Reset='1') then
MemMux1<=x"00000000";
MemMux2<=x"00000000";
reg_escr<="00000";
MemToReg<='0';
EscrReg<='0';
MEM_WB_ESCREG<='0';
else
if rising_edge(Clk) then
MemMux1<=D_DataIn;
MemMux2<=aluResultOUT;
reg_escr<=regEscribir2;
MemToReg<=WEctr2(0);
EscrReg<=WEctr2(1);
MEM_WB_ESCREG<=WEctr2(1);
MEM_WB_RD<=regEscribir2;
end if;
end if;
end process;
process (ALUOp, ALUcontrol) begin
case ALUOp is
when "10"=>--REG_A_REG
case ALUcontrol is
when "100000"=>--ADD
ALUctr<="0011";
when "100010"=>--SUB
ALUctr<="1000";
when "100100"=>--AND
ALUctr<="0000";
when "100101"=>--OR
ALUctr<="0001";
when "100110"=>--XOR
ALUctr<="0010";
when "101010"=>--SLT
ALUctr<="1010";
when others =>
ALUctr<="1111";
end case;
when "00"=>--LW ó SW
ALUctr<="0011";--ADD PARA CONSEGUIR LA DIRECCION DE MEMORIA
when "01"=>--BEQ
ALUctr<="0010";--XOR PARA VER SI RS Y RT SON IGUALES
when "11"=>--LIU
ALUctr<="1001";
when others =>
ALUctr<="1111";
end case;
end process;
process (Control) begin
case Control is
when "000000"=> --SPECIAL (R)
EXHAZARD<="1100";
MHAZARD<="000";
WEHAZARD<="10";
when "100011"=> --LW
EXHAZARD<="0001";
MHAZARD<="010";
WEHAZARD<="11";
when "101011"=> --SW
EXHAZARD<="0001";
MHAZARD<="001";
WEHAZARD<="00";
when "001111"=> --LIU
EXHAZARD<="0110";
MHAZARD<="000";
WEHAZARD<="10";
when "000100"=> --BE
EXHAZARD<="0010";
MHAZARD<="100";
WEHAZARD<="00";
when others =>
EXHAZARD<="0000";
MHAZARD<="000";
WEHAZARD<="00";
end case;
end process;
process (MUX_Sel, WEHAZARD,MHAZARD,EXHAZARD)
begin
if MUX_Sel='1' then
WEctr<="00";
Mctr<="000";
EXctr<="0000";
elsif MUX_Sel='0' then
WEctr<=WEHAZARD;
Mctr<=MHAZARD;
EXctr<=EXHAZARD;
end if;
end process;
end procesador_arq;
| mit | 773ecc3b9297d5fe91c34228262f659e | 0.591257 | 2.906166 | false | false | false | false |
hoglet67/AtomFpga | src/common/ROM/basic.vhd | 2 | 172,738 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity atombasic is
port (
CLK : in std_logic;
ADDR : in std_logic_vector(11 downto 0);
DATA : out std_logic_vector(7 downto 0)
);
end;
architecture RTL of atombasic is
signal rom_addr : std_logic_vector(11 downto 0);
begin
p_addr : process(ADDR)
begin
rom_addr <= (others => '0');
rom_addr(11 downto 0) <= ADDR;
end process;
p_rom : process
begin
wait until rising_edge(CLK);
DATA <= (others => '0');
case rom_addr is
when x"000" => DATA <= x"3C";
when x"001" => DATA <= x"3D";
when x"002" => DATA <= x"3E";
when x"003" => DATA <= x"FE";
when x"004" => DATA <= x"2D";
when x"005" => DATA <= x"2B";
when x"006" => DATA <= x"C8";
when x"007" => DATA <= x"23";
when x"008" => DATA <= x"28";
when x"009" => DATA <= x"21";
when x"00A" => DATA <= x"3F";
when x"00B" => DATA <= x"52";
when x"00C" => DATA <= x"54";
when x"00D" => DATA <= x"4C";
when x"00E" => DATA <= x"43";
when x"00F" => DATA <= x"41";
when x"010" => DATA <= x"50";
when x"011" => DATA <= x"45";
when x"012" => DATA <= x"47";
when x"013" => DATA <= x"42";
when x"014" => DATA <= x"46";
when x"015" => DATA <= x"F0";
when x"016" => DATA <= x"54";
when x"017" => DATA <= x"FF";
when x"018" => DATA <= x"4F";
when x"019" => DATA <= x"CB";
when x"01A" => DATA <= x"53";
when x"01B" => DATA <= x"CB";
when x"01C" => DATA <= x"54";
when x"01D" => DATA <= x"45";
when x"01E" => DATA <= x"50";
when x"01F" => DATA <= x"CB";
when x"020" => DATA <= x"54";
when x"021" => DATA <= x"C3";
when x"022" => DATA <= x"48";
when x"023" => DATA <= x"45";
when x"024" => DATA <= x"4E";
when x"025" => DATA <= x"C3";
when x"026" => DATA <= x"22";
when x"027" => DATA <= x"24";
when x"028" => DATA <= x"CE";
when x"029" => DATA <= x"CE";
when x"02A" => DATA <= x"CC";
when x"02B" => DATA <= x"24";
when x"02C" => DATA <= x"2C";
when x"02D" => DATA <= x"C5";
when x"02E" => DATA <= x"24";
when x"02F" => DATA <= x"26";
when x"030" => DATA <= x"3B";
when x"031" => DATA <= x"0D";
when x"032" => DATA <= x"2C";
when x"033" => DATA <= x"C3";
when x"034" => DATA <= x"C5";
when x"035" => DATA <= x"C2";
when x"036" => DATA <= x"3E";
when x"037" => DATA <= x"C7";
when x"038" => DATA <= x"3D";
when x"039" => DATA <= x"C7";
when x"03A" => DATA <= x"C7";
when x"03B" => DATA <= x"C7";
when x"03C" => DATA <= x"3D";
when x"03D" => DATA <= x"C7";
when x"03E" => DATA <= x"C7";
when x"03F" => DATA <= x"C8";
when x"040" => DATA <= x"52";
when x"041" => DATA <= x"C7";
when x"042" => DATA <= x"C7";
when x"043" => DATA <= x"4F";
when x"044" => DATA <= x"41";
when x"045" => DATA <= x"FE";
when x"046" => DATA <= x"24";
when x"047" => DATA <= x"C7";
when x"048" => DATA <= x"48";
when x"049" => DATA <= x"C9";
when x"04A" => DATA <= x"45";
when x"04B" => DATA <= x"4E";
when x"04C" => DATA <= x"C9";
when x"04D" => DATA <= x"4E";
when x"04E" => DATA <= x"44";
when x"04F" => DATA <= x"C7";
when x"050" => DATA <= x"C9";
when x"051" => DATA <= x"C9";
when x"052" => DATA <= x"C9";
when x"053" => DATA <= x"C9";
when x"054" => DATA <= x"4E";
when x"055" => DATA <= x"44";
when x"056" => DATA <= x"C9";
when x"057" => DATA <= x"4F";
when x"058" => DATA <= x"50";
when x"059" => DATA <= x"C9";
when x"05A" => DATA <= x"4F";
when x"05B" => DATA <= x"55";
when x"05C" => DATA <= x"4E";
when x"05D" => DATA <= x"54";
when x"05E" => DATA <= x"C9";
when x"05F" => DATA <= x"42";
when x"060" => DATA <= x"53";
when x"061" => DATA <= x"C9";
when x"062" => DATA <= x"54";
when x"063" => DATA <= x"52";
when x"064" => DATA <= x"CF";
when x"065" => DATA <= x"58";
when x"066" => DATA <= x"54";
when x"067" => DATA <= x"CF";
when x"068" => DATA <= x"45";
when x"069" => DATA <= x"54";
when x"06A" => DATA <= x"CF";
when x"06B" => DATA <= x"47";
when x"06C" => DATA <= x"45";
when x"06D" => DATA <= x"54";
when x"06E" => DATA <= x"CF";
when x"06F" => DATA <= x"49";
when x"070" => DATA <= x"4E";
when x"071" => DATA <= x"CF";
when x"072" => DATA <= x"4F";
when x"073" => DATA <= x"55";
when x"074" => DATA <= x"54";
when x"075" => DATA <= x"CF";
when x"076" => DATA <= x"C3";
when x"077" => DATA <= x"C3";
when x"078" => DATA <= x"52";
when x"079" => DATA <= x"49";
when x"07A" => DATA <= x"4E";
when x"07B" => DATA <= x"54";
when x"07C" => DATA <= x"C3";
when x"07D" => DATA <= x"4E";
when x"07E" => DATA <= x"4C";
when x"07F" => DATA <= x"55";
when x"080" => DATA <= x"4E";
when x"081" => DATA <= x"49";
when x"082" => DATA <= x"47";
when x"083" => DATA <= x"52";
when x"084" => DATA <= x"46";
when x"085" => DATA <= x"21";
when x"086" => DATA <= x"3F";
when x"087" => DATA <= x"24";
when x"088" => DATA <= x"50";
when x"089" => DATA <= x"44";
when x"08A" => DATA <= x"4C";
when x"08B" => DATA <= x"53";
when x"08C" => DATA <= x"42";
when x"08D" => DATA <= x"2A";
when x"08E" => DATA <= x"45";
when x"08F" => DATA <= x"F0";
when x"090" => DATA <= x"41";
when x"091" => DATA <= x"56";
when x"092" => DATA <= x"45";
when x"093" => DATA <= x"CF";
when x"094" => DATA <= x"45";
when x"095" => DATA <= x"57";
when x"096" => DATA <= x"C2";
when x"097" => DATA <= x"4F";
when x"098" => DATA <= x"CC";
when x"099" => DATA <= x"45";
when x"09A" => DATA <= x"54";
when x"09B" => DATA <= x"C3";
when x"09C" => DATA <= x"49";
when x"09D" => DATA <= x"4E";
when x"09E" => DATA <= x"4B";
when x"09F" => DATA <= x"C3";
when x"0A0" => DATA <= x"49";
when x"0A1" => DATA <= x"53";
when x"0A2" => DATA <= x"54";
when x"0A3" => DATA <= x"CA";
when x"0A4" => DATA <= x"4F";
when x"0A5" => DATA <= x"41";
when x"0A6" => DATA <= x"44";
when x"0A7" => DATA <= x"CE";
when x"0A8" => DATA <= x"4E";
when x"0A9" => DATA <= x"54";
when x"0AA" => DATA <= x"49";
when x"0AB" => DATA <= x"4C";
when x"0AC" => DATA <= x"CC";
when x"0AD" => DATA <= x"45";
when x"0AE" => DATA <= x"58";
when x"0AF" => DATA <= x"54";
when x"0B0" => DATA <= x"CA";
when x"0B1" => DATA <= x"46";
when x"0B2" => DATA <= x"C5";
when x"0B3" => DATA <= x"4E";
when x"0B4" => DATA <= x"50";
when x"0B5" => DATA <= x"55";
when x"0B6" => DATA <= x"54";
when x"0B7" => DATA <= x"CC";
when x"0B8" => DATA <= x"4F";
when x"0B9" => DATA <= x"53";
when x"0BA" => DATA <= x"55";
when x"0BB" => DATA <= x"42";
when x"0BC" => DATA <= x"CB";
when x"0BD" => DATA <= x"4F";
when x"0BE" => DATA <= x"54";
when x"0BF" => DATA <= x"4F";
when x"0C0" => DATA <= x"CC";
when x"0C1" => DATA <= x"45";
when x"0C2" => DATA <= x"54";
when x"0C3" => DATA <= x"55";
when x"0C4" => DATA <= x"52";
when x"0C5" => DATA <= x"4E";
when x"0C6" => DATA <= x"CB";
when x"0C7" => DATA <= x"45";
when x"0C8" => DATA <= x"4D";
when x"0C9" => DATA <= x"C5";
when x"0CA" => DATA <= x"55";
when x"0CB" => DATA <= x"4E";
when x"0CC" => DATA <= x"F1";
when x"0CD" => DATA <= x"4F";
when x"0CE" => DATA <= x"52";
when x"0CF" => DATA <= x"CB";
when x"0D0" => DATA <= x"4E";
when x"0D1" => DATA <= x"44";
when x"0D2" => DATA <= x"CD";
when x"0D3" => DATA <= x"47";
when x"0D4" => DATA <= x"45";
when x"0D5" => DATA <= x"54";
when x"0D6" => DATA <= x"CF";
when x"0D7" => DATA <= x"50";
when x"0D8" => DATA <= x"55";
when x"0D9" => DATA <= x"54";
when x"0DA" => DATA <= x"CF";
when x"0DB" => DATA <= x"48";
when x"0DC" => DATA <= x"55";
when x"0DD" => DATA <= x"54";
when x"0DE" => DATA <= x"CF";
when x"0DF" => DATA <= x"50";
when x"0E0" => DATA <= x"55";
when x"0E1" => DATA <= x"54";
when x"0E2" => DATA <= x"CF";
when x"0E3" => DATA <= x"54";
when x"0E4" => DATA <= x"52";
when x"0E5" => DATA <= x"CF";
when x"0E6" => DATA <= x"55";
when x"0E7" => DATA <= x"54";
when x"0E8" => DATA <= x"CF";
when x"0E9" => DATA <= x"C3";
when x"0EA" => DATA <= x"C4";
when x"0EB" => DATA <= x"CD";
when x"0EC" => DATA <= x"C4";
when x"0ED" => DATA <= x"2C";
when x"0EE" => DATA <= x"FE";
when x"0EF" => DATA <= x"36";
when x"0F0" => DATA <= x"3B";
when x"0F1" => DATA <= x"3C";
when x"0F2" => DATA <= x"C0";
when x"0F3" => DATA <= x"3F";
when x"0F4" => DATA <= x"06";
when x"0F5" => DATA <= x"DC";
when x"0F6" => DATA <= x"50";
when x"0F7" => DATA <= x"51";
when x"0F8" => DATA <= x"52";
when x"0F9" => DATA <= x"53";
when x"0FA" => DATA <= x"54";
when x"0FB" => DATA <= x"57";
when x"0FC" => DATA <= x"4A";
when x"0FD" => DATA <= x"5A";
when x"0FE" => DATA <= x"5F";
when x"0FF" => DATA <= x"62";
when x"100" => DATA <= x"65";
when x"101" => DATA <= x"68";
when x"102" => DATA <= x"6B";
when x"103" => DATA <= x"6F";
when x"104" => DATA <= x"2E";
when x"105" => DATA <= x"18";
when x"106" => DATA <= x"AC";
when x"107" => DATA <= x"17";
when x"108" => DATA <= x"81";
when x"109" => DATA <= x"1C";
when x"10A" => DATA <= x"BE";
when x"10B" => DATA <= x"17";
when x"10C" => DATA <= x"17";
when x"10D" => DATA <= x"17";
when x"10E" => DATA <= x"A2";
when x"10F" => DATA <= x"22";
when x"110" => DATA <= x"1B";
when x"111" => DATA <= x"17";
when x"112" => DATA <= x"17";
when x"113" => DATA <= x"17";
when x"114" => DATA <= x"1B";
when x"115" => DATA <= x"29";
when x"116" => DATA <= x"28";
when x"117" => DATA <= x"B6";
when x"118" => DATA <= x"BF";
when x"119" => DATA <= x"B6";
when x"11A" => DATA <= x"2A";
when x"11B" => DATA <= x"B7";
when x"11C" => DATA <= x"58";
when x"11D" => DATA <= x"76";
when x"11E" => DATA <= x"77";
when x"11F" => DATA <= x"34";
when x"120" => DATA <= x"34";
when x"121" => DATA <= x"7C";
when x"122" => DATA <= x"3F";
when x"123" => DATA <= x"4A";
when x"124" => DATA <= x"78";
when x"125" => DATA <= x"38";
when x"126" => DATA <= x"6D";
when x"127" => DATA <= x"3A";
when x"128" => DATA <= x"64";
when x"129" => DATA <= x"74";
when x"12A" => DATA <= x"5B";
when x"12B" => DATA <= x"3E";
when x"12C" => DATA <= x"7B";
when x"12D" => DATA <= x"82";
when x"12E" => DATA <= x"C1";
when x"12F" => DATA <= x"45";
when x"130" => DATA <= x"22";
when x"131" => DATA <= x"31";
when x"132" => DATA <= x"40";
when x"133" => DATA <= x"4D";
when x"134" => DATA <= x"4D";
when x"135" => DATA <= x"42";
when x"136" => DATA <= x"53";
when x"137" => DATA <= x"15";
when x"138" => DATA <= x"D2";
when x"139" => DATA <= x"15";
when x"13A" => DATA <= x"15";
when x"13B" => DATA <= x"BD";
when x"13C" => DATA <= x"45";
when x"13D" => DATA <= x"45";
when x"13E" => DATA <= x"14";
when x"13F" => DATA <= x"0A";
when x"140" => DATA <= x"44";
when x"141" => DATA <= x"5F";
when x"142" => DATA <= x"4C";
when x"143" => DATA <= x"15";
when x"144" => DATA <= x"15";
when x"145" => DATA <= x"86";
when x"146" => DATA <= x"15";
when x"147" => DATA <= x"15";
when x"148" => DATA <= x"73";
when x"149" => DATA <= x"48";
when x"14A" => DATA <= x"15";
when x"14B" => DATA <= x"15";
when x"14C" => DATA <= x"15";
when x"14D" => DATA <= x"7A";
when x"14E" => DATA <= x"15";
when x"14F" => DATA <= x"15";
when x"150" => DATA <= x"02";
when x"151" => DATA <= x"15";
when x"152" => DATA <= x"15";
when x"153" => DATA <= x"29";
when x"154" => DATA <= x"15";
when x"155" => DATA <= x"15";
when x"156" => DATA <= x"28";
when x"157" => DATA <= x"15";
when x"158" => DATA <= x"15";
when x"159" => DATA <= x"66";
when x"15A" => DATA <= x"15";
when x"15B" => DATA <= x"15";
when x"15C" => DATA <= x"15";
when x"15D" => DATA <= x"5B";
when x"15E" => DATA <= x"72";
when x"15F" => DATA <= x"15";
when x"160" => DATA <= x"A6";
when x"161" => DATA <= x"15";
when x"162" => DATA <= x"15";
when x"163" => DATA <= x"15";
when x"164" => DATA <= x"A7";
when x"165" => DATA <= x"90";
when x"166" => DATA <= x"35";
when x"167" => DATA <= x"E3";
when x"168" => DATA <= x"8F";
when x"169" => DATA <= x"8F";
when x"16A" => DATA <= x"8F";
when x"16B" => DATA <= x"34";
when x"16C" => DATA <= x"94";
when x"16D" => DATA <= x"A0";
when x"16E" => DATA <= x"A8";
when x"16F" => DATA <= x"AD";
when x"170" => DATA <= x"B1";
when x"171" => DATA <= x"BD";
when x"172" => DATA <= x"C1";
when x"173" => DATA <= x"CD";
when x"174" => DATA <= x"E9";
when x"175" => DATA <= x"EA";
when x"176" => DATA <= x"EB";
when x"177" => DATA <= x"78";
when x"178" => DATA <= x"97";
when x"179" => DATA <= x"99";
when x"17A" => DATA <= x"D3";
when x"17B" => DATA <= x"DF";
when x"17C" => DATA <= x"EC";
when x"17D" => DATA <= x"D0";
when x"17E" => DATA <= x"4B";
when x"17F" => DATA <= x"8F";
when x"180" => DATA <= x"8F";
when x"181" => DATA <= x"8F";
when x"182" => DATA <= x"0A";
when x"183" => DATA <= x"8F";
when x"184" => DATA <= x"AD";
when x"185" => DATA <= x"AD";
when x"186" => DATA <= x"8F";
when x"187" => DATA <= x"F0";
when x"188" => DATA <= x"9C";
when x"189" => DATA <= x"8F";
when x"18A" => DATA <= x"25";
when x"18B" => DATA <= x"8F";
when x"18C" => DATA <= x"8F";
when x"18D" => DATA <= x"8F";
when x"18E" => DATA <= x"B2";
when x"18F" => DATA <= x"A4";
when x"190" => DATA <= x"9C";
when x"191" => DATA <= x"8F";
when x"192" => DATA <= x"51";
when x"193" => DATA <= x"99";
when x"194" => DATA <= x"8F";
when x"195" => DATA <= x"8F";
when x"196" => DATA <= x"ED";
when x"197" => DATA <= x"8F";
when x"198" => DATA <= x"8F";
when x"199" => DATA <= x"8F";
when x"19A" => DATA <= x"8F";
when x"19B" => DATA <= x"D2";
when x"19C" => DATA <= x"8F";
when x"19D" => DATA <= x"8F";
when x"19E" => DATA <= x"8F";
when x"19F" => DATA <= x"CD";
when x"1A0" => DATA <= x"B3";
when x"1A1" => DATA <= x"66";
when x"1A2" => DATA <= x"8F";
when x"1A3" => DATA <= x"8F";
when x"1A4" => DATA <= x"8F";
when x"1A5" => DATA <= x"8F";
when x"1A6" => DATA <= x"81";
when x"1A7" => DATA <= x"8F";
when x"1A8" => DATA <= x"8F";
when x"1A9" => DATA <= x"8F";
when x"1AA" => DATA <= x"8F";
when x"1AB" => DATA <= x"D2";
when x"1AC" => DATA <= x"8F";
when x"1AD" => DATA <= x"B8";
when x"1AE" => DATA <= x"8F";
when x"1AF" => DATA <= x"05";
when x"1B0" => DATA <= x"CA";
when x"1B1" => DATA <= x"C7";
when x"1B2" => DATA <= x"8F";
when x"1B3" => DATA <= x"8F";
when x"1B4" => DATA <= x"8F";
when x"1B5" => DATA <= x"EC";
when x"1B6" => DATA <= x"8F";
when x"1B7" => DATA <= x"8F";
when x"1B8" => DATA <= x"75";
when x"1B9" => DATA <= x"8F";
when x"1BA" => DATA <= x"8F";
when x"1BB" => DATA <= x"41";
when x"1BC" => DATA <= x"8F";
when x"1BD" => DATA <= x"8F";
when x"1BE" => DATA <= x"57";
when x"1BF" => DATA <= x"8F";
when x"1C0" => DATA <= x"8F";
when x"1C1" => DATA <= x"98";
when x"1C2" => DATA <= x"D7";
when x"1C3" => DATA <= x"8F";
when x"1C4" => DATA <= x"8F";
when x"1C5" => DATA <= x"E3";
when x"1C6" => DATA <= x"DB";
when x"1C7" => DATA <= x"8F";
when x"1C8" => DATA <= x"8F";
when x"1C9" => DATA <= x"C5";
when x"1CA" => DATA <= x"90";
when x"1CB" => DATA <= x"8F";
when x"1CC" => DATA <= x"8F";
when x"1CD" => DATA <= x"B6";
when x"1CE" => DATA <= x"8F";
when x"1CF" => DATA <= x"8F";
when x"1D0" => DATA <= x"8F";
when x"1D1" => DATA <= x"8F";
when x"1D2" => DATA <= x"E6";
when x"1D3" => DATA <= x"8F";
when x"1D4" => DATA <= x"47";
when x"1D5" => DATA <= x"8F";
when x"1D6" => DATA <= x"8F";
when x"1D7" => DATA <= x"95";
when x"1D8" => DATA <= x"EE";
when x"1D9" => DATA <= x"06";
when x"1DA" => DATA <= x"5C";
when x"1DB" => DATA <= x"0F";
when x"1DC" => DATA <= x"35";
when x"1DD" => DATA <= x"2D";
when x"1DE" => DATA <= x"2B";
when x"1DF" => DATA <= x"7C";
when x"1E0" => DATA <= x"3A";
when x"1E1" => DATA <= x"FE";
when x"1E2" => DATA <= x"2A";
when x"1E3" => DATA <= x"2F";
when x"1E4" => DATA <= x"25";
when x"1E5" => DATA <= x"21";
when x"1E6" => DATA <= x"3F";
when x"1E7" => DATA <= x"26";
when x"1E8" => DATA <= x"FE";
when x"1E9" => DATA <= x"29";
when x"1EA" => DATA <= x"FF";
when x"1EB" => DATA <= x"3D";
when x"1EC" => DATA <= x"FF";
when x"1ED" => DATA <= x"21";
when x"1EE" => DATA <= x"3F";
when x"1EF" => DATA <= x"24";
when x"1F0" => DATA <= x"FF";
when x"1F1" => DATA <= x"3D";
when x"1F2" => DATA <= x"21";
when x"1F3" => DATA <= x"3F";
when x"1F4" => DATA <= x"FF";
when x"1F5" => DATA <= x"27";
when x"1F6" => DATA <= x"22";
when x"1F7" => DATA <= x"FE";
when x"1F8" => DATA <= x"B7";
when x"1F9" => DATA <= x"9A";
when x"1FA" => DATA <= x"D3";
when x"1FB" => DATA <= x"EF";
when x"1FC" => DATA <= x"EF";
when x"1FD" => DATA <= x"13";
when x"1FE" => DATA <= x"5E";
when x"1FF" => DATA <= x"70";
when x"200" => DATA <= x"B3";
when x"201" => DATA <= x"9C";
when x"202" => DATA <= x"7B";
when x"203" => DATA <= x"7B";
when x"204" => DATA <= x"78";
when x"205" => DATA <= x"78";
when x"206" => DATA <= x"78";
when x"207" => DATA <= x"78";
when x"208" => DATA <= x"EE";
when x"209" => DATA <= x"06";
when x"20A" => DATA <= x"5C";
when x"20B" => DATA <= x"5C";
when x"20C" => DATA <= x"E5";
when x"20D" => DATA <= x"75";
when x"20E" => DATA <= x"7B";
when x"20F" => DATA <= x"7B";
when x"210" => DATA <= x"6F";
when x"211" => DATA <= x"7A";
when x"212" => DATA <= x"C7";
when x"213" => DATA <= x"C7";
when x"214" => DATA <= x"C7";
when x"215" => DATA <= x"C7";
when x"216" => DATA <= x"C7";
when x"217" => DATA <= x"C8";
when x"218" => DATA <= x"C8";
when x"219" => DATA <= x"C8";
when x"21A" => DATA <= x"C8";
when x"21B" => DATA <= x"C8";
when x"21C" => DATA <= x"C8";
when x"21D" => DATA <= x"C8";
when x"21E" => DATA <= x"C2";
when x"21F" => DATA <= x"C2";
when x"220" => DATA <= x"C2";
when x"221" => DATA <= x"C2";
when x"222" => DATA <= x"C3";
when x"223" => DATA <= x"C4";
when x"224" => DATA <= x"CD";
when x"225" => DATA <= x"CD";
when x"226" => DATA <= x"C3";
when x"227" => DATA <= x"CD";
when x"228" => DATA <= x"CD";
when x"229" => DATA <= x"CD";
when x"22A" => DATA <= x"C3";
when x"22B" => DATA <= x"C3";
when x"22C" => DATA <= x"20";
when x"22D" => DATA <= x"3E";
when x"22E" => DATA <= x"CF";
when x"22F" => DATA <= x"84";
when x"230" => DATA <= x"0F";
when x"231" => DATA <= x"A2";
when x"232" => DATA <= x"ED";
when x"233" => DATA <= x"A4";
when x"234" => DATA <= x"03";
when x"235" => DATA <= x"88";
when x"236" => DATA <= x"C8";
when x"237" => DATA <= x"B1";
when x"238" => DATA <= x"05";
when x"239" => DATA <= x"C9";
when x"23A" => DATA <= x"20";
when x"23B" => DATA <= x"F0";
when x"23C" => DATA <= x"F9";
when x"23D" => DATA <= x"84";
when x"23E" => DATA <= x"5E";
when x"23F" => DATA <= x"85";
when x"240" => DATA <= x"52";
when x"241" => DATA <= x"E8";
when x"242" => DATA <= x"BD";
when x"243" => DATA <= x"FF";
when x"244" => DATA <= x"BF";
when x"245" => DATA <= x"30";
when x"246" => DATA <= x"24";
when x"247" => DATA <= x"C5";
when x"248" => DATA <= x"52";
when x"249" => DATA <= x"D0";
when x"24A" => DATA <= x"F6";
when x"24B" => DATA <= x"BD";
when x"24C" => DATA <= x"EE";
when x"24D" => DATA <= x"C0";
when x"24E" => DATA <= x"AA";
when x"24F" => DATA <= x"E8";
when x"250" => DATA <= x"C8";
when x"251" => DATA <= x"BD";
when x"252" => DATA <= x"FF";
when x"253" => DATA <= x"BF";
when x"254" => DATA <= x"30";
when x"255" => DATA <= x"15";
when x"256" => DATA <= x"D1";
when x"257" => DATA <= x"05";
when x"258" => DATA <= x"F0";
when x"259" => DATA <= x"F5";
when x"25A" => DATA <= x"B1";
when x"25B" => DATA <= x"05";
when x"25C" => DATA <= x"C9";
when x"25D" => DATA <= x"2E";
when x"25E" => DATA <= x"F0";
when x"25F" => DATA <= x"04";
when x"260" => DATA <= x"A4";
when x"261" => DATA <= x"5E";
when x"262" => DATA <= x"10";
when x"263" => DATA <= x"E7";
when x"264" => DATA <= x"E8";
when x"265" => DATA <= x"BD";
when x"266" => DATA <= x"FF";
when x"267" => DATA <= x"BF";
when x"268" => DATA <= x"10";
when x"269" => DATA <= x"FA";
when x"26A" => DATA <= x"C8";
when x"26B" => DATA <= x"C9";
when x"26C" => DATA <= x"FE";
when x"26D" => DATA <= x"B0";
when x"26E" => DATA <= x"3B";
when x"26F" => DATA <= x"85";
when x"270" => DATA <= x"53";
when x"271" => DATA <= x"BD";
when x"272" => DATA <= x"EE";
when x"273" => DATA <= x"C0";
when x"274" => DATA <= x"90";
when x"275" => DATA <= x"29";
when x"276" => DATA <= x"A6";
when x"277" => DATA <= x"04";
when x"278" => DATA <= x"60";
when x"279" => DATA <= x"A2";
when x"27A" => DATA <= x"0E";
when x"27B" => DATA <= x"A4";
when x"27C" => DATA <= x"03";
when x"27D" => DATA <= x"88";
when x"27E" => DATA <= x"C8";
when x"27F" => DATA <= x"B1";
when x"280" => DATA <= x"05";
when x"281" => DATA <= x"C9";
when x"282" => DATA <= x"20";
when x"283" => DATA <= x"F0";
when x"284" => DATA <= x"F9";
when x"285" => DATA <= x"DD";
when x"286" => DATA <= x"DD";
when x"287" => DATA <= x"C1";
when x"288" => DATA <= x"F0";
when x"289" => DATA <= x"0C";
when x"28A" => DATA <= x"85";
when x"28B" => DATA <= x"52";
when x"28C" => DATA <= x"E8";
when x"28D" => DATA <= x"BD";
when x"28E" => DATA <= x"DD";
when x"28F" => DATA <= x"C1";
when x"290" => DATA <= x"30";
when x"291" => DATA <= x"16";
when x"292" => DATA <= x"C5";
when x"293" => DATA <= x"52";
when x"294" => DATA <= x"D0";
when x"295" => DATA <= x"F6";
when x"296" => DATA <= x"BD";
when x"297" => DATA <= x"12";
when x"298" => DATA <= x"C2";
when x"299" => DATA <= x"85";
when x"29A" => DATA <= x"53";
when x"29B" => DATA <= x"BD";
when x"29C" => DATA <= x"F8";
when x"29D" => DATA <= x"C1";
when x"29E" => DATA <= x"C8";
when x"29F" => DATA <= x"85";
when x"2A0" => DATA <= x"52";
when x"2A1" => DATA <= x"84";
when x"2A2" => DATA <= x"03";
when x"2A3" => DATA <= x"A6";
when x"2A4" => DATA <= x"04";
when x"2A5" => DATA <= x"6C";
when x"2A6" => DATA <= x"52";
when x"2A7" => DATA <= x"00";
when x"2A8" => DATA <= x"C9";
when x"2A9" => DATA <= x"FE";
when x"2AA" => DATA <= x"F0";
when x"2AB" => DATA <= x"CA";
when x"2AC" => DATA <= x"00";
when x"2AD" => DATA <= x"20";
when x"2AE" => DATA <= x"E4";
when x"2AF" => DATA <= x"C4";
when x"2B0" => DATA <= x"D0";
when x"2B1" => DATA <= x"04";
when x"2B2" => DATA <= x"A9";
when x"2B3" => DATA <= x"29";
when x"2B4" => DATA <= x"85";
when x"2B5" => DATA <= x"12";
when x"2B6" => DATA <= x"A9";
when x"2B7" => DATA <= x"0D";
when x"2B8" => DATA <= x"A4";
when x"2B9" => DATA <= x"12";
when x"2BA" => DATA <= x"84";
when x"2BB" => DATA <= x"0E";
when x"2BC" => DATA <= x"A0";
when x"2BD" => DATA <= x"00";
when x"2BE" => DATA <= x"84";
when x"2BF" => DATA <= x"0D";
when x"2C0" => DATA <= x"91";
when x"2C1" => DATA <= x"0D";
when x"2C2" => DATA <= x"A9";
when x"2C3" => DATA <= x"FF";
when x"2C4" => DATA <= x"C8";
when x"2C5" => DATA <= x"91";
when x"2C6" => DATA <= x"0D";
when x"2C7" => DATA <= x"C8";
when x"2C8" => DATA <= x"84";
when x"2C9" => DATA <= x"0D";
when x"2CA" => DATA <= x"A9";
when x"2CB" => DATA <= x"08";
when x"2CC" => DATA <= x"8D";
when x"2CD" => DATA <= x"21";
when x"2CE" => DATA <= x"03";
when x"2CF" => DATA <= x"A9";
when x"2D0" => DATA <= x"3E";
when x"2D1" => DATA <= x"D8";
when x"2D2" => DATA <= x"20";
when x"2D3" => DATA <= x"0F";
when x"2D4" => DATA <= x"CD";
when x"2D5" => DATA <= x"A2";
when x"2D6" => DATA <= x"01";
when x"2D7" => DATA <= x"86";
when x"2D8" => DATA <= x"06";
when x"2D9" => DATA <= x"CA";
when x"2DA" => DATA <= x"86";
when x"2DB" => DATA <= x"05";
when x"2DC" => DATA <= x"86";
when x"2DD" => DATA <= x"01";
when x"2DE" => DATA <= x"86";
when x"2DF" => DATA <= x"02";
when x"2E0" => DATA <= x"A9";
when x"2E1" => DATA <= x"D8";
when x"2E2" => DATA <= x"8D";
when x"2E3" => DATA <= x"02";
when x"2E4" => DATA <= x"02";
when x"2E5" => DATA <= x"A9";
when x"2E6" => DATA <= x"C9";
when x"2E7" => DATA <= x"8D";
when x"2E8" => DATA <= x"03";
when x"2E9" => DATA <= x"02";
when x"2EA" => DATA <= x"A9";
when x"2EB" => DATA <= x"E7";
when x"2EC" => DATA <= x"85";
when x"2ED" => DATA <= x"10";
when x"2EE" => DATA <= x"A9";
when x"2EF" => DATA <= x"C9";
when x"2F0" => DATA <= x"85";
when x"2F1" => DATA <= x"11";
when x"2F2" => DATA <= x"A2";
when x"2F3" => DATA <= x"FF";
when x"2F4" => DATA <= x"9A";
when x"2F5" => DATA <= x"A9";
when x"2F6" => DATA <= x"00";
when x"2F7" => DATA <= x"85";
when x"2F8" => DATA <= x"04";
when x"2F9" => DATA <= x"85";
when x"2FA" => DATA <= x"03";
when x"2FB" => DATA <= x"85";
when x"2FC" => DATA <= x"15";
when x"2FD" => DATA <= x"85";
when x"2FE" => DATA <= x"13";
when x"2FF" => DATA <= x"85";
when x"300" => DATA <= x"14";
when x"301" => DATA <= x"A2";
when x"302" => DATA <= x"34";
when x"303" => DATA <= x"9D";
when x"304" => DATA <= x"8C";
when x"305" => DATA <= x"03";
when x"306" => DATA <= x"CA";
when x"307" => DATA <= x"D0";
when x"308" => DATA <= x"FA";
when x"309" => DATA <= x"20";
when x"30A" => DATA <= x"34";
when x"30B" => DATA <= x"C4";
when x"30C" => DATA <= x"B0";
when x"30D" => DATA <= x"21";
when x"30E" => DATA <= x"20";
when x"30F" => DATA <= x"6A";
when x"310" => DATA <= x"C4";
when x"311" => DATA <= x"90";
when x"312" => DATA <= x"03";
when x"313" => DATA <= x"4C";
when x"314" => DATA <= x"C9";
when x"315" => DATA <= x"CD";
when x"316" => DATA <= x"A2";
when x"317" => DATA <= x"7D";
when x"318" => DATA <= x"4C";
when x"319" => DATA <= x"33";
when x"31A" => DATA <= x"C2";
when x"31B" => DATA <= x"20";
when x"31C" => DATA <= x"34";
when x"31D" => DATA <= x"C4";
when x"31E" => DATA <= x"B0";
when x"31F" => DATA <= x"0F";
when x"320" => DATA <= x"A2";
when x"321" => DATA <= x"7F";
when x"322" => DATA <= x"4C";
when x"323" => DATA <= x"33";
when x"324" => DATA <= x"C2";
when x"325" => DATA <= x"20";
when x"326" => DATA <= x"34";
when x"327" => DATA <= x"C4";
when x"328" => DATA <= x"B0";
when x"329" => DATA <= x"05";
when x"32A" => DATA <= x"A2";
when x"32B" => DATA <= x"10";
when x"32C" => DATA <= x"4C";
when x"32D" => DATA <= x"7B";
when x"32E" => DATA <= x"C2";
when x"32F" => DATA <= x"A2";
when x"330" => DATA <= x"14";
when x"331" => DATA <= x"4C";
when x"332" => DATA <= x"7B";
when x"333" => DATA <= x"C2";
when x"334" => DATA <= x"38";
when x"335" => DATA <= x"66";
when x"336" => DATA <= x"0F";
when x"337" => DATA <= x"20";
when x"338" => DATA <= x"72";
when x"339" => DATA <= x"C3";
when x"33A" => DATA <= x"A2";
when x"33B" => DATA <= x"2E";
when x"33C" => DATA <= x"4C";
when x"33D" => DATA <= x"33";
when x"33E" => DATA <= x"C2";
when x"33F" => DATA <= x"20";
when x"340" => DATA <= x"8B";
when x"341" => DATA <= x"C7";
when x"342" => DATA <= x"20";
when x"343" => DATA <= x"CB";
when x"344" => DATA <= x"C3";
when x"345" => DATA <= x"A5";
when x"346" => DATA <= x"0F";
when x"347" => DATA <= x"30";
when x"348" => DATA <= x"21";
when x"349" => DATA <= x"A2";
when x"34A" => DATA <= x"00";
when x"34B" => DATA <= x"86";
when x"34C" => DATA <= x"27";
when x"34D" => DATA <= x"A0";
when x"34E" => DATA <= x"00";
when x"34F" => DATA <= x"B9";
when x"350" => DATA <= x"52";
when x"351" => DATA <= x"00";
when x"352" => DATA <= x"48";
when x"353" => DATA <= x"29";
when x"354" => DATA <= x"0F";
when x"355" => DATA <= x"95";
when x"356" => DATA <= x"45";
when x"357" => DATA <= x"68";
when x"358" => DATA <= x"4A";
when x"359" => DATA <= x"4A";
when x"35A" => DATA <= x"4A";
when x"35B" => DATA <= x"4A";
when x"35C" => DATA <= x"E8";
when x"35D" => DATA <= x"95";
when x"35E" => DATA <= x"45";
when x"35F" => DATA <= x"E8";
when x"360" => DATA <= x"C8";
when x"361" => DATA <= x"C0";
when x"362" => DATA <= x"04";
when x"363" => DATA <= x"90";
when x"364" => DATA <= x"EA";
when x"365" => DATA <= x"20";
when x"366" => DATA <= x"C8";
when x"367" => DATA <= x"C5";
when x"368" => DATA <= x"30";
when x"369" => DATA <= x"CD";
when x"36A" => DATA <= x"20";
when x"36B" => DATA <= x"89";
when x"36C" => DATA <= x"C5";
when x"36D" => DATA <= x"30";
when x"36E" => DATA <= x"C8";
when x"36F" => DATA <= x"20";
when x"370" => DATA <= x"54";
when x"371" => DATA <= x"CD";
when x"372" => DATA <= x"A2";
when x"373" => DATA <= x"18";
when x"374" => DATA <= x"4C";
when x"375" => DATA <= x"7B";
when x"376" => DATA <= x"C2";
when x"377" => DATA <= x"20";
when x"378" => DATA <= x"4C";
when x"379" => DATA <= x"CA";
when x"37A" => DATA <= x"B1";
when x"37B" => DATA <= x"05";
when x"37C" => DATA <= x"C8";
when x"37D" => DATA <= x"C9";
when x"37E" => DATA <= x"0D";
when x"37F" => DATA <= x"F0";
when x"380" => DATA <= x"1C";
when x"381" => DATA <= x"84";
when x"382" => DATA <= x"03";
when x"383" => DATA <= x"C9";
when x"384" => DATA <= x"22";
when x"385" => DATA <= x"D0";
when x"386" => DATA <= x"F0";
when x"387" => DATA <= x"B1";
when x"388" => DATA <= x"05";
when x"389" => DATA <= x"C9";
when x"38A" => DATA <= x"22";
when x"38B" => DATA <= x"D0";
when x"38C" => DATA <= x"E5";
when x"38D" => DATA <= x"C8";
when x"38E" => DATA <= x"B0";
when x"38F" => DATA <= x"E7";
when x"390" => DATA <= x"20";
when x"391" => DATA <= x"8B";
when x"392" => DATA <= x"C7";
when x"393" => DATA <= x"20";
when x"394" => DATA <= x"CB";
when x"395" => DATA <= x"C3";
when x"396" => DATA <= x"05";
when x"397" => DATA <= x"54";
when x"398" => DATA <= x"05";
when x"399" => DATA <= x"53";
when x"39A" => DATA <= x"F0";
when x"39B" => DATA <= x"0E";
when x"39C" => DATA <= x"A0";
when x"39D" => DATA <= x"00";
when x"39E" => DATA <= x"B1";
when x"39F" => DATA <= x"52";
when x"3A0" => DATA <= x"C9";
when x"3A1" => DATA <= x"0D";
when x"3A2" => DATA <= x"F0";
when x"3A3" => DATA <= x"93";
when x"3A4" => DATA <= x"20";
when x"3A5" => DATA <= x"4C";
when x"3A6" => DATA <= x"CA";
when x"3A7" => DATA <= x"C8";
when x"3A8" => DATA <= x"D0";
when x"3A9" => DATA <= x"F4";
when x"3AA" => DATA <= x"A5";
when x"3AB" => DATA <= x"52";
when x"3AC" => DATA <= x"20";
when x"3AD" => DATA <= x"4C";
when x"3AE" => DATA <= x"CA";
when x"3AF" => DATA <= x"4C";
when x"3B0" => DATA <= x"37";
when x"3B1" => DATA <= x"C3";
when x"3B2" => DATA <= x"20";
when x"3B3" => DATA <= x"C8";
when x"3B4" => DATA <= x"C3";
when x"3B5" => DATA <= x"20";
when x"3B6" => DATA <= x"E4";
when x"3B7" => DATA <= x"C4";
when x"3B8" => DATA <= x"AD";
when x"3B9" => DATA <= x"22";
when x"3BA" => DATA <= x"03";
when x"3BB" => DATA <= x"AE";
when x"3BC" => DATA <= x"39";
when x"3BD" => DATA <= x"03";
when x"3BE" => DATA <= x"AC";
when x"3BF" => DATA <= x"3A";
when x"3C0" => DATA <= x"03";
when x"3C1" => DATA <= x"20";
when x"3C2" => DATA <= x"A5";
when x"3C3" => DATA <= x"C2";
when x"3C4" => DATA <= x"D8";
when x"3C5" => DATA <= x"4C";
when x"3C6" => DATA <= x"5B";
when x"3C7" => DATA <= x"C5";
when x"3C8" => DATA <= x"20";
when x"3C9" => DATA <= x"BC";
when x"3CA" => DATA <= x"C8";
when x"3CB" => DATA <= x"A0";
when x"3CC" => DATA <= x"52";
when x"3CD" => DATA <= x"CA";
when x"3CE" => DATA <= x"86";
when x"3CF" => DATA <= x"04";
when x"3D0" => DATA <= x"B5";
when x"3D1" => DATA <= x"16";
when x"3D2" => DATA <= x"99";
when x"3D3" => DATA <= x"00";
when x"3D4" => DATA <= x"00";
when x"3D5" => DATA <= x"B5";
when x"3D6" => DATA <= x"25";
when x"3D7" => DATA <= x"99";
when x"3D8" => DATA <= x"01";
when x"3D9" => DATA <= x"00";
when x"3DA" => DATA <= x"B5";
when x"3DB" => DATA <= x"34";
when x"3DC" => DATA <= x"99";
when x"3DD" => DATA <= x"02";
when x"3DE" => DATA <= x"00";
when x"3DF" => DATA <= x"B5";
when x"3E0" => DATA <= x"43";
when x"3E1" => DATA <= x"99";
when x"3E2" => DATA <= x"03";
when x"3E3" => DATA <= x"00";
when x"3E4" => DATA <= x"60";
when x"3E5" => DATA <= x"20";
when x"3E6" => DATA <= x"E1";
when x"3E7" => DATA <= x"C4";
when x"3E8" => DATA <= x"20";
when x"3E9" => DATA <= x"2F";
when x"3EA" => DATA <= x"CA";
when x"3EB" => DATA <= x"4C";
when x"3EC" => DATA <= x"5B";
when x"3ED" => DATA <= x"C5";
when x"3EE" => DATA <= x"20";
when x"3EF" => DATA <= x"BC";
when x"3F0" => DATA <= x"C8";
when x"3F1" => DATA <= x"20";
when x"3F2" => DATA <= x"93";
when x"3F3" => DATA <= x"CE";
when x"3F4" => DATA <= x"B5";
when x"3F5" => DATA <= x"26";
when x"3F6" => DATA <= x"C8";
when x"3F7" => DATA <= x"91";
when x"3F8" => DATA <= x"52";
when x"3F9" => DATA <= x"C8";
when x"3FA" => DATA <= x"B5";
when x"3FB" => DATA <= x"35";
when x"3FC" => DATA <= x"91";
when x"3FD" => DATA <= x"52";
when x"3FE" => DATA <= x"C8";
when x"3FF" => DATA <= x"B5";
when x"400" => DATA <= x"44";
when x"401" => DATA <= x"91";
when x"402" => DATA <= x"52";
when x"403" => DATA <= x"4C";
when x"404" => DATA <= x"5B";
when x"405" => DATA <= x"C5";
when x"406" => DATA <= x"20";
when x"407" => DATA <= x"BC";
when x"408" => DATA <= x"C8";
when x"409" => DATA <= x"20";
when x"40A" => DATA <= x"93";
when x"40B" => DATA <= x"CE";
when x"40C" => DATA <= x"4C";
when x"40D" => DATA <= x"5B";
when x"40E" => DATA <= x"C5";
when x"40F" => DATA <= x"A2";
when x"410" => DATA <= x"00";
when x"411" => DATA <= x"B1";
when x"412" => DATA <= x"05";
when x"413" => DATA <= x"9D";
when x"414" => DATA <= x"00";
when x"415" => DATA <= x"01";
when x"416" => DATA <= x"84";
when x"417" => DATA <= x"03";
when x"418" => DATA <= x"C8";
when x"419" => DATA <= x"E8";
when x"41A" => DATA <= x"C9";
when x"41B" => DATA <= x"0D";
when x"41C" => DATA <= x"D0";
when x"41D" => DATA <= x"F3";
when x"41E" => DATA <= x"20";
when x"41F" => DATA <= x"F7";
when x"420" => DATA <= x"FF";
when x"421" => DATA <= x"4C";
when x"422" => DATA <= x"58";
when x"423" => DATA <= x"C5";
when x"424" => DATA <= x"AD";
when x"425" => DATA <= x"00";
when x"426" => DATA <= x"D0";
when x"427" => DATA <= x"C9";
when x"428" => DATA <= x"AA";
when x"429" => DATA <= x"D0";
when x"42A" => DATA <= x"38";
when x"42B" => DATA <= x"4A";
when x"42C" => DATA <= x"CD";
when x"42D" => DATA <= x"01";
when x"42E" => DATA <= x"D0";
when x"42F" => DATA <= x"D0";
when x"430" => DATA <= x"32";
when x"431" => DATA <= x"A4";
when x"432" => DATA <= x"5E";
when x"433" => DATA <= x"60";
when x"434" => DATA <= x"A4";
when x"435" => DATA <= x"03";
when x"436" => DATA <= x"10";
when x"437" => DATA <= x"03";
when x"438" => DATA <= x"C8";
when x"439" => DATA <= x"84";
when x"43A" => DATA <= x"03";
when x"43B" => DATA <= x"B1";
when x"43C" => DATA <= x"05";
when x"43D" => DATA <= x"C9";
when x"43E" => DATA <= x"20";
when x"43F" => DATA <= x"F0";
when x"440" => DATA <= x"F7";
when x"441" => DATA <= x"C9";
when x"442" => DATA <= x"5B";
when x"443" => DATA <= x"B0";
when x"444" => DATA <= x"1E";
when x"445" => DATA <= x"E9";
when x"446" => DATA <= x"3F";
when x"447" => DATA <= x"90";
when x"448" => DATA <= x"1B";
when x"449" => DATA <= x"A6";
when x"44A" => DATA <= x"04";
when x"44B" => DATA <= x"95";
when x"44C" => DATA <= x"16";
when x"44D" => DATA <= x"C8";
when x"44E" => DATA <= x"B1";
when x"44F" => DATA <= x"05";
when x"450" => DATA <= x"C9";
when x"451" => DATA <= x"2E";
when x"452" => DATA <= x"F0";
when x"453" => DATA <= x"0F";
when x"454" => DATA <= x"C9";
when x"455" => DATA <= x"5B";
when x"456" => DATA <= x"B0";
when x"457" => DATA <= x"04";
when x"458" => DATA <= x"C9";
when x"459" => DATA <= x"40";
when x"45A" => DATA <= x"B0";
when x"45B" => DATA <= x"07";
when x"45C" => DATA <= x"E8";
when x"45D" => DATA <= x"86";
when x"45E" => DATA <= x"04";
when x"45F" => DATA <= x"38";
when x"460" => DATA <= x"84";
when x"461" => DATA <= x"03";
when x"462" => DATA <= x"60";
when x"463" => DATA <= x"18";
when x"464" => DATA <= x"60";
when x"465" => DATA <= x"20";
when x"466" => DATA <= x"34";
when x"467" => DATA <= x"C4";
when x"468" => DATA <= x"B0";
when x"469" => DATA <= x"BB";
when x"46A" => DATA <= x"A2";
when x"46B" => DATA <= x"00";
when x"46C" => DATA <= x"A4";
when x"46D" => DATA <= x"03";
when x"46E" => DATA <= x"86";
when x"46F" => DATA <= x"52";
when x"470" => DATA <= x"86";
when x"471" => DATA <= x"53";
when x"472" => DATA <= x"86";
when x"473" => DATA <= x"54";
when x"474" => DATA <= x"86";
when x"475" => DATA <= x"55";
when x"476" => DATA <= x"88";
when x"477" => DATA <= x"C8";
when x"478" => DATA <= x"B1";
when x"479" => DATA <= x"05";
when x"47A" => DATA <= x"38";
when x"47B" => DATA <= x"E9";
when x"47C" => DATA <= x"30";
when x"47D" => DATA <= x"30";
when x"47E" => DATA <= x"54";
when x"47F" => DATA <= x"C9";
when x"480" => DATA <= x"0A";
when x"481" => DATA <= x"B0";
when x"482" => DATA <= x"50";
when x"483" => DATA <= x"A6";
when x"484" => DATA <= x"53";
when x"485" => DATA <= x"48";
when x"486" => DATA <= x"A5";
when x"487" => DATA <= x"55";
when x"488" => DATA <= x"48";
when x"489" => DATA <= x"A5";
when x"48A" => DATA <= x"54";
when x"48B" => DATA <= x"48";
when x"48C" => DATA <= x"A5";
when x"48D" => DATA <= x"52";
when x"48E" => DATA <= x"0A";
when x"48F" => DATA <= x"26";
when x"490" => DATA <= x"53";
when x"491" => DATA <= x"26";
when x"492" => DATA <= x"54";
when x"493" => DATA <= x"26";
when x"494" => DATA <= x"55";
when x"495" => DATA <= x"30";
when x"496" => DATA <= x"D4";
when x"497" => DATA <= x"0A";
when x"498" => DATA <= x"26";
when x"499" => DATA <= x"53";
when x"49A" => DATA <= x"26";
when x"49B" => DATA <= x"54";
when x"49C" => DATA <= x"26";
when x"49D" => DATA <= x"55";
when x"49E" => DATA <= x"30";
when x"49F" => DATA <= x"CB";
when x"4A0" => DATA <= x"65";
when x"4A1" => DATA <= x"52";
when x"4A2" => DATA <= x"85";
when x"4A3" => DATA <= x"52";
when x"4A4" => DATA <= x"8A";
when x"4A5" => DATA <= x"65";
when x"4A6" => DATA <= x"53";
when x"4A7" => DATA <= x"85";
when x"4A8" => DATA <= x"53";
when x"4A9" => DATA <= x"68";
when x"4AA" => DATA <= x"65";
when x"4AB" => DATA <= x"54";
when x"4AC" => DATA <= x"85";
when x"4AD" => DATA <= x"54";
when x"4AE" => DATA <= x"68";
when x"4AF" => DATA <= x"65";
when x"4B0" => DATA <= x"55";
when x"4B1" => DATA <= x"06";
when x"4B2" => DATA <= x"52";
when x"4B3" => DATA <= x"26";
when x"4B4" => DATA <= x"53";
when x"4B5" => DATA <= x"26";
when x"4B6" => DATA <= x"54";
when x"4B7" => DATA <= x"2A";
when x"4B8" => DATA <= x"30";
when x"4B9" => DATA <= x"B1";
when x"4BA" => DATA <= x"85";
when x"4BB" => DATA <= x"55";
when x"4BC" => DATA <= x"68";
when x"4BD" => DATA <= x"65";
when x"4BE" => DATA <= x"52";
when x"4BF" => DATA <= x"85";
when x"4C0" => DATA <= x"52";
when x"4C1" => DATA <= x"90";
when x"4C2" => DATA <= x"0C";
when x"4C3" => DATA <= x"E6";
when x"4C4" => DATA <= x"53";
when x"4C5" => DATA <= x"D0";
when x"4C6" => DATA <= x"08";
when x"4C7" => DATA <= x"E6";
when x"4C8" => DATA <= x"54";
when x"4C9" => DATA <= x"D0";
when x"4CA" => DATA <= x"04";
when x"4CB" => DATA <= x"E6";
when x"4CC" => DATA <= x"55";
when x"4CD" => DATA <= x"30";
when x"4CE" => DATA <= x"9C";
when x"4CF" => DATA <= x"A2";
when x"4D0" => DATA <= x"FF";
when x"4D1" => DATA <= x"D0";
when x"4D2" => DATA <= x"A4";
when x"4D3" => DATA <= x"8A";
when x"4D4" => DATA <= x"F0";
when x"4D5" => DATA <= x"8D";
when x"4D6" => DATA <= x"38";
when x"4D7" => DATA <= x"84";
when x"4D8" => DATA <= x"03";
when x"4D9" => DATA <= x"A0";
when x"4DA" => DATA <= x"52";
when x"4DB" => DATA <= x"4C";
when x"4DC" => DATA <= x"9F";
when x"4DD" => DATA <= x"C9";
when x"4DE" => DATA <= x"20";
when x"4DF" => DATA <= x"79";
when x"4E0" => DATA <= x"C2";
when x"4E1" => DATA <= x"20";
when x"4E2" => DATA <= x"8B";
when x"4E3" => DATA <= x"C7";
when x"4E4" => DATA <= x"A4";
when x"4E5" => DATA <= x"03";
when x"4E6" => DATA <= x"88";
when x"4E7" => DATA <= x"C8";
when x"4E8" => DATA <= x"B1";
when x"4E9" => DATA <= x"05";
when x"4EA" => DATA <= x"C9";
when x"4EB" => DATA <= x"20";
when x"4EC" => DATA <= x"F0";
when x"4ED" => DATA <= x"F9";
when x"4EE" => DATA <= x"C9";
when x"4EF" => DATA <= x"3B";
when x"4F0" => DATA <= x"F0";
when x"4F1" => DATA <= x"04";
when x"4F2" => DATA <= x"C9";
when x"4F3" => DATA <= x"0D";
when x"4F4" => DATA <= x"D0";
when x"4F5" => DATA <= x"66";
when x"4F6" => DATA <= x"18";
when x"4F7" => DATA <= x"98";
when x"4F8" => DATA <= x"65";
when x"4F9" => DATA <= x"05";
when x"4FA" => DATA <= x"85";
when x"4FB" => DATA <= x"05";
when x"4FC" => DATA <= x"90";
when x"4FD" => DATA <= x"02";
when x"4FE" => DATA <= x"E6";
when x"4FF" => DATA <= x"06";
when x"500" => DATA <= x"A0";
when x"501" => DATA <= x"01";
when x"502" => DATA <= x"84";
when x"503" => DATA <= x"03";
when x"504" => DATA <= x"AD";
when x"505" => DATA <= x"01";
when x"506" => DATA <= x"B0";
when x"507" => DATA <= x"29";
when x"508" => DATA <= x"20";
when x"509" => DATA <= x"F0";
when x"50A" => DATA <= x"3C";
when x"50B" => DATA <= x"60";
when x"50C" => DATA <= x"20";
when x"50D" => DATA <= x"E4";
when x"50E" => DATA <= x"C4";
when x"50F" => DATA <= x"88";
when x"510" => DATA <= x"B1";
when x"511" => DATA <= x"05";
when x"512" => DATA <= x"C9";
when x"513" => DATA <= x"3B";
when x"514" => DATA <= x"F0";
when x"515" => DATA <= x"F5";
when x"516" => DATA <= x"A5";
when x"517" => DATA <= x"06";
when x"518" => DATA <= x"C9";
when x"519" => DATA <= x"01";
when x"51A" => DATA <= x"F0";
when x"51B" => DATA <= x"7A";
when x"51C" => DATA <= x"C8";
when x"51D" => DATA <= x"B1";
when x"51E" => DATA <= x"05";
when x"51F" => DATA <= x"30";
when x"520" => DATA <= x"3B";
when x"521" => DATA <= x"85";
when x"522" => DATA <= x"02";
when x"523" => DATA <= x"C8";
when x"524" => DATA <= x"B1";
when x"525" => DATA <= x"05";
when x"526" => DATA <= x"85";
when x"527" => DATA <= x"01";
when x"528" => DATA <= x"C8";
when x"529" => DATA <= x"B1";
when x"52A" => DATA <= x"05";
when x"52B" => DATA <= x"88";
when x"52C" => DATA <= x"C9";
when x"52D" => DATA <= x"61";
when x"52E" => DATA <= x"90";
when x"52F" => DATA <= x"C7";
when x"530" => DATA <= x"E9";
when x"531" => DATA <= x"61";
when x"532" => DATA <= x"C9";
when x"533" => DATA <= x"1B";
when x"534" => DATA <= x"B0";
when x"535" => DATA <= x"C0";
when x"536" => DATA <= x"C8";
when x"537" => DATA <= x"0A";
when x"538" => DATA <= x"AA";
when x"539" => DATA <= x"20";
when x"53A" => DATA <= x"F6";
when x"53B" => DATA <= x"C4";
when x"53C" => DATA <= x"A5";
when x"53D" => DATA <= x"05";
when x"53E" => DATA <= x"9D";
when x"53F" => DATA <= x"8D";
when x"540" => DATA <= x"03";
when x"541" => DATA <= x"A5";
when x"542" => DATA <= x"06";
when x"543" => DATA <= x"9D";
when x"544" => DATA <= x"8E";
when x"545" => DATA <= x"03";
when x"546" => DATA <= x"60";
when x"547" => DATA <= x"4C";
when x"548" => DATA <= x"CF";
when x"549" => DATA <= x"C2";
when x"54A" => DATA <= x"88";
when x"54B" => DATA <= x"20";
when x"54C" => DATA <= x"F6";
when x"54D" => DATA <= x"C4";
when x"54E" => DATA <= x"D0";
when x"54F" => DATA <= x"0B";
when x"550" => DATA <= x"20";
when x"551" => DATA <= x"24";
when x"552" => DATA <= x"C4";
when x"553" => DATA <= x"90";
when x"554" => DATA <= x"03";
when x"555" => DATA <= x"6C";
when x"556" => DATA <= x"02";
when x"557" => DATA <= x"D0";
when x"558" => DATA <= x"20";
when x"559" => DATA <= x"E4";
when x"55A" => DATA <= x"C4";
when x"55B" => DATA <= x"A0";
when x"55C" => DATA <= x"00";
when x"55D" => DATA <= x"B1";
when x"55E" => DATA <= x"05";
when x"55F" => DATA <= x"C9";
when x"560" => DATA <= x"3B";
when x"561" => DATA <= x"D0";
when x"562" => DATA <= x"1A";
when x"563" => DATA <= x"4C";
when x"564" => DATA <= x"1B";
when x"565" => DATA <= x"C3";
when x"566" => DATA <= x"20";
when x"567" => DATA <= x"0C";
when x"568" => DATA <= x"C7";
when x"569" => DATA <= x"CA";
when x"56A" => DATA <= x"86";
when x"56B" => DATA <= x"04";
when x"56C" => DATA <= x"B5";
when x"56D" => DATA <= x"16";
when x"56E" => DATA <= x"F0";
when x"56F" => DATA <= x"05";
when x"570" => DATA <= x"A2";
when x"571" => DATA <= x"20";
when x"572" => DATA <= x"4C";
when x"573" => DATA <= x"33";
when x"574" => DATA <= x"C2";
when x"575" => DATA <= x"A9";
when x"576" => DATA <= x"0D";
when x"577" => DATA <= x"88";
when x"578" => DATA <= x"C8";
when x"579" => DATA <= x"D1";
when x"57A" => DATA <= x"05";
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when x"57D" => DATA <= x"A5";
when x"57E" => DATA <= x"06";
when x"57F" => DATA <= x"C9";
when x"580" => DATA <= x"01";
when x"581" => DATA <= x"F0";
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when x"583" => DATA <= x"20";
when x"584" => DATA <= x"1C";
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when x"586" => DATA <= x"4C";
when x"587" => DATA <= x"1B";
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when x"589" => DATA <= x"A5";
when x"58A" => DATA <= x"43";
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when x"58C" => DATA <= x"27";
when x"58D" => DATA <= x"10";
when x"58E" => DATA <= x"04";
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when x"591" => DATA <= x"C4";
when x"592" => DATA <= x"C8";
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when x"594" => DATA <= x"09";
when x"595" => DATA <= x"A9";
when x"596" => DATA <= x"00";
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when x"598" => DATA <= x"45";
when x"599" => DATA <= x"38";
when x"59A" => DATA <= x"A5";
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when x"59C" => DATA <= x"FD";
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when x"59E" => DATA <= x"C6";
when x"59F" => DATA <= x"48";
when x"5A0" => DATA <= x"A5";
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when x"5A2" => DATA <= x"FD";
when x"5A3" => DATA <= x"10";
when x"5A4" => DATA <= x"C6";
when x"5A5" => DATA <= x"48";
when x"5A6" => DATA <= x"A5";
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when x"5A8" => DATA <= x"FD";
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when x"5AA" => DATA <= x"C6";
when x"5AB" => DATA <= x"A8";
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when x"5AE" => DATA <= x"FD";
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when x"5B0" => DATA <= x"C6";
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when x"5B2" => DATA <= x"0E";
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when x"5B4" => DATA <= x"43";
when x"5B5" => DATA <= x"84";
when x"5B6" => DATA <= x"34";
when x"5B7" => DATA <= x"68";
when x"5B8" => DATA <= x"85";
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when x"5BA" => DATA <= x"68";
when x"5BB" => DATA <= x"85";
when x"5BC" => DATA <= x"16";
when x"5BD" => DATA <= x"F6";
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when x"5BF" => DATA <= x"D0";
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when x"5C2" => DATA <= x"68";
when x"5C3" => DATA <= x"CA";
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when x"5C5" => DATA <= x"CF";
when x"5C6" => DATA <= x"A2";
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when x"5C8" => DATA <= x"CA";
when x"5C9" => DATA <= x"F0";
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when x"5CB" => DATA <= x"B5";
when x"5CC" => DATA <= x"45";
when x"5CD" => DATA <= x"F0";
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when x"5CF" => DATA <= x"86";
when x"5D0" => DATA <= x"52";
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when x"5D2" => DATA <= x"27";
when x"5D3" => DATA <= x"10";
when x"5D4" => DATA <= x"02";
when x"5D5" => DATA <= x"E6";
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when x"5D7" => DATA <= x"38";
when x"5D8" => DATA <= x"AD";
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when x"5DA" => DATA <= x"03";
when x"5DB" => DATA <= x"F0";
when x"5DC" => DATA <= x"02";
when x"5DD" => DATA <= x"E9";
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when x"5DF" => DATA <= x"E5";
when x"5E0" => DATA <= x"52";
when x"5E1" => DATA <= x"F0";
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when x"5E4" => DATA <= x"09";
when x"5E5" => DATA <= x"A8";
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when x"5E8" => DATA <= x"20";
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when x"5EB" => DATA <= x"88";
when x"5EC" => DATA <= x"D0";
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when x"5EE" => DATA <= x"24";
when x"5EF" => DATA <= x"27";
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when x"5F1" => DATA <= x"05";
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when x"5F3" => DATA <= x"2D";
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when x"5F5" => DATA <= x"4C";
when x"5F6" => DATA <= x"CA";
when x"5F7" => DATA <= x"B5";
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when x"5F9" => DATA <= x"C9";
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when x"5FB" => DATA <= x"90";
when x"5FC" => DATA <= x"02";
when x"5FD" => DATA <= x"69";
when x"5FE" => DATA <= x"06";
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when x"600" => DATA <= x"30";
when x"601" => DATA <= x"20";
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when x"60F" => DATA <= x"80";
when x"610" => DATA <= x"00";
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when x"612" => DATA <= x"00";
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when x"615" => DATA <= x"86";
when x"616" => DATA <= x"42";
when x"617" => DATA <= x"96";
when x"618" => DATA <= x"E1";
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when x"61A" => DATA <= x"00";
when x"61B" => DATA <= x"00";
when x"61C" => DATA <= x"00";
when x"61D" => DATA <= x"00";
when x"61E" => DATA <= x"00";
when x"61F" => DATA <= x"01";
when x"620" => DATA <= x"0F";
when x"621" => DATA <= x"98";
when x"622" => DATA <= x"F5";
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when x"625" => DATA <= x"00";
when x"626" => DATA <= x"00";
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when x"628" => DATA <= x"00";
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when x"62F" => DATA <= x"04";
when x"630" => DATA <= x"A6";
when x"631" => DATA <= x"04";
when x"632" => DATA <= x"A0";
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when x"634" => DATA <= x"84";
when x"635" => DATA <= x"58";
when x"636" => DATA <= x"A5";
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when x"639" => DATA <= x"59";
when x"63A" => DATA <= x"88";
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when x"63C" => DATA <= x"0D";
when x"63D" => DATA <= x"C8";
when x"63E" => DATA <= x"D1";
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when x"640" => DATA <= x"D0";
when x"641" => DATA <= x"FB";
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when x"643" => DATA <= x"A1";
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when x"645" => DATA <= x"B1";
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when x"647" => DATA <= x"C8";
when x"648" => DATA <= x"D5";
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when x"64A" => DATA <= x"90";
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when x"64C" => DATA <= x"D0";
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when x"64E" => DATA <= x"B1";
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when x"650" => DATA <= x"D5";
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when x"652" => DATA <= x"90";
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when x"65F" => DATA <= x"18";
when x"660" => DATA <= x"60";
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when x"664" => DATA <= x"B5";
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when x"666" => DATA <= x"55";
when x"667" => DATA <= x"41";
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when x"680" => DATA <= x"84";
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when x"684" => DATA <= x"84";
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when x"686" => DATA <= x"84";
when x"687" => DATA <= x"5E";
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when x"68A" => DATA <= x"61";
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when x"68C" => DATA <= x"A5";
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when x"68E" => DATA <= x"20";
when x"68F" => DATA <= x"05";
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when x"692" => DATA <= x"EC";
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when x"6A3" => DATA <= x"57";
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when x"6B7" => DATA <= x"48";
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when x"6BC" => DATA <= x"48";
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when x"6CD" => DATA <= x"85";
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when x"6D4" => DATA <= x"68";
when x"6D5" => DATA <= x"68";
when x"6D6" => DATA <= x"88";
when x"6D7" => DATA <= x"D0";
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when x"6E2" => DATA <= x"49";
when x"6E3" => DATA <= x"80";
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when x"6E8" => DATA <= x"49";
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when x"6EA" => DATA <= x"85";
when x"6EB" => DATA <= x"54";
when x"6EC" => DATA <= x"A0";
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when x"6F3" => DATA <= x"85";
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when x"6F5" => DATA <= x"B5";
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when x"6F7" => DATA <= x"F5";
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when x"6F9" => DATA <= x"85";
when x"6FA" => DATA <= x"55";
when x"6FB" => DATA <= x"B5";
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when x"6FD" => DATA <= x"F5";
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when x"6FF" => DATA <= x"85";
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when x"705" => DATA <= x"05";
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when x"70F" => DATA <= x"A2";
when x"710" => DATA <= x"43";
when x"711" => DATA <= x"4C";
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when x"713" => DATA <= x"C2";
when x"714" => DATA <= x"20";
when x"715" => DATA <= x"2C";
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when x"719" => DATA <= x"35";
when x"71A" => DATA <= x"15";
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when x"71C" => DATA <= x"14";
when x"71D" => DATA <= x"C6";
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when x"71F" => DATA <= x"4C";
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when x"721" => DATA <= x"C7";
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when x"725" => DATA <= x"B5";
when x"726" => DATA <= x"14";
when x"727" => DATA <= x"15";
when x"728" => DATA <= x"15";
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when x"72C" => DATA <= x"A2";
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when x"72E" => DATA <= x"4C";
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when x"730" => DATA <= x"C2";
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when x"734" => DATA <= x"20";
when x"735" => DATA <= x"AE";
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when x"739" => DATA <= x"85";
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when x"73D" => DATA <= x"85";
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when x"73F" => DATA <= x"A0";
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when x"741" => DATA <= x"C8";
when x"742" => DATA <= x"B1";
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when x"744" => DATA <= x"D1";
when x"745" => DATA <= x"52";
when x"746" => DATA <= x"D0";
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when x"748" => DATA <= x"49";
when x"749" => DATA <= x"0D";
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when x"74B" => DATA <= x"F5";
when x"74C" => DATA <= x"A8";
when x"74D" => DATA <= x"F0";
when x"74E" => DATA <= x"11";
when x"74F" => DATA <= x"A0";
when x"750" => DATA <= x"00";
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when x"755" => DATA <= x"C7";
when x"756" => DATA <= x"A2";
when x"757" => DATA <= x"00";
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when x"759" => DATA <= x"33";
when x"75A" => DATA <= x"C2";
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when x"75C" => DATA <= x"DA";
when x"75D" => DATA <= x"C6";
when x"75E" => DATA <= x"D0";
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when x"760" => DATA <= x"C8";
when x"761" => DATA <= x"94";
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when x"763" => DATA <= x"60";
when x"764" => DATA <= x"20";
when x"765" => DATA <= x"DA";
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when x"767" => DATA <= x"F0";
when x"768" => DATA <= x"F7";
when x"769" => DATA <= x"90";
when x"76A" => DATA <= x"F5";
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when x"76C" => DATA <= x"F4";
when x"76D" => DATA <= x"20";
when x"76E" => DATA <= x"DA";
when x"76F" => DATA <= x"C6";
when x"770" => DATA <= x"D0";
when x"771" => DATA <= x"EE";
when x"772" => DATA <= x"F0";
when x"773" => DATA <= x"ED";
when x"774" => DATA <= x"20";
when x"775" => DATA <= x"DA";
when x"776" => DATA <= x"C6";
when x"777" => DATA <= x"90";
when x"778" => DATA <= x"E7";
when x"779" => DATA <= x"B0";
when x"77A" => DATA <= x"E6";
when x"77B" => DATA <= x"20";
when x"77C" => DATA <= x"DA";
when x"77D" => DATA <= x"C6";
when x"77E" => DATA <= x"B0";
when x"77F" => DATA <= x"E0";
when x"780" => DATA <= x"90";
when x"781" => DATA <= x"DF";
when x"782" => DATA <= x"20";
when x"783" => DATA <= x"DA";
when x"784" => DATA <= x"C6";
when x"785" => DATA <= x"F0";
when x"786" => DATA <= x"DA";
when x"787" => DATA <= x"B0";
when x"788" => DATA <= x"D7";
when x"789" => DATA <= x"90";
when x"78A" => DATA <= x"D6";
when x"78B" => DATA <= x"20";
when x"78C" => DATA <= x"0B";
when x"78D" => DATA <= x"C8";
when x"78E" => DATA <= x"4C";
when x"78F" => DATA <= x"95";
when x"790" => DATA <= x"C7";
when x"791" => DATA <= x"95";
when x"792" => DATA <= x"41";
when x"793" => DATA <= x"C6";
when x"794" => DATA <= x"04";
when x"795" => DATA <= x"A2";
when x"796" => DATA <= x"00";
when x"797" => DATA <= x"4C";
when x"798" => DATA <= x"7B";
when x"799" => DATA <= x"C2";
when x"79A" => DATA <= x"20";
when x"79B" => DATA <= x"0B";
when x"79C" => DATA <= x"C8";
when x"79D" => DATA <= x"18";
when x"79E" => DATA <= x"B5";
when x"79F" => DATA <= x"14";
when x"7A0" => DATA <= x"75";
when x"7A1" => DATA <= x"15";
when x"7A2" => DATA <= x"95";
when x"7A3" => DATA <= x"14";
when x"7A4" => DATA <= x"B5";
when x"7A5" => DATA <= x"23";
when x"7A6" => DATA <= x"75";
when x"7A7" => DATA <= x"24";
when x"7A8" => DATA <= x"95";
when x"7A9" => DATA <= x"23";
when x"7AA" => DATA <= x"B5";
when x"7AB" => DATA <= x"32";
when x"7AC" => DATA <= x"75";
when x"7AD" => DATA <= x"33";
when x"7AE" => DATA <= x"95";
when x"7AF" => DATA <= x"32";
when x"7B0" => DATA <= x"B5";
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when x"7B2" => DATA <= x"75";
when x"7B3" => DATA <= x"42";
when x"7B4" => DATA <= x"4C";
when x"7B5" => DATA <= x"91";
when x"7B6" => DATA <= x"C7";
when x"7B7" => DATA <= x"20";
when x"7B8" => DATA <= x"0B";
when x"7B9" => DATA <= x"C8";
when x"7BA" => DATA <= x"B5";
when x"7BB" => DATA <= x"14";
when x"7BC" => DATA <= x"F5";
when x"7BD" => DATA <= x"15";
when x"7BE" => DATA <= x"95";
when x"7BF" => DATA <= x"14";
when x"7C0" => DATA <= x"B5";
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when x"7C2" => DATA <= x"F5";
when x"7C3" => DATA <= x"24";
when x"7C4" => DATA <= x"95";
when x"7C5" => DATA <= x"23";
when x"7C6" => DATA <= x"B5";
when x"7C7" => DATA <= x"32";
when x"7C8" => DATA <= x"F5";
when x"7C9" => DATA <= x"33";
when x"7CA" => DATA <= x"95";
when x"7CB" => DATA <= x"32";
when x"7CC" => DATA <= x"B5";
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when x"7CE" => DATA <= x"F5";
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when x"7D0" => DATA <= x"4C";
when x"7D1" => DATA <= x"91";
when x"7D2" => DATA <= x"C7";
when x"7D3" => DATA <= x"20";
when x"7D4" => DATA <= x"0B";
when x"7D5" => DATA <= x"C8";
when x"7D6" => DATA <= x"B5";
when x"7D7" => DATA <= x"14";
when x"7D8" => DATA <= x"15";
when x"7D9" => DATA <= x"15";
when x"7DA" => DATA <= x"95";
when x"7DB" => DATA <= x"14";
when x"7DC" => DATA <= x"B5";
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when x"7DE" => DATA <= x"15";
when x"7DF" => DATA <= x"24";
when x"7E0" => DATA <= x"95";
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when x"7E2" => DATA <= x"B5";
when x"7E3" => DATA <= x"32";
when x"7E4" => DATA <= x"15";
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when x"7E6" => DATA <= x"95";
when x"7E7" => DATA <= x"32";
when x"7E8" => DATA <= x"B5";
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when x"7EA" => DATA <= x"15";
when x"7EB" => DATA <= x"42";
when x"7EC" => DATA <= x"4C";
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when x"7EE" => DATA <= x"C7";
when x"7EF" => DATA <= x"20";
when x"7F0" => DATA <= x"0B";
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when x"7F3" => DATA <= x"14";
when x"7F4" => DATA <= x"55";
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when x"7F6" => DATA <= x"95";
when x"7F7" => DATA <= x"14";
when x"7F8" => DATA <= x"B5";
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when x"7FA" => DATA <= x"55";
when x"7FB" => DATA <= x"24";
when x"7FC" => DATA <= x"95";
when x"7FD" => DATA <= x"23";
when x"7FE" => DATA <= x"B5";
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when x"800" => DATA <= x"55";
when x"801" => DATA <= x"33";
when x"802" => DATA <= x"95";
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when x"806" => DATA <= x"55";
when x"807" => DATA <= x"42";
when x"808" => DATA <= x"4C";
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when x"80B" => DATA <= x"20";
when x"80C" => DATA <= x"BC";
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when x"80E" => DATA <= x"A2";
when x"80F" => DATA <= x"05";
when x"810" => DATA <= x"4C";
when x"811" => DATA <= x"7B";
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when x"813" => DATA <= x"20";
when x"814" => DATA <= x"61";
when x"815" => DATA <= x"C6";
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when x"817" => DATA <= x"5A";
when x"818" => DATA <= x"66";
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when x"81A" => DATA <= x"66";
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when x"81C" => DATA <= x"66";
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when x"820" => DATA <= x"18";
when x"821" => DATA <= x"98";
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when x"824" => DATA <= x"A8";
when x"825" => DATA <= x"A5";
when x"826" => DATA <= x"5C";
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when x"828" => DATA <= x"54";
when x"829" => DATA <= x"85";
when x"82A" => DATA <= x"5C";
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when x"82C" => DATA <= x"5D";
when x"82D" => DATA <= x"65";
when x"82E" => DATA <= x"55";
when x"82F" => DATA <= x"85";
when x"830" => DATA <= x"5D";
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when x"832" => DATA <= x"5E";
when x"833" => DATA <= x"65";
when x"834" => DATA <= x"56";
when x"835" => DATA <= x"29";
when x"836" => DATA <= x"7F";
when x"837" => DATA <= x"85";
when x"838" => DATA <= x"5E";
when x"839" => DATA <= x"06";
when x"83A" => DATA <= x"53";
when x"83B" => DATA <= x"26";
when x"83C" => DATA <= x"54";
when x"83D" => DATA <= x"26";
when x"83E" => DATA <= x"55";
when x"83F" => DATA <= x"26";
when x"840" => DATA <= x"56";
when x"841" => DATA <= x"A5";
when x"842" => DATA <= x"57";
when x"843" => DATA <= x"05";
when x"844" => DATA <= x"58";
when x"845" => DATA <= x"05";
when x"846" => DATA <= x"59";
when x"847" => DATA <= x"05";
when x"848" => DATA <= x"5A";
when x"849" => DATA <= x"D0";
when x"84A" => DATA <= x"CB";
when x"84B" => DATA <= x"84";
when x"84C" => DATA <= x"5B";
when x"84D" => DATA <= x"A5";
when x"84E" => DATA <= x"52";
when x"84F" => DATA <= x"08";
when x"850" => DATA <= x"A0";
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when x"853" => DATA <= x"9F";
when x"854" => DATA <= x"C9";
when x"855" => DATA <= x"28";
when x"856" => DATA <= x"10";
when x"857" => DATA <= x"03";
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when x"859" => DATA <= x"C4";
when x"85A" => DATA <= x"C8";
when x"85B" => DATA <= x"4C";
when x"85C" => DATA <= x"0E";
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when x"85E" => DATA <= x"20";
when x"85F" => DATA <= x"89";
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when x"862" => DATA <= x"57";
when x"863" => DATA <= x"26";
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when x"865" => DATA <= x"26";
when x"866" => DATA <= x"59";
when x"867" => DATA <= x"26";
when x"868" => DATA <= x"5A";
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when x"86A" => DATA <= x"52";
when x"86B" => DATA <= x"08";
when x"86C" => DATA <= x"A0";
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when x"86E" => DATA <= x"D0";
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when x"871" => DATA <= x"89";
when x"872" => DATA <= x"C6";
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when x"874" => DATA <= x"04";
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when x"876" => DATA <= x"44";
when x"877" => DATA <= x"08";
when x"878" => DATA <= x"4C";
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when x"87A" => DATA <= x"C8";
when x"87B" => DATA <= x"20";
when x"87C" => DATA <= x"BC";
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when x"87F" => DATA <= x"86";
when x"880" => DATA <= x"04";
when x"881" => DATA <= x"B5";
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when x"883" => DATA <= x"35";
when x"884" => DATA <= x"16";
when x"885" => DATA <= x"95";
when x"886" => DATA <= x"15";
when x"887" => DATA <= x"B5";
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when x"889" => DATA <= x"35";
when x"88A" => DATA <= x"25";
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when x"88C" => DATA <= x"24";
when x"88D" => DATA <= x"B5";
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when x"88F" => DATA <= x"35";
when x"890" => DATA <= x"34";
when x"891" => DATA <= x"95";
when x"892" => DATA <= x"33";
when x"893" => DATA <= x"B5";
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when x"895" => DATA <= x"35";
when x"896" => DATA <= x"43";
when x"897" => DATA <= x"95";
when x"898" => DATA <= x"42";
when x"899" => DATA <= x"4C";
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when x"89B" => DATA <= x"C8";
when x"89C" => DATA <= x"20";
when x"89D" => DATA <= x"A2";
when x"89E" => DATA <= x"C8";
when x"89F" => DATA <= x"4C";
when x"8A0" => DATA <= x"0E";
when x"8A1" => DATA <= x"C8";
when x"8A2" => DATA <= x"20";
when x"8A3" => DATA <= x"BC";
when x"8A4" => DATA <= x"C8";
when x"8A5" => DATA <= x"18";
when x"8A6" => DATA <= x"B5";
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when x"8A8" => DATA <= x"75";
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when x"8AA" => DATA <= x"A8";
when x"8AB" => DATA <= x"B5";
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when x"8AD" => DATA <= x"75";
when x"8AE" => DATA <= x"23";
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when x"8B0" => DATA <= x"4C";
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when x"8B2" => DATA <= x"C9";
when x"8B3" => DATA <= x"20";
when x"8B4" => DATA <= x"A2";
when x"8B5" => DATA <= x"C8";
when x"8B6" => DATA <= x"20";
when x"8B7" => DATA <= x"62";
when x"8B8" => DATA <= x"C9";
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when x"8BB" => DATA <= x"C8";
when x"8BC" => DATA <= x"A2";
when x"8BD" => DATA <= x"04";
when x"8BE" => DATA <= x"4C";
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when x"8C0" => DATA <= x"C2";
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when x"8C2" => DATA <= x"DC";
when x"8C3" => DATA <= x"C8";
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when x"8C5" => DATA <= x"A9";
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when x"8C7" => DATA <= x"A8";
when x"8C8" => DATA <= x"F5";
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when x"8CA" => DATA <= x"95";
when x"8CB" => DATA <= x"15";
when x"8CC" => DATA <= x"98";
when x"8CD" => DATA <= x"F5";
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when x"8CF" => DATA <= x"95";
when x"8D0" => DATA <= x"24";
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when x"8D2" => DATA <= x"F5";
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when x"8D6" => DATA <= x"98";
when x"8D7" => DATA <= x"F5";
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when x"8D9" => DATA <= x"95";
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when x"8DB" => DATA <= x"60";
when x"8DC" => DATA <= x"20";
when x"8DD" => DATA <= x"34";
when x"8DE" => DATA <= x"C4";
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when x"8E0" => DATA <= x"17";
when x"8E1" => DATA <= x"B4";
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when x"8E3" => DATA <= x"B9";
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when x"8E5" => DATA <= x"03";
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when x"8E7" => DATA <= x"15";
when x"8E8" => DATA <= x"B9";
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when x"8EA" => DATA <= x"03";
when x"8EB" => DATA <= x"95";
when x"8EC" => DATA <= x"33";
when x"8ED" => DATA <= x"B9";
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when x"8F0" => DATA <= x"95";
when x"8F1" => DATA <= x"24";
when x"8F2" => DATA <= x"B9";
when x"8F3" => DATA <= x"72";
when x"8F4" => DATA <= x"03";
when x"8F5" => DATA <= x"95";
when x"8F6" => DATA <= x"42";
when x"8F7" => DATA <= x"60";
when x"8F8" => DATA <= x"20";
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when x"8FB" => DATA <= x"B0";
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when x"8FD" => DATA <= x"A2";
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when x"901" => DATA <= x"C2";
when x"902" => DATA <= x"20";
when x"903" => DATA <= x"BC";
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when x"906" => DATA <= x"42";
when x"907" => DATA <= x"30";
when x"908" => DATA <= x"BB";
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when x"90A" => DATA <= x"A2";
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when x"90C" => DATA <= x"86";
when x"90D" => DATA <= x"52";
when x"90E" => DATA <= x"86";
when x"90F" => DATA <= x"53";
when x"910" => DATA <= x"86";
when x"911" => DATA <= x"54";
when x"912" => DATA <= x"86";
when x"913" => DATA <= x"55";
when x"914" => DATA <= x"88";
when x"915" => DATA <= x"C8";
when x"916" => DATA <= x"B1";
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when x"918" => DATA <= x"C9";
when x"919" => DATA <= x"30";
when x"91A" => DATA <= x"90";
when x"91B" => DATA <= x"22";
when x"91C" => DATA <= x"C9";
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when x"91E" => DATA <= x"90";
when x"91F" => DATA <= x"0A";
when x"920" => DATA <= x"E9";
when x"921" => DATA <= x"37";
when x"922" => DATA <= x"C9";
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when x"924" => DATA <= x"90";
when x"925" => DATA <= x"18";
when x"926" => DATA <= x"C9";
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when x"928" => DATA <= x"B0";
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when x"92A" => DATA <= x"0A";
when x"92B" => DATA <= x"0A";
when x"92C" => DATA <= x"0A";
when x"92D" => DATA <= x"0A";
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when x"92F" => DATA <= x"03";
when x"930" => DATA <= x"0A";
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when x"932" => DATA <= x"52";
when x"933" => DATA <= x"26";
when x"934" => DATA <= x"53";
when x"935" => DATA <= x"26";
when x"936" => DATA <= x"54";
when x"937" => DATA <= x"26";
when x"938" => DATA <= x"55";
when x"939" => DATA <= x"CA";
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when x"93B" => DATA <= x"F4";
when x"93C" => DATA <= x"30";
when x"93D" => DATA <= x"D7";
when x"93E" => DATA <= x"8A";
when x"93F" => DATA <= x"10";
when x"940" => DATA <= x"18";
when x"941" => DATA <= x"4C";
when x"942" => DATA <= x"D6";
when x"943" => DATA <= x"C4";
when x"944" => DATA <= x"20";
when x"945" => DATA <= x"0C";
when x"946" => DATA <= x"C7";
when x"947" => DATA <= x"A2";
when x"948" => DATA <= x"0C";
when x"949" => DATA <= x"4C";
when x"94A" => DATA <= x"7B";
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when x"94C" => DATA <= x"20";
when x"94D" => DATA <= x"BC";
when x"94E" => DATA <= x"C8";
when x"94F" => DATA <= x"B4";
when x"950" => DATA <= x"15";
when x"951" => DATA <= x"B5";
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when x"953" => DATA <= x"85";
when x"954" => DATA <= x"53";
when x"955" => DATA <= x"84";
when x"956" => DATA <= x"52";
when x"957" => DATA <= x"CA";
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when x"959" => DATA <= x"00";
when x"95A" => DATA <= x"B1";
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when x"95C" => DATA <= x"4C";
when x"95D" => DATA <= x"7C";
when x"95E" => DATA <= x"C9";
when x"95F" => DATA <= x"20";
when x"960" => DATA <= x"4C";
when x"961" => DATA <= x"C9";
when x"962" => DATA <= x"A0";
when x"963" => DATA <= x"01";
when x"964" => DATA <= x"B1";
when x"965" => DATA <= x"52";
when x"966" => DATA <= x"95";
when x"967" => DATA <= x"24";
when x"968" => DATA <= x"C8";
when x"969" => DATA <= x"B1";
when x"96A" => DATA <= x"52";
when x"96B" => DATA <= x"95";
when x"96C" => DATA <= x"33";
when x"96D" => DATA <= x"C8";
when x"96E" => DATA <= x"B1";
when x"96F" => DATA <= x"52";
when x"970" => DATA <= x"95";
when x"971" => DATA <= x"42";
when x"972" => DATA <= x"60";
when x"973" => DATA <= x"A0";
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when x"975" => DATA <= x"20";
when x"976" => DATA <= x"A1";
when x"977" => DATA <= x"C9";
when x"978" => DATA <= x"F0";
when x"979" => DATA <= x"07";
when x"97A" => DATA <= x"A5";
when x"97B" => DATA <= x"07";
when x"97C" => DATA <= x"20";
when x"97D" => DATA <= x"B3";
when x"97E" => DATA <= x"C9";
when x"97F" => DATA <= x"95";
when x"980" => DATA <= x"24";
when x"981" => DATA <= x"95";
when x"982" => DATA <= x"33";
when x"983" => DATA <= x"95";
when x"984" => DATA <= x"42";
when x"985" => DATA <= x"60";
when x"986" => DATA <= x"A0";
when x"987" => DATA <= x"20";
when x"988" => DATA <= x"A5";
when x"989" => DATA <= x"0A";
when x"98A" => DATA <= x"4A";
when x"98B" => DATA <= x"4A";
when x"98C" => DATA <= x"4A";
when x"98D" => DATA <= x"45";
when x"98E" => DATA <= x"0C";
when x"98F" => DATA <= x"6A";
when x"990" => DATA <= x"26";
when x"991" => DATA <= x"08";
when x"992" => DATA <= x"26";
when x"993" => DATA <= x"09";
when x"994" => DATA <= x"26";
when x"995" => DATA <= x"0A";
when x"996" => DATA <= x"26";
when x"997" => DATA <= x"0B";
when x"998" => DATA <= x"26";
when x"999" => DATA <= x"0C";
when x"99A" => DATA <= x"88";
when x"99B" => DATA <= x"D0";
when x"99C" => DATA <= x"EB";
when x"99D" => DATA <= x"A0";
when x"99E" => DATA <= x"08";
when x"99F" => DATA <= x"A6";
when x"9A0" => DATA <= x"04";
when x"9A1" => DATA <= x"B9";
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when x"9A4" => DATA <= x"95";
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when x"9A8" => DATA <= x"00";
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when x"9AA" => DATA <= x"34";
when x"9AB" => DATA <= x"B9";
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when x"9AE" => DATA <= x"95";
when x"9AF" => DATA <= x"43";
when x"9B0" => DATA <= x"B9";
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when x"9B2" => DATA <= x"00";
when x"9B3" => DATA <= x"95";
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when x"9B5" => DATA <= x"E8";
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when x"9B7" => DATA <= x"04";
when x"9B8" => DATA <= x"A4";
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when x"9BA" => DATA <= x"A9";
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when x"9BC" => DATA <= x"60";
when x"9BD" => DATA <= x"20";
when x"9BE" => DATA <= x"BC";
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when x"9C0" => DATA <= x"20";
when x"9C1" => DATA <= x"CB";
when x"9C2" => DATA <= x"C3";
when x"9C3" => DATA <= x"A0";
when x"9C4" => DATA <= x"00";
when x"9C5" => DATA <= x"A9";
when x"9C6" => DATA <= x"0D";
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when x"9CB" => DATA <= x"C8";
when x"9CC" => DATA <= x"D0";
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when x"9CE" => DATA <= x"98";
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when x"9D2" => DATA <= x"20";
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when x"9D5" => DATA <= x"4C";
when x"9D6" => DATA <= x"58";
when x"9D7" => DATA <= x"C9";
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when x"9D9" => DATA <= x"68";
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when x"9EB" => DATA <= x"50";
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when x"9EF" => DATA <= x"24";
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when x"9F5" => DATA <= x"52";
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when x"A17" => DATA <= x"46";
when x"A18" => DATA <= x"46";
when x"A19" => DATA <= x"46";
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when x"A1C" => DATA <= x"00";
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when x"AA7" => DATA <= x"C8";
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when x"B1E" => DATA <= x"F9";
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when x"B21" => DATA <= x"85";
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when x"B33" => DATA <= x"54";
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when x"B3E" => DATA <= x"04";
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when x"B62" => DATA <= x"98";
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when x"B71" => DATA <= x"99";
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when x"B75" => DATA <= x"56";
when x"B76" => DATA <= x"02";
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when x"B79" => DATA <= x"99";
when x"B7A" => DATA <= x"4B";
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when x"B7C" => DATA <= x"A2";
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when x"B7E" => DATA <= x"4C";
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when x"B80" => DATA <= x"C2";
when x"B81" => DATA <= x"20";
when x"B82" => DATA <= x"8B";
when x"B83" => DATA <= x"C7";
when x"B84" => DATA <= x"A4";
when x"B85" => DATA <= x"15";
when x"B86" => DATA <= x"CA";
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when x"B88" => DATA <= x"04";
when x"B89" => DATA <= x"B5";
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when x"B8B" => DATA <= x"99";
when x"B8C" => DATA <= x"77";
when x"B8D" => DATA <= x"02";
when x"B8E" => DATA <= x"B5";
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when x"B90" => DATA <= x"99";
when x"B91" => DATA <= x"82";
when x"B92" => DATA <= x"02";
when x"B93" => DATA <= x"B5";
when x"B94" => DATA <= x"34";
when x"B95" => DATA <= x"99";
when x"B96" => DATA <= x"8D";
when x"B97" => DATA <= x"02";
when x"B98" => DATA <= x"B5";
when x"B99" => DATA <= x"43";
when x"B9A" => DATA <= x"99";
when x"B9B" => DATA <= x"98";
when x"B9C" => DATA <= x"02";
when x"B9D" => DATA <= x"A2";
when x"B9E" => DATA <= x"1A";
when x"B9F" => DATA <= x"4C";
when x"BA0" => DATA <= x"33";
when x"BA1" => DATA <= x"C2";
when x"BA2" => DATA <= x"20";
when x"BA3" => DATA <= x"8B";
when x"BA4" => DATA <= x"C7";
when x"BA5" => DATA <= x"A4";
when x"BA6" => DATA <= x"15";
when x"BA7" => DATA <= x"CA";
when x"BA8" => DATA <= x"86";
when x"BA9" => DATA <= x"04";
when x"BAA" => DATA <= x"B5";
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when x"BAC" => DATA <= x"99";
when x"BAD" => DATA <= x"4B";
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when x"BAF" => DATA <= x"B5";
when x"BB0" => DATA <= x"25";
when x"BB1" => DATA <= x"99";
when x"BB2" => DATA <= x"56";
when x"BB3" => DATA <= x"02";
when x"BB4" => DATA <= x"B5";
when x"BB5" => DATA <= x"34";
when x"BB6" => DATA <= x"99";
when x"BB7" => DATA <= x"61";
when x"BB8" => DATA <= x"02";
when x"BB9" => DATA <= x"B5";
when x"BBA" => DATA <= x"43";
when x"BBB" => DATA <= x"99";
when x"BBC" => DATA <= x"6C";
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when x"BBE" => DATA <= x"20";
when x"BBF" => DATA <= x"0C";
when x"BC0" => DATA <= x"C5";
when x"BC1" => DATA <= x"A4";
when x"BC2" => DATA <= x"15";
when x"BC3" => DATA <= x"A5";
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when x"BC5" => DATA <= x"99";
when x"BC6" => DATA <= x"A3";
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when x"BC8" => DATA <= x"A5";
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when x"BCA" => DATA <= x"99";
when x"BCB" => DATA <= x"AE";
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when x"BCD" => DATA <= x"E6";
when x"BCE" => DATA <= x"15";
when x"BCF" => DATA <= x"4C";
when x"BD0" => DATA <= x"1B";
when x"BD1" => DATA <= x"C3";
when x"BD2" => DATA <= x"20";
when x"BD3" => DATA <= x"1F";
when x"BD4" => DATA <= x"CC";
when x"BD5" => DATA <= x"20";
when x"BD6" => DATA <= x"0C";
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when x"BD9" => DATA <= x"14";
when x"BDA" => DATA <= x"C0";
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when x"BDC" => DATA <= x"B0";
when x"BDD" => DATA <= x"22";
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when x"BE0" => DATA <= x"99";
when x"BE1" => DATA <= x"CF";
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when x"BE3" => DATA <= x"A5";
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when x"BE5" => DATA <= x"99";
when x"BE6" => DATA <= x"DD";
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when x"BEA" => DATA <= x"90";
when x"BEB" => DATA <= x"1F";
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when x"BED" => DATA <= x"E4";
when x"BEE" => DATA <= x"C4";
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when x"BF0" => DATA <= x"14";
when x"BF1" => DATA <= x"F0";
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when x"BF3" => DATA <= x"C6";
when x"BF4" => DATA <= x"14";
when x"BF5" => DATA <= x"B9";
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when x"BFD" => DATA <= x"85";
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when x"C00" => DATA <= x"00";
when x"C01" => DATA <= x"C5";
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when x"C03" => DATA <= x"1B";
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when x"C05" => DATA <= x"20";
when x"C06" => DATA <= x"1F";
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when x"C08" => DATA <= x"20";
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when x"C0C" => DATA <= x"57";
when x"C0D" => DATA <= x"D0";
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when x"C10" => DATA <= x"2E";
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when x"C12" => DATA <= x"B0";
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when x"C14" => DATA <= x"A4";
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when x"C16" => DATA <= x"A5";
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when x"C18" => DATA <= x"84";
when x"C19" => DATA <= x"05";
when x"C1A" => DATA <= x"4C";
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when x"C1C" => DATA <= x"CB";
when x"C1D" => DATA <= x"00";
when x"C1E" => DATA <= x"C8";
when x"C1F" => DATA <= x"B1";
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when x"C21" => DATA <= x"C9";
when x"C22" => DATA <= x"20";
when x"C23" => DATA <= x"F0";
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when x"C27" => DATA <= x"90";
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when x"C29" => DATA <= x"85";
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when x"C2C" => DATA <= x"61";
when x"C2D" => DATA <= x"C9";
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when x"C30" => DATA <= x"48";
when x"C31" => DATA <= x"0A";
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when x"C3C" => DATA <= x"8E";
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when x"C3E" => DATA <= x"85";
when x"C3F" => DATA <= x"59";
when x"C40" => DATA <= x"05";
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when x"C42" => DATA <= x"D0";
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when x"C44" => DATA <= x"A8";
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when x"C47" => DATA <= x"85";
when x"C48" => DATA <= x"59";
when x"C49" => DATA <= x"88";
when x"C4A" => DATA <= x"A9";
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when x"C4C" => DATA <= x"C8";
when x"C4D" => DATA <= x"D1";
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when x"C4F" => DATA <= x"D0";
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when x"C51" => DATA <= x"C8";
when x"C52" => DATA <= x"B1";
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when x"C54" => DATA <= x"30";
when x"C55" => DATA <= x"45";
when x"C56" => DATA <= x"85";
when x"C57" => DATA <= x"02";
when x"C58" => DATA <= x"C8";
when x"C59" => DATA <= x"B1";
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when x"C5B" => DATA <= x"85";
when x"C5C" => DATA <= x"01";
when x"C5D" => DATA <= x"C8";
when x"C5E" => DATA <= x"B1";
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when x"C60" => DATA <= x"88";
when x"C61" => DATA <= x"C5";
when x"C62" => DATA <= x"57";
when x"C63" => DATA <= x"F0";
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when x"C65" => DATA <= x"20";
when x"C66" => DATA <= x"A1";
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when x"C68" => DATA <= x"4C";
when x"C69" => DATA <= x"4A";
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when x"C6B" => DATA <= x"20";
when x"C6C" => DATA <= x"A2";
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when x"C70" => DATA <= x"9D";
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when x"C72" => DATA <= x"03";
when x"C73" => DATA <= x"A5";
when x"C74" => DATA <= x"59";
when x"C75" => DATA <= x"9D";
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when x"C78" => DATA <= x"60";
when x"C79" => DATA <= x"20";
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when x"C7C" => DATA <= x"A9";
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when x"C7E" => DATA <= x"85";
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when x"C80" => DATA <= x"60";
when x"C81" => DATA <= x"20";
when x"C82" => DATA <= x"72";
when x"C83" => DATA <= x"C3";
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when x"C8C" => DATA <= x"33";
when x"C8D" => DATA <= x"C2";
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when x"C8F" => DATA <= x"09";
when x"C90" => DATA <= x"CD";
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when x"C93" => DATA <= x"48";
when x"C94" => DATA <= x"A5";
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when x"CA3" => DATA <= x"84";
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when x"CAC" => DATA <= x"85";
when x"CAD" => DATA <= x"06";
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when x"CAF" => DATA <= x"85";
when x"CB0" => DATA <= x"05";
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when x"CB2" => DATA <= x"2C";
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when x"CB4" => DATA <= x"33";
when x"CB5" => DATA <= x"C2";
when x"CB6" => DATA <= x"20";
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when x"CB8" => DATA <= x"C7";
when x"CB9" => DATA <= x"A0";
when x"CBA" => DATA <= x"54";
when x"CBB" => DATA <= x"20";
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when x"CBD" => DATA <= x"C3";
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when x"CC3" => DATA <= x"A0";
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when x"CCF" => DATA <= x"C8";
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when x"CD2" => DATA <= x"20";
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when x"CED" => DATA <= x"4C";
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when x"CF7" => DATA <= x"20";
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when x"CFF" => DATA <= x"A5";
when x"D00" => DATA <= x"06";
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when x"D03" => DATA <= x"02";
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when x"D0C" => DATA <= x"40";
when x"D0D" => DATA <= x"D0";
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when x"D0F" => DATA <= x"A0";
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when x"D12" => DATA <= x"4C";
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when x"D14" => DATA <= x"84";
when x"D15" => DATA <= x"52";
when x"D16" => DATA <= x"A4";
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when x"D18" => DATA <= x"20";
when x"D19" => DATA <= x"E6";
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when x"D1B" => DATA <= x"C9";
when x"D1C" => DATA <= x"7F";
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when x"D1F" => DATA <= x"88";
when x"D20" => DATA <= x"C4";
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when x"D22" => DATA <= x"10";
when x"D23" => DATA <= x"F4";
when x"D24" => DATA <= x"30";
when x"D25" => DATA <= x"F0";
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when x"D27" => DATA <= x"18";
when x"D28" => DATA <= x"D0";
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when x"D2A" => DATA <= x"20";
when x"D2B" => DATA <= x"54";
when x"D2C" => DATA <= x"CD";
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when x"D2F" => DATA <= x"CD";
when x"D30" => DATA <= x"C9";
when x"D31" => DATA <= x"1B";
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when x"D33" => DATA <= x"03";
when x"D34" => DATA <= x"4C";
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when x"D36" => DATA <= x"C2";
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when x"D38" => DATA <= x"00";
when x"D39" => DATA <= x"01";
when x"D3A" => DATA <= x"C9";
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when x"D3C" => DATA <= x"F0";
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when x"D3E" => DATA <= x"C8";
when x"D3F" => DATA <= x"98";
when x"D40" => DATA <= x"38";
when x"D41" => DATA <= x"E5";
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when x"D43" => DATA <= x"C9";
when x"D44" => DATA <= x"40";
when x"D45" => DATA <= x"90";
when x"D46" => DATA <= x"D1";
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when x"D48" => DATA <= x"E3";
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when x"D4A" => DATA <= x"C9";
when x"D4B" => DATA <= x"7F";
when x"D4C" => DATA <= x"D0";
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when x"D4E" => DATA <= x"20";
when x"D4F" => DATA <= x"F4";
when x"D50" => DATA <= x"FF";
when x"D51" => DATA <= x"4C";
when x"D52" => DATA <= x"1F";
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when x"D54" => DATA <= x"20";
when x"D55" => DATA <= x"ED";
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when x"D58" => DATA <= x"00";
when x"D59" => DATA <= x"85";
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when x"D5C" => DATA <= x"20";
when x"D5D" => DATA <= x"8B";
when x"D5E" => DATA <= x"C7";
when x"D5F" => DATA <= x"20";
when x"D60" => DATA <= x"AE";
when x"D61" => DATA <= x"CE";
when x"D62" => DATA <= x"A0";
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when x"D64" => DATA <= x"20";
when x"D65" => DATA <= x"CD";
when x"D66" => DATA <= x"C3";
when x"D67" => DATA <= x"A0";
when x"D68" => DATA <= x"FF";
when x"D69" => DATA <= x"C8";
when x"D6A" => DATA <= x"B1";
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when x"D6C" => DATA <= x"91";
when x"D6D" => DATA <= x"54";
when x"D6E" => DATA <= x"C9";
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when x"D70" => DATA <= x"D0";
when x"D71" => DATA <= x"F7";
when x"D72" => DATA <= x"4C";
when x"D73" => DATA <= x"58";
when x"D74" => DATA <= x"C5";
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when x"D76" => DATA <= x"81";
when x"D77" => DATA <= x"CD";
when x"D78" => DATA <= x"4C";
when x"D79" => DATA <= x"F1";
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when x"D7B" => DATA <= x"20";
when x"D7C" => DATA <= x"81";
when x"D7D" => DATA <= x"CD";
when x"D7E" => DATA <= x"4C";
when x"D7F" => DATA <= x"09";
when x"D80" => DATA <= x"C4";
when x"D81" => DATA <= x"20";
when x"D82" => DATA <= x"E1";
when x"D83" => DATA <= x"C8";
when x"D84" => DATA <= x"20";
when x"D85" => DATA <= x"BC";
when x"D86" => DATA <= x"C8";
when x"D87" => DATA <= x"CA";
when x"D88" => DATA <= x"18";
when x"D89" => DATA <= x"B5";
when x"D8A" => DATA <= x"16";
when x"D8B" => DATA <= x"75";
when x"D8C" => DATA <= x"15";
when x"D8D" => DATA <= x"95";
when x"D8E" => DATA <= x"15";
when x"D8F" => DATA <= x"B5";
when x"D90" => DATA <= x"25";
when x"D91" => DATA <= x"75";
when x"D92" => DATA <= x"24";
when x"D93" => DATA <= x"95";
when x"D94" => DATA <= x"24";
when x"D95" => DATA <= x"86";
when x"D96" => DATA <= x"04";
when x"D97" => DATA <= x"60";
when x"D98" => DATA <= x"20";
when x"D99" => DATA <= x"E4";
when x"D9A" => DATA <= x"C4";
when x"D9B" => DATA <= x"A5";
when x"D9C" => DATA <= x"12";
when x"D9D" => DATA <= x"85";
when x"D9E" => DATA <= x"0E";
when x"D9F" => DATA <= x"A0";
when x"DA0" => DATA <= x"00";
when x"DA1" => DATA <= x"84";
when x"DA2" => DATA <= x"0D";
when x"DA3" => DATA <= x"88";
when x"DA4" => DATA <= x"C8";
when x"DA5" => DATA <= x"B1";
when x"DA6" => DATA <= x"0D";
when x"DA7" => DATA <= x"C9";
when x"DA8" => DATA <= x"0D";
when x"DA9" => DATA <= x"D0";
when x"DAA" => DATA <= x"F9";
when x"DAB" => DATA <= x"20";
when x"DAC" => DATA <= x"BC";
when x"DAD" => DATA <= x"CD";
when x"DAE" => DATA <= x"B1";
when x"DAF" => DATA <= x"0D";
when x"DB0" => DATA <= x"30";
when x"DB1" => DATA <= x"03";
when x"DB2" => DATA <= x"C8";
when x"DB3" => DATA <= x"D0";
when x"DB4" => DATA <= x"EF";
when x"DB5" => DATA <= x"C8";
when x"DB6" => DATA <= x"20";
when x"DB7" => DATA <= x"BC";
when x"DB8" => DATA <= x"CD";
when x"DB9" => DATA <= x"4C";
when x"DBA" => DATA <= x"CF";
when x"DBB" => DATA <= x"C2";
when x"DBC" => DATA <= x"18";
when x"DBD" => DATA <= x"98";
when x"DBE" => DATA <= x"65";
when x"DBF" => DATA <= x"0D";
when x"DC0" => DATA <= x"85";
when x"DC1" => DATA <= x"0D";
when x"DC2" => DATA <= x"90";
when x"DC3" => DATA <= x"02";
when x"DC4" => DATA <= x"E6";
when x"DC5" => DATA <= x"0E";
when x"DC6" => DATA <= x"A0";
when x"DC7" => DATA <= x"01";
when x"DC8" => DATA <= x"60";
when x"DC9" => DATA <= x"84";
when x"DCA" => DATA <= x"56";
when x"DCB" => DATA <= x"20";
when x"DCC" => DATA <= x"2E";
when x"DCD" => DATA <= x"C6";
when x"DCE" => DATA <= x"B0";
when x"DCF" => DATA <= x"48";
when x"DD0" => DATA <= x"A5";
when x"DD1" => DATA <= x"58";
when x"DD2" => DATA <= x"85";
when x"DD3" => DATA <= x"52";
when x"DD4" => DATA <= x"E9";
when x"DD5" => DATA <= x"01";
when x"DD6" => DATA <= x"85";
when x"DD7" => DATA <= x"58";
when x"DD8" => DATA <= x"85";
when x"DD9" => DATA <= x"0D";
when x"DDA" => DATA <= x"A5";
when x"DDB" => DATA <= x"59";
when x"DDC" => DATA <= x"85";
when x"DDD" => DATA <= x"53";
when x"DDE" => DATA <= x"E9";
when x"DDF" => DATA <= x"00";
when x"DE0" => DATA <= x"85";
when x"DE1" => DATA <= x"0E";
when x"DE2" => DATA <= x"85";
when x"DE3" => DATA <= x"59";
when x"DE4" => DATA <= x"A9";
when x"DE5" => DATA <= x"0D";
when x"DE6" => DATA <= x"C8";
when x"DE7" => DATA <= x"D1";
when x"DE8" => DATA <= x"52";
when x"DE9" => DATA <= x"D0";
when x"DEA" => DATA <= x"FB";
when x"DEB" => DATA <= x"18";
when x"DEC" => DATA <= x"98";
when x"DED" => DATA <= x"65";
when x"DEE" => DATA <= x"52";
when x"DEF" => DATA <= x"85";
when x"DF0" => DATA <= x"52";
when x"DF1" => DATA <= x"90";
when x"DF2" => DATA <= x"02";
when x"DF3" => DATA <= x"E6";
when x"DF4" => DATA <= x"53";
when x"DF5" => DATA <= x"A0";
when x"DF6" => DATA <= x"00";
when x"DF7" => DATA <= x"B1";
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when x"DF9" => DATA <= x"91";
when x"DFA" => DATA <= x"0D";
when x"DFB" => DATA <= x"C9";
when x"DFC" => DATA <= x"0D";
when x"DFD" => DATA <= x"F0";
when x"DFE" => DATA <= x"09";
when x"DFF" => DATA <= x"C8";
when x"E00" => DATA <= x"D0";
when x"E01" => DATA <= x"F5";
when x"E02" => DATA <= x"E6";
when x"E03" => DATA <= x"53";
when x"E04" => DATA <= x"E6";
when x"E05" => DATA <= x"0E";
when x"E06" => DATA <= x"D0";
when x"E07" => DATA <= x"EF";
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when x"E0A" => DATA <= x"04";
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when x"E0C" => DATA <= x"53";
when x"E0D" => DATA <= x"E6";
when x"E0E" => DATA <= x"0E";
when x"E0F" => DATA <= x"B1";
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when x"E11" => DATA <= x"91";
when x"E12" => DATA <= x"0D";
when x"E13" => DATA <= x"10";
when x"E14" => DATA <= x"EA";
when x"E15" => DATA <= x"20";
when x"E16" => DATA <= x"BD";
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when x"E18" => DATA <= x"A0";
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when x"E1A" => DATA <= x"84";
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when x"E1C" => DATA <= x"88";
when x"E1D" => DATA <= x"A9";
when x"E1E" => DATA <= x"0D";
when x"E1F" => DATA <= x"D1";
when x"E20" => DATA <= x"56";
when x"E21" => DATA <= x"F0";
when x"E22" => DATA <= x"5D";
when x"E23" => DATA <= x"C8";
when x"E24" => DATA <= x"D1";
when x"E25" => DATA <= x"56";
when x"E26" => DATA <= x"D0";
when x"E27" => DATA <= x"FB";
when x"E28" => DATA <= x"C8";
when x"E29" => DATA <= x"C8";
when x"E2A" => DATA <= x"A5";
when x"E2B" => DATA <= x"0D";
when x"E2C" => DATA <= x"85";
when x"E2D" => DATA <= x"54";
when x"E2E" => DATA <= x"A5";
when x"E2F" => DATA <= x"0E";
when x"E30" => DATA <= x"85";
when x"E31" => DATA <= x"55";
when x"E32" => DATA <= x"20";
when x"E33" => DATA <= x"BD";
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when x"E35" => DATA <= x"85";
when x"E36" => DATA <= x"52";
when x"E37" => DATA <= x"A5";
when x"E38" => DATA <= x"0E";
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when x"E3A" => DATA <= x"53";
when x"E3B" => DATA <= x"88";
when x"E3C" => DATA <= x"A9";
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when x"E3E" => DATA <= x"91";
when x"E3F" => DATA <= x"0D";
when x"E40" => DATA <= x"D1";
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when x"E42" => DATA <= x"D0";
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when x"E44" => DATA <= x"0A";
when x"E45" => DATA <= x"91";
when x"E46" => DATA <= x"0D";
when x"E47" => DATA <= x"D1";
when x"E48" => DATA <= x"0D";
when x"E49" => DATA <= x"D0";
when x"E4A" => DATA <= x"AB";
when x"E4B" => DATA <= x"B1";
when x"E4C" => DATA <= x"54";
when x"E4D" => DATA <= x"91";
when x"E4E" => DATA <= x"52";
when x"E4F" => DATA <= x"98";
when x"E50" => DATA <= x"D0";
when x"E51" => DATA <= x"04";
when x"E52" => DATA <= x"C6";
when x"E53" => DATA <= x"55";
when x"E54" => DATA <= x"C6";
when x"E55" => DATA <= x"53";
when x"E56" => DATA <= x"88";
when x"E57" => DATA <= x"98";
when x"E58" => DATA <= x"65";
when x"E59" => DATA <= x"54";
when x"E5A" => DATA <= x"A6";
when x"E5B" => DATA <= x"55";
when x"E5C" => DATA <= x"90";
when x"E5D" => DATA <= x"01";
when x"E5E" => DATA <= x"E8";
when x"E5F" => DATA <= x"C5";
when x"E60" => DATA <= x"58";
when x"E61" => DATA <= x"8A";
when x"E62" => DATA <= x"E5";
when x"E63" => DATA <= x"59";
when x"E64" => DATA <= x"B0";
when x"E65" => DATA <= x"E5";
when x"E66" => DATA <= x"A0";
when x"E67" => DATA <= x"01";
when x"E68" => DATA <= x"A5";
when x"E69" => DATA <= x"25";
when x"E6A" => DATA <= x"91";
when x"E6B" => DATA <= x"58";
when x"E6C" => DATA <= x"C8";
when x"E6D" => DATA <= x"A5";
when x"E6E" => DATA <= x"16";
when x"E6F" => DATA <= x"91";
when x"E70" => DATA <= x"58";
when x"E71" => DATA <= x"38";
when x"E72" => DATA <= x"20";
when x"E73" => DATA <= x"A2";
when x"E74" => DATA <= x"CE";
when x"E75" => DATA <= x"A0";
when x"E76" => DATA <= x"FF";
when x"E77" => DATA <= x"C8";
when x"E78" => DATA <= x"B1";
when x"E79" => DATA <= x"56";
when x"E7A" => DATA <= x"91";
when x"E7B" => DATA <= x"58";
when x"E7C" => DATA <= x"C9";
when x"E7D" => DATA <= x"0D";
when x"E7E" => DATA <= x"D0";
when x"E7F" => DATA <= x"F7";
when x"E80" => DATA <= x"4C";
when x"E81" => DATA <= x"CF";
when x"E82" => DATA <= x"C2";
when x"E83" => DATA <= x"20";
when x"E84" => DATA <= x"E4";
when x"E85" => DATA <= x"C4";
when x"E86" => DATA <= x"A0";
when x"E87" => DATA <= x"00";
when x"E88" => DATA <= x"84";
when x"E89" => DATA <= x"05";
when x"E8A" => DATA <= x"84";
when x"E8B" => DATA <= x"03";
when x"E8C" => DATA <= x"A5";
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when x"E8E" => DATA <= x"85";
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when x"E90" => DATA <= x"4C";
when x"E91" => DATA <= x"5B";
when x"E92" => DATA <= x"C5";
when x"E93" => DATA <= x"20";
when x"E94" => DATA <= x"DE";
when x"E95" => DATA <= x"C4";
when x"E96" => DATA <= x"CA";
when x"E97" => DATA <= x"20";
when x"E98" => DATA <= x"CB";
when x"E99" => DATA <= x"C3";
when x"E9A" => DATA <= x"A0";
when x"E9B" => DATA <= x"00";
when x"E9C" => DATA <= x"B5";
when x"E9D" => DATA <= x"17";
when x"E9E" => DATA <= x"91";
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when x"EA0" => DATA <= x"60";
when x"EA1" => DATA <= x"18";
when x"EA2" => DATA <= x"98";
when x"EA3" => DATA <= x"65";
when x"EA4" => DATA <= x"58";
when x"EA5" => DATA <= x"85";
when x"EA6" => DATA <= x"58";
when x"EA7" => DATA <= x"90";
when x"EA8" => DATA <= x"02";
when x"EA9" => DATA <= x"E6";
when x"EAA" => DATA <= x"59";
when x"EAB" => DATA <= x"4C";
when x"EAC" => DATA <= x"00";
when x"EAD" => DATA <= x"C5";
when x"EAE" => DATA <= x"20";
when x"EAF" => DATA <= x"79";
when x"EB0" => DATA <= x"C2";
when x"EB1" => DATA <= x"A2";
when x"EB2" => DATA <= x"26";
when x"EB3" => DATA <= x"4C";
when x"EB4" => DATA <= x"33";
when x"EB5" => DATA <= x"C2";
when x"EB6" => DATA <= x"20";
when x"EB7" => DATA <= x"8B";
when x"EB8" => DATA <= x"C7";
when x"EB9" => DATA <= x"20";
when x"EBA" => DATA <= x"CB";
when x"EBB" => DATA <= x"C3";
when x"EBC" => DATA <= x"A4";
when x"EBD" => DATA <= x"03";
when x"EBE" => DATA <= x"60";
when x"EBF" => DATA <= x"20";
when x"EC0" => DATA <= x"F6";
when x"EC1" => DATA <= x"C4";
when x"EC2" => DATA <= x"84";
when x"EC3" => DATA <= x"53";
when x"EC4" => DATA <= x"88";
when x"EC5" => DATA <= x"A2";
when x"EC6" => DATA <= x"00";
when x"EC7" => DATA <= x"B1";
when x"EC8" => DATA <= x"05";
when x"EC9" => DATA <= x"C9";
when x"ECA" => DATA <= x"0D";
when x"ECB" => DATA <= x"F0";
when x"ECC" => DATA <= x"F9";
when x"ECD" => DATA <= x"9D";
when x"ECE" => DATA <= x"40";
when x"ECF" => DATA <= x"01";
when x"ED0" => DATA <= x"E8";
when x"ED1" => DATA <= x"C8";
when x"ED2" => DATA <= x"C9";
when x"ED3" => DATA <= x"22";
when x"ED4" => DATA <= x"D0";
when x"ED5" => DATA <= x"F1";
when x"ED6" => DATA <= x"B1";
when x"ED7" => DATA <= x"05";
when x"ED8" => DATA <= x"C9";
when x"ED9" => DATA <= x"22";
when x"EDA" => DATA <= x"F0";
when x"EDB" => DATA <= x"0E";
when x"EDC" => DATA <= x"A9";
when x"EDD" => DATA <= x"0D";
when x"EDE" => DATA <= x"9D";
when x"EDF" => DATA <= x"3F";
when x"EE0" => DATA <= x"01";
when x"EE1" => DATA <= x"84";
when x"EE2" => DATA <= x"03";
when x"EE3" => DATA <= x"A9";
when x"EE4" => DATA <= x"40";
when x"EE5" => DATA <= x"85";
when x"EE6" => DATA <= x"52";
when x"EE7" => DATA <= x"A6";
when x"EE8" => DATA <= x"04";
when x"EE9" => DATA <= x"60";
when x"EEA" => DATA <= x"C8";
when x"EEB" => DATA <= x"B0";
when x"EEC" => DATA <= x"DA";
when x"EED" => DATA <= x"20";
when x"EEE" => DATA <= x"FA";
when x"EEF" => DATA <= x"CE";
when x"EF0" => DATA <= x"88";
when x"EF1" => DATA <= x"84";
when x"EF2" => DATA <= x"56";
when x"EF3" => DATA <= x"38";
when x"EF4" => DATA <= x"20";
when x"EF5" => DATA <= x"E0";
when x"EF6" => DATA <= x"FF";
when x"EF7" => DATA <= x"4C";
when x"EF8" => DATA <= x"9B";
when x"EF9" => DATA <= x"CD";
when x"EFA" => DATA <= x"20";
when x"EFB" => DATA <= x"B1";
when x"EFC" => DATA <= x"CE";
when x"EFD" => DATA <= x"20";
when x"EFE" => DATA <= x"E4";
when x"EFF" => DATA <= x"C4";
when x"F00" => DATA <= x"88";
when x"F01" => DATA <= x"84";
when x"F02" => DATA <= x"54";
when x"F03" => DATA <= x"A5";
when x"F04" => DATA <= x"12";
when x"F05" => DATA <= x"85";
when x"F06" => DATA <= x"55";
when x"F07" => DATA <= x"A2";
when x"F08" => DATA <= x"52";
when x"F09" => DATA <= x"60";
when x"F0A" => DATA <= x"20";
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when x"F0C" => DATA <= x"CE";
when x"F0D" => DATA <= x"84";
when x"F0E" => DATA <= x"58";
when x"F0F" => DATA <= x"85";
when x"F10" => DATA <= x"59";
when x"F11" => DATA <= x"A5";
when x"F12" => DATA <= x"0D";
when x"F13" => DATA <= x"85";
when x"F14" => DATA <= x"5A";
when x"F15" => DATA <= x"A5";
when x"F16" => DATA <= x"0E";
when x"F17" => DATA <= x"85";
when x"F18" => DATA <= x"5B";
when x"F19" => DATA <= x"A9";
when x"F1A" => DATA <= x"B2";
when x"F1B" => DATA <= x"85";
when x"F1C" => DATA <= x"56";
when x"F1D" => DATA <= x"A9";
when x"F1E" => DATA <= x"C2";
when x"F1F" => DATA <= x"85";
when x"F20" => DATA <= x"57";
when x"F21" => DATA <= x"18";
when x"F22" => DATA <= x"20";
when x"F23" => DATA <= x"DD";
when x"F24" => DATA <= x"FF";
when x"F25" => DATA <= x"4C";
when x"F26" => DATA <= x"5B";
when x"F27" => DATA <= x"C5";
when x"F28" => DATA <= x"38";
when x"F29" => DATA <= x"A9";
when x"F2A" => DATA <= x"00";
when x"F2B" => DATA <= x"2A";
when x"F2C" => DATA <= x"48";
when x"F2D" => DATA <= x"20";
when x"F2E" => DATA <= x"3E";
when x"F2F" => DATA <= x"CF";
when x"F30" => DATA <= x"A2";
when x"F31" => DATA <= x"52";
when x"F32" => DATA <= x"68";
when x"F33" => DATA <= x"20";
when x"F34" => DATA <= x"DA";
when x"F35" => DATA <= x"FF";
when x"F36" => DATA <= x"A0";
when x"F37" => DATA <= x"52";
when x"F38" => DATA <= x"20";
when x"F39" => DATA <= x"9F";
when x"F3A" => DATA <= x"C9";
when x"F3B" => DATA <= x"95";
when x"F3C" => DATA <= x"42";
when x"F3D" => DATA <= x"60";
when x"F3E" => DATA <= x"20";
when x"F3F" => DATA <= x"BC";
when x"F40" => DATA <= x"C8";
when x"F41" => DATA <= x"B4";
when x"F42" => DATA <= x"15";
when x"F43" => DATA <= x"CA";
when x"F44" => DATA <= x"86";
when x"F45" => DATA <= x"04";
when x"F46" => DATA <= x"60";
when x"F47" => DATA <= x"20";
when x"F48" => DATA <= x"BC";
when x"F49" => DATA <= x"C8";
when x"F4A" => DATA <= x"20";
when x"F4B" => DATA <= x"DE";
when x"F4C" => DATA <= x"C4";
when x"F4D" => DATA <= x"20";
when x"F4E" => DATA <= x"CB";
when x"F4F" => DATA <= x"C3";
when x"F50" => DATA <= x"20";
when x"F51" => DATA <= x"41";
when x"F52" => DATA <= x"CF";
when x"F53" => DATA <= x"A2";
when x"F54" => DATA <= x"52";
when x"F55" => DATA <= x"20";
when x"F56" => DATA <= x"D7";
when x"F57" => DATA <= x"FF";
when x"F58" => DATA <= x"4C";
when x"F59" => DATA <= x"5B";
when x"F5A" => DATA <= x"C5";
when x"F5B" => DATA <= x"20";
when x"F5C" => DATA <= x"3E";
when x"F5D" => DATA <= x"CF";
when x"F5E" => DATA <= x"84";
when x"F5F" => DATA <= x"52";
when x"F60" => DATA <= x"20";
when x"F61" => DATA <= x"D4";
when x"F62" => DATA <= x"FF";
when x"F63" => DATA <= x"4C";
when x"F64" => DATA <= x"7C";
when x"F65" => DATA <= x"C9";
when x"F66" => DATA <= x"20";
when x"F67" => DATA <= x"5B";
when x"F68" => DATA <= x"CF";
when x"F69" => DATA <= x"A4";
when x"F6A" => DATA <= x"52";
when x"F6B" => DATA <= x"20";
when x"F6C" => DATA <= x"D4";
when x"F6D" => DATA <= x"FF";
when x"F6E" => DATA <= x"95";
when x"F6F" => DATA <= x"24";
when x"F70" => DATA <= x"20";
when x"F71" => DATA <= x"D4";
when x"F72" => DATA <= x"FF";
when x"F73" => DATA <= x"95";
when x"F74" => DATA <= x"33";
when x"F75" => DATA <= x"20";
when x"F76" => DATA <= x"D4";
when x"F77" => DATA <= x"FF";
when x"F78" => DATA <= x"95";
when x"F79" => DATA <= x"42";
when x"F7A" => DATA <= x"60";
when x"F7B" => DATA <= x"20";
when x"F7C" => DATA <= x"BC";
when x"F7D" => DATA <= x"C8";
when x"F7E" => DATA <= x"20";
when x"F7F" => DATA <= x"31";
when x"F80" => DATA <= x"C2";
when x"F81" => DATA <= x"20";
when x"F82" => DATA <= x"E1";
when x"F83" => DATA <= x"C4";
when x"F84" => DATA <= x"20";
when x"F85" => DATA <= x"CB";
when x"F86" => DATA <= x"C3";
when x"F87" => DATA <= x"20";
when x"F88" => DATA <= x"41";
when x"F89" => DATA <= x"CF";
when x"F8A" => DATA <= x"A5";
when x"F8B" => DATA <= x"52";
when x"F8C" => DATA <= x"6C";
when x"F8D" => DATA <= x"16";
when x"F8E" => DATA <= x"02";
when x"F8F" => DATA <= x"20";
when x"F90" => DATA <= x"7B";
when x"F91" => DATA <= x"CF";
when x"F92" => DATA <= x"4C";
when x"F93" => DATA <= x"5B";
when x"F94" => DATA <= x"C5";
when x"F95" => DATA <= x"20";
when x"F96" => DATA <= x"7B";
when x"F97" => DATA <= x"CF";
when x"F98" => DATA <= x"A2";
when x"F99" => DATA <= x"01";
when x"F9A" => DATA <= x"B5";
when x"F9B" => DATA <= x"52";
when x"F9C" => DATA <= x"20";
when x"F9D" => DATA <= x"D1";
when x"F9E" => DATA <= x"FF";
when x"F9F" => DATA <= x"E8";
when x"FA0" => DATA <= x"E0";
when x"FA1" => DATA <= x"04";
when x"FA2" => DATA <= x"90";
when x"FA3" => DATA <= x"F6";
when x"FA4" => DATA <= x"B0";
when x"FA5" => DATA <= x"EC";
when x"FA6" => DATA <= x"38";
when x"FA7" => DATA <= x"08";
when x"FA8" => DATA <= x"20";
when x"FA9" => DATA <= x"B1";
when x"FAA" => DATA <= x"CE";
when x"FAB" => DATA <= x"A2";
when x"FAC" => DATA <= x"52";
when x"FAD" => DATA <= x"28";
when x"FAE" => DATA <= x"20";
when x"FAF" => DATA <= x"CE";
when x"FB0" => DATA <= x"FF";
when x"FB1" => DATA <= x"A6";
when x"FB2" => DATA <= x"04";
when x"FB3" => DATA <= x"4C";
when x"FB4" => DATA <= x"7C";
when x"FB5" => DATA <= x"C9";
when x"FB6" => DATA <= x"20";
when x"FB7" => DATA <= x"BC";
when x"FB8" => DATA <= x"C8";
when x"FB9" => DATA <= x"20";
when x"FBA" => DATA <= x"E4";
when x"FBB" => DATA <= x"C4";
when x"FBC" => DATA <= x"20";
when x"FBD" => DATA <= x"41";
when x"FBE" => DATA <= x"CF";
when x"FBF" => DATA <= x"20";
when x"FC0" => DATA <= x"CB";
when x"FC1" => DATA <= x"FF";
when x"FC2" => DATA <= x"4C";
when x"FC3" => DATA <= x"5B";
when x"FC4" => DATA <= x"C5";
when x"FC5" => DATA <= x"20";
when x"FC6" => DATA <= x"2C";
when x"FC7" => DATA <= x"C2";
when x"FC8" => DATA <= x"20";
when x"FC9" => DATA <= x"B1";
when x"FCA" => DATA <= x"CE";
when x"FCB" => DATA <= x"20";
when x"FCC" => DATA <= x"E4";
when x"FCD" => DATA <= x"C4";
when x"FCE" => DATA <= x"88";
when x"FCF" => DATA <= x"B1";
when x"FD0" => DATA <= x"52";
when x"FD1" => DATA <= x"84";
when x"FD2" => DATA <= x"55";
when x"FD3" => DATA <= x"A4";
when x"FD4" => DATA <= x"0F";
when x"FD5" => DATA <= x"48";
when x"FD6" => DATA <= x"20";
when x"FD7" => DATA <= x"D1";
when x"FD8" => DATA <= x"FF";
when x"FD9" => DATA <= x"68";
when x"FDA" => DATA <= x"C9";
when x"FDB" => DATA <= x"0D";
when x"FDC" => DATA <= x"F0";
when x"FDD" => DATA <= x"E4";
when x"FDE" => DATA <= x"A4";
when x"FDF" => DATA <= x"55";
when x"FE0" => DATA <= x"C8";
when x"FE1" => DATA <= x"D0";
when x"FE2" => DATA <= x"EC";
when x"FE3" => DATA <= x"20";
when x"FE4" => DATA <= x"2C";
when x"FE5" => DATA <= x"C2";
when x"FE6" => DATA <= x"20";
when x"FE7" => DATA <= x"E1";
when x"FE8" => DATA <= x"C4";
when x"FE9" => DATA <= x"20";
when x"FEA" => DATA <= x"CB";
when x"FEB" => DATA <= x"C3";
when x"FEC" => DATA <= x"A0";
when x"FED" => DATA <= x"00";
when x"FEE" => DATA <= x"84";
when x"FEF" => DATA <= x"55";
when x"FF0" => DATA <= x"A4";
when x"FF1" => DATA <= x"0F";
when x"FF2" => DATA <= x"20";
when x"FF3" => DATA <= x"D4";
when x"FF4" => DATA <= x"FF";
when x"FF5" => DATA <= x"A4";
when x"FF6" => DATA <= x"55";
when x"FF7" => DATA <= x"91";
when x"FF8" => DATA <= x"52";
when x"FF9" => DATA <= x"C8";
when x"FFA" => DATA <= x"C9";
when x"FFB" => DATA <= x"0D";
when x"FFC" => DATA <= x"D0";
when x"FFD" => DATA <= x"F0";
when x"FFE" => DATA <= x"F0";
when x"FFF" => DATA <= x"C2";
when others => DATA <= (others => '0');
end case;
end process;
end RTL;
| apache-2.0 | c54fb45b9e880f0af6e5bcbbc02e6ae3 | 0.357929 | 2.925779 | false | false | false | false |
tghaefli/ADD | ISE/FMC_waj/fmc_rom.vhd | 2 | 5,939 | -------------------------------------------------------------------------------
-- Entity: fmc_rom
-- Author: Waj
-------------------------------------------------------------------------------
-- Description:
-- ROM for Floppy-Music Controller (channel-dependent content)
-- NOTE:
-- Since XST does not support the 'val attribute, the following cannot be used
-- to form the channel-number dependent MIF file name:
-- "fmc_rom_" & character'val(N+48) & ".mif"
-- As a workaround, a wrapper unit with conditional generate statements is
-- used.
-------------------------------------------------------------------------------
-- Total # of FFs: FMC_ROM_DW
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- FMC ROM core unit
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use work.mcu_pkg.all;
entity fmc_rom_core is
generic(MIF : string := "rom.mif" -- ROM init file
);
port(clk : in std_logic;
addr : in std_logic_vector(FMC_ROM_AW-1 downto 0);
data : out std_logic_vector(FMC_ROM_DW-1 downto 0)
);
end fmc_rom_core;
architecture rtl of fmc_rom_core is
type t_rom is array (0 to 2**FMC_ROM_AW-1) of std_logic_vector(FMC_ROM_DW-1 downto 0);
impure function f_assign_mif(file_name : in string) return t_rom is
FILE f : text open read_mode is file_name;
variable l : line;
variable s : string(FMC_ROM_DW downto 1);
variable r : t_rom;
begin
for i in t_rom'range loop
if not endfile(f) then
-- Note: The last row in .mif should have no CR
readline(f,l);
read(l,s);
for k in s'range loop
if s(k) = '1' then
r(i)(k-1) := '1';
else
r(i)(k-1) := '0';
end if;
end loop;
end if;
end loop;
return r;
end function;
signal rom_table : t_rom := f_assign_mif(MIF);
signal data_reg : std_logic_vector(FMC_ROM_DW-1 downto 0);
begin
-----------------------------------------------------------------------------
-- Behavioral description of ROM with latency of 2 cc
-----------------------------------------------------------------------------
P_rom: process(clk)
begin
if rising_edge(clk) then
data_reg <= rom_table(to_integer(unsigned(addr)));
data <= data_reg;
end if;
end process;
end rtl;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Wrapper Unit (workaround)
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mcu_pkg.all;
entity fmc_rom is
generic(N : natural := 0 -- channel number
);
port(clk : in std_logic;
addr : in std_logic_vector(FMC_ROM_AW-1 downto 0);
data : out std_logic_vector(FMC_ROM_DW-1 downto 0)
);
end fmc_rom;
architecture rtl of fmc_rom is
begin
-- ROM 0 ------------------------------------
rom_0: if N = 0 generate
rom_core : entity work.fmc_rom_core
generic map(MIF => "fmc_rom_0.mif")
port map (clk => clk,
addr => addr,
data => data
);
end generate;
-- ROM 1 ------------------------------------
rom_1: if N = 1 generate
rom_core : entity work.fmc_rom_core
generic map(MIF => "fmc_rom_1.mif")
port map (clk => clk,
addr => addr,
data => data
);
end generate;
-- ROM 2 ------------------------------------
rom_2: if N = 2 generate
rom_core : entity work.fmc_rom_core
generic map(MIF => "fmc_rom_2.mif")
port map (clk => clk,
addr => addr,
data => data
);
end generate;
-- ROM 3 ------------------------------------
rom_3: if N = 3 generate
rom_core : entity work.fmc_rom_core
generic map(MIF => "fmc_rom_3.mif")
port map (clk => clk,
addr => addr,
data => data
);
end generate;
-- ROM 4 ------------------------------------
rom_4: if N = 4 generate
rom_core : entity work.fmc_rom_core
generic map(MIF => "fmc_rom_4.mif")
port map (clk => clk,
addr => addr,
data => data
);
end generate;
-- ROM 5 ------------------------------------
rom_5: if N = 5 generate
rom_core : entity work.fmc_rom_core
generic map(MIF => "fmc_rom_5.mif")
port map (clk => clk,
addr => addr,
data => data
);
end generate;
-- ROM 6 ------------------------------------
rom_6: if N = 6 generate
rom_core : entity work.fmc_rom_core
generic map(MIF => "fmc_rom_6.mif")
port map (clk => clk,
addr => addr,
data => data
);
end generate;
-- ROM 7 ------------------------------------
rom_7: if N = 7 generate
rom_core : entity work.fmc_rom_core
generic map(MIF => "fmc_rom_7.mif")
port map (clk => clk,
addr => addr,
data => data
);
end generate;
end rtl;
| gpl-3.0 | e6b57ee041e96b70cf8bf92d5be42502 | 0.390807 | 4.533588 | false | false | false | false |
fquinto/Wireless_sensor_network | Avnet_UPC/hdl/temp_sensor_wrapper.vhd | 1 | 7,030 | -------------------------------------------------------------------------------
-- temp_sensor_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library xps_iic_v2_03_a;
use xps_iic_v2_03_a.all;
entity temp_sensor_wrapper is
port (
Sda_I : in std_logic;
Sda_O : out std_logic;
Sda_T : out std_logic;
Scl_I : in std_logic;
Scl_O : out std_logic;
Scl_T : out std_logic;
Gpo : out std_logic_vector(31 to 31);
IIC2INTC_Irpt : out std_logic;
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to 0);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 3);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to 31);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 31);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 1);
Sl_MWrErr : out std_logic_vector(0 to 1);
Sl_MRdErr : out std_logic_vector(0 to 1);
Sl_MIRQ : out std_logic_vector(0 to 1)
);
attribute x_core_info : STRING;
attribute x_core_info of temp_sensor_wrapper : entity is "xps_iic_v2_03_a";
end temp_sensor_wrapper;
architecture STRUCTURE of temp_sensor_wrapper is
component xps_iic is
generic (
C_IIC_FREQ : INTEGER;
C_TEN_BIT_ADR : INTEGER;
C_GPO_WIDTH : INTEGER;
C_CLK_FREQ : INTEGER;
C_SCL_INERTIAL_DELAY : INTEGER;
C_SDA_INERTIAL_DELAY : INTEGER;
C_BASEADDR : std_logic_vector(0 to 31);
C_HIGHADDR : std_logic_vector(0 to 31);
C_SPLB_MID_WIDTH : INTEGER;
C_SPLB_NUM_MASTERS : INTEGER;
C_SPLB_AWIDTH : INTEGER;
C_SPLB_DWIDTH : INTEGER;
C_FAMILY : STRING
);
port (
Sda_I : in std_logic;
Sda_O : out std_logic;
Sda_T : out std_logic;
Scl_I : in std_logic;
Scl_O : out std_logic;
Scl_T : out std_logic;
Gpo : out std_logic_vector((32-C_GPO_WIDTH) to (32-1));
IIC2INTC_Irpt : out std_logic;
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to (C_SPLB_MID_WIDTH-1));
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to ((C_SPLB_DWIDTH/8)-1));
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_DWIDTH-1));
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_DWIDTH-1));
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1))
);
end component;
begin
TEMP_SENSOR : xps_iic
generic map (
C_IIC_FREQ => 100000,
C_TEN_BIT_ADR => 0,
C_GPO_WIDTH => 1,
C_CLK_FREQ => 66666666,
C_SCL_INERTIAL_DELAY => 5,
C_SDA_INERTIAL_DELAY => 5,
C_BASEADDR => X"81600000",
C_HIGHADDR => X"8160ffff",
C_SPLB_MID_WIDTH => 1,
C_SPLB_NUM_MASTERS => 2,
C_SPLB_AWIDTH => 32,
C_SPLB_DWIDTH => 32,
C_FAMILY => "spartan3a"
)
port map (
Sda_I => Sda_I,
Sda_O => Sda_O,
Sda_T => Sda_T,
Scl_I => Scl_I,
Scl_O => Scl_O,
Scl_T => Scl_T,
Gpo => Gpo,
IIC2INTC_Irpt => IIC2INTC_Irpt,
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ
);
end architecture STRUCTURE;
| mit | 3dc2e0c578f9243a24c95415f7327540 | 0.577383 | 3.158131 | false | false | false | false |
tghaefli/ADD | EDK/IVK_Repos/IVK_IPLib/pcores/sg_xsvi_fanin_plbw_v1_01_a/hdl/vhdl/sg_xsvi_fanin.vhd | 1 | 102,274 |
-------------------------------------------------------------------
-- System Generator version 13.2 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package conv_pkg is
constant simulating : boolean := false
-- synopsys translate_off
or true
-- synopsys translate_on
;
constant xlUnsigned : integer := 1;
constant xlSigned : integer := 2;
constant xlFloat : integer := 3;
constant xlWrap : integer := 1;
constant xlSaturate : integer := 2;
constant xlTruncate : integer := 1;
constant xlRound : integer := 2;
constant xlRoundBanker : integer := 3;
constant xlAddMode : integer := 1;
constant xlSubMode : integer := 2;
attribute black_box : boolean;
attribute syn_black_box : boolean;
attribute fpga_dont_touch: string;
attribute box_type : string;
attribute keep : string;
attribute syn_keep : boolean;
function std_logic_vector_to_unsigned(inp : std_logic_vector) return unsigned;
function unsigned_to_std_logic_vector(inp : unsigned) return std_logic_vector;
function std_logic_vector_to_signed(inp : std_logic_vector) return signed;
function signed_to_std_logic_vector(inp : signed) return std_logic_vector;
function unsigned_to_signed(inp : unsigned) return signed;
function signed_to_unsigned(inp : signed) return unsigned;
function pos(inp : std_logic_vector; arith : INTEGER) return boolean;
function all_same(inp: std_logic_vector) return boolean;
function all_zeros(inp: std_logic_vector) return boolean;
function is_point_five(inp: std_logic_vector) return boolean;
function all_ones(inp: std_logic_vector) return boolean;
function convert_type (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith,
quantization, overflow : INTEGER)
return std_logic_vector;
function cast (inp : std_logic_vector; old_bin_pt,
new_width, new_bin_pt, new_arith : INTEGER)
return std_logic_vector;
function shift_division_result(quotient, fraction: std_logic_vector;
fraction_width, shift_value, shift_dir: INTEGER)
return std_logic_vector;
function shift_op (inp: std_logic_vector;
result_width, shift_value, shift_dir: INTEGER)
return std_logic_vector;
function vec_slice (inp : std_logic_vector; upper, lower : INTEGER)
return std_logic_vector;
function s2u_slice (inp : signed; upper, lower : INTEGER)
return unsigned;
function u2u_slice (inp : unsigned; upper, lower : INTEGER)
return unsigned;
function s2s_cast (inp : signed; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return signed;
function u2s_cast (inp : unsigned; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return signed;
function s2u_cast (inp : signed; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return unsigned;
function u2u_cast (inp : unsigned; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return unsigned;
function u2v_cast (inp : unsigned; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return std_logic_vector;
function s2v_cast (inp : signed; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return std_logic_vector;
function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith,
new_width, new_bin_pt, new_arith : INTEGER)
return std_logic_vector;
function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt,
new_arith : INTEGER) return std_logic_vector;
function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt,
new_arith : INTEGER) return std_logic_vector;
function max_signed(width : INTEGER) return std_logic_vector;
function min_signed(width : INTEGER) return std_logic_vector;
function saturation_arith(inp: std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith
: INTEGER) return std_logic_vector;
function wrap_arith(inp: std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith : INTEGER)
return std_logic_vector;
function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER;
function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER)
return INTEGER;
function sign_ext(inp : std_logic_vector; new_width : INTEGER)
return std_logic_vector;
function zero_ext(inp : std_logic_vector; new_width : INTEGER)
return std_logic_vector;
function zero_ext(inp : std_logic; new_width : INTEGER)
return std_logic_vector;
function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER)
return std_logic_vector;
function align_input(inp : std_logic_vector; old_width, delta, new_arith,
new_width: INTEGER)
return std_logic_vector;
function pad_LSB(inp : std_logic_vector; new_width: integer)
return std_logic_vector;
function pad_LSB(inp : std_logic_vector; new_width, arith : integer)
return std_logic_vector;
function max(L, R: INTEGER) return INTEGER;
function min(L, R: INTEGER) return INTEGER;
function "="(left,right: STRING) return boolean;
function boolean_to_signed (inp : boolean; width: integer)
return signed;
function boolean_to_unsigned (inp : boolean; width: integer)
return unsigned;
function boolean_to_vector (inp : boolean)
return std_logic_vector;
function std_logic_to_vector (inp : std_logic)
return std_logic_vector;
function integer_to_std_logic_vector (inp : integer; width, arith : integer)
return std_logic_vector;
function std_logic_vector_to_integer (inp : std_logic_vector; arith : integer)
return integer;
function std_logic_to_integer(constant inp : std_logic := '0')
return integer;
function bin_string_element_to_std_logic_vector (inp : string; width, index : integer)
return std_logic_vector;
function bin_string_to_std_logic_vector (inp : string)
return std_logic_vector;
function hex_string_to_std_logic_vector (inp : string; width : integer)
return std_logic_vector;
function makeZeroBinStr (width : integer) return STRING;
function and_reduce(inp: std_logic_vector) return std_logic;
-- synopsys translate_off
function is_binary_string_invalid (inp : string)
return boolean;
function is_binary_string_undefined (inp : string)
return boolean;
function is_XorU(inp : std_logic_vector)
return boolean;
function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer)
return real;
function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer)
return real;
function real_to_std_logic_vector (inp : real; width, bin_pt, arith : integer)
return std_logic_vector;
function real_string_to_std_logic_vector (inp : string; width, bin_pt, arith : integer)
return std_logic_vector;
constant display_precision : integer := 20;
function real_to_string (inp : real) return string;
function valid_bin_string(inp : string) return boolean;
function std_logic_vector_to_bin_string(inp : std_logic_vector) return string;
function std_logic_to_bin_string(inp : std_logic) return string;
function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer)
return string;
function real_to_bin_string(inp : real; width, bin_pt, arith : integer)
return string;
type stdlogic_to_char_t is array(std_logic) of character;
constant to_char : stdlogic_to_char_t := (
'U' => 'U',
'X' => 'X',
'0' => '0',
'1' => '1',
'Z' => 'Z',
'W' => 'W',
'L' => 'L',
'H' => 'H',
'-' => '-');
-- synopsys translate_on
end conv_pkg;
package body conv_pkg is
function std_logic_vector_to_unsigned(inp : std_logic_vector)
return unsigned
is
begin
return unsigned (inp);
end;
function unsigned_to_std_logic_vector(inp : unsigned)
return std_logic_vector
is
begin
return std_logic_vector(inp);
end;
function std_logic_vector_to_signed(inp : std_logic_vector)
return signed
is
begin
return signed (inp);
end;
function signed_to_std_logic_vector(inp : signed)
return std_logic_vector
is
begin
return std_logic_vector(inp);
end;
function unsigned_to_signed (inp : unsigned)
return signed
is
begin
return signed(std_logic_vector(inp));
end;
function signed_to_unsigned (inp : signed)
return unsigned
is
begin
return unsigned(std_logic_vector(inp));
end;
function pos(inp : std_logic_vector; arith : INTEGER)
return boolean
is
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
begin
vec := inp;
if arith = xlUnsigned then
return true;
else
if vec(width-1) = '0' then
return true;
else
return false;
end if;
end if;
return true;
end;
function max_signed(width : INTEGER)
return std_logic_vector
is
variable ones : std_logic_vector(width-2 downto 0);
variable result : std_logic_vector(width-1 downto 0);
begin
ones := (others => '1');
result(width-1) := '0';
result(width-2 downto 0) := ones;
return result;
end;
function min_signed(width : INTEGER)
return std_logic_vector
is
variable zeros : std_logic_vector(width-2 downto 0);
variable result : std_logic_vector(width-1 downto 0);
begin
zeros := (others => '0');
result(width-1) := '1';
result(width-2 downto 0) := zeros;
return result;
end;
function and_reduce(inp: std_logic_vector) return std_logic
is
variable result: std_logic;
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
begin
vec := inp;
result := vec(0);
if width > 1 then
for i in 1 to width-1 loop
result := result and vec(i);
end loop;
end if;
return result;
end;
function all_same(inp: std_logic_vector) return boolean
is
variable result: boolean;
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
begin
vec := inp;
result := true;
if width > 0 then
for i in 1 to width-1 loop
if vec(i) /= vec(0) then
result := false;
end if;
end loop;
end if;
return result;
end;
function all_zeros(inp: std_logic_vector)
return boolean
is
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
variable zero : std_logic_vector(width-1 downto 0);
variable result : boolean;
begin
zero := (others => '0');
vec := inp;
-- synopsys translate_off
if (is_XorU(vec)) then
return false;
end if;
-- synopsys translate_on
if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(zero)) then
result := true;
else
result := false;
end if;
return result;
end;
function is_point_five(inp: std_logic_vector)
return boolean
is
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
variable result : boolean;
begin
vec := inp;
-- synopsys translate_off
if (is_XorU(vec)) then
return false;
end if;
-- synopsys translate_on
if (width > 1) then
if ((vec(width-1) = '1') and (all_zeros(vec(width-2 downto 0)) = true)) then
result := true;
else
result := false;
end if;
else
if (vec(width-1) = '1') then
result := true;
else
result := false;
end if;
end if;
return result;
end;
function all_ones(inp: std_logic_vector)
return boolean
is
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
variable one : std_logic_vector(width-1 downto 0);
variable result : boolean;
begin
one := (others => '1');
vec := inp;
-- synopsys translate_off
if (is_XorU(vec)) then
return false;
end if;
-- synopsys translate_on
if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(one)) then
result := true;
else
result := false;
end if;
return result;
end;
function full_precision_num_width(quantization, overflow, old_width,
old_bin_pt, old_arith,
new_width, new_bin_pt, new_arith : INTEGER)
return integer
is
variable result : integer;
begin
result := old_width + 2;
return result;
end;
function quantized_num_width(quantization, overflow, old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith
: INTEGER)
return integer
is
variable right_of_dp, left_of_dp, result : integer;
begin
right_of_dp := max(new_bin_pt, old_bin_pt);
left_of_dp := max((new_width - new_bin_pt), (old_width - old_bin_pt));
result := (old_width + 2) + (new_bin_pt - old_bin_pt);
return result;
end;
function convert_type (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith,
quantization, overflow : INTEGER)
return std_logic_vector
is
constant fp_width : integer :=
full_precision_num_width(quantization, overflow, old_width,
old_bin_pt, old_arith, new_width,
new_bin_pt, new_arith);
constant fp_bin_pt : integer := old_bin_pt;
constant fp_arith : integer := old_arith;
variable full_precision_result : std_logic_vector(fp_width-1 downto 0);
constant q_width : integer :=
quantized_num_width(quantization, overflow, old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith);
constant q_bin_pt : integer := new_bin_pt;
constant q_arith : integer := old_arith;
variable quantized_result : std_logic_vector(q_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
result := (others => '0');
full_precision_result := cast(inp, old_bin_pt, fp_width, fp_bin_pt,
fp_arith);
if (quantization = xlRound) then
quantized_result := round_towards_inf(full_precision_result,
fp_width, fp_bin_pt,
fp_arith, q_width, q_bin_pt,
q_arith);
elsif (quantization = xlRoundBanker) then
quantized_result := round_towards_even(full_precision_result,
fp_width, fp_bin_pt,
fp_arith, q_width, q_bin_pt,
q_arith);
else
quantized_result := trunc(full_precision_result, fp_width, fp_bin_pt,
fp_arith, q_width, q_bin_pt, q_arith);
end if;
if (overflow = xlSaturate) then
result := saturation_arith(quantized_result, q_width, q_bin_pt,
q_arith, new_width, new_bin_pt, new_arith);
else
result := wrap_arith(quantized_result, q_width, q_bin_pt, q_arith,
new_width, new_bin_pt, new_arith);
end if;
return result;
end;
function cast (inp : std_logic_vector; old_bin_pt, new_width,
new_bin_pt, new_arith : INTEGER)
return std_logic_vector
is
constant old_width : integer := inp'length;
constant left_of_dp : integer := (new_width - new_bin_pt)
- (old_width - old_bin_pt);
constant right_of_dp : integer := (new_bin_pt - old_bin_pt);
variable vec : std_logic_vector(old_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
variable j : integer;
begin
vec := inp;
for i in new_width-1 downto 0 loop
j := i - right_of_dp;
if ( j > old_width-1) then
if (new_arith = xlUnsigned) then
result(i) := '0';
else
result(i) := vec(old_width-1);
end if;
elsif ( j >= 0) then
result(i) := vec(j);
else
result(i) := '0';
end if;
end loop;
return result;
end;
function shift_division_result(quotient, fraction: std_logic_vector;
fraction_width, shift_value, shift_dir: INTEGER)
return std_logic_vector
is
constant q_width : integer := quotient'length;
constant f_width : integer := fraction'length;
constant vec_MSB : integer := q_width+f_width-1;
constant result_MSB : integer := q_width+fraction_width-1;
constant result_LSB : integer := vec_MSB-result_MSB;
variable vec : std_logic_vector(vec_MSB downto 0);
variable result : std_logic_vector(result_MSB downto 0);
begin
vec := ( quotient & fraction );
if shift_dir = 1 then
for i in vec_MSB downto 0 loop
if (i < shift_value) then
vec(i) := '0';
else
vec(i) := vec(i-shift_value);
end if;
end loop;
else
for i in 0 to vec_MSB loop
if (i > vec_MSB-shift_value) then
vec(i) := vec(vec_MSB);
else
vec(i) := vec(i+shift_value);
end if;
end loop;
end if;
result := vec(vec_MSB downto result_LSB);
return result;
end;
function shift_op (inp: std_logic_vector;
result_width, shift_value, shift_dir: INTEGER)
return std_logic_vector
is
constant inp_width : integer := inp'length;
constant vec_MSB : integer := inp_width-1;
constant result_MSB : integer := result_width-1;
constant result_LSB : integer := vec_MSB-result_MSB;
variable vec : std_logic_vector(vec_MSB downto 0);
variable result : std_logic_vector(result_MSB downto 0);
begin
vec := inp;
if shift_dir = 1 then
for i in vec_MSB downto 0 loop
if (i < shift_value) then
vec(i) := '0';
else
vec(i) := vec(i-shift_value);
end if;
end loop;
else
for i in 0 to vec_MSB loop
if (i > vec_MSB-shift_value) then
vec(i) := vec(vec_MSB);
else
vec(i) := vec(i+shift_value);
end if;
end loop;
end if;
result := vec(vec_MSB downto result_LSB);
return result;
end;
function vec_slice (inp : std_logic_vector; upper, lower : INTEGER)
return std_logic_vector
is
begin
return inp(upper downto lower);
end;
function s2u_slice (inp : signed; upper, lower : INTEGER)
return unsigned
is
begin
return unsigned(vec_slice(std_logic_vector(inp), upper, lower));
end;
function u2u_slice (inp : unsigned; upper, lower : INTEGER)
return unsigned
is
begin
return unsigned(vec_slice(std_logic_vector(inp), upper, lower));
end;
function s2s_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER)
return signed
is
begin
return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned));
end;
function s2u_cast (inp : signed; old_bin_pt, new_width,
new_bin_pt : INTEGER)
return unsigned
is
begin
return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned));
end;
function u2s_cast (inp : unsigned; old_bin_pt, new_width,
new_bin_pt : INTEGER)
return signed
is
begin
return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned));
end;
function u2u_cast (inp : unsigned; old_bin_pt, new_width,
new_bin_pt : INTEGER)
return unsigned
is
begin
return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned));
end;
function u2v_cast (inp : unsigned; old_bin_pt, new_width,
new_bin_pt : INTEGER)
return std_logic_vector
is
begin
return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned);
end;
function s2v_cast (inp : signed; old_bin_pt, new_width,
new_bin_pt : INTEGER)
return std_logic_vector
is
begin
return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned);
end;
function boolean_to_signed (inp : boolean; width : integer)
return signed
is
variable result : signed(width - 1 downto 0);
begin
result := (others => '0');
if inp then
result(0) := '1';
else
result(0) := '0';
end if;
return result;
end;
function boolean_to_unsigned (inp : boolean; width : integer)
return unsigned
is
variable result : unsigned(width - 1 downto 0);
begin
result := (others => '0');
if inp then
result(0) := '1';
else
result(0) := '0';
end if;
return result;
end;
function boolean_to_vector (inp : boolean)
return std_logic_vector
is
variable result : std_logic_vector(1 - 1 downto 0);
begin
result := (others => '0');
if inp then
result(0) := '1';
else
result(0) := '0';
end if;
return result;
end;
function std_logic_to_vector (inp : std_logic)
return std_logic_vector
is
variable result : std_logic_vector(1 - 1 downto 0);
begin
result(0) := inp;
return result;
end;
function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith,
new_width, new_bin_pt, new_arith : INTEGER)
return std_logic_vector
is
constant right_of_dp : integer := (old_bin_pt - new_bin_pt);
variable vec : std_logic_vector(old_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if right_of_dp >= 0 then
if new_arith = xlUnsigned then
result := zero_ext(vec(old_width-1 downto right_of_dp), new_width);
else
result := sign_ext(vec(old_width-1 downto right_of_dp), new_width);
end if;
else
if new_arith = xlUnsigned then
result := zero_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
else
result := sign_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
end if;
end if;
return result;
end;
function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith
: INTEGER)
return std_logic_vector
is
constant right_of_dp : integer := (old_bin_pt - new_bin_pt);
constant expected_new_width : integer := old_width - right_of_dp + 1;
variable vec : std_logic_vector(old_width-1 downto 0);
variable one_or_zero : std_logic_vector(new_width-1 downto 0);
variable truncated_val : std_logic_vector(new_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if right_of_dp >= 0 then
if new_arith = xlUnsigned then
truncated_val := zero_ext(vec(old_width-1 downto right_of_dp),
new_width);
else
truncated_val := sign_ext(vec(old_width-1 downto right_of_dp),
new_width);
end if;
else
if new_arith = xlUnsigned then
truncated_val := zero_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
else
truncated_val := sign_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
end if;
end if;
one_or_zero := (others => '0');
if (new_arith = xlSigned) then
if (vec(old_width-1) = '0') then
one_or_zero(0) := '1';
end if;
if (right_of_dp >= 2) and (right_of_dp <= old_width) then
if (all_zeros(vec(right_of_dp-2 downto 0)) = false) then
one_or_zero(0) := '1';
end if;
end if;
if (right_of_dp >= 1) and (right_of_dp <= old_width) then
if vec(right_of_dp-1) = '0' then
one_or_zero(0) := '0';
end if;
else
one_or_zero(0) := '0';
end if;
else
if (right_of_dp >= 1) and (right_of_dp <= old_width) then
one_or_zero(0) := vec(right_of_dp-1);
end if;
end if;
if new_arith = xlSigned then
result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) +
std_logic_vector_to_signed(one_or_zero));
else
result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) +
std_logic_vector_to_unsigned(one_or_zero));
end if;
return result;
end;
function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith
: INTEGER)
return std_logic_vector
is
constant right_of_dp : integer := (old_bin_pt - new_bin_pt);
constant expected_new_width : integer := old_width - right_of_dp + 1;
variable vec : std_logic_vector(old_width-1 downto 0);
variable one_or_zero : std_logic_vector(new_width-1 downto 0);
variable truncated_val : std_logic_vector(new_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if right_of_dp >= 0 then
if new_arith = xlUnsigned then
truncated_val := zero_ext(vec(old_width-1 downto right_of_dp),
new_width);
else
truncated_val := sign_ext(vec(old_width-1 downto right_of_dp),
new_width);
end if;
else
if new_arith = xlUnsigned then
truncated_val := zero_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
else
truncated_val := sign_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
end if;
end if;
one_or_zero := (others => '0');
if (right_of_dp >= 1) and (right_of_dp <= old_width) then
if (is_point_five(vec(right_of_dp-1 downto 0)) = false) then
one_or_zero(0) := vec(right_of_dp-1);
else
one_or_zero(0) := vec(right_of_dp);
end if;
end if;
if new_arith = xlSigned then
result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) +
std_logic_vector_to_signed(one_or_zero));
else
result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) +
std_logic_vector_to_unsigned(one_or_zero));
end if;
return result;
end;
function saturation_arith(inp: std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith
: INTEGER)
return std_logic_vector
is
constant left_of_dp : integer := (old_width - old_bin_pt) -
(new_width - new_bin_pt);
variable vec : std_logic_vector(old_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
variable overflow : boolean;
begin
vec := inp;
overflow := true;
result := (others => '0');
if (new_width >= old_width) then
overflow := false;
end if;
if ((old_arith = xlSigned and new_arith = xlSigned) and (old_width > new_width)) then
if all_same(vec(old_width-1 downto new_width-1)) then
overflow := false;
end if;
end if;
if (old_arith = xlSigned and new_arith = xlUnsigned) then
if (old_width > new_width) then
if all_zeros(vec(old_width-1 downto new_width)) then
overflow := false;
end if;
else
if (old_width = new_width) then
if (vec(new_width-1) = '0') then
overflow := false;
end if;
end if;
end if;
end if;
if (old_arith = xlUnsigned and new_arith = xlUnsigned) then
if (old_width > new_width) then
if all_zeros(vec(old_width-1 downto new_width)) then
overflow := false;
end if;
else
if (old_width = new_width) then
overflow := false;
end if;
end if;
end if;
if ((old_arith = xlUnsigned and new_arith = xlSigned) and (old_width > new_width)) then
if all_same(vec(old_width-1 downto new_width-1)) then
overflow := false;
end if;
end if;
if overflow then
if new_arith = xlSigned then
if vec(old_width-1) = '0' then
result := max_signed(new_width);
else
result := min_signed(new_width);
end if;
else
if ((old_arith = xlSigned) and vec(old_width-1) = '1') then
result := (others => '0');
else
result := (others => '1');
end if;
end if;
else
if (old_arith = xlSigned) and (new_arith = xlUnsigned) then
if (vec(old_width-1) = '1') then
vec := (others => '0');
end if;
end if;
if new_width <= old_width then
result := vec(new_width-1 downto 0);
else
if new_arith = xlUnsigned then
result := zero_ext(vec, new_width);
else
result := sign_ext(vec, new_width);
end if;
end if;
end if;
return result;
end;
function wrap_arith(inp: std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith : INTEGER)
return std_logic_vector
is
variable result : std_logic_vector(new_width-1 downto 0);
variable result_arith : integer;
begin
if (old_arith = xlSigned) and (new_arith = xlUnsigned) then
result_arith := xlSigned;
end if;
result := cast(inp, old_bin_pt, new_width, new_bin_pt, result_arith);
return result;
end;
function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER is
begin
return max(a_bin_pt, b_bin_pt);
end;
function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER)
return INTEGER is
begin
return max(a_width - a_bin_pt, b_width - b_bin_pt);
end;
function pad_LSB(inp : std_logic_vector; new_width: integer)
return STD_LOGIC_VECTOR
is
constant orig_width : integer := inp'length;
variable vec : std_logic_vector(orig_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
variable pos : integer;
constant pad_pos : integer := new_width - orig_width - 1;
begin
vec := inp;
pos := new_width-1;
if (new_width >= orig_width) then
for i in orig_width-1 downto 0 loop
result(pos) := vec(i);
pos := pos - 1;
end loop;
if pad_pos >= 0 then
for i in pad_pos downto 0 loop
result(i) := '0';
end loop;
end if;
end if;
return result;
end;
function sign_ext(inp : std_logic_vector; new_width : INTEGER)
return std_logic_vector
is
constant old_width : integer := inp'length;
variable vec : std_logic_vector(old_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if new_width >= old_width then
result(old_width-1 downto 0) := vec;
if new_width-1 >= old_width then
for i in new_width-1 downto old_width loop
result(i) := vec(old_width-1);
end loop;
end if;
else
result(new_width-1 downto 0) := vec(new_width-1 downto 0);
end if;
return result;
end;
function zero_ext(inp : std_logic_vector; new_width : INTEGER)
return std_logic_vector
is
constant old_width : integer := inp'length;
variable vec : std_logic_vector(old_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if new_width >= old_width then
result(old_width-1 downto 0) := vec;
if new_width-1 >= old_width then
for i in new_width-1 downto old_width loop
result(i) := '0';
end loop;
end if;
else
result(new_width-1 downto 0) := vec(new_width-1 downto 0);
end if;
return result;
end;
function zero_ext(inp : std_logic; new_width : INTEGER)
return std_logic_vector
is
variable result : std_logic_vector(new_width-1 downto 0);
begin
result(0) := inp;
for i in new_width-1 downto 1 loop
result(i) := '0';
end loop;
return result;
end;
function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER)
return std_logic_vector
is
constant orig_width : integer := inp'length;
variable vec : std_logic_vector(orig_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if arith = xlUnsigned then
result := zero_ext(vec, new_width);
else
result := sign_ext(vec, new_width);
end if;
return result;
end;
function pad_LSB(inp : std_logic_vector; new_width, arith: integer)
return STD_LOGIC_VECTOR
is
constant orig_width : integer := inp'length;
variable vec : std_logic_vector(orig_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
variable pos : integer;
begin
vec := inp;
pos := new_width-1;
if (arith = xlUnsigned) then
result(pos) := '0';
pos := pos - 1;
else
result(pos) := vec(orig_width-1);
pos := pos - 1;
end if;
if (new_width >= orig_width) then
for i in orig_width-1 downto 0 loop
result(pos) := vec(i);
pos := pos - 1;
end loop;
if pos >= 0 then
for i in pos downto 0 loop
result(i) := '0';
end loop;
end if;
end if;
return result;
end;
function align_input(inp : std_logic_vector; old_width, delta, new_arith,
new_width: INTEGER)
return std_logic_vector
is
variable vec : std_logic_vector(old_width-1 downto 0);
variable padded_inp : std_logic_vector((old_width + delta)-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if delta > 0 then
padded_inp := pad_LSB(vec, old_width+delta);
result := extend_MSB(padded_inp, new_width, new_arith);
else
result := extend_MSB(vec, new_width, new_arith);
end if;
return result;
end;
function max(L, R: INTEGER) return INTEGER is
begin
if L > R then
return L;
else
return R;
end if;
end;
function min(L, R: INTEGER) return INTEGER is
begin
if L < R then
return L;
else
return R;
end if;
end;
function "="(left,right: STRING) return boolean is
begin
if (left'length /= right'length) then
return false;
else
test : for i in 1 to left'length loop
if left(i) /= right(i) then
return false;
end if;
end loop test;
return true;
end if;
end;
-- synopsys translate_off
function is_binary_string_invalid (inp : string)
return boolean
is
variable vec : string(1 to inp'length);
variable result : boolean;
begin
vec := inp;
result := false;
for i in 1 to vec'length loop
if ( vec(i) = 'X' ) then
result := true;
end if;
end loop;
return result;
end;
function is_binary_string_undefined (inp : string)
return boolean
is
variable vec : string(1 to inp'length);
variable result : boolean;
begin
vec := inp;
result := false;
for i in 1 to vec'length loop
if ( vec(i) = 'U' ) then
result := true;
end if;
end loop;
return result;
end;
function is_XorU(inp : std_logic_vector)
return boolean
is
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
variable result : boolean;
begin
vec := inp;
result := false;
for i in 0 to width-1 loop
if (vec(i) = 'U') or (vec(i) = 'X') then
result := true;
end if;
end loop;
return result;
end;
function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer)
return real
is
variable vec : std_logic_vector(inp'length-1 downto 0);
variable result, shift_val, undefined_real : real;
variable neg_num : boolean;
begin
vec := inp;
result := 0.0;
neg_num := false;
if vec(inp'length-1) = '1' then
neg_num := true;
end if;
for i in 0 to inp'length-1 loop
if vec(i) = 'U' or vec(i) = 'X' then
return undefined_real;
end if;
if arith = xlSigned then
if neg_num then
if vec(i) = '0' then
result := result + 2.0**i;
end if;
else
if vec(i) = '1' then
result := result + 2.0**i;
end if;
end if;
else
if vec(i) = '1' then
result := result + 2.0**i;
end if;
end if;
end loop;
if arith = xlSigned then
if neg_num then
result := result + 1.0;
result := result * (-1.0);
end if;
end if;
shift_val := 2.0**(-1*bin_pt);
result := result * shift_val;
return result;
end;
function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer)
return real
is
variable result : real := 0.0;
begin
if inp = '1' then
result := 1.0;
end if;
if arith = xlSigned then
assert false
report "It doesn't make sense to convert a 1 bit number to a signed real.";
end if;
return result;
end;
-- synopsys translate_on
function integer_to_std_logic_vector (inp : integer; width, arith : integer)
return std_logic_vector
is
variable result : std_logic_vector(width-1 downto 0);
variable unsigned_val : unsigned(width-1 downto 0);
variable signed_val : signed(width-1 downto 0);
begin
if (arith = xlSigned) then
signed_val := to_signed(inp, width);
result := signed_to_std_logic_vector(signed_val);
else
unsigned_val := to_unsigned(inp, width);
result := unsigned_to_std_logic_vector(unsigned_val);
end if;
return result;
end;
function std_logic_vector_to_integer (inp : std_logic_vector; arith : integer)
return integer
is
constant width : integer := inp'length;
variable unsigned_val : unsigned(width-1 downto 0);
variable signed_val : signed(width-1 downto 0);
variable result : integer;
begin
if (arith = xlSigned) then
signed_val := std_logic_vector_to_signed(inp);
result := to_integer(signed_val);
else
unsigned_val := std_logic_vector_to_unsigned(inp);
result := to_integer(unsigned_val);
end if;
return result;
end;
function std_logic_to_integer(constant inp : std_logic := '0')
return integer
is
begin
if inp = '1' then
return 1;
else
return 0;
end if;
end;
function makeZeroBinStr (width : integer) return STRING is
variable result : string(1 to width+3);
begin
result(1) := '0';
result(2) := 'b';
for i in 3 to width+2 loop
result(i) := '0';
end loop;
result(width+3) := '.';
return result;
end;
-- synopsys translate_off
function real_string_to_std_logic_vector (inp : string; width, bin_pt, arith : integer)
return std_logic_vector
is
variable result : std_logic_vector(width-1 downto 0);
begin
result := (others => '0');
return result;
end;
function real_to_std_logic_vector (inp : real; width, bin_pt, arith : integer)
return std_logic_vector
is
variable real_val : real;
variable int_val : integer;
variable result : std_logic_vector(width-1 downto 0) := (others => '0');
variable unsigned_val : unsigned(width-1 downto 0) := (others => '0');
variable signed_val : signed(width-1 downto 0) := (others => '0');
begin
real_val := inp;
int_val := integer(real_val * 2.0**(bin_pt));
if (arith = xlSigned) then
signed_val := to_signed(int_val, width);
result := signed_to_std_logic_vector(signed_val);
else
unsigned_val := to_unsigned(int_val, width);
result := unsigned_to_std_logic_vector(unsigned_val);
end if;
return result;
end;
-- synopsys translate_on
function valid_bin_string (inp : string)
return boolean
is
variable vec : string(1 to inp'length);
begin
vec := inp;
if (vec(1) = '0' and vec(2) = 'b') then
return true;
else
return false;
end if;
end;
function hex_string_to_std_logic_vector(inp: string; width : integer)
return std_logic_vector is
constant strlen : integer := inp'LENGTH;
variable result : std_logic_vector(width-1 downto 0);
variable bitval : std_logic_vector((strlen*4)-1 downto 0);
variable posn : integer;
variable ch : character;
variable vec : string(1 to strlen);
begin
vec := inp;
result := (others => '0');
posn := (strlen*4)-1;
for i in 1 to strlen loop
ch := vec(i);
case ch is
when '0' => bitval(posn downto posn-3) := "0000";
when '1' => bitval(posn downto posn-3) := "0001";
when '2' => bitval(posn downto posn-3) := "0010";
when '3' => bitval(posn downto posn-3) := "0011";
when '4' => bitval(posn downto posn-3) := "0100";
when '5' => bitval(posn downto posn-3) := "0101";
when '6' => bitval(posn downto posn-3) := "0110";
when '7' => bitval(posn downto posn-3) := "0111";
when '8' => bitval(posn downto posn-3) := "1000";
when '9' => bitval(posn downto posn-3) := "1001";
when 'A' | 'a' => bitval(posn downto posn-3) := "1010";
when 'B' | 'b' => bitval(posn downto posn-3) := "1011";
when 'C' | 'c' => bitval(posn downto posn-3) := "1100";
when 'D' | 'd' => bitval(posn downto posn-3) := "1101";
when 'E' | 'e' => bitval(posn downto posn-3) := "1110";
when 'F' | 'f' => bitval(posn downto posn-3) := "1111";
when others => bitval(posn downto posn-3) := "XXXX";
-- synopsys translate_off
ASSERT false
REPORT "Invalid hex value" SEVERITY ERROR;
-- synopsys translate_on
end case;
posn := posn - 4;
end loop;
if (width <= strlen*4) then
result := bitval(width-1 downto 0);
else
result((strlen*4)-1 downto 0) := bitval;
end if;
return result;
end;
function bin_string_to_std_logic_vector (inp : string)
return std_logic_vector
is
variable pos : integer;
variable vec : string(1 to inp'length);
variable result : std_logic_vector(inp'length-1 downto 0);
begin
vec := inp;
pos := inp'length-1;
result := (others => '0');
for i in 1 to vec'length loop
-- synopsys translate_off
if (pos < 0) and (vec(i) = '0' or vec(i) = '1' or vec(i) = 'X' or vec(i) = 'U') then
assert false
report "Input string is larger than output std_logic_vector. Truncating output.";
return result;
end if;
-- synopsys translate_on
if vec(i) = '0' then
result(pos) := '0';
pos := pos - 1;
end if;
if vec(i) = '1' then
result(pos) := '1';
pos := pos - 1;
end if;
-- synopsys translate_off
if (vec(i) = 'X' or vec(i) = 'U') then
result(pos) := 'U';
pos := pos - 1;
end if;
-- synopsys translate_on
end loop;
return result;
end;
function bin_string_element_to_std_logic_vector (inp : string; width, index : integer)
return std_logic_vector
is
constant str_width : integer := width + 4;
constant inp_len : integer := inp'length;
constant num_elements : integer := (inp_len + 1)/str_width;
constant reverse_index : integer := (num_elements-1) - index;
variable left_pos : integer;
variable right_pos : integer;
variable vec : string(1 to inp'length);
variable result : std_logic_vector(width-1 downto 0);
begin
vec := inp;
result := (others => '0');
if (reverse_index = 0) and (reverse_index < num_elements) and (inp_len-3 >= width) then
left_pos := 1;
right_pos := width + 3;
result := bin_string_to_std_logic_vector(vec(left_pos to right_pos));
end if;
if (reverse_index > 0) and (reverse_index < num_elements) and (inp_len-3 >= width) then
left_pos := (reverse_index * str_width) + 1;
right_pos := left_pos + width + 2;
result := bin_string_to_std_logic_vector(vec(left_pos to right_pos));
end if;
return result;
end;
-- synopsys translate_off
function std_logic_vector_to_bin_string(inp : std_logic_vector)
return string
is
variable vec : std_logic_vector(1 to inp'length);
variable result : string(vec'range);
begin
vec := inp;
for i in vec'range loop
result(i) := to_char(vec(i));
end loop;
return result;
end;
function std_logic_to_bin_string(inp : std_logic)
return string
is
variable result : string(1 to 3);
begin
result(1) := '0';
result(2) := 'b';
result(3) := to_char(inp);
return result;
end;
function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer)
return string
is
variable width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
variable str_pos : integer;
variable result : string(1 to width+3);
begin
vec := inp;
str_pos := 1;
result(str_pos) := '0';
str_pos := 2;
result(str_pos) := 'b';
str_pos := 3;
for i in width-1 downto 0 loop
if (((width+3) - bin_pt) = str_pos) then
result(str_pos) := '.';
str_pos := str_pos + 1;
end if;
result(str_pos) := to_char(vec(i));
str_pos := str_pos + 1;
end loop;
if (bin_pt = 0) then
result(str_pos) := '.';
end if;
return result;
end;
function real_to_bin_string(inp : real; width, bin_pt, arith : integer)
return string
is
variable result : string(1 to width);
variable vec : std_logic_vector(width-1 downto 0);
begin
vec := real_to_std_logic_vector(inp, width, bin_pt, arith);
result := std_logic_vector_to_bin_string(vec);
return result;
end;
function real_to_string (inp : real) return string
is
variable result : string(1 to display_precision) := (others => ' ');
begin
result(real'image(inp)'range) := real'image(inp);
return result;
end;
-- synopsys translate_on
end conv_pkg;
-------------------------------------------------------------------
-- System Generator version 13.2 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
-- synopsys translate_off
library unisim;
use unisim.vcomponents.all;
-- synopsys translate_on
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity srl17e is
generic (width : integer:=16;
latency : integer :=8);
port (clk : in std_logic;
ce : in std_logic;
d : in std_logic_vector(width-1 downto 0);
q : out std_logic_vector(width-1 downto 0));
end srl17e;
architecture structural of srl17e is
component SRL16E
port (D : in STD_ULOGIC;
CE : in STD_ULOGIC;
CLK : in STD_ULOGIC;
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
attribute syn_black_box of SRL16E : component is true;
attribute fpga_dont_touch of SRL16E : component is "true";
component FDE
port(
Q : out STD_ULOGIC;
D : in STD_ULOGIC;
C : in STD_ULOGIC;
CE : in STD_ULOGIC);
end component;
attribute syn_black_box of FDE : component is true;
attribute fpga_dont_touch of FDE : component is "true";
constant a : std_logic_vector(4 downto 0) :=
integer_to_std_logic_vector(latency-2,5,xlSigned);
signal d_delayed : std_logic_vector(width-1 downto 0);
signal srl16_out : std_logic_vector(width-1 downto 0);
begin
d_delayed <= d after 200 ps;
reg_array : for i in 0 to width-1 generate
srl16_used: if latency > 1 generate
u1 : srl16e port map(clk => clk,
d => d_delayed(i),
q => srl16_out(i),
ce => ce,
a0 => a(0),
a1 => a(1),
a2 => a(2),
a3 => a(3));
end generate;
srl16_not_used: if latency <= 1 generate
srl16_out(i) <= d_delayed(i);
end generate;
fde_used: if latency /= 0 generate
u2 : fde port map(c => clk,
d => srl16_out(i),
q => q(i),
ce => ce);
end generate;
fde_not_used: if latency = 0 generate
q(i) <= srl16_out(i);
end generate;
end generate;
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity synth_reg is
generic (width : integer := 8;
latency : integer := 1);
port (i : in std_logic_vector(width-1 downto 0);
ce : in std_logic;
clr : in std_logic;
clk : in std_logic;
o : out std_logic_vector(width-1 downto 0));
end synth_reg;
architecture structural of synth_reg is
component srl17e
generic (width : integer:=16;
latency : integer :=8);
port (clk : in std_logic;
ce : in std_logic;
d : in std_logic_vector(width-1 downto 0);
q : out std_logic_vector(width-1 downto 0));
end component;
function calc_num_srl17es (latency : integer)
return integer
is
variable remaining_latency : integer;
variable result : integer;
begin
result := latency / 17;
remaining_latency := latency - (result * 17);
if (remaining_latency /= 0) then
result := result + 1;
end if;
return result;
end;
constant complete_num_srl17es : integer := latency / 17;
constant num_srl17es : integer := calc_num_srl17es(latency);
constant remaining_latency : integer := latency - (complete_num_srl17es * 17);
type register_array is array (num_srl17es downto 0) of
std_logic_vector(width-1 downto 0);
signal z : register_array;
begin
z(0) <= i;
complete_ones : if complete_num_srl17es > 0 generate
srl17e_array: for i in 0 to complete_num_srl17es-1 generate
delay_comp : srl17e
generic map (width => width,
latency => 17)
port map (clk => clk,
ce => ce,
d => z(i),
q => z(i+1));
end generate;
end generate;
partial_one : if remaining_latency > 0 generate
last_srl17e : srl17e
generic map (width => width,
latency => remaining_latency)
port map (clk => clk,
ce => ce,
d => z(num_srl17es-1),
q => z(num_srl17es));
end generate;
o <= z(num_srl17es);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity synth_reg_reg is
generic (width : integer := 8;
latency : integer := 1);
port (i : in std_logic_vector(width-1 downto 0);
ce : in std_logic;
clr : in std_logic;
clk : in std_logic;
o : out std_logic_vector(width-1 downto 0));
end synth_reg_reg;
architecture behav of synth_reg_reg is
type reg_array_type is array (latency-1 downto 0) of std_logic_vector(width -1 downto 0);
signal reg_bank : reg_array_type := (others => (others => '0'));
signal reg_bank_in : reg_array_type := (others => (others => '0'));
attribute syn_allow_retiming : boolean;
attribute syn_srlstyle : string;
attribute syn_allow_retiming of reg_bank : signal is true;
attribute syn_allow_retiming of reg_bank_in : signal is true;
attribute syn_srlstyle of reg_bank : signal is "registers";
attribute syn_srlstyle of reg_bank_in : signal is "registers";
begin
latency_eq_0: if latency = 0 generate
o <= i;
end generate latency_eq_0;
latency_gt_0: if latency >= 1 generate
o <= reg_bank(latency-1);
reg_bank_in(0) <= i;
loop_gen: for idx in latency-2 downto 0 generate
reg_bank_in(idx+1) <= reg_bank(idx);
end generate loop_gen;
sync_loop: for sync_idx in latency-1 downto 0 generate
sync_proc: process (clk)
begin
if clk'event and clk = '1' then
if clr = '1' then
reg_bank_in <= (others => (others => '0'));
elsif ce = '1' then
reg_bank(sync_idx) <= reg_bank_in(sync_idx);
end if;
end if;
end process sync_proc;
end generate sync_loop;
end generate latency_gt_0;
end behav;
-------------------------------------------------------------------
-- System Generator version 13.2 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
-- synopsys translate_off
library unisim;
use unisim.vcomponents.all;
-- synopsys translate_on
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity single_reg_w_init is
generic (
width: integer := 8;
init_index: integer := 0;
init_value: bit_vector := b"0000"
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end single_reg_w_init;
architecture structural of single_reg_w_init is
function build_init_const(width: integer;
init_index: integer;
init_value: bit_vector)
return std_logic_vector
is
variable result: std_logic_vector(width - 1 downto 0);
begin
if init_index = 0 then
result := (others => '0');
elsif init_index = 1 then
result := (others => '0');
result(0) := '1';
else
result := to_stdlogicvector(init_value);
end if;
return result;
end;
component fdre
port (
q: out std_ulogic;
d: in std_ulogic;
c: in std_ulogic;
ce: in std_ulogic;
r: in std_ulogic
);
end component;
attribute syn_black_box of fdre: component is true;
attribute fpga_dont_touch of fdre: component is "true";
component fdse
port (
q: out std_ulogic;
d: in std_ulogic;
c: in std_ulogic;
ce: in std_ulogic;
s: in std_ulogic
);
end component;
attribute syn_black_box of fdse: component is true;
attribute fpga_dont_touch of fdse: component is "true";
constant init_const: std_logic_vector(width - 1 downto 0)
:= build_init_const(width, init_index, init_value);
begin
fd_prim_array: for index in 0 to width - 1 generate
bit_is_0: if (init_const(index) = '0') generate
fdre_comp: fdre
port map (
c => clk,
d => i(index),
q => o(index),
ce => ce,
r => clr
);
end generate;
bit_is_1: if (init_const(index) = '1') generate
fdse_comp: fdse
port map (
c => clk,
d => i(index),
q => o(index),
ce => ce,
s => clr
);
end generate;
end generate;
end architecture structural;
-- synopsys translate_off
library unisim;
use unisim.vcomponents.all;
-- synopsys translate_on
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity synth_reg_w_init is
generic (
width: integer := 8;
init_index: integer := 0;
init_value: bit_vector := b"0000";
latency: integer := 1
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end synth_reg_w_init;
architecture structural of synth_reg_w_init is
component single_reg_w_init
generic (
width: integer := 8;
init_index: integer := 0;
init_value: bit_vector := b"0000"
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end component;
signal dly_i: std_logic_vector((latency + 1) * width - 1 downto 0);
signal dly_clr: std_logic;
begin
latency_eq_0: if (latency = 0) generate
o <= i;
end generate;
latency_gt_0: if (latency >= 1) generate
dly_i((latency + 1) * width - 1 downto latency * width) <= i
after 200 ps;
dly_clr <= clr after 200 ps;
fd_array: for index in latency downto 1 generate
reg_comp: single_reg_w_init
generic map (
width => width,
init_index => init_index,
init_value => init_value
)
port map (
clk => clk,
i => dly_i((index + 1) * width - 1 downto index * width),
o => dly_i(index * width - 1 downto (index - 1) * width),
ce => ce,
clr => dly_clr
);
end generate;
o <= dly_i(width - 1 downto 0);
end generate;
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant_963ed6358a is
port (
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end constant_963ed6358a;
architecture behavior of constant_963ed6358a is
begin
op <= "0";
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity mcode_block_f4d0462e0e is
port (
plbrst : in std_logic_vector((1 - 1) downto 0);
plbabus : in std_logic_vector((32 - 1) downto 0);
plbpavalid : in std_logic_vector((1 - 1) downto 0);
plbrnw : in std_logic_vector((1 - 1) downto 0);
plbwrdbus : in std_logic_vector((32 - 1) downto 0);
rddata : in std_logic_vector((32 - 1) downto 0);
addrpref : in std_logic_vector((20 - 1) downto 0);
wrdbusreg : out std_logic_vector((32 - 1) downto 0);
addrack : out std_logic_vector((1 - 1) downto 0);
rdcomp : out std_logic_vector((1 - 1) downto 0);
wrdack : out std_logic_vector((1 - 1) downto 0);
bankaddr : out std_logic_vector((2 - 1) downto 0);
rnwreg : out std_logic_vector((1 - 1) downto 0);
rddack : out std_logic_vector((1 - 1) downto 0);
rddbus : out std_logic_vector((32 - 1) downto 0);
linearaddr : out std_logic_vector((8 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end mcode_block_f4d0462e0e;
architecture behavior of mcode_block_f4d0462e0e is
signal plbrst_1_110: unsigned((1 - 1) downto 0);
signal plbabus_1_118: unsigned((32 - 1) downto 0);
signal plbpavalid_1_127: unsigned((1 - 1) downto 0);
signal plbrnw_1_139: unsigned((1 - 1) downto 0);
signal plbwrdbus_1_147: unsigned((32 - 1) downto 0);
signal rddata_1_158: unsigned((32 - 1) downto 0);
signal addrpref_1_166: unsigned((20 - 1) downto 0);
signal plbrstreg_12_24_next: boolean;
signal plbrstreg_12_24: boolean := false;
signal plbabusreg_13_25_next: unsigned((32 - 1) downto 0);
signal plbabusreg_13_25: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000";
signal plbpavalidreg_14_28_next: boolean;
signal plbpavalidreg_14_28: boolean := false;
signal plbrnwreg_15_24_next: unsigned((1 - 1) downto 0);
signal plbrnwreg_15_24: unsigned((1 - 1) downto 0) := "0";
signal plbwrdbusreg_16_27_next: unsigned((32 - 1) downto 0);
signal plbwrdbusreg_16_27: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000";
signal avalidreg_28_23_next: boolean;
signal avalidreg_28_23: boolean := false;
signal ps1reg_39_20_next: boolean;
signal ps1reg_39_20: boolean := false;
signal psreg_47_19_next: boolean;
signal psreg_47_19: boolean := false;
type array_type_rdcompdelay_58_25 is array (0 to (3 - 1)) of unsigned((1 - 1) downto 0);
signal rdcompdelay_58_25: array_type_rdcompdelay_58_25 := (
"0",
"0",
"0");
signal rdcompdelay_58_25_front_din: unsigned((1 - 1) downto 0);
signal rdcompdelay_58_25_back: unsigned((1 - 1) downto 0);
signal rdcompdelay_58_25_push_front_pop_back_en: std_logic;
signal rdcompreg_62_23_next: unsigned((1 - 1) downto 0);
signal rdcompreg_62_23: unsigned((1 - 1) downto 0) := "0";
signal rddackreg_66_23_next: unsigned((1 - 1) downto 0);
signal rddackreg_66_23: unsigned((1 - 1) downto 0) := "0";
signal wrdackreg_70_23_next: unsigned((1 - 1) downto 0);
signal wrdackreg_70_23: unsigned((1 - 1) downto 0) := "0";
signal rddbusreg_84_23_next: unsigned((32 - 1) downto 0);
signal rddbusreg_84_23: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000";
signal bankaddr_20_1_slice: unsigned((2 - 1) downto 0);
signal linearaddr_21_1_slice: unsigned((8 - 1) downto 0);
signal addrpref_in_32_1_slice: unsigned((20 - 1) downto 0);
signal rel_33_4: boolean;
signal ps1_join_33_1: boolean;
signal ps_42_1_bit: boolean;
signal bitnot_49_49: boolean;
signal bitnot_49_73: boolean;
signal bit_49_49: boolean;
signal addrack_49_1_convert: unsigned((1 - 1) downto 0);
signal bit_55_43: unsigned((1 - 1) downto 0);
signal bitnot_72_35: unsigned((1 - 1) downto 0);
signal wrdackreg_72_1_bit: unsigned((1 - 1) downto 0);
signal rdsel_76_1_bit: unsigned((1 - 1) downto 0);
signal rel_78_4: boolean;
signal rddbus1_join_78_1: unsigned((32 - 1) downto 0);
signal plbwrdbusreg_97_1_slice: unsigned((32 - 1) downto 0);
signal plbrstreg_12_24_next_x_000000: boolean;
signal plbpavalidreg_14_28_next_x_000000: boolean;
begin
plbrst_1_110 <= std_logic_vector_to_unsigned(plbrst);
plbabus_1_118 <= std_logic_vector_to_unsigned(plbabus);
plbpavalid_1_127 <= std_logic_vector_to_unsigned(plbpavalid);
plbrnw_1_139 <= std_logic_vector_to_unsigned(plbrnw);
plbwrdbus_1_147 <= std_logic_vector_to_unsigned(plbwrdbus);
rddata_1_158 <= std_logic_vector_to_unsigned(rddata);
addrpref_1_166 <= std_logic_vector_to_unsigned(addrpref);
proc_plbrstreg_12_24: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
plbrstreg_12_24 <= plbrstreg_12_24_next;
end if;
end if;
end process proc_plbrstreg_12_24;
proc_plbabusreg_13_25: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
plbabusreg_13_25 <= plbabusreg_13_25_next;
end if;
end if;
end process proc_plbabusreg_13_25;
proc_plbpavalidreg_14_28: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
plbpavalidreg_14_28 <= plbpavalidreg_14_28_next;
end if;
end if;
end process proc_plbpavalidreg_14_28;
proc_plbrnwreg_15_24: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
plbrnwreg_15_24 <= plbrnwreg_15_24_next;
end if;
end if;
end process proc_plbrnwreg_15_24;
proc_plbwrdbusreg_16_27: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
plbwrdbusreg_16_27 <= plbwrdbusreg_16_27_next;
end if;
end if;
end process proc_plbwrdbusreg_16_27;
proc_avalidreg_28_23: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
avalidreg_28_23 <= avalidreg_28_23_next;
end if;
end if;
end process proc_avalidreg_28_23;
proc_ps1reg_39_20: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
ps1reg_39_20 <= ps1reg_39_20_next;
end if;
end if;
end process proc_ps1reg_39_20;
proc_psreg_47_19: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
psreg_47_19 <= psreg_47_19_next;
end if;
end if;
end process proc_psreg_47_19;
rdcompdelay_58_25_back <= rdcompdelay_58_25(2);
proc_rdcompdelay_58_25: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (rdcompdelay_58_25_push_front_pop_back_en = '1')) then
for i in 2 downto 1 loop
rdcompdelay_58_25(i) <= rdcompdelay_58_25(i-1);
end loop;
rdcompdelay_58_25(0) <= rdcompdelay_58_25_front_din;
end if;
end if;
end process proc_rdcompdelay_58_25;
proc_rdcompreg_62_23: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
rdcompreg_62_23 <= rdcompreg_62_23_next;
end if;
end if;
end process proc_rdcompreg_62_23;
proc_rddackreg_66_23: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
rddackreg_66_23 <= rddackreg_66_23_next;
end if;
end if;
end process proc_rddackreg_66_23;
proc_wrdackreg_70_23: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
wrdackreg_70_23 <= wrdackreg_70_23_next;
end if;
end if;
end process proc_wrdackreg_70_23;
proc_rddbusreg_84_23: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
rddbusreg_84_23 <= rddbusreg_84_23_next;
end if;
end if;
end process proc_rddbusreg_84_23;
bankaddr_20_1_slice <= u2u_slice(plbabusreg_13_25, 11, 10);
linearaddr_21_1_slice <= u2u_slice(plbabusreg_13_25, 9, 2);
addrpref_in_32_1_slice <= u2u_slice(plbabusreg_13_25, 31, 12);
rel_33_4 <= addrpref_in_32_1_slice = addrpref_1_166;
proc_if_33_1: process (rel_33_4)
is
begin
if rel_33_4 then
ps1_join_33_1 <= true;
else
ps1_join_33_1 <= false;
end if;
end process proc_if_33_1;
ps_42_1_bit <= ((boolean_to_vector(ps1_join_33_1) and boolean_to_vector(plbpavalidreg_14_28)) = "1");
bitnot_49_49 <= ((not boolean_to_vector(plbrstreg_12_24)) = "1");
bitnot_49_73 <= ((not boolean_to_vector(psreg_47_19)) = "1");
bit_49_49 <= ((boolean_to_vector(bitnot_49_49) and boolean_to_vector(ps_42_1_bit) and boolean_to_vector(bitnot_49_73)) = "1");
addrack_49_1_convert <= u2u_cast(std_logic_vector_to_unsigned(boolean_to_vector(bit_49_49)), 0, 1, 0);
bit_55_43 <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(addrack_49_1_convert) and unsigned_to_std_logic_vector(plbrnwreg_15_24));
bitnot_72_35 <= std_logic_vector_to_unsigned(not unsigned_to_std_logic_vector(plbrnwreg_15_24));
wrdackreg_72_1_bit <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(addrack_49_1_convert) and unsigned_to_std_logic_vector(bitnot_72_35));
rdsel_76_1_bit <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(rdcompdelay_58_25_back) or unsigned_to_std_logic_vector(rdcompreg_62_23));
rel_78_4 <= rdsel_76_1_bit = std_logic_vector_to_unsigned("1");
proc_if_78_1: process (rddata_1_158, rel_78_4)
is
begin
if rel_78_4 then
rddbus1_join_78_1 <= rddata_1_158;
else
rddbus1_join_78_1 <= std_logic_vector_to_unsigned("00000000000000000000000000000000");
end if;
end process proc_if_78_1;
plbwrdbusreg_97_1_slice <= u2u_slice(plbwrdbus_1_147, 31, 0);
plbrstreg_12_24_next_x_000000 <= (plbrst_1_110 /= "0");
plbrstreg_12_24_next <= plbrstreg_12_24_next_x_000000;
plbabusreg_13_25_next <= plbabus_1_118;
plbpavalidreg_14_28_next_x_000000 <= (plbpavalid_1_127 /= "0");
plbpavalidreg_14_28_next <= plbpavalidreg_14_28_next_x_000000;
plbrnwreg_15_24_next <= plbrnw_1_139;
plbwrdbusreg_16_27_next <= plbwrdbusreg_97_1_slice;
avalidreg_28_23_next <= plbpavalidreg_14_28;
ps1reg_39_20_next <= ps1_join_33_1;
psreg_47_19_next <= ps_42_1_bit;
rdcompdelay_58_25_front_din <= bit_55_43;
rdcompdelay_58_25_push_front_pop_back_en <= '1';
rdcompreg_62_23_next <= rdcompdelay_58_25_back;
rddackreg_66_23_next <= rdcompreg_62_23;
wrdackreg_70_23_next <= wrdackreg_72_1_bit;
rddbusreg_84_23_next <= rddbus1_join_78_1;
wrdbusreg <= unsigned_to_std_logic_vector(plbwrdbusreg_16_27);
addrack <= unsigned_to_std_logic_vector(addrack_49_1_convert);
rdcomp <= unsigned_to_std_logic_vector(rdcompreg_62_23);
wrdack <= unsigned_to_std_logic_vector(wrdackreg_70_23);
bankaddr <= unsigned_to_std_logic_vector(bankaddr_20_1_slice);
rnwreg <= unsigned_to_std_logic_vector(plbrnwreg_15_24);
rddack <= unsigned_to_std_logic_vector(rddackreg_66_23);
rddbus <= unsigned_to_std_logic_vector(rddbusreg_84_23);
linearaddr <= unsigned_to_std_logic_vector(linearaddr_21_1_slice);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity mcode_block_189a35de81 is
port (
wrdbus : in std_logic_vector((32 - 1) downto 0);
bankaddr : in std_logic_vector((2 - 1) downto 0);
linearaddr : in std_logic_vector((8 - 1) downto 0);
rnwreg : in std_logic_vector((1 - 1) downto 0);
addrack : in std_logic_vector((1 - 1) downto 0);
read_bank_out : out std_logic_vector((32 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end mcode_block_189a35de81;
architecture behavior of mcode_block_189a35de81 is
signal wrdbus_1_39: unsigned((32 - 1) downto 0);
signal bankaddr_1_47: unsigned((2 - 1) downto 0);
signal linearaddr_1_57: unsigned((8 - 1) downto 0);
signal rnwreg_1_69: unsigned((1 - 1) downto 0);
signal addrack_1_77: unsigned((1 - 1) downto 0);
signal read_bank_out_reg_53_31_next: unsigned((32 - 1) downto 0);
signal read_bank_out_reg_53_31: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000";
signal bankaddr_reg_56_26_next: unsigned((2 - 1) downto 0);
signal bankaddr_reg_56_26: unsigned((2 - 1) downto 0) := "00";
signal opcode_21_1_concat: unsigned((12 - 1) downto 0);
signal rel_58_4: boolean;
signal rel_61_8: boolean;
signal rel_64_8: boolean;
signal rel_67_8: boolean;
signal read_bank_out_reg_join_58_1: unsigned((32 - 1) downto 0);
begin
wrdbus_1_39 <= std_logic_vector_to_unsigned(wrdbus);
bankaddr_1_47 <= std_logic_vector_to_unsigned(bankaddr);
linearaddr_1_57 <= std_logic_vector_to_unsigned(linearaddr);
rnwreg_1_69 <= std_logic_vector_to_unsigned(rnwreg);
addrack_1_77 <= std_logic_vector_to_unsigned(addrack);
proc_read_bank_out_reg_53_31: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
read_bank_out_reg_53_31 <= read_bank_out_reg_53_31_next;
end if;
end if;
end process proc_read_bank_out_reg_53_31;
proc_bankaddr_reg_56_26: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
bankaddr_reg_56_26 <= bankaddr_reg_56_26_next;
end if;
end if;
end process proc_bankaddr_reg_56_26;
opcode_21_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(addrack_1_77) & unsigned_to_std_logic_vector(rnwreg_1_69) & unsigned_to_std_logic_vector(bankaddr_1_47) & unsigned_to_std_logic_vector(linearaddr_1_57));
rel_58_4 <= bankaddr_reg_56_26 = std_logic_vector_to_unsigned("00");
rel_61_8 <= bankaddr_reg_56_26 = std_logic_vector_to_unsigned("01");
rel_64_8 <= bankaddr_reg_56_26 = std_logic_vector_to_unsigned("10");
rel_67_8 <= bankaddr_reg_56_26 = std_logic_vector_to_unsigned("11");
proc_if_58_1: process (read_bank_out_reg_53_31, rel_58_4, rel_61_8, rel_64_8, rel_67_8)
is
begin
if rel_58_4 then
read_bank_out_reg_join_58_1 <= std_logic_vector_to_unsigned("00000000000000000000000000000000");
elsif rel_61_8 then
read_bank_out_reg_join_58_1 <= std_logic_vector_to_unsigned("00000000000000000000000000000000");
elsif rel_64_8 then
read_bank_out_reg_join_58_1 <= std_logic_vector_to_unsigned("00000000000000000000000000000000");
elsif rel_67_8 then
read_bank_out_reg_join_58_1 <= std_logic_vector_to_unsigned("00000000000000000000000000000000");
else
read_bank_out_reg_join_58_1 <= read_bank_out_reg_53_31;
end if;
end process proc_if_58_1;
read_bank_out_reg_53_31_next <= read_bank_out_reg_join_58_1;
bankaddr_reg_56_26_next <= bankaddr_1_47;
read_bank_out <= unsigned_to_std_logic_vector(read_bank_out_reg_53_31);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity concat_d0d1b9533e is
port (
in0 : in std_logic_vector((8 - 1) downto 0);
in1 : in std_logic_vector((8 - 1) downto 0);
in2 : in std_logic_vector((8 - 1) downto 0);
y : out std_logic_vector((24 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end concat_d0d1b9533e;
architecture behavior of concat_d0d1b9533e is
signal in0_1_23: unsigned((8 - 1) downto 0);
signal in1_1_27: unsigned((8 - 1) downto 0);
signal in2_1_31: unsigned((8 - 1) downto 0);
signal y_2_1_concat: unsigned((24 - 1) downto 0);
begin
in0_1_23 <= std_logic_vector_to_unsigned(in0);
in1_1_27 <= std_logic_vector_to_unsigned(in1);
in2_1_31 <= std_logic_vector_to_unsigned(in2);
y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27) & unsigned_to_std_logic_vector(in2_1_31));
y <= unsigned_to_std_logic_vector(y_2_1_concat);
end behavior;
-------------------------------------------------------------------
-- System Generator version 13.2 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity xlregister is
generic (d_width : integer := 5;
init_value : bit_vector := b"00");
port (d : in std_logic_vector (d_width-1 downto 0);
rst : in std_logic_vector(0 downto 0) := "0";
en : in std_logic_vector(0 downto 0) := "1";
ce : in std_logic;
clk : in std_logic;
q : out std_logic_vector (d_width-1 downto 0));
end xlregister;
architecture behavior of xlregister is
component synth_reg_w_init
generic (width : integer;
init_index : integer;
init_value : bit_vector;
latency : integer);
port (i : in std_logic_vector(width-1 downto 0);
ce : in std_logic;
clr : in std_logic;
clk : in std_logic;
o : out std_logic_vector(width-1 downto 0));
end component;
-- synopsys translate_off
signal real_d, real_q : real;
-- synopsys translate_on
signal internal_clr : std_logic;
signal internal_ce : std_logic;
begin
internal_clr <= rst(0) and ce;
internal_ce <= en(0) and ce;
synth_reg_inst : synth_reg_w_init
generic map (width => d_width,
init_index => 2,
init_value => init_value,
latency => 1)
port map (i => d,
ce => internal_ce,
clr => internal_clr,
clk => clk,
o => q);
end architecture behavior;
-------------------------------------------------------------------
-- System Generator version 13.2 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.conv_pkg.all;
entity xlslice is
generic (
new_msb : integer := 9;
new_lsb : integer := 1;
x_width : integer := 16;
y_width : integer := 8);
port (
x : in std_logic_vector (x_width-1 downto 0);
y : out std_logic_vector (y_width-1 downto 0));
end xlslice;
architecture behavior of xlslice is
begin
y <= x(new_msb downto new_lsb);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "sg_xsvi_fanin/EDK Processor"
entity edk_processor_entity_a5d11af1bf is
port (
plb_abus: in std_logic_vector(31 downto 0);
plb_ce_1: in std_logic;
plb_clk_1: in std_logic;
plb_pavalid: in std_logic;
plb_rnw: in std_logic;
plb_wrdbus: in std_logic_vector(31 downto 0);
sg_plb_addrpref: in std_logic_vector(19 downto 0);
splb_rst: in std_logic;
constant5_x0: out std_logic;
plb_decode_x0: out std_logic;
plb_decode_x1: out std_logic;
plb_decode_x2: out std_logic;
plb_decode_x3: out std_logic;
plb_decode_x4: out std_logic_vector(31 downto 0)
);
end edk_processor_entity_a5d11af1bf;
architecture structural of edk_processor_entity_a5d11af1bf is
signal bankaddr: std_logic_vector(1 downto 0);
signal linearaddr: std_logic_vector(7 downto 0);
signal plb_abus_net_x0: std_logic_vector(31 downto 0);
signal plb_ce_1_sg_x0: std_logic;
signal plb_clk_1_sg_x0: std_logic;
signal plb_pavalid_net_x0: std_logic;
signal plb_rnw_net_x0: std_logic;
signal plb_wrdbus_net_x0: std_logic_vector(31 downto 0);
signal rddata: std_logic_vector(31 downto 0);
signal rnwreg: std_logic;
signal sg_plb_addrpref_net_x0: std_logic_vector(19 downto 0);
signal sl_addrack_x0: std_logic;
signal sl_rdcomp_x0: std_logic;
signal sl_rddack_x0: std_logic;
signal sl_rddbus_x0: std_logic_vector(31 downto 0);
signal sl_wait_x0: std_logic;
signal sl_wrdack_x0: std_logic;
signal splb_rst_net_x0: std_logic;
signal wrdbusreg: std_logic_vector(31 downto 0);
begin
plb_abus_net_x0 <= plb_abus;
plb_ce_1_sg_x0 <= plb_ce_1;
plb_clk_1_sg_x0 <= plb_clk_1;
plb_pavalid_net_x0 <= plb_pavalid;
plb_rnw_net_x0 <= plb_rnw;
plb_wrdbus_net_x0 <= plb_wrdbus;
sg_plb_addrpref_net_x0 <= sg_plb_addrpref;
splb_rst_net_x0 <= splb_rst;
constant5_x0 <= sl_wait_x0;
plb_decode_x0 <= sl_addrack_x0;
plb_decode_x1 <= sl_rdcomp_x0;
plb_decode_x2 <= sl_wrdack_x0;
plb_decode_x3 <= sl_rddack_x0;
plb_decode_x4 <= sl_rddbus_x0;
constant5: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => sl_wait_x0
);
plb_decode: entity work.mcode_block_f4d0462e0e
port map (
addrpref => sg_plb_addrpref_net_x0,
ce => plb_ce_1_sg_x0,
clk => plb_clk_1_sg_x0,
clr => '0',
plbabus => plb_abus_net_x0,
plbpavalid(0) => plb_pavalid_net_x0,
plbrnw(0) => plb_rnw_net_x0,
plbrst(0) => splb_rst_net_x0,
plbwrdbus => plb_wrdbus_net_x0,
rddata => rddata,
addrack(0) => sl_addrack_x0,
bankaddr => bankaddr,
linearaddr => linearaddr,
rdcomp(0) => sl_rdcomp_x0,
rddack(0) => sl_rddack_x0,
rddbus => sl_rddbus_x0,
rnwreg(0) => rnwreg,
wrdack(0) => sl_wrdack_x0,
wrdbusreg => wrdbusreg
);
plb_memmap: entity work.mcode_block_189a35de81
port map (
addrack(0) => sl_addrack_x0,
bankaddr => bankaddr,
ce => plb_ce_1_sg_x0,
clk => plb_clk_1_sg_x0,
clr => '0',
linearaddr => linearaddr,
rnwreg(0) => rnwreg,
wrdbus => wrdbusreg,
read_bank_out => rddata
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "sg_xsvi_fanin"
entity sg_xsvi_fanin is
port (
active_video_i: in std_logic;
ce_1: in std_logic;
clk_1: in std_logic;
hblank_i: in std_logic;
hsync_i: in std_logic;
plb_abus: in std_logic_vector(31 downto 0);
plb_ce_1: in std_logic;
plb_clk_1: in std_logic;
plb_pavalid: in std_logic;
plb_rnw: in std_logic;
plb_wrdbus: in std_logic_vector(31 downto 0);
sg_plb_addrpref: in std_logic_vector(19 downto 0);
splb_rst: in std_logic;
vblank_i: in std_logic;
video_data_i: in std_logic_vector(23 downto 0);
vsync_i: in std_logic;
active_video_o: out std_logic;
hblank_o: out std_logic;
hsync_o: out std_logic;
sl_addrack: out std_logic;
sl_rdcomp: out std_logic;
sl_rddack: out std_logic;
sl_rddbus: out std_logic_vector(31 downto 0);
sl_wait: out std_logic;
sl_wrcomp: out std_logic;
sl_wrdack: out std_logic;
vblank_o: out std_logic;
video_data_o: out std_logic_vector(23 downto 0);
vsync_o: out std_logic
);
end sg_xsvi_fanin;
architecture structural of sg_xsvi_fanin is
attribute core_generation_info: string;
attribute core_generation_info of structural : architecture is "sg_xsvi_fanin,sysgen_core,{clock_period=10.00000000,clocking=Clock_Enables,sample_periods=1.00000000000 1.00000000000,testbench=0,total_blocks=102,xilinx_bit_slice_extractor_block=3,xilinx_bus_concatenator_block=1,xilinx_constant_block_block=1,xilinx_edk_processor_block=1,xilinx_gateway_in_block=12,xilinx_gateway_out_block=13,xilinx_mcode_block_block=2,xilinx_register_block=8,xilinx_system_generator_block=1,}";
signal active_video_i_net: std_logic;
signal active_video_o_net: std_logic;
signal blue: std_logic_vector(7 downto 0);
signal ce_1_sg_x0: std_logic;
signal clk_1_sg_x0: std_logic;
signal green: std_logic_vector(7 downto 0);
signal hblank_i_net: std_logic;
signal hblank_o_net: std_logic;
signal hsync_i_net: std_logic;
signal hsync_o_net: std_logic;
signal plb_abus_net: std_logic_vector(31 downto 0);
signal plb_ce_1_sg_x1: std_logic;
signal plb_clk_1_sg_x1: std_logic;
signal plb_pavalid_net: std_logic;
signal plb_rnw_net: std_logic;
signal plb_wrdbus_net: std_logic_vector(31 downto 0);
signal red: std_logic_vector(7 downto 0);
signal register5_q_net: std_logic_vector(7 downto 0);
signal register6_q_net: std_logic_vector(7 downto 0);
signal register7_q_net: std_logic_vector(7 downto 0);
signal sg_plb_addrpref_net: std_logic_vector(19 downto 0);
signal sl_addrack_net: std_logic;
signal sl_rdcomp_net: std_logic;
signal sl_rddack_net: std_logic;
signal sl_rddbus_net: std_logic_vector(31 downto 0);
signal sl_wait_net: std_logic;
signal sl_wrdack_x1: std_logic;
signal splb_rst_net: std_logic;
signal vblank_i_net: std_logic;
signal vblank_o_net: std_logic;
signal video_data_i_net: std_logic_vector(23 downto 0);
signal video_data_o_net: std_logic_vector(23 downto 0);
signal vsync_i_net: std_logic;
signal vsync_o_net: std_logic;
begin
active_video_i_net <= active_video_i;
ce_1_sg_x0 <= ce_1;
clk_1_sg_x0 <= clk_1;
hblank_i_net <= hblank_i;
hsync_i_net <= hsync_i;
plb_abus_net <= plb_abus;
plb_ce_1_sg_x1 <= plb_ce_1;
plb_clk_1_sg_x1 <= plb_clk_1;
plb_pavalid_net <= plb_pavalid;
plb_rnw_net <= plb_rnw;
plb_wrdbus_net <= plb_wrdbus;
sg_plb_addrpref_net <= sg_plb_addrpref;
splb_rst_net <= splb_rst;
vblank_i_net <= vblank_i;
video_data_i_net <= video_data_i;
vsync_i_net <= vsync_i;
active_video_o <= active_video_o_net;
hblank_o <= hblank_o_net;
hsync_o <= hsync_o_net;
sl_addrack <= sl_addrack_net;
sl_rdcomp <= sl_rdcomp_net;
sl_rddack <= sl_rddack_net;
sl_rddbus <= sl_rddbus_net;
sl_wait <= sl_wait_net;
sl_wrcomp <= sl_wrdack_x1;
sl_wrdack <= sl_wrdack_x1;
vblank_o <= vblank_o_net;
video_data_o <= video_data_o_net;
vsync_o <= vsync_o_net;
concat: entity work.concat_d0d1b9533e
port map (
ce => '0',
clk => '0',
clr => '0',
in0 => register5_q_net,
in1 => register6_q_net,
in2 => register7_q_net,
y => video_data_o_net
);
edk_processor_a5d11af1bf: entity work.edk_processor_entity_a5d11af1bf
port map (
plb_abus => plb_abus_net,
plb_ce_1 => plb_ce_1_sg_x1,
plb_clk_1 => plb_clk_1_sg_x1,
plb_pavalid => plb_pavalid_net,
plb_rnw => plb_rnw_net,
plb_wrdbus => plb_wrdbus_net,
sg_plb_addrpref => sg_plb_addrpref_net,
splb_rst => splb_rst_net,
constant5_x0 => sl_wait_net,
plb_decode_x0 => sl_addrack_net,
plb_decode_x1 => sl_rdcomp_net,
plb_decode_x2 => sl_wrdack_x1,
plb_decode_x3 => sl_rddack_net,
plb_decode_x4 => sl_rddbus_net
);
register1: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
d(0) => vsync_i_net,
en => "1",
rst => "0",
q(0) => vsync_o_net
);
register2: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
d(0) => hsync_i_net,
en => "1",
rst => "0",
q(0) => hsync_o_net
);
register3: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
d(0) => vblank_i_net,
en => "1",
rst => "0",
q(0) => vblank_o_net
);
register4: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
d(0) => hblank_i_net,
en => "1",
rst => "0",
q(0) => hblank_o_net
);
register5: entity work.xlregister
generic map (
d_width => 8,
init_value => b"00000000"
)
port map (
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
d => red,
en => "1",
rst => "0",
q => register5_q_net
);
register6: entity work.xlregister
generic map (
d_width => 8,
init_value => b"00000000"
)
port map (
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
d => green,
en => "1",
rst => "0",
q => register6_q_net
);
register7: entity work.xlregister
generic map (
d_width => 8,
init_value => b"00000000"
)
port map (
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
d => blue,
en => "1",
rst => "0",
q => register7_q_net
);
register_x0: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
d(0) => active_video_i_net,
en => "1",
rst => "0",
q(0) => active_video_o_net
);
slice15downto8: entity work.xlslice
generic map (
new_lsb => 8,
new_msb => 15,
x_width => 24,
y_width => 8
)
port map (
x => video_data_i_net,
y => green
);
slice23downto16: entity work.xlslice
generic map (
new_lsb => 16,
new_msb => 23,
x_width => 24,
y_width => 8
)
port map (
x => video_data_i_net,
y => red
);
slice7downto0: entity work.xlslice
generic map (
new_lsb => 0,
new_msb => 7,
x_width => 24,
y_width => 8
)
port map (
x => video_data_i_net,
y => blue
);
end structural;
| gpl-3.0 | a0bfd226981fce4b76681edefaa8fd7d | 0.572883 | 3.562189 | false | false | false | false |
Alabamajack/Garfield | FPGA_Design/ip_intern/Rotary_Encoder/rotary_encoder_avalon.vhd | 1 | 4,850 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity rotary_encoder_avalon is
generic(
datawidth : natural := 32
);
port(
-- ! avalon clk interface
clk : in std_logic;
-- ! avalon reset interface
rst : in std_logic;
-- ! avalon MM interface
address : in std_logic_vector(0 downto 0);
read, write, chipselect : in std_logic;
writedata : in std_logic_vector(datawidth - 1 downto 0);
readdata : out std_logic_vector(datawidth - 1 downto 0);
waitrequest : out std_logic;
-- ! avalon input interface
rotary_signal : in std_logic
);
end entity rotary_encoder_avalon;
architecture RTL of rotary_encoder_avalon is
-- --------------------------------------
-- constants
-- --------------------------------------
constant bit_enable_pos : natural := 0;
constant bit_clearcounter_pos : natural := 1;
constant bit_resetcore_pos : natural := 2;
constant bit_countererror_pos : natural := 16;
-- --------------------------------------
-- signals
-- --------------------------------------
signal datavalid_write : boolean := false;
signal reset_int : std_logic;
signal clear_counter : std_logic;
signal enable : std_logic;
signal counter : std_logic_vector(datawidth - 1 downto 0);
signal counter_error : boolean;
-- --------------------------------------
-- signals as registers
-- --------------------------------------
signal control_register_path : std_logic_vector(datawidth/2 - 1 downto 0) := (others => '0');
signal status_register_path : std_logic_vector(datawidth/2 - 1 downto 0) := (others => '0');
signal control_status_register : std_logic_vector(datawidth - 1 downto 0);
-- --------------------------------------
-- components
-- --------------------------------------
component rotary_encoder
generic(
core_frequency : natural := 100_000_000;
counter_width : natural := 32
);
port(
clk : in std_logic;
rst : in std_logic;
clear_counter : in std_logic;
enable : in std_logic;
counter : out std_logic_vector(counter_width - 1 downto 0);
counter_error : out boolean;
rotary_signal : in std_logic
);
end component rotary_encoder;
begin
-- --------------------------------------
-- components instantiations
-- --------------------------------------
rotary_enc_inst : rotary_encoder
generic map(
core_frequency => 100_000_000,
counter_width => datawidth
)
port map(
clk => clk,
rst => rst,
clear_counter => clear_counter,
enable => enable,
counter => counter,
counter_error => counter_error,
rotary_signal => rotary_signal
);
-- --------------------------------------
-- concurrent statements
-- --------------------------------------
control_status_register <= status_register_path & control_register_path;
reset_int <= rst or control_register_path(bit_resetcore_pos);
waitrequest <= '1' when (write = '1' and chipselect = '1') and not datavalid_write else '0';
status_register_path(bit_countererror_pos - datawidth/2) <= '1' when counter_error else '0';
enable <= control_register_path(bit_enable_pos);
clear_counter <= control_register_path(bit_clearcounter_pos);
-- --------------------------------------
-- processes
-- --------------------------------------
write_proc : process(clk) is
begin
if rising_edge(clk) then
control_register_path(bit_clearcounter_pos) <= '0';
datavalid_write <= false;
if reset_int = '1' then
control_register_path <= (others => '0');
elsif chipselect = '1' and write = '1' then
case address is
when "0" => -- the control register; base address 0x00
control_register_path(bit_enable_pos) <= writedata(bit_enable_pos);
control_register_path(bit_clearcounter_pos) <= writedata(bit_clearcounter_pos);
control_register_path(bit_resetcore_pos) <= writedata(bit_resetcore_pos);
when "1" => -- the result register, there is no write allowed; base address 0x04
null;
when others =>
null;
end case;
datavalid_write <= true;
else
null;
end if;
end if;
end process write_proc;
read_proc : process(address, chipselect, control_status_register, counter, read) is
begin
readdata <= (others => '0');
if chipselect = '1' and read = '1' then
case address is
when "0" => -- control/status register
readdata <= control_status_register;
when "1" => -- result register
readdata <= counter;
when others => null;
end case;
end if;
end process read_proc;
end architecture RTL;
| gpl-3.0 | 3e35a2f09a479c51c9e5e17ddab5af8a | 0.543093 | 3.765528 | false | false | false | false |
Alabamajack/Garfield | FPGA_Design/ip_intern/PWM_Generator/tb/pwm_generator_tb.vhdl | 1 | 1,219 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pwm_generator_tb is
end entity pwm_generator_tb;
architecture RTL of pwm_generator_tb is
constant width : natural := 8;
constant freq_pwm : integer := 100_000_000;
constant freq_clock : integer := 10_000;
signal clk : std_logic;
signal pwmvalue : std_logic_vector(width - 1 downto 0);
signal pwmout : std_logic;
begin
clock_driver : process
constant period : time := 10 ns;
begin
clk <= '0';
wait for period / 2;
clk <= '1';
wait for period / 2;
end process clock_driver;
inst : entity work.pwm_generator
generic map(
width => width,
freq_clock => freq_clock,
freq_pwm => freq_pwm
)
port map(
clk => clk,
pwmvalue => pwmvalue,
pwmout => pwmout
);
stim_proc : process is
begin
pwmvalue <= (others => '0');
wait for 10 ms;
pwmvalue <= std_logic_vector(to_unsigned(100, width));
wait for 100 ms;
pwmvalue <= std_logic_vector(to_unsigned(254, width));
wait for 100 ms;
pwmvalue <= std_logic_vector(to_unsigned(255, width));
wait for 100 ms;
pwmvalue <= std_logic_vector(to_unsigned(10, width));
wait;
end process stim_proc;
end architecture RTL;
| gpl-3.0 | 2a395adbf18a7a832d3fe712475315cb | 0.655455 | 2.965937 | false | false | false | false |
GSimas/EEL5105 | AULA9/reg4.vhd | 2 | 406 | library ieee;
use ieee.std_logic_1164.all;
entity D_4FF is port (
CLK, RST: in std_logic;
EN: in std_logic;
D: in std_logic_vector(3 downto 0);
Q: out std_logic_vector(3 downto 0)
);
end D_4FF;
architecture behv of D_4FF is
begin
process(CLK, D, RST)
begin
if RST = '0' then
Q <= "0000";
elsif (CLK'event and CLK = '1') then
if EN = '1' then
Q <= D;
end if;
end if;
end process;
end behv; | mit | 6056713bff34db707656657563545417 | 0.640394 | 2.346821 | false | false | false | false |
hoglet67/AtomFpga | src/common/ICET65/MOS6502CpuMonCore.vhd | 1 | 14,013 | ------------------------------------------------------------------------------
-- Copyright (c) 2019 David Banks
--
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ /
-- \ \ \/
-- \ \
-- / / Filename : MOS6502CpuMonCore.vhd
-- /___/ /\ Timestamp : 3/11/2019
-- \ \ / \
-- \___\/\___\
--
--Design Name: MOS6502CpuMonCore
--Device: multiple
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity MOS6502CpuMonCore is
generic (
UseT65Core : boolean;
UseAlanDCore : boolean;
-- default sizing is used by Electron/Beeb Fpga
num_comparators : integer := 8;
avr_prog_mem_size : integer := 1024 * 8;
filename : string
);
port (
clock_avr : in std_logic;
busmon_clk : in std_logic;
busmon_clken : in std_logic;
cpu_clk : in std_logic;
cpu_clken : in std_logic;
-- 6502 Signals
IRQ_n : in std_logic;
NMI_n : in std_logic;
Sync : out std_logic;
Addr : out std_logic_vector(15 downto 0);
R_W_n : out std_logic;
Din : in std_logic_vector(7 downto 0);
Dout : out std_logic_vector(7 downto 0);
SO_n : in std_logic;
Res_n : in std_logic;
Rdy : in std_logic;
-- External trigger inputs
trig : in std_logic_vector(1 downto 0);
-- Serial Console
avr_RxD : in std_logic;
avr_TxD : out std_logic;
-- Switches
sw_reset_cpu : in std_logic;
sw_reset_avr : in std_logic;
-- LEDs
led_bkpt : out std_logic;
led_trig0 : out std_logic;
led_trig1 : out std_logic
);
end MOS6502CpuMonCore;
architecture behavioral of MOS6502CpuMonCore is
type state_type is (idle, nop0, nop1, rd, wr, exec1, exec2);
signal state : state_type;
signal cpu_clken_ss : std_logic;
signal Data : std_logic_vector(7 downto 0);
signal Din_int : std_logic_vector(7 downto 0);
signal Dout_int : std_logic_vector(7 downto 0);
signal R_W_n_int : std_logic;
signal Rd_n_int : std_logic;
signal Wr_n_int : std_logic;
signal Sync_int : std_logic;
signal Addr_int : std_logic_vector(23 downto 0);
signal cpu_addr_us : unsigned (15 downto 0);
signal cpu_dout_us : unsigned (7 downto 0);
signal cpu_reset_n : std_logic;
signal Regs : std_logic_vector(63 downto 0);
signal Regs1 : std_logic_vector(255 downto 0);
signal last_PC : std_logic_vector(15 downto 0);
signal SS_Single : std_logic;
signal SS_Step : std_logic;
signal SS_Step_held : std_logic;
signal CountCycle : std_logic;
signal special : std_logic_vector(1 downto 0);
signal memory_rd : std_logic;
signal memory_rd1 : std_logic;
signal memory_wr : std_logic;
signal memory_wr1 : std_logic;
signal memory_addr : std_logic_vector(15 downto 0);
signal memory_dout : std_logic_vector(7 downto 0);
signal memory_din : std_logic_vector(7 downto 0);
signal memory_done : std_logic;
signal NMI_n_masked : std_logic;
signal IRQ_n_masked : std_logic;
signal exec : std_logic;
signal exec_held : std_logic;
signal op3 : std_logic;
begin
mon : entity work.BusMonCore
generic map (
num_comparators => num_comparators,
avr_prog_mem_size => avr_prog_mem_size,
filename => filename
)
port map (
clock_avr => clock_avr,
busmon_clk => busmon_clk,
busmon_clken => busmon_clken,
cpu_clk => cpu_clk,
cpu_clken => cpu_clken,
Addr => Addr_int(15 downto 0),
Data => Data,
Rd_n => Rd_n_int,
Wr_n => Wr_n_int,
RdIO_n => '1',
WrIO_n => '1',
Sync => Sync_int,
Rdy => open,
nRSTin => Res_n,
nRSTout => cpu_reset_n,
CountCycle => CountCycle,
trig => trig,
avr_RxD => avr_RxD,
avr_TxD => avr_TxD,
sw_reset_cpu => sw_reset_cpu,
sw_reset_avr => sw_reset_avr,
led_bkpt => led_bkpt,
led_trig0 => led_trig0,
led_trig1 => led_trig1,
Regs => Regs1,
RdMemOut => memory_rd,
WrMemOut => memory_wr,
RdIOOut => open,
WrIOOut => open,
ExecOut => exec,
AddrOut => memory_addr,
DataOut => memory_dout,
DataIn => memory_din,
Done => memory_done,
Special => special,
SS_Step => SS_Step,
SS_Single => SS_Single
);
Wr_n_int <= R_W_n_int;
Rd_n_int <= not R_W_n_int;
Data <= Din when R_W_n_int = '1' else Dout_int;
NMI_n_masked <= NMI_n or special(1);
IRQ_n_masked <= IRQ_n or special(0);
-- The CPU is slightly pipelined and the register update of the last
-- instruction overlaps with the opcode fetch of the next instruction.
--
-- If the single stepping stopped on the opcode fetch cycle, then the registers
-- valued would not accurately reflect the previous instruction.
--
-- To work around this, when single stepping, we stop on the cycle after
-- the opcode fetch, which means the program counter has advanced.
--
-- To hide this from the user single stepping, all we need to do is to
-- also pipeline the value of the program counter by one stage to compensate.
last_pc_gen : process(cpu_clk)
begin
if rising_edge(cpu_clk) then
if cpu_clken = '1' then
if state = idle then
last_PC <= Regs(63 downto 48);
end if;
end if;
end if;
end process;
Regs1( 47 downto 0) <= Regs( 47 downto 0);
Regs1( 63 downto 48) <= last_PC;
Regs1(255 downto 64) <= (others => '0');
cpu_clken_ss <= '1' when Rdy = '1' and (state = idle or state = exec1 or state = exec2) and cpu_clken = '1' else '0';
GenT65Core: if UseT65Core generate
inst_t65: entity work.T65 port map (
mode => "00",
Abort_n => '1',
SO_n => SO_n,
Res_n => cpu_reset_n,
Enable => cpu_clken_ss,
Clk => cpu_clk,
Rdy => '1',
IRQ_n => IRQ_n_masked,
NMI_n => NMI_n_masked,
R_W_n => R_W_n_int,
Sync => Sync_int,
A => Addr_int,
DI => Din_int,
DO => Dout_int,
Regs => Regs
);
end generate;
GenAlanDCore: if UseAlanDCore generate
inst_r65c02: entity work.r65c02 port map (
reset => cpu_reset_n,
clk => cpu_clk,
enable => cpu_clken_ss,
nmi_n => NMI_n_masked,
irq_n => IRQ_n_masked,
di => unsigned(Din_int),
do => cpu_dout_us,
addr => cpu_addr_us,
nwe => R_W_n_int,
sync => Sync_int,
sync_irq => open,
Regs => Regs
);
Dout_int <= std_logic_vector(cpu_dout_us);
Addr_int(15 downto 0) <= std_logic_vector(cpu_addr_us);
end generate;
-- 00 IMP, INDX, IMP, IMP, ZP, ZP, ZP, IMP, IMP, IMM, IMPA, IMP, ABS, ABS, ABS, IMP,
-- 10 BRA, INDY, IND, IMP, ZP, ZPX, ZPX, IMP, IMP, ABSY, IMPA, IMP, ABS, ABSX, ABSX, IMP,
-- 20 ABS, INDX, IMP, IMP, ZP, ZP, ZP, IMP, IMP, IMM, IMPA, IMP, ABS, ABS, ABS, IMP,
-- 30 BRA, INDY, IND, IMP, ZPX, ZPX, ZPX, IMP, IMP, ABSY, IMPA, IMP, ABSX, ABSX, ABSX, IMP,
-- 40 IMP, INDX, IMP, IMP, ZP, ZP, ZP, IMP, IMP, IMM, IMPA, IMP, ABS, ABS, ABS, IMP,
-- 50 BRA, INDY, IND, IMP, ZP, ZPX, ZPX, IMP, IMP, ABSY, IMP, IMP, ABS, ABSX, ABSX, IMP,
-- 60 IMP, INDX, IMP, IMP, ZP, ZP, ZP, IMP, IMP, IMM, IMPA, IMP, IND16, ABS, ABS, IMP,
-- 70 BRA, INDY, IND, IMP, ZPX, ZPX, ZPX, IMP, IMP, ABSY, IMP, IMP, IND1X, ABSX, ABSX, IMP,
-- 80 BRA, INDX, IMP, IMP, ZP, ZP, ZP, IMP, IMP, IMM, IMP, IMP, ABS, ABS, ABS, IMP,
-- 90 BRA, INDY, IND, IMP, ZPX, ZPX, ZPY, IMP, IMP, ABSY, IMP, IMP, ABS, ABSX, ABSX, IMP,
-- A0 IMM, INDX, IMM, IMP, ZP, ZP, ZP, IMP, IMP, IMM, IMP, IMP, ABS, ABS, ABS, IMP,
-- B0 BRA, INDY, IND, IMP, ZPX, ZPX, ZPY, IMP, IMP, ABSY, IMP, IMP, ABSX, ABSX, ABSY, IMP,
-- C0 IMM, INDX, IMP, IMP, ZP, ZP, ZP, IMP, IMP, IMM, IMP, IMP, ABS, ABS, ABS, IMP,
-- D0 BRA, INDY, IND, IMP, ZP, ZPX, ZPX, IMP, IMP, ABSY, IMP, IMP, ABS, ABSX, ABSX, IMP,
-- E0 IMM, INDX, IMP, IMP, ZP, ZP, ZP, IMP, IMP, IMM, IMP, IMP, ABS, ABS, ABS, IMP,
-- F0 BRA, INDY, IND, IMP, ZP, ZPX, ZPX, IMP, IMP, ABSY, IMP, IMP, ABS, ABSX, ABSX, IMP
-- Detect forced opcodes that are 3 bytes long
op3 <= '1' when memory_dout(7 downto 0) = "00100000" else
'1' when memory_dout(4 downto 0) = "11011" else
'1' when memory_dout(3 downto 0) = "1100" else
'1' when memory_dout(3 downto 0) = "1101" else
'1' when memory_dout(3 downto 0) = "1110" else
'0';
Din_int <= memory_dout( 7 downto 0) when state = idle and Sync_int = '1' and exec_held = '1' else
memory_addr( 7 downto 0) when state = exec1 else
memory_addr(15 downto 8) when state = exec2 else
Din;
men_access_machine : process(cpu_clk, cpu_reset_n)
begin
if cpu_reset_n = '0' then
state <= idle;
elsif rising_edge(cpu_clk) then
-- Extend the control signals from BusMonitorCore which
-- only last one cycle.
if SS_Step = '1' then
SS_Step_held <= '1';
elsif state = idle then
SS_Step_held <= '0';
end if;
if memory_rd = '1' then
memory_rd1 <= '1';
elsif state = rd then
memory_rd1 <= '0';
end if;
if memory_wr = '1' then
memory_wr1 <= '1';
elsif state = wr then
memory_wr1 <= '0';
end if;
if exec = '1' then
exec_held <= '1';
elsif state = exec1 then
exec_held <= '0';
end if;
if cpu_clken = '1' and Rdy = '1' then
case state is
-- idle is when the CPU is running normally
when idle =>
if Sync_int = '1' then
if exec_held = '1' then
state <= exec1;
elsif SS_Single = '1' then
state <= nop0;
end if;
end if;
-- nop0 is the first state entered when the CPU is paused
when nop0 =>
if memory_rd1 = '1' then
state <= rd;
elsif memory_wr1 = '1' then
state <= wr;
elsif SS_Step_held = '1' or exec_held = '1' then
state <= idle;
else
state <= nop1;
end if;
-- nop1 simulates a sync cycle
when nop1 =>
state <= nop0;
-- rd is a monitor initiated read cycle
when rd =>
state <= nop0;
-- wr is a monitor initiated write cycle
when wr =>
state <= nop0;
-- exec1 is the LSB of a forced JMP
when exec1 =>
if op3 = '1' then
state <= exec2;
else
state <= idle;
end if;
-- exec2 is the MSB of a forced JMP
when exec2 =>
state <= idle;
end case;
end if;
end if;
end process;
-- Only count cycles when the 6502 is actually running
-- TODO: Should this be qualified with cpu_clken and rdy?
CountCycle <= '1' when state = idle or state = exec1 or state = exec2 else '0';
R_W_n <= R_W_n_int when state = idle else
'0' when state = wr else
'1';
Addr <= Addr_int(15 downto 0) when state = idle else
memory_addr when state = rd or state = wr else
(others => '0');
Sync <= Sync_int when state = idle else
'1' when state = nop1 else
'0';
Dout <= Dout_int when state = idle else
memory_dout;
-- Data is captured by the bus monitor on the rising edge of cpu_clk
-- that sees done = 1.
memory_done <= '1' when state = rd or state = wr or (op3 = '0' and state = exec1) or state = exec2 else '0';
memory_din <= Din;
end behavioral;
| apache-2.0 | 88ec563d41ddb02833281ab5155ad540 | 0.458717 | 3.621866 | false | false | false | false |
GSimas/EEL5105 | PROJETO-EEL5105/Projeto/FSM_control.vhd | 1 | 1,900 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--FSM de controle de estados do jogo
entity FSM_control is port(
CLK, RESET, END_BONUS, END_TIME, ENTER, TARGET: in std_logic;
SEL_DISP: out std_logic_vector(1 downto 0);
STATESS: out std_logic_vector(4 downto 0);
SEL_LED, SET_ROLL, EN_TIME, RST: out std_logic
);
end FSM_control;
--Definir arquitetura
architecture bhv of FSM_control is
type states is (E0, E1, E2, E3);
signal EA, PE: states;
begin
--Processo 1 para Clock e Reset
P1: process(CLK, RESET)
begin
if RESET = '0' then
EA <= E0;
elsif CLK'event and CLK = '1' then
EA <= PE;
end if;
end process;
--Processo 2 para estados
P2: process(EA, TARGET, ENTER, END_TIME, END_BONUS)
begin
case EA is
--ESTADO INIT
when E0 => STATESS <= "00000";
SEL_LED <= '0';
SEL_DISP <= "10";
SET_ROLL <= '0';
EN_TIME <= '0';
RST <= '0';
if ENTER = '0' then
PE <= E1;
elsif ENTER = '1' then
PE <= E0;
end if;
--ESTADO SETUP
when E1 => STATESS <= "00001";
SEL_LED <= '0';
SEL_DISP <= "01";
SET_ROLL <= '0';
EN_TIME <= '0';
RST <= '1';
if ENTER = '0' then
PE <= E2;
elsif ENTER = '1' then
PE <= E1;
end if;
--ESTADO GAME
when E2 => STATESS <= "00010";
SEL_LED <= '1';
SEL_DISP <= "00";
SET_ROLL <= '1';
EN_TIME <= '1';
RST <= '1';
if TARGET = '1' or END_TIME = '1' or END_BONUS = '1' then
PE <= E3;
else
PE <= E2;
end if;
--ESTADO END
when E3 => STATESS <= "00011";
SEL_LED <= '0';
SEL_DISP <= "11";
SET_ROLL <= '0';
EN_TIME <= '0';
RST <= '1';
if ENTER = '0' then
PE <= E0;
elsif ENTER = '1' then
PE <= E3;
end if;
end case;
end process;
end bhv;
| mit | 81bc710f379e03216aca6831306cfc44 | 0.511579 | 2.672293 | false | false | false | false |
JoseHawk/Frequency_Counter | Frecuencímetro/Frecuencimetro.vhd | 1 | 3,447 | -- FRECUENCIMETRO
-- Librerias necesarias
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
-- Definimos la entidad
ENTITY Frecuencimetro IS
PORT(
reloj : IN STD_LOGIC; -- Reloj interno de la placa
senialGenerador : IN STD_LOGIC; -- Senial introducida por el generador
decenasDisplay : OUT STD_LOGIC_VECTOR (6 DOWNTO 0); -- Valor de las decenas a mostrar en el display
unidadesDisplay: OUT STD_LOGIC_VECTOR (6 DOWNTO 0) -- Valor de las unidades a mostrar en el display
);
END Frecuencimetro;
-- Definimos la arquitectura
ARCHITECTURE arquitecturaFrecuencimetro OF Frecuencimetro IS
SIGNAL salida : INTEGER RANGE 0 TO 90; -- En esta senial guardaremos el valor del numero de pulsos de la senial para mostrar dicho resultado
SIGNAL unidades : INTEGER RANGE 0 TO 9; -- Valor de las unidades
SIGNAL decenas : INTEGER RANGE 0 TO 9; -- Valor de las decenas
SIGNAL pulsosReloj : INTEGER RANGE 0 TO 26000; -- Contamos los pulsos de nuestra senial de reloj
SIGNAL pulsosSenial : INTEGER RANGE 0 TO 99; -- Contamos los pulsos de la senial introducida
SIGNAL flag : std_logic:='0'; -- Marca utilizada para reiniciar los pulso de la senial
-- Instanciamos el codificador de 7 segmentos para la representacion mediante display
COMPONENT codificador7Segmentos
PORT(
entrada : IN INTEGER RANGE 0 TO 9;
salida : OUT STD_LOGIC_VECTOR (6 DOWNTO 0)
);
END COMPONENT;
BEGIN
-- Proceso que cuenta el numero de pulsos que da el reloj. Cuando llegue a 25175 (ya que la frecuencia es de
-- 25'175 MHz = 25175000 pulsos por segundo) es que ha pasado un segundo. Por tanto mostramos los pulsos que ha dado
-- nuestra senial hasta entonces (en KHz)
cuantificadorReloj : PROCESS (reloj)
BEGIN
IF (reloj'EVENT AND reloj= '1') THEN
pulsosReloj <= pulsosReloj + 1;
flag <= '0';
IF (pulsosReloj >= 25175) THEN
flag <= '1';
salida <= pulsosSenial;
pulsosReloj <= 0;
END IF;
END IF;
END PROCESS cuantificadorReloj;
-- Proceso que cuenta el numero de pulsos que da la senial del generador en un segundo. Obtenemos asi su frecuencia
cuantificadorGenerador : PROCESS (flag, senialGenerador)
BEGIN
IF flag = '1' THEN
pulsosSenial <= 0;
else
IF (senialGenerador'EVENT AND senialGenerador = '1') THEN
pulsosSenial <= pulsosSenial + 1;
END IF;
END IF;
END PROCESS cuantificadorGenerador;
-- Proceso para obtener el valor de la frecuencia de la senial a partir del numero de pulsos obtenidos de esta
-- Como sabemos que se movera el valor entre los 1-90 KHz, en el primer display mostraremos las unidades en KHz y en el segundo las decenas en KHz
valoresDisplays : PROCESS (salida)
BEGIN
decenas <= (salida/10); -- Obtenemos las decenas
unidades <= salida - decenas*10; -- Obtenemos las unidades
END PROCESS valoresDisplays;
-- Codificamos para mostrar por el display de 7 segmentos las unidades
mostrarUnidadesDisplay : codificador7Segmentos PORT MAP(
entrada => unidades,
salida => unidadesDisplay
);
-- Codificamos para mostrar por el display de 7 segmenos las decenas
mostrarDecenasDisplay : codificador7Segmentos PORT MAP(
entrada => decenas,
salida => decenasDisplay
);
END arquitecturaFrecuencimetro; | gpl-2.0 | f91bbf29d1c033a8377feae750bb7622 | 0.692776 | 3.722462 | false | false | false | false |
hoglet67/AtomFpga | src/xilinx/AtomFpga_PapilioDuo.vhd | 1 | 9,483 | --------------------------------------------------------------------------------
-- Copyright (c) 2015 David Banks
--
-- based on work by Alan Daly. Copyright(c) 2009. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ /
-- \ \ \/
-- \ \
-- / / Filename : AtomFpga_PapilioDuo.vhd
-- /___/ /\ Timestamp : 19/04/2015
-- \ \ / \
-- \___\/\___\
--
--Design Name: AtomFpga_PapilioDuo
--Device: Spartan6 LX9
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity AtomFpga_PapilioDuo is
port (clk_32M00 : in std_logic;
ps2_kbd_clk : in std_logic;
ps2_kbd_data : in std_logic;
ps2_mse_clk : inout std_logic;
ps2_mse_data : inout std_logic;
ERST : in std_logic;
red : out std_logic_vector (3 downto 0);
green : out std_logic_vector (3 downto 0);
blue : out std_logic_vector (3 downto 0);
vsync : out std_logic;
hsync : out std_logic;
audioL : out std_logic;
audioR : out std_logic;
SRAM_nOE : out std_logic;
SRAM_nWE : out std_logic;
SRAM_nCS : out std_logic;
SRAM_A : out std_logic_vector (20 downto 0);
SRAM_D : inout std_logic_vector (7 downto 0);
SDMISO : in std_logic;
SDSS : out std_logic;
SDCLK : out std_logic;
SDMOSI : out std_logic;
LED1 : out std_logic;
LED2 : out std_logic;
ARDUINO_RESET : out std_logic;
SW1 : in std_logic;
FLASH_CS : out std_logic; -- Active low FLASH chip select
FLASH_SI : out std_logic; -- Serial output to FLASH chip SI pin
FLASH_CK : out std_logic; -- FLASH clock
FLASH_SO : in std_logic; -- Serial input from FLASH chip SO
avr_RxD : in std_logic;
avr_TxD : out std_logic;
uart_RxD : in std_logic;
uart_TxD : out std_logic;
DIP : in std_logic_vector (3 downto 0);
JOYSTICK1 : in std_logic_vector (7 downto 0);
JOYSTICK2 : in std_logic_vector (7 downto 0)
);
end AtomFpga_PapilioDuo;
architecture behavioral of AtomFpga_PapilioDuo is
signal clock_25 : std_logic;
signal clock_32 : std_logic;
signal powerup_reset_n : std_logic;
signal hard_reset_n : std_logic;
signal reset_counter : std_logic_vector(9 downto 0);
signal phi2 : std_logic;
signal RAM_A : std_logic_vector(18 downto 0);
signal RAM_Din : std_logic_vector(7 downto 0);
signal RAM_Dout : std_logic_vector(7 downto 0);
signal RAM_nWE : std_logic;
signal RAM_nOE : std_logic;
signal RAM_nCS : std_logic;
signal ExternCE : std_logic;
signal ExternWE : std_logic;
signal ExternA : std_logic_vector (18 downto 0);
signal ExternDin : std_logic_vector (7 downto 0);
signal ExternDout : std_logic_vector (7 downto 0);
-----------------------------------------------
-- Bootstrap ROM Image from SPI FLASH into SRAM
-----------------------------------------------
-- start address of user data in FLASH as obtained from bitmerge.py
-- this is safely beyond the end of the bitstream
constant user_address : std_logic_vector(23 downto 0) := x"060000";
-- lenth of user data in FLASH = 128KB (32x 4KB ROM) images
constant user_length : std_logic_vector(23 downto 0) := x"020000";
-- high when FLASH is being copied to SRAM, can be used by user as active high reset
signal bootstrap_busy : std_logic;
begin
--------------------------------------------------------
-- Atom Fpga Core
--------------------------------------------------------
inst_AtomFpga_Core : entity work.AtomFpga_Core
generic map (
CImplSDDOS => false,
CImplAtoMMC2 => true,
CImplGraphicsExt => true,
CImplSoftChar => true,
CImplSID => true,
CImplVGA80x40 => true,
CImplHWScrolling => true,
CImplMouse => true,
CImplUart => true,
CImplDoubleVideo => true,
CImplRamRomNone => false,
CImplRamRomPhill => true,
CImplRamRomAtom2015 => false,
CImplRamRomSchakelKaart => false,
MainClockSpeed => 32000000,
DefaultBaud => 115200
)
port map (
clk_vga => clock_25,
clk_main => clock_32,
clk_avr => clock_32,
clk_dac => clock_32,
clk_32M00 => clock_32,
ps2_clk => ps2_kbd_clk,
ps2_data => ps2_kbd_data,
ps2_mouse_clk => ps2_mse_clk,
ps2_mouse_data => ps2_mse_data,
powerup_reset_n => powerup_reset_n,
ext_reset_n => hard_reset_n,
int_reset_n => open,
red => red(3 downto 1),
green => green(3 downto 1),
blue => blue(3 downto 1),
vsync => vsync,
hsync => hsync,
phi2 => phi2,
ExternCE => ExternCE,
ExternWE => ExternWE,
ExternA => ExternA,
ExternDin => ExternDin,
ExternDout => ExternDout,
sid_audio => audiol,
sid_audio_d => open,
atom_audio => audioR,
SDMISO => SDMISO,
SDSS => SDSS,
SDCLK => SDCLK,
SDMOSI => SDMOSI,
uart_RxD => uart_RxD,
uart_TxD => uart_TxD,
avr_RxD => avr_RxD,
avr_TxD => avr_TxD,
LED1 => LED1,
LED2 => LED2,
charSet => DIP(0),
Joystick1 => JOYSTICK1,
Joystick2 => JOYSTICK2
);
red(0) <= '0';
green(0) <= '0';
blue(0) <= '0';
--------------------------------------------------------
-- Clock Generation
--------------------------------------------------------
inst_dcm4 : entity work.dcm4 port map(
CLKIN_IN => clk_32M00,
CLK0_OUT => clock_32,
CLKFX_OUT => clock_25
);
--------------------------------------------------------
-- Power Up Reset Generation
--------------------------------------------------------
-- On the Duo the external reset signal is not asserted on power up
-- This internal counter forces power up reset to happen
-- This is needed by the GODIL to initialize some of the registers
ResetProcess : process (clock_32)
begin
if rising_edge(clock_32) then
if (reset_counter(reset_counter'high) = '0') then
reset_counter <= reset_counter + 1;
end if;
powerup_reset_n <= not ERST and reset_counter(reset_counter'high);
end if;
end process;
-- extend the version seen by the core to hold the 6502 reset during bootstrap
hard_reset_n <= powerup_reset_n and not bootstrap_busy;
--------------------------------------------------------
-- Papilio Duo Misc
--------------------------------------------------------
ARDUINO_RESET <= SW1;
--------------------------------------------------------
-- BOOTSTRAP SPI FLASH to SRAM
--------------------------------------------------------
inst_bootstrap: entity work.bootstrap
generic map (
user_length => user_length
)
port map(
clock => clock_32,
powerup_reset_n => powerup_reset_n,
bootstrap_busy => bootstrap_busy,
user_address => user_address,
RAM_nOE => RAM_nOE,
RAM_nWE => RAM_nWE,
RAM_nCS => RAM_nCS,
RAM_A => RAM_A,
RAM_Din => RAM_Din,
RAM_Dout => RAM_Dout,
SRAM_nOE => SRAM_nOE,
SRAM_nWE => SRAM_nWE,
SRAM_nCS => SRAM_nCS,
SRAM_A => SRAM_A,
SRAM_D => SRAM_D,
FLASH_CS => FLASH_CS,
FLASH_SI => FLASH_SI,
FLASH_CK => FLASH_CK,
FLASH_SO => FLASH_SO
);
MemProcess : process (clock_32)
begin
if rising_edge(clock_32) then
RAM_A <= ExternA;
RAM_nCS <= not ExternCE;
RAM_nOE <= not ((not ExternWE) and ExternCE and phi2);
RAM_nWE <= not (ExternWE and ExternCE and phi2);
RAM_Din <= ExternDin;
end if;
end process;
ExternDout <= RAM_Dout;
end behavioral;
| apache-2.0 | a58d676439f83ec72af90c16be7fdd8d | 0.432669 | 4.16469 | false | false | false | false |
hoglet67/AtomFpga | src/common/AVR8/JTAG_OCD_Prg/JTAGDataPack.vhd | 4 | 1,359 | --**********************************************************************************************
-- Fuses/Lock bits and Calibration bytes for JTAG "Flash" Programmer
-- Version 0.11
-- Modified 19.05.2004
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
package JTAGDataPack is
-- Extended Fuse Byte
constant C_ExtFuseByte : std_logic_vector(7 downto 0) := x"FD"; -- x"00"
-- Fuse High Byte
constant C_HighFuseByte : std_logic_vector(7 downto 0) := x"19"; -- x"01"
-- Fuse Low Byte
constant C_LowFuseByte : std_logic_vector(7 downto 0) := x"E3"; -- x"00"
-- Lock bits
constant C_LockBits : std_logic_vector(7 downto 0) := x"FF";
-- Signature Bytes(3 Bytes)
constant C_SignByte1 : std_logic_vector(7 downto 0) := x"1E";
constant C_SignByte2 : std_logic_vector(7 downto 0) := x"97";
constant C_SignByte3 : std_logic_vector(7 downto 0) := x"02";
-- Calibration Bytes(4 Bytes)
constant C_CalibrByte1 : std_logic_vector(7 downto 0) := x"C1";
constant C_CalibrByte2 : std_logic_vector(7 downto 0) := x"C2";
constant C_CalibrByte3 : std_logic_vector(7 downto 0) := x"C3";
constant C_CalibrByte4 : std_logic_vector(7 downto 0) := x"C4";
end JTAGDataPack;
| apache-2.0 | fda8ddc2997b66b2db285faa4722ef2c | 0.558499 | 3.145833 | false | false | false | false |
GSimas/EEL5105 | Eletr-Digital/Relatório4/Controle de Motor de Passo/divisor2.vhd | 1 | 4,571 | -- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_counter
-- ============================================================
-- File Name: divisor2.vhd
-- Megafunction Name(s):
-- lpm_counter
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY divisor2 IS
PORT
(
clock : IN STD_LOGIC ;
cout : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (29 DOWNTO 0)
);
END divisor2;
ARCHITECTURE SYN OF divisor2 IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (29 DOWNTO 0);
COMPONENT lpm_counter
GENERIC (
lpm_direction : STRING;
lpm_modulus : NATURAL;
lpm_port_updown : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
clock : IN STD_LOGIC ;
cout : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (29 DOWNTO 0)
);
END COMPONENT;
BEGIN
cout <= sub_wire0;
q <= sub_wire1(29 DOWNTO 0);
lpm_counter_component : lpm_counter
GENERIC MAP (
lpm_direction => "UP",
lpm_modulus => 12500000,
lpm_port_updown => "PORT_UNUSED",
lpm_type => "LPM_COUNTER",
lpm_width => 30
)
PORT MAP (
clock => clock,
cout => sub_wire0,
q => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CNT_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-- Retrieval info: PRIVATE: CarryOut NUMERIC "1"
-- Retrieval info: PRIVATE: Direction NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
-- Retrieval info: PRIVATE: ModulusCounter NUMERIC "1"
-- Retrieval info: PRIVATE: ModulusValue NUMERIC "12500000"
-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "30"
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
-- Retrieval info: CONSTANT: LPM_MODULUS NUMERIC "12500000"
-- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "30"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: cout 0 0 0 0 OUTPUT NODEFVAL cout
-- Retrieval info: USED_PORT: q 0 0 30 0 OUTPUT NODEFVAL q[29..0]
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 30 0 @q 0 0 30 0
-- Retrieval info: CONNECT: cout 0 0 0 0 @cout 0 0 0 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL divisor2.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL divisor2.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL divisor2.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL divisor2.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL divisor2_inst.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL divisor2_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL divisor2_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: lpm
| mit | 4953527de05f24a550330efa39ce1356 | 0.656312 | 3.701215 | false | false | false | false |
tghaefli/ADD | EDK/IVK_Repos/IVK_IPLib/pcores/sg_2d_fir_plbw_v1_01_a/hdl/vhdl/sg_2d_fir.vhd | 1 | 303,279 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2012 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file addsb_11_0_48bcbc42a6774592.vhd when simulating
-- the core, addsb_11_0_48bcbc42a6774592. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY addsb_11_0_48bcbc42a6774592 IS
PORT (
a : IN STD_LOGIC_VECTOR(20 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(20 DOWNTO 0);
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
s : OUT STD_LOGIC_VECTOR(20 DOWNTO 0)
);
END addsb_11_0_48bcbc42a6774592;
ARCHITECTURE addsb_11_0_48bcbc42a6774592_a OF addsb_11_0_48bcbc42a6774592 IS
-- synthesis translate_off
COMPONENT wrapped_addsb_11_0_48bcbc42a6774592
PORT (
a : IN STD_LOGIC_VECTOR(20 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(20 DOWNTO 0);
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
s : OUT STD_LOGIC_VECTOR(20 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_addsb_11_0_48bcbc42a6774592 USE ENTITY XilinxCoreLib.c_addsub_v11_0(behavioral)
GENERIC MAP (
c_a_type => 0,
c_a_width => 21,
c_add_mode => 0,
c_ainit_val => "0",
c_b_constant => 0,
c_b_type => 0,
c_b_value => "000000000000000000000",
c_b_width => 21,
c_borrow_low => 1,
c_bypass_low => 0,
c_ce_overrides_bypass => 1,
c_ce_overrides_sclr => 0,
c_has_bypass => 0,
c_has_c_in => 0,
c_has_c_out => 0,
c_has_ce => 1,
c_has_sclr => 0,
c_has_sinit => 0,
c_has_sset => 0,
c_implementation => 0,
c_latency => 1,
c_out_width => 21,
c_sclr_overrides_sset => 0,
c_sinit_val => "0",
c_verbosity => 0,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_addsb_11_0_48bcbc42a6774592
PORT MAP (
a => a,
b => b,
clk => clk,
ce => ce,
s => s
);
-- synthesis translate_on
END addsb_11_0_48bcbc42a6774592_a;
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2012 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file addsb_11_0_da33f2d4b3b54185.vhd when simulating
-- the core, addsb_11_0_da33f2d4b3b54185. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY addsb_11_0_da33f2d4b3b54185 IS
PORT (
a : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
s : OUT STD_LOGIC_VECTOR(19 DOWNTO 0)
);
END addsb_11_0_da33f2d4b3b54185;
ARCHITECTURE addsb_11_0_da33f2d4b3b54185_a OF addsb_11_0_da33f2d4b3b54185 IS
-- synthesis translate_off
COMPONENT wrapped_addsb_11_0_da33f2d4b3b54185
PORT (
a : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
s : OUT STD_LOGIC_VECTOR(19 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_addsb_11_0_da33f2d4b3b54185 USE ENTITY XilinxCoreLib.c_addsub_v11_0(behavioral)
GENERIC MAP (
c_a_type => 0,
c_a_width => 20,
c_add_mode => 0,
c_ainit_val => "0",
c_b_constant => 0,
c_b_type => 0,
c_b_value => "00000000000000000000",
c_b_width => 20,
c_borrow_low => 1,
c_bypass_low => 0,
c_ce_overrides_bypass => 1,
c_ce_overrides_sclr => 0,
c_has_bypass => 0,
c_has_c_in => 0,
c_has_c_out => 0,
c_has_ce => 1,
c_has_sclr => 0,
c_has_sinit => 0,
c_has_sset => 0,
c_implementation => 0,
c_latency => 1,
c_out_width => 20,
c_sclr_overrides_sset => 0,
c_sinit_val => "0",
c_verbosity => 0,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_addsb_11_0_da33f2d4b3b54185
PORT MAP (
a => a,
b => b,
clk => clk,
ce => ce,
s => s
);
-- synthesis translate_on
END addsb_11_0_da33f2d4b3b54185_a;
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2012 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file addsb_11_0_e7b4231f2ca96446.vhd when simulating
-- the core, addsb_11_0_e7b4231f2ca96446. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY addsb_11_0_e7b4231f2ca96446 IS
PORT (
a : IN STD_LOGIC_VECTOR(21 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(21 DOWNTO 0);
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
s : OUT STD_LOGIC_VECTOR(21 DOWNTO 0)
);
END addsb_11_0_e7b4231f2ca96446;
ARCHITECTURE addsb_11_0_e7b4231f2ca96446_a OF addsb_11_0_e7b4231f2ca96446 IS
-- synthesis translate_off
COMPONENT wrapped_addsb_11_0_e7b4231f2ca96446
PORT (
a : IN STD_LOGIC_VECTOR(21 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(21 DOWNTO 0);
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
s : OUT STD_LOGIC_VECTOR(21 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_addsb_11_0_e7b4231f2ca96446 USE ENTITY XilinxCoreLib.c_addsub_v11_0(behavioral)
GENERIC MAP (
c_a_type => 0,
c_a_width => 22,
c_add_mode => 0,
c_ainit_val => "0",
c_b_constant => 0,
c_b_type => 0,
c_b_value => "0000000000000000000000",
c_b_width => 22,
c_borrow_low => 1,
c_bypass_low => 0,
c_ce_overrides_bypass => 1,
c_ce_overrides_sclr => 0,
c_has_bypass => 0,
c_has_c_in => 0,
c_has_c_out => 0,
c_has_ce => 1,
c_has_sclr => 0,
c_has_sinit => 0,
c_has_sset => 0,
c_implementation => 0,
c_latency => 1,
c_out_width => 22,
c_sclr_overrides_sset => 0,
c_sinit_val => "0",
c_verbosity => 0,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_addsb_11_0_e7b4231f2ca96446
PORT MAP (
a => a,
b => b,
clk => clk,
ce => ce,
s => s
);
-- synthesis translate_on
END addsb_11_0_e7b4231f2ca96446_a;
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2012 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file bmg_62_05852d43925e39b8.vhd when simulating
-- the core, bmg_62_05852d43925e39b8. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY bmg_62_05852d43925e39b8 IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END bmg_62_05852d43925e39b8;
ARCHITECTURE bmg_62_05852d43925e39b8_a OF bmg_62_05852d43925e39b8 IS
-- synthesis translate_off
COMPONENT wrapped_bmg_62_05852d43925e39b8
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_bmg_62_05852d43925e39b8 USE ENTITY XilinxCoreLib.blk_mem_gen_v6_2(behavioral)
GENERIC MAP (
c_addra_width => 12,
c_addrb_width => 12,
c_algorithm => 0,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_family => "spartan6",
c_has_axi_id => 0,
c_has_ena => 1,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file_name => "bmg_62_05852d43925e39b8.mif",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 1,
c_mem_type => 0,
c_mux_pipeline_stages => 0,
c_prim_type => 2,
c_read_depth_a => 4096,
c_read_depth_b => 4096,
c_read_width_a => 5,
c_read_width_b => 5,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 4096,
c_write_depth_b => 4096,
c_write_mode_a => "READ_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 5,
c_write_width_b => 5,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_bmg_62_05852d43925e39b8
PORT MAP (
clka => clka,
ena => ena,
wea => wea,
addra => addra,
dina => dina,
douta => douta
);
-- synthesis translate_on
END bmg_62_05852d43925e39b8_a;
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2012 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file bmg_62_54b11b852dca329b.vhd when simulating
-- the core, bmg_62_54b11b852dca329b. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY bmg_62_54b11b852dca329b IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END bmg_62_54b11b852dca329b;
ARCHITECTURE bmg_62_54b11b852dca329b_a OF bmg_62_54b11b852dca329b IS
-- synthesis translate_off
COMPONENT wrapped_bmg_62_54b11b852dca329b
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_bmg_62_54b11b852dca329b USE ENTITY XilinxCoreLib.blk_mem_gen_v6_2(behavioral)
GENERIC MAP (
c_addra_width => 12,
c_addrb_width => 12,
c_algorithm => 0,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_family => "spartan6",
c_has_axi_id => 0,
c_has_ena => 1,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file_name => "bmg_62_54b11b852dca329b.mif",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 1,
c_mem_type => 0,
c_mux_pipeline_stages => 0,
c_prim_type => 2,
c_read_depth_a => 4096,
c_read_depth_b => 4096,
c_read_width_a => 8,
c_read_width_b => 8,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 4096,
c_write_depth_b => 4096,
c_write_mode_a => "READ_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 8,
c_write_width_b => 8,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_bmg_62_54b11b852dca329b
PORT MAP (
clka => clka,
ena => ena,
wea => wea,
addra => addra,
dina => dina,
douta => douta
);
-- synthesis translate_on
END bmg_62_54b11b852dca329b_a;
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2012 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file cntr_11_0_862f833518f4973a.vhd when simulating
-- the core, cntr_11_0_862f833518f4973a. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY cntr_11_0_862f833518f4973a IS
PORT (
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
sinit : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END cntr_11_0_862f833518f4973a;
ARCHITECTURE cntr_11_0_862f833518f4973a_a OF cntr_11_0_862f833518f4973a IS
-- synthesis translate_off
COMPONENT wrapped_cntr_11_0_862f833518f4973a
PORT (
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
sinit : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_cntr_11_0_862f833518f4973a USE ENTITY XilinxCoreLib.c_counter_binary_v11_0(behavioral)
GENERIC MAP (
c_ainit_val => "0",
c_ce_overrides_sync => 0,
c_count_by => "1",
c_count_mode => 0,
c_count_to => "1",
c_fb_latency => 0,
c_has_ce => 1,
c_has_load => 0,
c_has_sclr => 0,
c_has_sinit => 1,
c_has_sset => 0,
c_has_thresh0 => 0,
c_implementation => 0,
c_latency => 1,
c_load_low => 0,
c_restrict_count => 0,
c_sclr_overrides_sset => 1,
c_sinit_val => "0",
c_thresh0_value => "1",
c_verbosity => 0,
c_width => 5,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_cntr_11_0_862f833518f4973a
PORT MAP (
clk => clk,
ce => ce,
sinit => sinit,
q => q
);
-- synthesis translate_on
END cntr_11_0_862f833518f4973a_a;
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2012 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file cntr_11_0_e859c6662c373192.vhd when simulating
-- the core, cntr_11_0_e859c6662c373192. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY cntr_11_0_e859c6662c373192 IS
PORT (
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
sinit : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
);
END cntr_11_0_e859c6662c373192;
ARCHITECTURE cntr_11_0_e859c6662c373192_a OF cntr_11_0_e859c6662c373192 IS
-- synthesis translate_off
COMPONENT wrapped_cntr_11_0_e859c6662c373192
PORT (
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
sinit : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_cntr_11_0_e859c6662c373192 USE ENTITY XilinxCoreLib.c_counter_binary_v11_0(behavioral)
GENERIC MAP (
c_ainit_val => "0",
c_ce_overrides_sync => 0,
c_count_by => "1",
c_count_mode => 0,
c_count_to => "1",
c_fb_latency => 0,
c_has_ce => 1,
c_has_load => 0,
c_has_sclr => 0,
c_has_sinit => 1,
c_has_sset => 0,
c_has_thresh0 => 0,
c_implementation => 0,
c_latency => 1,
c_load_low => 0,
c_restrict_count => 0,
c_sclr_overrides_sset => 1,
c_sinit_val => "0",
c_thresh0_value => "1",
c_verbosity => 0,
c_width => 3,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_cntr_11_0_e859c6662c373192
PORT MAP (
clk => clk,
ce => ce,
sinit => sinit,
q => q
);
-- synthesis translate_on
END cntr_11_0_e859c6662c373192_a;
--------------------------------------------------------------------------------
-- (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. --
-- --
-- This file contains confidential and proprietary information --
-- of Xilinx, Inc. and is protected under U.S. and --
-- international copyright and other intellectual property --
-- laws. --
-- --
-- DISCLAIMER --
-- This disclaimer is not a license and does not grant any --
-- rights to the materials distributed herewith. Except as --
-- otherwise provided in a valid license issued to you by --
-- Xilinx, and to the maximum extent permitted by applicable --
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --
-- (2) Xilinx shall not be liable (whether in contract or tort, --
-- including negligence, or under any other theory of --
-- liability) for any loss or damage of any kind or nature --
-- related to, arising under or in connection with these --
-- materials, including for any direct, or any indirect, --
-- special, incidental, or consequential loss or damage --
-- (including loss of data, profits, goodwill, or any type of --
-- loss or damage suffered as a result of any action brought --
-- by a third party) even if such damage or loss was --
-- reasonably foreseeable or Xilinx had been advised of the --
-- possibility of the same. --
-- --
-- CRITICAL APPLICATIONS --
-- Xilinx products are not designed or intended to be fail- --
-- safe, or for use in any application requiring fail-safe --
-- performance, such as life-support or safety devices or --
-- systems, Class III medical devices, nuclear facilities, --
-- applications related to the deployment of airbags, or any --
-- other applications that could lead to death, personal --
-- injury, or severe property or environmental damage --
-- (individually and collectively, "Critical --
-- Applications"). Customer assumes the sole risk and --
-- liability of any use of Xilinx products in Critical --
-- Applications, subject only to applicable laws and --
-- regulations governing limitations on product liability. --
-- --
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --
-- PART OF THIS FILE AT ALL TIMES. --
--------------------------------------------------------------------------------
-- Generated from component ID: xilinx.com:ip:fir_compiler:5.0
-- You must compile the wrapper file fr_cmplr_v5_0_0d2261239884a389.vhd when simulating
-- the core, fr_cmplr_v5_0_0d2261239884a389. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY fr_cmplr_v5_0_0d2261239884a389 IS
port (
clk: in std_logic;
ce: in std_logic;
nd: in std_logic;
coef_ld: in std_logic;
coef_we: in std_logic;
coef_din: in std_logic_vector(6 downto 0);
rfd: out std_logic;
rdy: out std_logic;
din: in std_logic_vector(7 downto 0);
dout: out std_logic_vector(18 downto 0));
END fr_cmplr_v5_0_0d2261239884a389;
ARCHITECTURE fr_cmplr_v5_0_0d2261239884a389_a OF fr_cmplr_v5_0_0d2261239884a389 IS
-- synthesis translate_off
component wrapped_fr_cmplr_v5_0_0d2261239884a389
port (
clk: in std_logic;
ce: in std_logic;
nd: in std_logic;
coef_ld: in std_logic;
coef_we: in std_logic;
coef_din: in std_logic_vector(6 downto 0);
rfd: out std_logic;
rdy: out std_logic;
din: in std_logic_vector(7 downto 0);
dout: out std_logic_vector(18 downto 0));
end component;
-- Configuration specification
for all : wrapped_fr_cmplr_v5_0_0d2261239884a389 use entity XilinxCoreLib.fir_compiler_v5_0(behavioral)
generic map(
coef_width => 7,
c_has_sclr => 0,
datapath_memtype => 0,
c_component_name => "fr_cmplr_v5_0_0d2261239884a389",
c_family => "spartan6",
round_mode => 0,
output_width => 19,
sclr_deterministic => 0,
col_config => "5",
coef_memtype => 0,
clock_freq => 1,
symmetry => 0,
col_pipe_len => 4,
c_latency => 11,
chan_sel_width => 1,
c_xdevicefamily => "spartan6",
c_has_nd => 1,
allow_approx => 0,
num_channels => 1,
data_width => 8,
filter_sel_width => 1,
sample_freq => 1,
coef_reload => 1,
neg_symmetry => 0,
filter_type => 0,
data_type => 1,
accum_width => 19,
rate_change_type => 0,
ipbuff_memtype => 0,
c_optimization => 1,
output_reg => 1,
data_memtype => 0,
c_has_data_valid => 0,
decim_rate => 1,
coef_type => 0,
filter_arch => 1,
interp_rate => 1,
num_taps => 5,
c_mem_init_file => "fr_cmplr_v5_0_0d2261239884a389.mif",
zero_packing_factor => 1,
num_paths => 1,
num_filts => 1,
col_mode => 0,
c_has_ce => 1,
chan_in_adv => 0,
opbuff_memtype => 0,
odd_symmetry => 1);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_fr_cmplr_v5_0_0d2261239884a389
port map (
clk => clk,
ce => ce,
nd => nd,
coef_ld => coef_ld,
coef_we => coef_we,
coef_din => coef_din,
rfd => rfd,
rdy => rdy,
din => din,
dout => dout);
-- synthesis translate_on
END fr_cmplr_v5_0_0d2261239884a389_a;
--------------------------------------------------------------------------------
-- (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. --
-- --
-- This file contains confidential and proprietary information --
-- of Xilinx, Inc. and is protected under U.S. and --
-- international copyright and other intellectual property --
-- laws. --
-- --
-- DISCLAIMER --
-- This disclaimer is not a license and does not grant any --
-- rights to the materials distributed herewith. Except as --
-- otherwise provided in a valid license issued to you by --
-- Xilinx, and to the maximum extent permitted by applicable --
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --
-- (2) Xilinx shall not be liable (whether in contract or tort, --
-- including negligence, or under any other theory of --
-- liability) for any loss or damage of any kind or nature --
-- related to, arising under or in connection with these --
-- materials, including for any direct, or any indirect, --
-- special, incidental, or consequential loss or damage --
-- (including loss of data, profits, goodwill, or any type of --
-- loss or damage suffered as a result of any action brought --
-- by a third party) even if such damage or loss was --
-- reasonably foreseeable or Xilinx had been advised of the --
-- possibility of the same. --
-- --
-- CRITICAL APPLICATIONS --
-- Xilinx products are not designed or intended to be fail- --
-- safe, or for use in any application requiring fail-safe --
-- performance, such as life-support or safety devices or --
-- systems, Class III medical devices, nuclear facilities, --
-- applications related to the deployment of airbags, or any --
-- other applications that could lead to death, personal --
-- injury, or severe property or environmental damage --
-- (individually and collectively, "Critical --
-- Applications"). Customer assumes the sole risk and --
-- liability of any use of Xilinx products in Critical --
-- Applications, subject only to applicable laws and --
-- regulations governing limitations on product liability. --
-- --
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --
-- PART OF THIS FILE AT ALL TIMES. --
--------------------------------------------------------------------------------
-- Generated from component ID: xilinx.com:ip:fir_compiler:5.0
-- You must compile the wrapper file fr_cmplr_v5_0_983c85a69a3a58e7.vhd when simulating
-- the core, fr_cmplr_v5_0_983c85a69a3a58e7. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY fr_cmplr_v5_0_983c85a69a3a58e7 IS
port (
clk: in std_logic;
ce: in std_logic;
nd: in std_logic;
coef_ld: in std_logic;
coef_we: in std_logic;
coef_din: in std_logic_vector(6 downto 0);
rfd: out std_logic;
rdy: out std_logic;
din: in std_logic_vector(7 downto 0);
dout: out std_logic_vector(18 downto 0));
END fr_cmplr_v5_0_983c85a69a3a58e7;
ARCHITECTURE fr_cmplr_v5_0_983c85a69a3a58e7_a OF fr_cmplr_v5_0_983c85a69a3a58e7 IS
-- synthesis translate_off
component wrapped_fr_cmplr_v5_0_983c85a69a3a58e7
port (
clk: in std_logic;
ce: in std_logic;
nd: in std_logic;
coef_ld: in std_logic;
coef_we: in std_logic;
coef_din: in std_logic_vector(6 downto 0);
rfd: out std_logic;
rdy: out std_logic;
din: in std_logic_vector(7 downto 0);
dout: out std_logic_vector(18 downto 0));
end component;
-- Configuration specification
for all : wrapped_fr_cmplr_v5_0_983c85a69a3a58e7 use entity XilinxCoreLib.fir_compiler_v5_0(behavioral)
generic map(
coef_width => 7,
c_has_sclr => 0,
datapath_memtype => 0,
c_component_name => "fr_cmplr_v5_0_983c85a69a3a58e7",
c_family => "spartan6",
round_mode => 0,
output_width => 19,
sclr_deterministic => 0,
col_config => "5",
coef_memtype => 0,
clock_freq => 1,
symmetry => 0,
col_pipe_len => 4,
c_latency => 11,
chan_sel_width => 1,
c_xdevicefamily => "spartan6",
c_has_nd => 1,
allow_approx => 0,
num_channels => 1,
data_width => 8,
filter_sel_width => 1,
sample_freq => 1,
coef_reload => 1,
neg_symmetry => 0,
filter_type => 0,
data_type => 1,
accum_width => 19,
rate_change_type => 0,
ipbuff_memtype => 0,
c_optimization => 1,
output_reg => 1,
data_memtype => 0,
c_has_data_valid => 0,
decim_rate => 1,
coef_type => 0,
filter_arch => 1,
interp_rate => 1,
num_taps => 5,
c_mem_init_file => "fr_cmplr_v5_0_983c85a69a3a58e7.mif",
zero_packing_factor => 1,
num_paths => 1,
num_filts => 1,
col_mode => 0,
c_has_ce => 1,
chan_in_adv => 0,
opbuff_memtype => 0,
odd_symmetry => 1);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_fr_cmplr_v5_0_983c85a69a3a58e7
port map (
clk => clk,
ce => ce,
nd => nd,
coef_ld => coef_ld,
coef_we => coef_we,
coef_din => coef_din,
rfd => rfd,
rdy => rdy,
din => din,
dout => dout);
-- synthesis translate_on
END fr_cmplr_v5_0_983c85a69a3a58e7_a;
--------------------------------------------------------------------------------
-- (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. --
-- --
-- This file contains confidential and proprietary information --
-- of Xilinx, Inc. and is protected under U.S. and --
-- international copyright and other intellectual property --
-- laws. --
-- --
-- DISCLAIMER --
-- This disclaimer is not a license and does not grant any --
-- rights to the materials distributed herewith. Except as --
-- otherwise provided in a valid license issued to you by --
-- Xilinx, and to the maximum extent permitted by applicable --
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --
-- (2) Xilinx shall not be liable (whether in contract or tort, --
-- including negligence, or under any other theory of --
-- liability) for any loss or damage of any kind or nature --
-- related to, arising under or in connection with these --
-- materials, including for any direct, or any indirect, --
-- special, incidental, or consequential loss or damage --
-- (including loss of data, profits, goodwill, or any type of --
-- loss or damage suffered as a result of any action brought --
-- by a third party) even if such damage or loss was --
-- reasonably foreseeable or Xilinx had been advised of the --
-- possibility of the same. --
-- --
-- CRITICAL APPLICATIONS --
-- Xilinx products are not designed or intended to be fail- --
-- safe, or for use in any application requiring fail-safe --
-- performance, such as life-support or safety devices or --
-- systems, Class III medical devices, nuclear facilities, --
-- applications related to the deployment of airbags, or any --
-- other applications that could lead to death, personal --
-- injury, or severe property or environmental damage --
-- (individually and collectively, "Critical --
-- Applications"). Customer assumes the sole risk and --
-- liability of any use of Xilinx products in Critical --
-- Applications, subject only to applicable laws and --
-- regulations governing limitations on product liability. --
-- --
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --
-- PART OF THIS FILE AT ALL TIMES. --
--------------------------------------------------------------------------------
-- Generated from component ID: xilinx.com:ip:fir_compiler:5.0
-- You must compile the wrapper file fr_cmplr_v5_0_bc5286c4b0615582.vhd when simulating
-- the core, fr_cmplr_v5_0_bc5286c4b0615582. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY fr_cmplr_v5_0_bc5286c4b0615582 IS
port (
clk: in std_logic;
ce: in std_logic;
nd: in std_logic;
coef_ld: in std_logic;
coef_we: in std_logic;
coef_din: in std_logic_vector(6 downto 0);
rfd: out std_logic;
rdy: out std_logic;
din: in std_logic_vector(7 downto 0);
dout: out std_logic_vector(18 downto 0));
END fr_cmplr_v5_0_bc5286c4b0615582;
ARCHITECTURE fr_cmplr_v5_0_bc5286c4b0615582_a OF fr_cmplr_v5_0_bc5286c4b0615582 IS
-- synthesis translate_off
component wrapped_fr_cmplr_v5_0_bc5286c4b0615582
port (
clk: in std_logic;
ce: in std_logic;
nd: in std_logic;
coef_ld: in std_logic;
coef_we: in std_logic;
coef_din: in std_logic_vector(6 downto 0);
rfd: out std_logic;
rdy: out std_logic;
din: in std_logic_vector(7 downto 0);
dout: out std_logic_vector(18 downto 0));
end component;
-- Configuration specification
for all : wrapped_fr_cmplr_v5_0_bc5286c4b0615582 use entity XilinxCoreLib.fir_compiler_v5_0(behavioral)
generic map(
coef_width => 7,
c_has_sclr => 0,
datapath_memtype => 0,
c_component_name => "fr_cmplr_v5_0_bc5286c4b0615582",
c_family => "spartan6",
round_mode => 0,
output_width => 19,
sclr_deterministic => 0,
col_config => "5",
coef_memtype => 0,
clock_freq => 1,
symmetry => 0,
col_pipe_len => 4,
c_latency => 11,
chan_sel_width => 1,
c_xdevicefamily => "spartan6",
c_has_nd => 1,
allow_approx => 0,
num_channels => 1,
data_width => 8,
filter_sel_width => 1,
sample_freq => 1,
coef_reload => 1,
neg_symmetry => 0,
filter_type => 0,
data_type => 1,
accum_width => 19,
rate_change_type => 0,
ipbuff_memtype => 0,
c_optimization => 1,
output_reg => 1,
data_memtype => 0,
c_has_data_valid => 0,
decim_rate => 1,
coef_type => 0,
filter_arch => 1,
interp_rate => 1,
num_taps => 5,
c_mem_init_file => "fr_cmplr_v5_0_bc5286c4b0615582.mif",
zero_packing_factor => 1,
num_paths => 1,
num_filts => 1,
col_mode => 0,
c_has_ce => 1,
chan_in_adv => 0,
opbuff_memtype => 0,
odd_symmetry => 1);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_fr_cmplr_v5_0_bc5286c4b0615582
port map (
clk => clk,
ce => ce,
nd => nd,
coef_ld => coef_ld,
coef_we => coef_we,
coef_din => coef_din,
rfd => rfd,
rdy => rdy,
din => din,
dout => dout);
-- synthesis translate_on
END fr_cmplr_v5_0_bc5286c4b0615582_a;
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2012 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file mult_11_2_fe92ad55b7635191.vhd when simulating
-- the core, mult_11_2_fe92ad55b7635191. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY mult_11_2_fe92ad55b7635191 IS
PORT (
clk : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR(22 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
ce : IN STD_LOGIC;
sclr : IN STD_LOGIC;
p : OUT STD_LOGIC_VECTOR(42 DOWNTO 0)
);
END mult_11_2_fe92ad55b7635191;
ARCHITECTURE mult_11_2_fe92ad55b7635191_a OF mult_11_2_fe92ad55b7635191 IS
-- synthesis translate_off
COMPONENT wrapped_mult_11_2_fe92ad55b7635191
PORT (
clk : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR(22 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
ce : IN STD_LOGIC;
sclr : IN STD_LOGIC;
p : OUT STD_LOGIC_VECTOR(42 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_mult_11_2_fe92ad55b7635191 USE ENTITY XilinxCoreLib.mult_gen_v11_2(behavioral)
GENERIC MAP (
c_a_type => 0,
c_a_width => 23,
c_b_type => 1,
c_b_value => "10000001",
c_b_width => 20,
c_ccm_imp => 0,
c_ce_overrides_sclr => 1,
c_has_ce => 1,
c_has_sclr => 1,
c_has_zero_detect => 0,
c_latency => 4,
c_model_type => 0,
c_mult_type => 1,
c_optimize_goal => 1,
c_out_high => 42,
c_out_low => 0,
c_round_output => 0,
c_round_pt => 0,
c_verbosity => 0,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_mult_11_2_fe92ad55b7635191
PORT MAP (
clk => clk,
a => a,
b => b,
ce => ce,
sclr => sclr,
p => p
);
-- synthesis translate_on
END mult_11_2_fe92ad55b7635191_a;
-------------------------------------------------------------------
-- System Generator version 13.2 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package conv_pkg is
constant simulating : boolean := false
-- synopsys translate_off
or true
-- synopsys translate_on
;
constant xlUnsigned : integer := 1;
constant xlSigned : integer := 2;
constant xlFloat : integer := 3;
constant xlWrap : integer := 1;
constant xlSaturate : integer := 2;
constant xlTruncate : integer := 1;
constant xlRound : integer := 2;
constant xlRoundBanker : integer := 3;
constant xlAddMode : integer := 1;
constant xlSubMode : integer := 2;
attribute black_box : boolean;
attribute syn_black_box : boolean;
attribute fpga_dont_touch: string;
attribute box_type : string;
attribute keep : string;
attribute syn_keep : boolean;
function std_logic_vector_to_unsigned(inp : std_logic_vector) return unsigned;
function unsigned_to_std_logic_vector(inp : unsigned) return std_logic_vector;
function std_logic_vector_to_signed(inp : std_logic_vector) return signed;
function signed_to_std_logic_vector(inp : signed) return std_logic_vector;
function unsigned_to_signed(inp : unsigned) return signed;
function signed_to_unsigned(inp : signed) return unsigned;
function pos(inp : std_logic_vector; arith : INTEGER) return boolean;
function all_same(inp: std_logic_vector) return boolean;
function all_zeros(inp: std_logic_vector) return boolean;
function is_point_five(inp: std_logic_vector) return boolean;
function all_ones(inp: std_logic_vector) return boolean;
function convert_type (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith,
quantization, overflow : INTEGER)
return std_logic_vector;
function cast (inp : std_logic_vector; old_bin_pt,
new_width, new_bin_pt, new_arith : INTEGER)
return std_logic_vector;
function shift_division_result(quotient, fraction: std_logic_vector;
fraction_width, shift_value, shift_dir: INTEGER)
return std_logic_vector;
function shift_op (inp: std_logic_vector;
result_width, shift_value, shift_dir: INTEGER)
return std_logic_vector;
function vec_slice (inp : std_logic_vector; upper, lower : INTEGER)
return std_logic_vector;
function s2u_slice (inp : signed; upper, lower : INTEGER)
return unsigned;
function u2u_slice (inp : unsigned; upper, lower : INTEGER)
return unsigned;
function s2s_cast (inp : signed; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return signed;
function u2s_cast (inp : unsigned; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return signed;
function s2u_cast (inp : signed; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return unsigned;
function u2u_cast (inp : unsigned; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return unsigned;
function u2v_cast (inp : unsigned; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return std_logic_vector;
function s2v_cast (inp : signed; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return std_logic_vector;
function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith,
new_width, new_bin_pt, new_arith : INTEGER)
return std_logic_vector;
function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt,
new_arith : INTEGER) return std_logic_vector;
function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt,
new_arith : INTEGER) return std_logic_vector;
function max_signed(width : INTEGER) return std_logic_vector;
function min_signed(width : INTEGER) return std_logic_vector;
function saturation_arith(inp: std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith
: INTEGER) return std_logic_vector;
function wrap_arith(inp: std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith : INTEGER)
return std_logic_vector;
function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER;
function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER)
return INTEGER;
function sign_ext(inp : std_logic_vector; new_width : INTEGER)
return std_logic_vector;
function zero_ext(inp : std_logic_vector; new_width : INTEGER)
return std_logic_vector;
function zero_ext(inp : std_logic; new_width : INTEGER)
return std_logic_vector;
function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER)
return std_logic_vector;
function align_input(inp : std_logic_vector; old_width, delta, new_arith,
new_width: INTEGER)
return std_logic_vector;
function pad_LSB(inp : std_logic_vector; new_width: integer)
return std_logic_vector;
function pad_LSB(inp : std_logic_vector; new_width, arith : integer)
return std_logic_vector;
function max(L, R: INTEGER) return INTEGER;
function min(L, R: INTEGER) return INTEGER;
function "="(left,right: STRING) return boolean;
function boolean_to_signed (inp : boolean; width: integer)
return signed;
function boolean_to_unsigned (inp : boolean; width: integer)
return unsigned;
function boolean_to_vector (inp : boolean)
return std_logic_vector;
function std_logic_to_vector (inp : std_logic)
return std_logic_vector;
function integer_to_std_logic_vector (inp : integer; width, arith : integer)
return std_logic_vector;
function std_logic_vector_to_integer (inp : std_logic_vector; arith : integer)
return integer;
function std_logic_to_integer(constant inp : std_logic := '0')
return integer;
function bin_string_element_to_std_logic_vector (inp : string; width, index : integer)
return std_logic_vector;
function bin_string_to_std_logic_vector (inp : string)
return std_logic_vector;
function hex_string_to_std_logic_vector (inp : string; width : integer)
return std_logic_vector;
function makeZeroBinStr (width : integer) return STRING;
function and_reduce(inp: std_logic_vector) return std_logic;
-- synopsys translate_off
function is_binary_string_invalid (inp : string)
return boolean;
function is_binary_string_undefined (inp : string)
return boolean;
function is_XorU(inp : std_logic_vector)
return boolean;
function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer)
return real;
function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer)
return real;
function real_to_std_logic_vector (inp : real; width, bin_pt, arith : integer)
return std_logic_vector;
function real_string_to_std_logic_vector (inp : string; width, bin_pt, arith : integer)
return std_logic_vector;
constant display_precision : integer := 20;
function real_to_string (inp : real) return string;
function valid_bin_string(inp : string) return boolean;
function std_logic_vector_to_bin_string(inp : std_logic_vector) return string;
function std_logic_to_bin_string(inp : std_logic) return string;
function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer)
return string;
function real_to_bin_string(inp : real; width, bin_pt, arith : integer)
return string;
type stdlogic_to_char_t is array(std_logic) of character;
constant to_char : stdlogic_to_char_t := (
'U' => 'U',
'X' => 'X',
'0' => '0',
'1' => '1',
'Z' => 'Z',
'W' => 'W',
'L' => 'L',
'H' => 'H',
'-' => '-');
-- synopsys translate_on
end conv_pkg;
package body conv_pkg is
function std_logic_vector_to_unsigned(inp : std_logic_vector)
return unsigned
is
begin
return unsigned (inp);
end;
function unsigned_to_std_logic_vector(inp : unsigned)
return std_logic_vector
is
begin
return std_logic_vector(inp);
end;
function std_logic_vector_to_signed(inp : std_logic_vector)
return signed
is
begin
return signed (inp);
end;
function signed_to_std_logic_vector(inp : signed)
return std_logic_vector
is
begin
return std_logic_vector(inp);
end;
function unsigned_to_signed (inp : unsigned)
return signed
is
begin
return signed(std_logic_vector(inp));
end;
function signed_to_unsigned (inp : signed)
return unsigned
is
begin
return unsigned(std_logic_vector(inp));
end;
function pos(inp : std_logic_vector; arith : INTEGER)
return boolean
is
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
begin
vec := inp;
if arith = xlUnsigned then
return true;
else
if vec(width-1) = '0' then
return true;
else
return false;
end if;
end if;
return true;
end;
function max_signed(width : INTEGER)
return std_logic_vector
is
variable ones : std_logic_vector(width-2 downto 0);
variable result : std_logic_vector(width-1 downto 0);
begin
ones := (others => '1');
result(width-1) := '0';
result(width-2 downto 0) := ones;
return result;
end;
function min_signed(width : INTEGER)
return std_logic_vector
is
variable zeros : std_logic_vector(width-2 downto 0);
variable result : std_logic_vector(width-1 downto 0);
begin
zeros := (others => '0');
result(width-1) := '1';
result(width-2 downto 0) := zeros;
return result;
end;
function and_reduce(inp: std_logic_vector) return std_logic
is
variable result: std_logic;
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
begin
vec := inp;
result := vec(0);
if width > 1 then
for i in 1 to width-1 loop
result := result and vec(i);
end loop;
end if;
return result;
end;
function all_same(inp: std_logic_vector) return boolean
is
variable result: boolean;
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
begin
vec := inp;
result := true;
if width > 0 then
for i in 1 to width-1 loop
if vec(i) /= vec(0) then
result := false;
end if;
end loop;
end if;
return result;
end;
function all_zeros(inp: std_logic_vector)
return boolean
is
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
variable zero : std_logic_vector(width-1 downto 0);
variable result : boolean;
begin
zero := (others => '0');
vec := inp;
-- synopsys translate_off
if (is_XorU(vec)) then
return false;
end if;
-- synopsys translate_on
if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(zero)) then
result := true;
else
result := false;
end if;
return result;
end;
function is_point_five(inp: std_logic_vector)
return boolean
is
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
variable result : boolean;
begin
vec := inp;
-- synopsys translate_off
if (is_XorU(vec)) then
return false;
end if;
-- synopsys translate_on
if (width > 1) then
if ((vec(width-1) = '1') and (all_zeros(vec(width-2 downto 0)) = true)) then
result := true;
else
result := false;
end if;
else
if (vec(width-1) = '1') then
result := true;
else
result := false;
end if;
end if;
return result;
end;
function all_ones(inp: std_logic_vector)
return boolean
is
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
variable one : std_logic_vector(width-1 downto 0);
variable result : boolean;
begin
one := (others => '1');
vec := inp;
-- synopsys translate_off
if (is_XorU(vec)) then
return false;
end if;
-- synopsys translate_on
if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(one)) then
result := true;
else
result := false;
end if;
return result;
end;
function full_precision_num_width(quantization, overflow, old_width,
old_bin_pt, old_arith,
new_width, new_bin_pt, new_arith : INTEGER)
return integer
is
variable result : integer;
begin
result := old_width + 2;
return result;
end;
function quantized_num_width(quantization, overflow, old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith
: INTEGER)
return integer
is
variable right_of_dp, left_of_dp, result : integer;
begin
right_of_dp := max(new_bin_pt, old_bin_pt);
left_of_dp := max((new_width - new_bin_pt), (old_width - old_bin_pt));
result := (old_width + 2) + (new_bin_pt - old_bin_pt);
return result;
end;
function convert_type (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith,
quantization, overflow : INTEGER)
return std_logic_vector
is
constant fp_width : integer :=
full_precision_num_width(quantization, overflow, old_width,
old_bin_pt, old_arith, new_width,
new_bin_pt, new_arith);
constant fp_bin_pt : integer := old_bin_pt;
constant fp_arith : integer := old_arith;
variable full_precision_result : std_logic_vector(fp_width-1 downto 0);
constant q_width : integer :=
quantized_num_width(quantization, overflow, old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith);
constant q_bin_pt : integer := new_bin_pt;
constant q_arith : integer := old_arith;
variable quantized_result : std_logic_vector(q_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
result := (others => '0');
full_precision_result := cast(inp, old_bin_pt, fp_width, fp_bin_pt,
fp_arith);
if (quantization = xlRound) then
quantized_result := round_towards_inf(full_precision_result,
fp_width, fp_bin_pt,
fp_arith, q_width, q_bin_pt,
q_arith);
elsif (quantization = xlRoundBanker) then
quantized_result := round_towards_even(full_precision_result,
fp_width, fp_bin_pt,
fp_arith, q_width, q_bin_pt,
q_arith);
else
quantized_result := trunc(full_precision_result, fp_width, fp_bin_pt,
fp_arith, q_width, q_bin_pt, q_arith);
end if;
if (overflow = xlSaturate) then
result := saturation_arith(quantized_result, q_width, q_bin_pt,
q_arith, new_width, new_bin_pt, new_arith);
else
result := wrap_arith(quantized_result, q_width, q_bin_pt, q_arith,
new_width, new_bin_pt, new_arith);
end if;
return result;
end;
function cast (inp : std_logic_vector; old_bin_pt, new_width,
new_bin_pt, new_arith : INTEGER)
return std_logic_vector
is
constant old_width : integer := inp'length;
constant left_of_dp : integer := (new_width - new_bin_pt)
- (old_width - old_bin_pt);
constant right_of_dp : integer := (new_bin_pt - old_bin_pt);
variable vec : std_logic_vector(old_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
variable j : integer;
begin
vec := inp;
for i in new_width-1 downto 0 loop
j := i - right_of_dp;
if ( j > old_width-1) then
if (new_arith = xlUnsigned) then
result(i) := '0';
else
result(i) := vec(old_width-1);
end if;
elsif ( j >= 0) then
result(i) := vec(j);
else
result(i) := '0';
end if;
end loop;
return result;
end;
function shift_division_result(quotient, fraction: std_logic_vector;
fraction_width, shift_value, shift_dir: INTEGER)
return std_logic_vector
is
constant q_width : integer := quotient'length;
constant f_width : integer := fraction'length;
constant vec_MSB : integer := q_width+f_width-1;
constant result_MSB : integer := q_width+fraction_width-1;
constant result_LSB : integer := vec_MSB-result_MSB;
variable vec : std_logic_vector(vec_MSB downto 0);
variable result : std_logic_vector(result_MSB downto 0);
begin
vec := ( quotient & fraction );
if shift_dir = 1 then
for i in vec_MSB downto 0 loop
if (i < shift_value) then
vec(i) := '0';
else
vec(i) := vec(i-shift_value);
end if;
end loop;
else
for i in 0 to vec_MSB loop
if (i > vec_MSB-shift_value) then
vec(i) := vec(vec_MSB);
else
vec(i) := vec(i+shift_value);
end if;
end loop;
end if;
result := vec(vec_MSB downto result_LSB);
return result;
end;
function shift_op (inp: std_logic_vector;
result_width, shift_value, shift_dir: INTEGER)
return std_logic_vector
is
constant inp_width : integer := inp'length;
constant vec_MSB : integer := inp_width-1;
constant result_MSB : integer := result_width-1;
constant result_LSB : integer := vec_MSB-result_MSB;
variable vec : std_logic_vector(vec_MSB downto 0);
variable result : std_logic_vector(result_MSB downto 0);
begin
vec := inp;
if shift_dir = 1 then
for i in vec_MSB downto 0 loop
if (i < shift_value) then
vec(i) := '0';
else
vec(i) := vec(i-shift_value);
end if;
end loop;
else
for i in 0 to vec_MSB loop
if (i > vec_MSB-shift_value) then
vec(i) := vec(vec_MSB);
else
vec(i) := vec(i+shift_value);
end if;
end loop;
end if;
result := vec(vec_MSB downto result_LSB);
return result;
end;
function vec_slice (inp : std_logic_vector; upper, lower : INTEGER)
return std_logic_vector
is
begin
return inp(upper downto lower);
end;
function s2u_slice (inp : signed; upper, lower : INTEGER)
return unsigned
is
begin
return unsigned(vec_slice(std_logic_vector(inp), upper, lower));
end;
function u2u_slice (inp : unsigned; upper, lower : INTEGER)
return unsigned
is
begin
return unsigned(vec_slice(std_logic_vector(inp), upper, lower));
end;
function s2s_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER)
return signed
is
begin
return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned));
end;
function s2u_cast (inp : signed; old_bin_pt, new_width,
new_bin_pt : INTEGER)
return unsigned
is
begin
return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned));
end;
function u2s_cast (inp : unsigned; old_bin_pt, new_width,
new_bin_pt : INTEGER)
return signed
is
begin
return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned));
end;
function u2u_cast (inp : unsigned; old_bin_pt, new_width,
new_bin_pt : INTEGER)
return unsigned
is
begin
return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned));
end;
function u2v_cast (inp : unsigned; old_bin_pt, new_width,
new_bin_pt : INTEGER)
return std_logic_vector
is
begin
return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned);
end;
function s2v_cast (inp : signed; old_bin_pt, new_width,
new_bin_pt : INTEGER)
return std_logic_vector
is
begin
return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned);
end;
function boolean_to_signed (inp : boolean; width : integer)
return signed
is
variable result : signed(width - 1 downto 0);
begin
result := (others => '0');
if inp then
result(0) := '1';
else
result(0) := '0';
end if;
return result;
end;
function boolean_to_unsigned (inp : boolean; width : integer)
return unsigned
is
variable result : unsigned(width - 1 downto 0);
begin
result := (others => '0');
if inp then
result(0) := '1';
else
result(0) := '0';
end if;
return result;
end;
function boolean_to_vector (inp : boolean)
return std_logic_vector
is
variable result : std_logic_vector(1 - 1 downto 0);
begin
result := (others => '0');
if inp then
result(0) := '1';
else
result(0) := '0';
end if;
return result;
end;
function std_logic_to_vector (inp : std_logic)
return std_logic_vector
is
variable result : std_logic_vector(1 - 1 downto 0);
begin
result(0) := inp;
return result;
end;
function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith,
new_width, new_bin_pt, new_arith : INTEGER)
return std_logic_vector
is
constant right_of_dp : integer := (old_bin_pt - new_bin_pt);
variable vec : std_logic_vector(old_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if right_of_dp >= 0 then
if new_arith = xlUnsigned then
result := zero_ext(vec(old_width-1 downto right_of_dp), new_width);
else
result := sign_ext(vec(old_width-1 downto right_of_dp), new_width);
end if;
else
if new_arith = xlUnsigned then
result := zero_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
else
result := sign_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
end if;
end if;
return result;
end;
function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith
: INTEGER)
return std_logic_vector
is
constant right_of_dp : integer := (old_bin_pt - new_bin_pt);
constant expected_new_width : integer := old_width - right_of_dp + 1;
variable vec : std_logic_vector(old_width-1 downto 0);
variable one_or_zero : std_logic_vector(new_width-1 downto 0);
variable truncated_val : std_logic_vector(new_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if right_of_dp >= 0 then
if new_arith = xlUnsigned then
truncated_val := zero_ext(vec(old_width-1 downto right_of_dp),
new_width);
else
truncated_val := sign_ext(vec(old_width-1 downto right_of_dp),
new_width);
end if;
else
if new_arith = xlUnsigned then
truncated_val := zero_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
else
truncated_val := sign_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
end if;
end if;
one_or_zero := (others => '0');
if (new_arith = xlSigned) then
if (vec(old_width-1) = '0') then
one_or_zero(0) := '1';
end if;
if (right_of_dp >= 2) and (right_of_dp <= old_width) then
if (all_zeros(vec(right_of_dp-2 downto 0)) = false) then
one_or_zero(0) := '1';
end if;
end if;
if (right_of_dp >= 1) and (right_of_dp <= old_width) then
if vec(right_of_dp-1) = '0' then
one_or_zero(0) := '0';
end if;
else
one_or_zero(0) := '0';
end if;
else
if (right_of_dp >= 1) and (right_of_dp <= old_width) then
one_or_zero(0) := vec(right_of_dp-1);
end if;
end if;
if new_arith = xlSigned then
result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) +
std_logic_vector_to_signed(one_or_zero));
else
result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) +
std_logic_vector_to_unsigned(one_or_zero));
end if;
return result;
end;
function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith
: INTEGER)
return std_logic_vector
is
constant right_of_dp : integer := (old_bin_pt - new_bin_pt);
constant expected_new_width : integer := old_width - right_of_dp + 1;
variable vec : std_logic_vector(old_width-1 downto 0);
variable one_or_zero : std_logic_vector(new_width-1 downto 0);
variable truncated_val : std_logic_vector(new_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if right_of_dp >= 0 then
if new_arith = xlUnsigned then
truncated_val := zero_ext(vec(old_width-1 downto right_of_dp),
new_width);
else
truncated_val := sign_ext(vec(old_width-1 downto right_of_dp),
new_width);
end if;
else
if new_arith = xlUnsigned then
truncated_val := zero_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
else
truncated_val := sign_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
end if;
end if;
one_or_zero := (others => '0');
if (right_of_dp >= 1) and (right_of_dp <= old_width) then
if (is_point_five(vec(right_of_dp-1 downto 0)) = false) then
one_or_zero(0) := vec(right_of_dp-1);
else
one_or_zero(0) := vec(right_of_dp);
end if;
end if;
if new_arith = xlSigned then
result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) +
std_logic_vector_to_signed(one_or_zero));
else
result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) +
std_logic_vector_to_unsigned(one_or_zero));
end if;
return result;
end;
function saturation_arith(inp: std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith
: INTEGER)
return std_logic_vector
is
constant left_of_dp : integer := (old_width - old_bin_pt) -
(new_width - new_bin_pt);
variable vec : std_logic_vector(old_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
variable overflow : boolean;
begin
vec := inp;
overflow := true;
result := (others => '0');
if (new_width >= old_width) then
overflow := false;
end if;
if ((old_arith = xlSigned and new_arith = xlSigned) and (old_width > new_width)) then
if all_same(vec(old_width-1 downto new_width-1)) then
overflow := false;
end if;
end if;
if (old_arith = xlSigned and new_arith = xlUnsigned) then
if (old_width > new_width) then
if all_zeros(vec(old_width-1 downto new_width)) then
overflow := false;
end if;
else
if (old_width = new_width) then
if (vec(new_width-1) = '0') then
overflow := false;
end if;
end if;
end if;
end if;
if (old_arith = xlUnsigned and new_arith = xlUnsigned) then
if (old_width > new_width) then
if all_zeros(vec(old_width-1 downto new_width)) then
overflow := false;
end if;
else
if (old_width = new_width) then
overflow := false;
end if;
end if;
end if;
if ((old_arith = xlUnsigned and new_arith = xlSigned) and (old_width > new_width)) then
if all_same(vec(old_width-1 downto new_width-1)) then
overflow := false;
end if;
end if;
if overflow then
if new_arith = xlSigned then
if vec(old_width-1) = '0' then
result := max_signed(new_width);
else
result := min_signed(new_width);
end if;
else
if ((old_arith = xlSigned) and vec(old_width-1) = '1') then
result := (others => '0');
else
result := (others => '1');
end if;
end if;
else
if (old_arith = xlSigned) and (new_arith = xlUnsigned) then
if (vec(old_width-1) = '1') then
vec := (others => '0');
end if;
end if;
if new_width <= old_width then
result := vec(new_width-1 downto 0);
else
if new_arith = xlUnsigned then
result := zero_ext(vec, new_width);
else
result := sign_ext(vec, new_width);
end if;
end if;
end if;
return result;
end;
function wrap_arith(inp: std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith : INTEGER)
return std_logic_vector
is
variable result : std_logic_vector(new_width-1 downto 0);
variable result_arith : integer;
begin
if (old_arith = xlSigned) and (new_arith = xlUnsigned) then
result_arith := xlSigned;
end if;
result := cast(inp, old_bin_pt, new_width, new_bin_pt, result_arith);
return result;
end;
function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER is
begin
return max(a_bin_pt, b_bin_pt);
end;
function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER)
return INTEGER is
begin
return max(a_width - a_bin_pt, b_width - b_bin_pt);
end;
function pad_LSB(inp : std_logic_vector; new_width: integer)
return STD_LOGIC_VECTOR
is
constant orig_width : integer := inp'length;
variable vec : std_logic_vector(orig_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
variable pos : integer;
constant pad_pos : integer := new_width - orig_width - 1;
begin
vec := inp;
pos := new_width-1;
if (new_width >= orig_width) then
for i in orig_width-1 downto 0 loop
result(pos) := vec(i);
pos := pos - 1;
end loop;
if pad_pos >= 0 then
for i in pad_pos downto 0 loop
result(i) := '0';
end loop;
end if;
end if;
return result;
end;
function sign_ext(inp : std_logic_vector; new_width : INTEGER)
return std_logic_vector
is
constant old_width : integer := inp'length;
variable vec : std_logic_vector(old_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if new_width >= old_width then
result(old_width-1 downto 0) := vec;
if new_width-1 >= old_width then
for i in new_width-1 downto old_width loop
result(i) := vec(old_width-1);
end loop;
end if;
else
result(new_width-1 downto 0) := vec(new_width-1 downto 0);
end if;
return result;
end;
function zero_ext(inp : std_logic_vector; new_width : INTEGER)
return std_logic_vector
is
constant old_width : integer := inp'length;
variable vec : std_logic_vector(old_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if new_width >= old_width then
result(old_width-1 downto 0) := vec;
if new_width-1 >= old_width then
for i in new_width-1 downto old_width loop
result(i) := '0';
end loop;
end if;
else
result(new_width-1 downto 0) := vec(new_width-1 downto 0);
end if;
return result;
end;
function zero_ext(inp : std_logic; new_width : INTEGER)
return std_logic_vector
is
variable result : std_logic_vector(new_width-1 downto 0);
begin
result(0) := inp;
for i in new_width-1 downto 1 loop
result(i) := '0';
end loop;
return result;
end;
function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER)
return std_logic_vector
is
constant orig_width : integer := inp'length;
variable vec : std_logic_vector(orig_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if arith = xlUnsigned then
result := zero_ext(vec, new_width);
else
result := sign_ext(vec, new_width);
end if;
return result;
end;
function pad_LSB(inp : std_logic_vector; new_width, arith: integer)
return STD_LOGIC_VECTOR
is
constant orig_width : integer := inp'length;
variable vec : std_logic_vector(orig_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
variable pos : integer;
begin
vec := inp;
pos := new_width-1;
if (arith = xlUnsigned) then
result(pos) := '0';
pos := pos - 1;
else
result(pos) := vec(orig_width-1);
pos := pos - 1;
end if;
if (new_width >= orig_width) then
for i in orig_width-1 downto 0 loop
result(pos) := vec(i);
pos := pos - 1;
end loop;
if pos >= 0 then
for i in pos downto 0 loop
result(i) := '0';
end loop;
end if;
end if;
return result;
end;
function align_input(inp : std_logic_vector; old_width, delta, new_arith,
new_width: INTEGER)
return std_logic_vector
is
variable vec : std_logic_vector(old_width-1 downto 0);
variable padded_inp : std_logic_vector((old_width + delta)-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if delta > 0 then
padded_inp := pad_LSB(vec, old_width+delta);
result := extend_MSB(padded_inp, new_width, new_arith);
else
result := extend_MSB(vec, new_width, new_arith);
end if;
return result;
end;
function max(L, R: INTEGER) return INTEGER is
begin
if L > R then
return L;
else
return R;
end if;
end;
function min(L, R: INTEGER) return INTEGER is
begin
if L < R then
return L;
else
return R;
end if;
end;
function "="(left,right: STRING) return boolean is
begin
if (left'length /= right'length) then
return false;
else
test : for i in 1 to left'length loop
if left(i) /= right(i) then
return false;
end if;
end loop test;
return true;
end if;
end;
-- synopsys translate_off
function is_binary_string_invalid (inp : string)
return boolean
is
variable vec : string(1 to inp'length);
variable result : boolean;
begin
vec := inp;
result := false;
for i in 1 to vec'length loop
if ( vec(i) = 'X' ) then
result := true;
end if;
end loop;
return result;
end;
function is_binary_string_undefined (inp : string)
return boolean
is
variable vec : string(1 to inp'length);
variable result : boolean;
begin
vec := inp;
result := false;
for i in 1 to vec'length loop
if ( vec(i) = 'U' ) then
result := true;
end if;
end loop;
return result;
end;
function is_XorU(inp : std_logic_vector)
return boolean
is
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
variable result : boolean;
begin
vec := inp;
result := false;
for i in 0 to width-1 loop
if (vec(i) = 'U') or (vec(i) = 'X') then
result := true;
end if;
end loop;
return result;
end;
function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer)
return real
is
variable vec : std_logic_vector(inp'length-1 downto 0);
variable result, shift_val, undefined_real : real;
variable neg_num : boolean;
begin
vec := inp;
result := 0.0;
neg_num := false;
if vec(inp'length-1) = '1' then
neg_num := true;
end if;
for i in 0 to inp'length-1 loop
if vec(i) = 'U' or vec(i) = 'X' then
return undefined_real;
end if;
if arith = xlSigned then
if neg_num then
if vec(i) = '0' then
result := result + 2.0**i;
end if;
else
if vec(i) = '1' then
result := result + 2.0**i;
end if;
end if;
else
if vec(i) = '1' then
result := result + 2.0**i;
end if;
end if;
end loop;
if arith = xlSigned then
if neg_num then
result := result + 1.0;
result := result * (-1.0);
end if;
end if;
shift_val := 2.0**(-1*bin_pt);
result := result * shift_val;
return result;
end;
function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer)
return real
is
variable result : real := 0.0;
begin
if inp = '1' then
result := 1.0;
end if;
if arith = xlSigned then
assert false
report "It doesn't make sense to convert a 1 bit number to a signed real.";
end if;
return result;
end;
-- synopsys translate_on
function integer_to_std_logic_vector (inp : integer; width, arith : integer)
return std_logic_vector
is
variable result : std_logic_vector(width-1 downto 0);
variable unsigned_val : unsigned(width-1 downto 0);
variable signed_val : signed(width-1 downto 0);
begin
if (arith = xlSigned) then
signed_val := to_signed(inp, width);
result := signed_to_std_logic_vector(signed_val);
else
unsigned_val := to_unsigned(inp, width);
result := unsigned_to_std_logic_vector(unsigned_val);
end if;
return result;
end;
function std_logic_vector_to_integer (inp : std_logic_vector; arith : integer)
return integer
is
constant width : integer := inp'length;
variable unsigned_val : unsigned(width-1 downto 0);
variable signed_val : signed(width-1 downto 0);
variable result : integer;
begin
if (arith = xlSigned) then
signed_val := std_logic_vector_to_signed(inp);
result := to_integer(signed_val);
else
unsigned_val := std_logic_vector_to_unsigned(inp);
result := to_integer(unsigned_val);
end if;
return result;
end;
function std_logic_to_integer(constant inp : std_logic := '0')
return integer
is
begin
if inp = '1' then
return 1;
else
return 0;
end if;
end;
function makeZeroBinStr (width : integer) return STRING is
variable result : string(1 to width+3);
begin
result(1) := '0';
result(2) := 'b';
for i in 3 to width+2 loop
result(i) := '0';
end loop;
result(width+3) := '.';
return result;
end;
-- synopsys translate_off
function real_string_to_std_logic_vector (inp : string; width, bin_pt, arith : integer)
return std_logic_vector
is
variable result : std_logic_vector(width-1 downto 0);
begin
result := (others => '0');
return result;
end;
function real_to_std_logic_vector (inp : real; width, bin_pt, arith : integer)
return std_logic_vector
is
variable real_val : real;
variable int_val : integer;
variable result : std_logic_vector(width-1 downto 0) := (others => '0');
variable unsigned_val : unsigned(width-1 downto 0) := (others => '0');
variable signed_val : signed(width-1 downto 0) := (others => '0');
begin
real_val := inp;
int_val := integer(real_val * 2.0**(bin_pt));
if (arith = xlSigned) then
signed_val := to_signed(int_val, width);
result := signed_to_std_logic_vector(signed_val);
else
unsigned_val := to_unsigned(int_val, width);
result := unsigned_to_std_logic_vector(unsigned_val);
end if;
return result;
end;
-- synopsys translate_on
function valid_bin_string (inp : string)
return boolean
is
variable vec : string(1 to inp'length);
begin
vec := inp;
if (vec(1) = '0' and vec(2) = 'b') then
return true;
else
return false;
end if;
end;
function hex_string_to_std_logic_vector(inp: string; width : integer)
return std_logic_vector is
constant strlen : integer := inp'LENGTH;
variable result : std_logic_vector(width-1 downto 0);
variable bitval : std_logic_vector((strlen*4)-1 downto 0);
variable posn : integer;
variable ch : character;
variable vec : string(1 to strlen);
begin
vec := inp;
result := (others => '0');
posn := (strlen*4)-1;
for i in 1 to strlen loop
ch := vec(i);
case ch is
when '0' => bitval(posn downto posn-3) := "0000";
when '1' => bitval(posn downto posn-3) := "0001";
when '2' => bitval(posn downto posn-3) := "0010";
when '3' => bitval(posn downto posn-3) := "0011";
when '4' => bitval(posn downto posn-3) := "0100";
when '5' => bitval(posn downto posn-3) := "0101";
when '6' => bitval(posn downto posn-3) := "0110";
when '7' => bitval(posn downto posn-3) := "0111";
when '8' => bitval(posn downto posn-3) := "1000";
when '9' => bitval(posn downto posn-3) := "1001";
when 'A' | 'a' => bitval(posn downto posn-3) := "1010";
when 'B' | 'b' => bitval(posn downto posn-3) := "1011";
when 'C' | 'c' => bitval(posn downto posn-3) := "1100";
when 'D' | 'd' => bitval(posn downto posn-3) := "1101";
when 'E' | 'e' => bitval(posn downto posn-3) := "1110";
when 'F' | 'f' => bitval(posn downto posn-3) := "1111";
when others => bitval(posn downto posn-3) := "XXXX";
-- synopsys translate_off
ASSERT false
REPORT "Invalid hex value" SEVERITY ERROR;
-- synopsys translate_on
end case;
posn := posn - 4;
end loop;
if (width <= strlen*4) then
result := bitval(width-1 downto 0);
else
result((strlen*4)-1 downto 0) := bitval;
end if;
return result;
end;
function bin_string_to_std_logic_vector (inp : string)
return std_logic_vector
is
variable pos : integer;
variable vec : string(1 to inp'length);
variable result : std_logic_vector(inp'length-1 downto 0);
begin
vec := inp;
pos := inp'length-1;
result := (others => '0');
for i in 1 to vec'length loop
-- synopsys translate_off
if (pos < 0) and (vec(i) = '0' or vec(i) = '1' or vec(i) = 'X' or vec(i) = 'U') then
assert false
report "Input string is larger than output std_logic_vector. Truncating output.";
return result;
end if;
-- synopsys translate_on
if vec(i) = '0' then
result(pos) := '0';
pos := pos - 1;
end if;
if vec(i) = '1' then
result(pos) := '1';
pos := pos - 1;
end if;
-- synopsys translate_off
if (vec(i) = 'X' or vec(i) = 'U') then
result(pos) := 'U';
pos := pos - 1;
end if;
-- synopsys translate_on
end loop;
return result;
end;
function bin_string_element_to_std_logic_vector (inp : string; width, index : integer)
return std_logic_vector
is
constant str_width : integer := width + 4;
constant inp_len : integer := inp'length;
constant num_elements : integer := (inp_len + 1)/str_width;
constant reverse_index : integer := (num_elements-1) - index;
variable left_pos : integer;
variable right_pos : integer;
variable vec : string(1 to inp'length);
variable result : std_logic_vector(width-1 downto 0);
begin
vec := inp;
result := (others => '0');
if (reverse_index = 0) and (reverse_index < num_elements) and (inp_len-3 >= width) then
left_pos := 1;
right_pos := width + 3;
result := bin_string_to_std_logic_vector(vec(left_pos to right_pos));
end if;
if (reverse_index > 0) and (reverse_index < num_elements) and (inp_len-3 >= width) then
left_pos := (reverse_index * str_width) + 1;
right_pos := left_pos + width + 2;
result := bin_string_to_std_logic_vector(vec(left_pos to right_pos));
end if;
return result;
end;
-- synopsys translate_off
function std_logic_vector_to_bin_string(inp : std_logic_vector)
return string
is
variable vec : std_logic_vector(1 to inp'length);
variable result : string(vec'range);
begin
vec := inp;
for i in vec'range loop
result(i) := to_char(vec(i));
end loop;
return result;
end;
function std_logic_to_bin_string(inp : std_logic)
return string
is
variable result : string(1 to 3);
begin
result(1) := '0';
result(2) := 'b';
result(3) := to_char(inp);
return result;
end;
function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer)
return string
is
variable width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
variable str_pos : integer;
variable result : string(1 to width+3);
begin
vec := inp;
str_pos := 1;
result(str_pos) := '0';
str_pos := 2;
result(str_pos) := 'b';
str_pos := 3;
for i in width-1 downto 0 loop
if (((width+3) - bin_pt) = str_pos) then
result(str_pos) := '.';
str_pos := str_pos + 1;
end if;
result(str_pos) := to_char(vec(i));
str_pos := str_pos + 1;
end loop;
if (bin_pt = 0) then
result(str_pos) := '.';
end if;
return result;
end;
function real_to_bin_string(inp : real; width, bin_pt, arith : integer)
return string
is
variable result : string(1 to width);
variable vec : std_logic_vector(width-1 downto 0);
begin
vec := real_to_std_logic_vector(inp, width, bin_pt, arith);
result := std_logic_vector_to_bin_string(vec);
return result;
end;
function real_to_string (inp : real) return string
is
variable result : string(1 to display_precision) := (others => ' ');
begin
result(real'image(inp)'range) := real'image(inp);
return result;
end;
-- synopsys translate_on
end conv_pkg;
-------------------------------------------------------------------
-- System Generator version 13.2 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
-- synopsys translate_off
library unisim;
use unisim.vcomponents.all;
-- synopsys translate_on
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity srl17e is
generic (width : integer:=16;
latency : integer :=8);
port (clk : in std_logic;
ce : in std_logic;
d : in std_logic_vector(width-1 downto 0);
q : out std_logic_vector(width-1 downto 0));
end srl17e;
architecture structural of srl17e is
component SRL16E
port (D : in STD_ULOGIC;
CE : in STD_ULOGIC;
CLK : in STD_ULOGIC;
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
attribute syn_black_box of SRL16E : component is true;
attribute fpga_dont_touch of SRL16E : component is "true";
component FDE
port(
Q : out STD_ULOGIC;
D : in STD_ULOGIC;
C : in STD_ULOGIC;
CE : in STD_ULOGIC);
end component;
attribute syn_black_box of FDE : component is true;
attribute fpga_dont_touch of FDE : component is "true";
constant a : std_logic_vector(4 downto 0) :=
integer_to_std_logic_vector(latency-2,5,xlSigned);
signal d_delayed : std_logic_vector(width-1 downto 0);
signal srl16_out : std_logic_vector(width-1 downto 0);
begin
d_delayed <= d after 200 ps;
reg_array : for i in 0 to width-1 generate
srl16_used: if latency > 1 generate
u1 : srl16e port map(clk => clk,
d => d_delayed(i),
q => srl16_out(i),
ce => ce,
a0 => a(0),
a1 => a(1),
a2 => a(2),
a3 => a(3));
end generate;
srl16_not_used: if latency <= 1 generate
srl16_out(i) <= d_delayed(i);
end generate;
fde_used: if latency /= 0 generate
u2 : fde port map(c => clk,
d => srl16_out(i),
q => q(i),
ce => ce);
end generate;
fde_not_used: if latency = 0 generate
q(i) <= srl16_out(i);
end generate;
end generate;
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity synth_reg is
generic (width : integer := 8;
latency : integer := 1);
port (i : in std_logic_vector(width-1 downto 0);
ce : in std_logic;
clr : in std_logic;
clk : in std_logic;
o : out std_logic_vector(width-1 downto 0));
end synth_reg;
architecture structural of synth_reg is
component srl17e
generic (width : integer:=16;
latency : integer :=8);
port (clk : in std_logic;
ce : in std_logic;
d : in std_logic_vector(width-1 downto 0);
q : out std_logic_vector(width-1 downto 0));
end component;
function calc_num_srl17es (latency : integer)
return integer
is
variable remaining_latency : integer;
variable result : integer;
begin
result := latency / 17;
remaining_latency := latency - (result * 17);
if (remaining_latency /= 0) then
result := result + 1;
end if;
return result;
end;
constant complete_num_srl17es : integer := latency / 17;
constant num_srl17es : integer := calc_num_srl17es(latency);
constant remaining_latency : integer := latency - (complete_num_srl17es * 17);
type register_array is array (num_srl17es downto 0) of
std_logic_vector(width-1 downto 0);
signal z : register_array;
begin
z(0) <= i;
complete_ones : if complete_num_srl17es > 0 generate
srl17e_array: for i in 0 to complete_num_srl17es-1 generate
delay_comp : srl17e
generic map (width => width,
latency => 17)
port map (clk => clk,
ce => ce,
d => z(i),
q => z(i+1));
end generate;
end generate;
partial_one : if remaining_latency > 0 generate
last_srl17e : srl17e
generic map (width => width,
latency => remaining_latency)
port map (clk => clk,
ce => ce,
d => z(num_srl17es-1),
q => z(num_srl17es));
end generate;
o <= z(num_srl17es);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity synth_reg_reg is
generic (width : integer := 8;
latency : integer := 1);
port (i : in std_logic_vector(width-1 downto 0);
ce : in std_logic;
clr : in std_logic;
clk : in std_logic;
o : out std_logic_vector(width-1 downto 0));
end synth_reg_reg;
architecture behav of synth_reg_reg is
type reg_array_type is array (latency-1 downto 0) of std_logic_vector(width -1 downto 0);
signal reg_bank : reg_array_type := (others => (others => '0'));
signal reg_bank_in : reg_array_type := (others => (others => '0'));
attribute syn_allow_retiming : boolean;
attribute syn_srlstyle : string;
attribute syn_allow_retiming of reg_bank : signal is true;
attribute syn_allow_retiming of reg_bank_in : signal is true;
attribute syn_srlstyle of reg_bank : signal is "registers";
attribute syn_srlstyle of reg_bank_in : signal is "registers";
begin
latency_eq_0: if latency = 0 generate
o <= i;
end generate latency_eq_0;
latency_gt_0: if latency >= 1 generate
o <= reg_bank(latency-1);
reg_bank_in(0) <= i;
loop_gen: for idx in latency-2 downto 0 generate
reg_bank_in(idx+1) <= reg_bank(idx);
end generate loop_gen;
sync_loop: for sync_idx in latency-1 downto 0 generate
sync_proc: process (clk)
begin
if clk'event and clk = '1' then
if clr = '1' then
reg_bank_in <= (others => (others => '0'));
elsif ce = '1' then
reg_bank(sync_idx) <= reg_bank_in(sync_idx);
end if;
end if;
end process sync_proc;
end generate sync_loop;
end generate latency_gt_0;
end behav;
-------------------------------------------------------------------
-- System Generator version 13.2 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
-- synopsys translate_off
library unisim;
use unisim.vcomponents.all;
-- synopsys translate_on
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity single_reg_w_init is
generic (
width: integer := 8;
init_index: integer := 0;
init_value: bit_vector := b"0000"
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end single_reg_w_init;
architecture structural of single_reg_w_init is
function build_init_const(width: integer;
init_index: integer;
init_value: bit_vector)
return std_logic_vector
is
variable result: std_logic_vector(width - 1 downto 0);
begin
if init_index = 0 then
result := (others => '0');
elsif init_index = 1 then
result := (others => '0');
result(0) := '1';
else
result := to_stdlogicvector(init_value);
end if;
return result;
end;
component fdre
port (
q: out std_ulogic;
d: in std_ulogic;
c: in std_ulogic;
ce: in std_ulogic;
r: in std_ulogic
);
end component;
attribute syn_black_box of fdre: component is true;
attribute fpga_dont_touch of fdre: component is "true";
component fdse
port (
q: out std_ulogic;
d: in std_ulogic;
c: in std_ulogic;
ce: in std_ulogic;
s: in std_ulogic
);
end component;
attribute syn_black_box of fdse: component is true;
attribute fpga_dont_touch of fdse: component is "true";
constant init_const: std_logic_vector(width - 1 downto 0)
:= build_init_const(width, init_index, init_value);
begin
fd_prim_array: for index in 0 to width - 1 generate
bit_is_0: if (init_const(index) = '0') generate
fdre_comp: fdre
port map (
c => clk,
d => i(index),
q => o(index),
ce => ce,
r => clr
);
end generate;
bit_is_1: if (init_const(index) = '1') generate
fdse_comp: fdse
port map (
c => clk,
d => i(index),
q => o(index),
ce => ce,
s => clr
);
end generate;
end generate;
end architecture structural;
-- synopsys translate_off
library unisim;
use unisim.vcomponents.all;
-- synopsys translate_on
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity synth_reg_w_init is
generic (
width: integer := 8;
init_index: integer := 0;
init_value: bit_vector := b"0000";
latency: integer := 1
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end synth_reg_w_init;
architecture structural of synth_reg_w_init is
component single_reg_w_init
generic (
width: integer := 8;
init_index: integer := 0;
init_value: bit_vector := b"0000"
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end component;
signal dly_i: std_logic_vector((latency + 1) * width - 1 downto 0);
signal dly_clr: std_logic;
begin
latency_eq_0: if (latency = 0) generate
o <= i;
end generate;
latency_gt_0: if (latency >= 1) generate
dly_i((latency + 1) * width - 1 downto latency * width) <= i
after 200 ps;
dly_clr <= clr after 200 ps;
fd_array: for index in latency downto 1 generate
reg_comp: single_reg_w_init
generic map (
width => width,
init_index => init_index,
init_value => init_value
)
port map (
clk => clk,
i => dly_i((index + 1) * width - 1 downto index * width),
o => dly_i(index * width - 1 downto (index - 1) * width),
ce => ce,
clr => dly_clr
);
end generate;
o <= dly_i(width - 1 downto 0);
end generate;
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity mux_029cd20aa9 is
port (
sel : in std_logic_vector((1 - 1) downto 0);
d0 : in std_logic_vector((22 - 1) downto 0);
d1 : in std_logic_vector((23 - 1) downto 0);
y : out std_logic_vector((23 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end mux_029cd20aa9;
architecture behavior of mux_029cd20aa9 is
signal sel_1_20: std_logic_vector((1 - 1) downto 0);
signal d0_1_24: std_logic_vector((22 - 1) downto 0);
signal d1_1_27: std_logic_vector((23 - 1) downto 0);
type array_type_pipe_16_22 is array (0 to (1 - 1)) of std_logic_vector((23 - 1) downto 0);
signal pipe_16_22: array_type_pipe_16_22 := (
0 => "00000000000000000000000");
signal pipe_16_22_front_din: std_logic_vector((23 - 1) downto 0);
signal pipe_16_22_back: std_logic_vector((23 - 1) downto 0);
signal pipe_16_22_push_front_pop_back_en: std_logic;
signal unregy_join_6_1: std_logic_vector((23 - 1) downto 0);
begin
sel_1_20 <= sel;
d0_1_24 <= d0;
d1_1_27 <= d1;
pipe_16_22_back <= pipe_16_22(0);
proc_pipe_16_22: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (pipe_16_22_push_front_pop_back_en = '1')) then
pipe_16_22(0) <= pipe_16_22_front_din;
end if;
end if;
end process proc_pipe_16_22;
proc_switch_6_1: process (d0_1_24, d1_1_27, sel_1_20)
is
begin
case sel_1_20 is
when "0" =>
unregy_join_6_1 <= cast(d0_1_24, 0, 23, 0, xlSigned);
when others =>
unregy_join_6_1 <= d1_1_27;
end case;
end process proc_switch_6_1;
pipe_16_22_front_din <= unregy_join_6_1;
pipe_16_22_push_front_pop_back_en <= '1';
y <= pipe_16_22_back;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity negate_142bd36a06 is
port (
ip : in std_logic_vector((22 - 1) downto 0);
op : out std_logic_vector((23 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end negate_142bd36a06;
architecture behavior of negate_142bd36a06 is
signal ip_18_25: signed((22 - 1) downto 0);
type array_type_op_mem_42_20 is array (0 to (1 - 1)) of signed((23 - 1) downto 0);
signal op_mem_42_20: array_type_op_mem_42_20 := (
0 => "00000000000000000000000");
signal op_mem_42_20_front_din: signed((23 - 1) downto 0);
signal op_mem_42_20_back: signed((23 - 1) downto 0);
signal op_mem_42_20_push_front_pop_back_en: std_logic;
signal cast_30_16: signed((23 - 1) downto 0);
signal internal_ip_30_1_neg: signed((23 - 1) downto 0);
begin
ip_18_25 <= std_logic_vector_to_signed(ip);
op_mem_42_20_back <= op_mem_42_20(0);
proc_op_mem_42_20: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (op_mem_42_20_push_front_pop_back_en = '1')) then
op_mem_42_20(0) <= op_mem_42_20_front_din;
end if;
end if;
end process proc_op_mem_42_20;
cast_30_16 <= s2s_cast(ip_18_25, 0, 23, 0);
internal_ip_30_1_neg <= -cast_30_16;
op_mem_42_20_front_din <= internal_ip_30_1_neg;
op_mem_42_20_push_front_pop_back_en <= '1';
op <= signed_to_std_logic_vector(op_mem_42_20_back);
end behavior;
-------------------------------------------------------------------
-- System Generator version 13.2 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity xlregister is
generic (d_width : integer := 5;
init_value : bit_vector := b"00");
port (d : in std_logic_vector (d_width-1 downto 0);
rst : in std_logic_vector(0 downto 0) := "0";
en : in std_logic_vector(0 downto 0) := "1";
ce : in std_logic;
clk : in std_logic;
q : out std_logic_vector (d_width-1 downto 0));
end xlregister;
architecture behavior of xlregister is
component synth_reg_w_init
generic (width : integer;
init_index : integer;
init_value : bit_vector;
latency : integer);
port (i : in std_logic_vector(width-1 downto 0);
ce : in std_logic;
clr : in std_logic;
clk : in std_logic;
o : out std_logic_vector(width-1 downto 0));
end component;
-- synopsys translate_off
signal real_d, real_q : real;
-- synopsys translate_on
signal internal_clr : std_logic;
signal internal_ce : std_logic;
begin
internal_clr <= rst(0) and ce;
internal_ce <= en(0) and ce;
synth_reg_inst : synth_reg_w_init
generic map (width => d_width,
init_index => 2,
init_value => init_value,
latency => 1)
port map (i => d,
ce => internal_ce,
clr => internal_clr,
clk => clk,
o => q);
end architecture behavior;
-------------------------------------------------------------------
-- System Generator version 13.2 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.conv_pkg.all;
entity xlslice is
generic (
new_msb : integer := 9;
new_lsb : integer := 1;
x_width : integer := 16;
y_width : integer := 8);
port (
x : in std_logic_vector (x_width-1 downto 0);
y : out std_logic_vector (y_width-1 downto 0));
end xlslice;
architecture behavior of xlslice is
begin
y <= x(new_msb downto new_lsb);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant_822933f89b is
port (
op : out std_logic_vector((3 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end constant_822933f89b;
architecture behavior of constant_822933f89b is
begin
op <= "000";
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant_a1c496ea88 is
port (
op : out std_logic_vector((3 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end constant_a1c496ea88;
architecture behavior of constant_a1c496ea88 is
begin
op <= "001";
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant_1f5cc32f1e is
port (
op : out std_logic_vector((3 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end constant_1f5cc32f1e;
architecture behavior of constant_1f5cc32f1e is
begin
op <= "010";
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant_0f59f02ba5 is
port (
op : out std_logic_vector((3 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end constant_0f59f02ba5;
architecture behavior of constant_0f59f02ba5 is
begin
op <= "011";
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant_469094441c is
port (
op : out std_logic_vector((3 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end constant_469094441c;
architecture behavior of constant_469094441c is
begin
op <= "100";
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity logical_80f90b97d0 is
port (
d0 : in std_logic_vector((1 - 1) downto 0);
d1 : in std_logic_vector((1 - 1) downto 0);
y : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end logical_80f90b97d0;
architecture behavior of logical_80f90b97d0 is
signal d0_1_24: std_logic;
signal d1_1_27: std_logic;
signal fully_2_1_bit: std_logic;
begin
d0_1_24 <= d0(0);
d1_1_27 <= d1(0);
fully_2_1_bit <= d0_1_24 and d1_1_27;
y <= std_logic_to_vector(fully_2_1_bit);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity relational_8fc7f5539b is
port (
a : in std_logic_vector((3 - 1) downto 0);
b : in std_logic_vector((3 - 1) downto 0);
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end relational_8fc7f5539b;
architecture behavior of relational_8fc7f5539b is
signal a_1_31: unsigned((3 - 1) downto 0);
signal b_1_34: unsigned((3 - 1) downto 0);
signal result_12_3_rel: boolean;
begin
a_1_31 <= std_logic_vector_to_unsigned(a);
b_1_34 <= std_logic_vector_to_unsigned(b);
result_12_3_rel <= a_1_31 = b_1_34;
op <= boolean_to_vector(result_12_3_rel);
end behavior;
-------------------------------------------------------------------
-- System Generator version 13.2 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
-- synopsys translate_off
library XilinxCoreLib;
-- synopsys translate_on
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity xlcounter_limit is
generic (
core_name0: string := "";
op_width: integer := 5;
op_arith: integer := xlSigned;
cnt_63_48: integer:= 0;
cnt_47_32: integer:= 0;
cnt_31_16: integer:= 0;
cnt_15_0: integer:= 0;
count_limited: integer := 0
);
port (
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
op: out std_logic_vector(op_width - 1 downto 0);
up: in std_logic_vector(0 downto 0) := (others => '0');
en: in std_logic_vector(0 downto 0);
rst: in std_logic_vector(0 downto 0)
);
end xlcounter_limit ;
architecture behavior of xlcounter_limit is
signal high_cnt_to: std_logic_vector(31 downto 0);
signal low_cnt_to: std_logic_vector(31 downto 0);
signal cnt_to: std_logic_vector(63 downto 0);
signal core_sinit, op_thresh0, core_ce: std_logic;
signal rst_overrides_en: std_logic;
signal op_net: std_logic_vector(op_width - 1 downto 0);
-- synopsys translate_off
signal real_op : real;
-- synopsys translate_on
function equals(op, cnt_to : std_logic_vector; width, arith : integer)
return std_logic
is
variable signed_op, signed_cnt_to : signed (width - 1 downto 0);
variable unsigned_op, unsigned_cnt_to : unsigned (width - 1 downto 0);
variable result : std_logic;
begin
-- synopsys translate_off
if ((is_XorU(op)) or (is_XorU(cnt_to)) ) then
result := '0';
return result;
end if;
-- synopsys translate_on
if (op = cnt_to) then
result := '1';
else
result := '0';
end if;
return result;
end;
component cntr_11_0_e859c6662c373192
port (
clk: in std_logic;
ce: in std_logic;
SINIT: in std_logic;
q: out std_logic_vector(op_width - 1 downto 0)
);
end component;
attribute syn_black_box of cntr_11_0_e859c6662c373192:
component is true;
attribute fpga_dont_touch of cntr_11_0_e859c6662c373192:
component is "true";
attribute box_type of cntr_11_0_e859c6662c373192:
component is "black_box";
component cntr_11_0_862f833518f4973a
port (
clk: in std_logic;
ce: in std_logic;
SINIT: in std_logic;
q: out std_logic_vector(op_width - 1 downto 0)
);
end component;
attribute syn_black_box of cntr_11_0_862f833518f4973a:
component is true;
attribute fpga_dont_touch of cntr_11_0_862f833518f4973a:
component is "true";
attribute box_type of cntr_11_0_862f833518f4973a:
component is "black_box";
-- synopsys translate_off
constant zeroVec : std_logic_vector(op_width - 1 downto 0) := (others => '0');
constant oneVec : std_logic_vector(op_width - 1 downto 0) := (others => '1');
constant zeroStr : string(1 to op_width) :=
std_logic_vector_to_bin_string(zeroVec);
constant oneStr : string(1 to op_width) :=
std_logic_vector_to_bin_string(oneVec);
-- synopsys translate_on
begin
-- synopsys translate_off
-- synopsys translate_on
cnt_to(63 downto 48) <= integer_to_std_logic_vector(cnt_63_48, 16, op_arith);
cnt_to(47 downto 32) <= integer_to_std_logic_vector(cnt_47_32, 16, op_arith);
cnt_to(31 downto 16) <= integer_to_std_logic_vector(cnt_31_16, 16, op_arith);
cnt_to(15 downto 0) <= integer_to_std_logic_vector(cnt_15_0, 16, op_arith);
op <= op_net;
core_ce <= ce and en(0);
rst_overrides_en <= rst(0) or en(0);
limit : if (count_limited = 1) generate
eq_cnt_to : process (op_net, cnt_to)
begin
op_thresh0 <= equals(op_net, cnt_to(op_width - 1 downto 0),
op_width, op_arith);
end process;
core_sinit <= (op_thresh0 or clr or rst(0)) and ce and rst_overrides_en;
end generate;
no_limit : if (count_limited = 0) generate
core_sinit <= (clr or rst(0)) and ce and rst_overrides_en;
end generate;
comp0: if ((core_name0 = "cntr_11_0_e859c6662c373192")) generate
core_instance0: cntr_11_0_e859c6662c373192
port map (
clk => clk,
ce => core_ce,
SINIT => core_sinit,
q => op_net
);
end generate;
comp1: if ((core_name0 = "cntr_11_0_862f833518f4973a")) generate
core_instance1: cntr_11_0_862f833518f4973a
port map (
clk => clk,
ce => core_ce,
SINIT => core_sinit,
q => op_net
);
end generate;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity inverter_e5b38cca3b is
port (
ip : in std_logic_vector((1 - 1) downto 0);
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end inverter_e5b38cca3b;
architecture behavior of inverter_e5b38cca3b is
signal ip_1_26: boolean;
type array_type_op_mem_22_20 is array (0 to (1 - 1)) of boolean;
signal op_mem_22_20: array_type_op_mem_22_20 := (
0 => false);
signal op_mem_22_20_front_din: boolean;
signal op_mem_22_20_back: boolean;
signal op_mem_22_20_push_front_pop_back_en: std_logic;
signal internal_ip_12_1_bitnot: boolean;
begin
ip_1_26 <= ((ip) = "1");
op_mem_22_20_back <= op_mem_22_20(0);
proc_op_mem_22_20: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (op_mem_22_20_push_front_pop_back_en = '1')) then
op_mem_22_20(0) <= op_mem_22_20_front_din;
end if;
end if;
end process proc_op_mem_22_20;
internal_ip_12_1_bitnot <= ((not boolean_to_vector(ip_1_26)) = "1");
op_mem_22_20_push_front_pop_back_en <= '0';
op <= boolean_to_vector(internal_ip_12_1_bitnot);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity xlfir_compiler_d885873ecd26cf15cdb95a5d10c7a292 is
port(
ce:in std_logic;
ce_logic_1:in std_logic;
clk:in std_logic;
clk_logic_1:in std_logic;
coef_din:in std_logic_vector(6 downto 0);
coef_ld:in std_logic;
coef_we:in std_logic;
din:in std_logic_vector(7 downto 0);
dout:out std_logic_vector(18 downto 0);
rdy:out std_logic;
rfd:out std_logic;
src_ce:in std_logic;
src_clk:in std_logic
);
end xlfir_compiler_d885873ecd26cf15cdb95a5d10c7a292;
architecture behavior of xlfir_compiler_d885873ecd26cf15cdb95a5d10c7a292 is
component fr_cmplr_v5_0_0d2261239884a389
port(
ce:in std_logic;
clk:in std_logic;
coef_din:in std_logic_vector(6 downto 0);
coef_ld:in std_logic;
coef_we:in std_logic;
din:in std_logic_vector(7 downto 0);
dout:out std_logic_vector(18 downto 0);
nd:in std_logic;
rdy:out std_logic;
rfd:out std_logic
);
end component;
begin
fr_cmplr_v5_0_0d2261239884a389_instance : fr_cmplr_v5_0_0d2261239884a389
port map(
ce=>ce,
clk=>clk,
coef_din=>coef_din,
coef_ld=>coef_ld,
coef_we=>coef_we,
din=>din,
dout=>dout,
nd=>ce_logic_1,
rdy=>rdy,
rfd=>rfd
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity xlfir_compiler_1e4b453df468e83a1cea0a55c8d9b90f is
port(
ce:in std_logic;
ce_logic_1:in std_logic;
clk:in std_logic;
clk_logic_1:in std_logic;
coef_din:in std_logic_vector(6 downto 0);
coef_ld:in std_logic;
coef_we:in std_logic;
din:in std_logic_vector(7 downto 0);
dout:out std_logic_vector(18 downto 0);
rdy:out std_logic;
rfd:out std_logic;
src_ce:in std_logic;
src_clk:in std_logic
);
end xlfir_compiler_1e4b453df468e83a1cea0a55c8d9b90f;
architecture behavior of xlfir_compiler_1e4b453df468e83a1cea0a55c8d9b90f is
component fr_cmplr_v5_0_983c85a69a3a58e7
port(
ce:in std_logic;
clk:in std_logic;
coef_din:in std_logic_vector(6 downto 0);
coef_ld:in std_logic;
coef_we:in std_logic;
din:in std_logic_vector(7 downto 0);
dout:out std_logic_vector(18 downto 0);
nd:in std_logic;
rdy:out std_logic;
rfd:out std_logic
);
end component;
begin
fr_cmplr_v5_0_983c85a69a3a58e7_instance : fr_cmplr_v5_0_983c85a69a3a58e7
port map(
ce=>ce,
clk=>clk,
coef_din=>coef_din,
coef_ld=>coef_ld,
coef_we=>coef_we,
din=>din,
dout=>dout,
nd=>ce_logic_1,
rdy=>rdy,
rfd=>rfd
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity xlfir_compiler_5077ad6f33cdc3f379ad80845501c286 is
port(
ce:in std_logic;
ce_logic_1:in std_logic;
clk:in std_logic;
clk_logic_1:in std_logic;
coef_din:in std_logic_vector(6 downto 0);
coef_ld:in std_logic;
coef_we:in std_logic;
din:in std_logic_vector(7 downto 0);
dout:out std_logic_vector(18 downto 0);
rdy:out std_logic;
rfd:out std_logic;
src_ce:in std_logic;
src_clk:in std_logic
);
end xlfir_compiler_5077ad6f33cdc3f379ad80845501c286;
architecture behavior of xlfir_compiler_5077ad6f33cdc3f379ad80845501c286 is
component fr_cmplr_v5_0_bc5286c4b0615582
port(
ce:in std_logic;
clk:in std_logic;
coef_din:in std_logic_vector(6 downto 0);
coef_ld:in std_logic;
coef_we:in std_logic;
din:in std_logic_vector(7 downto 0);
dout:out std_logic_vector(18 downto 0);
nd:in std_logic;
rdy:out std_logic;
rfd:out std_logic
);
end component;
begin
fr_cmplr_v5_0_bc5286c4b0615582_instance : fr_cmplr_v5_0_bc5286c4b0615582
port map(
ce=>ce,
clk=>clk,
coef_din=>coef_din,
coef_ld=>coef_ld,
coef_we=>coef_we,
din=>din,
dout=>dout,
nd=>ce_logic_1,
rdy=>rdy,
rfd=>rfd
);
end behavior;
-------------------------------------------------------------------
-- System Generator version 13.2 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
-- synopsys translate_off
library XilinxCoreLib;
-- synopsys translate_on
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.conv_pkg.all;
entity xladdsub is
generic (
core_name0: string := "";
a_width: integer := 16;
a_bin_pt: integer := 4;
a_arith: integer := xlUnsigned;
c_in_width: integer := 16;
c_in_bin_pt: integer := 4;
c_in_arith: integer := xlUnsigned;
c_out_width: integer := 16;
c_out_bin_pt: integer := 4;
c_out_arith: integer := xlUnsigned;
b_width: integer := 8;
b_bin_pt: integer := 2;
b_arith: integer := xlUnsigned;
s_width: integer := 17;
s_bin_pt: integer := 4;
s_arith: integer := xlUnsigned;
rst_width: integer := 1;
rst_bin_pt: integer := 0;
rst_arith: integer := xlUnsigned;
en_width: integer := 1;
en_bin_pt: integer := 0;
en_arith: integer := xlUnsigned;
full_s_width: integer := 17;
full_s_arith: integer := xlUnsigned;
mode: integer := xlAddMode;
extra_registers: integer := 0;
latency: integer := 0;
quantization: integer := xlTruncate;
overflow: integer := xlWrap;
c_latency: integer := 0;
c_output_width: integer := 17;
c_has_c_in : integer := 0;
c_has_c_out : integer := 0
);
port (
a: in std_logic_vector(a_width - 1 downto 0);
b: in std_logic_vector(b_width - 1 downto 0);
c_in : in std_logic_vector (0 downto 0) := "0";
ce: in std_logic;
clr: in std_logic := '0';
clk: in std_logic;
rst: in std_logic_vector(rst_width - 1 downto 0) := "0";
en: in std_logic_vector(en_width - 1 downto 0) := "1";
c_out : out std_logic_vector (0 downto 0);
s: out std_logic_vector(s_width - 1 downto 0)
);
end xladdsub;
architecture behavior of xladdsub is
component synth_reg
generic (
width: integer := 16;
latency: integer := 5
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end component;
function format_input(inp: std_logic_vector; old_width, delta, new_arith,
new_width: integer)
return std_logic_vector
is
variable vec: std_logic_vector(old_width-1 downto 0);
variable padded_inp: std_logic_vector((old_width + delta)-1 downto 0);
variable result: std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if (delta > 0) then
padded_inp := pad_LSB(vec, old_width+delta);
result := extend_MSB(padded_inp, new_width, new_arith);
else
result := extend_MSB(vec, new_width, new_arith);
end if;
return result;
end;
constant full_s_bin_pt: integer := fractional_bits(a_bin_pt, b_bin_pt);
constant full_a_width: integer := full_s_width;
constant full_b_width: integer := full_s_width;
signal full_a: std_logic_vector(full_a_width - 1 downto 0);
signal full_b: std_logic_vector(full_b_width - 1 downto 0);
signal core_s: std_logic_vector(full_s_width - 1 downto 0);
signal conv_s: std_logic_vector(s_width - 1 downto 0);
signal temp_cout : std_logic;
signal internal_clr: std_logic;
signal internal_ce: std_logic;
signal extra_reg_ce: std_logic;
signal override: std_logic;
signal logic1: std_logic_vector(0 downto 0);
component addsb_11_0_e7b4231f2ca96446
port (
a: in std_logic_vector(22 - 1 downto 0);
clk: in std_logic:= '0';
ce: in std_logic:= '0';
s: out std_logic_vector(c_output_width - 1 downto 0);
b: in std_logic_vector(22 - 1 downto 0)
);
end component;
attribute syn_black_box of addsb_11_0_e7b4231f2ca96446:
component is true;
attribute fpga_dont_touch of addsb_11_0_e7b4231f2ca96446:
component is "true";
attribute box_type of addsb_11_0_e7b4231f2ca96446:
component is "black_box";
component addsb_11_0_da33f2d4b3b54185
port (
a: in std_logic_vector(20 - 1 downto 0);
clk: in std_logic:= '0';
ce: in std_logic:= '0';
s: out std_logic_vector(c_output_width - 1 downto 0);
b: in std_logic_vector(20 - 1 downto 0)
);
end component;
attribute syn_black_box of addsb_11_0_da33f2d4b3b54185:
component is true;
attribute fpga_dont_touch of addsb_11_0_da33f2d4b3b54185:
component is "true";
attribute box_type of addsb_11_0_da33f2d4b3b54185:
component is "black_box";
component addsb_11_0_48bcbc42a6774592
port (
a: in std_logic_vector(21 - 1 downto 0);
clk: in std_logic:= '0';
ce: in std_logic:= '0';
s: out std_logic_vector(c_output_width - 1 downto 0);
b: in std_logic_vector(21 - 1 downto 0)
);
end component;
attribute syn_black_box of addsb_11_0_48bcbc42a6774592:
component is true;
attribute fpga_dont_touch of addsb_11_0_48bcbc42a6774592:
component is "true";
attribute box_type of addsb_11_0_48bcbc42a6774592:
component is "black_box";
begin
internal_clr <= (clr or (rst(0))) and ce;
internal_ce <= ce and en(0);
logic1(0) <= '1';
addsub_process: process (a, b, core_s)
begin
full_a <= format_input (a, a_width, b_bin_pt - a_bin_pt, a_arith,
full_a_width);
full_b <= format_input (b, b_width, a_bin_pt - b_bin_pt, b_arith,
full_b_width);
conv_s <= convert_type (core_s, full_s_width, full_s_bin_pt, full_s_arith,
s_width, s_bin_pt, s_arith, quantization, overflow);
end process addsub_process;
comp0: if ((core_name0 = "addsb_11_0_e7b4231f2ca96446")) generate
core_instance0: addsb_11_0_e7b4231f2ca96446
port map (
a => full_a,
clk => clk,
ce => internal_ce,
s => core_s,
b => full_b
);
end generate;
comp1: if ((core_name0 = "addsb_11_0_da33f2d4b3b54185")) generate
core_instance1: addsb_11_0_da33f2d4b3b54185
port map (
a => full_a,
clk => clk,
ce => internal_ce,
s => core_s,
b => full_b
);
end generate;
comp2: if ((core_name0 = "addsb_11_0_48bcbc42a6774592")) generate
core_instance2: addsb_11_0_48bcbc42a6774592
port map (
a => full_a,
clk => clk,
ce => internal_ce,
s => core_s,
b => full_b
);
end generate;
latency_test: if (extra_registers > 0) generate
override_test: if (c_latency > 1) generate
override_pipe: synth_reg
generic map (
width => 1,
latency => c_latency
)
port map (
i => logic1,
ce => internal_ce,
clr => internal_clr,
clk => clk,
o(0) => override);
extra_reg_ce <= ce and en(0) and override;
end generate override_test;
no_override: if ((c_latency = 0) or (c_latency = 1)) generate
extra_reg_ce <= ce and en(0);
end generate no_override;
extra_reg: synth_reg
generic map (
width => s_width,
latency => extra_registers
)
port map (
i => conv_s,
ce => extra_reg_ce,
clr => internal_clr,
clk => clk,
o => s
);
cout_test: if (c_has_c_out = 1) generate
c_out_extra_reg: synth_reg
generic map (
width => 1,
latency => extra_registers
)
port map (
i(0) => temp_cout,
ce => extra_reg_ce,
clr => internal_clr,
clk => clk,
o => c_out
);
end generate cout_test;
end generate;
latency_s: if ((latency = 0) or (extra_registers = 0)) generate
s <= conv_s;
end generate latency_s;
latency0: if (((latency = 0) or (extra_registers = 0)) and
(c_has_c_out = 1)) generate
c_out(0) <= temp_cout;
end generate latency0;
tie_dangling_cout: if (c_has_c_out = 0) generate
c_out <= "0";
end generate tie_dangling_cout;
end architecture behavior;
-------------------------------------------------------------------
-- System Generator version 13.2 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity xlpassthrough is
generic (
din_width : integer := 16;
dout_width : integer := 16
);
port (
din : in std_logic_vector (din_width-1 downto 0);
dout : out std_logic_vector (dout_width-1 downto 0));
end xlpassthrough;
architecture passthrough_arch of xlpassthrough is
begin
dout <= din;
end passthrough_arch;
-------------------------------------------------------------------
-- System Generator version 13.2 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity convert_func_call is
generic (
din_width : integer := 16;
din_bin_pt : integer := 4;
din_arith : integer := xlUnsigned;
dout_width : integer := 8;
dout_bin_pt : integer := 2;
dout_arith : integer := xlUnsigned;
quantization : integer := xlTruncate;
overflow : integer := xlWrap);
port (
din : in std_logic_vector (din_width-1 downto 0);
result : out std_logic_vector (dout_width-1 downto 0));
end convert_func_call;
architecture behavior of convert_func_call is
begin
result <= convert_type(din, din_width, din_bin_pt, din_arith,
dout_width, dout_bin_pt, dout_arith,
quantization, overflow);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity xlconvert is
generic (
din_width : integer := 16;
din_bin_pt : integer := 4;
din_arith : integer := xlUnsigned;
dout_width : integer := 8;
dout_bin_pt : integer := 2;
dout_arith : integer := xlUnsigned;
en_width : integer := 1;
en_bin_pt : integer := 0;
en_arith : integer := xlUnsigned;
bool_conversion : integer :=0;
latency : integer := 0;
quantization : integer := xlTruncate;
overflow : integer := xlWrap);
port (
din : in std_logic_vector (din_width-1 downto 0);
en : in std_logic_vector (en_width-1 downto 0);
ce : in std_logic;
clr : in std_logic;
clk : in std_logic;
dout : out std_logic_vector (dout_width-1 downto 0));
end xlconvert;
architecture behavior of xlconvert is
component synth_reg
generic (width : integer;
latency : integer);
port (i : in std_logic_vector(width-1 downto 0);
ce : in std_logic;
clr : in std_logic;
clk : in std_logic;
o : out std_logic_vector(width-1 downto 0));
end component;
component convert_func_call
generic (
din_width : integer := 16;
din_bin_pt : integer := 4;
din_arith : integer := xlUnsigned;
dout_width : integer := 8;
dout_bin_pt : integer := 2;
dout_arith : integer := xlUnsigned;
quantization : integer := xlTruncate;
overflow : integer := xlWrap);
port (
din : in std_logic_vector (din_width-1 downto 0);
result : out std_logic_vector (dout_width-1 downto 0));
end component;
-- synopsys translate_off
-- synopsys translate_on
signal result : std_logic_vector(dout_width-1 downto 0);
signal internal_ce : std_logic;
begin
-- synopsys translate_off
-- synopsys translate_on
internal_ce <= ce and en(0);
bool_conversion_generate : if (bool_conversion = 1)
generate
result <= din;
end generate;
std_conversion_generate : if (bool_conversion = 0)
generate
convert : convert_func_call
generic map (
din_width => din_width,
din_bin_pt => din_bin_pt,
din_arith => din_arith,
dout_width => dout_width,
dout_bin_pt => dout_bin_pt,
dout_arith => dout_arith,
quantization => quantization,
overflow => overflow)
port map (
din => din,
result => result);
end generate;
latency_test : if (latency > 0) generate
reg : synth_reg
generic map (
width => dout_width,
latency => latency
)
port map (
i => result,
ce => internal_ce,
clr => clr,
clk => clk,
o => dout
);
end generate;
latency0 : if (latency = 0)
generate
dout <= result;
end generate latency0;
end behavior;
-------------------------------------------------------------------
-- System Generator version 13.2 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
-- synopsys translate_off
library XilinxCoreLib;
-- synopsys translate_on
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.conv_pkg.all;
entity xlmult is
generic (
core_name0: string := "";
a_width: integer := 4;
a_bin_pt: integer := 2;
a_arith: integer := xlSigned;
b_width: integer := 4;
b_bin_pt: integer := 1;
b_arith: integer := xlSigned;
p_width: integer := 8;
p_bin_pt: integer := 2;
p_arith: integer := xlSigned;
rst_width: integer := 1;
rst_bin_pt: integer := 0;
rst_arith: integer := xlUnsigned;
en_width: integer := 1;
en_bin_pt: integer := 0;
en_arith: integer := xlUnsigned;
quantization: integer := xlTruncate;
overflow: integer := xlWrap;
extra_registers: integer := 0;
c_a_width: integer := 7;
c_b_width: integer := 7;
c_type: integer := 0;
c_a_type: integer := 0;
c_b_type: integer := 0;
c_pipelined: integer := 1;
c_baat: integer := 4;
multsign: integer := xlSigned;
c_output_width: integer := 16
);
port (
a: in std_logic_vector(a_width - 1 downto 0);
b: in std_logic_vector(b_width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
core_ce: in std_logic := '0';
core_clr: in std_logic := '0';
core_clk: in std_logic := '0';
rst: in std_logic_vector(rst_width - 1 downto 0);
en: in std_logic_vector(en_width - 1 downto 0);
p: out std_logic_vector(p_width - 1 downto 0)
);
end xlmult;
architecture behavior of xlmult is
component synth_reg
generic (
width: integer := 16;
latency: integer := 5
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end component;
component mult_11_2_fe92ad55b7635191
port (
b: in std_logic_vector(c_b_width - 1 downto 0);
p: out std_logic_vector(c_output_width - 1 downto 0);
clk: in std_logic;
ce: in std_logic;
sclr: in std_logic;
a: in std_logic_vector(c_a_width - 1 downto 0)
);
end component;
attribute syn_black_box of mult_11_2_fe92ad55b7635191:
component is true;
attribute fpga_dont_touch of mult_11_2_fe92ad55b7635191:
component is "true";
attribute box_type of mult_11_2_fe92ad55b7635191:
component is "black_box";
signal tmp_a: std_logic_vector(c_a_width - 1 downto 0);
signal conv_a: std_logic_vector(c_a_width - 1 downto 0);
signal tmp_b: std_logic_vector(c_b_width - 1 downto 0);
signal conv_b: std_logic_vector(c_b_width - 1 downto 0);
signal tmp_p: std_logic_vector(c_output_width - 1 downto 0);
signal conv_p: std_logic_vector(p_width - 1 downto 0);
-- synopsys translate_off
signal real_a, real_b, real_p: real;
-- synopsys translate_on
signal rfd: std_logic;
signal rdy: std_logic;
signal nd: std_logic;
signal internal_ce: std_logic;
signal internal_clr: std_logic;
signal internal_core_ce: std_logic;
begin
-- synopsys translate_off
-- synopsys translate_on
internal_ce <= ce and en(0);
internal_core_ce <= core_ce and en(0);
internal_clr <= (clr or rst(0)) and ce;
nd <= internal_ce;
input_process: process (a,b)
begin
tmp_a <= zero_ext(a, c_a_width);
tmp_b <= zero_ext(b, c_b_width);
end process;
output_process: process (tmp_p)
begin
conv_p <= convert_type(tmp_p, c_output_width, a_bin_pt+b_bin_pt, multsign,
p_width, p_bin_pt, p_arith, quantization, overflow);
end process;
comp0: if ((core_name0 = "mult_11_2_fe92ad55b7635191")) generate
core_instance0: mult_11_2_fe92ad55b7635191
port map (
a => tmp_a,
clk => clk,
ce => internal_ce,
sclr => internal_clr,
p => tmp_p,
b => tmp_b
);
end generate;
latency_gt_0: if (extra_registers > 0) generate
reg: synth_reg
generic map (
width => p_width,
latency => extra_registers
)
port map (
i => conv_p,
ce => internal_ce,
clr => internal_clr,
clk => clk,
o => p
);
end generate;
latency_eq_0: if (extra_registers = 0) generate
p <= conv_p;
end generate;
end architecture behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant_6293007044 is
port (
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end constant_6293007044;
architecture behavior of constant_6293007044 is
begin
op <= "1";
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity delay_23f848c85b is
port (
d : in std_logic_vector((8 - 1) downto 0);
q : out std_logic_vector((8 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end delay_23f848c85b;
architecture behavior of delay_23f848c85b is
signal d_1_22: std_logic_vector((8 - 1) downto 0);
type array_type_op_mem_20_24 is array (0 to (2 - 1)) of std_logic_vector((8 - 1) downto 0);
signal op_mem_20_24: array_type_op_mem_20_24 := (
"00000000",
"00000000");
signal op_mem_20_24_front_din: std_logic_vector((8 - 1) downto 0);
signal op_mem_20_24_back: std_logic_vector((8 - 1) downto 0);
signal op_mem_20_24_push_front_pop_back_en: std_logic;
begin
d_1_22 <= d;
op_mem_20_24_back <= op_mem_20_24(1);
proc_op_mem_20_24: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (op_mem_20_24_push_front_pop_back_en = '1')) then
for i in 1 downto 1 loop
op_mem_20_24(i) <= op_mem_20_24(i-1);
end loop;
op_mem_20_24(0) <= op_mem_20_24_front_din;
end if;
end if;
end process proc_op_mem_20_24;
op_mem_20_24_front_din <= d_1_22;
op_mem_20_24_push_front_pop_back_en <= '1';
q <= op_mem_20_24_back;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity delay_9565135955 is
port (
d : in std_logic_vector((8 - 1) downto 0);
q : out std_logic_vector((8 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end delay_9565135955;
architecture behavior of delay_9565135955 is
signal d_1_22: std_logic_vector((8 - 1) downto 0);
type array_type_op_mem_20_24 is array (0 to (3 - 1)) of std_logic_vector((8 - 1) downto 0);
signal op_mem_20_24: array_type_op_mem_20_24 := (
"00000000",
"00000000",
"00000000");
signal op_mem_20_24_front_din: std_logic_vector((8 - 1) downto 0);
signal op_mem_20_24_back: std_logic_vector((8 - 1) downto 0);
signal op_mem_20_24_push_front_pop_back_en: std_logic;
begin
d_1_22 <= d;
op_mem_20_24_back <= op_mem_20_24(2);
proc_op_mem_20_24: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (op_mem_20_24_push_front_pop_back_en = '1')) then
for i in 2 downto 1 loop
op_mem_20_24(i) <= op_mem_20_24(i-1);
end loop;
op_mem_20_24(0) <= op_mem_20_24_front_din;
end if;
end if;
end process proc_op_mem_20_24;
op_mem_20_24_front_din <= d_1_22;
op_mem_20_24_push_front_pop_back_en <= '1';
q <= op_mem_20_24_back;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity delay_fb08f2e938 is
port (
d : in std_logic_vector((8 - 1) downto 0);
q : out std_logic_vector((8 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end delay_fb08f2e938;
architecture behavior of delay_fb08f2e938 is
signal d_1_22: std_logic_vector((8 - 1) downto 0);
type array_type_op_mem_20_24 is array (0 to (4 - 1)) of std_logic_vector((8 - 1) downto 0);
signal op_mem_20_24: array_type_op_mem_20_24 := (
"00000000",
"00000000",
"00000000",
"00000000");
signal op_mem_20_24_front_din: std_logic_vector((8 - 1) downto 0);
signal op_mem_20_24_back: std_logic_vector((8 - 1) downto 0);
signal op_mem_20_24_push_front_pop_back_en: std_logic;
begin
d_1_22 <= d;
op_mem_20_24_back <= op_mem_20_24(3);
proc_op_mem_20_24: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (op_mem_20_24_push_front_pop_back_en = '1')) then
for i in 3 downto 1 loop
op_mem_20_24(i) <= op_mem_20_24(i-1);
end loop;
op_mem_20_24(0) <= op_mem_20_24_front_din;
end if;
end if;
end process proc_op_mem_20_24;
op_mem_20_24_front_din <= d_1_22;
op_mem_20_24_push_front_pop_back_en <= '1';
q <= op_mem_20_24_back;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity delay_ebec135d8a is
port (
d : in std_logic_vector((8 - 1) downto 0);
q : out std_logic_vector((8 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end delay_ebec135d8a;
architecture behavior of delay_ebec135d8a is
signal d_1_22: std_logic_vector((8 - 1) downto 0);
type array_type_op_mem_20_24 is array (0 to (1 - 1)) of std_logic_vector((8 - 1) downto 0);
signal op_mem_20_24: array_type_op_mem_20_24 := (
0 => "00000000");
signal op_mem_20_24_front_din: std_logic_vector((8 - 1) downto 0);
signal op_mem_20_24_back: std_logic_vector((8 - 1) downto 0);
signal op_mem_20_24_push_front_pop_back_en: std_logic;
begin
d_1_22 <= d;
op_mem_20_24_back <= op_mem_20_24(0);
proc_op_mem_20_24: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (op_mem_20_24_push_front_pop_back_en = '1')) then
op_mem_20_24(0) <= op_mem_20_24_front_din;
end if;
end if;
end process proc_op_mem_20_24;
op_mem_20_24_front_din <= d_1_22;
op_mem_20_24_push_front_pop_back_en <= '1';
q <= op_mem_20_24_back;
end behavior;
-------------------------------------------------------------------
-- System Generator version 13.2 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity xlspram is
generic (
core_name0: string := "";
c_width: integer := 12;
c_address_width: integer := 4;
latency: integer := 1
);
port (
data_in: in std_logic_vector(c_width - 1 downto 0);
addr: in std_logic_vector(c_address_width - 1 downto 0);
we: in std_logic_vector(0 downto 0);
en: in std_logic_vector(0 downto 0);
rst: in std_logic_vector(0 downto 0);
ce: in std_logic;
clk: in std_logic;
data_out: out std_logic_vector(c_width - 1 downto 0)
);
end xlspram ;
architecture behavior of xlspram is
component synth_reg
generic (
width: integer;
latency: integer
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end component;
signal core_data_out, dly_data_out: std_logic_vector(c_width - 1 downto 0);
signal core_we, core_ce, sinit: std_logic;
component bmg_62_54b11b852dca329b
port (
addra: in std_logic_vector(c_address_width - 1 downto 0);
clka: in std_logic;
dina: in std_logic_vector(c_width - 1 downto 0);
wea: in std_logic_vector(0 downto 0);
ena: in std_logic;
douta: out std_logic_vector(c_width - 1 downto 0)
);
end component;
attribute syn_black_box of bmg_62_54b11b852dca329b:
component is true;
attribute fpga_dont_touch of bmg_62_54b11b852dca329b:
component is "true";
attribute box_type of bmg_62_54b11b852dca329b:
component is "black_box";
component bmg_62_05852d43925e39b8
port (
addra: in std_logic_vector(c_address_width - 1 downto 0);
clka: in std_logic;
dina: in std_logic_vector(c_width - 1 downto 0);
wea: in std_logic_vector(0 downto 0);
ena: in std_logic;
douta: out std_logic_vector(c_width - 1 downto 0)
);
end component;
attribute syn_black_box of bmg_62_05852d43925e39b8:
component is true;
attribute fpga_dont_touch of bmg_62_05852d43925e39b8:
component is "true";
attribute box_type of bmg_62_05852d43925e39b8:
component is "black_box";
begin
data_out <= dly_data_out;
core_we <= we(0);
core_ce <= ce and en(0);
sinit <= rst(0) and ce;
comp0: if ((core_name0 = "bmg_62_54b11b852dca329b")) generate
core_instance0: bmg_62_54b11b852dca329b
port map (
addra => addr,
clka => clk,
dina => data_in,
wea(0) => core_we,
ena => core_ce,
douta => core_data_out
);
end generate;
comp1: if ((core_name0 = "bmg_62_05852d43925e39b8")) generate
core_instance1: bmg_62_05852d43925e39b8
port map (
addra => addr,
clka => clk,
dina => data_in,
wea(0) => core_we,
ena => core_ce,
douta => core_data_out
);
end generate;
latency_test: if (latency > 1) generate
reg: synth_reg
generic map (
width => c_width,
latency => latency - 1
)
port map (
i => core_data_out,
ce => core_ce,
clr => '0',
clk => clk,
o => dly_data_out
);
end generate;
latency_1: if (latency <= 1) generate
dly_data_out <= core_data_out;
end generate;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity delay_38f665f8aa is
port (
d : in std_logic_vector((5 - 1) downto 0);
q : out std_logic_vector((5 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end delay_38f665f8aa;
architecture behavior of delay_38f665f8aa is
signal d_1_22: std_logic_vector((5 - 1) downto 0);
type array_type_op_mem_20_24 is array (0 to (2 - 1)) of std_logic_vector((5 - 1) downto 0);
signal op_mem_20_24: array_type_op_mem_20_24 := (
"00000",
"00000");
signal op_mem_20_24_front_din: std_logic_vector((5 - 1) downto 0);
signal op_mem_20_24_back: std_logic_vector((5 - 1) downto 0);
signal op_mem_20_24_push_front_pop_back_en: std_logic;
begin
d_1_22 <= d;
op_mem_20_24_back <= op_mem_20_24(1);
proc_op_mem_20_24: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (op_mem_20_24_push_front_pop_back_en = '1')) then
for i in 1 downto 1 loop
op_mem_20_24(i) <= op_mem_20_24(i-1);
end loop;
op_mem_20_24(0) <= op_mem_20_24_front_din;
end if;
end if;
end process proc_op_mem_20_24;
op_mem_20_24_front_din <= d_1_22;
op_mem_20_24_push_front_pop_back_en <= '1';
q <= op_mem_20_24_back;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity concat_2b3acb49f4 is
port (
in0 : in std_logic_vector((1 - 1) downto 0);
in1 : in std_logic_vector((1 - 1) downto 0);
in2 : in std_logic_vector((1 - 1) downto 0);
in3 : in std_logic_vector((1 - 1) downto 0);
in4 : in std_logic_vector((1 - 1) downto 0);
y : out std_logic_vector((5 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end concat_2b3acb49f4;
architecture behavior of concat_2b3acb49f4 is
signal in0_1_23: unsigned((1 - 1) downto 0);
signal in1_1_27: unsigned((1 - 1) downto 0);
signal in2_1_31: unsigned((1 - 1) downto 0);
signal in3_1_35: unsigned((1 - 1) downto 0);
signal in4_1_39: unsigned((1 - 1) downto 0);
signal y_2_1_concat: unsigned((5 - 1) downto 0);
begin
in0_1_23 <= std_logic_vector_to_unsigned(in0);
in1_1_27 <= std_logic_vector_to_unsigned(in1);
in2_1_31 <= std_logic_vector_to_unsigned(in2);
in3_1_35 <= std_logic_vector_to_unsigned(in3);
in4_1_39 <= std_logic_vector_to_unsigned(in4);
y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27) & unsigned_to_std_logic_vector(in2_1_31) & unsigned_to_std_logic_vector(in3_1_35) & unsigned_to_std_logic_vector(in4_1_39));
y <= unsigned_to_std_logic_vector(y_2_1_concat);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity delay_4714bdf2a7 is
port (
d : in std_logic_vector((5 - 1) downto 0);
q : out std_logic_vector((5 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end delay_4714bdf2a7;
architecture behavior of delay_4714bdf2a7 is
signal d_1_22: std_logic_vector((5 - 1) downto 0);
type array_type_op_mem_20_24 is array (0 to (26 - 1)) of std_logic_vector((5 - 1) downto 0);
signal op_mem_20_24: array_type_op_mem_20_24 := (
"00000",
"00000",
"00000",
"00000",
"00000",
"00000",
"00000",
"00000",
"00000",
"00000",
"00000",
"00000",
"00000",
"00000",
"00000",
"00000",
"00000",
"00000",
"00000",
"00000",
"00000",
"00000",
"00000",
"00000",
"00000",
"00000");
signal op_mem_20_24_front_din: std_logic_vector((5 - 1) downto 0);
signal op_mem_20_24_back: std_logic_vector((5 - 1) downto 0);
signal op_mem_20_24_push_front_pop_back_en: std_logic;
begin
d_1_22 <= d;
op_mem_20_24_back <= op_mem_20_24(25);
proc_op_mem_20_24: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (op_mem_20_24_push_front_pop_back_en = '1')) then
for i in 25 downto 1 loop
op_mem_20_24(i) <= op_mem_20_24(i-1);
end loop;
op_mem_20_24(0) <= op_mem_20_24_front_din;
end if;
end if;
end process proc_op_mem_20_24;
op_mem_20_24_front_din <= d_1_22;
op_mem_20_24_push_front_pop_back_en <= '1';
q <= op_mem_20_24_back;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant_fdce3802d7 is
port (
op : out std_logic_vector((5 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end constant_fdce3802d7;
architecture behavior of constant_fdce3802d7 is
begin
op <= "11001";
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant_963ed6358a is
port (
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end constant_963ed6358a;
architecture behavior of constant_963ed6358a is
begin
op <= "0";
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant_7244cd602b is
port (
op : out std_logic_vector((7 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end constant_7244cd602b;
architecture behavior of constant_7244cd602b is
begin
op <= "0000000";
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity expr_1e33fcde03 is
port (
a : in std_logic_vector((1 - 1) downto 0);
b : in std_logic_vector((1 - 1) downto 0);
dout : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end expr_1e33fcde03;
architecture behavior of expr_1e33fcde03 is
signal a_1_24: unsigned((1 - 1) downto 0);
signal b_1_27: unsigned((1 - 1) downto 0);
signal bitnot_5_35: unsigned((1 - 1) downto 0);
signal fulldout_5_2_bit: unsigned((1 - 1) downto 0);
begin
a_1_24 <= std_logic_vector_to_unsigned(a);
b_1_27 <= std_logic_vector_to_unsigned(b);
bitnot_5_35 <= std_logic_vector_to_unsigned(not unsigned_to_std_logic_vector(a_1_24));
fulldout_5_2_bit <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(b_1_27) and unsigned_to_std_logic_vector(bitnot_5_35));
dout <= unsigned_to_std_logic_vector(fulldout_5_2_bit);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity inverter_e2b989a05e is
port (
ip : in std_logic_vector((1 - 1) downto 0);
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end inverter_e2b989a05e;
architecture behavior of inverter_e2b989a05e is
signal ip_1_26: unsigned((1 - 1) downto 0);
type array_type_op_mem_22_20 is array (0 to (1 - 1)) of unsigned((1 - 1) downto 0);
signal op_mem_22_20: array_type_op_mem_22_20 := (
0 => "0");
signal op_mem_22_20_front_din: unsigned((1 - 1) downto 0);
signal op_mem_22_20_back: unsigned((1 - 1) downto 0);
signal op_mem_22_20_push_front_pop_back_en: std_logic;
signal internal_ip_12_1_bitnot: unsigned((1 - 1) downto 0);
begin
ip_1_26 <= std_logic_vector_to_unsigned(ip);
op_mem_22_20_back <= op_mem_22_20(0);
proc_op_mem_22_20: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (op_mem_22_20_push_front_pop_back_en = '1')) then
op_mem_22_20(0) <= op_mem_22_20_front_din;
end if;
end if;
end process proc_op_mem_22_20;
internal_ip_12_1_bitnot <= std_logic_vector_to_unsigned(not unsigned_to_std_logic_vector(ip_1_26));
op_mem_22_20_push_front_pop_back_en <= '0';
op <= unsigned_to_std_logic_vector(internal_ip_12_1_bitnot);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity relational_dc5bc996c9 is
port (
a : in std_logic_vector((5 - 1) downto 0);
b : in std_logic_vector((5 - 1) downto 0);
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end relational_dc5bc996c9;
architecture behavior of relational_dc5bc996c9 is
signal a_1_31: unsigned((5 - 1) downto 0);
signal b_1_34: unsigned((5 - 1) downto 0);
signal result_14_3_rel: boolean;
begin
a_1_31 <= std_logic_vector_to_unsigned(a);
b_1_34 <= std_logic_vector_to_unsigned(b);
result_14_3_rel <= a_1_31 /= b_1_34;
op <= boolean_to_vector(result_14_3_rel);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity addsub_ba7fff8397 is
port (
a : in std_logic_vector((13 - 1) downto 0);
b : in std_logic_vector((12 - 1) downto 0);
s : out std_logic_vector((12 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end addsub_ba7fff8397;
architecture behavior of addsub_ba7fff8397 is
signal a_17_32: signed((13 - 1) downto 0);
signal b_17_35: unsigned((12 - 1) downto 0);
type array_type_op_mem_91_20 is array (0 to (1 - 1)) of unsigned((12 - 1) downto 0);
signal op_mem_91_20: array_type_op_mem_91_20 := (
0 => "000000000000");
signal op_mem_91_20_front_din: unsigned((12 - 1) downto 0);
signal op_mem_91_20_back: unsigned((12 - 1) downto 0);
signal op_mem_91_20_push_front_pop_back_en: std_logic;
type array_type_cout_mem_92_22 is array (0 to (1 - 1)) of unsigned((1 - 1) downto 0);
signal cout_mem_92_22: array_type_cout_mem_92_22 := (
0 => "0");
signal cout_mem_92_22_front_din: unsigned((1 - 1) downto 0);
signal cout_mem_92_22_back: unsigned((1 - 1) downto 0);
signal cout_mem_92_22_push_front_pop_back_en: std_logic;
signal prev_mode_93_22_next: unsigned((3 - 1) downto 0);
signal prev_mode_93_22: unsigned((3 - 1) downto 0);
signal prev_mode_93_22_reg_i: std_logic_vector((3 - 1) downto 0);
signal prev_mode_93_22_reg_o: std_logic_vector((3 - 1) downto 0);
signal cast_69_18: signed((14 - 1) downto 0);
signal cast_69_22: signed((14 - 1) downto 0);
signal internal_s_69_5_addsub: signed((14 - 1) downto 0);
signal cast_internal_s_83_3_convert: unsigned((12 - 1) downto 0);
begin
a_17_32 <= std_logic_vector_to_signed(a);
b_17_35 <= std_logic_vector_to_unsigned(b);
op_mem_91_20_back <= op_mem_91_20(0);
proc_op_mem_91_20: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (op_mem_91_20_push_front_pop_back_en = '1')) then
op_mem_91_20(0) <= op_mem_91_20_front_din;
end if;
end if;
end process proc_op_mem_91_20;
cout_mem_92_22_back <= cout_mem_92_22(0);
proc_cout_mem_92_22: process (clk)
is
variable i_x_000000: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (cout_mem_92_22_push_front_pop_back_en = '1')) then
cout_mem_92_22(0) <= cout_mem_92_22_front_din;
end if;
end if;
end process proc_cout_mem_92_22;
prev_mode_93_22_reg_i <= unsigned_to_std_logic_vector(prev_mode_93_22_next);
prev_mode_93_22 <= std_logic_vector_to_unsigned(prev_mode_93_22_reg_o);
prev_mode_93_22_reg_inst: entity work.synth_reg_w_init
generic map (
init_index => 2,
init_value => b"010",
latency => 1,
width => 3)
port map (
ce => ce,
clk => clk,
clr => clr,
i => prev_mode_93_22_reg_i,
o => prev_mode_93_22_reg_o);
cast_69_18 <= s2s_cast(a_17_32, 0, 14, 0);
cast_69_22 <= u2s_cast(b_17_35, 0, 14, 0);
internal_s_69_5_addsub <= cast_69_18 + cast_69_22;
cast_internal_s_83_3_convert <= s2u_cast(internal_s_69_5_addsub, 0, 12, 0);
op_mem_91_20_push_front_pop_back_en <= '0';
cout_mem_92_22_push_front_pop_back_en <= '0';
prev_mode_93_22_next <= std_logic_vector_to_unsigned("000");
s <= unsigned_to_std_logic_vector(cast_internal_s_83_3_convert);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant_9b805894ff is
port (
op : out std_logic_vector((12 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end constant_9b805894ff;
architecture behavior of constant_9b805894ff is
begin
op <= "111111111111";
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant_7c91b1b314 is
port (
op : out std_logic_vector((12 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end constant_7c91b1b314;
architecture behavior of constant_7c91b1b314 is
begin
op <= "000000000001";
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant_be6eece885 is
port (
op : out std_logic_vector((12 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end constant_be6eece885;
architecture behavior of constant_be6eece885 is
begin
op <= "111111111101";
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity expr_f50101e101 is
port (
reset : in std_logic_vector((1 - 1) downto 0);
tc : in std_logic_vector((1 - 1) downto 0);
dout : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end expr_f50101e101;
architecture behavior of expr_f50101e101 is
signal reset_1_24: boolean;
signal tc_1_31: boolean;
signal bit_5_25: boolean;
signal fulldout_5_2_bitnot: boolean;
begin
reset_1_24 <= ((reset) = "1");
tc_1_31 <= ((tc) = "1");
bit_5_25 <= ((boolean_to_vector(reset_1_24) or boolean_to_vector(tc_1_31)) = "1");
fulldout_5_2_bitnot <= ((not boolean_to_vector(bit_5_25)) = "1");
dout <= boolean_to_vector(fulldout_5_2_bitnot);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity mux_b53670f063 is
port (
sel : in std_logic_vector((1 - 1) downto 0);
d0 : in std_logic_vector((12 - 1) downto 0);
d1 : in std_logic_vector((13 - 1) downto 0);
y : out std_logic_vector((13 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end mux_b53670f063;
architecture behavior of mux_b53670f063 is
signal sel_1_20: std_logic;
signal d0_1_24: std_logic_vector((12 - 1) downto 0);
signal d1_1_27: std_logic_vector((13 - 1) downto 0);
signal sel_internal_2_1_convert: std_logic_vector((1 - 1) downto 0);
signal unregy_join_6_1: std_logic_vector((13 - 1) downto 0);
begin
sel_1_20 <= sel(0);
d0_1_24 <= d0;
d1_1_27 <= d1;
sel_internal_2_1_convert <= cast(std_logic_to_vector(sel_1_20), 0, 1, 0, xlUnsigned);
proc_switch_6_1: process (d0_1_24, d1_1_27, sel_internal_2_1_convert)
is
begin
case sel_internal_2_1_convert is
when "0" =>
unregy_join_6_1 <= cast(d0_1_24, 0, 13, 0, xlSigned);
when others =>
unregy_join_6_1 <= d1_1_27;
end case;
end process proc_switch_6_1;
y <= unregy_join_6_1;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity relational_d36fe12c1c is
port (
a : in std_logic_vector((12 - 1) downto 0);
b : in std_logic_vector((12 - 1) downto 0);
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end relational_d36fe12c1c;
architecture behavior of relational_d36fe12c1c is
signal a_1_31: unsigned((12 - 1) downto 0);
signal b_1_34: unsigned((12 - 1) downto 0);
signal result_12_3_rel: boolean;
begin
a_1_31 <= std_logic_vector_to_unsigned(a);
b_1_34 <= std_logic_vector_to_unsigned(b);
result_12_3_rel <= a_1_31 = b_1_34;
op <= boolean_to_vector(result_12_3_rel);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity delay_9f02caa990 is
port (
d : in std_logic_vector((1 - 1) downto 0);
q : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end delay_9f02caa990;
architecture behavior of delay_9f02caa990 is
signal d_1_22: std_logic;
type array_type_op_mem_20_24 is array (0 to (1 - 1)) of std_logic;
signal op_mem_20_24: array_type_op_mem_20_24 := (
0 => '0');
signal op_mem_20_24_front_din: std_logic;
signal op_mem_20_24_back: std_logic;
signal op_mem_20_24_push_front_pop_back_en: std_logic;
begin
d_1_22 <= d(0);
op_mem_20_24_back <= op_mem_20_24(0);
proc_op_mem_20_24: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (op_mem_20_24_push_front_pop_back_en = '1')) then
op_mem_20_24(0) <= op_mem_20_24_front_din;
end if;
end if;
end process proc_op_mem_20_24;
op_mem_20_24_front_din <= d_1_22;
op_mem_20_24_push_front_pop_back_en <= '1';
q <= std_logic_to_vector(op_mem_20_24_back);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity delay_5753e4c658 is
port (
d : in std_logic_vector((1 - 1) downto 0);
q : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end delay_5753e4c658;
architecture behavior of delay_5753e4c658 is
signal d_1_22: std_logic_vector((1 - 1) downto 0);
type array_type_op_mem_20_24 is array (0 to (1 - 1)) of std_logic_vector((1 - 1) downto 0);
signal op_mem_20_24: array_type_op_mem_20_24 := (
0 => "0");
signal op_mem_20_24_front_din: std_logic_vector((1 - 1) downto 0);
signal op_mem_20_24_back: std_logic_vector((1 - 1) downto 0);
signal op_mem_20_24_push_front_pop_back_en: std_logic;
begin
d_1_22 <= d;
op_mem_20_24_back <= op_mem_20_24(0);
proc_op_mem_20_24: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (op_mem_20_24_push_front_pop_back_en = '1')) then
op_mem_20_24(0) <= op_mem_20_24_front_din;
end if;
end if;
end process proc_op_mem_20_24;
op_mem_20_24_front_din <= d_1_22;
op_mem_20_24_push_front_pop_back_en <= '1';
q <= op_mem_20_24_back;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity expr_305312c97b is
port (
d0 : in std_logic_vector((1 - 1) downto 0);
d1 : in std_logic_vector((1 - 1) downto 0);
rst : in std_logic_vector((1 - 1) downto 0);
dout : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end expr_305312c97b;
architecture behavior of expr_305312c97b is
signal d0_1_24: unsigned((1 - 1) downto 0);
signal d1_1_28: unsigned((1 - 1) downto 0);
signal rst_1_32: unsigned((1 - 1) downto 0);
signal bitnot_6_54: unsigned((1 - 1) downto 0);
signal bit_6_37: unsigned((1 - 1) downto 0);
signal fulldout_6_2_bit: unsigned((1 - 1) downto 0);
begin
d0_1_24 <= std_logic_vector_to_unsigned(d0);
d1_1_28 <= std_logic_vector_to_unsigned(d1);
rst_1_32 <= std_logic_vector_to_unsigned(rst);
bitnot_6_54 <= std_logic_vector_to_unsigned(not unsigned_to_std_logic_vector(d0_1_24));
bit_6_37 <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(d1_1_28) and unsigned_to_std_logic_vector(bitnot_6_54));
fulldout_6_2_bit <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(rst_1_32) or unsigned_to_std_logic_vector(bit_6_37));
dout <= unsigned_to_std_logic_vector(fulldout_6_2_bit);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity mcode_block_f4d0462e0e is
port (
plbrst : in std_logic_vector((1 - 1) downto 0);
plbabus : in std_logic_vector((32 - 1) downto 0);
plbpavalid : in std_logic_vector((1 - 1) downto 0);
plbrnw : in std_logic_vector((1 - 1) downto 0);
plbwrdbus : in std_logic_vector((32 - 1) downto 0);
rddata : in std_logic_vector((32 - 1) downto 0);
addrpref : in std_logic_vector((20 - 1) downto 0);
wrdbusreg : out std_logic_vector((32 - 1) downto 0);
addrack : out std_logic_vector((1 - 1) downto 0);
rdcomp : out std_logic_vector((1 - 1) downto 0);
wrdack : out std_logic_vector((1 - 1) downto 0);
bankaddr : out std_logic_vector((2 - 1) downto 0);
rnwreg : out std_logic_vector((1 - 1) downto 0);
rddack : out std_logic_vector((1 - 1) downto 0);
rddbus : out std_logic_vector((32 - 1) downto 0);
linearaddr : out std_logic_vector((8 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end mcode_block_f4d0462e0e;
architecture behavior of mcode_block_f4d0462e0e is
signal plbrst_1_110: unsigned((1 - 1) downto 0);
signal plbabus_1_118: unsigned((32 - 1) downto 0);
signal plbpavalid_1_127: unsigned((1 - 1) downto 0);
signal plbrnw_1_139: unsigned((1 - 1) downto 0);
signal plbwrdbus_1_147: unsigned((32 - 1) downto 0);
signal rddata_1_158: unsigned((32 - 1) downto 0);
signal addrpref_1_166: unsigned((20 - 1) downto 0);
signal plbrstreg_12_24_next: boolean;
signal plbrstreg_12_24: boolean := false;
signal plbabusreg_13_25_next: unsigned((32 - 1) downto 0);
signal plbabusreg_13_25: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000";
signal plbpavalidreg_14_28_next: boolean;
signal plbpavalidreg_14_28: boolean := false;
signal plbrnwreg_15_24_next: unsigned((1 - 1) downto 0);
signal plbrnwreg_15_24: unsigned((1 - 1) downto 0) := "0";
signal plbwrdbusreg_16_27_next: unsigned((32 - 1) downto 0);
signal plbwrdbusreg_16_27: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000";
signal avalidreg_28_23_next: boolean;
signal avalidreg_28_23: boolean := false;
signal ps1reg_39_20_next: boolean;
signal ps1reg_39_20: boolean := false;
signal psreg_47_19_next: boolean;
signal psreg_47_19: boolean := false;
type array_type_rdcompdelay_58_25 is array (0 to (3 - 1)) of unsigned((1 - 1) downto 0);
signal rdcompdelay_58_25: array_type_rdcompdelay_58_25 := (
"0",
"0",
"0");
signal rdcompdelay_58_25_front_din: unsigned((1 - 1) downto 0);
signal rdcompdelay_58_25_back: unsigned((1 - 1) downto 0);
signal rdcompdelay_58_25_push_front_pop_back_en: std_logic;
signal rdcompreg_62_23_next: unsigned((1 - 1) downto 0);
signal rdcompreg_62_23: unsigned((1 - 1) downto 0) := "0";
signal rddackreg_66_23_next: unsigned((1 - 1) downto 0);
signal rddackreg_66_23: unsigned((1 - 1) downto 0) := "0";
signal wrdackreg_70_23_next: unsigned((1 - 1) downto 0);
signal wrdackreg_70_23: unsigned((1 - 1) downto 0) := "0";
signal rddbusreg_84_23_next: unsigned((32 - 1) downto 0);
signal rddbusreg_84_23: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000";
signal bankaddr_20_1_slice: unsigned((2 - 1) downto 0);
signal linearaddr_21_1_slice: unsigned((8 - 1) downto 0);
signal addrpref_in_32_1_slice: unsigned((20 - 1) downto 0);
signal rel_33_4: boolean;
signal ps1_join_33_1: boolean;
signal ps_42_1_bit: boolean;
signal bitnot_49_49: boolean;
signal bitnot_49_73: boolean;
signal bit_49_49: boolean;
signal addrack_49_1_convert: unsigned((1 - 1) downto 0);
signal bit_55_43: unsigned((1 - 1) downto 0);
signal bitnot_72_35: unsigned((1 - 1) downto 0);
signal wrdackreg_72_1_bit: unsigned((1 - 1) downto 0);
signal rdsel_76_1_bit: unsigned((1 - 1) downto 0);
signal rel_78_4: boolean;
signal rddbus1_join_78_1: unsigned((32 - 1) downto 0);
signal plbwrdbusreg_97_1_slice: unsigned((32 - 1) downto 0);
signal plbrstreg_12_24_next_x_000000: boolean;
signal plbpavalidreg_14_28_next_x_000000: boolean;
begin
plbrst_1_110 <= std_logic_vector_to_unsigned(plbrst);
plbabus_1_118 <= std_logic_vector_to_unsigned(plbabus);
plbpavalid_1_127 <= std_logic_vector_to_unsigned(plbpavalid);
plbrnw_1_139 <= std_logic_vector_to_unsigned(plbrnw);
plbwrdbus_1_147 <= std_logic_vector_to_unsigned(plbwrdbus);
rddata_1_158 <= std_logic_vector_to_unsigned(rddata);
addrpref_1_166 <= std_logic_vector_to_unsigned(addrpref);
proc_plbrstreg_12_24: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
plbrstreg_12_24 <= plbrstreg_12_24_next;
end if;
end if;
end process proc_plbrstreg_12_24;
proc_plbabusreg_13_25: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
plbabusreg_13_25 <= plbabusreg_13_25_next;
end if;
end if;
end process proc_plbabusreg_13_25;
proc_plbpavalidreg_14_28: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
plbpavalidreg_14_28 <= plbpavalidreg_14_28_next;
end if;
end if;
end process proc_plbpavalidreg_14_28;
proc_plbrnwreg_15_24: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
plbrnwreg_15_24 <= plbrnwreg_15_24_next;
end if;
end if;
end process proc_plbrnwreg_15_24;
proc_plbwrdbusreg_16_27: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
plbwrdbusreg_16_27 <= plbwrdbusreg_16_27_next;
end if;
end if;
end process proc_plbwrdbusreg_16_27;
proc_avalidreg_28_23: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
avalidreg_28_23 <= avalidreg_28_23_next;
end if;
end if;
end process proc_avalidreg_28_23;
proc_ps1reg_39_20: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
ps1reg_39_20 <= ps1reg_39_20_next;
end if;
end if;
end process proc_ps1reg_39_20;
proc_psreg_47_19: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
psreg_47_19 <= psreg_47_19_next;
end if;
end if;
end process proc_psreg_47_19;
rdcompdelay_58_25_back <= rdcompdelay_58_25(2);
proc_rdcompdelay_58_25: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (rdcompdelay_58_25_push_front_pop_back_en = '1')) then
for i in 2 downto 1 loop
rdcompdelay_58_25(i) <= rdcompdelay_58_25(i-1);
end loop;
rdcompdelay_58_25(0) <= rdcompdelay_58_25_front_din;
end if;
end if;
end process proc_rdcompdelay_58_25;
proc_rdcompreg_62_23: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
rdcompreg_62_23 <= rdcompreg_62_23_next;
end if;
end if;
end process proc_rdcompreg_62_23;
proc_rddackreg_66_23: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
rddackreg_66_23 <= rddackreg_66_23_next;
end if;
end if;
end process proc_rddackreg_66_23;
proc_wrdackreg_70_23: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
wrdackreg_70_23 <= wrdackreg_70_23_next;
end if;
end if;
end process proc_wrdackreg_70_23;
proc_rddbusreg_84_23: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
rddbusreg_84_23 <= rddbusreg_84_23_next;
end if;
end if;
end process proc_rddbusreg_84_23;
bankaddr_20_1_slice <= u2u_slice(plbabusreg_13_25, 11, 10);
linearaddr_21_1_slice <= u2u_slice(plbabusreg_13_25, 9, 2);
addrpref_in_32_1_slice <= u2u_slice(plbabusreg_13_25, 31, 12);
rel_33_4 <= addrpref_in_32_1_slice = addrpref_1_166;
proc_if_33_1: process (rel_33_4)
is
begin
if rel_33_4 then
ps1_join_33_1 <= true;
else
ps1_join_33_1 <= false;
end if;
end process proc_if_33_1;
ps_42_1_bit <= ((boolean_to_vector(ps1_join_33_1) and boolean_to_vector(plbpavalidreg_14_28)) = "1");
bitnot_49_49 <= ((not boolean_to_vector(plbrstreg_12_24)) = "1");
bitnot_49_73 <= ((not boolean_to_vector(psreg_47_19)) = "1");
bit_49_49 <= ((boolean_to_vector(bitnot_49_49) and boolean_to_vector(ps_42_1_bit) and boolean_to_vector(bitnot_49_73)) = "1");
addrack_49_1_convert <= u2u_cast(std_logic_vector_to_unsigned(boolean_to_vector(bit_49_49)), 0, 1, 0);
bit_55_43 <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(addrack_49_1_convert) and unsigned_to_std_logic_vector(plbrnwreg_15_24));
bitnot_72_35 <= std_logic_vector_to_unsigned(not unsigned_to_std_logic_vector(plbrnwreg_15_24));
wrdackreg_72_1_bit <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(addrack_49_1_convert) and unsigned_to_std_logic_vector(bitnot_72_35));
rdsel_76_1_bit <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(rdcompdelay_58_25_back) or unsigned_to_std_logic_vector(rdcompreg_62_23));
rel_78_4 <= rdsel_76_1_bit = std_logic_vector_to_unsigned("1");
proc_if_78_1: process (rddata_1_158, rel_78_4)
is
begin
if rel_78_4 then
rddbus1_join_78_1 <= rddata_1_158;
else
rddbus1_join_78_1 <= std_logic_vector_to_unsigned("00000000000000000000000000000000");
end if;
end process proc_if_78_1;
plbwrdbusreg_97_1_slice <= u2u_slice(plbwrdbus_1_147, 31, 0);
plbrstreg_12_24_next_x_000000 <= (plbrst_1_110 /= "0");
plbrstreg_12_24_next <= plbrstreg_12_24_next_x_000000;
plbabusreg_13_25_next <= plbabus_1_118;
plbpavalidreg_14_28_next_x_000000 <= (plbpavalid_1_127 /= "0");
plbpavalidreg_14_28_next <= plbpavalidreg_14_28_next_x_000000;
plbrnwreg_15_24_next <= plbrnw_1_139;
plbwrdbusreg_16_27_next <= plbwrdbusreg_97_1_slice;
avalidreg_28_23_next <= plbpavalidreg_14_28;
ps1reg_39_20_next <= ps1_join_33_1;
psreg_47_19_next <= ps_42_1_bit;
rdcompdelay_58_25_front_din <= bit_55_43;
rdcompdelay_58_25_push_front_pop_back_en <= '1';
rdcompreg_62_23_next <= rdcompdelay_58_25_back;
rddackreg_66_23_next <= rdcompreg_62_23;
wrdackreg_70_23_next <= wrdackreg_72_1_bit;
rddbusreg_84_23_next <= rddbus1_join_78_1;
wrdbusreg <= unsigned_to_std_logic_vector(plbwrdbusreg_16_27);
addrack <= unsigned_to_std_logic_vector(addrack_49_1_convert);
rdcomp <= unsigned_to_std_logic_vector(rdcompreg_62_23);
wrdack <= unsigned_to_std_logic_vector(wrdackreg_70_23);
bankaddr <= unsigned_to_std_logic_vector(bankaddr_20_1_slice);
rnwreg <= unsigned_to_std_logic_vector(plbrnwreg_15_24);
rddack <= unsigned_to_std_logic_vector(rddackreg_66_23);
rddbus <= unsigned_to_std_logic_vector(rddbusreg_84_23);
linearaddr <= unsigned_to_std_logic_vector(linearaddr_21_1_slice);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity mcode_block_6fff803424 is
port (
wrdbus : in std_logic_vector((32 - 1) downto 0);
bankaddr : in std_logic_vector((2 - 1) downto 0);
linearaddr : in std_logic_vector((8 - 1) downto 0);
rnwreg : in std_logic_vector((1 - 1) downto 0);
addrack : in std_logic_vector((1 - 1) downto 0);
sm_coef_update : in std_logic_vector((1 - 1) downto 0);
sm_coef_gain : in std_logic_vector((20 - 1) downto 0);
sm_coef_buffer : in std_logic_vector((7 - 1) downto 0);
read_bank_out : out std_logic_vector((32 - 1) downto 0);
sm_coef_update_din : out std_logic_vector((1 - 1) downto 0);
sm_coef_update_en : out std_logic_vector((1 - 1) downto 0);
sm_coef_gain_din : out std_logic_vector((20 - 1) downto 0);
sm_coef_gain_en : out std_logic_vector((1 - 1) downto 0);
sm_coef_buffer_addr : out std_logic_vector((5 - 1) downto 0);
sm_coef_buffer_din : out std_logic_vector((7 - 1) downto 0);
sm_coef_buffer_we : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end mcode_block_6fff803424;
architecture behavior of mcode_block_6fff803424 is
signal wrdbus_1_173: unsigned((32 - 1) downto 0);
signal bankaddr_1_181: unsigned((2 - 1) downto 0);
signal linearaddr_1_191: unsigned((8 - 1) downto 0);
signal rnwreg_1_203: unsigned((1 - 1) downto 0);
signal addrack_1_211: unsigned((1 - 1) downto 0);
signal sm_coef_update_1_220: unsigned((1 - 1) downto 0);
signal sm_coef_gain_1_236: unsigned((20 - 1) downto 0);
signal sm_coef_buffer_1_250: signed((7 - 1) downto 0);
signal reg_bank_out_reg_25_30_next: unsigned((32 - 1) downto 0);
signal reg_bank_out_reg_25_30: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000";
signal ram_bank_out_reg_49_30_next: unsigned((32 - 1) downto 0);
signal ram_bank_out_reg_49_30: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000";
signal sm_coef_buffer_we_reg_62_35_next: boolean;
signal sm_coef_buffer_we_reg_62_35: boolean := false;
signal sm_coef_buffer_addr_reg_74_1_next: unsigned((5 - 1) downto 0);
signal sm_coef_buffer_addr_reg_74_1: unsigned((5 - 1) downto 0) := "00000";
signal read_bank_out_reg_112_31_next: unsigned((32 - 1) downto 0);
signal read_bank_out_reg_112_31: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000";
signal bankaddr_reg_115_26_next: unsigned((2 - 1) downto 0);
signal bankaddr_reg_115_26: unsigned((2 - 1) downto 0) := "00";
signal sm_coef_buffer_bus_19_1_force: unsigned((7 - 1) downto 0);
signal rel_28_4: boolean;
signal rel_30_8: boolean;
signal reg_bank_out_reg_join_28_1: unsigned((32 - 1) downto 0);
signal opcode_42_1_concat: unsigned((12 - 1) downto 0);
signal slice_56_39: unsigned((7 - 1) downto 0);
signal sm_coef_buffer_din_56_1_force: signed((7 - 1) downto 0);
signal opcode_sm_coef_buffer_64_1_concat: unsigned((4 - 1) downto 0);
signal rel_65_4: boolean;
signal sm_coef_buffer_we_reg_join_65_1: boolean;
signal rel_83_4: boolean;
signal sm_coef_update_en_join_83_1: boolean;
signal rel_89_4: boolean;
signal sm_coef_gain_en_join_89_1: boolean;
signal slice_104_39: unsigned((1 - 1) downto 0);
signal slice_107_37: unsigned((20 - 1) downto 0);
signal rel_117_4: boolean;
signal rel_120_8: boolean;
signal rel_123_8: boolean;
signal rel_126_8: boolean;
signal read_bank_out_reg_join_117_1: unsigned((32 - 1) downto 0);
signal cast_ram_bank_out_reg_49_30_next: unsigned((32 - 1) downto 0);
signal cast_sm_coef_buffer_addr_reg_74_1_next: unsigned((5 - 1) downto 0);
begin
wrdbus_1_173 <= std_logic_vector_to_unsigned(wrdbus);
bankaddr_1_181 <= std_logic_vector_to_unsigned(bankaddr);
linearaddr_1_191 <= std_logic_vector_to_unsigned(linearaddr);
rnwreg_1_203 <= std_logic_vector_to_unsigned(rnwreg);
addrack_1_211 <= std_logic_vector_to_unsigned(addrack);
sm_coef_update_1_220 <= std_logic_vector_to_unsigned(sm_coef_update);
sm_coef_gain_1_236 <= std_logic_vector_to_unsigned(sm_coef_gain);
sm_coef_buffer_1_250 <= std_logic_vector_to_signed(sm_coef_buffer);
proc_reg_bank_out_reg_25_30: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
reg_bank_out_reg_25_30 <= reg_bank_out_reg_25_30_next;
end if;
end if;
end process proc_reg_bank_out_reg_25_30;
proc_ram_bank_out_reg_49_30: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
ram_bank_out_reg_49_30 <= ram_bank_out_reg_49_30_next;
end if;
end if;
end process proc_ram_bank_out_reg_49_30;
proc_sm_coef_buffer_we_reg_62_35: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
sm_coef_buffer_we_reg_62_35 <= sm_coef_buffer_we_reg_62_35_next;
end if;
end if;
end process proc_sm_coef_buffer_we_reg_62_35;
proc_sm_coef_buffer_addr_reg_74_1: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
sm_coef_buffer_addr_reg_74_1 <= sm_coef_buffer_addr_reg_74_1_next;
end if;
end if;
end process proc_sm_coef_buffer_addr_reg_74_1;
proc_read_bank_out_reg_112_31: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
read_bank_out_reg_112_31 <= read_bank_out_reg_112_31_next;
end if;
end if;
end process proc_read_bank_out_reg_112_31;
proc_bankaddr_reg_115_26: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
bankaddr_reg_115_26 <= bankaddr_reg_115_26_next;
end if;
end if;
end process proc_bankaddr_reg_115_26;
sm_coef_buffer_bus_19_1_force <= signed_to_unsigned(sm_coef_buffer_1_250);
rel_28_4 <= linearaddr_1_191 = std_logic_vector_to_unsigned("00000000");
rel_30_8 <= linearaddr_1_191 = std_logic_vector_to_unsigned("00000001");
proc_if_28_1: process (reg_bank_out_reg_25_30, rel_28_4, rel_30_8, sm_coef_gain_1_236, sm_coef_update_1_220)
is
begin
if rel_28_4 then
reg_bank_out_reg_join_28_1 <= u2u_cast(sm_coef_update_1_220, 0, 32, 0);
elsif rel_30_8 then
reg_bank_out_reg_join_28_1 <= u2u_cast(sm_coef_gain_1_236, 0, 32, 0);
else
reg_bank_out_reg_join_28_1 <= reg_bank_out_reg_25_30;
end if;
end process proc_if_28_1;
opcode_42_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(addrack_1_211) & unsigned_to_std_logic_vector(rnwreg_1_203) & unsigned_to_std_logic_vector(bankaddr_1_181) & unsigned_to_std_logic_vector(linearaddr_1_191));
slice_56_39 <= u2u_slice(wrdbus_1_173, 6, 0);
sm_coef_buffer_din_56_1_force <= unsigned_to_signed(slice_56_39);
opcode_sm_coef_buffer_64_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(addrack_1_211) & unsigned_to_std_logic_vector(rnwreg_1_203) & unsigned_to_std_logic_vector(bankaddr_1_181));
rel_65_4 <= opcode_sm_coef_buffer_64_1_concat = std_logic_vector_to_unsigned("1000");
proc_if_65_1: process (rel_65_4)
is
begin
if rel_65_4 then
sm_coef_buffer_we_reg_join_65_1 <= true;
else
sm_coef_buffer_we_reg_join_65_1 <= false;
end if;
end process proc_if_65_1;
rel_83_4 <= opcode_42_1_concat = std_logic_vector_to_unsigned("101000000000");
proc_if_83_1: process (rel_83_4)
is
begin
if rel_83_4 then
sm_coef_update_en_join_83_1 <= true;
else
sm_coef_update_en_join_83_1 <= false;
end if;
end process proc_if_83_1;
rel_89_4 <= opcode_42_1_concat = std_logic_vector_to_unsigned("101000000001");
proc_if_89_1: process (rel_89_4)
is
begin
if rel_89_4 then
sm_coef_gain_en_join_89_1 <= true;
else
sm_coef_gain_en_join_89_1 <= false;
end if;
end process proc_if_89_1;
slice_104_39 <= u2u_slice(wrdbus_1_173, 0, 0);
slice_107_37 <= u2u_slice(wrdbus_1_173, 19, 0);
rel_117_4 <= bankaddr_reg_115_26 = std_logic_vector_to_unsigned("00");
rel_120_8 <= bankaddr_reg_115_26 = std_logic_vector_to_unsigned("01");
rel_123_8 <= bankaddr_reg_115_26 = std_logic_vector_to_unsigned("10");
rel_126_8 <= bankaddr_reg_115_26 = std_logic_vector_to_unsigned("11");
proc_if_117_1: process (ram_bank_out_reg_49_30, read_bank_out_reg_112_31, reg_bank_out_reg_25_30, rel_117_4, rel_120_8, rel_123_8, rel_126_8)
is
begin
if rel_117_4 then
read_bank_out_reg_join_117_1 <= ram_bank_out_reg_49_30;
elsif rel_120_8 then
read_bank_out_reg_join_117_1 <= std_logic_vector_to_unsigned("00000000000000000000000000000000");
elsif rel_123_8 then
read_bank_out_reg_join_117_1 <= reg_bank_out_reg_25_30;
elsif rel_126_8 then
read_bank_out_reg_join_117_1 <= std_logic_vector_to_unsigned("00000000000000000000000000000000");
else
read_bank_out_reg_join_117_1 <= read_bank_out_reg_112_31;
end if;
end process proc_if_117_1;
reg_bank_out_reg_25_30_next <= reg_bank_out_reg_join_28_1;
cast_ram_bank_out_reg_49_30_next <= u2u_cast(sm_coef_buffer_bus_19_1_force, 0, 32, 0);
ram_bank_out_reg_49_30_next <= cast_ram_bank_out_reg_49_30_next;
sm_coef_buffer_we_reg_62_35_next <= sm_coef_buffer_we_reg_join_65_1;
cast_sm_coef_buffer_addr_reg_74_1_next <= u2u_cast(linearaddr_1_191, 0, 5, 0);
sm_coef_buffer_addr_reg_74_1_next <= cast_sm_coef_buffer_addr_reg_74_1_next;
read_bank_out_reg_112_31_next <= read_bank_out_reg_join_117_1;
bankaddr_reg_115_26_next <= bankaddr_1_181;
read_bank_out <= unsigned_to_std_logic_vector(read_bank_out_reg_112_31);
sm_coef_update_din <= unsigned_to_std_logic_vector(slice_104_39);
sm_coef_update_en <= boolean_to_vector(sm_coef_update_en_join_83_1);
sm_coef_gain_din <= unsigned_to_std_logic_vector(slice_107_37);
sm_coef_gain_en <= boolean_to_vector(sm_coef_gain_en_join_89_1);
sm_coef_buffer_addr <= unsigned_to_std_logic_vector(sm_coef_buffer_addr_reg_74_1);
sm_coef_buffer_din <= signed_to_std_logic_vector(sm_coef_buffer_din_56_1_force);
sm_coef_buffer_we <= boolean_to_vector(sm_coef_buffer_we_reg_62_35);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity concat_d0d1b9533e is
port (
in0 : in std_logic_vector((8 - 1) downto 0);
in1 : in std_logic_vector((8 - 1) downto 0);
in2 : in std_logic_vector((8 - 1) downto 0);
y : out std_logic_vector((24 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end concat_d0d1b9533e;
architecture behavior of concat_d0d1b9533e is
signal in0_1_23: unsigned((8 - 1) downto 0);
signal in1_1_27: unsigned((8 - 1) downto 0);
signal in2_1_31: unsigned((8 - 1) downto 0);
signal y_2_1_concat: unsigned((24 - 1) downto 0);
begin
in0_1_23 <= std_logic_vector_to_unsigned(in0);
in1_1_27 <= std_logic_vector_to_unsigned(in1);
in2_1_31 <= std_logic_vector_to_unsigned(in2);
y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27) & unsigned_to_std_logic_vector(in2_1_31));
y <= unsigned_to_std_logic_vector(y_2_1_concat);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "sg_2d_fir/5x5_Filters/Blue_Filter/5x5_Filter/ABS"
entity abs_entity_9ef2dfe1e8 is
port (
ce_1: in std_logic;
clk_1: in std_logic;
in1: in std_logic_vector(21 downto 0);
out1: out std_logic_vector(22 downto 0)
);
end abs_entity_9ef2dfe1e8;
architecture structural of abs_entity_9ef2dfe1e8 is
signal addsub15_s_net_x0: std_logic_vector(21 downto 0);
signal ce_1_sg_x0: std_logic;
signal clk_1_sg_x0: std_logic;
signal mux_y_net_x0: std_logic_vector(22 downto 0);
signal negate_op_net: std_logic_vector(22 downto 0);
signal register1_q_net: std_logic_vector(21 downto 0);
signal register2_q_net: std_logic;
signal slice_y_net: std_logic;
begin
ce_1_sg_x0 <= ce_1;
clk_1_sg_x0 <= clk_1;
addsub15_s_net_x0 <= in1;
out1 <= mux_y_net_x0;
mux: entity work.mux_029cd20aa9
port map (
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
clr => '0',
d0 => register1_q_net,
d1 => negate_op_net,
sel(0) => register2_q_net,
y => mux_y_net_x0
);
negate: entity work.negate_142bd36a06
port map (
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
clr => '0',
ip => addsub15_s_net_x0,
op => negate_op_net
);
register1: entity work.xlregister
generic map (
d_width => 22,
init_value => b"0000000000000000000000"
)
port map (
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
d => addsub15_s_net_x0,
en => "1",
rst => "0",
q => register1_q_net
);
register2: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
d(0) => slice_y_net,
en => "1",
rst => "0",
q(0) => register2_q_net
);
slice: entity work.xlslice
generic map (
new_lsb => 21,
new_msb => 21,
x_width => 22,
y_width => 1
)
port map (
x => addsub15_s_net_x0,
y(0) => slice_y_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "sg_2d_fir/5x5_Filters/Blue_Filter/5x5_Filter/load_sequencer"
entity load_sequencer_entity_8724dffd75 is
port (
ce_1: in std_logic;
clk_1: in std_logic;
load: in std_logic;
load_1: out std_logic;
load_2: out std_logic;
load_3: out std_logic;
load_4: out std_logic;
load_5: out std_logic
);
end load_sequencer_entity_8724dffd75;
architecture structural of load_sequencer_entity_8724dffd75 is
signal ce_1_sg_x1: std_logic;
signal clk_1_sg_x1: std_logic;
signal constant1_op_net: std_logic_vector(2 downto 0);
signal constant2_op_net: std_logic_vector(2 downto 0);
signal constant3_op_net: std_logic_vector(2 downto 0);
signal constant4_op_net: std_logic_vector(2 downto 0);
signal constant5_op_net: std_logic_vector(2 downto 0);
signal constant7_op_net: std_logic_vector(2 downto 0);
signal counter_op_net: std_logic_vector(2 downto 0);
signal index_count_op_net: std_logic_vector(2 downto 0);
signal logical1_y_net_x0: std_logic;
signal logical2_y_net_x0: std_logic;
signal logical3_y_net_x0: std_logic;
signal logical4_y_net_x0: std_logic;
signal logical5_y_net: std_logic;
signal logical_y_net_x0: std_logic;
signal relational1_op_net: std_logic;
signal relational2_op_net: std_logic;
signal relational3_op_net: std_logic;
signal relational3_op_net_x1: std_logic;
signal relational4_op_net: std_logic;
signal relational5_op_net: std_logic;
signal relational6_op_net: std_logic;
signal relational_op_net: std_logic;
begin
ce_1_sg_x1 <= ce_1;
clk_1_sg_x1 <= clk_1;
relational3_op_net_x1 <= load;
load_1 <= logical_y_net_x0;
load_2 <= logical1_y_net_x0;
load_3 <= logical2_y_net_x0;
load_4 <= logical3_y_net_x0;
load_5 <= logical4_y_net_x0;
constant1: entity work.constant_822933f89b
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant1_op_net
);
constant2: entity work.constant_a1c496ea88
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant2_op_net
);
constant3: entity work.constant_1f5cc32f1e
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant3_op_net
);
constant4: entity work.constant_0f59f02ba5
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant4_op_net
);
constant5: entity work.constant_469094441c
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant5_op_net
);
constant7: entity work.constant_469094441c
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant7_op_net
);
counter: entity work.xlcounter_limit
generic map (
cnt_15_0 => 4,
cnt_31_16 => 0,
cnt_47_32 => 0,
cnt_63_48 => 0,
core_name0 => "cntr_11_0_e859c6662c373192",
count_limited => 1,
op_arith => xlUnsigned,
op_width => 3
)
port map (
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
clr => '0',
en(0) => relational3_op_net_x1,
rst(0) => relational6_op_net,
op => counter_op_net
);
index_count: entity work.xlcounter_limit
generic map (
cnt_15_0 => 4,
cnt_31_16 => 0,
cnt_47_32 => 0,
cnt_63_48 => 0,
core_name0 => "cntr_11_0_e859c6662c373192",
count_limited => 1,
op_arith => xlUnsigned,
op_width => 3
)
port map (
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
clr => '0',
en(0) => relational6_op_net,
rst(0) => logical5_y_net,
op => index_count_op_net
);
logical: entity work.logical_80f90b97d0
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => relational1_op_net,
d1(0) => relational3_op_net_x1,
y(0) => logical_y_net_x0
);
logical1: entity work.logical_80f90b97d0
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => relational2_op_net,
d1(0) => relational3_op_net_x1,
y(0) => logical1_y_net_x0
);
logical2: entity work.logical_80f90b97d0
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => relational3_op_net,
d1(0) => relational3_op_net_x1,
y(0) => logical2_y_net_x0
);
logical3: entity work.logical_80f90b97d0
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => relational4_op_net,
d1(0) => relational3_op_net_x1,
y(0) => logical3_y_net_x0
);
logical4: entity work.logical_80f90b97d0
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => relational5_op_net,
d1(0) => relational3_op_net_x1,
y(0) => logical4_y_net_x0
);
logical5: entity work.logical_80f90b97d0
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => relational_op_net,
d1(0) => relational6_op_net,
y(0) => logical5_y_net
);
relational: entity work.relational_8fc7f5539b
port map (
a => index_count_op_net,
b => constant7_op_net,
ce => '0',
clk => '0',
clr => '0',
op(0) => relational_op_net
);
relational1: entity work.relational_8fc7f5539b
port map (
a => index_count_op_net,
b => constant1_op_net,
ce => '0',
clk => '0',
clr => '0',
op(0) => relational1_op_net
);
relational2: entity work.relational_8fc7f5539b
port map (
a => index_count_op_net,
b => constant2_op_net,
ce => '0',
clk => '0',
clr => '0',
op(0) => relational2_op_net
);
relational3: entity work.relational_8fc7f5539b
port map (
a => index_count_op_net,
b => constant3_op_net,
ce => '0',
clk => '0',
clr => '0',
op(0) => relational3_op_net
);
relational4: entity work.relational_8fc7f5539b
port map (
a => index_count_op_net,
b => constant4_op_net,
ce => '0',
clk => '0',
clr => '0',
op(0) => relational4_op_net
);
relational5: entity work.relational_8fc7f5539b
port map (
a => index_count_op_net,
b => constant5_op_net,
ce => '0',
clk => '0',
clr => '0',
op(0) => relational5_op_net
);
relational6: entity work.relational_8fc7f5539b
port map (
a => counter_op_net,
b => constant7_op_net,
ce => '0',
clk => '0',
clr => '0',
op(0) => relational6_op_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "sg_2d_fir/5x5_Filters/Blue_Filter/5x5_Filter/n-tap FIR Compiler Filter/Rising Edge Detector1"
entity rising_edge_detector1_entity_0d24c36d60 is
port (
ce_1: in std_logic;
clk_1: in std_logic;
din: in std_logic;
dout: out std_logic
);
end rising_edge_detector1_entity_0d24c36d60;
architecture structural of rising_edge_detector1_entity_0d24c36d60 is
signal ce_1_sg_x2: std_logic;
signal clk_1_sg_x2: std_logic;
signal inverter_op_net: std_logic;
signal logical_y_net_x1: std_logic;
signal logical_y_net_x2: std_logic;
signal register1_q_net: std_logic;
begin
ce_1_sg_x2 <= ce_1;
clk_1_sg_x2 <= clk_1;
logical_y_net_x1 <= din;
dout <= logical_y_net_x2;
inverter: entity work.inverter_e5b38cca3b
port map (
ce => ce_1_sg_x2,
clk => clk_1_sg_x2,
clr => '0',
ip(0) => register1_q_net,
op(0) => inverter_op_net
);
logical: entity work.logical_80f90b97d0
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => logical_y_net_x1,
d1(0) => inverter_op_net,
y(0) => logical_y_net_x2
);
register1: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x2,
clk => clk_1_sg_x2,
d(0) => logical_y_net_x1,
en => "1",
rst => "0",
q(0) => register1_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "sg_2d_fir/5x5_Filters/Blue_Filter/5x5_Filter/n-tap FIR Compiler Filter"
entity n_tap_fir_compiler_filter_entity_7d40670988 is
port (
ce_1: in std_logic;
ce_logic_1: in std_logic;
clk_1: in std_logic;
coef: in std_logic_vector(6 downto 0);
din: in std_logic_vector(7 downto 0);
load: in std_logic;
out_x0: out std_logic_vector(18 downto 0)
);
end n_tap_fir_compiler_filter_entity_7d40670988;
architecture structural of n_tap_fir_compiler_filter_entity_7d40670988 is
signal ce_1_sg_x3: std_logic;
signal ce_logic_1_sg_x0: std_logic;
signal clk_1_sg_x3: std_logic;
signal fir_compiler_5_0_dout_net: std_logic_vector(18 downto 0);
signal fir_compiler_5_0_rdy_net: std_logic;
signal l1_x0: std_logic_vector(7 downto 0);
signal logical_y_net_x2: std_logic;
signal logical_y_net_x3: std_logic;
signal register2_q_net: std_logic;
signal register_q_net_x0: std_logic_vector(18 downto 0);
signal shared_memory_data_out_net_x0: std_logic_vector(6 downto 0);
begin
ce_1_sg_x3 <= ce_1;
ce_logic_1_sg_x0 <= ce_logic_1;
clk_1_sg_x3 <= clk_1;
shared_memory_data_out_net_x0 <= coef;
l1_x0 <= din;
logical_y_net_x3 <= load;
out_x0 <= register_q_net_x0;
fir_compiler_5_0: entity work.xlfir_compiler_d885873ecd26cf15cdb95a5d10c7a292
port map (
ce => ce_1_sg_x3,
ce_logic_1 => ce_logic_1_sg_x0,
clk => clk_1_sg_x3,
clk_logic_1 => clk_1_sg_x3,
coef_din => shared_memory_data_out_net_x0,
coef_ld => logical_y_net_x2,
coef_we => register2_q_net,
din => l1_x0,
src_ce => ce_1_sg_x3,
src_clk => clk_1_sg_x3,
dout => fir_compiler_5_0_dout_net,
rdy => fir_compiler_5_0_rdy_net
);
register2: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x3,
clk => clk_1_sg_x3,
d(0) => logical_y_net_x3,
en => "1",
rst => "0",
q(0) => register2_q_net
);
register_x0: entity work.xlregister
generic map (
d_width => 19,
init_value => b"0000000000000000000"
)
port map (
ce => ce_1_sg_x3,
clk => clk_1_sg_x3,
d => fir_compiler_5_0_dout_net,
en(0) => fir_compiler_5_0_rdy_net,
rst => "0",
q => register_q_net_x0
);
rising_edge_detector1_0d24c36d60: entity work.rising_edge_detector1_entity_0d24c36d60
port map (
ce_1 => ce_1_sg_x3,
clk_1 => clk_1_sg_x3,
din => logical_y_net_x3,
dout => logical_y_net_x2
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "sg_2d_fir/5x5_Filters/Blue_Filter/5x5_Filter/n-tap FIR Compiler Filter1"
entity n_tap_fir_compiler_filter1_entity_b6187dc1dd is
port (
ce_1: in std_logic;
ce_logic_1: in std_logic;
clk_1: in std_logic;
coef: in std_logic_vector(6 downto 0);
din: in std_logic_vector(7 downto 0);
load: in std_logic;
out_x0: out std_logic_vector(18 downto 0)
);
end n_tap_fir_compiler_filter1_entity_b6187dc1dd;
architecture structural of n_tap_fir_compiler_filter1_entity_b6187dc1dd is
signal ce_1_sg_x5: std_logic;
signal ce_logic_1_sg_x1: std_logic;
signal clk_1_sg_x5: std_logic;
signal fir_compiler_5_0_dout_net: std_logic_vector(18 downto 0);
signal fir_compiler_5_0_rdy_net: std_logic;
signal l2_x0: std_logic_vector(7 downto 0);
signal logical1_y_net_x2: std_logic;
signal logical_y_net_x0: std_logic;
signal register2_q_net: std_logic;
signal register_q_net_x0: std_logic_vector(18 downto 0);
signal shared_memory_data_out_net_x1: std_logic_vector(6 downto 0);
begin
ce_1_sg_x5 <= ce_1;
ce_logic_1_sg_x1 <= ce_logic_1;
clk_1_sg_x5 <= clk_1;
shared_memory_data_out_net_x1 <= coef;
l2_x0 <= din;
logical1_y_net_x2 <= load;
out_x0 <= register_q_net_x0;
fir_compiler_5_0: entity work.xlfir_compiler_1e4b453df468e83a1cea0a55c8d9b90f
port map (
ce => ce_1_sg_x5,
ce_logic_1 => ce_logic_1_sg_x1,
clk => clk_1_sg_x5,
clk_logic_1 => clk_1_sg_x5,
coef_din => shared_memory_data_out_net_x1,
coef_ld => logical_y_net_x0,
coef_we => register2_q_net,
din => l2_x0,
src_ce => ce_1_sg_x5,
src_clk => clk_1_sg_x5,
dout => fir_compiler_5_0_dout_net,
rdy => fir_compiler_5_0_rdy_net
);
register2: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x5,
clk => clk_1_sg_x5,
d(0) => logical1_y_net_x2,
en => "1",
rst => "0",
q(0) => register2_q_net
);
register_x0: entity work.xlregister
generic map (
d_width => 19,
init_value => b"0000000000000000000"
)
port map (
ce => ce_1_sg_x5,
clk => clk_1_sg_x5,
d => fir_compiler_5_0_dout_net,
en(0) => fir_compiler_5_0_rdy_net,
rst => "0",
q => register_q_net_x0
);
rising_edge_detector1_a171a70c77: entity work.rising_edge_detector1_entity_0d24c36d60
port map (
ce_1 => ce_1_sg_x5,
clk_1 => clk_1_sg_x5,
din => logical1_y_net_x2,
dout => logical_y_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "sg_2d_fir/5x5_Filters/Blue_Filter/5x5_Filter/n-tap FIR Compiler Filter2"
entity n_tap_fir_compiler_filter2_entity_92eb71d873 is
port (
ce_1: in std_logic;
ce_logic_1: in std_logic;
clk_1: in std_logic;
coef: in std_logic_vector(6 downto 0);
din: in std_logic_vector(7 downto 0);
load: in std_logic;
out_x0: out std_logic_vector(18 downto 0)
);
end n_tap_fir_compiler_filter2_entity_92eb71d873;
architecture structural of n_tap_fir_compiler_filter2_entity_92eb71d873 is
signal ce_1_sg_x7: std_logic;
signal ce_logic_1_sg_x2: std_logic;
signal clk_1_sg_x7: std_logic;
signal fir_compiler_5_0_dout_net: std_logic_vector(18 downto 0);
signal fir_compiler_5_0_rdy_net: std_logic;
signal l3_x0: std_logic_vector(7 downto 0);
signal logical2_y_net_x2: std_logic;
signal logical_y_net_x0: std_logic;
signal register2_q_net: std_logic;
signal register_q_net_x0: std_logic_vector(18 downto 0);
signal shared_memory_data_out_net_x2: std_logic_vector(6 downto 0);
begin
ce_1_sg_x7 <= ce_1;
ce_logic_1_sg_x2 <= ce_logic_1;
clk_1_sg_x7 <= clk_1;
shared_memory_data_out_net_x2 <= coef;
l3_x0 <= din;
logical2_y_net_x2 <= load;
out_x0 <= register_q_net_x0;
fir_compiler_5_0: entity work.xlfir_compiler_5077ad6f33cdc3f379ad80845501c286
port map (
ce => ce_1_sg_x7,
ce_logic_1 => ce_logic_1_sg_x2,
clk => clk_1_sg_x7,
clk_logic_1 => clk_1_sg_x7,
coef_din => shared_memory_data_out_net_x2,
coef_ld => logical_y_net_x0,
coef_we => register2_q_net,
din => l3_x0,
src_ce => ce_1_sg_x7,
src_clk => clk_1_sg_x7,
dout => fir_compiler_5_0_dout_net,
rdy => fir_compiler_5_0_rdy_net
);
register2: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x7,
clk => clk_1_sg_x7,
d(0) => logical2_y_net_x2,
en => "1",
rst => "0",
q(0) => register2_q_net
);
register_x0: entity work.xlregister
generic map (
d_width => 19,
init_value => b"0000000000000000000"
)
port map (
ce => ce_1_sg_x7,
clk => clk_1_sg_x7,
d => fir_compiler_5_0_dout_net,
en(0) => fir_compiler_5_0_rdy_net,
rst => "0",
q => register_q_net_x0
);
rising_edge_detector1_858d3eaa96: entity work.rising_edge_detector1_entity_0d24c36d60
port map (
ce_1 => ce_1_sg_x7,
clk_1 => clk_1_sg_x7,
din => logical2_y_net_x2,
dout => logical_y_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "sg_2d_fir/5x5_Filters/Blue_Filter/5x5_Filter"
entity x5x5_filter_entity_e192f59c95 is
port (
ce_1: in std_logic;
ce_logic_1: in std_logic;
clk_1: in std_logic;
coef: in std_logic_vector(6 downto 0);
gain: in std_logic_vector(19 downto 0);
line1: in std_logic_vector(7 downto 0);
line2: in std_logic_vector(7 downto 0);
line3: in std_logic_vector(7 downto 0);
line4: in std_logic_vector(7 downto 0);
line5: in std_logic_vector(7 downto 0);
load: in std_logic;
dout: out std_logic_vector(7 downto 0)
);
end x5x5_filter_entity_e192f59c95;
architecture structural of x5x5_filter_entity_e192f59c95 is
signal addsub15_s_net_x0: std_logic_vector(21 downto 0);
signal addsub2_s_net: std_logic_vector(19 downto 0);
signal addsub3_s_net: std_logic_vector(19 downto 0);
signal addsub4_s_net: std_logic_vector(20 downto 0);
signal assert_dout_net: std_logic_vector(19 downto 0);
signal ce_1_sg_x12: std_logic;
signal ce_logic_1_sg_x5: std_logic;
signal clk_1_sg_x12: std_logic;
signal coef_gain_q_net: std_logic_vector(19 downto 0);
signal convert1_dout_net_x0: std_logic_vector(7 downto 0);
signal from_register_data_out_net_x0: std_logic_vector(19 downto 0);
signal l1_x1: std_logic_vector(7 downto 0);
signal l2_x1: std_logic_vector(7 downto 0);
signal l3_x1: std_logic_vector(7 downto 0);
signal l4_x1: std_logic_vector(7 downto 0);
signal l5_x1: std_logic_vector(7 downto 0);
signal logical1_y_net_x2: std_logic;
signal logical2_y_net_x2: std_logic;
signal logical3_y_net_x2: std_logic;
signal logical4_y_net_x2: std_logic;
signal logical_y_net_x3: std_logic;
signal mult_p_net: std_logic_vector(42 downto 0);
signal mux_y_net_x0: std_logic_vector(22 downto 0);
signal register1_q_net: std_logic_vector(18 downto 0);
signal register2_q_net: std_logic_vector(18 downto 0);
signal register_q_net_x0: std_logic_vector(18 downto 0);
signal register_q_net_x1: std_logic_vector(18 downto 0);
signal register_q_net_x2: std_logic_vector(18 downto 0);
signal register_q_net_x3: std_logic_vector(18 downto 0);
signal register_q_net_x4: std_logic_vector(18 downto 0);
signal relational3_op_net_x2: std_logic;
signal shared_memory_data_out_net_x5: std_logic_vector(6 downto 0);
begin
ce_1_sg_x12 <= ce_1;
ce_logic_1_sg_x5 <= ce_logic_1;
clk_1_sg_x12 <= clk_1;
shared_memory_data_out_net_x5 <= coef;
from_register_data_out_net_x0 <= gain;
l1_x1 <= line1;
l2_x1 <= line2;
l3_x1 <= line3;
l4_x1 <= line4;
l5_x1 <= line5;
relational3_op_net_x2 <= load;
dout <= convert1_dout_net_x0;
abs_9ef2dfe1e8: entity work.abs_entity_9ef2dfe1e8
port map (
ce_1 => ce_1_sg_x12,
clk_1 => clk_1_sg_x12,
in1 => addsub15_s_net_x0,
out1 => mux_y_net_x0
);
addsub15: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 0,
a_width => 21,
b_arith => xlSigned,
b_bin_pt => 0,
b_width => 19,
c_has_c_out => 0,
c_latency => 1,
c_output_width => 22,
core_name0 => "addsb_11_0_e7b4231f2ca96446",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 22,
latency => 1,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 0,
s_width => 22
)
port map (
a => addsub4_s_net,
b => register2_q_net,
ce => ce_1_sg_x12,
clk => clk_1_sg_x12,
clr => '0',
en => "1",
s => addsub15_s_net_x0
);
addsub2: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 0,
a_width => 19,
b_arith => xlSigned,
b_bin_pt => 0,
b_width => 19,
c_has_c_out => 0,
c_latency => 1,
c_output_width => 20,
core_name0 => "addsb_11_0_da33f2d4b3b54185",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 20,
latency => 1,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 0,
s_width => 20
)
port map (
a => register_q_net_x0,
b => register_q_net_x1,
ce => ce_1_sg_x12,
clk => clk_1_sg_x12,
clr => '0',
en => "1",
s => addsub2_s_net
);
addsub3: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 0,
a_width => 19,
b_arith => xlSigned,
b_bin_pt => 0,
b_width => 19,
c_has_c_out => 0,
c_latency => 1,
c_output_width => 20,
core_name0 => "addsb_11_0_da33f2d4b3b54185",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 20,
latency => 1,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 0,
s_width => 20
)
port map (
a => register_q_net_x2,
b => register_q_net_x3,
ce => ce_1_sg_x12,
clk => clk_1_sg_x12,
clr => '0',
en => "1",
s => addsub3_s_net
);
addsub4: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 0,
a_width => 20,
b_arith => xlSigned,
b_bin_pt => 0,
b_width => 20,
c_has_c_out => 0,
c_latency => 1,
c_output_width => 21,
core_name0 => "addsb_11_0_48bcbc42a6774592",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 21,
latency => 1,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 0,
s_width => 21
)
port map (
a => addsub2_s_net,
b => addsub3_s_net,
ce => ce_1_sg_x12,
clk => clk_1_sg_x12,
clr => '0',
en => "1",
s => addsub4_s_net
);
assert_x0: entity work.xlpassthrough
generic map (
din_width => 20,
dout_width => 20
)
port map (
din => from_register_data_out_net_x0,
dout => assert_dout_net
);
coef_gain: entity work.xlregister
generic map (
d_width => 20,
init_value => b"11111111111111111111"
)
port map (
ce => ce_1_sg_x12,
clk => clk_1_sg_x12,
d => assert_dout_net,
en(0) => logical4_y_net_x2,
rst => "0",
q => coef_gain_q_net
);
convert1: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 2,
din_bin_pt => 17,
din_width => 43,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 8,
latency => 1,
overflow => xlSaturate,
quantization => xlTruncate
)
port map (
ce => ce_1_sg_x12,
clk => clk_1_sg_x12,
clr => '0',
din => mult_p_net,
en => "1",
dout => convert1_dout_net_x0
);
load_sequencer_8724dffd75: entity work.load_sequencer_entity_8724dffd75
port map (
ce_1 => ce_1_sg_x12,
clk_1 => clk_1_sg_x12,
load => relational3_op_net_x2,
load_1 => logical_y_net_x3,
load_2 => logical1_y_net_x2,
load_3 => logical2_y_net_x2,
load_4 => logical3_y_net_x2,
load_5 => logical4_y_net_x2
);
mult: entity work.xlmult
generic map (
a_arith => xlSigned,
a_bin_pt => 0,
a_width => 23,
b_arith => xlUnsigned,
b_bin_pt => 17,
b_width => 20,
c_a_type => 0,
c_a_width => 23,
c_b_type => 1,
c_b_width => 20,
c_baat => 23,
c_output_width => 43,
c_type => 0,
core_name0 => "mult_11_2_fe92ad55b7635191",
extra_registers => 0,
multsign => 2,
overflow => 1,
p_arith => xlSigned,
p_bin_pt => 17,
p_width => 43,
quantization => 1
)
port map (
a => mux_y_net_x0,
b => coef_gain_q_net,
ce => ce_1_sg_x12,
clk => clk_1_sg_x12,
clr => '0',
core_ce => ce_1_sg_x12,
core_clk => clk_1_sg_x12,
core_clr => '1',
en => "1",
rst => "0",
p => mult_p_net
);
n_tap_fir_compiler_filter1_b6187dc1dd: entity work.n_tap_fir_compiler_filter1_entity_b6187dc1dd
port map (
ce_1 => ce_1_sg_x12,
ce_logic_1 => ce_logic_1_sg_x5,
clk_1 => clk_1_sg_x12,
coef => shared_memory_data_out_net_x5,
din => l2_x1,
load => logical1_y_net_x2,
out_x0 => register_q_net_x1
);
n_tap_fir_compiler_filter2_92eb71d873: entity work.n_tap_fir_compiler_filter2_entity_92eb71d873
port map (
ce_1 => ce_1_sg_x12,
ce_logic_1 => ce_logic_1_sg_x5,
clk_1 => clk_1_sg_x12,
coef => shared_memory_data_out_net_x5,
din => l3_x1,
load => logical2_y_net_x2,
out_x0 => register_q_net_x2
);
n_tap_fir_compiler_filter3_5fb9ad894d: entity work.n_tap_fir_compiler_filter1_entity_b6187dc1dd
port map (
ce_1 => ce_1_sg_x12,
ce_logic_1 => ce_logic_1_sg_x5,
clk_1 => clk_1_sg_x12,
coef => shared_memory_data_out_net_x5,
din => l4_x1,
load => logical3_y_net_x2,
out_x0 => register_q_net_x3
);
n_tap_fir_compiler_filter4_91b51287e2: entity work.n_tap_fir_compiler_filter_entity_7d40670988
port map (
ce_1 => ce_1_sg_x12,
ce_logic_1 => ce_logic_1_sg_x5,
clk_1 => clk_1_sg_x12,
coef => shared_memory_data_out_net_x5,
din => l5_x1,
load => logical4_y_net_x2,
out_x0 => register_q_net_x4
);
n_tap_fir_compiler_filter_7d40670988: entity work.n_tap_fir_compiler_filter_entity_7d40670988
port map (
ce_1 => ce_1_sg_x12,
ce_logic_1 => ce_logic_1_sg_x5,
clk_1 => clk_1_sg_x12,
coef => shared_memory_data_out_net_x5,
din => l1_x1,
load => logical_y_net_x3,
out_x0 => register_q_net_x0
);
register1: entity work.xlregister
generic map (
d_width => 19,
init_value => b"0000000000000000000"
)
port map (
ce => ce_1_sg_x12,
clk => clk_1_sg_x12,
d => register_q_net_x4,
en => "1",
rst => "0",
q => register1_q_net
);
register2: entity work.xlregister
generic map (
d_width => 19,
init_value => b"0000000000000000000"
)
port map (
ce => ce_1_sg_x12,
clk => clk_1_sg_x12,
d => register1_q_net,
en => "1",
rst => "0",
q => register2_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "sg_2d_fir/5x5_Filters/Blue_Filter/Line_Buffer"
entity line_buffer_entity_edde027544 is
port (
addr: in std_logic_vector(11 downto 0);
ce_1: in std_logic;
clk_1: in std_logic;
data: in std_logic_vector(7 downto 0);
l1: out std_logic_vector(7 downto 0);
l2: out std_logic_vector(7 downto 0);
l3: out std_logic_vector(7 downto 0);
l4: out std_logic_vector(7 downto 0);
l5: out std_logic_vector(7 downto 0)
);
end line_buffer_entity_edde027544;
architecture structural of line_buffer_entity_edde027544 is
signal blue_x0: std_logic_vector(7 downto 0);
signal ce_1_sg_x13: std_logic;
signal clk_1_sg_x13: std_logic;
signal constant6_op_net: std_logic;
signal delay9_q_net: std_logic_vector(7 downto 0);
signal l1_x2: std_logic_vector(7 downto 0);
signal l2_x2: std_logic_vector(7 downto 0);
signal l3_x2: std_logic_vector(7 downto 0);
signal l4_x2: std_logic_vector(7 downto 0);
signal l5_x2: std_logic_vector(7 downto 0);
signal rctr_q_net_x0: std_logic_vector(11 downto 0);
signal single_port_ram2_data_out_net: std_logic_vector(7 downto 0);
signal single_port_ram3_data_out_net: std_logic_vector(7 downto 0);
signal single_port_ram_data_out_net: std_logic_vector(7 downto 0);
begin
rctr_q_net_x0 <= addr;
ce_1_sg_x13 <= ce_1;
clk_1_sg_x13 <= clk_1;
blue_x0 <= data;
l1 <= l1_x2;
l2 <= l2_x2;
l3 <= l3_x2;
l4 <= l4_x2;
l5 <= l5_x2;
constant6: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant6_op_net
);
delay1: entity work.delay_23f848c85b
port map (
ce => ce_1_sg_x13,
clk => clk_1_sg_x13,
clr => '0',
d => single_port_ram2_data_out_net,
q => l3_x2
);
delay2: entity work.delay_9565135955
port map (
ce => ce_1_sg_x13,
clk => clk_1_sg_x13,
clr => '0',
d => single_port_ram3_data_out_net,
q => l4_x2
);
delay7: entity work.delay_fb08f2e938
port map (
ce => ce_1_sg_x13,
clk => clk_1_sg_x13,
clr => '0',
d => delay9_q_net,
q => l5_x2
);
delay8: entity work.delay_ebec135d8a
port map (
ce => ce_1_sg_x13,
clk => clk_1_sg_x13,
clr => '0',
d => single_port_ram_data_out_net,
q => l2_x2
);
delay9: entity work.delay_23f848c85b
port map (
ce => ce_1_sg_x13,
clk => clk_1_sg_x13,
clr => '0',
d => blue_x0,
q => delay9_q_net
);
single_port_ram: entity work.xlspram
generic map (
c_address_width => 12,
c_width => 8,
core_name0 => "bmg_62_54b11b852dca329b",
latency => 1
)
port map (
addr => rctr_q_net_x0,
ce => ce_1_sg_x13,
clk => clk_1_sg_x13,
data_in => single_port_ram2_data_out_net,
en => "1",
rst => "0",
we(0) => constant6_op_net,
data_out => single_port_ram_data_out_net
);
single_port_ram1: entity work.xlspram
generic map (
c_address_width => 12,
c_width => 8,
core_name0 => "bmg_62_54b11b852dca329b",
latency => 1
)
port map (
addr => rctr_q_net_x0,
ce => ce_1_sg_x13,
clk => clk_1_sg_x13,
data_in => single_port_ram_data_out_net,
en => "1",
rst => "0",
we(0) => constant6_op_net,
data_out => l1_x2
);
single_port_ram2: entity work.xlspram
generic map (
c_address_width => 12,
c_width => 8,
core_name0 => "bmg_62_54b11b852dca329b",
latency => 1
)
port map (
addr => rctr_q_net_x0,
ce => ce_1_sg_x13,
clk => clk_1_sg_x13,
data_in => single_port_ram3_data_out_net,
en => "1",
rst => "0",
we(0) => constant6_op_net,
data_out => single_port_ram2_data_out_net
);
single_port_ram3: entity work.xlspram
generic map (
c_address_width => 12,
c_width => 8,
core_name0 => "bmg_62_54b11b852dca329b",
latency => 1
)
port map (
addr => rctr_q_net_x0,
ce => ce_1_sg_x13,
clk => clk_1_sg_x13,
data_in => delay9_q_net,
en => "1",
rst => "0",
we(0) => constant6_op_net,
data_out => single_port_ram3_data_out_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "sg_2d_fir/5x5_Filters/Blue_Filter"
entity blue_filter_entity_d29ca0c8b1 is
port (
addr: in std_logic_vector(11 downto 0);
ce_1: in std_logic;
ce_logic_1: in std_logic;
clk_1: in std_logic;
coef: in std_logic_vector(6 downto 0);
din: in std_logic_vector(7 downto 0);
gain: in std_logic_vector(19 downto 0);
load: in std_logic;
dout: out std_logic_vector(7 downto 0)
);
end blue_filter_entity_d29ca0c8b1;
architecture structural of blue_filter_entity_d29ca0c8b1 is
signal blue_x1: std_logic_vector(7 downto 0);
signal ce_1_sg_x14: std_logic;
signal ce_logic_1_sg_x6: std_logic;
signal clk_1_sg_x14: std_logic;
signal convert1_dout_net_x1: std_logic_vector(7 downto 0);
signal from_register_data_out_net_x1: std_logic_vector(19 downto 0);
signal l1_x2: std_logic_vector(7 downto 0);
signal l2_x2: std_logic_vector(7 downto 0);
signal l3_x2: std_logic_vector(7 downto 0);
signal l4_x2: std_logic_vector(7 downto 0);
signal l5_x2: std_logic_vector(7 downto 0);
signal rctr_q_net_x1: std_logic_vector(11 downto 0);
signal relational3_op_net_x3: std_logic;
signal shared_memory_data_out_net_x6: std_logic_vector(6 downto 0);
begin
rctr_q_net_x1 <= addr;
ce_1_sg_x14 <= ce_1;
ce_logic_1_sg_x6 <= ce_logic_1;
clk_1_sg_x14 <= clk_1;
shared_memory_data_out_net_x6 <= coef;
blue_x1 <= din;
from_register_data_out_net_x1 <= gain;
relational3_op_net_x3 <= load;
dout <= convert1_dout_net_x1;
line_buffer_edde027544: entity work.line_buffer_entity_edde027544
port map (
addr => rctr_q_net_x1,
ce_1 => ce_1_sg_x14,
clk_1 => clk_1_sg_x14,
data => blue_x1,
l1 => l1_x2,
l2 => l2_x2,
l3 => l3_x2,
l4 => l4_x2,
l5 => l5_x2
);
x5x5_filter_e192f59c95: entity work.x5x5_filter_entity_e192f59c95
port map (
ce_1 => ce_1_sg_x14,
ce_logic_1 => ce_logic_1_sg_x6,
clk_1 => clk_1_sg_x14,
coef => shared_memory_data_out_net_x6,
gain => from_register_data_out_net_x1,
line1 => l1_x2,
line2 => l2_x2,
line3 => l3_x2,
line4 => l4_x2,
line5 => l5_x2,
load => relational3_op_net_x3,
dout => convert1_dout_net_x1
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "sg_2d_fir/5x5_Filters/Ctrl_Delay/Line_Buffer"
entity line_buffer_entity_d14b7609fd is
port (
addr: in std_logic_vector(11 downto 0);
ce_1: in std_logic;
clk_1: in std_logic;
data: in std_logic_vector(4 downto 0);
l3_x0: out std_logic_vector(4 downto 0)
);
end line_buffer_entity_d14b7609fd;
architecture structural of line_buffer_entity_d14b7609fd is
signal ce_1_sg_x15: std_logic;
signal clk_1_sg_x15: std_logic;
signal concat_y_net_x0: std_logic_vector(4 downto 0);
signal constant6_op_net: std_logic;
signal delay9_q_net: std_logic_vector(4 downto 0);
signal l3_x1: std_logic_vector(4 downto 0);
signal rctr_q_net_x2: std_logic_vector(11 downto 0);
signal single_port_ram2_data_out_net: std_logic_vector(4 downto 0);
signal single_port_ram3_data_out_net: std_logic_vector(4 downto 0);
begin
rctr_q_net_x2 <= addr;
ce_1_sg_x15 <= ce_1;
clk_1_sg_x15 <= clk_1;
concat_y_net_x0 <= data;
l3_x0 <= l3_x1;
constant6: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant6_op_net
);
delay1: entity work.delay_38f665f8aa
port map (
ce => ce_1_sg_x15,
clk => clk_1_sg_x15,
clr => '0',
d => single_port_ram2_data_out_net,
q => l3_x1
);
delay9: entity work.delay_38f665f8aa
port map (
ce => ce_1_sg_x15,
clk => clk_1_sg_x15,
clr => '0',
d => concat_y_net_x0,
q => delay9_q_net
);
single_port_ram2: entity work.xlspram
generic map (
c_address_width => 12,
c_width => 5,
core_name0 => "bmg_62_05852d43925e39b8",
latency => 1
)
port map (
addr => rctr_q_net_x2,
ce => ce_1_sg_x15,
clk => clk_1_sg_x15,
data_in => single_port_ram3_data_out_net,
en => "1",
rst => "0",
we(0) => constant6_op_net,
data_out => single_port_ram2_data_out_net
);
single_port_ram3: entity work.xlspram
generic map (
c_address_width => 12,
c_width => 5,
core_name0 => "bmg_62_05852d43925e39b8",
latency => 1
)
port map (
addr => rctr_q_net_x2,
ce => ce_1_sg_x15,
clk => clk_1_sg_x15,
data_in => delay9_q_net,
en => "1",
rst => "0",
we(0) => constant6_op_net,
data_out => single_port_ram3_data_out_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "sg_2d_fir/5x5_Filters/Ctrl_Delay"
entity ctrl_delay_entity_b2aeac3e46 is
port (
addr: in std_logic_vector(11 downto 0);
av_i: in std_logic;
ce_1: in std_logic;
clk_1: in std_logic;
hb_i: in std_logic;
hs_i: in std_logic;
vb_i: in std_logic;
vs_i: in std_logic;
av_o: out std_logic;
hb_o: out std_logic;
hs_o: out std_logic;
vb_o: out std_logic;
vs_o: out std_logic
);
end ctrl_delay_entity_b2aeac3e46;
architecture structural of ctrl_delay_entity_b2aeac3e46 is
signal active_video_i_net_x0: std_logic;
signal bit0_y_net_x0: std_logic;
signal bit1_y_net_x0: std_logic;
signal bit2_y_net_x0: std_logic;
signal bit3_y_net_x0: std_logic;
signal bit4_y_net_x0: std_logic;
signal ce_1_sg_x16: std_logic;
signal clk_1_sg_x16: std_logic;
signal concat_y_net_x0: std_logic_vector(4 downto 0);
signal delay7_q_net: std_logic_vector(4 downto 0);
signal hblank_i_net_x0: std_logic;
signal hsync_i_net_x0: std_logic;
signal l3_x1: std_logic_vector(4 downto 0);
signal rctr_q_net_x3: std_logic_vector(11 downto 0);
signal vblank_i_net_x0: std_logic;
signal vsync_i_net_x0: std_logic;
begin
rctr_q_net_x3 <= addr;
active_video_i_net_x0 <= av_i;
ce_1_sg_x16 <= ce_1;
clk_1_sg_x16 <= clk_1;
hblank_i_net_x0 <= hb_i;
hsync_i_net_x0 <= hs_i;
vblank_i_net_x0 <= vb_i;
vsync_i_net_x0 <= vs_i;
av_o <= bit4_y_net_x0;
hb_o <= bit0_y_net_x0;
hs_o <= bit2_y_net_x0;
vb_o <= bit1_y_net_x0;
vs_o <= bit3_y_net_x0;
bit0: entity work.xlslice
generic map (
new_lsb => 0,
new_msb => 0,
x_width => 5,
y_width => 1
)
port map (
x => delay7_q_net,
y(0) => bit0_y_net_x0
);
bit1: entity work.xlslice
generic map (
new_lsb => 1,
new_msb => 1,
x_width => 5,
y_width => 1
)
port map (
x => delay7_q_net,
y(0) => bit1_y_net_x0
);
bit2: entity work.xlslice
generic map (
new_lsb => 2,
new_msb => 2,
x_width => 5,
y_width => 1
)
port map (
x => delay7_q_net,
y(0) => bit2_y_net_x0
);
bit3: entity work.xlslice
generic map (
new_lsb => 3,
new_msb => 3,
x_width => 5,
y_width => 1
)
port map (
x => delay7_q_net,
y(0) => bit3_y_net_x0
);
bit4: entity work.xlslice
generic map (
new_lsb => 4,
new_msb => 4,
x_width => 5,
y_width => 1
)
port map (
x => delay7_q_net,
y(0) => bit4_y_net_x0
);
concat: entity work.concat_2b3acb49f4
port map (
ce => '0',
clk => '0',
clr => '0',
in0(0) => active_video_i_net_x0,
in1(0) => vsync_i_net_x0,
in2(0) => hsync_i_net_x0,
in3(0) => vblank_i_net_x0,
in4(0) => hblank_i_net_x0,
y => concat_y_net_x0
);
delay7: entity work.delay_4714bdf2a7
port map (
ce => ce_1_sg_x16,
clk => clk_1_sg_x16,
clr => '0',
d => l3_x1,
q => delay7_q_net
);
line_buffer_d14b7609fd: entity work.line_buffer_entity_d14b7609fd
port map (
addr => rctr_q_net_x3,
ce_1 => ce_1_sg_x16,
clk_1 => clk_1_sg_x16,
data => concat_y_net_x0,
l3_x0 => l3_x1
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "sg_2d_fir/5x5_Filters/coefficient_memory"
entity coefficient_memory_entity_d275723ee2 is
port (
ce_1: in std_logic;
clk_1: in std_logic;
from_register1: in std_logic;
vsync: in std_logic;
constant1_x0: out std_logic;
constant2_x0: out std_logic_vector(6 downto 0);
counter_x0: out std_logic_vector(4 downto 0);
load: out std_logic
);
end coefficient_memory_entity_d275723ee2;
architecture structural of coefficient_memory_entity_d275723ee2 is
signal ce_1_sg_x47: std_logic;
signal clk_1_sg_x47: std_logic;
signal constant1_op_net_x0: std_logic;
signal constant2_op_net_x0: std_logic_vector(6 downto 0);
signal constant_op_net: std_logic_vector(4 downto 0);
signal convert1_dout_net: std_logic;
signal convert_dout_net: std_logic;
signal counter_op_net_x0: std_logic_vector(4 downto 0);
signal expression_dout_net: std_logic;
signal from_register1_data_out_net_x0: std_logic;
signal inverter_op_net: std_logic;
signal register1_q_net: std_logic;
signal register_q_net: std_logic;
signal relational3_op_net_x10: std_logic;
signal vsync_i_net_x1: std_logic;
begin
ce_1_sg_x47 <= ce_1;
clk_1_sg_x47 <= clk_1;
from_register1_data_out_net_x0 <= from_register1;
vsync_i_net_x1 <= vsync;
constant1_x0 <= constant1_op_net_x0;
constant2_x0 <= constant2_op_net_x0;
counter_x0 <= counter_op_net_x0;
load <= relational3_op_net_x10;
constant1: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant1_op_net_x0
);
constant2: entity work.constant_7244cd602b
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant2_op_net_x0
);
constant_x0: entity work.constant_fdce3802d7
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant_op_net
);
convert: entity work.xlconvert
generic map (
bool_conversion => 1,
din_arith => 1,
din_bin_pt => 0,
din_width => 1,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 1,
latency => 0,
overflow => xlWrap,
quantization => xlTruncate
)
port map (
ce => ce_1_sg_x47,
clk => clk_1_sg_x47,
clr => '0',
din(0) => register1_q_net,
en => "1",
dout(0) => convert_dout_net
);
convert1: entity work.xlconvert
generic map (
bool_conversion => 1,
din_arith => 1,
din_bin_pt => 0,
din_width => 1,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 1,
latency => 0,
overflow => xlWrap,
quantization => xlTruncate
)
port map (
ce => ce_1_sg_x47,
clk => clk_1_sg_x47,
clr => '0',
din(0) => inverter_op_net,
en => "1",
dout(0) => convert1_dout_net
);
counter: entity work.xlcounter_limit
generic map (
cnt_15_0 => 25,
cnt_31_16 => 0,
cnt_47_32 => 0,
cnt_63_48 => 0,
core_name0 => "cntr_11_0_862f833518f4973a",
count_limited => 1,
op_arith => xlUnsigned,
op_width => 5
)
port map (
ce => ce_1_sg_x47,
clk => clk_1_sg_x47,
clr => '0',
en(0) => relational3_op_net_x10,
rst(0) => convert_dout_net,
op => counter_op_net_x0
);
expression: entity work.expr_1e33fcde03
port map (
a(0) => vsync_i_net_x1,
b(0) => register_q_net,
ce => '0',
clk => '0',
clr => '0',
dout(0) => expression_dout_net
);
inverter: entity work.inverter_e2b989a05e
port map (
ce => ce_1_sg_x47,
clk => clk_1_sg_x47,
clr => '0',
ip(0) => from_register1_data_out_net_x0,
op(0) => inverter_op_net
);
register1: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x47,
clk => clk_1_sg_x47,
d(0) => expression_dout_net,
en => "1",
rst(0) => convert1_dout_net,
q(0) => register1_q_net
);
register_x0: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x47,
clk => clk_1_sg_x47,
d(0) => vsync_i_net_x1,
en => "1",
rst => "0",
q(0) => register_q_net
);
relational3: entity work.relational_dc5bc996c9
port map (
a => constant_op_net,
b => counter_op_net_x0,
ce => '0',
clk => '0',
clr => '0',
op(0) => relational3_op_net_x10
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "sg_2d_fir/5x5_Filters/line_ctrs/loop_ctr"
entity loop_ctr_entity_861427efa6 is
port (
ce_1: in std_logic;
clk_1: in std_logic;
reset: in std_logic;
count: out std_logic_vector(11 downto 0)
);
end loop_ctr_entity_861427efa6;
architecture structural of loop_ctr_entity_861427efa6 is
signal addsub1_s_net: std_logic_vector(11 downto 0);
signal bool2_dout_net: std_logic_vector(12 downto 0);
signal bool_dout_net: std_logic;
signal ce_1_sg_x48: std_logic;
signal clk_1_sg_x48: std_logic;
signal constant1_op_net: std_logic_vector(11 downto 0);
signal constant6_op_net: std_logic_vector(11 downto 0);
signal constant7_op_net: std_logic_vector(11 downto 0);
signal expression_dout_net_x0: std_logic;
signal expression_dout_net_x1: std_logic;
signal mux_y_net: std_logic_vector(12 downto 0);
signal rctr_q_net_x8: std_logic_vector(11 downto 0);
signal relational5_op_net: std_logic;
signal tcfb1_q_net: std_logic;
signal tcfb2_q_net: std_logic;
begin
ce_1_sg_x48 <= ce_1;
clk_1_sg_x48 <= clk_1;
expression_dout_net_x1 <= reset;
count <= rctr_q_net_x8;
addsub1: entity work.addsub_ba7fff8397
port map (
a => mux_y_net,
b => constant6_op_net,
ce => ce_1_sg_x48,
clk => clk_1_sg_x48,
clr => '0',
s => addsub1_s_net
);
bool: entity work.xlconvert
generic map (
bool_conversion => 1,
din_arith => 1,
din_bin_pt => 0,
din_width => 1,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 1,
latency => 0,
overflow => xlWrap,
quantization => xlTruncate
)
port map (
ce => ce_1_sg_x48,
clk => clk_1_sg_x48,
clr => '0',
din(0) => expression_dout_net_x1,
en => "1",
dout(0) => bool_dout_net
);
bool2: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 1,
din_bin_pt => 0,
din_width => 12,
dout_arith => 2,
dout_bin_pt => 0,
dout_width => 13,
latency => 0,
overflow => xlWrap,
quantization => xlTruncate
)
port map (
ce => ce_1_sg_x48,
clk => clk_1_sg_x48,
clr => '0',
din => rctr_q_net_x8,
en => "1",
dout => bool2_dout_net
);
constant1: entity work.constant_9b805894ff
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant1_op_net
);
constant6: entity work.constant_7c91b1b314
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant6_op_net
);
constant7: entity work.constant_be6eece885
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant7_op_net
);
expression: entity work.expr_f50101e101
port map (
ce => '0',
clk => '0',
clr => '0',
reset(0) => tcfb2_q_net,
tc(0) => tcfb1_q_net,
dout(0) => expression_dout_net_x0
);
mux: entity work.mux_b53670f063
port map (
ce => '0',
clk => '0',
clr => '0',
d0 => constant1_op_net,
d1 => bool2_dout_net,
sel(0) => expression_dout_net_x0,
y => mux_y_net
);
rctr: entity work.xlregister
generic map (
d_width => 12,
init_value => b"000000000000"
)
port map (
ce => ce_1_sg_x48,
clk => clk_1_sg_x48,
d => addsub1_s_net,
en => "1",
rst => "0",
q => rctr_q_net_x8
);
relational5: entity work.relational_d36fe12c1c
port map (
a => rctr_q_net_x8,
b => constant7_op_net,
ce => '0',
clk => '0',
clr => '0',
op(0) => relational5_op_net
);
tcfb1: entity work.delay_9f02caa990
port map (
ce => ce_1_sg_x48,
clk => clk_1_sg_x48,
clr => '0',
d(0) => relational5_op_net,
q(0) => tcfb1_q_net
);
tcfb2: entity work.delay_9f02caa990
port map (
ce => ce_1_sg_x48,
clk => clk_1_sg_x48,
clr => '0',
d(0) => bool_dout_net,
q(0) => tcfb2_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "sg_2d_fir/5x5_Filters/line_ctrs"
entity line_ctrs_entity_8878c4bf27 is
port (
ce_1: in std_logic;
clk_1: in std_logic;
h: in std_logic;
rst: in std_logic;
addr: out std_logic_vector(11 downto 0)
);
end line_ctrs_entity_8878c4bf27;
architecture structural of line_ctrs_entity_8878c4bf27 is
signal ce_1_sg_x49: std_logic;
signal clk_1_sg_x49: std_logic;
signal delay_q_net: std_logic;
signal expression_dout_net_x1: std_logic;
signal hsync_i_net_x1: std_logic;
signal rctr_q_net_x9: std_logic_vector(11 downto 0);
signal reset_net_x0: std_logic;
begin
ce_1_sg_x49 <= ce_1;
clk_1_sg_x49 <= clk_1;
hsync_i_net_x1 <= h;
reset_net_x0 <= rst;
addr <= rctr_q_net_x9;
delay: entity work.delay_5753e4c658
port map (
ce => ce_1_sg_x49,
clk => clk_1_sg_x49,
clr => '0',
d(0) => hsync_i_net_x1,
q(0) => delay_q_net
);
expression: entity work.expr_305312c97b
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => hsync_i_net_x1,
d1(0) => delay_q_net,
rst(0) => reset_net_x0,
dout(0) => expression_dout_net_x1
);
loop_ctr_861427efa6: entity work.loop_ctr_entity_861427efa6
port map (
ce_1 => ce_1_sg_x49,
clk_1 => clk_1_sg_x49,
reset => expression_dout_net_x1,
count => rctr_q_net_x9
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "sg_2d_fir/5x5_Filters"
entity x5x5_filters_entity_1ec75b0e3e is
port (
av_i: in std_logic;
b: in std_logic_vector(7 downto 0);
ce_1: in std_logic;
ce_logic_1: in std_logic;
clk_1: in std_logic;
from_register: in std_logic_vector(19 downto 0);
from_register1: in std_logic;
g: in std_logic_vector(7 downto 0);
hb_i: in std_logic;
hs_i: in std_logic;
r: in std_logic_vector(7 downto 0);
rst: in std_logic;
shared_memory: in std_logic_vector(6 downto 0);
vb_i: in std_logic;
vs_i: in std_logic;
b_o: out std_logic_vector(7 downto 0);
coefficient_memory: out std_logic;
coefficient_memory_x0: out std_logic_vector(6 downto 0);
coefficient_memory_x1: out std_logic_vector(4 downto 0);
de_o: out std_logic;
g_o: out std_logic_vector(7 downto 0);
hb_o: out std_logic;
hs_o: out std_logic;
r_o: out std_logic_vector(7 downto 0);
vb_o: out std_logic;
vs_o: out std_logic
);
end x5x5_filters_entity_1ec75b0e3e;
architecture structural of x5x5_filters_entity_1ec75b0e3e is
signal active_video_i_net_x1: std_logic;
signal bit0_y_net_x1: std_logic;
signal bit1_y_net_x1: std_logic;
signal bit2_y_net_x1: std_logic;
signal bit3_y_net_x1: std_logic;
signal bit4_y_net_x1: std_logic;
signal blue_x2: std_logic_vector(7 downto 0);
signal ce_1_sg_x50: std_logic;
signal ce_logic_1_sg_x21: std_logic;
signal clk_1_sg_x50: std_logic;
signal constant1_op_net_x1: std_logic;
signal constant2_op_net_x1: std_logic_vector(6 downto 0);
signal convert1_dout_net_x4: std_logic_vector(7 downto 0);
signal convert1_dout_net_x5: std_logic_vector(7 downto 0);
signal convert1_dout_net_x6: std_logic_vector(7 downto 0);
signal counter_op_net_x1: std_logic_vector(4 downto 0);
signal from_register1_data_out_net_x1: std_logic;
signal from_register_data_out_net_x6: std_logic_vector(19 downto 0);
signal green_x2: std_logic_vector(7 downto 0);
signal hblank_i_net_x1: std_logic;
signal hsync_i_net_x2: std_logic;
signal rctr_q_net_x9: std_logic_vector(11 downto 0);
signal red_x2: std_logic_vector(7 downto 0);
signal relational3_op_net_x10: std_logic;
signal reset_net_x1: std_logic;
signal shared_memory_data_out_net_x21: std_logic_vector(6 downto 0);
signal vblank_i_net_x1: std_logic;
signal vsync_i_net_x2: std_logic;
begin
active_video_i_net_x1 <= av_i;
blue_x2 <= b;
ce_1_sg_x50 <= ce_1;
ce_logic_1_sg_x21 <= ce_logic_1;
clk_1_sg_x50 <= clk_1;
from_register_data_out_net_x6 <= from_register;
from_register1_data_out_net_x1 <= from_register1;
green_x2 <= g;
hblank_i_net_x1 <= hb_i;
hsync_i_net_x2 <= hs_i;
red_x2 <= r;
reset_net_x1 <= rst;
shared_memory_data_out_net_x21 <= shared_memory;
vblank_i_net_x1 <= vb_i;
vsync_i_net_x2 <= vs_i;
b_o <= convert1_dout_net_x4;
coefficient_memory <= constant1_op_net_x1;
coefficient_memory_x0 <= constant2_op_net_x1;
coefficient_memory_x1 <= counter_op_net_x1;
de_o <= bit4_y_net_x1;
g_o <= convert1_dout_net_x5;
hb_o <= bit0_y_net_x1;
hs_o <= bit2_y_net_x1;
r_o <= convert1_dout_net_x6;
vb_o <= bit1_y_net_x1;
vs_o <= bit3_y_net_x1;
blue_filter_d29ca0c8b1: entity work.blue_filter_entity_d29ca0c8b1
port map (
addr => rctr_q_net_x9,
ce_1 => ce_1_sg_x50,
ce_logic_1 => ce_logic_1_sg_x21,
clk_1 => clk_1_sg_x50,
coef => shared_memory_data_out_net_x21,
din => blue_x2,
gain => from_register_data_out_net_x6,
load => relational3_op_net_x10,
dout => convert1_dout_net_x4
);
coefficient_memory_d275723ee2: entity work.coefficient_memory_entity_d275723ee2
port map (
ce_1 => ce_1_sg_x50,
clk_1 => clk_1_sg_x50,
from_register1 => from_register1_data_out_net_x1,
vsync => vsync_i_net_x2,
constant1_x0 => constant1_op_net_x1,
constant2_x0 => constant2_op_net_x1,
counter_x0 => counter_op_net_x1,
load => relational3_op_net_x10
);
ctrl_delay_b2aeac3e46: entity work.ctrl_delay_entity_b2aeac3e46
port map (
addr => rctr_q_net_x9,
av_i => active_video_i_net_x1,
ce_1 => ce_1_sg_x50,
clk_1 => clk_1_sg_x50,
hb_i => hblank_i_net_x1,
hs_i => hsync_i_net_x2,
vb_i => vblank_i_net_x1,
vs_i => vsync_i_net_x2,
av_o => bit4_y_net_x1,
hb_o => bit0_y_net_x1,
hs_o => bit2_y_net_x1,
vb_o => bit1_y_net_x1,
vs_o => bit3_y_net_x1
);
green_filter_dc51fce7d5: entity work.blue_filter_entity_d29ca0c8b1
port map (
addr => rctr_q_net_x9,
ce_1 => ce_1_sg_x50,
ce_logic_1 => ce_logic_1_sg_x21,
clk_1 => clk_1_sg_x50,
coef => shared_memory_data_out_net_x21,
din => green_x2,
gain => from_register_data_out_net_x6,
load => relational3_op_net_x10,
dout => convert1_dout_net_x5
);
line_ctrs_8878c4bf27: entity work.line_ctrs_entity_8878c4bf27
port map (
ce_1 => ce_1_sg_x50,
clk_1 => clk_1_sg_x50,
h => hsync_i_net_x2,
rst => reset_net_x1,
addr => rctr_q_net_x9
);
red_filter_078d79d78e: entity work.blue_filter_entity_d29ca0c8b1
port map (
addr => rctr_q_net_x9,
ce_1 => ce_1_sg_x50,
ce_logic_1 => ce_logic_1_sg_x21,
clk_1 => clk_1_sg_x50,
coef => shared_memory_data_out_net_x21,
din => red_x2,
gain => from_register_data_out_net_x6,
load => relational3_op_net_x10,
dout => convert1_dout_net_x6
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "sg_2d_fir/EDK Processor"
entity edk_processor_entity_45d14a6139 is
port (
plb_abus: in std_logic_vector(31 downto 0);
plb_ce_1: in std_logic;
plb_clk_1: in std_logic;
plb_pavalid: in std_logic;
plb_rnw: in std_logic;
plb_wrdbus: in std_logic_vector(31 downto 0);
sg_plb_addrpref: in std_logic_vector(19 downto 0);
shared_memory: in std_logic_vector(6 downto 0);
splb_rst: in std_logic;
to_register: in std_logic;
to_register1: in std_logic_vector(19 downto 0);
constant5_x0: out std_logic;
plb_decode_x0: out std_logic;
plb_decode_x1: out std_logic;
plb_decode_x2: out std_logic;
plb_decode_x3: out std_logic;
plb_decode_x4: out std_logic_vector(31 downto 0);
plb_memmap_x0: out std_logic;
plb_memmap_x1: out std_logic;
plb_memmap_x2: out std_logic_vector(19 downto 0);
plb_memmap_x3: out std_logic;
plb_memmap_x4: out std_logic_vector(4 downto 0);
plb_memmap_x5: out std_logic_vector(6 downto 0);
plb_memmap_x6: out std_logic
);
end edk_processor_entity_45d14a6139;
architecture structural of edk_processor_entity_45d14a6139 is
signal bankaddr: std_logic_vector(1 downto 0);
signal coef_buffer_addr_x0: std_logic_vector(4 downto 0);
signal coef_buffer_din_x0: std_logic_vector(6 downto 0);
signal coef_buffer_dout_x0: std_logic_vector(6 downto 0);
signal coef_buffer_we_x0: std_logic;
signal coef_gain_din_x0: std_logic_vector(19 downto 0);
signal coef_gain_dout_x0: std_logic_vector(19 downto 0);
signal coef_gain_en_x0: std_logic;
signal coef_update_din_x0: std_logic;
signal coef_update_dout_x0: std_logic;
signal coef_update_en_x0: std_logic;
signal linearaddr: std_logic_vector(7 downto 0);
signal plb_abus_net_x0: std_logic_vector(31 downto 0);
signal plb_ce_1_sg_x0: std_logic;
signal plb_clk_1_sg_x0: std_logic;
signal plb_pavalid_net_x0: std_logic;
signal plb_rnw_net_x0: std_logic;
signal plb_wrdbus_net_x0: std_logic_vector(31 downto 0);
signal rddata: std_logic_vector(31 downto 0);
signal rnwreg: std_logic;
signal sg_plb_addrpref_net_x0: std_logic_vector(19 downto 0);
signal sl_addrack_x0: std_logic;
signal sl_rdcomp_x0: std_logic;
signal sl_rddack_x0: std_logic;
signal sl_rddbus_x0: std_logic_vector(31 downto 0);
signal sl_wait_x0: std_logic;
signal sl_wrdack_x0: std_logic;
signal splb_rst_net_x0: std_logic;
signal wrdbusreg: std_logic_vector(31 downto 0);
begin
plb_abus_net_x0 <= plb_abus;
plb_ce_1_sg_x0 <= plb_ce_1;
plb_clk_1_sg_x0 <= plb_clk_1;
plb_pavalid_net_x0 <= plb_pavalid;
plb_rnw_net_x0 <= plb_rnw;
plb_wrdbus_net_x0 <= plb_wrdbus;
sg_plb_addrpref_net_x0 <= sg_plb_addrpref;
coef_buffer_dout_x0 <= shared_memory;
splb_rst_net_x0 <= splb_rst;
coef_update_dout_x0 <= to_register;
coef_gain_dout_x0 <= to_register1;
constant5_x0 <= sl_wait_x0;
plb_decode_x0 <= sl_addrack_x0;
plb_decode_x1 <= sl_rdcomp_x0;
plb_decode_x2 <= sl_wrdack_x0;
plb_decode_x3 <= sl_rddack_x0;
plb_decode_x4 <= sl_rddbus_x0;
plb_memmap_x0 <= coef_update_din_x0;
plb_memmap_x1 <= coef_update_en_x0;
plb_memmap_x2 <= coef_gain_din_x0;
plb_memmap_x3 <= coef_gain_en_x0;
plb_memmap_x4 <= coef_buffer_addr_x0;
plb_memmap_x5 <= coef_buffer_din_x0;
plb_memmap_x6 <= coef_buffer_we_x0;
constant5: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => sl_wait_x0
);
plb_decode: entity work.mcode_block_f4d0462e0e
port map (
addrpref => sg_plb_addrpref_net_x0,
ce => plb_ce_1_sg_x0,
clk => plb_clk_1_sg_x0,
clr => '0',
plbabus => plb_abus_net_x0,
plbpavalid(0) => plb_pavalid_net_x0,
plbrnw(0) => plb_rnw_net_x0,
plbrst(0) => splb_rst_net_x0,
plbwrdbus => plb_wrdbus_net_x0,
rddata => rddata,
addrack(0) => sl_addrack_x0,
bankaddr => bankaddr,
linearaddr => linearaddr,
rdcomp(0) => sl_rdcomp_x0,
rddack(0) => sl_rddack_x0,
rddbus => sl_rddbus_x0,
rnwreg(0) => rnwreg,
wrdack(0) => sl_wrdack_x0,
wrdbusreg => wrdbusreg
);
plb_memmap: entity work.mcode_block_6fff803424
port map (
addrack(0) => sl_addrack_x0,
bankaddr => bankaddr,
ce => plb_ce_1_sg_x0,
clk => plb_clk_1_sg_x0,
clr => '0',
linearaddr => linearaddr,
rnwreg(0) => rnwreg,
sm_coef_buffer => coef_buffer_dout_x0,
sm_coef_gain => coef_gain_dout_x0,
sm_coef_update(0) => coef_update_dout_x0,
wrdbus => wrdbusreg,
read_bank_out => rddata,
sm_coef_buffer_addr => coef_buffer_addr_x0,
sm_coef_buffer_din => coef_buffer_din_x0,
sm_coef_buffer_we(0) => coef_buffer_we_x0,
sm_coef_gain_din => coef_gain_din_x0,
sm_coef_gain_en(0) => coef_gain_en_x0,
sm_coef_update_din(0) => coef_update_din_x0,
sm_coef_update_en(0) => coef_update_en_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "sg_2d_fir"
entity sg_2d_fir is
port (
active_video_i: in std_logic;
ce_1: in std_logic;
ce_logic_1: in std_logic;
clk_1: in std_logic;
data_out: in std_logic_vector(19 downto 0);
data_out_x0: in std_logic;
data_out_x1: in std_logic_vector(6 downto 0);
data_out_x2: in std_logic_vector(6 downto 0);
dout: in std_logic;
dout_x0: in std_logic_vector(19 downto 0);
hblank_i: in std_logic;
hsync_i: in std_logic;
plb_abus: in std_logic_vector(31 downto 0);
plb_ce_1: in std_logic;
plb_clk_1: in std_logic;
plb_pavalid: in std_logic;
plb_rnw: in std_logic;
plb_wrdbus: in std_logic_vector(31 downto 0);
reset: in std_logic;
sg_plb_addrpref: in std_logic_vector(19 downto 0);
splb_rst: in std_logic;
vblank_i: in std_logic;
video_data_i: in std_logic_vector(23 downto 0);
vsync_i: in std_logic;
active_video_o: out std_logic;
addr: out std_logic_vector(4 downto 0);
addr_x0: out std_logic_vector(4 downto 0);
data_in: out std_logic_vector(6 downto 0);
data_in_x0: out std_logic_vector(6 downto 0);
data_in_x1: out std_logic;
data_in_x2: out std_logic_vector(19 downto 0);
en: out std_logic;
en_x0: out std_logic;
hblank_o: out std_logic;
hsync_o: out std_logic;
sl_addrack: out std_logic;
sl_rdcomp: out std_logic;
sl_rddack: out std_logic;
sl_rddbus: out std_logic_vector(31 downto 0);
sl_wait: out std_logic;
sl_wrcomp: out std_logic;
sl_wrdack: out std_logic;
vblank_o: out std_logic;
video_data_o: out std_logic_vector(23 downto 0);
vsync_o: out std_logic;
we: out std_logic;
we_x0: out std_logic
);
end sg_2d_fir;
architecture structural of sg_2d_fir is
attribute core_generation_info: string;
attribute core_generation_info of structural : architecture is "sg_2d_fir,sysgen_core,{clock_period=10.00000000,clocking=Clock_Enables,sample_periods=1.00000000000 1.00000000000,testbench=0,total_blocks=669,xilinx_adder_subtracter_block=13,xilinx_arithmetic_relational_operator_block=23,xilinx_assert_block=3,xilinx_bit_slice_extractor_block=11,xilinx_bitwise_expression_evaluator_block=3,xilinx_bus_concatenator_block=2,xilinx_bus_multiplexer_block=4,xilinx_constant_block_block=29,xilinx_counter_block=7,xilinx_delay_block=25,xilinx_edk_processor_block=1,xilinx_fir_compiler_5_0_block=15,xilinx_gateway_in_block=13,xilinx_gateway_out_block=13,xilinx_inverter_block=16,xilinx_logical_block_block=33,xilinx_mcode_block_block=2,xilinx_multiplier_block=3,xilinx_negate_block_block=3,xilinx_register_block=63,xilinx_shared_memory_based_from_register_block=2,xilinx_shared_memory_based_to_register_block=2,xilinx_shared_memory_random_access_memory_block=2,xilinx_single_port_random_access_memory_block=16,xilinx_system_generator_block=1,xilinx_type_converter_block=7,}";
signal active_video_i_net: std_logic;
signal active_video_o_net: std_logic;
signal addr_net: std_logic_vector(4 downto 0);
signal addr_x0_net: std_logic_vector(4 downto 0);
signal blue_x2: std_logic_vector(7 downto 0);
signal ce_1_sg_x51: std_logic;
signal ce_logic_1_sg_x22: std_logic;
signal clk_1_sg_x51: std_logic;
signal convert1_dout_net_x4: std_logic_vector(7 downto 0);
signal convert1_dout_net_x5: std_logic_vector(7 downto 0);
signal convert1_dout_net_x6: std_logic_vector(7 downto 0);
signal data_in_net: std_logic_vector(6 downto 0);
signal data_in_x0_net: std_logic_vector(6 downto 0);
signal data_in_x1_net: std_logic;
signal data_in_x2_net: std_logic_vector(19 downto 0);
signal data_out_net: std_logic_vector(19 downto 0);
signal data_out_x0_net: std_logic;
signal data_out_x1_net: std_logic_vector(6 downto 0);
signal data_out_x2_net: std_logic_vector(6 downto 0);
signal dout_net: std_logic;
signal dout_x0_net: std_logic_vector(19 downto 0);
signal en_net: std_logic;
signal en_x0_net: std_logic;
signal green_x2: std_logic_vector(7 downto 0);
signal hblank_i_net: std_logic;
signal hblank_o_net: std_logic;
signal hsync_i_net: std_logic;
signal hsync_o_net: std_logic;
signal plb_abus_net: std_logic_vector(31 downto 0);
signal plb_ce_1_sg_x1: std_logic;
signal plb_clk_1_sg_x1: std_logic;
signal plb_pavalid_net: std_logic;
signal plb_rnw_net: std_logic;
signal plb_wrdbus_net: std_logic_vector(31 downto 0);
signal red_x2: std_logic_vector(7 downto 0);
signal reset_net: std_logic;
signal sg_plb_addrpref_net: std_logic_vector(19 downto 0);
signal sl_addrack_net: std_logic;
signal sl_rdcomp_net: std_logic;
signal sl_rddack_net: std_logic;
signal sl_rddbus_net: std_logic_vector(31 downto 0);
signal sl_wait_net: std_logic;
signal sl_wrdack_x1: std_logic;
signal splb_rst_net: std_logic;
signal vblank_i_net: std_logic;
signal vblank_o_net: std_logic;
signal video_data_i_net: std_logic_vector(23 downto 0);
signal video_data_o_net: std_logic_vector(23 downto 0);
signal vsync_i_net: std_logic;
signal vsync_o_net: std_logic;
signal we_net: std_logic;
signal we_x0_net: std_logic;
begin
active_video_i_net <= active_video_i;
ce_1_sg_x51 <= ce_1;
ce_logic_1_sg_x22 <= ce_logic_1;
clk_1_sg_x51 <= clk_1;
data_out_net <= data_out;
data_out_x0_net <= data_out_x0;
data_out_x1_net <= data_out_x1;
data_out_x2_net <= data_out_x2;
dout_net <= dout;
dout_x0_net <= dout_x0;
hblank_i_net <= hblank_i;
hsync_i_net <= hsync_i;
plb_abus_net <= plb_abus;
plb_ce_1_sg_x1 <= plb_ce_1;
plb_clk_1_sg_x1 <= plb_clk_1;
plb_pavalid_net <= plb_pavalid;
plb_rnw_net <= plb_rnw;
plb_wrdbus_net <= plb_wrdbus;
reset_net <= reset;
sg_plb_addrpref_net <= sg_plb_addrpref;
splb_rst_net <= splb_rst;
vblank_i_net <= vblank_i;
video_data_i_net <= video_data_i;
vsync_i_net <= vsync_i;
active_video_o <= active_video_o_net;
addr <= addr_net;
addr_x0 <= addr_x0_net;
data_in <= data_in_net;
data_in_x0 <= data_in_x0_net;
data_in_x1 <= data_in_x1_net;
data_in_x2 <= data_in_x2_net;
en <= en_net;
en_x0 <= en_x0_net;
hblank_o <= hblank_o_net;
hsync_o <= hsync_o_net;
sl_addrack <= sl_addrack_net;
sl_rdcomp <= sl_rdcomp_net;
sl_rddack <= sl_rddack_net;
sl_rddbus <= sl_rddbus_net;
sl_wait <= sl_wait_net;
sl_wrcomp <= sl_wrdack_x1;
sl_wrdack <= sl_wrdack_x1;
vblank_o <= vblank_o_net;
video_data_o <= video_data_o_net;
vsync_o <= vsync_o_net;
we <= we_net;
we_x0 <= we_x0_net;
concat: entity work.concat_d0d1b9533e
port map (
ce => '0',
clk => '0',
clr => '0',
in0 => convert1_dout_net_x6,
in1 => convert1_dout_net_x5,
in2 => convert1_dout_net_x4,
y => video_data_o_net
);
edk_processor_45d14a6139: entity work.edk_processor_entity_45d14a6139
port map (
plb_abus => plb_abus_net,
plb_ce_1 => plb_ce_1_sg_x1,
plb_clk_1 => plb_clk_1_sg_x1,
plb_pavalid => plb_pavalid_net,
plb_rnw => plb_rnw_net,
plb_wrdbus => plb_wrdbus_net,
sg_plb_addrpref => sg_plb_addrpref_net,
shared_memory => data_out_x2_net,
splb_rst => splb_rst_net,
to_register => dout_net,
to_register1 => dout_x0_net,
constant5_x0 => sl_wait_net,
plb_decode_x0 => sl_addrack_net,
plb_decode_x1 => sl_rdcomp_net,
plb_decode_x2 => sl_wrdack_x1,
plb_decode_x3 => sl_rddack_net,
plb_decode_x4 => sl_rddbus_net,
plb_memmap_x0 => data_in_x1_net,
plb_memmap_x1 => en_net,
plb_memmap_x2 => data_in_x2_net,
plb_memmap_x3 => en_x0_net,
plb_memmap_x4 => addr_x0_net,
plb_memmap_x5 => data_in_x0_net,
plb_memmap_x6 => we_x0_net
);
slice15downto8: entity work.xlslice
generic map (
new_lsb => 8,
new_msb => 15,
x_width => 24,
y_width => 8
)
port map (
x => video_data_i_net,
y => green_x2
);
slice23downto16: entity work.xlslice
generic map (
new_lsb => 16,
new_msb => 23,
x_width => 24,
y_width => 8
)
port map (
x => video_data_i_net,
y => red_x2
);
slice7downto0: entity work.xlslice
generic map (
new_lsb => 0,
new_msb => 7,
x_width => 24,
y_width => 8
)
port map (
x => video_data_i_net,
y => blue_x2
);
x5x5_filters_1ec75b0e3e: entity work.x5x5_filters_entity_1ec75b0e3e
port map (
av_i => active_video_i_net,
b => blue_x2,
ce_1 => ce_1_sg_x51,
ce_logic_1 => ce_logic_1_sg_x22,
clk_1 => clk_1_sg_x51,
from_register => data_out_net,
from_register1 => data_out_x0_net,
g => green_x2,
hb_i => hblank_i_net,
hs_i => hsync_i_net,
r => red_x2,
rst => reset_net,
shared_memory => data_out_x1_net,
vb_i => vblank_i_net,
vs_i => vsync_i_net,
b_o => convert1_dout_net_x4,
coefficient_memory => we_net,
coefficient_memory_x0 => data_in_net,
coefficient_memory_x1 => addr_net,
de_o => active_video_o_net,
g_o => convert1_dout_net_x5,
hb_o => hblank_o_net,
hs_o => hsync_o_net,
r_o => convert1_dout_net_x6,
vb_o => vblank_o_net,
vs_o => vsync_o_net
);
end structural;
| gpl-3.0 | 027c4f2dc9f3c35d461f9252b81e13ad | 0.583522 | 3.23539 | false | false | false | false |
bertuccio/ARQ | Practica5/memoria_simple.vhd | 3 | 3,298 | library STD;
use STD.textio.all;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.std_logic_textio.all;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity memoria is
generic(
C_ELF_FILENAME : string := "programa";
C_TARGET_SECTION : string := ".text"; -- No se usa
C_BASE_ADDRESS : integer := 16#400000#; -- No se usa
C_MEM_SIZE : integer := 1024;
C_WAIT_STATES : integer := 0 -- No se usa
);
Port ( Addr : in std_logic_vector(31 downto 0);
DataIn : in std_logic_vector(31 downto 0);
RdStb : in std_logic ;
WrStb : in std_logic ;
Clk : in std_logic ;
Reset : in std_logic ; -- No se usa
AddrStb : in std_logic ; -- No se usa
Rdy : out std_logic ; -- No se usa, siempre a '1'
DataOut : out std_logic_vector(31 downto 0));
end memoria;
architecture Behavioral of memoria is
type matriz is array(0 to C_MEM_SIZE-1) of STD_LOGIC_VECTOR(7 downto 0);
signal memo: matriz;
signal aux : STD_LOGIC_VECTOR (31 downto 0):= (others=>'0');
begin
process (clk)
variable cargar : boolean := true;
variable address : STD_LOGIC_VECTOR(31 downto 0);
variable datum : STD_LOGIC_VECTOR(31 downto 0);
file bin_file : text is in C_ELF_FILENAME;
variable current_line : line;
begin
if cargar then
-- primero iniciamos la memoria con ceros
for i in 0 to C_MEM_SIZE-1 loop
memo(i) <= (others => '0');
end loop;
-- luego cargamos el archivo en la misma
while (not endfile (bin_file)) loop
readline (bin_file, current_line);
hread(current_line, address);
hread(current_line, datum);
assert CONV_INTEGER(address(30 downto 0))<C_MEM_SIZE
report "Direccion fuera de rango en el fichero de la memoria"
severity failure;
memo(CONV_INTEGER(address(30 downto 0))) <= datum(31 downto 24);
memo(CONV_INTEGER(address(30 downto 0)+'1')) <= datum(23 downto 16);
memo(CONV_INTEGER(address(30 downto 0)+"10")) <= datum(15 downto 8);
memo(CONV_INTEGER(address(30 downto 0)+"11")) <= datum(7 downto 0);
end loop;
-- por ultimo cerramos el archivo y actualizamos el flag de memoria cargada
file_close (bin_file);
cargar := false;
elsif (Clk'event and Clk = '0') then
if (WrStb = '1') then
memo(CONV_INTEGER(Addr(30 downto 0))) <= DataIn(31 downto 24);
memo(CONV_INTEGER(Addr(30 downto 0)+'1')) <= DataIn(23 downto 16);
memo(CONV_INTEGER(Addr(30 downto 0)+"10")) <= DataIn(15 downto 8);
memo(CONV_INTEGER(Addr(30 downto 0)+"11")) <= DataIn(7 downto 0);
elsif (RdStb = '1')then
aux(31 downto 24) <= memo(conv_integer(Addr(30 downto 0)));
aux(23 downto 16) <= memo(conv_integer(Addr(30 downto 0)+'1'));
aux(15 downto 8) <= memo(conv_integer(Addr(30 downto 0)+"10"));
aux(7 downto 0) <= memo(conv_integer(Addr(30 downto 0)+"11"));
end if;
end if;
end process;
DataOut <= aux;
Rdy <= '1';
end Behavioral;
| mit | 56390914dbe53ce535c33bb6c708f150 | 0.608854 | 3.317907 | false | false | false | false |
GSimas/EEL5105 | Eletr-Digital/Relatório3/DIVISOR/divisor120.vhd | 1 | 4,587 | -- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_counter
-- ============================================================
-- File Name: divisor120.vhd
-- Megafunction Name(s):
-- lpm_counter
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY divisor120 IS
PORT
(
clock : IN STD_LOGIC ;
cout : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (19 DOWNTO 0)
);
END divisor120;
ARCHITECTURE SYN OF divisor120 IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (19 DOWNTO 0);
COMPONENT lpm_counter
GENERIC (
lpm_direction : STRING;
lpm_modulus : NATURAL;
lpm_port_updown : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
clock : IN STD_LOGIC ;
cout : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (19 DOWNTO 0)
);
END COMPONENT;
BEGIN
cout <= sub_wire0;
q <= sub_wire1(19 DOWNTO 0);
lpm_counter_component : lpm_counter
GENERIC MAP (
lpm_direction => "UP",
lpm_modulus => 208333,
lpm_port_updown => "PORT_UNUSED",
lpm_type => "LPM_COUNTER",
lpm_width => 20
)
PORT MAP (
clock => clock,
cout => sub_wire0,
q => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CNT_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-- Retrieval info: PRIVATE: CarryOut NUMERIC "1"
-- Retrieval info: PRIVATE: Direction NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
-- Retrieval info: PRIVATE: ModulusCounter NUMERIC "1"
-- Retrieval info: PRIVATE: ModulusValue NUMERIC "208333"
-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "20"
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
-- Retrieval info: CONSTANT: LPM_MODULUS NUMERIC "208333"
-- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "20"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: cout 0 0 0 0 OUTPUT NODEFVAL cout
-- Retrieval info: USED_PORT: q 0 0 20 0 OUTPUT NODEFVAL q[19..0]
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 20 0 @q 0 0 20 0
-- Retrieval info: CONNECT: cout 0 0 0 0 @cout 0 0 0 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL divisor120.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL divisor120.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL divisor120.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL divisor120.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL divisor120_inst.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL divisor120_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL divisor120_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: lpm
| mit | d1018bf6f123a0e227cb9070728964aa | 0.65751 | 3.71417 | false | false | false | false |
GSimas/EEL5105 | PROJETO-EEL5105/Projeto/FSM_clock.vhd | 1 | 1,425 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--FSM para geracao de clocks
entity FSM_clock is port(
CLK: in std_logic;
CLK1, CLK2, CLK3, CLK4, CLK5: out std_logic;
CLK_led: out std_logic
);
end FSM_clock;
--Definicao de Arquitetura
architecture bhv of FSM_clock is
signal conta1, conta2, conta3, conta4, conta5: integer := 0;
signal sig_led: std_logic := '0';
begin
P1: process(CLK, conta1, conta2, conta3, conta4, conta5)
begin
if CLK'event and CLK = '1' then -- Incrementar contador na subida de clock
conta1 <= conta1 + 1;
conta2 <= conta2 + 1;
conta3 <= conta3 + 1;
conta4 <= conta4 + 1;
conta5 <= conta5 + 1;
end if;
CLK1 <= '0';
CLK2 <= '0';
CLK3 <= '0';
CLK4 <= '0';
CLK5 <= '0';
if conta1 = 50000000 then -- se atingir 50.000.000 - CLK 1Hz
conta1 <= 0;
CLK1 <= '1';
end if;
if conta2 = 25000000 then -- se atingir 25.000.000 CLK 2Hz
conta2 <= 0;
CLK2 <= '1';
end if;
if conta3 = 16666667 then -- se atingir 16.666.667 CLK 3Hz
conta3 <= 0;
CLK3 <= '1';
end if;
if conta4 = 12500000 then -- se atingir 12.500.000 CLK 4Hz
conta4 <= 0;
CLK4 <= '1';
end if;
if conta5 = 10000000 then -- se atingir 10.000.000 CLK 5Hz
conta5 <= 0;
CLK5 <= '1';
sig_led <= not(sig_led);
end if;
end process;
CLK_led <= sig_led;
end bhv;
| mit | c07e55bd3b6dd349c9711d71cb163769 | 0.58386 | 2.673546 | false | false | false | false |
hoglet67/AtomFpga | src/common/AtomPL8.vhd | 2 | 7,621 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity AtomPL8 is
port (
-- Atom side
clk : in std_logic;
enable : in std_logic;
nRST : in std_logic; -- Reset from 6502
RW : in std_logic; -- R/W
Addr : in std_logic_vector(2 downto 0); -- CPU Address bus
DataIn : in std_logic_vector(7 downto 0); -- CPU Data bus (in)
DataOut : out std_logic_vector(7 downto 0); -- CPU Data bus (out)
-- AVR side
AVRDataIn : in std_logic_vector(7 downto 0); -- AVR 'Data bus' PC0..7 on AVR
AVRDataOut : out std_logic_vector(7 downto 0); -- AVR 'Data bus' PC0..7 on AVR
nARD : in std_logic; -- Read strobe from AVR PB0 on AVR
nAWR : in std_logic; -- Write strobe from AVR PB1 on AVR
AVRA0 : in std_logic; -- Address line from AVR
AVRINTOut : out std_logic; -- Inturrupt to AVR PB2 on AVR
-- Test
AtomIORDOut : out std_logic;
AtomIOWROut : out std_logic
);
end AtomPL8;
architecture Behavioral of AtomPL8 is
-- Combinatorial signals
signal RDS : std_logic;
signal WDS : std_logic;
signal AtomRD : std_logic;
signal AtomWR : std_logic;
signal AtomIO : std_logic;
signal AtomIORD : std_logic;
signal AtomIOWR : std_logic;
signal AVRStatus : std_logic;
signal AVRStatusRD : std_logic;
signal AtomCMDWR : std_logic;
signal nAVRRDData : std_logic;
signal AtomDataOut : std_logic_vector(7 downto 0);
signal Test1 : std_logic;
signal Test2 : std_logic;
-- Atom to AVR and AVR to Atom registers
signal AtomToAVR : std_logic_vector(7 downto 0);
signal AVRToAtom : std_logic_vector(7 downto 0);
signal AddrLatch : std_logic_vector(2 downto 0);
signal AtomRW : std_logic;
signal AVRINT : std_logic;
-- Handshake bits
signal AtomW_AVRR : std_logic; -- Set by Atom write, cleared by AVR read.
signal AVRW_AtomR : std_logic; -- Set by AVR write, cleared by Atom read.
signal AVRBusy : std_logic; -- Set by Atom write, cleard by AVR write
-- Edge detection bits
signal AtomIORD1 : std_logic;
signal AtomIOWR1 : std_logic;
signal nAVRRDData1: std_logic;
signal AVRINT1 : std_logic;
signal nAWR1 : std_logic;
signal AtomCMDWR1 : std_logic;
begin
-- ==========================================================
-- Combinatorial logic
-- ==========================================================
-- Atom read strobes and address decodes
RDS <= RW;
WDS <= not RW;
AtomRD <= RDS and enable;
AtomWR <= WDS and enable;
AtomIO <= '1' when (Addr >= "000" and Addr <= "011") else '0';
AtomCMDWR <= '1' when (Addr = "000" and AtomWR = '1') else '0';
AVRStatus <= '1' when (Addr = "100") else '0';
Test1 <= '1' when (Addr = "101") else '0';
Test2 <= '1' when (Addr = "110") else '0';
AVRStatusRD <= AVRStatus and AtomRD;
AtomIORD <= AtomIO and AtomRD;
AtomIOWR <= AtomIO and AtomWR;
-- goes low when AVR reads data.
nAVRRDData <= nARD or AVRA0;
-- Signal to the AVR that the Atom has read or written
AVRINT <= AtomIORD or AtomIOWR;
AVRINTOut <= AVRInt;
-- Assign AtomDataOut, depending on if reading staus or data
AtomDataOut <= ("00000" & AVRW_AtomR & AtomW_AVRR & AVRBusy) when AVRStatus = '1' else
( "000" & AtomRW & "0" & AddrLatch) when Test1 = '1' else
AtomToAVR when Test2 = '1' else
AVRToAtom;
-- When the Atom reads give it the AVR data
-- Data = AtomRD ? AtomDataOut : 8'bz;
DataOut <= AtomDataOut;
-- Assign AVRDataOut, depending on if reading staus or data
AVRDataOut <= ("000" & AtomRW & "0" & AddrLatch) when AVRA0 = '1' else AtomToAVR;
AtomIORDOut <= AtomIORD;
AtomIOWROut <= AtomIOWR;
-- ==========================================================
-- Synchronous logic
-- ==========================================================
EdgeProcess : process (nRST, clk)
begin
if nRST = '0' then
AtomIORD1 <= '0';
AtomIOWR1 <= '0';
nAVRRDData1 <= '0';
AVRINT1 <= '0';
nAWR1 <= '0';
AtomCMDWR1 <= '0';
elsif rising_edge(clk) then
AtomIORD1 <= AtomIORD;
AtomIOWR1 <= AtomIOWR;
nAVRRDData1 <= nAVRRDData;
AVRINT1 <= AVRINT;
nAWR1 <= nAWR;
AtomCMDWR1 <= AtomCMDWR;
end if;
end process;
-- Capture the bottom 3 address lines on a write by the Atom.
AddrLatchProcess : process (nRST, clk)
begin
if nRST = '0' then
AddrLatch <= "000";
elsif rising_edge(clk) and (AtomIOWR = '1' and AtomIOWR1 = '0') then
AddrLatch <= Addr;
end if;
end process;
-- Latch read or write
AtomRWProcess : process (clk)
begin
if rising_edge(clk) and ((AtomIOWR = '1' and AtomIOWR1 = '0') or (AtomIORD = '1' and AtomIORD1 = '0')) then
AtomRW <= RW;
end if;
end process;
-- Latch Atom to AVR reg on atom write
-- This may be dodgy on this edge!!
AtomToAVRProcess : process (clk)
begin
if rising_edge(clk) and (AtomIOWR = '1' and AtomIOWR1 = '0') then
AtomToAVR <= DataIn;
end if;
end process;
-- Latch AVR to Atom on AVR write
AVRToAtomProcess : process (clk)
begin
if rising_edge(clk) and nAWR = '0' and nAWR1 = '1' then
AVRToAtom <= AVRDataIn;
end if;
end process;
-- Handshake lines.
-- AtomW_AVRR set by a write from the Atom, cleared by a read by the AVR.
-- Cleared on reset.
AtomW_AVRRProcess : process (nRST, clk)
begin
if nRST = '0' then
AtomW_AVRR <= '0';
elsif rising_edge(clk) then
if (AtomIOWR = '1' and AtomIOWR1 = '0') then
AtomW_AVRR <= '1';
elsif (nAVRRDData = '1' and nAVRRDData1 = '0') then
AtomW_AVRR <= '0';
end if;
end if;
end process;
-- AVRW_AtomR set by a write from the AVR, cleared by a read by the Atom.
-- Cleared on reset.
AVRW_AtomRLatch : process (nRST, clk)
begin
if nRST = '0' then
AVRW_AtomR <= '0';
elsif rising_edge(clk) then
if (AtomIORD = '1' and AtomIORD1 = '0') then
AVRW_AtomR <= '0';
elsif (nAWR = '1' and nAWR1 = '0') then
AVRW_AtomR <= '1';
end if;
end if;
end process;
-- AVRBusy set by Atom write to command register, reset by AVR write, as all
-- commands should return at least one byte (status or data)
-- We use posedge nAVRW, so that busy is not reset until the data has been written
-- by the AVR, and is ready to be read by the Atom.
AVRBusyProcess : process (nRST, clk)
begin
if nRST = '0' then
AVRBusy <= '0';
elsif rising_edge(clk) then
if (AtomCMDWR = '1' and AtomCMDWR1 = '0') then
AVRBusy <= '1';
elsif (nAWR = '1' and nAWR1 = '0') then
AVRBusy <= '0';
end if;
end if;
end process;
end Behavioral;
| apache-2.0 | 4cbdbba5993df2a4774aacd62660bcb4 | 0.529983 | 3.462517 | false | false | false | false |
bertuccio/ARQ | Practica5/ForwardingUnit.vhd | 2 | 1,382 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ForwardingUnit is
Port ( EX_MEM_ESCREG : in STD_LOGIC;
MEM_WB_ESCREG : in STD_LOGIC;
AnticipaA : out STD_LOGIC_VECTOR (1 downto 0);
AnticipaB : out STD_LOGIC_VECTOR (1 downto 0);
ID_EX_RS : in STD_LOGIC_VECTOR (4 downto 0);
ID_EX_RT : in STD_LOGIC_VECTOR (4 downto 0);
EX_MEM_RD : in STD_LOGIC_VECTOR (4 downto 0);
MEM_WB_RD : in STD_LOGIC_VECTOR (4 downto 0));
end ForwardingUnit;
architecture Behavioral of ForwardingUnit is
begin
process (EX_MEM_ESCREG,EX_MEM_RD,ID_EX_RS,MEM_WB_ESCREG,MEM_WB_RD)
begin
if EX_MEM_ESCREG='1' and EX_MEM_RD/="00000" and EX_MEM_RD=ID_EX_RS then
AnticipaA<="10";
elsif MEM_WB_ESCREG='1' and MEM_WB_RD/="00000" and EX_MEM_RD/=ID_EX_RS and MEM_WB_RD=ID_EX_RS then
AnticipaA<="01";
else
AnticipaA<="00";
end if;
end process;
process (EX_MEM_ESCREG,EX_MEM_RD,ID_EX_RT,MEM_WB_ESCREG,MEM_WB_RD)
begin
if EX_MEM_ESCREG='1' and EX_MEM_RD/="00000" and EX_MEM_RD=ID_EX_RT then
AnticipaB<="10";
elsif MEM_WB_ESCREG='1' and MEM_WB_RD/="00000" and EX_MEM_RD/=ID_EX_RT and MEM_WB_RD=ID_EX_RT then
AnticipaB<="01";
else
AnticipaB<="00";
end if;
end process;
end Behavioral;
| mit | 3b224572d6ef2707cd2ad949520e202f | 0.62301 | 2.642447 | false | false | false | false |
hoglet67/AtomFpga | src/common/T6502/T65_MCode.vhd | 1 | 44,547 | -- ****
-- T65(b) core. In an effort to merge and maintain bug fixes ....
--
-- See list of changes in T65 top file (T65.vhd)...
--
-- ****
-- 65xx compatible microprocessor core
--
-- FPGAARCADE SVN: $Id: T65_MCode.vhd 1234 2015-02-28 20:14:50Z wolfgang.scherr $
--
-- Copyright (c) 2002...2015
-- Daniel Wallner (jesus <at> opencores <dot> org)
-- Mike Johnson (mikej <at> fpgaarcade <dot> com)
-- Wolfgang Scherr (WoS <at> pin4 <dot> at>
-- Morten Leikvoll ()
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author(s), but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- Limitations :
-- See in T65 top file (T65.vhd)...
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use ieee.std_logic_unsigned.all;
use work.T65_Pack.all;
entity T65_MCode is
port(
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816
IR : in std_logic_vector(7 downto 0);
MCycle : in T_Lcycle;
P : in std_logic_vector(7 downto 0);
LCycle : out T_Lcycle;
ALU_Op : out T_ALU_Op;
Set_BusA_To : out T_Set_BusA_To; -- DI,A,X,Y,S,P,DA,DAO,DAX,AAX
Set_Addr_To : out T_Set_Addr_To; -- PC Adder,S,AD,BA
Write_Data : out T_Write_Data; -- DL,A,X,Y,S,P,PCL,PCH,AX,AXB,XB,YB
Jump : out std_logic_vector(1 downto 0); -- PC,++,DIDL,Rel
BAAdd : out std_logic_vector(1 downto 0); -- None,DB Inc,BA Add,BA Adj
BreakAtNA : out std_logic;
ADAdd : out std_logic;
AddY : out std_logic;
PCAdd : out std_logic;
Inc_S : out std_logic;
Dec_S : out std_logic;
LDA : out std_logic;
LDP : out std_logic;
LDX : out std_logic;
LDY : out std_logic;
LDS : out std_logic;
LDDI : out std_logic;
LDALU : out std_logic;
LDAD : out std_logic;
LDBAL : out std_logic;
LDBAH : out std_logic;
SaveP : out std_logic;
Write : out std_logic
);
end T65_MCode;
architecture rtl of T65_MCode is
signal Branch : std_logic;
signal ALUmore:std_logic;
begin
with IR(7 downto 5) select
Branch <= not P(Flag_N) when "000",
P(Flag_N) when "001",
not P(Flag_V) when "010",
P(Flag_V) when "011",
not P(Flag_C) when "100",
P(Flag_C) when "101",
not P(Flag_Z) when "110",
P(Flag_Z) when others;
process (IR, MCycle, P, Branch, Mode)
begin
lCycle <= Cycle_1;
Set_BusA_To <= Set_BusA_To_ABC;
Set_Addr_To <= Set_Addr_To_PBR;
Write_Data <= Write_Data_DL;
Jump <= (others => '0');
BAAdd <= "00";
BreakAtNA <= '0';
ADAdd <= '0';
PCAdd <= '0';
Inc_S <= '0';
Dec_S <= '0';
LDA <= '0';
LDP <= '0';
LDX <= '0';
LDY <= '0';
LDS <= '0';
LDDI <= '0';
LDALU <= '0';
LDAD <= '0';
LDBAL <= '0';
LDBAH <= '0';
SaveP <= '0';
Write <= '0';
AddY <= '0';
ALUmore <= '0';
case IR(7 downto 5) is
when "100" => -- covers $8x,$9x
case IR(1 downto 0) is
when "00" => -- IR: $80,$84,$88,$8C,$90,$94,$98,$9C
Set_BusA_To <= Set_BusA_To_Y;
if IR(4 downto 2)="111" then -- SYA ($9C)
Write_Data <= Write_Data_YB;
else
Write_Data <= Write_Data_Y;
end if;
when "10" => -- IR: $82,$86,$8A,$8E,$92,$96,$9A,$9E
Set_BusA_To <= Set_BusA_To_X;
if IR(4 downto 2)="111" then -- SXA ($9E)
Write_Data <= Write_Data_XB;
else
Write_Data <= Write_Data_X;
end if;
when "11" => -- IR: $83,$87,$8B,$8F,$93,$97,$9B,$9F
if IR(4 downto 2)="110" then -- SHS ($9B)
Set_BusA_To <= Set_BusA_To_AAX;
LDS <= '1';
else
Set_BusA_To <= Set_BusA_To_ABC;
end if;
if IR(4 downto 2)="111" or IR(4 downto 2)="110" or IR(4 downto 2)="100" then -- SHA ($9F, $93), SHS ($9B)
Write_Data <= Write_Data_AXB;
else
Write_Data <= Write_Data_AX;
end if;
when others => -- IR: $81,$85,$89,$8D,$91,$95,$99,$9D
Write_Data <= Write_Data_ABC;
end case;
when "101" => -- covers $Ax,$Bx
Set_BusA_To <= Set_BusA_To_DI;
case IR(1 downto 0) is
when "00" => -- IR: $A0,$A4,$A8,$AC,$B0,$B4,$B8,$BC
if IR(4) /= '1' or IR(2) /= '0' then--only for $A0,$A4,$A8,$AC or $B4,$BC
LDY <= '1';
end if;
when "01" => -- IR: $A1,$A5,$A9,$AD,$B1,$B5,$B9,$BD
LDA <= '1';
when "10" => -- IR: $A2,$A6,$AA,$AE,$B2,$B6,$BA,$BE
LDX <= '1';
when others => -- IR: $A3,$A7,$AB,$AF,$B3,$B7,$BB,$BF (undoc)
LDX <= '1';
LDA <= '1';
if IR(4 downto 2)="110" then -- LAS (BB)
Set_BusA_To <= Set_BusA_To_S;
LDS <= '1';
end if;
end case;
when "110" => -- covers $Cx,$Dx
case IR(1 downto 0) is
when "00" => -- IR: $C0,$C4,$C8,$CC,$D0,$D4,$D8,$DC
if IR(4) = '0' then--only for $Cx
LDY <= '1';
end if;
Set_BusA_To <= Set_BusA_To_Y;
when others => -- IR: $C1,$C5,$C9,$CD,$D1,$D5,$D9,$DD, $C2,$C6,$CA,$CE,$D2,$D6,$DA,$DE, $C3,$C7,$CB,$CF,$D3,$D7,$DB,$DF
Set_BusA_To <= Set_BusA_To_ABC;
end case;
when "111" => -- covers $Ex,$Fx
case IR(1 downto 0) is
when "00" => -- IR: $E0,$E4,$E8,$EC,$F0,$F4,$F8,$FC
if IR(4) = '0' then -- only $Ex
LDX <= '1';
end if;
Set_BusA_To <= Set_BusA_To_X;
when others => -- IR: $E1,$E5,$E9,$ED,$F1,$F5,$F9,$FD, $E2,$E6,$EA,$EE,$F2,$F6,$FA,$FE, $E3,$E7,$EB,$EF,$F3,$F7,$FB,$FF
Set_BusA_To <= Set_BusA_To_ABC;
end case;
when others =>
end case;
if IR(7 downto 6) /= "10" and IR(1) = '1' and (mode="00" or IR(0)='0') then--covers $0x-$7x, $Cx-$Fx x=2,3,6,7,A,B,E,F, for 6502 undocs
if IR=x"eb" then
Set_BusA_To <= Set_BusA_To_ABC; -- alternate SBC ($EB)
else
Set_BusA_To <= Set_BusA_To_DI;
end if;
end if;
case IR(4 downto 0) is
-- IR: $00,$20,$40,$60,$80,$A0,$C0,$E0
-- $08,$28,$48,$68,$88,$A8,$C8,$E8
-- $0A,$2A,$4A,$6A,$8A,$AA,$CA,$EA
-- $18,$38,$58,$78,$98,$B8,$D8,$F8
-- $1A,$3A,$5A,$7A,$9A,$BA,$DA,$FA
when "00000" | "01000" | "01010" | "11000" | "11010" =>
-- Implied
case IR is
when x"00" =>
-- BRK ($00)
lCycle <= Cycle_6;
case MCycle is
when Cycle_1 =>
Set_Addr_To <= Set_Addr_To_SP;
Write_Data <= Write_Data_PCH;
Write <= '1';
when Cycle_2 =>
Dec_S <= '1';
Set_Addr_To <= Set_Addr_To_SP;
Write_Data <= Write_Data_PCL;
Write <= '1';
when Cycle_3 =>
Dec_S <= '1';
Set_Addr_To <= Set_Addr_To_SP;
Write_Data <= Write_Data_P;
Write <= '1';
when Cycle_4 =>
Dec_S <= '1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_5 =>
LDDI <= '1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_6 =>
Jump <= "10";
when others =>
end case;
when x"20" => -- JSR ($20)
lCycle <= Cycle_5;
case MCycle is
when Cycle_1 =>
Jump <= "01";
LDDI <= '1';
Set_Addr_To <= Set_Addr_To_SP;
when Cycle_2 =>
Set_Addr_To <= Set_Addr_To_SP;
Write_Data <= Write_Data_PCH;
Write <= '1';
when Cycle_3 =>
Dec_S <= '1';
Set_Addr_To <= Set_Addr_To_SP;
Write_Data <= Write_Data_PCL;
Write <= '1';
when Cycle_4 =>
Dec_S <= '1';
when Cycle_5 =>
Jump <= "10";
when others =>
end case;
when x"40" => -- RTI ($40)
lCycle <= Cycle_5;
case MCycle is
when Cycle_1 =>
Set_Addr_To <= Set_Addr_To_SP;
when Cycle_2 =>
Inc_S <= '1';
Set_Addr_To <= Set_Addr_To_SP;
when Cycle_3 =>
Inc_S <= '1';
Set_Addr_To <= Set_Addr_To_SP;
Set_BusA_To <= Set_BusA_To_DI;
when Cycle_4 =>
LDP <= '1';
Inc_S <= '1';
LDDI <= '1';
Set_Addr_To <= Set_Addr_To_SP;
when Cycle_5 =>
Jump <= "10";
when others =>
end case;
when x"60" => -- RTS ($60)
lCycle <= Cycle_5;
case MCycle is
when Cycle_1 =>
Set_Addr_To <= Set_Addr_To_SP;
when Cycle_2 =>
Inc_S <= '1';
Set_Addr_To <= Set_Addr_To_SP;
when Cycle_3 =>
Inc_S <= '1';
LDDI <= '1';
Set_Addr_To <= Set_Addr_To_SP;
when Cycle_4 =>
Jump <= "10";
when Cycle_5 =>
Jump <= "01";
when others =>
end case;
when x"08" | x"48" | x"5a" | x"da" => -- PHP, PHA, PHY*, PHX* ($08,$48,$5A,$DA)
lCycle <= Cycle_2;
if Mode = "00" and IR(1) = '1' then--2 cycle nop
lCycle <= Cycle_1;
end if;
case MCycle is
when Cycle_1 =>
if mode/="00" or IR(1)='0' then --wrong on 6502
Write <= '1';
case IR(7 downto 4) is
when "0000" =>
Write_Data <= Write_Data_P;
when "0100" =>
Write_Data <= Write_Data_ABC;
when "0101" =>
if Mode /= "00" then
Write_Data <= Write_Data_Y;
else
Write <= '0';
end if;
when "1101" =>
if Mode /= "00" then
Write_Data <= Write_Data_X;
else
Write <= '0';
end if;
when others =>
end case;
Set_Addr_To <= Set_Addr_To_SP;
end if;
when Cycle_2 =>
Dec_S <= '1';
when others =>
end case;
when x"28" | x"68" | x"7a" | x"fa" => -- PLP, PLA, PLY*, PLX* ($28,$68,$7A,$FA)
lCycle <= Cycle_3;
if Mode = "00" and IR(1) = '1' then--2 cycle nop
lCycle <= Cycle_1;
end if;
case IR(7 downto 4) is
when "0010" =>--plp
LDP <= '1';
when "0110" =>--pla
LDA <= '1';
when "0111" =>--ply not for 6502
if Mode /= "00" then
LDY <= '1';
end if;
when "1111" =>--plx not for 6502
if Mode /= "00" then
LDX <= '1';
end if;
when others =>
end case;
case MCycle is
when Cycle_sync =>
if Mode /= "00" or IR(1) = '0' then--wrong on 6502
SaveP <= '1';
end if;
when Cycle_1 =>
if Mode /= "00" or IR(1) = '0' then--wrong on 6502
Set_Addr_To <= Set_Addr_To_SP;
LDP <= '0';
end if;
when Cycle_2 =>
Inc_S <= '1';
Set_Addr_To <= Set_Addr_To_SP;
LDP <= '0';
when Cycle_3 =>
Set_BusA_To <= Set_BusA_To_DI;
when others =>
end case;
when x"a0" | x"c0" | x"e0" => -- LDY, CPY, CPX ($A0,$C0,$E0)
-- Immediate
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Jump <= "01";
when others =>
end case;
when x"88" => -- DEY ($88)
LDY <= '1';
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Set_BusA_To <= Set_BusA_To_Y;
when others =>
end case;
when x"ca" => -- DEX ($CA)
LDX <= '1';
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Set_BusA_To <= Set_BusA_To_X;
when others =>
end case;
when x"1a" | x"3a" => -- INC*, DEC* ($1A,$3A)
if Mode /= "00" then
LDA <= '1'; -- A
else
lCycle <= Cycle_1;--undoc 2 cycle nop
end if;
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Set_BusA_To <= Set_BusA_To_S;
when others =>
end case;
when x"0a" | x"2a" | x"4a" | x"6a" => -- ASL, ROL, LSR, ROR ($0A,$2A,$4A,$6A)
LDA <= '1'; -- A
Set_BusA_To <= Set_BusA_To_ABC;
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
when others =>
end case;
when x"8a" | x"98" => -- TYA, TXA ($8A,$98)
LDA <= '1';
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
when others =>
end case;
when x"aa" | x"a8" => -- TAX, TAY ($AA,$A8)
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Set_BusA_To <= Set_BusA_To_ABC;
when others =>
end case;
when x"9a" => -- TXS ($9A)
LDS <= '1'; -- will be set only in Cycle_sync
when x"ba" => -- TSX ($BA)
LDX <= '1';
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Set_BusA_To <= Set_BusA_To_S;
when others =>
end case;
when x"80" => -- undoc: NOP imm2 ($80)
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Jump <= "01";
when others =>
end case;
when others => -- others ($0A,$EA, $18,$38,$58,$78,$B8,$C8,$D8,$E8,$F8)
case MCycle is
when Cycle_sync =>
when others =>
end case;
end case;
-- IR: $01,$21,$41,$61,$81,$A1,$C1,$E1
-- $03,$23,$43,$63,$83,$A3,$C3,$E3
when "00001" | "00011" =>
-- Zero Page Indexed Indirect (d,x)
lCycle <= Cycle_5;
if IR(7 downto 6) /= "10" then -- ($01,$21,$41,$61,$C1,$E1,$03,$23,$43,$63,$C3,$E3)
LDA <= '1';
if Mode="00" and IR(1)='1' then
lCycle <= Cycle_7;
end if;
end if;
case MCycle is
when Cycle_1 =>
Jump <= "01";
LDAD <= '1';
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_2 =>
ADAdd <= '1';
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_3 =>
BAAdd <= "01";
LDBAL <= '1';
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_4 =>
LDBAH <= '1';
if IR(7 downto 5) = "100" then
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_5=>
if Mode="00" and IR(1)='1' and IR(7 downto 6)/="10" then
Set_Addr_To <= Set_Addr_To_BA;
Write <= '1';
LDDI<='1';
end if;
when Cycle_6=>
Write <= '1';
LDALU<='1';
SaveP<='1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_7 =>
ALUmore <= '1';
Set_BusA_To <= Set_BusA_To_ABC;
when others =>
end case;
-- IR: $09,$29,$49,$69,$89,$A9,$C9,$E9
when "01001" =>
-- Immediate
if IR(7 downto 5)/="100" then -- all except undoc. NOP imm2 (not $89)
LDA <= '1';
end if;
case MCycle is
when Cycle_1 =>
Jump <= "01";
when others =>
end case;
-- IR: $0B,$2B,$4B,$6B,$8B,$AB,$CB,$EB
when "01011" =>
if Mode="00" then
-- Immediate undoc for 6500
case IR(7 downto 5) is
when "010"|"011"|"000"|"001" =>--ALR,ARR
Set_BusA_To<=Set_BusA_To_DA;
LDA <= '1';
when "100" =>--XAA
Set_BusA_To<=Set_BusA_To_DAX;
LDA <= '1';
when "110" =>--SAX (SBX)
Set_BusA_To<=Set_BusA_To_AAX;
LDX <= '1';
when "101" =>--OAL
Set_BusA_To<=Set_BusA_To_DAO;
LDA <= '1';
when others=>
LDA <= '1';
end case;
case MCycle is
when Cycle_1 =>
Jump <= "01";
when others =>
end case;
end if;
-- IR: $02,$22,$42,$62,$82,$A2,$C2,$E2
-- $12,$32,$52,$72,$92,$B2,$D2,$F2
when "00010" | "10010" =>
-- Immediate, SKB, KIL
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
if IR = "10100010" then
-- LDX ($A2)
Jump <= "01";
LDX <= '1'; -- Moved, Lorenz test showed X changing on SKB (NOPx)
elsif IR(7 downto 4)="1000" or IR(7 downto 4)="1100" or IR(7 downto 4)="1110" then
-- undoc: NOP imm2
Jump <= "01";
else
-- KIL !!!
end if;
when others =>
end case;
-- IR: $04,$24,$44,$64,$84,$A4,$C4,$E4
when "00100" =>
-- Zero Page
lCycle <= Cycle_2;
case MCycle is
when Cycle_sync =>
if IR(7 downto 5) = "001" then--24=BIT zpg
SaveP <= '1';
end if;
when Cycle_1 =>
Jump <= "01";
LDAD <= '1';
if IR(7 downto 5) = "100" then--84=sty zpg (the only write in this group)
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_2 =>
when others =>
end case;
-- IR: $05,$25,$45,$65,$85,$A5,$C5,$E5
-- $06,$26,$46,$66,$86,$A6,$C6,$E6
-- $07,$27,$47,$67,$87,$A7,$C7,$E7
when "00101" | "00110" | "00111" =>
-- Zero Page
if IR(7 downto 6) /= "10" and IR(1) = '1' and (mode="00" or IR(0)='0') then--covers 0x-7x,cx-fx x=2,3,6,7,a,b,e,f, for 6502 undocs
-- Read-Modify-Write
lCycle <= Cycle_4;
if Mode="00" and IR(0)='1' then
LDA<='1';
end if;
case MCycle is
when Cycle_1 =>
Jump <= "01";
LDAD <= '1';
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_2 =>
LDDI <= '1';
if Mode="00" then--The old 6500 writes back what is just read, before changing. The 65c does another read
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_3 =>
LDALU <= '1';
SaveP <= '1';
Write <= '1';
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_4 =>
if Mode="00" and IR(0)='1' then
Set_BusA_To<=Set_BusA_To_ABC;
ALUmore <= '1'; -- For undoc DCP/DCM support
LDDI <= '1'; -- requires DIN to reflect DOUT!
end if;
when others =>
end case;
else
lCycle <= Cycle_2;
if IR(7 downto 6) /= "10" then
LDA <= '1';
end if;
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Jump <= "01";
LDAD <= '1';
if IR(7 downto 5) = "100" then
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_2 =>
when others =>
end case;
end if;
-- IR: $0C,$2C,$4C,$6C,$8C,$AC,$CC,$EC
when "01100" =>
-- Absolute
if IR(7 downto 6) = "01" and IR(4 downto 0) = "01100" then -- JMP ($4C,$6C)
if IR(5) = '0' then
lCycle <= Cycle_2;
case MCycle is
when Cycle_1 =>
Jump <= "01";
LDDI <= '1';
when Cycle_2 =>
Jump <= "10";
when others =>
end case;
else
lCycle <= Cycle_4;
case MCycle is
when Cycle_1 =>
Jump <= "01";
LDDI <= '1';
LDBAL <= '1';
when Cycle_2 =>
LDBAH <= '1';
if Mode /= "00" then
Jump <= "10";
end if;
if Mode = "00" then
Set_Addr_To <= Set_Addr_To_BA;
end if;
when Cycle_3 =>
LDDI <= '1';
if Mode = "00" then
Set_Addr_To <= Set_Addr_To_BA;
BAAdd <= "01"; -- DB Inc
else
Jump <= "01";
end if;
when Cycle_4 =>
Jump <= "10";
when others =>
end case;
end if;
else
lCycle <= Cycle_3;
case MCycle is
when Cycle_sync =>
if IR(7 downto 5) = "001" then--2c-BIT
SaveP <= '1';
end if;
when Cycle_1 =>
Jump <= "01";
LDBAL <= '1';
when Cycle_2 =>
Jump <= "01";
LDBAH <= '1';
if IR(7 downto 5) = "100" then--80, sty, the only write in this group
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_3 =>
when others =>
end case;
end if;
-- IR: $0D,$2D,$4D,$6D,$8D,$AD,$CD,$ED
-- $0E,$2E,$4E,$6E,$8E,$AE,$CE,$EE
-- $0F,$2F,$4F,$6F,$8F,$AF,$CF,$EF
when "01101" | "01110" | "01111" =>
-- Absolute
if IR(7 downto 6) /= "10" and IR(1) = '1' and (mode="00" or IR(0)='0') then -- ($0E,$2E,$4E,$6E,$CE,$EE, $0F,$2F,$4F,$6F,$CF,$EF)
-- Read-Modify-Write
lCycle <= Cycle_5;
if Mode="00" and IR(0) = '1' then
LDA <= '1';
end if;
case MCycle is
when Cycle_1 =>
Jump <= "01";
LDBAL <= '1';
when Cycle_2 =>
Jump <= "01";
LDBAH <= '1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_3 =>
LDDI <= '1';
if Mode="00" then--The old 6500 writes back what is just read, before changing. The 65c does another read
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_4 =>
Write <= '1';
LDALU <= '1';
SaveP <= '1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_5 =>
if Mode="00" and IR(0)='1' then
ALUmore <= '1'; -- For undoc DCP/DCM support
Set_BusA_To<=Set_BusA_To_ABC;
end if;
when others =>
end case;
else
lCycle <= Cycle_3;
if IR(7 downto 6) /= "10" then -- all but $8D, $8E, $8F, $AD, $AE, $AF ($AD does set LDA in an earlier case statement)
LDA <= '1';
end if;
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Jump <= "01";
LDBAL <= '1';
when Cycle_2 =>
Jump <= "01";
LDBAH <= '1';
if IR(7 downto 5) = "100" then--8d
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_3 =>
when others =>
end case;
end if;
-- IR: $10,$30,$50,$70,$90,$B0,$D0,$F0
when "10000" =>
-- Relative
-- This circuit dictates when the last
-- microcycle occurs for the branch depending on
-- whether or not the branch is taken and if a page
-- is crossed...
if (Branch = '1') then
lCycle <= Cycle_3; -- We're done @ T3 if branching...upper
-- level logic will stop at T2 if no page cross
-- (See the Break signal)
else
lCycle <= Cycle_1;
end if;
-- This decodes the current microcycle and takes the
-- proper course of action...
case MCycle is
-- On the T1 microcycle, increment the program counter
-- and instruct the upper level logic to fetch the offset
-- from the Din bus and store it in the data latches. This
-- will be the last microcycle if the branch isn't taken.
when Cycle_1 =>
Jump <= "01"; -- Increments the PC by one (PC will now be PC+2)
-- from microcycle T0.
LDDI <= '1'; -- Tells logic in top level (T65.vhd) to route
-- the Din bus to the memory data latch (DL)
-- so that the branch offset is fetched.
-- In microcycle T2, tell the logic in the top level to
-- add the offset. If the most significant byte of the
-- program counter (i.e. the current "page") does not need
-- updating, we are done here...the Break signal at the
-- T65.vhd level takes care of that...
when Cycle_2 =>
Jump <= "11"; -- Tell the PC Jump logic to use relative mode.
PCAdd <= '1'; -- This tells the PC adder to update itself with
-- the current offset recently fetched from
-- memory.
-- The following is microcycle T3 :
-- The program counter should be completely updated
-- on this cycle after the page cross is detected.
-- We don't need to do anything here...
when Cycle_3 =>
when others => null; -- Do nothing.
end case;
-- IR: $11,$31,$51,$71,$91,$B1,$D1,$F1
-- $13,$33,$53,$73,$93,$B3,$D3,$F3
when "10001" | "10011" =>
lCycle <= Cycle_5;
if IR(7 downto 6) /= "10" then -- ($11,$31,$51,$71,$D1,$F1,$13,$33,$53,$73,$D3,$F3)
LDA <= '1';
if Mode="00" and IR(1)='1' then
lCycle <= Cycle_7;
end if;
end if;
case MCycle is
when Cycle_1 =>
Jump <= "01";
LDAD <= '1';
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_2 =>
LDBAL <= '1';
BAAdd <= "01"; -- DB Inc
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_3 =>
Set_BusA_To <= Set_BusA_To_Y;
BAAdd <= "10"; -- BA Add
LDBAH <= '1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_4 =>
BAAdd <= "11"; -- BA Adj
if IR(7 downto 5) = "100" then
Write <= '1';
elsif IR(1)='0' or IR=x"B3" then -- Dont do this on $x3, except undoc LAXiy $B3 (says real CPU and Lorenz tests)
BreakAtNA <= '1';
end if;
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_5 =>
if Mode="00" and IR(1)='1' and IR(7 downto 6)/="10" then
Set_Addr_To <= Set_Addr_To_BA;
LDDI<='1';
Write <= '1';
end if;
when Cycle_6 =>
LDALU<='1';
SaveP<='1';
Write <= '1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_7 =>
ALUmore <= '1';
Set_BusA_To<=Set_BusA_To_ABC;
when others =>
end case;
-- IR: $14,$34,$54,$74,$94,$B4,$D4,$F4
-- $15,$35,$55,$75,$95,$B5,$D5,$F5
-- $16,$36,$56,$76,$96,$B6,$D6,$F6
-- $17,$37,$57,$77,$97,$B7,$D7,$F7
when "10100" | "10101" | "10110" | "10111" =>
-- Zero Page, X
if IR(7 downto 6) /= "10" and IR(1) = '1' and (Mode="00" or IR(0)='0') then -- ($16,$36,$56,$76,$D6,$F6, $17,$37,$57,$77,$D7,$F7)
-- Read-Modify-Write
if Mode="00" and IR(0)='1' then
LDA<='1';
end if;
lCycle <= Cycle_5;
case MCycle is
when Cycle_1 =>
Jump <= "01";
LDAD <= '1';
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_2 =>
ADAdd <= '1';
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_3 =>
LDDI <= '1';
if Mode="00" then -- The old 6500 writes back what is just read, before changing. The 65c does another read
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_4 =>
LDALU <= '1';
SaveP <= '1';
Write <= '1';
Set_Addr_To <= Set_Addr_To_ZPG;
if Mode="00" and IR(0)='1' then
LDDI<='1';
end if;
when Cycle_5 =>
if Mode="00" and IR(0)='1' then
ALUmore <= '1'; -- For undoc DCP/DCM support
Set_BusA_To<=Set_BusA_To_ABC;
end if;
when others =>
end case;
else
lCycle <= Cycle_3;
if IR(7 downto 6) /= "10" and IR(0)='1' then -- dont LDA on undoc skip
LDA <= '1';
end if;
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Jump <= "01";
LDAD <= '1';
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_2 =>
ADAdd <= '1';
-- Added this check for Y reg. use, added undocs
if (IR(3 downto 1) = "011") then -- ($16,$36,$56,$76,$96,$B6,$D6,$F6,$17,$37,$57,$77,$97,$B7,$D7,$F7)
AddY <= '1';
end if;
if IR(7 downto 5) = "100" then -- ($14,$34,$15,$35,$16,$36,$17,$37) the only write instruction
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_3 => null;
when others =>
end case;
end if;
-- IR: $19,$39,$59,$79,$99,$B9,$D9,$F9
-- $1B,$3B,$5B,$7B,$9B,$BB,$DB,$FB
when "11001" | "11011" =>
-- Absolute Y
lCycle <= Cycle_4;
if IR(7 downto 6) /= "10" then
LDA <= '1';
if Mode="00" and IR(1)='1' then
lCycle <= Cycle_6;
end if;
end if;
case MCycle is
when Cycle_1 =>
Jump <= "01";
LDBAL <= '1';
when Cycle_2 =>
Jump <= "01";
Set_BusA_To <= Set_BusA_To_Y;
BAAdd <= "10"; -- BA Add
LDBAH <= '1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_3 =>
BAAdd <= "11"; -- BA adj
if IR(7 downto 5) = "100" then--99/9b
Write <= '1';
elsif IR(1)='0' or IR=x"BB" then -- Dont do this on $xB, except undoc $BB (says real CPU and Lorenz tests)
BreakAtNA <= '1';
end if;
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_4 => -- just for undoc
if Mode="00" and IR(1)='1' and IR(7 downto 6)/="10" then
Set_Addr_To <= Set_Addr_To_BA;
LDDI<='1';
Write <= '1';
end if;
when Cycle_5 =>
Write <= '1';
LDALU<='1';
Set_Addr_To <= Set_Addr_To_BA;
SaveP<='1';
when Cycle_6 =>
ALUmore <= '1';
Set_BusA_To <= Set_BusA_To_ABC;
when others =>
end case;
-- IR: $1C,$3C,$5C,$7C,$9C,$BC,$DC,$FC
-- $1D,$3D,$5D,$7D,$9D,$BD,$DD,$FD
-- $1E,$3E,$5E,$7E,$9E,$BE,$DE,$FE
-- $1F,$3F,$5F,$7F,$9F,$BF,$DF,$FF
when "11100" | "11101" | "11110" | "11111" =>
-- Absolute X
if IR(7 downto 6) /= "10" and IR(1) = '1' and (Mode="00" or IR(0)='0') then -- ($1E,$3E,$5E,$7E,$DE,$FE, $1F,$3F,$5F,$7F,$DF,$FF)
-- Read-Modify-Write
lCycle <= Cycle_6;
if Mode="00" and IR(0)='1' then
LDA <= '1';
end if;
case MCycle is
when Cycle_1 =>
Jump <= "01";
LDBAL <= '1';
when Cycle_2 =>
Jump <= "01";
Set_BusA_To <= Set_BusA_To_X;
BAAdd <= "10"; -- BA Add
LDBAH <= '1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_3 =>
BAAdd <= "11"; -- BA adj
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_4 =>
LDDI <= '1';
if Mode="00" then--The old 6500 writes back what is just read, before changing. The 65c does another read
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_5 =>
LDALU <= '1';
SaveP <= '1';
Write <= '1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_6 =>
if Mode="00" and IR(0)='1' then
ALUmore <= '1';
Set_BusA_To <= Set_BusA_To_ABC;
end if;
when others =>
end case;
else -- ($1C,$3C,$5C,$7C,$9C,$BC,$DC,$FC, $1D,$3D,$5D,$7D,$9D,$BD,$DD,$FD, $9E,$BE,$9F,$BF)
lCycle <= Cycle_4;--Or 3 if not page crossing
if IR(7 downto 6) /= "10" then
if Mode/="00" or IR(4)='0' or IR(1 downto 0)/="00" then
LDA <= '1';
end if;
end if;
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Jump <= "01";
LDBAL <= '1';
when Cycle_2 =>
Jump <= "01";
-- special case $BE which uses Y reg as index!!
if(IR(7 downto 6)="10" and IR(4 downto 1)="1111") then
Set_BusA_To <= Set_BusA_To_Y;
else
Set_BusA_To <= Set_BusA_To_X;
end if;
BAAdd <= "10"; -- BA Add
LDBAH <= '1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_3 =>
BAAdd <= "11"; -- BA adj
if IR(7 downto 5) = "100" then -- ($9E,$9F)
Write <= '1';
else
BreakAtNA <= '1';
end if;
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_4 =>
when others =>
end case;
end if;
when others =>
end case;
end process;
process (IR, MCycle, Mode,ALUmore)
begin
-- ORA, AND, EOR, ADC, NOP, LD, CMP, SBC
-- ASL, ROL, LSR, ROR, BIT, LD, DEC, INC
case IR(1 downto 0) is
when "00" =>
case IR(4 downto 2) is
-- IR: $00,$20,$40,$60,$80,$A0,$C0,$E0
-- $04,$24,$44,$64,$84,$A4,$C4,$E4
-- $0C,$2C,$4C,$6C,$8C,$AC,$CC,$EC
when "000" | "001" | "011" =>
case IR(7 downto 5) is
when "110" | "111" => -- CP ($C0,$C4,$CC,$E0,$E4,$EC)
ALU_Op <= ALU_OP_CMP;
when "101" => -- LD ($A0,$A4,$AC)
ALU_Op <= ALU_OP_EQ2;
when "001" => -- BIT ($20,$24,$2C - $20 is ignored, as its a jmp)
ALU_Op <= ALU_OP_BIT;
when others => -- other, NOP/ST ($x0,$x4,$xC)
ALU_Op <= ALU_OP_EQ1;
end case;
-- IR: $08,$28,$48,$68,$88,$A8,$C8,$E8
when "010" =>
case IR(7 downto 5) is
when "111" | "110" => -- IN ($C8,$E8)
ALU_Op <= ALU_OP_INC;
when "100" => -- DEY ($88)
ALU_Op <= ALU_OP_DEC;
when others => -- LD
ALU_Op <= ALU_OP_EQ2;
end case;
-- IR: $18,$38,$58,$78,$98,$B8,$D8,$F8
when "110" =>
case IR(7 downto 5) is
when "100" => -- TYA ($98)
ALU_Op <= ALU_OP_EQ2;
when others =>
ALU_Op <= ALU_OP_EQ1;
end case;
-- IR: $10,$30,$50,$70,$90,$B0,$D0,$F0
-- $14,$34,$54,$74,$94,$B4,$D4,$F4
-- $1C,$3C,$5C,$7C,$9C,$BC,$DC,$FC
when others =>
case IR(7 downto 5) is
when "101" => -- LD ($B0,$B4,$BC)
ALU_Op <= ALU_OP_EQ2;
when others =>
ALU_Op <= ALU_OP_EQ1;
end case;
end case;
when "01" => -- OR
case(to_integer(unsigned(IR(7 downto 5)))) is
when 0=> -- IR: $01,$05,$09,$0D,$11,$15,$19,$1D
ALU_Op<=ALU_OP_OR;
when 1=> -- IR: $21,$25,$29,$2D,$31,$35,$39,$3D
ALU_Op<=ALU_OP_AND;
when 2=> -- IR: $41,$45,$49,$4D,$51,$55,$59,$5D
ALU_Op<=ALU_OP_EOR;
when 3=> -- IR: $61,$65,$69,$6D,$71,$75,$79,$7D
ALU_Op<=ALU_OP_ADC;
when 4=>-- IR: $81,$85,$89,$8D,$91,$95,$99,$9D
ALU_Op<=ALU_OP_EQ1; -- STA
when 5=> -- IR: $A1,$A5,$A9,$AD,$B1,$B5,$B9,$BD
ALU_Op<=ALU_OP_EQ2; -- LDA
when 6=> -- IR: $C1,$C5,$C9,$CD,$D1,$D5,$D9,$DD
ALU_Op<=ALU_OP_CMP;
when others=> -- IR: $E1,$E5,$E9,$ED,$F1,$F5,$F9,$FD
ALU_Op<=ALU_OP_SBC;
end case;
when "10" =>
case(to_integer(unsigned(IR(7 downto 5)))) is
when 0=> -- IR: $02,$06,$0A,$0E,$12,$16,$1A,$1E
ALU_Op<=ALU_OP_ASL;
if IR(4 downto 2) = "110" and Mode/="00" then -- 00011010,$1A -> INC acc, not on 6502
ALU_Op <= ALU_OP_INC;
end if;
when 1=> -- IR: $22,$26,$2A,$2E,$32,$36,$3A,$3E
ALU_Op<=ALU_OP_ROL;
if IR(4 downto 2) = "110" and Mode/="00" then -- 00111010,$3A -> DEC acc, not on 6502
ALU_Op <= ALU_OP_DEC;
end if;
when 2=> -- IR: $42,$46,$4A,$4E,$52,$56,$5A,$5E
ALU_Op<=ALU_OP_LSR;
when 3=> -- IR: $62,$66,$6A,$6E,$72,$76,$7A,$7E
ALU_Op<=ALU_OP_ROR;
when 4=> -- IR: $82,$86,$8A,$8E,$92,$96,$9A,$9E
ALU_Op<=ALU_OP_BIT;
if IR(4 downto 2) = "010" then -- 10001010, $8A -> TXA
ALU_Op <= ALU_OP_EQ2;
else -- 100xxx10, $82,$86,$8E,$92,$96,$9A,$9E
ALU_Op <= ALU_OP_EQ1;
end if;
when 5=> -- IR: $A2,$A6,$AA,$AE,$B2,$B6,$BA,$BE
ALU_Op<=ALU_OP_EQ2; -- LDX
when 6=> -- IR: $C2,$C6,$CA,$CE,$D2,$D6,$DA,$DE
ALU_Op<=ALU_OP_DEC;
when others=> -- IR: $E2,$E6,$EA,$EE,$F2,$F6,$FA,$FE
ALU_Op<=ALU_OP_INC;
end case;
when others => -- "11" undoc double alu ops
case(to_integer(unsigned(IR(7 downto 5)))) is
-- IR: $A3,$A7,$AB,$AF,$B3,$B7,$BB,$BF
when 5 =>
if IR=x"bb" then--LAS
ALU_Op <= ALU_OP_AND;
else
ALU_Op <= ALU_OP_EQ2;
end if;
-- IR: $03,$07,$0B,$0F,$13,$17,$1B,$1F
-- $23,$27,$2B,$2F,$33,$37,$3B,$3F
-- $43,$47,$4B,$4F,$53,$57,$5B,$5F
-- $63,$67,$6B,$6F,$73,$77,$7B,$7F
-- $83,$87,$8B,$8F,$93,$97,$9B,$9F
-- $C3,$C7,$CB,$CF,$D3,$D7,$DB,$DF
-- $E3,$E7,$EB,$EF,$F3,$F7,$FB,$FF
when others =>
if IR=x"6b" then -- ARR
ALU_Op<=ALU_OP_ARR;
elsif IR=x"8b" then -- ARR
ALU_Op<=ALU_OP_XAA; -- we can't use the bit operation as we don't set all flags...
elsif IR=x"0b" or IR=x"2b" then -- ANC
ALU_Op<=ALU_OP_ANC;
elsif IR=x"eb" then -- alternate SBC
ALU_Op<=ALU_OP_SBC;
elsif ALUmore='1' then
case(to_integer(unsigned(IR(7 downto 5)))) is
when 0=>
ALU_Op<=ALU_OP_OR;
when 1=>
ALU_Op<=ALU_OP_AND;
when 2=>
ALU_Op<=ALU_OP_EOR;
when 3=>
ALU_Op<=ALU_OP_ADC;
when 4=>
ALU_Op<=ALU_OP_EQ1; -- STA
when 5=>
ALU_Op<=ALU_OP_EQ2; -- LDA
when 6=>
ALU_Op<=ALU_OP_CMP;
when others=>
ALU_Op<=ALU_OP_SBC;
end case;
else
case(to_integer(unsigned(IR(7 downto 5)))) is
when 0=>
ALU_Op<=ALU_OP_ASL;
when 1=>
ALU_Op<=ALU_OP_ROL;
when 2=>
ALU_Op<=ALU_OP_LSR;
when 3=>
ALU_Op<=ALU_OP_ROR;
when 4=>
ALU_Op<=ALU_OP_BIT;
when 5=>
ALU_Op<=ALU_OP_EQ2; -- LDX
when 6=>
ALU_Op<=ALU_OP_DEC;
if IR(4 downto 2)="010" then -- $6B
ALU_Op<=ALU_OP_SAX; -- special SAX (SBX) case
end if;
when others=>
ALU_Op<=ALU_OP_INC;
end case;
end if;
end case;
end case;
end process;
end;
| apache-2.0 | e99e7e9742a263c6f049f20481a09a86 | 0.40391 | 3.49005 | false | false | false | false |
GSimas/EEL5105 | Rep CAEE/11.2.Projeto/_PROJETO/multiplicador.vhd | 1 | 5,840 | -- ALUNOS:
-- Bruno Luiz da Silva
-- Gustavo Fernades
--
--
-- TÍTULO:
-- Multiplicador
--
--
-- RESUMO:
-- Conjunto de componentes os quais formam um multiplicador
--
--
-- ENTRADAS/SAÍDAS (I/O):
-- (I) a: entradas de 8 bits, sendo essas o multiplicando e o multiplicador.
-- (I) arguments: usado no input_control e assim ele controlará qual componente habilitar e quais desabilitar.
-- (I) clk, rst: clock e reset, sendo que o reset zera todas saídas.
-- (O) q: saída da multiplicação gerada (16 bits) onde constituirá a mantissa do projeto.
-- (O) exp_nor: saída da quantidade de deslocamentos que foram necessários para normalizar a saída gerada (mantissa).
--
--
-- DESCRIÇÃO:
-- O usuário entrará com os dados de 8 bits e para controlar para quais componentes esses dados irão, será utilizado o
-- input_control, sendo que os "arguments" serão enviados por uma FSM e habilitará os componentes corretos no momento
-- certo. Deve-se primeiramente carregar o registrador de 8 bits com esses dados (reg_8/ "001"), depois carregar a
-- parte baixa do registrador de 16 bits (reg16 / "010") e então iniciar a adição e/ou deslocamento.
--
-- Para tal o componente de soma deverá ser ativado, sendo que o mesmo argumento ativa o armazenamento de dados para a
-- parte alta registrador de 16 bits ("011"). Essa operação envia a saída da parte alta do registrador de 16 bits para
-- a entrada "b" do somador e na entrada "a" tem-se o valor do registrador de 8 bits. Ainda é enviado o último bit
-- presente no reg_16 pois caso ele for 0 os valores armazenados serão apenas deslocados a direita e caso for 1 então
-- soma-se as duas entradas e desloca-se os valores armazenados. Para realizar o deslocamento usa-se o argumento "100".
--
-- O processo de adição e deslocamento deve ser efetuado oito vezes. Quando esse processo terminar tem-se o valor da
-- multiplicação, porém para o projeto será necessário normalizar a mantissa. Para tal o primeiro bit do resultado
-- deve ser 1 e para isso é preciso avaliar esse bit e caso for 0 desloca-se o valor armazenado para a esquerda. Essa
-- operação é realizada pelo registrador de 16 bits (argumento: "101"). Cada vez que houver o deslocamento será
-- incrementado 1 em um contador interno. Após o LSB for 1 então finaliza-se o processo e terá-se o valor de vezes que
-- o número foi deslocado. Esse resultado será utilizado para decrementar o expoente posteriormente.
--
--
-- ANEXOS:
-- Parte alta do registrador de 16 bits: refere-se aos valores de 15 a 8 do reg_16 -> reg_16_out(15 downto 8).
-- Parte baixa do registrador de 16 bits: refere-se aos valores de 7 a 0 do reg_16 -> reg_16_out(7 downto 0).
-- Cada argumento possui uma operação específica que é melhor explicada na documentação do componente input_control.
--
--
-- (I): INPUT / (O): OUTPUT
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity multiplicador is
generic(N: natural := 8);
port(
a: in std_logic_vector((N-1) downto 0); -- Multiplicando e multiplicador
arguments: in std_logic_vector(2 downto 0); -- Argumentos que dará as ordens para o componente
clk,rst: in std_logic; -- Clock e reset
q: out std_logic_vector(((2*N)-1) downto 0); -- Produto normalizado
exp_nor: out std_logic_vector(3 downto 0) -- Expoente da normalização
);
end multiplicador;
architecture func of multiplicador is
-- Registrador de 8 bits (guardará o multiplicando)
component reg_8 is
port(
d: in std_logic_vector(7 downto 0);
enable, clk, rst: in std_logic;
q: out std_logic_vector(7 downto 0)
);
end component;
-- Registrador de 16 (+1) bits - 1 bit a mais para o carry
-- (guardará o multiplicador na parte baixa e as somas parciais na parte alta, deslocando a cada operação e
-- por fim normalizará o resultado)
component reg_16 is
port(
soma: std_logic_vector(8 downto 0); -- Resultado do enviado pelo somador
chave: std_logic_vector (7 downto 0); -- Valor do multiplicador
start, load, shift, normalize: in std_logic;-- Recursos para armazenar e manipular valores
clk, rst: in std_logic; -- Clock e reset do registrador
q: out std_logic_vector(15 downto 0); -- Saída (dados armazenados)
exp: out std_logic_vector(3 downto 0) -- Saída de números de deslocamentos realizados
);
end component;
-- Soma do multiplicando com parte alta do registrador de 16 bits.
component somador is
generic(N: natural := 8);
port(
a,b: in std_logic_vector((N-1) downto 0); -- Multiplicando e parte alta do registrador de 16 bits
control,enable: in std_logic; -- Clock e ativação
q: out std_logic_vector(N downto 0) -- Soma
);
end component;
-- Executa as operações de acordo com os argumentos enviados
component input_control is
generic(N: natural := 8);
port(
a,reg: in std_logic_vector((N-1) downto 0); -- Dado de entrada e valor da parte alta do registrador de 16 bits
arguments: in std_logic_vector(2 downto 0); -- Argumentos para operação
clk,rst: in std_logic; -- Clock, reset
l1,l2,s1,shift,n1: out std_logic; -- Saída para ativar os registradores
q: out std_logic_vector((N-1) downto 0) -- Saída do dado de entrada
);
end component;
signal reg16in, reg8in, reg8out, control_out: std_logic_vector(7 downto 0);
signal soma: std_logic_vector(8 downto 0);
signal reg16out: std_logic_vector(15 downto 0);
signal l1,l2,s1,shift,n1: std_logic;
signal exp: std_logic_vector(3 downto 0);
begin
INPUT: input_control port map (a,reg16out(15 downto 8),arguments,clk,rst,l1,l2,s1,shift,n1,control_out);
REG8 : reg_8 port map (control_out, l1, clk, rst, reg8out);
REG16: reg_16 port map (soma, control_out, s1, l2, shift, n1, clk, rst, reg16out, exp);
SUM: somador port map (reg8out, control_out, reg16out(0), l2, soma);
q <= reg16out;
exp_nor <= exp;
end func; | mit | 4a972c7908936c5a991f3cbe5ff728df | 0.719007 | 3.052797 | false | false | false | false |
hoglet67/AtomFpga | src/xilinx/AtomFpga_PapilioOne.vhd | 1 | 6,340 | --------------------------------------------------------------------------------
-- Copyright (c) 2009 Alan Daly. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ /
-- \ \ \/
-- \ \
-- / / Filename : AtomFpga_PapilioOne.vhd
-- /___/ /\ Timestamp : 02/03/2013 06:17:50
-- \ \ / \
-- \___\/\___\
--
--Design Name: AtomFpga_PapilioOne
--Device: spartan3E
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity AtomFpga_PapilioOne is
port (clk_32M00 : in std_logic;
ps2_clk : in std_logic;
ps2_data : in std_logic;
ps2_mouse_clk : inout std_logic;
ps2_mouse_data : inout std_logic;
ERST : in std_logic;
red : out std_logic_vector (2 downto 0);
green : out std_logic_vector (2 downto 0);
blue : out std_logic_vector (2 downto 0);
vsync : out std_logic;
hsync : out std_logic;
audiol : out std_logic;
audioR : out std_logic;
SDMISO : in std_logic;
SDSS : out std_logic;
SDCLK : out std_logic;
SDMOSI : out std_logic;
RxD : in std_logic;
TxD : out std_logic;
LED1 : out std_logic;
LED2 : out std_logic;
LED3 : out std_logic;
LED4 : out std_logic
);
end AtomFpga_PapilioOne;
architecture behavioral of AtomFpga_PapilioOne is
signal clock_16 : std_logic;
signal clock_25 : std_logic;
signal clock_32 : std_logic;
signal ERSTn : std_logic;
signal RomCE1 : std_logic;
signal RomCE2 : std_logic;
signal RamCE1 : std_logic;
signal RamCE2 : std_logic;
signal ExternCE : std_logic;
signal ExternWE : std_logic;
signal ExternA : std_logic_vector (18 downto 0);
signal ExternDin : std_logic_vector (7 downto 0);
signal ExternDout : std_logic_vector (7 downto 0);
signal RamDout1 : std_logic_vector (7 downto 0);
signal RamDout2 : std_logic_vector (7 downto 0);
signal RomDout1 : std_logic_vector (7 downto 0);
signal RomDout2 : std_logic_vector (7 downto 0);
begin
inst_dcm4 : entity work.dcm4 port map(
CLKIN_IN => clk_32M00,
CLK0_OUT => clock_32,
CLKFX_OUT => clock_25
);
inst_dcm5 : entity work.dcm5 port map(
CLKIN_IN => clk_32M00,
CLKFX_OUT => clock_16
);
ram_0000_07ff : entity work.RAM_2K port map(
clk => clock_16,
we_uP => ExternWE,
ce => RamCE1,
addr_uP => ExternA(10 downto 0),
D_uP => ExternDin,
Q_uP => RamDout1
);
ram_2000_3fff : entity work.RAM_8K port map(
clk => clock_16,
we_uP => ExternWE,
ce => RamCE2,
addr_uP => ExternA(12 downto 0),
D_uP => ExternDin,
Q_uP => RamDout2
);
rom_c000_ffff : entity work.InternalROM port map(
CLK => clock_16,
ADDR => ExternA(16 downto 0),
DATA => RomDout1
);
rom_a000 : entity work.fpgautils port map(
CLK => clock_16,
ADDR => ExternA(11 downto 0),
DATA => RomDout2
);
RamCE1 <= '1' when ExternCE = '1' and ExternA(15 downto 11) = "00000" else '0';
RamCE2 <= '1' when ExternCE = '1' and ExternA(15 downto 13) = "001" else '0';
RomCE1 <= '1' when ExternCE = '1' and ExternA(15 downto 14) = "11" else '0';
RomCE2 <= '1' when ExternCE = '1' and ExternA(15 downto 12) = "1010" else '0';
ExternDout(7 downto 0) <= RamDout1 when RamCE1 = '1' else
RamDout2 when RamCE2 = '1' else
RomDout1 when RomCE1 = '1' else
RomDout2 when RomCE2 = '1' else
"11110001";
ERSTn <= not ERST;
inst_AtomFpga_Core : entity work.AtomFpga_Core
generic map (
CImplSDDOS => true,
CImplAtoMMC2 => false,
CImplGraphicsExt => true,
CImplSoftChar => false,
CImplSID => true,
CImplVGA80x40 => true,
CImplHWScrolling => true,
CImplMouse => true,
CImplUart => true,
CImplDoubleVideo => false,
CImplRamRomNone => true,
CImplRamRomPhill => false,
CImplRamRomAtom2015 => false,
CImplRamRomSchakelKaart => false,
MainClockSpeed => 16000000,
DefaultBaud => 115200
)
port map(
clk_vga => clock_25,
clk_main => clock_16,
clk_avr => clock_16,
clk_dac => clock_32,
clk_32M00 => clock_32,
ps2_clk => ps2_clk,
ps2_data => ps2_data,
ps2_mouse_clk => ps2_mouse_clk,
ps2_mouse_data => ps2_mouse_data,
powerup_reset_n => ERSTn,
ext_reset_n => '1',
int_reset_n => open,
red => red,
green => green,
blue => blue,
vsync => vsync,
hsync => hsync,
phi2 => open,
ExternCE => ExternCE,
ExternWE => ExternWE,
ExternA => ExternA,
ExternDin => ExternDin,
ExternDout => ExternDout,
sid_audio => audiol,
sid_audio_d => open,
atom_audio => audioR,
SDMISO => SDMISO,
SDSS => SDSS,
SDCLK => SDCLK,
SDMOSI => SDMOSI,
uart_RxD => RxD,
uart_TxD => TxD,
avr_RxD => '1',
avr_TxD => open,
LED1 => LED1,
LED2 => LED2,
charSet => '0'
);
LED3 <= '0';
LED4 <= '0';
end behavioral;
| apache-2.0 | 3a16aa9ca13e95d963d2459470e8de29 | 0.450631 | 3.668981 | false | false | false | false |
fquinto/Wireless_sensor_network | Avnet_UPC/hdl/mb_plb_wrapper.vhd | 1 | 14,619 | -------------------------------------------------------------------------------
-- mb_plb_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library plb_v46_v1_05_a;
use plb_v46_v1_05_a.all;
entity mb_plb_wrapper is
port (
PLB_Clk : in std_logic;
SYS_Rst : in std_logic;
PLB_Rst : out std_logic;
SPLB_Rst : out std_logic_vector(0 to 8);
MPLB_Rst : out std_logic_vector(0 to 1);
PLB_dcrAck : out std_logic;
PLB_dcrDBus : out std_logic_vector(0 to 31);
DCR_ABus : in std_logic_vector(0 to 9);
DCR_DBus : in std_logic_vector(0 to 31);
DCR_Read : in std_logic;
DCR_Write : in std_logic;
M_ABus : in std_logic_vector(0 to 63);
M_UABus : in std_logic_vector(0 to 63);
M_BE : in std_logic_vector(0 to 7);
M_RNW : in std_logic_vector(0 to 1);
M_abort : in std_logic_vector(0 to 1);
M_busLock : in std_logic_vector(0 to 1);
M_TAttribute : in std_logic_vector(0 to 31);
M_lockErr : in std_logic_vector(0 to 1);
M_MSize : in std_logic_vector(0 to 3);
M_priority : in std_logic_vector(0 to 3);
M_rdBurst : in std_logic_vector(0 to 1);
M_request : in std_logic_vector(0 to 1);
M_size : in std_logic_vector(0 to 7);
M_type : in std_logic_vector(0 to 5);
M_wrBurst : in std_logic_vector(0 to 1);
M_wrDBus : in std_logic_vector(0 to 63);
Sl_addrAck : in std_logic_vector(0 to 8);
Sl_MRdErr : in std_logic_vector(0 to 17);
Sl_MWrErr : in std_logic_vector(0 to 17);
Sl_MBusy : in std_logic_vector(0 to 17);
Sl_rdBTerm : in std_logic_vector(0 to 8);
Sl_rdComp : in std_logic_vector(0 to 8);
Sl_rdDAck : in std_logic_vector(0 to 8);
Sl_rdDBus : in std_logic_vector(0 to 287);
Sl_rdWdAddr : in std_logic_vector(0 to 35);
Sl_rearbitrate : in std_logic_vector(0 to 8);
Sl_SSize : in std_logic_vector(0 to 17);
Sl_wait : in std_logic_vector(0 to 8);
Sl_wrBTerm : in std_logic_vector(0 to 8);
Sl_wrComp : in std_logic_vector(0 to 8);
Sl_wrDAck : in std_logic_vector(0 to 8);
Sl_MIRQ : in std_logic_vector(0 to 17);
PLB_MIRQ : out std_logic_vector(0 to 1);
PLB_ABus : out std_logic_vector(0 to 31);
PLB_UABus : out std_logic_vector(0 to 31);
PLB_BE : out std_logic_vector(0 to 3);
PLB_MAddrAck : out std_logic_vector(0 to 1);
PLB_MTimeout : out std_logic_vector(0 to 1);
PLB_MBusy : out std_logic_vector(0 to 1);
PLB_MRdErr : out std_logic_vector(0 to 1);
PLB_MWrErr : out std_logic_vector(0 to 1);
PLB_MRdBTerm : out std_logic_vector(0 to 1);
PLB_MRdDAck : out std_logic_vector(0 to 1);
PLB_MRdDBus : out std_logic_vector(0 to 63);
PLB_MRdWdAddr : out std_logic_vector(0 to 7);
PLB_MRearbitrate : out std_logic_vector(0 to 1);
PLB_MWrBTerm : out std_logic_vector(0 to 1);
PLB_MWrDAck : out std_logic_vector(0 to 1);
PLB_MSSize : out std_logic_vector(0 to 3);
PLB_PAValid : out std_logic;
PLB_RNW : out std_logic;
PLB_SAValid : out std_logic;
PLB_abort : out std_logic;
PLB_busLock : out std_logic;
PLB_TAttribute : out std_logic_vector(0 to 15);
PLB_lockErr : out std_logic;
PLB_masterID : out std_logic_vector(0 to 0);
PLB_MSize : out std_logic_vector(0 to 1);
PLB_rdPendPri : out std_logic_vector(0 to 1);
PLB_wrPendPri : out std_logic_vector(0 to 1);
PLB_rdPendReq : out std_logic;
PLB_wrPendReq : out std_logic;
PLB_rdBurst : out std_logic;
PLB_rdPrim : out std_logic_vector(0 to 8);
PLB_reqPri : out std_logic_vector(0 to 1);
PLB_size : out std_logic_vector(0 to 3);
PLB_type : out std_logic_vector(0 to 2);
PLB_wrBurst : out std_logic;
PLB_wrDBus : out std_logic_vector(0 to 31);
PLB_wrPrim : out std_logic_vector(0 to 8);
PLB_SaddrAck : out std_logic;
PLB_SMRdErr : out std_logic_vector(0 to 1);
PLB_SMWrErr : out std_logic_vector(0 to 1);
PLB_SMBusy : out std_logic_vector(0 to 1);
PLB_SrdBTerm : out std_logic;
PLB_SrdComp : out std_logic;
PLB_SrdDAck : out std_logic;
PLB_SrdDBus : out std_logic_vector(0 to 31);
PLB_SrdWdAddr : out std_logic_vector(0 to 3);
PLB_Srearbitrate : out std_logic;
PLB_Sssize : out std_logic_vector(0 to 1);
PLB_Swait : out std_logic;
PLB_SwrBTerm : out std_logic;
PLB_SwrComp : out std_logic;
PLB_SwrDAck : out std_logic;
Bus_Error_Det : out std_logic
);
attribute x_core_info : STRING;
attribute x_core_info of mb_plb_wrapper : entity is "plb_v46_v1_05_a";
end mb_plb_wrapper;
architecture STRUCTURE of mb_plb_wrapper is
component plb_v46 is
generic (
C_PLBV46_NUM_MASTERS : integer;
C_PLBV46_NUM_SLAVES : integer;
C_PLBV46_MID_WIDTH : integer;
C_PLBV46_AWIDTH : integer;
C_PLBV46_DWIDTH : integer;
C_DCR_INTFCE : integer;
C_BASEADDR : std_logic_vector;
C_HIGHADDR : std_logic_vector;
C_DCR_AWIDTH : integer;
C_DCR_DWIDTH : integer;
C_EXT_RESET_HIGH : integer;
C_IRQ_ACTIVE : std_logic;
C_ADDR_PIPELINING_TYPE : integer;
C_FAMILY : string;
C_P2P : integer;
C_ARB_TYPE : integer
);
port (
PLB_Clk : in std_logic;
SYS_Rst : in std_logic;
PLB_Rst : out std_logic;
SPLB_Rst : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
MPLB_Rst : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_dcrAck : out std_logic;
PLB_dcrDBus : out std_logic_vector(0 to C_DCR_DWIDTH-1);
DCR_ABus : in std_logic_vector(0 to C_DCR_AWIDTH-1);
DCR_DBus : in std_logic_vector(0 to C_DCR_DWIDTH-1);
DCR_Read : in std_logic;
DCR_Write : in std_logic;
M_ABus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*32)-1);
M_UABus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*32)-1);
M_BE : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*(C_PLBV46_DWIDTH/8))-1);
M_RNW : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_abort : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_busLock : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_TAttribute : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*16)-1);
M_lockErr : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_MSize : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*2)-1);
M_priority : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*2)-1);
M_rdBurst : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_request : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_size : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*4)-1);
M_type : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*3)-1);
M_wrBurst : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_wrDBus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*C_PLBV46_DWIDTH)-1);
Sl_addrAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_MRdErr : in std_logic_vector(0 to (C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS)-1);
Sl_MWrErr : in std_logic_vector(0 to (C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS)-1);
Sl_MBusy : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS - 1 );
Sl_rdBTerm : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_rdComp : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_rdDAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_rdDBus : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*C_PLBV46_DWIDTH-1);
Sl_rdWdAddr : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*4-1);
Sl_rearbitrate : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_SSize : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*2-1);
Sl_wait : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_wrBTerm : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_wrComp : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_wrDAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_MIRQ : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS-1);
PLB_MIRQ : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_ABus : out std_logic_vector(0 to 31);
PLB_UABus : out std_logic_vector(0 to 31);
PLB_BE : out std_logic_vector(0 to (C_PLBV46_DWIDTH/8)-1);
PLB_MAddrAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MTimeout : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MBusy : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MWrErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdBTerm : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdDAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdDBus : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*C_PLBV46_DWIDTH)-1);
PLB_MRdWdAddr : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*4)-1);
PLB_MRearbitrate : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MWrBTerm : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MWrDAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MSSize : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*2)-1);
PLB_PAValid : out std_logic;
PLB_RNW : out std_logic;
PLB_SAValid : out std_logic;
PLB_abort : out std_logic;
PLB_busLock : out std_logic;
PLB_TAttribute : out std_logic_vector(0 to 15);
PLB_lockErr : out std_logic;
PLB_masterID : out std_logic_vector(0 to C_PLBV46_MID_WIDTH-1);
PLB_MSize : out std_logic_vector(0 to 1);
PLB_rdPendPri : out std_logic_vector(0 to 1);
PLB_wrPendPri : out std_logic_vector(0 to 1);
PLB_rdPendReq : out std_logic;
PLB_wrPendReq : out std_logic;
PLB_rdBurst : out std_logic;
PLB_rdPrim : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
PLB_reqPri : out std_logic_vector(0 to 1);
PLB_size : out std_logic_vector(0 to 3);
PLB_type : out std_logic_vector(0 to 2);
PLB_wrBurst : out std_logic;
PLB_wrDBus : out std_logic_vector(0 to C_PLBV46_DWIDTH-1);
PLB_wrPrim : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
PLB_SaddrAck : out std_logic;
PLB_SMRdErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_SMWrErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_SMBusy : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_SrdBTerm : out std_logic;
PLB_SrdComp : out std_logic;
PLB_SrdDAck : out std_logic;
PLB_SrdDBus : out std_logic_vector(0 to C_PLBV46_DWIDTH-1);
PLB_SrdWdAddr : out std_logic_vector(0 to 3);
PLB_Srearbitrate : out std_logic;
PLB_Sssize : out std_logic_vector(0 to 1);
PLB_Swait : out std_logic;
PLB_SwrBTerm : out std_logic;
PLB_SwrComp : out std_logic;
PLB_SwrDAck : out std_logic;
Bus_Error_Det : out std_logic
);
end component;
begin
mb_plb : plb_v46
generic map (
C_PLBV46_NUM_MASTERS => 2,
C_PLBV46_NUM_SLAVES => 9,
C_PLBV46_MID_WIDTH => 1,
C_PLBV46_AWIDTH => 32,
C_PLBV46_DWIDTH => 32,
C_DCR_INTFCE => 0,
C_BASEADDR => B"1111111111",
C_HIGHADDR => B"0000000000",
C_DCR_AWIDTH => 10,
C_DCR_DWIDTH => 32,
C_EXT_RESET_HIGH => 1,
C_IRQ_ACTIVE => '1',
C_ADDR_PIPELINING_TYPE => 1,
C_FAMILY => "spartan3a",
C_P2P => 0,
C_ARB_TYPE => 0
)
port map (
PLB_Clk => PLB_Clk,
SYS_Rst => SYS_Rst,
PLB_Rst => PLB_Rst,
SPLB_Rst => SPLB_Rst,
MPLB_Rst => MPLB_Rst,
PLB_dcrAck => PLB_dcrAck,
PLB_dcrDBus => PLB_dcrDBus,
DCR_ABus => DCR_ABus,
DCR_DBus => DCR_DBus,
DCR_Read => DCR_Read,
DCR_Write => DCR_Write,
M_ABus => M_ABus,
M_UABus => M_UABus,
M_BE => M_BE,
M_RNW => M_RNW,
M_abort => M_abort,
M_busLock => M_busLock,
M_TAttribute => M_TAttribute,
M_lockErr => M_lockErr,
M_MSize => M_MSize,
M_priority => M_priority,
M_rdBurst => M_rdBurst,
M_request => M_request,
M_size => M_size,
M_type => M_type,
M_wrBurst => M_wrBurst,
M_wrDBus => M_wrDBus,
Sl_addrAck => Sl_addrAck,
Sl_MRdErr => Sl_MRdErr,
Sl_MWrErr => Sl_MWrErr,
Sl_MBusy => Sl_MBusy,
Sl_rdBTerm => Sl_rdBTerm,
Sl_rdComp => Sl_rdComp,
Sl_rdDAck => Sl_rdDAck,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rearbitrate => Sl_rearbitrate,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_wrBTerm => Sl_wrBTerm,
Sl_wrComp => Sl_wrComp,
Sl_wrDAck => Sl_wrDAck,
Sl_MIRQ => Sl_MIRQ,
PLB_MIRQ => PLB_MIRQ,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_BE => PLB_BE,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MTimeout => PLB_MTimeout,
PLB_MBusy => PLB_MBusy,
PLB_MRdErr => PLB_MRdErr,
PLB_MWrErr => PLB_MWrErr,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MWrBTerm => PLB_MWrBTerm,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MSSize => PLB_MSSize,
PLB_PAValid => PLB_PAValid,
PLB_RNW => PLB_RNW,
PLB_SAValid => PLB_SAValid,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_TAttribute => PLB_TAttribute,
PLB_lockErr => PLB_lockErr,
PLB_masterID => PLB_masterID,
PLB_MSize => PLB_MSize,
PLB_rdPendPri => PLB_rdPendPri,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdBurst => PLB_rdBurst,
PLB_rdPrim => PLB_rdPrim,
PLB_reqPri => PLB_reqPri,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_wrBurst => PLB_wrBurst,
PLB_wrDBus => PLB_wrDBus,
PLB_wrPrim => PLB_wrPrim,
PLB_SaddrAck => PLB_SaddrAck,
PLB_SMRdErr => PLB_SMRdErr,
PLB_SMWrErr => PLB_SMWrErr,
PLB_SMBusy => PLB_SMBusy,
PLB_SrdBTerm => PLB_SrdBTerm,
PLB_SrdComp => PLB_SrdComp,
PLB_SrdDAck => PLB_SrdDAck,
PLB_SrdDBus => PLB_SrdDBus,
PLB_SrdWdAddr => PLB_SrdWdAddr,
PLB_Srearbitrate => PLB_Srearbitrate,
PLB_Sssize => PLB_Sssize,
PLB_Swait => PLB_Swait,
PLB_SwrBTerm => PLB_SwrBTerm,
PLB_SwrComp => PLB_SwrComp,
PLB_SwrDAck => PLB_SwrDAck,
Bus_Error_Det => Bus_Error_Det
);
end architecture STRUCTURE;
| mit | 71ad2e906401d5afe8fddd51e2ed6d59 | 0.610302 | 3.033617 | false | false | false | false |
bertuccio/ARQ | Practica3/procesador.vhd | 1 | 13,702 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity procesador is
port(
Clk : in std_logic;
Reset : in std_logic;
-- Instruction memory
I_Addr : out std_logic_vector(31 downto 0);
I_RdStb : out std_logic;
I_WrStb : out std_logic;
I_AddrStb : out std_logic;
I_DataOut : out std_logic_vector(31 downto 0);
I_Rdy : in std_logic;
I_DataIn : in std_logic_vector(31 downto 0);
-- Data memory
D_Addr : out std_logic_vector(31 downto 0);
D_RdStb : out std_logic;
D_WrStb : out std_logic;
D_AddrStb : out std_logic;
D_DataOut : out std_logic_vector(31 downto 0);
D_Rdy : in std_logic;
D_DataIn : in std_logic_vector(31 downto 0)
);
end procesador;
architecture procesador_arq of procesador is
------------------------
------COMPONENTES-------
------------------------
component tabla_registros PORT
( CLK : in STD_LOGIC;
Reset : in STD_LOGIC;
EscrReg : in STD_LOGIC;
reg_lec1 : in STD_LOGIC_VECTOR (4 downto 0);
reg_lec2 : in STD_LOGIC_VECTOR (4 downto 0);
reg_escr: in STD_LOGIC_VECTOR (4 downto 0);
dato_escr : in STD_LOGIC_VECTOR (31 downto 0);
dato_leido1 : out STD_LOGIC_VECTOR (31 downto 0);
dato_leido2 : out STD_LOGIC_VECTOR (31 downto 0));
end component;
component ALU PORT
( A : in STD_LOGIC_VECTOR (31 downto 0);
B : in STD_LOGIC_VECTOR (31 downto 0);
control : in STD_LOGIC_VECTOR (3 downto 0);
resultado : out STD_LOGIC_VECTOR (31 downto 0);
igual : out STD_LOGIC);
end component;
component ForwardingUnit Port
( ID_EX_RS : in STD_LOGIC_VECTOR (4 downto 0);
ID_EX_RT : in STD_LOGIC_VECTOR (4 downto 0);
EX_MEM_ESCREG : in STD_LOGIC;
MEM_WB_ESCREG : in STD_LOGIC;
EX_MEM_RD : in STD_LOGIC_VECTOR (4 downto 0);
MEM_WB_RD : in STD_LOGIC_VECTOR (4 downto 0);
AnticipaA : out STD_LOGIC_VECTOR (1 downto 0);
AnticipaB : out STD_LOGIC_VECTOR (1 downto 0));
end component;
component HAZARD
Port ( PC_Write : out STD_LOGIC;
IFID_Write : out STD_LOGIC;
IDEX_Memread : in STD_LOGIC;
MUX_sel : out STD_LOGIC;
IDEX_Rt : in STD_LOGIC_VECTOR (4 downto 0);
IFID_Rs : in STD_LOGIC_VECTOR (4 downto 0);
IFID_Rt : in STD_LOGIC_VECTOR (4 downto 0));
end component;
------------------
-----SEÑALES------
------------------
signal PC_IN : STD_LOGIC_VECTOR (31 downto 0);
signal PC_IN1 : STD_LOGIC_VECTOR (31 downto 0);
signal addResultIN : STD_LOGIC_VECTOR (31 downto 0);
signal addResultOUT : STD_LOGIC_VECTOR (31 downto 0);
signal MemMux1 : STD_LOGIC_VECTOR (31 downto 0);
signal MemMux2 : STD_LOGIC_VECTOR (31 downto 0);
-------ALU-----------------------------------------
signal OpA : STD_LOGIC_VECTOR (31 downto 0);
signal OpAPosible : STD_LOGIC_VECTOR (31 downto 0);
signal OpB : STD_LOGIC_VECTOR (31 downto 0);
signal mux1OpB: STD_LOGIC_VECTOR (31 downto 0);
signal mux1OpBPosible : STD_LOGIC_VECTOR (31 downto 0);
signal mux2OpB: STD_LOGIC_VECTOR (31 downto 0);
signal AluControl : STD_LOGIC_VECTOR (5 downto 0);
signal ALUctr : STD_LOGIC_VECTOR (3 downto 0);
signal Zero : STD_LOGIC;
signal AluResultIN : STD_LOGIC_VECTOR (31 downto 0);
signal AluResultOUT : STD_LOGIC_VECTOR (31 downto 0);
---------------------------------------------------
--------------CONTROL----------------------------
signal Control: STD_LOGIC_VECTOR (5 downto 0);
------EX------------
signal EXctr : std_logic_vector(3 downto 0);
signal EXHAZARD : std_logic_vector(3 downto 0);
signal RegDst: STD_LOGIC;
signal ALUOp: STD_LOGIC_VECTOR (1 downto 0);
signal AluSrc : STD_LOGIC;
-------M------------
signal Mctr : std_logic_vector(2 downto 0);
signal MHAZARD : std_logic_vector(2 downto 0);
signal Mctr1 : std_logic_vector(2 downto 0);
signal Mctr2 : std_logic_vector(2 downto 0);
signal PCSrc : STD_LOGIC;
------WB------------
signal WEctr : std_logic_vector(1 downto 0);
signal WEHAZARD : std_logic_vector(1 downto 0);
signal WEctr1 : std_logic_vector(1 downto 0);
signal WEctr2 : std_logic_vector(1 downto 0);
signal EscrReg : STD_LOGIC;
signal MemToReg : STD_LOGIC;
---------------------------------------------------
signal signo_extend: STD_LOGIC_VECTOR (31 downto 0);
signal reg_lect1IF : STD_LOGIC_VECTOR (4 downto 0);
signal reg_lect2IF : STD_LOGIC_VECTOR (4 downto 0);
signal rdInstCarg : STD_LOGIC_VECTOR (4 downto 0);
signal rdInstALU : STD_LOGIC_VECTOR (4 downto 0);
signal reg_escr: STD_LOGIC_VECTOR (4 downto 0);
signal reg_escrIN: STD_LOGIC_VECTOR (4 downto 0);
signal dato_leido1 : STD_LOGIC_VECTOR (31 downto 0);
signal dato_leido2 : STD_LOGIC_VECTOR (31 downto 0);
signal dato_escr : STD_LOGIC_VECTOR (31 downto 0);
signal RegEscribir1 : STD_LOGIC_VECTOR (4 downto 0);
signal RegEscribir2 : STD_LOGIC_VECTOR (4 downto 0);
signal mux_aux1 : STD_LOGIC_VECTOR (4 downto 0);
signal mux_aux2 : STD_LOGIC_VECTOR (4 downto 0);
---------FORWARDINGUNIT-----------
signal ID_EX_RS : STD_LOGIC_VECTOR (4 downto 0);
signal ID_EX_RT : STD_LOGIC_VECTOR (4 downto 0);
signal EX_MEM_ESCREG : STD_LOGIC;
signal MEM_WB_ESCREG : STD_LOGIC;
signal EX_MEM_RD : STD_LOGIC_VECTOR (4 downto 0);
signal MEM_WB_RD : STD_LOGIC_VECTOR (4 downto 0);
signal AnticipaA : STD_LOGIC_VECTOR (1 downto 0);
signal AnticipaB : STD_LOGIC_VECTOR (1 downto 0);
signal PC_Write : STD_LOGIC;
signal IFID_Write : STD_LOGIC;
signal IDEX_Memread : STD_LOGIC;
signal MUX_sel : STD_LOGIC;
signal IDEX_Rt : STD_LOGIC_VECTOR (4 downto 0);
signal IFID_Rs : STD_LOGIC_VECTOR (4 downto 0);
signal IFID_Rt : STD_LOGIC_VECTOR (4 downto 0);
begin
-----------------
----PORT-MAPS----
-----------------
--BANCO REGISTROS--
BANCO: tabla_registros port map(
CLK => Clk,
Reset => Reset,
EscrReg => EscrReg,
reg_lec1 => reg_lect1IF,
reg_lec2 => reg_lect2IF,
reg_escr => reg_escr,
dato_escr => dato_escr,
dato_leido1 => dato_leido1,
dato_leido2 => dato_leido2);
--ALU--
UAL : ALU port map(
A => OpA,
B => OpB,
control => ALUctr,
resultado => AluResultIN,
igual => Zero);
UnitForward: ForwardingUnit port map(
ID_EX_RS =>ID_EX_RS,
ID_EX_RT =>ID_EX_RT,
EX_MEM_ESCREG => EX_MEM_ESCREG,
MEM_WB_ESCREG =>MEM_WB_ESCREG,
EX_MEM_RD => EX_MEM_RD,
MEM_WB_RD => MEM_WB_RD,
AnticipaA => AnticipaA,
AnticipaB => AnticipaB);
HazardUnit: HAZARD port map(
PC_Write=>PC_Write,
IFID_Write=> IFID_Write,
IDEX_Memread=>IDEX_Memread,
MUX_sel=>MUX_sel,
IDEX_Rt=>IDEX_Rt,
IFID_Rs=>IFID_Rs,
IFID_Rt=>IFID_Rt);
I_RdStb<='1';
I_WrStb<='0';
I_AddrStb<='1';
D_AddrStb<='1';
I_Addr<=PC_IN;
I_DataOut<=x"00000000";
------------------------------
----CONTADOR DE PROGRAMA------
------------------------------
process(Clk,Reset)
begin
if Reset='1' then
PC_IN<=x"00000000";
else
if rising_edge(Clk) then
if PC_Write='1' then
if (PCSrc='1') then
PC_IN<=addResultOUT;
else
PC_IN<=PC_IN+4;
end if;
end if;
end if;
end if;
end process;
-----------------------
---PRIMER PIPE (IF)----
-----------------------
process (Clk,Reset)
begin
if (Reset='1')or (PcSrc='1') then
PC_IN1<=x"00000000";
Control<= "111111";
reg_lect1IF<="00000";
reg_lect2IF<="00000";
rdInstCarg<= "00000";
rdInstALU<= "00000";
signo_extend<=x"00000000";
IFID_Rs<="00000";
IFID_Rt<="00000";
else
if rising_edge(Clk) then
if (IFID_Write='1') then
PC_IN1<=PC_IN;
Control <= I_DataIn(31 downto 26);
reg_lect1IF <=I_DataIn(25 downto 21);
reg_lect2IF <=I_DataIn(20 downto 16);
rdInstCarg <= I_DataIn(20 downto 16);
rdInstALU <= I_DataIn(15 downto 11);
if I_DataIn(15)='1' then
signo_extend<=x"FFFF"&I_DataIn(15 downto 0);
else
signo_extend<=x"0000"&I_DataIn(15 downto 0);
end if;
end if;
end if;
end if;
end process;
IFID_Rs<=reg_lect1IF;
IFID_Rt<=reg_lect2IF;
IDEX_Rt<=mux_aux1;
IDEX_Memread<=Mctr1(1);
-----------------------
---SEGUNDO PIPE (EX)--
-----------------------
process (Clk,Reset)
begin
if (Reset='1')or (PcSrc='1') then
WEctr1<="00";
Mctr1<="000";
ALUOp<="00";
ALUcontrol<="000000";
OpAPosible<=x"00000000";
mux1OpBPosible<=x"00000000";
mux2OpB<=x"00000000";
mux_aux1<="00000";
mux_aux2<="00000";
addResultIN<=x"00000000";
AluSrc<='0';
RegDst<='0';
ID_EX_RS<="00000";
ID_EX_RT<="00000";
IDEX_Rt<="00000";
else
if rising_edge(Clk) then
if (PcSrc='1') then
WEctr1<="00";
Mctr1<="000";
ALUOp<="00";
ALUcontrol<="000000";
OpAPosible<=x"00000000";
mux1OpBPosible<=x"00000000";
mux2OpB<=x"00000000";
mux_aux1<="00000";
mux_aux2<="00000";
addResultIN<=x"00000000";
AluSrc<='0';
RegDst<='0';
ID_EX_RS<="00000";
ID_EX_RT<="00000";
IDEX_Rt<="00000";
else
WEctr1<=WEctr;
Mctr1<=Mctr;
ALUcontrol<=signo_extend(5 downto 0);
mux2OpB<=signo_extend;
addResultIN<=signo_extend(29 downto 0)&"00"+PC_IN1;
OpAPosible<=dato_leido1;
mux1OpBPosible<=dato_leido2;
mux_aux1<=rdInstCarg;
mux_aux2<=rdInstALU;
RegDst<=EXctr(3);
ALUOp<=EXctr(2 downto 1);
AluSrc<=EXctr(0);
ID_EX_RS<=reg_lect1IF;
ID_EX_RT<=reg_lect2IF;
end if;
end if;
end if;
end process;
----------MULTIPLEXORES--------------
WITH AluSrc SELECT
OpB <=mux1OpB WHEN '0',
mux2OpB WHEN OTHERS;
WITH RegDst SELECT
regEscribir1 <=mux_aux1 WHEN '0',
mux_aux2 WHEN OTHERS;
WITH MemToReg SELECT
dato_escr <=MemMux2 WHEN '0',
MemMux1 WHEN OTHERS;
------------------------------------
--MULTIPLEXOR PARA ELEGIR LA ENTRADA A LA ALU DEL OPERANDO A
process (OpAPosible, AnticipaA, dato_escr, aluResultOUT)
begin
if( AnticipaA= "00" )then
OpA <= OpAPosible;
elsif( AnticipaA="01" ) then
OpA <= dato_escr;
elsif( AnticipaA="10" ) then
OpA <= aluResultOUT;--when AnticipaA="10"
end if;
end process;
--MULTIPLEXOR PARA ELEGIR LA ENTRADA POSIBLE DEL OPERANDO B
process (mux1OpB, AnticipaB, dato_escr, aluResultOUT)
begin
if( AnticipaB= "00" )then
mux1OpB <= mux1OpBPosible;
elsif( AnticipaB="01" ) then
mux1OpB <= dato_escr;
elsif( AnticipaB="10" ) then
mux1OpB <= aluResultOUT;
end if;
end process;
-----------------------
---TERCER PIPE (MEM)--
-----------------------
process (Clk,Reset)
begin
if (Reset='1') then
addResultOUT<=x"00000000";
D_WrStb<='0';--memwrite
D_RdStb<='0';--memread
PCSrc<='0';
D_DataOut<=x"00000000";
aluResultOUT<=x"00000000";
WEctr2<="00";
regEscribir2<="00000";
D_Addr<=x"00000000";
EX_MEM_ESCREG<='0';
IDEX_Memread <= '0';
EX_MEM_RD<="00000";
else
if rising_edge(Clk) then
if (PcSrc='1') then
addResultOUT<=x"00000000";
D_WrStb<='0';--memwrite
D_RdStb<='0';--memread
PCSrc<='0';
D_DataOut<=x"00000000";
aluResultOUT<=x"00000000";
WEctr2<="00";
regEscribir2<="00000";
D_Addr<=x"00000000";
EX_MEM_ESCREG<='0';
IDEX_Memread <= '0';
EX_MEM_RD<="00000";
else
WEctr2<=WEctr1;
addResultOUT<=addResultIN;
D_WrStb<=Mctr1(0);--memwrite
D_RdStb<=Mctr1(1);--memread
PCSrc<=Mctr1(2) and Zero;
EX_MEM_RD<=regEscribir1;
D_Addr<=AluResultIN;
aluResultOUT<=AluResultIN;
D_DataOut<=mux1OpB;
regEscribir2<=regEscribir1;
EX_MEM_ESCREG<=WEctr1(1);
end if;
end if;
end if;
end process;
-------------------
----REGISTRO 4-----
-------------------
process (Clk,Reset) begin
if (Reset='1')or (PcSrc='1') then
MemMux1<=x"00000000";
MemMux2<=x"00000000";
reg_escr<="00000";
MemToReg<='0';
EscrReg<='0';
MEM_WB_ESCREG<='0';
else
if rising_edge(Clk) then
MemMux1<=D_DataIn;
MemMux2<=aluResultOUT;
reg_escr<=regEscribir2;
MemToReg<=WEctr2(0);
EscrReg<=WEctr2(1);
MEM_WB_ESCREG<=WEctr2(1);
MEM_WB_RD<=regEscribir2;
end if;
end if;
end process;
process (ALUOp, ALUcontrol) begin
case ALUOp is
when "10"=>--REG_A_REG
case ALUcontrol is
when "100000"=>--ADD
ALUctr<="0011";
when "100010"=>--SUB
ALUctr<="1000";
when "100100"=>--AND
ALUctr<="0000";
when "100101"=>--OR
ALUctr<="0001";
when "100110"=>--XOR
ALUctr<="0010";
when "101010"=>--SLT
ALUctr<="1010";
when others =>
ALUctr<="1111";
end case;
when "00"=>--LW ó SW
ALUctr<="0011";--ADD PARA CONSEGUIR LA DIRECCION DE MEMORIA
when "01"=>--BEQ
ALUctr<="0010";--XOR PARA VER SI RS Y RT SON IGUALES
when "11"=>--LIU
ALUctr<="1001";
when others =>
ALUctr<="1111";
end case;
end process;
process (Control) begin
case Control is
when "000000"=> --SPECIAL (R)
EXHAZARD<="1100";
MHAZARD<="000";
WEHAZARD<="10";
when "100011"=> --LW
EXHAZARD<="0001";
MHAZARD<="010";
WEHAZARD<="11";
when "101011"=> --SW
EXHAZARD<="0001";
MHAZARD<="001";
WEHAZARD<="00";
when "001111"=> --LIU
EXHAZARD<="0110";
MHAZARD<="000";
WEHAZARD<="10";
when "000100"=> --BE
EXHAZARD<="0010";
MHAZARD<="100";
WEHAZARD<="00";
when others =>
EXHAZARD<="0000";
MHAZARD<="000";
WEHAZARD<="00";
end case;
end process;
process (MUX_Sel, WEHAZARD,MHAZARD,EXHAZARD)
begin
if MUX_Sel='1' then
WEctr<="00";
Mctr<="000";
EXctr<="0000";
elsif MUX_Sel='0' then
WEctr<=WEHAZARD;
Mctr<=MHAZARD;
EXctr<=EXHAZARD;
end if;
end process;
end procesador_arq;
| mit | 7b2be025d3ed934f408c9d9eda56a5d6 | 0.588016 | 2.901122 | false | false | false | false |
JavierRizzoA/Sacagawea | sources/Sacagawea.vhd | 1 | 2,874 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:15:24 06/06/2016
-- Design Name:
-- Module Name: Sacagawea - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Sacagawea is
Port ( clk : in STD_LOGIC;
senal_rst : in STD_LOGIC;
switches_sal : in STD_LOGIC_VECTOR (7 downto 0);
leds_in : out STD_LOGIC_VECTOR (7 downto 0);
bus_datos_memtoregs : out std_logic_vector(7 downto 0);
bus_datos_mbrtomem : out std_logic_vector(7 downto 0);
senal_rw : out std_logic;
conta : out std_logic_vector(24 downto 0);
salida_ip : out std_logic_vector(11 downto 0);
salida_ir : out std_logic_vector(7 downto 0);
salida_ar : out std_logic_vector(11 downto 0)
);
end Sacagawea;
architecture Behavioral of Sacagawea is
COMPONENT CPU
Port (
clk : in STD_LOGIC;
senal_rst : in STD_LOGIC;
ar_sal : out STD_LOGIC_VECTOR (11 downto 0);
bus_datos_out: in STD_LOGIC_VECTOR (7 DOWNTO 0);
bus_datos_in : out std_logic_vector(7 downto 0);
read_write: out STD_LOGIC;
cont : out std_logic_vector(24 downto 0);
salida_ip : out std_logic_vector(11 downto 0);
salida_ir : out std_logic_vector(7 downto 0)
);
END COMPONENT;
COMPONENT Dispositivos
port(
ar : in std_logic_vector(11 downto 0);
clk : in std_logic;
ram_w_r: in std_logic;
bus_datos_out : out std_logic_vector(7 downto 0);
bus_datos_in : in std_logic_vector(7 downto 0);
sal_leds_spartan : out std_logic_vector(7 downto 0);
in_switches_spartan : in std_logic_vector(7 downto 0)
);
END COMPONENT;
SIGNAL ar_sal : STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL bus_datos0, bus_datos1 : STD_LOGIC_VECTOR(7 DOWNTO 0); -- 0 salida hacia regs ... 1 entrada a mem
SIGNAL read_write: STD_LOGIC;
signal contout : std_logic_vector(24 downto 0);
begin
cpu0: CPU port map(clk, senal_rst, ar_sal, bus_datos0, bus_datos1, read_write, contout, salida_ip, salida_ir);
memes: Dispositivos port map(ar_sal, clk, read_write, bus_datos0, bus_datos1, leds_in, switches_sal);
bus_datos_memtoregs <= bus_datos0;
bus_datos_mbrtomem <= bus_datos1;
senal_rw <= read_write;
conta <= contout;
salida_ar <= ar_sal;
end Behavioral;
| mit | ed671b7fb784eedcc16fe85074eb47e5 | 0.625609 | 3.258503 | false | false | false | false |
timofonic/PHDL | misc/projects/spartan_pcie_board/fpga/lx45t_pinout/ipcore_dir/pcie_core/source/pcie_bram_top_s6.vhd | 1 | 7,659 | -------------------------------------------------------------------------------
--
-- (c) Copyright 2008, 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Project : Spartan-6 Integrated Block for PCI Express
-- File : pcie_bram_top_s6.vhd
-- Description: BlockRAM top level module for Spartan-6 PCIe Block
--
-- Given the selected core configuration, calculate the number of
-- BRAMs and pipeline stages and instantiate the BRAMS.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity pcie_bram_top_s6 is
generic (
DEV_CAP_MAX_PAYLOAD_SUPPORTED : integer := 0;
VC0_TX_LASTPACKET : integer := 31;
TLM_TX_OVERHEAD : integer := 20;
TL_TX_RAM_RADDR_LATENCY : integer := 1;
TL_TX_RAM_RDATA_LATENCY : integer := 2;
TL_TX_RAM_WRITE_LATENCY : integer := 1;
VC0_RX_LIMIT : integer := 16#1FFF#;
TL_RX_RAM_RADDR_LATENCY : integer := 1;
TL_RX_RAM_RDATA_LATENCY : integer := 2;
TL_RX_RAM_WRITE_LATENCY : integer := 1
);
port (
user_clk_i : in std_logic;
reset_i : in std_logic;
mim_tx_wen : in std_logic;
mim_tx_waddr : in std_logic_vector(11 downto 0);
mim_tx_wdata : in std_logic_vector(35 downto 0);
mim_tx_ren : in std_logic;
mim_tx_rce : in std_logic;
mim_tx_raddr : in std_logic_vector(11 downto 0);
mim_tx_rdata : out std_logic_vector(35 downto 0);
mim_rx_wen : in std_logic;
mim_rx_waddr : in std_logic_vector(11 downto 0);
mim_rx_wdata : in std_logic_vector(35 downto 0);
mim_rx_ren : in std_logic;
mim_rx_rce : in std_logic;
mim_rx_raddr : in std_logic_vector(11 downto 0);
mim_rx_rdata : out std_logic_vector(35 downto 0)
);
end pcie_bram_top_s6;
architecture rtl of pcie_bram_top_s6 is
component pcie_brams_s6
generic (
NUM_BRAMS : integer;
RAM_RADDR_LATENCY : integer;
RAM_RDATA_LATENCY : integer;
RAM_WRITE_LATENCY : integer
);
port (
user_clk_i : in std_logic;
reset_i : in std_logic;
wen : in std_logic;
waddr : in std_logic_vector(11 downto 0);
wdata : in std_logic_vector(35 downto 0);
ren : in std_logic;
rce : in std_logic;
raddr : in std_logic_vector(11 downto 0);
rdata : out std_logic_vector(35 downto 0)
);
end component;
function CALC_TX_COLS(constant MPS : in integer;
constant LASTPACKET : in integer;
constant OVERHEAD : in integer
) return integer is
variable MPS_BYTES : integer;
variable BYTES_TX : integer;
variable COLS_TX : integer;
begin
-- Decode MPS value
if (MPS = 0) then MPS_BYTES := 128;
elsif (MPS = 1) then MPS_BYTES := 256;
else MPS_BYTES := 512; -- MPS = 2
end if;
-- Calculate total bytes from MPS, number of packets, and overhead
BYTES_TX := (LASTPACKET + 1) * (MPS_BYTES + OVERHEAD);
-- Determine number of BRAM columns from total bytes
if (BYTES_TX <= 2048) then COLS_TX := 1;
elsif (BYTES_TX <= 4096) then COLS_TX := 2;
else COLS_TX := 4; -- BYTES_TX <= 8192
end if;
return COLS_TX;
end function CALC_TX_COLS;
function CALC_RX_COLS(constant LIMIT : in integer) return integer is
variable COLS_RX : integer;
begin
-- Determine number of BRAM columns from total RAM size
if (LIMIT <= 512) then COLS_RX := 1;
elsif (LIMIT <= 1024) then COLS_RX := 2;
else COLS_RX := 4; -- LIMIT <= 2048
end if;
return COLS_RX;
end function CALC_RX_COLS;
begin
pcie_brams_tx : pcie_brams_s6
generic map(
NUM_BRAMS => CALC_TX_COLS(DEV_CAP_MAX_PAYLOAD_SUPPORTED, VC0_TX_LASTPACKET, TLM_TX_OVERHEAD),
RAM_RADDR_LATENCY => TL_TX_RAM_RADDR_LATENCY,
RAM_RDATA_LATENCY => TL_TX_RAM_RDATA_LATENCY,
RAM_WRITE_LATENCY => TL_TX_RAM_WRITE_LATENCY
)
port map (
user_clk_i => user_clk_i,
reset_i => reset_i,
waddr => mim_tx_waddr,
wen => mim_tx_wen,
ren => mim_tx_ren,
rce => mim_tx_rce,
wdata => mim_tx_wdata,
raddr => mim_tx_raddr,
rdata => mim_tx_rdata
);
pcie_brams_rx : pcie_brams_s6
generic map(
NUM_BRAMS => CALC_RX_COLS(VC0_RX_LIMIT),
RAM_RADDR_LATENCY => TL_RX_RAM_RADDR_LATENCY,
RAM_RDATA_LATENCY => TL_RX_RAM_RDATA_LATENCY,
RAM_WRITE_LATENCY => TL_RX_RAM_WRITE_LATENCY
)
port map (
user_clk_i => user_clk_i,
reset_i => reset_i,
waddr => mim_rx_waddr,
wen => mim_rx_wen,
ren => mim_rx_ren,
rce => mim_rx_rce,
wdata => mim_rx_wdata,
raddr => mim_rx_raddr,
rdata => mim_rx_rdata
);
end rtl;
| gpl-3.0 | 0879291bfb5699b0af2e1190f3c1027c | 0.578927 | 3.761788 | false | false | false | false |
Nixon-/VHDL_library | basic/nbit_encoder.vhd | 1 | 859 | Library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity nbit_encoder is
generic(
numInputs: integer:=4
);
port(
enable: in std_logic;
inputVector: in std_logic_vector(numInputs -1 downto 0);
outputVector: out std_logic_vector(integer(log2(Real(numInputs))) -1 downto 0)
);
end nbit_encoder;
architecture primary of nbit_encoder is
signal outputTemp: std_logic_vector(integer(log2(Real(numInputs))) -1 downto 0);
begin
process(enable,inputVector,outputTemp)
begin
if(enable = '1') then
outputTemp <= (others=>'0');
for num in 0 to numInputs-1 loop
if(inputVector(num) = '1') then
outputTemp <= std_logic_vector((to_unsigned(num, integer(log2(Real(numInputs))))));
end if;
end loop;
else
outputTemp <= (others=>'0');
end if
end process;
outputVector<=outputTemp;
end primary;
| gpl-2.0 | d2ac4b4854879b84dbafa6f1e0ca38f8 | 0.710128 | 2.95189 | false | false | false | false |
masaruohashi/tic-tac-toe | uart/contador_transmissao.vhd | 1 | 960 | -- VHDL de um contador_transmissao de modulo 16
-- OBS: Para esse experimento so eh utilizada a contagem ate 11
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity contador_transmissao is
port(clock : in std_logic;
enable : in std_logic;
zera : in std_logic;
conta : in std_logic;
contagem : out std_logic_vector(3 downto 0);
fim : out std_logic);
end contador_transmissao;
architecture exemplo of contador_transmissao is
signal IQ: unsigned(3 downto 0);
begin
process (clock, conta, IQ, zera)
begin
if zera = '1' then
IQ <= (others => '0');
elsif clock'event and clock = '1' then
if conta = '1' and enable = '1' then
IQ <= IQ + 1;
end if;
end if;
if IQ = 11 then
fim <= '1';
else
fim <= '0';
end if;
contagem <= std_logic_vector(IQ);
end process;
end exemplo;
| mit | 7ea16844881f9559ea8322efa682f848 | 0.580208 | 3.428571 | false | false | false | false |
timofonic/PHDL | misc/projects/spartan_pcie_board/fpga/lx45t_pinout/ipcore_dir/pcie_core/simulation/dsport/pcie_bram_top_v6.vhd | 1 | 9,563 | -------------------------------------------------------------------------------
--
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Project : Spartan-6 Integrated Block for PCI Express
-- File : pcie_bram_top_v6.vhd
-- Description: BlockRAM top level module for Virtex6 PCIe Block
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity pcie_bram_top_v6 is
generic (
DEV_CAP_MAX_PAYLOAD_SUPPORTED : integer := 0;
VC0_TX_LASTPACKET : integer := 31;
TLM_TX_OVERHEAD : integer := 24;
TL_TX_RAM_RADDR_LATENCY : integer := 1;
TL_TX_RAM_RDATA_LATENCY : integer := 2;
TL_TX_RAM_WRITE_LATENCY : integer := 1;
VC0_RX_LIMIT : bit_vector := x"1FFF";
TL_RX_RAM_RADDR_LATENCY : integer := 1;
TL_RX_RAM_RDATA_LATENCY : integer := 2;
TL_RX_RAM_WRITE_LATENCY : integer := 1
);
port (
user_clk_i : in std_logic;
reset_i : in std_logic;
mim_tx_wen : in std_logic;
mim_tx_waddr : in std_logic_vector(12 downto 0);
mim_tx_wdata : in std_logic_vector(71 downto 0);
mim_tx_ren : in std_logic;
mim_tx_rce : in std_logic;
mim_tx_raddr : in std_logic_vector(12 downto 0);
mim_tx_rdata : out std_logic_vector(71 downto 0);
mim_rx_wen : in std_logic;
mim_rx_waddr : in std_logic_vector(12 downto 0);
mim_rx_wdata : in std_logic_vector(71 downto 0);
mim_rx_ren : in std_logic;
mim_rx_rce : in std_logic;
mim_rx_raddr : in std_logic_vector(12 downto 0);
mim_rx_rdata : out std_logic_vector(71 downto 0)
);
end pcie_bram_top_v6;
architecture v6_pcie of pcie_bram_top_v6 is
component pcie_brams_v6
generic (
NUM_BRAMS : integer;
RAM_RADDR_LATENCY : integer;
RAM_RDATA_LATENCY : integer;
RAM_WRITE_LATENCY : integer);
port (
user_clk_i : in std_logic;
reset_i : in std_logic;
wen : in std_logic;
waddr : in std_logic_vector(12 downto 0);
wdata : in std_logic_vector(71 downto 0);
ren : in std_logic;
rce : in std_logic;
raddr : in std_logic_vector(12 downto 0);
rdata : out std_logic_vector(71 downto 0));
end component;
-- TX calculations
function cols_tx (
constant CMPS : integer;
constant VC0_TX_LASTPACKET : integer;
constant TLM_TX_OVERHEAD : integer)
return integer is
variable MPS_BYTES : integer := 128;
variable BYTES_TX : integer := 0;
variable COLS_TX : integer := 1;
begin -- cols_tx
if (cmps = 0) then
MPS_BYTES := 128;
elsif (cmps = 1) then
MPS_BYTES := 256;
elsif (cmps = 2) then
MPS_BYTES := 512;
else
MPS_BYTES := 1024;
end if;
BYTES_TX := ((VC0_TX_LASTPACKET + 1) * (MPS_BYTES + TLM_TX_OVERHEAD));
if (BYTES_TX <= 4096) then
COLS_TX := 1;
elsif (BYTES_TX <= 8192) then
COLS_TX := 2;
elsif (BYTES_TX <= 16384) then
COLS_TX := 4;
elsif (BYTES_TX <= 32768) then
COLS_TX := 8;
else
COLS_TX := 18;
end if;
return COLS_TX;
end cols_tx;
FUNCTION to_integer (
val_in : bit_vector) RETURN integer IS
CONSTANT vctr : bit_vector(val_in'high-val_in'low DOWNTO 0) := val_in;
VARIABLE ret : integer := 0;
BEGIN
FOR index IN vctr'RANGE LOOP
IF (vctr(index) = '1') THEN
ret := ret + (2**index);
END IF;
END LOOP;
RETURN(ret);
END to_integer;
-- RX calculations
function cols_rx (
constant VC0_RX_LIMIT : integer)
return integer is
variable COLS_RX : integer := 1;
begin -- cols_rx
if (VC0_RX_LIMIT < 512) then -- X"0200"
COLS_RX := 1;
elsif (VC0_RX_LIMIT < 1024) then -- X"0400"
COLS_RX := 2;
elsif (VC0_RX_LIMIT < 2048) then -- X"0800"
COLS_RX := 4;
elsif (VC0_RX_LIMIT < 4096) then -- X"1000"
COLS_RX := 8;
else
COLS_RX := 18;
end if;
return COLS_RX;
end cols_rx;
constant ROWS_TX : integer := 1;
constant ROWS_RX : integer := 1;
-- Declare intermediate signals for referenced outputs
signal mim_tx_rdata_v6pcie1 : std_logic_vector(71 downto 0);
signal mim_rx_rdata_v6pcie0 : std_logic_vector(71 downto 0);
begin
-- Drive referenced outputs
mim_tx_rdata <= mim_tx_rdata_v6pcie1;
mim_rx_rdata <= mim_rx_rdata_v6pcie0;
-- process
-- begin
-- -- $display("[%t] %m ROWS_TX %0d COLS_TX %0d", now, to_stdlogic(ROWS_TX), to_stdlogicvector(COLS_TX, 13));
-- -- $display("[%t] %m ROWS_RX %0d COLS_RX %0d", now, to_stdlogic(ROWS_RX), to_stdlogicvector(COLS_RX, 13));
-- wait;
-- end process;
pcie_brams_tx : pcie_brams_v6
generic map (
NUM_BRAMS => cols_tx(DEV_CAP_MAX_PAYLOAD_SUPPORTED, VC0_TX_LASTPACKET, TLM_TX_OVERHEAD),
RAM_RADDR_LATENCY => TL_TX_RAM_RADDR_LATENCY,
RAM_RDATA_LATENCY => TL_TX_RAM_RDATA_LATENCY,
RAM_WRITE_LATENCY => TL_TX_RAM_WRITE_LATENCY
)
port map (
user_clk_i => user_clk_i,
reset_i => reset_i,
waddr => mim_tx_waddr,
wen => mim_tx_wen,
ren => mim_tx_ren,
rce => mim_tx_rce,
wdata => mim_tx_wdata,
raddr => mim_tx_raddr,
rdata => mim_tx_rdata_v6pcie1
);
pcie_brams_rx : pcie_brams_v6
generic map (
NUM_BRAMS => cols_rx(to_integer(VC0_RX_LIMIT)),
RAM_RADDR_LATENCY => TL_RX_RAM_RADDR_LATENCY,
RAM_RDATA_LATENCY => TL_RX_RAM_RDATA_LATENCY,
RAM_WRITE_LATENCY => TL_RX_RAM_WRITE_LATENCY
)
port map (
user_clk_i => user_clk_i,
reset_i => reset_i,
waddr => mim_rx_waddr,
wen => mim_rx_wen,
ren => mim_rx_ren,
rce => mim_rx_rce,
wdata => mim_rx_wdata,
raddr => mim_rx_raddr,
rdata => mim_rx_rdata_v6pcie0
);
end v6_pcie;
-- pcie_bram_top
| gpl-3.0 | 1450d102b982433014487fdff19f03fb | 0.522639 | 3.885819 | false | false | false | false |
Nixon-/VHDL_library | basic/nbit_XtoY_mux.vhd | 1 | 1,019 | Library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity nbit_XtoY_mux is
generic(
bitPerInput: integer:=2;
numInputs: integer:=4
);
port(
enable: in std_logic;
input:in std_logic_vector(bitPerInput*numInputs-1 downto 0);
output:out std_logic_vector(bitPerInput-1 downto 0);
selectors: in std_logic_vector(integer(log2(real(numInputs)))-1 downto 0)
);
end entity;
architecture primary of nbit_XtoY_mux is
type inputArray is array (numInputs-1 downto 0) of std_logic_vector(bitPerInput-1 downto 0);
signal inputs: inputArray;
begin
process(input,enable,inputs,selectors) begin
if(enable ='1') then
for i in 0 to numInputs-1 loop
inputs(i) <= input(((i+1)*bitPerInput)-1 downto i*bitPerInput);
end loop;
output <= inputs(to_integer(unsigned(selectors)));
else
output <= (others=>'0');
for i in 0 to numInputs-1 loop
inputs(i) <= (others=>'0');
end loop;
end if;
end process;
end primary;
| gpl-2.0 | c14463a1a65a16206771578f703f97f5 | 0.680079 | 2.997059 | false | false | false | false |
Nixon-/VHDL_library | memory/RAM_NxI.vhd | 1 | 975 | Library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity RAM_NxI is
generic(
numberAddress: integer:=1024;
entrySize: integer:=8
);
port(
enable,clk,rd0_wr1: in std_logic;
address: in std_logic_vector((integer(log2(real(numberAddress))))-1 downto 0);
dataIN: in std_logic_vector(entrySize-1 downto 0);
dataOUT: out std_logic_vector(entrySize-1 downto 0)
);
end RAM_NxI;
architecture primary of RAM_NxI is
type RAM is array (numberAddress-1 downto 0) of integer range 0 to (2**entrySize)-1;
begin
process(clk,rd0_wr1,enable,address,dataIN)
variable storage: RAM;
begin
if(clk' event and clk ='1') then
if(enable = '1') then
if(rd0_wr1 = '0') then
dataOUT <= std_logic_vector(to_unsigned(storage(to_integer(unsigned(address))),entrySize));
elsif(rd0_wr1 = '1') then
storage(to_integer(unsigned(address))) := to_integer(unsigned(dataIN));
end if;
end if;
end if;
end process;
end primary;
| gpl-2.0 | 17f77de2da8bee4fc3b09a95498e007c | 0.705641 | 2.834302 | false | false | false | false |
Nixon-/VHDL_library | IO/debounce.vhd | 1 | 1,133 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity debounce is
generic(timeOut: integer:=2000000);
port(
input: in std_logic;
clk: in std_logic;
output: out std_logic;
reset: in std_logic
);
end debounce;
architecture Behavioral of debounce is
signal capture: std_logic;
begin
count: process(input,clk)
variable count: integer range 0 to timeOut*2:=0;
variable inputCapture: std_logic;
begin
if(reset = '1') then
count := 0;
inputCapture <= '0';
output <= '0';
elsif(rising_edge(clk)) then
if(count = 0) then
inputCapture := input;
capture <= '1';
else
capture <= '0';
inputCapture := inputCapture;
end if;
if(capture = '1' AND count = timeOut AND input = inputCapture) then
output <= inputCapture;
count := 0;
capture <= '0';
elsif (capture = '1' and count = timeOut and not(input = inputCapture)) then
count := 0;
capture <= '0';
output <= input;
elsif(capture = '1') then
capture <= capture;
count := count+1;
output <= '0';
else
count := count;
output <= ;
capture <= '0';
end if;
end if;
end process;
end Behavioral;
| gpl-2.0 | 8e17e50af7be07505ac031440180e081 | 0.627538 | 3.129834 | false | false | false | false |
masaruohashi/tic-tac-toe | modem/modem_transmissao.vhd | 1 | 3,360 | -- modem_transmissao.vhd
--
-- componente que modela a transmissao de dados do modem
-- => usar para os testes de simulacao do projeto final
--
-- ATENCAO:
-- mudar comentarios nas linhas 90 ou 91 para selecionar contagem de atraso do CTS (sintese vs simulacao)
--
-- Labdig (3o quadrimestre de 2017)
library IEEE;
use IEEE.std_logic_1164.all;
entity modem_transmissao is
port ( clock, reset, DTR, RTS, TD: in STD_LOGIC;
CTS, TC: out STD_LOGIC );
end;
architecture modem_transmissao of modem_transmissao is
type estados_tx is (inicial_tx, espera_rts, ativa_tempo_cts, espera_tempo_cts, ativa_cts, em_transmissao);
signal Eatual, Eprox: estados_tx;
signal clear,enable,fim: STD_LOGIC;
begin
-- state memory
process (RESET, CLOCK)
begin
if RESET = '1' then
Eatual <= inicial_tx;
elsif CLOCK'event and CLOCK = '1' then
Eatual <= Eprox;
end if;
end process;
-- next-state logic
process (DTR, RTS, fim, Eatual)
variable contagem : integer range 0 to 9999;
begin
case Eatual is
when inicial_tx => if DTR='0' then Eprox <= espera_rts;
else Eprox <= inicial_tx;
end if;
when espera_rts => if DTR='1' then Eprox <= inicial_tx;
elsif RTS='0' then Eprox <= ativa_tempo_cts;
else Eprox <= espera_rts;
end if;
when ativa_tempo_cts => Eprox <= espera_tempo_cts;
when espera_tempo_cts => if fim='0' then Eprox <= espera_tempo_cts;
else Eprox <= ativa_cts;
end if;
when ativa_cts => Eprox <= em_transmissao;
when em_transmissao => if DTR='1' then Eprox <= inicial_tx;
elsif RTS='0' then Eprox <= em_transmissao;
else Eprox <= espera_rts;
end if;
when others => Eprox <= inicial_tx;
end case;
end process;
-- saidas
with Eatual select
CTS <= '0' when ativa_cts|em_transmissao, '1' when others;
with Eatual select
TC <= TD when em_transmissao, '0' when others;
-- sinais de controle da contagem para atraso do CTS
with Eatual select
clear <= '1' when ativa_cts, '0' when others;
with Eatual select
enable <= '1' when espera_tempo_cts, '0' when others;
-- contagem (atraso do CTS)
process (clear,enable,CLOCK)
variable contagem: integer range 0 to 9999;
begin
if CLOCK'event and CLOCK = '1' then
if clear='1' then contagem := 0;
elsif enable='1' then contagem := contagem+1;
else contagem := contagem;
end if;
end if;
-- if contagem = 9999 then fim<='1'; -- para clock de 50MHz -> atraso de 20ns x 10.000=200us
if contagem = 9 then fim<='1'; -- para teste de simulacao (atraso de 10 clocks)
else fim<='0';
end if;
end process;
end modem_transmissao;
| mit | 5cd632e44958d0ed63dd5d8b5c35e57f | 0.51756 | 4.173913 | false | false | false | false |
timofonic/PHDL | misc/projects/spartan_pcie_board/fpga/lx45t_pinout/ipcore_dir/pcie_core/simulation/dsport/pci_exp_usrapp_cfg.vhd | 1 | 5,831 | -------------------------------------------------------------------------------
--
-- (c) Copyright 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Project : Spartan-6 Integrated Block for PCI Express
-- File : pci_exp_usrapp_cfg.vhd
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.test_interface.all;
entity pci_exp_usrapp_cfg is
port (
cfg_do : in std_logic_vector((32 - 1) downto 0);
cfg_di : out std_logic_vector((32 - 1) downto 0);
cfg_byte_en_n : out std_logic_vector(((32/8) - 1) downto 0);
cfg_dwaddr : out std_logic_vector((10 - 1) downto 0);
cfg_wr_en_n : out std_logic;
cfg_rd_en_n : out std_logic;
cfg_rd_wr_done_n : in std_logic;
cfg_err_cor_n : out std_logic;
cfg_err_ur_n : out std_logic;
cfg_err_ecrc_n : out std_logic;
cfg_err_cpl_timeout_n : out std_logic;
cfg_err_cpl_abort_n : out std_logic;
cfg_err_cpl_unexpect_n : out std_logic;
cfg_err_posted_n : out std_logic;
cfg_err_tlp_cpl_header : out std_logic_vector(( 48 - 1) downto 0);
cfg_interrupt_n : out std_logic;
cfg_interrupt_rdy_n : in std_logic;
cfg_turnoff_ok_n : out std_logic;
cfg_to_turnoff_n : in std_logic;
cfg_pm_wake_n : out std_logic;
cfg_bus_number : in std_logic_vector((8 -1) downto 0);
cfg_device_number : in std_logic_vector((5 - 1) downto 0);
cfg_function_number : in std_logic_vector((3 - 1) downto 0);
cfg_status : in std_logic_vector((16 - 1) downto 0);
cfg_command : in std_logic_vector((16 - 1) downto 0);
cfg_dstatus : in std_logic_vector((16 - 1) downto 0);
cfg_dcommand : in std_logic_vector((16 - 1) downto 0);
cfg_lstatus : in std_logic_vector((16 - 1) downto 0);
cfg_lcommand : in std_logic_vector((16 - 1) downto 0);
cfg_pcie_link_state_n : in std_logic_vector((3 - 1) downto 0);
cfg_trn_pending_n : out std_logic;
trn_clk : in std_logic;
trn_reset_n : in std_logic
);
end pci_exp_usrapp_cfg;
architecture rtl of pci_exp_usrapp_cfg is
begin
-- Signals not used by testbench at this point
cfg_err_cor_n <= '1';
cfg_err_ur_n <= '1';
cfg_err_ecrc_n <= '1';
cfg_err_cpl_timeout_n <= '1';
cfg_err_cpl_abort_n <= '1';
cfg_err_cpl_unexpect_n <= '1';
cfg_err_posted_n <= '0';
cfg_interrupt_n <= '1';
cfg_turnoff_ok_n <= '1';
cfg_err_tlp_cpl_header <= (others => '0');
cfg_pm_wake_n <= '1';
cfg_trn_pending_n <= '0';
------------------
-- The following signals are driven by processes defined in
-- test_package and called from tests.vhd
------------------
-- Inputs to CFG procecces / Outputs of core
cfg_rdwr_int.trn_clk <= trn_clk;
cfg_rdwr_int.trn_reset_n <= trn_reset_n;
cfg_rdwr_int.cfg_rd_wr_done_n <= cfg_rd_wr_done_n;
cfg_rdwr_int.cfg_do <= cfg_do;
-- Outputs of CFG processes / Inputs to core
cfg_dwaddr <= cfg_rdwr_int.cfg_dwaddr;
cfg_di <= cfg_rdwr_int.cfg_di;
cfg_byte_en_n <= cfg_rdwr_int.cfg_byte_en_n;
cfg_wr_en_n <= cfg_rdwr_int.cfg_wr_en_n;
cfg_rd_en_n <= cfg_rdwr_int.cfg_rd_en_n;
end; -- pci_exp_usrapp_cfg
| gpl-3.0 | bb5cb2731278e8da1913fa43e0a6eb02 | 0.600583 | 3.51901 | false | false | false | false |
JavierRizzoA/Sacagawea | sources/registers/Register8.vhd | 1 | 617 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Register8 is
Port (
d : in STD_LOGIC_VECTOR(7 downto 0) := X"00"; --Input.
load : in STD_LOGIC; --Load/Enable.
clr : in STD_LOGIC; --Async clear.
clk : in STD_LOGIC; --Clock.
q : out STD_LOGIC_VECTOR(7 downto 0) := X"00" --Output
);
end Register8;
architecture Behavioral of Register8 is
begin
process(clk, clr)
begin
if rising_edge(clk) then
if clr = '1' then
q <= "00000000";
elsif load = '1' then
q <= d;
end if;
end if;
end process;
end Behavioral; | mit | a508ad5e53c52b2fe3c353bf0cb5645a | 0.557536 | 3.247368 | false | false | false | false |
JavierRizzoA/Sacagawea | sources/Divisor.vhd | 1 | 1,723 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:31:04 06/03/2016
-- Design Name:
-- Module Name: Divisor - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_arith.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Divisor is
port(M, Q : in std_logic_vector(7 downto 0);
S : out std_logic_vector (7 downto 0));
end Divisor;
architecture Behavioral of Divisor is
begin
process(M, Q)
variable A, B : std_logic_vector(7 downto 0);
begin
A := "00000000";
B := Q;
for I in 0 to 7 loop
A := to_stdlogicvector(to_bitvector(A) sll 1);
A(0) := B(7);
B := to_stdlogicvector(to_bitvector(B) sll 1);
A := SIGNED(A) - SIGNED(M);
if SIGNED(A) < conv_signed(0, 7) then
B(0) := '0';
A := UNSIGNED(A) + UNSIGNED(M);
else
B(0) := '1';
end if;
report "ITER: "&integer'image(I);
for t in 0 to 7 loop
report "A("&integer'image(t)&") value is" &
std_logic'image(A(t));
end loop;
for t in 0 to 7 loop
report "B("&integer'image(t)&") value is" &
std_logic'image(B(t));
end loop;
end loop;
S <= B;
end process;
end Behavioral;
| mit | 457372856f352af3e813000cafc7db7b | 0.571097 | 3.257089 | false | false | false | false |
JavierRizzoA/Sacagawea | test_procesador_2016.vhd | 1 | 24,561 | -- TestBench Template
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY testbench IS
END testbench;
ARCHITECTURE behavior OF testbench IS
-- Component Declaration
COMPONENT Sacagawea
PORT(
clk : in STD_LOGIC;
senal_rst : in STD_LOGIC;
switches_sal : in STD_LOGIC_VECTOR (7 downto 0);
leds_in : out STD_LOGIC_VECTOR (7 downto 0);
bus_datos_memtoregs : out std_logic_vector(7 downto 0);
bus_datos_mbrtomem : out std_logic_vector(7 downto 0);
senal_rw : out std_logic;
conta : out std_logic_vector(24 downto 0);
salida_ip : out std_logic_vector(11 downto 0);
salida_ir : out std_logic_vector(7 downto 0);
salida_ar : out std_logic_vector(11 downto 0)
);
END COMPONENT;
--inputs
signal clk : std_logic := '0';
signal senal_rst : std_logic := '0';
signal switches_sal : std_logic_vector(7 downto 0) := "00000000";
-- outputs
signal leds_in : std_logic_vector(7 downto 0) := "00000000";
signal bus_datos_memtoregs : std_logic_vector(7 downto 0);
signal bus_datos_mbrtomem : std_logic_vector(7 downto 0);
signal senal_rw : std_logic := '0';
signal conta : std_logic_vector(24 downto 0);
signal salida_ip : std_logic_vector(11 downto 0);
signal salida_ir : std_logic_vector(7 downto 0);
signal salida_ar : std_logic_vector(11 downto 0);
BEGIN
-- Component Instantiation
uut: Sacagawea PORT MAP(
clk => clk,
senal_rst => senal_rst,
switches_sal => switches_sal,
leds_in => leds_in,
bus_datos_memtoregs => bus_datos_memtoregs,
bus_datos_mbrtomem => bus_datos_mbrtomem,
senal_rw => senal_rw,
conta => conta,
salida_ip => salida_ip,
salida_ir => salida_ir,
salida_ar => salida_ar
);
-- Test Bench Statements
tb : PROCESS
BEGIN
-- ya funciona cargar numero directo a RAM :)
-- ya carga un numero a LEDS
-- No funciona el SLT
-- Error con switches, no funciona
wait for 100 ns; -- wait until global set/reset completes
clk <= '0';
switches_sal <= X"53";
wait for 100 ns;
clk <= '1';
wait for 100 ns;
clk <= '0';
wait for 100 ns;
clk <= '1';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
clk <= '0';
senal_rst <= '0';
wait for 100 ns;
clk <= '1';
senal_rst <= '0';
wait for 100 ns;
wait; -- will wait forever
END PROCESS tb;
-- End Test Bench
END;
| mit | 15f82c1492f45066b36fa5616a65ccce | 0.38268 | 2.940381 | false | false | false | false |
timofonic/PHDL | misc/projects/spartan_pcie_board/fpga/lx45t_pinout/ipcore_dir/pcie_core/simulation/functional/sys_clk_gen_ds.vhd | 1 | 3,446 | -------------------------------------------------------------------------------
--
-- (c) Copyright 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Project : Spartan-6 Integrated Block for PCI Express
-- File : sys_clk_gen_ds.vhd
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity sys_clk_gen_ds is
generic
(
HALFCYCLE : integer := 500;
OFFSET : integer := 0
);
port
(
sys_clk_p : out std_logic;
sys_clk_n : out std_logic
);
end sys_clk_gen_ds;
architecture sim of sys_clk_gen_ds is
component sys_clk_gen is
generic
(
HALFCYCLE : integer := 500;
OFFSET : integer := 0
);
port
(
sys_clk : out std_logic
);
end component sys_clk_gen;
signal sys_clk_c : std_logic;
begin
clk_gen : sys_clk_gen
generic map
(
HALFCYCLE => HALFCYCLE,
OFFSET => OFFSET
)
port map
(
sys_clk => sys_clk_c
);
sys_clk_p <= sys_clk_c;
sys_clk_n <= not sys_clk_c;
end; -- sys_clk_gen
| gpl-3.0 | 4d37962b962048a9971712081e3c1623 | 0.638131 | 4.126946 | false | false | false | false |
masaruohashi/tic-tac-toe | interface_jogo/memoria_caractere.vhd | 1 | 4,699 | -- VHDL de uma memoria do jogo da velha
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity memoria_caractere is
port(
clock : in std_logic;
reset : in std_logic;
leitura : in std_logic;
escrita : in std_logic;
jogador : in std_logic;
enable_fim : in std_logic;
mensagem_fim : in std_logic_vector(48 downto 0);
endereco_leitura : in std_logic_vector(6 downto 0);
endereco_escrita : in std_logic_vector(6 downto 0);
saida : out std_logic_vector(6 downto 0)
);
end memoria_caractere;
architecture estrutural of memoria_caractere is
type memoria is array (0 to 76) of std_logic_vector(6 downto 0);
constant c_enter: std_logic_vector(6 downto 0) := "0001101";
constant c_espaco: std_logic_vector(6 downto 0) := "0100000";
constant c_hifen: std_logic_vector(6 downto 0) := "0101101";
constant c_mais: std_logic_vector(6 downto 0) := "0101011";
constant c_pipe: std_logic_vector(6 downto 0) := "1111100";
constant c_x: std_logic_vector(6 downto 0) := "1011000";
constant c_o: std_logic_vector(6 downto 0) := "1001111";
constant c_esc: std_logic_vector(6 downto 0) := "0011011";
constant c_zero: std_logic_vector(6 downto 0) := "0110000";
constant c_dois: std_logic_vector(6 downto 0) := "0110010";
constant c_abrechaves: std_logic_vector(6 downto 0) := "1011011";
constant c_pontovirgula: std_logic_vector(6 downto 0) := "0111011";
constant c_J: std_logic_vector(6 downto 0) := "1001010";
constant c_H: std_logic_vector(6 downto 0) := "1001000";
signal memoria_tabuleiro: memoria := (c_esc, c_abrechaves, c_dois, c_J,
c_esc, c_abrechaves, c_zero, c_pontovirgula, c_zero, c_H,
c_espaco, c_espaco, c_espaco, c_pipe, c_espaco, c_espaco, c_espaco, c_pipe, c_espaco, c_espaco, c_espaco, c_enter,
c_hifen, c_hifen, c_hifen, c_mais, c_hifen, c_hifen, c_hifen, c_mais, c_hifen, c_hifen, c_hifen, c_enter,
c_espaco, c_espaco, c_espaco, c_pipe, c_espaco, c_espaco, c_espaco, c_pipe, c_espaco, c_espaco, c_espaco, c_enter,
c_hifen, c_hifen, c_hifen, c_mais, c_hifen, c_hifen, c_hifen, c_mais, c_hifen, c_hifen, c_hifen, c_enter,
c_espaco, c_espaco, c_espaco, c_pipe, c_espaco, c_espaco, c_espaco, c_pipe, c_espaco, c_espaco, c_espaco, c_enter,
c_espaco, c_espaco, c_espaco, c_espaco, c_espaco, c_espaco, c_espaco);
begin
process (clock, reset, leitura, escrita, jogador)
begin
if reset='1' then
memoria_tabuleiro <= (c_esc, c_abrechaves, c_dois, c_J,
c_esc, c_abrechaves, c_zero, c_pontovirgula, c_zero, c_H,
c_espaco, c_espaco, c_espaco, c_pipe, c_espaco, c_espaco, c_espaco, c_pipe, c_espaco, c_espaco, c_espaco, c_enter,
c_hifen, c_hifen, c_hifen, c_mais, c_hifen, c_hifen, c_hifen, c_mais, c_hifen, c_hifen, c_hifen, c_enter,
c_espaco, c_espaco, c_espaco, c_pipe, c_espaco, c_espaco, c_espaco, c_pipe, c_espaco, c_espaco, c_espaco, c_enter,
c_hifen, c_hifen, c_hifen, c_mais, c_hifen, c_hifen, c_hifen, c_mais, c_hifen, c_hifen, c_hifen, c_enter,
c_espaco, c_espaco, c_espaco, c_pipe, c_espaco, c_espaco, c_espaco, c_pipe, c_espaco, c_espaco, c_espaco, c_enter,
c_espaco, c_espaco, c_espaco, c_espaco, c_espaco, c_espaco, c_espaco);
elsif clock'event and clock='1' then
if leitura='1' then
saida <= memoria_tabuleiro(to_integer(unsigned(endereco_leitura)));
elsif escrita='1' then
if jogador='0' then
memoria_tabuleiro(to_integer(unsigned(endereco_escrita))) <= c_x;
else
memoria_tabuleiro(to_integer(unsigned(endereco_escrita))) <= c_o;
end if;
elsif enable_fim='1' then
memoria_tabuleiro(70) <= mensagem_fim(48 downto 42);
memoria_tabuleiro(71) <= mensagem_fim(41 downto 35);
memoria_tabuleiro(72) <= mensagem_fim(34 downto 28);
memoria_tabuleiro(73) <= mensagem_fim(27 downto 21);
memoria_tabuleiro(74) <= mensagem_fim(20 downto 14);
memoria_tabuleiro(75) <= mensagem_fim(13 downto 7);
memoria_tabuleiro(76) <= mensagem_fim(6 downto 0);
else
memoria_tabuleiro(70 to 76) <= (others => c_espaco);
end if;
end if;
end process;
end estrutural;
| mit | f0fc9f28fb2121e8aad25e7d96114b3c | 0.5814 | 3.049319 | false | false | false | false |
Pinwino/dbg_ohwr | debugger_gw/fmc-delay/top/synthesis_descriptor.vhd | 1 | 1,804 | -------------------------------------------------------------------------------
-- Title : Wishbone Debugger SDB descriptor
-- Project : FMC DEL 1ns 4cha-stand-alone application (fmc-delay-1ns-4cha-sa)
-------------------------------------------------------------------------------
-- File : synthesis_descriptor.vhd
-- Author : Jose Jimenez <[email protected]>
-- Company : University of Granada
-- Created : 2014-07-31
-- Last update: 2014-07-36
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: SDB descriptor for the WB Debugger and top level of the FMC used
-- on a SPEC carrier.
-- Contains synthesis & source repository information.
-- Warning: this file is modified whenever a synthesis is executed.
-------------------------------------------------------------------------------
library ieee;
use ieee.STD_LOGIC_1164.all;
use work.wishbone_pkg.all;
package synthesis_descriptor is
constant c_sdb_FMC_DEL_synthesis_info : t_sdb_synthesis :=
(
syn_module_name => "spec-fine-delay ",
syn_commit_id => "00000000000000000000000000000000",
syn_tool_name => "ISE ",
syn_tool_version => x"00000147",
syn_date => x"20140731",
syn_username => "jjimenez ");
constant c_sdb_repo_url : t_sdb_repo_url :=
(
repo_url => "git://ohwr.org/fmc-projects/fmc-delay-1ns-8cha-sa.git "
);
constant c_sdb_synthesis_info : t_sdb_synthesis :=
(
syn_module_name => "wb-debugger ",
syn_commit_id => "00000000000000000000000000000000",
syn_tool_name => "ISE ",
syn_tool_version => x"00000147",
syn_date => x"20140731",
syn_username => "jjimenez ");
end package synthesis_descriptor;
| gpl-3.0 | 9449a8754c59789145cc47b227ccaa95 | 0.53714 | 3.973568 | false | false | false | false |
timofonic/PHDL | misc/projects/spartan_pcie_board/fpga/lx45t_pinout/ipcore_dir/ddr3_controller/user_design/rtl/memc3_wrapper.vhd | 2 | 46,755 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.9
-- \ \ Application : MIG
-- / / Filename : memc3_wrapper.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:59 $
-- \ \ / \ Date Created :
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : This module instantiates mcb_raw_wrapper module.
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity memc3_wrapper is
generic (
C_MEMCLK_PERIOD : integer := 2500;
C_P0_MASK_SIZE : integer := 4;
C_P0_DATA_PORT_SIZE : integer := 32;
C_P1_MASK_SIZE : integer := 4;
C_P1_DATA_PORT_SIZE : integer := 32;
C_ARB_NUM_TIME_SLOTS : integer := 12;
C_ARB_TIME_SLOT_0 : bit_vector := "000";
C_ARB_TIME_SLOT_1 : bit_vector := "000";
C_ARB_TIME_SLOT_2 : bit_vector := "000";
C_ARB_TIME_SLOT_3 : bit_vector := "000";
C_ARB_TIME_SLOT_4 : bit_vector := "000";
C_ARB_TIME_SLOT_5 : bit_vector := "000";
C_ARB_TIME_SLOT_6 : bit_vector := "000";
C_ARB_TIME_SLOT_7 : bit_vector := "000";
C_ARB_TIME_SLOT_8 : bit_vector := "000";
C_ARB_TIME_SLOT_9 : bit_vector := "000";
C_ARB_TIME_SLOT_10 : bit_vector := "000";
C_ARB_TIME_SLOT_11 : bit_vector := "000";
C_MEM_TRAS : integer := 45000;
C_MEM_TRCD : integer := 12500;
C_MEM_TREFI : integer := 7800000;
C_MEM_TRFC : integer := 127500;
C_MEM_TRP : integer := 12500;
C_MEM_TWR : integer := 15000;
C_MEM_TRTP : integer := 7500;
C_MEM_TWTR : integer := 7500;
C_MEM_ADDR_ORDER : string :="ROW_BANK_COLUMN";
C_MEM_TYPE : string :="DDR2";
C_MEM_DENSITY : string :="1Gb";
C_NUM_DQ_PINS : integer := 4;
C_MEM_BURST_LEN : integer := 8;
C_MEM_CAS_LATENCY : integer := 5;
C_MEM_ADDR_WIDTH : integer := 14;
C_MEM_BANKADDR_WIDTH : integer := 3;
C_MEM_NUM_COL_BITS : integer := 11;
C_MEM_DDR1_2_ODS : string := "FULL";
C_MEM_DDR2_RTT : string := "50OHMS";
C_MEM_DDR2_DIFF_DQS_EN : string := "YES";
C_MEM_DDR2_3_PA_SR : string := "FULL";
C_MEM_DDR2_3_HIGH_TEMP_SR : string := "NORMAL";
C_MEM_DDR3_CAS_LATENCY : integer:= 7;
C_MEM_DDR3_CAS_WR_LATENCY : integer:= 5;
C_MEM_DDR3_ODS : string := "DIV6";
C_MEM_DDR3_RTT : string := "DIV2";
C_MEM_DDR3_AUTO_SR : string := "ENABLED";
C_MEM_MOBILE_PA_SR : string := "FULL";
C_MEM_MDDR_ODS : string := "FULL";
C_MC_CALIB_BYPASS : string := "NO";
C_LDQSP_TAP_DELAY_VAL : integer := 0;
C_UDQSP_TAP_DELAY_VAL : integer := 0;
C_LDQSN_TAP_DELAY_VAL : integer := 0;
C_UDQSN_TAP_DELAY_VAL : integer := 0;
C_DQ0_TAP_DELAY_VAL : integer := 0;
C_DQ1_TAP_DELAY_VAL : integer := 0;
C_DQ2_TAP_DELAY_VAL : integer := 0;
C_DQ3_TAP_DELAY_VAL : integer := 0;
C_DQ4_TAP_DELAY_VAL : integer := 0;
C_DQ5_TAP_DELAY_VAL : integer := 0;
C_DQ6_TAP_DELAY_VAL : integer := 0;
C_DQ7_TAP_DELAY_VAL : integer := 0;
C_DQ8_TAP_DELAY_VAL : integer := 0;
C_DQ9_TAP_DELAY_VAL : integer := 0;
C_DQ10_TAP_DELAY_VAL : integer := 0;
C_DQ11_TAP_DELAY_VAL : integer := 0;
C_DQ12_TAP_DELAY_VAL : integer := 0;
C_DQ13_TAP_DELAY_VAL : integer := 0;
C_DQ14_TAP_DELAY_VAL : integer := 0;
C_DQ15_TAP_DELAY_VAL : integer := 0;
C_SKIP_IN_TERM_CAL : integer := 0;
C_SKIP_DYNAMIC_CAL : integer := 0;
C_SIMULATION : string := "FALSE";
C_MC_CALIBRATION_MODE : string := "CALIBRATION";
C_MC_CALIBRATION_DELAY : string := "QUARTER";
C_CALIB_SOFT_IP : string := "TRUE"
);
port
(
-- high-speed PLL clock interface
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
async_rst : in std_logic;
--User Port0 Interface Signals
p0_cmd_clk : in std_logic;
p0_cmd_en : in std_logic;
p0_cmd_instr : in std_logic_vector(2 downto 0) ;
p0_cmd_bl : in std_logic_vector(5 downto 0) ;
p0_cmd_byte_addr : in std_logic_vector(29 downto 0) ;
p0_cmd_empty : out std_logic;
p0_cmd_full : out std_logic;
-- Data Wr Port signals
p0_wr_clk : in std_logic;
p0_wr_en : in std_logic;
p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 downto 0) ;
p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0) ;
p0_wr_full : out std_logic;
p0_wr_empty : out std_logic;
p0_wr_count : out std_logic_vector(6 downto 0) ;
p0_wr_underrun : out std_logic;
p0_wr_error : out std_logic;
--Data Rd Port signals
p0_rd_clk : in std_logic;
p0_rd_en : in std_logic;
p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0) ;
p0_rd_full : out std_logic;
p0_rd_empty : out std_logic;
p0_rd_count : out std_logic_vector(6 downto 0) ;
p0_rd_overflow : out std_logic;
p0_rd_error : out std_logic;
-- memory interface signals
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
mcb3_dram_a : out std_logic_vector(C_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
-- mcb3_dram_odt : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dq : inout std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_reset_n : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
-- Calibration signals
mcb_drp_clk : in std_logic;
calib_done : out std_logic;
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end entity;
architecture acch of memc3_wrapper is
component mcb_raw_wrapper IS
GENERIC (
C_MEMCLK_PERIOD : integer;
C_PORT_ENABLE : std_logic_vector(5 downto 0);
C_MEM_ADDR_ORDER : string;
C_ARB_NUM_TIME_SLOTS : integer;
C_ARB_TIME_SLOT_0 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_1 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_2 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_3 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_4 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_5 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_6 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_7 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_8 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_9 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_10 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_11 : bit_vector(17 downto 0);
C_PORT_CONFIG : string;
C_MEM_TRAS : integer;
C_MEM_TRCD : integer;
C_MEM_TREFI : integer;
C_MEM_TRFC : integer;
C_MEM_TRP : integer;
C_MEM_TWR : integer;
C_MEM_TRTP : integer;
C_MEM_TWTR : integer;
C_NUM_DQ_PINS : integer;
C_MEM_TYPE : string;
C_MEM_DENSITY : string;
C_MEM_BURST_LEN : integer;
C_MEM_CAS_LATENCY : integer;
C_MEM_ADDR_WIDTH : integer;
C_MEM_BANKADDR_WIDTH : integer;
C_MEM_NUM_COL_BITS : integer;
C_MEM_DDR3_CAS_LATENCY : integer;
C_MEM_MOBILE_PA_SR : string;
C_MEM_DDR1_2_ODS : string;
C_MEM_DDR3_ODS : string;
C_MEM_DDR2_RTT : string;
C_MEM_DDR3_RTT : string;
C_MEM_MDDR_ODS : string;
C_MEM_DDR2_DIFF_DQS_EN : string;
C_MEM_DDR2_3_PA_SR : string;
C_MEM_DDR3_CAS_WR_LATENCY : integer;
C_MEM_DDR3_AUTO_SR : string;
C_MEM_DDR2_3_HIGH_TEMP_SR : string;
C_MEM_DDR3_DYN_WRT_ODT : string;
C_MC_CALIB_BYPASS : string;
C_MC_CALIBRATION_RA : bit_vector(15 DOWNTO 0);
C_MC_CALIBRATION_BA : bit_vector(2 DOWNTO 0);
C_CALIB_SOFT_IP : string;
C_MC_CALIBRATION_CA : bit_vector(11 DOWNTO 0);
C_MC_CALIBRATION_CLK_DIV : integer;
C_MC_CALIBRATION_MODE : string;
C_MC_CALIBRATION_DELAY : string;
LDQSP_TAP_DELAY_VAL : integer;
UDQSP_TAP_DELAY_VAL : integer;
LDQSN_TAP_DELAY_VAL : integer;
UDQSN_TAP_DELAY_VAL : integer;
DQ0_TAP_DELAY_VAL : integer;
DQ1_TAP_DELAY_VAL : integer;
DQ2_TAP_DELAY_VAL : integer;
DQ3_TAP_DELAY_VAL : integer;
DQ4_TAP_DELAY_VAL : integer;
DQ5_TAP_DELAY_VAL : integer;
DQ6_TAP_DELAY_VAL : integer;
DQ7_TAP_DELAY_VAL : integer;
DQ8_TAP_DELAY_VAL : integer;
DQ9_TAP_DELAY_VAL : integer;
DQ10_TAP_DELAY_VAL : integer;
DQ11_TAP_DELAY_VAL : integer;
DQ12_TAP_DELAY_VAL : integer;
DQ13_TAP_DELAY_VAL : integer;
DQ14_TAP_DELAY_VAL : integer;
DQ15_TAP_DELAY_VAL : integer;
C_P0_MASK_SIZE : integer;
C_P0_DATA_PORT_SIZE : integer;
C_P1_MASK_SIZE : integer;
C_P1_DATA_PORT_SIZE : integer;
C_SIMULATION : string ;
C_SKIP_IN_TERM_CAL : integer;
C_SKIP_DYNAMIC_CAL : integer;
C_SKIP_DYN_IN_TERM : integer;
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0)
);
PORT (
-- HIGH-SPEED PLL clock interface
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
sys_rst : in std_logic;
p0_arb_en : in std_logic;
p0_cmd_clk : in std_logic;
p0_cmd_en : in std_logic;
p0_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p0_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p0_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p0_cmd_empty : out std_logic;
p0_cmd_full : out std_logic;
p0_wr_clk : in std_logic;
p0_wr_en : in std_logic;
p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 DOWNTO 0);
p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 DOWNTO 0);
p0_wr_full : out std_logic;
p0_wr_empty : out std_logic;
p0_wr_count : out std_logic_vector(6 DOWNTO 0);
p0_wr_underrun : out std_logic;
p0_wr_error : out std_logic;
p0_rd_clk : in std_logic;
p0_rd_en : in std_logic;
p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 DOWNTO 0);
p0_rd_full : out std_logic;
p0_rd_empty : out std_logic;
p0_rd_count : out std_logic_vector(6 DOWNTO 0);
p0_rd_overflow : out std_logic;
p0_rd_error : out std_logic;
p1_arb_en : in std_logic;
p1_cmd_clk : in std_logic;
p1_cmd_en : in std_logic;
p1_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p1_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p1_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p1_cmd_empty : out std_logic;
p1_cmd_full : out std_logic;
p1_wr_clk : in std_logic;
p1_wr_en : in std_logic;
p1_wr_mask : in std_logic_vector(C_P1_MASK_SIZE - 1 DOWNTO 0);
p1_wr_data : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 DOWNTO 0);
p1_wr_full : out std_logic;
p1_wr_empty : out std_logic;
p1_wr_count : out std_logic_vector(6 DOWNTO 0);
p1_wr_underrun : out std_logic;
p1_wr_error : out std_logic;
p1_rd_clk : in std_logic;
p1_rd_en : in std_logic;
p1_rd_data : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 DOWNTO 0);
p1_rd_full : out std_logic;
p1_rd_empty : out std_logic;
p1_rd_count : out std_logic_vector(6 DOWNTO 0);
p1_rd_overflow : out std_logic;
p1_rd_error : out std_logic;
p2_arb_en : in std_logic;
p2_cmd_clk : in std_logic;
p2_cmd_en : in std_logic;
p2_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p2_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p2_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p2_cmd_empty : out std_logic;
p2_cmd_full : out std_logic;
p2_wr_clk : in std_logic;
p2_wr_en : in std_logic;
p2_wr_mask : in std_logic_vector(3 DOWNTO 0);
p2_wr_data : in std_logic_vector(31 DOWNTO 0);
p2_wr_full : out std_logic;
p2_wr_empty : out std_logic;
p2_wr_count : out std_logic_vector(6 DOWNTO 0);
p2_wr_underrun : out std_logic;
p2_wr_error : out std_logic;
p2_rd_clk : in std_logic;
p2_rd_en : in std_logic;
p2_rd_data : out std_logic_vector(31 DOWNTO 0);
p2_rd_full : out std_logic;
p2_rd_empty : out std_logic;
p2_rd_count : out std_logic_vector(6 DOWNTO 0);
p2_rd_overflow : out std_logic;
p2_rd_error : out std_logic;
p3_arb_en : in std_logic;
p3_cmd_clk : in std_logic;
p3_cmd_en : in std_logic;
p3_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p3_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p3_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p3_cmd_empty : out std_logic;
p3_cmd_full : out std_logic;
p3_wr_clk : in std_logic;
p3_wr_en : in std_logic;
p3_wr_mask : in std_logic_vector(3 DOWNTO 0);
p3_wr_data : in std_logic_vector(31 DOWNTO 0);
p3_wr_full : out std_logic;
p3_wr_empty : out std_logic;
p3_wr_count : out std_logic_vector(6 DOWNTO 0);
p3_wr_underrun : out std_logic;
p3_wr_error : out std_logic;
p3_rd_clk : in std_logic;
p3_rd_en : in std_logic;
p3_rd_data : out std_logic_vector(31 DOWNTO 0);
p3_rd_full : out std_logic;
p3_rd_empty : out std_logic;
p3_rd_count : out std_logic_vector(6 DOWNTO 0);
p3_rd_overflow : out std_logic;
p3_rd_error : out std_logic;
p4_arb_en : in std_logic;
p4_cmd_clk : in std_logic;
p4_cmd_en : in std_logic;
p4_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p4_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p4_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p4_cmd_empty : out std_logic;
p4_cmd_full : out std_logic;
p4_wr_clk : in std_logic;
p4_wr_en : in std_logic;
p4_wr_mask : in std_logic_vector(3 DOWNTO 0);
p4_wr_data : in std_logic_vector(31 DOWNTO 0);
p4_wr_full : out std_logic;
p4_wr_empty : out std_logic;
p4_wr_count : out std_logic_vector(6 DOWNTO 0);
p4_wr_underrun : out std_logic;
p4_wr_error : out std_logic;
p4_rd_clk : in std_logic;
p4_rd_en : in std_logic;
p4_rd_data : out std_logic_vector(31 DOWNTO 0);
p4_rd_full : out std_logic;
p4_rd_empty : out std_logic;
p4_rd_count : out std_logic_vector(6 DOWNTO 0);
p4_rd_overflow : out std_logic;
p4_rd_error : out std_logic;
p5_arb_en : in std_logic;
p5_cmd_clk : in std_logic;
p5_cmd_en : in std_logic;
p5_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p5_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p5_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p5_cmd_empty : out std_logic;
p5_cmd_full : out std_logic;
p5_wr_clk : in std_logic;
p5_wr_en : in std_logic;
p5_wr_mask : in std_logic_vector(3 DOWNTO 0);
p5_wr_data : in std_logic_vector(31 DOWNTO 0);
p5_wr_full : out std_logic;
p5_wr_empty : out std_logic;
p5_wr_count : out std_logic_vector(6 DOWNTO 0);
p5_wr_underrun : out std_logic;
p5_wr_error : out std_logic;
p5_rd_clk : in std_logic;
p5_rd_en : in std_logic;
p5_rd_data : out std_logic_vector(31 DOWNTO 0);
p5_rd_full : out std_logic;
p5_rd_empty : out std_logic;
p5_rd_count : out std_logic_vector(6 DOWNTO 0);
p5_rd_overflow : out std_logic;
p5_rd_error : out std_logic;
mcbx_dram_addr : out std_logic_vector(C_MEM_ADDR_WIDTH - 1 DOWNTO 0);
mcbx_dram_ba : out std_logic_vector(C_MEM_BANKADDR_WIDTH - 1 DOWNTO 0);
mcbx_dram_ras_n : out std_logic;
mcbx_dram_cas_n : out std_logic;
mcbx_dram_we_n : out std_logic;
mcbx_dram_cke : out std_logic;
mcbx_dram_clk : out std_logic;
mcbx_dram_clk_n : out std_logic;
mcbx_dram_dq : inout std_logic_vector(C_NUM_DQ_PINS-1 DOWNTO 0);
mcbx_dram_dqs : inout std_logic;
mcbx_dram_dqs_n : inout std_logic;
mcbx_dram_udqs : inout std_logic;
mcbx_dram_udqs_n : inout std_logic;
mcbx_dram_udm : out std_logic;
mcbx_dram_ldm : out std_logic;
mcbx_dram_odt : out std_logic;
mcbx_dram_ddr3_rst : out std_logic;
calib_recal : in std_logic;
rzq : inout std_logic;
zio : inout std_logic;
ui_read : in std_logic;
ui_add : in std_logic;
ui_cs : in std_logic;
ui_clk : in std_logic;
ui_sdi : in std_logic;
ui_addr : in std_logic_vector(4 DOWNTO 0);
ui_broadcast : in std_logic;
ui_drp_update : in std_logic;
ui_done_cal : in std_logic;
ui_cmd : in std_logic;
ui_cmd_in : in std_logic;
ui_cmd_en : in std_logic;
ui_dqcount : in std_logic_vector(3 DOWNTO 0);
ui_dq_lower_dec : in std_logic;
ui_dq_lower_inc : in std_logic;
ui_dq_upper_dec : in std_logic;
ui_dq_upper_inc : in std_logic;
ui_udqs_inc : in std_logic;
ui_udqs_dec : in std_logic;
ui_ldqs_inc : in std_logic;
ui_ldqs_dec : in std_logic;
uo_data : out std_logic_vector(7 DOWNTO 0);
uo_data_valid : out std_logic;
uo_done_cal : out std_logic;
uo_cmd_ready_in : out std_logic;
uo_refrsh_flag : out std_logic;
uo_cal_start : out std_logic;
uo_sdo : out std_logic;
status : out std_logic_vector(31 DOWNTO 0);
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end component;
signal uo_data : std_logic_vector(7 downto 0);
constant C_PORT_ENABLE : std_logic_vector(5 downto 0) := "000001";
constant C_PORT_CONFIG : string := "B32_B32_R32_R32_R32_R32";
constant ARB_TIME_SLOT_0 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_0(2 downto 0));
constant ARB_TIME_SLOT_1 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_1(2 downto 0));
constant ARB_TIME_SLOT_2 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_2(2 downto 0));
constant ARB_TIME_SLOT_3 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_3(2 downto 0));
constant ARB_TIME_SLOT_4 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_4(2 downto 0));
constant ARB_TIME_SLOT_5 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_5(2 downto 0));
constant ARB_TIME_SLOT_6 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_6(2 downto 0));
constant ARB_TIME_SLOT_7 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_7(2 downto 0));
constant ARB_TIME_SLOT_8 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_8(2 downto 0));
constant ARB_TIME_SLOT_9 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_9(2 downto 0));
constant ARB_TIME_SLOT_10 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_10(2 downto 0));
constant ARB_TIME_SLOT_11 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_11(2 downto 0));
constant C_MC_CALIBRATION_CLK_DIV : integer := 1;
constant C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000" + "0000010000"; -- 16 cycles are added to avoid trfc violations
constant C_SKIP_DYN_IN_TERM : integer := 1;
constant C_MC_CALIBRATION_RA : bit_vector(15 downto 0) := X"0000";
constant C_MC_CALIBRATION_BA : bit_vector(2 downto 0) := o"0";
constant C_MC_CALIBRATION_CA : bit_vector(11 downto 0) := X"000";
constant C_MEM_DDR3_DYN_WRT_ODT : string := "OFF";
signal status : std_logic_vector(31 downto 0);
signal uo_data_valid : std_logic;
signal uo_cmd_ready_in : std_logic;
signal uo_refrsh_flag : std_logic;
signal uo_cal_start : std_logic;
signal uo_sdo : std_logic;
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of acch : architecture IS
"mig_v3_9_ddr3_s6, Coregen 13.3";
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of acch : architecture IS "mcb3_ddr3_s6,mig_v3_9,{LANGUAGE=VHDL, SYNTHESIS_TOOL=ISE, NO_OF_CONTROLLERS=2, AXI_ENABLE=0, MEM_INTERFACE_TYPE=DDR3_SDRAM, CLK_PERIOD=2500, MEMORY_PART=mt41j128m16xx-15e, MEMORY_DEVICE_WIDTH=16, OUTPUT_DRV=DIV6, RTT_NOM=DIV4, AUTO_SR=ENABLED, HIGH_TEMP_SR=NORMAL, PORT_CONFIG=Two 32-bit bi-directional and four 32-bit unidirectional ports, MEM_ADDR_ORDER=ROW_BANK_COLUMN, PORT_ENABLE=Port0, INPUT_PIN_TERMINATION=CALIB_TERM, DATA_TERMINATION=25 Ohms, CLKFBOUT_MULT_F=2, CLKOUT_DIVIDE=1, DEBUG_PORT=0, INPUT_CLK_TYPE=Differential}";
begin
memc3_mcb_raw_wrapper_inst : mcb_raw_wrapper
generic map
(
C_MEMCLK_PERIOD => C_MEMCLK_PERIOD,
C_P0_MASK_SIZE => C_P0_MASK_SIZE,
C_P0_DATA_PORT_SIZE => C_P0_DATA_PORT_SIZE,
C_P1_MASK_SIZE => C_P1_MASK_SIZE,
C_P1_DATA_PORT_SIZE => C_P1_DATA_PORT_SIZE,
C_ARB_NUM_TIME_SLOTS => C_ARB_NUM_TIME_SLOTS,
C_ARB_TIME_SLOT_0 => ARB_TIME_SLOT_0,
C_ARB_TIME_SLOT_1 => ARB_TIME_SLOT_1,
C_ARB_TIME_SLOT_2 => ARB_TIME_SLOT_2,
C_ARB_TIME_SLOT_3 => ARB_TIME_SLOT_3,
C_ARB_TIME_SLOT_4 => ARB_TIME_SLOT_4,
C_ARB_TIME_SLOT_5 => ARB_TIME_SLOT_5,
C_ARB_TIME_SLOT_6 => ARB_TIME_SLOT_6,
C_ARB_TIME_SLOT_7 => ARB_TIME_SLOT_7,
C_ARB_TIME_SLOT_8 => ARB_TIME_SLOT_8,
C_ARB_TIME_SLOT_9 => ARB_TIME_SLOT_9,
C_ARB_TIME_SLOT_10 => ARB_TIME_SLOT_10,
C_ARB_TIME_SLOT_11 => ARB_TIME_SLOT_11,
C_PORT_CONFIG => C_PORT_CONFIG,
C_PORT_ENABLE => C_PORT_ENABLE,
C_MEM_TRAS => C_MEM_TRAS,
C_MEM_TRCD => C_MEM_TRCD,
C_MEM_TREFI => C_MEM_TREFI,
C_MEM_TRFC => C_MEM_TRFC,
C_MEM_TRP => C_MEM_TRP,
C_MEM_TWR => C_MEM_TWR,
C_MEM_TRTP => C_MEM_TRTP,
C_MEM_TWTR => C_MEM_TWTR,
C_MEM_ADDR_ORDER => C_MEM_ADDR_ORDER,
C_NUM_DQ_PINS => C_NUM_DQ_PINS,
C_MEM_TYPE => C_MEM_TYPE,
C_MEM_DENSITY => C_MEM_DENSITY,
C_MEM_BURST_LEN => C_MEM_BURST_LEN,
C_MEM_CAS_LATENCY => C_MEM_CAS_LATENCY,
C_MEM_ADDR_WIDTH => C_MEM_ADDR_WIDTH,
C_MEM_BANKADDR_WIDTH => C_MEM_BANKADDR_WIDTH,
C_MEM_NUM_COL_BITS => C_MEM_NUM_COL_BITS,
C_MEM_DDR1_2_ODS => C_MEM_DDR1_2_ODS,
C_MEM_DDR2_RTT => C_MEM_DDR2_RTT,
C_MEM_DDR2_DIFF_DQS_EN => C_MEM_DDR2_DIFF_DQS_EN,
C_MEM_DDR2_3_PA_SR => C_MEM_DDR2_3_PA_SR,
C_MEM_DDR2_3_HIGH_TEMP_SR => C_MEM_DDR2_3_HIGH_TEMP_SR,
C_MEM_DDR3_CAS_LATENCY => C_MEM_DDR3_CAS_LATENCY,
C_MEM_DDR3_ODS => C_MEM_DDR3_ODS,
C_MEM_DDR3_RTT => C_MEM_DDR3_RTT,
C_MEM_DDR3_CAS_WR_LATENCY => C_MEM_DDR3_CAS_WR_LATENCY,
C_MEM_DDR3_AUTO_SR => C_MEM_DDR3_AUTO_SR,
C_MEM_DDR3_DYN_WRT_ODT => C_MEM_DDR3_DYN_WRT_ODT,
C_MEM_MOBILE_PA_SR => C_MEM_MOBILE_PA_SR,
C_MEM_MDDR_ODS => C_MEM_MDDR_ODS,
C_MC_CALIBRATION_CLK_DIV => C_MC_CALIBRATION_CLK_DIV,
C_MC_CALIBRATION_MODE => C_MC_CALIBRATION_MODE,
C_MC_CALIBRATION_DELAY => C_MC_CALIBRATION_DELAY,
C_MC_CALIB_BYPASS => C_MC_CALIB_BYPASS,
C_MC_CALIBRATION_RA => C_MC_CALIBRATION_RA,
C_MC_CALIBRATION_BA => C_MC_CALIBRATION_BA,
C_MC_CALIBRATION_CA => C_MC_CALIBRATION_CA,
C_CALIB_SOFT_IP => C_CALIB_SOFT_IP,
C_SIMULATION => C_SIMULATION,
C_SKIP_IN_TERM_CAL => C_SKIP_IN_TERM_CAL,
C_SKIP_DYNAMIC_CAL => C_SKIP_DYNAMIC_CAL,
C_SKIP_DYN_IN_TERM => C_SKIP_DYN_IN_TERM,
C_MEM_TZQINIT_MAXCNT => C_MEM_TZQINIT_MAXCNT,
LDQSP_TAP_DELAY_VAL => C_LDQSP_TAP_DELAY_VAL,
UDQSP_TAP_DELAY_VAL => C_UDQSP_TAP_DELAY_VAL,
LDQSN_TAP_DELAY_VAL => C_LDQSN_TAP_DELAY_VAL,
UDQSN_TAP_DELAY_VAL => C_UDQSN_TAP_DELAY_VAL,
DQ0_TAP_DELAY_VAL => C_DQ0_TAP_DELAY_VAL,
DQ1_TAP_DELAY_VAL => C_DQ1_TAP_DELAY_VAL,
DQ2_TAP_DELAY_VAL => C_DQ2_TAP_DELAY_VAL,
DQ3_TAP_DELAY_VAL => C_DQ3_TAP_DELAY_VAL,
DQ4_TAP_DELAY_VAL => C_DQ4_TAP_DELAY_VAL,
DQ5_TAP_DELAY_VAL => C_DQ5_TAP_DELAY_VAL,
DQ6_TAP_DELAY_VAL => C_DQ6_TAP_DELAY_VAL,
DQ7_TAP_DELAY_VAL => C_DQ7_TAP_DELAY_VAL,
DQ8_TAP_DELAY_VAL => C_DQ8_TAP_DELAY_VAL,
DQ9_TAP_DELAY_VAL => C_DQ9_TAP_DELAY_VAL,
DQ10_TAP_DELAY_VAL => C_DQ10_TAP_DELAY_VAL,
DQ11_TAP_DELAY_VAL => C_DQ11_TAP_DELAY_VAL,
DQ12_TAP_DELAY_VAL => C_DQ12_TAP_DELAY_VAL,
DQ13_TAP_DELAY_VAL => C_DQ13_TAP_DELAY_VAL,
DQ14_TAP_DELAY_VAL => C_DQ14_TAP_DELAY_VAL,
DQ15_TAP_DELAY_VAL => C_DQ15_TAP_DELAY_VAL
)
port map
(
sys_rst => async_rst,
sysclk_2x => sysclk_2x,
sysclk_2x_180 => sysclk_2x_180,
pll_ce_0 => pll_ce_0,
pll_ce_90 => pll_ce_90,
pll_lock => pll_lock,
mcbx_dram_addr => mcb3_dram_a,
mcbx_dram_ba => mcb3_dram_ba,
mcbx_dram_ras_n => mcb3_dram_ras_n,
mcbx_dram_cas_n => mcb3_dram_cas_n,
mcbx_dram_we_n => mcb3_dram_we_n,
mcbx_dram_cke => mcb3_dram_cke,
mcbx_dram_clk => mcb3_dram_ck,
mcbx_dram_clk_n => mcb3_dram_ck_n,
mcbx_dram_dq => mcb3_dram_dq,
mcbx_dram_odt => mcb3_dram_odt,
mcbx_dram_ldm => mcb3_dram_dm,
mcbx_dram_udm => mcb3_dram_udm,
mcbx_dram_dqs => mcb3_dram_dqs,
mcbx_dram_dqs_n => mcb3_dram_dqs_n,
mcbx_dram_udqs => mcb3_dram_udqs,
mcbx_dram_udqs_n => mcb3_dram_udqs_n,
mcbx_dram_ddr3_rst => mcb3_dram_reset_n,
calib_recal => '0',
rzq => mcb3_rzq,
zio => mcb3_zio,
ui_read => '0',
ui_add => '0',
ui_cs => '0',
ui_clk => mcb_drp_clk,
ui_sdi => '0',
ui_addr => (others => '0'),
ui_broadcast => '0',
ui_drp_update => '0',
ui_done_cal => '1',
ui_cmd => '0',
ui_cmd_in => '0',
ui_cmd_en => '0',
ui_dqcount => (others => '0'),
ui_dq_lower_dec => '0',
ui_dq_lower_inc => '0',
ui_dq_upper_dec => '0',
ui_dq_upper_inc => '0',
ui_udqs_inc => '0',
ui_udqs_dec => '0',
ui_ldqs_inc => '0',
ui_ldqs_dec => '0',
uo_data => uo_data,
uo_data_valid => uo_data_valid,
uo_done_cal => calib_done,
uo_cmd_ready_in => uo_cmd_ready_in,
uo_refrsh_flag => uo_refrsh_flag,
uo_cal_start => uo_cal_start,
uo_sdo => uo_sdo,
status => status,
selfrefresh_enter => '0',
selfrefresh_mode => selfrefresh_mode,
p0_arb_en => '1',
p0_cmd_clk => p0_cmd_clk,
p0_cmd_en => p0_cmd_en,
p0_cmd_instr => p0_cmd_instr,
p0_cmd_bl => p0_cmd_bl,
p0_cmd_byte_addr => p0_cmd_byte_addr,
p0_cmd_empty => p0_cmd_empty,
p0_cmd_full => p0_cmd_full,
p0_wr_clk => p0_wr_clk,
p0_wr_en => p0_wr_en,
p0_wr_mask => p0_wr_mask,
p0_wr_data => p0_wr_data,
p0_wr_full => p0_wr_full,
p0_wr_empty => p0_wr_empty,
p0_wr_count => p0_wr_count,
p0_wr_underrun => p0_wr_underrun,
p0_wr_error => p0_wr_error,
p0_rd_clk => p0_rd_clk,
p0_rd_en => p0_rd_en,
p0_rd_data => p0_rd_data,
p0_rd_full => p0_rd_full,
p0_rd_empty => p0_rd_empty,
p0_rd_count => p0_rd_count,
p0_rd_overflow => p0_rd_overflow,
p0_rd_error => p0_rd_error,
p1_arb_en => '0',
p1_cmd_clk => '0',
p1_cmd_en => '0',
p1_cmd_instr => (others => '0'),
p1_cmd_bl => (others => '0'),
p1_cmd_byte_addr => (others => '0'),
p1_cmd_empty => open,
p1_cmd_full => open,
p1_rd_clk => '0',
p1_rd_en => '0',
p1_rd_data => open,
p1_rd_full => open,
p1_rd_empty => open,
p1_rd_count => open,
p1_rd_overflow => open,
p1_rd_error => open,
p1_wr_clk => '0',
p1_wr_en => '0',
p1_wr_mask => (others => '0'),
p1_wr_data => (others => '0'),
p1_wr_full => open,
p1_wr_empty => open,
p1_wr_count => open,
p1_wr_underrun => open,
p1_wr_error => open,
p2_arb_en => '0',
p2_cmd_clk => '0',
p2_cmd_en => '0',
p2_cmd_instr => (others => '0'),
p2_cmd_bl => (others => '0'),
p2_cmd_byte_addr => (others => '0'),
p2_cmd_empty => open,
p2_cmd_full => open,
p2_rd_clk => '0',
p2_rd_en => '0',
p2_rd_data => open,
p2_rd_full => open,
p2_rd_empty => open,
p2_rd_count => open,
p2_rd_overflow => open,
p2_rd_error => open,
p2_wr_clk => '0',
p2_wr_en => '0',
p2_wr_mask => (others => '0'),
p2_wr_data => (others => '0'),
p2_wr_full => open,
p2_wr_empty => open,
p2_wr_count => open,
p2_wr_underrun => open,
p2_wr_error => open,
p3_arb_en => '0',
p3_cmd_clk => '0',
p3_cmd_en => '0',
p3_cmd_instr => (others => '0'),
p3_cmd_bl => (others => '0'),
p3_cmd_byte_addr => (others => '0'),
p3_cmd_empty => open,
p3_cmd_full => open,
p3_rd_clk => '0',
p3_rd_en => '0',
p3_rd_data => open,
p3_rd_full => open,
p3_rd_empty => open,
p3_rd_count => open,
p3_rd_overflow => open,
p3_rd_error => open,
p3_wr_clk => '0',
p3_wr_en => '0',
p3_wr_mask => (others => '0'),
p3_wr_data => (others => '0'),
p3_wr_full => open,
p3_wr_empty => open,
p3_wr_count => open,
p3_wr_underrun => open,
p3_wr_error => open,
p4_arb_en => '0',
p4_cmd_clk => '0',
p4_cmd_en => '0',
p4_cmd_instr => (others => '0'),
p4_cmd_bl => (others => '0'),
p4_cmd_byte_addr => (others => '0'),
p4_cmd_empty => open,
p4_cmd_full => open,
p4_rd_clk => '0',
p4_rd_en => '0',
p4_rd_data => open,
p4_rd_full => open,
p4_rd_empty => open,
p4_rd_count => open,
p4_rd_overflow => open,
p4_rd_error => open,
p4_wr_clk => '0',
p4_wr_en => '0',
p4_wr_mask => (others => '0'),
p4_wr_data => (others => '0'),
p4_wr_full => open,
p4_wr_empty => open,
p4_wr_count => open,
p4_wr_underrun => open,
p4_wr_error => open,
p5_arb_en => '0',
p5_cmd_clk => '0',
p5_cmd_en => '0',
p5_cmd_instr => (others => '0'),
p5_cmd_bl => (others => '0'),
p5_cmd_byte_addr => (others => '0'),
p5_cmd_empty => open,
p5_cmd_full => open,
p5_rd_clk => '0',
p5_rd_en => '0',
p5_rd_data => open,
p5_rd_full => open,
p5_rd_empty => open,
p5_rd_count => open,
p5_rd_overflow => open,
p5_rd_error => open,
p5_wr_clk => '0',
p5_wr_en => '0',
p5_wr_mask => (others => '0'),
p5_wr_data => (others => '0'),
p5_wr_full => open,
p5_wr_empty => open,
p5_wr_count => open,
p5_wr_underrun => open,
p5_wr_error => open
);
end architecture;
| gpl-3.0 | 3adc35c5154111297cc7dc6c6d6d6aa3 | 0.415549 | 3.553082 | false | false | false | false |
masaruohashi/tic-tac-toe | interface_jogo/registrador_mensagem.vhd | 1 | 1,494 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity registrador_mensagem is
port(
clock : in std_logic;
reset : in std_logic;
enable : in std_logic;
jogador_vencedor : in std_logic;
empate : in std_logic;
saida : out std_logic_vector(48 downto 0)
);
end registrador_mensagem;
architecture comportamental of registrador_mensagem is
signal s_vitoria: std_logic_vector(48 downto 0) := "1010110110100111101001101111111001011010011100001"; -- mensagem "vitoria"
signal s_derrota: std_logic_vector(48 downto 0) := "1000100110010111100101110010110111111101001100001"; -- mensagem "derrota"
signal s_empate : std_logic_vector(48 downto 0) := "1000101110110111100001100001111010011001010100000"; -- mensagem "empate "
begin
process(clock, reset, empate, jogador_vencedor)
begin
if reset='1' then
saida <= "0100000010000001000000100000010000001000000100000"; -- saida recebe 7 caracteres 'espaco'
elsif clock'event and clock='1' then
if enable='1' then
if empate='1' then
saida <= s_empate; -- saida recebe a palavra 'empate' + 1 caractere 'espaco'
elsif jogador_vencedor='0' then
saida <= s_vitoria; -- saida recebe a palavra 'vitoria'
else
saida <= s_derrota; -- saida recebe a palavra 'derrota'
end if;
end if;
end if;
end process;
end comportamental;
| mit | 0aa5c029b197cab7dce3911fed8c37ba | 0.650602 | 3.643902 | false | false | false | false |
JavierRizzoA/Sacagawea | sources/registers/Register4.vhd | 1 | 614 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Register4 is
Port (
d : in STD_LOGIC_VECTOR(3 downto 0) := "0000"; --Input.
load : in STD_LOGIC; --Load/Enable.
clr : in STD_LOGIC; --Async clear.
clk : in STD_LOGIC; --Clock.
q : out STD_LOGIC_VECTOR(3 downto 0) :="0000" --Output
);
end Register4;
architecture Behavioral of Register4 is
begin
process(clk, clr)
begin
if rising_edge(clk) then
if clr = '1' then
q <= "0000";
elsif load = '1' then
q <= d;
end if;
end if;
end process;
end Behavioral; | mit | efd6d8908ba68643a83f9efe40e7fbde | 0.557003 | 3.283422 | false | false | false | false |
srohrer32/beamformer | hdl/nearfield_processing.vhd | 1 | 22,411 | -----------------------------------------------------------------------------------
-- Created by Sam Rohrer --
-- Beamforms in the nearfield based on a generic for distance --
-- This is the actual processing that was written for the FPGA --
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity nearfield_processing is
generic(
divisor : integer := 50; -- difference between system clock 1 us
speed_sound : integer := 13397; -- in inches/second
speaker_distance : integer := 2 * 10**3; -- in inches
sample_period : integer := 22
);
port(
i_datain_r : in std_logic_vector (7 downto 0); -- 8 bit from memory
i_datain_l : in std_logic_vector (7 downto 0); -- 8 bit from memory
i_clock : in std_logic; --
i_distance : in std_logic_vector (4 downto 0); -- Switches determine distance
i_reset : in std_logic ; -- To reset the entire system
i_sampleclock : in std_logic ; -- Rate at which the music is playing
o_speaker_enable : out std_logic; --LDAC enable
o_dataout : out std_logic_vector (7 downto 0); -- 8 bit to be multiplexed
o_channel : out std_logic_vector (4 downto 0); -- 5 bit to select which DAC to enable
o_us_clock : out std_logic
);
end nearfield_processing;
architecture Behavioral of nearfield_processing is
-- Holding Data
type sr_array is array(natural range <>) of std_logic_vector(7 downto 0);
signal shift_register_l : sr_array(4 downto 0);
signal shift_register_r : sr_array(4 downto 0);
--Sound dataout signals to hold before output
signal data_r_0 : std_logic_vector(7 downto 0);
signal data_r_1 : std_logic_vector(7 downto 0);
signal data_r_2 : std_logic_vector(7 downto 0);
signal data_r_3 : std_logic_vector(7 downto 0);
signal data_r_4 : std_logic_vector(7 downto 0);
signal data_l_0 : std_logic_vector(7 downto 0);
signal data_l_1 : std_logic_vector(7 downto 0);
signal data_l_2 : std_logic_vector(7 downto 0);
signal data_l_3 : std_logic_vector(7 downto 0);
signal data_l_4 : std_logic_vector(7 downto 0);
--Anti-Sound data signals
signal anti_data_r_0 : std_logic_vector(7 downto 0);
signal anti_data_r_1 : std_logic_vector(7 downto 0);
signal anti_data_r_2 : std_logic_vector(7 downto 0);
signal anti_data_r_3 : std_logic_vector(7 downto 0);
signal anti_data_r_4 : std_logic_vector(7 downto 0);
signal anti_data_l_0 : std_logic_vector(7 downto 0);
signal anti_data_l_1 : std_logic_vector(7 downto 0);
signal anti_data_l_2 : std_logic_vector(7 downto 0);
signal anti_data_l_3 : std_logic_vector(7 downto 0);
signal anti_data_l_4 : std_logic_vector(7 downto 0);
--Counts through delays
signal sample_edges : integer range 0 to 7;
signal output_counter_l_0 : integer range 0 to 127 := 0;
signal output_counter_r_0 : integer range 0 to 127 := 0;
signal output_counter_l_1 : integer range 0 to 127 := 0;
signal output_counter_r_1 : integer range 0 to 127 := 0;
signal output_counter_l_2 : integer range 0 to 127 := 0;
signal output_counter_r_2 : integer range 0 to 127 := 0;
signal output_counter_l_3 : integer range 0 to 127 := 0;
signal output_counter_r_3 : integer range 0 to 127 := 0;
signal output_counter_l_4 : integer range 0 to 127 := 0;
signal output_counter_r_4 : integer range 0 to 127 := 0;
-- Counts through 5 different channels
signal mux_counter : integer range 0 to 5;
signal temp_extended_0 : std_logic_vector (8 downto 0);
signal temp_extended_2_0 : std_logic_vector (8 downto 0);
signal temp_extended_1 : std_logic_vector (8 downto 0);
signal temp_extended_2_1 : std_logic_vector (8 downto 0);
signal temp_extended_2 : std_logic_vector (8 downto 0);
signal temp_extended_2_2 : std_logic_vector (8 downto 0);
signal temp_extended_3 : std_logic_vector (8 downto 0);
signal temp_extended_2_3 : std_logic_vector (8 downto 0);
signal temp_extended_4 : std_logic_vector (8 downto 0);
signal temp_extended_2_4 : std_logic_vector (8 downto 0);
signal anti_temp_extended_0 : std_logic_vector (8 downto 0);
signal anti_temp_extended_2_0 : std_logic_vector (8 downto 0);
signal anti_temp_extended_1 : std_logic_vector (8 downto 0);
signal anti_temp_extended_2_1 : std_logic_vector (8 downto 0);
signal anti_temp_extended_2 : std_logic_vector (8 downto 0);
signal anti_temp_extended_2_2 : std_logic_vector (8 downto 0);
signal anti_temp_extended_3 : std_logic_vector (8 downto 0);
signal anti_temp_extended_2_3 : std_logic_vector (8 downto 0);
signal anti_temp_extended_4 : std_logic_vector (8 downto 0);
signal anti_temp_extended_2_4 : std_logic_vector (8 downto 0);
signal result_0 : std_logic_vector (8 downto 0);
signal result_1 : std_logic_vector (8 downto 0);
signal result_2 : std_logic_vector (8 downto 0);
signal result_3 : std_logic_vector (8 downto 0);
signal result_4 : std_logic_vector (8 downto 0);
--Delays & Calculation Signals
signal delay_1 : integer range 0 to 127;
signal delay_2 : integer range 0 to 127;
signal delay_3 : integer range 0 to 127;
signal delay_4 : integer range 0 to 127;
signal us_clock : std_logic;
signal sqrt_est : integer range 0 to 31;
signal dif_dist_sq_1 : integer range 0 to 511;
signal dif_dist_sq_2 : integer range 0 to 511;
signal dif_dist_sq_3 : integer range 0 to 511;
signal dif_dist_sq_4 : integer range 0 to 511;
signal dif_dist_sqrt_1 : integer range 0 to 511 := 25;
signal dif_dist_sqrt_2 : integer range 0 to 511 := 25;
signal dif_dist_sqrt_3 : integer range 0 to 511 := 25;
signal dif_dist_sqrt_4 : integer range 0 to 511 := 25;
signal dif_time_1 : integer range 0 to 127;
signal dif_time_2 : integer range 0 to 127;
signal dif_time_3 : integer range 0 to 127;
signal dif_time_4 : integer range 0 to 127;
-- Distance to Delay Calculation Signals
signal distance : integer range 0 to 127;
--Clock Division
signal clockpulses : integer range 0 to 127;
begin
--************** Tying output signals ******************--
o_us_clock <= us_clock;
--************** From system clock to 1 us *************--
clock_division : process(i_reset, i_clock)
begin
if (i_reset = '1') then
clockpulses <= 0;
us_clock <= '0';
elsif(rising_edge(i_clock)) then
clockpulses <= clockpulses + 1 ;
if(clockpulses = (divisor-1)) then
us_clock <= Not us_clock;
clockpulses <= 0;
end if;
end if;
end process;
--*************** Distance to integer **************--
distance <= conv_integer(i_distance);
--*************** Distance to delay converter*******--
distance_to_delay : process (i_reset, i_clock, clockpulses,distance)
begin
if(i_reset = '1') then
delay_1 <= 0;
delay_2 <= 0;
delay_3 <= 0;
delay_4 <= 0;
sqrt_est <= 25;
dif_time_1 <= 0;
dif_time_2 <= 0;
dif_time_3 <= 0;
dif_time_4 <= 0;
elsif(rising_edge(i_clock)) then
if(clockpulses = 1) then
dif_dist_sq_1 <= (distance*distance + (1 * speaker_distance) * (1 * speaker_distance));
dif_dist_sq_2 <= (distance*distance + (2 * speaker_distance) * (2 * speaker_distance));
dif_dist_sq_3 <= (distance*distance + (3 * speaker_distance) * (3 * speaker_distance));
dif_dist_sq_4 <= (distance*distance + (4 * speaker_distance) * (4 * speaker_distance));
dif_dist_sqrt_1 <= sqrt_est;
dif_dist_sqrt_2 <= sqrt_est;
dif_dist_sqrt_3 <= sqrt_est;
dif_dist_sqrt_4 <= sqrt_est;
elsif(clockpulses = 2) then
dif_dist_sqrt_1 <= ((dif_dist_sqrt_1 + (dif_dist_sq_1 / dif_dist_sqrt_1))/2);
dif_dist_sqrt_2 <= ((dif_dist_sqrt_2 + (dif_dist_sq_2 / dif_dist_sqrt_2))/2);
dif_dist_sqrt_3 <= ((dif_dist_sqrt_3 + (dif_dist_sq_3 / dif_dist_sqrt_3))/2);
dif_dist_sqrt_4 <= ((dif_dist_sqrt_4 + (dif_dist_sq_4 / dif_dist_sqrt_4))/2);
elsif(clockpulses = 3) then
dif_dist_sqrt_1 <= ((dif_dist_sqrt_1 + (dif_dist_sq_1 / dif_dist_sqrt_1))/2);
dif_dist_sqrt_2 <= ((dif_dist_sqrt_2 + (dif_dist_sq_2 / dif_dist_sqrt_2))/2);
dif_dist_sqrt_3 <= ((dif_dist_sqrt_3 + (dif_dist_sq_3 / dif_dist_sqrt_3))/2);
dif_dist_sqrt_4 <= ((dif_dist_sqrt_4 + (dif_dist_sq_4 / dif_dist_sqrt_4))/2);
elsif(clockpulses = 4) then
dif_dist_sqrt_1 <= ((dif_dist_sqrt_1 + (dif_dist_sq_1 / dif_dist_sqrt_1))/2);
dif_dist_sqrt_2 <= ((dif_dist_sqrt_2 + (dif_dist_sq_2 / dif_dist_sqrt_2))/2);
dif_dist_sqrt_3 <= ((dif_dist_sqrt_3 + (dif_dist_sq_3 / dif_dist_sqrt_3))/2);
dif_dist_sqrt_4 <= ((dif_dist_sqrt_4 + (dif_dist_sq_4 / dif_dist_sqrt_4))/2);
elsif(clockpulses = 5) then
dif_dist_sqrt_1 <= ((dif_dist_sqrt_1 + (dif_dist_sq_1 / dif_dist_sqrt_1))/2);
dif_dist_sqrt_2 <= ((dif_dist_sqrt_2 + (dif_dist_sq_2 / dif_dist_sqrt_2))/2);
dif_dist_sqrt_3 <= ((dif_dist_sqrt_3 + (dif_dist_sq_3 / dif_dist_sqrt_3))/2);
dif_dist_sqrt_4 <= ((dif_dist_sqrt_4 + (dif_dist_sq_4 / dif_dist_sqrt_4))/2);
elsif(clockpulses = 6) then
dif_time_1 <= ((dif_dist_sqrt_1 - distance)/ speed_sound);
dif_time_2 <= ((dif_dist_sqrt_2 - distance)/ speed_sound);
dif_time_3 <= ((dif_dist_sqrt_3 - distance)/ speed_sound);
dif_time_4 <= ((dif_dist_sqrt_4 - distance)/ speed_sound);
elsif(clockpulses = 7) then
delay_1 <= (dif_time_4 - dif_time_3) * 10**6;
delay_2 <= (dif_time_4 - dif_time_2) * 10**6;
delay_3 <= (dif_time_4 - dif_time_1) * 10**6;
delay_4 <= (dif_time_4) * 10**6;
end if;
end if;
--********** Manually Set Delays ****************--
-- delay_1 <= (22+2); --42
-- delay_2 <= (44+2); --72
-- delay_3 <= (66+2); --91
-- delay_4 <= (88+2); --97
-- sample_period <= 22;
--********** End Manually Set Delays ************--
end process;
--**************** Filling Shift Registers ************--
fill_regs : process (i_reset, i_sampleclock)
begin
if (i_reset = '1') then
shift_register_l <= (others => X"00");
shift_register_r <= (others => X"00");
-- Conditions to shift in the shift register (every new sample)
elsif( rising_edge (i_sampleclock)) then
if(sample_edges = 0) then
shift_register_r(0) <= i_datain_r;
shift_register_l(0) <= i_datain_l;
elsif(sample_edges = 1) then
shift_register_r(1) <= i_datain_r;
shift_register_l(1) <= i_datain_l;
elsif(sample_edges = 2) then
shift_register_r(2) <= i_datain_r;
shift_register_l(2) <= i_datain_l;
elsif(sample_edges = 3) then
shift_register_r(3) <= i_datain_r;
shift_register_l(3) <= i_datain_l;
elsif(sample_edges = 4) then
shift_register_r(4) <= i_datain_r;
shift_register_l(4) <= i_datain_l;
end if;
end if;
end process;
--******************* Sample Edge Counter ***********************--
sample_edge_counter : process (i_reset, i_sampleclock)
begin
if(i_reset = '1') then
sample_edges <= 0;
elsif (rising_edge(i_sampleclock)) then
sample_edges <= sample_edges +1;
if (sample_edges = 4) then
sample_edges <= 0;
end if;
end if;
end process;
--************* Processes data by inserting delays **************--
speaker_processing_l : process(us_clock)
begin
if(rising_edge(us_clock)) then
if(i_reset = '1') then
output_counter_l_0 <= 0;
output_counter_l_1 <= sample_period;
output_counter_l_2 <= (sample_period*2);
output_counter_l_3 <= (sample_period*3);
output_counter_l_4 <= (sample_period*4);
data_l_0 <= X"00";
data_l_1 <= X"00";
data_l_2 <= X"00";
data_l_3 <= X"00";
data_l_4 <= X"00";
else
--Output Conditions based on delays calculated or inserted
if(output_counter_l_0 = 2) then
data_l_0 <= shift_register_l(0);
elsif(output_counter_l_0 = delay_1) then
data_l_1 <= shift_register_l(0);
elsif(output_counter_l_0 = delay_2) then
data_l_2 <= shift_register_l(0);
elsif(output_counter_l_0 = delay_3) then
data_l_3 <= shift_register_l(0);
elsif(output_counter_l_0 = delay_4) then
data_l_4 <= shift_register_l(0);
end if;
if(output_counter_l_1 = 2) then
data_l_0 <= shift_register_l(1);
elsif(output_counter_l_1 = delay_1) then
data_l_1 <= shift_register_l(1);
elsif(output_counter_l_1 = delay_2) then
data_l_2 <= shift_register_l(1);
elsif(output_counter_l_1 = delay_3) then
data_l_3 <= shift_register_l(1);
elsif(output_counter_l_1 = delay_4) then
data_l_4 <= shift_register_l(1);
end if;
if(output_counter_l_2 = 2) then
data_l_0 <= shift_register_l(2);
elsif(output_counter_l_2 = delay_1) then
data_l_1 <= shift_register_l(2);
elsif(output_counter_l_2 = delay_2) then
data_l_2 <= shift_register_l(2);
elsif(output_counter_l_2 = delay_3) then
data_l_3 <= shift_register_l(2);
elsif(output_counter_l_2 = delay_4) then
data_l_4 <= shift_register_l(2);
end if;
if(output_counter_l_3 = 2) then
data_l_0 <= shift_register_l(3);
elsif(output_counter_l_3 = delay_1) then
data_l_1 <= shift_register_l(3);
elsif(output_counter_l_3 = delay_2) then
data_l_2 <= shift_register_l(3);
elsif(output_counter_l_3 = delay_3) then
data_l_3 <= shift_register_l(3);
elsif(output_counter_l_3 = delay_4) then
data_l_4 <= shift_register_l(3);
end if;
if(output_counter_l_4 = 2) then
data_l_0 <= shift_register_l(4);
elsif(output_counter_l_4 = delay_1) then
data_l_1 <= shift_register_l(4);
elsif(output_counter_l_4 = delay_2) then
data_l_2 <= shift_register_l(4);
elsif(output_counter_l_4 = delay_3) then
data_l_3 <= shift_register_l(4);
elsif(output_counter_l_4 = delay_4) then
data_l_4 <= shift_register_l(4);
end if;
if(output_counter_l_0 = (sample_period*5-1)) then
output_counter_l_0 <= 0;
else
output_counter_l_0 <= output_counter_l_0 +1;
end if;
if(output_counter_l_1 = (sample_period*5-1)) then
output_counter_l_1 <= 0;
else
output_counter_l_1 <= output_counter_l_1 +1;
end if;
if(output_counter_l_2 = (sample_period*5-1)) then
output_counter_l_2 <= 0;
else
output_counter_l_2 <= output_counter_l_2 +1;
end if;
if(output_counter_l_3 = (sample_period*5-1)) then
output_counter_l_3 <= 0;
else
output_counter_l_3 <= output_counter_l_3 +1;
end if;
if(output_counter_l_4 = (sample_period*5-1)) then
output_counter_l_4 <= 0;
else
output_counter_l_4 <= output_counter_l_4 +1;
end if;
end if;
end if;
end process;
--************* Processes data by inserting delays **************--
speaker_processing_r : process(us_clock)
begin
if(rising_edge(us_clock)) then
if(i_reset = '1') then
output_counter_r_0 <= 0;
output_counter_r_1 <= sample_period;
output_counter_r_2 <= (sample_period*2);
output_counter_r_3 <= (sample_period*3);
output_counter_r_4 <= (sample_period*4);
data_r_0 <= X"00";
data_r_1 <= X"00";
data_r_2 <= X"00";
data_r_3 <= X"00";
data_r_4 <= X"00";
else
--Output Conditions based on delays calculated or inserted
if(output_counter_r_0 = 2) then
data_r_0 <= shift_register_r(0);
elsif(output_counter_r_0 = delay_1) then
data_r_1 <= shift_register_r(0);
elsif(output_counter_r_0 = delay_2) then
data_r_2 <= shift_register_r(0);
elsif(output_counter_r_0 = delay_3) then
data_r_3 <= shift_register_r(0);
elsif(output_counter_r_0 = delay_4) then
data_r_4 <= shift_register_r(0);
end if;
if(output_counter_r_1 = 2) then
data_r_0 <= shift_register_r(1);
elsif(output_counter_r_1 = delay_1) then
data_r_1 <= shift_register_r(1);
elsif(output_counter_r_1 = delay_2) then
data_r_2 <= shift_register_r(1);
elsif(output_counter_r_1 = delay_3) then
data_r_3 <= shift_register_r(1);
elsif(output_counter_r_1 = delay_4) then
data_r_4 <= shift_register_r(1);
end if;
if(output_counter_r_2 = 2) then
data_r_0 <= shift_register_r(2);
elsif(output_counter_r_2 = delay_1) then
data_r_1 <= shift_register_r(2);
elsif(output_counter_r_2 = delay_2) then
data_r_2 <= shift_register_r(2);
elsif(output_counter_r_2 = delay_3) then
data_r_3 <= shift_register_r(2);
elsif(output_counter_r_2 = delay_4) then
data_r_4 <= shift_register_r(2);
end if;
if(output_counter_r_3 = 2) then
data_r_0 <= shift_register_r(3);
elsif(output_counter_r_3 = delay_1) then
data_r_1 <= shift_register_r(3);
elsif(output_counter_r_3 = delay_2) then
data_r_2 <= shift_register_r(3);
elsif(output_counter_r_3 = delay_3) then
data_r_3 <= shift_register_r(3);
elsif(output_counter_r_3 = delay_4) then
data_r_4 <= shift_register_r(3);
end if;
if(output_counter_r_4 = 2) then
data_r_0 <= shift_register_r(4);
elsif(output_counter_r_4 = delay_1) then
data_r_1 <= shift_register_r(4);
elsif(output_counter_r_4 = delay_2) then
data_r_2 <= shift_register_r(4);
elsif(output_counter_r_4 = delay_3) then
data_r_3 <= shift_register_r(4);
elsif(output_counter_r_4 = delay_4) then
data_r_4 <= shift_register_r(4);
end if;
if(output_counter_r_0 = (sample_period*5-1)) then
output_counter_r_0 <= 0;
else
output_counter_r_0 <= output_counter_r_0 +1;
end if;
if(output_counter_r_1 = (sample_period*5-1)) then
output_counter_r_1 <= 0;
else
output_counter_r_1 <= output_counter_r_1 +1;
end if;
if(output_counter_r_2 = (sample_period*5-1)) then
output_counter_r_2 <= 0;
else
output_counter_r_2 <= output_counter_r_2 +1;
end if;
if(output_counter_r_3 = (sample_period*5-1)) then
output_counter_r_3 <= 0;
else
output_counter_r_3 <= output_counter_r_3 +1;
end if;
if(output_counter_r_4 = (sample_period*5-1)) then
output_counter_r_4 <= 0;
else
output_counter_r_4 <= output_counter_r_4 +1;
end if;
end if;
end if;
end process;
--*************** Anti-Sound Being Generated *************--
anti_sound: process(i_reset)
begin
if(i_reset = '1') then
anti_data_r_0 <= X"00";
anti_data_r_1 <= X"00";
anti_data_r_2 <= X"00";
anti_data_r_3 <= X"00";
anti_data_r_4 <= X"00";
anti_data_l_0 <= X"00";
anti_data_l_1 <= X"00";
anti_data_l_2 <= X"00";
anti_data_l_3 <= X"00";
anti_data_l_4 <= X"00";
else
anti_data_r_0 <= NOT data_r_0;
anti_data_r_1 <= NOT data_r_1;
anti_data_r_2 <= NOT data_r_2;
anti_data_r_3 <= NOT data_r_3;
anti_data_r_4 <= NOT data_r_4;
anti_data_l_0 <= NOT data_l_0;
anti_data_l_1 <= NOT data_l_1;
anti_data_l_2 <= NOT data_l_2;
anti_data_l_3 <= NOT data_l_3;
anti_data_l_4 <= NOT data_l_4;
end if;
end process;
----************* Output Selector (through MUX) *************--
output_selector : process (i_reset, us_clock, i_clock, clockpulses)
begin
if(rising_edge(i_clock)) then
if (i_reset = '1') then
mux_counter <= 0;
elsif(clockpulses = 40) then
o_channel <= (OTHERS => '1');
o_speaker_enable <= '1';
elsif (rising_edge (us_clock)) then
--Selects which DAC to output to (cycles every 6 us)
-- also selects the data to use on each output
if(mux_counter = 0) then
o_dataout <= result_0 (8 downto 1);
mux_counter <= mux_counter + 1;
o_speaker_enable <= '1';
o_channel <= (0=>'0', OTHERS=>'1');
elsif (mux_counter = 1) then
o_dataout <= result_1 (8 downto 1);
mux_counter <= mux_counter + 1;
o_speaker_enable <= '1';
o_channel <= (1=>'0', OTHERS=>'1');
elsif (mux_counter = 2) then
o_dataout <= result_2 (8 downto 1);
mux_counter <= mux_counter + 1;
o_speaker_enable <= '1';
o_channel <= (2=>'0', OTHERS=>'1');
elsif (mux_counter = 3) then
o_dataout <= result_3 (8 downto 1);
mux_counter <= mux_counter + 1;
o_speaker_enable <= '1';
o_channel <= (3=>'0', OTHERS=>'1');
elsif (mux_counter = 4) then
o_dataout <= result_4 (8 downto 1);
mux_counter <= mux_counter + 1;
o_speaker_enable <= '1';
o_channel <= (4=>'0', OTHERS=>'1');
elsif (mux_counter = 5) then
o_dataout <= X"00";
mux_counter <= 0;
o_speaker_enable <= '0';
o_channel <= (OTHERS=>'1');
end if;
end if;
end if;
end process;
--********************* Combinatorial to add data together **************************--
--Combinatorial Logic to fill the result registers
temp_extended_0 <= '0' & data_r_0;
temp_extended_2_0 <= '0' & data_l_4;
result_0 <= temp_extended_0 + temp_extended_2_0;
temp_extended_1 <= '0' & data_r_1;
temp_extended_2_1 <= '0' & data_l_3;
result_1 <= temp_extended_1 + temp_extended_2_1;
temp_extended_2 <= '0' & data_r_2;
temp_extended_2_2 <= '0' & data_l_2;
result_2 <= temp_extended_2 + temp_extended_2_2;
temp_extended_3 <= '0' & data_r_3;
temp_extended_2_3 <= '0' & data_l_1;
result_3 <= temp_extended_3 + temp_extended_2_3;
temp_extended_4 <= '0' & data_r_4;
temp_extended_2_4 <= '0' & data_l_0;
result_4 <= temp_extended_4 + temp_extended_2_4;
--**************************************************************--
end Behavioral;
| apache-2.0 | b2c8b0f02be140584b8977c39dd7ec51 | 0.567802 | 2.808748 | false | false | false | false |
timofonic/PHDL | misc/projects/spartan_pcie_board/fpga/lx45t_pinout/ipcore_dir/ddr3_controller/user_design/rtl/memc1_wrapper.vhd | 2 | 46,755 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.9
-- \ \ Application : MIG
-- / / Filename : memc1_wrapper.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:59 $
-- \ \ / \ Date Created :
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : This module instantiates mcb_raw_wrapper module.
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity memc1_wrapper is
generic (
C_MEMCLK_PERIOD : integer := 2500;
C_P0_MASK_SIZE : integer := 4;
C_P0_DATA_PORT_SIZE : integer := 32;
C_P1_MASK_SIZE : integer := 4;
C_P1_DATA_PORT_SIZE : integer := 32;
C_ARB_NUM_TIME_SLOTS : integer := 12;
C_ARB_TIME_SLOT_0 : bit_vector := "000";
C_ARB_TIME_SLOT_1 : bit_vector := "000";
C_ARB_TIME_SLOT_2 : bit_vector := "000";
C_ARB_TIME_SLOT_3 : bit_vector := "000";
C_ARB_TIME_SLOT_4 : bit_vector := "000";
C_ARB_TIME_SLOT_5 : bit_vector := "000";
C_ARB_TIME_SLOT_6 : bit_vector := "000";
C_ARB_TIME_SLOT_7 : bit_vector := "000";
C_ARB_TIME_SLOT_8 : bit_vector := "000";
C_ARB_TIME_SLOT_9 : bit_vector := "000";
C_ARB_TIME_SLOT_10 : bit_vector := "000";
C_ARB_TIME_SLOT_11 : bit_vector := "000";
C_MEM_TRAS : integer := 45000;
C_MEM_TRCD : integer := 12500;
C_MEM_TREFI : integer := 7800000;
C_MEM_TRFC : integer := 127500;
C_MEM_TRP : integer := 12500;
C_MEM_TWR : integer := 15000;
C_MEM_TRTP : integer := 7500;
C_MEM_TWTR : integer := 7500;
C_MEM_ADDR_ORDER : string :="ROW_BANK_COLUMN";
C_MEM_TYPE : string :="DDR2";
C_MEM_DENSITY : string :="1Gb";
C_NUM_DQ_PINS : integer := 4;
C_MEM_BURST_LEN : integer := 8;
C_MEM_CAS_LATENCY : integer := 5;
C_MEM_ADDR_WIDTH : integer := 14;
C_MEM_BANKADDR_WIDTH : integer := 3;
C_MEM_NUM_COL_BITS : integer := 11;
C_MEM_DDR1_2_ODS : string := "FULL";
C_MEM_DDR2_RTT : string := "50OHMS";
C_MEM_DDR2_DIFF_DQS_EN : string := "YES";
C_MEM_DDR2_3_PA_SR : string := "FULL";
C_MEM_DDR2_3_HIGH_TEMP_SR : string := "NORMAL";
C_MEM_DDR3_CAS_LATENCY : integer:= 7;
C_MEM_DDR3_CAS_WR_LATENCY : integer:= 5;
C_MEM_DDR3_ODS : string := "DIV6";
C_MEM_DDR3_RTT : string := "DIV2";
C_MEM_DDR3_AUTO_SR : string := "ENABLED";
C_MEM_MOBILE_PA_SR : string := "FULL";
C_MEM_MDDR_ODS : string := "FULL";
C_MC_CALIB_BYPASS : string := "NO";
C_LDQSP_TAP_DELAY_VAL : integer := 0;
C_UDQSP_TAP_DELAY_VAL : integer := 0;
C_LDQSN_TAP_DELAY_VAL : integer := 0;
C_UDQSN_TAP_DELAY_VAL : integer := 0;
C_DQ0_TAP_DELAY_VAL : integer := 0;
C_DQ1_TAP_DELAY_VAL : integer := 0;
C_DQ2_TAP_DELAY_VAL : integer := 0;
C_DQ3_TAP_DELAY_VAL : integer := 0;
C_DQ4_TAP_DELAY_VAL : integer := 0;
C_DQ5_TAP_DELAY_VAL : integer := 0;
C_DQ6_TAP_DELAY_VAL : integer := 0;
C_DQ7_TAP_DELAY_VAL : integer := 0;
C_DQ8_TAP_DELAY_VAL : integer := 0;
C_DQ9_TAP_DELAY_VAL : integer := 0;
C_DQ10_TAP_DELAY_VAL : integer := 0;
C_DQ11_TAP_DELAY_VAL : integer := 0;
C_DQ12_TAP_DELAY_VAL : integer := 0;
C_DQ13_TAP_DELAY_VAL : integer := 0;
C_DQ14_TAP_DELAY_VAL : integer := 0;
C_DQ15_TAP_DELAY_VAL : integer := 0;
C_SKIP_IN_TERM_CAL : integer := 0;
C_SKIP_DYNAMIC_CAL : integer := 0;
C_SIMULATION : string := "FALSE";
C_MC_CALIBRATION_MODE : string := "CALIBRATION";
C_MC_CALIBRATION_DELAY : string := "QUARTER";
C_CALIB_SOFT_IP : string := "TRUE"
);
port
(
-- high-speed PLL clock interface
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
async_rst : in std_logic;
--User Port0 Interface Signals
p0_cmd_clk : in std_logic;
p0_cmd_en : in std_logic;
p0_cmd_instr : in std_logic_vector(2 downto 0) ;
p0_cmd_bl : in std_logic_vector(5 downto 0) ;
p0_cmd_byte_addr : in std_logic_vector(29 downto 0) ;
p0_cmd_empty : out std_logic;
p0_cmd_full : out std_logic;
-- Data Wr Port signals
p0_wr_clk : in std_logic;
p0_wr_en : in std_logic;
p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 downto 0) ;
p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0) ;
p0_wr_full : out std_logic;
p0_wr_empty : out std_logic;
p0_wr_count : out std_logic_vector(6 downto 0) ;
p0_wr_underrun : out std_logic;
p0_wr_error : out std_logic;
--Data Rd Port signals
p0_rd_clk : in std_logic;
p0_rd_en : in std_logic;
p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0) ;
p0_rd_full : out std_logic;
p0_rd_empty : out std_logic;
p0_rd_count : out std_logic_vector(6 downto 0) ;
p0_rd_overflow : out std_logic;
p0_rd_error : out std_logic;
-- memory interface signals
mcb1_dram_ck : out std_logic;
mcb1_dram_ck_n : out std_logic;
mcb1_dram_a : out std_logic_vector(C_MEM_ADDR_WIDTH-1 downto 0);
mcb1_dram_ba : out std_logic_vector(C_MEM_BANKADDR_WIDTH-1 downto 0);
mcb1_dram_ras_n : out std_logic;
mcb1_dram_cas_n : out std_logic;
mcb1_dram_we_n : out std_logic;
mcb1_dram_odt : out std_logic;
-- mcb1_dram_odt : out std_logic;
mcb1_dram_cke : out std_logic;
mcb1_dram_dq : inout std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
mcb1_dram_dqs : inout std_logic;
mcb1_dram_dqs_n : inout std_logic;
mcb1_dram_reset_n : out std_logic;
mcb1_dram_udqs : inout std_logic;
mcb1_dram_udqs_n : inout std_logic;
mcb1_dram_udm : out std_logic;
mcb1_dram_dm : out std_logic;
mcb1_rzq : inout std_logic;
mcb1_zio : inout std_logic;
-- Calibration signals
mcb_drp_clk : in std_logic;
calib_done : out std_logic;
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end entity;
architecture acch of memc1_wrapper is
component mcb_raw_wrapper IS
GENERIC (
C_MEMCLK_PERIOD : integer;
C_PORT_ENABLE : std_logic_vector(5 downto 0);
C_MEM_ADDR_ORDER : string;
C_ARB_NUM_TIME_SLOTS : integer;
C_ARB_TIME_SLOT_0 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_1 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_2 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_3 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_4 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_5 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_6 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_7 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_8 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_9 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_10 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_11 : bit_vector(17 downto 0);
C_PORT_CONFIG : string;
C_MEM_TRAS : integer;
C_MEM_TRCD : integer;
C_MEM_TREFI : integer;
C_MEM_TRFC : integer;
C_MEM_TRP : integer;
C_MEM_TWR : integer;
C_MEM_TRTP : integer;
C_MEM_TWTR : integer;
C_NUM_DQ_PINS : integer;
C_MEM_TYPE : string;
C_MEM_DENSITY : string;
C_MEM_BURST_LEN : integer;
C_MEM_CAS_LATENCY : integer;
C_MEM_ADDR_WIDTH : integer;
C_MEM_BANKADDR_WIDTH : integer;
C_MEM_NUM_COL_BITS : integer;
C_MEM_DDR3_CAS_LATENCY : integer;
C_MEM_MOBILE_PA_SR : string;
C_MEM_DDR1_2_ODS : string;
C_MEM_DDR3_ODS : string;
C_MEM_DDR2_RTT : string;
C_MEM_DDR3_RTT : string;
C_MEM_MDDR_ODS : string;
C_MEM_DDR2_DIFF_DQS_EN : string;
C_MEM_DDR2_3_PA_SR : string;
C_MEM_DDR3_CAS_WR_LATENCY : integer;
C_MEM_DDR3_AUTO_SR : string;
C_MEM_DDR2_3_HIGH_TEMP_SR : string;
C_MEM_DDR3_DYN_WRT_ODT : string;
C_MC_CALIB_BYPASS : string;
C_MC_CALIBRATION_RA : bit_vector(15 DOWNTO 0);
C_MC_CALIBRATION_BA : bit_vector(2 DOWNTO 0);
C_CALIB_SOFT_IP : string;
C_MC_CALIBRATION_CA : bit_vector(11 DOWNTO 0);
C_MC_CALIBRATION_CLK_DIV : integer;
C_MC_CALIBRATION_MODE : string;
C_MC_CALIBRATION_DELAY : string;
LDQSP_TAP_DELAY_VAL : integer;
UDQSP_TAP_DELAY_VAL : integer;
LDQSN_TAP_DELAY_VAL : integer;
UDQSN_TAP_DELAY_VAL : integer;
DQ0_TAP_DELAY_VAL : integer;
DQ1_TAP_DELAY_VAL : integer;
DQ2_TAP_DELAY_VAL : integer;
DQ3_TAP_DELAY_VAL : integer;
DQ4_TAP_DELAY_VAL : integer;
DQ5_TAP_DELAY_VAL : integer;
DQ6_TAP_DELAY_VAL : integer;
DQ7_TAP_DELAY_VAL : integer;
DQ8_TAP_DELAY_VAL : integer;
DQ9_TAP_DELAY_VAL : integer;
DQ10_TAP_DELAY_VAL : integer;
DQ11_TAP_DELAY_VAL : integer;
DQ12_TAP_DELAY_VAL : integer;
DQ13_TAP_DELAY_VAL : integer;
DQ14_TAP_DELAY_VAL : integer;
DQ15_TAP_DELAY_VAL : integer;
C_P0_MASK_SIZE : integer;
C_P0_DATA_PORT_SIZE : integer;
C_P1_MASK_SIZE : integer;
C_P1_DATA_PORT_SIZE : integer;
C_SIMULATION : string ;
C_SKIP_IN_TERM_CAL : integer;
C_SKIP_DYNAMIC_CAL : integer;
C_SKIP_DYN_IN_TERM : integer;
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0)
);
PORT (
-- HIGH-SPEED PLL clock interface
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
sys_rst : in std_logic;
p0_arb_en : in std_logic;
p0_cmd_clk : in std_logic;
p0_cmd_en : in std_logic;
p0_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p0_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p0_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p0_cmd_empty : out std_logic;
p0_cmd_full : out std_logic;
p0_wr_clk : in std_logic;
p0_wr_en : in std_logic;
p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 DOWNTO 0);
p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 DOWNTO 0);
p0_wr_full : out std_logic;
p0_wr_empty : out std_logic;
p0_wr_count : out std_logic_vector(6 DOWNTO 0);
p0_wr_underrun : out std_logic;
p0_wr_error : out std_logic;
p0_rd_clk : in std_logic;
p0_rd_en : in std_logic;
p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 DOWNTO 0);
p0_rd_full : out std_logic;
p0_rd_empty : out std_logic;
p0_rd_count : out std_logic_vector(6 DOWNTO 0);
p0_rd_overflow : out std_logic;
p0_rd_error : out std_logic;
p1_arb_en : in std_logic;
p1_cmd_clk : in std_logic;
p1_cmd_en : in std_logic;
p1_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p1_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p1_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p1_cmd_empty : out std_logic;
p1_cmd_full : out std_logic;
p1_wr_clk : in std_logic;
p1_wr_en : in std_logic;
p1_wr_mask : in std_logic_vector(C_P1_MASK_SIZE - 1 DOWNTO 0);
p1_wr_data : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 DOWNTO 0);
p1_wr_full : out std_logic;
p1_wr_empty : out std_logic;
p1_wr_count : out std_logic_vector(6 DOWNTO 0);
p1_wr_underrun : out std_logic;
p1_wr_error : out std_logic;
p1_rd_clk : in std_logic;
p1_rd_en : in std_logic;
p1_rd_data : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 DOWNTO 0);
p1_rd_full : out std_logic;
p1_rd_empty : out std_logic;
p1_rd_count : out std_logic_vector(6 DOWNTO 0);
p1_rd_overflow : out std_logic;
p1_rd_error : out std_logic;
p2_arb_en : in std_logic;
p2_cmd_clk : in std_logic;
p2_cmd_en : in std_logic;
p2_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p2_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p2_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p2_cmd_empty : out std_logic;
p2_cmd_full : out std_logic;
p2_wr_clk : in std_logic;
p2_wr_en : in std_logic;
p2_wr_mask : in std_logic_vector(3 DOWNTO 0);
p2_wr_data : in std_logic_vector(31 DOWNTO 0);
p2_wr_full : out std_logic;
p2_wr_empty : out std_logic;
p2_wr_count : out std_logic_vector(6 DOWNTO 0);
p2_wr_underrun : out std_logic;
p2_wr_error : out std_logic;
p2_rd_clk : in std_logic;
p2_rd_en : in std_logic;
p2_rd_data : out std_logic_vector(31 DOWNTO 0);
p2_rd_full : out std_logic;
p2_rd_empty : out std_logic;
p2_rd_count : out std_logic_vector(6 DOWNTO 0);
p2_rd_overflow : out std_logic;
p2_rd_error : out std_logic;
p3_arb_en : in std_logic;
p3_cmd_clk : in std_logic;
p3_cmd_en : in std_logic;
p3_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p3_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p3_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p3_cmd_empty : out std_logic;
p3_cmd_full : out std_logic;
p3_wr_clk : in std_logic;
p3_wr_en : in std_logic;
p3_wr_mask : in std_logic_vector(3 DOWNTO 0);
p3_wr_data : in std_logic_vector(31 DOWNTO 0);
p3_wr_full : out std_logic;
p3_wr_empty : out std_logic;
p3_wr_count : out std_logic_vector(6 DOWNTO 0);
p3_wr_underrun : out std_logic;
p3_wr_error : out std_logic;
p3_rd_clk : in std_logic;
p3_rd_en : in std_logic;
p3_rd_data : out std_logic_vector(31 DOWNTO 0);
p3_rd_full : out std_logic;
p3_rd_empty : out std_logic;
p3_rd_count : out std_logic_vector(6 DOWNTO 0);
p3_rd_overflow : out std_logic;
p3_rd_error : out std_logic;
p4_arb_en : in std_logic;
p4_cmd_clk : in std_logic;
p4_cmd_en : in std_logic;
p4_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p4_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p4_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p4_cmd_empty : out std_logic;
p4_cmd_full : out std_logic;
p4_wr_clk : in std_logic;
p4_wr_en : in std_logic;
p4_wr_mask : in std_logic_vector(3 DOWNTO 0);
p4_wr_data : in std_logic_vector(31 DOWNTO 0);
p4_wr_full : out std_logic;
p4_wr_empty : out std_logic;
p4_wr_count : out std_logic_vector(6 DOWNTO 0);
p4_wr_underrun : out std_logic;
p4_wr_error : out std_logic;
p4_rd_clk : in std_logic;
p4_rd_en : in std_logic;
p4_rd_data : out std_logic_vector(31 DOWNTO 0);
p4_rd_full : out std_logic;
p4_rd_empty : out std_logic;
p4_rd_count : out std_logic_vector(6 DOWNTO 0);
p4_rd_overflow : out std_logic;
p4_rd_error : out std_logic;
p5_arb_en : in std_logic;
p5_cmd_clk : in std_logic;
p5_cmd_en : in std_logic;
p5_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p5_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p5_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p5_cmd_empty : out std_logic;
p5_cmd_full : out std_logic;
p5_wr_clk : in std_logic;
p5_wr_en : in std_logic;
p5_wr_mask : in std_logic_vector(3 DOWNTO 0);
p5_wr_data : in std_logic_vector(31 DOWNTO 0);
p5_wr_full : out std_logic;
p5_wr_empty : out std_logic;
p5_wr_count : out std_logic_vector(6 DOWNTO 0);
p5_wr_underrun : out std_logic;
p5_wr_error : out std_logic;
p5_rd_clk : in std_logic;
p5_rd_en : in std_logic;
p5_rd_data : out std_logic_vector(31 DOWNTO 0);
p5_rd_full : out std_logic;
p5_rd_empty : out std_logic;
p5_rd_count : out std_logic_vector(6 DOWNTO 0);
p5_rd_overflow : out std_logic;
p5_rd_error : out std_logic;
mcbx_dram_addr : out std_logic_vector(C_MEM_ADDR_WIDTH - 1 DOWNTO 0);
mcbx_dram_ba : out std_logic_vector(C_MEM_BANKADDR_WIDTH - 1 DOWNTO 0);
mcbx_dram_ras_n : out std_logic;
mcbx_dram_cas_n : out std_logic;
mcbx_dram_we_n : out std_logic;
mcbx_dram_cke : out std_logic;
mcbx_dram_clk : out std_logic;
mcbx_dram_clk_n : out std_logic;
mcbx_dram_dq : inout std_logic_vector(C_NUM_DQ_PINS-1 DOWNTO 0);
mcbx_dram_dqs : inout std_logic;
mcbx_dram_dqs_n : inout std_logic;
mcbx_dram_udqs : inout std_logic;
mcbx_dram_udqs_n : inout std_logic;
mcbx_dram_udm : out std_logic;
mcbx_dram_ldm : out std_logic;
mcbx_dram_odt : out std_logic;
mcbx_dram_ddr3_rst : out std_logic;
calib_recal : in std_logic;
rzq : inout std_logic;
zio : inout std_logic;
ui_read : in std_logic;
ui_add : in std_logic;
ui_cs : in std_logic;
ui_clk : in std_logic;
ui_sdi : in std_logic;
ui_addr : in std_logic_vector(4 DOWNTO 0);
ui_broadcast : in std_logic;
ui_drp_update : in std_logic;
ui_done_cal : in std_logic;
ui_cmd : in std_logic;
ui_cmd_in : in std_logic;
ui_cmd_en : in std_logic;
ui_dqcount : in std_logic_vector(3 DOWNTO 0);
ui_dq_lower_dec : in std_logic;
ui_dq_lower_inc : in std_logic;
ui_dq_upper_dec : in std_logic;
ui_dq_upper_inc : in std_logic;
ui_udqs_inc : in std_logic;
ui_udqs_dec : in std_logic;
ui_ldqs_inc : in std_logic;
ui_ldqs_dec : in std_logic;
uo_data : out std_logic_vector(7 DOWNTO 0);
uo_data_valid : out std_logic;
uo_done_cal : out std_logic;
uo_cmd_ready_in : out std_logic;
uo_refrsh_flag : out std_logic;
uo_cal_start : out std_logic;
uo_sdo : out std_logic;
status : out std_logic_vector(31 DOWNTO 0);
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end component;
signal uo_data : std_logic_vector(7 downto 0);
constant C_PORT_ENABLE : std_logic_vector(5 downto 0) := "000001";
constant C_PORT_CONFIG : string := "B32_B32_R32_R32_R32_R32";
constant ARB_TIME_SLOT_0 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_0(2 downto 0));
constant ARB_TIME_SLOT_1 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_1(2 downto 0));
constant ARB_TIME_SLOT_2 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_2(2 downto 0));
constant ARB_TIME_SLOT_3 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_3(2 downto 0));
constant ARB_TIME_SLOT_4 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_4(2 downto 0));
constant ARB_TIME_SLOT_5 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_5(2 downto 0));
constant ARB_TIME_SLOT_6 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_6(2 downto 0));
constant ARB_TIME_SLOT_7 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_7(2 downto 0));
constant ARB_TIME_SLOT_8 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_8(2 downto 0));
constant ARB_TIME_SLOT_9 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_9(2 downto 0));
constant ARB_TIME_SLOT_10 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_10(2 downto 0));
constant ARB_TIME_SLOT_11 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_11(2 downto 0));
constant C_MC_CALIBRATION_CLK_DIV : integer := 1;
constant C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000" + "0000010000"; -- 16 cycles are added to avoid trfc violations
constant C_SKIP_DYN_IN_TERM : integer := 1;
constant C_MC_CALIBRATION_RA : bit_vector(15 downto 0) := X"0000";
constant C_MC_CALIBRATION_BA : bit_vector(2 downto 0) := o"0";
constant C_MC_CALIBRATION_CA : bit_vector(11 downto 0) := X"000";
constant C_MEM_DDR3_DYN_WRT_ODT : string := "OFF";
signal status : std_logic_vector(31 downto 0);
signal uo_data_valid : std_logic;
signal uo_cmd_ready_in : std_logic;
signal uo_refrsh_flag : std_logic;
signal uo_cal_start : std_logic;
signal uo_sdo : std_logic;
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of acch : architecture IS
"mig_v3_9_ddr3_s6, Coregen 13.3";
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of acch : architecture IS "mcb1_ddr3_s6,mig_v3_9,{LANGUAGE=VHDL, SYNTHESIS_TOOL=ISE, NO_OF_CONTROLLERS=2, AXI_ENABLE=0, MEM_INTERFACE_TYPE=DDR3_SDRAM, CLK_PERIOD=2500, MEMORY_PART=mt41j128m16xx-15e, MEMORY_DEVICE_WIDTH=16, OUTPUT_DRV=DIV6, RTT_NOM=DIV4, AUTO_SR=ENABLED, HIGH_TEMP_SR=NORMAL, PORT_CONFIG=Two 32-bit bi-directional and four 32-bit unidirectional ports, MEM_ADDR_ORDER=ROW_BANK_COLUMN, PORT_ENABLE=Port0, INPUT_PIN_TERMINATION=CALIB_TERM, DATA_TERMINATION=25 Ohms, CLKFBOUT_MULT_F=2, CLKOUT_DIVIDE=1, DEBUG_PORT=0, INPUT_CLK_TYPE=Differential}";
begin
memc1_mcb_raw_wrapper_inst : mcb_raw_wrapper
generic map
(
C_MEMCLK_PERIOD => C_MEMCLK_PERIOD,
C_P0_MASK_SIZE => C_P0_MASK_SIZE,
C_P0_DATA_PORT_SIZE => C_P0_DATA_PORT_SIZE,
C_P1_MASK_SIZE => C_P1_MASK_SIZE,
C_P1_DATA_PORT_SIZE => C_P1_DATA_PORT_SIZE,
C_ARB_NUM_TIME_SLOTS => C_ARB_NUM_TIME_SLOTS,
C_ARB_TIME_SLOT_0 => ARB_TIME_SLOT_0,
C_ARB_TIME_SLOT_1 => ARB_TIME_SLOT_1,
C_ARB_TIME_SLOT_2 => ARB_TIME_SLOT_2,
C_ARB_TIME_SLOT_3 => ARB_TIME_SLOT_3,
C_ARB_TIME_SLOT_4 => ARB_TIME_SLOT_4,
C_ARB_TIME_SLOT_5 => ARB_TIME_SLOT_5,
C_ARB_TIME_SLOT_6 => ARB_TIME_SLOT_6,
C_ARB_TIME_SLOT_7 => ARB_TIME_SLOT_7,
C_ARB_TIME_SLOT_8 => ARB_TIME_SLOT_8,
C_ARB_TIME_SLOT_9 => ARB_TIME_SLOT_9,
C_ARB_TIME_SLOT_10 => ARB_TIME_SLOT_10,
C_ARB_TIME_SLOT_11 => ARB_TIME_SLOT_11,
C_PORT_CONFIG => C_PORT_CONFIG,
C_PORT_ENABLE => C_PORT_ENABLE,
C_MEM_TRAS => C_MEM_TRAS,
C_MEM_TRCD => C_MEM_TRCD,
C_MEM_TREFI => C_MEM_TREFI,
C_MEM_TRFC => C_MEM_TRFC,
C_MEM_TRP => C_MEM_TRP,
C_MEM_TWR => C_MEM_TWR,
C_MEM_TRTP => C_MEM_TRTP,
C_MEM_TWTR => C_MEM_TWTR,
C_MEM_ADDR_ORDER => C_MEM_ADDR_ORDER,
C_NUM_DQ_PINS => C_NUM_DQ_PINS,
C_MEM_TYPE => C_MEM_TYPE,
C_MEM_DENSITY => C_MEM_DENSITY,
C_MEM_BURST_LEN => C_MEM_BURST_LEN,
C_MEM_CAS_LATENCY => C_MEM_CAS_LATENCY,
C_MEM_ADDR_WIDTH => C_MEM_ADDR_WIDTH,
C_MEM_BANKADDR_WIDTH => C_MEM_BANKADDR_WIDTH,
C_MEM_NUM_COL_BITS => C_MEM_NUM_COL_BITS,
C_MEM_DDR1_2_ODS => C_MEM_DDR1_2_ODS,
C_MEM_DDR2_RTT => C_MEM_DDR2_RTT,
C_MEM_DDR2_DIFF_DQS_EN => C_MEM_DDR2_DIFF_DQS_EN,
C_MEM_DDR2_3_PA_SR => C_MEM_DDR2_3_PA_SR,
C_MEM_DDR2_3_HIGH_TEMP_SR => C_MEM_DDR2_3_HIGH_TEMP_SR,
C_MEM_DDR3_CAS_LATENCY => C_MEM_DDR3_CAS_LATENCY,
C_MEM_DDR3_ODS => C_MEM_DDR3_ODS,
C_MEM_DDR3_RTT => C_MEM_DDR3_RTT,
C_MEM_DDR3_CAS_WR_LATENCY => C_MEM_DDR3_CAS_WR_LATENCY,
C_MEM_DDR3_AUTO_SR => C_MEM_DDR3_AUTO_SR,
C_MEM_DDR3_DYN_WRT_ODT => C_MEM_DDR3_DYN_WRT_ODT,
C_MEM_MOBILE_PA_SR => C_MEM_MOBILE_PA_SR,
C_MEM_MDDR_ODS => C_MEM_MDDR_ODS,
C_MC_CALIBRATION_CLK_DIV => C_MC_CALIBRATION_CLK_DIV,
C_MC_CALIBRATION_MODE => C_MC_CALIBRATION_MODE,
C_MC_CALIBRATION_DELAY => C_MC_CALIBRATION_DELAY,
C_MC_CALIB_BYPASS => C_MC_CALIB_BYPASS,
C_MC_CALIBRATION_RA => C_MC_CALIBRATION_RA,
C_MC_CALIBRATION_BA => C_MC_CALIBRATION_BA,
C_MC_CALIBRATION_CA => C_MC_CALIBRATION_CA,
C_CALIB_SOFT_IP => C_CALIB_SOFT_IP,
C_SIMULATION => C_SIMULATION,
C_SKIP_IN_TERM_CAL => C_SKIP_IN_TERM_CAL,
C_SKIP_DYNAMIC_CAL => C_SKIP_DYNAMIC_CAL,
C_SKIP_DYN_IN_TERM => C_SKIP_DYN_IN_TERM,
C_MEM_TZQINIT_MAXCNT => C_MEM_TZQINIT_MAXCNT,
LDQSP_TAP_DELAY_VAL => C_LDQSP_TAP_DELAY_VAL,
UDQSP_TAP_DELAY_VAL => C_UDQSP_TAP_DELAY_VAL,
LDQSN_TAP_DELAY_VAL => C_LDQSN_TAP_DELAY_VAL,
UDQSN_TAP_DELAY_VAL => C_UDQSN_TAP_DELAY_VAL,
DQ0_TAP_DELAY_VAL => C_DQ0_TAP_DELAY_VAL,
DQ1_TAP_DELAY_VAL => C_DQ1_TAP_DELAY_VAL,
DQ2_TAP_DELAY_VAL => C_DQ2_TAP_DELAY_VAL,
DQ3_TAP_DELAY_VAL => C_DQ3_TAP_DELAY_VAL,
DQ4_TAP_DELAY_VAL => C_DQ4_TAP_DELAY_VAL,
DQ5_TAP_DELAY_VAL => C_DQ5_TAP_DELAY_VAL,
DQ6_TAP_DELAY_VAL => C_DQ6_TAP_DELAY_VAL,
DQ7_TAP_DELAY_VAL => C_DQ7_TAP_DELAY_VAL,
DQ8_TAP_DELAY_VAL => C_DQ8_TAP_DELAY_VAL,
DQ9_TAP_DELAY_VAL => C_DQ9_TAP_DELAY_VAL,
DQ10_TAP_DELAY_VAL => C_DQ10_TAP_DELAY_VAL,
DQ11_TAP_DELAY_VAL => C_DQ11_TAP_DELAY_VAL,
DQ12_TAP_DELAY_VAL => C_DQ12_TAP_DELAY_VAL,
DQ13_TAP_DELAY_VAL => C_DQ13_TAP_DELAY_VAL,
DQ14_TAP_DELAY_VAL => C_DQ14_TAP_DELAY_VAL,
DQ15_TAP_DELAY_VAL => C_DQ15_TAP_DELAY_VAL
)
port map
(
sys_rst => async_rst,
sysclk_2x => sysclk_2x,
sysclk_2x_180 => sysclk_2x_180,
pll_ce_0 => pll_ce_0,
pll_ce_90 => pll_ce_90,
pll_lock => pll_lock,
mcbx_dram_addr => mcb1_dram_a,
mcbx_dram_ba => mcb1_dram_ba,
mcbx_dram_ras_n => mcb1_dram_ras_n,
mcbx_dram_cas_n => mcb1_dram_cas_n,
mcbx_dram_we_n => mcb1_dram_we_n,
mcbx_dram_cke => mcb1_dram_cke,
mcbx_dram_clk => mcb1_dram_ck,
mcbx_dram_clk_n => mcb1_dram_ck_n,
mcbx_dram_dq => mcb1_dram_dq,
mcbx_dram_odt => mcb1_dram_odt,
mcbx_dram_ldm => mcb1_dram_dm,
mcbx_dram_udm => mcb1_dram_udm,
mcbx_dram_dqs => mcb1_dram_dqs,
mcbx_dram_dqs_n => mcb1_dram_dqs_n,
mcbx_dram_udqs => mcb1_dram_udqs,
mcbx_dram_udqs_n => mcb1_dram_udqs_n,
mcbx_dram_ddr3_rst => mcb1_dram_reset_n,
calib_recal => '0',
rzq => mcb1_rzq,
zio => mcb1_zio,
ui_read => '0',
ui_add => '0',
ui_cs => '0',
ui_clk => mcb_drp_clk,
ui_sdi => '0',
ui_addr => (others => '0'),
ui_broadcast => '0',
ui_drp_update => '0',
ui_done_cal => '1',
ui_cmd => '0',
ui_cmd_in => '0',
ui_cmd_en => '0',
ui_dqcount => (others => '0'),
ui_dq_lower_dec => '0',
ui_dq_lower_inc => '0',
ui_dq_upper_dec => '0',
ui_dq_upper_inc => '0',
ui_udqs_inc => '0',
ui_udqs_dec => '0',
ui_ldqs_inc => '0',
ui_ldqs_dec => '0',
uo_data => uo_data,
uo_data_valid => uo_data_valid,
uo_done_cal => calib_done,
uo_cmd_ready_in => uo_cmd_ready_in,
uo_refrsh_flag => uo_refrsh_flag,
uo_cal_start => uo_cal_start,
uo_sdo => uo_sdo,
status => status,
selfrefresh_enter => '0',
selfrefresh_mode => selfrefresh_mode,
p0_arb_en => '1',
p0_cmd_clk => p0_cmd_clk,
p0_cmd_en => p0_cmd_en,
p0_cmd_instr => p0_cmd_instr,
p0_cmd_bl => p0_cmd_bl,
p0_cmd_byte_addr => p0_cmd_byte_addr,
p0_cmd_empty => p0_cmd_empty,
p0_cmd_full => p0_cmd_full,
p0_wr_clk => p0_wr_clk,
p0_wr_en => p0_wr_en,
p0_wr_mask => p0_wr_mask,
p0_wr_data => p0_wr_data,
p0_wr_full => p0_wr_full,
p0_wr_empty => p0_wr_empty,
p0_wr_count => p0_wr_count,
p0_wr_underrun => p0_wr_underrun,
p0_wr_error => p0_wr_error,
p0_rd_clk => p0_rd_clk,
p0_rd_en => p0_rd_en,
p0_rd_data => p0_rd_data,
p0_rd_full => p0_rd_full,
p0_rd_empty => p0_rd_empty,
p0_rd_count => p0_rd_count,
p0_rd_overflow => p0_rd_overflow,
p0_rd_error => p0_rd_error,
p1_arb_en => '0',
p1_cmd_clk => '0',
p1_cmd_en => '0',
p1_cmd_instr => (others => '0'),
p1_cmd_bl => (others => '0'),
p1_cmd_byte_addr => (others => '0'),
p1_cmd_empty => open,
p1_cmd_full => open,
p1_rd_clk => '0',
p1_rd_en => '0',
p1_rd_data => open,
p1_rd_full => open,
p1_rd_empty => open,
p1_rd_count => open,
p1_rd_overflow => open,
p1_rd_error => open,
p1_wr_clk => '0',
p1_wr_en => '0',
p1_wr_mask => (others => '0'),
p1_wr_data => (others => '0'),
p1_wr_full => open,
p1_wr_empty => open,
p1_wr_count => open,
p1_wr_underrun => open,
p1_wr_error => open,
p2_arb_en => '0',
p2_cmd_clk => '0',
p2_cmd_en => '0',
p2_cmd_instr => (others => '0'),
p2_cmd_bl => (others => '0'),
p2_cmd_byte_addr => (others => '0'),
p2_cmd_empty => open,
p2_cmd_full => open,
p2_rd_clk => '0',
p2_rd_en => '0',
p2_rd_data => open,
p2_rd_full => open,
p2_rd_empty => open,
p2_rd_count => open,
p2_rd_overflow => open,
p2_rd_error => open,
p2_wr_clk => '0',
p2_wr_en => '0',
p2_wr_mask => (others => '0'),
p2_wr_data => (others => '0'),
p2_wr_full => open,
p2_wr_empty => open,
p2_wr_count => open,
p2_wr_underrun => open,
p2_wr_error => open,
p3_arb_en => '0',
p3_cmd_clk => '0',
p3_cmd_en => '0',
p3_cmd_instr => (others => '0'),
p3_cmd_bl => (others => '0'),
p3_cmd_byte_addr => (others => '0'),
p3_cmd_empty => open,
p3_cmd_full => open,
p3_rd_clk => '0',
p3_rd_en => '0',
p3_rd_data => open,
p3_rd_full => open,
p3_rd_empty => open,
p3_rd_count => open,
p3_rd_overflow => open,
p3_rd_error => open,
p3_wr_clk => '0',
p3_wr_en => '0',
p3_wr_mask => (others => '0'),
p3_wr_data => (others => '0'),
p3_wr_full => open,
p3_wr_empty => open,
p3_wr_count => open,
p3_wr_underrun => open,
p3_wr_error => open,
p4_arb_en => '0',
p4_cmd_clk => '0',
p4_cmd_en => '0',
p4_cmd_instr => (others => '0'),
p4_cmd_bl => (others => '0'),
p4_cmd_byte_addr => (others => '0'),
p4_cmd_empty => open,
p4_cmd_full => open,
p4_rd_clk => '0',
p4_rd_en => '0',
p4_rd_data => open,
p4_rd_full => open,
p4_rd_empty => open,
p4_rd_count => open,
p4_rd_overflow => open,
p4_rd_error => open,
p4_wr_clk => '0',
p4_wr_en => '0',
p4_wr_mask => (others => '0'),
p4_wr_data => (others => '0'),
p4_wr_full => open,
p4_wr_empty => open,
p4_wr_count => open,
p4_wr_underrun => open,
p4_wr_error => open,
p5_arb_en => '0',
p5_cmd_clk => '0',
p5_cmd_en => '0',
p5_cmd_instr => (others => '0'),
p5_cmd_bl => (others => '0'),
p5_cmd_byte_addr => (others => '0'),
p5_cmd_empty => open,
p5_cmd_full => open,
p5_rd_clk => '0',
p5_rd_en => '0',
p5_rd_data => open,
p5_rd_full => open,
p5_rd_empty => open,
p5_rd_count => open,
p5_rd_overflow => open,
p5_rd_error => open,
p5_wr_clk => '0',
p5_wr_en => '0',
p5_wr_mask => (others => '0'),
p5_wr_data => (others => '0'),
p5_wr_full => open,
p5_wr_empty => open,
p5_wr_count => open,
p5_wr_underrun => open,
p5_wr_error => open
);
end architecture;
| gpl-3.0 | 3569bef37ccf7c2e761087e806f90466 | 0.415549 | 3.553082 | false | false | false | false |
timofonic/PHDL | misc/projects/spartan_pcie_board/fpga/lx45t_pinout/ipcore_dir/pcie_core/source/pcie_brams_s6.vhd | 1 | 10,572 | -------------------------------------------------------------------------------
--
-- (c) Copyright 2008, 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
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-- Applications"). Customer assumes the sole risk and
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-- Applications, subject only to applicable laws and
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Project : Spartan-6 Integrated Block for PCI Express
-- File : pcie_brams_s6.vhd
-- Description: BlockRAM module for Spartan-6 PCIe Block
--
-- Arranges and connects brams
-- Implements address decoding, datapath muxing and
-- pipeline stages
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity pcie_brams_s6 is
generic (
-- the number of BRAMs to use
-- supported values are:
-- 1,2,4,9
NUM_BRAMS : integer := 0;
-- BRAM read address latency
--
-- value meaning
-- ====================================================
-- 0 BRAM read address port sample
-- 1 BRAM read address port sample and a pipeline stage on the address port
RAM_RADDR_LATENCY : integer := 1;
-- BRAM read data latency
--
-- value meaning
-- ====================================================
-- 1 no BRAM OREG
-- 2 use BRAM OREG
-- 3 use BRAM OREG and a pipeline stage on the data port
RAM_RDATA_LATENCY : integer := 1;
-- BRAM write latency
-- The BRAM write port is synchronous
--
-- value meaning
-- ====================================================
-- 0 BRAM write port sample
-- 1 BRAM write port sample plus pipeline stage
RAM_WRITE_LATENCY : integer := 1
);
port (
user_clk_i : in std_logic;
reset_i : in std_logic;
wen : in std_logic;
waddr : in std_logic_vector(11 downto 0);
wdata : in std_logic_vector(35 downto 0);
ren : in std_logic;
rce : in std_logic;
raddr : in std_logic_vector(11 downto 0);
rdata : out std_logic_vector(35 downto 0)
);
end pcie_brams_s6;
architecture rtl of pcie_brams_s6 is
constant TCQ : time := 1 ns; -- Clock-to-out delay to be modeled
-- Turn on the bram output register
function CALC_DOB_REG(constant RAM_RDATA_LATENCY : in integer) return integer is
variable DOB_REG : integer;
begin
if (RAM_RDATA_LATENCY > 1) then DOB_REG := 1;
else DOB_REG := 0;
end if;
return DOB_REG;
end function CALC_DOB_REG;
-- Calculate the data width of the individual BRAMs
function CALC_WIDTH(constant NUM_BRAMS : in integer) return integer is
variable WIDTH : integer;
begin
if (NUM_BRAMS = 1) then WIDTH := 36;
elsif (NUM_BRAMS = 2) then WIDTH := 18;
elsif (NUM_BRAMS = 4) then WIDTH := 9;
else WIDTH := 4; -- NUM_BRAMS = 9
end if;
return WIDTH;
end function CALC_WIDTH;
component pcie_bram_s6 is
generic (
DOB_REG : integer;
WIDTH : integer
);
port (
user_clk_i : in std_logic;
reset_i : in std_logic;
wen_i : in std_logic;
waddr_i : in std_logic_vector(11 downto 0);
wdata_i : in std_logic_vector(CALC_WIDTH(NUM_BRAMS)-1 downto 0);
ren_i : in std_logic;
rce_i : in std_logic;
raddr_i : in std_logic_vector(11 downto 0);
rdata_o : out std_logic_vector(CALC_WIDTH(NUM_BRAMS)-1 downto 0) -- read data
);
end component;
-- Model the delays for RAM write latency
signal wen_int : std_logic;
signal waddr_int : std_logic_vector(11 downto 0);
signal wdata_int : std_logic_vector(35 downto 0);
signal wen_dly : std_logic;
signal waddr_dly : std_logic_vector(11 downto 0);
signal wdata_dly : std_logic_vector(35 downto 0);
-- Model the delays for RAM read latency
signal ren_int : std_logic;
signal raddr_int : std_logic_vector(11 downto 0);
signal rdata_int : std_logic_vector(35 downto 0);
signal ren_dly : std_logic;
signal raddr_dly : std_logic_vector(11 downto 0);
signal rdata_dly : std_logic_vector(35 downto 0);
begin
--synthesis translate_off
process begin
case NUM_BRAMS is
when 1 | 2 | 4 | 9 =>
null;
when others =>
report "Error NUM_BRAMS size " & integer'image(NUM_BRAMS) & " is not supported." severity failure;
end case; -- case NUM_BRAMS
case RAM_RADDR_LATENCY is
when 0 | 1 =>
null;
when others =>
report "Error RAM_RADDR_LATENCY size " & integer'image(RAM_RADDR_LATENCY) & " is not supported." severity failure;
end case; -- case RAM_RADDR_LATENCY
case RAM_RDATA_LATENCY is
when 1 | 2 | 3 =>
null;
when others =>
report "Error RAM_RDATA_LATENCY size " & integer'image(RAM_RDATA_LATENCY) & " is not supported." severity failure;
end case; -- case RAM_RDATA_LATENCY
case RAM_WRITE_LATENCY is
when 0 | 1 =>
null;
when others =>
report "Error RAM_WRITE_LATENCY size " & integer'image(RAM_WRITE_LATENCY) & " is not supported." severity failure;
end case; -- case RAM_WRITE_LATENCY
wait;
end process;
--synthesis translate_on
-- 1 stage RAM write pipeline
wr_lat_1 : if(RAM_WRITE_LATENCY = 1) generate
process (user_clk_i) begin
if (user_clk_i'event and user_clk_i = '1') then
if (reset_i = '1') then
wen_dly <= '0' after TCQ;
waddr_dly <= (others => '0') after TCQ;
wdata_dly <= (others => '0') after TCQ;
else
wen_dly <= wen after TCQ;
waddr_dly <= waddr after TCQ;
wdata_dly <= wdata after TCQ;
end if;
end if;
end process;
wen_int <= wen_dly;
waddr_int <= waddr_dly;
wdata_int <= wdata_dly;
end generate wr_lat_1;
-- No RAM write pipeline
wr_lat_0 : if(RAM_WRITE_LATENCY /= 1) generate
wen_int <= wen;
waddr_int <= waddr;
wdata_int <= wdata;
end generate wr_lat_0;
-- 1 stage RAM read addr pipeline
raddr_lat_1 : if(RAM_RADDR_LATENCY = 1) generate
process (user_clk_i) begin
if (user_clk_i'event and user_clk_i = '1') then
if (reset_i = '1') then
ren_dly <= '0' after TCQ;
raddr_dly <= (others => '0') after TCQ;
else
ren_dly <= ren after TCQ;
raddr_dly <= raddr after TCQ;
end if;
end if;
end process;
ren_int <= ren_dly;
raddr_int <= raddr_dly;
end generate raddr_lat_1;
-- No RAM read addr pipeline
raddr_lat_0 : if(RAM_RADDR_LATENCY /= 1) generate
ren_int <= ren after TCQ;
raddr_int <= raddr after TCQ;
end generate raddr_lat_0;
-- 3 stages RAM read data pipeline (first is internal to BRAM)
rdata_lat_3 : if(RAM_RDATA_LATENCY = 3) generate
process (user_clk_i) begin
if (user_clk_i'event and user_clk_i = '1') then
if (reset_i = '1') then
rdata_dly <= (others => '0') after TCQ;
else
rdata_dly <= rdata_int after TCQ;
end if;
end if;
end process;
rdata <= rdata_dly;
end generate rdata_lat_3;
-- 1 or 2 stages RAM read data pipeline
rdata_lat_1_2 : if(RAM_RDATA_LATENCY /= 3) generate
rdata <= rdata_int;
end generate rdata_lat_1_2;
-- Instantiate BRAM(s)
brams : for i in 0 to (NUM_BRAMS - 1) generate
begin
ram : pcie_bram_s6
generic map (
DOB_REG => CALC_DOB_REG(RAM_RDATA_LATENCY),
WIDTH => CALC_WIDTH(NUM_BRAMS)
)
port map (
user_clk_i => user_clk_i,
reset_i => reset_i,
wen_i => wen_int,
waddr_i => waddr_int,
wdata_i => wdata_int((((i + 1) * CALC_WIDTH(NUM_BRAMS)) - 1) downto (i * CALC_WIDTH(NUM_BRAMS))),
ren_i => ren_int,
rce_i => rce,
raddr_i => raddr_int,
rdata_o => rdata_int((((i + 1) * CALC_WIDTH(NUM_BRAMS)) - 1) downto (i * CALC_WIDTH(NUM_BRAMS)))
);
end generate brams;
end rtl;
| gpl-3.0 | 7563682856aa284c1c7ad2d7b8d2cf0b | 0.574631 | 3.875367 | false | false | false | false |
timofonic/PHDL | misc/projects/spartan_pcie_board/fpga/lx45t_pinout/ipcore_dir/pcie_core/example_design/PIO_EP_MEM.vhd | 1 | 14,304 | -------------------------------------------------------------------------------
--
-- (c) Copyright 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Project : Spartan-6 Integrated Block for PCI Express
-- File : PIO_EP_MEM.vhd
-- Description: Endpoint Memory: 8KB organized as 4 x (512 DW) BlockRAM banks.
-- Block RAM Port A: Read Port
-- Block RAM Port B: Write Port
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity PIO_EP_MEM is
port (
clk_i : in std_logic;
a_rd_a_i_0 : in std_logic_vector(8 downto 0);
a_rd_d_o_0 : out std_logic_vector(31 downto 0);
a_rd_en_i_0 : in std_logic;
b_wr_a_i_0 : in std_logic_vector(8 downto 0);
b_wr_d_i_0 : in std_logic_vector(31 downto 0);
b_wr_en_i_0 : in std_logic;
b_rd_d_o_0 : out std_logic_vector(31 downto 0);
b_rd_en_i_0 : in std_logic;
a_rd_a_i_1 : in std_logic_vector(8 downto 0);
a_rd_d_o_1 : out std_logic_vector(31 downto 0);
a_rd_en_i_1 : in std_logic;
b_wr_a_i_1 : in std_logic_vector(8 downto 0);
b_wr_d_i_1 : in std_logic_vector(31 downto 0);
b_wr_en_i_1 : in std_logic;
b_rd_d_o_1 : out std_logic_vector(31 downto 0);
b_rd_en_i_1 : in std_logic;
a_rd_a_i_2 : in std_logic_vector(8 downto 0);
a_rd_d_o_2 : out std_logic_vector(31 downto 0);
a_rd_en_i_2 : in std_logic;
b_wr_a_i_2 : in std_logic_vector(8 downto 0);
b_wr_d_i_2 : in std_logic_vector(31 downto 0);
b_wr_en_i_2 : in std_logic;
b_rd_d_o_2 : out std_logic_vector(31 downto 0);
b_rd_en_i_2 : in std_logic;
a_rd_a_i_3 : in std_logic_vector(8 downto 0);
a_rd_d_o_3 : out std_logic_vector(31 downto 0);
a_rd_en_i_3 : in std_logic;
b_wr_a_i_3 : in std_logic_vector(8 downto 0);
b_wr_d_i_3 : in std_logic_vector(31 downto 0);
b_wr_en_i_3 : in std_logic;
b_rd_d_o_3 : out std_logic_vector(31 downto 0);
b_rd_en_i_3 : in std_logic
);
end PIO_EP_MEM;
architecture rtl of PIO_EP_MEM is
signal a_rd_a_0_int : std_logic_vector(13 downto 0);
signal b_wr_a_0_int : std_logic_vector(13 downto 0);
signal b_wr_en_0_int : std_logic_vector(3 downto 0);
signal a_rd_a_1_int : std_logic_vector(13 downto 0);
signal b_wr_a_1_int : std_logic_vector(13 downto 0);
signal b_wr_en_1_int : std_logic_vector(3 downto 0);
signal a_rd_a_2_int : std_logic_vector(13 downto 0);
signal b_wr_a_2_int : std_logic_vector(13 downto 0);
signal b_wr_en_2_int : std_logic_vector(3 downto 0);
signal a_rd_a_3_int : std_logic_vector(13 downto 0);
signal b_wr_a_3_int : std_logic_vector(13 downto 0);
signal b_wr_en_3_int : std_logic_vector(3 downto 0);
begin
------------------------------------------------------------------
--
-- 4 x 512 DWs Buffer Banks (512 x 32 bits + 512 x 4 bits)
--
------------------------------------------------------------------
a_rd_a_0_int <= a_rd_a_i_0 & "00000";
b_wr_a_0_int <= b_wr_a_i_0 & "00000";
b_wr_en_0_int <= b_wr_en_i_0 & b_wr_en_i_0 & b_wr_en_i_0 & b_wr_en_i_0;
ep_io_mem : RAMB16BWER
generic map (
DOA_REG => 1, -- Optional output registers on A port (0 or 1)
DOB_REG => 1, -- Optional output registers on B port (0 or 1)
DATA_WIDTH_A => 36, -- Valid values are 1, 2, 4, 9, 18, or 36
DATA_WIDTH_B => 36, -- Valid values are 1, 2, 4, 9, 18, or 36
SIM_COLLISION_CHECK => "ALL", -- Collision check enable "ALL", "WARNING_ONLY",
-- "GENERATE_X_ONLY" or "NONE"
WRITE_MODE_A => "WRITE_FIRST", -- "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE
WRITE_MODE_B => "WRITE_FIRST" -- "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE
)
port map (
DOA => a_rd_d_o_0, -- 32-bit A port data output
DOB => b_rd_d_o_0, -- 32-bit B port data output
DOPA => open, -- 4-bit A port parity data output
DOPB => open, -- 4-bit B port parity data output
ADDRA => a_rd_a_0_int, -- 15-bit A port address input
ADDRB => b_wr_a_0_int, -- 15-bit B port address input
CLKA => clk_i, -- 1-bit A port clock input
CLKB => clk_i, -- 1-bit B port clock input
DIA => (others => '0'), -- 32-bit A port data input
DIB => b_wr_d_i_0, -- 32-bit B port data input
DIPA => "0000", -- 4-bit A port parity data input
DIPB => "0000", -- 4-bit B port parity data input
ENA => a_rd_en_i_0, -- 1-bit A port enable input
ENB => b_rd_en_i_0, -- 1-bit B port enable input
REGCEA => '1', -- 1-bit A port register enable input
REGCEB => '1', -- 1-bit B port register enable input
RSTA => '0', -- 1-bit A port set/reset input
RSTB => '0', -- 1-bit B port set/reset input
WEA => "0000", -- 4-bit A port write enable input
WEB => b_wr_en_0_int -- 4-bit B port write enable input
);
a_rd_a_1_int <= a_rd_a_i_1 & "00000";
b_wr_a_1_int <= b_wr_a_i_1 & "00000";
b_wr_en_1_int <= b_wr_en_i_1 & b_wr_en_i_1 & b_wr_en_i_1 & b_wr_en_i_1;
ep_mem32 : RAMB16BWER
generic map (
DOA_REG => 1, -- Optional output registers on A port (0 or 1)
DOB_REG => 1, -- Optional output registers on B port (0 or 1)
DATA_WIDTH_A => 36, -- Valid values are 1, 2, 4, 9, 18, or 36
DATA_WIDTH_B => 36, -- Valid values are 1, 2, 4, 9, 18, or 36
SIM_COLLISION_CHECK => "ALL", -- Collision check enable "ALL", "WARNING_ONLY",
-- "GENERATE_X_ONLY" or "NONE"
WRITE_MODE_A => "WRITE_FIRST", -- "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE
WRITE_MODE_B => "WRITE_FIRST" -- "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE
)
port map (
DOA => a_rd_d_o_1, -- 32-bit A port data output
DOB => b_rd_d_o_1, -- 32-bit B port data output
DOPA => open, -- 4-bit A port parity data output
DOPB => open, -- 4-bit B port parity data output
ADDRA => a_rd_a_1_int, -- 15-bit A port address input
ADDRB => b_wr_a_1_int, -- 15-bit B port address input
CLKA => clk_i, -- 1-bit A port clock input
CLKB => clk_i, -- 1-bit B port clock input
DIA => (others => '0'), -- 32-bit A port data input
DIB => b_wr_d_i_1, -- 32-bit B port data input
DIPA => "0000", -- 4-bit A port parity data input
DIPB => "0000", -- 4-bit B port parity data input
ENA => a_rd_en_i_1, -- 1-bit A port enable input
ENB => b_rd_en_i_1, -- 1-bit B port enable input
REGCEA => '1', -- 1-bit A port register enable input
REGCEB => '1', -- 1-bit B port register enable input
RSTA => '0', -- 1-bit A port set/reset input
RSTB => '0', -- 1-bit B port set/reset input
WEA => "0000", -- 4-bit A port write enable input
WEB => b_wr_en_1_int -- 4-bit B port write enable input
);
a_rd_a_2_int <= a_rd_a_i_2 & "00000";
b_wr_a_2_int <= b_wr_a_i_2 & "00000";
b_wr_en_2_int <= b_wr_en_i_2 & b_wr_en_i_2 & b_wr_en_i_2 & b_wr_en_i_2;
ep_mem64 : RAMB16BWER
generic map (
DOA_REG => 1, -- Optional output registers on A port (0 or 1)
DOB_REG => 1, -- Optional output registers on B port (0 or 1)
DATA_WIDTH_A => 36, -- Valid values are 1, 2, 4, 9, 18, or 36
DATA_WIDTH_B => 36, -- Valid values are 1, 2, 4, 9, 18, or 36
SIM_COLLISION_CHECK => "ALL", -- Collision check enable "ALL", "WARNING_ONLY",
-- "GENERATE_X_ONLY" or "NONE"
WRITE_MODE_A => "WRITE_FIRST", -- "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE
WRITE_MODE_B => "WRITE_FIRST" -- "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE
)
port map (
DOA => a_rd_d_o_2, -- 32-bit A port data output
DOB => b_rd_d_o_2, -- 32-bit B port data output
DOPA => open, -- 4-bit A port parity data output
DOPB => open, -- 4-bit B port parity data output
ADDRA => a_rd_a_2_int, -- 15-bit A port address input
ADDRB => b_wr_a_2_int, -- 15-bit B port address input
CLKA => clk_i, -- 1-bit A port clock input
CLKB => clk_i, -- 1-bit B port clock input
DIA => (others => '0'), -- 32-bit A port data input
DIB => b_wr_d_i_2, -- 32-bit B port data input
DIPA => "0000", -- 4-bit A port parity data input
DIPB => "0000", -- 4-bit B port parity data input
ENA => a_rd_en_i_2, -- 1-bit A port enable input
ENB => b_rd_en_i_2, -- 1-bit B port enable input
REGCEA => '1', -- 1-bit A port register enable input
REGCEB => '1', -- 1-bit B port register enable input
RSTA => '0', -- 1-bit A port set/reset input
RSTB => '0', -- 1-bit B port set/reset input
WEA => "0000", -- 4-bit A port write enable input
WEB => b_wr_en_2_int -- 4-bit B port write enable input
);
a_rd_a_3_int <= a_rd_a_i_3 & "00000";
b_wr_a_3_int <= b_wr_a_i_3 & "00000";
b_wr_en_3_int <= b_wr_en_i_3 & b_wr_en_i_3 & b_wr_en_i_3 & b_wr_en_i_3;
ep_mem_erom : RAMB16BWER
generic map (
DOA_REG => 1, -- Optional output registers on A port (0 or 1)
DOB_REG => 1, -- Optional output registers on B port (0 or 1)
DATA_WIDTH_A => 36, -- Valid values are 1, 2, 4, 9, 18, or 36
DATA_WIDTH_B => 36, -- Valid values are 1, 2, 4, 9, 18, or 36
SIM_COLLISION_CHECK => "ALL", -- Collision check enable "ALL", "WARNING_ONLY",
-- "GENERATE_X_ONLY" or "NONE"
WRITE_MODE_A => "WRITE_FIRST", -- "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE
WRITE_MODE_B => "WRITE_FIRST" -- "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE
)
port map (
DOA => a_rd_d_o_3, -- 32-bit A port data output
DOB => b_rd_d_o_3, -- 32-bit B port data output
DOPA => open, -- 4-bit A port parity data output
DOPB => open, -- 4-bit B port parity data output
ADDRA => a_rd_a_3_int, -- 15-bit A port address input
ADDRB => b_wr_a_3_int, -- 15-bit B port address input
CLKA => clk_i, -- 1-bit A port clock input
CLKB => clk_i, -- 1-bit B port clock input
DIA => (others => '0'), -- 32-bit A port data input
DIB => b_wr_d_i_3, -- 32-bit B port data input
DIPA => "0000", -- 4-bit A port parity data input
DIPB => "0000", -- 4-bit B port parity data input
ENA => a_rd_en_i_3, -- 1-bit A port enable input
ENB => b_rd_en_i_3, -- 1-bit B port enable input
REGCEA => '1', -- 1-bit A port register enable input
REGCEB => '1', -- 1-bit B port register enable input
RSTA => '0', -- 1-bit A port set/reset input
RSTB => '0', -- 1-bit B port set/reset input
WEA => "0000", -- 4-bit A port write enable input
WEB => b_wr_en_3_int -- 4-bit B port write enable input
);
end; -- PIO_EP_MEM
| gpl-3.0 | 349d1793e9692ee46e081d8d769a6ad4 | 0.528873 | 3.175844 | false | false | false | false |
timofonic/PHDL | misc/projects/spartan_pcie_board/fpga/lx45t_pinout/ipcore_dir/pcie_core/simulation/dsport/pcie_gtx_v6.vhd | 1 | 33,963 | -------------------------------------------------------------------------------
--
-- (c) Copyright 2008, 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Project : Spartan-6 Integrated Block for PCI Express
-- File : pcie_gtx_v6.vhd
-- Description: GTX module for Virtex6 PCIe Block
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity pcie_gtx_v6 is
generic (
NO_OF_LANES : integer := 8; -- 1 - x1 , 2 - x2 , 4 - x4 , 8 - x8
LINK_CAP_MAX_LINK_SPEED : bit_vector := X"1"; -- 1 - Gen1, 2 - Gen2
REF_CLK_FREQ : integer := 0; -- 0 - 100 MHz , 1 - 125 MHz , 2 - 250 MHz
PL_FAST_TRAIN : boolean := FALSE
);
port (
-- Pipe Per-Link Signals
pipe_tx_rcvr_det : in std_logic;
pipe_tx_reset : in std_logic;
pipe_tx_rate : in std_logic;
pipe_tx_deemph : in std_logic;
pipe_tx_margin : in std_logic_vector(2 downto 0);
pipe_tx_swing : in std_logic;
-- Pipe Per-Lane Signals - Lane 0
pipe_rx0_char_is_k : out std_logic_vector(1 downto 0);
pipe_rx0_data : out std_logic_vector(15 downto 0);
pipe_rx0_valid : out std_logic;
pipe_rx0_chanisaligned : out std_logic;
pipe_rx0_status : out std_logic_vector(2 downto 0);
pipe_rx0_phy_status : out std_logic;
pipe_rx0_elec_idle : out std_logic;
pipe_rx0_polarity : in std_logic;
pipe_tx0_compliance : in std_logic;
pipe_tx0_char_is_k : in std_logic_vector(1 downto 0);
pipe_tx0_data : in std_logic_vector(15 downto 0);
pipe_tx0_elec_idle : in std_logic;
pipe_tx0_powerdown : in std_logic_vector(1 downto 0);
-- Pipe Per-Lane Signals - Lane 1
pipe_rx1_char_is_k : out std_logic_vector(1 downto 0);
pipe_rx1_data : out std_logic_vector(15 downto 0);
pipe_rx1_valid : out std_logic;
pipe_rx1_chanisaligned : out std_logic;
pipe_rx1_status : out std_logic_vector(2 downto 0);
pipe_rx1_phy_status : out std_logic;
pipe_rx1_elec_idle : out std_logic;
pipe_rx1_polarity : in std_logic;
pipe_tx1_compliance : in std_logic;
pipe_tx1_char_is_k : in std_logic_vector(1 downto 0);
pipe_tx1_data : in std_logic_vector(15 downto 0);
pipe_tx1_elec_idle : in std_logic;
pipe_tx1_powerdown : in std_logic_vector(1 downto 0);
-- Pipe Per-Lane Signals - Lane 2
pipe_rx2_char_is_k : out std_logic_vector(1 downto 0);
pipe_rx2_data : out std_logic_vector(15 downto 0);
pipe_rx2_valid : out std_logic;
pipe_rx2_chanisaligned : out std_logic;
pipe_rx2_status : out std_logic_vector(2 downto 0);
pipe_rx2_phy_status : out std_logic;
pipe_rx2_elec_idle : out std_logic;
pipe_rx2_polarity : in std_logic;
pipe_tx2_compliance : in std_logic;
pipe_tx2_char_is_k : in std_logic_vector(1 downto 0);
pipe_tx2_data : in std_logic_vector(15 downto 0);
pipe_tx2_elec_idle : in std_logic;
pipe_tx2_powerdown : in std_logic_vector(1 downto 0);
-- Pipe Per-Lane Signals - Lane 3
pipe_rx3_char_is_k : out std_logic_vector(1 downto 0);
pipe_rx3_data : out std_logic_vector(15 downto 0);
pipe_rx3_valid : out std_logic;
pipe_rx3_chanisaligned : out std_logic;
pipe_rx3_status : out std_logic_vector(2 downto 0);
pipe_rx3_phy_status : out std_logic;
pipe_rx3_elec_idle : out std_logic;
pipe_rx3_polarity : in std_logic;
pipe_tx3_compliance : in std_logic;
pipe_tx3_char_is_k : in std_logic_vector(1 downto 0);
pipe_tx3_data : in std_logic_vector(15 downto 0);
pipe_tx3_elec_idle : in std_logic;
pipe_tx3_powerdown : in std_logic_vector(1 downto 0);
-- Pipe Per-Lane Signals - Lane 4
pipe_rx4_char_is_k : out std_logic_vector(1 downto 0);
pipe_rx4_data : out std_logic_vector(15 downto 0);
pipe_rx4_valid : out std_logic;
pipe_rx4_chanisaligned : out std_logic;
pipe_rx4_status : out std_logic_vector(2 downto 0);
pipe_rx4_phy_status : out std_logic;
pipe_rx4_elec_idle : out std_logic;
pipe_rx4_polarity : in std_logic;
pipe_tx4_compliance : in std_logic;
pipe_tx4_char_is_k : in std_logic_vector(1 downto 0);
pipe_tx4_data : in std_logic_vector(15 downto 0);
pipe_tx4_elec_idle : in std_logic;
pipe_tx4_powerdown : in std_logic_vector(1 downto 0);
-- Pipe Per-Lane Signals - Lane 5
pipe_rx5_char_is_k : out std_logic_vector(1 downto 0);
pipe_rx5_data : out std_logic_vector(15 downto 0);
pipe_rx5_valid : out std_logic;
pipe_rx5_chanisaligned : out std_logic;
pipe_rx5_status : out std_logic_vector(2 downto 0);
pipe_rx5_phy_status : out std_logic;
pipe_rx5_elec_idle : out std_logic;
pipe_rx5_polarity : in std_logic;
pipe_tx5_compliance : in std_logic;
pipe_tx5_char_is_k : in std_logic_vector(1 downto 0);
pipe_tx5_data : in std_logic_vector(15 downto 0);
pipe_tx5_elec_idle : in std_logic;
pipe_tx5_powerdown : in std_logic_vector(1 downto 0);
-- Pipe Per-Lane Signals - Lane 6
pipe_rx6_char_is_k : out std_logic_vector(1 downto 0);
pipe_rx6_data : out std_logic_vector(15 downto 0);
pipe_rx6_valid : out std_logic;
pipe_rx6_chanisaligned : out std_logic;
pipe_rx6_status : out std_logic_vector(2 downto 0);
pipe_rx6_phy_status : out std_logic;
pipe_rx6_elec_idle : out std_logic;
pipe_rx6_polarity : in std_logic;
pipe_tx6_compliance : in std_logic;
pipe_tx6_char_is_k : in std_logic_vector(1 downto 0);
pipe_tx6_data : in std_logic_vector(15 downto 0);
pipe_tx6_elec_idle : in std_logic;
pipe_tx6_powerdown : in std_logic_vector(1 downto 0);
-- Pipe Per-Lane Signals - Lane 7
pipe_rx7_char_is_k : out std_logic_vector(1 downto 0);
pipe_rx7_data : out std_logic_vector(15 downto 0);
pipe_rx7_valid : out std_logic;
pipe_rx7_chanisaligned : out std_logic;
pipe_rx7_status : out std_logic_vector(2 downto 0);
pipe_rx7_phy_status : out std_logic;
pipe_rx7_elec_idle : out std_logic;
pipe_rx7_polarity : in std_logic;
pipe_tx7_compliance : in std_logic;
pipe_tx7_char_is_k : in std_logic_vector(1 downto 0);
pipe_tx7_data : in std_logic_vector(15 downto 0);
pipe_tx7_elec_idle : in std_logic;
pipe_tx7_powerdown : in std_logic_vector(1 downto 0);
-- PCI Express signals
pci_exp_txn : out std_logic_vector((NO_OF_LANES - 1) downto 0);
pci_exp_txp : out std_logic_vector((NO_OF_LANES - 1) downto 0);
pci_exp_rxn : in std_logic_vector((NO_OF_LANES - 1) downto 0);
pci_exp_rxp : in std_logic_vector((NO_OF_LANES - 1) downto 0);
-- Non PIPE signals
sys_clk : in std_logic;
sys_rst_n : in std_logic;
pipe_clk : in std_logic;
drp_clk : in std_logic;
clock_locked : in std_logic;
gt_pll_lock : out std_logic;
pl_ltssm_state : in std_logic_vector(5 downto 0);
phy_rdy_n : out std_logic;
TxOutClk : out std_logic
);
end pcie_gtx_v6;
architecture v6_pcie of pcie_gtx_v6 is
component gtx_wrapper_v6 is
generic (
NO_OF_LANES : integer := 1;
REF_CLK_FREQ : integer := 0;
PL_FAST_TRAIN : boolean := FALSE
);
port (
TX : out std_logic_vector(NO_OF_LANES - 1 downto 0);
TXN : out std_logic_vector(NO_OF_LANES - 1 downto 0);
TxData : in std_logic_vector((NO_OF_LANES * 16) - 1 downto 0);
TxDataK : in std_logic_vector((NO_OF_LANES * 2) - 1 downto 0);
TxElecIdle : in std_logic_vector(NO_OF_LANES - 1 downto 0);
TxCompliance : in std_logic_vector(NO_OF_LANES - 1 downto 0);
RX : in std_logic_vector(NO_OF_LANES - 1 downto 0);
RXN : in std_logic_vector(NO_OF_LANES - 1 downto 0);
RxData : out std_logic_vector((NO_OF_LANES * 16) - 1 downto 0);
RxDataK : out std_logic_vector((NO_OF_LANES * 2) - 1 downto 0);
RxPolarity : in std_logic_vector(NO_OF_LANES - 1 downto 0);
RxValid : out std_logic_vector(NO_OF_LANES - 1 downto 0);
RxElecIdle : out std_logic_vector(NO_OF_LANES - 1 downto 0);
RxStatus : out std_logic_vector((NO_OF_LANES * 3) - 1 downto 0);
GTRefClkout : out std_logic_vector(NO_OF_LANES - 1 downto 0);
plm_in_l0 : in std_logic;
plm_in_rl : in std_logic;
plm_in_dt : in std_logic;
plm_in_rs : in std_logic;
RxPLLLkDet : out std_logic_vector(NO_OF_LANES - 1 downto 0);
TxDetectRx : in std_logic;
PhyStatus : out std_logic_vector(NO_OF_LANES - 1 downto 0);
TXPdownAsynch : in std_logic;
PowerDown : in std_logic_vector((NO_OF_LANES * 2) - 1 downto 0);
Rate : in std_logic;
Reset_n : in std_logic;
GTReset_n : in std_logic;
PCLK : in std_logic;
REFCLK : in std_logic;
TxDeemph : in std_logic;
TxMargin : in std_logic;
TxSwing : in std_logic;
ChanIsAligned : out std_logic_vector(NO_OF_LANES - 1 downto 0);
local_pcs_reset : in std_logic;
RxResetDone : out std_logic;
SyncDone : out std_logic;
DRPCLK : in std_logic;
TxOutClk : out std_logic
);
end component;
constant TCQ : integer := 1; -- clock to out delay model
FUNCTION to_stdlogic (
in_val : IN boolean) RETURN std_logic IS
BEGIN
IF (in_val) THEN
RETURN('1');
ELSE
RETURN('0');
END IF;
END to_stdlogic;
FUNCTION and_bw (
val_in : std_logic_vector) RETURN std_logic IS
VARIABLE ret : std_logic := '1';
BEGIN
FOR index IN val_in'RANGE LOOP
ret := ret AND val_in(index);
END LOOP;
RETURN(ret);
END and_bw;
FUNCTION nand_bw (
val_in : std_logic_vector) RETURN std_logic IS
VARIABLE ret : std_logic := '1';
BEGIN
FOR index IN val_in'RANGE LOOP
ret := ret AND val_in(index);
END LOOP;
RETURN(NOT ret);
END nand_bw;
signal gt_rx_phy_status_wire : std_logic_vector(7 downto 0);
signal gt_rxchanisaligned_wire : std_logic_vector(7 downto 0);
signal gt_rx_data_k_wire : std_logic_vector(127 downto 0);
signal gt_rx_data_wire : std_logic_vector(127 downto 0);
signal gt_rx_elec_idle_wire : std_logic_vector(7 downto 0);
signal gt_rx_status_wire : std_logic_vector(23 downto 0);
signal gt_rx_valid_wire : std_logic_vector(7 downto 0);
signal gt_rx_polarity : std_logic_vector(7 downto 0);
signal gt_power_down : std_logic_vector(15 downto 0);
signal gt_tx_char_disp_mode : std_logic_vector(7 downto 0);
signal gt_tx_data_k : std_logic_vector(15 downto 0);
signal gt_tx_data : std_logic_vector(127 downto 0);
signal gt_tx_detect_rx_loopback : std_logic;
signal gt_tx_elec_idle : std_logic_vector(7 downto 0);
signal gt_rx_elec_idle_reset : std_logic_vector(7 downto 0);
signal plllkdet : std_logic_vector(NO_OF_LANES - 1 downto 0);
signal RxResetDone : std_logic;
signal plm_in_l0 : std_logic;
signal plm_in_rl : std_logic;
signal plm_in_dt : std_logic;
signal plm_in_rs : std_logic;
signal local_pcs_reset : std_logic;
signal local_pcs_reset_done : std_logic;
signal cnt_local_pcs_reset : std_logic_vector(3 downto 0);
signal phy_rdy_pre_cnt : std_logic_vector(4 downto 0);
signal pl_ltssm_state_q : std_logic_vector(5 downto 0);
signal SyncDone : std_logic;
-- X-HDL generated signals
signal v6pcie5 : std_logic;
-- Declare intermediate signals for referenced outputs
signal pci_exp_txn_v6pcie2 : std_logic_vector((NO_OF_LANES - 1) downto 0);
signal pci_exp_txp_v6pcie3 : std_logic_vector((NO_OF_LANES - 1) downto 0);
signal gt_pll_lock_v6pcie1 : std_logic;
signal phy_rdy_n_v6pcie4 : std_logic;
signal TxOutClk_v6pcie0 : std_logic;
signal plllkdet_nand : std_logic;
begin
-- Drive referenced outputs
pci_exp_txn <= pci_exp_txn_v6pcie2;
pci_exp_txp <= pci_exp_txp_v6pcie3;
gt_pll_lock <= gt_pll_lock_v6pcie1;
phy_rdy_n <= phy_rdy_n_v6pcie4;
TxOutClk <= TxOutClk_v6pcie0;
plm_in_l0 <= to_stdlogic((pl_ltssm_state = "010110"));
plm_in_rl <= to_stdlogic((pl_ltssm_state = "011100"));
plm_in_dt <= to_stdlogic((pl_ltssm_state = "101101"));
plm_in_rs <= to_stdlogic((pl_ltssm_state = "011111"));
v6pcie5 <= not(clock_locked);
gtx_v6_i : gtx_wrapper_v6
generic map (
NO_OF_LANES => NO_OF_LANES,
REF_CLK_FREQ => REF_CLK_FREQ,
PL_FAST_TRAIN => PL_FAST_TRAIN
)
port map (
-- TX
TX => pci_exp_txp_v6pcie3(((NO_OF_LANES) - 1) downto 0),
TXN => pci_exp_txn_v6pcie2(((NO_OF_LANES) - 1) downto 0),
TxData => gt_tx_data(((16 * NO_OF_LANES) - 1) downto 0),
TxDataK => gt_tx_data_k(((2 * NO_OF_LANES) - 1) downto 0),
TxElecIdle => gt_tx_elec_idle(((NO_OF_LANES) - 1) downto 0),
TxCompliance => gt_tx_char_disp_mode(((NO_OF_LANES) - 1) downto 0),
-- RX
RX => pci_exp_rxp(((NO_OF_LANES) - 1) downto 0),
RXN => pci_exp_rxn(((NO_OF_LANES) - 1) downto 0),
RxData => gt_rx_data_wire(((16 * NO_OF_LANES) - 1) downto 0),
RxDataK => gt_rx_data_k_wire(((2 * NO_OF_LANES) - 1) downto 0),
RxPolarity => gt_rx_polarity(((NO_OF_LANES) - 1) downto 0),
RxValid => gt_rx_valid_wire(((NO_OF_LANES) - 1) downto 0),
RxElecIdle => gt_rx_elec_idle_wire(((NO_OF_LANES) - 1) downto 0),
RxStatus => gt_rx_status_wire(((3 * NO_OF_LANES) - 1) downto 0),
-- other
GTRefClkout => open,
plm_in_l0 => plm_in_l0,
plm_in_rl => plm_in_rl,
plm_in_dt => plm_in_dt,
plm_in_rs => plm_in_rs,
RxPLLLkDet => plllkdet,
ChanIsAligned => gt_rxchanisaligned_wire(((NO_OF_LANES) - 1) downto 0),
TxDetectRx => gt_tx_detect_rx_loopback,
PhyStatus => gt_rx_phy_status_wire(((NO_OF_LANES) - 1) downto 0),
TXPdownAsynch => v6pcie5,
PowerDown => gt_power_down(((2 * NO_OF_LANES) - 1) downto 0),
Rate => pipe_tx_rate,
Reset_n => clock_locked,
GTReset_n => sys_rst_n,
PCLK => pipe_clk,
REFCLK => sys_clk,
DRPCLK => drp_clk,
TxDeemph => pipe_tx_deemph,
TxMargin => pipe_tx_margin(2),
TxSwing => pipe_tx_swing,
local_pcs_reset => local_pcs_reset,
RxResetDone => RxResetDone,
SyncDone => SyncDone,
TxOutClk => TxOutClk_v6pcie0
);
pipe_rx0_phy_status <= gt_rx_phy_status_wire(0);
pipe_rx1_phy_status <= gt_rx_phy_status_wire(1) when (NO_OF_LANES >= 2) else
'0';
pipe_rx2_phy_status <= gt_rx_phy_status_wire(2) when (NO_OF_LANES >= 4) else
'0';
pipe_rx3_phy_status <= gt_rx_phy_status_wire(3) when (NO_OF_LANES >= 4) else
'0';
pipe_rx4_phy_status <= gt_rx_phy_status_wire(4) when (NO_OF_LANES >= 8) else
'0';
pipe_rx5_phy_status <= gt_rx_phy_status_wire(5) when (NO_OF_LANES >= 8) else
'0';
pipe_rx6_phy_status <= gt_rx_phy_status_wire(6) when (NO_OF_LANES >= 8) else
'0';
pipe_rx7_phy_status <= gt_rx_phy_status_wire(7) when (NO_OF_LANES >= 8) else
'0';
pipe_rx0_chanisaligned <= gt_rxchanisaligned_wire(0);
pipe_rx1_chanisaligned <= gt_rxchanisaligned_wire(1) when (NO_OF_LANES >= 2) else
'0';
pipe_rx2_chanisaligned <= gt_rxchanisaligned_wire(2) when (NO_OF_LANES >= 4) else
'0';
pipe_rx3_chanisaligned <= gt_rxchanisaligned_wire(3) when (NO_OF_LANES >= 4) else
'0';
pipe_rx4_chanisaligned <= gt_rxchanisaligned_wire(4) when (NO_OF_LANES >= 8) else
'0';
pipe_rx5_chanisaligned <= gt_rxchanisaligned_wire(5) when (NO_OF_LANES >= 8) else
'0';
pipe_rx6_chanisaligned <= gt_rxchanisaligned_wire(6) when (NO_OF_LANES >= 8) else
'0';
pipe_rx7_chanisaligned <= gt_rxchanisaligned_wire(7) when (NO_OF_LANES >= 8) else
'0';
--<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
--<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
pipe_rx0_char_is_k <= (gt_rx_data_k_wire(1) & gt_rx_data_k_wire(0));
pipe_rx1_char_is_k <= (gt_rx_data_k_wire(3) & gt_rx_data_k_wire(2)) when (NO_OF_LANES >= 2) else
"00";
pipe_rx2_char_is_k <= (gt_rx_data_k_wire(5) & gt_rx_data_k_wire(4)) when (NO_OF_LANES >= 4) else
"00";
pipe_rx3_char_is_k <= (gt_rx_data_k_wire(7) & gt_rx_data_k_wire(6)) when (NO_OF_LANES >= 4) else
"00";
pipe_rx4_char_is_k <= (gt_rx_data_k_wire(9) & gt_rx_data_k_wire(8)) when (NO_OF_LANES >= 8) else
"00";
pipe_rx5_char_is_k <= (gt_rx_data_k_wire(11) & gt_rx_data_k_wire(10)) when (NO_OF_LANES >= 8) else
"00";
pipe_rx6_char_is_k <= (gt_rx_data_k_wire(13) & gt_rx_data_k_wire(12)) when (NO_OF_LANES >= 8) else
"00";
pipe_rx7_char_is_k <= (gt_rx_data_k_wire(15) & gt_rx_data_k_wire(14)) when (NO_OF_LANES >= 8) else
"00";
pipe_rx0_data <= (gt_rx_data_wire(15 downto 8) & gt_rx_data_wire(7 downto 0));
pipe_rx1_data <= (gt_rx_data_wire(31 downto 24) & gt_rx_data_wire(23 downto 16)) when (NO_OF_LANES >= 2) else
"0000000000000000";
pipe_rx2_data <= (gt_rx_data_wire(47 downto 40) & gt_rx_data_wire(39 downto 32)) when (NO_OF_LANES >= 4) else
"0000000000000000";
pipe_rx3_data <= (gt_rx_data_wire(63 downto 56) & gt_rx_data_wire(55 downto 48)) when (NO_OF_LANES >= 4) else
"0000000000000000";
pipe_rx4_data <= (gt_rx_data_wire(79 downto 72) & gt_rx_data_wire(71 downto 64)) when (NO_OF_LANES >= 8) else
"0000000000000000";
pipe_rx5_data <= (gt_rx_data_wire(95 downto 88) & gt_rx_data_wire(87 downto 80)) when (NO_OF_LANES >= 8) else
"0000000000000000";
pipe_rx6_data <= (gt_rx_data_wire(111 downto 104) & gt_rx_data_wire(103 downto 96)) when (NO_OF_LANES >= 8) else
"0000000000000000";
pipe_rx7_data <= (gt_rx_data_wire(127 downto 120) & gt_rx_data_wire(119 downto 112)) when (NO_OF_LANES >= 8) else
"0000000000000000";
--<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
--<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
pipe_rx0_elec_idle <= gt_rx_elec_idle_wire(0);
pipe_rx1_elec_idle <= gt_rx_elec_idle_wire(1) when (NO_OF_LANES >= 2) else
'1';
pipe_rx2_elec_idle <= gt_rx_elec_idle_wire(2) when (NO_OF_LANES >= 4) else
'1';
pipe_rx3_elec_idle <= gt_rx_elec_idle_wire(3) when (NO_OF_LANES >= 4) else
'1';
pipe_rx4_elec_idle <= gt_rx_elec_idle_wire(4) when (NO_OF_LANES >= 8) else
'1';
pipe_rx5_elec_idle <= gt_rx_elec_idle_wire(5) when (NO_OF_LANES >= 8) else
'1';
pipe_rx6_elec_idle <= gt_rx_elec_idle_wire(6) when (NO_OF_LANES >= 8) else
'1';
pipe_rx7_elec_idle <= gt_rx_elec_idle_wire(7) when (NO_OF_LANES >= 8) else
'1';
pipe_rx0_status <= gt_rx_status_wire(2 downto 0);
pipe_rx1_status <= gt_rx_status_wire(5 downto 3) when (NO_OF_LANES >= 2) else
"000";
pipe_rx2_status <= gt_rx_status_wire(8 downto 6) when (NO_OF_LANES >= 4) else
"000";
pipe_rx3_status <= gt_rx_status_wire(11 downto 9) when (NO_OF_LANES >= 4) else
"000";
pipe_rx4_status <= gt_rx_status_wire(14 downto 12) when (NO_OF_LANES >= 8) else
"000";
pipe_rx5_status <= gt_rx_status_wire(17 downto 15) when (NO_OF_LANES >= 8) else
"000";
pipe_rx6_status <= gt_rx_status_wire(20 downto 18) when (NO_OF_LANES >= 8) else
"000";
pipe_rx7_status <= gt_rx_status_wire(23 downto 21) when (NO_OF_LANES >= 8) else
"000";
pipe_rx0_valid <= gt_rx_valid_wire(0);
pipe_rx1_valid <= gt_rx_valid_wire(1) when (NO_OF_LANES >= 2) else
'0';
pipe_rx2_valid <= gt_rx_valid_wire(2) when (NO_OF_LANES >= 4) else
'0';
pipe_rx3_valid <= gt_rx_valid_wire(3) when (NO_OF_LANES >= 4) else
'0';
pipe_rx4_valid <= gt_rx_valid_wire(4) when (NO_OF_LANES >= 8) else
'0';
pipe_rx5_valid <= gt_rx_valid_wire(5) when (NO_OF_LANES >= 8) else
'0';
pipe_rx6_valid <= gt_rx_valid_wire(6) when (NO_OF_LANES >= 8) else
'0';
pipe_rx7_valid <= gt_rx_valid_wire(7) when (NO_OF_LANES >= 8) else
'0';
gt_rx_polarity(0) <= pipe_rx0_polarity;
gt_rx_polarity(1) <= pipe_rx1_polarity;
gt_rx_polarity(2) <= pipe_rx2_polarity;
gt_rx_polarity(3) <= pipe_rx3_polarity;
gt_rx_polarity(4) <= pipe_rx4_polarity;
gt_rx_polarity(5) <= pipe_rx5_polarity;
gt_rx_polarity(6) <= pipe_rx6_polarity;
gt_rx_polarity(7) <= pipe_rx7_polarity;
gt_power_down(1 downto 0) <= pipe_tx0_powerdown;
gt_power_down(3 downto 2) <= pipe_tx1_powerdown;
gt_power_down(5 downto 4) <= pipe_tx2_powerdown;
gt_power_down(7 downto 6) <= pipe_tx3_powerdown;
gt_power_down(9 downto 8) <= pipe_tx4_powerdown;
gt_power_down(11 downto 10) <= pipe_tx5_powerdown;
gt_power_down(13 downto 12) <= pipe_tx6_powerdown;
gt_power_down(15 downto 14) <= pipe_tx7_powerdown;
gt_tx_char_disp_mode <= (pipe_tx7_compliance & pipe_tx6_compliance & pipe_tx5_compliance & pipe_tx4_compliance & pipe_tx3_compliance & pipe_tx2_compliance & pipe_tx1_compliance & pipe_tx0_compliance);
gt_tx_data_k <= (pipe_tx7_char_is_k & pipe_tx6_char_is_k & pipe_tx5_char_is_k & pipe_tx4_char_is_k & pipe_tx3_char_is_k & pipe_tx2_char_is_k & pipe_tx1_char_is_k & pipe_tx0_char_is_k);
gt_tx_data <= (pipe_tx7_data & pipe_tx6_data & pipe_tx5_data & pipe_tx4_data & pipe_tx3_data & pipe_tx2_data & pipe_tx1_data & pipe_tx0_data);
gt_tx_detect_rx_loopback <= pipe_tx_rcvr_det;
gt_tx_elec_idle <= (pipe_tx7_elec_idle & pipe_tx6_elec_idle & pipe_tx5_elec_idle & pipe_tx4_elec_idle & pipe_tx3_elec_idle & pipe_tx2_elec_idle & pipe_tx1_elec_idle & pipe_tx0_elec_idle);
gt_pll_lock_v6pcie1 <= and_bw(plllkdet(NO_OF_LANES - 1 downto 0)) or not(phy_rdy_pre_cnt(4));
plllkdet_nand <= nand_bw(plllkdet(NO_OF_LANES - 1 downto 0));
-- Asserted after all workarounds have completed.
process (pipe_clk, clock_locked)
begin
if ((not(clock_locked)) = '1') then
phy_rdy_n_v6pcie4 <= '1' after (TCQ)*1 ps;
elsif (pipe_clk'event and pipe_clk = '1') then
if (plllkdet_nand = '1') then
phy_rdy_n_v6pcie4 <= '1' after (TCQ)*1 ps;
elsif ((local_pcs_reset_done and RxResetDone and phy_rdy_n_v6pcie4 and SyncDone) = '1') then
phy_rdy_n_v6pcie4 <= '0' after (TCQ)*1 ps;
end if;
end if;
end process;
-- Handle the warm reset case, where sys_rst_n is asseted when
-- phy_rdy_n is asserted. phy_rdy_n is to be de-asserted
-- before gt_pll_lock is de-asserted so that synnchronous
-- logic see reset de-asset before clock is lost.
process (pipe_clk, clock_locked)
begin
if ((not(clock_locked)) = '1') then
phy_rdy_pre_cnt <= "11111" after (TCQ)*1 ps;
elsif (pipe_clk'event and pipe_clk = '1') then
if ((gt_pll_lock_v6pcie1 and phy_rdy_n_v6pcie4) = '1') then
phy_rdy_pre_cnt <= phy_rdy_pre_cnt + "00001" after (TCQ)*1 ps;
end if;
end if;
end process;
process (pipe_clk, clock_locked)
begin
if ((not(clock_locked)) = '1') then
cnt_local_pcs_reset <= "1111" after (TCQ)*1 ps;
local_pcs_reset <= '0' after (TCQ)*1 ps;
local_pcs_reset_done <= '0' after (TCQ)*1 ps;
elsif (pipe_clk'event and pipe_clk = '1') then
if ((local_pcs_reset = '0') and (cnt_local_pcs_reset = "1111")) then
local_pcs_reset <= '1' after (TCQ)*1 ps;
elsif ((local_pcs_reset = '1') and (cnt_local_pcs_reset /= "0000")) then
local_pcs_reset <= '1' after (TCQ)*1 ps;
cnt_local_pcs_reset <= cnt_local_pcs_reset - "0001" after (TCQ)*1 ps;
elsif ((local_pcs_reset = '1') and (cnt_local_pcs_reset = "0000")) then
local_pcs_reset <= '0' after (TCQ)*1 ps;
local_pcs_reset_done <= '1' after (TCQ)*1 ps;
end if;
end if;
end process;
process (pipe_clk, clock_locked)
begin
if ((not(clock_locked)) = '1') then
pl_ltssm_state_q <= "000000" after (TCQ)*1 ps;
elsif (pipe_clk'event and pipe_clk = '1') then
pl_ltssm_state_q <= pl_ltssm_state_q + "000001" after (TCQ)*1 ps;
end if;
end process;
end v6_pcie;
| gpl-3.0 | d024b593d629c7ca46fd7aac8171233f | 0.475341 | 3.698465 | false | false | false | false |
masaruohashi/tic-tac-toe | logica_jogo/unidade_controle_logica_jogo.vhd | 1 | 3,305 | -- VHDL da Unidade de Controle da interface jogo da velha
library ieee;
use ieee.std_logic_1164.all;
entity unidade_controle_logica_jogo is
port(
clock : in std_logic;
reset : in std_logic;
start : in std_logic;
fim_recepcao : in std_logic; -- indica que um caractere terminou de ser recebido
jogada_ok : in std_logic; -- indica que o caractere recebido é valido
fim_jogo : in std_logic; -- indica que o jogo acabou
recebe_dado : out std_logic; -- habilita a recepção de um dado
insere_dado : out std_logic; -- habilita a inserção do dado na memoria
jogo_acabado : out std_logic; -- indica que o jogo acabou
pronto : out std_logic; -- indica que a jogada terminou de ser processada
estados : out std_logic_vector(2 downto 0)
);
end unidade_controle_logica_jogo;
architecture comportamental of unidade_controle_logica_jogo is
type tipo_estado is (inicial, recebe, valida_jogada, guarda, valida_tabuleiro, aguarda, final);
signal estado : tipo_estado;
begin
process (clock, estado, reset)
begin
if reset = '1' then
estado <= inicial;
elsif (clock'event and clock = '1') then
case estado is
when inicial => -- Aguarda sinal de start
if start = '1' then
estado <= recebe;
else
estado <= inicial;
end if;
when recebe => -- Espera o dado ser recebido
if fim_recepcao = '1' then
estado <= valida_jogada;
else
estado <= recebe;
end if;
when valida_jogada => -- Verifica se o caractere é valido
if jogada_ok = '0' then
estado <= recebe;
else
estado <= guarda;
end if;
when guarda => -- Guarda o dado no tabuleiro
estado <= valida_tabuleiro;
when valida_tabuleiro => -- Verifica se o jogo acabou
if fim_jogo = '1' then
estado <= final;
else
estado <= aguarda;
end if;
when aguarda => -- Prepara a interface do jogo
estado <= inicial;
when final => -- Fim do jogo
estado <= final;
when others => -- Default
estado <= inicial;
end case;
end if;
end process;
-- logica de saída
with estado select
recebe_dado <= '1' when recebe,
'0' when others;
with estado select
insere_dado <= '1' when guarda,
'0' when others;
with estado select
jogo_acabado <= '1' when final,
'0' when others;
with estado select
pronto <= '1' when aguarda,
'0' when others;
process(estado)
begin
case estado is
when inicial => estados <= "000";
when recebe => estados <= "001";
when valida_jogada => estados <= "010";
when guarda => estados <= "011";
when valida_tabuleiro => estados <= "100";
when aguarda => estados <= "101";
when final => estados <= "110";
when others => null;
end case;
end process;
end comportamental;
| mit | c606ee7f6804047e73ecd3f1e52af9bb | 0.538811 | 4.1225 | false | false | false | false |
timofonic/PHDL | misc/projects/spartan_pcie_board/fpga/lx45t_pinout/ipcore_dir/pcie_core/simulation/dsport/gtx_wrapper_v6.vhd | 1 | 40,743 | -------------------------------------------------------------------------------
--
-- (c) Copyright 2008, 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Project : Spartan-6 Integrated Block for PCI Express
-- File : gtx_wrapper_v6.vhd
-- Description: GTX module for Virtex6 PCIe Block
--
--
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity gtx_wrapper_v6 is
generic (
NO_OF_LANES : integer := 1;
REF_CLK_FREQ : integer := 0;
PL_FAST_TRAIN : boolean := FALSE
);
port (
-- TX
TX : out std_logic_vector(NO_OF_LANES - 1 downto 0);
TXN : out std_logic_vector(NO_OF_LANES - 1 downto 0);
TxData : in std_logic_vector((NO_OF_LANES * 16) - 1 downto 0);
TxDataK : in std_logic_vector((NO_OF_LANES * 2) - 1 downto 0);
TxElecIdle : in std_logic_vector(NO_OF_LANES - 1 downto 0);
TxCompliance : in std_logic_vector(NO_OF_LANES - 1 downto 0);
-- RX
RX : in std_logic_vector(NO_OF_LANES - 1 downto 0);
RXN : in std_logic_vector(NO_OF_LANES - 1 downto 0);
RxData : out std_logic_vector((NO_OF_LANES * 16) - 1 downto 0);
RxDataK : out std_logic_vector((NO_OF_LANES * 2) - 1 downto 0);
RxPolarity : in std_logic_vector(NO_OF_LANES - 1 downto 0);
RxValid : out std_logic_vector(NO_OF_LANES - 1 downto 0);
RxElecIdle : out std_logic_vector(NO_OF_LANES - 1 downto 0);
RxStatus : out std_logic_vector((NO_OF_LANES * 3) - 1 downto 0);
-- other
GTRefClkout : out std_logic_vector(NO_OF_LANES - 1 downto 0);
plm_in_l0 : in std_logic;
plm_in_rl : in std_logic;
plm_in_dt : in std_logic;
plm_in_rs : in std_logic;
RxPLLLkDet : out std_logic_vector(NO_OF_LANES - 1 downto 0);
TxDetectRx : in std_logic;
PhyStatus : out std_logic_vector(NO_OF_LANES - 1 downto 0);
TXPdownAsynch : in std_logic;
PowerDown : in std_logic_vector((NO_OF_LANES * 2) - 1 downto 0);
Rate : in std_logic;
Reset_n : in std_logic;
GTReset_n : in std_logic;
PCLK : in std_logic;
REFCLK : in std_logic;
TxDeemph : in std_logic;
TxMargin : in std_logic;
TxSwing : in std_logic;
ChanIsAligned : out std_logic_vector(NO_OF_LANES - 1 downto 0);
local_pcs_reset : in std_logic;
RxResetDone : out std_logic;
SyncDone : out std_logic;
DRPCLK : in std_logic;
TxOutClk : out std_logic
);
end gtx_wrapper_v6;
architecture v6_pcie of gtx_wrapper_v6 is
component GTX_RX_VALID_FILTER_V6 is
generic (
CLK_COR_MIN_LAT : integer
);
port (
USER_RXCHARISK : out std_logic_vector(1 downto 0);
USER_RXDATA : out std_logic_vector(15 downto 0);
USER_RXVALID : out std_logic;
USER_RXELECIDLE : out std_logic;
USER_RX_STATUS : out std_logic_vector(2 downto 0);
USER_RX_PHY_STATUS : out std_logic;
GT_RXCHARISK : in std_logic_vector(1 downto 0);
GT_RXDATA : in std_logic_vector(15 downto 0);
GT_RXVALID : in std_logic;
GT_RXELECIDLE : in std_logic;
GT_RX_STATUS : in std_logic_vector(2 downto 0);
GT_RX_PHY_STATUS : in std_logic;
PLM_IN_L0 : in std_logic;
PLM_IN_RS : in std_logic;
USER_CLK : in std_logic;
RESET : in std_logic
);
end component;
component GTX_DRP_CHANALIGN_FIX_3752_V6 is
generic (
C_SIMULATION : integer
);
port (
dwe : out std_logic;
din : out std_logic_vector(15 downto 0);
den : out std_logic;
daddr : out std_logic_vector(7 downto 0);
drpstate : out std_logic_vector(3 downto 0);
write_ts1 : in std_logic;
write_fts : in std_logic;
dout : in std_logic_vector(15 downto 0);
drdy : in std_logic;
Reset_n : in std_logic;
drp_clk : in std_logic
);
end component;
component GTX_TX_SYNC_RATE_V6 is
generic (
C_SIMULATION : integer
);
port (
ENPMAPHASEALIGN : out std_logic;
PMASETPHASE : out std_logic;
SYNC_DONE : out std_logic;
OUT_DIV_RESET : out std_logic;
PCS_RESET : out std_logic;
USER_PHYSTATUS : out std_logic;
TXALIGNDISABLE : out std_logic;
DELAYALIGNRESET : out std_logic;
USER_CLK : in std_logic;
RESET : in std_logic;
RATE : in std_logic;
RATEDONE : in std_logic;
GT_PHYSTATUS : in std_logic;
RESETDONE : in std_logic
);
end component;
FUNCTION to_stdlogicvector (
val_in : IN integer;
length : IN integer) RETURN std_logic_vector IS
VARIABLE ret : std_logic_vector(length-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE num : integer := val_in;
VARIABLE x : integer;
BEGIN
FOR index IN 0 TO length-1 LOOP
x := num rem 2;
num := num/2;
IF (x = 1) THEN
ret(index) := '1';
ELSE
ret(index) := '0';
END IF;
END LOOP;
RETURN(ret);
END to_stdlogicvector;
FUNCTION and_bw (
val_in : std_logic_vector) RETURN std_logic IS
VARIABLE ret : std_logic := '1';
BEGIN
FOR index IN val_in'RANGE LOOP
ret := ret AND val_in(index);
END LOOP;
RETURN(ret);
END and_bw;
FUNCTION to_integer (
in_val : IN boolean) RETURN integer IS
BEGIN
IF (in_val) THEN
RETURN(1);
ELSE
RETURN(0);
END IF;
END to_integer;
FUNCTION to_stdlogic (
in_val : IN boolean) RETURN std_logic IS
BEGIN
IF (in_val) THEN
RETURN('1');
ELSE
RETURN('0');
END IF;
END to_stdlogic;
-- purpose: PLL_CP_CFG selector function
function pll_cp_cfg_sel (
ref_freq : integer)
return bit_vector is
begin -- pll_cp_cfg_sel
if (ref_freq = 2) then
return (X"05");
else
return (X"05");
end if;
end pll_cp_cfg_sel;
FUNCTION clk_div (
in_val : IN integer) RETURN integer IS
BEGIN
if (in_val = 0) THEN
return (4);
elsif (in_val = 1) then
return (5);
else
return (10);
end if;
END clk_div;
FUNCTION pll_div (
in_val : IN integer) RETURN integer IS
BEGIN
if (in_val = 0) THEN
return (5);
elsif (in_val = 1) then
return (4);
elsif (in_val = 2) then
return (2);
else
return (0);
end if;
END pll_div;
-- ground and tied_to_vcc_i signals
signal tied_to_ground_i : std_logic;
signal tied_to_ground_vec_i : std_logic_vector(31 downto 0);
signal tied_to_vcc_i : std_logic;
type type_v6pcie10 is array (NO_OF_LANES + 1 downto 0) of std_logic_vector(3 downto 0);
type type_v6pcie11 is array (NO_OF_LANES - 1 downto 0) of std_logic;
type type_v6pcie16 is array (NO_OF_LANES - 1 downto 0) of std_logic_vector(12 downto 0);
-- dummy signals to avoid port mismatch with DUAL_GTX
signal RxData_dummy : std_logic_vector(15 downto 0);
signal RxDataK_dummy : std_logic_vector(1 downto 0);
signal TxData_dummy : std_logic_vector(15 downto 0);
signal TxDataK_dummy : std_logic_vector(1 downto 0);
-- inputs
signal GTX_TxData : std_logic_vector((NO_OF_LANES * 16) - 1 downto 0);
signal GTX_TxDataK : std_logic_vector((NO_OF_LANES * 2) - 1 downto 0);
signal GTX_TxElecIdle : std_logic_vector((NO_OF_LANES) - 1 downto 0);
signal GTX_TxCompliance : std_logic_vector((NO_OF_LANES - 1) downto 0);
signal GTX_RXP : std_logic_vector((NO_OF_LANES) - 1 downto 0);
signal GTX_RXN : std_logic_vector((NO_OF_LANES) - 1 downto 0);
-- outputs
signal GTX_TXP : std_logic_vector((NO_OF_LANES) - 1 downto 0);
signal GTX_TXN : std_logic_vector((NO_OF_LANES) - 1 downto 0);
signal GTX_RxData : std_logic_vector((NO_OF_LANES * 16) - 1 downto 0);
signal GTX_RxDataK : std_logic_vector((NO_OF_LANES * 2) - 1 downto 0);
signal GTX_RxPolarity : std_logic_vector((NO_OF_LANES) - 1 downto 0);
signal GTX_RxValid : std_logic_vector((NO_OF_LANES) - 1 downto 0);
signal GTX_RxElecIdle : std_logic_vector((NO_OF_LANES) - 1 downto 0);
signal GTX_RxResetDone : std_logic_vector((NO_OF_LANES - 1) downto 0);
signal GTX_RxChbondLevel : std_logic_vector((NO_OF_LANES * 3) - 1 downto 0);
signal GTX_RxStatus : std_logic_vector((NO_OF_LANES * 3) - 1 downto 0);
signal RXCHBOND : type_v6pcie10;
signal TXBYPASS8B10B : std_logic_vector(3 downto 0);
signal RXDEC8B10BUSE : std_logic;
signal GTX_PhyStatus : std_logic_vector(NO_OF_LANES - 1 downto 0);
signal RESETDONE : type_v6pcie11;
signal GTXRESET : std_logic;
signal RXRECCLK : std_logic;
signal SYNC_DONE : std_logic_vector(NO_OF_LANES - 1 downto 0);
signal OUT_DIV_RESET : std_logic_vector(NO_OF_LANES - 1 downto 0);
signal PCS_RESET : std_logic_vector(NO_OF_LANES - 1 downto 0);
signal TXENPMAPHASEALIGN : std_logic_vector(NO_OF_LANES - 1 downto 0);
signal TXPMASETPHASE : std_logic_vector(NO_OF_LANES - 1 downto 0);
signal TXRESETDONE : std_logic_vector(NO_OF_LANES - 1 downto 0);
signal TXRATEDONE : std_logic_vector(NO_OF_LANES - 1 downto 0);
signal PHYSTATUS_int : std_logic_vector(NO_OF_LANES - 1 downto 0);
signal RATE_CLK_SEL : std_logic_vector(NO_OF_LANES - 1 downto 0);
signal TXOCLK : std_logic_vector(NO_OF_LANES - 1 downto 0);
signal TXDLYALIGNDISABLE : std_logic_vector(NO_OF_LANES - 1 downto 0);
signal TXDLYALIGNRESET : std_logic_vector(NO_OF_LANES - 1 downto 0);
signal GTX_RxResetDone_q : std_logic_vector((NO_OF_LANES - 1) downto 0);
signal TXRESETDONE_q : std_logic_vector((NO_OF_LANES - 1) downto 0);
signal daddr : std_logic_vector((NO_OF_LANES * 8 - 1) downto 0);
signal den : std_logic_vector(NO_OF_LANES - 1 downto 0);
signal din : std_logic_vector((NO_OF_LANES * 16 - 1) downto 0);
signal dwe : std_logic_vector(NO_OF_LANES - 1 downto 0);
signal drpstate : std_logic_vector((NO_OF_LANES * 4 - 1) downto 0);
signal drdy : std_logic_vector(NO_OF_LANES - 1 downto 0);
signal dout : std_logic_vector((NO_OF_LANES * 16 - 1) downto 0);
signal write_drp_cb_fts : std_logic;
signal write_drp_cb_ts1 : std_logic;
-- X-HDL generated signals
signal v6pcie12 : std_logic;
signal v6pcie13 : std_logic;
signal v6pcie14 : std_logic_vector(NO_OF_LANES - 1 downto 0);
signal v6pcie15 : std_logic;
signal v6pcie16 : type_v6pcie16;
signal v6pcie18 : std_logic_vector(1 downto 0);
signal v6pcie21 : std_logic_vector((NO_OF_LANES*4) - 1 downto 0);
signal v6pcie23 : std_logic_vector((NO_OF_LANES*32) - 1 downto 0);
signal v6pcie24 : std_logic_vector(1 downto 0);
signal v6pcie25 : std_logic_vector(NO_OF_LANES - 1 downto 0);
signal v6pcie26 : std_logic_vector(19 downto 0);
signal v6pcie27 : std_logic_vector((NO_OF_LANES * 4) - 1 downto 0);
signal v6pcie28 : std_logic_vector((NO_OF_LANES * 4) - 1 downto 0);
signal v6pcie29 : std_logic_vector((NO_OF_LANES * 32) - 1 downto 0) := (others => '0');
signal v6pcie30 : std_logic_vector(2 downto 0);
-- Declare intermediate signals for referenced outputs
signal RxData_v6pcie3 : std_logic_vector((NO_OF_LANES * 16) - 1 downto 0);
signal RxDataK_v6pcie4 : std_logic_vector((NO_OF_LANES * 2) - 1 downto 0);
signal RxValid_v6pcie8 : std_logic_vector(NO_OF_LANES - 1 downto 0);
signal RxElecIdle_v6pcie5 : std_logic_vector(NO_OF_LANES - 1 downto 0);
signal RxStatus_v6pcie7 : std_logic_vector((NO_OF_LANES * 3) - 1 downto 0);
signal RxPLLLkDet_v6pcie6 : std_logic_vector(NO_OF_LANES - 1 downto 0);
signal PhyStatus_v6pcie1 : std_logic_vector(NO_OF_LANES - 1 downto 0);
signal ChanIsAligned_v6pcie0 : std_logic_vector(NO_OF_LANES - 1 downto 0);
begin
--------------------------- Static signal Assignments ---------------------
tied_to_ground_i <= '0';
tied_to_ground_vec_i(31 downto 0) <= (others => '0');
tied_to_vcc_i <= '1';
-- Drive referenced outputs
RxData <= RxData_v6pcie3;
RxDataK <= RxDataK_v6pcie4;
RxValid <= RxValid_v6pcie8;
RxElecIdle <= RxElecIdle_v6pcie5;
RxStatus <= RxStatus_v6pcie7;
RxPLLLkDet <= RxPLLLkDet_v6pcie6;
PhyStatus <= PhyStatus_v6pcie1;
ChanIsAligned <= ChanIsAligned_v6pcie0;
GTX_TxData <= TxData;
GTX_TxDataK <= TxDataK;
GTX_TxElecIdle <= TxElecIdle;
GTX_TxCompliance <= TxCompliance;
GTX_RXP <= RX((NO_OF_LANES) - 1 downto 0);
GTX_RXN <= RXN((NO_OF_LANES) - 1 downto 0);
GTX_RxPolarity <= RxPolarity;
TXBYPASS8B10B <= "0000";
RXDEC8B10BUSE <= '1';
GTXRESET <= '0';
RxResetDone <= and_bw((GTX_RxResetDone_q((NO_OF_LANES) - 1 downto 0)));
TX((NO_OF_LANES - 1) downto 0) <= GTX_TXP((NO_OF_LANES - 1) downto 0);
TXN((NO_OF_LANES - 1) downto 0) <= GTX_TXN((NO_OF_LANES - 1) downto 0);
RXCHBOND(0) <= "0000";
TxData_dummy <= "0000000000000000";
TxDataK_dummy <= "00";
SyncDone <= and_bw((SYNC_DONE((NO_OF_LANES - 1) downto 0)));
TxOutClk <= TXOCLK(0);
write_drp_cb_fts <= plm_in_l0;
write_drp_cb_ts1 <= plm_in_rl or plm_in_dt;
-- pipeline to improve timing
process (PCLK)
begin
if (PCLK'event and PCLK = '1') then
GTX_RxResetDone_q((NO_OF_LANES - 1) downto 0) <= GTX_RxResetDone((NO_OF_LANES - 1) downto 0);
TXRESETDONE_q((NO_OF_LANES - 1) downto 0) <= TXRESETDONE((NO_OF_LANES - 1) downto 0);
end if;
end process;
GTXD : for i in 0 to (NO_OF_LANES - 1) generate
GTX_RxChbondLevel((3 * i) + 2 downto (3 * i)) <= (to_stdlogicvector((NO_OF_LANES - (i + 1)), 3));
GTX_DRP_CHANALIGN_FIX_3752 : GTX_DRP_CHANALIGN_FIX_3752_V6
generic map (
C_SIMULATION => to_integer(PL_FAST_TRAIN)
)
port map (
dwe => dwe(i),
din => din((16 * i) + 15 downto (16 * i)),
den => den(i),
daddr => daddr((8 * i) + 7 downto (8 * i)),
drpstate => drpstate((4 * i) + 3 downto (4 * i)),
write_ts1 => write_drp_cb_ts1,
write_fts => write_drp_cb_fts,
dout => dout((16 * i) + 15 downto (16 * i)),
drdy => drdy(i),
Reset_n => Reset_n,
drp_clk => DRPCLK
);
v6pcie12 <= not(Reset_n); --I
GTX_RX_VALID_FILTER : GTX_RX_VALID_FILTER_V6
generic map (
CLK_COR_MIN_LAT => 28
)
port map (
USER_RXCHARISK => RxDataK_v6pcie4((2 * i) + 1 downto 2 * i), --O
USER_RXDATA => RxData_v6pcie3((16 * i) + 15 downto (16 * i) + 0), --O
USER_RXVALID => RxValid_v6pcie8(i), --O
USER_RXELECIDLE => RxElecIdle_v6pcie5(i), --O
USER_RX_STATUS => RxStatus_v6pcie7((3 * i) + 2 downto (3 * i)), --O
USER_RX_PHY_STATUS => PhyStatus_v6pcie1(i), --O
GT_RXCHARISK => GTX_RxDataK((2 * i) + 1 downto 2 * i), --I
GT_RXDATA => GTX_RxData((16 * i) + 15 downto (16 * i) + 0), --I
GT_RXVALID => GTX_RxValid(i), --I
GT_RXELECIDLE => GTX_RxElecIdle(i), --I
GT_RX_STATUS => GTX_RxStatus((3 * i) + 2 downto (3 * i)), --I
GT_RX_PHY_STATUS => PHYSTATUS_int(i), --I
PLM_IN_L0 => plm_in_l0, --I
PLM_IN_RS => plm_in_rs, --I
USER_CLK => PCLK, --I
RESET => v6pcie12 --I
);
v6pcie14(i) <= (TXRESETDONE_q(i) and GTX_RxResetDone_q(i)); --I
GTX_TX_SYNC : GTX_TX_SYNC_RATE_V6
generic map (
C_SIMULATION => to_integer(PL_FAST_TRAIN)
)
port map (
ENPMAPHASEALIGN => TXENPMAPHASEALIGN(i), --O
PMASETPHASE => TXPMASETPHASE(i), --O
SYNC_DONE => SYNC_DONE(i), --O
OUT_DIV_RESET => OUT_DIV_RESET(i), --O
PCS_RESET => PCS_RESET(i), --O
USER_PHYSTATUS => PHYSTATUS_int(i), --O
TXALIGNDISABLE => TXDLYALIGNDISABLE(i), --O
DELAYALIGNRESET => TXDLYALIGNRESET(i), --O
USER_CLK => PCLK, --I
RESET => v6pcie12, --I
RATE => Rate, --I
RATEDONE => TXRATEDONE(i), --I
GT_PHYSTATUS => GTX_PhyStatus(i), --I
RESETDONE => v6pcie14(i) --I
);
v6pcie15 <= not(GTReset_n);
v6pcie16(i) <= ("10000000000" & OUT_DIV_RESET(i) & '0');
v6pcie18 <= ('0' & REFCLK);
GTX_RxDataK((2 * i) + 1 downto 2 * i) <= v6pcie21((4*i)+1 downto (4*i));
GTX_RxData((16 * i) + 15 downto (16 * i) + 0) <= v6pcie23((32*i)+15 downto (32*i));
v6pcie24 <= ('1' & Rate);
v6pcie25(i) <= not(GTReset_n) or local_pcs_reset or PCS_RESET(i);
v6pcie26 <= (others => '1');
v6pcie27((4 * i) + 3 downto (4 * i) + 0) <= ("000" & GTX_TxCompliance(i));
v6pcie28((4 * i) + 3 downto (4 * i) + 0) <= (TxDataK_dummy(1 downto 0) & GTX_TxDataK((2 * i) + 1 downto 2 * i));
v6pcie29((32 * i) + 31 downto (32 * i) + 0) <= (TxData_dummy(15 downto 0) & GTX_TxData((16 * i) + 15 downto (16 * i) + 0));
v6pcie30 <= (TxMargin & "00");
GTX : GTXE1
generic map (
TX_DRIVE_MODE => "PIPE",
TX_CLK_SOURCE => "RXPLL",
POWER_SAVE => "0000100100",
CM_TRIM => "01",
PMA_CDR_SCAN => x"640404C",
PMA_CFG => x"0040000040000000003",
RCV_TERM_GND => TRUE,
RCV_TERM_VTTRX => FALSE,
RX_DLYALIGN_EDGESET => "00010",
RX_DLYALIGN_LPFINC => "0110",
RX_DLYALIGN_OVRDSETTING => "10000000",
TERMINATION_CTRL => "10101",
TERMINATION_OVRD => TRUE,
TX_DLYALIGN_LPFINC => "0110",
TX_DLYALIGN_OVRDSETTING => "10000000",
TXPLL_CP_CFG => pll_cp_cfg_sel(REF_CLK_FREQ),
OOBDETECT_THRESHOLD => "011",
RXPLL_CP_CFG => pll_cp_cfg_sel(REF_CLK_FREQ),
-------------------------------------------------------------------------
-- TX_DETECT_RX_CFG => x"1832",
-------------------------------------------------------------------------
TX_TDCC_CFG => "11",
BIAS_CFG => x"00014",
AC_CAP_DIS => FALSE,
DFE_CFG => "00011011",
SIM_TX_ELEC_IDLE_LEVEL => "1",
SIM_RECEIVER_DETECT_PASS => TRUE,
RX_EN_REALIGN_RESET_BUF => FALSE,
TX_IDLE_ASSERT_DELAY => "110", -- TX-idle-set-to-idle (13 UI)
TX_IDLE_DEASSERT_DELAY => "100", -- TX-idle-to-diff (7 UI)
CHAN_BOND_SEQ_2_CFG => "11111", -- 5'b11111 for PCIE mode, 5'b00000 for other modes
CHAN_BOND_KEEP_ALIGN => TRUE,
RX_IDLE_HI_CNT => "1000",
RX_IDLE_LO_CNT => "0000",
RX_EN_IDLE_RESET_BUF => TRUE,
TX_DATA_WIDTH => 20,
RX_DATA_WIDTH => 20,
ALIGN_COMMA_WORD => 1,
CHAN_BOND_1_MAX_SKEW => 7,
CHAN_BOND_2_MAX_SKEW => 1,
CHAN_BOND_SEQ_1_1 => "0001000101", -- D5.2 (end TS2)
CHAN_BOND_SEQ_1_2 => "0001000101", -- D5.2 (end TS2)
CHAN_BOND_SEQ_1_3 => "0001000101", -- D5.2 (end TS2)
CHAN_BOND_SEQ_1_4 => "0110111100", -- K28.5 (COM)
CHAN_BOND_SEQ_1_ENABLE => "1111", -- order is 4321
CHAN_BOND_SEQ_2_1 => "0100111100", -- K28.1 (FTS)
CHAN_BOND_SEQ_2_2 => "0100111100", -- K28.1 (FTS)
CHAN_BOND_SEQ_2_3 => "0110111100", -- K28.5 (COM)
CHAN_BOND_SEQ_2_4 => "0100111100", -- K28.1 (FTS)
CHAN_BOND_SEQ_2_ENABLE => "1111", -- order is 4321
CHAN_BOND_SEQ_2_USE => TRUE,
CHAN_BOND_SEQ_LEN => 4, -- 1..4
RX_CLK25_DIVIDER => clk_div(REF_CLK_FREQ),
TX_CLK25_DIVIDER => clk_div(REF_CLK_FREQ),
CLK_COR_ADJ_LEN => 1, -- 1..4
CLK_COR_DET_LEN => 1, -- 1..4
CLK_COR_INSERT_IDLE_FLAG => FALSE,
CLK_COR_KEEP_IDLE => FALSE,
CLK_COR_MAX_LAT => 30,
CLK_COR_MIN_LAT => 28,
CLK_COR_PRECEDENCE => TRUE,
CLK_CORRECT_USE => TRUE,
CLK_COR_REPEAT_WAIT => 0,
CLK_COR_SEQ_1_1 => "0100011100", -- K28.0 (SKP)
CLK_COR_SEQ_1_2 => "0000000000",
CLK_COR_SEQ_1_3 => "0000000000",
CLK_COR_SEQ_1_4 => "0000000000",
CLK_COR_SEQ_1_ENABLE => "1111",
CLK_COR_SEQ_2_1 => "0000000000",
CLK_COR_SEQ_2_2 => "0000000000",
CLK_COR_SEQ_2_3 => "0000000000",
CLK_COR_SEQ_2_4 => "0000000000",
CLK_COR_SEQ_2_ENABLE => "1111",
CLK_COR_SEQ_2_USE => FALSE,
COMMA_10B_ENABLE => "1111111111",
COMMA_DOUBLE => FALSE,
DEC_MCOMMA_DETECT => TRUE,
DEC_PCOMMA_DETECT => TRUE,
DEC_VALID_COMMA_ONLY => TRUE,
MCOMMA_10B_VALUE => "1010000011",
MCOMMA_DETECT => TRUE,
PCI_EXPRESS_MODE => TRUE,
PCOMMA_10B_VALUE => "0101111100",
PCOMMA_DETECT => TRUE,
RXPLL_DIVSEL_FB => pll_div(REF_CLK_FREQ), -- 1..5, 8, 10
TXPLL_DIVSEL_FB => pll_div(REF_CLK_FREQ), -- 1..5, 8, 10
RXPLL_DIVSEL_REF => 1, -- 1..6, 8, 10, 12, 16, 20
TXPLL_DIVSEL_REF => 1, -- 1..6, 8, 10, 12, 16, 20
RXPLL_DIVSEL_OUT => 2, -- 1, 2, 4
TXPLL_DIVSEL_OUT => 2, -- 1, 2, 4
RXPLL_DIVSEL45_FB => 5,
TXPLL_DIVSEL45_FB => 5,
RX_BUFFER_USE => TRUE,
RX_DECODE_SEQ_MATCH => TRUE,
RX_LOS_INVALID_INCR => 8, -- power of 2: 1..128
RX_LOSS_OF_SYNC_FSM => FALSE,
RX_LOS_THRESHOLD => 128, -- power of 2: 4..512
RX_SLIDE_MODE => "OFF", -- 00=OFF 01=AUTO 10=PCS 11=PMA
RX_XCLK_SEL => "RXREC",
TX_BUFFER_USE => FALSE, -- Must be set to FALSE for use by PCIE
TX_XCLK_SEL => "TXUSR", -- Must be set to TXUSR for use by PCIE
TXPLL_LKDET_CFG => "101",
RX_EYE_SCANMODE => "00",
RX_EYE_OFFSET => x"3F",
PMA_RX_CFG => x"05ce044",
TRANS_TIME_NON_P2 => x"02", -- Reduced simulation time
TRANS_TIME_FROM_P2 => x"03c", -- Reduced simulation time
TRANS_TIME_TO_P2 => x"064", -- Reduced simulation time
TRANS_TIME_RATE => x"D7", -- Reduced simulation time
SHOW_REALIGN_COMMA => FALSE,
TX_PMADATA_OPT => '1', -- Lockup latch between PCS and PMA
PMA_TX_CFG => x"80082", -- Aligns posedge of USRCLK
TXOUTCLK_CTRL => "TXPLLREFCLK_DIV1"
)
port map (
COMFINISH => open,
COMINITDET => open,
COMSASDET => open,
COMWAKEDET => open,
DADDR => daddr((8 * i) + 7 downto (8 * i)),
DCLK => DRPCLK,
DEN => den(i),
DFECLKDLYADJ => "010011", -- Hex 13
DFECLKDLYADJMON => open,
DFEDLYOVRD => '1',
DFEEYEDACMON => open,
DFESENSCAL => open,
DFETAP1 => "01000",
DFETAP1MONITOR => open,
DFETAP2 => tied_to_ground_vec_i(4 downto 0),
DFETAP2MONITOR => open,
DFETAP3 => tied_to_ground_vec_i(3 downto 0),
DFETAP3MONITOR => open,
DFETAP4 => tied_to_ground_vec_i(3 downto 0),
DFETAP4MONITOR => open,
DFETAPOVRD => '1',
DI => din((16 * i) + 15 downto (16 * i)),
DRDY => drdy(i),
DRPDO => dout((16 * i) + 15 downto (16 * i)),
DWE => dwe(i),
GATERXELECIDLE => '0',
GREFCLKRX => tied_to_ground_i,
GREFCLKTX => tied_to_ground_i,
GTXRXRESET => v6pcie15,
GTXTEST => v6pcie16(i),
GTXTXRESET => v6pcie15,
LOOPBACK => "000",
MGTREFCLKFAB => open,
MGTREFCLKRX => v6pcie18,
MGTREFCLKTX => v6pcie18,
NORTHREFCLKRX => tied_to_ground_vec_i(1 downto 0),
NORTHREFCLKTX => tied_to_ground_vec_i(1 downto 0),
PHYSTATUS => GTX_PhyStatus(i),
PLLRXRESET => '0',
PLLTXRESET => '0',
PRBSCNTRESET => '0',
RXBUFRESET => '0',
RXBUFSTATUS => open,
RXBYTEISALIGNED => open,
RXBYTEREALIGN => open,
RXCDRRESET => '0',
RXCHANBONDSEQ => open,
RXCHANISALIGNED => ChanIsAligned_v6pcie0(i),
RXCHANREALIGN => open,
RXCHARISCOMMA => open,
RXCHARISK => v6pcie21((4 * i) + 3 downto (4 * i)),
RXCHBONDI => RXCHBOND(i),
RXCHBONDLEVEL => GTX_RxChbondLevel((3 * i) + 2 downto (3 * i)),
RXCHBONDMASTER => to_stdlogic(i = 0),
RXCHBONDO => RXCHBOND(i + 1),
RXCHBONDSLAVE => to_stdlogic(i > 0),
RXCLKCORCNT => open,
RXCOMMADET => open,
RXCOMMADETUSE => '1',
RXDATA => v6pcie23(((32 * i) + 31) downto (32 * i)),
RXDATAVALID => open,
RXDEC8B10BUSE => RXDEC8B10BUSE,
RXDISPERR => open,
RXDLYALIGNDISABLE => '1',
RXELECIDLE => GTX_RxElecIdle(i),
RXENCHANSYNC => '1',
RXENMCOMMAALIGN => '1',
RXENPCOMMAALIGN => '1',
RXENPMAPHASEALIGN => '0',
RXENPRBSTST => "000",
RXENSAMPLEALIGN => '0',
RXDLYALIGNMONENB => '1',
RXEQMIX => "0110000011",
RXGEARBOXSLIP => '0',
RXHEADER => open,
RXHEADERVALID => open,
RXLOSSOFSYNC => open,
RXN => GTX_RXN(i),
RXNOTINTABLE => open,
RXOVERSAMPLEERR => open,
RXP => GTX_RXP(i),
RXPLLLKDET => RxPLLLkDet_v6pcie6(i),
RXPLLLKDETEN => '1',
RXPLLPOWERDOWN => '0',
RXPLLREFSELDY => "000",
RXPMASETPHASE => '0',
RXPOLARITY => GTX_RxPolarity(i),
RXPOWERDOWN => PowerDown((2 * i) + 1 downto (2 * i)),
RXPRBSERR => open,
RXRATE => v6pcie24,
RXRATEDONE => open,
RXRECCLK => RXRECCLK,
RXRECCLKPCS => open,
RXRESET => v6pcie25(i),
RXRESETDONE => GTX_RxResetDone(i),
RXRUNDISP => open,
RXSLIDE => '0',
RXSTARTOFSEQ => open,
RXSTATUS => GTX_RxStatus((3 * i) + 2 downto (3 * i)),
RXUSRCLK => PCLK,
RXUSRCLK2 => PCLK,
RXVALID => GTX_RxValid(i),
SOUTHREFCLKRX => tied_to_ground_vec_i(1 downto 0),
SOUTHREFCLKTX => tied_to_ground_vec_i(1 downto 0),
TSTCLK0 => '0',
TSTCLK1 => '0',
TSTIN => v6pcie26,
TSTOUT => open,
TXBUFDIFFCTRL => "111",
TXBUFSTATUS => open,
TXBYPASS8B10B => TXBYPASS8B10B(3 downto 0),
TXCHARDISPMODE => v6pcie27((4 * i) + 3 downto (4 * i) + 0),
TXCHARDISPVAL => "0000",
TXCHARISK => v6pcie28((4 * i) + 3 downto (4 * i) + 0),
TXCOMINIT => '0',
TXCOMSAS => '0',
TXCOMWAKE => '0',
TXDATA => v6pcie29((32 * i) + 31 downto (32 * i) + 0),
TXDEEMPH => TxDeemph,
TXDETECTRX => TxDetectRx,
TXDIFFCTRL => "1111",
TXDLYALIGNDISABLE => TXDLYALIGNDISABLE(i),
TXDLYALIGNRESET => TXDLYALIGNRESET(i),
TXELECIDLE => GTX_TxElecIdle(i),
TXENC8B10BUSE => '1',
TXENPMAPHASEALIGN => TXENPMAPHASEALIGN(i),
TXENPRBSTST => tied_to_ground_vec_i(2 downto 0),
TXGEARBOXREADY => open,
TXHEADER => tied_to_ground_vec_i(2 downto 0),
TXINHIBIT => '0',
TXKERR => open,
TXMARGIN => v6pcie30,
TXN => GTX_TXN(i),
TXOUTCLK => TXOCLK(i),
TXOUTCLKPCS => open,
TXP => GTX_TXP(i),
TXPDOWNASYNCH => TXPdownAsynch,
TXPLLLKDET => open,
TXPLLLKDETEN => '0',
TXPLLPOWERDOWN => '0',
TXPLLREFSELDY => "000",
TXPMASETPHASE => TXPMASETPHASE(i),
TXPOLARITY => '0',
TXPOSTEMPHASIS => tied_to_ground_vec_i(4 downto 0),
TXPOWERDOWN => PowerDown((2 * i) + 1 downto (2 * i)),
TXPRBSFORCEERR => tied_to_ground_i,
TXPREEMPHASIS => tied_to_ground_vec_i(3 downto 0),
TXRATE => v6pcie24,
TXRESET => v6pcie25(i),
TXRESETDONE => TXRESETDONE(i),
TXRUNDISP => open,
TXSEQUENCE => tied_to_ground_vec_i(6 downto 0),
TXSTARTSEQ => tied_to_ground_i,
TXSWING => TxSwing,
TXUSRCLK => PCLK,
TXUSRCLK2 => PCLK,
USRCODEERR => tied_to_ground_i,
IGNORESIGDET => tied_to_ground_i,
PERFCLKRX => tied_to_ground_i,
PERFCLKTX => tied_to_ground_i,
RXDLYALIGNMONITOR => open,
RXDLYALIGNOVERRIDE => '0',
RXDLYALIGNRESET => tied_to_ground_i,
RXDLYALIGNSWPPRECURB => '1',
RXDLYALIGNUPDSW => '0',
TXDLYALIGNMONITOR => open,
TXDLYALIGNOVERRIDE => '0',
TXDLYALIGNUPDSW => '0',
TXDLYALIGNMONENB => '1',
TXRATEDONE => TXRATEDONE(i)
);
end generate;
end v6_pcie;
| gpl-3.0 | e2534ba3687a3512a6c935c0fd53597c | 0.427681 | 4.168508 | false | false | false | false |
Nixon-/VHDL_library | memory/RAM_1024x8.vhd | 1 | 808 | Library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity RAM_1024x8 is
port(
rd0_wr1,clk,enable:in std_logic;
address: in std_logic_vector(9 downto 0);
dataIN: in std_logic_vector( 7 downto 0);
dataOUT: out std_logic_vector(7 downto 0)
);
end RAM_1024x8;
architecture primary of RAM_1024x8 is
type RAM is array (1023 downto 0) of integer range 0 to 255;
begin
process(clk,rd0_wr1,enable,address, dataIN)
variable storage: RAM;
begin
if(clk' event and clk = '1') then
if(enable = '1') then
if(rd0_wr1 = '0') then
dataOUT <= std_logic_vector(to_unsigned(storage(to_integer(unsigned(address))),8));
elsif(rd0_wr1 = '1') then
storage(to_integer(unsigned(address))) := to_integer(unsigned(dataIN));
end if;
end if;
end if;
end process;
end;
| gpl-2.0 | 8d3c2d0baba46bf04956e57342d5db1b | 0.683168 | 2.865248 | false | false | false | false |
masaruohashi/tic-tac-toe | uart/registrador_deslocamento_transmissao.vhd | 1 | 1,373 | -- VHDL de um Registrador de Deslocamento para a direita
library ieee;
use ieee.std_logic_1164.all;
entity registrador_deslocamento_transmissao is
port(
clock: in std_logic;
enable: in std_logic;
load: in std_logic;
shift: in std_logic;
RIN: in std_logic;
entrada: in std_logic_vector(6 downto 0);
bit_out: out std_logic := '1';
saida: out std_logic_vector(11 downto 0));
end registrador_deslocamento_transmissao;
architecture exemplo of registrador_deslocamento_transmissao is
signal IQ : std_logic_vector(11 downto 0);
signal paridade : std_logic;
begin
process (clock, load, shift, IQ)
begin
-- usaremos paridade PAR
paridade <= entrada(0) xor entrada(1) xor entrada(2)
xor entrada(3) xor entrada(4) xor entrada(5)
xor entrada (6);
if (clock'event and clock = '1') then
if (load = '1') then
IQ(0) <= '1'; -- bit de repouso
IQ(1) <= '0'; -- start bit
IQ(8 downto 2) <= entrada; -- bits do caractere ASCII
IQ(9) <= paridade; -- paridade
IQ(11 downto 10) <= "11"; -- stop bits
end if;
if (shift = '1' and enable = '1') then
bit_out <= IQ(0);
IQ <= RIN & IQ(11 downto 1);
end if;
end if;
saida <= IQ;
end process;
end exemplo;
| mit | f853813aa70d92c9237b016f6cc6c756 | 0.574654 | 3.511509 | false | false | false | false |
JavierRizzoA/Sacagawea | sources/registers/Register12.vhd | 1 | 636 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Register12 is
Port (
d : in STD_LOGIC_VECTOR(11 downto 0) := X"000"; --Input.
load : in STD_LOGIC; --Load/Enable.
clr : in STD_LOGIC; --Async clear.
clk : in STD_LOGIC; --Clock.
q : out STD_LOGIC_VECTOR(11 downto 0) := X"000" --Output
);
end Register12;
architecture Behavioral of Register12 is
begin
process(clk, clr)
begin
if rising_edge(clk) then
if clr = '1' then
q <= "000000000000";
elsif load = '1' then
q <= d;
end if;
end if;
end process;
end Behavioral; | mit | e3ea0de6452ed39c63733c502d5d8956 | 0.558176 | 3.3125 | false | false | false | false |
Pinwino/dbg_ohwr | debugger_gw/wb_debugger.vhd | 1 | 13,867 | -------------------------------------------------------------------------------
-- Title : Wishbone Debugger component
-- Project : FMC DEL 1ns 4cha-stand-alone application (fmc-delay-1ns-4cha-sa)
-------------------------------------------------------------------------------
-- File : wb_debugger.vhd
-- Author : Jose Jimenez <[email protected]>
-- Company : University of Granada
-- Created : 2014-06-08
-- Last update: 2014-07-31
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-06-08 1.0 jjimenez Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.wishbone_pkg.all;
use work.genram_pkg.all;
use work.wb_irq_pkg.all;
use work.debugger_pkg.all;
use work.synthesis_descriptor.all;
entity wb_debugger is
generic(
g_dbg_dpram_size : integer;
g_dbg_init_file : string;
g_reset_vector : t_wishbone_address := x"00000000"; -- if wb_irq_lm32 from general-cores::proposed-master
g_msi_queues : natural := 1;
g_profile : string := "medium_icache_debug";
g_internal_time_ref : boolean := true;
g_timers : integer := 1;
g_slave_interface_mode: t_wishbone_interface_mode := PIPELINED;
g_slave_granularity : t_wishbone_address_granularity := BYTE);
port(
clk_sys : in std_logic;
reset_n : in std_logic;
master_i : in t_wishbone_master_in;
master_o : out t_wishbone_master_out;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
wrpc_uart_rxd_i : inout std_logic;
wrpc_uart_txd_o : inout std_logic;
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic;
dbg_indicator : out std_logic;
dbg_control_select : in std_logic);
end wb_debugger;
architecture Behavioral of wb_debugger is
function f_check_if_lm32_firmware_necessary return boolean is
begin
if(g_dbg_init_file /= "") then
return true;
else
return false;
end if;
end function;
function f_generate_irq_timer return integer is
begin
if(g_timers /= 0) then
return 1;
else
return 0;
end if;
end function;
function f_generate_time_ref return integer is
begin
if(g_internal_time_ref) then
return 1;
else
return 0;
end if;
end function;
function f_choose_lm32_firmware_file return string is
begin
if(g_dbg_init_file = "debugger") then
report "[Dbg Core] Using debugging firmware." severity note;
return "../../dbg.ram";
elsif (g_dbg_init_file = "FD_node") then
report "[Dbg Core] Using FMC Delay stand alone node firmware." severity note;
return "../../fd_std.ram";
else
report "[Dbg Core] Using user provided firmware." severity note;
return g_dbg_init_file;
end if;
end function;
function f_select_dpram_size return integer is
begin
if(g_dbg_init_file = "debugger") then
report "[Dbg Core] Using a 40960 Bytes size RAM." severity note;
return 40960/4;
elsif (g_dbg_init_file = "FD_node") then
report "[Dbg Core] Using a 94208 Bytes RAM." severity note;
return 94208/4;
else
report "[Dbg Core] Using user specifie size RAM size." severity note;
return g_dbg_dpram_size;
end if;
end function;
-- constant c_NUM_WB_MASTERS : integer := 6 + f_generate_irq_timer + f_generate_time_ref;
constant c_NUM_WB_MASTERS : integer := 4 + f_generate_irq_timer + f_generate_time_ref;
constant c_NUM_WB_SLAVES : integer := 3;
constant c_MASTER_LM32 : integer := 0;
constant c_MASTER_ADAPT : integer := 2;
constant c_EXT_BRIDGE : integer := 0;
constant c_SLAVE_DPRAM : integer := 1;
constant c_SLAVE_UART : integer := 2;
constant c_SLAVE_IRQ_CTRL : integer := 3;
constant c_SLAVE_TICS : integer := c_SLAVE_IRQ_CTRL + f_generate_time_ref;
constant c_SLAVE_TIMER_IRQ: integer := c_SLAVE_TICS + f_generate_irq_timer;
constant c_EXT_BRIDGE_SDB : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"000effff", x"00000000");
constant c_FREQ_DIVIDER : integer := 62500; -- LM32 clk = 62.5 Mhz
function f_generate_c_interconection_layout(
num_wb_masters : integer;
last_mandatory_slave : integer
)
return t_sdb_record_array is
variable interconnect_layout : t_sdb_record_array(NUM_WB_MASTERS-1 downto 0);
variable offset : integer range last_mandatory_slave to NUM_WB_MASTERS-1 := last_mandatory_slave;
variable adr_off: unsigned (c_wishbone_address_width-1 downto 0);
begin
-- Vader is Coming Look Busy
interconnect_layout (offset downto 0):=
(c_EXT_BRIDGE => f_sdb_embed_bridge(c_EXT_BRIDGE_SDB, x"00100000"),
c_SLAVE_DPRAM => f_sdb_embed_device(f_xwb_dbg_dpram(f_select_dpram_size), x"00000000"),
c_SLAVE_UART => f_sdb_embed_device(c_dbg_uart_sdb, x"00020100"),
c_SLAVE_IRQ_CTRL => f_sdb_embed_device(c_dbg_irq_ctrl_sdb, x"00020200"));
adr_off := x"00020300";
if (f_generate_time_ref /= 0) then
offset := offset + f_generate_time_ref;
interconnect_layout (offset) := f_sdb_embed_device(c_xwb_dbg_tics_sdb, t_wishbone_address(adr_off));
adr_off := adr_off + x"100";
end if;
if (f_generate_irq_timer /= 0) then
offset := offset + f_generate_irq_timer;
interconnect_layout (offset) := f_sdb_embed_device(c_dbg_irq_timer_sdb, t_wishbone_address(adr_off));
adr_off := adr_off + x"100";
end if;
--interconnect_layout (offset+1) := f_sdb_embed_synthesis(c_sdb_synthesis_info);
--interconnect_layout (offset+2) := f_sdb_embed_repo_url(c_sdb_repo_url);
return interconnect_layout;
end function;
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array := f_generate_c_interconection_layout (c_NUM_WB_MASTERS, c_SLAVE_IRQ_CTRL);
constant c_SDB_ADDRESS : t_wishbone_address := x"00020800";
signal cnx_master_out : t_wishbone_master_out_array(c_NUM_WB_MASTERS-1 downto 0);
signal cnx_master_in : t_wishbone_master_in_array (c_NUM_WB_MASTERS-1 downto 0);
signal cnx_slave_out : t_wishbone_slave_out_array(c_NUM_WB_SLAVES-1 downto 0);
signal cnx_slave_in : t_wishbone_slave_in_array (c_NUM_WB_SLAVES-1 downto 0);
signal dummy_debugger_ram_wbb_i : t_wishbone_slave_in;
signal forced_lm32_reset_n : std_logic := '1';
signal irq_slave_i : t_wishbone_slave_in_array(g_msi_queues-1 to 0);
signal irq_slave_o : t_wishbone_slave_out_array(g_msi_queues-1 to 0);
signal local_counter : unsigned (63 downto 0);
signal uart_dummy_i : std_logic;
signal uart_dummy_o : std_logic;
signal dbg_uart_rxd_i : std_logic;
signal dbg_uart_txd_o : std_logic;
signal use_dbg_uart : std_logic := '1';
signal state_control : unsigned (39 downto 0) := x"0000000000";
begin
dbg_indicator <= forced_lm32_reset_n;
master_o <= cnx_master_out(c_EXT_BRIDGE);
cnx_master_in(c_EXT_BRIDGE) <= master_i;
--------------------------------------
-- UART Selector & Reset controller
--------------------------------------
controller : process (clk_sys)
begin
if (rising_edge(clk_sys)) then
if (dbg_control_select = '0') then
if (state_control /= x"ffffffffff") then
state_control <= state_control + 1;
end if;
else
if ((state_control /= x"0000000000") and (state_control <= x"3B9ACA0")) then --0.5s
forced_lm32_reset_n <= not forced_lm32_reset_n;
elsif (state_control > x"3B9ACA0") then
use_dbg_uart <= not use_dbg_uart;
end if;
state_control <= x"0000000000";
end if;
end if;
end process;
--------------------------------------
-- UART
--------------------------------------
uart_txd_o <= dbg_uart_txd_o when use_dbg_uart ='1' else wrpc_uart_txd_o;
dbg_uart_rxd_i <= uart_rxd_i when use_dbg_uart ='1' else '1';
wrpc_uart_rxd_i <= uart_rxd_i when use_dbg_uart ='0' else '1';
DBG_UART : xwb_simple_uart
generic map(
g_with_virtual_uart => true,
g_with_physical_uart => true,
g_interface_mode => PIPELINED,
g_address_granularity => BYTE
)
port map(
clk_sys_i => clk_sys,
rst_n_i => reset_n,
slave_i => cnx_master_out(c_SLAVE_UART),
slave_o => cnx_master_in(c_SLAVE_UART),
desc_o => open,
uart_rxd_i => dbg_uart_rxd_i,
uart_txd_o => dbg_uart_txd_o
);
-----------------------------------------------------------------------------
-- LM32, with MSI interface
-----------------------------------------------------------------------------
DBG_IRQ_LM32_CORE : wb_irq_lm32
generic map(
g_msi_queues => g_msi_queues,
g_profile => g_profile
)
port map(
clk_sys_i => clk_sys,
rst_n_i => forced_lm32_reset_n,
dwb_o => cnx_slave_in(c_MASTER_LM32),
dwb_i => cnx_slave_out(c_MASTER_LM32),
iwb_o => cnx_slave_in(c_MASTER_LM32+1),
iwb_i => cnx_slave_out(c_MASTER_LM32+1),
irq_slave_o => irq_slave_o, -- wb msi interface
irq_slave_i => irq_slave_i,
ctrl_slave_o => cnx_master_in(c_SLAVE_IRQ_CTRL), -- ctrl interface for LM32 irq processing
ctrl_slave_i => cnx_master_out(c_SLAVE_IRQ_CTRL)
);
---------------------------------------------------------------------------
-- Dual-port RAM
-----------------------------------------------------------------------------
DBG_DPRAM : xwb_dpram
generic map(
g_size => f_select_dpram_size, --in 32-bit words
-- g_size => g_dbg_dpram_size, --in 32-bit words
g_init_file => f_choose_lm32_firmware_file,
g_must_have_init_file => f_check_if_lm32_firmware_necessary,
g_slave1_interface_mode => PIPELINED,
g_slave2_interface_mode => PIPELINED,
g_slave1_granularity => BYTE,
g_slave2_granularity => WORD
)
port map(
clk_sys_i => clk_sys,
rst_n_i => reset_n,
slave1_i => cnx_master_out(c_SLAVE_DPRAM),
slave1_o => cnx_master_in(c_SLAVE_DPRAM),
slave2_i => dummy_debugger_ram_wbb_i,
slave2_o => open
);
---------------------------------------------------------------------------
-- TIMER
---------------------------------------------------------------------------
gen_time_ref : if (f_generate_time_ref /= 0) generate
begin
DBG_TIME_REF : xwb_tics
generic map(
g_period => c_FREQ_DIVIDER
)
port map(
clk_sys_i => clk_sys,
rst_n_i => reset_n,
-- Wishbone
slave_i => cnx_master_out(c_SLAVE_TICS),
slave_o => cnx_master_in(c_SLAVE_TICS),
desc_o => open
);
end generate gen_time_ref;
gen_timer : if (g_timers > 0) generate
begin
process(clk_sys)
begin
if (clk_sys'event and clk_sys = '1') then
if (reset_n = '0') then
local_counter <= (others => '0');
else
local_counter <= local_counter + 1;
end if;
end if;
end process;
DBG_IRQ_TIMER : wb_irq_timer
generic map(
g_timers => g_timers
)
port map(
clk_sys_i => clk_sys,
rst_sys_n_i => forced_lm32_reset_n,
tm_tai8ns_i => std_logic_vector(local_counter),
ctrl_slave_o => cnx_master_in(c_SLAVE_TIMER_IRQ), -- ctrl interface for LM32 irq processing
ctrl_slave_i => cnx_master_out(c_SLAVE_TIMER_IRQ),
irq_master_o => irq_slave_i(g_timers-1), -- wb msi interface
irq_master_i => irq_slave_o(g_timers-1)
);
end generate gen_timer;
---------------------------------------------------------------------------
-- Crossbar
---------------------------------------------------------------------------
DBG_MAIN_INTERCON : xwb_sdb_crossbar
generic map (
g_num_masters => c_NUM_WB_SLAVES,
g_num_slaves => c_NUM_WB_MASTERS,
g_registered => true,
g_wraparound => true,
g_layout => c_INTERCONNECT_LAYOUT,
g_sdb_addr => c_SDB_ADDRESS
)
port map (
clk_sys_i => clk_sys,
rst_n_i => reset_n,
slave_i => cnx_slave_in,
slave_o => cnx_slave_out,
master_i => cnx_master_in,
master_o => cnx_master_out
);
---------------------------------------------------------------------------
-- Adatper
---------------------------------------------------------------------------
DBG_SALVE_ADAPTER : wb_slave_adapter
generic map (
g_master_use_struct => true,
g_master_mode => g_slave_interface_mode,
g_master_granularity => BYTE,
g_slave_use_struct => false,
g_slave_mode => g_slave_interface_mode,
g_slave_granularity => g_slave_granularity)
port map (
clk_sys_i => clk_sys,
rst_n_i => reset_n,
master_i => cnx_slave_out(c_MASTER_ADAPT),
master_o => cnx_slave_in(c_MASTER_ADAPT),
-- Slave interface 0x0 to 0x3ffff
sl_adr_i(c_wishbone_address_width-1 downto 18) => (others => '0'),
sl_adr_i(17 downto 0) => slave_i.adr(17 downto 0),
sl_dat_i => slave_i.dat,
sl_sel_i => slave_i.sel,
sl_cyc_i => slave_i.cyc,
sl_stb_i => slave_i.stb,
sl_we_i => slave_i.we,
sl_dat_o => slave_o.dat,
sl_ack_o => slave_o.ack,
sl_err_o => slave_o.err,
sl_rty_o => slave_o.rty,
sl_stall_o => slave_o.stall
);
end Behavioral;
| gpl-3.0 | c936c3297fac49278280179e6e7ab94c | 0.540564 | 3.375609 | false | false | false | false |
timofonic/PHDL | misc/projects/spartan_pcie_board/fpga/lx45t_pinout/ipcore_dir/pcie_core/example_design/PIO_32_RX_ENGINE.vhd | 1 | 18,672 | -------------------------------------------------------------------------------
--
-- (c) Copyright 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Project : Spartan-6 Integrated Block for PCI Express
-- File : PIO_32_RX_ENGINE.vhd
-- Description: 32-bit Local-Link Receive Unit.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity PIO_32_RX_ENGINE is
port (
clk : in std_logic;
rst_n : in std_logic;
--
-- Receive local link interface from PCIe core
--
trn_rd : in std_logic_vector(31 downto 0);
trn_rsof_n : in std_logic;
trn_reof_n : in std_logic;
trn_rsrc_rdy_n : in std_logic;
trn_rsrc_dsc_n : in std_logic;
trn_rbar_hit_n : in std_logic_vector(6 downto 0);
trn_rdst_rdy_n : out std_logic;
--
-- Memory Read data handshake with Completion
-- transmit unit. Transmit unit reponds to
-- req_compl assertion and responds with compl_done
-- assertion when a Completion w/ data is transmitted.
--
req_compl_o : out std_logic;
req_compl_with_data_o : out std_logic;
compl_done_i : in std_logic;
req_tc_o : out std_logic_vector(2 downto 0); -- Memory Read TC
req_td_o : out std_logic; -- Memory Read TD
req_ep_o : out std_logic; -- Memory Read EP
req_attr_o : out std_logic_vector(1 downto 0); -- Memory Read Attribute
req_len_o : out std_logic_vector(9 downto 0); -- Memory Read Length (1DW)
req_rid_o : out std_logic_vector(15 downto 0); -- Memory Read Requestor ID
req_tag_o : out std_logic_vector(7 downto 0); -- Memory Read Tag
req_be_o : out std_logic_vector(7 downto 0); -- Memory Read Byte Enables
req_addr_o : out std_logic_vector(12 downto 0); -- Memory Read Address
--
-- Memory interface used to save 1 DW data received
-- on Memory Write 32 TLP. Data extracted from
-- inbound TLP is presented to the Endpoint memory
-- unit. Endpoint memory unit reacts to wr_en_o
-- assertion and asserts wr_busy_i when it is
-- processing written information.
--
wr_addr_o : out std_logic_vector(10 downto 0); -- Memory Write Address
wr_be_o : out std_logic_vector(7 downto 0); -- Memory Write Byte Enable
wr_data_o : out std_logic_vector(31 downto 0); -- Memory Write Data
wr_en_o : out std_logic; -- Memory Write Enable
wr_busy_i : in std_logic -- Memory Write Busy
);
end PIO_32_RX_ENGINE;
architecture rtl of PIO_32_RX_ENGINE is
-- Clock-to-out delay
constant TCQ : time := 1 ns;
-- TLP Header format/type values
constant PIO_32_RX_MEM_RD32_FMT_TYPE : std_logic_vector(6 downto 0) := "0000000";
constant PIO_32_RX_MEM_WR32_FMT_TYPE : std_logic_vector(6 downto 0) := "1000000";
constant PIO_32_RX_MEM_RD64_FMT_TYPE : std_logic_vector(6 downto 0) := "0100000";
constant PIO_32_RX_MEM_WR64_FMT_TYPE : std_logic_vector(6 downto 0) := "1100000";
constant PIO_32_RX_IO_RD32_FMT_TYPE : std_logic_vector(6 downto 0) := "0000010";
constant PIO_32_RX_IO_WR32_FMT_TYPE : std_logic_vector(6 downto 0) := "1000010";
-- States
type state_type is (
PIO_32_RX_RST_STATE,
PIO_32_RX_MEM_RD32_DW1,
PIO_32_RX_MEM_RD32_DW2,
PIO_32_RX_IO_MEM_WR32_DW1,
PIO_32_RX_IO_MEM_WR32_DW2,
PIO_32_RX_IO_MEM_WR32_DW3,
PIO_32_RX_IO_MEM_WR32_DW4,
PIO_32_RX_MEM_RD64_DW1,
PIO_32_RX_MEM_RD64_DW2,
PIO_32_RX_MEM_RD64_DW3,
PIO_32_RX_MEM_WR64_DW1,
PIO_32_RX_MEM_WR64_DW2,
PIO_32_RX_MEM_WR64_DW3,
PIO_32_RX_MEM_WR64_DW4,
PIO_32_RX_WAIT_STATE
);
signal state : state_type;
signal tlp_type : std_logic_vector(6 downto 0);
signal trn_rdst_rdy_n_int : std_logic;
signal io_bar_hit_n : std_logic;
signal mem32_bar_hit_n : std_logic;
signal mem64_bar_hit_n : std_logic;
signal erom_bar_hit_n : std_logic;
signal bar_hit_select : std_logic_vector(3 downto 0);
signal region_select : std_logic_vector(1 downto 0);
begin
trn_rdst_rdy_n <= trn_rdst_rdy_n_int;
process begin
wait until rising_edge(clk);
if (rst_n = '0') then
trn_rdst_rdy_n_int <= '0' after TCQ;
req_compl_o <= '0' after TCQ;
req_compl_with_data_o <= '1' after TCQ;
req_tc_o <= (others => '0') after TCQ;
req_td_o <= '0' after TCQ;
req_ep_o <= '0' after TCQ;
req_attr_o <= (others => '0') after TCQ;
req_len_o <= (others => '0') after TCQ;
req_rid_o <= (others => '0') after TCQ;
req_tag_o <= (others => '0') after TCQ;
req_be_o <= (others => '0') after TCQ;
req_addr_o <= (others => '0') after TCQ;
wr_be_o <= (others => '0') after TCQ;
wr_addr_o <= (others => '0') after TCQ;
wr_data_o <= (others => '0') after TCQ;
wr_en_o <= '0' after TCQ;
state <= PIO_32_RX_RST_STATE after TCQ;
tlp_type <= (others => '0') after TCQ;
else
wr_en_o <= '0' after TCQ;
req_compl_o <= '0' after TCQ;
req_compl_with_data_o <= '1' after TCQ;
case (state) is
when PIO_32_RX_RST_STATE =>
trn_rdst_rdy_n_int <= '0' after TCQ;
tlp_type <= trn_rd(30 downto 24) after TCQ;
req_tc_o <= trn_rd(22 downto 20) after TCQ;
req_td_o <= trn_rd(15) after TCQ;
req_ep_o <= trn_rd(14) after TCQ;
req_attr_o <= trn_rd(13 downto 12) after TCQ;
req_len_o <= trn_rd(9 downto 0) after TCQ;
if ((trn_rsof_n = '0') and (trn_rsrc_rdy_n = '0') and (trn_rdst_rdy_n_int = '0')) then
case (trn_rd(30 downto 24)) is
when PIO_32_RX_MEM_RD32_FMT_TYPE =>
if (trn_rd(9 downto 0) = "0000000001") then
state <= PIO_32_RX_MEM_RD32_DW1 after TCQ;
else
state <= PIO_32_RX_RST_STATE after TCQ;
end if;
when PIO_32_RX_MEM_WR32_FMT_TYPE =>
if (trn_rd(9 downto 0) = "0000000001") then
state <= PIO_32_RX_IO_MEM_WR32_DW1 after TCQ;
else
state <= PIO_32_RX_RST_STATE after TCQ;
end if;
when PIO_32_RX_MEM_RD64_FMT_TYPE =>
if (trn_rd(9 downto 0) = "0000000001") then
state <= PIO_32_RX_MEM_RD64_DW1 after TCQ;
else
state <= PIO_32_RX_RST_STATE after TCQ;
end if;
when PIO_32_RX_MEM_WR64_FMT_TYPE =>
if (trn_rd(9 downto 0) = "0000000001") then
state <= PIO_32_RX_MEM_WR64_DW1 after TCQ;
else
state <= PIO_32_RX_RST_STATE after TCQ;
end if;
when PIO_32_RX_IO_RD32_FMT_TYPE =>
if (trn_rd(9 downto 0) = "0000000001") then
state <= PIO_32_RX_MEM_RD32_DW1 after TCQ;
else
state <= PIO_32_RX_RST_STATE after TCQ;
end if;
when PIO_32_RX_IO_WR32_FMT_TYPE =>
if (trn_rd(9 downto 0) = "0000000001") then
state <= PIO_32_RX_IO_MEM_WR32_DW1 after TCQ;
else
state <= PIO_32_RX_RST_STATE after TCQ;
end if;
when others => -- other TLPs
state <= PIO_32_RX_RST_STATE after TCQ;
end case; -- trn_rd(30 downto 24)
else -- ((trn_rsof_n = '0') and (trn_rsrc_rdy_n = '0') and (trn_rdst_rdy_n_int = '0'))
state <= PIO_32_RX_RST_STATE after TCQ;
end if;
-- end of PIO_32_RX_RST_STATE
when PIO_32_RX_MEM_RD32_DW1 =>
if ((trn_rsrc_rdy_n = '0') and (trn_rdst_rdy_n_int ='0')) then
req_rid_o <= trn_rd(31 downto 16) after TCQ;
req_tag_o <= trn_rd(15 downto 8) after TCQ;
req_be_o <= trn_rd(7 downto 0) after TCQ;
state <= PIO_32_RX_MEM_RD32_DW2 after TCQ;
else
state <= PIO_32_RX_MEM_RD32_DW1 after TCQ;
end if;
-- end of PIO_32_RX_MEM_RD32_DW1
when PIO_32_RX_MEM_RD32_DW2 =>
if ((trn_rsrc_rdy_n = '0') and (trn_rdst_rdy_n_int = '0')) then
req_addr_o <= region_select(1 downto 0) & trn_rd(10 downto 2) & "00" after TCQ;
req_compl_o <= '1' after TCQ;
trn_rdst_rdy_n_int <= '1' after TCQ;
state <= PIO_32_RX_WAIT_STATE after TCQ;
else
state <= PIO_32_RX_MEM_RD32_DW2 after TCQ;
end if;
-- end of PIO_32_RX_MEM_RD32_DW2
when PIO_32_RX_IO_MEM_WR32_DW1 =>
if ((trn_rsrc_rdy_n = '0') and (trn_rdst_rdy_n_int = '0')) then
wr_be_o <= trn_rd(7 downto 0) after TCQ;
state <= PIO_32_RX_IO_MEM_WR32_DW2 after TCQ;
else
state <= PIO_32_RX_IO_MEM_WR32_DW1 after TCQ;
end if;
-- end of PIO_32_RX_IO_MEM_WR32_DW1
when PIO_32_RX_IO_MEM_WR32_DW2 =>
if ((trn_rsrc_rdy_n = '0') and (trn_rdst_rdy_n_int = '0')) then
wr_addr_o <= region_select(1 downto 0) & trn_rd(10 downto 2) after TCQ;
state <= PIO_32_RX_IO_MEM_WR32_DW3 after TCQ;
else
state <= PIO_32_RX_IO_MEM_WR32_DW2 after TCQ;
end if;
-- end of PIO_32_RX_IO_MEM_WR32_DW2
when PIO_32_RX_IO_MEM_WR32_DW3 =>
if ((trn_rsrc_rdy_n = '0') and (trn_rdst_rdy_n_int = '0')) then
wr_data_o <= trn_rd(31 downto 0) after TCQ;
wr_en_o <= '1' after TCQ;
if (tlp_type = PIO_32_RX_IO_WR32_FMT_TYPE) then
req_compl_o <= '1' after TCQ;
else
req_compl_o <= '0' after TCQ;
end if;
req_compl_with_data_o <= '0' after TCQ;
trn_rdst_rdy_n_int <= '1' after TCQ;
state <= PIO_32_RX_WAIT_STATE after TCQ;
else
state <= PIO_32_RX_IO_MEM_WR32_DW3 after TCQ;
end if;
-- end of PIO_32_RX_IO_MEM_WR32_DW3
when PIO_32_RX_MEM_RD64_DW1 =>
if ((trn_rsrc_rdy_n = '0') and (trn_rdst_rdy_n_int ='0')) then
req_rid_o <= trn_rd(31 downto 16) after TCQ;
req_tag_o <= trn_rd(15 downto 8) after TCQ;
req_be_o <= trn_rd(7 downto 0) after TCQ;
state <= PIO_32_RX_MEM_RD64_DW2 after TCQ;
else
state <= PIO_32_RX_MEM_RD64_DW1 after TCQ;
end if;
-- end of PIO_32_RX_MEM_RD64_DW1
when PIO_32_RX_MEM_RD64_DW2 =>
if ((trn_rsrc_rdy_n = '0') and (trn_rdst_rdy_n_int = '0')) then
state <= PIO_32_RX_MEM_RD64_DW3 after TCQ;
else
state <= PIO_32_RX_MEM_RD64_DW2 after TCQ;
end if;
-- end of PIO_32_RX_MEM_RD64_DW2
when PIO_32_RX_MEM_RD64_DW3 =>
if ((trn_rsrc_rdy_n = '0') and (trn_rdst_rdy_n_int = '0')) then
req_addr_o <= region_select(1 downto 0) & trn_rd(10 downto 2) & "00" after TCQ;
req_compl_o <= '1' after TCQ;
trn_rdst_rdy_n_int <= '1' after TCQ;
state <= PIO_32_RX_WAIT_STATE after TCQ;
else
state <= PIO_32_RX_MEM_RD64_DW3 after TCQ;
end if;
-- end of PIO_32_RX_MEM_RD64_DW3
when PIO_32_RX_MEM_WR64_DW1 =>
if ((trn_rsrc_rdy_n = '0') and (trn_rdst_rdy_n_int = '0')) then
wr_be_o <= trn_rd(7 downto 0) after TCQ;
state <= PIO_32_RX_MEM_WR64_DW2 after TCQ;
else
state <= PIO_32_RX_MEM_WR64_DW1 after TCQ;
end if;
-- end of PIO_32_RX_MEM_WR64_DW1
when PIO_32_RX_MEM_WR64_DW2 =>
if ((trn_rsrc_rdy_n = '0') and (trn_rdst_rdy_n_int = '0')) then
state <= PIO_32_RX_MEM_WR64_DW3 after TCQ;
else
state <= PIO_32_RX_MEM_WR64_DW2 after TCQ;
end if;
-- end of PIO_32_RX_MEM_WR64_DW2
when PIO_32_RX_MEM_WR64_DW3 =>
if ((trn_rsrc_rdy_n = '0') and (trn_rdst_rdy_n_int = '0')) then
wr_addr_o <= region_select(1 downto 0) & trn_rd(10 downto 2) after TCQ;
state <= PIO_32_RX_MEM_WR64_DW4 after TCQ;
else
state <= PIO_32_RX_MEM_WR64_DW3 after TCQ;
end if;
-- end of PIO_32_RX_MEM_WR64_DW3
when PIO_32_RX_MEM_WR64_DW4 =>
if ((trn_rsrc_rdy_n = '0') and (trn_rdst_rdy_n_int = '0')) then
wr_data_o <= trn_rd(31 downto 0) after TCQ;
wr_en_o <= '1' after TCQ;
trn_rdst_rdy_n_int <= '1' after TCQ;
state <= PIO_32_RX_WAIT_STATE after TCQ;
else
state <= PIO_32_RX_MEM_WR64_DW4 after TCQ;
end if;
-- end of PIO_32_RX_MEM_WR64_DW4
when PIO_32_RX_WAIT_STATE =>
wr_en_o <= '0' after TCQ;
req_compl_o <= '0' after TCQ;
if ((tlp_type = PIO_32_RX_MEM_WR32_FMT_TYPE) and (wr_busy_i = '0')) then
trn_rdst_rdy_n_int <= '0' after TCQ;
state <= PIO_32_RX_RST_STATE after TCQ;
elsif ((tlp_type = PIO_32_RX_IO_WR32_FMT_TYPE) and (wr_busy_i = '0')) then
trn_rdst_rdy_n_int <= '0' after TCQ;
state <= PIO_32_RX_RST_STATE after TCQ;
elsif ((tlp_type = PIO_32_RX_MEM_WR64_FMT_TYPE) and (wr_busy_i = '0')) then
trn_rdst_rdy_n_int <= '0' after TCQ;
state <= PIO_32_RX_RST_STATE after TCQ;
elsif ((tlp_type = PIO_32_RX_MEM_RD32_FMT_TYPE) and (compl_done_i = '1')) then
trn_rdst_rdy_n_int <= '0' after TCQ;
state <= PIO_32_RX_RST_STATE after TCQ;
elsif ((tlp_type = PIO_32_RX_IO_RD32_FMT_TYPE) and (compl_done_i = '1')) then
trn_rdst_rdy_n_int <= '0' after TCQ;
state <= PIO_32_RX_RST_STATE after TCQ;
elsif ((tlp_type = PIO_32_RX_MEM_RD64_FMT_TYPE) and (compl_done_i = '1')) then
trn_rdst_rdy_n_int <= '0' after TCQ;
state <= PIO_32_RX_RST_STATE after TCQ;
else
state <= PIO_32_RX_WAIT_STATE after TCQ;
end if;
-- end of PIO_32_RX_WAIT_STATE
when others =>
state <= PIO_32_RX_WAIT_STATE after TCQ;
end case;
end if;
end process;
mem64_bar_hit_n <= '1';
io_bar_hit_n <= '1';
mem32_bar_hit_n <= trn_rbar_hit_n(0);
erom_bar_hit_n <= trn_rbar_hit_n(6);
bar_hit_select <= io_bar_hit_n & mem32_bar_hit_n & mem64_bar_hit_n & erom_bar_hit_n;
process (bar_hit_select) begin
case (bar_hit_select) is
when "0111" =>
region_select <= "00";
when "1011" =>
region_select <= "01";
when "1101" =>
region_select <= "10";
when "1110" =>
region_select <= "11";
when others =>
region_select <= "00";
end case;
end process;
end; -- PIO_32_RX_ENGINE
| gpl-3.0 | a5884cd26ad78aae3e8db44ffdc0cdd9 | 0.50964 | 3.311225 | false | false | false | false |
timofonic/PHDL | misc/projects/spartan_pcie_board/fpga/lx45t_pinout/ipcore_dir/pcie_core/simulation/dsport/pcie_upconfig_fix_3451_v6.vhd | 1 | 6,906 | -------------------------------------------------------------------------------
--
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Project : Spartan-6 Integrated Block for PCI Express
-- File : pcie_upconfig_fix_3451_v6.vhd
-- Description: Virtex6 Workaround for Root Port Upconfigurability Bug
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity pcie_upconfig_fix_3451_v6 is
generic (
UPSTREAM_FACING : boolean := TRUE;
PL_FAST_TRAIN : boolean := FALSE;
LINK_CAP_MAX_LINK_WIDTH : bit_vector := X"08"
);
port (
pipe_clk : in std_logic;
pl_phy_lnkup_n : in std_logic;
pl_ltssm_state : in std_logic_vector(5 downto 0);
pl_sel_lnk_rate : in std_logic;
pl_directed_link_change : in std_logic_vector(1 downto 0);
cfg_link_status_negotiated_width : in std_logic_vector(3 downto 0);
filter_pipe : out std_logic
);
end pcie_upconfig_fix_3451_v6;
architecture v6_pcie of pcie_upconfig_fix_3451_v6 is
constant TCQ : integer := 1;
signal reg_filter_pipe : std_logic;
signal reg_prev_pl_ltssm_state : std_logic_vector(5 downto 0);
signal prev_pl_ltssm_state : std_logic_vector(5 downto 0);
signal reg_tsx_counter : std_logic_vector(15 downto 0);
signal tsx_counter : std_logic_vector(15 downto 0);
signal cap_link_width : std_logic_vector(5 downto 0);
-- X-HDL generated signals
signal v6pcie1 : std_logic_vector(15 downto 0);
signal v6pcie2 : std_logic_vector(15 downto 0);
-- Declare intermediate signals for referenced outputs
signal filter_pipe_v6pcie0 : std_logic;
begin
-- Drive referenced outputs
filter_pipe <= filter_pipe_v6pcie0;
-- Corrupting all Tsx on all lanes as soon as we do R.RC->R.RI transition to allow time for
-- the core to see the TS1s on all the lanes being configured at the same time
-- R.RI has a 2ms timeout.Corrupting tsxs for ~1/4 of that time
-- 225 (00E1 Hex) pipe_clk cycles-sim_fast_train
-- 60000 (EA60 Hex) pipe_clk cycles-without sim_fast_train
-- Not taking any action when PLDIRECTEDLINKCHANGE is set
v6pcie1 <= X"7530" when (pl_sel_lnk_rate = '1') else
X"EA60";
v6pcie2 <= X"00E1" when (PL_FAST_TRAIN) else
v6pcie1;
process (pipe_clk)
begin
if (pipe_clk'event and pipe_clk = '1') then
if (pl_phy_lnkup_n = '1') then
reg_tsx_counter <= "0000000000000000" after (TCQ)*1 ps;
reg_filter_pipe <= '0' after (TCQ)*1 ps;
elsif ((pl_ltssm_state = "100000") and (prev_pl_ltssm_state = "011101") and (("00" & cfg_link_status_negotiated_width) /= cap_link_width(5 downto 0)) and (pl_directed_link_change(1 downto 0) = "00")) then
reg_tsx_counter <= "0000000000000000" after (TCQ)*1 ps;
reg_filter_pipe <= '1' after (TCQ)*1 ps;
elsif (filter_pipe_v6pcie0 = '1') then
if (tsx_counter < v6pcie2) then
reg_tsx_counter <= tsx_counter + "0000000000000001" after (TCQ)*1 ps;
reg_filter_pipe <= '1' after (TCQ)*1 ps;
else
reg_tsx_counter <= "0000000000000000" after (TCQ)*1 ps;
reg_filter_pipe <= '0' after (TCQ)*1 ps;
end if;
end if;
end if;
end process;
filter_pipe_v6pcie0 <= '0' when (UPSTREAM_FACING) else
reg_filter_pipe;
tsx_counter <= reg_tsx_counter;
process (pipe_clk)
begin
if (pipe_clk'event and pipe_clk = '1') then
if (pl_phy_lnkup_n = '1') then
reg_prev_pl_ltssm_state <= "000000" after (TCQ)*1 ps;
else
reg_prev_pl_ltssm_state <= pl_ltssm_state after (TCQ)*1 ps;
end if;
end if;
end process;
prev_pl_ltssm_state <= reg_prev_pl_ltssm_state;
cap_link_width <= to_stdlogicvector(LINK_CAP_MAX_LINK_WIDTH);
end v6_pcie;
| gpl-3.0 | c89845d703849e8e2f9e38c18dfc062e | 0.582247 | 4.026822 | false | false | false | false |
JavierRizzoA/Sacagawea | sources/ROM.vhd | 1 | 11,243 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ROM is
port (clk : in std_logic;
rom_enable: in std_logic;
direccion : in std_logic_vector(9 downto 0);
rom_datos : out std_logic_vector(7 downto 0));
end ROM;
architecture syn of ROM is
type rom_type is array (0 to 1023) of std_logic_vector (7 downto 0);
signal ROM : rom_type:= (X"20", X"2C", X"13", X"00", X"20", X"24", X"1C", X"05",
X"B0", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00");
signal rdata : std_logic_vector(7 downto 0);
begin
rdata <= ROM(conv_integer(direccion));
process (clk)
begin
if (clk'event and clk = '1') then
if (rom_enable = '1') then
rom_datos <= rdata;
else
rom_datos <= "ZZZZZZZZ";
end if;
end if;
end process;
end syn;
| mit | 2116794146d5d3e4a25057f337add0fa | 0.31255 | 2.528221 | false | false | false | false |
masaruohashi/tic-tac-toe | interface_jogo/contador_tabuleiro.vhd | 1 | 844 | -- VHDL de um contador para a impressao do tabuleiro
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity contador_tabuleiro is
port(
clock : in std_logic;
zera : in std_logic;
conta : in std_logic;
contagem : out std_logic_vector(6 downto 0);
fim : out std_logic
);
end contador_tabuleiro;
architecture exemplo of contador_tabuleiro is
signal IQ: unsigned(6 downto 0);
begin
process (clock, conta, IQ, zera)
begin
if zera = '1' then
IQ <= (others => '0');
elsif clock'event and clock = '1' then
if (conta = '1') then
IQ <= IQ + 1;
end if;
end if;
if IQ = 77 then
fim <= '1';
else
fim <= '0';
end if;
contagem <= std_logic_vector(IQ);
end process;
end exemplo;
| mit | 272bcd044f6ca137ef423d3b1f307d1d | 0.56872 | 3.284047 | false | false | false | false |
timofonic/PHDL | misc/projects/spartan_pcie_board/fpga/lx45t_pinout/ipcore_dir/pcie_core/simulation/functional/sys_clk_gen.vhd | 1 | 3,296 | -------------------------------------------------------------------------------
--
-- (c) Copyright 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Project : Spartan-6 Integrated Block for PCI Express
-- File : sys_clk_gen.vhd
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity sys_clk_gen is
generic
(
HALFCYCLE : integer := 500;
OFFSET : integer := 0
);
port
(
sys_clk : out std_logic
);
end sys_clk_gen;
architecture sim of sys_clk_gen is
constant HALFCYCLE_INT : time := HALFCYCLE * 1 ps;
constant OFFSET_INT : time := OFFSET * 1 ps;
signal sys_clk_c : std_logic := '0';
begin
clk_gen : process
begin
wait for OFFSET_INT;
while true loop
wait for HALFCYCLE_INT;
sys_clk_c <= not sys_clk_c;
end loop;
end process clk_gen;
sys_clk <= sys_clk_c;
end; -- sys_clk_gen
| gpl-3.0 | c89ea69cd51a25396a76e54ab06d1c20 | 0.652306 | 4.214834 | false | false | false | false |
masaruohashi/tic-tac-toe | uart/registrador_dado_recebido.vhd | 1 | 705 | -- VHDL de um Registrador de dados para a recepcao
library ieee;
use ieee.std_logic_1164.all;
entity registrador_dado_recebido is
port(
clock: in std_logic;
enable: in std_logic;
clear: in std_logic;
entrada: in std_logic_vector(11 downto 0);
saida: out std_logic_vector(11 downto 0)
);
end registrador_dado_recebido;
architecture exemplo of registrador_dado_recebido is
signal IQ : std_logic_vector(11 downto 0);
begin
process (clock, enable, clear, IQ)
begin
if (clock'event and clock = '1') then
if clear = '1' then
IQ <= (others => '0');
elsif enable = '1' then
IQ <= entrada;
end if;
end if;
saida <= IQ;
end process;
end exemplo;
| mit | 9a6e684d26a2c0edce12455ff9e4116d | 0.655319 | 3.248848 | false | false | false | false |
masaruohashi/tic-tac-toe | uart/recepcao_serial.vhd | 1 | 2,368 | -- VHDL do Sistema Digital
library ieee;
use ieee.std_logic_1164.all;
entity recepcao_serial is
port(
clock: in std_logic;
reset: in std_logic;
entrada: in std_logic;
recebe_dado: in std_logic;
dado_rec: out std_logic_vector(11 downto 0);
tem_dado_rec: out std_logic;
dep_paridade_ok: out std_logic;
dep_tick_rx: out std_logic;
dep_estados: out std_logic_vector(5 downto 0);
dep_habilita_recepcao: out std_logic
);
end recepcao_serial;
architecture estrutural of recepcao_serial is
component circuito_recepcao is
port(
dado_serial : in std_logic;
reset : in std_logic;
clock : in std_logic;
tick : in std_logic;
dados_ascii : out std_logic_vector(11 downto 0);
saidas_estado : out std_logic_vector(5 downto 0);
pronto : out std_logic;
paridade_ok : out std_logic;
dep_habilita_recepcao : out std_logic
);
end component;
component interface_recepcao is
port(
clock: in std_logic;
reset: in std_logic;
pronto: in std_logic;
paridade_ok: in std_logic;
recebe_dado: in std_logic;
dado_entrada: in std_logic_vector(11 downto 0);
tem_dado_rec: out std_logic;
dado_rec: out std_logic_vector(11 downto 0)
);
end component;
component gerador_tick is
generic(
M: integer := 454545 -- para transmissao de 110 bauds
);
port(
clock, reset: in std_logic;
tick: out std_logic
);
end component;
signal sinal_tick: std_logic;
signal sinal_dados_ascii: std_logic_vector(11 downto 0);
signal sinal_pronto: std_logic;
signal sinal_paridade_ok: std_logic;
begin
circuito : circuito_recepcao port map (entrada, reset, clock, sinal_tick, sinal_dados_ascii, dep_estados, sinal_pronto, sinal_paridade_ok, dep_habilita_recepcao);
gera_tick: gerador_tick generic map (M => 28409) port map(clock, reset, sinal_tick);
--para teste usar a linha abaixo de comentar a de cima
--gera_tick: gerador_tick generic map (M => 2) port map(clock, reset, sinal_tick);
interface: interface_recepcao port map (clock, reset, sinal_pronto, sinal_paridade_ok, recebe_dado, sinal_dados_ascii, tem_dado_rec, dado_rec);
dep_paridade_ok <= sinal_paridade_ok;
dep_tick_rx <= sinal_tick;
end estrutural;
| mit | c6a7cbf20e0e99613005c69de45e5139 | 0.648649 | 3.373219 | false | false | false | false |
JavierRizzoA/Sacagawea | sources/RAM.vhd | 1 | 1,054 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity RAM is
port (
clk : in std_logic;
write_read : in std_logic; -- write = 1 read = 0
ram_enable : in std_logic;
direccion : in std_logic_vector(9 downto 0);
ram_datos_escritura : out std_logic_vector(7 downto 0);
ram_datos_lectura : in std_logic_vector(7 downto 0)
);
end RAM;
architecture syn of RAM is
type ram_type is array (0 to 1023) of std_logic_vector (7 downto 0);
signal RAM: ram_type;
attribute ram_style : string;
attribute ram_style of RAM : signal is "block";
begin
process (clk)
begin
if clk'event and clk = '1' then
if ram_enable = '1' then
if write_read = '1' then
RAM(conv_integer(direccion)) <= ram_datos_lectura;
else
ram_datos_escritura <= RAM(conv_integer(direccion)) ;
end if;
else
ram_datos_escritura <= "ZZZZZZZZ";
end if;
end if;
end process;
end syn;
| mit | 8cd532db058322b605207490409a0cb1 | 0.58444 | 3.367412 | false | false | false | false |
timofonic/PHDL | misc/projects/spartan_pcie_board/fpga/lx45t_pinout/ipcore_dir/ddr3_controller/example_design/rtl/example_top.vhd | 1 | 72,742 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.9
-- \ \ Application : MIG
-- / / Filename : example_top.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:59 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : This is the design top level. which instantiates top wrapper,
-- test bench top and infrastructure modules.
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
entity example_top is
generic
(
C1_P0_MASK_SIZE : integer := 4;
C1_P0_DATA_PORT_SIZE : integer := 32;
C1_P1_MASK_SIZE : integer := 4;
C1_P1_DATA_PORT_SIZE : integer := 32;
C1_MEMCLK_PERIOD : integer := 2500;
-- Memory data transfer clock period.
C1_RST_ACT_LOW : integer := 0;
-- # = 1 for active low reset,
-- # = 0 for active high reset.
C1_INPUT_CLK_TYPE : string := "DIFFERENTIAL";
-- input clock type DIFFERENTIAL or SINGLE_ENDED.
C1_CALIB_SOFT_IP : string := "TRUE";
-- # = TRUE, Enables the soft calibration logic,
-- # = FALSE, Disables the soft calibration logic.
C1_SIMULATION : string := "FALSE";
-- # = TRUE, Simulating the design. Useful to reduce the simulation time,
-- # = FALSE, Implementing the design.
C1_HW_TESTING : string := "FALSE";
-- Determines the address space accessed by the traffic generator,
-- # = FALSE, Smaller address space,
-- # = TRUE, Large address space.
DEBUG_EN : integer := 0;
-- # = 1, Enable debug signals/controls,
-- = 0, Disable debug signals/controls.
C1_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
-- The order in which user address is provided to the memory controller,
-- ROW_BANK_COLUMN or BANK_ROW_COLUMN.
C1_NUM_DQ_PINS : integer := 16;
-- External memory data width.
C1_MEM_ADDR_WIDTH : integer := 14;
-- External memory address width.
C1_MEM_BANKADDR_WIDTH : integer := 3;
-- External memory bank address width.
C3_P0_MASK_SIZE : integer := 4;
C3_P0_DATA_PORT_SIZE : integer := 32;
C3_P1_MASK_SIZE : integer := 4;
C3_P1_DATA_PORT_SIZE : integer := 32;
C3_MEMCLK_PERIOD : integer := 2500;
-- Memory data transfer clock period.
C3_RST_ACT_LOW : integer := 0;
-- # = 1 for active low reset,
-- # = 0 for active high reset.
C3_INPUT_CLK_TYPE : string := "DIFFERENTIAL";
-- input clock type DIFFERENTIAL or SINGLE_ENDED.
C3_CALIB_SOFT_IP : string := "TRUE";
-- # = TRUE, Enables the soft calibration logic,
-- # = FALSE, Disables the soft calibration logic.
C3_SIMULATION : string := "FALSE";
-- # = TRUE, Simulating the design. Useful to reduce the simulation time,
-- # = FALSE, Implementing the design.
C3_HW_TESTING : string := "FALSE";
-- Determines the address space accessed by the traffic generator,
-- # = FALSE, Smaller address space,
-- # = TRUE, Large address space.
C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
-- The order in which user address is provided to the memory controller,
-- ROW_BANK_COLUMN or BANK_ROW_COLUMN.
C3_NUM_DQ_PINS : integer := 16;
-- External memory data width.
C3_MEM_ADDR_WIDTH : integer := 14;
-- External memory address width.
C3_MEM_BANKADDR_WIDTH : integer := 3
-- External memory bank address width.
);
port
(
calib_done : out std_logic;
error : out std_logic;
mcb1_dram_dq : inout std_logic_vector(C1_NUM_DQ_PINS-1 downto 0);
mcb1_dram_a : out std_logic_vector(C1_MEM_ADDR_WIDTH-1 downto 0);
mcb1_dram_ba : out std_logic_vector(C1_MEM_BANKADDR_WIDTH-1 downto 0);
mcb1_dram_ras_n : out std_logic;
mcb1_dram_cas_n : out std_logic;
mcb1_dram_we_n : out std_logic;
mcb1_dram_odt : out std_logic;
mcb1_dram_reset_n : out std_logic;
mcb1_dram_cke : out std_logic;
mcb1_dram_dm : out std_logic;
mcb1_dram_udqs : inout std_logic;
mcb1_dram_udqs_n : inout std_logic;
mcb1_rzq : inout std_logic;
mcb1_zio : inout std_logic;
mcb1_dram_udm : out std_logic;
c1_sys_clk_p : in std_logic;
c1_sys_clk_n : in std_logic;
c1_sys_rst_i : in std_logic;
mcb1_dram_dqs : inout std_logic;
mcb1_dram_dqs_n : inout std_logic;
mcb1_dram_ck : out std_logic;
mcb1_dram_ck_n : out std_logic;
mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_reset_n : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
mcb3_dram_udm : out std_logic;
c3_sys_clk_p : in std_logic;
c3_sys_clk_n : in std_logic;
c3_sys_rst_i : in std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic
);
end example_top;
architecture arc of example_top is
component memc1_infrastructure is
generic (
C_RST_ACT_LOW : integer;
C_INPUT_CLK_TYPE : string;
C_CLKOUT0_DIVIDE : integer;
C_CLKOUT1_DIVIDE : integer;
C_CLKOUT2_DIVIDE : integer;
C_CLKOUT3_DIVIDE : integer;
C_CLKFBOUT_MULT : integer;
C_DIVCLK_DIVIDE : integer;
C_INCLK_PERIOD : integer
);
port (
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_clk : in std_logic;
sys_rst_i : in std_logic;
clk0 : out std_logic;
rst0 : out std_logic;
async_rst : out std_logic;
sysclk_2x : out std_logic;
sysclk_2x_180 : out std_logic;
pll_ce_0 : out std_logic;
pll_ce_90 : out std_logic;
pll_lock : out std_logic;
mcb_drp_clk : out std_logic
);
end component;
component memc3_infrastructure is
generic (
C_RST_ACT_LOW : integer;
C_INPUT_CLK_TYPE : string;
C_CLKOUT0_DIVIDE : integer;
C_CLKOUT1_DIVIDE : integer;
C_CLKOUT2_DIVIDE : integer;
C_CLKOUT3_DIVIDE : integer;
C_CLKFBOUT_MULT : integer;
C_DIVCLK_DIVIDE : integer;
C_INCLK_PERIOD : integer
);
port (
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_clk : in std_logic;
sys_rst_i : in std_logic;
clk0 : out std_logic;
rst0 : out std_logic;
async_rst : out std_logic;
sysclk_2x : out std_logic;
sysclk_2x_180 : out std_logic;
pll_ce_0 : out std_logic;
pll_ce_90 : out std_logic;
pll_lock : out std_logic;
mcb_drp_clk : out std_logic
);
end component;
component memc1_wrapper is
generic (
C_MEMCLK_PERIOD : integer;
C_CALIB_SOFT_IP : string;
C_SIMULATION : string;
C_P0_MASK_SIZE : integer;
C_P0_DATA_PORT_SIZE : integer;
C_P1_MASK_SIZE : integer;
C_P1_DATA_PORT_SIZE : integer;
C_ARB_NUM_TIME_SLOTS : integer;
C_ARB_TIME_SLOT_0 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_1 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_2 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_3 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_4 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_5 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_6 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_7 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_8 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_9 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_10 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_11 : bit_vector(2 downto 0);
C_MEM_TRAS : integer;
C_MEM_TRCD : integer;
C_MEM_TREFI : integer;
C_MEM_TRFC : integer;
C_MEM_TRP : integer;
C_MEM_TWR : integer;
C_MEM_TRTP : integer;
C_MEM_TWTR : integer;
C_MEM_ADDR_ORDER : string;
C_NUM_DQ_PINS : integer;
C_MEM_TYPE : string;
C_MEM_DENSITY : string;
C_MEM_BURST_LEN : integer;
C_MEM_CAS_LATENCY : integer;
C_MEM_ADDR_WIDTH : integer;
C_MEM_BANKADDR_WIDTH : integer;
C_MEM_NUM_COL_BITS : integer;
C_MEM_DDR1_2_ODS : string;
C_MEM_DDR2_RTT : string;
C_MEM_DDR2_DIFF_DQS_EN : string;
C_MEM_DDR2_3_PA_SR : string;
C_MEM_DDR2_3_HIGH_TEMP_SR : string;
C_MEM_DDR3_CAS_LATENCY : integer;
C_MEM_DDR3_ODS : string;
C_MEM_DDR3_RTT : string;
C_MEM_DDR3_CAS_WR_LATENCY : integer;
C_MEM_DDR3_AUTO_SR : string;
C_MEM_MOBILE_PA_SR : string;
C_MEM_MDDR_ODS : string;
C_MC_CALIB_BYPASS : string;
C_MC_CALIBRATION_MODE : string;
C_MC_CALIBRATION_DELAY : string;
C_SKIP_IN_TERM_CAL : integer;
C_SKIP_DYNAMIC_CAL : integer;
C_LDQSP_TAP_DELAY_VAL : integer;
C_LDQSN_TAP_DELAY_VAL : integer;
C_UDQSP_TAP_DELAY_VAL : integer;
C_UDQSN_TAP_DELAY_VAL : integer;
C_DQ0_TAP_DELAY_VAL : integer;
C_DQ1_TAP_DELAY_VAL : integer;
C_DQ2_TAP_DELAY_VAL : integer;
C_DQ3_TAP_DELAY_VAL : integer;
C_DQ4_TAP_DELAY_VAL : integer;
C_DQ5_TAP_DELAY_VAL : integer;
C_DQ6_TAP_DELAY_VAL : integer;
C_DQ7_TAP_DELAY_VAL : integer;
C_DQ8_TAP_DELAY_VAL : integer;
C_DQ9_TAP_DELAY_VAL : integer;
C_DQ10_TAP_DELAY_VAL : integer;
C_DQ11_TAP_DELAY_VAL : integer;
C_DQ12_TAP_DELAY_VAL : integer;
C_DQ13_TAP_DELAY_VAL : integer;
C_DQ14_TAP_DELAY_VAL : integer;
C_DQ15_TAP_DELAY_VAL : integer
);
port (
mcb1_dram_dq : inout std_logic_vector((C_NUM_DQ_PINS-1) downto 0);
mcb1_dram_a : out std_logic_vector((C_MEM_ADDR_WIDTH-1) downto 0);
mcb1_dram_ba : out std_logic_vector((C_MEM_BANKADDR_WIDTH-1) downto 0);
mcb1_dram_ras_n : out std_logic;
mcb1_dram_cas_n : out std_logic;
mcb1_dram_we_n : out std_logic;
mcb1_dram_odt : out std_logic;
mcb1_dram_reset_n : out std_logic;
mcb1_dram_cke : out std_logic;
mcb1_dram_dm : out std_logic;
mcb1_dram_udqs : inout std_logic;
mcb1_dram_udqs_n : inout std_logic;
mcb1_rzq : inout std_logic;
mcb1_zio : inout std_logic;
mcb1_dram_udm : out std_logic;
calib_done : out std_logic;
async_rst : in std_logic;
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
mcb_drp_clk : in std_logic;
mcb1_dram_dqs : inout std_logic;
mcb1_dram_dqs_n : inout std_logic;
mcb1_dram_ck : out std_logic;
mcb1_dram_ck_n : out std_logic;
p0_cmd_clk : in std_logic;
p0_cmd_en : in std_logic;
p0_cmd_instr : in std_logic_vector(2 downto 0);
p0_cmd_bl : in std_logic_vector(5 downto 0);
p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
p0_cmd_empty : out std_logic;
p0_cmd_full : out std_logic;
p0_wr_clk : in std_logic;
p0_wr_en : in std_logic;
p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_wr_full : out std_logic;
p0_wr_empty : out std_logic;
p0_wr_count : out std_logic_vector(6 downto 0);
p0_wr_underrun : out std_logic;
p0_wr_error : out std_logic;
p0_rd_clk : in std_logic;
p0_rd_en : in std_logic;
p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_rd_full : out std_logic;
p0_rd_empty : out std_logic;
p0_rd_count : out std_logic_vector(6 downto 0);
p0_rd_overflow : out std_logic;
p0_rd_error : out std_logic;
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end component;
component memc3_wrapper is
generic (
C_MEMCLK_PERIOD : integer;
C_CALIB_SOFT_IP : string;
C_SIMULATION : string;
C_P0_MASK_SIZE : integer;
C_P0_DATA_PORT_SIZE : integer;
C_P1_MASK_SIZE : integer;
C_P1_DATA_PORT_SIZE : integer;
C_ARB_NUM_TIME_SLOTS : integer;
C_ARB_TIME_SLOT_0 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_1 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_2 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_3 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_4 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_5 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_6 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_7 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_8 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_9 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_10 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_11 : bit_vector(2 downto 0);
C_MEM_TRAS : integer;
C_MEM_TRCD : integer;
C_MEM_TREFI : integer;
C_MEM_TRFC : integer;
C_MEM_TRP : integer;
C_MEM_TWR : integer;
C_MEM_TRTP : integer;
C_MEM_TWTR : integer;
C_MEM_ADDR_ORDER : string;
C_NUM_DQ_PINS : integer;
C_MEM_TYPE : string;
C_MEM_DENSITY : string;
C_MEM_BURST_LEN : integer;
C_MEM_CAS_LATENCY : integer;
C_MEM_ADDR_WIDTH : integer;
C_MEM_BANKADDR_WIDTH : integer;
C_MEM_NUM_COL_BITS : integer;
C_MEM_DDR1_2_ODS : string;
C_MEM_DDR2_RTT : string;
C_MEM_DDR2_DIFF_DQS_EN : string;
C_MEM_DDR2_3_PA_SR : string;
C_MEM_DDR2_3_HIGH_TEMP_SR : string;
C_MEM_DDR3_CAS_LATENCY : integer;
C_MEM_DDR3_ODS : string;
C_MEM_DDR3_RTT : string;
C_MEM_DDR3_CAS_WR_LATENCY : integer;
C_MEM_DDR3_AUTO_SR : string;
C_MEM_MOBILE_PA_SR : string;
C_MEM_MDDR_ODS : string;
C_MC_CALIB_BYPASS : string;
C_MC_CALIBRATION_MODE : string;
C_MC_CALIBRATION_DELAY : string;
C_SKIP_IN_TERM_CAL : integer;
C_SKIP_DYNAMIC_CAL : integer;
C_LDQSP_TAP_DELAY_VAL : integer;
C_LDQSN_TAP_DELAY_VAL : integer;
C_UDQSP_TAP_DELAY_VAL : integer;
C_UDQSN_TAP_DELAY_VAL : integer;
C_DQ0_TAP_DELAY_VAL : integer;
C_DQ1_TAP_DELAY_VAL : integer;
C_DQ2_TAP_DELAY_VAL : integer;
C_DQ3_TAP_DELAY_VAL : integer;
C_DQ4_TAP_DELAY_VAL : integer;
C_DQ5_TAP_DELAY_VAL : integer;
C_DQ6_TAP_DELAY_VAL : integer;
C_DQ7_TAP_DELAY_VAL : integer;
C_DQ8_TAP_DELAY_VAL : integer;
C_DQ9_TAP_DELAY_VAL : integer;
C_DQ10_TAP_DELAY_VAL : integer;
C_DQ11_TAP_DELAY_VAL : integer;
C_DQ12_TAP_DELAY_VAL : integer;
C_DQ13_TAP_DELAY_VAL : integer;
C_DQ14_TAP_DELAY_VAL : integer;
C_DQ15_TAP_DELAY_VAL : integer
);
port (
mcb3_dram_dq : inout std_logic_vector((C_NUM_DQ_PINS-1) downto 0);
mcb3_dram_a : out std_logic_vector((C_MEM_ADDR_WIDTH-1) downto 0);
mcb3_dram_ba : out std_logic_vector((C_MEM_BANKADDR_WIDTH-1) downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_reset_n : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
mcb3_dram_udm : out std_logic;
calib_done : out std_logic;
async_rst : in std_logic;
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
mcb_drp_clk : in std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
p0_cmd_clk : in std_logic;
p0_cmd_en : in std_logic;
p0_cmd_instr : in std_logic_vector(2 downto 0);
p0_cmd_bl : in std_logic_vector(5 downto 0);
p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
p0_cmd_empty : out std_logic;
p0_cmd_full : out std_logic;
p0_wr_clk : in std_logic;
p0_wr_en : in std_logic;
p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_wr_full : out std_logic;
p0_wr_empty : out std_logic;
p0_wr_count : out std_logic_vector(6 downto 0);
p0_wr_underrun : out std_logic;
p0_wr_error : out std_logic;
p0_rd_clk : in std_logic;
p0_rd_en : in std_logic;
p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_rd_full : out std_logic;
p0_rd_empty : out std_logic;
p0_rd_count : out std_logic_vector(6 downto 0);
p0_rd_overflow : out std_logic;
p0_rd_error : out std_logic;
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end component;
component memc1_tb_top is
generic (
C_SIMULATION : string;
C_P0_MASK_SIZE : integer;
C_P0_DATA_PORT_SIZE : integer;
C_P1_MASK_SIZE : integer;
C_P1_DATA_PORT_SIZE : integer;
C_NUM_DQ_PINS : integer;
C_MEM_BURST_LEN : integer;
C_MEM_NUM_COL_BITS : integer;
C_SMALL_DEVICE : string;
C_p0_BEGIN_ADDRESS : std_logic_vector(31 downto 0);
C_p0_DATA_MODE : std_logic_vector(3 downto 0);
C_p0_END_ADDRESS : std_logic_vector(31 downto 0);
C_p0_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0);
C_p0_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0)
);
port (
error : out std_logic;
calib_done : in std_logic;
clk0 : in std_logic;
rst0 : in std_logic;
cmp_error : out std_logic;
cmp_data_valid : out std_logic;
vio_modify_enable : in std_logic;
error_status : out std_logic_vector(127 downto 0);
vio_data_mode_value : in std_logic_vector(2 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
cmp_data : out std_logic_vector(31 downto 0);
p0_mcb_cmd_en_o : out std_logic;
p0_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p0_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p0_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p0_mcb_cmd_full_i : in std_logic;
p0_mcb_wr_en_o : out std_logic;
p0_mcb_wr_mask_o : out std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
p0_mcb_wr_data_o : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_mcb_wr_full_i : in std_logic;
p0_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
p0_mcb_rd_en_o : out std_logic;
p0_mcb_rd_data_i : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_mcb_rd_empty_i : in std_logic;
p0_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0)
);
end component;
component memc3_tb_top is
generic (
C_SIMULATION : string;
C_P0_MASK_SIZE : integer;
C_P0_DATA_PORT_SIZE : integer;
C_P1_MASK_SIZE : integer;
C_P1_DATA_PORT_SIZE : integer;
C_NUM_DQ_PINS : integer;
C_MEM_BURST_LEN : integer;
C_MEM_NUM_COL_BITS : integer;
C_SMALL_DEVICE : string;
C_p0_BEGIN_ADDRESS : std_logic_vector(31 downto 0);
C_p0_DATA_MODE : std_logic_vector(3 downto 0);
C_p0_END_ADDRESS : std_logic_vector(31 downto 0);
C_p0_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0);
C_p0_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0)
);
port (
error : out std_logic;
calib_done : in std_logic;
clk0 : in std_logic;
rst0 : in std_logic;
cmp_error : out std_logic;
cmp_data_valid : out std_logic;
vio_modify_enable : in std_logic;
error_status : out std_logic_vector(127 downto 0);
vio_data_mode_value : in std_logic_vector(2 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
cmp_data : out std_logic_vector(31 downto 0);
p0_mcb_cmd_en_o : out std_logic;
p0_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p0_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p0_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p0_mcb_cmd_full_i : in std_logic;
p0_mcb_wr_en_o : out std_logic;
p0_mcb_wr_mask_o : out std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
p0_mcb_wr_data_o : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_mcb_wr_full_i : in std_logic;
p0_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
p0_mcb_rd_en_o : out std_logic;
p0_mcb_rd_data_i : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_mcb_rd_empty_i : in std_logic;
p0_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0)
);
end component;
function c1_sim_hw (val1:std_logic_vector( 31 downto 0); val2: std_logic_vector( 31 downto 0) ) return std_logic_vector is
begin
if (C1_HW_TESTING = "FALSE") then
return val1;
else
return val2;
end if;
end function;
function c3_sim_hw (val1:std_logic_vector( 31 downto 0); val2: std_logic_vector( 31 downto 0) ) return std_logic_vector is
begin
if (C3_HW_TESTING = "FALSE") then
return val1;
else
return val2;
end if;
end function;
constant C1_CLKOUT0_DIVIDE : integer := 1;
constant C1_CLKOUT1_DIVIDE : integer := 1;
constant C1_CLKOUT2_DIVIDE : integer := 16;
constant C1_CLKOUT3_DIVIDE : integer := 8;
constant C1_CLKFBOUT_MULT : integer := 2;
constant C1_DIVCLK_DIVIDE : integer := 1;
constant C1_INCLK_PERIOD : integer := ((C1_MEMCLK_PERIOD * C1_CLKFBOUT_MULT) / (C1_DIVCLK_DIVIDE * C1_CLKOUT0_DIVIDE * 2));
constant C1_ARB_NUM_TIME_SLOTS : integer := 12;
constant C1_ARB_TIME_SLOT_0 : bit_vector(2 downto 0) := o"0";
constant C1_ARB_TIME_SLOT_1 : bit_vector(2 downto 0) := o"0";
constant C1_ARB_TIME_SLOT_2 : bit_vector(2 downto 0) := o"0";
constant C1_ARB_TIME_SLOT_3 : bit_vector(2 downto 0) := o"0";
constant C1_ARB_TIME_SLOT_4 : bit_vector(2 downto 0) := o"0";
constant C1_ARB_TIME_SLOT_5 : bit_vector(2 downto 0) := o"0";
constant C1_ARB_TIME_SLOT_6 : bit_vector(2 downto 0) := o"0";
constant C1_ARB_TIME_SLOT_7 : bit_vector(2 downto 0) := o"0";
constant C1_ARB_TIME_SLOT_8 : bit_vector(2 downto 0) := o"0";
constant C1_ARB_TIME_SLOT_9 : bit_vector(2 downto 0) := o"0";
constant C1_ARB_TIME_SLOT_10 : bit_vector(2 downto 0) := o"0";
constant C1_ARB_TIME_SLOT_11 : bit_vector(2 downto 0) := o"0";
constant C1_MEM_TRAS : integer := 36000;
constant C1_MEM_TRCD : integer := 13500;
constant C1_MEM_TREFI : integer := 7800000;
constant C1_MEM_TRFC : integer := 160000;
constant C1_MEM_TRP : integer := 13500;
constant C1_MEM_TWR : integer := 15000;
constant C1_MEM_TRTP : integer := 7500;
constant C1_MEM_TWTR : integer := 7500;
constant C1_MEM_TYPE : string := "DDR3";
constant C1_MEM_DENSITY : string := "2Gb";
constant C1_MEM_BURST_LEN : integer := 8;
constant C1_MEM_CAS_LATENCY : integer := 6;
constant C1_MEM_NUM_COL_BITS : integer := 10;
constant C1_MEM_DDR1_2_ODS : string := "FULL";
constant C1_MEM_DDR2_RTT : string := "50OHMS";
constant C1_MEM_DDR2_DIFF_DQS_EN : string := "YES";
constant C1_MEM_DDR2_3_PA_SR : string := "FULL";
constant C1_MEM_DDR2_3_HIGH_TEMP_SR : string := "NORMAL";
constant C1_MEM_DDR3_CAS_LATENCY : integer := 6;
constant C1_MEM_DDR3_ODS : string := "DIV6";
constant C1_MEM_DDR3_RTT : string := "DIV4";
constant C1_MEM_DDR3_CAS_WR_LATENCY : integer := 5;
constant C1_MEM_DDR3_AUTO_SR : string := "ENABLED";
constant C1_MEM_MOBILE_PA_SR : string := "FULL";
constant C1_MEM_MDDR_ODS : string := "FULL";
constant C1_MC_CALIB_BYPASS : string := "NO";
constant C1_MC_CALIBRATION_MODE : string := "CALIBRATION";
constant C1_MC_CALIBRATION_DELAY : string := "HALF";
constant C1_SKIP_IN_TERM_CAL : integer := 0;
constant C1_SKIP_DYNAMIC_CAL : integer := 0;
constant C1_LDQSP_TAP_DELAY_VAL : integer := 0;
constant C1_LDQSN_TAP_DELAY_VAL : integer := 0;
constant C1_UDQSP_TAP_DELAY_VAL : integer := 0;
constant C1_UDQSN_TAP_DELAY_VAL : integer := 0;
constant C1_DQ0_TAP_DELAY_VAL : integer := 0;
constant C1_DQ1_TAP_DELAY_VAL : integer := 0;
constant C1_DQ2_TAP_DELAY_VAL : integer := 0;
constant C1_DQ3_TAP_DELAY_VAL : integer := 0;
constant C1_DQ4_TAP_DELAY_VAL : integer := 0;
constant C1_DQ5_TAP_DELAY_VAL : integer := 0;
constant C1_DQ6_TAP_DELAY_VAL : integer := 0;
constant C1_DQ7_TAP_DELAY_VAL : integer := 0;
constant C1_DQ8_TAP_DELAY_VAL : integer := 0;
constant C1_DQ9_TAP_DELAY_VAL : integer := 0;
constant C1_DQ10_TAP_DELAY_VAL : integer := 0;
constant C1_DQ11_TAP_DELAY_VAL : integer := 0;
constant C1_DQ12_TAP_DELAY_VAL : integer := 0;
constant C1_DQ13_TAP_DELAY_VAL : integer := 0;
constant C1_DQ14_TAP_DELAY_VAL : integer := 0;
constant C1_DQ15_TAP_DELAY_VAL : integer := 0;
constant C1_SMALL_DEVICE : string := "FALSE"; -- The parameter is set to TRUE for all packages of xc6slx9 device
-- as most of them cannot fit the complete example design when the
-- Chip scope modules are enabled
constant C3_CLKOUT0_DIVIDE : integer := 1;
constant C3_CLKOUT1_DIVIDE : integer := 1;
constant C3_CLKOUT2_DIVIDE : integer := 16;
constant C3_CLKOUT3_DIVIDE : integer := 8;
constant C3_CLKFBOUT_MULT : integer := 2;
constant C3_DIVCLK_DIVIDE : integer := 1;
constant C3_INCLK_PERIOD : integer := ((C3_MEMCLK_PERIOD * C3_CLKFBOUT_MULT) / (C3_DIVCLK_DIVIDE * C3_CLKOUT0_DIVIDE * 2));
constant C3_ARB_NUM_TIME_SLOTS : integer := 12;
constant C3_ARB_TIME_SLOT_0 : bit_vector(2 downto 0) := o"0";
constant C3_ARB_TIME_SLOT_1 : bit_vector(2 downto 0) := o"0";
constant C3_ARB_TIME_SLOT_2 : bit_vector(2 downto 0) := o"0";
constant C3_ARB_TIME_SLOT_3 : bit_vector(2 downto 0) := o"0";
constant C3_ARB_TIME_SLOT_4 : bit_vector(2 downto 0) := o"0";
constant C3_ARB_TIME_SLOT_5 : bit_vector(2 downto 0) := o"0";
constant C3_ARB_TIME_SLOT_6 : bit_vector(2 downto 0) := o"0";
constant C3_ARB_TIME_SLOT_7 : bit_vector(2 downto 0) := o"0";
constant C3_ARB_TIME_SLOT_8 : bit_vector(2 downto 0) := o"0";
constant C3_ARB_TIME_SLOT_9 : bit_vector(2 downto 0) := o"0";
constant C3_ARB_TIME_SLOT_10 : bit_vector(2 downto 0) := o"0";
constant C3_ARB_TIME_SLOT_11 : bit_vector(2 downto 0) := o"0";
constant C3_MEM_TRAS : integer := 36000;
constant C3_MEM_TRCD : integer := 13500;
constant C3_MEM_TREFI : integer := 7800000;
constant C3_MEM_TRFC : integer := 160000;
constant C3_MEM_TRP : integer := 13500;
constant C3_MEM_TWR : integer := 15000;
constant C3_MEM_TRTP : integer := 7500;
constant C3_MEM_TWTR : integer := 7500;
constant C3_MEM_TYPE : string := "DDR3";
constant C3_MEM_DENSITY : string := "2Gb";
constant C3_MEM_BURST_LEN : integer := 8;
constant C3_MEM_CAS_LATENCY : integer := 6;
constant C3_MEM_NUM_COL_BITS : integer := 10;
constant C3_MEM_DDR1_2_ODS : string := "FULL";
constant C3_MEM_DDR2_RTT : string := "50OHMS";
constant C3_MEM_DDR2_DIFF_DQS_EN : string := "YES";
constant C3_MEM_DDR2_3_PA_SR : string := "FULL";
constant C3_MEM_DDR2_3_HIGH_TEMP_SR : string := "NORMAL";
constant C3_MEM_DDR3_CAS_LATENCY : integer := 6;
constant C3_MEM_DDR3_ODS : string := "DIV6";
constant C3_MEM_DDR3_RTT : string := "DIV4";
constant C3_MEM_DDR3_CAS_WR_LATENCY : integer := 5;
constant C3_MEM_DDR3_AUTO_SR : string := "ENABLED";
constant C3_MEM_MOBILE_PA_SR : string := "FULL";
constant C3_MEM_MDDR_ODS : string := "FULL";
constant C3_MC_CALIB_BYPASS : string := "NO";
constant C3_MC_CALIBRATION_MODE : string := "CALIBRATION";
constant C3_MC_CALIBRATION_DELAY : string := "HALF";
constant C3_SKIP_IN_TERM_CAL : integer := 0;
constant C3_SKIP_DYNAMIC_CAL : integer := 0;
constant C3_LDQSP_TAP_DELAY_VAL : integer := 0;
constant C3_LDQSN_TAP_DELAY_VAL : integer := 0;
constant C3_UDQSP_TAP_DELAY_VAL : integer := 0;
constant C3_UDQSN_TAP_DELAY_VAL : integer := 0;
constant C3_DQ0_TAP_DELAY_VAL : integer := 0;
constant C3_DQ1_TAP_DELAY_VAL : integer := 0;
constant C3_DQ2_TAP_DELAY_VAL : integer := 0;
constant C3_DQ3_TAP_DELAY_VAL : integer := 0;
constant C3_DQ4_TAP_DELAY_VAL : integer := 0;
constant C3_DQ5_TAP_DELAY_VAL : integer := 0;
constant C3_DQ6_TAP_DELAY_VAL : integer := 0;
constant C3_DQ7_TAP_DELAY_VAL : integer := 0;
constant C3_DQ8_TAP_DELAY_VAL : integer := 0;
constant C3_DQ9_TAP_DELAY_VAL : integer := 0;
constant C3_DQ10_TAP_DELAY_VAL : integer := 0;
constant C3_DQ11_TAP_DELAY_VAL : integer := 0;
constant C3_DQ12_TAP_DELAY_VAL : integer := 0;
constant C3_DQ13_TAP_DELAY_VAL : integer := 0;
constant C3_DQ14_TAP_DELAY_VAL : integer := 0;
constant C3_DQ15_TAP_DELAY_VAL : integer := 0;
constant C3_SMALL_DEVICE : string := "FALSE"; -- The parameter is set to TRUE for all packages of xc6slx9 device
-- as most of them cannot fit the complete example design when the
-- Chip scope modules are enabled
constant C1_p0_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := c1_sim_hw (x"00000100", x"01000000");
constant C1_p0_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant C1_p0_END_ADDRESS : std_logic_vector(31 downto 0) := c1_sim_hw (x"000002ff", x"02ffffff");
constant C1_p0_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := c1_sim_hw (x"fffffc00", x"fc000000");
constant C1_p0_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := c1_sim_hw (x"00000100", x"01000000");
constant C3_p0_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000100", x"01000000");
constant C3_p0_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant C3_p0_END_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"000002ff", x"02ffffff");
constant C3_p0_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"fffffc00", x"fc000000");
constant C3_p0_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000100", x"01000000");
signal c1_sys_clk : std_logic;
signal c1_error : std_logic;
signal c1_calib_done : std_logic;
signal c1_clk0 : std_logic;
signal c1_rst0 : std_logic;
signal c1_async_rst : std_logic;
signal c1_sysclk_2x : std_logic;
signal c1_sysclk_2x_180 : std_logic;
signal c1_pll_ce_0 : std_logic;
signal c1_pll_ce_90 : std_logic;
signal c1_pll_lock : std_logic;
signal c1_mcb_drp_clk : std_logic;
signal c1_cmp_error : std_logic;
signal c1_cmp_data_valid : std_logic;
signal c1_vio_modify_enable : std_logic;
signal c1_error_status : std_logic_vector(127 downto 0);
signal c1_vio_data_mode_value : std_logic_vector(2 downto 0);
signal c1_vio_addr_mode_value : std_logic_vector(2 downto 0);
signal c1_cmp_data : std_logic_vector(31 downto 0);
signal c3_sys_clk : std_logic;
signal c3_error : std_logic;
signal c3_calib_done : std_logic;
signal c3_clk0 : std_logic;
signal c3_rst0 : std_logic;
signal c3_async_rst : std_logic;
signal c3_sysclk_2x : std_logic;
signal c3_sysclk_2x_180 : std_logic;
signal c3_pll_ce_0 : std_logic;
signal c3_pll_ce_90 : std_logic;
signal c3_pll_lock : std_logic;
signal c3_mcb_drp_clk : std_logic;
signal c3_cmp_error : std_logic;
signal c3_cmp_data_valid : std_logic;
signal c3_vio_modify_enable : std_logic;
signal c3_error_status : std_logic_vector(127 downto 0);
signal c3_vio_data_mode_value : std_logic_vector(2 downto 0);
signal c3_vio_addr_mode_value : std_logic_vector(2 downto 0);
signal c3_cmp_data : std_logic_vector(31 downto 0);
signal c1_p0_cmd_en : std_logic;
signal c1_p0_cmd_instr : std_logic_vector(2 downto 0);
signal c1_p0_cmd_bl : std_logic_vector(5 downto 0);
signal c1_p0_cmd_byte_addr : std_logic_vector(29 downto 0);
signal c1_p0_cmd_empty : std_logic;
signal c1_p0_cmd_full : std_logic;
signal c1_p0_wr_en : std_logic;
signal c1_p0_wr_mask : std_logic_vector(C1_P0_MASK_SIZE - 1 downto 0);
signal c1_p0_wr_data : std_logic_vector(C1_P0_DATA_PORT_SIZE - 1 downto 0);
signal c1_p0_wr_full : std_logic;
signal c1_p0_wr_empty : std_logic;
signal c1_p0_wr_count : std_logic_vector(6 downto 0);
signal c1_p0_wr_underrun : std_logic;
signal c1_p0_wr_error : std_logic;
signal c1_p0_rd_en : std_logic;
signal c1_p0_rd_data : std_logic_vector(C1_P0_DATA_PORT_SIZE - 1 downto 0);
signal c1_p0_rd_full : std_logic;
signal c1_p0_rd_empty : std_logic;
signal c1_p0_rd_count : std_logic_vector(6 downto 0);
signal c1_p0_rd_overflow : std_logic;
signal c1_p0_rd_error : std_logic;
signal c1_selfrefresh_enter : std_logic;
signal c1_selfrefresh_mode : std_logic;
signal c3_p0_cmd_en : std_logic;
signal c3_p0_cmd_instr : std_logic_vector(2 downto 0);
signal c3_p0_cmd_bl : std_logic_vector(5 downto 0);
signal c3_p0_cmd_byte_addr : std_logic_vector(29 downto 0);
signal c3_p0_cmd_empty : std_logic;
signal c3_p0_cmd_full : std_logic;
signal c3_p0_wr_en : std_logic;
signal c3_p0_wr_mask : std_logic_vector(C3_P0_MASK_SIZE - 1 downto 0);
signal c3_p0_wr_data : std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
signal c3_p0_wr_full : std_logic;
signal c3_p0_wr_empty : std_logic;
signal c3_p0_wr_count : std_logic_vector(6 downto 0);
signal c3_p0_wr_underrun : std_logic;
signal c3_p0_wr_error : std_logic;
signal c3_p0_rd_en : std_logic;
signal c3_p0_rd_data : std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
signal c3_p0_rd_full : std_logic;
signal c3_p0_rd_empty : std_logic;
signal c3_p0_rd_count : std_logic_vector(6 downto 0);
signal c3_p0_rd_overflow : std_logic;
signal c3_p0_rd_error : std_logic;
signal c3_selfrefresh_enter : std_logic;
signal c3_selfrefresh_mode : std_logic;
begin
error <= c1_error or c3_error;
calib_done <= c1_calib_done and c3_calib_done;
c1_sys_clk <= '0';
c3_sys_clk <= '0';
c1_selfrefresh_enter <= '0';
c3_selfrefresh_enter <= '0';
memc1_infrastructure_inst : memc1_infrastructure
generic map
(
C_RST_ACT_LOW => C1_RST_ACT_LOW,
C_INPUT_CLK_TYPE => C1_INPUT_CLK_TYPE,
C_CLKOUT0_DIVIDE => C1_CLKOUT0_DIVIDE,
C_CLKOUT1_DIVIDE => C1_CLKOUT1_DIVIDE,
C_CLKOUT2_DIVIDE => C1_CLKOUT2_DIVIDE,
C_CLKOUT3_DIVIDE => C1_CLKOUT3_DIVIDE,
C_CLKFBOUT_MULT => C1_CLKFBOUT_MULT,
C_DIVCLK_DIVIDE => C1_DIVCLK_DIVIDE,
C_INCLK_PERIOD => C1_INCLK_PERIOD
)
port map
(
sys_clk_p => c1_sys_clk_p,
sys_clk_n => c1_sys_clk_n,
sys_clk => c1_sys_clk,
sys_rst_i => c1_sys_rst_i,
clk0 => c1_clk0,
rst0 => c1_rst0,
async_rst => c1_async_rst,
sysclk_2x => c1_sysclk_2x,
sysclk_2x_180 => c1_sysclk_2x_180,
pll_ce_0 => c1_pll_ce_0,
pll_ce_90 => c1_pll_ce_90,
pll_lock => c1_pll_lock,
mcb_drp_clk => c1_mcb_drp_clk
);
memc3_infrastructure_inst : memc3_infrastructure
generic map
(
C_RST_ACT_LOW => C3_RST_ACT_LOW,
C_INPUT_CLK_TYPE => C3_INPUT_CLK_TYPE,
C_CLKOUT0_DIVIDE => C3_CLKOUT0_DIVIDE,
C_CLKOUT1_DIVIDE => C3_CLKOUT1_DIVIDE,
C_CLKOUT2_DIVIDE => C3_CLKOUT2_DIVIDE,
C_CLKOUT3_DIVIDE => C3_CLKOUT3_DIVIDE,
C_CLKFBOUT_MULT => C3_CLKFBOUT_MULT,
C_DIVCLK_DIVIDE => C3_DIVCLK_DIVIDE,
C_INCLK_PERIOD => C3_INCLK_PERIOD
)
port map
(
sys_clk_p => c3_sys_clk_p,
sys_clk_n => c3_sys_clk_n,
sys_clk => c3_sys_clk,
sys_rst_i => c3_sys_rst_i,
clk0 => c3_clk0,
rst0 => c3_rst0,
async_rst => c3_async_rst,
sysclk_2x => c3_sysclk_2x,
sysclk_2x_180 => c3_sysclk_2x_180,
pll_ce_0 => c3_pll_ce_0,
pll_ce_90 => c3_pll_ce_90,
pll_lock => c3_pll_lock,
mcb_drp_clk => c3_mcb_drp_clk
);
-- wrapper instantiation
memc1_wrapper_inst : memc1_wrapper
generic map
(
C_MEMCLK_PERIOD => C1_MEMCLK_PERIOD,
C_CALIB_SOFT_IP => C1_CALIB_SOFT_IP,
C_SIMULATION => C1_SIMULATION,
C_P0_MASK_SIZE => C1_P0_MASK_SIZE,
C_P0_DATA_PORT_SIZE => C1_P0_DATA_PORT_SIZE,
C_P1_MASK_SIZE => C1_P1_MASK_SIZE,
C_P1_DATA_PORT_SIZE => C1_P1_DATA_PORT_SIZE,
C_ARB_NUM_TIME_SLOTS => C1_ARB_NUM_TIME_SLOTS,
C_ARB_TIME_SLOT_0 => C1_ARB_TIME_SLOT_0,
C_ARB_TIME_SLOT_1 => C1_ARB_TIME_SLOT_1,
C_ARB_TIME_SLOT_2 => C1_ARB_TIME_SLOT_2,
C_ARB_TIME_SLOT_3 => C1_ARB_TIME_SLOT_3,
C_ARB_TIME_SLOT_4 => C1_ARB_TIME_SLOT_4,
C_ARB_TIME_SLOT_5 => C1_ARB_TIME_SLOT_5,
C_ARB_TIME_SLOT_6 => C1_ARB_TIME_SLOT_6,
C_ARB_TIME_SLOT_7 => C1_ARB_TIME_SLOT_7,
C_ARB_TIME_SLOT_8 => C1_ARB_TIME_SLOT_8,
C_ARB_TIME_SLOT_9 => C1_ARB_TIME_SLOT_9,
C_ARB_TIME_SLOT_10 => C1_ARB_TIME_SLOT_10,
C_ARB_TIME_SLOT_11 => C1_ARB_TIME_SLOT_11,
C_MEM_TRAS => C1_MEM_TRAS,
C_MEM_TRCD => C1_MEM_TRCD,
C_MEM_TREFI => C1_MEM_TREFI,
C_MEM_TRFC => C1_MEM_TRFC,
C_MEM_TRP => C1_MEM_TRP,
C_MEM_TWR => C1_MEM_TWR,
C_MEM_TRTP => C1_MEM_TRTP,
C_MEM_TWTR => C1_MEM_TWTR,
C_MEM_ADDR_ORDER => C1_MEM_ADDR_ORDER,
C_NUM_DQ_PINS => C1_NUM_DQ_PINS,
C_MEM_TYPE => C1_MEM_TYPE,
C_MEM_DENSITY => C1_MEM_DENSITY,
C_MEM_BURST_LEN => C1_MEM_BURST_LEN,
C_MEM_CAS_LATENCY => C1_MEM_CAS_LATENCY,
C_MEM_ADDR_WIDTH => C1_MEM_ADDR_WIDTH,
C_MEM_BANKADDR_WIDTH => C1_MEM_BANKADDR_WIDTH,
C_MEM_NUM_COL_BITS => C1_MEM_NUM_COL_BITS,
C_MEM_DDR1_2_ODS => C1_MEM_DDR1_2_ODS,
C_MEM_DDR2_RTT => C1_MEM_DDR2_RTT,
C_MEM_DDR2_DIFF_DQS_EN => C1_MEM_DDR2_DIFF_DQS_EN,
C_MEM_DDR2_3_PA_SR => C1_MEM_DDR2_3_PA_SR,
C_MEM_DDR2_3_HIGH_TEMP_SR => C1_MEM_DDR2_3_HIGH_TEMP_SR,
C_MEM_DDR3_CAS_LATENCY => C1_MEM_DDR3_CAS_LATENCY,
C_MEM_DDR3_ODS => C1_MEM_DDR3_ODS,
C_MEM_DDR3_RTT => C1_MEM_DDR3_RTT,
C_MEM_DDR3_CAS_WR_LATENCY => C1_MEM_DDR3_CAS_WR_LATENCY,
C_MEM_DDR3_AUTO_SR => C1_MEM_DDR3_AUTO_SR,
C_MEM_MOBILE_PA_SR => C1_MEM_MOBILE_PA_SR,
C_MEM_MDDR_ODS => C1_MEM_MDDR_ODS,
C_MC_CALIB_BYPASS => C1_MC_CALIB_BYPASS,
C_MC_CALIBRATION_MODE => C1_MC_CALIBRATION_MODE,
C_MC_CALIBRATION_DELAY => C1_MC_CALIBRATION_DELAY,
C_SKIP_IN_TERM_CAL => C1_SKIP_IN_TERM_CAL,
C_SKIP_DYNAMIC_CAL => C1_SKIP_DYNAMIC_CAL,
C_LDQSP_TAP_DELAY_VAL => C1_LDQSP_TAP_DELAY_VAL,
C_LDQSN_TAP_DELAY_VAL => C1_LDQSN_TAP_DELAY_VAL,
C_UDQSP_TAP_DELAY_VAL => C1_UDQSP_TAP_DELAY_VAL,
C_UDQSN_TAP_DELAY_VAL => C1_UDQSN_TAP_DELAY_VAL,
C_DQ0_TAP_DELAY_VAL => C1_DQ0_TAP_DELAY_VAL,
C_DQ1_TAP_DELAY_VAL => C1_DQ1_TAP_DELAY_VAL,
C_DQ2_TAP_DELAY_VAL => C1_DQ2_TAP_DELAY_VAL,
C_DQ3_TAP_DELAY_VAL => C1_DQ3_TAP_DELAY_VAL,
C_DQ4_TAP_DELAY_VAL => C1_DQ4_TAP_DELAY_VAL,
C_DQ5_TAP_DELAY_VAL => C1_DQ5_TAP_DELAY_VAL,
C_DQ6_TAP_DELAY_VAL => C1_DQ6_TAP_DELAY_VAL,
C_DQ7_TAP_DELAY_VAL => C1_DQ7_TAP_DELAY_VAL,
C_DQ8_TAP_DELAY_VAL => C1_DQ8_TAP_DELAY_VAL,
C_DQ9_TAP_DELAY_VAL => C1_DQ9_TAP_DELAY_VAL,
C_DQ10_TAP_DELAY_VAL => C1_DQ10_TAP_DELAY_VAL,
C_DQ11_TAP_DELAY_VAL => C1_DQ11_TAP_DELAY_VAL,
C_DQ12_TAP_DELAY_VAL => C1_DQ12_TAP_DELAY_VAL,
C_DQ13_TAP_DELAY_VAL => C1_DQ13_TAP_DELAY_VAL,
C_DQ14_TAP_DELAY_VAL => C1_DQ14_TAP_DELAY_VAL,
C_DQ15_TAP_DELAY_VAL => C1_DQ15_TAP_DELAY_VAL
)
port map
(
mcb1_dram_dq => mcb1_dram_dq,
mcb1_dram_a => mcb1_dram_a,
mcb1_dram_ba => mcb1_dram_ba,
mcb1_dram_ras_n => mcb1_dram_ras_n,
mcb1_dram_cas_n => mcb1_dram_cas_n,
mcb1_dram_we_n => mcb1_dram_we_n,
mcb1_dram_odt => mcb1_dram_odt,
mcb1_dram_reset_n => mcb1_dram_reset_n,
mcb1_dram_cke => mcb1_dram_cke,
mcb1_dram_dm => mcb1_dram_dm,
mcb1_dram_udqs => mcb1_dram_udqs,
mcb1_dram_udqs_n => mcb1_dram_udqs_n,
mcb1_rzq => mcb1_rzq,
mcb1_zio => mcb1_zio,
mcb1_dram_udm => mcb1_dram_udm,
calib_done => c1_calib_done,
async_rst => c1_async_rst,
sysclk_2x => c1_sysclk_2x,
sysclk_2x_180 => c1_sysclk_2x_180,
pll_ce_0 => c1_pll_ce_0,
pll_ce_90 => c1_pll_ce_90,
pll_lock => c1_pll_lock,
mcb_drp_clk => c1_mcb_drp_clk,
mcb1_dram_dqs => mcb1_dram_dqs,
mcb1_dram_dqs_n => mcb1_dram_dqs_n,
mcb1_dram_ck => mcb1_dram_ck,
mcb1_dram_ck_n => mcb1_dram_ck_n,
p0_cmd_clk => c1_clk0,
p0_cmd_en => c1_p0_cmd_en,
p0_cmd_instr => c1_p0_cmd_instr,
p0_cmd_bl => c1_p0_cmd_bl,
p0_cmd_byte_addr => c1_p0_cmd_byte_addr,
p0_cmd_empty => c1_p0_cmd_empty,
p0_cmd_full => c1_p0_cmd_full,
p0_wr_clk => c1_clk0,
p0_wr_en => c1_p0_wr_en,
p0_wr_mask => c1_p0_wr_mask,
p0_wr_data => c1_p0_wr_data,
p0_wr_full => c1_p0_wr_full,
p0_wr_empty => c1_p0_wr_empty,
p0_wr_count => c1_p0_wr_count,
p0_wr_underrun => c1_p0_wr_underrun,
p0_wr_error => c1_p0_wr_error,
p0_rd_clk => c1_clk0,
p0_rd_en => c1_p0_rd_en,
p0_rd_data => c1_p0_rd_data,
p0_rd_full => c1_p0_rd_full,
p0_rd_empty => c1_p0_rd_empty,
p0_rd_count => c1_p0_rd_count,
p0_rd_overflow => c1_p0_rd_overflow,
p0_rd_error => c1_p0_rd_error,
selfrefresh_enter => c1_selfrefresh_enter,
selfrefresh_mode => c1_selfrefresh_mode
);
memc3_wrapper_inst : memc3_wrapper
generic map
(
C_MEMCLK_PERIOD => C3_MEMCLK_PERIOD,
C_CALIB_SOFT_IP => C3_CALIB_SOFT_IP,
C_SIMULATION => C3_SIMULATION,
C_P0_MASK_SIZE => C3_P0_MASK_SIZE,
C_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE,
C_P1_MASK_SIZE => C3_P1_MASK_SIZE,
C_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE,
C_ARB_NUM_TIME_SLOTS => C3_ARB_NUM_TIME_SLOTS,
C_ARB_TIME_SLOT_0 => C3_ARB_TIME_SLOT_0,
C_ARB_TIME_SLOT_1 => C3_ARB_TIME_SLOT_1,
C_ARB_TIME_SLOT_2 => C3_ARB_TIME_SLOT_2,
C_ARB_TIME_SLOT_3 => C3_ARB_TIME_SLOT_3,
C_ARB_TIME_SLOT_4 => C3_ARB_TIME_SLOT_4,
C_ARB_TIME_SLOT_5 => C3_ARB_TIME_SLOT_5,
C_ARB_TIME_SLOT_6 => C3_ARB_TIME_SLOT_6,
C_ARB_TIME_SLOT_7 => C3_ARB_TIME_SLOT_7,
C_ARB_TIME_SLOT_8 => C3_ARB_TIME_SLOT_8,
C_ARB_TIME_SLOT_9 => C3_ARB_TIME_SLOT_9,
C_ARB_TIME_SLOT_10 => C3_ARB_TIME_SLOT_10,
C_ARB_TIME_SLOT_11 => C3_ARB_TIME_SLOT_11,
C_MEM_TRAS => C3_MEM_TRAS,
C_MEM_TRCD => C3_MEM_TRCD,
C_MEM_TREFI => C3_MEM_TREFI,
C_MEM_TRFC => C3_MEM_TRFC,
C_MEM_TRP => C3_MEM_TRP,
C_MEM_TWR => C3_MEM_TWR,
C_MEM_TRTP => C3_MEM_TRTP,
C_MEM_TWTR => C3_MEM_TWTR,
C_MEM_ADDR_ORDER => C3_MEM_ADDR_ORDER,
C_NUM_DQ_PINS => C3_NUM_DQ_PINS,
C_MEM_TYPE => C3_MEM_TYPE,
C_MEM_DENSITY => C3_MEM_DENSITY,
C_MEM_BURST_LEN => C3_MEM_BURST_LEN,
C_MEM_CAS_LATENCY => C3_MEM_CAS_LATENCY,
C_MEM_ADDR_WIDTH => C3_MEM_ADDR_WIDTH,
C_MEM_BANKADDR_WIDTH => C3_MEM_BANKADDR_WIDTH,
C_MEM_NUM_COL_BITS => C3_MEM_NUM_COL_BITS,
C_MEM_DDR1_2_ODS => C3_MEM_DDR1_2_ODS,
C_MEM_DDR2_RTT => C3_MEM_DDR2_RTT,
C_MEM_DDR2_DIFF_DQS_EN => C3_MEM_DDR2_DIFF_DQS_EN,
C_MEM_DDR2_3_PA_SR => C3_MEM_DDR2_3_PA_SR,
C_MEM_DDR2_3_HIGH_TEMP_SR => C3_MEM_DDR2_3_HIGH_TEMP_SR,
C_MEM_DDR3_CAS_LATENCY => C3_MEM_DDR3_CAS_LATENCY,
C_MEM_DDR3_ODS => C3_MEM_DDR3_ODS,
C_MEM_DDR3_RTT => C3_MEM_DDR3_RTT,
C_MEM_DDR3_CAS_WR_LATENCY => C3_MEM_DDR3_CAS_WR_LATENCY,
C_MEM_DDR3_AUTO_SR => C3_MEM_DDR3_AUTO_SR,
C_MEM_MOBILE_PA_SR => C3_MEM_MOBILE_PA_SR,
C_MEM_MDDR_ODS => C3_MEM_MDDR_ODS,
C_MC_CALIB_BYPASS => C3_MC_CALIB_BYPASS,
C_MC_CALIBRATION_MODE => C3_MC_CALIBRATION_MODE,
C_MC_CALIBRATION_DELAY => C3_MC_CALIBRATION_DELAY,
C_SKIP_IN_TERM_CAL => C3_SKIP_IN_TERM_CAL,
C_SKIP_DYNAMIC_CAL => C3_SKIP_DYNAMIC_CAL,
C_LDQSP_TAP_DELAY_VAL => C3_LDQSP_TAP_DELAY_VAL,
C_LDQSN_TAP_DELAY_VAL => C3_LDQSN_TAP_DELAY_VAL,
C_UDQSP_TAP_DELAY_VAL => C3_UDQSP_TAP_DELAY_VAL,
C_UDQSN_TAP_DELAY_VAL => C3_UDQSN_TAP_DELAY_VAL,
C_DQ0_TAP_DELAY_VAL => C3_DQ0_TAP_DELAY_VAL,
C_DQ1_TAP_DELAY_VAL => C3_DQ1_TAP_DELAY_VAL,
C_DQ2_TAP_DELAY_VAL => C3_DQ2_TAP_DELAY_VAL,
C_DQ3_TAP_DELAY_VAL => C3_DQ3_TAP_DELAY_VAL,
C_DQ4_TAP_DELAY_VAL => C3_DQ4_TAP_DELAY_VAL,
C_DQ5_TAP_DELAY_VAL => C3_DQ5_TAP_DELAY_VAL,
C_DQ6_TAP_DELAY_VAL => C3_DQ6_TAP_DELAY_VAL,
C_DQ7_TAP_DELAY_VAL => C3_DQ7_TAP_DELAY_VAL,
C_DQ8_TAP_DELAY_VAL => C3_DQ8_TAP_DELAY_VAL,
C_DQ9_TAP_DELAY_VAL => C3_DQ9_TAP_DELAY_VAL,
C_DQ10_TAP_DELAY_VAL => C3_DQ10_TAP_DELAY_VAL,
C_DQ11_TAP_DELAY_VAL => C3_DQ11_TAP_DELAY_VAL,
C_DQ12_TAP_DELAY_VAL => C3_DQ12_TAP_DELAY_VAL,
C_DQ13_TAP_DELAY_VAL => C3_DQ13_TAP_DELAY_VAL,
C_DQ14_TAP_DELAY_VAL => C3_DQ14_TAP_DELAY_VAL,
C_DQ15_TAP_DELAY_VAL => C3_DQ15_TAP_DELAY_VAL
)
port map
(
mcb3_dram_dq => mcb3_dram_dq,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_odt => mcb3_dram_odt,
mcb3_dram_reset_n => mcb3_dram_reset_n,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_dm => mcb3_dram_dm,
mcb3_dram_udqs => mcb3_dram_udqs,
mcb3_dram_udqs_n => mcb3_dram_udqs_n,
mcb3_rzq => mcb3_rzq,
mcb3_zio => mcb3_zio,
mcb3_dram_udm => mcb3_dram_udm,
calib_done => c3_calib_done,
async_rst => c3_async_rst,
sysclk_2x => c3_sysclk_2x,
sysclk_2x_180 => c3_sysclk_2x_180,
pll_ce_0 => c3_pll_ce_0,
pll_ce_90 => c3_pll_ce_90,
pll_lock => c3_pll_lock,
mcb_drp_clk => c3_mcb_drp_clk,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_dqs_n => mcb3_dram_dqs_n,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
p0_cmd_clk => c3_clk0,
p0_cmd_en => c3_p0_cmd_en,
p0_cmd_instr => c3_p0_cmd_instr,
p0_cmd_bl => c3_p0_cmd_bl,
p0_cmd_byte_addr => c3_p0_cmd_byte_addr,
p0_cmd_empty => c3_p0_cmd_empty,
p0_cmd_full => c3_p0_cmd_full,
p0_wr_clk => c3_clk0,
p0_wr_en => c3_p0_wr_en,
p0_wr_mask => c3_p0_wr_mask,
p0_wr_data => c3_p0_wr_data,
p0_wr_full => c3_p0_wr_full,
p0_wr_empty => c3_p0_wr_empty,
p0_wr_count => c3_p0_wr_count,
p0_wr_underrun => c3_p0_wr_underrun,
p0_wr_error => c3_p0_wr_error,
p0_rd_clk => c3_clk0,
p0_rd_en => c3_p0_rd_en,
p0_rd_data => c3_p0_rd_data,
p0_rd_full => c3_p0_rd_full,
p0_rd_empty => c3_p0_rd_empty,
p0_rd_count => c3_p0_rd_count,
p0_rd_overflow => c3_p0_rd_overflow,
p0_rd_error => c3_p0_rd_error,
selfrefresh_enter => c3_selfrefresh_enter,
selfrefresh_mode => c3_selfrefresh_mode
);
memc1_tb_top_inst : memc1_tb_top
generic map
(
C_SIMULATION => C1_SIMULATION,
C_P0_MASK_SIZE => C1_P0_MASK_SIZE,
C_P0_DATA_PORT_SIZE => C1_P0_DATA_PORT_SIZE,
C_P1_MASK_SIZE => C1_P1_MASK_SIZE,
C_P1_DATA_PORT_SIZE => C1_P1_DATA_PORT_SIZE,
C_NUM_DQ_PINS => C1_NUM_DQ_PINS,
C_MEM_BURST_LEN => C1_MEM_BURST_LEN,
C_MEM_NUM_COL_BITS => C1_MEM_NUM_COL_BITS,
C_SMALL_DEVICE => C1_SMALL_DEVICE,
C_p0_BEGIN_ADDRESS => C1_p0_BEGIN_ADDRESS,
C_p0_DATA_MODE => C1_p0_DATA_MODE,
C_p0_END_ADDRESS => C1_p0_END_ADDRESS,
C_p0_PRBS_EADDR_MASK_POS => C1_p0_PRBS_EADDR_MASK_POS,
C_p0_PRBS_SADDR_MASK_POS => C1_p0_PRBS_SADDR_MASK_POS
)
port map
(
error => c1_error,
calib_done => c1_calib_done,
clk0 => c1_clk0,
rst0 => c1_rst0,
cmp_error => c1_cmp_error,
cmp_data_valid => c1_cmp_data_valid,
vio_modify_enable => c1_vio_modify_enable,
error_status => c1_error_status,
vio_data_mode_value => c1_vio_data_mode_value,
vio_addr_mode_value => c1_vio_addr_mode_value,
cmp_data => c1_cmp_data,
p0_mcb_cmd_en_o => c1_p0_cmd_en,
p0_mcb_cmd_instr_o => c1_p0_cmd_instr,
p0_mcb_cmd_bl_o => c1_p0_cmd_bl,
p0_mcb_cmd_addr_o => c1_p0_cmd_byte_addr,
p0_mcb_cmd_full_i => c1_p0_cmd_full,
p0_mcb_wr_en_o => c1_p0_wr_en,
p0_mcb_wr_mask_o => c1_p0_wr_mask,
p0_mcb_wr_data_o => c1_p0_wr_data,
p0_mcb_wr_full_i => c1_p0_wr_full,
p0_mcb_wr_fifo_counts => c1_p0_wr_count,
p0_mcb_rd_en_o => c1_p0_rd_en,
p0_mcb_rd_data_i => c1_p0_rd_data,
p0_mcb_rd_empty_i => c1_p0_rd_empty,
p0_mcb_rd_fifo_counts => c1_p0_rd_count
);
memc3_tb_top_inst : memc3_tb_top
generic map
(
C_SIMULATION => C3_SIMULATION,
C_P0_MASK_SIZE => C3_P0_MASK_SIZE,
C_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE,
C_P1_MASK_SIZE => C3_P1_MASK_SIZE,
C_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE,
C_NUM_DQ_PINS => C3_NUM_DQ_PINS,
C_MEM_BURST_LEN => C3_MEM_BURST_LEN,
C_MEM_NUM_COL_BITS => C3_MEM_NUM_COL_BITS,
C_SMALL_DEVICE => C3_SMALL_DEVICE,
C_p0_BEGIN_ADDRESS => C3_p0_BEGIN_ADDRESS,
C_p0_DATA_MODE => C3_p0_DATA_MODE,
C_p0_END_ADDRESS => C3_p0_END_ADDRESS,
C_p0_PRBS_EADDR_MASK_POS => C3_p0_PRBS_EADDR_MASK_POS,
C_p0_PRBS_SADDR_MASK_POS => C3_p0_PRBS_SADDR_MASK_POS
)
port map
(
error => c3_error,
calib_done => c3_calib_done,
clk0 => c3_clk0,
rst0 => c3_rst0,
cmp_error => c3_cmp_error,
cmp_data_valid => c3_cmp_data_valid,
vio_modify_enable => c3_vio_modify_enable,
error_status => c3_error_status,
vio_data_mode_value => c3_vio_data_mode_value,
vio_addr_mode_value => c3_vio_addr_mode_value,
cmp_data => c3_cmp_data,
p0_mcb_cmd_en_o => c3_p0_cmd_en,
p0_mcb_cmd_instr_o => c3_p0_cmd_instr,
p0_mcb_cmd_bl_o => c3_p0_cmd_bl,
p0_mcb_cmd_addr_o => c3_p0_cmd_byte_addr,
p0_mcb_cmd_full_i => c3_p0_cmd_full,
p0_mcb_wr_en_o => c3_p0_wr_en,
p0_mcb_wr_mask_o => c3_p0_wr_mask,
p0_mcb_wr_data_o => c3_p0_wr_data,
p0_mcb_wr_full_i => c3_p0_wr_full,
p0_mcb_wr_fifo_counts => c3_p0_wr_count,
p0_mcb_rd_en_o => c3_p0_rd_en,
p0_mcb_rd_data_i => c3_p0_rd_data,
p0_mcb_rd_empty_i => c3_p0_rd_empty,
p0_mcb_rd_fifo_counts => c3_p0_rd_count
);
end arc;
| gpl-3.0 | 1d3b894510c1c7d4ed904524f2dd73a6 | 0.446386 | 3.440965 | false | false | false | false |
Nixon-/VHDL_library | basic/segment_decoder.vhd | 1 | 1,019 | Library ieee;
use ieee.std_logic_1164.all;
entity segment_decoder is
port(
hexIn: in std_logic_vector(3 downto 0);
segmentMux: out std_logic_vector(6 downto 0)
);
end segment_decoder;
architecture primary of segment_decoder is
begin
process(hexIn) begin
case hexIn is
when "0000" => segmentMux <= "0000001";
when "0001" => segmentMux <= "1111001";
when "0010" => segmentMux <= "0100100";
when "0011" => segmentMux <= "0110000";
when "0100" => segmentMux <= "0011001";
when "0101" => segmentMux <= "0010010";
when "0110" => segmentMux <= "0000010";
when "0111" => segmentMux <= "1111000";
when "1000" => segmentMux <= "0000000";
when "1001" => segmentMux <= "0010000";
when "1010" => segmentMux <= "0001000";
when "1011" => segmentMux <= "0000011";
when "1100" => segmentMux <= "1000110";
when "1101" => segmentMux <= "0100001";
when "1110" => segmentMux <= "0000110";
when "1111" => segmentMux <= "0001110";
end case;
end process;
end primary; | gpl-2.0 | e7be3ba3a27e3e6a9eb9c90a4360199b | 0.625123 | 3.204403 | false | false | false | false |
masaruohashi/tic-tac-toe | uart/unidade_controle_transmissao.vhd | 1 | 1,680 | -- VHDL da Unidade de Controle
library ieee;
use ieee.std_logic_1164.all;
entity unidade_controle_transmissao is
port(clock : in std_logic;
comeca : in std_logic;
fim : in std_logic;
reseta : in std_logic;
saida : out std_logic_vector(4 downto 0)); -- carrega|zera|desloca|conta|pronto
end unidade_controle_transmissao;
architecture exemplo of unidade_controle_transmissao is
type tipo_estado is (inicial, preparacao, transmissao, final, espera);
signal estado : tipo_estado;
begin
process (clock, estado, reseta)
begin
if reseta = '1' then
estado <= inicial;
elsif (clock'event and clock = '1') then
case estado is
when inicial => -- Aguarda sinal de inicio
if comeca = '1' then
estado <= preparacao;
end if;
when preparacao => -- Zera contador e carrega bits no registrador
estado <= transmissao;
when transmissao => -- Desloca os bits no registrador
if fim = '1' then
estado <= final;
else
estado <= transmissao;
end if;
when final => -- Fim da transmissao serial
estado <= espera;
when espera => -- Detector de borda do sinal de inicio
if comeca = '1' then
estado <= espera;
else
estado <= inicial;
end if;
end case;
end if;
end process;
process (estado)
begin
case estado is
when inicial =>
saida <= "00000";
when preparacao =>
saida <= "11000";
when transmissao =>
saida <= "00110";
when final =>
saida <= "00001";
when espera =>
saida <= "00000";
end case;
end process;
end exemplo;
| mit | 028c4aa8bd389ccb6a679f21f88bb03d | 0.599405 | 3.559322 | false | false | false | false |
JavierRizzoA/Sacagawea | sources/mem_control.vhd | 1 | 43,520 |
-- Company:
-- Engineer:
--
-- Create Date: 16:52:41 06/05/2016
-- Design Name:
-- Module Name: mem_control - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity mem_control is
port(
IR: in std_logic_vector(7 downto 0);
CONT: in std_logic_vector(2 downto 0);
salida_mem_control : out std_logic_vector(24 downto 0)
);
end mem_control;
architecture Behavioral of mem_control is
signal señales_de_control : std_logic_vector(27 downto 0);
begin
señales_de_control <= X"0050100" WHEN IR&CONT = "00000000000" ELSE
X"0004000" WHEN IR&CONT = "00000000001" ELSE
X"0802000" WHEN IR&CONT = "00000000010" ELSE
X"0050100" WHEN IR&CONT = "00000001000" ELSE
X"0004000" WHEN IR&CONT = "00000001001" ELSE
X"0802001" WHEN IR&CONT = "00000001010" ELSE
X"0050100" WHEN IR&CONT = "00000010000" ELSE
X"0004000" WHEN IR&CONT = "00000010001" ELSE
X"0802002" WHEN IR&CONT = "00000010010" ELSE
X"0050100" WHEN IR&CONT = "00000011000" ELSE
X"0004000" WHEN IR&CONT = "00000011001" ELSE
X"0050100" WHEN IR&CONT = "00000011010" ELSE
X"0008000" WHEN IR&CONT = "00000011011" ELSE
X"0802003" WHEN IR&CONT = "00000011100" ELSE
X"0050100" WHEN IR&CONT = "00000100000" ELSE
X"0004000" WHEN IR&CONT = "00000100001" ELSE
X"0801004" WHEN IR&CONT = "00000100010" ELSE
X"0050100" WHEN IR&CONT = "00000101000" ELSE
X"0004000" WHEN IR&CONT = "00000101001" ELSE
X"0801005" WHEN IR&CONT = "00000101010" ELSE
X"0050100" WHEN IR&CONT = "00000110000" ELSE
X"0004000" WHEN IR&CONT = "00000110001" ELSE
X"0801006" WHEN IR&CONT = "00000110010" ELSE
X"0050100" WHEN IR&CONT = "00000111000" ELSE
X"0004000" WHEN IR&CONT = "00000111001" ELSE
X"0050100" WHEN IR&CONT = "00000111010" ELSE
X"0008000" WHEN IR&CONT = "00000111011" ELSE
X"0801007" WHEN IR&CONT = "00000111100" ELSE
X"0050100" WHEN IR&CONT = "00001000000" ELSE
X"0004000" WHEN IR&CONT = "00001000001" ELSE
X"0800808" WHEN IR&CONT = "00001000010" ELSE
X"0050100" WHEN IR&CONT = "00001001000" ELSE
X"0004000" WHEN IR&CONT = "00001001001" ELSE
X"0800809" WHEN IR&CONT = "00001001010" ELSE
X"0050100" WHEN IR&CONT = "00001010000" ELSE
X"0004000" WHEN IR&CONT = "00001010001" ELSE
X"080080A" WHEN IR&CONT = "00001010010" ELSE
X"0050100" WHEN IR&CONT = "00001011000" ELSE
X"0004000" WHEN IR&CONT = "00001011001" ELSE
X"0050100" WHEN IR&CONT = "00001011010" ELSE
X"0008000" WHEN IR&CONT = "00001011011" ELSE
X"080080B" WHEN IR&CONT = "00001011100" ELSE
X"0050100" WHEN IR&CONT = "00010011000" ELSE
X"0004000" WHEN IR&CONT = "00010011001" ELSE
X"0050100" WHEN IR&CONT = "00010011010" ELSE
X"0008000" WHEN IR&CONT = "00010011011" ELSE
X"0010020" WHEN IR&CONT = "00010011100" ELSE
X"0008000" WHEN IR&CONT = "00010011101" ELSE
X"0802003" WHEN IR&CONT = "00010011110" ELSE
X"0050100" WHEN IR&CONT = "00011100000" ELSE
X"0004000" WHEN IR&CONT = "00011100001" ELSE
X"0050100" WHEN IR&CONT = "00011100010" ELSE
X"0008000" WHEN IR&CONT = "00011100011" ELSE
X"0010020" WHEN IR&CONT = "00011100100" ELSE
X"0008010" WHEN IR&CONT = "00011100101" ELSE
X"0800200" WHEN IR&CONT = "00011100110" ELSE
X"0050100" WHEN IR&CONT = "00010111000" ELSE
X"0004000" WHEN IR&CONT = "00010111001" ELSE
X"0050100" WHEN IR&CONT = "00010111010" ELSE
X"0008000" WHEN IR&CONT = "00010111011" ELSE
X"0010020" WHEN IR&CONT = "00010111100" ELSE
X"0008000" WHEN IR&CONT = "00010111101" ELSE
X"0801007" WHEN IR&CONT = "00010111110" ELSE
X"0050100" WHEN IR&CONT = "00011101000" ELSE
X"0004000" WHEN IR&CONT = "00011101001" ELSE
X"0050100" WHEN IR&CONT = "00011101010" ELSE
X"0008000" WHEN IR&CONT = "00011101011" ELSE
X"0010020" WHEN IR&CONT = "00011101100" ELSE
X"0008015" WHEN IR&CONT = "00011101101" ELSE
X"0800200" WHEN IR&CONT = "00011101110" ELSE
X"0050100" WHEN IR&CONT = "00011011000" ELSE
X"0004000" WHEN IR&CONT = "00011011001" ELSE
X"0050100" WHEN IR&CONT = "00011011010" ELSE
X"0008000" WHEN IR&CONT = "00011011011" ELSE
X"0010020" WHEN IR&CONT = "00011011100" ELSE
X"0008000" WHEN IR&CONT = "00011011101" ELSE
X"080080B" WHEN IR&CONT = "00011011110" ELSE
X"0050100" WHEN IR&CONT = "00011110000" ELSE
X"0004000" WHEN IR&CONT = "00011110001" ELSE
X"0050100" WHEN IR&CONT = "00011110010" ELSE
X"0008000" WHEN IR&CONT = "00011110011" ELSE
X"0010020" WHEN IR&CONT = "00011110100" ELSE
X"000801A" WHEN IR&CONT = "00011110101" ELSE
X"0800200" WHEN IR&CONT = "00011110110" ELSE
X"0050100" WHEN IR&CONT = "00100000000" ELSE
X"0004000" WHEN IR&CONT = "00100000001" ELSE
X"0820000" WHEN IR&CONT = "00100000010" ELSE
X"0050100" WHEN IR&CONT = "00100001000" ELSE
X"0004000" WHEN IR&CONT = "00100001001" ELSE
X"0820000" WHEN IR&CONT = "00100001010" ELSE
X"0050100" WHEN IR&CONT = "00100010000" ELSE
X"0004000" WHEN IR&CONT = "00100010001" ELSE
X"0820000" WHEN IR&CONT = "00100010010" ELSE
X"0050100" WHEN IR&CONT = "00100011000" ELSE
X"0004000" WHEN IR&CONT = "00100011001" ELSE
X"0820000" WHEN IR&CONT = "00100011010" ELSE
X"0050100" WHEN IR&CONT = "00100100000" ELSE
X"0004000" WHEN IR&CONT = "00100100001" ELSE
X"0820000" WHEN IR&CONT = "00100100010" ELSE
X"0050100" WHEN IR&CONT = "00100101000" ELSE
X"0004000" WHEN IR&CONT = "00100101001" ELSE
X"0820000" WHEN IR&CONT = "00100101010" ELSE
X"0050100" WHEN IR&CONT = "00100110000" ELSE
X"0004000" WHEN IR&CONT = "00100110001" ELSE
X"0820000" WHEN IR&CONT = "00100110010" ELSE
X"0050100" WHEN IR&CONT = "00100111000" ELSE
X"0004000" WHEN IR&CONT = "00100111001" ELSE
X"0820000" WHEN IR&CONT = "00100111010" ELSE
X"0050100" WHEN IR&CONT = "00101000000" ELSE
X"0004000" WHEN IR&CONT = "00101000001" ELSE
X"0820000" WHEN IR&CONT = "00101000010" ELSE
X"0050100" WHEN IR&CONT = "00101001000" ELSE
X"0004000" WHEN IR&CONT = "00101001001" ELSE
X"0820000" WHEN IR&CONT = "00101001010" ELSE
X"0050100" WHEN IR&CONT = "00101010000" ELSE
X"0004000" WHEN IR&CONT = "00101010001" ELSE
X"0820000" WHEN IR&CONT = "00101010010" ELSE
X"0050100" WHEN IR&CONT = "00101011000" ELSE
X"0004000" WHEN IR&CONT = "00101011001" ELSE
X"0820000" WHEN IR&CONT = "00101011010" ELSE
X"0050100" WHEN IR&CONT = "00101100000" ELSE
X"0004000" WHEN IR&CONT = "00101100001" ELSE
X"0820000" WHEN IR&CONT = "00101100010" ELSE
X"0050100" WHEN IR&CONT = "00101101000" ELSE
X"0004000" WHEN IR&CONT = "00101101001" ELSE
X"0820000" WHEN IR&CONT = "00101101010" ELSE
X"0050100" WHEN IR&CONT = "00101110000" ELSE
X"0004000" WHEN IR&CONT = "00101110001" ELSE
X"0820000" WHEN IR&CONT = "00101110010" ELSE
X"0050100" WHEN IR&CONT = "00101111000" ELSE
X"0004000" WHEN IR&CONT = "00101111001" ELSE
X"0820000" WHEN IR&CONT = "00101111010" ELSE
X"0050100" WHEN IR&CONT = "00110000000" ELSE
X"0004000" WHEN IR&CONT = "00110000001" ELSE
X"0882000" WHEN IR&CONT = "00110000010" ELSE
X"0050100" WHEN IR&CONT = "00110001000" ELSE
X"0004000" WHEN IR&CONT = "00110001001" ELSE
X"0882001" WHEN IR&CONT = "00110001010" ELSE
X"0050100" WHEN IR&CONT = "00110010000" ELSE
X"0004000" WHEN IR&CONT = "00110010001" ELSE
X"0882002" WHEN IR&CONT = "00110010010" ELSE
X"0050100" WHEN IR&CONT = "00110011000" ELSE
X"0004000" WHEN IR&CONT = "00110011001" ELSE
X"0050100" WHEN IR&CONT = "00110011010" ELSE
X"0008000" WHEN IR&CONT = "00110011011" ELSE
X"0882003" WHEN IR&CONT = "00110011100" ELSE
X"0050100" WHEN IR&CONT = "00110100000" ELSE
X"0004000" WHEN IR&CONT = "00110100001" ELSE
X"0881004" WHEN IR&CONT = "00110100010" ELSE
X"0050100" WHEN IR&CONT = "00110101000" ELSE
X"0004000" WHEN IR&CONT = "00110101001" ELSE
X"0881005" WHEN IR&CONT = "00110101010" ELSE
X"0050100" WHEN IR&CONT = "00110110000" ELSE
X"0004000" WHEN IR&CONT = "00110110001" ELSE
X"0881006" WHEN IR&CONT = "00110110010" ELSE
X"0050100" WHEN IR&CONT = "00110111000" ELSE
X"0004000" WHEN IR&CONT = "00110111001" ELSE
X"0050100" WHEN IR&CONT = "00110111010" ELSE
X"0008000" WHEN IR&CONT = "00110111011" ELSE
X"0881007" WHEN IR&CONT = "00110111100" ELSE
X"0050100" WHEN IR&CONT = "00111000000" ELSE
X"0004000" WHEN IR&CONT = "00111000001" ELSE
X"0880808" WHEN IR&CONT = "00111000010" ELSE
X"0050100" WHEN IR&CONT = "00111001000" ELSE
X"0004000" WHEN IR&CONT = "00111001001" ELSE
X"0880809" WHEN IR&CONT = "00111001010" ELSE
X"0050100" WHEN IR&CONT = "00111010000" ELSE
X"0004000" WHEN IR&CONT = "00111010001" ELSE
X"088080A" WHEN IR&CONT = "00111010010" ELSE
X"0050100" WHEN IR&CONT = "00111011000" ELSE
X"0004000" WHEN IR&CONT = "00111011001" ELSE
X"0050100" WHEN IR&CONT = "00111011010" ELSE
X"0008000" WHEN IR&CONT = "00111011011" ELSE
X"088080B" WHEN IR&CONT = "00111011100" ELSE
X"0050100" WHEN IR&CONT = "01000000000" ELSE
X"0004000" WHEN IR&CONT = "01000000001" ELSE
X"0902000" WHEN IR&CONT = "01000000010" ELSE
X"0050100" WHEN IR&CONT = "01000001000" ELSE
X"0004000" WHEN IR&CONT = "01000001001" ELSE
X"0902001" WHEN IR&CONT = "01000001010" ELSE
X"0050100" WHEN IR&CONT = "01000010000" ELSE
X"0004000" WHEN IR&CONT = "01000010001" ELSE
X"0902002" WHEN IR&CONT = "01000010010" ELSE
X"0050100" WHEN IR&CONT = "01000011000" ELSE
X"0004000" WHEN IR&CONT = "01000011001" ELSE
X"0050100" WHEN IR&CONT = "01000011010" ELSE
X"0008000" WHEN IR&CONT = "01000011011" ELSE
X"0902003" WHEN IR&CONT = "01000011100" ELSE
X"0050100" WHEN IR&CONT = "01000100000" ELSE
X"0004000" WHEN IR&CONT = "01000100001" ELSE
X"0901004" WHEN IR&CONT = "01000100010" ELSE
X"0050100" WHEN IR&CONT = "01000101000" ELSE
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X"080080B" WHEN IR&CONT = "11011010101" ELSE
X"0050100" WHEN IR&CONT = "11100000000" ELSE
X"0004000" WHEN IR&CONT = "11100000001" ELSE
X"0008010" WHEN IR&CONT = "11100000010" ELSE
X"0010020" WHEN IR&CONT = "11100000011" ELSE
X"0008010" WHEN IR&CONT = "11100000100" ELSE
X"0800200" WHEN IR&CONT = "11100000101" ELSE
X"0050100" WHEN IR&CONT = "11100001000" ELSE
X"0004000" WHEN IR&CONT = "11100001001" ELSE
X"0008010" WHEN IR&CONT = "11100001010" ELSE
X"0010020" WHEN IR&CONT = "11100001011" ELSE
X"0008015" WHEN IR&CONT = "11100001100" ELSE
X"0800200" WHEN IR&CONT = "11100001101" ELSE
X"0050100" WHEN IR&CONT = "11100010000" ELSE
X"0004000" WHEN IR&CONT = "11100010001" ELSE
X"0008010" WHEN IR&CONT = "11100010010" ELSE
X"0010020" WHEN IR&CONT = "11100010011" ELSE
X"000801A" WHEN IR&CONT = "11100010100" ELSE
X"0800200" WHEN IR&CONT = "11100010101" ELSE
X"0050100" WHEN IR&CONT = "11100100000" ELSE
X"0004000" WHEN IR&CONT = "11100100001" ELSE
X"0008015" WHEN IR&CONT = "11100100010" ELSE
X"0010020" WHEN IR&CONT = "11100100011" ELSE
X"0008010" WHEN IR&CONT = "11100100100" ELSE
X"0800200" WHEN IR&CONT = "11100100101" ELSE
X"0050100" WHEN IR&CONT = "11100101000" ELSE
X"0004000" WHEN IR&CONT = "11100101001" ELSE
X"0008015" WHEN IR&CONT = "11100101010" ELSE
X"0010020" WHEN IR&CONT = "11100101011" ELSE
X"0008015" WHEN IR&CONT = "11100101100" ELSE
X"0800200" WHEN IR&CONT = "11100101101" ELSE
X"0050100" WHEN IR&CONT = "11100110000" ELSE
X"0004000" WHEN IR&CONT = "11100110001" ELSE
X"0008015" WHEN IR&CONT = "11100110010" ELSE
X"0010020" WHEN IR&CONT = "11100110011" ELSE
X"000801A" WHEN IR&CONT = "11100110100" ELSE
X"0800200" WHEN IR&CONT = "11100110101" ELSE
X"0050100" WHEN IR&CONT = "11101000000" ELSE
X"0004000" WHEN IR&CONT = "11101000001" ELSE
X"000801A" WHEN IR&CONT = "11101000010" ELSE
X"0010020" WHEN IR&CONT = "11101000011" ELSE
X"0008010" WHEN IR&CONT = "11101000100" ELSE
X"0800200" WHEN IR&CONT = "11101000101" ELSE
X"0050100" WHEN IR&CONT = "11101001000" ELSE
X"0004000" WHEN IR&CONT = "11101001001" ELSE
X"000801A" WHEN IR&CONT = "11101001010" ELSE
X"0010020" WHEN IR&CONT = "11101001011" ELSE
X"0008015" WHEN IR&CONT = "11101001100" ELSE
X"0800200" WHEN IR&CONT = "11101001101" ELSE
X"0050100" WHEN IR&CONT = "11101010000" ELSE
X"0004000" WHEN IR&CONT = "11101010001" ELSE
X"000801A" WHEN IR&CONT = "11101010010" ELSE
X"0010020" WHEN IR&CONT = "11101010011" ELSE
X"000801A" WHEN IR&CONT = "11101010100" ELSE
X"0800200" WHEN IR&CONT = "11101010101" ELSE
X"0050100" WHEN IR&CONT = "11110000000" ELSE
X"0004000" WHEN IR&CONT = "11110000001" ELSE
X"0050100" WHEN IR&CONT = "11110000010" ELSE
X"0008000" WHEN IR&CONT = "11110000011" ELSE
X"1000000" WHEN IR&CONT = "11110000100" ELSE
X"0840040" WHEN IR&CONT = "11110000101" ELSE
X"0050100" WHEN IR&CONT = "11110001000" ELSE
X"0004000" WHEN IR&CONT = "11110001001" ELSE
X"0050100" WHEN IR&CONT = "11110001010" ELSE
X"0008000" WHEN IR&CONT = "11110001011" ELSE
X"1000000" WHEN IR&CONT = "11110001100" ELSE
X"0840040" WHEN IR&CONT = "11110001101" ELSE
X"0050100" WHEN IR&CONT = "11110010000" ELSE
X"0004000" WHEN IR&CONT = "11110010001" ELSE
X"0050100" WHEN IR&CONT = "11110010010" ELSE
X"0008000" WHEN IR&CONT = "11110010011" ELSE
X"1000000" WHEN IR&CONT = "11110010100" ELSE
X"0840040" WHEN IR&CONT = "11110010101" ELSE
X"0050100" WHEN IR&CONT = "11110011000" ELSE
X"0004000" WHEN IR&CONT = "11110011001" ELSE
X"0050100" WHEN IR&CONT = "11110011010" ELSE
X"0008000" WHEN IR&CONT = "11110011011" ELSE
X"1000000" WHEN IR&CONT = "11110011100" ELSE
X"0840040" WHEN IR&CONT = "11110011101" ELSE
X"0050100" WHEN IR&CONT = "11110100000" ELSE
X"0004000" WHEN IR&CONT = "11110100001" ELSE
X"0050100" WHEN IR&CONT = "11110100010" ELSE
X"0008000" WHEN IR&CONT = "11110100011" ELSE
X"1000000" WHEN IR&CONT = "11110100100" ELSE
X"0840040" WHEN IR&CONT = "11110100101" ELSE
X"0050100" WHEN IR&CONT = "11110101000" ELSE
X"0004000" WHEN IR&CONT = "11110101001" ELSE
X"0050100" WHEN IR&CONT = "11110101010" ELSE
X"0008000" WHEN IR&CONT = "11110101011" ELSE
X"1000000" WHEN IR&CONT = "11110101100" ELSE
X"0840040" WHEN IR&CONT = "11110101101" ELSE
X"0050100" WHEN IR&CONT = "11110110000" ELSE
X"0004000" WHEN IR&CONT = "11110110001" ELSE
X"0050100" WHEN IR&CONT = "11110110010" ELSE
X"0008000" WHEN IR&CONT = "11110110011" ELSE
X"1000000" WHEN IR&CONT = "11110110100" ELSE
X"0840040" WHEN IR&CONT = "11110110101" ELSE
X"0050100" WHEN IR&CONT = "11110111000" ELSE
X"0004000" WHEN IR&CONT = "11110111001" ELSE
X"0050100" WHEN IR&CONT = "11110111010" ELSE
X"0008000" WHEN IR&CONT = "11110111011" ELSE
X"1000000" WHEN IR&CONT = "11110111100" ELSE
X"0840040" WHEN IR&CONT = "11110111101" ELSE
X"0050100" WHEN IR&CONT = "11111000000" ELSE
X"0004000" WHEN IR&CONT = "11111000001" ELSE
X"0050100" WHEN IR&CONT = "11111000010" ELSE
X"0008000" WHEN IR&CONT = "11111000011" ELSE
X"1000000" WHEN IR&CONT = "11111000100" ELSE
X"0840040" WHEN IR&CONT = "11111000101" ELSE
X"0050100" WHEN IR&CONT = "11111001000" ELSE
X"0004000" WHEN IR&CONT = "11111001001" ELSE
X"0050100" WHEN IR&CONT = "11111001010" ELSE
X"0008000" WHEN IR&CONT = "11111001011" ELSE
X"1000000" WHEN IR&CONT = "11111001100" ELSE
X"0840040" WHEN IR&CONT = "11111001101" ELSE
X"0050100" WHEN IR&CONT = "11111010000" ELSE
X"0004000" WHEN IR&CONT = "11111010001" ELSE
X"0050100" WHEN IR&CONT = "11111010010" ELSE
X"0008000" WHEN IR&CONT = "11111010011" ELSE
X"1000000" WHEN IR&CONT = "11111010100" ELSE
X"0840040" WHEN IR&CONT = "11111010101" ELSE
X"0050100" WHEN IR&CONT = "11111011000" ELSE
X"0004000" WHEN IR&CONT = "11111011001" ELSE
X"0050100" WHEN IR&CONT = "11111011010" ELSE
X"0008000" WHEN IR&CONT = "11111011011" ELSE
X"1000000" WHEN IR&CONT = "11111011100" ELSE
X"0840040" WHEN IR&CONT = "11111011101" ELSE
X"0050100" WHEN IR&CONT = "11111100000" ELSE
X"0004000" WHEN IR&CONT = "11111100001" ELSE
X"0050100" WHEN IR&CONT = "11111100010" ELSE
X"0008000" WHEN IR&CONT = "11111100011" ELSE
X"1000000" WHEN IR&CONT = "11111100100" ELSE
X"0840040" WHEN IR&CONT = "11111100101" ELSE
X"0050100" WHEN IR&CONT = "11111101000" ELSE
X"0004000" WHEN IR&CONT = "11111101001" ELSE
X"0050100" WHEN IR&CONT = "11111101010" ELSE
X"0008000" WHEN IR&CONT = "11111101011" ELSE
X"1000000" WHEN IR&CONT = "11111101100" ELSE
X"0840040" WHEN IR&CONT = "11111101101" ELSE
X"0050100" WHEN IR&CONT = "11111110000" ELSE
X"0004000" WHEN IR&CONT = "11111110001" ELSE
X"0050100" WHEN IR&CONT = "11111110010" ELSE
X"0008000" WHEN IR&CONT = "11111110011" ELSE
X"1000000" WHEN IR&CONT = "11111110100" ELSE
X"0840040" WHEN IR&CONT = "11111110101" ELSE
X"0050100" WHEN IR&CONT = "11111111000" ELSE
X"0004000" WHEN IR&CONT = "11111111001" ELSE
X"0050100" WHEN IR&CONT = "11111111010" ELSE
X"0008000" WHEN IR&CONT = "11111111011" ELSE
X"1000000" WHEN IR&CONT = "11111111100" ELSE
X"0840040" WHEN IR&CONT = "11111111101" ELSE
X"0050100" WHEN IR&CONT = "10011110000" ELSE
X"0004000" WHEN IR&CONT = "10011110001" ELSE
X"0840080" WHEN IR&CONT = "10011110010" ELSE
X"0004000";
salida_mem_control <= señales_de_control(24 downto 0);
end Behavioral;
| mit | c5549178e9db45ce091947e92f3c904e | 0.604756 | 3.482436 | false | false | false | false |
timofonic/PHDL | misc/projects/spartan_pcie_board/fpga/lx45t_pinout/ipcore_dir/pcie_core/source/pcie_bram_s6.vhd | 1 | 7,355 | -------------------------------------------------------------------------------
--
-- (c) Copyright 2008, 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Project : Spartan-6 Integrated Block for PCI Express
-- File : pcie_bram_s6.vhd
-- Description: BlockRAM module for Spartan-6 PCIe Block
-- The BRAM A port is the write port.
-- The BRAM B port is the read port.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity pcie_bram_s6 is
generic (
DOB_REG : integer := 0; -- 1 use output register, 0 don't use output register
WIDTH : integer := 0 -- supported WIDTH values are: 4, 9, 18, 36
);
port (
user_clk_i : in std_logic; -- user clock
reset_i : in std_logic; -- bram reset
wen_i : in std_logic; -- write enable
waddr_i : in std_logic_vector(11 downto 0); -- write address
wdata_i : in std_logic_vector(WIDTH-1 downto 0); -- write data
ren_i : in std_logic; -- read enable
rce_i : in std_logic; -- output register clock enable
raddr_i : in std_logic_vector(11 downto 0); -- read address
rdata_o : out std_logic_vector(WIDTH-1 downto 0) -- read data
);
end pcie_bram_s6;
architecture rtl of pcie_bram_s6 is
function CALC_ADDR(constant WIDTH : in integer;
constant addr_in : in std_logic_vector(11 downto 0)
) return std_logic_vector is
variable ADDR : std_logic_vector(13 downto 0);
begin
if WIDTH = 4 then ADDR := addr_in(11 downto 0) & "00";
elsif WIDTH = 9 then ADDR := addr_in(10 downto 0) & "000";
elsif WIDTH = 18 then ADDR := addr_in(9 downto 0) & "0000";
else ADDR := addr_in(8 downto 0) & "00000"; -- WIDTH=36
end if;
return ADDR;
end function CALC_ADDR;
signal di_int : std_logic_vector(31 downto 0);
signal dip_int : std_logic_vector(3 downto 0);
signal do_int : std_logic_vector(31 downto 0);
signal dop_int : std_logic_vector(3 downto 0);
signal waddr_int : std_logic_vector(13 downto 0);
signal raddr_int : std_logic_vector(13 downto 0);
signal wen_int : std_logic_vector(3 downto 0);
begin
--synthesis translate_off
process
begin
case WIDTH is
when 4 | 9 | 18 | 36 =>
null;
when others =>
report "ERROR: WIDTH size " & integer'image(WIDTH) & " is not supported."
severity failure;
end case;
wait;
end process;
--synthesis translate_on
-- Wire up BRAM I/Os to module I/Os - map data & parity bits appropriately
width_36 : if (WIDTH = 36) generate
di_int <= wdata_i(31 downto 0);
dip_int <= wdata_i(35 downto 32);
rdata_o(35 downto 32) <= dop_int;
rdata_o(31 downto 0) <= do_int;
end generate width_36;
width_18 : if (WIDTH = 18) generate
di_int(31 downto 16) <= (OTHERS => '0');
di_int(15 downto 0) <= wdata_i(15 downto 0);
dip_int(3 downto 2) <= (OTHERS => '0');
dip_int(1 downto 0) <= wdata_i(17 downto 16);
rdata_o(17 downto 16) <= dop_int(1 downto 0);
rdata_o(15 downto 0) <= do_int(15 downto 0);
end generate width_18;
width_9 : if (WIDTH = 9) generate
di_int(31 downto 8) <= (OTHERS => '0');
di_int(7 downto 0) <= wdata_i(7 downto 0);
dip_int(3 downto 1) <= (OTHERS => '0');
dip_int(0) <= wdata_i(8);
rdata_o(8) <= dop_int(0);
rdata_o(7 downto 0) <= do_int(7 downto 0);
end generate width_9;
width_4 : if (WIDTH = 4) generate
di_int(31 downto 4) <= (OTHERS => '0');
di_int(3 downto 0) <= wdata_i(3 downto 0);
dip_int <= (OTHERS => '0');
rdata_o <= do_int(3 downto 0);
end generate width_4;
waddr_int <= CALC_ADDR(WIDTH, waddr_i);
raddr_int <= CALC_ADDR(WIDTH, raddr_i);
wen_int <= wen_i & wen_i & wen_i & wen_i;
ramb16 : RAMB16BWER
generic map (
DATA_WIDTH_A => WIDTH,
DATA_WIDTH_B => WIDTH,
DOA_REG => 0,
DOB_REG => DOB_REG,
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE"
)
port map (
CLKA => user_clk_i,
RSTA => reset_i,
DOA => open,
DOPA => open,
ADDRA => waddr_int,
DIA => di_int,
DIPA => dip_int,
ENA => wen_i,
WEA => wen_int,
REGCEA => '0',
CLKB => user_clk_i,
RSTB => reset_i,
WEB => "0000",
DIB => x"00000000",
DIPB => "0000",
ADDRB => raddr_int,
DOB => do_int,
DOPB => dop_int,
ENB => ren_i,
REGCEB => rce_i
);
end rtl;
| gpl-3.0 | 279f52d6546d855c8eb17f22702c700a | 0.57308 | 3.70529 | false | false | false | false |
timofonic/PHDL | misc/projects/spartan_pcie_board/fpga/lx45t_pinout/ipcore_dir/pcie_core/simulation/dsport/pci_exp_usrapp_tx.vhd | 1 | 5,398 | -------------------------------------------------------------------------------
--
-- (c) Copyright 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Project : Spartan-6 Integrated Block for PCI Express
-- File : pci_exp_usrapp_tx.vhd
-- Description: PCI Express dsport Tx interface.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
entity pci_exp_usrapp_tx is
port (
trn_td : out std_logic_vector (63 downto 0 );
trn_trem_n : out std_logic_vector (7 downto 0 );
trn_tsof_n : out std_logic;
trn_teof_n : out std_logic;
trn_terrfwd_n : out std_logic;
trn_tsrc_rdy_n : out std_logic;
trn_tsrc_dsc_n : out std_logic;
trn_clk : in std_logic;
trn_reset_n : in std_logic;
trn_lnk_up_n : in std_logic;
trn_tdst_rdy_n : in std_logic;
trn_tdst_dsc_n : in std_logic;
trn_tbuf_av : in std_logic_vector (5 downto 0);
rx_tx_read_data : in std_logic_vector(31 downto 0);
rx_tx_read_data_valid : in std_logic;
tx_rx_read_data_valid : out std_logic
);
end pci_exp_usrapp_tx;
architecture rtl of pci_exp_usrapp_tx is
component tests
generic (
test_selector : in string := String'("pio_writeReadBack_test0")
);
port (
trn_td : out std_logic_vector (63 downto 0 );
trn_trem_n : out std_logic_vector (7 downto 0 );
trn_tsof_n : out std_logic;
trn_teof_n : out std_logic;
trn_terrfwd_n : out std_logic;
trn_tsrc_rdy_n : out std_logic;
trn_tsrc_dsc_n : out std_logic;
trn_clk : in std_logic;
trn_reset_n : in std_logic;
trn_lnk_up_n : in std_logic;
trn_tdst_rdy_n : in std_logic;
trn_tdst_dsc_n : in std_logic;
trn_tbuf_av : in std_logic_vector(5 downto 0);
rx_tx_read_data : in std_logic_vector(31 downto 0);
rx_tx_read_data_valid : in std_logic;
tx_rx_read_data_valid : out std_logic
);
end component;
begin
TESTS_INST : tests
generic map (
test_selector => String'("pio_writeReadBack_test0")
)
port map (
trn_td => trn_td,
trn_trem_n => trn_trem_n,
trn_tsof_n => trn_tsof_n,
trn_teof_n => trn_teof_n,
trn_terrfwd_n => trn_terrfwd_n,
trn_tsrc_rdy_n => trn_tsrc_rdy_n,
trn_tsrc_dsc_n => trn_tsrc_dsc_n,
trn_clk => trn_clk,
trn_reset_n => trn_reset_n,
trn_lnk_up_n => trn_lnk_up_n,
trn_tdst_rdy_n => trn_tdst_rdy_n,
trn_tdst_dsc_n => trn_tdst_dsc_n,
trn_tbuf_av => trn_tbuf_av,
rx_tx_read_data => rx_tx_read_data,
rx_tx_read_data_valid => rx_tx_read_data_valid,
tx_rx_read_data_valid => tx_rx_read_data_valid
);
end; -- pci_exp_usrapp_tx
| gpl-3.0 | 7b2594d411d4a6e0c8b271fcbecc99b9 | 0.606891 | 3.491591 | false | false | false | false |
Pinwino/dbg_ohwr | debugger_gw/fmc-delay/top/spec_reset_gen.vhd | 2 | 1,220 | library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.NUMERIC_STD.all;
use work.gencores_pkg.all;
entity spec_reset_gen is
port (
clk_sys_i : in std_logic;
rst_pcie_n_a_i : in std_logic;
rst_button_n_a_i : in std_logic;
rst_n_o : out std_logic
);
end spec_reset_gen;
architecture behavioral of spec_reset_gen is
signal powerup_cnt : unsigned(7 downto 0) := x"00";
signal button_synced_n : std_logic;
signal pcie_synced_n : std_logic;
signal powerup_n : std_logic := '0';
begin -- behavioral
U_EdgeDet_PCIe : gc_sync_ffs port map (
clk_i => clk_sys_i,
rst_n_i => '1',
data_i => rst_pcie_n_a_i,
ppulse_o => pcie_synced_n);
U_Sync_Button : gc_sync_ffs port map (
clk_i => clk_sys_i,
rst_n_i => '1',
data_i => rst_button_n_a_i,
synced_o => button_synced_n);
p_powerup_reset : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if(powerup_cnt /= x"ff") then
powerup_cnt <= powerup_cnt + 1;
powerup_n <= '0';
else
powerup_n <= '1';
end if;
end if;
end process;
rst_n_o <= powerup_n and button_synced_n and (not pcie_synced_n);
end behavioral;
| gpl-3.0 | b7bf4d0c1c546f0d0fa507461c514a50 | 0.578689 | 2.804598 | false | false | false | false |
masaruohashi/tic-tac-toe | uart/unidade_controle_interface_transmissao.vhd | 1 | 1,541 | -- unidade_controle_interface_transmissao.vhd
-- unidade de controle da interface para a transmissao serial
library IEEE;
use IEEE.std_logic_1164.all;
entity unidade_controle_interface_transmissao is
port(
clock: in STD_LOGIC;
reset: in STD_LOGIC;
transmite_dado: in STD_LOGIC;
pronto: in STD_LOGIC;
transmissao_andamento: out STD_LOGIC
);
end;
architecture comportamental of unidade_controle_interface_transmissao is
type Tipo_estado is (inicial, transmite, final); -- estados
signal Eatual, -- estado atual
Eprox: Tipo_estado; -- proximo estado
begin
process (clock, reset) -- memoria de estado
begin
if reset = '1' then
Eatual <= inicial;
elsif CLOCK'event and CLOCK = '1' then
Eatual <= Eprox;
end if;
end process;
process (transmite_dado, pronto, Eatual) -- logica de proximo estado
begin
case Eatual is
when inicial =>
if transmite_dado = '1' then
Eprox <= transmite;
else
Eprox <= inicial;
end if;
when transmite =>
if pronto='1' then
Eprox <= final;
else
Eprox <= transmite;
end if;
when final =>
if transmite_dado = '0' then
Eprox <= inicial;
else
Eprox <= final;
end if;
when others =>
Eprox <= inicial;
end case;
end process;
with Eatual select -- logica de saida (Moore)
transmissao_andamento <=
'0' when inicial,
'1' when transmite,
'0' when final;
end comportamental;
| mit | d8403315c894121ada6454bcee373801 | 0.61843 | 3.971649 | false | false | false | false |
masaruohashi/tic-tac-toe | modem/modem_recepcao.vhd | 1 | 1,463 | -- modem_recepcao.vhd
--
-- componente que modela a recepcao de dados do modem
-- => usar para os testes de simulacao do projeto final
--
-- Labdig (3o quadrimestre de 2017)
library IEEE;
use IEEE.std_logic_1164.all;
entity modem_recepcao is
port ( clock, reset, DTR, RC: in STD_LOGIC;
CD, RD: out STD_LOGIC );
end;
architecture modem_recepcao of modem_recepcao is
type estados_rx is (inicial_rx, em_recepcao);
signal Eatual, Eprox: estados_rx;
begin
-- estado
process (RESET, CLOCK)
begin
if RESET = '1' then
Eatual <= inicial_rx;
elsif CLOCK'event and CLOCK = '1' then
Eatual <= Eprox;
end if;
end process;
-- proximo estado
process (DTR, Eatual)
begin
case Eatual is
when inicial_rx => if DTR='0' then Eprox <= em_recepcao;
else Eprox <= inicial_rx;
end if;
when em_recepcao => if DTR='1' then Eprox <= inicial_rx;
else Eprox <= em_recepcao;
end if;
when others => Eprox <= inicial_rx;
end case;
end process;
-- saidas
with Eatual select
CD <= '0' when em_recepcao, '1' when others;
with Eatual select
RD <= RC when em_recepcao, '0' when others;
end modem_recepcao;
| mit | 26e04679cb040cc642a598a57671a65c | 0.521531 | 4.019231 | false | false | false | false |
masaruohashi/tic-tac-toe | uart/unidade_controle_interface_recepcao.vhd | 1 | 1,805 | -- VHDL da Unidade de Controle
library ieee;
use ieee.std_logic_1164.all;
entity unidade_controle_interface_recepcao is
port(
clock: in std_logic;
reset: in std_logic;
pronto: in std_logic;
recebe_dado: in std_logic;
tem_dado_rec: out std_logic;
habilita_registrador: out std_logic
);
end unidade_controle_interface_recepcao;
architecture exemplo of unidade_controle_interface_recepcao is
type tipo_estado is (inicial, prepara, recebe, final, aguarda);
signal estado : tipo_estado;
begin
process (clock, estado, reset)
begin
if reset = '1' then
estado <= inicial;
elsif (clock'event and clock = '1') then
case estado is
when inicial => -- Aguarda sinal de inicio
if recebe_dado = '1' then
estado <= prepara;
else
estado <= inicial;
end if;
when prepara => -- Espera o final de uma recepção
if pronto = '1' then
estado <= recebe;
else
estado <= prepara;
end if;
when recebe => -- Habilita o registrador no fluxo de dados
estado <= final;
when final =>
estado <= aguarda;
when aguarda => -- Habilita saida para os displays
if recebe_dado = '0' then
estado <= inicial;
else
estado <= aguarda;
end if;
when others => -- Default
estado <= inicial;
end case;
end if;
end process;
-- logica de saída
with estado select
tem_dado_rec <= '1' when final,
'0' when others;
with estado select
habilita_registrador <= '1' when recebe,
'0' when others;
end exemplo;
| mit | 561610b8be4edd76fb639ba33864d944 | 0.547725 | 4.25 | false | false | false | false |
srohrer32/beamformer | hdl/testbench_nearfield.vhd | 1 | 5,540 | ----------------------------------------------------------------------------------
-- Created by Sam Rohrer --
-- Beamforms in the nearfield based on a generic for distance --
-- This is the testbench used for ISim models --
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity testbench_nearfield is
generic(
sample_divisor : integer := 11
);
port(
--sys_clock : in std_logic; -- system clk signal
--swt_distance : in std_logic_vector (4 downto 0); -- switch 0 to 4
--but_reset : in std_logic ; --Button D
pin_dataout : out std_logic_vector (7 downto 0); -- JA 0 to 7
pin_channel : out std_logic_vector (4 downto 0); -- JB 0 to 4
--pin_datain_r : in std_logic_vector (7 downto 0); -- JC 0 to 7
--pin_datain_l : in std_logic_vector (7 downto 0); -- JD 0 to 7
--pin_int : in std_logic; -- JB5
pin_speaker_enable : out std_logic; --JB7
pin_rd : out std_logic --JB6
);
end testbench_nearfield;
architecture Behavioral of testbench_nearfield is
--******************* Signal Processing ***************--
component nearfield_processing is
generic(
divisor : integer := 50; -- difference between system clock 1 us
speed_sound : integer := 13397; -- in inches/second
speaker_distance : integer := 2; -- in inches
sample_period : integer := 22
);
port(
i_datain_r : in std_logic_vector (7 downto 0); -- 8 bit from memory
i_datain_l : in std_logic_vector (7 downto 0); -- 8 bit from memory
i_clock : in std_logic; --
i_distance : in std_logic_vector (4 downto 0); -- Switches determine distance
i_reset : in std_logic ; -- To reset the entire system
i_sampleclock : in std_logic ; -- Rate at which the music is playing
o_speaker_enable : out std_logic; --LDAC enable
o_dataout : out std_logic_vector (7 downto 0); -- 8 bit to be multiplexed
o_channel : out std_logic_vector (4 downto 0); -- 5 bit to select which DAC to enable
o_us_clock : out std_logic
);
end component;
--**************** User Signals ***************--
-- To mimic the input ports
signal test_datain_r : std_logic_vector (7 downto 0) := X"00";
signal test_datain_l : std_logic_vector (7 downto 0) := X"00";
signal sys_clock : std_logic;
signal but_reset : std_logic;
signal pin_int : std_logic;
signal swt_distance : std_logic_vector (4 downto 0) :="00000";
-- Normal signals needed
signal clockpulses : integer range 0 to 2200;
signal us_clockpulses : integer range 0 to 12;
signal sample_clock : std_logic;
signal us_clock : std_logic;
signal sig_datain_r : std_logic_vector (7 downto 0);
signal sig_datain_l : std_logic_vector (7 downto 0);
--**************** End User Signals ***********--
begin
--*************** User Processes **************--
but_reset <= '0', '1' after 100 ns, '0' after 1000 ns;
pin_int <= '0';
swt_distance <= "11000";
-- *************** Test Data Being Generated **********--
generate_data: process (sample_clock)
begin
if (rising_edge(sample_clock)) then
test_datain_r <= test_datain_r + X"11";
test_datain_l <= test_datain_l + X"11";
end if;
end process;
-- **************************************************** --
clock: process
begin
sys_clock <= '0';
wait for 5 ns;
sys_clock <= '1';
wait for 5 ns;
end process;
sampleclock_division : process(but_reset, us_clock)
begin
if (but_reset = '1') then
us_clockpulses <= 0;
sample_clock <= '0';
elsif(rising_edge(us_clock)) then
us_clockpulses <= us_clockpulses + 1 ;
if(us_clockpulses = (sample_divisor-1)) then
sample_clock <= Not sample_clock;
us_clockpulses <= 0;
end if;
end if;
end process;
rd_control : process (but_reset, sys_clock, clockpulses, sample_clock)
begin
if (but_reset = '1' ) then
pin_rd <= '1';
clockpulses <= 0;
elsif (rising_edge(sys_clock)) then
clockpulses <= clockpulses + 1;
if (clockpulses = 0) then
pin_rd <= '0';
elsif (clockpulses = 250) then
pin_rd <= '1';
elsif(pin_int = '0') then
sig_datain_r <= test_datain_r;
sig_datain_l <= test_datain_l;
elsif(rising_edge(sample_clock)) then
clockpulses <= 0;
end if;
end if;
end process;
--*************** End User Processes **********--
--**************** Signal Processing Port Map ***********--
fpga : nearfield_processing
generic map(
divisor => 50,
speed_sound => 13397,
speaker_distance => 2,
sample_period => 22
)
port map(
i_datain_r => sig_datain_r,
i_datain_l => sig_datain_l,
i_clock => sys_clock,
i_distance => swt_distance,
i_reset => but_reset,
i_sampleclock => sample_clock,
o_speaker_enable => pin_speaker_enable,
o_dataout => pin_dataout,
o_channel => pin_channel,
o_us_clock => us_clock
);
end Behavioral; | apache-2.0 | 948b3b3834bf72385a0e694e49324509 | 0.520036 | 3.421865 | false | true | false | false |
NiceCircuits/SUPER_UART | cpld/SUPER_UART.vhd | 1 | 24,796 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.7
-- \ \ Application : sch2hdl
-- / / Filename : SUPER_UART.vhf
-- /___/ /\ Timestamp : 10/21/2017 20:49:12
-- \ \ / \
-- \___\/\___\
--
--Command: sch2hdl -intstyle ise -family xc9500xl -flat -suppress -vhdl D:/OneDrive/super_UART/fpga/SUPER_UART.vhf -w D:/OneDrive/super_UART/fpga/SUPER_UART.sch
--Design Name: SUPER_UART
--Device: xc9500xl
--Purpose:
-- This vhdl netlist is translated from an ECS schematic. It can be
-- synthesized and simulated, but it should not be modified.
--
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity SUPER_UART is
port ( FTDI_DTR_A : in std_logic;
FTDI_DTR_B : in std_logic;
FTDI_TXD_A : in std_logic;
FTDI_TXD_B : in std_logic;
FTDI_TXD_C : in std_logic;
FTDI_TXD_D : in std_logic;
N_OE : in std_logic;
RXD_A : in std_logic;
RXD_B : in std_logic;
RXD_C : in std_logic;
RXD_D : in std_logic;
RXD_D1 : in std_logic;
SR_CLK : in std_logic;
SR_DATA : in std_logic;
SR_LOAD : in std_logic;
CTS_A_OC : out std_logic;
CTS_B_OC : out std_logic;
DTR_A : out std_logic;
DTR_B : out std_logic;
FTDI_RXD_C : out std_logic;
FTDI_RXD_D : out std_logic;
N_BUZZER : out std_logic;
OPTO_EN : out std_logic;
RXD_A_OC : out std_logic;
RXD_B_OC : out std_logic;
TXD_D : out std_logic;
CTS_A : inout std_logic;
CTS_B : inout std_logic;
FTDI_CTS_A : inout std_logic;
FTDI_CTS_B : inout std_logic;
FTDI_RTS_A : inout std_logic;
FTDI_RTS_B : inout std_logic;
FTDI_RXD_A : inout std_logic;
FTDI_RXD_B : inout std_logic);
end SUPER_UART;
entity M2_1E_MXILINX_SUPER_UART is
port ( D0 : in std_logic;
D1 : in std_logic;
E : in std_logic;
S0 : in std_logic;
O : out std_logic);
end M2_1E_MXILINX_SUPER_UART;
architecture BEHAVIORAL of M2_1E_MXILINX_SUPER_UART is
attribute BOX_TYPE : string ;
signal M0 : std_logic;
signal M1 : std_logic;
component AND3
port ( I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND3 : component is "BLACK_BOX";
component AND3B1
port ( I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND3B1 : component is "BLACK_BOX";
component OR2
port ( I0 : in std_logic;
I1 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of OR2 : component is "BLACK_BOX";
begin
I_36_30 : AND3
port map (I0=>D1,
I1=>E,
I2=>S0,
O=>M1);
I_36_31 : AND3B1
port map (I0=>S0,
I1=>E,
I2=>D0,
O=>M0);
I_36_38 : OR2
port map (I0=>M1,
I1=>M0,
O=>O);
end BEHAVIORAL;
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity M2_1_MXILINX_SUPER_UART is
port ( D0 : in std_logic;
D1 : in std_logic;
S0 : in std_logic;
O : out std_logic);
end M2_1_MXILINX_SUPER_UART;
architecture BEHAVIORAL of M2_1_MXILINX_SUPER_UART is
attribute BOX_TYPE : string ;
signal M0 : std_logic;
signal M1 : std_logic;
component AND2B1
port ( I0 : in std_logic;
I1 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND2B1 : component is "BLACK_BOX";
component OR2
port ( I0 : in std_logic;
I1 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of OR2 : component is "BLACK_BOX";
component AND2
port ( I0 : in std_logic;
I1 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND2 : component is "BLACK_BOX";
begin
I_36_7 : AND2B1
port map (I0=>S0,
I1=>D0,
O=>M0);
I_36_8 : OR2
port map (I0=>M1,
I1=>M0,
O=>O);
I_36_9 : AND2
port map (I0=>D1,
I1=>S0,
O=>M1);
end BEHAVIORAL;
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity M4_1E_MXILINX_SUPER_UART is
port ( D0 : in std_logic;
D1 : in std_logic;
D2 : in std_logic;
D3 : in std_logic;
E : in std_logic;
S0 : in std_logic;
S1 : in std_logic;
O : out std_logic);
end M4_1E_MXILINX_SUPER_UART;
architecture BEHAVIORAL of M4_1E_MXILINX_SUPER_UART is
attribute HU_SET : string ;
signal M01 : std_logic;
signal M23 : std_logic;
component M2_1E_MXILINX_SUPER_UART
port ( D0 : in std_logic;
D1 : in std_logic;
E : in std_logic;
S0 : in std_logic;
O : out std_logic);
end component;
component M2_1_MXILINX_SUPER_UART
port ( D0 : in std_logic;
D1 : in std_logic;
S0 : in std_logic;
O : out std_logic);
end component;
attribute HU_SET of U1 : label is "U1_2";
attribute HU_SET of U2 : label is "U2_1";
attribute HU_SET of U3 : label is "U3_0";
begin
U1 : M2_1E_MXILINX_SUPER_UART
port map (D0=>D0,
D1=>D1,
E=>E,
S0=>S0,
O=>M01);
U2 : M2_1E_MXILINX_SUPER_UART
port map (D0=>D2,
D1=>D3,
E=>E,
S0=>S0,
O=>M23);
U3 : M2_1_MXILINX_SUPER_UART
port map (D0=>M01,
D1=>M23,
S0=>S1,
O=>O);
end BEHAVIORAL;
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity OBUFE_MXILINX_SUPER_UART is
port ( E : in std_logic;
I : in std_logic;
O : out std_logic);
end OBUFE_MXILINX_SUPER_UART;
architecture BEHAVIORAL of OBUFE_MXILINX_SUPER_UART is
attribute BOX_TYPE : string ;
signal T : std_logic;
component OBUFT
port ( I : in std_logic;
T : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of OBUFT : component is "BLACK_BOX";
component INV
port ( I : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of INV : component is "BLACK_BOX";
begin
I_36_10 : OBUFT
port map (I=>I,
T=>T,
O=>O);
I_36_12 : INV
port map (I=>E,
O=>T);
end BEHAVIORAL;
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity SR4CE_MXILINX_SUPER_UART is
port ( C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
SLI : in std_logic;
Q0 : out std_logic;
Q1 : out std_logic;
Q2 : out std_logic;
Q3 : out std_logic);
end SR4CE_MXILINX_SUPER_UART;
architecture BEHAVIORAL of SR4CE_MXILINX_SUPER_UART is
attribute BOX_TYPE : string ;
signal Q0_DUMMY : std_logic;
signal Q1_DUMMY : std_logic;
signal Q2_DUMMY : std_logic;
component FDCE
generic( INIT : bit := '0');
port ( C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic;
Q : out std_logic);
end component;
attribute BOX_TYPE of FDCE : component is "BLACK_BOX";
begin
Q0 <= Q0_DUMMY;
Q1 <= Q1_DUMMY;
Q2 <= Q2_DUMMY;
U0 : FDCE
port map (C=>C,
CE=>CE,
CLR=>CLR,
D=>SLI,
Q=>Q0_DUMMY);
U1 : FDCE
port map (C=>C,
CE=>CE,
CLR=>CLR,
D=>Q0_DUMMY,
Q=>Q1_DUMMY);
U2 : FDCE
port map (C=>C,
CE=>CE,
CLR=>CLR,
D=>Q1_DUMMY,
Q=>Q2_DUMMY);
U3 : FDCE
port map (C=>C,
CE=>CE,
CLR=>CLR,
D=>Q2_DUMMY,
Q=>Q3);
end BEHAVIORAL;
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity LD4_MXILINX_SUPER_UART is
port ( D0 : in std_logic;
D1 : in std_logic;
D2 : in std_logic;
D3 : in std_logic;
G : in std_logic;
Q0 : out std_logic;
Q1 : out std_logic;
Q2 : out std_logic;
Q3 : out std_logic);
end LD4_MXILINX_SUPER_UART;
architecture BEHAVIORAL of LD4_MXILINX_SUPER_UART is
attribute BOX_TYPE : string ;
component LD
generic( INIT : bit := '0');
port ( D : in std_logic;
G : in std_logic;
Q : out std_logic);
end component;
attribute BOX_TYPE of LD : component is "BLACK_BOX";
begin
U0 : LD
port map (D=>D0,
G=>G,
Q=>Q0);
U1 : LD
port map (D=>D1,
G=>G,
Q=>Q1);
U2 : LD
port map (D=>D2,
G=>G,
Q=>Q2);
U3 : LD
port map (D=>D3,
G=>G,
Q=>Q3);
end BEHAVIORAL;
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
architecture BEHAVIORAL of SUPER_UART is
attribute BOX_TYPE : string ;
attribute HU_SET : string ;
attribute SLEW : string ;
signal BUZZER_N_EN_RX : std_logic;
signal BUZZER_N_EN_TX : std_logic;
signal I2C_EN_A : std_logic;
signal I2C_EN_B : std_logic;
signal MPSSE_EN_A : std_logic;
signal MPSSE_EN_B : std_logic;
signal N_MPSSE_EN_A : std_logic;
signal N_MPSSE_EN_B : std_logic;
signal RXD_A_INT : std_logic;
signal RXD_B_INT : std_logic;
signal SPY_EN : std_logic;
signal TXD_D_INT : std_logic;
signal XLXN_35 : std_logic;
signal XLXN_46 : std_logic;
signal XLXN_47 : std_logic;
signal XLXN_103 : std_logic;
signal XLXN_124 : std_logic;
signal XLXN_137 : std_logic;
signal XLXN_147 : std_logic;
signal XLXN_149 : std_logic;
signal XLXN_150 : std_logic;
signal XLXN_159 : std_logic;
signal XLXN_160 : std_logic;
signal XLXN_161 : std_logic;
signal XLXN_162 : std_logic;
signal XLXN_168 : std_logic;
signal XLXN_171 : std_logic;
signal XLXN_172 : std_logic;
signal XLXN_230 : std_logic;
signal XLXN_239 : std_logic;
signal XLXN_255 : std_logic;
signal XLXN_269 : std_logic;
signal XLXN_271 : std_logic;
signal XLXN_276 : std_logic;
signal XLXN_284 : std_logic;
signal XLXN_286 : std_logic;
signal XLXN_287 : std_logic;
signal XLXN_288 : std_logic;
signal XLXN_296 : std_logic;
signal XLXN_298 : std_logic;
signal XLXN_303 : std_logic;
signal XLXN_307 : std_logic;
signal XLXN_309 : std_logic;
signal XLXN_312 : std_logic;
signal XLXN_317 : std_logic;
signal XLXN_410 : std_logic;
signal XLXN_412 : std_logic;
signal XLXN_415 : std_logic;
signal XLXN_430 : std_logic;
signal XLXN_460 : std_logic;
signal XLXN_466 : std_logic;
signal XLXN_467 : std_logic;
component IOBUFE
port ( I : in std_logic;
IO : inout std_logic;
O : out std_logic;
E : in std_logic);
end component;
attribute BOX_TYPE of IOBUFE : component is "BLACK_BOX";
component INV
port ( I : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of INV : component is "BLACK_BOX";
component OR2B1
port ( I0 : in std_logic;
I1 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of OR2B1 : component is "BLACK_BOX";
component AND2
port ( I0 : in std_logic;
I1 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND2 : component is "BLACK_BOX";
component LD4_MXILINX_SUPER_UART
port ( D0 : in std_logic;
D1 : in std_logic;
D2 : in std_logic;
D3 : in std_logic;
G : in std_logic;
Q0 : out std_logic;
Q1 : out std_logic;
Q2 : out std_logic;
Q3 : out std_logic);
end component;
component SR4CE_MXILINX_SUPER_UART
port ( C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
SLI : in std_logic;
Q0 : out std_logic;
Q1 : out std_logic;
Q2 : out std_logic;
Q3 : out std_logic);
end component;
component GND
port ( G : out std_logic);
end component;
attribute BOX_TYPE of GND : component is "BLACK_BOX";
component VCC
port ( P : out std_logic);
end component;
attribute BOX_TYPE of VCC : component is "BLACK_BOX";
component OBUFE_MXILINX_SUPER_UART
port ( E : in std_logic;
I : in std_logic;
O : out std_logic);
end component;
component AND2B1
port ( I0 : in std_logic;
I1 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND2B1 : component is "BLACK_BOX";
component AND3B2
port ( I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND3B2 : component is "BLACK_BOX";
component IBUF
port ( I : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of IBUF : component is "BLACK_BOX";
component OBUF
port ( I : in std_logic;
O : out std_logic);
end component;
attribute SLEW of OBUF : component is "SLOW";
attribute BOX_TYPE of OBUF : component is "BLACK_BOX";
component AND4B2
port ( I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND4B2 : component is "BLACK_BOX";
component M4_1E_MXILINX_SUPER_UART
port ( D0 : in std_logic;
D1 : in std_logic;
D2 : in std_logic;
D3 : in std_logic;
E : in std_logic;
S0 : in std_logic;
S1 : in std_logic;
O : out std_logic);
end component;
component M2_1_MXILINX_SUPER_UART
port ( D0 : in std_logic;
D1 : in std_logic;
S0 : in std_logic;
O : out std_logic);
end component;
component AND2B2
port ( I0 : in std_logic;
I1 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND2B2 : component is "BLACK_BOX";
component OR2
port ( I0 : in std_logic;
I1 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of OR2 : component is "BLACK_BOX";
component AND3
port ( I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND3 : component is "BLACK_BOX";
attribute HU_SET of XLXI_49 : label is "XLXI_49_3";
attribute HU_SET of XLXI_50 : label is "XLXI_50_4";
attribute HU_SET of XLXI_53 : label is "XLXI_53_5";
attribute HU_SET of XLXI_54 : label is "XLXI_54_6";
attribute HU_SET of XLXI_57 : label is "XLXI_57_7";
attribute HU_SET of XLXI_95 : label is "XLXI_95_8";
attribute HU_SET of XLXI_104 : label is "XLXI_104_9";
attribute HU_SET of XLXI_108 : label is "XLXI_108_10";
attribute HU_SET of XLXI_116 : label is "XLXI_116_11";
attribute HU_SET of XLXI_154 : label is "XLXI_154_12";
begin
XLXI_7 : IOBUFE
port map (E=>XLXN_230,
I=>RXD_A_INT,
O=>XLXN_124,
IO=>FTDI_RXD_A);
XLXI_12 : INV
port map (I=>MPSSE_EN_A,
O=>N_MPSSE_EN_A);
XLXI_13 : IOBUFE
port map (E=>XLXN_276,
I=>XLXN_46,
O=>XLXN_47,
IO=>FTDI_CTS_A);
XLXI_14 : IOBUFE
port map (E=>XLXN_35,
I=>XLXN_124,
O=>XLXN_46,
IO=>CTS_A);
XLXI_37 : OR2B1
port map (I0=>SPY_EN,
I1=>FTDI_TXD_C,
O=>XLXN_103);
XLXI_46 : AND2
port map (I0=>XLXN_137,
I1=>FTDI_TXD_D,
O=>XLXN_430);
XLXI_47 : OR2B1
port map (I0=>SPY_EN,
I1=>FTDI_TXD_B,
O=>XLXN_137);
XLXI_49 : LD4_MXILINX_SUPER_UART
port map (D0=>XLXN_147,
D1=>XLXN_149,
D2=>XLXN_150,
D3=>XLXN_168,
G=>SR_LOAD,
Q0=>I2C_EN_A,
Q1=>MPSSE_EN_A,
Q2=>I2C_EN_B,
Q3=>MPSSE_EN_B);
XLXI_50 : SR4CE_MXILINX_SUPER_UART
port map (C=>SR_CLK,
CE=>XLXN_172,
CLR=>XLXN_171,
SLI=>SR_DATA,
Q0=>XLXN_147,
Q1=>XLXN_149,
Q2=>XLXN_150,
Q3=>XLXN_168);
XLXI_53 : LD4_MXILINX_SUPER_UART
port map (D0=>XLXN_159,
D1=>XLXN_160,
D2=>XLXN_161,
D3=>XLXN_162,
G=>SR_LOAD,
Q0=>SPY_EN,
Q1=>OPTO_EN,
Q2=>BUZZER_N_EN_TX,
Q3=>BUZZER_N_EN_RX);
XLXI_54 : SR4CE_MXILINX_SUPER_UART
port map (C=>SR_CLK,
CE=>XLXN_172,
CLR=>XLXN_171,
SLI=>XLXN_168,
Q0=>XLXN_159,
Q1=>XLXN_160,
Q2=>XLXN_161,
Q3=>XLXN_162);
XLXI_55 : GND
port map (G=>XLXN_171);
XLXI_56 : VCC
port map (P=>XLXN_172);
XLXI_57 : OBUFE_MXILINX_SUPER_UART
port map (E=>XLXN_230,
I=>RXD_A_INT,
O=>FTDI_RTS_A);
XLXI_75 : AND2B1
port map (I0=>N_OE,
I1=>MPSSE_EN_A,
O=>XLXN_230);
XLXI_80 : AND3B2
port map (I0=>N_OE,
I1=>I2C_EN_A,
I2=>MPSSE_EN_A,
O=>XLXN_35);
XLXI_81 : IBUF
port map (I=>RXD_A,
O=>RXD_A_INT);
XLXI_82 : OBUF
port map (I=>XLXN_239,
O=>RXD_A_OC);
XLXI_83 : AND4B2
port map (I0=>XLXN_124,
I1=>N_OE,
I2=>MPSSE_EN_A,
I3=>I2C_EN_A,
O=>XLXN_239);
XLXI_87 : OBUF
port map (I=>XLXN_255,
O=>CTS_A_OC);
XLXI_92 : AND4B2
port map (I0=>FTDI_TXD_A,
I1=>N_OE,
I2=>MPSSE_EN_A,
I3=>I2C_EN_A,
O=>XLXN_255);
XLXI_95 : M4_1E_MXILINX_SUPER_UART
port map (D0=>XLXN_47,
D1=>FTDI_DTR_A,
D2=>XLXN_269,
D3=>XLXN_269,
E=>XLXN_269,
S0=>N_MPSSE_EN_A,
S1=>N_OE,
O=>XLXN_271);
XLXI_96 : OBUF
port map (I=>XLXN_271,
O=>DTR_A);
XLXI_97 : VCC
port map (P=>XLXN_269);
XLXI_100 : IOBUFE
port map (E=>XLXN_312,
I=>XLXN_286,
O=>XLXN_298,
IO=>FTDI_CTS_B);
XLXI_101 : INV
port map (I=>MPSSE_EN_B,
O=>N_MPSSE_EN_B);
XLXI_102 : IOBUFE
port map (E=>XLXN_288,
I=>RXD_B_INT,
O=>XLXN_287,
IO=>FTDI_RXD_B);
XLXI_103 : AND2B1
port map (I0=>N_OE,
I1=>MPSSE_EN_B,
O=>XLXN_288);
XLXI_104 : OBUFE_MXILINX_SUPER_UART
port map (E=>XLXN_288,
I=>RXD_B_INT,
O=>FTDI_RTS_B);
XLXI_105 : AND4B2
port map (I0=>XLXN_287,
I1=>N_OE,
I2=>MPSSE_EN_B,
I3=>I2C_EN_B,
O=>XLXN_296);
XLXI_106 : OBUF
port map (I=>XLXN_296,
O=>RXD_B_OC);
XLXI_107 : AND4B2
port map (I0=>FTDI_TXD_B,
I1=>N_OE,
I2=>MPSSE_EN_B,
I3=>I2C_EN_B,
O=>XLXN_303);
XLXI_108 : M4_1E_MXILINX_SUPER_UART
port map (D0=>XLXN_298,
D1=>FTDI_DTR_B,
D2=>XLXN_307,
D3=>XLXN_307,
E=>XLXN_307,
S0=>N_MPSSE_EN_B,
S1=>N_OE,
O=>XLXN_309);
XLXI_109 : VCC
port map (P=>XLXN_307);
XLXI_110 : OBUF
port map (I=>XLXN_309,
O=>DTR_B);
XLXI_111 : OBUF
port map (I=>XLXN_303,
O=>CTS_B_OC);
XLXI_112 : IBUF
port map (I=>RXD_B,
O=>XLXN_317);
XLXI_113 : IOBUFE
port map (E=>XLXN_284,
I=>XLXN_287,
O=>XLXN_286,
IO=>CTS_B);
XLXI_115 : AND3B2
port map (I0=>N_OE,
I1=>I2C_EN_B,
I2=>MPSSE_EN_B,
O=>XLXN_284);
XLXI_116 : M2_1_MXILINX_SUPER_UART
port map (D0=>XLXN_317,
D1=>RXD_D,
S0=>SPY_EN,
O=>RXD_B_INT);
XLXI_118 : AND2B2
port map (I0=>N_OE,
I1=>MPSSE_EN_B,
O=>XLXN_312);
XLXI_119 : AND2B2
port map (I0=>N_OE,
I1=>MPSSE_EN_A,
O=>XLXN_276);
XLXI_154 : M4_1E_MXILINX_SUPER_UART
port map (D0=>RXD_C,
D1=>TXD_D_INT,
D2=>XLXN_412,
D3=>XLXN_412,
E=>XLXN_412,
S0=>SPY_EN,
S1=>N_OE,
O=>XLXN_410);
XLXI_157 : OBUF
port map (I=>XLXN_410,
O=>FTDI_RXD_C);
XLXI_158 : VCC
port map (P=>XLXN_412);
XLXI_159 : OR2
port map (I0=>N_OE,
I1=>XLXN_430,
O=>TXD_D_INT);
XLXI_160 : OR2
port map (I0=>XLXN_460,
I1=>N_OE,
O=>XLXN_415);
XLXI_162 : OBUF
port map (I=>XLXN_415,
O=>FTDI_RXD_D);
XLXI_168 : OBUF
port map (I=>TXD_D_INT,
O=>TXD_D);
XLXI_178 : AND3
port map (I0=>XLXN_103,
I1=>RXD_D1,
I2=>RXD_D1,
O=>XLXN_460);
XLXI_180 : OR2
port map (I0=>BUZZER_N_EN_RX,
I1=>RXD_D1,
O=>XLXN_466);
XLXI_181 : OR2
port map (I0=>BUZZER_N_EN_TX,
I1=>FTDI_TXD_D,
O=>XLXN_467);
XLXI_182 : AND2
port map (I0=>XLXN_467,
I1=>XLXN_466,
O=>N_BUZZER);
end BEHAVIORAL;
| unlicense | 56299f49c30a6194230c265cdacb8732 | 0.463059 | 3.312759 | false | false | false | false |
masaruohashi/tic-tac-toe | interface_modem/unidade_controle_modem_recepcao.vhd | 1 | 2,124 | -- VHDL da Unidade de Controle da transmissão
library ieee;
use ieee.std_logic_1164.all;
entity unidade_controle_modem_recepcao is
port(clock : in std_logic;
reset : in std_logic;
liga : in std_logic;
CD : in std_logic;
RD : in std_logic;
DTR : out std_logic;
temDadoRecebido : out std_logic;
saida : out std_logic_vector(3 downto 0)); -- controle de estados
end unidade_controle_modem_recepcao;
architecture unidade_controle of unidade_controle_modem_recepcao is
type tipo_estado is (inicial, recepcao, final, desabilitado);
signal estado : tipo_estado;
begin
process (clock, estado, reset)
begin
if liga = '0' then
estado <= desabilitado;
elsif reset = '1' then
estado <= inicial;
elsif (clock'event and clock = '1') then
case estado is
when inicial => -- Aguarda sinal de inicio
if CD = '0' then -- Ativo em baixo
estado <= recepcao;
end if;
when recepcao => -- Recebe o sinal do modem
if CD = '1' then -- Ativo em baixo
estado <= final;
end if;
when final => -- Aguarda desativação do sinal RD
if RD = '1' then -- Ativo em baixo
estado <= inicial;
end if;
when desabilitado => -- Circuito desabilitado
if liga = '1' then
estado <= inicial;
end if;
end case;
end if;
end process;
process (estado)
begin
case estado is
when inicial =>
DTR <= '0';
saida <= "0000";
temDadoRecebido <= '0';
when recepcao =>
DTR <= '0';
saida <= "0001";
temDadoRecebido <= '1';
when final =>
DTR <= '0';
saida <= "0010";
temDadoRecebido <= '0';
when desabilitado =>
DTR <= '1';
saida <= "1111";
temDadoRecebido <= '0';
end case;
end process;
end unidade_controle; | mit | d7ee35d834ec471ae41aee6be098769e | 0.51108 | 4.118447 | false | false | false | false |
masaruohashi/tic-tac-toe | uart/registrador_deslocamento_recepcao.vhd | 1 | 748 | -- VHDL de um Registrador de Deslocamento para a direita.
library ieee;
use ieee.std_logic_1164.all;
entity registrador_deslocamento_recepcao is
port(
clock : in std_logic;
enable : in std_logic;
shift : in std_logic;
RIN : in std_logic;
saida : out std_logic_vector(11 downto 0)
);
end registrador_deslocamento_recepcao;
architecture exemplo of registrador_deslocamento_recepcao is
signal IQ : std_logic_vector(11 downto 0);
begin
process (clock, shift, IQ)
begin
if (clock'event and clock = '1') then
if (shift = '1' and enable = '1') then
IQ <= RIN & IQ(11 downto 1);
end if;
end if;
saida <= IQ;
end process;
end exemplo;
| mit | bbe97841f36c52d1b8cdee437d8c5414 | 0.613636 | 3.47907 | false | false | false | false |
timofonic/PHDL | misc/projects/spartan_pcie_board/fpga/lx45t_pinout/ipcore_dir/pcie_core/example_design/xilinx_pcie_1_1_ep_s6.vhd | 1 | 31,136 | -------------------------------------------------------------------------------
--
-- (c) Copyright 2008, 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Project : Spartan-6 Integrated Block for PCI Express
-- File : xilinx_pcie_1_1_ep_s6.vhd
-- Description: PCI Express Endpoint example FPGA design
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_bit.all;
library unisim;
use unisim.VCOMPONENTS.all;
entity xilinx_pcie_1_1_ep_s6 is
generic
(
FAST_TRAIN : boolean := FALSE
);
port
(
pci_exp_txp : out std_logic;
pci_exp_txn : out std_logic;
pci_exp_rxp : in std_logic;
pci_exp_rxn : in std_logic;
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_reset_n : in std_logic;
led_0 : out std_logic;
led_1 : out std_logic;
led_2 : out std_logic
);
end xilinx_pcie_1_1_ep_s6;
architecture rtl of xilinx_pcie_1_1_ep_s6 is
-------------------------
-- Component declarations
-------------------------
component pcie_app_s6 is
port (
trn_clk : in std_logic;
trn_reset_n : in std_logic;
trn_lnk_up_n : in std_logic;
trn_tbuf_av : in std_logic_vector(5 downto 0);
trn_tcfg_req_n : in std_logic;
trn_terr_drop_n : in std_logic;
trn_tdst_rdy_n : in std_logic;
trn_td : out std_logic_vector(31 downto 0);
trn_tsof_n : out std_logic;
trn_teof_n : out std_logic;
trn_tsrc_rdy_n : out std_logic;
trn_tsrc_dsc_n : out std_logic;
trn_terrfwd_n : out std_logic;
trn_tcfg_gnt_n : out std_logic;
trn_tstr_n : out std_logic;
trn_rd : in std_logic_vector(31 downto 0);
trn_rsof_n : in std_logic;
trn_reof_n : in std_logic;
trn_rsrc_rdy_n : in std_logic;
trn_rsrc_dsc_n : in std_logic;
trn_rerrfwd_n : in std_logic;
trn_rbar_hit_n : in std_logic_vector(6 downto 0);
trn_rdst_rdy_n : out std_logic;
trn_rnp_ok_n : out std_logic;
trn_fc_cpld : in std_logic_vector(11 downto 0);
trn_fc_cplh : in std_logic_vector(7 downto 0);
trn_fc_npd : in std_logic_vector(11 downto 0);
trn_fc_nph : in std_logic_vector(7 downto 0);
trn_fc_pd : in std_logic_vector(11 downto 0);
trn_fc_ph : in std_logic_vector(7 downto 0);
trn_fc_sel : out std_logic_vector(2 downto 0);
cfg_do : in std_logic_vector(31 downto 0);
cfg_rd_wr_done_n : in std_logic;
cfg_dwaddr : out std_logic_vector(9 downto 0);
cfg_rd_en_n : out std_logic;
cfg_err_cor_n : out std_logic;
cfg_err_ur_n : out std_logic;
cfg_err_ecrc_n : out std_logic;
cfg_err_cpl_timeout_n : out std_logic;
cfg_err_cpl_abort_n : out std_logic;
cfg_err_posted_n : out std_logic;
cfg_err_locked_n : out std_logic;
cfg_err_tlp_cpl_header : out std_logic_vector(47 downto 0);
cfg_err_cpl_rdy_n : in std_logic;
cfg_interrupt_n : out std_logic;
cfg_interrupt_rdy_n : in std_logic;
cfg_interrupt_assert_n : out std_logic;
cfg_interrupt_di : out std_logic_vector(7 downto 0);
cfg_interrupt_do : in std_logic_vector(7 downto 0);
cfg_interrupt_mmenable : in std_logic_vector(2 downto 0);
cfg_interrupt_msienable : in std_logic;
cfg_turnoff_ok_n : out std_logic;
cfg_to_turnoff_n : in std_logic;
cfg_trn_pending_n : out std_logic;
cfg_pm_wake_n : out std_logic;
cfg_bus_number : in std_logic_vector(7 downto 0);
cfg_device_number : in std_logic_vector(4 downto 0);
cfg_function_number : in std_logic_vector(2 downto 0);
cfg_status : in std_logic_vector(15 downto 0);
cfg_command : in std_logic_vector(15 downto 0);
cfg_dstatus : in std_logic_vector(15 downto 0);
cfg_dcommand : in std_logic_vector(15 downto 0);
cfg_lstatus : in std_logic_vector(15 downto 0);
cfg_lcommand : in std_logic_vector(15 downto 0);
cfg_pcie_link_state_n : in std_logic_vector(2 downto 0);
cfg_dsn : out std_logic_vector(63 downto 0)
);
end component pcie_app_s6;
component pcie_core is
generic (
TL_TX_RAM_RADDR_LATENCY : integer := 0;
TL_TX_RAM_RDATA_LATENCY : integer := 2;
TL_RX_RAM_RADDR_LATENCY : integer := 0;
TL_RX_RAM_RDATA_LATENCY : integer := 2;
TL_RX_RAM_WRITE_LATENCY : integer := 0;
VC0_TX_LASTPACKET : integer := 14;
VC0_RX_RAM_LIMIT : bit_vector := x"7FF";
VC0_TOTAL_CREDITS_PH : integer := 32;
VC0_TOTAL_CREDITS_PD : integer := 211;
VC0_TOTAL_CREDITS_NPH : integer := 8;
VC0_TOTAL_CREDITS_CH : integer := 40;
VC0_TOTAL_CREDITS_CD : integer := 211;
VC0_CPL_INFINITE : boolean := TRUE;
BAR0 : bit_vector := x"FFFFFC00";
BAR1 : bit_vector := x"FFFFC000";
BAR2 : bit_vector := x"FF000000";
BAR3 : bit_vector := x"00000000";
BAR4 : bit_vector := x"00000000";
BAR5 : bit_vector := x"00000000";
EXPANSION_ROM : bit_vector := "0000000000000000000000";
DISABLE_BAR_FILTERING : boolean := FALSE;
DISABLE_ID_CHECK : boolean := FALSE;
TL_TFC_DISABLE : boolean := FALSE;
TL_TX_CHECKS_DISABLE : boolean := FALSE;
USR_CFG : boolean := FALSE;
USR_EXT_CFG : boolean := FALSE;
DEV_CAP_MAX_PAYLOAD_SUPPORTED : integer := 2;
CLASS_CODE : bit_vector := x"050000";
CARDBUS_CIS_POINTER : bit_vector := x"00000000";
PCIE_CAP_CAPABILITY_VERSION : bit_vector := x"1";
PCIE_CAP_DEVICE_PORT_TYPE : bit_vector := x"0";
PCIE_CAP_SLOT_IMPLEMENTED : boolean := FALSE;
PCIE_CAP_INT_MSG_NUM : bit_vector := "00000";
DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT : integer := 0;
DEV_CAP_EXT_TAG_SUPPORTED : boolean := FALSE;
DEV_CAP_ENDPOINT_L0S_LATENCY : integer := 7;
DEV_CAP_ENDPOINT_L1_LATENCY : integer := 7;
SLOT_CAP_ATT_BUTTON_PRESENT : boolean := FALSE;
SLOT_CAP_ATT_INDICATOR_PRESENT : boolean := FALSE;
SLOT_CAP_POWER_INDICATOR_PRESENT : boolean := FALSE;
DEV_CAP_ROLE_BASED_ERROR : boolean := TRUE;
LINK_CAP_ASPM_SUPPORT : integer := 1;
LINK_CAP_L0S_EXIT_LATENCY : integer := 7;
LINK_CAP_L1_EXIT_LATENCY : integer := 7;
LL_ACK_TIMEOUT : bit_vector := x"00B7";
LL_ACK_TIMEOUT_EN : boolean := FALSE;
LL_REPLAY_TIMEOUT : bit_vector := x"0204";
LL_REPLAY_TIMEOUT_EN : boolean := FALSE;
MSI_CAP_MULTIMSGCAP : integer := 0;
MSI_CAP_MULTIMSG_EXTENSION : integer := 0;
LINK_STATUS_SLOT_CLOCK_CONFIG : boolean := FALSE;
PLM_AUTO_CONFIG : boolean := FALSE;
FAST_TRAIN : boolean := FALSE;
ENABLE_RX_TD_ECRC_TRIM : boolean := FALSE;
DISABLE_SCRAMBLING : boolean := FALSE;
PM_CAP_VERSION : integer := 3;
PM_CAP_PME_CLOCK : boolean := FALSE;
PM_CAP_DSI : boolean := FALSE;
PM_CAP_AUXCURRENT : integer := 0;
PM_CAP_D1SUPPORT : boolean := TRUE;
PM_CAP_D2SUPPORT : boolean := TRUE;
PM_CAP_PMESUPPORT : bit_vector := x"0F";
PM_DATA0 : bit_vector := x"00";
PM_DATA_SCALE0 : bit_vector := x"0";
PM_DATA1 : bit_vector := x"00";
PM_DATA_SCALE1 : bit_vector := x"0";
PM_DATA2 : bit_vector := x"00";
PM_DATA_SCALE2 : bit_vector := x"0";
PM_DATA3 : bit_vector := x"00";
PM_DATA_SCALE3 : bit_vector := x"0";
PM_DATA4 : bit_vector := x"00";
PM_DATA_SCALE4 : bit_vector := x"0";
PM_DATA5 : bit_vector := x"00";
PM_DATA_SCALE5 : bit_vector := x"0";
PM_DATA6 : bit_vector := x"00";
PM_DATA_SCALE6 : bit_vector := x"0";
PM_DATA7 : bit_vector := x"00";
PM_DATA_SCALE7 : bit_vector := x"0";
PCIE_GENERIC : bit_vector := "000011101111";
GTP_SEL : integer := 0;
CFG_VEN_ID : std_logic_vector(15 downto 0) := x"10EE";
CFG_DEV_ID : std_logic_vector(15 downto 0) := x"0007";
CFG_REV_ID : std_logic_vector(7 downto 0) := x"00";
CFG_SUBSYS_VEN_ID : std_logic_vector(15 downto 0) := x"10EE";
CFG_SUBSYS_ID : std_logic_vector(15 downto 0) := x"0007";
REF_CLK_FREQ : integer := 1
);
port (
-- PCI Express Fabric Interface
pci_exp_txp : out std_logic;
pci_exp_txn : out std_logic;
pci_exp_rxp : in std_logic;
pci_exp_rxn : in std_logic;
-- Transaction (TRN) Interface
trn_lnk_up_n : out std_logic;
-- Tx
trn_td : in std_logic_vector(31 downto 0);
trn_tsof_n : in std_logic;
trn_teof_n : in std_logic;
trn_tsrc_rdy_n : in std_logic;
trn_tdst_rdy_n : out std_logic;
trn_terr_drop_n : out std_logic;
trn_tsrc_dsc_n : in std_logic;
trn_terrfwd_n : in std_logic;
trn_tbuf_av : out std_logic_vector(5 downto 0);
trn_tstr_n : in std_logic;
trn_tcfg_req_n : out std_logic;
trn_tcfg_gnt_n : in std_logic;
-- Rx
trn_rd : out std_logic_vector(31 downto 0);
trn_rsof_n : out std_logic;
trn_reof_n : out std_logic;
trn_rsrc_rdy_n : out std_logic;
trn_rsrc_dsc_n : out std_logic;
trn_rdst_rdy_n : in std_logic;
trn_rerrfwd_n : out std_logic;
trn_rnp_ok_n : in std_logic;
trn_rbar_hit_n : out std_logic_vector(6 downto 0);
trn_fc_sel : in std_logic_vector(2 downto 0);
trn_fc_nph : out std_logic_vector(7 downto 0);
trn_fc_npd : out std_logic_vector(11 downto 0);
trn_fc_ph : out std_logic_vector(7 downto 0);
trn_fc_pd : out std_logic_vector(11 downto 0);
trn_fc_cplh : out std_logic_vector(7 downto 0);
trn_fc_cpld : out std_logic_vector(11 downto 0);
-- Host (CFG) Interface
cfg_do : out std_logic_vector(31 downto 0);
cfg_rd_wr_done_n : out std_logic;
cfg_dwaddr : in std_logic_vector(9 downto 0);
cfg_rd_en_n : in std_logic;
cfg_err_ur_n : in std_logic;
cfg_err_cor_n : in std_logic;
cfg_err_ecrc_n : in std_logic;
cfg_err_cpl_timeout_n : in std_logic;
cfg_err_cpl_abort_n : in std_logic;
cfg_err_posted_n : in std_logic;
cfg_err_locked_n : in std_logic;
cfg_err_tlp_cpl_header : in std_logic_vector(47 downto 0);
cfg_err_cpl_rdy_n : out std_logic;
cfg_interrupt_n : in std_logic;
cfg_interrupt_rdy_n : out std_logic;
cfg_interrupt_assert_n : in std_logic;
cfg_interrupt_do : out std_logic_vector(7 downto 0);
cfg_interrupt_di : in std_logic_vector(7 downto 0);
cfg_interrupt_mmenable : out std_logic_vector(2 downto 0);
cfg_interrupt_msienable : out std_logic;
cfg_turnoff_ok_n : in std_logic;
cfg_to_turnoff_n : out std_logic;
cfg_pm_wake_n : in std_logic;
cfg_pcie_link_state_n : out std_logic_vector(2 downto 0);
cfg_trn_pending_n : in std_logic;
cfg_dsn : in std_logic_vector(63 downto 0);
cfg_bus_number : out std_logic_vector(7 downto 0);
cfg_device_number : out std_logic_vector(4 downto 0);
cfg_function_number : out std_logic_vector(2 downto 0);
cfg_status : out std_logic_vector(15 downto 0);
cfg_command : out std_logic_vector(15 downto 0);
cfg_dstatus : out std_logic_vector(15 downto 0);
cfg_dcommand : out std_logic_vector(15 downto 0);
cfg_lstatus : out std_logic_vector(15 downto 0);
cfg_lcommand : out std_logic_vector(15 downto 0);
-- System Interface
sys_clk : in std_logic;
sys_reset_n : in std_logic;
trn_clk : out std_logic;
trn_reset_n : out std_logic;
received_hot_reset : out std_logic
);
end component pcie_core;
----------------------
-- Signal declarations
----------------------
-- Common
signal trn_clk : std_logic;
signal trn_reset_n : std_logic;
signal trn_lnk_up_n : std_logic;
-- Tx
signal trn_tbuf_av : std_logic_vector(5 downto 0);
signal trn_tcfg_req_n : std_logic;
signal trn_terr_drop_n : std_logic;
signal trn_tdst_rdy_n : std_logic;
signal trn_td : std_logic_vector(31 downto 0);
signal trn_tsof_n : std_logic;
signal trn_teof_n : std_logic;
signal trn_tsrc_rdy_n : std_logic;
signal trn_tsrc_dsc_n : std_logic;
signal trn_terrfwd_n : std_logic;
signal trn_tcfg_gnt_n : std_logic;
signal trn_tstr_n : std_logic;
-- Rx
signal trn_rd : std_logic_vector(31 downto 0);
signal trn_rsof_n : std_logic;
signal trn_reof_n : std_logic;
signal trn_rsrc_rdy_n : std_logic;
signal trn_rsrc_dsc_n : std_logic;
signal trn_rerrfwd_n : std_logic;
signal trn_rbar_hit_n : std_logic_vector(6 downto 0);
signal trn_rdst_rdy_n : std_logic;
signal trn_rnp_ok_n : std_logic;
-- Flow Control
signal trn_fc_cpld : std_logic_vector(11 downto 0);
signal trn_fc_cplh : std_logic_vector(7 downto 0);
signal trn_fc_npd : std_logic_vector(11 downto 0);
signal trn_fc_nph : std_logic_vector(7 downto 0);
signal trn_fc_pd : std_logic_vector(11 downto 0);
signal trn_fc_ph : std_logic_vector(7 downto 0);
signal trn_fc_sel : std_logic_vector(2 downto 0);
-- Config
signal cfg_dsn : std_logic_vector(63 downto 0);
signal cfg_do : std_logic_vector(31 downto 0);
signal cfg_rd_wr_done_n : std_logic;
signal cfg_dwaddr : std_logic_vector(9 downto 0);
signal cfg_rd_en_n : std_logic;
-- Error signaling
signal cfg_err_cor_n : std_logic;
signal cfg_err_ur_n : std_logic;
signal cfg_err_ecrc_n : std_logic;
signal cfg_err_cpl_timeout_n : std_logic;
signal cfg_err_cpl_abort_n : std_logic;
signal cfg_err_posted_n : std_logic;
signal cfg_err_locked_n : std_logic;
signal cfg_err_tlp_cpl_header : std_logic_vector(47 downto 0);
signal cfg_err_cpl_rdy_n : std_logic;
-- Interrupt signaling
signal cfg_interrupt_n : std_logic;
signal cfg_interrupt_rdy_n : std_logic;
signal cfg_interrupt_assert_n : std_logic;
signal cfg_interrupt_di : std_logic_vector(7 downto 0);
signal cfg_interrupt_do : std_logic_vector(7 downto 0);
signal cfg_interrupt_mmenable : std_logic_vector(2 downto 0);
signal cfg_interrupt_msienable : std_logic;
-- Power management signaling
signal cfg_turnoff_ok_n : std_logic;
signal cfg_to_turnoff_n : std_logic;
signal cfg_trn_pending_n : std_logic;
signal cfg_pm_wake_n : std_logic;
-- System configuration and status
signal cfg_bus_number : std_logic_vector(7 downto 0);
signal cfg_device_number : std_logic_vector(4 downto 0);
signal cfg_function_number : std_logic_vector(2 downto 0);
signal cfg_status : std_logic_vector(15 downto 0);
signal cfg_command : std_logic_vector(15 downto 0);
signal cfg_dstatus : std_logic_vector(15 downto 0);
signal cfg_dcommand : std_logic_vector(15 downto 0);
signal cfg_lstatus : std_logic_vector(15 downto 0);
signal cfg_lcommand : std_logic_vector(15 downto 0);
signal cfg_pcie_link_state_n : std_logic_vector(2 downto 0);
-- System (SYS) Interface
signal sys_clk_c : std_logic;
signal sys_reset_n_c : std_logic;
begin
---------------------------------------------------------
-- Clock Input Buffer for differential system clock
---------------------------------------------------------
refclk_ibuf : IBUFDS
port map
(
O => sys_clk_c,
I => sys_clk_p,
IB => sys_clk_n
);
---------------------------------------------------------
-- Input buffer for system reset signal
---------------------------------------------------------
sys_reset_n_ibuf : IBUF
port map
(
O => sys_reset_n_c,
I => sys_reset_n
);
---------------------------------------------------------
-- Output buffers for diagnostic LEDs
---------------------------------------------------------
led_0_obuf : OBUF
port map
(
O => led_0,
I => sys_reset_n_c
);
led_1_obuf : OBUF
port map
(
O => led_1,
I => trn_reset_n
);
led_2_obuf : OBUF
port map
(
O => led_2,
I => trn_lnk_up_n
);
---------------------------------------------------------
-- User application
---------------------------------------------------------
app : pcie_app_s6
port map
(
-- Transaction (TRN) Interface
-- Common lock & reset
trn_clk => trn_clk,
trn_reset_n => trn_reset_n,
trn_lnk_up_n => trn_lnk_up_n,
-- Common flow control
trn_fc_cpld => trn_fc_cpld,
trn_fc_cplh => trn_fc_cplh,
trn_fc_npd => trn_fc_npd,
trn_fc_nph => trn_fc_nph,
trn_fc_pd => trn_fc_pd,
trn_fc_ph => trn_fc_ph,
trn_fc_sel => trn_fc_sel,
-- Transaction Tx
trn_tbuf_av => trn_tbuf_av,
trn_tcfg_req_n => trn_tcfg_req_n,
trn_terr_drop_n => trn_terr_drop_n,
trn_tdst_rdy_n => trn_tdst_rdy_n,
trn_td => trn_td,
trn_tsof_n => trn_tsof_n,
trn_teof_n => trn_teof_n,
trn_tsrc_rdy_n => trn_tsrc_rdy_n,
trn_tsrc_dsc_n => trn_tsrc_dsc_n,
trn_terrfwd_n => trn_terrfwd_n,
trn_tcfg_gnt_n => trn_tcfg_gnt_n,
trn_tstr_n => trn_tstr_n,
-- Transaction Rx
trn_rd => trn_rd,
trn_rsof_n => trn_rsof_n,
trn_reof_n => trn_reof_n,
trn_rsrc_rdy_n => trn_rsrc_rdy_n,
trn_rsrc_dsc_n => trn_rsrc_dsc_n,
trn_rerrfwd_n => trn_rerrfwd_n,
trn_rbar_hit_n => trn_rbar_hit_n,
trn_rdst_rdy_n => trn_rdst_rdy_n,
trn_rnp_ok_n => trn_rnp_ok_n,
-- Configuration (CFG) Interface
-- Configuration space access
cfg_do => cfg_do,
cfg_rd_wr_done_n => cfg_rd_wr_done_n,
cfg_dwaddr => cfg_dwaddr,
cfg_rd_en_n => cfg_rd_en_n,
-- Error signaling
cfg_err_cor_n => cfg_err_cor_n,
cfg_err_ur_n => cfg_err_ur_n,
cfg_err_ecrc_n => cfg_err_ecrc_n,
cfg_err_cpl_timeout_n => cfg_err_cpl_timeout_n,
cfg_err_cpl_abort_n => cfg_err_cpl_abort_n,
cfg_err_posted_n => cfg_err_posted_n,
cfg_err_locked_n => cfg_err_locked_n,
cfg_err_tlp_cpl_header => cfg_err_tlp_cpl_header,
cfg_err_cpl_rdy_n => cfg_err_cpl_rdy_n,
-- Interrupt generation
cfg_interrupt_n => cfg_interrupt_n,
cfg_interrupt_rdy_n => cfg_interrupt_rdy_n,
cfg_interrupt_assert_n => cfg_interrupt_assert_n,
cfg_interrupt_di => cfg_interrupt_di,
cfg_interrupt_do => cfg_interrupt_do,
cfg_interrupt_mmenable => cfg_interrupt_mmenable,
cfg_interrupt_msienable => cfg_interrupt_msienable,
-- Power managemnt signaling
cfg_turnoff_ok_n => cfg_turnoff_ok_n,
cfg_to_turnoff_n => cfg_to_turnoff_n,
cfg_trn_pending_n => cfg_trn_pending_n,
cfg_pm_wake_n => cfg_pm_wake_n,
-- System configuration and status
cfg_bus_number => cfg_bus_number,
cfg_device_number => cfg_device_number,
cfg_function_number => cfg_function_number,
cfg_status => cfg_status,
cfg_command => cfg_command,
cfg_dstatus => cfg_dstatus,
cfg_dcommand => cfg_dcommand,
cfg_lstatus => cfg_lstatus,
cfg_lcommand => cfg_lcommand,
cfg_pcie_link_state_n => cfg_pcie_link_state_n,
cfg_dsn => cfg_dsn
);
pcie_core_i : pcie_core generic map
(
FAST_TRAIN => FAST_TRAIN
)
port map (
-- PCI Express (PCI_EXP) Fabric Interface
pci_exp_txp => pci_exp_txp,
pci_exp_txn => pci_exp_txn,
pci_exp_rxp => pci_exp_rxp,
pci_exp_rxn => pci_exp_rxn,
-- Transaction (TRN) Interface
-- Common clock & reset
trn_lnk_up_n => trn_lnk_up_n,
trn_clk => trn_clk,
trn_reset_n => trn_reset_n,
-- Common flow control
trn_fc_sel => trn_fc_sel,
trn_fc_nph => trn_fc_nph,
trn_fc_npd => trn_fc_npd,
trn_fc_ph => trn_fc_ph,
trn_fc_pd => trn_fc_pd,
trn_fc_cplh => trn_fc_cplh,
trn_fc_cpld => trn_fc_cpld,
-- Transaction Tx
trn_td => trn_td,
trn_tsof_n => trn_tsof_n,
trn_teof_n => trn_teof_n,
trn_tsrc_rdy_n => trn_tsrc_rdy_n,
trn_tdst_rdy_n => trn_tdst_rdy_n,
trn_terr_drop_n => trn_terr_drop_n,
trn_tsrc_dsc_n => trn_tsrc_dsc_n,
trn_terrfwd_n => trn_terrfwd_n,
trn_tbuf_av => trn_tbuf_av,
trn_tstr_n => trn_tstr_n,
trn_tcfg_req_n => trn_tcfg_req_n,
trn_tcfg_gnt_n => trn_tcfg_gnt_n,
-- Transaction Rx
trn_rd => trn_rd,
trn_rsof_n => trn_rsof_n,
trn_reof_n => trn_reof_n,
trn_rsrc_rdy_n => trn_rsrc_rdy_n,
trn_rsrc_dsc_n => trn_rsrc_dsc_n,
trn_rdst_rdy_n => trn_rdst_rdy_n,
trn_rerrfwd_n => trn_rerrfwd_n,
trn_rnp_ok_n => trn_rnp_ok_n,
trn_rbar_hit_n => trn_rbar_hit_n,
-- Configuration (CFG) Interface
-- Configuration space access
cfg_do => cfg_do,
cfg_rd_wr_done_n => cfg_rd_wr_done_n,
cfg_dwaddr => cfg_dwaddr,
cfg_rd_en_n => cfg_rd_en_n,
-- Error reporting
cfg_err_ur_n => cfg_err_ur_n,
cfg_err_cor_n => cfg_err_cor_n,
cfg_err_ecrc_n => cfg_err_ecrc_n,
cfg_err_cpl_timeout_n => cfg_err_cpl_timeout_n,
cfg_err_cpl_abort_n => cfg_err_cpl_abort_n,
cfg_err_posted_n => cfg_err_posted_n,
cfg_err_locked_n => cfg_err_locked_n,
cfg_err_tlp_cpl_header => cfg_err_tlp_cpl_header,
cfg_err_cpl_rdy_n => cfg_err_cpl_rdy_n,
-- Interrupt generation
cfg_interrupt_n => cfg_interrupt_n,
cfg_interrupt_rdy_n => cfg_interrupt_rdy_n,
cfg_interrupt_assert_n => cfg_interrupt_assert_n,
cfg_interrupt_do => cfg_interrupt_do,
cfg_interrupt_di => cfg_interrupt_di,
cfg_interrupt_mmenable => cfg_interrupt_mmenable,
cfg_interrupt_msienable => cfg_interrupt_msienable,
-- Power management signaling
cfg_turnoff_ok_n => cfg_turnoff_ok_n,
cfg_to_turnoff_n => cfg_to_turnoff_n,
cfg_pm_wake_n => cfg_pm_wake_n,
cfg_pcie_link_state_n => cfg_pcie_link_state_n,
cfg_trn_pending_n => cfg_trn_pending_n,
-- System configuration and status
cfg_dsn => cfg_dsn,
cfg_bus_number => cfg_bus_number,
cfg_device_number => cfg_device_number,
cfg_function_number => cfg_function_number,
cfg_status => cfg_status,
cfg_command => cfg_command,
cfg_dstatus => cfg_dstatus,
cfg_dcommand => cfg_dcommand,
cfg_lstatus => cfg_lstatus,
cfg_lcommand => cfg_lcommand,
-- System (SYS) Interface
sys_clk => sys_clk_c,
sys_reset_n => sys_reset_n_c,
received_hot_reset => OPEN
);
end rtl;
| gpl-3.0 | b6b19e05537e824741cb1463f23c8077 | 0.470484 | 3.707549 | false | false | false | false |
timofonic/PHDL | misc/projects/spartan_pcie_board/fpga/lx45t_pinout/ipcore_dir/pcie_core/simulation/dsport/pcie_brams_v6.vhd | 1 | 12,113 | -------------------------------------------------------------------------------
--
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Project : Spartan-6 Integrated Block for PCI Express
-- File : pcie_brams_v6.vhd
-- Description: BlockRAM module for Virtex6 PCIe Block
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity pcie_brams_v6 is
generic (
-- the number of BRAMs to use
-- supported values are:
-- 1,2,4,8,18
NUM_BRAMS : integer := 0;
-- BRAM read address latency
--
-- value meaning
-- ====================================================
-- 0 BRAM read address port sample
-- 1 BRAM read address port sample and a pipeline stage on the address port
RAM_RADDR_LATENCY : integer := 1;
-- BRAM read data latency
--
-- value meaning
-- ====================================================
-- 1 no BRAM OREG
-- 2 use BRAM OREG
-- 3 use BRAM OREG and a pipeline stage on the data port
RAM_RDATA_LATENCY : integer := 1;
-- BRAM write latency
-- The BRAM write port is synchronous
--
-- value meaning
-- ====================================================
-- 0 BRAM write port sample
-- 1 BRAM write port sample plus pipeline stage
RAM_WRITE_LATENCY : integer := 1
);
port (
user_clk_i : in std_logic;
reset_i : in std_logic;
wen : in std_logic;
waddr : in std_logic_vector(12 downto 0);
wdata : in std_logic_vector(71 downto 0);
ren : in std_logic;
rce : in std_logic;
raddr : in std_logic_vector(12 downto 0);
rdata : out std_logic_vector(71 downto 0)
);
end pcie_brams_v6;
architecture v6_pcie of pcie_brams_v6 is
component pcie_bram_v6 is
generic (
DOB_REG : integer;
WIDTH : integer
);
port (
user_clk_i : in std_logic;
reset_i : in std_logic;
wen_i : in std_logic;
waddr_i : in std_logic_vector(12 downto 0);
wdata_i : in std_logic_vector(WIDTH - 1 downto 0);
ren_i : in std_logic;
rce_i : in std_logic;
raddr_i : in std_logic_vector(12 downto 0);
rdata_o : out std_logic_vector(WIDTH - 1 downto 0)
);
end component;
FUNCTION to_integer (
in_val : IN boolean) RETURN integer IS
BEGIN
IF (in_val) THEN
RETURN(1);
ELSE
RETURN(0);
END IF;
END to_integer;
-- turn on the bram output register
constant DOB_REG : integer := to_integer(RAM_RDATA_LATENCY > 1);
-- calculate the data width of the individual brams
function width (
constant NUM_BRAM : integer)
return integer is
variable WIDTH_BRAM : integer := 1;
begin -- width
if (NUM_BRAM = 1) then
WIDTH_BRAM := 72;
elsif (NUM_BRAM = 2) then
WIDTH_BRAM := 36;
elsif (NUM_BRAM = 4) then
WIDTH_BRAM := 18;
elsif (NUM_BRAM = 8) then
WIDTH_BRAM := 9;
else
WIDTH_BRAM := 4;
end if;
return WIDTH_BRAM;
end width;
constant BRAM_WIDTH : integer := width(NUM_BRAMS);
constant TCQ : integer := 1;
signal wen_int : std_logic;
signal waddr_int : std_logic_vector(12 downto 0);
signal wdata_int : std_logic_vector(71 downto 0);
signal wen_dly : std_logic := '0';
signal waddr_dly : std_logic_vector(12 downto 0) := (others => '0');
signal wdata_dly : std_logic_vector(71 downto 0) := (others => '0');
-- if (RAM_WRITE_LATENCY == 1)
-- model the delays for ram read latency
signal ren_int : std_logic;
signal raddr_int : std_logic_vector(12 downto 0);
signal rdata_int : std_logic_vector(71 downto 0);
signal ren_dly : std_logic;
signal raddr_dly : std_logic_vector(12 downto 0);
signal rdata_dly : std_logic_vector(71 downto 0);
begin
--synthesis translate_off
process
begin
-- $display("[%t] %m NUM_BRAMS %0d DOB_REG %0d WIDTH %0d RAM_WRITE_LATENCY %0d RAM_RADDR_LATENCY %0d RAM_RDATA_LATENCY %0d", now, to_stdlogic(NUM_BRAMS), to_stdlogicvector(DOB_REG, 13), ("00000000000000000000000000000000000000000000000000000000000000000" & WIDTH), to_stdlogic(RAM_WRITE_LATENCY), to_stdlogic(RAM_RADDR_LATENCY), to_stdlogicvector(RAM_RDATA_LATENCY, 13));
case NUM_BRAMS is
when 1 | 2 | 4 | 8 | 18 =>
when others =>
-- $display("[%t] %m Error NUM_BRAMS %0d not supported", now, to_stdlogic(NUM_BRAMS));
-- $finish();
end case; -- case(NUM_BRAMS)
case RAM_RADDR_LATENCY is
when 0 | 1 =>
when others =>
-- $display("[%t] %m Error RAM_READ_LATENCY %0d not supported", now, to_stdlogic(RAM_RADDR_LATENCY));
-- $finish();
end case; -- case (RAM_RADDR_LATENCY)
case RAM_RDATA_LATENCY is
when 1 | 2 | 3 =>
when others =>
-- $display("[%t] %m Error RAM_READ_LATENCY %0d not supported", now, to_stdlogic(RAM_RDATA_LATENCY));
-- $finish();
end case; -- case (RAM_RDATA_LATENCY)
case RAM_WRITE_LATENCY is
when 0 | 1 =>
when others =>
-- $display("[%t] %m Error RAM_WRITE_LATENCY %0d not supported", now, to_stdlogic(RAM_WRITE_LATENCY));
-- $finish();
end case; -- case(RAM_WRITE_LATENCY)
wait;
end process;
--synthesis translate_on
-- model the delays for ram write latency
wr_lat_2 : if (RAM_WRITE_LATENCY = 1) generate
process (user_clk_i)
begin
if (user_clk_i'event and user_clk_i = '1') then
if (reset_i = '1') then
wen_dly <= '0' after (TCQ)*1 ps;
waddr_dly <= "0000000000000" after (TCQ)*1 ps;
wdata_dly <= "000000000000000000000000000000000000000000000000000000000000000000000000" after (TCQ)*1 ps;
else
wen_dly <= wen after (TCQ)*1 ps;
waddr_dly <= waddr after (TCQ)*1 ps;
wdata_dly <= wdata after (TCQ)*1 ps;
end if;
end if;
end process;
wen_int <= wen_dly;
waddr_int <= waddr_dly;
wdata_int <= wdata_dly;
end generate;
wr_lat_1 : if (RAM_WRITE_LATENCY = 0) generate
wen_int <= wen;
waddr_int <= waddr;
wdata_int <= wdata;
end generate;
raddr_lat_2 : if (RAM_RADDR_LATENCY = 1) generate
process (user_clk_i)
begin
if (user_clk_i'event and user_clk_i = '1') then
if (reset_i = '1') then
ren_dly <= '0' after (TCQ)*1 ps;
raddr_dly <= "0000000000000" after (TCQ)*1 ps;
else
ren_dly <= ren after (TCQ)*1 ps;
raddr_dly <= raddr after (TCQ)*1 ps;
end if;
end if;
end process;
ren_int <= ren_dly;
raddr_int <= raddr_dly;
end generate; -- block: rd_lat_addr_2
raddr_lat_1 : if (not(RAM_RADDR_LATENCY = 1)) generate
ren_int <= ren;
raddr_int <= raddr;
end generate;
rdata_lat_3 : if (RAM_RDATA_LATENCY = 3) generate
process (user_clk_i)
begin
if (user_clk_i'event and user_clk_i = '1') then
if (reset_i = '1') then
rdata_dly <= "000000000000000000000000000000000000000000000000000000000000000000000000" after (TCQ)*1 ps;
else
rdata_dly <= rdata_int after (TCQ)*1 ps;
end if;
end if;
end process;
rdata <= rdata_dly;
end generate; -- block: rd_lat_data_3
rdata_lat_1_2 : if (not(RAM_RDATA_LATENCY = 3)) generate
rdata <= rdata_int after (TCQ)*1 ps;
end generate;
-- instantiate the brams
brams : for i in 0 to NUM_BRAMS - 1 generate
ram : pcie_bram_v6
generic map (
DOB_REG => DOB_REG,
WIDTH => BRAM_WIDTH
)
port map (
user_clk_i => user_clk_i,
reset_i => reset_i,
wen_i => wen_int,
waddr_i => waddr_int,
wdata_i => wdata_int((((i + 1) * BRAM_WIDTH) - 1) downto (i * BRAM_WIDTH)),
ren_i => ren_int,
raddr_i => raddr_int,
rdata_o => rdata_int((((i + 1) * BRAM_WIDTH) - 1) downto (i * BRAM_WIDTH)),
rce_i => rce
);
end generate;
-- pcie_brams_v6
end v6_pcie;
| gpl-3.0 | 1435b53517a6c4890cc717901f93327d | 0.510691 | 4.262139 | false | false | false | false |
timofonic/PHDL | misc/projects/spartan_pcie_board/fpga/lx45t_pinout/ipcore_dir/pcie_core/simulation/dsport/pcie_pipe_misc_v6.vhd | 1 | 8,948 | -------------------------------------------------------------------------------
--
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Project : Spartan-6 Integrated Block for PCI Express
-- File : pcie_pipe_misc_v6.vhd
-- Description: Misc PIPE module for Virtex6 PCIe Block
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity pcie_pipe_misc_v6 is
generic (
PIPE_PIPELINE_STAGES : integer := 0 -- 0 - 0 stages, 1 - 1 stage, 2 - 2 stages
);
port (
pipe_tx_rcvr_det_i : in std_logic;
pipe_tx_reset_i : in std_logic;
pipe_tx_rate_i : in std_logic;
pipe_tx_deemph_i : in std_logic;
pipe_tx_margin_i : in std_logic_vector(2 downto 0);
pipe_tx_swing_i : in std_logic;
pipe_tx_rcvr_det_o : out std_logic;
pipe_tx_reset_o : out std_logic;
pipe_tx_rate_o : out std_logic;
pipe_tx_deemph_o : out std_logic;
pipe_tx_margin_o : out std_logic_vector(2 downto 0);
pipe_tx_swing_o : out std_logic;
pipe_clk : in std_logic;
rst_n : in std_logic
);
end pcie_pipe_misc_v6;
architecture v6_pcie of pcie_pipe_misc_v6 is
--******************************************************************//
-- Reality check. //
--******************************************************************//
constant TCQ : integer := 1; -- clock to out delay model
signal pipe_tx_rcvr_det_q : std_logic;
signal pipe_tx_reset_q : std_logic;
signal pipe_tx_rate_q : std_logic;
signal pipe_tx_deemph_q : std_logic;
signal pipe_tx_margin_q : std_logic_vector(2 downto 0);
signal pipe_tx_swing_q : std_logic;
signal pipe_tx_rcvr_det_qq : std_logic;
signal pipe_tx_reset_qq : std_logic;
signal pipe_tx_rate_qq : std_logic;
signal pipe_tx_deemph_qq : std_logic;
signal pipe_tx_margin_qq : std_logic_vector(2 downto 0);
signal pipe_tx_swing_qq : std_logic;
begin
v6pcie0 : if (PIPE_PIPELINE_STAGES = 0) generate
pipe_tx_rcvr_det_o <= pipe_tx_rcvr_det_i;
pipe_tx_reset_o <= pipe_tx_reset_i;
pipe_tx_rate_o <= pipe_tx_rate_i;
pipe_tx_deemph_o <= pipe_tx_deemph_i;
pipe_tx_margin_o <= pipe_tx_margin_i;
pipe_tx_swing_o <= pipe_tx_swing_i;
end generate;
v6pcie1 : if (PIPE_PIPELINE_STAGES = 1) generate
process (pipe_clk)
begin
if (pipe_clk'event and pipe_clk = '1') then
if (rst_n = '1') then
pipe_tx_rcvr_det_q <= '0' after (TCQ)*1 ps;
pipe_tx_reset_q <= '1' after (TCQ)*1 ps;
pipe_tx_rate_q <= '0' after (TCQ)*1 ps;
pipe_tx_deemph_q <= '1' after (TCQ)*1 ps;
pipe_tx_margin_q <= "000" after (TCQ)*1 ps;
pipe_tx_swing_q <= '0' after (TCQ)*1 ps;
else
pipe_tx_rcvr_det_q <= pipe_tx_rcvr_det_i after (TCQ)*1 ps;
pipe_tx_reset_q <= pipe_tx_reset_i after (TCQ)*1 ps;
pipe_tx_rate_q <= pipe_tx_rate_i after (TCQ)*1 ps;
pipe_tx_deemph_q <= pipe_tx_deemph_i after (TCQ)*1 ps;
pipe_tx_margin_q <= pipe_tx_margin_i after (TCQ)*1 ps;
pipe_tx_swing_q <= pipe_tx_swing_i after (TCQ)*1 ps;
end if;
end if;
end process;
pipe_tx_rcvr_det_o <= pipe_tx_rcvr_det_q;
pipe_tx_reset_o <= pipe_tx_reset_q;
pipe_tx_rate_o <= pipe_tx_rate_q;
pipe_tx_deemph_o <= pipe_tx_deemph_q;
pipe_tx_margin_o <= pipe_tx_margin_q;
pipe_tx_swing_o <= pipe_tx_swing_q;
end generate;
v6pcie2 : if (PIPE_PIPELINE_STAGES = 2) generate
process (pipe_clk)
begin
if (pipe_clk'event and pipe_clk = '1') then
if (rst_n = '1') then
pipe_tx_rcvr_det_q <= '0' after (TCQ)*1 ps;
pipe_tx_reset_q <= '1' after (TCQ)*1 ps;
pipe_tx_rate_q <= '0' after (TCQ)*1 ps;
pipe_tx_deemph_q <= '1' after (TCQ)*1 ps;
pipe_tx_margin_q <= "000" after (TCQ)*1 ps;
pipe_tx_swing_q <= '0' after (TCQ)*1 ps;
pipe_tx_rcvr_det_qq <= '0' after (TCQ)*1 ps;
pipe_tx_reset_qq <= '1' after (TCQ)*1 ps;
pipe_tx_rate_qq <= '0' after (TCQ)*1 ps;
pipe_tx_deemph_qq <= '1' after (TCQ)*1 ps;
pipe_tx_margin_qq <= "000" after (TCQ)*1 ps;
pipe_tx_swing_qq <= '0' after (TCQ)*1 ps;
else
pipe_tx_rcvr_det_q <= pipe_tx_rcvr_det_i after (TCQ)*1 ps;
pipe_tx_reset_q <= pipe_tx_reset_i after (TCQ)*1 ps;
pipe_tx_rate_q <= pipe_tx_rate_i after (TCQ)*1 ps;
pipe_tx_deemph_q <= pipe_tx_deemph_i after (TCQ)*1 ps;
pipe_tx_margin_q <= pipe_tx_margin_i after (TCQ)*1 ps;
pipe_tx_swing_q <= pipe_tx_swing_i after (TCQ)*1 ps;
pipe_tx_rcvr_det_qq <= pipe_tx_rcvr_det_q after (TCQ)*1 ps;
pipe_tx_reset_qq <= pipe_tx_reset_q after (TCQ)*1 ps;
pipe_tx_rate_qq <= pipe_tx_rate_q after (TCQ)*1 ps;
pipe_tx_deemph_qq <= pipe_tx_deemph_q after (TCQ)*1 ps;
pipe_tx_margin_qq <= pipe_tx_margin_q after (TCQ)*1 ps;
pipe_tx_swing_qq <= pipe_tx_swing_q after (TCQ)*1 ps;
end if;
end if;
end process;
pipe_tx_rcvr_det_o <= pipe_tx_rcvr_det_qq;
pipe_tx_reset_o <= pipe_tx_reset_qq;
pipe_tx_rate_o <= pipe_tx_rate_qq;
pipe_tx_deemph_o <= pipe_tx_deemph_qq;
pipe_tx_margin_o <= pipe_tx_margin_qq;
pipe_tx_swing_o <= pipe_tx_swing_qq;
end generate;
end v6_pcie;
| gpl-3.0 | 3ca6b02ebfa84dd12589afcfb886e0d0 | 0.512517 | 3.747069 | false | false | false | false |
masaruohashi/tic-tac-toe | uart/detector_erro_paridade.vhd | 1 | 1,137 | -- VHDL de um circuito verificador de paridade.
-- Realiza a verficacao da paridade dos dados recebidos.
-- Eh zerado durante o estado de preparacao.
library ieee;
use ieee.std_logic_1164.all;
entity detector_erro_paridade is
port(
entrada : in std_logic_vector(11 downto 0);
clock : in std_logic;
enable : in std_logic;
reset : in std_logic;
paridade_ok : out std_logic
);
end detector_erro_paridade;
architecture comportamental of detector_erro_paridade is
begin
process (clock, entrada, enable, reset)
begin
if clock'event and clock = '1' then
if reset = '1' then
paridade_ok <= '0';
elsif enable = '1' then
-- faz a verificacao da paridade do dado ASCII recebido
-- se for 1, a paridade esta correta,
-- se for 0, houve ruido na transmissao e o dado eh invalido.
paridade_ok <= (entrada(8) xor entrada(7) xor entrada(6) xor
entrada(5) xor entrada(4) xor entrada(3) xor
entrada(2)) xnor entrada(9);
end if;
end if;
end process;
end comportamental;
| mit | ba0bcae4fd56cd1547860f645b8b9a20 | 0.620053 | 3.740132 | false | false | false | false |
timofonic/PHDL | misc/projects/spartan_pcie_board/fpga/lx45t_pinout/ipcore_dir/pcie_core/simulation/dsport/test_interface.vhd | 1 | 99,173 | -------------------------------------------------------------------------------
--
-- (c) Copyright 2008, 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Project : Spartan-6 Integrated Block for PCI Express
-- File : test_interface.vhd
-- Description: Procedures invoked by the test program file.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
-- Package Declaration
package test_interface is
type BYTE_ARRAY is array (999 downto 0) of std_logic_vector(7 downto 0);
type DATA_ARRAY is array (499 downto 0) of std_logic_vector(7 downto 0);
type THIRTY_THREE_BIT_ARRAY is array (6 downto 0) of std_logic_vector((33 - 1) downto 0);
type DWORD_ARRAY is array (6 downto 0) of std_logic_vector((32 - 1) downto 0);
type ENABLE_ARRAY is array (6 downto 0) of INTEGER;
constant PCI_EXP_MEM_READ32 : std_logic_vector(6 downto 0) := "0000000";
constant PCI_EXP_IO_READ : std_logic_vector(6 downto 0) := "0000010";
constant PCI_EXP_CFG_READ0 : std_logic_vector(6 downto 0) := "0000100";
constant PCI_EXP_COMPLETION_WO_DATA : std_logic_vector(6 downto 0) := "0001010";
constant PCI_EXP_MEM_READ64 : std_logic_vector(6 downto 0) := "0100000";
constant PCI_EXP_MSG_NODATA : std_logic_vector(6 downto 3) := "0110";
constant PCI_EXP_MEM_WRITE32 : std_logic_vector(6 downto 0) := "1000000";
constant PCI_EXP_IO_WRITE : std_logic_vector(6 downto 0) := "1000010";
constant PCI_EXP_CFG_WRITE0 : std_logic_vector(6 downto 0) := "1000100";
constant PCI_EXP_COMPLETION_DATA : std_logic_vector(6 downto 0) := "1001010";
constant PCI_EXP_MEM_WRITE64 : std_logic_vector(6 downto 0) := "1100000";
constant PCI_EXP_MSG_DATA : std_logic_vector(6 downto 3) := "1110";
constant COMPLETER_ID_CFG : std_logic_vector(15 downto 0) := X"01A0";
constant DEV_ID : std_logic_vector(15 downto 0) := X"0007";
constant VEN_ID : std_logic_vector(15 downto 0) := X"10EE";
constant DEV_VEN_ID : std_logic_vector(31 downto 0) := (DEV_ID & VEN_ID);
signal trn_trem_n_c : std_logic_vector ((8 - 1) downto 0 );
signal trn_td_c : std_logic_vector ((64 - 1) downto 0 );
shared variable frame_store_tx : BYTE_ARRAY;
shared variable frame_store_tx_idx : INTEGER;
shared variable DATA_STORE : DATA_ARRAY;
shared variable P_READ_DATA : std_logic_vector(31 downto 0);
shared variable Lglobal : line;
shared variable BAR_RANGE : DWORD_ARRAY;
shared variable BAR : THIRTY_THREE_BIT_ARRAY;
shared variable NUMBER_OF_IO_BARS : INTEGER;
shared variable NUMBER_OF_MEM64_BARS : INTEGER;
shared variable NUMBER_OF_MEM32_BARS : INTEGER;
shared variable BAR_ENABLED : ENABLE_ARRAY;
shared variable pio_check_design : boolean;
shared variable i : INTEGER;
shared variable success : boolean;
-- Cfg Rd/Wr interface signals
type cfg_rdwr_sigs is record
trn_clk : std_logic;
trn_reset_n : std_logic;
cfg_rd_wr_done_n : std_logic;
cfg_dwaddr : std_logic_vector(9 downto 0);
cfg_di : std_logic_vector(31 downto 0);
cfg_do : std_logic_vector(31 downto 0);
cfg_byte_en_n : std_logic_vector(3 downto 0);
cfg_wr_en_n : std_logic;
cfg_rd_en_n : std_logic;
end record;
signal cfg_rdwr_int : cfg_rdwr_sigs := (trn_clk => 'Z', trn_reset_n => 'Z', cfg_rd_wr_done_n => '1', cfg_dwaddr => (OTHERS => '0'), cfg_di => x"00000000", cfg_do => x"00000000", cfg_byte_en_n => "1111", cfg_wr_en_n => '1', cfg_rd_en_n => '1');
file tx_file : TEXT open write_mode is "tx.dat";
procedure writeNowToTx ( text_string : in string);
procedure writeHexToTx ( text_string : in string;
hexValue : in std_logic_vector);
procedure writeNowToScreen (text_string : in string);
procedure FINISH;
procedure FINISH_FAILURE;
procedure PROC_TX_SYNCHRONIZE (
first : in INTEGER;
last_call: in INTEGER;
signal trn_lnk_up_n : in std_logic;
signal trn_tdst_rdy_n : in std_logic;
signal trn_clk : in std_logic
);
procedure PROC_TX_TYPE0_CONFIGURATION_READ (
tag : in std_logic_vector (7 downto 0);
reg_addr : in std_logic_vector (11 downto 0);
first_dw_be : in std_logic_vector (3 downto 0);
signal trn_td_c : out std_logic_vector(63 downto 0);
signal trn_tsof_n : out std_logic;
signal trn_teof_n : out std_logic;
signal trn_trem_n_c : out std_logic_vector(7 downto 0);
signal trn_tsrc_rdy_n : out std_logic;
signal trn_lnk_up_n : in std_logic;
signal trn_tdst_rdy_n : in std_logic;
signal trn_clk : in std_logic
);
procedure PROC_TX_TYPE0_CONFIGURATION_WRITE (
tag : in std_logic_vector (7 downto 0);
reg_addr : in std_logic_vector (11 downto 0);
reg_data : in std_logic_vector (31 downto 0);
first_dw_be : in std_logic_vector (3 downto 0);
signal trn_td_c : out std_logic_vector(63 downto 0);
signal trn_tsof_n : out std_logic;
signal trn_teof_n : out std_logic;
signal trn_trem_n_c : out std_logic_vector(7 downto 0);
signal trn_tsrc_rdy_n : out std_logic;
signal trn_lnk_up_n : in std_logic;
signal trn_tdst_rdy_n : in std_logic;
signal trn_clk : in std_logic
);
procedure PROC_TX_TYPE1_CONFIGURATION_READ (
tag : in std_logic_vector (7 downto 0);
reg_addr : in std_logic_vector (11 downto 0);
first_dw_be : in std_logic_vector (3 downto 0);
signal trn_td_c : out std_logic_vector(63 downto 0);
signal trn_tsof_n : out std_logic;
signal trn_teof_n : out std_logic;
signal trn_trem_n_c : out std_logic_vector(7 downto 0);
signal trn_tsrc_rdy_n : out std_logic;
signal trn_lnk_up_n : in std_logic;
signal trn_tdst_rdy_n : in std_logic;
signal trn_clk : in std_logic
);
procedure PROC_TX_TYPE1_CONFIGURATION_WRITE (
tag : in std_logic_vector (7 downto 0);
reg_addr : in std_logic_vector (11 downto 0);
reg_data : in std_logic_vector (31 downto 0);
first_dw_be : in std_logic_vector (3 downto 0);
signal trn_td_c : out std_logic_vector(63 downto 0);
signal trn_tsof_n : out std_logic;
signal trn_teof_n : out std_logic;
signal trn_trem_n_c : out std_logic_vector(7 downto 0);
signal trn_tsrc_rdy_n : out std_logic;
signal trn_lnk_up_n : in std_logic;
signal trn_tdst_rdy_n : in std_logic;
signal trn_clk : in std_logic
);
procedure PROC_TX_MEMORY_READ_32 (
tag : in std_logic_vector (7 downto 0);
tc : in std_logic_vector (2 downto 0);
len : in std_logic_vector (9 downto 0);
addr : in std_logic_vector (31 downto 0);
last_dw_be : in std_logic_vector (3 downto 0);
first_dw_be : in std_logic_vector (3 downto 0);
signal trn_td_c : out std_logic_vector(63 downto 0);
signal trn_tsof_n : out std_logic;
signal trn_teof_n : out std_logic;
signal trn_trem_n_c : out std_logic_vector(7 downto 0);
signal trn_tsrc_rdy_n : out std_logic;
signal trn_lnk_up_n : in std_logic;
signal trn_tdst_rdy_n : in std_logic;
signal trn_clk : in std_logic
);
procedure PROC_TX_MEMORY_READ_64 (
tag : in std_logic_vector (7 downto 0);
tc : in std_logic_vector (2 downto 0);
len : in std_logic_vector (9 downto 0);
addr : in std_logic_vector (63 downto 0);
last_dw_be : in std_logic_vector (3 downto 0);
first_dw_be : in std_logic_vector (3 downto 0);
signal trn_td_c : out std_logic_vector(63 downto 0);
signal trn_tsof_n : out std_logic;
signal trn_teof_n : out std_logic;
signal trn_trem_n_c : out std_logic_vector(7 downto 0);
signal trn_tsrc_rdy_n : out std_logic;
signal trn_lnk_up_n : in std_logic;
signal trn_tdst_rdy_n : in std_logic;
signal trn_clk : in std_logic
);
procedure PROC_TX_MEMORY_WRITE_32 (
tag : in std_logic_vector (7 downto 0);
tc : in std_logic_vector (2 downto 0);
len : in std_logic_vector (9 downto 0);
addr : in std_logic_vector (31 downto 0);
last_dw_be : in std_logic_vector (3 downto 0);
first_dw_be : in std_logic_vector (3 downto 0);
ep : in std_logic;
signal trn_td_c : out std_logic_vector(63 downto 0);
signal trn_tsof_n : out std_logic;
signal trn_teof_n : out std_logic;
signal trn_trem_n_c : out std_logic_vector(7 downto 0);
signal trn_tsrc_rdy_n : out std_logic;
signal trn_terrfwd_n : out std_logic;
signal trn_lnk_up_n : in std_logic;
signal trn_tdst_rdy_n : in std_logic;
signal trn_clk : in std_logic
);
procedure PROC_TX_MEMORY_WRITE_64 (
tag : in std_logic_vector (7 downto 0);
tc : in std_logic_vector (2 downto 0);
len : in std_logic_vector (9 downto 0);
addr : in std_logic_vector (63 downto 0);
last_dw_be : in std_logic_vector (3 downto 0);
first_dw_be : in std_logic_vector (3 downto 0);
ep : in std_logic;
signal trn_td_c : out std_logic_vector(63 downto 0);
signal trn_tsof_n : out std_logic;
signal trn_teof_n : out std_logic;
signal trn_trem_n_c : out std_logic_vector(7 downto 0);
signal trn_tsrc_rdy_n : out std_logic;
signal trn_terrfwd_n : out std_logic;
signal trn_lnk_up_n : in std_logic;
signal trn_tdst_rdy_n : in std_logic;
signal trn_clk : in std_logic
);
procedure PROC_TX_COMPLETION (
tag : in std_logic_vector (7 downto 0);
tc : in std_logic_vector (2 downto 0);
len : in std_logic_vector (9 downto 0);
comp_status : in std_logic_vector (2 downto 0);
signal trn_td_c : out std_logic_vector(63 downto 0);
signal trn_tsof_n : out std_logic;
signal trn_teof_n : out std_logic;
signal trn_trem_n_c : out std_logic_vector(7 downto 0);
signal trn_tsrc_rdy_n : out std_logic;
signal trn_lnk_up_n : in std_logic;
signal trn_tdst_rdy_n : in std_logic;
signal trn_clk : in std_logic
);
procedure PROC_TX_COMPLETION_DATA (
tag : in std_logic_vector (7 downto 0);
tc : in std_logic_vector (2 downto 0);
len : in std_logic_vector (9 downto 0);
byte_count : in std_logic_vector (11 downto 0);
lower_addr : in std_logic_vector (6 downto 0);
comp_status : in std_logic_vector (2 downto 0);
ep : in std_logic;
signal trn_td_c : out std_logic_vector(63 downto 0);
signal trn_tsof_n : out std_logic;
signal trn_teof_n : out std_logic;
signal trn_trem_n_c : out std_logic_vector(7 downto 0);
signal trn_tsrc_rdy_n : out std_logic;
signal trn_terrfwd_n : out std_logic;
signal trn_lnk_up_n : in std_logic;
signal trn_tdst_rdy_n : in std_logic;
signal trn_clk : in std_logic
);
procedure PROC_TX_MESSAGE (
tag : in std_logic_vector (7 downto 0);
tc : in std_logic_vector (2 downto 0);
len : in std_logic_vector (9 downto 0);
data : in std_logic_vector (63 downto 0);
message_rtg : in std_logic_vector (2 downto 0);
message_code : in std_logic_vector (7 downto 0);
signal trn_td_c : out std_logic_vector(63 downto 0);
signal trn_tsof_n : out std_logic;
signal trn_teof_n : out std_logic;
signal trn_trem_n_c : out std_logic_vector(7 downto 0);
signal trn_tsrc_rdy_n : out std_logic;
signal trn_lnk_up_n : in std_logic;
signal trn_tdst_rdy_n : in std_logic;
signal trn_clk : in std_logic
);
procedure PROC_TX_MESSAGE_DATA (
tag : in std_logic_vector (7 downto 0);
tc : in std_logic_vector (2 downto 0);
len : in std_logic_vector (9 downto 0);
data : in std_logic_vector (63 downto 0);
message_rtg : in std_logic_vector (2 downto 0);
message_code : in std_logic_vector (7 downto 0);
signal trn_td_c : out std_logic_vector(63 downto 0);
signal trn_tsof_n : out std_logic;
signal trn_teof_n : out std_logic;
signal trn_trem_n_c : out std_logic_vector(7 downto 0);
signal trn_tsrc_rdy_n : out std_logic;
signal trn_lnk_up_n : in std_logic;
signal trn_tdst_rdy_n : in std_logic;
signal trn_clk : in std_logic
);
procedure PROC_TX_IO_READ (
tag : in std_logic_vector (7 downto 0);
addr : in std_logic_vector (31 downto 0);
first_dw_be : in std_logic_vector (3 downto 0);
signal trn_td_c : out std_logic_vector(63 downto 0);
signal trn_tsof_n : out std_logic;
signal trn_teof_n : out std_logic;
signal trn_trem_n_c : out std_logic_vector(7 downto 0);
signal trn_tsrc_rdy_n : out std_logic;
signal trn_lnk_up_n : in std_logic;
signal trn_tdst_rdy_n : in std_logic;
signal trn_clk : in std_logic
);
procedure PROC_TX_IO_WRITE (
tag : in std_logic_vector (7 downto 0);
addr : in std_logic_vector (31 downto 0);
first_dw_be : in std_logic_vector (3 downto 0);
data : in std_logic_vector(31 downto 0);
signal trn_td_c : out std_logic_vector(63 downto 0);
signal trn_tsof_n : out std_logic;
signal trn_teof_n : out std_logic;
signal trn_trem_n_c : out std_logic_vector(7 downto 0);
signal trn_tsrc_rdy_n : out std_logic;
signal trn_lnk_up_n : in std_logic;
signal trn_tdst_rdy_n : in std_logic;
signal trn_clk : in std_logic
);
procedure PROC_USR_DATA_SETUP_SEQ;
procedure PROC_TX_CLK_EAT (
clock_count : in INTEGER;
signal trn_clk : in std_logic
);
procedure PROC_SET_READ_DATA (
be : in std_logic_vector(3 downto 0);
data : in std_logic_vector(31 downto 0)
);
procedure PROC_WAIT_FOR_READ_DATA (
signal tx_rx_read_data_valid : out std_logic;
signal rx_tx_read_data_valid : in std_logic;
signal rx_tx_read_data : in std_logic_vector(31 downto 0);
signal trn_clk : in std_logic
);
procedure PROC_DISPLAY_PCIE_MAP (
BAR : THIRTY_THREE_BIT_ARRAY;
BAR_ENABLED : ENABLE_ARRAY;
BAR_RANGE : DWORD_ARRAY
);
procedure PROC_BUILD_PCIE_MAP
;
procedure PROC_BAR_SCAN (
signal tx_rx_read_data_valid : out std_logic;
signal rx_tx_read_data_valid : in std_logic;
signal rx_tx_read_data : in std_logic_vector (31 downto 0);
signal trn_td_c : out std_logic_vector(63 downto 0);
signal trn_tsof_n : out std_logic;
signal trn_teof_n : out std_logic;
signal trn_trem_n_c : out std_logic_vector(7 downto 0);
signal trn_tsrc_rdy_n : out std_logic;
signal trn_lnk_up_n : in std_logic;
signal trn_tdst_rdy_n : in std_logic;
signal trn_clk : in std_logic
);
procedure PROC_BAR_PROGRAM (
signal trn_td_c : out std_logic_vector(63 downto 0);
signal trn_tsof_n : out std_logic;
signal trn_teof_n : out std_logic;
signal trn_trem_n_c : out std_logic_vector(7 downto 0);
signal trn_tsrc_rdy_n : out std_logic;
signal trn_lnk_up_n : in std_logic;
signal trn_tdst_rdy_n : in std_logic;
signal trn_clk : in std_logic
);
procedure PROC_BAR_INIT (
signal tx_rx_read_data_valid : out std_logic;
signal rx_tx_read_data_valid : in std_logic;
signal rx_tx_read_data : in std_logic_vector (31 downto 0);
signal trn_td_c : out std_logic_vector(63 downto 0);
signal trn_tsof_n : out std_logic;
signal trn_teof_n : out std_logic;
signal trn_trem_n_c : out std_logic_vector(7 downto 0);
signal trn_tsrc_rdy_n : out std_logic;
signal trn_lnk_up_n : in std_logic;
signal trn_tdst_rdy_n : in std_logic;
signal trn_clk : in std_logic
);
procedure PROC_SYSTEM_INITIALIZATION(
signal trn_reset_n: in std_logic;
signal trn_lnk_up_n: in std_logic );
procedure PROC_READ_CFG_DW (
addr : in std_logic_vector(9 downto 0);
signal cfg_rdwr_int : inout cfg_rdwr_sigs
);
procedure PROC_WRITE_CFG_DW (
addr : in std_logic_vector(9 downto 0);
data : in std_logic_vector(31 downto 0);
byte_en_n : in std_logic_vector(3 downto 0);
signal cfg_rdwr_int : inout cfg_rdwr_sigs
);
end package test_interface;
-- Package Body
package body test_interface is
--************************************************************
-- Proc : writeNowToTx
-- Inputs : Text String
-- Outputs : None
-- Description : Displays text string to Tx file pre-appended with
-- current simulation time..
--*************************************************************
procedure writeNowToTx (
text_string : in string
) is
variable L : line;
begin
write (L, String'("[ "));
write (L, now);
write (L, String'(" ] : "));
write (L, text_string);
writeline (tx_file, L);
end writeNowToTx;
--************************************************************
-- Proc : writeHexToTx
-- Inputs : hex value with bit width that is multiple of 4
-- Outputs : None
-- Description : Displays nibble aligned hex value to Tx file
--
--*************************************************************
procedure writeHexToTx (
text_string : in string;
hexValue : in std_logic_vector
) is
variable L : line;
begin
write (L, text_string);
hwrite(L, hexValue);
writeline (tx_file, L);
end writeHexToTx;
--************************************************************
-- Proc : writeNowToScreen
-- Inputs : Text String
-- Outputs : None
-- Description : Displays current simulation time and text string to
-- standard output.
--*************************************************************
procedure writeNowToScreen (
text_string : in string
) is
variable L : line;
begin
write (L, String'("[ "));
write (L, now);
write (L, String'(" ] : "));
write (L, text_string);
writeline (output, L);
end writeNowToScreen;
--************************************************************
-- Proc : PROC_READ_DATA
-- Inputs : None
-- Outputs : None
-- Description : Consume clocks.
-- *************************************************************/
procedure PROC_READ_DATA (
last : in INTEGER;
trn_d : in std_logic_vector (63 downto 0);
trn_rem : in std_logic_vector (7 downto 0)
) is
variable i : INTEGER;
variable data_byte : std_logic_vector (7 downto 0);
variable remain : INTEGER;
variable hi_index : INTEGER;
variable low_index : INTEGER;
variable my_line : line;
begin
hi_index := 63;
low_index := 56;
if (last = 1) then
if (trn_rem = X"0F") then
remain := 4;
else remain := 8;
end if;
else
remain := 8;
end if;
for i in 0 to (remain - 1) loop
data_byte := trn_d( hi_index downto low_index);
hi_index := hi_index - 8;
low_index := low_index - 8;
frame_store_tx(frame_store_tx_idx) := data_byte;
frame_store_tx_idx := frame_store_tx_idx + 1;
end loop;
end PROC_READ_DATA;
--************************************************************
-- Proc : PROC_DECIPHER_FRAME
-- Inputs : None
-- Outputs : fmt, tlp_type, traffic_class, td, ep, attr, length
-- Description : Deciphers frame
-- *************************************************************/
procedure PROC_DECIPHER_FRAME (
fmt : out std_logic_vector (1 downto 0);
tlp_type : out std_logic_vector (4 downto 0);
traffic_class : out std_logic_vector (2 downto 0);
td : out std_logic;
ep : out std_logic;
attr : out std_logic_vector (1 downto 0);
length : out std_logic_vector (9 downto 0)
) is
begin
fmt := frame_store_tx(0)(6 downto 5);
tlp_type := frame_store_tx(0)(4 downto 0);
traffic_class := frame_store_tx(1)(6 downto 4);
td := frame_store_tx(2)(7);
ep := frame_store_tx(2)(6);
attr := frame_store_tx(2)(5 downto 4);
length(9 downto 8) := frame_store_tx(2)(1 downto 0);
length(7 downto 0) := frame_store_tx(3);
end PROC_DECIPHER_FRAME;
-- ************************************************************
-- Proc : PROC_3DW
-- Inputs : fmt, type, traffic_class, td, ep, attr, length,
-- payload,
-- Outputs : None
-- Description : Gets variables and prints frame
-- *************************************************************/
procedure PROC_3DW (
fmt : in std_logic_vector (1 downto 0);
tlp_type : in std_logic_vector (4 downto 0);
traffic_class : in std_logic_vector (2 downto 0);
td : in std_logic;
ep : in std_logic;
attr : in std_logic_vector (1 downto 0);
length : in std_logic_vector (9 downto 0);
payload : in INTEGER
) is
variable requester_id : std_logic_vector (15 downto 0);
variable tag : std_logic_vector (7 downto 0);
variable byte_enables : std_logic_vector (7 downto 0);
variable address_low : std_logic_vector (31 downto 0);
variable completer_id : std_logic_vector (15 downto 0);
variable register_address : std_logic_vector (9 downto 0);
variable completion_status : std_logic_vector (2 downto 0);
variable i : INTEGER;
variable L : line;
variable fmt_type : std_logic_vector (6 downto 0);
begin
writeHexToTx (String'(" Traffic Class: 0x"), '0' & traffic_class);
write (L, String'(" TD: ")); write(L, td); writeline (tx_file, L);
write (L, String'(" EP: ")); write(L, ep); writeline (tx_file, L);
writeHexToTx (String'(" Attributes: 0x"), "00" & attr);
writeHexToTx (String'(" Length: 0x"), "00" & length);
fmt_type := fmt & tlp_type;
case (fmt_type) is
when PCI_EXP_CFG_READ0 | PCI_EXP_CFG_WRITE0 =>
requester_id := frame_store_tx(4) & frame_store_tx(5);
tag := frame_store_tx(6);
byte_enables := frame_store_tx(7);
completer_id := frame_store_tx(8) & frame_store_tx(9);
register_address(9 downto 8) := frame_store_tx(10)(1 downto 0);
register_address(7 downto 0) := frame_store_tx(11);
writeHexToTx ( String'(" Requester Id: 0x"), requester_id);
writeHexToTx ( String'(" Tag: 0x"), tag);
writeHexToTx ( String'(" Last and First Byte Enables: 0x"), byte_enables);
writeHexToTx ( String'(" Completer Id: 0x"), completer_id);
writeHexToTx ( String'(" Register Address: 0x"), "00" & register_address);
if (payload = 1) then
write (L, String'("")); writeline(tx_file, L);
for i in 12 to (frame_store_tx_idx - 1) loop
writeHexToTx ( String'(" 0x"), frame_store_tx(i));
end loop;
end if;
write (L, String'("")); writeline(tx_file, L);
when PCI_EXP_COMPLETION_WO_DATA | PCI_EXP_COMPLETION_DATA=>
completer_id := frame_store_tx(4) & frame_store_tx(5);
completion_status(2 downto 0) := frame_store_tx(6)(7 downto 5);
requester_id := frame_store_tx(8) & frame_store_tx(9);
tag := frame_store_tx(10);
writeHexToTx ( String'(" Completer Id: 0x"), completer_id);
writeHexToTx ( String'(" Completion Status: 0x"), '0' & completion_status);
writeHexToTx ( String'(" Requester Id: 0x"), requester_id);
writeHexToTx ( String'(" Tag: 0x"), tag);
if (payload = 1) then
write (L, String'("")); writeline(tx_file, L);
for i in 12 to (frame_store_tx_idx - 1) loop
writeHexToTx ( String'(" 0x"), frame_store_tx(i));
end loop;
end if;
write (L, String'("")); writeline(tx_file, L);
when others =>
requester_id := frame_store_tx(4) & frame_store_tx(5);
tag := frame_store_tx(6);
byte_enables := frame_store_tx(7);
address_low(31 downto 24) := frame_store_tx(8);
address_low(23 downto 16) := frame_store_tx(9);
address_low(15 downto 8) := frame_store_tx(10);
address_low( 7 downto 0) := frame_store_tx(11);
writeHexToTx ( String'(" Requester Id: 0x"), requester_id);
writeHexToTx ( String'(" Tag: 0x"), tag);
writeHexToTx ( String'(" Last and First Byte Enables: 0x"), byte_enables);
writeHexToTx ( String'(" Address Low: 0x"), address_low);
if (payload = 1) then
write (L, String'("")); writeline(tx_file, L);
for i in 12 to (frame_store_tx_idx - 1) loop
writeHexToTx ( String'(" 0x"), frame_store_tx(i));
end loop;
end if;
write (L, String'("")); writeline(tx_file, L);
end case;
end PROC_3DW;
-- ************************************************************
-- Proc : PROC_4DW
-- Inputs : fmt, type, traffic_class, td, ep, attr, length
-- payload
-- Outputs : None
-- Description : Gets variables and prints frame
-- *************************************************************/
procedure PROC_4DW (
fmt : in std_logic_vector (1 downto 0);
tlp_type : in std_logic_vector (4 downto 0);
traffic_class : in std_logic_vector (2 downto 0);
td : in std_logic;
ep : in std_logic;
attr : in std_logic_vector (1 downto 0);
length : in std_logic_vector (9 downto 0);
payload : in INTEGER
) is
variable requester_id : std_logic_vector (15 downto 0);
variable tag : std_logic_vector (7 downto 0);
variable byte_enables : std_logic_vector (7 downto 0);
variable message_code : std_logic_vector (7 downto 0);
variable address_high : std_logic_vector (31 downto 0);
variable address_low : std_logic_vector (31 downto 0);
variable msg_type : std_logic_vector (2 downto 0);
variable i : INTEGER;
variable L : line;
variable fmt_type : std_logic_vector (6 downto 0);
begin
writeHexToTx (String'(" Traffic Class: 0x"), '0' & traffic_class);
write (L, String'(" TD: ")); write(L, td); writeline (tx_file, L);
write (L, String'(" EP: ")); write(L, ep); writeline (tx_file, L);
writeHexToTx (String'(" Attributes: 0x"), "00" & attr);
writeHexToTx (String'(" Length: 0x"), "00" & length);
requester_id := frame_store_tx(4) & frame_store_tx(5);
tag := frame_store_tx(6);
byte_enables := frame_store_tx(7);
message_code := frame_store_tx(7);
address_high(31 downto 24) := frame_store_tx(8);
address_high(23 downto 16) := frame_store_tx(9) ;
address_high(15 downto 8) := frame_store_tx(10);
address_high(7 downto 0) := frame_store_tx(11);
address_low(31 downto 24) := frame_store_tx(12);
address_low(23 downto 16) := frame_store_tx(13);
address_low(15 downto 8) := frame_store_tx(14) ;
address_low(7 downto 0) := frame_store_tx(15);
writeHexToTx ( String'(" Requester Id: 0x"), requester_id);
writeHexToTx ( String'(" Tag: 0x"), tag);
fmt_type := fmt & tlp_type;
if ((fmt_type(6 downto 3) = PCI_EXP_MSG_NODATA)
or (fmt_type(6 downto 3) = PCI_EXP_MSG_DATA)) then
msg_type := tlp_type(2 downto 0);
writeHexToTx ( String'(" Message Type: 0x"), '0' & msg_type);
writeHexToTx ( String'(" Message Code: 0x"), message_code);
writeHexToTx ( String'(" Address High: 0x"), address_high);
writeHexToTx ( String'(" Address Low: 0x"), address_low);
if (payload = 1) then
write (L, String'("")); writeline(tx_file, L);
for i in 16 to (frame_store_tx_idx - 1) loop
writeHexToTx ( String'(" 0x"), frame_store_tx(i));
end loop;
end if;
write (L, String'("")); writeline(tx_file, L);
else
case (fmt_type) is
when PCI_EXP_MEM_READ64 | PCI_EXP_MEM_WRITE64 =>
writeHexToTx ( String'(" Last and First Byte Enables: 0x"), byte_enables);
writeHexToTx ( String'(" Address High: 0x"), address_high);
writeHexToTx ( String'(" Address Low: 0x"), address_low);
if (payload = 1) then
write (L, String'("")); writeline(tx_file, L);
for i in 16 to (frame_store_tx_idx - 1) loop
writeHexToTx ( String'(" 0x"), frame_store_tx(i));
end loop;
end if;
write (L, String'("")); writeline(tx_file, L);
when others =>
write (L, String'(": Not a vaild frame")); writeline (tx_file, L); write (L, String'("")); writeline(tx_file, L);
assert (false)
report "Simulation Ended"
severity failure;
end case; -- (fmt_type)
end if;
end PROC_4DW;
--************************************************************
-- Proc : PROC_PARSE_FRAME
-- Inputs : None
-- Outputs : None
-- Description : Parse frame data
-- *************************************************************/
procedure PROC_PARSE_FRAME is
variable fmt : std_logic_vector (1 downto 0);
variable tlp_type : std_logic_vector (4 downto 0);
variable traffic_class : std_logic_vector (2 downto 0);
variable td : std_logic;
variable ep : std_logic;
variable attr : std_logic_vector (1 downto 0);
variable length : std_logic_vector (9 downto 0);
variable payload : INTEGER;
variable reqester_id : std_logic_vector(15 downto 0);
variable completer_id : std_logic_vector(15 downto 0);
variable tag : std_logic_vector(7 downto 0);
variable byte_enables : std_logic_vector(7 downto 0);
variable message_code : std_logic_vector(7 downto 0);
variable address_low : std_logic_vector(31 downto 0);
variable address_high : std_logic_vector(31 downto 0);
variable register_address : std_logic_vector (9 downto 0);
variable completion_status : std_logic_vector (2 downto 0);
variable log_file_ptr : std_logic_vector (31 downto 0);
variable frame_store_idx : INTEGER;
variable fmt_type : std_logic_vector (6 downto 0);
variable L : line;
begin
writeNowToScreen ( String'("PROC_PARSE_FRAME on Transmit"));
PROC_DECIPHER_FRAME (fmt, tlp_type, traffic_class, td, ep, attr, length);
-- decode the packets received based on fmt and type
fmt_type := fmt & tlp_type;
if (fmt_type(6 downto 3) = PCI_EXP_MSG_NODATA) then
writeNowToTx("Message With No Data Frame");
payload := 0;
PROC_4DW(fmt, tlp_type, traffic_class, td, ep, attr, length, payload);
elsif (fmt_type(6 downto 3) = PCI_EXP_MSG_DATA) then
writeNowToTx("Message With Data Frame");
payload := 1;
PROC_4DW(fmt, tlp_type, traffic_class, td, ep, attr, length, payload);
else
case (fmt_type) is
when PCI_EXP_MEM_READ32 =>
writeNowToTx("Memory Read-32 Frame");
payload := 0;
PROC_3DW(fmt, tlp_type, traffic_class, td, ep, attr, length, payload);
when PCI_EXP_IO_READ =>
writeNowToTx("IO Read Frame");
payload := 0;
PROC_3DW(fmt, tlp_type, traffic_class, td, ep, attr, length, payload);
when PCI_EXP_CFG_READ0 =>
writeNowToTx("Config Read Type 0 Frame");
payload := 0;
PROC_3DW(fmt, tlp_type, traffic_class, td, ep, attr, length, payload);
when PCI_EXP_COMPLETION_WO_DATA =>
writeNowToTx("Completion Without Data Frame");
payload := 0;
PROC_3DW(fmt, tlp_type, traffic_class, td, ep, attr, length, payload);
when PCI_EXP_MEM_READ64 =>
writeNowToTx("Memory Read-64 Frame");
payload := 0;
PROC_4DW(fmt, tlp_type, traffic_class, td, ep, attr, length, payload);
when PCI_EXP_MEM_WRITE32 =>
writeNowToTx("Memory Write-32 Frame");
payload := 1;
PROC_3DW(fmt, tlp_type, traffic_class, td, ep, attr, length, payload);
when PCI_EXP_IO_WRITE =>
writeNowToTx("IO Write Frame");
payload := 1;
PROC_3DW(fmt, tlp_type, traffic_class, td, ep, attr, length, payload);
when PCI_EXP_CFG_WRITE0 =>
writeNowToTx("Config Write Type 0 Frame");
payload := 1;
PROC_3DW(fmt, tlp_type, traffic_class, td, ep, attr, length, payload);
when PCI_EXP_COMPLETION_DATA =>
writeNowToTx("Completion With Data Frame");
payload := 1;
PROC_3DW(fmt, tlp_type, traffic_class, td, ep, attr, length, payload);
when PCI_EXP_MEM_WRITE64 =>
writeNowToTx("Memory Write-64 Frame");
payload := 1;
PROC_4DW(fmt, tlp_type, traffic_class, td, ep, attr, length, payload);
when others =>
writeNowToTx("Not a vaild frame. fmt_type = ");
write (L, fmt_type);
writeline (tx_file, L);
assert (false)
report "Simulation Ended"
severity failure;
end case;
end if;
frame_store_tx_idx := 0; -- reset frame pointer
end PROC_PARSE_FRAME;
--************************************************************
-- Proc : FINISH
-- Inputs : None
-- Outputs : None
-- Description : Ends simulation with successful message
--*************************************************************/
procedure FINISH is
variable L : line;
begin
assert (false)
report "Simulation Stopped."
severity failure;
end FINISH;
--************************************************************
-- Proc : FINISH_FAILURE
-- Inputs : None
-- Outputs : None
-- Description : Ends simulation with failure message
--*************************************************************/
procedure FINISH_FAILURE is
variable L : line;
begin
assert (false)
report "Simulation Ended With 1 or more failures"
severity failure;
end FINISH_FAILURE;
--************************************************************
-- Proc : PROC_TX_CLK_EAT
-- Inputs : None
-- Outputs : None
-- Description : Consume clocks.
--*************************************************************/
procedure PROC_TX_CLK_EAT (
clock_count : in INTEGER;
signal trn_clk : in std_logic
) is
variable i : INTEGER;
begin
for i in 0 to (clock_count - 1) loop
wait until (trn_clk'event and trn_clk = '1');
end loop;
end PROC_TX_CLK_EAT;
--************************************************************
-- Proc : PROC_TX_SYNCHRONIZE
-- Inputs : first_, last_call_
-- Outputs : None
-- Description : Synchronize with tx clock and handshake signals
--*************************************************************/
procedure PROC_TX_SYNCHRONIZE (
first : in INTEGER;
last_call: in INTEGER;
signal trn_lnk_up_n : in std_logic;
signal trn_tdst_rdy_n : in std_logic;
signal trn_clk : in std_logic
) is
variable last : INTEGER;
begin
assert (trn_lnk_up_n = '0')
report "TX Trn interface is MIA"
severity failure;
wait until (trn_clk'event and trn_clk = '1');
if ((trn_tdst_rdy_n = '1') and (first = 1)) then
while (trn_tdst_rdy_n = '1') loop
wait until (trn_clk'event and trn_clk = '1');
end loop;
end if;
if (first = 1) then
if (trn_trem_n_c = X"00") then --"00000000") then
last := 0;
else
last := 1;
end if;
PROC_READ_DATA(last, trn_td_c, trn_trem_n_c);
end if;
if (last_call = 1) then
PROC_PARSE_FRAME;
end if;
end PROC_TX_SYNCHRONIZE;
--************************************************************
-- Proc : PROC_TX_TYPE0_CONFIGURATION_READ
-- Inputs : Tag, PCI/PCI-Express Reg Address, First BypeEn
-- Outputs : Transaction Tx Interface Signaling
-- Description : Generates a Type 0 Configuration Read TLP
--*************************************************************/
procedure PROC_TX_TYPE0_CONFIGURATION_READ (
tag : in std_logic_vector (7 downto 0);
reg_addr : in std_logic_vector (11 downto 0);
first_dw_be : in std_logic_vector (3 downto 0);
signal trn_td_c : out std_logic_vector(63 downto 0);
signal trn_tsof_n : out std_logic;
signal trn_teof_n : out std_logic;
signal trn_trem_n_c : out std_logic_vector(7 downto 0);
signal trn_tsrc_rdy_n : out std_logic;
signal trn_lnk_up_n : in std_logic;
signal trn_tdst_rdy_n : in std_logic;
signal trn_clk : in std_logic
) is
begin
assert (trn_lnk_up_n = '0')
report "TX Trn interface is MIA"
severity failure;
PROC_TX_SYNCHRONIZE(0, 0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
trn_td_c <= '0' &
"00" &
"00100" &
'0' &
"000" &
"0000" &
'0' &
'0' &
"00" &
"00" &
"0000000001" &
COMPLETER_ID_CFG &
tag(7 downto 0) &
"0000" &
first_dw_be(3 downto 0);
trn_tsof_n <= '0';
trn_teof_n <= '1';
trn_trem_n_c <= X"00";
trn_tsrc_rdy_n <= '0';
PROC_TX_SYNCHRONIZE(1,0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
trn_td_c <= COMPLETER_ID_CFG &
"0000" &
reg_addr(11 downto 2) &
"00" &
X"00000000";
trn_tsof_n <= '1';
trn_teof_n <= '0';
trn_trem_n_c <= X"0F";
trn_tsrc_rdy_n <= '0';
PROC_TX_SYNCHRONIZE(1, 1, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
trn_teof_n <= '1';
trn_trem_n_c <= X"00";
trn_tsrc_rdy_n <= '1';
end PROC_TX_TYPE0_CONFIGURATION_READ;
--************************************************************
-- Proc : PROC_TX_TYPE0_CONFIGURATION_WRITE
-- Inputs : Tag, PCI/PCI-Express Reg Address, First BypeEn
-- Outputs : Transaction Tx Interface Signaling
-- Description : Generates a Type 0 Configuration Write TLP
--*************************************************************/
procedure PROC_TX_TYPE0_CONFIGURATION_WRITE (
tag : in std_logic_vector (7 downto 0);
reg_addr : in std_logic_vector (11 downto 0);
reg_data : in std_logic_vector (31 downto 0);
first_dw_be : in std_logic_vector (3 downto 0);
signal trn_td_c : out std_logic_vector(63 downto 0);
signal trn_tsof_n : out std_logic;
signal trn_teof_n : out std_logic;
signal trn_trem_n_c : out std_logic_vector(7 downto 0);
signal trn_tsrc_rdy_n : out std_logic;
signal trn_lnk_up_n : in std_logic;
signal trn_tdst_rdy_n : in std_logic;
signal trn_clk : in std_logic
) is
begin
assert (trn_lnk_up_n = '0')
report "TX Trn interface is MIA"
severity failure;
PROC_TX_SYNCHRONIZE(0, 0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
trn_td_c <= '0' &
"10" &
"00100" &
'0' &
"000" &
"0000" &
'0' &
'0' &
"00" &
"00" &
"0000000001" &
COMPLETER_ID_CFG &
tag(7 downto 0) &
"0000" &
first_dw_be(3 downto 0);
trn_tsof_n <= '0';
trn_tsrc_rdy_n <= '0';
PROC_TX_SYNCHRONIZE(1,0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
trn_td_c <= COMPLETER_ID_CFG &
"0000" &
reg_addr(11 downto 2) &
"00" &
reg_data(7 downto 0) &
reg_data(15 downto 8) &
reg_data(23 downto 16) &
reg_data(31 downto 24);
trn_tsof_n <= '1';
trn_teof_n <= '0';
trn_trem_n_c <= X"00";
PROC_TX_SYNCHRONIZE(1, 1, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
trn_teof_n <= '1';
trn_tsrc_rdy_n <= '1';
end PROC_TX_TYPE0_CONFIGURATION_WRITE;
--************************************************************
-- Proc : PROC_TX_TYPE1_CONFIGURATION_READ
-- Inputs : Tag, PCI/PCI-Express Reg Address, First BypeEn
-- Outputs : Transaction Tx Interface Signaling
-- Description : Generates a Type 1 Configuration Read TLP
--*************************************************************/
procedure PROC_TX_TYPE1_CONFIGURATION_READ (
tag : in std_logic_vector (7 downto 0);
reg_addr : in std_logic_vector (11 downto 0);
first_dw_be : in std_logic_vector (3 downto 0);
signal trn_td_c : out std_logic_vector(63 downto 0);
signal trn_tsof_n : out std_logic;
signal trn_teof_n : out std_logic;
signal trn_trem_n_c : out std_logic_vector(7 downto 0);
signal trn_tsrc_rdy_n : out std_logic;
signal trn_lnk_up_n : in std_logic;
signal trn_tdst_rdy_n : in std_logic;
signal trn_clk : in std_logic
) is
begin
assert (trn_lnk_up_n = '0')
report "TX Trn interface is MIA"
severity failure;
PROC_TX_SYNCHRONIZE(0, 0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
trn_td_c <= '0' &
"00" &
"00101" &
'0' &
"000" &
"0000" &
'0' &
'0' &
"00" &
"00" &
"0000000001" &
COMPLETER_ID_CFG &
tag(7 downto 0) &
"0000" &
first_dw_be(3 downto 0);
trn_tsof_n <= '0';
trn_teof_n <= '1';
trn_trem_n_c <= X"00";
trn_tsrc_rdy_n <= '0';
PROC_TX_SYNCHRONIZE(1,0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
trn_td_c <= COMPLETER_ID_CFG &
"0000" &
reg_addr(11 downto 2) &
"00" &
X"00000000";
trn_tsof_n <= '1';
trn_teof_n <= '0';
trn_trem_n_c <= X"0F";
trn_tsrc_rdy_n <= '0';
PROC_TX_SYNCHRONIZE(1, 1, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
trn_teof_n <= '1';
trn_trem_n_c <= X"00";
trn_tsrc_rdy_n <= '1';
end PROC_TX_TYPE1_CONFIGURATION_READ;
--************************************************************
-- Proc : PROC_TX_TYPE1_CONFIGURATION_WRITE
-- Inputs : Tag, PCI/PCI-Express Reg Address, First BypeEn
-- Outputs : Transaction Tx Interface Signaling
-- Description : Generates a Type 1 Configuration Write TLP
--*************************************************************/
procedure PROC_TX_TYPE1_CONFIGURATION_WRITE (
tag : in std_logic_vector (7 downto 0);
reg_addr : in std_logic_vector (11 downto 0);
reg_data : in std_logic_vector (31 downto 0);
first_dw_be : in std_logic_vector (3 downto 0);
signal trn_td_c : out std_logic_vector(63 downto 0);
signal trn_tsof_n : out std_logic;
signal trn_teof_n : out std_logic;
signal trn_trem_n_c : out std_logic_vector(7 downto 0);
signal trn_tsrc_rdy_n : out std_logic;
signal trn_lnk_up_n : in std_logic;
signal trn_tdst_rdy_n : in std_logic;
signal trn_clk : in std_logic
) is
begin
assert (trn_lnk_up_n = '0')
report "TX Trn interface is MIA"
severity failure;
PROC_TX_SYNCHRONIZE(0, 0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
trn_td_c <= '0' &
"10" &
"00101" &
'0' &
"000" &
"0000" &
'0' &
'0' &
"00" &
"00" &
"0000000001" &
COMPLETER_ID_CFG &
tag(7 downto 0) &
"0000" &
first_dw_be(3 downto 0);
trn_tsof_n <= '0';
trn_tsrc_rdy_n <= '0';
PROC_TX_SYNCHRONIZE(1,0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
trn_td_c <= COMPLETER_ID_CFG &
"0000" &
reg_addr(11 downto 2) &
"00" &
reg_data(7 downto 0) &
reg_data(15 downto 8) &
reg_data(23 downto 16) &
reg_data(31 downto 24);
trn_tsof_n <= '1';
trn_teof_n <= '0';
trn_trem_n_c <= X"00";
PROC_TX_SYNCHRONIZE(1, 1, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
trn_teof_n <= '1';
trn_tsrc_rdy_n <= '1';
end PROC_TX_TYPE1_CONFIGURATION_WRITE;
--************************************************************
-- Procedure : PROC_TX_MEMORY_READ_32
-- Inputs : Tag, Length, Address, Last Byte En, First Byte En
-- Outputs : Transaction Tx Interface Signaling
-- Description : Generates a Memory Read 32 TLP
--*************************************************************/
procedure PROC_TX_MEMORY_READ_32 (
tag : in std_logic_vector (7 downto 0);
tc : in std_logic_vector (2 downto 0);
len : in std_logic_vector (9 downto 0);
addr : in std_logic_vector (31 downto 0);
last_dw_be : in std_logic_vector (3 downto 0);
first_dw_be : in std_logic_vector (3 downto 0);
signal trn_td_c : out std_logic_vector(63 downto 0);
signal trn_tsof_n : out std_logic;
signal trn_teof_n : out std_logic;
signal trn_trem_n_c : out std_logic_vector(7 downto 0);
signal trn_tsrc_rdy_n : out std_logic;
signal trn_lnk_up_n : in std_logic;
signal trn_tdst_rdy_n : in std_logic;
signal trn_clk : in std_logic
) is
begin
assert (trn_lnk_up_n = '0')
report "TX Trn interface is MIA"
severity failure;
PROC_TX_SYNCHRONIZE(0, 0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
trn_td_c <= '0' &
"00" &
"00000" &
'0' &
tc(2 downto 0) &
"0000" &
'0' &
'0' &
"00" &
"00" &
len(9 downto 0) &
COMPLETER_ID_CFG &
tag(7 downto 0) &
last_dw_be(3 downto 0) &
first_dw_be(3 downto 0);
trn_tsof_n <= '0';
trn_teof_n <= '1';
trn_trem_n_c <= X"00";
trn_tsrc_rdy_n <= '0';
PROC_TX_SYNCHRONIZE(1,0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
trn_td_c <= addr(31 downto 2) &
"00" &
X"00000000";
trn_tsof_n <= '1';
trn_teof_n <= '0';
trn_trem_n_c <= X"0F";
trn_tsrc_rdy_n <= '0';
PROC_TX_SYNCHRONIZE(1, 1, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
trn_teof_n <= '1';
trn_trem_n_c <= X"00";
trn_tsrc_rdy_n <= '1';
end PROC_TX_MEMORY_READ_32;
--************************************************************
-- Proc : PROC_TX_MEMORY_READ_64
-- Inputs : Tag, Length, Address, Last Byte En, First Byte En
-- Outputs : Transaction Tx Interface Signaling
-- Description : Generates a Memory Read 64 TLP
--*************************************************************/
procedure PROC_TX_MEMORY_READ_64 (
tag : in std_logic_vector (7 downto 0);
tc : in std_logic_vector (2 downto 0);
len : in std_logic_vector (9 downto 0);
addr : in std_logic_vector (63 downto 0);
last_dw_be : in std_logic_vector (3 downto 0);
first_dw_be : in std_logic_vector (3 downto 0);
signal trn_td_c : out std_logic_vector(63 downto 0);
signal trn_tsof_n : out std_logic;
signal trn_teof_n : out std_logic;
signal trn_trem_n_c : out std_logic_vector(7 downto 0);
signal trn_tsrc_rdy_n : out std_logic;
signal trn_lnk_up_n : in std_logic;
signal trn_tdst_rdy_n : in std_logic;
signal trn_clk : in std_logic
) is
begin
assert (trn_lnk_up_n = '0')
report "TX Trn interface is MIA"
severity failure;
PROC_TX_SYNCHRONIZE(0, 0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
trn_td_c <= '0' &
"01" &
"00000" &
'0' &
tc(2 downto 0) &
"0000" &
'0' &
'0' &
"00" &
"00" &
len(9 downto 0) &
COMPLETER_ID_CFG &
tag(7 downto 0) &
last_dw_be(3 downto 0) &
first_dw_be(3 downto 0);
trn_tsof_n <= '0';
trn_teof_n <= '1';
trn_trem_n_c <= X"00";
trn_tsrc_rdy_n <= '0';
PROC_TX_SYNCHRONIZE(1,0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
trn_td_c <= addr(63 downto 2) &
"00";
trn_tsof_n <= '1';
trn_teof_n <= '0';
trn_trem_n_c <= X"00";
trn_tsrc_rdy_n <= '0';
PROC_TX_SYNCHRONIZE(1, 1, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
trn_teof_n <= '1';
trn_trem_n_c <= X"00";
trn_tsrc_rdy_n <= '1';
end PROC_TX_MEMORY_READ_64;
--************************************************************
-- Proc : PROC_TX_MEMORY_WRITE_32
-- Inputs : Tag, Length, Address, Last Byte En, First Byte En
-- Outputs : Transaction Tx Interface Signaling
-- Description : Generates a Memory Write 32 TLP
--*************************************************************/
procedure PROC_TX_MEMORY_WRITE_32 (
tag : in std_logic_vector (7 downto 0);
tc : in std_logic_vector (2 downto 0);
len : in std_logic_vector (9 downto 0);
addr : in std_logic_vector (31 downto 0);
last_dw_be : in std_logic_vector (3 downto 0);
first_dw_be : in std_logic_vector (3 downto 0);
ep : in std_logic;
signal trn_td_c : out std_logic_vector(63 downto 0);
signal trn_tsof_n : out std_logic;
signal trn_teof_n : out std_logic;
signal trn_trem_n_c : out std_logic_vector(7 downto 0);
signal trn_tsrc_rdy_n : out std_logic;
signal trn_terrfwd_n : out std_logic;
signal trn_lnk_up_n : in std_logic;
signal trn_tdst_rdy_n : in std_logic;
signal trn_clk : in std_logic
) is
variable length : std_logic_vector(9 downto 0);
variable i : INTEGER;
variable int_length : INTEGER;
variable unsigned_length : unsigned(9 downto 0);
begin
assert (trn_lnk_up_n = '0')
report "TX Trn interface is MIA"
severity failure;
if (len = "0000000000") then
length := "1000000000"; --1024
else
length := len;
end if;
PROC_TX_SYNCHRONIZE(0, 0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
trn_td_c <= '0' &
"10" &
"00000" &
'0' &
tc(2 downto 0) &
"0000" &
'0' &
'0' &
"00" &
"00" &
len(9 downto 0) &
COMPLETER_ID_CFG &
tag(7 downto 0) &
last_dw_be(3 downto 0) &
first_dw_be(3 downto 0);
trn_tsof_n <= '0';
trn_teof_n <= '1';
trn_trem_n_c <= X"00";
trn_tsrc_rdy_n <= '0';
PROC_TX_SYNCHRONIZE(1,0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
trn_td_c <= addr(31 downto 2) &
"00" &
DATA_STORE(0) &
DATA_STORE(1) &
DATA_STORE(2) &
DATA_STORE(3);
trn_tsof_n <= '1';
if (length /= "0000000001") then
unsigned_length := unsigned(length);
int_length := to_integer( unsigned_length);
i := 4;
while (i < (int_length * 4)) loop
PROC_TX_SYNCHRONIZE(1,0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
trn_td_c <= DATA_STORE(i+0) &
DATA_STORE(i+1) &
DATA_STORE(i+2) &
DATA_STORE(i+3) &
DATA_STORE(i+4) &
DATA_STORE(i+5) &
DATA_STORE(i+6) &
DATA_STORE(i+7);
if ((i+7) >= ((int_length*4)-1) ) then
trn_teof_n <= '0';
if (ep = '1') then
trn_terrfwd_n <= '0';
end if;
if (((int_length - 1) mod 2) = 0) then
trn_trem_n_c <= X"00";
else
trn_trem_n_c <= X"0F";
end if;
end if;
i := i + 8;
end loop;
else
trn_teof_n <= '0';
if (ep = '1') then
trn_terrfwd_n <= '0';
end if;
trn_trem_n_c <= X"00";
end if;
PROC_TX_SYNCHRONIZE(1, 1, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
trn_teof_n <= '1';
trn_trem_n_c <= X"00";
trn_terrfwd_n <= '1';
trn_tsrc_rdy_n <= '1';
end PROC_TX_MEMORY_WRITE_32;
--************************************************************
-- Proc : PROC_TX_MEMORY_WRITE_64
-- Inputs : Tag, Length, Address, Last Byte En, First Byte En
-- Outputs : Transaction Tx Interface Signaling
-- Description : Generates a Memory Write 64 TLP
--*************************************************************/
procedure PROC_TX_MEMORY_WRITE_64 (
tag : in std_logic_vector (7 downto 0);
tc : in std_logic_vector (2 downto 0);
len : in std_logic_vector (9 downto 0);
addr : in std_logic_vector (63 downto 0);
last_dw_be : in std_logic_vector (3 downto 0);
first_dw_be : in std_logic_vector (3 downto 0);
ep : in std_logic;
signal trn_td_c : out std_logic_vector(63 downto 0);
signal trn_tsof_n : out std_logic;
signal trn_teof_n : out std_logic;
signal trn_trem_n_c : out std_logic_vector(7 downto 0);
signal trn_tsrc_rdy_n : out std_logic;
signal trn_terrfwd_n : out std_logic;
signal trn_lnk_up_n : in std_logic;
signal trn_tdst_rdy_n : in std_logic;
signal trn_clk : in std_logic
) is
variable length : std_logic_vector(9 downto 0);
variable i : INTEGER;
variable int_length : INTEGER;
variable unsigned_length : unsigned(9 downto 0);
begin
assert (trn_lnk_up_n = '0')
report "TX Trn interface is MIA"
severity failure;
if (len = "0000000000") then
length := "1000000000"; --1024
else
length := len;
end if;
PROC_TX_SYNCHRONIZE(0, 0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
trn_td_c <= '0' &
"11" &
"00000" &
'0' &
tc(2 downto 0) &
"0000" &
'0' &
'0' &
"00" &
"00" &
len(9 downto 0) &
COMPLETER_ID_CFG &
tag(7 downto 0) &
last_dw_be(3 downto 0) &
first_dw_be(3 downto 0);
trn_tsof_n <= '0';
trn_teof_n <= '1';
trn_trem_n_c <= X"00";
trn_tsrc_rdy_n <= '0';
PROC_TX_SYNCHRONIZE(1,0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
trn_td_c <= addr(63 downto 2) &
"00" ;
trn_tsof_n <= '1';
unsigned_length := unsigned(length);
int_length := to_integer( unsigned_length);
if (int_length = 1) then
DATA_STORE(4) := X"00";
DATA_STORE(5) := X"00";
DATA_STORE(6) := X"00";
DATA_STORE(7) := X"00";
end if;
i := 0;
while (i < (int_length * 4)) loop
PROC_TX_SYNCHRONIZE(1,0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
trn_td_c <= DATA_STORE(i+0) &
DATA_STORE(i+1) &
DATA_STORE(i+2) &
DATA_STORE(i+3) &
DATA_STORE(i+4) &
DATA_STORE(i+5) &
DATA_STORE(i+6) &
DATA_STORE(i+7);
if ((i+7) >= ((int_length*4)-1) ) then
trn_teof_n <= '0';
if (ep = '1') then
trn_terrfwd_n <= '0';
end if;
if ((int_length mod 2) = 0) then
trn_trem_n_c <= X"00";
else
trn_trem_n_c <= X"0F";
end if;
end if;
i := i + 8;
end loop;
PROC_TX_SYNCHRONIZE(1, 1, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
trn_teof_n <= '1';
trn_terrfwd_n <= '1';
trn_trem_n_c <= X"00";
trn_tsrc_rdy_n <= '1';
end PROC_TX_MEMORY_WRITE_64;
--************************************************************
-- Proc : PROC_TX_COMPLETION_
-- Inputs : Tag, Tc, Length, Completion Status
-- Outputs : Transaction Tx Interface Signaling
-- Description : Generates a Completion TLP
--*************************************************************/
procedure PROC_TX_COMPLETION (
tag : in std_logic_vector (7 downto 0);
tc : in std_logic_vector (2 downto 0);
len : in std_logic_vector (9 downto 0);
comp_status : in std_logic_vector (2 downto 0);
signal trn_td_c : out std_logic_vector(63 downto 0);
signal trn_tsof_n : out std_logic;
signal trn_teof_n : out std_logic;
signal trn_trem_n_c : out std_logic_vector(7 downto 0);
signal trn_tsrc_rdy_n : out std_logic;
signal trn_lnk_up_n : in std_logic;
signal trn_tdst_rdy_n : in std_logic;
signal trn_clk : in std_logic
) is
begin
assert (trn_lnk_up_n = '0')
report "TX Trn interface is MIA"
severity failure;
PROC_TX_SYNCHRONIZE(0, 0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
trn_td_c <= '0' &
"00" &
"01010" &
'0' &
tc(2 downto 0) &
"0000" &
'0' &
'0' &
"00" &
"00" &
len(9 downto 0) &
COMPLETER_ID_CFG &
comp_status(2 downto 0) &
'0' &
X"000";
trn_tsof_n <= '0';
trn_teof_n <= '1';
trn_trem_n_c <= X"00";
trn_tsrc_rdy_n <= '0';
PROC_TX_SYNCHRONIZE(1,0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
trn_td_c <= COMPLETER_ID_CFG &
tag(7 downto 0) &
X"00" &
X"00000000";
trn_tsof_n <= '1';
trn_teof_n <= '0';
trn_trem_n_c <= X"0F";
PROC_TX_SYNCHRONIZE(1, 1, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
trn_teof_n <= '1';
trn_trem_n_c <= X"00";
trn_tsrc_rdy_n <= '1';
end PROC_TX_COMPLETION;
--************************************************************
-- Proc : PROC_TX_COMPLETION_DATA_
-- Inputs : Tag, Tc, Length, Completion Status
-- Outputs : Transaction Tx Interface Signaling
-- Description : Generates a Completion with Data TLP
--*************************************************************/
procedure PROC_TX_COMPLETION_DATA (
tag : in std_logic_vector (7 downto 0);
tc : in std_logic_vector (2 downto 0);
len : in std_logic_vector (9 downto 0);
byte_count : in std_logic_vector (11 downto 0);
lower_addr : in std_logic_vector (6 downto 0);
comp_status : in std_logic_vector (2 downto 0);
ep : in std_logic;
signal trn_td_c : out std_logic_vector(63 downto 0);
signal trn_tsof_n : out std_logic;
signal trn_teof_n : out std_logic;
signal trn_trem_n_c : out std_logic_vector(7 downto 0);
signal trn_tsrc_rdy_n : out std_logic;
signal trn_terrfwd_n : out std_logic;
signal trn_lnk_up_n : in std_logic;
signal trn_tdst_rdy_n : in std_logic;
signal trn_clk : in std_logic
) is
variable length : std_logic_vector(9 downto 0);
variable i : INTEGER;
variable int_length : INTEGER;
variable unsigned_length : unsigned(9 downto 0);
begin
assert (trn_lnk_up_n = '0')
report "TX Trn interface is MIA"
severity failure;
if (len = "0000000000") then
length := "1000000000"; --1024
else
length := len;
end if;
PROC_TX_SYNCHRONIZE(0, 0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
trn_td_c <= '0' &
"10" &
"01010" &
'0' &
tc(2 downto 0) &
"0000" &
'0' &
'0' &
"00" &
"00" &
len(9 downto 0) &
COMPLETER_ID_CFG &
comp_status(2 downto 0) &
'0' &
byte_count(11 downto 0);
trn_tsof_n <= '0';
trn_teof_n <= '1';
trn_trem_n_c <= X"00";
trn_tsrc_rdy_n <= '0';
PROC_TX_SYNCHRONIZE(1,0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
trn_td_c <= COMPLETER_ID_CFG &
tag(7 downto 0) &
'0' &
lower_addr(6 downto 0) &
DATA_STORE(0) &
DATA_STORE(1) &
DATA_STORE(2) &
DATA_STORE(3);
trn_tsof_n <= '1';
if (length /= "0000000001") then
unsigned_length := unsigned(length);
int_length := to_integer( unsigned_length);
i := 4;
while (i < (int_length * 4)) loop
PROC_TX_SYNCHRONIZE(1,0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
trn_td_c <= DATA_STORE(i+0) &
DATA_STORE(i+1) &
DATA_STORE(i+2) &
DATA_STORE(i+3) &
DATA_STORE(i+4) &
DATA_STORE(i+5) &
DATA_STORE(i+6) &
DATA_STORE(i+7);
if ((i+7) >= ((int_length*4)-1) ) then
trn_teof_n <= '0';
if (ep = '1') then
trn_terrfwd_n <= '0';
end if;
if (((int_length - 1) mod 2) = 0) then
trn_trem_n_c <= X"00";
else
trn_trem_n_c <= X"0F";
end if;
end if;
i := i + 8;
end loop;
else
trn_teof_n <= '0';
if (ep = '1') then
trn_terrfwd_n <= '0';
end if;
trn_trem_n_c <= X"00";
end if;
PROC_TX_SYNCHRONIZE(1, 1, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
trn_teof_n <= '1';
trn_terrfwd_n <= '1';
trn_trem_n_c <= X"00";
trn_tsrc_rdy_n <= '1';
end PROC_TX_COMPLETION_DATA;
--************************************************************
-- Proc : PROC_TX_MESSAGE
-- Inputs : Tag, TC, Address, Message Routing, Message Code
-- Outputs : Transaction Tx Interface Signaling
-- Description : Generates a Message TLP
--*************************************************************/
procedure PROC_TX_MESSAGE (
tag : in std_logic_vector (7 downto 0);
tc : in std_logic_vector (2 downto 0);
len : in std_logic_vector (9 downto 0);
data : in std_logic_vector (63 downto 0);
message_rtg : in std_logic_vector (2 downto 0);
message_code : in std_logic_vector (7 downto 0);
signal trn_td_c : out std_logic_vector(63 downto 0);
signal trn_tsof_n : out std_logic;
signal trn_teof_n : out std_logic;
signal trn_trem_n_c : out std_logic_vector(7 downto 0);
signal trn_tsrc_rdy_n : out std_logic;
signal trn_lnk_up_n : in std_logic;
signal trn_tdst_rdy_n : in std_logic;
signal trn_clk : in std_logic
) is
begin
assert (trn_lnk_up_n = '0')
report "TX Trn interface is MIA"
severity failure;
PROC_TX_SYNCHRONIZE(0, 0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
trn_td_c <= '0' &
"01" &
"10" & message_rtg(2 downto 0) &
'0' &
tc(2 downto 0) &
"0000" &
'0' &
'0' &
"00" &
"00" &
"0000000000" &
COMPLETER_ID_CFG &
tag(7 downto 0) &
message_code(7 downto 0);
trn_tsof_n <= '0';
trn_teof_n <= '1';
trn_trem_n_c <= X"00";
trn_tsrc_rdy_n <= '0';
PROC_TX_SYNCHRONIZE(1,0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
trn_td_c <= data;
trn_tsof_n <= '1';
trn_teof_n <= '0';
trn_trem_n_c <= X"00";
PROC_TX_SYNCHRONIZE(1, 1, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
trn_teof_n <= '1';
trn_trem_n_c <= X"00";
trn_tsrc_rdy_n <= '1';
end PROC_TX_MESSAGE;
--************************************************************
-- Proc : PROC_TX_MESSAGE_DATA
-- Inputs : Tag, TC, Address, Message Routing, Message Code
-- Outputs : Transaction Tx Interface Signaling
-- Description : Generates a Message Data TLP
--*************************************************************/
procedure PROC_TX_MESSAGE_DATA (
tag : in std_logic_vector (7 downto 0);
tc : in std_logic_vector (2 downto 0);
len : in std_logic_vector (9 downto 0);
data : in std_logic_vector (63 downto 0);
message_rtg : in std_logic_vector (2 downto 0);
message_code : in std_logic_vector (7 downto 0);
signal trn_td_c : out std_logic_vector(63 downto 0);
signal trn_tsof_n : out std_logic;
signal trn_teof_n : out std_logic;
signal trn_trem_n_c : out std_logic_vector(7 downto 0);
signal trn_tsrc_rdy_n : out std_logic;
signal trn_lnk_up_n : in std_logic;
signal trn_tdst_rdy_n : in std_logic;
signal trn_clk : in std_logic
) is
variable length : std_logic_vector(9 downto 0);
variable i : INTEGER;
variable int_length : INTEGER;
variable unsigned_length : unsigned(9 downto 0);
begin
assert (trn_lnk_up_n = '0')
report "TX Trn interface is MIA"
severity failure;
if (len = "0000000000") then
length := "1000000000"; --1024
else
length := len;
end if;
PROC_TX_SYNCHRONIZE(0, 0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
trn_td_c <= '0' &
"11" &
"10" & message_rtg(2 downto 0) &
'0' &
tc(2 downto 0) &
"0000" &
'0' &
'0' &
"00" &
"00" &
length(9 downto 0) &
COMPLETER_ID_CFG &
tag(7 downto 0) &
message_code(7 downto 0);
trn_tsof_n <= '0';
trn_teof_n <= '1';
trn_trem_n_c <= X"00";
trn_tsrc_rdy_n <= '0';
PROC_TX_SYNCHRONIZE(1,0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
trn_td_c <= data;
trn_tsof_n <= '1';
unsigned_length := unsigned(length);
int_length := to_integer( unsigned_length);
i := 0;
while (i < (int_length * 4)) loop
PROC_TX_SYNCHRONIZE(1,0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
trn_td_c <= DATA_STORE(i+0) &
DATA_STORE(i+1) &
DATA_STORE(i+2) &
DATA_STORE(i+3) &
DATA_STORE(i+4) &
DATA_STORE(i+5) &
DATA_STORE(i+6) &
DATA_STORE(i+7);
if ((i+7) >= ((int_length*4)-1) ) then
trn_teof_n <= '0';
if ((int_length mod 2) = 0) then
trn_trem_n_c <= X"00";
else
trn_trem_n_c <= X"0F";
end if;
end if;
i := i + 8;
end loop;
PROC_TX_SYNCHRONIZE(1, 1, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
trn_teof_n <= '1';
trn_trem_n_c <= X"00";
trn_tsrc_rdy_n <= '1';
end PROC_TX_MESSAGE_DATA;
--************************************************************
-- Proc : PROC_TX_IO_READ
-- Inputs : Tag, Address
-- Outputs : Transaction Tx Interface Signaling
-- Description : Generates a IO Read TLP
--*************************************************************/
procedure PROC_TX_IO_READ (
tag : in std_logic_vector (7 downto 0);
addr : in std_logic_vector (31 downto 0);
first_dw_be : in std_logic_vector (3 downto 0);
signal trn_td_c : out std_logic_vector(63 downto 0);
signal trn_tsof_n : out std_logic;
signal trn_teof_n : out std_logic;
signal trn_trem_n_c : out std_logic_vector(7 downto 0);
signal trn_tsrc_rdy_n : out std_logic;
signal trn_lnk_up_n : in std_logic;
signal trn_tdst_rdy_n : in std_logic;
signal trn_clk : in std_logic
) is
begin
assert (trn_lnk_up_n = '0')
report "TX Trn interface is MIA"
severity failure;
PROC_TX_SYNCHRONIZE(0, 0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
trn_td_c <= '0' &
"00" &
"00010" &
'0' &
"000" &
"0000" &
'0' &
'0' &
"00" &
"00" &
"0000000001" &
COMPLETER_ID_CFG &
tag(7 downto 0) &
"0000" &
first_dw_be(3 downto 0);
trn_tsof_n <= '0';
trn_teof_n <= '1';
trn_trem_n_c <= X"00";
trn_tsrc_rdy_n <= '0';
PROC_TX_SYNCHRONIZE(1,0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
trn_td_c <= addr(31 downto 2) &
"00" &
X"00000000";
trn_tsof_n <= '1';
trn_teof_n <= '0';
trn_trem_n_c <= X"0F";
trn_tsrc_rdy_n <= '0';
PROC_TX_SYNCHRONIZE(1, 1, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
trn_teof_n <= '1';
trn_trem_n_c <= X"00";
trn_tsrc_rdy_n <= '1';
end PROC_TX_IO_READ;
--************************************************************
-- Proc : PROC_TX_IO_WRITE
-- Inputs : Tag, Address, Data
-- Outputs : Transaction Tx Interface Signaling
-- Description : Generates a IO Read TLP
--*************************************************************/
procedure PROC_TX_IO_WRITE (
tag : in std_logic_vector (7 downto 0);
addr : in std_logic_vector (31 downto 0);
first_dw_be : in std_logic_vector (3 downto 0);
data : in std_logic_vector(31 downto 0);
signal trn_td_c : out std_logic_vector(63 downto 0);
signal trn_tsof_n : out std_logic;
signal trn_teof_n : out std_logic;
signal trn_trem_n_c : out std_logic_vector(7 downto 0);
signal trn_tsrc_rdy_n : out std_logic;
signal trn_lnk_up_n : in std_logic;
signal trn_tdst_rdy_n : in std_logic;
signal trn_clk : in std_logic
) is
begin
assert (trn_lnk_up_n = '0')
report "TX Trn interface is MIA"
severity failure;
PROC_TX_SYNCHRONIZE(0, 0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
trn_td_c <= '0' &
"10" &
"00010" &
'0' &
"000" &
"0000" &
'0' &
'0' &
"00" &
"00" &
"0000000001" &
COMPLETER_ID_CFG &
tag(7 downto 0) &
"0000" &
first_dw_be(3 downto 0);
trn_tsof_n <= '0';
trn_teof_n <= '1';
trn_trem_n_c <= X"00";
trn_tsrc_rdy_n <= '0';
PROC_TX_SYNCHRONIZE(1,0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
trn_td_c <= addr(31 downto 2) &
"00" &
data(7 downto 0) &
data(15 downto 8) &
data(23 downto 16) &
data(31 downto 24);
trn_tsof_n <= '1';
trn_teof_n <= '0';
trn_trem_n_c <= X"00";
PROC_TX_SYNCHRONIZE(1, 1, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
trn_teof_n <= '1';
trn_trem_n_c <= X"00";
trn_tsrc_rdy_n <= '1';
end PROC_TX_IO_WRITE;
--************************************************************
-- Proc : PROC_USR_DATA_SETUP_SEQ
-- Inputs : None
-- Outputs : None
-- Description : Populates scratch pad data area with known good data.
--*************************************************************/
procedure PROC_USR_DATA_SETUP_SEQ is
variable i : INTEGER;
variable unsigned_i : unsigned(7 downto 0);
variable vector_i : std_logic_vector(7 downto 0);
begin
for i in 0 to 4095 loop
unsigned_i := to_unsigned(i, 8);
vector_i := std_logic_vector(unsigned_i);
DATA_STORE(i) := vector_i(7 downto 0);
end loop;
end PROC_USR_DATA_SETUP_SEQ;
--************************************************************
-- Proc : PROC_SET_READ_DATA
-- Inputs : Data
-- Outputs : None
-- Description : Set read data to known value
--*************************************************************/
procedure PROC_SET_READ_DATA (
be : in std_logic_vector(3 downto 0);
data : in std_logic_vector(31 downto 0)
) is
begin
P_READ_DATA := data;
end PROC_SET_READ_DATA;
--************************************************************
-- Proc : PROC_WAIT_FOR_READ_DATA
-- Inputs : None
-- Outputs : Read data P_READ_DATA will be valid
-- Description : This task must be executed
-- immediately following a read call
-- in order for the read process to function
-- correctly.
--*************************************************************/
procedure PROC_WAIT_FOR_READ_DATA (
signal tx_rx_read_data_valid : out std_logic;
signal rx_tx_read_data_valid : in std_logic;
signal rx_tx_read_data : in std_logic_vector(31 downto 0);
signal trn_clk : in std_logic
) is
variable j : INTEGER;
begin
j := 10;
tx_rx_read_data_valid <= '1';
while (rx_tx_read_data_valid = '0') loop
wait until (trn_clk'event and trn_clk = '1');
end loop;
P_READ_DATA := rx_tx_read_data;
tx_rx_read_data_valid <= '0'; -- indicate to rx_app to make rx_tx_valid = 0
wait until rx_tx_read_data_valid = '0';
end PROC_WAIT_FOR_READ_DATA;
--***********************************************************
-- Procedure : PROC_DISPLAY_PCIE_MAP
-- Inputs : none
-- Outputs : none
-- Description : Displays the Memory Manager's P_MAP calculations
-- based on range values read from PCI_E device.
--*************************************************************/
procedure PROC_DISPLAY_PCIE_MAP (
BAR : THIRTY_THREE_BIT_ARRAY;
BAR_ENABLED : ENABLE_ARRAY;
BAR_RANGE : DWORD_ARRAY
) is
variable i : INTEGER;
variable L : line;
variable func_result : std_logic_vector(31 downto 0);
begin
for i in 0 to 6 loop
write (L, String'(" BAR "));
hwrite(L, std_logic_vector(to_unsigned(i, 4)));
write (L, String'(" = 0x"));
hwrite(L, BAR(i)(31 downto 0));
write (L, String'(" RANGE = 0x"));
hwrite(L, BAR_RANGE(i)(31 downto 0));
case BAR_ENABLED(i) is
when 1 => write (L, String'(" IO MAPPED"));
when 2 => write (L, String'(" MEM32 MAPPED"));
when 3 => write (L, String'(" MEM64 MAPPED"));
when others => write (L, String'(" DISABLED"));
end case;
writeline (output, L);
end loop;
end PROC_DISPLAY_PCIE_MAP;
--*************************************************************
-- Procedure : PROC_BUILD_PCIE_MAP
-- Inputs :
-- Outputs :
-- Description : Looks at range values read from config space and
-- builds corresponding mem/io map
--*************************************************************/
procedure PROC_BUILD_PCIE_MAP
is
variable i : INTEGER;
variable L : line;
variable RANGE_VALUE : std_logic_vector(31 downto 0);
begin
writeNowToScreen(String'("PCI EXPRESS BAR MEMORY/IO MAPPING PROCESS BEGUN.."));
BAR(0) := '0' & X"10000000";
BAR(1) := '0' & X"20000000";
BAR(2) := '0' & X"30000000";
BAR(3) := '0' & X"40000000";
BAR(4) := '0' & X"50000000";
BAR(5) := '0' & X"60000000";
BAR(6) := '0' & X"70000001"; -- bit 0 must be set to enable the EROM
i := 0;
while (i <= 6) loop
RANGE_VALUE := BAR_RANGE(i);
if (RANGE_VALUE = X"00000000") then
BAR_ENABLED(i) := 0; -- Disabled
BAR(i) := '0' & X"00000000";
else
if ((RANGE_VALUE(0) = '1') and (i /= 6)) then
BAR_ENABLED(i) := 1; -- IO
NUMBER_OF_IO_BARS := NUMBER_OF_IO_BARS + 1;
if (pio_check_design and (NUMBER_OF_IO_BARS >1)) then
write (L, String'("Warning: PIO design only supports 1 IO BAR. Testbench will disable BAR"));
hwrite(L, std_logic_vector(to_unsigned(i, 4)));
writeline (output, L);
BAR_ENABLED(i) := 0; -- Disabled
end if;
else
if (RANGE_VALUE(2) = '1') then
BAR_ENABLED(i) := 3; -- Mem64
BAR_ENABLED(i+1) := 0; -- Mem64 uses upper BAR so set as disabled
NUMBER_OF_MEM64_BARS := NUMBER_OF_MEM64_BARS + 1;
if (pio_check_design and (NUMBER_OF_MEM64_BARS >1)) then
write (L, String'("Warning: PIO design only supports 1 MEM64 BAR. Testbench will disable BAR"));
hwrite(L, std_logic_vector(to_unsigned(i, 4)));
writeline (output, L);
BAR_ENABLED(i) := 0; -- Disabled
end if;
i := i + 1;
else
if (i /= 6) then NUMBER_OF_MEM32_BARS := NUMBER_OF_MEM32_BARS + 1;
end if;
BAR_ENABLED(i) := 2; -- Mem32
if (pio_check_design and (NUMBER_OF_MEM32_BARS >1)) then
write (L, String'("Warning: PIO design only supports 1 MEM32 BAR. Testbench will disable BAR"));
hwrite(L, std_logic_vector(to_unsigned(i, 4)));
writeline (output, L);
BAR_ENABLED(i) := 0; -- Disabled
end if;
end if;
end if;
end if;
i := i + 1;
end loop;
end PROC_BUILD_PCIE_MAP;
--***********************************************************
-- Proc : PROC_BAR_SCAN
-- Inputs : None
-- Outputs : None
-- Description : Scans PCI core's configuration registers.
--*************************************************************/
procedure PROC_BAR_SCAN (
signal tx_rx_read_data_valid : out std_logic;
signal rx_tx_read_data_valid : in std_logic;
signal rx_tx_read_data : in std_logic_vector (31 downto 0);
signal trn_td_c : out std_logic_vector(63 downto 0);
signal trn_tsof_n : out std_logic;
signal trn_teof_n : out std_logic;
signal trn_trem_n_c : out std_logic_vector(7 downto 0);
signal trn_tsrc_rdy_n : out std_logic;
signal trn_lnk_up_n : in std_logic;
signal trn_tdst_rdy_n : in std_logic;
signal trn_clk : in std_logic
) is
variable P_ADDRESS_MASK : std_logic_vector((32 - 1) downto 0);
variable L : line;
variable DEFAULT_TAG : std_logic_vector(( 8 - 1) downto 0);
begin
-- TRN MODEL Initialization
BAR_RANGE(0) := X"FFFFFC00";
BAR_RANGE(1) := X"FFFFC000";
BAR_RANGE(2) := X"FF000000";
BAR_RANGE(3) := X"00000000";
BAR_RANGE(4) := X"00000000";
BAR_RANGE(5) := X"00000000";
BAR_RANGE(6) := X"00000000";
end PROC_BAR_SCAN;
--************************************************************
-- Procedure : PROC_BAR_PROGRAM
-- Inputs : None
-- Outputs : None
-- Description : Program's PCI core's configuration registers.
-- ************************************************************/
procedure PROC_BAR_PROGRAM (
signal trn_td_c : out std_logic_vector(63 downto 0);
signal trn_tsof_n : out std_logic;
signal trn_teof_n : out std_logic;
signal trn_trem_n_c : out std_logic_vector(7 downto 0);
signal trn_tsrc_rdy_n : out std_logic;
signal trn_lnk_up_n : in std_logic;
signal trn_tdst_rdy_n : in std_logic;
signal trn_clk : in std_logic
) is
variable L : line;
variable DEFAULT_TAG : std_logic_vector(( 8 - 1) downto 0);
begin
DEFAULT_TAG := X"0f";
write (L, String'("[ ")); write (L, now);
write (L, String'(" ] : Setting Core Configuration Space..."));
writeline (output, L);
-- Program BAR0
PROC_TX_TYPE0_CONFIGURATION_WRITE (
DEFAULT_TAG, --tag :in std_logic_vector (7 downto 0);
X"010", --reg_addr 12'h10
BAR(0)(31 downto 0), --reg_data : in std_logic_vector (31 downto 0);
X"F", --first_dw_be : in std_logic_vector (3 downto 0);
trn_td_c, trn_tsof_n,trn_teof_n,trn_trem_n_c, trn_tsrc_rdy_n, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
DEFAULT_TAG := X"10";
PROC_TX_CLK_EAT(100, trn_clk);
-- Program BAR1
PROC_TX_TYPE0_CONFIGURATION_WRITE (
DEFAULT_TAG, --tag :in std_logic_vector (7 downto 0);
X"014", --reg_addr 12'h14
BAR(1)(31 downto 0), --reg_data : in std_logic_vector (31 downto 0);
X"F", --first_dw_be : in std_logic_vector (3 downto 0);
trn_td_c, trn_tsof_n,trn_teof_n,trn_trem_n_c, trn_tsrc_rdy_n, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
DEFAULT_TAG := X"11";
PROC_TX_CLK_EAT(100, trn_clk);
-- Program BAR2
PROC_TX_TYPE0_CONFIGURATION_WRITE (
DEFAULT_TAG, --tag :in std_logic_vector (7 downto 0);
X"018", --reg_addr 12'h18
BAR(2)(31 downto 0), --reg_data : in std_logic_vector (31 downto 0);
X"F", --first_dw_be : in std_logic_vector (3 downto 0);
trn_td_c, trn_tsof_n,trn_teof_n,trn_trem_n_c, trn_tsrc_rdy_n, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
DEFAULT_TAG := X"12";
PROC_TX_CLK_EAT(100, trn_clk);
-- Program BAR3
PROC_TX_TYPE0_CONFIGURATION_WRITE (
DEFAULT_TAG, --tag :in std_logic_vector (7 downto 0);
X"01C", --reg_addr 12'h1C
BAR(3)(31 downto 0), --reg_data : in std_logic_vector (31 downto 0);
X"F", --first_dw_be : in std_logic_vector (3 downto 0);
trn_td_c, trn_tsof_n,trn_teof_n,trn_trem_n_c, trn_tsrc_rdy_n, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
DEFAULT_TAG := X"13";
PROC_TX_CLK_EAT(100, trn_clk);
-- Program BAR4
PROC_TX_TYPE0_CONFIGURATION_WRITE (
DEFAULT_TAG, --tag :in std_logic_vector (7 downto 0);
X"020", --reg_addr 12'h20
BAR(4)(31 downto 0), --reg_data : in std_logic_vector (31 downto 0);
X"F", --first_dw_be : in std_logic_vector (3 downto 0);
trn_td_c, trn_tsof_n,trn_teof_n,trn_trem_n_c, trn_tsrc_rdy_n, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
DEFAULT_TAG := X"14";
PROC_TX_CLK_EAT(100, trn_clk);
-- Program BAR5
PROC_TX_TYPE0_CONFIGURATION_WRITE (
DEFAULT_TAG, --tag :in std_logic_vector (7 downto 0);
X"024", --reg_addr 12'h24
BAR(5)(31 downto 0), --reg_data : in std_logic_vector (31 downto 0);
X"F", --first_dw_be : in std_logic_vector (3 downto 0);
trn_td_c, trn_tsof_n,trn_teof_n,trn_trem_n_c, trn_tsrc_rdy_n, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
DEFAULT_TAG := X"15";
PROC_TX_CLK_EAT(100, trn_clk);
-- Program Expansion ROM BAR
PROC_TX_TYPE0_CONFIGURATION_WRITE (
DEFAULT_TAG, --tag :in std_logic_vector (7 downto 0);
X"030", --reg_addr 12'h30
BAR(6)(31 downto 0), --reg_data : in std_logic_vector (31 downto 0);
X"F", --first_dw_be : in std_logic_vector (3 downto 0);
trn_td_c, trn_tsof_n,trn_teof_n,trn_trem_n_c, trn_tsrc_rdy_n, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
DEFAULT_TAG := X"16";
PROC_TX_CLK_EAT(100, trn_clk);
-- Program PCI Command Register
PROC_TX_TYPE0_CONFIGURATION_WRITE (
DEFAULT_TAG, --tag :in std_logic_vector (7 downto 0);
X"004", --reg_addr 12'h04
X"00000003", --reg_data : in std_logic_vector (31 downto 0);
X"1", --first_dw_be : in std_logic_vector (3 downto 0);
trn_td_c, trn_tsof_n,trn_teof_n,trn_trem_n_c, trn_tsrc_rdy_n, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
DEFAULT_TAG := X"17";
PROC_TX_CLK_EAT(100, trn_clk);
-- Program PCIe Device Control Register
PROC_TX_TYPE0_CONFIGURATION_WRITE (
DEFAULT_TAG, --tag :in std_logic_vector (7 downto 0);
X"068", --reg_addr 12'h68
X"0000005F", --reg_data : in std_logic_vector (31 downto 0);
X"1", --first_dw_be : in std_logic_vector (3 downto 0);
trn_td_c, trn_tsof_n,trn_teof_n,trn_trem_n_c, trn_tsrc_rdy_n, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
DEFAULT_TAG := X"18";
PROC_TX_CLK_EAT(1000, trn_clk);
end PROC_BAR_PROGRAM;
-- ***********************************************************
-- Procedure : PROC_BAR_INIT
-- Inputs : None
-- Outputs : None
-- Description : Initialize PCI core based on core's configuration.
-- *************************************************************/
procedure PROC_BAR_INIT (
signal tx_rx_read_data_valid : out std_logic;
signal rx_tx_read_data_valid : in std_logic;
signal rx_tx_read_data : in std_logic_vector (31 downto 0);
signal trn_td_c : out std_logic_vector(63 downto 0);
signal trn_tsof_n : out std_logic;
signal trn_teof_n : out std_logic;
signal trn_trem_n_c : out std_logic_vector(7 downto 0);
signal trn_tsrc_rdy_n : out std_logic;
signal trn_lnk_up_n : in std_logic;
signal trn_tdst_rdy_n : in std_logic;
signal trn_clk : in std_logic
) is
begin
PROC_BAR_SCAN(tx_rx_read_data_valid, rx_tx_read_data_valid, rx_tx_read_data, trn_td_c, trn_tsof_n,
trn_teof_n, trn_trem_n_c, trn_tsrc_rdy_n, trn_lnk_up_n, trn_tdst_rdy_n,trn_clk);
PROC_BUILD_PCIE_MAP;
PROC_DISPLAY_PCIE_MAP(BAR, BAR_ENABLED, BAR_RANGE );
PROC_BAR_PROGRAM( trn_td_c, trn_tsof_n, trn_teof_n,
trn_trem_n_c, trn_tsrc_rdy_n, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
end PROC_BAR_INIT;
--************************************************************
-- Proc : PROC_SYSTEM_INITIALIZATION
-- Inputs : None
-- Outputs : None
-- Description : Waits for Reset to deassert and for Link up.
--*************************************************************/
procedure PROC_SYSTEM_INITIALIZATION(
signal trn_reset_n: in std_logic;
signal trn_lnk_up_n: in std_logic ) is
variable L : line;
begin
--------------------------------------------------------------------------
-- Wait for Transaction reset to be de-asserted..
--------------------------------------------------------------------------
wait until trn_reset_n = '1';
writeNowToScreen ( String'("Transaction Reset is De-asserted"));
--------------------------------------------------------------------------
-- Wait for Transaction link to be asserted..
--------------------------------------------------------------------------
wait until trn_lnk_up_n = '0';
writeNowToScreen ( String'("Transaction Link is Up"));
end PROC_SYSTEM_INITIALIZATION;
--************************************************************
-- Proc : PROC_READ_CFG_DW
-- Inputs : addr - 10-bit address
-- Outputs : None
-- Inouts : cfg_rdwr_int - configuration interface signals
-- Description : Read Configuration Space DW
--*************************************************************/
procedure PROC_READ_CFG_DW (
addr : in std_logic_vector(9 downto 0);
signal cfg_rdwr_int : inout cfg_rdwr_sigs
) is
variable L : line;
begin
-- Because cfg_rdwr_int is an inout, we have to tri-state the sub-signals we want to read
cfg_rdwr_int.cfg_rd_wr_done_n <= 'Z';
cfg_rdwr_int.cfg_do <= (OTHERS => 'Z');
cfg_rdwr_int.trn_clk <= 'Z';
cfg_rdwr_int.trn_reset_n <= 'Z';
assert (cfg_rdwr_int.trn_reset_n = '1')
report "TX Reset is asserted"
severity failure;
if (cfg_rdwr_int.cfg_rd_wr_done_n /= '1') then
wait until (rising_edge(cfg_rdwr_int.trn_clk) and cfg_rdwr_int.cfg_rd_wr_done_n = '1');
end if;
wait until (rising_edge(cfg_rdwr_int.trn_clk));
cfg_rdwr_int.cfg_dwaddr <= addr;
cfg_rdwr_int.cfg_wr_en_n <= '1';
cfg_rdwr_int.cfg_rd_en_n <= '0';
writeNowToScreen(String'("Reading Config space"));
write (L, String'(" Addr: [0x"));
hwrite(L, "00" & addr);
write (L, String'("]"));
writeline(output, L);
wait until (rising_edge(cfg_rdwr_int.trn_clk) and cfg_rdwr_int.cfg_rd_wr_done_n = '0');
cfg_rdwr_int.cfg_rd_en_n <= '1';
write (L, String'(" Cfg Addr [0x"));
hwrite(L, "00" & addr);
write (L, String'("] -> Data [0x"));
hwrite(L, cfg_rdwr_int.cfg_do);
write (L, String'("]"));
writeline(output, L);
end PROC_READ_CFG_DW;
--************************************************************
-- Proc : PROC_WRITE_CFG_DW
-- Inputs : addr - 10-bit address
-- data - 32-bit data to write
-- byte_en_n - 4-bit active-low byte enable
-- Outputs : None
-- Inouts : cfg_rdwr_int - configuration interface signals
-- Description : Write Configuration Space DW
--*************************************************************/
procedure PROC_WRITE_CFG_DW (
addr : in std_logic_vector(9 downto 0);
data : in std_logic_vector(31 downto 0);
byte_en_n : in std_logic_vector(3 downto 0);
signal cfg_rdwr_int : inout cfg_rdwr_sigs
) is
variable L : line;
begin
-- Because cfg_rdwr_int is an inout, we have to tri-state the sub-signals we want to read
cfg_rdwr_int.cfg_rd_wr_done_n <= 'Z';
cfg_rdwr_int.cfg_do <= (OTHERS => 'Z');
cfg_rdwr_int.trn_clk <= 'Z';
cfg_rdwr_int.trn_reset_n <= 'Z';
assert (cfg_rdwr_int.trn_reset_n = '1')
report "TX Reset is asserted"
severity failure;
if (cfg_rdwr_int.cfg_rd_wr_done_n /= '1') then
wait until (rising_edge(cfg_rdwr_int.trn_clk) and cfg_rdwr_int.cfg_rd_wr_done_n = '1');
end if;
wait until (rising_edge(cfg_rdwr_int.trn_clk));
cfg_rdwr_int.cfg_dwaddr <= addr;
cfg_rdwr_int.cfg_wr_en_n <= '0';
cfg_rdwr_int.cfg_rd_en_n <= '1';
cfg_rdwr_int.cfg_di <= data;
cfg_rdwr_int.cfg_byte_en_n <= byte_en_n;
writeNowToScreen(String'("Writing Config space"));
write (L, String'(" Addr: [0x"));
hwrite(L, "00" & addr);
write (L, String'("] -> Data [0x"));
hwrite(L, data);
write (L, String'("]"));
writeline(output, L);
wait until (rising_edge(cfg_rdwr_int.trn_clk) and cfg_rdwr_int.cfg_rd_wr_done_n = '0');
cfg_rdwr_int.cfg_wr_en_n <= '1';
end PROC_WRITE_CFG_DW;
end package body test_interface;
| gpl-3.0 | 7b3a5591178d30946750b52c97825660 | 0.489145 | 3.47951 | false | false | false | false |
masaruohashi/tic-tac-toe | uart/circuito_superamostragem.vhd | 1 | 1,244 | -- circuito_superamostragem.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity circuito_superamostragem is
generic(
M: integer := 16 -- para transmissao de 110 bauds com gerador de tick 16 * 110 Hz
);
port(
clock, reset: in std_logic;
tick: in std_logic;
load: in std_logic;
habilita_circuito: out std_logic
);
end circuito_superamostragem;
architecture arch of circuito_superamostragem is
signal contagem, prox_contagem: integer;
signal prox_enable: std_logic;
begin
process(clock,reset)
begin
if (reset='1') then
contagem <= 0;
elsif (clock'event and clock='1') then
if tick = '1' then
if load = '1' then
contagem <= (M / 2);
else
contagem <= prox_contagem;
end if;
end if;
if prox_enable = '0' then
if((contagem = (M-1)) and (tick = '1')) then
prox_enable <= '1';
end if;
else
prox_enable <= '0';
end if;
end if;
end process;
-- logica de proximo estado
prox_contagem <= 0 when contagem=(M-1) else contagem + 1;
-- logica de saida
habilita_circuito <= prox_enable;
end arch;
| mit | d4c39c67bd38cd313ed02f634570ed17 | 0.579582 | 3.680473 | false | false | false | false |
JavierRizzoA/Sacagawea | sources/ALUToFlag.vhd | 1 | 1,265 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:21:59 06/06/2016
-- Design Name:
-- Module Name: ALUToFlag - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ALUToFlag is
Port ( alu_sal : in STD_LOGIC_VECTOR (7 downto 0);
ma : out STD_LOGIC;
me : out STD_LOGIC;
z : out STD_LOGIC);
end ALUToFlag;
architecture Behavioral of ALUToFlag is
SIGNAL mamez: STD_LOGIC_VECTOR(2 DOWNTO 0);
begin
mamez <= "001" WHEN alu_sal = "00000000" ELSE
"010" WHEN alu_sal(7) = '1' ELSE
"100";
ma <= mamez(2);
me <= mamez(1);
z <= mamez(0);
end Behavioral;
| mit | 3ae79ad8b08570fcc13a81d47b48d7cc | 0.561265 | 3.731563 | false | false | false | false |
timofonic/PHDL | misc/projects/spartan_pcie_board/fpga/lx45t_pinout/ipcore_dir/pcie_core/simulation/dsport/pcie_2_0_v6_rp.vhd | 1 | 165,948 | -------------------------------------------------------------------------------
--
-- (c) Copyright 2008, 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Project : Spartan-6 Integrated Block for PCI Express
-- File : pcie_2_0_v6_rp.vhd
-- Description: Spartan-6 solution wrapper : Root Port for PCI Express
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity pcie_2_0_v6_rp is
generic (
TCQ : integer := 1;
REF_CLK_FREQ : integer := 0; -- 0 - 100 MHz, 1 - 125 MHz, 2 - 250 MHz
PIPE_PIPELINE_STAGES : integer := 0; -- 0 - 0 stages, 1 - 1 stage, 2 - 2 stages
LINK_CAP_MAX_LINK_WIDTH_int : integer := 8;
AER_BASE_PTR : bit_vector := X"128";
AER_CAP_ECRC_CHECK_CAPABLE : boolean := FALSE;
AER_CAP_ECRC_GEN_CAPABLE : boolean := FALSE;
AER_CAP_ID : bit_vector := X"0001";
AER_CAP_INT_MSG_NUM_MSI : bit_vector := X"0A";
AER_CAP_INT_MSG_NUM_MSIX : bit_vector := X"15";
AER_CAP_NEXTPTR : bit_vector := X"160";
AER_CAP_ON : boolean := FALSE;
AER_CAP_PERMIT_ROOTERR_UPDATE : boolean := TRUE;
AER_CAP_VERSION : bit_vector := X"1";
ALLOW_X8_GEN2 : boolean := FALSE;
BAR0 : bit_vector := X"FFFFFF00";
BAR1 : bit_vector := X"FFFF0000";
BAR2 : bit_vector := X"FFFF000C";
BAR3 : bit_vector := X"FFFFFFFF";
BAR4 : bit_vector := X"00000000";
BAR5 : bit_vector := X"00000000";
CAPABILITIES_PTR : bit_vector := X"40";
CARDBUS_CIS_POINTER : bit_vector := X"00000000";
CLASS_CODE : bit_vector := X"000000";
CMD_INTX_IMPLEMENTED : boolean := TRUE;
CPL_TIMEOUT_DISABLE_SUPPORTED : boolean := FALSE;
CPL_TIMEOUT_RANGES_SUPPORTED : bit_vector := X"0";
CRM_MODULE_RSTS : bit_vector := X"00";
DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE : boolean := TRUE;
DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE : boolean := TRUE;
DEV_CAP_ENDPOINT_L0S_LATENCY : integer := 0;
DEV_CAP_ENDPOINT_L1_LATENCY : integer := 0;
DEV_CAP_EXT_TAG_SUPPORTED : boolean := TRUE;
DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE : boolean := FALSE;
DEV_CAP_MAX_PAYLOAD_SUPPORTED : integer := 2;
DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT : integer := 0;
DEV_CAP_ROLE_BASED_ERROR : boolean := TRUE;
DEV_CAP_RSVD_14_12 : integer := 0;
DEV_CAP_RSVD_17_16 : integer := 0;
DEV_CAP_RSVD_31_29 : integer := 0;
DEV_CONTROL_AUX_POWER_SUPPORTED : boolean := FALSE;
DEVICE_ID : bit_vector := X"0007";
DISABLE_ASPM_L1_TIMER : boolean := FALSE;
DISABLE_BAR_FILTERING : boolean := FALSE;
DISABLE_ID_CHECK : boolean := FALSE;
DISABLE_LANE_REVERSAL : boolean := FALSE;
DISABLE_RX_TC_FILTER : boolean := FALSE;
DISABLE_SCRAMBLING : boolean := FALSE;
DNSTREAM_LINK_NUM : bit_vector := X"00";
DSN_BASE_PTR : bit_vector := X"100";
DSN_CAP_ID : bit_vector := X"0003";
DSN_CAP_NEXTPTR : bit_vector := X"000";
DSN_CAP_ON : boolean := TRUE;
DSN_CAP_VERSION : bit_vector := X"1";
ENABLE_MSG_ROUTE : bit_vector := X"000";
ENABLE_RX_TD_ECRC_TRIM : boolean := FALSE;
ENTER_RVRY_EI_L0 : boolean := TRUE;
EXPANSION_ROM : bit_vector := X"FFFFF001";
EXT_CFG_CAP_PTR : bit_vector := X"3F";
EXT_CFG_XP_CAP_PTR : bit_vector := X"3FF";
HEADER_TYPE : bit_vector := X"00";
INFER_EI : bit_vector := X"00";
INTERRUPT_PIN : bit_vector := X"01";
IS_SWITCH : boolean := FALSE;
LAST_CONFIG_DWORD : bit_vector := X"042";
LINK_CAP_ASPM_SUPPORT : integer := 1;
LINK_CAP_CLOCK_POWER_MANAGEMENT : boolean := FALSE;
LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP : boolean := FALSE;
LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 : integer := 7;
LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 : integer := 7;
LINK_CAP_L0S_EXIT_LATENCY_GEN1 : integer := 7;
LINK_CAP_L0S_EXIT_LATENCY_GEN2 : integer := 7;
LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 : integer := 7;
LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 : integer := 7;
LINK_CAP_L1_EXIT_LATENCY_GEN1 : integer := 7;
LINK_CAP_L1_EXIT_LATENCY_GEN2 : integer := 7;
LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP : boolean := FALSE;
LINK_CAP_MAX_LINK_SPEED : bit_vector := X"1";
LINK_CAP_MAX_LINK_WIDTH : bit_vector := X"08";
LINK_CAP_RSVD_23_22 : integer := 0;
LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE : boolean := FALSE;
LINK_CONTROL_RCB : integer := 0;
LINK_CTRL2_DEEMPHASIS : boolean := FALSE;
LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE : boolean := FALSE;
LINK_CTRL2_TARGET_LINK_SPEED : bit_vector := X"2";
LINK_STATUS_SLOT_CLOCK_CONFIG : boolean := TRUE;
LL_ACK_TIMEOUT : bit_vector := X"0000";
LL_ACK_TIMEOUT_EN : boolean := FALSE;
LL_ACK_TIMEOUT_FUNC : integer := 0;
LL_REPLAY_TIMEOUT : bit_vector := X"0000";
LL_REPLAY_TIMEOUT_EN : boolean := FALSE;
LL_REPLAY_TIMEOUT_FUNC : integer := 0;
LTSSM_MAX_LINK_WIDTH : bit_vector := X"01";
MSI_BASE_PTR : bit_vector := X"48";
MSI_CAP_ID : bit_vector := X"05";
MSI_CAP_MULTIMSGCAP : integer := 0;
MSI_CAP_MULTIMSG_EXTENSION : integer := 0;
MSI_CAP_NEXTPTR : bit_vector := X"60";
MSI_CAP_ON : boolean := FALSE;
MSI_CAP_PER_VECTOR_MASKING_CAPABLE : boolean := TRUE;
MSI_CAP_64_BIT_ADDR_CAPABLE : boolean := TRUE;
MSIX_BASE_PTR : bit_vector := X"9C";
MSIX_CAP_ID : bit_vector := X"11";
MSIX_CAP_NEXTPTR : bit_vector := X"00";
MSIX_CAP_ON : boolean := FALSE;
MSIX_CAP_PBA_BIR : integer := 0;
MSIX_CAP_PBA_OFFSET : bit_vector := X"00000050";
MSIX_CAP_TABLE_BIR : integer := 0;
MSIX_CAP_TABLE_OFFSET : bit_vector := X"00000040";
MSIX_CAP_TABLE_SIZE : bit_vector := X"000";
N_FTS_COMCLK_GEN1 : integer := 255;
N_FTS_COMCLK_GEN2 : integer := 255;
N_FTS_GEN1 : integer := 255;
N_FTS_GEN2 : integer := 255;
PCIE_BASE_PTR : bit_vector := X"60";
PCIE_CAP_CAPABILITY_ID : bit_vector := X"10";
PCIE_CAP_CAPABILITY_VERSION : bit_vector := X"2";
PCIE_CAP_DEVICE_PORT_TYPE : bit_vector := X"0";
PCIE_CAP_INT_MSG_NUM : bit_vector := X"00";
PCIE_CAP_NEXTPTR : bit_vector := X"00";
PCIE_CAP_ON : boolean := TRUE;
PCIE_CAP_RSVD_15_14 : integer := 0;
PCIE_CAP_SLOT_IMPLEMENTED : boolean := FALSE;
PCIE_REVISION : integer := 2;
PGL0_LANE : integer := 0;
PGL1_LANE : integer := 1;
PGL2_LANE : integer := 2;
PGL3_LANE : integer := 3;
PGL4_LANE : integer := 4;
PGL5_LANE : integer := 5;
PGL6_LANE : integer := 6;
PGL7_LANE : integer := 7;
PL_AUTO_CONFIG : integer := 0;
PL_FAST_TRAIN : boolean := FALSE;
PM_BASE_PTR : bit_vector := X"40";
PM_CAP_AUXCURRENT : integer := 0;
PM_CAP_DSI : boolean := FALSE;
PM_CAP_D1SUPPORT : boolean := TRUE;
PM_CAP_D2SUPPORT : boolean := TRUE;
PM_CAP_ID : bit_vector := X"11";
PM_CAP_NEXTPTR : bit_vector := X"48";
PM_CAP_ON : boolean := TRUE;
PM_CAP_PME_CLOCK : boolean := FALSE;
PM_CAP_PMESUPPORT : bit_vector := X"0F";
PM_CAP_RSVD_04 : integer := 0;
PM_CAP_VERSION : integer := 3;
PM_CSR_BPCCEN : boolean := FALSE;
PM_CSR_B2B3 : boolean := FALSE;
PM_CSR_NOSOFTRST : boolean := TRUE;
PM_DATA0 : bit_vector := X"01";
PM_DATA1 : bit_vector := X"01";
PM_DATA2 : bit_vector := X"01";
PM_DATA3 : bit_vector := X"01";
PM_DATA4 : bit_vector := X"01";
PM_DATA5 : bit_vector := X"01";
PM_DATA6 : bit_vector := X"01";
PM_DATA7 : bit_vector := X"01";
PM_DATA_SCALE0 : bit_vector := X"1";
PM_DATA_SCALE1 : bit_vector := X"1";
PM_DATA_SCALE2 : bit_vector := X"1";
PM_DATA_SCALE3 : bit_vector := X"1";
PM_DATA_SCALE4 : bit_vector := X"1";
PM_DATA_SCALE5 : bit_vector := X"1";
PM_DATA_SCALE6 : bit_vector := X"1";
PM_DATA_SCALE7 : bit_vector := X"1";
RECRC_CHK : integer := 0;
RECRC_CHK_TRIM : boolean := FALSE;
REVISION_ID : bit_vector := X"00";
ROOT_CAP_CRS_SW_VISIBILITY : boolean := FALSE;
SELECT_DLL_IF : boolean := FALSE;
SLOT_CAP_ATT_BUTTON_PRESENT : boolean := FALSE;
SLOT_CAP_ATT_INDICATOR_PRESENT : boolean := FALSE;
SLOT_CAP_ELEC_INTERLOCK_PRESENT : boolean := FALSE;
SLOT_CAP_HOTPLUG_CAPABLE : boolean := FALSE;
SLOT_CAP_HOTPLUG_SURPRISE : boolean := FALSE;
SLOT_CAP_MRL_SENSOR_PRESENT : boolean := FALSE;
SLOT_CAP_NO_CMD_COMPLETED_SUPPORT : boolean := FALSE;
SLOT_CAP_PHYSICAL_SLOT_NUM : bit_vector := X"0000";
SLOT_CAP_POWER_CONTROLLER_PRESENT : boolean := FALSE;
SLOT_CAP_POWER_INDICATOR_PRESENT : boolean := FALSE;
SLOT_CAP_SLOT_POWER_LIMIT_SCALE : integer := 0;
SLOT_CAP_SLOT_POWER_LIMIT_VALUE : bit_vector := X"00";
SPARE_BIT0 : integer := 0;
SPARE_BIT1 : integer := 0;
SPARE_BIT2 : integer := 0;
SPARE_BIT3 : integer := 0;
SPARE_BIT4 : integer := 0;
SPARE_BIT5 : integer := 0;
SPARE_BIT6 : integer := 0;
SPARE_BIT7 : integer := 0;
SPARE_BIT8 : integer := 0;
SPARE_BYTE0 : bit_vector := X"00";
SPARE_BYTE1 : bit_vector := X"00";
SPARE_BYTE2 : bit_vector := X"00";
SPARE_BYTE3 : bit_vector := X"00";
SPARE_WORD0 : bit_vector := X"00000000";
SPARE_WORD1 : bit_vector := X"00000000";
SPARE_WORD2 : bit_vector := X"00000000";
SPARE_WORD3 : bit_vector := X"00000000";
SUBSYSTEM_ID : bit_vector := X"0007";
SUBSYSTEM_VENDOR_ID : bit_vector := X"10EE";
TL_RBYPASS : boolean := FALSE;
TL_RX_RAM_RADDR_LATENCY : integer := 0;
TL_RX_RAM_RDATA_LATENCY : integer := 2;
TL_RX_RAM_WRITE_LATENCY : integer := 0;
TL_TFC_DISABLE : boolean := FALSE;
TL_TX_CHECKS_DISABLE : boolean := FALSE;
TL_TX_RAM_RADDR_LATENCY : integer := 0;
TL_TX_RAM_RDATA_LATENCY : integer := 2;
TL_TX_RAM_WRITE_LATENCY : integer := 0;
UPCONFIG_CAPABLE : boolean := TRUE;
UPSTREAM_FACING : boolean := TRUE;
UR_INV_REQ : boolean := TRUE;
USER_CLK_FREQ : integer := 3;
EXIT_LOOPBACK_ON_EI : boolean := TRUE;
VC_BASE_PTR : bit_vector := X"10C";
VC_CAP_ID : bit_vector := X"0002";
VC_CAP_NEXTPTR : bit_vector := X"000";
VC_CAP_ON : boolean := FALSE;
VC_CAP_REJECT_SNOOP_TRANSACTIONS : boolean := FALSE;
VC_CAP_VERSION : bit_vector := X"1";
VC0_CPL_INFINITE : boolean := TRUE;
VC0_RX_RAM_LIMIT : bit_vector := X"03FF";
VC0_TOTAL_CREDITS_CD : integer := 127;
VC0_TOTAL_CREDITS_CH : integer := 31;
VC0_TOTAL_CREDITS_NPH : integer := 12;
VC0_TOTAL_CREDITS_PD : integer := 288;
VC0_TOTAL_CREDITS_PH : integer := 32;
VC0_TX_LASTPACKET : integer := 31;
VENDOR_ID : bit_vector := X"10EE";
VSEC_BASE_PTR : bit_vector := X"160";
VSEC_CAP_HDR_ID : bit_vector := X"1234";
VSEC_CAP_HDR_LENGTH : bit_vector := X"018";
VSEC_CAP_HDR_REVISION : bit_vector := X"1";
VSEC_CAP_ID : bit_vector := X"000B";
VSEC_CAP_IS_LINK_VISIBLE : boolean := TRUE;
VSEC_CAP_NEXTPTR : bit_vector := X"000";
VSEC_CAP_ON : boolean := FALSE;
VSEC_CAP_VERSION : bit_vector := X"1"
);
port (
PCIEXPRXN : in std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
PCIEXPRXP : in std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
PCIEXPTXN : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
PCIEXPTXP : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
SYSCLK : in std_logic;
FUNDRSTN : in std_logic;
TRNLNKUPN : out std_logic;
TRNCLK : out std_logic;
PHYRDYN : out std_logic;
USERRSTN : out std_logic;
RECEIVEDFUNCLVLRSTN : out std_logic;
LNKCLKEN : out std_logic;
SYSRSTN : in std_logic;
PLRSTN : in std_logic;
DLRSTN : in std_logic;
TLRSTN : in std_logic;
FUNCLVLRSTN : in std_logic;
CMRSTN : in std_logic;
CMSTICKYRSTN : in std_logic;
TRNRBARHITN : out std_logic_vector(6 downto 0);
TRNRD : out std_logic_vector(63 downto 0);
TRNRECRCERRN : out std_logic;
TRNREOFN : out std_logic;
TRNRERRFWDN : out std_logic;
TRNRREMN : out std_logic;
TRNRSOFN : out std_logic;
TRNRSRCDSCN : out std_logic;
TRNRSRCRDYN : out std_logic;
TRNRDSTRDYN : in std_logic;
TRNRNPOKN : in std_logic;
TRNTBUFAV : out std_logic_vector(5 downto 0);
TRNTCFGREQN : out std_logic;
TRNTDLLPDSTRDYN : out std_logic;
TRNTDSTRDYN : out std_logic;
TRNTERRDROPN : out std_logic;
TRNTCFGGNTN : in std_logic;
TRNTD : in std_logic_vector(63 downto 0);
TRNTDLLPDATA : in std_logic_vector(31 downto 0);
TRNTDLLPSRCRDYN : in std_logic;
TRNTECRCGENN : in std_logic;
TRNTEOFN : in std_logic;
TRNTERRFWDN : in std_logic;
TRNTREMN : in std_logic;
TRNTSOFN : in std_logic;
TRNTSRCDSCN : in std_logic;
TRNTSRCRDYN : in std_logic;
TRNTSTRN : in std_logic;
TRNFCCPLD : out std_logic_vector(11 downto 0);
TRNFCCPLH : out std_logic_vector(7 downto 0);
TRNFCNPD : out std_logic_vector(11 downto 0);
TRNFCNPH : out std_logic_vector(7 downto 0);
TRNFCPD : out std_logic_vector(11 downto 0);
TRNFCPH : out std_logic_vector(7 downto 0);
TRNFCSEL : in std_logic_vector(2 downto 0);
CFGAERECRCCHECKEN : out std_logic;
CFGAERECRCGENEN : out std_logic;
CFGCOMMANDBUSMASTERENABLE : out std_logic;
CFGCOMMANDINTERRUPTDISABLE : out std_logic;
CFGCOMMANDIOENABLE : out std_logic;
CFGCOMMANDMEMENABLE : out std_logic;
CFGCOMMANDSERREN : out std_logic;
CFGDEVCONTROLAUXPOWEREN : out std_logic;
CFGDEVCONTROLCORRERRREPORTINGEN : out std_logic;
CFGDEVCONTROLENABLERO : out std_logic;
CFGDEVCONTROLEXTTAGEN : out std_logic;
CFGDEVCONTROLFATALERRREPORTINGEN : out std_logic;
CFGDEVCONTROLMAXPAYLOAD : out std_logic_vector(2 downto 0);
CFGDEVCONTROLMAXREADREQ : out std_logic_vector(2 downto 0);
CFGDEVCONTROLNONFATALREPORTINGEN : out std_logic;
CFGDEVCONTROLNOSNOOPEN : out std_logic;
CFGDEVCONTROLPHANTOMEN : out std_logic;
CFGDEVCONTROLURERRREPORTINGEN : out std_logic;
CFGDEVCONTROL2CPLTIMEOUTDIS : out std_logic;
CFGDEVCONTROL2CPLTIMEOUTVAL : out std_logic_vector(3 downto 0);
CFGDEVSTATUSCORRERRDETECTED : out std_logic;
CFGDEVSTATUSFATALERRDETECTED : out std_logic;
CFGDEVSTATUSNONFATALERRDETECTED : out std_logic;
CFGDEVSTATUSURDETECTED : out std_logic;
CFGDO : out std_logic_vector(31 downto 0);
CFGERRAERHEADERLOGSETN : out std_logic;
CFGERRCPLRDYN : out std_logic;
CFGINTERRUPTDO : out std_logic_vector(7 downto 0);
CFGINTERRUPTMMENABLE : out std_logic_vector(2 downto 0);
CFGINTERRUPTMSIENABLE : out std_logic;
CFGINTERRUPTMSIXENABLE : out std_logic;
CFGINTERRUPTMSIXFM : out std_logic;
CFGINTERRUPTRDYN : out std_logic;
CFGLINKCONTROLRCB : out std_logic;
CFGLINKCONTROLASPMCONTROL : out std_logic_vector(1 downto 0);
CFGLINKCONTROLAUTOBANDWIDTHINTEN : out std_logic;
CFGLINKCONTROLBANDWIDTHINTEN : out std_logic;
CFGLINKCONTROLCLOCKPMEN : out std_logic;
CFGLINKCONTROLCOMMONCLOCK : out std_logic;
CFGLINKCONTROLEXTENDEDSYNC : out std_logic;
CFGLINKCONTROLHWAUTOWIDTHDIS : out std_logic;
CFGLINKCONTROLLINKDISABLE : out std_logic;
CFGLINKCONTROLRETRAINLINK : out std_logic;
CFGLINKSTATUSAUTOBANDWIDTHSTATUS : out std_logic;
CFGLINKSTATUSBANDWITHSTATUS : out std_logic;
CFGLINKSTATUSCURRENTSPEED : out std_logic_vector(1 downto 0);
CFGLINKSTATUSDLLACTIVE : out std_logic;
CFGLINKSTATUSLINKTRAINING : out std_logic;
CFGLINKSTATUSNEGOTIATEDWIDTH : out std_logic_vector(3 downto 0);
CFGMSGDATA : out std_logic_vector(15 downto 0);
CFGMSGRECEIVED : out std_logic;
CFGMSGRECEIVEDASSERTINTA : out std_logic;
CFGMSGRECEIVEDASSERTINTB : out std_logic;
CFGMSGRECEIVEDASSERTINTC : out std_logic;
CFGMSGRECEIVEDASSERTINTD : out std_logic;
CFGMSGRECEIVEDDEASSERTINTA : out std_logic;
CFGMSGRECEIVEDDEASSERTINTB : out std_logic;
CFGMSGRECEIVEDDEASSERTINTC : out std_logic;
CFGMSGRECEIVEDDEASSERTINTD : out std_logic;
CFGMSGRECEIVEDERRCOR : out std_logic;
CFGMSGRECEIVEDERRFATAL : out std_logic;
CFGMSGRECEIVEDERRNONFATAL : out std_logic;
CFGMSGRECEIVEDPMASNAK : out std_logic;
CFGMSGRECEIVEDPMETO : out std_logic;
CFGMSGRECEIVEDPMETOACK : out std_logic;
CFGMSGRECEIVEDPMPME : out std_logic;
CFGMSGRECEIVEDSETSLOTPOWERLIMIT : out std_logic;
CFGMSGRECEIVEDUNLOCK : out std_logic;
CFGPCIELINKSTATE : out std_logic_vector(2 downto 0);
CFGPMCSRPMEEN : out std_logic;
CFGPMCSRPMESTATUS : out std_logic;
CFGPMCSRPOWERSTATE : out std_logic_vector(1 downto 0);
CFGPMRCVASREQL1N : out std_logic;
CFGPMRCVENTERL1N : out std_logic;
CFGPMRCVENTERL23N : out std_logic;
CFGPMRCVREQACKN : out std_logic;
CFGRDWRDONEN : out std_logic;
CFGSLOTCONTROLELECTROMECHILCTLPULSE : out std_logic;
CFGTRANSACTION : out std_logic;
CFGTRANSACTIONADDR : out std_logic_vector(6 downto 0);
CFGTRANSACTIONTYPE : out std_logic;
CFGVCTCVCMAP : out std_logic_vector(6 downto 0);
CFGBYTEENN : in std_logic_vector(3 downto 0);
CFGDI : in std_logic_vector(31 downto 0);
CFGDSBUSNUMBER : in std_logic_vector(7 downto 0);
CFGDSDEVICENUMBER : in std_logic_vector(4 downto 0);
CFGDSFUNCTIONNUMBER : in std_logic_vector(2 downto 0);
CFGDSN : in std_logic_vector(63 downto 0);
CFGDWADDR : in std_logic_vector(9 downto 0);
CFGERRACSN : in std_logic;
CFGERRAERHEADERLOG : in std_logic_vector(127 downto 0);
CFGERRCORN : in std_logic;
CFGERRCPLABORTN : in std_logic;
CFGERRCPLTIMEOUTN : in std_logic;
CFGERRCPLUNEXPECTN : in std_logic;
CFGERRECRCN : in std_logic;
CFGERRLOCKEDN : in std_logic;
CFGERRPOSTEDN : in std_logic;
CFGERRTLPCPLHEADER : in std_logic_vector(47 downto 0);
CFGERRURN : in std_logic;
CFGINTERRUPTASSERTN : in std_logic;
CFGINTERRUPTDI : in std_logic_vector(7 downto 0);
CFGINTERRUPTN : in std_logic;
CFGPMDIRECTASPML1N : in std_logic;
CFGPMSENDPMACKN : in std_logic;
CFGPMSENDPMETON : in std_logic;
CFGPMSENDPMNAKN : in std_logic;
CFGPMTURNOFFOKN : in std_logic;
CFGPMWAKEN : in std_logic;
CFGPORTNUMBER : in std_logic_vector(7 downto 0);
CFGRDENN : in std_logic;
CFGTRNPENDINGN : in std_logic;
CFGWRENN : in std_logic;
CFGWRREADONLYN : in std_logic;
CFGWRRW1CASRWN : in std_logic;
PLINITIALLINKWIDTH : out std_logic_vector(2 downto 0);
PLLANEREVERSALMODE : out std_logic_vector(1 downto 0);
PLLINKGEN2CAP : out std_logic;
PLLINKPARTNERGEN2SUPPORTED : out std_logic;
PLLINKUPCFGCAP : out std_logic;
PLLTSSMSTATE : out std_logic_vector(5 downto 0);
PLPHYLNKUPN : out std_logic;
PLRECEIVEDHOTRST : out std_logic;
PLRXPMSTATE : out std_logic_vector(1 downto 0);
PLSELLNKRATE : out std_logic;
PLSELLNKWIDTH : out std_logic_vector(1 downto 0);
PLTXPMSTATE : out std_logic_vector(2 downto 0);
PLDIRECTEDLINKAUTON : in std_logic;
PLDIRECTEDLINKCHANGE : in std_logic_vector(1 downto 0);
PLDIRECTEDLINKSPEED : in std_logic;
PLDIRECTEDLINKWIDTH : in std_logic_vector(1 downto 0);
PLDOWNSTREAMDEEMPHSOURCE : in std_logic;
PLUPSTREAMPREFERDEEMPH : in std_logic;
PLTRANSMITHOTRST : in std_logic;
DBGSCLRA : out std_logic;
DBGSCLRB : out std_logic;
DBGSCLRC : out std_logic;
DBGSCLRD : out std_logic;
DBGSCLRE : out std_logic;
DBGSCLRF : out std_logic;
DBGSCLRG : out std_logic;
DBGSCLRH : out std_logic;
DBGSCLRI : out std_logic;
DBGSCLRJ : out std_logic;
DBGSCLRK : out std_logic;
DBGVECA : out std_logic_vector(63 downto 0);
DBGVECB : out std_logic_vector(63 downto 0);
DBGVECC : out std_logic_vector(11 downto 0);
PLDBGVEC : out std_logic_vector(11 downto 0);
DBGMODE : in std_logic_vector(1 downto 0);
DBGSUBMODE : in std_logic;
PLDBGMODE : in std_logic_vector(2 downto 0);
PCIEDRPDO : out std_logic_vector(15 downto 0);
PCIEDRPDRDY : out std_logic;
PCIEDRPCLK : in std_logic;
PCIEDRPDADDR : in std_logic_vector(8 downto 0);
PCIEDRPDEN : in std_logic;
PCIEDRPDI : in std_logic_vector(15 downto 0);
PCIEDRPDWE : in std_logic;
GTPLLLOCK : out std_logic;
PIPECLK : in std_logic;
USERCLK : in std_logic;
DRPCLK : in std_logic;
CLOCKLOCKED : in std_logic;
TxOutClk : out std_logic
);
end pcie_2_0_v6_rp;
architecture v6_pcie of pcie_2_0_v6_rp is
component pcie_pipe_v6
generic (
NO_OF_LANES : integer;
LINK_CAP_MAX_LINK_SPEED : bit_vector;
PIPE_PIPELINE_STAGES : integer);
port (
pipe_tx_rcvr_det_i : in std_logic;
pipe_tx_reset_i : in std_logic;
pipe_tx_rate_i : in std_logic;
pipe_tx_deemph_i : in std_logic;
pipe_tx_margin_i : in std_logic_vector(2 downto 0);
pipe_tx_swing_i : in std_logic;
pipe_tx_rcvr_det_o : out std_logic;
pipe_tx_reset_o : out std_logic;
pipe_tx_rate_o : out std_logic;
pipe_tx_deemph_o : out std_logic;
pipe_tx_margin_o : out std_logic_vector(2 downto 0);
pipe_tx_swing_o : out std_logic;
pipe_rx0_char_is_k_o : out std_logic_vector(1 downto 0);
pipe_rx0_data_o : out std_logic_vector(15 downto 0);
pipe_rx0_valid_o : out std_logic;
pipe_rx0_chanisaligned_o : out std_logic;
pipe_rx0_status_o : out std_logic_vector(2 downto 0);
pipe_rx0_phy_status_o : out std_logic;
pipe_rx0_elec_idle_o : out std_logic;
pipe_rx0_polarity_i : in std_logic;
pipe_tx0_compliance_i : in std_logic;
pipe_tx0_char_is_k_i : in std_logic_vector(1 downto 0);
pipe_tx0_data_i : in std_logic_vector(15 downto 0);
pipe_tx0_elec_idle_i : in std_logic;
pipe_tx0_powerdown_i : in std_logic_vector(1 downto 0);
pipe_rx0_char_is_k_i : in std_logic_vector(1 downto 0);
pipe_rx0_data_i : in std_logic_vector(15 downto 0);
pipe_rx0_valid_i : in std_logic;
pipe_rx0_chanisaligned_i : in std_logic;
pipe_rx0_status_i : in std_logic_vector(2 downto 0);
pipe_rx0_phy_status_i : in std_logic;
pipe_rx0_elec_idle_i : in std_logic;
pipe_rx0_polarity_o : out std_logic;
pipe_tx0_compliance_o : out std_logic;
pipe_tx0_char_is_k_o : out std_logic_vector(1 downto 0);
pipe_tx0_data_o : out std_logic_vector(15 downto 0);
pipe_tx0_elec_idle_o : out std_logic;
pipe_tx0_powerdown_o : out std_logic_vector(1 downto 0);
pipe_rx1_char_is_k_o : out std_logic_vector(1 downto 0);
pipe_rx1_data_o : out std_logic_vector(15 downto 0);
pipe_rx1_valid_o : out std_logic;
pipe_rx1_chanisaligned_o : out std_logic;
pipe_rx1_status_o : out std_logic_vector(2 downto 0);
pipe_rx1_phy_status_o : out std_logic;
pipe_rx1_elec_idle_o : out std_logic;
pipe_rx1_polarity_i : in std_logic;
pipe_tx1_compliance_i : in std_logic;
pipe_tx1_char_is_k_i : in std_logic_vector(1 downto 0);
pipe_tx1_data_i : in std_logic_vector(15 downto 0);
pipe_tx1_elec_idle_i : in std_logic;
pipe_tx1_powerdown_i : in std_logic_vector(1 downto 0);
pipe_rx1_char_is_k_i : in std_logic_vector(1 downto 0);
pipe_rx1_data_i : in std_logic_vector(15 downto 0);
pipe_rx1_valid_i : in std_logic;
pipe_rx1_chanisaligned_i : in std_logic;
pipe_rx1_status_i : in std_logic_vector(2 downto 0);
pipe_rx1_phy_status_i : in std_logic;
pipe_rx1_elec_idle_i : in std_logic;
pipe_rx1_polarity_o : out std_logic;
pipe_tx1_compliance_o : out std_logic;
pipe_tx1_char_is_k_o : out std_logic_vector(1 downto 0);
pipe_tx1_data_o : out std_logic_vector(15 downto 0);
pipe_tx1_elec_idle_o : out std_logic;
pipe_tx1_powerdown_o : out std_logic_vector(1 downto 0);
pipe_rx2_char_is_k_o : out std_logic_vector(1 downto 0);
pipe_rx2_data_o : out std_logic_vector(15 downto 0);
pipe_rx2_valid_o : out std_logic;
pipe_rx2_chanisaligned_o : out std_logic;
pipe_rx2_status_o : out std_logic_vector(2 downto 0);
pipe_rx2_phy_status_o : out std_logic;
pipe_rx2_elec_idle_o : out std_logic;
pipe_rx2_polarity_i : in std_logic;
pipe_tx2_compliance_i : in std_logic;
pipe_tx2_char_is_k_i : in std_logic_vector(1 downto 0);
pipe_tx2_data_i : in std_logic_vector(15 downto 0);
pipe_tx2_elec_idle_i : in std_logic;
pipe_tx2_powerdown_i : in std_logic_vector(1 downto 0);
pipe_rx2_char_is_k_i : in std_logic_vector(1 downto 0);
pipe_rx2_data_i : in std_logic_vector(15 downto 0);
pipe_rx2_valid_i : in std_logic;
pipe_rx2_chanisaligned_i : in std_logic;
pipe_rx2_status_i : in std_logic_vector(2 downto 0);
pipe_rx2_phy_status_i : in std_logic;
pipe_rx2_elec_idle_i : in std_logic;
pipe_rx2_polarity_o : out std_logic;
pipe_tx2_compliance_o : out std_logic;
pipe_tx2_char_is_k_o : out std_logic_vector(1 downto 0);
pipe_tx2_data_o : out std_logic_vector(15 downto 0);
pipe_tx2_elec_idle_o : out std_logic;
pipe_tx2_powerdown_o : out std_logic_vector(1 downto 0);
pipe_rx3_char_is_k_o : out std_logic_vector(1 downto 0);
pipe_rx3_data_o : out std_logic_vector(15 downto 0);
pipe_rx3_valid_o : out std_logic;
pipe_rx3_chanisaligned_o : out std_logic;
pipe_rx3_status_o : out std_logic_vector(2 downto 0);
pipe_rx3_phy_status_o : out std_logic;
pipe_rx3_elec_idle_o : out std_logic;
pipe_rx3_polarity_i : in std_logic;
pipe_tx3_compliance_i : in std_logic;
pipe_tx3_char_is_k_i : in std_logic_vector(1 downto 0);
pipe_tx3_data_i : in std_logic_vector(15 downto 0);
pipe_tx3_elec_idle_i : in std_logic;
pipe_tx3_powerdown_i : in std_logic_vector(1 downto 0);
pipe_rx3_char_is_k_i : in std_logic_vector(1 downto 0);
pipe_rx3_data_i : in std_logic_vector(15 downto 0);
pipe_rx3_valid_i : in std_logic;
pipe_rx3_chanisaligned_i : in std_logic;
pipe_rx3_status_i : in std_logic_vector(2 downto 0);
pipe_rx3_phy_status_i : in std_logic;
pipe_rx3_elec_idle_i : in std_logic;
pipe_rx3_polarity_o : out std_logic;
pipe_tx3_compliance_o : out std_logic;
pipe_tx3_char_is_k_o : out std_logic_vector(1 downto 0);
pipe_tx3_data_o : out std_logic_vector(15 downto 0);
pipe_tx3_elec_idle_o : out std_logic;
pipe_tx3_powerdown_o : out std_logic_vector(1 downto 0);
pipe_rx4_char_is_k_o : out std_logic_vector(1 downto 0);
pipe_rx4_data_o : out std_logic_vector(15 downto 0);
pipe_rx4_valid_o : out std_logic;
pipe_rx4_chanisaligned_o : out std_logic;
pipe_rx4_status_o : out std_logic_vector(2 downto 0);
pipe_rx4_phy_status_o : out std_logic;
pipe_rx4_elec_idle_o : out std_logic;
pipe_rx4_polarity_i : in std_logic;
pipe_tx4_compliance_i : in std_logic;
pipe_tx4_char_is_k_i : in std_logic_vector(1 downto 0);
pipe_tx4_data_i : in std_logic_vector(15 downto 0);
pipe_tx4_elec_idle_i : in std_logic;
pipe_tx4_powerdown_i : in std_logic_vector(1 downto 0);
pipe_rx4_char_is_k_i : in std_logic_vector(1 downto 0);
pipe_rx4_data_i : in std_logic_vector(15 downto 0);
pipe_rx4_valid_i : in std_logic;
pipe_rx4_chanisaligned_i : in std_logic;
pipe_rx4_status_i : in std_logic_vector(2 downto 0);
pipe_rx4_phy_status_i : in std_logic;
pipe_rx4_elec_idle_i : in std_logic;
pipe_rx4_polarity_o : out std_logic;
pipe_tx4_compliance_o : out std_logic;
pipe_tx4_char_is_k_o : out std_logic_vector(1 downto 0);
pipe_tx4_data_o : out std_logic_vector(15 downto 0);
pipe_tx4_elec_idle_o : out std_logic;
pipe_tx4_powerdown_o : out std_logic_vector(1 downto 0);
pipe_rx5_char_is_k_o : out std_logic_vector(1 downto 0);
pipe_rx5_data_o : out std_logic_vector(15 downto 0);
pipe_rx5_valid_o : out std_logic;
pipe_rx5_chanisaligned_o : out std_logic;
pipe_rx5_status_o : out std_logic_vector(2 downto 0);
pipe_rx5_phy_status_o : out std_logic;
pipe_rx5_elec_idle_o : out std_logic;
pipe_rx5_polarity_i : in std_logic;
pipe_tx5_compliance_i : in std_logic;
pipe_tx5_char_is_k_i : in std_logic_vector(1 downto 0);
pipe_tx5_data_i : in std_logic_vector(15 downto 0);
pipe_tx5_elec_idle_i : in std_logic;
pipe_tx5_powerdown_i : in std_logic_vector(1 downto 0);
pipe_rx5_char_is_k_i : in std_logic_vector(1 downto 0);
pipe_rx5_data_i : in std_logic_vector(15 downto 0);
pipe_rx5_valid_i : in std_logic;
pipe_rx5_chanisaligned_i : in std_logic;
pipe_rx5_status_i : in std_logic_vector(2 downto 0);
pipe_rx5_phy_status_i : in std_logic;
pipe_rx5_elec_idle_i : in std_logic;
pipe_rx5_polarity_o : out std_logic;
pipe_tx5_compliance_o : out std_logic;
pipe_tx5_char_is_k_o : out std_logic_vector(1 downto 0);
pipe_tx5_data_o : out std_logic_vector(15 downto 0);
pipe_tx5_elec_idle_o : out std_logic;
pipe_tx5_powerdown_o : out std_logic_vector(1 downto 0);
pipe_rx6_char_is_k_o : out std_logic_vector(1 downto 0);
pipe_rx6_data_o : out std_logic_vector(15 downto 0);
pipe_rx6_valid_o : out std_logic;
pipe_rx6_chanisaligned_o : out std_logic;
pipe_rx6_status_o : out std_logic_vector(2 downto 0);
pipe_rx6_phy_status_o : out std_logic;
pipe_rx6_elec_idle_o : out std_logic;
pipe_rx6_polarity_i : in std_logic;
pipe_tx6_compliance_i : in std_logic;
pipe_tx6_char_is_k_i : in std_logic_vector(1 downto 0);
pipe_tx6_data_i : in std_logic_vector(15 downto 0);
pipe_tx6_elec_idle_i : in std_logic;
pipe_tx6_powerdown_i : in std_logic_vector(1 downto 0);
pipe_rx6_char_is_k_i : in std_logic_vector(1 downto 0);
pipe_rx6_data_i : in std_logic_vector(15 downto 0);
pipe_rx6_valid_i : in std_logic;
pipe_rx6_chanisaligned_i : in std_logic;
pipe_rx6_status_i : in std_logic_vector(2 downto 0);
pipe_rx6_phy_status_i : in std_logic;
pipe_rx6_elec_idle_i : in std_logic;
pipe_rx6_polarity_o : out std_logic;
pipe_tx6_compliance_o : out std_logic;
pipe_tx6_char_is_k_o : out std_logic_vector(1 downto 0);
pipe_tx6_data_o : out std_logic_vector(15 downto 0);
pipe_tx6_elec_idle_o : out std_logic;
pipe_tx6_powerdown_o : out std_logic_vector(1 downto 0);
pipe_rx7_char_is_k_o : out std_logic_vector(1 downto 0);
pipe_rx7_data_o : out std_logic_vector(15 downto 0);
pipe_rx7_valid_o : out std_logic;
pipe_rx7_chanisaligned_o : out std_logic;
pipe_rx7_status_o : out std_logic_vector(2 downto 0);
pipe_rx7_phy_status_o : out std_logic;
pipe_rx7_elec_idle_o : out std_logic;
pipe_rx7_polarity_i : in std_logic;
pipe_tx7_compliance_i : in std_logic;
pipe_tx7_char_is_k_i : in std_logic_vector(1 downto 0);
pipe_tx7_data_i : in std_logic_vector(15 downto 0);
pipe_tx7_elec_idle_i : in std_logic;
pipe_tx7_powerdown_i : in std_logic_vector(1 downto 0);
pipe_rx7_char_is_k_i : in std_logic_vector(1 downto 0);
pipe_rx7_data_i : in std_logic_vector(15 downto 0);
pipe_rx7_valid_i : in std_logic;
pipe_rx7_chanisaligned_i : in std_logic;
pipe_rx7_status_i : in std_logic_vector(2 downto 0);
pipe_rx7_phy_status_i : in std_logic;
pipe_rx7_elec_idle_i : in std_logic;
pipe_rx7_polarity_o : out std_logic;
pipe_tx7_compliance_o : out std_logic;
pipe_tx7_char_is_k_o : out std_logic_vector(1 downto 0);
pipe_tx7_data_o : out std_logic_vector(15 downto 0);
pipe_tx7_elec_idle_o : out std_logic;
pipe_tx7_powerdown_o : out std_logic_vector(1 downto 0);
pl_ltssm_state : in std_logic_vector(5 downto 0);
pipe_clk : in std_logic;
rst_n : in std_logic);
end component;
component pcie_gtx_v6
generic (
NO_OF_LANES : integer;
LINK_CAP_MAX_LINK_SPEED : bit_vector;
REF_CLK_FREQ : integer;
PL_FAST_TRAIN : boolean);
port (
pipe_tx_rcvr_det : in std_logic;
pipe_tx_reset : in std_logic;
pipe_tx_rate : in std_logic;
pipe_tx_deemph : in std_logic;
pipe_tx_margin : in std_logic_vector(2 downto 0);
pipe_tx_swing : in std_logic;
pipe_rx0_char_is_k : out std_logic_vector(1 downto 0);
pipe_rx0_data : out std_logic_vector(15 downto 0);
pipe_rx0_valid : out std_logic;
pipe_rx0_chanisaligned : out std_logic;
pipe_rx0_status : out std_logic_vector(2 downto 0);
pipe_rx0_phy_status : out std_logic;
pipe_rx0_elec_idle : out std_logic;
pipe_rx0_polarity : in std_logic;
pipe_tx0_compliance : in std_logic;
pipe_tx0_char_is_k : in std_logic_vector(1 downto 0);
pipe_tx0_data : in std_logic_vector(15 downto 0);
pipe_tx0_elec_idle : in std_logic;
pipe_tx0_powerdown : in std_logic_vector(1 downto 0);
pipe_rx1_char_is_k : out std_logic_vector(1 downto 0);
pipe_rx1_data : out std_logic_vector(15 downto 0);
pipe_rx1_valid : out std_logic;
pipe_rx1_chanisaligned : out std_logic;
pipe_rx1_status : out std_logic_vector(2 downto 0);
pipe_rx1_phy_status : out std_logic;
pipe_rx1_elec_idle : out std_logic;
pipe_rx1_polarity : in std_logic;
pipe_tx1_compliance : in std_logic;
pipe_tx1_char_is_k : in std_logic_vector(1 downto 0);
pipe_tx1_data : in std_logic_vector(15 downto 0);
pipe_tx1_elec_idle : in std_logic;
pipe_tx1_powerdown : in std_logic_vector(1 downto 0);
pipe_rx2_char_is_k : out std_logic_vector(1 downto 0);
pipe_rx2_data : out std_logic_vector(15 downto 0);
pipe_rx2_valid : out std_logic;
pipe_rx2_chanisaligned : out std_logic;
pipe_rx2_status : out std_logic_vector(2 downto 0);
pipe_rx2_phy_status : out std_logic;
pipe_rx2_elec_idle : out std_logic;
pipe_rx2_polarity : in std_logic;
pipe_tx2_compliance : in std_logic;
pipe_tx2_char_is_k : in std_logic_vector(1 downto 0);
pipe_tx2_data : in std_logic_vector(15 downto 0);
pipe_tx2_elec_idle : in std_logic;
pipe_tx2_powerdown : in std_logic_vector(1 downto 0);
pipe_rx3_char_is_k : out std_logic_vector(1 downto 0);
pipe_rx3_data : out std_logic_vector(15 downto 0);
pipe_rx3_valid : out std_logic;
pipe_rx3_chanisaligned : out std_logic;
pipe_rx3_status : out std_logic_vector(2 downto 0);
pipe_rx3_phy_status : out std_logic;
pipe_rx3_elec_idle : out std_logic;
pipe_rx3_polarity : in std_logic;
pipe_tx3_compliance : in std_logic;
pipe_tx3_char_is_k : in std_logic_vector(1 downto 0);
pipe_tx3_data : in std_logic_vector(15 downto 0);
pipe_tx3_elec_idle : in std_logic;
pipe_tx3_powerdown : in std_logic_vector(1 downto 0);
pipe_rx4_char_is_k : out std_logic_vector(1 downto 0);
pipe_rx4_data : out std_logic_vector(15 downto 0);
pipe_rx4_valid : out std_logic;
pipe_rx4_chanisaligned : out std_logic;
pipe_rx4_status : out std_logic_vector(2 downto 0);
pipe_rx4_phy_status : out std_logic;
pipe_rx4_elec_idle : out std_logic;
pipe_rx4_polarity : in std_logic;
pipe_tx4_compliance : in std_logic;
pipe_tx4_char_is_k : in std_logic_vector(1 downto 0);
pipe_tx4_data : in std_logic_vector(15 downto 0);
pipe_tx4_elec_idle : in std_logic;
pipe_tx4_powerdown : in std_logic_vector(1 downto 0);
pipe_rx5_char_is_k : out std_logic_vector(1 downto 0);
pipe_rx5_data : out std_logic_vector(15 downto 0);
pipe_rx5_valid : out std_logic;
pipe_rx5_chanisaligned : out std_logic;
pipe_rx5_status : out std_logic_vector(2 downto 0);
pipe_rx5_phy_status : out std_logic;
pipe_rx5_elec_idle : out std_logic;
pipe_rx5_polarity : in std_logic;
pipe_tx5_compliance : in std_logic;
pipe_tx5_char_is_k : in std_logic_vector(1 downto 0);
pipe_tx5_data : in std_logic_vector(15 downto 0);
pipe_tx5_elec_idle : in std_logic;
pipe_tx5_powerdown : in std_logic_vector(1 downto 0);
pipe_rx6_char_is_k : out std_logic_vector(1 downto 0);
pipe_rx6_data : out std_logic_vector(15 downto 0);
pipe_rx6_valid : out std_logic;
pipe_rx6_chanisaligned : out std_logic;
pipe_rx6_status : out std_logic_vector(2 downto 0);
pipe_rx6_phy_status : out std_logic;
pipe_rx6_elec_idle : out std_logic;
pipe_rx6_polarity : in std_logic;
pipe_tx6_compliance : in std_logic;
pipe_tx6_char_is_k : in std_logic_vector(1 downto 0);
pipe_tx6_data : in std_logic_vector(15 downto 0);
pipe_tx6_elec_idle : in std_logic;
pipe_tx6_powerdown : in std_logic_vector(1 downto 0);
pipe_rx7_char_is_k : out std_logic_vector(1 downto 0);
pipe_rx7_data : out std_logic_vector(15 downto 0);
pipe_rx7_valid : out std_logic;
pipe_rx7_chanisaligned : out std_logic;
pipe_rx7_status : out std_logic_vector(2 downto 0);
pipe_rx7_phy_status : out std_logic;
pipe_rx7_elec_idle : out std_logic;
pipe_rx7_polarity : in std_logic;
pipe_tx7_compliance : in std_logic;
pipe_tx7_char_is_k : in std_logic_vector(1 downto 0);
pipe_tx7_data : in std_logic_vector(15 downto 0);
pipe_tx7_elec_idle : in std_logic;
pipe_tx7_powerdown : in std_logic_vector(1 downto 0);
pci_exp_txn : out std_logic_vector((NO_OF_LANES - 1) downto 0);
pci_exp_txp : out std_logic_vector((NO_OF_LANES - 1) downto 0);
pci_exp_rxn : in std_logic_vector((NO_OF_LANES - 1) downto 0);
pci_exp_rxp : in std_logic_vector((NO_OF_LANES - 1) downto 0);
sys_clk : in std_logic;
sys_rst_n : in std_logic;
pipe_clk : in std_logic;
drp_clk : in std_logic;
clock_locked : in std_logic;
gt_pll_lock : out std_logic;
pl_ltssm_state : in std_logic_vector(5 downto 0);
phy_rdy_n : out std_logic;
TxOutClk : out std_logic);
end component;
component pcie_bram_top_v6
generic (
DEV_CAP_MAX_PAYLOAD_SUPPORTED : integer;
VC0_TX_LASTPACKET : integer;
TL_TX_RAM_RADDR_LATENCY : integer;
TL_TX_RAM_RDATA_LATENCY : integer;
TL_TX_RAM_WRITE_LATENCY : integer;
VC0_RX_LIMIT : bit_vector;
TL_RX_RAM_RADDR_LATENCY : integer;
TL_RX_RAM_RDATA_LATENCY : integer;
TL_RX_RAM_WRITE_LATENCY : integer);
port (
user_clk_i : in std_logic;
reset_i : in std_logic;
mim_tx_wen : in std_logic;
mim_tx_waddr : in std_logic_vector(12 downto 0);
mim_tx_wdata : in std_logic_vector(71 downto 0);
mim_tx_ren : in std_logic;
mim_tx_rce : in std_logic;
mim_tx_raddr : in std_logic_vector(12 downto 0);
mim_tx_rdata : out std_logic_vector(71 downto 0);
mim_rx_wen : in std_logic;
mim_rx_waddr : in std_logic_vector(12 downto 0);
mim_rx_wdata : in std_logic_vector(71 downto 0);
mim_rx_ren : in std_logic;
mim_rx_rce : in std_logic;
mim_rx_raddr : in std_logic_vector(12 downto 0);
mim_rx_rdata : out std_logic_vector(71 downto 0));
end component;
component pcie_upconfig_fix_3451_v6
generic (
UPSTREAM_FACING : boolean;
PL_FAST_TRAIN : boolean;
LINK_CAP_MAX_LINK_WIDTH : bit_vector);
port (
pipe_clk : in std_logic;
pl_phy_lnkup_n : in std_logic;
pl_ltssm_state : in std_logic_vector(5 downto 0);
pl_sel_lnk_rate : in std_logic;
pl_directed_link_change : in std_logic_vector(1 downto 0);
cfg_link_status_negotiated_width : in std_logic_vector(3 downto 0);
filter_pipe : out std_logic);
end component;
-- wire declarations
signal LL2BADDLLPERRN : std_logic;
signal LL2BADTLPERRN : std_logic;
signal LL2PROTOCOLERRN : std_logic;
signal LL2REPLAYROERRN : std_logic;
signal LL2REPLAYTOERRN : std_logic;
signal LL2SUSPENDOKN : std_logic;
signal LL2TFCINIT1SEQN : std_logic;
signal LL2TFCINIT2SEQN : std_logic;
signal MIMRXRADDR : std_logic_vector(12 downto 0);
signal MIMRXRCE : std_logic;
signal MIMRXREN : std_logic;
signal MIMRXWADDR : std_logic_vector(12 downto 0);
signal MIMRXWDATA : std_logic_vector(67 downto 0);
signal MIMRXWDATA_tmp : std_logic_vector(71 downto 0);
signal MIMRXWEN : std_logic;
signal MIMTXRADDR : std_logic_vector(12 downto 0);
signal MIMTXRCE : std_logic;
signal MIMTXREN : std_logic;
signal MIMTXWADDR : std_logic_vector(12 downto 0);
signal MIMTXWDATA : std_logic_vector(68 downto 0);
signal MIMTXWDATA_tmp : std_logic_vector(71 downto 0);
signal MIMTXWEN : std_logic;
signal PIPERX0POLARITY : std_logic;
signal PIPERX1POLARITY : std_logic;
signal PIPERX2POLARITY : std_logic;
signal PIPERX3POLARITY : std_logic;
signal PIPERX4POLARITY : std_logic;
signal PIPERX5POLARITY : std_logic;
signal PIPERX6POLARITY : std_logic;
signal PIPERX7POLARITY : std_logic;
signal PIPETXDEEMPH : std_logic;
signal PIPETXMARGIN : std_logic_vector(2 downto 0);
signal PIPETXRATE : std_logic;
signal PIPETXRCVRDET : std_logic;
signal PIPETXRESET : std_logic;
signal PIPETX0CHARISK : std_logic_vector(1 downto 0);
signal PIPETX0COMPLIANCE : std_logic;
signal PIPETX0DATA : std_logic_vector(15 downto 0);
signal PIPETX0ELECIDLE : std_logic;
signal PIPETX0POWERDOWN : std_logic_vector(1 downto 0);
signal PIPETX1CHARISK : std_logic_vector(1 downto 0);
signal PIPETX1COMPLIANCE : std_logic;
signal PIPETX1DATA : std_logic_vector(15 downto 0);
signal PIPETX1ELECIDLE : std_logic;
signal PIPETX1POWERDOWN : std_logic_vector(1 downto 0);
signal PIPETX2CHARISK : std_logic_vector(1 downto 0);
signal PIPETX2COMPLIANCE : std_logic;
signal PIPETX2DATA : std_logic_vector(15 downto 0);
signal PIPETX2ELECIDLE : std_logic;
signal PIPETX2POWERDOWN : std_logic_vector(1 downto 0);
signal PIPETX3CHARISK : std_logic_vector(1 downto 0);
signal PIPETX3COMPLIANCE : std_logic;
signal PIPETX3DATA : std_logic_vector(15 downto 0);
signal PIPETX3ELECIDLE : std_logic;
signal PIPETX3POWERDOWN : std_logic_vector(1 downto 0);
signal PIPETX4CHARISK : std_logic_vector(1 downto 0);
signal PIPETX4COMPLIANCE : std_logic;
signal PIPETX4DATA : std_logic_vector(15 downto 0);
signal PIPETX4ELECIDLE : std_logic;
signal PIPETX4POWERDOWN : std_logic_vector(1 downto 0);
signal PIPETX5CHARISK : std_logic_vector(1 downto 0);
signal PIPETX5COMPLIANCE : std_logic;
signal PIPETX5DATA : std_logic_vector(15 downto 0);
signal PIPETX5ELECIDLE : std_logic;
signal PIPETX5POWERDOWN : std_logic_vector(1 downto 0);
signal PIPETX6CHARISK : std_logic_vector(1 downto 0);
signal PIPETX6COMPLIANCE : std_logic;
signal PIPETX6DATA : std_logic_vector(15 downto 0);
signal PIPETX6ELECIDLE : std_logic;
signal PIPETX6POWERDOWN : std_logic_vector(1 downto 0);
signal PIPETX7CHARISK : std_logic_vector(1 downto 0);
signal PIPETX7COMPLIANCE : std_logic;
signal PIPETX7DATA : std_logic_vector(15 downto 0);
signal PIPETX7ELECIDLE : std_logic;
signal PIPETX7POWERDOWN : std_logic_vector(1 downto 0);
signal PL2LINKUPN : std_logic;
signal PL2RECEIVERERRN : std_logic;
signal PL2RECOVERYN : std_logic;
signal PL2RXELECIDLE : std_logic;
signal PL2SUSPENDOK : std_logic;
signal TL2ASPMSUSPENDCREDITCHECKOKN : std_logic;
signal TL2ASPMSUSPENDREQN : std_logic;
signal TL2PPMSUSPENDOKN : std_logic;
signal LL2SENDASREQL1N : std_logic;
signal LL2SENDENTERL1N : std_logic;
signal LL2SENDENTERL23N : std_logic;
signal LL2SUSPENDNOWN : std_logic;
signal LL2TLPRCVN : std_logic;
signal MIMRXRDATA : std_logic_vector(71 downto 0);
signal MIMTXRDATA : std_logic_vector(71 downto 0);
signal PL2DIRECTEDLSTATE : std_logic_vector(4 downto 0);
signal TL2ASPMSUSPENDCREDITCHECKN : std_logic;
signal TL2PPMSUSPENDREQN : std_logic;
signal PIPERX0CHANISALIGNED : std_logic;
signal PIPERX0CHARISK : std_logic_vector(1 downto 0);
signal PIPERX0DATA : std_logic_vector(15 downto 0);
signal PIPERX0ELECIDLE : std_logic;
signal PIPERX0PHYSTATUS : std_logic;
signal PIPERX0STATUS : std_logic_vector(2 downto 0);
signal PIPERX0VALID : std_logic;
signal PIPERX1CHANISALIGNED : std_logic;
signal PIPERX1CHARISK : std_logic_vector(1 downto 0);
signal PIPERX1DATA : std_logic_vector(15 downto 0);
signal PIPERX1ELECIDLE : std_logic;
signal PIPERX1PHYSTATUS : std_logic;
signal PIPERX1STATUS : std_logic_vector(2 downto 0);
signal PIPERX1VALID : std_logic;
signal PIPERX2CHANISALIGNED : std_logic;
signal PIPERX2CHARISK : std_logic_vector(1 downto 0);
signal PIPERX2DATA : std_logic_vector(15 downto 0);
signal PIPERX2ELECIDLE : std_logic;
signal PIPERX2PHYSTATUS : std_logic;
signal PIPERX2STATUS : std_logic_vector(2 downto 0);
signal PIPERX2VALID : std_logic;
signal PIPERX3CHANISALIGNED : std_logic;
signal PIPERX3CHARISK : std_logic_vector(1 downto 0);
signal PIPERX3DATA : std_logic_vector(15 downto 0);
signal PIPERX3ELECIDLE : std_logic;
signal PIPERX3PHYSTATUS : std_logic;
signal PIPERX3STATUS : std_logic_vector(2 downto 0);
signal PIPERX3VALID : std_logic;
signal PIPERX4CHANISALIGNED : std_logic;
signal PIPERX4CHARISK : std_logic_vector(1 downto 0);
signal PIPERX4DATA : std_logic_vector(15 downto 0);
signal PIPERX4ELECIDLE : std_logic;
signal PIPERX4PHYSTATUS : std_logic;
signal PIPERX4STATUS : std_logic_vector(2 downto 0);
signal PIPERX4VALID : std_logic;
signal PIPERX5CHANISALIGNED : std_logic;
signal PIPERX5CHARISK : std_logic_vector(1 downto 0);
signal PIPERX5DATA : std_logic_vector(15 downto 0);
signal PIPERX5ELECIDLE : std_logic;
signal PIPERX5PHYSTATUS : std_logic;
signal PIPERX5STATUS : std_logic_vector(2 downto 0);
signal PIPERX5VALID : std_logic;
signal PIPERX6CHANISALIGNED : std_logic;
signal PIPERX6CHARISK : std_logic_vector(1 downto 0);
signal PIPERX6DATA : std_logic_vector(15 downto 0);
signal PIPERX6ELECIDLE : std_logic;
signal PIPERX6PHYSTATUS : std_logic;
signal PIPERX6STATUS : std_logic_vector(2 downto 0);
signal PIPERX6VALID : std_logic;
signal PIPERX7CHANISALIGNED : std_logic;
signal PIPERX7CHARISK : std_logic_vector(1 downto 0);
signal PIPERX7DATA : std_logic_vector(15 downto 0);
signal PIPERX7ELECIDLE : std_logic;
signal PIPERX7PHYSTATUS : std_logic;
signal PIPERX7STATUS : std_logic_vector(2 downto 0);
signal PIPERX7VALID : std_logic;
signal PIPERX0POLARITYGT : std_logic;
signal PIPERX1POLARITYGT : std_logic;
signal PIPERX2POLARITYGT : std_logic;
signal PIPERX3POLARITYGT : std_logic;
signal PIPERX4POLARITYGT : std_logic;
signal PIPERX5POLARITYGT : std_logic;
signal PIPERX6POLARITYGT : std_logic;
signal PIPERX7POLARITYGT : std_logic;
signal PIPETXDEEMPHGT : std_logic;
signal PIPETXMARGINGT : std_logic_vector(2 downto 0);
signal PIPETXRATEGT : std_logic;
signal PIPETXRCVRDETGT : std_logic;
signal PIPETX0CHARISKGT : std_logic_vector(1 downto 0);
signal PIPETX0COMPLIANCEGT : std_logic;
signal PIPETX0DATAGT : std_logic_vector(15 downto 0);
signal PIPETX0ELECIDLEGT : std_logic;
signal PIPETX0POWERDOWNGT : std_logic_vector(1 downto 0);
signal PIPETX1CHARISKGT : std_logic_vector(1 downto 0);
signal PIPETX1COMPLIANCEGT : std_logic;
signal PIPETX1DATAGT : std_logic_vector(15 downto 0);
signal PIPETX1ELECIDLEGT : std_logic;
signal PIPETX1POWERDOWNGT : std_logic_vector(1 downto 0);
signal PIPETX2CHARISKGT : std_logic_vector(1 downto 0);
signal PIPETX2COMPLIANCEGT : std_logic;
signal PIPETX2DATAGT : std_logic_vector(15 downto 0);
signal PIPETX2ELECIDLEGT : std_logic;
signal PIPETX2POWERDOWNGT : std_logic_vector(1 downto 0);
signal PIPETX3CHARISKGT : std_logic_vector(1 downto 0);
signal PIPETX3COMPLIANCEGT : std_logic;
signal PIPETX3DATAGT : std_logic_vector(15 downto 0);
signal PIPETX3ELECIDLEGT : std_logic;
signal PIPETX3POWERDOWNGT : std_logic_vector(1 downto 0);
signal PIPETX4CHARISKGT : std_logic_vector(1 downto 0);
signal PIPETX4COMPLIANCEGT : std_logic;
signal PIPETX4DATAGT : std_logic_vector(15 downto 0);
signal PIPETX4ELECIDLEGT : std_logic;
signal PIPETX4POWERDOWNGT : std_logic_vector(1 downto 0);
signal PIPETX5CHARISKGT : std_logic_vector(1 downto 0);
signal PIPETX5COMPLIANCEGT : std_logic;
signal PIPETX5DATAGT : std_logic_vector(15 downto 0);
signal PIPETX5ELECIDLEGT : std_logic;
signal PIPETX5POWERDOWNGT : std_logic_vector(1 downto 0);
signal PIPETX6CHARISKGT : std_logic_vector(1 downto 0);
signal PIPETX6COMPLIANCEGT : std_logic;
signal PIPETX6DATAGT : std_logic_vector(15 downto 0);
signal PIPETX6ELECIDLEGT : std_logic;
signal PIPETX6POWERDOWNGT : std_logic_vector(1 downto 0);
signal PIPETX7CHARISKGT : std_logic_vector(1 downto 0);
signal PIPETX7COMPLIANCEGT : std_logic;
signal PIPETX7DATAGT : std_logic_vector(15 downto 0);
signal PIPETX7ELECIDLEGT : std_logic;
signal PIPETX7POWERDOWNGT : std_logic_vector(1 downto 0);
signal PIPERX0CHANISALIGNEDGT : std_logic;
signal PIPERX0CHARISKGT : std_logic_vector(1 downto 0);
signal PIPERX0DATAGT : std_logic_vector(15 downto 0);
signal PIPERX0ELECIDLEGT : std_logic;
signal PIPERX0PHYSTATUSGT : std_logic;
signal PIPERX0STATUSGT : std_logic_vector(2 downto 0);
signal PIPERX0VALIDGT : std_logic;
signal PIPERX1CHANISALIGNEDGT : std_logic;
signal PIPERX1CHARISKGT : std_logic_vector(1 downto 0);
signal PIPERX1DATAGT : std_logic_vector(15 downto 0);
signal PIPERX1ELECIDLEGT : std_logic;
signal PIPERX1PHYSTATUSGT : std_logic;
signal PIPERX1STATUSGT : std_logic_vector(2 downto 0);
signal PIPERX1VALIDGT : std_logic;
signal PIPERX2CHANISALIGNEDGT : std_logic;
signal PIPERX2CHARISKGT : std_logic_vector(1 downto 0);
signal PIPERX2DATAGT : std_logic_vector(15 downto 0);
signal PIPERX2ELECIDLEGT : std_logic;
signal PIPERX2PHYSTATUSGT : std_logic;
signal PIPERX2STATUSGT : std_logic_vector(2 downto 0);
signal PIPERX2VALIDGT : std_logic;
signal PIPERX3CHANISALIGNEDGT : std_logic;
signal PIPERX3CHARISKGT : std_logic_vector(1 downto 0);
signal PIPERX3DATAGT : std_logic_vector(15 downto 0);
signal PIPERX3ELECIDLEGT : std_logic;
signal PIPERX3PHYSTATUSGT : std_logic;
signal PIPERX3STATUSGT : std_logic_vector(2 downto 0);
signal PIPERX3VALIDGT : std_logic;
signal PIPERX4CHANISALIGNEDGT : std_logic;
signal PIPERX4CHARISKGT : std_logic_vector(1 downto 0);
signal PIPERX4DATAGT : std_logic_vector(15 downto 0);
signal PIPERX4ELECIDLEGT : std_logic;
signal PIPERX4PHYSTATUSGT : std_logic;
signal PIPERX4STATUSGT : std_logic_vector(2 downto 0);
signal PIPERX4VALIDGT : std_logic;
signal PIPERX5CHANISALIGNEDGT : std_logic;
signal PIPERX5CHARISKGT : std_logic_vector(1 downto 0);
signal PIPERX5DATAGT : std_logic_vector(15 downto 0);
signal PIPERX5ELECIDLEGT : std_logic;
signal PIPERX5PHYSTATUSGT : std_logic;
signal PIPERX5STATUSGT : std_logic_vector(2 downto 0);
signal PIPERX5VALIDGT : std_logic;
signal PIPERX6CHANISALIGNEDGT : std_logic;
signal PIPERX6CHARISKGT : std_logic_vector(1 downto 0);
signal PIPERX6DATAGT : std_logic_vector(15 downto 0);
signal PIPERX6ELECIDLEGT : std_logic;
signal PIPERX6PHYSTATUSGT : std_logic;
signal PIPERX6STATUSGT : std_logic_vector(2 downto 0);
signal PIPERX6VALIDGT : std_logic;
signal PIPERX7CHANISALIGNEDGT : std_logic;
signal PIPERX7CHARISKGT : std_logic_vector(1 downto 0);
signal PIPERX7DATAGT : std_logic_vector(15 downto 0);
signal PIPERX7ELECIDLEGT : std_logic;
signal PIPERX7PHYSTATUSGT : std_logic;
signal PIPERX7STATUSGT : std_logic_vector(2 downto 0);
signal PIPERX7VALIDGT : std_logic;
signal filter_pipe_upconfig_fix_3451 : std_logic;
signal TRNRDLLPSRCRDYN : std_logic;
-- Declare intermediate signals for referenced outputs
signal PCIEXPTXN_v6pcie100 : std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
signal PCIEXPTXP_v6pcie101 : std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
signal TRNLNKUPN_v6pcie123 : std_logic;
signal PHYRDYN_v6pcie102 : std_logic;
signal USERRSTN_v6pcie139 : std_logic;
signal RECEIVEDFUNCLVLRSTN_v6pcie116 : std_logic;
signal LNKCLKEN_v6pcie97 : std_logic;
signal TRNRBARHITN_v6pcie124 : std_logic_vector(6 downto 0);
signal TRNRD_v6pcie125 : std_logic_vector(63 downto 0);
signal TRNRECRCERRN_v6pcie126 : std_logic;
signal TRNREOFN_v6pcie127 : std_logic;
signal TRNRERRFWDN_v6pcie128 : std_logic;
signal TRNRREMN_v6pcie129 : std_logic;
signal TRNRSOFN_v6pcie130 : std_logic;
signal TRNRSRCDSCN_v6pcie131 : std_logic;
signal TRNRSRCRDYN_v6pcie132 : std_logic;
signal TRNTBUFAV_v6pcie133 : std_logic_vector(5 downto 0);
signal TRNTCFGREQN_v6pcie134 : std_logic;
signal TRNTDLLPDSTRDYN_v6pcie135 : std_logic;
signal TRNTDSTRDYN_v6pcie136 : std_logic;
signal TRNTERRDROPN_v6pcie137 : std_logic;
signal TRNFCCPLD_v6pcie117 : std_logic_vector(11 downto 0);
signal TRNFCCPLH_v6pcie118 : std_logic_vector(7 downto 0);
signal TRNFCNPD_v6pcie119 : std_logic_vector(11 downto 0);
signal TRNFCNPH_v6pcie120 : std_logic_vector(7 downto 0);
signal TRNFCPD_v6pcie121 : std_logic_vector(11 downto 0);
signal TRNFCPH_v6pcie122 : std_logic_vector(7 downto 0);
signal CFGAERECRCCHECKEN_v6pcie0 : std_logic;
signal CFGAERECRCGENEN_v6pcie1 : std_logic;
signal CFGCOMMANDBUSMASTERENABLE_v6pcie2 : std_logic;
signal CFGCOMMANDINTERRUPTDISABLE_v6pcie3 : std_logic;
signal CFGCOMMANDIOENABLE_v6pcie4 : std_logic;
signal CFGCOMMANDMEMENABLE_v6pcie5 : std_logic;
signal CFGCOMMANDSERREN_v6pcie6 : std_logic;
signal CFGDEVCONTROLAUXPOWEREN_v6pcie9 : std_logic;
signal CFGDEVCONTROLCORRERRREPORTINGEN_v6pcie10 : std_logic;
signal CFGDEVCONTROLENABLERO_v6pcie11 : std_logic;
signal CFGDEVCONTROLEXTTAGEN_v6pcie12 : std_logic;
signal CFGDEVCONTROLFATALERRREPORTINGEN_v6pcie13 : std_logic;
signal CFGDEVCONTROLMAXPAYLOAD_v6pcie14 : std_logic_vector(2 downto 0);
signal CFGDEVCONTROLMAXREADREQ_v6pcie15 : std_logic_vector(2 downto 0);
signal CFGDEVCONTROLNONFATALREPORTINGEN_v6pcie16 : std_logic;
signal CFGDEVCONTROLNOSNOOPEN_v6pcie17 : std_logic;
signal CFGDEVCONTROLPHANTOMEN_v6pcie18 : std_logic;
signal CFGDEVCONTROLURERRREPORTINGEN_v6pcie19 : std_logic;
signal CFGDEVCONTROL2CPLTIMEOUTDIS_v6pcie7 : std_logic;
signal CFGDEVCONTROL2CPLTIMEOUTVAL_v6pcie8 : std_logic_vector(3 downto 0);
signal CFGDEVSTATUSCORRERRDETECTED_v6pcie20 : std_logic;
signal CFGDEVSTATUSFATALERRDETECTED_v6pcie21 : std_logic;
signal CFGDEVSTATUSNONFATALERRDETECTED_v6pcie22 : std_logic;
signal CFGDEVSTATUSURDETECTED_v6pcie23 : std_logic;
signal CFGDO_v6pcie24 : std_logic_vector(31 downto 0);
signal CFGERRAERHEADERLOGSETN_v6pcie25 : std_logic;
signal CFGERRCPLRDYN_v6pcie26 : std_logic;
signal CFGINTERRUPTDO_v6pcie27 : std_logic_vector(7 downto 0);
signal CFGINTERRUPTMMENABLE_v6pcie28 : std_logic_vector(2 downto 0);
signal CFGINTERRUPTMSIENABLE_v6pcie29 : std_logic;
signal CFGINTERRUPTMSIXENABLE_v6pcie30 : std_logic;
signal CFGINTERRUPTMSIXFM_v6pcie31 : std_logic;
signal CFGINTERRUPTRDYN_v6pcie32 : std_logic;
signal CFGLINKCONTROLRCB_v6pcie41 : std_logic;
signal CFGLINKCONTROLASPMCONTROL_v6pcie33 : std_logic_vector(1 downto 0);
signal CFGLINKCONTROLAUTOBANDWIDTHINTEN_v6pcie34 : std_logic;
signal CFGLINKCONTROLBANDWIDTHINTEN_v6pcie35 : std_logic;
signal CFGLINKCONTROLCLOCKPMEN_v6pcie36 : std_logic;
signal CFGLINKCONTROLCOMMONCLOCK_v6pcie37 : std_logic;
signal CFGLINKCONTROLEXTENDEDSYNC_v6pcie38 : std_logic;
signal CFGLINKCONTROLHWAUTOWIDTHDIS_v6pcie39 : std_logic;
signal CFGLINKCONTROLLINKDISABLE_v6pcie40 : std_logic;
signal CFGLINKCONTROLRETRAINLINK_v6pcie42 : std_logic;
signal CFGLINKSTATUSAUTOBANDWIDTHSTATUS_v6pcie43 : std_logic;
signal CFGLINKSTATUSBANDWITHSTATUS_v6pcie44 : std_logic;
signal CFGLINKSTATUSCURRENTSPEED_v6pcie45 : std_logic_vector(1 downto 0);
signal CFGLINKSTATUSDLLACTIVE_v6pcie46 : std_logic;
signal CFGLINKSTATUSLINKTRAINING_v6pcie47 : std_logic;
signal CFGLINKSTATUSNEGOTIATEDWIDTH_v6pcie48 : std_logic_vector(3 downto 0);
signal CFGMSGDATA_v6pcie49 : std_logic_vector(15 downto 0);
signal CFGMSGRECEIVED_v6pcie50 : std_logic;
signal CFGMSGRECEIVEDASSERTINTA_v6pcie51 : std_logic;
signal CFGMSGRECEIVEDASSERTINTB_v6pcie52 : std_logic;
signal CFGMSGRECEIVEDASSERTINTC_v6pcie53 : std_logic;
signal CFGMSGRECEIVEDASSERTINTD_v6pcie54 : std_logic;
signal CFGMSGRECEIVEDDEASSERTINTA_v6pcie55 : std_logic;
signal CFGMSGRECEIVEDDEASSERTINTB_v6pcie56 : std_logic;
signal CFGMSGRECEIVEDDEASSERTINTC_v6pcie57 : std_logic;
signal CFGMSGRECEIVEDDEASSERTINTD_v6pcie58 : std_logic;
signal CFGMSGRECEIVEDERRCOR_v6pcie59 : std_logic;
signal CFGMSGRECEIVEDERRFATAL_v6pcie60 : std_logic;
signal CFGMSGRECEIVEDERRNONFATAL_v6pcie61 : std_logic;
signal CFGMSGRECEIVEDPMASNAK_v6pcie62 : std_logic;
signal CFGMSGRECEIVEDPMETO_v6pcie63 : std_logic;
signal CFGMSGRECEIVEDPMETOACK_v6pcie64 : std_logic;
signal CFGMSGRECEIVEDPMPME_v6pcie65 : std_logic;
signal CFGMSGRECEIVEDSETSLOTPOWERLIMIT_v6pcie66 : std_logic;
signal CFGMSGRECEIVEDUNLOCK_v6pcie67 : std_logic;
signal CFGPCIELINKSTATE_v6pcie68 : std_logic_vector(2 downto 0);
signal CFGPMCSRPMEEN_v6pcie69 : std_logic;
signal CFGPMCSRPMESTATUS_v6pcie70 : std_logic;
signal CFGPMCSRPOWERSTATE_v6pcie71 : std_logic_vector(1 downto 0);
signal CFGPMRCVASREQL1N_v6pcie72 : std_logic;
signal CFGPMRCVENTERL1N_v6pcie73 : std_logic;
signal CFGPMRCVENTERL23N_v6pcie74 : std_logic;
signal CFGPMRCVREQACKN_v6pcie75 : std_logic;
signal CFGRDWRDONEN_v6pcie76 : std_logic;
signal CFGSLOTCONTROLELECTROMECHILCTLPULSE_v6pcie77 : std_logic;
signal CFGTRANSACTION_v6pcie78 : std_logic;
signal CFGTRANSACTIONADDR_v6pcie79 : std_logic_vector(6 downto 0);
signal CFGTRANSACTIONTYPE_v6pcie80 : std_logic;
signal CFGVCTCVCMAP_v6pcie81 : std_logic_vector(6 downto 0);
signal PLINITIALLINKWIDTH_v6pcie104 : std_logic_vector(2 downto 0);
signal PLLANEREVERSALMODE_v6pcie105 : std_logic_vector(1 downto 0);
signal PLLINKGEN2CAP_v6pcie106 : std_logic;
signal PLLINKPARTNERGEN2SUPPORTED_v6pcie107 : std_logic;
signal PLLINKUPCFGCAP_v6pcie108 : std_logic;
signal PLLTSSMSTATE_v6pcie109 : std_logic_vector(5 downto 0);
signal PLPHYLNKUPN_v6pcie110 : std_logic;
signal PLRECEIVEDHOTRST_v6pcie111 : std_logic;
signal PLRXPMSTATE_v6pcie112 : std_logic_vector(1 downto 0);
signal PLSELLNKRATE_v6pcie113 : std_logic;
signal PLSELLNKWIDTH_v6pcie114 : std_logic_vector(1 downto 0);
signal PLTXPMSTATE_v6pcie115 : std_logic_vector(2 downto 0);
signal DBGSCLRA_v6pcie82 : std_logic;
signal DBGSCLRB_v6pcie83 : std_logic;
signal DBGSCLRC_v6pcie84 : std_logic;
signal DBGSCLRD_v6pcie85 : std_logic;
signal DBGSCLRE_v6pcie86 : std_logic;
signal DBGSCLRF_v6pcie87 : std_logic;
signal DBGSCLRG_v6pcie88 : std_logic;
signal DBGSCLRH_v6pcie89 : std_logic;
signal DBGSCLRI_v6pcie90 : std_logic;
signal DBGSCLRJ_v6pcie91 : std_logic;
signal DBGSCLRK_v6pcie92 : std_logic;
signal DBGVECA_v6pcie93 : std_logic_vector(63 downto 0);
signal DBGVECB_v6pcie94 : std_logic_vector(63 downto 0);
signal DBGVECC_v6pcie95 : std_logic_vector(11 downto 0);
signal PLDBGVEC_v6pcie103 : std_logic_vector(11 downto 0);
signal PCIEDRPDO_v6pcie98 : std_logic_vector(15 downto 0);
signal PCIEDRPDRDY_v6pcie99 : std_logic;
signal GTPLLLOCK_v6pcie96 : std_logic;
signal TxOutClk_v6pcie138 : std_logic;
signal PIPERX0CHARISK_v6pcie : std_logic_vector(1 downto 0);
signal PIPERX1CHARISK_v6pcie : std_logic_vector(1 downto 0);
signal PIPERX2CHARISK_v6pcie : std_logic_vector(1 downto 0);
signal PIPERX3CHARISK_v6pcie : std_logic_vector(1 downto 0);
signal PIPERX4CHARISK_v6pcie : std_logic_vector(1 downto 0);
signal PIPERX5CHARISK_v6pcie : std_logic_vector(1 downto 0);
signal PIPERX6CHARISK_v6pcie : std_logic_vector(1 downto 0);
signal PIPERX7CHARISK_v6pcie : std_logic_vector(1 downto 0);
begin
-- Drive referenced outputs
PCIEXPTXN <= PCIEXPTXN_v6pcie100;
PCIEXPTXP <= PCIEXPTXP_v6pcie101;
TRNLNKUPN <= TRNLNKUPN_v6pcie123;
PHYRDYN <= PHYRDYN_v6pcie102;
USERRSTN <= USERRSTN_v6pcie139;
RECEIVEDFUNCLVLRSTN <= RECEIVEDFUNCLVLRSTN_v6pcie116;
LNKCLKEN <= LNKCLKEN_v6pcie97;
TRNRBARHITN <= TRNRBARHITN_v6pcie124;
TRNRD <= TRNRD_v6pcie125;
TRNRECRCERRN <= TRNRECRCERRN_v6pcie126;
TRNREOFN <= TRNREOFN_v6pcie127;
TRNRERRFWDN <= TRNRERRFWDN_v6pcie128;
TRNRREMN <= TRNRREMN_v6pcie129;
TRNRSOFN <= TRNRSOFN_v6pcie130;
TRNRSRCDSCN <= TRNRSRCDSCN_v6pcie131;
TRNRSRCRDYN <= TRNRSRCRDYN_v6pcie132;
TRNTBUFAV <= TRNTBUFAV_v6pcie133;
TRNTCFGREQN <= TRNTCFGREQN_v6pcie134;
TRNTDLLPDSTRDYN <= TRNTDLLPDSTRDYN_v6pcie135;
TRNTDSTRDYN <= TRNTDSTRDYN_v6pcie136;
TRNTERRDROPN <= TRNTERRDROPN_v6pcie137;
TRNFCCPLD <= TRNFCCPLD_v6pcie117;
TRNFCCPLH <= TRNFCCPLH_v6pcie118;
TRNFCNPD <= TRNFCNPD_v6pcie119;
TRNFCNPH <= TRNFCNPH_v6pcie120;
TRNFCPD <= TRNFCPD_v6pcie121;
TRNFCPH <= TRNFCPH_v6pcie122;
CFGAERECRCCHECKEN <= CFGAERECRCCHECKEN_v6pcie0;
CFGAERECRCGENEN <= CFGAERECRCGENEN_v6pcie1;
CFGCOMMANDBUSMASTERENABLE <= CFGCOMMANDBUSMASTERENABLE_v6pcie2;
CFGCOMMANDINTERRUPTDISABLE <= CFGCOMMANDINTERRUPTDISABLE_v6pcie3;
CFGCOMMANDIOENABLE <= CFGCOMMANDIOENABLE_v6pcie4;
CFGCOMMANDMEMENABLE <= CFGCOMMANDMEMENABLE_v6pcie5;
CFGCOMMANDSERREN <= CFGCOMMANDSERREN_v6pcie6;
CFGDEVCONTROLAUXPOWEREN <= CFGDEVCONTROLAUXPOWEREN_v6pcie9;
CFGDEVCONTROLCORRERRREPORTINGEN <= CFGDEVCONTROLCORRERRREPORTINGEN_v6pcie10;
CFGDEVCONTROLENABLERO <= CFGDEVCONTROLENABLERO_v6pcie11;
CFGDEVCONTROLEXTTAGEN <= CFGDEVCONTROLEXTTAGEN_v6pcie12;
CFGDEVCONTROLFATALERRREPORTINGEN <= CFGDEVCONTROLFATALERRREPORTINGEN_v6pcie13;
CFGDEVCONTROLMAXPAYLOAD <= CFGDEVCONTROLMAXPAYLOAD_v6pcie14;
CFGDEVCONTROLMAXREADREQ <= CFGDEVCONTROLMAXREADREQ_v6pcie15;
CFGDEVCONTROLNONFATALREPORTINGEN <= CFGDEVCONTROLNONFATALREPORTINGEN_v6pcie16;
CFGDEVCONTROLNOSNOOPEN <= CFGDEVCONTROLNOSNOOPEN_v6pcie17;
CFGDEVCONTROLPHANTOMEN <= CFGDEVCONTROLPHANTOMEN_v6pcie18;
CFGDEVCONTROLURERRREPORTINGEN <= CFGDEVCONTROLURERRREPORTINGEN_v6pcie19;
CFGDEVCONTROL2CPLTIMEOUTDIS <= CFGDEVCONTROL2CPLTIMEOUTDIS_v6pcie7;
CFGDEVCONTROL2CPLTIMEOUTVAL <= CFGDEVCONTROL2CPLTIMEOUTVAL_v6pcie8;
CFGDEVSTATUSCORRERRDETECTED <= CFGDEVSTATUSCORRERRDETECTED_v6pcie20;
CFGDEVSTATUSFATALERRDETECTED <= CFGDEVSTATUSFATALERRDETECTED_v6pcie21;
CFGDEVSTATUSNONFATALERRDETECTED <= CFGDEVSTATUSNONFATALERRDETECTED_v6pcie22;
CFGDEVSTATUSURDETECTED <= CFGDEVSTATUSURDETECTED_v6pcie23;
CFGDO <= CFGDO_v6pcie24;
CFGERRAERHEADERLOGSETN <= CFGERRAERHEADERLOGSETN_v6pcie25;
CFGERRCPLRDYN <= CFGERRCPLRDYN_v6pcie26;
CFGINTERRUPTDO <= CFGINTERRUPTDO_v6pcie27;
CFGINTERRUPTMMENABLE <= CFGINTERRUPTMMENABLE_v6pcie28;
CFGINTERRUPTMSIENABLE <= CFGINTERRUPTMSIENABLE_v6pcie29;
CFGINTERRUPTMSIXENABLE <= CFGINTERRUPTMSIXENABLE_v6pcie30;
CFGINTERRUPTMSIXFM <= CFGINTERRUPTMSIXFM_v6pcie31;
CFGINTERRUPTRDYN <= CFGINTERRUPTRDYN_v6pcie32;
CFGLINKCONTROLRCB <= CFGLINKCONTROLRCB_v6pcie41;
CFGLINKCONTROLASPMCONTROL <= CFGLINKCONTROLASPMCONTROL_v6pcie33;
CFGLINKCONTROLAUTOBANDWIDTHINTEN <= CFGLINKCONTROLAUTOBANDWIDTHINTEN_v6pcie34;
CFGLINKCONTROLBANDWIDTHINTEN <= CFGLINKCONTROLBANDWIDTHINTEN_v6pcie35;
CFGLINKCONTROLCLOCKPMEN <= CFGLINKCONTROLCLOCKPMEN_v6pcie36;
CFGLINKCONTROLCOMMONCLOCK <= CFGLINKCONTROLCOMMONCLOCK_v6pcie37;
CFGLINKCONTROLEXTENDEDSYNC <= CFGLINKCONTROLEXTENDEDSYNC_v6pcie38;
CFGLINKCONTROLHWAUTOWIDTHDIS <= CFGLINKCONTROLHWAUTOWIDTHDIS_v6pcie39;
CFGLINKCONTROLLINKDISABLE <= CFGLINKCONTROLLINKDISABLE_v6pcie40;
CFGLINKCONTROLRETRAINLINK <= CFGLINKCONTROLRETRAINLINK_v6pcie42;
CFGLINKSTATUSAUTOBANDWIDTHSTATUS <= CFGLINKSTATUSAUTOBANDWIDTHSTATUS_v6pcie43;
CFGLINKSTATUSBANDWITHSTATUS <= CFGLINKSTATUSBANDWITHSTATUS_v6pcie44;
CFGLINKSTATUSCURRENTSPEED <= CFGLINKSTATUSCURRENTSPEED_v6pcie45;
CFGLINKSTATUSDLLACTIVE <= CFGLINKSTATUSDLLACTIVE_v6pcie46;
CFGLINKSTATUSLINKTRAINING <= CFGLINKSTATUSLINKTRAINING_v6pcie47;
CFGLINKSTATUSNEGOTIATEDWIDTH <= CFGLINKSTATUSNEGOTIATEDWIDTH_v6pcie48;
CFGMSGDATA <= CFGMSGDATA_v6pcie49;
CFGMSGRECEIVED <= CFGMSGRECEIVED_v6pcie50;
CFGMSGRECEIVEDASSERTINTA <= CFGMSGRECEIVEDASSERTINTA_v6pcie51;
CFGMSGRECEIVEDASSERTINTB <= CFGMSGRECEIVEDASSERTINTB_v6pcie52;
CFGMSGRECEIVEDASSERTINTC <= CFGMSGRECEIVEDASSERTINTC_v6pcie53;
CFGMSGRECEIVEDASSERTINTD <= CFGMSGRECEIVEDASSERTINTD_v6pcie54;
CFGMSGRECEIVEDDEASSERTINTA <= CFGMSGRECEIVEDDEASSERTINTA_v6pcie55;
CFGMSGRECEIVEDDEASSERTINTB <= CFGMSGRECEIVEDDEASSERTINTB_v6pcie56;
CFGMSGRECEIVEDDEASSERTINTC <= CFGMSGRECEIVEDDEASSERTINTC_v6pcie57;
CFGMSGRECEIVEDDEASSERTINTD <= CFGMSGRECEIVEDDEASSERTINTD_v6pcie58;
CFGMSGRECEIVEDERRCOR <= CFGMSGRECEIVEDERRCOR_v6pcie59;
CFGMSGRECEIVEDERRFATAL <= CFGMSGRECEIVEDERRFATAL_v6pcie60;
CFGMSGRECEIVEDERRNONFATAL <= CFGMSGRECEIVEDERRNONFATAL_v6pcie61;
CFGMSGRECEIVEDPMASNAK <= CFGMSGRECEIVEDPMASNAK_v6pcie62;
CFGMSGRECEIVEDPMETO <= CFGMSGRECEIVEDPMETO_v6pcie63;
CFGMSGRECEIVEDPMETOACK <= CFGMSGRECEIVEDPMETOACK_v6pcie64;
CFGMSGRECEIVEDPMPME <= CFGMSGRECEIVEDPMPME_v6pcie65;
CFGMSGRECEIVEDSETSLOTPOWERLIMIT <= CFGMSGRECEIVEDSETSLOTPOWERLIMIT_v6pcie66;
CFGMSGRECEIVEDUNLOCK <= CFGMSGRECEIVEDUNLOCK_v6pcie67;
CFGPCIELINKSTATE <= CFGPCIELINKSTATE_v6pcie68;
CFGPMCSRPMEEN <= CFGPMCSRPMEEN_v6pcie69;
CFGPMCSRPMESTATUS <= CFGPMCSRPMESTATUS_v6pcie70;
CFGPMCSRPOWERSTATE <= CFGPMCSRPOWERSTATE_v6pcie71;
CFGPMRCVASREQL1N <= CFGPMRCVASREQL1N_v6pcie72;
CFGPMRCVENTERL1N <= CFGPMRCVENTERL1N_v6pcie73;
CFGPMRCVENTERL23N <= CFGPMRCVENTERL23N_v6pcie74;
CFGPMRCVREQACKN <= CFGPMRCVREQACKN_v6pcie75;
CFGRDWRDONEN <= CFGRDWRDONEN_v6pcie76;
CFGSLOTCONTROLELECTROMECHILCTLPULSE <= CFGSLOTCONTROLELECTROMECHILCTLPULSE_v6pcie77;
CFGTRANSACTION <= CFGTRANSACTION_v6pcie78;
CFGTRANSACTIONADDR <= CFGTRANSACTIONADDR_v6pcie79;
CFGTRANSACTIONTYPE <= CFGTRANSACTIONTYPE_v6pcie80;
CFGVCTCVCMAP <= CFGVCTCVCMAP_v6pcie81;
PLINITIALLINKWIDTH <= PLINITIALLINKWIDTH_v6pcie104;
PLLANEREVERSALMODE <= PLLANEREVERSALMODE_v6pcie105;
PLLINKGEN2CAP <= PLLINKGEN2CAP_v6pcie106;
PLLINKPARTNERGEN2SUPPORTED <= PLLINKPARTNERGEN2SUPPORTED_v6pcie107;
PLLINKUPCFGCAP <= PLLINKUPCFGCAP_v6pcie108;
PLLTSSMSTATE <= PLLTSSMSTATE_v6pcie109;
PLPHYLNKUPN <= PLPHYLNKUPN_v6pcie110;
PLRECEIVEDHOTRST <= PLRECEIVEDHOTRST_v6pcie111;
PLRXPMSTATE <= PLRXPMSTATE_v6pcie112;
PLSELLNKRATE <= PLSELLNKRATE_v6pcie113;
PLSELLNKWIDTH <= PLSELLNKWIDTH_v6pcie114;
PLTXPMSTATE <= PLTXPMSTATE_v6pcie115;
DBGSCLRA <= DBGSCLRA_v6pcie82;
DBGSCLRB <= DBGSCLRB_v6pcie83;
DBGSCLRC <= DBGSCLRC_v6pcie84;
DBGSCLRD <= DBGSCLRD_v6pcie85;
DBGSCLRE <= DBGSCLRE_v6pcie86;
DBGSCLRF <= DBGSCLRF_v6pcie87;
DBGSCLRG <= DBGSCLRG_v6pcie88;
DBGSCLRH <= DBGSCLRH_v6pcie89;
DBGSCLRI <= DBGSCLRI_v6pcie90;
DBGSCLRJ <= DBGSCLRJ_v6pcie91;
DBGSCLRK <= DBGSCLRK_v6pcie92;
DBGVECA <= DBGVECA_v6pcie93;
DBGVECB <= DBGVECB_v6pcie94;
DBGVECC <= DBGVECC_v6pcie95;
PLDBGVEC <= PLDBGVEC_v6pcie103;
PCIEDRPDO <= PCIEDRPDO_v6pcie98;
PCIEDRPDRDY <= PCIEDRPDRDY_v6pcie99;
GTPLLLOCK <= GTPLLLOCK_v6pcie96;
TxOutClk <= TxOutClk_v6pcie138;
LL2SENDASREQL1N <= '1';
LL2SENDENTERL1N <= '1';
LL2SENDENTERL23N <= '1';
LL2SUSPENDNOWN <= '1';
LL2TLPRCVN <= '1';
PL2DIRECTEDLSTATE <= "00000";
-- Assignments to outputs
TRNCLK <= USERCLK;
PIPERX0CHARISK_v6pcie <= "11" when (filter_pipe_upconfig_fix_3451 = '1') else
PIPERX0CHARISK;
PIPERX1CHARISK_v6pcie <= "11" when (filter_pipe_upconfig_fix_3451 = '1') else
PIPERX1CHARISK;
PIPERX2CHARISK_v6pcie <= "11" when (filter_pipe_upconfig_fix_3451 = '1') else
PIPERX2CHARISK;
PIPERX3CHARISK_v6pcie <= "11" when (filter_pipe_upconfig_fix_3451 = '1') else
PIPERX3CHARISK;
PIPERX4CHARISK_v6pcie <= "11" when (filter_pipe_upconfig_fix_3451 = '1') else
PIPERX4CHARISK;
PIPERX5CHARISK_v6pcie <= "11" when (filter_pipe_upconfig_fix_3451 = '1') else
PIPERX5CHARISK;
PIPERX6CHARISK_v6pcie <= "11" when (filter_pipe_upconfig_fix_3451 = '1') else
PIPERX6CHARISK;
PIPERX7CHARISK_v6pcie <= "11" when (filter_pipe_upconfig_fix_3451 = '1') else
PIPERX7CHARISK;
---------------------------------------------------------
-- Virtex6 PCI Express Block Module
---------------------------------------------------------
pcie_block_i : PCIE_2_0
generic map (
AER_BASE_PTR => AER_BASE_PTR,
AER_CAP_ECRC_CHECK_CAPABLE => AER_CAP_ECRC_CHECK_CAPABLE,
AER_CAP_ECRC_GEN_CAPABLE => AER_CAP_ECRC_GEN_CAPABLE,
AER_CAP_ID => AER_CAP_ID,
AER_CAP_INT_MSG_NUM_MSI => AER_CAP_INT_MSG_NUM_MSI,
AER_CAP_INT_MSG_NUM_MSIX => AER_CAP_INT_MSG_NUM_MSIX,
AER_CAP_NEXTPTR => AER_CAP_NEXTPTR,
AER_CAP_ON => AER_CAP_ON,
AER_CAP_PERMIT_ROOTERR_UPDATE => AER_CAP_PERMIT_ROOTERR_UPDATE,
AER_CAP_VERSION => AER_CAP_VERSION,
ALLOW_X8_GEN2 => ALLOW_X8_GEN2,
BAR0 => BAR0,
BAR1 => BAR1,
BAR2 => BAR2,
BAR3 => BAR3,
BAR4 => BAR4,
BAR5 => BAR5,
CAPABILITIES_PTR => CAPABILITIES_PTR,
CARDBUS_CIS_POINTER => CARDBUS_CIS_POINTER,
CLASS_CODE => CLASS_CODE,
CMD_INTX_IMPLEMENTED => CMD_INTX_IMPLEMENTED,
CPL_TIMEOUT_DISABLE_SUPPORTED => CPL_TIMEOUT_DISABLE_SUPPORTED,
CPL_TIMEOUT_RANGES_SUPPORTED => CPL_TIMEOUT_RANGES_SUPPORTED,
CRM_MODULE_RSTS => CRM_MODULE_RSTS,
DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE => DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE,
DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE => DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE,
DEV_CAP_ENDPOINT_L0S_LATENCY => DEV_CAP_ENDPOINT_L0S_LATENCY,
DEV_CAP_ENDPOINT_L1_LATENCY => DEV_CAP_ENDPOINT_L1_LATENCY,
DEV_CAP_EXT_TAG_SUPPORTED => DEV_CAP_EXT_TAG_SUPPORTED,
DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE => DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE,
DEV_CAP_MAX_PAYLOAD_SUPPORTED => DEV_CAP_MAX_PAYLOAD_SUPPORTED,
DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT => DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT,
DEV_CAP_ROLE_BASED_ERROR => DEV_CAP_ROLE_BASED_ERROR,
DEV_CAP_RSVD_14_12 => DEV_CAP_RSVD_14_12,
DEV_CAP_RSVD_17_16 => DEV_CAP_RSVD_17_16,
DEV_CAP_RSVD_31_29 => DEV_CAP_RSVD_31_29,
DEV_CONTROL_AUX_POWER_SUPPORTED => DEV_CONTROL_AUX_POWER_SUPPORTED,
DEVICE_ID => DEVICE_ID,
DISABLE_ASPM_L1_TIMER => DISABLE_ASPM_L1_TIMER,
DISABLE_BAR_FILTERING => DISABLE_BAR_FILTERING,
DISABLE_ID_CHECK => DISABLE_ID_CHECK,
DISABLE_LANE_REVERSAL => DISABLE_LANE_REVERSAL,
DISABLE_RX_TC_FILTER => DISABLE_RX_TC_FILTER,
DISABLE_SCRAMBLING => DISABLE_SCRAMBLING,
DNSTREAM_LINK_NUM => DNSTREAM_LINK_NUM,
DSN_BASE_PTR => DSN_BASE_PTR,
DSN_CAP_ID => DSN_CAP_ID,
DSN_CAP_NEXTPTR => DSN_CAP_NEXTPTR,
DSN_CAP_ON => DSN_CAP_ON,
DSN_CAP_VERSION => DSN_CAP_VERSION,
ENABLE_MSG_ROUTE => ENABLE_MSG_ROUTE,
ENABLE_RX_TD_ECRC_TRIM => ENABLE_RX_TD_ECRC_TRIM,
ENTER_RVRY_EI_L0 => ENTER_RVRY_EI_L0,
EXPANSION_ROM => EXPANSION_ROM,
EXT_CFG_CAP_PTR => EXT_CFG_CAP_PTR,
EXT_CFG_XP_CAP_PTR => EXT_CFG_XP_CAP_PTR,
HEADER_TYPE => HEADER_TYPE,
INFER_EI => INFER_EI,
INTERRUPT_PIN => INTERRUPT_PIN,
IS_SWITCH => IS_SWITCH,
LAST_CONFIG_DWORD => LAST_CONFIG_DWORD,
LINK_CAP_ASPM_SUPPORT => LINK_CAP_ASPM_SUPPORT,
LINK_CAP_CLOCK_POWER_MANAGEMENT => LINK_CAP_CLOCK_POWER_MANAGEMENT,
LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP => LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP,
LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP => LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP,
LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 => LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1,
LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 => LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2,
LINK_CAP_L0S_EXIT_LATENCY_GEN1 => LINK_CAP_L0S_EXIT_LATENCY_GEN1,
LINK_CAP_L0S_EXIT_LATENCY_GEN2 => LINK_CAP_L0S_EXIT_LATENCY_GEN2,
LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 => LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1,
LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 => LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2,
LINK_CAP_L1_EXIT_LATENCY_GEN1 => LINK_CAP_L1_EXIT_LATENCY_GEN1,
LINK_CAP_L1_EXIT_LATENCY_GEN2 => LINK_CAP_L1_EXIT_LATENCY_GEN2,
LINK_CAP_MAX_LINK_SPEED => LINK_CAP_MAX_LINK_SPEED,
LINK_CAP_MAX_LINK_WIDTH => LINK_CAP_MAX_LINK_WIDTH,
LINK_CAP_RSVD_23_22 => LINK_CAP_RSVD_23_22,
LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE => LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE,
LINK_CONTROL_RCB => LINK_CONTROL_RCB,
LINK_CTRL2_DEEMPHASIS => LINK_CTRL2_DEEMPHASIS,
LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE => LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE,
LINK_CTRL2_TARGET_LINK_SPEED => LINK_CTRL2_TARGET_LINK_SPEED,
LINK_STATUS_SLOT_CLOCK_CONFIG => LINK_STATUS_SLOT_CLOCK_CONFIG,
LL_ACK_TIMEOUT => LL_ACK_TIMEOUT,
LL_ACK_TIMEOUT_EN => LL_ACK_TIMEOUT_EN,
LL_ACK_TIMEOUT_FUNC => LL_ACK_TIMEOUT_FUNC,
LL_REPLAY_TIMEOUT => LL_REPLAY_TIMEOUT,
LL_REPLAY_TIMEOUT_EN => LL_REPLAY_TIMEOUT_EN,
LL_REPLAY_TIMEOUT_FUNC => LL_REPLAY_TIMEOUT_FUNC,
LTSSM_MAX_LINK_WIDTH => LTSSM_MAX_LINK_WIDTH,
MSI_BASE_PTR => MSI_BASE_PTR,
MSI_CAP_ID => MSI_CAP_ID,
MSI_CAP_MULTIMSGCAP => MSI_CAP_MULTIMSGCAP,
MSI_CAP_MULTIMSG_EXTENSION => MSI_CAP_MULTIMSG_EXTENSION,
MSI_CAP_NEXTPTR => MSI_CAP_NEXTPTR,
MSI_CAP_ON => MSI_CAP_ON,
MSI_CAP_PER_VECTOR_MASKING_CAPABLE => MSI_CAP_PER_VECTOR_MASKING_CAPABLE,
MSI_CAP_64_BIT_ADDR_CAPABLE => MSI_CAP_64_BIT_ADDR_CAPABLE,
MSIX_BASE_PTR => MSIX_BASE_PTR,
MSIX_CAP_ID => MSIX_CAP_ID,
MSIX_CAP_NEXTPTR => MSIX_CAP_NEXTPTR,
MSIX_CAP_ON => MSIX_CAP_ON,
MSIX_CAP_PBA_BIR => MSIX_CAP_PBA_BIR,
MSIX_CAP_PBA_OFFSET => MSIX_CAP_PBA_OFFSET,
MSIX_CAP_TABLE_BIR => MSIX_CAP_TABLE_BIR,
MSIX_CAP_TABLE_OFFSET => MSIX_CAP_TABLE_OFFSET,
MSIX_CAP_TABLE_SIZE => MSIX_CAP_TABLE_SIZE,
N_FTS_COMCLK_GEN1 => N_FTS_COMCLK_GEN1,
N_FTS_COMCLK_GEN2 => N_FTS_COMCLK_GEN2,
N_FTS_GEN1 => N_FTS_GEN1,
N_FTS_GEN2 => N_FTS_GEN2,
PCIE_BASE_PTR => PCIE_BASE_PTR,
PCIE_CAP_CAPABILITY_ID => PCIE_CAP_CAPABILITY_ID,
PCIE_CAP_CAPABILITY_VERSION => PCIE_CAP_CAPABILITY_VERSION,
PCIE_CAP_DEVICE_PORT_TYPE => PCIE_CAP_DEVICE_PORT_TYPE,
PCIE_CAP_INT_MSG_NUM => PCIE_CAP_INT_MSG_NUM,
PCIE_CAP_NEXTPTR => PCIE_CAP_NEXTPTR,
PCIE_CAP_ON => PCIE_CAP_ON,
PCIE_CAP_RSVD_15_14 => PCIE_CAP_RSVD_15_14,
PCIE_CAP_SLOT_IMPLEMENTED => PCIE_CAP_SLOT_IMPLEMENTED,
PCIE_REVISION => PCIE_REVISION,
PGL0_LANE => PGL0_LANE,
PGL1_LANE => PGL1_LANE,
PGL2_LANE => PGL2_LANE,
PGL3_LANE => PGL3_LANE,
PGL4_LANE => PGL4_LANE,
PGL5_LANE => PGL5_LANE,
PGL6_LANE => PGL6_LANE,
PGL7_LANE => PGL7_LANE,
PL_AUTO_CONFIG => PL_AUTO_CONFIG,
PL_FAST_TRAIN => PL_FAST_TRAIN,
PM_BASE_PTR => PM_BASE_PTR,
PM_CAP_AUXCURRENT => PM_CAP_AUXCURRENT,
PM_CAP_DSI => PM_CAP_DSI,
PM_CAP_D1SUPPORT => PM_CAP_D1SUPPORT,
PM_CAP_D2SUPPORT => PM_CAP_D2SUPPORT,
PM_CAP_ID => PM_CAP_ID,
PM_CAP_NEXTPTR => PM_CAP_NEXTPTR,
PM_CAP_ON => PM_CAP_ON,
PM_CAP_PME_CLOCK => PM_CAP_PME_CLOCK,
PM_CAP_PMESUPPORT => PM_CAP_PMESUPPORT,
PM_CAP_RSVD_04 => PM_CAP_RSVD_04,
PM_CAP_VERSION => PM_CAP_VERSION,
PM_CSR_BPCCEN => PM_CSR_BPCCEN,
PM_CSR_B2B3 => PM_CSR_B2B3,
PM_CSR_NOSOFTRST => PM_CSR_NOSOFTRST,
PM_DATA_SCALE0 => PM_DATA_SCALE0,
PM_DATA_SCALE1 => PM_DATA_SCALE1,
PM_DATA_SCALE2 => PM_DATA_SCALE2,
PM_DATA_SCALE3 => PM_DATA_SCALE3,
PM_DATA_SCALE4 => PM_DATA_SCALE4,
PM_DATA_SCALE5 => PM_DATA_SCALE5,
PM_DATA_SCALE6 => PM_DATA_SCALE6,
PM_DATA_SCALE7 => PM_DATA_SCALE7,
PM_DATA0 => PM_DATA0,
PM_DATA1 => PM_DATA1,
PM_DATA2 => PM_DATA2,
PM_DATA3 => PM_DATA3,
PM_DATA4 => PM_DATA4,
PM_DATA5 => PM_DATA5,
PM_DATA6 => PM_DATA6,
PM_DATA7 => PM_DATA7,
RECRC_CHK => RECRC_CHK,
RECRC_CHK_TRIM => RECRC_CHK_TRIM,
REVISION_ID => REVISION_ID,
ROOT_CAP_CRS_SW_VISIBILITY => ROOT_CAP_CRS_SW_VISIBILITY,
SELECT_DLL_IF => SELECT_DLL_IF,
SLOT_CAP_ATT_BUTTON_PRESENT => SLOT_CAP_ATT_BUTTON_PRESENT,
SLOT_CAP_ATT_INDICATOR_PRESENT => SLOT_CAP_ATT_INDICATOR_PRESENT,
SLOT_CAP_ELEC_INTERLOCK_PRESENT => SLOT_CAP_ELEC_INTERLOCK_PRESENT,
SLOT_CAP_HOTPLUG_CAPABLE => SLOT_CAP_HOTPLUG_CAPABLE,
SLOT_CAP_HOTPLUG_SURPRISE => SLOT_CAP_HOTPLUG_SURPRISE,
SLOT_CAP_MRL_SENSOR_PRESENT => SLOT_CAP_MRL_SENSOR_PRESENT,
SLOT_CAP_NO_CMD_COMPLETED_SUPPORT => SLOT_CAP_NO_CMD_COMPLETED_SUPPORT,
SLOT_CAP_PHYSICAL_SLOT_NUM => SLOT_CAP_PHYSICAL_SLOT_NUM,
SLOT_CAP_POWER_CONTROLLER_PRESENT => SLOT_CAP_POWER_CONTROLLER_PRESENT,
SLOT_CAP_POWER_INDICATOR_PRESENT => SLOT_CAP_POWER_INDICATOR_PRESENT,
SLOT_CAP_SLOT_POWER_LIMIT_SCALE => SLOT_CAP_SLOT_POWER_LIMIT_SCALE,
SLOT_CAP_SLOT_POWER_LIMIT_VALUE => SLOT_CAP_SLOT_POWER_LIMIT_VALUE,
SPARE_BIT0 => SPARE_BIT0,
SPARE_BIT1 => SPARE_BIT1,
SPARE_BIT2 => SPARE_BIT2,
SPARE_BIT3 => SPARE_BIT3,
SPARE_BIT4 => SPARE_BIT4,
SPARE_BIT5 => SPARE_BIT5,
SPARE_BIT6 => SPARE_BIT6,
SPARE_BIT7 => SPARE_BIT7,
SPARE_BIT8 => SPARE_BIT8,
SPARE_BYTE0 => SPARE_BYTE0,
SPARE_BYTE1 => SPARE_BYTE1,
SPARE_BYTE2 => SPARE_BYTE2,
SPARE_BYTE3 => SPARE_BYTE3,
SPARE_WORD0 => SPARE_WORD0,
SPARE_WORD1 => SPARE_WORD1,
SPARE_WORD2 => SPARE_WORD2,
SPARE_WORD3 => SPARE_WORD3,
SUBSYSTEM_ID => SUBSYSTEM_ID,
SUBSYSTEM_VENDOR_ID => SUBSYSTEM_VENDOR_ID,
TL_RBYPASS => TL_RBYPASS,
TL_RX_RAM_RADDR_LATENCY => TL_RX_RAM_RADDR_LATENCY,
TL_RX_RAM_RDATA_LATENCY => TL_RX_RAM_RDATA_LATENCY,
TL_RX_RAM_WRITE_LATENCY => TL_RX_RAM_WRITE_LATENCY,
TL_TFC_DISABLE => TL_TFC_DISABLE,
TL_TX_CHECKS_DISABLE => TL_TX_CHECKS_DISABLE,
TL_TX_RAM_RADDR_LATENCY => TL_TX_RAM_RADDR_LATENCY,
TL_TX_RAM_RDATA_LATENCY => TL_TX_RAM_RDATA_LATENCY,
TL_TX_RAM_WRITE_LATENCY => TL_TX_RAM_WRITE_LATENCY,
UPCONFIG_CAPABLE => UPCONFIG_CAPABLE,
UPSTREAM_FACING => UPSTREAM_FACING,
EXIT_LOOPBACK_ON_EI => EXIT_LOOPBACK_ON_EI,
UR_INV_REQ => UR_INV_REQ,
USER_CLK_FREQ => USER_CLK_FREQ,
VC_BASE_PTR => VC_BASE_PTR,
VC_CAP_ID => VC_CAP_ID,
VC_CAP_NEXTPTR => VC_CAP_NEXTPTR,
VC_CAP_ON => VC_CAP_ON,
VC_CAP_REJECT_SNOOP_TRANSACTIONS => VC_CAP_REJECT_SNOOP_TRANSACTIONS,
VC_CAP_VERSION => VC_CAP_VERSION,
VC0_CPL_INFINITE => VC0_CPL_INFINITE,
VC0_RX_RAM_LIMIT => VC0_RX_RAM_LIMIT,
VC0_TOTAL_CREDITS_CD => VC0_TOTAL_CREDITS_CD,
VC0_TOTAL_CREDITS_CH => VC0_TOTAL_CREDITS_CH,
VC0_TOTAL_CREDITS_NPH => VC0_TOTAL_CREDITS_NPH,
VC0_TOTAL_CREDITS_PD => VC0_TOTAL_CREDITS_PD,
VC0_TOTAL_CREDITS_PH => VC0_TOTAL_CREDITS_PH,
VC0_TX_LASTPACKET => VC0_TX_LASTPACKET,
VENDOR_ID => VENDOR_ID,
VSEC_BASE_PTR => VSEC_BASE_PTR,
VSEC_CAP_HDR_ID => VSEC_CAP_HDR_ID,
VSEC_CAP_HDR_LENGTH => VSEC_CAP_HDR_LENGTH,
VSEC_CAP_HDR_REVISION => VSEC_CAP_HDR_REVISION,
VSEC_CAP_ID => VSEC_CAP_ID,
VSEC_CAP_IS_LINK_VISIBLE => VSEC_CAP_IS_LINK_VISIBLE,
VSEC_CAP_NEXTPTR => VSEC_CAP_NEXTPTR,
VSEC_CAP_ON => VSEC_CAP_ON,
VSEC_CAP_VERSION => VSEC_CAP_VERSION
)
port map (
CFGAERECRCCHECKEN => CFGAERECRCCHECKEN_v6pcie0,
CFGAERECRCGENEN => CFGAERECRCGENEN_v6pcie1,
CFGCOMMANDBUSMASTERENABLE => CFGCOMMANDBUSMASTERENABLE_v6pcie2,
CFGCOMMANDINTERRUPTDISABLE => CFGCOMMANDINTERRUPTDISABLE_v6pcie3,
CFGCOMMANDIOENABLE => CFGCOMMANDIOENABLE_v6pcie4,
CFGCOMMANDMEMENABLE => CFGCOMMANDMEMENABLE_v6pcie5,
CFGCOMMANDSERREN => CFGCOMMANDSERREN_v6pcie6,
CFGDEVCONTROLAUXPOWEREN => CFGDEVCONTROLAUXPOWEREN_v6pcie9,
CFGDEVCONTROLCORRERRREPORTINGEN => CFGDEVCONTROLCORRERRREPORTINGEN_v6pcie10,
CFGDEVCONTROLENABLERO => CFGDEVCONTROLENABLERO_v6pcie11,
CFGDEVCONTROLEXTTAGEN => CFGDEVCONTROLEXTTAGEN_v6pcie12,
CFGDEVCONTROLFATALERRREPORTINGEN => CFGDEVCONTROLFATALERRREPORTINGEN_v6pcie13,
CFGDEVCONTROLMAXPAYLOAD => CFGDEVCONTROLMAXPAYLOAD_v6pcie14,
CFGDEVCONTROLMAXREADREQ => CFGDEVCONTROLMAXREADREQ_v6pcie15,
CFGDEVCONTROLNONFATALREPORTINGEN => CFGDEVCONTROLNONFATALREPORTINGEN_v6pcie16,
CFGDEVCONTROLNOSNOOPEN => CFGDEVCONTROLNOSNOOPEN_v6pcie17,
CFGDEVCONTROLPHANTOMEN => CFGDEVCONTROLPHANTOMEN_v6pcie18,
CFGDEVCONTROLURERRREPORTINGEN => CFGDEVCONTROLURERRREPORTINGEN_v6pcie19,
CFGDEVCONTROL2CPLTIMEOUTDIS => CFGDEVCONTROL2CPLTIMEOUTDIS_v6pcie7,
CFGDEVCONTROL2CPLTIMEOUTVAL => CFGDEVCONTROL2CPLTIMEOUTVAL_v6pcie8,
CFGDEVSTATUSCORRERRDETECTED => CFGDEVSTATUSCORRERRDETECTED_v6pcie20,
CFGDEVSTATUSFATALERRDETECTED => CFGDEVSTATUSFATALERRDETECTED_v6pcie21,
CFGDEVSTATUSNONFATALERRDETECTED => CFGDEVSTATUSNONFATALERRDETECTED_v6pcie22,
CFGDEVSTATUSURDETECTED => CFGDEVSTATUSURDETECTED_v6pcie23,
CFGDO => CFGDO_v6pcie24,
CFGERRAERHEADERLOGSETN => CFGERRAERHEADERLOGSETN_v6pcie25,
CFGERRCPLRDYN => CFGERRCPLRDYN_v6pcie26,
CFGINTERRUPTDO => CFGINTERRUPTDO_v6pcie27,
CFGINTERRUPTMMENABLE => CFGINTERRUPTMMENABLE_v6pcie28,
CFGINTERRUPTMSIENABLE => CFGINTERRUPTMSIENABLE_v6pcie29,
CFGINTERRUPTMSIXENABLE => CFGINTERRUPTMSIXENABLE_v6pcie30,
CFGINTERRUPTMSIXFM => CFGINTERRUPTMSIXFM_v6pcie31,
CFGINTERRUPTRDYN => CFGINTERRUPTRDYN_v6pcie32,
CFGLINKCONTROLRCB => CFGLINKCONTROLRCB_v6pcie41,
CFGLINKCONTROLASPMCONTROL => CFGLINKCONTROLASPMCONTROL_v6pcie33,
CFGLINKCONTROLAUTOBANDWIDTHINTEN => CFGLINKCONTROLAUTOBANDWIDTHINTEN_v6pcie34,
CFGLINKCONTROLBANDWIDTHINTEN => CFGLINKCONTROLBANDWIDTHINTEN_v6pcie35,
CFGLINKCONTROLCLOCKPMEN => CFGLINKCONTROLCLOCKPMEN_v6pcie36,
CFGLINKCONTROLCOMMONCLOCK => CFGLINKCONTROLCOMMONCLOCK_v6pcie37,
CFGLINKCONTROLEXTENDEDSYNC => CFGLINKCONTROLEXTENDEDSYNC_v6pcie38,
CFGLINKCONTROLHWAUTOWIDTHDIS => CFGLINKCONTROLHWAUTOWIDTHDIS_v6pcie39,
CFGLINKCONTROLLINKDISABLE => CFGLINKCONTROLLINKDISABLE_v6pcie40,
CFGLINKCONTROLRETRAINLINK => CFGLINKCONTROLRETRAINLINK_v6pcie42,
CFGLINKSTATUSAUTOBANDWIDTHSTATUS => CFGLINKSTATUSAUTOBANDWIDTHSTATUS_v6pcie43,
CFGLINKSTATUSBANDWITHSTATUS => CFGLINKSTATUSBANDWITHSTATUS_v6pcie44,
CFGLINKSTATUSCURRENTSPEED => CFGLINKSTATUSCURRENTSPEED_v6pcie45,
CFGLINKSTATUSDLLACTIVE => CFGLINKSTATUSDLLACTIVE_v6pcie46,
CFGLINKSTATUSLINKTRAINING => CFGLINKSTATUSLINKTRAINING_v6pcie47,
CFGLINKSTATUSNEGOTIATEDWIDTH => CFGLINKSTATUSNEGOTIATEDWIDTH_v6pcie48,
CFGMSGDATA => CFGMSGDATA_v6pcie49,
CFGMSGRECEIVED => CFGMSGRECEIVED_v6pcie50,
CFGMSGRECEIVEDASSERTINTA => CFGMSGRECEIVEDASSERTINTA_v6pcie51,
CFGMSGRECEIVEDASSERTINTB => CFGMSGRECEIVEDASSERTINTB_v6pcie52,
CFGMSGRECEIVEDASSERTINTC => CFGMSGRECEIVEDASSERTINTC_v6pcie53,
CFGMSGRECEIVEDASSERTINTD => CFGMSGRECEIVEDASSERTINTD_v6pcie54,
CFGMSGRECEIVEDDEASSERTINTA => CFGMSGRECEIVEDDEASSERTINTA_v6pcie55,
CFGMSGRECEIVEDDEASSERTINTB => CFGMSGRECEIVEDDEASSERTINTB_v6pcie56,
CFGMSGRECEIVEDDEASSERTINTC => CFGMSGRECEIVEDDEASSERTINTC_v6pcie57,
CFGMSGRECEIVEDDEASSERTINTD => CFGMSGRECEIVEDDEASSERTINTD_v6pcie58,
CFGMSGRECEIVEDERRCOR => CFGMSGRECEIVEDERRCOR_v6pcie59,
CFGMSGRECEIVEDERRFATAL => CFGMSGRECEIVEDERRFATAL_v6pcie60,
CFGMSGRECEIVEDERRNONFATAL => CFGMSGRECEIVEDERRNONFATAL_v6pcie61,
CFGMSGRECEIVEDPMASNAK => CFGMSGRECEIVEDPMASNAK_v6pcie62,
CFGMSGRECEIVEDPMETO => CFGMSGRECEIVEDPMETO_v6pcie63,
CFGMSGRECEIVEDPMETOACK => CFGMSGRECEIVEDPMETOACK_v6pcie64,
CFGMSGRECEIVEDPMPME => CFGMSGRECEIVEDPMPME_v6pcie65,
CFGMSGRECEIVEDSETSLOTPOWERLIMIT => CFGMSGRECEIVEDSETSLOTPOWERLIMIT_v6pcie66,
CFGMSGRECEIVEDUNLOCK => CFGMSGRECEIVEDUNLOCK_v6pcie67,
CFGPCIELINKSTATE => CFGPCIELINKSTATE_v6pcie68,
CFGPMRCVASREQL1N => CFGPMRCVASREQL1N_v6pcie72,
CFGPMRCVENTERL1N => CFGPMRCVENTERL1N_v6pcie73,
CFGPMRCVENTERL23N => CFGPMRCVENTERL23N_v6pcie74,
CFGPMRCVREQACKN => CFGPMRCVREQACKN_v6pcie75,
CFGPMCSRPMEEN => CFGPMCSRPMEEN_v6pcie69,
CFGPMCSRPMESTATUS => CFGPMCSRPMESTATUS_v6pcie70,
CFGPMCSRPOWERSTATE => CFGPMCSRPOWERSTATE_v6pcie71,
CFGRDWRDONEN => CFGRDWRDONEN_v6pcie76,
CFGSLOTCONTROLELECTROMECHILCTLPULSE => CFGSLOTCONTROLELECTROMECHILCTLPULSE_v6pcie77,
CFGTRANSACTION => CFGTRANSACTION_v6pcie78,
CFGTRANSACTIONADDR => CFGTRANSACTIONADDR_v6pcie79,
CFGTRANSACTIONTYPE => CFGTRANSACTIONTYPE_v6pcie80,
CFGVCTCVCMAP => CFGVCTCVCMAP_v6pcie81,
DBGSCLRA => DBGSCLRA_v6pcie82,
DBGSCLRB => DBGSCLRB_v6pcie83,
DBGSCLRC => DBGSCLRC_v6pcie84,
DBGSCLRD => DBGSCLRD_v6pcie85,
DBGSCLRE => DBGSCLRE_v6pcie86,
DBGSCLRF => DBGSCLRF_v6pcie87,
DBGSCLRG => DBGSCLRG_v6pcie88,
DBGSCLRH => DBGSCLRH_v6pcie89,
DBGSCLRI => DBGSCLRI_v6pcie90,
DBGSCLRJ => DBGSCLRJ_v6pcie91,
DBGSCLRK => DBGSCLRK_v6pcie92,
DBGVECA => DBGVECA_v6pcie93,
DBGVECB => DBGVECB_v6pcie94,
DBGVECC => DBGVECC_v6pcie95,
DRPDO => PCIEDRPDO_v6pcie98,
DRPDRDY => PCIEDRPDRDY_v6pcie99,
LL2BADDLLPERRN => LL2BADDLLPERRN,
LL2BADTLPERRN => LL2BADTLPERRN,
LL2PROTOCOLERRN => LL2PROTOCOLERRN,
LL2REPLAYROERRN => LL2REPLAYROERRN,
LL2REPLAYTOERRN => LL2REPLAYTOERRN,
LL2SUSPENDOKN => LL2SUSPENDOKN,
LL2TFCINIT1SEQN => LL2TFCINIT1SEQN,
LL2TFCINIT2SEQN => LL2TFCINIT2SEQN,
MIMRXRADDR => MIMRXRADDR,
MIMRXRCE => MIMRXRCE,
MIMRXREN => MIMRXREN,
MIMRXWADDR => MIMRXWADDR,
MIMRXWDATA => MIMRXWDATA,
MIMRXWEN => MIMRXWEN,
MIMTXRADDR => MIMTXRADDR,
MIMTXRCE => MIMTXRCE,
MIMTXREN => MIMTXREN,
MIMTXWADDR => MIMTXWADDR,
MIMTXWDATA => MIMTXWDATA,
MIMTXWEN => MIMTXWEN,
PIPERX0POLARITY => PIPERX0POLARITY,
PIPERX1POLARITY => PIPERX1POLARITY,
PIPERX2POLARITY => PIPERX2POLARITY,
PIPERX3POLARITY => PIPERX3POLARITY,
PIPERX4POLARITY => PIPERX4POLARITY,
PIPERX5POLARITY => PIPERX5POLARITY,
PIPERX6POLARITY => PIPERX6POLARITY,
PIPERX7POLARITY => PIPERX7POLARITY,
PIPETXDEEMPH => PIPETXDEEMPH,
PIPETXMARGIN => PIPETXMARGIN,
PIPETXRATE => PIPETXRATE,
PIPETXRCVRDET => PIPETXRCVRDET,
PIPETXRESET => PIPETXRESET,
PIPETX0CHARISK => PIPETX0CHARISK,
PIPETX0COMPLIANCE => PIPETX0COMPLIANCE,
PIPETX0DATA => PIPETX0DATA,
PIPETX0ELECIDLE => PIPETX0ELECIDLE,
PIPETX0POWERDOWN => PIPETX0POWERDOWN,
PIPETX1CHARISK => PIPETX1CHARISK,
PIPETX1COMPLIANCE => PIPETX1COMPLIANCE,
PIPETX1DATA => PIPETX1DATA,
PIPETX1ELECIDLE => PIPETX1ELECIDLE,
PIPETX1POWERDOWN => PIPETX1POWERDOWN,
PIPETX2CHARISK => PIPETX2CHARISK,
PIPETX2COMPLIANCE => PIPETX2COMPLIANCE,
PIPETX2DATA => PIPETX2DATA,
PIPETX2ELECIDLE => PIPETX2ELECIDLE,
PIPETX2POWERDOWN => PIPETX2POWERDOWN,
PIPETX3CHARISK => PIPETX3CHARISK,
PIPETX3COMPLIANCE => PIPETX3COMPLIANCE,
PIPETX3DATA => PIPETX3DATA,
PIPETX3ELECIDLE => PIPETX3ELECIDLE,
PIPETX3POWERDOWN => PIPETX3POWERDOWN,
PIPETX4CHARISK => PIPETX4CHARISK,
PIPETX4COMPLIANCE => PIPETX4COMPLIANCE,
PIPETX4DATA => PIPETX4DATA,
PIPETX4ELECIDLE => PIPETX4ELECIDLE,
PIPETX4POWERDOWN => PIPETX4POWERDOWN,
PIPETX5CHARISK => PIPETX5CHARISK,
PIPETX5COMPLIANCE => PIPETX5COMPLIANCE,
PIPETX5DATA => PIPETX5DATA,
PIPETX5ELECIDLE => PIPETX5ELECIDLE,
PIPETX5POWERDOWN => PIPETX5POWERDOWN,
PIPETX6CHARISK => PIPETX6CHARISK,
PIPETX6COMPLIANCE => PIPETX6COMPLIANCE,
PIPETX6DATA => PIPETX6DATA,
PIPETX6ELECIDLE => PIPETX6ELECIDLE,
PIPETX6POWERDOWN => PIPETX6POWERDOWN,
PIPETX7CHARISK => PIPETX7CHARISK,
PIPETX7COMPLIANCE => PIPETX7COMPLIANCE,
PIPETX7DATA => PIPETX7DATA,
PIPETX7ELECIDLE => PIPETX7ELECIDLE,
PIPETX7POWERDOWN => PIPETX7POWERDOWN,
PLDBGVEC => PLDBGVEC_v6pcie103,
PLINITIALLINKWIDTH => PLINITIALLINKWIDTH_v6pcie104,
PLLANEREVERSALMODE => PLLANEREVERSALMODE_v6pcie105,
PLLINKGEN2CAP => PLLINKGEN2CAP_v6pcie106,
PLLINKPARTNERGEN2SUPPORTED => PLLINKPARTNERGEN2SUPPORTED_v6pcie107,
PLLINKUPCFGCAP => PLLINKUPCFGCAP_v6pcie108,
PLLTSSMSTATE => PLLTSSMSTATE_v6pcie109,
PLPHYLNKUPN => PLPHYLNKUPN_v6pcie110,
PLRECEIVEDHOTRST => PLRECEIVEDHOTRST_v6pcie111,
PLRXPMSTATE => PLRXPMSTATE_v6pcie112,
PLSELLNKRATE => PLSELLNKRATE_v6pcie113,
PLSELLNKWIDTH => PLSELLNKWIDTH_v6pcie114,
PLTXPMSTATE => PLTXPMSTATE_v6pcie115,
PL2LINKUPN => PL2LINKUPN,
PL2RECEIVERERRN => PL2RECEIVERERRN,
PL2RECOVERYN => PL2RECOVERYN,
PL2RXELECIDLE => PL2RXELECIDLE,
PL2SUSPENDOK => PL2SUSPENDOK,
RECEIVEDFUNCLVLRSTN => RECEIVEDFUNCLVLRSTN_v6pcie116,
LNKCLKEN => LNKCLKEN_v6pcie97,
TL2ASPMSUSPENDCREDITCHECKOKN => TL2ASPMSUSPENDCREDITCHECKOKN,
TL2ASPMSUSPENDREQN => TL2ASPMSUSPENDREQN,
TL2PPMSUSPENDOKN => TL2PPMSUSPENDOKN,
TRNFCCPLD => TRNFCCPLD_v6pcie117,
TRNFCCPLH => TRNFCCPLH_v6pcie118,
TRNFCNPD => TRNFCNPD_v6pcie119,
TRNFCNPH => TRNFCNPH_v6pcie120,
TRNFCPD => TRNFCPD_v6pcie121,
TRNFCPH => TRNFCPH_v6pcie122,
TRNLNKUPN => TRNLNKUPN_v6pcie123,
TRNRBARHITN => TRNRBARHITN_v6pcie124,
TRNRD => TRNRD_v6pcie125,
TRNRDLLPDATA => open,
TRNRDLLPSRCRDYN => TRNRDLLPSRCRDYN,
TRNRECRCERRN => TRNRECRCERRN_v6pcie126,
TRNREOFN => TRNREOFN_v6pcie127,
TRNRERRFWDN => TRNRERRFWDN_v6pcie128,
TRNRREMN => TRNRREMN_v6pcie129,
TRNRSOFN => TRNRSOFN_v6pcie130,
TRNRSRCDSCN => TRNRSRCDSCN_v6pcie131,
TRNRSRCRDYN => TRNRSRCRDYN_v6pcie132,
TRNTBUFAV => TRNTBUFAV_v6pcie133,
TRNTCFGREQN => TRNTCFGREQN_v6pcie134,
TRNTDLLPDSTRDYN => TRNTDLLPDSTRDYN_v6pcie135,
TRNTDSTRDYN => TRNTDSTRDYN_v6pcie136,
TRNTERRDROPN => TRNTERRDROPN_v6pcie137,
USERRSTN => USERRSTN_v6pcie139,
CFGBYTEENN => CFGBYTEENN,
CFGDI => CFGDI,
CFGDSBUSNUMBER => CFGDSBUSNUMBER,
CFGDSDEVICENUMBER => CFGDSDEVICENUMBER,
CFGDSFUNCTIONNUMBER => CFGDSFUNCTIONNUMBER,
CFGDSN => CFGDSN,
CFGDWADDR => CFGDWADDR,
CFGERRACSN => CFGERRACSN,
CFGERRAERHEADERLOG => CFGERRAERHEADERLOG,
CFGERRCORN => CFGERRCORN,
CFGERRCPLABORTN => CFGERRCPLABORTN,
CFGERRCPLTIMEOUTN => CFGERRCPLTIMEOUTN,
CFGERRCPLUNEXPECTN => CFGERRCPLUNEXPECTN,
CFGERRECRCN => CFGERRECRCN,
CFGERRLOCKEDN => CFGERRLOCKEDN,
CFGERRPOSTEDN => CFGERRPOSTEDN,
CFGERRTLPCPLHEADER => CFGERRTLPCPLHEADER,
CFGERRURN => CFGERRURN,
CFGINTERRUPTASSERTN => CFGINTERRUPTASSERTN,
CFGINTERRUPTDI => CFGINTERRUPTDI,
CFGINTERRUPTN => CFGINTERRUPTN,
CFGPMDIRECTASPML1N => CFGPMDIRECTASPML1N,
CFGPMSENDPMACKN => CFGPMSENDPMACKN,
CFGPMSENDPMETON => CFGPMSENDPMETON,
CFGPMSENDPMNAKN => CFGPMSENDPMNAKN,
CFGPMTURNOFFOKN => CFGPMTURNOFFOKN,
CFGPMWAKEN => CFGPMWAKEN,
CFGPORTNUMBER => CFGPORTNUMBER,
CFGRDENN => CFGRDENN,
CFGTRNPENDINGN => CFGTRNPENDINGN,
CFGWRENN => CFGWRENN,
CFGWRREADONLYN => CFGWRREADONLYN,
CFGWRRW1CASRWN => CFGWRRW1CASRWN,
CMRSTN => CMRSTN,
CMSTICKYRSTN => CMSTICKYRSTN,
DBGMODE => DBGMODE,
DBGSUBMODE => DBGSUBMODE,
DLRSTN => DLRSTN,
DRPCLK => PCIEDRPCLK,
DRPDADDR => PCIEDRPDADDR,
DRPDEN => PCIEDRPDEN,
DRPDI => PCIEDRPDI,
DRPDWE => PCIEDRPDWE,
FUNCLVLRSTN => FUNCLVLRSTN,
LL2SENDASREQL1N => LL2SENDASREQL1N,
LL2SENDENTERL1N => LL2SENDENTERL1N,
LL2SENDENTERL23N => LL2SENDENTERL23N,
LL2SUSPENDNOWN => LL2SUSPENDNOWN,
LL2TLPRCVN => LL2TLPRCVN,
MIMRXRDATA => MIMRXRDATA(67 downto 0),
MIMTXRDATA => MIMTXRDATA(68 downto 0),
PIPECLK => PIPECLK,
PIPERX0CHANISALIGNED => PIPERX0CHANISALIGNED,
PIPERX0CHARISK => PIPERX0CHARISK_v6pcie,
PIPERX0DATA => PIPERX0DATA,
PIPERX0ELECIDLE => PIPERX0ELECIDLE,
PIPERX0PHYSTATUS => PIPERX0PHYSTATUS,
PIPERX0STATUS => PIPERX0STATUS,
PIPERX0VALID => PIPERX0VALID,
PIPERX1CHANISALIGNED => PIPERX1CHANISALIGNED,
PIPERX1CHARISK => PIPERX1CHARISK_v6pcie,
PIPERX1DATA => PIPERX1DATA,
PIPERX1ELECIDLE => PIPERX1ELECIDLE,
PIPERX1PHYSTATUS => PIPERX1PHYSTATUS,
PIPERX1STATUS => PIPERX1STATUS,
PIPERX1VALID => PIPERX1VALID,
PIPERX2CHANISALIGNED => PIPERX2CHANISALIGNED,
PIPERX2CHARISK => PIPERX2CHARISK_v6pcie,
PIPERX2DATA => PIPERX2DATA,
PIPERX2ELECIDLE => PIPERX2ELECIDLE,
PIPERX2PHYSTATUS => PIPERX2PHYSTATUS,
PIPERX2STATUS => PIPERX2STATUS,
PIPERX2VALID => PIPERX2VALID,
PIPERX3CHANISALIGNED => PIPERX3CHANISALIGNED,
PIPERX3CHARISK => PIPERX3CHARISK_v6pcie,
PIPERX3DATA => PIPERX3DATA,
PIPERX3ELECIDLE => PIPERX3ELECIDLE,
PIPERX3PHYSTATUS => PIPERX3PHYSTATUS,
PIPERX3STATUS => PIPERX3STATUS,
PIPERX3VALID => PIPERX3VALID,
PIPERX4CHANISALIGNED => PIPERX4CHANISALIGNED,
PIPERX4CHARISK => PIPERX4CHARISK_v6pcie,
PIPERX4DATA => PIPERX4DATA,
PIPERX4ELECIDLE => PIPERX4ELECIDLE,
PIPERX4PHYSTATUS => PIPERX4PHYSTATUS,
PIPERX4STATUS => PIPERX4STATUS,
PIPERX4VALID => PIPERX4VALID,
PIPERX5CHANISALIGNED => PIPERX5CHANISALIGNED,
PIPERX5CHARISK => PIPERX5CHARISK_v6pcie,
PIPERX5DATA => PIPERX5DATA,
PIPERX5ELECIDLE => PIPERX5ELECIDLE,
PIPERX5PHYSTATUS => PIPERX5PHYSTATUS,
PIPERX5STATUS => PIPERX5STATUS,
PIPERX5VALID => PIPERX5VALID,
PIPERX6CHANISALIGNED => PIPERX6CHANISALIGNED,
PIPERX6CHARISK => PIPERX6CHARISK_v6pcie,
PIPERX6DATA => PIPERX6DATA,
PIPERX6ELECIDLE => PIPERX6ELECIDLE,
PIPERX6PHYSTATUS => PIPERX6PHYSTATUS,
PIPERX6STATUS => PIPERX6STATUS,
PIPERX6VALID => PIPERX6VALID,
PIPERX7CHANISALIGNED => PIPERX7CHANISALIGNED,
PIPERX7CHARISK => PIPERX7CHARISK_v6pcie,
PIPERX7DATA => PIPERX7DATA,
PIPERX7ELECIDLE => PIPERX7ELECIDLE,
PIPERX7PHYSTATUS => PIPERX7PHYSTATUS,
PIPERX7STATUS => PIPERX7STATUS,
PIPERX7VALID => PIPERX7VALID,
PLDBGMODE => PLDBGMODE,
PLDIRECTEDLINKAUTON => PLDIRECTEDLINKAUTON,
PLDIRECTEDLINKCHANGE => PLDIRECTEDLINKCHANGE,
PLDIRECTEDLINKSPEED => PLDIRECTEDLINKSPEED,
PLDIRECTEDLINKWIDTH => PLDIRECTEDLINKWIDTH,
PLDOWNSTREAMDEEMPHSOURCE => PLDOWNSTREAMDEEMPHSOURCE,
PLRSTN => PLRSTN,
PLTRANSMITHOTRST => PLTRANSMITHOTRST,
PLUPSTREAMPREFERDEEMPH => PLUPSTREAMPREFERDEEMPH,
PL2DIRECTEDLSTATE => PL2DIRECTEDLSTATE,
SYSRSTN => SYSRSTN,
TLRSTN => TLRSTN,
TL2ASPMSUSPENDCREDITCHECKN => '1',
TL2PPMSUSPENDREQN => '1',
TRNFCSEL => TRNFCSEL,
TRNRDSTRDYN => TRNRDSTRDYN,
TRNRNPOKN => TRNRNPOKN,
TRNTCFGGNTN => TRNTCFGGNTN,
TRNTD => TRNTD,
TRNTDLLPDATA => TRNTDLLPDATA,
TRNTDLLPSRCRDYN => TRNTDLLPSRCRDYN,
TRNTECRCGENN => TRNTECRCGENN,
TRNTEOFN => TRNTEOFN,
TRNTERRFWDN => TRNTERRFWDN,
TRNTREMN => TRNTREMN,
TRNTSOFN => TRNTSOFN,
TRNTSRCDSCN => TRNTSRCDSCN,
TRNTSRCRDYN => TRNTSRCRDYN,
TRNTSTRN => TRNTSTRN,
USERCLK => USERCLK
);
---------------------------------------------------------
-- Virtex6 PIPE Module
---------------------------------------------------------
pcie_pipe_i : pcie_pipe_v6
generic map (
NO_OF_LANES => LINK_CAP_MAX_LINK_WIDTH_int,
LINK_CAP_MAX_LINK_SPEED => LINK_CAP_MAX_LINK_SPEED,
PIPE_PIPELINE_STAGES => PIPE_PIPELINE_STAGES
)
port map (
-- Pipe Per-Link Signals
pipe_tx_rcvr_det_i => PIPETXRCVRDET,
pipe_tx_reset_i => PIPETXRESET,
pipe_tx_rate_i => PIPETXRATE,
pipe_tx_deemph_i => PIPETXDEEMPH,
pipe_tx_margin_i => PIPETXMARGIN,
pipe_tx_swing_i => '0',
pipe_tx_rcvr_det_o => PIPETXRCVRDETGT,
pipe_tx_reset_o => open,
pipe_tx_rate_o => PIPETXRATEGT,
pipe_tx_deemph_o => PIPETXDEEMPHGT,
pipe_tx_margin_o => PIPETXMARGINGT,
pipe_tx_swing_o => open,
-- Pipe Per-Lane Signals - Lane 0
pipe_rx0_char_is_k_o => PIPERX0CHARISK,
pipe_rx0_data_o => PIPERX0DATA,
pipe_rx0_valid_o => PIPERX0VALID,
pipe_rx0_chanisaligned_o => PIPERX0CHANISALIGNED,
pipe_rx0_status_o => PIPERX0STATUS,
pipe_rx0_phy_status_o => PIPERX0PHYSTATUS,
pipe_rx0_elec_idle_i => PIPERX0ELECIDLEGT,
pipe_rx0_polarity_i => PIPERX0POLARITY,
pipe_tx0_compliance_i => PIPETX0COMPLIANCE,
pipe_tx0_char_is_k_i => PIPETX0CHARISK,
pipe_tx0_data_i => PIPETX0DATA,
pipe_tx0_elec_idle_i => PIPETX0ELECIDLE,
pipe_tx0_powerdown_i => PIPETX0POWERDOWN,
pipe_rx0_char_is_k_i => PIPERX0CHARISKGT,
pipe_rx0_data_i => PIPERX0DATAGT,
pipe_rx0_valid_i => PIPERX0VALIDGT,
pipe_rx0_chanisaligned_i => PIPERX0CHANISALIGNEDGT,
pipe_rx0_status_i => PIPERX0STATUSGT,
pipe_rx0_phy_status_i => PIPERX0PHYSTATUSGT,
pipe_rx0_elec_idle_o => PIPERX0ELECIDLE,
pipe_rx0_polarity_o => PIPERX0POLARITYGT,
pipe_tx0_compliance_o => PIPETX0COMPLIANCEGT,
pipe_tx0_char_is_k_o => PIPETX0CHARISKGT,
pipe_tx0_data_o => PIPETX0DATAGT,
pipe_tx0_elec_idle_o => PIPETX0ELECIDLEGT,
pipe_tx0_powerdown_o => PIPETX0POWERDOWNGT,
-- Pipe Per-Lane Signals - Lane 1
pipe_rx1_char_is_k_o => PIPERX1CHARISK,
pipe_rx1_data_o => PIPERX1DATA,
pipe_rx1_valid_o => PIPERX1VALID,
pipe_rx1_chanisaligned_o => PIPERX1CHANISALIGNED,
pipe_rx1_status_o => PIPERX1STATUS,
pipe_rx1_phy_status_o => PIPERX1PHYSTATUS,
pipe_rx1_elec_idle_i => PIPERX1ELECIDLEGT,
pipe_rx1_polarity_i => PIPERX1POLARITY,
pipe_tx1_compliance_i => PIPETX1COMPLIANCE,
pipe_tx1_char_is_k_i => PIPETX1CHARISK,
pipe_tx1_data_i => PIPETX1DATA,
pipe_tx1_elec_idle_i => PIPETX1ELECIDLE,
pipe_tx1_powerdown_i => PIPETX1POWERDOWN,
pipe_rx1_char_is_k_i => PIPERX1CHARISKGT,
pipe_rx1_data_i => PIPERX1DATAGT,
pipe_rx1_valid_i => PIPERX1VALIDGT,
pipe_rx1_chanisaligned_i => PIPERX1CHANISALIGNEDGT,
pipe_rx1_status_i => PIPERX1STATUSGT,
pipe_rx1_phy_status_i => PIPERX1PHYSTATUSGT,
pipe_rx1_elec_idle_o => PIPERX1ELECIDLE,
pipe_rx1_polarity_o => PIPERX1POLARITYGT,
pipe_tx1_compliance_o => PIPETX1COMPLIANCEGT,
pipe_tx1_char_is_k_o => PIPETX1CHARISKGT,
pipe_tx1_data_o => PIPETX1DATAGT,
pipe_tx1_elec_idle_o => PIPETX1ELECIDLEGT,
pipe_tx1_powerdown_o => PIPETX1POWERDOWNGT,
-- Pipe Per-Lane Signals - Lane 2
pipe_rx2_char_is_k_o => PIPERX2CHARISK,
pipe_rx2_data_o => PIPERX2DATA,
pipe_rx2_valid_o => PIPERX2VALID,
pipe_rx2_chanisaligned_o => PIPERX2CHANISALIGNED,
pipe_rx2_status_o => PIPERX2STATUS,
pipe_rx2_phy_status_o => PIPERX2PHYSTATUS,
pipe_rx2_elec_idle_i => PIPERX2ELECIDLEGT,
pipe_rx2_polarity_i => PIPERX2POLARITY,
pipe_tx2_compliance_i => PIPETX2COMPLIANCE,
pipe_tx2_char_is_k_i => PIPETX2CHARISK,
pipe_tx2_data_i => PIPETX2DATA,
pipe_tx2_elec_idle_i => PIPETX2ELECIDLE,
pipe_tx2_powerdown_i => PIPETX2POWERDOWN,
pipe_rx2_char_is_k_i => PIPERX2CHARISKGT,
pipe_rx2_data_i => PIPERX2DATAGT,
pipe_rx2_valid_i => PIPERX2VALIDGT,
pipe_rx2_chanisaligned_i => PIPERX2CHANISALIGNEDGT,
pipe_rx2_status_i => PIPERX2STATUSGT,
pipe_rx2_phy_status_i => PIPERX2PHYSTATUSGT,
pipe_rx2_elec_idle_o => PIPERX2ELECIDLE,
pipe_rx2_polarity_o => PIPERX2POLARITYGT,
pipe_tx2_compliance_o => PIPETX2COMPLIANCEGT,
pipe_tx2_char_is_k_o => PIPETX2CHARISKGT,
pipe_tx2_data_o => PIPETX2DATAGT,
pipe_tx2_elec_idle_o => PIPETX2ELECIDLEGT,
pipe_tx2_powerdown_o => PIPETX2POWERDOWNGT,
-- Pipe Per-Lane Signals - Lane 3
pipe_rx3_char_is_k_o => PIPERX3CHARISK,
pipe_rx3_data_o => PIPERX3DATA,
pipe_rx3_valid_o => PIPERX3VALID,
pipe_rx3_chanisaligned_o => PIPERX3CHANISALIGNED,
pipe_rx3_status_o => PIPERX3STATUS,
pipe_rx3_phy_status_o => PIPERX3PHYSTATUS,
pipe_rx3_elec_idle_i => PIPERX3ELECIDLEGT,
pipe_rx3_polarity_i => PIPERX3POLARITY,
pipe_tx3_compliance_i => PIPETX3COMPLIANCE,
pipe_tx3_char_is_k_i => PIPETX3CHARISK,
pipe_tx3_data_i => PIPETX3DATA,
pipe_tx3_elec_idle_i => PIPETX3ELECIDLE,
pipe_tx3_powerdown_i => PIPETX3POWERDOWN,
pipe_rx3_char_is_k_i => PIPERX3CHARISKGT,
pipe_rx3_data_i => PIPERX3DATAGT,
pipe_rx3_valid_i => PIPERX3VALIDGT,
pipe_rx3_chanisaligned_i => PIPERX3CHANISALIGNEDGT,
pipe_rx3_status_i => PIPERX3STATUSGT,
pipe_rx3_phy_status_i => PIPERX3PHYSTATUSGT,
pipe_rx3_elec_idle_o => PIPERX3ELECIDLE,
pipe_rx3_polarity_o => PIPERX3POLARITYGT,
pipe_tx3_compliance_o => PIPETX3COMPLIANCEGT,
pipe_tx3_char_is_k_o => PIPETX3CHARISKGT,
pipe_tx3_data_o => PIPETX3DATAGT,
pipe_tx3_elec_idle_o => PIPETX3ELECIDLEGT,
pipe_tx3_powerdown_o => PIPETX3POWERDOWNGT,
-- Pipe Per-Lane Signals - Lane 4
pipe_rx4_char_is_k_o => PIPERX4CHARISK,
pipe_rx4_data_o => PIPERX4DATA,
pipe_rx4_valid_o => PIPERX4VALID,
pipe_rx4_chanisaligned_o => PIPERX4CHANISALIGNED,
pipe_rx4_status_o => PIPERX4STATUS,
pipe_rx4_phy_status_o => PIPERX4PHYSTATUS,
pipe_rx4_elec_idle_i => PIPERX4ELECIDLEGT,
pipe_rx4_polarity_i => PIPERX4POLARITY,
pipe_tx4_compliance_i => PIPETX4COMPLIANCE,
pipe_tx4_char_is_k_i => PIPETX4CHARISK,
pipe_tx4_data_i => PIPETX4DATA,
pipe_tx4_elec_idle_i => PIPETX4ELECIDLE,
pipe_tx4_powerdown_i => PIPETX4POWERDOWN,
pipe_rx4_char_is_k_i => PIPERX4CHARISKGT,
pipe_rx4_data_i => PIPERX4DATAGT,
pipe_rx4_valid_i => PIPERX4VALIDGT,
pipe_rx4_chanisaligned_i => PIPERX4CHANISALIGNEDGT,
pipe_rx4_status_i => PIPERX4STATUSGT,
pipe_rx4_phy_status_i => PIPERX4PHYSTATUSGT,
pipe_rx4_elec_idle_o => PIPERX4ELECIDLE,
pipe_rx4_polarity_o => PIPERX4POLARITYGT,
pipe_tx4_compliance_o => PIPETX4COMPLIANCEGT,
pipe_tx4_char_is_k_o => PIPETX4CHARISKGT,
pipe_tx4_data_o => PIPETX4DATAGT,
pipe_tx4_elec_idle_o => PIPETX4ELECIDLEGT,
pipe_tx4_powerdown_o => PIPETX4POWERDOWNGT,
-- Pipe Per-Lane Signals - Lane 5
pipe_rx5_char_is_k_o => PIPERX5CHARISK,
pipe_rx5_data_o => PIPERX5DATA,
pipe_rx5_valid_o => PIPERX5VALID,
pipe_rx5_chanisaligned_o => PIPERX5CHANISALIGNED,
pipe_rx5_status_o => PIPERX5STATUS,
pipe_rx5_phy_status_o => PIPERX5PHYSTATUS,
pipe_rx5_elec_idle_i => PIPERX5ELECIDLEGT,
pipe_rx5_polarity_i => PIPERX5POLARITY,
pipe_tx5_compliance_i => PIPETX5COMPLIANCE,
pipe_tx5_char_is_k_i => PIPETX5CHARISK,
pipe_tx5_data_i => PIPETX5DATA,
pipe_tx5_elec_idle_i => PIPETX5ELECIDLE,
pipe_tx5_powerdown_i => PIPETX5POWERDOWN,
pipe_rx5_char_is_k_i => PIPERX5CHARISKGT,
pipe_rx5_data_i => PIPERX5DATAGT,
pipe_rx5_valid_i => PIPERX5VALIDGT,
pipe_rx5_chanisaligned_i => PIPERX5CHANISALIGNEDGT,
pipe_rx5_status_i => PIPERX5STATUSGT,
pipe_rx5_phy_status_i => PIPERX5PHYSTATUSGT,
pipe_rx5_elec_idle_o => PIPERX5ELECIDLE,
pipe_rx5_polarity_o => PIPERX5POLARITYGT,
pipe_tx5_compliance_o => PIPETX5COMPLIANCEGT,
pipe_tx5_char_is_k_o => PIPETX5CHARISKGT,
pipe_tx5_data_o => PIPETX5DATAGT,
pipe_tx5_elec_idle_o => PIPETX5ELECIDLEGT,
pipe_tx5_powerdown_o => PIPETX5POWERDOWNGT,
-- Pipe Per-Lane Signals - Lane 6
pipe_rx6_char_is_k_o => PIPERX6CHARISK,
pipe_rx6_data_o => PIPERX6DATA,
pipe_rx6_valid_o => PIPERX6VALID,
pipe_rx6_chanisaligned_o => PIPERX6CHANISALIGNED,
pipe_rx6_status_o => PIPERX6STATUS,
pipe_rx6_phy_status_o => PIPERX6PHYSTATUS,
pipe_rx6_elec_idle_i => PIPERX6ELECIDLEGT,
pipe_rx6_polarity_i => PIPERX6POLARITY,
pipe_tx6_compliance_i => PIPETX6COMPLIANCE,
pipe_tx6_char_is_k_i => PIPETX6CHARISK,
pipe_tx6_data_i => PIPETX6DATA,
pipe_tx6_elec_idle_i => PIPETX6ELECIDLE,
pipe_tx6_powerdown_i => PIPETX6POWERDOWN,
pipe_rx6_char_is_k_i => PIPERX6CHARISKGT,
pipe_rx6_data_i => PIPERX6DATAGT,
pipe_rx6_valid_i => PIPERX6VALIDGT,
pipe_rx6_chanisaligned_i => PIPERX6CHANISALIGNEDGT,
pipe_rx6_status_i => PIPERX6STATUSGT,
pipe_rx6_phy_status_i => PIPERX6PHYSTATUSGT,
pipe_rx6_elec_idle_o => PIPERX6ELECIDLE,
pipe_rx6_polarity_o => PIPERX6POLARITYGT,
pipe_tx6_compliance_o => PIPETX6COMPLIANCEGT,
pipe_tx6_char_is_k_o => PIPETX6CHARISKGT,
pipe_tx6_data_o => PIPETX6DATAGT,
pipe_tx6_elec_idle_o => PIPETX6ELECIDLEGT,
pipe_tx6_powerdown_o => PIPETX6POWERDOWNGT,
-- Pipe Per-Lane Signals - Lane 7
pipe_rx7_char_is_k_o => PIPERX7CHARISK,
pipe_rx7_data_o => PIPERX7DATA,
pipe_rx7_valid_o => PIPERX7VALID,
pipe_rx7_chanisaligned_o => PIPERX7CHANISALIGNED,
pipe_rx7_status_o => PIPERX7STATUS,
pipe_rx7_phy_status_o => PIPERX7PHYSTATUS,
pipe_rx7_elec_idle_i => PIPERX7ELECIDLEGT,
pipe_rx7_polarity_i => PIPERX7POLARITY,
pipe_tx7_compliance_i => PIPETX7COMPLIANCE,
pipe_tx7_char_is_k_i => PIPETX7CHARISK,
pipe_tx7_data_i => PIPETX7DATA,
pipe_tx7_elec_idle_i => PIPETX7ELECIDLE,
pipe_tx7_powerdown_i => PIPETX7POWERDOWN,
pipe_rx7_char_is_k_i => PIPERX7CHARISKGT,
pipe_rx7_data_i => PIPERX7DATAGT,
pipe_rx7_valid_i => PIPERX7VALIDGT,
pipe_rx7_chanisaligned_i => PIPERX7CHANISALIGNEDGT,
pipe_rx7_status_i => PIPERX7STATUSGT,
pipe_rx7_phy_status_i => PIPERX7PHYSTATUSGT,
pipe_rx7_elec_idle_o => PIPERX7ELECIDLE,
pipe_rx7_polarity_o => PIPERX7POLARITYGT,
pipe_tx7_compliance_o => PIPETX7COMPLIANCEGT,
pipe_tx7_char_is_k_o => PIPETX7CHARISKGT,
pipe_tx7_data_o => PIPETX7DATAGT,
pipe_tx7_elec_idle_o => PIPETX7ELECIDLEGT,
pipe_tx7_powerdown_o => PIPETX7POWERDOWNGT,
-- Non PIPE signals
pl_ltssm_state => PLLTSSMSTATE_v6pcie109,
pipe_clk => PIPECLK,
rst_n => PHYRDYN_v6pcie102
);
---------------------------------------------------------
-- Virtex6 GTX Module
---------------------------------------------------------
pcie_gt_i : pcie_gtx_v6
generic map (
NO_OF_LANES => LINK_CAP_MAX_LINK_WIDTH_int,
LINK_CAP_MAX_LINK_SPEED => LINK_CAP_MAX_LINK_SPEED,
REF_CLK_FREQ => REF_CLK_FREQ,
PL_FAST_TRAIN => PL_FAST_TRAIN
)
port map (
-- Pipe Common Signals
pipe_tx_rcvr_det => PIPETXRCVRDETGT,
pipe_tx_reset => '0',
pipe_tx_rate => PIPETXRATEGT,
pipe_tx_deemph => PIPETXDEEMPHGT,
pipe_tx_margin => PIPETXMARGINGT,
pipe_tx_swing => '0',
-- Pipe Per-Lane Signals - Lane 0
pipe_rx0_char_is_k => PIPERX0CHARISKGT,
pipe_rx0_data => PIPERX0DATAGT,
pipe_rx0_valid => PIPERX0VALIDGT,
pipe_rx0_chanisaligned => PIPERX0CHANISALIGNEDGT,
pipe_rx0_status => PIPERX0STATUSGT,
pipe_rx0_phy_status => PIPERX0PHYSTATUSGT,
pipe_rx0_elec_idle => PIPERX0ELECIDLEGT,
pipe_rx0_polarity => PIPERX0POLARITYGT,
pipe_tx0_compliance => PIPETX0COMPLIANCEGT,
pipe_tx0_char_is_k => PIPETX0CHARISKGT,
pipe_tx0_data => PIPETX0DATAGT,
pipe_tx0_elec_idle => PIPETX0ELECIDLEGT,
pipe_tx0_powerdown => PIPETX0POWERDOWNGT,
-- Pipe Per-Lane Signals - Lane 1
pipe_rx1_char_is_k => PIPERX1CHARISKGT,
pipe_rx1_data => PIPERX1DATAGT,
pipe_rx1_valid => PIPERX1VALIDGT,
pipe_rx1_chanisaligned => PIPERX1CHANISALIGNEDGT,
pipe_rx1_status => PIPERX1STATUSGT,
pipe_rx1_phy_status => PIPERX1PHYSTATUSGT,
pipe_rx1_elec_idle => PIPERX1ELECIDLEGT,
pipe_rx1_polarity => PIPERX1POLARITYGT,
pipe_tx1_compliance => PIPETX1COMPLIANCEGT,
pipe_tx1_char_is_k => PIPETX1CHARISKGT,
pipe_tx1_data => PIPETX1DATAGT,
pipe_tx1_elec_idle => PIPETX1ELECIDLEGT,
pipe_tx1_powerdown => PIPETX1POWERDOWNGT,
-- Pipe Per-Lane Signals - Lane 2
pipe_rx2_char_is_k => PIPERX2CHARISKGT,
pipe_rx2_data => PIPERX2DATAGT,
pipe_rx2_valid => PIPERX2VALIDGT,
pipe_rx2_chanisaligned => PIPERX2CHANISALIGNEDGT,
pipe_rx2_status => PIPERX2STATUSGT,
pipe_rx2_phy_status => PIPERX2PHYSTATUSGT,
pipe_rx2_elec_idle => PIPERX2ELECIDLEGT,
pipe_rx2_polarity => PIPERX2POLARITYGT,
pipe_tx2_compliance => PIPETX2COMPLIANCEGT,
pipe_tx2_char_is_k => PIPETX2CHARISKGT,
pipe_tx2_data => PIPETX2DATAGT,
pipe_tx2_elec_idle => PIPETX2ELECIDLEGT,
pipe_tx2_powerdown => PIPETX2POWERDOWNGT,
-- Pipe Per-Lane Signals - Lane 3
pipe_rx3_char_is_k => PIPERX3CHARISKGT,
pipe_rx3_data => PIPERX3DATAGT,
pipe_rx3_valid => PIPERX3VALIDGT,
pipe_rx3_chanisaligned => PIPERX3CHANISALIGNEDGT,
pipe_rx3_status => PIPERX3STATUSGT,
pipe_rx3_phy_status => PIPERX3PHYSTATUSGT,
pipe_rx3_elec_idle => PIPERX3ELECIDLEGT,
pipe_rx3_polarity => PIPERX3POLARITYGT,
pipe_tx3_compliance => PIPETX3COMPLIANCEGT,
pipe_tx3_char_is_k => PIPETX3CHARISKGT,
pipe_tx3_data => PIPETX3DATAGT,
pipe_tx3_elec_idle => PIPETX3ELECIDLEGT,
pipe_tx3_powerdown => PIPETX3POWERDOWNGT,
-- Pipe Per-Lane Signals - Lane 4
pipe_rx4_char_is_k => PIPERX4CHARISKGT,
pipe_rx4_data => PIPERX4DATAGT,
pipe_rx4_valid => PIPERX4VALIDGT,
pipe_rx4_chanisaligned => PIPERX4CHANISALIGNEDGT,
pipe_rx4_status => PIPERX4STATUSGT,
pipe_rx4_phy_status => PIPERX4PHYSTATUSGT,
pipe_rx4_elec_idle => PIPERX4ELECIDLEGT,
pipe_rx4_polarity => PIPERX4POLARITYGT,
pipe_tx4_compliance => PIPETX4COMPLIANCEGT,
pipe_tx4_char_is_k => PIPETX4CHARISKGT,
pipe_tx4_data => PIPETX4DATAGT,
pipe_tx4_elec_idle => PIPETX4ELECIDLEGT,
pipe_tx4_powerdown => PIPETX4POWERDOWNGT,
-- Pipe Per-Lane Signals - Lane 5
pipe_rx5_char_is_k => PIPERX5CHARISKGT,
pipe_rx5_data => PIPERX5DATAGT,
pipe_rx5_valid => PIPERX5VALIDGT,
pipe_rx5_chanisaligned => PIPERX5CHANISALIGNEDGT,
pipe_rx5_status => PIPERX5STATUSGT,
pipe_rx5_phy_status => PIPERX5PHYSTATUSGT,
pipe_rx5_elec_idle => PIPERX5ELECIDLEGT,
pipe_rx5_polarity => PIPERX5POLARITYGT,
pipe_tx5_compliance => PIPETX5COMPLIANCEGT,
pipe_tx5_char_is_k => PIPETX5CHARISKGT,
pipe_tx5_data => PIPETX5DATAGT,
pipe_tx5_elec_idle => PIPETX5ELECIDLEGT,
pipe_tx5_powerdown => PIPETX5POWERDOWNGT,
-- Pipe Per-Lane Signals - Lane 6
pipe_rx6_char_is_k => PIPERX6CHARISKGT,
pipe_rx6_data => PIPERX6DATAGT,
pipe_rx6_valid => PIPERX6VALIDGT,
pipe_rx6_chanisaligned => PIPERX6CHANISALIGNEDGT,
pipe_rx6_status => PIPERX6STATUSGT,
pipe_rx6_phy_status => PIPERX6PHYSTATUSGT,
pipe_rx6_elec_idle => PIPERX6ELECIDLEGT,
pipe_rx6_polarity => PIPERX6POLARITYGT,
pipe_tx6_compliance => PIPETX6COMPLIANCEGT,
pipe_tx6_char_is_k => PIPETX6CHARISKGT,
pipe_tx6_data => PIPETX6DATAGT,
pipe_tx6_elec_idle => PIPETX6ELECIDLEGT,
pipe_tx6_powerdown => PIPETX6POWERDOWNGT,
-- Pipe Per-Lane Signals - Lane 7
pipe_rx7_char_is_k => PIPERX7CHARISKGT,
pipe_rx7_data => PIPERX7DATAGT,
pipe_rx7_valid => PIPERX7VALIDGT,
pipe_rx7_chanisaligned => PIPERX7CHANISALIGNEDGT,
pipe_rx7_status => PIPERX7STATUSGT,
pipe_rx7_phy_status => PIPERX7PHYSTATUSGT,
pipe_rx7_elec_idle => PIPERX7ELECIDLEGT,
pipe_rx7_polarity => PIPERX7POLARITYGT,
pipe_tx7_compliance => PIPETX7COMPLIANCEGT,
pipe_tx7_char_is_k => PIPETX7CHARISKGT,
pipe_tx7_data => PIPETX7DATAGT,
pipe_tx7_elec_idle => PIPETX7ELECIDLEGT,
pipe_tx7_powerdown => PIPETX7POWERDOWNGT,
-- PCI Express Signals
pci_exp_txn => PCIEXPTXN_v6pcie100,
pci_exp_txp => PCIEXPTXP_v6pcie101,
pci_exp_rxn => PCIEXPRXN,
pci_exp_rxp => PCIEXPRXP,
-- Non PIPE Signals
sys_clk => SYSCLK,
sys_rst_n => FUNDRSTN,
pipe_clk => PIPECLK,
drp_clk => DRPCLK,
clock_locked => CLOCKLOCKED,
pl_ltssm_state => PLLTSSMSTATE_v6pcie109,
gt_pll_lock => GTPLLLOCK_v6pcie96,
phy_rdy_n => PHYRDYN_v6pcie102,
txoutclk => TxOutClk_v6pcie138
);
---------------------------------------------------------
-- PCI Express BRAM Module
---------------------------------------------------------
MIMTXWDATA_tmp <= "000" & MIMTXWDATA;
MIMRXWDATA_tmp <= "0000" & MIMRXWDATA;
pcie_bram_i : pcie_bram_top_v6
generic map (
DEV_CAP_MAX_PAYLOAD_SUPPORTED => DEV_CAP_MAX_PAYLOAD_SUPPORTED,
VC0_TX_LASTPACKET => VC0_TX_LASTPACKET,
TL_TX_RAM_RADDR_LATENCY => TL_TX_RAM_RADDR_LATENCY,
TL_TX_RAM_RDATA_LATENCY => TL_TX_RAM_RDATA_LATENCY,
TL_TX_RAM_WRITE_LATENCY => TL_TX_RAM_WRITE_LATENCY,
VC0_RX_LIMIT => VC0_RX_RAM_LIMIT,
TL_RX_RAM_RADDR_LATENCY => TL_RX_RAM_RADDR_LATENCY,
TL_RX_RAM_RDATA_LATENCY => TL_RX_RAM_RDATA_LATENCY,
TL_RX_RAM_WRITE_LATENCY => TL_RX_RAM_WRITE_LATENCY
)
port map (
-- elseEN_128B_INT
user_clk_i => USERCLK,
reset_i => PHYRDYN_v6pcie102,
-- endifEN_128B_INT
mim_tx_waddr => MIMTXWADDR,
mim_tx_wen => MIMTXWEN,
mim_tx_ren => MIMTXREN,
mim_tx_rce => MIMTXRCE,
mim_tx_wdata => MIMTXWDATA_tmp,
mim_tx_raddr => MIMTXRADDR,
mim_tx_rdata => MIMTXRDATA,
mim_rx_waddr => MIMRXWADDR,
mim_rx_wen => MIMRXWEN,
mim_rx_ren => MIMRXREN,
mim_rx_rce => MIMRXRCE,
mim_rx_wdata => MIMRXWDATA_tmp,
mim_rx_raddr => MIMRXRADDR,
mim_rx_rdata => MIMRXRDATA
);
---------------------------------------------------------
-- PCI Express Port Workarounds
---------------------------------------------------------
pcie_upconfig_fix_3451_v6_i : pcie_upconfig_fix_3451_v6
generic map (
UPSTREAM_FACING => UPSTREAM_FACING,
PL_FAST_TRAIN => PL_FAST_TRAIN,
LINK_CAP_MAX_LINK_WIDTH => LINK_CAP_MAX_LINK_WIDTH
)
port map (
pipe_clk => PIPECLK,
pl_phy_lnkup_n => PLPHYLNKUPN_v6pcie110,
pl_ltssm_state => PLLTSSMSTATE_v6pcie109,
pl_sel_lnk_rate => PLSELLNKRATE_v6pcie113,
pl_directed_link_change => PLDIRECTEDLINKCHANGE,
cfg_link_status_negotiated_width => CFGLINKSTATUSNEGOTIATEDWIDTH_v6pcie48,
filter_pipe => filter_pipe_upconfig_fix_3451
);
end v6_pcie;
| gpl-3.0 | 9a0fffb97d689b90438e0ddecb9f0283 | 0.485658 | 3.978805 | false | false | false | false |
timofonic/PHDL | misc/projects/spartan_pcie_board/fpga/lx45t_pinout/ipcore_dir/pcie_core/source/gtpa1_dual_wrapper.vhd | 1 | 25,933 | -------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 1.7
-- \ \ Application : Spartan-6 FPGA GTP Transceiver Wizard
-- / / Filename : gtpa1_dual_wrapper.vhd
-- /___/ /\ Timestamp :
-- \ \ / \
-- \___\/\___\
--
--
-- Module GTPA1_DUAL_WRAPPER (a GTP Wrapper)
-- Generated by Xilinx Spartan-6 FPGA GTP Transceiver Wizard
--
--
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
--***************************** Entity Declaration ****************************
entity GTPA1_DUAL_WRAPPER is
generic
(
-- Simulation attributes
WRAPPER_SIM_GTPRESET_SPEEDUP : integer := 0; -- Set to 1 to speed up sim reset
WRAPPER_CLK25_DIVIDER_0 : integer := 4;
WRAPPER_CLK25_DIVIDER_1 : integer := 4;
WRAPPER_PLL_DIVSEL_FB_0 : integer := 5;
WRAPPER_PLL_DIVSEL_FB_1 : integer := 5;
WRAPPER_PLL_DIVSEL_REF_0 : integer := 2;
WRAPPER_PLL_DIVSEL_REF_1 : integer := 2;
WRAPPER_SIMULATION : integer := 0 -- Set to 1 for simulation
);
port
(
--_________________________________________________________________________
--_________________________________________________________________________
--TILE0 (X0_Y0)
------------------------ Loopback and Powerdown Ports ----------------------
TILE0_RXPOWERDOWN0_IN : in std_logic_vector(1 downto 0);
TILE0_RXPOWERDOWN1_IN : in std_logic_vector(1 downto 0);
TILE0_TXPOWERDOWN0_IN : in std_logic_vector(1 downto 0);
TILE0_TXPOWERDOWN1_IN : in std_logic_vector(1 downto 0);
--------------------------------- PLL Ports --------------------------------
TILE0_CLK00_IN : in std_logic;
TILE0_CLK01_IN : in std_logic;
TILE0_GTPRESET0_IN : in std_logic;
TILE0_GTPRESET1_IN : in std_logic;
TILE0_PLLLKDET0_OUT : out std_logic;
TILE0_PLLLKDET1_OUT : out std_logic;
TILE0_RESETDONE0_OUT : out std_logic;
TILE0_RESETDONE1_OUT : out std_logic;
----------------------- Receive Ports - 8b10b Decoder ----------------------
TILE0_RXCHARISK0_OUT : out std_logic_vector(1 downto 0);
TILE0_RXCHARISK1_OUT : out std_logic_vector(1 downto 0);
TILE0_RXDISPERR0_OUT : out std_logic_vector(1 downto 0);
TILE0_RXDISPERR1_OUT : out std_logic_vector(1 downto 0);
TILE0_RXNOTINTABLE0_OUT : out std_logic_vector(1 downto 0);
TILE0_RXNOTINTABLE1_OUT : out std_logic_vector(1 downto 0);
---------------------- Receive Ports - Clock Correction --------------------
TILE0_RXCLKCORCNT0_OUT : out std_logic_vector(2 downto 0);
TILE0_RXCLKCORCNT1_OUT : out std_logic_vector(2 downto 0);
--------------- Receive Ports - Comma Detection and Alignment --------------
TILE0_RXENMCOMMAALIGN0_IN : in std_logic;
TILE0_RXENMCOMMAALIGN1_IN : in std_logic;
TILE0_RXENPCOMMAALIGN0_IN : in std_logic;
TILE0_RXENPCOMMAALIGN1_IN : in std_logic;
------------------- Receive Ports - RX Data Path interface -----------------
TILE0_RXDATA0_OUT : out std_logic_vector(15 downto 0);
TILE0_RXDATA1_OUT : out std_logic_vector(15 downto 0);
TILE0_RXRESET0_IN : in std_logic;
TILE0_RXRESET1_IN : in std_logic;
TILE0_RXUSRCLK0_IN : in std_logic;
TILE0_RXUSRCLK1_IN : in std_logic;
TILE0_RXUSRCLK20_IN : in std_logic;
TILE0_RXUSRCLK21_IN : in std_logic;
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
TILE0_GATERXELECIDLE0_IN : in std_logic;
TILE0_GATERXELECIDLE1_IN : in std_logic;
TILE0_IGNORESIGDET0_IN : in std_logic;
TILE0_IGNORESIGDET1_IN : in std_logic;
TILE0_RXELECIDLE0_OUT : out std_logic;
TILE0_RXELECIDLE1_OUT : out std_logic;
TILE0_RXN0_IN : in std_logic;
TILE0_RXN1_IN : in std_logic;
TILE0_RXP0_IN : in std_logic;
TILE0_RXP1_IN : in std_logic;
----------- Receive Ports - RX Elastic Buffer and Phase Alignment ----------
TILE0_RXSTATUS0_OUT : out std_logic_vector(2 downto 0);
TILE0_RXSTATUS1_OUT : out std_logic_vector(2 downto 0);
-------------- Receive Ports - RX Pipe Control for PCI Express -------------
TILE0_PHYSTATUS0_OUT : out std_logic;
TILE0_PHYSTATUS1_OUT : out std_logic;
TILE0_RXVALID0_OUT : out std_logic;
TILE0_RXVALID1_OUT : out std_logic;
-------------------- Receive Ports - RX Polarity Control -------------------
TILE0_RXPOLARITY0_IN : in std_logic;
TILE0_RXPOLARITY1_IN : in std_logic;
---------------------------- TX/RX Datapath Ports --------------------------
TILE0_GTPCLKOUT0_OUT : out std_logic_vector(1 downto 0);
TILE0_GTPCLKOUT1_OUT : out std_logic_vector(1 downto 0);
------------------- Transmit Ports - 8b10b Encoder Control -----------------
TILE0_TXCHARDISPMODE0_IN : in std_logic_vector(1 downto 0);
TILE0_TXCHARDISPMODE1_IN : in std_logic_vector(1 downto 0);
TILE0_TXCHARISK0_IN : in std_logic_vector(1 downto 0);
TILE0_TXCHARISK1_IN : in std_logic_vector(1 downto 0);
------------------ Transmit Ports - TX Data Path interface -----------------
TILE0_TXDATA0_IN : in std_logic_vector(15 downto 0);
TILE0_TXDATA1_IN : in std_logic_vector(15 downto 0);
TILE0_TXUSRCLK0_IN : in std_logic;
TILE0_TXUSRCLK1_IN : in std_logic;
TILE0_TXUSRCLK20_IN : in std_logic;
TILE0_TXUSRCLK21_IN : in std_logic;
--------------- Transmit Ports - TX Driver and OOB signalling --------------
TILE0_TXN0_OUT : out std_logic;
TILE0_TXN1_OUT : out std_logic;
TILE0_TXP0_OUT : out std_logic;
TILE0_TXP1_OUT : out std_logic;
----------------- Transmit Ports - TX Ports for PCI Express ----------------
TILE0_TXDETECTRX0_IN : in std_logic;
TILE0_TXDETECTRX1_IN : in std_logic;
TILE0_TXELECIDLE0_IN : in std_logic;
TILE0_TXELECIDLE1_IN : in std_logic
);
end GTPA1_DUAL_WRAPPER;
architecture RTL of GTPA1_DUAL_WRAPPER is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of RTL : architecture is "GTPA1_DUAL_WRAPPER,s6_gtpwizard_v1_4,{gtp0_protocol_file=pcie,gtp1_protocol_file=Use_GTP0_settings}";
--***************************** Signal Declarations *****************************
-- ground and tied_to_vcc_i signals
signal tied_to_ground_i : std_logic;
signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
signal tied_to_vcc_i : std_logic;
signal tile0_plllkdet0_i : std_logic;
signal tile0_plllkdet1_i : std_logic;
signal tile0_plllkdet0_i2 : std_logic;
signal tile0_plllkdet1_i2 : std_logic;
--*************************** Component Declarations **************************
component GTPA1_DUAL_WRAPPER_TILE
generic
(
-- Simulation attributes
TILE_SIM_GTPRESET_SPEEDUP : integer := 0; -- Set to 1 to speed up sim reset
TILE_CLK25_DIVIDER_0 : integer := 4;
TILE_CLK25_DIVIDER_1 : integer := 4;
TILE_PLL_DIVSEL_FB_0 : integer := 5;
TILE_PLL_DIVSEL_FB_1 : integer := 5;
TILE_PLL_DIVSEL_REF_0 : integer := 2;
TILE_PLL_DIVSEL_REF_1 : integer := 2;
--
TILE_PLL_SOURCE_0 : string := "PLL0";
TILE_PLL_SOURCE_1 : string := "PLL1"
);
port
(
------------------------ Loopback and Powerdown Ports ----------------------
RXPOWERDOWN0_IN : in std_logic_vector(1 downto 0);
RXPOWERDOWN1_IN : in std_logic_vector(1 downto 0);
TXPOWERDOWN0_IN : in std_logic_vector(1 downto 0);
TXPOWERDOWN1_IN : in std_logic_vector(1 downto 0);
--------------------------------- PLL Ports --------------------------------
CLK00_IN : in std_logic;
CLK01_IN : in std_logic;
GTPRESET0_IN : in std_logic;
GTPRESET1_IN : in std_logic;
PLLLKDET0_OUT : out std_logic;
PLLLKDET1_OUT : out std_logic;
RESETDONE0_OUT : out std_logic;
RESETDONE1_OUT : out std_logic;
----------------------- Receive Ports - 8b10b Decoder ----------------------
RXCHARISK0_OUT : out std_logic_vector(1 downto 0);
RXCHARISK1_OUT : out std_logic_vector(1 downto 0);
RXDISPERR0_OUT : out std_logic_vector(1 downto 0);
RXDISPERR1_OUT : out std_logic_vector(1 downto 0);
RXNOTINTABLE0_OUT : out std_logic_vector(1 downto 0);
RXNOTINTABLE1_OUT : out std_logic_vector(1 downto 0);
---------------------- Receive Ports - Clock Correction --------------------
RXCLKCORCNT0_OUT : out std_logic_vector(2 downto 0);
RXCLKCORCNT1_OUT : out std_logic_vector(2 downto 0);
--------------- Receive Ports - Comma Detection and Alignment --------------
RXENMCOMMAALIGN0_IN : in std_logic;
RXENMCOMMAALIGN1_IN : in std_logic;
RXENPCOMMAALIGN0_IN : in std_logic;
RXENPCOMMAALIGN1_IN : in std_logic;
------------------- Receive Ports - RX Data Path interface -----------------
RXDATA0_OUT : out std_logic_vector(15 downto 0);
RXDATA1_OUT : out std_logic_vector(15 downto 0);
RXRESET0_IN : in std_logic;
RXRESET1_IN : in std_logic;
RXUSRCLK0_IN : in std_logic;
RXUSRCLK1_IN : in std_logic;
RXUSRCLK20_IN : in std_logic;
RXUSRCLK21_IN : in std_logic;
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
GATERXELECIDLE0_IN : in std_logic;
GATERXELECIDLE1_IN : in std_logic;
IGNORESIGDET0_IN : in std_logic;
IGNORESIGDET1_IN : in std_logic;
RXELECIDLE0_OUT : out std_logic;
RXELECIDLE1_OUT : out std_logic;
RXN0_IN : in std_logic;
RXN1_IN : in std_logic;
RXP0_IN : in std_logic;
RXP1_IN : in std_logic;
----------- Receive Ports - RX Elastic Buffer and Phase Alignment ----------
RXSTATUS0_OUT : out std_logic_vector(2 downto 0);
RXSTATUS1_OUT : out std_logic_vector(2 downto 0);
-------------- Receive Ports - RX Pipe Control for PCI Express -------------
PHYSTATUS0_OUT : out std_logic;
PHYSTATUS1_OUT : out std_logic;
RXVALID0_OUT : out std_logic;
RXVALID1_OUT : out std_logic;
-------------------- Receive Ports - RX Polarity Control -------------------
RXPOLARITY0_IN : in std_logic;
RXPOLARITY1_IN : in std_logic;
---------------------------- TX/RX Datapath Ports --------------------------
GTPCLKOUT0_OUT : out std_logic_vector(1 downto 0);
GTPCLKOUT1_OUT : out std_logic_vector(1 downto 0);
------------------- Transmit Ports - 8b10b Encoder Control -----------------
TXCHARDISPMODE0_IN : in std_logic_vector(1 downto 0);
TXCHARDISPMODE1_IN : in std_logic_vector(1 downto 0);
TXCHARISK0_IN : in std_logic_vector(1 downto 0);
TXCHARISK1_IN : in std_logic_vector(1 downto 0);
------------------ Transmit Ports - TX Data Path interface -----------------
TXDATA0_IN : in std_logic_vector(15 downto 0);
TXDATA1_IN : in std_logic_vector(15 downto 0);
TXUSRCLK0_IN : in std_logic;
TXUSRCLK1_IN : in std_logic;
TXUSRCLK20_IN : in std_logic;
TXUSRCLK21_IN : in std_logic;
--------------- Transmit Ports - TX Driver and OOB signalling --------------
TXN0_OUT : out std_logic;
TXN1_OUT : out std_logic;
TXP0_OUT : out std_logic;
TXP1_OUT : out std_logic;
----------------- Transmit Ports - TX Ports for PCI Express ----------------
TXDETECTRX0_IN : in std_logic;
TXDETECTRX1_IN : in std_logic;
TXELECIDLE0_IN : in std_logic;
TXELECIDLE1_IN : in std_logic
);
end component;
--********************************* Main Body of Code**************************
begin
tied_to_ground_i <= '0';
tied_to_ground_vec_i(63 downto 0) <= (others => '0');
tied_to_vcc_i <= '1';
simulation : if WRAPPER_SIMULATION = 1 generate
TILE0_PLLLKDET0_OUT <= tile0_plllkdet0_i2;
process
begin
wait until tile0_plllkdet0_i'event;
if(tile0_plllkdet0_i = '1') then
tile0_plllkdet0_i2 <= '1' after 100 ns;
else
tile0_plllkdet0_i2 <= tile0_plllkdet0_i;
end if;
end process;
TILE0_PLLLKDET1_OUT <= tile0_plllkdet1_i2;
process
begin
wait until tile0_plllkdet1_i'event;
if(tile0_plllkdet1_i = '1') then
tile0_plllkdet1_i2 <= '1' after 100 ns;
else
tile0_plllkdet1_i2 <= tile0_plllkdet1_i;
end if;
end process;
end generate simulation;
implementation : if WRAPPER_SIMULATION = 0 generate
TILE0_PLLLKDET0_OUT <= tile0_plllkdet0_i;
TILE0_PLLLKDET1_OUT <= tile0_plllkdet1_i;
end generate implementation;
--------------------------- Tile Instances -------------------------------
--_________________________________________________________________________
--_________________________________________________________________________
--TILE0 (X0_Y0)
tile0_gtpa1_dual_wrapper_i : GTPA1_DUAL_WRAPPER_TILE
generic map
(
-- Simulation attributes
TILE_SIM_GTPRESET_SPEEDUP => WRAPPER_SIM_GTPRESET_SPEEDUP,
TILE_CLK25_DIVIDER_0 => WRAPPER_CLK25_DIVIDER_0,
TILE_CLK25_DIVIDER_1 => WRAPPER_CLK25_DIVIDER_1,
TILE_PLL_DIVSEL_FB_0 => WRAPPER_PLL_DIVSEL_FB_0,
TILE_PLL_DIVSEL_FB_1 => WRAPPER_PLL_DIVSEL_FB_1,
TILE_PLL_DIVSEL_REF_0 => WRAPPER_PLL_DIVSEL_REF_0,
TILE_PLL_DIVSEL_REF_1 => WRAPPER_PLL_DIVSEL_REF_1,
--
TILE_PLL_SOURCE_0 => "PLL0",
TILE_PLL_SOURCE_1 => "PLL1"
)
port map
(
------------------------ Loopback and Powerdown Ports ----------------------
RXPOWERDOWN0_IN => TILE0_RXPOWERDOWN0_IN,
RXPOWERDOWN1_IN => TILE0_RXPOWERDOWN1_IN,
TXPOWERDOWN0_IN => TILE0_TXPOWERDOWN0_IN,
TXPOWERDOWN1_IN => TILE0_TXPOWERDOWN1_IN,
--------------------------------- PLL Ports --------------------------------
CLK00_IN => TILE0_CLK00_IN,
CLK01_IN => TILE0_CLK01_IN,
GTPRESET0_IN => TILE0_GTPRESET0_IN,
GTPRESET1_IN => TILE0_GTPRESET1_IN,
PLLLKDET0_OUT => tile0_plllkdet0_i,
PLLLKDET1_OUT => tile0_plllkdet1_i,
RESETDONE0_OUT => TILE0_RESETDONE0_OUT,
RESETDONE1_OUT => TILE0_RESETDONE1_OUT,
----------------------- Receive Ports - 8b10b Decoder ----------------------
RXCHARISK0_OUT => TILE0_RXCHARISK0_OUT,
RXCHARISK1_OUT => TILE0_RXCHARISK1_OUT,
RXDISPERR0_OUT => TILE0_RXDISPERR0_OUT,
RXDISPERR1_OUT => TILE0_RXDISPERR1_OUT,
RXNOTINTABLE0_OUT => TILE0_RXNOTINTABLE0_OUT,
RXNOTINTABLE1_OUT => TILE0_RXNOTINTABLE1_OUT,
---------------------- Receive Ports - Clock Correction --------------------
RXCLKCORCNT0_OUT => TILE0_RXCLKCORCNT0_OUT,
RXCLKCORCNT1_OUT => TILE0_RXCLKCORCNT1_OUT,
--------------- Receive Ports - Comma Detection and Alignment --------------
RXENMCOMMAALIGN0_IN => TILE0_RXENMCOMMAALIGN0_IN,
RXENMCOMMAALIGN1_IN => TILE0_RXENMCOMMAALIGN1_IN,
RXENPCOMMAALIGN0_IN => TILE0_RXENPCOMMAALIGN0_IN,
RXENPCOMMAALIGN1_IN => TILE0_RXENPCOMMAALIGN1_IN,
------------------- Receive Ports - RX Data Path interface -----------------
RXDATA0_OUT => TILE0_RXDATA0_OUT,
RXDATA1_OUT => TILE0_RXDATA1_OUT,
RXRESET0_IN => TILE0_RXRESET0_IN,
RXRESET1_IN => TILE0_RXRESET1_IN,
RXUSRCLK0_IN => TILE0_RXUSRCLK0_IN,
RXUSRCLK1_IN => TILE0_RXUSRCLK1_IN,
RXUSRCLK20_IN => TILE0_RXUSRCLK20_IN,
RXUSRCLK21_IN => TILE0_RXUSRCLK21_IN,
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
GATERXELECIDLE0_IN => TILE0_GATERXELECIDLE0_IN,
GATERXELECIDLE1_IN => TILE0_GATERXELECIDLE1_IN,
IGNORESIGDET0_IN => TILE0_IGNORESIGDET0_IN,
IGNORESIGDET1_IN => TILE0_IGNORESIGDET1_IN,
RXELECIDLE0_OUT => TILE0_RXELECIDLE0_OUT,
RXELECIDLE1_OUT => TILE0_RXELECIDLE1_OUT,
RXN0_IN => TILE0_RXN0_IN,
RXN1_IN => TILE0_RXN1_IN,
RXP0_IN => TILE0_RXP0_IN,
RXP1_IN => TILE0_RXP1_IN,
----------- Receive Ports - RX Elastic Buffer and Phase Alignment ----------
RXSTATUS0_OUT => TILE0_RXSTATUS0_OUT,
RXSTATUS1_OUT => TILE0_RXSTATUS1_OUT,
-------------- Receive Ports - RX Pipe Control for PCI Express -------------
PHYSTATUS0_OUT => TILE0_PHYSTATUS0_OUT,
PHYSTATUS1_OUT => TILE0_PHYSTATUS1_OUT,
RXVALID0_OUT => TILE0_RXVALID0_OUT,
RXVALID1_OUT => TILE0_RXVALID1_OUT,
-------------------- Receive Ports - RX Polarity Control -------------------
RXPOLARITY0_IN => TILE0_RXPOLARITY0_IN,
RXPOLARITY1_IN => TILE0_RXPOLARITY1_IN,
---------------------------- TX/RX Datapath Ports --------------------------
GTPCLKOUT0_OUT => TILE0_GTPCLKOUT0_OUT,
GTPCLKOUT1_OUT => TILE0_GTPCLKOUT1_OUT,
------------------- Transmit Ports - 8b10b Encoder Control -----------------
TXCHARDISPMODE0_IN => TILE0_TXCHARDISPMODE0_IN,
TXCHARDISPMODE1_IN => TILE0_TXCHARDISPMODE1_IN,
TXCHARISK0_IN => TILE0_TXCHARISK0_IN,
TXCHARISK1_IN => TILE0_TXCHARISK1_IN,
------------------ Transmit Ports - TX Data Path interface -----------------
TXDATA0_IN => TILE0_TXDATA0_IN,
TXDATA1_IN => TILE0_TXDATA1_IN,
TXUSRCLK0_IN => TILE0_TXUSRCLK0_IN,
TXUSRCLK1_IN => TILE0_TXUSRCLK1_IN,
TXUSRCLK20_IN => TILE0_TXUSRCLK20_IN,
TXUSRCLK21_IN => TILE0_TXUSRCLK21_IN,
--------------- Transmit Ports - TX Driver and OOB signalling --------------
TXN0_OUT => TILE0_TXN0_OUT,
TXN1_OUT => TILE0_TXN1_OUT,
TXP0_OUT => TILE0_TXP0_OUT,
TXP1_OUT => TILE0_TXP1_OUT,
----------------- Transmit Ports - TX Ports for PCI Express ----------------
TXDETECTRX0_IN => TILE0_TXDETECTRX0_IN,
TXDETECTRX1_IN => TILE0_TXDETECTRX1_IN,
TXELECIDLE0_IN => TILE0_TXELECIDLE0_IN,
TXELECIDLE1_IN => TILE0_TXELECIDLE1_IN
);
end RTL;
| gpl-3.0 | b41903a3f2e25ef84e3fd662e8b0d605 | 0.454556 | 4.229126 | false | false | false | false |
masaruohashi/tic-tac-toe | interface_jogo/unidade_controle_interface_jogo.vhd | 1 | 4,958 | -- VHDL da Unidade de Controle da interface jogo da velha
library ieee;
use ieee.std_logic_1164.all;
entity unidade_controle_interface_jogo is
port(
clock : in std_logic;
reset : in std_logic;
start : in std_logic;
jogador : in std_logic; -- indica se o jogador é o primeiro a jogar ou o segundo
fim_impressao : in std_logic; -- indica que o tabuleiro terminou de ser impresso
fim_recepcao : in std_logic; -- indica que um caractere terminou de ser recebido
fim_transmissao : in std_logic; -- indica que um caractere terminou de ser eniado para a outra bancada
fim_jogo : in std_logic; -- indica que o jogo acabou
liga_modem : out std_logic; -- indica que a interface do modem deve ser ligada
imprime_tabuleiro : out std_logic; -- habilita a impressao do tabuleiro
envia_jogada : out std_logic; -- habilita o envio da jogada para a outra bancada
recebe_dado : out std_logic; -- habilita a recepção de um caractere do terminal
jogador_atual : out std_logic; -- indica o jogador atual do jogo da velha
dep_estados : out std_logic_vector(2 downto 0)
);
end unidade_controle_interface_jogo;
architecture comportamental of unidade_controle_interface_jogo is
type tipo_estado is (inicial, imprime_oponente, recebe_jogador, envia_caractere, imprime_jogador, recebe_oponente, imprime_final, final);
signal estado : tipo_estado;
begin
process (clock, estado, reset)
begin
if reset = '1' then
estado <= inicial;
elsif (clock'event and clock = '1') then
case estado is
when inicial => -- Aguarda sinal de start
if start = '1' then
if jogador='0' then
estado <= imprime_oponente;
else
estado <= imprime_jogador;
end if;
else
estado <= inicial;
end if;
when imprime_oponente => -- Imprime o tabuleiro no terminal
if fim_impressao = '1' then
estado <= recebe_jogador;
else
estado <= imprime_oponente;
end if;
when recebe_jogador => -- Espera o dado ser recebido do terminal
if fim_recepcao = '1' then
estado <= envia_caractere;
elsif fim_jogo = '1' then
estado <= imprime_final;
else
estado <= recebe_jogador;
end if;
when envia_caractere =>
if fim_transmissao = '1' then
estado <= imprime_jogador;
else
estado <= envia_caractere;
end if;
when imprime_jogador => -- Imprime o tabuleiro no terminal
if fim_impressao = '1' then
estado <= recebe_oponente;
else
estado <= imprime_jogador;
end if;
when recebe_oponente => -- Espera o dado ser recebido da outra bancada
if fim_recepcao = '1' then
estado <= imprime_oponente;
elsif fim_jogo = '1' then
estado <= imprime_final;
else
estado <= recebe_oponente;
end if;
when imprime_final => -- Imprime o tabuleiro no terminal
if fim_impressao = '1' then
estado <= final;
else
estado <= imprime_final;
end if;
when final =>
estado <= final;
when others => -- Default
estado <= inicial;
end case;
end if;
end process;
-- logica de saída
with estado select
imprime_tabuleiro <= '1' when imprime_oponente | imprime_jogador | imprime_final,
'0' when others;
with estado select
recebe_dado <= '1' when recebe_jogador | recebe_oponente,
'0' when others;
with estado select
envia_jogada <= '1' when envia_caractere,
'0' when others;
with estado select
jogador_atual <= '1' when imprime_oponente | recebe_oponente,
'0' when others;
with estado select
liga_modem <= '1' when envia_caractere | recebe_oponente,
'0' when others;
process (estado)
begin
case estado is
when inicial =>
dep_estados <= "000";
when imprime_oponente =>
dep_estados <= "001";
when recebe_jogador =>
dep_estados <= "010";
when envia_caractere =>
dep_estados <= "011";
when imprime_jogador =>
dep_estados <= "100";
when recebe_oponente =>
dep_estados <= "101";
when imprime_final =>
dep_estados <= "110";
when final =>
dep_estados <= "111";
when others =>
null;
end case;
end process;
end comportamental;
| mit | f1995229d59a3cdbea5dc37e80e8b23b | 0.546831 | 3.979116 | false | false | false | false |
timofonic/PHDL | misc/projects/spartan_pcie_board/fpga/lx45t_pinout/ipcore_dir/pcie_core/simulation/dsport/gtx_tx_sync_rate_v6.vhd | 1 | 18,407 | -------------------------------------------------------------------------------
--
-- (c) Copyright 2008, 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Project : Spartan-6 Integrated Block for PCI Express
-- File : gtx_tx_sync_rate_v6.vhd
--
-- Module TX_SYNC
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- Module TX_SYNC
entity GTX_TX_SYNC_RATE_V6 is
generic (
C_SIMULATION : integer := 0 -- Set to 1 for simulation
);
port (
ENPMAPHASEALIGN : out std_logic;
PMASETPHASE : out std_logic;
SYNC_DONE : out std_logic;
OUT_DIV_RESET : out std_logic;
PCS_RESET : out std_logic;
USER_PHYSTATUS : out std_logic;
TXALIGNDISABLE : out std_logic;
DELAYALIGNRESET : out std_logic;
USER_CLK : in std_logic;
RESET : in std_logic;
RATE : in std_logic;
RATEDONE : in std_logic;
GT_PHYSTATUS : in std_logic;
RESETDONE : in std_logic
);
end GTX_TX_SYNC_RATE_V6;
architecture v6_pcie of GTX_TX_SYNC_RATE_V6 is
constant TCQ : integer := 1;
FUNCTION to_stdlogic (
in_val : IN boolean) RETURN std_logic IS
BEGIN
IF (in_val) THEN
RETURN('1');
ELSE
RETURN('0');
END IF;
END to_stdlogic;
constant IDLE : std_logic_vector(21 downto 0) := "0000000000000000000001";
constant PHASEALIGN : std_logic_vector(21 downto 0) := "0000000000000000000010";
constant RATECHANGE_DIVRESET : std_logic_vector(21 downto 0) := "0000000000000000000100";
constant RATECHANGE_DIVRESET_POST : std_logic_vector(21 downto 0) := "0000000000000000001000";
constant RATECHANGE_ENPMADISABLE : std_logic_vector(21 downto 0) := "0000000000000000010000";
constant RATECHANGE_ENPMADISABLE_POST : std_logic_vector(21 downto 0) := "0000000000000000100000";
constant RATECHANGE_PMARESET : std_logic_vector(21 downto 0) := "0000000000000001000000";
constant RATECHANGE_IDLE : std_logic_vector(21 downto 0) := "0000000000000010000000";
constant RATECHANGE_PCSRESET : std_logic_vector(21 downto 0) := "0000000000000100000000";
constant RATECHANGE_PCSRESET_POST : std_logic_vector(21 downto 0) := "0000000000001000000000";
constant RATECHANGE_ASSERTPHY : std_logic_vector(21 downto 0) := "0000000000010000000000";
constant RESET_STATE : std_logic_vector(21 downto 0) := "0000000000100000000000";
constant WAIT_PHYSTATUS : std_logic_vector(21 downto 0) := "0000000010000000000000";
constant RATECHANGE_PMARESET_POST : std_logic_vector(21 downto 0) := "0000000100000000000000";
constant RATECHANGE_DISABLEPHASE : std_logic_vector(21 downto 0) := "0000001000000000000000";
constant DELAYALIGNRST : std_logic_vector(21 downto 0) := "0000010000000000000000";
constant SETENPMAPHASEALIGN : std_logic_vector(21 downto 0) := "0000100000000000000000";
constant TXALIGNDISABLEDEASSERT : std_logic_vector(21 downto 0) := "0001000000000000000000";
constant RATECHANGE_TXDLYALIGNDISABLE : std_logic_vector(21 downto 0) := "0010000000000000000000";
constant OUTDIVRESET : std_logic_vector(21 downto 0) := "0100000000000000000000";
constant RATECHANGE_DISABLE_TXALIGNDISABLE : std_logic_vector(21 downto 0) := "1000000000000000000000";
function s_idx(
constant C_SIMULATION : integer)
return integer is
variable sidx_out : integer := 8;
begin -- s_idx
if (C_SIMULATION /= 0) then
sidx_out := 0;
else
sidx_out := 2;
end if;
return sidx_out;
end s_idx;
function pma_idx(
constant C_SIMULATION : integer)
return integer is
variable pma_idx_out : integer := 8;
begin -- pma_idx
if (C_SIMULATION /= 0) then
pma_idx_out := 0;
else
pma_idx_out := 7;
end if;
return pma_idx_out;
end pma_idx;
constant SYNC_IDX : integer := s_idx(C_SIMULATION);
constant PMARESET_IDX : integer := pma_idx(C_SIMULATION);
signal ENPMAPHASEALIGN_c : std_logic;
signal PMASETPHASE_c : std_logic;
signal SYNC_DONE_c : std_logic;
signal OUT_DIV_RESET_c : std_logic;
signal PCS_RESET_c : std_logic;
signal USER_PHYSTATUS_c : std_logic;
signal DELAYALIGNRESET_c : std_logic;
signal TXALIGNDISABLE_c : std_logic;
signal state : std_logic_vector(21 downto 0);
signal nextstate : std_logic_vector(21 downto 0);
signal wait_amt : std_logic_vector(15 downto 0);
signal wait_c : std_logic_vector(15 downto 0);
signal waitcounter : std_logic_vector(7 downto 0);
signal nextwaitcounter : std_logic_vector(7 downto 0);
signal waitcounter2 : std_logic_vector(7 downto 0);
signal waitcounter2_check : std_logic_vector(7 downto 0);
signal nextwaitcounter2 : std_logic_vector(7 downto 0);
signal ratedone_r : std_logic;
signal ratedone_r2 : std_logic;
signal ratedone_pulse_i : std_logic;
signal gt_phystatus_q : std_logic;
-- Declare intermediate signals for referenced outputs
signal state_v6pcie0 : std_logic_vector(4 downto 0);
-- signal waitcounter_v6pcie1 : std_logic_vector(16 downto 0);
begin
-- Drive referenced outputs
-- state <= state_v6pcie0;
-- waitcounter <= waitcounter_v6pcie1;
process (USER_CLK)
begin
if (USER_CLK'event and USER_CLK = '1') then
if (RESET = '1') then
state <= RESET_STATE after (TCQ)*1 ps;
waitcounter <= X"00" after (TCQ)*1 ps;
waitcounter2 <= X"00" after (TCQ)*1 ps;
USER_PHYSTATUS <= GT_PHYSTATUS after (TCQ)*1 ps;
SYNC_DONE <= '0' after (TCQ)*1 ps;
ENPMAPHASEALIGN <= '0' after (TCQ)*1 ps;
PMASETPHASE <= '0' after (TCQ)*1 ps;
OUT_DIV_RESET <= '0' after (TCQ)*1 ps;
PCS_RESET <= '0' after (TCQ)*1 ps;
DELAYALIGNRESET <= '0' after (TCQ)*1 ps;
TXALIGNDISABLE <= '1' after (TCQ)*1 ps;
else
state <= nextstate after (TCQ)*1 ps;
waitcounter <= nextwaitcounter after (TCQ)*1 ps;
waitcounter2 <= nextwaitcounter2 after (TCQ)*1 ps;
USER_PHYSTATUS <= USER_PHYSTATUS_c after (TCQ)*1 ps;
SYNC_DONE <= SYNC_DONE_c after (TCQ)*1 ps;
ENPMAPHASEALIGN <= ENPMAPHASEALIGN_c after (TCQ)*1 ps;
PMASETPHASE <= PMASETPHASE_c after (TCQ)*1 ps;
OUT_DIV_RESET <= OUT_DIV_RESET_c after (TCQ)*1 ps;
PCS_RESET <= PCS_RESET_c after (TCQ)*1 ps;
DELAYALIGNRESET <= DELAYALIGNRESET_c after (TCQ)*1 ps;
TXALIGNDISABLE <= TXALIGNDISABLE_c after (TCQ)*1 ps;
end if;
end if;
end process;
waitcounter2_check <= waitcounter2 + X"01" when (waitcounter = X"FF") else
waitcounter2;
process (state, GT_PHYSTATUS, waitcounter, waitcounter2, waitcounter2_check, ratedone_pulse_i, gt_phystatus_q, RESETDONE)
begin
-- DEFAULT CONDITIONS
DELAYALIGNRESET_c <= '0';
SYNC_DONE_c <= '0';
ENPMAPHASEALIGN_c <= '1';
PMASETPHASE_c <= '0';
OUT_DIV_RESET_c <= '0';
PCS_RESET_c <= '0';
TXALIGNDISABLE_c <= '0';
nextstate <= state;
USER_PHYSTATUS_c <= GT_PHYSTATUS;
nextwaitcounter <= waitcounter + X"01";
nextwaitcounter2 <= waitcounter2_check;
case state is
-- START IN RESET
when RESET_STATE =>
TXALIGNDISABLE_c <= '1';
ENPMAPHASEALIGN_c <= '0';
nextstate <= OUTDIVRESET;
nextwaitcounter <= X"00";
nextwaitcounter2 <= X"00";
-- Assert OUTDIVRESET
when OUTDIVRESET =>
OUT_DIV_RESET_c <= '1';
TXALIGNDISABLE_c <= '1';
ENPMAPHASEALIGN_c <= '0';
if ((waitcounter2(4)) = '1') then
nextstate <= DELAYALIGNRST;
nextwaitcounter <= X"00";
nextwaitcounter2 <= X"00";
end if;
-- ASSERT TXDLYALIGNRESET FOR 16 CLOCK CYCLES
when DELAYALIGNRST =>
DELAYALIGNRESET_c <= '1';
ENPMAPHASEALIGN_c <= '0';
TXALIGNDISABLE_c <= '1';
if ((waitcounter(4)) = '1') then
nextstate <= SETENPMAPHASEALIGN;
nextwaitcounter <= X"00";
nextwaitcounter2 <= X"00";
end if;
-- ASSERT ENPMAPHASEALIGN FOR 32 CLOCK CYCLES
when SETENPMAPHASEALIGN =>
TXALIGNDISABLE_c <= '1';
if ((waitcounter(5)) = '1') then
nextstate <= PHASEALIGN;
nextwaitcounter <= X"00";
nextwaitcounter2 <= X"00";
end if;
-- ASSERT PMASETPHASE OUT OF RESET for 32K CYCLES
when PHASEALIGN =>
PMASETPHASE_c <= '1';
TXALIGNDISABLE_c <= '1';
if ((waitcounter2(PMARESET_IDX)) = '1') then
nextstate <= TXALIGNDISABLEDEASSERT;
nextwaitcounter <= X"00";
nextwaitcounter2 <= X"00";
end if;
-- KEEP TXALIGNDISABLE ASSERTED for 64 CYCLES
when TXALIGNDISABLEDEASSERT =>
TXALIGNDISABLE_c <= '1';
if ((waitcounter(6)) = '1') then
nextwaitcounter <= X"00";
nextstate <= IDLE;
nextwaitcounter2 <= X"00";
end if;
-- NOW IN IDLE, ASSERT SYNC DONE, WAIT FOR RATECHANGE
when IDLE =>
SYNC_DONE_c <= '1';
if (ratedone_pulse_i = '1') then
USER_PHYSTATUS_c <= '0';
nextstate <= WAIT_PHYSTATUS;
nextwaitcounter <= X"00";
nextwaitcounter2 <= X"00";
end if;
-- WAIT FOR PHYSTATUS
when WAIT_PHYSTATUS =>
USER_PHYSTATUS_c <= '0';
if (gt_phystatus_q = '1') then
nextstate <= RATECHANGE_IDLE;
nextwaitcounter <= X"00";
nextwaitcounter2 <= X"00";
end if;
-- WAIT 64 CYCLES BEFORE WE START THE RATE CHANGE
when RATECHANGE_IDLE =>
USER_PHYSTATUS_c <= '0';
if ((waitcounter(6)) = '1') then
nextstate <= RATECHANGE_TXDLYALIGNDISABLE;
nextwaitcounter <= X"00";
nextwaitcounter2 <= X"00";
end if;
-- ASSERT TXALIGNDISABLE FOR 32 CYCLES
when RATECHANGE_TXDLYALIGNDISABLE =>
USER_PHYSTATUS_c <= '0';
TXALIGNDISABLE_c <= '1';
if ((waitcounter(5)) = '1') then
nextstate <= RATECHANGE_DIVRESET;
nextwaitcounter <= X"00";
nextwaitcounter2 <= X"00";
end if;
-- ASSERT DIV RESET FOR 16 CLOCK CYCLES
when RATECHANGE_DIVRESET =>
OUT_DIV_RESET_c <= '1';
USER_PHYSTATUS_c <= '0';
TXALIGNDISABLE_c <= '1';
if ((waitcounter(4)) = '1') then
nextstate <= RATECHANGE_DIVRESET_POST;
nextwaitcounter <= X"00";
nextwaitcounter2 <= X"00";
end if;
-- WAIT FOR 32 CLOCK CYCLES BEFORE NEXT STEP
when RATECHANGE_DIVRESET_POST =>
USER_PHYSTATUS_c <= '0';
TXALIGNDISABLE_c <= '1';
if ((waitcounter(5)) = '1') then
nextstate <= RATECHANGE_PMARESET;
nextwaitcounter <= X"00";
nextwaitcounter2 <= X"00";
end if;
-- ASSERT PMA RESET FOR 32K CYCLES
when RATECHANGE_PMARESET =>
PMASETPHASE_c <= '1';
USER_PHYSTATUS_c <= '0';
TXALIGNDISABLE_c <= '1';
if ((waitcounter2(PMARESET_IDX)) = '1') then
nextstate <= RATECHANGE_PMARESET_POST;
nextwaitcounter <= X"00";
nextwaitcounter2 <= X"00";
end if;
-- WAIT FOR 32 CYCLES BEFORE DISABLING TXALIGNDISABLE
when RATECHANGE_PMARESET_POST =>
USER_PHYSTATUS_c <= '0';
TXALIGNDISABLE_c <= '1';
if ((waitcounter(5)) = '1') then
nextstate <= RATECHANGE_DISABLE_TXALIGNDISABLE;
nextwaitcounter <= X"00";
nextwaitcounter2 <= X"00";
end if;
-- DISABLE TXALIGNDISABLE FOR 32 CYCLES
when RATECHANGE_DISABLE_TXALIGNDISABLE =>
USER_PHYSTATUS_c <= '0';
if ((waitcounter(5)) = '1') then
nextstate <= RATECHANGE_PCSRESET;
nextwaitcounter <= X"00";
nextwaitcounter2 <= X"00";
end if;
-- NOW ASSERT PCS RESET FOR 32 CYCLES
when RATECHANGE_PCSRESET =>
PCS_RESET_c <= '1';
USER_PHYSTATUS_c <= '0';
if ((waitcounter(5)) = '1') then
nextstate <= RATECHANGE_PCSRESET_POST;
nextwaitcounter <= X"00";
nextwaitcounter2 <= X"00";
end if;
-- WAIT FOR RESETDONE BEFORE ASSERTING PHY_STATUS_OUT
when RATECHANGE_PCSRESET_POST =>
USER_PHYSTATUS_c <= '0';
if (RESETDONE = '1') then
nextstate <= RATECHANGE_ASSERTPHY;
end if;
-- ASSERT PHYSTATUSOUT MEANING RATECHANGE IS DONE AND GO BACK TO IDLE
when RATECHANGE_ASSERTPHY =>
USER_PHYSTATUS_c <= '1';
nextstate <= IDLE;
when others =>
nextstate <= IDLE;
end case;
end process;
-- Generate Ratechange Pulse
process (USER_CLK)
begin
if (USER_CLK'event and USER_CLK = '1') then
if (RESET = '1') then
ratedone_r <= '0' after (TCQ)*1 ps;
ratedone_r2 <= '0' after (TCQ)*1 ps;
gt_phystatus_q <= '0' after (TCQ)*1 ps;
else
ratedone_r <= RATE after (TCQ)*1 ps;
ratedone_r2 <= ratedone_r after (TCQ)*1 ps;
gt_phystatus_q <= GT_PHYSTATUS after (TCQ)*1 ps;
end if;
end if;
end process;
ratedone_pulse_i <= to_stdlogic((ratedone_r /= ratedone_r2));
end v6_pcie;
| gpl-3.0 | 49093bbf0509505616b762df96009854 | 0.520074 | 4.295683 | false | false | false | false |
timofonic/PHDL | misc/projects/spartan_pcie_board/fpga/lx45t_pinout/ipcore_dir/ddr3_controller/user_design/sim/memc3_tb_top.vhd | 2 | 21,803 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.9
-- \ \ Application : MIG
-- / / Filename : memc3_tb_top.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:59 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : This is top level module for test bench. which instantiates
-- init_mem_pattern_ctr and mcb_traffic_gen modules for each user
-- port.
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity memc3_tb_top is
generic
(
C_P0_MASK_SIZE : integer := 4;
C_P0_DATA_PORT_SIZE : integer := 32;
C_P1_MASK_SIZE : integer := 4;
C_P1_DATA_PORT_SIZE : integer := 32;
C_MEM_BURST_LEN : integer := 8;
C_SIMULATION : string := "FALSE";
C_MEM_NUM_COL_BITS : integer := 11;
C_NUM_DQ_PINS : integer := 8;
C_SMALL_DEVICE : string := "FALSE";
C_p0_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000100";
C_p0_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
C_p0_END_ADDRESS : std_logic_vector(31 downto 0) := X"000002ff";
C_p0_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffffc00";
C_p0_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000100"
);
port
(
clk0 : in std_logic;
rst0 : in std_logic;
calib_done : in std_logic;
p0_mcb_cmd_en_o : out std_logic;
p0_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p0_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p0_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p0_mcb_cmd_full_i : in std_logic;
p0_mcb_wr_en_o : out std_logic;
p0_mcb_wr_mask_o : out std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
p0_mcb_wr_data_o : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_mcb_wr_full_i : in std_logic;
p0_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
p0_mcb_rd_en_o : out std_logic;
p0_mcb_rd_data_i : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_mcb_rd_empty_i : in std_logic;
p0_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
vio_modify_enable : in std_logic;
vio_data_mode_value : in std_logic_vector(2 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
cmp_error : out std_logic;
cmp_data : out std_logic_vector(31 downto 0);
cmp_data_valid : out std_logic;
error : out std_logic;
error_status : out std_logic_vector(127 downto 0)
);
end memc3_tb_top;
architecture arc of memc3_tb_top is
function ERROR_DQWIDTH (val_i : integer) return integer is
begin
if (val_i = 4) then
return 1;
else
return val_i/8;
end if;
end function ERROR_DQWIDTH;
constant DQ_ERROR_WIDTH : integer := ERROR_DQWIDTH(C_NUM_DQ_PINS);
component init_mem_pattern_ctr IS
generic (
FAMILY : string;
BEGIN_ADDRESS : std_logic_vector(31 downto 0);
END_ADDRESS : std_logic_vector(31 downto 0);
DWIDTH : integer;
CMD_SEED_VALUE : std_logic_vector(31 downto 0);
DATA_SEED_VALUE : std_logic_vector(31 downto 0);
DATA_MODE : std_logic_vector(3 downto 0);
PORT_MODE : string
);
PORT (
clk_i : in std_logic;
rst_i : in std_logic;
mcb_cmd_bl_i : in std_logic_vector(5 downto 0);
mcb_cmd_en_i : in std_logic;
mcb_cmd_instr_i : in std_logic_vector(2 downto 0);
mcb_init_done_i : in std_logic;
mcb_wr_en_i : in std_logic;
vio_modify_enable : in std_logic;
vio_data_mode_value : in std_logic_vector(2 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
vio_bl_mode_value : in STD_LOGIC_VECTOR(1 downto 0);
vio_fixed_bl_value : in STD_LOGIC_VECTOR(5 downto 0);
cmp_error : in std_logic;
run_traffic_o : out std_logic;
start_addr_o : out std_logic_vector(31 downto 0);
end_addr_o : out std_logic_vector(31 downto 0);
cmd_seed_o : out std_logic_vector(31 downto 0);
data_seed_o : out std_logic_vector(31 downto 0);
load_seed_o : out std_logic;
addr_mode_o : out std_logic_vector(2 downto 0);
instr_mode_o : out std_logic_vector(3 downto 0);
bl_mode_o : out std_logic_vector(1 downto 0);
data_mode_o : out std_logic_vector(3 downto 0);
mode_load_o : out std_logic;
fixed_bl_o : out std_logic_vector(5 downto 0);
fixed_instr_o : out std_logic_vector(2 downto 0);
fixed_addr_o : out std_logic_vector(31 downto 0)
);
end component;
component mcb_traffic_gen is
generic (
FAMILY : string;
SIMULATION : string;
MEM_BURST_LEN : integer;
PORT_MODE : string;
DATA_PATTERN : string;
CMD_PATTERN : string;
ADDR_WIDTH : integer;
CMP_DATA_PIPE_STAGES : integer;
MEM_COL_WIDTH : integer;
NUM_DQ_PINS : integer;
DQ_ERROR_WIDTH : integer;
DWIDTH : integer;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0);
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0);
PRBS_EADDR : std_logic_vector(31 downto 0);
PRBS_SADDR : std_logic_vector(31 downto 0)
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
run_traffic_i : in std_logic;
manual_clear_error : in std_logic;
-- *** runtime parameter ***
start_addr_i : in std_logic_vector(31 downto 0);
end_addr_i : in std_logic_vector(31 downto 0);
cmd_seed_i : in std_logic_vector(31 downto 0);
data_seed_i : in std_logic_vector(31 downto 0);
load_seed_i : in std_logic;
addr_mode_i : in std_logic_vector(2 downto 0);
instr_mode_i : in std_logic_vector(3 downto 0);
bl_mode_i : in std_logic_vector(1 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
mode_load_i : in std_logic;
-- fixed pattern inputs interface
fixed_bl_i : in std_logic_vector(5 downto 0);
fixed_instr_i : in std_logic_vector(2 downto 0);
fixed_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : IN STD_LOGIC_VECTOR(DWIDTH-1 DOWNTO 0);
bram_cmd_i : in std_logic_vector(38 downto 0);
bram_valid_i : in std_logic;
bram_rdy_o : out std_logic;
--///////////////////////////////////////////////////////////////////////////
-- MCB INTERFACE
-- interface to mcb command port
mcb_cmd_en_o : out std_logic;
mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
mcb_cmd_addr_o : out std_logic_vector(ADDR_WIDTH - 1 downto 0);
mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
mcb_cmd_full_i : in std_logic;
-- interface to mcb wr data port
mcb_wr_en_o : out std_logic;
mcb_wr_data_o : out std_logic_vector(DWIDTH - 1 downto 0);
mcb_wr_mask_o : out std_logic_vector((DWIDTH / 8) - 1 downto 0);
mcb_wr_data_end_o : OUT std_logic;
mcb_wr_full_i : in std_logic;
mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
-- interface to mcb rd data port
mcb_rd_en_o : out std_logic;
mcb_rd_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
mcb_rd_empty_i : in std_logic;
mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
--///////////////////////////////////////////////////////////////////////////
-- status feedback
counts_rst : in std_logic;
wr_data_counts : out std_logic_vector(47 downto 0);
rd_data_counts : out std_logic_vector(47 downto 0);
cmp_data : out std_logic_vector(DWIDTH - 1 downto 0);
cmp_data_valid : out std_logic;
cmp_error : out std_logic;
error : out std_logic;
error_status : out std_logic_vector(64 + (2 * DWIDTH - 1) downto 0);
mem_rd_data : out std_logic_vector(DWIDTH - 1 downto 0);
dq_error_bytelane_cmp : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
cumlative_dq_lane_error : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0)
);
end component;
-- Function to determine the number of data patterns to be generated
function DATA_PATTERN_CALC return string is
begin
if (C_SMALL_DEVICE = "FALSE") then
return "DGEN_ALL";
else
return "DGEN_ADDR";
end if;
end function;
constant FAMILY : string := "SPARTAN6";
constant DATA_PATTERN : string := DATA_PATTERN_CALC;
constant CMD_PATTERN : string := "CGEN_ALL";
constant ADDR_WIDTH : integer := 30;
constant CMP_DATA_PIPE_STAGES : integer := 0;
constant PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00007000";
constant PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFF8000";
constant PRBS_SADDR : std_logic_vector(31 downto 0) := X"00005000";
constant PRBS_EADDR : std_logic_vector(31 downto 0) := X"00007fff";
constant BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000000";
constant END_ADDRESS : std_logic_vector(31 downto 0) := X"00000fff";
constant DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant p0_DWIDTH : integer := 32;
constant p0_PORT_MODE : string := "BI_MODE";
--p0 Signal declarations
signal p0_tg_run_traffic : std_logic;
signal p0_tg_start_addr : std_logic_vector(31 downto 0);
signal p0_tg_end_addr : std_logic_vector(31 downto 0);
signal p0_tg_cmd_seed : std_logic_vector(31 downto 0);
signal p0_tg_data_seed : std_logic_vector(31 downto 0);
signal p0_tg_load_seed : std_logic;
signal p0_tg_addr_mode : std_logic_vector(2 downto 0);
signal p0_tg_instr_mode : std_logic_vector(3 downto 0);
signal p0_tg_bl_mode : std_logic_vector(1 downto 0);
signal p0_tg_data_mode : std_logic_vector(3 downto 0);
signal p0_tg_mode_load : std_logic;
signal p0_tg_fixed_bl : std_logic_vector(5 downto 0);
signal p0_tg_fixed_instr : std_logic_vector(2 downto 0);
signal p0_tg_fixed_addr : std_logic_vector(31 downto 0);
signal p0_error_status : std_logic_vector(64 + (2*p0_DWIDTH - 1) downto 0);
signal p0_error : std_logic;
signal p0_cmp_error : std_logic;
signal p0_cmp_data : std_logic_vector(p0_DWIDTH-1 downto 0);
signal p0_cmp_data_valid : std_logic;
signal p0_mcb_cmd_en_o_int : std_logic;
signal p0_mcb_cmd_instr_o_int : std_logic_vector(2 downto 0);
signal p0_mcb_cmd_bl_o_int : std_logic_vector(5 downto 0);
signal p0_mcb_cmd_addr_o_int : std_logic_vector(29 downto 0);
signal p0_mcb_wr_en_o_int : std_logic;
--signal cmp_data : std_logic_vector(31 downto 0);
begin
cmp_error <= p0_cmp_error;
error <= p0_error;
error_status <= p0_error_status;
cmp_data <= p0_cmp_data(31 downto 0);
cmp_data_valid <= p0_cmp_data_valid;
p0_mcb_cmd_en_o <= p0_mcb_cmd_en_o_int;
p0_mcb_cmd_instr_o <= p0_mcb_cmd_instr_o_int;
p0_mcb_cmd_bl_o <= p0_mcb_cmd_bl_o_int;
p0_mcb_cmd_addr_o <= p0_mcb_cmd_addr_o_int;
p0_mcb_wr_en_o <= p0_mcb_wr_en_o_int;
init_mem_pattern_ctr_p0 :init_mem_pattern_ctr
generic map
(
DWIDTH => p0_DWIDTH,
FAMILY => FAMILY,
BEGIN_ADDRESS => C_p0_BEGIN_ADDRESS,
END_ADDRESS => C_p0_END_ADDRESS,
CMD_SEED_VALUE => X"56456783",
DATA_SEED_VALUE => X"12345678",
DATA_MODE => C_p0_DATA_MODE,
PORT_MODE => p0_PORT_MODE
)
port map
(
clk_i => clk0,
rst_i => rst0,
mcb_cmd_en_i => p0_mcb_cmd_en_o_int,
mcb_cmd_instr_i => p0_mcb_cmd_instr_o_int,
mcb_cmd_bl_i => p0_mcb_cmd_bl_o_int,
mcb_wr_en_i => p0_mcb_wr_en_o_int,
vio_modify_enable => vio_modify_enable,
vio_data_mode_value => vio_data_mode_value,
vio_addr_mode_value => vio_addr_mode_value,
vio_bl_mode_value => "10",--vio_bl_mode_value,
vio_fixed_bl_value => "000000",--vio_fixed_bl_value,
mcb_init_done_i => calib_done,
cmp_error => p0_error,
run_traffic_o => p0_tg_run_traffic,
start_addr_o => p0_tg_start_addr,
end_addr_o => p0_tg_end_addr ,
cmd_seed_o => p0_tg_cmd_seed ,
data_seed_o => p0_tg_data_seed ,
load_seed_o => p0_tg_load_seed ,
addr_mode_o => p0_tg_addr_mode ,
instr_mode_o => p0_tg_instr_mode ,
bl_mode_o => p0_tg_bl_mode ,
data_mode_o => p0_tg_data_mode ,
mode_load_o => p0_tg_mode_load ,
fixed_bl_o => p0_tg_fixed_bl ,
fixed_instr_o => p0_tg_fixed_instr,
fixed_addr_o => p0_tg_fixed_addr
);
m_traffic_gen_p0 : mcb_traffic_gen
generic map(
MEM_BURST_LEN => C_MEM_BURST_LEN,
MEM_COL_WIDTH => C_MEM_NUM_COL_BITS,
NUM_DQ_PINS => C_NUM_DQ_PINS,
DQ_ERROR_WIDTH => DQ_ERROR_WIDTH,
PORT_MODE => p0_PORT_MODE,
DWIDTH => p0_DWIDTH,
CMP_DATA_PIPE_STAGES => CMP_DATA_PIPE_STAGES,
FAMILY => FAMILY,
SIMULATION => "FALSE",
DATA_PATTERN => DATA_PATTERN,
CMD_PATTERN => "CGEN_ALL",
ADDR_WIDTH => 30,
PRBS_SADDR_MASK_POS => C_p0_PRBS_SADDR_MASK_POS,
PRBS_EADDR_MASK_POS => C_p0_PRBS_EADDR_MASK_POS,
PRBS_SADDR => C_p0_BEGIN_ADDRESS,
PRBS_EADDR => C_p0_END_ADDRESS
)
port map
(
clk_i => clk0,
rst_i => rst0,
run_traffic_i => p0_tg_run_traffic,
manual_clear_error => rst0,
-- runtime parameter
start_addr_i => p0_tg_start_addr ,
end_addr_i => p0_tg_end_addr ,
cmd_seed_i => p0_tg_cmd_seed ,
data_seed_i => p0_tg_data_seed ,
load_seed_i => p0_tg_load_seed,
addr_mode_i => p0_tg_addr_mode,
instr_mode_i => p0_tg_instr_mode ,
bl_mode_i => p0_tg_bl_mode ,
data_mode_i => p0_tg_data_mode ,
mode_load_i => p0_tg_mode_load ,
-- fixed pattern inputs interface
fixed_bl_i => p0_tg_fixed_bl,
fixed_instr_i => p0_tg_fixed_instr,
fixed_addr_i => p0_tg_fixed_addr,
fixed_data_i => (others => '0'),
-- BRAM interface.
bram_cmd_i => (others => '0'),
bram_valid_i => '0',
bram_rdy_o => open,
-- MCB INTERFACE
mcb_cmd_en_o => p0_mcb_cmd_en_o_int,
mcb_cmd_instr_o => p0_mcb_cmd_instr_o_int,
mcb_cmd_bl_o => p0_mcb_cmd_bl_o_int,
mcb_cmd_addr_o => p0_mcb_cmd_addr_o_int,
mcb_cmd_full_i => p0_mcb_cmd_full_i,
mcb_wr_en_o => p0_mcb_wr_en_o_int,
mcb_wr_mask_o => p0_mcb_wr_mask_o,
mcb_wr_data_o => p0_mcb_wr_data_o,
mcb_wr_data_end_o => open,
mcb_wr_full_i => p0_mcb_wr_full_i,
mcb_wr_fifo_counts => p0_mcb_wr_fifo_counts,
mcb_rd_en_o => p0_mcb_rd_en_o,
mcb_rd_data_i => p0_mcb_rd_data_i,
mcb_rd_empty_i => p0_mcb_rd_empty_i,
mcb_rd_fifo_counts => p0_mcb_rd_fifo_counts,
-- status feedback
counts_rst => rst0,
wr_data_counts => open,
rd_data_counts => open,
cmp_data => p0_cmp_data,
cmp_data_valid => p0_cmp_data_valid,
cmp_error => p0_cmp_error,
error => p0_error,
error_status => p0_error_status,
mem_rd_data => open,
dq_error_bytelane_cmp => open,
cumlative_dq_lane_error => open
);
end architecture;
| gpl-3.0 | d0dfbaaf82bf177ec63c34f45cccae8d | 0.489015 | 3.527994 | false | false | false | false |
masaruohashi/tic-tac-toe | interface_jogo/mapeador_uart.vhd | 1 | 689 | -- VHDL de um mapeador para a habilitação da UART
library ieee;
use ieee.std_logic_1164.all;
entity mapeador_uart is
port(
jogador: in std_logic;
uart_recebe_dado: in std_logic;
uart_jogador: out std_logic;
uart_oponente: out std_logic
);
end mapeador_uart;
architecture estrutural of mapeador_uart is
begin
process (uart_recebe_dado, jogador)
begin
if uart_recebe_dado = '1' then
if jogador='0' then
uart_jogador <= '1';
uart_oponente <= '0';
else
uart_jogador <= '0';
uart_oponente <= '1';
end if;
else
uart_jogador <= '0';
uart_oponente <= '0';
end if;
end process;
end estrutural;
| mit | 37d4d6d0962c734b7c0bfb1799d4d956 | 0.615721 | 3.136986 | false | false | false | false |
JavierRizzoA/Sacagawea | sources/DECODIFICADOR.vhd | 1 | 1,494 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:18:59 06/05/2016
-- Design Name:
-- Module Name: DECODIFICADOR - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity DECODIFICADOR is
Port ( dir_ar : in STD_LOGIC_VECTOR (1 downto 0);
enable_ROM : out STD_LOGIC;
enable_RAM : out STD_LOGIC;
enable_LEDS : out STD_LOGIC;
enable_SWITCHES : out STD_LOGIC
);
end DECODIFICADOR;
architecture Behavioral of DECODIFICADOR is
signal temp : std_logic_vector(3 downto 0);
begin
temp <= "1000" when (dir_ar = "00") else
"0100" when (dir_ar = "01") else
"0010" when (dir_ar = "10") else
"0001";
enable_ROM <= temp(3);
enable_RAM <= temp(2);
enable_LEDS <= temp(1);
enable_SWITCHES <= temp(0);
end Behavioral;
| mit | 93adb1051ab798c87d24cbea804a3cc6 | 0.551539 | 3.725686 | false | false | false | false |
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