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tghaefli/ADD
EDK/IVK_Repos/IVK_IPLib/pcores/ivk_video_gen_v2_01_a/hdl/vhdl/videosyncgen.vhd
1
12,384
------------------------------------------------------------------ -- _____ -- / \ -- /____ \____ -- / \===\ \==/ -- /___\===\___\/ AVNET -- \======/ -- \====/ ----------------------------------------------------------------- -- -- This design is the property of Avnet. Publication of this -- design is not authorized without written consent from Avnet. -- -- Please direct any questions to: [email protected] -- -- Disclaimer: -- Avnet, Inc. makes no warranty for the use of this code or design. -- This code is provided "As Is". Avnet, Inc assumes no responsibility for -- any errors, which may appear in this code, nor does it make a commitment -- to update the information contained herein. Avnet, Inc specifically -- disclaims any implied warranties of fitness for a particular purpose. -- Copyright(c) 2010 Avnet, Inc. -- All rights reserved. -- ------------------------------------------------------------------ -- -- Create Date: Dec 03, 2009 -- Design Name: IVK -- Module Name: ivk_video_gen\videosyncgen.vhd -- Project Name: IVK -- Target Devices: Spartan-6 -- Avnet Boards: IVK -- -- Tool versions: ISE 11.4 -- -- Description: Video Synchronization Generator -- -- Dependencies: -- -- Revision: Dec 03, 2009: 1.00 Initial version -- Feb 08, 2010: 1.02 Add generation of VBLANK/HBLANK -- ------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity VideoSyncGen is generic ( HWidth_g : integer := 16; VWidth_g : integer := 16 ); port ( -- Global Reset i_Clk_p : in std_logic; i_Reset_p : in std_logic; -- Video Configuration iv16_VidHActive_p : in std_logic_vector(15 downto 0); iv16_VidHFPorch_p : in std_logic_vector(15 downto 0); iv16_VidHSync_p : in std_logic_vector(15 downto 0); iv16_VidHBPorch_p : in std_logic_vector(15 downto 0); -- iv16_VidVActive_p : in std_logic_vector(15 downto 0); iv16_VidVFPorch_p : in std_logic_vector(15 downto 0); iv16_VidVSync_p : in std_logic_vector(15 downto 0); iv16_VidVBPorch_p : in std_logic_vector(15 downto 0); -- Video Synchronization Signals o_HSync_p : out std_logic; o_VSync_p : out std_logic; o_De_p : out std_logic; o_HBlank_p : out std_logic; o_VBlank_p : out std_logic; -- Data Request strobe (1 cycle in advance of synchronization signals) ov_HCount_p : out std_logic_vector(HWidth_g-1 downto 0); ov_VCount_p : out std_logic_vector(VWidth_g-1 downto 0); o_PixelRequest_p : out std_logic ); end entity VideoSyncGen; architecture Rtl of VideoSyncGen is -- -- Intermediate signals for output ports -- -- Video Synchronization Signals signal HSync_s : std_logic; signal VSync_s : std_logic; signal De_s : std_logic; signal HBlank_s : std_logic; signal VBlank_s : std_logic; -- Data Request strobe (1 cycle in advance of synchronization signals) signal v_HCount_s : unsigned(HWidth_g-1 downto 0); signal v_VCount_s : unsigned(VWidth_g-1 downto 0); signal PixelRequest_s : std_logic; -- -- Sync State Machines -- type SyncState_t is ( FrontPorch_c, SyncPulse_c, BackPorch_c, ActiveVideo_c ); signal HSyncState_s : SyncState_t; signal VSyncState_s : SyncState_t; signal VSyncStateD1_s : SyncState_t; attribute fsm_encoding : string; attribute fsm_encoding of HSyncState_s : signal is "sequential"; attribute fsm_encoding of VSyncState_s : signal is "sequential"; attribute safe_implementation : string; attribute safe_implementation of HSyncState_s : signal is "yes"; attribute safe_implementation of VSyncState_s : signal is "yes"; signal v_HSyncCount_s : unsigned(HWidth_g+1 downto 0); signal v_VSyncCount_s : unsigned(VWidth_g+1 downto 0); signal HSyncDone_s : std_logic; signal VSyncDone_s : std_logic; signal HSyncA1_s : std_logic; signal VSyncA1_s : std_logic; signal DeA1_s : std_logic; signal HBlankA1_s : std_logic; signal VBlankA1_s : std_logic; begin -- -- Output port assignments -- -- Video Synchronization Signals o_VSync_p <= VSync_s; o_HSync_p <= HSync_s; o_De_p <= De_s; o_HBlank_p <= HBlank_s; o_VBlank_p <= VBlank_s; -- Data Request strobe (1 cycle in advance of synchronization signals) ov_HCount_p <= std_logic_vector(v_HCount_s); ov_VCount_p <= std_logic_vector(v_VCount_s); o_PixelRequest_p <= PixelRequest_s; -- -- HSync State Machine -- HSyncFsm_l : process ( i_Clk_p, i_Reset_p ) begin if ( i_Reset_p = '1' ) then HSyncState_s <= FrontPorch_c; v_HSyncCount_s <= (others => '0'); HSyncA1_s <= '0'; DeA1_s <= '0'; HBlankA1_s <= '0'; HSync_s <= '0'; De_s <= '0'; HBlank_s <= '0'; v_HCount_s <= (others => '0'); HSyncDone_s <= '0'; elsif rising_edge( i_Clk_p ) then -- Default values HSyncDone_s <= '0'; -- HSync Counter v_HSyncCount_s <= v_HSyncCount_s + 1; -- HSync State Machine case HSyncState_s is when FrontPorch_c => if v_HSyncCount_s >= (unsigned(iv16_VidHFPorch_p) - 1) then v_HSyncCount_s <= (others => '0'); HSyncDone_s <= '1'; HSyncState_s <= SyncPulse_c; if ( iv16_VidHSync_p(15) = '1' ) then HSyncA1_s <= '1'; -- Active High sync pulse else HSyncA1_s <= '0'; -- Active Low sync pulse end if; end if; when SyncPulse_c => if v_HSyncCount_s >= (unsigned(iv16_VidHSync_p(14 downto 0)) - 1) then v_HSyncCount_s <= (others => '0'); HSyncState_s <= BackPorch_c; if ( iv16_VidHSync_p(15) = '1' ) then HSyncA1_s <= '0'; -- Active High sync pulse else HSyncA1_s <= '1'; -- Active Low sync pulse end if; end if; when BackPorch_c => if v_HSyncCount_s >= (unsigned(iv16_VidHBPorch_p) - 1) then v_HSyncCount_s <= (others => '0'); HSyncState_s <= ActiveVideo_c; v_HCount_s <= (others => '0'); --if ( VSyncState_s = ActiveVideo_c ) then if ( VSyncStateD1_s = ActiveVideo_c ) then DeA1_s <= '1'; end if; HBlankA1_s <= '0'; end if; when ActiveVideo_c => v_HCount_s <= v_HCount_s + 1; if v_HSyncCount_s >= (unsigned(iv16_VidHActive_p) - 1) then v_HSyncCount_s <= (others => '0'); HSyncState_s <= FrontPorch_c; DeA1_s <= '0'; HBlankA1_s <= '1'; end if; when others => HSyncState_s <= ActiveVideo_c; v_HSyncCount_s <= (others => '0'); HSyncDone_s <= '0'; end case; -- non-advanced versions of synchronization signals (ie. delayed by 1 clock cycle) HSync_s <= HSyncA1_s; De_s <= DeA1_s; HBlank_s <= HBlankA1_s; end if; end process HSyncFsm_l; -- Pixel Request is advanced version of DE PixelRequest_s <= DeA1_s; -- -- VSync State Machine -- VSyncFsm_l : process ( i_Clk_p, i_Reset_p ) begin if ( i_Reset_p = '1' ) then VSyncState_s <= FrontPorch_c; VSyncStateD1_s <= FrontPorch_c; v_VSyncCount_s <= (others => '0'); VSyncA1_s <= '0'; VBlankA1_s <= '0'; VSync_s <= '0'; VBlank_s <= '0'; v_VCount_s <= (others => '0'); VSyncDone_s <= '0'; elsif rising_edge( i_Clk_p ) then -- Default values VSyncDone_s <= '0'; if ( HSyncDone_s = '1' ) then -- VSync Counter v_VSyncCount_s <= v_VSyncCount_s + 1; -- VSync State Machine case VSyncState_s is when FrontPorch_c => if v_VSyncCount_s >= (unsigned(iv16_VidVFPorch_p) - 1) then v_VSyncCount_s <= (others => '0'); VSyncState_s <= SyncPulse_c; if ( iv16_VidVSync_p(15) = '1' ) then VSyncA1_s <= '1'; -- Active High sync pulse else VSyncA1_s <= '0'; -- Active Low sync pulse end if; end if; -- The following assignment is not required -- but conveniently indicates the number of active lines during blanking intervals v_VCount_s <= unsigned(iv16_VidVActive_p(VWidth_g-1 downto 0)); when SyncPulse_c => if v_VSyncCount_s >= (unsigned(iv16_VidVSync_p(14 downto 0)) - 1) then v_VSyncCount_s <= (others => '0'); VSyncState_s <= BackPorch_c; if ( iv16_VidVSync_p(15) = '1' ) then VSyncA1_s <= '0'; -- Active High sync pulse else VSyncA1_s <= '1'; -- Active Low sync pulse end if; end if; when BackPorch_c => if v_VSyncCount_s >= (unsigned(iv16_VidVBPorch_p) - 1) then v_VSyncCount_s <= (others => '0'); VSyncState_s <= ActiveVideo_c; v_VCount_s <= (others => '0'); VSyncDone_s <= '1'; VBlankA1_s <= '0'; end if; when ActiveVideo_c => v_VCount_s <= v_VSyncCount_s(VWidth_g-1 downto 0); if v_VSyncCount_s >= (unsigned(iv16_VidVActive_p) - 1) then v_VSyncCount_s <= (others => '0'); VSyncState_s <= FrontPorch_c; VBlankA1_s <= '1'; end if; when others => VSyncState_s <= ActiveVideo_c; v_VSyncCount_s <= (others => '0'); VSyncDone_s <= '0'; end case; -- non-advanced versions of synchronization signals (ie. delayed by 1 line) VSync_s <= VSyncA1_s; VBlank_s <= VBlankA1_s; -- delayed version of VSyncState VSyncStateD1_s <= VSyncState_s; end if; -- if ( HSyncDone_s = '1' ) end if; end process VSyncFsm_l; end architecture Rtl;
gpl-3.0
718af81c5d1b63c7cbe7a30b12f4cc46
0.443152
4.182371
false
false
false
false
hoglet67/AtomFpga
src/xilinx/AtomFpga_Atom2K18.vhd
1
50,723
-------------------------------------------------------------------------------- -- Copyright (c) 2020 David Banks and Roland Leurs -- -- based on work by Alan Daly. Copyright(c) 2009. All rights reserved. -------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / -- \ \ \/ -- \ \ -- / / Filename : AtomFpga_Atom2K18.vhd -- /___/ /\ Timestamp : 13/06/2020 -- \ \ / \ -- \___\/\___\ -- --Design Name: AtomFpga_Atom2K18 --Device: Spartan6 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; library unisim; use unisim.vcomponents.all; entity AtomFpga_Atom2K18 is generic ( -- Design identifier, readable after configuration from #BFFB DESIGN_NUM : integer := 0; -- Set CImplCpu65c02 to true to use a 65C02 core rather than a 6502 CImplCpu65c02 : boolean := false; -- Set CImplAtoMMC to true to use an internal AtoMMC CImplAtoMMC2 : boolean := true; -- Set CImplDebugger to true to enable the ICE-6502 Debugger CImplDebugger : boolean := false; -- Set CImplDebugger to true to enable the ICE-6502 Debugger CImplSID : boolean := true -- NOTE: If CImplAtoMMC2 and CImplDebugger are both true, several -- smaller features are disabled to make space in the FPGA: -- GODIL: SID and Mouse -- -- If you are not happy with this, then you can experiment with -- enabling individual features in the constants section below. ); port ( -- Clock clk_50 : in std_logic; -- External Bus bus_a : out std_logic_vector(18 downto 0); bus_d : inout std_logic_vector(7 downto 0); bus_blk_b : out std_logic; bus_phi2 : out std_logic; bus_rnw : out std_logic; bus_nrds : out std_logic; bus_nwds : out std_logic; bus_sync : out std_logic; bus_nmi_n : in std_logic; bus_irq_n : in std_logic; bus_rst_n : inout std_logic; bus_rdy : in std_logic; bus_so : in std_logic; -- External device chip selects cs_ram_n : out std_logic; cs_rom_n : out std_logic; cs_via_n : out std_logic; cs_tube_n : out std_logic; cs_buf_n : out std_logic; buf_dir : out std_logic; -- Video vga_red1 : out std_logic; -- this is the MSB vga_red2 : out std_logic; vga_green1 : out std_logic; -- this is the MSB vga_green2 : out std_logic; vga_blue1 : out std_logic; -- this is the MSB vga_blue2 : out std_logic; vga_vsync : out std_logic; vga_hsync : out std_logic; -- Audio audio : out std_logic; dac_cs_n : out std_logic; dac_sdi : out std_logic; dac_ldac_n : out std_logic; dac_sck : out std_logic; -- Keyboard kbd_pa : out std_logic_vector(3 downto 0); kbd_pb : in std_logic_vector(7 downto 0); kbd_pc : in std_logic_vector(6 downto 6); -- Mouse ps2_mouse_clk : inout std_logic; ps2_mouse_data : inout std_logic; -- Cassette cas_in : in std_logic; cas_out : out std_logic; -- Serial serial_tx : out std_logic; serial_rx : in std_logic; -- SD Card mmc_led_red : out std_logic; mmc_led_green : out std_logic; mmc_clk : out std_logic; mmc_ss : out std_logic; mmc_mosi : out std_logic; mmc_miso : in std_logic; -- LEDs on FPGA Module led : out std_logic_vector(1 to 8); -- Switches on FPGA Module sw : in std_logic_vector(2 downto 1); -- USB Uart on FPGA Module avr_tx : out std_logic; avr_rx : in std_logic ); end AtomFpga_Atom2K18; architecture behavioral of AtomFpga_Atom2K18 is ------------------------------------------------------ -- Constants controlling single features ------------------------------------------------------ -- Approx resource usage -- -- (5,720) (32) -- LUTs RamB16 -- Baseline 1197 5.5 -- CImplCpu65C02 -47 1.5 -- CImplAtoMMC2 1325 11 -- CImplDebugger 2342 11 -- CImplVGA80x40 116 -- CImplSID 826 2 -- CImplHWScrolling 90 -- CImplMouse 250 1 -- CImplUart 167 -- CImplDoubleVideo -35 4 -- CImplVIA 254 -- CImplLEDs 131 -- CImplProfilingCounters 174 -- CImplRTC 173 -- CImplSAM 136 -- CImplPAM 28 -- CImplPalette 100 -- CImplConfig 104 -- When both AtoMMC2 and Debugger are included, we need to disable other -- features to make space constant CImplMakeSpace1 : boolean := CImplAtoMMC2 and CImplDebugger and CImplSID; constant CImplMakeSpace2 : boolean := CImplAtoMMC2 and CImplDebugger and not CImplSID; -- GODIL features constant CImplGraphicsExt : boolean := true; constant CImplSoftChar : boolean := true; constant CImplVGA80x40 : boolean := true; constant CImplHWScrolling : boolean := not CImplMakeSpace1; constant CImplMouse : boolean := not CImplMakeSpace1 and not CImplMakeSpace2; constant CImplUart : boolean := not CImplMakeSpace1; constant CImplDoubleVideo : boolean := not CImplMakeSpace1; -- Atom2K18 features constant CImplVIA : boolean := true; constant CImplLEDs : boolean := true; constant CImplProfilingCounters : boolean := not CImplMakeSpace1; constant CImplRTC : boolean := not CImplMakeSpace1; constant CImplSAM : boolean := true; constant CImplPAM : boolean := true; constant CImplPalette : boolean := true; constant CImplConfig : boolean := true; ------------------------------------------------ -- Signals ------------------------------------------------ -- Clock generation signal clk0 : std_logic; signal clk1 : std_logic; signal clk2 : std_logic; signal clkfb : std_logic; signal clkfb_buf : std_logic; signal clkin_buf : std_logic; signal clock_16 : std_logic; signal clock_25 : std_logic; signal clock_32 : std_logic; signal clock_debugger : std_logic; -- Reset generation signal reset_n : std_logic; signal int_reset_n : std_logic; signal ext_reset_n : std_logic; signal powerup_reset_n : std_logic; signal reset_counter : std_logic_vector(9 downto 0); -- External bus interface signal phi2 : std_logic; signal rnw : std_logic; signal sync : std_logic; -- 16 bit address generated by the CPU signal cpu_a : std_logic_vector(15 downto 0); -- 19 bit external address generated by the RamRom signal extern_a : std_logic_vector(18 downto 0); signal extern_din : std_logic_vector(7 downto 0); signal extern_dout : std_logic_vector(7 downto 0); signal extern_bus : std_logic; signal extern_ce : std_logic; signal extern_we : std_logic; -- Audio mixer and DAC constant dacwidth : integer := 16; -- this needs to match the MCP4822 frame size signal atom_audio : std_logic; signal sid_audio : std_logic_vector(17 downto 0); signal cycle : std_logic_vector(6 downto 0); signal audio_l : std_logic_vector(dacwidth - 1 downto 0); signal audio_r : std_logic_vector(dacwidth - 1 downto 0); signal dac_shift_reg_l : std_logic_vector(dacwidth - 1 downto 0); signal dac_shift_reg_r : std_logic_vector(dacwidth - 1 downto 0); -- Matrix Keyboard signal ps2_kbd_enable : std_logic; signal ps2_kbd_clk : std_logic; signal ps2_kbd_data : std_logic; signal int_kbd_pb : std_logic_vector(7 downto 0); signal int_kbd_pc : std_logic_vector(6 downto 6); -- External devices signal extern_rom : std_logic; signal extern_ram : std_logic; signal extern_tube : std_logic; signal extern_via : std_logic; signal extern_pam : std_logic; -- enable for #B1xx signal extern_sam_rd : std_logic; -- enable for #BFF0 signal extern_sam_wr : std_logic; -- enable for #BFF1 -- Internal devices signal intern_led : std_logic; signal intern_rtc : std_logic; signal intern_pam_reg0 : std_logic; -- enable for #BFF8 signal intern_pam_reg1 : std_logic; -- enable for #BFF9 signal intern_sam_reg : std_logic; -- enable for #BFF2 signal intern_palette : std_logic; -- enable for #BD0x signal intern_config : std_logic; -- enable for #BFFB -- Reconfiguration signal config_data : std_logic_vector(7 downto 0) := std_logic_vector(to_unsigned(DESIGN_NUM, 8)); -- Colour palette registers signal palette_data : std_logic_vector(7 downto 0); signal logical_colour : std_logic_vector(3 downto 0); signal physical_colour : std_logic_vector(5 downto 0); type palette_type is array (0 to 15) of std_logic_vector(5 downto 0); signal palette : palette_type := ( 0 => "000000", 1 => "000011", 2 => "000100", 3 => "000111", 4 => "001000", 5 => "001011", 6 => "001100", 7 => "001111", 8 => "110000", 9 => "110011", 10 => "110100", 11 => "110111", 12 => "111000", 13 => "111011", 14 => "111100", 15 => "111111" ); -- Video signal vga_blank : std_logic; signal hsync_vga : std_logic; signal vsync_vga : std_logic; signal red_vga : std_logic_vector(2 downto 0); signal green_vga : std_logic_vector(2 downto 0); signal blue_vga : std_logic_vector(2 downto 0); -- PAM relayed signals signal pam_page : std_logic_vector(8 downto 0); -- SAM related signals signal sam_rd_addr : std_logic_vector(17 downto 0); signal sam_rd_next : std_logic_vector(17 downto 0); signal sam_rd_inc : std_logic; signal sam_wr_addr : std_logic_vector(17 downto 0); signal sam_wr_next : std_logic_vector(17 downto 0); signal sam_wr_inc : std_logic; signal sam_empty : std_logic; signal sam_full : std_logic; signal sam_underflow : std_logic; signal sam_overflow : std_logic; signal sam_status : std_logic_vector(7 downto 0); -- Switch debouncing signal sw_pressed : std_logic_vector(2 downto 1); -- LED control/ Speedometer signal led_ctrl_reg : std_logic_vector(7 downto 0); signal led_data_reg : std_logic_vector(7 downto 0); signal last_sync : std_logic; signal instr_count : unsigned(15 downto 0); signal led_state : unsigned(3 downto 0); signal led_data : std_logic_vector(7 downto 0); -- RTC signal rtc_seconds : std_logic_vector(7 downto 0); signal rtc_minutes : std_logic_vector(7 downto 0); signal rtc_hours : std_logic_vector(7 downto 0); signal rtc_day : std_logic_vector(7 downto 0) := x"01"; signal rtc_month : std_logic_vector(7 downto 0) := x"01"; signal rtc_year : std_logic_vector(7 downto 0); signal rtc_irq_flags : std_logic_vector(7 downto 0); signal rtc_control : std_logic_vector(7 downto 0); signal rtc_10hz : std_logic_vector(3 downto 0); signal rtc_cnt : std_logic_vector(21 downto 0); signal rtc_irq_n : std_logic := '1'; signal rtc_data : std_logic_vector(7 downto 0); -- Interrupt logic signal irq_n : std_logic := '1'; -- Debug mode signal remote_access : std_logic; signal debug_mode : std_logic; begin ------------------------------------------------ -- Clock generation -- -- from the on-board 50MHz Oscillator -- using a PLL for the 16/32 MHz -- using a DCM for the 25.175 MHz (approx) ------------------------------------------------ inst_clkin_buf : IBUFG port map ( I => clk_50, O => clkin_buf ); inst_PLL : PLL_BASE generic map ( BANDWIDTH => "OPTIMIZED", CLK_FEEDBACK => "CLKFBOUT", COMPENSATION => "SYSTEM_SYNCHRONOUS", DIVCLK_DIVIDE => 1, CLKFBOUT_MULT => 16, -- 50 * 16 = 800 CLKFBOUT_PHASE => 0.000, CLKOUT0_DIVIDE => 50, -- 800 / 50 = 16MHz CLKOUT0_PHASE => 0.000, CLKOUT0_DUTY_CYCLE => 0.500, CLKOUT1_DIVIDE => 25, -- 800 / 25 = 32MHz CLKOUT1_PHASE => 0.000, CLKOUT1_DUTY_CYCLE => 0.500, CLKOUT2_DIVIDE => 31, -- 800 / 31 = 25.0864MHz CLKOUT2_PHASE => 0.000, CLKOUT2_DUTY_CYCLE => 0.500, CLKIN_PERIOD => 20.000, REF_JITTER => 0.010 ) port map ( -- Output clocks CLKFBOUT => clkfb, CLKOUT0 => clk0, CLKOUT1 => clk1, CLKOUT2 => clk2, RST => '0', -- Input clock control CLKFBIN => clkfb_buf, CLKIN => clkin_buf ); inst_clkfb_buf : BUFG port map ( I => clkfb, O => clkfb_buf ); inst_clk0_buf : BUFG port map ( I => clk0, O => clock_16 ); inst_clk1_buf : BUFG port map ( I => clk1, O => clock_32 ); inst_clk2_buf : BUFG port map ( I => clk2, O => clock_debugger ); inst_DCM : DCM generic map ( CLKFX_MULTIPLY => 11, CLKFX_DIVIDE => 14, CLKIN_PERIOD => 31.250, CLK_FEEDBACK => "NONE" ) port map ( CLKIN => clock_32, CLKFB => '0', RST => '0', DSSEN => '0', PSINCDEC => '0', PSEN => '0', PSCLK => '0', CLKFX => clock_25 ); -------------------------------------------------------- -- Reset generation -------------------------------------------------------- -- The external reset signal is not asserted on power up -- This internal counter forces power up reset to happen -- This is needed by AtomGodilVideo to initialize some of the registers process (clock_32) begin if rising_edge(clock_32) then if (reset_counter(reset_counter'high) = '0') then reset_counter <= reset_counter + 1; end if; powerup_reset_n <= reset_counter(reset_counter'high); -- logically or the internal and external resets, for use in this file -- this is now synchronised to the 32MHz clock reset_n <= ext_reset_n and int_reset_n; end if; end process; -- logically or the powerup and bus resets, to pass down to the core ext_reset_n <= powerup_reset_n and bus_rst_n; -- Drive the external reset low when there's a power up reset, or -- when int_reset_n (currently just F10 on the PS/2 keyboard). -- Otherwise, it becomes and input (there's a 3K3 external pullup) bus_rst_n <= '0' when powerup_reset_n = '0' or int_reset_n = '0' else 'Z'; ------------------------------------------------ -- Atom FPGA Core ------------------------------------------------ inst_AtomFpga_Core : entity work.AtomFpga_Core generic map ( CImplCpu65c02 => CImplCpu65c02, CImplDebugger => CImplDebugger, CImplSDDOS => false, CImplAtoMMC2 => CImplAtoMMC2, CImplGraphicsExt => CImplGraphicsExt, CImplSoftChar => CImplSoftChar, CImplSID => CImplSID, CImplVGA80x40 => CImplVGA80x40, CImplHWScrolling => CImplHWScrolling, CImplMouse => CImplMouse, CImplUart => CImplUart, CImplDoubleVideo => CImplDoubleVideo, CImplRamRomNone => false, CImplRamRomPhill => false, CImplRamRomAtom2015 => true, CImplRamRomSchakelKaart => false, CImplVIA => CImplVIA, CImplProfilingCounters => CImplProfilingCounters, MainClockSpeed => 32000000, DefaultBaud => 115200 ) port map( clk_vga => clock_25, clk_main => clock_32, clk_avr => clock_32, -- this is the AtoMMC AVR clock clk_avr_debug => clock_debugger, -- this is the ICE6502 AVR clock clk_dac => clock_32, clk_32M00 => clock_32, kbd_pa => kbd_pa, kbd_pb => int_kbd_pb, kbd_pc => int_kbd_pc, ps2_clk => ps2_kbd_clk, ps2_data => ps2_kbd_data, ps2_mouse_clk => ps2_mouse_clk, ps2_mouse_data => ps2_mouse_data, powerup_reset_n => powerup_reset_n, ext_reset_n => ext_reset_n, int_reset_n => int_reset_n, red => red_vga, green => green_vga, blue => blue_vga, vsync => vsync_vga, hsync => hsync_vga, blank => vga_blank, phi2 => phi2, sync => sync, rnw => rnw, rdy => bus_rdy, so => bus_so, irq_n => irq_n, nmi_n => bus_nmi_n, addr => cpu_a, ExternBus => extern_bus, -- active high external bus select ExternCE => extern_ce, -- active high Ram/Rom chip select ExternWE => extern_we, -- active high Ram/Rom write ExternA => extern_a, ExternDin => extern_din, ExternDout => extern_dout, sid_audio => open, sid_audio_d => sid_audio, atom_audio => atom_audio, SDMISO => mmc_miso, SDSS => mmc_ss, SDCLK => mmc_clk, SDMOSI => mmc_mosi, uart_RxD => serial_rx, uart_TxD => serial_tx, avr_RxD => avr_rx, avr_TxD => avr_tx, cas_in => cas_in, cas_out => cas_out, LED1 => mmc_led_green, LED2 => mmc_led_red, charSet => '1' ); ------------------------------------------------ -- External bus ------------------------------------------------ -- 22/4/2019 -- -- I'm not happy with the design of the external bus interface, for the -- following reasons: -- -- 1. extern_we and extern_ce are mediated by the pluggable RAMROM modules -- in AtomFpga_Core. This means they are not active when external devices -- in Bxxx are accessed. -- -- 2. As a work around, I've exposed the 6502 RNW (rnw) signal directly, -- which is probably the right thing to do, as Atom2K18 does have a full -- external bus. But it's now confusing as to when to use extern_we and -- when to use rnw. -- -- 3. It's not clear how addresses on extern_a correspond to what the CPU -- accessed, again because this signal is the output of a RAMROM module. -- -- 4. It seemed wrong to have to add ExternTube and ExternVIA signals to the -- AtomFpga_Core. It should have been possible to implement these externally -- in the FPGA target specific wrapper. But (3) made this difficult. -- -- 5. The NRDS and NWDS signals are currently generated from the RAMROM -- specific extern_ce and extern_we. It would be better if they uses -- rnw and ignored extern_ce. But this is more dangerous, so lets -- see how the current version works before breaking things more! -- -- What's in place currently will work (I think) for the VIA and Tube, but -- will not currently allow any devices to be added to the bus. Need to -- talk with Roland about how he thinks the external bus should be mapped -- into the Atom address space. -- -- 22/4/2019 -- -- Roland's reply: -- -- All addresses from #B000 - #BFFF should be external except for: -- #B000 - #B003 (8255) -- #B400 - #B403 (AtoMMC) -- #B800 - #B80F (6522) -- #BD00 - #BDFF (Godil + reserved address space) -- #BFF0 - #BFFF (control registers, some addresses are reserved) -- -- 23/4/2019 -- -- For consistency, I ended up using a minimum of 16-byte blocks. -- This is all implemented in AtomFpga_Core -- -- To answer my concerns above -- 1. This is resolved by adding a seperate ExternBus output from the core -- 2. I'm happy exposing RNW directly -- 3. The RamRom modules should just output the CPU address when not selected -- 4. ExternVia and ExternTube replaced with ExternBus -- 5. Use ExternCE/ExternWE (for RamRom) and ExternBus/rnw (for Bus) bus_phi2 <= phi2; bus_rnw <= rnw; bus_sync <= sync; -- Used on the bus to enable I/O devices in a safe manner bus_blk_b <= not extern_bus; bus_a <= "1" & sam_rd_addr when extern_sam_rd = '1' and rnw = '1' and CImplSAM else "1" & sam_wr_addr when extern_sam_wr = '1' and rnw = '0' and CImplSAM else "00" & pam_page & extern_a(7 downto 0) when extern_pam = '1' and CImplPAM else extern_a; -- Enable data out of the FPGA onto the 3.3V databus in the following cases: -- case 1. all writes from the "core" -- case 2. reads that are internal to the "core", when debug mode enables -- case 3. reads of the led registers, when debug mode enabled -- case 4. reads of the rtc registers, when debug mode enabled bus_d <= extern_din when phi2 = '1' and rnw = '0' else extern_din when phi2 = '1' and extern_ce = '0' and extern_bus = '0' and debug_mode = '1' else led_data when phi2 = '1' and intern_led = '1' and debug_mode = '1' and CImplLEDs else rtc_data when phi2 = '1' and intern_rtc = '1' and debug_mode = '1' and CImplRTC else palette_data when phi2 = '1' and intern_palette = '1' and debug_mode = '1' and CImplPalette else config_data when phi2 = '1' and intern_config = '1' and debug_mode = '1' and CImplConfig else sam_status when phi2 = '1' and intern_sam_reg = '1' and debug_mode = '1' and CImplSAM else pam_page(7 downto 0) when phi2 = '1' and intern_pam_reg0 = '1' and debug_mode = '1' and CImplPAM else "0000000" & pam_page(8) when phi2 = '1' and intern_pam_reg1 = '1' and debug_mode = '1' and CImplPAM else "ZZZZZZZZ"; bus_nrds <= '0' when extern_ce = '1' and extern_we = '0' and phi2 = '1' else -- RamRom '0' when extern_bus = '1' and rnw = '1' and phi2 = '1' else -- Bus '1'; bus_nwds <= '0' when extern_ce = '1' and extern_we = '1' and phi2 = '1' else -- RamRom '0' when extern_bus = '1' and rnw = '0' and phi2 = '1' else -- Bus '1'; -- data back into the Atom Core extern_dout <= led_data when intern_led = '1' and CImplLEDs else rtc_data when intern_rtc = '1' and CImplRTC else palette_data when intern_palette = '1' and CImplPalette else config_data when intern_config = '1' and CImplConfig else sam_status when intern_sam_reg = '1' and CImplSAM else pam_page(7 downto 0) when intern_pam_reg0 = '1' and CImplPAM else "0000000" & pam_page(8) when intern_pam_reg1 = '1' and CImplPAM else bus_d; ------------------------------------------------ -- Interrupt logic ------------------------------------------------ irq_n <= bus_irq_n and rtc_irq_n; ------------------------------------------------ -- Sequential Access Memory (SAM) ------------------------------------------------ sam_block: if CImplSAM generate process(clock_32) begin if rising_edge(clock_32) then if intern_sam_reg = '1' and rnw = '0' and phi2 = '1' then -- a write of '1' to SAM control register bit 0 clears the overflow error if extern_din(0) = '1' then sam_overflow <= '0'; end if; -- a write of '1' to SAM control register bit 1 clears the underflow error if extern_din(1) = '1' then sam_underflow <= '0'; end if; -- a write of '1' to SAM control register bit 2 resets everything if extern_din(2) = '1' then sam_rd_inc <= '0'; sam_wr_inc <= '0'; sam_rd_addr <= (others => '0'); sam_wr_addr <= (others => '0'); sam_underflow <= '0'; sam_overflow <= '0'; end if; elsif extern_sam_rd = '1' and rnw = '1' and phi2 = '1' then -- a read from the SAM data register if sam_empty = '0' then sam_rd_inc <= '1'; else sam_underflow <= '1'; end if; elsif extern_sam_wr = '1' and rnw = '0' and phi2 = '1' then -- a write to the SAM data register if sam_full = '0' then sam_wr_inc <= '1'; else sam_overflow <= '1'; end if; elsif phi2 = '0' then -- Handle the update of the SAM addresses as soon as Phi2 goes -- low at the start of the next bus cycle if sam_rd_inc = '1' then sam_rd_addr <= sam_rd_next; end if; if sam_wr_inc = '1' then sam_wr_addr <= sam_wr_next; end if; -- clear the inc flags, so we only increment by one sam_rd_inc <= '0'; sam_wr_inc <= '0'; end if; end if; end process; -- combinatorial logic for full,empty flags process(sam_rd_addr, sam_wr_addr) begin if sam_rd_addr = sam_wr_addr then sam_empty <= '1'; else sam_empty <= '0'; end if; if sam_wr_next = sam_rd_addr then sam_full <= '1'; else sam_full <= '0'; end if; end process; -- combinatorial logic for next rd address process(sam_rd_addr) begin sam_rd_next <= sam_rd_addr + 1; end process; -- combinatorial logic for next write address process(sam_wr_addr) begin sam_wr_next <= sam_wr_addr + 1; end process; -- Status byte sam_status <= sam_empty & sam_full & "0000" & sam_underflow & sam_overflow; end generate; ------------------------------------------------ -- Page Access Memory (PAM) ------------------------------------------------ pam_block: if CImplPAM generate process(clock_32) begin if rising_edge(clock_32) then if rnw = '0' and phi2 = '1' then if intern_pam_reg0 = '1' then pam_page(7 downto 0) <= extern_din; end if; if intern_pam_reg1 = '1' then pam_page(8) <= extern_din(0); end if; end if; end if; end process; end generate; ------------------------------------------------ -- Internal device chip selects ------------------------------------------------ intern_led <= '1' when extern_bus = '1' and extern_a(15 downto 4) = x"BFE" and CImplLEDs else '0'; intern_rtc <= '1' when extern_bus = '1' and extern_a(15 downto 4) = x"BFD" and CImplRTC else '0'; intern_sam_reg <= '1' when extern_bus = '1' and extern_a(15 downto 0) = x"BFF2" and CImplSAM else '0'; intern_pam_reg0 <= '1' when extern_bus = '1' and extern_a(15 downto 0) = x"BFF8" and CImplPAM else '0'; intern_pam_reg1 <= '1' when extern_bus = '1' and extern_a(15 downto 0) = x"BFF9" and CImplPAM else '0'; intern_palette <= '1' when extern_bus = '1' and extern_a(15 downto 4) = x"BD0" and CImplPalette else '0'; intern_config <= '1' when extern_bus = '1' and extern_a(15 downto 0) = x"BFFB" and CImplConfig else '0'; ------------------------------------------------ -- External device chip selects ------------------------------------------------ extern_rom <= '1' when extern_ce = '1' and extern_a(17) = '0' else '0'; extern_ram <= '1' when extern_ce = '1' and extern_a(17) = '1' else '1' when (extern_sam_rd = '1' or extern_sam_wr = '1') and CImplSAM else '1' when extern_pam = '1' and CImplPAM else '0'; extern_via <= '1' when extern_bus = '1' and extern_a(15 downto 4) = x"B81" else '0'; extern_tube <= '1' when extern_bus = '1' and extern_a(15 downto 4) = x"BEE" else '0'; extern_sam_rd <= '1' when extern_bus = '1' and extern_a(15 downto 0) = x"BFF0" and CImplSAM else '0'; extern_sam_wr <= '1' when extern_bus = '1' and extern_a(15 downto 0) = x"BFF1" and CImplSAM else '0'; extern_pam <= '1' when extern_bus = '1' and extern_a(15 downto 8) = x"B1" and CImplPAM else '0'; cs_rom_n <= not(extern_rom); cs_ram_n <= not(extern_ram); cs_via_n <= not(extern_via); cs_tube_n <= not(extern_tube); -- A remote access is to a device on the far side of the data buffers -- The tube is on the near side of the data buffers, so exclude -- The LED and RTC registers are internal to this module, so exclude remote_access <= '1' when extern_bus = '1' and extern_tube = '0' and extern_sam_rd = '0' and extern_sam_wr = '0' and extern_pam = '0' and intern_led = '0' and intern_rtc = '0' and intern_palette = '0' and intern_config = '0' and intern_sam_reg = '0' and intern_pam_reg0 = '0' and intern_pam_reg1 = '0' else '0'; -- In normal mode, enable the data buffers only for remote accesses. -- In debug mode, enable the data buffers all the time. cs_buf_n <= '0' when phi2 = '1' and debug_mode = '1' else '0' when phi2 = '1' and remote_access = '1' and debug_mode = '0' else '1'; -- In normal mode, the direction is inward for reads, outward for writes. -- In debug mode, the direction is inward for remote reads, outward for everything else. buf_dir <= '1' when remote_access = '1' and rnw = '1' and debug_mode = '1' else '0' when debug_mode = '1' else rnw; ------------------------------------------------ -- Audio mixer ------------------------------------------------ process(atom_audio, sid_audio) variable l : std_logic_vector(dacwidth - 1 downto 0); variable r : std_logic_vector(dacwidth - 1 downto 0); begin -- Atom Audio is a single bit if (atom_audio = '1') then l := x"1000"; r := x"1000"; else l := x"EFFF"; r := x"EFFF"; end if; -- SID output is 18-bit unsigned if CImplSID then l := l + sid_audio(17 downto 2); r := r + sid_audio(17 downto 2); else l := l + x"8000"; r := r + x"8000"; end if; -- Currently the left and right channels are identical audio_l <= l; audio_r <= r; end process; ------------------------------------------------ -- MCP4822 SPI 12-bit DAC -- -- note: this actually takes 16-bit samples ------------------------------------------------ process(clock_16) begin if rising_edge(clock_16) then cycle <= cycle + 1; if (unsigned(cycle(5 downto 0)) < 33) then dac_cs_n <= '0'; dac_sck <= cycle(0); else dac_cs_n <= '1'; dac_sck <= '0'; end if; if (cycle(0) = '0') then if (unsigned(cycle(5 downto 1)) = 0) then if (cycle(6) = '0') then dac_shift_reg_l <= audio_l; dac_shift_reg_r <= audio_r; end if; dac_sdi <= cycle(6); elsif (unsigned(cycle(5 downto 1)) < 4) then dac_sdi <= '1'; elsif (unsigned(cycle(5 downto 1)) < 16) then if (cycle(6) = '0') then dac_sdi <= dac_shift_reg_l(dacwidth - 1); dac_shift_reg_l <= dac_shift_reg_l(dacwidth - 2 downto 0) & '0'; else dac_sdi <= dac_shift_reg_r(dacwidth - 1); dac_shift_reg_r <= dac_shift_reg_r(dacwidth - 2 downto 0) & '0'; end if; else dac_sdi <= '0'; end if; if (unsigned(cycle(6 downto 1)) = 60) then dac_ldac_n <= '0'; else dac_ldac_n <= '1'; end if; end if; end if; end process; ------------------------------------------------ -- Atom Audio ------------------------------------------------ audio <= atom_audio; ------------------------------------------------ -- Keyboard ------------------------------------------------ process(clock_32) begin if rising_edge(clock_32) then if powerup_reset_n = '0' then -- PC(7) linked to ground indicates a PS/2 keyboard should be used ps2_kbd_enable <= not kbd_pc(6); end if; end if; end process; -- Enable/Disable the PS/2 keyboard ps2_kbd_clk <= kbd_pb(6) when ps2_kbd_enable = '1' else '1'; ps2_kbd_data <= kbd_pb(7) when ps2_kbd_enable = '1' else '1'; -- Enable/Disable the Matrix keyboard int_kbd_pb <= kbd_pb when ps2_kbd_enable = '0' else (others => '1'); int_kbd_pc <= kbd_pc when ps2_kbd_enable = '0' else (others => '1'); -------------------------------------------------------- -- LED control / speedometer -------------------------------------------------------- leds_block: if CImplLEDs generate inst_debounce1 : entity work.debounce generic map ( counter_size => 20 -- 32ms @ 32MHz ) port map ( clock => clock_32, button => sw(1), pressed => sw_pressed(1) ); inst_debounce2 : entity work.debounce generic map ( counter_size => 20 -- 32ms @ 32MHz ) port map ( clock => clock_32, button => sw(2), pressed => sw_pressed(2) ); process(clock_32) begin if rising_edge(clock_32) then -- SW1/2 manually increment/decrement bits 0/1 of the LED control register if sw_pressed(1) = '1' then led_ctrl_reg(1 downto 0) <= led_ctrl_reg(1 downto 0) - 1; elsif sw_pressed(2) = '1' then led_ctrl_reg(1 downto 0) <= led_ctrl_reg(1 downto 0) + 1; end if; -- LED control/data registers if intern_led = '1' and rnw = '0' and phi2 = '1' then if extern_a(0) = '1' then led_data_reg <= extern_din; else led_ctrl_reg <= extern_din; end if; end if; -- LED Speedometer last_sync <= sync; if last_sync = '0' and sync = '1' then instr_count <= instr_count + 1; if instr_count = 0 then if led_state = x"D" then led_state <= (others => '0'); else led_state <= led_state + 1; end if; end if; end if; -- LED driver logic case led_ctrl_reg(1 downto 0) is when "01" => case led_state is when x"0" => led <= "01000000"; when x"1" => led <= "10000000"; when x"2" => led <= "01000000"; when x"3" => led <= "00100000"; when x"4" => led <= "00010000"; when x"5" => led <= "00001000"; when x"6" => led <= "00000100"; when x"7" => led <= "00000010"; when x"8" => led <= "00000001"; when x"9" => led <= "00000010"; when x"A" => led <= "00000100"; when x"B" => led <= "00001000"; when x"C" => led <= "00010000"; when x"D" => led <= "00100000"; when others => led <= "00000000"; end case; when "10" => led <= cpu_a(15 downto 8); when "11" => led <= cpu_a(7 downto 0); when others => led <= led_data_reg; end case; end if; end process; led_data <= led_ctrl_reg when extern_a(0) = '0' else led_data_reg when extern_a(1) = '1' else x"00"; -- Enable debug mode (logic analyzer output to data bus)in address mode -- (when the LEDs are showing the low or high address bus) debug_mode <= led_ctrl_reg(1); end generate; not_leds_block: if not CImplLEDs generate led <= x"00"; debug_mode <= '0'; end generate; -------------------------------------------------------- -- RTC Real Time Clock -------------------------------------------------------- rtc_block: if CImplRTC generate process (clock_32) begin if rising_edge(clock_32) then if rtc_control(7) = '0' then if rtc_cnt = 3199999 then rtc_cnt <= (others => '0'); rtc_10hz <= rtc_10hz + 1; if rtc_control(0) = '1' then rtc_irq_flags(0) <= '1'; rtc_irq_flags(7) <= '1'; end if; else rtc_cnt <= rtc_cnt + 1; end if; if rtc_10hz = 10 then rtc_seconds <= rtc_seconds + 1; rtc_10hz <= x"0"; if rtc_control(1) = '1' then rtc_irq_flags(1) <= '1'; rtc_irq_flags(7) <= '1'; end if; end if; if rtc_seconds = 60 then rtc_minutes <= rtc_minutes + 1; rtc_seconds <= x"00"; if rtc_control(2) = '1' then rtc_irq_flags(2) <= '1'; rtc_irq_flags(7) <= '1'; end if; end if; if rtc_minutes = 60 then rtc_hours <= rtc_hours + 1; rtc_minutes <= x"00"; if rtc_control(3) = '1' then rtc_irq_flags(3) <= '1'; rtc_irq_flags(7) <= '1'; end if; end if; if rtc_hours = 24 then rtc_day <= rtc_day + 1; rtc_hours <= x"00"; if rtc_control(4) = '1' then rtc_irq_flags(4) <= '1'; rtc_irq_flags(7) <= '1'; end if; end if; if (rtc_day = 31 and (rtc_month = 4 or rtc_month = 6 or rtc_month = 9 or rtc_month = 11)) or (rtc_day = 30 and rtc_month = 2 and rtc_year(1 downto 0) = "00") or (rtc_day = 29 and rtc_month = 2 and (rtc_year(1) = '1' or rtc_year(0) = '1')) or (rtc_day = 32) then rtc_month <= rtc_month + 1; rtc_day <= x"01"; if rtc_control(5) = '1' then rtc_irq_flags(5) <= '1'; rtc_irq_flags(7) <= '1'; end if; end if; if rtc_month = 13 then rtc_year <= rtc_year + 1; rtc_month <= x"01"; if rtc_control(6) = '1' then rtc_irq_flags(6) <= '1'; rtc_irq_flags(7) <= '1'; end if; end if; end if; -- write RTC control/data registers if intern_rtc = '1' and rnw = '0' and phi2 = '1' then case extern_a(2 downto 0) is when "000" => rtc_year <= extern_din; when "001" => rtc_month <= extern_din; when "010" => rtc_day <= extern_din; when "011" => rtc_hours <= extern_din; when "100" => rtc_minutes <= extern_din; when "101" => rtc_seconds <= extern_din; when "110" => rtc_control <= extern_din; when others => rtc_irq_flags <= x"00"; end case; end if; if reset_n = '0' then rtc_control <= x"00"; rtc_irq_flags <= x"00"; end if; end if; end process; rtc_data <= rtc_year when extern_a(2 downto 0) = "000" else rtc_month when extern_a(2 downto 0) = "001" else rtc_day when extern_a(2 downto 0) = "010" else rtc_hours when extern_a(2 downto 0) = "011" else rtc_minutes when extern_a(2 downto 0) = "100" else rtc_seconds when extern_a(2 downto 0) = "101" else rtc_control when extern_a(2 downto 0) = "110" else rtc_irq_flags when extern_a(2 downto 0) = "111" else x"00"; rtc_irq_n <= not(rtc_irq_flags(7)); end generate; not_rtc_block: if not CImplRTC generate rtc_data <= x"00"; rtc_irq_n <= '1'; end generate; -------------------------------------------------------- -- Colour palette control -------------------------------------------------------- palette_block: if CImplPalette generate process (clock_32) begin if rising_edge(clock_32) then if reset_n = '0' then -- initializing like this mean the palette will be -- implemented with LUTs rather than as a block RAM palette(0) <= "000000"; palette(1) <= "000011"; palette(2) <= "000100"; palette(3) <= "000111"; palette(4) <= "001000"; palette(5) <= "001011"; palette(6) <= "001100"; palette(7) <= "001111"; palette(8) <= "110000"; palette(9) <= "110011"; palette(10) <= "110100"; palette(11) <= "110111"; palette(12) <= "111000"; palette(13) <= "111011"; palette(14) <= "111100"; palette(15) <= "111111"; else -- write colour palette registers if intern_palette = '1' and rnw = '0' and phi2 = '1' then palette(conv_integer(extern_a(3 downto 0))) <= extern_din(7 downto 2); end if; end if; end if; end process; logical_colour <= red_vga(2) & green_vga(2) & green_vga(1) & blue_vga(2); -- Making this a synchronous process should improve the timing -- and potentially make the pixels more defined process (clock_25) begin if rising_edge(clock_25) then if vga_blank = '1' then physical_colour <= (others => '0'); else physical_colour <= palette(conv_integer(logical_colour)); end if; -- Also register hsync/vsync so they are correctly -- aligned with the colour changes vga_hsync <= hsync_vga; vga_vsync <= vsync_vga; end if; end process; vga_red2 <= physical_colour(5); vga_red1 <= physical_colour(4); vga_green2 <= physical_colour(3); vga_green1 <= physical_colour(2); vga_blue2 <= physical_colour(1); vga_blue1 <= physical_colour(0); palette_data <= palette(conv_integer(extern_a(3 downto 0))) & "00"; end generate; not_palette_block: if not CImplPalette generate vga_hsync <= hsync_vga; vga_vsync <= vsync_vga; vga_red2 <= red_vga(2); vga_red1 <= red_vga(1); vga_green2 <= green_vga(2); vga_green1 <= green_vga(1); vga_blue2 <= blue_vga(2); vga_blue1 <= blue_vga(1); end generate; -------------------------------------------------------- -- Colour palette control -------------------------------------------------------- config_block: if CImplConfig generate process (clock_32) begin if rising_edge(clock_32) then -- write RTC control/data registers if intern_config = '1' and rnw = '0' and phi2 = '1' then -- Bit 7 triggers the reconfiguration -- Bits 2..0 specify the design (0..7) config_data <= extern_din; end if; end if; end process; Inst_ICAP_core: entity work.ICAP_core port map ( fastclk => clock_32, design_num => '0' & config_data(2 downto 0), reconfigure => config_data(7), powerup => '0', sw_in => x"0" ); end generate; end behavioral;
apache-2.0
fc4236c73c6b455f3c028cf8e3374c01
0.443191
4.168899
false
false
false
false
GSimas/EEL5105
PROJETO-EEL5105/Projeto/PROJETO.vhd
1
16,480
library IEEE; use IEEE.Std_Logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; --------------- INICIO DA ENTIDADE ------------------------- entity PROJETO is port (SW: in std_logic_vector(9 downto 0); HEX0, HEX1, HEX2, HEX3, HEX4, HEX5: out std_logic_vector(6 downto 0); LEDR: out std_logic_vector(9 downto 0); KEY: in std_logic_vector(3 downto 0); CLOCK_50: in std_logic ); end PROJETO; --------------- INICIO DOS SINAIS DA ARQUITETURA ------------------------- architecture topo_stru of PROJETO is signal btn0, btn1, btn2, btn3: std_logic; -- saida dos botoes do Debouncer signal MAP1F0, MAP1F1, MAP1F2, MAP1F3, MAP1F4, MAP1F5, MAP1F6, MAP1F7, MAP1F8, -- Saida Mapa 1 MAP1F9, MAP1F10, MAP1F11, MAP1F12, MAP1F13, MAP1F14, MAP1F15: std_logic_vector(31 downto 0); signal MAP2F0, MAP2F1, MAP2F2, MAP2F3, MAP2F4, MAP2F5, MAP2F6, MAP2F7, MAP2F8, -- Saida Mapa 2 MAP2F9, MAP2F10, MAP2F11, MAP2F12, MAP2F13, MAP2F14, MAP2F15: std_logic_vector(31 downto 0); signal MAP3F0, MAP3F1, MAP3F2, MAP3F3, MAP3F4, MAP3F5, MAP3F6, MAP3F7, MAP3F8, -- Saida Mapa 3 MAP3F9, MAP3F10, MAP3F11, MAP3F12, MAP3F13, MAP3F14, MAP3F15: std_logic_vector(31 downto 0); signal MAP4F0, MAP4F1, MAP4F2, MAP4F3, MAP4F4, MAP4F5, MAP4F6, MAP4F7, MAP4F8, -- Saida Mapa 4 MAP4F9, MAP4F10, MAP4F11, MAP4F12, MAP4F13, MAP4F14, MAP4F15: std_logic_vector(31 downto 0); signal clock1, clock2, clock3, clock4, clock5, clockm, clockled: std_logic; -- sinais de clock signal en_timee, reset, sel_led, set_rol: std_logic; -- sinais controle signal sel_disp: std_logic_vector(1 downto 0); -- sinal controle seleciona display signal states: std_logic_vector(4 downto 0); -- sinal controle estados signal cnt_b: std_logic_vector(4 downto 0); -- sinais contadores signal cnt_d, cnt_u: std_logic_vector(9 downto 0); -- sinais contadores signal speed: std_logic_vector(2 downto 0); -- sinal velocidade signal up_down: std_logic_vector(3 downto 0); -- sinal posicao cima / baixo constant compare_end_time: std_logic_vector(9 downto 0) := "0000000000"; -- constante comparacao Fim do Tempo constant compare_target: std_logic_vector(9 downto 0) := "0010000000"; -- constante comparacao Target constant compare_bonus: std_logic_vector(4 downto 0) := "00000"; -- constante comparacao Bonus / Vida signal soma: std_logic_vector(9 downto 0) := "0000" & cnt_b & '0'; -- sinal entrada de somador de pontos signal point: std_logic_vector(9 downto 0); -- sinal de pontuacao signal end_time, end_bonus, target: std_logic; -- sinais de finalizacao signal reg_in0, reg_in1, reg_in2, reg_in3, reg_in4, reg_in5, reg_in6, reg_in7, reg_in8, -- sinais registradores mapa entra reg_in9, reg_in10, reg_in11, reg_in12, reg_in13, reg_in14, reg_in15: std_logic_vector(31 downto 0); signal reg_out, reg_out0, reg_out1, reg_out2, reg_out3, reg_out4, reg_out5, reg_out6, reg_out7, reg_out8, -- sinais registradores mapa sai reg_out9, reg_out10, reg_out11, reg_out12, reg_out13, reg_out14, reg_out15: std_logic_vector(31 downto 0); signal mux1: std_logic_vector(29 downto 0) := "01110" & states & "101100101011001000" & SW(8) & SW(7); -- sinal 1 multiplexador display signal mux2: std_logic_vector(29 downto 0) := "01110" & states & "11110000000111101111"; -- sinal 2 multiplexador display signal mux3: std_logic_vector(29 downto 0) := "01110" & states & "1100111101" & point; -- sinal 3 multiplexador display signal hx: std_logic_vector(29 downto 0); -- sinal saida multiplexador display signal mux2_sig1: std_logic_vector(9 downto 0) := "0000000000"; -- sinal 1 para multiplexador 2x1 10 bits (LEDS) signal mux2_sig2: std_logic_vector(9 downto 0) := clockled & reg_out(30 downto 22); -- sinal 2 para multiplexador 2x1 10 bits (LEDS) signal mux2_30_sig1: std_logic_vector(29 downto 0) := "01110" & states & "01011" & cnt_b & cnt_d; -- sinal 1 Multiplexador 2x1 30 bits (Display) signal mux2_30_sig2: std_logic_vector(29 downto 0) := "11100" & "00" & speed & "11001" & "0" & up_down & cnt_u; -- sinal 2 Multiplexador 2x1 30 bits (Display) signal screen: std_logic_vector(29 downto 0); -- sinal display signal led_out: std_logic_vector(9 downto 0); -- sinal led --------------- INICIO DOS COMPONENTES ------------------------- -- Componente Debouncer de botao component ButtonSync is port ( -- Input ports key0 : in std_logic; key1 : in std_logic; key2 : in std_logic; key3 : in std_logic; clk : in std_logic; -- Output ports btn0 : out std_logic; btn1 : out std_logic; btn2 : out std_logic; btn3 : out std_logic ); end component; -- Componente MAPA 1 component map1 is port ( F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13, F14, F15: out std_logic_vector(31 downto 0) ); end component; -- Componente MAPA 2 component map2 is port ( F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13, F14, F15: out std_logic_vector(31 downto 0) ); end component; -- Componente MAPA 3 component map3 is port ( F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13, F14, F15: out std_logic_vector(31 downto 0) ); end component; -- Componente MAPA 4 component map4 is port ( F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13, F14, F15: out std_logic_vector(31 downto 0) ); end component; -- Componente FSM CLOCK component FSM_clock is port( CLK: in std_logic; CLK1, CLK2, CLK3, CLK4, CLK5: out std_logic; CLK_led: out std_logic ); end component; -- Componente Contador Descendente Tempo component Conta_des is port( EN_TIME, CLK, RST: in std_logic; CNT_OUT: out std_logic_vector(9 downto 0) ); end component; -- Componente Contador Ascendente Posicao component Conta_asc is port( EN_TIME, CLK, RST: in std_logic; SPEED: in std_logic_vector(2 downto 0); CNT_OUT: out std_logic_vector(9 downto 0) ); end component; -- Componente Contador Descendente Bonus / vida component Conta_bonus is port( EN_TIME, REG_ROM, CLK, RST: in std_logic; CNT_OUT: out std_logic_vector(4 downto 0) ); end component; -- Componente Comparador 10 bits component compare_10 is port (IN1: in std_logic_vector(9 downto 0); IN2: in std_logic_vector(9 downto 0); OUT1: out std_logic ); end component; -- Componente Comparador 5 bits component compare_5 is port (IN1: in std_logic_vector(4 downto 0); IN2: in std_logic_vector(4 downto 0); OUT1: out std_logic ); end component; -- Componente Somador 10 bits component adder_10 is port( IN1, IN2: in std_logic_vector(9 downto 0); OUT1: out std_logic_vector(9 downto 0) ); end component; -- Componente FSM Posicao component FSM_position is port( CLK, RST, EN_TIME, SW1, SW0: in std_logic; SPEED: in std_logic_vector(2 downto 0); UP_DOWN: out std_logic_vector(3 downto 0) ); end component; -- Componente FSM Velocidade component FSM_speed is port( CLK, RST, BRK, ACC, EN_TIME: in std_logic; speed: out std_logic_vector(2 downto 0) ); end component; -- Componente Deslocamento e Rotacao a esquerda component rot_32 is port( SET_ROLL, EN_TIME, CLOCK_M, RST: in std_logic; SPEED: in std_logic_vector(2 downto 0); REG_IN: in std_logic_vector(31 downto 0); REG_OUT: out std_logic_vector(31 downto 0) ); end component; -- Componente FSM de Controle component FSM_control is port( CLK, RESET, END_BONUS, END_TIME, ENTER, TARGET: in std_logic; SEL_DISP: out std_logic_vector(1 downto 0); STATESS: out std_logic_vector(4 downto 0); SEL_LED, SET_ROLL, EN_TIME, RST: out std_logic ); end component; -- Componente Multiplexador 4x1 32 bits component mux4x1_32 is port (MAP1, MAP2, MAP3, MAP4: in std_logic_vector(31 downto 0); REG: out std_logic_vector(31 downto 0); SW: in std_logic_vector(1 downto 0) ); end component; -- Componente Multiplexador 4x1 30 bits component mux4x1_30 is port (MAP1, MAP2, MAP3, MAP4: in std_logic_vector(29 downto 0); REG: out std_logic_vector(29 downto 0); SW: in std_logic_vector(1 downto 0) ); end component; -- Componente Multiplexador 8x1 1 bit component mux8x1 is port (IN0,IN1,IN2,IN3,IN4,IN5,IN6,IN7: in std_logic; REG: out std_logic; SW: in std_logic_vector(2 downto 0) ); end component; -- Componente Multiplexador 16x1 32 bits component mux16x1_32 is port (IN0,IN1,IN2,IN3,IN4,IN5,IN6,IN7,IN8,IN9,IN10,IN11,IN12,IN13,IN14,IN15: in std_logic_vector(31 downto 0); REG: out std_logic_vector(31 downto 0); UP_DOWN: in std_logic_vector(3 downto 0) ); end component; -- Componente Multiplexador 2x1 10 bits component mux2x1_10 is port (IN0,IN1: in std_logic_vector(9 downto 0); REG: out std_logic_vector(9 downto 0); SW: in std_logic ); end component; -- Componente Multiplexador 2x1 30 bits component mux2x1_30 is port (IN0,IN1: in std_logic_vector(29 downto 0); REG: out std_logic_vector(29 downto 0); SW: in std_logic ); end component; -- Componente Decodificador para Display LED 7 segmentos component decod7seg is port (C: in std_logic_vector(4 downto 0); F: out std_logic_vector(6 downto 0) ); end component; --------------- INICIO DOS LEVELS ------------------------- begin --- BLOCO DEBOUNCER --- L1: ButtonSync port map(KEY(0), KEY(1), KEY(2), KEY(3), CLOCK_50, btn0, btn1, btn2, btn3); -- Debouncer --- BLOCO MAPAS --- L2: map1 port map(MAP1F0, MAP1F1, MAP1F2, MAP1F3, MAP1F4, MAP1F5, MAP1F6, MAP1F7, MAP1F8, MAP1F9, MAP1F10, MAP1F11, MAP1F12, MAP1F13, MAP1F14, MAP1F15); -- Mapa1 L3: map2 port map(MAP2F0, MAP2F1, MAP2F2, MAP2F3, MAP2F4, MAP2F5, MAP2F6, MAP2F7, MAP2F8, MAP2F9, MAP2F10, MAP2F11, MAP2F12, MAP2F13, MAP2F14, MAP2F15); -- Mapa2 L4: map3 port map(MAP3F0, MAP3F1, MAP3F2, MAP3F3, MAP3F4, MAP3F5, MAP3F6, MAP3F7, MAP3F8, MAP3F9, MAP3F10, MAP3F11, MAP3F12, MAP3F13, MAP3F14, MAP3F15); -- Mapa3 L5: map4 port map(MAP4F0, MAP4F1, MAP4F2, MAP4F3, MAP4F4, MAP4F5, MAP4F6, MAP4F7, MAP4F8, MAP4F9, MAP4F10, MAP4F11, MAP4F12, MAP4F13, MAP4F14, MAP4F15); -- Mapa4 --- BLOCO CONTADORES --- L6: FSM_clock port map(CLOCK_50, clock1, clock2, clock3, clock4, clock5, clockled); -- FSM Clock L7: Conta_des port map(en_timee, clock1, reset, cnt_d); -- Contador Descendente Tempo 99 -> 00 L8: Conta_asc port map(en_timee, clockm, reset, speed, cnt_u); -- Contador Ascendente Posicao L9: Conta_bonus port map(en_timee, reg_out(31), clockm, reset, cnt_b); -- Contador Descendente Bonus / Vida --- BLOCO COMPARADORES E SOMADORES --- L10: compare_10 port map(compare_end_time, cnt_d, end_time); -- Comparador 10 bits Fim Tempo L11: compare_10 port map(compare_target, cnt_u, target); -- Comparador 10 bits Target - Ganhou jogo L12: compare_5 port map(compare_bonus, cnt_b, end_bonus); -- Comparador 5 bits Fim Bonus / Vida L13: adder_10 port map(soma, cnt_u, point); -- Somador 10 bits Pontos --- BLOCO REGISTRADORES --- L14: FSM_position port map(clockm, reset, en_timee, SW(2), SW(0), speed, up_down); -- FSM Posicao L15: FSM_speed port map(CLOCK_50, reset, btn3, btn2, en_timee, speed); -- FSM Velocidade L16: rot_32 port map(set_rol, en_timee, clockm, reset, speed, reg_in0, reg_out0); -- Deslocamento e rotacao a esquerda da fila / linha 0 L17: rot_32 port map(set_rol, en_timee, clockm, reset, speed, reg_in1, reg_out1); -- Deslocamento e rotacao a esquerda da fila / linha 1 L18: rot_32 port map(set_rol, en_timee, clockm, reset, speed, reg_in2, reg_out2); -- Deslocamento e rotacao a esquerda da fila / linha 2 L19: rot_32 port map(set_rol, en_timee, clockm, reset, speed, reg_in3, reg_out3); -- Deslocamento e rotacao a esquerda da fila / linha 3 L20: rot_32 port map(set_rol, en_timee, clockm, reset, speed, reg_in4, reg_out4); -- Deslocamento e rotacao a esquerda da fila / linha 4 L21: rot_32 port map(set_rol, en_timee, clockm, reset, speed, reg_in5, reg_out5); -- Deslocamento e rotacao a esquerda da fila / linha 5 L22: rot_32 port map(set_rol, en_timee, clockm, reset, speed, reg_in6, reg_out6); -- Deslocamento e rotacao a esquerda da fila / linha 6 L23: rot_32 port map(set_rol, en_timee, clockm, reset, speed, reg_in7, reg_out7); -- Deslocamento e rotacao a esquerda da fila / linha 7 L24: rot_32 port map(set_rol, en_timee, clockm, reset, speed, reg_in8, reg_out8); -- Deslocamento e rotacao a esquerda da fila / linha 8 L25: rot_32 port map(set_rol, en_timee, clockm, reset, speed, reg_in9, reg_out9); -- Deslocamento e rotacao a esquerda da fila / linha 9 L26: rot_32 port map(set_rol, en_timee, clockm, reset, speed, reg_in10, reg_out10); -- Deslocamento e rotacao a esquerda da fila / linha 10 L27: rot_32 port map(set_rol, en_timee, clockm, reset, speed, reg_in11, reg_out11); -- Deslocamento e rotacao a esquerda da fila / linha 11 L28: rot_32 port map(set_rol, en_timee, clockm, reset, speed, reg_in12, reg_out12); -- Deslocamento e rotacao a esquerda da fila / linha 12 L29: rot_32 port map(set_rol, en_timee, clockm, reset, speed, reg_in13, reg_out13); -- Deslocamento e rotacao a esquerda da fila / linha 13 L30: rot_32 port map(set_rol, en_timee, clockm, reset, speed, reg_in14, reg_out14); -- Deslocamento e rotacao a esquerda da fila / linha 14 L31: rot_32 port map(set_rol, en_timee, clockm, reset, speed, reg_in15, reg_out15); -- Deslocamento e rotacao a esquerda da fila / linha 15 --- BLOCO CONTROLADOR --- L32: FSM_control port map( CLOCK_50, btn0, end_bonus, end_time, btn1, target, sel_disp, states, sel_led, set_rol, en_timee, reset); -- FSM de Controle --- BLOCO CONTROLADOR --- L33: mux4x1_32 port map(MAP1F0, MAP2F0, MAP3F0, MAP4F0, reg_in0, SW(8 downto 7)); -- Seleciona Mapa Fila 0 L34: mux4x1_32 port map(MAP1F1, MAP2F1, MAP3F1, MAP4F1, reg_in1, SW(8 downto 7)); -- Seleciona Mapa Fila 1 L35: mux4x1_32 port map(MAP1F2, MAP2F2, MAP3F2, MAP4F2, reg_in2, SW(8 downto 7)); -- Seleciona Mapa Fila 2 L36: mux4x1_32 port map(MAP1F3, MAP2F3, MAP3F3, MAP4F3, reg_in3, SW(8 downto 7)); -- Seleciona Mapa Fila 3 L37: mux4x1_32 port map(MAP1F4, MAP2F4, MAP3F4, MAP4F4, reg_in4, SW(8 downto 7)); -- Seleciona Mapa Fila 4 L38: mux4x1_32 port map(MAP1F5, MAP2F5, MAP3F5, MAP4F5, reg_in5, SW(8 downto 7)); -- Seleciona Mapa Fila 5 L39: mux4x1_32 port map(MAP1F6, MAP2F6, MAP3F6, MAP4F6, reg_in6, SW(8 downto 7)); -- Seleciona Mapa Fila 6 L40: mux4x1_32 port map(MAP1F7, MAP2F7, MAP3F7, MAP4F7, reg_in7, SW(8 downto 7)); -- Seleciona Mapa Fila 7 L41: mux4x1_32 port map(MAP1F8, MAP2F8, MAP3F8, MAP4F8, reg_in8, SW(8 downto 7)); -- Seleciona Mapa Fila 8 L42: mux4x1_32 port map(MAP1F9, MAP2F9, MAP3F9, MAP4F9, reg_in9, SW(8 downto 7)); -- Seleciona Mapa Fila 9 L43: mux4x1_32 port map(MAP1F10, MAP2F10, MAP3F10, MAP4F10, reg_in10, SW(8 downto 7)); -- Seleciona Mapa Fila 10 L44: mux4x1_32 port map(MAP1F11, MAP2F11, MAP3F11, MAP4F11, reg_in11, SW(8 downto 7)); -- Seleciona Mapa Fila 11 L45: mux4x1_32 port map(MAP1F12, MAP2F12, MAP3F12, MAP4F12, reg_in12, SW(8 downto 7)); -- Seleciona Mapa Fila 12 L46: mux4x1_32 port map(MAP1F13, MAP2F13, MAP3F13, MAP4F13, reg_in13, SW(8 downto 7)); -- Seleciona Mapa Fila 13 L47: mux4x1_32 port map(MAP1F14, MAP2F14, MAP3F14, MAP4F14, reg_in14, SW(8 downto 7)); -- Seleciona Mapa Fila 14 L48: mux4x1_32 port map(MAP1F15, MAP2F15, MAP3F15, MAP4F15, reg_in15, SW(8 downto 7)); -- Seleciona Mapa Fila 15 L49: mux4x1_30 port map(screen, mux1, mux2, mux3, hx, sel_disp); -- Multiplexador display L50: mux8x1 port map(clock1, clock1, clock2, clock3, clock4, clock5, clock1, clock1, clockm, speed); -- Multiplexador clocks L51: mux16x1_32 port map( reg_out0, reg_out1, reg_out2, reg_out3, reg_out4, reg_out5, reg_out6, reg_out7, reg_out8, reg_out9, reg_out10, reg_out11, reg_out12, reg_out13, reg_out14, reg_out15, reg_out, up_down); -- Multiplexador Registradores Mapa saida L52: mux2x1_10 port map(mux2_sig1, mux2_sig2, led_out, sel_led); -- Multiplexador saida LEDS L53: mux2x1_30 port map(mux2_30_sig1, mux2_30_sig2, screen, SW(9)); -- Multiplexador saida Display L54: decod7seg port map(hx(29 downto 25), HEX5); -- Decodificador 1 LED 7 segmentos L55: decod7seg port map(hx(24 downto 20), HEX4); -- Decodificador 2 LED 7 segmentos L56: decod7seg port map(hx(19 downto 15), HEX3); -- Decodificador 3 LED 7 segmentos L57: decod7seg port map(hx(14 downto 10), HEX2); -- Decodificador 4 LED 7 segmentos L58: decod7seg port map(hx(9 downto 5), HEX1); -- Decodificador 5 LED 7 segmentos L59: decod7seg port map(hx(4 downto 0), HEX0); -- Decodificador 6 LED 7 segmentos LEDR(9) <= clockled; LEDR(8 downto 0) <= led_out(8 downto 0); end topo_stru; --------------- FIM DO CODIGO -------------------------
mit
1059e31f7de4c022c9cec3c561e3769b
0.695206
2.544781
false
false
false
false
fquinto/Wireless_sensor_network
Avnet_UPC/hdl/mdm_0_wrapper.vhd
1
17,527
------------------------------------------------------------------------------- -- mdm_0_wrapper.vhd ------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; library mdm_v2_00_a; use mdm_v2_00_a.all; entity mdm_0_wrapper is port ( Interrupt : out std_logic; Debug_SYS_Rst : out std_logic; Ext_BRK : out std_logic; Ext_NM_BRK : out std_logic; S_AXI_ACLK : in std_logic; S_AXI_ARESETN : in std_logic; S_AXI_AWADDR : in std_logic_vector(31 downto 0); S_AXI_AWVALID : in std_logic; S_AXI_AWREADY : out std_logic; S_AXI_WDATA : in std_logic_vector(31 downto 0); S_AXI_WSTRB : in std_logic_vector(3 downto 0); S_AXI_WVALID : in std_logic; S_AXI_WREADY : out std_logic; S_AXI_BRESP : out std_logic_vector(1 downto 0); S_AXI_BVALID : out std_logic; S_AXI_BREADY : in std_logic; S_AXI_ARADDR : in std_logic_vector(31 downto 0); S_AXI_ARVALID : in std_logic; S_AXI_ARREADY : out std_logic; S_AXI_RDATA : out std_logic_vector(31 downto 0); S_AXI_RRESP : out std_logic_vector(1 downto 0); S_AXI_RVALID : out std_logic; S_AXI_RREADY : in std_logic; SPLB_Clk : in std_logic; SPLB_Rst : in std_logic; PLB_ABus : in std_logic_vector(0 to 31); PLB_UABus : in std_logic_vector(0 to 31); PLB_PAValid : in std_logic; PLB_SAValid : in std_logic; PLB_rdPrim : in std_logic; PLB_wrPrim : in std_logic; PLB_masterID : in std_logic_vector(0 to 0); PLB_abort : in std_logic; PLB_busLock : in std_logic; PLB_RNW : in std_logic; PLB_BE : in std_logic_vector(0 to 3); PLB_MSize : in std_logic_vector(0 to 1); PLB_size : in std_logic_vector(0 to 3); PLB_type : in std_logic_vector(0 to 2); PLB_lockErr : in std_logic; PLB_wrDBus : in std_logic_vector(0 to 31); PLB_wrBurst : in std_logic; PLB_rdBurst : in std_logic; PLB_wrPendReq : in std_logic; PLB_rdPendReq : in std_logic; PLB_wrPendPri : in std_logic_vector(0 to 1); PLB_rdPendPri : in std_logic_vector(0 to 1); PLB_reqPri : in std_logic_vector(0 to 1); PLB_TAttribute : in std_logic_vector(0 to 15); Sl_addrAck : out std_logic; Sl_SSize : out std_logic_vector(0 to 1); Sl_wait : out std_logic; Sl_rearbitrate : out std_logic; Sl_wrDAck : out std_logic; Sl_wrComp : out std_logic; Sl_wrBTerm : out std_logic; Sl_rdDBus : out std_logic_vector(0 to 31); Sl_rdWdAddr : out std_logic_vector(0 to 3); Sl_rdDAck : out std_logic; Sl_rdComp : out std_logic; Sl_rdBTerm : out std_logic; Sl_MBusy : out std_logic_vector(0 to 1); Sl_MWrErr : out std_logic_vector(0 to 1); Sl_MRdErr : out std_logic_vector(0 to 1); Sl_MIRQ : out std_logic_vector(0 to 1); Dbg_Clk_0 : out std_logic; Dbg_TDI_0 : out std_logic; Dbg_TDO_0 : in std_logic; Dbg_Reg_En_0 : out std_logic_vector(0 to 7); Dbg_Capture_0 : out std_logic; Dbg_Shift_0 : out std_logic; Dbg_Update_0 : out std_logic; Dbg_Rst_0 : out std_logic; Dbg_Clk_1 : out std_logic; Dbg_TDI_1 : out std_logic; Dbg_TDO_1 : in std_logic; Dbg_Reg_En_1 : out std_logic_vector(0 to 7); Dbg_Capture_1 : out std_logic; Dbg_Shift_1 : out std_logic; Dbg_Update_1 : out std_logic; Dbg_Rst_1 : out std_logic; Dbg_Clk_2 : out std_logic; Dbg_TDI_2 : out std_logic; Dbg_TDO_2 : in std_logic; Dbg_Reg_En_2 : out std_logic_vector(0 to 7); Dbg_Capture_2 : out std_logic; Dbg_Shift_2 : out std_logic; Dbg_Update_2 : out std_logic; Dbg_Rst_2 : out std_logic; Dbg_Clk_3 : out std_logic; Dbg_TDI_3 : out std_logic; Dbg_TDO_3 : in std_logic; Dbg_Reg_En_3 : out std_logic_vector(0 to 7); Dbg_Capture_3 : out std_logic; Dbg_Shift_3 : out std_logic; Dbg_Update_3 : out std_logic; Dbg_Rst_3 : out std_logic; Dbg_Clk_4 : out std_logic; Dbg_TDI_4 : out std_logic; Dbg_TDO_4 : in std_logic; Dbg_Reg_En_4 : out std_logic_vector(0 to 7); Dbg_Capture_4 : out std_logic; Dbg_Shift_4 : out std_logic; Dbg_Update_4 : out std_logic; Dbg_Rst_4 : out std_logic; Dbg_Clk_5 : out std_logic; Dbg_TDI_5 : out std_logic; Dbg_TDO_5 : in std_logic; Dbg_Reg_En_5 : out std_logic_vector(0 to 7); Dbg_Capture_5 : out std_logic; Dbg_Shift_5 : out std_logic; Dbg_Update_5 : out std_logic; Dbg_Rst_5 : out std_logic; Dbg_Clk_6 : out std_logic; Dbg_TDI_6 : out std_logic; Dbg_TDO_6 : in std_logic; Dbg_Reg_En_6 : out std_logic_vector(0 to 7); Dbg_Capture_6 : out std_logic; Dbg_Shift_6 : out std_logic; Dbg_Update_6 : out std_logic; Dbg_Rst_6 : out std_logic; Dbg_Clk_7 : out std_logic; Dbg_TDI_7 : out std_logic; Dbg_TDO_7 : in std_logic; Dbg_Reg_En_7 : out std_logic_vector(0 to 7); Dbg_Capture_7 : out std_logic; Dbg_Shift_7 : out std_logic; Dbg_Update_7 : out std_logic; Dbg_Rst_7 : out std_logic; bscan_tdi : out std_logic; bscan_reset : out std_logic; bscan_shift : out std_logic; bscan_update : out std_logic; bscan_capture : out std_logic; bscan_sel1 : out std_logic; bscan_drck1 : out std_logic; bscan_tdo1 : in std_logic; Ext_JTAG_DRCK : out std_logic; Ext_JTAG_RESET : out std_logic; Ext_JTAG_SEL : out std_logic; Ext_JTAG_CAPTURE : out std_logic; Ext_JTAG_SHIFT : out std_logic; Ext_JTAG_UPDATE : out std_logic; Ext_JTAG_TDI : out std_logic; Ext_JTAG_TDO : in std_logic ); attribute x_core_info : STRING; attribute x_core_info of mdm_0_wrapper : entity is "mdm_v2_00_a"; end mdm_0_wrapper; architecture STRUCTURE of mdm_0_wrapper is component mdm is generic ( C_FAMILY : STRING; C_JTAG_CHAIN : INTEGER; C_INTERCONNECT : INTEGER; C_BASEADDR : STD_LOGIC_VECTOR; C_HIGHADDR : STD_LOGIC_VECTOR; C_SPLB_AWIDTH : INTEGER; C_SPLB_DWIDTH : INTEGER; C_SPLB_P2P : INTEGER; C_SPLB_MID_WIDTH : INTEGER; C_SPLB_NUM_MASTERS : INTEGER; C_SPLB_NATIVE_DWIDTH : INTEGER; C_SPLB_SUPPORT_BURSTS : INTEGER; C_MB_DBG_PORTS : INTEGER; C_USE_UART : INTEGER; C_S_AXI_ADDR_WIDTH : INTEGER; C_S_AXI_DATA_WIDTH : INTEGER ); port ( Interrupt : out std_logic; Debug_SYS_Rst : out std_logic; Ext_BRK : out std_logic; Ext_NM_BRK : out std_logic; S_AXI_ACLK : in std_logic; S_AXI_ARESETN : in std_logic; S_AXI_AWADDR : in std_logic_vector((C_S_AXI_ADDR_WIDTH-1) downto 0); S_AXI_AWVALID : in std_logic; S_AXI_AWREADY : out std_logic; S_AXI_WDATA : in std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0); S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8-1) downto 0); S_AXI_WVALID : in std_logic; S_AXI_WREADY : out std_logic; S_AXI_BRESP : out std_logic_vector(1 downto 0); S_AXI_BVALID : out std_logic; S_AXI_BREADY : in std_logic; S_AXI_ARADDR : in std_logic_vector((C_S_AXI_ADDR_WIDTH-1) downto 0); S_AXI_ARVALID : in std_logic; S_AXI_ARREADY : out std_logic; S_AXI_RDATA : out std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0); S_AXI_RRESP : out std_logic_vector(1 downto 0); S_AXI_RVALID : out std_logic; S_AXI_RREADY : in std_logic; SPLB_Clk : in std_logic; SPLB_Rst : in std_logic; PLB_ABus : in std_logic_vector(0 to 31); PLB_UABus : in std_logic_vector(0 to 31); PLB_PAValid : in std_logic; PLB_SAValid : in std_logic; PLB_rdPrim : in std_logic; PLB_wrPrim : in std_logic; PLB_masterID : in std_logic_vector(0 to (C_SPLB_MID_WIDTH-1)); PLB_abort : in std_logic; PLB_busLock : in std_logic; PLB_RNW : in std_logic; PLB_BE : in std_logic_vector(0 to ((C_SPLB_DWIDTH/8)-1)); PLB_MSize : in std_logic_vector(0 to 1); PLB_size : in std_logic_vector(0 to 3); PLB_type : in std_logic_vector(0 to 2); PLB_lockErr : in std_logic; PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_DWIDTH-1)); PLB_wrBurst : in std_logic; PLB_rdBurst : in std_logic; PLB_wrPendReq : in std_logic; PLB_rdPendReq : in std_logic; PLB_wrPendPri : in std_logic_vector(0 to 1); PLB_rdPendPri : in std_logic_vector(0 to 1); PLB_reqPri : in std_logic_vector(0 to 1); PLB_TAttribute : in std_logic_vector(0 to 15); Sl_addrAck : out std_logic; Sl_SSize : out std_logic_vector(0 to 1); Sl_wait : out std_logic; Sl_rearbitrate : out std_logic; Sl_wrDAck : out std_logic; Sl_wrComp : out std_logic; Sl_wrBTerm : out std_logic; Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_DWIDTH-1)); Sl_rdWdAddr : out std_logic_vector(0 to 3); Sl_rdDAck : out std_logic; Sl_rdComp : out std_logic; Sl_rdBTerm : out std_logic; Sl_MBusy : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1)); Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1)); Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1)); Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1)); Dbg_Clk_0 : out std_logic; Dbg_TDI_0 : out std_logic; Dbg_TDO_0 : in std_logic; Dbg_Reg_En_0 : out std_logic_vector(0 to 7); Dbg_Capture_0 : out std_logic; Dbg_Shift_0 : out std_logic; Dbg_Update_0 : out std_logic; Dbg_Rst_0 : out std_logic; Dbg_Clk_1 : out std_logic; Dbg_TDI_1 : out std_logic; Dbg_TDO_1 : in std_logic; Dbg_Reg_En_1 : out std_logic_vector(0 to 7); Dbg_Capture_1 : out std_logic; Dbg_Shift_1 : out std_logic; Dbg_Update_1 : out std_logic; Dbg_Rst_1 : out std_logic; Dbg_Clk_2 : out std_logic; Dbg_TDI_2 : out std_logic; Dbg_TDO_2 : in std_logic; Dbg_Reg_En_2 : out std_logic_vector(0 to 7); Dbg_Capture_2 : out std_logic; Dbg_Shift_2 : out std_logic; Dbg_Update_2 : out std_logic; Dbg_Rst_2 : out std_logic; Dbg_Clk_3 : out std_logic; Dbg_TDI_3 : out std_logic; Dbg_TDO_3 : in std_logic; Dbg_Reg_En_3 : out std_logic_vector(0 to 7); Dbg_Capture_3 : out std_logic; Dbg_Shift_3 : out std_logic; Dbg_Update_3 : out std_logic; Dbg_Rst_3 : out std_logic; Dbg_Clk_4 : out std_logic; Dbg_TDI_4 : out std_logic; Dbg_TDO_4 : in std_logic; Dbg_Reg_En_4 : out std_logic_vector(0 to 7); Dbg_Capture_4 : out std_logic; Dbg_Shift_4 : out std_logic; Dbg_Update_4 : out std_logic; Dbg_Rst_4 : out std_logic; Dbg_Clk_5 : out std_logic; Dbg_TDI_5 : out std_logic; Dbg_TDO_5 : in std_logic; Dbg_Reg_En_5 : out std_logic_vector(0 to 7); Dbg_Capture_5 : out std_logic; Dbg_Shift_5 : out std_logic; Dbg_Update_5 : out std_logic; Dbg_Rst_5 : out std_logic; Dbg_Clk_6 : out std_logic; Dbg_TDI_6 : out std_logic; Dbg_TDO_6 : in std_logic; Dbg_Reg_En_6 : out std_logic_vector(0 to 7); Dbg_Capture_6 : out std_logic; Dbg_Shift_6 : out std_logic; Dbg_Update_6 : out std_logic; Dbg_Rst_6 : out std_logic; Dbg_Clk_7 : out std_logic; Dbg_TDI_7 : out std_logic; Dbg_TDO_7 : in std_logic; Dbg_Reg_En_7 : out std_logic_vector(0 to 7); Dbg_Capture_7 : out std_logic; Dbg_Shift_7 : out std_logic; Dbg_Update_7 : out std_logic; Dbg_Rst_7 : out std_logic; bscan_tdi : out std_logic; bscan_reset : out std_logic; bscan_shift : out std_logic; bscan_update : out std_logic; bscan_capture : out std_logic; bscan_sel1 : out std_logic; bscan_drck1 : out std_logic; bscan_tdo1 : in std_logic; Ext_JTAG_DRCK : out std_logic; Ext_JTAG_RESET : out std_logic; Ext_JTAG_SEL : out std_logic; Ext_JTAG_CAPTURE : out std_logic; Ext_JTAG_SHIFT : out std_logic; Ext_JTAG_UPDATE : out std_logic; Ext_JTAG_TDI : out std_logic; Ext_JTAG_TDO : in std_logic ); end component; begin mdm_0 : mdm generic map ( C_FAMILY => "spartan3a", C_JTAG_CHAIN => 2, C_INTERCONNECT => 1, C_BASEADDR => X"84400000", C_HIGHADDR => X"8440ffff", C_SPLB_AWIDTH => 32, C_SPLB_DWIDTH => 32, C_SPLB_P2P => 0, C_SPLB_MID_WIDTH => 1, C_SPLB_NUM_MASTERS => 2, C_SPLB_NATIVE_DWIDTH => 32, C_SPLB_SUPPORT_BURSTS => 0, C_MB_DBG_PORTS => 1, C_USE_UART => 1, C_S_AXI_ADDR_WIDTH => 32, C_S_AXI_DATA_WIDTH => 32 ) port map ( Interrupt => Interrupt, Debug_SYS_Rst => Debug_SYS_Rst, Ext_BRK => Ext_BRK, Ext_NM_BRK => Ext_NM_BRK, S_AXI_ACLK => S_AXI_ACLK, S_AXI_ARESETN => S_AXI_ARESETN, S_AXI_AWADDR => S_AXI_AWADDR, S_AXI_AWVALID => S_AXI_AWVALID, S_AXI_AWREADY => S_AXI_AWREADY, S_AXI_WDATA => S_AXI_WDATA, S_AXI_WSTRB => S_AXI_WSTRB, S_AXI_WVALID => S_AXI_WVALID, S_AXI_WREADY => S_AXI_WREADY, S_AXI_BRESP => S_AXI_BRESP, S_AXI_BVALID => S_AXI_BVALID, S_AXI_BREADY => S_AXI_BREADY, S_AXI_ARADDR => S_AXI_ARADDR, S_AXI_ARVALID => S_AXI_ARVALID, S_AXI_ARREADY => S_AXI_ARREADY, S_AXI_RDATA => S_AXI_RDATA, S_AXI_RRESP => S_AXI_RRESP, S_AXI_RVALID => S_AXI_RVALID, S_AXI_RREADY => S_AXI_RREADY, SPLB_Clk => SPLB_Clk, SPLB_Rst => SPLB_Rst, PLB_ABus => PLB_ABus, PLB_UABus => PLB_UABus, PLB_PAValid => PLB_PAValid, PLB_SAValid => PLB_SAValid, PLB_rdPrim => PLB_rdPrim, PLB_wrPrim => PLB_wrPrim, PLB_masterID => PLB_masterID, PLB_abort => PLB_abort, PLB_busLock => PLB_busLock, PLB_RNW => PLB_RNW, PLB_BE => PLB_BE, PLB_MSize => PLB_MSize, PLB_size => PLB_size, PLB_type => PLB_type, PLB_lockErr => PLB_lockErr, PLB_wrDBus => PLB_wrDBus, PLB_wrBurst => PLB_wrBurst, PLB_rdBurst => PLB_rdBurst, PLB_wrPendReq => PLB_wrPendReq, PLB_rdPendReq => PLB_rdPendReq, PLB_wrPendPri => PLB_wrPendPri, PLB_rdPendPri => PLB_rdPendPri, PLB_reqPri => PLB_reqPri, PLB_TAttribute => PLB_TAttribute, Sl_addrAck => Sl_addrAck, Sl_SSize => Sl_SSize, Sl_wait => Sl_wait, Sl_rearbitrate => Sl_rearbitrate, Sl_wrDAck => Sl_wrDAck, Sl_wrComp => Sl_wrComp, Sl_wrBTerm => Sl_wrBTerm, Sl_rdDBus => Sl_rdDBus, Sl_rdWdAddr => Sl_rdWdAddr, Sl_rdDAck => Sl_rdDAck, Sl_rdComp => Sl_rdComp, Sl_rdBTerm => Sl_rdBTerm, Sl_MBusy => Sl_MBusy, Sl_MWrErr => Sl_MWrErr, Sl_MRdErr => Sl_MRdErr, Sl_MIRQ => Sl_MIRQ, Dbg_Clk_0 => Dbg_Clk_0, Dbg_TDI_0 => Dbg_TDI_0, Dbg_TDO_0 => Dbg_TDO_0, Dbg_Reg_En_0 => Dbg_Reg_En_0, Dbg_Capture_0 => Dbg_Capture_0, Dbg_Shift_0 => Dbg_Shift_0, Dbg_Update_0 => Dbg_Update_0, Dbg_Rst_0 => Dbg_Rst_0, Dbg_Clk_1 => Dbg_Clk_1, Dbg_TDI_1 => Dbg_TDI_1, Dbg_TDO_1 => Dbg_TDO_1, Dbg_Reg_En_1 => Dbg_Reg_En_1, Dbg_Capture_1 => Dbg_Capture_1, Dbg_Shift_1 => Dbg_Shift_1, Dbg_Update_1 => Dbg_Update_1, Dbg_Rst_1 => Dbg_Rst_1, Dbg_Clk_2 => Dbg_Clk_2, Dbg_TDI_2 => Dbg_TDI_2, Dbg_TDO_2 => Dbg_TDO_2, Dbg_Reg_En_2 => Dbg_Reg_En_2, Dbg_Capture_2 => Dbg_Capture_2, Dbg_Shift_2 => Dbg_Shift_2, Dbg_Update_2 => Dbg_Update_2, Dbg_Rst_2 => Dbg_Rst_2, Dbg_Clk_3 => Dbg_Clk_3, Dbg_TDI_3 => Dbg_TDI_3, Dbg_TDO_3 => Dbg_TDO_3, Dbg_Reg_En_3 => Dbg_Reg_En_3, Dbg_Capture_3 => Dbg_Capture_3, Dbg_Shift_3 => Dbg_Shift_3, Dbg_Update_3 => Dbg_Update_3, Dbg_Rst_3 => Dbg_Rst_3, Dbg_Clk_4 => Dbg_Clk_4, Dbg_TDI_4 => Dbg_TDI_4, Dbg_TDO_4 => Dbg_TDO_4, Dbg_Reg_En_4 => Dbg_Reg_En_4, Dbg_Capture_4 => Dbg_Capture_4, Dbg_Shift_4 => Dbg_Shift_4, Dbg_Update_4 => Dbg_Update_4, Dbg_Rst_4 => Dbg_Rst_4, Dbg_Clk_5 => Dbg_Clk_5, Dbg_TDI_5 => Dbg_TDI_5, Dbg_TDO_5 => Dbg_TDO_5, Dbg_Reg_En_5 => Dbg_Reg_En_5, Dbg_Capture_5 => Dbg_Capture_5, Dbg_Shift_5 => Dbg_Shift_5, Dbg_Update_5 => Dbg_Update_5, Dbg_Rst_5 => Dbg_Rst_5, Dbg_Clk_6 => Dbg_Clk_6, Dbg_TDI_6 => Dbg_TDI_6, Dbg_TDO_6 => Dbg_TDO_6, Dbg_Reg_En_6 => Dbg_Reg_En_6, Dbg_Capture_6 => Dbg_Capture_6, Dbg_Shift_6 => Dbg_Shift_6, Dbg_Update_6 => Dbg_Update_6, Dbg_Rst_6 => Dbg_Rst_6, Dbg_Clk_7 => Dbg_Clk_7, Dbg_TDI_7 => Dbg_TDI_7, Dbg_TDO_7 => Dbg_TDO_7, Dbg_Reg_En_7 => Dbg_Reg_En_7, Dbg_Capture_7 => Dbg_Capture_7, Dbg_Shift_7 => Dbg_Shift_7, Dbg_Update_7 => Dbg_Update_7, Dbg_Rst_7 => Dbg_Rst_7, bscan_tdi => bscan_tdi, bscan_reset => bscan_reset, bscan_shift => bscan_shift, bscan_update => bscan_update, bscan_capture => bscan_capture, bscan_sel1 => bscan_sel1, bscan_drck1 => bscan_drck1, bscan_tdo1 => bscan_tdo1, Ext_JTAG_DRCK => Ext_JTAG_DRCK, Ext_JTAG_RESET => Ext_JTAG_RESET, Ext_JTAG_SEL => Ext_JTAG_SEL, Ext_JTAG_CAPTURE => Ext_JTAG_CAPTURE, Ext_JTAG_SHIFT => Ext_JTAG_SHIFT, Ext_JTAG_UPDATE => Ext_JTAG_UPDATE, Ext_JTAG_TDI => Ext_JTAG_TDI, Ext_JTAG_TDO => Ext_JTAG_TDO ); end architecture STRUCTURE;
mit
84f726667f212e8d0e7711059c78df0e
0.576824
2.893677
false
false
false
false
tghaefli/ADD
EDK/IVK_Repos/IVK_IPLib/pcores/fmc_imageov_dvi_out_v1_02_d/hdl/vhdl/fmc_imageov_dvi_out.vhd
1
18,039
------------------------------------------------------------------ -- _____ -- / \ -- /____ \____ -- / \===\ \==/ -- /___\===\___\/ AVNET -- \======/ -- \====/ ----------------------------------------------------------------- -- -- This design is the property of Avnet. Publication of this -- design is not authorized without written consent from Avnet. -- -- Please direct any questions to: [email protected] -- -- Disclaimer: -- Avnet, Inc. makes no warranty for the use of this code or design. -- This code is provided "As Is". Avnet, Inc assumes no responsibility for -- any errors, which may appear in this code, nor does it make a commitment -- to update the information contained herein. Avnet, Inc specifically -- disclaims any implied warranties of fitness for a particular purpose. -- Copyright(c) 2010 Avnet, Inc. -- All rights reserved. -- ------------------------------------------------------------------ -- -- Create Date: Jul 03, 2009 -- Design Name: FMC-IMAGEOV -- Module Name: fmc_imageov_dvi_out.vhd -- Project Name: FMC-IMAGEOV -- Target Devices: Spartan-6 -- Avnet Boards: FMC-IMAGEOV -- -- Tool versions: ISE 11.4 -- -- Description: FMC-IMAGEOV DVI output interface. -- Based on VSK dvi_out.vhd and modified as follows: -- - rename dvi_out to fmc_imageov_dvi_out -- - replace dvi_clk_p/dvi_clk_n by single-ended dvi_clk -- - add support for more devices via C_FAMILY generic: -- - spartan3adsp -- - spartan6 -- -- Dependencies: -- -- Revision: Jul 03, 2009: 1.00 Initial version -- Jan 15, 2010: 1.01 Add a second set of regs -- Add an output enable port -- Add oe and reset to debug port -- Feb 01, 2010: 1.02 Add selectable video interface -- Feb 10, 2010: 1.02b Fix XSVI video_data ordering: -- [23:16] = red -- [15: 8] = blue -- [ 7: 0] = green -- May 12, 2010: 1.02c Add V6 support -- ------------------------------------------------------------------ -- DISCLAIMER OF LIABILITY -- -- This text/file contains proprietary, confidential -- information of Xilinx, Inc., is distributed under license -- from Xilinx, Inc., and may be used, copied and/or -- disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a -- license to use this text/file solely for design, simulation, -- implementation and creation of design files limited -- to Xilinx devices or technologies. Use with non-Xilinx -- devices or technologies is expressly prohibited and -- immediately terminates your license unless covered by -- a separate agreement. -- -- Xilinx is providing this design, code, or information -- "as-is" solely for use in developing programs and -- solutions for Xilinx devices, with no obligation on the -- part of Xilinx to provide support. By providing this design, -- code, or information as one possible implementation of -- this feature, application or standard, Xilinx is making no -- representation that this implementation is free from any -- claims of infringement. You are responsible for -- obtaining any rights you may require for your implementation. -- Xilinx expressly disclaims any warranty whatsoever with -- respect to the adequacy of the implementation, including -- but not limited to any warranties or representations that this -- implementation is free from claims of infringement, implied -- warranties of merchantability or fitness for a particular -- purpose. -- -- Xilinx products are not intended for use in life support -- appliances, devices, or systems. Use in such applications is -- expressly prohibited. -- -- Any modifications that are made to the Source Code are -- done at the user’s sole risk and will be unsupported. -- -- -- Copyright (c) 2007, 2008 Xilinx, Inc. All rights reserved. -- -- This copyright and support notice must be retained as part -- of this text at all times. -- ------------------------------------------------------------------------------ -- Filename : dvi_out.vhd -- $Revision:: 2433 $: Revision of last commit -- $Date:: 2008-05-27#$: Date of last commit -- Description : DVI Output Hardware Interface ------------------------------------------------------------------------------ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. library UNISIM; use UNISIM.VComponents.all; entity fmc_imageov_dvi_out is Generic ( C_VIDEO_INTERFACE : integer := 2; C_DATA_WIDTH : integer := 8; C_FAMILY : string := "spartan6" ); Port ( clk : in std_logic; reset : in std_logic; ce : in std_logic; oe : in std_logic; -- DVI Input Port dvi_de_i : in std_logic; dvi_vsync_i : in std_logic; dvi_hsync_i : in std_logic; dvi_red_i : in std_logic_vector(7 downto 0); dvi_green_i : in std_logic_vector(7 downto 0); dvi_blue_i : in std_logic_vector(7 downto 0); -- XSVI Input Port xsvi_vsync_i : in std_logic; xsvi_hsync_i : in std_logic; xsvi_active_video_i: in std_logic; xsvi_video_data_i : in std_logic_vector((C_DATA_WIDTH-1) downto 0); -- I/O pins io_dvi_de : out std_logic; io_dvi_vsync : out std_logic; io_dvi_hsync : out std_logic; io_dvi_data : out std_logic_vector(11 downto 0); io_dvi_clk : out std_logic; io_dvi_reset_n : out std_logic; -- Debug Port debug_o : out std_logic_vector(28 downto 0) ); end fmc_imageov_dvi_out; architecture rtl of fmc_imageov_dvi_out is signal clk_n : std_logic; signal net0 : std_logic; signal net1 : std_logic; signal de_r : std_logic; signal vsync_r : std_logic; signal hsync_r : std_logic; signal red_r : std_logic_vector(7 downto 0); signal green_r : std_logic_vector(7 downto 0); signal blue_r : std_logic_vector(7 downto 0); signal d1 : std_logic_vector(11 downto 0); signal d2 : std_logic_vector(11 downto 0); signal d2_r : std_logic_vector(11 downto 0); signal oe_n : std_logic; signal dvi_de_o : std_logic; signal dvi_vsync_o : std_logic; signal dvi_hsync_o : std_logic; signal dvi_data_o : std_logic_vector(11 downto 0); signal dvi_clk_o : std_logic; signal dvi_reset_n_o : std_logic; signal dvi_de_t : std_logic; signal dvi_vsync_t : std_logic; signal dvi_hsync_t : std_logic; signal dvi_data_t : std_logic_vector(11 downto 0); signal dvi_clk_t : std_logic; signal dvi_reset_n_t : std_logic; begin clk_n <= not clk; net0 <= '0'; net1 <= '1'; dvi_reset_n_o <= not reset; dvi_reset_n_t <= not oe; DVI_IPORT_GEN : if (C_VIDEO_INTERFACE = 1) generate dvi_iregs_l : process (clk) begin if Rising_Edge(clk) then de_r <= dvi_de_i; vsync_r <= dvi_vsync_i; hsync_r <= dvi_hsync_i; red_r <= dvi_red_i; green_r <= dvi_green_i; blue_r <= dvi_blue_i; end if; end process; end generate DVI_IPORT_GEN; XSVI_IPORT_GEN : if (C_VIDEO_INTERFACE = 2) generate XSVI_8BIT_GEN : if (C_DATA_WIDTH = 8) generate xsvi_8bit_iregs_l : process (clk) begin if Rising_Edge(clk) then de_r <= xsvi_active_video_i; vsync_r <= xsvi_vsync_i; hsync_r <= xsvi_hsync_i; red_r <= xsvi_video_data_i(7 downto 0); green_r <= xsvi_video_data_i(7 downto 0); blue_r <= xsvi_video_data_i(7 downto 0); end if; end process; end generate XSVI_8BIT_GEN; XSVI_24BIT_GEN : if (C_DATA_WIDTH = 24) generate xsvi_24bit_iregs_l : process (clk) begin if Rising_Edge(clk) then de_r <= xsvi_active_video_i; vsync_r <= xsvi_vsync_i; hsync_r <= xsvi_hsync_i; red_r <= xsvi_video_data_i(23 downto 16); blue_r <= xsvi_video_data_i( 7 downto 0); green_r <= xsvi_video_data_i(15 downto 8); end if; end process; end generate XSVI_24BIT_GEN; XSVI_30BIT_GEN : if (C_DATA_WIDTH = 30) generate xsvi_20bit_iregs_l : process (clk) begin if Rising_Edge(clk) then de_r <= xsvi_active_video_i; vsync_r <= xsvi_vsync_i; hsync_r <= xsvi_hsync_i; red_r <= xsvi_video_data_i(29 downto 22); green_r <= xsvi_video_data_i( 9 downto 2); blue_r <= xsvi_video_data_i(19 downto 12); end if; end process; end generate XSVI_30BIT_GEN; end generate XSVI_IPORT_GEN; d1 <= green_r(3 downto 0) & blue_r; d2 <= red_r & green_r(7 downto 4); oe_n <= not oe; OUT_Reg : process (clk) begin if Rising_Edge(clk) then dvi_de_o <= de_r; dvi_vsync_o <= vsync_r; dvi_hsync_o <= hsync_r; -- dvi_de_t <= oe_n; dvi_vsync_t <= oe_n; dvi_hsync_t <= oe_n; end if; end process; S3ADSP_GEN : if (C_FAMILY = "spartan3adsp") generate Delay_Reg : process (clk) begin if (clk'event and (clk = '1')) then d2_r <= d2; end if; end process; O1: for I in 0 to 11 generate ODDR_dvi_data_o : ODDR2 generic map ( DDR_ALIGNMENT => "NONE", -- "NONE", "C0" or "C1" INIT => '1', -- Sets initial state of Q SRTYPE => "ASYNC") -- Reset type port map ( Q => dvi_data_o(I), C0 => clk, C1 => clk_n, CE => net1, D0 => d1(I), D1 => d2_r(I), R => net0, S => net0); end generate O1; ODDR_dvi_clk_o : ODDR2 generic map ( DDR_ALIGNMENT => "NONE", -- "NONE", "C0" or "C1" INIT => '1', -- Sets initial state of Q SRTYPE => "ASYNC") -- Reset type port map ( Q => dvi_clk_o, C0 => clk, C1 => clk_n, CE => net1, D0 => net0, D1 => net1, R => net0, S => net0); T1: for I in 0 to 11 generate ODDR_dvi_data_t : ODDR2 generic map ( DDR_ALIGNMENT => "NONE", -- "NONE", "C0" or "C1" INIT => '1', -- Sets initial state of Q SRTYPE => "ASYNC") -- Reset type port map ( Q => dvi_data_t(I), C0 => clk, C1 => clk_n, CE => net1, D0 => oe_n, D1 => oe_n, R => net0, S => net0); end generate T1; ODDR_dvi_clk_t : ODDR2 generic map ( DDR_ALIGNMENT => "NONE", -- "NONE", "C0" or "C1" INIT => '1', -- Sets initial state of Q SRTYPE => "ASYNC") -- Reset type port map ( Q => dvi_clk_t, C0 => clk, C1 => clk_n, CE => net1, D0 => oe_n, D1 => oe_n, R => net0, S => net0); end generate S3ADSP_GEN; S6_GEN : if (C_FAMILY = "spartan6") generate O1: for I in 0 to 11 generate ODDR_dvi_data_o : ODDR2 generic map ( DDR_ALIGNMENT => "C0", -- "NONE", "C0" or "C1" INIT => '1', -- Sets initial state of Q SRTYPE => "ASYNC") -- Reset type port map ( Q => dvi_data_o(I), C0 => clk, C1 => clk_n, CE => net1, D0 => d1(I), D1 => d2(I), R => net0, S => net0); end generate O1; ODDR_dvi_clk_o : ODDR2 generic map ( DDR_ALIGNMENT => "C0", -- "NONE", "C0" or "C1" INIT => '1', -- Sets initial state of Q SRTYPE => "ASYNC") -- Reset type port map ( Q => dvi_clk_o, C0 => clk, C1 => clk_n, CE => net1, D0 => net0, D1 => net1, R => net0, S => net0); T1: for I in 0 to 11 generate ODDR_dvi_data_t : ODDR2 generic map ( DDR_ALIGNMENT => "C0", -- "NONE", "C0" or "C1" INIT => '1', -- Sets initial state of Q SRTYPE => "ASYNC") -- Reset type port map ( Q => dvi_data_t(I), C0 => clk, C1 => clk_n, CE => net1, D0 => oe_n, D1 => oe_n, R => net0, S => net0); end generate T1; ODDR_dvi_clk_t : ODDR2 generic map ( DDR_ALIGNMENT => "C0", -- "NONE", "C0" or "C1" INIT => '1', -- Sets initial state of Q SRTYPE => "ASYNC") -- Reset type port map ( Q => dvi_clk_t, C0 => clk, C1 => clk_n, CE => net1, D0 => oe_n, D1 => oe_n, R => net0, S => net0); end generate S6_GEN; V6_GEN : if (C_FAMILY = "virtex6") generate O1: for I in 0 to 11 generate ODDR_dvi_data_o : ODDR generic map ( DDR_CLK_EDGE => "SAME_EDGE") port map ( Q => dvi_data_o(I), C => clk, CE => net1, D1 => d1(I), D2 => d2(I), R => net0, S => net0); end generate O1; ODDR_dvi_clk_o : ODDR generic map ( DDR_CLK_EDGE => "SAME_EDGE") port map ( Q => dvi_clk_o, C => clk, CE => net1, D1 => net0, D2 => net1, R => net0, S => net0); T1: for I in 0 to 11 generate ODDR_dvi_data_t : ODDR generic map ( DDR_CLK_EDGE => "SAME_EDGE") port map ( Q => dvi_data_t(I), C => clk, CE => net1, D1 => oe_n, D2 => oe_n, R => net0, S => net0); end generate T1; ODDR_dvi_clk_t : ODDR generic map ( DDR_CLK_EDGE => "SAME_EDGE") port map ( Q => dvi_clk_t, C => clk, CE => net1, D1 => oe_n, D2 => oe_n, R => net0, S => net0); end generate V6_GEN; -- -- Tri-stateable outputs -- Can be used to disable outputs to FMC connector -- until FMC module is correctly identified. -- OBUFT_dvi_de : OBUFT port map ( O => io_dvi_de, I => dvi_de_o, T => dvi_de_t ); OBUFT_dvi_vsync : OBUFT port map ( O => io_dvi_vsync, I => dvi_vsync_o, T => dvi_vsync_t ); OBUFT_dvi_hsync : OBUFT port map ( O => io_dvi_hsync, I => dvi_hsync_o, T => dvi_hsync_t ); IO1: for I in 0 to 11 generate OBUFT_dvi_data : OBUFT port map ( O => io_dvi_data(I), I => dvi_data_o(I), T => dvi_data_t(I) ); end generate IO1; OBUFT_dvi_clk : OBUFT port map ( O => io_dvi_clk, I => dvi_clk_o, T => dvi_clk_t ); OBUFT_dvi_reset_n : OBUFT port map ( O => io_dvi_reset_n, I => dvi_reset_n_o, T => dvi_reset_n_t ); -- -- Debug Port -- Can be used to connect to ChipScope for debugging. -- Having a port makes these signals accessible for debug via EDK. -- debug_l : process (clk) begin if Rising_Edge(clk) then debug_o( 7 downto 0) <= blue_r; debug_o(15 downto 8) <= green_r; debug_o(23 downto 16) <= red_r; debug_o( 24) <= de_r; debug_o( 25) <= hsync_r; debug_o( 26) <= vsync_r; debug_o( 27) <= oe; debug_o( 28) <= reset; end if; end process; end rtl;
gpl-3.0
7e4cb8d92ee3778f4da7858ec6a1e97c
0.44997
3.776219
false
false
false
false
fquinto/Wireless_sensor_network
Avnet_UPC/hdl/elaborate/clock_generator_0_v4_00_a/hdl/vhdl/clock_generator.vhd
1
32,348
------------------------------------------------------------------------------ -- C:/Datos/Proyecto/PlacaSpartan3A/Avnet/Avnet_UPC/hdl/elaborate/clock_generator_0_v4_00_a/hdl/vhdl/clock_generator.vhd ------------------------------------------------------------------------------ -- ClkGen Wrapper HDL file generated by ClkGen's TCL generator library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.all; library Unisim; use Unisim.vcomponents.all; library clock_generator_v4_00_a; use clock_generator_v4_00_a.all; entity clock_generator is generic ( C_FAMILY : string := "spartan3a" ; C_DEVICE : string := "3s400a"; C_PACKAGE : string := "ft256"; C_SPEEDGRADE : string := "-4"; C_CLK_GEN : string := "PASSED" ); port ( -- clock generation CLKIN : in std_logic; CLKOUT0 : out std_logic; CLKOUT1 : out std_logic; CLKOUT2 : out std_logic; CLKOUT3 : out std_logic; CLKOUT4 : out std_logic; CLKOUT5 : out std_logic; CLKOUT6 : out std_logic; CLKOUT7 : out std_logic; CLKOUT8 : out std_logic; CLKOUT9 : out std_logic; CLKOUT10 : out std_logic; CLKOUT11 : out std_logic; CLKOUT12 : out std_logic; CLKOUT13 : out std_logic; CLKOUT14 : out std_logic; CLKOUT15 : out std_logic; -- external feedback CLKFBIN : in std_logic; CLKFBOUT : out std_logic; -- variable phase shift PSCLK : in std_logic; PSEN : in std_logic; PSINCDEC : in std_logic; PSDONE : out std_logic; -- reset RST : in std_logic; LOCKED : out std_logic ); end clock_generator; architecture STRUCTURE of clock_generator is ---------------------------------------------------------------------------- -- Components ( copy from entity, exact the same in low level parameters ) ---------------------------------------------------------------------------- component dcm_module is generic ( C_DFS_FREQUENCY_MODE : string := "LOW"; C_DLL_FREQUENCY_MODE : string := "LOW"; C_DUTY_CYCLE_CORRECTION : boolean := true; C_CLKIN_DIVIDE_BY_2 : boolean := false; C_CLK_FEEDBACK : string := "1X"; C_CLKOUT_PHASE_SHIFT : string := "NONE"; C_DSS_MODE : string := "NONE"; C_STARTUP_WAIT : boolean := false; C_PHASE_SHIFT : integer := 0; C_CLKFX_MULTIPLY : integer := 4; C_CLKFX_DIVIDE : integer := 1; C_CLKDV_DIVIDE : real := 2.0; C_CLKIN_PERIOD : real := 41.6666666; C_DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS"; C_CLKIN_BUF : boolean := false; C_CLKFB_BUF : boolean := false; C_CLK0_BUF : boolean := false; C_CLK90_BUF : boolean := false; C_CLK180_BUF : boolean := false; C_CLK270_BUF : boolean := false; C_CLKDV_BUF : boolean := false; C_CLK2X_BUF : boolean := false; C_CLK2X180_BUF : boolean := false; C_CLKFX_BUF : boolean := false; C_CLKFX180_BUF : boolean := false; C_EXT_RESET_HIGH : integer := 1; C_FAMILY : string := "spartan6" ); port ( RST : in std_logic; CLKIN : in std_logic; CLKFB : in std_logic; PSEN : in std_logic; PSINCDEC : in std_logic; PSCLK : in std_logic; DSSEN : in std_logic; CLK0 : out std_logic; CLK90 : out std_logic; CLK180 : out std_logic; CLK270 : out std_logic; CLKDV : out std_logic; CLK2X : out std_logic; CLK2X180 : out std_logic; CLKFX : out std_logic; CLKFX180 : out std_logic; STATUS : out std_logic_vector(7 downto 0); LOCKED : out std_logic; PSDONE : out std_logic ); end component; ---------------------------------------------------------------------------- -- Functions ---------------------------------------------------------------------------- -- Note : The string functions are put here to remove dependency to other pcore level libraries function UpperCase_Char(char : character) return character is begin -- If char is not an upper case letter then return char if char < 'a' or char > 'z' then return char; end if; -- Otherwise map char to its corresponding lower case character and -- return that case char is when 'a' => return 'A'; when 'b' => return 'B'; when 'c' => return 'C'; when 'd' => return 'D'; when 'e' => return 'E'; when 'f' => return 'F'; when 'g' => return 'G'; when 'h' => return 'H'; when 'i' => return 'I'; when 'j' => return 'J'; when 'k' => return 'K'; when 'l' => return 'L'; when 'm' => return 'M'; when 'n' => return 'N'; when 'o' => return 'O'; when 'p' => return 'P'; when 'q' => return 'Q'; when 'r' => return 'R'; when 's' => return 'S'; when 't' => return 'T'; when 'u' => return 'U'; when 'v' => return 'V'; when 'w' => return 'W'; when 'x' => return 'X'; when 'y' => return 'Y'; when 'z' => return 'Z'; when others => return char; end case; end UpperCase_Char; function UpperCase_String (s : string) return string is variable res : string(s'range); begin -- function LoweerCase_String for I in s'range loop res(I) := UpperCase_Char(s(I)); end loop; -- I return res; end function UpperCase_String; -- Returns true if case insensitive string comparison determines that -- str1 and str2 are equal function equalString( str1, str2 : string ) return boolean is constant len1 : integer := str1'length; constant len2 : integer := str2'length; variable equal : boolean := true; begin if not (len1 = len2) then equal := false; else for i in str1'range loop if not (UpperCase_Char(str1(i)) = UpperCase_Char(str2(i))) then equal := false; end if; end loop; end if; return equal; end equalString; ---------------------------------------------------------------------------- -- Signals ---------------------------------------------------------------------------- -- signals: gnd signal net_gnd0 : std_logic; signal net_gnd1 : std_logic_vector(0 to 0); signal net_gnd16 : std_logic_vector(0 to 15); -- signals: vdd signal net_vdd0 : std_logic; -- signals : DCM0 wrapper signal SIG_DCM0_RST : std_logic; signal SIG_DCM0_CLKIN : std_logic; signal SIG_DCM0_CLKFB : std_logic; signal SIG_DCM0_PSEN : std_logic; signal SIG_DCM0_PSINCDEC : std_logic; signal SIG_DCM0_PSCLK : std_logic; signal SIG_DCM0_DSSEN : std_logic; signal SIG_DCM0_CLK0 : std_logic; signal SIG_DCM0_CLK90 : std_logic; signal SIG_DCM0_CLK180 : std_logic; signal SIG_DCM0_CLK270 : std_logic; signal SIG_DCM0_CLKDV : std_logic; signal SIG_DCM0_CLKDV180 : std_logic; signal SIG_DCM0_CLK2X : std_logic; signal SIG_DCM0_CLK2X180 : std_logic; signal SIG_DCM0_CLKFX : std_logic; signal SIG_DCM0_CLKFX180 : std_logic; signal SIG_DCM0_STATUS : std_logic; signal SIG_DCM0_LOCKED : std_logic; signal SIG_DCM0_PSDONE : std_logic; signal SIG_DCM0_CLK0_BUF : std_logic; signal SIG_DCM0_CLK90_BUF : std_logic; signal SIG_DCM0_CLK180_BUF : std_logic; signal SIG_DCM0_CLK270_BUF : std_logic; signal SIG_DCM0_CLKDV_BUF : std_logic; signal SIG_DCM0_CLKDV180_BUF : std_logic; signal SIG_DCM0_CLK2X_BUF : std_logic; signal SIG_DCM0_CLK2X180_BUF : std_logic; signal SIG_DCM0_CLKFX_BUF : std_logic; signal SIG_DCM0_CLKFX180_BUF : std_logic; begin ---------------------------------------------------------------------------- -- GND and VCC signals ---------------------------------------------------------------------------- net_gnd0 <= '0'; net_gnd1(0 to 0) <= B"0"; net_gnd16(0 to 15) <= B"0000000000000000"; net_vdd0 <= '1'; ---------------------------------------------------------------------------- -- DCM wrappers ---------------------------------------------------------------------------- -- DCM0 wrapper DCM0_INST : dcm_module generic map ( C_DFS_FREQUENCY_MODE => "LOW", C_DLL_FREQUENCY_MODE => "LOW", C_DUTY_CYCLE_CORRECTION => true, C_CLKIN_DIVIDE_BY_2 => false, C_CLK_FEEDBACK => "1X", C_CLKOUT_PHASE_SHIFT => "NONE", C_DSS_MODE => "NONE", C_STARTUP_WAIT => false, C_PHASE_SHIFT => 0, C_CLKFX_MULTIPLY => 25, C_CLKFX_DIVIDE => 6, C_CLKDV_DIVIDE => 2.0, C_CLKIN_PERIOD => 62.500000, C_DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", C_CLKIN_BUF => false, C_CLKFB_BUF => false, C_CLK0_BUF => false, C_CLK90_BUF => false, C_CLK180_BUF => false, C_CLK270_BUF => false, C_CLKDV_BUF => false, C_CLK2X_BUF => false, C_CLK2X180_BUF => false, C_CLKFX_BUF => false, C_CLKFX180_BUF => false, C_EXT_RESET_HIGH => 1, C_FAMILY => "spartan3a" ) port map ( RST => SIG_DCM0_RST, CLKIN => SIG_DCM0_CLKIN, CLKFB => SIG_DCM0_CLKFB, PSEN => SIG_DCM0_PSEN, PSINCDEC => SIG_DCM0_PSINCDEC, PSCLK => SIG_DCM0_PSCLK, DSSEN => net_gnd0, CLK0 => SIG_DCM0_CLK0, CLK90 => SIG_DCM0_CLK90, CLK180 => open, CLK270 => open, CLKDV => SIG_DCM0_CLKDV, CLK2X => SIG_DCM0_CLK2X, CLK2X180 => open, CLKFX => SIG_DCM0_CLKFX, CLKFX180 => open, STATUS => open, LOCKED => SIG_DCM0_LOCKED, PSDONE => SIG_DCM0_PSDONE ); -- wrapper of clkout : CLK0 and clkinv : CLK180 DCM0_CLK0_BUFG_INST : BUFG port map ( I => SIG_DCM0_CLK0, O => SIG_DCM0_CLK0_BUF ); SIG_DCM0_CLK180 <= NOT SIG_DCM0_CLK0; SIG_DCM0_CLK180_BUF <= NOT SIG_DCM0_CLK0_BUF; -- wrapper of clkout : CLK90 and clkinv : CLK270 SIG_DCM0_CLK90_BUF <= SIG_DCM0_CLK90; SIG_DCM0_CLK270 <= NOT SIG_DCM0_CLK90; SIG_DCM0_CLK270_BUF <= NOT SIG_DCM0_CLK90_BUF; -- wrapper of clkout : CLK2X and clkinv : CLK2X180 SIG_DCM0_CLK2X_BUF <= SIG_DCM0_CLK2X; SIG_DCM0_CLK2X180 <= NOT SIG_DCM0_CLK2X; SIG_DCM0_CLK2X180_BUF <= NOT SIG_DCM0_CLK2X_BUF; -- wrapper of clkout : CLKDV and clkinv : CLKDV180 SIG_DCM0_CLKDV_BUF <= SIG_DCM0_CLKDV; SIG_DCM0_CLKDV180 <= NOT SIG_DCM0_CLKDV; SIG_DCM0_CLKDV180_BUF <= NOT SIG_DCM0_CLKDV_BUF; -- wrapper of clkout : CLKFX and clkinv : CLKFX180 DCM0_CLKFX_BUFG_INST : BUFG port map ( I => SIG_DCM0_CLKFX, O => SIG_DCM0_CLKFX_BUF ); SIG_DCM0_CLKFX180 <= NOT SIG_DCM0_CLKFX; SIG_DCM0_CLKFX180_BUF <= NOT SIG_DCM0_CLKFX_BUF; ---------------------------------------------------------------------------- -- PLL wrappers ---------------------------------------------------------------------------- ---------------------------------------------------------------------------- -- MMCM wrappers ---------------------------------------------------------------------------- ---------------------------------------------------------------------------- -- DCMs CLKIN, CLKFB and RST signal connection ---------------------------------------------------------------------------- -- DCM0 CLKIN SIG_DCM0_CLKIN <= CLKIN; -- DCM0 CLKFB SIG_DCM0_CLKFB <= SIG_DCM0_CLK0_BUF; -- DCM0 RST SIG_DCM0_RST <= RST; ---------------------------------------------------------------------------- -- PLLs CLKIN1, CLKFBIN and RST signal connection ---------------------------------------------------------------------------- ---------------------------------------------------------------------------- -- MMCMs CLKIN1, CLKFBIN, RST and Variable_Phase_Control signal connection ---------------------------------------------------------------------------- ---------------------------------------------------------------------------- -- CLKGEN CLKOUT, CLKFBOUT and LOCKED signal connection ---------------------------------------------------------------------------- -- CLKGEN CLKOUT CLKOUT0 <= SIG_DCM0_CLKFX_BUF; -- CLKGEN CLKFBOUT -- CLKGEN LOCKED LOCKED <= SIG_DCM0_LOCKED; end architecture STRUCTURE; ------------------------------------------------------------------------------ -- High level parameters ------------------------------------------------------------------------------ -- C_CLK_GEN = PASSED -- C_ELABORATE_DIR = -- C_ELABORATE_RES = NOT_SET -- C_FAMILY = spartan3a -- C_DEVICE = 3s400a -- C_PACKAGE = ft256 -- C_SPEEDGRADE = -4 ---------------------------------------- -- C_CLKIN_FREQ = 16000000 -- C_CLKOUT0_FREQ = 66666666 -- C_CLKOUT0_PHASE = 0 -- C_CLKOUT0_GROUP = NONE -- C_CLKOUT0_BUF = TRUE -- C_CLKOUT0_VARIABLE_PHASE = FALSE -- C_CLKOUT1_FREQ = 0 -- C_CLKOUT1_PHASE = 0 -- C_CLKOUT1_GROUP = NONE -- C_CLKOUT1_BUF = TRUE -- C_CLKOUT1_VARIABLE_PHASE = FALSE -- C_CLKOUT2_FREQ = 0 -- C_CLKOUT2_PHASE = 0 -- C_CLKOUT2_GROUP = NONE -- C_CLKOUT2_BUF = TRUE -- C_CLKOUT2_VARIABLE_PHASE = FALSE -- C_CLKOUT3_FREQ = 0 -- C_CLKOUT3_PHASE = 0 -- C_CLKOUT3_GROUP = NONE -- C_CLKOUT3_BUF = TRUE -- C_CLKOUT3_VARIABLE_PHASE = FALSE -- C_CLKOUT4_FREQ = 0 -- C_CLKOUT4_PHASE = 0 -- C_CLKOUT4_GROUP = NONE -- C_CLKOUT4_BUF = TRUE -- C_CLKOUT4_VARIABLE_PHASE = FALSE -- C_CLKOUT5_FREQ = 0 -- C_CLKOUT5_PHASE = 0 -- C_CLKOUT5_GROUP = NONE -- C_CLKOUT5_BUF = TRUE -- C_CLKOUT5_VARIABLE_PHASE = FALSE -- C_CLKOUT6_FREQ = 0 -- C_CLKOUT6_PHASE = 0 -- C_CLKOUT6_GROUP = NONE -- C_CLKOUT6_BUF = TRUE -- C_CLKOUT6_VARIABLE_PHASE = FALSE -- C_CLKOUT7_FREQ = 0 -- C_CLKOUT7_PHASE = 0 -- C_CLKOUT7_GROUP = NONE -- C_CLKOUT7_BUF = TRUE -- C_CLKOUT7_VARIABLE_PHASE = FALSE -- C_CLKOUT8_FREQ = 0 -- C_CLKOUT8_PHASE = 0 -- C_CLKOUT8_GROUP = NONE -- C_CLKOUT8_BUF = TRUE -- C_CLKOUT8_VARIABLE_PHASE = FALSE -- C_CLKOUT9_FREQ = 0 -- C_CLKOUT9_PHASE = 0 -- C_CLKOUT9_GROUP = NONE -- C_CLKOUT9_BUF = TRUE -- C_CLKOUT9_VARIABLE_PHASE = FALSE -- C_CLKOUT10_FREQ = 0 -- C_CLKOUT10_PHASE = 0 -- C_CLKOUT10_GROUP = NONE -- C_CLKOUT10_BUF = TRUE -- C_CLKOUT10_VARIABLE_PHASE = FALSE -- C_CLKOUT11_FREQ = 0 -- C_CLKOUT11_PHASE = 0 -- C_CLKOUT11_GROUP = NONE -- C_CLKOUT11_BUF = TRUE -- C_CLKOUT11_VARIABLE_PHASE = FALSE -- C_CLKOUT12_FREQ = 0 -- C_CLKOUT12_PHASE = 0 -- C_CLKOUT12_GROUP = NONE -- C_CLKOUT12_BUF = TRUE -- C_CLKOUT12_VARIABLE_PHASE = FALSE -- C_CLKOUT13_FREQ = 0 -- C_CLKOUT13_PHASE = 0 -- C_CLKOUT13_GROUP = NONE -- C_CLKOUT13_BUF = TRUE -- C_CLKOUT13_VARIABLE_PHASE = FALSE -- C_CLKOUT14_FREQ = 0 -- C_CLKOUT14_PHASE = 0 -- C_CLKOUT14_GROUP = NONE -- C_CLKOUT14_BUF = TRUE -- C_CLKOUT14_VARIABLE_PHASE = FALSE -- C_CLKOUT15_FREQ = 0 -- C_CLKOUT15_PHASE = 0 -- C_CLKOUT15_GROUP = NONE -- C_CLKOUT15_BUF = TRUE -- C_CLKOUT15_VARIABLE_PHASE = FALSE ---------------------------------------- -- C_CLKFBIN_FREQ = 0 -- C_CLKFBIN_DESKEW = NONE -- C_CLKFBOUT_FREQ = 0 -- C_CLKFBOUT_GROUP = NONE -- C_CLKFBOUT_BUF = TRUE ---------------------------------------- -- C_PSDONE_GROUP = NONE ------------------------------------------------------------------------------ -- Low level parameters ------------------------------------------------------------------------------ -- C_CLKOUT0_MODULE = DCM0 -- C_CLKOUT0_PORT = CLKFXB -- C_CLKOUT1_MODULE = NONE -- C_CLKOUT1_PORT = NONE -- C_CLKOUT2_MODULE = NONE -- C_CLKOUT2_PORT = NONE -- C_CLKOUT3_MODULE = NONE -- C_CLKOUT3_PORT = NONE -- C_CLKOUT4_MODULE = NONE -- C_CLKOUT4_PORT = NONE -- C_CLKOUT5_MODULE = NONE -- C_CLKOUT5_PORT = NONE -- C_CLKOUT6_MODULE = NONE -- C_CLKOUT6_PORT = NONE -- C_CLKOUT7_MODULE = NONE -- C_CLKOUT7_PORT = NONE -- C_CLKOUT8_MODULE = NONE -- C_CLKOUT8_PORT = NONE -- C_CLKOUT9_MODULE = NONE -- C_CLKOUT9_PORT = NONE -- C_CLKOUT10_MODULE = NONE -- C_CLKOUT10_PORT = NONE -- C_CLKOUT11_MODULE = NONE -- C_CLKOUT11_PORT = NONE -- C_CLKOUT12_MODULE = NONE -- C_CLKOUT12_PORT = NONE -- C_CLKOUT13_MODULE = NONE -- C_CLKOUT13_PORT = NONE -- C_CLKOUT14_MODULE = NONE -- C_CLKOUT14_PORT = NONE -- C_CLKOUT15_MODULE = NONE -- C_CLKOUT15_PORT = NONE ---------------------------------------- -- C_CLKFBOUT_MODULE = NONE -- C_CLKFBOUT_PORT = NONE -- C_CLKFBOUT_get_clkgen_dcm_default_params = NONE ---------------------------------------- -- C_PSDONE_MODULE = NONE ---------------------------------------- -- C_DCM0_DFS_FREQUENCY_MODE = "LOW" -- C_DCM0_DLL_FREQUENCY_MODE = "LOW" -- C_DCM0_DUTY_CYCLE_CORRECTION = true -- C_DCM0_CLKIN_DIVIDE_BY_2 = false -- C_DCM0_CLK_FEEDBACK = "1X" -- C_DCM0_CLKOUT_PHASE_SHIFT = "NONE" -- C_DCM0_DSS_MODE = "NONE" -- C_DCM0_STARTUP_WAIT = false -- C_DCM0_PHASE_SHIFT = 0 -- C_DCM0_CLKFX_MULTIPLY = 25 -- C_DCM0_CLKFX_DIVIDE = 6 -- C_DCM0_CLKDV_DIVIDE = 2.0 -- C_DCM0_CLKIN_PERIOD = 62.500000 -- C_DCM0_DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS" -- C_DCM0_CLKIN_BUF = false -- C_DCM0_CLKFB_BUF = false -- C_DCM0_CLK0_BUF = TRUE -- C_DCM0_CLK90_BUF = false -- C_DCM0_CLK180_BUF = false -- C_DCM0_CLK270_BUF = false -- C_DCM0_CLKDV_BUF = false -- C_DCM0_CLK2X_BUF = false -- C_DCM0_CLK2X180_BUF = false -- C_DCM0_CLKFX_BUF = TRUE -- C_DCM0_CLKFX180_BUF = false -- C_DCM0_EXT_RESET_HIGH = 1 -- C_DCM0_FAMILY = "spartan3a" -- C_DCM0_CLKIN_MODULE = CLKGEN -- C_DCM0_CLKIN_PORT = CLKIN -- C_DCM0_CLKFB_MODULE = DCM0 -- C_DCM0_CLKFB_PORT = CLK0B -- C_DCM0_RST_MODULE = CLKGEN -- C_DCM1_DFS_FREQUENCY_MODE = "LOW" -- C_DCM1_DLL_FREQUENCY_MODE = "LOW" -- C_DCM1_DUTY_CYCLE_CORRECTION = true -- C_DCM1_CLKIN_DIVIDE_BY_2 = false -- C_DCM1_CLK_FEEDBACK = "1X" -- C_DCM1_CLKOUT_PHASE_SHIFT = "NONE" -- C_DCM1_DSS_MODE = "NONE" -- C_DCM1_STARTUP_WAIT = false -- C_DCM1_PHASE_SHIFT = 0 -- C_DCM1_CLKFX_MULTIPLY = 4 -- C_DCM1_CLKFX_DIVIDE = 1 -- C_DCM1_CLKDV_DIVIDE = 2.0 -- C_DCM1_CLKIN_PERIOD = 41.6666666 -- C_DCM1_DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS" -- C_DCM1_CLKIN_BUF = false -- C_DCM1_CLKFB_BUF = false -- C_DCM1_CLK0_BUF = false -- C_DCM1_CLK90_BUF = false -- C_DCM1_CLK180_BUF = false -- C_DCM1_CLK270_BUF = false -- C_DCM1_CLKDV_BUF = false -- C_DCM1_CLK2X_BUF = false -- C_DCM1_CLK2X180_BUF = false -- C_DCM1_CLKFX_BUF = false -- C_DCM1_CLKFX180_BUF = false -- C_DCM1_EXT_RESET_HIGH = 1 -- C_DCM1_FAMILY = "spartan3a" -- C_DCM1_CLKIN_MODULE = NONE -- C_DCM1_CLKIN_PORT = NONE -- C_DCM1_CLKFB_MODULE = NONE -- C_DCM1_CLKFB_PORT = NONE -- C_DCM1_RST_MODULE = NONE -- C_DCM2_DFS_FREQUENCY_MODE = "LOW" -- C_DCM2_DLL_FREQUENCY_MODE = "LOW" -- C_DCM2_DUTY_CYCLE_CORRECTION = true -- C_DCM2_CLKIN_DIVIDE_BY_2 = false -- C_DCM2_CLK_FEEDBACK = "1X" -- C_DCM2_CLKOUT_PHASE_SHIFT = "NONE" -- C_DCM2_DSS_MODE = "NONE" -- C_DCM2_STARTUP_WAIT = false -- C_DCM2_PHASE_SHIFT = 0 -- C_DCM2_CLKFX_MULTIPLY = 4 -- C_DCM2_CLKFX_DIVIDE = 1 -- C_DCM2_CLKDV_DIVIDE = 2.0 -- C_DCM2_CLKIN_PERIOD = 41.6666666 -- C_DCM2_DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS" -- C_DCM2_CLKIN_BUF = false -- C_DCM2_CLKFB_BUF = false -- C_DCM2_CLK0_BUF = false -- C_DCM2_CLK90_BUF = false -- C_DCM2_CLK180_BUF = false -- C_DCM2_CLK270_BUF = false -- C_DCM2_CLKDV_BUF = false -- C_DCM2_CLK2X_BUF = false -- C_DCM2_CLK2X180_BUF = false -- C_DCM2_CLKFX_BUF = false -- C_DCM2_CLKFX180_BUF = false -- C_DCM2_EXT_RESET_HIGH = 1 -- C_DCM2_FAMILY = "spartan3a" -- C_DCM2_CLKIN_MODULE = NONE -- C_DCM2_CLKIN_PORT = NONE -- C_DCM2_CLKFB_MODULE = NONE -- C_DCM2_CLKFB_PORT = NONE -- C_DCM2_RST_MODULE = NONE -- C_DCM3_DFS_FREQUENCY_MODE = "LOW" -- C_DCM3_DLL_FREQUENCY_MODE = "LOW" -- C_DCM3_DUTY_CYCLE_CORRECTION = true -- C_DCM3_CLKIN_DIVIDE_BY_2 = false -- C_DCM3_CLK_FEEDBACK = "1X" -- C_DCM3_CLKOUT_PHASE_SHIFT = "NONE" -- C_DCM3_DSS_MODE = "NONE" -- C_DCM3_STARTUP_WAIT = false -- C_DCM3_PHASE_SHIFT = 0 -- C_DCM3_CLKFX_MULTIPLY = 4 -- C_DCM3_CLKFX_DIVIDE = 1 -- C_DCM3_CLKDV_DIVIDE = 2.0 -- C_DCM3_CLKIN_PERIOD = 41.6666666 -- C_DCM3_DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS" -- C_DCM3_CLKIN_BUF = false -- C_DCM3_CLKFB_BUF = false -- C_DCM3_CLK0_BUF = false -- C_DCM3_CLK90_BUF = false -- C_DCM3_CLK180_BUF = false -- C_DCM3_CLK270_BUF = false -- C_DCM3_CLKDV_BUF = false -- C_DCM3_CLK2X_BUF = false -- C_DCM3_CLK2X180_BUF = false -- C_DCM3_CLKFX_BUF = false -- C_DCM3_CLKFX180_BUF = false -- C_DCM3_EXT_RESET_HIGH = 1 -- C_DCM3_FAMILY = "spartan3a" -- C_DCM3_CLKIN_MODULE = NONE -- C_DCM3_CLKIN_PORT = NONE -- C_DCM3_CLKFB_MODULE = NONE -- C_DCM3_CLKFB_PORT = NONE -- C_DCM3_RST_MODULE = NONE ---------------------------------------- -- C_PLL0_BANDWIDTH = "OPTIMIZED" -- C_PLL0_CLKFBOUT_MULT = 1 -- C_PLL0_CLKFBOUT_PHASE = 0.0 -- C_PLL0_CLKIN1_PERIOD = 0.000 -- C_PLL0_CLKOUT0_DIVIDE = 1 -- C_PLL0_CLKOUT0_DUTY_CYCLE = 0.5 -- C_PLL0_CLKOUT0_PHASE = 0.0 -- C_PLL0_CLKOUT1_DIVIDE = 1 -- C_PLL0_CLKOUT1_DUTY_CYCLE = 0.5 -- C_PLL0_CLKOUT1_PHASE = 0.0 -- C_PLL0_CLKOUT2_DIVIDE = 1 -- C_PLL0_CLKOUT2_DUTY_CYCLE = 0.5 -- C_PLL0_CLKOUT2_PHASE = 0.0 -- C_PLL0_CLKOUT3_DIVIDE = 1 -- C_PLL0_CLKOUT3_DUTY_CYCLE = 0.5 -- C_PLL0_CLKOUT3_PHASE = 0.0 -- C_PLL0_CLKOUT4_DIVIDE = 1 -- C_PLL0_CLKOUT4_DUTY_CYCLE = 0.5 -- C_PLL0_CLKOUT4_PHASE = 0.0 -- C_PLL0_CLKOUT5_DIVIDE = 1 -- C_PLL0_CLKOUT5_DUTY_CYCLE = 0.5 -- C_PLL0_CLKOUT5_PHASE = 0.0 -- C_PLL0_COMPENSATION = "SYSTEM_SYNCHRONOUS" -- C_PLL0_DIVCLK_DIVIDE = 1 -- C_PLL0_REF_JITTER = 0.100 -- C_PLL0_RESET_ON_LOSS_OF_LOCK = false -- C_PLL0_RST_DEASSERT_CLK = "CLKIN1" -- C_PLL0_CLKOUT0_DESKEW_ADJUST = "NONE" -- C_PLL0_CLKOUT1_DESKEW_ADJUST = "NONE" -- C_PLL0_CLKOUT2_DESKEW_ADJUST = "PPC" -- C_PLL0_CLKOUT3_DESKEW_ADJUST = "PPC" -- C_PLL0_CLKOUT4_DESKEW_ADJUST = "PPC" -- C_PLL0_CLKOUT5_DESKEW_ADJUST = "PPC" -- C_PLL0_CLKFBOUT_DESKEW_ADJUST = "PPC" -- C_PLL0_CLKIN1_BUF = false -- C_PLL0_CLKFBOUT_BUF = false -- C_PLL0_CLKOUT0_BUF = false -- C_PLL0_CLKOUT1_BUF = false -- C_PLL0_CLKOUT2_BUF = false -- C_PLL0_CLKOUT3_BUF = false -- C_PLL0_CLKOUT4_BUF = false -- C_PLL0_CLKOUT5_BUF = false -- C_PLL0_EXT_RESET_HIGH = 1 -- C_PLL0_FAMILY = "spartan3a" -- C_PLL0_CLKIN1_MODULE = NONE -- C_PLL0_CLKIN1_PORT = NONE -- C_PLL0_CLKFBIN_MODULE = NONE -- C_PLL0_CLKFBIN_PORT = NONE -- C_PLL0_RST_MODULE = NONE -- C_PLL1_BANDWIDTH = "OPTIMIZED" -- C_PLL1_CLKFBOUT_MULT = 1 -- C_PLL1_CLKFBOUT_PHASE = 0.0 -- C_PLL1_CLKIN1_PERIOD = 0.000 -- C_PLL1_CLKOUT0_DIVIDE = 1 -- C_PLL1_CLKOUT0_DUTY_CYCLE = 0.5 -- C_PLL1_CLKOUT0_PHASE = 0.0 -- C_PLL1_CLKOUT1_DIVIDE = 1 -- C_PLL1_CLKOUT1_DUTY_CYCLE = 0.5 -- C_PLL1_CLKOUT1_PHASE = 0.0 -- C_PLL1_CLKOUT2_DIVIDE = 1 -- C_PLL1_CLKOUT2_DUTY_CYCLE = 0.5 -- C_PLL1_CLKOUT2_PHASE = 0.0 -- C_PLL1_CLKOUT3_DIVIDE = 1 -- C_PLL1_CLKOUT3_DUTY_CYCLE = 0.5 -- C_PLL1_CLKOUT3_PHASE = 0.0 -- C_PLL1_CLKOUT4_DIVIDE = 1 -- C_PLL1_CLKOUT4_DUTY_CYCLE = 0.5 -- C_PLL1_CLKOUT4_PHASE = 0.0 -- C_PLL1_CLKOUT5_DIVIDE = 1 -- C_PLL1_CLKOUT5_DUTY_CYCLE = 0.5 -- C_PLL1_CLKOUT5_PHASE = 0.0 -- C_PLL1_COMPENSATION = "SYSTEM_SYNCHRONOUS" -- C_PLL1_DIVCLK_DIVIDE = 1 -- C_PLL1_REF_JITTER = 0.100 -- C_PLL1_RESET_ON_LOSS_OF_LOCK = false -- C_PLL1_RST_DEASSERT_CLK = "CLKIN1" -- C_PLL1_CLKOUT0_DESKEW_ADJUST = "NONE" -- C_PLL1_CLKOUT1_DESKEW_ADJUST = "NONE" -- C_PLL1_CLKOUT2_DESKEW_ADJUST = "PPC" -- C_PLL1_CLKOUT3_DESKEW_ADJUST = "PPC" -- C_PLL1_CLKOUT4_DESKEW_ADJUST = "PPC" -- C_PLL1_CLKOUT5_DESKEW_ADJUST = "PPC" -- C_PLL1_CLKFBOUT_DESKEW_ADJUST = "PPC" -- C_PLL1_CLKIN1_BUF = false -- C_PLL1_CLKFBOUT_BUF = false -- C_PLL1_CLKOUT0_BUF = false -- C_PLL1_CLKOUT1_BUF = false -- C_PLL1_CLKOUT2_BUF = false -- C_PLL1_CLKOUT3_BUF = false -- C_PLL1_CLKOUT4_BUF = false -- C_PLL1_CLKOUT5_BUF = false -- C_PLL1_EXT_RESET_HIGH = 1 -- C_PLL1_FAMILY = "spartan3a" -- C_PLL1_CLKIN1_MODULE = NONE -- C_PLL1_CLKIN1_PORT = NONE -- C_PLL1_CLKFBIN_MODULE = NONE -- C_PLL1_CLKFBIN_PORT = NONE -- C_PLL1_RST_MODULE = NONE ---------------------------------------- -- C_MMCM0_BANDWIDTH = "OPTIMIZED" -- C_MMCM0_CLKFBOUT_MULT_F = 1.0 -- C_MMCM0_CLKFBOUT_PHASE = 0.0 -- C_MMCM0_CLKFBOUT_USE_FINE_PS = false -- C_MMCM0_CLKIN1_PERIOD = 0.000 -- C_MMCM0_CLKOUT0_DIVIDE_F = 1.0 -- C_MMCM0_CLKOUT0_DUTY_CYCLE = 0.5 -- C_MMCM0_CLKOUT0_PHASE = 0.0 -- C_MMCM0_CLKOUT1_DIVIDE = 1 -- C_MMCM0_CLKOUT1_DUTY_CYCLE = 0.5 -- C_MMCM0_CLKOUT1_PHASE = 0.0 -- C_MMCM0_CLKOUT2_DIVIDE = 1 -- C_MMCM0_CLKOUT2_DUTY_CYCLE = 0.5 -- C_MMCM0_CLKOUT2_PHASE = 0.0 -- C_MMCM0_CLKOUT3_DIVIDE = 1 -- C_MMCM0_CLKOUT3_DUTY_CYCLE = 0.5 -- C_MMCM0_CLKOUT3_PHASE = 0.0 -- C_MMCM0_CLKOUT4_DIVIDE = 1 -- C_MMCM0_CLKOUT4_DUTY_CYCLE = 0.5 -- C_MMCM0_CLKOUT4_PHASE = 0.0 -- C_MMCM0_CLKOUT4_CASCADE = false -- C_MMCM0_CLKOUT5_DIVIDE = 1 -- C_MMCM0_CLKOUT5_DUTY_CYCLE = 0.5 -- C_MMCM0_CLKOUT5_PHASE = 0.0 -- C_MMCM0_CLKOUT6_DIVIDE = 1 -- C_MMCM0_CLKOUT6_DUTY_CYCLE = 0.5 -- C_MMCM0_CLKOUT6_PHASE = 0.0 -- C_MMCM0_CLKOUT0_USE_FINE_PS = false -- C_MMCM0_CLKOUT1_USE_FINE_PS = false -- C_MMCM0_CLKOUT2_USE_FINE_PS = false -- C_MMCM0_CLKOUT3_USE_FINE_PS = false -- C_MMCM0_CLKOUT4_USE_FINE_PS = false -- C_MMCM0_CLKOUT5_USE_FINE_PS = false -- C_MMCM0_CLKOUT6_USE_FINE_PS = false -- C_MMCM0_COMPENSATION = "ZHOLD" -- C_MMCM0_DIVCLK_DIVIDE = 1 -- C_MMCM0_REF_JITTER1 = 0.010 -- C_MMCM0_CLKIN1_BUF = false -- C_MMCM0_CLKFBOUT_BUF = false -- C_MMCM0_CLKOUT0_BUF = false -- C_MMCM0_CLKOUT1_BUF = false -- C_MMCM0_CLKOUT2_BUF = false -- C_MMCM0_CLKOUT3_BUF = false -- C_MMCM0_CLKOUT4_BUF = false -- C_MMCM0_CLKOUT5_BUF = false -- C_MMCM0_CLKOUT6_BUF = false -- C_MMCM0_CLOCK_HOLD = false -- C_MMCM0_STARTUP_WAIT = false -- C_MMCM0_EXT_RESET_HIGH = 1 -- C_MMCM0_FAMILY = "spartan3a" -- C_MMCM0_CLKIN1_MODULE = NONE -- C_MMCM0_CLKIN1_PORT = NONE -- C_MMCM0_CLKFBIN_MODULE = NONE -- C_MMCM0_CLKFBIN_PORT = NONE -- C_MMCM0_RST_MODULE = NONE -- C_MMCM1_BANDWIDTH = "OPTIMIZED" -- C_MMCM1_CLKFBOUT_MULT_F = 1.0 -- C_MMCM1_CLKFBOUT_PHASE = 0.0 -- C_MMCM1_CLKFBOUT_USE_FINE_PS = false -- C_MMCM1_CLKIN1_PERIOD = 0.000 -- C_MMCM1_CLKOUT0_DIVIDE_F = 1.0 -- C_MMCM1_CLKOUT0_DUTY_CYCLE = 0.5 -- C_MMCM1_CLKOUT0_PHASE = 0.0 -- C_MMCM1_CLKOUT1_DIVIDE = 1 -- C_MMCM1_CLKOUT1_DUTY_CYCLE = 0.5 -- C_MMCM1_CLKOUT1_PHASE = 0.0 -- C_MMCM1_CLKOUT2_DIVIDE = 1 -- C_MMCM1_CLKOUT2_DUTY_CYCLE = 0.5 -- C_MMCM1_CLKOUT2_PHASE = 0.0 -- C_MMCM1_CLKOUT3_DIVIDE = 1 -- C_MMCM1_CLKOUT3_DUTY_CYCLE = 0.5 -- C_MMCM1_CLKOUT3_PHASE = 0.0 -- C_MMCM1_CLKOUT4_DIVIDE = 1 -- C_MMCM1_CLKOUT4_DUTY_CYCLE = 0.5 -- C_MMCM1_CLKOUT4_PHASE = 0.0 -- C_MMCM1_CLKOUT4_CASCADE = false -- C_MMCM1_CLKOUT5_DIVIDE = 1 -- C_MMCM1_CLKOUT5_DUTY_CYCLE = 0.5 -- C_MMCM1_CLKOUT5_PHASE = 0.0 -- C_MMCM1_CLKOUT6_DIVIDE = 1 -- C_MMCM1_CLKOUT6_DUTY_CYCLE = 0.5 -- C_MMCM1_CLKOUT6_PHASE = 0.0 -- C_MMCM1_CLKOUT0_USE_FINE_PS = false -- C_MMCM1_CLKOUT1_USE_FINE_PS = false -- C_MMCM1_CLKOUT2_USE_FINE_PS = false -- C_MMCM1_CLKOUT3_USE_FINE_PS = false -- C_MMCM1_CLKOUT4_USE_FINE_PS = false -- C_MMCM1_CLKOUT5_USE_FINE_PS = false -- C_MMCM1_CLKOUT6_USE_FINE_PS = false -- C_MMCM1_COMPENSATION = "ZHOLD" -- C_MMCM1_DIVCLK_DIVIDE = 1 -- C_MMCM1_REF_JITTER1 = 0.010 -- C_MMCM1_CLKIN1_BUF = false -- C_MMCM1_CLKFBOUT_BUF = false -- C_MMCM1_CLKOUT0_BUF = false -- C_MMCM1_CLKOUT1_BUF = false -- C_MMCM1_CLKOUT2_BUF = false -- C_MMCM1_CLKOUT3_BUF = false -- C_MMCM1_CLKOUT4_BUF = false -- C_MMCM1_CLKOUT5_BUF = false -- C_MMCM1_CLKOUT6_BUF = false -- C_MMCM1_CLOCK_HOLD = false -- C_MMCM1_STARTUP_WAIT = false -- C_MMCM1_EXT_RESET_HIGH = 1 -- C_MMCM1_FAMILY = "spartan3a" -- C_MMCM1_CLKIN1_MODULE = NONE -- C_MMCM1_CLKIN1_PORT = NONE -- C_MMCM1_CLKFBIN_MODULE = NONE -- C_MMCM1_CLKFBIN_PORT = NONE -- C_MMCM1_RST_MODULE = NONE -- C_MMCM2_BANDWIDTH = "OPTIMIZED" -- C_MMCM2_CLKFBOUT_MULT_F = 1.0 -- C_MMCM2_CLKFBOUT_PHASE = 0.0 -- C_MMCM2_CLKFBOUT_USE_FINE_PS = false -- C_MMCM2_CLKIN1_PERIOD = 0.000 -- C_MMCM2_CLKOUT0_DIVIDE_F = 1.0 -- C_MMCM2_CLKOUT0_DUTY_CYCLE = 0.5 -- C_MMCM2_CLKOUT0_PHASE = 0.0 -- C_MMCM2_CLKOUT1_DIVIDE = 1 -- C_MMCM2_CLKOUT1_DUTY_CYCLE = 0.5 -- C_MMCM2_CLKOUT1_PHASE = 0.0 -- C_MMCM2_CLKOUT2_DIVIDE = 1 -- C_MMCM2_CLKOUT2_DUTY_CYCLE = 0.5 -- C_MMCM2_CLKOUT2_PHASE = 0.0 -- C_MMCM2_CLKOUT3_DIVIDE = 1 -- C_MMCM2_CLKOUT3_DUTY_CYCLE = 0.5 -- C_MMCM2_CLKOUT3_PHASE = 0.0 -- C_MMCM2_CLKOUT4_DIVIDE = 1 -- C_MMCM2_CLKOUT4_DUTY_CYCLE = 0.5 -- C_MMCM2_CLKOUT4_PHASE = 0.0 -- C_MMCM2_CLKOUT4_CASCADE = false -- C_MMCM2_CLKOUT5_DIVIDE = 1 -- C_MMCM2_CLKOUT5_DUTY_CYCLE = 0.5 -- C_MMCM2_CLKOUT5_PHASE = 0.0 -- C_MMCM2_CLKOUT6_DIVIDE = 1 -- C_MMCM2_CLKOUT6_DUTY_CYCLE = 0.5 -- C_MMCM2_CLKOUT6_PHASE = 0.0 -- C_MMCM2_CLKOUT0_USE_FINE_PS = false -- C_MMCM2_CLKOUT1_USE_FINE_PS = false -- C_MMCM2_CLKOUT2_USE_FINE_PS = false -- C_MMCM2_CLKOUT3_USE_FINE_PS = false -- C_MMCM2_CLKOUT4_USE_FINE_PS = false -- C_MMCM2_CLKOUT5_USE_FINE_PS = false -- C_MMCM2_CLKOUT6_USE_FINE_PS = false -- C_MMCM2_COMPENSATION = "ZHOLD" -- C_MMCM2_DIVCLK_DIVIDE = 1 -- C_MMCM2_REF_JITTER1 = 0.010 -- C_MMCM2_CLKIN1_BUF = false -- C_MMCM2_CLKFBOUT_BUF = false -- C_MMCM2_CLKOUT0_BUF = false -- C_MMCM2_CLKOUT1_BUF = false -- C_MMCM2_CLKOUT2_BUF = false -- C_MMCM2_CLKOUT3_BUF = false -- C_MMCM2_CLKOUT4_BUF = false -- C_MMCM2_CLKOUT5_BUF = false -- C_MMCM2_CLKOUT6_BUF = false -- C_MMCM2_CLOCK_HOLD = false -- C_MMCM2_STARTUP_WAIT = false -- C_MMCM2_EXT_RESET_HIGH = 1 -- C_MMCM2_FAMILY = "spartan3a" -- C_MMCM2_CLKIN1_MODULE = NONE -- C_MMCM2_CLKIN1_PORT = NONE -- C_MMCM2_CLKFBIN_MODULE = NONE -- C_MMCM2_CLKFBIN_PORT = NONE -- C_MMCM2_RST_MODULE = NONE -- C_MMCM3_BANDWIDTH = "OPTIMIZED" -- C_MMCM3_CLKFBOUT_MULT_F = 1.0 -- C_MMCM3_CLKFBOUT_PHASE = 0.0 -- C_MMCM3_CLKFBOUT_USE_FINE_PS = false -- C_MMCM3_CLKIN1_PERIOD = 0.000 -- C_MMCM3_CLKOUT0_DIVIDE_F = 1.0 -- C_MMCM3_CLKOUT0_DUTY_CYCLE = 0.5 -- C_MMCM3_CLKOUT0_PHASE = 0.0 -- C_MMCM3_CLKOUT1_DIVIDE = 1 -- C_MMCM3_CLKOUT1_DUTY_CYCLE = 0.5 -- C_MMCM3_CLKOUT1_PHASE = 0.0 -- C_MMCM3_CLKOUT2_DIVIDE = 1 -- C_MMCM3_CLKOUT2_DUTY_CYCLE = 0.5 -- C_MMCM3_CLKOUT2_PHASE = 0.0 -- C_MMCM3_CLKOUT3_DIVIDE = 1 -- C_MMCM3_CLKOUT3_DUTY_CYCLE = 0.5 -- C_MMCM3_CLKOUT3_PHASE = 0.0 -- C_MMCM3_CLKOUT4_DIVIDE = 1 -- C_MMCM3_CLKOUT4_DUTY_CYCLE = 0.5 -- C_MMCM3_CLKOUT4_PHASE = 0.0 -- C_MMCM3_CLKOUT4_CASCADE = false -- C_MMCM3_CLKOUT5_DIVIDE = 1 -- C_MMCM3_CLKOUT5_DUTY_CYCLE = 0.5 -- C_MMCM3_CLKOUT5_PHASE = 0.0 -- C_MMCM3_CLKOUT6_DIVIDE = 1 -- C_MMCM3_CLKOUT6_DUTY_CYCLE = 0.5 -- C_MMCM3_CLKOUT6_PHASE = 0.0 -- C_MMCM3_CLKOUT0_USE_FINE_PS = false -- C_MMCM3_CLKOUT1_USE_FINE_PS = false -- C_MMCM3_CLKOUT2_USE_FINE_PS = false -- C_MMCM3_CLKOUT3_USE_FINE_PS = false -- C_MMCM3_CLKOUT4_USE_FINE_PS = false -- C_MMCM3_CLKOUT5_USE_FINE_PS = false -- C_MMCM3_CLKOUT6_USE_FINE_PS = false -- C_MMCM3_COMPENSATION = "ZHOLD" -- C_MMCM3_DIVCLK_DIVIDE = 1 -- C_MMCM3_REF_JITTER1 = 0.010 -- C_MMCM3_CLKIN1_BUF = false -- C_MMCM3_CLKFBOUT_BUF = false -- C_MMCM3_CLKOUT0_BUF = false -- C_MMCM3_CLKOUT1_BUF = false -- C_MMCM3_CLKOUT2_BUF = false -- C_MMCM3_CLKOUT3_BUF = false -- C_MMCM3_CLKOUT4_BUF = false -- C_MMCM3_CLKOUT5_BUF = false -- C_MMCM3_CLKOUT6_BUF = false -- C_MMCM3_CLOCK_HOLD = false -- C_MMCM3_STARTUP_WAIT = false -- C_MMCM3_EXT_RESET_HIGH = 1 -- C_MMCM3_FAMILY = "spartan3a" -- C_MMCM3_CLKIN1_MODULE = NONE -- C_MMCM3_CLKIN1_PORT = NONE -- C_MMCM3_CLKFBIN_MODULE = NONE -- C_MMCM3_CLKFBIN_PORT = NONE -- C_MMCM3_RST_MODULE = NONE ----------------------------------------
mit
a9a17e463e9e5f8c29db57c0cbfd9305
0.55617
2.905857
false
false
false
false
GSimas/EEL5105
Rep CAEE/11.2.Projeto/_PROJETO/reg_8.vhd
1
1,238
-- ALUNOS: -- Bruno Luiz da Silva -- Gustavo Fernades -- -- -- TÍTULO: -- Registrador de 8 bits -- -- -- RESUMO: -- Registrador de 8 bits que armazerá o multiplicando -- -- -- ENTRADAS/SAÍDAS (I/O): -- (I) d: valor de 8 bits que será guardado no registrador, sendo, nesse caso, o multiplicando. -- (I) enable: ativa ou não o armazenamento de dados -- (I) clock,reset: clock e reset, sendo que o reset zera todas saídas -- (O) q: saída com os dados que foram armazenados previamente -- -- -- DESCRIÇÃO: -- Quando for dado um nível lógico alto para "enable" quando o clock estiver na borda de subida -- então a entrada (d) será armazenada e então a saída desse registrador passará a ser essa entrada. -- -- -- (I): INPUT / (O): OUTPUT library ieee; use ieee.std_logic_1164.all; entity reg_8 is port( d: in std_logic_vector(7 downto 0); -- Valor do multiplicando enable, clk, rst: in std_logic; -- Enable, clock e reset q: out std_logic_vector(7 downto 0) -- Dados armazenados ); end reg_8; architecture func of reg_8 is begin FFD: process(d, clk, rst) begin if (rst = '1') then q <= (others => '0'); elsif (rising_edge(clk)) then if(enable = '1') then q <= d; end if; end if; end process; end func;
mit
9c37dcc90bf5ccbb6971af3e16ff7e91
0.663166
2.714912
false
false
false
false
tghaefli/ADD
EDK/IVK_Repos/IVK_IPLib/pcores/ivk_video_gen_v2_01_a/hdl/vhdl/ivk_video_gen.vhd
1
26,261
------------------------------------------------------------------ -- _____ -- / \ -- /____ \____ -- / \===\ \==/ -- /___\===\___\/ AVNET -- \======/ -- \====/ ----------------------------------------------------------------- -- -- This design is the property of Avnet. Publication of this -- design is not authorized without written consent from Avnet. -- -- Please direct any questions to: [email protected] -- -- Disclaimer: -- Avnet, Inc. makes no warranty for the use of this code or design. -- This code is provided "As Is". Avnet, Inc assumes no responsibility for -- any errors, which may appear in this code, nor does it make a commitment -- to update the information contained herein. Avnet, Inc specifically -- disclaims any implied warranties of fitness for a particular purpose. -- Copyright(c) 2010 Avnet, Inc. -- All rights reserved. -- ------------------------------------------------------------------ -- -- Create Date: Dec 03, 2009 -- Design Name: IVK -- Module Name: ivk_video_gen.vhd -- Project Name: IVK -- Target Devices: Spartan-6 -- Avnet Boards: IVK -- -- Tool versions: ISE 12.1 -- -- Description: -- -- Dependencies: -- -- Revision: Dec 03, 2009: 1.00 Initial version -- Feb 01, 2010: 1.02 Add selectable video interface -- Feb 10, 2010: 1.02b Fix XSVI video_data ordering: -- [23:16] = red -- [15: 8] = blue -- [ 7: 0] = green -- Mar 02, 2010: 1.03 Add optionnal VDMA Write Port -- Mar 10, 2010: 1.04 Force FSYNC to active high polarity -- Apr 12, 2010: 1.05 Fix VBlank/HBlank outputs -- Apr 13, 2010: 1.06 Add support for 16bit data width on XSVI input -- May 14, 2010: 2.01 Update for 12.1 -- ------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library proc_common_v3_00_a; use proc_common_v3_00_a.proc_common_pkg.all; use proc_common_v3_00_a.ipif_pkg.all; use proc_common_v3_00_a.soft_reset; library plbv46_slave_single_v1_01_a; use plbv46_slave_single_v1_01_a.plbv46_slave_single; library ivk_video_gen_v2_01_a; use ivk_video_gen_v2_01_a.user_logic; ------------------------------------------------------------------------------ -- Entity section ------------------------------------------------------------------------------ -- Definition of Generics: -- C_BASEADDR -- PLBv46 slave: base address -- C_HIGHADDR -- PLBv46 slave: high address -- C_SPLB_AWIDTH -- PLBv46 slave: address bus width -- C_SPLB_DWIDTH -- PLBv46 slave: data bus width -- C_SPLB_NUM_MASTERS -- PLBv46 slave: Number of masters -- C_SPLB_MID_WIDTH -- PLBv46 slave: master ID bus width -- C_SPLB_NATIVE_DWIDTH -- PLBv46 slave: internal native data bus width -- C_SPLB_P2P -- PLBv46 slave: point to point interconnect scheme -- C_SPLB_SUPPORT_BURSTS -- PLBv46 slave: support bursts -- C_SPLB_SMALLEST_MASTER -- PLBv46 slave: width of the smallest master -- C_SPLB_CLK_PERIOD_PS -- PLBv46 slave: bus clock in picoseconds -- C_INCLUDE_DPHASE_TIMER -- PLBv46 slave: Data Phase Timer configuration; 0 = exclude timer, 1 = include timer -- C_FAMILY -- Xilinx FPGA family -- -- Definition of Ports: -- SPLB_Clk -- PLB main bus clock -- SPLB_Rst -- PLB main bus reset -- PLB_ABus -- PLB address bus -- PLB_UABus -- PLB upper address bus -- PLB_PAValid -- PLB primary address valid indicator -- PLB_SAValid -- PLB secondary address valid indicator -- PLB_rdPrim -- PLB secondary to primary read request indicator -- PLB_wrPrim -- PLB secondary to primary write request indicator -- PLB_masterID -- PLB current master identifier -- PLB_abort -- PLB abort request indicator -- PLB_busLock -- PLB bus lock -- PLB_RNW -- PLB read/not write -- PLB_BE -- PLB byte enables -- PLB_MSize -- PLB master data bus size -- PLB_size -- PLB transfer size -- PLB_type -- PLB transfer type -- PLB_lockErr -- PLB lock error indicator -- PLB_wrDBus -- PLB write data bus -- PLB_wrBurst -- PLB burst write transfer indicator -- PLB_rdBurst -- PLB burst read transfer indicator -- PLB_wrPendReq -- PLB write pending bus request indicator -- PLB_rdPendReq -- PLB read pending bus request indicator -- PLB_wrPendPri -- PLB write pending request priority -- PLB_rdPendPri -- PLB read pending request priority -- PLB_reqPri -- PLB current request priority -- PLB_TAttribute -- PLB transfer attribute -- Sl_addrAck -- Slave address acknowledge -- Sl_SSize -- Slave data bus size -- Sl_wait -- Slave wait indicator -- Sl_rearbitrate -- Slave re-arbitrate bus indicator -- Sl_wrDAck -- Slave write data acknowledge -- Sl_wrComp -- Slave write transfer complete indicator -- Sl_wrBTerm -- Slave terminate write burst transfer -- Sl_rdDBus -- Slave read data bus -- Sl_rdWdAddr -- Slave read word address -- Sl_rdDAck -- Slave read data acknowledge -- Sl_rdComp -- Slave read transfer complete indicator -- Sl_rdBTerm -- Slave terminate read burst transfer -- Sl_MBusy -- Slave busy indicator -- Sl_MWrErr -- Slave write error indicator -- Sl_MRdErr -- Slave read error indicator -- Sl_MIRQ -- Slave interrupt indicator ------------------------------------------------------------------------------ entity ivk_video_gen is generic ( -- ADD USER GENERICS BELOW THIS LINE --------------- C_GEN_FSYNC : integer := 0; C_GEN_RD_VDMA : integer := 0; C_VIDEO_INTERFACE : integer := 2; C_XSVI_DATA_WIDTH : integer := 24; C_VDMA_DATA_WIDTH : integer := 32; -- ADD USER GENERICS ABOVE THIS LINE --------------- -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol parameters, do not add to or delete C_BASEADDR : std_logic_vector := X"FFFFFFFF"; C_HIGHADDR : std_logic_vector := X"00000000"; C_SPLB_AWIDTH : integer := 32; C_SPLB_DWIDTH : integer := 128; C_SPLB_NUM_MASTERS : integer := 8; C_SPLB_MID_WIDTH : integer := 3; C_SPLB_NATIVE_DWIDTH : integer := 32; C_SPLB_P2P : integer := 0; C_SPLB_SUPPORT_BURSTS : integer := 0; C_SPLB_SMALLEST_MASTER : integer := 32; C_SPLB_CLK_PERIOD_PS : integer := 10000; C_INCLUDE_DPHASE_TIMER : integer := 0; C_FAMILY : string := "spartan6" -- DO NOT EDIT ABOVE THIS LINE --------------------- ); port ( -- ADD USER PORTS BELOW THIS LINE ------------------ -- Global Reset (asynchronous) reset : in std_logic; clk : in std_logic; -- Camera Port camera_frame_valid_o : out std_logic; camera_line_valid_o : out std_logic; camera_data_o : out std_logic_vector((C_XSVI_DATA_WIDTH-1) downto 0); -- DVI Port dvi_vsync_o : out std_logic; dvi_hsync_o : out std_logic; dvi_de_o : out std_logic; dvi_red_o : out std_logic_vector(7 downto 0); dvi_green_o : out std_logic_vector(7 downto 0); dvi_blue_o : out std_logic_vector(7 downto 0); -- XSVI Port xsvi_vsync_o : out std_logic; xsvi_hsync_o : out std_logic; xsvi_vblank_o : out std_logic; xsvi_hblank_o : out std_logic; xsvi_active_video_o : out std_logic; xsvi_video_data_o : out std_logic_vector((C_XSVI_DATA_WIDTH-1) downto 0); -- VDMA Read Port --vdma_rcmd_clk : out std_logic; vdma_rd_clk : out std_logic; vdma_rd_read : out std_logic; vdma_rd_data : in std_logic_vector((C_VDMA_DATA_WIDTH-1) downto 0); -- Frame Sync Output Port fsync_o : out std_logic; -- ADD USER PORTS ABOVE THIS LINE ------------------ -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol ports, do not add to or delete SPLB_Clk : in std_logic; SPLB_Rst : in std_logic; PLB_ABus : in std_logic_vector(0 to 31); PLB_UABus : in std_logic_vector(0 to 31); PLB_PAValid : in std_logic; PLB_SAValid : in std_logic; PLB_rdPrim : in std_logic; PLB_wrPrim : in std_logic; PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1); PLB_abort : in std_logic; PLB_busLock : in std_logic; PLB_RNW : in std_logic; PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1); PLB_MSize : in std_logic_vector(0 to 1); PLB_size : in std_logic_vector(0 to 3); PLB_type : in std_logic_vector(0 to 2); PLB_lockErr : in std_logic; PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1); PLB_wrBurst : in std_logic; PLB_rdBurst : in std_logic; PLB_wrPendReq : in std_logic; PLB_rdPendReq : in std_logic; PLB_wrPendPri : in std_logic_vector(0 to 1); PLB_rdPendPri : in std_logic_vector(0 to 1); PLB_reqPri : in std_logic_vector(0 to 1); PLB_TAttribute : in std_logic_vector(0 to 15); Sl_addrAck : out std_logic; Sl_SSize : out std_logic_vector(0 to 1); Sl_wait : out std_logic; Sl_rearbitrate : out std_logic; Sl_wrDAck : out std_logic; Sl_wrComp : out std_logic; Sl_wrBTerm : out std_logic; Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1); Sl_rdWdAddr : out std_logic_vector(0 to 3); Sl_rdDAck : out std_logic; Sl_rdComp : out std_logic; Sl_rdBTerm : out std_logic; Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1); Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1); Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1); Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1) -- DO NOT EDIT ABOVE THIS LINE --------------------- ); attribute SIGIS : string; attribute SIGIS of SPLB_Clk : signal is "CLK"; attribute SIGIS of SPLB_Rst : signal is "RST"; end entity ivk_video_gen; ------------------------------------------------------------------------------ -- Architecture section ------------------------------------------------------------------------------ architecture IMP of ivk_video_gen is ------------------------------------------ -- Array of base/high address pairs for each address range ------------------------------------------ constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0'); constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR or X"00000000"; constant USER_SLV_HIGHADDR : std_logic_vector := C_BASEADDR or X"000000FF"; constant RST_BASEADDR : std_logic_vector := C_BASEADDR or X"00000100"; constant RST_HIGHADDR : std_logic_vector := C_BASEADDR or X"000001FF"; constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE := ( ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address ZERO_ADDR_PAD & USER_SLV_HIGHADDR, -- user logic slave space high address ZERO_ADDR_PAD & RST_BASEADDR, -- soft reset space base address ZERO_ADDR_PAD & RST_HIGHADDR -- soft reset space high address ); ------------------------------------------ -- Array of desired number of chip enables for each address range ------------------------------------------ constant USER_SLV_NUM_REG : integer := 4; constant USER_NUM_REG : integer := USER_SLV_NUM_REG; constant RST_NUM_CE : integer := 1; constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := ( 0 => pad_power2(USER_SLV_NUM_REG), -- number of ce for user logic slave space 1 => RST_NUM_CE -- number of ce for soft reset space ); ------------------------------------------ -- Ratio of bus clock to core clock (for use in dual clock systems) -- 1 = ratio is 1:1 -- 2 = ratio is 2:1 ------------------------------------------ constant IPIF_BUS2CORE_CLK_RATIO : integer := 1; ------------------------------------------ -- Width of the slave data bus (32 only) ------------------------------------------ constant USER_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH; constant IPIF_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH; ------------------------------------------ -- Width of triggered reset in bus clocks ------------------------------------------ constant RESET_WIDTH : integer := 4; ------------------------------------------ -- Index for CS/CE ------------------------------------------ constant USER_SLV_CS_INDEX : integer := 0; constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX); constant RST_CS_INDEX : integer := 1; constant RST_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, RST_CS_INDEX); constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX; ------------------------------------------ -- IP Interconnect (IPIC) signal declarations ------------------------------------------ signal ipif_Bus2IP_Clk : std_logic; signal ipif_Bus2IP_Reset : std_logic; signal ipif_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1); signal ipif_IP2Bus_WrAck : std_logic; signal ipif_IP2Bus_RdAck : std_logic; signal ipif_IP2Bus_Error : std_logic; signal ipif_Bus2IP_Addr : std_logic_vector(0 to C_SPLB_AWIDTH-1); signal ipif_Bus2IP_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1); signal ipif_Bus2IP_RNW : std_logic; signal ipif_Bus2IP_BE : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1); signal ipif_Bus2IP_CS : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1); signal ipif_Bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1); signal ipif_Bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1); signal rst_Bus2IP_Reset : std_logic; signal rst_IP2Bus_WrAck : std_logic; signal rst_IP2Bus_Error : std_logic; signal user_Bus2IP_RdCE : std_logic_vector(0 to USER_NUM_REG-1); signal user_Bus2IP_WrCE : std_logic_vector(0 to USER_NUM_REG-1); signal user_IP2Bus_Data : std_logic_vector(0 to USER_SLV_DWIDTH-1); signal user_IP2Bus_RdAck : std_logic; signal user_IP2Bus_WrAck : std_logic; signal user_IP2Bus_Error : std_logic; begin ------------------------------------------ -- instantiate plbv46_slave_single ------------------------------------------ PLBV46_SLAVE_SINGLE_I : entity plbv46_slave_single_v1_01_a.plbv46_slave_single generic map ( C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY, C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY, C_SPLB_P2P => C_SPLB_P2P, C_BUS2CORE_CLK_RATIO => IPIF_BUS2CORE_CLK_RATIO, C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH, C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS, C_SPLB_AWIDTH => C_SPLB_AWIDTH, C_SPLB_DWIDTH => C_SPLB_DWIDTH, C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH, C_INCLUDE_DPHASE_TIMER => C_INCLUDE_DPHASE_TIMER, C_FAMILY => C_FAMILY ) port map ( SPLB_Clk => SPLB_Clk, SPLB_Rst => SPLB_Rst, PLB_ABus => PLB_ABus, PLB_UABus => PLB_UABus, PLB_PAValid => PLB_PAValid, PLB_SAValid => PLB_SAValid, PLB_rdPrim => PLB_rdPrim, PLB_wrPrim => PLB_wrPrim, PLB_masterID => PLB_masterID, PLB_abort => PLB_abort, PLB_busLock => PLB_busLock, PLB_RNW => PLB_RNW, PLB_BE => PLB_BE, PLB_MSize => PLB_MSize, PLB_size => PLB_size, PLB_type => PLB_type, PLB_lockErr => PLB_lockErr, PLB_wrDBus => PLB_wrDBus, PLB_wrBurst => PLB_wrBurst, PLB_rdBurst => PLB_rdBurst, PLB_wrPendReq => PLB_wrPendReq, PLB_rdPendReq => PLB_rdPendReq, PLB_wrPendPri => PLB_wrPendPri, PLB_rdPendPri => PLB_rdPendPri, PLB_reqPri => PLB_reqPri, PLB_TAttribute => PLB_TAttribute, Sl_addrAck => Sl_addrAck, Sl_SSize => Sl_SSize, Sl_wait => Sl_wait, Sl_rearbitrate => Sl_rearbitrate, Sl_wrDAck => Sl_wrDAck, Sl_wrComp => Sl_wrComp, Sl_wrBTerm => Sl_wrBTerm, Sl_rdDBus => Sl_rdDBus, Sl_rdWdAddr => Sl_rdWdAddr, Sl_rdDAck => Sl_rdDAck, Sl_rdComp => Sl_rdComp, Sl_rdBTerm => Sl_rdBTerm, Sl_MBusy => Sl_MBusy, Sl_MWrErr => Sl_MWrErr, Sl_MRdErr => Sl_MRdErr, Sl_MIRQ => Sl_MIRQ, Bus2IP_Clk => ipif_Bus2IP_Clk, Bus2IP_Reset => ipif_Bus2IP_Reset, IP2Bus_Data => ipif_IP2Bus_Data, IP2Bus_WrAck => ipif_IP2Bus_WrAck, IP2Bus_RdAck => ipif_IP2Bus_RdAck, IP2Bus_Error => ipif_IP2Bus_Error, Bus2IP_Addr => ipif_Bus2IP_Addr, Bus2IP_Data => ipif_Bus2IP_Data, Bus2IP_RNW => ipif_Bus2IP_RNW, Bus2IP_BE => ipif_Bus2IP_BE, Bus2IP_CS => ipif_Bus2IP_CS, Bus2IP_RdCE => ipif_Bus2IP_RdCE, Bus2IP_WrCE => ipif_Bus2IP_WrCE ); ------------------------------------------ -- instantiate soft_reset ------------------------------------------ SOFT_RESET_I : entity proc_common_v3_00_a.soft_reset generic map ( C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH, C_RESET_WIDTH => RESET_WIDTH ) port map ( Bus2IP_Reset => ipif_Bus2IP_Reset, Bus2IP_Clk => ipif_Bus2IP_Clk, Bus2IP_WrCE => ipif_Bus2IP_WrCE(RST_CE_INDEX), Bus2IP_Data => ipif_Bus2IP_Data, Bus2IP_BE => ipif_Bus2IP_BE, Reset2IP_Reset => rst_Bus2IP_Reset, Reset2Bus_WrAck => rst_IP2Bus_WrAck, Reset2Bus_Error => rst_IP2Bus_Error, Reset2Bus_ToutSup => open ); ------------------------------------------ -- instantiate User Logic ------------------------------------------ USER_LOGIC_I : entity ivk_video_gen_v2_01_a.user_logic generic map ( -- MAP USER GENERICS BELOW THIS LINE --------------- C_GEN_FSYNC => C_GEN_FSYNC, C_GEN_RD_VDMA => C_GEN_RD_VDMA, C_VIDEO_INTERFACE => C_VIDEO_INTERFACE, C_XSVI_DATA_WIDTH => C_XSVI_DATA_WIDTH, C_VDMA_DATA_WIDTH => C_VDMA_DATA_WIDTH, -- MAP USER GENERICS ABOVE THIS LINE --------------- C_SLV_DWIDTH => USER_SLV_DWIDTH, C_NUM_REG => USER_NUM_REG, C_FAMILY => C_FAMILY ) port map ( -- MAP USER PORTS BELOW THIS LINE ------------------ -- Global Reset (asynchronous) reset => reset, clk => clk, -- Camera Port camera_frame_valid_o => camera_frame_valid_o, camera_line_valid_o => camera_line_valid_o, camera_data_o => camera_data_o, -- DVI Port dvi_vsync_o => dvi_vsync_o, dvi_hsync_o => dvi_hsync_o, dvi_de_o => dvi_de_o, dvi_red_o => dvi_red_o, dvi_green_o => dvi_green_o, dvi_blue_o => dvi_blue_o, -- XSVI Port xsvi_vsync_o => xsvi_vsync_o, xsvi_hsync_o => xsvi_hsync_o, xsvi_vblank_o => xsvi_vblank_o, xsvi_hblank_o => xsvi_hblank_o, xsvi_active_video_o => xsvi_active_video_o, xsvi_video_data_o => xsvi_video_data_o, -- VDMA Read Port --vdma_rcmd_clk => vdma_rcmd_clk, vdma_rd_clk => vdma_rd_clk, vdma_rd_read => vdma_rd_read, vdma_rd_data => vdma_rd_data, -- Frame Sync Output Port fsync_o => fsync_o, -- MAP USER PORTS ABOVE THIS LINE ------------------ Bus2IP_Clk => ipif_Bus2IP_Clk, Bus2IP_Reset => rst_Bus2IP_Reset, Bus2IP_Data => ipif_Bus2IP_Data, Bus2IP_BE => ipif_Bus2IP_BE, Bus2IP_RdCE => user_Bus2IP_RdCE, Bus2IP_WrCE => user_Bus2IP_WrCE, IP2Bus_Data => user_IP2Bus_Data, IP2Bus_RdAck => user_IP2Bus_RdAck, IP2Bus_WrAck => user_IP2Bus_WrAck, IP2Bus_Error => user_IP2Bus_Error ); ------------------------------------------ -- connect internal signals ------------------------------------------ IP2BUS_DATA_MUX_PROC : process( ipif_Bus2IP_CS, user_IP2Bus_Data ) is begin case ipif_Bus2IP_CS is when "10" => ipif_IP2Bus_Data <= user_IP2Bus_Data; when "01" => ipif_IP2Bus_Data <= (others => '0'); when others => ipif_IP2Bus_Data <= (others => '0'); end case; end process IP2BUS_DATA_MUX_PROC; ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck or rst_IP2Bus_WrAck; ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck; ipif_IP2Bus_Error <= user_IP2Bus_Error or rst_IP2Bus_Error; user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1); user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1); end IMP;
gpl-3.0
01ec54e281419b26548e3fc614f7be2c
0.441377
4.190362
false
false
false
false
tghaefli/ADD
ISE/FMC_waj/gpio.vhd
1
3,701
------------------------------------------------------------------------------- -- Entity: ram -- Author: Waj ------------------------------------------------------------------------------- -- Description: (ECS Uebung 9) -- GPIO block for simple von-Neumann MCU. ------------------------------------------------------------------------------- -- Total # of FFs: ... tbd ... ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.mcu_pkg.all; entity gpio is port(rst : in std_logic; clk : in std_logic; -- GPIO bus signals bus_in : in t_bus2rws; bus_out : out t_rws2bus; -- GPIO pin signals gpio_in : in std_logic_vector(DW-1 downto 0); gpio_out : out std_logic_vector(DW-1 downto 0); gpio_out_enb : out std_logic_vector(DW-1 downto 0) ); end gpio; architecture rtl of gpio is -- address select signal signal addr_sel : t_gpio_addr_sel; -- peripheral registers signal data_in_reg : std_logic_vector(DW-1 downto 0); signal data_out_reg : std_logic_vector(DW-1 downto 0); signal out_enb_reg : std_logic_vector(DW-1 downto 0); begin -- output ssignment gpio_out <= data_out_reg; gpio_out_enb <= out_enb_reg; ----------------------------------------------------------------------------- -- Input register ----------------------------------------------------------------------------- P_in: process(clk) begin if rising_edge(clk) then data_in_reg <= gpio_in; end if; end process; ----------------------------------------------------------------------------- -- Address Decoding (combinationally) ----------------------------------------------------------------------------- process(bus_in.addr) begin case bus_in.addr is -- Port 1 addresses ----------------------------------------------------- when c_addr_gpio_data_in => addr_sel <= gpio_data_in; when c_addr_gpio_data_out => addr_sel <= gpio_data_out; when c_addr_gpio_out_enb => addr_sel <= gpio_enb; -- unused addresses ----------------------------------------------------- when others => addr_sel <= none; end case; end process; ----------------------------------------------------------------------------- -- Read Access (R and R/W registers) ----------------------------------------------------------------------------- P_read: process(clk) begin if rising_edge(clk) then -- default assignment bus_out.data <= (others => '0'); -- use address select signal case addr_sel is when gpio_data_in => bus_out.data <= data_in_reg; when gpio_data_out => bus_out.data <= data_out_reg; when gpio_enb => bus_out.data <= out_enb_reg; when others => null; end case; end if; end process; ----------------------------------------------------------------------------- -- Write Access (R/W registers only) ----------------------------------------------------------------------------- P_write: process(clk, rst) begin if rst = '1' then data_out_reg <= (others => '0'); out_enb_reg <= (others => '0'); -- output disabled per default elsif rising_edge(clk) then if bus_in.wr_enb = '1' then -- use address select signal case addr_sel is when gpio_data_out => data_out_reg <= bus_in.data; when gpio_enb => out_enb_reg <= bus_in.data; when others => null; end case; end if; end if; end process; end rtl;
gpl-3.0
b077de7376f75a55d2d5d335eeb6b3cc
0.408538
4.464415
false
false
false
false
abyrne55/my-little-processor
control_circuit.vhd
1
3,814
LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- Control Circuit (FSM) ENTITY control_circuit IS PORT ( clock, reset : IN STD_LOGIC; func : IN STD_LOGIC_VECTOR (15 DOWNTO 0); done, A_in, G_in, G_out, extern, R0_in, R1_in : OUT STD_LOGIC := '0'; R0_out, R1_out, R0_xor, R1_xor, PC_in, PC_out : OUT STD_LOGIC := '0'; c_state : OUT INTEGER ); END; ARCHITECTURE behavioural OF control_circuit IS COMPONENT find_ns IS PORT ( state : IN INTEGER; reset : IN STD_LOGIC; instr : IN STD_LOGIC_VECTOR(3 DOWNTO 0); rx, ry : IN STD_LOGIC_VECTOR(3 DOWNTO 0); ns : OUT INTEGER ); END COMPONENT; SIGNAL c_state_temp : INTEGER := 255; SIGNAL n_state : INTEGER := 0; BEGIN instance1 : find_ns PORT MAP( reset => reset, state => c_state_temp, instr => func(15 DOWNTO 12), rx => func(11 DOWNTO 8), ry => func(7 DOWNTO 4), ns => n_state ); PROCESS (c_state_temp, func) BEGIN done <= '0'; R0_in <= '0'; R0_in <= '0'; R0_out <= '0'; R0_xor <= '0'; R1_in <= '0'; R1_out <= '0'; R1_xor <= '0'; PC_in <= '0'; PC_out <= '0'; A_in <= '0'; G_in <= '0'; G_out <= '0'; extern <= '0'; CASE c_state_temp IS -- START state WHEN 255 => done <= '1'; -- IDLE State WHEN 0 => -- Wait for next instruction -- LOAD States WHEN 10 => done <= '1'; WHEN 11 => --Rx = R0 extern <= '1'; R0_in <= '1'; WHEN 12 => -- Rx = R1 extern <= '1'; R1_in <= '1'; WHEN 13 => extern <= '1'; done <= '1'; WHEN 14 => done <= '1'; -- MOV States WHEN 20 => -- Rx = R0 R0_in <= '1'; R1_out <= '1'; WHEN 21 => -- Rx = R1 R1_in <= '1'; R0_out <= '1'; WHEN 22 => done <= '1'; -- ADD States WHEN 30 => R0_out <= '1'; A_in <= '1'; WHEN 31 => R1_out <= '1'; G_in <= '1'; WHEN 32 => -- Rx = R0 G_out <= '1'; R0_in <= '1'; WHEN 33 => -- Rx = R1 G_out <= '1'; R1_in <= '1'; WHEN 34 => done <= '1'; -- XOR States WHEN 40 => --Rx = R0 R1_out <= '1'; R0_xor <= '1'; WHEN 41 => --Rx = R1 R0_out <= '1'; R1_xor <= '1'; WHEN 42 => done <= '1'; -- LDPC, Load PC to Rx WHEN 50 => --Rx = R0 R0_in <= '1'; PC_out <= '1'; WHEN 51 => --Rx = R1 R1_in <= '1'; PC_out <= '1'; WHEN 52 => done <= '1'; -- BRANCH, Load Rx to PC WHEN 60 => --Rx = R0 PC_in <= '1'; R0_out <= '1'; WHEN 61 => --Rx = R1 PC_in <= '1'; R1_out <= '1'; WHEN 62 => R1_out <= '1'; done <= '1'; --Double Ry, store in Rx WHEN 701 => --Rx = R0, Ry = R0 R0_out <= '1'; A_in <= '1'; WHEN 702 => R0_out <= '1'; G_in <= '1'; WHEN 703 => G_out <= '1'; R0_in <= '1'; WHEN 711 => --Rx = R1, Ry = R0 R0_out <= '1'; A_in <= '1'; G_in <= '1'; WHEN 712 => R0_out <= '1'; G_in <= '1'; WHEN 713 => G_out <= '1'; R1_in <= '1'; WHEN 721 => --Rx = R0, Ry = R1 R1_out <= '1'; A_in <= '1'; G_in <= '1'; WHEN 722 => R1_out <= '1'; G_in <= '1'; WHEN 723 => G_out <= '1'; R0_in <= '1'; WHEN 731 => --Rx = R1, Ry = R1 R1_out <= '1'; A_in <= '1'; G_in <= '1'; WHEN 732 => R1_out <= '1'; G_in <= '1'; WHEN 733 => G_out <= '1'; R1_in <= '1'; WHEN 740 => done <= '1'; WHEN OTHERS => -- Return to IDLE END CASE; END PROCESS; PROCESS (clock) BEGIN IF rising_edge(clock) THEN c_state_temp <= n_state; END IF; END PROCESS; c_state <= c_state_temp; END behavioural;
mit
655b870c5c36dab6f8dbb31ab4c517fa
0.418196
2.432398
false
false
false
false
hoglet67/AtomFpga
src/common/debounce.vhd
1
1,669
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity debounce is generic ( counter_size : integer := 18 -- approx 16ms @ 16MHz ); port ( clock : in std_logic; button : in std_logic; -- button input result : out std_logic; -- debounced button input pressed : out std_logic; -- active got one cycle when button pressed released : out std_logic -- active got one cycle when button released ); end debounce; architecture behavioural of debounce is signal button_in : std_logic; -- synchronised to clock, but not debounced signal button_out : std_logic; -- fully debounced signal counter : std_logic_vector(counter_size downto 0) := (others => '0'); begin process(clock) begin if rising_edge(clock) then button_in <= button; pressed <= '0'; released <= '0'; if button_in = button_out then -- input same as output, reset the counter counter <= (others => '0'); else -- input is different to output, start counting counter <= counter + 1; -- difference lasts for N-1 cycles, update the output if counter(counter_size) = '1' then button_out <= button_in; if button_in = '1' then pressed <= '1'; else released <= '1'; end if; end if; end if; end if; end process; result <= button_out; end behavioural;
apache-2.0
ba5134dd26f2b4aa528db1f106688fe7
0.523667
4.450667
false
false
false
false
tghaefli/ADD
EDK/IVK_Repos/IVK_IPLib/pcores/sg_i2c_controller_s6_plbw_v1_01_a/hdl/vhdl/fifo_generator_spartan6_6_1_a1065cba3626fc97.vhd
1
6,333
-------------------------------------------------------------------------------- -- This file is owned and controlled by Xilinx and must be used -- -- solely for design, simulation, implementation and creation of -- -- design files limited to Xilinx devices or technologies. Use -- -- with non-Xilinx devices or technologies is expressly prohibited -- -- and immediately terminates your license. -- -- -- -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- -- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- -- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- -- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- -- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- -- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- -- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- -- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- -- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- -- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- -- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- -- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- -- FOR A PARTICULAR PURPOSE. -- -- -- -- Xilinx products are not intended for use in life support -- -- appliances, devices, or systems. Use in such applications are -- -- expressly prohibited. -- -- -- -- (c) Copyright 1995-2009 Xilinx, Inc. -- -- All rights reserved. -- -------------------------------------------------------------------------------- -- You must compile the wrapper file fifo_generator_spartan6_6_1_a1065cba3626fc97.vhd when simulating -- the core, fifo_generator_spartan6_6_1_a1065cba3626fc97. When compiling the wrapper file, be sure to -- reference the XilinxCoreLib VHDL simulation library. For detailed -- instructions, please refer to the "CORE Generator Help". -- The synthesis directives "translate_off/translate_on" specified -- below are supported by Xilinx, Mentor Graphics and Synplicity -- synthesis tools. Ensure they are correct for your synthesis tool(s). LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- synthesis translate_off Library XilinxCoreLib; -- synthesis translate_on ENTITY fifo_generator_spartan6_6_1_a1065cba3626fc97 IS port ( rst: IN std_logic; wr_clk: IN std_logic; rd_clk: IN std_logic; din: IN std_logic_VECTOR(31 downto 0); wr_en: IN std_logic; rd_en: IN std_logic; dout: OUT std_logic_VECTOR(31 downto 0); full: OUT std_logic; empty: OUT std_logic; rd_data_count: OUT std_logic_VECTOR(0 downto 0); wr_data_count: OUT std_logic_VECTOR(0 downto 0)); END fifo_generator_spartan6_6_1_a1065cba3626fc97; ARCHITECTURE fifo_generator_spartan6_6_1_a1065cba3626fc97_a OF fifo_generator_spartan6_6_1_a1065cba3626fc97 IS -- synthesis translate_off component wrapped_fifo_generator_spartan6_6_1_a1065cba3626fc97 port ( rst: IN std_logic; wr_clk: IN std_logic; rd_clk: IN std_logic; din: IN std_logic_VECTOR(31 downto 0); wr_en: IN std_logic; rd_en: IN std_logic; dout: OUT std_logic_VECTOR(31 downto 0); full: OUT std_logic; empty: OUT std_logic; rd_data_count: OUT std_logic_VECTOR(0 downto 0); wr_data_count: OUT std_logic_VECTOR(0 downto 0)); end component; -- Configuration specification for all : wrapped_fifo_generator_spartan6_6_1_a1065cba3626fc97 use entity XilinxCoreLib.fifo_generator_v6_1(behavioral) generic map( c_has_int_clk => 0, c_wr_response_latency => 1, c_rd_freq => 1, c_has_srst => 0, c_enable_rst_sync => 1, c_has_rd_data_count => 1, c_din_width => 32, c_has_wr_data_count => 1, c_full_flags_rst_val => 1, c_implementation_type => 2, c_family => "spartan6", c_use_embedded_reg => 0, c_has_wr_rst => 0, c_wr_freq => 1, c_use_dout_rst => 1, c_underflow_low => 0, c_has_meminit_file => 0, c_has_overflow => 0, c_preload_latency => 1, c_dout_width => 32, c_msgon_val => 1, c_rd_depth => 32, c_default_value => "BlankString", c_mif_file_name => "BlankString", c_error_injection_type => 0, c_has_underflow => 0, c_has_rd_rst => 0, c_has_almost_full => 0, c_has_rst => 1, c_data_count_width => 5, c_has_wr_ack => 0, c_use_ecc => 0, c_wr_ack_low => 0, c_common_clock => 0, c_rd_pntr_width => 5, c_use_fwft_data_count => 0, c_has_almost_empty => 0, c_rd_data_count_width => 1, c_enable_rlocs => 0, c_wr_pntr_width => 5, c_overflow_low => 0, c_prog_empty_type => 0, c_optimization_mode => 0, c_wr_data_count_width => 1, c_preload_regs => 0, c_dout_rst_val => "0", c_has_data_count => 0, c_prog_full_thresh_negate_val => 28, c_wr_depth => 32, c_prog_empty_thresh_negate_val => 3, c_prog_empty_thresh_assert_val => 2, c_has_valid => 0, c_init_wr_pntr_val => 0, c_prog_full_thresh_assert_val => 29, c_use_fifo16_flags => 0, c_has_backup => 0, c_valid_low => 0, c_prim_fifo_type => "512x36", c_count_type => 0, c_prog_full_type => 0, c_memory_type => 2); -- synthesis translate_on BEGIN -- synthesis translate_off U0 : wrapped_fifo_generator_spartan6_6_1_a1065cba3626fc97 port map ( rst => rst, wr_clk => wr_clk, rd_clk => rd_clk, din => din, wr_en => wr_en, rd_en => rd_en, dout => dout, full => full, empty => empty, rd_data_count => rd_data_count, wr_data_count => wr_data_count); -- synthesis translate_on END fifo_generator_spartan6_6_1_a1065cba3626fc97_a;
gpl-3.0
c334e889f599851e6a6bffb5ad7be4fe
0.568767
3.361465
false
false
false
false
tghaefli/ADD
EDK/IVK_Repos/IVK_IPLib/pcores/ivk_video_gen_v2_01_a/hdl/vhdl/user_logic.vhd
1
28,399
------------------------------------------------------------------ -- _____ -- / \ -- /____ \____ -- / \===\ \==/ -- /___\===\___\/ AVNET -- \======/ -- \====/ ----------------------------------------------------------------- -- -- This design is the property of Avnet. Publication of this -- design is not authorized without written consent from Avnet. -- -- Please direct any questions to: [email protected] -- -- Disclaimer: -- Avnet, Inc. makes no warranty for the use of this code or design. -- This code is provided "As Is". Avnet, Inc assumes no responsibility for -- any errors, which may appear in this code, nor does it make a commitment -- to update the information contained herein. Avnet, Inc specifically -- disclaims any implied warranties of fitness for a particular purpose. -- Copyright(c) 2010 Avnet, Inc. -- All rights reserved. -- ------------------------------------------------------------------ -- -- Create Date: Dec 03, 2009 -- Design Name: IVK -- Module Name: ivk_video_gen\user_logic.vhd -- Project Name: IVK -- Target Devices: Spartan-6 -- Avnet Boards: IVK -- -- Tool versions: ISE 12.1 -- -- Description: -- -- Dependencies: -- -- Revision: Dec 03, 2009: 1.00 Initial version -- Feb 01, 2010: 1.02 Add selectable video interface -- Feb 10, 2010: 1.02b Fix XSVI video_data ordering: -- [23:16] = red -- [15: 8] = blue -- [ 7: 0] = green -- Mar 02, 2010: 1.03 Add optionnal VDMA Write Port -- Mar 10, 2010: 1.04 Force FSYNC to active high polarity -- Apr 12, 2010: 1.05 Fix VBlank/HBlank outputs -- Apr 13, 2010: 1.06 Add support for 16bit data width on XSVI input -- May 14, 2010: 2.01 Update for 12.1 -- ------------------------------------------------------------------ -- DO NOT EDIT BELOW THIS LINE -------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library proc_common_v3_00_a; use proc_common_v3_00_a.proc_common_pkg.all; -- DO NOT EDIT ABOVE THIS LINE -------------------- --USER libraries added here ------------------------------------------------------------------------------ -- Entity section ------------------------------------------------------------------------------ -- Definition of Generics: -- C_SLV_DWIDTH -- Slave interface data bus width -- C_NUM_REG -- Number of software accessible registers -- -- Definition of Ports: -- Bus2IP_Clk -- Bus to IP clock -- Bus2IP_Reset -- Bus to IP reset -- Bus2IP_Data -- Bus to IP data bus -- Bus2IP_BE -- Bus to IP byte enables -- Bus2IP_RdCE -- Bus to IP read chip enable -- Bus2IP_WrCE -- Bus to IP write chip enable -- IP2Bus_Data -- IP to Bus data bus -- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement -- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement -- IP2Bus_Error -- IP to Bus error response ------------------------------------------------------------------------------ entity user_logic is generic ( -- ADD USER GENERICS BELOW THIS LINE --------------- C_GEN_FSYNC : integer := 0; C_GEN_RD_VDMA : integer := 0; C_VIDEO_INTERFACE : integer := 2; C_XSVI_DATA_WIDTH : integer := 24; C_VDMA_DATA_WIDTH : integer := 32; -- ADD USER GENERICS ABOVE THIS LINE --------------- -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol parameters, do not add to or delete C_SLV_DWIDTH : integer := 32; C_NUM_REG : integer := 4; C_FAMILY : string := "spartan6" -- DO NOT EDIT ABOVE THIS LINE --------------------- ); port ( -- ADD USER PORTS BELOW THIS LINE ------------------ -- Global Reset (asynchronous) reset : in std_logic; clk : in std_logic; -- Camera Port camera_frame_valid_o : out std_logic; camera_line_valid_o : out std_logic; camera_data_o : out std_logic_vector((C_XSVI_DATA_WIDTH-1) downto 0); -- DVI Port dvi_vsync_o : out std_logic; dvi_hsync_o : out std_logic; dvi_de_o : out std_logic; dvi_red_o : out std_logic_vector(7 downto 0); dvi_green_o : out std_logic_vector(7 downto 0); dvi_blue_o : out std_logic_vector(7 downto 0); -- XSVI Port xsvi_vsync_o : out std_logic; xsvi_hsync_o : out std_logic; xsvi_vblank_o : out std_logic; xsvi_hblank_o : out std_logic; xsvi_active_video_o : out std_logic; xsvi_video_data_o : out std_logic_vector((C_XSVI_DATA_WIDTH-1) downto 0); -- VDMA Read Port --vdma_rcmd_clk : out std_logic; vdma_rd_clk : out std_logic; vdma_rd_read : out std_logic; vdma_rd_data : in std_logic_vector((C_VDMA_DATA_WIDTH-1) downto 0); -- Frame Sync Output Port fsync_o : out std_logic; -- ADD USER PORTS ABOVE THIS LINE ------------------ -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol ports, do not add to or delete Bus2IP_Clk : in std_logic; Bus2IP_Reset : in std_logic; Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1); Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1); Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1); Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1); IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1); IP2Bus_RdAck : out std_logic; IP2Bus_WrAck : out std_logic; IP2Bus_Error : out std_logic -- DO NOT EDIT ABOVE THIS LINE --------------------- ); attribute SIGIS : string; attribute SIGIS of Bus2IP_Clk : signal is "CLK"; attribute SIGIS of Bus2IP_Reset : signal is "RST"; end entity user_logic; ------------------------------------------------------------------------------ -- Architecture section ------------------------------------------------------------------------------ architecture rtl of user_logic is function toLittleEndian (a : std_logic_vector) return std_logic_vector is variable result : std_logic_vector(a'length-1 downto 0); begin for i in result'RANGE loop result(i) := a(a'length-1-i); end loop; return result; end; function toBigEndian (a: std_logic_vector) return std_logic_vector is variable result : std_logic_vector(0 to a'length-1); begin for i in result'RANGE loop result(i) := a(a'length-1-i); end loop; return result; end; ------------------------------------------ -- Signals for user logic slave model s/w accessible register example ------------------------------------------ signal slv_reg0 : std_logic_vector(0 to C_SLV_DWIDTH-1); signal slv_reg1 : std_logic_vector(0 to C_SLV_DWIDTH-1); signal slv_reg2 : std_logic_vector(0 to C_SLV_DWIDTH-1); signal slv_reg3 : std_logic_vector(0 to C_SLV_DWIDTH-1); signal slv_reg_write_sel : std_logic_vector(0 to 3); signal slv_reg_read_sel : std_logic_vector(0 to 3); signal slv_ip2bus_data : std_logic_vector(0 to C_SLV_DWIDTH-1); signal slv_read_ack : std_logic; signal slv_write_ack : std_logic; signal rd_hsync1_reg : std_logic_vector(31 downto 0); signal rd_hsync2_reg : std_logic_vector(31 downto 0); signal rd_vsync1_reg : std_logic_vector(31 downto 0); signal rd_vsync2_reg : std_logic_vector(31 downto 0); -- -- Video Synchronization Generator -- constant HWidth_c : integer := 16; constant VWidth_c : integer := 16; component VideoSyncGen generic ( HWidth_g : integer := 16; VWidth_g : integer := 16 ); port ( -- Global Reset i_Clk_p : in std_logic; i_Reset_p : in std_logic; -- Video Configuration iv16_VidHActive_p : in std_logic_vector(15 downto 0); iv16_VidHFPorch_p : in std_logic_vector(15 downto 0); iv16_VidHSync_p : in std_logic_vector(15 downto 0); iv16_VidHBPorch_p : in std_logic_vector(15 downto 0); -- iv16_VidVActive_p : in std_logic_vector(15 downto 0); iv16_VidVFPorch_p : in std_logic_vector(15 downto 0); iv16_VidVSync_p : in std_logic_vector(15 downto 0); iv16_VidVBPorch_p : in std_logic_vector(15 downto 0); -- Video Synchronization Signals o_HBlank_p : out std_logic; o_VBlank_p : out std_logic; o_HSync_p : out std_logic; o_VSync_p : out std_logic; o_De_p : out std_logic; -- Data Request strobe (1 cycle in advance of synchronization signals) ov_HCount_p : out std_logic_vector(HWidth_g-1 downto 0); ov_VCount_p : out std_logic_vector(VWidth_g-1 downto 0); o_PixelRequest_p : out std_logic ); end component; -- Video Configuration signal v16_VidHActive_s : std_logic_vector(15 downto 0); signal v16_VidHFPorch_s : std_logic_vector(15 downto 0); signal v16_VidHSync_s : std_logic_vector(15 downto 0); signal v16_VidHBPorch_s : std_logic_vector(15 downto 0); -- signal v16_VidVActive_s : std_logic_vector(15 downto 0); signal v16_VidVFPorch_s : std_logic_vector(15 downto 0); signal v16_VidVSync_s : std_logic_vector(15 downto 0); signal v16_VidVBPorch_s : std_logic_vector(15 downto 0); -- Video Synchronization Signals signal RdVideoHBlank_s : std_logic; signal RdVideoVBlank_s : std_logic; signal RdVideoHSync_s : std_logic; signal RdVideoVSync_s : std_logic; signal RdVideoDe_s : std_logic; signal RdVideoDeA1_s : std_logic; -- 1 cycle in advance of VideoDe_s -- Data Request strobe (1 cycle in advance of synchronization signals) signal v_RdVideoHCount_s : std_logic_vector(HWidth_c-1 downto 0); signal v_RdVideoVCount_s : std_logic_vector(VWidth_c-1 downto 0); -- signal RdVideoPixelRequest_s : std_logic; -- -- Color Bar Generator -- component ColorBarGen generic ( HWidth_g : integer := 16; VWidth_g : integer := 16 ); port ( -- Global Reset i_clk_p : in std_logic; i_Reset_p : in std_logic; -- Image Size iv_HActive_p : in std_logic_vector(HWidth_g-1 downto 0); iv_VActive_p : in std_logic_vector(VWidth_g-1 downto 0); -- Data Request strobe (1 cycle in advance of synchronization signals) iv_HCount_p : in std_logic_vector(HWidth_g-1 downto 0); iv_VCount_p : in std_logic_vector(VWidth_g-1 downto 0); i_PixelRequest_p : in std_logic; -- Pixel Output o_PixelValid_p : out std_logic; ov8_RPixel_p : out std_logic_vector(7 downto 0); ov8_GPixel_p : out std_logic_vector(7 downto 0); ov8_BPixel_p : out std_logic_vector(7 downto 0) ); end component; signal ColorBarValid_s : std_logic; signal v8_ColorBarRed_s : std_logic_vector(7 downto 0); signal v8_ColorBarGreen_s : std_logic_vector(7 downto 0); signal v8_ColorBarBlue_s : std_logic_vector(7 downto 0); -- -- Vsync Polarity Detection -- signal vsync_polarity : std_logic; begin --USER logic implementation added here ------------------------------------------ -- Example code to read/write user logic slave model s/w accessible registers -- -- Note: -- The example code presented here is to show you one way of reading/writing -- software accessible registers implemented in the user logic slave model. -- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond -- to one software accessible register by the top level template. For example, -- if you have four 32 bit software accessible registers in the user logic, -- you are basically operating on the following memory mapped registers: -- -- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register -- "10000000" C_BASEADDR + 0x00 -- "01000000" C_BASEADDR + 0x04 -- "00100000" C_BASEADDR + 0x08 -- "00010000" C_BASEADDR + 0x0C -- "00001000" C_BASEADDR + 0x10 -- "00000100" C_BASEADDR + 0x14 -- "00000010" C_BASEADDR + 0x18 -- "00000001" C_BASEADDR + 0x1C -- ------------------------------------------ slv_reg_write_sel <= Bus2IP_WrCE(0 to C_NUM_REG-1); slv_reg_read_sel <= Bus2IP_RdCE(0 to C_NUM_REG-1); slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3); slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1) or Bus2IP_RdCE(2) or Bus2IP_RdCE(3); -- implement slave model software accessible register(s) SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is begin if Bus2IP_Clk'event and Bus2IP_Clk = '1' then if Bus2IP_Reset = '1' then slv_reg0 <= (others => '0'); slv_reg1 <= (others => '0'); slv_reg2 <= (others => '0'); slv_reg3 <= (others => '0'); else case slv_reg_write_sel is when "1000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg0(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7); end if; end loop; when "0100" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg1(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7); end if; end loop; when "0010" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg2(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7); end if; end loop; when "0001" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg3(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7); end if; end loop; when others => null; end case; end if; end if; end process SLAVE_REG_WRITE_PROC; -- implement slave model software accessible register(s) read mux SLAVE_REG_READ_PROC : process( slv_reg_read_sel ) is begin case slv_reg_read_sel is when "1000" => slv_ip2bus_data <= slv_reg0; when "0100" => slv_ip2bus_data <= slv_reg1; when "0010" => slv_ip2bus_data <= slv_reg2; when "0001" => slv_ip2bus_data <= slv_reg3; when others => slv_ip2bus_data <= (others => '0'); end case; end process SLAVE_REG_READ_PROC; IP_REG_PROC : process(clk) is begin if rising_edge(clk) then rd_hsync1_reg <= toLittleEndian(slv_reg0); rd_hsync2_reg <= toLittleEndian(slv_reg1); rd_vsync1_reg <= toLittleEndian(slv_reg2); rd_vsync2_reg <= toLittleEndian(slv_reg3); end if; end process IP_REG_PROC; v16_VidHActive_s <= rd_hsync1_reg(31 downto 16); v16_VidHFPorch_s <= rd_hsync1_reg(15 downto 0); v16_VidHSync_s <= rd_hsync2_reg(31 downto 16); v16_VidHBPorch_s <= rd_hsync2_reg(15 downto 0); v16_VidVActive_s <= rd_vsync1_reg(31 downto 16); v16_VidVFPorch_s <= rd_vsync1_reg(15 downto 0); v16_VidVSync_s <= rd_vsync2_reg(31 downto 16); v16_VidVBPorch_s <= rd_vsync2_reg(15 downto 0); ------------------------------------------ -- Example code to drive IP to Bus signals ------------------------------------------ IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else (others => '0'); IP2Bus_WrAck <= slv_write_ack; IP2Bus_RdAck <= slv_read_ack; IP2Bus_Error <= '0'; -- -- Video Synchronization Generator -- VideoSyncGen_l : VideoSyncGen generic map ( HWidth_g => HWidth_c, VWidth_g => VWidth_c ) port map ( -- Global Reset i_Clk_p => clk, i_Reset_p => reset, -- Video Configuration iv16_VidHActive_p => v16_VidHActive_s, iv16_VidHFPorch_p => v16_VidHFPorch_s, iv16_VidHSync_p => v16_VidHSync_s, iv16_VidHBPorch_p => v16_VidHBPorch_s, -- iv16_VidVActive_p => v16_VidVActive_s, iv16_VidVFPorch_p => v16_VidVFPorch_s, iv16_VidVSync_p => v16_VidVSync_s, iv16_VidVBPorch_p => v16_VidVBPorch_s, -- Video Synchronization Signals o_HBlank_p => RdVideoHBlank_s, o_VBlank_p => RdVideoVBlank_s, o_HSync_p => RdVideoHSync_s, o_VSync_p => RdVideoVSync_s, o_De_p => RdVideoDe_s, -- Data Request strobe (1 cycle in advance of synchronization signals) ov_HCount_p => v_RdVideoHCount_s, ov_VCount_p => v_RdVideoVCount_s, o_PixelRequest_p => RdVideoDeA1_s ); -- -- Color Bar Generator -- PIXELS_FROM_COLORBARGEN : if ( C_GEN_RD_VDMA = 0 ) generate ColorBarGen_l : ColorBarGen generic map ( HWidth_g => HWidth_c, VWidth_g => VWidth_c ) port map ( -- Global Reset i_clk_p => clk, i_Reset_p => reset, -- Image Size iv_HActive_p => v16_VidHActive_s, iv_VActive_p => v16_VidVActive_s, -- Data Request strobe (1 cycle in advance of synchronization signals) iv_HCount_p => v_RdVideoHCount_s, iv_VCount_p => v_RdVideoVCount_s, i_PixelRequest_p => RdVideoDeA1_s, -- Pixel Output o_PixelValid_p => ColorBarValid_s, ov8_RPixel_p => v8_ColorBarRed_s, ov8_GPixel_p => v8_ColorBarGreen_s, ov8_BPixel_p => v8_ColorBarBlue_s ); end generate PIXELS_FROM_COLORBARGEN; -- -- VDMA Read Port -- --vdma_rcmd_clk <= clk; vdma_rd_clk <= clk; vdma_rd_read <= RdVideoDeA1_s; PIXELS_FROM_RD_VDMA : if ( C_GEN_RD_VDMA = 1 ) generate VDMA_DATA_8BIT_GEN : if (C_VDMA_DATA_WIDTH = 8) generate v8_ColorBarRed_s <= X"00"; v8_ColorBarGreen_s <= vdma_rd_data( 7 downto 0); v8_ColorBarBlue_s <= X"00"; end generate VDMA_DATA_8BIT_GEN; VDMA_DATA_16BIT_GEN : if (C_VDMA_DATA_WIDTH = 16) generate v8_ColorBarRed_s <= X"00"; v8_ColorBarGreen_s <= vdma_rd_data( 7 downto 0); v8_ColorBarBlue_s <= vdma_rd_data(15 downto 8); end generate VDMA_DATA_16BIT_GEN; VDMA_DATA_32BIT_GEN : if (C_VDMA_DATA_WIDTH = 32) generate v8_ColorBarRed_s <= vdma_rd_data(23 downto 16); v8_ColorBarGreen_s <= vdma_rd_data( 7 downto 0); v8_ColorBarBlue_s <= vdma_rd_data(15 downto 8); end generate VDMA_DATA_32BIT_GEN; end generate PIXELS_FROM_RD_VDMA; -- -- Camera Port -- CAMERA_OPORT_GEN : if (C_VIDEO_INTERFACE = 0) generate CAMERA_8BIT_GEN : if (C_XSVI_DATA_WIDTH = 8) generate camera_8bit_oregs_l : process (clk) begin if rising_edge( clk ) then camera_frame_valid_o <= RdVideoVSync_s; camera_line_valid_o <= RdVideoDe_s; camera_data_o <= v8_ColorBarRed_s; end if; end process; end generate CAMERA_8BIT_GEN; CAMERA_10BIT_GEN : if (C_XSVI_DATA_WIDTH = 10) generate camera_10bit_oregs_l : process (clk) begin if rising_edge( clk ) then camera_frame_valid_o <= RdVideoVSync_s; camera_line_valid_o <= RdVideoDe_s; camera_data_o <= v8_ColorBarRed_s & "00"; end if; end process; end generate CAMERA_10BIT_GEN; -- dvi_vsync_o <= '0'; dvi_hsync_o <= '0'; dvi_de_o <= '0'; dvi_red_o <= (others => '0'); dvi_green_o <= (others => '0'); dvi_blue_o <= (others => '0'); -- xsvi_vsync_o <= '0'; xsvi_hsync_o <= '0'; xsvi_vblank_o <= '0'; xsvi_hblank_o <= '0'; xsvi_active_video_o <= '0'; xsvi_video_data_o <= (others => '0'); end generate CAMERA_OPORT_GEN; -- -- DVI Port -- DVI_OPORT_GEN : if (C_VIDEO_INTERFACE = 1) generate dvi_oregs_l : process (clk) begin if rising_edge( clk ) then dvi_vsync_o <= RdVideoVSync_s; dvi_hsync_o <= RdVideoHSync_s; dvi_de_o <= RdVideoDe_s; dvi_red_o <= v8_ColorBarRed_s; dvi_green_o <= v8_ColorBarGreen_s; dvi_blue_o <= v8_ColorBarBlue_s; end if; end process; -- camera_frame_valid_o <= '0'; camera_line_valid_o <= '0'; camera_data_o <= (others => '0'); -- xsvi_vsync_o <= '0'; xsvi_hsync_o <= '0'; xsvi_vblank_o <= '0'; xsvi_hblank_o <= '0'; xsvi_active_video_o <= '0'; xsvi_video_data_o <= (others => '0'); end generate DVI_OPORT_GEN; -- -- XSVI Port -- XSVI_OPORT_GEN : if (C_VIDEO_INTERFACE = 2) generate XSVI_8BIT_GEN : if (C_XSVI_DATA_WIDTH = 8) generate xsvi_8bit_oregs_l : process (clk) begin if rising_edge( clk ) then xsvi_vsync_o <= RdVideoVSync_s; xsvi_hsync_o <= RdVideoHSync_s; xsvi_vblank_o <= RdVideoVBlank_s; xsvi_hblank_o <= RdVideoHBlank_s; xsvi_active_video_o <= RdVideoDe_s; xsvi_video_data_o <= v8_ColorBarRed_s; end if; end process; end generate XSVI_8BIT_GEN; XSVI_10BIT_GEN : if (C_XSVI_DATA_WIDTH = 10) generate xsvi_10bit_oregs_l : process (clk) begin if rising_edge( clk ) then xsvi_vsync_o <= RdVideoVSync_s; xsvi_hsync_o <= RdVideoHSync_s; xsvi_vblank_o <= RdVideoVBlank_s; xsvi_hblank_o <= RdVideoHBlank_s; xsvi_active_video_o <= RdVideoDe_s; xsvi_video_data_o <= v8_ColorBarRed_s & "00"; end if; end process; end generate XSVI_10BIT_GEN; XSVI_16BIT_GEN : if (C_XSVI_DATA_WIDTH = 16) generate xsvi_16bit_oregs_l : process (clk) begin if rising_edge( clk ) then xsvi_vsync_o <= RdVideoVSync_s; xsvi_hsync_o <= RdVideoHSync_s; xsvi_vblank_o <= RdVideoVBlank_s; xsvi_hblank_o <= RdVideoHBlank_s; xsvi_active_video_o <= RdVideoDe_s; xsvi_video_data_o <= v8_ColorBarBlue_s & v8_ColorBarGreen_s; end if; end process; end generate XSVI_16BIT_GEN; XSVI_24BIT_GEN : if (C_XSVI_DATA_WIDTH = 24) generate xsvi_24bit_oregs_l : process (clk) begin if rising_edge( clk ) then xsvi_vsync_o <= RdVideoVSync_s; xsvi_hsync_o <= RdVideoHSync_s; xsvi_vblank_o <= RdVideoVBlank_s; xsvi_hblank_o <= RdVideoHBlank_s; xsvi_active_video_o <= RdVideoDe_s; xsvi_video_data_o <= v8_ColorBarRed_s & v8_ColorBarBlue_s & v8_ColorBarGreen_s; end if; end process; end generate XSVI_24BIT_GEN; XSVI_32BIT_GEN : if (C_XSVI_DATA_WIDTH = 32) generate xsvi_24bit_oregs_l : process (clk) begin if rising_edge( clk ) then xsvi_vsync_o <= RdVideoVSync_s; xsvi_hsync_o <= RdVideoHSync_s; xsvi_vblank_o <= RdVideoVBlank_s; xsvi_hblank_o <= RdVideoHBlank_s; xsvi_active_video_o <= RdVideoDe_s; xsvi_video_data_o <= "00000000" & v8_ColorBarRed_s & v8_ColorBarBlue_s & v8_ColorBarGreen_s; end if; end process; end generate XSVI_32BIT_GEN; -- camera_frame_valid_o <= '0'; camera_line_valid_o <= '0'; camera_data_o <= (others => '0'); -- dvi_vsync_o <= '0'; dvi_hsync_o <= '0'; dvi_de_o <= '0'; dvi_red_o <= (others => '0'); dvi_green_o <= (others => '0'); dvi_blue_o <= (others => '0'); end generate XSVI_OPORT_GEN; -- -- Vsync Polarity Detection -- vsync_polarity_l : process (clk) begin if rising_edge( clk ) then if ( RdVideoDe_s = '1' ) then vsync_polarity <= not RdVideoVSync_s; end if; end if; end process; -- -- Frame Sync Output Port -- fsync_l : process (clk) begin if rising_edge( clk ) then if ( vsync_polarity = '1' ) then fsync_o <= RdVideoVSync_s; else fsync_o <= not RdVideoVSync_s; end if; end if; end process; end rtl;
gpl-3.0
466363946eeb63a8e690684993b6bf73
0.47963
3.697305
false
false
false
false
fquinto/Wireless_sensor_network
Avnet_UPC/hdl/msp430_uart_wrapper.vhd
1
6,704
------------------------------------------------------------------------------- -- msp430_uart_wrapper.vhd ------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; library xps_uartlite_v1_01_a; use xps_uartlite_v1_01_a.all; entity msp430_uart_wrapper is port ( SPLB_Clk : in std_logic; SPLB_Rst : in std_logic; PLB_ABus : in std_logic_vector(0 to 31); PLB_PAValid : in std_logic; PLB_masterID : in std_logic_vector(0 to 0); PLB_RNW : in std_logic; PLB_BE : in std_logic_vector(0 to 3); PLB_size : in std_logic_vector(0 to 3); PLB_type : in std_logic_vector(0 to 2); PLB_wrDBus : in std_logic_vector(0 to 31); PLB_UABus : in std_logic_vector(0 to 31); PLB_SAValid : in std_logic; PLB_rdPrim : in std_logic; PLB_wrPrim : in std_logic; PLB_abort : in std_logic; PLB_busLock : in std_logic; PLB_MSize : in std_logic_vector(0 to 1); PLB_lockErr : in std_logic; PLB_wrBurst : in std_logic; PLB_rdBurst : in std_logic; PLB_wrPendReq : in std_logic; PLB_rdPendReq : in std_logic; PLB_wrPendPri : in std_logic_vector(0 to 1); PLB_rdPendPri : in std_logic_vector(0 to 1); PLB_reqPri : in std_logic_vector(0 to 1); PLB_TAttribute : in std_logic_vector(0 to 15); Sl_addrAck : out std_logic; Sl_SSize : out std_logic_vector(0 to 1); Sl_wait : out std_logic; Sl_rearbitrate : out std_logic; Sl_wrDAck : out std_logic; Sl_wrComp : out std_logic; Sl_rdDBus : out std_logic_vector(0 to 31); Sl_rdDAck : out std_logic; Sl_rdComp : out std_logic; Sl_MBusy : out std_logic_vector(0 to 1); Sl_MWrErr : out std_logic_vector(0 to 1); Sl_MRdErr : out std_logic_vector(0 to 1); Sl_wrBTerm : out std_logic; Sl_rdWdAddr : out std_logic_vector(0 to 3); Sl_rdBTerm : out std_logic; Sl_MIRQ : out std_logic_vector(0 to 1); RX : in std_logic; TX : out std_logic; Interrupt : out std_logic ); attribute x_core_info : STRING; attribute x_core_info of msp430_uart_wrapper : entity is "xps_uartlite_v1_01_a"; end msp430_uart_wrapper; architecture STRUCTURE of msp430_uart_wrapper is component xps_uartlite is generic ( C_FAMILY : STRING; C_SPLB_CLK_FREQ_HZ : INTEGER; C_BASEADDR : std_logic_vector(0 to 31); C_HIGHADDR : std_logic_vector(0 to 31); C_SPLB_AWIDTH : INTEGER; C_SPLB_DWIDTH : INTEGER; C_SPLB_P2P : INTEGER; C_SPLB_MID_WIDTH : INTEGER; C_SPLB_NUM_MASTERS : INTEGER; C_SPLB_SUPPORT_BURSTS : INTEGER; C_SPLB_NATIVE_DWIDTH : INTEGER; C_BAUDRATE : INTEGER; C_DATA_BITS : INTEGER; C_USE_PARITY : INTEGER; C_ODD_PARITY : INTEGER ); port ( SPLB_Clk : in std_logic; SPLB_Rst : in std_logic; PLB_ABus : in std_logic_vector(0 to 31); PLB_PAValid : in std_logic; PLB_masterID : in std_logic_vector(0 to (C_SPLB_MID_WIDTH-1)); PLB_RNW : in std_logic; PLB_BE : in std_logic_vector(0 to ((C_SPLB_DWIDTH/8)-1)); PLB_size : in std_logic_vector(0 to 3); PLB_type : in std_logic_vector(0 to 2); PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_DWIDTH-1)); PLB_UABus : in std_logic_vector(0 to 31); PLB_SAValid : in std_logic; PLB_rdPrim : in std_logic; PLB_wrPrim : in std_logic; PLB_abort : in std_logic; PLB_busLock : in std_logic; PLB_MSize : in std_logic_vector(0 to 1); PLB_lockErr : in std_logic; PLB_wrBurst : in std_logic; PLB_rdBurst : in std_logic; PLB_wrPendReq : in std_logic; PLB_rdPendReq : in std_logic; PLB_wrPendPri : in std_logic_vector(0 to 1); PLB_rdPendPri : in std_logic_vector(0 to 1); PLB_reqPri : in std_logic_vector(0 to 1); PLB_TAttribute : in std_logic_vector(0 to 15); Sl_addrAck : out std_logic; Sl_SSize : out std_logic_vector(0 to 1); Sl_wait : out std_logic; Sl_rearbitrate : out std_logic; Sl_wrDAck : out std_logic; Sl_wrComp : out std_logic; Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_DWIDTH-1)); Sl_rdDAck : out std_logic; Sl_rdComp : out std_logic; Sl_MBusy : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1)); Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1)); Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1)); Sl_wrBTerm : out std_logic; Sl_rdWdAddr : out std_logic_vector(0 to 3); Sl_rdBTerm : out std_logic; Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1)); RX : in std_logic; TX : out std_logic; Interrupt : out std_logic ); end component; begin MSP430_UART : xps_uartlite generic map ( C_FAMILY => "spartan3a", C_SPLB_CLK_FREQ_HZ => 66666666, C_BASEADDR => X"81700000", C_HIGHADDR => X"8170FFFF", C_SPLB_AWIDTH => 32, C_SPLB_DWIDTH => 32, C_SPLB_P2P => 0, C_SPLB_MID_WIDTH => 1, C_SPLB_NUM_MASTERS => 2, C_SPLB_SUPPORT_BURSTS => 0, C_SPLB_NATIVE_DWIDTH => 32, C_BAUDRATE => 9600, C_DATA_BITS => 8, C_USE_PARITY => 0, C_ODD_PARITY => 1 ) port map ( SPLB_Clk => SPLB_Clk, SPLB_Rst => SPLB_Rst, PLB_ABus => PLB_ABus, PLB_PAValid => PLB_PAValid, PLB_masterID => PLB_masterID, PLB_RNW => PLB_RNW, PLB_BE => PLB_BE, PLB_size => PLB_size, PLB_type => PLB_type, PLB_wrDBus => PLB_wrDBus, PLB_UABus => PLB_UABus, PLB_SAValid => PLB_SAValid, PLB_rdPrim => PLB_rdPrim, PLB_wrPrim => PLB_wrPrim, PLB_abort => PLB_abort, PLB_busLock => PLB_busLock, PLB_MSize => PLB_MSize, PLB_lockErr => PLB_lockErr, PLB_wrBurst => PLB_wrBurst, PLB_rdBurst => PLB_rdBurst, PLB_wrPendReq => PLB_wrPendReq, PLB_rdPendReq => PLB_rdPendReq, PLB_wrPendPri => PLB_wrPendPri, PLB_rdPendPri => PLB_rdPendPri, PLB_reqPri => PLB_reqPri, PLB_TAttribute => PLB_TAttribute, Sl_addrAck => Sl_addrAck, Sl_SSize => Sl_SSize, Sl_wait => Sl_wait, Sl_rearbitrate => Sl_rearbitrate, Sl_wrDAck => Sl_wrDAck, Sl_wrComp => Sl_wrComp, Sl_rdDBus => Sl_rdDBus, Sl_rdDAck => Sl_rdDAck, Sl_rdComp => Sl_rdComp, Sl_MBusy => Sl_MBusy, Sl_MWrErr => Sl_MWrErr, Sl_MRdErr => Sl_MRdErr, Sl_wrBTerm => Sl_wrBTerm, Sl_rdWdAddr => Sl_rdWdAddr, Sl_rdBTerm => Sl_rdBTerm, Sl_MIRQ => Sl_MIRQ, RX => RX, TX => TX, Interrupt => Interrupt ); end architecture STRUCTURE;
mit
db7305bae7a3ce1045d937cd7610291b
0.582488
3.216891
false
false
false
false
hoglet67/AtomFpga
src/xilinx/DCM/dcm1.vhd
2
2,052
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library UNISIM; use UNISIM.Vcomponents.all; entity dcm1 is port (CLKIN_IN : in std_logic; CLK0_OUT : out std_logic; CLK0_OUT1 : out std_logic; CLK2X_OUT : out std_logic); end dcm1; architecture BEHAVIORAL of dcm1 is signal CLKFX_BUF : std_logic; signal CLKIN_IBUFG : std_logic; signal GND_BIT : std_logic; begin GND_BIT <= '0'; CLKFX_BUFG_INST : BUFG port map (I => CLKFX_BUF, O => CLK0_OUT); DCM_INST : DCM generic map(CLK_FEEDBACK => "NONE", CLKDV_DIVIDE => 4.0, -- 12.5000 = 25 * 10 / 20 CLKFX_DIVIDE => 20, CLKFX_MULTIPLY => 10, CLKIN_DIVIDE_BY_2 => false, CLKIN_PERIOD => 40.000, CLKOUT_PHASE_SHIFT => "NONE", DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW", DUTY_CYCLE_CORRECTION => true, FACTORY_JF => x"C080", PHASE_SHIFT => 0, STARTUP_WAIT => false) port map (CLKFB => GND_BIT, CLKIN => CLKIN_IN, DSSEN => GND_BIT, PSCLK => GND_BIT, PSEN => GND_BIT, PSINCDEC => GND_BIT, RST => GND_BIT, CLKDV => open, CLKFX => CLKFX_BUF, CLKFX180 => open, CLK0 => open, CLK2X => open, CLK2X180 => open, CLK90 => open, CLK180 => open, CLK270 => open, LOCKED => open, PSDONE => open, STATUS => open); end BEHAVIORAL;
apache-2.0
ee232466b48f11ff30401f5ae4e8f645
0.403509
4.301887
false
false
false
false
abyrne55/my-little-processor
PC.vhd
1
636
LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY PC IS PORT ( input : IN std_logic_vector(15 DOWNTO 0); en_in, clock, done, reset : IN std_logic; read_addr : OUT INTEGER ); END PC; ARCHITECTURE behavioural OF PC IS SIGNAL addr_temp : INTEGER := 0; BEGIN PROCESS (clock, done, reset, en_in, input) BEGIN IF reset = '1' THEN addr_temp <= 0; ELSIF en_in = '1' THEN addr_temp <= to_integer(unsigned(input)); ELSIF rising_edge(clock) AND done = '1' THEN addr_temp <= addr_temp + 1; END IF; END PROCESS; read_addr <= addr_temp; END behavioural;
mit
679af3114445f4fd50d2c1490b18874b
0.625786
2.930876
false
false
false
false
bertuccio/ARQ
Practica5/sistema_tb.vhd
1
2,143
-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 10:32:33 11/27/2009 -- Design Name: -- Module Name: D:/practica3/sistema_tb.vhd -- Project Name: proyecto -- Target Device: -- Tool versions: -- Description: -- -- VHDL Test Bench Created by ISE for module: sistema -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY sistema_tb IS END sistema_tb; ARCHITECTURE behavior OF sistema_tb IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT sistema PORT( Clk : IN std_logic; Reset : IN std_logic; data_perif_1 : INOUT std_logic_vector(7 downto 0); data_perif_2 : INOUT std_logic_vector(7 downto 0) ); END COMPONENT; --Inputs signal Clk : std_logic := '0'; signal Reset : std_logic := '0'; --BiDirs signal data_perif_1 : std_logic_vector(7 downto 0); signal data_perif_2 : std_logic_vector(7 downto 0); BEGIN -- Instantiate the Unit Under Test (UUT) uut: sistema PORT MAP ( Clk => Clk, Reset => Reset, data_perif_1 => data_perif_1, data_perif_2 => data_perif_2 ); process begin RESET <= '1'; wait for 20 ns; RESET <= '0'; wait; end process; process begin CLK <= '0'; wait for 5 ns; CLK <= '1'; wait for 5 ns; end process; process begin data_perif_1 <= x"AA"; wait for 100 ns; data_perif_1 <= x"45"; wait for 100 ns; data_perif_1 <= x"37"; wait for 100 ns; end process; END;
mit
f83abdaad25fd56a8bd2203940131561
0.584694
3.456452
false
true
false
false
GSimas/EEL5105
PROJETO-EEL5105/Projeto/Moore.vhd
1
1,642
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity FSM_Conta is port( CLK, RST, PIN: in std_logic; NUM_clk: in std_logic_vector(2 downto 0); contagem: out std_logic_vector(3 downto 0) ); end FSM_Conta; architecture bhv of FSM_Conta is type states is (S0,S1,S2,S3,S4); signal C50: std_logic; signal contador: std_logic_vector(27 downto 0); signal EA, PE: states; begin P1: process(CLK, RST, NUM_clk) begin if RST = '0' then contador <= x"0000000"; EA <= S0; elsif CLK'event and CLK = '1' then contador <= contador + 1; if C50 = '1' then EA <= PE; end if; if NUM_clk = "001" and contador = x"2FAF080" then contador <= x"0000000"; C50 <= '1'; elsif NUM_clk = "010" and contador = x"17D7840" then contador <= x"0000000"; C50 <= '1'; elsif NUM_clk = "011" and contador = x"FE502B" then contador <= x"0000000"; C50 <= '1'; elsif NUM_clk = "100" and contador = x"BEBC20" then contador <= x"0000000"; C50 <= '1'; elsif NUM_clk = "100" and contador = x"989680" then contador <= x"0000000"; C50 <= '1'; else C50 <= '0'; end if; end if; end process; P2: process(EA) begin case EA is when S0 => contagem <= "0001"; PE <= S1; when S1 => contagem <= "0010"; PE <= S2; when S2 => contagem <= "0011"; PE <= S3; when S3 => contagem <= "0100"; PE <= S4; when S4 => contagem <= "0101"; PE <= S0; end case; end process; end bhv;
mit
fe032c90733708e97130cec6104be54d
0.533496
2.845754
false
false
false
false
GSimas/EEL5105
PROJETO-EEL5105/Projeto/map2.vhd
1
953
library ieee; use ieee.std_logic_1164.all; entity map2 is port ( F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13, F14, F15: out std_logic_vector(31 downto 0) ); end map2; architecture map2_struct of map2 is begin F0 <= "00000000000000011100000011000000"; F1 <= "00000001100000001000000011000000"; F2 <= "00000001100000000000000011000000"; F3 <= "00000001100000000000000011000000"; F4 <= "00000001111000011100000011000000"; F5 <= "00000000111000000000000011000000"; F6 <= "00000000001000000000000011000000"; F7 <= "00000110001000000010000000000000"; F8 <= "00000110000000000000000011000000"; F9 <= "00000000000001110000000011000000"; F10 <= "00000011000011100001000011000000"; F11 <= "00000011000000000001000011000000"; F12 <= "00000001110000000000000011000000"; F13 <= "00000000011100000100000011000000"; F14 <= "00000011000000000000000011000000"; F15 <= "00000000000110000000000011000000"; end map2_struct;
mit
8b48465085db2a5a115298b34966d5b2
0.75341
3.320557
false
false
false
false
hoglet67/AtomFpga
src/common/ROM/kernel.vhd
1
172,874
-- generated with romgen v3.0.1r4 by MikeJ truhy and eD library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; library UNISIM; use UNISIM.Vcomponents.all; entity atomkernal is port ( CLK : in std_logic; ADDR : in std_logic_vector(11 downto 0); DATA : out std_logic_vector(7 downto 0) ); end; architecture RTL of atomkernal is signal rom_addr : std_logic_vector(11 downto 0); begin p_addr : process(ADDR) begin rom_addr <= (others => '0'); rom_addr(11 downto 0) <= ADDR; end process; p_rom : process begin wait until rising_edge(CLK); DATA <= (others => '0'); case rom_addr is when x"000" => DATA <= x"50"; when x"001" => DATA <= x"4C"; when x"002" => DATA <= x"4F"; when x"003" => DATA <= x"54"; when x"004" => DATA <= x"F5"; when x"005" => DATA <= x"4E"; when x"006" => DATA <= x"44"; when x"007" => DATA <= x"52"; when x"008" => DATA <= x"41"; when x"009" => DATA <= x"57"; when x"00A" => DATA <= x"F5"; when x"00B" => DATA <= x"42"; when x"00C" => DATA <= x"4D"; when x"00D" => DATA <= x"4F"; when x"00E" => DATA <= x"56"; when x"00F" => DATA <= x"45"; when x"010" => DATA <= x"F5"; when x"011" => DATA <= x"46"; when x"012" => DATA <= x"43"; when x"013" => DATA <= x"4C"; when x"014" => DATA <= x"45"; when x"015" => DATA <= x"41"; when x"016" => DATA <= x"52"; when x"017" => DATA <= x"F6"; when x"018" => DATA <= x"7B"; when x"019" => DATA <= x"44"; when x"01A" => DATA <= x"49"; when x"01B" => DATA <= x"4D"; when x"01C" => DATA <= x"F0"; when x"01D" => DATA <= x"AE"; when x"01E" => DATA <= x"5B"; when x"01F" => DATA <= x"F2"; when x"020" => DATA <= x"A1"; when x"021" => DATA <= x"4F"; when x"022" => DATA <= x"4C"; when x"023" => DATA <= x"44"; when x"024" => DATA <= x"F5"; when x"025" => DATA <= x"31"; when x"026" => DATA <= x"57"; when x"027" => DATA <= x"41"; when x"028" => DATA <= x"49"; when x"029" => DATA <= x"54"; when x"02A" => DATA <= x"F1"; when x"02B" => DATA <= x"4C"; when x"02C" => DATA <= x"C5"; when x"02D" => DATA <= x"50"; when x"02E" => DATA <= x"A4"; when x"02F" => DATA <= x"5E"; when x"030" => DATA <= x"B1"; when x"031" => DATA <= x"05"; when x"032" => DATA <= x"C9"; when x"033" => DATA <= x"40"; when x"034" => DATA <= x"90"; when x"035" => DATA <= x"12"; when x"036" => DATA <= x"C9"; when x"037" => DATA <= x"5B"; when x"038" => DATA <= x"B0"; when x"039" => DATA <= x"0E"; when x"03A" => DATA <= x"C8"; when x"03B" => DATA <= x"D1"; when x"03C" => DATA <= x"05"; when x"03D" => DATA <= x"D0"; when x"03E" => DATA <= x"09"; when x"03F" => DATA <= x"20"; when x"040" => DATA <= x"8B"; when x"041" => DATA <= x"F0"; when x"042" => DATA <= x"20"; when x"043" => DATA <= x"4F"; when x"044" => DATA <= x"C9"; when x"045" => DATA <= x"4C"; when x"046" => DATA <= x"62"; when x"047" => DATA <= x"C9"; when x"048" => DATA <= x"4C"; when x"049" => DATA <= x"24"; when x"04A" => DATA <= x"CA"; when x"04B" => DATA <= x"A2"; when x"04C" => DATA <= x"FF"; when x"04D" => DATA <= x"A4"; when x"04E" => DATA <= x"5E"; when x"04F" => DATA <= x"C6"; when x"050" => DATA <= x"5E"; when x"051" => DATA <= x"B1"; when x"052" => DATA <= x"05"; when x"053" => DATA <= x"C9"; when x"054" => DATA <= x"40"; when x"055" => DATA <= x"90"; when x"056" => DATA <= x"09"; when x"057" => DATA <= x"C9"; when x"058" => DATA <= x"5B"; when x"059" => DATA <= x"B0"; when x"05A" => DATA <= x"05"; when x"05B" => DATA <= x"C8"; when x"05C" => DATA <= x"D1"; when x"05D" => DATA <= x"05"; when x"05E" => DATA <= x"F0"; when x"05F" => DATA <= x"25"; when x"060" => DATA <= x"A4"; when x"061" => DATA <= x"5E"; when x"062" => DATA <= x"E8"; when x"063" => DATA <= x"C8"; when x"064" => DATA <= x"BD"; when x"065" => DATA <= x"00"; when x"066" => DATA <= x"F0"; when x"067" => DATA <= x"30"; when x"068" => DATA <= x"0C"; when x"069" => DATA <= x"D1"; when x"06A" => DATA <= x"05"; when x"06B" => DATA <= x"F0"; when x"06C" => DATA <= x"F5"; when x"06D" => DATA <= x"E8"; when x"06E" => DATA <= x"BD"; when x"06F" => DATA <= x"FF"; when x"070" => DATA <= x"EF"; when x"071" => DATA <= x"10"; when x"072" => DATA <= x"FA"; when x"073" => DATA <= x"D0"; when x"074" => DATA <= x"EB"; when x"075" => DATA <= x"85"; when x"076" => DATA <= x"53"; when x"077" => DATA <= x"BD"; when x"078" => DATA <= x"01"; when x"079" => DATA <= x"F0"; when x"07A" => DATA <= x"85"; when x"07B" => DATA <= x"52"; when x"07C" => DATA <= x"84"; when x"07D" => DATA <= x"03"; when x"07E" => DATA <= x"A6"; when x"07F" => DATA <= x"04"; when x"080" => DATA <= x"E6"; when x"081" => DATA <= x"5E"; when x"082" => DATA <= x"6C"; when x"083" => DATA <= x"52"; when x"084" => DATA <= x"00"; when x"085" => DATA <= x"20"; when x"086" => DATA <= x"8B"; when x"087" => DATA <= x"F0"; when x"088" => DATA <= x"4C"; when x"089" => DATA <= x"F1"; when x"08A" => DATA <= x"C3"; when x"08B" => DATA <= x"C8"; when x"08C" => DATA <= x"84"; when x"08D" => DATA <= x"03"; when x"08E" => DATA <= x"E9"; when x"08F" => DATA <= x"40"; when x"090" => DATA <= x"48"; when x"091" => DATA <= x"20"; when x"092" => DATA <= x"BC"; when x"093" => DATA <= x"C8"; when x"094" => DATA <= x"68"; when x"095" => DATA <= x"A8"; when x"096" => DATA <= x"B5"; when x"097" => DATA <= x"15"; when x"098" => DATA <= x"0A"; when x"099" => DATA <= x"36"; when x"09A" => DATA <= x"24"; when x"09B" => DATA <= x"0A"; when x"09C" => DATA <= x"36"; when x"09D" => DATA <= x"24"; when x"09E" => DATA <= x"18"; when x"09F" => DATA <= x"79"; when x"0A0" => DATA <= x"EB"; when x"0A1" => DATA <= x"02"; when x"0A2" => DATA <= x"95"; when x"0A3" => DATA <= x"15"; when x"0A4" => DATA <= x"B5"; when x"0A5" => DATA <= x"24"; when x"0A6" => DATA <= x"79"; when x"0A7" => DATA <= x"06"; when x"0A8" => DATA <= x"03"; when x"0A9" => DATA <= x"95"; when x"0AA" => DATA <= x"24"; when x"0AB" => DATA <= x"B0"; when x"0AC" => DATA <= x"D7"; when x"0AD" => DATA <= x"60"; when x"0AE" => DATA <= x"A5"; when x"0AF" => DATA <= x"01"; when x"0B0" => DATA <= x"05"; when x"0B1" => DATA <= x"02"; when x"0B2" => DATA <= x"F0"; when x"0B3" => DATA <= x"22"; when x"0B4" => DATA <= x"20"; when x"0B5" => DATA <= x"34"; when x"0B6" => DATA <= x"C4"; when x"0B7" => DATA <= x"90"; when x"0B8" => DATA <= x"1E"; when x"0B9" => DATA <= x"20"; when x"0BA" => DATA <= x"BC"; when x"0BB" => DATA <= x"C8"; when x"0BC" => DATA <= x"CA"; when x"0BD" => DATA <= x"CA"; when x"0BE" => DATA <= x"86"; when x"0BF" => DATA <= x"04"; when x"0C0" => DATA <= x"B4"; when x"0C1" => DATA <= x"16"; when x"0C2" => DATA <= x"38"; when x"0C3" => DATA <= x"A5"; when x"0C4" => DATA <= x"23"; when x"0C5" => DATA <= x"99"; when x"0C6" => DATA <= x"21"; when x"0C7" => DATA <= x"03"; when x"0C8" => DATA <= x"75"; when x"0C9" => DATA <= x"17"; when x"0CA" => DATA <= x"85"; when x"0CB" => DATA <= x"23"; when x"0CC" => DATA <= x"A5"; when x"0CD" => DATA <= x"24"; when x"0CE" => DATA <= x"99"; when x"0CF" => DATA <= x"3C"; when x"0D0" => DATA <= x"03"; when x"0D1" => DATA <= x"75"; when x"0D2" => DATA <= x"26"; when x"0D3" => DATA <= x"4C"; when x"0D4" => DATA <= x"19"; when x"0D5" => DATA <= x"F1"; when x"0D6" => DATA <= x"00"; when x"0D7" => DATA <= x"A4"; when x"0D8" => DATA <= x"03"; when x"0D9" => DATA <= x"B1"; when x"0DA" => DATA <= x"05"; when x"0DB" => DATA <= x"C9"; when x"0DC" => DATA <= x"40"; when x"0DD" => DATA <= x"90"; when x"0DE" => DATA <= x"F7"; when x"0DF" => DATA <= x"C9"; when x"0E0" => DATA <= x"5B"; when x"0E1" => DATA <= x"B0"; when x"0E2" => DATA <= x"F3"; when x"0E3" => DATA <= x"C8"; when x"0E4" => DATA <= x"D1"; when x"0E5" => DATA <= x"05"; when x"0E6" => DATA <= x"D0"; when x"0E7" => DATA <= x"EE"; when x"0E8" => DATA <= x"E9"; when x"0E9" => DATA <= x"40"; when x"0EA" => DATA <= x"48"; when x"0EB" => DATA <= x"C8"; when x"0EC" => DATA <= x"84"; when x"0ED" => DATA <= x"03"; when x"0EE" => DATA <= x"20"; when x"0EF" => DATA <= x"BC"; when x"0F0" => DATA <= x"C8"; when x"0F1" => DATA <= x"68"; when x"0F2" => DATA <= x"A8"; when x"0F3" => DATA <= x"A5"; when x"0F4" => DATA <= x"23"; when x"0F5" => DATA <= x"99"; when x"0F6" => DATA <= x"EB"; when x"0F7" => DATA <= x"02"; when x"0F8" => DATA <= x"A5"; when x"0F9" => DATA <= x"24"; when x"0FA" => DATA <= x"99"; when x"0FB" => DATA <= x"06"; when x"0FC" => DATA <= x"03"; when x"0FD" => DATA <= x"CA"; when x"0FE" => DATA <= x"86"; when x"0FF" => DATA <= x"04"; when x"100" => DATA <= x"B4"; when x"101" => DATA <= x"16"; when x"102" => DATA <= x"C8"; when x"103" => DATA <= x"D0"; when x"104" => DATA <= x"02"; when x"105" => DATA <= x"F6"; when x"106" => DATA <= x"25"; when x"107" => DATA <= x"98"; when x"108" => DATA <= x"0A"; when x"109" => DATA <= x"36"; when x"10A" => DATA <= x"25"; when x"10B" => DATA <= x"0A"; when x"10C" => DATA <= x"36"; when x"10D" => DATA <= x"25"; when x"10E" => DATA <= x"18"; when x"10F" => DATA <= x"65"; when x"110" => DATA <= x"23"; when x"111" => DATA <= x"85"; when x"112" => DATA <= x"23"; when x"113" => DATA <= x"B5"; when x"114" => DATA <= x"25"; when x"115" => DATA <= x"65"; when x"116" => DATA <= x"24"; when x"117" => DATA <= x"B0"; when x"118" => DATA <= x"BD"; when x"119" => DATA <= x"85"; when x"11A" => DATA <= x"24"; when x"11B" => DATA <= x"A0"; when x"11C" => DATA <= x"00"; when x"11D" => DATA <= x"A9"; when x"11E" => DATA <= x"AA"; when x"11F" => DATA <= x"91"; when x"120" => DATA <= x"23"; when x"121" => DATA <= x"D1"; when x"122" => DATA <= x"23"; when x"123" => DATA <= x"D0"; when x"124" => DATA <= x"F7"; when x"125" => DATA <= x"4A"; when x"126" => DATA <= x"91"; when x"127" => DATA <= x"23"; when x"128" => DATA <= x"D1"; when x"129" => DATA <= x"23"; when x"12A" => DATA <= x"D0"; when x"12B" => DATA <= x"F0"; when x"12C" => DATA <= x"20"; when x"12D" => DATA <= x"34"; when x"12E" => DATA <= x"C4"; when x"12F" => DATA <= x"B0"; when x"130" => DATA <= x"A5"; when x"131" => DATA <= x"A4"; when x"132" => DATA <= x"03"; when x"133" => DATA <= x"B1"; when x"134" => DATA <= x"05"; when x"135" => DATA <= x"C9"; when x"136" => DATA <= x"2C"; when x"137" => DATA <= x"D0"; when x"138" => DATA <= x"05"; when x"139" => DATA <= x"E6"; when x"13A" => DATA <= x"03"; when x"13B" => DATA <= x"4C"; when x"13C" => DATA <= x"AE"; when x"13D" => DATA <= x"F0"; when x"13E" => DATA <= x"4C"; when x"13F" => DATA <= x"58"; when x"140" => DATA <= x"C5"; when x"141" => DATA <= x"A5"; when x"142" => DATA <= x"0D"; when x"143" => DATA <= x"85"; when x"144" => DATA <= x"23"; when x"145" => DATA <= x"A5"; when x"146" => DATA <= x"0E"; when x"147" => DATA <= x"85"; when x"148" => DATA <= x"24"; when x"149" => DATA <= x"4C"; when x"14A" => DATA <= x"83"; when x"14B" => DATA <= x"CE"; when x"14C" => DATA <= x"20"; when x"14D" => DATA <= x"E4"; when x"14E" => DATA <= x"C4"; when x"14F" => DATA <= x"20"; when x"150" => DATA <= x"66"; when x"151" => DATA <= x"FE"; when x"152" => DATA <= x"4C"; when x"153" => DATA <= x"5B"; when x"154" => DATA <= x"C5"; when x"155" => DATA <= x"1C"; when x"156" => DATA <= x"8A"; when x"157" => DATA <= x"1C"; when x"158" => DATA <= x"23"; when x"159" => DATA <= x"5D"; when x"15A" => DATA <= x"8B"; when x"15B" => DATA <= x"1B"; when x"15C" => DATA <= x"A1"; when x"15D" => DATA <= x"9D"; when x"15E" => DATA <= x"8A"; when x"15F" => DATA <= x"1D"; when x"160" => DATA <= x"23"; when x"161" => DATA <= x"9D"; when x"162" => DATA <= x"8B"; when x"163" => DATA <= x"1D"; when x"164" => DATA <= x"A1"; when x"165" => DATA <= x"00"; when x"166" => DATA <= x"29"; when x"167" => DATA <= x"19"; when x"168" => DATA <= x"AE"; when x"169" => DATA <= x"69"; when x"16A" => DATA <= x"A8"; when x"16B" => DATA <= x"19"; when x"16C" => DATA <= x"23"; when x"16D" => DATA <= x"24"; when x"16E" => DATA <= x"53"; when x"16F" => DATA <= x"1B"; when x"170" => DATA <= x"23"; when x"171" => DATA <= x"24"; when x"172" => DATA <= x"53"; when x"173" => DATA <= x"19"; when x"174" => DATA <= x"A1"; when x"175" => DATA <= x"00"; when x"176" => DATA <= x"1A"; when x"177" => DATA <= x"5B"; when x"178" => DATA <= x"5B"; when x"179" => DATA <= x"A5"; when x"17A" => DATA <= x"69"; when x"17B" => DATA <= x"24"; when x"17C" => DATA <= x"24"; when x"17D" => DATA <= x"AE"; when x"17E" => DATA <= x"AE"; when x"17F" => DATA <= x"A8"; when x"180" => DATA <= x"AD"; when x"181" => DATA <= x"29"; when x"182" => DATA <= x"00"; when x"183" => DATA <= x"7C"; when x"184" => DATA <= x"00"; when x"185" => DATA <= x"15"; when x"186" => DATA <= x"9C"; when x"187" => DATA <= x"6D"; when x"188" => DATA <= x"9C"; when x"189" => DATA <= x"A5"; when x"18A" => DATA <= x"69"; when x"18B" => DATA <= x"29"; when x"18C" => DATA <= x"53"; when x"18D" => DATA <= x"84"; when x"18E" => DATA <= x"13"; when x"18F" => DATA <= x"34"; when x"190" => DATA <= x"11"; when x"191" => DATA <= x"A5"; when x"192" => DATA <= x"69"; when x"193" => DATA <= x"23"; when x"194" => DATA <= x"A0"; when x"195" => DATA <= x"D8"; when x"196" => DATA <= x"62"; when x"197" => DATA <= x"5A"; when x"198" => DATA <= x"48"; when x"199" => DATA <= x"26"; when x"19A" => DATA <= x"62"; when x"19B" => DATA <= x"94"; when x"19C" => DATA <= x"88"; when x"19D" => DATA <= x"54"; when x"19E" => DATA <= x"44"; when x"19F" => DATA <= x"C8"; when x"1A0" => DATA <= x"54"; when x"1A1" => DATA <= x"68"; when x"1A2" => DATA <= x"44"; when x"1A3" => DATA <= x"E8"; when x"1A4" => DATA <= x"94"; when x"1A5" => DATA <= x"00"; when x"1A6" => DATA <= x"B4"; when x"1A7" => DATA <= x"08"; when x"1A8" => DATA <= x"84"; when x"1A9" => DATA <= x"74"; when x"1AA" => DATA <= x"B4"; when x"1AB" => DATA <= x"28"; when x"1AC" => DATA <= x"6E"; when x"1AD" => DATA <= x"74"; when x"1AE" => DATA <= x"F4"; when x"1AF" => DATA <= x"CC"; when x"1B0" => DATA <= x"4A"; when x"1B1" => DATA <= x"72"; when x"1B2" => DATA <= x"F2"; when x"1B3" => DATA <= x"A4"; when x"1B4" => DATA <= x"8A"; when x"1B5" => DATA <= x"00"; when x"1B6" => DATA <= x"AA"; when x"1B7" => DATA <= x"A2"; when x"1B8" => DATA <= x"A2"; when x"1B9" => DATA <= x"74"; when x"1BA" => DATA <= x"74"; when x"1BB" => DATA <= x"74"; when x"1BC" => DATA <= x"72"; when x"1BD" => DATA <= x"44"; when x"1BE" => DATA <= x"68"; when x"1BF" => DATA <= x"B2"; when x"1C0" => DATA <= x"32"; when x"1C1" => DATA <= x"B2"; when x"1C2" => DATA <= x"00"; when x"1C3" => DATA <= x"22"; when x"1C4" => DATA <= x"00"; when x"1C5" => DATA <= x"1A"; when x"1C6" => DATA <= x"1A"; when x"1C7" => DATA <= x"26"; when x"1C8" => DATA <= x"26"; when x"1C9" => DATA <= x"72"; when x"1CA" => DATA <= x"72"; when x"1CB" => DATA <= x"88"; when x"1CC" => DATA <= x"C8"; when x"1CD" => DATA <= x"C4"; when x"1CE" => DATA <= x"CA"; when x"1CF" => DATA <= x"26"; when x"1D0" => DATA <= x"48"; when x"1D1" => DATA <= x"44"; when x"1D2" => DATA <= x"44"; when x"1D3" => DATA <= x"A2"; when x"1D4" => DATA <= x"C8"; when x"1D5" => DATA <= x"00"; when x"1D6" => DATA <= x"02"; when x"1D7" => DATA <= x"00"; when x"1D8" => DATA <= x"08"; when x"1D9" => DATA <= x"F2"; when x"1DA" => DATA <= x"FF"; when x"1DB" => DATA <= x"80"; when x"1DC" => DATA <= x"01"; when x"1DD" => DATA <= x"C0"; when x"1DE" => DATA <= x"E2"; when x"1DF" => DATA <= x"C0"; when x"1E0" => DATA <= x"C0"; when x"1E1" => DATA <= x"FF"; when x"1E2" => DATA <= x"00"; when x"1E3" => DATA <= x"00"; when x"1E4" => DATA <= x"08"; when x"1E5" => DATA <= x"00"; when x"1E6" => DATA <= x"10"; when x"1E7" => DATA <= x"80"; when x"1E8" => DATA <= x"40"; when x"1E9" => DATA <= x"C0"; when x"1EA" => DATA <= x"00"; when x"1EB" => DATA <= x"C0"; when x"1EC" => DATA <= x"00"; when x"1ED" => DATA <= x"40"; when x"1EE" => DATA <= x"00"; when x"1EF" => DATA <= x"00"; when x"1F0" => DATA <= x"E4"; when x"1F1" => DATA <= x"20"; when x"1F2" => DATA <= x"80"; when x"1F3" => DATA <= x"00"; when x"1F4" => DATA <= x"FC"; when x"1F5" => DATA <= x"00"; when x"1F6" => DATA <= x"08"; when x"1F7" => DATA <= x"08"; when x"1F8" => DATA <= x"F8"; when x"1F9" => DATA <= x"FC"; when x"1FA" => DATA <= x"F4"; when x"1FB" => DATA <= x"0C"; when x"1FC" => DATA <= x"10"; when x"1FD" => DATA <= x"04"; when x"1FE" => DATA <= x"F4"; when x"1FF" => DATA <= x"00"; when x"200" => DATA <= x"20"; when x"201" => DATA <= x"10"; when x"202" => DATA <= x"00"; when x"203" => DATA <= x"00"; when x"204" => DATA <= x"0F"; when x"205" => DATA <= x"01"; when x"206" => DATA <= x"01"; when x"207" => DATA <= x"01"; when x"208" => DATA <= x"11"; when x"209" => DATA <= x"11"; when x"20A" => DATA <= x"02"; when x"20B" => DATA <= x"02"; when x"20C" => DATA <= x"11"; when x"20D" => DATA <= x"11"; when x"20E" => DATA <= x"02"; when x"20F" => DATA <= x"12"; when x"210" => DATA <= x"02"; when x"211" => DATA <= x"00"; when x"212" => DATA <= x"08"; when x"213" => DATA <= x"10"; when x"214" => DATA <= x"18"; when x"215" => DATA <= x"20"; when x"216" => DATA <= x"28"; when x"217" => DATA <= x"30"; when x"218" => DATA <= x"38"; when x"219" => DATA <= x"40"; when x"21A" => DATA <= x"48"; when x"21B" => DATA <= x"50"; when x"21C" => DATA <= x"58"; when x"21D" => DATA <= x"60"; when x"21E" => DATA <= x"68"; when x"21F" => DATA <= x"70"; when x"220" => DATA <= x"78"; when x"221" => DATA <= x"80"; when x"222" => DATA <= x"88"; when x"223" => DATA <= x"90"; when x"224" => DATA <= x"98"; when x"225" => DATA <= x"A0"; when x"226" => DATA <= x"A8"; when x"227" => DATA <= x"B0"; when x"228" => DATA <= x"B8"; when x"229" => DATA <= x"C0"; when x"22A" => DATA <= x"C8"; when x"22B" => DATA <= x"D0"; when x"22C" => DATA <= x"D8"; when x"22D" => DATA <= x"E0"; when x"22E" => DATA <= x"E8"; when x"22F" => DATA <= x"F0"; when x"230" => DATA <= x"F8"; when x"231" => DATA <= x"0C"; when x"232" => DATA <= x"2C"; when x"233" => DATA <= x"4C"; when x"234" => DATA <= x"4C"; when x"235" => DATA <= x"8C"; when x"236" => DATA <= x"AC"; when x"237" => DATA <= x"CC"; when x"238" => DATA <= x"EC"; when x"239" => DATA <= x"8A"; when x"23A" => DATA <= x"9A"; when x"23B" => DATA <= x"AA"; when x"23C" => DATA <= x"BA"; when x"23D" => DATA <= x"CA"; when x"23E" => DATA <= x"DA"; when x"23F" => DATA <= x"EA"; when x"240" => DATA <= x"FA"; when x"241" => DATA <= x"0E"; when x"242" => DATA <= x"2E"; when x"243" => DATA <= x"4E"; when x"244" => DATA <= x"6E"; when x"245" => DATA <= x"8E"; when x"246" => DATA <= x"AE"; when x"247" => DATA <= x"CE"; when x"248" => DATA <= x"EE"; when x"249" => DATA <= x"0D"; when x"24A" => DATA <= x"2D"; when x"24B" => DATA <= x"4D"; when x"24C" => DATA <= x"6D"; when x"24D" => DATA <= x"8D"; when x"24E" => DATA <= x"AD"; when x"24F" => DATA <= x"CD"; when x"250" => DATA <= x"ED"; when x"251" => DATA <= x"0D"; when x"252" => DATA <= x"0D"; when x"253" => DATA <= x"0C"; when x"254" => DATA <= x"0D"; when x"255" => DATA <= x"0E"; when x"256" => DATA <= x"0D"; when x"257" => DATA <= x"0C"; when x"258" => DATA <= x"0D"; when x"259" => DATA <= x"0D"; when x"25A" => DATA <= x"0D"; when x"25B" => DATA <= x"0C"; when x"25C" => DATA <= x"0D"; when x"25D" => DATA <= x"0D"; when x"25E" => DATA <= x"0D"; when x"25F" => DATA <= x"0C"; when x"260" => DATA <= x"0D"; when x"261" => DATA <= x"0F"; when x"262" => DATA <= x"0D"; when x"263" => DATA <= x"0C"; when x"264" => DATA <= x"0D"; when x"265" => DATA <= x"09"; when x"266" => DATA <= x"0D"; when x"267" => DATA <= x"0C"; when x"268" => DATA <= x"0D"; when x"269" => DATA <= x"08"; when x"26A" => DATA <= x"0D"; when x"26B" => DATA <= x"0C"; when x"26C" => DATA <= x"0D"; when x"26D" => DATA <= x"08"; when x"26E" => DATA <= x"0D"; when x"26F" => DATA <= x"0C"; when x"270" => DATA <= x"0D"; when x"271" => DATA <= x"0F"; when x"272" => DATA <= x"06"; when x"273" => DATA <= x"0B"; when x"274" => DATA <= x"0B"; when x"275" => DATA <= x"04"; when x"276" => DATA <= x"0A"; when x"277" => DATA <= x"08"; when x"278" => DATA <= x"08"; when x"279" => DATA <= x"0D"; when x"27A" => DATA <= x"0D"; when x"27B" => DATA <= x"0D"; when x"27C" => DATA <= x"0D"; when x"27D" => DATA <= x"0D"; when x"27E" => DATA <= x"0F"; when x"27F" => DATA <= x"0D"; when x"280" => DATA <= x"0F"; when x"281" => DATA <= x"07"; when x"282" => DATA <= x"07"; when x"283" => DATA <= x"07"; when x"284" => DATA <= x"07"; when x"285" => DATA <= x"05"; when x"286" => DATA <= x"09"; when x"287" => DATA <= x"03"; when x"288" => DATA <= x"03"; when x"289" => DATA <= x"01"; when x"28A" => DATA <= x"01"; when x"28B" => DATA <= x"01"; when x"28C" => DATA <= x"01"; when x"28D" => DATA <= x"02"; when x"28E" => DATA <= x"01"; when x"28F" => DATA <= x"01"; when x"290" => DATA <= x"01"; when x"291" => DATA <= x"A4"; when x"292" => DATA <= x"03"; when x"293" => DATA <= x"B1"; when x"294" => DATA <= x"05"; when x"295" => DATA <= x"E6"; when x"296" => DATA <= x"03"; when x"297" => DATA <= x"C9"; when x"298" => DATA <= x"20"; when x"299" => DATA <= x"F0"; when x"29A" => DATA <= x"F6"; when x"29B" => DATA <= x"60"; when x"29C" => DATA <= x"E6"; when x"29D" => DATA <= x"03"; when x"29E" => DATA <= x"4C"; when x"29F" => DATA <= x"1B"; when x"2A0" => DATA <= x"C3"; when x"2A1" => DATA <= x"B1"; when x"2A2" => DATA <= x"05"; when x"2A3" => DATA <= x"C9"; when x"2A4" => DATA <= x"5D"; when x"2A5" => DATA <= x"F0"; when x"2A6" => DATA <= x"F5"; when x"2A7" => DATA <= x"20"; when x"2A8" => DATA <= x"F6"; when x"2A9" => DATA <= x"C4"; when x"2AA" => DATA <= x"C6"; when x"2AB" => DATA <= x"03"; when x"2AC" => DATA <= x"20"; when x"2AD" => DATA <= x"8E"; when x"2AE" => DATA <= x"F3"; when x"2AF" => DATA <= x"C6"; when x"2B0" => DATA <= x"03"; when x"2B1" => DATA <= x"A5"; when x"2B2" => DATA <= x"52"; when x"2B3" => DATA <= x"48"; when x"2B4" => DATA <= x"A5"; when x"2B5" => DATA <= x"53"; when x"2B6" => DATA <= x"48"; when x"2B7" => DATA <= x"AD"; when x"2B8" => DATA <= x"21"; when x"2B9" => DATA <= x"03"; when x"2BA" => DATA <= x"48"; when x"2BB" => DATA <= x"A9"; when x"2BC" => DATA <= x"00"; when x"2BD" => DATA <= x"85"; when x"2BE" => DATA <= x"34"; when x"2BF" => DATA <= x"85"; when x"2C0" => DATA <= x"43"; when x"2C1" => DATA <= x"A9"; when x"2C2" => DATA <= x"05"; when x"2C3" => DATA <= x"8D"; when x"2C4" => DATA <= x"21"; when x"2C5" => DATA <= x"03"; when x"2C6" => DATA <= x"A5"; when x"2C7" => DATA <= x"01"; when x"2C8" => DATA <= x"85"; when x"2C9" => DATA <= x"16"; when x"2CA" => DATA <= x"A5"; when x"2CB" => DATA <= x"02"; when x"2CC" => DATA <= x"85"; when x"2CD" => DATA <= x"25"; when x"2CE" => DATA <= x"20"; when x"2CF" => DATA <= x"89"; when x"2D0" => DATA <= x"C5"; when x"2D1" => DATA <= x"20"; when x"2D2" => DATA <= x"79"; when x"2D3" => DATA <= x"F3"; when x"2D4" => DATA <= x"68"; when x"2D5" => DATA <= x"8D"; when x"2D6" => DATA <= x"21"; when x"2D7" => DATA <= x"03"; when x"2D8" => DATA <= x"68"; when x"2D9" => DATA <= x"20"; when x"2DA" => DATA <= x"7E"; when x"2DB" => DATA <= x"F3"; when x"2DC" => DATA <= x"68"; when x"2DD" => DATA <= x"20"; when x"2DE" => DATA <= x"76"; when x"2DF" => DATA <= x"F3"; when x"2E0" => DATA <= x"A0"; when x"2E1" => DATA <= x"00"; when x"2E2" => DATA <= x"C4"; when x"2E3" => DATA <= x"00"; when x"2E4" => DATA <= x"F0"; when x"2E5" => DATA <= x"09"; when x"2E6" => DATA <= x"B9"; when x"2E7" => DATA <= x"66"; when x"2E8" => DATA <= x"00"; when x"2E9" => DATA <= x"20"; when x"2EA" => DATA <= x"76"; when x"2EB" => DATA <= x"F3"; when x"2EC" => DATA <= x"C8"; when x"2ED" => DATA <= x"D0"; when x"2EE" => DATA <= x"F3"; when x"2EF" => DATA <= x"C0"; when x"2F0" => DATA <= x"03"; when x"2F1" => DATA <= x"F0"; when x"2F2" => DATA <= x"0C"; when x"2F3" => DATA <= x"20"; when x"2F4" => DATA <= x"79"; when x"2F5" => DATA <= x"F3"; when x"2F6" => DATA <= x"20"; when x"2F7" => DATA <= x"4C"; when x"2F8" => DATA <= x"CA"; when x"2F9" => DATA <= x"20"; when x"2FA" => DATA <= x"4C"; when x"2FB" => DATA <= x"CA"; when x"2FC" => DATA <= x"C8"; when x"2FD" => DATA <= x"D0"; when x"2FE" => DATA <= x"F0"; when x"2FF" => DATA <= x"A0"; when x"300" => DATA <= x"00"; when x"301" => DATA <= x"B1"; when x"302" => DATA <= x"05"; when x"303" => DATA <= x"C9"; when x"304" => DATA <= x"3B"; when x"305" => DATA <= x"F0"; when x"306" => DATA <= x"0A"; when x"307" => DATA <= x"C9"; when x"308" => DATA <= x"0D"; when x"309" => DATA <= x"F0"; when x"30A" => DATA <= x"06"; when x"30B" => DATA <= x"20"; when x"30C" => DATA <= x"4C"; when x"30D" => DATA <= x"CA"; when x"30E" => DATA <= x"C8"; when x"30F" => DATA <= x"D0"; when x"310" => DATA <= x"F0"; when x"311" => DATA <= x"20"; when x"312" => DATA <= x"54"; when x"313" => DATA <= x"CD"; when x"314" => DATA <= x"20"; when x"315" => DATA <= x"E4"; when x"316" => DATA <= x"C4"; when x"317" => DATA <= x"88"; when x"318" => DATA <= x"B1"; when x"319" => DATA <= x"05"; when x"31A" => DATA <= x"C8"; when x"31B" => DATA <= x"C9"; when x"31C" => DATA <= x"3B"; when x"31D" => DATA <= x"F0"; when x"31E" => DATA <= x"0C"; when x"31F" => DATA <= x"A5"; when x"320" => DATA <= x"06"; when x"321" => DATA <= x"C9"; when x"322" => DATA <= x"01"; when x"323" => DATA <= x"D0"; when x"324" => DATA <= x"03"; when x"325" => DATA <= x"4C"; when x"326" => DATA <= x"CF"; when x"327" => DATA <= x"C2"; when x"328" => DATA <= x"20"; when x"329" => DATA <= x"1D"; when x"32A" => DATA <= x"C5"; when x"32B" => DATA <= x"4C"; when x"32C" => DATA <= x"A1"; when x"32D" => DATA <= x"F2"; when x"32E" => DATA <= x"20"; when x"32F" => DATA <= x"91"; when x"330" => DATA <= x"F2"; when x"331" => DATA <= x"85"; when x"332" => DATA <= x"66"; when x"333" => DATA <= x"20"; when x"334" => DATA <= x"91"; when x"335" => DATA <= x"F2"; when x"336" => DATA <= x"C5"; when x"337" => DATA <= x"66"; when x"338" => DATA <= x"D0"; when x"339" => DATA <= x"10"; when x"33A" => DATA <= x"C9"; when x"33B" => DATA <= x"40"; when x"33C" => DATA <= x"90"; when x"33D" => DATA <= x"0C"; when x"33E" => DATA <= x"C9"; when x"33F" => DATA <= x"5B"; when x"340" => DATA <= x"B0"; when x"341" => DATA <= x"08"; when x"342" => DATA <= x"38"; when x"343" => DATA <= x"20"; when x"344" => DATA <= x"8E"; when x"345" => DATA <= x"F0"; when x"346" => DATA <= x"20"; when x"347" => DATA <= x"CB"; when x"348" => DATA <= x"C3"; when x"349" => DATA <= x"A0"; when x"34A" => DATA <= x"00"; when x"34B" => DATA <= x"AD"; when x"34C" => DATA <= x"31"; when x"34D" => DATA <= x"03"; when x"34E" => DATA <= x"91"; when x"34F" => DATA <= x"52"; when x"350" => DATA <= x"AD"; when x"351" => DATA <= x"4C"; when x"352" => DATA <= x"03"; when x"353" => DATA <= x"C8"; when x"354" => DATA <= x"91"; when x"355" => DATA <= x"52"; when x"356" => DATA <= x"A9"; when x"357" => DATA <= x"00"; when x"358" => DATA <= x"C8"; when x"359" => DATA <= x"91"; when x"35A" => DATA <= x"52"; when x"35B" => DATA <= x"C8"; when x"35C" => DATA <= x"91"; when x"35D" => DATA <= x"52"; when x"35E" => DATA <= x"D0"; when x"35F" => DATA <= x"36"; when x"360" => DATA <= x"20"; when x"361" => DATA <= x"91"; when x"362" => DATA <= x"F2"; when x"363" => DATA <= x"C9"; when x"364" => DATA <= x"3B"; when x"365" => DATA <= x"F0"; when x"366" => DATA <= x"04"; when x"367" => DATA <= x"C9"; when x"368" => DATA <= x"0D"; when x"369" => DATA <= x"D0"; when x"36A" => DATA <= x"F5"; when x"36B" => DATA <= x"AD"; when x"36C" => DATA <= x"31"; when x"36D" => DATA <= x"03"; when x"36E" => DATA <= x"85"; when x"36F" => DATA <= x"52"; when x"370" => DATA <= x"AD"; when x"371" => DATA <= x"4C"; when x"372" => DATA <= x"03"; when x"373" => DATA <= x"85"; when x"374" => DATA <= x"53"; when x"375" => DATA <= x"60"; when x"376" => DATA <= x"20"; when x"377" => DATA <= x"7E"; when x"378" => DATA <= x"F3"; when x"379" => DATA <= x"A9"; when x"37A" => DATA <= x"20"; when x"37B" => DATA <= x"4C"; when x"37C" => DATA <= x"4C"; when x"37D" => DATA <= x"CA"; when x"37E" => DATA <= x"A2"; when x"37F" => DATA <= x"FF"; when x"380" => DATA <= x"48"; when x"381" => DATA <= x"4A"; when x"382" => DATA <= x"4A"; when x"383" => DATA <= x"4A"; when x"384" => DATA <= x"4A"; when x"385" => DATA <= x"20"; when x"386" => DATA <= x"F9"; when x"387" => DATA <= x"C5"; when x"388" => DATA <= x"68"; when x"389" => DATA <= x"29"; when x"38A" => DATA <= x"0F"; when x"38B" => DATA <= x"4C"; when x"38C" => DATA <= x"F9"; when x"38D" => DATA <= x"C5"; when x"38E" => DATA <= x"A2"; when x"38F" => DATA <= x"00"; when x"390" => DATA <= x"86"; when x"391" => DATA <= x"00"; when x"392" => DATA <= x"86"; when x"393" => DATA <= x"64"; when x"394" => DATA <= x"86"; when x"395" => DATA <= x"65"; when x"396" => DATA <= x"20"; when x"397" => DATA <= x"91"; when x"398" => DATA <= x"F2"; when x"399" => DATA <= x"C9"; when x"39A" => DATA <= x"3A"; when x"39B" => DATA <= x"F0"; when x"39C" => DATA <= x"91"; when x"39D" => DATA <= x"C9"; when x"39E" => DATA <= x"3B"; when x"39F" => DATA <= x"F0"; when x"3A0" => DATA <= x"CA"; when x"3A1" => DATA <= x"C9"; when x"3A2" => DATA <= x"0D"; when x"3A3" => DATA <= x"F0"; when x"3A4" => DATA <= x"C6"; when x"3A5" => DATA <= x"C9"; when x"3A6" => DATA <= x"5C"; when x"3A7" => DATA <= x"F0"; when x"3A8" => DATA <= x"B7"; when x"3A9" => DATA <= x"A0"; when x"3AA" => DATA <= x"05"; when x"3AB" => DATA <= x"38"; when x"3AC" => DATA <= x"69"; when x"3AD" => DATA <= x"00"; when x"3AE" => DATA <= x"0A"; when x"3AF" => DATA <= x"0A"; when x"3B0" => DATA <= x"0A"; when x"3B1" => DATA <= x"0A"; when x"3B2" => DATA <= x"26"; when x"3B3" => DATA <= x"6A"; when x"3B4" => DATA <= x"26"; when x"3B5" => DATA <= x"69"; when x"3B6" => DATA <= x"88"; when x"3B7" => DATA <= x"D0"; when x"3B8" => DATA <= x"F8"; when x"3B9" => DATA <= x"E8"; when x"3BA" => DATA <= x"E0"; when x"3BB" => DATA <= x"03"; when x"3BC" => DATA <= x"D0"; when x"3BD" => DATA <= x"D8"; when x"3BE" => DATA <= x"06"; when x"3BF" => DATA <= x"6A"; when x"3C0" => DATA <= x"26"; when x"3C1" => DATA <= x"69"; when x"3C2" => DATA <= x"A2"; when x"3C3" => DATA <= x"40"; when x"3C4" => DATA <= x"A5"; when x"3C5" => DATA <= x"69"; when x"3C6" => DATA <= x"DD"; when x"3C7" => DATA <= x"54"; when x"3C8" => DATA <= x"F1"; when x"3C9" => DATA <= x"F0"; when x"3CA" => DATA <= x"04"; when x"3CB" => DATA <= x"CA"; when x"3CC" => DATA <= x"D0"; when x"3CD" => DATA <= x"F8"; when x"3CE" => DATA <= x"00"; when x"3CF" => DATA <= x"BC"; when x"3D0" => DATA <= x"94"; when x"3D1" => DATA <= x"F1"; when x"3D2" => DATA <= x"C4"; when x"3D3" => DATA <= x"6A"; when x"3D4" => DATA <= x"D0"; when x"3D5" => DATA <= x"F5"; when x"3D6" => DATA <= x"BD"; when x"3D7" => DATA <= x"10"; when x"3D8" => DATA <= x"F2"; when x"3D9" => DATA <= x"85"; when x"3DA" => DATA <= x"66"; when x"3DB" => DATA <= x"BC"; when x"3DC" => DATA <= x"50"; when x"3DD" => DATA <= x"F2"; when x"3DE" => DATA <= x"84"; when x"3DF" => DATA <= x"0F"; when x"3E0" => DATA <= x"66"; when x"3E1" => DATA <= x"64"; when x"3E2" => DATA <= x"66"; when x"3E3" => DATA <= x"65"; when x"3E4" => DATA <= x"88"; when x"3E5" => DATA <= x"D0"; when x"3E6" => DATA <= x"F9"; when x"3E7" => DATA <= x"A4"; when x"3E8" => DATA <= x"0F"; when x"3E9" => DATA <= x"C0"; when x"3EA" => DATA <= x"0D"; when x"3EB" => DATA <= x"D0"; when x"3EC" => DATA <= x"05"; when x"3ED" => DATA <= x"A2"; when x"3EE" => DATA <= x"00"; when x"3EF" => DATA <= x"4C"; when x"3F0" => DATA <= x"9B"; when x"3F1" => DATA <= x"F4"; when x"3F2" => DATA <= x"20"; when x"3F3" => DATA <= x"91"; when x"3F4" => DATA <= x"F2"; when x"3F5" => DATA <= x"C9"; when x"3F6" => DATA <= x"40"; when x"3F7" => DATA <= x"F0"; when x"3F8" => DATA <= x"5B"; when x"3F9" => DATA <= x"C9"; when x"3FA" => DATA <= x"28"; when x"3FB" => DATA <= x"F0"; when x"3FC" => DATA <= x"65"; when x"3FD" => DATA <= x"A2"; when x"3FE" => DATA <= x"01"; when x"3FF" => DATA <= x"C9"; when x"400" => DATA <= x"41"; when x"401" => DATA <= x"F0"; when x"402" => DATA <= x"EC"; when x"403" => DATA <= x"C6"; when x"404" => DATA <= x"03"; when x"405" => DATA <= x"20"; when x"406" => DATA <= x"8B"; when x"407" => DATA <= x"C7"; when x"408" => DATA <= x"20"; when x"409" => DATA <= x"91"; when x"40A" => DATA <= x"F2"; when x"40B" => DATA <= x"C9"; when x"40C" => DATA <= x"2C"; when x"40D" => DATA <= x"D0"; when x"40E" => DATA <= x"31"; when x"40F" => DATA <= x"20"; when x"410" => DATA <= x"91"; when x"411" => DATA <= x"F2"; when x"412" => DATA <= x"A4"; when x"413" => DATA <= x"25"; when x"414" => DATA <= x"F0"; when x"415" => DATA <= x"15"; when x"416" => DATA <= x"A2"; when x"417" => DATA <= x"09"; when x"418" => DATA <= x"C9"; when x"419" => DATA <= x"58"; when x"41A" => DATA <= x"F0"; when x"41B" => DATA <= x"7F"; when x"41C" => DATA <= x"CA"; when x"41D" => DATA <= x"C9"; when x"41E" => DATA <= x"59"; when x"41F" => DATA <= x"D0"; when x"420" => DATA <= x"79"; when x"421" => DATA <= x"A5"; when x"422" => DATA <= x"0F"; when x"423" => DATA <= x"C9"; when x"424" => DATA <= x"09"; when x"425" => DATA <= x"D0"; when x"426" => DATA <= x"74"; when x"427" => DATA <= x"A2"; when x"428" => DATA <= x"0E"; when x"429" => DATA <= x"D0"; when x"42A" => DATA <= x"70"; when x"42B" => DATA <= x"A2"; when x"42C" => DATA <= x"04"; when x"42D" => DATA <= x"C9"; when x"42E" => DATA <= x"58"; when x"42F" => DATA <= x"F0"; when x"430" => DATA <= x"6A"; when x"431" => DATA <= x"C9"; when x"432" => DATA <= x"59"; when x"433" => DATA <= x"D0"; when x"434" => DATA <= x"65"; when x"435" => DATA <= x"CA"; when x"436" => DATA <= x"A4"; when x"437" => DATA <= x"0F"; when x"438" => DATA <= x"C0"; when x"439" => DATA <= x"03"; when x"43A" => DATA <= x"B0"; when x"43B" => DATA <= x"5F"; when x"43C" => DATA <= x"A2"; when x"43D" => DATA <= x"08"; when x"43E" => DATA <= x"D0"; when x"43F" => DATA <= x"5B"; when x"440" => DATA <= x"C6"; when x"441" => DATA <= x"03"; when x"442" => DATA <= x"A2"; when x"443" => DATA <= x"02"; when x"444" => DATA <= x"A4"; when x"445" => DATA <= x"0F"; when x"446" => DATA <= x"C0"; when x"447" => DATA <= x"0C"; when x"448" => DATA <= x"F0"; when x"449" => DATA <= x"51"; when x"44A" => DATA <= x"A2"; when x"44B" => DATA <= x"05"; when x"44C" => DATA <= x"A5"; when x"44D" => DATA <= x"25"; when x"44E" => DATA <= x"F0"; when x"44F" => DATA <= x"4B"; when x"450" => DATA <= x"A2"; when x"451" => DATA <= x"0C"; when x"452" => DATA <= x"D0"; when x"453" => DATA <= x"47"; when x"454" => DATA <= x"20"; when x"455" => DATA <= x"8B"; when x"456" => DATA <= x"C7"; when x"457" => DATA <= x"A5"; when x"458" => DATA <= x"0F"; when x"459" => DATA <= x"A2"; when x"45A" => DATA <= x"06"; when x"45B" => DATA <= x"C9"; when x"45C" => DATA <= x"01"; when x"45D" => DATA <= x"F0"; when x"45E" => DATA <= x"3C"; when x"45F" => DATA <= x"E8"; when x"460" => DATA <= x"D0"; when x"461" => DATA <= x"39"; when x"462" => DATA <= x"20"; when x"463" => DATA <= x"8B"; when x"464" => DATA <= x"C7"; when x"465" => DATA <= x"20"; when x"466" => DATA <= x"91"; when x"467" => DATA <= x"F2"; when x"468" => DATA <= x"C9"; when x"469" => DATA <= x"29"; when x"46A" => DATA <= x"F0"; when x"46B" => DATA <= x"16"; when x"46C" => DATA <= x"C9"; when x"46D" => DATA <= x"2C"; when x"46E" => DATA <= x"D0"; when x"46F" => DATA <= x"2A"; when x"470" => DATA <= x"20"; when x"471" => DATA <= x"91"; when x"472" => DATA <= x"F2"; when x"473" => DATA <= x"C9"; when x"474" => DATA <= x"58"; when x"475" => DATA <= x"D0"; when x"476" => DATA <= x"23"; when x"477" => DATA <= x"20"; when x"478" => DATA <= x"91"; when x"479" => DATA <= x"F2"; when x"47A" => DATA <= x"C9"; when x"47B" => DATA <= x"29"; when x"47C" => DATA <= x"D0"; when x"47D" => DATA <= x"1C"; when x"47E" => DATA <= x"A2"; when x"47F" => DATA <= x"0B"; when x"480" => DATA <= x"D0"; when x"481" => DATA <= x"19"; when x"482" => DATA <= x"A2"; when x"483" => DATA <= x"0D"; when x"484" => DATA <= x"A5"; when x"485" => DATA <= x"0F"; when x"486" => DATA <= x"C9"; when x"487" => DATA <= x"0B"; when x"488" => DATA <= x"F0"; when x"489" => DATA <= x"11"; when x"48A" => DATA <= x"A2"; when x"48B" => DATA <= x"0A"; when x"48C" => DATA <= x"20"; when x"48D" => DATA <= x"91"; when x"48E" => DATA <= x"F2"; when x"48F" => DATA <= x"C9"; when x"490" => DATA <= x"2C"; when x"491" => DATA <= x"D0"; when x"492" => DATA <= x"07"; when x"493" => DATA <= x"20"; when x"494" => DATA <= x"91"; when x"495" => DATA <= x"F2"; when x"496" => DATA <= x"C9"; when x"497" => DATA <= x"59"; when x"498" => DATA <= x"F0"; when x"499" => DATA <= x"01"; when x"49A" => DATA <= x"00"; when x"49B" => DATA <= x"20"; when x"49C" => DATA <= x"60"; when x"49D" => DATA <= x"F3"; when x"49E" => DATA <= x"BD"; when x"49F" => DATA <= x"D5"; when x"4A0" => DATA <= x"F1"; when x"4A1" => DATA <= x"F0"; when x"4A2" => DATA <= x"04"; when x"4A3" => DATA <= x"25"; when x"4A4" => DATA <= x"64"; when x"4A5" => DATA <= x"D0"; when x"4A6" => DATA <= x"07"; when x"4A7" => DATA <= x"BD"; when x"4A8" => DATA <= x"E4"; when x"4A9" => DATA <= x"F1"; when x"4AA" => DATA <= x"25"; when x"4AB" => DATA <= x"65"; when x"4AC" => DATA <= x"F0"; when x"4AD" => DATA <= x"EC"; when x"4AE" => DATA <= x"18"; when x"4AF" => DATA <= x"BD"; when x"4B0" => DATA <= x"F3"; when x"4B1" => DATA <= x"F1"; when x"4B2" => DATA <= x"65"; when x"4B3" => DATA <= x"66"; when x"4B4" => DATA <= x"85"; when x"4B5" => DATA <= x"66"; when x"4B6" => DATA <= x"BD"; when x"4B7" => DATA <= x"02"; when x"4B8" => DATA <= x"F2"; when x"4B9" => DATA <= x"A2"; when x"4BA" => DATA <= x"00"; when x"4BB" => DATA <= x"86"; when x"4BC" => DATA <= x"04"; when x"4BD" => DATA <= x"A4"; when x"4BE" => DATA <= x"16"; when x"4BF" => DATA <= x"84"; when x"4C0" => DATA <= x"67"; when x"4C1" => DATA <= x"A4"; when x"4C2" => DATA <= x"25"; when x"4C3" => DATA <= x"84"; when x"4C4" => DATA <= x"68"; when x"4C5" => DATA <= x"C9"; when x"4C6" => DATA <= x"0F"; when x"4C7" => DATA <= x"F0"; when x"4C8" => DATA <= x"23"; when x"4C9" => DATA <= x"29"; when x"4CA" => DATA <= x"0F"; when x"4CB" => DATA <= x"A8"; when x"4CC" => DATA <= x"C8"; when x"4CD" => DATA <= x"84"; when x"4CE" => DATA <= x"00"; when x"4CF" => DATA <= x"C0"; when x"4D0" => DATA <= x"02"; when x"4D1" => DATA <= x"D0"; when x"4D2" => DATA <= x"04"; when x"4D3" => DATA <= x"A4"; when x"4D4" => DATA <= x"68"; when x"4D5" => DATA <= x"D0"; when x"4D6" => DATA <= x"C3"; when x"4D7" => DATA <= x"A0"; when x"4D8" => DATA <= x"00"; when x"4D9" => DATA <= x"B9"; when x"4DA" => DATA <= x"66"; when x"4DB" => DATA <= x"00"; when x"4DC" => DATA <= x"91"; when x"4DD" => DATA <= x"52"; when x"4DE" => DATA <= x"C8"; when x"4DF" => DATA <= x"EE"; when x"4E0" => DATA <= x"31"; when x"4E1" => DATA <= x"03"; when x"4E2" => DATA <= x"D0"; when x"4E3" => DATA <= x"03"; when x"4E4" => DATA <= x"EE"; when x"4E5" => DATA <= x"4C"; when x"4E6" => DATA <= x"03"; when x"4E7" => DATA <= x"C4"; when x"4E8" => DATA <= x"00"; when x"4E9" => DATA <= x"D0"; when x"4EA" => DATA <= x"EE"; when x"4EB" => DATA <= x"60"; when x"4EC" => DATA <= x"A9"; when x"4ED" => DATA <= x"02"; when x"4EE" => DATA <= x"85"; when x"4EF" => DATA <= x"00"; when x"4F0" => DATA <= x"38"; when x"4F1" => DATA <= x"A5"; when x"4F2" => DATA <= x"67"; when x"4F3" => DATA <= x"ED"; when x"4F4" => DATA <= x"31"; when x"4F5" => DATA <= x"03"; when x"4F6" => DATA <= x"85"; when x"4F7" => DATA <= x"67"; when x"4F8" => DATA <= x"A5"; when x"4F9" => DATA <= x"68"; when x"4FA" => DATA <= x"ED"; when x"4FB" => DATA <= x"4C"; when x"4FC" => DATA <= x"03"; when x"4FD" => DATA <= x"85"; when x"4FE" => DATA <= x"68"; when x"4FF" => DATA <= x"38"; when x"500" => DATA <= x"A5"; when x"501" => DATA <= x"67"; when x"502" => DATA <= x"E9"; when x"503" => DATA <= x"02"; when x"504" => DATA <= x"85"; when x"505" => DATA <= x"67"; when x"506" => DATA <= x"A8"; when x"507" => DATA <= x"A5"; when x"508" => DATA <= x"68"; when x"509" => DATA <= x"E9"; when x"50A" => DATA <= x"00"; when x"50B" => DATA <= x"F0"; when x"50C" => DATA <= x"1F"; when x"50D" => DATA <= x"C9"; when x"50E" => DATA <= x"FF"; when x"50F" => DATA <= x"F0"; when x"510" => DATA <= x"16"; when x"511" => DATA <= x"20"; when x"512" => DATA <= x"D1"; when x"513" => DATA <= x"F7"; when x"514" => DATA <= x"4F"; when x"515" => DATA <= x"55"; when x"516" => DATA <= x"54"; when x"517" => DATA <= x"20"; when x"518" => DATA <= x"4F"; when x"519" => DATA <= x"46"; when x"51A" => DATA <= x"20"; when x"51B" => DATA <= x"52"; when x"51C" => DATA <= x"41"; when x"51D" => DATA <= x"4E"; when x"51E" => DATA <= x"47"; when x"51F" => DATA <= x"45"; when x"520" => DATA <= x"3A"; when x"521" => DATA <= x"0A"; when x"522" => DATA <= x"0D"; when x"523" => DATA <= x"84"; when x"524" => DATA <= x"67"; when x"525" => DATA <= x"30"; when x"526" => DATA <= x"B0"; when x"527" => DATA <= x"98"; when x"528" => DATA <= x"30"; when x"529" => DATA <= x"AD"; when x"52A" => DATA <= x"10"; when x"52B" => DATA <= x"E5"; when x"52C" => DATA <= x"98"; when x"52D" => DATA <= x"10"; when x"52E" => DATA <= x"A8"; when x"52F" => DATA <= x"30"; when x"530" => DATA <= x"E0"; when x"531" => DATA <= x"20"; when x"532" => DATA <= x"E4"; when x"533" => DATA <= x"C4"; when x"534" => DATA <= x"88"; when x"535" => DATA <= x"84"; when x"536" => DATA <= x"52"; when x"537" => DATA <= x"A5"; when x"538" => DATA <= x"12"; when x"539" => DATA <= x"85"; when x"53A" => DATA <= x"53"; when x"53B" => DATA <= x"98"; when x"53C" => DATA <= x"C8"; when x"53D" => DATA <= x"91"; when x"53E" => DATA <= x"52"; when x"53F" => DATA <= x"4C"; when x"540" => DATA <= x"9B"; when x"541" => DATA <= x"CD"; when x"542" => DATA <= x"A2"; when x"543" => DATA <= x"05"; when x"544" => DATA <= x"D0"; when x"545" => DATA <= x"02"; when x"546" => DATA <= x"A2"; when x"547" => DATA <= x"0C"; when x"548" => DATA <= x"86"; when x"549" => DATA <= x"16"; when x"54A" => DATA <= x"E6"; when x"54B" => DATA <= x"04"; when x"54C" => DATA <= x"D0"; when x"54D" => DATA <= x"06"; when x"54E" => DATA <= x"20"; when x"54F" => DATA <= x"BC"; when x"550" => DATA <= x"C8"; when x"551" => DATA <= x"20"; when x"552" => DATA <= x"31"; when x"553" => DATA <= x"C2"; when x"554" => DATA <= x"20"; when x"555" => DATA <= x"BC"; when x"556" => DATA <= x"C8"; when x"557" => DATA <= x"20"; when x"558" => DATA <= x"31"; when x"559" => DATA <= x"C2"; when x"55A" => DATA <= x"20"; when x"55B" => DATA <= x"BC"; when x"55C" => DATA <= x"C8"; when x"55D" => DATA <= x"20"; when x"55E" => DATA <= x"E4"; when x"55F" => DATA <= x"C4"; when x"560" => DATA <= x"B5"; when x"561" => DATA <= x"15"; when x"562" => DATA <= x"85"; when x"563" => DATA <= x"5C"; when x"564" => DATA <= x"B5"; when x"565" => DATA <= x"24"; when x"566" => DATA <= x"85"; when x"567" => DATA <= x"5D"; when x"568" => DATA <= x"B5"; when x"569" => DATA <= x"14"; when x"56A" => DATA <= x"85"; when x"56B" => DATA <= x"5A"; when x"56C" => DATA <= x"B5"; when x"56D" => DATA <= x"23"; when x"56E" => DATA <= x"85"; when x"56F" => DATA <= x"5B"; when x"570" => DATA <= x"A2"; when x"571" => DATA <= x"00"; when x"572" => DATA <= x"86"; when x"573" => DATA <= x"04"; when x"574" => DATA <= x"A2"; when x"575" => DATA <= x"03"; when x"576" => DATA <= x"BD"; when x"577" => DATA <= x"C1"; when x"578" => DATA <= x"03"; when x"579" => DATA <= x"95"; when x"57A" => DATA <= x"52"; when x"57B" => DATA <= x"CA"; when x"57C" => DATA <= x"10"; when x"57D" => DATA <= x"F8"; when x"57E" => DATA <= x"A5"; when x"57F" => DATA <= x"16"; when x"580" => DATA <= x"29"; when x"581" => DATA <= x"04"; when x"582" => DATA <= x"D0"; when x"583" => DATA <= x"13"; when x"584" => DATA <= x"A2"; when x"585" => DATA <= x"02"; when x"586" => DATA <= x"18"; when x"587" => DATA <= x"B5"; when x"588" => DATA <= x"5A"; when x"589" => DATA <= x"75"; when x"58A" => DATA <= x"52"; when x"58B" => DATA <= x"95"; when x"58C" => DATA <= x"5A"; when x"58D" => DATA <= x"B5"; when x"58E" => DATA <= x"5B"; when x"58F" => DATA <= x"75"; when x"590" => DATA <= x"53"; when x"591" => DATA <= x"95"; when x"592" => DATA <= x"5B"; when x"593" => DATA <= x"CA"; when x"594" => DATA <= x"CA"; when x"595" => DATA <= x"10"; when x"596" => DATA <= x"EF"; when x"597" => DATA <= x"A2"; when x"598" => DATA <= x"03"; when x"599" => DATA <= x"B5"; when x"59A" => DATA <= x"5A"; when x"59B" => DATA <= x"9D"; when x"59C" => DATA <= x"C1"; when x"59D" => DATA <= x"03"; when x"59E" => DATA <= x"CA"; when x"59F" => DATA <= x"10"; when x"5A0" => DATA <= x"F8"; when x"5A1" => DATA <= x"A5"; when x"5A2" => DATA <= x"16"; when x"5A3" => DATA <= x"29"; when x"5A4" => DATA <= x"03"; when x"5A5" => DATA <= x"F0"; when x"5A6" => DATA <= x"0B"; when x"5A7" => DATA <= x"85"; when x"5A8" => DATA <= x"5E"; when x"5A9" => DATA <= x"A5"; when x"5AA" => DATA <= x"16"; when x"5AB" => DATA <= x"29"; when x"5AC" => DATA <= x"08"; when x"5AD" => DATA <= x"F0"; when x"5AE" => DATA <= x"06"; when x"5AF" => DATA <= x"20"; when x"5B0" => DATA <= x"78"; when x"5B1" => DATA <= x"F6"; when x"5B2" => DATA <= x"4C"; when x"5B3" => DATA <= x"5B"; when x"5B4" => DATA <= x"C5"; when x"5B5" => DATA <= x"A2"; when x"5B6" => DATA <= x"02"; when x"5B7" => DATA <= x"38"; when x"5B8" => DATA <= x"B5"; when x"5B9" => DATA <= x"5A"; when x"5BA" => DATA <= x"F5"; when x"5BB" => DATA <= x"52"; when x"5BC" => DATA <= x"B4"; when x"5BD" => DATA <= x"52"; when x"5BE" => DATA <= x"94"; when x"5BF" => DATA <= x"5A"; when x"5C0" => DATA <= x"95"; when x"5C1" => DATA <= x"52"; when x"5C2" => DATA <= x"B4"; when x"5C3" => DATA <= x"53"; when x"5C4" => DATA <= x"B5"; when x"5C5" => DATA <= x"5B"; when x"5C6" => DATA <= x"F5"; when x"5C7" => DATA <= x"53"; when x"5C8" => DATA <= x"94"; when x"5C9" => DATA <= x"5B"; when x"5CA" => DATA <= x"95"; when x"5CB" => DATA <= x"53"; when x"5CC" => DATA <= x"95"; when x"5CD" => DATA <= x"56"; when x"5CE" => DATA <= x"10"; when x"5CF" => DATA <= x"0D"; when x"5D0" => DATA <= x"A9"; when x"5D1" => DATA <= x"00"; when x"5D2" => DATA <= x"38"; when x"5D3" => DATA <= x"F5"; when x"5D4" => DATA <= x"52"; when x"5D5" => DATA <= x"95"; when x"5D6" => DATA <= x"52"; when x"5D7" => DATA <= x"A9"; when x"5D8" => DATA <= x"00"; when x"5D9" => DATA <= x"F5"; when x"5DA" => DATA <= x"53"; when x"5DB" => DATA <= x"95"; when x"5DC" => DATA <= x"53"; when x"5DD" => DATA <= x"CA"; when x"5DE" => DATA <= x"CA"; when x"5DF" => DATA <= x"10"; when x"5E0" => DATA <= x"D6"; when x"5E1" => DATA <= x"A5"; when x"5E2" => DATA <= x"54"; when x"5E3" => DATA <= x"C5"; when x"5E4" => DATA <= x"52"; when x"5E5" => DATA <= x"A5"; when x"5E6" => DATA <= x"55"; when x"5E7" => DATA <= x"E5"; when x"5E8" => DATA <= x"53"; when x"5E9" => DATA <= x"90"; when x"5EA" => DATA <= x"31"; when x"5EB" => DATA <= x"A9"; when x"5EC" => DATA <= x"00"; when x"5ED" => DATA <= x"E5"; when x"5EE" => DATA <= x"54"; when x"5EF" => DATA <= x"85"; when x"5F0" => DATA <= x"57"; when x"5F1" => DATA <= x"A9"; when x"5F2" => DATA <= x"00"; when x"5F3" => DATA <= x"E5"; when x"5F4" => DATA <= x"55"; when x"5F5" => DATA <= x"38"; when x"5F6" => DATA <= x"6A"; when x"5F7" => DATA <= x"85"; when x"5F8" => DATA <= x"59"; when x"5F9" => DATA <= x"66"; when x"5FA" => DATA <= x"57"; when x"5FB" => DATA <= x"20"; when x"5FC" => DATA <= x"78"; when x"5FD" => DATA <= x"F6"; when x"5FE" => DATA <= x"A5"; when x"5FF" => DATA <= x"5C"; when x"600" => DATA <= x"CD"; when x"601" => DATA <= x"C3"; when x"602" => DATA <= x"03"; when x"603" => DATA <= x"D0"; when x"604" => DATA <= x"0A"; when x"605" => DATA <= x"A5"; when x"606" => DATA <= x"5D"; when x"607" => DATA <= x"CD"; when x"608" => DATA <= x"C4"; when x"609" => DATA <= x"03"; when x"60A" => DATA <= x"D0"; when x"60B" => DATA <= x"03"; when x"60C" => DATA <= x"4C"; when x"60D" => DATA <= x"5B"; when x"60E" => DATA <= x"C5"; when x"60F" => DATA <= x"20"; when x"610" => DATA <= x"55"; when x"611" => DATA <= x"F6"; when x"612" => DATA <= x"A5"; when x"613" => DATA <= x"59"; when x"614" => DATA <= x"30"; when x"615" => DATA <= x"E5"; when x"616" => DATA <= x"20"; when x"617" => DATA <= x"44"; when x"618" => DATA <= x"F6"; when x"619" => DATA <= x"4C"; when x"61A" => DATA <= x"FB"; when x"61B" => DATA <= x"F5"; when x"61C" => DATA <= x"A5"; when x"61D" => DATA <= x"53"; when x"61E" => DATA <= x"4A"; when x"61F" => DATA <= x"85"; when x"620" => DATA <= x"59"; when x"621" => DATA <= x"A5"; when x"622" => DATA <= x"52"; when x"623" => DATA <= x"6A"; when x"624" => DATA <= x"85"; when x"625" => DATA <= x"57"; when x"626" => DATA <= x"20"; when x"627" => DATA <= x"78"; when x"628" => DATA <= x"F6"; when x"629" => DATA <= x"A5"; when x"62A" => DATA <= x"5A"; when x"62B" => DATA <= x"CD"; when x"62C" => DATA <= x"C1"; when x"62D" => DATA <= x"03"; when x"62E" => DATA <= x"D0"; when x"62F" => DATA <= x"07"; when x"630" => DATA <= x"A5"; when x"631" => DATA <= x"5B"; when x"632" => DATA <= x"CD"; when x"633" => DATA <= x"C2"; when x"634" => DATA <= x"03"; when x"635" => DATA <= x"F0"; when x"636" => DATA <= x"D5"; when x"637" => DATA <= x"20"; when x"638" => DATA <= x"44"; when x"639" => DATA <= x"F6"; when x"63A" => DATA <= x"A5"; when x"63B" => DATA <= x"59"; when x"63C" => DATA <= x"10"; when x"63D" => DATA <= x"E8"; when x"63E" => DATA <= x"20"; when x"63F" => DATA <= x"55"; when x"640" => DATA <= x"F6"; when x"641" => DATA <= x"4C"; when x"642" => DATA <= x"26"; when x"643" => DATA <= x"F6"; when x"644" => DATA <= x"38"; when x"645" => DATA <= x"A5"; when x"646" => DATA <= x"57"; when x"647" => DATA <= x"E5"; when x"648" => DATA <= x"54"; when x"649" => DATA <= x"85"; when x"64A" => DATA <= x"57"; when x"64B" => DATA <= x"A5"; when x"64C" => DATA <= x"59"; when x"64D" => DATA <= x"E5"; when x"64E" => DATA <= x"55"; when x"64F" => DATA <= x"85"; when x"650" => DATA <= x"59"; when x"651" => DATA <= x"A2"; when x"652" => DATA <= x"00"; when x"653" => DATA <= x"F0"; when x"654" => DATA <= x"0F"; when x"655" => DATA <= x"18"; when x"656" => DATA <= x"A5"; when x"657" => DATA <= x"57"; when x"658" => DATA <= x"65"; when x"659" => DATA <= x"52"; when x"65A" => DATA <= x"85"; when x"65B" => DATA <= x"57"; when x"65C" => DATA <= x"A5"; when x"65D" => DATA <= x"59"; when x"65E" => DATA <= x"65"; when x"65F" => DATA <= x"53"; when x"660" => DATA <= x"85"; when x"661" => DATA <= x"59"; when x"662" => DATA <= x"A2"; when x"663" => DATA <= x"02"; when x"664" => DATA <= x"B5"; when x"665" => DATA <= x"56"; when x"666" => DATA <= x"10"; when x"667" => DATA <= x"09"; when x"668" => DATA <= x"B5"; when x"669" => DATA <= x"5A"; when x"66A" => DATA <= x"D0"; when x"66B" => DATA <= x"02"; when x"66C" => DATA <= x"D6"; when x"66D" => DATA <= x"5B"; when x"66E" => DATA <= x"D6"; when x"66F" => DATA <= x"5A"; when x"670" => DATA <= x"60"; when x"671" => DATA <= x"F6"; when x"672" => DATA <= x"5A"; when x"673" => DATA <= x"D0"; when x"674" => DATA <= x"FB"; when x"675" => DATA <= x"F6"; when x"676" => DATA <= x"5B"; when x"677" => DATA <= x"60"; when x"678" => DATA <= x"6C"; when x"679" => DATA <= x"FE"; when x"67A" => DATA <= x"03"; when x"67B" => DATA <= x"20"; when x"67C" => DATA <= x"C8"; when x"67D" => DATA <= x"C3"; when x"67E" => DATA <= x"A0"; when x"67F" => DATA <= x"00"; when x"680" => DATA <= x"A5"; when x"681" => DATA <= x"52"; when x"682" => DATA <= x"F0"; when x"683" => DATA <= x"3E"; when x"684" => DATA <= x"C9"; when x"685" => DATA <= x"05"; when x"686" => DATA <= x"90"; when x"687" => DATA <= x"02"; when x"688" => DATA <= x"A9"; when x"689" => DATA <= x"04"; when x"68A" => DATA <= x"A2"; when x"68B" => DATA <= x"80"; when x"68C" => DATA <= x"86"; when x"68D" => DATA <= x"54"; when x"68E" => DATA <= x"84"; when x"68F" => DATA <= x"53"; when x"690" => DATA <= x"85"; when x"691" => DATA <= x"52"; when x"692" => DATA <= x"AA"; when x"693" => DATA <= x"BD"; when x"694" => DATA <= x"CE"; when x"695" => DATA <= x"F6"; when x"696" => DATA <= x"A6"; when x"697" => DATA <= x"12"; when x"698" => DATA <= x"10"; when x"699" => DATA <= x"04"; when x"69A" => DATA <= x"C5"; when x"69B" => DATA <= x"12"; when x"69C" => DATA <= x"B0"; when x"69D" => DATA <= x"E1"; when x"69E" => DATA <= x"AA"; when x"69F" => DATA <= x"98"; when x"6A0" => DATA <= x"91"; when x"6A1" => DATA <= x"53"; when x"6A2" => DATA <= x"88"; when x"6A3" => DATA <= x"D0"; when x"6A4" => DATA <= x"FB"; when x"6A5" => DATA <= x"E6"; when x"6A6" => DATA <= x"54"; when x"6A7" => DATA <= x"E4"; when x"6A8" => DATA <= x"54"; when x"6A9" => DATA <= x"D0"; when x"6AA" => DATA <= x"F5"; when x"6AB" => DATA <= x"A4"; when x"6AC" => DATA <= x"52"; when x"6AD" => DATA <= x"B9"; when x"6AE" => DATA <= x"D8"; when x"6AF" => DATA <= x"F6"; when x"6B0" => DATA <= x"8D"; when x"6B1" => DATA <= x"FF"; when x"6B2" => DATA <= x"03"; when x"6B3" => DATA <= x"B9"; when x"6B4" => DATA <= x"D3"; when x"6B5" => DATA <= x"F6"; when x"6B6" => DATA <= x"8D"; when x"6B7" => DATA <= x"FE"; when x"6B8" => DATA <= x"03"; when x"6B9" => DATA <= x"B9"; when x"6BA" => DATA <= x"DD"; when x"6BB" => DATA <= x"F6"; when x"6BC" => DATA <= x"8D"; when x"6BD" => DATA <= x"00"; when x"6BE" => DATA <= x"B0"; when x"6BF" => DATA <= x"4C"; when x"6C0" => DATA <= x"58"; when x"6C1" => DATA <= x"C5"; when x"6C2" => DATA <= x"A9"; when x"6C3" => DATA <= x"40"; when x"6C4" => DATA <= x"99"; when x"6C5" => DATA <= x"00"; when x"6C6" => DATA <= x"80"; when x"6C7" => DATA <= x"99"; when x"6C8" => DATA <= x"00"; when x"6C9" => DATA <= x"81"; when x"6CA" => DATA <= x"88"; when x"6CB" => DATA <= x"D0"; when x"6CC" => DATA <= x"F7"; when x"6CD" => DATA <= x"F0"; when x"6CE" => DATA <= x"DC"; when x"6CF" => DATA <= x"84"; when x"6D0" => DATA <= x"86"; when x"6D1" => DATA <= x"8C"; when x"6D2" => DATA <= x"98"; when x"6D3" => DATA <= x"E2"; when x"6D4" => DATA <= x"3B"; when x"6D5" => DATA <= x"54"; when x"6D6" => DATA <= x"6D"; when x"6D7" => DATA <= x"AA"; when x"6D8" => DATA <= x"F6"; when x"6D9" => DATA <= x"F7"; when x"6DA" => DATA <= x"F7"; when x"6DB" => DATA <= x"F7"; when x"6DC" => DATA <= x"F7"; when x"6DD" => DATA <= x"00"; when x"6DE" => DATA <= x"30"; when x"6DF" => DATA <= x"70"; when x"6E0" => DATA <= x"B0"; when x"6E1" => DATA <= x"F0"; when x"6E2" => DATA <= x"A5"; when x"6E3" => DATA <= x"5B"; when x"6E4" => DATA <= x"05"; when x"6E5" => DATA <= x"5D"; when x"6E6" => DATA <= x"D0"; when x"6E7" => DATA <= x"52"; when x"6E8" => DATA <= x"A5"; when x"6E9" => DATA <= x"5A"; when x"6EA" => DATA <= x"C9"; when x"6EB" => DATA <= x"40"; when x"6EC" => DATA <= x"B0"; when x"6ED" => DATA <= x"4C"; when x"6EE" => DATA <= x"4A"; when x"6EF" => DATA <= x"85"; when x"6F0" => DATA <= x"5F"; when x"6F1" => DATA <= x"A9"; when x"6F2" => DATA <= x"2F"; when x"6F3" => DATA <= x"38"; when x"6F4" => DATA <= x"E5"; when x"6F5" => DATA <= x"5C"; when x"6F6" => DATA <= x"C9"; when x"6F7" => DATA <= x"30"; when x"6F8" => DATA <= x"B0"; when x"6F9" => DATA <= x"40"; when x"6FA" => DATA <= x"A2"; when x"6FB" => DATA <= x"FF"; when x"6FC" => DATA <= x"38"; when x"6FD" => DATA <= x"E8"; when x"6FE" => DATA <= x"E9"; when x"6FF" => DATA <= x"03"; when x"700" => DATA <= x"B0"; when x"701" => DATA <= x"FB"; when x"702" => DATA <= x"69"; when x"703" => DATA <= x"03"; when x"704" => DATA <= x"85"; when x"705" => DATA <= x"61"; when x"706" => DATA <= x"8A"; when x"707" => DATA <= x"0A"; when x"708" => DATA <= x"0A"; when x"709" => DATA <= x"0A"; when x"70A" => DATA <= x"0A"; when x"70B" => DATA <= x"0A"; when x"70C" => DATA <= x"05"; when x"70D" => DATA <= x"5F"; when x"70E" => DATA <= x"85"; when x"70F" => DATA <= x"5F"; when x"710" => DATA <= x"A9"; when x"711" => DATA <= x"80"; when x"712" => DATA <= x"69"; when x"713" => DATA <= x"00"; when x"714" => DATA <= x"85"; when x"715" => DATA <= x"60"; when x"716" => DATA <= x"A5"; when x"717" => DATA <= x"5A"; when x"718" => DATA <= x"4A"; when x"719" => DATA <= x"A5"; when x"71A" => DATA <= x"61"; when x"71B" => DATA <= x"2A"; when x"71C" => DATA <= x"A8"; when x"71D" => DATA <= x"B9"; when x"71E" => DATA <= x"CB"; when x"71F" => DATA <= x"F7"; when x"720" => DATA <= x"A0"; when x"721" => DATA <= x"00"; when x"722" => DATA <= x"A6"; when x"723" => DATA <= x"5E"; when x"724" => DATA <= x"CA"; when x"725" => DATA <= x"F0"; when x"726" => DATA <= x"0F"; when x"727" => DATA <= x"CA"; when x"728" => DATA <= x"F0"; when x"729" => DATA <= x"07"; when x"72A" => DATA <= x"49"; when x"72B" => DATA <= x"FF"; when x"72C" => DATA <= x"31"; when x"72D" => DATA <= x"5F"; when x"72E" => DATA <= x"91"; when x"72F" => DATA <= x"5F"; when x"730" => DATA <= x"60"; when x"731" => DATA <= x"51"; when x"732" => DATA <= x"5F"; when x"733" => DATA <= x"91"; when x"734" => DATA <= x"5F"; when x"735" => DATA <= x"60"; when x"736" => DATA <= x"11"; when x"737" => DATA <= x"5F"; when x"738" => DATA <= x"91"; when x"739" => DATA <= x"5F"; when x"73A" => DATA <= x"60"; when x"73B" => DATA <= x"A5"; when x"73C" => DATA <= x"5B"; when x"73D" => DATA <= x"05"; when x"73E" => DATA <= x"5D"; when x"73F" => DATA <= x"D0"; when x"740" => DATA <= x"F9"; when x"741" => DATA <= x"A5"; when x"742" => DATA <= x"5A"; when x"743" => DATA <= x"30"; when x"744" => DATA <= x"F5"; when x"745" => DATA <= x"4A"; when x"746" => DATA <= x"4A"; when x"747" => DATA <= x"4A"; when x"748" => DATA <= x"85"; when x"749" => DATA <= x"5F"; when x"74A" => DATA <= x"A9"; when x"74B" => DATA <= x"3F"; when x"74C" => DATA <= x"38"; when x"74D" => DATA <= x"E5"; when x"74E" => DATA <= x"5C"; when x"74F" => DATA <= x"C9"; when x"750" => DATA <= x"40"; when x"751" => DATA <= x"90"; when x"752" => DATA <= x"32"; when x"753" => DATA <= x"60"; when x"754" => DATA <= x"A5"; when x"755" => DATA <= x"5B"; when x"756" => DATA <= x"05"; when x"757" => DATA <= x"5D"; when x"758" => DATA <= x"D0"; when x"759" => DATA <= x"E0"; when x"75A" => DATA <= x"A5"; when x"75B" => DATA <= x"5A"; when x"75C" => DATA <= x"30"; when x"75D" => DATA <= x"DC"; when x"75E" => DATA <= x"4A"; when x"75F" => DATA <= x"4A"; when x"760" => DATA <= x"4A"; when x"761" => DATA <= x"85"; when x"762" => DATA <= x"5F"; when x"763" => DATA <= x"A9"; when x"764" => DATA <= x"5F"; when x"765" => DATA <= x"38"; when x"766" => DATA <= x"E5"; when x"767" => DATA <= x"5C"; when x"768" => DATA <= x"C9"; when x"769" => DATA <= x"60"; when x"76A" => DATA <= x"90"; when x"76B" => DATA <= x"19"; when x"76C" => DATA <= x"60"; when x"76D" => DATA <= x"A5"; when x"76E" => DATA <= x"5B"; when x"76F" => DATA <= x"05"; when x"770" => DATA <= x"5D"; when x"771" => DATA <= x"D0"; when x"772" => DATA <= x"C7"; when x"773" => DATA <= x"A5"; when x"774" => DATA <= x"5A"; when x"775" => DATA <= x"30"; when x"776" => DATA <= x"C3"; when x"777" => DATA <= x"4A"; when x"778" => DATA <= x"4A"; when x"779" => DATA <= x"4A"; when x"77A" => DATA <= x"85"; when x"77B" => DATA <= x"5F"; when x"77C" => DATA <= x"A9"; when x"77D" => DATA <= x"BF"; when x"77E" => DATA <= x"38"; when x"77F" => DATA <= x"E5"; when x"780" => DATA <= x"5C"; when x"781" => DATA <= x"C9"; when x"782" => DATA <= x"C0"; when x"783" => DATA <= x"B0"; when x"784" => DATA <= x"B5"; when x"785" => DATA <= x"A0"; when x"786" => DATA <= x"00"; when x"787" => DATA <= x"84"; when x"788" => DATA <= x"60"; when x"789" => DATA <= x"0A"; when x"78A" => DATA <= x"26"; when x"78B" => DATA <= x"60"; when x"78C" => DATA <= x"0A"; when x"78D" => DATA <= x"26"; when x"78E" => DATA <= x"60"; when x"78F" => DATA <= x"0A"; when x"790" => DATA <= x"26"; when x"791" => DATA <= x"60"; when x"792" => DATA <= x"0A"; when x"793" => DATA <= x"26"; when x"794" => DATA <= x"60"; when x"795" => DATA <= x"65"; when x"796" => DATA <= x"5F"; when x"797" => DATA <= x"85"; when x"798" => DATA <= x"5F"; when x"799" => DATA <= x"A5"; when x"79A" => DATA <= x"60"; when x"79B" => DATA <= x"69"; when x"79C" => DATA <= x"80"; when x"79D" => DATA <= x"85"; when x"79E" => DATA <= x"60"; when x"79F" => DATA <= x"A5"; when x"7A0" => DATA <= x"5A"; when x"7A1" => DATA <= x"29"; when x"7A2" => DATA <= x"07"; when x"7A3" => DATA <= x"A8"; when x"7A4" => DATA <= x"B9"; when x"7A5" => DATA <= x"C9"; when x"7A6" => DATA <= x"F7"; when x"7A7" => DATA <= x"4C"; when x"7A8" => DATA <= x"20"; when x"7A9" => DATA <= x"F7"; when x"7AA" => DATA <= x"A5"; when x"7AB" => DATA <= x"5B"; when x"7AC" => DATA <= x"05"; when x"7AD" => DATA <= x"5D"; when x"7AE" => DATA <= x"D0"; when x"7AF" => DATA <= x"BC"; when x"7B0" => DATA <= x"A5"; when x"7B1" => DATA <= x"5A"; when x"7B2" => DATA <= x"4A"; when x"7B3" => DATA <= x"4A"; when x"7B4" => DATA <= x"4A"; when x"7B5" => DATA <= x"85"; when x"7B6" => DATA <= x"5F"; when x"7B7" => DATA <= x"A9"; when x"7B8" => DATA <= x"BF"; when x"7B9" => DATA <= x"38"; when x"7BA" => DATA <= x"E5"; when x"7BB" => DATA <= x"5C"; when x"7BC" => DATA <= x"C9"; when x"7BD" => DATA <= x"C0"; when x"7BE" => DATA <= x"B0"; when x"7BF" => DATA <= x"AC"; when x"7C0" => DATA <= x"A0"; when x"7C1" => DATA <= x"00"; when x"7C2" => DATA <= x"84"; when x"7C3" => DATA <= x"60"; when x"7C4" => DATA <= x"0A"; when x"7C5" => DATA <= x"26"; when x"7C6" => DATA <= x"60"; when x"7C7" => DATA <= x"10"; when x"7C8" => DATA <= x"C0"; when x"7C9" => DATA <= x"80"; when x"7CA" => DATA <= x"40"; when x"7CB" => DATA <= x"20"; when x"7CC" => DATA <= x"10"; when x"7CD" => DATA <= x"08"; when x"7CE" => DATA <= x"04"; when x"7CF" => DATA <= x"02"; when x"7D0" => DATA <= x"01"; when x"7D1" => DATA <= x"68"; when x"7D2" => DATA <= x"85"; when x"7D3" => DATA <= x"E8"; when x"7D4" => DATA <= x"68"; when x"7D5" => DATA <= x"85"; when x"7D6" => DATA <= x"E9"; when x"7D7" => DATA <= x"A0"; when x"7D8" => DATA <= x"00"; when x"7D9" => DATA <= x"E6"; when x"7DA" => DATA <= x"E8"; when x"7DB" => DATA <= x"D0"; when x"7DC" => DATA <= x"02"; when x"7DD" => DATA <= x"E6"; when x"7DE" => DATA <= x"E9"; when x"7DF" => DATA <= x"B1"; when x"7E0" => DATA <= x"E8"; when x"7E1" => DATA <= x"30"; when x"7E2" => DATA <= x"06"; when x"7E3" => DATA <= x"20"; when x"7E4" => DATA <= x"F4"; when x"7E5" => DATA <= x"FF"; when x"7E6" => DATA <= x"4C"; when x"7E7" => DATA <= x"D7"; when x"7E8" => DATA <= x"F7"; when x"7E9" => DATA <= x"6C"; when x"7EA" => DATA <= x"E8"; when x"7EB" => DATA <= x"00"; when x"7EC" => DATA <= x"A2"; when x"7ED" => DATA <= x"D4"; when x"7EE" => DATA <= x"20"; when x"7EF" => DATA <= x"F1"; when x"7F0" => DATA <= x"F7"; when x"7F1" => DATA <= x"B5"; when x"7F2" => DATA <= x"01"; when x"7F3" => DATA <= x"20"; when x"7F4" => DATA <= x"02"; when x"7F5" => DATA <= x"F8"; when x"7F6" => DATA <= x"E8"; when x"7F7" => DATA <= x"E8"; when x"7F8" => DATA <= x"B5"; when x"7F9" => DATA <= x"FE"; when x"7FA" => DATA <= x"20"; when x"7FB" => DATA <= x"02"; when x"7FC" => DATA <= x"F8"; when x"7FD" => DATA <= x"A9"; when x"7FE" => DATA <= x"20"; when x"7FF" => DATA <= x"4C"; when x"800" => DATA <= x"F4"; when x"801" => DATA <= x"FF"; when x"802" => DATA <= x"48"; when x"803" => DATA <= x"4A"; when x"804" => DATA <= x"4A"; when x"805" => DATA <= x"4A"; when x"806" => DATA <= x"4A"; when x"807" => DATA <= x"20"; when x"808" => DATA <= x"0B"; when x"809" => DATA <= x"F8"; when x"80A" => DATA <= x"68"; when x"80B" => DATA <= x"29"; when x"80C" => DATA <= x"0F"; when x"80D" => DATA <= x"C9"; when x"80E" => DATA <= x"0A"; when x"80F" => DATA <= x"90"; when x"810" => DATA <= x"02"; when x"811" => DATA <= x"69"; when x"812" => DATA <= x"06"; when x"813" => DATA <= x"69"; when x"814" => DATA <= x"30"; when x"815" => DATA <= x"4C"; when x"816" => DATA <= x"F4"; when x"817" => DATA <= x"FF"; when x"818" => DATA <= x"20"; when x"819" => DATA <= x"76"; when x"81A" => DATA <= x"F8"; when x"81B" => DATA <= x"A2"; when x"81C" => DATA <= x"00"; when x"81D" => DATA <= x"C9"; when x"81E" => DATA <= x"22"; when x"81F" => DATA <= x"F0"; when x"820" => DATA <= x"06"; when x"821" => DATA <= x"E8"; when x"822" => DATA <= x"D0"; when x"823" => DATA <= x"1B"; when x"824" => DATA <= x"4C"; when x"825" => DATA <= x"7D"; when x"826" => DATA <= x"FA"; when x"827" => DATA <= x"C8"; when x"828" => DATA <= x"B9"; when x"829" => DATA <= x"00"; when x"82A" => DATA <= x"01"; when x"82B" => DATA <= x"C9"; when x"82C" => DATA <= x"0D"; when x"82D" => DATA <= x"F0"; when x"82E" => DATA <= x"F5"; when x"82F" => DATA <= x"9D"; when x"830" => DATA <= x"40"; when x"831" => DATA <= x"01"; when x"832" => DATA <= x"E8"; when x"833" => DATA <= x"C9"; when x"834" => DATA <= x"22"; when x"835" => DATA <= x"D0"; when x"836" => DATA <= x"F0"; when x"837" => DATA <= x"C8"; when x"838" => DATA <= x"B9"; when x"839" => DATA <= x"00"; when x"83A" => DATA <= x"01"; when x"83B" => DATA <= x"C9"; when x"83C" => DATA <= x"22"; when x"83D" => DATA <= x"F0"; when x"83E" => DATA <= x"E8"; when x"83F" => DATA <= x"A9"; when x"840" => DATA <= x"0D"; when x"841" => DATA <= x"9D"; when x"842" => DATA <= x"3F"; when x"843" => DATA <= x"01"; when x"844" => DATA <= x"A9"; when x"845" => DATA <= x"40"; when x"846" => DATA <= x"85"; when x"847" => DATA <= x"C9"; when x"848" => DATA <= x"A9"; when x"849" => DATA <= x"01"; when x"84A" => DATA <= x"85"; when x"84B" => DATA <= x"CA"; when x"84C" => DATA <= x"A2"; when x"84D" => DATA <= x"C9"; when x"84E" => DATA <= x"60"; when x"84F" => DATA <= x"A0"; when x"850" => DATA <= x"00"; when x"851" => DATA <= x"B5"; when x"852" => DATA <= x"00"; when x"853" => DATA <= x"99"; when x"854" => DATA <= x"C9"; when x"855" => DATA <= x"00"; when x"856" => DATA <= x"E8"; when x"857" => DATA <= x"C8"; when x"858" => DATA <= x"C0"; when x"859" => DATA <= x"0A"; when x"85A" => DATA <= x"90"; when x"85B" => DATA <= x"F5"; when x"85C" => DATA <= x"A0"; when x"85D" => DATA <= x"FF"; when x"85E" => DATA <= x"A9"; when x"85F" => DATA <= x"0D"; when x"860" => DATA <= x"C8"; when x"861" => DATA <= x"C0"; when x"862" => DATA <= x"0E"; when x"863" => DATA <= x"B0"; when x"864" => DATA <= x"07"; when x"865" => DATA <= x"D1"; when x"866" => DATA <= x"C9"; when x"867" => DATA <= x"D0"; when x"868" => DATA <= x"F7"; when x"869" => DATA <= x"C0"; when x"86A" => DATA <= x"00"; when x"86B" => DATA <= x"60"; when x"86C" => DATA <= x"20"; when x"86D" => DATA <= x"D1"; when x"86E" => DATA <= x"F7"; when x"86F" => DATA <= x"4E"; when x"870" => DATA <= x"41"; when x"871" => DATA <= x"4D"; when x"872" => DATA <= x"45"; when x"873" => DATA <= x"EA"; when x"874" => DATA <= x"00"; when x"875" => DATA <= x"C8"; when x"876" => DATA <= x"B9"; when x"877" => DATA <= x"00"; when x"878" => DATA <= x"01"; when x"879" => DATA <= x"C9"; when x"87A" => DATA <= x"20"; when x"87B" => DATA <= x"F0"; when x"87C" => DATA <= x"F8"; when x"87D" => DATA <= x"60"; when x"87E" => DATA <= x"C9"; when x"87F" => DATA <= x"30"; when x"880" => DATA <= x"90"; when x"881" => DATA <= x"0F"; when x"882" => DATA <= x"C9"; when x"883" => DATA <= x"3A"; when x"884" => DATA <= x"90"; when x"885" => DATA <= x"08"; when x"886" => DATA <= x"E9"; when x"887" => DATA <= x"07"; when x"888" => DATA <= x"90"; when x"889" => DATA <= x"07"; when x"88A" => DATA <= x"C9"; when x"88B" => DATA <= x"40"; when x"88C" => DATA <= x"B0"; when x"88D" => DATA <= x"02"; when x"88E" => DATA <= x"29"; when x"88F" => DATA <= x"0F"; when x"890" => DATA <= x"60"; when x"891" => DATA <= x"38"; when x"892" => DATA <= x"60"; when x"893" => DATA <= x"A9"; when x"894" => DATA <= x"00"; when x"895" => DATA <= x"95"; when x"896" => DATA <= x"00"; when x"897" => DATA <= x"95"; when x"898" => DATA <= x"01"; when x"899" => DATA <= x"95"; when x"89A" => DATA <= x"02"; when x"89B" => DATA <= x"20"; when x"89C" => DATA <= x"76"; when x"89D" => DATA <= x"F8"; when x"89E" => DATA <= x"B9"; when x"89F" => DATA <= x"00"; when x"8A0" => DATA <= x"01"; when x"8A1" => DATA <= x"20"; when x"8A2" => DATA <= x"7E"; when x"8A3" => DATA <= x"F8"; when x"8A4" => DATA <= x"B0"; when x"8A5" => DATA <= x"15"; when x"8A6" => DATA <= x"0A"; when x"8A7" => DATA <= x"0A"; when x"8A8" => DATA <= x"0A"; when x"8A9" => DATA <= x"0A"; when x"8AA" => DATA <= x"94"; when x"8AB" => DATA <= x"02"; when x"8AC" => DATA <= x"A0"; when x"8AD" => DATA <= x"04"; when x"8AE" => DATA <= x"0A"; when x"8AF" => DATA <= x"36"; when x"8B0" => DATA <= x"00"; when x"8B1" => DATA <= x"36"; when x"8B2" => DATA <= x"01"; when x"8B3" => DATA <= x"88"; when x"8B4" => DATA <= x"D0"; when x"8B5" => DATA <= x"F8"; when x"8B6" => DATA <= x"B4"; when x"8B7" => DATA <= x"02"; when x"8B8" => DATA <= x"C8"; when x"8B9" => DATA <= x"D0"; when x"8BA" => DATA <= x"E3"; when x"8BB" => DATA <= x"B5"; when x"8BC" => DATA <= x"02"; when x"8BD" => DATA <= x"60"; when x"8BE" => DATA <= x"43"; when x"8BF" => DATA <= x"41"; when x"8C0" => DATA <= x"54"; when x"8C1" => DATA <= x"FA"; when x"8C2" => DATA <= x"2A"; when x"8C3" => DATA <= x"4C"; when x"8C4" => DATA <= x"4F"; when x"8C5" => DATA <= x"41"; when x"8C6" => DATA <= x"44"; when x"8C7" => DATA <= x"F9"; when x"8C8" => DATA <= x"58"; when x"8C9" => DATA <= x"53"; when x"8CA" => DATA <= x"41"; when x"8CB" => DATA <= x"56"; when x"8CC" => DATA <= x"45"; when x"8CD" => DATA <= x"FA"; when x"8CE" => DATA <= x"BB"; when x"8CF" => DATA <= x"52"; when x"8D0" => DATA <= x"55"; when x"8D1" => DATA <= x"4E"; when x"8D2" => DATA <= x"FA"; when x"8D3" => DATA <= x"20"; when x"8D4" => DATA <= x"4D"; when x"8D5" => DATA <= x"4F"; when x"8D6" => DATA <= x"4E"; when x"8D7" => DATA <= x"FA"; when x"8D8" => DATA <= x"1A"; when x"8D9" => DATA <= x"4E"; when x"8DA" => DATA <= x"4F"; when x"8DB" => DATA <= x"4D"; when x"8DC" => DATA <= x"4F"; when x"8DD" => DATA <= x"4E"; when x"8DE" => DATA <= x"FA"; when x"8DF" => DATA <= x"19"; when x"8E0" => DATA <= x"46"; when x"8E1" => DATA <= x"4C"; when x"8E2" => DATA <= x"4F"; when x"8E3" => DATA <= x"41"; when x"8E4" => DATA <= x"44"; when x"8E5" => DATA <= x"F9"; when x"8E6" => DATA <= x"55"; when x"8E7" => DATA <= x"44"; when x"8E8" => DATA <= x"4F"; when x"8E9" => DATA <= x"53"; when x"8EA" => DATA <= x"CC"; when x"8EB" => DATA <= x"EF"; when x"8EC" => DATA <= x"00"; when x"8ED" => DATA <= x"F9"; when x"8EE" => DATA <= x"26"; when x"8EF" => DATA <= x"A2"; when x"8F0" => DATA <= x"FF"; when x"8F1" => DATA <= x"D8"; when x"8F2" => DATA <= x"A0"; when x"8F3" => DATA <= x"00"; when x"8F4" => DATA <= x"84"; when x"8F5" => DATA <= x"DD"; when x"8F6" => DATA <= x"20"; when x"8F7" => DATA <= x"76"; when x"8F8" => DATA <= x"F8"; when x"8F9" => DATA <= x"88"; when x"8FA" => DATA <= x"C8"; when x"8FB" => DATA <= x"E8"; when x"8FC" => DATA <= x"BD"; when x"8FD" => DATA <= x"BE"; when x"8FE" => DATA <= x"F8"; when x"8FF" => DATA <= x"30"; when x"900" => DATA <= x"18"; when x"901" => DATA <= x"D9"; when x"902" => DATA <= x"00"; when x"903" => DATA <= x"01"; when x"904" => DATA <= x"F0"; when x"905" => DATA <= x"F4"; when x"906" => DATA <= x"CA"; when x"907" => DATA <= x"E8"; when x"908" => DATA <= x"BD"; when x"909" => DATA <= x"BE"; when x"90A" => DATA <= x"F8"; when x"90B" => DATA <= x"10"; when x"90C" => DATA <= x"FA"; when x"90D" => DATA <= x"E8"; when x"90E" => DATA <= x"B9"; when x"90F" => DATA <= x"00"; when x"910" => DATA <= x"01"; when x"911" => DATA <= x"C9"; when x"912" => DATA <= x"2E"; when x"913" => DATA <= x"D0"; when x"914" => DATA <= x"DD"; when x"915" => DATA <= x"C8"; when x"916" => DATA <= x"CA"; when x"917" => DATA <= x"B0"; when x"918" => DATA <= x"E3"; when x"919" => DATA <= x"85"; when x"91A" => DATA <= x"CA"; when x"91B" => DATA <= x"BD"; when x"91C" => DATA <= x"BF"; when x"91D" => DATA <= x"F8"; when x"91E" => DATA <= x"85"; when x"91F" => DATA <= x"C9"; when x"920" => DATA <= x"18"; when x"921" => DATA <= x"A2"; when x"922" => DATA <= x"00"; when x"923" => DATA <= x"6C"; when x"924" => DATA <= x"C9"; when x"925" => DATA <= x"00"; when x"926" => DATA <= x"20"; when x"927" => DATA <= x"D1"; when x"928" => DATA <= x"F7"; when x"929" => DATA <= x"43"; when x"92A" => DATA <= x"4F"; when x"92B" => DATA <= x"4D"; when x"92C" => DATA <= x"3F"; when x"92D" => DATA <= x"EA"; when x"92E" => DATA <= x"00"; when x"92F" => DATA <= x"20"; when x"930" => DATA <= x"8E"; when x"931" => DATA <= x"FB"; when x"932" => DATA <= x"50"; when x"933" => DATA <= x"FA"; when x"934" => DATA <= x"F0"; when x"935" => DATA <= x"F9"; when x"936" => DATA <= x"20"; when x"937" => DATA <= x"2B"; when x"938" => DATA <= x"FC"; when x"939" => DATA <= x"A0"; when x"93A" => DATA <= x"00"; when x"93B" => DATA <= x"20"; when x"93C" => DATA <= x"D4"; when x"93D" => DATA <= x"FF"; when x"93E" => DATA <= x"91"; when x"93F" => DATA <= x"CB"; when x"940" => DATA <= x"E6"; when x"941" => DATA <= x"CB"; when x"942" => DATA <= x"D0"; when x"943" => DATA <= x"02"; when x"944" => DATA <= x"E6"; when x"945" => DATA <= x"CC"; when x"946" => DATA <= x"A2"; when x"947" => DATA <= x"D4"; when x"948" => DATA <= x"20"; when x"949" => DATA <= x"08"; when x"94A" => DATA <= x"FA"; when x"94B" => DATA <= x"D0"; when x"94C" => DATA <= x"EE"; when x"94D" => DATA <= x"38"; when x"94E" => DATA <= x"66"; when x"94F" => DATA <= x"DD"; when x"950" => DATA <= x"18"; when x"951" => DATA <= x"66"; when x"952" => DATA <= x"DD"; when x"953" => DATA <= x"28"; when x"954" => DATA <= x"60"; when x"955" => DATA <= x"38"; when x"956" => DATA <= x"66"; when x"957" => DATA <= x"DD"; when x"958" => DATA <= x"20"; when x"959" => DATA <= x"18"; when x"95A" => DATA <= x"F8"; when x"95B" => DATA <= x"A2"; when x"95C" => DATA <= x"CB"; when x"95D" => DATA <= x"20"; when x"95E" => DATA <= x"93"; when x"95F" => DATA <= x"F8"; when x"960" => DATA <= x"F0"; when x"961" => DATA <= x"04"; when x"962" => DATA <= x"A9"; when x"963" => DATA <= x"FF"; when x"964" => DATA <= x"85"; when x"965" => DATA <= x"CD"; when x"966" => DATA <= x"20"; when x"967" => DATA <= x"76"; when x"968" => DATA <= x"FA"; when x"969" => DATA <= x"A2"; when x"96A" => DATA <= x"C9"; when x"96B" => DATA <= x"6C"; when x"96C" => DATA <= x"0C"; when x"96D" => DATA <= x"02"; when x"96E" => DATA <= x"08"; when x"96F" => DATA <= x"78"; when x"970" => DATA <= x"20"; when x"971" => DATA <= x"4F"; when x"972" => DATA <= x"F8"; when x"973" => DATA <= x"08"; when x"974" => DATA <= x"20"; when x"975" => DATA <= x"3E"; when x"976" => DATA <= x"FC"; when x"977" => DATA <= x"28"; when x"978" => DATA <= x"F0"; when x"979" => DATA <= x"B5"; when x"97A" => DATA <= x"A9"; when x"97B" => DATA <= x"00"; when x"97C" => DATA <= x"85"; when x"97D" => DATA <= x"D0"; when x"97E" => DATA <= x"85"; when x"97F" => DATA <= x"D1"; when x"980" => DATA <= x"20"; when x"981" => DATA <= x"A2"; when x"982" => DATA <= x"F9"; when x"983" => DATA <= x"90"; when x"984" => DATA <= x"C9"; when x"985" => DATA <= x"E6"; when x"986" => DATA <= x"D0"; when x"987" => DATA <= x"E6"; when x"988" => DATA <= x"CC"; when x"989" => DATA <= x"D0"; when x"98A" => DATA <= x"F5"; when x"98B" => DATA <= x"18"; when x"98C" => DATA <= x"90"; when x"98D" => DATA <= x"C0"; when x"98E" => DATA <= x"20"; when x"98F" => DATA <= x"F4"; when x"990" => DATA <= x"FF"; when x"991" => DATA <= x"C8"; when x"992" => DATA <= x"B9"; when x"993" => DATA <= x"ED"; when x"994" => DATA <= x"00"; when x"995" => DATA <= x"C9"; when x"996" => DATA <= x"0D"; when x"997" => DATA <= x"D0"; when x"998" => DATA <= x"F5"; when x"999" => DATA <= x"C8"; when x"99A" => DATA <= x"20"; when x"99B" => DATA <= x"FD"; when x"99C" => DATA <= x"F7"; when x"99D" => DATA <= x"C0"; when x"99E" => DATA <= x"0E"; when x"99F" => DATA <= x"90"; when x"9A0" => DATA <= x"F8"; when x"9A1" => DATA <= x"60"; when x"9A2" => DATA <= x"A9"; when x"9A3" => DATA <= x"00"; when x"9A4" => DATA <= x"85"; when x"9A5" => DATA <= x"DC"; when x"9A6" => DATA <= x"20"; when x"9A7" => DATA <= x"8E"; when x"9A8" => DATA <= x"FB"; when x"9A9" => DATA <= x"50"; when x"9AA" => DATA <= x"F8"; when x"9AB" => DATA <= x"D0"; when x"9AC" => DATA <= x"F5"; when x"9AD" => DATA <= x"20"; when x"9AE" => DATA <= x"C9"; when x"9AF" => DATA <= x"FB"; when x"9B0" => DATA <= x"08"; when x"9B1" => DATA <= x"20"; when x"9B2" => DATA <= x"E2"; when x"9B3" => DATA <= x"FB"; when x"9B4" => DATA <= x"28"; when x"9B5" => DATA <= x"F0"; when x"9B6" => DATA <= x"10"; when x"9B7" => DATA <= x"A5"; when x"9B8" => DATA <= x"DB"; when x"9B9" => DATA <= x"29"; when x"9BA" => DATA <= x"20"; when x"9BB" => DATA <= x"05"; when x"9BC" => DATA <= x"EA"; when x"9BD" => DATA <= x"D0"; when x"9BE" => DATA <= x"E3"; when x"9BF" => DATA <= x"20"; when x"9C0" => DATA <= x"92"; when x"9C1" => DATA <= x"F9"; when x"9C2" => DATA <= x"20"; when x"9C3" => DATA <= x"ED"; when x"9C4" => DATA <= x"FF"; when x"9C5" => DATA <= x"D0"; when x"9C6" => DATA <= x"DB"; when x"9C7" => DATA <= x"A2"; when x"9C8" => DATA <= x"02"; when x"9C9" => DATA <= x"A5"; when x"9CA" => DATA <= x"DD"; when x"9CB" => DATA <= x"30"; when x"9CC" => DATA <= x"13"; when x"9CD" => DATA <= x"B5"; when x"9CE" => DATA <= x"CF"; when x"9CF" => DATA <= x"D5"; when x"9D0" => DATA <= x"D8"; when x"9D1" => DATA <= x"B0"; when x"9D2" => DATA <= x"08"; when x"9D3" => DATA <= x"A9"; when x"9D4" => DATA <= x"05"; when x"9D5" => DATA <= x"20"; when x"9D6" => DATA <= x"40"; when x"9D7" => DATA <= x"FC"; when x"9D8" => DATA <= x"20"; when x"9D9" => DATA <= x"3E"; when x"9DA" => DATA <= x"FC"; when x"9DB" => DATA <= x"D0"; when x"9DC" => DATA <= x"C5"; when x"9DD" => DATA <= x"CA"; when x"9DE" => DATA <= x"D0"; when x"9DF" => DATA <= x"ED"; when x"9E0" => DATA <= x"20"; when x"9E1" => DATA <= x"2B"; when x"9E2" => DATA <= x"FC"; when x"9E3" => DATA <= x"24"; when x"9E4" => DATA <= x"DB"; when x"9E5" => DATA <= x"50"; when x"9E6" => DATA <= x"0B"; when x"9E7" => DATA <= x"88"; when x"9E8" => DATA <= x"C8"; when x"9E9" => DATA <= x"20"; when x"9EA" => DATA <= x"D4"; when x"9EB" => DATA <= x"FF"; when x"9EC" => DATA <= x"91"; when x"9ED" => DATA <= x"CB"; when x"9EE" => DATA <= x"C4"; when x"9EF" => DATA <= x"D8"; when x"9F0" => DATA <= x"D0"; when x"9F1" => DATA <= x"F6"; when x"9F2" => DATA <= x"A5"; when x"9F3" => DATA <= x"DC"; when x"9F4" => DATA <= x"85"; when x"9F5" => DATA <= x"CE"; when x"9F6" => DATA <= x"20"; when x"9F7" => DATA <= x"D4"; when x"9F8" => DATA <= x"FF"; when x"9F9" => DATA <= x"C5"; when x"9FA" => DATA <= x"CE"; when x"9FB" => DATA <= x"F0"; when x"9FC" => DATA <= x"08"; when x"9FD" => DATA <= x"20"; when x"9FE" => DATA <= x"D1"; when x"9FF" => DATA <= x"F7"; when x"A00" => DATA <= x"53"; when x"A01" => DATA <= x"55"; when x"A02" => DATA <= x"4D"; when x"A03" => DATA <= x"EA"; when x"A04" => DATA <= x"00"; when x"A05" => DATA <= x"26"; when x"A06" => DATA <= x"DB"; when x"A07" => DATA <= x"60"; when x"A08" => DATA <= x"F6"; when x"A09" => DATA <= x"00"; when x"A0A" => DATA <= x"D0"; when x"A0B" => DATA <= x"02"; when x"A0C" => DATA <= x"F6"; when x"A0D" => DATA <= x"01"; when x"A0E" => DATA <= x"B5"; when x"A0F" => DATA <= x"00"; when x"A10" => DATA <= x"D5"; when x"A11" => DATA <= x"02"; when x"A12" => DATA <= x"D0"; when x"A13" => DATA <= x"04"; when x"A14" => DATA <= x"B5"; when x"A15" => DATA <= x"01"; when x"A16" => DATA <= x"D5"; when x"A17" => DATA <= x"03"; when x"A18" => DATA <= x"60"; when x"A19" => DATA <= x"CA"; when x"A1A" => DATA <= x"20"; when x"A1B" => DATA <= x"76"; when x"A1C" => DATA <= x"FA"; when x"A1D" => DATA <= x"86"; when x"A1E" => DATA <= x"EA"; when x"A1F" => DATA <= x"60"; when x"A20" => DATA <= x"20"; when x"A21" => DATA <= x"58"; when x"A22" => DATA <= x"F9"; when x"A23" => DATA <= x"24"; when x"A24" => DATA <= x"DD"; when x"A25" => DATA <= x"70"; when x"A26" => DATA <= x"4C"; when x"A27" => DATA <= x"6C"; when x"A28" => DATA <= x"D6"; when x"A29" => DATA <= x"00"; when x"A2A" => DATA <= x"08"; when x"A2B" => DATA <= x"20"; when x"A2C" => DATA <= x"76"; when x"A2D" => DATA <= x"FA"; when x"A2E" => DATA <= x"20"; when x"A2F" => DATA <= x"3E"; when x"A30" => DATA <= x"FC"; when x"A31" => DATA <= x"20"; when x"A32" => DATA <= x"8E"; when x"A33" => DATA <= x"FB"; when x"A34" => DATA <= x"70"; when x"A35" => DATA <= x"02"; when x"A36" => DATA <= x"28"; when x"A37" => DATA <= x"60"; when x"A38" => DATA <= x"F0"; when x"A39" => DATA <= x"0A"; when x"A3A" => DATA <= x"A0"; when x"A3B" => DATA <= x"00"; when x"A3C" => DATA <= x"20"; when x"A3D" => DATA <= x"99"; when x"A3E" => DATA <= x"F9"; when x"A3F" => DATA <= x"20"; when x"A40" => DATA <= x"EC"; when x"A41" => DATA <= x"F7"; when x"A42" => DATA <= x"D0"; when x"A43" => DATA <= x"19"; when x"A44" => DATA <= x"20"; when x"A45" => DATA <= x"C9"; when x"A46" => DATA <= x"FB"; when x"A47" => DATA <= x"20"; when x"A48" => DATA <= x"E2"; when x"A49" => DATA <= x"FB"; when x"A4A" => DATA <= x"20"; when x"A4B" => DATA <= x"92"; when x"A4C" => DATA <= x"F9"; when x"A4D" => DATA <= x"20"; when x"A4E" => DATA <= x"EC"; when x"A4F" => DATA <= x"F7"; when x"A50" => DATA <= x"26"; when x"A51" => DATA <= x"DB"; when x"A52" => DATA <= x"10"; when x"A53" => DATA <= x"09"; when x"A54" => DATA <= x"E8"; when x"A55" => DATA <= x"20"; when x"A56" => DATA <= x"F1"; when x"A57" => DATA <= x"F7"; when x"A58" => DATA <= x"B5"; when x"A59" => DATA <= x"FD"; when x"A5A" => DATA <= x"20"; when x"A5B" => DATA <= x"02"; when x"A5C" => DATA <= x"F8"; when x"A5D" => DATA <= x"20"; when x"A5E" => DATA <= x"ED"; when x"A5F" => DATA <= x"FF"; when x"A60" => DATA <= x"D0"; when x"A61" => DATA <= x"CF"; when x"A62" => DATA <= x"4C"; when x"A63" => DATA <= x"ED"; when x"A64" => DATA <= x"FF"; when x"A65" => DATA <= x"20"; when x"A66" => DATA <= x"93"; when x"A67" => DATA <= x"F8"; when x"A68" => DATA <= x"F0"; when x"A69" => DATA <= x"13"; when x"A6A" => DATA <= x"60"; when x"A6B" => DATA <= x"A2"; when x"A6C" => DATA <= x"CB"; when x"A6D" => DATA <= x"20"; when x"A6E" => DATA <= x"65"; when x"A6F" => DATA <= x"FA"; when x"A70" => DATA <= x"20"; when x"A71" => DATA <= x"76"; when x"A72" => DATA <= x"FA"; when x"A73" => DATA <= x"6C"; when x"A74" => DATA <= x"CB"; when x"A75" => DATA <= x"00"; when x"A76" => DATA <= x"20"; when x"A77" => DATA <= x"76"; when x"A78" => DATA <= x"F8"; when x"A79" => DATA <= x"C9"; when x"A7A" => DATA <= x"0D"; when x"A7B" => DATA <= x"F0"; when x"A7C" => DATA <= x"A2"; when x"A7D" => DATA <= x"20"; when x"A7E" => DATA <= x"D1"; when x"A7F" => DATA <= x"F7"; when x"A80" => DATA <= x"53"; when x"A81" => DATA <= x"59"; when x"A82" => DATA <= x"4E"; when x"A83" => DATA <= x"3F"; when x"A84" => DATA <= x"EA"; when x"A85" => DATA <= x"00"; when x"A86" => DATA <= x"38"; when x"A87" => DATA <= x"A5"; when x"A88" => DATA <= x"D1"; when x"A89" => DATA <= x"E5"; when x"A8A" => DATA <= x"CF"; when x"A8B" => DATA <= x"48"; when x"A8C" => DATA <= x"A5"; when x"A8D" => DATA <= x"D2"; when x"A8E" => DATA <= x"E5"; when x"A8F" => DATA <= x"D0"; when x"A90" => DATA <= x"A8"; when x"A91" => DATA <= x"68"; when x"A92" => DATA <= x"18"; when x"A93" => DATA <= x"65"; when x"A94" => DATA <= x"CB"; when x"A95" => DATA <= x"85"; when x"A96" => DATA <= x"CD"; when x"A97" => DATA <= x"98"; when x"A98" => DATA <= x"65"; when x"A99" => DATA <= x"CC"; when x"A9A" => DATA <= x"85"; when x"A9B" => DATA <= x"CE"; when x"A9C" => DATA <= x"A0"; when x"A9D" => DATA <= x"04"; when x"A9E" => DATA <= x"B9"; when x"A9F" => DATA <= x"CA"; when x"AA0" => DATA <= x"00"; when x"AA1" => DATA <= x"20"; when x"AA2" => DATA <= x"D1"; when x"AA3" => DATA <= x"FF"; when x"AA4" => DATA <= x"88"; when x"AA5" => DATA <= x"D0"; when x"AA6" => DATA <= x"F7"; when x"AA7" => DATA <= x"B1"; when x"AA8" => DATA <= x"CF"; when x"AA9" => DATA <= x"20"; when x"AAA" => DATA <= x"D1"; when x"AAB" => DATA <= x"FF"; when x"AAC" => DATA <= x"E6"; when x"AAD" => DATA <= x"CF"; when x"AAE" => DATA <= x"D0"; when x"AAF" => DATA <= x"02"; when x"AB0" => DATA <= x"E6"; when x"AB1" => DATA <= x"D0"; when x"AB2" => DATA <= x"A2"; when x"AB3" => DATA <= x"CB"; when x"AB4" => DATA <= x"20"; when x"AB5" => DATA <= x"08"; when x"AB6" => DATA <= x"FA"; when x"AB7" => DATA <= x"D0"; when x"AB8" => DATA <= x"EE"; when x"AB9" => DATA <= x"28"; when x"ABA" => DATA <= x"60"; when x"ABB" => DATA <= x"20"; when x"ABC" => DATA <= x"18"; when x"ABD" => DATA <= x"F8"; when x"ABE" => DATA <= x"A2"; when x"ABF" => DATA <= x"CB"; when x"AC0" => DATA <= x"20"; when x"AC1" => DATA <= x"65"; when x"AC2" => DATA <= x"FA"; when x"AC3" => DATA <= x"A2"; when x"AC4" => DATA <= x"D1"; when x"AC5" => DATA <= x"20"; when x"AC6" => DATA <= x"65"; when x"AC7" => DATA <= x"FA"; when x"AC8" => DATA <= x"A2"; when x"AC9" => DATA <= x"CD"; when x"ACA" => DATA <= x"20"; when x"ACB" => DATA <= x"93"; when x"ACC" => DATA <= x"F8"; when x"ACD" => DATA <= x"08"; when x"ACE" => DATA <= x"A5"; when x"ACF" => DATA <= x"CB"; when x"AD0" => DATA <= x"A6"; when x"AD1" => DATA <= x"CC"; when x"AD2" => DATA <= x"28"; when x"AD3" => DATA <= x"D0"; when x"AD4" => DATA <= x"04"; when x"AD5" => DATA <= x"85"; when x"AD6" => DATA <= x"CD"; when x"AD7" => DATA <= x"86"; when x"AD8" => DATA <= x"CE"; when x"AD9" => DATA <= x"85"; when x"ADA" => DATA <= x"CF"; when x"ADB" => DATA <= x"86"; when x"ADC" => DATA <= x"D0"; when x"ADD" => DATA <= x"20"; when x"ADE" => DATA <= x"76"; when x"ADF" => DATA <= x"FA"; when x"AE0" => DATA <= x"A2"; when x"AE1" => DATA <= x"C9"; when x"AE2" => DATA <= x"6C"; when x"AE3" => DATA <= x"0E"; when x"AE4" => DATA <= x"02"; when x"AE5" => DATA <= x"08"; when x"AE6" => DATA <= x"78"; when x"AE7" => DATA <= x"20"; when x"AE8" => DATA <= x"4F"; when x"AE9" => DATA <= x"F8"; when x"AEA" => DATA <= x"08"; when x"AEB" => DATA <= x"A9"; when x"AEC" => DATA <= x"06"; when x"AED" => DATA <= x"20"; when x"AEE" => DATA <= x"40"; when x"AEF" => DATA <= x"FC"; when x"AF0" => DATA <= x"A2"; when x"AF1" => DATA <= x"07"; when x"AF2" => DATA <= x"20"; when x"AF3" => DATA <= x"7A"; when x"AF4" => DATA <= x"FB"; when x"AF5" => DATA <= x"28"; when x"AF6" => DATA <= x"F0"; when x"AF7" => DATA <= x"8E"; when x"AF8" => DATA <= x"A2"; when x"AF9" => DATA <= x"04"; when x"AFA" => DATA <= x"B5"; when x"AFB" => DATA <= x"CE"; when x"AFC" => DATA <= x"95"; when x"AFD" => DATA <= x"D2"; when x"AFE" => DATA <= x"CA"; when x"AFF" => DATA <= x"D0"; when x"B00" => DATA <= x"F9"; when x"B01" => DATA <= x"86"; when x"B02" => DATA <= x"D0"; when x"B03" => DATA <= x"86"; when x"B04" => DATA <= x"D1"; when x"B05" => DATA <= x"A5"; when x"B06" => DATA <= x"D5"; when x"B07" => DATA <= x"D0"; when x"B08" => DATA <= x"02"; when x"B09" => DATA <= x"C6"; when x"B0A" => DATA <= x"D6"; when x"B0B" => DATA <= x"C6"; when x"B0C" => DATA <= x"D5"; when x"B0D" => DATA <= x"18"; when x"B0E" => DATA <= x"66"; when x"B0F" => DATA <= x"D2"; when x"B10" => DATA <= x"38"; when x"B11" => DATA <= x"A2"; when x"B12" => DATA <= x"FF"; when x"B13" => DATA <= x"A5"; when x"B14" => DATA <= x"D5"; when x"B15" => DATA <= x"E5"; when x"B16" => DATA <= x"D3"; when x"B17" => DATA <= x"85"; when x"B18" => DATA <= x"CF"; when x"B19" => DATA <= x"A5"; when x"B1A" => DATA <= x"D6"; when x"B1B" => DATA <= x"E5"; when x"B1C" => DATA <= x"D4"; when x"B1D" => DATA <= x"08"; when x"B1E" => DATA <= x"66"; when x"B1F" => DATA <= x"D2"; when x"B20" => DATA <= x"28"; when x"B21" => DATA <= x"90"; when x"B22" => DATA <= x"06"; when x"B23" => DATA <= x"18"; when x"B24" => DATA <= x"F0"; when x"B25" => DATA <= x"03"; when x"B26" => DATA <= x"86"; when x"B27" => DATA <= x"CF"; when x"B28" => DATA <= x"38"; when x"B29" => DATA <= x"66"; when x"B2A" => DATA <= x"D2"; when x"B2B" => DATA <= x"E8"; when x"B2C" => DATA <= x"20"; when x"B2D" => DATA <= x"3B"; when x"B2E" => DATA <= x"FB"; when x"B2F" => DATA <= x"E6"; when x"B30" => DATA <= x"D0"; when x"B31" => DATA <= x"E6"; when x"B32" => DATA <= x"D4"; when x"B33" => DATA <= x"E6"; when x"B34" => DATA <= x"CC"; when x"B35" => DATA <= x"26"; when x"B36" => DATA <= x"D2"; when x"B37" => DATA <= x"B0"; when x"B38" => DATA <= x"D5"; when x"B39" => DATA <= x"28"; when x"B3A" => DATA <= x"60"; when x"B3B" => DATA <= x"A2"; when x"B3C" => DATA <= x"07"; when x"B3D" => DATA <= x"20"; when x"B3E" => DATA <= x"7A"; when x"B3F" => DATA <= x"FB"; when x"B40" => DATA <= x"86"; when x"B41" => DATA <= x"DC"; when x"B42" => DATA <= x"A0"; when x"B43" => DATA <= x"04"; when x"B44" => DATA <= x"A9"; when x"B45" => DATA <= x"2A"; when x"B46" => DATA <= x"20"; when x"B47" => DATA <= x"D1"; when x"B48" => DATA <= x"FF"; when x"B49" => DATA <= x"88"; when x"B4A" => DATA <= x"D0"; when x"B4B" => DATA <= x"F8"; when x"B4C" => DATA <= x"B1"; when x"B4D" => DATA <= x"C9"; when x"B4E" => DATA <= x"20"; when x"B4F" => DATA <= x"D1"; when x"B50" => DATA <= x"FF"; when x"B51" => DATA <= x"C8"; when x"B52" => DATA <= x"C9"; when x"B53" => DATA <= x"0D"; when x"B54" => DATA <= x"D0"; when x"B55" => DATA <= x"F6"; when x"B56" => DATA <= x"A0"; when x"B57" => DATA <= x"08"; when x"B58" => DATA <= x"B9"; when x"B59" => DATA <= x"CA"; when x"B5A" => DATA <= x"00"; when x"B5B" => DATA <= x"20"; when x"B5C" => DATA <= x"D1"; when x"B5D" => DATA <= x"FF"; when x"B5E" => DATA <= x"88"; when x"B5F" => DATA <= x"D0"; when x"B60" => DATA <= x"F7"; when x"B61" => DATA <= x"20"; when x"B62" => DATA <= x"81"; when x"B63" => DATA <= x"FB"; when x"B64" => DATA <= x"24"; when x"B65" => DATA <= x"D2"; when x"B66" => DATA <= x"50"; when x"B67" => DATA <= x"0B"; when x"B68" => DATA <= x"88"; when x"B69" => DATA <= x"C8"; when x"B6A" => DATA <= x"B1"; when x"B6B" => DATA <= x"D3"; when x"B6C" => DATA <= x"20"; when x"B6D" => DATA <= x"D1"; when x"B6E" => DATA <= x"FF"; when x"B6F" => DATA <= x"C4"; when x"B70" => DATA <= x"CF"; when x"B71" => DATA <= x"D0"; when x"B72" => DATA <= x"F6"; when x"B73" => DATA <= x"A5"; when x"B74" => DATA <= x"DC"; when x"B75" => DATA <= x"20"; when x"B76" => DATA <= x"D1"; when x"B77" => DATA <= x"FF"; when x"B78" => DATA <= x"A2"; when x"B79" => DATA <= x"04"; when x"B7A" => DATA <= x"8E"; when x"B7B" => DATA <= x"02"; when x"B7C" => DATA <= x"B0"; when x"B7D" => DATA <= x"A2"; when x"B7E" => DATA <= x"78"; when x"B7F" => DATA <= x"D0"; when x"B80" => DATA <= x"02"; when x"B81" => DATA <= x"A2"; when x"B82" => DATA <= x"1E"; when x"B83" => DATA <= x"20"; when x"B84" => DATA <= x"66"; when x"B85" => DATA <= x"FE"; when x"B86" => DATA <= x"CA"; when x"B87" => DATA <= x"D0"; when x"B88" => DATA <= x"FA"; when x"B89" => DATA <= x"60"; when x"B8A" => DATA <= x"A2"; when x"B8B" => DATA <= x"06"; when x"B8C" => DATA <= x"D0"; when x"B8D" => DATA <= x"F5"; when x"B8E" => DATA <= x"2C"; when x"B8F" => DATA <= x"01"; when x"B90" => DATA <= x"B0"; when x"B91" => DATA <= x"10"; when x"B92" => DATA <= x"FB"; when x"B93" => DATA <= x"50"; when x"B94" => DATA <= x"F9"; when x"B95" => DATA <= x"A0"; when x"B96" => DATA <= x"00"; when x"B97" => DATA <= x"85"; when x"B98" => DATA <= x"C3"; when x"B99" => DATA <= x"A9"; when x"B9A" => DATA <= x"10"; when x"B9B" => DATA <= x"85"; when x"B9C" => DATA <= x"C2"; when x"B9D" => DATA <= x"2C"; when x"B9E" => DATA <= x"01"; when x"B9F" => DATA <= x"B0"; when x"BA0" => DATA <= x"10"; when x"BA1" => DATA <= x"0F"; when x"BA2" => DATA <= x"50"; when x"BA3" => DATA <= x"0D"; when x"BA4" => DATA <= x"20"; when x"BA5" => DATA <= x"BD"; when x"BA6" => DATA <= x"FC"; when x"BA7" => DATA <= x"B0"; when x"BA8" => DATA <= x"EC"; when x"BA9" => DATA <= x"C6"; when x"BAA" => DATA <= x"C3"; when x"BAB" => DATA <= x"D0"; when x"BAC" => DATA <= x"F0"; when x"BAD" => DATA <= x"C6"; when x"BAE" => DATA <= x"C2"; when x"BAF" => DATA <= x"D0"; when x"BB0" => DATA <= x"EC"; when x"BB1" => DATA <= x"70"; when x"BB2" => DATA <= x"01"; when x"BB3" => DATA <= x"60"; when x"BB4" => DATA <= x"A0"; when x"BB5" => DATA <= x"04"; when x"BB6" => DATA <= x"08"; when x"BB7" => DATA <= x"20"; when x"BB8" => DATA <= x"E4"; when x"BB9" => DATA <= x"FB"; when x"BBA" => DATA <= x"28"; when x"BBB" => DATA <= x"A0"; when x"BBC" => DATA <= x"04"; when x"BBD" => DATA <= x"A9"; when x"BBE" => DATA <= x"2A"; when x"BBF" => DATA <= x"D9"; when x"BC0" => DATA <= x"D3"; when x"BC1" => DATA <= x"00"; when x"BC2" => DATA <= x"D0"; when x"BC3" => DATA <= x"03"; when x"BC4" => DATA <= x"88"; when x"BC5" => DATA <= x"D0"; when x"BC6" => DATA <= x"F8"; when x"BC7" => DATA <= x"60"; when x"BC8" => DATA <= x"C8"; when x"BC9" => DATA <= x"20"; when x"BCA" => DATA <= x"D4"; when x"BCB" => DATA <= x"FF"; when x"BCC" => DATA <= x"99"; when x"BCD" => DATA <= x"ED"; when x"BCE" => DATA <= x"00"; when x"BCF" => DATA <= x"C9"; when x"BD0" => DATA <= x"0D"; when x"BD1" => DATA <= x"D0"; when x"BD2" => DATA <= x"F5"; when x"BD3" => DATA <= x"A0"; when x"BD4" => DATA <= x"FF"; when x"BD5" => DATA <= x"C8"; when x"BD6" => DATA <= x"B1"; when x"BD7" => DATA <= x"C9"; when x"BD8" => DATA <= x"D9"; when x"BD9" => DATA <= x"ED"; when x"BDA" => DATA <= x"00"; when x"BDB" => DATA <= x"D0"; when x"BDC" => DATA <= x"EA"; when x"BDD" => DATA <= x"C9"; when x"BDE" => DATA <= x"0D"; when x"BDF" => DATA <= x"D0"; when x"BE0" => DATA <= x"F4"; when x"BE1" => DATA <= x"60"; when x"BE2" => DATA <= x"A0"; when x"BE3" => DATA <= x"08"; when x"BE4" => DATA <= x"20"; when x"BE5" => DATA <= x"D4"; when x"BE6" => DATA <= x"FF"; when x"BE7" => DATA <= x"99"; when x"BE8" => DATA <= x"D3"; when x"BE9" => DATA <= x"00"; when x"BEA" => DATA <= x"88"; when x"BEB" => DATA <= x"D0"; when x"BEC" => DATA <= x"F7"; when x"BED" => DATA <= x"60"; when x"BEE" => DATA <= x"86"; when x"BEF" => DATA <= x"EC"; when x"BF0" => DATA <= x"84"; when x"BF1" => DATA <= x"C3"; when x"BF2" => DATA <= x"08"; when x"BF3" => DATA <= x"78"; when x"BF4" => DATA <= x"A9"; when x"BF5" => DATA <= x"78"; when x"BF6" => DATA <= x"85"; when x"BF7" => DATA <= x"C0"; when x"BF8" => DATA <= x"20"; when x"BF9" => DATA <= x"BD"; when x"BFA" => DATA <= x"FC"; when x"BFB" => DATA <= x"90"; when x"BFC" => DATA <= x"F7"; when x"BFD" => DATA <= x"E6"; when x"BFE" => DATA <= x"C0"; when x"BFF" => DATA <= x"10"; when x"C00" => DATA <= x"F7"; when x"C01" => DATA <= x"A9"; when x"C02" => DATA <= x"53"; when x"C03" => DATA <= x"85"; when x"C04" => DATA <= x"C4"; when x"C05" => DATA <= x"A2"; when x"C06" => DATA <= x"00"; when x"C07" => DATA <= x"AC"; when x"C08" => DATA <= x"02"; when x"C09" => DATA <= x"B0"; when x"C0A" => DATA <= x"20"; when x"C0B" => DATA <= x"CD"; when x"C0C" => DATA <= x"FC"; when x"C0D" => DATA <= x"F0"; when x"C0E" => DATA <= x"00"; when x"C0F" => DATA <= x"F0"; when x"C10" => DATA <= x"01"; when x"C11" => DATA <= x"E8"; when x"C12" => DATA <= x"C6"; when x"C13" => DATA <= x"C4"; when x"C14" => DATA <= x"D0"; when x"C15" => DATA <= x"F4"; when x"C16" => DATA <= x"E0"; when x"C17" => DATA <= x"0C"; when x"C18" => DATA <= x"66"; when x"C19" => DATA <= x"C0"; when x"C1A" => DATA <= x"90"; when x"C1B" => DATA <= x"E5"; when x"C1C" => DATA <= x"A5"; when x"C1D" => DATA <= x"C0"; when x"C1E" => DATA <= x"28"; when x"C1F" => DATA <= x"A4"; when x"C20" => DATA <= x"C3"; when x"C21" => DATA <= x"A6"; when x"C22" => DATA <= x"EC"; when x"C23" => DATA <= x"48"; when x"C24" => DATA <= x"18"; when x"C25" => DATA <= x"65"; when x"C26" => DATA <= x"DC"; when x"C27" => DATA <= x"85"; when x"C28" => DATA <= x"DC"; when x"C29" => DATA <= x"68"; when x"C2A" => DATA <= x"60"; when x"C2B" => DATA <= x"A5"; when x"C2C" => DATA <= x"CD"; when x"C2D" => DATA <= x"30"; when x"C2E" => DATA <= x"08"; when x"C2F" => DATA <= x"A5"; when x"C30" => DATA <= x"D4"; when x"C31" => DATA <= x"85"; when x"C32" => DATA <= x"CB"; when x"C33" => DATA <= x"A5"; when x"C34" => DATA <= x"D5"; when x"C35" => DATA <= x"85"; when x"C36" => DATA <= x"CC"; when x"C37" => DATA <= x"60"; when x"C38" => DATA <= x"B0"; when x"C39" => DATA <= x"04"; when x"C3A" => DATA <= x"A9"; when x"C3B" => DATA <= x"06"; when x"C3C" => DATA <= x"D0"; when x"C3D" => DATA <= x"02"; when x"C3E" => DATA <= x"A9"; when x"C3F" => DATA <= x"04"; when x"C40" => DATA <= x"A2"; when x"C41" => DATA <= x"07"; when x"C42" => DATA <= x"8E"; when x"C43" => DATA <= x"02"; when x"C44" => DATA <= x"B0"; when x"C45" => DATA <= x"24"; when x"C46" => DATA <= x"EA"; when x"C47" => DATA <= x"D0"; when x"C48" => DATA <= x"2D"; when x"C49" => DATA <= x"C9"; when x"C4A" => DATA <= x"05"; when x"C4B" => DATA <= x"F0"; when x"C4C" => DATA <= x"16"; when x"C4D" => DATA <= x"B0"; when x"C4E" => DATA <= x"09"; when x"C4F" => DATA <= x"20"; when x"C50" => DATA <= x"D1"; when x"C51" => DATA <= x"F7"; when x"C52" => DATA <= x"50"; when x"C53" => DATA <= x"4C"; when x"C54" => DATA <= x"41"; when x"C55" => DATA <= x"59"; when x"C56" => DATA <= x"D0"; when x"C57" => DATA <= x"15"; when x"C58" => DATA <= x"20"; when x"C59" => DATA <= x"D1"; when x"C5A" => DATA <= x"F7"; when x"C5B" => DATA <= x"52"; when x"C5C" => DATA <= x"45"; when x"C5D" => DATA <= x"43"; when x"C5E" => DATA <= x"4F"; when x"C5F" => DATA <= x"52"; when x"C60" => DATA <= x"44"; when x"C61" => DATA <= x"D0"; when x"C62" => DATA <= x"0A"; when x"C63" => DATA <= x"20"; when x"C64" => DATA <= x"D1"; when x"C65" => DATA <= x"F7"; when x"C66" => DATA <= x"52"; when x"C67" => DATA <= x"45"; when x"C68" => DATA <= x"57"; when x"C69" => DATA <= x"49"; when x"C6A" => DATA <= x"4E"; when x"C6B" => DATA <= x"44"; when x"C6C" => DATA <= x"EA"; when x"C6D" => DATA <= x"20"; when x"C6E" => DATA <= x"D1"; when x"C6F" => DATA <= x"F7"; when x"C70" => DATA <= x"20"; when x"C71" => DATA <= x"54"; when x"C72" => DATA <= x"41"; when x"C73" => DATA <= x"50"; when x"C74" => DATA <= x"45"; when x"C75" => DATA <= x"EA"; when x"C76" => DATA <= x"20"; when x"C77" => DATA <= x"E3"; when x"C78" => DATA <= x"FF"; when x"C79" => DATA <= x"4C"; when x"C7A" => DATA <= x"ED"; when x"C7B" => DATA <= x"FF"; when x"C7C" => DATA <= x"86"; when x"C7D" => DATA <= x"EC"; when x"C7E" => DATA <= x"84"; when x"C7F" => DATA <= x"C3"; when x"C80" => DATA <= x"08"; when x"C81" => DATA <= x"78"; when x"C82" => DATA <= x"48"; when x"C83" => DATA <= x"20"; when x"C84" => DATA <= x"23"; when x"C85" => DATA <= x"FC"; when x"C86" => DATA <= x"85"; when x"C87" => DATA <= x"C0"; when x"C88" => DATA <= x"20"; when x"C89" => DATA <= x"D8"; when x"C8A" => DATA <= x"FC"; when x"C8B" => DATA <= x"A9"; when x"C8C" => DATA <= x"0A"; when x"C8D" => DATA <= x"85"; when x"C8E" => DATA <= x"C1"; when x"C8F" => DATA <= x"18"; when x"C90" => DATA <= x"90"; when x"C91" => DATA <= x"0A"; when x"C92" => DATA <= x"A2"; when x"C93" => DATA <= x"07"; when x"C94" => DATA <= x"8E"; when x"C95" => DATA <= x"02"; when x"C96" => DATA <= x"B0"; when x"C97" => DATA <= x"20"; when x"C98" => DATA <= x"DA"; when x"C99" => DATA <= x"FC"; when x"C9A" => DATA <= x"30"; when x"C9B" => DATA <= x"13"; when x"C9C" => DATA <= x"A0"; when x"C9D" => DATA <= x"04"; when x"C9E" => DATA <= x"A9"; when x"C9F" => DATA <= x"04"; when x"CA0" => DATA <= x"8D"; when x"CA1" => DATA <= x"02"; when x"CA2" => DATA <= x"B0"; when x"CA3" => DATA <= x"20"; when x"CA4" => DATA <= x"D8"; when x"CA5" => DATA <= x"FC"; when x"CA6" => DATA <= x"EE"; when x"CA7" => DATA <= x"02"; when x"CA8" => DATA <= x"B0"; when x"CA9" => DATA <= x"20"; when x"CAA" => DATA <= x"D8"; when x"CAB" => DATA <= x"FC"; when x"CAC" => DATA <= x"88"; when x"CAD" => DATA <= x"D0"; when x"CAE" => DATA <= x"EF"; when x"CAF" => DATA <= x"38"; when x"CB0" => DATA <= x"66"; when x"CB1" => DATA <= x"C0"; when x"CB2" => DATA <= x"C6"; when x"CB3" => DATA <= x"C1"; when x"CB4" => DATA <= x"D0"; when x"CB5" => DATA <= x"DA"; when x"CB6" => DATA <= x"A4"; when x"CB7" => DATA <= x"C3"; when x"CB8" => DATA <= x"A6"; when x"CB9" => DATA <= x"EC"; when x"CBA" => DATA <= x"68"; when x"CBB" => DATA <= x"28"; when x"CBC" => DATA <= x"60"; when x"CBD" => DATA <= x"A2"; when x"CBE" => DATA <= x"00"; when x"CBF" => DATA <= x"AC"; when x"CC0" => DATA <= x"02"; when x"CC1" => DATA <= x"B0"; when x"CC2" => DATA <= x"E8"; when x"CC3" => DATA <= x"F0"; when x"CC4" => DATA <= x"07"; when x"CC5" => DATA <= x"20"; when x"CC6" => DATA <= x"CD"; when x"CC7" => DATA <= x"FC"; when x"CC8" => DATA <= x"F0"; when x"CC9" => DATA <= x"F8"; when x"CCA" => DATA <= x"E0"; when x"CCB" => DATA <= x"08"; when x"CCC" => DATA <= x"60"; when x"CCD" => DATA <= x"84"; when x"CCE" => DATA <= x"C5"; when x"CCF" => DATA <= x"AD"; when x"CD0" => DATA <= x"02"; when x"CD1" => DATA <= x"B0"; when x"CD2" => DATA <= x"A8"; when x"CD3" => DATA <= x"45"; when x"CD4" => DATA <= x"C5"; when x"CD5" => DATA <= x"29"; when x"CD6" => DATA <= x"20"; when x"CD7" => DATA <= x"60"; when x"CD8" => DATA <= x"A2"; when x"CD9" => DATA <= x"00"; when x"CDA" => DATA <= x"A9"; when x"CDB" => DATA <= x"10"; when x"CDC" => DATA <= x"2C"; when x"CDD" => DATA <= x"02"; when x"CDE" => DATA <= x"B0"; when x"CDF" => DATA <= x"F0"; when x"CE0" => DATA <= x"FB"; when x"CE1" => DATA <= x"2C"; when x"CE2" => DATA <= x"02"; when x"CE3" => DATA <= x"B0"; when x"CE4" => DATA <= x"D0"; when x"CE5" => DATA <= x"FB"; when x"CE6" => DATA <= x"CA"; when x"CE7" => DATA <= x"10"; when x"CE8" => DATA <= x"F3"; when x"CE9" => DATA <= x"60"; when x"CEA" => DATA <= x"C9"; when x"CEB" => DATA <= x"06"; when x"CEC" => DATA <= x"F0"; when x"CED" => DATA <= x"1D"; when x"CEE" => DATA <= x"C9"; when x"CEF" => DATA <= x"15"; when x"CF0" => DATA <= x"F0"; when x"CF1" => DATA <= x"1F"; when x"CF2" => DATA <= x"A4"; when x"CF3" => DATA <= x"E0"; when x"CF4" => DATA <= x"30"; when x"CF5" => DATA <= x"23"; when x"CF6" => DATA <= x"C9"; when x"CF7" => DATA <= x"1B"; when x"CF8" => DATA <= x"F0"; when x"CF9" => DATA <= x"11"; when x"CFA" => DATA <= x"C9"; when x"CFB" => DATA <= x"07"; when x"CFC" => DATA <= x"F0"; when x"CFD" => DATA <= x"1C"; when x"CFE" => DATA <= x"20"; when x"CFF" => DATA <= x"44"; when x"D00" => DATA <= x"FD"; when x"D01" => DATA <= x"A2"; when x"D02" => DATA <= x"0A"; when x"D03" => DATA <= x"20"; when x"D04" => DATA <= x"C5"; when x"D05" => DATA <= x"FE"; when x"D06" => DATA <= x"D0"; when x"D07" => DATA <= x"21"; when x"D08" => DATA <= x"4C"; when x"D09" => DATA <= x"B7"; when x"D0A" => DATA <= x"FE"; when x"D0B" => DATA <= x"18"; when x"D0C" => DATA <= x"A2"; when x"D0D" => DATA <= x"00"; when x"D0E" => DATA <= x"8E"; when x"D0F" => DATA <= x"00"; when x"D10" => DATA <= x"B0"; when x"D11" => DATA <= x"A2"; when x"D12" => DATA <= x"02"; when x"D13" => DATA <= x"08"; when x"D14" => DATA <= x"16"; when x"D15" => DATA <= x"DE"; when x"D16" => DATA <= x"28"; when x"D17" => DATA <= x"76"; when x"D18" => DATA <= x"DE"; when x"D19" => DATA <= x"60"; when x"D1A" => DATA <= x"A9"; when x"D1B" => DATA <= x"05"; when x"D1C" => DATA <= x"A8"; when x"D1D" => DATA <= x"8D"; when x"D1E" => DATA <= x"03"; when x"D1F" => DATA <= x"B0"; when x"D20" => DATA <= x"CA"; when x"D21" => DATA <= x"D0"; when x"D22" => DATA <= x"FD"; when x"D23" => DATA <= x"49"; when x"D24" => DATA <= x"01"; when x"D25" => DATA <= x"C8"; when x"D26" => DATA <= x"10"; when x"D27" => DATA <= x"F5"; when x"D28" => DATA <= x"60"; when x"D29" => DATA <= x"C9"; when x"D2A" => DATA <= x"20"; when x"D2B" => DATA <= x"90"; when x"D2C" => DATA <= x"17"; when x"D2D" => DATA <= x"69"; when x"D2E" => DATA <= x"1F"; when x"D2F" => DATA <= x"30"; when x"D30" => DATA <= x"02"; when x"D31" => DATA <= x"49"; when x"D32" => DATA <= x"60"; when x"D33" => DATA <= x"20"; when x"D34" => DATA <= x"6B"; when x"D35" => DATA <= x"FE"; when x"D36" => DATA <= x"91"; when x"D37" => DATA <= x"DE"; when x"D38" => DATA <= x"C8"; when x"D39" => DATA <= x"C0"; when x"D3A" => DATA <= x"20"; when x"D3B" => DATA <= x"90"; when x"D3C" => DATA <= x"05"; when x"D3D" => DATA <= x"20"; when x"D3E" => DATA <= x"EC"; when x"D3F" => DATA <= x"FD"; when x"D40" => DATA <= x"A0"; when x"D41" => DATA <= x"00"; when x"D42" => DATA <= x"84"; when x"D43" => DATA <= x"E0"; when x"D44" => DATA <= x"48"; when x"D45" => DATA <= x"20"; when x"D46" => DATA <= x"6B"; when x"D47" => DATA <= x"FE"; when x"D48" => DATA <= x"B1"; when x"D49" => DATA <= x"DE"; when x"D4A" => DATA <= x"45"; when x"D4B" => DATA <= x"E1"; when x"D4C" => DATA <= x"91"; when x"D4D" => DATA <= x"DE"; when x"D4E" => DATA <= x"68"; when x"D4F" => DATA <= x"60"; when x"D50" => DATA <= x"20"; when x"D51" => DATA <= x"35"; when x"D52" => DATA <= x"FE"; when x"D53" => DATA <= x"A9"; when x"D54" => DATA <= x"20"; when x"D55" => DATA <= x"20"; when x"D56" => DATA <= x"6B"; when x"D57" => DATA <= x"FE"; when x"D58" => DATA <= x"91"; when x"D59" => DATA <= x"DE"; when x"D5A" => DATA <= x"10"; when x"D5B" => DATA <= x"E6"; when x"D5C" => DATA <= x"20"; when x"D5D" => DATA <= x"35"; when x"D5E" => DATA <= x"FE"; when x"D5F" => DATA <= x"4C"; when x"D60" => DATA <= x"42"; when x"D61" => DATA <= x"FD"; when x"D62" => DATA <= x"20"; when x"D63" => DATA <= x"EC"; when x"D64" => DATA <= x"FD"; when x"D65" => DATA <= x"A4"; when x"D66" => DATA <= x"E0"; when x"D67" => DATA <= x"10"; when x"D68" => DATA <= x"D9"; when x"D69" => DATA <= x"A0"; when x"D6A" => DATA <= x"80"; when x"D6B" => DATA <= x"84"; when x"D6C" => DATA <= x"E1"; when x"D6D" => DATA <= x"A0"; when x"D6E" => DATA <= x"00"; when x"D6F" => DATA <= x"8C"; when x"D70" => DATA <= x"00"; when x"D71" => DATA <= x"B0"; when x"D72" => DATA <= x"A9"; when x"D73" => DATA <= x"20"; when x"D74" => DATA <= x"99"; when x"D75" => DATA <= x"00"; when x"D76" => DATA <= x"80"; when x"D77" => DATA <= x"99"; when x"D78" => DATA <= x"00"; when x"D79" => DATA <= x"81"; when x"D7A" => DATA <= x"C8"; when x"D7B" => DATA <= x"D0"; when x"D7C" => DATA <= x"F7"; when x"D7D" => DATA <= x"A9"; when x"D7E" => DATA <= x"80"; when x"D7F" => DATA <= x"A0"; when x"D80" => DATA <= x"00"; when x"D81" => DATA <= x"85"; when x"D82" => DATA <= x"DF"; when x"D83" => DATA <= x"84"; when x"D84" => DATA <= x"DE"; when x"D85" => DATA <= x"F0"; when x"D86" => DATA <= x"BB"; when x"D87" => DATA <= x"20"; when x"D88" => DATA <= x"3A"; when x"D89" => DATA <= x"FE"; when x"D8A" => DATA <= x"4C"; when x"D8B" => DATA <= x"42"; when x"D8C" => DATA <= x"FD"; when x"D8D" => DATA <= x"18"; when x"D8E" => DATA <= x"A9"; when x"D8F" => DATA <= x"10"; when x"D90" => DATA <= x"85"; when x"D91" => DATA <= x"E6"; when x"D92" => DATA <= x"A2"; when x"D93" => DATA <= x"08"; when x"D94" => DATA <= x"20"; when x"D95" => DATA <= x"13"; when x"D96" => DATA <= x"FD"; when x"D97" => DATA <= x"4C"; when x"D98" => DATA <= x"44"; when x"D99" => DATA <= x"FD"; when x"D9A" => DATA <= x"A5"; when x"D9B" => DATA <= x"E7"; when x"D9C" => DATA <= x"49"; when x"D9D" => DATA <= x"60"; when x"D9E" => DATA <= x"85"; when x"D9F" => DATA <= x"E7"; when x"DA0" => DATA <= x"B0"; when x"DA1" => DATA <= x"09"; when x"DA2" => DATA <= x"29"; when x"DA3" => DATA <= x"05"; when x"DA4" => DATA <= x"2E"; when x"DA5" => DATA <= x"01"; when x"DA6" => DATA <= x"B0"; when x"DA7" => DATA <= x"2A"; when x"DA8" => DATA <= x"20"; when x"DA9" => DATA <= x"EA"; when x"DAA" => DATA <= x"FC"; when x"DAB" => DATA <= x"4C"; when x"DAC" => DATA <= x"9A"; when x"DAD" => DATA <= x"FE"; when x"DAE" => DATA <= x"A4"; when x"DAF" => DATA <= x"E0"; when x"DB0" => DATA <= x"20"; when x"DB1" => DATA <= x"6B"; when x"DB2" => DATA <= x"FE"; when x"DB3" => DATA <= x"B1"; when x"DB4" => DATA <= x"DE"; when x"DB5" => DATA <= x"45"; when x"DB6" => DATA <= x"E1"; when x"DB7" => DATA <= x"30"; when x"DB8" => DATA <= x"02"; when x"DB9" => DATA <= x"49"; when x"DBA" => DATA <= x"60"; when x"DBB" => DATA <= x"E9"; when x"DBC" => DATA <= x"20"; when x"DBD" => DATA <= x"4C"; when x"DBE" => DATA <= x"E9"; when x"DBF" => DATA <= x"FD"; when x"DC0" => DATA <= x"A9"; when x"DC1" => DATA <= x"5F"; when x"DC2" => DATA <= x"49"; when x"DC3" => DATA <= x"20"; when x"DC4" => DATA <= x"D0"; when x"DC5" => DATA <= x"23"; when x"DC6" => DATA <= x"45"; when x"DC7" => DATA <= x"E7"; when x"DC8" => DATA <= x"2C"; when x"DC9" => DATA <= x"01"; when x"DCA" => DATA <= x"B0"; when x"DCB" => DATA <= x"30"; when x"DCC" => DATA <= x"02"; when x"DCD" => DATA <= x"49"; when x"DCE" => DATA <= x"60"; when x"DCF" => DATA <= x"4C"; when x"DD0" => DATA <= x"DF"; when x"DD1" => DATA <= x"FD"; when x"DD2" => DATA <= x"69"; when x"DD3" => DATA <= x"39"; when x"DD4" => DATA <= x"90"; when x"DD5" => DATA <= x"F2"; when x"DD6" => DATA <= x"49"; when x"DD7" => DATA <= x"10"; when x"DD8" => DATA <= x"2C"; when x"DD9" => DATA <= x"01"; when x"DDA" => DATA <= x"B0"; when x"DDB" => DATA <= x"30"; when x"DDC" => DATA <= x"02"; when x"DDD" => DATA <= x"49"; when x"DDE" => DATA <= x"10"; when x"DDF" => DATA <= x"18"; when x"DE0" => DATA <= x"69"; when x"DE1" => DATA <= x"20"; when x"DE2" => DATA <= x"2C"; when x"DE3" => DATA <= x"01"; when x"DE4" => DATA <= x"B0"; when x"DE5" => DATA <= x"70"; when x"DE6" => DATA <= x"02"; when x"DE7" => DATA <= x"29"; when x"DE8" => DATA <= x"1F"; when x"DE9" => DATA <= x"4C"; when x"DEA" => DATA <= x"60"; when x"DEB" => DATA <= x"FE"; when x"DEC" => DATA <= x"A5"; when x"DED" => DATA <= x"DE"; when x"DEE" => DATA <= x"A4"; when x"DEF" => DATA <= x"DF"; when x"DF0" => DATA <= x"C0"; when x"DF1" => DATA <= x"81"; when x"DF2" => DATA <= x"90"; when x"DF3" => DATA <= x"38"; when x"DF4" => DATA <= x"C9"; when x"DF5" => DATA <= x"E0"; when x"DF6" => DATA <= x"90"; when x"DF7" => DATA <= x"34"; when x"DF8" => DATA <= x"A4"; when x"DF9" => DATA <= x"E6"; when x"DFA" => DATA <= x"30"; when x"DFB" => DATA <= x"0C"; when x"DFC" => DATA <= x"88"; when x"DFD" => DATA <= x"D0"; when x"DFE" => DATA <= x"07"; when x"DFF" => DATA <= x"20"; when x"E00" => DATA <= x"71"; when x"E01" => DATA <= x"FE"; when x"E02" => DATA <= x"B0"; when x"E03" => DATA <= x"FB"; when x"E04" => DATA <= x"A0"; when x"E05" => DATA <= x"10"; when x"E06" => DATA <= x"84"; when x"E07" => DATA <= x"E6"; when x"E08" => DATA <= x"A0"; when x"E09" => DATA <= x"20"; when x"E0A" => DATA <= x"20"; when x"E0B" => DATA <= x"66"; when x"E0C" => DATA <= x"FE"; when x"E0D" => DATA <= x"B9"; when x"E0E" => DATA <= x"00"; when x"E0F" => DATA <= x"80"; when x"E10" => DATA <= x"99"; when x"E11" => DATA <= x"E0"; when x"E12" => DATA <= x"7F"; when x"E13" => DATA <= x"C8"; when x"E14" => DATA <= x"D0"; when x"E15" => DATA <= x"F7"; when x"E16" => DATA <= x"20"; when x"E17" => DATA <= x"6B"; when x"E18" => DATA <= x"FE"; when x"E19" => DATA <= x"B9"; when x"E1A" => DATA <= x"00"; when x"E1B" => DATA <= x"81"; when x"E1C" => DATA <= x"99"; when x"E1D" => DATA <= x"E0"; when x"E1E" => DATA <= x"80"; when x"E1F" => DATA <= x"C8"; when x"E20" => DATA <= x"D0"; when x"E21" => DATA <= x"F7"; when x"E22" => DATA <= x"A0"; when x"E23" => DATA <= x"1F"; when x"E24" => DATA <= x"A9"; when x"E25" => DATA <= x"20"; when x"E26" => DATA <= x"91"; when x"E27" => DATA <= x"DE"; when x"E28" => DATA <= x"88"; when x"E29" => DATA <= x"10"; when x"E2A" => DATA <= x"FB"; when x"E2B" => DATA <= x"60"; when x"E2C" => DATA <= x"69"; when x"E2D" => DATA <= x"20"; when x"E2E" => DATA <= x"85"; when x"E2F" => DATA <= x"DE"; when x"E30" => DATA <= x"D0"; when x"E31" => DATA <= x"02"; when x"E32" => DATA <= x"E6"; when x"E33" => DATA <= x"DF"; when x"E34" => DATA <= x"60"; when x"E35" => DATA <= x"88"; when x"E36" => DATA <= x"10"; when x"E37" => DATA <= x"19"; when x"E38" => DATA <= x"A0"; when x"E39" => DATA <= x"1F"; when x"E3A" => DATA <= x"A5"; when x"E3B" => DATA <= x"DE"; when x"E3C" => DATA <= x"D0"; when x"E3D" => DATA <= x"0B"; when x"E3E" => DATA <= x"A6"; when x"E3F" => DATA <= x"DF"; when x"E40" => DATA <= x"E0"; when x"E41" => DATA <= x"80"; when x"E42" => DATA <= x"D0"; when x"E43" => DATA <= x"05"; when x"E44" => DATA <= x"68"; when x"E45" => DATA <= x"68"; when x"E46" => DATA <= x"4C"; when x"E47" => DATA <= x"65"; when x"E48" => DATA <= x"FD"; when x"E49" => DATA <= x"E9"; when x"E4A" => DATA <= x"20"; when x"E4B" => DATA <= x"85"; when x"E4C" => DATA <= x"DE"; when x"E4D" => DATA <= x"B0"; when x"E4E" => DATA <= x"02"; when x"E4F" => DATA <= x"C6"; when x"E50" => DATA <= x"DF"; when x"E51" => DATA <= x"60"; when x"E52" => DATA <= x"20"; when x"E53" => DATA <= x"FB"; when x"E54" => DATA <= x"FE"; when x"E55" => DATA <= x"08"; when x"E56" => DATA <= x"48"; when x"E57" => DATA <= x"D8"; when x"E58" => DATA <= x"84"; when x"E59" => DATA <= x"E5"; when x"E5A" => DATA <= x"86"; when x"E5B" => DATA <= x"E4"; when x"E5C" => DATA <= x"20"; when x"E5D" => DATA <= x"EA"; when x"E5E" => DATA <= x"FC"; when x"E5F" => DATA <= x"68"; when x"E60" => DATA <= x"A6"; when x"E61" => DATA <= x"E4"; when x"E62" => DATA <= x"A4"; when x"E63" => DATA <= x"E5"; when x"E64" => DATA <= x"28"; when x"E65" => DATA <= x"60"; when x"E66" => DATA <= x"2C"; when x"E67" => DATA <= x"02"; when x"E68" => DATA <= x"B0"; when x"E69" => DATA <= x"10"; when x"E6A" => DATA <= x"FB"; when x"E6B" => DATA <= x"2C"; when x"E6C" => DATA <= x"02"; when x"E6D" => DATA <= x"B0"; when x"E6E" => DATA <= x"30"; when x"E6F" => DATA <= x"FB"; when x"E70" => DATA <= x"60"; when x"E71" => DATA <= x"A0"; when x"E72" => DATA <= x"3B"; when x"E73" => DATA <= x"18"; when x"E74" => DATA <= x"A9"; when x"E75" => DATA <= x"20"; when x"E76" => DATA <= x"A2"; when x"E77" => DATA <= x"0A"; when x"E78" => DATA <= x"2C"; when x"E79" => DATA <= x"01"; when x"E7A" => DATA <= x"B0"; when x"E7B" => DATA <= x"F0"; when x"E7C" => DATA <= x"08"; when x"E7D" => DATA <= x"EE"; when x"E7E" => DATA <= x"00"; when x"E7F" => DATA <= x"B0"; when x"E80" => DATA <= x"88"; when x"E81" => DATA <= x"CA"; when x"E82" => DATA <= x"D0"; when x"E83" => DATA <= x"F4"; when x"E84" => DATA <= x"4A"; when x"E85" => DATA <= x"08"; when x"E86" => DATA <= x"48"; when x"E87" => DATA <= x"AD"; when x"E88" => DATA <= x"00"; when x"E89" => DATA <= x"B0"; when x"E8A" => DATA <= x"29"; when x"E8B" => DATA <= x"F0"; when x"E8C" => DATA <= x"8D"; when x"E8D" => DATA <= x"00"; when x"E8E" => DATA <= x"B0"; when x"E8F" => DATA <= x"68"; when x"E90" => DATA <= x"28"; when x"E91" => DATA <= x"D0"; when x"E92" => DATA <= x"E3"; when x"E93" => DATA <= x"60"; when x"E94" => DATA <= x"08"; when x"E95" => DATA <= x"D8"; when x"E96" => DATA <= x"86"; when x"E97" => DATA <= x"E4"; when x"E98" => DATA <= x"84"; when x"E99" => DATA <= x"E5"; when x"E9A" => DATA <= x"2C"; when x"E9B" => DATA <= x"02"; when x"E9C" => DATA <= x"B0"; when x"E9D" => DATA <= x"50"; when x"E9E" => DATA <= x"05"; when x"E9F" => DATA <= x"20"; when x"EA0" => DATA <= x"71"; when x"EA1" => DATA <= x"FE"; when x"EA2" => DATA <= x"90"; when x"EA3" => DATA <= x"F6"; when x"EA4" => DATA <= x"20"; when x"EA5" => DATA <= x"8A"; when x"EA6" => DATA <= x"FB"; when x"EA7" => DATA <= x"20"; when x"EA8" => DATA <= x"71"; when x"EA9" => DATA <= x"FE"; when x"EAA" => DATA <= x"B0"; when x"EAB" => DATA <= x"FB"; when x"EAC" => DATA <= x"20"; when x"EAD" => DATA <= x"71"; when x"EAE" => DATA <= x"FE"; when x"EAF" => DATA <= x"B0"; when x"EB0" => DATA <= x"F6"; when x"EB1" => DATA <= x"98"; when x"EB2" => DATA <= x"A2"; when x"EB3" => DATA <= x"17"; when x"EB4" => DATA <= x"20"; when x"EB5" => DATA <= x"C5"; when x"EB6" => DATA <= x"FE"; when x"EB7" => DATA <= x"BD"; when x"EB8" => DATA <= x"E3"; when x"EB9" => DATA <= x"FE"; when x"EBA" => DATA <= x"85"; when x"EBB" => DATA <= x"E2"; when x"EBC" => DATA <= x"A9"; when x"EBD" => DATA <= x"FD"; when x"EBE" => DATA <= x"85"; when x"EBF" => DATA <= x"E3"; when x"EC0" => DATA <= x"98"; when x"EC1" => DATA <= x"6C"; when x"EC2" => DATA <= x"E2"; when x"EC3" => DATA <= x"00"; when x"EC4" => DATA <= x"CA"; when x"EC5" => DATA <= x"DD"; when x"EC6" => DATA <= x"CB"; when x"EC7" => DATA <= x"FE"; when x"EC8" => DATA <= x"90"; when x"EC9" => DATA <= x"FA"; when x"ECA" => DATA <= x"60"; when x"ECB" => DATA <= x"00"; when x"ECC" => DATA <= x"08"; when x"ECD" => DATA <= x"09"; when x"ECE" => DATA <= x"0A"; when x"ECF" => DATA <= x"0B"; when x"ED0" => DATA <= x"0C"; when x"ED1" => DATA <= x"0D"; when x"ED2" => DATA <= x"0E"; when x"ED3" => DATA <= x"0F"; when x"ED4" => DATA <= x"1E"; when x"ED5" => DATA <= x"7F"; when x"ED6" => DATA <= x"00"; when x"ED7" => DATA <= x"01"; when x"ED8" => DATA <= x"05"; when x"ED9" => DATA <= x"06"; when x"EDA" => DATA <= x"08"; when x"EDB" => DATA <= x"0E"; when x"EDC" => DATA <= x"0F"; when x"EDD" => DATA <= x"10"; when x"EDE" => DATA <= x"11"; when x"EDF" => DATA <= x"1C"; when x"EE0" => DATA <= x"20"; when x"EE1" => DATA <= x"21"; when x"EE2" => DATA <= x"3B"; when x"EE3" => DATA <= x"44"; when x"EE4" => DATA <= x"5C"; when x"EE5" => DATA <= x"38"; when x"EE6" => DATA <= x"62"; when x"EE7" => DATA <= x"87"; when x"EE8" => DATA <= x"69"; when x"EE9" => DATA <= x"40"; when x"EEA" => DATA <= x"8D"; when x"EEB" => DATA <= x"92"; when x"EEC" => DATA <= x"7D"; when x"EED" => DATA <= x"50"; when x"EEE" => DATA <= x"DF"; when x"EEF" => DATA <= x"D2"; when x"EF0" => DATA <= x"9A"; when x"EF1" => DATA <= x"A2"; when x"EF2" => DATA <= x"E2"; when x"EF3" => DATA <= x"AE"; when x"EF4" => DATA <= x"C0"; when x"EF5" => DATA <= x"DF"; when x"EF6" => DATA <= x"D8"; when x"EF7" => DATA <= x"D6"; when x"EF8" => DATA <= x"C8"; when x"EF9" => DATA <= x"C6"; when x"EFA" => DATA <= x"C2"; when x"EFB" => DATA <= x"48"; when x"EFC" => DATA <= x"C9"; when x"EFD" => DATA <= x"02"; when x"EFE" => DATA <= x"F0"; when x"EFF" => DATA <= x"27"; when x"F00" => DATA <= x"C9"; when x"F01" => DATA <= x"03"; when x"F02" => DATA <= x"F0"; when x"F03" => DATA <= x"34"; when x"F04" => DATA <= x"C5"; when x"F05" => DATA <= x"FE"; when x"F06" => DATA <= x"F0"; when x"F07" => DATA <= x"2E"; when x"F08" => DATA <= x"AD"; when x"F09" => DATA <= x"0C"; when x"F0A" => DATA <= x"B8"; when x"F0B" => DATA <= x"29"; when x"F0C" => DATA <= x"0E"; when x"F0D" => DATA <= x"F0"; when x"F0E" => DATA <= x"27"; when x"F0F" => DATA <= x"68"; when x"F10" => DATA <= x"2C"; when x"F11" => DATA <= x"01"; when x"F12" => DATA <= x"B8"; when x"F13" => DATA <= x"30"; when x"F14" => DATA <= x"FB"; when x"F15" => DATA <= x"8D"; when x"F16" => DATA <= x"01"; when x"F17" => DATA <= x"B8"; when x"F18" => DATA <= x"48"; when x"F19" => DATA <= x"AD"; when x"F1A" => DATA <= x"0C"; when x"F1B" => DATA <= x"B8"; when x"F1C" => DATA <= x"29"; when x"F1D" => DATA <= x"F0"; when x"F1E" => DATA <= x"09"; when x"F1F" => DATA <= x"0C"; when x"F20" => DATA <= x"8D"; when x"F21" => DATA <= x"0C"; when x"F22" => DATA <= x"B8"; when x"F23" => DATA <= x"09"; when x"F24" => DATA <= x"02"; when x"F25" => DATA <= x"D0"; when x"F26" => DATA <= x"0C"; when x"F27" => DATA <= x"A9"; when x"F28" => DATA <= x"7F"; when x"F29" => DATA <= x"8D"; when x"F2A" => DATA <= x"03"; when x"F2B" => DATA <= x"B8"; when x"F2C" => DATA <= x"AD"; when x"F2D" => DATA <= x"0C"; when x"F2E" => DATA <= x"B8"; when x"F2F" => DATA <= x"29"; when x"F30" => DATA <= x"F0"; when x"F31" => DATA <= x"09"; when x"F32" => DATA <= x"0E"; when x"F33" => DATA <= x"8D"; when x"F34" => DATA <= x"0C"; when x"F35" => DATA <= x"B8"; when x"F36" => DATA <= x"68"; when x"F37" => DATA <= x"60"; when x"F38" => DATA <= x"AD"; when x"F39" => DATA <= x"0C"; when x"F3A" => DATA <= x"B8"; when x"F3B" => DATA <= x"29"; when x"F3C" => DATA <= x"F0"; when x"F3D" => DATA <= x"B0"; when x"F3E" => DATA <= x"F4"; when x"F3F" => DATA <= x"A2"; when x"F40" => DATA <= x"17"; when x"F41" => DATA <= x"BD"; when x"F42" => DATA <= x"9A"; when x"F43" => DATA <= x"FF"; when x"F44" => DATA <= x"9D"; when x"F45" => DATA <= x"04"; when x"F46" => DATA <= x"02"; when x"F47" => DATA <= x"CA"; when x"F48" => DATA <= x"10"; when x"F49" => DATA <= x"F7"; when x"F4A" => DATA <= x"9A"; when x"F4B" => DATA <= x"8A"; when x"F4C" => DATA <= x"E8"; when x"F4D" => DATA <= x"86"; when x"F4E" => DATA <= x"EA"; when x"F4F" => DATA <= x"86"; when x"F50" => DATA <= x"E1"; when x"F51" => DATA <= x"86"; when x"F52" => DATA <= x"E7"; when x"F53" => DATA <= x"A2"; when x"F54" => DATA <= x"33"; when x"F55" => DATA <= x"9D"; when x"F56" => DATA <= x"EB"; when x"F57" => DATA <= x"02"; when x"F58" => DATA <= x"CA"; when x"F59" => DATA <= x"10"; when x"F5A" => DATA <= x"FA"; when x"F5B" => DATA <= x"A9"; when x"F5C" => DATA <= x"0A"; when x"F5D" => DATA <= x"85"; when x"F5E" => DATA <= x"FE"; when x"F5F" => DATA <= x"A9"; when x"F60" => DATA <= x"8A"; when x"F61" => DATA <= x"8D"; when x"F62" => DATA <= x"03"; when x"F63" => DATA <= x"B0"; when x"F64" => DATA <= x"A9"; when x"F65" => DATA <= x"07"; when x"F66" => DATA <= x"8D"; when x"F67" => DATA <= x"02"; when x"F68" => DATA <= x"B0"; when x"F69" => DATA <= x"20"; when x"F6A" => DATA <= x"D1"; when x"F6B" => DATA <= x"F7"; when x"F6C" => DATA <= x"06"; when x"F6D" => DATA <= x"0C"; when x"F6E" => DATA <= x"0F"; when x"F6F" => DATA <= x"41"; when x"F70" => DATA <= x"43"; when x"F71" => DATA <= x"4F"; when x"F72" => DATA <= x"52"; when x"F73" => DATA <= x"4E"; when x"F74" => DATA <= x"20"; when x"F75" => DATA <= x"41"; when x"F76" => DATA <= x"54"; when x"F77" => DATA <= x"4F"; when x"F78" => DATA <= x"4D"; when x"F79" => DATA <= x"0A"; when x"F7A" => DATA <= x"0A"; when x"F7B" => DATA <= x"0D"; when x"F7C" => DATA <= x"A9"; when x"F7D" => DATA <= x"82"; when x"F7E" => DATA <= x"85"; when x"F7F" => DATA <= x"12"; when x"F80" => DATA <= x"58"; when x"F81" => DATA <= x"A9"; when x"F82" => DATA <= x"55"; when x"F83" => DATA <= x"8D"; when x"F84" => DATA <= x"01"; when x"F85" => DATA <= x"29"; when x"F86" => DATA <= x"CD"; when x"F87" => DATA <= x"01"; when x"F88" => DATA <= x"29"; when x"F89" => DATA <= x"D0"; when x"F8A" => DATA <= x"0C"; when x"F8B" => DATA <= x"0A"; when x"F8C" => DATA <= x"8D"; when x"F8D" => DATA <= x"01"; when x"F8E" => DATA <= x"29"; when x"F8F" => DATA <= x"CD"; when x"F90" => DATA <= x"01"; when x"F91" => DATA <= x"29"; when x"F92" => DATA <= x"D0"; when x"F93" => DATA <= x"03"; when x"F94" => DATA <= x"4C"; when x"F95" => DATA <= x"00"; when x"F96" => DATA <= x"E0"; when x"F97" => DATA <= x"4C"; when x"F98" => DATA <= x"B6"; when x"F99" => DATA <= x"C2"; when x"F9A" => DATA <= x"00"; when x"F9B" => DATA <= x"A0"; when x"F9C" => DATA <= x"EF"; when x"F9D" => DATA <= x"F8"; when x"F9E" => DATA <= x"52"; when x"F9F" => DATA <= x"FE"; when x"FA0" => DATA <= x"94"; when x"FA1" => DATA <= x"FE"; when x"FA2" => DATA <= x"6E"; when x"FA3" => DATA <= x"F9"; when x"FA4" => DATA <= x"E5"; when x"FA5" => DATA <= x"FA"; when x"FA6" => DATA <= x"AC"; when x"FA7" => DATA <= x"C2"; when x"FA8" => DATA <= x"AC"; when x"FA9" => DATA <= x"C2"; when x"FAA" => DATA <= x"EE"; when x"FAB" => DATA <= x"FB"; when x"FAC" => DATA <= x"7C"; when x"FAD" => DATA <= x"FC"; when x"FAE" => DATA <= x"38"; when x"FAF" => DATA <= x"FC"; when x"FB0" => DATA <= x"78"; when x"FB1" => DATA <= x"C2"; when x"FB2" => DATA <= x"85"; when x"FB3" => DATA <= x"FF"; when x"FB4" => DATA <= x"68"; when x"FB5" => DATA <= x"48"; when x"FB6" => DATA <= x"29"; when x"FB7" => DATA <= x"10"; when x"FB8" => DATA <= x"D0"; when x"FB9" => DATA <= x"06"; when x"FBA" => DATA <= x"A5"; when x"FBB" => DATA <= x"FF"; when x"FBC" => DATA <= x"48"; when x"FBD" => DATA <= x"6C"; when x"FBE" => DATA <= x"04"; when x"FBF" => DATA <= x"02"; when x"FC0" => DATA <= x"A5"; when x"FC1" => DATA <= x"FF"; when x"FC2" => DATA <= x"28"; when x"FC3" => DATA <= x"08"; when x"FC4" => DATA <= x"6C"; when x"FC5" => DATA <= x"02"; when x"FC6" => DATA <= x"02"; when x"FC7" => DATA <= x"48"; when x"FC8" => DATA <= x"6C"; when x"FC9" => DATA <= x"00"; when x"FCA" => DATA <= x"02"; when x"FCB" => DATA <= x"6C"; when x"FCC" => DATA <= x"1A"; when x"FCD" => DATA <= x"02"; when x"FCE" => DATA <= x"6C"; when x"FCF" => DATA <= x"18"; when x"FD0" => DATA <= x"02"; when x"FD1" => DATA <= x"6C"; when x"FD2" => DATA <= x"16"; when x"FD3" => DATA <= x"02"; when x"FD4" => DATA <= x"6C"; when x"FD5" => DATA <= x"14"; when x"FD6" => DATA <= x"02"; when x"FD7" => DATA <= x"6C"; when x"FD8" => DATA <= x"12"; when x"FD9" => DATA <= x"02"; when x"FDA" => DATA <= x"6C"; when x"FDB" => DATA <= x"10"; when x"FDC" => DATA <= x"02"; when x"FDD" => DATA <= x"6C"; when x"FDE" => DATA <= x"0E"; when x"FDF" => DATA <= x"02"; when x"FE0" => DATA <= x"6C"; when x"FE1" => DATA <= x"0C"; when x"FE2" => DATA <= x"02"; when x"FE3" => DATA <= x"6C"; when x"FE4" => DATA <= x"0A"; when x"FE5" => DATA <= x"02"; when x"FE6" => DATA <= x"20"; when x"FE7" => DATA <= x"E3"; when x"FE8" => DATA <= x"FF"; when x"FE9" => DATA <= x"C9"; when x"FEA" => DATA <= x"0D"; when x"FEB" => DATA <= x"D0"; when x"FEC" => DATA <= x"07"; when x"FED" => DATA <= x"A9"; when x"FEE" => DATA <= x"0A"; when x"FEF" => DATA <= x"20"; when x"FF0" => DATA <= x"F4"; when x"FF1" => DATA <= x"FF"; when x"FF2" => DATA <= x"A9"; when x"FF3" => DATA <= x"0D"; when x"FF4" => DATA <= x"6C"; when x"FF5" => DATA <= x"08"; when x"FF6" => DATA <= x"02"; when x"FF7" => DATA <= x"6C"; when x"FF8" => DATA <= x"06"; when x"FF9" => DATA <= x"02"; when x"FFA" => DATA <= x"C7"; when x"FFB" => DATA <= x"FF"; when x"FFC" => DATA <= x"3F"; when x"FFD" => DATA <= x"FF"; when x"FFE" => DATA <= x"B2"; when x"FFF" => DATA <= x"FF"; when others => DATA <= (others => '0'); end case; end process; end RTL;
apache-2.0
d02583e9e29a1200c58d2fa4c71ff67e
0.358261
2.919133
false
false
false
false
GSimas/EEL5105
PROJETO-EEL5105/Projeto/Conta_asc.vhd
1
912
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; -- Contador ascendente de posicao entity Conta_asc is port( EN_TIME, CLK, RST: in std_logic; SPEED: in std_logic_vector(2 downto 0); CNT_OUT: out std_logic_vector(9 downto 0) ); end Conta_asc; architecture bhv of Conta_asc is signal contador1: std_logic_vector(4 downto 0); signal contador2: std_logic_vector(4 downto 0); signal speed_sig: std_logic := SPEED(0) or SPEED(1) or SPEED(2); begin process(CLK, RST, EN_TIME, SPEED) begin if RST = '0' then contador1 <= (others => '0'); contador2 <= (others => '0'); elsif rising_edge(CLK) and EN_TIME = '1' and speed_sig = '1' then contador2 <= contador2 + '1'; if contador2 = "01111" then contador1 <= contador1 + '1'; contador2 <= (others => '0'); end if; end if; end process; CNT_OUT <= contador1 & contador2; end bhv;
mit
036555c36d804c0df4bb62ef70a22746
0.644737
2.858934
false
false
false
false
hoglet67/AtomFpga
src/common/AVR8/CommonPacks/AVRuCPackage.vhd
3
10,818
-- ***************************************************************************************** -- AVR constants and type declarations -- Version 1.0A(Special version for the JTAG OCD) -- Modified 05.05.2004 -- Designed by Ruslan Lepetenok -- ***************************************************************************************** library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use WORK.SynthCtrlPack.all; package AVRuCPackage is -- Old package type ext_mux_din_type is array(0 to CExtMuxInSize-1) of std_logic_vector(7 downto 0); subtype ext_mux_en_type is std_logic_vector(0 to CExtMuxInSize-1); -- End of old package constant IOAdrWidth : positive := 16; type AVRIOAdr_Type is array(0 to 63) of std_logic_vector(IOAdrWidth-1 downto 0); constant CAVRIOAdr : AVRIOAdr_Type :=("0000000000000000","0000000000000001","0000000000000010","0000000000000011", "0000000000000100","0000000000000101","0000000000000110","0000000000000111", "0000000000001000","0000000000001001","0000000000001010","0000000000001011", "0000000000001100","0000000000001101","0000000000001110","0000000000001111", "0000000000010000","0000000000010001","0000000000010010","0000000000010011", "0000000000010100","0000000000010101","0000000000010110","0000000000010111", "0000000000011000","0000000000011001","0000000000011010","0000000000011011", "0000000000011100","0000000000011101","0000000000011110","0000000000011111", "0000000000100000","0000000000100001","0000000000100010","0000000000100011", "0000000000100100","0000000000100101","0000000000100110","0000000000100111", "0000000000101000","0000000000101001","0000000000101010","0000000000101011", "0000000000101100","0000000000101101","0000000000101110","0000000000101111", "0000000000110000","0000000000110001","0000000000110010","0000000000110011", "0000000000110100","0000000000110101","0000000000110110","0000000000110111", "0000000000111000","0000000000111001","0000000000111010","0000000000111011", "0000000000111100","0000000000111101","0000000000111110","0000000000111111"); -- I/O port addresses -- I/O register file constant RAMPZ_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#3B#); constant SPL_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#3D#); constant SPH_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#3E#); constant SREG_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#3F#); -- End of I/O register file -- UART constant UDR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#0C#); constant UBRR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#09#); constant USR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#0B#); constant UCR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#0A#); -- End of UART -- Timer/Counter constant TCCR0_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#33#); constant TCCR1A_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#2F#); constant TCCR1B_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#2E#); constant TCCR2_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#25#); constant ASSR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#30#); constant TIMSK_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#37#); constant TIFR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#36#); constant TCNT0_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#32#); constant TCNT2_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#24#); constant OCR0_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#31#); constant OCR2_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#23#); constant TCNT1H_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#2D#); constant TCNT1L_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#2C#); constant OCR1AH_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#2B#); constant OCR1AL_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#2A#); constant OCR1BH_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#29#); constant OCR1BL_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#28#); constant ICR1AH_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#27#); constant ICR1AL_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#26#); -- End of Timer/Counter -- Service module constant MCUCR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#35#); constant EIMSK_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#39#); constant EIFR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#38#); constant EICR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#3A#); constant MCUSR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#34#); constant XDIV_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#3C#); -- End of service module -- EEPROM constant EEARH_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#1F#); constant EEARL_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#1E#); constant EEDR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#1D#); constant EECR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#1C#); -- End of EEPROM -- SPI constant SPDR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#0F#); constant SPSR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#0E#); constant SPCR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#0D#); -- End of SPI -- PORTA addresses constant PORTA_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#1B#); constant DDRA_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#1A#); constant PINA_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#19#); -- PORTB addresses constant PORTB_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#18#); constant DDRB_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#17#); constant PINB_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#16#); -- PORTC addresses constant PORTC_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#15#); constant DDRC_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#14#); constant PINC_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#13#); -- PORTD addresses constant PORTD_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#12#); constant DDRD_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#11#); constant PIND_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#10#); -- PORTE addresses constant PORTE_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#03#); constant DDRE_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#02#); constant PINE_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#01#); -- PORTF addresses constant PORTF_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#07#); constant DDRF_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#08#); constant PINF_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#00#); -- ******************** Parallel port address table ************************************** constant CMaxNumOfPPort : positive := 6; type PPortAdrTbl_Type is record Port_Adr : std_logic_vector(IOAdrWidth-1 downto 0); DDR_Adr : std_logic_vector(IOAdrWidth-1 downto 0); Pin_Adr : std_logic_vector(IOAdrWidth-1 downto 0); end record; type PPortAdrTblArray_Type is array (0 to CMaxNumOfPPort-1) of PPortAdrTbl_Type; constant PPortAdrArray : PPortAdrTblArray_Type := ((PORTA_Address,DDRA_Address,PINA_Address), -- PORTA (PORTB_Address,DDRB_Address,PINB_Address), -- PORTB (PORTC_Address,DDRC_Address,PINC_Address), -- PORTC (PORTD_Address,DDRD_Address,PIND_Address), -- PORTD (PORTE_Address,DDRE_Address,PINE_Address), -- PORTE (PORTF_Address,DDRF_Address,PINF_Address)); -- PORTF -- *************************************************************************************** -- Analog to digital converter constant ADCL_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#04#); constant ADCH_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#05#); constant ADCSR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#06#); constant ADMUX_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#07#); -- Analog comparator constant ACSR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#08#); -- Watchdog constant WDTCR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#21#); -- JTAG OCDR (ATmega128) constant OCDR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#22#); -- JTAG OCDR (ATmega16) --constant OCDR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#31#); -- *************************************************************************************** -- Function declaration function LOG2(Number : positive) return natural; end AVRuCPackage; package body AVRuCPackage is -- Functions function LOG2(Number : positive) return natural is variable Temp : positive; begin Temp := 1; if Number>1 then for i in 1 to integer'high loop Temp := 2*Temp; if Temp>=Number then return i; end if; end loop; end if; return 0; end LOG2; -- End of functions end AVRuCPackage;
apache-2.0
53d108dc8208121d336aa03ec2d139d0
0.639767
3.426671
false
false
false
false
hoglet67/AtomFpga
src/common/AVR8/MemArbAndMux/MemAccessCtrlPack.vhd
4
1,154
-- ***************************************************************************************** -- -- Version 0.14 -- Modified 02.08.2005 -- Designed by Ruslan Lepetenok -- ***************************************************************************************** library IEEE; use IEEE.std_logic_1164.all; package MemAccessCtrlPack is constant CNumOfBusMasters : positive := 3; constant CNumOfSlaves : positive := 2; constant CUseRAMSel : boolean := FALSE; -- Masters type MastOutBus_Type is record ramadr : std_logic_vector(15 downto 0); dout : std_logic_vector(7 downto 0); ramre : std_logic; ramwe : std_logic; end record; type MastersOutBus_Type is array(CNumOfBusMasters-1 downto 0) of MastOutBus_Type; -- Slave type SlvOutBus_Type is record dout : std_logic_vector(7 downto 0); out_en : std_logic; end record; type SlavesOutBus_Type is array(CNumOfSlaves-1 downto 0) of SlvOutBus_Type; -- Memory address decoder constant CMemMappedIOBaseAdr : std_logic_vector(3 downto 0) := x"D"; constant CDRAMBaseAdr : std_logic_vector(1 downto 0) := "00"; end MemAccessCtrlPack;
apache-2.0
3b92128506ba4ace0eb8b196c2e3ccb3
0.578856
3.475904
false
false
false
false
GSimas/EEL5105
Eletr-Digital/Projeto Final/PROJETO COFRE FUNCIONANDO/BuzzerRe.vhd
1
4,562
-- megafunction wizard: %LPM_COUNTER% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: lpm_counter -- ============================================================ -- File Name: BuzzerRe.vhd -- Megafunction Name(s): -- lpm_counter -- -- Simulation Library Files(s): -- lpm -- ============================================================ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- -- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition -- ************************************************************ --Copyright (C) 1991-2010 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject --to the terms and conditions of the Altera Program License --Subscription Agreement, Altera MegaCore Function License --Agreement, or other applicable license agreement, including, --without limitation, that your use is for the sole purpose of --programming logic devices manufactured by Altera and sold by --Altera or its authorized distributors. Please refer to the --applicable agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY lpm; USE lpm.all; ENTITY BuzzerRe IS PORT ( clock : IN STD_LOGIC ; cout : OUT STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (29 DOWNTO 0) ); END BuzzerRe; ARCHITECTURE SYN OF buzzerre IS SIGNAL sub_wire0 : STD_LOGIC ; SIGNAL sub_wire1 : STD_LOGIC_VECTOR (29 DOWNTO 0); COMPONENT lpm_counter GENERIC ( lpm_direction : STRING; lpm_modulus : NATURAL; lpm_port_updown : STRING; lpm_type : STRING; lpm_width : NATURAL ); PORT ( clock : IN STD_LOGIC ; cout : OUT STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (29 DOWNTO 0) ); END COMPONENT; BEGIN cout <= sub_wire0; q <= sub_wire1(29 DOWNTO 0); lpm_counter_component : lpm_counter GENERIC MAP ( lpm_direction => "UP", lpm_modulus => 84175, lpm_port_updown => "PORT_UNUSED", lpm_type => "LPM_COUNTER", lpm_width => 30 ) PORT MAP ( clock => clock, cout => sub_wire0, q => sub_wire1 ); END SYN; -- ============================================================ -- CNX file retrieval info -- ============================================================ -- Retrieval info: PRIVATE: ACLR NUMERIC "0" -- Retrieval info: PRIVATE: ALOAD NUMERIC "0" -- Retrieval info: PRIVATE: ASET NUMERIC "0" -- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1" -- Retrieval info: PRIVATE: CLK_EN NUMERIC "0" -- Retrieval info: PRIVATE: CNT_EN NUMERIC "0" -- Retrieval info: PRIVATE: CarryIn NUMERIC "0" -- Retrieval info: PRIVATE: CarryOut NUMERIC "1" -- Retrieval info: PRIVATE: Direction NUMERIC "0" -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" -- Retrieval info: PRIVATE: ModulusCounter NUMERIC "1" -- Retrieval info: PRIVATE: ModulusValue NUMERIC "84175" -- Retrieval info: PRIVATE: SCLR NUMERIC "0" -- Retrieval info: PRIVATE: SLOAD NUMERIC "0" -- Retrieval info: PRIVATE: SSET NUMERIC "0" -- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: nBit NUMERIC "30" -- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP" -- Retrieval info: CONSTANT: LPM_MODULUS NUMERIC "84175" -- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER" -- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "30" -- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock -- Retrieval info: USED_PORT: cout 0 0 0 0 OUTPUT NODEFVAL cout -- Retrieval info: USED_PORT: q 0 0 30 0 OUTPUT NODEFVAL q[29..0] -- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 -- Retrieval info: CONNECT: q 0 0 30 0 @q 0 0 30 0 -- Retrieval info: CONNECT: cout 0 0 0 0 @cout 0 0 0 0 -- Retrieval info: LIBRARY: lpm lpm.lpm_components.all -- Retrieval info: GEN_FILE: TYPE_NORMAL BuzzerRe.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL BuzzerRe.inc TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL BuzzerRe.cmp TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL BuzzerRe.bsf TRUE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL BuzzerRe_inst.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL BuzzerRe_waveforms.html TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL BuzzerRe_wave*.jpg FALSE -- Retrieval info: LIB_FILE: lpm
mit
8cddb1e8b4837afb3fc146cef65e600b
0.655633
3.664257
false
false
false
false
abyrne55/my-little-processor
binary_to_sevenSeg.vhd
1
1,047
LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY binary_to_sevenSeg IS PORT ( binary_value : IN STD_LOGIC_VECTOR(3 DOWNTO 0); sevenSeg : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) ); END; ARCHITECTURE behavioural OF binary_to_sevenSeg IS BEGIN PROCESS (binary_value) BEGIN CASE binary_value IS WHEN "0000" => sevenSeg <= "1000000"; WHEN "0001" => sevenSeg <= "1001111"; WHEN "0010" => sevenSeg <= "0100100"; WHEN "0011" => sevenSeg <= "0110000"; WHEN "0100" => sevenSeg <= "0011001"; WHEN "0101" => sevenSeg <= "0010010"; WHEN "0110" => sevenSeg <= "0000010"; WHEN "0111" => sevenSeg <= "1111000"; WHEN "1000" => sevenSeg <= "0000000"; WHEN "1001" => sevenSeg <= "0010000"; WHEN "1010" => sevenSeg <= "0001000"; WHEN "1011" => sevenSeg <= "0000000"; WHEN "1100" => sevenSeg <= "1000110"; WHEN "1101" => sevenSeg <= "1000000"; WHEN "1110" => sevenSeg <= "0000110"; WHEN "1111" => sevenSeg <= "0001110"; WHEN OTHERS => sevenSeg <= "1111111"; END CASE; END PROCESS; END behavioural;
mit
94e5512efc75daa7f96f348f5979f7d6
0.615091
3.271875
false
false
false
false
hoglet67/AtomFpga
src/common/AVR8/Core/io_adr_dec.vhd
4
1,339
--************************************************************************************************ -- Internal I/O registers decoder/multiplexer for the AVR core -- Version 1.11 -- Modified 05.06.2003 -- Designed by Ruslan Lepetenok --************************************************************************************************ library IEEE; use IEEE.std_logic_1164.all; use WORK.AVRuCPackage.all; entity io_adr_dec is port ( adr : in std_logic_vector(15 downto 0); iore : in std_logic; dbusin_ext : in std_logic_vector(7 downto 0); dbusin_int : out std_logic_vector(7 downto 0); spl_out : in std_logic_vector(7 downto 0); sph_out : in std_logic_vector(7 downto 0); sreg_out : in std_logic_vector(7 downto 0); rampz_out : in std_logic_vector(7 downto 0)); end io_adr_dec; architecture RTL of io_adr_dec is begin dbusin_int <= spl_out when (adr=SPL_Address and iore='1') else sph_out when (adr=SPH_Address and iore='1') else sreg_out when (adr=SREG_Address and iore='1') else rampz_out when (adr=RAMPZ_Address and iore='1') else dbusin_ext; end RTL;
apache-2.0
d400c0b9a7a5cc61d250e832a155d71b
0.463779
3.926686
false
false
false
false
fquinto/Wireless_sensor_network
Avnet_UPC/hdl/cs_push_3bit_wrapper.vhd
1
7,790
------------------------------------------------------------------------------- -- cs_push_3bit_wrapper.vhd ------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; library xps_gpio_v2_00_a; use xps_gpio_v2_00_a.all; entity cs_push_3bit_wrapper is port ( SPLB_Clk : in std_logic; SPLB_Rst : in std_logic; PLB_ABus : in std_logic_vector(0 to 31); PLB_UABus : in std_logic_vector(0 to 31); PLB_PAValid : in std_logic; PLB_SAValid : in std_logic; PLB_rdPrim : in std_logic; PLB_wrPrim : in std_logic; PLB_masterID : in std_logic_vector(0 to 0); PLB_abort : in std_logic; PLB_busLock : in std_logic; PLB_RNW : in std_logic; PLB_BE : in std_logic_vector(0 to 3); PLB_MSize : in std_logic_vector(0 to 1); PLB_size : in std_logic_vector(0 to 3); PLB_type : in std_logic_vector(0 to 2); PLB_lockErr : in std_logic; PLB_wrDBus : in std_logic_vector(0 to 31); PLB_wrBurst : in std_logic; PLB_rdBurst : in std_logic; PLB_wrPendReq : in std_logic; PLB_rdPendReq : in std_logic; PLB_wrPendPri : in std_logic_vector(0 to 1); PLB_rdPendPri : in std_logic_vector(0 to 1); PLB_reqPri : in std_logic_vector(0 to 1); PLB_TAttribute : in std_logic_vector(0 to 15); Sl_addrAck : out std_logic; Sl_SSize : out std_logic_vector(0 to 1); Sl_wait : out std_logic; Sl_rearbitrate : out std_logic; Sl_wrDAck : out std_logic; Sl_wrComp : out std_logic; Sl_wrBTerm : out std_logic; Sl_rdDBus : out std_logic_vector(0 to 31); Sl_rdWdAddr : out std_logic_vector(0 to 3); Sl_rdDAck : out std_logic; Sl_rdComp : out std_logic; Sl_rdBTerm : out std_logic; Sl_MBusy : out std_logic_vector(0 to 1); Sl_MWrErr : out std_logic_vector(0 to 1); Sl_MRdErr : out std_logic_vector(0 to 1); Sl_MIRQ : out std_logic_vector(0 to 1); IP2INTC_Irpt : out std_logic; GPIO_IO_I : in std_logic_vector(0 to 2); GPIO_IO_O : out std_logic_vector(0 to 2); GPIO_IO_T : out std_logic_vector(0 to 2); GPIO2_IO_I : in std_logic_vector(0 to 31); GPIO2_IO_O : out std_logic_vector(0 to 31); GPIO2_IO_T : out std_logic_vector(0 to 31) ); attribute x_core_info : STRING; attribute x_core_info of cs_push_3bit_wrapper : entity is "xps_gpio_v2_00_a"; end cs_push_3bit_wrapper; architecture STRUCTURE of cs_push_3bit_wrapper is component xps_gpio is generic ( C_BASEADDR : std_logic_vector(0 to 31); C_HIGHADDR : std_logic_vector(0 to 31); C_SPLB_AWIDTH : INTEGER; C_SPLB_DWIDTH : INTEGER; C_SPLB_P2P : INTEGER; C_SPLB_MID_WIDTH : INTEGER; C_SPLB_NUM_MASTERS : INTEGER; C_SPLB_NATIVE_DWIDTH : INTEGER; C_SPLB_SUPPORT_BURSTS : INTEGER; C_FAMILY : STRING; C_ALL_INPUTS : INTEGER; C_ALL_INPUTS_2 : INTEGER; C_GPIO_WIDTH : INTEGER; C_GPIO2_WIDTH : INTEGER; C_INTERRUPT_PRESENT : INTEGER; C_DOUT_DEFAULT : std_logic_vector; C_TRI_DEFAULT : std_logic_vector; C_IS_DUAL : INTEGER; C_DOUT_DEFAULT_2 : std_logic_vector; C_TRI_DEFAULT_2 : std_logic_vector ); port ( SPLB_Clk : in std_logic; SPLB_Rst : in std_logic; PLB_ABus : in std_logic_vector(0 to 31); PLB_UABus : in std_logic_vector(0 to 31); PLB_PAValid : in std_logic; PLB_SAValid : in std_logic; PLB_rdPrim : in std_logic; PLB_wrPrim : in std_logic; PLB_masterID : in std_logic_vector(0 to (C_SPLB_MID_WIDTH-1)); PLB_abort : in std_logic; PLB_busLock : in std_logic; PLB_RNW : in std_logic; PLB_BE : in std_logic_vector(0 to ((C_SPLB_DWIDTH/8)-1)); PLB_MSize : in std_logic_vector(0 to 1); PLB_size : in std_logic_vector(0 to 3); PLB_type : in std_logic_vector(0 to 2); PLB_lockErr : in std_logic; PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_DWIDTH-1)); PLB_wrBurst : in std_logic; PLB_rdBurst : in std_logic; PLB_wrPendReq : in std_logic; PLB_rdPendReq : in std_logic; PLB_wrPendPri : in std_logic_vector(0 to 1); PLB_rdPendPri : in std_logic_vector(0 to 1); PLB_reqPri : in std_logic_vector(0 to 1); PLB_TAttribute : in std_logic_vector(0 to 15); Sl_addrAck : out std_logic; Sl_SSize : out std_logic_vector(0 to 1); Sl_wait : out std_logic; Sl_rearbitrate : out std_logic; Sl_wrDAck : out std_logic; Sl_wrComp : out std_logic; Sl_wrBTerm : out std_logic; Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_DWIDTH-1)); Sl_rdWdAddr : out std_logic_vector(0 to 3); Sl_rdDAck : out std_logic; Sl_rdComp : out std_logic; Sl_rdBTerm : out std_logic; Sl_MBusy : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1)); Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1)); Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1)); Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1)); IP2INTC_Irpt : out std_logic; GPIO_IO_I : in std_logic_vector(0 to (C_GPIO_WIDTH-1)); GPIO_IO_O : out std_logic_vector(0 to (C_GPIO_WIDTH-1)); GPIO_IO_T : out std_logic_vector(0 to (C_GPIO_WIDTH-1)); GPIO2_IO_I : in std_logic_vector(0 to (C_GPIO2_WIDTH-1)); GPIO2_IO_O : out std_logic_vector(0 to (C_GPIO2_WIDTH-1)); GPIO2_IO_T : out std_logic_vector(0 to (C_GPIO2_WIDTH-1)) ); end component; begin CS_PUSH_3BIT : xps_gpio generic map ( C_BASEADDR => X"81420000", C_HIGHADDR => X"8142ffff", C_SPLB_AWIDTH => 32, C_SPLB_DWIDTH => 32, C_SPLB_P2P => 0, C_SPLB_MID_WIDTH => 1, C_SPLB_NUM_MASTERS => 2, C_SPLB_NATIVE_DWIDTH => 32, C_SPLB_SUPPORT_BURSTS => 0, C_FAMILY => "spartan3a", C_ALL_INPUTS => 1, C_ALL_INPUTS_2 => 0, C_GPIO_WIDTH => 3, C_GPIO2_WIDTH => 32, C_INTERRUPT_PRESENT => 0, C_DOUT_DEFAULT => X"00000000", C_TRI_DEFAULT => X"ffffffff", C_IS_DUAL => 0, C_DOUT_DEFAULT_2 => X"00000000", C_TRI_DEFAULT_2 => X"ffffffff" ) port map ( SPLB_Clk => SPLB_Clk, SPLB_Rst => SPLB_Rst, PLB_ABus => PLB_ABus, PLB_UABus => PLB_UABus, PLB_PAValid => PLB_PAValid, PLB_SAValid => PLB_SAValid, PLB_rdPrim => PLB_rdPrim, PLB_wrPrim => PLB_wrPrim, PLB_masterID => PLB_masterID, PLB_abort => PLB_abort, PLB_busLock => PLB_busLock, PLB_RNW => PLB_RNW, PLB_BE => PLB_BE, PLB_MSize => PLB_MSize, PLB_size => PLB_size, PLB_type => PLB_type, PLB_lockErr => PLB_lockErr, PLB_wrDBus => PLB_wrDBus, PLB_wrBurst => PLB_wrBurst, PLB_rdBurst => PLB_rdBurst, PLB_wrPendReq => PLB_wrPendReq, PLB_rdPendReq => PLB_rdPendReq, PLB_wrPendPri => PLB_wrPendPri, PLB_rdPendPri => PLB_rdPendPri, PLB_reqPri => PLB_reqPri, PLB_TAttribute => PLB_TAttribute, Sl_addrAck => Sl_addrAck, Sl_SSize => Sl_SSize, Sl_wait => Sl_wait, Sl_rearbitrate => Sl_rearbitrate, Sl_wrDAck => Sl_wrDAck, Sl_wrComp => Sl_wrComp, Sl_wrBTerm => Sl_wrBTerm, Sl_rdDBus => Sl_rdDBus, Sl_rdWdAddr => Sl_rdWdAddr, Sl_rdDAck => Sl_rdDAck, Sl_rdComp => Sl_rdComp, Sl_rdBTerm => Sl_rdBTerm, Sl_MBusy => Sl_MBusy, Sl_MWrErr => Sl_MWrErr, Sl_MRdErr => Sl_MRdErr, Sl_MIRQ => Sl_MIRQ, IP2INTC_Irpt => IP2INTC_Irpt, GPIO_IO_I => GPIO_IO_I, GPIO_IO_O => GPIO_IO_O, GPIO_IO_T => GPIO_IO_T, GPIO2_IO_I => GPIO2_IO_I, GPIO2_IO_O => GPIO2_IO_O, GPIO2_IO_T => GPIO2_IO_T ); end architecture STRUCTURE;
mit
378e4ceb341843432cbb49b27f719375
0.583312
3.065722
false
false
false
false
hoglet67/AtomFpga
src/common/AVR8/resync/rsnc_l_vect.vhd
4
1,771
--********************************************************************************************** -- Resynchronizer (for n-bit vector) with latch -- Version 0.1 -- Modified 10.01.2007 -- Designed by Ruslan Lepetenok --********************************************************************************************** library IEEE; use IEEE.std_logic_1164.all; entity rsnc_l_vect is generic( tech : integer := 0; width : integer := 8; add_stgs_num : integer := 0 ); port( clk : in std_logic; di : in std_logic_vector(width-1 downto 0); do : out std_logic_vector(width-1 downto 0) ); end rsnc_l_vect; architecture rtl of rsnc_l_vect is type rsnc_vect_type is array(add_stgs_num+1 downto 0) of std_logic_vector(width-1 downto 0); signal rsnc_rg_current : rsnc_vect_type; signal rsnc_rg_next : rsnc_vect_type; begin -- Latch latch_prc:process(clk) begin if(clk='0') then rsnc_rg_current(rsnc_rg_current'low) <= rsnc_rg_next(rsnc_rg_next'low); end if; end process; -- Latch seq_re_prc:process(clk) begin if(clk='1' and clk'event) then -- Clock (rising edge) rsnc_rg_current(rsnc_rg_current'high downto rsnc_rg_current'low+1) <= rsnc_rg_next(rsnc_rg_current'high downto rsnc_rg_current'low+1); end if; end process; comb_prc:process(di,rsnc_rg_current) begin rsnc_rg_next(0) <= di; for i in 1 to rsnc_rg_next'high loop rsnc_rg_next(i) <= rsnc_rg_current(i-1); end loop; end process; do <= rsnc_rg_current(rsnc_rg_current'high); end rtl;
apache-2.0
e5bf8cf548372fc48cd8012c620513fa
0.498024
3.27963
false
false
false
false
Alabamajack/Garfield
FPGA_Design/Garfield_Design/Garfield.vhdl
1
28,367
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Garfield is port( ADC_CONVST : out std_logic; ADC_SCK : out std_logic; ADC_SDI : out std_logic; ADC_SDO : in std_logic; -- ARDUINO ARDUINO_IO : inout std_logic_vector(15 downto 0); ARDUINO_RESET_N : inout std_logic; -- CLK -- CLK_I2C_SCL : out std_logic; -- CLK_I2C_SDA : inout std_logic; -- FPGA FPGA_CLK1_50 : in std_logic; FPGA_CLK2_50 : in std_logic; FPGA_CLK3_50 : in std_logic; -- GPIO GPIO_0 : inout std_logic_vector(35 downto 0); GPIO_1 : inout std_logic_vector(35 downto 0); -- HPS HPS_CONV_USB_N : inout std_logic; HPS_DDR3_ADDR : out std_logic_vector(14 downto 0); HPS_DDR3_BA : out std_logic_vector(2 downto 0); HPS_DDR3_CAS_N : out std_logic; HPS_DDR3_CKE : out std_logic; HPS_DDR3_CK_N : out std_logic; HPS_DDR3_CK_P : out std_logic; HPS_DDR3_CS_N : out std_logic; HPS_DDR3_DM : out std_logic_vector(3 downto 0); HPS_DDR3_DQ : inout std_logic_vector(31 downto 0); HPS_DDR3_DQS_N : inout std_logic_vector(3 downto 0); HPS_DDR3_DQS_P : inout std_logic_vector(3 downto 0); HPS_DDR3_ODT : out std_logic; HPS_DDR3_RAS_N : out std_logic; HPS_DDR3_RESET_N : out std_logic; HPS_DDR3_RZQ : in std_logic; HPS_DDR3_WE_N : out std_logic; HPS_ENET_GTX_CLK : out std_logic; HPS_ENET_INT_N : inout std_logic; HPS_ENET_MDC : out std_logic; HPS_ENET_MDIO : inout std_logic; HPS_ENET_RX_CLK : in std_logic; HPS_ENET_RX_DATA : in std_logic_vector(3 downto 0); HPS_ENET_RX_DV : in std_logic; HPS_ENET_TX_DATA : out std_logic_vector(3 downto 0); HPS_ENET_TX_EN : out std_logic; HPS_GSENSOR_INT : inout std_logic; HPS_I2C0_SCLK : inout std_logic; HPS_I2C0_SDAT : inout std_logic; HPS_I2C1_SCLK : inout std_logic; HPS_I2C1_SDAT : inout std_logic; HPS_KEY : inout std_logic; HPS_LED : inout std_logic; HPS_LTC_GPIO : inout std_logic; HPS_SD_CLK : out std_logic; HPS_SD_CMD : inout std_logic; HPS_SD_DATA : inout std_logic_vector(3 downto 0); HPS_SPIM_CLK : out std_logic; HPS_SPIM_MISO : in std_logic; HPS_SPIM_MOSI : out std_logic; HPS_SPIM_SS : inout std_logic; HPS_UART_RX : in std_logic; HPS_UART_TX : out std_logic; HPS_USB_CLKOUT : in std_logic; HPS_USB_DATA : inout std_logic_vector(7 downto 0); HPS_USB_DIR : in std_logic; HPS_USB_NXT : in std_logic; HPS_USB_STP : out std_logic; -- Key KEY : in std_logic_vector(1 downto 0); -- LEDs LED : out std_logic_vector(7 downto 0); -- SW SW : in std_logic_vector(3 downto 0) ); end Garfield; architecture RTL of Garfield is component Garfield_system is port ( clk_clk : in std_logic := 'X'; -- clk clk_1_fpga_clock_clk : in std_logic := 'X'; -- clk clk_1_fpga_reset_reset_n : in std_logic := 'X'; -- reset_n drive_pwm_pwm_signal_export : out std_logic; -- export garfield_general_io_external_connection_export : out std_logic_vector(7 downto 0); -- export garfield_lighting_led_external_connection_export : out std_logic_vector(3 downto 0); -- export hps_0_f2h_cold_reset_req_reset_n : in std_logic := 'X'; -- reset_n hps_0_f2h_debug_reset_req_reset_n : in std_logic := 'X'; -- reset_n hps_0_f2h_stm_hw_events_stm_hwevents : in std_logic_vector(27 downto 0) := (others => 'X'); -- stm_hwevents hps_0_f2h_warm_reset_req_reset_n : in std_logic := 'X'; -- reset_n hps_0_h2f_reset_reset_n : out std_logic; -- reset_n hps_0_hps_io_hps_io_emac1_inst_TX_CLK : out std_logic; -- hps_io_emac1_inst_TX_CLK hps_0_hps_io_hps_io_emac1_inst_TXD0 : out std_logic; -- hps_io_emac1_inst_TXD0 hps_0_hps_io_hps_io_emac1_inst_TXD1 : out std_logic; -- hps_io_emac1_inst_TXD1 hps_0_hps_io_hps_io_emac1_inst_TXD2 : out std_logic; -- hps_io_emac1_inst_TXD2 hps_0_hps_io_hps_io_emac1_inst_TXD3 : out std_logic; -- hps_io_emac1_inst_TXD3 hps_0_hps_io_hps_io_emac1_inst_RXD0 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD0 hps_0_hps_io_hps_io_emac1_inst_MDIO : inout std_logic := 'X'; -- hps_io_emac1_inst_MDIO hps_0_hps_io_hps_io_emac1_inst_MDC : out std_logic; -- hps_io_emac1_inst_MDC hps_0_hps_io_hps_io_emac1_inst_RX_CTL : in std_logic := 'X'; -- hps_io_emac1_inst_RX_CTL hps_0_hps_io_hps_io_emac1_inst_TX_CTL : out std_logic; -- hps_io_emac1_inst_TX_CTL hps_0_hps_io_hps_io_emac1_inst_RX_CLK : in std_logic := 'X'; -- hps_io_emac1_inst_RX_CLK hps_0_hps_io_hps_io_emac1_inst_RXD1 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD1 hps_0_hps_io_hps_io_emac1_inst_RXD2 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD2 hps_0_hps_io_hps_io_emac1_inst_RXD3 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD3 hps_0_hps_io_hps_io_sdio_inst_CMD : inout std_logic := 'X'; -- hps_io_sdio_inst_CMD hps_0_hps_io_hps_io_sdio_inst_D0 : inout std_logic := 'X'; -- hps_io_sdio_inst_D0 hps_0_hps_io_hps_io_sdio_inst_D1 : inout std_logic := 'X'; -- hps_io_sdio_inst_D1 hps_0_hps_io_hps_io_sdio_inst_CLK : out std_logic; -- hps_io_sdio_inst_CLK hps_0_hps_io_hps_io_sdio_inst_D2 : inout std_logic := 'X'; -- hps_io_sdio_inst_D2 hps_0_hps_io_hps_io_sdio_inst_D3 : inout std_logic := 'X'; -- hps_io_sdio_inst_D3 hps_0_hps_io_hps_io_usb1_inst_D0 : inout std_logic := 'X'; -- hps_io_usb1_inst_D0 hps_0_hps_io_hps_io_usb1_inst_D1 : inout std_logic := 'X'; -- hps_io_usb1_inst_D1 hps_0_hps_io_hps_io_usb1_inst_D2 : inout std_logic := 'X'; -- hps_io_usb1_inst_D2 hps_0_hps_io_hps_io_usb1_inst_D3 : inout std_logic := 'X'; -- hps_io_usb1_inst_D3 hps_0_hps_io_hps_io_usb1_inst_D4 : inout std_logic := 'X'; -- hps_io_usb1_inst_D4 hps_0_hps_io_hps_io_usb1_inst_D5 : inout std_logic := 'X'; -- hps_io_usb1_inst_D5 hps_0_hps_io_hps_io_usb1_inst_D6 : inout std_logic := 'X'; -- hps_io_usb1_inst_D6 hps_0_hps_io_hps_io_usb1_inst_D7 : inout std_logic := 'X'; -- hps_io_usb1_inst_D7 hps_0_hps_io_hps_io_usb1_inst_CLK : in std_logic := 'X'; -- hps_io_usb1_inst_CLK hps_0_hps_io_hps_io_usb1_inst_STP : out std_logic; -- hps_io_usb1_inst_STP hps_0_hps_io_hps_io_usb1_inst_DIR : in std_logic := 'X'; -- hps_io_usb1_inst_DIR hps_0_hps_io_hps_io_usb1_inst_NXT : in std_logic := 'X'; -- hps_io_usb1_inst_NXT hps_0_hps_io_hps_io_spim1_inst_CLK : out std_logic; -- hps_io_spim1_inst_CLK hps_0_hps_io_hps_io_spim1_inst_MOSI : out std_logic; -- hps_io_spim1_inst_MOSI hps_0_hps_io_hps_io_spim1_inst_MISO : in std_logic := 'X'; -- hps_io_spim1_inst_MISO hps_0_hps_io_hps_io_spim1_inst_SS0 : out std_logic; -- hps_io_spim1_inst_SS0 hps_0_hps_io_hps_io_uart0_inst_RX : in std_logic := 'X'; -- hps_io_uart0_inst_RX hps_0_hps_io_hps_io_uart0_inst_TX : out std_logic; -- hps_io_uart0_inst_TX hps_0_hps_io_hps_io_i2c0_inst_SDA : inout std_logic := 'X'; -- hps_io_i2c0_inst_SDA hps_0_hps_io_hps_io_i2c0_inst_SCL : inout std_logic := 'X'; -- hps_io_i2c0_inst_SCL hps_0_hps_io_hps_io_i2c1_inst_SDA : inout std_logic := 'X'; -- hps_io_i2c1_inst_SDA hps_0_hps_io_hps_io_i2c1_inst_SCL : inout std_logic := 'X'; -- hps_io_i2c1_inst_SCL hps_0_hps_io_hps_io_gpio_inst_GPIO09 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO09 hps_0_hps_io_hps_io_gpio_inst_GPIO35 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO35 hps_0_hps_io_hps_io_gpio_inst_GPIO40 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO40 hps_0_hps_io_hps_io_gpio_inst_GPIO53 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO53 hps_0_hps_io_hps_io_gpio_inst_GPIO54 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO54 hps_0_hps_io_hps_io_gpio_inst_GPIO61 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO61 i2c_opencores_0_export_sda_pad_in : in std_logic := 'X'; -- sda_pad_in i2c_opencores_0_export_sda_pad_out : out std_logic; -- sda_pad_out i2c_opencores_0_export_sda_pad_en : out std_logic; -- sda_pad_en i2c_opencores_0_export_scl_pad_in : in std_logic := 'X'; -- scl_pad_in i2c_opencores_0_export_scl_pad_out : out std_logic; -- scl_pad_out i2c_opencores_0_export_scl_pad_en : out std_logic; -- scl_pad_en memory_mem_a : out std_logic_vector(14 downto 0); -- mem_a memory_mem_ba : out std_logic_vector(2 downto 0); -- mem_ba memory_mem_ck : out std_logic; -- mem_ck memory_mem_ck_n : out std_logic; -- mem_ck_n memory_mem_cke : out std_logic; -- mem_cke memory_mem_cs_n : out std_logic; -- mem_cs_n memory_mem_ras_n : out std_logic; -- mem_ras_n memory_mem_cas_n : out std_logic; -- mem_cas_n memory_mem_we_n : out std_logic; -- mem_we_n memory_mem_reset_n : out std_logic; -- mem_reset_n memory_mem_dq : inout std_logic_vector(31 downto 0) := (others => 'X'); -- mem_dq memory_mem_dqs : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs memory_mem_dqs_n : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs_n memory_mem_odt : out std_logic; -- mem_odt memory_mem_dm : out std_logic_vector(3 downto 0); -- mem_dm memory_oct_rzqin : in std_logic := 'X'; -- oct_rzqin onboard_button_external_connection_export : in std_logic_vector(1 downto 0) := (others => 'X'); -- export onboard_dipsw_external_connection_export : in std_logic_vector(3 downto 0) := (others => 'X'); -- export onboard_led_external_connection_export : out std_logic_vector(7 downto 0); -- export reset_reset_n : in std_logic := 'X'; -- reset_n rotary_encoder_0_conduit_end_rot_input : in std_logic := 'X'; -- rot_input spi_0_external_connection_MISO : in std_logic := 'X'; -- MISO spi_0_external_connection_MOSI : out std_logic; -- MOSI spi_0_external_connection_SCLK : out std_logic; -- SCLK spi_0_external_connection_SS_n : out std_logic_vector(2 downto 0); -- SS_n steering_pwm_pwm_signal_export : out std_logic -- export ); end component Garfield_system; component altera_edge_detector is generic( PULSE_EXT : natural := 0; EDGE_TYPE : natural := 0; IGNORE_RST_WHILE_BUSY : natural := 0 ); port( clk : in std_logic; rst_n : in std_logic; signal_in : in std_logic; pulse_out : out std_logic ); end component; component hps_reset is port( probe : in std_logic; source_clk : in std_logic; source : out std_logic_vector(2 downto 0) ); end component; ---------------------------------------------------------------------------- ---------------------- signals for top level logic ---------------------------------------------------------------------------- signal hps_fpga_reset_n : std_logic; signal fpga_debounced_buttons : std_logic_vector(1 downto 0); signal fpga_led_internal : std_logic_vector(7 downto 0); signal hps_reset_req : std_logic_vector(2 downto 0); signal hps_cold_reset : std_logic; signal hps_warm_reset : std_logic; signal hps_debug_reset : std_logic; signal stm_hw_events : std_logic_vector(27 downto 0); signal fpga_clk_50 : std_logic; signal spi_0_miso : std_logic; signal spi_0_mosi : std_logic; signal spi_0_sclk : std_logic; signal spi_0_cs_n : std_logic_vector(2 downto 0); signal i2c0_sda_i : std_logic; signal i2c0_sda_o : std_logic; signal i2c0_sda_en : std_logic; signal i2c0_scl_i : std_logic; signal i2c0_scl_o : std_logic; signal i2c0_scl_en : std_logic; signal garfield_lighting : std_logic_vector(3 downto 0); signal garfield_gpio : std_logic_vector(7 downto 0); signal garfield_drive_pwm : std_logic; signal garfield_steering_pwm : std_logic; signal speed_rotary : std_logic; signal status_led : std_logic := '0'; signal status_led_counter : natural := 0; begin u0 : component Garfield_system port map( clk_clk => FPGA_CLK1_50, -- clk.clk clk_1_fpga_clock_clk => FPGA_CLK2_50, -- clk_1_fpga_clock.clk clk_1_fpga_reset_reset_n => hps_fpga_reset_n, -- clk_1_fpga_reset.reset_n drive_pwm_pwm_signal_export => garfield_drive_pwm, -- drive_pwm_pwm_signal.export garfield_general_io_external_connection_export => garfield_gpio, -- garfield_general_io_external_connection.export garfield_lighting_led_external_connection_export => garfield_lighting, -- garfield_lighting_led_external_connection.export hps_0_f2h_cold_reset_req_reset_n => not hps_cold_reset, -- hps_0_f2h_cold_reset_req.reset_n hps_0_f2h_debug_reset_req_reset_n => not hps_debug_reset, -- hps_0_f2h_debug_reset_req.reset_n hps_0_f2h_stm_hw_events_stm_hwevents => stm_hw_events, -- hps_0_f2h_stm_hw_events.stm_hwevents hps_0_f2h_warm_reset_req_reset_n => not hps_warm_reset, -- hps_0_f2h_warm_reset_req.reset_n hps_0_h2f_reset_reset_n => hps_fpga_reset_n, -- hps_0_h2f_reset.reset_n hps_0_hps_io_hps_io_emac1_inst_TX_CLK => HPS_ENET_GTX_CLK, -- hps_0_hps_io.hps_io_emac1_inst_TX_CLK hps_0_hps_io_hps_io_emac1_inst_TXD0 => HPS_ENET_TX_DATA(0), -- .hps_io_emac1_inst_TXD0 hps_0_hps_io_hps_io_emac1_inst_TXD1 => HPS_ENET_TX_DATA(1), -- .hps_io_emac1_inst_TXD1 hps_0_hps_io_hps_io_emac1_inst_TXD2 => HPS_ENET_TX_DATA(2), -- .hps_io_emac1_inst_TXD2 hps_0_hps_io_hps_io_emac1_inst_TXD3 => HPS_ENET_TX_DATA(3), -- .hps_io_emac1_inst_TXD3 hps_0_hps_io_hps_io_emac1_inst_RXD0 => HPS_ENET_RX_DATA(0), -- .hps_io_emac1_inst_RXD0 hps_0_hps_io_hps_io_emac1_inst_MDIO => HPS_ENET_MDIO, -- .hps_io_emac1_inst_MDIO hps_0_hps_io_hps_io_emac1_inst_MDC => HPS_ENET_MDC, -- .hps_io_emac1_inst_MDC hps_0_hps_io_hps_io_emac1_inst_RX_CTL => HPS_ENET_RX_DV, -- .hps_io_emac1_inst_RX_CTL hps_0_hps_io_hps_io_emac1_inst_TX_CTL => HPS_ENET_TX_EN, -- .hps_io_emac1_inst_TX_CTL hps_0_hps_io_hps_io_emac1_inst_RX_CLK => HPS_ENET_RX_CLK, -- .hps_io_emac1_inst_RX_CLK hps_0_hps_io_hps_io_emac1_inst_RXD1 => HPS_ENET_RX_DATA(1), -- .hps_io_emac1_inst_RXD1 hps_0_hps_io_hps_io_emac1_inst_RXD2 => HPS_ENET_RX_DATA(2), -- .hps_io_emac1_inst_RXD2 hps_0_hps_io_hps_io_emac1_inst_RXD3 => HPS_ENET_RX_DATA(3), -- .hps_io_emac1_inst_RXD3 hps_0_hps_io_hps_io_sdio_inst_CMD => HPS_SD_CMD, -- .hps_io_sdio_inst_CMD hps_0_hps_io_hps_io_sdio_inst_D0 => HPS_SD_DATA(0), -- .hps_io_sdio_inst_D0 hps_0_hps_io_hps_io_sdio_inst_D1 => HPS_SD_DATA(1), -- .hps_io_sdio_inst_D1 hps_0_hps_io_hps_io_sdio_inst_CLK => HPS_SD_CLK, -- .hps_io_sdio_inst_CLK hps_0_hps_io_hps_io_sdio_inst_D2 => HPS_SD_DATA(2), -- .hps_io_sdio_inst_D2 hps_0_hps_io_hps_io_sdio_inst_D3 => HPS_SD_DATA(3), -- .hps_io_sdio_inst_D3 hps_0_hps_io_hps_io_usb1_inst_D0 => HPS_USB_DATA(0), -- .hps_io_usb1_inst_D0 hps_0_hps_io_hps_io_usb1_inst_D1 => HPS_USB_DATA(1), -- .hps_io_usb1_inst_D1 hps_0_hps_io_hps_io_usb1_inst_D2 => HPS_USB_DATA(2), -- .hps_io_usb1_inst_D2 hps_0_hps_io_hps_io_usb1_inst_D3 => HPS_USB_DATA(3), -- .hps_io_usb1_inst_D3 hps_0_hps_io_hps_io_usb1_inst_D4 => HPS_USB_DATA(4), -- .hps_io_usb1_inst_D4 hps_0_hps_io_hps_io_usb1_inst_D5 => HPS_USB_DATA(5), -- .hps_io_usb1_inst_D5 hps_0_hps_io_hps_io_usb1_inst_D6 => HPS_USB_DATA(6), -- .hps_io_usb1_inst_D6 hps_0_hps_io_hps_io_usb1_inst_D7 => HPS_USB_DATA(7), -- .hps_io_usb1_inst_D7 hps_0_hps_io_hps_io_usb1_inst_CLK => HPS_USB_CLKOUT, -- .hps_io_usb1_inst_CLK hps_0_hps_io_hps_io_usb1_inst_STP => HPS_USB_STP, -- .hps_io_usb1_inst_STP hps_0_hps_io_hps_io_usb1_inst_DIR => HPS_USB_DIR, -- .hps_io_usb1_inst_DIR hps_0_hps_io_hps_io_usb1_inst_NXT => HPS_USB_NXT, -- .hps_io_usb1_inst_NXT hps_0_hps_io_hps_io_spim1_inst_CLK => HPS_SPIM_CLK, -- .hps_io_spim1_inst_CLK hps_0_hps_io_hps_io_spim1_inst_MOSI => HPS_SPIM_MOSI, -- .hps_io_spim1_inst_MOSI hps_0_hps_io_hps_io_spim1_inst_MISO => HPS_SPIM_MISO, -- .hps_io_spim1_inst_MISO hps_0_hps_io_hps_io_spim1_inst_SS0 => HPS_SPIM_SS, -- .hps_io_spim1_inst_SS0 hps_0_hps_io_hps_io_uart0_inst_RX => HPS_UART_RX, -- .hps_io_uart0_inst_RX hps_0_hps_io_hps_io_uart0_inst_TX => HPS_UART_TX, -- .hps_io_uart0_inst_TX hps_0_hps_io_hps_io_i2c0_inst_SDA => HPS_I2C0_SDAT, -- .hps_io_i2c0_inst_SDA hps_0_hps_io_hps_io_i2c0_inst_SCL => HPS_I2C0_SCLK, -- .hps_io_i2c0_inst_SCL hps_0_hps_io_hps_io_i2c1_inst_SDA => HPS_I2C1_SDAT, -- .hps_io_i2c1_inst_SDA hps_0_hps_io_hps_io_i2c1_inst_SCL => HPS_I2C1_SCLK, -- .hps_io_i2c1_inst_SCL hps_0_hps_io_hps_io_gpio_inst_GPIO09 => HPS_CONV_USB_N, -- .hps_io_gpio_inst_GPIO09 hps_0_hps_io_hps_io_gpio_inst_GPIO35 => HPS_ENET_INT_N, -- .hps_io_gpio_inst_GPIO35 hps_0_hps_io_hps_io_gpio_inst_GPIO40 => HPS_LTC_GPIO, -- .hps_io_gpio_inst_GPIO40 hps_0_hps_io_hps_io_gpio_inst_GPIO53 => HPS_LED, -- .hps_io_gpio_inst_GPIO53 hps_0_hps_io_hps_io_gpio_inst_GPIO54 => HPS_KEY, -- .hps_io_gpio_inst_GPIO54 hps_0_hps_io_hps_io_gpio_inst_GPIO61 => HPS_GSENSOR_INT, -- .hps_io_gpio_inst_GPIO61 memory_mem_a => HPS_DDR3_ADDR, -- memory.mem_a memory_mem_ba => HPS_DDR3_BA, -- .mem_ba memory_mem_ck => HPS_DDR3_CK_P, -- .mem_ck memory_mem_ck_n => HPS_DDR3_CK_N, -- .mem_ck_n memory_mem_cke => HPS_DDR3_CKE, -- .mem_cke memory_mem_cs_n => HPS_DDR3_CS_N, -- .mem_cs_n memory_mem_ras_n => HPS_DDR3_RAS_N, -- .mem_ras_n memory_mem_cas_n => HPS_DDR3_CAS_N, -- .mem_cas_n memory_mem_we_n => HPS_DDR3_WE_N, -- .mem_we_n memory_mem_reset_n => HPS_DDR3_RESET_N, -- .mem_reset_n memory_mem_dq => HPS_DDR3_DQ, -- .mem_dq memory_mem_dqs => HPS_DDR3_DQS_P, -- .mem_dqs memory_mem_dqs_n => HPS_DDR3_DQS_N, -- .mem_dqs_n memory_mem_odt => HPS_DDR3_ODT, -- .mem_odt memory_mem_dm => HPS_DDR3_DM, -- .mem_dm memory_oct_rzqin => HPS_DDR3_RZQ, -- .oct_rzqin onboard_button_external_connection_export => fpga_debounced_buttons, -- onboard_button_external_connection.export onboard_dipsw_external_connection_export => SW, -- onboard_dipsw_external_connection.export onboard_led_external_connection_export => fpga_led_internal, -- onboard_led_external_connection.export reset_reset_n => hps_fpga_reset_n, -- reset.reset_n rotary_encoder_0_conduit_end_rot_input => speed_rotary, -- rotary_encoder_0_conduit_end.rot_input spi_0_external_connection_MISO => spi_0_miso, -- spi_0_external_connection.MISO spi_0_external_connection_MOSI => spi_0_mosi, -- .MOSI spi_0_external_connection_SCLK => spi_0_sclk, -- .SCLK spi_0_external_connection_SS_n => spi_0_cs_n, -- .SS_n steering_pwm_pwm_signal_export => garfield_steering_pwm, -- steering_pwm_pwm_signal.export i2c_opencores_0_export_sda_pad_in => i2c0_sda_i, -- sda_pad_in i2c_opencores_0_export_sda_pad_out => i2c0_sda_o, -- sda_pad_out i2c_opencores_0_export_sda_pad_en => i2c0_sda_en, -- sda_pad_en i2c_opencores_0_export_scl_pad_in => i2c0_scl_i, -- scl_pad_in i2c_opencores_0_export_scl_pad_out => i2c0_scl_o, -- scl_pad_out i2c_opencores_0_export_scl_pad_en => i2c0_scl_en ); pulse_cold_reset : component altera_edge_detector generic map( PULSE_EXT => 6, EDGE_TYPE => 1, IGNORE_RST_WHILE_BUSY => 1 ) port map( clk => fpga_clk_50, rst_n => hps_fpga_reset_n, signal_in => hps_reset_req(0), pulse_out => hps_cold_reset ); pulse_warm_reset : component altera_edge_detector generic map( PULSE_EXT => 2, EDGE_TYPE => 1, IGNORE_RST_WHILE_BUSY => 1 ) port map( clk => fpga_clk_50, rst_n => hps_fpga_reset_n, signal_in => hps_reset_req(1), pulse_out => hps_warm_reset ); pulse_debug_reset : component altera_edge_detector generic map( PULSE_EXT => 32, EDGE_TYPE => 1, IGNORE_RST_WHILE_BUSY => 1 ) port map( clk => fpga_clk_50, rst_n => hps_fpga_reset_n, signal_in => hps_reset_req(2), pulse_out => hps_debug_reset ); ---------------------------------------------------------------------------- -- concurrent statements ---------------------------------------------------------------------------- -- i2c0 GPIO_1(0) <= 'Z' when i2c0_sda_en = '1' else i2c0_sda_o; GPIO_1(2) <= 'Z' when i2c0_scl_en = '1' else i2c0_scl_o; i2c0_sda_i <= GPIO_1(0); i2c0_scl_i <= GPIO_1(2); -- garfield lighting GPIO_1(1) <= garfield_lighting(0); GPIO_1(3) <= garfield_lighting(1); GPIO_1(5) <= garfield_lighting(2); GPIO_1(7) <= garfield_lighting(3); -- spi for display ARDUINO_IO(13) <= spi_0_sclk; ARDUINO_IO(12) <= spi_0_miso; ARDUINO_IO(11) <= spi_0_mosi; ARDUINO_IO(10) <= spi_0_cs_n(0); -- tft chipselect ARDUINO_IO(9) <= garfield_gpio(7); -- tft data command switch ARDUINO_IO(4) <= spi_0_cs_n(1); -- sd card chipselect -- pwm's and rotary of garfield GPIO_1(4) <= garfield_drive_pwm; GPIO_1(6) <= garfield_gpio(0); GPIO_1(9) <= garfield_steering_pwm; speed_rotary <= GPIO_1(11); -- others stm_hw_events <= (others => '0'); fpga_clk_50 <= FPGA_CLK1_50; LED(7 downto 1) <= fpga_led_internal(7 downto 1); LED(0) <= status_led; ---------------------------------------------------------------------------- -- processes ---------------------------------------------------------------------------- status_led_proc : process(fpga_clk_50, hps_fpga_reset_n) is begin if (hps_fpga_reset_n = '0') then status_led_counter <= 0; elsif (rising_edge(fpga_clk_50)) then if status_led_counter = 24999999 then status_led <= not status_led; status_led_counter <= 0; else status_led_counter <= status_led_counter + 1; end if; end if; end process status_led_proc; end architecture RTL;
gpl-3.0
a66d36835851100221881e957358d2b3
0.470476
3.031958
false
false
false
false
hoglet67/AtomFpga
src/common/ROM/fpgautils.vhd
1
32,780
-- generated with romgen v3.0.1r4 by MikeJ truhy and eD library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; library UNISIM; use UNISIM.Vcomponents.all; entity fpgautils is port ( CLK : in std_logic; ADDR : in std_logic_vector(11 downto 0); DATA : out std_logic_vector(7 downto 0) ); end; architecture RTL of fpgautils is function romgen_str2bv (str : string) return bit_vector is variable result : bit_vector (str'length*4-1 downto 0); begin for i in 0 to str'length-1 loop case str(str'high-i) is when '0' => result(i*4+3 downto i*4) := x"0"; when '1' => result(i*4+3 downto i*4) := x"1"; when '2' => result(i*4+3 downto i*4) := x"2"; when '3' => result(i*4+3 downto i*4) := x"3"; when '4' => result(i*4+3 downto i*4) := x"4"; when '5' => result(i*4+3 downto i*4) := x"5"; when '6' => result(i*4+3 downto i*4) := x"6"; when '7' => result(i*4+3 downto i*4) := x"7"; when '8' => result(i*4+3 downto i*4) := x"8"; when '9' => result(i*4+3 downto i*4) := x"9"; when 'A' => result(i*4+3 downto i*4) := x"A"; when 'B' => result(i*4+3 downto i*4) := x"B"; when 'C' => result(i*4+3 downto i*4) := x"C"; when 'D' => result(i*4+3 downto i*4) := x"D"; when 'E' => result(i*4+3 downto i*4) := x"E"; when 'F' => result(i*4+3 downto i*4) := x"F"; when others => null; end case; end loop; return result; end romgen_str2bv; attribute INIT_00 : string; attribute INIT_01 : string; attribute INIT_02 : string; attribute INIT_03 : string; attribute INIT_04 : string; attribute INIT_05 : string; attribute INIT_06 : string; attribute INIT_07 : string; attribute INIT_08 : string; attribute INIT_09 : string; attribute INIT_0A : string; attribute INIT_0B : string; attribute INIT_0C : string; attribute INIT_0D : string; attribute INIT_0E : string; attribute INIT_0F : string; attribute INIT_10 : string; attribute INIT_11 : string; attribute INIT_12 : string; attribute INIT_13 : string; attribute INIT_14 : string; attribute INIT_15 : string; attribute INIT_16 : string; attribute INIT_17 : string; attribute INIT_18 : string; attribute INIT_19 : string; attribute INIT_1A : string; attribute INIT_1B : string; attribute INIT_1C : string; attribute INIT_1D : string; attribute INIT_1E : string; attribute INIT_1F : string; attribute INIT_20 : string; attribute INIT_21 : string; attribute INIT_22 : string; attribute INIT_23 : string; attribute INIT_24 : string; attribute INIT_25 : string; attribute INIT_26 : string; attribute INIT_27 : string; attribute INIT_28 : string; attribute INIT_29 : string; attribute INIT_2A : string; attribute INIT_2B : string; attribute INIT_2C : string; attribute INIT_2D : string; attribute INIT_2E : string; attribute INIT_2F : string; attribute INIT_30 : string; attribute INIT_31 : string; attribute INIT_32 : string; attribute INIT_33 : string; attribute INIT_34 : string; attribute INIT_35 : string; attribute INIT_36 : string; attribute INIT_37 : string; attribute INIT_38 : string; attribute INIT_39 : string; attribute INIT_3A : string; attribute INIT_3B : string; attribute INIT_3C : string; attribute INIT_3D : string; attribute INIT_3E : string; attribute INIT_3F : string; component RAMB16_S4 --pragma translate_off generic ( INIT_00 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; INIT_01 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; INIT_02 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; INIT_03 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; INIT_04 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; INIT_05 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; INIT_06 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; INIT_07 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; INIT_08 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; INIT_09 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0A : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0B : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0C : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0D : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0E : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0F : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; INIT_10 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; INIT_11 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; INIT_12 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; INIT_13 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; INIT_14 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; INIT_15 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; INIT_16 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; INIT_17 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; INIT_18 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; INIT_19 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1A : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1B : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1C : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1D : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1E : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1F : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; INIT_20 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; INIT_21 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; INIT_22 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; INIT_23 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; INIT_24 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; INIT_25 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; INIT_26 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; INIT_27 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; INIT_28 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; INIT_29 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2A : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2B : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2C : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2D : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2E : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2F : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; INIT_30 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; INIT_31 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; INIT_32 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; INIT_33 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; INIT_34 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; INIT_35 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; INIT_36 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; INIT_37 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; INIT_38 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; INIT_39 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3A : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3B : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3C : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3D : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3E : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3F : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000" ); --pragma translate_on port ( DO : out std_logic_vector (3 downto 0); ADDR : in std_logic_vector (11 downto 0); CLK : in std_logic; DI : in std_logic_vector (3 downto 0); EN : in std_logic; SSR : in std_logic; WE : in std_logic ); end component; signal rom_addr : std_logic_vector(11 downto 0); begin p_addr : process(ADDR) begin rom_addr <= (others => '0'); rom_addr(11 downto 0) <= ADDR; end process; rom0 : if true generate attribute INIT_00 of inst : label is "C58602C58C46020904602250DD353470A860E951A00BD85051400CD888E4F2F0"; attribute INIT_01 of inst : label is "2B4831C676439C2613237441FCE45441FC05D345F373E934345FE93734512F60"; attribute INIT_02 of inst : label is "4E5CCE42143C0E42143C0E4E5CCE42143C0000E541204512C0854A0817676255"; attribute INIT_03 of inst : label is "603C94501706710035652575155505652108C02108C0000EBE12CCE42143C00E"; attribute INIT_04 of inst : label is "8514D95860095850955154505FFDF9508A888FDC82085820951B0020400A02E0"; attribute INIT_05 of inst : label is "88FFDF9D595885A5A0AA6A72958A5A0AA6A7285E035554025455620469524D41"; attribute INIT_06 of inst : label is "808080808080808080808080808080808080808080808080808080808080088A"; attribute INIT_07 of inst : label is "8080808080808080808080808080808080808080808080808080808080808080"; attribute INIT_08 of inst : label is "8080808080808080808080808080808080808080808080808080808080808080"; attribute INIT_09 of inst : label is "8080808080808080808080808080808080808080808080808080808080808080"; attribute INIT_0A of inst : label is "3210DCFE89AB01235476BA98EFCDBA98EFCD01235476DCFE89AB674532108080"; attribute INIT_0B of inst : label is "98BA76542301AB89FEDC1032456710324567AB89FEDC76542301CDEF98BA6745"; attribute INIT_0C of inst : label is "765498BACDEF45671032FEDCAB89FEDCAB894567103298BACDEF23017654CDEF"; attribute INIT_0D of inst : label is "DCFE32106745EFCDBA985476012354760123EFCDBA983210674589ABDCFE2301"; attribute INIT_0E of inst : label is "5652108C0E2CD0D89019D1D8029D3928D890D0D9029D1D02BD392AD293D089AB"; attribute INIT_0F of inst : label is "0D2D75820D3D85A69686766C0E5D5C5B509A50995D9859975096535554545553"; attribute INIT_10 of inst : label is "5652108C00203555802545562046D0D419019D1D00551545051E01B0040FDC82"; attribute INIT_11 of inst : label is "2D005030860A8029D1D02109029D1D94840035152505ADA141404E5371015550"; attribute INIT_12 of inst : label is "4E500DA7108200582015A0A42143710A036E0269524D21D0D8514D958602D490"; attribute INIT_13 of inst : label is "108C01ECA0A32300DA71095885A5A0AA6A72958A5A0AA6A72858202582035A0A"; attribute INIT_14 of inst : label is "EF3710FD082005658201555A0DF2607108204575A0BE120D127F207102108C02"; attribute INIT_15 of inst : label is "C900ADAEEE7E9DD127F20DA97100ADA4542F21DAE7101099F30A0F9EF980D296"; attribute INIT_16 of inst : label is "5AAD59FFD2955DA9FFD5955D09FFD59AAD59FFD2955DA9FFD59880C50B088095"; attribute INIT_17 of inst : label is "FFD4555D09FFD59AAD59FFD2955DA9FFD590035092509808D0A020000D09FFD4"; attribute INIT_18 of inst : label is "0FCCFED8980C508088096790058C4602888FFDF9D57009353616108D0A822101"; attribute INIT_19 of inst : label is "185710F00CD888FD0508F40600E9508905F4009508F40600CDF40090002FD001"; attribute INIT_1A of inst : label is "9A09149000ADA4C000430831C60DA00043041FCE40DA002511045120DAA35C0D"; attribute INIT_1B of inst : label is "956585800023509150925050989DB988D0982DA981D09509088091B9108B0924"; attribute INIT_1C of inst : label is "59065850C0008FD0790F40098208582095F4009820F9A00A9956049858000275"; attribute INIT_1D of inst : label is "8889083041A0F988418410608F4060418C09541208584100557945D901C30759"; attribute INIT_1E of inst : label is "F03F41C50792F0C5E25B1360792F041FC61A10792F03931216D5055558094545"; attribute INIT_1F of inst : label is "0393120322BF04F30393120322AC04F203931203226504F10393120322460792"; attribute INIT_20 of inst : label is "44349059E260261023DDF418A045834100C5E25B10904583410041FC619804F4"; attribute INIT_21 of inst : label is "F31BA052E3603F44377036045C7F803FD0322A403E2603717E9052E36026103F"; attribute INIT_22 of inst : label is "31010FD540E2F319503C130E2F314203C130E2F311503C130E2F31B603C130E2"; attribute INIT_23 of inst : label is "390E552330B512102F49EFD0B5123042F70E2F3136008450E2F31EA046450E2F"; attribute INIT_24 of inst : label is "DF412400E360531BB02E2605317E00E2605311B0949C9450661210E552330B51"; attribute INIT_25 of inst : label is "F2B3942908F2DF34401281CB0422E16037F4E97039DF41D101E16037F4E97039"; attribute INIT_26 of inst : label is "301B010E1608F2535FDD008F23FA2604E2603717FC0DF2B394B80DF2B394BB0D"; attribute INIT_27 of inst : label is "2E360DF243E203E260DF243F606E260116C13F501E1608F28266037E1605D218"; attribute INIT_28 of inst : label is "5E0DF413940EF93F200908F2CFF4000CE08F2CFF40006E039312250530001D04"; attribute INIT_29 of inst : label is "0EF930B1049450EF930B5049450EF9302F0752540EF930100DF413940EF93F20"; attribute INIT_2A of inst : label is "EBE5FF01E160949C94507FCC97350DF257042F6417550949C945033F2B904945"; attribute INIT_2B of inst : label is "D0C70A2B80407910B9B004C059D069F4CC9D0D092BDB92AD5929DB928D190E7F"; attribute INIT_2C of inst : label is "B80B6CB40F0E1EB009B40D4C0400B8050008E1EB00920F97009DAC0D1CDBCC8C"; attribute INIT_2D of inst : label is "B0C0F4E5BBCA20A01E59D2C65898B6CB90DDC408C501090090900C0014002004"; attribute INIT_2E of inst : label is "0E5090B08E109F0C70708009109EB0708F09009E60006480B0E10708C0647009"; attribute INIT_2F of inst : label is "5002C5446880854468A204654888EB00F620E509B0C885000F6B0E5F09080F62"; attribute INIT_30 of inst : label is "0FE86510FEFEDCBA9800A0CDDA02C835CDD25C5DC7072860E10B0E10BA060E10"; attribute INIT_31 of inst : label is "09409309209DDDDDDDDDBDDDBBBBBBBBBBB26868F0E2CA2FBB9444EDC78B10C1"; attribute INIT_32 of inst : label is "096097084095097083094097082093097081092090C09B09A099098097096095"; attribute INIT_33 of inst : label is "FFFF00708B09C09708A09B09708909A097088099097087098097086097097085"; attribute INIT_34 of inst : label is "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"; attribute INIT_35 of inst : label is "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"; attribute INIT_36 of inst : label is "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"; attribute INIT_37 of inst : label is "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"; attribute INIT_38 of inst : label is "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"; attribute INIT_39 of inst : label is "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"; attribute INIT_3A of inst : label is "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"; attribute INIT_3B of inst : label is "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"; attribute INIT_3C of inst : label is "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"; attribute INIT_3D of inst : label is "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"; attribute INIT_3E of inst : label is "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"; attribute INIT_3F of inst : label is "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"; begin inst : RAMB16_S4 --pragma translate_off generic map ( INIT_00 => romgen_str2bv(inst'INIT_00), INIT_01 => romgen_str2bv(inst'INIT_01), INIT_02 => romgen_str2bv(inst'INIT_02), INIT_03 => romgen_str2bv(inst'INIT_03), INIT_04 => romgen_str2bv(inst'INIT_04), INIT_05 => romgen_str2bv(inst'INIT_05), INIT_06 => romgen_str2bv(inst'INIT_06), INIT_07 => romgen_str2bv(inst'INIT_07), INIT_08 => romgen_str2bv(inst'INIT_08), INIT_09 => romgen_str2bv(inst'INIT_09), INIT_0A => romgen_str2bv(inst'INIT_0A), INIT_0B => romgen_str2bv(inst'INIT_0B), INIT_0C => romgen_str2bv(inst'INIT_0C), INIT_0D => romgen_str2bv(inst'INIT_0D), INIT_0E => romgen_str2bv(inst'INIT_0E), INIT_0F => romgen_str2bv(inst'INIT_0F), INIT_10 => romgen_str2bv(inst'INIT_10), INIT_11 => romgen_str2bv(inst'INIT_11), INIT_12 => romgen_str2bv(inst'INIT_12), INIT_13 => romgen_str2bv(inst'INIT_13), INIT_14 => romgen_str2bv(inst'INIT_14), INIT_15 => romgen_str2bv(inst'INIT_15), INIT_16 => romgen_str2bv(inst'INIT_16), INIT_17 => romgen_str2bv(inst'INIT_17), INIT_18 => romgen_str2bv(inst'INIT_18), INIT_19 => romgen_str2bv(inst'INIT_19), INIT_1A => romgen_str2bv(inst'INIT_1A), INIT_1B => romgen_str2bv(inst'INIT_1B), INIT_1C => romgen_str2bv(inst'INIT_1C), INIT_1D => romgen_str2bv(inst'INIT_1D), INIT_1E => romgen_str2bv(inst'INIT_1E), INIT_1F => romgen_str2bv(inst'INIT_1F), INIT_20 => romgen_str2bv(inst'INIT_20), INIT_21 => romgen_str2bv(inst'INIT_21), INIT_22 => romgen_str2bv(inst'INIT_22), INIT_23 => romgen_str2bv(inst'INIT_23), INIT_24 => romgen_str2bv(inst'INIT_24), INIT_25 => romgen_str2bv(inst'INIT_25), INIT_26 => romgen_str2bv(inst'INIT_26), INIT_27 => romgen_str2bv(inst'INIT_27), INIT_28 => romgen_str2bv(inst'INIT_28), INIT_29 => romgen_str2bv(inst'INIT_29), INIT_2A => romgen_str2bv(inst'INIT_2A), INIT_2B => romgen_str2bv(inst'INIT_2B), INIT_2C => romgen_str2bv(inst'INIT_2C), INIT_2D => romgen_str2bv(inst'INIT_2D), INIT_2E => romgen_str2bv(inst'INIT_2E), INIT_2F => romgen_str2bv(inst'INIT_2F), INIT_30 => romgen_str2bv(inst'INIT_30), INIT_31 => romgen_str2bv(inst'INIT_31), INIT_32 => romgen_str2bv(inst'INIT_32), INIT_33 => romgen_str2bv(inst'INIT_33), INIT_34 => romgen_str2bv(inst'INIT_34), INIT_35 => romgen_str2bv(inst'INIT_35), INIT_36 => romgen_str2bv(inst'INIT_36), INIT_37 => romgen_str2bv(inst'INIT_37), INIT_38 => romgen_str2bv(inst'INIT_38), INIT_39 => romgen_str2bv(inst'INIT_39), INIT_3A => romgen_str2bv(inst'INIT_3A), INIT_3B => romgen_str2bv(inst'INIT_3B), INIT_3C => romgen_str2bv(inst'INIT_3C), INIT_3D => romgen_str2bv(inst'INIT_3D), INIT_3E => romgen_str2bv(inst'INIT_3E), INIT_3F => romgen_str2bv(inst'INIT_3F) ) --pragma translate_on port map ( DO => DATA(3 downto 0), ADDR => rom_addr, CLK => CLK, DI => "0000", EN => '1', SSR => '0', WE => '0' ); end generate; rom1 : if true generate attribute INIT_00 of inst : label is "4444056C54080AA32080A58A3B5808EBCCED2C0BF1A3BEFF0D13A3BCE85AFAB4"; attribute INIT_01 of inst : label is "4FA45444BA554450A4543A4444440A4444559A55458A4458A554445BA45443A5"; attribute INIT_02 of inst : label is "444323554553035545530344432355455300003454524544305CCA334452A444"; attribute INIT_03 of inst : label is "525445524454FD26882A881A882A881AC32CB2C32CB200034444323554553003"; attribute INIT_04 of inst : label is "88A858A8A0A88880A888A888ABF8120148497FE4F028AF028AA120AAD26E3323"; attribute INIT_05 of inst : label is "65BF802FA886888AF1C8600A8A48AF1C8600A8ADD8C8AED8C8A8E0D8E88A858B"; attribute INIT_06 of inst : label is "71AC9F4235E8538EF92417CABD60DB0671AC9F4235E8538EF92417CABD606A6A"; attribute INIT_07 of inst : label is "71AC9F4235E8538EF92417CABD60DB0671AC9F4235E8538EF92417CABD60DB06"; attribute INIT_08 of inst : label is "71AC9F4235E8538EF92417CABD60DB0671AC9F4235E8538EF92417CABD60DB06"; attribute INIT_09 of inst : label is "71AC9F4235E8538EF92417CABD60DB0671AC9F4235E8538EF92417CABD60DB06"; attribute INIT_0A of inst : label is "333333333333222222222222222211111111111111110000000000000000DB06"; attribute INIT_0B of inst : label is "6666666666667777777777777777444444444444444455555555555555553333"; attribute INIT_0C of inst : label is "8888888888889999999999999999AAAAAAAAAAAAAAAABBBBBBBBBBBBBBBB6666"; attribute INIT_0D of inst : label is "DDDDDDDDDDDDCCCCCCCCCCCCCCCCFFFFFFFFFFFFFFFFEEEEEEEEEEEEEEEE8888"; attribute INIT_0E of inst : label is "81AC32CB2F54BB86FF02BBA46008AA008AA6BBAFF02BBA6008AA0089AA92DDDD"; attribute INIT_0F of inst : label is "2BB85AF02BB85A52525252C82585858580A580A583A580A580A584A583A582A5"; attribute INIT_10 of inst : label is "81AC32CB26ED8C8AED8C8A8E0D8EBB88BFF02BBA0A888A888AA02A12AD2FE4F0"; attribute INIT_11 of inst : label is "0A0A2FFD8FDC0D02BBA0A1DFF02BBA88880A888A888AE00454424445FD2882A8"; attribute INIT_12 of inst : label is "4442200FD2F028AF028AE2355455FD2CD8ECD8E88A8589BBA88A858A8AB0804B"; attribute INIT_13 of inst : label is "32CB2A04E234542200FD2886888AF1C8600A8A48AF1C8600A8AF028AF028AE23"; attribute INIT_14 of inst : label is "444FD2FE2F02881AF02882AE244542FD2F02881AE2444424454455FD2C32CB2C"; attribute INIT_15 of inst : label is "8B0AE0022244444454455005FD26E004455444004FD21F5CFE2E232425224544"; attribute INIT_16 of inst : label is "AAA85ABF80AA58AABF80AA588ABF80AAA85ABF80AA58AABF80A7204FD9CC209A"; attribute INIT_17 of inst : label is "BF88AA58AABF80AAA85ABF80AA58AABF80A0A88AA880AFD8FDC0A0AA083ABF88"; attribute INIT_18 of inst : label is "2FF6BF80A204FD0CC209A3B0AC54080A665BF802FACDBC8A8E8EDDCFDC0A898B"; attribute INIT_19 of inst : label is "454FD2C1A3BEECFE2FDCFF20FA8BFD0CEAFF22AFDEFF203A3BFF22A0A0AFE2AF"; attribute INIT_1A of inst : label is "B309A8B0A6E00323333224544420033332244444420033333324544200354454"; attribute INIT_1B of inst : label is "8A888A2020A88BA88AA88880A2283A2280A2283A2280AFD6CC209A1BFDC309A8"; attribute INIT_1C of inst : label is "A0D8C8A6CDAEEFE2A32FF22AF028AF028AFF22AF021282F2C8A0D8C8A2028A88"; attribute INIT_1D of inst : label is "19CFDC0F8BEFFCCC8388B6FDCFF20F8BC0D8C8B1D8CC8B0A88AA888AAF40D8C8"; attribute INIT_1E of inst : label is "425444440445424445444E8044542544444AA044542445444D7CD8886A0A8886"; attribute INIT_1F of inst : label is "24454424442103232445442444D503232445442444E5032324454424441F0445"; attribute INIT_20 of inst : label is "445B4033235255423444454920444454524445444FB044445452544444450323"; attribute INIT_21 of inst : label is "4444903323525444551035254444425442444EB0323525444B10332352554254"; attribute INIT_22 of inst : label is "44BF044442454444F04444245444FE04444245444BC044442454445104444245"; attribute INIT_23 of inst : label is "FE04445452444100545444424449404545245444B203344245444CF033442454"; attribute INIT_24 of inst : label is "4454430323524442B0323524449B032352444EF0554445524247604445452444"; attribute INIT_25 of inst : label is "454544BF05444445D03554CE0443235255444452444454780323525544445244"; attribute INIT_26 of inst : label is "45C60332352544455446905445446003235254449404454544C7044545441304"; attribute INIT_27 of inst : label is "3235244545CE032352445455203235244444597032352544554E033235244544"; attribute INIT_28 of inst : label is "810445454424454455740544444525569054444452556004454454555255BB03"; attribute INIT_29 of inst : label is "2444555A05444244455540544424445519045444244455060445454424454455"; attribute INIT_2A of inst : label is "4445FF03235255444552544445F104454524544545F405544455255454905444"; attribute INIT_2B of inst : label is "0DA220AA221F0C1F1C13EA1F1C1F0CFF40ABE88A008AA008FA008AA008EA0454"; attribute INIT_2C of inst : label is "A72A24AC2E1D9F622AAC2F44E80AA72095CCD9F62640316192CF146F14F04A14"; attribute INIT_2D of inst : label is "398CDADAAF4AE22B0202F94E82A1A24AC2F74FDCA728098092AB080AE88AE1EA"; attribute INIT_2E of inst : label is "9D8566F18D92A4AA92FDC8B980BF62FDC7B980BF625AE82AFBF720D803EA393C"; attribute INIT_2F of inst : label is "05B02E8E8D062EAEA6AE2E8E8D40FF26DC0BD85EA44660D8EDA0DDA4A1186DE0"; attribute INIT_30 of inst : label is "10000000710000000006F9A2DC0E69E8A5BE8A4BA221A9FBF72FBF72F82F9F72"; attribute INIT_31 of inst : label is "09809809809FFFFFFFFFAFFFAAAAAAAAAAACCCDDDCAE69DD2566245313232211"; attribute INIT_32 of inst : label is "B980BFDC8B980BFDC8B980BFDC8B980BFDC8B980B68098098098098098098098"; attribute INIT_33 of inst : label is "FFFF06FDC8B980BFDC8B980BFDC8B980BFDC8B980BFDC8B980BFDC8B980BFDC8"; attribute INIT_34 of inst : label is "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"; attribute INIT_35 of inst : label is "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"; attribute INIT_36 of inst : label is "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"; attribute INIT_37 of inst : label is "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"; attribute INIT_38 of inst : label is "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"; attribute INIT_39 of inst : label is "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"; attribute INIT_3A of inst : label is "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"; attribute INIT_3B of inst : label is "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"; attribute INIT_3C of inst : label is "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"; attribute INIT_3D of inst : label is "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"; attribute INIT_3E of inst : label is "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"; attribute INIT_3F of inst : label is "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"; begin inst : RAMB16_S4 --pragma translate_off generic map ( INIT_00 => romgen_str2bv(inst'INIT_00), INIT_01 => romgen_str2bv(inst'INIT_01), INIT_02 => romgen_str2bv(inst'INIT_02), INIT_03 => romgen_str2bv(inst'INIT_03), INIT_04 => romgen_str2bv(inst'INIT_04), INIT_05 => romgen_str2bv(inst'INIT_05), INIT_06 => romgen_str2bv(inst'INIT_06), INIT_07 => romgen_str2bv(inst'INIT_07), INIT_08 => romgen_str2bv(inst'INIT_08), INIT_09 => romgen_str2bv(inst'INIT_09), INIT_0A => romgen_str2bv(inst'INIT_0A), INIT_0B => romgen_str2bv(inst'INIT_0B), INIT_0C => romgen_str2bv(inst'INIT_0C), INIT_0D => romgen_str2bv(inst'INIT_0D), INIT_0E => romgen_str2bv(inst'INIT_0E), INIT_0F => romgen_str2bv(inst'INIT_0F), INIT_10 => romgen_str2bv(inst'INIT_10), INIT_11 => romgen_str2bv(inst'INIT_11), INIT_12 => romgen_str2bv(inst'INIT_12), INIT_13 => romgen_str2bv(inst'INIT_13), INIT_14 => romgen_str2bv(inst'INIT_14), INIT_15 => romgen_str2bv(inst'INIT_15), INIT_16 => romgen_str2bv(inst'INIT_16), INIT_17 => romgen_str2bv(inst'INIT_17), INIT_18 => romgen_str2bv(inst'INIT_18), INIT_19 => romgen_str2bv(inst'INIT_19), INIT_1A => romgen_str2bv(inst'INIT_1A), INIT_1B => romgen_str2bv(inst'INIT_1B), INIT_1C => romgen_str2bv(inst'INIT_1C), INIT_1D => romgen_str2bv(inst'INIT_1D), INIT_1E => romgen_str2bv(inst'INIT_1E), INIT_1F => romgen_str2bv(inst'INIT_1F), INIT_20 => romgen_str2bv(inst'INIT_20), INIT_21 => romgen_str2bv(inst'INIT_21), INIT_22 => romgen_str2bv(inst'INIT_22), INIT_23 => romgen_str2bv(inst'INIT_23), INIT_24 => romgen_str2bv(inst'INIT_24), INIT_25 => romgen_str2bv(inst'INIT_25), INIT_26 => romgen_str2bv(inst'INIT_26), INIT_27 => romgen_str2bv(inst'INIT_27), INIT_28 => romgen_str2bv(inst'INIT_28), INIT_29 => romgen_str2bv(inst'INIT_29), INIT_2A => romgen_str2bv(inst'INIT_2A), INIT_2B => romgen_str2bv(inst'INIT_2B), INIT_2C => romgen_str2bv(inst'INIT_2C), INIT_2D => romgen_str2bv(inst'INIT_2D), INIT_2E => romgen_str2bv(inst'INIT_2E), INIT_2F => romgen_str2bv(inst'INIT_2F), INIT_30 => romgen_str2bv(inst'INIT_30), INIT_31 => romgen_str2bv(inst'INIT_31), INIT_32 => romgen_str2bv(inst'INIT_32), INIT_33 => romgen_str2bv(inst'INIT_33), INIT_34 => romgen_str2bv(inst'INIT_34), INIT_35 => romgen_str2bv(inst'INIT_35), INIT_36 => romgen_str2bv(inst'INIT_36), INIT_37 => romgen_str2bv(inst'INIT_37), INIT_38 => romgen_str2bv(inst'INIT_38), INIT_39 => romgen_str2bv(inst'INIT_39), INIT_3A => romgen_str2bv(inst'INIT_3A), INIT_3B => romgen_str2bv(inst'INIT_3B), INIT_3C => romgen_str2bv(inst'INIT_3C), INIT_3D => romgen_str2bv(inst'INIT_3D), INIT_3E => romgen_str2bv(inst'INIT_3E), INIT_3F => romgen_str2bv(inst'INIT_3F) ) --pragma translate_on port map ( DO => DATA(7 downto 4), ADDR => rom_addr, CLK => CLK, DI => "0000", EN => '1', SSR => '0', WE => '0' ); end generate; end RTL;
apache-2.0
edf31bab279cba9ad0e5c50200285e15
0.729835
3.466582
false
false
false
false
abyrne55/my-little-processor
instantiate.vhd
1
3,029
LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY instantiate IS PORT ( SW : IN STD_LOGIC_VECTOR(17 DOWNTO 0); KEY : IN STD_LOGIC_VECTOR(3 DOWNTO 0); LEDR : OUT STD_LOGIC_VECTOR(17 DOWNTO 0); LEDG : OUT STD_LOGIC_VECTOR(8 DOWNTO 0); HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) ); END; ARCHITECTURE behavioural OF instantiate IS SIGNAL done : std_logic; SIGNAL not_key : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL read_addr : STD_LOGIC_VECTOR(15 DOWNTO 0); SIGNAL func : STD_LOGIC_VECTOR(15 DOWNTO 0); SIGNAL flag : std_logic; SIGNAL reg0_out : std_logic_vector(15 DOWNTO 0); SIGNAL reg1_out : std_logic_vector(15 DOWNTO 0); SIGNAL c_state : INTEGER; COMPONENT binaryto4hex IS PORT ( binary : IN STD_LOGIC_VECTOR(15 DOWNTO 0); output0, output1, output2, output3 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) ); END COMPONENT; COMPONENT ram_16bit IS PORT ( clock : IN STD_LOGIC; done : IN STD_LOGIC; data : IN STD_LOGIC_VECTOR (15 DOWNTO 0); write_addr : IN STD_LOGIC_VECTOR (15 DOWNTO 0); read_addr : IN STD_LOGIC_VECTOR (15 DOWNTO 0); write_enable : IN STD_LOGIC; q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0) ); END COMPONENT; COMPONENT my_little_processor IS PORT ( clock, reset : IN STD_LOGIC; data_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0); flag_out, done_out : OUT STD_LOGIC; read_addr, reg0_out, reg1_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); c_state : OUT INTEGER ); END COMPONENT; BEGIN ram : ram_16bit PORT MAP( clock => not_key(2), done => done, data => "0000000000000000", write_addr => "0000000000000000", read_addr => read_addr, write_enable => '0', q => func ); processor : my_little_processor PORT MAP( clock => not_key(2), reset => not_key(1), data_in => func, flag_out => flag, done_out => done, read_addr => read_addr, reg0_out => reg0_out, reg1_out => reg1_out, c_state => c_state ); bintohex0 : binaryto4hex PORT MAP( binary => reg1_out, output0 => HEX0, output1 => HEX1, output2 => HEX2, output3 => HEX3 ); bintohex1 : binaryto4hex PORT MAP( binary => reg0_out, output0 => HEX4, output1 => HEX5, output2 => HEX6, output3 => HEX7 ); -- Negate key state (not_key[0] = 1 when KEY0 is pressed) not_key <= NOT KEY; -- Assign LEDG's above KEYs to current state LEDG(7 DOWNTO 0) <= std_logic_vector(to_unsigned(c_state, 8)); LEDG(8) <= not_key(2); --Assign current instruction to 16 LEDs LEDR(15 DOWNTO 0) <= func; -- Assign the flag LEDR(17) <= flag; LEDR(16) <= flag; END behavioural;
mit
2e88476bfd4a3514df390bb186a9c0d5
0.562892
3.038114
false
false
false
false
GSimas/EEL5105
Rep CAEE/11.2.Projeto/_PROJETO/input_control.vhd
1
3,924
-- ALUNOS: -- Bruno Luiz da Silva -- Gustavo Fernades -- -- -- TÍTULO: -- Controle de entradas -- -- -- RESUMO: -- Bloco que envia a sua entrada para um dos registradores desejados dependendo somente dos argumentos dados -- -- -- ENTRADAS/SAÍDAS (I/O): -- (I) a: as chaves SW serão conectadas aqui e posteriormente enviadas para certos componentes dependendo de -- "arguments". -- (I) reg: a parte alta da saída do registrador de 16 bits será conectada aqui para então alimentar certas -- partes do componente de multiplicação, como por exemplo o bloco de adição e deslocamento. -- (I) arguments: argumentos que serão dados (valores de 3 bits) os quais serão interpretados e darão um valor -- lógico alto para uma porta de habilitação específica e as outras receberão valor lógico baixo. -- (I) clk,rst: clock e reset, sendo que o reset zera todas saídas. -- (O) l1,l2,s1,shift,n1: saídas que serão conectadas nas portas de habilitação dos outros componentes. -- (O) q: saída de dados que será ou o valor "a" ou "reg". -- -- -- DESCRIÇÃO: -- As entradas "a" e "reg" serão enviadas para a saída, sendo essa redirecionada para alguns componentes. Para -- escolher qual componente "receberá" o dado deve-se enviar um argumento (comando de 3 bits) para esse componente -- (input_control) sendo que a cada valor desse argumento um componente diferente será habilitado. Segue a relação: -- -- 000: nada -- 001: saída será "a" e l1 (load 1) será alto - carregará o registrador de 8 bits -- 010: saída será "a" e s1 (start) será alto - carregará a parte baixa do registrador de 16 bits -- 011: saída será "reg" e l2 será alto - ativa o somador e o registrador de 16 bits, sendo que a soma realizada -- será entre o valor do registrador de 8 bits com "reg" que será a parte alta do registrador de 16 bits. -- O resultado da soma é enviado para a parte alta do registrador de 16 bits que estará ativado enquanto l2 -- for alto. -- 100: shift será alto - habilitará o deslocamento do registrador de 16 bits, deslocando os bits a esquerda -- 101: normalize será alto - habilitará a normalização do registrador de 16 bits, normalizando o valor armazenado. -- -- -- ANEXO: -- Ainda existem mais dois argumentos porém eles não fazem nenhuma operação aqui. São eles: -- -- 110: realiza a soma entre os dois expoentes dados (a e b). -- 111: realiza a subtração do atual valor guardado (soma de a e b) com o número de deslocamentos -- realizados na normalização da mantissa. -- -- -- (I): INPUT / (O): OUTPUT library ieee; use ieee.std_logic_1164.all; entity input_control is generic(N: natural := 8); port( a,reg: in std_logic_vector((N-1) downto 0); -- Dados de entrada arguments: in std_logic_vector(2 downto 0); -- Argumentos clk,rst: in std_logic; -- Clock, reset l1,l2,s1,shift,n1: out std_logic; -- Saída de controle q: out std_logic_vector((N-1) downto 0) -- Saída de dados ); end input_control; architecture func of input_control is begin INPUT: process(a,reg) begin if(rst = '1') then q <= (others => '0'); else -- Checar lista da DESCRIÇÃO para entender o que cada argumento realiza case arguments is when "001" => q <= a; l1 <= '1'; s1 <= '0'; l2 <= '0'; shift <= '0'; n1 <= '0'; when "010" => q <= a; l1 <= '0'; s1 <= '1'; l2 <= '0'; shift <= '0'; n1 <= '0'; when "011" => q <= reg; l1 <= '0'; s1 <= '0'; l2 <= '1'; shift <= '0'; n1 <= '0'; when "100" => l1 <= '0'; s1 <= '0'; l2 <= '0'; shift <= '1'; n1 <= '0'; when "101" => l1 <= '0'; s1 <= '0'; l2 <= '0'; shift <= '0'; n1 <= '1'; when others => q <= (others => '0'); l1 <= '0'; s1 <= '0'; l2 <= '0'; shift <= '0'; n1 <= '0'; end case; end if; end process; end func;
mit
590dae87eec96dbeedb38a6f5a258b34
0.627676
2.823022
false
false
false
false
hoglet67/AtomFpga
src/common/RamRom_None.vhd
1
1,853
-------------------------------------------------------------------------------- -- Copyright (c) 2016 David Banks -------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / -- \ \ \/ -- \ \ -- / / Filename : RamRom_None -- /___/ /\ Timestamp : 04/07/2016 -- \ \ / \ -- \___\/\___\ -- --Design Name: RamRom_None library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; entity RamRom_None is port (clock : in std_logic; reset_n : in std_logic; -- signals from/to 6502 cpu_addr : in std_logic_vector (15 downto 0); cpu_we : in std_logic; cpu_dout : in std_logic_vector (7 downto 0); cpu_din : out std_logic_vector (7 downto 0); -- signals from/to external memory system ExternCE : out std_logic; ExternWE : out std_logic; ExternA : out std_logic_vector (18 downto 0); ExternDin : out std_logic_vector (7 downto 0); ExternDout : in std_logic_vector (7 downto 0) ); end RamRom_None; architecture behavioral of RamRom_None is signal RamCE : std_logic; signal RomCE : std_logic; begin RamCE <= '1' when cpu_addr(15) = '0' else '0'; RomCE <= '1' when cpu_addr(15 downto 14) = "11" else '1' when cpu_addr(15 downto 12) = "1010" else '0'; ExternCE <= RamCE or RomCE; ExternWE <= cpu_we and RamCE; ExternA <= "000" & cpu_addr(15 downto 0); ExternDin <= cpu_dout; cpu_din <= ExternDout; end behavioral;
apache-2.0
1e15a870d24b7c78996e04e5edff8939
0.432812
3.713427
false
false
false
false
bertuccio/ARQ
Practica2/procesador.vhd
1
9,065
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_UNSIGNED.all; entity procesador is port( Clk : in std_logic; Reset : in std_logic; -- Instruction memory I_Addr : out std_logic_vector(31 downto 0); I_RdStb : out std_logic; I_WrStb : out std_logic; I_AddrStb : out std_logic; I_DataOut : out std_logic_vector(31 downto 0); I_Rdy : in std_logic; I_DataIn : in std_logic_vector(31 downto 0); -- Data memory D_Addr : out std_logic_vector(31 downto 0); D_RdStb : out std_logic; D_WrStb : out std_logic; D_AddrStb : out std_logic; D_DataOut : out std_logic_vector(31 downto 0); D_Rdy : in std_logic; D_DataIn : in std_logic_vector(31 downto 0) ); end procesador; architecture procesador_arq of procesador is ------------------------ ------COMPONENTES------- ------------------------ component tabla_registros PORT ( CLK : in STD_LOGIC; Reset : in STD_LOGIC; EscrReg : in STD_LOGIC; reg_lec1 : in STD_LOGIC_VECTOR (4 downto 0); reg_lec2 : in STD_LOGIC_VECTOR (4 downto 0); reg_escr: in STD_LOGIC_VECTOR (4 downto 0); dato_escr : in STD_LOGIC_VECTOR (31 downto 0); dato_leido1 : out STD_LOGIC_VECTOR (31 downto 0); dato_leido2 : out STD_LOGIC_VECTOR (31 downto 0)); end component; component ALU PORT ( A : in STD_LOGIC_VECTOR (31 downto 0); B : in STD_LOGIC_VECTOR (31 downto 0); control : in STD_LOGIC_VECTOR (3 downto 0); resultado : out STD_LOGIC_VECTOR (31 downto 0); igual : out STD_LOGIC); end component; ------------------ -----SEÑALES------ ------------------ signal PC_IN : STD_LOGIC_VECTOR (31 downto 0); signal PC_IN1 : STD_LOGIC_VECTOR (31 downto 0); signal PC_IN2 : STD_LOGIC_VECTOR (31 downto 0); signal addResultIN : STD_LOGIC_VECTOR (31 downto 0); signal addResultOUT : STD_LOGIC_VECTOR (31 downto 0); signal MemMux1 : STD_LOGIC_VECTOR (31 downto 0); signal MemMux2 : STD_LOGIC_VECTOR (31 downto 0); -------ALU----------------------------------------- signal OpA : STD_LOGIC_VECTOR (31 downto 0); signal OpB : STD_LOGIC_VECTOR (31 downto 0); signal mux1OpB: STD_LOGIC_VECTOR (31 downto 0); signal mux2OpB: STD_LOGIC_VECTOR (31 downto 0); signal AluControl : STD_LOGIC_VECTOR (5 downto 0); signal ALUctr : STD_LOGIC_VECTOR (3 downto 0); signal Zero : STD_LOGIC; signal AluResultIN : STD_LOGIC_VECTOR (31 downto 0); signal AluResultOUT : STD_LOGIC_VECTOR (31 downto 0); --------------------------------------------------- --------------CONTROL---------------------------- signal Control: STD_LOGIC_VECTOR (5 downto 0); ------EX------------ signal EXctr : std_logic_vector(3 downto 0); signal RegDst: STD_LOGIC; signal ALUOp: STD_LOGIC_VECTOR (1 downto 0); signal AluSrc : STD_LOGIC; -------M------------ signal Mctr : std_logic_vector(2 downto 0); signal Mctr1 : std_logic_vector(2 downto 0); signal Mctr2 : std_logic_vector(2 downto 0); signal PCSrc : STD_LOGIC; ------WB------------ signal WEctr : std_logic_vector(1 downto 0); signal WEctr1 : std_logic_vector(1 downto 0); signal WEctr2 : std_logic_vector(1 downto 0); signal EscrReg : STD_LOGIC; signal MemToReg : STD_LOGIC; --------------------------------------------------- signal signo_extend: STD_LOGIC_VECTOR (31 downto 0); signal reg_lect1IF : STD_LOGIC_VECTOR (4 downto 0); signal reg_lect2IF : STD_LOGIC_VECTOR (4 downto 0); signal rdInstCarg : STD_LOGIC_VECTOR (4 downto 0); signal rdInstALU : STD_LOGIC_VECTOR (4 downto 0); signal reg_escr: STD_LOGIC_VECTOR (4 downto 0); signal reg_escrIN: STD_LOGIC_VECTOR (4 downto 0); signal dato_leido1 : STD_LOGIC_VECTOR (31 downto 0); signal dato_leido2 : STD_LOGIC_VECTOR (31 downto 0); signal dato_escr : STD_LOGIC_VECTOR (31 downto 0); signal RegEscribir1 : STD_LOGIC_VECTOR (4 downto 0); signal RegEscribir2 : STD_LOGIC_VECTOR (4 downto 0); signal mux_aux1 : STD_LOGIC_VECTOR (4 downto 0); signal mux_aux2 : STD_LOGIC_VECTOR (4 downto 0); begin ----------------- ----PORT-MAPS---- ----------------- --BANCO REGISTROS-- BANCO: tabla_registros port map( CLK => Clk, Reset => Reset, EscrReg => EscrReg, reg_lec1 => reg_lect1IF, reg_lec2 => reg_lect2IF, reg_escr => reg_escr, dato_escr => dato_escr, dato_leido1 => dato_leido1, dato_leido2 => dato_leido2); --ALU-- UAL : ALU port map( A => OpA, B => OpB, control => ALUctr, resultado => AluResultIN, igual => Zero); I_RdStb<='1'; I_WrStb<='0'; I_AddrStb<='1'; D_AddrStb<='1'; I_Addr<=PC_IN; I_DataOut<=x"00000000"; ------------------------------ ----CONTADOR DE PROGRAMA------ ------------------------------ process(Clk,Reset) begin if Reset='1' then PC_IN<=x"00000000"; else if rising_edge(Clk) then if (PCSrc='1') then PC_IN<=addResultOUT; else PC_IN<=PC_IN+4; end if; end if; end if; end process; ----------------------- ---PRIMER PIPE (IF)---- ----------------------- process (Clk,Reset) begin if (Reset='1') then PC_IN1<=x"00000000"; Control<= "000000"; reg_lect1IF<="00000"; reg_lect2IF<="00000"; rdInstCarg<= "00000"; rdInstALU<= "00000"; signo_extend<=x"00000000"; else if rising_edge(Clk) then PC_IN1<=PC_IN; Control <= I_DataIn(31 downto 26); reg_lect1IF <=I_DataIn(25 downto 21); reg_lect2IF <=I_DataIn(20 downto 16); rdInstCarg <= I_DataIn(20 downto 16); rdInstALU <= I_DataIn(15 downto 11); if I_DataIn(15)='1' then signo_extend<=x"FFFF"&I_DataIn(15 downto 0); else signo_extend<=x"0000"&I_DataIn(15 downto 0); end if; end if; end if; end process; ----------------------- ---SEGUNDO PIPE (EX)-- ----------------------- process (Clk,Reset) begin if (Reset='1') then WEctr1<="00"; Mctr1<="000"; ALUOp<="00"; ALUcontrol<="000000"; OpA<=x"00000000"; mux1OpB<=x"00000000"; mux2OpB<=x"00000000"; mux_aux1<="00000"; mux_aux2<="00000"; addResultIN<=x"00000000"; AluSrc<='0'; RegDst<='0'; else if rising_edge(Clk) then WEctr1<=WEctr; Mctr1<=Mctr; ALUcontrol<=signo_extend(5 downto 0); mux2OpB<=signo_extend; addResultIN<=signo_extend(29 downto 0)&"00"+PC_IN1; OpA<=dato_leido1; mux1OpB<=dato_leido2; mux_aux1<=rdInstCarg; mux_aux2<=rdInstALU; RegDst<=EXctr(3); ALUOp<=EXctr(2 downto 1); AluSrc<=EXctr(0); end if; end if; end process; ----------MULTIPLEXORES-------------- WITH AluSrc SELECT OpB <=mux1OpB WHEN '0', mux2OpB WHEN OTHERS; WITH RegDst SELECT regEscribir1 <=mux_aux1 WHEN '0', mux_aux2 WHEN OTHERS; WITH MemToReg SELECT dato_escr <=MemMux2 WHEN '0', MemMux1 WHEN OTHERS; ------------------------------------ ----------------------- ---TERCER PIPE (MEM)-- ----------------------- process (Clk,Reset) begin if (Reset='1') then addResultOUT<=x"00000000"; D_WrStb<='0';--memwrite D_RdStb<='0';--memread PCSrc<='0'; D_DataOut<=x"00000000"; aluResultOUT<=x"00000000"; WEctr2<="00"; regEscribir2<="00000"; D_Addr<=x"00000000"; else if rising_edge(Clk) then WEctr2<=WEctr1; addResultOUT<=addResultIN; D_WrStb<=Mctr1(0);--memwrite D_RdStb<=Mctr1(1);--memread PCSrc<=Mctr1(2) and Zero; D_Addr<=AluResultIN; aluResultOUT<=AluResultIN; D_DataOut<=mux1OpB; regEscribir2<=regEscribir1; end if; end if; end process; ------------------- ----REGISTRO 4----- ------------------- process (Clk) begin if (Reset='1') then MemMux1<=x"00000000"; MemMux2<=x"00000000"; reg_escr<="00000"; MemToReg<='0'; EscrReg<='0'; else if rising_edge(Clk) then MemMux1<=D_DataIn; MemMux2<=aluResultOUT; reg_escr<=regEscribir2; MemToReg<=WEctr2(0); EscrReg<=WEctr2(1); end if; end if; end process; process (ALUOp, ALUcontrol) begin case ALUOp is when "10"=>--REG_A_REG case ALUcontrol is when "100000"=>--ADD ALUctr<="0011"; when "100010"=>--SUB ALUctr<="1000"; when "100100"=>--AND ALUctr<="0000"; when "100101"=>--OR ALUctr<="0001"; when "100110"=>--XOR ALUctr<="0010"; when "101010"=>--SLT ALUctr<="1010"; when others => ALUctr<="1111"; end case; when "00"=>--LW ó SW ALUctr<="0011";--ADD PARA CONSEGUIR LA DIRECCION DE MEMORIA when "01"=>--BEQ ALUctr<="0010";--XOR PARA VER SI RS Y RT SON IGUALES when "11"=>--LIU ALUctr<="1001"; when others => ALUctr<="1111"; end case; end process; process (Control) begin case Control is when "000000"=> --SPECIAL (R) EXctr<="1100"; Mctr<="000"; WEctr<="10"; when "100011"=> --LW EXctr<="0001"; Mctr<="010"; WEctr<="11"; when "101011"=> --SW EXctr<="0001"; Mctr<="001"; WEctr<="00"; when "001111"=> --LIU EXctr<="0110"; Mctr<="000"; WEctr<="10"; when "000100"=> --BE EXctr<="0010"; Mctr<="100"; WEctr<="00"; when others => EXctr<="0000"; Mctr<="000"; WEctr<="00"; end case; end process; end procesador_arq;
mit
abf02a6cb0636dc22960d7dfd46f4338
0.580585
2.974081
false
false
false
false
bertuccio/ARQ
Practica5/banco.vhd
3
1,946
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity tabla_registros is PORT( CLK : in std_logic; -- Reloj EscrReg : in std_logic; -- Habilitacion escritura Reset : in std_logic; -- Reset asíncrono a nivel alto reg_lec1 : in std_logic_vector(4 downto 0); -- Direccion lectura 1 reg_lec2 : in std_logic_vector(4 downto 0); -- Direccion lectura 2 reg_escr : in std_logic_vector(4 downto 0); -- Direccion escritura 1 dato_escr : in std_logic_vector(31 downto 0); -- Dato entrada escritura dato_leido1 : out std_logic_vector(31 downto 0); -- Dato salida 1 dato_leido2 : out std_logic_vector(31 downto 0)); -- Dato salida 2 end tabla_registros; architecture Behavioral of tabla_registros is type Matriz is array (0 to 31) of std_logic_vector(31 downto 0); signal banco: matriz; constant ZERO: std_logic_vector(31 downto 0):=x"00000000"; constant TAMANO : integer:=31; begin process(CLK,Reset) begin if(Reset='1') then for i in 0 to TAMANO loop banco(i)<=(others=>'0'); end loop; else --Escribir en registro if (falling_edge(CLK)and EscrReg='1') then banco(conv_integer(reg_escr(4 downto 0)))<=dato_escr(31 downto 0); end if; end if; end process; --Lectura combinacional dato_leido1<=ZERO(31 downto 0) when(reg_lec1=ZERO(4 downto 0)) else banco(conv_integer(reg_lec1(4 downto 0))); dato_leido2<=ZERO(31 downto 0) when(reg_lec2=ZERO(4 downto 0)) else banco(conv_integer(reg_lec2(4 downto 0))); end architecture;
mit
2b30ac070d0571d377fd481039e97d0c
0.553957
3.706667
false
false
false
false
GSimas/EEL5105
Eletr-Digital/Projeto Final/PROJETO COFRE FUNCIONANDO/BuzzerMi.vhd
1
4,562
-- megafunction wizard: %LPM_COUNTER% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: lpm_counter -- ============================================================ -- File Name: BuzzerMi.vhd -- Megafunction Name(s): -- lpm_counter -- -- Simulation Library Files(s): -- lpm -- ============================================================ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- -- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition -- ************************************************************ --Copyright (C) 1991-2010 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject --to the terms and conditions of the Altera Program License --Subscription Agreement, Altera MegaCore Function License --Agreement, or other applicable license agreement, including, --without limitation, that your use is for the sole purpose of --programming logic devices manufactured by Altera and sold by --Altera or its authorized distributors. Please refer to the --applicable agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY lpm; USE lpm.all; ENTITY BuzzerMi IS PORT ( clock : IN STD_LOGIC ; cout : OUT STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (29 DOWNTO 0) ); END BuzzerMi; ARCHITECTURE SYN OF buzzermi IS SIGNAL sub_wire0 : STD_LOGIC ; SIGNAL sub_wire1 : STD_LOGIC_VECTOR (29 DOWNTO 0); COMPONENT lpm_counter GENERIC ( lpm_direction : STRING; lpm_modulus : NATURAL; lpm_port_updown : STRING; lpm_type : STRING; lpm_width : NATURAL ); PORT ( clock : IN STD_LOGIC ; cout : OUT STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (29 DOWNTO 0) ); END COMPONENT; BEGIN cout <= sub_wire0; q <= sub_wire1(29 DOWNTO 0); lpm_counter_component : lpm_counter GENERIC MAP ( lpm_direction => "UP", lpm_modulus => 75757, lpm_port_updown => "PORT_UNUSED", lpm_type => "LPM_COUNTER", lpm_width => 30 ) PORT MAP ( clock => clock, cout => sub_wire0, q => sub_wire1 ); END SYN; -- ============================================================ -- CNX file retrieval info -- ============================================================ -- Retrieval info: PRIVATE: ACLR NUMERIC "0" -- Retrieval info: PRIVATE: ALOAD NUMERIC "0" -- Retrieval info: PRIVATE: ASET NUMERIC "0" -- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1" -- Retrieval info: PRIVATE: CLK_EN NUMERIC "0" -- Retrieval info: PRIVATE: CNT_EN NUMERIC "0" -- Retrieval info: PRIVATE: CarryIn NUMERIC "0" -- Retrieval info: PRIVATE: CarryOut NUMERIC "1" -- Retrieval info: PRIVATE: Direction NUMERIC "0" -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" -- Retrieval info: PRIVATE: ModulusCounter NUMERIC "1" -- Retrieval info: PRIVATE: ModulusValue NUMERIC "75757" -- Retrieval info: PRIVATE: SCLR NUMERIC "0" -- Retrieval info: PRIVATE: SLOAD NUMERIC "0" -- Retrieval info: PRIVATE: SSET NUMERIC "0" -- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: nBit NUMERIC "30" -- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP" -- Retrieval info: CONSTANT: LPM_MODULUS NUMERIC "75757" -- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER" -- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "30" -- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock -- Retrieval info: USED_PORT: cout 0 0 0 0 OUTPUT NODEFVAL cout -- Retrieval info: USED_PORT: q 0 0 30 0 OUTPUT NODEFVAL q[29..0] -- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 -- Retrieval info: CONNECT: q 0 0 30 0 @q 0 0 30 0 -- Retrieval info: CONNECT: cout 0 0 0 0 @cout 0 0 0 0 -- Retrieval info: LIBRARY: lpm lpm.lpm_components.all -- Retrieval info: GEN_FILE: TYPE_NORMAL BuzzerMi.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL BuzzerMi.inc TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL BuzzerMi.cmp TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL BuzzerMi.bsf TRUE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL BuzzerMi_inst.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL BuzzerMi_waveforms.html TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL BuzzerMi_wave*.jpg FALSE -- Retrieval info: LIB_FILE: lpm
mit
07d77dbc3320ead41bcd891400d99d09
0.655633
3.664257
false
false
false
false
GSimas/EEL5105
PROJETO-EEL5105/Projeto/decod7seg.vhd
1
1,584
library IEEE; use IEEE.Std_Logic_1164.all; --Decodificador 5bits para Display LED 7 segmentos entity decod7seg is port (C: in std_logic_vector(4 downto 0); F: out std_logic_vector(6 downto 0) ); end decod7seg; --Definicao de arquitetura architecture decod of decod7seg is begin F <= "1000000" when C = "00000" else -- 0 "1111001" when C = "00001" else -- 1 "0100100" when C = "00010" else -- 2 "0110000" when C = "00011" else -- 3 "0011001" when C = "00100" else -- 4 "0010010" when C = "00101" else -- 5 "0000010" when C = "00110" else -- 6 "1111000" when C = "00111" else -- 7 "0000000" when C = "01000" else -- 8 "0010000" when C = "01001" else -- 8 "0001000" when C = "01010" else -- A "0000011" when C = "01011" else -- b "1000110" when C = "01100" else -- C "0100001" when C = "01101" else -- d "0000110" when C = "01110" else -- E "0001110" when C = "01111" else -- F "0010000" when C = "10000" else -- g "0001001" when C = "10001" else -- H "0000110" when C = "10010" else -- I "1100001" when C = "10011" else -- J "0000101" when C = "10100" else -- K "1000111" when C = "10101" else -- L "0101011" when C = "10110" else -- m "1001000" when C = "10111" else -- N "1000000" when C = "11000" else -- O "0001100" when C = "11001" else -- P "0011000" when C = "11010" else -- q "0101111" when C = "11011" else -- r "0010010" when C = "11100" else -- S "0000111" when C = "11101" else -- t "1111111" when C = "11110" else -- U "1000001"; end decod;
mit
3dec24f0bc221425c78a62a8f5870cef
0.57702
2.938776
false
false
false
false
hoglet67/AtomFpga
src/common/T6502/T65_ALU.vhd
1
9,755
-- **** -- T65(b) core. In an effort to merge and maintain bug fixes .... -- -- See list of changes in T65 top file (T65.vhd)... -- -- **** -- 65xx compatible microprocessor core -- -- FPGAARCADE SVN: $Id: T65_ALU.vhd 2653 2018-06-05 18:14:10Z gary.mups $ -- -- Copyright (c) 2002...2015 -- Daniel Wallner (jesus <at> opencores <dot> org) -- Mike Johnson (mikej <at> fpgaarcade <dot> com) -- Wolfgang Scherr (WoS <at> pin4 <dot> at> -- Morten Leikvoll () -- -- All rights reserved -- -- Redistribution and use in source and synthezised forms, with or without -- modification, are permitted provided that the following conditions are met: -- -- Redistributions of source code must retain the above copyright notice, -- this list of conditions and the following disclaimer. -- -- Redistributions in synthesized form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- Neither the name of the author nor the names of other contributors may -- be used to endorse or promote products derived from this software without -- specific prior written permission. -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- -- Please report bugs to the author(s), but before you do so, please -- make sure that this is not a derivative work and that -- you have the latest version of this file. -- -- Limitations : -- See in T65 top file (T65.vhd)... library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.T65_Pack.all; entity T65_ALU is port( Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816 Op : in T_ALU_OP; BusA : in std_logic_vector(7 downto 0); BusB : in std_logic_vector(7 downto 0); P_In : in std_logic_vector(7 downto 0); P_Out : out std_logic_vector(7 downto 0); Q : out std_logic_vector(7 downto 0) ); end T65_ALU; architecture rtl of T65_ALU is -- AddSub variables (temporary signals) signal ADC_Z : std_logic; signal ADC_C : std_logic; signal ADC_V : std_logic; signal ADC_N : std_logic; signal ADC_Q : std_logic_vector(7 downto 0); signal SBC_Z : std_logic; signal SBC_C : std_logic; signal SBC_V : std_logic; signal SBC_N : std_logic; signal SBC_Q : std_logic_vector(7 downto 0); signal SBX_Q : std_logic_vector(7 downto 0); begin process (P_In, BusA, BusB) variable AL : unsigned(6 downto 0); variable AH : unsigned(6 downto 0); variable C : std_logic; begin AL := resize(unsigned(BusA(3 downto 0) & P_In(Flag_C)), 7) + resize(unsigned(BusB(3 downto 0) & "1"), 7); AH := resize(unsigned(BusA(7 downto 4) & AL(5)), 7) + resize(unsigned(BusB(7 downto 4) & "1"), 7); -- pragma translate_off if is_x(std_logic_vector(AL)) then AL := "0000000"; end if; if is_x(std_logic_vector(AH)) then AH := "0000000"; end if; -- pragma translate_on if AL(4 downto 1) = 0 and AH(4 downto 1) = 0 then ADC_Z <= '1'; else ADC_Z <= '0'; end if; if AL(5 downto 1) > 9 and P_In(Flag_D) = '1' then AL(6 downto 1) := AL(6 downto 1) + 6; end if; C := AL(6) or AL(5); AH := resize(unsigned(BusA(7 downto 4) & C), 7) + resize(unsigned(BusB(7 downto 4) & "1"), 7); ADC_N <= AH(4); ADC_V <= (AH(4) xor BusA(7)) and not (BusA(7) xor BusB(7)); -- pragma translate_off if is_x(std_logic_vector(AH)) then AH := "0000000"; end if; -- pragma translate_on if AH(5 downto 1) > 9 and P_In(Flag_D) = '1' then AH(6 downto 1) := AH(6 downto 1) + 6; end if; ADC_C <= AH(6) or AH(5); ADC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1)); end process; process (Op, P_In, BusA, BusB) variable AL : unsigned(6 downto 0); variable AH : unsigned(5 downto 0); variable C : std_logic; variable CT : std_logic; begin CT:='0'; if( Op=ALU_OP_AND or --"0001" These OpCodes used to have LSB set Op=ALU_OP_ADC or --"0011" Op=ALU_OP_EQ2 or --"0101" Op=ALU_OP_SBC or --"0111" Op=ALU_OP_ROL or --"1001" Op=ALU_OP_ROR or --"1011" -- Op=ALU_OP_EQ3 or --"1101" Op=ALU_OP_INC --"1111" ) then CT:='1'; end if; C := P_In(Flag_C) or not CT;--was: or not Op(0); AL := resize(unsigned(BusA(3 downto 0) & C), 7) - resize(unsigned(BusB(3 downto 0) & "1"), 6); AH := resize(unsigned(BusA(7 downto 4) & "0"), 6) - resize(unsigned(BusB(7 downto 4) & AL(5)), 6); -- pragma translate_off if is_x(std_logic_vector(AL)) then AL := "0000000"; end if; if is_x(std_logic_vector(AH)) then AH := "000000"; end if; -- pragma translate_on if AL(4 downto 1) = 0 and AH(4 downto 1) = 0 then SBC_Z <= '1'; else SBC_Z <= '0'; end if; SBC_C <= not AH(5); SBC_V <= (AH(4) xor BusA(7)) and (BusA(7) xor BusB(7)); SBC_N <= AH(4); SBX_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1)); if P_In(Flag_D) = '1' then if AL(5) = '1' then AL(5 downto 1) := AL(5 downto 1) - 6; end if; AH := resize(unsigned(BusA(7 downto 4) & "0"), 6) - resize(unsigned(BusB(7 downto 4) & AL(6)), 6); if AH(5) = '1' then AH(5 downto 1) := AH(5 downto 1) - 6; end if; end if; SBC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1)); end process; process (Op, P_In, BusA, BusB, ADC_Z, ADC_C, ADC_V, ADC_N, ADC_Q, SBC_Z, SBC_C, SBC_V, SBC_N, SBC_Q) variable Q_t : std_logic_vector(7 downto 0); variable Q2_t : std_logic_vector(7 downto 0); begin -- ORA, AND, EOR, ADC, NOP, LD, CMP, SBC -- ASL, ROL, LSR, ROR, BIT, LD, DEC, INC P_Out <= P_In; Q_t := BusA; Q2_t := BusA; case Op is when ALU_OP_OR=> Q_t := BusA or BusB; when ALU_OP_AND=> Q_t := BusA and BusB; when ALU_OP_EOR=> Q_t := BusA xor BusB; when ALU_OP_ADC=> P_Out(Flag_V) <= ADC_V; P_Out(Flag_C) <= ADC_C; Q_t := ADC_Q; when ALU_OP_CMP=> P_Out(Flag_C) <= SBC_C; when ALU_OP_SAX=> P_Out(Flag_C) <= SBC_C; Q_t := SBX_Q; -- undoc: subtract (A & X) - (immediate) when ALU_OP_SBC=> P_Out(Flag_V) <= SBC_V; P_Out(Flag_C) <= SBC_C; Q_t := SBC_Q; -- undoc: subtract (A & X) - (immediate), then decimal correction when ALU_OP_ASL=> Q_t := BusA(6 downto 0) & "0"; P_Out(Flag_C) <= BusA(7); when ALU_OP_ROL=> Q_t := BusA(6 downto 0) & P_In(Flag_C); P_Out(Flag_C) <= BusA(7); when ALU_OP_LSR=> Q_t := "0" & BusA(7 downto 1); P_Out(Flag_C) <= BusA(0); when ALU_OP_ROR=> Q_t := P_In(Flag_C) & BusA(7 downto 1); P_Out(Flag_C) <= BusA(0); when ALU_OP_ARR=> Q_t := P_In(Flag_C) & (BusA(7 downto 1) and BusB(7 downto 1)); P_Out(Flag_V) <= Q_t(5) xor Q_t(6); Q2_t := Q_t; if P_In(Flag_D)='1' then if (BusA(3 downto 0) and BusB(3 downto 0)) > "0100" then Q2_t(3 downto 0) := std_logic_vector(unsigned(Q_t(3 downto 0)) + x"6"); end if; if (BusA(7 downto 4) and BusB(7 downto 4)) > "0100" then Q2_t(7 downto 4) := std_logic_vector(unsigned(Q_t(7 downto 4)) + x"6"); P_Out(Flag_C) <= '1'; else P_Out(Flag_C) <= '0'; end if; else P_Out(Flag_C) <= Q_t(6); end if; when ALU_OP_BIT=> P_Out(Flag_V) <= BusB(6); when ALU_OP_DEC=> Q_t := std_logic_vector(unsigned(BusA) - 1); when ALU_OP_INC=> Q_t := std_logic_vector(unsigned(BusA) + 1); when others => null; --EQ1,EQ2,EQ3 passes BusA to Q_t and P_in to P_out end case; case Op is when ALU_OP_ADC=> P_Out(Flag_N) <= ADC_N; P_Out(Flag_Z) <= ADC_Z; when ALU_OP_CMP|ALU_OP_SBC|ALU_OP_SAX=> P_Out(Flag_N) <= SBC_N; P_Out(Flag_Z) <= SBC_Z; when ALU_OP_EQ1=>--dont touch P when ALU_OP_BIT=> P_Out(Flag_N) <= BusB(7); if (BusA and BusB) = "00000000" then P_Out(Flag_Z) <= '1'; else P_Out(Flag_Z) <= '0'; end if; when ALU_OP_ANC=> P_Out(Flag_N) <= Q_t(7); P_Out(Flag_C) <= Q_t(7); if Q_t = "00000000" then P_Out(Flag_Z) <= '1'; else P_Out(Flag_Z) <= '0'; end if; when others => P_Out(Flag_N) <= Q_t(7); if Q_t = "00000000" then P_Out(Flag_Z) <= '1'; else P_Out(Flag_Z) <= '0'; end if; end case; if Op=ALU_OP_ARR then -- handled above in ARR code Q <= Q2_t; else Q <= Q_t; end if; end process; end;
apache-2.0
cc24e84a4e74552a0892bdea07667177
0.552435
3.029503
false
false
false
false
hoglet67/AtomFpga
src/common/ROM/InternalROM.vhd
1
2,892
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; library UNISIM; use UNISIM.Vcomponents.all; entity InternalROM is port ( CLK : in std_logic; ADDR : in std_logic_vector(16 downto 0); DATA : out std_logic_vector(7 downto 0) ); end; architecture BEHAVIORAL of InternalROM is component e000 is port ( CLK : in std_logic; ADDR : in std_logic_vector(11 downto 0); DATA : out std_logic_vector(7 downto 0)); end component; component atombasic port ( CLK : in std_logic; ADDR : in std_logic_vector(11 downto 0); DATA : out std_logic_vector(7 downto 0)); end component; component atomfloat port ( CLK : in std_logic; ADDR : in std_logic_vector(11 downto 0); DATA : out std_logic_vector(7 downto 0)); end component; component atomkernal port ( CLK : in std_logic; ADDR : in std_logic_vector(11 downto 0); DATA : out std_logic_vector(7 downto 0)); end component; signal basic_rom_enable : std_logic; signal kernal_rom_enable : std_logic; signal float_rom_enable : std_logic; signal sddos_rom_enable : std_logic; signal kernal_data : std_logic_vector(7 downto 0); signal basic_data : std_logic_vector(7 downto 0); signal float_data : std_logic_vector(7 downto 0); signal sddos_data : std_logic_vector(7 downto 0); begin romc000 : atombasic port map( CLK => CLK, ADDR => ADDR(11 downto 0), DATA => basic_data); romd000 : atomfloat port map( CLK => CLK, ADDR => ADDR(11 downto 0), DATA => float_data); rome000 : e000 port map( CLK => CLK, ADDR => ADDR(11 downto 0), DATA => sddos_data); romf000 : atomkernal port map( CLK => CLK, ADDR => ADDR(11 downto 0), DATA => kernal_data); process(ADDR) begin -- All regions normally de-selected sddos_rom_enable <= '0'; basic_rom_enable <= '0'; kernal_rom_enable <= '0'; float_rom_enable <= '0'; case ADDR(15 downto 12) is when x"C" => basic_rom_enable <= '1'; when x"D" => float_rom_enable <= '1'; when x"E" => sddos_rom_enable <= '1'; when x"F" => kernal_rom_enable <= '1'; when others => null; end case; end process; DATA <= basic_data when basic_rom_enable = '1' else float_data when float_rom_enable = '1' else sddos_data when sddos_rom_enable = '1' else kernal_data when kernal_rom_enable = '1' else x"f1"; -- un-decoded locations end BEHAVIORAL;
apache-2.0
8f3ac91907800b46de60f661bb376fa5
0.544952
3.509709
false
false
false
false
tghaefli/ADD
EDK/IVK_Repos/IVK_IPLib/pcores/fmc_imageov_camera_in_v1_02_a/hdl/vhdl/fmc_imageov_camera_in.vhd
1
16,813
------------------------------------------------------------------ -- _____ -- / \ -- /____ \____ -- / \===\ \==/ -- /___\===\___\/ AVNET -- \======/ -- \====/ ----------------------------------------------------------------- -- -- This design is the property of Avnet. Publication of this -- design is not authorized without written consent from Avnet. -- -- Please direct any questions to: [email protected] -- -- Disclaimer: -- Avnet, Inc. makes no warranty for the use of this code or design. -- This code is provided "As Is". Avnet, Inc assumes no responsibility for -- any errors, which may appear in this code, nor does it make a commitment -- to update the information contained herein. Avnet, Inc specifically -- disclaims any implied warranties of fitness for a particular purpose. -- Copyright(c) 2010 Avnet, Inc. -- All rights reserved. -- ------------------------------------------------------------------ -- -- Create Date: Jul 03, 2009 -- Design Name: FMC-IMAGEOV -- Module Name: fmc_imageov_dvi_out.vhd -- Project Name: FMC-IMAGEOV -- Target Devices: Spartan-6 -- Avnet Boards: FMC-IMAGEOV -- -- Tool versions: ISE 11.4 -- -- Description: FMC-IMAGEOV Camera input interface. -- Based on VSK camera.vhd and modified as follows: -- - rename camera to fmc_imageov_camera_in -- - add support for more devices via C_FAMILY generic: -- - spartan3adsp -- - spartan6 -- -- The OV9715 image sensor is configured to generate CCIR656 codes. -- - VREF is used as VSYNC -- - HREF is used as HSYNC -- - The following signals are generated from the CCIR656 codes: -- - ACTIVE_VIDEO (DE) -- - HBLANK -- - VBLANK -- -- Observations with ChipScope reveils that the first active line -- has unusual CCIR656 codes, which results in line 1 being dropped. -- -- Case Code Y[9:0] => 1 F V H P3 P2 P1 P0 -- -- -- ============================================================= -- ACTIVE LINE 1 FS 0x2AC 1 0 1 0 1 0 1 1 0 0 -- LE 0x274 1 0 0 1 1 1 0 1 0 0 -- ------------------------------------------------------------- -- ACTIVE LINES 2-N LS 0x200 1 0 0 0 0 0 0 0 0 0 -- LE 0x274 1 0 0 1 1 1 0 1 0 0 -- ------------------------------------------------------------- -- INACTIVE LINES FS 0x2AC 1 0 1 0 1 0 1 1 0 0 -- FE 0x2D8 1 0 1 1 0 1 1 0 0 0 -- ============================================================= -- -- Dependencies: -- -- Revision: Jul 03, 2009: 1.00 Initial version -- Dec 01, 2009: 1.01 Increase CAMERA_VIDEO_OUT data width to 10 bits -- Feb 01, 2010: 1.02 Add selectable video interface -- ------------------------------------------------------------------ -- DISCLAIMER OF LIABILITY -- -- This text/file contains proprietary, confidential -- information of Xilinx, Inc., is distributed under license -- from Xilinx, Inc., and may be used, copied and/or -- disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you -- a license to use this text/file solely for design, simulation, -- implementation and creation of design files limited -- to Xilinx devices or technologies. Use with non-Xilinx -- devices or technologies is expressly prohibited and -- immediately terminates your license unless covered by -- a separate agreement. -- -- Xilinx is providing this design, code, or information -- "as-is" solely for use in developing programs and -- solutions for Xilinx devices. By providing this design, -- code, or information as one possible implementation of -- this feature, application or standard, Xilinx is making no -- representation that this implementation is free from any -- claims of infringement. You are responsible for -- obtaining any rights you may require for your implementation. -- Xilinx expressly disclaims any warranty whatsoever with -- respect to the adequacy of the implementation, including -- but not limited to any warranties or representations that this -- implementation is free from claims of infringement, implied -- warranties of merchantability or fitness for a particular -- purpose. -- -- Xilinx products are not intended for use in life support -- appliances, devices, or systems. Use in such applications is -- expressly prohibited. -- -- -- Copyright (c) 2007, 2008 Xilinx, Inc. All rights reserved. -- -- This copyright and support notice must be retained as part -- of this text at all times. -- ------------------------------------------------------------------------------ -- Filename : camera.vhd -- $Revision:: 2433 $: Revision of last commit -- $Date:: 2008-05-27#$: Date of last commit -- Description : Camera VHDL Hardware Interface ------------------------------------------------------------------------------ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity fmc_imageov_camera_in is Generic ( C_VIDEO_INTERFACE : integer := 2; C_DATA_WIDTH : integer := 8; C_FAMILY : string := "spartan6" ); Port ( clk : in std_logic; ce : in std_logic; -- IO Pins io_frame_valid_i : in std_logic; io_line_valid_i : in std_logic; io_data_i : in std_logic_vector(9 downto 0); -- Camera Port camera_frame_valid_o : out std_logic; camera_line_valid_o : out std_logic; camera_data_o : out std_logic_vector((C_DATA_WIDTH-1) downto 0); -- DVI Port dvi_vsync_o : out std_logic; dvi_hsync_o : out std_logic; dvi_de_o : out std_logic; dvi_red_o : out std_logic_vector(7 downto 0); dvi_green_o : out std_logic_vector(7 downto 0); dvi_blue_o : out std_logic_vector(7 downto 0); -- XSVI Port xsvi_vsync_o : out std_logic; xsvi_hsync_o : out std_logic; xsvi_vblank_o : out std_logic; xsvi_hblank_o : out std_logic; xsvi_active_video_o : out std_logic; xsvi_video_data_o : out std_logic_vector((C_DATA_WIDTH-1) downto 0); -- Debug Ports debug_o : out std_logic_vector(14 downto 0) ); end fmc_imageov_camera_in; architecture rtl of fmc_imageov_camera_in is signal frame_valid_r : std_logic; signal line_valid_r : std_logic; signal data_r : std_logic_vector(9 downto 0); -- -- Input Delay -- signal data_d1 : std_logic_vector(9 downto 0); signal data_d2 : std_logic_vector(9 downto 0); signal data_d3 : std_logic_vector(9 downto 0); signal data_d4 : std_logic_vector(9 downto 0); signal frame_valid_d1 : std_logic; signal frame_valid_d2 : std_logic; signal frame_valid_d3 : std_logic; signal frame_valid_d4 : std_logic; signal line_valid_d1 : std_logic; signal line_valid_d2 : std_logic; signal line_valid_d3 : std_logic; signal line_valid_d4 : std_logic; -- -- CCIR656 Decode Logic -- signal sav : std_logic; signal eav : std_logic; signal siv : std_logic; signal eiv : std_logic; signal sav_d1 : std_logic; signal sav_d2 : std_logic; signal sav_d3 : std_logic; signal sav_d4 : std_logic; signal siv_d1 : std_logic; signal siv_d2 : std_logic; signal siv_d3 : std_logic; signal siv_d4 : std_logic; signal vblank : std_logic; signal hblank : std_logic; signal active_video : std_logic; begin In_Reg : process (clk) begin if Rising_Edge(clk) then frame_valid_r <= io_frame_valid_i; line_valid_r <= io_line_valid_i; data_r <= io_data_i; end if; end process; -- -- Input Delay -- input_delay_l : process (clk) begin if Rising_Edge(clk) then -- Delay DATA by 4 cycles to have a 4 cycle view of data data_d1 <= data_r; data_d2 <= data_d1; data_d3 <= data_d2; data_d4 <= data_d3; -- frame_valid_d1 <= frame_valid_r; frame_valid_d2 <= frame_valid_d1; frame_valid_d3 <= frame_valid_d2; frame_valid_d4 <= frame_valid_d3; -- line_valid_d1 <= line_valid_r; line_valid_d2 <= line_valid_d1; line_valid_d3 <= line_valid_d2; line_valid_d4 <= line_valid_d3; end if; end process; -- -- CCIR656 Decode Logic -- ccir656_decode_l : process ( data_r, data_d1, data_d2, data_d3, data_d4 ) begin -- Start of Active Video (H=0, V=0) sav <= '0'; if ( (data_d3 = X"3FF") and (data_d2 = X"000") and (data_d1 = X"000") and (data_r = X"200") ) then sav <= '1'; end if; -- End of Active Video (H=1, V=0) eav <= '0'; if ( (data_d3 = X"3FF") and (data_d2 = X"000") and (data_d1 = X"000") and (data_r = X"274") ) then eav <= '1'; end if; -- Start of Inactive Video (H=0, V=1) siv <= '0'; if ( (data_d3 = X"3FF") and (data_d2 = X"000") and (data_d1 = X"000") and (data_r = X"2AC") ) then siv <= '1'; end if; -- End of Inactive Video (H=1, V=1) eiv <= '0'; if ( (data_d3 = X"3FF") and (data_d2 = X"000") and (data_d2 = X"000") and (data_r = X"2D8") ) then eiv <= '1'; end if; end process; ccir656_syncgen_l : process (clk) begin if Rising_Edge(clk) then -- Delay DATA by 4 cycles to have a 4 cycle view of data data_d1 <= data_r; data_d2 <= data_d1; data_d3 <= data_d2; data_d4 <= data_d3; -- Delay SAV by 4 cycles sav_d1 <= sav; sav_d2 <= sav_d1; sav_d3 <= sav_d2; sav_d4 <= sav_d3; -- Delay SIV by 4 cycles siv_d1 <= siv; siv_d2 <= siv_d1; siv_d3 <= siv_d2; siv_d4 <= siv_d3; -- Create Active Video strobe based on SAV/EAV events if ( sav_d4 = '1' ) then active_video<= '1'; end if; if ( eav = '1' ) then active_video<= '0'; end if; -- Create VBLANK strobes based on SIV/SAV events if ( siv = '1' ) then vblank <= '1'; end if; if ( sav = '1' ) then vblank <= '0'; end if; -- Create HBLANK strobes based on SAV/EAV/SIV/EIV events if ( sav_d4 = '1' or siv_d4 = '1' ) then hblank <= '0'; end if; if ( eav = '1' or eiv = '1' ) then hblank <= '1'; end if; end if; end process; -- -- Camera Port -- CAMERA_OPORT_GEN : if (C_VIDEO_INTERFACE = 0) generate CAMERA_8BIT_GEN : if (C_DATA_WIDTH = 8) generate camera_8bit_oregs_l : process (clk) begin if rising_edge( clk ) then camera_frame_valid_o <= frame_valid_r; camera_line_valid_o <= line_valid_r; camera_data_o <= data_r(9 downto 2); end if; end process; end generate CAMERA_8BIT_GEN; CAMERA_10BIT_GEN : if (C_DATA_WIDTH = 10) generate camera_10bit_oregs_l : process (clk) begin if rising_edge( clk ) then camera_frame_valid_o <= frame_valid_r; camera_line_valid_o <= line_valid_r; camera_data_o <= data_r(9 downto 0); end if; end process; end generate CAMERA_10BIT_GEN; -- dvi_vsync_o <= '0'; dvi_hsync_o <= '0'; dvi_de_o <= '0'; dvi_red_o <= (others => '0'); dvi_green_o <= (others => '0'); dvi_blue_o <= (others => '0'); -- xsvi_vsync_o <= '0'; xsvi_hsync_o <= '0'; xsvi_vblank_o <= '0'; xsvi_hblank_o <= '0'; xsvi_active_video_o <= '0'; xsvi_video_data_o <= (others => '0'); end generate CAMERA_OPORT_GEN; -- -- DVI Port -- DVI_OPORT_GEN : if (C_VIDEO_INTERFACE = 1) generate dvi_oregs_l : process (clk) begin if rising_edge( clk ) then dvi_vsync_o <= frame_valid_d4; dvi_hsync_o <= line_valid_d4; dvi_de_o <= active_video; dvi_red_o <= data_d4(9 downto 2); dvi_green_o <= data_d4(9 downto 2); dvi_blue_o <= data_d4(9 downto 2); end if; end process; -- camera_frame_valid_o <= '0'; camera_line_valid_o <= '0'; camera_data_o <= (others => '0'); -- xsvi_vsync_o <= '0'; xsvi_hsync_o <= '0'; xsvi_vblank_o <= '0'; xsvi_hblank_o <= '0'; xsvi_active_video_o <= '0'; xsvi_video_data_o <= (others => '0'); end generate DVI_OPORT_GEN; -- -- XSVI Port -- XSVI_OPORT_GEN : if (C_VIDEO_INTERFACE = 2) generate XSVI_8BIT_GEN : if (C_DATA_WIDTH = 8) generate xsvi_8bit_oregs_l : process (clk) begin if rising_edge( clk ) then xsvi_vsync_o <= frame_valid_d4; xsvi_hsync_o <= line_valid_d4; xsvi_vblank_o <= vblank; xsvi_hblank_o <= hblank; xsvi_active_video_o <= active_video; xsvi_video_data_o <= data_d4(9 downto 2); end if; end process; end generate XSVI_8BIT_GEN; XSVI_10BIT_GEN : if (C_DATA_WIDTH = 10) generate xsvi_10bit_oregs_l : process (clk) begin if rising_edge( clk ) then xsvi_vsync_o <= frame_valid_d4; xsvi_hsync_o <= line_valid_d4; xsvi_vblank_o <= vblank; xsvi_hblank_o <= hblank; xsvi_active_video_o <= active_video; xsvi_video_data_o <= data_d4(9 downto 0); end if; end process; end generate XSVI_10BIT_GEN; -- camera_frame_valid_o <= '0'; camera_line_valid_o <= '0'; camera_data_o <= (others => '0'); -- dvi_vsync_o <= '0'; dvi_hsync_o <= '0'; dvi_de_o <= '0'; dvi_red_o <= (others => '0'); dvi_green_o <= (others => '0'); dvi_blue_o <= (others => '0'); end generate XSVI_OPORT_GEN; -- -- Debug Port -- Can be used to connect to ChipScope for debugging. -- Having a port makes these signals accessible for debug via EDK. -- debug_l : process (clk) begin if rising_edge( clk ) then debug_o <= vblank & hblank & active_video & frame_valid_d4 & line_valid_d4 & data_d4; end if; end process; end rtl;
gpl-3.0
2468397c1e96275a967f988602ed5bad
0.46922
3.690299
false
false
false
false
bertuccio/ARQ
Practica5/alu.vhd
3
1,264
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity ALU is Port ( A : in STD_LOGIC_VECTOR (31 downto 0); B : in STD_LOGIC_VECTOR (31 downto 0); resultado : out STD_LOGIC_VECTOR (31 downto 0); control : in STD_LOGIC_VECTOR (3 downto 0); igual : out STD_LOGIC); end ALU; architecture Behavior of ALU is begin process (A,B,control) variable rAux: std_logic_vector(31 downto 0); variable igualAux : std_logic; begin rAux:= (A) - (B); if(rAux=x"00000000") then igualAux:='1'; else igualAux:='0'; end if; if (control="0000") then rAux:= (A) AND (B); elsif(control="0001") then rAux:= (A) OR (B); elsif(control="0010") then rAux:= (A) XOR (B); elsif(control="0011") then rAux:= (A) + (B); elsif(control="1000") then rAux:= (A) - (B); elsif(control="1001") then raux:=B(15 downto 0)&x"0000"; elsif(control="1010") then rAux:= (A) - (B); if(rAux(31)='1') then rAux:=x"00000001"; else rAux:=x"00000000"; end if; else rAux:=(others=>'0'); igualAux:='0'; end if; resultado<=rAux; igual<=igualAux; end process; end Behavior;
mit
d68efe40914ec97b02dae23e07970978
0.573576
2.765864
false
false
false
false
GSimas/EEL5105
Rep CAEE/11.2.Projeto/_PROJETO/reg_16.vhd
1
4,022
-- ALUNOS: -- Bruno Luiz da Silva -- Gustavo Fernades -- -- -- TÍTULO: -- Registrador de 16 (+ 1) bits -- -- -- RESUMO: -- Registrador de 16 bits com recurso de deslocamento e normalização. É utilizado num multiplicador. -- -- -- ENTRADAS/SAÍDAS (I/O): -- (I) soma: dado da saída do armazenador (soma ou somente a cópia da parte alta desse registrador) -- (I) chave: utilizado para carregar a parte baixa do registrador (7 downto 0), sendo conectado nas -- chaves (SW). Só será lida quando start tiver valor lógico alto. -- (I) start, load: o primeiro ativa a leitura de "chave" e então armazena dados na parte baixa do reg_16. -- Já o load permite o armazenamento de "soma" na parte alta do registrador. -- (I) shift, normalize: recursos extras do registrador que serão utilizados para realizar a multiplicação -- de números float. "shift", quando alto, deslocará os dados para a esquerda -- e "normalize" irá deslocar os dados para a direita e acresentará 1 ao signal -- "exp_aux". -- (I) clock,reset: clock e reset, sendo que o reset zera todas saídas -- (O) q: saída dos dados armazenados -- (O) exp: número de vezes em que os dados foram deslocados para direita até que o LSB fosse 1. -- -- -- DESCRIÇÃO: -- Serão, primeiramente, dados os valores do multiplicador e estes serão guardados na parte baixa do -- registrador (7 downto 0). Para tal será necessário dar um valor lógico alto para "start". -- Para carregar o valor que vier do somador terá-se que colocar um valor lógico alto em "load" e assim -- o valor será guardado na parte alta do registrador (15 downto 8). -- -- Como esse bloco será usado para um multiplicador então será necessário que o valor seja deslocado -- após a operação do componente "somador". Para realizar isto será necessário dar um valor lógico alto -- para "shift" a cada deslocamento desejado. -- -- A normalização far-se-á necessária neste projeto, logo "normalize" deve receber um valor lógico alto -- para que inicie-se a normalização. Nesse processo o signal "works" tornará-se 1 e enquanto o LSB não for -- 1, "works" permanecerá em 1, desabilitando qualquer outra operação do componente. Quando a operação -- estiver concluída ter-se-á o número normalizado e "exp" armazenará o número de deslocamentos que foram -- necessários. -- -- -- (I): INPUT / (O): OUTPUT library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity reg_16 is port( soma: std_logic_vector(8 downto 0); -- Resultado do somador chave: std_logic_vector (7 downto 0); -- Valor do multiplicador start, load, shift, normalize: in std_logic; -- Recursos para armazenar e manipular valores clk, rst: in std_logic; -- Clock e reset do registrador q: out std_logic_vector(15 downto 0); -- Saída (dados armazenados) exp: out std_logic_vector(3 downto 0) -- Número de deslocamentos realizados pela normalização ); end reg_16; architecture func of reg_16 is signal aux: std_logic_vector(16 downto 0); signal exp_aux: std_logic_vector(3 downto 0); signal works: std_logic; begin REG16: process(clk,rst) begin if (rst = '1') then -- Deleta os dados atuais do registrador aux <= (others => '0'); works <= '0'; elsif (rising_edge(clk)) then if(works = '0') then if(start = '1') then -- Carrega o multiplicador para a parte baixa do -- registrador e preenche com 0s a parte alta. aux <= '0' & x"00" & chave; elsif(load = '1') then -- Carrega a soma para a parte baixa do registrador aux(16 downto 8) <= soma; elsif(shift = '1') then -- Desloca os bits uma unidade para a direita. aux <= '0' & aux(16 downto 1); elsif(normalize = '1') then works <= '1'; exp_aux <= (others => '0'); end if; else if(aux(15) = '0') then exp_aux <= exp_aux + 1; aux <= aux(15 downto 0) & '0'; end if; end if; end if; exp <= exp_aux; q <= aux(15 downto 0); -- Guarda as operações acima efetuadas no registrador. end process; end func;
mit
d3be943a83e2b4398d7c49ace763c597
0.685977
3.051593
false
false
false
false
hoglet67/AtomFpga
src/common/AVR8/Memory/XPM_Generic.vhd
1
3,170
library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; -- For f_log2 definition use WORK.SynthCtrlPack.all; -- For loadin use std.textio.all; use IEEE.std_logic_textio.all; entity XPM is generic ( WIDTH : integer; SIZE : integer; FILENAME : string ); port( cp2 : in std_logic; ce : in std_logic; address : in std_logic_vector(f_log2(SIZE) - 1 downto 0); din : in std_logic_vector(WIDTH - 1 downto 0); dout : out std_logic_vector(WIDTH - 1 downto 0); we : in std_logic ); end; architecture RTL of XPM is -- If the ROM is not a power of 2, the ISE does a poor job of optimization -- e.g. a 10Kx16 rom takes up the space of a 16Kx16 -- -- To avoid this, we break the RAM into two parts function is_power_of_2 return boolean is begin return 2**f_log2(SIZE) = SIZE; end function; function ram1_size return integer is begin if is_power_of_2 then return SIZE; else return 2**(f_log2(SIZE) - 1); end if; end function; function ram2_size return integer is begin return SIZE - ram1_size; end function; type ram1_type is array (0 to ram1_size - 1) of std_logic_vector (WIDTH - 1 downto 0); type ram2_type is array (0 to ram2_size - 1) of std_logic_vector (WIDTH - 1 downto 0); impure function InitRam1FromFile (RamFileName : in string) return ram1_type is FILE ramfile : text is in RamFileName; variable RamFileLine : line; variable ram : ram1_type; begin for i in ram1_type'range loop readline(ramfile, RamFileLine); hread(RamFileLine, ram(i)); end loop; return ram; end function; impure function InitRam2FromFile (RamFileName : in string) return ram2_type is FILE ramfile : text is in RamFileName; variable RamFileLine : line; variable ram : ram2_type; begin for i in ram1_type'range loop readline(ramfile, RamFileLine); end loop; for i in ram2_type'range loop readline(ramfile, RamFileLine); hread(RamFileLine, ram(i)); end loop; return ram; end function; signal RAM1 : ram1_type := InitRam1FromFile(FILENAME); signal RAM2 : ram2_type := InitRam2FromFile(FILENAME); signal dout1 : std_logic_vector(WIDTH - 1 downto 0); signal dout2 : std_logic_vector(WIDTH - 1 downto 0); begin process (cp2) begin if rising_edge(cp2) then if ce = '1' then if is_power_of_2 then dout1 <= RAM1(conv_integer(address)); dout2 <= (others => '0'); else dout1 <= RAM1(conv_integer(address(f_log2(ram1_size) - 1 downto 0))); dout2 <= RAM2(conv_integer(address(f_log2(ram2_size) - 1 downto 0))); end if; end if; end if; end process; dout <= dout1 when is_power_of_2 or address(f_log2(SIZE) - 1) = '0' else dout2; end RTL;
apache-2.0
3d9103c1779f9157d18329044e11d067
0.577918
3.711944
false
false
false
false
GSimas/EEL5105
AULA5/decod7seg.vhd
1
841
library IEEE; use IEEE.Std_Logic_1164.all; entity decod7seg is port (C: in std_logic_vector(3 downto 0); F: out std_logic_vector(6 downto 0) ); end decod7seg; architecture decod of decod7seg is begin F <= "1000000" when C = "0000" else -- 0 "1111001" when C = "0001" else -- 1 "0100100" when C = "0010" else -- 2 "0110000" when C = "0011" else -- 3 "0011001" when C = "0100" else -- 4 "0010010" when C = "0101" else -- 5 "0000010" when C = "0110" else -- 6 "1111000" when C = "0111" else -- 7 "0000000" when C = "1000" else -- 8 "0010000" when C = "1001" else -- 9 "0001000" when C = "1010" else -- A "0000011" when C = "1011" else -- b "1000110" when C = "1100" else -- C "0100001" when C = "1101" else -- d "0000110" when C = "1110" else -- E "0001110"; -- F end decod;
mit
7ce0d540d2a7cf3569b34d1f6d7feafe
0.575505
2.812709
false
false
false
false
hoglet67/AtomFpga
src/common/i82C55/i82c55.vhd
1
3,002
--------------------------------------------------- -- Alan Daly 2009(c) -- AtomIC project -- minimal implementation of an 8255 -- just enough for the machine to function --------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; entity I82C55 is port ( I_ADDR : in std_logic_vector(1 downto 0); -- A1-A0 I_DATA : in std_logic_vector(7 downto 0); -- D7-D0 O_DATA : out std_logic_vector(7 downto 0); CS_H : in std_logic; WR_L : in std_logic; O_PA : out std_logic_vector(7 downto 0); I_PB : in std_logic_vector(7 downto 0); I_PC : in std_logic_vector(3 downto 0); O_PC : out std_logic_vector(3 downto 0); RESET : in std_logic; ENA : in std_logic; -- (CPU) clk enable CLK : in std_logic); end; architecture RTL of I82C55 is -- registers signal r_porta : std_logic_vector(7 downto 0); signal r_portb : std_logic_vector(7 downto 0); signal l_portc : std_logic_vector(3 downto 0); signal h_portc : std_logic_vector(3 downto 0); signal ctrl_reg : std_logic_vector(7 downto 0); begin p_write_reg_reset : process(RESET, CLK) begin if (RESET = '0') then r_porta <= x"00"; r_portb <= x"00"; l_portc <= x"0"; h_portc <= x"0"; ctrl_reg <= x"00"; elsif rising_edge(CLK) then if ENA = '1' then O_PA <= r_porta; r_portb <= I_PB; h_portc <= I_PC; O_PC <= l_portc; if (CS_H = '1') then if (WR_L = '0') then case I_ADDR is when "00" => r_porta <= I_DATA; --when "01" => r_portb <= I_DATA; when "10" => l_portc <= I_DATA (3 downto 0); when "11" => if (I_DATA(7) = '0') then -- set/clr l_portc(2) <= I_DATA(0); else ctrl_reg <= I_DATA; end if; when others => null; end case; else -- read ports case I_ADDR is when "00" => O_DATA <= r_porta; when "01" => O_DATA <= r_portb; when "10" => O_DATA <= h_portc & l_portc; when "11" => O_DATA <= ctrl_reg; when others => null; end case; end if; end if; end if; end if; end process; end architecture RTL;
apache-2.0
c6986a4d5ce5332ff302db756f3e9296
0.392738
3.929319
false
false
false
false
gufernandez/PorrinhaGame
user.vhd
1
1,340
LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY porrinha_user IS -- Choice: define se é a vez de escolha do usuário -- Guess: define se é a vez de chute do usuário -- Fim: define se a rodada acabou -- FimFim: define se o jogo acabou -- winner: define o vencedor da rodada -- clk: sinal de clock -- guess_opt: dá o valor do chute do oponente (0 a 9) -- P1 e P2: pontos dos jogadores (0 a 3) -- pal: palitos colocados pelo jogadores (0 a 3) -- guess_user: chute do usuário da placa (0 a 9) PORT (Choice, Guess, Fim, FimFim, winner, clk: IN STD_LOGIC; guess_opt: IN STD_LOGIC_VECTOR(2 downto 0); P1, P2: IN STD_LOGIC_VECTOR(1 downto 0); pal: OUT STD_LOGIC_VECTOR(1 downto 0); guess_user: OUT STD_LOGIC_VECTOR(2 downto 0)); END porrinha_user; architecture behavior of porrinha_user is begin process(Choice, Guess, Fim, clk, P1, P2, guess_opt) begin --if (clk'event and clk = '1') then -- Precisa? if ((Choice = '0') and (Guess = '0') and (Fim = '0')) then --monitor.wait(); elsif (Choice = '1') then --monitor.choice(pal); elsif (Guess = '1') then --monitor.guess(guess_opt, guess_user); elsif (Fim = '1') then --monitor.finish(winner, P1, P2); elsif (FimFim = '1') then --monitor.gameover(winner, P1, P2); end if; end process; --end if; end behavior;
mit
3f7b81c6e1189323d3a07cc4bf611f6e
0.645427
2.673347
false
false
false
false
GSimas/EEL5105
PROJETO-EEL5105/Projeto/ButtonSync.vhd
1
3,383
-- Button Press Synchronizer para keys que são ativas baixas (ou seja, quando pressionadas vao para nivel baixo) library ieee; use ieee.std_logic_1164.all; entity ButtonSync is port ( -- Input ports key0 : in std_logic; key1 : in std_logic; key2 : in std_logic; key3 : in std_logic; clk : in std_logic; -- Output ports btn0 : out std_logic; btn1 : out std_logic; btn2 : out std_logic; btn3 : out std_logic ); end ButtonSync; -- Definicao de Arquitetura architecture ButtonSyncImpl of ButtonSync is type STATES is (EsperaApertar, SaidaAtiva, EsperaSoltar); signal btn0state, btn1state, btn2state, btn3state : STATES := EsperaApertar; signal btn0next, btn1next, btn2next, btn3next : STATES := EsperaApertar; begin process (clk) begin if clk'event and clk = '1' then -- Resposta na transicao positiva do clock btn0state <= btn0next; btn1state <= btn1next; btn2state <= btn2next; btn3state <= btn3next; end if; end process; process (key0,btn0state) -- Processo para botao 0 begin case btn0state is when EsperaApertar => -- esperar apertar o botao if key0 = '0' then btn0next <= SaidaAtiva; else btn0next <= EsperaApertar; end if; btn0 <= '1'; when SaidaAtiva => -- saida ativa por 1 ciclo de clock if key0 = '0' then btn0next <= EsperaSoltar; else btn0next <= EsperaApertar; end if; btn0 <= '0'; when EsperaSoltar => -- enquanto esta apertando o botao if key0 = '0' then btn0next <= EsperaSoltar; else btn0next <= EsperaApertar; end if; btn0 <= '1'; end case; end process; process (key1,btn1state) -- Processo para botao 1 begin case btn1state is when EsperaApertar => -- espera apertar o botao if key1 = '0' then btn1next <= SaidaAtiva; else btn1next <= EsperaApertar; end if; btn1 <= '1'; when SaidaAtiva => -- saida ativa por 1 ciclo de clock if key1 = '0' then btn1next <= EsperaSoltar; else btn1next <= EsperaApertar; end if; btn1 <= '0'; when EsperaSoltar => -- enquanto esta apertando o botao if key1 = '0' then btn1next <= EsperaSoltar; else btn1next <= EsperaApertar; end if; btn1 <= '1'; end case; end process; process (key2,btn2state) -- Processo para botao 2 begin case btn2state is when EsperaApertar => -- espera apertar o botao if key2 = '0' then btn2next <= SaidaAtiva; else btn2next <= EsperaApertar; end if; btn2 <= '1'; when SaidaAtiva => -- saida ativa para 1 ciclo de clock if key2 = '0' then btn2next <= EsperaSoltar; else btn2next <= EsperaApertar; end if; btn2 <= '0'; when EsperaSoltar => -- enquanto esta apertando o botao if key2 = '0' then btn2next <= EsperaSoltar; else btn2next <= EsperaApertar; end if; btn2 <= '1'; end case; end process; process (key3,btn3state) -- Processo para botao 3 begin case btn3state is when EsperaApertar => -- espera apertar o botao if key3 = '0' then btn3next <= SaidaAtiva; else btn3next <= EsperaApertar; end if; btn3 <= '1'; when SaidaAtiva => -- saida ativa para 1 ciclo de clock if key3 = '0' then btn3next <= EsperaSoltar; else btn3next <= EsperaApertar; end if; btn3 <= '0'; when EsperaSoltar => -- enquanto esta apertando o botao if key3 = '0' then btn3next <= EsperaSoltar; else btn3next <= EsperaApertar; end if; btn3 <= '1'; end case; end process; end ButtonSyncImpl;
mit
d3b56808d4b9647b6b65591c40dccc5e
0.672088
3.175587
false
false
false
false
tghaefli/ADD
ISE/FMC/fmc_ch.vhd
1
5,669
------------------------------------------------------------------------------- -- Entity: fmc_ch -- Author: Sandro Arnold ------------------------------------------------------------------------------- -- Description: Testatbung Floppy Music Controller -- FMC_CH Channel of Floppy Music Controller ------------------------------------------------------------------------------- -- Total # of FFs: ... tbd ... ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.mcu_pkg.all; entity fmc_ch is generic(N : natural := 0 -- channel number ); port( rst : in std_logic; clk : in std_logic; -- FMC_CH FMC_TOP signals tick_dur : in std_logic; --period = 1ms tick_nco : in std_logic; --period = 1us enb : in std_logic; fmc_ch_out_enb : out std_logic; fmc_chn_out_step : out std_logic; fmc_chn_out_dir : out std_logic ); end fmc_ch; architecture rtl of fmc_ch is -- Address signal addr : std_logic_vector(FMC_ROM_AW-1 downto 0); signal rom_data : std_logic_vector(FMC_ROM_DW-1 downto 0); -- signal duration_cnt, tone_duration: unsigned(FMC_DUR_WW-1 downto 0); signal tone_number : std_logic_vector(FMC_TON_WW-1 downto 0); -- LUT: tone number ==> NCO seed type t_nco_lut is array (2**FMC_TON_WW-1 downto 0) of natural; constant nco_lut : t_nco_lut := ( 0,0,0,0,0,0,0,0,0,0,0,0,0,0,7382,6968,6577,6207,5859,5530,5220,4927,4650,4389,4143,3910,3691, 3484,3288,3104,2930,2765,2610,2463,2325,2195,2071,1955,1845,1742,1644,1552,1465,1383,1305,1232, 1163,1097,1036,978,923,871,822,776,732,691,652,616,581,549,518,489,461,0); -- Tone oscillator signals signal seed : unsigned(12 downto 0); -- 13 bit seed signal osc_cnt : unsigned(23 downto 0); -- 24 bit NCO -- Step counter signals for changing direction signal stp_cnt : integer range 0 to 80 := 0; -- signal stp_cnt : unsigned(6 downto 0); -- 7 bit step counter signal dir : std_logic; signal stp_log : std_logic; -- Wait during tone ist playing signals signal wait_cnt : unsigned(FMC_DUR_WW-1 downto 0); signal tone_duration : unsigned(FMC_DUR_WW-1 downto 0); signal next_tone_enb :std_logic; begin -- output assignment fmc_chn_out_step <= osc_cnt(23); fmc_chn_out_dir <= dir; --fmc_ch_out_enb <= enb; fmc_ch_out_enb <= '1' when to_integer(unsigned(tone_number)) = 0 else '0'; ----------------------------------------------------------------------------- -- Direction changing ----------------------------------------------------------------------------- P_dir_change: process(clk, rst) begin if rst = '1' then stp_cnt <= 0; dir <= '0'; elsif rising_edge(clk) then stp_log <= osc_cnt(23); --rising edge if (stp_log = '0' AND osc_cnt(23) = '1') then --rising edge stp_cnt <= stp_cnt + 1; end if; --if (stp_cnt = 79) then if (stp_cnt = 2) then dir <= not dir; stp_cnt <= 0; end if; end if; end process; ----------------------------------------------------------------------------- -- wait during tone is playing ----------------------------------------------------------------------------- P_wait: process(clk, rst) begin if rst = '1' then wait_cnt <= (others => '0'); addr <= (others => '0'); next_tone_enb <= '0'; elsif rising_edge(clk) then --default assignemt next_tone_enb <= '0'; --wait for next tone if tick_dur = '1' then if (wait_cnt = tone_duration-1) then wait_cnt <= (others => '0'); -- decode next tone next_tone_enb <='1'; else wait_cnt <= wait_cnt + 1; --next_tone_enb <='0'; end if; end if; if tone_duration = FMC_LAST_TONE then addr <= (others => '0'); elsif next_tone_enb = '1' then addr <= std_logic_vector(unsigned(addr)+1); end if; end if; end process; ----------------------------------------------------------------------------- -- count address for tone playing next ----------------------------------------------------------------------------- -- P_next_tone: process(rst, clk) -- begin -- if rst = '1' then -- addr <= (others => '0'); -- elsif rising_edge(clk) then -- if next_tone_enb = '1' then -- if tone_duration = FMC_LAST_TONE then -- -- restart playing from 1st tone -- addr <= (others => '0'); -- else -- addr <= std_logic_vector(unsigned(addr)+1); -- end if; -- end if; -- end if; -- end process; ----------------------------------------------------------------------------- -- Tone frequency Oscillator ----------------------------------------------------------------------------- P_tone_osc: process(clk, rst) begin if rst = '1' then seed <= (others => '0'); osc_cnt <= (others => '0'); elsif rising_edge(clk) then if(tick_nco = '1') then --f_clk_enb = 1MHz seed <= to_unsigned(nco_lut(to_integer(unsigned(tone_number))),13); osc_cnt <= osc_cnt + seed; end if; end if; end process; ----------------------------------------------------------------------------- -- channel number dependent FMC ROM instance ----------------------------------------------------------------------------- rom : entity work.fmc_rom generic map(N => N) port map (clk => clk, addr => addr, data => rom_data ); tone_duration <= unsigned(rom_data(FMC_DUR_WW+FMC_TON_WW-1 downto FMC_TON_WW)); tone_number <= rom_data(FMC_TON_WW-1 downto 0); end rtl;
gpl-3.0
f12dcebce83418650eee23154d41e472
0.473629
3.569899
false
false
false
false
hoglet67/AtomFpga
src/common/AVR8/CommonPacks/SynthCtrlPack.vhd
3
1,322
-- ***************************************************************************************** -- AVR synthesis control package -- Version 1.32 (Special version for the JTAG OCD) -- Modified 14.07.2005 -- Designed by Ruslan Lepetenok -- ***************************************************************************************** library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; package SynthCtrlPack is -- Function f_log2 returns the number of bits required to express -- an unsigned integer in binary. It is used, for example, to -- returns the width of a memory address bus, given the memory -- depth in words -- Function definition function f_log2 (x : positive) return natural; -- Reset generator constant CSecondClockUsed : boolean := FALSE; constant CImplClockSw : boolean := FALSE; -- Only for ASICs constant CSynchLatchUsed : boolean := FALSE; -- Register file constant CResetRegFile : boolean := TRUE; -- External multiplexer size constant CExtMuxInSize : positive := 16; end SynthCtrlPack; package body SynthCtrlPack is -- Function body function f_log2 (x : positive) return natural is variable i : natural; begin i := 0; while (2**i < x) and i < 31 loop i := i + 1; end loop; return i; end function; end SynthCtrlPack;
apache-2.0
6834089a34db4260dbce3f110902c1ce
0.601362
4.067692
false
false
false
false
tghaefli/ADD
ISE/FMC_waj/fmc_top.vhd
1
5,419
------------------------------------------------------------------------------- -- Entity: fmc_top -- Author: Waj ------------------------------------------------------------------------------- -- Description: (ECS Uebung 9) -- Top-level of Floppy-Music Controller peripheral module in MCU. ------------------------------------------------------------------------------- -- Total # of FFs: ... tbd ... ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.mcu_pkg.all; entity fmc_top is generic(CLK_FRQ : natural := CF ); port(rst : in std_logic; clk : in std_logic; -- FMC bus signals bus_in : in t_bus2rws; bus_out : out t_rws2bus; -- FMC pin signals fmc_enable : out std_logic_vector(FMC_NUM_CHN-1 downto 0); fmc_direct : out std_logic_vector(FMC_NUM_CHN-1 downto 0); fmc_step : out std_logic_vector(FMC_NUM_CHN-1 downto 0) ); end fmc_top; architecture rtl of fmc_top is -- address select signal signal addr_sel : t_fmc_addr_sel; -- peripheral registers signal chn_enb_reg : std_logic_vector(FMC_NUM_CHN-1 downto 0); signal tmp_ctrl_reg : std_logic_vector(9 downto 0); -- prescaler signals signal tick_dur, tick_nco : std_logic; signal tick_dur_cnt : unsigned(15 downto 0); signal tick_nco_cnt : unsigned( 5 downto 0); signal tick_dur_speed : unsigned(25 downto 0); -- prescaler constants constant C_TICK_DUR : unsigned(15 downto 0) := to_unsigned(CLK_FRQ/1_000 -1,16); -- 1 kHZ = 1s/1_000 constant C_TICK_NCO : unsigned( 5 downto 0) := to_unsigned(CLK_FRQ/1_000_000-1, 6); -- 1 MHZ = 1s/1_000_000 begin ----------------------------------------------------------------------------- -- Address Decoding (combinationally) ----------------------------------------------------------------------------- process(bus_in.addr) begin case bus_in.addr is -- FMC addresses -------------------------------------------------------- when c_addr_fmc_chn_enb => addr_sel <= fmc_chn_enb; when c_addr_fmc_tmp_ctrl => addr_sel <= fmc_tmp_ctrl; -- unused addresses ----------------------------------------------------- when others => addr_sel <= none; end case; end process; ----------------------------------------------------------------------------- -- Read Access (R and R/W registers) ----------------------------------------------------------------------------- P_read: process(clk) begin if rising_edge(clk) then -- default assignment bus_out.data <= (others => '0'); -- use address select signal case addr_sel is when fmc_chn_enb => bus_out.data(FMC_NUM_CHN-1 downto 0) <= chn_enb_reg; when fmc_tmp_ctrl => bus_out.data( 9 downto 0) <= tmp_ctrl_reg; when others => null; end case; end if; end process; ----------------------------------------------------------------------------- -- Write Access (R/W regsiters only) ----------------------------------------------------------------------------- P_write: process(clk, rst) begin if rst = '1' then chn_enb_reg <= (others => '0'); tmp_ctrl_reg <= (others => '0'); elsif rising_edge(clk) then if bus_in.wr_enb = '1' then -- use address select signal case addr_sel is when fmc_chn_enb => chn_enb_reg <= bus_in.data(FMC_NUM_CHN-1 downto 0); when fmc_tmp_ctrl => tmp_ctrl_reg <= bus_in.data( 9 downto 0); when others => null; end case; end if; end if; end process; ----------------------------------------------------------------------------- -- Clock Prescaler ----------------------------------------------------------------------------- P_scl: process(rst,clk) begin if rst = '1' then tick_dur_cnt <= (others => '0'); tick_nco_cnt <= (others => '0'); elsif rising_edge(clk) then -- default assignment tick_dur <= '0'; tick_nco <= '0'; tick_dur_cnt <= tick_dur_cnt + 1; tick_nco_cnt <= tick_nco_cnt + 1; -- maintain duration tick counter tick_dur_speed <= unsigned(tmp_ctrl_reg) * C_TICK_DUR; -- UFix_10_6 * UFix_16_0 = UFix_26_6 if tick_dur_cnt = tick_dur_speed(25 downto 6) then -- drop fractional bits tick_dur <= '1'; tick_dur_cnt <= (others => '0'); end if; -- maintain NCO tick counter if tick_nco_cnt = C_TICK_NCO then tick_nco <= '1'; tick_nco_cnt <= (others => '0'); end if; end if; end process; ----------------------------------------------------------------------------- -- Instantiation of FMC channels ----------------------------------------------------------------------------- fmc_i: for i in 0 to FMC_NUM_CHN-1 generate fmc_chn_i : entity work.fmc_chn generic map(N => i) port map (rst => rst, clk => clk, tick_dur => tick_dur, tick_nco => tick_nco, chn_enb => chn_enb_reg(i), fmc_enb => fmc_enable(i), fmc_dir => fmc_direct(i), fmc_stp => fmc_step(i) ); end generate; end rtl;
gpl-3.0
6da9d279733f5ec481ac3a6c51e7e7c8
0.429046
4.124049
false
false
false
false
hoglet67/AtomFpga
src/common/ROM/SDROM23ROM.vhd
1
152,358
-- generated with romgen v3.0.1r4 by MikeJ truhy and eD library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; library UNISIM; use UNISIM.Vcomponents.all; entity e000 is port ( CLK : in std_logic; ADDR : in std_logic_vector(11 downto 0); DATA : out std_logic_vector(7 downto 0) ); end; architecture RTL of e000 is signal rom_addr : std_logic_vector(11 downto 0); begin p_addr : process(ADDR) begin rom_addr <= (others => '0'); rom_addr(11 downto 0) <= ADDR; end process; p_rom : process begin wait until rising_edge(CLK); DATA <= (others => '0'); case rom_addr is when x"000" => DATA <= x"2C"; when x"001" => DATA <= x"01"; when x"002" => DATA <= x"B0"; when x"003" => DATA <= x"70"; when x"004" => DATA <= x"03"; when x"005" => DATA <= x"4C"; when x"006" => DATA <= x"B2"; when x"007" => DATA <= x"C2"; when x"008" => DATA <= x"98"; when x"009" => DATA <= x"48"; when x"00A" => DATA <= x"8A"; when x"00B" => DATA <= x"48"; when x"00C" => DATA <= x"A2"; when x"00D" => DATA <= x"00"; when x"00E" => DATA <= x"8E"; when x"00F" => DATA <= x"CA"; when x"010" => DATA <= x"03"; when x"011" => DATA <= x"A9"; when x"012" => DATA <= x"2B"; when x"013" => DATA <= x"8D"; when x"014" => DATA <= x"0B"; when x"015" => DATA <= x"80"; when x"016" => DATA <= x"BD"; when x"017" => DATA <= x"8A"; when x"018" => DATA <= x"EB"; when x"019" => DATA <= x"29"; when x"01A" => DATA <= x"BF"; when x"01B" => DATA <= x"9D"; when x"01C" => DATA <= x"0D"; when x"01D" => DATA <= x"80"; when x"01E" => DATA <= x"E8"; when x"01F" => DATA <= x"C9"; when x"020" => DATA <= x"20"; when x"021" => DATA <= x"D0"; when x"022" => DATA <= x"F3"; when x"023" => DATA <= x"20"; when x"024" => DATA <= x"D6"; when x"025" => DATA <= x"E7"; when x"026" => DATA <= x"2C"; when x"027" => DATA <= x"01"; when x"028" => DATA <= x"B0"; when x"029" => DATA <= x"30"; when x"02A" => DATA <= x"0A"; when x"02B" => DATA <= x"A9"; when x"02C" => DATA <= x"3C"; when x"02D" => DATA <= x"8D"; when x"02E" => DATA <= x"0A"; when x"02F" => DATA <= x"02"; when x"030" => DATA <= x"A9"; when x"031" => DATA <= x"E0"; when x"032" => DATA <= x"8D"; when x"033" => DATA <= x"0B"; when x"034" => DATA <= x"02"; when x"035" => DATA <= x"68"; when x"036" => DATA <= x"AA"; when x"037" => DATA <= x"68"; when x"038" => DATA <= x"A8"; when x"039" => DATA <= x"4C"; when x"03A" => DATA <= x"B2"; when x"03B" => DATA <= x"C2"; when x"03C" => DATA <= x"08"; when x"03D" => DATA <= x"D8"; when x"03E" => DATA <= x"86"; when x"03F" => DATA <= x"E4"; when x"040" => DATA <= x"84"; when x"041" => DATA <= x"E5"; when x"042" => DATA <= x"AE"; when x"043" => DATA <= x"CA"; when x"044" => DATA <= x"03"; when x"045" => DATA <= x"BD"; when x"046" => DATA <= x"66"; when x"047" => DATA <= x"E0"; when x"048" => DATA <= x"C9"; when x"049" => DATA <= x"0D"; when x"04A" => DATA <= x"F0"; when x"04B" => DATA <= x"0A"; when x"04C" => DATA <= x"E8"; when x"04D" => DATA <= x"8E"; when x"04E" => DATA <= x"CA"; when x"04F" => DATA <= x"03"; when x"050" => DATA <= x"A6"; when x"051" => DATA <= x"E4"; when x"052" => DATA <= x"A4"; when x"053" => DATA <= x"E5"; when x"054" => DATA <= x"28"; when x"055" => DATA <= x"60"; when x"056" => DATA <= x"A9"; when x"057" => DATA <= x"94"; when x"058" => DATA <= x"8D"; when x"059" => DATA <= x"0A"; when x"05A" => DATA <= x"02"; when x"05B" => DATA <= x"A9"; when x"05C" => DATA <= x"FE"; when x"05D" => DATA <= x"8D"; when x"05E" => DATA <= x"0B"; when x"05F" => DATA <= x"02"; when x"060" => DATA <= x"A9"; when x"061" => DATA <= x"0D"; when x"062" => DATA <= x"48"; when x"063" => DATA <= x"4C"; when x"064" => DATA <= x"5C"; when x"065" => DATA <= x"FE"; when x"066" => DATA <= x"2A"; when x"067" => DATA <= x"4D"; when x"068" => DATA <= x"45"; when x"069" => DATA <= x"4E"; when x"06A" => DATA <= x"55"; when x"06B" => DATA <= x"0D"; when x"06C" => DATA <= x"00"; when x"06D" => DATA <= x"6C"; when x"06E" => DATA <= x"52"; when x"06F" => DATA <= x"00"; when x"070" => DATA <= x"A2"; when x"071" => DATA <= x"FF"; when x"072" => DATA <= x"D8"; when x"073" => DATA <= x"A0"; when x"074" => DATA <= x"00"; when x"075" => DATA <= x"20"; when x"076" => DATA <= x"76"; when x"077" => DATA <= x"F8"; when x"078" => DATA <= x"88"; when x"079" => DATA <= x"C8"; when x"07A" => DATA <= x"E8"; when x"07B" => DATA <= x"BD"; when x"07C" => DATA <= x"CD"; when x"07D" => DATA <= x"E0"; when x"07E" => DATA <= x"30"; when x"07F" => DATA <= x"18"; when x"080" => DATA <= x"D9"; when x"081" => DATA <= x"00"; when x"082" => DATA <= x"01"; when x"083" => DATA <= x"F0"; when x"084" => DATA <= x"F4"; when x"085" => DATA <= x"CA"; when x"086" => DATA <= x"E8"; when x"087" => DATA <= x"BD"; when x"088" => DATA <= x"CD"; when x"089" => DATA <= x"E0"; when x"08A" => DATA <= x"10"; when x"08B" => DATA <= x"FA"; when x"08C" => DATA <= x"E8"; when x"08D" => DATA <= x"B9"; when x"08E" => DATA <= x"00"; when x"08F" => DATA <= x"01"; when x"090" => DATA <= x"C9"; when x"091" => DATA <= x"2E"; when x"092" => DATA <= x"D0"; when x"093" => DATA <= x"DF"; when x"094" => DATA <= x"C8"; when x"095" => DATA <= x"CA"; when x"096" => DATA <= x"B0"; when x"097" => DATA <= x"E3"; when x"098" => DATA <= x"84"; when x"099" => DATA <= x"9A"; when x"09A" => DATA <= x"A4"; when x"09B" => DATA <= x"03"; when x"09C" => DATA <= x"84"; when x"09D" => DATA <= x"D5"; when x"09E" => DATA <= x"A4"; when x"09F" => DATA <= x"05"; when x"0A0" => DATA <= x"84"; when x"0A1" => DATA <= x"D6"; when x"0A2" => DATA <= x"A4"; when x"0A3" => DATA <= x"06"; when x"0A4" => DATA <= x"84"; when x"0A5" => DATA <= x"D7"; when x"0A6" => DATA <= x"A0"; when x"0A7" => DATA <= x"00"; when x"0A8" => DATA <= x"84"; when x"0A9" => DATA <= x"05"; when x"0AA" => DATA <= x"A0"; when x"0AB" => DATA <= x"01"; when x"0AC" => DATA <= x"84"; when x"0AD" => DATA <= x"06"; when x"0AE" => DATA <= x"A4"; when x"0AF" => DATA <= x"9A"; when x"0B0" => DATA <= x"84"; when x"0B1" => DATA <= x"03"; when x"0B2" => DATA <= x"85"; when x"0B3" => DATA <= x"53"; when x"0B4" => DATA <= x"BD"; when x"0B5" => DATA <= x"CE"; when x"0B6" => DATA <= x"E0"; when x"0B7" => DATA <= x"85"; when x"0B8" => DATA <= x"52"; when x"0B9" => DATA <= x"20"; when x"0BA" => DATA <= x"6D"; when x"0BB" => DATA <= x"E0"; when x"0BC" => DATA <= x"A4"; when x"0BD" => DATA <= x"D6"; when x"0BE" => DATA <= x"84"; when x"0BF" => DATA <= x"05"; when x"0C0" => DATA <= x"A4"; when x"0C1" => DATA <= x"D7"; when x"0C2" => DATA <= x"84"; when x"0C3" => DATA <= x"06"; when x"0C4" => DATA <= x"A4"; when x"0C5" => DATA <= x"D5"; when x"0C6" => DATA <= x"84"; when x"0C7" => DATA <= x"03"; when x"0C8" => DATA <= x"A9"; when x"0C9" => DATA <= x"0D"; when x"0CA" => DATA <= x"91"; when x"0CB" => DATA <= x"05"; when x"0CC" => DATA <= x"60"; when x"0CD" => DATA <= x"43"; when x"0CE" => DATA <= x"41"; when x"0CF" => DATA <= x"54"; when x"0D0" => DATA <= x"E1"; when x"0D1" => DATA <= x"8A"; when x"0D2" => DATA <= x"44"; when x"0D3" => DATA <= x"45"; when x"0D4" => DATA <= x"4C"; when x"0D5" => DATA <= x"45"; when x"0D6" => DATA <= x"54"; when x"0D7" => DATA <= x"45"; when x"0D8" => DATA <= x"E2"; when x"0D9" => DATA <= x"B7"; when x"0DA" => DATA <= x"44"; when x"0DB" => DATA <= x"49"; when x"0DC" => DATA <= x"52"; when x"0DD" => DATA <= x"E2"; when x"0DE" => DATA <= x"DA"; when x"0DF" => DATA <= x"44"; when x"0E0" => DATA <= x"52"; when x"0E1" => DATA <= x"49"; when x"0E2" => DATA <= x"56"; when x"0E3" => DATA <= x"45"; when x"0E4" => DATA <= x"E2"; when x"0E5" => DATA <= x"E0"; when x"0E6" => DATA <= x"49"; when x"0E7" => DATA <= x"4E"; when x"0E8" => DATA <= x"46"; when x"0E9" => DATA <= x"4F"; when x"0EA" => DATA <= x"E2"; when x"0EB" => DATA <= x"F5"; when x"0EC" => DATA <= x"49"; when x"0ED" => DATA <= x"4E"; when x"0EE" => DATA <= x"46"; when x"0EF" => DATA <= x"41"; when x"0F0" => DATA <= x"4C"; when x"0F1" => DATA <= x"4C"; when x"0F2" => DATA <= x"E2"; when x"0F3" => DATA <= x"FB"; when x"0F4" => DATA <= x"4C"; when x"0F5" => DATA <= x"4F"; when x"0F6" => DATA <= x"41"; when x"0F7" => DATA <= x"44"; when x"0F8" => DATA <= x"E3"; when x"0F9" => DATA <= x"12"; when x"0FA" => DATA <= x"4C"; when x"0FB" => DATA <= x"4F"; when x"0FC" => DATA <= x"43"; when x"0FD" => DATA <= x"4B"; when x"0FE" => DATA <= x"E3"; when x"0FF" => DATA <= x"BD"; when x"100" => DATA <= x"4D"; when x"101" => DATA <= x"4F"; when x"102" => DATA <= x"4E"; when x"103" => DATA <= x"E3"; when x"104" => DATA <= x"C1"; when x"105" => DATA <= x"4E"; when x"106" => DATA <= x"4F"; when x"107" => DATA <= x"4D"; when x"108" => DATA <= x"4F"; when x"109" => DATA <= x"4E"; when x"10A" => DATA <= x"E3"; when x"10B" => DATA <= x"CB"; when x"10C" => DATA <= x"52"; when x"10D" => DATA <= x"55"; when x"10E" => DATA <= x"4E"; when x"10F" => DATA <= x"E3"; when x"110" => DATA <= x"D0"; when x"111" => DATA <= x"53"; when x"112" => DATA <= x"41"; when x"113" => DATA <= x"56"; when x"114" => DATA <= x"45"; when x"115" => DATA <= x"E3"; when x"116" => DATA <= x"DB"; when x"117" => DATA <= x"53"; when x"118" => DATA <= x"45"; when x"119" => DATA <= x"54"; when x"11A" => DATA <= x"E5"; when x"11B" => DATA <= x"79"; when x"11C" => DATA <= x"54"; when x"11D" => DATA <= x"49"; when x"11E" => DATA <= x"54"; when x"11F" => DATA <= x"4C"; when x"120" => DATA <= x"45"; when x"121" => DATA <= x"E5"; when x"122" => DATA <= x"87"; when x"123" => DATA <= x"55"; when x"124" => DATA <= x"4E"; when x"125" => DATA <= x"4C"; when x"126" => DATA <= x"4F"; when x"127" => DATA <= x"43"; when x"128" => DATA <= x"4B"; when x"129" => DATA <= x"E5"; when x"12A" => DATA <= x"F1"; when x"12B" => DATA <= x"55"; when x"12C" => DATA <= x"53"; when x"12D" => DATA <= x"45"; when x"12E" => DATA <= x"E6"; when x"12F" => DATA <= x"10"; when x"130" => DATA <= x"44"; when x"131" => DATA <= x"49"; when x"132" => DATA <= x"4E"; when x"133" => DATA <= x"E8"; when x"134" => DATA <= x"31"; when x"135" => DATA <= x"44"; when x"136" => DATA <= x"43"; when x"137" => DATA <= x"41"; when x"138" => DATA <= x"54"; when x"139" => DATA <= x"E8"; when x"13A" => DATA <= x"94"; when x"13B" => DATA <= x"44"; when x"13C" => DATA <= x"44"; when x"13D" => DATA <= x"49"; when x"13E" => DATA <= x"53"; when x"13F" => DATA <= x"4B"; when x"140" => DATA <= x"53"; when x"141" => DATA <= x"E9"; when x"142" => DATA <= x"3F"; when x"143" => DATA <= x"44"; when x"144" => DATA <= x"50"; when x"145" => DATA <= x"52"; when x"146" => DATA <= x"4F"; when x"147" => DATA <= x"54"; when x"148" => DATA <= x"E9"; when x"149" => DATA <= x"85"; when x"14A" => DATA <= x"44"; when x"14B" => DATA <= x"55"; when x"14C" => DATA <= x"4E"; when x"14D" => DATA <= x"50"; when x"14E" => DATA <= x"52"; when x"14F" => DATA <= x"4F"; when x"150" => DATA <= x"54"; when x"151" => DATA <= x"E9"; when x"152" => DATA <= x"9D"; when x"153" => DATA <= x"44"; when x"154" => DATA <= x"46"; when x"155" => DATA <= x"52"; when x"156" => DATA <= x"45"; when x"157" => DATA <= x"45"; when x"158" => DATA <= x"E9"; when x"159" => DATA <= x"B5"; when x"15A" => DATA <= x"44"; when x"15B" => DATA <= x"4B"; when x"15C" => DATA <= x"49"; when x"15D" => DATA <= x"4C"; when x"15E" => DATA <= x"4C"; when x"15F" => DATA <= x"EA"; when x"160" => DATA <= x"23"; when x"161" => DATA <= x"44"; when x"162" => DATA <= x"52"; when x"163" => DATA <= x"45"; when x"164" => DATA <= x"53"; when x"165" => DATA <= x"54"; when x"166" => DATA <= x"4F"; when x"167" => DATA <= x"52"; when x"168" => DATA <= x"45"; when x"169" => DATA <= x"EA"; when x"16A" => DATA <= x"61"; when x"16B" => DATA <= x"44"; when x"16C" => DATA <= x"4E"; when x"16D" => DATA <= x"45"; when x"16E" => DATA <= x"57"; when x"16F" => DATA <= x"EA"; when x"170" => DATA <= x"76"; when x"171" => DATA <= x"44"; when x"172" => DATA <= x"46"; when x"173" => DATA <= x"4F"; when x"174" => DATA <= x"52"; when x"175" => DATA <= x"4D"; when x"176" => DATA <= x"EA"; when x"177" => DATA <= x"EE"; when x"178" => DATA <= x"44"; when x"179" => DATA <= x"4F"; when x"17A" => DATA <= x"4E"; when x"17B" => DATA <= x"42"; when x"17C" => DATA <= x"4F"; when x"17D" => DATA <= x"4F"; when x"17E" => DATA <= x"54"; when x"17F" => DATA <= x"EB"; when x"180" => DATA <= x"64"; when x"181" => DATA <= x"44"; when x"182" => DATA <= x"48"; when x"183" => DATA <= x"45"; when x"184" => DATA <= x"4C"; when x"185" => DATA <= x"50"; when x"186" => DATA <= x"EB"; when x"187" => DATA <= x"81"; when x"188" => DATA <= x"E6"; when x"189" => DATA <= x"20"; when x"18A" => DATA <= x"20"; when x"18B" => DATA <= x"DA"; when x"18C" => DATA <= x"E2"; when x"18D" => DATA <= x"A2"; when x"18E" => DATA <= x"00"; when x"18F" => DATA <= x"86"; when x"190" => DATA <= x"B6"; when x"191" => DATA <= x"BD"; when x"192" => DATA <= x"00"; when x"193" => DATA <= x"20"; when x"194" => DATA <= x"E0"; when x"195" => DATA <= x"08"; when x"196" => DATA <= x"90"; when x"197" => DATA <= x"03"; when x"198" => DATA <= x"BD"; when x"199" => DATA <= x"F8"; when x"19A" => DATA <= x"20"; when x"19B" => DATA <= x"20"; when x"19C" => DATA <= x"F4"; when x"19D" => DATA <= x"FF"; when x"19E" => DATA <= x"E8"; when x"19F" => DATA <= x"E0"; when x"1A0" => DATA <= x"0D"; when x"1A1" => DATA <= x"D0"; when x"1A2" => DATA <= x"EE"; when x"1A3" => DATA <= x"20"; when x"1A4" => DATA <= x"D1"; when x"1A5" => DATA <= x"F7"; when x"1A6" => DATA <= x"20"; when x"1A7" => DATA <= x"44"; when x"1A8" => DATA <= x"52"; when x"1A9" => DATA <= x"3A"; when x"1AA" => DATA <= x"EA"; when x"1AB" => DATA <= x"A5"; when x"1AC" => DATA <= x"EE"; when x"1AD" => DATA <= x"20"; when x"1AE" => DATA <= x"0B"; when x"1AF" => DATA <= x"F8"; when x"1B0" => DATA <= x"20"; when x"1B1" => DATA <= x"D1"; when x"1B2" => DATA <= x"F7"; when x"1B3" => DATA <= x"20"; when x"1B4" => DATA <= x"51"; when x"1B5" => DATA <= x"3A"; when x"1B6" => DATA <= x"EA"; when x"1B7" => DATA <= x"A5"; when x"1B8" => DATA <= x"AC"; when x"1B9" => DATA <= x"20"; when x"1BA" => DATA <= x"F4"; when x"1BB" => DATA <= x"FF"; when x"1BC" => DATA <= x"20"; when x"1BD" => DATA <= x"D1"; when x"1BE" => DATA <= x"F7"; when x"1BF" => DATA <= x"20"; when x"1C0" => DATA <= x"44"; when x"1C1" => DATA <= x"53"; when x"1C2" => DATA <= x"4B"; when x"1C3" => DATA <= x"3A"; when x"1C4" => DATA <= x"EA"; when x"1C5" => DATA <= x"A5"; when x"1C6" => DATA <= x"EE"; when x"1C7" => DATA <= x"0A"; when x"1C8" => DATA <= x"A8"; when x"1C9" => DATA <= x"B6"; when x"1CA" => DATA <= x"F0"; when x"1CB" => DATA <= x"B9"; when x"1CC" => DATA <= x"F1"; when x"1CD" => DATA <= x"00"; when x"1CE" => DATA <= x"A8"; when x"1CF" => DATA <= x"20"; when x"1D0" => DATA <= x"88"; when x"1D1" => DATA <= x"ED"; when x"1D2" => DATA <= x"A0"; when x"1D3" => DATA <= x"00"; when x"1D4" => DATA <= x"20"; when x"1D5" => DATA <= x"ED"; when x"1D6" => DATA <= x"E1"; when x"1D7" => DATA <= x"90"; when x"1D8" => DATA <= x"4A"; when x"1D9" => DATA <= x"20"; when x"1DA" => DATA <= x"15"; when x"1DB" => DATA <= x"EE"; when x"1DC" => DATA <= x"B9"; when x"1DD" => DATA <= x"08"; when x"1DE" => DATA <= x"20"; when x"1DF" => DATA <= x"29"; when x"1E0" => DATA <= x"7F"; when x"1E1" => DATA <= x"99"; when x"1E2" => DATA <= x"08"; when x"1E3" => DATA <= x"20"; when x"1E4" => DATA <= x"98"; when x"1E5" => DATA <= x"D0"; when x"1E6" => DATA <= x"F2"; when x"1E7" => DATA <= x"4C"; when x"1E8" => DATA <= x"ED"; when x"1E9" => DATA <= x"FF"; when x"1EA" => DATA <= x"20"; when x"1EB" => DATA <= x"0C"; when x"1EC" => DATA <= x"EE"; when x"1ED" => DATA <= x"CC"; when x"1EE" => DATA <= x"05"; when x"1EF" => DATA <= x"21"; when x"1F0" => DATA <= x"B0"; when x"1F1" => DATA <= x"05"; when x"1F2" => DATA <= x"B9"; when x"1F3" => DATA <= x"08"; when x"1F4" => DATA <= x"20"; when x"1F5" => DATA <= x"30"; when x"1F6" => DATA <= x"F3"; when x"1F7" => DATA <= x"60"; when x"1F8" => DATA <= x"A4"; when x"1F9" => DATA <= x"B8"; when x"1FA" => DATA <= x"F0"; when x"1FB" => DATA <= x"05"; when x"1FC" => DATA <= x"20"; when x"1FD" => DATA <= x"ED"; when x"1FE" => DATA <= x"FF"; when x"1FF" => DATA <= x"A0"; when x"200" => DATA <= x"FF"; when x"201" => DATA <= x"C8"; when x"202" => DATA <= x"84"; when x"203" => DATA <= x"B8"; when x"204" => DATA <= x"20"; when x"205" => DATA <= x"03"; when x"206" => DATA <= x"EE"; when x"207" => DATA <= x"A9"; when x"208" => DATA <= x"23"; when x"209" => DATA <= x"A4"; when x"20A" => DATA <= x"B7"; when x"20B" => DATA <= x"BE"; when x"20C" => DATA <= x"0F"; when x"20D" => DATA <= x"20"; when x"20E" => DATA <= x"30"; when x"20F" => DATA <= x"02"; when x"210" => DATA <= x"A9"; when x"211" => DATA <= x"20"; when x"212" => DATA <= x"20"; when x"213" => DATA <= x"F4"; when x"214" => DATA <= x"FF"; when x"215" => DATA <= x"A2"; when x"216" => DATA <= x"00"; when x"217" => DATA <= x"B5"; when x"218" => DATA <= x"AE"; when x"219" => DATA <= x"20"; when x"21A" => DATA <= x"F4"; when x"21B" => DATA <= x"FF"; when x"21C" => DATA <= x"E8"; when x"21D" => DATA <= x"E0"; when x"21E" => DATA <= x"07"; when x"21F" => DATA <= x"D0"; when x"220" => DATA <= x"F6"; when x"221" => DATA <= x"F0"; when x"222" => DATA <= x"AF"; when x"223" => DATA <= x"84"; when x"224" => DATA <= x"B7"; when x"225" => DATA <= x"A2"; when x"226" => DATA <= x"00"; when x"227" => DATA <= x"B9"; when x"228" => DATA <= x"08"; when x"229" => DATA <= x"20"; when x"22A" => DATA <= x"29"; when x"22B" => DATA <= x"7F"; when x"22C" => DATA <= x"95"; when x"22D" => DATA <= x"AE"; when x"22E" => DATA <= x"C8"; when x"22F" => DATA <= x"E8"; when x"230" => DATA <= x"E0"; when x"231" => DATA <= x"08"; when x"232" => DATA <= x"D0"; when x"233" => DATA <= x"F3"; when x"234" => DATA <= x"20"; when x"235" => DATA <= x"ED"; when x"236" => DATA <= x"E1"; when x"237" => DATA <= x"B0"; when x"238" => DATA <= x"1D"; when x"239" => DATA <= x"A2"; when x"23A" => DATA <= x"06"; when x"23B" => DATA <= x"38"; when x"23C" => DATA <= x"B9"; when x"23D" => DATA <= x"0E"; when x"23E" => DATA <= x"20"; when x"23F" => DATA <= x"F5"; when x"240" => DATA <= x"AE"; when x"241" => DATA <= x"88"; when x"242" => DATA <= x"CA"; when x"243" => DATA <= x"10"; when x"244" => DATA <= x"F7"; when x"245" => DATA <= x"20"; when x"246" => DATA <= x"0D"; when x"247" => DATA <= x"EE"; when x"248" => DATA <= x"B9"; when x"249" => DATA <= x"0F"; when x"24A" => DATA <= x"20"; when x"24B" => DATA <= x"29"; when x"24C" => DATA <= x"7F"; when x"24D" => DATA <= x"E5"; when x"24E" => DATA <= x"B5"; when x"24F" => DATA <= x"90"; when x"250" => DATA <= x"D2"; when x"251" => DATA <= x"20"; when x"252" => DATA <= x"0C"; when x"253" => DATA <= x"EE"; when x"254" => DATA <= x"B0"; when x"255" => DATA <= x"DE"; when x"256" => DATA <= x"A4"; when x"257" => DATA <= x"B7"; when x"258" => DATA <= x"B9"; when x"259" => DATA <= x"08"; when x"25A" => DATA <= x"20"; when x"25B" => DATA <= x"09"; when x"25C" => DATA <= x"80"; when x"25D" => DATA <= x"99"; when x"25E" => DATA <= x"08"; when x"25F" => DATA <= x"20"; when x"260" => DATA <= x"A5"; when x"261" => DATA <= x"B5"; when x"262" => DATA <= x"C5"; when x"263" => DATA <= x"B6"; when x"264" => DATA <= x"F0"; when x"265" => DATA <= x"92"; when x"266" => DATA <= x"85"; when x"267" => DATA <= x"B6"; when x"268" => DATA <= x"20"; when x"269" => DATA <= x"ED"; when x"26A" => DATA <= x"FF"; when x"26B" => DATA <= x"A5"; when x"26C" => DATA <= x"B5"; when x"26D" => DATA <= x"20"; when x"26E" => DATA <= x"F4"; when x"26F" => DATA <= x"FF"; when x"270" => DATA <= x"A9"; when x"271" => DATA <= x"3A"; when x"272" => DATA <= x"20"; when x"273" => DATA <= x"F4"; when x"274" => DATA <= x"FF"; when x"275" => DATA <= x"A0"; when x"276" => DATA <= x"04"; when x"277" => DATA <= x"20"; when x"278" => DATA <= x"05"; when x"279" => DATA <= x"EE"; when x"27A" => DATA <= x"84"; when x"27B" => DATA <= x"B8"; when x"27C" => DATA <= x"F0"; when x"27D" => DATA <= x"89"; when x"27E" => DATA <= x"B9"; when x"27F" => DATA <= x"0E"; when x"280" => DATA <= x"21"; when x"281" => DATA <= x"20"; when x"282" => DATA <= x"1F"; when x"283" => DATA <= x"EE"; when x"284" => DATA <= x"85"; when x"285" => DATA <= x"A2"; when x"286" => DATA <= x"18"; when x"287" => DATA <= x"A9"; when x"288" => DATA <= x"FF"; when x"289" => DATA <= x"79"; when x"28A" => DATA <= x"0C"; when x"28B" => DATA <= x"21"; when x"28C" => DATA <= x"B9"; when x"28D" => DATA <= x"0F"; when x"28E" => DATA <= x"21"; when x"28F" => DATA <= x"79"; when x"290" => DATA <= x"0D"; when x"291" => DATA <= x"21"; when x"292" => DATA <= x"85"; when x"293" => DATA <= x"A3"; when x"294" => DATA <= x"B9"; when x"295" => DATA <= x"0E"; when x"296" => DATA <= x"21"; when x"297" => DATA <= x"29"; when x"298" => DATA <= x"0F"; when x"299" => DATA <= x"65"; when x"29A" => DATA <= x"A2"; when x"29B" => DATA <= x"85"; when x"29C" => DATA <= x"A2"; when x"29D" => DATA <= x"38"; when x"29E" => DATA <= x"B9"; when x"29F" => DATA <= x"07"; when x"2A0" => DATA <= x"21"; when x"2A1" => DATA <= x"E5"; when x"2A2" => DATA <= x"A3"; when x"2A3" => DATA <= x"48"; when x"2A4" => DATA <= x"B9"; when x"2A5" => DATA <= x"06"; when x"2A6" => DATA <= x"21"; when x"2A7" => DATA <= x"29"; when x"2A8" => DATA <= x"0F"; when x"2A9" => DATA <= x"E5"; when x"2AA" => DATA <= x"A2"; when x"2AB" => DATA <= x"AA"; when x"2AC" => DATA <= x"A9"; when x"2AD" => DATA <= x"00"; when x"2AE" => DATA <= x"C5"; when x"2AF" => DATA <= x"A0"; when x"2B0" => DATA <= x"68"; when x"2B1" => DATA <= x"E5"; when x"2B2" => DATA <= x"A1"; when x"2B3" => DATA <= x"8A"; when x"2B4" => DATA <= x"E9"; when x"2B5" => DATA <= x"00"; when x"2B6" => DATA <= x"60"; when x"2B7" => DATA <= x"20"; when x"2B8" => DATA <= x"E4"; when x"2B9" => DATA <= x"ED"; when x"2BA" => DATA <= x"B9"; when x"2BB" => DATA <= x"0F"; when x"2BC" => DATA <= x"20"; when x"2BD" => DATA <= x"30"; when x"2BE" => DATA <= x"11"; when x"2BF" => DATA <= x"20"; when x"2C0" => DATA <= x"FA"; when x"2C1" => DATA <= x"E6"; when x"2C2" => DATA <= x"20"; when x"2C3" => DATA <= x"63"; when x"2C4" => DATA <= x"E6"; when x"2C5" => DATA <= x"A4"; when x"2C6" => DATA <= x"9A"; when x"2C7" => DATA <= x"20"; when x"2C8" => DATA <= x"AD"; when x"2C9" => DATA <= x"E7"; when x"2CA" => DATA <= x"20"; when x"2CB" => DATA <= x"7B"; when x"2CC" => DATA <= x"EC"; when x"2CD" => DATA <= x"4C"; when x"2CE" => DATA <= x"56"; when x"2CF" => DATA <= x"E3"; when x"2D0" => DATA <= x"20"; when x"2D1" => DATA <= x"D1"; when x"2D2" => DATA <= x"F7"; when x"2D3" => DATA <= x"50"; when x"2D4" => DATA <= x"52"; when x"2D5" => DATA <= x"4F"; when x"2D6" => DATA <= x"54"; when x"2D7" => DATA <= x"3F"; when x"2D8" => DATA <= x"EA"; when x"2D9" => DATA <= x"00"; when x"2DA" => DATA <= x"20"; when x"2DB" => DATA <= x"E0"; when x"2DC" => DATA <= x"E2"; when x"2DD" => DATA <= x"4C"; when x"2DE" => DATA <= x"2D"; when x"2DF" => DATA <= x"EC"; when x"2E0" => DATA <= x"20"; when x"2E1" => DATA <= x"76"; when x"2E2" => DATA <= x"F8"; when x"2E3" => DATA <= x"C9"; when x"2E4" => DATA <= x"0D"; when x"2E5" => DATA <= x"F0"; when x"2E6" => DATA <= x"0D"; when x"2E7" => DATA <= x"20"; when x"2E8" => DATA <= x"3E"; when x"2E9" => DATA <= x"ED"; when x"2EA" => DATA <= x"45"; when x"2EB" => DATA <= x"EE"; when x"2EC" => DATA <= x"C9"; when x"2ED" => DATA <= x"80"; when x"2EE" => DATA <= x"F0"; when x"2EF" => DATA <= x"04"; when x"2F0" => DATA <= x"45"; when x"2F1" => DATA <= x"EE"; when x"2F2" => DATA <= x"85"; when x"2F3" => DATA <= x"EE"; when x"2F4" => DATA <= x"60"; when x"2F5" => DATA <= x"20"; when x"2F6" => DATA <= x"E4"; when x"2F7" => DATA <= x"ED"; when x"2F8" => DATA <= x"4C"; when x"2F9" => DATA <= x"FE"; when x"2FA" => DATA <= x"E6"; when x"2FB" => DATA <= x"20"; when x"2FC" => DATA <= x"2D"; when x"2FD" => DATA <= x"EC"; when x"2FE" => DATA <= x"A0"; when x"2FF" => DATA <= x"00"; when x"300" => DATA <= x"84"; when x"301" => DATA <= x"9A"; when x"302" => DATA <= x"20"; when x"303" => DATA <= x"FE"; when x"304" => DATA <= x"E6"; when x"305" => DATA <= x"A4"; when x"306" => DATA <= x"9A"; when x"307" => DATA <= x"20"; when x"308" => DATA <= x"0C"; when x"309" => DATA <= x"EE"; when x"30A" => DATA <= x"84"; when x"30B" => DATA <= x"9A"; when x"30C" => DATA <= x"CC"; when x"30D" => DATA <= x"05"; when x"30E" => DATA <= x"21"; when x"30F" => DATA <= x"D0"; when x"310" => DATA <= x"F1"; when x"311" => DATA <= x"60"; when x"312" => DATA <= x"20"; when x"313" => DATA <= x"63"; when x"314" => DATA <= x"E7"; when x"315" => DATA <= x"A2"; when x"316" => DATA <= x"9C"; when x"317" => DATA <= x"20"; when x"318" => DATA <= x"93"; when x"319" => DATA <= x"F8"; when x"31A" => DATA <= x"F0"; when x"31B" => DATA <= x"04"; when x"31C" => DATA <= x"A9"; when x"31D" => DATA <= x"FF"; when x"31E" => DATA <= x"85"; when x"31F" => DATA <= x"9E"; when x"320" => DATA <= x"A2"; when x"321" => DATA <= x"9A"; when x"322" => DATA <= x"18"; when x"323" => DATA <= x"6C"; when x"324" => DATA <= x"0C"; when x"325" => DATA <= x"02"; when x"326" => DATA <= x"20"; when x"327" => DATA <= x"E7"; when x"328" => DATA <= x"ED"; when x"329" => DATA <= x"A2"; when x"32A" => DATA <= x"00"; when x"32B" => DATA <= x"A5"; when x"32C" => DATA <= x"9E"; when x"32D" => DATA <= x"10"; when x"32E" => DATA <= x"04"; when x"32F" => DATA <= x"A2"; when x"330" => DATA <= x"02"; when x"331" => DATA <= x"C8"; when x"332" => DATA <= x"C8"; when x"333" => DATA <= x"B9"; when x"334" => DATA <= x"08"; when x"335" => DATA <= x"21"; when x"336" => DATA <= x"95"; when x"337" => DATA <= x"9C"; when x"338" => DATA <= x"C8"; when x"339" => DATA <= x"E8"; when x"33A" => DATA <= x"E0"; when x"33B" => DATA <= x"08"; when x"33C" => DATA <= x"D0"; when x"33D" => DATA <= x"F5"; when x"33E" => DATA <= x"A5"; when x"33F" => DATA <= x"9C"; when x"340" => DATA <= x"85"; when x"341" => DATA <= x"F9"; when x"342" => DATA <= x"A5"; when x"343" => DATA <= x"9D"; when x"344" => DATA <= x"85"; when x"345" => DATA <= x"FA"; when x"346" => DATA <= x"A5"; when x"347" => DATA <= x"A0"; when x"348" => DATA <= x"85"; when x"349" => DATA <= x"FB"; when x"34A" => DATA <= x"A5"; when x"34B" => DATA <= x"A1"; when x"34C" => DATA <= x"85"; when x"34D" => DATA <= x"FC"; when x"34E" => DATA <= x"20"; when x"34F" => DATA <= x"5B"; when x"350" => DATA <= x"E3"; when x"351" => DATA <= x"A4"; when x"352" => DATA <= x"9A"; when x"353" => DATA <= x"20"; when x"354" => DATA <= x"FA"; when x"355" => DATA <= x"E6"; when x"356" => DATA <= x"A5"; when x"357" => DATA <= x"AD"; when x"358" => DATA <= x"85"; when x"359" => DATA <= x"AC"; when x"35A" => DATA <= x"60"; when x"35B" => DATA <= x"20"; when x"35C" => DATA <= x"8B"; when x"35D" => DATA <= x"EC"; when x"35E" => DATA <= x"24"; when x"35F" => DATA <= x"FD"; when x"360" => DATA <= x"30"; when x"361" => DATA <= x"03"; when x"362" => DATA <= x"4C"; when x"363" => DATA <= x"70"; when x"364" => DATA <= x"E3"; when x"365" => DATA <= x"20"; when x"366" => DATA <= x"9F"; when x"367" => DATA <= x"EE"; when x"368" => DATA <= x"20"; when x"369" => DATA <= x"B4"; when x"36A" => DATA <= x"E3"; when x"36B" => DATA <= x"A2"; when x"36C" => DATA <= x"01"; when x"36D" => DATA <= x"4C"; when x"36E" => DATA <= x"75"; when x"36F" => DATA <= x"E3"; when x"370" => DATA <= x"20"; when x"371" => DATA <= x"9F"; when x"372" => DATA <= x"EE"; when x"373" => DATA <= x"A2"; when x"374" => DATA <= x"02"; when x"375" => DATA <= x"A0"; when x"376" => DATA <= x"00"; when x"377" => DATA <= x"20"; when x"378" => DATA <= x"FB"; when x"379" => DATA <= x"EF"; when x"37A" => DATA <= x"91"; when x"37B" => DATA <= x"F9"; when x"37C" => DATA <= x"A5"; when x"37D" => DATA <= x"FB"; when x"37E" => DATA <= x"D0"; when x"37F" => DATA <= x"02"; when x"380" => DATA <= x"C6"; when x"381" => DATA <= x"FC"; when x"382" => DATA <= x"C6"; when x"383" => DATA <= x"FB"; when x"384" => DATA <= x"A5"; when x"385" => DATA <= x"FB"; when x"386" => DATA <= x"05"; when x"387" => DATA <= x"FC"; when x"388" => DATA <= x"F0"; when x"389" => DATA <= x"18"; when x"38A" => DATA <= x"C8"; when x"38B" => DATA <= x"D0"; when x"38C" => DATA <= x"EA"; when x"38D" => DATA <= x"E6"; when x"38E" => DATA <= x"FA"; when x"38F" => DATA <= x"CA"; when x"390" => DATA <= x"D0"; when x"391" => DATA <= x"E3"; when x"392" => DATA <= x"20"; when x"393" => DATA <= x"AE"; when x"394" => DATA <= x"EE"; when x"395" => DATA <= x"E6"; when x"396" => DATA <= x"84"; when x"397" => DATA <= x"D0"; when x"398" => DATA <= x"06"; when x"399" => DATA <= x"E6"; when x"39A" => DATA <= x"85"; when x"39B" => DATA <= x"D0"; when x"39C" => DATA <= x"02"; when x"39D" => DATA <= x"E6"; when x"39E" => DATA <= x"86"; when x"39F" => DATA <= x"4C"; when x"3A0" => DATA <= x"70"; when x"3A1" => DATA <= x"E3"; when x"3A2" => DATA <= x"C0"; when x"3A3" => DATA <= x"00"; when x"3A4" => DATA <= x"F0"; when x"3A5" => DATA <= x"04"; when x"3A6" => DATA <= x"20"; when x"3A7" => DATA <= x"B6"; when x"3A8" => DATA <= x"E3"; when x"3A9" => DATA <= x"CA"; when x"3AA" => DATA <= x"E0"; when x"3AB" => DATA <= x"00"; when x"3AC" => DATA <= x"F0"; when x"3AD" => DATA <= x"03"; when x"3AE" => DATA <= x"20"; when x"3AF" => DATA <= x"B4"; when x"3B0" => DATA <= x"E3"; when x"3B1" => DATA <= x"4C"; when x"3B2" => DATA <= x"AE"; when x"3B3" => DATA <= x"EE"; when x"3B4" => DATA <= x"A0"; when x"3B5" => DATA <= x"00"; when x"3B6" => DATA <= x"20"; when x"3B7" => DATA <= x"FB"; when x"3B8" => DATA <= x"EF"; when x"3B9" => DATA <= x"C8"; when x"3BA" => DATA <= x"D0"; when x"3BB" => DATA <= x"FA"; when x"3BC" => DATA <= x"60"; when x"3BD" => DATA <= x"38"; when x"3BE" => DATA <= x"4C"; when x"3BF" => DATA <= x"F2"; when x"3C0" => DATA <= x"E5"; when x"3C1" => DATA <= x"A2"; when x"3C2" => DATA <= x"00"; when x"3C3" => DATA <= x"20"; when x"3C4" => DATA <= x"F0"; when x"3C5" => DATA <= x"ED"; when x"3C6" => DATA <= x"86"; when x"3C7" => DATA <= x"EF"; when x"3C8" => DATA <= x"4C"; when x"3C9" => DATA <= x"56"; when x"3CA" => DATA <= x"E3"; when x"3CB" => DATA <= x"A2"; when x"3CC" => DATA <= x"FF"; when x"3CD" => DATA <= x"4C"; when x"3CE" => DATA <= x"C3"; when x"3CF" => DATA <= x"E3"; when x"3D0" => DATA <= x"20"; when x"3D1" => DATA <= x"12"; when x"3D2" => DATA <= x"E3"; when x"3D3" => DATA <= x"A4"; when x"3D4" => DATA <= x"03"; when x"3D5" => DATA <= x"20"; when x"3D6" => DATA <= x"51"; when x"3D7" => DATA <= x"E6"; when x"3D8" => DATA <= x"6C"; when x"3D9" => DATA <= x"9E"; when x"3DA" => DATA <= x"00"; when x"3DB" => DATA <= x"20"; when x"3DC" => DATA <= x"63"; when x"3DD" => DATA <= x"E7"; when x"3DE" => DATA <= x"A2"; when x"3DF" => DATA <= x"9C"; when x"3E0" => DATA <= x"20"; when x"3E1" => DATA <= x"65"; when x"3E2" => DATA <= x"FA"; when x"3E3" => DATA <= x"A2"; when x"3E4" => DATA <= x"A2"; when x"3E5" => DATA <= x"20"; when x"3E6" => DATA <= x"65"; when x"3E7" => DATA <= x"FA"; when x"3E8" => DATA <= x"A2"; when x"3E9" => DATA <= x"9E"; when x"3EA" => DATA <= x"20"; when x"3EB" => DATA <= x"93"; when x"3EC" => DATA <= x"F8"; when x"3ED" => DATA <= x"08"; when x"3EE" => DATA <= x"A5"; when x"3EF" => DATA <= x"9C"; when x"3F0" => DATA <= x"A6"; when x"3F1" => DATA <= x"9D"; when x"3F2" => DATA <= x"28"; when x"3F3" => DATA <= x"D0"; when x"3F4" => DATA <= x"04"; when x"3F5" => DATA <= x"85"; when x"3F6" => DATA <= x"9E"; when x"3F7" => DATA <= x"86"; when x"3F8" => DATA <= x"9F"; when x"3F9" => DATA <= x"85"; when x"3FA" => DATA <= x"A0"; when x"3FB" => DATA <= x"86"; when x"3FC" => DATA <= x"A1"; when x"3FD" => DATA <= x"84"; when x"3FE" => DATA <= x"03"; when x"3FF" => DATA <= x"20"; when x"400" => DATA <= x"76"; when x"401" => DATA <= x"FA"; when x"402" => DATA <= x"A2"; when x"403" => DATA <= x"9A"; when x"404" => DATA <= x"18"; when x"405" => DATA <= x"6C"; when x"406" => DATA <= x"0E"; when x"407" => DATA <= x"02"; when x"408" => DATA <= x"20"; when x"409" => DATA <= x"91"; when x"40A" => DATA <= x"E6"; when x"40B" => DATA <= x"20"; when x"40C" => DATA <= x"2D"; when x"40D" => DATA <= x"EC"; when x"40E" => DATA <= x"20"; when x"40F" => DATA <= x"63"; when x"410" => DATA <= x"E6"; when x"411" => DATA <= x"20"; when x"412" => DATA <= x"CB"; when x"413" => DATA <= x"E6"; when x"414" => DATA <= x"90"; when x"415" => DATA <= x"03"; when x"416" => DATA <= x"20"; when x"417" => DATA <= x"AD"; when x"418" => DATA <= x"E7"; when x"419" => DATA <= x"A5"; when x"41A" => DATA <= x"A0"; when x"41B" => DATA <= x"48"; when x"41C" => DATA <= x"A5"; when x"41D" => DATA <= x"A1"; when x"41E" => DATA <= x"48"; when x"41F" => DATA <= x"38"; when x"420" => DATA <= x"A5"; when x"421" => DATA <= x"A2"; when x"422" => DATA <= x"E5"; when x"423" => DATA <= x"A0"; when x"424" => DATA <= x"85"; when x"425" => DATA <= x"A0"; when x"426" => DATA <= x"A5"; when x"427" => DATA <= x"A3"; when x"428" => DATA <= x"E5"; when x"429" => DATA <= x"A1"; when x"42A" => DATA <= x"85"; when x"42B" => DATA <= x"A1"; when x"42C" => DATA <= x"A9"; when x"42D" => DATA <= x"00"; when x"42E" => DATA <= x"85"; when x"42F" => DATA <= x"A2"; when x"430" => DATA <= x"A9"; when x"431" => DATA <= x"02"; when x"432" => DATA <= x"85"; when x"433" => DATA <= x"A3"; when x"434" => DATA <= x"AC"; when x"435" => DATA <= x"05"; when x"436" => DATA <= x"21"; when x"437" => DATA <= x"F0"; when x"438" => DATA <= x"44"; when x"439" => DATA <= x"C0"; when x"43A" => DATA <= x"F8"; when x"43B" => DATA <= x"90"; when x"43C" => DATA <= x"09"; when x"43D" => DATA <= x"20"; when x"43E" => DATA <= x"D1"; when x"43F" => DATA <= x"F7"; when x"440" => DATA <= x"46"; when x"441" => DATA <= x"55"; when x"442" => DATA <= x"4C"; when x"443" => DATA <= x"4C"; when x"444" => DATA <= x"EA"; when x"445" => DATA <= x"00"; when x"446" => DATA <= x"20"; when x"447" => DATA <= x"DF"; when x"448" => DATA <= x"E4"; when x"449" => DATA <= x"4C"; when x"44A" => DATA <= x"52"; when x"44B" => DATA <= x"E4"; when x"44C" => DATA <= x"20"; when x"44D" => DATA <= x"15"; when x"44E" => DATA <= x"EE"; when x"44F" => DATA <= x"20"; when x"450" => DATA <= x"C0"; when x"451" => DATA <= x"E4"; when x"452" => DATA <= x"98"; when x"453" => DATA <= x"F0"; when x"454" => DATA <= x"02"; when x"455" => DATA <= x"90"; when x"456" => DATA <= x"F5"; when x"457" => DATA <= x"B0"; when x"458" => DATA <= x"0C"; when x"459" => DATA <= x"20"; when x"45A" => DATA <= x"D1"; when x"45B" => DATA <= x"F7"; when x"45C" => DATA <= x"4E"; when x"45D" => DATA <= x"4F"; when x"45E" => DATA <= x"20"; when x"45F" => DATA <= x"52"; when x"460" => DATA <= x"4F"; when x"461" => DATA <= x"4F"; when x"462" => DATA <= x"4D"; when x"463" => DATA <= x"EA"; when x"464" => DATA <= x"00"; when x"465" => DATA <= x"84"; when x"466" => DATA <= x"EA"; when x"467" => DATA <= x"AC"; when x"468" => DATA <= x"05"; when x"469" => DATA <= x"21"; when x"46A" => DATA <= x"C4"; when x"46B" => DATA <= x"EA"; when x"46C" => DATA <= x"F0"; when x"46D" => DATA <= x"0F"; when x"46E" => DATA <= x"B9"; when x"46F" => DATA <= x"07"; when x"470" => DATA <= x"20"; when x"471" => DATA <= x"99"; when x"472" => DATA <= x"0F"; when x"473" => DATA <= x"20"; when x"474" => DATA <= x"B9"; when x"475" => DATA <= x"07"; when x"476" => DATA <= x"21"; when x"477" => DATA <= x"99"; when x"478" => DATA <= x"0F"; when x"479" => DATA <= x"21"; when x"47A" => DATA <= x"88"; when x"47B" => DATA <= x"B0"; when x"47C" => DATA <= x"ED"; when x"47D" => DATA <= x"A2"; when x"47E" => DATA <= x"00"; when x"47F" => DATA <= x"B5"; when x"480" => DATA <= x"A5"; when x"481" => DATA <= x"99"; when x"482" => DATA <= x"08"; when x"483" => DATA <= x"20"; when x"484" => DATA <= x"C8"; when x"485" => DATA <= x"E8"; when x"486" => DATA <= x"E0"; when x"487" => DATA <= x"08"; when x"488" => DATA <= x"D0"; when x"489" => DATA <= x"F5"; when x"48A" => DATA <= x"B5"; when x"48B" => DATA <= x"9B"; when x"48C" => DATA <= x"88"; when x"48D" => DATA <= x"99"; when x"48E" => DATA <= x"08"; when x"48F" => DATA <= x"21"; when x"490" => DATA <= x"CA"; when x"491" => DATA <= x"D0"; when x"492" => DATA <= x"F7"; when x"493" => DATA <= x"20"; when x"494" => DATA <= x"FA"; when x"495" => DATA <= x"E6"; when x"496" => DATA <= x"68"; when x"497" => DATA <= x"85"; when x"498" => DATA <= x"9D"; when x"499" => DATA <= x"68"; when x"49A" => DATA <= x"85"; when x"49B" => DATA <= x"9C"; when x"49C" => DATA <= x"AC"; when x"49D" => DATA <= x"05"; when x"49E" => DATA <= x"21"; when x"49F" => DATA <= x"20"; when x"4A0" => DATA <= x"0C"; when x"4A1" => DATA <= x"EE"; when x"4A2" => DATA <= x"8C"; when x"4A3" => DATA <= x"05"; when x"4A4" => DATA <= x"21"; when x"4A5" => DATA <= x"20"; when x"4A6" => DATA <= x"7B"; when x"4A7" => DATA <= x"EC"; when x"4A8" => DATA <= x"A5"; when x"4A9" => DATA <= x"9C"; when x"4AA" => DATA <= x"85"; when x"4AB" => DATA <= x"F9"; when x"4AC" => DATA <= x"A5"; when x"4AD" => DATA <= x"9D"; when x"4AE" => DATA <= x"85"; when x"4AF" => DATA <= x"FA"; when x"4B0" => DATA <= x"A5"; when x"4B1" => DATA <= x"A1"; when x"4B2" => DATA <= x"85"; when x"4B3" => DATA <= x"FB"; when x"4B4" => DATA <= x"A5"; when x"4B5" => DATA <= x"A0"; when x"4B6" => DATA <= x"F0"; when x"4B7" => DATA <= x"02"; when x"4B8" => DATA <= x"E6"; when x"4B9" => DATA <= x"FB"; when x"4BA" => DATA <= x"20"; when x"4BB" => DATA <= x"F9"; when x"4BC" => DATA <= x"E4"; when x"4BD" => DATA <= x"4C"; when x"4BE" => DATA <= x"56"; when x"4BF" => DATA <= x"E3"; when x"4C0" => DATA <= x"B9"; when x"4C1" => DATA <= x"0E"; when x"4C2" => DATA <= x"21"; when x"4C3" => DATA <= x"20"; when x"4C4" => DATA <= x"1F"; when x"4C5" => DATA <= x"EE"; when x"4C6" => DATA <= x"85"; when x"4C7" => DATA <= x"A2"; when x"4C8" => DATA <= x"18"; when x"4C9" => DATA <= x"A9"; when x"4CA" => DATA <= x"FF"; when x"4CB" => DATA <= x"79"; when x"4CC" => DATA <= x"0C"; when x"4CD" => DATA <= x"21"; when x"4CE" => DATA <= x"B9"; when x"4CF" => DATA <= x"0F"; when x"4D0" => DATA <= x"21"; when x"4D1" => DATA <= x"79"; when x"4D2" => DATA <= x"0D"; when x"4D3" => DATA <= x"21"; when x"4D4" => DATA <= x"85"; when x"4D5" => DATA <= x"A3"; when x"4D6" => DATA <= x"B9"; when x"4D7" => DATA <= x"0E"; when x"4D8" => DATA <= x"21"; when x"4D9" => DATA <= x"29"; when x"4DA" => DATA <= x"0F"; when x"4DB" => DATA <= x"65"; when x"4DC" => DATA <= x"A2"; when x"4DD" => DATA <= x"85"; when x"4DE" => DATA <= x"A2"; when x"4DF" => DATA <= x"38"; when x"4E0" => DATA <= x"B9"; when x"4E1" => DATA <= x"07"; when x"4E2" => DATA <= x"21"; when x"4E3" => DATA <= x"E5"; when x"4E4" => DATA <= x"A3"; when x"4E5" => DATA <= x"48"; when x"4E6" => DATA <= x"B9"; when x"4E7" => DATA <= x"06"; when x"4E8" => DATA <= x"21"; when x"4E9" => DATA <= x"29"; when x"4EA" => DATA <= x"0F"; when x"4EB" => DATA <= x"E5"; when x"4EC" => DATA <= x"A2"; when x"4ED" => DATA <= x"AA"; when x"4EE" => DATA <= x"A9"; when x"4EF" => DATA <= x"00"; when x"4F0" => DATA <= x"C5"; when x"4F1" => DATA <= x"A0"; when x"4F2" => DATA <= x"68"; when x"4F3" => DATA <= x"E5"; when x"4F4" => DATA <= x"A1"; when x"4F5" => DATA <= x"8A"; when x"4F6" => DATA <= x"E9"; when x"4F7" => DATA <= x"00"; when x"4F8" => DATA <= x"60"; when x"4F9" => DATA <= x"20"; when x"4FA" => DATA <= x"8B"; when x"4FB" => DATA <= x"EC"; when x"4FC" => DATA <= x"24"; when x"4FD" => DATA <= x"FD"; when x"4FE" => DATA <= x"30"; when x"4FF" => DATA <= x"03"; when x"500" => DATA <= x"4C"; when x"501" => DATA <= x"16"; when x"502" => DATA <= x"E5"; when x"503" => DATA <= x"20"; when x"504" => DATA <= x"52"; when x"505" => DATA <= x"E5"; when x"506" => DATA <= x"C6"; when x"507" => DATA <= x"FA"; when x"508" => DATA <= x"20"; when x"509" => DATA <= x"B7"; when x"50A" => DATA <= x"EE"; when x"50B" => DATA <= x"20"; when x"50C" => DATA <= x"6E"; when x"50D" => DATA <= x"E5"; when x"50E" => DATA <= x"20"; when x"50F" => DATA <= x"65"; when x"510" => DATA <= x"E5"; when x"511" => DATA <= x"A2"; when x"512" => DATA <= x"01"; when x"513" => DATA <= x"4C"; when x"514" => DATA <= x"27"; when x"515" => DATA <= x"E5"; when x"516" => DATA <= x"A5"; when x"517" => DATA <= x"FB"; when x"518" => DATA <= x"C9"; when x"519" => DATA <= x"01"; when x"51A" => DATA <= x"D0"; when x"51B" => DATA <= x"06"; when x"51C" => DATA <= x"20"; when x"51D" => DATA <= x"52"; when x"51E" => DATA <= x"E5"; when x"51F" => DATA <= x"20"; when x"520" => DATA <= x"65"; when x"521" => DATA <= x"E5"; when x"522" => DATA <= x"20"; when x"523" => DATA <= x"B7"; when x"524" => DATA <= x"EE"; when x"525" => DATA <= x"A2"; when x"526" => DATA <= x"02"; when x"527" => DATA <= x"20"; when x"528" => DATA <= x"6E"; when x"529" => DATA <= x"E5"; when x"52A" => DATA <= x"E6"; when x"52B" => DATA <= x"FA"; when x"52C" => DATA <= x"C6"; when x"52D" => DATA <= x"FB"; when x"52E" => DATA <= x"F0"; when x"52F" => DATA <= x"13"; when x"530" => DATA <= x"CA"; when x"531" => DATA <= x"D0"; when x"532" => DATA <= x"F4"; when x"533" => DATA <= x"20"; when x"534" => DATA <= x"D7"; when x"535" => DATA <= x"EE"; when x"536" => DATA <= x"E6"; when x"537" => DATA <= x"84"; when x"538" => DATA <= x"D0"; when x"539" => DATA <= x"06"; when x"53A" => DATA <= x"E6"; when x"53B" => DATA <= x"85"; when x"53C" => DATA <= x"D0"; when x"53D" => DATA <= x"02"; when x"53E" => DATA <= x"E6"; when x"53F" => DATA <= x"86"; when x"540" => DATA <= x"4C"; when x"541" => DATA <= x"16"; when x"542" => DATA <= x"E5"; when x"543" => DATA <= x"E0"; when x"544" => DATA <= x"02"; when x"545" => DATA <= x"D0"; when x"546" => DATA <= x"08"; when x"547" => DATA <= x"20"; when x"548" => DATA <= x"EF"; when x"549" => DATA <= x"EB"; when x"54A" => DATA <= x"E6"; when x"54B" => DATA <= x"FA"; when x"54C" => DATA <= x"20"; when x"54D" => DATA <= x"6E"; when x"54E" => DATA <= x"E5"; when x"54F" => DATA <= x"4C"; when x"550" => DATA <= x"D7"; when x"551" => DATA <= x"EE"; when x"552" => DATA <= x"8A"; when x"553" => DATA <= x"48"; when x"554" => DATA <= x"A5"; when x"555" => DATA <= x"F9"; when x"556" => DATA <= x"85"; when x"557" => DATA <= x"FE"; when x"558" => DATA <= x"A5"; when x"559" => DATA <= x"FA"; when x"55A" => DATA <= x"85"; when x"55B" => DATA <= x"FF"; when x"55C" => DATA <= x"20"; when x"55D" => DATA <= x"EF"; when x"55E" => DATA <= x"EB"; when x"55F" => DATA <= x"20"; when x"560" => DATA <= x"71"; when x"561" => DATA <= x"EE"; when x"562" => DATA <= x"68"; when x"563" => DATA <= x"AA"; when x"564" => DATA <= x"60"; when x"565" => DATA <= x"A5"; when x"566" => DATA <= x"FF"; when x"567" => DATA <= x"85"; when x"568" => DATA <= x"FA"; when x"569" => DATA <= x"A5"; when x"56A" => DATA <= x"FE"; when x"56B" => DATA <= x"85"; when x"56C" => DATA <= x"F9"; when x"56D" => DATA <= x"60"; when x"56E" => DATA <= x"A0"; when x"56F" => DATA <= x"00"; when x"570" => DATA <= x"B1"; when x"571" => DATA <= x"F9"; when x"572" => DATA <= x"20"; when x"573" => DATA <= x"FD"; when x"574" => DATA <= x"EF"; when x"575" => DATA <= x"C8"; when x"576" => DATA <= x"D0"; when x"577" => DATA <= x"F8"; when x"578" => DATA <= x"60"; when x"579" => DATA <= x"A4"; when x"57A" => DATA <= x"03"; when x"57B" => DATA <= x"C8"; when x"57C" => DATA <= x"20"; when x"57D" => DATA <= x"76"; when x"57E" => DATA <= x"FA"; when x"57F" => DATA <= x"B9"; when x"580" => DATA <= x"FF"; when x"581" => DATA <= x"00"; when x"582" => DATA <= x"85"; when x"583" => DATA <= x"AC"; when x"584" => DATA <= x"85"; when x"585" => DATA <= x"AD"; when x"586" => DATA <= x"60"; when x"587" => DATA <= x"20"; when x"588" => DATA <= x"63"; when x"589" => DATA <= x"E7"; when x"58A" => DATA <= x"20"; when x"58B" => DATA <= x"2D"; when x"58C" => DATA <= x"EC"; when x"58D" => DATA <= x"A2"; when x"58E" => DATA <= x"FF"; when x"58F" => DATA <= x"E8"; when x"590" => DATA <= x"BD"; when x"591" => DATA <= x"40"; when x"592" => DATA <= x"01"; when x"593" => DATA <= x"C9"; when x"594" => DATA <= x"0D"; when x"595" => DATA <= x"D0"; when x"596" => DATA <= x"F8"; when x"597" => DATA <= x"E0"; when x"598" => DATA <= x"0E"; when x"599" => DATA <= x"B0"; when x"59A" => DATA <= x"03"; when x"59B" => DATA <= x"4C"; when x"59C" => DATA <= x"A8"; when x"59D" => DATA <= x"E5"; when x"59E" => DATA <= x"20"; when x"59F" => DATA <= x"D1"; when x"5A0" => DATA <= x"F7"; when x"5A1" => DATA <= x"4E"; when x"5A2" => DATA <= x"41"; when x"5A3" => DATA <= x"4D"; when x"5A4" => DATA <= x"45"; when x"5A5" => DATA <= x"3F"; when x"5A6" => DATA <= x"EA"; when x"5A7" => DATA <= x"00"; when x"5A8" => DATA <= x"A5"; when x"5A9" => DATA <= x"EE"; when x"5AA" => DATA <= x"20"; when x"5AB" => DATA <= x"AA"; when x"5AC" => DATA <= x"ED"; when x"5AD" => DATA <= x"20"; when x"5AE" => DATA <= x"16"; when x"5AF" => DATA <= x"EC"; when x"5B0" => DATA <= x"20"; when x"5B1" => DATA <= x"63"; when x"5B2" => DATA <= x"E6"; when x"5B3" => DATA <= x"A0"; when x"5B4" => DATA <= x"00"; when x"5B5" => DATA <= x"B9"; when x"5B6" => DATA <= x"40"; when x"5B7" => DATA <= x"01"; when x"5B8" => DATA <= x"C9"; when x"5B9" => DATA <= x"0D"; when x"5BA" => DATA <= x"F0"; when x"5BB" => DATA <= x"13"; when x"5BC" => DATA <= x"91"; when x"5BD" => DATA <= x"87"; when x"5BE" => DATA <= x"C0"; when x"5BF" => DATA <= x"08"; when x"5C0" => DATA <= x"B0"; when x"5C1" => DATA <= x"06"; when x"5C2" => DATA <= x"99"; when x"5C3" => DATA <= x"00"; when x"5C4" => DATA <= x"20"; when x"5C5" => DATA <= x"4C"; when x"5C6" => DATA <= x"CB"; when x"5C7" => DATA <= x"E5"; when x"5C8" => DATA <= x"99"; when x"5C9" => DATA <= x"F8"; when x"5CA" => DATA <= x"20"; when x"5CB" => DATA <= x"C8"; when x"5CC" => DATA <= x"4C"; when x"5CD" => DATA <= x"B5"; when x"5CE" => DATA <= x"E5"; when x"5CF" => DATA <= x"C0"; when x"5D0" => DATA <= x"0D"; when x"5D1" => DATA <= x"F0"; when x"5D2" => DATA <= x"15"; when x"5D3" => DATA <= x"A9"; when x"5D4" => DATA <= x"20"; when x"5D5" => DATA <= x"91"; when x"5D6" => DATA <= x"87"; when x"5D7" => DATA <= x"C0"; when x"5D8" => DATA <= x"08"; when x"5D9" => DATA <= x"B0"; when x"5DA" => DATA <= x"06"; when x"5DB" => DATA <= x"99"; when x"5DC" => DATA <= x"00"; when x"5DD" => DATA <= x"20"; when x"5DE" => DATA <= x"4C"; when x"5DF" => DATA <= x"E4"; when x"5E0" => DATA <= x"E5"; when x"5E1" => DATA <= x"99"; when x"5E2" => DATA <= x"F8"; when x"5E3" => DATA <= x"20"; when x"5E4" => DATA <= x"C8"; when x"5E5" => DATA <= x"4C"; when x"5E6" => DATA <= x"CF"; when x"5E7" => DATA <= x"E5"; when x"5E8" => DATA <= x"20"; when x"5E9" => DATA <= x"26"; when x"5EA" => DATA <= x"EC"; when x"5EB" => DATA <= x"20"; when x"5EC" => DATA <= x"7B"; when x"5ED" => DATA <= x"EC"; when x"5EE" => DATA <= x"4C"; when x"5EF" => DATA <= x"E0"; when x"5F0" => DATA <= x"EB"; when x"5F1" => DATA <= x"18"; when x"5F2" => DATA <= x"08"; when x"5F3" => DATA <= x"20"; when x"5F4" => DATA <= x"63"; when x"5F5" => DATA <= x"E7"; when x"5F6" => DATA <= x"20"; when x"5F7" => DATA <= x"91"; when x"5F8" => DATA <= x"E6"; when x"5F9" => DATA <= x"20"; when x"5FA" => DATA <= x"BC"; when x"5FB" => DATA <= x"E6"; when x"5FC" => DATA <= x"20"; when x"5FD" => DATA <= x"63"; when x"5FE" => DATA <= x"E6"; when x"5FF" => DATA <= x"A5"; when x"600" => DATA <= x"AC"; when x"601" => DATA <= x"2A"; when x"602" => DATA <= x"28"; when x"603" => DATA <= x"6A"; when x"604" => DATA <= x"99"; when x"605" => DATA <= x"0F"; when x"606" => DATA <= x"20"; when x"607" => DATA <= x"20"; when x"608" => DATA <= x"FA"; when x"609" => DATA <= x"E6"; when x"60A" => DATA <= x"20"; when x"60B" => DATA <= x"7B"; when x"60C" => DATA <= x"EC"; when x"60D" => DATA <= x"4C"; when x"60E" => DATA <= x"56"; when x"60F" => DATA <= x"E3"; when x"610" => DATA <= x"A5"; when x"611" => DATA <= x"AC"; when x"612" => DATA <= x"85"; when x"613" => DATA <= x"AD"; when x"614" => DATA <= x"A4"; when x"615" => DATA <= x"03"; when x"616" => DATA <= x"C8"; when x"617" => DATA <= x"20"; when x"618" => DATA <= x"76"; when x"619" => DATA <= x"FA"; when x"61A" => DATA <= x"B9"; when x"61B" => DATA <= x"FF"; when x"61C" => DATA <= x"00"; when x"61D" => DATA <= x"85"; when x"61E" => DATA <= x"AC"; when x"61F" => DATA <= x"60"; when x"620" => DATA <= x"20"; when x"621" => DATA <= x"63"; when x"622" => DATA <= x"E7"; when x"623" => DATA <= x"20"; when x"624" => DATA <= x"91"; when x"625" => DATA <= x"E6"; when x"626" => DATA <= x"20"; when x"627" => DATA <= x"51"; when x"628" => DATA <= x"E6"; when x"629" => DATA <= x"20"; when x"62A" => DATA <= x"CB"; when x"62B" => DATA <= x"E6"; when x"62C" => DATA <= x"B0"; when x"62D" => DATA <= x"03"; when x"62E" => DATA <= x"4C"; when x"62F" => DATA <= x"26"; when x"630" => DATA <= x"F9"; when x"631" => DATA <= x"A5"; when x"632" => DATA <= x"EE"; when x"633" => DATA <= x"85"; when x"634" => DATA <= x"C7"; when x"635" => DATA <= x"A5"; when x"636" => DATA <= x"AC"; when x"637" => DATA <= x"85"; when x"638" => DATA <= x"C8"; when x"639" => DATA <= x"A9"; when x"63A" => DATA <= x"20"; when x"63B" => DATA <= x"85"; when x"63C" => DATA <= x"AC"; when x"63D" => DATA <= x"A9"; when x"63E" => DATA <= x"00"; when x"63F" => DATA <= x"85"; when x"640" => DATA <= x"EE"; when x"641" => DATA <= x"85"; when x"642" => DATA <= x"9E"; when x"643" => DATA <= x"20"; when x"644" => DATA <= x"20"; when x"645" => DATA <= x"E3"; when x"646" => DATA <= x"A5"; when x"647" => DATA <= x"C7"; when x"648" => DATA <= x"85"; when x"649" => DATA <= x"EE"; when x"64A" => DATA <= x"A5"; when x"64B" => DATA <= x"C8"; when x"64C" => DATA <= x"85"; when x"64D" => DATA <= x"AC"; when x"64E" => DATA <= x"6C"; when x"64F" => DATA <= x"9E"; when x"650" => DATA <= x"00"; when x"651" => DATA <= x"20"; when x"652" => DATA <= x"76"; when x"653" => DATA <= x"F8"; when x"654" => DATA <= x"A2"; when x"655" => DATA <= x"00"; when x"656" => DATA <= x"B9"; when x"657" => DATA <= x"00"; when x"658" => DATA <= x"01"; when x"659" => DATA <= x"9D"; when x"65A" => DATA <= x"00"; when x"65B" => DATA <= x"01"; when x"65C" => DATA <= x"E8"; when x"65D" => DATA <= x"C8"; when x"65E" => DATA <= x"C9"; when x"65F" => DATA <= x"0D"; when x"660" => DATA <= x"D0"; when x"661" => DATA <= x"F4"; when x"662" => DATA <= x"60"; when x"663" => DATA <= x"A5"; when x"664" => DATA <= x"F8"; when x"665" => DATA <= x"4C"; when x"666" => DATA <= x"7E"; when x"667" => DATA <= x"E6"; when x"668" => DATA <= x"A0"; when x"669" => DATA <= x"0F"; when x"66A" => DATA <= x"B1"; when x"66B" => DATA <= x"87"; when x"66C" => DATA <= x"C9"; when x"66D" => DATA <= x"FF"; when x"66E" => DATA <= x"D0"; when x"66F" => DATA <= x"20"; when x"670" => DATA <= x"20"; when x"671" => DATA <= x"D1"; when x"672" => DATA <= x"F7"; when x"673" => DATA <= x"4E"; when x"674" => DATA <= x"4F"; when x"675" => DATA <= x"54"; when x"676" => DATA <= x"20"; when x"677" => DATA <= x"56"; when x"678" => DATA <= x"41"; when x"679" => DATA <= x"4C"; when x"67A" => DATA <= x"49"; when x"67B" => DATA <= x"44"; when x"67C" => DATA <= x"EA"; when x"67D" => DATA <= x"00"; when x"67E" => DATA <= x"C9"; when x"67F" => DATA <= x"00"; when x"680" => DATA <= x"D0"; when x"681" => DATA <= x"0E"; when x"682" => DATA <= x"20"; when x"683" => DATA <= x"D1"; when x"684" => DATA <= x"F7"; when x"685" => DATA <= x"44"; when x"686" => DATA <= x"49"; when x"687" => DATA <= x"53"; when x"688" => DATA <= x"4B"; when x"689" => DATA <= x"20"; when x"68A" => DATA <= x"50"; when x"68B" => DATA <= x"52"; when x"68C" => DATA <= x"4F"; when x"68D" => DATA <= x"54"; when x"68E" => DATA <= x"EA"; when x"68F" => DATA <= x"00"; when x"690" => DATA <= x"60"; when x"691" => DATA <= x"A0"; when x"692" => DATA <= x"00"; when x"693" => DATA <= x"B5"; when x"694" => DATA <= x"00"; when x"695" => DATA <= x"99"; when x"696" => DATA <= x"9A"; when x"697" => DATA <= x"00"; when x"698" => DATA <= x"E8"; when x"699" => DATA <= x"C8"; when x"69A" => DATA <= x"C0"; when x"69B" => DATA <= x"0A"; when x"69C" => DATA <= x"90"; when x"69D" => DATA <= x"F5"; when x"69E" => DATA <= x"A9"; when x"69F" => DATA <= x"20"; when x"6A0" => DATA <= x"A0"; when x"6A1" => DATA <= x"06"; when x"6A2" => DATA <= x"99"; when x"6A3" => DATA <= x"A5"; when x"6A4" => DATA <= x"00"; when x"6A5" => DATA <= x"88"; when x"6A6" => DATA <= x"10"; when x"6A7" => DATA <= x"FA"; when x"6A8" => DATA <= x"C8"; when x"6A9" => DATA <= x"B1"; when x"6AA" => DATA <= x"9A"; when x"6AB" => DATA <= x"C9"; when x"6AC" => DATA <= x"0D"; when x"6AD" => DATA <= x"F0"; when x"6AE" => DATA <= x"09"; when x"6AF" => DATA <= x"C0"; when x"6B0" => DATA <= x"07"; when x"6B1" => DATA <= x"B0"; when x"6B2" => DATA <= x"06"; when x"6B3" => DATA <= x"99"; when x"6B4" => DATA <= x"A5"; when x"6B5" => DATA <= x"00"; when x"6B6" => DATA <= x"D0"; when x"6B7" => DATA <= x"F0"; when x"6B8" => DATA <= x"60"; when x"6B9" => DATA <= x"4C"; when x"6BA" => DATA <= x"9E"; when x"6BB" => DATA <= x"E5"; when x"6BC" => DATA <= x"20"; when x"6BD" => DATA <= x"CB"; when x"6BE" => DATA <= x"E6"; when x"6BF" => DATA <= x"B0"; when x"6C0" => DATA <= x"F7"; when x"6C1" => DATA <= x"20"; when x"6C2" => DATA <= x"D1"; when x"6C3" => DATA <= x"F7"; when x"6C4" => DATA <= x"46"; when x"6C5" => DATA <= x"49"; when x"6C6" => DATA <= x"4C"; when x"6C7" => DATA <= x"45"; when x"6C8" => DATA <= x"3F"; when x"6C9" => DATA <= x"EA"; when x"6CA" => DATA <= x"00"; when x"6CB" => DATA <= x"20"; when x"6CC" => DATA <= x"2D"; when x"6CD" => DATA <= x"EC"; when x"6CE" => DATA <= x"A0"; when x"6CF" => DATA <= x"F8"; when x"6D0" => DATA <= x"20"; when x"6D1" => DATA <= x"0C"; when x"6D2" => DATA <= x"EE"; when x"6D3" => DATA <= x"CC"; when x"6D4" => DATA <= x"05"; when x"6D5" => DATA <= x"21"; when x"6D6" => DATA <= x"B0"; when x"6D7" => DATA <= x"20"; when x"6D8" => DATA <= x"B9"; when x"6D9" => DATA <= x"0F"; when x"6DA" => DATA <= x"20"; when x"6DB" => DATA <= x"29"; when x"6DC" => DATA <= x"7F"; when x"6DD" => DATA <= x"C5"; when x"6DE" => DATA <= x"AC"; when x"6DF" => DATA <= x"D0"; when x"6E0" => DATA <= x"EF"; when x"6E1" => DATA <= x"20"; when x"6E2" => DATA <= x"0D"; when x"6E3" => DATA <= x"EE"; when x"6E4" => DATA <= x"A2"; when x"6E5" => DATA <= x"06"; when x"6E6" => DATA <= x"B9"; when x"6E7" => DATA <= x"07"; when x"6E8" => DATA <= x"20"; when x"6E9" => DATA <= x"D5"; when x"6EA" => DATA <= x"A5"; when x"6EB" => DATA <= x"D0"; when x"6EC" => DATA <= x"05"; when x"6ED" => DATA <= x"88"; when x"6EE" => DATA <= x"CA"; when x"6EF" => DATA <= x"10"; when x"6F0" => DATA <= x"F5"; when x"6F1" => DATA <= x"60"; when x"6F2" => DATA <= x"88"; when x"6F3" => DATA <= x"CA"; when x"6F4" => DATA <= x"10"; when x"6F5" => DATA <= x"FC"; when x"6F6" => DATA <= x"30"; when x"6F7" => DATA <= x"D8"; when x"6F8" => DATA <= x"18"; when x"6F9" => DATA <= x"60"; when x"6FA" => DATA <= x"A5"; when x"6FB" => DATA <= x"EF"; when x"6FC" => DATA <= x"D0"; when x"6FD" => DATA <= x"64"; when x"6FE" => DATA <= x"B9"; when x"6FF" => DATA <= x"0F"; when x"700" => DATA <= x"20"; when x"701" => DATA <= x"29"; when x"702" => DATA <= x"7F"; when x"703" => DATA <= x"20"; when x"704" => DATA <= x"F4"; when x"705" => DATA <= x"FF"; when x"706" => DATA <= x"20"; when x"707" => DATA <= x"FD"; when x"708" => DATA <= x"F7"; when x"709" => DATA <= x"BE"; when x"70A" => DATA <= x"0F"; when x"70B" => DATA <= x"20"; when x"70C" => DATA <= x"10"; when x"70D" => DATA <= x"02"; when x"70E" => DATA <= x"A9"; when x"70F" => DATA <= x"23"; when x"710" => DATA <= x"20"; when x"711" => DATA <= x"F4"; when x"712" => DATA <= x"FF"; when x"713" => DATA <= x"A2"; when x"714" => DATA <= x"07"; when x"715" => DATA <= x"B9"; when x"716" => DATA <= x"08"; when x"717" => DATA <= x"20"; when x"718" => DATA <= x"20"; when x"719" => DATA <= x"F4"; when x"71A" => DATA <= x"FF"; when x"71B" => DATA <= x"C8"; when x"71C" => DATA <= x"CA"; when x"71D" => DATA <= x"D0"; when x"71E" => DATA <= x"F6"; when x"71F" => DATA <= x"20"; when x"720" => DATA <= x"FD"; when x"721" => DATA <= x"F7"; when x"722" => DATA <= x"B9"; when x"723" => DATA <= x"02"; when x"724" => DATA <= x"21"; when x"725" => DATA <= x"20"; when x"726" => DATA <= x"02"; when x"727" => DATA <= x"F8"; when x"728" => DATA <= x"B9"; when x"729" => DATA <= x"01"; when x"72A" => DATA <= x"21"; when x"72B" => DATA <= x"20"; when x"72C" => DATA <= x"02"; when x"72D" => DATA <= x"F8"; when x"72E" => DATA <= x"C8"; when x"72F" => DATA <= x"E8"; when x"730" => DATA <= x"C8"; when x"731" => DATA <= x"E0"; when x"732" => DATA <= x"02"; when x"733" => DATA <= x"90"; when x"734" => DATA <= x"EA"; when x"735" => DATA <= x"20"; when x"736" => DATA <= x"FD"; when x"737" => DATA <= x"F7"; when x"738" => DATA <= x"20"; when x"739" => DATA <= x"FD"; when x"73A" => DATA <= x"F7"; when x"73B" => DATA <= x"B9"; when x"73C" => DATA <= x"03"; when x"73D" => DATA <= x"21"; when x"73E" => DATA <= x"20"; when x"73F" => DATA <= x"1F"; when x"740" => DATA <= x"EE"; when x"741" => DATA <= x"20"; when x"742" => DATA <= x"0B"; when x"743" => DATA <= x"F8"; when x"744" => DATA <= x"B9"; when x"745" => DATA <= x"02"; when x"746" => DATA <= x"21"; when x"747" => DATA <= x"20"; when x"748" => DATA <= x"02"; when x"749" => DATA <= x"F8"; when x"74A" => DATA <= x"B9"; when x"74B" => DATA <= x"01"; when x"74C" => DATA <= x"21"; when x"74D" => DATA <= x"20"; when x"74E" => DATA <= x"02"; when x"74F" => DATA <= x"F8"; when x"750" => DATA <= x"20"; when x"751" => DATA <= x"FD"; when x"752" => DATA <= x"F7"; when x"753" => DATA <= x"B9"; when x"754" => DATA <= x"03"; when x"755" => DATA <= x"21"; when x"756" => DATA <= x"20"; when x"757" => DATA <= x"0B"; when x"758" => DATA <= x"F8"; when x"759" => DATA <= x"B9"; when x"75A" => DATA <= x"04"; when x"75B" => DATA <= x"21"; when x"75C" => DATA <= x"20"; when x"75D" => DATA <= x"02"; when x"75E" => DATA <= x"F8"; when x"75F" => DATA <= x"20"; when x"760" => DATA <= x"ED"; when x"761" => DATA <= x"FF"; when x"762" => DATA <= x"60"; when x"763" => DATA <= x"A2"; when x"764" => DATA <= x"00"; when x"765" => DATA <= x"A4"; when x"766" => DATA <= x"9A"; when x"767" => DATA <= x"20"; when x"768" => DATA <= x"76"; when x"769" => DATA <= x"F8"; when x"76A" => DATA <= x"C9"; when x"76B" => DATA <= x"22"; when x"76C" => DATA <= x"F0"; when x"76D" => DATA <= x"20"; when x"76E" => DATA <= x"C9"; when x"76F" => DATA <= x"0D"; when x"770" => DATA <= x"F0"; when x"771" => DATA <= x"0C"; when x"772" => DATA <= x"9D"; when x"773" => DATA <= x"40"; when x"774" => DATA <= x"01"; when x"775" => DATA <= x"E8"; when x"776" => DATA <= x"C8"; when x"777" => DATA <= x"B9"; when x"778" => DATA <= x"00"; when x"779" => DATA <= x"01"; when x"77A" => DATA <= x"C9"; when x"77B" => DATA <= x"20"; when x"77C" => DATA <= x"D0"; when x"77D" => DATA <= x"F0"; when x"77E" => DATA <= x"A9"; when x"77F" => DATA <= x"0D"; when x"780" => DATA <= x"9D"; when x"781" => DATA <= x"40"; when x"782" => DATA <= x"01"; when x"783" => DATA <= x"A9"; when x"784" => DATA <= x"40"; when x"785" => DATA <= x"85"; when x"786" => DATA <= x"9A"; when x"787" => DATA <= x"A9"; when x"788" => DATA <= x"01"; when x"789" => DATA <= x"85"; when x"78A" => DATA <= x"9B"; when x"78B" => DATA <= x"A2"; when x"78C" => DATA <= x"9A"; when x"78D" => DATA <= x"60"; when x"78E" => DATA <= x"C8"; when x"78F" => DATA <= x"B9"; when x"790" => DATA <= x"00"; when x"791" => DATA <= x"01"; when x"792" => DATA <= x"C9"; when x"793" => DATA <= x"0D"; when x"794" => DATA <= x"F0"; when x"795" => DATA <= x"14"; when x"796" => DATA <= x"9D"; when x"797" => DATA <= x"40"; when x"798" => DATA <= x"01"; when x"799" => DATA <= x"E8"; when x"79A" => DATA <= x"C9"; when x"79B" => DATA <= x"22"; when x"79C" => DATA <= x"D0"; when x"79D" => DATA <= x"F0"; when x"79E" => DATA <= x"CA"; when x"79F" => DATA <= x"C8"; when x"7A0" => DATA <= x"B9"; when x"7A1" => DATA <= x"00"; when x"7A2" => DATA <= x"01"; when x"7A3" => DATA <= x"C9"; when x"7A4" => DATA <= x"22"; when x"7A5" => DATA <= x"D0"; when x"7A6" => DATA <= x"D7"; when x"7A7" => DATA <= x"E8"; when x"7A8" => DATA <= x"B0"; when x"7A9" => DATA <= x"E4"; when x"7AA" => DATA <= x"4C"; when x"7AB" => DATA <= x"9E"; when x"7AC" => DATA <= x"E5"; when x"7AD" => DATA <= x"B9"; when x"7AE" => DATA <= x"0F"; when x"7AF" => DATA <= x"20"; when x"7B0" => DATA <= x"30"; when x"7B1" => DATA <= x"19"; when x"7B2" => DATA <= x"B9"; when x"7B3" => DATA <= x"10"; when x"7B4" => DATA <= x"20"; when x"7B5" => DATA <= x"99"; when x"7B6" => DATA <= x"08"; when x"7B7" => DATA <= x"20"; when x"7B8" => DATA <= x"B9"; when x"7B9" => DATA <= x"10"; when x"7BA" => DATA <= x"21"; when x"7BB" => DATA <= x"99"; when x"7BC" => DATA <= x"08"; when x"7BD" => DATA <= x"21"; when x"7BE" => DATA <= x"C8"; when x"7BF" => DATA <= x"CC"; when x"7C0" => DATA <= x"05"; when x"7C1" => DATA <= x"21"; when x"7C2" => DATA <= x"90"; when x"7C3" => DATA <= x"EE"; when x"7C4" => DATA <= x"98"; when x"7C5" => DATA <= x"E9"; when x"7C6" => DATA <= x"08"; when x"7C7" => DATA <= x"8D"; when x"7C8" => DATA <= x"05"; when x"7C9" => DATA <= x"21"; when x"7CA" => DATA <= x"60"; when x"7CB" => DATA <= x"4C"; when x"7CC" => DATA <= x"D0"; when x"7CD" => DATA <= x"E2"; when x"7CE" => DATA <= x"53"; when x"7CF" => DATA <= x"44"; when x"7D0" => DATA <= x"44"; when x"7D1" => DATA <= x"4F"; when x"7D2" => DATA <= x"53"; when x"7D3" => DATA <= x"20"; when x"7D4" => DATA <= x"20"; when x"7D5" => DATA <= x"20"; when x"7D6" => DATA <= x"20"; when x"7D7" => DATA <= x"24"; when x"7D8" => DATA <= x"EE"; when x"7D9" => DATA <= x"20"; when x"7DA" => DATA <= x"01"; when x"7DB" => DATA <= x"EC"; when x"7DC" => DATA <= x"A0"; when x"7DD" => DATA <= x"07"; when x"7DE" => DATA <= x"B9"; when x"7DF" => DATA <= x"08"; when x"7E0" => DATA <= x"23"; when x"7E1" => DATA <= x"D9"; when x"7E2" => DATA <= x"CE"; when x"7E3" => DATA <= x"E7"; when x"7E4" => DATA <= x"F0"; when x"7E5" => DATA <= x"0F"; when x"7E6" => DATA <= x"20"; when x"7E7" => DATA <= x"D1"; when x"7E8" => DATA <= x"F7"; when x"7E9" => DATA <= x"53"; when x"7EA" => DATA <= x"44"; when x"7EB" => DATA <= x"20"; when x"7EC" => DATA <= x"46"; when x"7ED" => DATA <= x"4F"; when x"7EE" => DATA <= x"52"; when x"7EF" => DATA <= x"4D"; when x"7F0" => DATA <= x"41"; when x"7F1" => DATA <= x"54"; when x"7F2" => DATA <= x"3F"; when x"7F3" => DATA <= x"EA"; when x"7F4" => DATA <= x"00"; when x"7F5" => DATA <= x"88"; when x"7F6" => DATA <= x"10"; when x"7F7" => DATA <= x"E6"; when x"7F8" => DATA <= x"A0"; when x"7F9" => DATA <= x"07"; when x"7FA" => DATA <= x"B9"; when x"7FB" => DATA <= x"00"; when x"7FC" => DATA <= x"23"; when x"7FD" => DATA <= x"99"; when x"7FE" => DATA <= x"F0"; when x"7FF" => DATA <= x"00"; when x"800" => DATA <= x"88"; when x"801" => DATA <= x"10"; when x"802" => DATA <= x"F7"; when x"803" => DATA <= x"A9"; when x"804" => DATA <= x"70"; when x"805" => DATA <= x"8D"; when x"806" => DATA <= x"06"; when x"807" => DATA <= x"02"; when x"808" => DATA <= x"A9"; when x"809" => DATA <= x"E0"; when x"80A" => DATA <= x"8D"; when x"80B" => DATA <= x"07"; when x"80C" => DATA <= x"02"; when x"80D" => DATA <= x"A2"; when x"80E" => DATA <= x"03"; when x"80F" => DATA <= x"BD"; when x"810" => DATA <= x"2D"; when x"811" => DATA <= x"E8"; when x"812" => DATA <= x"9D"; when x"813" => DATA <= x"0C"; when x"814" => DATA <= x"02"; when x"815" => DATA <= x"CA"; when x"816" => DATA <= x"10"; when x"817" => DATA <= x"F7"; when x"818" => DATA <= x"A9"; when x"819" => DATA <= x"20"; when x"81A" => DATA <= x"85"; when x"81B" => DATA <= x"AC"; when x"81C" => DATA <= x"85"; when x"81D" => DATA <= x"AD"; when x"81E" => DATA <= x"49"; when x"81F" => DATA <= x"20"; when x"820" => DATA <= x"85"; when x"821" => DATA <= x"EE"; when x"822" => DATA <= x"85"; when x"823" => DATA <= x"C0"; when x"824" => DATA <= x"85"; when x"825" => DATA <= x"B9"; when x"826" => DATA <= x"85"; when x"827" => DATA <= x"BA"; when x"828" => DATA <= x"A0"; when x"829" => DATA <= x"FF"; when x"82A" => DATA <= x"84"; when x"82B" => DATA <= x"EF"; when x"82C" => DATA <= x"60"; when x"82D" => DATA <= x"26"; when x"82E" => DATA <= x"E3"; when x"82F" => DATA <= x"08"; when x"830" => DATA <= x"E4"; when x"831" => DATA <= x"20"; when x"832" => DATA <= x"3E"; when x"833" => DATA <= x"ED"; when x"834" => DATA <= x"20"; when x"835" => DATA <= x"55"; when x"836" => DATA <= x"ED"; when x"837" => DATA <= x"20"; when x"838" => DATA <= x"F0"; when x"839" => DATA <= x"ED"; when x"83A" => DATA <= x"A2"; when x"83B" => DATA <= x"FF"; when x"83C" => DATA <= x"A5"; when x"83D" => DATA <= x"83"; when x"83E" => DATA <= x"C5"; when x"83F" => DATA <= x"F1"; when x"840" => DATA <= x"D0"; when x"841" => DATA <= x"0D"; when x"842" => DATA <= x"A5"; when x"843" => DATA <= x"82"; when x"844" => DATA <= x"C5"; when x"845" => DATA <= x"F0"; when x"846" => DATA <= x"D0"; when x"847" => DATA <= x"07"; when x"848" => DATA <= x"86"; when x"849" => DATA <= x"F0"; when x"84A" => DATA <= x"86"; when x"84B" => DATA <= x"F1"; when x"84C" => DATA <= x"4C"; when x"84D" => DATA <= x"85"; when x"84E" => DATA <= x"E8"; when x"84F" => DATA <= x"A5"; when x"850" => DATA <= x"83"; when x"851" => DATA <= x"C5"; when x"852" => DATA <= x"F3"; when x"853" => DATA <= x"D0"; when x"854" => DATA <= x"0D"; when x"855" => DATA <= x"A5"; when x"856" => DATA <= x"82"; when x"857" => DATA <= x"C5"; when x"858" => DATA <= x"F2"; when x"859" => DATA <= x"D0"; when x"85A" => DATA <= x"07"; when x"85B" => DATA <= x"86"; when x"85C" => DATA <= x"F2"; when x"85D" => DATA <= x"86"; when x"85E" => DATA <= x"F3"; when x"85F" => DATA <= x"4C"; when x"860" => DATA <= x"85"; when x"861" => DATA <= x"E8"; when x"862" => DATA <= x"A5"; when x"863" => DATA <= x"83"; when x"864" => DATA <= x"C5"; when x"865" => DATA <= x"F5"; when x"866" => DATA <= x"D0"; when x"867" => DATA <= x"0D"; when x"868" => DATA <= x"A5"; when x"869" => DATA <= x"82"; when x"86A" => DATA <= x"C5"; when x"86B" => DATA <= x"F4"; when x"86C" => DATA <= x"D0"; when x"86D" => DATA <= x"07"; when x"86E" => DATA <= x"86"; when x"86F" => DATA <= x"F4"; when x"870" => DATA <= x"86"; when x"871" => DATA <= x"F5"; when x"872" => DATA <= x"4C"; when x"873" => DATA <= x"85"; when x"874" => DATA <= x"E8"; when x"875" => DATA <= x"A5"; when x"876" => DATA <= x"83"; when x"877" => DATA <= x"C5"; when x"878" => DATA <= x"F7"; when x"879" => DATA <= x"D0"; when x"87A" => DATA <= x"0A"; when x"87B" => DATA <= x"A5"; when x"87C" => DATA <= x"82"; when x"87D" => DATA <= x"C5"; when x"87E" => DATA <= x"F6"; when x"87F" => DATA <= x"D0"; when x"880" => DATA <= x"04"; when x"881" => DATA <= x"86"; when x"882" => DATA <= x"F6"; when x"883" => DATA <= x"86"; when x"884" => DATA <= x"F7"; when x"885" => DATA <= x"A5"; when x"886" => DATA <= x"80"; when x"887" => DATA <= x"0A"; when x"888" => DATA <= x"AA"; when x"889" => DATA <= x"A5"; when x"88A" => DATA <= x"82"; when x"88B" => DATA <= x"95"; when x"88C" => DATA <= x"F0"; when x"88D" => DATA <= x"A5"; when x"88E" => DATA <= x"83"; when x"88F" => DATA <= x"95"; when x"890" => DATA <= x"F1"; when x"891" => DATA <= x"4C"; when x"892" => DATA <= x"E0"; when x"893" => DATA <= x"EB"; when x"894" => DATA <= x"20"; when x"895" => DATA <= x"55"; when x"896" => DATA <= x"ED"; when x"897" => DATA <= x"A5"; when x"898" => DATA <= x"82"; when x"899" => DATA <= x"85"; when x"89A" => DATA <= x"92"; when x"89B" => DATA <= x"A5"; when x"89C" => DATA <= x"83"; when x"89D" => DATA <= x"85"; when x"89E" => DATA <= x"93"; when x"89F" => DATA <= x"20"; when x"8A0" => DATA <= x"55"; when x"8A1" => DATA <= x"ED"; when x"8A2" => DATA <= x"A5"; when x"8A3" => DATA <= x"82"; when x"8A4" => DATA <= x"85"; when x"8A5" => DATA <= x"94"; when x"8A6" => DATA <= x"A5"; when x"8A7" => DATA <= x"83"; when x"8A8" => DATA <= x"85"; when x"8A9" => DATA <= x"95"; when x"8AA" => DATA <= x"20"; when x"8AB" => DATA <= x"76"; when x"8AC" => DATA <= x"F8"; when x"8AD" => DATA <= x"C9"; when x"8AE" => DATA <= x"0D"; when x"8AF" => DATA <= x"F0"; when x"8B0" => DATA <= x"19"; when x"8B1" => DATA <= x"A4"; when x"8B2" => DATA <= x"03"; when x"8B3" => DATA <= x"B1"; when x"8B4" => DATA <= x"05"; when x"8B5" => DATA <= x"C9"; when x"8B6" => DATA <= x"0D"; when x"8B7" => DATA <= x"F0"; when x"8B8" => DATA <= x"11"; when x"8B9" => DATA <= x"85"; when x"8BA" => DATA <= x"96"; when x"8BB" => DATA <= x"C8"; when x"8BC" => DATA <= x"B1"; when x"8BD" => DATA <= x"05"; when x"8BE" => DATA <= x"C9"; when x"8BF" => DATA <= x"0D"; when x"8C0" => DATA <= x"D0"; when x"8C1" => DATA <= x"71"; when x"8C2" => DATA <= x"84"; when x"8C3" => DATA <= x"03"; when x"8C4" => DATA <= x"20"; when x"8C5" => DATA <= x"31"; when x"8C6" => DATA <= x"C2"; when x"8C7" => DATA <= x"4C"; when x"8C8" => DATA <= x"CE"; when x"8C9" => DATA <= x"E8"; when x"8CA" => DATA <= x"A2"; when x"8CB" => DATA <= x"00"; when x"8CC" => DATA <= x"86"; when x"8CD" => DATA <= x"96"; when x"8CE" => DATA <= x"20"; when x"8CF" => DATA <= x"ED"; when x"8D0" => DATA <= x"FF"; when x"8D1" => DATA <= x"A9"; when x"8D2" => DATA <= x"00"; when x"8D3" => DATA <= x"85"; when x"8D4" => DATA <= x"90"; when x"8D5" => DATA <= x"85"; when x"8D6" => DATA <= x"91"; when x"8D7" => DATA <= x"A6"; when x"8D8" => DATA <= x"92"; when x"8D9" => DATA <= x"A4"; when x"8DA" => DATA <= x"93"; when x"8DB" => DATA <= x"20"; when x"8DC" => DATA <= x"0D"; when x"8DD" => DATA <= x"EC"; when x"8DE" => DATA <= x"A0"; when x"8DF" => DATA <= x"0F"; when x"8E0" => DATA <= x"B1"; when x"8E1" => DATA <= x"87"; when x"8E2" => DATA <= x"30"; when x"8E3" => DATA <= x"1C"; when x"8E4" => DATA <= x"A5"; when x"8E5" => DATA <= x"96"; when x"8E6" => DATA <= x"F0"; when x"8E7" => DATA <= x"08"; when x"8E8" => DATA <= x"A0"; when x"8E9" => DATA <= x"00"; when x"8EA" => DATA <= x"B1"; when x"8EB" => DATA <= x"87"; when x"8EC" => DATA <= x"C5"; when x"8ED" => DATA <= x"96"; when x"8EE" => DATA <= x"D0"; when x"8EF" => DATA <= x"10"; when x"8F0" => DATA <= x"A6"; when x"8F1" => DATA <= x"92"; when x"8F2" => DATA <= x"A4"; when x"8F3" => DATA <= x"93"; when x"8F4" => DATA <= x"20"; when x"8F5" => DATA <= x"B7"; when x"8F6" => DATA <= x"ED"; when x"8F7" => DATA <= x"20"; when x"8F8" => DATA <= x"ED"; when x"8F9" => DATA <= x"FF"; when x"8FA" => DATA <= x"E6"; when x"8FB" => DATA <= x"90"; when x"8FC" => DATA <= x"D0"; when x"8FD" => DATA <= x"02"; when x"8FE" => DATA <= x"E6"; when x"8FF" => DATA <= x"91"; when x"900" => DATA <= x"E6"; when x"901" => DATA <= x"92"; when x"902" => DATA <= x"D0"; when x"903" => DATA <= x"02"; when x"904" => DATA <= x"E6"; when x"905" => DATA <= x"93"; when x"906" => DATA <= x"A5"; when x"907" => DATA <= x"93"; when x"908" => DATA <= x"C5"; when x"909" => DATA <= x"95"; when x"90A" => DATA <= x"90"; when x"90B" => DATA <= x"CB"; when x"90C" => DATA <= x"D0"; when x"90D" => DATA <= x"08"; when x"90E" => DATA <= x"A5"; when x"90F" => DATA <= x"92"; when x"910" => DATA <= x"C5"; when x"911" => DATA <= x"94"; when x"912" => DATA <= x"90"; when x"913" => DATA <= x"C3"; when x"914" => DATA <= x"F0"; when x"915" => DATA <= x"C1"; when x"916" => DATA <= x"20"; when x"917" => DATA <= x"ED"; when x"918" => DATA <= x"FF"; when x"919" => DATA <= x"20"; when x"91A" => DATA <= x"D1"; when x"91B" => DATA <= x"F7"; when x"91C" => DATA <= x"44"; when x"91D" => DATA <= x"49"; when x"91E" => DATA <= x"53"; when x"91F" => DATA <= x"4B"; when x"920" => DATA <= x"53"; when x"921" => DATA <= x"20"; when x"922" => DATA <= x"46"; when x"923" => DATA <= x"4F"; when x"924" => DATA <= x"55"; when x"925" => DATA <= x"4E"; when x"926" => DATA <= x"44"; when x"927" => DATA <= x"3A"; when x"928" => DATA <= x"EA"; when x"929" => DATA <= x"A6"; when x"92A" => DATA <= x"90"; when x"92B" => DATA <= x"A4"; when x"92C" => DATA <= x"91"; when x"92D" => DATA <= x"20"; when x"92E" => DATA <= x"88"; when x"92F" => DATA <= x"ED"; when x"930" => DATA <= x"4C"; when x"931" => DATA <= x"ED"; when x"932" => DATA <= x"FF"; when x"933" => DATA <= x"20"; when x"934" => DATA <= x"D1"; when x"935" => DATA <= x"F7"; when x"936" => DATA <= x"46"; when x"937" => DATA <= x"49"; when x"938" => DATA <= x"4C"; when x"939" => DATA <= x"54"; when x"93A" => DATA <= x"45"; when x"93B" => DATA <= x"52"; when x"93C" => DATA <= x"3F"; when x"93D" => DATA <= x"EA"; when x"93E" => DATA <= x"00"; when x"93F" => DATA <= x"20"; when x"940" => DATA <= x"F0"; when x"941" => DATA <= x"ED"; when x"942" => DATA <= x"A2"; when x"943" => DATA <= x"00"; when x"944" => DATA <= x"86"; when x"945" => DATA <= x"80"; when x"946" => DATA <= x"A5"; when x"947" => DATA <= x"80"; when x"948" => DATA <= x"48"; when x"949" => DATA <= x"20"; when x"94A" => DATA <= x"0B"; when x"94B" => DATA <= x"F8"; when x"94C" => DATA <= x"A9"; when x"94D" => DATA <= x"3A"; when x"94E" => DATA <= x"20"; when x"94F" => DATA <= x"F4"; when x"950" => DATA <= x"FF"; when x"951" => DATA <= x"68"; when x"952" => DATA <= x"20"; when x"953" => DATA <= x"AA"; when x"954" => DATA <= x"ED"; when x"955" => DATA <= x"30"; when x"956" => DATA <= x"18"; when x"957" => DATA <= x"20"; when x"958" => DATA <= x"16"; when x"959" => DATA <= x"EC"; when x"95A" => DATA <= x"A0"; when x"95B" => DATA <= x"0F"; when x"95C" => DATA <= x"B1"; when x"95D" => DATA <= x"87"; when x"95E" => DATA <= x"C9"; when x"95F" => DATA <= x"FF"; when x"960" => DATA <= x"F0"; when x"961" => DATA <= x"0D"; when x"962" => DATA <= x"A6"; when x"963" => DATA <= x"82"; when x"964" => DATA <= x"A4"; when x"965" => DATA <= x"83"; when x"966" => DATA <= x"20"; when x"967" => DATA <= x"B7"; when x"968" => DATA <= x"ED"; when x"969" => DATA <= x"20"; when x"96A" => DATA <= x"ED"; when x"96B" => DATA <= x"FF"; when x"96C" => DATA <= x"4C"; when x"96D" => DATA <= x"7A"; when x"96E" => DATA <= x"E9"; when x"96F" => DATA <= x"20"; when x"970" => DATA <= x"D1"; when x"971" => DATA <= x"F7"; when x"972" => DATA <= x"20"; when x"973" => DATA <= x"20"; when x"974" => DATA <= x"20"; when x"975" => DATA <= x"2D"; when x"976" => DATA <= x"EA"; when x"977" => DATA <= x"20"; when x"978" => DATA <= x"ED"; when x"979" => DATA <= x"FF"; when x"97A" => DATA <= x"E6"; when x"97B" => DATA <= x"80"; when x"97C" => DATA <= x"A5"; when x"97D" => DATA <= x"80"; when x"97E" => DATA <= x"C9"; when x"97F" => DATA <= x"04"; when x"980" => DATA <= x"D0"; when x"981" => DATA <= x"C4"; when x"982" => DATA <= x"4C"; when x"983" => DATA <= x"ED"; when x"984" => DATA <= x"FF"; when x"985" => DATA <= x"20"; when x"986" => DATA <= x"55"; when x"987" => DATA <= x"ED"; when x"988" => DATA <= x"20"; when x"989" => DATA <= x"F0"; when x"98A" => DATA <= x"ED"; when x"98B" => DATA <= x"20"; when x"98C" => DATA <= x"16"; when x"98D" => DATA <= x"EC"; when x"98E" => DATA <= x"20"; when x"98F" => DATA <= x"68"; when x"990" => DATA <= x"E6"; when x"991" => DATA <= x"A0"; when x"992" => DATA <= x"0F"; when x"993" => DATA <= x"A9"; when x"994" => DATA <= x"00"; when x"995" => DATA <= x"91"; when x"996" => DATA <= x"87"; when x"997" => DATA <= x"20"; when x"998" => DATA <= x"26"; when x"999" => DATA <= x"EC"; when x"99A" => DATA <= x"4C"; when x"99B" => DATA <= x"E0"; when x"99C" => DATA <= x"EB"; when x"99D" => DATA <= x"20"; when x"99E" => DATA <= x"55"; when x"99F" => DATA <= x"ED"; when x"9A0" => DATA <= x"20"; when x"9A1" => DATA <= x"F0"; when x"9A2" => DATA <= x"ED"; when x"9A3" => DATA <= x"20"; when x"9A4" => DATA <= x"16"; when x"9A5" => DATA <= x"EC"; when x"9A6" => DATA <= x"20"; when x"9A7" => DATA <= x"68"; when x"9A8" => DATA <= x"E6"; when x"9A9" => DATA <= x"A0"; when x"9AA" => DATA <= x"0F"; when x"9AB" => DATA <= x"A9"; when x"9AC" => DATA <= x"0F"; when x"9AD" => DATA <= x"91"; when x"9AE" => DATA <= x"87"; when x"9AF" => DATA <= x"20"; when x"9B0" => DATA <= x"26"; when x"9B1" => DATA <= x"EC"; when x"9B2" => DATA <= x"4C"; when x"9B3" => DATA <= x"E0"; when x"9B4" => DATA <= x"EB"; when x"9B5" => DATA <= x"20"; when x"9B6" => DATA <= x"F0"; when x"9B7" => DATA <= x"ED"; when x"9B8" => DATA <= x"A9"; when x"9B9" => DATA <= x"00"; when x"9BA" => DATA <= x"85"; when x"9BB" => DATA <= x"90"; when x"9BC" => DATA <= x"85"; when x"9BD" => DATA <= x"91"; when x"9BE" => DATA <= x"85"; when x"9BF" => DATA <= x"92"; when x"9C0" => DATA <= x"85"; when x"9C1" => DATA <= x"93"; when x"9C2" => DATA <= x"85"; when x"9C3" => DATA <= x"94"; when x"9C4" => DATA <= x"85"; when x"9C5" => DATA <= x"95"; when x"9C6" => DATA <= x"A6"; when x"9C7" => DATA <= x"94"; when x"9C8" => DATA <= x"A4"; when x"9C9" => DATA <= x"95"; when x"9CA" => DATA <= x"20"; when x"9CB" => DATA <= x"0D"; when x"9CC" => DATA <= x"EC"; when x"9CD" => DATA <= x"A0"; when x"9CE" => DATA <= x"0F"; when x"9CF" => DATA <= x"B1"; when x"9D0" => DATA <= x"87"; when x"9D1" => DATA <= x"C9"; when x"9D2" => DATA <= x"FF"; when x"9D3" => DATA <= x"F0"; when x"9D4" => DATA <= x"10"; when x"9D5" => DATA <= x"E6"; when x"9D6" => DATA <= x"90"; when x"9D7" => DATA <= x"D0"; when x"9D8" => DATA <= x"02"; when x"9D9" => DATA <= x"E6"; when x"9DA" => DATA <= x"91"; when x"9DB" => DATA <= x"29"; when x"9DC" => DATA <= x"F0"; when x"9DD" => DATA <= x"F0"; when x"9DE" => DATA <= x"06"; when x"9DF" => DATA <= x"E6"; when x"9E0" => DATA <= x"92"; when x"9E1" => DATA <= x"D0"; when x"9E2" => DATA <= x"02"; when x"9E3" => DATA <= x"E6"; when x"9E4" => DATA <= x"93"; when x"9E5" => DATA <= x"E6"; when x"9E6" => DATA <= x"94"; when x"9E7" => DATA <= x"D0"; when x"9E8" => DATA <= x"02"; when x"9E9" => DATA <= x"E6"; when x"9EA" => DATA <= x"95"; when x"9EB" => DATA <= x"A5"; when x"9EC" => DATA <= x"95"; when x"9ED" => DATA <= x"C9"; when x"9EE" => DATA <= x"03"; when x"9EF" => DATA <= x"90"; when x"9F0" => DATA <= x"D5"; when x"9F1" => DATA <= x"D0"; when x"9F2" => DATA <= x"08"; when x"9F3" => DATA <= x"A5"; when x"9F4" => DATA <= x"94"; when x"9F5" => DATA <= x"C9"; when x"9F6" => DATA <= x"FE"; when x"9F7" => DATA <= x"90"; when x"9F8" => DATA <= x"CD"; when x"9F9" => DATA <= x"F0"; when x"9FA" => DATA <= x"CB"; when x"9FB" => DATA <= x"A6"; when x"9FC" => DATA <= x"92"; when x"9FD" => DATA <= x"A4"; when x"9FE" => DATA <= x"93"; when x"9FF" => DATA <= x"20"; when x"A00" => DATA <= x"88"; when x"A01" => DATA <= x"ED"; when x"A02" => DATA <= x"20"; when x"A03" => DATA <= x"D1"; when x"A04" => DATA <= x"F7"; when x"A05" => DATA <= x"20"; when x"A06" => DATA <= x"4F"; when x"A07" => DATA <= x"46"; when x"A08" => DATA <= x"20"; when x"A09" => DATA <= x"EA"; when x"A0A" => DATA <= x"A6"; when x"A0B" => DATA <= x"90"; when x"A0C" => DATA <= x"A4"; when x"A0D" => DATA <= x"91"; when x"A0E" => DATA <= x"20"; when x"A0F" => DATA <= x"88"; when x"A10" => DATA <= x"ED"; when x"A11" => DATA <= x"20"; when x"A12" => DATA <= x"D1"; when x"A13" => DATA <= x"F7"; when x"A14" => DATA <= x"20"; when x"A15" => DATA <= x"44"; when x"A16" => DATA <= x"49"; when x"A17" => DATA <= x"53"; when x"A18" => DATA <= x"4B"; when x"A19" => DATA <= x"53"; when x"A1A" => DATA <= x"20"; when x"A1B" => DATA <= x"46"; when x"A1C" => DATA <= x"52"; when x"A1D" => DATA <= x"45"; when x"A1E" => DATA <= x"45"; when x"A1F" => DATA <= x"EA"; when x"A20" => DATA <= x"4C"; when x"A21" => DATA <= x"ED"; when x"A22" => DATA <= x"FF"; when x"A23" => DATA <= x"20"; when x"A24" => DATA <= x"55"; when x"A25" => DATA <= x"ED"; when x"A26" => DATA <= x"20"; when x"A27" => DATA <= x"F0"; when x"A28" => DATA <= x"ED"; when x"A29" => DATA <= x"20"; when x"A2A" => DATA <= x"16"; when x"A2B" => DATA <= x"EC"; when x"A2C" => DATA <= x"20"; when x"A2D" => DATA <= x"68"; when x"A2E" => DATA <= x"E6"; when x"A2F" => DATA <= x"20"; when x"A30" => DATA <= x"7E"; when x"A31" => DATA <= x"E6"; when x"A32" => DATA <= x"20"; when x"A33" => DATA <= x"D1"; when x"A34" => DATA <= x"F7"; when x"A35" => DATA <= x"4B"; when x"A36" => DATA <= x"49"; when x"A37" => DATA <= x"4C"; when x"A38" => DATA <= x"4C"; when x"A39" => DATA <= x"20"; when x"A3A" => DATA <= x"44"; when x"A3B" => DATA <= x"49"; when x"A3C" => DATA <= x"53"; when x"A3D" => DATA <= x"4B"; when x"A3E" => DATA <= x"3A"; when x"A3F" => DATA <= x"EA"; when x"A40" => DATA <= x"20"; when x"A41" => DATA <= x"A3"; when x"A42" => DATA <= x"ED"; when x"A43" => DATA <= x"20"; when x"A44" => DATA <= x"F5"; when x"A45" => DATA <= x"ED"; when x"A46" => DATA <= x"48"; when x"A47" => DATA <= x"20"; when x"A48" => DATA <= x"F4"; when x"A49" => DATA <= x"FF"; when x"A4A" => DATA <= x"68"; when x"A4B" => DATA <= x"C9"; when x"A4C" => DATA <= x"59"; when x"A4D" => DATA <= x"F0"; when x"A4E" => DATA <= x"03"; when x"A4F" => DATA <= x"4C"; when x"A50" => DATA <= x"ED"; when x"A51" => DATA <= x"FF"; when x"A52" => DATA <= x"20"; when x"A53" => DATA <= x"ED"; when x"A54" => DATA <= x"FF"; when x"A55" => DATA <= x"A0"; when x"A56" => DATA <= x"0F"; when x"A57" => DATA <= x"A9"; when x"A58" => DATA <= x"F0"; when x"A59" => DATA <= x"91"; when x"A5A" => DATA <= x"87"; when x"A5B" => DATA <= x"20"; when x"A5C" => DATA <= x"26"; when x"A5D" => DATA <= x"EC"; when x"A5E" => DATA <= x"4C"; when x"A5F" => DATA <= x"E0"; when x"A60" => DATA <= x"EB"; when x"A61" => DATA <= x"20"; when x"A62" => DATA <= x"55"; when x"A63" => DATA <= x"ED"; when x"A64" => DATA <= x"20"; when x"A65" => DATA <= x"F0"; when x"A66" => DATA <= x"ED"; when x"A67" => DATA <= x"20"; when x"A68" => DATA <= x"16"; when x"A69" => DATA <= x"EC"; when x"A6A" => DATA <= x"A0"; when x"A6B" => DATA <= x"0F"; when x"A6C" => DATA <= x"A9"; when x"A6D" => DATA <= x"0F"; when x"A6E" => DATA <= x"91"; when x"A6F" => DATA <= x"87"; when x"A70" => DATA <= x"20"; when x"A71" => DATA <= x"26"; when x"A72" => DATA <= x"EC"; when x"A73" => DATA <= x"4C"; when x"A74" => DATA <= x"E0"; when x"A75" => DATA <= x"EB"; when x"A76" => DATA <= x"20"; when x"A77" => DATA <= x"E0"; when x"A78" => DATA <= x"E2"; when x"A79" => DATA <= x"20"; when x"A7A" => DATA <= x"F0"; when x"A7B" => DATA <= x"ED"; when x"A7C" => DATA <= x"A9"; when x"A7D" => DATA <= x"00"; when x"A7E" => DATA <= x"85"; when x"A7F" => DATA <= x"90"; when x"A80" => DATA <= x"85"; when x"A81" => DATA <= x"91"; when x"A82" => DATA <= x"A6"; when x"A83" => DATA <= x"90"; when x"A84" => DATA <= x"A4"; when x"A85" => DATA <= x"91"; when x"A86" => DATA <= x"20"; when x"A87" => DATA <= x"0D"; when x"A88" => DATA <= x"EC"; when x"A89" => DATA <= x"A0"; when x"A8A" => DATA <= x"0F"; when x"A8B" => DATA <= x"B1"; when x"A8C" => DATA <= x"87"; when x"A8D" => DATA <= x"C9"; when x"A8E" => DATA <= x"F0"; when x"A8F" => DATA <= x"F0"; when x"A90" => DATA <= x"2A"; when x"A91" => DATA <= x"E6"; when x"A92" => DATA <= x"90"; when x"A93" => DATA <= x"D0"; when x"A94" => DATA <= x"02"; when x"A95" => DATA <= x"E6"; when x"A96" => DATA <= x"91"; when x"A97" => DATA <= x"A5"; when x"A98" => DATA <= x"91"; when x"A99" => DATA <= x"C9"; when x"A9A" => DATA <= x"03"; when x"A9B" => DATA <= x"90"; when x"A9C" => DATA <= x"E5"; when x"A9D" => DATA <= x"D0"; when x"A9E" => DATA <= x"08"; when x"A9F" => DATA <= x"A5"; when x"AA0" => DATA <= x"90"; when x"AA1" => DATA <= x"C9"; when x"AA2" => DATA <= x"FE"; when x"AA3" => DATA <= x"90"; when x"AA4" => DATA <= x"DD"; when x"AA5" => DATA <= x"F0"; when x"AA6" => DATA <= x"DB"; when x"AA7" => DATA <= x"20"; when x"AA8" => DATA <= x"D1"; when x"AA9" => DATA <= x"F7"; when x"AAA" => DATA <= x"4E"; when x"AAB" => DATA <= x"4F"; when x"AAC" => DATA <= x"20"; when x"AAD" => DATA <= x"44"; when x"AAE" => DATA <= x"49"; when x"AAF" => DATA <= x"53"; when x"AB0" => DATA <= x"4B"; when x"AB1" => DATA <= x"20"; when x"AB2" => DATA <= x"46"; when x"AB3" => DATA <= x"4F"; when x"AB4" => DATA <= x"55"; when x"AB5" => DATA <= x"4E"; when x"AB6" => DATA <= x"44"; when x"AB7" => DATA <= x"EA"; when x"AB8" => DATA <= x"4C"; when x"AB9" => DATA <= x"EB"; when x"ABA" => DATA <= x"EA"; when x"ABB" => DATA <= x"A5"; when x"ABC" => DATA <= x"90"; when x"ABD" => DATA <= x"85"; when x"ABE" => DATA <= x"82"; when x"ABF" => DATA <= x"A5"; when x"AC0" => DATA <= x"91"; when x"AC1" => DATA <= x"85"; when x"AC2" => DATA <= x"83"; when x"AC3" => DATA <= x"A5"; when x"AC4" => DATA <= x"EE"; when x"AC5" => DATA <= x"85"; when x"AC6" => DATA <= x"80"; when x"AC7" => DATA <= x"A9"; when x"AC8" => DATA <= x"00"; when x"AC9" => DATA <= x"20"; when x"ACA" => DATA <= x"3A"; when x"ACB" => DATA <= x"E8"; when x"ACC" => DATA <= x"20"; when x"ACD" => DATA <= x"D1"; when x"ACE" => DATA <= x"F7"; when x"ACF" => DATA <= x"44"; when x"AD0" => DATA <= x"49"; when x"AD1" => DATA <= x"53"; when x"AD2" => DATA <= x"4B"; when x"AD3" => DATA <= x"20"; when x"AD4" => DATA <= x"EA"; when x"AD5" => DATA <= x"20"; when x"AD6" => DATA <= x"A3"; when x"AD7" => DATA <= x"ED"; when x"AD8" => DATA <= x"20"; when x"AD9" => DATA <= x"D1"; when x"ADA" => DATA <= x"F7"; when x"ADB" => DATA <= x"20"; when x"ADC" => DATA <= x"49"; when x"ADD" => DATA <= x"4E"; when x"ADE" => DATA <= x"20"; when x"ADF" => DATA <= x"44"; when x"AE0" => DATA <= x"52"; when x"AE1" => DATA <= x"49"; when x"AE2" => DATA <= x"56"; when x"AE3" => DATA <= x"45"; when x"AE4" => DATA <= x"20"; when x"AE5" => DATA <= x"EA"; when x"AE6" => DATA <= x"A5"; when x"AE7" => DATA <= x"EE"; when x"AE8" => DATA <= x"20"; when x"AE9" => DATA <= x"0B"; when x"AEA" => DATA <= x"F8"; when x"AEB" => DATA <= x"4C"; when x"AEC" => DATA <= x"ED"; when x"AED" => DATA <= x"FF"; when x"AEE" => DATA <= x"20"; when x"AEF" => DATA <= x"55"; when x"AF0" => DATA <= x"ED"; when x"AF1" => DATA <= x"20"; when x"AF2" => DATA <= x"F0"; when x"AF3" => DATA <= x"ED"; when x"AF4" => DATA <= x"20"; when x"AF5" => DATA <= x"16"; when x"AF6" => DATA <= x"EC"; when x"AF7" => DATA <= x"20"; when x"AF8" => DATA <= x"68"; when x"AF9" => DATA <= x"E6"; when x"AFA" => DATA <= x"20"; when x"AFB" => DATA <= x"7E"; when x"AFC" => DATA <= x"E6"; when x"AFD" => DATA <= x"20"; when x"AFE" => DATA <= x"D1"; when x"AFF" => DATA <= x"F7"; when x"B00" => DATA <= x"46"; when x"B01" => DATA <= x"4F"; when x"B02" => DATA <= x"52"; when x"B03" => DATA <= x"4D"; when x"B04" => DATA <= x"41"; when x"B05" => DATA <= x"54"; when x"B06" => DATA <= x"20"; when x"B07" => DATA <= x"44"; when x"B08" => DATA <= x"49"; when x"B09" => DATA <= x"53"; when x"B0A" => DATA <= x"4B"; when x"B0B" => DATA <= x"3A"; when x"B0C" => DATA <= x"EA"; when x"B0D" => DATA <= x"20"; when x"B0E" => DATA <= x"A3"; when x"B0F" => DATA <= x"ED"; when x"B10" => DATA <= x"20"; when x"B11" => DATA <= x"F5"; when x"B12" => DATA <= x"ED"; when x"B13" => DATA <= x"48"; when x"B14" => DATA <= x"20"; when x"B15" => DATA <= x"F4"; when x"B16" => DATA <= x"FF"; when x"B17" => DATA <= x"68"; when x"B18" => DATA <= x"C9"; when x"B19" => DATA <= x"59"; when x"B1A" => DATA <= x"F0"; when x"B1B" => DATA <= x"03"; when x"B1C" => DATA <= x"4C"; when x"B1D" => DATA <= x"ED"; when x"B1E" => DATA <= x"FF"; when x"B1F" => DATA <= x"20"; when x"B20" => DATA <= x"67"; when x"B21" => DATA <= x"EA"; when x"B22" => DATA <= x"20"; when x"B23" => DATA <= x"ED"; when x"B24" => DATA <= x"FF"; when x"B25" => DATA <= x"A9"; when x"B26" => DATA <= x"20"; when x"B27" => DATA <= x"A2"; when x"B28" => DATA <= x"00"; when x"B29" => DATA <= x"9D"; when x"B2A" => DATA <= x"00"; when x"B2B" => DATA <= x"20"; when x"B2C" => DATA <= x"9D"; when x"B2D" => DATA <= x"00"; when x"B2E" => DATA <= x"21"; when x"B2F" => DATA <= x"E8"; when x"B30" => DATA <= x"D0"; when x"B31" => DATA <= x"F7"; when x"B32" => DATA <= x"A9"; when x"B33" => DATA <= x"00"; when x"B34" => DATA <= x"8D"; when x"B35" => DATA <= x"05"; when x"B36" => DATA <= x"21"; when x"B37" => DATA <= x"A9"; when x"B38" => DATA <= x"01"; when x"B39" => DATA <= x"8D"; when x"B3A" => DATA <= x"06"; when x"B3B" => DATA <= x"21"; when x"B3C" => DATA <= x"A9"; when x"B3D" => DATA <= x"90"; when x"B3E" => DATA <= x"8D"; when x"B3F" => DATA <= x"07"; when x"B40" => DATA <= x"21"; when x"B41" => DATA <= x"20"; when x"B42" => DATA <= x"7B"; when x"B43" => DATA <= x"EC"; when x"B44" => DATA <= x"A0"; when x"B45" => DATA <= x"00"; when x"B46" => DATA <= x"A2"; when x"B47" => DATA <= x"00"; when x"B48" => DATA <= x"BD"; when x"B49" => DATA <= x"00"; when x"B4A" => DATA <= x"20"; when x"B4B" => DATA <= x"91"; when x"B4C" => DATA <= x"87"; when x"B4D" => DATA <= x"C8"; when x"B4E" => DATA <= x"E8"; when x"B4F" => DATA <= x"E0"; when x"B50" => DATA <= x"08"; when x"B51" => DATA <= x"D0"; when x"B52" => DATA <= x"F5"; when x"B53" => DATA <= x"BD"; when x"B54" => DATA <= x"F8"; when x"B55" => DATA <= x"20"; when x"B56" => DATA <= x"91"; when x"B57" => DATA <= x"87"; when x"B58" => DATA <= x"C8"; when x"B59" => DATA <= x"E8"; when x"B5A" => DATA <= x"E0"; when x"B5B" => DATA <= x"0D"; when x"B5C" => DATA <= x"D0"; when x"B5D" => DATA <= x"F5"; when x"B5E" => DATA <= x"20"; when x"B5F" => DATA <= x"26"; when x"B60" => DATA <= x"EC"; when x"B61" => DATA <= x"4C"; when x"B62" => DATA <= x"E0"; when x"B63" => DATA <= x"EB"; when x"B64" => DATA <= x"20"; when x"B65" => DATA <= x"3E"; when x"B66" => DATA <= x"ED"; when x"B67" => DATA <= x"20"; when x"B68" => DATA <= x"55"; when x"B69" => DATA <= x"ED"; when x"B6A" => DATA <= x"20"; when x"B6B" => DATA <= x"F0"; when x"B6C" => DATA <= x"ED"; when x"B6D" => DATA <= x"20"; when x"B6E" => DATA <= x"01"; when x"B6F" => DATA <= x"EC"; when x"B70" => DATA <= x"A5"; when x"B71" => DATA <= x"80"; when x"B72" => DATA <= x"0A"; when x"B73" => DATA <= x"A8"; when x"B74" => DATA <= x"A5"; when x"B75" => DATA <= x"82"; when x"B76" => DATA <= x"99"; when x"B77" => DATA <= x"00"; when x"B78" => DATA <= x"23"; when x"B79" => DATA <= x"A5"; when x"B7A" => DATA <= x"83"; when x"B7B" => DATA <= x"99"; when x"B7C" => DATA <= x"01"; when x"B7D" => DATA <= x"23"; when x"B7E" => DATA <= x"4C"; when x"B7F" => DATA <= x"07"; when x"B80" => DATA <= x"EC"; when x"B81" => DATA <= x"20"; when x"B82" => DATA <= x"F0"; when x"B83" => DATA <= x"ED"; when x"B84" => DATA <= x"20"; when x"B85" => DATA <= x"ED"; when x"B86" => DATA <= x"FF"; when x"B87" => DATA <= x"20"; when x"B88" => DATA <= x"D1"; when x"B89" => DATA <= x"F7"; when x"B8A" => DATA <= x"53"; when x"B8B" => DATA <= x"44"; when x"B8C" => DATA <= x"44"; when x"B8D" => DATA <= x"4F"; when x"B8E" => DATA <= x"53"; when x"B8F" => DATA <= x"20"; when x"B90" => DATA <= x"56"; when x"B91" => DATA <= x"32"; when x"B92" => DATA <= x"2E"; when x"B93" => DATA <= x"33"; when x"B94" => DATA <= x"45"; when x"B95" => DATA <= x"EA"; when x"B96" => DATA <= x"20"; when x"B97" => DATA <= x"ED"; when x"B98" => DATA <= x"FF"; when x"B99" => DATA <= x"20"; when x"B9A" => DATA <= x"ED"; when x"B9B" => DATA <= x"FF"; when x"B9C" => DATA <= x"A0"; when x"B9D" => DATA <= x"00"; when x"B9E" => DATA <= x"A2"; when x"B9F" => DATA <= x"0F"; when x"BA0" => DATA <= x"B9"; when x"BA1" => DATA <= x"30"; when x"BA2" => DATA <= x"E1"; when x"BA3" => DATA <= x"30"; when x"BA4" => DATA <= x"08"; when x"BA5" => DATA <= x"20"; when x"BA6" => DATA <= x"F4"; when x"BA7" => DATA <= x"FF"; when x"BA8" => DATA <= x"C8"; when x"BA9" => DATA <= x"CA"; when x"BAA" => DATA <= x"4C"; when x"BAB" => DATA <= x"A0"; when x"BAC" => DATA <= x"EB"; when x"BAD" => DATA <= x"E0"; when x"BAE" => DATA <= x"04"; when x"BAF" => DATA <= x"F0"; when x"BB0" => DATA <= x"08"; when x"BB1" => DATA <= x"A9"; when x"BB2" => DATA <= x"20"; when x"BB3" => DATA <= x"20"; when x"BB4" => DATA <= x"F4"; when x"BB5" => DATA <= x"FF"; when x"BB6" => DATA <= x"CA"; when x"BB7" => DATA <= x"D0"; when x"BB8" => DATA <= x"F4"; when x"BB9" => DATA <= x"B9"; when x"BBA" => DATA <= x"30"; when x"BBB" => DATA <= x"E1"; when x"BBC" => DATA <= x"20"; when x"BBD" => DATA <= x"02"; when x"BBE" => DATA <= x"F8"; when x"BBF" => DATA <= x"B9"; when x"BC0" => DATA <= x"31"; when x"BC1" => DATA <= x"E1"; when x"BC2" => DATA <= x"20"; when x"BC3" => DATA <= x"02"; when x"BC4" => DATA <= x"F8"; when x"BC5" => DATA <= x"A9"; when x"BC6" => DATA <= x"20"; when x"BC7" => DATA <= x"20"; when x"BC8" => DATA <= x"F4"; when x"BC9" => DATA <= x"FF"; when x"BCA" => DATA <= x"C8"; when x"BCB" => DATA <= x"C8"; when x"BCC" => DATA <= x"B9"; when x"BCD" => DATA <= x"30"; when x"BCE" => DATA <= x"E1"; when x"BCF" => DATA <= x"C9"; when x"BD0" => DATA <= x"E6"; when x"BD1" => DATA <= x"D0"; when x"BD2" => DATA <= x"07"; when x"BD3" => DATA <= x"B9"; when x"BD4" => DATA <= x"31"; when x"BD5" => DATA <= x"E1"; when x"BD6" => DATA <= x"C9"; when x"BD7" => DATA <= x"20"; when x"BD8" => DATA <= x"F0"; when x"BD9" => DATA <= x"03"; when x"BDA" => DATA <= x"4C"; when x"BDB" => DATA <= x"9E"; when x"BDC" => DATA <= x"EB"; when x"BDD" => DATA <= x"4C"; when x"BDE" => DATA <= x"ED"; when x"BDF" => DATA <= x"FF"; when x"BE0" => DATA <= x"A5"; when x"BE1" => DATA <= x"EE"; when x"BE2" => DATA <= x"29"; when x"BE3" => DATA <= x"03"; when x"BE4" => DATA <= x"85"; when x"BE5" => DATA <= x"EE"; when x"BE6" => DATA <= x"60"; when x"BE7" => DATA <= x"A9"; when x"BE8" => DATA <= x"00"; when x"BE9" => DATA <= x"85"; when x"BEA" => DATA <= x"84"; when x"BEB" => DATA <= x"85"; when x"BEC" => DATA <= x"85"; when x"BED" => DATA <= x"85"; when x"BEE" => DATA <= x"86"; when x"BEF" => DATA <= x"A9"; when x"BF0" => DATA <= x"00"; when x"BF1" => DATA <= x"85"; when x"BF2" => DATA <= x"F9"; when x"BF3" => DATA <= x"A9"; when x"BF4" => DATA <= x"23"; when x"BF5" => DATA <= x"85"; when x"BF6" => DATA <= x"FA"; when x"BF7" => DATA <= x"60"; when x"BF8" => DATA <= x"A9"; when x"BF9" => DATA <= x"00"; when x"BFA" => DATA <= x"85"; when x"BFB" => DATA <= x"F9"; when x"BFC" => DATA <= x"A9"; when x"BFD" => DATA <= x"20"; when x"BFE" => DATA <= x"85"; when x"BFF" => DATA <= x"FA"; when x"C00" => DATA <= x"60"; when x"C01" => DATA <= x"20"; when x"C02" => DATA <= x"E7"; when x"C03" => DATA <= x"EB"; when x"C04" => DATA <= x"4C"; when x"C05" => DATA <= x"71"; when x"C06" => DATA <= x"EE"; when x"C07" => DATA <= x"20"; when x"C08" => DATA <= x"E7"; when x"C09" => DATA <= x"EB"; when x"C0A" => DATA <= x"4C"; when x"C0B" => DATA <= x"88"; when x"C0C" => DATA <= x"EE"; when x"C0D" => DATA <= x"20"; when x"C0E" => DATA <= x"B4"; when x"C0F" => DATA <= x"EC"; when x"C10" => DATA <= x"20"; when x"C11" => DATA <= x"EF"; when x"C12" => DATA <= x"EB"; when x"C13" => DATA <= x"4C"; when x"C14" => DATA <= x"71"; when x"C15" => DATA <= x"EE"; when x"C16" => DATA <= x"A6"; when x"C17" => DATA <= x"82"; when x"C18" => DATA <= x"A4"; when x"C19" => DATA <= x"83"; when x"C1A" => DATA <= x"4C"; when x"C1B" => DATA <= x"0D"; when x"C1C" => DATA <= x"EC"; when x"C1D" => DATA <= x"20"; when x"C1E" => DATA <= x"B4"; when x"C1F" => DATA <= x"EC"; when x"C20" => DATA <= x"20"; when x"C21" => DATA <= x"EF"; when x"C22" => DATA <= x"EB"; when x"C23" => DATA <= x"4C"; when x"C24" => DATA <= x"88"; when x"C25" => DATA <= x"EE"; when x"C26" => DATA <= x"A6"; when x"C27" => DATA <= x"82"; when x"C28" => DATA <= x"A4"; when x"C29" => DATA <= x"83"; when x"C2A" => DATA <= x"4C"; when x"C2B" => DATA <= x"1D"; when x"C2C" => DATA <= x"EC"; when x"C2D" => DATA <= x"A5"; when x"C2E" => DATA <= x"EE"; when x"C2F" => DATA <= x"29"; when x"C30" => DATA <= x"80"; when x"C31" => DATA <= x"F0"; when x"C32" => DATA <= x"03"; when x"C33" => DATA <= x"4C"; when x"C34" => DATA <= x"78"; when x"C35" => DATA <= x"EC"; when x"C36" => DATA <= x"A5"; when x"C37" => DATA <= x"EE"; when x"C38" => DATA <= x"20"; when x"C39" => DATA <= x"AA"; when x"C3A" => DATA <= x"ED"; when x"C3B" => DATA <= x"10"; when x"C3C" => DATA <= x"0C"; when x"C3D" => DATA <= x"20"; when x"C3E" => DATA <= x"D1"; when x"C3F" => DATA <= x"F7"; when x"C40" => DATA <= x"4E"; when x"C41" => DATA <= x"4F"; when x"C42" => DATA <= x"20"; when x"C43" => DATA <= x"44"; when x"C44" => DATA <= x"49"; when x"C45" => DATA <= x"53"; when x"C46" => DATA <= x"4B"; when x"C47" => DATA <= x"EA"; when x"C48" => DATA <= x"00"; when x"C49" => DATA <= x"20"; when x"C4A" => DATA <= x"16"; when x"C4B" => DATA <= x"EC"; when x"C4C" => DATA <= x"A0"; when x"C4D" => DATA <= x"0F"; when x"C4E" => DATA <= x"B1"; when x"C4F" => DATA <= x"87"; when x"C50" => DATA <= x"85"; when x"C51" => DATA <= x"F8"; when x"C52" => DATA <= x"C9"; when x"C53" => DATA <= x"F0"; when x"C54" => DATA <= x"D0"; when x"C55" => DATA <= x"10"; when x"C56" => DATA <= x"20"; when x"C57" => DATA <= x"D1"; when x"C58" => DATA <= x"F7"; when x"C59" => DATA <= x"55"; when x"C5A" => DATA <= x"4E"; when x"C5B" => DATA <= x"46"; when x"C5C" => DATA <= x"4F"; when x"C5D" => DATA <= x"52"; when x"C5E" => DATA <= x"4D"; when x"C5F" => DATA <= x"41"; when x"C60" => DATA <= x"54"; when x"C61" => DATA <= x"54"; when x"C62" => DATA <= x"45"; when x"C63" => DATA <= x"44"; when x"C64" => DATA <= x"EA"; when x"C65" => DATA <= x"00"; when x"C66" => DATA <= x"20"; when x"C67" => DATA <= x"6C"; when x"C68" => DATA <= x"E6"; when x"C69" => DATA <= x"20"; when x"C6A" => DATA <= x"E3"; when x"C6B" => DATA <= x"EC"; when x"C6C" => DATA <= x"20"; when x"C6D" => DATA <= x"F8"; when x"C6E" => DATA <= x"EB"; when x"C6F" => DATA <= x"20"; when x"C70" => DATA <= x"71"; when x"C71" => DATA <= x"EE"; when x"C72" => DATA <= x"A5"; when x"C73" => DATA <= x"EE"; when x"C74" => DATA <= x"09"; when x"C75" => DATA <= x"80"; when x"C76" => DATA <= x"85"; when x"C77" => DATA <= x"EE"; when x"C78" => DATA <= x"A5"; when x"C79" => DATA <= x"F8"; when x"C7A" => DATA <= x"60"; when x"C7B" => DATA <= x"20"; when x"C7C" => DATA <= x"E3"; when x"C7D" => DATA <= x"EC"; when x"C7E" => DATA <= x"20"; when x"C7F" => DATA <= x"F8"; when x"C80" => DATA <= x"EB"; when x"C81" => DATA <= x"20"; when x"C82" => DATA <= x"88"; when x"C83" => DATA <= x"EE"; when x"C84" => DATA <= x"A5"; when x"C85" => DATA <= x"EE"; when x"C86" => DATA <= x"09"; when x"C87" => DATA <= x"80"; when x"C88" => DATA <= x"85"; when x"C89" => DATA <= x"EE"; when x"C8A" => DATA <= x"60"; when x"C8B" => DATA <= x"A5"; when x"C8C" => DATA <= x"EE"; when x"C8D" => DATA <= x"20"; when x"C8E" => DATA <= x"AA"; when x"C8F" => DATA <= x"ED"; when x"C90" => DATA <= x"20"; when x"C91" => DATA <= x"E3"; when x"C92" => DATA <= x"EC"; when x"C93" => DATA <= x"A5"; when x"C94" => DATA <= x"A3"; when x"C95" => DATA <= x"4A"; when x"C96" => DATA <= x"66"; when x"C97" => DATA <= x"FD"; when x"C98" => DATA <= x"18"; when x"C99" => DATA <= x"65"; when x"C9A" => DATA <= x"84"; when x"C9B" => DATA <= x"85"; when x"C9C" => DATA <= x"84"; when x"C9D" => DATA <= x"A5"; when x"C9E" => DATA <= x"A2"; when x"C9F" => DATA <= x"29"; when x"CA0" => DATA <= x"0F"; when x"CA1" => DATA <= x"F0"; when x"CA2" => DATA <= x"04"; when x"CA3" => DATA <= x"69"; when x"CA4" => DATA <= x"80"; when x"CA5" => DATA <= x"85"; when x"CA6" => DATA <= x"84"; when x"CA7" => DATA <= x"A5"; when x"CA8" => DATA <= x"85"; when x"CA9" => DATA <= x"69"; when x"CAA" => DATA <= x"00"; when x"CAB" => DATA <= x"85"; when x"CAC" => DATA <= x"85"; when x"CAD" => DATA <= x"A5"; when x"CAE" => DATA <= x"86"; when x"CAF" => DATA <= x"69"; when x"CB0" => DATA <= x"00"; when x"CB1" => DATA <= x"85"; when x"CB2" => DATA <= x"86"; when x"CB3" => DATA <= x"60"; when x"CB4" => DATA <= x"E8"; when x"CB5" => DATA <= x"86"; when x"CB6" => DATA <= x"84"; when x"CB7" => DATA <= x"D0"; when x"CB8" => DATA <= x"01"; when x"CB9" => DATA <= x"C8"; when x"CBA" => DATA <= x"84"; when x"CBB" => DATA <= x"85"; when x"CBC" => DATA <= x"A9"; when x"CBD" => DATA <= x"00"; when x"CBE" => DATA <= x"85"; when x"CBF" => DATA <= x"86"; when x"CC0" => DATA <= x"85"; when x"CC1" => DATA <= x"87"; when x"CC2" => DATA <= x"85"; when x"CC3" => DATA <= x"88"; when x"CC4" => DATA <= x"A2"; when x"CC5" => DATA <= x"04"; when x"CC6" => DATA <= x"46"; when x"CC7" => DATA <= x"85"; when x"CC8" => DATA <= x"66"; when x"CC9" => DATA <= x"84"; when x"CCA" => DATA <= x"66"; when x"CCB" => DATA <= x"87"; when x"CCC" => DATA <= x"CA"; when x"CCD" => DATA <= x"D0"; when x"CCE" => DATA <= x"F7"; when x"CCF" => DATA <= x"46"; when x"CD0" => DATA <= x"85"; when x"CD1" => DATA <= x"66"; when x"CD2" => DATA <= x"84"; when x"CD3" => DATA <= x"26"; when x"CD4" => DATA <= x"88"; when x"CD5" => DATA <= x"18"; when x"CD6" => DATA <= x"A5"; when x"CD7" => DATA <= x"87"; when x"CD8" => DATA <= x"69"; when x"CD9" => DATA <= x"00"; when x"CDA" => DATA <= x"85"; when x"CDB" => DATA <= x"87"; when x"CDC" => DATA <= x"A5"; when x"CDD" => DATA <= x"88"; when x"CDE" => DATA <= x"69"; when x"CDF" => DATA <= x"23"; when x"CE0" => DATA <= x"85"; when x"CE1" => DATA <= x"88"; when x"CE2" => DATA <= x"60"; when x"CE3" => DATA <= x"A9"; when x"CE4" => DATA <= x"00"; when x"CE5" => DATA <= x"85"; when x"CE6" => DATA <= x"84"; when x"CE7" => DATA <= x"85"; when x"CE8" => DATA <= x"85"; when x"CE9" => DATA <= x"85"; when x"CEA" => DATA <= x"86"; when x"CEB" => DATA <= x"85"; when x"CEC" => DATA <= x"8B"; when x"CED" => DATA <= x"A5"; when x"CEE" => DATA <= x"83"; when x"CEF" => DATA <= x"85"; when x"CF0" => DATA <= x"8A"; when x"CF1" => DATA <= x"A5"; when x"CF2" => DATA <= x"82"; when x"CF3" => DATA <= x"85"; when x"CF4" => DATA <= x"89"; when x"CF5" => DATA <= x"20"; when x"CF6" => DATA <= x"1A"; when x"CF7" => DATA <= x"ED"; when x"CF8" => DATA <= x"20"; when x"CF9" => DATA <= x"2A"; when x"CFA" => DATA <= x"ED"; when x"CFB" => DATA <= x"20"; when x"CFC" => DATA <= x"1A"; when x"CFD" => DATA <= x"ED"; when x"CFE" => DATA <= x"20"; when x"CFF" => DATA <= x"2A"; when x"D00" => DATA <= x"ED"; when x"D01" => DATA <= x"20"; when x"D02" => DATA <= x"23"; when x"D03" => DATA <= x"ED"; when x"D04" => DATA <= x"20"; when x"D05" => DATA <= x"2A"; when x"D06" => DATA <= x"ED"; when x"D07" => DATA <= x"18"; when x"D08" => DATA <= x"A9"; when x"D09" => DATA <= x"20"; when x"D0A" => DATA <= x"65"; when x"D0B" => DATA <= x"84"; when x"D0C" => DATA <= x"85"; when x"D0D" => DATA <= x"84"; when x"D0E" => DATA <= x"A9"; when x"D0F" => DATA <= x"00"; when x"D10" => DATA <= x"65"; when x"D11" => DATA <= x"85"; when x"D12" => DATA <= x"85"; when x"D13" => DATA <= x"85"; when x"D14" => DATA <= x"A9"; when x"D15" => DATA <= x"00"; when x"D16" => DATA <= x"65"; when x"D17" => DATA <= x"86"; when x"D18" => DATA <= x"85"; when x"D19" => DATA <= x"86"; when x"D1A" => DATA <= x"A2"; when x"D1B" => DATA <= x"03"; when x"D1C" => DATA <= x"20"; when x"D1D" => DATA <= x"23"; when x"D1E" => DATA <= x"ED"; when x"D1F" => DATA <= x"CA"; when x"D20" => DATA <= x"D0"; when x"D21" => DATA <= x"FA"; when x"D22" => DATA <= x"60"; when x"D23" => DATA <= x"06"; when x"D24" => DATA <= x"89"; when x"D25" => DATA <= x"26"; when x"D26" => DATA <= x"8A"; when x"D27" => DATA <= x"26"; when x"D28" => DATA <= x"8B"; when x"D29" => DATA <= x"60"; when x"D2A" => DATA <= x"18"; when x"D2B" => DATA <= x"A5"; when x"D2C" => DATA <= x"89"; when x"D2D" => DATA <= x"65"; when x"D2E" => DATA <= x"84"; when x"D2F" => DATA <= x"85"; when x"D30" => DATA <= x"84"; when x"D31" => DATA <= x"A5"; when x"D32" => DATA <= x"8A"; when x"D33" => DATA <= x"65"; when x"D34" => DATA <= x"85"; when x"D35" => DATA <= x"85"; when x"D36" => DATA <= x"85"; when x"D37" => DATA <= x"A5"; when x"D38" => DATA <= x"8B"; when x"D39" => DATA <= x"65"; when x"D3A" => DATA <= x"86"; when x"D3B" => DATA <= x"85"; when x"D3C" => DATA <= x"86"; when x"D3D" => DATA <= x"60"; when x"D3E" => DATA <= x"20"; when x"D3F" => DATA <= x"77"; when x"D40" => DATA <= x"ED"; when x"D41" => DATA <= x"85"; when x"D42" => DATA <= x"80"; when x"D43" => DATA <= x"C9"; when x"D44" => DATA <= x"04"; when x"D45" => DATA <= x"B0"; when x"D46" => DATA <= x"03"; when x"D47" => DATA <= x"A5"; when x"D48" => DATA <= x"80"; when x"D49" => DATA <= x"60"; when x"D4A" => DATA <= x"20"; when x"D4B" => DATA <= x"D1"; when x"D4C" => DATA <= x"F7"; when x"D4D" => DATA <= x"44"; when x"D4E" => DATA <= x"52"; when x"D4F" => DATA <= x"49"; when x"D50" => DATA <= x"56"; when x"D51" => DATA <= x"45"; when x"D52" => DATA <= x"3F"; when x"D53" => DATA <= x"EA"; when x"D54" => DATA <= x"00"; when x"D55" => DATA <= x"20"; when x"D56" => DATA <= x"77"; when x"D57" => DATA <= x"ED"; when x"D58" => DATA <= x"85"; when x"D59" => DATA <= x"82"; when x"D5A" => DATA <= x"86"; when x"D5B" => DATA <= x"83"; when x"D5C" => DATA <= x"A5"; when x"D5D" => DATA <= x"83"; when x"D5E" => DATA <= x"C9"; when x"D5F" => DATA <= x"03"; when x"D60" => DATA <= x"90"; when x"D61" => DATA <= x"0A"; when x"D62" => DATA <= x"D0"; when x"D63" => DATA <= x"09"; when x"D64" => DATA <= x"A5"; when x"D65" => DATA <= x"82"; when x"D66" => DATA <= x"C9"; when x"D67" => DATA <= x"FE"; when x"D68" => DATA <= x"90"; when x"D69" => DATA <= x"02"; when x"D6A" => DATA <= x"D0"; when x"D6B" => DATA <= x"01"; when x"D6C" => DATA <= x"60"; when x"D6D" => DATA <= x"20"; when x"D6E" => DATA <= x"D1"; when x"D6F" => DATA <= x"F7"; when x"D70" => DATA <= x"44"; when x"D71" => DATA <= x"49"; when x"D72" => DATA <= x"53"; when x"D73" => DATA <= x"4B"; when x"D74" => DATA <= x"3F"; when x"D75" => DATA <= x"EA"; when x"D76" => DATA <= x"00"; when x"D77" => DATA <= x"20"; when x"D78" => DATA <= x"BC"; when x"D79" => DATA <= x"C8"; when x"D7A" => DATA <= x"20"; when x"D7B" => DATA <= x"31"; when x"D7C" => DATA <= x"C2"; when x"D7D" => DATA <= x"A0"; when x"D7E" => DATA <= x"00"; when x"D7F" => DATA <= x"84"; when x"D80" => DATA <= x"04"; when x"D81" => DATA <= x"A5"; when x"D82" => DATA <= x"16"; when x"D83" => DATA <= x"A6"; when x"D84" => DATA <= x"25"; when x"D85" => DATA <= x"A4"; when x"D86" => DATA <= x"34"; when x"D87" => DATA <= x"60"; when x"D88" => DATA <= x"AD"; when x"D89" => DATA <= x"21"; when x"D8A" => DATA <= x"03"; when x"D8B" => DATA <= x"48"; when x"D8C" => DATA <= x"A9"; when x"D8D" => DATA <= x"05"; when x"D8E" => DATA <= x"8D"; when x"D8F" => DATA <= x"21"; when x"D90" => DATA <= x"03"; when x"D91" => DATA <= x"86"; when x"D92" => DATA <= x"16"; when x"D93" => DATA <= x"84"; when x"D94" => DATA <= x"25"; when x"D95" => DATA <= x"A9"; when x"D96" => DATA <= x"00"; when x"D97" => DATA <= x"85"; when x"D98" => DATA <= x"34"; when x"D99" => DATA <= x"85"; when x"D9A" => DATA <= x"43"; when x"D9B" => DATA <= x"20"; when x"D9C" => DATA <= x"89"; when x"D9D" => DATA <= x"C5"; when x"D9E" => DATA <= x"68"; when x"D9F" => DATA <= x"8D"; when x"DA0" => DATA <= x"21"; when x"DA1" => DATA <= x"03"; when x"DA2" => DATA <= x"60"; when x"DA3" => DATA <= x"A6"; when x"DA4" => DATA <= x"82"; when x"DA5" => DATA <= x"A4"; when x"DA6" => DATA <= x"83"; when x"DA7" => DATA <= x"4C"; when x"DA8" => DATA <= x"88"; when x"DA9" => DATA <= x"ED"; when x"DAA" => DATA <= x"0A"; when x"DAB" => DATA <= x"A8"; when x"DAC" => DATA <= x"B9"; when x"DAD" => DATA <= x"F0"; when x"DAE" => DATA <= x"00"; when x"DAF" => DATA <= x"85"; when x"DB0" => DATA <= x"82"; when x"DB1" => DATA <= x"B9"; when x"DB2" => DATA <= x"F1"; when x"DB3" => DATA <= x"00"; when x"DB4" => DATA <= x"85"; when x"DB5" => DATA <= x"83"; when x"DB6" => DATA <= x"60"; when x"DB7" => DATA <= x"20"; when x"DB8" => DATA <= x"88"; when x"DB9" => DATA <= x"ED"; when x"DBA" => DATA <= x"A9"; when x"DBB" => DATA <= x"20"; when x"DBC" => DATA <= x"20"; when x"DBD" => DATA <= x"F4"; when x"DBE" => DATA <= x"FF"; when x"DBF" => DATA <= x"A0"; when x"DC0" => DATA <= x"00"; when x"DC1" => DATA <= x"B1"; when x"DC2" => DATA <= x"87"; when x"DC3" => DATA <= x"C9"; when x"DC4" => DATA <= x"20"; when x"DC5" => DATA <= x"10"; when x"DC6" => DATA <= x"02"; when x"DC7" => DATA <= x"A9"; when x"DC8" => DATA <= x"20"; when x"DC9" => DATA <= x"20"; when x"DCA" => DATA <= x"F4"; when x"DCB" => DATA <= x"FF"; when x"DCC" => DATA <= x"C8"; when x"DCD" => DATA <= x"C0"; when x"DCE" => DATA <= x"0D"; when x"DCF" => DATA <= x"D0"; when x"DD0" => DATA <= x"F0"; when x"DD1" => DATA <= x"A9"; when x"DD2" => DATA <= x"20"; when x"DD3" => DATA <= x"20"; when x"DD4" => DATA <= x"F4"; when x"DD5" => DATA <= x"FF"; when x"DD6" => DATA <= x"A0"; when x"DD7" => DATA <= x"0F"; when x"DD8" => DATA <= x"B1"; when x"DD9" => DATA <= x"87"; when x"DDA" => DATA <= x"29"; when x"DDB" => DATA <= x"0F"; when x"DDC" => DATA <= x"D0"; when x"DDD" => DATA <= x"05"; when x"DDE" => DATA <= x"A9"; when x"DDF" => DATA <= x"50"; when x"DE0" => DATA <= x"20"; when x"DE1" => DATA <= x"F4"; when x"DE2" => DATA <= x"FF"; when x"DE3" => DATA <= x"60"; when x"DE4" => DATA <= x"20"; when x"DE5" => DATA <= x"63"; when x"DE6" => DATA <= x"E7"; when x"DE7" => DATA <= x"20"; when x"DE8" => DATA <= x"91"; when x"DE9" => DATA <= x"E6"; when x"DEA" => DATA <= x"20"; when x"DEB" => DATA <= x"BC"; when x"DEC" => DATA <= x"E6"; when x"DED" => DATA <= x"84"; when x"DEE" => DATA <= x"9A"; when x"DEF" => DATA <= x"60"; when x"DF0" => DATA <= x"A4"; when x"DF1" => DATA <= x"03"; when x"DF2" => DATA <= x"4C"; when x"DF3" => DATA <= x"76"; when x"DF4" => DATA <= x"FA"; when x"DF5" => DATA <= x"20"; when x"DF6" => DATA <= x"D1"; when x"DF7" => DATA <= x"F7"; when x"DF8" => DATA <= x"20"; when x"DF9" => DATA <= x"3A"; when x"DFA" => DATA <= x"28"; when x"DFB" => DATA <= x"59"; when x"DFC" => DATA <= x"2F"; when x"DFD" => DATA <= x"4E"; when x"DFE" => DATA <= x"29"; when x"DFF" => DATA <= x"EA"; when x"E00" => DATA <= x"4C"; when x"E01" => DATA <= x"94"; when x"E02" => DATA <= x"FE"; when x"E03" => DATA <= x"A0"; when x"E04" => DATA <= x"06"; when x"E05" => DATA <= x"20"; when x"E06" => DATA <= x"FD"; when x"E07" => DATA <= x"F7"; when x"E08" => DATA <= x"88"; when x"E09" => DATA <= x"D0"; when x"E0A" => DATA <= x"FA"; when x"E0B" => DATA <= x"60"; when x"E0C" => DATA <= x"C8"; when x"E0D" => DATA <= x"C8"; when x"E0E" => DATA <= x"C8"; when x"E0F" => DATA <= x"C8"; when x"E10" => DATA <= x"C8"; when x"E11" => DATA <= x"C8"; when x"E12" => DATA <= x"C8"; when x"E13" => DATA <= x"C8"; when x"E14" => DATA <= x"60"; when x"E15" => DATA <= x"88"; when x"E16" => DATA <= x"88"; when x"E17" => DATA <= x"88"; when x"E18" => DATA <= x"88"; when x"E19" => DATA <= x"88"; when x"E1A" => DATA <= x"88"; when x"E1B" => DATA <= x"88"; when x"E1C" => DATA <= x"88"; when x"E1D" => DATA <= x"60"; when x"E1E" => DATA <= x"4A"; when x"E1F" => DATA <= x"4A"; when x"E20" => DATA <= x"4A"; when x"E21" => DATA <= x"4A"; when x"E22" => DATA <= x"4A"; when x"E23" => DATA <= x"60"; when x"E24" => DATA <= x"A9"; when x"E25" => DATA <= x"EB"; when x"E26" => DATA <= x"8D"; when x"E27" => DATA <= x"3E"; when x"E28" => DATA <= x"02"; when x"E29" => DATA <= x"A9"; when x"E2A" => DATA <= x"EE"; when x"E2B" => DATA <= x"8D"; when x"E2C" => DATA <= x"3F"; when x"E2D" => DATA <= x"02"; when x"E2E" => DATA <= x"A9"; when x"E2F" => DATA <= x"80"; when x"E30" => DATA <= x"8D"; when x"E31" => DATA <= x"2B"; when x"E32" => DATA <= x"02"; when x"E33" => DATA <= x"20"; when x"E34" => DATA <= x"21"; when x"E35" => DATA <= x"EF"; when x"E36" => DATA <= x"B0"; when x"E37" => DATA <= x"29"; when x"E38" => DATA <= x"A9"; when x"E39" => DATA <= x"F8"; when x"E3A" => DATA <= x"8D"; when x"E3B" => DATA <= x"3E"; when x"E3C" => DATA <= x"02"; when x"E3D" => DATA <= x"A9"; when x"E3E" => DATA <= x"EE"; when x"E3F" => DATA <= x"8D"; when x"E40" => DATA <= x"3F"; when x"E41" => DATA <= x"02"; when x"E42" => DATA <= x"A9"; when x"E43" => DATA <= x"40"; when x"E44" => DATA <= x"8D"; when x"E45" => DATA <= x"2B"; when x"E46" => DATA <= x"02"; when x"E47" => DATA <= x"20"; when x"E48" => DATA <= x"54"; when x"E49" => DATA <= x"EF"; when x"E4A" => DATA <= x"20"; when x"E4B" => DATA <= x"21"; when x"E4C" => DATA <= x"EF"; when x"E4D" => DATA <= x"B0"; when x"E4E" => DATA <= x"12"; when x"E4F" => DATA <= x"A9"; when x"E50" => DATA <= x"62"; when x"E51" => DATA <= x"8D"; when x"E52" => DATA <= x"3E"; when x"E53" => DATA <= x"02"; when x"E54" => DATA <= x"A9"; when x"E55" => DATA <= x"EE"; when x"E56" => DATA <= x"8D"; when x"E57" => DATA <= x"3F"; when x"E58" => DATA <= x"02"; when x"E59" => DATA <= x"A9"; when x"E5A" => DATA <= x"00"; when x"E5B" => DATA <= x"8D"; when x"E5C" => DATA <= x"2B"; when x"E5D" => DATA <= x"02"; when x"E5E" => DATA <= x"4C"; when x"E5F" => DATA <= x"62"; when x"E60" => DATA <= x"EE"; when x"E61" => DATA <= x"60"; when x"E62" => DATA <= x"20"; when x"E63" => DATA <= x"D1"; when x"E64" => DATA <= x"F7"; when x"E65" => DATA <= x"49"; when x"E66" => DATA <= x"4E"; when x"E67" => DATA <= x"54"; when x"E68" => DATA <= x"45"; when x"E69" => DATA <= x"52"; when x"E6A" => DATA <= x"46"; when x"E6B" => DATA <= x"41"; when x"E6C" => DATA <= x"43"; when x"E6D" => DATA <= x"45"; when x"E6E" => DATA <= x"3F"; when x"E6F" => DATA <= x"EA"; when x"E70" => DATA <= x"00"; when x"E71" => DATA <= x"20"; when x"E72" => DATA <= x"9F"; when x"E73" => DATA <= x"EE"; when x"E74" => DATA <= x"A2"; when x"E75" => DATA <= x"02"; when x"E76" => DATA <= x"A0"; when x"E77" => DATA <= x"00"; when x"E78" => DATA <= x"20"; when x"E79" => DATA <= x"FB"; when x"E7A" => DATA <= x"EF"; when x"E7B" => DATA <= x"91"; when x"E7C" => DATA <= x"F9"; when x"E7D" => DATA <= x"C8"; when x"E7E" => DATA <= x"D0"; when x"E7F" => DATA <= x"F8"; when x"E80" => DATA <= x"E6"; when x"E81" => DATA <= x"FA"; when x"E82" => DATA <= x"CA"; when x"E83" => DATA <= x"D0"; when x"E84" => DATA <= x"F3"; when x"E85" => DATA <= x"4C"; when x"E86" => DATA <= x"AE"; when x"E87" => DATA <= x"EE"; when x"E88" => DATA <= x"20"; when x"E89" => DATA <= x"B7"; when x"E8A" => DATA <= x"EE"; when x"E8B" => DATA <= x"A2"; when x"E8C" => DATA <= x"02"; when x"E8D" => DATA <= x"A0"; when x"E8E" => DATA <= x"00"; when x"E8F" => DATA <= x"B1"; when x"E90" => DATA <= x"F9"; when x"E91" => DATA <= x"20"; when x"E92" => DATA <= x"FD"; when x"E93" => DATA <= x"EF"; when x"E94" => DATA <= x"C8"; when x"E95" => DATA <= x"D0"; when x"E96" => DATA <= x"F8"; when x"E97" => DATA <= x"E6"; when x"E98" => DATA <= x"FA"; when x"E99" => DATA <= x"CA"; when x"E9A" => DATA <= x"D0"; when x"E9B" => DATA <= x"F3"; when x"E9C" => DATA <= x"4C"; when x"E9D" => DATA <= x"D7"; when x"E9E" => DATA <= x"EE"; when x"E9F" => DATA <= x"20"; when x"EA0" => DATA <= x"E5"; when x"EA1" => DATA <= x"EF"; when x"EA2" => DATA <= x"A9"; when x"EA3" => DATA <= x"51"; when x"EA4" => DATA <= x"20"; when x"EA5" => DATA <= x"6E"; when x"EA6" => DATA <= x"EF"; when x"EA7" => DATA <= x"D0"; when x"EA8" => DATA <= x"20"; when x"EA9" => DATA <= x"A9"; when x"EAA" => DATA <= x"FE"; when x"EAB" => DATA <= x"4C"; when x"EAC" => DATA <= x"BF"; when x"EAD" => DATA <= x"EF"; when x"EAE" => DATA <= x"20"; when x"EAF" => DATA <= x"FB"; when x"EB0" => DATA <= x"EF"; when x"EB1" => DATA <= x"20"; when x"EB2" => DATA <= x"FB"; when x"EB3" => DATA <= x"EF"; when x"EB4" => DATA <= x"4C"; when x"EB5" => DATA <= x"AF"; when x"EB6" => DATA <= x"EF"; when x"EB7" => DATA <= x"20"; when x"EB8" => DATA <= x"E5"; when x"EB9" => DATA <= x"EF"; when x"EBA" => DATA <= x"A9"; when x"EBB" => DATA <= x"58"; when x"EBC" => DATA <= x"20"; when x"EBD" => DATA <= x"6E"; when x"EBE" => DATA <= x"EF"; when x"EBF" => DATA <= x"F0"; when x"EC0" => DATA <= x"03"; when x"EC1" => DATA <= x"4C"; when x"EC2" => DATA <= x"C9"; when x"EC3" => DATA <= x"EE"; when x"EC4" => DATA <= x"A9"; when x"EC5" => DATA <= x"FE"; when x"EC6" => DATA <= x"4C"; when x"EC7" => DATA <= x"FD"; when x"EC8" => DATA <= x"EF"; when x"EC9" => DATA <= x"20"; when x"ECA" => DATA <= x"D1"; when x"ECB" => DATA <= x"F7"; when x"ECC" => DATA <= x"4E"; when x"ECD" => DATA <= x"4F"; when x"ECE" => DATA <= x"54"; when x"ECF" => DATA <= x"20"; when x"ED0" => DATA <= x"52"; when x"ED1" => DATA <= x"45"; when x"ED2" => DATA <= x"41"; when x"ED3" => DATA <= x"44"; when x"ED4" => DATA <= x"59"; when x"ED5" => DATA <= x"EA"; when x"ED6" => DATA <= x"00"; when x"ED7" => DATA <= x"20"; when x"ED8" => DATA <= x"FB"; when x"ED9" => DATA <= x"EF"; when x"EDA" => DATA <= x"20"; when x"EDB" => DATA <= x"FB"; when x"EDC" => DATA <= x"EF"; when x"EDD" => DATA <= x"20"; when x"EDE" => DATA <= x"FB"; when x"EDF" => DATA <= x"EF"; when x"EE0" => DATA <= x"A9"; when x"EE1" => DATA <= x"FF"; when x"EE2" => DATA <= x"20"; when x"EE3" => DATA <= x"BF"; when x"EE4" => DATA <= x"EF"; when x"EE5" => DATA <= x"20"; when x"EE6" => DATA <= x"FB"; when x"EE7" => DATA <= x"EF"; when x"EE8" => DATA <= x"4C"; when x"EE9" => DATA <= x"AF"; when x"EEA" => DATA <= x"EF"; when x"EEB" => DATA <= x"8D"; when x"EEC" => DATA <= x"00"; when x"EED" => DATA <= x"B4"; when x"EEE" => DATA <= x"EA"; when x"EEF" => DATA <= x"EA"; when x"EF0" => DATA <= x"EA"; when x"EF1" => DATA <= x"EA"; when x"EF2" => DATA <= x"EA"; when x"EF3" => DATA <= x"EA"; when x"EF4" => DATA <= x"AD"; when x"EF5" => DATA <= x"00"; when x"EF6" => DATA <= x"B4"; when x"EF7" => DATA <= x"60"; when x"EF8" => DATA <= x"8E"; when x"EF9" => DATA <= x"D4"; when x"EFA" => DATA <= x"03"; when x"EFB" => DATA <= x"8C"; when x"EFC" => DATA <= x"D5"; when x"EFD" => DATA <= x"03"; when x"EFE" => DATA <= x"A0"; when x"EFF" => DATA <= x"08"; when x"F00" => DATA <= x"48"; when x"F01" => DATA <= x"29"; when x"F02" => DATA <= x"80"; when x"F03" => DATA <= x"8D"; when x"F04" => DATA <= x"00"; when x"F05" => DATA <= x"B8"; when x"F06" => DATA <= x"09"; when x"F07" => DATA <= x"40"; when x"F08" => DATA <= x"8D"; when x"F09" => DATA <= x"00"; when x"F0A" => DATA <= x"B8"; when x"F0B" => DATA <= x"AE"; when x"F0C" => DATA <= x"00"; when x"F0D" => DATA <= x"B8"; when x"F0E" => DATA <= x"49"; when x"F0F" => DATA <= x"40"; when x"F10" => DATA <= x"8D"; when x"F11" => DATA <= x"00"; when x"F12" => DATA <= x"B8"; when x"F13" => DATA <= x"8A"; when x"F14" => DATA <= x"6A"; when x"F15" => DATA <= x"68"; when x"F16" => DATA <= x"2A"; when x"F17" => DATA <= x"88"; when x"F18" => DATA <= x"D0"; when x"F19" => DATA <= x"E6"; when x"F1A" => DATA <= x"AC"; when x"F1B" => DATA <= x"D5"; when x"F1C" => DATA <= x"03"; when x"F1D" => DATA <= x"AE"; when x"F1E" => DATA <= x"D4"; when x"F1F" => DATA <= x"03"; when x"F20" => DATA <= x"60"; when x"F21" => DATA <= x"A2"; when x"F22" => DATA <= x"01"; when x"F23" => DATA <= x"86"; when x"F24" => DATA <= x"04"; when x"F25" => DATA <= x"A9"; when x"F26" => DATA <= x"00"; when x"F27" => DATA <= x"95"; when x"F28" => DATA <= x"16"; when x"F29" => DATA <= x"95"; when x"F2A" => DATA <= x"25"; when x"F2B" => DATA <= x"95"; when x"F2C" => DATA <= x"34"; when x"F2D" => DATA <= x"95"; when x"F2E" => DATA <= x"43"; when x"F2F" => DATA <= x"A9"; when x"F30" => DATA <= x"40"; when x"F31" => DATA <= x"20"; when x"F32" => DATA <= x"6E"; when x"F33" => DATA <= x"EF"; when x"F34" => DATA <= x"C9"; when x"F35" => DATA <= x"01"; when x"F36" => DATA <= x"D0"; when x"F37" => DATA <= x"18"; when x"F38" => DATA <= x"A9"; when x"F39" => DATA <= x"69"; when x"F3A" => DATA <= x"20"; when x"F3B" => DATA <= x"6E"; when x"F3C" => DATA <= x"EF"; when x"F3D" => DATA <= x"F0"; when x"F3E" => DATA <= x"13"; when x"F3F" => DATA <= x"A9"; when x"F40" => DATA <= x"00"; when x"F41" => DATA <= x"8D"; when x"F42" => DATA <= x"D1"; when x"F43" => DATA <= x"03"; when x"F44" => DATA <= x"A9"; when x"F45" => DATA <= x"41"; when x"F46" => DATA <= x"20"; when x"F47" => DATA <= x"6E"; when x"F48" => DATA <= x"EF"; when x"F49" => DATA <= x"F0"; when x"F4A" => DATA <= x"07"; when x"F4B" => DATA <= x"CE"; when x"F4C" => DATA <= x"D1"; when x"F4D" => DATA <= x"03"; when x"F4E" => DATA <= x"D0"; when x"F4F" => DATA <= x"F4"; when x"F50" => DATA <= x"18"; when x"F51" => DATA <= x"60"; when x"F52" => DATA <= x"38"; when x"F53" => DATA <= x"60"; when x"F54" => DATA <= x"A9"; when x"F55" => DATA <= x"E0"; when x"F56" => DATA <= x"8D"; when x"F57" => DATA <= x"00"; when x"F58" => DATA <= x"B8"; when x"F59" => DATA <= x"A9"; when x"F5A" => DATA <= x"FE"; when x"F5B" => DATA <= x"8D"; when x"F5C" => DATA <= x"02"; when x"F5D" => DATA <= x"B8"; when x"F5E" => DATA <= x"A9"; when x"F5F" => DATA <= x"E0"; when x"F60" => DATA <= x"A2"; when x"F61" => DATA <= x"A0"; when x"F62" => DATA <= x"A0"; when x"F63" => DATA <= x"58"; when x"F64" => DATA <= x"8D"; when x"F65" => DATA <= x"00"; when x"F66" => DATA <= x"B8"; when x"F67" => DATA <= x"8E"; when x"F68" => DATA <= x"00"; when x"F69" => DATA <= x"B8"; when x"F6A" => DATA <= x"88"; when x"F6B" => DATA <= x"D0"; when x"F6C" => DATA <= x"F7"; when x"F6D" => DATA <= x"60"; when x"F6E" => DATA <= x"48"; when x"F6F" => DATA <= x"AD"; when x"F70" => DATA <= x"2B"; when x"F71" => DATA <= x"02"; when x"F72" => DATA <= x"F0"; when x"F73" => DATA <= x"34"; when x"F74" => DATA <= x"20"; when x"F75" => DATA <= x"AB"; when x"F76" => DATA <= x"EF"; when x"F77" => DATA <= x"20"; when x"F78" => DATA <= x"FB"; when x"F79" => DATA <= x"EF"; when x"F7A" => DATA <= x"68"; when x"F7B" => DATA <= x"20"; when x"F7C" => DATA <= x"FD"; when x"F7D" => DATA <= x"EF"; when x"F7E" => DATA <= x"A6"; when x"F7F" => DATA <= x"04"; when x"F80" => DATA <= x"B5"; when x"F81" => DATA <= x"43"; when x"F82" => DATA <= x"20"; when x"F83" => DATA <= x"FD"; when x"F84" => DATA <= x"EF"; when x"F85" => DATA <= x"B5"; when x"F86" => DATA <= x"34"; when x"F87" => DATA <= x"20"; when x"F88" => DATA <= x"FD"; when x"F89" => DATA <= x"EF"; when x"F8A" => DATA <= x"B5"; when x"F8B" => DATA <= x"25"; when x"F8C" => DATA <= x"20"; when x"F8D" => DATA <= x"FD"; when x"F8E" => DATA <= x"EF"; when x"F8F" => DATA <= x"B5"; when x"F90" => DATA <= x"16"; when x"F91" => DATA <= x"20"; when x"F92" => DATA <= x"FD"; when x"F93" => DATA <= x"EF"; when x"F94" => DATA <= x"A9"; when x"F95" => DATA <= x"95"; when x"F96" => DATA <= x"20"; when x"F97" => DATA <= x"FD"; when x"F98" => DATA <= x"EF"; when x"F99" => DATA <= x"A0"; when x"F9A" => DATA <= x"00"; when x"F9B" => DATA <= x"88"; when x"F9C" => DATA <= x"F0"; when x"F9D" => DATA <= x"07"; when x"F9E" => DATA <= x"20"; when x"F9F" => DATA <= x"FB"; when x"FA0" => DATA <= x"EF"; when x"FA1" => DATA <= x"29"; when x"FA2" => DATA <= x"FF"; when x"FA3" => DATA <= x"30"; when x"FA4" => DATA <= x"F6"; when x"FA5" => DATA <= x"C9"; when x"FA6" => DATA <= x"00"; when x"FA7" => DATA <= x"60"; when x"FA8" => DATA <= x"4C"; when x"FA9" => DATA <= x"62"; when x"FAA" => DATA <= x"EE"; when x"FAB" => DATA <= x"A9"; when x"FAC" => DATA <= x"80"; when x"FAD" => DATA <= x"D0"; when x"FAE" => DATA <= x"02"; when x"FAF" => DATA <= x"A9"; when x"FB0" => DATA <= x"A0"; when x"FB1" => DATA <= x"2C"; when x"FB2" => DATA <= x"2B"; when x"FB3" => DATA <= x"02"; when x"FB4" => DATA <= x"30"; when x"FB5" => DATA <= x"08"; when x"FB6" => DATA <= x"8D"; when x"FB7" => DATA <= x"00"; when x"FB8" => DATA <= x"B8"; when x"FB9" => DATA <= x"A2"; when x"FBA" => DATA <= x"00"; when x"FBB" => DATA <= x"CA"; when x"FBC" => DATA <= x"D0"; when x"FBD" => DATA <= x"FD"; when x"FBE" => DATA <= x"60"; when x"FBF" => DATA <= x"A0"; when x"FC0" => DATA <= x"00"; when x"FC1" => DATA <= x"8D"; when x"FC2" => DATA <= x"D1"; when x"FC3" => DATA <= x"03"; when x"FC4" => DATA <= x"88"; when x"FC5" => DATA <= x"F0"; when x"FC6" => DATA <= x"09"; when x"FC7" => DATA <= x"20"; when x"FC8" => DATA <= x"FB"; when x"FC9" => DATA <= x"EF"; when x"FCA" => DATA <= x"CD"; when x"FCB" => DATA <= x"D1"; when x"FCC" => DATA <= x"03"; when x"FCD" => DATA <= x"D0"; when x"FCE" => DATA <= x"F5"; when x"FCF" => DATA <= x"60"; when x"FD0" => DATA <= x"20"; when x"FD1" => DATA <= x"D1"; when x"FD2" => DATA <= x"F7"; when x"FD3" => DATA <= x"20"; when x"FD4" => DATA <= x"20"; when x"FD5" => DATA <= x"52"; when x"FD6" => DATA <= x"45"; when x"FD7" => DATA <= x"53"; when x"FD8" => DATA <= x"50"; when x"FD9" => DATA <= x"4F"; when x"FDA" => DATA <= x"4E"; when x"FDB" => DATA <= x"53"; when x"FDC" => DATA <= x"45"; when x"FDD" => DATA <= x"20"; when x"FDE" => DATA <= x"45"; when x"FDF" => DATA <= x"52"; when x"FE0" => DATA <= x"52"; when x"FE1" => DATA <= x"4F"; when x"FE2" => DATA <= x"52"; when x"FE3" => DATA <= x"EA"; when x"FE4" => DATA <= x"00"; when x"FE5" => DATA <= x"A6"; when x"FE6" => DATA <= x"04"; when x"FE7" => DATA <= x"A5"; when x"FE8" => DATA <= x"84"; when x"FE9" => DATA <= x"0A"; when x"FEA" => DATA <= x"95"; when x"FEB" => DATA <= x"25"; when x"FEC" => DATA <= x"A5"; when x"FED" => DATA <= x"85"; when x"FEE" => DATA <= x"2A"; when x"FEF" => DATA <= x"95"; when x"FF0" => DATA <= x"34"; when x"FF1" => DATA <= x"A5"; when x"FF2" => DATA <= x"86"; when x"FF3" => DATA <= x"2A"; when x"FF4" => DATA <= x"95"; when x"FF5" => DATA <= x"43"; when x"FF6" => DATA <= x"A9"; when x"FF7" => DATA <= x"00"; when x"FF8" => DATA <= x"95"; when x"FF9" => DATA <= x"16"; when x"FFA" => DATA <= x"60"; when x"FFB" => DATA <= x"A9"; when x"FFC" => DATA <= x"FF"; when x"FFD" => DATA <= x"6C"; when x"FFE" => DATA <= x"3E"; when x"FFF" => DATA <= x"02"; when others => DATA <= (others => '0'); end case; end process; end RTL;
apache-2.0
c39fae4c4952996c22c9dda4467a6385
0.406424
2.580196
false
false
false
false
hoglet67/AtomFpga
src/common/AVR8/uC/external_mux.vhd
4
1,631
--************************************************************************************************ -- External multeplexer for AVR core -- Version 2.2 -- Designed by Ruslan Lepetenok 05.11.2001 -- Modified 29.08.2003 --************************************************************************************************ library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use WORK.AVRuCPackage.all; entity external_mux is port( ramre : in std_logic; dbus_out : out std_logic_vector(7 downto 0); ram_data_out : in std_logic_vector(7 downto 0); io_port_bus : in ext_mux_din_type; io_port_en_bus : in ext_mux_en_type; irqack : in std_logic; irqackad : in std_logic_vector(4 downto 0); ind_irq_ack : out std_logic_vector(22 downto 0) ); end external_mux; architecture RTL of external_mux is signal ext_mux_out : ext_mux_din_type; begin ext_mux_out(0) <= io_port_bus(0) when io_port_en_bus(0)='1' else (others => '0'); data_mux_for_read:for i in 1 to ext_mux_out'high generate ext_mux_out(i) <= io_port_bus(i) when io_port_en_bus(i)='1' else ext_mux_out(i-1); end generate; dbus_out <= ram_data_out when ramre='1' else ext_mux_out(ext_mux_out'high); interrupt_ack:for i in ind_irq_ack'range generate ind_irq_ack(i) <= '1' when (irqackad=i+1 and irqack='1') else '0'; end generate; end RTL;
apache-2.0
5bd5af46ffe7cbb39c6a468606bc8e09
0.481913
3.397917
false
false
false
false
hoglet67/AtomFpga
src/xilinx/DCM/dcm5.vhd
1
1,981
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library UNISIM; use UNISIM.Vcomponents.all; entity dcm5 is port (CLKIN_IN : in std_logic; CLKFX_OUT : out std_logic); end dcm5; architecture BEHAVIORAL of dcm5 is signal CLKFX_BUF : std_logic; signal CLKIN_IBUFG : std_logic; signal GND_BIT : std_logic; signal CLK0 : std_logic; begin GND_BIT <= '0'; CLKFX_BUFG_INST : BUFG port map (I => CLKFX_BUF, O => CLKFX_OUT); DCM_INST : DCM generic map(CLK_FEEDBACK => "1X", CLKDV_DIVIDE => 4.0, CLKFX_DIVIDE => 16, CLKFX_MULTIPLY => 8, CLKIN_DIVIDE_BY_2 => false, CLKIN_PERIOD => 31.250, CLKOUT_PHASE_SHIFT => "NONE", DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW", DUTY_CYCLE_CORRECTION => true, FACTORY_JF => x"C080", PHASE_SHIFT => 0, STARTUP_WAIT => false) port map (CLKFB => CLK0, CLKIN => CLKIN_IN, DSSEN => GND_BIT, PSCLK => GND_BIT, PSEN => GND_BIT, PSINCDEC => GND_BIT, RST => GND_BIT, CLKDV => open, CLKFX => CLKFX_BUF, CLKFX180 => open, CLK0 => CLK0, CLK2X => open, CLK2X180 => open, CLK90 => open, CLK180 => open, CLK270 => open, LOCKED => open, PSDONE => open, STATUS => open); end BEHAVIORAL;
apache-2.0
eb946e55de6c9cd4fd09c24b8796bf61
0.400303
4.412027
false
false
false
false
hoglet67/AtomFpga
src/altera/pll25.vhd
1
15,432
-- megafunction wizard: %ALTPLL% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: altpll -- ============================================================ -- File Name: pll25.vhd -- Megafunction Name(s): -- altpll -- -- Simulation Library Files(s): -- altera_mf -- ============================================================ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- -- 9.1 Build 222 10/21/2009 SJ Web Edition -- ************************************************************ --Copyright (C) 1991-2009 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject --to the terms and conditions of the Altera Program License --Subscription Agreement, Altera MegaCore Function License --Agreement, or other applicable license agreement, including, --without limitation, that your use is for the sole purpose of --programming logic devices manufactured by Altera and sold by --Altera or its authorized distributors. Please refer to the --applicable agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY altera_mf; USE altera_mf.all; ENTITY pll25 IS PORT ( areset : IN STD_LOGIC := '0'; inclk0 : IN STD_LOGIC := '0'; c0 : OUT STD_LOGIC ; locked : OUT STD_LOGIC ); END pll25; ARCHITECTURE SYN OF pll25 IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0); SIGNAL sub_wire1 : STD_LOGIC ; SIGNAL sub_wire2 : STD_LOGIC ; SIGNAL sub_wire3 : STD_LOGIC ; SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0); SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0); SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0); COMPONENT altpll GENERIC ( clk0_divide_by : NATURAL; clk0_duty_cycle : NATURAL; clk0_multiply_by : NATURAL; clk0_phase_shift : STRING; compensate_clock : STRING; gate_lock_signal : STRING; inclk0_input_frequency : NATURAL; intended_device_family : STRING; invalid_lock_multiplier : NATURAL; lpm_hint : STRING; lpm_type : STRING; operation_mode : STRING; port_activeclock : STRING; port_areset : STRING; port_clkbad0 : STRING; port_clkbad1 : STRING; port_clkloss : STRING; port_clkswitch : STRING; port_configupdate : STRING; port_fbin : STRING; port_inclk0 : STRING; port_inclk1 : STRING; port_locked : STRING; port_pfdena : STRING; port_phasecounterselect : STRING; port_phasedone : STRING; port_phasestep : STRING; port_phaseupdown : STRING; port_pllena : STRING; port_scanaclr : STRING; port_scanclk : STRING; port_scanclkena : STRING; port_scandata : STRING; port_scandataout : STRING; port_scandone : STRING; port_scanread : STRING; port_scanwrite : STRING; port_clk0 : STRING; port_clk1 : STRING; port_clk2 : STRING; port_clk3 : STRING; port_clk4 : STRING; port_clk5 : STRING; port_clkena0 : STRING; port_clkena1 : STRING; port_clkena2 : STRING; port_clkena3 : STRING; port_clkena4 : STRING; port_clkena5 : STRING; port_extclk0 : STRING; port_extclk1 : STRING; port_extclk2 : STRING; port_extclk3 : STRING; valid_lock_multiplier : NATURAL ); PORT ( inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); locked : OUT STD_LOGIC ; areset : IN STD_LOGIC ; clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0) ); END COMPONENT; BEGIN sub_wire5_bv(0 DOWNTO 0) <= "0"; sub_wire5 <= To_stdlogicvector(sub_wire5_bv); sub_wire1 <= sub_wire0(0); c0 <= sub_wire1; locked <= sub_wire2; sub_wire3 <= inclk0; sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3; altpll_component : altpll GENERIC MAP ( clk0_divide_by => 4, clk0_duty_cycle => 50, clk0_multiply_by => 2, clk0_phase_shift => "0", compensate_clock => "CLK0", gate_lock_signal => "NO", inclk0_input_frequency => 41666, intended_device_family => "Cyclone II", invalid_lock_multiplier => 5, lpm_hint => "CBX_MODULE_PREFIX=pll25", lpm_type => "altpll", operation_mode => "NORMAL", port_activeclock => "PORT_UNUSED", port_areset => "PORT_USED", port_clkbad0 => "PORT_UNUSED", port_clkbad1 => "PORT_UNUSED", port_clkloss => "PORT_UNUSED", port_clkswitch => "PORT_UNUSED", port_configupdate => "PORT_UNUSED", port_fbin => "PORT_UNUSED", port_inclk0 => "PORT_USED", port_inclk1 => "PORT_UNUSED", port_locked => "PORT_USED", port_pfdena => "PORT_UNUSED", port_phasecounterselect => "PORT_UNUSED", port_phasedone => "PORT_UNUSED", port_phasestep => "PORT_UNUSED", port_phaseupdown => "PORT_UNUSED", port_pllena => "PORT_UNUSED", port_scanaclr => "PORT_UNUSED", port_scanclk => "PORT_UNUSED", port_scanclkena => "PORT_UNUSED", port_scandata => "PORT_UNUSED", port_scandataout => "PORT_UNUSED", port_scandone => "PORT_UNUSED", port_scanread => "PORT_UNUSED", port_scanwrite => "PORT_UNUSED", port_clk0 => "PORT_USED", port_clk1 => "PORT_UNUSED", port_clk2 => "PORT_UNUSED", port_clk3 => "PORT_UNUSED", port_clk4 => "PORT_UNUSED", port_clk5 => "PORT_UNUSED", port_clkena0 => "PORT_UNUSED", port_clkena1 => "PORT_UNUSED", port_clkena2 => "PORT_UNUSED", port_clkena3 => "PORT_UNUSED", port_clkena4 => "PORT_UNUSED", port_clkena5 => "PORT_UNUSED", port_extclk0 => "PORT_UNUSED", port_extclk1 => "PORT_UNUSED", port_extclk2 => "PORT_UNUSED", port_extclk3 => "PORT_UNUSED", valid_lock_multiplier => 1 ) PORT MAP ( inclk => sub_wire4, areset => areset, clk => sub_wire0, locked => sub_wire2 ); END SYN; -- ============================================================ -- CNX file retrieval info -- ============================================================ -- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" -- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" -- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0" -- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" -- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" -- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" -- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0" -- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" -- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" -- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" -- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1" -- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" -- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" -- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" -- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" -- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0" -- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7" -- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" -- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" -- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "25.000000" -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" -- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" -- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1" -- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" -- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" -- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" -- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000" -- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" -- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" -- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" -- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" -- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" -- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" -- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" -- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "312.000" -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" -- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" -- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" -- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" -- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" -- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "25.00000000" -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" -- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0" -- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" -- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" -- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" -- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" -- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" -- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" -- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0" -- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" -- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" -- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" -- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" -- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" -- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" -- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" -- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll25.mif" -- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" -- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0" -- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" -- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" -- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" -- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" -- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" -- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" -- Retrieval info: PRIVATE: SPREAD_USE STRING "0" -- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" -- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" -- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" -- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: USE_CLK0 STRING "1" -- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" -- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" -- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "4" -- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" -- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2" -- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" -- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" -- Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO" -- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "41666" -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II" -- Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5" -- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" -- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" -- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" -- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" -- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" -- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" -- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1" -- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]" -- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]" -- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" -- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" -- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" -- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" -- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" -- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 -- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 -- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 -- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 -- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 -- Retrieval info: GEN_FILE: TYPE_NORMAL pll25.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL pll25.ppf TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL pll25.inc FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL pll25.cmp FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL pll25.bsf FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL pll25_inst.vhd FALSE -- Retrieval info: LIB_FILE: altera_mf -- Retrieval info: CBX_MODULE_PREFIX: ON
apache-2.0
ee1698a2a31d9219e9d21639ffd94b3b
0.699132
3.35114
false
false
false
false
fquinto/Wireless_sensor_network
Avnet_UPC/hdl/ilmb_cntlr_wrapper.vhd
1
3,132
------------------------------------------------------------------------------- -- ilmb_cntlr_wrapper.vhd ------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; library lmb_bram_if_cntlr_v2_10_b; use lmb_bram_if_cntlr_v2_10_b.all; entity ilmb_cntlr_wrapper is port ( LMB_Clk : in std_logic; LMB_Rst : in std_logic; LMB_ABus : in std_logic_vector(0 to 31); LMB_WriteDBus : in std_logic_vector(0 to 31); LMB_AddrStrobe : in std_logic; LMB_ReadStrobe : in std_logic; LMB_WriteStrobe : in std_logic; LMB_BE : in std_logic_vector(0 to 3); Sl_DBus : out std_logic_vector(0 to 31); Sl_Ready : out std_logic; BRAM_Rst_A : out std_logic; BRAM_Clk_A : out std_logic; BRAM_EN_A : out std_logic; BRAM_WEN_A : out std_logic_vector(0 to 3); BRAM_Addr_A : out std_logic_vector(0 to 31); BRAM_Din_A : in std_logic_vector(0 to 31); BRAM_Dout_A : out std_logic_vector(0 to 31) ); attribute x_core_info : STRING; attribute x_core_info of ilmb_cntlr_wrapper : entity is "lmb_bram_if_cntlr_v2_10_b"; end ilmb_cntlr_wrapper; architecture STRUCTURE of ilmb_cntlr_wrapper is component lmb_bram_if_cntlr is generic ( C_BASEADDR : std_logic_vector(0 to 31); C_HIGHADDR : std_logic_vector(0 to 31); C_MASK : std_logic_vector(0 to 31); C_LMB_AWIDTH : integer; C_LMB_DWIDTH : integer ); port ( LMB_Clk : in std_logic; LMB_Rst : in std_logic; LMB_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1); LMB_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1); LMB_AddrStrobe : in std_logic; LMB_ReadStrobe : in std_logic; LMB_WriteStrobe : in std_logic; LMB_BE : in std_logic_vector(0 to C_LMB_DWIDTH/8-1); Sl_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1); Sl_Ready : out std_logic; BRAM_Rst_A : out std_logic; BRAM_Clk_A : out std_logic; BRAM_EN_A : out std_logic; BRAM_WEN_A : out std_logic_vector(0 to (C_LMB_DWIDTH/8)-1); BRAM_Addr_A : out std_logic_vector(0 to C_LMB_AWIDTH-1); BRAM_Din_A : in std_logic_vector(0 to C_LMB_DWIDTH-1); BRAM_Dout_A : out std_logic_vector(0 to C_LMB_DWIDTH-1) ); end component; begin ilmb_cntlr : lmb_bram_if_cntlr generic map ( C_BASEADDR => X"00000000", C_HIGHADDR => X"00007fff", C_MASK => X"80000000", C_LMB_AWIDTH => 32, C_LMB_DWIDTH => 32 ) port map ( LMB_Clk => LMB_Clk, LMB_Rst => LMB_Rst, LMB_ABus => LMB_ABus, LMB_WriteDBus => LMB_WriteDBus, LMB_AddrStrobe => LMB_AddrStrobe, LMB_ReadStrobe => LMB_ReadStrobe, LMB_WriteStrobe => LMB_WriteStrobe, LMB_BE => LMB_BE, Sl_DBus => Sl_DBus, Sl_Ready => Sl_Ready, BRAM_Rst_A => BRAM_Rst_A, BRAM_Clk_A => BRAM_Clk_A, BRAM_EN_A => BRAM_EN_A, BRAM_WEN_A => BRAM_WEN_A, BRAM_Addr_A => BRAM_Addr_A, BRAM_Din_A => BRAM_Din_A, BRAM_Dout_A => BRAM_Dout_A ); end architecture STRUCTURE;
mit
76e8d0d521580d21b9c22b0028bd9dc1
0.576948
3.082677
false
false
false
false
hoglet67/AtomFpga
src/common/AVR8/Core/io_reg_file.vhd
4
4,134
--************************************************************************************************ -- Internal I/O registers (implemented inside the core) decoder/multiplexer -- for AVR core -- Version 1.3 (Special version for the JTAG OCD) -- Designed by Ruslan Lepetenok -- Modified 22.04.2004 --************************************************************************************************ library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use WORK.AVRuCPackage.all; entity io_reg_file is port ( --Clock and reset cp2 : in std_logic; cp2en : in std_logic; ireset : in std_logic; adr : in std_logic_vector(15 downto 0); iowe : in std_logic; dbusout : in std_logic_vector(7 downto 0); sreg_fl_in : in std_logic_vector(7 downto 0); sreg_out : out std_logic_vector(7 downto 0); sreg_fl_wr_en : in std_logic_vector (7 downto 0); --FLAGS WRITE ENABLE SIGNALS spl_out : out std_logic_vector(7 downto 0); sph_out : out std_logic_vector(7 downto 0); sp_ndown_up : in std_logic; -- DIRECTION OF CHANGING OF STACK POINTER SPH:SPL 0->UP(+) 1->DOWN(-) sp_en : in std_logic; -- WRITE ENABLE(COUNT ENABLE) FOR SPH AND SPL REGISTERS rampz_out : out std_logic_vector(7 downto 0)); end io_reg_file; architecture rtl of io_reg_file is signal sreg : std_logic_vector(7 downto 0); signal sph : std_logic_vector(7 downto 0); signal spl : std_logic_vector(7 downto 0); signal rampz : std_logic_vector(7 downto 0); signal sp_int : std_logic_vector(15 downto 0); signal sp_intp : std_logic_vector(15 downto 0); signal sp_intm : std_logic_vector(15 downto 0); signal sp_res : std_logic_vector(15 downto 0); begin sreg_write:process(cp2,ireset) begin if ireset='0' then sreg <= (others => '0'); elsif (cp2='1' and cp2'event) then if (cp2en='1') then -- Clock enable for i in sreg'range loop if (sreg_fl_wr_en(i)='1' or (adr=SREG_Address and iowe='1')) then -- CLOCK ENABLE if iowe='1' then sreg(i) <= dbusout(i); -- FROM THE INTERNAL DATA BUS else sreg(i) <= sreg_fl_in(i); -- FROM ALU FLAGS end if; end if; end loop; end if; end if; end process; sreg_out <= sreg; sp_intp<=(sph&spl)+1; sp_intm<=(sph&spl)-1; sp_res<= sp_intm when sp_ndown_up='0' else sp_intp; spl_write:process(cp2,ireset) begin if ireset='0' then spl <= (others => '0'); elsif (cp2='1' and cp2'event) then if (sp_en='1' or (adr=SPL_Address and iowe='1')) then -- CLOCK ENABLE if iowe='1' then spl <= dbusout; -- FROM THE INTERNAL DATA BUS else spl <= sp_res(7 downto 0); -- FROM SPL BUS end if; end if; end if; end process; spl_out <= spl; sph_write:process(cp2,ireset) begin if ireset='0' then sph <= (others => '0'); elsif (cp2='1' and cp2'event) then if (sp_en='1' or (adr=SPH_Address and iowe='1')) then -- CLOCK ENABLE if iowe='1' then sph <= dbusout; -- FROM THE INTERNAL DATA BUS else sph <= sp_res(15 downto 8); -- FROM SPH BUS end if; end if; end if; end process; sph_out <= sph; rampz_write:process(cp2,ireset) begin if ireset='0' then rampz <= (others => '0'); elsif (cp2='1' and cp2'event) then if (adr=RAMPZ_Address and iowe='1') then -- CLOCK ENABLE rampz <= dbusout; -- FROM THE INTERNAL DATA BUS end if; end if; end process; rampz_out <= rampz; end rtl;
apache-2.0
feb402cfc616923021ba77977c722e25
0.492743
3.509338
false
false
false
false
bertuccio/ARQ
Practica5/ctrl_in.vhd
1
992
---------------------------------------------------------------------------------- -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity ctrl_in is generic(NUM_PERIF: integer:=3); Port ( dir : in STD_LOGIC_VECTOR (31 downto 0); data_read : in STD_LOGIC; perif_en : out STD_LOGIC_VECTOR (NUM_PERIF-1 downto 0)); end ctrl_in; architecture Behavioral of ctrl_in is begin process (data_read,dir) begin if (data_read='1') then if dir <= x"0000FFFF" and dir >= x"00000000" then perif_en<="001"; elsif dir <= x"600000FF" and dir >= x"60000000"then perif_en<="010"; elsif dir <= x"600001FF" and dir >= x"60000100"then perif_en<="100"; else perif_en<="000"; end if; else perif_en<="000"; end if; end process; end Behavioral;
mit
b85c9f286a0de96f2bef7cad96615c5f
0.492944
3.408935
false
false
false
false
GSimas/EEL5105
PROJETO-EEL5105/Projeto/map1.vhd
1
952
library ieee; use ieee.std_logic_1164.all; entity map1 is port ( F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13, F14, F15: out std_logic_vector(31 downto 0) ); end map1; architecture map1_struct of map1 is begin F0 <= "00000000001000000000110000000000"; F1 <= "00000000000000011000110000011000"; F2 <= "00111111000000111100000000011000"; F3 <= "00000000010000000000001100000000"; F4 <= "00000000000000001000001100000000"; F5 <= "00000000000110011000001100001110"; F6 <= "00000000000110111000000000001110"; F7 <= "00000011000000111000000000000010"; F8 <= "00000011000000111000110000000110"; F9 <= "00000000000000111000110000000110"; F10 <= "00000000000010011000000000110000"; F11 <= "00000000011000001000000000110000"; F12 <= "00000000011000000000110000000000"; F13 <= "00000010000000000000110011000000"; F14 <= "00000000010000000000000011011000"; F15 <= "00000000000010000000000000011000"; end map1_struct;
mit
cbf80c6caa62b305b7f274707e667533
0.754202
3.305556
false
false
false
false
fquinto/Wireless_sensor_network
Avnet_UPC/hdl/usb_uart_wrapper.vhd
1
6,688
------------------------------------------------------------------------------- -- usb_uart_wrapper.vhd ------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; library xps_uartlite_v1_01_a; use xps_uartlite_v1_01_a.all; entity usb_uart_wrapper is port ( SPLB_Clk : in std_logic; SPLB_Rst : in std_logic; PLB_ABus : in std_logic_vector(0 to 31); PLB_PAValid : in std_logic; PLB_masterID : in std_logic_vector(0 to 0); PLB_RNW : in std_logic; PLB_BE : in std_logic_vector(0 to 3); PLB_size : in std_logic_vector(0 to 3); PLB_type : in std_logic_vector(0 to 2); PLB_wrDBus : in std_logic_vector(0 to 31); PLB_UABus : in std_logic_vector(0 to 31); PLB_SAValid : in std_logic; PLB_rdPrim : in std_logic; PLB_wrPrim : in std_logic; PLB_abort : in std_logic; PLB_busLock : in std_logic; PLB_MSize : in std_logic_vector(0 to 1); PLB_lockErr : in std_logic; PLB_wrBurst : in std_logic; PLB_rdBurst : in std_logic; PLB_wrPendReq : in std_logic; PLB_rdPendReq : in std_logic; PLB_wrPendPri : in std_logic_vector(0 to 1); PLB_rdPendPri : in std_logic_vector(0 to 1); PLB_reqPri : in std_logic_vector(0 to 1); PLB_TAttribute : in std_logic_vector(0 to 15); Sl_addrAck : out std_logic; Sl_SSize : out std_logic_vector(0 to 1); Sl_wait : out std_logic; Sl_rearbitrate : out std_logic; Sl_wrDAck : out std_logic; Sl_wrComp : out std_logic; Sl_rdDBus : out std_logic_vector(0 to 31); Sl_rdDAck : out std_logic; Sl_rdComp : out std_logic; Sl_MBusy : out std_logic_vector(0 to 1); Sl_MWrErr : out std_logic_vector(0 to 1); Sl_MRdErr : out std_logic_vector(0 to 1); Sl_wrBTerm : out std_logic; Sl_rdWdAddr : out std_logic_vector(0 to 3); Sl_rdBTerm : out std_logic; Sl_MIRQ : out std_logic_vector(0 to 1); RX : in std_logic; TX : out std_logic; Interrupt : out std_logic ); attribute x_core_info : STRING; attribute x_core_info of usb_uart_wrapper : entity is "xps_uartlite_v1_01_a"; end usb_uart_wrapper; architecture STRUCTURE of usb_uart_wrapper is component xps_uartlite is generic ( C_FAMILY : STRING; C_SPLB_CLK_FREQ_HZ : INTEGER; C_BASEADDR : std_logic_vector(0 to 31); C_HIGHADDR : std_logic_vector(0 to 31); C_SPLB_AWIDTH : INTEGER; C_SPLB_DWIDTH : INTEGER; C_SPLB_P2P : INTEGER; C_SPLB_MID_WIDTH : INTEGER; C_SPLB_NUM_MASTERS : INTEGER; C_SPLB_SUPPORT_BURSTS : INTEGER; C_SPLB_NATIVE_DWIDTH : INTEGER; C_BAUDRATE : INTEGER; C_DATA_BITS : INTEGER; C_USE_PARITY : INTEGER; C_ODD_PARITY : INTEGER ); port ( SPLB_Clk : in std_logic; SPLB_Rst : in std_logic; PLB_ABus : in std_logic_vector(0 to 31); PLB_PAValid : in std_logic; PLB_masterID : in std_logic_vector(0 to (C_SPLB_MID_WIDTH-1)); PLB_RNW : in std_logic; PLB_BE : in std_logic_vector(0 to ((C_SPLB_DWIDTH/8)-1)); PLB_size : in std_logic_vector(0 to 3); PLB_type : in std_logic_vector(0 to 2); PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_DWIDTH-1)); PLB_UABus : in std_logic_vector(0 to 31); PLB_SAValid : in std_logic; PLB_rdPrim : in std_logic; PLB_wrPrim : in std_logic; PLB_abort : in std_logic; PLB_busLock : in std_logic; PLB_MSize : in std_logic_vector(0 to 1); PLB_lockErr : in std_logic; PLB_wrBurst : in std_logic; PLB_rdBurst : in std_logic; PLB_wrPendReq : in std_logic; PLB_rdPendReq : in std_logic; PLB_wrPendPri : in std_logic_vector(0 to 1); PLB_rdPendPri : in std_logic_vector(0 to 1); PLB_reqPri : in std_logic_vector(0 to 1); PLB_TAttribute : in std_logic_vector(0 to 15); Sl_addrAck : out std_logic; Sl_SSize : out std_logic_vector(0 to 1); Sl_wait : out std_logic; Sl_rearbitrate : out std_logic; Sl_wrDAck : out std_logic; Sl_wrComp : out std_logic; Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_DWIDTH-1)); Sl_rdDAck : out std_logic; Sl_rdComp : out std_logic; Sl_MBusy : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1)); Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1)); Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1)); Sl_wrBTerm : out std_logic; Sl_rdWdAddr : out std_logic_vector(0 to 3); Sl_rdBTerm : out std_logic; Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1)); RX : in std_logic; TX : out std_logic; Interrupt : out std_logic ); end component; begin USB_UART : xps_uartlite generic map ( C_FAMILY => "spartan3a", C_SPLB_CLK_FREQ_HZ => 66666666, C_BASEADDR => X"84000000", C_HIGHADDR => X"8400ffff", C_SPLB_AWIDTH => 32, C_SPLB_DWIDTH => 32, C_SPLB_P2P => 0, C_SPLB_MID_WIDTH => 1, C_SPLB_NUM_MASTERS => 2, C_SPLB_SUPPORT_BURSTS => 0, C_SPLB_NATIVE_DWIDTH => 32, C_BAUDRATE => 115200, C_DATA_BITS => 8, C_USE_PARITY => 0, C_ODD_PARITY => 0 ) port map ( SPLB_Clk => SPLB_Clk, SPLB_Rst => SPLB_Rst, PLB_ABus => PLB_ABus, PLB_PAValid => PLB_PAValid, PLB_masterID => PLB_masterID, PLB_RNW => PLB_RNW, PLB_BE => PLB_BE, PLB_size => PLB_size, PLB_type => PLB_type, PLB_wrDBus => PLB_wrDBus, PLB_UABus => PLB_UABus, PLB_SAValid => PLB_SAValid, PLB_rdPrim => PLB_rdPrim, PLB_wrPrim => PLB_wrPrim, PLB_abort => PLB_abort, PLB_busLock => PLB_busLock, PLB_MSize => PLB_MSize, PLB_lockErr => PLB_lockErr, PLB_wrBurst => PLB_wrBurst, PLB_rdBurst => PLB_rdBurst, PLB_wrPendReq => PLB_wrPendReq, PLB_rdPendReq => PLB_rdPendReq, PLB_wrPendPri => PLB_wrPendPri, PLB_rdPendPri => PLB_rdPendPri, PLB_reqPri => PLB_reqPri, PLB_TAttribute => PLB_TAttribute, Sl_addrAck => Sl_addrAck, Sl_SSize => Sl_SSize, Sl_wait => Sl_wait, Sl_rearbitrate => Sl_rearbitrate, Sl_wrDAck => Sl_wrDAck, Sl_wrComp => Sl_wrComp, Sl_rdDBus => Sl_rdDBus, Sl_rdDAck => Sl_rdDAck, Sl_rdComp => Sl_rdComp, Sl_MBusy => Sl_MBusy, Sl_MWrErr => Sl_MWrErr, Sl_MRdErr => Sl_MRdErr, Sl_wrBTerm => Sl_wrBTerm, Sl_rdWdAddr => Sl_rdWdAddr, Sl_rdBTerm => Sl_rdBTerm, Sl_MIRQ => Sl_MIRQ, RX => RX, TX => TX, Interrupt => Interrupt ); end architecture STRUCTURE;
mit
8f62ac02793338dd11d8711a8df200d4
0.581489
3.227799
false
false
false
false
tghaefli/ADD
EDK/IVK_Repos/IVK_IPLib/pcores/sg_2d_fir_plbw_v1_02_b/hdl/vhdl/sg_2d_fir_plbw.vhd
3
10,089
------------------------------------------------------------------- -- System Generator version 11.1.00 VHDL source file. -- -- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2007 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; entity plbaddrpref is generic ( C_BASEADDR : std_logic_vector(31 downto 0) := X"80000000"; C_HIGHADDR : std_logic_vector(31 downto 0) := X"8000FFFF"; C_SPLB_DWIDTH : integer range 32 to 128 := 32; C_SPLB_NATIVE_DWIDTH : integer range 32 to 32 := 32 ); port ( addrpref : out std_logic_vector(20-1 downto 0); sl_rddbus : out std_logic_vector(0 to C_SPLB_DWIDTH-1); plb_wrdbus : in std_logic_vector(0 to C_SPLB_DWIDTH-1); sgsl_rddbus : in std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH-1); sgplb_wrdbus : out std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH-1) ); end plbaddrpref; architecture behavior of plbaddrpref is signal sl_rddbus_i : std_logic_vector(0 to C_SPLB_DWIDTH-1); begin addrpref <= C_BASEADDR(32-1 downto 12); ------------------------------------------------------------------------------- -- Mux/Steer data/be's correctly for connect 32-bit slave to 128-bit plb ------------------------------------------------------------------------------- GEN_128_TO_32_SLAVE : if C_SPLB_NATIVE_DWIDTH = 32 and C_SPLB_DWIDTH = 128 generate begin ----------------------------------------------------------------------- -- Map lower rd data to each quarter of the plb slave read bus ----------------------------------------------------------------------- sl_rddbus_i(0 to 31) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1); sl_rddbus_i(32 to 63) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1); sl_rddbus_i(64 to 95) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1); sl_rddbus_i(96 to 127) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1); end generate GEN_128_TO_32_SLAVE; ------------------------------------------------------------------------------- -- Mux/Steer data/be's correctly for connect 32-bit slave to 64-bit plb ------------------------------------------------------------------------------- GEN_64_TO_32_SLAVE : if C_SPLB_NATIVE_DWIDTH = 32 and C_SPLB_DWIDTH = 64 generate begin --------------------------------------------------------------------------- -- Map lower rd data to upper and lower halves of plb slave read bus --------------------------------------------------------------------------- sl_rddbus_i(0 to 31) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1); sl_rddbus_i(32 to 63) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1); end generate GEN_64_TO_32_SLAVE; ------------------------------------------------------------------------------- -- IPIF DWidth = PLB DWidth -- If IPIF Slave Data width is equal to the PLB Bus Data Width -- Then BE and Read Data Bus map directly to eachother. ------------------------------------------------------------------------------- GEN_FOR_EQUAL_SLAVE : if C_SPLB_NATIVE_DWIDTH = C_SPLB_DWIDTH generate sl_rddbus_i <= sgsl_rddbus; end generate GEN_FOR_EQUAL_SLAVE; sl_rddbus <= sl_rddbus_i; sgplb_wrdbus <= plb_wrdbus(0 to C_SPLB_NATIVE_DWIDTH-1); end behavior; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity sg_2d_fir_plbw is generic ( C_BASEADDR: std_logic_vector(31 downto 0) := X"80000000"; C_HIGHADDR: std_logic_vector(31 downto 0) := X"80000FFF"; C_SPLB_AWIDTH: integer := 0; C_SPLB_DWIDTH: integer := 0; C_SPLB_MID_WIDTH: integer := 0; C_SPLB_NATIVE_DWIDTH: integer := 0; C_SPLB_NUM_MASTERS: integer := 0; C_SPLB_SUPPORT_BURSTS: integer := 0 ); port ( active_video_i: in std_logic; hblank_i: in std_logic; hsync_i: in std_logic; plb_abus: in std_logic_vector(0 to 31); plb_pavalid: in std_logic; plb_rnw: in std_logic; plb_wrdbus: in std_logic_vector(0 to C_SPLB_DWIDTH-1); reset: in std_logic; splb_clk: in std_logic; splb_rst: in std_logic; sysgen_clk: in std_logic; vblank_i: in std_logic; video_data_i: in std_logic_vector(0 to 23); vsync_i: in std_logic; active_video_o: out std_logic; hblank_o: out std_logic; hsync_o: out std_logic; sl_addrack: out std_logic; sl_rdcomp: out std_logic; sl_rddack: out std_logic; sl_rddbus: out std_logic_vector(0 to C_SPLB_DWIDTH-1); sl_wait: out std_logic; sl_wrcomp: out std_logic; sl_wrdack: out std_logic; vblank_o: out std_logic; video_data_o: out std_logic_vector(0 to 23); vsync_o: out std_logic ); end sg_2d_fir_plbw; architecture structural of sg_2d_fir_plbw is signal active_video_i_x0: std_logic; signal active_video_o_x0: std_logic; signal clk: std_logic; signal hblank_i_x0: std_logic; signal hblank_o_x0: std_logic; signal hsync_i_x0: std_logic; signal hsync_o_x0: std_logic; signal plb_abus_x0: std_logic_vector(31 downto 0); signal plb_pavalid_x0: std_logic; signal plb_rnw_x0: std_logic; signal plbaddrpref_addrpref_net: std_logic_vector(19 downto 0); signal plbaddrpref_plb_wrdbus_net: std_logic_vector(C_SPLB_DWIDTH-1 downto 0); signal plbaddrpref_sgplb_wrdbus_net: std_logic_vector(31 downto 0); signal plbaddrpref_sgsl_rddbus_net: std_logic_vector(31 downto 0); signal plbaddrpref_sl_rddbus_net: std_logic_vector(C_SPLB_DWIDTH-1 downto 0); signal reset_x0: std_logic; signal sl_addrack_x0: std_logic; signal sl_rdcomp_x0: std_logic; signal sl_rddack_x0: std_logic; signal sl_wait_x0: std_logic; signal sl_wrcomp_x0: std_logic; signal sl_wrdack_x0: std_logic; signal splb_rst_x0: std_logic; signal vblank_i_x0: std_logic; signal vblank_o_x0: std_logic; signal video_data_i_x0: std_logic_vector(23 downto 0); signal video_data_o_x0: std_logic_vector(23 downto 0); signal vsync_i_x0: std_logic; signal vsync_o_x0: std_logic; signal xps_clk: std_logic; begin active_video_i_x0 <= active_video_i; hblank_i_x0 <= hblank_i; hsync_i_x0 <= hsync_i; plb_abus_x0 <= plb_abus; plb_pavalid_x0 <= plb_pavalid; plb_rnw_x0 <= plb_rnw; plbaddrpref_plb_wrdbus_net <= plb_wrdbus; reset_x0 <= reset; xps_clk <= splb_clk; splb_rst_x0 <= splb_rst; clk <= sysgen_clk; vblank_i_x0 <= vblank_i; video_data_i_x0 <= video_data_i; vsync_i_x0 <= vsync_i; active_video_o <= active_video_o_x0; hblank_o <= hblank_o_x0; hsync_o <= hsync_o_x0; sl_addrack <= sl_addrack_x0; sl_rdcomp <= sl_rdcomp_x0; sl_rddack <= sl_rddack_x0; sl_rddbus <= plbaddrpref_sl_rddbus_net; sl_wait <= sl_wait_x0; sl_wrcomp <= sl_wrcomp_x0; sl_wrdack <= sl_wrdack_x0; vblank_o <= vblank_o_x0; video_data_o <= video_data_o_x0; vsync_o <= vsync_o_x0; plbaddrpref_x0: entity work.plbaddrpref generic map ( C_BASEADDR => C_BASEADDR, C_HIGHADDR => C_HIGHADDR, C_SPLB_DWIDTH => C_SPLB_DWIDTH, C_SPLB_NATIVE_DWIDTH => C_SPLB_NATIVE_DWIDTH ) port map ( plb_wrdbus => plbaddrpref_plb_wrdbus_net, sgsl_rddbus => plbaddrpref_sgsl_rddbus_net, addrpref => plbaddrpref_addrpref_net, sgplb_wrdbus => plbaddrpref_sgplb_wrdbus_net, sl_rddbus => plbaddrpref_sl_rddbus_net ); sysgen_dut: entity work.sg_2d_fir_cw port map ( active_video_i => active_video_i_x0, clk => clk, hblank_i => hblank_i_x0, hsync_i => hsync_i_x0, plb_abus => plb_abus_x0, plb_pavalid => plb_pavalid_x0, plb_rnw => plb_rnw_x0, plb_wrdbus => plbaddrpref_sgplb_wrdbus_net, reset => reset_x0, sg_plb_addrpref => plbaddrpref_addrpref_net, splb_rst => splb_rst_x0, vblank_i => vblank_i_x0, video_data_i => video_data_i_x0, vsync_i => vsync_i_x0, xps_clk => xps_clk, active_video_o => active_video_o_x0, hblank_o => hblank_o_x0, hsync_o => hsync_o_x0, sl_addrack => sl_addrack_x0, sl_rdcomp => sl_rdcomp_x0, sl_rddack => sl_rddack_x0, sl_rddbus => plbaddrpref_sgsl_rddbus_net, sl_wait => sl_wait_x0, sl_wrcomp => sl_wrcomp_x0, sl_wrdack => sl_wrdack_x0, vblank_o => vblank_o_x0, video_data_o => video_data_o_x0, vsync_o => vsync_o_x0 ); end structural;
gpl-3.0
23763caa071427248b2679c6fa676c87
0.602637
3.311126
false
false
false
false
Alabamajack/Garfield
FPGA_Design/ip_intern/Rotary_Encoder/tb/rotary_encoder_tb.vhdl
1
2,117
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity rotary_encoder_tb is end entity rotary_encoder_tb; architecture RTL of rotary_encoder_tb is constant core_frequency : natural := 100_000_000; constant counter_width : natural := 32; constant period : time := 10 ns; signal clk : std_logic; signal rst : std_logic; signal clear_counter, enable : std_logic; signal counter : std_logic_vector(counter_width - 1 downto 0); signal rotary_signal : std_logic; signal counter_error : boolean; signal counter_int : integer range 0 to integer'high := 0; begin rot_inst : entity work.rotary_encoder generic map( core_frequency => core_frequency, counter_width => counter_width ) port map( clk => clk, rst => rst, clear_counter => clear_counter, enable => enable, counter => counter, counter_error => counter_error, rotary_signal => rotary_signal ); counter_int <= to_integer(unsigned(counter)); clock_driver : process begin clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2; end process clock_driver; rotary_signal_stim : process is begin rotary_signal <= '0'; wait for 1 ms; for i in 0 to 25 loop rotary_signal <= '1'; wait for 1 ms; rotary_signal <= '0'; wait for 1 ms; end loop; report "End of the first for loop, the counter value is " & integer'image(counter_int) severity note; if counter_int /= 26 then report "The countervalue does not match the right value, the value is " & integer'image(counter_int) severity error; end if; for i in 0 to 10 loop rotary_signal <= '1'; wait for 8 ms; rotary_signal <= '0'; wait for 8 ms; end loop; end process rotary_signal_stim; stim_proc : process is begin rst <= '1'; clear_counter <= '0'; wait for 100 ns; rst <= '0'; enable <= '1'; wait for 75 ms; clear_counter <= '1'; wait for period; clear_counter <= '0'; wait; end process stim_proc; end architecture RTL;
gpl-3.0
272f3b4f35b9090eaf5e99149b7e0e3d
0.620217
3.212443
false
false
false
false
tghaefli/ADD
ISE/FMC/tb_mcu.vhd
1
804
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.mcu_pkg.all; entity tb_mcu is end tb_mcu; architecture TB of tb_mcu is signal rst : std_logic := '1'; signal clk : std_logic := '0'; signal Switch : std_logic_vector(3 downto 0); signal LED : std_logic_vector(7 downto 0); constant SIM_CF : natural := CF/10; -- 50 MHz/10 for simulation begin -- instantiate MUT MUT : entity work.mcu --generic map(CLK_FRQ => SIM_CF) port map( rst => rst, clk => clk, LED => LED, Switch => Switch ); -- generate reset rst <= '1', '0' after 5us; -- clock generation p_clk: process begin wait for 1 sec / SIM_CF/2; clk <= not clk; end process; end TB;
gpl-3.0
896b5be8fba3a2c5900d5d59581454f0
0.558458
3.268293
false
false
false
false
bertuccio/ARQ
Practica4/p4a.vhd
1
3,300
------------------------------------------------------------------------------- -- Memoria cache de correspondencia directa ------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ------------------------------------------------------------------------------- -- Memoria cache de correspondencia directa ------------------------------------------------------------------------------- entity DM_CACHE is generic ( W : integer; -- Ancho bus direcciones L : integer; -- Ancho bus de datos ENTRIES : integer); -- Ancho direcciones de la cache port ( CLK : in std_logic; -- Reloj REQ_C : in std_logic; -- Solicitud de direccion M_WAIT : in std_logic; -- Esperar a la memoria RESET : in std_logic; -- Reset AD : in std_logic_vector(W-1 downto 0); -- Bus direcciones D : in std_logic_vector(L-1 downto 0); -- Bus de datos WAIT_C : out std_logic; -- Esperar a la cache M_REQ : out std_logic; -- Solicitud de acceso Q : out std_logic_vector(L-1 downto 0)); -- Salida de datos end DM_CACHE; architecture PRACTICA of DM_CACHE is --mas uno por el bit de validez type Matriz is array (2**ENTRIES-1 downto 0) of std_logic_vector(W-ENTRIES+L downto 0); type estados is(comparar,espera); signal SRAM: Matriz; signal estado : estados; begin process(RESET, CLK) begin if(RESET = '1') then --Q indeterminada M_REQ<='0'; WAIT_C<='0'; --bit de validez a 0 en cada entrada for i in 0 to 2**ENTRIES-1 loop SRAM(i)(0)<='0'; end loop; estado<=comparar; else if(falling_edge(CLK)) then if(REQ_C='1') then if estado=comparar then --si el tag coincide if(SRAM(conv_integer(AD(ENTRIES-1 downto 0)))(W-ENTRIES+L downto L+1) = AD(W-1 downto ENTRIES)) then --si el bit de validez esta a 1 if SRAM(conv_integer(AD(ENTRIES-1 downto 0)))(0)='1' then --introduce el dato en Q y baja las señales WAIT_C y M_REQ Q<=SRAM(conv_integer(AD(ENTRIES-1 downto 0)))(L downto 1); WAIT_C<='0'; M_REQ<='0'; end if; else --Pone WAIT_C a 1 y M_REQ a 1. De este modo se hace esperar al --microprocesador, y se pide el dato a la memoria estado<=espera; WAIT_C <= '1'; M_REQ <= '1'; end if; else --Mientras M_WAIT esté a 1, espera (no hace nada) if M_WAIT='0' then --Guarda la etiqueta y el dato en la entrada correspondiente, y pone el dato en Q, --bajando las señales WAIT_C y M_REQ SRAM(conv_integer(AD(ENTRIES-1 downto 0)))(0) <= '1'; SRAM(conv_integer(AD(ENTRIES-1 downto 0)))(L downto 1) <= D; SRAM(conv_integer(AD(ENTRIES-1 downto 0)))(W-ENTRIES+L downto L+1) <= AD(W-1 downto ENTRIES); Q <= D; estado <= comparar; WAIT_C <= '0'; M_REQ <= '0'; end if; end if; end if; end if; end if; end process; end PRACTICA;
mit
8425ebc176aea2bf18b1d1c2b800825f
0.501515
3.540773
false
false
false
false
tghaefli/ADD
EDK/IVK_Repos/IVK_IPLib/pcores/sg_2d_fir_plbw_v1_02_b/hdl/vhdl/sg_2d_fir.vhd
1
284,742
-------------------------------------------------------------------------------- -- This file is owned and controlled by Xilinx and must be used solely -- -- for design, simulation, implementation and creation of design files -- -- limited to Xilinx devices or technologies. Use with non-Xilinx -- -- devices or technologies is expressly prohibited and immediately -- -- terminates your license. -- -- -- -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY -- -- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -- -- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE -- -- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS -- -- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY -- -- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY -- -- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY -- -- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- -- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- -- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- -- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- -- PARTICULAR PURPOSE. -- -- -- -- Xilinx products are not intended for use in life support appliances, -- -- devices, or systems. Use in such applications are expressly -- -- prohibited. -- -- -- -- (c) Copyright 1995-2012 Xilinx, Inc. -- -- All rights reserved. -- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -- You must compile the wrapper file addsb_11_0_48bcbc42a6774592.vhd when simulating -- the core, addsb_11_0_48bcbc42a6774592. When compiling the wrapper file, be sure to -- reference the XilinxCoreLib VHDL simulation library. For detailed -- instructions, please refer to the "CORE Generator Help". -- The synthesis directives "translate_off/translate_on" specified -- below are supported by Xilinx, Mentor Graphics and Synplicity -- synthesis tools. Ensure they are correct for your synthesis tool(s). LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- synthesis translate_off LIBRARY XilinxCoreLib; -- synthesis translate_on ENTITY addsb_11_0_48bcbc42a6774592 IS PORT ( a : IN STD_LOGIC_VECTOR(20 DOWNTO 0); b : IN STD_LOGIC_VECTOR(20 DOWNTO 0); clk : IN STD_LOGIC; ce : IN STD_LOGIC; s : OUT STD_LOGIC_VECTOR(20 DOWNTO 0) ); END addsb_11_0_48bcbc42a6774592; ARCHITECTURE addsb_11_0_48bcbc42a6774592_a OF addsb_11_0_48bcbc42a6774592 IS -- synthesis translate_off COMPONENT wrapped_addsb_11_0_48bcbc42a6774592 PORT ( a : IN STD_LOGIC_VECTOR(20 DOWNTO 0); b : IN STD_LOGIC_VECTOR(20 DOWNTO 0); clk : IN STD_LOGIC; ce : IN STD_LOGIC; s : OUT STD_LOGIC_VECTOR(20 DOWNTO 0) ); END COMPONENT; -- Configuration specification FOR ALL : wrapped_addsb_11_0_48bcbc42a6774592 USE ENTITY XilinxCoreLib.c_addsub_v11_0(behavioral) GENERIC MAP ( c_a_type => 0, c_a_width => 21, c_add_mode => 0, c_ainit_val => "0", c_b_constant => 0, c_b_type => 0, c_b_value => "000000000000000000000", c_b_width => 21, c_borrow_low => 1, c_bypass_low => 0, c_ce_overrides_bypass => 1, c_ce_overrides_sclr => 0, c_has_bypass => 0, c_has_c_in => 0, c_has_c_out => 0, c_has_ce => 1, c_has_sclr => 0, c_has_sinit => 0, c_has_sset => 0, c_implementation => 0, c_latency => 1, c_out_width => 21, c_sclr_overrides_sset => 0, c_sinit_val => "0", c_verbosity => 0, c_xdevicefamily => "spartan6" ); -- synthesis translate_on BEGIN -- synthesis translate_off U0 : wrapped_addsb_11_0_48bcbc42a6774592 PORT MAP ( a => a, b => b, clk => clk, ce => ce, s => s ); -- synthesis translate_on END addsb_11_0_48bcbc42a6774592_a; -------------------------------------------------------------------------------- -- This file is owned and controlled by Xilinx and must be used solely -- -- for design, simulation, implementation and creation of design files -- -- limited to Xilinx devices or technologies. Use with non-Xilinx -- -- devices or technologies is expressly prohibited and immediately -- -- terminates your license. -- -- -- -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY -- -- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -- -- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE -- -- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS -- -- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY -- -- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY -- -- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY -- -- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- -- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- -- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- -- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- -- PARTICULAR PURPOSE. -- -- -- -- Xilinx products are not intended for use in life support appliances, -- -- devices, or systems. Use in such applications are expressly -- -- prohibited. -- -- -- -- (c) Copyright 1995-2012 Xilinx, Inc. -- -- All rights reserved. -- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -- You must compile the wrapper file addsb_11_0_da33f2d4b3b54185.vhd when simulating -- the core, addsb_11_0_da33f2d4b3b54185. When compiling the wrapper file, be sure to -- reference the XilinxCoreLib VHDL simulation library. For detailed -- instructions, please refer to the "CORE Generator Help". -- The synthesis directives "translate_off/translate_on" specified -- below are supported by Xilinx, Mentor Graphics and Synplicity -- synthesis tools. Ensure they are correct for your synthesis tool(s). LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- synthesis translate_off LIBRARY XilinxCoreLib; -- synthesis translate_on ENTITY addsb_11_0_da33f2d4b3b54185 IS PORT ( a : IN STD_LOGIC_VECTOR(19 DOWNTO 0); b : IN STD_LOGIC_VECTOR(19 DOWNTO 0); clk : IN STD_LOGIC; ce : IN STD_LOGIC; s : OUT STD_LOGIC_VECTOR(19 DOWNTO 0) ); END addsb_11_0_da33f2d4b3b54185; ARCHITECTURE addsb_11_0_da33f2d4b3b54185_a OF addsb_11_0_da33f2d4b3b54185 IS -- synthesis translate_off COMPONENT wrapped_addsb_11_0_da33f2d4b3b54185 PORT ( a : IN STD_LOGIC_VECTOR(19 DOWNTO 0); b : IN STD_LOGIC_VECTOR(19 DOWNTO 0); clk : IN STD_LOGIC; ce : IN STD_LOGIC; s : OUT STD_LOGIC_VECTOR(19 DOWNTO 0) ); END COMPONENT; -- Configuration specification FOR ALL : wrapped_addsb_11_0_da33f2d4b3b54185 USE ENTITY XilinxCoreLib.c_addsub_v11_0(behavioral) GENERIC MAP ( c_a_type => 0, c_a_width => 20, c_add_mode => 0, c_ainit_val => "0", c_b_constant => 0, c_b_type => 0, c_b_value => "00000000000000000000", c_b_width => 20, c_borrow_low => 1, c_bypass_low => 0, c_ce_overrides_bypass => 1, c_ce_overrides_sclr => 0, c_has_bypass => 0, c_has_c_in => 0, c_has_c_out => 0, c_has_ce => 1, c_has_sclr => 0, c_has_sinit => 0, c_has_sset => 0, c_implementation => 0, c_latency => 1, c_out_width => 20, c_sclr_overrides_sset => 0, c_sinit_val => "0", c_verbosity => 0, c_xdevicefamily => "spartan6" ); -- synthesis translate_on BEGIN -- synthesis translate_off U0 : wrapped_addsb_11_0_da33f2d4b3b54185 PORT MAP ( a => a, b => b, clk => clk, ce => ce, s => s ); -- synthesis translate_on END addsb_11_0_da33f2d4b3b54185_a; -------------------------------------------------------------------------------- -- This file is owned and controlled by Xilinx and must be used solely -- -- for design, simulation, implementation and creation of design files -- -- limited to Xilinx devices or technologies. Use with non-Xilinx -- -- devices or technologies is expressly prohibited and immediately -- -- terminates your license. -- -- -- -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY -- -- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -- -- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE -- -- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS -- -- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY -- -- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY -- -- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY -- -- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- -- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- -- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- -- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- -- PARTICULAR PURPOSE. -- -- -- -- Xilinx products are not intended for use in life support appliances, -- -- devices, or systems. Use in such applications are expressly -- -- prohibited. -- -- -- -- (c) Copyright 1995-2012 Xilinx, Inc. -- -- All rights reserved. -- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -- You must compile the wrapper file addsb_11_0_e7b4231f2ca96446.vhd when simulating -- the core, addsb_11_0_e7b4231f2ca96446. When compiling the wrapper file, be sure to -- reference the XilinxCoreLib VHDL simulation library. For detailed -- instructions, please refer to the "CORE Generator Help". -- The synthesis directives "translate_off/translate_on" specified -- below are supported by Xilinx, Mentor Graphics and Synplicity -- synthesis tools. Ensure they are correct for your synthesis tool(s). LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- synthesis translate_off LIBRARY XilinxCoreLib; -- synthesis translate_on ENTITY addsb_11_0_e7b4231f2ca96446 IS PORT ( a : IN STD_LOGIC_VECTOR(21 DOWNTO 0); b : IN STD_LOGIC_VECTOR(21 DOWNTO 0); clk : IN STD_LOGIC; ce : IN STD_LOGIC; s : OUT STD_LOGIC_VECTOR(21 DOWNTO 0) ); END addsb_11_0_e7b4231f2ca96446; ARCHITECTURE addsb_11_0_e7b4231f2ca96446_a OF addsb_11_0_e7b4231f2ca96446 IS -- synthesis translate_off COMPONENT wrapped_addsb_11_0_e7b4231f2ca96446 PORT ( a : IN STD_LOGIC_VECTOR(21 DOWNTO 0); b : IN STD_LOGIC_VECTOR(21 DOWNTO 0); clk : IN STD_LOGIC; ce : IN STD_LOGIC; s : OUT STD_LOGIC_VECTOR(21 DOWNTO 0) ); END COMPONENT; -- Configuration specification FOR ALL : wrapped_addsb_11_0_e7b4231f2ca96446 USE ENTITY XilinxCoreLib.c_addsub_v11_0(behavioral) GENERIC MAP ( c_a_type => 0, c_a_width => 22, c_add_mode => 0, c_ainit_val => "0", c_b_constant => 0, c_b_type => 0, c_b_value => "0000000000000000000000", c_b_width => 22, c_borrow_low => 1, c_bypass_low => 0, c_ce_overrides_bypass => 1, c_ce_overrides_sclr => 0, c_has_bypass => 0, c_has_c_in => 0, c_has_c_out => 0, c_has_ce => 1, c_has_sclr => 0, c_has_sinit => 0, c_has_sset => 0, c_implementation => 0, c_latency => 1, c_out_width => 22, c_sclr_overrides_sset => 0, c_sinit_val => "0", c_verbosity => 0, c_xdevicefamily => "spartan6" ); -- synthesis translate_on BEGIN -- synthesis translate_off U0 : wrapped_addsb_11_0_e7b4231f2ca96446 PORT MAP ( a => a, b => b, clk => clk, ce => ce, s => s ); -- synthesis translate_on END addsb_11_0_e7b4231f2ca96446_a; -------------------------------------------------------------------------------- -- This file is owned and controlled by Xilinx and must be used solely -- -- for design, simulation, implementation and creation of design files -- -- limited to Xilinx devices or technologies. Use with non-Xilinx -- -- devices or technologies is expressly prohibited and immediately -- -- terminates your license. -- -- -- -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY -- -- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -- -- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE -- -- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS -- -- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY -- -- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY -- -- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY -- -- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- -- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- -- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- -- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- -- PARTICULAR PURPOSE. -- -- -- -- Xilinx products are not intended for use in life support appliances, -- -- devices, or systems. Use in such applications are expressly -- -- prohibited. -- -- -- -- (c) Copyright 1995-2012 Xilinx, Inc. -- -- All rights reserved. -- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -- You must compile the wrapper file bmg_62_05852d43925e39b8.vhd when simulating -- the core, bmg_62_05852d43925e39b8. When compiling the wrapper file, be sure to -- reference the XilinxCoreLib VHDL simulation library. For detailed -- instructions, please refer to the "CORE Generator Help". -- The synthesis directives "translate_off/translate_on" specified -- below are supported by Xilinx, Mentor Graphics and Synplicity -- synthesis tools. Ensure they are correct for your synthesis tool(s). LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- synthesis translate_off LIBRARY XilinxCoreLib; -- synthesis translate_on ENTITY bmg_62_05852d43925e39b8 IS PORT ( clka : IN STD_LOGIC; ena : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(4 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(4 DOWNTO 0) ); END bmg_62_05852d43925e39b8; ARCHITECTURE bmg_62_05852d43925e39b8_a OF bmg_62_05852d43925e39b8 IS -- synthesis translate_off COMPONENT wrapped_bmg_62_05852d43925e39b8 PORT ( clka : IN STD_LOGIC; ena : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(4 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(4 DOWNTO 0) ); END COMPONENT; -- Configuration specification FOR ALL : wrapped_bmg_62_05852d43925e39b8 USE ENTITY XilinxCoreLib.blk_mem_gen_v6_2(behavioral) GENERIC MAP ( c_addra_width => 12, c_addrb_width => 12, c_algorithm => 0, c_axi_id_width => 4, c_axi_slave_type => 0, c_axi_type => 1, c_byte_size => 9, c_common_clk => 0, c_default_data => "0", c_disable_warn_bhv_coll => 0, c_disable_warn_bhv_range => 0, c_family => "spartan6", c_has_axi_id => 0, c_has_ena => 1, c_has_enb => 0, c_has_injecterr => 0, c_has_mem_output_regs_a => 0, c_has_mem_output_regs_b => 0, c_has_mux_output_regs_a => 0, c_has_mux_output_regs_b => 0, c_has_regcea => 0, c_has_regceb => 0, c_has_rsta => 0, c_has_rstb => 0, c_has_softecc_input_regs_a => 0, c_has_softecc_output_regs_b => 0, c_init_file_name => "bmg_62_05852d43925e39b8.mif", c_inita_val => "0", c_initb_val => "0", c_interface_type => 0, c_load_init_file => 1, c_mem_type => 0, c_mux_pipeline_stages => 0, c_prim_type => 2, c_read_depth_a => 4096, c_read_depth_b => 4096, c_read_width_a => 5, c_read_width_b => 5, c_rst_priority_a => "CE", c_rst_priority_b => "CE", c_rst_type => "SYNC", c_rstram_a => 0, c_rstram_b => 0, c_sim_collision_check => "ALL", c_use_byte_wea => 0, c_use_byte_web => 0, c_use_default_data => 0, c_use_ecc => 0, c_use_softecc => 0, c_wea_width => 1, c_web_width => 1, c_write_depth_a => 4096, c_write_depth_b => 4096, c_write_mode_a => "READ_FIRST", c_write_mode_b => "WRITE_FIRST", c_write_width_a => 5, c_write_width_b => 5, c_xdevicefamily => "spartan6" ); -- synthesis translate_on BEGIN -- synthesis translate_off U0 : wrapped_bmg_62_05852d43925e39b8 PORT MAP ( clka => clka, ena => ena, wea => wea, addra => addra, dina => dina, douta => douta ); -- synthesis translate_on END bmg_62_05852d43925e39b8_a; -------------------------------------------------------------------------------- -- This file is owned and controlled by Xilinx and must be used solely -- -- for design, simulation, implementation and creation of design files -- -- limited to Xilinx devices or technologies. Use with non-Xilinx -- -- devices or technologies is expressly prohibited and immediately -- -- terminates your license. -- -- -- -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY -- -- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -- -- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE -- -- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS -- -- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY -- -- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY -- -- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY -- -- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- -- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- -- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- -- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- -- PARTICULAR PURPOSE. -- -- -- -- Xilinx products are not intended for use in life support appliances, -- -- devices, or systems. Use in such applications are expressly -- -- prohibited. -- -- -- -- (c) Copyright 1995-2012 Xilinx, Inc. -- -- All rights reserved. -- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -- You must compile the wrapper file bmg_62_54b11b852dca329b.vhd when simulating -- the core, bmg_62_54b11b852dca329b. When compiling the wrapper file, be sure to -- reference the XilinxCoreLib VHDL simulation library. For detailed -- instructions, please refer to the "CORE Generator Help". -- The synthesis directives "translate_off/translate_on" specified -- below are supported by Xilinx, Mentor Graphics and Synplicity -- synthesis tools. Ensure they are correct for your synthesis tool(s). LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- synthesis translate_off LIBRARY XilinxCoreLib; -- synthesis translate_on ENTITY bmg_62_54b11b852dca329b IS PORT ( clka : IN STD_LOGIC; ena : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END bmg_62_54b11b852dca329b; ARCHITECTURE bmg_62_54b11b852dca329b_a OF bmg_62_54b11b852dca329b IS -- synthesis translate_off COMPONENT wrapped_bmg_62_54b11b852dca329b PORT ( clka : IN STD_LOGIC; ena : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END COMPONENT; -- Configuration specification FOR ALL : wrapped_bmg_62_54b11b852dca329b USE ENTITY XilinxCoreLib.blk_mem_gen_v6_2(behavioral) GENERIC MAP ( c_addra_width => 12, c_addrb_width => 12, c_algorithm => 0, c_axi_id_width => 4, c_axi_slave_type => 0, c_axi_type => 1, c_byte_size => 9, c_common_clk => 0, c_default_data => "0", c_disable_warn_bhv_coll => 0, c_disable_warn_bhv_range => 0, c_family => "spartan6", c_has_axi_id => 0, c_has_ena => 1, c_has_enb => 0, c_has_injecterr => 0, c_has_mem_output_regs_a => 0, c_has_mem_output_regs_b => 0, c_has_mux_output_regs_a => 0, c_has_mux_output_regs_b => 0, c_has_regcea => 0, c_has_regceb => 0, c_has_rsta => 0, c_has_rstb => 0, c_has_softecc_input_regs_a => 0, c_has_softecc_output_regs_b => 0, c_init_file_name => "bmg_62_54b11b852dca329b.mif", c_inita_val => "0", c_initb_val => "0", c_interface_type => 0, c_load_init_file => 1, c_mem_type => 0, c_mux_pipeline_stages => 0, c_prim_type => 2, c_read_depth_a => 4096, c_read_depth_b => 4096, c_read_width_a => 8, c_read_width_b => 8, c_rst_priority_a => "CE", c_rst_priority_b => "CE", c_rst_type => "SYNC", c_rstram_a => 0, c_rstram_b => 0, c_sim_collision_check => "ALL", c_use_byte_wea => 0, c_use_byte_web => 0, c_use_default_data => 0, c_use_ecc => 0, c_use_softecc => 0, c_wea_width => 1, c_web_width => 1, c_write_depth_a => 4096, c_write_depth_b => 4096, c_write_mode_a => "READ_FIRST", c_write_mode_b => "WRITE_FIRST", c_write_width_a => 8, c_write_width_b => 8, c_xdevicefamily => "spartan6" ); -- synthesis translate_on BEGIN -- synthesis translate_off U0 : wrapped_bmg_62_54b11b852dca329b PORT MAP ( clka => clka, ena => ena, wea => wea, addra => addra, dina => dina, douta => douta ); -- synthesis translate_on END bmg_62_54b11b852dca329b_a; -------------------------------------------------------------------------------- -- This file is owned and controlled by Xilinx and must be used solely -- -- for design, simulation, implementation and creation of design files -- -- limited to Xilinx devices or technologies. Use with non-Xilinx -- -- devices or technologies is expressly prohibited and immediately -- -- terminates your license. -- -- -- -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY -- -- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -- -- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE -- -- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS -- -- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY -- -- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY -- -- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY -- -- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- -- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- -- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- -- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- -- PARTICULAR PURPOSE. -- -- -- -- Xilinx products are not intended for use in life support appliances, -- -- devices, or systems. Use in such applications are expressly -- -- prohibited. -- -- -- -- (c) Copyright 1995-2012 Xilinx, Inc. -- -- All rights reserved. -- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -- You must compile the wrapper file cntr_11_0_862f833518f4973a.vhd when simulating -- the core, cntr_11_0_862f833518f4973a. When compiling the wrapper file, be sure to -- reference the XilinxCoreLib VHDL simulation library. For detailed -- instructions, please refer to the "CORE Generator Help". -- The synthesis directives "translate_off/translate_on" specified -- below are supported by Xilinx, Mentor Graphics and Synplicity -- synthesis tools. Ensure they are correct for your synthesis tool(s). LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- synthesis translate_off LIBRARY XilinxCoreLib; -- synthesis translate_on ENTITY cntr_11_0_862f833518f4973a IS PORT ( clk : IN STD_LOGIC; ce : IN STD_LOGIC; sinit : IN STD_LOGIC; q : OUT STD_LOGIC_VECTOR(4 DOWNTO 0) ); END cntr_11_0_862f833518f4973a; ARCHITECTURE cntr_11_0_862f833518f4973a_a OF cntr_11_0_862f833518f4973a IS -- synthesis translate_off COMPONENT wrapped_cntr_11_0_862f833518f4973a PORT ( clk : IN STD_LOGIC; ce : IN STD_LOGIC; sinit : IN STD_LOGIC; q : OUT STD_LOGIC_VECTOR(4 DOWNTO 0) ); END COMPONENT; -- Configuration specification FOR ALL : wrapped_cntr_11_0_862f833518f4973a USE ENTITY XilinxCoreLib.c_counter_binary_v11_0(behavioral) GENERIC MAP ( c_ainit_val => "0", c_ce_overrides_sync => 0, c_count_by => "1", c_count_mode => 0, c_count_to => "1", c_fb_latency => 0, c_has_ce => 1, c_has_load => 0, c_has_sclr => 0, c_has_sinit => 1, c_has_sset => 0, c_has_thresh0 => 0, c_implementation => 0, c_latency => 1, c_load_low => 0, c_restrict_count => 0, c_sclr_overrides_sset => 1, c_sinit_val => "0", c_thresh0_value => "1", c_verbosity => 0, c_width => 5, c_xdevicefamily => "spartan6" ); -- synthesis translate_on BEGIN -- synthesis translate_off U0 : wrapped_cntr_11_0_862f833518f4973a PORT MAP ( clk => clk, ce => ce, sinit => sinit, q => q ); -- synthesis translate_on END cntr_11_0_862f833518f4973a_a; -------------------------------------------------------------------------------- -- This file is owned and controlled by Xilinx and must be used solely -- -- for design, simulation, implementation and creation of design files -- -- limited to Xilinx devices or technologies. Use with non-Xilinx -- -- devices or technologies is expressly prohibited and immediately -- -- terminates your license. -- -- -- -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY -- -- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -- -- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE -- -- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS -- -- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY -- -- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY -- -- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY -- -- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- -- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- -- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- -- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- -- PARTICULAR PURPOSE. -- -- -- -- Xilinx products are not intended for use in life support appliances, -- -- devices, or systems. Use in such applications are expressly -- -- prohibited. -- -- -- -- (c) Copyright 1995-2012 Xilinx, Inc. -- -- All rights reserved. -- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -- You must compile the wrapper file cntr_11_0_e859c6662c373192.vhd when simulating -- the core, cntr_11_0_e859c6662c373192. When compiling the wrapper file, be sure to -- reference the XilinxCoreLib VHDL simulation library. For detailed -- instructions, please refer to the "CORE Generator Help". -- The synthesis directives "translate_off/translate_on" specified -- below are supported by Xilinx, Mentor Graphics and Synplicity -- synthesis tools. Ensure they are correct for your synthesis tool(s). LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- synthesis translate_off LIBRARY XilinxCoreLib; -- synthesis translate_on ENTITY cntr_11_0_e859c6662c373192 IS PORT ( clk : IN STD_LOGIC; ce : IN STD_LOGIC; sinit : IN STD_LOGIC; q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) ); END cntr_11_0_e859c6662c373192; ARCHITECTURE cntr_11_0_e859c6662c373192_a OF cntr_11_0_e859c6662c373192 IS -- synthesis translate_off COMPONENT wrapped_cntr_11_0_e859c6662c373192 PORT ( clk : IN STD_LOGIC; ce : IN STD_LOGIC; sinit : IN STD_LOGIC; q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) ); END COMPONENT; -- Configuration specification FOR ALL : wrapped_cntr_11_0_e859c6662c373192 USE ENTITY XilinxCoreLib.c_counter_binary_v11_0(behavioral) GENERIC MAP ( c_ainit_val => "0", c_ce_overrides_sync => 0, c_count_by => "1", c_count_mode => 0, c_count_to => "1", c_fb_latency => 0, c_has_ce => 1, c_has_load => 0, c_has_sclr => 0, c_has_sinit => 1, c_has_sset => 0, c_has_thresh0 => 0, c_implementation => 0, c_latency => 1, c_load_low => 0, c_restrict_count => 0, c_sclr_overrides_sset => 1, c_sinit_val => "0", c_thresh0_value => "1", c_verbosity => 0, c_width => 3, c_xdevicefamily => "spartan6" ); -- synthesis translate_on BEGIN -- synthesis translate_off U0 : wrapped_cntr_11_0_e859c6662c373192 PORT MAP ( clk => clk, ce => ce, sinit => sinit, q => q ); -- synthesis translate_on END cntr_11_0_e859c6662c373192_a; -------------------------------------------------------------------------------- -- (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. -- -- -- -- This file contains confidential and proprietary information -- -- of Xilinx, Inc. and is protected under U.S. and -- -- international copyright and other intellectual property -- -- laws. -- -- -- -- DISCLAIMER -- -- This disclaimer is not a license and does not grant any -- -- rights to the materials distributed herewith. Except as -- -- otherwise provided in a valid license issued to you by -- -- Xilinx, and to the maximum extent permitted by applicable -- -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- -- (2) Xilinx shall not be liable (whether in contract or tort, -- -- including negligence, or under any other theory of -- -- liability) for any loss or damage of any kind or nature -- -- related to, arising under or in connection with these -- -- materials, including for any direct, or any indirect, -- -- special, incidental, or consequential loss or damage -- -- (including loss of data, profits, goodwill, or any type of -- -- loss or damage suffered as a result of any action brought -- -- by a third party) even if such damage or loss was -- -- reasonably foreseeable or Xilinx had been advised of the -- -- possibility of the same. -- -- -- -- CRITICAL APPLICATIONS -- -- Xilinx products are not designed or intended to be fail- -- -- safe, or for use in any application requiring fail-safe -- -- performance, such as life-support or safety devices or -- -- systems, Class III medical devices, nuclear facilities, -- -- applications related to the deployment of airbags, or any -- -- other applications that could lead to death, personal -- -- injury, or severe property or environmental damage -- -- (individually and collectively, "Critical -- -- Applications"). Customer assumes the sole risk and -- -- liability of any use of Xilinx products in Critical -- -- Applications, subject only to applicable laws and -- -- regulations governing limitations on product liability. -- -- -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- -- PART OF THIS FILE AT ALL TIMES. -- -------------------------------------------------------------------------------- -- Generated from component ID: xilinx.com:ip:fir_compiler:5.0 -- You must compile the wrapper file fr_cmplr_v5_0_70a7f64f38920660.vhd when simulating -- the core, fr_cmplr_v5_0_70a7f64f38920660. When compiling the wrapper file, be sure to -- reference the XilinxCoreLib VHDL simulation library. For detailed -- instructions, please refer to the "CORE Generator Help". -- The synthesis directives "translate_off/translate_on" specified -- below are supported by Xilinx, Mentor Graphics and Synplicity -- synthesis tools. Ensure they are correct for your synthesis tool(s). LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- synthesis translate_off Library XilinxCoreLib; -- synthesis translate_on ENTITY fr_cmplr_v5_0_70a7f64f38920660 IS port ( clk: in std_logic; ce: in std_logic; nd: in std_logic; coef_ld: in std_logic; coef_we: in std_logic; coef_din: in std_logic_vector(6 downto 0); rfd: out std_logic; rdy: out std_logic; din: in std_logic_vector(7 downto 0); dout: out std_logic_vector(18 downto 0)); END fr_cmplr_v5_0_70a7f64f38920660; ARCHITECTURE fr_cmplr_v5_0_70a7f64f38920660_a OF fr_cmplr_v5_0_70a7f64f38920660 IS -- synthesis translate_off component wrapped_fr_cmplr_v5_0_70a7f64f38920660 port ( clk: in std_logic; ce: in std_logic; nd: in std_logic; coef_ld: in std_logic; coef_we: in std_logic; coef_din: in std_logic_vector(6 downto 0); rfd: out std_logic; rdy: out std_logic; din: in std_logic_vector(7 downto 0); dout: out std_logic_vector(18 downto 0)); end component; -- Configuration specification for all : wrapped_fr_cmplr_v5_0_70a7f64f38920660 use entity XilinxCoreLib.fir_compiler_v5_0(behavioral) generic map( coef_width => 7, c_has_sclr => 0, datapath_memtype => 0, c_component_name => "fr_cmplr_v5_0_70a7f64f38920660", c_family => "spartan6", round_mode => 0, output_width => 19, sclr_deterministic => 0, col_config => "5", coef_memtype => 0, clock_freq => 1, symmetry => 0, col_pipe_len => 4, c_latency => 11, chan_sel_width => 1, c_xdevicefamily => "spartan6", c_has_nd => 1, allow_approx => 0, num_channels => 1, data_width => 8, filter_sel_width => 1, sample_freq => 1, coef_reload => 1, neg_symmetry => 0, filter_type => 0, data_type => 1, accum_width => 19, rate_change_type => 0, ipbuff_memtype => 0, c_optimization => 1, output_reg => 1, data_memtype => 0, c_has_data_valid => 0, decim_rate => 1, coef_type => 0, filter_arch => 1, interp_rate => 1, num_taps => 5, c_mem_init_file => "fr_cmplr_v5_0_70a7f64f38920660.mif", zero_packing_factor => 1, num_paths => 1, num_filts => 1, col_mode => 0, c_has_ce => 1, chan_in_adv => 0, opbuff_memtype => 0, odd_symmetry => 1); -- synthesis translate_on BEGIN -- synthesis translate_off U0 : wrapped_fr_cmplr_v5_0_70a7f64f38920660 port map ( clk => clk, ce => ce, nd => nd, coef_ld => coef_ld, coef_we => coef_we, coef_din => coef_din, rfd => rfd, rdy => rdy, din => din, dout => dout); -- synthesis translate_on END fr_cmplr_v5_0_70a7f64f38920660_a; -------------------------------------------------------------------------------- -- This file is owned and controlled by Xilinx and must be used solely -- -- for design, simulation, implementation and creation of design files -- -- limited to Xilinx devices or technologies. Use with non-Xilinx -- -- devices or technologies is expressly prohibited and immediately -- -- terminates your license. -- -- -- -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY -- -- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -- -- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE -- -- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS -- -- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY -- -- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY -- -- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY -- -- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- -- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- -- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- -- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- -- PARTICULAR PURPOSE. -- -- -- -- Xilinx products are not intended for use in life support appliances, -- -- devices, or systems. Use in such applications are expressly -- -- prohibited. -- -- -- -- (c) Copyright 1995-2012 Xilinx, Inc. -- -- All rights reserved. -- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -- You must compile the wrapper file mult_11_2_fe92ad55b7635191.vhd when simulating -- the core, mult_11_2_fe92ad55b7635191. When compiling the wrapper file, be sure to -- reference the XilinxCoreLib VHDL simulation library. For detailed -- instructions, please refer to the "CORE Generator Help". -- The synthesis directives "translate_off/translate_on" specified -- below are supported by Xilinx, Mentor Graphics and Synplicity -- synthesis tools. Ensure they are correct for your synthesis tool(s). LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- synthesis translate_off LIBRARY XilinxCoreLib; -- synthesis translate_on ENTITY mult_11_2_fe92ad55b7635191 IS PORT ( clk : IN STD_LOGIC; a : IN STD_LOGIC_VECTOR(22 DOWNTO 0); b : IN STD_LOGIC_VECTOR(19 DOWNTO 0); ce : IN STD_LOGIC; sclr : IN STD_LOGIC; p : OUT STD_LOGIC_VECTOR(42 DOWNTO 0) ); END mult_11_2_fe92ad55b7635191; ARCHITECTURE mult_11_2_fe92ad55b7635191_a OF mult_11_2_fe92ad55b7635191 IS -- synthesis translate_off COMPONENT wrapped_mult_11_2_fe92ad55b7635191 PORT ( clk : IN STD_LOGIC; a : IN STD_LOGIC_VECTOR(22 DOWNTO 0); b : IN STD_LOGIC_VECTOR(19 DOWNTO 0); ce : IN STD_LOGIC; sclr : IN STD_LOGIC; p : OUT STD_LOGIC_VECTOR(42 DOWNTO 0) ); END COMPONENT; -- Configuration specification FOR ALL : wrapped_mult_11_2_fe92ad55b7635191 USE ENTITY XilinxCoreLib.mult_gen_v11_2(behavioral) GENERIC MAP ( c_a_type => 0, c_a_width => 23, c_b_type => 1, c_b_value => "10000001", c_b_width => 20, c_ccm_imp => 0, c_ce_overrides_sclr => 1, c_has_ce => 1, c_has_sclr => 1, c_has_zero_detect => 0, c_latency => 4, c_model_type => 0, c_mult_type => 1, c_optimize_goal => 1, c_out_high => 42, c_out_low => 0, c_round_output => 0, c_round_pt => 0, c_verbosity => 0, c_xdevicefamily => "spartan6" ); -- synthesis translate_on BEGIN -- synthesis translate_off U0 : wrapped_mult_11_2_fe92ad55b7635191 PORT MAP ( clk => clk, a => a, b => b, ce => ce, sclr => sclr, p => p ); -- synthesis translate_on END mult_11_2_fe92ad55b7635191_a; ------------------------------------------------------------------- -- System Generator version 13.2 VHDL source file. -- -- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; package conv_pkg is constant simulating : boolean := false -- synopsys translate_off or true -- synopsys translate_on ; constant xlUnsigned : integer := 1; constant xlSigned : integer := 2; constant xlFloat : integer := 3; constant xlWrap : integer := 1; constant xlSaturate : integer := 2; constant xlTruncate : integer := 1; constant xlRound : integer := 2; constant xlRoundBanker : integer := 3; constant xlAddMode : integer := 1; constant xlSubMode : integer := 2; attribute black_box : boolean; attribute syn_black_box : boolean; attribute fpga_dont_touch: string; attribute box_type : string; attribute keep : string; attribute syn_keep : boolean; function std_logic_vector_to_unsigned(inp : std_logic_vector) return unsigned; function unsigned_to_std_logic_vector(inp : unsigned) return std_logic_vector; function std_logic_vector_to_signed(inp : std_logic_vector) return signed; function signed_to_std_logic_vector(inp : signed) return std_logic_vector; function unsigned_to_signed(inp : unsigned) return signed; function signed_to_unsigned(inp : signed) return unsigned; function pos(inp : std_logic_vector; arith : INTEGER) return boolean; function all_same(inp: std_logic_vector) return boolean; function all_zeros(inp: std_logic_vector) return boolean; function is_point_five(inp: std_logic_vector) return boolean; function all_ones(inp: std_logic_vector) return boolean; function convert_type (inp : std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith, quantization, overflow : INTEGER) return std_logic_vector; function cast (inp : std_logic_vector; old_bin_pt, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector; function shift_division_result(quotient, fraction: std_logic_vector; fraction_width, shift_value, shift_dir: INTEGER) return std_logic_vector; function shift_op (inp: std_logic_vector; result_width, shift_value, shift_dir: INTEGER) return std_logic_vector; function vec_slice (inp : std_logic_vector; upper, lower : INTEGER) return std_logic_vector; function s2u_slice (inp : signed; upper, lower : INTEGER) return unsigned; function u2u_slice (inp : unsigned; upper, lower : INTEGER) return unsigned; function s2s_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER) return signed; function u2s_cast (inp : unsigned; old_bin_pt, new_width, new_bin_pt : INTEGER) return signed; function s2u_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER) return unsigned; function u2u_cast (inp : unsigned; old_bin_pt, new_width, new_bin_pt : INTEGER) return unsigned; function u2v_cast (inp : unsigned; old_bin_pt, new_width, new_bin_pt : INTEGER) return std_logic_vector; function s2v_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER) return std_logic_vector; function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector; function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector; function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector; function max_signed(width : INTEGER) return std_logic_vector; function min_signed(width : INTEGER) return std_logic_vector; function saturation_arith(inp: std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector; function wrap_arith(inp: std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector; function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER; function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER) return INTEGER; function sign_ext(inp : std_logic_vector; new_width : INTEGER) return std_logic_vector; function zero_ext(inp : std_logic_vector; new_width : INTEGER) return std_logic_vector; function zero_ext(inp : std_logic; new_width : INTEGER) return std_logic_vector; function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER) return std_logic_vector; function align_input(inp : std_logic_vector; old_width, delta, new_arith, new_width: INTEGER) return std_logic_vector; function pad_LSB(inp : std_logic_vector; new_width: integer) return std_logic_vector; function pad_LSB(inp : std_logic_vector; new_width, arith : integer) return std_logic_vector; function max(L, R: INTEGER) return INTEGER; function min(L, R: INTEGER) return INTEGER; function "="(left,right: STRING) return boolean; function boolean_to_signed (inp : boolean; width: integer) return signed; function boolean_to_unsigned (inp : boolean; width: integer) return unsigned; function boolean_to_vector (inp : boolean) return std_logic_vector; function std_logic_to_vector (inp : std_logic) return std_logic_vector; function integer_to_std_logic_vector (inp : integer; width, arith : integer) return std_logic_vector; function std_logic_vector_to_integer (inp : std_logic_vector; arith : integer) return integer; function std_logic_to_integer(constant inp : std_logic := '0') return integer; function bin_string_element_to_std_logic_vector (inp : string; width, index : integer) return std_logic_vector; function bin_string_to_std_logic_vector (inp : string) return std_logic_vector; function hex_string_to_std_logic_vector (inp : string; width : integer) return std_logic_vector; function makeZeroBinStr (width : integer) return STRING; function and_reduce(inp: std_logic_vector) return std_logic; -- synopsys translate_off function is_binary_string_invalid (inp : string) return boolean; function is_binary_string_undefined (inp : string) return boolean; function is_XorU(inp : std_logic_vector) return boolean; function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer) return real; function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer) return real; function real_to_std_logic_vector (inp : real; width, bin_pt, arith : integer) return std_logic_vector; function real_string_to_std_logic_vector (inp : string; width, bin_pt, arith : integer) return std_logic_vector; constant display_precision : integer := 20; function real_to_string (inp : real) return string; function valid_bin_string(inp : string) return boolean; function std_logic_vector_to_bin_string(inp : std_logic_vector) return string; function std_logic_to_bin_string(inp : std_logic) return string; function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer) return string; function real_to_bin_string(inp : real; width, bin_pt, arith : integer) return string; type stdlogic_to_char_t is array(std_logic) of character; constant to_char : stdlogic_to_char_t := ( 'U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z', 'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-'); -- synopsys translate_on end conv_pkg; package body conv_pkg is function std_logic_vector_to_unsigned(inp : std_logic_vector) return unsigned is begin return unsigned (inp); end; function unsigned_to_std_logic_vector(inp : unsigned) return std_logic_vector is begin return std_logic_vector(inp); end; function std_logic_vector_to_signed(inp : std_logic_vector) return signed is begin return signed (inp); end; function signed_to_std_logic_vector(inp : signed) return std_logic_vector is begin return std_logic_vector(inp); end; function unsigned_to_signed (inp : unsigned) return signed is begin return signed(std_logic_vector(inp)); end; function signed_to_unsigned (inp : signed) return unsigned is begin return unsigned(std_logic_vector(inp)); end; function pos(inp : std_logic_vector; arith : INTEGER) return boolean is constant width : integer := inp'length; variable vec : std_logic_vector(width-1 downto 0); begin vec := inp; if arith = xlUnsigned then return true; else if vec(width-1) = '0' then return true; else return false; end if; end if; return true; end; function max_signed(width : INTEGER) return std_logic_vector is variable ones : std_logic_vector(width-2 downto 0); variable result : std_logic_vector(width-1 downto 0); begin ones := (others => '1'); result(width-1) := '0'; result(width-2 downto 0) := ones; return result; end; function min_signed(width : INTEGER) return std_logic_vector is variable zeros : std_logic_vector(width-2 downto 0); variable result : std_logic_vector(width-1 downto 0); begin zeros := (others => '0'); result(width-1) := '1'; result(width-2 downto 0) := zeros; return result; end; function and_reduce(inp: std_logic_vector) return std_logic is variable result: std_logic; constant width : integer := inp'length; variable vec : std_logic_vector(width-1 downto 0); begin vec := inp; result := vec(0); if width > 1 then for i in 1 to width-1 loop result := result and vec(i); end loop; end if; return result; end; function all_same(inp: std_logic_vector) return boolean is variable result: boolean; constant width : integer := inp'length; variable vec : std_logic_vector(width-1 downto 0); begin vec := inp; result := true; if width > 0 then for i in 1 to width-1 loop if vec(i) /= vec(0) then result := false; end if; end loop; end if; return result; end; function all_zeros(inp: std_logic_vector) return boolean is constant width : integer := inp'length; variable vec : std_logic_vector(width-1 downto 0); variable zero : std_logic_vector(width-1 downto 0); variable result : boolean; begin zero := (others => '0'); vec := inp; -- synopsys translate_off if (is_XorU(vec)) then return false; end if; -- synopsys translate_on if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(zero)) then result := true; else result := false; end if; return result; end; function is_point_five(inp: std_logic_vector) return boolean is constant width : integer := inp'length; variable vec : std_logic_vector(width-1 downto 0); variable result : boolean; begin vec := inp; -- synopsys translate_off if (is_XorU(vec)) then return false; end if; -- synopsys translate_on if (width > 1) then if ((vec(width-1) = '1') and (all_zeros(vec(width-2 downto 0)) = true)) then result := true; else result := false; end if; else if (vec(width-1) = '1') then result := true; else result := false; end if; end if; return result; end; function all_ones(inp: std_logic_vector) return boolean is constant width : integer := inp'length; variable vec : std_logic_vector(width-1 downto 0); variable one : std_logic_vector(width-1 downto 0); variable result : boolean; begin one := (others => '1'); vec := inp; -- synopsys translate_off if (is_XorU(vec)) then return false; end if; -- synopsys translate_on if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(one)) then result := true; else result := false; end if; return result; end; function full_precision_num_width(quantization, overflow, old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return integer is variable result : integer; begin result := old_width + 2; return result; end; function quantized_num_width(quantization, overflow, old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return integer is variable right_of_dp, left_of_dp, result : integer; begin right_of_dp := max(new_bin_pt, old_bin_pt); left_of_dp := max((new_width - new_bin_pt), (old_width - old_bin_pt)); result := (old_width + 2) + (new_bin_pt - old_bin_pt); return result; end; function convert_type (inp : std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith, quantization, overflow : INTEGER) return std_logic_vector is constant fp_width : integer := full_precision_num_width(quantization, overflow, old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith); constant fp_bin_pt : integer := old_bin_pt; constant fp_arith : integer := old_arith; variable full_precision_result : std_logic_vector(fp_width-1 downto 0); constant q_width : integer := quantized_num_width(quantization, overflow, old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith); constant q_bin_pt : integer := new_bin_pt; constant q_arith : integer := old_arith; variable quantized_result : std_logic_vector(q_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); begin result := (others => '0'); full_precision_result := cast(inp, old_bin_pt, fp_width, fp_bin_pt, fp_arith); if (quantization = xlRound) then quantized_result := round_towards_inf(full_precision_result, fp_width, fp_bin_pt, fp_arith, q_width, q_bin_pt, q_arith); elsif (quantization = xlRoundBanker) then quantized_result := round_towards_even(full_precision_result, fp_width, fp_bin_pt, fp_arith, q_width, q_bin_pt, q_arith); else quantized_result := trunc(full_precision_result, fp_width, fp_bin_pt, fp_arith, q_width, q_bin_pt, q_arith); end if; if (overflow = xlSaturate) then result := saturation_arith(quantized_result, q_width, q_bin_pt, q_arith, new_width, new_bin_pt, new_arith); else result := wrap_arith(quantized_result, q_width, q_bin_pt, q_arith, new_width, new_bin_pt, new_arith); end if; return result; end; function cast (inp : std_logic_vector; old_bin_pt, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector is constant old_width : integer := inp'length; constant left_of_dp : integer := (new_width - new_bin_pt) - (old_width - old_bin_pt); constant right_of_dp : integer := (new_bin_pt - old_bin_pt); variable vec : std_logic_vector(old_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); variable j : integer; begin vec := inp; for i in new_width-1 downto 0 loop j := i - right_of_dp; if ( j > old_width-1) then if (new_arith = xlUnsigned) then result(i) := '0'; else result(i) := vec(old_width-1); end if; elsif ( j >= 0) then result(i) := vec(j); else result(i) := '0'; end if; end loop; return result; end; function shift_division_result(quotient, fraction: std_logic_vector; fraction_width, shift_value, shift_dir: INTEGER) return std_logic_vector is constant q_width : integer := quotient'length; constant f_width : integer := fraction'length; constant vec_MSB : integer := q_width+f_width-1; constant result_MSB : integer := q_width+fraction_width-1; constant result_LSB : integer := vec_MSB-result_MSB; variable vec : std_logic_vector(vec_MSB downto 0); variable result : std_logic_vector(result_MSB downto 0); begin vec := ( quotient & fraction ); if shift_dir = 1 then for i in vec_MSB downto 0 loop if (i < shift_value) then vec(i) := '0'; else vec(i) := vec(i-shift_value); end if; end loop; else for i in 0 to vec_MSB loop if (i > vec_MSB-shift_value) then vec(i) := vec(vec_MSB); else vec(i) := vec(i+shift_value); end if; end loop; end if; result := vec(vec_MSB downto result_LSB); return result; end; function shift_op (inp: std_logic_vector; result_width, shift_value, shift_dir: INTEGER) return std_logic_vector is constant inp_width : integer := inp'length; constant vec_MSB : integer := inp_width-1; constant result_MSB : integer := result_width-1; constant result_LSB : integer := vec_MSB-result_MSB; variable vec : std_logic_vector(vec_MSB downto 0); variable result : std_logic_vector(result_MSB downto 0); begin vec := inp; if shift_dir = 1 then for i in vec_MSB downto 0 loop if (i < shift_value) then vec(i) := '0'; else vec(i) := vec(i-shift_value); end if; end loop; else for i in 0 to vec_MSB loop if (i > vec_MSB-shift_value) then vec(i) := vec(vec_MSB); else vec(i) := vec(i+shift_value); end if; end loop; end if; result := vec(vec_MSB downto result_LSB); return result; end; function vec_slice (inp : std_logic_vector; upper, lower : INTEGER) return std_logic_vector is begin return inp(upper downto lower); end; function s2u_slice (inp : signed; upper, lower : INTEGER) return unsigned is begin return unsigned(vec_slice(std_logic_vector(inp), upper, lower)); end; function u2u_slice (inp : unsigned; upper, lower : INTEGER) return unsigned is begin return unsigned(vec_slice(std_logic_vector(inp), upper, lower)); end; function s2s_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER) return signed is begin return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned)); end; function s2u_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER) return unsigned is begin return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned)); end; function u2s_cast (inp : unsigned; old_bin_pt, new_width, new_bin_pt : INTEGER) return signed is begin return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned)); end; function u2u_cast (inp : unsigned; old_bin_pt, new_width, new_bin_pt : INTEGER) return unsigned is begin return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned)); end; function u2v_cast (inp : unsigned; old_bin_pt, new_width, new_bin_pt : INTEGER) return std_logic_vector is begin return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned); end; function s2v_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER) return std_logic_vector is begin return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned); end; function boolean_to_signed (inp : boolean; width : integer) return signed is variable result : signed(width - 1 downto 0); begin result := (others => '0'); if inp then result(0) := '1'; else result(0) := '0'; end if; return result; end; function boolean_to_unsigned (inp : boolean; width : integer) return unsigned is variable result : unsigned(width - 1 downto 0); begin result := (others => '0'); if inp then result(0) := '1'; else result(0) := '0'; end if; return result; end; function boolean_to_vector (inp : boolean) return std_logic_vector is variable result : std_logic_vector(1 - 1 downto 0); begin result := (others => '0'); if inp then result(0) := '1'; else result(0) := '0'; end if; return result; end; function std_logic_to_vector (inp : std_logic) return std_logic_vector is variable result : std_logic_vector(1 - 1 downto 0); begin result(0) := inp; return result; end; function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector is constant right_of_dp : integer := (old_bin_pt - new_bin_pt); variable vec : std_logic_vector(old_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); begin vec := inp; if right_of_dp >= 0 then if new_arith = xlUnsigned then result := zero_ext(vec(old_width-1 downto right_of_dp), new_width); else result := sign_ext(vec(old_width-1 downto right_of_dp), new_width); end if; else if new_arith = xlUnsigned then result := zero_ext(pad_LSB(vec, old_width + abs(right_of_dp)), new_width); else result := sign_ext(pad_LSB(vec, old_width + abs(right_of_dp)), new_width); end if; end if; return result; end; function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector is constant right_of_dp : integer := (old_bin_pt - new_bin_pt); constant expected_new_width : integer := old_width - right_of_dp + 1; variable vec : std_logic_vector(old_width-1 downto 0); variable one_or_zero : std_logic_vector(new_width-1 downto 0); variable truncated_val : std_logic_vector(new_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); begin vec := inp; if right_of_dp >= 0 then if new_arith = xlUnsigned then truncated_val := zero_ext(vec(old_width-1 downto right_of_dp), new_width); else truncated_val := sign_ext(vec(old_width-1 downto right_of_dp), new_width); end if; else if new_arith = xlUnsigned then truncated_val := zero_ext(pad_LSB(vec, old_width + abs(right_of_dp)), new_width); else truncated_val := sign_ext(pad_LSB(vec, old_width + abs(right_of_dp)), new_width); end if; end if; one_or_zero := (others => '0'); if (new_arith = xlSigned) then if (vec(old_width-1) = '0') then one_or_zero(0) := '1'; end if; if (right_of_dp >= 2) and (right_of_dp <= old_width) then if (all_zeros(vec(right_of_dp-2 downto 0)) = false) then one_or_zero(0) := '1'; end if; end if; if (right_of_dp >= 1) and (right_of_dp <= old_width) then if vec(right_of_dp-1) = '0' then one_or_zero(0) := '0'; end if; else one_or_zero(0) := '0'; end if; else if (right_of_dp >= 1) and (right_of_dp <= old_width) then one_or_zero(0) := vec(right_of_dp-1); end if; end if; if new_arith = xlSigned then result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) + std_logic_vector_to_signed(one_or_zero)); else result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) + std_logic_vector_to_unsigned(one_or_zero)); end if; return result; end; function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector is constant right_of_dp : integer := (old_bin_pt - new_bin_pt); constant expected_new_width : integer := old_width - right_of_dp + 1; variable vec : std_logic_vector(old_width-1 downto 0); variable one_or_zero : std_logic_vector(new_width-1 downto 0); variable truncated_val : std_logic_vector(new_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); begin vec := inp; if right_of_dp >= 0 then if new_arith = xlUnsigned then truncated_val := zero_ext(vec(old_width-1 downto right_of_dp), new_width); else truncated_val := sign_ext(vec(old_width-1 downto right_of_dp), new_width); end if; else if new_arith = xlUnsigned then truncated_val := zero_ext(pad_LSB(vec, old_width + abs(right_of_dp)), new_width); else truncated_val := sign_ext(pad_LSB(vec, old_width + abs(right_of_dp)), new_width); end if; end if; one_or_zero := (others => '0'); if (right_of_dp >= 1) and (right_of_dp <= old_width) then if (is_point_five(vec(right_of_dp-1 downto 0)) = false) then one_or_zero(0) := vec(right_of_dp-1); else one_or_zero(0) := vec(right_of_dp); end if; end if; if new_arith = xlSigned then result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) + std_logic_vector_to_signed(one_or_zero)); else result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) + std_logic_vector_to_unsigned(one_or_zero)); end if; return result; end; function saturation_arith(inp: std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector is constant left_of_dp : integer := (old_width - old_bin_pt) - (new_width - new_bin_pt); variable vec : std_logic_vector(old_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); variable overflow : boolean; begin vec := inp; overflow := true; result := (others => '0'); if (new_width >= old_width) then overflow := false; end if; if ((old_arith = xlSigned and new_arith = xlSigned) and (old_width > new_width)) then if all_same(vec(old_width-1 downto new_width-1)) then overflow := false; end if; end if; if (old_arith = xlSigned and new_arith = xlUnsigned) then if (old_width > new_width) then if all_zeros(vec(old_width-1 downto new_width)) then overflow := false; end if; else if (old_width = new_width) then if (vec(new_width-1) = '0') then overflow := false; end if; end if; end if; end if; if (old_arith = xlUnsigned and new_arith = xlUnsigned) then if (old_width > new_width) then if all_zeros(vec(old_width-1 downto new_width)) then overflow := false; end if; else if (old_width = new_width) then overflow := false; end if; end if; end if; if ((old_arith = xlUnsigned and new_arith = xlSigned) and (old_width > new_width)) then if all_same(vec(old_width-1 downto new_width-1)) then overflow := false; end if; end if; if overflow then if new_arith = xlSigned then if vec(old_width-1) = '0' then result := max_signed(new_width); else result := min_signed(new_width); end if; else if ((old_arith = xlSigned) and vec(old_width-1) = '1') then result := (others => '0'); else result := (others => '1'); end if; end if; else if (old_arith = xlSigned) and (new_arith = xlUnsigned) then if (vec(old_width-1) = '1') then vec := (others => '0'); end if; end if; if new_width <= old_width then result := vec(new_width-1 downto 0); else if new_arith = xlUnsigned then result := zero_ext(vec, new_width); else result := sign_ext(vec, new_width); end if; end if; end if; return result; end; function wrap_arith(inp: std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector is variable result : std_logic_vector(new_width-1 downto 0); variable result_arith : integer; begin if (old_arith = xlSigned) and (new_arith = xlUnsigned) then result_arith := xlSigned; end if; result := cast(inp, old_bin_pt, new_width, new_bin_pt, result_arith); return result; end; function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER is begin return max(a_bin_pt, b_bin_pt); end; function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER) return INTEGER is begin return max(a_width - a_bin_pt, b_width - b_bin_pt); end; function pad_LSB(inp : std_logic_vector; new_width: integer) return STD_LOGIC_VECTOR is constant orig_width : integer := inp'length; variable vec : std_logic_vector(orig_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); variable pos : integer; constant pad_pos : integer := new_width - orig_width - 1; begin vec := inp; pos := new_width-1; if (new_width >= orig_width) then for i in orig_width-1 downto 0 loop result(pos) := vec(i); pos := pos - 1; end loop; if pad_pos >= 0 then for i in pad_pos downto 0 loop result(i) := '0'; end loop; end if; end if; return result; end; function sign_ext(inp : std_logic_vector; new_width : INTEGER) return std_logic_vector is constant old_width : integer := inp'length; variable vec : std_logic_vector(old_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); begin vec := inp; if new_width >= old_width then result(old_width-1 downto 0) := vec; if new_width-1 >= old_width then for i in new_width-1 downto old_width loop result(i) := vec(old_width-1); end loop; end if; else result(new_width-1 downto 0) := vec(new_width-1 downto 0); end if; return result; end; function zero_ext(inp : std_logic_vector; new_width : INTEGER) return std_logic_vector is constant old_width : integer := inp'length; variable vec : std_logic_vector(old_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); begin vec := inp; if new_width >= old_width then result(old_width-1 downto 0) := vec; if new_width-1 >= old_width then for i in new_width-1 downto old_width loop result(i) := '0'; end loop; end if; else result(new_width-1 downto 0) := vec(new_width-1 downto 0); end if; return result; end; function zero_ext(inp : std_logic; new_width : INTEGER) return std_logic_vector is variable result : std_logic_vector(new_width-1 downto 0); begin result(0) := inp; for i in new_width-1 downto 1 loop result(i) := '0'; end loop; return result; end; function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER) return std_logic_vector is constant orig_width : integer := inp'length; variable vec : std_logic_vector(orig_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); begin vec := inp; if arith = xlUnsigned then result := zero_ext(vec, new_width); else result := sign_ext(vec, new_width); end if; return result; end; function pad_LSB(inp : std_logic_vector; new_width, arith: integer) return STD_LOGIC_VECTOR is constant orig_width : integer := inp'length; variable vec : std_logic_vector(orig_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); variable pos : integer; begin vec := inp; pos := new_width-1; if (arith = xlUnsigned) then result(pos) := '0'; pos := pos - 1; else result(pos) := vec(orig_width-1); pos := pos - 1; end if; if (new_width >= orig_width) then for i in orig_width-1 downto 0 loop result(pos) := vec(i); pos := pos - 1; end loop; if pos >= 0 then for i in pos downto 0 loop result(i) := '0'; end loop; end if; end if; return result; end; function align_input(inp : std_logic_vector; old_width, delta, new_arith, new_width: INTEGER) return std_logic_vector is variable vec : std_logic_vector(old_width-1 downto 0); variable padded_inp : std_logic_vector((old_width + delta)-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); begin vec := inp; if delta > 0 then padded_inp := pad_LSB(vec, old_width+delta); result := extend_MSB(padded_inp, new_width, new_arith); else result := extend_MSB(vec, new_width, new_arith); end if; return result; end; function max(L, R: INTEGER) return INTEGER is begin if L > R then return L; else return R; end if; end; function min(L, R: INTEGER) return INTEGER is begin if L < R then return L; else return R; end if; end; function "="(left,right: STRING) return boolean is begin if (left'length /= right'length) then return false; else test : for i in 1 to left'length loop if left(i) /= right(i) then return false; end if; end loop test; return true; end if; end; -- synopsys translate_off function is_binary_string_invalid (inp : string) return boolean is variable vec : string(1 to inp'length); variable result : boolean; begin vec := inp; result := false; for i in 1 to vec'length loop if ( vec(i) = 'X' ) then result := true; end if; end loop; return result; end; function is_binary_string_undefined (inp : string) return boolean is variable vec : string(1 to inp'length); variable result : boolean; begin vec := inp; result := false; for i in 1 to vec'length loop if ( vec(i) = 'U' ) then result := true; end if; end loop; return result; end; function is_XorU(inp : std_logic_vector) return boolean is constant width : integer := inp'length; variable vec : std_logic_vector(width-1 downto 0); variable result : boolean; begin vec := inp; result := false; for i in 0 to width-1 loop if (vec(i) = 'U') or (vec(i) = 'X') then result := true; end if; end loop; return result; end; function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer) return real is variable vec : std_logic_vector(inp'length-1 downto 0); variable result, shift_val, undefined_real : real; variable neg_num : boolean; begin vec := inp; result := 0.0; neg_num := false; if vec(inp'length-1) = '1' then neg_num := true; end if; for i in 0 to inp'length-1 loop if vec(i) = 'U' or vec(i) = 'X' then return undefined_real; end if; if arith = xlSigned then if neg_num then if vec(i) = '0' then result := result + 2.0**i; end if; else if vec(i) = '1' then result := result + 2.0**i; end if; end if; else if vec(i) = '1' then result := result + 2.0**i; end if; end if; end loop; if arith = xlSigned then if neg_num then result := result + 1.0; result := result * (-1.0); end if; end if; shift_val := 2.0**(-1*bin_pt); result := result * shift_val; return result; end; function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer) return real is variable result : real := 0.0; begin if inp = '1' then result := 1.0; end if; if arith = xlSigned then assert false report "It doesn't make sense to convert a 1 bit number to a signed real."; end if; return result; end; -- synopsys translate_on function integer_to_std_logic_vector (inp : integer; width, arith : integer) return std_logic_vector is variable result : std_logic_vector(width-1 downto 0); variable unsigned_val : unsigned(width-1 downto 0); variable signed_val : signed(width-1 downto 0); begin if (arith = xlSigned) then signed_val := to_signed(inp, width); result := signed_to_std_logic_vector(signed_val); else unsigned_val := to_unsigned(inp, width); result := unsigned_to_std_logic_vector(unsigned_val); end if; return result; end; function std_logic_vector_to_integer (inp : std_logic_vector; arith : integer) return integer is constant width : integer := inp'length; variable unsigned_val : unsigned(width-1 downto 0); variable signed_val : signed(width-1 downto 0); variable result : integer; begin if (arith = xlSigned) then signed_val := std_logic_vector_to_signed(inp); result := to_integer(signed_val); else unsigned_val := std_logic_vector_to_unsigned(inp); result := to_integer(unsigned_val); end if; return result; end; function std_logic_to_integer(constant inp : std_logic := '0') return integer is begin if inp = '1' then return 1; else return 0; end if; end; function makeZeroBinStr (width : integer) return STRING is variable result : string(1 to width+3); begin result(1) := '0'; result(2) := 'b'; for i in 3 to width+2 loop result(i) := '0'; end loop; result(width+3) := '.'; return result; end; -- synopsys translate_off function real_string_to_std_logic_vector (inp : string; width, bin_pt, arith : integer) return std_logic_vector is variable result : std_logic_vector(width-1 downto 0); begin result := (others => '0'); return result; end; function real_to_std_logic_vector (inp : real; width, bin_pt, arith : integer) return std_logic_vector is variable real_val : real; variable int_val : integer; variable result : std_logic_vector(width-1 downto 0) := (others => '0'); variable unsigned_val : unsigned(width-1 downto 0) := (others => '0'); variable signed_val : signed(width-1 downto 0) := (others => '0'); begin real_val := inp; int_val := integer(real_val * 2.0**(bin_pt)); if (arith = xlSigned) then signed_val := to_signed(int_val, width); result := signed_to_std_logic_vector(signed_val); else unsigned_val := to_unsigned(int_val, width); result := unsigned_to_std_logic_vector(unsigned_val); end if; return result; end; -- synopsys translate_on function valid_bin_string (inp : string) return boolean is variable vec : string(1 to inp'length); begin vec := inp; if (vec(1) = '0' and vec(2) = 'b') then return true; else return false; end if; end; function hex_string_to_std_logic_vector(inp: string; width : integer) return std_logic_vector is constant strlen : integer := inp'LENGTH; variable result : std_logic_vector(width-1 downto 0); variable bitval : std_logic_vector((strlen*4)-1 downto 0); variable posn : integer; variable ch : character; variable vec : string(1 to strlen); begin vec := inp; result := (others => '0'); posn := (strlen*4)-1; for i in 1 to strlen loop ch := vec(i); case ch is when '0' => bitval(posn downto posn-3) := "0000"; when '1' => bitval(posn downto posn-3) := "0001"; when '2' => bitval(posn downto posn-3) := "0010"; when '3' => bitval(posn downto posn-3) := "0011"; when '4' => bitval(posn downto posn-3) := "0100"; when '5' => bitval(posn downto posn-3) := "0101"; when '6' => bitval(posn downto posn-3) := "0110"; when '7' => bitval(posn downto posn-3) := "0111"; when '8' => bitval(posn downto posn-3) := "1000"; when '9' => bitval(posn downto posn-3) := "1001"; when 'A' | 'a' => bitval(posn downto posn-3) := "1010"; when 'B' | 'b' => bitval(posn downto posn-3) := "1011"; when 'C' | 'c' => bitval(posn downto posn-3) := "1100"; when 'D' | 'd' => bitval(posn downto posn-3) := "1101"; when 'E' | 'e' => bitval(posn downto posn-3) := "1110"; when 'F' | 'f' => bitval(posn downto posn-3) := "1111"; when others => bitval(posn downto posn-3) := "XXXX"; -- synopsys translate_off ASSERT false REPORT "Invalid hex value" SEVERITY ERROR; -- synopsys translate_on end case; posn := posn - 4; end loop; if (width <= strlen*4) then result := bitval(width-1 downto 0); else result((strlen*4)-1 downto 0) := bitval; end if; return result; end; function bin_string_to_std_logic_vector (inp : string) return std_logic_vector is variable pos : integer; variable vec : string(1 to inp'length); variable result : std_logic_vector(inp'length-1 downto 0); begin vec := inp; pos := inp'length-1; result := (others => '0'); for i in 1 to vec'length loop -- synopsys translate_off if (pos < 0) and (vec(i) = '0' or vec(i) = '1' or vec(i) = 'X' or vec(i) = 'U') then assert false report "Input string is larger than output std_logic_vector. Truncating output."; return result; end if; -- synopsys translate_on if vec(i) = '0' then result(pos) := '0'; pos := pos - 1; end if; if vec(i) = '1' then result(pos) := '1'; pos := pos - 1; end if; -- synopsys translate_off if (vec(i) = 'X' or vec(i) = 'U') then result(pos) := 'U'; pos := pos - 1; end if; -- synopsys translate_on end loop; return result; end; function bin_string_element_to_std_logic_vector (inp : string; width, index : integer) return std_logic_vector is constant str_width : integer := width + 4; constant inp_len : integer := inp'length; constant num_elements : integer := (inp_len + 1)/str_width; constant reverse_index : integer := (num_elements-1) - index; variable left_pos : integer; variable right_pos : integer; variable vec : string(1 to inp'length); variable result : std_logic_vector(width-1 downto 0); begin vec := inp; result := (others => '0'); if (reverse_index = 0) and (reverse_index < num_elements) and (inp_len-3 >= width) then left_pos := 1; right_pos := width + 3; result := bin_string_to_std_logic_vector(vec(left_pos to right_pos)); end if; if (reverse_index > 0) and (reverse_index < num_elements) and (inp_len-3 >= width) then left_pos := (reverse_index * str_width) + 1; right_pos := left_pos + width + 2; result := bin_string_to_std_logic_vector(vec(left_pos to right_pos)); end if; return result; end; -- synopsys translate_off function std_logic_vector_to_bin_string(inp : std_logic_vector) return string is variable vec : std_logic_vector(1 to inp'length); variable result : string(vec'range); begin vec := inp; for i in vec'range loop result(i) := to_char(vec(i)); end loop; return result; end; function std_logic_to_bin_string(inp : std_logic) return string is variable result : string(1 to 3); begin result(1) := '0'; result(2) := 'b'; result(3) := to_char(inp); return result; end; function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer) return string is variable width : integer := inp'length; variable vec : std_logic_vector(width-1 downto 0); variable str_pos : integer; variable result : string(1 to width+3); begin vec := inp; str_pos := 1; result(str_pos) := '0'; str_pos := 2; result(str_pos) := 'b'; str_pos := 3; for i in width-1 downto 0 loop if (((width+3) - bin_pt) = str_pos) then result(str_pos) := '.'; str_pos := str_pos + 1; end if; result(str_pos) := to_char(vec(i)); str_pos := str_pos + 1; end loop; if (bin_pt = 0) then result(str_pos) := '.'; end if; return result; end; function real_to_bin_string(inp : real; width, bin_pt, arith : integer) return string is variable result : string(1 to width); variable vec : std_logic_vector(width-1 downto 0); begin vec := real_to_std_logic_vector(inp, width, bin_pt, arith); result := std_logic_vector_to_bin_string(vec); return result; end; function real_to_string (inp : real) return string is variable result : string(1 to display_precision) := (others => ' '); begin result(real'image(inp)'range) := real'image(inp); return result; end; -- synopsys translate_on end conv_pkg; ------------------------------------------------------------------- -- System Generator version 13.2 VHDL source file. -- -- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- -- synopsys translate_off library unisim; use unisim.vcomponents.all; -- synopsys translate_on library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity srl17e is generic (width : integer:=16; latency : integer :=8); port (clk : in std_logic; ce : in std_logic; d : in std_logic_vector(width-1 downto 0); q : out std_logic_vector(width-1 downto 0)); end srl17e; architecture structural of srl17e is component SRL16E port (D : in STD_ULOGIC; CE : in STD_ULOGIC; CLK : in STD_ULOGIC; A0 : in STD_ULOGIC; A1 : in STD_ULOGIC; A2 : in STD_ULOGIC; A3 : in STD_ULOGIC; Q : out STD_ULOGIC); end component; attribute syn_black_box of SRL16E : component is true; attribute fpga_dont_touch of SRL16E : component is "true"; component FDE port( Q : out STD_ULOGIC; D : in STD_ULOGIC; C : in STD_ULOGIC; CE : in STD_ULOGIC); end component; attribute syn_black_box of FDE : component is true; attribute fpga_dont_touch of FDE : component is "true"; constant a : std_logic_vector(4 downto 0) := integer_to_std_logic_vector(latency-2,5,xlSigned); signal d_delayed : std_logic_vector(width-1 downto 0); signal srl16_out : std_logic_vector(width-1 downto 0); begin d_delayed <= d after 200 ps; reg_array : for i in 0 to width-1 generate srl16_used: if latency > 1 generate u1 : srl16e port map(clk => clk, d => d_delayed(i), q => srl16_out(i), ce => ce, a0 => a(0), a1 => a(1), a2 => a(2), a3 => a(3)); end generate; srl16_not_used: if latency <= 1 generate srl16_out(i) <= d_delayed(i); end generate; fde_used: if latency /= 0 generate u2 : fde port map(c => clk, d => srl16_out(i), q => q(i), ce => ce); end generate; fde_not_used: if latency = 0 generate q(i) <= srl16_out(i); end generate; end generate; end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity synth_reg is generic (width : integer := 8; latency : integer := 1); port (i : in std_logic_vector(width-1 downto 0); ce : in std_logic; clr : in std_logic; clk : in std_logic; o : out std_logic_vector(width-1 downto 0)); end synth_reg; architecture structural of synth_reg is component srl17e generic (width : integer:=16; latency : integer :=8); port (clk : in std_logic; ce : in std_logic; d : in std_logic_vector(width-1 downto 0); q : out std_logic_vector(width-1 downto 0)); end component; function calc_num_srl17es (latency : integer) return integer is variable remaining_latency : integer; variable result : integer; begin result := latency / 17; remaining_latency := latency - (result * 17); if (remaining_latency /= 0) then result := result + 1; end if; return result; end; constant complete_num_srl17es : integer := latency / 17; constant num_srl17es : integer := calc_num_srl17es(latency); constant remaining_latency : integer := latency - (complete_num_srl17es * 17); type register_array is array (num_srl17es downto 0) of std_logic_vector(width-1 downto 0); signal z : register_array; begin z(0) <= i; complete_ones : if complete_num_srl17es > 0 generate srl17e_array: for i in 0 to complete_num_srl17es-1 generate delay_comp : srl17e generic map (width => width, latency => 17) port map (clk => clk, ce => ce, d => z(i), q => z(i+1)); end generate; end generate; partial_one : if remaining_latency > 0 generate last_srl17e : srl17e generic map (width => width, latency => remaining_latency) port map (clk => clk, ce => ce, d => z(num_srl17es-1), q => z(num_srl17es)); end generate; o <= z(num_srl17es); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity synth_reg_reg is generic (width : integer := 8; latency : integer := 1); port (i : in std_logic_vector(width-1 downto 0); ce : in std_logic; clr : in std_logic; clk : in std_logic; o : out std_logic_vector(width-1 downto 0)); end synth_reg_reg; architecture behav of synth_reg_reg is type reg_array_type is array (latency-1 downto 0) of std_logic_vector(width -1 downto 0); signal reg_bank : reg_array_type := (others => (others => '0')); signal reg_bank_in : reg_array_type := (others => (others => '0')); attribute syn_allow_retiming : boolean; attribute syn_srlstyle : string; attribute syn_allow_retiming of reg_bank : signal is true; attribute syn_allow_retiming of reg_bank_in : signal is true; attribute syn_srlstyle of reg_bank : signal is "registers"; attribute syn_srlstyle of reg_bank_in : signal is "registers"; begin latency_eq_0: if latency = 0 generate o <= i; end generate latency_eq_0; latency_gt_0: if latency >= 1 generate o <= reg_bank(latency-1); reg_bank_in(0) <= i; loop_gen: for idx in latency-2 downto 0 generate reg_bank_in(idx+1) <= reg_bank(idx); end generate loop_gen; sync_loop: for sync_idx in latency-1 downto 0 generate sync_proc: process (clk) begin if clk'event and clk = '1' then if clr = '1' then reg_bank_in <= (others => (others => '0')); elsif ce = '1' then reg_bank(sync_idx) <= reg_bank_in(sync_idx); end if; end if; end process sync_proc; end generate sync_loop; end generate latency_gt_0; end behav; ------------------------------------------------------------------- -- System Generator version 13.2 VHDL source file. -- -- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- -- synopsys translate_off library unisim; use unisim.vcomponents.all; -- synopsys translate_on library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity single_reg_w_init is generic ( width: integer := 8; init_index: integer := 0; init_value: bit_vector := b"0000" ); port ( i: in std_logic_vector(width - 1 downto 0); ce: in std_logic; clr: in std_logic; clk: in std_logic; o: out std_logic_vector(width - 1 downto 0) ); end single_reg_w_init; architecture structural of single_reg_w_init is function build_init_const(width: integer; init_index: integer; init_value: bit_vector) return std_logic_vector is variable result: std_logic_vector(width - 1 downto 0); begin if init_index = 0 then result := (others => '0'); elsif init_index = 1 then result := (others => '0'); result(0) := '1'; else result := to_stdlogicvector(init_value); end if; return result; end; component fdre port ( q: out std_ulogic; d: in std_ulogic; c: in std_ulogic; ce: in std_ulogic; r: in std_ulogic ); end component; attribute syn_black_box of fdre: component is true; attribute fpga_dont_touch of fdre: component is "true"; component fdse port ( q: out std_ulogic; d: in std_ulogic; c: in std_ulogic; ce: in std_ulogic; s: in std_ulogic ); end component; attribute syn_black_box of fdse: component is true; attribute fpga_dont_touch of fdse: component is "true"; constant init_const: std_logic_vector(width - 1 downto 0) := build_init_const(width, init_index, init_value); begin fd_prim_array: for index in 0 to width - 1 generate bit_is_0: if (init_const(index) = '0') generate fdre_comp: fdre port map ( c => clk, d => i(index), q => o(index), ce => ce, r => clr ); end generate; bit_is_1: if (init_const(index) = '1') generate fdse_comp: fdse port map ( c => clk, d => i(index), q => o(index), ce => ce, s => clr ); end generate; end generate; end architecture structural; -- synopsys translate_off library unisim; use unisim.vcomponents.all; -- synopsys translate_on library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity synth_reg_w_init is generic ( width: integer := 8; init_index: integer := 0; init_value: bit_vector := b"0000"; latency: integer := 1 ); port ( i: in std_logic_vector(width - 1 downto 0); ce: in std_logic; clr: in std_logic; clk: in std_logic; o: out std_logic_vector(width - 1 downto 0) ); end synth_reg_w_init; architecture structural of synth_reg_w_init is component single_reg_w_init generic ( width: integer := 8; init_index: integer := 0; init_value: bit_vector := b"0000" ); port ( i: in std_logic_vector(width - 1 downto 0); ce: in std_logic; clr: in std_logic; clk: in std_logic; o: out std_logic_vector(width - 1 downto 0) ); end component; signal dly_i: std_logic_vector((latency + 1) * width - 1 downto 0); signal dly_clr: std_logic; begin latency_eq_0: if (latency = 0) generate o <= i; end generate; latency_gt_0: if (latency >= 1) generate dly_i((latency + 1) * width - 1 downto latency * width) <= i after 200 ps; dly_clr <= clr after 200 ps; fd_array: for index in latency downto 1 generate reg_comp: single_reg_w_init generic map ( width => width, init_index => init_index, init_value => init_value ) port map ( clk => clk, i => dly_i((index + 1) * width - 1 downto index * width), o => dly_i(index * width - 1 downto (index - 1) * width), ce => ce, clr => dly_clr ); end generate; o <= dly_i(width - 1 downto 0); end generate; end structural; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity mux_029cd20aa9 is port ( sel : in std_logic_vector((1 - 1) downto 0); d0 : in std_logic_vector((22 - 1) downto 0); d1 : in std_logic_vector((23 - 1) downto 0); y : out std_logic_vector((23 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end mux_029cd20aa9; architecture behavior of mux_029cd20aa9 is signal sel_1_20: std_logic_vector((1 - 1) downto 0); signal d0_1_24: std_logic_vector((22 - 1) downto 0); signal d1_1_27: std_logic_vector((23 - 1) downto 0); type array_type_pipe_16_22 is array (0 to (1 - 1)) of std_logic_vector((23 - 1) downto 0); signal pipe_16_22: array_type_pipe_16_22 := ( 0 => "00000000000000000000000"); signal pipe_16_22_front_din: std_logic_vector((23 - 1) downto 0); signal pipe_16_22_back: std_logic_vector((23 - 1) downto 0); signal pipe_16_22_push_front_pop_back_en: std_logic; signal unregy_join_6_1: std_logic_vector((23 - 1) downto 0); begin sel_1_20 <= sel; d0_1_24 <= d0; d1_1_27 <= d1; pipe_16_22_back <= pipe_16_22(0); proc_pipe_16_22: process (clk) is variable i: integer; begin if (clk'event and (clk = '1')) then if ((ce = '1') and (pipe_16_22_push_front_pop_back_en = '1')) then pipe_16_22(0) <= pipe_16_22_front_din; end if; end if; end process proc_pipe_16_22; proc_switch_6_1: process (d0_1_24, d1_1_27, sel_1_20) is begin case sel_1_20 is when "0" => unregy_join_6_1 <= cast(d0_1_24, 0, 23, 0, xlSigned); when others => unregy_join_6_1 <= d1_1_27; end case; end process proc_switch_6_1; pipe_16_22_front_din <= unregy_join_6_1; pipe_16_22_push_front_pop_back_en <= '1'; y <= pipe_16_22_back; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity negate_142bd36a06 is port ( ip : in std_logic_vector((22 - 1) downto 0); op : out std_logic_vector((23 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end negate_142bd36a06; architecture behavior of negate_142bd36a06 is signal ip_18_25: signed((22 - 1) downto 0); type array_type_op_mem_42_20 is array (0 to (1 - 1)) of signed((23 - 1) downto 0); signal op_mem_42_20: array_type_op_mem_42_20 := ( 0 => "00000000000000000000000"); signal op_mem_42_20_front_din: signed((23 - 1) downto 0); signal op_mem_42_20_back: signed((23 - 1) downto 0); signal op_mem_42_20_push_front_pop_back_en: std_logic; signal cast_30_16: signed((23 - 1) downto 0); signal internal_ip_30_1_neg: signed((23 - 1) downto 0); begin ip_18_25 <= std_logic_vector_to_signed(ip); op_mem_42_20_back <= op_mem_42_20(0); proc_op_mem_42_20: process (clk) is variable i: integer; begin if (clk'event and (clk = '1')) then if ((ce = '1') and (op_mem_42_20_push_front_pop_back_en = '1')) then op_mem_42_20(0) <= op_mem_42_20_front_din; end if; end if; end process proc_op_mem_42_20; cast_30_16 <= s2s_cast(ip_18_25, 0, 23, 0); internal_ip_30_1_neg <= -cast_30_16; op_mem_42_20_front_din <= internal_ip_30_1_neg; op_mem_42_20_push_front_pop_back_en <= '1'; op <= signed_to_std_logic_vector(op_mem_42_20_back); end behavior; ------------------------------------------------------------------- -- System Generator version 13.2 VHDL source file. -- -- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity xlregister is generic (d_width : integer := 5; init_value : bit_vector := b"00"); port (d : in std_logic_vector (d_width-1 downto 0); rst : in std_logic_vector(0 downto 0) := "0"; en : in std_logic_vector(0 downto 0) := "1"; ce : in std_logic; clk : in std_logic; q : out std_logic_vector (d_width-1 downto 0)); end xlregister; architecture behavior of xlregister is component synth_reg_w_init generic (width : integer; init_index : integer; init_value : bit_vector; latency : integer); port (i : in std_logic_vector(width-1 downto 0); ce : in std_logic; clr : in std_logic; clk : in std_logic; o : out std_logic_vector(width-1 downto 0)); end component; -- synopsys translate_off signal real_d, real_q : real; -- synopsys translate_on signal internal_clr : std_logic; signal internal_ce : std_logic; begin internal_clr <= rst(0) and ce; internal_ce <= en(0) and ce; synth_reg_inst : synth_reg_w_init generic map (width => d_width, init_index => 2, init_value => init_value, latency => 1) port map (i => d, ce => internal_ce, clr => internal_clr, clk => clk, o => q); end architecture behavior; ------------------------------------------------------------------- -- System Generator version 13.2 VHDL source file. -- -- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use work.conv_pkg.all; entity xlslice is generic ( new_msb : integer := 9; new_lsb : integer := 1; x_width : integer := 16; y_width : integer := 8); port ( x : in std_logic_vector (x_width-1 downto 0); y : out std_logic_vector (y_width-1 downto 0)); end xlslice; architecture behavior of xlslice is begin y <= x(new_msb downto new_lsb); end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity inverter_e5b38cca3b is port ( ip : in std_logic_vector((1 - 1) downto 0); op : out std_logic_vector((1 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end inverter_e5b38cca3b; architecture behavior of inverter_e5b38cca3b is signal ip_1_26: boolean; type array_type_op_mem_22_20 is array (0 to (1 - 1)) of boolean; signal op_mem_22_20: array_type_op_mem_22_20 := ( 0 => false); signal op_mem_22_20_front_din: boolean; signal op_mem_22_20_back: boolean; signal op_mem_22_20_push_front_pop_back_en: std_logic; signal internal_ip_12_1_bitnot: boolean; begin ip_1_26 <= ((ip) = "1"); op_mem_22_20_back <= op_mem_22_20(0); proc_op_mem_22_20: process (clk) is variable i: integer; begin if (clk'event and (clk = '1')) then if ((ce = '1') and (op_mem_22_20_push_front_pop_back_en = '1')) then op_mem_22_20(0) <= op_mem_22_20_front_din; end if; end if; end process proc_op_mem_22_20; internal_ip_12_1_bitnot <= ((not boolean_to_vector(ip_1_26)) = "1"); op_mem_22_20_push_front_pop_back_en <= '0'; op <= boolean_to_vector(internal_ip_12_1_bitnot); end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity logical_80f90b97d0 is port ( d0 : in std_logic_vector((1 - 1) downto 0); d1 : in std_logic_vector((1 - 1) downto 0); y : out std_logic_vector((1 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end logical_80f90b97d0; architecture behavior of logical_80f90b97d0 is signal d0_1_24: std_logic; signal d1_1_27: std_logic; signal fully_2_1_bit: std_logic; begin d0_1_24 <= d0(0); d1_1_27 <= d1(0); fully_2_1_bit <= d0_1_24 and d1_1_27; y <= std_logic_to_vector(fully_2_1_bit); end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity xlfir_compiler_acc9ad12ef8a3d59fab07d7a4ad1b777 is port( ce:in std_logic; ce_logic_1:in std_logic; clk:in std_logic; clk_logic_1:in std_logic; coef_din:in std_logic_vector(6 downto 0); coef_ld:in std_logic; coef_we:in std_logic; din:in std_logic_vector(7 downto 0); dout:out std_logic_vector(18 downto 0); rdy:out std_logic; rfd:out std_logic; src_ce:in std_logic; src_clk:in std_logic ); end xlfir_compiler_acc9ad12ef8a3d59fab07d7a4ad1b777; architecture behavior of xlfir_compiler_acc9ad12ef8a3d59fab07d7a4ad1b777 is component fr_cmplr_v5_0_70a7f64f38920660 port( ce:in std_logic; clk:in std_logic; coef_din:in std_logic_vector(6 downto 0); coef_ld:in std_logic; coef_we:in std_logic; din:in std_logic_vector(7 downto 0); dout:out std_logic_vector(18 downto 0); nd:in std_logic; rdy:out std_logic; rfd:out std_logic ); end component; begin fr_cmplr_v5_0_70a7f64f38920660_instance : fr_cmplr_v5_0_70a7f64f38920660 port map( ce=>ce, clk=>clk, coef_din=>coef_din, coef_ld=>coef_ld, coef_we=>coef_we, din=>din, dout=>dout, nd=>ce_logic_1, rdy=>rdy, rfd=>rfd ); end behavior; ------------------------------------------------------------------- -- System Generator version 13.2 VHDL source file. -- -- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- -- synopsys translate_off library XilinxCoreLib; -- synopsys translate_on library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use work.conv_pkg.all; entity xladdsub is generic ( core_name0: string := ""; a_width: integer := 16; a_bin_pt: integer := 4; a_arith: integer := xlUnsigned; c_in_width: integer := 16; c_in_bin_pt: integer := 4; c_in_arith: integer := xlUnsigned; c_out_width: integer := 16; c_out_bin_pt: integer := 4; c_out_arith: integer := xlUnsigned; b_width: integer := 8; b_bin_pt: integer := 2; b_arith: integer := xlUnsigned; s_width: integer := 17; s_bin_pt: integer := 4; s_arith: integer := xlUnsigned; rst_width: integer := 1; rst_bin_pt: integer := 0; rst_arith: integer := xlUnsigned; en_width: integer := 1; en_bin_pt: integer := 0; en_arith: integer := xlUnsigned; full_s_width: integer := 17; full_s_arith: integer := xlUnsigned; mode: integer := xlAddMode; extra_registers: integer := 0; latency: integer := 0; quantization: integer := xlTruncate; overflow: integer := xlWrap; c_latency: integer := 0; c_output_width: integer := 17; c_has_c_in : integer := 0; c_has_c_out : integer := 0 ); port ( a: in std_logic_vector(a_width - 1 downto 0); b: in std_logic_vector(b_width - 1 downto 0); c_in : in std_logic_vector (0 downto 0) := "0"; ce: in std_logic; clr: in std_logic := '0'; clk: in std_logic; rst: in std_logic_vector(rst_width - 1 downto 0) := "0"; en: in std_logic_vector(en_width - 1 downto 0) := "1"; c_out : out std_logic_vector (0 downto 0); s: out std_logic_vector(s_width - 1 downto 0) ); end xladdsub; architecture behavior of xladdsub is component synth_reg generic ( width: integer := 16; latency: integer := 5 ); port ( i: in std_logic_vector(width - 1 downto 0); ce: in std_logic; clr: in std_logic; clk: in std_logic; o: out std_logic_vector(width - 1 downto 0) ); end component; function format_input(inp: std_logic_vector; old_width, delta, new_arith, new_width: integer) return std_logic_vector is variable vec: std_logic_vector(old_width-1 downto 0); variable padded_inp: std_logic_vector((old_width + delta)-1 downto 0); variable result: std_logic_vector(new_width-1 downto 0); begin vec := inp; if (delta > 0) then padded_inp := pad_LSB(vec, old_width+delta); result := extend_MSB(padded_inp, new_width, new_arith); else result := extend_MSB(vec, new_width, new_arith); end if; return result; end; constant full_s_bin_pt: integer := fractional_bits(a_bin_pt, b_bin_pt); constant full_a_width: integer := full_s_width; constant full_b_width: integer := full_s_width; signal full_a: std_logic_vector(full_a_width - 1 downto 0); signal full_b: std_logic_vector(full_b_width - 1 downto 0); signal core_s: std_logic_vector(full_s_width - 1 downto 0); signal conv_s: std_logic_vector(s_width - 1 downto 0); signal temp_cout : std_logic; signal internal_clr: std_logic; signal internal_ce: std_logic; signal extra_reg_ce: std_logic; signal override: std_logic; signal logic1: std_logic_vector(0 downto 0); component addsb_11_0_e7b4231f2ca96446 port ( a: in std_logic_vector(22 - 1 downto 0); clk: in std_logic:= '0'; ce: in std_logic:= '0'; s: out std_logic_vector(c_output_width - 1 downto 0); b: in std_logic_vector(22 - 1 downto 0) ); end component; attribute syn_black_box of addsb_11_0_e7b4231f2ca96446: component is true; attribute fpga_dont_touch of addsb_11_0_e7b4231f2ca96446: component is "true"; attribute box_type of addsb_11_0_e7b4231f2ca96446: component is "black_box"; component addsb_11_0_da33f2d4b3b54185 port ( a: in std_logic_vector(20 - 1 downto 0); clk: in std_logic:= '0'; ce: in std_logic:= '0'; s: out std_logic_vector(c_output_width - 1 downto 0); b: in std_logic_vector(20 - 1 downto 0) ); end component; attribute syn_black_box of addsb_11_0_da33f2d4b3b54185: component is true; attribute fpga_dont_touch of addsb_11_0_da33f2d4b3b54185: component is "true"; attribute box_type of addsb_11_0_da33f2d4b3b54185: component is "black_box"; component addsb_11_0_48bcbc42a6774592 port ( a: in std_logic_vector(21 - 1 downto 0); clk: in std_logic:= '0'; ce: in std_logic:= '0'; s: out std_logic_vector(c_output_width - 1 downto 0); b: in std_logic_vector(21 - 1 downto 0) ); end component; attribute syn_black_box of addsb_11_0_48bcbc42a6774592: component is true; attribute fpga_dont_touch of addsb_11_0_48bcbc42a6774592: component is "true"; attribute box_type of addsb_11_0_48bcbc42a6774592: component is "black_box"; begin internal_clr <= (clr or (rst(0))) and ce; internal_ce <= ce and en(0); logic1(0) <= '1'; addsub_process: process (a, b, core_s) begin full_a <= format_input (a, a_width, b_bin_pt - a_bin_pt, a_arith, full_a_width); full_b <= format_input (b, b_width, a_bin_pt - b_bin_pt, b_arith, full_b_width); conv_s <= convert_type (core_s, full_s_width, full_s_bin_pt, full_s_arith, s_width, s_bin_pt, s_arith, quantization, overflow); end process addsub_process; comp0: if ((core_name0 = "addsb_11_0_e7b4231f2ca96446")) generate core_instance0: addsb_11_0_e7b4231f2ca96446 port map ( a => full_a, clk => clk, ce => internal_ce, s => core_s, b => full_b ); end generate; comp1: if ((core_name0 = "addsb_11_0_da33f2d4b3b54185")) generate core_instance1: addsb_11_0_da33f2d4b3b54185 port map ( a => full_a, clk => clk, ce => internal_ce, s => core_s, b => full_b ); end generate; comp2: if ((core_name0 = "addsb_11_0_48bcbc42a6774592")) generate core_instance2: addsb_11_0_48bcbc42a6774592 port map ( a => full_a, clk => clk, ce => internal_ce, s => core_s, b => full_b ); end generate; latency_test: if (extra_registers > 0) generate override_test: if (c_latency > 1) generate override_pipe: synth_reg generic map ( width => 1, latency => c_latency ) port map ( i => logic1, ce => internal_ce, clr => internal_clr, clk => clk, o(0) => override); extra_reg_ce <= ce and en(0) and override; end generate override_test; no_override: if ((c_latency = 0) or (c_latency = 1)) generate extra_reg_ce <= ce and en(0); end generate no_override; extra_reg: synth_reg generic map ( width => s_width, latency => extra_registers ) port map ( i => conv_s, ce => extra_reg_ce, clr => internal_clr, clk => clk, o => s ); cout_test: if (c_has_c_out = 1) generate c_out_extra_reg: synth_reg generic map ( width => 1, latency => extra_registers ) port map ( i(0) => temp_cout, ce => extra_reg_ce, clr => internal_clr, clk => clk, o => c_out ); end generate cout_test; end generate; latency_s: if ((latency = 0) or (extra_registers = 0)) generate s <= conv_s; end generate latency_s; latency0: if (((latency = 0) or (extra_registers = 0)) and (c_has_c_out = 1)) generate c_out(0) <= temp_cout; end generate latency0; tie_dangling_cout: if (c_has_c_out = 0) generate c_out <= "0"; end generate tie_dangling_cout; end architecture behavior; ------------------------------------------------------------------- -- System Generator version 13.2 VHDL source file. -- -- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity xlpassthrough is generic ( din_width : integer := 16; dout_width : integer := 16 ); port ( din : in std_logic_vector (din_width-1 downto 0); dout : out std_logic_vector (dout_width-1 downto 0)); end xlpassthrough; architecture passthrough_arch of xlpassthrough is begin dout <= din; end passthrough_arch; ------------------------------------------------------------------- -- System Generator version 13.2 VHDL source file. -- -- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity convert_func_call is generic ( din_width : integer := 16; din_bin_pt : integer := 4; din_arith : integer := xlUnsigned; dout_width : integer := 8; dout_bin_pt : integer := 2; dout_arith : integer := xlUnsigned; quantization : integer := xlTruncate; overflow : integer := xlWrap); port ( din : in std_logic_vector (din_width-1 downto 0); result : out std_logic_vector (dout_width-1 downto 0)); end convert_func_call; architecture behavior of convert_func_call is begin result <= convert_type(din, din_width, din_bin_pt, din_arith, dout_width, dout_bin_pt, dout_arith, quantization, overflow); end behavior; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity xlconvert is generic ( din_width : integer := 16; din_bin_pt : integer := 4; din_arith : integer := xlUnsigned; dout_width : integer := 8; dout_bin_pt : integer := 2; dout_arith : integer := xlUnsigned; en_width : integer := 1; en_bin_pt : integer := 0; en_arith : integer := xlUnsigned; bool_conversion : integer :=0; latency : integer := 0; quantization : integer := xlTruncate; overflow : integer := xlWrap); port ( din : in std_logic_vector (din_width-1 downto 0); en : in std_logic_vector (en_width-1 downto 0); ce : in std_logic; clr : in std_logic; clk : in std_logic; dout : out std_logic_vector (dout_width-1 downto 0)); end xlconvert; architecture behavior of xlconvert is component synth_reg generic (width : integer; latency : integer); port (i : in std_logic_vector(width-1 downto 0); ce : in std_logic; clr : in std_logic; clk : in std_logic; o : out std_logic_vector(width-1 downto 0)); end component; component convert_func_call generic ( din_width : integer := 16; din_bin_pt : integer := 4; din_arith : integer := xlUnsigned; dout_width : integer := 8; dout_bin_pt : integer := 2; dout_arith : integer := xlUnsigned; quantization : integer := xlTruncate; overflow : integer := xlWrap); port ( din : in std_logic_vector (din_width-1 downto 0); result : out std_logic_vector (dout_width-1 downto 0)); end component; -- synopsys translate_off -- synopsys translate_on signal result : std_logic_vector(dout_width-1 downto 0); signal internal_ce : std_logic; begin -- synopsys translate_off -- synopsys translate_on internal_ce <= ce and en(0); bool_conversion_generate : if (bool_conversion = 1) generate result <= din; end generate; std_conversion_generate : if (bool_conversion = 0) generate convert : convert_func_call generic map ( din_width => din_width, din_bin_pt => din_bin_pt, din_arith => din_arith, dout_width => dout_width, dout_bin_pt => dout_bin_pt, dout_arith => dout_arith, quantization => quantization, overflow => overflow) port map ( din => din, result => result); end generate; latency_test : if (latency > 0) generate reg : synth_reg generic map ( width => dout_width, latency => latency ) port map ( i => result, ce => internal_ce, clr => clr, clk => clk, o => dout ); end generate; latency0 : if (latency = 0) generate dout <= result; end generate latency0; end behavior; ------------------------------------------------------------------- -- System Generator version 13.2 VHDL source file. -- -- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- -- synopsys translate_off library XilinxCoreLib; -- synopsys translate_on library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use work.conv_pkg.all; entity xlmult is generic ( core_name0: string := ""; a_width: integer := 4; a_bin_pt: integer := 2; a_arith: integer := xlSigned; b_width: integer := 4; b_bin_pt: integer := 1; b_arith: integer := xlSigned; p_width: integer := 8; p_bin_pt: integer := 2; p_arith: integer := xlSigned; rst_width: integer := 1; rst_bin_pt: integer := 0; rst_arith: integer := xlUnsigned; en_width: integer := 1; en_bin_pt: integer := 0; en_arith: integer := xlUnsigned; quantization: integer := xlTruncate; overflow: integer := xlWrap; extra_registers: integer := 0; c_a_width: integer := 7; c_b_width: integer := 7; c_type: integer := 0; c_a_type: integer := 0; c_b_type: integer := 0; c_pipelined: integer := 1; c_baat: integer := 4; multsign: integer := xlSigned; c_output_width: integer := 16 ); port ( a: in std_logic_vector(a_width - 1 downto 0); b: in std_logic_vector(b_width - 1 downto 0); ce: in std_logic; clr: in std_logic; clk: in std_logic; core_ce: in std_logic := '0'; core_clr: in std_logic := '0'; core_clk: in std_logic := '0'; rst: in std_logic_vector(rst_width - 1 downto 0); en: in std_logic_vector(en_width - 1 downto 0); p: out std_logic_vector(p_width - 1 downto 0) ); end xlmult; architecture behavior of xlmult is component synth_reg generic ( width: integer := 16; latency: integer := 5 ); port ( i: in std_logic_vector(width - 1 downto 0); ce: in std_logic; clr: in std_logic; clk: in std_logic; o: out std_logic_vector(width - 1 downto 0) ); end component; component mult_11_2_fe92ad55b7635191 port ( b: in std_logic_vector(c_b_width - 1 downto 0); p: out std_logic_vector(c_output_width - 1 downto 0); clk: in std_logic; ce: in std_logic; sclr: in std_logic; a: in std_logic_vector(c_a_width - 1 downto 0) ); end component; attribute syn_black_box of mult_11_2_fe92ad55b7635191: component is true; attribute fpga_dont_touch of mult_11_2_fe92ad55b7635191: component is "true"; attribute box_type of mult_11_2_fe92ad55b7635191: component is "black_box"; signal tmp_a: std_logic_vector(c_a_width - 1 downto 0); signal conv_a: std_logic_vector(c_a_width - 1 downto 0); signal tmp_b: std_logic_vector(c_b_width - 1 downto 0); signal conv_b: std_logic_vector(c_b_width - 1 downto 0); signal tmp_p: std_logic_vector(c_output_width - 1 downto 0); signal conv_p: std_logic_vector(p_width - 1 downto 0); -- synopsys translate_off signal real_a, real_b, real_p: real; -- synopsys translate_on signal rfd: std_logic; signal rdy: std_logic; signal nd: std_logic; signal internal_ce: std_logic; signal internal_clr: std_logic; signal internal_core_ce: std_logic; begin -- synopsys translate_off -- synopsys translate_on internal_ce <= ce and en(0); internal_core_ce <= core_ce and en(0); internal_clr <= (clr or rst(0)) and ce; nd <= internal_ce; input_process: process (a,b) begin tmp_a <= zero_ext(a, c_a_width); tmp_b <= zero_ext(b, c_b_width); end process; output_process: process (tmp_p) begin conv_p <= convert_type(tmp_p, c_output_width, a_bin_pt+b_bin_pt, multsign, p_width, p_bin_pt, p_arith, quantization, overflow); end process; comp0: if ((core_name0 = "mult_11_2_fe92ad55b7635191")) generate core_instance0: mult_11_2_fe92ad55b7635191 port map ( a => tmp_a, clk => clk, ce => internal_ce, sclr => internal_clr, p => tmp_p, b => tmp_b ); end generate; latency_gt_0: if (extra_registers > 0) generate reg: synth_reg generic map ( width => p_width, latency => extra_registers ) port map ( i => conv_p, ce => internal_ce, clr => internal_clr, clk => clk, o => p ); end generate; latency_eq_0: if (extra_registers = 0) generate p <= conv_p; end generate; end architecture behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity constant_822933f89b is port ( op : out std_logic_vector((3 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end constant_822933f89b; architecture behavior of constant_822933f89b is begin op <= "000"; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity constant_a1c496ea88 is port ( op : out std_logic_vector((3 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end constant_a1c496ea88; architecture behavior of constant_a1c496ea88 is begin op <= "001"; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity constant_1f5cc32f1e is port ( op : out std_logic_vector((3 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end constant_1f5cc32f1e; architecture behavior of constant_1f5cc32f1e is begin op <= "010"; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity constant_0f59f02ba5 is port ( op : out std_logic_vector((3 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end constant_0f59f02ba5; architecture behavior of constant_0f59f02ba5 is begin op <= "011"; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity constant_469094441c is port ( op : out std_logic_vector((3 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end constant_469094441c; architecture behavior of constant_469094441c is begin op <= "100"; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity relational_8fc7f5539b is port ( a : in std_logic_vector((3 - 1) downto 0); b : in std_logic_vector((3 - 1) downto 0); op : out std_logic_vector((1 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end relational_8fc7f5539b; architecture behavior of relational_8fc7f5539b is signal a_1_31: unsigned((3 - 1) downto 0); signal b_1_34: unsigned((3 - 1) downto 0); signal result_12_3_rel: boolean; begin a_1_31 <= std_logic_vector_to_unsigned(a); b_1_34 <= std_logic_vector_to_unsigned(b); result_12_3_rel <= a_1_31 = b_1_34; op <= boolean_to_vector(result_12_3_rel); end behavior; ------------------------------------------------------------------- -- System Generator version 13.2 VHDL source file. -- -- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- -- synopsys translate_off library XilinxCoreLib; -- synopsys translate_on library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity xlcounter_limit is generic ( core_name0: string := ""; op_width: integer := 5; op_arith: integer := xlSigned; cnt_63_48: integer:= 0; cnt_47_32: integer:= 0; cnt_31_16: integer:= 0; cnt_15_0: integer:= 0; count_limited: integer := 0 ); port ( ce: in std_logic; clr: in std_logic; clk: in std_logic; op: out std_logic_vector(op_width - 1 downto 0); up: in std_logic_vector(0 downto 0) := (others => '0'); en: in std_logic_vector(0 downto 0); rst: in std_logic_vector(0 downto 0) ); end xlcounter_limit ; architecture behavior of xlcounter_limit is signal high_cnt_to: std_logic_vector(31 downto 0); signal low_cnt_to: std_logic_vector(31 downto 0); signal cnt_to: std_logic_vector(63 downto 0); signal core_sinit, op_thresh0, core_ce: std_logic; signal rst_overrides_en: std_logic; signal op_net: std_logic_vector(op_width - 1 downto 0); -- synopsys translate_off signal real_op : real; -- synopsys translate_on function equals(op, cnt_to : std_logic_vector; width, arith : integer) return std_logic is variable signed_op, signed_cnt_to : signed (width - 1 downto 0); variable unsigned_op, unsigned_cnt_to : unsigned (width - 1 downto 0); variable result : std_logic; begin -- synopsys translate_off if ((is_XorU(op)) or (is_XorU(cnt_to)) ) then result := '0'; return result; end if; -- synopsys translate_on if (op = cnt_to) then result := '1'; else result := '0'; end if; return result; end; component cntr_11_0_e859c6662c373192 port ( clk: in std_logic; ce: in std_logic; SINIT: in std_logic; q: out std_logic_vector(op_width - 1 downto 0) ); end component; attribute syn_black_box of cntr_11_0_e859c6662c373192: component is true; attribute fpga_dont_touch of cntr_11_0_e859c6662c373192: component is "true"; attribute box_type of cntr_11_0_e859c6662c373192: component is "black_box"; component cntr_11_0_862f833518f4973a port ( clk: in std_logic; ce: in std_logic; SINIT: in std_logic; q: out std_logic_vector(op_width - 1 downto 0) ); end component; attribute syn_black_box of cntr_11_0_862f833518f4973a: component is true; attribute fpga_dont_touch of cntr_11_0_862f833518f4973a: component is "true"; attribute box_type of cntr_11_0_862f833518f4973a: component is "black_box"; -- synopsys translate_off constant zeroVec : std_logic_vector(op_width - 1 downto 0) := (others => '0'); constant oneVec : std_logic_vector(op_width - 1 downto 0) := (others => '1'); constant zeroStr : string(1 to op_width) := std_logic_vector_to_bin_string(zeroVec); constant oneStr : string(1 to op_width) := std_logic_vector_to_bin_string(oneVec); -- synopsys translate_on begin -- synopsys translate_off -- synopsys translate_on cnt_to(63 downto 48) <= integer_to_std_logic_vector(cnt_63_48, 16, op_arith); cnt_to(47 downto 32) <= integer_to_std_logic_vector(cnt_47_32, 16, op_arith); cnt_to(31 downto 16) <= integer_to_std_logic_vector(cnt_31_16, 16, op_arith); cnt_to(15 downto 0) <= integer_to_std_logic_vector(cnt_15_0, 16, op_arith); op <= op_net; core_ce <= ce and en(0); rst_overrides_en <= rst(0) or en(0); limit : if (count_limited = 1) generate eq_cnt_to : process (op_net, cnt_to) begin op_thresh0 <= equals(op_net, cnt_to(op_width - 1 downto 0), op_width, op_arith); end process; core_sinit <= (op_thresh0 or clr or rst(0)) and ce and rst_overrides_en; end generate; no_limit : if (count_limited = 0) generate core_sinit <= (clr or rst(0)) and ce and rst_overrides_en; end generate; comp0: if ((core_name0 = "cntr_11_0_e859c6662c373192")) generate core_instance0: cntr_11_0_e859c6662c373192 port map ( clk => clk, ce => core_ce, SINIT => core_sinit, q => op_net ); end generate; comp1: if ((core_name0 = "cntr_11_0_862f833518f4973a")) generate core_instance1: cntr_11_0_862f833518f4973a port map ( clk => clk, ce => core_ce, SINIT => core_sinit, q => op_net ); end generate; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity constant_6293007044 is port ( op : out std_logic_vector((1 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end constant_6293007044; architecture behavior of constant_6293007044 is begin op <= "1"; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity delay_23f848c85b is port ( d : in std_logic_vector((8 - 1) downto 0); q : out std_logic_vector((8 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end delay_23f848c85b; architecture behavior of delay_23f848c85b is signal d_1_22: std_logic_vector((8 - 1) downto 0); type array_type_op_mem_20_24 is array (0 to (2 - 1)) of std_logic_vector((8 - 1) downto 0); signal op_mem_20_24: array_type_op_mem_20_24 := ( "00000000", "00000000"); signal op_mem_20_24_front_din: std_logic_vector((8 - 1) downto 0); signal op_mem_20_24_back: std_logic_vector((8 - 1) downto 0); signal op_mem_20_24_push_front_pop_back_en: std_logic; begin d_1_22 <= d; op_mem_20_24_back <= op_mem_20_24(1); proc_op_mem_20_24: process (clk) is variable i: integer; begin if (clk'event and (clk = '1')) then if ((ce = '1') and (op_mem_20_24_push_front_pop_back_en = '1')) then for i in 1 downto 1 loop op_mem_20_24(i) <= op_mem_20_24(i-1); end loop; op_mem_20_24(0) <= op_mem_20_24_front_din; end if; end if; end process proc_op_mem_20_24; op_mem_20_24_front_din <= d_1_22; op_mem_20_24_push_front_pop_back_en <= '1'; q <= op_mem_20_24_back; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity delay_9565135955 is port ( d : in std_logic_vector((8 - 1) downto 0); q : out std_logic_vector((8 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end delay_9565135955; architecture behavior of delay_9565135955 is signal d_1_22: std_logic_vector((8 - 1) downto 0); type array_type_op_mem_20_24 is array (0 to (3 - 1)) of std_logic_vector((8 - 1) downto 0); signal op_mem_20_24: array_type_op_mem_20_24 := ( "00000000", "00000000", "00000000"); signal op_mem_20_24_front_din: std_logic_vector((8 - 1) downto 0); signal op_mem_20_24_back: std_logic_vector((8 - 1) downto 0); signal op_mem_20_24_push_front_pop_back_en: std_logic; begin d_1_22 <= d; op_mem_20_24_back <= op_mem_20_24(2); proc_op_mem_20_24: process (clk) is variable i: integer; begin if (clk'event and (clk = '1')) then if ((ce = '1') and (op_mem_20_24_push_front_pop_back_en = '1')) then for i in 2 downto 1 loop op_mem_20_24(i) <= op_mem_20_24(i-1); end loop; op_mem_20_24(0) <= op_mem_20_24_front_din; end if; end if; end process proc_op_mem_20_24; op_mem_20_24_front_din <= d_1_22; op_mem_20_24_push_front_pop_back_en <= '1'; q <= op_mem_20_24_back; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity delay_fb08f2e938 is port ( d : in std_logic_vector((8 - 1) downto 0); q : out std_logic_vector((8 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end delay_fb08f2e938; architecture behavior of delay_fb08f2e938 is signal d_1_22: std_logic_vector((8 - 1) downto 0); type array_type_op_mem_20_24 is array (0 to (4 - 1)) of std_logic_vector((8 - 1) downto 0); signal op_mem_20_24: array_type_op_mem_20_24 := ( "00000000", "00000000", "00000000", "00000000"); signal op_mem_20_24_front_din: std_logic_vector((8 - 1) downto 0); signal op_mem_20_24_back: std_logic_vector((8 - 1) downto 0); signal op_mem_20_24_push_front_pop_back_en: std_logic; begin d_1_22 <= d; op_mem_20_24_back <= op_mem_20_24(3); proc_op_mem_20_24: process (clk) is variable i: integer; begin if (clk'event and (clk = '1')) then if ((ce = '1') and (op_mem_20_24_push_front_pop_back_en = '1')) then for i in 3 downto 1 loop op_mem_20_24(i) <= op_mem_20_24(i-1); end loop; op_mem_20_24(0) <= op_mem_20_24_front_din; end if; end if; end process proc_op_mem_20_24; op_mem_20_24_front_din <= d_1_22; op_mem_20_24_push_front_pop_back_en <= '1'; q <= op_mem_20_24_back; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity delay_ebec135d8a is port ( d : in std_logic_vector((8 - 1) downto 0); q : out std_logic_vector((8 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end delay_ebec135d8a; architecture behavior of delay_ebec135d8a is signal d_1_22: std_logic_vector((8 - 1) downto 0); type array_type_op_mem_20_24 is array (0 to (1 - 1)) of std_logic_vector((8 - 1) downto 0); signal op_mem_20_24: array_type_op_mem_20_24 := ( 0 => "00000000"); signal op_mem_20_24_front_din: std_logic_vector((8 - 1) downto 0); signal op_mem_20_24_back: std_logic_vector((8 - 1) downto 0); signal op_mem_20_24_push_front_pop_back_en: std_logic; begin d_1_22 <= d; op_mem_20_24_back <= op_mem_20_24(0); proc_op_mem_20_24: process (clk) is variable i: integer; begin if (clk'event and (clk = '1')) then if ((ce = '1') and (op_mem_20_24_push_front_pop_back_en = '1')) then op_mem_20_24(0) <= op_mem_20_24_front_din; end if; end if; end process proc_op_mem_20_24; op_mem_20_24_front_din <= d_1_22; op_mem_20_24_push_front_pop_back_en <= '1'; q <= op_mem_20_24_back; end behavior; ------------------------------------------------------------------- -- System Generator version 13.2 VHDL source file. -- -- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity xlspram is generic ( core_name0: string := ""; c_width: integer := 12; c_address_width: integer := 4; latency: integer := 1 ); port ( data_in: in std_logic_vector(c_width - 1 downto 0); addr: in std_logic_vector(c_address_width - 1 downto 0); we: in std_logic_vector(0 downto 0); en: in std_logic_vector(0 downto 0); rst: in std_logic_vector(0 downto 0); ce: in std_logic; clk: in std_logic; data_out: out std_logic_vector(c_width - 1 downto 0) ); end xlspram ; architecture behavior of xlspram is component synth_reg generic ( width: integer; latency: integer ); port ( i: in std_logic_vector(width - 1 downto 0); ce: in std_logic; clr: in std_logic; clk: in std_logic; o: out std_logic_vector(width - 1 downto 0) ); end component; signal core_data_out, dly_data_out: std_logic_vector(c_width - 1 downto 0); signal core_we, core_ce, sinit: std_logic; component bmg_62_54b11b852dca329b port ( addra: in std_logic_vector(c_address_width - 1 downto 0); clka: in std_logic; dina: in std_logic_vector(c_width - 1 downto 0); wea: in std_logic_vector(0 downto 0); ena: in std_logic; douta: out std_logic_vector(c_width - 1 downto 0) ); end component; attribute syn_black_box of bmg_62_54b11b852dca329b: component is true; attribute fpga_dont_touch of bmg_62_54b11b852dca329b: component is "true"; attribute box_type of bmg_62_54b11b852dca329b: component is "black_box"; component bmg_62_05852d43925e39b8 port ( addra: in std_logic_vector(c_address_width - 1 downto 0); clka: in std_logic; dina: in std_logic_vector(c_width - 1 downto 0); wea: in std_logic_vector(0 downto 0); ena: in std_logic; douta: out std_logic_vector(c_width - 1 downto 0) ); end component; attribute syn_black_box of bmg_62_05852d43925e39b8: component is true; attribute fpga_dont_touch of bmg_62_05852d43925e39b8: component is "true"; attribute box_type of bmg_62_05852d43925e39b8: component is "black_box"; begin data_out <= dly_data_out; core_we <= we(0); core_ce <= ce and en(0); sinit <= rst(0) and ce; comp0: if ((core_name0 = "bmg_62_54b11b852dca329b")) generate core_instance0: bmg_62_54b11b852dca329b port map ( addra => addr, clka => clk, dina => data_in, wea(0) => core_we, ena => core_ce, douta => core_data_out ); end generate; comp1: if ((core_name0 = "bmg_62_05852d43925e39b8")) generate core_instance1: bmg_62_05852d43925e39b8 port map ( addra => addr, clka => clk, dina => data_in, wea(0) => core_we, ena => core_ce, douta => core_data_out ); end generate; latency_test: if (latency > 1) generate reg: synth_reg generic map ( width => c_width, latency => latency - 1 ) port map ( i => core_data_out, ce => core_ce, clr => '0', clk => clk, o => dly_data_out ); end generate; latency_1: if (latency <= 1) generate dly_data_out <= core_data_out; end generate; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity delay_38f665f8aa is port ( d : in std_logic_vector((5 - 1) downto 0); q : out std_logic_vector((5 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end delay_38f665f8aa; architecture behavior of delay_38f665f8aa is signal d_1_22: std_logic_vector((5 - 1) downto 0); type array_type_op_mem_20_24 is array (0 to (2 - 1)) of std_logic_vector((5 - 1) downto 0); signal op_mem_20_24: array_type_op_mem_20_24 := ( "00000", "00000"); signal op_mem_20_24_front_din: std_logic_vector((5 - 1) downto 0); signal op_mem_20_24_back: std_logic_vector((5 - 1) downto 0); signal op_mem_20_24_push_front_pop_back_en: std_logic; begin d_1_22 <= d; op_mem_20_24_back <= op_mem_20_24(1); proc_op_mem_20_24: process (clk) is variable i: integer; begin if (clk'event and (clk = '1')) then if ((ce = '1') and (op_mem_20_24_push_front_pop_back_en = '1')) then for i in 1 downto 1 loop op_mem_20_24(i) <= op_mem_20_24(i-1); end loop; op_mem_20_24(0) <= op_mem_20_24_front_din; end if; end if; end process proc_op_mem_20_24; op_mem_20_24_front_din <= d_1_22; op_mem_20_24_push_front_pop_back_en <= '1'; q <= op_mem_20_24_back; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity concat_2b3acb49f4 is port ( in0 : in std_logic_vector((1 - 1) downto 0); in1 : in std_logic_vector((1 - 1) downto 0); in2 : in std_logic_vector((1 - 1) downto 0); in3 : in std_logic_vector((1 - 1) downto 0); in4 : in std_logic_vector((1 - 1) downto 0); y : out std_logic_vector((5 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end concat_2b3acb49f4; architecture behavior of concat_2b3acb49f4 is signal in0_1_23: unsigned((1 - 1) downto 0); signal in1_1_27: unsigned((1 - 1) downto 0); signal in2_1_31: unsigned((1 - 1) downto 0); signal in3_1_35: unsigned((1 - 1) downto 0); signal in4_1_39: unsigned((1 - 1) downto 0); signal y_2_1_concat: unsigned((5 - 1) downto 0); begin in0_1_23 <= std_logic_vector_to_unsigned(in0); in1_1_27 <= std_logic_vector_to_unsigned(in1); in2_1_31 <= std_logic_vector_to_unsigned(in2); in3_1_35 <= std_logic_vector_to_unsigned(in3); in4_1_39 <= std_logic_vector_to_unsigned(in4); y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27) & unsigned_to_std_logic_vector(in2_1_31) & unsigned_to_std_logic_vector(in3_1_35) & unsigned_to_std_logic_vector(in4_1_39)); y <= unsigned_to_std_logic_vector(y_2_1_concat); end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity delay_4714bdf2a7 is port ( d : in std_logic_vector((5 - 1) downto 0); q : out std_logic_vector((5 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end delay_4714bdf2a7; architecture behavior of delay_4714bdf2a7 is signal d_1_22: std_logic_vector((5 - 1) downto 0); type array_type_op_mem_20_24 is array (0 to (26 - 1)) of std_logic_vector((5 - 1) downto 0); signal op_mem_20_24: array_type_op_mem_20_24 := ( "00000", "00000", "00000", "00000", "00000", "00000", "00000", "00000", "00000", "00000", "00000", "00000", "00000", "00000", "00000", "00000", "00000", "00000", "00000", "00000", "00000", "00000", "00000", "00000", "00000", "00000"); signal op_mem_20_24_front_din: std_logic_vector((5 - 1) downto 0); signal op_mem_20_24_back: std_logic_vector((5 - 1) downto 0); signal op_mem_20_24_push_front_pop_back_en: std_logic; begin d_1_22 <= d; op_mem_20_24_back <= op_mem_20_24(25); proc_op_mem_20_24: process (clk) is variable i: integer; begin if (clk'event and (clk = '1')) then if ((ce = '1') and (op_mem_20_24_push_front_pop_back_en = '1')) then for i in 25 downto 1 loop op_mem_20_24(i) <= op_mem_20_24(i-1); end loop; op_mem_20_24(0) <= op_mem_20_24_front_din; end if; end if; end process proc_op_mem_20_24; op_mem_20_24_front_din <= d_1_22; op_mem_20_24_push_front_pop_back_en <= '1'; q <= op_mem_20_24_back; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity constant_fdce3802d7 is port ( op : out std_logic_vector((5 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end constant_fdce3802d7; architecture behavior of constant_fdce3802d7 is begin op <= "11001"; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity constant_963ed6358a is port ( op : out std_logic_vector((1 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end constant_963ed6358a; architecture behavior of constant_963ed6358a is begin op <= "0"; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity constant_7244cd602b is port ( op : out std_logic_vector((7 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end constant_7244cd602b; architecture behavior of constant_7244cd602b is begin op <= "0000000"; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity expr_1e33fcde03 is port ( a : in std_logic_vector((1 - 1) downto 0); b : in std_logic_vector((1 - 1) downto 0); dout : out std_logic_vector((1 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end expr_1e33fcde03; architecture behavior of expr_1e33fcde03 is signal a_1_24: unsigned((1 - 1) downto 0); signal b_1_27: unsigned((1 - 1) downto 0); signal bitnot_5_35: unsigned((1 - 1) downto 0); signal fulldout_5_2_bit: unsigned((1 - 1) downto 0); begin a_1_24 <= std_logic_vector_to_unsigned(a); b_1_27 <= std_logic_vector_to_unsigned(b); bitnot_5_35 <= std_logic_vector_to_unsigned(not unsigned_to_std_logic_vector(a_1_24)); fulldout_5_2_bit <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(b_1_27) and unsigned_to_std_logic_vector(bitnot_5_35)); dout <= unsigned_to_std_logic_vector(fulldout_5_2_bit); end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity inverter_e2b989a05e is port ( ip : in std_logic_vector((1 - 1) downto 0); op : out std_logic_vector((1 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end inverter_e2b989a05e; architecture behavior of inverter_e2b989a05e is signal ip_1_26: unsigned((1 - 1) downto 0); type array_type_op_mem_22_20 is array (0 to (1 - 1)) of unsigned((1 - 1) downto 0); signal op_mem_22_20: array_type_op_mem_22_20 := ( 0 => "0"); signal op_mem_22_20_front_din: unsigned((1 - 1) downto 0); signal op_mem_22_20_back: unsigned((1 - 1) downto 0); signal op_mem_22_20_push_front_pop_back_en: std_logic; signal internal_ip_12_1_bitnot: unsigned((1 - 1) downto 0); begin ip_1_26 <= std_logic_vector_to_unsigned(ip); op_mem_22_20_back <= op_mem_22_20(0); proc_op_mem_22_20: process (clk) is variable i: integer; begin if (clk'event and (clk = '1')) then if ((ce = '1') and (op_mem_22_20_push_front_pop_back_en = '1')) then op_mem_22_20(0) <= op_mem_22_20_front_din; end if; end if; end process proc_op_mem_22_20; internal_ip_12_1_bitnot <= std_logic_vector_to_unsigned(not unsigned_to_std_logic_vector(ip_1_26)); op_mem_22_20_push_front_pop_back_en <= '0'; op <= unsigned_to_std_logic_vector(internal_ip_12_1_bitnot); end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity relational_dc5bc996c9 is port ( a : in std_logic_vector((5 - 1) downto 0); b : in std_logic_vector((5 - 1) downto 0); op : out std_logic_vector((1 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end relational_dc5bc996c9; architecture behavior of relational_dc5bc996c9 is signal a_1_31: unsigned((5 - 1) downto 0); signal b_1_34: unsigned((5 - 1) downto 0); signal result_14_3_rel: boolean; begin a_1_31 <= std_logic_vector_to_unsigned(a); b_1_34 <= std_logic_vector_to_unsigned(b); result_14_3_rel <= a_1_31 /= b_1_34; op <= boolean_to_vector(result_14_3_rel); end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity addsub_ba7fff8397 is port ( a : in std_logic_vector((13 - 1) downto 0); b : in std_logic_vector((12 - 1) downto 0); s : out std_logic_vector((12 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end addsub_ba7fff8397; architecture behavior of addsub_ba7fff8397 is signal a_17_32: signed((13 - 1) downto 0); signal b_17_35: unsigned((12 - 1) downto 0); type array_type_op_mem_91_20 is array (0 to (1 - 1)) of unsigned((12 - 1) downto 0); signal op_mem_91_20: array_type_op_mem_91_20 := ( 0 => "000000000000"); signal op_mem_91_20_front_din: unsigned((12 - 1) downto 0); signal op_mem_91_20_back: unsigned((12 - 1) downto 0); signal op_mem_91_20_push_front_pop_back_en: std_logic; type array_type_cout_mem_92_22 is array (0 to (1 - 1)) of unsigned((1 - 1) downto 0); signal cout_mem_92_22: array_type_cout_mem_92_22 := ( 0 => "0"); signal cout_mem_92_22_front_din: unsigned((1 - 1) downto 0); signal cout_mem_92_22_back: unsigned((1 - 1) downto 0); signal cout_mem_92_22_push_front_pop_back_en: std_logic; signal prev_mode_93_22_next: unsigned((3 - 1) downto 0); signal prev_mode_93_22: unsigned((3 - 1) downto 0); signal prev_mode_93_22_reg_i: std_logic_vector((3 - 1) downto 0); signal prev_mode_93_22_reg_o: std_logic_vector((3 - 1) downto 0); signal cast_69_18: signed((14 - 1) downto 0); signal cast_69_22: signed((14 - 1) downto 0); signal internal_s_69_5_addsub: signed((14 - 1) downto 0); signal cast_internal_s_83_3_convert: unsigned((12 - 1) downto 0); begin a_17_32 <= std_logic_vector_to_signed(a); b_17_35 <= std_logic_vector_to_unsigned(b); op_mem_91_20_back <= op_mem_91_20(0); proc_op_mem_91_20: process (clk) is variable i: integer; begin if (clk'event and (clk = '1')) then if ((ce = '1') and (op_mem_91_20_push_front_pop_back_en = '1')) then op_mem_91_20(0) <= op_mem_91_20_front_din; end if; end if; end process proc_op_mem_91_20; cout_mem_92_22_back <= cout_mem_92_22(0); proc_cout_mem_92_22: process (clk) is variable i_x_000000: integer; begin if (clk'event and (clk = '1')) then if ((ce = '1') and (cout_mem_92_22_push_front_pop_back_en = '1')) then cout_mem_92_22(0) <= cout_mem_92_22_front_din; end if; end if; end process proc_cout_mem_92_22; prev_mode_93_22_reg_i <= unsigned_to_std_logic_vector(prev_mode_93_22_next); prev_mode_93_22 <= std_logic_vector_to_unsigned(prev_mode_93_22_reg_o); prev_mode_93_22_reg_inst: entity work.synth_reg_w_init generic map ( init_index => 2, init_value => b"010", latency => 1, width => 3) port map ( ce => ce, clk => clk, clr => clr, i => prev_mode_93_22_reg_i, o => prev_mode_93_22_reg_o); cast_69_18 <= s2s_cast(a_17_32, 0, 14, 0); cast_69_22 <= u2s_cast(b_17_35, 0, 14, 0); internal_s_69_5_addsub <= cast_69_18 + cast_69_22; cast_internal_s_83_3_convert <= s2u_cast(internal_s_69_5_addsub, 0, 12, 0); op_mem_91_20_push_front_pop_back_en <= '0'; cout_mem_92_22_push_front_pop_back_en <= '0'; prev_mode_93_22_next <= std_logic_vector_to_unsigned("000"); s <= unsigned_to_std_logic_vector(cast_internal_s_83_3_convert); end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity constant_9b805894ff is port ( op : out std_logic_vector((12 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end constant_9b805894ff; architecture behavior of constant_9b805894ff is begin op <= "111111111111"; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity constant_7c91b1b314 is port ( op : out std_logic_vector((12 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end constant_7c91b1b314; architecture behavior of constant_7c91b1b314 is begin op <= "000000000001"; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity constant_be6eece885 is port ( op : out std_logic_vector((12 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end constant_be6eece885; architecture behavior of constant_be6eece885 is begin op <= "111111111101"; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity expr_f50101e101 is port ( reset : in std_logic_vector((1 - 1) downto 0); tc : in std_logic_vector((1 - 1) downto 0); dout : out std_logic_vector((1 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end expr_f50101e101; architecture behavior of expr_f50101e101 is signal reset_1_24: boolean; signal tc_1_31: boolean; signal bit_5_25: boolean; signal fulldout_5_2_bitnot: boolean; begin reset_1_24 <= ((reset) = "1"); tc_1_31 <= ((tc) = "1"); bit_5_25 <= ((boolean_to_vector(reset_1_24) or boolean_to_vector(tc_1_31)) = "1"); fulldout_5_2_bitnot <= ((not boolean_to_vector(bit_5_25)) = "1"); dout <= boolean_to_vector(fulldout_5_2_bitnot); end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity mux_b53670f063 is port ( sel : in std_logic_vector((1 - 1) downto 0); d0 : in std_logic_vector((12 - 1) downto 0); d1 : in std_logic_vector((13 - 1) downto 0); y : out std_logic_vector((13 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end mux_b53670f063; architecture behavior of mux_b53670f063 is signal sel_1_20: std_logic; signal d0_1_24: std_logic_vector((12 - 1) downto 0); signal d1_1_27: std_logic_vector((13 - 1) downto 0); signal sel_internal_2_1_convert: std_logic_vector((1 - 1) downto 0); signal unregy_join_6_1: std_logic_vector((13 - 1) downto 0); begin sel_1_20 <= sel(0); d0_1_24 <= d0; d1_1_27 <= d1; sel_internal_2_1_convert <= cast(std_logic_to_vector(sel_1_20), 0, 1, 0, xlUnsigned); proc_switch_6_1: process (d0_1_24, d1_1_27, sel_internal_2_1_convert) is begin case sel_internal_2_1_convert is when "0" => unregy_join_6_1 <= cast(d0_1_24, 0, 13, 0, xlSigned); when others => unregy_join_6_1 <= d1_1_27; end case; end process proc_switch_6_1; y <= unregy_join_6_1; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity relational_d36fe12c1c is port ( a : in std_logic_vector((12 - 1) downto 0); b : in std_logic_vector((12 - 1) downto 0); op : out std_logic_vector((1 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end relational_d36fe12c1c; architecture behavior of relational_d36fe12c1c is signal a_1_31: unsigned((12 - 1) downto 0); signal b_1_34: unsigned((12 - 1) downto 0); signal result_12_3_rel: boolean; begin a_1_31 <= std_logic_vector_to_unsigned(a); b_1_34 <= std_logic_vector_to_unsigned(b); result_12_3_rel <= a_1_31 = b_1_34; op <= boolean_to_vector(result_12_3_rel); end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity delay_9f02caa990 is port ( d : in std_logic_vector((1 - 1) downto 0); q : out std_logic_vector((1 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end delay_9f02caa990; architecture behavior of delay_9f02caa990 is signal d_1_22: std_logic; type array_type_op_mem_20_24 is array (0 to (1 - 1)) of std_logic; signal op_mem_20_24: array_type_op_mem_20_24 := ( 0 => '0'); signal op_mem_20_24_front_din: std_logic; signal op_mem_20_24_back: std_logic; signal op_mem_20_24_push_front_pop_back_en: std_logic; begin d_1_22 <= d(0); op_mem_20_24_back <= op_mem_20_24(0); proc_op_mem_20_24: process (clk) is variable i: integer; begin if (clk'event and (clk = '1')) then if ((ce = '1') and (op_mem_20_24_push_front_pop_back_en = '1')) then op_mem_20_24(0) <= op_mem_20_24_front_din; end if; end if; end process proc_op_mem_20_24; op_mem_20_24_front_din <= d_1_22; op_mem_20_24_push_front_pop_back_en <= '1'; q <= std_logic_to_vector(op_mem_20_24_back); end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity delay_5753e4c658 is port ( d : in std_logic_vector((1 - 1) downto 0); q : out std_logic_vector((1 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end delay_5753e4c658; architecture behavior of delay_5753e4c658 is signal d_1_22: std_logic_vector((1 - 1) downto 0); type array_type_op_mem_20_24 is array (0 to (1 - 1)) of std_logic_vector((1 - 1) downto 0); signal op_mem_20_24: array_type_op_mem_20_24 := ( 0 => "0"); signal op_mem_20_24_front_din: std_logic_vector((1 - 1) downto 0); signal op_mem_20_24_back: std_logic_vector((1 - 1) downto 0); signal op_mem_20_24_push_front_pop_back_en: std_logic; begin d_1_22 <= d; op_mem_20_24_back <= op_mem_20_24(0); proc_op_mem_20_24: process (clk) is variable i: integer; begin if (clk'event and (clk = '1')) then if ((ce = '1') and (op_mem_20_24_push_front_pop_back_en = '1')) then op_mem_20_24(0) <= op_mem_20_24_front_din; end if; end if; end process proc_op_mem_20_24; op_mem_20_24_front_din <= d_1_22; op_mem_20_24_push_front_pop_back_en <= '1'; q <= op_mem_20_24_back; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity expr_305312c97b is port ( d0 : in std_logic_vector((1 - 1) downto 0); d1 : in std_logic_vector((1 - 1) downto 0); rst : in std_logic_vector((1 - 1) downto 0); dout : out std_logic_vector((1 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end expr_305312c97b; architecture behavior of expr_305312c97b is signal d0_1_24: unsigned((1 - 1) downto 0); signal d1_1_28: unsigned((1 - 1) downto 0); signal rst_1_32: unsigned((1 - 1) downto 0); signal bitnot_6_54: unsigned((1 - 1) downto 0); signal bit_6_37: unsigned((1 - 1) downto 0); signal fulldout_6_2_bit: unsigned((1 - 1) downto 0); begin d0_1_24 <= std_logic_vector_to_unsigned(d0); d1_1_28 <= std_logic_vector_to_unsigned(d1); rst_1_32 <= std_logic_vector_to_unsigned(rst); bitnot_6_54 <= std_logic_vector_to_unsigned(not unsigned_to_std_logic_vector(d0_1_24)); bit_6_37 <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(d1_1_28) and unsigned_to_std_logic_vector(bitnot_6_54)); fulldout_6_2_bit <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(rst_1_32) or unsigned_to_std_logic_vector(bit_6_37)); dout <= unsigned_to_std_logic_vector(fulldout_6_2_bit); end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity mcode_block_f4d0462e0e is port ( plbrst : in std_logic_vector((1 - 1) downto 0); plbabus : in std_logic_vector((32 - 1) downto 0); plbpavalid : in std_logic_vector((1 - 1) downto 0); plbrnw : in std_logic_vector((1 - 1) downto 0); plbwrdbus : in std_logic_vector((32 - 1) downto 0); rddata : in std_logic_vector((32 - 1) downto 0); addrpref : in std_logic_vector((20 - 1) downto 0); wrdbusreg : out std_logic_vector((32 - 1) downto 0); addrack : out std_logic_vector((1 - 1) downto 0); rdcomp : out std_logic_vector((1 - 1) downto 0); wrdack : out std_logic_vector((1 - 1) downto 0); bankaddr : out std_logic_vector((2 - 1) downto 0); rnwreg : out std_logic_vector((1 - 1) downto 0); rddack : out std_logic_vector((1 - 1) downto 0); rddbus : out std_logic_vector((32 - 1) downto 0); linearaddr : out std_logic_vector((8 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end mcode_block_f4d0462e0e; architecture behavior of mcode_block_f4d0462e0e is signal plbrst_1_110: unsigned((1 - 1) downto 0); signal plbabus_1_118: unsigned((32 - 1) downto 0); signal plbpavalid_1_127: unsigned((1 - 1) downto 0); signal plbrnw_1_139: unsigned((1 - 1) downto 0); signal plbwrdbus_1_147: unsigned((32 - 1) downto 0); signal rddata_1_158: unsigned((32 - 1) downto 0); signal addrpref_1_166: unsigned((20 - 1) downto 0); signal plbrstreg_12_24_next: boolean; signal plbrstreg_12_24: boolean := false; signal plbabusreg_13_25_next: unsigned((32 - 1) downto 0); signal plbabusreg_13_25: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000"; signal plbpavalidreg_14_28_next: boolean; signal plbpavalidreg_14_28: boolean := false; signal plbrnwreg_15_24_next: unsigned((1 - 1) downto 0); signal plbrnwreg_15_24: unsigned((1 - 1) downto 0) := "0"; signal plbwrdbusreg_16_27_next: unsigned((32 - 1) downto 0); signal plbwrdbusreg_16_27: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000"; signal avalidreg_28_23_next: boolean; signal avalidreg_28_23: boolean := false; signal ps1reg_39_20_next: boolean; signal ps1reg_39_20: boolean := false; signal psreg_47_19_next: boolean; signal psreg_47_19: boolean := false; type array_type_rdcompdelay_58_25 is array (0 to (3 - 1)) of unsigned((1 - 1) downto 0); signal rdcompdelay_58_25: array_type_rdcompdelay_58_25 := ( "0", "0", "0"); signal rdcompdelay_58_25_front_din: unsigned((1 - 1) downto 0); signal rdcompdelay_58_25_back: unsigned((1 - 1) downto 0); signal rdcompdelay_58_25_push_front_pop_back_en: std_logic; signal rdcompreg_62_23_next: unsigned((1 - 1) downto 0); signal rdcompreg_62_23: unsigned((1 - 1) downto 0) := "0"; signal rddackreg_66_23_next: unsigned((1 - 1) downto 0); signal rddackreg_66_23: unsigned((1 - 1) downto 0) := "0"; signal wrdackreg_70_23_next: unsigned((1 - 1) downto 0); signal wrdackreg_70_23: unsigned((1 - 1) downto 0) := "0"; signal rddbusreg_84_23_next: unsigned((32 - 1) downto 0); signal rddbusreg_84_23: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000"; signal bankaddr_20_1_slice: unsigned((2 - 1) downto 0); signal linearaddr_21_1_slice: unsigned((8 - 1) downto 0); signal addrpref_in_32_1_slice: unsigned((20 - 1) downto 0); signal rel_33_4: boolean; signal ps1_join_33_1: boolean; signal ps_42_1_bit: boolean; signal bitnot_49_49: boolean; signal bitnot_49_73: boolean; signal bit_49_49: boolean; signal addrack_49_1_convert: unsigned((1 - 1) downto 0); signal bit_55_43: unsigned((1 - 1) downto 0); signal bitnot_72_35: unsigned((1 - 1) downto 0); signal wrdackreg_72_1_bit: unsigned((1 - 1) downto 0); signal rdsel_76_1_bit: unsigned((1 - 1) downto 0); signal rel_78_4: boolean; signal rddbus1_join_78_1: unsigned((32 - 1) downto 0); signal plbwrdbusreg_97_1_slice: unsigned((32 - 1) downto 0); signal plbrstreg_12_24_next_x_000000: boolean; signal plbpavalidreg_14_28_next_x_000000: boolean; begin plbrst_1_110 <= std_logic_vector_to_unsigned(plbrst); plbabus_1_118 <= std_logic_vector_to_unsigned(plbabus); plbpavalid_1_127 <= std_logic_vector_to_unsigned(plbpavalid); plbrnw_1_139 <= std_logic_vector_to_unsigned(plbrnw); plbwrdbus_1_147 <= std_logic_vector_to_unsigned(plbwrdbus); rddata_1_158 <= std_logic_vector_to_unsigned(rddata); addrpref_1_166 <= std_logic_vector_to_unsigned(addrpref); proc_plbrstreg_12_24: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then plbrstreg_12_24 <= plbrstreg_12_24_next; end if; end if; end process proc_plbrstreg_12_24; proc_plbabusreg_13_25: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then plbabusreg_13_25 <= plbabusreg_13_25_next; end if; end if; end process proc_plbabusreg_13_25; proc_plbpavalidreg_14_28: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then plbpavalidreg_14_28 <= plbpavalidreg_14_28_next; end if; end if; end process proc_plbpavalidreg_14_28; proc_plbrnwreg_15_24: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then plbrnwreg_15_24 <= plbrnwreg_15_24_next; end if; end if; end process proc_plbrnwreg_15_24; proc_plbwrdbusreg_16_27: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then plbwrdbusreg_16_27 <= plbwrdbusreg_16_27_next; end if; end if; end process proc_plbwrdbusreg_16_27; proc_avalidreg_28_23: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then avalidreg_28_23 <= avalidreg_28_23_next; end if; end if; end process proc_avalidreg_28_23; proc_ps1reg_39_20: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then ps1reg_39_20 <= ps1reg_39_20_next; end if; end if; end process proc_ps1reg_39_20; proc_psreg_47_19: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then psreg_47_19 <= psreg_47_19_next; end if; end if; end process proc_psreg_47_19; rdcompdelay_58_25_back <= rdcompdelay_58_25(2); proc_rdcompdelay_58_25: process (clk) is variable i: integer; begin if (clk'event and (clk = '1')) then if ((ce = '1') and (rdcompdelay_58_25_push_front_pop_back_en = '1')) then for i in 2 downto 1 loop rdcompdelay_58_25(i) <= rdcompdelay_58_25(i-1); end loop; rdcompdelay_58_25(0) <= rdcompdelay_58_25_front_din; end if; end if; end process proc_rdcompdelay_58_25; proc_rdcompreg_62_23: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then rdcompreg_62_23 <= rdcompreg_62_23_next; end if; end if; end process proc_rdcompreg_62_23; proc_rddackreg_66_23: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then rddackreg_66_23 <= rddackreg_66_23_next; end if; end if; end process proc_rddackreg_66_23; proc_wrdackreg_70_23: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then wrdackreg_70_23 <= wrdackreg_70_23_next; end if; end if; end process proc_wrdackreg_70_23; proc_rddbusreg_84_23: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then rddbusreg_84_23 <= rddbusreg_84_23_next; end if; end if; end process proc_rddbusreg_84_23; bankaddr_20_1_slice <= u2u_slice(plbabusreg_13_25, 11, 10); linearaddr_21_1_slice <= u2u_slice(plbabusreg_13_25, 9, 2); addrpref_in_32_1_slice <= u2u_slice(plbabusreg_13_25, 31, 12); rel_33_4 <= addrpref_in_32_1_slice = addrpref_1_166; proc_if_33_1: process (rel_33_4) is begin if rel_33_4 then ps1_join_33_1 <= true; else ps1_join_33_1 <= false; end if; end process proc_if_33_1; ps_42_1_bit <= ((boolean_to_vector(ps1_join_33_1) and boolean_to_vector(plbpavalidreg_14_28)) = "1"); bitnot_49_49 <= ((not boolean_to_vector(plbrstreg_12_24)) = "1"); bitnot_49_73 <= ((not boolean_to_vector(psreg_47_19)) = "1"); bit_49_49 <= ((boolean_to_vector(bitnot_49_49) and boolean_to_vector(ps_42_1_bit) and boolean_to_vector(bitnot_49_73)) = "1"); addrack_49_1_convert <= u2u_cast(std_logic_vector_to_unsigned(boolean_to_vector(bit_49_49)), 0, 1, 0); bit_55_43 <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(addrack_49_1_convert) and unsigned_to_std_logic_vector(plbrnwreg_15_24)); bitnot_72_35 <= std_logic_vector_to_unsigned(not unsigned_to_std_logic_vector(plbrnwreg_15_24)); wrdackreg_72_1_bit <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(addrack_49_1_convert) and unsigned_to_std_logic_vector(bitnot_72_35)); rdsel_76_1_bit <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(rdcompdelay_58_25_back) or unsigned_to_std_logic_vector(rdcompreg_62_23)); rel_78_4 <= rdsel_76_1_bit = std_logic_vector_to_unsigned("1"); proc_if_78_1: process (rddata_1_158, rel_78_4) is begin if rel_78_4 then rddbus1_join_78_1 <= rddata_1_158; else rddbus1_join_78_1 <= std_logic_vector_to_unsigned("00000000000000000000000000000000"); end if; end process proc_if_78_1; plbwrdbusreg_97_1_slice <= u2u_slice(plbwrdbus_1_147, 31, 0); plbrstreg_12_24_next_x_000000 <= (plbrst_1_110 /= "0"); plbrstreg_12_24_next <= plbrstreg_12_24_next_x_000000; plbabusreg_13_25_next <= plbabus_1_118; plbpavalidreg_14_28_next_x_000000 <= (plbpavalid_1_127 /= "0"); plbpavalidreg_14_28_next <= plbpavalidreg_14_28_next_x_000000; plbrnwreg_15_24_next <= plbrnw_1_139; plbwrdbusreg_16_27_next <= plbwrdbusreg_97_1_slice; avalidreg_28_23_next <= plbpavalidreg_14_28; ps1reg_39_20_next <= ps1_join_33_1; psreg_47_19_next <= ps_42_1_bit; rdcompdelay_58_25_front_din <= bit_55_43; rdcompdelay_58_25_push_front_pop_back_en <= '1'; rdcompreg_62_23_next <= rdcompdelay_58_25_back; rddackreg_66_23_next <= rdcompreg_62_23; wrdackreg_70_23_next <= wrdackreg_72_1_bit; rddbusreg_84_23_next <= rddbus1_join_78_1; wrdbusreg <= unsigned_to_std_logic_vector(plbwrdbusreg_16_27); addrack <= unsigned_to_std_logic_vector(addrack_49_1_convert); rdcomp <= unsigned_to_std_logic_vector(rdcompreg_62_23); wrdack <= unsigned_to_std_logic_vector(wrdackreg_70_23); bankaddr <= unsigned_to_std_logic_vector(bankaddr_20_1_slice); rnwreg <= unsigned_to_std_logic_vector(plbrnwreg_15_24); rddack <= unsigned_to_std_logic_vector(rddackreg_66_23); rddbus <= unsigned_to_std_logic_vector(rddbusreg_84_23); linearaddr <= unsigned_to_std_logic_vector(linearaddr_21_1_slice); end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity mcode_block_6fff803424 is port ( wrdbus : in std_logic_vector((32 - 1) downto 0); bankaddr : in std_logic_vector((2 - 1) downto 0); linearaddr : in std_logic_vector((8 - 1) downto 0); rnwreg : in std_logic_vector((1 - 1) downto 0); addrack : in std_logic_vector((1 - 1) downto 0); sm_coef_update : in std_logic_vector((1 - 1) downto 0); sm_coef_gain : in std_logic_vector((20 - 1) downto 0); sm_coef_buffer : in std_logic_vector((7 - 1) downto 0); read_bank_out : out std_logic_vector((32 - 1) downto 0); sm_coef_update_din : out std_logic_vector((1 - 1) downto 0); sm_coef_update_en : out std_logic_vector((1 - 1) downto 0); sm_coef_gain_din : out std_logic_vector((20 - 1) downto 0); sm_coef_gain_en : out std_logic_vector((1 - 1) downto 0); sm_coef_buffer_addr : out std_logic_vector((5 - 1) downto 0); sm_coef_buffer_din : out std_logic_vector((7 - 1) downto 0); sm_coef_buffer_we : out std_logic_vector((1 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end mcode_block_6fff803424; architecture behavior of mcode_block_6fff803424 is signal wrdbus_1_173: unsigned((32 - 1) downto 0); signal bankaddr_1_181: unsigned((2 - 1) downto 0); signal linearaddr_1_191: unsigned((8 - 1) downto 0); signal rnwreg_1_203: unsigned((1 - 1) downto 0); signal addrack_1_211: unsigned((1 - 1) downto 0); signal sm_coef_update_1_220: unsigned((1 - 1) downto 0); signal sm_coef_gain_1_236: unsigned((20 - 1) downto 0); signal sm_coef_buffer_1_250: signed((7 - 1) downto 0); signal reg_bank_out_reg_25_30_next: unsigned((32 - 1) downto 0); signal reg_bank_out_reg_25_30: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000"; signal ram_bank_out_reg_49_30_next: unsigned((32 - 1) downto 0); signal ram_bank_out_reg_49_30: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000"; signal sm_coef_buffer_we_reg_62_35_next: boolean; signal sm_coef_buffer_we_reg_62_35: boolean := false; signal sm_coef_buffer_addr_reg_74_1_next: unsigned((5 - 1) downto 0); signal sm_coef_buffer_addr_reg_74_1: unsigned((5 - 1) downto 0) := "00000"; signal read_bank_out_reg_112_31_next: unsigned((32 - 1) downto 0); signal read_bank_out_reg_112_31: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000"; signal bankaddr_reg_115_26_next: unsigned((2 - 1) downto 0); signal bankaddr_reg_115_26: unsigned((2 - 1) downto 0) := "00"; signal sm_coef_buffer_bus_19_1_force: unsigned((7 - 1) downto 0); signal rel_28_4: boolean; signal rel_30_8: boolean; signal reg_bank_out_reg_join_28_1: unsigned((32 - 1) downto 0); signal opcode_42_1_concat: unsigned((12 - 1) downto 0); signal slice_56_39: unsigned((7 - 1) downto 0); signal sm_coef_buffer_din_56_1_force: signed((7 - 1) downto 0); signal opcode_sm_coef_buffer_64_1_concat: unsigned((4 - 1) downto 0); signal rel_65_4: boolean; signal sm_coef_buffer_we_reg_join_65_1: boolean; signal rel_83_4: boolean; signal sm_coef_update_en_join_83_1: boolean; signal rel_89_4: boolean; signal sm_coef_gain_en_join_89_1: boolean; signal slice_104_39: unsigned((1 - 1) downto 0); signal slice_107_37: unsigned((20 - 1) downto 0); signal rel_117_4: boolean; signal rel_120_8: boolean; signal rel_123_8: boolean; signal rel_126_8: boolean; signal read_bank_out_reg_join_117_1: unsigned((32 - 1) downto 0); signal cast_ram_bank_out_reg_49_30_next: unsigned((32 - 1) downto 0); signal cast_sm_coef_buffer_addr_reg_74_1_next: unsigned((5 - 1) downto 0); begin wrdbus_1_173 <= std_logic_vector_to_unsigned(wrdbus); bankaddr_1_181 <= std_logic_vector_to_unsigned(bankaddr); linearaddr_1_191 <= std_logic_vector_to_unsigned(linearaddr); rnwreg_1_203 <= std_logic_vector_to_unsigned(rnwreg); addrack_1_211 <= std_logic_vector_to_unsigned(addrack); sm_coef_update_1_220 <= std_logic_vector_to_unsigned(sm_coef_update); sm_coef_gain_1_236 <= std_logic_vector_to_unsigned(sm_coef_gain); sm_coef_buffer_1_250 <= std_logic_vector_to_signed(sm_coef_buffer); proc_reg_bank_out_reg_25_30: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then reg_bank_out_reg_25_30 <= reg_bank_out_reg_25_30_next; end if; end if; end process proc_reg_bank_out_reg_25_30; proc_ram_bank_out_reg_49_30: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then ram_bank_out_reg_49_30 <= ram_bank_out_reg_49_30_next; end if; end if; end process proc_ram_bank_out_reg_49_30; proc_sm_coef_buffer_we_reg_62_35: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then sm_coef_buffer_we_reg_62_35 <= sm_coef_buffer_we_reg_62_35_next; end if; end if; end process proc_sm_coef_buffer_we_reg_62_35; proc_sm_coef_buffer_addr_reg_74_1: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then sm_coef_buffer_addr_reg_74_1 <= sm_coef_buffer_addr_reg_74_1_next; end if; end if; end process proc_sm_coef_buffer_addr_reg_74_1; proc_read_bank_out_reg_112_31: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then read_bank_out_reg_112_31 <= read_bank_out_reg_112_31_next; end if; end if; end process proc_read_bank_out_reg_112_31; proc_bankaddr_reg_115_26: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then bankaddr_reg_115_26 <= bankaddr_reg_115_26_next; end if; end if; end process proc_bankaddr_reg_115_26; sm_coef_buffer_bus_19_1_force <= signed_to_unsigned(sm_coef_buffer_1_250); rel_28_4 <= linearaddr_1_191 = std_logic_vector_to_unsigned("00000000"); rel_30_8 <= linearaddr_1_191 = std_logic_vector_to_unsigned("00000001"); proc_if_28_1: process (reg_bank_out_reg_25_30, rel_28_4, rel_30_8, sm_coef_gain_1_236, sm_coef_update_1_220) is begin if rel_28_4 then reg_bank_out_reg_join_28_1 <= u2u_cast(sm_coef_update_1_220, 0, 32, 0); elsif rel_30_8 then reg_bank_out_reg_join_28_1 <= u2u_cast(sm_coef_gain_1_236, 0, 32, 0); else reg_bank_out_reg_join_28_1 <= reg_bank_out_reg_25_30; end if; end process proc_if_28_1; opcode_42_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(addrack_1_211) & unsigned_to_std_logic_vector(rnwreg_1_203) & unsigned_to_std_logic_vector(bankaddr_1_181) & unsigned_to_std_logic_vector(linearaddr_1_191)); slice_56_39 <= u2u_slice(wrdbus_1_173, 6, 0); sm_coef_buffer_din_56_1_force <= unsigned_to_signed(slice_56_39); opcode_sm_coef_buffer_64_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(addrack_1_211) & unsigned_to_std_logic_vector(rnwreg_1_203) & unsigned_to_std_logic_vector(bankaddr_1_181)); rel_65_4 <= opcode_sm_coef_buffer_64_1_concat = std_logic_vector_to_unsigned("1000"); proc_if_65_1: process (rel_65_4) is begin if rel_65_4 then sm_coef_buffer_we_reg_join_65_1 <= true; else sm_coef_buffer_we_reg_join_65_1 <= false; end if; end process proc_if_65_1; rel_83_4 <= opcode_42_1_concat = std_logic_vector_to_unsigned("101000000000"); proc_if_83_1: process (rel_83_4) is begin if rel_83_4 then sm_coef_update_en_join_83_1 <= true; else sm_coef_update_en_join_83_1 <= false; end if; end process proc_if_83_1; rel_89_4 <= opcode_42_1_concat = std_logic_vector_to_unsigned("101000000001"); proc_if_89_1: process (rel_89_4) is begin if rel_89_4 then sm_coef_gain_en_join_89_1 <= true; else sm_coef_gain_en_join_89_1 <= false; end if; end process proc_if_89_1; slice_104_39 <= u2u_slice(wrdbus_1_173, 0, 0); slice_107_37 <= u2u_slice(wrdbus_1_173, 19, 0); rel_117_4 <= bankaddr_reg_115_26 = std_logic_vector_to_unsigned("00"); rel_120_8 <= bankaddr_reg_115_26 = std_logic_vector_to_unsigned("01"); rel_123_8 <= bankaddr_reg_115_26 = std_logic_vector_to_unsigned("10"); rel_126_8 <= bankaddr_reg_115_26 = std_logic_vector_to_unsigned("11"); proc_if_117_1: process (ram_bank_out_reg_49_30, read_bank_out_reg_112_31, reg_bank_out_reg_25_30, rel_117_4, rel_120_8, rel_123_8, rel_126_8) is begin if rel_117_4 then read_bank_out_reg_join_117_1 <= ram_bank_out_reg_49_30; elsif rel_120_8 then read_bank_out_reg_join_117_1 <= std_logic_vector_to_unsigned("00000000000000000000000000000000"); elsif rel_123_8 then read_bank_out_reg_join_117_1 <= reg_bank_out_reg_25_30; elsif rel_126_8 then read_bank_out_reg_join_117_1 <= std_logic_vector_to_unsigned("00000000000000000000000000000000"); else read_bank_out_reg_join_117_1 <= read_bank_out_reg_112_31; end if; end process proc_if_117_1; reg_bank_out_reg_25_30_next <= reg_bank_out_reg_join_28_1; cast_ram_bank_out_reg_49_30_next <= u2u_cast(sm_coef_buffer_bus_19_1_force, 0, 32, 0); ram_bank_out_reg_49_30_next <= cast_ram_bank_out_reg_49_30_next; sm_coef_buffer_we_reg_62_35_next <= sm_coef_buffer_we_reg_join_65_1; cast_sm_coef_buffer_addr_reg_74_1_next <= u2u_cast(linearaddr_1_191, 0, 5, 0); sm_coef_buffer_addr_reg_74_1_next <= cast_sm_coef_buffer_addr_reg_74_1_next; read_bank_out_reg_112_31_next <= read_bank_out_reg_join_117_1; bankaddr_reg_115_26_next <= bankaddr_1_181; read_bank_out <= unsigned_to_std_logic_vector(read_bank_out_reg_112_31); sm_coef_update_din <= unsigned_to_std_logic_vector(slice_104_39); sm_coef_update_en <= boolean_to_vector(sm_coef_update_en_join_83_1); sm_coef_gain_din <= unsigned_to_std_logic_vector(slice_107_37); sm_coef_gain_en <= boolean_to_vector(sm_coef_gain_en_join_89_1); sm_coef_buffer_addr <= unsigned_to_std_logic_vector(sm_coef_buffer_addr_reg_74_1); sm_coef_buffer_din <= signed_to_std_logic_vector(sm_coef_buffer_din_56_1_force); sm_coef_buffer_we <= boolean_to_vector(sm_coef_buffer_we_reg_62_35); end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity concat_d0d1b9533e is port ( in0 : in std_logic_vector((8 - 1) downto 0); in1 : in std_logic_vector((8 - 1) downto 0); in2 : in std_logic_vector((8 - 1) downto 0); y : out std_logic_vector((24 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end concat_d0d1b9533e; architecture behavior of concat_d0d1b9533e is signal in0_1_23: unsigned((8 - 1) downto 0); signal in1_1_27: unsigned((8 - 1) downto 0); signal in2_1_31: unsigned((8 - 1) downto 0); signal y_2_1_concat: unsigned((24 - 1) downto 0); begin in0_1_23 <= std_logic_vector_to_unsigned(in0); in1_1_27 <= std_logic_vector_to_unsigned(in1); in2_1_31 <= std_logic_vector_to_unsigned(in2); y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27) & unsigned_to_std_logic_vector(in2_1_31)); y <= unsigned_to_std_logic_vector(y_2_1_concat); end behavior; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; -- Generated from Simulink block "sg_2d_fir/5x5_Filters/Blue_Filter/5x5_Filter/2D_FIR/ABS" entity abs_entity_13c6ead9ca is port ( ce_1: in std_logic; clk_1: in std_logic; in1: in std_logic_vector(21 downto 0); out1: out std_logic_vector(22 downto 0) ); end abs_entity_13c6ead9ca; architecture structural of abs_entity_13c6ead9ca is signal addsub15_s_net_x0: std_logic_vector(21 downto 0); signal ce_1_sg_x0: std_logic; signal clk_1_sg_x0: std_logic; signal mux_y_net_x0: std_logic_vector(22 downto 0); signal negate_op_net: std_logic_vector(22 downto 0); signal register1_q_net: std_logic_vector(21 downto 0); signal register2_q_net: std_logic; signal slice_y_net: std_logic; begin ce_1_sg_x0 <= ce_1; clk_1_sg_x0 <= clk_1; addsub15_s_net_x0 <= in1; out1 <= mux_y_net_x0; mux: entity work.mux_029cd20aa9 port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, clr => '0', d0 => register1_q_net, d1 => negate_op_net, sel(0) => register2_q_net, y => mux_y_net_x0 ); negate: entity work.negate_142bd36a06 port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, clr => '0', ip => addsub15_s_net_x0, op => negate_op_net ); register1: entity work.xlregister generic map ( d_width => 22, init_value => b"0000000000000000000000" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d => addsub15_s_net_x0, en => "1", rst => "0", q => register1_q_net ); register2: entity work.xlregister generic map ( d_width => 1, init_value => b"0" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d(0) => slice_y_net, en => "1", rst => "0", q(0) => register2_q_net ); slice: entity work.xlslice generic map ( new_lsb => 21, new_msb => 21, x_width => 22, y_width => 1 ) port map ( x => addsub15_s_net_x0, y(0) => slice_y_net ); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; -- Generated from Simulink block "sg_2d_fir/5x5_Filters/Blue_Filter/5x5_Filter/2D_FIR/n-tap FIR Compiler Filter1/Rising Edge Detector1" entity rising_edge_detector1_entity_8b96cf7ac4 is port ( ce_1: in std_logic; clk_1: in std_logic; din: in std_logic; dout: out std_logic ); end rising_edge_detector1_entity_8b96cf7ac4; architecture structural of rising_edge_detector1_entity_8b96cf7ac4 is signal ce_1_sg_x1: std_logic; signal clk_1_sg_x1: std_logic; signal inverter_op_net: std_logic; signal logical_y_net_x1: std_logic; signal logical_y_net_x2: std_logic; signal register1_q_net: std_logic; begin ce_1_sg_x1 <= ce_1; clk_1_sg_x1 <= clk_1; logical_y_net_x1 <= din; dout <= logical_y_net_x2; inverter: entity work.inverter_e5b38cca3b port map ( ce => ce_1_sg_x1, clk => clk_1_sg_x1, clr => '0', ip(0) => register1_q_net, op(0) => inverter_op_net ); logical: entity work.logical_80f90b97d0 port map ( ce => '0', clk => '0', clr => '0', d0(0) => logical_y_net_x1, d1(0) => inverter_op_net, y(0) => logical_y_net_x2 ); register1: entity work.xlregister generic map ( d_width => 1, init_value => b"0" ) port map ( ce => ce_1_sg_x1, clk => clk_1_sg_x1, d(0) => logical_y_net_x1, en => "1", rst => "0", q(0) => register1_q_net ); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; -- Generated from Simulink block "sg_2d_fir/5x5_Filters/Blue_Filter/5x5_Filter/2D_FIR/n-tap FIR Compiler Filter1" --entity n_tap_fir_compiler_filter1_entity_2d915a7ccf is -- port ( -- ce_1: in std_logic; -- ce_logic_1: in std_logic; -- clk_1: in std_logic; -- coef: in std_logic_vector(6 downto 0); -- din: in std_logic_vector(7 downto 0); -- load: in std_logic; -- out_x0: out std_logic_vector(18 downto 0) -- ); --end n_tap_fir_compiler_filter1_entity_2d915a7ccf; --architecture structural of n_tap_fir_compiler_filter1_entity_2d915a7ccf is -- signal ce_1_sg_x2: std_logic; -- signal ce_logic_1_sg_x0: std_logic; -- signal clk_1_sg_x2: std_logic; -- signal fir_compiler_5_0_dout_net: std_logic_vector(18 downto 0); -- signal fir_compiler_5_0_rdy_net: std_logic; -- signal l1_x0: std_logic_vector(7 downto 0); -- signal logical_y_net_x2: std_logic; -- signal logical_y_net_x3: std_logic; -- signal register2_q_net: std_logic; -- signal register_q_net_x0: std_logic_vector(18 downto 0); -- signal shared_memory_data_out_net_x0: std_logic_vector(6 downto 0); --begin -- ce_1_sg_x2 <= ce_1; -- ce_logic_1_sg_x0 <= ce_logic_1; -- clk_1_sg_x2 <= clk_1; -- shared_memory_data_out_net_x0 <= coef; -- l1_x0 <= din; -- logical_y_net_x3 <= load; -- out_x0 <= register_q_net_x0; -- fir_compiler_5_0: entity work.xlfir_compiler_acc9ad12ef8a3d59fab07d7a4ad1b777 -- port map ( -- ce => ce_1_sg_x2, -- ce_logic_1 => ce_logic_1_sg_x0, -- clk => clk_1_sg_x2, -- clk_logic_1 => clk_1_sg_x2, -- coef_din => shared_memory_data_out_net_x0, -- coef_ld => logical_y_net_x2, -- coef_we => register2_q_net, -- din => l1_x0, -- src_ce => ce_1_sg_x2, -- src_clk => clk_1_sg_x2, -- dout => fir_compiler_5_0_dout_net, -- rdy => fir_compiler_5_0_rdy_net -- ); -- register2: entity work.xlregister -- generic map ( -- d_width => 1, -- init_value => b"0" -- ) -- port map ( -- ce => ce_1_sg_x2, -- clk => clk_1_sg_x2, -- d(0) => logical_y_net_x3, -- en => "1", -- rst => "0", -- q(0) => register2_q_net -- ); -- register_x0: entity work.xlregister -- generic map ( -- d_width => 19, -- init_value => b"0000000000000000000" -- ) -- port map ( -- ce => ce_1_sg_x2, -- clk => clk_1_sg_x2, -- d => fir_compiler_5_0_dout_net, -- en(0) => fir_compiler_5_0_rdy_net, -- rst => "0", -- q => register_q_net_x0 -- ); -- rising_edge_detector1_8b96cf7ac4: entity work.rising_edge_detector1_entity_8b96cf7ac4 -- port map ( -- ce_1 => ce_1_sg_x2, -- clk_1 => clk_1_sg_x2, -- din => logical_y_net_x3, -- dout => logical_y_net_x2 -- ); --end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; -- Generated from Simulink block "sg_2d_fir/5x5_Filters/Blue_Filter/5x5_Filter/2D_FIR" --entity x2d_fir_entity_587bafe04d is -- port ( -- ce_1: in std_logic; -- ce_logic_1: in std_logic; -- clk_1: in std_logic; -- coef: in std_logic_vector(6 downto 0); -- gain: in std_logic_vector(19 downto 0); -- line1: in std_logic_vector(7 downto 0); -- line2: in std_logic_vector(7 downto 0); -- line3: in std_logic_vector(7 downto 0); -- line4: in std_logic_vector(7 downto 0); -- line5: in std_logic_vector(7 downto 0); -- load_1: in std_logic; -- load_2: in std_logic; -- load_3: in std_logic; -- load_4: in std_logic; -- load_5: in std_logic; -- dout: out std_logic_vector(7 downto 0) -- ); --end x2d_fir_entity_587bafe04d; --architecture structural of x2d_fir_entity_587bafe04d is -- signal addsub15_s_net_x0: std_logic_vector(21 downto 0); -- signal addsub2_s_net: std_logic_vector(19 downto 0); -- signal addsub3_s_net: std_logic_vector(19 downto 0); -- signal addsub4_s_net: std_logic_vector(20 downto 0); -- signal assert_dout_net: std_logic_vector(19 downto 0); -- signal ce_1_sg_x11: std_logic; -- signal ce_logic_1_sg_x5: std_logic; -- signal clk_1_sg_x11: std_logic; -- signal coef_gain_q_net: std_logic_vector(19 downto 0); -- signal convert1_dout_net_x0: std_logic_vector(7 downto 0); -- signal from_register_data_out_net_x0: std_logic_vector(19 downto 0); -- signal l1_x1: std_logic_vector(7 downto 0); -- signal l2_x1: std_logic_vector(7 downto 0); -- signal l3_x1: std_logic_vector(7 downto 0); -- signal l4_x1: std_logic_vector(7 downto 0); -- signal l5_x1: std_logic_vector(7 downto 0); -- signal logical1_y_net_x2: std_logic; -- signal logical2_y_net_x2: std_logic; -- signal logical3_y_net_x2: std_logic; -- signal logical4_y_net_x2: std_logic; -- signal logical_y_net_x4: std_logic; -- signal mult_p_net: std_logic_vector(42 downto 0); -- signal mux_y_net_x0: std_logic_vector(22 downto 0); -- signal register1_q_net: std_logic_vector(18 downto 0); -- signal register2_q_net: std_logic_vector(18 downto 0); -- signal register_q_net_x0: std_logic_vector(18 downto 0); -- signal register_q_net_x1: std_logic_vector(18 downto 0); -- signal register_q_net_x2: std_logic_vector(18 downto 0); -- signal register_q_net_x3: std_logic_vector(18 downto 0); -- signal register_q_net_x4: std_logic_vector(18 downto 0); -- signal shared_memory_data_out_net_x5: std_logic_vector(6 downto 0); --begin -- ce_1_sg_x11 <= ce_1; -- ce_logic_1_sg_x5 <= ce_logic_1; -- clk_1_sg_x11 <= clk_1; -- shared_memory_data_out_net_x5 <= coef; -- from_register_data_out_net_x0 <= gain; -- l1_x1 <= line1; -- l2_x1 <= line2; -- l3_x1 <= line3; -- l4_x1 <= line4; -- l5_x1 <= line5; -- logical_y_net_x4 <= load_1; -- logical1_y_net_x2 <= load_2; -- logical2_y_net_x2 <= load_3; -- logical3_y_net_x2 <= load_4; -- logical4_y_net_x2 <= load_5; -- dout <= convert1_dout_net_x0; -- abs_13c6ead9ca: entity work.abs_entity_13c6ead9ca -- port map ( -- ce_1 => ce_1_sg_x11, -- clk_1 => clk_1_sg_x11, -- in1 => addsub15_s_net_x0, -- out1 => mux_y_net_x0 -- ); -- addsub15: entity work.xladdsub -- generic map ( -- a_arith => xlSigned, -- a_bin_pt => 0, -- a_width => 21, -- b_arith => xlSigned, -- b_bin_pt => 0, -- b_width => 19, -- c_has_c_out => 0, -- c_latency => 1, -- c_output_width => 22, -- core_name0 => "addsb_11_0_e7b4231f2ca96446", -- extra_registers => 0, -- full_s_arith => 2, -- full_s_width => 22, -- latency => 1, -- overflow => 1, -- quantization => 1, -- s_arith => xlSigned, -- s_bin_pt => 0, -- s_width => 22 -- ) -- port map ( -- a => addsub4_s_net, -- b => register2_q_net, -- ce => ce_1_sg_x11, -- clk => clk_1_sg_x11, -- clr => '0', -- en => "1", -- s => addsub15_s_net_x0 -- ); -- addsub2: entity work.xladdsub -- generic map ( -- a_arith => xlSigned, -- a_bin_pt => 0, -- a_width => 19, -- b_arith => xlSigned, -- b_bin_pt => 0, -- b_width => 19, -- c_has_c_out => 0, -- c_latency => 1, -- c_output_width => 20, -- core_name0 => "addsb_11_0_da33f2d4b3b54185", -- extra_registers => 0, -- full_s_arith => 2, -- full_s_width => 20, -- latency => 1, -- overflow => 1, -- quantization => 1, -- s_arith => xlSigned, -- s_bin_pt => 0, -- s_width => 20 -- ) -- port map ( -- a => register_q_net_x0, -- b => register_q_net_x1, -- ce => ce_1_sg_x11, -- clk => clk_1_sg_x11, -- clr => '0', -- en => "1", -- s => addsub2_s_net -- ); -- addsub3: entity work.xladdsub -- generic map ( -- a_arith => xlSigned, -- a_bin_pt => 0, -- a_width => 19, -- b_arith => xlSigned, -- b_bin_pt => 0, -- b_width => 19, -- c_has_c_out => 0, -- c_latency => 1, -- c_output_width => 20, -- core_name0 => "addsb_11_0_da33f2d4b3b54185", -- extra_registers => 0, -- full_s_arith => 2, -- full_s_width => 20, -- latency => 1, -- overflow => 1, -- quantization => 1, -- s_arith => xlSigned, -- s_bin_pt => 0, -- s_width => 20 -- ) -- port map ( -- a => register_q_net_x2, -- b => register_q_net_x3, -- ce => ce_1_sg_x11, -- clk => clk_1_sg_x11, -- clr => '0', -- en => "1", -- s => addsub3_s_net -- ); -- addsub4: entity work.xladdsub -- generic map ( -- a_arith => xlSigned, -- a_bin_pt => 0, -- a_width => 20, -- b_arith => xlSigned, -- b_bin_pt => 0, -- b_width => 20, -- c_has_c_out => 0, -- c_latency => 1, -- c_output_width => 21, -- core_name0 => "addsb_11_0_48bcbc42a6774592", -- extra_registers => 0, -- full_s_arith => 2, -- full_s_width => 21, -- latency => 1, -- overflow => 1, -- quantization => 1, -- s_arith => xlSigned, -- s_bin_pt => 0, -- s_width => 21 -- ) -- port map ( -- a => addsub2_s_net, -- b => addsub3_s_net, -- ce => ce_1_sg_x11, -- clk => clk_1_sg_x11, -- clr => '0', -- en => "1", -- s => addsub4_s_net -- ); -- assert_x0: entity work.xlpassthrough -- generic map ( -- din_width => 20, -- dout_width => 20 -- ) -- port map ( -- din => from_register_data_out_net_x0, -- dout => assert_dout_net -- ); -- coef_gain: entity work.xlregister -- generic map ( -- d_width => 20, -- init_value => b"00000000000000000000" -- ) -- port map ( -- ce => ce_1_sg_x11, -- clk => clk_1_sg_x11, -- d => assert_dout_net, -- en(0) => logical4_y_net_x2, -- rst => "0", -- q => coef_gain_q_net -- ); -- convert1: entity work.xlconvert -- generic map ( -- bool_conversion => 0, -- din_arith => 2, -- din_bin_pt => 17, -- din_width => 43, -- dout_arith => 1, -- dout_bin_pt => 0, -- dout_width => 8, -- latency => 1, -- overflow => xlSaturate, -- quantization => xlTruncate -- ) -- port map ( -- ce => ce_1_sg_x11, -- clk => clk_1_sg_x11, -- clr => '0', -- din => mult_p_net, -- en => "1", -- dout => convert1_dout_net_x0 -- ); -- mult: entity work.xlmult -- generic map ( -- a_arith => xlSigned, -- a_bin_pt => 0, -- a_width => 23, -- b_arith => xlUnsigned, -- b_bin_pt => 17, -- b_width => 20, -- c_a_type => 0, -- c_a_width => 23, -- c_b_type => 1, -- c_b_width => 20, -- c_baat => 23, -- c_output_width => 43, -- c_type => 0, -- core_name0 => "mult_11_2_fe92ad55b7635191", -- extra_registers => 0, -- multsign => 2, -- overflow => 1, -- p_arith => xlSigned, -- p_bin_pt => 17, -- p_width => 43, -- quantization => 1 -- ) -- port map ( -- a => mux_y_net_x0, -- b => coef_gain_q_net, -- ce => ce_1_sg_x11, -- clk => clk_1_sg_x11, -- clr => '0', -- core_ce => ce_1_sg_x11, -- core_clk => clk_1_sg_x11, -- core_clr => '1', -- en => "1", -- rst => "0", -- p => mult_p_net -- ); -- n_tap_fir_compiler_filter1_2d915a7ccf: entity work.fir_1d_trn_load -- generic map( -- IN_DW => 8, -- OUT_DW => 19, -- COEF_DW => 7, -- TAPS => 5, -- DELAY => 8 -- ) -- port map ( -- ce_1 => ce_1_sg_x11, -- clk_1 => clk_1_sg_x11, -- coef => shared_memory_data_out_net_x5, -- din => l1_x1, -- load => logical_y_net_x4, -- out_data => register_q_net_x0 -- ); -- n_tap_fir_compiler_filter2_89a7e4bb68: entity work.fir_1d_trn_load -- generic map( -- IN_DW => 8, -- OUT_DW => 19, -- COEF_DW => 7, -- TAPS => 5, -- DELAY => 8 -- ) -- port map ( -- ce_1 => ce_1_sg_x11, -- clk_1 => clk_1_sg_x11, -- coef => shared_memory_data_out_net_x5, -- din => l2_x1, -- load => logical1_y_net_x2, -- out_data => register_q_net_x1 -- ); -- n_tap_fir_compiler_filter3_2a2055e6f6: entity work.fir_1d_trn_load -- generic map( -- IN_DW => 8, -- OUT_DW => 19, -- COEF_DW => 7, -- TAPS => 5, -- DELAY => 8 -- ) -- port map ( -- ce_1 => ce_1_sg_x11, -- clk_1 => clk_1_sg_x11, -- coef => shared_memory_data_out_net_x5, -- din => l3_x1, -- load => logical2_y_net_x2, -- out_data => register_q_net_x2 -- ); -- n_tap_fir_compiler_filter4_777d8a504f: entity work.fir_1d_trn_load -- generic map( -- IN_DW => 8, -- OUT_DW => 19, -- COEF_DW => 7, -- TAPS => 5, -- DELAY => 8 -- ) -- port map ( -- ce_1 => ce_1_sg_x11, -- clk_1 => clk_1_sg_x11, -- coef => shared_memory_data_out_net_x5, -- din => l4_x1, -- load => logical3_y_net_x2, -- out_data => register_q_net_x3 -- ); -- n_tap_fir_compiler_filter5_552fc58734: entity work.fir_1d_trn_load -- generic map( -- IN_DW => 8, -- OUT_DW => 19, -- COEF_DW => 7, -- TAPS => 5, -- DELAY => 8 -- ) -- port map ( -- ce_1 => ce_1_sg_x11, -- clk_1 => clk_1_sg_x11, -- coef => shared_memory_data_out_net_x5, -- din => l5_x1, -- load => logical4_y_net_x2, -- out_data => register_q_net_x4 -- ); -- register1: entity work.xlregister -- generic map ( -- d_width => 19, -- init_value => b"0000000000000000000" -- ) -- port map ( -- ce => ce_1_sg_x11, -- clk => clk_1_sg_x11, -- d => register_q_net_x4, -- en => "1", -- rst => "0", -- q => register1_q_net -- ); -- register2: entity work.xlregister -- generic map ( -- d_width => 19, -- init_value => b"0000000000000000000" -- ) -- port map ( -- ce => ce_1_sg_x11, -- clk => clk_1_sg_x11, -- d => register1_q_net, -- en => "1", -- rst => "0", -- q => register2_q_net -- ); --end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; -- Generated from Simulink block "sg_2d_fir/5x5_Filters/Blue_Filter/5x5_Filter/load_sequencer" entity load_sequencer_entity_8724dffd75 is port ( ce_1: in std_logic; clk_1: in std_logic; load: in std_logic; load_1: out std_logic; load_2: out std_logic; load_3: out std_logic; load_4: out std_logic; load_5: out std_logic ); end load_sequencer_entity_8724dffd75; architecture structural of load_sequencer_entity_8724dffd75 is signal ce_1_sg_x12: std_logic; signal clk_1_sg_x12: std_logic; signal constant1_op_net: std_logic_vector(2 downto 0); signal constant2_op_net: std_logic_vector(2 downto 0); signal constant3_op_net: std_logic_vector(2 downto 0); signal constant4_op_net: std_logic_vector(2 downto 0); signal constant5_op_net: std_logic_vector(2 downto 0); signal constant7_op_net: std_logic_vector(2 downto 0); signal counter_op_net: std_logic_vector(2 downto 0); signal index_count_op_net: std_logic_vector(2 downto 0); signal logical1_y_net_x3: std_logic; signal logical2_y_net_x3: std_logic; signal logical3_y_net_x3: std_logic; signal logical4_y_net_x3: std_logic; signal logical5_y_net: std_logic; signal logical_y_net_x5: std_logic; signal relational1_op_net: std_logic; signal relational2_op_net: std_logic; signal relational3_op_net: std_logic; signal relational3_op_net_x1: std_logic; signal relational4_op_net: std_logic; signal relational5_op_net: std_logic; signal relational6_op_net: std_logic; signal relational_op_net: std_logic; begin ce_1_sg_x12 <= ce_1; clk_1_sg_x12 <= clk_1; relational3_op_net_x1 <= load; load_1 <= logical_y_net_x5; load_2 <= logical1_y_net_x3; load_3 <= logical2_y_net_x3; load_4 <= logical3_y_net_x3; load_5 <= logical4_y_net_x3; constant1: entity work.constant_822933f89b port map ( ce => '0', clk => '0', clr => '0', op => constant1_op_net ); constant2: entity work.constant_a1c496ea88 port map ( ce => '0', clk => '0', clr => '0', op => constant2_op_net ); constant3: entity work.constant_1f5cc32f1e port map ( ce => '0', clk => '0', clr => '0', op => constant3_op_net ); constant4: entity work.constant_0f59f02ba5 port map ( ce => '0', clk => '0', clr => '0', op => constant4_op_net ); constant5: entity work.constant_469094441c port map ( ce => '0', clk => '0', clr => '0', op => constant5_op_net ); constant7: entity work.constant_469094441c port map ( ce => '0', clk => '0', clr => '0', op => constant7_op_net ); counter: entity work.xlcounter_limit generic map ( cnt_15_0 => 4, cnt_31_16 => 0, cnt_47_32 => 0, cnt_63_48 => 0, core_name0 => "cntr_11_0_e859c6662c373192", count_limited => 1, op_arith => xlUnsigned, op_width => 3 ) port map ( ce => ce_1_sg_x12, clk => clk_1_sg_x12, clr => '0', en(0) => relational3_op_net_x1, rst(0) => relational6_op_net, op => counter_op_net ); index_count: entity work.xlcounter_limit generic map ( cnt_15_0 => 4, cnt_31_16 => 0, cnt_47_32 => 0, cnt_63_48 => 0, core_name0 => "cntr_11_0_e859c6662c373192", count_limited => 1, op_arith => xlUnsigned, op_width => 3 ) port map ( ce => ce_1_sg_x12, clk => clk_1_sg_x12, clr => '0', en(0) => relational6_op_net, rst(0) => logical5_y_net, op => index_count_op_net ); logical: entity work.logical_80f90b97d0 port map ( ce => '0', clk => '0', clr => '0', d0(0) => relational1_op_net, d1(0) => relational3_op_net_x1, y(0) => logical_y_net_x5 ); logical1: entity work.logical_80f90b97d0 port map ( ce => '0', clk => '0', clr => '0', d0(0) => relational2_op_net, d1(0) => relational3_op_net_x1, y(0) => logical1_y_net_x3 ); logical2: entity work.logical_80f90b97d0 port map ( ce => '0', clk => '0', clr => '0', d0(0) => relational3_op_net, d1(0) => relational3_op_net_x1, y(0) => logical2_y_net_x3 ); logical3: entity work.logical_80f90b97d0 port map ( ce => '0', clk => '0', clr => '0', d0(0) => relational4_op_net, d1(0) => relational3_op_net_x1, y(0) => logical3_y_net_x3 ); logical4: entity work.logical_80f90b97d0 port map ( ce => '0', clk => '0', clr => '0', d0(0) => relational5_op_net, d1(0) => relational3_op_net_x1, y(0) => logical4_y_net_x3 ); logical5: entity work.logical_80f90b97d0 port map ( ce => '0', clk => '0', clr => '0', d0(0) => relational_op_net, d1(0) => relational6_op_net, y(0) => logical5_y_net ); relational: entity work.relational_8fc7f5539b port map ( a => index_count_op_net, b => constant7_op_net, ce => '0', clk => '0', clr => '0', op(0) => relational_op_net ); relational1: entity work.relational_8fc7f5539b port map ( a => index_count_op_net, b => constant1_op_net, ce => '0', clk => '0', clr => '0', op(0) => relational1_op_net ); relational2: entity work.relational_8fc7f5539b port map ( a => index_count_op_net, b => constant2_op_net, ce => '0', clk => '0', clr => '0', op(0) => relational2_op_net ); relational3: entity work.relational_8fc7f5539b port map ( a => index_count_op_net, b => constant3_op_net, ce => '0', clk => '0', clr => '0', op(0) => relational3_op_net ); relational4: entity work.relational_8fc7f5539b port map ( a => index_count_op_net, b => constant4_op_net, ce => '0', clk => '0', clr => '0', op(0) => relational4_op_net ); relational5: entity work.relational_8fc7f5539b port map ( a => index_count_op_net, b => constant5_op_net, ce => '0', clk => '0', clr => '0', op(0) => relational5_op_net ); relational6: entity work.relational_8fc7f5539b port map ( a => counter_op_net, b => constant7_op_net, ce => '0', clk => '0', clr => '0', op(0) => relational6_op_net ); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; -- Generated from Simulink block "sg_2d_fir/5x5_Filters/Blue_Filter/5x5_Filter" entity x5x5_filter_entity_e192f59c95 is port ( ce_1: in std_logic; ce_logic_1: in std_logic; clk_1: in std_logic; coef: in std_logic_vector(6 downto 0); gain: in std_logic_vector(19 downto 0); line1: in std_logic_vector(7 downto 0); line2: in std_logic_vector(7 downto 0); line3: in std_logic_vector(7 downto 0); line4: in std_logic_vector(7 downto 0); line5: in std_logic_vector(7 downto 0); load: in std_logic; dout: out std_logic_vector(7 downto 0) ); end x5x5_filter_entity_e192f59c95; architecture structural of x5x5_filter_entity_e192f59c95 is signal ce_1_sg_x13: std_logic; signal ce_logic_1_sg_x6: std_logic; signal clk_1_sg_x13: std_logic; signal convert1_dout_net_x1: std_logic_vector(7 downto 0); signal from_register_data_out_net_x1: std_logic_vector(19 downto 0); signal l1_x2: std_logic_vector(7 downto 0); signal l2_x2: std_logic_vector(7 downto 0); signal l3_x2: std_logic_vector(7 downto 0); signal l4_x2: std_logic_vector(7 downto 0); signal l5_x2: std_logic_vector(7 downto 0); signal logical1_y_net_x3: std_logic; signal logical2_y_net_x3: std_logic; signal logical3_y_net_x3: std_logic; signal logical4_y_net_x3: std_logic; signal logical_y_net_x5: std_logic; signal relational3_op_net_x2: std_logic; signal shared_memory_data_out_net_x6: std_logic_vector(6 downto 0); begin ce_1_sg_x13 <= ce_1; ce_logic_1_sg_x6 <= ce_logic_1; clk_1_sg_x13 <= clk_1; shared_memory_data_out_net_x6 <= coef; from_register_data_out_net_x1 <= gain; l1_x2 <= line1; l2_x2 <= line2; l3_x2 <= line3; l4_x2 <= line4; l5_x2 <= line5; relational3_op_net_x2 <= load; dout <= convert1_dout_net_x1; load_sequencer_8724dffd75: entity work.load_sequencer_entity_8724dffd75 port map ( ce_1 => ce_1_sg_x13, clk_1 => clk_1_sg_x13, load => relational3_op_net_x2, load_1 => logical_y_net_x5, load_2 => logical1_y_net_x3, load_3 => logical2_y_net_x3, load_4 => logical3_y_net_x3, load_5 => logical4_y_net_x3 ); x2d_fir_587bafe04d: entity work.fir_2d_trn_load -- Waj port map ( ce_1 => ce_1_sg_x13, clk_1 => clk_1_sg_x13, coef => shared_memory_data_out_net_x6, gain => from_register_data_out_net_x1, line1 => l1_x2, line2 => l2_x2, line3 => l3_x2, line4 => l4_x2, line5 => l5_x2, load_1 => logical_y_net_x5, load_2 => logical1_y_net_x3, load_3 => logical2_y_net_x3, load_4 => logical3_y_net_x3, load_5 => logical4_y_net_x3, dout => convert1_dout_net_x1 ); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; -- Generated from Simulink block "sg_2d_fir/5x5_Filters/Blue_Filter/Line_Buffer" entity line_buffer_entity_edde027544 is port ( addr: in std_logic_vector(11 downto 0); ce_1: in std_logic; clk_1: in std_logic; data: in std_logic_vector(7 downto 0); l1: out std_logic_vector(7 downto 0); l2: out std_logic_vector(7 downto 0); l3: out std_logic_vector(7 downto 0); l4: out std_logic_vector(7 downto 0); l5: out std_logic_vector(7 downto 0) ); end line_buffer_entity_edde027544; architecture structural of line_buffer_entity_edde027544 is signal blue_x0: std_logic_vector(7 downto 0); signal ce_1_sg_x14: std_logic; signal clk_1_sg_x14: std_logic; signal constant6_op_net: std_logic; signal delay9_q_net: std_logic_vector(7 downto 0); signal l1_x3: std_logic_vector(7 downto 0); signal l2_x3: std_logic_vector(7 downto 0); signal l3_x3: std_logic_vector(7 downto 0); signal l4_x3: std_logic_vector(7 downto 0); signal l5_x3: std_logic_vector(7 downto 0); signal rctr_q_net_x0: std_logic_vector(11 downto 0); signal single_port_ram2_data_out_net: std_logic_vector(7 downto 0); signal single_port_ram3_data_out_net: std_logic_vector(7 downto 0); signal single_port_ram_data_out_net: std_logic_vector(7 downto 0); begin rctr_q_net_x0 <= addr; ce_1_sg_x14 <= ce_1; clk_1_sg_x14 <= clk_1; blue_x0 <= data; l1 <= l1_x3; l2 <= l2_x3; l3 <= l3_x3; l4 <= l4_x3; l5 <= l5_x3; constant6: entity work.constant_6293007044 port map ( ce => '0', clk => '0', clr => '0', op(0) => constant6_op_net ); delay1: entity work.delay_23f848c85b port map ( ce => ce_1_sg_x14, clk => clk_1_sg_x14, clr => '0', d => single_port_ram2_data_out_net, q => l3_x3 ); delay2: entity work.delay_9565135955 port map ( ce => ce_1_sg_x14, clk => clk_1_sg_x14, clr => '0', d => single_port_ram3_data_out_net, q => l4_x3 ); delay7: entity work.delay_fb08f2e938 port map ( ce => ce_1_sg_x14, clk => clk_1_sg_x14, clr => '0', d => delay9_q_net, q => l5_x3 ); delay8: entity work.delay_ebec135d8a port map ( ce => ce_1_sg_x14, clk => clk_1_sg_x14, clr => '0', d => single_port_ram_data_out_net, q => l2_x3 ); delay9: entity work.delay_23f848c85b port map ( ce => ce_1_sg_x14, clk => clk_1_sg_x14, clr => '0', d => blue_x0, q => delay9_q_net ); single_port_ram: entity work.xlspram generic map ( c_address_width => 12, c_width => 8, core_name0 => "bmg_62_54b11b852dca329b", latency => 1 ) port map ( addr => rctr_q_net_x0, ce => ce_1_sg_x14, clk => clk_1_sg_x14, data_in => single_port_ram2_data_out_net, en => "1", rst => "0", we(0) => constant6_op_net, data_out => single_port_ram_data_out_net ); single_port_ram1: entity work.xlspram generic map ( c_address_width => 12, c_width => 8, core_name0 => "bmg_62_54b11b852dca329b", latency => 1 ) port map ( addr => rctr_q_net_x0, ce => ce_1_sg_x14, clk => clk_1_sg_x14, data_in => single_port_ram_data_out_net, en => "1", rst => "0", we(0) => constant6_op_net, data_out => l1_x3 ); single_port_ram2: entity work.xlspram generic map ( c_address_width => 12, c_width => 8, core_name0 => "bmg_62_54b11b852dca329b", latency => 1 ) port map ( addr => rctr_q_net_x0, ce => ce_1_sg_x14, clk => clk_1_sg_x14, data_in => single_port_ram3_data_out_net, en => "1", rst => "0", we(0) => constant6_op_net, data_out => single_port_ram2_data_out_net ); single_port_ram3: entity work.xlspram generic map ( c_address_width => 12, c_width => 8, core_name0 => "bmg_62_54b11b852dca329b", latency => 1 ) port map ( addr => rctr_q_net_x0, ce => ce_1_sg_x14, clk => clk_1_sg_x14, data_in => delay9_q_net, en => "1", rst => "0", we(0) => constant6_op_net, data_out => single_port_ram3_data_out_net ); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; -- Generated from Simulink block "sg_2d_fir/5x5_Filters/Blue_Filter" entity blue_filter_entity_d29ca0c8b1 is port ( addr: in std_logic_vector(11 downto 0); ce_1: in std_logic; ce_logic_1: in std_logic; clk_1: in std_logic; coef: in std_logic_vector(6 downto 0); din: in std_logic_vector(7 downto 0); gain: in std_logic_vector(19 downto 0); load: in std_logic; dout: out std_logic_vector(7 downto 0) ); end blue_filter_entity_d29ca0c8b1; architecture structural of blue_filter_entity_d29ca0c8b1 is signal blue_x1: std_logic_vector(7 downto 0); signal ce_1_sg_x15: std_logic; signal ce_logic_1_sg_x7: std_logic; signal clk_1_sg_x15: std_logic; signal convert1_dout_net_x2: std_logic_vector(7 downto 0); signal from_register_data_out_net_x2: std_logic_vector(19 downto 0); signal l1_x3: std_logic_vector(7 downto 0); signal l2_x3: std_logic_vector(7 downto 0); signal l3_x3: std_logic_vector(7 downto 0); signal l4_x3: std_logic_vector(7 downto 0); signal l5_x3: std_logic_vector(7 downto 0); signal rctr_q_net_x1: std_logic_vector(11 downto 0); signal relational3_op_net_x3: std_logic; signal shared_memory_data_out_net_x7: std_logic_vector(6 downto 0); begin rctr_q_net_x1 <= addr; ce_1_sg_x15 <= ce_1; ce_logic_1_sg_x7 <= ce_logic_1; clk_1_sg_x15 <= clk_1; shared_memory_data_out_net_x7 <= coef; blue_x1 <= din; from_register_data_out_net_x2 <= gain; relational3_op_net_x3 <= load; dout <= convert1_dout_net_x2; line_buffer_edde027544: entity work.line_buffer_entity_edde027544 port map ( addr => rctr_q_net_x1, ce_1 => ce_1_sg_x15, clk_1 => clk_1_sg_x15, data => blue_x1, l1 => l1_x3, l2 => l2_x3, l3 => l3_x3, l4 => l4_x3, l5 => l5_x3 ); x5x5_filter_e192f59c95: entity work.x5x5_filter_entity_e192f59c95 port map ( ce_1 => ce_1_sg_x15, ce_logic_1 => ce_logic_1_sg_x7, clk_1 => clk_1_sg_x15, coef => shared_memory_data_out_net_x7, gain => from_register_data_out_net_x2, line1 => l1_x3, line2 => l2_x3, line3 => l3_x3, line4 => l4_x3, line5 => l5_x3, load => relational3_op_net_x3, dout => convert1_dout_net_x2 ); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; -- Generated from Simulink block "sg_2d_fir/5x5_Filters/Ctrl_Delay/Line_Buffer" entity line_buffer_entity_d14b7609fd is port ( addr: in std_logic_vector(11 downto 0); ce_1: in std_logic; clk_1: in std_logic; data: in std_logic_vector(4 downto 0); l3_x0: out std_logic_vector(4 downto 0) ); end line_buffer_entity_d14b7609fd; architecture structural of line_buffer_entity_d14b7609fd is signal ce_1_sg_x16: std_logic; signal clk_1_sg_x16: std_logic; signal concat_y_net_x0: std_logic_vector(4 downto 0); signal constant6_op_net: std_logic; signal delay9_q_net: std_logic_vector(4 downto 0); signal l3_x1: std_logic_vector(4 downto 0); signal rctr_q_net_x2: std_logic_vector(11 downto 0); signal single_port_ram2_data_out_net: std_logic_vector(4 downto 0); signal single_port_ram3_data_out_net: std_logic_vector(4 downto 0); begin rctr_q_net_x2 <= addr; ce_1_sg_x16 <= ce_1; clk_1_sg_x16 <= clk_1; concat_y_net_x0 <= data; l3_x0 <= l3_x1; constant6: entity work.constant_6293007044 port map ( ce => '0', clk => '0', clr => '0', op(0) => constant6_op_net ); delay1: entity work.delay_38f665f8aa port map ( ce => ce_1_sg_x16, clk => clk_1_sg_x16, clr => '0', d => single_port_ram2_data_out_net, q => l3_x1 ); delay9: entity work.delay_38f665f8aa port map ( ce => ce_1_sg_x16, clk => clk_1_sg_x16, clr => '0', d => concat_y_net_x0, q => delay9_q_net ); single_port_ram2: entity work.xlspram generic map ( c_address_width => 12, c_width => 5, core_name0 => "bmg_62_05852d43925e39b8", latency => 1 ) port map ( addr => rctr_q_net_x2, ce => ce_1_sg_x16, clk => clk_1_sg_x16, data_in => single_port_ram3_data_out_net, en => "1", rst => "0", we(0) => constant6_op_net, data_out => single_port_ram2_data_out_net ); single_port_ram3: entity work.xlspram generic map ( c_address_width => 12, c_width => 5, core_name0 => "bmg_62_05852d43925e39b8", latency => 1 ) port map ( addr => rctr_q_net_x2, ce => ce_1_sg_x16, clk => clk_1_sg_x16, data_in => delay9_q_net, en => "1", rst => "0", we(0) => constant6_op_net, data_out => single_port_ram3_data_out_net ); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; -- Generated from Simulink block "sg_2d_fir/5x5_Filters/Ctrl_Delay" entity ctrl_delay_entity_b2aeac3e46 is port ( addr: in std_logic_vector(11 downto 0); av_i: in std_logic; ce_1: in std_logic; clk_1: in std_logic; hb_i: in std_logic; hs_i: in std_logic; vb_i: in std_logic; vs_i: in std_logic; av_o: out std_logic; hb_o: out std_logic; hs_o: out std_logic; vb_o: out std_logic; vs_o: out std_logic ); end ctrl_delay_entity_b2aeac3e46; architecture structural of ctrl_delay_entity_b2aeac3e46 is signal active_video_i_net_x0: std_logic; signal bit0_y_net_x0: std_logic; signal bit1_y_net_x0: std_logic; signal bit2_y_net_x0: std_logic; signal bit3_y_net_x0: std_logic; signal bit4_y_net_x0: std_logic; signal ce_1_sg_x17: std_logic; signal clk_1_sg_x17: std_logic; signal concat_y_net_x0: std_logic_vector(4 downto 0); signal delay7_q_net: std_logic_vector(4 downto 0); signal hblank_i_net_x0: std_logic; signal hsync_i_net_x0: std_logic; signal l3_x1: std_logic_vector(4 downto 0); signal rctr_q_net_x3: std_logic_vector(11 downto 0); signal vblank_i_net_x0: std_logic; signal vsync_i_net_x0: std_logic; begin rctr_q_net_x3 <= addr; active_video_i_net_x0 <= av_i; ce_1_sg_x17 <= ce_1; clk_1_sg_x17 <= clk_1; hblank_i_net_x0 <= hb_i; hsync_i_net_x0 <= hs_i; vblank_i_net_x0 <= vb_i; vsync_i_net_x0 <= vs_i; av_o <= bit4_y_net_x0; hb_o <= bit0_y_net_x0; hs_o <= bit2_y_net_x0; vb_o <= bit1_y_net_x0; vs_o <= bit3_y_net_x0; bit0: entity work.xlslice generic map ( new_lsb => 0, new_msb => 0, x_width => 5, y_width => 1 ) port map ( x => delay7_q_net, y(0) => bit0_y_net_x0 ); bit1: entity work.xlslice generic map ( new_lsb => 1, new_msb => 1, x_width => 5, y_width => 1 ) port map ( x => delay7_q_net, y(0) => bit1_y_net_x0 ); bit2: entity work.xlslice generic map ( new_lsb => 2, new_msb => 2, x_width => 5, y_width => 1 ) port map ( x => delay7_q_net, y(0) => bit2_y_net_x0 ); bit3: entity work.xlslice generic map ( new_lsb => 3, new_msb => 3, x_width => 5, y_width => 1 ) port map ( x => delay7_q_net, y(0) => bit3_y_net_x0 ); bit4: entity work.xlslice generic map ( new_lsb => 4, new_msb => 4, x_width => 5, y_width => 1 ) port map ( x => delay7_q_net, y(0) => bit4_y_net_x0 ); concat: entity work.concat_2b3acb49f4 port map ( ce => '0', clk => '0', clr => '0', in0(0) => active_video_i_net_x0, in1(0) => vsync_i_net_x0, in2(0) => hsync_i_net_x0, in3(0) => vblank_i_net_x0, in4(0) => hblank_i_net_x0, y => concat_y_net_x0 ); delay7: entity work.delay_4714bdf2a7 port map ( ce => ce_1_sg_x17, clk => clk_1_sg_x17, clr => '0', d => l3_x1, q => delay7_q_net ); line_buffer_d14b7609fd: entity work.line_buffer_entity_d14b7609fd port map ( addr => rctr_q_net_x3, ce_1 => ce_1_sg_x17, clk_1 => clk_1_sg_x17, data => concat_y_net_x0, l3_x0 => l3_x1 ); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; -- Generated from Simulink block "sg_2d_fir/5x5_Filters/coefficient_memory" entity coefficient_memory_entity_d275723ee2 is port ( ce_1: in std_logic; clk_1: in std_logic; from_register1: in std_logic; vsync: in std_logic; constant1_x0: out std_logic; constant2_x0: out std_logic_vector(6 downto 0); counter_x0: out std_logic_vector(4 downto 0); load: out std_logic ); end coefficient_memory_entity_d275723ee2; architecture structural of coefficient_memory_entity_d275723ee2 is signal ce_1_sg_x50: std_logic; signal clk_1_sg_x50: std_logic; signal constant1_op_net_x0: std_logic; signal constant2_op_net_x0: std_logic_vector(6 downto 0); signal constant_op_net: std_logic_vector(4 downto 0); signal convert1_dout_net: std_logic; signal convert_dout_net: std_logic; signal counter_op_net_x0: std_logic_vector(4 downto 0); signal expression_dout_net: std_logic; signal from_register1_data_out_net_x0: std_logic; signal inverter_op_net: std_logic; signal register1_q_net: std_logic; signal register_q_net: std_logic; signal relational3_op_net_x10: std_logic; signal vsync_i_net_x1: std_logic; begin ce_1_sg_x50 <= ce_1; clk_1_sg_x50 <= clk_1; from_register1_data_out_net_x0 <= from_register1; vsync_i_net_x1 <= vsync; constant1_x0 <= constant1_op_net_x0; constant2_x0 <= constant2_op_net_x0; counter_x0 <= counter_op_net_x0; load <= relational3_op_net_x10; constant1: entity work.constant_963ed6358a port map ( ce => '0', clk => '0', clr => '0', op(0) => constant1_op_net_x0 ); constant2: entity work.constant_7244cd602b port map ( ce => '0', clk => '0', clr => '0', op => constant2_op_net_x0 ); constant_x0: entity work.constant_fdce3802d7 port map ( ce => '0', clk => '0', clr => '0', op => constant_op_net ); convert: entity work.xlconvert generic map ( bool_conversion => 1, din_arith => 1, din_bin_pt => 0, din_width => 1, dout_arith => 1, dout_bin_pt => 0, dout_width => 1, latency => 0, overflow => xlWrap, quantization => xlTruncate ) port map ( ce => ce_1_sg_x50, clk => clk_1_sg_x50, clr => '0', din(0) => register1_q_net, en => "1", dout(0) => convert_dout_net ); convert1: entity work.xlconvert generic map ( bool_conversion => 1, din_arith => 1, din_bin_pt => 0, din_width => 1, dout_arith => 1, dout_bin_pt => 0, dout_width => 1, latency => 0, overflow => xlWrap, quantization => xlTruncate ) port map ( ce => ce_1_sg_x50, clk => clk_1_sg_x50, clr => '0', din(0) => inverter_op_net, en => "1", dout(0) => convert1_dout_net ); counter: entity work.xlcounter_limit generic map ( cnt_15_0 => 25, cnt_31_16 => 0, cnt_47_32 => 0, cnt_63_48 => 0, core_name0 => "cntr_11_0_862f833518f4973a", count_limited => 1, op_arith => xlUnsigned, op_width => 5 ) port map ( ce => ce_1_sg_x50, clk => clk_1_sg_x50, clr => '0', en(0) => relational3_op_net_x10, rst(0) => convert_dout_net, op => counter_op_net_x0 ); expression: entity work.expr_1e33fcde03 port map ( a(0) => vsync_i_net_x1, b(0) => register_q_net, ce => '0', clk => '0', clr => '0', dout(0) => expression_dout_net ); inverter: entity work.inverter_e2b989a05e port map ( ce => ce_1_sg_x50, clk => clk_1_sg_x50, clr => '0', ip(0) => from_register1_data_out_net_x0, op(0) => inverter_op_net ); register1: entity work.xlregister generic map ( d_width => 1, init_value => b"0" ) port map ( ce => ce_1_sg_x50, clk => clk_1_sg_x50, d(0) => expression_dout_net, en => "1", rst(0) => convert1_dout_net, q(0) => register1_q_net ); register_x0: entity work.xlregister generic map ( d_width => 1, init_value => b"0" ) port map ( ce => ce_1_sg_x50, clk => clk_1_sg_x50, d(0) => vsync_i_net_x1, en => "1", rst => "0", q(0) => register_q_net ); relational3: entity work.relational_dc5bc996c9 port map ( a => constant_op_net, b => counter_op_net_x0, ce => '0', clk => '0', clr => '0', op(0) => relational3_op_net_x10 ); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; -- Generated from Simulink block "sg_2d_fir/5x5_Filters/line_ctrs/loop_ctr" entity loop_ctr_entity_861427efa6 is port ( ce_1: in std_logic; clk_1: in std_logic; reset: in std_logic; count: out std_logic_vector(11 downto 0) ); end loop_ctr_entity_861427efa6; architecture structural of loop_ctr_entity_861427efa6 is signal addsub1_s_net: std_logic_vector(11 downto 0); signal bool2_dout_net: std_logic_vector(12 downto 0); signal bool_dout_net: std_logic; signal ce_1_sg_x51: std_logic; signal clk_1_sg_x51: std_logic; signal constant1_op_net: std_logic_vector(11 downto 0); signal constant6_op_net: std_logic_vector(11 downto 0); signal constant7_op_net: std_logic_vector(11 downto 0); signal expression_dout_net_x0: std_logic; signal expression_dout_net_x1: std_logic; signal mux_y_net: std_logic_vector(12 downto 0); signal rctr_q_net_x8: std_logic_vector(11 downto 0); signal relational5_op_net: std_logic; signal tcfb1_q_net: std_logic; signal tcfb2_q_net: std_logic; begin ce_1_sg_x51 <= ce_1; clk_1_sg_x51 <= clk_1; expression_dout_net_x1 <= reset; count <= rctr_q_net_x8; addsub1: entity work.addsub_ba7fff8397 port map ( a => mux_y_net, b => constant6_op_net, ce => ce_1_sg_x51, clk => clk_1_sg_x51, clr => '0', s => addsub1_s_net ); bool: entity work.xlconvert generic map ( bool_conversion => 1, din_arith => 1, din_bin_pt => 0, din_width => 1, dout_arith => 1, dout_bin_pt => 0, dout_width => 1, latency => 0, overflow => xlWrap, quantization => xlTruncate ) port map ( ce => ce_1_sg_x51, clk => clk_1_sg_x51, clr => '0', din(0) => expression_dout_net_x1, en => "1", dout(0) => bool_dout_net ); bool2: entity work.xlconvert generic map ( bool_conversion => 0, din_arith => 1, din_bin_pt => 0, din_width => 12, dout_arith => 2, dout_bin_pt => 0, dout_width => 13, latency => 0, overflow => xlWrap, quantization => xlTruncate ) port map ( ce => ce_1_sg_x51, clk => clk_1_sg_x51, clr => '0', din => rctr_q_net_x8, en => "1", dout => bool2_dout_net ); constant1: entity work.constant_9b805894ff port map ( ce => '0', clk => '0', clr => '0', op => constant1_op_net ); constant6: entity work.constant_7c91b1b314 port map ( ce => '0', clk => '0', clr => '0', op => constant6_op_net ); constant7: entity work.constant_be6eece885 port map ( ce => '0', clk => '0', clr => '0', op => constant7_op_net ); expression: entity work.expr_f50101e101 port map ( ce => '0', clk => '0', clr => '0', reset(0) => tcfb2_q_net, tc(0) => tcfb1_q_net, dout(0) => expression_dout_net_x0 ); mux: entity work.mux_b53670f063 port map ( ce => '0', clk => '0', clr => '0', d0 => constant1_op_net, d1 => bool2_dout_net, sel(0) => expression_dout_net_x0, y => mux_y_net ); rctr: entity work.xlregister generic map ( d_width => 12, init_value => b"000000000000" ) port map ( ce => ce_1_sg_x51, clk => clk_1_sg_x51, d => addsub1_s_net, en => "1", rst => "0", q => rctr_q_net_x8 ); relational5: entity work.relational_d36fe12c1c port map ( a => rctr_q_net_x8, b => constant7_op_net, ce => '0', clk => '0', clr => '0', op(0) => relational5_op_net ); tcfb1: entity work.delay_9f02caa990 port map ( ce => ce_1_sg_x51, clk => clk_1_sg_x51, clr => '0', d(0) => relational5_op_net, q(0) => tcfb1_q_net ); tcfb2: entity work.delay_9f02caa990 port map ( ce => ce_1_sg_x51, clk => clk_1_sg_x51, clr => '0', d(0) => bool_dout_net, q(0) => tcfb2_q_net ); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; -- Generated from Simulink block "sg_2d_fir/5x5_Filters/line_ctrs" entity line_ctrs_entity_8878c4bf27 is port ( ce_1: in std_logic; clk_1: in std_logic; h: in std_logic; rst: in std_logic; addr: out std_logic_vector(11 downto 0) ); end line_ctrs_entity_8878c4bf27; architecture structural of line_ctrs_entity_8878c4bf27 is signal ce_1_sg_x52: std_logic; signal clk_1_sg_x52: std_logic; signal delay_q_net: std_logic; signal expression_dout_net_x1: std_logic; signal hsync_i_net_x1: std_logic; signal rctr_q_net_x9: std_logic_vector(11 downto 0); signal reset_net_x0: std_logic; begin ce_1_sg_x52 <= ce_1; clk_1_sg_x52 <= clk_1; hsync_i_net_x1 <= h; reset_net_x0 <= rst; addr <= rctr_q_net_x9; delay: entity work.delay_5753e4c658 port map ( ce => ce_1_sg_x52, clk => clk_1_sg_x52, clr => '0', d(0) => hsync_i_net_x1, q(0) => delay_q_net ); expression: entity work.expr_305312c97b port map ( ce => '0', clk => '0', clr => '0', d0(0) => hsync_i_net_x1, d1(0) => delay_q_net, rst(0) => reset_net_x0, dout(0) => expression_dout_net_x1 ); loop_ctr_861427efa6: entity work.loop_ctr_entity_861427efa6 port map ( ce_1 => ce_1_sg_x52, clk_1 => clk_1_sg_x52, reset => expression_dout_net_x1, count => rctr_q_net_x9 ); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; -- Generated from Simulink block "sg_2d_fir/5x5_Filters" entity x5x5_filters_entity_1ec75b0e3e is port ( av_i: in std_logic; b: in std_logic_vector(7 downto 0); ce_1: in std_logic; ce_logic_1: in std_logic; clk_1: in std_logic; from_register: in std_logic_vector(19 downto 0); from_register1: in std_logic; g: in std_logic_vector(7 downto 0); hb_i: in std_logic; hs_i: in std_logic; r: in std_logic_vector(7 downto 0); rst: in std_logic; shared_memory: in std_logic_vector(6 downto 0); vb_i: in std_logic; vs_i: in std_logic; b_o: out std_logic_vector(7 downto 0); coefficient_memory: out std_logic; coefficient_memory_x0: out std_logic_vector(6 downto 0); coefficient_memory_x1: out std_logic_vector(4 downto 0); de_o: out std_logic; g_o: out std_logic_vector(7 downto 0); hb_o: out std_logic; hs_o: out std_logic; r_o: out std_logic_vector(7 downto 0); vb_o: out std_logic; vs_o: out std_logic ); end x5x5_filters_entity_1ec75b0e3e; architecture structural of x5x5_filters_entity_1ec75b0e3e is signal active_video_i_net_x1: std_logic; signal bit0_y_net_x1: std_logic; signal bit1_y_net_x1: std_logic; signal bit2_y_net_x1: std_logic; signal bit3_y_net_x1: std_logic; signal bit4_y_net_x1: std_logic; signal blue_x2: std_logic_vector(7 downto 0); signal ce_1_sg_x53: std_logic; signal ce_logic_1_sg_x24: std_logic; signal clk_1_sg_x53: std_logic; signal constant1_op_net_x1: std_logic; signal constant2_op_net_x1: std_logic_vector(6 downto 0); signal convert1_dout_net_x5: std_logic_vector(7 downto 0); signal convert1_dout_net_x6: std_logic_vector(7 downto 0); signal convert1_dout_net_x7: std_logic_vector(7 downto 0); signal counter_op_net_x1: std_logic_vector(4 downto 0); signal from_register1_data_out_net_x1: std_logic; signal from_register_data_out_net_x9: std_logic_vector(19 downto 0); signal green_x2: std_logic_vector(7 downto 0); signal hblank_i_net_x1: std_logic; signal hsync_i_net_x2: std_logic; signal rctr_q_net_x9: std_logic_vector(11 downto 0); signal red_x2: std_logic_vector(7 downto 0); signal relational3_op_net_x10: std_logic; signal reset_net_x1: std_logic; signal shared_memory_data_out_net_x24: std_logic_vector(6 downto 0); signal vblank_i_net_x1: std_logic; signal vsync_i_net_x2: std_logic; begin active_video_i_net_x1 <= av_i; blue_x2 <= b; ce_1_sg_x53 <= ce_1; ce_logic_1_sg_x24 <= ce_logic_1; clk_1_sg_x53 <= clk_1; from_register_data_out_net_x9 <= from_register; from_register1_data_out_net_x1 <= from_register1; green_x2 <= g; hblank_i_net_x1 <= hb_i; hsync_i_net_x2 <= hs_i; red_x2 <= r; reset_net_x1 <= rst; shared_memory_data_out_net_x24 <= shared_memory; vblank_i_net_x1 <= vb_i; vsync_i_net_x2 <= vs_i; b_o <= convert1_dout_net_x5; coefficient_memory <= constant1_op_net_x1; coefficient_memory_x0 <= constant2_op_net_x1; coefficient_memory_x1 <= counter_op_net_x1; de_o <= bit4_y_net_x1; g_o <= convert1_dout_net_x6; hb_o <= bit0_y_net_x1; hs_o <= bit2_y_net_x1; r_o <= convert1_dout_net_x7; vb_o <= bit1_y_net_x1; vs_o <= bit3_y_net_x1; blue_filter_d29ca0c8b1: entity work.blue_filter_entity_d29ca0c8b1 port map ( addr => rctr_q_net_x9, ce_1 => ce_1_sg_x53, ce_logic_1 => ce_logic_1_sg_x24, clk_1 => clk_1_sg_x53, coef => shared_memory_data_out_net_x24, din => blue_x2, gain => from_register_data_out_net_x9, load => relational3_op_net_x10, dout => convert1_dout_net_x5 ); coefficient_memory_d275723ee2: entity work.coefficient_memory_entity_d275723ee2 port map ( ce_1 => ce_1_sg_x53, clk_1 => clk_1_sg_x53, from_register1 => from_register1_data_out_net_x1, vsync => vsync_i_net_x2, constant1_x0 => constant1_op_net_x1, constant2_x0 => constant2_op_net_x1, counter_x0 => counter_op_net_x1, load => relational3_op_net_x10 ); ctrl_delay_b2aeac3e46: entity work.ctrl_delay_entity_b2aeac3e46 port map ( addr => rctr_q_net_x9, av_i => active_video_i_net_x1, ce_1 => ce_1_sg_x53, clk_1 => clk_1_sg_x53, hb_i => hblank_i_net_x1, hs_i => hsync_i_net_x2, vb_i => vblank_i_net_x1, vs_i => vsync_i_net_x2, av_o => bit4_y_net_x1, hb_o => bit0_y_net_x1, hs_o => bit2_y_net_x1, vb_o => bit1_y_net_x1, vs_o => bit3_y_net_x1 ); green_filter_dc51fce7d5: entity work.blue_filter_entity_d29ca0c8b1 port map ( addr => rctr_q_net_x9, ce_1 => ce_1_sg_x53, ce_logic_1 => ce_logic_1_sg_x24, clk_1 => clk_1_sg_x53, coef => shared_memory_data_out_net_x24, din => green_x2, gain => from_register_data_out_net_x9, load => relational3_op_net_x10, dout => convert1_dout_net_x6 ); line_ctrs_8878c4bf27: entity work.line_ctrs_entity_8878c4bf27 port map ( ce_1 => ce_1_sg_x53, clk_1 => clk_1_sg_x53, h => hsync_i_net_x2, rst => reset_net_x1, addr => rctr_q_net_x9 ); red_filter_078d79d78e: entity work.blue_filter_entity_d29ca0c8b1 port map ( addr => rctr_q_net_x9, ce_1 => ce_1_sg_x53, ce_logic_1 => ce_logic_1_sg_x24, clk_1 => clk_1_sg_x53, coef => shared_memory_data_out_net_x24, din => red_x2, gain => from_register_data_out_net_x9, load => relational3_op_net_x10, dout => convert1_dout_net_x7 ); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; -- Generated from Simulink block "sg_2d_fir/EDK Processor" entity edk_processor_entity_45d14a6139 is port ( plb_abus: in std_logic_vector(31 downto 0); plb_ce_1: in std_logic; plb_clk_1: in std_logic; plb_pavalid: in std_logic; plb_rnw: in std_logic; plb_wrdbus: in std_logic_vector(31 downto 0); sg_plb_addrpref: in std_logic_vector(19 downto 0); shared_memory: in std_logic_vector(6 downto 0); splb_rst: in std_logic; to_register: in std_logic; to_register1: in std_logic_vector(19 downto 0); constant5_x0: out std_logic; plb_decode_x0: out std_logic; plb_decode_x1: out std_logic; plb_decode_x2: out std_logic; plb_decode_x3: out std_logic; plb_decode_x4: out std_logic_vector(31 downto 0); plb_memmap_x0: out std_logic; plb_memmap_x1: out std_logic; plb_memmap_x2: out std_logic_vector(19 downto 0); plb_memmap_x3: out std_logic; plb_memmap_x4: out std_logic_vector(4 downto 0); plb_memmap_x5: out std_logic_vector(6 downto 0); plb_memmap_x6: out std_logic ); end edk_processor_entity_45d14a6139; architecture structural of edk_processor_entity_45d14a6139 is signal bankaddr: std_logic_vector(1 downto 0); signal coef_buffer_addr_x0: std_logic_vector(4 downto 0); signal coef_buffer_din_x0: std_logic_vector(6 downto 0); signal coef_buffer_dout_x0: std_logic_vector(6 downto 0); signal coef_buffer_we_x0: std_logic; signal coef_gain_din_x0: std_logic_vector(19 downto 0); signal coef_gain_dout_x0: std_logic_vector(19 downto 0); signal coef_gain_en_x0: std_logic; signal coef_update_din_x0: std_logic; signal coef_update_dout_x0: std_logic; signal coef_update_en_x0: std_logic; signal linearaddr: std_logic_vector(7 downto 0); signal plb_abus_net_x0: std_logic_vector(31 downto 0); signal plb_ce_1_sg_x0: std_logic; signal plb_clk_1_sg_x0: std_logic; signal plb_pavalid_net_x0: std_logic; signal plb_rnw_net_x0: std_logic; signal plb_wrdbus_net_x0: std_logic_vector(31 downto 0); signal rddata: std_logic_vector(31 downto 0); signal rnwreg: std_logic; signal sg_plb_addrpref_net_x0: std_logic_vector(19 downto 0); signal sl_addrack_x0: std_logic; signal sl_rdcomp_x0: std_logic; signal sl_rddack_x0: std_logic; signal sl_rddbus_x0: std_logic_vector(31 downto 0); signal sl_wait_x0: std_logic; signal sl_wrdack_x0: std_logic; signal splb_rst_net_x0: std_logic; signal wrdbusreg: std_logic_vector(31 downto 0); begin plb_abus_net_x0 <= plb_abus; plb_ce_1_sg_x0 <= plb_ce_1; plb_clk_1_sg_x0 <= plb_clk_1; plb_pavalid_net_x0 <= plb_pavalid; plb_rnw_net_x0 <= plb_rnw; plb_wrdbus_net_x0 <= plb_wrdbus; sg_plb_addrpref_net_x0 <= sg_plb_addrpref; coef_buffer_dout_x0 <= shared_memory; splb_rst_net_x0 <= splb_rst; coef_update_dout_x0 <= to_register; coef_gain_dout_x0 <= to_register1; constant5_x0 <= sl_wait_x0; plb_decode_x0 <= sl_addrack_x0; plb_decode_x1 <= sl_rdcomp_x0; plb_decode_x2 <= sl_wrdack_x0; plb_decode_x3 <= sl_rddack_x0; plb_decode_x4 <= sl_rddbus_x0; plb_memmap_x0 <= coef_update_din_x0; plb_memmap_x1 <= coef_update_en_x0; plb_memmap_x2 <= coef_gain_din_x0; plb_memmap_x3 <= coef_gain_en_x0; plb_memmap_x4 <= coef_buffer_addr_x0; plb_memmap_x5 <= coef_buffer_din_x0; plb_memmap_x6 <= coef_buffer_we_x0; constant5: entity work.constant_963ed6358a port map ( ce => '0', clk => '0', clr => '0', op(0) => sl_wait_x0 ); plb_decode: entity work.mcode_block_f4d0462e0e port map ( addrpref => sg_plb_addrpref_net_x0, ce => plb_ce_1_sg_x0, clk => plb_clk_1_sg_x0, clr => '0', plbabus => plb_abus_net_x0, plbpavalid(0) => plb_pavalid_net_x0, plbrnw(0) => plb_rnw_net_x0, plbrst(0) => splb_rst_net_x0, plbwrdbus => plb_wrdbus_net_x0, rddata => rddata, addrack(0) => sl_addrack_x0, bankaddr => bankaddr, linearaddr => linearaddr, rdcomp(0) => sl_rdcomp_x0, rddack(0) => sl_rddack_x0, rddbus => sl_rddbus_x0, rnwreg(0) => rnwreg, wrdack(0) => sl_wrdack_x0, wrdbusreg => wrdbusreg ); plb_memmap: entity work.mcode_block_6fff803424 port map ( addrack(0) => sl_addrack_x0, bankaddr => bankaddr, ce => plb_ce_1_sg_x0, clk => plb_clk_1_sg_x0, clr => '0', linearaddr => linearaddr, rnwreg(0) => rnwreg, sm_coef_buffer => coef_buffer_dout_x0, sm_coef_gain => coef_gain_dout_x0, sm_coef_update(0) => coef_update_dout_x0, wrdbus => wrdbusreg, read_bank_out => rddata, sm_coef_buffer_addr => coef_buffer_addr_x0, sm_coef_buffer_din => coef_buffer_din_x0, sm_coef_buffer_we(0) => coef_buffer_we_x0, sm_coef_gain_din => coef_gain_din_x0, sm_coef_gain_en(0) => coef_gain_en_x0, sm_coef_update_din(0) => coef_update_din_x0, sm_coef_update_en(0) => coef_update_en_x0 ); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; -- Generated from Simulink block "sg_2d_fir" entity sg_2d_fir is port ( active_video_i: in std_logic; ce_1: in std_logic; ce_logic_1: in std_logic; clk_1: in std_logic; data_out: in std_logic_vector(19 downto 0); data_out_x0: in std_logic; data_out_x1: in std_logic_vector(6 downto 0); data_out_x2: in std_logic_vector(6 downto 0); dout: in std_logic; dout_x0: in std_logic_vector(19 downto 0); hblank_i: in std_logic; hsync_i: in std_logic; plb_abus: in std_logic_vector(31 downto 0); plb_ce_1: in std_logic; plb_clk_1: in std_logic; plb_pavalid: in std_logic; plb_rnw: in std_logic; plb_wrdbus: in std_logic_vector(31 downto 0); reset: in std_logic; sg_plb_addrpref: in std_logic_vector(19 downto 0); splb_rst: in std_logic; vblank_i: in std_logic; video_data_i: in std_logic_vector(23 downto 0); vsync_i: in std_logic; active_video_o: out std_logic; addr: out std_logic_vector(4 downto 0); addr_x0: out std_logic_vector(4 downto 0); data_in: out std_logic_vector(6 downto 0); data_in_x0: out std_logic; data_in_x1: out std_logic_vector(19 downto 0); data_in_x2: out std_logic_vector(6 downto 0); en: out std_logic; en_x0: out std_logic; hblank_o: out std_logic; hsync_o: out std_logic; sl_addrack: out std_logic; sl_rdcomp: out std_logic; sl_rddack: out std_logic; sl_rddbus: out std_logic_vector(31 downto 0); sl_wait: out std_logic; sl_wrcomp: out std_logic; sl_wrdack: out std_logic; vblank_o: out std_logic; video_data_o: out std_logic_vector(23 downto 0); vsync_o: out std_logic; we: out std_logic; we_x0: out std_logic ); end sg_2d_fir; architecture structural of sg_2d_fir is attribute core_generation_info: string; attribute core_generation_info of structural : architecture is "sg_2d_fir,sysgen_core,{clock_period=10.00000000,clocking=Clock_Enables,sample_periods=1.00000000000 1.00000000000,testbench=0,total_blocks=711,xilinx_adder_subtracter_block=13,xilinx_arithmetic_relational_operator_block=23,xilinx_assert_block=3,xilinx_bit_slice_extractor_block=11,xilinx_bitwise_expression_evaluator_block=3,xilinx_bus_concatenator_block=2,xilinx_bus_multiplexer_block=4,xilinx_constant_block_block=29,xilinx_counter_block=7,xilinx_delay_block=25,xilinx_edk_processor_block=1,xilinx_fir_compiler_5_0_block=15,xilinx_gateway_in_block=13,xilinx_gateway_out_block=13,xilinx_inverter_block=16,xilinx_logical_block_block=33,xilinx_mcode_block_block=2,xilinx_multiplier_block=3,xilinx_negate_block_block=3,xilinx_register_block=63,xilinx_shared_memory_based_from_register_block=2,xilinx_shared_memory_based_to_register_block=2,xilinx_shared_memory_random_access_memory_block=2,xilinx_single_port_random_access_memory_block=16,xilinx_system_generator_block=1,xilinx_type_converter_block=7,}"; signal active_video_i_net: std_logic; signal active_video_o_net: std_logic; signal addr_net: std_logic_vector(4 downto 0); signal addr_x0_net: std_logic_vector(4 downto 0); signal blue_x2: std_logic_vector(7 downto 0); signal ce_1_sg_x54: std_logic; signal ce_logic_1_sg_x25: std_logic; signal clk_1_sg_x54: std_logic; signal convert1_dout_net_x5: std_logic_vector(7 downto 0); signal convert1_dout_net_x6: std_logic_vector(7 downto 0); signal convert1_dout_net_x7: std_logic_vector(7 downto 0); signal data_in_net: std_logic_vector(6 downto 0); signal data_in_x0_net: std_logic; signal data_in_x1_net: std_logic_vector(19 downto 0); signal data_in_x2_net: std_logic_vector(6 downto 0); signal data_out_net: std_logic_vector(19 downto 0); signal data_out_x0_net: std_logic; signal data_out_x1_net: std_logic_vector(6 downto 0); signal data_out_x2_net: std_logic_vector(6 downto 0); signal dout_net: std_logic; signal dout_x0_net: std_logic_vector(19 downto 0); signal en_net: std_logic; signal en_x0_net: std_logic; signal green_x2: std_logic_vector(7 downto 0); signal hblank_i_net: std_logic; signal hblank_o_net: std_logic; signal hsync_i_net: std_logic; signal hsync_o_net: std_logic; signal plb_abus_net: std_logic_vector(31 downto 0); signal plb_ce_1_sg_x1: std_logic; signal plb_clk_1_sg_x1: std_logic; signal plb_pavalid_net: std_logic; signal plb_rnw_net: std_logic; signal plb_wrdbus_net: std_logic_vector(31 downto 0); signal red_x2: std_logic_vector(7 downto 0); signal reset_net: std_logic; signal sg_plb_addrpref_net: std_logic_vector(19 downto 0); signal sl_addrack_net: std_logic; signal sl_rdcomp_net: std_logic; signal sl_rddack_net: std_logic; signal sl_rddbus_net: std_logic_vector(31 downto 0); signal sl_wait_net: std_logic; signal sl_wrdack_x1: std_logic; signal splb_rst_net: std_logic; signal vblank_i_net: std_logic; signal vblank_o_net: std_logic; signal video_data_i_net: std_logic_vector(23 downto 0); signal video_data_o_net: std_logic_vector(23 downto 0); signal vsync_i_net: std_logic; signal vsync_o_net: std_logic; signal we_net: std_logic; signal we_x0_net: std_logic; begin active_video_i_net <= active_video_i; ce_1_sg_x54 <= ce_1; ce_logic_1_sg_x25 <= ce_logic_1; clk_1_sg_x54 <= clk_1; data_out_net <= data_out; data_out_x0_net <= data_out_x0; data_out_x1_net <= data_out_x1; data_out_x2_net <= data_out_x2; dout_net <= dout; dout_x0_net <= dout_x0; hblank_i_net <= hblank_i; hsync_i_net <= hsync_i; plb_abus_net <= plb_abus; plb_ce_1_sg_x1 <= plb_ce_1; plb_clk_1_sg_x1 <= plb_clk_1; plb_pavalid_net <= plb_pavalid; plb_rnw_net <= plb_rnw; plb_wrdbus_net <= plb_wrdbus; reset_net <= reset; sg_plb_addrpref_net <= sg_plb_addrpref; splb_rst_net <= splb_rst; vblank_i_net <= vblank_i; video_data_i_net <= video_data_i; vsync_i_net <= vsync_i; active_video_o <= active_video_o_net; addr <= addr_net; addr_x0 <= addr_x0_net; data_in <= data_in_net; data_in_x0 <= data_in_x0_net; data_in_x1 <= data_in_x1_net; data_in_x2 <= data_in_x2_net; en <= en_net; en_x0 <= en_x0_net; hblank_o <= hblank_o_net; hsync_o <= hsync_o_net; sl_addrack <= sl_addrack_net; sl_rdcomp <= sl_rdcomp_net; sl_rddack <= sl_rddack_net; sl_rddbus <= sl_rddbus_net; sl_wait <= sl_wait_net; sl_wrcomp <= sl_wrdack_x1; sl_wrdack <= sl_wrdack_x1; vblank_o <= vblank_o_net; video_data_o <= video_data_o_net; vsync_o <= vsync_o_net; we <= we_net; we_x0 <= we_x0_net; concat: entity work.concat_d0d1b9533e port map ( ce => '0', clk => '0', clr => '0', in0 => convert1_dout_net_x7, in1 => convert1_dout_net_x6, in2 => convert1_dout_net_x5, y => video_data_o_net ); edk_processor_45d14a6139: entity work.edk_processor_entity_45d14a6139 port map ( plb_abus => plb_abus_net, plb_ce_1 => plb_ce_1_sg_x1, plb_clk_1 => plb_clk_1_sg_x1, plb_pavalid => plb_pavalid_net, plb_rnw => plb_rnw_net, plb_wrdbus => plb_wrdbus_net, sg_plb_addrpref => sg_plb_addrpref_net, shared_memory => data_out_x2_net, splb_rst => splb_rst_net, to_register => dout_net, to_register1 => dout_x0_net, constant5_x0 => sl_wait_net, plb_decode_x0 => sl_addrack_net, plb_decode_x1 => sl_rdcomp_net, plb_decode_x2 => sl_wrdack_x1, plb_decode_x3 => sl_rddack_net, plb_decode_x4 => sl_rddbus_net, plb_memmap_x0 => data_in_x0_net, plb_memmap_x1 => en_net, plb_memmap_x2 => data_in_x1_net, plb_memmap_x3 => en_x0_net, plb_memmap_x4 => addr_x0_net, plb_memmap_x5 => data_in_x2_net, plb_memmap_x6 => we_x0_net ); slice15downto8: entity work.xlslice generic map ( new_lsb => 8, new_msb => 15, x_width => 24, y_width => 8 ) port map ( x => video_data_i_net, y => green_x2 ); slice23downto16: entity work.xlslice generic map ( new_lsb => 16, new_msb => 23, x_width => 24, y_width => 8 ) port map ( x => video_data_i_net, y => red_x2 ); slice7downto0: entity work.xlslice generic map ( new_lsb => 0, new_msb => 7, x_width => 24, y_width => 8 ) port map ( x => video_data_i_net, y => blue_x2 ); x5x5_filters_1ec75b0e3e: entity work.x5x5_filters_entity_1ec75b0e3e port map ( av_i => active_video_i_net, b => blue_x2, ce_1 => ce_1_sg_x54, ce_logic_1 => ce_logic_1_sg_x25, clk_1 => clk_1_sg_x54, from_register => data_out_net, from_register1 => data_out_x0_net, g => green_x2, hb_i => hblank_i_net, hs_i => hsync_i_net, r => red_x2, rst => reset_net, shared_memory => data_out_x1_net, vb_i => vblank_i_net, vs_i => vsync_i_net, b_o => convert1_dout_net_x5, coefficient_memory => we_net, coefficient_memory_x0 => data_in_net, coefficient_memory_x1 => addr_net, de_o => active_video_o_net, g_o => convert1_dout_net_x6, hb_o => hblank_o_net, hs_o => hsync_o_net, r_o => convert1_dout_net_x7, vb_o => vblank_o_net, vs_o => vsync_o_net ); end structural;
gpl-3.0
3812d60ffcc4aeab792da511b79a3ea4
0.583251
3.200067
false
false
false
false
hoglet67/AtomFpga
src/common/AtomFpga_Core.vhd
1
39,052
-------------------------------------------------------------------------------- -- Copyright (c) 2019 David Banks -- -- based on work by Alan Daly. Copyright(c) 2009. All rights reserved. -------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / -- \ \ \/ -- \ \ -- / / Filename : AtomFpga_Core -- /___/ /\ Timestamp : 02/03/2013 06:17:50 -- \ \ / \ -- \___\/\___\ -- --Design Name: Atomic_top.vhf library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; entity AtomFpga_Core is generic ( CImplCpu65c02 : boolean := false; CImplDebugger : boolean := false; CImplSDDOS : boolean; CImplAtoMMC2 : boolean; CImplGraphicsExt : boolean; CImplSoftChar : boolean; CImplSID : boolean; CImplVGA80x40 : boolean; CImplHWScrolling : boolean; CImplMouse : boolean; CImplUart : boolean; CImplDoubleVideo : boolean; CImplRamRomNone : boolean; CImplRamRomPhill : boolean; CImplRamRomAtom2015 : boolean; CImplRamRomSchakelKaart : boolean; CImplVIA : boolean := true; CImplProfilingCounters : boolean := false; MainClockSpeed : integer; DefaultBaud : integer ); port ( -- Clocking clk_vga : in std_logic; -- nominally 25.175MHz VGA clock clk_main : in std_logic; -- clock for the main system clk_avr : in std_logic; -- clock for the AtoMMC AVR clk_avr_debug : in std_logic; -- clock for the Debugger AVR clk_dac : in std_logic; -- fast clock for the 1-bit DAC clk_32M00 : in std_logic; -- fixed clock, used for SID and casette -- Keyboard/mouse kbd_pa : out std_logic_vector(3 downto 0); kbd_pb : in std_logic_vector(7 downto 0) := (others => '1'); kbd_pc : in std_logic_vector(6 downto 6) := (others => '1'); ps2_clk : in std_logic; ps2_data : in std_logic; ps2_mouse_clk : inout std_logic; ps2_mouse_data : inout std_logic; -- Resets powerup_reset_n : in std_logic := '1'; -- power up reset only (optional) ext_reset_n : in std_logic := '1'; -- external bus reset (optional) int_reset_n : out std_logic; -- internal bus reset (e.g. PS/2 break) -- Video red : out std_logic_vector (2 downto 0); green : out std_logic_vector (2 downto 0); blue : out std_logic_vector (2 downto 0); vsync : out std_logic; hsync : out std_logic; blank : out std_logic; -- External 6502 bus interface phi2 : out std_logic; sync : out std_logic; rnw : out std_logic; addr : out std_logic_vector(15 downto 0); rdy : in std_logic := '1'; so : in std_logic := '1'; irq_n : in std_logic := '1'; nmi_n : in std_logic := '1'; -- External Bus/Ram/Rom interface ExternBus : out std_logic; ExternCE : out std_logic; ExternWE : out std_logic; ExternA : out std_logic_vector (18 downto 0); ExternDin : out std_logic_vector (7 downto 0); ExternDout : in std_logic_vector (7 downto 0); -- Audio sid_audio_d : out std_logic_vector (17 downto 0); sid_audio : out std_logic; atom_audio : out std_logic; -- SD Card SDMISO : in std_logic; SDSS : out std_logic; SDCLK : out std_logic; SDMOSI : out std_logic; -- Serial uart_RxD : in std_logic; uart_TxD : out std_logic; avr_RxD : in std_logic; avr_TxD : out std_logic; -- Cassette cas_in : in std_logic := '0'; cas_out : out std_logic; -- Misc LED1 : out std_logic; LED2 : out std_logic; charSet : in std_logic; Joystick1 : in std_logic_vector (7 downto 0) := (others => '1'); Joystick2 : in std_logic_vector (7 downto 0) := (others => '1') ); end AtomFpga_Core; architecture BEHAVIORAL of AtomFpga_Core is function InitBFFE_Atom2015 return std_logic_vector is begin if CImplAtoMMC2 then -- Use OS ROM Bank 0 (contains AVR AtoMMC) return x"00"; else -- Use OS ROM Bank 1 (contains PIC AtoMMC) return x"08"; end if; end function; ------------------------------------------------- -- Clocks and enables ------------------------------------------------- signal clk_counter : std_logic_vector(4 downto 0); signal cpu_cycle : std_logic; signal cpu_clken : std_logic; signal pia_clken : std_logic; signal sample_data : std_logic; ------------------------------------------------- -- CPU signals ------------------------------------------------- signal powerup_reset_n_sync : std_logic; signal ext_reset_n_sync : std_logic; signal RSTn : std_logic; signal cpu_R_W_n : std_logic; signal not_cpu_R_W_n : std_logic; signal cpu_addr : std_logic_vector (15 downto 0); signal cpu_din : std_logic_vector (7 downto 0); signal cpu_dout : std_logic_vector (7 downto 0); signal cpu_IRQ_n : std_logic; signal cpu_NMI_n : std_logic; signal ExternDin1 : std_logic_vector (7 downto 0); signal ExternDout1 : std_logic_vector (7 downto 0); --------------------------------------------------- -- VDG signals --------------------------------------------------- signal vdg_fs_n : std_logic; signal vdg_an_g : std_logic; signal vdg_gm : std_logic_vector(2 downto 0); signal vdg_css : std_logic; signal vdg_red : std_logic; signal vdg_green1 : std_logic; signal vdg_green0 : std_logic; signal vdg_blue : std_logic; signal vdg_hsync : std_logic; signal vdg_vsync : std_logic; signal vdg_blank : std_logic; ---------------------------------------------------- -- Device enables ---------------------------------------------------- signal mc6522_enable : std_logic; signal i8255_enable : std_logic; signal ext_ramrom_enable : std_logic; signal ext_bus_enable : std_logic; signal video_ram_enable : std_logic; signal reg_enable : std_logic; signal sid_enable : std_logic; signal uart_enable : std_logic; signal counter_enable : std_logic; signal gated_we : std_logic; signal video_ram_we : std_logic; signal reg_we : std_logic; signal sid_we : std_logic; signal uart_we : std_logic; ---------------------------------------------------- -- External data ---------------------------------------------------- signal extern_data : std_logic_vector(7 downto 0); signal godil_data : std_logic_vector(7 downto 0); ---------------------------------------------------- -- 6522 signals ---------------------------------------------------- signal via4_clken : std_logic; signal via1_clken : std_logic; signal mc6522_data : std_logic_vector(7 downto 0); signal mc6522_irq : std_logic; signal mc6522_ca1 : std_logic; signal mc6522_ca2 : std_logic; signal mc6522_cb1 : std_logic; signal mc6522_cb2 : std_logic; signal mc6522_porta : std_logic_vector(7 downto 0); signal mc6522_portb : std_logic_vector(7 downto 0); ---------------------------------------------------- -- 8255 signals ---------------------------------------------------- signal i8255_pa_data : std_logic_vector(7 downto 0); signal i8255_pb_idata : std_logic_vector(7 downto 0); signal i8255_pc_data : std_logic_vector(7 downto 0); signal i8255_pc_idata : std_logic_vector(7 downto 0); signal i8255_data : std_logic_vector(7 downto 0); signal i8255_rd : std_logic; signal ps2dataout : std_logic_vector(5 downto 0); signal key_shift : std_logic; signal key_ctrl : std_logic; signal key_repeat : std_logic; signal key_break : std_logic; signal key_escape : std_logic; signal key_turbo : std_logic_vector(1 downto 0); signal cas_divider : std_logic_vector(15 downto 0); signal cas_tone : std_logic; signal turbo : std_logic_vector(1 downto 0); signal turbo_synced : std_logic_vector(1 downto 0); ---------------------------------------------------- -- AtoMMC signals ---------------------------------------------------- signal pl8_enable : std_logic; signal pl8_data : std_logic_vector (7 downto 0); signal uart_escape : std_logic; signal uart_break : std_logic; signal nARD : std_logic; signal nAWR : std_logic; signal AVRA0 : std_logic; signal AVRInt : std_logic; signal AVRDataIn : std_logic_vector (7 downto 0); signal AVRDataOut : std_logic_vector (7 downto 0); signal ioport : std_logic_vector (7 downto 0); signal LED1n : std_logic; signal LED2n : std_logic; signal avr_TxD_debugger : std_logic; signal avr_TxD_atommc : std_logic; ---------------------------------------------------- -- Profiling Counter Signals ---------------------------------------------------- signal p_counter_ctrl : std_logic_vector (7 downto 0); signal p_counter_data : std_logic_vector (7 downto 0); signal p_divider_latch : std_logic_vector (31 downto 0); signal p_divider_counter : std_logic_vector (31 downto 0); signal p_profile_counter : std_logic_vector (31 downto 0); signal p_reset : std_logic; signal p_pause : std_logic; signal p_reset_last : std_logic; -------------------------------------------------------------------- -- here it begin :) -------------------------------------------------------------------- begin --------------------------------------------------------------------- -- 6502 CPU (using a wrapper module --------------------------------------------------------------------- cpu : entity work.CpuWrapper generic map ( CImplDebugger => CImplDebugger, CImplCpu65c02 => CImplCpu65c02 ) port map ( clk_main => clk_main, clk_avr => clk_avr_debug, cpu_clken => cpu_clken, IRQ_n => cpu_IRQ_n, NMI_n => nmi_n, RST_n => RSTn, PRST_n => powerup_reset_n, SO => So, RDY => Rdy, Din => cpu_din, Dout => cpu_dout, R_W_n => cpu_R_W_n, Sync => Sync, Addr => cpu_addr, avr_RxD => avr_RxD, avr_TxD => avr_TxD_debugger ); not_cpu_R_W_n <= not cpu_R_W_n; cpu_IRQ_n <= irq_n and mc6522_irq when CImplVIA else irq_n; cpu_NMI_n <= nmi_n; avr_TxD <= avr_TxD_debugger and avr_TxD_atommc; -- reset logic process(clk_main) begin if rising_edge(clk_main) then powerup_reset_n_sync <= powerup_reset_n; ext_reset_n_sync <= ext_reset_n; RSTn <= key_break and powerup_reset_n_sync and ext_reset_n_sync; int_reset_n <= key_break; end if; end process; -- write enables gated_we <= not_cpu_R_W_n; uart_we <= gated_we; video_ram_we <= gated_we and video_ram_enable; reg_we <= gated_we; sid_we <= gated_we; -- external bus rnw <= cpu_R_W_n; addr <= cpu_addr; --------------------------------------------------------------------- -- Atom GODIL Video adapter --------------------------------------------------------------------- Inst_AtomGodilVideo : entity work.AtomGodilVideo generic map ( CImplGraphicsExt => CImplGraphicsExt, CImplSoftChar => CImplSoftChar, CImplSID => CImplSID, CImplVGA80x40 => CImplVGA80x40, CImplHWScrolling => CImplHWScrolling, CImplMouse => CImplMouse, CImplUart => CImplUart, CImplDoubleVideo => CImplDoubleVideo, MainClockSpeed => MainClockSpeed, DefaultBaud => DefaultBaud ) port map ( clock_vga => clk_vga, clock_main => clk_main, clock_sid_32Mhz => clk_32M00, clock_sid_dac => clk_dac, reset => not RSTn, reset_vid => '0', din => cpu_dout, dout => godil_data, addr => cpu_addr(12 downto 0), CSS => vdg_css, AG => vdg_an_g, GM => vdg_gm, nFS => vdg_fs_n, ram_we => video_ram_we, reg_cs => reg_enable, reg_we => reg_we, sid_cs => sid_enable, sid_we => sid_we, sid_audio => sid_audio, sid_audio_d => sid_audio_d, PS2_CLK => ps2_mouse_clk, PS2_DATA => ps2_mouse_data, uart_cs => uart_enable, uart_we => uart_we, uart_RxD => uart_RxD, uart_TxD => uart_TxD, uart_escape => uart_escape, uart_break => uart_break, final_red => vdg_red, final_green1 => vdg_green1, final_green0 => vdg_green0, final_blue => vdg_blue, final_vsync => vdg_vsync, final_hsync => vdg_hsync, final_blank => vdg_blank, charSet => charSet ); -- external ouputs red(2 downto 0) <= vdg_red & vdg_red & vdg_red; green(2 downto 0) <= vdg_green1 & vdg_green0 & vdg_green0; blue(2 downto 0) <= vdg_blue & vdg_blue & vdg_blue; vsync <= vdg_vsync; hsync <= vdg_hsync; blank <= vdg_blank; --------------------------------------------------------------------- -- 8255 PIA --------------------------------------------------------------------- pia : entity work.I82C55 port map( I_ADDR => cpu_addr(1 downto 0), -- A1-A0 I_DATA => cpu_dout, -- D7-D0 O_DATA => i8255_data, CS_H => i8255_enable, WR_L => cpu_R_W_n, O_PA => i8255_pa_data, I_PB => i8255_pb_idata, I_PC => i8255_pc_idata(7 downto 4), O_PC => i8255_pc_data(3 downto 0), RESET => RSTn, ENA => pia_clken, CLK => clk_main); -- Port A -- bits 7..4 (output) determine the 6847 graphics mode -- bits 3..0 (output) drive the keyboard matrix vdg_gm <= i8255_pa_data(7 downto 5) when RSTn='1' else "000"; vdg_an_g <= i8255_pa_data(4) when RSTn='1' else '0'; kbd_pa <= i8255_pa_data(3 downto 0); -- Port B -- bits 7..0 (input) read the keyboard matrix i8255_pb_idata <= (key_shift & key_ctrl & ps2dataout) and (kbd_pb); -- Port C -- bit 7 (input) FS from the 6847 -- bit 6 (input) Repeat from the keyboard matrix -- bit 5 (input) Cassette input -- bit 4 (input) 2.4KHz tone input -- bit 3 (output) CSS to the 6847 -- bit 2 (output) Audio -- bit 1 (output) Enable 2.4KHz tone to casette output -- bit 0 (output) Cassette output vdg_css <= i8255_pc_data(3) when RSTn='1' else '0'; atom_audio <= i8255_pc_data(2); i8255_pc_idata <= vdg_fs_n & (key_repeat and kbd_pc(6)) & cas_in & cas_tone & i8255_pc_data (3 downto 0); -- Cassette divider -- 32 MHz / 2 / 13 / 16 / 16 = 4807 Hz process(clk_32M00) begin if rising_edge(clk_32M00) then if cas_divider = 0 then cas_divider <= x"19FF"; cas_tone <= not cas_tone; else cas_divider <= cas_divider - 1; end if; end if; end process; -- this is a direct translation of the logic in the atom -- (two NAND gates and an inverter) cas_out <= not(not((not cas_tone) and i8255_pc_data(1)) and i8255_pc_data(0)); --------------------------------------------------------------------- -- PS/2 Keyboard Emulation --------------------------------------------------------------------- input : entity work.keyboard port map( CLOCK => clk_main, nRESET => powerup_reset_n_sync, CLKEN_1MHZ => cpu_clken, PS2_CLK => ps2_clk, PS2_DATA => ps2_data, KEYOUT => ps2dataout, ROW => i8255_pa_data(3 downto 0), ESC_IN => uart_escape, BREAK_IN => uart_break, SHIFT_OUT => key_shift, CTRL_OUT => key_ctrl, REPEAT_OUT => key_repeat, BREAK_OUT => key_break, TURBO => key_turbo, ESC_OUT => key_escape, Joystick1 => Joystick1, Joystick2 => Joystick2 ); --------------------------------------------------------------------- -- 6522 VIA --------------------------------------------------------------------- Inst_via: if (CImplVIA) generate via : entity work.M6522 port map( I_RS => cpu_addr(3 downto 0), I_DATA => cpu_dout, O_DATA => mc6522_data(7 downto 0), I_RW_L => cpu_R_W_n, I_CS1 => mc6522_enable, I_CS2_L => '0', O_IRQ_L => mc6522_irq, I_CA1 => mc6522_ca1, I_CA2 => mc6522_ca2, O_CA2 => mc6522_ca2, I_PA => mc6522_porta(7 downto 0), O_PA => mc6522_porta(7 downto 0), I_CB1 => mc6522_cb1, O_CB1 => mc6522_cb1, I_CB2 => mc6522_cb2, O_CB2 => mc6522_cb2, I_PB => mc6522_portb(7 downto 0), O_PB => mc6522_portb(7 downto 0), RESET_L => RSTn, I_P2_H => via1_clken, ENA_4 => via4_clken, CLK => clk_main); mc6522_ca1 <= '1'; end generate; -------------------------------------------------------- -- SDDOS -------------------------------------------------------- Inst_spi: if (CImplSDDOS) generate Inst_spi_comp : entity work.SPI_Port port map ( nRST => RSTn, clk => clk_main, enable => pl8_enable, nwe => cpu_R_W_n, address => cpu_addr(2 downto 0), datain => cpu_dout, dataout => pl8_data, MISO => SDMISO, MOSI => SDMOSI, NSS => SDSS, SPICLK => SDCLK ); LED1 <= '0'; LED2 <= '0'; end generate; -------------------------------------------------------- -- AtomMMC -------------------------------------------------------- Inst_atommc2: if (CImplAtoMMC2) generate Inst_AVR8: entity work.AVR8 generic map( CDATAMEMSIZE => 4096, CPROGMEMSIZE => 9216, FILENAME => "avr_progmem_atommc2.data", CImplPORTA => TRUE, CImplPORTB => TRUE, CImplPORTD => TRUE, CImplPORTE => TRUE, CImplUART => TRUE, CImplSPI => TRUE, CImplExtIRQ => TRUE ) port map( clk16M => clk_avr, nrst => RSTn, portain => AVRDataOut, portaout => AVRDataIn, portbin(0) => '0', portbin(1) => '0', portbin(2) => '0', portbin(3) => '0', portbin(4) => AVRInt, portbin(5) => '0', portbin(6) => '0', portbin(7) => '0', portbout(0) => nARD, portbout(1) => nAWR, portbout(2) => open, portbout(3) => AVRA0, portbout(4) => open, portbout(5) => open, portbout(6) => LED1n, portbout(7) => LED2n, portdin => (others => '0'), portdout(0) => open, portdout(1) => open, portdout(2) => open, portdout(3) => open, portdout(4) => SDSS, portdout(5) => open, portdout(6) => open, portdout(7) => open, -- FUDLR portein => ioport, porteout => open, spi_mosio => SDMOSI, spi_scko => SDCLK, spi_misoi => SDMISO, rxd => avr_RxD, txd => avr_TxD_atommc ); ioport <= "111" & Joystick1(5) & Joystick1(0) & Joystick1(1) & Joystick1(2) & Joystick1(3); Inst_AtomPL8: entity work.AtomPL8 port map( clk => clk_main, enable => pl8_enable, nRST => RSTn, RW => cpu_R_W_n, Addr => cpu_addr(2 downto 0), DataIn => cpu_dout, DataOut => pl8_data, AVRDataIn => AVRDataIn, AVRDataOut => AVRDataOut, nARD => nARD, nAWR => nAWR, AVRA0 => AVRA0, AVRINTOut => AVRInt, AtomIORDOut => open, AtomIOWROut => open ); LED1 <= not LED1n; LED2 <= not LED2n; end generate; Inst_not_atommc2: if not CImplAtoMMC2 generate avr_TxD_atommc <= '1'; end generate; --------------------------------------------------------------------- -- No SD Filesystem --------------------------------------------------------------------- Inst_no_atommc2: if ((not CImplSDDOS) and (not CImplAtoMMC2)) generate SDCLK <= '1'; SDSS <= '1'; SDMOSI <= '1'; LED1 <= '0'; LED2 <= '0'; end generate; --------------------------------------------------------------------- -- Ram Rom board functionality --------------------------------------------------------------------- process(clk_main) begin if rising_edge(clk_main) then if sample_data = '1' then ExternDout1 <= ExternDout; end if; end if; end process; Inst_RamRomNone: if (CImplRamRomNone) generate Inst_RamRomNone_comp: entity work.RamRom_None port map( clock => clk_main, reset_n => RSTn, -- signals from/to 6502 cpu_addr => cpu_addr, cpu_we => not_cpu_R_W_n, cpu_dout => cpu_dout, cpu_din => extern_data, -- signals from/to external memory system ExternCE => ExternCE, ExternWE => ExternWE, ExternA => ExternA, ExternDin => ExternDin1, ExternDout => ExternDout1 ); turbo <= key_turbo; end generate; Inst_RamRomPhill: if (CImplRamRomPhill) generate Inst_RamRomPhill_comp: entity work.RamRom_Phill port map( clock => clk_main, reset_n => RSTn, -- signals from/to 6502 cpu_addr => cpu_addr, cpu_we => not_cpu_R_W_n, cpu_dout => cpu_dout, cpu_din => extern_data, -- signals from/to external memory system ExternCE => ExternCE, ExternWE => ExternWE, ExternA => ExternA, ExternDin => ExternDin1, ExternDout => ExternDout1 ); turbo <= key_turbo; end generate; Inst_RamRomAtom2015: if (CImplRamRomAtom2015) generate Inst_RamRomAtom2015_comp: entity work.RamRom_Atom2015 generic map( InitBFFE => InitBFFE_Atom2015, InitBFFF => x"00" ) port map( clock => clk_main, reset_n => RSTn, -- signals from/to 6502 cpu_addr => cpu_addr, cpu_we => not_cpu_R_W_n, cpu_dout => cpu_dout, cpu_din => extern_data, -- signals from/to external memory system ExternCE => ExternCE, ExternWE => ExternWE, ExternA => ExternA, ExternDin => ExternDin1, ExternDout => ExternDout1, -- turbo mode control turbo_in => key_turbo, turbo_out => turbo ); end generate; Inst_RamRomSchakelKaart: if (CImplRamRomSchakelKaart) generate Inst_RamRomSchakelKaart_comp: entity work.RamRom_SchakelKaart port map( clock => clk_main, reset_n => RSTn, -- signals from/to 6502 cpu_addr => cpu_addr, cpu_we => not_cpu_R_W_n, cpu_dout => cpu_dout, cpu_din => extern_data, -- signals from/to external memory system ExternCE => ExternCE, ExternWE => ExternWE, ExternA => ExternA, ExternDin => ExternDin1, ExternDout => ExternDout1 ); turbo <= key_turbo; end generate; ExternDin <= ExternDin1 when cpu_R_W_n = '0' else cpu_din; --------------------------------------------------------------------- -- Profiling Counters --------------------------------------------------------------------- Inst_ProfilingCounters: if (CImplProfilingCounters) generate p_reset <= p_counter_ctrl(0); p_pause <= p_counter_ctrl(1); process(clk_main) begin if rising_edge(clk_main) then -- Detect falling edge of reset p_reset_last <= p_reset; if (p_reset_last = '1' and p_reset = '0') or (p_pause = '0' and p_divider_counter = 0) then -- Reload the divider on falling edge of reset, or when it reaches 0 p_divider_counter <= p_divider_latch - 1; elsif p_pause = '0' then -- Otherwise decrent divider if not paused p_divider_counter <= p_divider_counter - 1; end if; -- Clock main counter when divider reaches 0 if p_divider_counter = 0 and p_reset = '0' and p_pause = '0' then p_profile_counter <= p_profile_counter + 1; end if; -- CPU Writes to Counter Registers if cpu_clken = '1' and counter_enable = '1' and cpu_R_W_n = '0' then case cpu_addr(3 downto 0) is when x"0" => p_counter_ctrl <= cpu_dout; when x"4" => p_divider_latch(7 downto 0) <= cpu_dout; when x"5" => p_divider_latch(15 downto 8) <= cpu_dout; when x"6" => p_divider_latch(23 downto 16) <= cpu_dout; when x"7" => p_divider_latch(31 downto 24) <= cpu_dout; when x"8" => p_profile_counter(7 downto 0) <= cpu_dout; when x"9" => p_profile_counter(15 downto 8) <= cpu_dout; when x"A" => p_profile_counter(23 downto 16) <= cpu_dout; when x"B" => p_profile_counter(31 downto 24) <= cpu_dout; when others => null; end case; end if; -- CPU Reads from Counter Registers case cpu_addr(3 downto 0) is when x"0" => p_counter_data <= p_counter_ctrl; when x"4" => p_counter_data <= p_divider_latch(7 downto 0); when x"5" => p_counter_data <= p_divider_latch(15 downto 8); when x"6" => p_counter_data <= p_divider_latch(23 downto 16); when x"7" => p_counter_data <= p_divider_latch(31 downto 24); when x"8" => p_counter_data <= p_profile_counter(7 downto 0); when x"9" => p_counter_data <= p_profile_counter(15 downto 8); when x"A" => p_counter_data <= p_profile_counter(23 downto 16); when x"B" => p_counter_data <= p_profile_counter(31 downto 24); when others => p_counter_data <= x"00"; end case; end if; end process; end generate; --------------------------------------------------------------------- -- Device enables --------------------------------------------------------------------- process(cpu_addr) begin -- All regions normally de-selected mc6522_enable <= '0'; i8255_enable <= '0'; video_ram_enable <= '0'; sid_enable <= '0'; pl8_enable <= '0'; reg_enable <= '0'; uart_enable <= '0'; counter_enable <= '0'; ext_ramrom_enable <= '0'; ext_bus_enable <= '0'; case cpu_addr(15 downto 12) is when x"0" => ext_ramrom_enable <= '1'; -- 0x0000 -- 0x03ff is RAM when x"1" => ext_ramrom_enable <= '1'; when x"2" => ext_ramrom_enable <= '1'; when x"3" => ext_ramrom_enable <= '1'; when x"4" => ext_ramrom_enable <= '1'; when x"5" => ext_ramrom_enable <= '1'; when x"6" => ext_ramrom_enable <= '1'; when x"7" => ext_ramrom_enable <= '1'; when x"8" => video_ram_enable <= '1'; -- 0x8000 -- 0x9fff is RAM when x"9" => video_ram_enable <= '1'; when x"A" => ext_ramrom_enable <= '1'; when x"B" => if cpu_addr(11 downto 4) = x"00" then -- 0xB00x 8255 PIA i8255_enable <= '1'; elsif cpu_addr(11 downto 4) = x"40" then -- 0xB40x AtoMMC/SPI if CImplSDDOS or CImplAtoMMC2 then pl8_enable <= '1'; else ext_bus_enable <= '1'; end if; elsif cpu_addr(11 downto 4) = x"80" then -- 0xB80x 6522 VIA if CImplVIA then mc6522_enable <= '1'; else ext_bus_enable <= '1'; end if; elsif cpu_addr(11 downto 4) = x"DA" then -- 0xBDAx Profiling Counters if CImplProfilingCounters then counter_enable <= '1'; else ext_bus_enable <= '1'; end if; elsif cpu_addr(11 downto 4) = x"DB" then -- 0xBDBx UART if CImplUart then uart_enable <= '1'; else ext_bus_enable <= '1'; end if; elsif cpu_addr(11 downto 5) & '0' = x"DC" then -- 0xBDCx, 0xBDDx SID if CImplSID then sid_enable <= '1'; else ext_bus_enable <= '1'; end if; elsif cpu_addr(11 downto 5) & '0' = x"DE" then -- 0xBDEx, 0xBDFx GODIL Registers reg_enable <= '1'; elsif cpu_addr(11 downto 2) & "00"= x"FFC" then -- 0xBFFC-BFFF RomLatch ext_ramrom_enable <= '1'; elsif cpu_addr(11 downto 7) /= "11011" then -- any non-mapped 0xBxxx address is deemed external ext_bus_enable <= '1'; -- apart from 0xBD80-0xBDFF which are deemed reserved end if; when x"C" => ext_ramrom_enable <= '1'; when x"D" => ext_ramrom_enable <= '1'; when x"E" => ext_ramrom_enable <= '1'; when x"F" => ext_ramrom_enable <= '1'; when others => null; end case; end process; -- External bus enable ExternBus <= ext_bus_enable; --------------------------------------------------------------------- -- CPU data input multiplexor --------------------------------------------------------------------- cpu_din <= godil_data when video_ram_enable = '1' else i8255_data when i8255_enable = '1' else mc6522_data when mc6522_enable = '1' else godil_data when sid_enable = '1' and CImplSID else godil_data when uart_enable = '1' and CImplUart else godil_data when reg_enable = '1' else -- TODO add CImpl constraint pl8_data when pl8_enable = '1' and CImplSDDOS else pl8_data when pl8_enable = '1' and CImplAtoMMC2 else extern_data when ext_ramrom_enable = '1' else extern_data when ext_bus_enable = '1' else p_counter_data when counter_enable = '1' and CImplProfilingCounters else x"f1"; -- un-decoded locations -------------------------------------------------------- -- Clock enable generator -------------------------------------------------------- process(clk_main) variable mask4 : std_logic_vector(4 downto 0); variable limit : integer; variable phi2l : integer; variable phi2h : integer; variable sampl : integer; begin -- Don't include reset here, so 6502 continues to be clocked during reset if rising_edge(clk_main) then -- Counter: -- main_clock = 32MHz -- 1MHz 0..31 -- 2MHz 0..15 -- 4MHz 0..7 -- 8MHz 0..3 -- main_clock = 16MHz -- 1MHz 0..15 -- 2MHz 0..7 -- 4MHz 0..3 -- 8MHz not supported -- Work out optimal timing -- mask4 - mask to give a 4x speed clock -- limit - maximum value of clk_counter so it wraps at 1MHz -- phi2l - when phi2 should go low -- phi2h - when phi2 should go high -- sample - when sample_data should asserted -- none of the variables are stateful if (MainClockSpeed = 32000000) then -- 32MHz case (turbo_synced) is when "11" => mask4 := "00000"; limit := 3; phi2l := 3; phi2h := 1; sampl := 2; -- 8MHz when "10" => mask4 := "00001"; limit := 7; phi2l := 7; phi2h := 3; sampl := 6; -- 4MHz when "01" => mask4 := "00011"; limit := 15; phi2l := 15; phi2h := 7; sampl := 14; -- 2MHz when others => mask4 := "00111"; limit := 31; phi2l := 31; phi2h := 15; sampl := 30; -- 1MHz end case; else -- 16MHz case (turbo_synced) is when "10" => mask4 := "00000"; limit := 3; phi2l := 3; phi2h := 1; sampl := 2; -- 4MHz when "01" => mask4 := "00001"; limit := 7; phi2l := 7; phi2h := 3; sampl := 6; -- 2MHz when others => mask4 := "00011"; limit := 15; phi2l := 15; phi2h := 7; sampl := 14; -- 1MHz end case; end if; if clk_counter = limit then turbo_synced <= turbo; -- only change the timing at the end of the cycle clk_counter <= (others => '0'); else clk_counter <= clk_counter + 1; end if; -- Assert cpu_clken in cycle 0 if clk_counter = limit then cpu_clken <= '1'; else cpu_clken <= '0'; end if; -- Assert pia_clken in anti-phase with cpu_clken if clk_counter = phi2h then pia_clken <= '1'; else pia_clken <= '0'; end if; -- Assert via1_clken in cycle 0 if clk_counter = limit then via1_clken <= '1'; else via1_clken <= '0'; end if; -- Assert via4 at 4x the rate of via1 if (clk_counter and mask4) = (std_logic_vector(to_unsigned(limit,5)) and mask4) then via4_clken <= '1'; else via4_clken <= '0'; end if; -- Assert phi2 at the specified times if clk_counter = phi2h then phi2 <= '1'; elsif clk_counter = phi2l then phi2 <= '0'; end if; -- Assert sample_data at the specified time if clk_counter = sampl then sample_data <= '1'; else sample_data <= '0'; end if; end if; end process; end BEHAVIORAL;
apache-2.0
0277cdd0a311b9c7837b45c549a644d6
0.425177
4.028056
false
false
false
false
abyrne55/my-little-processor
testbench_project.vhd
1
7,040
LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; library STD; use STD.textio.all; -- entity declaration for your testbench.Dont declare any ports here ENTITY testbench_project IS END testbench_project; ARCHITECTURE behavior OF testbench_project IS -- ------------------ Add Componenets ------------------ -- Add your components here COMPONENT my_little_processor IS PORT ( clock, reset : IN STD_LOGIC; data_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0); flag_out : OUT STD_LOGIC; done_out : OUT STD_LOGIC; c_state_preout: OUT INTEGER; instr_preout : OUT STD_LOGIC_VECTOR(3 downto 0); read_addr, reg0_out, reg1_out, main_bus_out, ALU_preout, G_preout, A_preout: OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ); END COMPONENT; -- ------------------ Add Componenets ------------------ -- cnt is for the testbench only, use to set test values for every clock cycle signal cnt: integer:= 0; -- Internal Signals -- Your circuit will need clk and reset signals. signal clk_in, reset_in : STD_LOGIC; -- For the initial part, it will also need an assembly code input signal code : std_logic_vector(22 downto 0); signal flag : std_logic; signal done_sig: std_logic; signal data_in: std_logic_vector(15 downto 0); signal c_state: INTEGER; signal instruction_code: STD_LOGIC_VECTOR(3 downto 0); signal read_addr, reg0_out, reg1_out, main_bus_out, ALU_preout, G_preout, A_preout: STD_LOGIC_VECTOR(15 DOWNTO 0); signal RAM_load_count: INTEGER := 0; -- For the testbench, the assembly code is 23 bits of the following form -- Load: 3 bit operation code (000), 4-bit destination register (note x"" -- means hex, so for example, x"A" would mean register 10), then 16-bit data -- value (note once again this is defined using hex. e.g x"12AB" would equal -- "0001 0010 1010 1011") -- mov: 3 bit operation code (001), 4-bit destination register, 4-bit input register, 12 unused bits -- add: 3 bit operation code (010), 4-bit input and destination register, 4-bit input register, 12 unused bits -- add: 3 bit operation code (011), 4-bit input and destination register, 4-bit input register, 12 unused bits -- ldpc: 3 bit operation code (100), 4-bit destination register, 16 unused bits -- branch: 3 bit operation code (101), 4-bit destination register, 16 unused bits -- Feel free to create your own assembly code -- ------------------ Add Your Internal Signals (if needed) ------------------ -- You may not need anything, you can design your processor to only -- use clk_in, reset_in and (assembly) code signals. -- If you instatiate multiple modules, you may need them -- ------------------ Add Your Internal Signals (if needed) ------------------ BEGIN PROCESS(code, RAM_load_count) begin IF code(22 downto 20) = "000" AND RAM_load_count = 1 THEN data_in <= code(15 downto 0); RAM_load_count <= 0; ELSIF code(22 downto 20) = "000" THEN RAM_load_count <= RAM_load_count + 1; data_in(15 downto 12) <= "0" & code(22 downto 20); data_in(11 downto 8) <= code(19 downto 16); data_in(7 downto 0) <= "00000000"; ELSE data_in <= code(22 downto 7); END IF; END PROCESS; -- ------------------ Instantiate modules ------------------ -- Instantiate your processor here -- ------------------ Instantiate modules ------------------ my_little_processor0: my_little_processor PORT MAP( clock => clk_in, reset => reset_in, flag_out => flag, done_out => done_sig, data_in => data_in, c_state_preout => c_state, instr_preout => instruction_code, read_addr => read_addr, reg0_out => reg0_out, reg1_out => reg1_out, main_bus_out => main_bus_out, ALU_preout => ALU_preout, G_preout => G_preout, A_preout => A_preout ); -- Create a clk stim_proc: process begin wait for 50 ns; clk_in <= not(clk_in); end process; -- cnt is for the testbench only, use to set test values for every clock cycle stim_proc2: process(clk_in) begin if rising_edge(clk_in) then cnt <= cnt+1; end if; end process; -- This is the 'program'. It loads 4 values into r0 to r3. -- It then stores the current address location in r4 -- It then branches to the 'sum' procedure, located at 50 in memory -- To do this, the value 50 is loaded into r5, then you branch to r5. -- After returning from branch, store the value in r6 -- (IMPORTANT: you can use this testbench irrespective of the branching, -- just do nothing for these commands) -- It then loads another 4 values into r0 to r3 -- Performs the sum of these values and returns -- Finally it computes the xor of the two sums process (cnt) begin case cnt is -- Reset when 0 to 4 => reset_in <= '1'; code <= ("000" & x"0" & x"0000"); -- load r0 x"0001" when 5 to 9 => reset_in <= '0'; code <= ("000" & x"0" & x"0001"); -- load r1 x"0001" when 10 to 14 => reset_in <= '0'; code <= ("000" & x"1" & x"0001"); -- load r2 x"0020" when 15 to 19 => reset_in <= '0'; code <= ("000" & x"2" & x"0020"); -- load r3 x"0020" when 20 to 24 => reset_in <= '0'; code <= ("000" & x"3" & x"0020"); -- load r5 x"0050" when 25 to 29 => reset_in <= '0'; code <= ("000" & x"5" & x"0050"); -- ldpc r4 when 30 to 34 => reset_in <= '0'; code <= ("100" & x"4" & x"0000"); -- branch r5 when 35 to 39 => reset_in <= '0'; code <= ("101" & x"5" & x"0000"); -- add r0 r1 when 40 to 44 => reset_in <= '0'; code <= ("010" & x"0" & x"1" & x"000"); -- add r0 r2 when 45 to 49 => reset_in <= '0'; code <= ("010" & x"0" & x"2" & x"000"); -- add r0 r3 when 50 to 54 => reset_in <= '0'; code <= ("010" & x"0" & x"3" & x"000"); -- branch r4 when 55 to 59 => reset_in <= '0'; code <= ("101" & x"4" & x"0000"); -- mov r6 r0 when 60 to 64 => reset_in <= '0'; code <= ("001" & x"6" & x"0" & x"000"); -- load r0 x"0003" when 65 to 69 => reset_in <= '0'; code <= ("000" & x"0" & x"0003"); -- load r1 x"0004" when 70 to 74 => reset_in <= '0'; code <= ("000" & x"1" & x"0004"); -- load r2 x"001B" when 75 to 79 => reset_in <= '0'; code <= ("000" & x"2" & x"001B"); -- load r3 x"0034" when 80 to 84 => reset_in <= '0'; code <= ("000" & x"3" & x"0050"); -- ldpc r4 when 85 to 89 => reset_in <= '0'; code <= ("100" & x"4" & x"0000"); -- branch r5 when 90 to 94 => reset_in <= '0'; code <= ("101" & x"5" & x"0000"); -- add r0 r1 when 95 to 99 => reset_in <= '0'; code <= ("010" & x"0" & x"1" & x"000"); -- add r0 r2 when 100 to 104 => reset_in <= '0'; code <= ("010" & x"0" & x"2" & x"000"); -- add r0 r3 when 105 to 109 => reset_in <= '0'; code <= ("010" & x"0" & x"3" & x"000"); -- branch r4 when 110 to 114 => reset_in <= '0'; code <= ("101" & x"4" & x"0000"); -- xor r0 r6 when 115 to 120 => reset_in <= '0'; code <= ("001" & x"6" & x"0" & x"000"); when others => reset_in <= '0'; code <= ("001" & x"6" & x"0" & x"000"); end case; end process; END;
mit
006546a16b2892cd5f19ef2a5001eb58
0.583949
2.780411
false
true
false
false
tghaefli/ADD
ISE/FMC_waj/fmc_chn.vhd
1
5,606
------------------------------------------------------------------------------- -- Entity: fmc_chn -- Author: Waj ------------------------------------------------------------------------------- -- Description: -- Floppy-Music Controller (1 channel) ------------------------------------------------------------------------------- -- Total # of FFs: ... tbd ... ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.mcu_pkg.all; entity fmc_chn is generic(N : natural := 0 -- channel number ); port(rst : in std_logic; clk : in std_logic; -- control inputs tick_dur : in std_logic; -- nominal period = 1 ms tick_nco : in std_logic; -- nominal period = 1 us chn_enb : in std_logic; -- outputs to pins fmc_enb : out std_logic; fmc_dir : out std_logic; fmc_stp : out std_logic ); end fmc_chn; architecture rtl of fmc_chn is -- output signals signal stp_cnt : unsigned(6 downto 0); constant MAX_STP : unsigned(6 downto 0) := to_unsigned(79-1,7); signal stp_reg : std_logic; signal dir_reg : std_logic; -- ROM and addressing signal rom_addr : std_logic_vector(FMC_ROM_AW-1 downto 0); signal rom_data : std_logic_vector(FMC_ROM_DW-1 downto 0); signal duration_cnt : unsigned(FMC_DUR_WW-1 downto 0); signal tone_duration : unsigned(FMC_DUR_WW-1 downto 0); signal tone_number : unsigned(FMC_TON_WW-1 downto 0); signal tone_end_evt : std_logic; -- LUT: tone number ==> NCO seed type t_nco_lut is array (2**FMC_TON_WW-1 downto 0) of natural; constant nco_lut : t_nco_lut := ( 0,0,0,0,0,0,0,0,0,0,0,0,0,0,7382,6968,6577,6207,5859,5530,5220,4927,4650,4389,4143,3910,3691, 3484,3288,3104,2930,2765,2610,2463,2325,2195,2071,1955,1845,1742,1644,1552,1465,1383,1305,1232, 1163,1097,1036,978,923,871,822,776,732,691,652,616,581,549,518,489,461,0); -- NCO signals signal seed : unsigned(12 downto 0); -- 13 bit seed signal nco_reg : unsigned(23 downto 0); -- 24 bit NCO begin ----------------------------------------------------------------------------- -- output assignments ----------------------------------------------------------------------------- fmc_stp <= stp_reg; fmc_dir <= dir_reg; ----------------------------------------------------------------------------- -- generate and register FMC outputs ----------------------------------------------------------------------------- P_out: process(rst, clk) begin if rst = '1' then fmc_enb <= '1'; stp_reg <= '0'; dir_reg <= '0'; stp_cnt <= (others => '0'); elsif rising_edge(clk) then -- set enable active during times when any tone is played if tone_number > 0 then -- enable is low-active fmc_enb <= '0'; else fmc_enb <= '1'; end if; -- connect step output to NCO output (MSB) to generate desired frequency stp_reg <= std_logic(nco_reg(nco_reg'left)); -- toggle direction output after every 80 steps (rising edges on fmc_stp) if stp_reg = '0' and std_logic(nco_reg(nco_reg'left)) = '1' then -- rising edge on step output if stp_cnt = MAX_STP then stp_cnt <= (others => '0'); dir_reg <= not dir_reg; else stp_cnt <= stp_cnt + 1; end if; end if; end if; end process; ----------------------------------------------------------------------------- -- ROM addressing and tick counting ----------------------------------------------------------------------------- P_read: process(rst, clk) begin if rst = '1' then duration_cnt <= (others => '0'); tone_end_evt <= '0'; rom_addr <= (others => '0'); elsif rising_edge(clk) then -- default assignment tone_end_evt <= '0'; -- maintain tone duration counter if tick_dur = '1' then if duration_cnt = tone_duration-1 then duration_cnt <= (others => '0'); tone_end_evt <= '1'; else duration_cnt <= duration_cnt + 1; end if; end if; -- maintain ROM address if chn_enb = '0' or tone_duration = FMC_LAST_TONE then -- restart playing from 1st tone rom_addr <= (others => '0'); duration_cnt <= (others => '0'); elsif tone_end_evt = '1' then rom_addr <= std_logic_vector(unsigned(rom_addr)+1); end if; end if; end process; ----------------------------------------------------------------------------- -- channel number dependent FMC ROM instance ----------------------------------------------------------------------------- rom : entity work.fmc_rom generic map(N => N) port map (clk => clk, addr => rom_addr, data => rom_data ); tone_duration <= unsigned(rom_data(FMC_DUR_WW+FMC_TON_WW-1 downto FMC_TON_WW)); tone_number <= unsigned(rom_data(FMC_TON_WW-1 downto 0)); ----------------------------------------------------------------------------- -- NCO (tone frequency generation) ----------------------------------------------------------------------------- P_nco: process(rst, clk) begin if rst = '1' then seed <= (others => '0'); nco_reg <= (others => '0'); elsif rising_edge(clk) then seed <= to_unsigned(nco_lut(to_integer(tone_number)),13); if tick_nco = '1' then nco_reg <= nco_reg + seed; end if; end if; end process; end rtl;
gpl-3.0
baa88b20a5b052754023f05bfd5ce694
0.462183
3.987198
false
false
false
false
hoglet67/AtomFpga
src/common/AVR8/Peripheral/portx.vhd
4
4,513
--********************************************************************************************** -- Parallel Port Peripheral for the AVR Core -- Version 0.7 -- Modified 10.08.2003 -- Designed by Ruslan Lepetenok. -- -- The possibility of implementing level sensitive LATCH instead of edge sensitive DFF -- (for the first stage of the synchronizer) is added. --********************************************************************************************** library IEEE; use IEEE.std_logic_1164.all; use WORK.AVRuCPackage.all; use WORK.SynthCtrlPack.all; -- Synthesis control use WORK.SynchronizerCompPack.all; -- Component declarations for the synchronizers entity pport is generic(PPortNum : natural); port( -- AVR Control ireset : in std_logic; cp2 : in std_logic; adr : in std_logic_vector(15 downto 0); dbus_in : in std_logic_vector(7 downto 0); dbus_out : out std_logic_vector(7 downto 0); iore : in std_logic; iowe : in std_logic; out_en : out std_logic; -- --Info -- miso_LOC : in integer; -- spi_spe : in std_logic; -- External connection -- spi_misoi : out std_logic; portx : out std_logic_vector(7 downto 0); ddrx : out std_logic_vector(7 downto 0); pinx : in std_logic_vector(7 downto 0); irqlines : out std_logic_vector(7 downto 0)); end pport; architecture RTL of pport is signal PORTx_Int : std_logic_vector(portx'range); signal DDRx_Int : std_logic_vector(ddrx'range); signal PINx_Tmp : std_logic_vector(pinx'range); signal PINx_Resync : std_logic_vector(pinx'range); signal PORTx_Sel : std_logic; signal DDRx_Sel : std_logic; signal PINx_Sel : std_logic; begin PORTx_Sel <= '1' when adr=PPortAdrArray(PPortNum).Port_Adr else '0'; DDRx_Sel <= '1' when adr=PPortAdrArray(PPortNum).DDR_Adr else '0'; PINx_Sel <= '1' when adr=PPortAdrArray(PPortNum).Pin_Adr else '0'; --spi_misoi_Sel <= '1' when adr=PPortAdrArray(PPortNum).Pin_Adr else '0'; out_en <= (PORTx_Sel or DDRx_Sel or PINx_Sel) and iore; PORTx_DFF:process(cp2,ireset) begin if (ireset='0') then -- Reset PORTx_Int <= (others => '0'); elsif (cp2='1' and cp2'event) then -- Clock if PORTx_Sel='1' and iowe='1' then -- Clock enable PORTx_Int <= dbus_in; end if; end if; end process; DDRx_DFF:process(cp2,ireset) begin if (ireset='0') then -- Reset DDRx_Int <= (others => '0'); elsif (cp2='1' and cp2'event) then -- Clock if DDRx_Sel='1' and iowe='1' then -- Clock enable DDRx_Int <= dbus_in; end if; end if; end process; -- The first stage of the resynchronizer : DFF or Latch SynchDFF:if not CSynchLatchUsed generate PINxDFFSynchronizer:for i in pinx'range generate PINxDFFSynchronizer_Inst:component SynchronizerDFF port map( NRST => ireset, CLK => cp2, D => pinx(i), Q => PINx_Tmp(i)); end generate; end generate; SynchLatch:if CSynchLatchUsed generate PINxLatchSynchronizer:for i in pinx'range generate PINxLatchSynchronizer_Inst:component SynchronizerLatch port map( D => pinx(i), G => cp2, Q => PINx_Tmp(i), QN => open); end generate; end generate; -- End of the first stage of the resynchronizer PINXInputReg:process(cp2,ireset) begin if (ireset='0') then -- Reset PINx_Resync <= (others => '0'); elsif (cp2='1' and cp2'event) then -- Clock PINx_Resync <= PINx_Tmp; end if; end process; DBusOutMux:for i in pinx'range generate dbus_out(i) <= (PORTx_Int(i) and PORTx_Sel)or(DDRx_Int(i) and DDRx_Sel)or(PINx_Resync(i) and PINx_Sel); irqlines(i) <= PINx_Resync(i); --spi_misoi <= pinx(i) when miso_Loc = i and spi_spe = '1'; end generate; -- Outputs portx <= PORTx_Int; ddrx <= DDRx_Int; end RTL;
apache-2.0
510f46c37109f92225971af78181d7c5
0.519832
3.542386
false
false
false
false
fquinto/Wireless_sensor_network
Avnet_UPC/hdl/leds_4bit_wrapper.vhd
1
7,772
------------------------------------------------------------------------------- -- leds_4bit_wrapper.vhd ------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; library xps_gpio_v2_00_a; use xps_gpio_v2_00_a.all; entity leds_4bit_wrapper is port ( SPLB_Clk : in std_logic; SPLB_Rst : in std_logic; PLB_ABus : in std_logic_vector(0 to 31); PLB_UABus : in std_logic_vector(0 to 31); PLB_PAValid : in std_logic; PLB_SAValid : in std_logic; PLB_rdPrim : in std_logic; PLB_wrPrim : in std_logic; PLB_masterID : in std_logic_vector(0 to 0); PLB_abort : in std_logic; PLB_busLock : in std_logic; PLB_RNW : in std_logic; PLB_BE : in std_logic_vector(0 to 3); PLB_MSize : in std_logic_vector(0 to 1); PLB_size : in std_logic_vector(0 to 3); PLB_type : in std_logic_vector(0 to 2); PLB_lockErr : in std_logic; PLB_wrDBus : in std_logic_vector(0 to 31); PLB_wrBurst : in std_logic; PLB_rdBurst : in std_logic; PLB_wrPendReq : in std_logic; PLB_rdPendReq : in std_logic; PLB_wrPendPri : in std_logic_vector(0 to 1); PLB_rdPendPri : in std_logic_vector(0 to 1); PLB_reqPri : in std_logic_vector(0 to 1); PLB_TAttribute : in std_logic_vector(0 to 15); Sl_addrAck : out std_logic; Sl_SSize : out std_logic_vector(0 to 1); Sl_wait : out std_logic; Sl_rearbitrate : out std_logic; Sl_wrDAck : out std_logic; Sl_wrComp : out std_logic; Sl_wrBTerm : out std_logic; Sl_rdDBus : out std_logic_vector(0 to 31); Sl_rdWdAddr : out std_logic_vector(0 to 3); Sl_rdDAck : out std_logic; Sl_rdComp : out std_logic; Sl_rdBTerm : out std_logic; Sl_MBusy : out std_logic_vector(0 to 1); Sl_MWrErr : out std_logic_vector(0 to 1); Sl_MRdErr : out std_logic_vector(0 to 1); Sl_MIRQ : out std_logic_vector(0 to 1); IP2INTC_Irpt : out std_logic; GPIO_IO_I : in std_logic_vector(0 to 3); GPIO_IO_O : out std_logic_vector(0 to 3); GPIO_IO_T : out std_logic_vector(0 to 3); GPIO2_IO_I : in std_logic_vector(0 to 31); GPIO2_IO_O : out std_logic_vector(0 to 31); GPIO2_IO_T : out std_logic_vector(0 to 31) ); attribute x_core_info : STRING; attribute x_core_info of leds_4bit_wrapper : entity is "xps_gpio_v2_00_a"; end leds_4bit_wrapper; architecture STRUCTURE of leds_4bit_wrapper is component xps_gpio is generic ( C_BASEADDR : std_logic_vector(0 to 31); C_HIGHADDR : std_logic_vector(0 to 31); C_SPLB_AWIDTH : INTEGER; C_SPLB_DWIDTH : INTEGER; C_SPLB_P2P : INTEGER; C_SPLB_MID_WIDTH : INTEGER; C_SPLB_NUM_MASTERS : INTEGER; C_SPLB_NATIVE_DWIDTH : INTEGER; C_SPLB_SUPPORT_BURSTS : INTEGER; C_FAMILY : STRING; C_ALL_INPUTS : INTEGER; C_ALL_INPUTS_2 : INTEGER; C_GPIO_WIDTH : INTEGER; C_GPIO2_WIDTH : INTEGER; C_INTERRUPT_PRESENT : INTEGER; C_DOUT_DEFAULT : std_logic_vector; C_TRI_DEFAULT : std_logic_vector; C_IS_DUAL : INTEGER; C_DOUT_DEFAULT_2 : std_logic_vector; C_TRI_DEFAULT_2 : std_logic_vector ); port ( SPLB_Clk : in std_logic; SPLB_Rst : in std_logic; PLB_ABus : in std_logic_vector(0 to 31); PLB_UABus : in std_logic_vector(0 to 31); PLB_PAValid : in std_logic; PLB_SAValid : in std_logic; PLB_rdPrim : in std_logic; PLB_wrPrim : in std_logic; PLB_masterID : in std_logic_vector(0 to (C_SPLB_MID_WIDTH-1)); PLB_abort : in std_logic; PLB_busLock : in std_logic; PLB_RNW : in std_logic; PLB_BE : in std_logic_vector(0 to ((C_SPLB_DWIDTH/8)-1)); PLB_MSize : in std_logic_vector(0 to 1); PLB_size : in std_logic_vector(0 to 3); PLB_type : in std_logic_vector(0 to 2); PLB_lockErr : in std_logic; PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_DWIDTH-1)); PLB_wrBurst : in std_logic; PLB_rdBurst : in std_logic; PLB_wrPendReq : in std_logic; PLB_rdPendReq : in std_logic; PLB_wrPendPri : in std_logic_vector(0 to 1); PLB_rdPendPri : in std_logic_vector(0 to 1); PLB_reqPri : in std_logic_vector(0 to 1); PLB_TAttribute : in std_logic_vector(0 to 15); Sl_addrAck : out std_logic; Sl_SSize : out std_logic_vector(0 to 1); Sl_wait : out std_logic; Sl_rearbitrate : out std_logic; Sl_wrDAck : out std_logic; Sl_wrComp : out std_logic; Sl_wrBTerm : out std_logic; Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_DWIDTH-1)); Sl_rdWdAddr : out std_logic_vector(0 to 3); Sl_rdDAck : out std_logic; Sl_rdComp : out std_logic; Sl_rdBTerm : out std_logic; Sl_MBusy : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1)); Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1)); Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1)); Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1)); IP2INTC_Irpt : out std_logic; GPIO_IO_I : in std_logic_vector(0 to (C_GPIO_WIDTH-1)); GPIO_IO_O : out std_logic_vector(0 to (C_GPIO_WIDTH-1)); GPIO_IO_T : out std_logic_vector(0 to (C_GPIO_WIDTH-1)); GPIO2_IO_I : in std_logic_vector(0 to (C_GPIO2_WIDTH-1)); GPIO2_IO_O : out std_logic_vector(0 to (C_GPIO2_WIDTH-1)); GPIO2_IO_T : out std_logic_vector(0 to (C_GPIO2_WIDTH-1)) ); end component; begin LEDS_4BIT : xps_gpio generic map ( C_BASEADDR => X"81400000", C_HIGHADDR => X"8140ffff", C_SPLB_AWIDTH => 32, C_SPLB_DWIDTH => 32, C_SPLB_P2P => 0, C_SPLB_MID_WIDTH => 1, C_SPLB_NUM_MASTERS => 2, C_SPLB_NATIVE_DWIDTH => 32, C_SPLB_SUPPORT_BURSTS => 0, C_FAMILY => "spartan3a", C_ALL_INPUTS => 0, C_ALL_INPUTS_2 => 0, C_GPIO_WIDTH => 4, C_GPIO2_WIDTH => 32, C_INTERRUPT_PRESENT => 0, C_DOUT_DEFAULT => X"00000000", C_TRI_DEFAULT => X"ffffffff", C_IS_DUAL => 0, C_DOUT_DEFAULT_2 => X"00000000", C_TRI_DEFAULT_2 => X"ffffffff" ) port map ( SPLB_Clk => SPLB_Clk, SPLB_Rst => SPLB_Rst, PLB_ABus => PLB_ABus, PLB_UABus => PLB_UABus, PLB_PAValid => PLB_PAValid, PLB_SAValid => PLB_SAValid, PLB_rdPrim => PLB_rdPrim, PLB_wrPrim => PLB_wrPrim, PLB_masterID => PLB_masterID, PLB_abort => PLB_abort, PLB_busLock => PLB_busLock, PLB_RNW => PLB_RNW, PLB_BE => PLB_BE, PLB_MSize => PLB_MSize, PLB_size => PLB_size, PLB_type => PLB_type, PLB_lockErr => PLB_lockErr, PLB_wrDBus => PLB_wrDBus, PLB_wrBurst => PLB_wrBurst, PLB_rdBurst => PLB_rdBurst, PLB_wrPendReq => PLB_wrPendReq, PLB_rdPendReq => PLB_rdPendReq, PLB_wrPendPri => PLB_wrPendPri, PLB_rdPendPri => PLB_rdPendPri, PLB_reqPri => PLB_reqPri, PLB_TAttribute => PLB_TAttribute, Sl_addrAck => Sl_addrAck, Sl_SSize => Sl_SSize, Sl_wait => Sl_wait, Sl_rearbitrate => Sl_rearbitrate, Sl_wrDAck => Sl_wrDAck, Sl_wrComp => Sl_wrComp, Sl_wrBTerm => Sl_wrBTerm, Sl_rdDBus => Sl_rdDBus, Sl_rdWdAddr => Sl_rdWdAddr, Sl_rdDAck => Sl_rdDAck, Sl_rdComp => Sl_rdComp, Sl_rdBTerm => Sl_rdBTerm, Sl_MBusy => Sl_MBusy, Sl_MWrErr => Sl_MWrErr, Sl_MRdErr => Sl_MRdErr, Sl_MIRQ => Sl_MIRQ, IP2INTC_Irpt => IP2INTC_Irpt, GPIO_IO_I => GPIO_IO_I, GPIO_IO_O => GPIO_IO_O, GPIO_IO_T => GPIO_IO_T, GPIO2_IO_I => GPIO2_IO_I, GPIO2_IO_O => GPIO2_IO_O, GPIO2_IO_T => GPIO2_IO_T ); end architecture STRUCTURE;
mit
c5668310d84f0e29d4f6382f3777dfca
0.583119
3.073151
false
false
false
false
tghaefli/ADD
EDK/IVK_Repos/IVK_IPLib/pcores/ivk_video_det_v2_01_a/hdl/vhdl/user_logic.vhd
1
18,714
------------------------------------------------------------------ -- _____ -- / \ -- /____ \____ -- / \===\ \==/ -- /___\===\___\/ AVNET -- \======/ -- \====/ ----------------------------------------------------------------- -- -- This design is the property of Avnet. Publication of this -- design is not authorized without written consent from Avnet. -- -- Please direct any questions to: [email protected] -- -- Disclaimer: -- Avnet, Inc. makes no warranty for the use of this code or design. -- This code is provided "As Is". Avnet, Inc assumes no responsibility for -- any errors, which may appear in this code, nor does it make a commitment -- to update the information contained herein. Avnet, Inc specifically -- disclaims any implied warranties of fitness for a particular purpose. -- Copyright(c) 2010 Avnet, Inc. -- All rights reserved. -- ------------------------------------------------------------------ -- -- Create Date: Feb 18, 2010 -- Design Name: IVK -- Module Name: ivk_video_det\user_logic.vhd -- Project Name: IVK -- Target Devices: Spartan-6 -- Avnet Boards: IVK -- -- Tool versions: ISE 12.1 -- -- Description: -- -- Dependencies: -- -- Revision: Feb 18, 2010: 1.01 Initial version -- Mar 02, 2010: 1.02 Add optionnal VDMA Write Port -- Mar 10, 2010: 1.04 Force FSYNC to active high polarity -- Apr 13, 2010: 1.05 Add support for 16bit data width on XSVI input -- May 14, 2010: 2.01 Update for 12.1 -- ------------------------------------------------------------------ -- DO NOT EDIT BELOW THIS LINE -------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library proc_common_v3_00_a; use proc_common_v3_00_a.proc_common_pkg.all; -- DO NOT EDIT ABOVE THIS LINE -------------------- --USER libraries added here ------------------------------------------------------------------------------ -- Entity section ------------------------------------------------------------------------------ -- Definition of Generics: -- C_SLV_DWIDTH -- Slave interface data bus width -- C_NUM_REG -- Number of software accessible registers -- -- Definition of Ports: -- Bus2IP_Clk -- Bus to IP clock -- Bus2IP_Reset -- Bus to IP reset -- Bus2IP_Data -- Bus to IP data bus -- Bus2IP_BE -- Bus to IP byte enables -- Bus2IP_RdCE -- Bus to IP read chip enable -- Bus2IP_WrCE -- Bus to IP write chip enable -- IP2Bus_Data -- IP to Bus data bus -- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement -- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement -- IP2Bus_Error -- IP to Bus error response ------------------------------------------------------------------------------ entity user_logic is generic ( -- ADD USER GENERICS BELOW THIS LINE --------------- C_GEN_FSYNC : integer := 0; C_GEN_XSVI_OUT : integer := 1; C_GEN_WD_VDMA : integer := 0; --C_VIDEO_INTERFACE : integer := 0; C_XSVII_DATA_WIDTH : integer := 24; C_XSVIO_DATA_WIDTH : integer := 24; C_VDMA_DATA_WIDTH : integer := 32; -- ADD USER GENERICS ABOVE THIS LINE --------------- -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol parameters, do not add to or delete C_SLV_DWIDTH : integer := 32; C_NUM_REG : integer := 4; C_FAMILY : string := "spartan6" -- DO NOT EDIT ABOVE THIS LINE --------------------- ); port ( -- ADD USER PORTS BELOW THIS LINE ------------------ -- Global Reset (asynchronous) reset : in std_logic; clk : in std_logic; -- XSVI Input Port xsvi_vsync_i : in std_logic; xsvi_hsync_i : in std_logic; xsvi_vblank_i : in std_logic; xsvi_hblank_i : in std_logic; xsvi_active_video_i : in std_logic; xsvi_video_data_i : in std_logic_vector((C_XSVII_DATA_WIDTH-1) downto 0); -- XSVI Output Port xsvi_vsync_o : out std_logic; xsvi_hsync_o : out std_logic; xsvi_vblank_o : out std_logic; xsvi_hblank_o : out std_logic; xsvi_active_video_o : out std_logic; xsvi_video_data_o : out std_logic_vector((C_XSVIO_DATA_WIDTH-1) downto 0); -- VDMA Write Port --vdma_wcmd_clk : out std_logic; vdma_wd_clk : out std_logic; vdma_wd_write : out std_logic; vdma_wd_data : out std_logic_vector((C_VDMA_DATA_WIDTH-1) downto 0); vdma_wd_data_be : out std_logic_vector(((C_VDMA_DATA_WIDTH/8)-1) downto 0); -- Frame Sync Output Port fsync_o : out std_logic; -- Debug Ports debug1_o : out std_logic_vector((5+C_XSVII_DATA_WIDTH-1) downto 0); debug2_o : out std_logic_vector(31 downto 0); -- ADD USER PORTS ABOVE THIS LINE ------------------ -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol ports, do not add to or delete Bus2IP_Clk : in std_logic; Bus2IP_Reset : in std_logic; Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1); Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1); Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1); Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1); IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1); IP2Bus_RdAck : out std_logic; IP2Bus_WrAck : out std_logic; IP2Bus_Error : out std_logic -- DO NOT EDIT ABOVE THIS LINE --------------------- ); attribute SIGIS : string; attribute SIGIS of Bus2IP_Clk : signal is "CLK"; attribute SIGIS of Bus2IP_Reset : signal is "RST"; end entity user_logic; ------------------------------------------------------------------------------ -- Architecture section ------------------------------------------------------------------------------ architecture rtl of user_logic is function toLittleEndian (a : std_logic_vector) return std_logic_vector is variable result : std_logic_vector(a'length-1 downto 0); begin for i in result'RANGE loop result(i) := a(a'length-1-i); end loop; return result; end; function toBigEndian (a: std_logic_vector) return std_logic_vector is variable result : std_logic_vector(0 to a'length-1); begin for i in result'RANGE loop result(i) := a(a'length-1-i); end loop; return result; end; ------------------------------------------ -- Signals for user logic slave model s/w accessible register example ------------------------------------------ signal slv_reg0 : std_logic_vector(0 to C_SLV_DWIDTH-1); signal slv_reg1 : std_logic_vector(0 to C_SLV_DWIDTH-1); signal slv_reg2 : std_logic_vector(0 to C_SLV_DWIDTH-1); signal slv_reg3 : std_logic_vector(0 to C_SLV_DWIDTH-1); signal slv_reg_write_sel : std_logic_vector(0 to 3); signal slv_reg_read_sel : std_logic_vector(0 to 3); signal slv_ip2bus_data : std_logic_vector(0 to C_SLV_DWIDTH-1); signal slv_read_ack : std_logic; signal slv_write_ack : std_logic; -- signal dummy1_reg : std_logic_vector(31 downto 0); -- signal dummy2_reg : std_logic_vector(31 downto 0); -- signal dummy3_reg : std_logic_vector(31 downto 0); -- signal dummy4_reg : std_logic_vector(31 downto 0); -- -- XSVI Input Registers -- signal xsvi_vsync_r : std_logic; signal xsvi_hsync_r : std_logic; signal xsvi_vblank_r : std_logic; signal xsvi_hblank_r : std_logic; signal xsvi_active_video_r : std_logic; signal xsvi_video_data_r : std_logic_vector((C_XSVII_DATA_WIDTH-1) downto 0); -- -- Video Dimension Counters -- signal active_video_d1 : std_logic; signal active_video_d2 : std_logic; -- signal vsync_d1 : std_logic; signal vsync_d2 : std_logic; -- signal width_counter : unsigned(15 downto 0); signal height_counter : unsigned(15 downto 0); signal video_width : std_logic_vector(15 downto 0); signal video_height : std_logic_vector(15 downto 0); -- -- Vsync Polarity Detection -- signal vsync_polarity : std_logic; begin --USER logic implementation added here ------------------------------------------ -- Example code to read/write user logic slave model s/w accessible registers -- -- Note: -- The example code presented here is to show you one way of reading/writing -- software accessible registers implemented in the user logic slave model. -- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond -- to one software accessible register by the top level template. For example, -- if you have four 32 bit software accessible registers in the user logic, -- you are basically operating on the following memory mapped registers: -- -- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register -- "10000000" C_BASEADDR + 0x00 -- "01000000" C_BASEADDR + 0x04 -- "00100000" C_BASEADDR + 0x08 -- "00010000" C_BASEADDR + 0x0C -- "00001000" C_BASEADDR + 0x10 -- "00000100" C_BASEADDR + 0x14 -- "00000010" C_BASEADDR + 0x18 -- "00000001" C_BASEADDR + 0x1C -- ------------------------------------------ slv_reg_write_sel <= Bus2IP_WrCE(0 to C_NUM_REG-1); slv_reg_read_sel <= Bus2IP_RdCE(0 to C_NUM_REG-1); slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3); slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1) or Bus2IP_RdCE(2) or Bus2IP_RdCE(3); -- implement slave model software accessible register(s) SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is begin if Bus2IP_Clk'event and Bus2IP_Clk = '1' then if Bus2IP_Reset = '1' then slv_reg0 <= (others => '0'); slv_reg1 <= (others => '0'); slv_reg2 <= (others => '0'); slv_reg3 <= (others => '0'); else case slv_reg_write_sel is when "1000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg0(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7); end if; end loop; when "0100" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg1(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7); end if; end loop; when "0010" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg2(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7); end if; end loop; when "0001" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg3(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7); end if; end loop; when others => null; end case; end if; end if; end process SLAVE_REG_WRITE_PROC; -- implement slave model software accessible register(s) read mux SLAVE_REG_READ_PROC : process( slv_reg_read_sel ) is begin case slv_reg_read_sel is -- when "1000" => slv_ip2bus_data <= toBigEndian(X"0000" & video_width); -- when "0100" => slv_ip2bus_data <= toBigEndian(X"0000" & video_height); when "1000" => slv_ip2bus_data <= X"0000" & video_width; when "0100" => slv_ip2bus_data <= X"0000" & video_height; when "0010" => slv_ip2bus_data <= slv_reg2; when "0001" => slv_ip2bus_data <= slv_reg3; when others => slv_ip2bus_data <= (others => '0'); end case; end process SLAVE_REG_READ_PROC; IP_REG_PROC : process(clk) is begin if rising_edge(clk) then -- dummy1_reg <= toLittleEndian(slv_reg0); -- dummy2_reg <= toLittleEndian(slv_reg1); -- dummy3_reg <= toLittleEndian(slv_reg2); -- dummy4_reg <= toLittleEndian(slv_reg3); end if; end process IP_REG_PROC; ------------------------------------------ -- Example code to drive IP to Bus signals ------------------------------------------ IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else (others => '0'); IP2Bus_WrAck <= slv_write_ack; IP2Bus_RdAck <= slv_read_ack; IP2Bus_Error <= '0'; -- -- XSVI Input Registers -- xsvi_iregs_l : process (clk) begin if rising_edge( clk ) then xsvi_vsync_r <= xsvi_vsync_i; xsvi_hsync_r <= xsvi_hsync_i; xsvi_vblank_r <= xsvi_vblank_i; xsvi_hblank_r <= xsvi_hblank_i; xsvi_active_video_r <= xsvi_active_video_i; xsvi_video_data_r <= xsvi_video_data_i; end if; end process; -- -- Video Dimension Counters -- video_det_l : process (clk, reset) begin if ( reset = '1' ) then active_video_d1 <= '0'; active_video_d2 <= '0'; -- vsync_d1 <= '0'; vsync_d2 <= '0'; -- width_counter <= (others => '0'); height_counter <= (others => '0'); video_width <= (others => '0'); video_height <= (others => '0'); elsif rising_edge( clk ) then -- Horizontal Counter -- - increment during active_video -- - latch result and clear at falling edge of active_video active_video_d1 <= xsvi_active_video_r; active_video_d2 <= active_video_d1; if ( xsvi_active_video_r = '1' ) then width_counter <= width_counter + 1; end if; if ( active_video_d1 = '0' and active_video_d2 = '1' ) then video_width <= std_logic_vector(width_counter); width_counter <= (others => '0'); end if; -- Vertical Counter -- - increment at falling edge of active_video -- - latch result and clear at rising_edge of vsync vsync_d1 <= xsvi_vsync_r; vsync_d2 <= vsync_d1; if ( active_video_d1 = '0' and active_video_d2 = '1' ) then height_counter <= height_counter + 1; end if; if ( vsync_d1 = '1' and vsync_d2 = '0' ) then video_height <= std_logic_vector(height_counter); height_counter <= (others => '0'); end if; end if; end process; -- -- XSVI Output Port -- xsvi_output_l : process (clk) begin if rising_edge( clk ) then -- default values xsvi_video_data_o <= (others => '0'); xsvi_vsync_o <= xsvi_vsync_r; xsvi_hsync_o <= xsvi_hsync_r; xsvi_vblank_o <= xsvi_vblank_r; xsvi_hblank_o <= xsvi_hblank_r; xsvi_active_video_o <= xsvi_active_video_r; xsvi_video_data_o(C_XSVII_DATA_WIDTH-1 downto 0) <= xsvi_video_data_r; end if; end process; -- -- VDMA Write Port -- --vdma_wcmd_clk <= clk; vdma_wd_clk <= clk; vdma_write_l : process (clk) begin if rising_edge( clk ) then -- default values vdma_wd_data <= (others => '0'); vdma_wd_write <= xsvi_active_video_r; vdma_wd_data(C_XSVII_DATA_WIDTH-1 downto 0) <= xsvi_video_data_r; vdma_wd_data_be <= (others => '1'); end if; end process; -- -- Vsync Polarity Detection -- vsync_polarity_l : process (clk) begin if rising_edge( clk ) then if ( xsvi_active_video_r = '1' ) then vsync_polarity <= not xsvi_vsync_r; end if; end if; end process; -- -- Frame Sync Output Port -- fsync_l : process (clk) begin if rising_edge( clk ) then if ( vsync_polarity = '1' ) then fsync_o <= xsvi_vsync_r; else fsync_o <= not xsvi_vsync_r; end if; end if; end process; -- -- Debug Ports -- debug_l : process (clk) begin if rising_edge( clk ) then debug1_o <= xsvi_vsync_r & xsvi_hsync_r & xsvi_vblank_r & xsvi_hblank_r & xsvi_active_video_r & xsvi_video_data_r; debug2_o(31 downto 16) <= std_logic_vector(width_counter); debug2_o(15 downto 0) <= std_logic_vector(height_counter); end if; end process; end rtl;
gpl-3.0
fdc8aebbaca100220f172281f98320b1
0.478839
3.802886
false
false
false
false
hoglet67/AtomFpga
src/xilinx/bootstrap.vhd
1
11,359
-------------------------------------------------------------------------------- -- Copyright (c) 2015 David Banks -------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / -- \ \ \/ -- \ \ -- / / Filename : bootstrap.vhd -- /___/ /\ Timestamp : 28/07/2015 -- \ \ / \ -- \___\/\___\ -- --Design Name: bootstrap --Device: Spartan6 LX9 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; library UNISIM; use UNISIM.Vcomponents.all; entity bootstrap is generic ( -- whether to gate the WE signal with the clock gated_write : boolean := true; -- length user data in flash user_length : std_logic_vector(23 downto 0) := x"040000" ); port ( clock : in std_logic; -- initiate bootstrap powerup_reset_n : in std_logic; -- high when FLASH is being copied to SRAM, can be used by user as active high reset bootstrap_busy : out std_logic; -- start address of user data in FLASH user_address : in std_logic_vector(23 downto 0); -- interface from design RAM_nOE : in std_logic; RAM_nWE : in std_logic; RAM_nCS : in std_logic; RAM_A : in std_logic_vector (18 downto 0); RAM_Din : in std_logic_vector (7 downto 0); RAM_Dout : out std_logic_vector (7 downto 0); -- interface to external SRAM SRAM_nOE : out std_logic; SRAM_nWE : out std_logic; SRAM_nCS : out std_logic; SRAM_A : out std_logic_vector (20 downto 0); SRAM_D : inout std_logic_vector (7 downto 0); -- interface to external FLASH FLASH_CS : out std_logic; -- Active low FLASH chip select FLASH_SI : out std_logic; -- Serial output to FLASH chip SI pin FLASH_CK : out std_logic; -- FLASH clock FLASH_SO : in std_logic -- Serial input from FLASH chip SO pin ); end; architecture behavioral of bootstrap is -- the inverted clock signal clock_n : std_logic; -- an internal clock enable, avoiding gated clocks signal clock_en : std_logic := '0'; -- internal signals for SRAM interface signal SRAM_Din : std_logic_vector (7 downto 0); signal SRAM_nDOE : std_logic_vector (7 downto 0); signal SRAM_nWE_int : std_logic; signal SRAM_nWE_idle : std_logic; -- -- bootstrap signals -- signal flash_init : std_logic; -- when low places FLASH driver in init state signal flash_Done : std_logic; -- FLASH init finished when high signal flash_data : std_logic_vector(7 downto 0); -- bootstrap control of SRAM, these signals connect to SRAM when boostrap_busy = '1' signal bs_A : std_logic_vector(18 downto 0); signal bs_Din : std_logic_vector(7 downto 0); signal bs_nCS : std_logic; signal bs_nWE : std_logic; signal bs_nOE : std_logic; signal bs_busy : std_logic; -- for bootstrap state machine type BS_STATE_TYPE is ( INIT, START_READ_FLASH, READ_FLASH, FLASH0, FLASH1, FLASH2, FLASH3, FLASH4, FLASH5, FLASH6, FLASH7, WAIT0, WAIT1, WAIT2, WAIT3, WAIT4, WAIT5, WAIT6, WAIT7, WAIT8, WAIT9, WAIT10, WAIT11 ); signal bs_state : BS_STATE_TYPE := INIT; begin bootstrap_busy <= bs_busy; -------------------------------------------------------- -- SRAM Multiplexor -------------------------------------------------------- SRAM_Din <= bs_Din when bs_busy = '1' else RAM_Din; SRAM_A(18 downto 0) <= bs_A when bs_busy = '1' else RAM_A; SRAM_A(19) <= '0'; SRAM_A(20) <= '0'; SRAM_nCS <= bs_nCS when bs_busy = '1' else RAM_nCS; SRAM_nOE <= bs_nOE when bs_busy = '1' else RAM_nOE; -------------------------------------------------------- -- Generate a gated RAM WE and Dout tristate controls -------------------------------------------------------- clock_n <= not clock; -- The point of all this is to avoid conflicts with the SRAM -- where the data bus changes direction -- On the falling edge of clock_32, SRAM_nWE goes low if SRAM_nWE_int is low -- On the rising edhe of clock_32, SRAM_nWE goes high again SRAM_nWE_int <= bs_nWE when bs_busy = '1' else RAM_nWE; SRAM_nWE_idle <= '1' when gated_write else SRAM_nWE_int; rx_clk_ddr : ODDR2 port map ( Q => SRAM_nWE, C0 => clock_n, C1 => clock, CE => '1', D0 => SRAM_nWE_int, D1 => SRAM_nWE_idle, R => '0', S => '0' ); gen_sram_data_io: for i in 0 to 7 generate -- replicate the ODDR2 for each data bit, because of limited routing oddr2x : ODDR2 port map ( Q => SRAM_nDOE(i), C0 => clock_n, C1 => clock, CE => '1', D0 => SRAM_nWE_int, D1 => SRAM_nWE_idle, R => '0', S => '0' ); -- the active low tristate connects directly to the IOBUFT in the same IOB iobufx : IOBUF generic map ( DRIVE => 8 ) port map ( O => RAM_Dout(i), I => SRAM_Din(i), IO => SRAM_D(i), T => SRAM_nDOE(i) ); end generate; -------------------------------------------------------- -- Bootstrap SRAM from SPI FLASH -------------------------------------------------------- -- flash clock enable toggles on alternate cycles process(clock) begin if rising_edge(clock) then clock_en <= not clock_en; end if; end process; -- bootstrap state machine state_bootstrap : process(clock, powerup_reset_n) begin if powerup_reset_n = '0' then -- external reset pin bs_state <= INIT; -- move state machine to INIT state elsif rising_edge(clock) then if clock_en = '1' then case bs_state is when INIT => bs_busy <= '1'; -- indicate bootstrap in progress (holds user in reset) flash_init <= '0'; -- signal FLASH to begin init bs_A <= (others => '1'); -- SRAM address all ones (becomes zero on first increment) bs_nCS <= '0'; -- SRAM always selected during bootstrap bs_nOE <= '1'; -- SRAM output disabled during bootstrap bs_nWE <= '1'; -- SRAM write enable inactive default state bs_state <= START_READ_FLASH; when START_READ_FLASH => flash_init <= '1'; -- allow FLASH to exit init state if flash_Done = '0' then -- wait for FLASH init to begin bs_state <= READ_FLASH; end if; when READ_FLASH => if flash_Done = '1' then -- wait for FLASH init to complete bs_state <= WAIT0; end if; when WAIT0 => -- wait for the first FLASH byte to be available bs_state <= WAIT1; when WAIT1 => bs_state <= WAIT2; when WAIT2 => bs_state <= WAIT3; when WAIT3 => bs_state <= WAIT4; when WAIT4 => bs_state <= WAIT5; when WAIT5 => bs_state <= WAIT6; when WAIT6 => bs_state <= WAIT7; when WAIT7 => bs_state <= WAIT8; when WAIT8 => bs_state <= FLASH0; when WAIT9 => bs_state <= WAIT10; when WAIT10 => bs_state <= WAIT11; when WAIT11 => bs_state <= FLASH0; -- every 8 clock cycles (32M/8 = 2Mhz) we have a new byte from FLASH -- use this ample time to write it to SRAM, we just have to toggle nWE when FLASH0 => bs_A <= bs_A + 1; -- increment SRAM address bs_state <= FLASH1; -- idle when FLASH1 => bs_Din( 7 downto 0) <= flash_data; -- place byte on SRAM data bus bs_state <= FLASH2; -- idle when FLASH2 => bs_nWE <= '0'; -- SRAM write enable bs_state <= FLASH3; when FLASH3 => bs_state <= FLASH4; -- idle when FLASH4 => bs_state <= FLASH5; -- idle when FLASH5 => bs_state <= FLASH6; -- idle when FLASH6 => bs_nWE <= '1'; -- SRAM write disable bs_state <= FLASH7; when FLASH7 => if "000" & bs_A = user_length then -- when we've reached end address bs_busy <= '0'; -- indicate bootsrap is done flash_init <= '0'; -- place FLASH in init state bs_state <= FLASH7; -- remain in this state until reset else bs_state <= FLASH0; -- else loop back end if; when others => -- catch all, never reached bs_state <= INIT; end case; end if; end if; end process; -- FLASH chip SPI driver u_flash : entity work.spi_flash port map ( flash_clk => clock, flash_clken => clock_en, flash_init => flash_init, flash_addr => user_address, flash_data => flash_data, flash_Done => flash_Done, U_FLASH_CK => FLASH_CK, U_FLASH_CS => FLASH_CS, U_FLASH_SI => FLASH_SI, U_FLASH_SO => FLASH_SO ); end behavioral;
apache-2.0
7ff3ab627fb27236872a28d658387c7b
0.418347
4.596924
false
false
false
false
hoglet67/AtomFpga
src/common/AVR8/JTAG_OCD_Prg/JTAGProgrammerPack.vhd
4
12,299
--********************************************************************************************** -- Constants and types for JTAG "Flash" proggrammer for AVR Core -- Version 0.11 -- Modified 13.05.2004 -- Designed by Ruslan Lepetenok --********************************************************************************************** library IEEE; use IEEE.std_logic_1164.all; package JTAGProgrammerPack is -- JTAG Programming Instruction (Page 311 Table 131) constant CPrgComdRgLength : positive := 15; -- --------------------------------------------------------------------------------------------------- -- 1a. Chip erase constant C_Prg_1A_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001110000000"; constant C_Prg_1A_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010000110000000"; -- "011000110000000" constant C_Prg_1A_3 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001110000000"; -- "011001110000000" constant C_Prg_1A_4 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001110000000"; -- "011001110000000" -- 1b. Poll for chip erase complete constant C_Prg_1B : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001110000000"; -- "011001110000000" -- --------------------------------------------------------------------------------------------------- -- 2a. Enter Flash Write constant C_Prg_2A : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001100010000"; -- 2b. Load Address High Byte (+ 8 Bit) constant C_Prg_2B : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0000111"; -- 2c. Load Address Low Byte (+ 8 Bit) constant C_Prg_2C : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0000011"; -- 2d. Load Data Low Byte (+ 8 Bit) constant C_Prg_2D : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0010011"; -- 2e. Load Data High Byte (+ 8 Bit) constant C_Prg_2E : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0010111"; -- 2f. Latch Data constant C_Prg_2F_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000"; constant C_Prg_2F_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "111011100000000"; constant C_Prg_2F_3 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000"; -- 2g. Write Flash Page constant C_Prg_2G_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000"; constant C_Prg_2G_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011010100000000"; constant C_Prg_2G_3 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000"; constant C_Prg_2G_4 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000"; -- 2h. Poll for Page Write complete constant C_Prg_2H : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000"; -- --------------------------------------------------------------------------------------------------- -- 3a. Enter Flash Read constant C_Prg_3A : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001100000010"; -- 3b. Load Address High Byte (+ 8 Bit) constant C_Prg_3B : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0000111"; -- 3c. Load Address Low Byte (+ 8 Bit) constant C_Prg_3C : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0000011"; -- 3d. Read Data Low and High Byte constant C_Prg_3D_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001000000000"; constant C_Prg_3D_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011000000000"; constant C_Prg_3D_3 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000"; -- --------------------------------------------------------------------------------------------------- -- 4a. Enter EEPROM Write constant C_Prg_4A : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001100010001"; -- 4b. Load Address High Byte (+ 8 Bit) constant C_Prg_4B : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0000111"; -- 4c. Load Address Low Byte (+ 8 Bit) constant C_Prg_4C : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0000011"; -- 4d. Load Data Byte (+ 8 Bit) constant C_Prg_4D : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0010011"; -- 4e. Latch Data constant C_Prg_4E_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000"; constant C_Prg_4E_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "111011100000000"; constant C_Prg_4E_3 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000"; -- 4f. Write EEPROM Page constant C_Prg_4F_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000"; constant C_Prg_4F_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011000100000000"; constant C_Prg_4F_3 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000"; constant C_Prg_4F_4 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000"; -- 4g. Poll for Page Write complete constant C_Prg_4G : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000"; -- --------------------------------------------------------------------------------------------------- -- 5a. Enter EEPROM Read constant C_Prg_5A : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001100000011"; -- 5b. Load Address High Byte (+ 8 Bit) constant C_Prg_5B : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0000111"; -- 5c. Load Address Low Byte (+ 8 Bit) constant C_Prg_5C : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0000011"; -- 5d. Read Data Byte constant C_Prg_5D_1 : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0110011"; constant C_Prg_5D_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001000000000"; constant C_Prg_5D_3 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000"; -- --------------------------------------------------------------------------------------------------- -- 6a. Enter Fuse Write constant C_Prg_6A : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001101000000"; -- 6b. Load Data Low Byte(6) (+ 8 Bit) constant C_Prg_6B : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0010011"; -- 6c. Write Fuse Extended byte constant C_Prg_6C_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011101100000000"; constant C_Prg_6C_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011100100000000"; constant C_Prg_6C_3 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011101100000000"; constant C_Prg_6C_4 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011101100000000"; -- 6d. Poll for Fuse Write complete constant C_Prg_6D : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000"; -- 6e. Load Data Low Byte (+ 8 Bit) constant C_Prg_6E : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0010011"; -- 6f. Write Fuse High byte constant C_Prg_6F_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000"; constant C_Prg_6F_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011010100000000"; constant C_Prg_6F_3 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000"; constant C_Prg_6F_4 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000"; -- 6g. Poll for Fuse Write complete constant C_Prg_6G : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000"; -- 6h. Load Data Low Byte (+ 8 Bit) constant C_Prg_6H : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0010011"; -- 6i. Write Fuse Low byte constant C_Prg_6I_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000"; constant C_Prg_6I_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011000100000000"; constant C_Prg_6I_3 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000"; constant C_Prg_6I_4 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000"; -- 6j. Poll for Fuse Write complete constant C_Prg_6J : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000"; -- --------------------------------------------------------------------------------------------------- -- 7a. Enter Lock bit Write constant C_Prg_7A : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001100100000"; -- 7b. Load Data Byte (+6 Bit) constant C_Prg_7B : std_logic_vector(CPrgComdRgLength-6-1 downto 0) := "001001111"; -- 7c. Write Lock bits constant C_Prg_7C_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000"; constant C_Prg_7C_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011000100000000"; constant C_Prg_7C_3 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000"; constant C_Prg_7C_4 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000"; -- 7d. Poll for Lock bit Write complete constant C_Prg_7D : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000"; -- --------------------------------------------------------------------------------------------------- -- 8a. Enter Fuse/Lock bit Read constant C_Prg_8A : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001100000100"; -- 8b. Read Extended Fuse Byte constant C_Prg_8B_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011101000000000"; constant C_Prg_8B_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011101100000000"; -- 8c. Read Fuse High Byte constant C_Prg_8C_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011111000000000"; constant C_Prg_8C_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011111100000000"; -- 8d. Read Fuse Low Byte constant C_Prg_8D_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001000000000"; constant C_Prg_8D_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000"; -- 8e. Read Lock bits constant C_Prg_8E_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011000000000"; constant C_Prg_8E_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000"; --8f. Read Fuses and Lock bits 0111010000000 constant C_Prg_8F_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011101000000000"; constant C_Prg_8F_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011111000000000"; constant C_Prg_8F_3 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001000000000"; constant C_Prg_8F_4 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011000000000"; constant C_Prg_8F_5 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000"; -- --------------------------------------------------------------------------------------------------- -- 9a. Enter Signature Byte Read 0100010001000 constant C_Prg_9A : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001100001000"; -- 9b. Load Address Byte (+ 8 Bit) constant C_Prg_9B : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0000011"; -- 9c. Read Signature Byte constant C_Prg_9C_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001000000000"; constant C_Prg_9C_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000"; -- --------------------------------------------------------------------------------------------------- -- 10a. Enter Calibration Byte Read constant C_Prg_10A : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001100001000"; -- 10b. Load Address Byte (+ 8 Bit) constant C_Prg_10B : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0000011"; -- 10c. Read Calibration Byte constant C_Prg_10C_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011000000000"; constant C_Prg_10C_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000"; -- --------------------------------------------------------------------------------------------------- -- 11a. Load No Operation Command constant C_Prg_11A_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001100000000"; constant C_Prg_11A_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000"; -- --------------------------------------------------------------------------------------------------- end JTAGProgrammerPack;
apache-2.0
20857e8cf66bb0e0284d72219d9e906e
0.612164
3.180502
false
false
false
false
GSimas/EEL5105
AULA9/FSMctrl.vhd
1
1,723
library IEEE; use ieee.std_logic_1164.all; -- ENTITY entity FSMctrl is port( CLK, RST, ENTER: in std_logic; Operacao: in std_logic_vector(1 downto 0); Selecao: out std_logic_vector(1 downto 0); Enable_1, Enable_2: out std_logic ); end FSMctrl; --ARCHITECTURE architecture FSM_beh of FSMctrl is type states is(S0,S1,S2,S3,S4,S5,S6,S7); signal EA, PE: states; signal clock: std_logic; signal reset: std_logic; begin clock <= CLK; P1: process(clock, reset) begin if reset = '0' then EA <= S0; elsif clock'event and clock = '1' then EA <= PE; end if; end process; P2: process(EA, ENTER, Operacao) begin case EA is when S0 => if Enter = '1' then PE <= S0; else PE <= S1; end if; Enable_1 <= '0'; Enable_2 <= '0'; when S1 => if Enter = '0' then PE <= S1; else PE <= S2; end if; Enable_1 <= '1'; Enable_2 <= '0'; when S2 => Enable_1 <= '0'; Enable_2 <= '0'; if Operacao = "00" then PE <= S3; elsif Operacao = "01" then PE <= S4; elsif Operacao = "10" then PE <= S5; elsif Operacao = "11" then PE <= S6; end if; when S3 => Selecao <= "00"; if Enter = '1' then PE <= S3; else PE <= S7; end if; when S4 => Selecao <= "01"; if Enter = '1' then PE <= S4; else PE <= S7; end if; when S5 => Enable_1 <= '1'; Enable_2 <= '1'; Selecao <= "10"; PE <= S0; when S6 => Enable_1 <= '1'; Enable_2 <= '1'; Selecao <= "11"; PE <= S0; when S7 => Enable_1 <= '0'; Enable_2 <= '1'; PE <= S0; end case; end process; end FSM_beh;
mit
038bd3285bff68ff54d12bfff320e0ba
0.502612
2.526393
false
false
false
false
GSimas/EEL5105
AULA7b/Lab7b-estru.vhd
1
1,011
library ieee; use ieee.std_logic_1164.all; entity LAB7b is port ( KEY : in std_logic_vector(3 downto 0); HEX0: out std_logic_vector(6 downto 0); LEDR : out std_logic_vector(9 downto 0) ); end LAB7b; architecture LAB7b_estru of LAB7b is signal QQ, q: std_logic_vector(3 downto 0); signal F: std_logic_vector (3 downto 0); component D_4FF port ( CLK, RST: in std_logic; D: in std_logic_vector(3 downto 0); Q: out std_logic_vector(3 downto 0) ); end component; component decod7seg port ( C: in std_logic_vector(3 downto 0); F: out std_logic_vector(6 downto 0) ); end component; begin -- Inicio da FSM -- QQ(3) <= '0'; QQ(2) <= (not(q(3)) and not(q(2)) and q(1) and q(0)); QQ(1) <= (not(q(3)) and not(q(2))) and (q(1) xor q(0)); QQ(0) <= (not(q(3)) and q(2) and not(q(1))) or (not(q(3)) and not(q(2)) and q(1) and not(q(0))); L0: D_4FF port map (KEY(1), KEY(0), QQ(3 downto 0), q(3 downto 0)); F <= q; -- Fim da FSM – LEDR <= "000000" & F; L1: decod7seg port map (F(3 downto 0), HEX0); end LAB7b_estru;
mit
3452388b173ca072d8305e31d0a0f2d8
0.635282
2.287982
false
false
false
false
fquinto/Wireless_sensor_network
Avnet_UPC/hdl/ilmb_wrapper.vhd
1
3,169
------------------------------------------------------------------------------- -- ilmb_wrapper.vhd ------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; library lmb_v10_v1_00_a; use lmb_v10_v1_00_a.all; entity ilmb_wrapper is port ( LMB_Clk : in std_logic; SYS_Rst : in std_logic; LMB_Rst : out std_logic; M_ABus : in std_logic_vector(0 to 31); M_ReadStrobe : in std_logic; M_WriteStrobe : in std_logic; M_AddrStrobe : in std_logic; M_DBus : in std_logic_vector(0 to 31); M_BE : in std_logic_vector(0 to 3); Sl_DBus : in std_logic_vector(0 to 31); Sl_Ready : in std_logic_vector(0 to 0); LMB_ABus : out std_logic_vector(0 to 31); LMB_ReadStrobe : out std_logic; LMB_WriteStrobe : out std_logic; LMB_AddrStrobe : out std_logic; LMB_ReadDBus : out std_logic_vector(0 to 31); LMB_WriteDBus : out std_logic_vector(0 to 31); LMB_Ready : out std_logic; LMB_BE : out std_logic_vector(0 to 3) ); attribute x_core_info : STRING; attribute x_core_info of ilmb_wrapper : entity is "lmb_v10_v1_00_a"; end ilmb_wrapper; architecture STRUCTURE of ilmb_wrapper is component lmb_v10 is generic ( C_LMB_NUM_SLAVES : integer; C_LMB_AWIDTH : integer; C_LMB_DWIDTH : integer; C_EXT_RESET_HIGH : integer ); port ( LMB_Clk : in std_logic; SYS_Rst : in std_logic; LMB_Rst : out std_logic; M_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1); M_ReadStrobe : in std_logic; M_WriteStrobe : in std_logic; M_AddrStrobe : in std_logic; M_DBus : in std_logic_vector(0 to C_LMB_DWIDTH-1); M_BE : in std_logic_vector(0 to (C_LMB_DWIDTH+7)/8-1); Sl_DBus : in std_logic_vector(0 to (C_LMB_DWIDTH*C_LMB_NUM_SLAVES)-1); Sl_Ready : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1); LMB_ABus : out std_logic_vector(0 to C_LMB_AWIDTH-1); LMB_ReadStrobe : out std_logic; LMB_WriteStrobe : out std_logic; LMB_AddrStrobe : out std_logic; LMB_ReadDBus : out std_logic_vector(0 to C_LMB_DWIDTH-1); LMB_WriteDBus : out std_logic_vector(0 to C_LMB_DWIDTH-1); LMB_Ready : out std_logic; LMB_BE : out std_logic_vector(0 to (C_LMB_DWIDTH+7)/8-1) ); end component; begin ilmb : lmb_v10 generic map ( C_LMB_NUM_SLAVES => 1, C_LMB_AWIDTH => 32, C_LMB_DWIDTH => 32, C_EXT_RESET_HIGH => 1 ) port map ( LMB_Clk => LMB_Clk, SYS_Rst => SYS_Rst, LMB_Rst => LMB_Rst, M_ABus => M_ABus, M_ReadStrobe => M_ReadStrobe, M_WriteStrobe => M_WriteStrobe, M_AddrStrobe => M_AddrStrobe, M_DBus => M_DBus, M_BE => M_BE, Sl_DBus => Sl_DBus, Sl_Ready => Sl_Ready, LMB_ABus => LMB_ABus, LMB_ReadStrobe => LMB_ReadStrobe, LMB_WriteStrobe => LMB_WriteStrobe, LMB_AddrStrobe => LMB_AddrStrobe, LMB_ReadDBus => LMB_ReadDBus, LMB_WriteDBus => LMB_WriteDBus, LMB_Ready => LMB_Ready, LMB_BE => LMB_BE ); end architecture STRUCTURE;
mit
fb032414610df71bff2d79f067caeeca
0.575891
3.181727
false
true
false
false
tghaefli/ADD
ISE/FMC_waj/mcu_pkg.vhd
1
10,904
------------------------------------------------------------------------------- -- Entity: mcu_pkg -- Author: Waj ------------------------------------------------------------------------------- -- Description: -- VHDL package for definition of design parameters and types used throughout -- the MCU. ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; package mcu_pkg is ----------------------------------------------------------------------------- -- tool chain selection (because no suppoprt of 'val attritube in ISE XST) ----------------------------------------------------------------------------- constant ISE_TOOL : boolean := true; -- true = ISE XST -- false = other synthesizer (e.g. Vivado) -- system clock frequency in Hz constant CF : natural := 50_000_000; -- 50 MHz ----------------------------------------------------------------------------- -- Helper functions (prototypes) ----------------------------------------------------------------------------- -- std_logic_vector(to_signed(i,w)) function i2slv(i : integer; w : positive) return std_logic_vector; -- std_logic_vector(to_unsigned(n,w)) function n2slv(n : natural; w : positive) return std_logic_vector; -- form instruction word for NOP instruction function iw_nop return std_logic_vector; ----------------------------------------------------------------------------- -- design parameters: Memory Map & Peripherals ----------------------------------------------------------------------------- -- bus architecture parameters constant DW : natural range 4 to 64 := 16; -- data word width constant AW : natural range 2 to 64 := 10; -- total address width constant AWH : natural range 1 to 64 := 4; -- high address width constant AWL : natural range 1 to 64 := AW-AWH; -- low address width -- memory map type t_bus_slave is (ROM, RAM, GPIO, FMC, TIM, UART); -- list of bus slaves type t_ba is array (t_bus_slave) of std_logic_vector(AW-1 downto 0); constant BA : t_ba := ( -- full base addresses ROM => "0-" & "----" & "----", RAM => "10" & "----" & "----", GPIO => "11" & "00--" & "----", FMC => "11" & "01--" & "----", TIM => "11" & "10--" & "----", UART => "11" & "11--" & "----" ); type t_hba is array (t_bus_slave) of std_logic_vector(AWH-1 downto 0); constant HBA : t_hba := ( -- high base address for decoding ROM => BA(ROM) (AW-1 downto AW-AWH), RAM => BA(RAM) (AW-1 downto AW-AWH), GPIO => BA(GPIO)(AW-1 downto AW-AWH), FMC => BA(FMC) (AW-1 downto AW-AWH), TIM => BA(TIM) (AW-1 downto AW-AWH), UART => BA(UART)(AW-1 downto AW-AWH) ); -- Relative Register Addresses of Peripherals -- GPIO constant c_addr_gpio_data_in : std_logic_vector(AWL-1 downto 0) := n2slv( 0, AWL); constant c_addr_gpio_data_out : std_logic_vector(AWL-1 downto 0) := n2slv( 1, AWL); constant c_addr_gpio_out_enb : std_logic_vector(AWL-1 downto 0) := n2slv( 2, AWL); type t_gpio_addr_sel is (none, gpio_data_in, gpio_data_out, gpio_enb); -- FMC constant FMC_NUM_CHN : natural range 1 to 8 := 8; -- # of FMC channels constant FMC_ROM_AW : natural range 1 to 10 := 10; -- FMC ROM addr width constant FMC_ROM_DW : natural range 1 to 20 := 20; -- FMC ROM data width constant FMC_TON_WW : natural range 1 to 16 := 6; -- FMC duration word width constant FMC_DUR_WW : natural range 1 to 16 := 14; -- FMC tone word width constant FMC_LAST_TONE : unsigned(FMC_DUR_WW-1 downto 0) := (others => '1'); -- last-tone indicator constant c_addr_fmc_chn_enb : std_logic_vector(AWL-1 downto 0) := n2slv( 0, AWL); constant c_addr_fmc_tmp_ctrl : std_logic_vector(AWL-1 downto 0) := n2slv( 1, AWL); type t_fmc_addr_sel is (none, fmc_chn_enb, fmc_tmp_ctrl); -- TIM -- UART ----------------------------------------------------------------------------- -- design parameters: CPU Instructions ----------------------------------------------------------------------------- -- CPU instruction set -- Note: Defining the OPcode in the way shown below, allows assembler-style -- programming with mnemonics rather than machine coding (see rom.vhd). constant OPCW : natural range 1 to DW := 5; -- Opcode word width constant OPAW : natural range 1 to DW := 4; -- ALU operation word width constant IOWW : natural range 1 to DW := 8; -- immediate operand word width type t_instr is (add, sub, andi, ori, xori, slai, srai, mov, ld, st, addil, addih, setil, setih, jmp, bne, bge, blt, bca, bov, nop); -- Instructions targeted at the ALU are defined by means of a sub-type. -- This allows changing the opcode of instructions without having to -- modify the source code of the ALU. subtype t_alu_instr is t_instr range add to mov; type t_opcode is array (t_instr) of std_logic_vector(OPCW-1 downto 0); constant OPC : t_opcode := ( -- OPcode -- ALU operations ------------------------------- add => "00000", -- 0: addition sub => "00001", -- 1: subtraction andi => "00010", -- 2: bit-wise AND ori => "00011", -- 3: bit-wise OR xori => "00100", -- 4: bit-wise XOR slai => "00101", -- 5: shift-left arithmetically srai => "00110", -- 6: shift-right arithmetically mov => "00111", -- 7: move between register -- Immediate Operands --------------------------- addil => "01100", -- 12: add imm. constant low addih => "01101", -- 13: add imm. constant high setil => "01110", -- 14: set imm. constant low setih => "01111", -- 15: set imm. constant high -- Memory load/store ---------------------------- ld => "10000", -- 16: load from memory st => "10001", -- 17: store to memory -- Jump/Branch ---------------------------------- jmp => "11000", -- 24: absolute jump bne => "11001", -- 25: branch if not equal (not Z) bge => "11010", -- 26: branch if greater/equal (not N or Z) blt => "11011", -- 27: branch if less than (N) bca => "11100", -- 28: branch if carry set (C) bov => "11101", -- 29: branch if overflow set (O) -- Others --------------------------------------- nop => "11111" -- 31: no operation ); type t_flags is (Z, N, C, O); -- ALU flags (zero, negative, carry, overflow) type t_flag_arr is array (t_flags) of std_logic; -- register block constant RIDW : natural range 1 to DW := 3; -- register ID word width type t_regid is array(0 to 7) of std_logic_vector(RIDW-1 downto 0); constant reg : t_regid := ("000","001","010","011","100","101","110","111"); type t_regblk is array(0 to 7) of std_logic_vector(DW-1 downto 0); -- CPU address generation type t_pc_mode is (linear, abs_jump, rel_offset); -- addr calcultion modi type t_addr_exc is (no_err, lin_err, rel_err); -- address exceptions ----------------------------------------------------------------------------- -- global types ----------------------------------------------------------------------------- -- Master bus interface ----------------------------------------------------- type t_bus2cpu is record data : std_logic_vector(DW-1 downto 0); end record; type t_cpu2bus is record data : std_logic_vector(DW-1 downto 0); addr : std_logic_vector(AW-1 downto 0); rd_enb : std_logic; wr_enb : std_logic; end record; -- Read-only slave bus interface ------------------------------------------- type t_bus2ros is record addr : std_logic_vector(AWL-1 downto 0); rd_enb : std_logic; end record; type t_ros2bus is record data : std_logic_vector(DW-1 downto 0); end record; -- read/write slave bus interface ------------------------------------------- type t_bus2rws is record addr : std_logic_vector(AWL-1 downto 0); data : std_logic_vector(DW-1 downto 0); rd_enb : std_logic; -- use of this signal is optional, depending on slave wr_enb : std_logic; end record; type t_rws2bus is record data : std_logic_vector(DW-1 downto 0); end record; ----------------------------------------------------------------------------- -- CPU internal types ----------------------------------------------------------------------------- -- Control Unit / Register Block interface ---------------------------------- type t_ctr2reg is record src1 : std_logic_vector(RIDW-1 downto 0); src2 : std_logic_vector(RIDW-1 downto 0); dest : std_logic_vector(RIDW-1 downto 0); enb_res : std_logic; data : std_logic_vector(DW-1 downto 0); enb_data : std_logic; end record; type t_reg2ctr is record data : std_logic_vector(DW-1 downto 0); addr : std_logic_vector(AW-1 downto 0); end record; -- Control Unit / Program Counter interface -------------------------------- type t_ctr2prc is record enb : std_logic; mode : t_pc_mode; addr : std_logic_vector(AW-1 downto 0); end record; type t_prc2ctr is record pc : std_logic_vector(AW-1 downto 0); exc : t_addr_exc; end record; -- Control Unit / ALU interface --------------------------------------------- type t_ctr2alu is record op : std_logic_vector(OPAW-1 downto 0); -- operation imm : std_logic_vector(IOWW-1 downto 0); -- immediate operand enb : std_logic; -- enable flag update end record; type t_alu2ctr is record flag : t_flag_arr; end record; end package mcu_pkg; package body mcu_pkg is ----------------------------------------------------------------------------- -- Function Implementations ----------------------------------------------------------------------------- function i2slv(i : integer;w : positive) return std_logic_vector is begin return std_logic_vector(to_signed(i,w)); end function i2slv; function n2slv(n : natural;w : positive) return std_logic_vector is begin return std_logic_vector(to_unsigned(n,w)); end function n2slv; function iw_nop return std_logic_vector is variable v : std_logic_vector(DW-1 downto 0); begin for k in DW-1 downto DW-OPCW loop v(k) := OPC(nop)(k-DW+OPCW); end loop; for k in DW-OPCW-1 downto 0 loop v(k) := '0'; end loop; return v; end function iw_nop; end package body mcu_pkg;
gpl-3.0
2837eaafbdd8dac07285e654ffe59c73
0.493947
4.022132
false
false
false
false
GSimas/EEL5105
Multiplicador_Quartus/contador4.vhd
1
538
library ieee; use ieee.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity contador4 is port ( clk : in std_logic; clr : in std_logic; en : in std_logic; N : out std_logic_vector(3 downto 0) ); end entity; architecture rtlcontador4 of contador4 is signal NN : std_logic_vector(3 downto 0); begin process(clk,clr) begin if (clr = '1') then NN <= "0000"; elsif rising_edge(clk) then if (en = '1') then NN <= NN + '1'; end if; end if; end process; N <= NN; end rtlcontador4;
mit
2866f053371a789e7ad95e5185a94984
0.618959
2.62439
false
false
false
false
fquinto/Wireless_sensor_network
Avnet_UPC/hdl/lmb_bram_wrapper.vhd
1
2,862
------------------------------------------------------------------------------- -- lmb_bram_wrapper.vhd ------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; library lmb_bram_elaborate_v1_00_a; use lmb_bram_elaborate_v1_00_a.all; entity lmb_bram_wrapper is port ( BRAM_Rst_A : in std_logic; BRAM_Clk_A : in std_logic; BRAM_EN_A : in std_logic; BRAM_WEN_A : in std_logic_vector(0 to 3); BRAM_Addr_A : in std_logic_vector(0 to 31); BRAM_Din_A : out std_logic_vector(0 to 31); BRAM_Dout_A : in std_logic_vector(0 to 31); BRAM_Rst_B : in std_logic; BRAM_Clk_B : in std_logic; BRAM_EN_B : in std_logic; BRAM_WEN_B : in std_logic_vector(0 to 3); BRAM_Addr_B : in std_logic_vector(0 to 31); BRAM_Din_B : out std_logic_vector(0 to 31); BRAM_Dout_B : in std_logic_vector(0 to 31) ); attribute x_core_info : STRING; attribute keep_hierarchy : STRING; attribute x_core_info of lmb_bram_wrapper : entity is "lmb_bram_elaborate_v1_00_a"; attribute keep_hierarchy of lmb_bram_wrapper : entity is "yes"; end lmb_bram_wrapper; architecture STRUCTURE of lmb_bram_wrapper is component lmb_bram_elaborate is generic ( C_MEMSIZE : integer; C_PORT_DWIDTH : integer; C_PORT_AWIDTH : integer; C_NUM_WE : integer; C_FAMILY : string ); port ( BRAM_Rst_A : in std_logic; BRAM_Clk_A : in std_logic; BRAM_EN_A : in std_logic; BRAM_WEN_A : in std_logic_vector(0 to C_NUM_WE-1); BRAM_Addr_A : in std_logic_vector(0 to C_PORT_AWIDTH-1); BRAM_Din_A : out std_logic_vector(0 to C_PORT_DWIDTH-1); BRAM_Dout_A : in std_logic_vector(0 to C_PORT_DWIDTH-1); BRAM_Rst_B : in std_logic; BRAM_Clk_B : in std_logic; BRAM_EN_B : in std_logic; BRAM_WEN_B : in std_logic_vector(0 to C_NUM_WE-1); BRAM_Addr_B : in std_logic_vector(0 to C_PORT_AWIDTH-1); BRAM_Din_B : out std_logic_vector(0 to C_PORT_DWIDTH-1); BRAM_Dout_B : in std_logic_vector(0 to C_PORT_DWIDTH-1) ); end component; begin lmb_bram : lmb_bram_elaborate generic map ( C_MEMSIZE => 16#8000#, C_PORT_DWIDTH => 32, C_PORT_AWIDTH => 32, C_NUM_WE => 4, C_FAMILY => "spartan3a" ) port map ( BRAM_Rst_A => BRAM_Rst_A, BRAM_Clk_A => BRAM_Clk_A, BRAM_EN_A => BRAM_EN_A, BRAM_WEN_A => BRAM_WEN_A, BRAM_Addr_A => BRAM_Addr_A, BRAM_Din_A => BRAM_Din_A, BRAM_Dout_A => BRAM_Dout_A, BRAM_Rst_B => BRAM_Rst_B, BRAM_Clk_B => BRAM_Clk_B, BRAM_EN_B => BRAM_EN_B, BRAM_WEN_B => BRAM_WEN_B, BRAM_Addr_B => BRAM_Addr_B, BRAM_Din_B => BRAM_Din_B, BRAM_Dout_B => BRAM_Dout_B ); end architecture STRUCTURE;
mit
6a457ff9946d60aa464af078612b325b
0.569532
2.938398
false
false
false
false
GSimas/EEL5105
PROJETO-EEL5105/Projeto/Conta_des.vhd
1
763
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; -- Contador descendente 99 -> 0 entity Conta_des is port( EN_TIME, CLK, RST: in std_logic; CNT_OUT: out std_logic_vector(9 downto 0) ); end Conta_des; --Definicao de arquitetura architecture bhv of Conta_des is signal contador1, contador2: std_logic_vector(4 downto 0); begin process(CLK, RST, EN_TIME) begin if RST = '0' then contador1 <= "01001"; contador2 <= "01001"; elsif rising_edge(CLK) and EN_TIME = '1' then if contador2 <= "00000" then contador2 <= "01001"; contador1 <= contador1 - '1'; else contador2 <= contador2 - '1'; end if; end if; end process; CNT_OUT <= contador1 & contador2; end bhv;
mit
39fca0a0bb577ef74561d8cf2d31db18
0.635649
2.945946
false
false
false
false
GSimas/EEL5105
Eletr-Digital/Relatório4/Controle de Motor de Passo/divisor5.vhd
1
4,568
-- megafunction wizard: %LPM_COUNTER% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: lpm_counter -- ============================================================ -- File Name: divisor5.vhd -- Megafunction Name(s): -- lpm_counter -- -- Simulation Library Files(s): -- lpm -- ============================================================ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- -- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition -- ************************************************************ --Copyright (C) 1991-2010 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject --to the terms and conditions of the Altera Program License --Subscription Agreement, Altera MegaCore Function License --Agreement, or other applicable license agreement, including, --without limitation, that your use is for the sole purpose of --programming logic devices manufactured by Altera and sold by --Altera or its authorized distributors. Please refer to the --applicable agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY lpm; USE lpm.all; ENTITY divisor5 IS PORT ( clock : IN STD_LOGIC ; cout : OUT STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (29 DOWNTO 0) ); END divisor5; ARCHITECTURE SYN OF divisor5 IS SIGNAL sub_wire0 : STD_LOGIC ; SIGNAL sub_wire1 : STD_LOGIC_VECTOR (29 DOWNTO 0); COMPONENT lpm_counter GENERIC ( lpm_direction : STRING; lpm_modulus : NATURAL; lpm_port_updown : STRING; lpm_type : STRING; lpm_width : NATURAL ); PORT ( clock : IN STD_LOGIC ; cout : OUT STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (29 DOWNTO 0) ); END COMPONENT; BEGIN cout <= sub_wire0; q <= sub_wire1(29 DOWNTO 0); lpm_counter_component : lpm_counter GENERIC MAP ( lpm_direction => "UP", lpm_modulus => 5000000, lpm_port_updown => "PORT_UNUSED", lpm_type => "LPM_COUNTER", lpm_width => 30 ) PORT MAP ( clock => clock, cout => sub_wire0, q => sub_wire1 ); END SYN; -- ============================================================ -- CNX file retrieval info -- ============================================================ -- Retrieval info: PRIVATE: ACLR NUMERIC "0" -- Retrieval info: PRIVATE: ALOAD NUMERIC "0" -- Retrieval info: PRIVATE: ASET NUMERIC "0" -- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1" -- Retrieval info: PRIVATE: CLK_EN NUMERIC "0" -- Retrieval info: PRIVATE: CNT_EN NUMERIC "0" -- Retrieval info: PRIVATE: CarryIn NUMERIC "0" -- Retrieval info: PRIVATE: CarryOut NUMERIC "1" -- Retrieval info: PRIVATE: Direction NUMERIC "0" -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" -- Retrieval info: PRIVATE: ModulusCounter NUMERIC "1" -- Retrieval info: PRIVATE: ModulusValue NUMERIC "5000000" -- Retrieval info: PRIVATE: SCLR NUMERIC "0" -- Retrieval info: PRIVATE: SLOAD NUMERIC "0" -- Retrieval info: PRIVATE: SSET NUMERIC "0" -- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: nBit NUMERIC "30" -- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP" -- Retrieval info: CONSTANT: LPM_MODULUS NUMERIC "5000000" -- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER" -- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "30" -- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock -- Retrieval info: USED_PORT: cout 0 0 0 0 OUTPUT NODEFVAL cout -- Retrieval info: USED_PORT: q 0 0 30 0 OUTPUT NODEFVAL q[29..0] -- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 -- Retrieval info: CONNECT: q 0 0 30 0 @q 0 0 30 0 -- Retrieval info: CONNECT: cout 0 0 0 0 @cout 0 0 0 0 -- Retrieval info: LIBRARY: lpm lpm.lpm_components.all -- Retrieval info: GEN_FILE: TYPE_NORMAL divisor5.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL divisor5.inc TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL divisor5.cmp TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL divisor5.bsf TRUE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL divisor5_inst.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL divisor5_waveforms.html TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL divisor5_wave*.jpg FALSE -- Retrieval info: LIB_FILE: lpm
mit
eb60a6b781ecc5ec653a18352cf4d6f5
0.656086
3.707792
false
false
false
false
hoglet67/AtomFpga
src/common/AVR8/MemArbAndMux/MemRdMux.vhd
4
1,646
--************************************************************************************************ -- -- Version 0.1 -- Designed by Ruslan Lepetenok -- Modified 24.07.2005 --************************************************************************************************ library IEEE; use IEEE.std_logic_1164.all; use WORK.MemAccessCtrlPack.all; entity MemRdMux is port( slv_outs : in SlavesOutBus_Type; ram_sel : in std_logic; -- Data RAM selection(optional input) ram_dout : in std_logic_vector(7 downto 0); -- Data memory output dout : out std_logic_vector(7 downto 0) -- Data output ); end MemRdMux; architecture RTL of MemRdMux is constant c_zero_vect : std_logic_vector(CNumOfSlaves-1 downto 0) := (others => '0'); signal slv_data_out : std_logic_vector(dout'range); --CUseRAMSel begin SlvSelOutMux:process(slv_outs) -- Combinatorial begin slv_data_out <= (others => '0'); for i in 0 to CNumOfSlaves-1 loop if(slv_outs(i).out_en='1') then slv_data_out <= slv_outs(i).dout; exit; end if; end loop; end process; RamSelIsNotUsed:if not CUseRAMSel generate OutMux:process(slv_outs,slv_data_out,ram_dout) -- Combinatorial begin dout <= ram_dout; for i in 0 to CNumOfSlaves-1 loop if(slv_outs(i).out_en='1') then dout <= slv_data_out; exit; end if; end loop; end process; end generate; RamSelIsUsed:if CUseRAMSel generate dout <= ram_dout when (ram_sel='1') else slv_data_out; end generate; end RTL;
apache-2.0
c84c07f1c1430c4d43c6cf6bbba99448
0.532807
3.443515
false
false
false
false
hoglet67/AtomFpga
src/common/ICET65/BusMonCore.vhd
1
23,012
-------------------------------------------------------------------------------- -- Copyright (c) 2015 David Banks -- -------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / -- \ \ \/ -- \ \ -- / / Filename : BusMonCore.vhd -- /___/ /\ Timestamp : 30/05/2015 -- \ \ / \ -- \___\/\___\ -- --Design Name: AtomBusMon --Device: XC3S250E library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; entity BusMonCore is generic ( num_comparators : integer := 8; reg_width : integer := 46; fifo_width : integer := 72; avr_data_mem_size : integer := 1024 * 2; -- 2K is the mimimum avr_prog_mem_size : integer := 1024 * 8; -- Default is 8K, 6809 amd Z80 need 9K filename : string ); port ( clock_avr : in std_logic; busmon_clk : in std_logic; busmon_clken : in std_logic; cpu_clk : in std_logic; cpu_clken : in std_logic; -- CPU Signals Addr : in std_logic_vector(15 downto 0); Data : in std_logic_vector(7 downto 0); Rd_n : in std_logic; Wr_n : in std_logic; RdIO_n : in std_logic; WrIO_n : in std_logic; Sync : in std_logic; Rdy : out std_logic; nRSTin : in std_logic; nRSTout : out std_logic; CountCycle : in std_logic; -- CPU Registers -- unused in pure bus monitor mode Regs : in std_logic_vector(255 downto 0); -- CPI Specific data PdcData : in std_logic_vector(7 downto 0) := x"00"; -- CPU Memory Read/Write -- unused in pure bus monitor mode RdMemOut : out std_logic; WrMemOut : out std_logic; RdIOOut : out std_logic; WrIOOut : out std_logic; ExecOut : out std_logic; AddrOut : out std_logic_vector(15 downto 0); DataOut : out std_logic_vector(7 downto 0); DataIn : in std_logic_vector(7 downto 0); Done : in std_logic; -- Special outputs (function is CPU specific) Special : out std_logic_vector(1 downto 0); -- Single Step interface SS_Single : out std_logic; SS_Step : out std_logic; -- External trigger inputs trig : in std_logic_vector(1 downto 0); -- AVR Serial Port avr_RxD : in std_logic; avr_TxD : out std_logic; -- Switches sw_reset_cpu : in std_logic; sw_reset_avr : in std_logic; -- LEDs led_bkpt : out std_logic; led_trig0 : out std_logic; led_trig1 : out std_logic ); end BusMonCore; architecture behavioral of BusMonCore is signal cpu_reset_n : std_logic; signal nrst_avr : std_logic; signal nrst1 : std_logic; signal nrst2 : std_logic; signal nrst3 : std_logic; -- debounce time is 2^17 / 16MHz = 8.192ms signal nrst_counter : unsigned(17 downto 0); signal mux : std_logic_vector(7 downto 0); signal muxsel : std_logic_vector(5 downto 0); signal cmd_edge : std_logic; signal cmd_edge1 : std_logic; signal cmd_edge2 : std_logic; signal cmd_ack : std_logic; signal cmd_ack1 : std_logic; signal cmd_ack2 : std_logic; signal cmd : std_logic_vector(4 downto 0); signal addr_sync : std_logic_vector(15 downto 0); signal addr_inst : std_logic_vector(15 downto 0); signal Addr1 : std_logic_vector(15 downto 0); signal Data1 : std_logic_vector(7 downto 0); signal cycleCount : std_logic_vector(23 downto 0); signal cycleCount_inst : std_logic_vector(23 downto 0); signal single : std_logic; signal reset : std_logic; signal step : std_logic; signal bw_status : std_logic_vector(3 downto 0); signal bw_status1 : std_logic_vector(3 downto 0); signal auto_inc : std_logic; signal brkpt_reg : std_logic_vector(num_comparators * reg_width - 1 downto 0); signal brkpt_enable : std_logic; signal brkpt_active : std_logic; signal brkpt_active1 : std_logic; signal watch_active : std_logic; signal fifo_din : std_logic_vector(fifo_width - 1 downto 0); signal fifo_dout : std_logic_vector(fifo_width - 1 downto 0); signal fifo_empty : std_logic; signal fifo_full : std_logic; signal fifo_not_empty1 : std_logic; signal fifo_not_empty2 : std_logic; signal fifo_rd : std_logic; signal fifo_rd_en : std_logic; signal fifo_wr : std_logic; signal fifo_wr_en : std_logic; signal fifo_rst : std_logic; signal memory_rd : std_logic; signal memory_wr : std_logic; signal io_rd : std_logic; signal io_wr : std_logic; signal exec : std_logic; signal addr_dout_reg : std_logic_vector(23 downto 0); signal din_reg : std_logic_vector(7 downto 0); signal Rdy_int : std_logic; signal unused_d6 : std_logic; signal unused_d7 : std_logic; signal last_done : std_logic; signal cmd_done : std_logic; signal reset_counter : std_logic_vector(9 downto 0); signal dropped_counter : std_logic_vector(3 downto 0); begin Inst_AVR8: entity work.AVR8 generic map( CDATAMEMSIZE => avr_data_mem_size, CPROGMEMSIZE => avr_prog_mem_size, FILENAME => filename, CImplPORTA => TRUE, CImplPORTB => TRUE, CImplPORTD => TRUE, CImplPORTE => TRUE, CImplUART => TRUE ) port map( clk16M => clock_avr, nrst => nrst_avr, portain => PdcData, portaout => open, -- Command Port portbin(0) => '0', portbin(1) => '0', portbin(2) => '0', portbin(3) => '0', portbin(4) => '0', portbin(5) => '0', portbin(6) => '0', portbin(7) => '0', portbout(0) => cmd(0), portbout(1) => cmd(1), portbout(2) => cmd(2), portbout(3) => cmd(3), portbout(4) => cmd(4), portbout(5) => cmd_edge, portbout(6) => Special(0), portbout(7) => Special(1), -- Status Port portdin(0) => '0', portdin(1) => '0', portdin(2) => '0', portdin(3) => '0', portdin(4) => '0', portdin(5) => '0', portdin(6) => cmd_ack2, portdin(7) => fifo_not_empty2, portdout(0) => muxsel(0), portdout(1) => muxsel(1), portdout(2) => muxsel(2), portdout(3) => muxsel(3), portdout(4) => muxsel(4), portdout(5) => muxsel(5), portdout(6) => unused_d6, portdout(7) => unused_d7, -- Mux Port portein => mux, porteout => open, spi_mosio => open, spi_scko => open, spi_misoi => '0', rxd => avr_RxD, txd => avr_TxD ); -- Syncronise signals crossing busmon_clk / clock_avr boundary process (clock_avr) begin if rising_edge(clock_avr) then fifo_not_empty1 <= not fifo_empty; fifo_not_empty2 <= fifo_not_empty1; cmd_ack1 <= cmd_ack; cmd_ack2 <= cmd_ack1; end if; end process; WatchEvents_inst : entity work.WatchEvents port map( clk => busmon_clk, srst => fifo_rst, din => fifo_din, wr_en => fifo_wr_en, rd_en => fifo_rd_en, dout => fifo_dout, full => fifo_full, empty => fifo_empty ); fifo_wr_en <= fifo_wr and busmon_clken; fifo_rd_en <= fifo_rd and busmon_clken; -- The fifo is writen the cycle after the break point -- Addr1 is the address bus delayed by 1 cycle -- DataWr1 is the data being written delayed by 1 cycle -- DataRd is the data being read, that is already one cycle late -- bw_state1(1) is 1 for writes, and 0 for reads fifo_din <= cycleCount_inst & dropped_counter & bw_status1 & Data1 & Addr1 & addr_inst; -- Implement a 4-bit saturating counter of the number of dropped events process (busmon_clk) begin if rising_edge(busmon_clk) then if busmon_clken = '1' then if fifo_rst = '1' then dropped_counter <= x"0"; elsif fifo_wr_en = '1' then if fifo_full = '1' then if dropped_counter /= x"F" then dropped_counter <= dropped_counter + 1; end if; else dropped_counter <= x"0"; end if; end if; end if; end if; end process; led_trig0 <= trig(0); led_trig1 <= trig(1); led_bkpt <= brkpt_active; nrst_avr <= not sw_reset_avr; mux <= addr_inst(7 downto 0) when muxsel = 0 else addr_inst(15 downto 8) when muxsel = 1 else din_reg when muxsel = 2 else cycleCount(23 downto 16) when muxsel = 3 else cycleCount(7 downto 0) when muxsel = 4 else cycleCount(15 downto 8) when muxsel = 5 else fifo_dout(7 downto 0) when muxsel = 6 else fifo_dout(15 downto 8) when muxsel = 7 else fifo_dout(23 downto 16) when muxsel = 8 else fifo_dout(31 downto 24) when muxsel = 9 else fifo_dout(39 downto 32) when muxsel = 10 else fifo_dout(47 downto 40) when muxsel = 11 else fifo_dout(55 downto 48) when muxsel = 12 else fifo_dout(63 downto 56) when muxsel = 13 else fifo_dout(71 downto 64) when muxsel = 14 else Regs(8 * to_integer(unsigned(muxsel(4 downto 0))) + 7 downto 8 * to_integer(unsigned(muxsel(4 downto 0)))); -- Combinatorial set of comparators to decode breakpoint/watch addresses brkpt_active_process: process (brkpt_reg, brkpt_enable, Addr, Sync, Rd_n, Wr_n, RdIO_n, WrIO_n, trig) variable i : integer; variable reg_addr : std_logic_vector(15 downto 0); variable reg_mask : std_logic_vector(15 downto 0); variable reg_mode_bmr : std_logic; variable reg_mode_bmw : std_logic; variable reg_mode_bir : std_logic; variable reg_mode_biw : std_logic; variable reg_mode_bx : std_logic; variable reg_mode_wmr : std_logic; variable reg_mode_wmw : std_logic; variable reg_mode_wir : std_logic; variable reg_mode_wiw : std_logic; variable reg_mode_wx : std_logic; variable reg_mode_all : std_logic_vector(9 downto 0); variable bactive : std_logic; variable wactive : std_logic; variable status : std_logic_vector(3 downto 0); variable trigval : std_logic; begin bactive := '0'; wactive := '0'; status := (others => '0'); if (brkpt_enable = '1') then for i in 0 to num_comparators - 1 loop reg_addr := brkpt_reg(i * reg_width + 15 downto i * reg_width); reg_mask := brkpt_reg(i * reg_width + 31 downto i * reg_width + 16); reg_mode_bmr := brkpt_reg(i * reg_width + 32); reg_mode_wmr := brkpt_reg(i * reg_width + 33); reg_mode_bmw := brkpt_reg(i * reg_width + 34); reg_mode_wmw := brkpt_reg(i * reg_width + 35); reg_mode_bir := brkpt_reg(i * reg_width + 36); reg_mode_wir := brkpt_reg(i * reg_width + 37); reg_mode_biw := brkpt_reg(i * reg_width + 38); reg_mode_wiw := brkpt_reg(i * reg_width + 39); reg_mode_bx := brkpt_reg(i * reg_width + 40); reg_mode_wx := brkpt_reg(i * reg_width + 41); reg_mode_all := brkpt_reg(i * reg_width + 41 downto i * reg_width + 32); trigval := brkpt_reg(i * reg_width + 42 + to_integer(unsigned(trig))); if (trigval = '1' and ((Addr and reg_mask) = reg_addr or (reg_mode_all = "0000000000"))) then if (Sync = '1') then if (reg_mode_bx = '1') then bactive := '1'; status := "1000"; elsif (reg_mode_wx = '1') then wactive := '1'; status := "1001"; end if; elsif (Rd_n = '0') then if (reg_mode_bmr = '1') then bactive := '1'; status := "0000"; elsif (reg_mode_wmr = '1') then wactive := '1'; status := "0001"; end if; elsif (Wr_n = '0') then if (reg_mode_bmw = '1') then bactive := '1'; status := "0010"; elsif (reg_mode_wmw = '1') then wactive := '1'; status := "0011"; end if; elsif (RdIO_n = '0') then if (reg_mode_bir = '1') then bactive := '1'; status := "0100"; elsif (reg_mode_wir = '1') then wactive := '1'; status := "0101"; end if; elsif (WrIO_n = '0') then if (reg_mode_biw = '1') then bactive := '1'; status := "0110"; elsif (reg_mode_wiw = '1') then wactive := '1'; status := "0111"; end if; end if; end if; end loop; end if; watch_active <= wactive; brkpt_active <= bactive; bw_status <= status; end process; -- CPU Control Commands -- 0000x Enable/Disable single stepping -- 0001x Enable/Disable breakpoints / watches -- 0010x Load breakpoint / watch register -- 0011x Reset CPU -- 01000 Singe Step CPU -- 01001 Read FIFO -- 01010 Reset FIFO -- 01011 Unused -- 0110x Load address/data register -- 0111x Unused -- 10000 Read Memory -- 10001 Read Memory and Auto Inc Address -- 10010 Write Memory -- 10011 Write Memory and Auto Inc Address -- 10100 Read IO -- 10101 Read IO and Auto Inc Address -- 10110 Write IO -- 10111 Write IO and Auto Inc Address -- 11000 Execute 6502 instruction -- 111xx Unused -- 11x1x Unused -- 11xx1 Unused cpuProcess: process (busmon_clk) begin if rising_edge(busmon_clk) then if busmon_clken = '1' then -- Cycle counter, wraps every 16s at 1MHz if (cpu_reset_n = '0') then cycleCount <= (others => '0'); elsif (CountCycle = '1') then cycleCount <= cycleCount + 1; end if; -- Command processing cmd_edge1 <= cmd_edge; cmd_edge2 <= cmd_edge1; fifo_rd <= '0'; fifo_wr <= '0'; fifo_rst <= '0'; memory_rd <= '0'; memory_wr <= '0'; io_rd <= '0'; io_wr <= '0'; exec <= '0'; SS_Step <= '0'; if (cmd_edge2 /= cmd_edge1) then if (cmd(4 downto 1) = "0000") then single <= cmd(0); end if; if (cmd(4 downto 1) = "0001") then brkpt_enable <= cmd(0); end if; if (cmd(4 downto 1) = "0010") then brkpt_reg <= cmd(0) & brkpt_reg(brkpt_reg'length - 1 downto 1); end if; if (cmd(4 downto 1) = "0110") then addr_dout_reg <= cmd(0) & addr_dout_reg(addr_dout_reg'length - 1 downto 1); end if; if (cmd(4 downto 1) = "0011") then reset <= cmd(0); end if; if (cmd(4 downto 0) = "01001") then fifo_rd <= '1'; end if; if (cmd(4 downto 0) = "01010") then fifo_rst <= '1'; end if; if (cmd(4 downto 1) = "1000") then memory_rd <= '1'; auto_inc <= cmd(0); end if; if (cmd(4 downto 1) = "1001") then memory_wr <= '1'; auto_inc <= cmd(0); end if; if (cmd(4 downto 1) = "1010") then io_rd <= '1'; auto_inc <= cmd(0); end if; if (cmd(4 downto 1) = "1011") then io_wr <= '1'; auto_inc <= cmd(0); end if; if (cmd(4 downto 0) = "11000") then exec <= '1'; end if; -- Acknowlege certain commands immediately if cmd(4) = '0' then cmd_ack <= not cmd_ack; end if; end if; if cmd_done = '1' then -- Acknowlege memory access commands when thet complete cmd_ack <= not cmd_ack; -- Auto increment the memory address reg the cycle after a rd/wr if auto_inc = '1' then addr_dout_reg(23 downto 8) <= addr_dout_reg(23 downto 8) + 1; end if; end if; -- Single Stepping if (brkpt_active = '1') then single <= '1'; end if; if ((single = '0') or (cmd_edge2 /= cmd_edge1 and cmd = "01000")) then Rdy_int <= (not brkpt_active); SS_Step <= (not brkpt_active); else Rdy_int <= (not Sync); end if; -- Latch instruction address for the whole cycle if (Sync = '1') then addr_inst <= Addr; cycleCount_inst <= cycleCount; end if; -- Breakpoints and Watches written to the FIFO brkpt_active1 <= brkpt_active; bw_status1 <= bw_status; if watch_active = '1' or (brkpt_active = '1' and brkpt_active1 = '0') then fifo_wr <= '1'; Addr1 <= Addr; end if; end if; end if; end process; dataProcess: process (cpu_clk) begin if rising_edge(cpu_clk) then if cpu_clken = '1' then -- Latch the data bus for use in watches Data1 <= Data; -- Latch memory read in response to a read command if (Done = '1') then din_reg <= DataIn; end if; -- Delay the increnting of the address by one cycle last_done <= Done; if Done = '1' and last_done = '0' then cmd_done <= '1'; else cmd_done <= '0'; end if; end if; end if; end process; Rdy <= Rdy_int; RdMemOut <= memory_rd; WrMemOut <= memory_wr; RdIOOut <= io_rd; WrIOOut <= io_wr; AddrOut <= addr_dout_reg(23 downto 8); DataOut <= addr_dout_reg(7 downto 0); SS_Single <= single; ExecOut <= exec; -- Reset Logic -- Generate a short (~1ms @ 1MHz) power up reset pulse -- -- This is in case FPGA configuration takes longer than -- the length of the host system reset pulse. -- -- Some 6502 cores (particularly the AlanD core) needs -- reset to be asserted to start. -- Debounce nRSTin using clock_avr as this is always 16MHz -- nrst1 is the possibly glitchy input -- nrst2 is the filtered output process(clock_avr) begin if rising_edge(clock_avr) then -- Syncronise nRSTin nrst1 <= nRSTin and (not sw_reset_cpu); -- De-glitch NRST if nrst1 = '0' then nrst_counter <= to_unsigned(0, nrst_counter'length); nrst2 <= '0'; elsif nrst_counter(nrst_counter'high) = '0' then nrst_counter <= nrst_counter + 1; else nrst2 <= '1'; end if; end if; end process; process(cpu_clk) begin if rising_edge(cpu_clk) then if cpu_clken = '1' then if reset_counter(reset_counter'high) = '0' then reset_counter <= reset_counter + 1; end if; nrst3 <= nrst2 and reset_counter(reset_counter'high) and (not reset); cpu_reset_n <= nrst3; end if; end if; end process; nRSTout <= cpu_reset_n; end behavioral;
apache-2.0
924f10da58fe59910ce5eea8399f77fb
0.44442
4.13216
false
false
false
false
hoglet67/AtomFpga
src/common/SPI/spi.vhd
2
4,101
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_ARITH.all; use IEEE.STD_LOGIC_UNSIGNED.all; -- 0x0 read data -- 0x0 write data -- 0x01 write dummy 0xff -- 0x02 write dummy 0x00 -- 0x03 set cs -- 0x04 clr cs entity SPI_Port is port ( nRST : in std_logic; clk : in std_logic; enable : in std_logic; nwe : in std_logic; address : in std_logic_vector (2 downto 0); datain : in std_logic_vector (7 downto 0); dataout : out std_logic_vector (7 downto 0); MISO : in std_logic; MOSI : out std_logic; NSS : out std_logic; SPICLK : out std_logic ); end SPI_Port; architecture Behavioral of SPI_Port is type STATE_TYPE is (init, s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17); signal state : STATE_TYPE; signal SerialOut : std_logic_vector(7 downto 0); signal SerialIn : std_logic_vector(7 downto 0); signal count : std_logic_vector(12 downto 0); begin -------------------------------------------------------------- -- Process Copies SPI port word to appropriate ctrl register -------------------------------------------------------------- SPIport : process (nRST, clk, SerialOut, SerialIn) begin if nRST = '0' then state <= init; NSS <= '1'; MOSI <= '1'; SPICLK <= '0'; SerialOut <= (others => '1'); count <= (others => '0'); elsif rising_edge(clk) then if (state = init) then if (count = 5663) then -- 88 * 64 + 31 state <= s0; SPICLK <= '0'; NSS <= '0'; else SPICLK <= count(5); -- 250 KHz count <= count + 1; end if; elsif enable = '1' and nwe = '0' then if address = "010" then SerialOut <= (others => '0'); state <= s1; elsif address = "001" then SerialOut <= (others => '1'); state <= s1; elsif address = "000" then SerialOut <= datain; state <= s1; elsif address = "011" then NSS <= '1'; elsif address = "100" then NSS <= '0'; elsif address = "101" then SPICLK <= '1'; elsif address = "110" then SPICLK <= '0'; elsif address = "111" then state <= init; NSS <= '1'; MOSI <= '1'; SPICLK <= '0'; SerialOut <= (others => '1'); count <= (others => '0'); end if; else case state is -- Address state machine when s1 => state <= s2; SPICLK <= '0'; MOSI <= SerialOut(7); when s2 => state <= s3; SPICLK <= '1'; when s3 => state <= s4; SPICLK <= '0'; MOSI <= SerialOut(6); SerialIn(7) <= MISO; --SerialIn when s4 => state <= s5; SPICLK <= '1'; when s5 => state <= s6; SPICLK <= '0'; MOSI <= SerialOut(5); SerialIn(6) <= MISO; when s6 => state <= s7; SPICLK <= '1'; when s7 => state <= s8; SPICLK <= '0'; MOSI <= SerialOut(4); SerialIn(5) <= MISO; when s8 => state <= s9; SPICLK <= '1'; when s9 => state <= s10; SPICLK <= '0'; MOSI <= SerialOut(3); SerialIn(4) <= MISO; when s10 => state <= s11; SPICLK <= '1'; when s11 => state <= s12; SPICLK <= '0'; MOSI <= SerialOut(2); SerialIn(3) <= MISO; when s12 => state <= s13; SPICLK <= '1'; when s13 => state <= s14; SPICLK <= '0'; MOSI <= SerialOut(1); SerialIn(2) <= MISO; when s14 => state <= s15; SPICLK <= '1'; when s15 => state <= s16; SPICLK <= '0'; MOSI <= SerialOut(0); SerialIn(1) <= MISO; when s16 => state <= s17; SPICLK <= '1'; when s17 => state <= s0; SPICLK <= '0'; MOSI <= '0'; SerialIn(0) <= MISO; when others => state <= s0; -- retrun to idle state end case; end if; dataout <= SerialIn; end if; end process; end Behavioral;
apache-2.0
410eb305f4bf04558b7425e1c230f013
0.46891
3.406146
false
false
false
false
fquinto/Wireless_sensor_network
Avnet_UPC/hdl/flash_2mx16_wrapper.vhd
1
18,464
------------------------------------------------------------------------------- -- flash_2mx16_wrapper.vhd ------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; library xps_mch_emc_v3_01_a; use xps_mch_emc_v3_01_a.all; entity flash_2mx16_wrapper is port ( MCH_SPLB_Clk : in std_logic; RdClk : in std_logic; MCH_SPLB_Rst : in std_logic; MCH0_Access_Control : in std_logic; MCH0_Access_Data : in std_logic_vector(0 to 31); MCH0_Access_Write : in std_logic; MCH0_Access_Full : out std_logic; MCH0_ReadData_Control : out std_logic; MCH0_ReadData_Data : out std_logic_vector(0 to 31); MCH0_ReadData_Read : in std_logic; MCH0_ReadData_Exists : out std_logic; MCH1_Access_Control : in std_logic; MCH1_Access_Data : in std_logic_vector(0 to 31); MCH1_Access_Write : in std_logic; MCH1_Access_Full : out std_logic; MCH1_ReadData_Control : out std_logic; MCH1_ReadData_Data : out std_logic_vector(0 to 31); MCH1_ReadData_Read : in std_logic; MCH1_ReadData_Exists : out std_logic; MCH2_Access_Control : in std_logic; MCH2_Access_Data : in std_logic_vector(0 to 31); MCH2_Access_Write : in std_logic; MCH2_Access_Full : out std_logic; MCH2_ReadData_Control : out std_logic; MCH2_ReadData_Data : out std_logic_vector(0 to 31); MCH2_ReadData_Read : in std_logic; MCH2_ReadData_Exists : out std_logic; MCH3_Access_Control : in std_logic; MCH3_Access_Data : in std_logic_vector(0 to 31); MCH3_Access_Write : in std_logic; MCH3_Access_Full : out std_logic; MCH3_ReadData_Control : out std_logic; MCH3_ReadData_Data : out std_logic_vector(0 to 31); MCH3_ReadData_Read : in std_logic; MCH3_ReadData_Exists : out std_logic; PLB_ABus : in std_logic_vector(0 to 31); PLB_UABus : in std_logic_vector(0 to 31); PLB_PAValid : in std_logic; PLB_SAValid : in std_logic; PLB_rdPrim : in std_logic; PLB_wrPrim : in std_logic; PLB_masterID : in std_logic_vector(0 to 0); PLB_abort : in std_logic; PLB_busLock : in std_logic; PLB_RNW : in std_logic; PLB_BE : in std_logic_vector(0 to 3); PLB_MSize : in std_logic_vector(0 to 1); PLB_size : in std_logic_vector(0 to 3); PLB_type : in std_logic_vector(0 to 2); PLB_lockErr : in std_logic; PLB_wrDBus : in std_logic_vector(0 to 31); PLB_wrBurst : in std_logic; PLB_rdBurst : in std_logic; PLB_wrPendReq : in std_logic; PLB_rdPendReq : in std_logic; PLB_wrPendPri : in std_logic_vector(0 to 1); PLB_rdPendPri : in std_logic_vector(0 to 1); PLB_reqPri : in std_logic_vector(0 to 1); PLB_TAttribute : in std_logic_vector(0 to 15); Sl_addrAck : out std_logic; Sl_SSize : out std_logic_vector(0 to 1); Sl_wait : out std_logic; Sl_rearbitrate : out std_logic; Sl_wrDAck : out std_logic; Sl_wrComp : out std_logic; Sl_wrBTerm : out std_logic; Sl_rdDBus : out std_logic_vector(0 to 31); Sl_rdWdAddr : out std_logic_vector(0 to 3); Sl_rdDAck : out std_logic; Sl_rdComp : out std_logic; Sl_rdBTerm : out std_logic; Sl_MBusy : out std_logic_vector(0 to 1); Sl_MWrErr : out std_logic_vector(0 to 1); Sl_MRdErr : out std_logic_vector(0 to 1); Sl_MIRQ : out std_logic_vector(0 to 1); Mem_DQ_I : in std_logic_vector(0 to 15); Mem_DQ_O : out std_logic_vector(0 to 15); Mem_DQ_T : out std_logic_vector(0 to 15); Mem_A : out std_logic_vector(0 to 31); Mem_RPN : out std_logic; Mem_CEN : out std_logic_vector(0 to 0); Mem_OEN : out std_logic_vector(0 to 0); Mem_WEN : out std_logic; Mem_QWEN : out std_logic_vector(0 to 1); Mem_BEN : out std_logic_vector(0 to 1); Mem_CE : out std_logic_vector(0 to 0); Mem_ADV_LDN : out std_logic; Mem_LBON : out std_logic; Mem_CKEN : out std_logic; Mem_RNW : out std_logic ); attribute x_core_info : STRING; attribute x_core_info of flash_2mx16_wrapper : entity is "xps_mch_emc_v3_01_a"; end flash_2mx16_wrapper; architecture STRUCTURE of flash_2mx16_wrapper is component xps_mch_emc is generic ( C_FAMILY : STRING; C_NUM_BANKS_MEM : INTEGER; C_NUM_CHANNELS : INTEGER; C_PRIORITY_MODE : INTEGER; C_INCLUDE_PLB_IPIF : INTEGER; C_INCLUDE_WRBUF : INTEGER; C_SPLB_MID_WIDTH : INTEGER; C_SPLB_NUM_MASTERS : INTEGER; C_SPLB_P2P : INTEGER; C_SPLB_DWIDTH : INTEGER; C_MCH_SPLB_AWIDTH : INTEGER; C_SPLB_SMALLEST_MASTER : INTEGER; C_MCH_NATIVE_DWIDTH : INTEGER; C_MCH_SPLB_CLK_PERIOD_PS : INTEGER; C_MEM0_BASEADDR : std_logic_vector; C_MEM0_HIGHADDR : std_logic_vector; C_MEM1_BASEADDR : std_logic_vector; C_MEM1_HIGHADDR : std_logic_vector; C_MEM2_BASEADDR : std_logic_vector; C_MEM2_HIGHADDR : std_logic_vector; C_MEM3_BASEADDR : std_logic_vector; C_MEM3_HIGHADDR : std_logic_vector; C_PAGEMODE_FLASH_0 : INTEGER; C_PAGEMODE_FLASH_1 : INTEGER; C_PAGEMODE_FLASH_2 : INTEGER; C_PAGEMODE_FLASH_3 : INTEGER; C_INCLUDE_NEGEDGE_IOREGS : INTEGER; C_MEM0_WIDTH : INTEGER; C_MEM1_WIDTH : INTEGER; C_MEM2_WIDTH : INTEGER; C_MEM3_WIDTH : INTEGER; C_MAX_MEM_WIDTH : INTEGER; C_INCLUDE_DATAWIDTH_MATCHING_0 : INTEGER; C_INCLUDE_DATAWIDTH_MATCHING_1 : INTEGER; C_INCLUDE_DATAWIDTH_MATCHING_2 : INTEGER; C_INCLUDE_DATAWIDTH_MATCHING_3 : INTEGER; C_SYNCH_MEM_0 : INTEGER; C_SYNCH_PIPEDELAY_0 : INTEGER; C_TCEDV_PS_MEM_0 : INTEGER; C_TAVDV_PS_MEM_0 : INTEGER; C_TPACC_PS_FLASH_0 : INTEGER; C_THZCE_PS_MEM_0 : INTEGER; C_THZOE_PS_MEM_0 : INTEGER; C_TWC_PS_MEM_0 : INTEGER; C_TWP_PS_MEM_0 : INTEGER; C_TLZWE_PS_MEM_0 : INTEGER; C_SYNCH_MEM_1 : INTEGER; C_SYNCH_PIPEDELAY_1 : INTEGER; C_TCEDV_PS_MEM_1 : INTEGER; C_TAVDV_PS_MEM_1 : INTEGER; C_TPACC_PS_FLASH_1 : INTEGER; C_THZCE_PS_MEM_1 : INTEGER; C_THZOE_PS_MEM_1 : INTEGER; C_TWC_PS_MEM_1 : INTEGER; C_TWP_PS_MEM_1 : INTEGER; C_TLZWE_PS_MEM_1 : INTEGER; C_SYNCH_MEM_2 : INTEGER; C_SYNCH_PIPEDELAY_2 : INTEGER; C_TCEDV_PS_MEM_2 : INTEGER; C_TAVDV_PS_MEM_2 : INTEGER; C_TPACC_PS_FLASH_2 : INTEGER; C_THZCE_PS_MEM_2 : INTEGER; C_THZOE_PS_MEM_2 : INTEGER; C_TWC_PS_MEM_2 : INTEGER; C_TWP_PS_MEM_2 : INTEGER; C_TLZWE_PS_MEM_2 : INTEGER; C_SYNCH_MEM_3 : INTEGER; C_SYNCH_PIPEDELAY_3 : INTEGER; C_TCEDV_PS_MEM_3 : INTEGER; C_TAVDV_PS_MEM_3 : INTEGER; C_TPACC_PS_FLASH_3 : INTEGER; C_THZCE_PS_MEM_3 : INTEGER; C_THZOE_PS_MEM_3 : INTEGER; C_TWC_PS_MEM_3 : INTEGER; C_TWP_PS_MEM_3 : INTEGER; C_TLZWE_PS_MEM_3 : INTEGER; C_MCH0_PROTOCOL : INTEGER; C_MCH0_ACCESSBUF_DEPTH : INTEGER; C_MCH0_RDDATABUF_DEPTH : INTEGER; C_MCH1_PROTOCOL : INTEGER; C_MCH1_ACCESSBUF_DEPTH : INTEGER; C_MCH1_RDDATABUF_DEPTH : INTEGER; C_MCH2_PROTOCOL : INTEGER; C_MCH2_ACCESSBUF_DEPTH : INTEGER; C_MCH2_RDDATABUF_DEPTH : INTEGER; C_MCH3_PROTOCOL : INTEGER; C_MCH3_ACCESSBUF_DEPTH : INTEGER; C_MCH3_RDDATABUF_DEPTH : INTEGER; C_XCL0_LINESIZE : INTEGER; C_XCL0_WRITEXFER : INTEGER; C_XCL1_LINESIZE : INTEGER; C_XCL1_WRITEXFER : INTEGER; C_XCL2_LINESIZE : INTEGER; C_XCL2_WRITEXFER : INTEGER; C_XCL3_LINESIZE : INTEGER; C_XCL3_WRITEXFER : INTEGER ); port ( MCH_SPLB_Clk : in std_logic; RdClk : in std_logic; MCH_SPLB_Rst : in std_logic; MCH0_Access_Control : in std_logic; MCH0_Access_Data : in std_logic_vector(0 to (C_MCH_NATIVE_DWIDTH-1)); MCH0_Access_Write : in std_logic; MCH0_Access_Full : out std_logic; MCH0_ReadData_Control : out std_logic; MCH0_ReadData_Data : out std_logic_vector(0 to (C_MCH_NATIVE_DWIDTH-1)); MCH0_ReadData_Read : in std_logic; MCH0_ReadData_Exists : out std_logic; MCH1_Access_Control : in std_logic; MCH1_Access_Data : in std_logic_vector(0 to (C_MCH_NATIVE_DWIDTH-1)); MCH1_Access_Write : in std_logic; MCH1_Access_Full : out std_logic; MCH1_ReadData_Control : out std_logic; MCH1_ReadData_Data : out std_logic_vector(0 to (C_MCH_NATIVE_DWIDTH-1)); MCH1_ReadData_Read : in std_logic; MCH1_ReadData_Exists : out std_logic; MCH2_Access_Control : in std_logic; MCH2_Access_Data : in std_logic_vector(0 to (C_MCH_NATIVE_DWIDTH-1)); MCH2_Access_Write : in std_logic; MCH2_Access_Full : out std_logic; MCH2_ReadData_Control : out std_logic; MCH2_ReadData_Data : out std_logic_vector(0 to (C_MCH_NATIVE_DWIDTH-1)); MCH2_ReadData_Read : in std_logic; MCH2_ReadData_Exists : out std_logic; MCH3_Access_Control : in std_logic; MCH3_Access_Data : in std_logic_vector(0 to (C_MCH_NATIVE_DWIDTH-1)); MCH3_Access_Write : in std_logic; MCH3_Access_Full : out std_logic; MCH3_ReadData_Control : out std_logic; MCH3_ReadData_Data : out std_logic_vector(0 to (C_MCH_NATIVE_DWIDTH-1)); MCH3_ReadData_Read : in std_logic; MCH3_ReadData_Exists : out std_logic; PLB_ABus : in std_logic_vector(0 to 31); PLB_UABus : in std_logic_vector(0 to 31); PLB_PAValid : in std_logic; PLB_SAValid : in std_logic; PLB_rdPrim : in std_logic; PLB_wrPrim : in std_logic; PLB_masterID : in std_logic_vector(0 to (C_SPLB_MID_WIDTH-1)); PLB_abort : in std_logic; PLB_busLock : in std_logic; PLB_RNW : in std_logic; PLB_BE : in std_logic_vector(0 to ((C_SPLB_DWIDTH/8)-1)); PLB_MSize : in std_logic_vector(0 to 1); PLB_size : in std_logic_vector(0 to 3); PLB_type : in std_logic_vector(0 to 2); PLB_lockErr : in std_logic; PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_DWIDTH-1)); PLB_wrBurst : in std_logic; PLB_rdBurst : in std_logic; PLB_wrPendReq : in std_logic; PLB_rdPendReq : in std_logic; PLB_wrPendPri : in std_logic_vector(0 to 1); PLB_rdPendPri : in std_logic_vector(0 to 1); PLB_reqPri : in std_logic_vector(0 to 1); PLB_TAttribute : in std_logic_vector(0 to 15); Sl_addrAck : out std_logic; Sl_SSize : out std_logic_vector(0 to 1); Sl_wait : out std_logic; Sl_rearbitrate : out std_logic; Sl_wrDAck : out std_logic; Sl_wrComp : out std_logic; Sl_wrBTerm : out std_logic; Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_DWIDTH-1)); Sl_rdWdAddr : out std_logic_vector(0 to 3); Sl_rdDAck : out std_logic; Sl_rdComp : out std_logic; Sl_rdBTerm : out std_logic; Sl_MBusy : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1)); Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1)); Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1)); Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1)); Mem_DQ_I : in std_logic_vector(0 to (C_MAX_MEM_WIDTH-1)); Mem_DQ_O : out std_logic_vector(0 to (C_MAX_MEM_WIDTH-1)); Mem_DQ_T : out std_logic_vector(0 to (C_MAX_MEM_WIDTH-1)); Mem_A : out std_logic_vector(0 to (C_MCH_SPLB_AWIDTH-1)); Mem_RPN : out std_logic; Mem_CEN : out std_logic_vector(0 to (C_NUM_BANKS_MEM-1)); Mem_OEN : out std_logic_vector(0 to (C_NUM_BANKS_MEM-1)); Mem_WEN : out std_logic; Mem_QWEN : out std_logic_vector(0 to ((C_MAX_MEM_WIDTH/8)-1)); Mem_BEN : out std_logic_vector(0 to ((C_MAX_MEM_WIDTH/8)-1)); Mem_CE : out std_logic_vector(0 to (C_NUM_BANKS_MEM-1)); Mem_ADV_LDN : out std_logic; Mem_LBON : out std_logic; Mem_CKEN : out std_logic; Mem_RNW : out std_logic ); end component; begin FLASH_2Mx16 : xps_mch_emc generic map ( C_FAMILY => "spartan3a", C_NUM_BANKS_MEM => 1, C_NUM_CHANNELS => 1, C_PRIORITY_MODE => 0, C_INCLUDE_PLB_IPIF => 1, C_INCLUDE_WRBUF => 1, C_SPLB_MID_WIDTH => 1, C_SPLB_NUM_MASTERS => 2, C_SPLB_P2P => 0, C_SPLB_DWIDTH => 32, C_MCH_SPLB_AWIDTH => 32, C_SPLB_SMALLEST_MASTER => 32, C_MCH_NATIVE_DWIDTH => 32, C_MCH_SPLB_CLK_PERIOD_PS => 15000, C_MEM0_BASEADDR => X"84c00000", C_MEM0_HIGHADDR => X"84ffffff", C_MEM1_BASEADDR => X"ffffffff", C_MEM1_HIGHADDR => X"00000000", C_MEM2_BASEADDR => X"ffffffff", C_MEM2_HIGHADDR => X"00000000", C_MEM3_BASEADDR => X"ffffffff", C_MEM3_HIGHADDR => X"00000000", C_PAGEMODE_FLASH_0 => 0, C_PAGEMODE_FLASH_1 => 0, C_PAGEMODE_FLASH_2 => 0, C_PAGEMODE_FLASH_3 => 0, C_INCLUDE_NEGEDGE_IOREGS => 0, C_MEM0_WIDTH => 16, C_MEM1_WIDTH => 32, C_MEM2_WIDTH => 32, C_MEM3_WIDTH => 32, C_MAX_MEM_WIDTH => 16, C_INCLUDE_DATAWIDTH_MATCHING_0 => 1, C_INCLUDE_DATAWIDTH_MATCHING_1 => 0, C_INCLUDE_DATAWIDTH_MATCHING_2 => 0, C_INCLUDE_DATAWIDTH_MATCHING_3 => 0, C_SYNCH_MEM_0 => 0, C_SYNCH_PIPEDELAY_0 => 2, C_TCEDV_PS_MEM_0 => 90000, C_TAVDV_PS_MEM_0 => 90000, C_TPACC_PS_FLASH_0 => 25000, C_THZCE_PS_MEM_0 => 20000, C_THZOE_PS_MEM_0 => 20000, C_TWC_PS_MEM_0 => 90000, C_TWP_PS_MEM_0 => 90000, C_TLZWE_PS_MEM_0 => 35000, C_SYNCH_MEM_1 => 0, C_SYNCH_PIPEDELAY_1 => 2, C_TCEDV_PS_MEM_1 => 15000, C_TAVDV_PS_MEM_1 => 15000, C_TPACC_PS_FLASH_1 => 25000, C_THZCE_PS_MEM_1 => 7000, C_THZOE_PS_MEM_1 => 7000, C_TWC_PS_MEM_1 => 15000, C_TWP_PS_MEM_1 => 12000, C_TLZWE_PS_MEM_1 => 0, C_SYNCH_MEM_2 => 0, C_SYNCH_PIPEDELAY_2 => 2, C_TCEDV_PS_MEM_2 => 15000, C_TAVDV_PS_MEM_2 => 15000, C_TPACC_PS_FLASH_2 => 25000, C_THZCE_PS_MEM_2 => 7000, C_THZOE_PS_MEM_2 => 7000, C_TWC_PS_MEM_2 => 15000, C_TWP_PS_MEM_2 => 12000, C_TLZWE_PS_MEM_2 => 0, C_SYNCH_MEM_3 => 0, C_SYNCH_PIPEDELAY_3 => 2, C_TCEDV_PS_MEM_3 => 15000, C_TAVDV_PS_MEM_3 => 15000, C_TPACC_PS_FLASH_3 => 25000, C_THZCE_PS_MEM_3 => 7000, C_THZOE_PS_MEM_3 => 7000, C_TWC_PS_MEM_3 => 15000, C_TWP_PS_MEM_3 => 12000, C_TLZWE_PS_MEM_3 => 0, C_MCH0_PROTOCOL => 0, C_MCH0_ACCESSBUF_DEPTH => 16, C_MCH0_RDDATABUF_DEPTH => 16, C_MCH1_PROTOCOL => 0, C_MCH1_ACCESSBUF_DEPTH => 16, C_MCH1_RDDATABUF_DEPTH => 16, C_MCH2_PROTOCOL => 0, C_MCH2_ACCESSBUF_DEPTH => 16, C_MCH2_RDDATABUF_DEPTH => 16, C_MCH3_PROTOCOL => 0, C_MCH3_ACCESSBUF_DEPTH => 16, C_MCH3_RDDATABUF_DEPTH => 16, C_XCL0_LINESIZE => 4, C_XCL0_WRITEXFER => 1, C_XCL1_LINESIZE => 4, C_XCL1_WRITEXFER => 1, C_XCL2_LINESIZE => 4, C_XCL2_WRITEXFER => 1, C_XCL3_LINESIZE => 4, C_XCL3_WRITEXFER => 1 ) port map ( MCH_SPLB_Clk => MCH_SPLB_Clk, RdClk => RdClk, MCH_SPLB_Rst => MCH_SPLB_Rst, MCH0_Access_Control => MCH0_Access_Control, MCH0_Access_Data => MCH0_Access_Data, MCH0_Access_Write => MCH0_Access_Write, MCH0_Access_Full => MCH0_Access_Full, MCH0_ReadData_Control => MCH0_ReadData_Control, MCH0_ReadData_Data => MCH0_ReadData_Data, MCH0_ReadData_Read => MCH0_ReadData_Read, MCH0_ReadData_Exists => MCH0_ReadData_Exists, MCH1_Access_Control => MCH1_Access_Control, MCH1_Access_Data => MCH1_Access_Data, MCH1_Access_Write => MCH1_Access_Write, MCH1_Access_Full => MCH1_Access_Full, MCH1_ReadData_Control => MCH1_ReadData_Control, MCH1_ReadData_Data => MCH1_ReadData_Data, MCH1_ReadData_Read => MCH1_ReadData_Read, MCH1_ReadData_Exists => MCH1_ReadData_Exists, MCH2_Access_Control => MCH2_Access_Control, MCH2_Access_Data => MCH2_Access_Data, MCH2_Access_Write => MCH2_Access_Write, MCH2_Access_Full => MCH2_Access_Full, MCH2_ReadData_Control => MCH2_ReadData_Control, MCH2_ReadData_Data => MCH2_ReadData_Data, MCH2_ReadData_Read => MCH2_ReadData_Read, MCH2_ReadData_Exists => MCH2_ReadData_Exists, MCH3_Access_Control => MCH3_Access_Control, MCH3_Access_Data => MCH3_Access_Data, MCH3_Access_Write => MCH3_Access_Write, MCH3_Access_Full => MCH3_Access_Full, MCH3_ReadData_Control => MCH3_ReadData_Control, MCH3_ReadData_Data => MCH3_ReadData_Data, MCH3_ReadData_Read => MCH3_ReadData_Read, MCH3_ReadData_Exists => MCH3_ReadData_Exists, PLB_ABus => PLB_ABus, PLB_UABus => PLB_UABus, PLB_PAValid => PLB_PAValid, PLB_SAValid => PLB_SAValid, PLB_rdPrim => PLB_rdPrim, PLB_wrPrim => PLB_wrPrim, PLB_masterID => PLB_masterID, PLB_abort => PLB_abort, PLB_busLock => PLB_busLock, PLB_RNW => PLB_RNW, PLB_BE => PLB_BE, PLB_MSize => PLB_MSize, PLB_size => PLB_size, PLB_type => PLB_type, PLB_lockErr => PLB_lockErr, PLB_wrDBus => PLB_wrDBus, PLB_wrBurst => PLB_wrBurst, PLB_rdBurst => PLB_rdBurst, PLB_wrPendReq => PLB_wrPendReq, PLB_rdPendReq => PLB_rdPendReq, PLB_wrPendPri => PLB_wrPendPri, PLB_rdPendPri => PLB_rdPendPri, PLB_reqPri => PLB_reqPri, PLB_TAttribute => PLB_TAttribute, Sl_addrAck => Sl_addrAck, Sl_SSize => Sl_SSize, Sl_wait => Sl_wait, Sl_rearbitrate => Sl_rearbitrate, Sl_wrDAck => Sl_wrDAck, Sl_wrComp => Sl_wrComp, Sl_wrBTerm => Sl_wrBTerm, Sl_rdDBus => Sl_rdDBus, Sl_rdWdAddr => Sl_rdWdAddr, Sl_rdDAck => Sl_rdDAck, Sl_rdComp => Sl_rdComp, Sl_rdBTerm => Sl_rdBTerm, Sl_MBusy => Sl_MBusy, Sl_MWrErr => Sl_MWrErr, Sl_MRdErr => Sl_MRdErr, Sl_MIRQ => Sl_MIRQ, Mem_DQ_I => Mem_DQ_I, Mem_DQ_O => Mem_DQ_O, Mem_DQ_T => Mem_DQ_T, Mem_A => Mem_A, Mem_RPN => Mem_RPN, Mem_CEN => Mem_CEN, Mem_OEN => Mem_OEN, Mem_WEN => Mem_WEN, Mem_QWEN => Mem_QWEN, Mem_BEN => Mem_BEN, Mem_CE => Mem_CE, Mem_ADV_LDN => Mem_ADV_LDN, Mem_LBON => Mem_LBON, Mem_CKEN => Mem_CKEN, Mem_RNW => Mem_RNW ); end architecture STRUCTURE;
mit
e9cb6a182f4e269d5e5ca953150026b7
0.596675
2.978545
false
false
false
false
abyrne55/my-little-processor
binaryto4hex_bad.vhd
1
1,717
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.ALL; ENTITY binaryto4hex IS PORT ( binary : IN STD_LOGIC_VECTOR(15 downto 0); output0, output1, output2, output3 : OUT STD_LOGIC_VECTOR(6 downto 0) ); END binaryto4hex; ARCHITECTURE Behavioural OF binaryto4hex IS COMPONENT binary_to_sevenSeg PORT ( binary_value : IN STD_LOGIC_VECTOR(3 DOWNTO 0); sevenSeg : OUT STD_LOGIC_VECTOR(6 downto 0) ); END COMPONENT; SIGNAL H0, H1, H2, H3 : STD_LOGIC_VECTOR(3 downto 0); SIGNAL num : INTEGER; BEGIN num <= to_integer(unsigned(binary)); PROCESS (num) begin IF num < 10 THEN H3 <= "0000"; H2 <= "0000"; H1 <= "0000"; H0 <= std_logic_vector(to_unsigned(num, 4)); ELSIF num < 100 THEN H3 <= "0000"; H2 <= "0000"; H1 <= std_logic_vector(to_unsigned(num/10, 4)); H0 <= std_logic_vector(to_unsigned(num rem 10, 4)); ELSIF num < 1000 THEN H3 <= "0000"; H2 <= std_logic_vector(to_unsigned(num/100, 4)); H1 <= std_logic_vector(to_unsigned((num rem 100)/10, 4)); H0 <= std_logic_vector(to_unsigned(num rem 10, 4)); ELSE H3 <= std_logic_vector(to_unsigned(num/1000, 4)); H2 <= std_logic_vector(to_unsigned((num rem 1000)/100, 4)); H1 <= std_logic_vector(to_unsigned((num rem 100)/10, 4)); H0 <= std_logic_vector(to_unsigned(num rem 10, 4)); END IF; END PROCESS; bintoseg1: binary_to_sevenSeg PORT MAP ( binary_value => H0, sevenSeg => output0 ); bintoseg2: binary_to_sevenSeg PORT MAP ( binary_value => H1, sevenSeg => output1 ); bintoseg3: binary_to_sevenSeg PORT MAP ( binary_value => H2, sevenSeg => output2 ); bintoseg4: binary_to_sevenSeg PORT MAP ( binary_value => H3, sevenSeg => output3 ); END Behavioural;
mit
83ec96532c5fed602b987f913cde98ec
0.654048
2.703937
false
false
false
false
hoglet67/AtomFpga
src/common/AVR8/uC/AVR8.vhd
1
31,559
--************************************************************************************************ -- Top entity for AVR microcontroller (for synthesis) with JTAG OCD and DMAs -- Version 0.5 (Version for Xilinx) -- Designed by Ruslan Lepetenok -- Modified 31.05.2006 --************************************************************************************************ --************************************************************************************************ -- Adapted for AtomFPGA -- input clock is now 16MHz --************************************************************************************************ --************************************************************************************************ --Adapted for the Papilio FPGA development board. To learn more visit http://papilio.cc --Gadget Factory Note: This project is currently configured for the Papilio One board Version 2.03 or greater. It assumes a 32Mhz oscillator and a ucf with a period of 31.25. --************************************************************************************************* --************************************************************************************************* --This is AVR8-based SoC for processing diode signals --modifications by Zvonimir Bandic --modified 01/05/2013 --************************************************************************************************* library IEEE; use IEEE.std_logic_1164.all; use WORK.AVRuCPackage.all; use WORK.AVR_uC_CompPack.all; use WORK.SynthCtrlPack.all; -- Synthesis control use WORK.spi_mod_comp_pack.all; --SPI use WORK.spi_slv_sel_comp_pack.all; use WORK.MemAccessCtrlPack.all; use WORK.MemAccessCompPack.all; entity AVR8 is generic ( CDATAMEMSIZE : integer; CPROGMEMSIZE : integer; FILENAME : string; -- Use these setting to control which peripherals you want to include with your custom AVR8 implementation. CImplPORTA : boolean := FALSE; CImplPORTB : boolean := FALSE; CImplPORTC : boolean := FALSE; CImplPORTD : boolean := FALSE; CImplPORTE : boolean := FALSE; CImplPORTF : boolean := FALSE; CImplUART : boolean := FALSE; CImplSPI : boolean := FALSE; CImplTmrCnt : boolean := FALSE; CImplExtIRQ : boolean := FALSE ); port ( nrst : in std_logic; --Uncomment this to connect reset to an external pushbutton. Must be defined in ucf. clk16M : in std_logic; portaout : out std_logic_vector(7 downto 0); portain : in std_logic_vector(7 downto 0); portbout : out std_logic_vector(7 downto 0); portbin : in std_logic_vector(7 downto 0); portc : inout std_logic_vector(7 downto 0); portdin : in std_logic_vector(7 downto 0); portdout : out std_logic_vector(7 downto 0); portein : in std_logic_vector(7 downto 0); porteout : out std_logic_vector(7 downto 0); portf : inout std_logic_vector(7 downto 0); spi_mosio : out std_logic; spi_scko : out std_logic; spi_cs_n : out std_logic; spi_misoi : in std_logic; -- UART rxd : in std_logic; txd : out std_logic ); end AVR8; architecture Struct of AVR8 is -- ############################## Signals connected directly to the core ########################################## signal core_cpuwait : std_logic; -- Program memory signal core_pc : std_logic_vector (15 downto 0); -- PROM address signal core_inst : std_logic_vector (15 downto 0); -- PROM data -- I/O registers signal core_adr : std_logic_vector (15 downto 0); signal core_iore : std_logic; signal core_iowe : std_logic; -- Data memery signal core_ramadr : std_logic_vector (15 downto 0); signal core_ramre : std_logic; signal core_ramwe : std_logic; signal core_dbusin : std_logic_vector (7 downto 0); signal core_dbusout : std_logic_vector (7 downto 0); -- Interrupts signal core_irqlines : std_logic_vector(22 downto 0); signal core_irqack : std_logic; signal core_irqackad : std_logic_vector(4 downto 0); -- ############################################################################################################### -- ############################## Signals connected directly to the SRAM controller ############################### signal ram_din : std_logic_vector(7 downto 0); -- ############################################################################################################### -- ####################### Signals connected directly to the external multiplexer ################################ signal io_port_out : ext_mux_din_type; signal io_port_out_en : ext_mux_en_type; signal ind_irq_ack : std_logic_vector(core_irqlines'range); -- ############################################################################################################### -- ################################## Reset signals ############################################# signal core_ireset : std_logic; -- ############################################################################################## -- Port signals signal PortAReg : std_logic_vector(portain'range); signal DDRAReg : std_logic_vector(portain'range); signal PortBReg : std_logic_vector(portbin'range); signal DDRBReg : std_logic_vector(portbin'range); signal PortCReg : std_logic_vector(portc'range); signal DDRCReg : std_logic_vector(portc'range); signal PortDReg : std_logic_vector(portdin'range); signal DDRDReg : std_logic_vector(portdin'range); signal PortEReg : std_logic_vector(portein'range); signal DDREReg : std_logic_vector(portein'range); signal PortFReg : std_logic_vector(portf'range); signal DDRFReg : std_logic_vector(portf'range); -- Added for Synopsys compatibility signal gnd : std_logic; signal vcc : std_logic; -- Sleep support signal core_cp2 : std_logic; -- Global clock signal after gating(and global primitive) signal sleep_en : std_logic; signal sleepi : std_logic; signal irqok : std_logic; signal globint : std_logic; signal nrst_clksw : std_logic; -- Separate reset for clock gating module -- Watchdog related signals signal wdtmout : std_logic; -- Watchdog overflow signal core_wdri : std_logic; -- Watchdog clear -- ********************** JTAG and memory ********************************************** -- PM address,data and control signal pm_adr : std_logic_vector(core_pc'range); signal pm_h_we : std_logic; signal pm_l_we : std_logic; signal pm_din : std_logic_vector(core_inst'range); signal pm_dout : std_logic_vector(core_inst'range); signal TDO_Out : std_logic; signal TDO_OE : std_logic; signal JTAG_Rst : std_logic; -- ********************** JTAG and memory ********************************************** signal nrst_cp64m_tmp : std_logic; signal ram_cp2_n : std_logic; signal sleep_mode : std_logic; -- "EEPROM" related signals signal EEPrgSel : std_logic; signal EEAdr : std_logic_vector(11 downto 0); signal EEWrData : std_logic_vector(7 downto 0); signal EERdData : std_logic_vector(7 downto 0); signal EEWr : std_logic; -- New signal busmin : MastersOutBus_Type; signal busmwait : std_logic_vector(CNumOfBusMasters-1 downto 0) := (others => '0'); signal slv_outs : SlavesOutBus_Type; signal ram_sel : std_logic; -- UART DMA signal udma_mack : std_logic; signal mem_mux_out : std_logic_vector (7 downto 0); -- Place Holder Signals for JTAG instead of connecting them externally signal TRSTn : std_logic; signal TMS : std_logic; signal TCK : std_logic; signal TDI : std_logic; signal TDO : std_logic; -- AES signal aes_mack : std_logic; -- Address decoder signal stb_IO : std_logic; signal stb_IOmod : std_logic_vector (CNumOfSlaves-1 downto 0); signal ram_ce : std_logic; signal slv_cpuwait : std_logic; -- Memory i/f signal mem_ramadr : std_logic_vector (15 downto 0); signal mem_ram_dbus_in : std_logic_vector (7 downto 0); signal mem_ram_dbus_out : std_logic_vector (7 downto 0); signal mem_ramwe : std_logic; signal mem_ramre : std_logic; -- RAM signal ram_ramwe : std_logic; -- nrst --signal nrst : std_logic; --Comment this to connect reset to an external pushbutton. -- ############################## Signals connected directly to the I/O registers ################################ -- PortA signal porta_dbusout : std_logic_vector (7 downto 0); signal porta_out_en : std_logic; -- PortB signal portb_dbusout : std_logic_vector (7 downto 0); signal portb_out_en : std_logic; -- PortC signal portc_dbusout : std_logic_vector (7 downto 0); signal portc_out_en : std_logic; -- PortD signal portd_dbusout : std_logic_vector (7 downto 0); signal portd_out_en : std_logic; -- PortE signal porte_dbusout : std_logic_vector (7 downto 0); signal porte_out_en : std_logic; -- PortF signal portf_dbusout : std_logic_vector (7 downto 0); signal portf_out_en : std_logic; -- Timer/Counter signal tc_dbusout : std_logic_vector (7 downto 0); signal tc_out_en : std_logic; -- Ext IRQ Controller signal extirq_dbusout : std_logic_vector (7 downto 0); signal extirq_out_en : std_logic; signal ext_irqlines : std_logic_vector(7 downto 0); -- UART signal uart_dbusout : std_logic_vector (7 downto 0); signal uart_out_en : std_logic; -- SPI constant c_spi_slvs_num : integer := 1; --signal spi_misoi : std_logic; signal spi_mosii : std_logic; signal spi_scki : std_logic; signal spi_ss_b : std_logic; signal spi_misoo : std_logic; --signal spi_mosio : std_logic; --signal spi_scko : std_logic; signal spi_spe : std_logic; signal spi_spimaster : std_logic; signal spi_dbusout : std_logic_vector (7 downto 0); signal spi_out_en : std_logic; -- Slave selects signal spi_slv_sel_n : std_logic_vector(c_spi_slvs_num-1 downto 0); -- SPI -- ############################################################################################################### -- ############################## Define Signals for User Cores ################################################## -- Example Core - - core9 --signal core9_input_sig : std_logic_vector(1 downto 0); --Define a signal for the inputs. -- ############################################################################################################### begin -- Added for Synopsys compatibility gnd <= '0'; vcc <= '1'; -- Added for Synopsys compatibility --nrst <= '1'; --Comment this to connect reset to an external pushbutton. core_inst <= pm_dout; --Signals to connect peripherals controlled from Generics to the physical ports -- ****************** User Cores - Instantiate User Cores Here ************************** -- ****************** END User Cores - Instantiate User Cores Here ************************** -- Unused IRQ lines --core_irqlines(7 downto 4) <= ( others => '0'); --core_irqlines(3 downto 0) <= ( others => '0'); core_irqlines(13 downto 10) <= ( others => '0'); --core_irqlines(16) <= '0'; --now used by SPI core_irqlines(22 downto 20) <= ( others => '0'); -- ************************ -- Unused out_en io_port_out_en(11 to 15) <= (others => '0'); io_port_out(11 to 15) <= (others => (others => '0')); AVR_Core_Inst:component AVR_Core port map( --Clock and reset cp2 => core_cp2, cp2en => vcc, ireset => core_ireset, -- JTAG OCD support valid_instr => open, insert_nop => gnd, block_irq => gnd, change_flow => open, -- Program Memory pc => core_pc, inst => core_inst, -- I/O control adr => core_adr, iore => core_iore, iowe => core_iowe, -- Data memory control ramadr => core_ramadr, ramre => core_ramre, ramwe => core_ramwe, cpuwait => core_cpuwait, -- Data paths dbusin => core_dbusin, dbusout => core_dbusout, -- Interrupts irqlines => core_irqlines, irqack => core_irqack, irqackad => core_irqackad, --Sleep Control sleepi => sleepi, irqok => irqok, globint => globint, --Watchdog wdri => core_wdri); RAM_Data_Register:component RAMDataReg port map( ireset => core_ireset, cp2 => clk16M, -- clk, cpuwait => core_cpuwait, RAMDataIn => core_dbusout, RAMDataOut => ram_din ); EXT_MUX:component external_mux port map( ramre => mem_ramre, -- ramre output of the arbiter and multiplexor dbus_out => core_dbusin, -- Data input of the core ram_data_out => mem_mux_out, -- Data output of the RAM mux(RAM or memory located I/O) io_port_bus => io_port_out, -- Data outputs of the I/O io_port_en_bus => io_port_out_en, -- Out enable outputs of I/O irqack => core_irqack, irqackad => core_irqackad, ind_irq_ack => ind_irq_ack -- Individual interrupt acknolege for the peripheral ); -- ****************** PORTA ************************** PORTA_Impl:if CImplPORTA generate PORTA_COMP:component pport generic map(PPortNum => 0) port map( -- AVR Control ireset => core_ireset, cp2 => clk16M, -- clk, adr => core_adr, dbus_in => core_dbusout, dbus_out => porta_dbusout, iore => core_iore, iowe => core_iowe, out_en => porta_out_en, -- External connection portx => PortAReg, ddrx => DDRAReg, pinx => portain, irqlines => open); -- PORTA connection to the external multiplexer io_port_out(0) <= porta_dbusout; io_port_out_en(0) <= porta_out_en; ---- Tri-state control for PORTA --PortAZCtrl:for i in porta'range generate --porta(i) <= PortAReg(i) when DDRAReg(i)='1' else 'Z'; --end generate; -- Tri-state control for PORTA PortAZCtrl:for i in portaout'range generate portaout(i) <= PortAReg(i) when DDRAReg(i)='1' else '0'; end generate; end generate; PORTA_Not_Impl:if not CImplPORTA generate portaout <= (others => '0'); end generate; -- ****************** PORTB ************************** PORTB_Impl:if CImplPORTB generate PORTB_COMP:component pport generic map (PPortNum => 1) port map( -- AVR Control ireset => core_ireset, cp2 => clk16M, -- clk, adr => core_adr, dbus_in => core_dbusout, dbus_out => portb_dbusout, iore => core_iore, iowe => core_iowe, out_en => portb_out_en, -- External connection portx => PortBReg, ddrx => DDRBReg, pinx => portbin, irqlines => ext_irqlines); -- PORTB connection to the external multiplexer io_port_out(1) <= portb_dbusout; io_port_out_en(1) <= portb_out_en; ---- Tri-state control for PORTB --PortBZCtrl:for i in portb'range generate --portb(i) <= PortBReg(i) when DDRBReg(i)='1' else 'Z'; --end generate; -- Tri-state control for PORTB PortBZCtrl:for i in portbout'range generate --portb(i) <= PortBReg(i) when DDRBReg(i)='1' else 'Z'; portbout(i) <= PortBReg(i) when DDRBReg(i)='1' else '0'; end generate; end generate; PORTB_Not_Impl:if not CImplPORTB generate portbout <= (others => '0'); end generate; -- ************************************************ -- ****************** PORTC ************************** PORTC_Impl:if CImplPORTC generate PORTC_COMP:component pport generic map(PPortNum => 2) port map( -- AVR Control ireset => core_ireset, cp2 => clk16M, -- clk, adr => core_adr, dbus_in => core_dbusout, dbus_out => portc_dbusout, iore => core_iore, iowe => core_iowe, out_en => portc_out_en, -- External connection portx => PortCReg, ddrx => DDRCReg, pinx => portc, irqlines => open); -- PORTC connection to the external multiplexer io_port_out(5) <= portc_dbusout; io_port_out_en(5) <= portc_out_en; ---- Tri-state control for PORTC --PortCZCtrl:for i in portc'range generate --portc(i) <= PortCReg(i) when DDRCReg(i)='1' else 'Z'; --end generate; -- Tri-state control for PORTC PortCZCtrl:for i in portc'range generate portc(i) <= PortCReg(i) when DDRCReg(i)='1' else 'Z'; end generate; end generate; PORTC_Not_Impl:if not CImplPORTC generate portc <= (others => 'Z'); end generate; -- ****************** PORTD ************************** PORTD_Impl:if CImplPORTD generate PORTD_COMP:component pport generic map (PPortNum => 3) port map( -- AVR Control ireset => core_ireset, cp2 => clk16M, -- clk, adr => core_adr, dbus_in => core_dbusout, dbus_out => portd_dbusout, iore => core_iore, iowe => core_iowe, out_en => portd_out_en, -- External connection portx => PortDReg, ddrx => DDRDReg, pinx => portdin, irqlines => open); -- PORTD connection to the external multiplexer io_port_out(6) <= portd_dbusout; io_port_out_en(6) <= portd_out_en; ---- Tri-state control for PORTD --PortDZCtrl:for i in portd'range generate --portd(i) <= PortDReg(i) when DDRDReg(i)='1' else 'Z'; --end generate; -- Tri-state control for PORTD PortDZCtrl:for i in portdout'range generate portdout(i) <= PortDReg(i) when DDRDReg(i)='1' else '0'; end generate; end generate; PORTD_Not_Impl:if not CImplPORTD generate portdout <= (others => '0'); end generate; -- ************************************************ -- ****************** PORTE ************************** PORTE_Impl:if CImplPORTE generate PORTE_COMP:component pport generic map(PPortNum => 4) port map( -- AVR Control ireset => core_ireset, cp2 => clk16M, -- clk, adr => core_adr, dbus_in => core_dbusout, dbus_out => porte_dbusout, iore => core_iore, iowe => core_iowe, out_en => porte_out_en, -- External connection portx => PortEReg, ddrx => DDREReg, pinx => portein, irqlines => open); -- PORTE connection to the external multiplexer io_port_out(7) <= porte_dbusout; io_port_out_en(7) <= porte_out_en; ---- Tri-state control for PORTE --PortEZCtrl:for i in porte'range generate --porte(i) <= PortEReg(i) when DDREReg(i)='1' else 'Z'; --end generate; -- Tri-state control for PORTE PortEZCtrl:for i in porteout'range generate porteout(i) <= PortEReg(i) when DDREReg(i)='1' else 'Z'; end generate; end generate; PORTE_Not_Impl:if not CImplPORTE generate porteout <= (others => 'Z'); end generate; -- ****************** PORTF ************************** PORTF_Impl:if CImplPORTF generate PORTF_COMP:component pport generic map (PPortNum => 5) port map( -- AVR Control ireset => core_ireset, cp2 => clk16M, -- clk, adr => core_adr, dbus_in => core_dbusout, dbus_out => portf_dbusout, iore => core_iore, iowe => core_iowe, out_en => portf_out_en, -- External connection portx => PortFReg, ddrx => DDRFReg, pinx => portf, irqlines => open); -- PORTF connection to the external multiplexer io_port_out(8) <= portf_dbusout; io_port_out_en(8) <= portf_out_en; -- Tri-state control for PORTF PortFZCtrl:for i in portf'range generate portf(i) <= PortFReg(i) when DDRFReg(i)='1' else 'Z'; end generate; end generate; PORTF_Not_Impl:if not CImplPORTF generate portf <= (others => 'Z'); end generate; -- ************************************************ --****************** External IRQ Controller************************** ExtIRQ_Impl:if CImplExtIRQ generate ExtIRQ_Inst:component ExtIRQ_Controller port map( -- AVR Control nReset => core_ireset, clk => clk16M, -- clk, clken => vcc, irq_clken => vcc, adr => core_adr, dbus_in => core_dbusout, dbus_out => extirq_dbusout, iore => core_iore, iowe => core_iowe, out_en => extirq_out_en, ------------------------------------------------ extpins => ext_irqlines, INTx => core_irqlines(7 downto 0)); -- ExtIRQ connection to the external multiplexer io_port_out(10) <= extirq_dbusout; io_port_out_en(10) <= extirq_out_en; end generate; --****************** Timer/Counter ************************** TmrCnt_Impl:if CImplTmrCnt generate TmrCnt_Inst:component Timer_Counter port map( -- AVR Control ireset => core_ireset, cp2 => clk16M, -- clk, cp2en => vcc, tmr_cp2en => vcc, stopped_mode => gnd, tmr_running => gnd, adr => core_adr, dbus_in => core_dbusout, dbus_out => tc_dbusout, iore => core_iore, iowe => core_iowe, out_en => tc_out_en, -- External inputs/outputs EXT1 => gnd, EXT2 => gnd, OC0_PWM0 => open, OC1A_PWM1A => open, OC1B_PWM1B => open, OC2_PWM2 => open, -- Interrupt related signals TC0OvfIRQ => core_irqlines(15), -- Timer/Counter0 overflow ($0020) TC0OvfIRQ_Ack => ind_irq_ack(15), TC0CmpIRQ => core_irqlines(14), -- Timer/Counter0 Compare Match ($001E) TC0CmpIRQ_Ack => ind_irq_ack(14), TC2OvfIRQ => core_irqlines(9), -- Timer/Counter2 overflow ($0014) TC2OvfIRQ_Ack => ind_irq_ack(9), TC2CmpIRQ => core_irqlines(8), -- Timer/Counter2 Compare Match ($0012) TC2CmpIRQ_Ack => ind_irq_ack(8), TC1OvfIRQ => open, TC1OvfIRQ_Ack => gnd, TC1CmpAIRQ => open, TC1CmpAIRQ_Ack => gnd, TC1CmpBIRQ => open, TC1CmpBIRQ_Ack => gnd, TC1ICIRQ => open, TC1ICIRQ_Ack => gnd, PWM0bit => open, PWM10bit => open, PWM11bit => open, PWM2bit => open); -- Timer/Counter connection to the external multiplexer io_port_out(4) <= tc_dbusout; io_port_out_en(4) <= tc_out_en; end generate; -- Watchdog is not implemented wdtmout <= '0'; -- Reset generator ResetGenerator_Inst:component ResetGenerator port map( -- Clock inputs cp2 => clk16M, -- clk, cp64m => gnd, -- Reset inputs nrst => nrst, npwrrst => vcc, wdovf => wdtmout, jtagrst => JTAG_Rst, -- Reset outputs nrst_cp2 => core_ireset, nrst_cp64m => nrst_cp64m_tmp, nrst_clksw => nrst_clksw ); ClockGatingDis:if not CImplClockSw generate core_cp2 <= clk16M; end generate; -- ********************** JTAG and memory ********************************************** ram_cp2_n <= not clk16M; ---- Data memory(8-bit) DM_Inst : entity work.XDM generic map ( WIDTH => 8, SIZE => CDATAMEMSIZE ) port map( cp2 => ram_cp2_n, ce => vcc, address => mem_ramadr(f_log2(CDATAMEMSIZE) - 1 downto 0), din => mem_ram_dbus_in, dout => mem_ram_dbus_out, we => ram_ramwe ); -- Program memory PM_Inst : entity work.XPM generic map ( WIDTH => 16, SIZE => CPROGMEMSIZE, FILENAME => FILENAME ) port map( cp2 => ram_cp2_n, ce => vcc, address => pm_adr(f_log2(CPROGMEMSIZE) - 1 downto 0), din => pm_din, dout => pm_dout, we => pm_l_we ); -- ********************** JTAG and memory ********************************************** -- Sleep mode is not implemented sleep_mode <= '0'; JTAGOCDPrgTop_Inst:component JTAGOCDPrgTop port map( -- AVR Control ireset => core_ireset, cp2 => core_cp2, -- JTAG related inputs/outputs TRSTn => TRSTn, -- Optional TMS => TMS, TCK => TCK, TDI => TDI, TDO => TDO_Out, TDO_OE => TDO_OE, -- From the core PC => core_pc, -- To the PM("Flash") pm_adr => pm_adr, pm_h_we => pm_h_we, pm_l_we => pm_l_we, pm_dout => pm_dout, pm_din => pm_din, -- To the "EEPROM" EEPrgSel => EEPrgSel, EEAdr => EEAdr, EEWrData => EEWrData, EERdData => EERdData, EEWr => EEWr, -- CPU reset jtag_rst => JTAG_Rst ); -- JTAG OCD module connection to the external multiplexer io_port_out(3) <= (others => '0'); io_port_out_en(3) <= gnd; TDO <= TDO_Out when TDO_OE='1' else 'Z'; -- ******************************************************************************************************* -- DMA, Memory decoder, ... -- ******************************************************************************************************* -- ****************** SPI ************************** spi_is_used:if CImplSPI generate spi_mod_inst:component spi_mod port map( -- AVR Control ireset => core_ireset, cp2 => clk16M, adr => core_adr, dbus_in => core_dbusout, dbus_out => spi_dbusout, iore => core_iore, iowe => core_iowe, out_en => spi_out_en, -- SPI i/f misoi => spi_misoi, mosii => spi_mosii, scki => spi_scki, ss_b => spi_ss_b, misoo => spi_misoo, mosio => spi_mosio, scko => spi_scko, spe => spi_spe, spimaster => spi_spimaster, -- IRQ spiirq => core_irqlines(16), spiack => ind_irq_ack(16), -- Slave Programming Mode por => gnd, spiextload => gnd, spidwrite => open, spiload => open ); -- SPI connection to the external multiplexer io_port_out(9) <= spi_dbusout; io_port_out_en(9) <= spi_out_en; -- Pads --mosi_SIG <= spi_mosio when (spi_spimaster='1') else 'Z'; --miso_SIG <= spi_misoo when (spi_spimaster='0') else 'Z'; --sck_SIG <= spi_scko when (spi_spimaster='1') else 'Z'; -- --spi_misoi <= miso_SIG; --spi_mosii <= mosi_SIG; --spi_scki <= sck_SIG; spi_ss_b <= vcc; -- Pads spi_slv_sel_inst:component spi_slv_sel generic map(num_of_slvs => c_spi_slvs_num) port map( -- AVR Control ireset => core_ireset, cp2 => core_cp2, adr => core_adr, dbus_in => core_dbusout, dbus_out => open, iore => core_iore, iowe => core_iowe, out_en => open, -- Output slv_sel_n => spi_slv_sel_n ); end generate; spi_cs_n <= spi_slv_sel_n(0); no_spi:if not CImplSPI generate --mosi_SIG <= 'Z'; --miso_SIG <= 'Z'; --sck_SIG <= 'Z'; --io_slv_out(1).dbusout <= (others => '0'); --io_slv_out(1).out_en <= gnd; spi_slv_sel_n <= (others => '1'); end generate; uart_Inst:component uart port map( -- AVR Control ireset => core_ireset, cp2 => core_cp2, adr => core_adr, dbus_in => core_dbusout, dbus_out => uart_dbusout, iore => core_iore, iowe => core_iowe, out_en => uart_out_en, -- UART rxd => rxd, rx_en => open, txd => txd, tx_en => open, -- IRQ txcirq => core_irqlines(19), txc_irqack => ind_irq_ack(19), udreirq => core_irqlines(18), rxcirq => core_irqlines(17) ); -- UART connection to the external multiplexer io_port_out(2) <= uart_dbusout; io_port_out_en(2) <= uart_out_en; -- Arbiter and mux ArbiterAndMux_Inst:component ArbiterAndMux port map( --Clock and reset ireset => core_ireset, cp2 => core_cp2, -- Bus masters busmin => busmin, busmwait => busmwait, -- Memory Address,Data and Control ramadr => mem_ramadr, ramdout => mem_ram_dbus_in, ramre => mem_ramre, ramwe => mem_ramwe, cpuwait => slv_cpuwait ); -- cpuwait slv_cpuwait <= '0'; -- Core connection busmin(0).ramadr <= core_ramadr; busmin(0).dout <= ram_din; -- !!! busmin(0).ramre <= core_ramre; busmin(0).ramwe <= core_ramwe; core_cpuwait <= busmwait(0); -- UART DMA connection busmin(1).ramadr <= (others => '0'); busmin(1).dout <= (others => '0'); -- !!! busmin(1).ramre <= gnd; busmin(1).ramwe <= gnd; udma_mack <= not busmwait(1); -- AES DMA connection busmin(2).ramadr <= (others => '0'); busmin(2).dout <= (others => '0'); busmin(2).ramre <= gnd; busmin(2).ramwe <= gnd; aes_mack <= not busmwait(2); -- UART DMA slave part slv_outs(0).dout <= (others => '0'); slv_outs(0).out_en <= gnd; -- AES DMA slave part slv_outs(1).dout <= (others => '0'); slv_outs(1).out_en <= gnd; -- Memory read mux MemRdMux_inst:component MemRdMux port map( slv_outs => slv_outs, ram_sel => ram_sel, -- Data RAM selection(optional input) ram_dout => mem_ram_dbus_out, -- Data memory output (From RAM) dout => mem_mux_out -- Data output (To the core and other bus masters) ); -- Address decoder RAMAdrDcd_Inst:component RAMAdrDcd port map( ramadr => mem_ramadr, ramre => mem_ramre, ramwe => mem_ramwe, -- Memory mapped I/O i/f stb_IO => stb_IO, stb_IOmod => stb_IOmod, -- Data memory i/f ram_we => ram_ramwe, ram_ce => ram_ce, ram_sel => ram_sel ); end Struct;
apache-2.0
bf65fce2c54120d9717a3c3be746ce1c
0.498273
3.70237
false
false
false
false
GSimas/EEL5105
Eletr-Digital/Projeto Final/PROJETO COFRE FUNCIONANDO/BuzzerDo.vhd
1
4,562
-- megafunction wizard: %LPM_COUNTER% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: lpm_counter -- ============================================================ -- File Name: BuzzerDo.vhd -- Megafunction Name(s): -- lpm_counter -- -- Simulation Library Files(s): -- lpm -- ============================================================ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- -- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition -- ************************************************************ --Copyright (C) 1991-2010 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject --to the terms and conditions of the Altera Program License --Subscription Agreement, Altera MegaCore Function License --Agreement, or other applicable license agreement, including, --without limitation, that your use is for the sole purpose of --programming logic devices manufactured by Altera and sold by --Altera or its authorized distributors. Please refer to the --applicable agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY lpm; USE lpm.all; ENTITY BuzzerDo IS PORT ( clock : IN STD_LOGIC ; cout : OUT STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (29 DOWNTO 0) ); END BuzzerDo; ARCHITECTURE SYN OF buzzerdo IS SIGNAL sub_wire0 : STD_LOGIC ; SIGNAL sub_wire1 : STD_LOGIC_VECTOR (29 DOWNTO 0); COMPONENT lpm_counter GENERIC ( lpm_direction : STRING; lpm_modulus : NATURAL; lpm_port_updown : STRING; lpm_type : STRING; lpm_width : NATURAL ); PORT ( clock : IN STD_LOGIC ; cout : OUT STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (29 DOWNTO 0) ); END COMPONENT; BEGIN cout <= sub_wire0; q <= sub_wire1(29 DOWNTO 0); lpm_counter_component : lpm_counter GENERIC MAP ( lpm_direction => "UP", lpm_modulus => 94697, lpm_port_updown => "PORT_UNUSED", lpm_type => "LPM_COUNTER", lpm_width => 30 ) PORT MAP ( clock => clock, cout => sub_wire0, q => sub_wire1 ); END SYN; -- ============================================================ -- CNX file retrieval info -- ============================================================ -- Retrieval info: PRIVATE: ACLR NUMERIC "0" -- Retrieval info: PRIVATE: ALOAD NUMERIC "0" -- Retrieval info: PRIVATE: ASET NUMERIC "0" -- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1" -- Retrieval info: PRIVATE: CLK_EN NUMERIC "0" -- Retrieval info: PRIVATE: CNT_EN NUMERIC "0" -- Retrieval info: PRIVATE: CarryIn NUMERIC "0" -- Retrieval info: PRIVATE: CarryOut NUMERIC "1" -- Retrieval info: PRIVATE: Direction NUMERIC "0" -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" -- Retrieval info: PRIVATE: ModulusCounter NUMERIC "1" -- Retrieval info: PRIVATE: ModulusValue NUMERIC "94697" -- Retrieval info: PRIVATE: SCLR NUMERIC "0" -- Retrieval info: PRIVATE: SLOAD NUMERIC "0" -- Retrieval info: PRIVATE: SSET NUMERIC "0" -- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: nBit NUMERIC "30" -- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP" -- Retrieval info: CONSTANT: LPM_MODULUS NUMERIC "94697" -- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER" -- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "30" -- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock -- Retrieval info: USED_PORT: cout 0 0 0 0 OUTPUT NODEFVAL cout -- Retrieval info: USED_PORT: q 0 0 30 0 OUTPUT NODEFVAL q[29..0] -- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 -- Retrieval info: CONNECT: q 0 0 30 0 @q 0 0 30 0 -- Retrieval info: CONNECT: cout 0 0 0 0 @cout 0 0 0 0 -- Retrieval info: LIBRARY: lpm lpm.lpm_components.all -- Retrieval info: GEN_FILE: TYPE_NORMAL BuzzerDo.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL BuzzerDo.inc TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL BuzzerDo.cmp TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL BuzzerDo.bsf TRUE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL BuzzerDo_inst.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL BuzzerDo_waveforms.html TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL BuzzerDo_wave*.jpg FALSE -- Retrieval info: LIB_FILE: lpm
mit
472f2b82cf3db7cc4b6a5f01a7451111
0.655633
3.664257
false
false
false
false
hoglet67/AtomFpga
src/common/RAM/RAM0x8000.vhd
2
1,270
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity SRAM0x8000 is port ( clk : in std_logic; rd_vid : in std_logic; addr_vid : in std_logic_vector (12 downto 0); Q_vid : out std_logic_vector (7 downto 0); we_uP : in std_logic; ce : in std_logic; addr_uP : in std_logic_vector (12 downto 0); D_uP : in std_logic_vector (7 downto 0); Q_uP : out std_logic_vector (7 downto 0)); end SRAM0x8000; architecture BEHAVIORAL of SRAM0x8000 is type ram_type is array (8191 downto 0) of std_logic_vector (7 downto 0); signal RAM : ram_type := (8191 downto 0 => X"ff"); attribute RAM_STYLE : string; attribute RAM_STYLE of RAM : signal is "BLOCK"; begin process (clk) begin if rising_edge(clk) then if (we_UP = '1' and ce = '1') then RAM(conv_integer(addr_uP(12 downto 0))) <= D_up; end if; Q_up <= RAM(conv_integer(addr_uP(12 downto 0))); if (rd_vid = '1') then Q_vid <= RAM(conv_integer(addr_vid(12 downto 0))); end if; end if; end process; end BEHAVIORAL;
apache-2.0
e1c719cdca71cba9b2f65f53ff9746b6
0.532283
3.37766
false
false
false
false
tghaefli/ADD
ISE/FMC/mcu_pkg.vhd
1
11,163
------------------------------------------------------------------------------- -- Entity: mcu_pkg -- Author: Waj ------------------------------------------------------------------------------- -- Description: -- VHDL package for definition of design parameters and types used throughout -- the MCU. ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; package mcu_pkg is ----------------------------------------------------------------------------- -- tool chain selection (because no suppoprt of 'val attritube in ISE XST) ----------------------------------------------------------------------------- constant ISE_TOOL : boolean := true; -- true = ISE XST -- false = other synthesizer (e.g. Vivado) -- system clock frequency in Hz constant CF : natural := 50_000_000; -- 50 MHz -- prescaler factor constant DUR_SCALE : natural := 5_000; -- constant scale factor -> Tclk 1ms constant NCO_SCALE : natural := 5; -- constant scale factor -> Tclk 1ms ----------------------------------------------------------------------------- -- Helper functions (prototypes) ----------------------------------------------------------------------------- -- std_logic_vector(to_signed(i,w)) function i2slv(i : integer; w : positive) return std_logic_vector; -- std_logic_vector(to_unsigned(n,w)) function n2slv(n : natural; w : positive) return std_logic_vector; -- form instruction word for NOP instruction function iw_nop return std_logic_vector; ----------------------------------------------------------------------------- -- design parameters: Memory Map ----------------------------------------------------------------------------- -- bus architecture parameters constant DW : natural range 4 to 64 := 16; -- data word width constant AW : natural range 2 to 64 := 10; -- total address width constant AWH : natural range 1 to 64 := 4; -- high address width constant AWL : natural range 1 to 64 := AW-AWH; -- low address width -- fmc rom parameters constant FMC_NUM_CHN: natural range 1 to 8 := 8; -- # of FMC channels constant FMC_ROM_AW : natural range 1 to 10 := 10; --FMC_ROM address width constant FMC_ROM_DW : natural range 1 to 20 := 20; --FMC_ROM data word width constant FMC_DUR_WW : natural range 1 to 16 := 14; --FMC_ROM tone duration word width constant FMC_TON_WW : natural range 1 to 16 := 6; --FMC_ROM tone duration word width constant FMC_LAST_TONE : unsigned(FMC_DUR_WW-1 downto 0) := (others => '1'); -- last-tone indicator -- memory map type t_bus_slave is (ROM, RAM, GPIO, FMC, TIM, UART); -- list of bus slaves type t_ba is array (t_bus_slave) of std_logic_vector(AW-1 downto 0); constant BA : t_ba := ( -- full base addresses ROM => "0-" & "----" & "----", RAM => "10" & "----" & "----", GPIO => "11" & "00--" & "----", FMC => "11" & "01--" & "----", TIM => "11" & "10--" & "----", UART => "11" & "11--" & "----" ); type t_hba is array (t_bus_slave) of std_logic_vector(AWH-1 downto 0); constant HBA : t_hba := ( -- high base address for decoding ROM => BA(ROM) (AW-1 downto AW-AWH), RAM => BA(RAM) (AW-1 downto AW-AWH), GPIO => BA(GPIO)(AW-1 downto AW-AWH), FMC => BA(FMC) (AW-1 downto AW-AWH), TIM => BA(TIM) (AW-1 downto AW-AWH), UART => BA(UART)(AW-1 downto AW-AWH) ); -- Relative Register Addresses of Peripherals -- GPIO constant c_addr_gpio_data_in : std_logic_vector(AWL-1 downto 0) := n2slv( 0, AWL); constant c_addr_gpio_data_out : std_logic_vector(AWL-1 downto 0) := n2slv( 1, AWL); constant c_addr_gpio_out_enb : std_logic_vector(AWL-1 downto 0) := n2slv( 2, AWL); type t_gpio_addr_sel is (none, gpio_data_in, gpio_data_out, gpio_enb); -- FMC constant N_FMC : natural range 1 to 8 := 8; --# of FMC channels constant c_addr_fmc_chn_enb : std_logic_vector(AWL-1 downto 0) := n2slv( 0, AWL); constant c_addr_fmc_tmp_ctrl : std_logic_vector(AWL-1 downto 0) := n2slv( 1, AWL); type t_fmc_addr_sel is (none, fmc_chn_enb, fmc_tmp_ctrl); -- TIM -- UART ----------------------------------------------------------------------------- -- design parameters: CPU Instructions ----------------------------------------------------------------------------- -- CPU instruction set -- Note: Defining the OPcode in the way shown below, allows assembler-style -- programming with mnemonics rather than machine coding (see rom.vhd). constant OPCW : natural range 1 to DW := 5; -- Opcode word width constant OPAW : natural range 1 to DW := 4; -- ALU operation word width constant IOWW : natural range 1 to DW := 8; -- immediate operand word width type t_instr is (add, sub, andi, ori, xori, slai, srai, mov, ld, st, addil, addih, setil, setih, jmp, bne, bge, blt, bca, bov, nop); -- Instructions targeted at the ALU are defined by means of a sub-type. -- This allows changing the opcode of instructions without having to -- modify the source code of the ALU. subtype t_alu_instr is t_instr range add to mov; type t_opcode is array (t_instr) of std_logic_vector(OPCW-1 downto 0); constant OPC : t_opcode := ( -- OPcode -- ALU operations ------------------------------- add => "00000", -- 0: addition sub => "00001", -- 1: subtraction andi => "00010", -- 2: bit-wise AND ori => "00011", -- 3: bit-wise OR xori => "00100", -- 4: bit-wise XOR slai => "00101", -- 5: shift-left arithmetically srai => "00110", -- 6: shift-right arithmetically mov => "00111", -- 7: move between register -- Immediate Operands --------------------------- addil => "01100", -- 12: add imm. constant low addih => "01101", -- 13: add imm. constant high setil => "01110", -- 14: set imm. constant low setih => "01111", -- 15: set imm. constant high -- Memory load/store ---------------------------- ld => "10000", -- 16: load from memory st => "10001", -- 17: store to memory -- Jump/Branch ---------------------------------- jmp => "11000", -- 24: absolute jump bne => "11001", -- 25: branch if not equal (not Z) bge => "11010", -- 26: branch if greater/equal (not N or Z) blt => "11011", -- 27: branch if less than (N) bca => "11100", -- 28: branch if carry set (C) bov => "11101", -- 29: branch if overflow set (O) -- Others --------------------------------------- nop => "11111" -- 31: no operation ); type t_flags is (Z, N, C, O); -- ALU flags (zero, negative, carry, overflow) type t_flag_arr is array (t_flags) of std_logic; -- register block constant RIDW : natural range 1 to DW := 3; -- register ID word width type t_regid is array(0 to 7) of std_logic_vector(RIDW-1 downto 0); constant reg : t_regid := ("000","001","010","011","100","101","110","111"); type t_regblk is array(0 to 7) of std_logic_vector(DW-1 downto 0); -- CPU address generation type t_pc_mode is (linear, abs_jump, rel_offset); -- addr calcultion modi type t_addr_exc is (no_err, lin_err, rel_err); -- address exceptions ----------------------------------------------------------------------------- -- global types ----------------------------------------------------------------------------- -- Master bus interface ----------------------------------------------------- type t_bus2cpu is record data : std_logic_vector(DW-1 downto 0); end record; type t_cpu2bus is record data : std_logic_vector(DW-1 downto 0); addr : std_logic_vector(AW-1 downto 0); rd_enb : std_logic; wr_enb : std_logic; end record; -- Read-only slave bus interface ------------------------------------------- type t_bus2ros is record addr : std_logic_vector(AWL-1 downto 0); rd_enb : std_logic; end record; type t_ros2bus is record data : std_logic_vector(DW-1 downto 0); end record; -- read/write slave bus interface ------------------------------------------- type t_bus2rws is record addr : std_logic_vector(AWL-1 downto 0); data : std_logic_vector(DW-1 downto 0); rd_enb : std_logic; -- use of this signal is optional, depending on slave wr_enb : std_logic; end record; type t_rws2bus is record data : std_logic_vector(DW-1 downto 0); end record; ----------------------------------------------------------------------------- -- CPU internal types ----------------------------------------------------------------------------- -- Control Unit / Register Block interface ---------------------------------- type t_ctr2reg is record src1 : std_logic_vector(RIDW-1 downto 0); src2 : std_logic_vector(RIDW-1 downto 0); dest : std_logic_vector(RIDW-1 downto 0); enb_res : std_logic; data : std_logic_vector(DW-1 downto 0); enb_data : std_logic; end record; type t_reg2ctr is record data : std_logic_vector(DW-1 downto 0); addr : std_logic_vector(AW-1 downto 0); end record; -- Control Unit / Program Counter interface -------------------------------- type t_ctr2prc is record enb : std_logic; mode : t_pc_mode; addr : std_logic_vector(AW-1 downto 0); end record; type t_prc2ctr is record pc : std_logic_vector(AW-1 downto 0); exc : t_addr_exc; end record; -- Control Unit / ALU interface --------------------------------------------- type t_ctr2alu is record op : std_logic_vector(OPAW-1 downto 0); -- operation imm : std_logic_vector(IOWW-1 downto 0); -- immediate operand enb : std_logic; -- enable flag update end record; type t_alu2ctr is record flag : t_flag_arr; end record; end package mcu_pkg; package body mcu_pkg is ----------------------------------------------------------------------------- -- Function Implementations ----------------------------------------------------------------------------- function i2slv(i : integer;w : positive) return std_logic_vector is begin return std_logic_vector(to_signed(i,w)); end function i2slv; function n2slv(n : natural;w : positive) return std_logic_vector is begin return std_logic_vector(to_unsigned(n,w)); end function n2slv; function iw_nop return std_logic_vector is variable v : std_logic_vector(DW-1 downto 0); begin for k in DW-1 downto DW-OPCW loop v(k) := OPC(nop)(k-DW+OPCW); end loop; for k in DW-OPCW-1 downto 0 loop v(k) := '0'; end loop; return v; end function iw_nop; end package body mcu_pkg;
gpl-3.0
e58993f4b57cace5c072d61a1db68850
0.499507
3.98394
false
false
false
false
GSimas/EEL5105
Eletr-Digital/Projeto Final/PROJETO COFRE FUNCIONANDO/buzzermusiquinha.vhd
1
4,659
-- megafunction wizard: %LPM_COUNTER% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: lpm_counter -- ============================================================ -- File Name: buzzermusiquinha.vhd -- Megafunction Name(s): -- lpm_counter -- -- Simulation Library Files(s): -- lpm -- ============================================================ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- -- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition -- ************************************************************ --Copyright (C) 1991-2010 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject --to the terms and conditions of the Altera Program License --Subscription Agreement, Altera MegaCore Function License --Agreement, or other applicable license agreement, including, --without limitation, that your use is for the sole purpose of --programming logic devices manufactured by Altera and sold by --Altera or its authorized distributors. Please refer to the --applicable agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY lpm; USE lpm.all; ENTITY buzzermusiquinha IS PORT ( clock : IN STD_LOGIC ; cout : OUT STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (29 DOWNTO 0) ); END buzzermusiquinha; ARCHITECTURE SYN OF buzzermusiquinha IS SIGNAL sub_wire0 : STD_LOGIC ; SIGNAL sub_wire1 : STD_LOGIC_VECTOR (29 DOWNTO 0); COMPONENT lpm_counter GENERIC ( lpm_direction : STRING; lpm_modulus : NATURAL; lpm_port_updown : STRING; lpm_type : STRING; lpm_width : NATURAL ); PORT ( clock : IN STD_LOGIC ; cout : OUT STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (29 DOWNTO 0) ); END COMPONENT; BEGIN cout <= sub_wire0; q <= sub_wire1(29 DOWNTO 0); lpm_counter_component : lpm_counter GENERIC MAP ( lpm_direction => "UP", lpm_modulus => 25000000, lpm_port_updown => "PORT_UNUSED", lpm_type => "LPM_COUNTER", lpm_width => 30 ) PORT MAP ( clock => clock, cout => sub_wire0, q => sub_wire1 ); END SYN; -- ============================================================ -- CNX file retrieval info -- ============================================================ -- Retrieval info: PRIVATE: ACLR NUMERIC "0" -- Retrieval info: PRIVATE: ALOAD NUMERIC "0" -- Retrieval info: PRIVATE: ASET NUMERIC "0" -- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1" -- Retrieval info: PRIVATE: CLK_EN NUMERIC "0" -- Retrieval info: PRIVATE: CNT_EN NUMERIC "0" -- Retrieval info: PRIVATE: CarryIn NUMERIC "0" -- Retrieval info: PRIVATE: CarryOut NUMERIC "1" -- Retrieval info: PRIVATE: Direction NUMERIC "0" -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" -- Retrieval info: PRIVATE: ModulusCounter NUMERIC "1" -- Retrieval info: PRIVATE: ModulusValue NUMERIC "25000000" -- Retrieval info: PRIVATE: SCLR NUMERIC "0" -- Retrieval info: PRIVATE: SLOAD NUMERIC "0" -- Retrieval info: PRIVATE: SSET NUMERIC "0" -- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: nBit NUMERIC "30" -- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP" -- Retrieval info: CONSTANT: LPM_MODULUS NUMERIC "25000000" -- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER" -- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "30" -- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock -- Retrieval info: USED_PORT: cout 0 0 0 0 OUTPUT NODEFVAL cout -- Retrieval info: USED_PORT: q 0 0 30 0 OUTPUT NODEFVAL q[29..0] -- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 -- Retrieval info: CONNECT: q 0 0 30 0 @q 0 0 30 0 -- Retrieval info: CONNECT: cout 0 0 0 0 @cout 0 0 0 0 -- Retrieval info: LIBRARY: lpm lpm.lpm_components.all -- Retrieval info: GEN_FILE: TYPE_NORMAL buzzermusiquinha.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL buzzermusiquinha.inc TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL buzzermusiquinha.cmp TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL buzzermusiquinha.bsf TRUE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL buzzermusiquinha_inst.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL buzzermusiquinha_waveforms.html TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL buzzermusiquinha_wave*.jpg FALSE -- Retrieval info: LIB_FILE: lpm
mit
438216bfa960816f624c2b55fd9ed76f
0.662803
3.64554
false
false
false
false
tghaefli/ADD
EDK/IVK_Repos/IVK_IPLib/pcores/sg_i2c_controller_s6_plbw_v1_01_a/hdl/vhdl/sg_i2c_controller_s6.vhd
1
187,229
-------------------------------------------------------------------------------- -- This file is owned and controlled by Xilinx and must be used -- -- solely for design, simulation, implementation and creation of -- -- design files limited to Xilinx devices or technologies. Use -- -- with non-Xilinx devices or technologies is expressly prohibited -- -- and immediately terminates your license. -- -- -- -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- -- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- -- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- -- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- -- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- -- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- -- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- -- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- -- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- -- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- -- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- -- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- -- FOR A PARTICULAR PURPOSE. -- -- -- -- Xilinx products are not intended for use in life support -- -- appliances, devices, or systems. Use in such applications are -- -- expressly prohibited. -- -- -- -- (c) Copyright 1995-2009 Xilinx, Inc. -- -- All rights reserved. -- -------------------------------------------------------------------------------- -- You must compile the wrapper file bmg_41_99d18de731b34188.vhd when simulating -- the core, bmg_41_99d18de731b34188. When compiling the wrapper file, be sure to -- reference the XilinxCoreLib VHDL simulation library. For detailed -- instructions, please refer to the "CORE Generator Help". -- The synthesis directives "translate_off/translate_on" specified -- below are supported by Xilinx, Mentor Graphics and Synplicity -- synthesis tools. Ensure they are correct for your synthesis tool(s). LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- synthesis translate_off Library XilinxCoreLib; -- synthesis translate_on ENTITY bmg_41_99d18de731b34188 IS port ( clka: IN std_logic; ena: IN std_logic; addra: IN std_logic_VECTOR(9 downto 0); douta: OUT std_logic_VECTOR(17 downto 0)); END bmg_41_99d18de731b34188; ARCHITECTURE bmg_41_99d18de731b34188_a OF bmg_41_99d18de731b34188 IS -- synthesis translate_off component wrapped_bmg_41_99d18de731b34188 port ( clka: IN std_logic; ena: IN std_logic; addra: IN std_logic_VECTOR(9 downto 0); douta: OUT std_logic_VECTOR(17 downto 0)); end component; -- Configuration specification for all : wrapped_bmg_41_99d18de731b34188 use entity XilinxCoreLib.blk_mem_gen_v4_1(behavioral) generic map( c_has_regceb => 0, c_has_regcea => 0, c_mem_type => 3, c_rstram_b => 0, c_rstram_a => 0, c_has_injecterr => 0, c_rst_type => "SYNC", c_prim_type => 1, c_read_width_b => 18, c_initb_val => "0", c_family => "spartan6", c_read_width_a => 18, c_disable_warn_bhv_coll => 0, c_use_softecc => 0, c_write_mode_b => "WRITE_FIRST", c_init_file_name => "bmg_41_99d18de731b34188.mif", c_write_mode_a => "WRITE_FIRST", c_mux_pipeline_stages => 0, c_has_softecc_output_regs_b => 0, c_has_softecc_output_regs_a => 0, c_has_mem_output_regs_b => 0, c_has_mem_output_regs_a => 0, c_load_init_file => 1, c_xdevicefamily => "spartan6", c_write_depth_b => 1024, c_write_depth_a => 1024, c_has_rstb => 0, c_has_rsta => 0, c_has_mux_output_regs_b => 0, c_inita_val => "0", c_has_mux_output_regs_a => 0, c_addra_width => 10, c_has_softecc_input_regs_b => 0, c_has_softecc_input_regs_a => 0, c_addrb_width => 10, c_default_data => "0", c_use_ecc => 0, c_algorithm => 1, c_disable_warn_bhv_range => 0, c_write_width_b => 18, c_write_width_a => 18, c_read_depth_b => 1024, c_read_depth_a => 1024, c_byte_size => 9, c_sim_collision_check => "ALL", c_common_clk => 0, c_wea_width => 1, c_has_enb => 0, c_web_width => 1, c_has_ena => 1, c_use_byte_web => 0, c_use_byte_wea => 0, c_rst_priority_b => "CE", c_rst_priority_a => "CE", c_use_default_data => 0); -- synthesis translate_on BEGIN -- synthesis translate_off U0 : wrapped_bmg_41_99d18de731b34188 port map ( clka => clka, ena => ena, addra => addra, douta => douta); -- synthesis translate_on END bmg_41_99d18de731b34188_a; ------------------------------------------------------------------- -- System Generator version 12.1 VHDL source file. -- -- Copyright(C) 2010 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2010 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; package conv_pkg is constant simulating : boolean := false -- synopsys translate_off or true -- synopsys translate_on ; constant xlUnsigned : integer := 1; constant xlSigned : integer := 2; constant xlWrap : integer := 1; constant xlSaturate : integer := 2; constant xlTruncate : integer := 1; constant xlRound : integer := 2; constant xlRoundBanker : integer := 3; constant xlAddMode : integer := 1; constant xlSubMode : integer := 2; attribute black_box : boolean; attribute syn_black_box : boolean; attribute fpga_dont_touch: string; attribute box_type : string; attribute keep : string; attribute syn_keep : boolean; function std_logic_vector_to_unsigned(inp : std_logic_vector) return unsigned; function unsigned_to_std_logic_vector(inp : unsigned) return std_logic_vector; function std_logic_vector_to_signed(inp : std_logic_vector) return signed; function signed_to_std_logic_vector(inp : signed) return std_logic_vector; function unsigned_to_signed(inp : unsigned) return signed; function signed_to_unsigned(inp : signed) return unsigned; function pos(inp : std_logic_vector; arith : INTEGER) return boolean; function all_same(inp: std_logic_vector) return boolean; function all_zeros(inp: std_logic_vector) return boolean; function is_point_five(inp: std_logic_vector) return boolean; function all_ones(inp: std_logic_vector) return boolean; function convert_type (inp : std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith, quantization, overflow : INTEGER) return std_logic_vector; function cast (inp : std_logic_vector; old_bin_pt, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector; function vec_slice (inp : std_logic_vector; upper, lower : INTEGER) return std_logic_vector; function s2u_slice (inp : signed; upper, lower : INTEGER) return unsigned; function u2u_slice (inp : unsigned; upper, lower : INTEGER) return unsigned; function s2s_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER) return signed; function u2s_cast (inp : unsigned; old_bin_pt, new_width, new_bin_pt : INTEGER) return signed; function s2u_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER) return unsigned; function u2u_cast (inp : unsigned; old_bin_pt, new_width, new_bin_pt : INTEGER) return unsigned; function u2v_cast (inp : unsigned; old_bin_pt, new_width, new_bin_pt : INTEGER) return std_logic_vector; function s2v_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER) return std_logic_vector; function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector; function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector; function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector; function max_signed(width : INTEGER) return std_logic_vector; function min_signed(width : INTEGER) return std_logic_vector; function saturation_arith(inp: std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector; function wrap_arith(inp: std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector; function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER; function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER) return INTEGER; function sign_ext(inp : std_logic_vector; new_width : INTEGER) return std_logic_vector; function zero_ext(inp : std_logic_vector; new_width : INTEGER) return std_logic_vector; function zero_ext(inp : std_logic; new_width : INTEGER) return std_logic_vector; function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER) return std_logic_vector; function align_input(inp : std_logic_vector; old_width, delta, new_arith, new_width: INTEGER) return std_logic_vector; function pad_LSB(inp : std_logic_vector; new_width: integer) return std_logic_vector; function pad_LSB(inp : std_logic_vector; new_width, arith : integer) return std_logic_vector; function max(L, R: INTEGER) return INTEGER; function min(L, R: INTEGER) return INTEGER; function "="(left,right: STRING) return boolean; function boolean_to_signed (inp : boolean; width: integer) return signed; function boolean_to_unsigned (inp : boolean; width: integer) return unsigned; function boolean_to_vector (inp : boolean) return std_logic_vector; function std_logic_to_vector (inp : std_logic) return std_logic_vector; function integer_to_std_logic_vector (inp : integer; width, arith : integer) return std_logic_vector; function std_logic_vector_to_integer (inp : std_logic_vector; arith : integer) return integer; function std_logic_to_integer(constant inp : std_logic := '0') return integer; function bin_string_element_to_std_logic_vector (inp : string; width, index : integer) return std_logic_vector; function bin_string_to_std_logic_vector (inp : string) return std_logic_vector; function hex_string_to_std_logic_vector (inp : string; width : integer) return std_logic_vector; function makeZeroBinStr (width : integer) return STRING; function and_reduce(inp: std_logic_vector) return std_logic; -- synopsys translate_off function is_binary_string_invalid (inp : string) return boolean; function is_binary_string_undefined (inp : string) return boolean; function is_XorU(inp : std_logic_vector) return boolean; function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer) return real; function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer) return real; function real_to_std_logic_vector (inp : real; width, bin_pt, arith : integer) return std_logic_vector; function real_string_to_std_logic_vector (inp : string; width, bin_pt, arith : integer) return std_logic_vector; constant display_precision : integer := 20; function real_to_string (inp : real) return string; function valid_bin_string(inp : string) return boolean; function std_logic_vector_to_bin_string(inp : std_logic_vector) return string; function std_logic_to_bin_string(inp : std_logic) return string; function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer) return string; function real_to_bin_string(inp : real; width, bin_pt, arith : integer) return string; type stdlogic_to_char_t is array(std_logic) of character; constant to_char : stdlogic_to_char_t := ( 'U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z', 'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-'); -- synopsys translate_on end conv_pkg; package body conv_pkg is function std_logic_vector_to_unsigned(inp : std_logic_vector) return unsigned is begin return unsigned (inp); end; function unsigned_to_std_logic_vector(inp : unsigned) return std_logic_vector is begin return std_logic_vector(inp); end; function std_logic_vector_to_signed(inp : std_logic_vector) return signed is begin return signed (inp); end; function signed_to_std_logic_vector(inp : signed) return std_logic_vector is begin return std_logic_vector(inp); end; function unsigned_to_signed (inp : unsigned) return signed is begin return signed(std_logic_vector(inp)); end; function signed_to_unsigned (inp : signed) return unsigned is begin return unsigned(std_logic_vector(inp)); end; function pos(inp : std_logic_vector; arith : INTEGER) return boolean is constant width : integer := inp'length; variable vec : std_logic_vector(width-1 downto 0); begin vec := inp; if arith = xlUnsigned then return true; else if vec(width-1) = '0' then return true; else return false; end if; end if; return true; end; function max_signed(width : INTEGER) return std_logic_vector is variable ones : std_logic_vector(width-2 downto 0); variable result : std_logic_vector(width-1 downto 0); begin ones := (others => '1'); result(width-1) := '0'; result(width-2 downto 0) := ones; return result; end; function min_signed(width : INTEGER) return std_logic_vector is variable zeros : std_logic_vector(width-2 downto 0); variable result : std_logic_vector(width-1 downto 0); begin zeros := (others => '0'); result(width-1) := '1'; result(width-2 downto 0) := zeros; return result; end; function and_reduce(inp: std_logic_vector) return std_logic is variable result: std_logic; constant width : integer := inp'length; variable vec : std_logic_vector(width-1 downto 0); begin vec := inp; result := vec(0); if width > 1 then for i in 1 to width-1 loop result := result and vec(i); end loop; end if; return result; end; function all_same(inp: std_logic_vector) return boolean is variable result: boolean; constant width : integer := inp'length; variable vec : std_logic_vector(width-1 downto 0); begin vec := inp; result := true; if width > 0 then for i in 1 to width-1 loop if vec(i) /= vec(0) then result := false; end if; end loop; end if; return result; end; function all_zeros(inp: std_logic_vector) return boolean is constant width : integer := inp'length; variable vec : std_logic_vector(width-1 downto 0); variable zero : std_logic_vector(width-1 downto 0); variable result : boolean; begin zero := (others => '0'); vec := inp; -- synopsys translate_off if (is_XorU(vec)) then return false; end if; -- synopsys translate_on if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(zero)) then result := true; else result := false; end if; return result; end; function is_point_five(inp: std_logic_vector) return boolean is constant width : integer := inp'length; variable vec : std_logic_vector(width-1 downto 0); variable result : boolean; begin vec := inp; -- synopsys translate_off if (is_XorU(vec)) then return false; end if; -- synopsys translate_on if (width > 1) then if ((vec(width-1) = '1') and (all_zeros(vec(width-2 downto 0)) = true)) then result := true; else result := false; end if; else if (vec(width-1) = '1') then result := true; else result := false; end if; end if; return result; end; function all_ones(inp: std_logic_vector) return boolean is constant width : integer := inp'length; variable vec : std_logic_vector(width-1 downto 0); variable one : std_logic_vector(width-1 downto 0); variable result : boolean; begin one := (others => '1'); vec := inp; -- synopsys translate_off if (is_XorU(vec)) then return false; end if; -- synopsys translate_on if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(one)) then result := true; else result := false; end if; return result; end; function full_precision_num_width(quantization, overflow, old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return integer is variable result : integer; begin result := old_width + 2; return result; end; function quantized_num_width(quantization, overflow, old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return integer is variable right_of_dp, left_of_dp, result : integer; begin right_of_dp := max(new_bin_pt, old_bin_pt); left_of_dp := max((new_width - new_bin_pt), (old_width - old_bin_pt)); result := (old_width + 2) + (new_bin_pt - old_bin_pt); return result; end; function convert_type (inp : std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith, quantization, overflow : INTEGER) return std_logic_vector is constant fp_width : integer := full_precision_num_width(quantization, overflow, old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith); constant fp_bin_pt : integer := old_bin_pt; constant fp_arith : integer := old_arith; variable full_precision_result : std_logic_vector(fp_width-1 downto 0); constant q_width : integer := quantized_num_width(quantization, overflow, old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith); constant q_bin_pt : integer := new_bin_pt; constant q_arith : integer := old_arith; variable quantized_result : std_logic_vector(q_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); begin result := (others => '0'); full_precision_result := cast(inp, old_bin_pt, fp_width, fp_bin_pt, fp_arith); if (quantization = xlRound) then quantized_result := round_towards_inf(full_precision_result, fp_width, fp_bin_pt, fp_arith, q_width, q_bin_pt, q_arith); elsif (quantization = xlRoundBanker) then quantized_result := round_towards_even(full_precision_result, fp_width, fp_bin_pt, fp_arith, q_width, q_bin_pt, q_arith); else quantized_result := trunc(full_precision_result, fp_width, fp_bin_pt, fp_arith, q_width, q_bin_pt, q_arith); end if; if (overflow = xlSaturate) then result := saturation_arith(quantized_result, q_width, q_bin_pt, q_arith, new_width, new_bin_pt, new_arith); else result := wrap_arith(quantized_result, q_width, q_bin_pt, q_arith, new_width, new_bin_pt, new_arith); end if; return result; end; function cast (inp : std_logic_vector; old_bin_pt, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector is constant old_width : integer := inp'length; constant left_of_dp : integer := (new_width - new_bin_pt) - (old_width - old_bin_pt); constant right_of_dp : integer := (new_bin_pt - old_bin_pt); variable vec : std_logic_vector(old_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); variable j : integer; begin vec := inp; for i in new_width-1 downto 0 loop j := i - right_of_dp; if ( j > old_width-1) then if (new_arith = xlUnsigned) then result(i) := '0'; else result(i) := vec(old_width-1); end if; elsif ( j >= 0) then result(i) := vec(j); else result(i) := '0'; end if; end loop; return result; end; function vec_slice (inp : std_logic_vector; upper, lower : INTEGER) return std_logic_vector is begin return inp(upper downto lower); end; function s2u_slice (inp : signed; upper, lower : INTEGER) return unsigned is begin return unsigned(vec_slice(std_logic_vector(inp), upper, lower)); end; function u2u_slice (inp : unsigned; upper, lower : INTEGER) return unsigned is begin return unsigned(vec_slice(std_logic_vector(inp), upper, lower)); end; function s2s_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER) return signed is begin return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned)); end; function s2u_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER) return unsigned is begin return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned)); end; function u2s_cast (inp : unsigned; old_bin_pt, new_width, new_bin_pt : INTEGER) return signed is begin return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned)); end; function u2u_cast (inp : unsigned; old_bin_pt, new_width, new_bin_pt : INTEGER) return unsigned is begin return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned)); end; function u2v_cast (inp : unsigned; old_bin_pt, new_width, new_bin_pt : INTEGER) return std_logic_vector is begin return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned); end; function s2v_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER) return std_logic_vector is begin return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned); end; function boolean_to_signed (inp : boolean; width : integer) return signed is variable result : signed(width - 1 downto 0); begin result := (others => '0'); if inp then result(0) := '1'; else result(0) := '0'; end if; return result; end; function boolean_to_unsigned (inp : boolean; width : integer) return unsigned is variable result : unsigned(width - 1 downto 0); begin result := (others => '0'); if inp then result(0) := '1'; else result(0) := '0'; end if; return result; end; function boolean_to_vector (inp : boolean) return std_logic_vector is variable result : std_logic_vector(1 - 1 downto 0); begin result := (others => '0'); if inp then result(0) := '1'; else result(0) := '0'; end if; return result; end; function std_logic_to_vector (inp : std_logic) return std_logic_vector is variable result : std_logic_vector(1 - 1 downto 0); begin result(0) := inp; return result; end; function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector is constant right_of_dp : integer := (old_bin_pt - new_bin_pt); variable vec : std_logic_vector(old_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); begin vec := inp; if right_of_dp >= 0 then if new_arith = xlUnsigned then result := zero_ext(vec(old_width-1 downto right_of_dp), new_width); else result := sign_ext(vec(old_width-1 downto right_of_dp), new_width); end if; else if new_arith = xlUnsigned then result := zero_ext(pad_LSB(vec, old_width + abs(right_of_dp)), new_width); else result := sign_ext(pad_LSB(vec, old_width + abs(right_of_dp)), new_width); end if; end if; return result; end; function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector is constant right_of_dp : integer := (old_bin_pt - new_bin_pt); constant expected_new_width : integer := old_width - right_of_dp + 1; variable vec : std_logic_vector(old_width-1 downto 0); variable one_or_zero : std_logic_vector(new_width-1 downto 0); variable truncated_val : std_logic_vector(new_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); begin vec := inp; if right_of_dp >= 0 then if new_arith = xlUnsigned then truncated_val := zero_ext(vec(old_width-1 downto right_of_dp), new_width); else truncated_val := sign_ext(vec(old_width-1 downto right_of_dp), new_width); end if; else if new_arith = xlUnsigned then truncated_val := zero_ext(pad_LSB(vec, old_width + abs(right_of_dp)), new_width); else truncated_val := sign_ext(pad_LSB(vec, old_width + abs(right_of_dp)), new_width); end if; end if; one_or_zero := (others => '0'); if (new_arith = xlSigned) then if (vec(old_width-1) = '0') then one_or_zero(0) := '1'; end if; if (right_of_dp >= 2) and (right_of_dp <= old_width) then if (all_zeros(vec(right_of_dp-2 downto 0)) = false) then one_or_zero(0) := '1'; end if; end if; if (right_of_dp >= 1) and (right_of_dp <= old_width) then if vec(right_of_dp-1) = '0' then one_or_zero(0) := '0'; end if; else one_or_zero(0) := '0'; end if; else if (right_of_dp >= 1) and (right_of_dp <= old_width) then one_or_zero(0) := vec(right_of_dp-1); end if; end if; if new_arith = xlSigned then result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) + std_logic_vector_to_signed(one_or_zero)); else result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) + std_logic_vector_to_unsigned(one_or_zero)); end if; return result; end; function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector is constant right_of_dp : integer := (old_bin_pt - new_bin_pt); constant expected_new_width : integer := old_width - right_of_dp + 1; variable vec : std_logic_vector(old_width-1 downto 0); variable one_or_zero : std_logic_vector(new_width-1 downto 0); variable truncated_val : std_logic_vector(new_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); begin vec := inp; if right_of_dp >= 0 then if new_arith = xlUnsigned then truncated_val := zero_ext(vec(old_width-1 downto right_of_dp), new_width); else truncated_val := sign_ext(vec(old_width-1 downto right_of_dp), new_width); end if; else if new_arith = xlUnsigned then truncated_val := zero_ext(pad_LSB(vec, old_width + abs(right_of_dp)), new_width); else truncated_val := sign_ext(pad_LSB(vec, old_width + abs(right_of_dp)), new_width); end if; end if; one_or_zero := (others => '0'); if (right_of_dp >= 1) and (right_of_dp <= old_width) then if (is_point_five(vec(right_of_dp-1 downto 0)) = false) then one_or_zero(0) := vec(right_of_dp-1); else one_or_zero(0) := vec(right_of_dp); end if; end if; if new_arith = xlSigned then result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) + std_logic_vector_to_signed(one_or_zero)); else result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) + std_logic_vector_to_unsigned(one_or_zero)); end if; return result; end; function saturation_arith(inp: std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector is constant left_of_dp : integer := (old_width - old_bin_pt) - (new_width - new_bin_pt); variable vec : std_logic_vector(old_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); variable overflow : boolean; begin vec := inp; overflow := true; result := (others => '0'); if (new_width >= old_width) then overflow := false; end if; if ((old_arith = xlSigned and new_arith = xlSigned) and (old_width > new_width)) then if all_same(vec(old_width-1 downto new_width-1)) then overflow := false; end if; end if; if (old_arith = xlSigned and new_arith = xlUnsigned) then if (old_width > new_width) then if all_zeros(vec(old_width-1 downto new_width)) then overflow := false; end if; else if (old_width = new_width) then if (vec(new_width-1) = '0') then overflow := false; end if; end if; end if; end if; if (old_arith = xlUnsigned and new_arith = xlUnsigned) then if (old_width > new_width) then if all_zeros(vec(old_width-1 downto new_width)) then overflow := false; end if; else if (old_width = new_width) then overflow := false; end if; end if; end if; if ((old_arith = xlUnsigned and new_arith = xlSigned) and (old_width > new_width)) then if all_same(vec(old_width-1 downto new_width-1)) then overflow := false; end if; end if; if overflow then if new_arith = xlSigned then if vec(old_width-1) = '0' then result := max_signed(new_width); else result := min_signed(new_width); end if; else if ((old_arith = xlSigned) and vec(old_width-1) = '1') then result := (others => '0'); else result := (others => '1'); end if; end if; else if (old_arith = xlSigned) and (new_arith = xlUnsigned) then if (vec(old_width-1) = '1') then vec := (others => '0'); end if; end if; if new_width <= old_width then result := vec(new_width-1 downto 0); else if new_arith = xlUnsigned then result := zero_ext(vec, new_width); else result := sign_ext(vec, new_width); end if; end if; end if; return result; end; function wrap_arith(inp: std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector is variable result : std_logic_vector(new_width-1 downto 0); variable result_arith : integer; begin if (old_arith = xlSigned) and (new_arith = xlUnsigned) then result_arith := xlSigned; end if; result := cast(inp, old_bin_pt, new_width, new_bin_pt, result_arith); return result; end; function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER is begin return max(a_bin_pt, b_bin_pt); end; function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER) return INTEGER is begin return max(a_width - a_bin_pt, b_width - b_bin_pt); end; function pad_LSB(inp : std_logic_vector; new_width: integer) return STD_LOGIC_VECTOR is constant orig_width : integer := inp'length; variable vec : std_logic_vector(orig_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); variable pos : integer; constant pad_pos : integer := new_width - orig_width - 1; begin vec := inp; pos := new_width-1; if (new_width >= orig_width) then for i in orig_width-1 downto 0 loop result(pos) := vec(i); pos := pos - 1; end loop; if pad_pos >= 0 then for i in pad_pos downto 0 loop result(i) := '0'; end loop; end if; end if; return result; end; function sign_ext(inp : std_logic_vector; new_width : INTEGER) return std_logic_vector is constant old_width : integer := inp'length; variable vec : std_logic_vector(old_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); begin vec := inp; if new_width >= old_width then result(old_width-1 downto 0) := vec; if new_width-1 >= old_width then for i in new_width-1 downto old_width loop result(i) := vec(old_width-1); end loop; end if; else result(new_width-1 downto 0) := vec(new_width-1 downto 0); end if; return result; end; function zero_ext(inp : std_logic_vector; new_width : INTEGER) return std_logic_vector is constant old_width : integer := inp'length; variable vec : std_logic_vector(old_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); begin vec := inp; if new_width >= old_width then result(old_width-1 downto 0) := vec; if new_width-1 >= old_width then for i in new_width-1 downto old_width loop result(i) := '0'; end loop; end if; else result(new_width-1 downto 0) := vec(new_width-1 downto 0); end if; return result; end; function zero_ext(inp : std_logic; new_width : INTEGER) return std_logic_vector is variable result : std_logic_vector(new_width-1 downto 0); begin result(0) := inp; for i in new_width-1 downto 1 loop result(i) := '0'; end loop; return result; end; function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER) return std_logic_vector is constant orig_width : integer := inp'length; variable vec : std_logic_vector(orig_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); begin vec := inp; if arith = xlUnsigned then result := zero_ext(vec, new_width); else result := sign_ext(vec, new_width); end if; return result; end; function pad_LSB(inp : std_logic_vector; new_width, arith: integer) return STD_LOGIC_VECTOR is constant orig_width : integer := inp'length; variable vec : std_logic_vector(orig_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); variable pos : integer; begin vec := inp; pos := new_width-1; if (arith = xlUnsigned) then result(pos) := '0'; pos := pos - 1; else result(pos) := vec(orig_width-1); pos := pos - 1; end if; if (new_width >= orig_width) then for i in orig_width-1 downto 0 loop result(pos) := vec(i); pos := pos - 1; end loop; if pos >= 0 then for i in pos downto 0 loop result(i) := '0'; end loop; end if; end if; return result; end; function align_input(inp : std_logic_vector; old_width, delta, new_arith, new_width: INTEGER) return std_logic_vector is variable vec : std_logic_vector(old_width-1 downto 0); variable padded_inp : std_logic_vector((old_width + delta)-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); begin vec := inp; if delta > 0 then padded_inp := pad_LSB(vec, old_width+delta); result := extend_MSB(padded_inp, new_width, new_arith); else result := extend_MSB(vec, new_width, new_arith); end if; return result; end; function max(L, R: INTEGER) return INTEGER is begin if L > R then return L; else return R; end if; end; function min(L, R: INTEGER) return INTEGER is begin if L < R then return L; else return R; end if; end; function "="(left,right: STRING) return boolean is begin if (left'length /= right'length) then return false; else test : for i in 1 to left'length loop if left(i) /= right(i) then return false; end if; end loop test; return true; end if; end; -- synopsys translate_off function is_binary_string_invalid (inp : string) return boolean is variable vec : string(1 to inp'length); variable result : boolean; begin vec := inp; result := false; for i in 1 to vec'length loop if ( vec(i) = 'X' ) then result := true; end if; end loop; return result; end; function is_binary_string_undefined (inp : string) return boolean is variable vec : string(1 to inp'length); variable result : boolean; begin vec := inp; result := false; for i in 1 to vec'length loop if ( vec(i) = 'U' ) then result := true; end if; end loop; return result; end; function is_XorU(inp : std_logic_vector) return boolean is constant width : integer := inp'length; variable vec : std_logic_vector(width-1 downto 0); variable result : boolean; begin vec := inp; result := false; for i in 0 to width-1 loop if (vec(i) = 'U') or (vec(i) = 'X') then result := true; end if; end loop; return result; end; function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer) return real is variable vec : std_logic_vector(inp'length-1 downto 0); variable result, shift_val, undefined_real : real; variable neg_num : boolean; begin vec := inp; result := 0.0; neg_num := false; if vec(inp'length-1) = '1' then neg_num := true; end if; for i in 0 to inp'length-1 loop if vec(i) = 'U' or vec(i) = 'X' then return undefined_real; end if; if arith = xlSigned then if neg_num then if vec(i) = '0' then result := result + 2.0**i; end if; else if vec(i) = '1' then result := result + 2.0**i; end if; end if; else if vec(i) = '1' then result := result + 2.0**i; end if; end if; end loop; if arith = xlSigned then if neg_num then result := result + 1.0; result := result * (-1.0); end if; end if; shift_val := 2.0**(-1*bin_pt); result := result * shift_val; return result; end; function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer) return real is variable result : real := 0.0; begin if inp = '1' then result := 1.0; end if; if arith = xlSigned then assert false report "It doesn't make sense to convert a 1 bit number to a signed real."; end if; return result; end; -- synopsys translate_on function integer_to_std_logic_vector (inp : integer; width, arith : integer) return std_logic_vector is variable result : std_logic_vector(width-1 downto 0); variable unsigned_val : unsigned(width-1 downto 0); variable signed_val : signed(width-1 downto 0); begin if (arith = xlSigned) then signed_val := to_signed(inp, width); result := signed_to_std_logic_vector(signed_val); else unsigned_val := to_unsigned(inp, width); result := unsigned_to_std_logic_vector(unsigned_val); end if; return result; end; function std_logic_vector_to_integer (inp : std_logic_vector; arith : integer) return integer is constant width : integer := inp'length; variable unsigned_val : unsigned(width-1 downto 0); variable signed_val : signed(width-1 downto 0); variable result : integer; begin if (arith = xlSigned) then signed_val := std_logic_vector_to_signed(inp); result := to_integer(signed_val); else unsigned_val := std_logic_vector_to_unsigned(inp); result := to_integer(unsigned_val); end if; return result; end; function std_logic_to_integer(constant inp : std_logic := '0') return integer is begin if inp = '1' then return 1; else return 0; end if; end; function makeZeroBinStr (width : integer) return STRING is variable result : string(1 to width+3); begin result(1) := '0'; result(2) := 'b'; for i in 3 to width+2 loop result(i) := '0'; end loop; result(width+3) := '.'; return result; end; -- synopsys translate_off function real_string_to_std_logic_vector (inp : string; width, bin_pt, arith : integer) return std_logic_vector is variable result : std_logic_vector(width-1 downto 0); begin result := (others => '0'); return result; end; function real_to_std_logic_vector (inp : real; width, bin_pt, arith : integer) return std_logic_vector is variable real_val : real; variable int_val : integer; variable result : std_logic_vector(width-1 downto 0) := (others => '0'); variable unsigned_val : unsigned(width-1 downto 0) := (others => '0'); variable signed_val : signed(width-1 downto 0) := (others => '0'); begin real_val := inp; int_val := integer(real_val * 2.0**(bin_pt)); if (arith = xlSigned) then signed_val := to_signed(int_val, width); result := signed_to_std_logic_vector(signed_val); else unsigned_val := to_unsigned(int_val, width); result := unsigned_to_std_logic_vector(unsigned_val); end if; return result; end; -- synopsys translate_on function valid_bin_string (inp : string) return boolean is variable vec : string(1 to inp'length); begin vec := inp; if (vec(1) = '0' and vec(2) = 'b') then return true; else return false; end if; end; function hex_string_to_std_logic_vector(inp: string; width : integer) return std_logic_vector is constant strlen : integer := inp'LENGTH; variable result : std_logic_vector(width-1 downto 0); variable bitval : std_logic_vector((strlen*4)-1 downto 0); variable posn : integer; variable ch : character; variable vec : string(1 to strlen); begin vec := inp; result := (others => '0'); posn := (strlen*4)-1; for i in 1 to strlen loop ch := vec(i); case ch is when '0' => bitval(posn downto posn-3) := "0000"; when '1' => bitval(posn downto posn-3) := "0001"; when '2' => bitval(posn downto posn-3) := "0010"; when '3' => bitval(posn downto posn-3) := "0011"; when '4' => bitval(posn downto posn-3) := "0100"; when '5' => bitval(posn downto posn-3) := "0101"; when '6' => bitval(posn downto posn-3) := "0110"; when '7' => bitval(posn downto posn-3) := "0111"; when '8' => bitval(posn downto posn-3) := "1000"; when '9' => bitval(posn downto posn-3) := "1001"; when 'A' | 'a' => bitval(posn downto posn-3) := "1010"; when 'B' | 'b' => bitval(posn downto posn-3) := "1011"; when 'C' | 'c' => bitval(posn downto posn-3) := "1100"; when 'D' | 'd' => bitval(posn downto posn-3) := "1101"; when 'E' | 'e' => bitval(posn downto posn-3) := "1110"; when 'F' | 'f' => bitval(posn downto posn-3) := "1111"; when others => bitval(posn downto posn-3) := "XXXX"; -- synopsys translate_off ASSERT false REPORT "Invalid hex value" SEVERITY ERROR; -- synopsys translate_on end case; posn := posn - 4; end loop; if (width <= strlen*4) then result := bitval(width-1 downto 0); else result((strlen*4)-1 downto 0) := bitval; end if; return result; end; function bin_string_to_std_logic_vector (inp : string) return std_logic_vector is variable pos : integer; variable vec : string(1 to inp'length); variable result : std_logic_vector(inp'length-1 downto 0); begin vec := inp; pos := inp'length-1; result := (others => '0'); for i in 1 to vec'length loop -- synopsys translate_off if (pos < 0) and (vec(i) = '0' or vec(i) = '1' or vec(i) = 'X' or vec(i) = 'U') then assert false report "Input string is larger than output std_logic_vector. Truncating output."; return result; end if; -- synopsys translate_on if vec(i) = '0' then result(pos) := '0'; pos := pos - 1; end if; if vec(i) = '1' then result(pos) := '1'; pos := pos - 1; end if; -- synopsys translate_off if (vec(i) = 'X' or vec(i) = 'U') then result(pos) := 'U'; pos := pos - 1; end if; -- synopsys translate_on end loop; return result; end; function bin_string_element_to_std_logic_vector (inp : string; width, index : integer) return std_logic_vector is constant str_width : integer := width + 4; constant inp_len : integer := inp'length; constant num_elements : integer := (inp_len + 1)/str_width; constant reverse_index : integer := (num_elements-1) - index; variable left_pos : integer; variable right_pos : integer; variable vec : string(1 to inp'length); variable result : std_logic_vector(width-1 downto 0); begin vec := inp; result := (others => '0'); if (reverse_index = 0) and (reverse_index < num_elements) and (inp_len-3 >= width) then left_pos := 1; right_pos := width + 3; result := bin_string_to_std_logic_vector(vec(left_pos to right_pos)); end if; if (reverse_index > 0) and (reverse_index < num_elements) and (inp_len-3 >= width) then left_pos := (reverse_index * str_width) + 1; right_pos := left_pos + width + 2; result := bin_string_to_std_logic_vector(vec(left_pos to right_pos)); end if; return result; end; -- synopsys translate_off function std_logic_vector_to_bin_string(inp : std_logic_vector) return string is variable vec : std_logic_vector(1 to inp'length); variable result : string(vec'range); begin vec := inp; for i in vec'range loop result(i) := to_char(vec(i)); end loop; return result; end; function std_logic_to_bin_string(inp : std_logic) return string is variable result : string(1 to 3); begin result(1) := '0'; result(2) := 'b'; result(3) := to_char(inp); return result; end; function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer) return string is variable width : integer := inp'length; variable vec : std_logic_vector(width-1 downto 0); variable str_pos : integer; variable result : string(1 to width+3); begin vec := inp; str_pos := 1; result(str_pos) := '0'; str_pos := 2; result(str_pos) := 'b'; str_pos := 3; for i in width-1 downto 0 loop if (((width+3) - bin_pt) = str_pos) then result(str_pos) := '.'; str_pos := str_pos + 1; end if; result(str_pos) := to_char(vec(i)); str_pos := str_pos + 1; end loop; if (bin_pt = 0) then result(str_pos) := '.'; end if; return result; end; function real_to_bin_string(inp : real; width, bin_pt, arith : integer) return string is variable result : string(1 to width); variable vec : std_logic_vector(width-1 downto 0); begin vec := real_to_std_logic_vector(inp, width, bin_pt, arith); result := std_logic_vector_to_bin_string(vec); return result; end; function real_to_string (inp : real) return string is variable result : string(1 to display_precision) := (others => ' '); begin result(real'image(inp)'range) := real'image(inp); return result; end; -- synopsys translate_on end conv_pkg; ------------------------------------------------------------------- -- System Generator version 12.1 VHDL source file. -- -- Copyright(C) 2010 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2010 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- -- synopsys translate_off library unisim; use unisim.vcomponents.all; -- synopsys translate_on library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity srl17e is generic (width : integer:=16; latency : integer :=8); port (clk : in std_logic; ce : in std_logic; d : in std_logic_vector(width-1 downto 0); q : out std_logic_vector(width-1 downto 0)); end srl17e; architecture structural of srl17e is component SRL16E port (D : in STD_ULOGIC; CE : in STD_ULOGIC; CLK : in STD_ULOGIC; A0 : in STD_ULOGIC; A1 : in STD_ULOGIC; A2 : in STD_ULOGIC; A3 : in STD_ULOGIC; Q : out STD_ULOGIC); end component; attribute syn_black_box of SRL16E : component is true; attribute fpga_dont_touch of SRL16E : component is "true"; component FDE port( Q : out STD_ULOGIC; D : in STD_ULOGIC; C : in STD_ULOGIC; CE : in STD_ULOGIC); end component; attribute syn_black_box of FDE : component is true; attribute fpga_dont_touch of FDE : component is "true"; constant a : std_logic_vector(4 downto 0) := integer_to_std_logic_vector(latency-2,5,xlSigned); signal d_delayed : std_logic_vector(width-1 downto 0); signal srl16_out : std_logic_vector(width-1 downto 0); begin d_delayed <= d after 200 ps; reg_array : for i in 0 to width-1 generate srl16_used: if latency > 1 generate u1 : srl16e port map(clk => clk, d => d_delayed(i), q => srl16_out(i), ce => ce, a0 => a(0), a1 => a(1), a2 => a(2), a3 => a(3)); end generate; srl16_not_used: if latency <= 1 generate srl16_out(i) <= d_delayed(i); end generate; fde_used: if latency /= 0 generate u2 : fde port map(c => clk, d => srl16_out(i), q => q(i), ce => ce); end generate; fde_not_used: if latency = 0 generate q(i) <= srl16_out(i); end generate; end generate; end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity synth_reg is generic (width : integer := 8; latency : integer := 1); port (i : in std_logic_vector(width-1 downto 0); ce : in std_logic; clr : in std_logic; clk : in std_logic; o : out std_logic_vector(width-1 downto 0)); end synth_reg; architecture structural of synth_reg is component srl17e generic (width : integer:=16; latency : integer :=8); port (clk : in std_logic; ce : in std_logic; d : in std_logic_vector(width-1 downto 0); q : out std_logic_vector(width-1 downto 0)); end component; function calc_num_srl17es (latency : integer) return integer is variable remaining_latency : integer; variable result : integer; begin result := latency / 17; remaining_latency := latency - (result * 17); if (remaining_latency /= 0) then result := result + 1; end if; return result; end; constant complete_num_srl17es : integer := latency / 17; constant num_srl17es : integer := calc_num_srl17es(latency); constant remaining_latency : integer := latency - (complete_num_srl17es * 17); type register_array is array (num_srl17es downto 0) of std_logic_vector(width-1 downto 0); signal z : register_array; begin z(0) <= i; complete_ones : if complete_num_srl17es > 0 generate srl17e_array: for i in 0 to complete_num_srl17es-1 generate delay_comp : srl17e generic map (width => width, latency => 17) port map (clk => clk, ce => ce, d => z(i), q => z(i+1)); end generate; end generate; partial_one : if remaining_latency > 0 generate last_srl17e : srl17e generic map (width => width, latency => remaining_latency) port map (clk => clk, ce => ce, d => z(num_srl17es-1), q => z(num_srl17es)); end generate; o <= z(num_srl17es); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity synth_reg_reg is generic (width : integer := 8; latency : integer := 1); port (i : in std_logic_vector(width-1 downto 0); ce : in std_logic; clr : in std_logic; clk : in std_logic; o : out std_logic_vector(width-1 downto 0)); end synth_reg_reg; architecture behav of synth_reg_reg is type reg_array_type is array (latency-1 downto 0) of std_logic_vector(width -1 downto 0); signal reg_bank : reg_array_type := (others => (others => '0')); signal reg_bank_in : reg_array_type := (others => (others => '0')); attribute syn_allow_retiming : boolean; attribute syn_srlstyle : string; attribute syn_allow_retiming of reg_bank : signal is true; attribute syn_allow_retiming of reg_bank_in : signal is true; attribute syn_srlstyle of reg_bank : signal is "registers"; attribute syn_srlstyle of reg_bank_in : signal is "registers"; begin latency_eq_0: if latency = 0 generate o <= i; end generate latency_eq_0; latency_gt_0: if latency >= 1 generate o <= reg_bank(latency-1); reg_bank_in(0) <= i; loop_gen: for idx in latency-2 downto 0 generate reg_bank_in(idx+1) <= reg_bank(idx); end generate loop_gen; sync_loop: for sync_idx in latency-1 downto 0 generate sync_proc: process (clk) begin if clk'event and clk = '1' then if ce = '1' then reg_bank(sync_idx) <= reg_bank_in(sync_idx); end if; end if; end process sync_proc; end generate sync_loop; end generate latency_gt_0; end behav; ------------------------------------------------------------------- -- System Generator version 12.1 VHDL source file. -- -- Copyright(C) 2010 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2010 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- -- synopsys translate_off library unisim; use unisim.vcomponents.all; -- synopsys translate_on library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity single_reg_w_init is generic ( width: integer := 8; init_index: integer := 0; init_value: bit_vector := b"0000" ); port ( i: in std_logic_vector(width - 1 downto 0); ce: in std_logic; clr: in std_logic; clk: in std_logic; o: out std_logic_vector(width - 1 downto 0) ); end single_reg_w_init; architecture structural of single_reg_w_init is function build_init_const(width: integer; init_index: integer; init_value: bit_vector) return std_logic_vector is variable result: std_logic_vector(width - 1 downto 0); begin if init_index = 0 then result := (others => '0'); elsif init_index = 1 then result := (others => '0'); result(0) := '1'; else result := to_stdlogicvector(init_value); end if; return result; end; component fdre port ( q: out std_ulogic; d: in std_ulogic; c: in std_ulogic; ce: in std_ulogic; r: in std_ulogic ); end component; attribute syn_black_box of fdre: component is true; attribute fpga_dont_touch of fdre: component is "true"; component fdse port ( q: out std_ulogic; d: in std_ulogic; c: in std_ulogic; ce: in std_ulogic; s: in std_ulogic ); end component; attribute syn_black_box of fdse: component is true; attribute fpga_dont_touch of fdse: component is "true"; constant init_const: std_logic_vector(width - 1 downto 0) := build_init_const(width, init_index, init_value); begin fd_prim_array: for index in 0 to width - 1 generate bit_is_0: if (init_const(index) = '0') generate fdre_comp: fdre port map ( c => clk, d => i(index), q => o(index), ce => ce, r => clr ); end generate; bit_is_1: if (init_const(index) = '1') generate fdse_comp: fdse port map ( c => clk, d => i(index), q => o(index), ce => ce, s => clr ); end generate; end generate; end architecture structural; -- synopsys translate_off library unisim; use unisim.vcomponents.all; -- synopsys translate_on library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity synth_reg_w_init is generic ( width: integer := 8; init_index: integer := 0; init_value: bit_vector := b"0000"; latency: integer := 1 ); port ( i: in std_logic_vector(width - 1 downto 0); ce: in std_logic; clr: in std_logic; clk: in std_logic; o: out std_logic_vector(width - 1 downto 0) ); end synth_reg_w_init; architecture structural of synth_reg_w_init is component single_reg_w_init generic ( width: integer := 8; init_index: integer := 0; init_value: bit_vector := b"0000" ); port ( i: in std_logic_vector(width - 1 downto 0); ce: in std_logic; clr: in std_logic; clk: in std_logic; o: out std_logic_vector(width - 1 downto 0) ); end component; signal dly_i: std_logic_vector((latency + 1) * width - 1 downto 0); signal dly_clr: std_logic; begin latency_eq_0: if (latency = 0) generate o <= i; end generate; latency_gt_0: if (latency >= 1) generate dly_i((latency + 1) * width - 1 downto latency * width) <= i after 200 ps; dly_clr <= clr after 200 ps; fd_array: for index in latency downto 1 generate reg_comp: single_reg_w_init generic map ( width => width, init_index => init_index, init_value => init_value ) port map ( clk => clk, i => dly_i((index + 1) * width - 1 downto index * width), o => dly_i(index * width - 1 downto (index - 1) * width), ce => ce, clr => dly_clr ); end generate; o <= dly_i(width - 1 downto 0); end generate; end structural; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity constant_963ed6358a is port ( op : out std_logic_vector((1 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end constant_963ed6358a; architecture behavior of constant_963ed6358a is begin op <= "0"; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity mcode_block_f4d0462e0e is port ( plbrst : in std_logic_vector((1 - 1) downto 0); plbabus : in std_logic_vector((32 - 1) downto 0); plbpavalid : in std_logic_vector((1 - 1) downto 0); plbrnw : in std_logic_vector((1 - 1) downto 0); plbwrdbus : in std_logic_vector((32 - 1) downto 0); rddata : in std_logic_vector((32 - 1) downto 0); addrpref : in std_logic_vector((20 - 1) downto 0); wrdbusreg : out std_logic_vector((32 - 1) downto 0); addrack : out std_logic_vector((1 - 1) downto 0); rdcomp : out std_logic_vector((1 - 1) downto 0); wrdack : out std_logic_vector((1 - 1) downto 0); bankaddr : out std_logic_vector((2 - 1) downto 0); rnwreg : out std_logic_vector((1 - 1) downto 0); rddack : out std_logic_vector((1 - 1) downto 0); rddbus : out std_logic_vector((32 - 1) downto 0); linearaddr : out std_logic_vector((8 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end mcode_block_f4d0462e0e; architecture behavior of mcode_block_f4d0462e0e is signal plbrst_1_110: unsigned((1 - 1) downto 0); signal plbabus_1_118: unsigned((32 - 1) downto 0); signal plbpavalid_1_127: unsigned((1 - 1) downto 0); signal plbrnw_1_139: unsigned((1 - 1) downto 0); signal plbwrdbus_1_147: unsigned((32 - 1) downto 0); signal rddata_1_158: unsigned((32 - 1) downto 0); signal addrpref_1_166: unsigned((20 - 1) downto 0); signal plbrstreg_12_24_next: boolean; signal plbrstreg_12_24: boolean := false; signal plbabusreg_13_25_next: unsigned((32 - 1) downto 0); signal plbabusreg_13_25: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000"; signal plbpavalidreg_14_28_next: boolean; signal plbpavalidreg_14_28: boolean := false; signal plbrnwreg_15_24_next: unsigned((1 - 1) downto 0); signal plbrnwreg_15_24: unsigned((1 - 1) downto 0) := "0"; signal plbwrdbusreg_16_27_next: unsigned((32 - 1) downto 0); signal plbwrdbusreg_16_27: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000"; signal avalidreg_28_23_next: boolean; signal avalidreg_28_23: boolean := false; signal ps1reg_39_20_next: boolean; signal ps1reg_39_20: boolean := false; signal psreg_47_19_next: boolean; signal psreg_47_19: boolean := false; type array_type_rdcompdelay_58_25 is array (0 to (3 - 1)) of unsigned((1 - 1) downto 0); signal rdcompdelay_58_25: array_type_rdcompdelay_58_25 := ( "0", "0", "0"); signal rdcompdelay_58_25_front_din: unsigned((1 - 1) downto 0); signal rdcompdelay_58_25_back: unsigned((1 - 1) downto 0); signal rdcompdelay_58_25_push_front_pop_back_en: std_logic; signal rdcompreg_62_23_next: unsigned((1 - 1) downto 0); signal rdcompreg_62_23: unsigned((1 - 1) downto 0) := "0"; signal rddackreg_66_23_next: unsigned((1 - 1) downto 0); signal rddackreg_66_23: unsigned((1 - 1) downto 0) := "0"; signal wrdackreg_70_23_next: unsigned((1 - 1) downto 0); signal wrdackreg_70_23: unsigned((1 - 1) downto 0) := "0"; signal rddbusreg_84_23_next: unsigned((32 - 1) downto 0); signal rddbusreg_84_23: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000"; signal bankaddr_20_1_slice: unsigned((2 - 1) downto 0); signal linearaddr_21_1_slice: unsigned((8 - 1) downto 0); signal addrpref_in_32_1_slice: unsigned((20 - 1) downto 0); signal rel_33_4: boolean; signal ps1_join_33_1: boolean; signal ps_42_1_bit: boolean; signal bitnot_49_49: boolean; signal bitnot_49_73: boolean; signal bit_49_49: boolean; signal addrack_49_1_convert: unsigned((1 - 1) downto 0); signal bit_55_43: unsigned((1 - 1) downto 0); signal bitnot_72_35: unsigned((1 - 1) downto 0); signal wrdackreg_72_1_bit: unsigned((1 - 1) downto 0); signal rdsel_76_1_bit: unsigned((1 - 1) downto 0); signal rel_78_4: boolean; signal rddbus1_join_78_1: unsigned((32 - 1) downto 0); signal plbwrdbusreg_97_1_slice: unsigned((32 - 1) downto 0); signal plbrstreg_12_24_next_x_000000: boolean; signal plbpavalidreg_14_28_next_x_000000: boolean; begin plbrst_1_110 <= std_logic_vector_to_unsigned(plbrst); plbabus_1_118 <= std_logic_vector_to_unsigned(plbabus); plbpavalid_1_127 <= std_logic_vector_to_unsigned(plbpavalid); plbrnw_1_139 <= std_logic_vector_to_unsigned(plbrnw); plbwrdbus_1_147 <= std_logic_vector_to_unsigned(plbwrdbus); rddata_1_158 <= std_logic_vector_to_unsigned(rddata); addrpref_1_166 <= std_logic_vector_to_unsigned(addrpref); proc_plbrstreg_12_24: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then plbrstreg_12_24 <= plbrstreg_12_24_next; end if; end if; end process proc_plbrstreg_12_24; proc_plbabusreg_13_25: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then plbabusreg_13_25 <= plbabusreg_13_25_next; end if; end if; end process proc_plbabusreg_13_25; proc_plbpavalidreg_14_28: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then plbpavalidreg_14_28 <= plbpavalidreg_14_28_next; end if; end if; end process proc_plbpavalidreg_14_28; proc_plbrnwreg_15_24: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then plbrnwreg_15_24 <= plbrnwreg_15_24_next; end if; end if; end process proc_plbrnwreg_15_24; proc_plbwrdbusreg_16_27: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then plbwrdbusreg_16_27 <= plbwrdbusreg_16_27_next; end if; end if; end process proc_plbwrdbusreg_16_27; proc_avalidreg_28_23: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then avalidreg_28_23 <= avalidreg_28_23_next; end if; end if; end process proc_avalidreg_28_23; proc_ps1reg_39_20: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then ps1reg_39_20 <= ps1reg_39_20_next; end if; end if; end process proc_ps1reg_39_20; proc_psreg_47_19: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then psreg_47_19 <= psreg_47_19_next; end if; end if; end process proc_psreg_47_19; rdcompdelay_58_25_back <= rdcompdelay_58_25(2); proc_rdcompdelay_58_25: process (clk) is variable i: integer; begin if (clk'event and (clk = '1')) then if ((ce = '1') and (rdcompdelay_58_25_push_front_pop_back_en = '1')) then for i in 2 downto 1 loop rdcompdelay_58_25(i) <= rdcompdelay_58_25(i-1); end loop; rdcompdelay_58_25(0) <= rdcompdelay_58_25_front_din; end if; end if; end process proc_rdcompdelay_58_25; proc_rdcompreg_62_23: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then rdcompreg_62_23 <= rdcompreg_62_23_next; end if; end if; end process proc_rdcompreg_62_23; proc_rddackreg_66_23: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then rddackreg_66_23 <= rddackreg_66_23_next; end if; end if; end process proc_rddackreg_66_23; proc_wrdackreg_70_23: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then wrdackreg_70_23 <= wrdackreg_70_23_next; end if; end if; end process proc_wrdackreg_70_23; proc_rddbusreg_84_23: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then rddbusreg_84_23 <= rddbusreg_84_23_next; end if; end if; end process proc_rddbusreg_84_23; bankaddr_20_1_slice <= u2u_slice(plbabusreg_13_25, 11, 10); linearaddr_21_1_slice <= u2u_slice(plbabusreg_13_25, 9, 2); addrpref_in_32_1_slice <= u2u_slice(plbabusreg_13_25, 31, 12); rel_33_4 <= addrpref_in_32_1_slice = addrpref_1_166; proc_if_33_1: process (rel_33_4) is begin if rel_33_4 then ps1_join_33_1 <= true; else ps1_join_33_1 <= false; end if; end process proc_if_33_1; ps_42_1_bit <= ((boolean_to_vector(ps1_join_33_1) and boolean_to_vector(plbpavalidreg_14_28)) = "1"); bitnot_49_49 <= ((not boolean_to_vector(plbrstreg_12_24)) = "1"); bitnot_49_73 <= ((not boolean_to_vector(psreg_47_19)) = "1"); bit_49_49 <= ((boolean_to_vector(bitnot_49_49) and boolean_to_vector(ps_42_1_bit) and boolean_to_vector(bitnot_49_73)) = "1"); addrack_49_1_convert <= u2u_cast(std_logic_vector_to_unsigned(boolean_to_vector(bit_49_49)), 0, 1, 0); bit_55_43 <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(addrack_49_1_convert) and unsigned_to_std_logic_vector(plbrnwreg_15_24)); bitnot_72_35 <= std_logic_vector_to_unsigned(not unsigned_to_std_logic_vector(plbrnwreg_15_24)); wrdackreg_72_1_bit <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(addrack_49_1_convert) and unsigned_to_std_logic_vector(bitnot_72_35)); rdsel_76_1_bit <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(rdcompdelay_58_25_back) or unsigned_to_std_logic_vector(rdcompreg_62_23)); rel_78_4 <= rdsel_76_1_bit = std_logic_vector_to_unsigned("1"); proc_if_78_1: process (rddata_1_158, rel_78_4) is begin if rel_78_4 then rddbus1_join_78_1 <= rddata_1_158; else rddbus1_join_78_1 <= std_logic_vector_to_unsigned("00000000000000000000000000000000"); end if; end process proc_if_78_1; plbwrdbusreg_97_1_slice <= u2u_slice(plbwrdbus_1_147, 31, 0); plbrstreg_12_24_next_x_000000 <= (plbrst_1_110 /= "0"); plbrstreg_12_24_next <= plbrstreg_12_24_next_x_000000; plbabusreg_13_25_next <= plbabus_1_118; plbpavalidreg_14_28_next_x_000000 <= (plbpavalid_1_127 /= "0"); plbpavalidreg_14_28_next <= plbpavalidreg_14_28_next_x_000000; plbrnwreg_15_24_next <= plbrnw_1_139; plbwrdbusreg_16_27_next <= plbwrdbusreg_97_1_slice; avalidreg_28_23_next <= plbpavalidreg_14_28; ps1reg_39_20_next <= ps1_join_33_1; psreg_47_19_next <= ps_42_1_bit; rdcompdelay_58_25_front_din <= bit_55_43; rdcompdelay_58_25_push_front_pop_back_en <= '1'; rdcompreg_62_23_next <= rdcompdelay_58_25_back; rddackreg_66_23_next <= rdcompreg_62_23; wrdackreg_70_23_next <= wrdackreg_72_1_bit; rddbusreg_84_23_next <= rddbus1_join_78_1; wrdbusreg <= unsigned_to_std_logic_vector(plbwrdbusreg_16_27); addrack <= unsigned_to_std_logic_vector(addrack_49_1_convert); rdcomp <= unsigned_to_std_logic_vector(rdcompreg_62_23); wrdack <= unsigned_to_std_logic_vector(wrdackreg_70_23); bankaddr <= unsigned_to_std_logic_vector(bankaddr_20_1_slice); rnwreg <= unsigned_to_std_logic_vector(plbrnwreg_15_24); rddack <= unsigned_to_std_logic_vector(rddackreg_66_23); rddbus <= unsigned_to_std_logic_vector(rddbusreg_84_23); linearaddr <= unsigned_to_std_logic_vector(linearaddr_21_1_slice); end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity mcode_block_57a988c97d is port ( wrdbus : in std_logic_vector((32 - 1) downto 0); bankaddr : in std_logic_vector((2 - 1) downto 0); linearaddr : in std_logic_vector((8 - 1) downto 0); rnwreg : in std_logic_vector((1 - 1) downto 0); addrack : in std_logic_vector((1 - 1) downto 0); sm_gpio_out8 : in std_logic_vector((8 - 1) downto 0); sm_cmd_response : in std_logic_vector((32 - 1) downto 0); sm_cmd_response_pfull : in std_logic_vector((1 - 1) downto 0); sm_cmd_response_empty : in std_logic_vector((1 - 1) downto 0); sm_cmd_request_pfull : in std_logic_vector((1 - 1) downto 0); sm_cmd_request_full : in std_logic_vector((1 - 1) downto 0); read_bank_out : out std_logic_vector((32 - 1) downto 0); sm_gpio_out8_din : out std_logic_vector((8 - 1) downto 0); sm_gpio_out8_en : out std_logic_vector((1 - 1) downto 0); sm_cmd_response_re : out std_logic_vector((1 - 1) downto 0); sm_cmd_request_din : out std_logic_vector((32 - 1) downto 0); sm_cmd_request_we : out std_logic_vector((1 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end mcode_block_57a988c97d; architecture behavior of mcode_block_57a988c97d is signal wrdbus_1_133: unsigned((32 - 1) downto 0); signal bankaddr_1_141: unsigned((2 - 1) downto 0); signal linearaddr_1_151: unsigned((8 - 1) downto 0); signal rnwreg_1_163: unsigned((1 - 1) downto 0); signal addrack_1_171: unsigned((1 - 1) downto 0); signal sm_gpio_out8_1_180: unsigned((8 - 1) downto 0); signal sm_cmd_response_1_194: unsigned((32 - 1) downto 0); signal sm_cmd_response_pfull_1_211: unsigned((1 - 1) downto 0); signal sm_cmd_response_empty_1_234: boolean; signal sm_cmd_request_pfull_1_257: unsigned((1 - 1) downto 0); signal sm_cmd_request_full_1_279: boolean; signal reg_bank_out_reg_31_30_next: unsigned((32 - 1) downto 0); signal reg_bank_out_reg_31_30: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000"; signal fifo_bank_out_reg_40_31_next: unsigned((32 - 1) downto 0); signal fifo_bank_out_reg_40_31: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000"; signal read_bank_out_reg_111_31_next: unsigned((32 - 1) downto 0); signal read_bank_out_reg_111_31: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000"; signal bankaddr_reg_114_26_next: unsigned((2 - 1) downto 0); signal bankaddr_reg_114_26: unsigned((2 - 1) downto 0) := "00"; signal sm_cmd_response_empty_bus_18_1_convert: unsigned((32 - 1) downto 0); signal sm_cmd_request_full_bus_24_1_convert: unsigned((32 - 1) downto 0); signal rel_43_4: boolean; signal rel_45_8: boolean; signal rel_47_8: boolean; signal rel_49_8: boolean; signal rel_51_8: boolean; signal fifo_bank_out_reg_join_43_1: unsigned((32 - 1) downto 0); signal opcode_55_1_concat: unsigned((12 - 1) downto 0); signal rel_73_4: boolean; signal sm_cmd_response_re_join_73_1: boolean; signal rel_82_4: boolean; signal sm_gpio_out8_en_join_82_1: boolean; signal slice_91_39: unsigned((32 - 1) downto 0); signal rel_97_4: boolean; signal sm_cmd_request_we_join_97_1: boolean; signal slice_106_37: unsigned((8 - 1) downto 0); signal rel_116_4: boolean; signal rel_119_8: boolean; signal rel_122_8: boolean; signal rel_125_8: boolean; signal read_bank_out_reg_join_116_1: unsigned((32 - 1) downto 0); signal cast_reg_bank_out_reg_31_30_next: unsigned((32 - 1) downto 0); begin wrdbus_1_133 <= std_logic_vector_to_unsigned(wrdbus); bankaddr_1_141 <= std_logic_vector_to_unsigned(bankaddr); linearaddr_1_151 <= std_logic_vector_to_unsigned(linearaddr); rnwreg_1_163 <= std_logic_vector_to_unsigned(rnwreg); addrack_1_171 <= std_logic_vector_to_unsigned(addrack); sm_gpio_out8_1_180 <= std_logic_vector_to_unsigned(sm_gpio_out8); sm_cmd_response_1_194 <= std_logic_vector_to_unsigned(sm_cmd_response); sm_cmd_response_pfull_1_211 <= std_logic_vector_to_unsigned(sm_cmd_response_pfull); sm_cmd_response_empty_1_234 <= ((sm_cmd_response_empty) = "1"); sm_cmd_request_pfull_1_257 <= std_logic_vector_to_unsigned(sm_cmd_request_pfull); sm_cmd_request_full_1_279 <= ((sm_cmd_request_full) = "1"); proc_reg_bank_out_reg_31_30: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then reg_bank_out_reg_31_30 <= reg_bank_out_reg_31_30_next; end if; end if; end process proc_reg_bank_out_reg_31_30; proc_fifo_bank_out_reg_40_31: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then fifo_bank_out_reg_40_31 <= fifo_bank_out_reg_40_31_next; end if; end if; end process proc_fifo_bank_out_reg_40_31; proc_read_bank_out_reg_111_31: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then read_bank_out_reg_111_31 <= read_bank_out_reg_111_31_next; end if; end if; end process proc_read_bank_out_reg_111_31; proc_bankaddr_reg_114_26: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then bankaddr_reg_114_26 <= bankaddr_reg_114_26_next; end if; end if; end process proc_bankaddr_reg_114_26; sm_cmd_response_empty_bus_18_1_convert <= u2u_cast(std_logic_vector_to_unsigned(boolean_to_vector(sm_cmd_response_empty_1_234)), 0, 32, 0); sm_cmd_request_full_bus_24_1_convert <= u2u_cast(std_logic_vector_to_unsigned(boolean_to_vector(sm_cmd_request_full_1_279)), 0, 32, 0); rel_43_4 <= linearaddr_1_151 = std_logic_vector_to_unsigned("00000000"); rel_45_8 <= linearaddr_1_151 = std_logic_vector_to_unsigned("00000001"); rel_47_8 <= linearaddr_1_151 = std_logic_vector_to_unsigned("00000010"); rel_49_8 <= linearaddr_1_151 = std_logic_vector_to_unsigned("00000011"); rel_51_8 <= linearaddr_1_151 = std_logic_vector_to_unsigned("00000100"); proc_if_43_1: process (fifo_bank_out_reg_40_31, rel_43_4, rel_45_8, rel_47_8, rel_49_8, rel_51_8, sm_cmd_request_full_bus_24_1_convert, sm_cmd_request_pfull_1_257, sm_cmd_response_1_194, sm_cmd_response_empty_bus_18_1_convert, sm_cmd_response_pfull_1_211) is begin if rel_43_4 then fifo_bank_out_reg_join_43_1 <= sm_cmd_response_1_194; elsif rel_45_8 then fifo_bank_out_reg_join_43_1 <= u2u_cast(sm_cmd_response_pfull_1_211, 0, 32, 0); elsif rel_47_8 then fifo_bank_out_reg_join_43_1 <= sm_cmd_response_empty_bus_18_1_convert; elsif rel_49_8 then fifo_bank_out_reg_join_43_1 <= u2u_cast(sm_cmd_request_pfull_1_257, 0, 32, 0); elsif rel_51_8 then fifo_bank_out_reg_join_43_1 <= sm_cmd_request_full_bus_24_1_convert; else fifo_bank_out_reg_join_43_1 <= fifo_bank_out_reg_40_31; end if; end process proc_if_43_1; opcode_55_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(addrack_1_171) & unsigned_to_std_logic_vector(rnwreg_1_163) & unsigned_to_std_logic_vector(bankaddr_1_141) & unsigned_to_std_logic_vector(linearaddr_1_151)); rel_73_4 <= opcode_55_1_concat = std_logic_vector_to_unsigned("110100000000"); proc_if_73_1: process (rel_73_4) is begin if rel_73_4 then sm_cmd_response_re_join_73_1 <= true; else sm_cmd_response_re_join_73_1 <= false; end if; end process proc_if_73_1; rel_82_4 <= opcode_55_1_concat = std_logic_vector_to_unsigned("101000000000"); proc_if_82_1: process (rel_82_4) is begin if rel_82_4 then sm_gpio_out8_en_join_82_1 <= true; else sm_gpio_out8_en_join_82_1 <= false; end if; end process proc_if_82_1; slice_91_39 <= u2u_slice(wrdbus_1_133, 31, 0); rel_97_4 <= opcode_55_1_concat = std_logic_vector_to_unsigned("100100000000"); proc_if_97_1: process (rel_97_4) is begin if rel_97_4 then sm_cmd_request_we_join_97_1 <= true; else sm_cmd_request_we_join_97_1 <= false; end if; end process proc_if_97_1; slice_106_37 <= u2u_slice(wrdbus_1_133, 7, 0); rel_116_4 <= bankaddr_reg_114_26 = std_logic_vector_to_unsigned("00"); rel_119_8 <= bankaddr_reg_114_26 = std_logic_vector_to_unsigned("01"); rel_122_8 <= bankaddr_reg_114_26 = std_logic_vector_to_unsigned("10"); rel_125_8 <= bankaddr_reg_114_26 = std_logic_vector_to_unsigned("11"); proc_if_116_1: process (fifo_bank_out_reg_40_31, read_bank_out_reg_111_31, reg_bank_out_reg_31_30, rel_116_4, rel_119_8, rel_122_8, rel_125_8) is begin if rel_116_4 then read_bank_out_reg_join_116_1 <= std_logic_vector_to_unsigned("00000000000000000000000000000000"); elsif rel_119_8 then read_bank_out_reg_join_116_1 <= fifo_bank_out_reg_40_31; elsif rel_122_8 then read_bank_out_reg_join_116_1 <= reg_bank_out_reg_31_30; elsif rel_125_8 then read_bank_out_reg_join_116_1 <= std_logic_vector_to_unsigned("00000000000000000000000000000000"); else read_bank_out_reg_join_116_1 <= read_bank_out_reg_111_31; end if; end process proc_if_116_1; cast_reg_bank_out_reg_31_30_next <= u2u_cast(sm_gpio_out8_1_180, 0, 32, 0); reg_bank_out_reg_31_30_next <= cast_reg_bank_out_reg_31_30_next; fifo_bank_out_reg_40_31_next <= fifo_bank_out_reg_join_43_1; read_bank_out_reg_111_31_next <= read_bank_out_reg_join_116_1; bankaddr_reg_114_26_next <= bankaddr_1_141; read_bank_out <= unsigned_to_std_logic_vector(read_bank_out_reg_111_31); sm_gpio_out8_din <= unsigned_to_std_logic_vector(slice_106_37); sm_gpio_out8_en <= boolean_to_vector(sm_gpio_out8_en_join_82_1); sm_cmd_response_re <= boolean_to_vector(sm_cmd_response_re_join_73_1); sm_cmd_request_din <= unsigned_to_std_logic_vector(slice_91_39); sm_cmd_request_we <= boolean_to_vector(sm_cmd_request_we_join_97_1); end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity inverter_e5b38cca3b is port ( ip : in std_logic_vector((1 - 1) downto 0); op : out std_logic_vector((1 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end inverter_e5b38cca3b; architecture behavior of inverter_e5b38cca3b is signal ip_1_26: boolean; type array_type_op_mem_22_20 is array (0 to (1 - 1)) of boolean; signal op_mem_22_20: array_type_op_mem_22_20 := ( 0 => false); signal op_mem_22_20_front_din: boolean; signal op_mem_22_20_back: boolean; signal op_mem_22_20_push_front_pop_back_en: std_logic; signal internal_ip_12_1_bitnot: boolean; begin ip_1_26 <= ((ip) = "1"); op_mem_22_20_back <= op_mem_22_20(0); proc_op_mem_22_20: process (clk) is variable i: integer; begin if (clk'event and (clk = '1')) then if ((ce = '1') and (op_mem_22_20_push_front_pop_back_en = '1')) then op_mem_22_20(0) <= op_mem_22_20_front_din; end if; end if; end process proc_op_mem_22_20; internal_ip_12_1_bitnot <= ((not boolean_to_vector(ip_1_26)) = "1"); op_mem_22_20_push_front_pop_back_en <= '0'; op <= boolean_to_vector(internal_ip_12_1_bitnot); end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity mcode_block_f21d0469ad is port ( out_port : in std_logic_vector((8 - 1) downto 0); port_id : in std_logic_vector((8 - 1) downto 0); rs : in std_logic_vector((1 - 1) downto 0); ws : in std_logic_vector((1 - 1) downto 0); sda_i : in std_logic_vector((1 - 1) downto 0); cmd_req : in std_logic_vector((32 - 1) downto 0); cmd_rdy : in std_logic_vector((1 - 1) downto 0); in_port : out std_logic_vector((8 - 1) downto 0); reset_dcm_o : out std_logic_vector((1 - 1) downto 0); sda_o : out std_logic_vector((1 - 1) downto 0); scl_o : out std_logic_vector((1 - 1) downto 0); cmd_get : out std_logic_vector((1 - 1) downto 0); cmd_rsp : out std_logic_vector((32 - 1) downto 0); cmd_ack : out std_logic_vector((1 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end mcode_block_f21d0469ad; architecture behavior of mcode_block_f21d0469ad is signal out_port_1_91: unsigned((8 - 1) downto 0); signal port_id_1_101: unsigned((8 - 1) downto 0); signal rs_1_110: boolean; signal ws_1_114: boolean; signal sda_i_1_118: boolean; signal cmd_req_1_125: unsigned((32 - 1) downto 0); signal cmd_rdy_1_134: boolean; signal reset_dcm_reg_4_27_next: boolean; signal reset_dcm_reg_4_27: boolean := false; signal reset_dcm_reg_4_27_en: std_logic; signal sda_reg_5_27_next: boolean; signal sda_reg_5_27: boolean := false; signal sda_reg_5_27_en: std_logic; signal scl_reg_6_27_next: boolean; signal scl_reg_6_27: boolean := false; signal scl_reg_6_27_en: std_logic; signal cmd_get_reg_7_27_next: boolean; signal cmd_get_reg_7_27: boolean := false; signal cmd_ack_reg_8_27_next: boolean; signal cmd_ack_reg_8_27: boolean := false; signal cmd_rsp0_reg_9_27_next: unsigned((8 - 1) downto 0); signal cmd_rsp0_reg_9_27: unsigned((8 - 1) downto 0) := "00000000"; signal cmd_rsp0_reg_9_27_en: std_logic; signal cmd_rsp1_reg_10_27_next: unsigned((8 - 1) downto 0); signal cmd_rsp1_reg_10_27: unsigned((8 - 1) downto 0) := "00000000"; signal cmd_rsp1_reg_10_27_en: std_logic; signal cmd_rsp2_reg_11_27_next: unsigned((8 - 1) downto 0); signal cmd_rsp2_reg_11_27: unsigned((8 - 1) downto 0) := "00000000"; signal cmd_rsp2_reg_11_27_en: std_logic; signal cmd_rsp3_reg_12_27_next: unsigned((8 - 1) downto 0); signal cmd_rsp3_reg_12_27: unsigned((8 - 1) downto 0) := "00000000"; signal cmd_rsp3_reg_12_27_en: std_logic; signal rel_22_6: boolean; signal rel_24_10: boolean; signal rel_26_10: boolean; signal rel_28_10: boolean; signal rel_30_10: boolean; signal rel_32_10: boolean; signal rel_34_10: boolean; signal reset_sel_join_22_1: boolean; signal i2c_sel_join_22_1: boolean; signal cmd_ctrl_sel_join_22_1: boolean; signal cmd_dat0_sel_join_22_1: boolean; signal cmd_dat1_sel_join_22_1: boolean; signal cmd_dat2_sel_join_22_1: boolean; signal cmd_dat3_sel_join_22_1: boolean; signal reset_we_39_1_bit: boolean; signal i2c_we_40_1_bit: boolean; signal cmd_ctrl_we_41_1_bit: boolean; signal cmd_dat0_we_42_1_bit: boolean; signal cmd_dat1_we_43_1_bit: boolean; signal cmd_dat2_we_44_1_bit: boolean; signal cmd_dat3_we_45_1_bit: boolean; signal slice_49_43: unsigned((1 - 1) downto 0); signal reset_dcm_49_5_convert: boolean; signal rel_48_6: boolean; signal reset_dcm_join_48_1: boolean; signal reset_dcm_join_48_1_en: std_logic; signal slice_56_37: unsigned((1 - 1) downto 0); signal sda_56_5_convert: boolean; signal slice_55_47: unsigned((1 - 1) downto 0); signal convert_55_26: boolean; signal bit_55_14: boolean; signal rel_55_12: boolean; signal sda_join_55_1: boolean; signal sda_join_55_1_en: std_logic; signal slice_63_37: unsigned((1 - 1) downto 0); signal scl_63_5_convert: boolean; signal slice_62_46: unsigned((1 - 1) downto 0); signal convert_62_25: boolean; signal bit_62_13: boolean; signal rel_62_11: boolean; signal scl_join_62_1: boolean; signal scl_join_62_1_en: std_logic; signal slice_70_41: unsigned((1 - 1) downto 0); signal cmd_get_70_5_convert: boolean; signal slice_71_41: unsigned((1 - 1) downto 0); signal cmd_ack_71_5_convert: boolean; signal rel_69_6: boolean; signal cmd_ack_join_69_1: boolean; signal cmd_get_join_69_1: boolean; signal rel_76_6: boolean; signal cmd_rsp0_join_76_1: unsigned((8 - 1) downto 0); signal cmd_rsp0_join_76_1_en: std_logic; signal rel_81_6: boolean; signal cmd_rsp1_join_81_1: unsigned((8 - 1) downto 0); signal cmd_rsp1_join_81_1_en: std_logic; signal rel_86_6: boolean; signal cmd_rsp2_join_86_1: unsigned((8 - 1) downto 0); signal cmd_rsp2_join_86_1_en: std_logic; signal rel_91_6: boolean; signal cmd_rsp3_join_91_1: unsigned((8 - 1) downto 0); signal cmd_rsp3_join_91_1_en: std_logic; signal convert_99_56: unsigned((1 - 1) downto 0); signal in_port_99_5_concat: unsigned((8 - 1) downto 0); signal convert_101_56: unsigned((1 - 1) downto 0); signal in_port_101_5_concat: unsigned((8 - 1) downto 0); signal in_port_103_5_slice: unsigned((8 - 1) downto 0); signal in_port_105_5_slice: unsigned((8 - 1) downto 0); signal in_port_107_5_slice: unsigned((8 - 1) downto 0); signal in_port_109_5_slice: unsigned((8 - 1) downto 0); signal rel_98_6: boolean; signal rel_100_10: boolean; signal rel_102_10: boolean; signal rel_104_10: boolean; signal rel_106_10: boolean; signal rel_108_10: boolean; signal in_port_join_98_1: unsigned((8 - 1) downto 0); signal cmd_rsp_118_1_concat: unsigned((32 - 1) downto 0); begin out_port_1_91 <= std_logic_vector_to_unsigned(out_port); port_id_1_101 <= std_logic_vector_to_unsigned(port_id); rs_1_110 <= ((rs) = "1"); ws_1_114 <= ((ws) = "1"); sda_i_1_118 <= ((sda_i) = "1"); cmd_req_1_125 <= std_logic_vector_to_unsigned(cmd_req); cmd_rdy_1_134 <= ((cmd_rdy) = "1"); proc_reset_dcm_reg_4_27: process (clk) is begin if (clk'event and (clk = '1')) then if ((ce = '1') and (reset_dcm_reg_4_27_en = '1')) then reset_dcm_reg_4_27 <= reset_dcm_reg_4_27_next; end if; end if; end process proc_reset_dcm_reg_4_27; proc_sda_reg_5_27: process (clk) is begin if (clk'event and (clk = '1')) then if ((ce = '1') and (sda_reg_5_27_en = '1')) then sda_reg_5_27 <= sda_reg_5_27_next; end if; end if; end process proc_sda_reg_5_27; proc_scl_reg_6_27: process (clk) is begin if (clk'event and (clk = '1')) then if ((ce = '1') and (scl_reg_6_27_en = '1')) then scl_reg_6_27 <= scl_reg_6_27_next; end if; end if; end process proc_scl_reg_6_27; proc_cmd_get_reg_7_27: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then cmd_get_reg_7_27 <= cmd_get_reg_7_27_next; end if; end if; end process proc_cmd_get_reg_7_27; proc_cmd_ack_reg_8_27: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then cmd_ack_reg_8_27 <= cmd_ack_reg_8_27_next; end if; end if; end process proc_cmd_ack_reg_8_27; proc_cmd_rsp0_reg_9_27: process (clk) is begin if (clk'event and (clk = '1')) then if ((ce = '1') and (cmd_rsp0_reg_9_27_en = '1')) then cmd_rsp0_reg_9_27 <= cmd_rsp0_reg_9_27_next; end if; end if; end process proc_cmd_rsp0_reg_9_27; proc_cmd_rsp1_reg_10_27: process (clk) is begin if (clk'event and (clk = '1')) then if ((ce = '1') and (cmd_rsp1_reg_10_27_en = '1')) then cmd_rsp1_reg_10_27 <= cmd_rsp1_reg_10_27_next; end if; end if; end process proc_cmd_rsp1_reg_10_27; proc_cmd_rsp2_reg_11_27: process (clk) is begin if (clk'event and (clk = '1')) then if ((ce = '1') and (cmd_rsp2_reg_11_27_en = '1')) then cmd_rsp2_reg_11_27 <= cmd_rsp2_reg_11_27_next; end if; end if; end process proc_cmd_rsp2_reg_11_27; proc_cmd_rsp3_reg_12_27: process (clk) is begin if (clk'event and (clk = '1')) then if ((ce = '1') and (cmd_rsp3_reg_12_27_en = '1')) then cmd_rsp3_reg_12_27 <= cmd_rsp3_reg_12_27_next; end if; end if; end process proc_cmd_rsp3_reg_12_27; rel_22_6 <= port_id_1_101 = std_logic_vector_to_unsigned("00000000"); rel_24_10 <= port_id_1_101 = std_logic_vector_to_unsigned("00000001"); rel_26_10 <= port_id_1_101 = std_logic_vector_to_unsigned("00000011"); rel_28_10 <= port_id_1_101 = std_logic_vector_to_unsigned("00000100"); rel_30_10 <= port_id_1_101 = std_logic_vector_to_unsigned("00000101"); rel_32_10 <= port_id_1_101 = std_logic_vector_to_unsigned("00000110"); rel_34_10 <= port_id_1_101 = std_logic_vector_to_unsigned("00000111"); proc_if_22_1: process (rel_22_6, rel_24_10, rel_26_10, rel_28_10, rel_30_10, rel_32_10, rel_34_10) is begin if rel_22_6 then reset_sel_join_22_1 <= true; i2c_sel_join_22_1 <= false; cmd_ctrl_sel_join_22_1 <= false; cmd_dat0_sel_join_22_1 <= false; cmd_dat1_sel_join_22_1 <= false; cmd_dat2_sel_join_22_1 <= false; cmd_dat3_sel_join_22_1 <= false; elsif rel_24_10 then reset_sel_join_22_1 <= false; i2c_sel_join_22_1 <= true; cmd_ctrl_sel_join_22_1 <= false; cmd_dat0_sel_join_22_1 <= false; cmd_dat1_sel_join_22_1 <= false; cmd_dat2_sel_join_22_1 <= false; cmd_dat3_sel_join_22_1 <= false; elsif rel_26_10 then reset_sel_join_22_1 <= false; i2c_sel_join_22_1 <= false; cmd_ctrl_sel_join_22_1 <= true; cmd_dat0_sel_join_22_1 <= false; cmd_dat1_sel_join_22_1 <= false; cmd_dat2_sel_join_22_1 <= false; cmd_dat3_sel_join_22_1 <= false; elsif rel_28_10 then reset_sel_join_22_1 <= false; i2c_sel_join_22_1 <= false; cmd_ctrl_sel_join_22_1 <= false; cmd_dat0_sel_join_22_1 <= true; cmd_dat1_sel_join_22_1 <= false; cmd_dat2_sel_join_22_1 <= false; cmd_dat3_sel_join_22_1 <= false; elsif rel_30_10 then reset_sel_join_22_1 <= false; i2c_sel_join_22_1 <= false; cmd_ctrl_sel_join_22_1 <= false; cmd_dat0_sel_join_22_1 <= false; cmd_dat1_sel_join_22_1 <= true; cmd_dat2_sel_join_22_1 <= false; cmd_dat3_sel_join_22_1 <= false; elsif rel_32_10 then reset_sel_join_22_1 <= false; i2c_sel_join_22_1 <= false; cmd_ctrl_sel_join_22_1 <= false; cmd_dat0_sel_join_22_1 <= false; cmd_dat1_sel_join_22_1 <= false; cmd_dat2_sel_join_22_1 <= true; cmd_dat3_sel_join_22_1 <= false; elsif rel_34_10 then reset_sel_join_22_1 <= false; i2c_sel_join_22_1 <= false; cmd_ctrl_sel_join_22_1 <= false; cmd_dat0_sel_join_22_1 <= false; cmd_dat1_sel_join_22_1 <= false; cmd_dat2_sel_join_22_1 <= false; cmd_dat3_sel_join_22_1 <= true; else reset_sel_join_22_1 <= false; i2c_sel_join_22_1 <= false; cmd_ctrl_sel_join_22_1 <= false; cmd_dat0_sel_join_22_1 <= false; cmd_dat1_sel_join_22_1 <= false; cmd_dat2_sel_join_22_1 <= false; cmd_dat3_sel_join_22_1 <= false; end if; end process proc_if_22_1; reset_we_39_1_bit <= ((boolean_to_vector(reset_sel_join_22_1) and boolean_to_vector(ws_1_114)) = "1"); i2c_we_40_1_bit <= ((boolean_to_vector(i2c_sel_join_22_1) and boolean_to_vector(ws_1_114)) = "1"); cmd_ctrl_we_41_1_bit <= ((boolean_to_vector(cmd_ctrl_sel_join_22_1) and boolean_to_vector(ws_1_114)) = "1"); cmd_dat0_we_42_1_bit <= ((boolean_to_vector(cmd_dat0_sel_join_22_1) and boolean_to_vector(ws_1_114)) = "1"); cmd_dat1_we_43_1_bit <= ((boolean_to_vector(cmd_dat1_sel_join_22_1) and boolean_to_vector(ws_1_114)) = "1"); cmd_dat2_we_44_1_bit <= ((boolean_to_vector(cmd_dat2_sel_join_22_1) and boolean_to_vector(ws_1_114)) = "1"); cmd_dat3_we_45_1_bit <= ((boolean_to_vector(cmd_dat3_sel_join_22_1) and boolean_to_vector(ws_1_114)) = "1"); slice_49_43 <= u2u_slice(out_port_1_91, 0, 0); reset_dcm_49_5_convert <= (slice_49_43 /= "0"); rel_48_6 <= reset_we_39_1_bit = true; proc_if_48_1: process (rel_48_6, reset_dcm_49_5_convert) is begin if rel_48_6 then reset_dcm_join_48_1_en <= '1'; else reset_dcm_join_48_1_en <= '0'; end if; reset_dcm_join_48_1 <= reset_dcm_49_5_convert; end process proc_if_48_1; slice_56_37 <= u2u_slice(out_port_1_91, 0, 0); sda_56_5_convert <= (slice_56_37 /= "0"); slice_55_47 <= u2u_slice(out_port_1_91, 1, 1); convert_55_26 <= (slice_55_47 /= "0"); bit_55_14 <= ((boolean_to_vector(i2c_we_40_1_bit) and boolean_to_vector(convert_55_26)) = "1"); rel_55_12 <= bit_55_14 = true; proc_if_55_1: process (rel_55_12, sda_56_5_convert) is begin if rel_55_12 then sda_join_55_1_en <= '1'; else sda_join_55_1_en <= '0'; end if; sda_join_55_1 <= sda_56_5_convert; end process proc_if_55_1; slice_63_37 <= u2u_slice(out_port_1_91, 2, 2); scl_63_5_convert <= (slice_63_37 /= "0"); slice_62_46 <= u2u_slice(out_port_1_91, 3, 3); convert_62_25 <= (slice_62_46 /= "0"); bit_62_13 <= ((boolean_to_vector(i2c_we_40_1_bit) and boolean_to_vector(convert_62_25)) = "1"); rel_62_11 <= bit_62_13 = true; proc_if_62_1: process (rel_62_11, scl_63_5_convert) is begin if rel_62_11 then scl_join_62_1_en <= '1'; else scl_join_62_1_en <= '0'; end if; scl_join_62_1 <= scl_63_5_convert; end process proc_if_62_1; slice_70_41 <= u2u_slice(out_port_1_91, 1, 1); cmd_get_70_5_convert <= (slice_70_41 /= "0"); slice_71_41 <= u2u_slice(out_port_1_91, 0, 0); cmd_ack_71_5_convert <= (slice_71_41 /= "0"); rel_69_6 <= cmd_ctrl_we_41_1_bit = true; proc_if_69_1: process (cmd_ack_71_5_convert, cmd_get_70_5_convert, rel_69_6) is begin if rel_69_6 then cmd_ack_join_69_1 <= cmd_ack_71_5_convert; cmd_get_join_69_1 <= cmd_get_70_5_convert; else cmd_ack_join_69_1 <= false; cmd_get_join_69_1 <= false; end if; end process proc_if_69_1; rel_76_6 <= cmd_dat0_we_42_1_bit = true; proc_if_76_1: process (out_port_1_91, rel_76_6) is begin if rel_76_6 then cmd_rsp0_join_76_1_en <= '1'; else cmd_rsp0_join_76_1_en <= '0'; end if; cmd_rsp0_join_76_1 <= out_port_1_91; end process proc_if_76_1; rel_81_6 <= cmd_dat1_we_43_1_bit = true; proc_if_81_1: process (out_port_1_91, rel_81_6) is begin if rel_81_6 then cmd_rsp1_join_81_1_en <= '1'; else cmd_rsp1_join_81_1_en <= '0'; end if; cmd_rsp1_join_81_1 <= out_port_1_91; end process proc_if_81_1; rel_86_6 <= cmd_dat2_we_44_1_bit = true; proc_if_86_1: process (out_port_1_91, rel_86_6) is begin if rel_86_6 then cmd_rsp2_join_86_1_en <= '1'; else cmd_rsp2_join_86_1_en <= '0'; end if; cmd_rsp2_join_86_1 <= out_port_1_91; end process proc_if_86_1; rel_91_6 <= cmd_dat3_we_45_1_bit = true; proc_if_91_1: process (out_port_1_91, rel_91_6) is begin if rel_91_6 then cmd_rsp3_join_91_1_en <= '1'; else cmd_rsp3_join_91_1_en <= '0'; end if; cmd_rsp3_join_91_1 <= out_port_1_91; end process proc_if_91_1; convert_99_56 <= u2u_cast(std_logic_vector_to_unsigned(boolean_to_vector(sda_i_1_118)), 0, 1, 0); in_port_99_5_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(std_logic_vector_to_unsigned("0000000")) & unsigned_to_std_logic_vector(convert_99_56)); convert_101_56 <= u2u_cast(std_logic_vector_to_unsigned(boolean_to_vector(cmd_rdy_1_134)), 0, 1, 0); in_port_101_5_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(std_logic_vector_to_unsigned("0000000")) & unsigned_to_std_logic_vector(convert_101_56)); in_port_103_5_slice <= u2u_slice(cmd_req_1_125, 7, 0); in_port_105_5_slice <= u2u_slice(cmd_req_1_125, 15, 8); in_port_107_5_slice <= u2u_slice(cmd_req_1_125, 23, 16); in_port_109_5_slice <= u2u_slice(cmd_req_1_125, 31, 24); rel_98_6 <= i2c_sel_join_22_1 = true; rel_100_10 <= cmd_ctrl_sel_join_22_1 = true; rel_102_10 <= cmd_dat0_sel_join_22_1 = true; rel_104_10 <= cmd_dat1_sel_join_22_1 = true; rel_106_10 <= cmd_dat2_sel_join_22_1 = true; rel_108_10 <= cmd_dat3_sel_join_22_1 = true; proc_if_98_1: process (in_port_101_5_concat, in_port_103_5_slice, in_port_105_5_slice, in_port_107_5_slice, in_port_109_5_slice, in_port_99_5_concat, rel_100_10, rel_102_10, rel_104_10, rel_106_10, rel_108_10, rel_98_6) is begin if rel_98_6 then in_port_join_98_1 <= in_port_99_5_concat; elsif rel_100_10 then in_port_join_98_1 <= in_port_101_5_concat; elsif rel_102_10 then in_port_join_98_1 <= in_port_103_5_slice; elsif rel_104_10 then in_port_join_98_1 <= in_port_105_5_slice; elsif rel_106_10 then in_port_join_98_1 <= in_port_107_5_slice; elsif rel_108_10 then in_port_join_98_1 <= in_port_109_5_slice; else in_port_join_98_1 <= std_logic_vector_to_unsigned("00000000"); end if; end process proc_if_98_1; cmd_rsp_118_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(cmd_rsp3_reg_12_27) & unsigned_to_std_logic_vector(cmd_rsp2_reg_11_27) & unsigned_to_std_logic_vector(cmd_rsp1_reg_10_27) & unsigned_to_std_logic_vector(cmd_rsp0_reg_9_27)); reset_dcm_reg_4_27_next <= reset_dcm_49_5_convert; reset_dcm_reg_4_27_en <= reset_dcm_join_48_1_en; sda_reg_5_27_next <= sda_56_5_convert; sda_reg_5_27_en <= sda_join_55_1_en; scl_reg_6_27_next <= scl_63_5_convert; scl_reg_6_27_en <= scl_join_62_1_en; cmd_get_reg_7_27_next <= cmd_get_join_69_1; cmd_ack_reg_8_27_next <= cmd_ack_join_69_1; cmd_rsp0_reg_9_27_next <= out_port_1_91; cmd_rsp0_reg_9_27_en <= cmd_rsp0_join_76_1_en; cmd_rsp1_reg_10_27_next <= out_port_1_91; cmd_rsp1_reg_10_27_en <= cmd_rsp1_join_81_1_en; cmd_rsp2_reg_11_27_next <= out_port_1_91; cmd_rsp2_reg_11_27_en <= cmd_rsp2_join_86_1_en; cmd_rsp3_reg_12_27_next <= out_port_1_91; cmd_rsp3_reg_12_27_en <= cmd_rsp3_join_91_1_en; in_port <= unsigned_to_std_logic_vector(in_port_join_98_1); reset_dcm_o <= boolean_to_vector(reset_dcm_reg_4_27); sda_o <= boolean_to_vector(sda_reg_5_27); scl_o <= boolean_to_vector(scl_reg_6_27); cmd_get <= boolean_to_vector(cmd_get_reg_7_27); cmd_rsp <= unsigned_to_std_logic_vector(cmd_rsp_118_1_concat); cmd_ack <= boolean_to_vector(cmd_ack_reg_8_27); end behavior; ------------------------------------------------------------------- -- System Generator version 12.1 VHDL source file. -- -- Copyright(C) 2010 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2010 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use work.conv_pkg.all; entity xlsprom is generic ( core_name0: string := ""; c_width: integer := 12; c_address_width: integer := 4; latency: integer := 1 ); port ( addr: in std_logic_vector(c_address_width - 1 downto 0); en: in std_logic_vector(0 downto 0); rst: in std_logic_vector(0 downto 0); ce: in std_logic; clk: in std_logic; data: out std_logic_vector(c_width - 1 downto 0) ); end xlsprom ; architecture behavior of xlsprom is component synth_reg generic ( width: integer; latency: integer ); port ( i: in std_logic_vector(width - 1 downto 0); ce: in std_logic; clr: in std_logic; clk: in std_logic; o: out std_logic_vector(width - 1 downto 0) ); end component; signal core_addr: std_logic_vector(c_address_width - 1 downto 0); signal core_data_out: std_logic_vector(c_width - 1 downto 0); signal core_ce, sinit: std_logic; component bmg_41_99d18de731b34188 port ( addra: in std_logic_vector(c_address_width - 1 downto 0); clka: in std_logic; ena: in std_logic; douta: out std_logic_vector(c_width - 1 downto 0) ); end component; attribute syn_black_box of bmg_41_99d18de731b34188: component is true; attribute fpga_dont_touch of bmg_41_99d18de731b34188: component is "true"; attribute box_type of bmg_41_99d18de731b34188: component is "black_box"; begin core_addr <= addr; core_ce <= ce and en(0); sinit <= rst(0) and ce; comp0: if ((core_name0 = "bmg_41_99d18de731b34188")) generate core_instance0: bmg_41_99d18de731b34188 port map ( addra => core_addr, clka => clk, ena => core_ce, douta => core_data_out ); end generate; latency_test: if (latency > 1) generate reg: synth_reg generic map ( width => c_width, latency => latency - 1 ) port map ( i => core_data_out, ce => core_ce, clr => '0', clk => clk, o => data ); end generate; latency_1: if (latency <= 1) generate data <= core_data_out; end generate; end behavior; ------------------------------------------------------------------- -- System Generator version 12.1 VHDL source file. -- -- Copyright(C) 2010 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2010 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; library unisim; use unisim.vcomponents.all; entity kcpsm3 is Port ( address : out std_logic_vector(9 downto 0); instruction : in std_logic_vector(17 downto 0); port_id : out std_logic_vector(7 downto 0); write_strobe : out std_logic; out_port : out std_logic_vector(7 downto 0); read_strobe : out std_logic; in_port : in std_logic_vector(7 downto 0); interrupt : in std_logic; interrupt_ack : out std_logic; reset : in std_logic; clk : in std_logic); end kcpsm3; architecture low_level_definition of kcpsm3 is signal t_state : std_logic; signal not_t_state : std_logic; signal internal_reset : std_logic; signal reset_delay : std_logic; signal move_group : std_logic; signal condition_met : std_logic; signal normal_count : std_logic; signal call_type : std_logic; signal push_or_pop_type : std_logic; signal valid_to_move : std_logic; signal flag_type : std_logic; signal flag_write : std_logic; signal flag_enable : std_logic; signal zero_flag : std_logic; signal sel_shadow_zero : std_logic; signal low_zero : std_logic; signal high_zero : std_logic; signal low_zero_carry : std_logic; signal high_zero_carry : std_logic; signal zero_carry : std_logic; signal zero_fast_route : std_logic; signal low_parity : std_logic; signal high_parity : std_logic; signal parity_carry : std_logic; signal parity : std_logic; signal carry_flag : std_logic; signal sel_parity : std_logic; signal sel_arith_carry : std_logic; signal sel_shift_carry : std_logic; signal sel_shadow_carry : std_logic; signal sel_carry : std_logic_vector(3 downto 0); signal carry_fast_route : std_logic; signal active_interrupt : std_logic; signal int_pulse : std_logic; signal clean_int : std_logic; signal shadow_carry : std_logic; signal shadow_zero : std_logic; signal int_enable : std_logic; signal int_update_enable : std_logic; signal int_enable_value : std_logic; signal interrupt_ack_internal : std_logic; signal pc : std_logic_vector(9 downto 0); signal pc_vector : std_logic_vector(9 downto 0); signal pc_vector_carry : std_logic_vector(8 downto 0); signal inc_pc_vector : std_logic_vector(9 downto 0); signal pc_value : std_logic_vector(9 downto 0); signal pc_value_carry : std_logic_vector(8 downto 0); signal inc_pc_value : std_logic_vector(9 downto 0); signal pc_enable : std_logic; signal sx : std_logic_vector(7 downto 0); signal sy : std_logic_vector(7 downto 0); signal register_type : std_logic; signal register_write : std_logic; signal register_enable : std_logic; signal second_operand : std_logic_vector(7 downto 0); signal memory_data : std_logic_vector(7 downto 0); signal store_data : std_logic_vector(7 downto 0); signal memory_type : std_logic; signal memory_write : std_logic; signal memory_enable : std_logic; signal stack_pop_data : std_logic_vector(9 downto 0); signal stack_ram_data : std_logic_vector(9 downto 0); signal stack_address : std_logic_vector(4 downto 0); signal half_stack_address : std_logic_vector(4 downto 0); signal stack_address_carry : std_logic_vector(3 downto 0); signal next_stack_address : std_logic_vector(4 downto 0); signal stack_write_enable : std_logic; signal not_active_interrupt : std_logic; signal logical_result : std_logic_vector(7 downto 0); signal logical_value : std_logic_vector(7 downto 0); signal sel_logical : std_logic; signal shift_result : std_logic_vector(7 downto 0); signal shift_value : std_logic_vector(7 downto 0); signal sel_shift : std_logic; signal high_shift_in : std_logic; signal low_shift_in : std_logic; signal shift_in : std_logic; signal shift_carry : std_logic; signal shift_carry_value : std_logic; signal arith_result : std_logic_vector(7 downto 0); signal arith_value : std_logic_vector(7 downto 0); signal half_arith : std_logic_vector(7 downto 0); signal arith_internal_carry : std_logic_vector(7 downto 0); signal sel_arith_carry_in : std_logic; signal arith_carry_in : std_logic; signal invert_arith_carry : std_logic; signal arith_carry_out : std_logic; signal sel_arith : std_logic; signal arith_carry : std_logic; signal input_fetch_type : std_logic; signal sel_group : std_logic; signal alu_group : std_logic_vector(7 downto 0); signal input_group : std_logic_vector(7 downto 0); signal alu_result : std_logic_vector(7 downto 0); signal io_initial_decode : std_logic; signal write_active : std_logic; signal read_active : std_logic; attribute INIT : string; attribute INIT of t_state_lut : label is "1"; attribute INIT of int_pulse_lut : label is "0080"; attribute INIT of int_update_lut : label is "EAAA"; attribute INIT of int_value_lut : label is "04"; attribute INIT of move_group_lut : label is "7400"; attribute INIT of condition_met_lut : label is "5A3C"; attribute INIT of normal_count_lut : label is "2F"; attribute INIT of call_type_lut : label is "1000"; attribute INIT of push_pop_lut : label is "5400"; attribute INIT of valid_move_lut : label is "D"; attribute INIT of flag_type_lut : label is "41FC"; attribute INIT of flag_enable_lut : label is "8"; attribute INIT of low_zero_lut : label is "0001"; attribute INIT of high_zero_lut : label is "0001"; attribute INIT of sel_shadow_zero_lut : label is "3F"; attribute INIT of low_parity_lut : label is "6996"; attribute INIT of high_parity_lut : label is "6996"; attribute INIT of sel_parity_lut : label is "F3FF"; attribute INIT of sel_arith_carry_lut : label is "F3"; attribute INIT of sel_shift_carry_lut : label is "C"; attribute INIT of sel_shadow_carry_lut : label is "3"; attribute INIT of register_type_lut : label is "0145"; attribute INIT of register_enable_lut : label is "8"; attribute INIT of memory_type_lut : label is "0400"; attribute INIT of memory_enable_lut : label is "8000"; attribute INIT of sel_logical_lut : label is "FFE2"; attribute INIT of low_shift_in_lut : label is "E4"; attribute INIT of high_shift_in_lut : label is "E4"; attribute INIT of shift_carry_lut : label is "E4"; attribute INIT of sel_arith_lut : label is "1F"; attribute INIT of input_fetch_type_lut : label is "0002"; attribute INIT of io_decode_lut : label is "0010"; attribute INIT of write_active_lut : label is "4000"; attribute INIT of read_active_lut : label is "0100"; begin t_state_lut: LUT1 generic map (INIT => "01") port map( I0 => t_state, O => not_t_state ); toggle_flop: FDR port map ( D => not_t_state, Q => t_state, R => internal_reset, C => clk); reset_flop1: FDS port map ( D => '0', Q => reset_delay, S => reset, C => clk); reset_flop2: FDS port map ( D => reset_delay, Q => internal_reset, S => reset, C => clk); int_capture_flop: FDR port map ( D => interrupt, Q => clean_int, R => internal_reset, C => clk); int_pulse_lut: LUT4 generic map (INIT => X"0080") port map( I0 => t_state, I1 => clean_int, I2 => int_enable, I3 => active_interrupt, O => int_pulse ); int_flop: FDR port map ( D => int_pulse, Q => active_interrupt, R => internal_reset, C => clk); ack_flop: FD port map ( D => active_interrupt, Q => interrupt_ack_internal, C => clk); interrupt_ack <= interrupt_ack_internal; shadow_carry_flop: FDE port map ( D => carry_flag, Q => shadow_carry, CE => active_interrupt, C => clk); shadow_zero_flop: FDE port map ( D => zero_flag, Q => shadow_zero, CE => active_interrupt, C => clk); int_update_lut: LUT4 generic map (INIT => X"EAAA") port map( I0 => active_interrupt, I1 => instruction(15), I2 => instruction(16), I3 => instruction(17), O => int_update_enable ); int_value_lut: LUT3 generic map (INIT => X"04") port map( I0 => active_interrupt, I1 => instruction(0), I2 => interrupt_ack_internal, O => int_enable_value ); int_enable_flop: FDRE port map ( D => int_enable_value, Q => int_enable, CE => int_update_enable, R => internal_reset, C => clk); move_group_lut: LUT4 generic map (INIT => X"7400") port map( I0 => instruction(14), I1 => instruction(15), I2 => instruction(16), I3 => instruction(17), O => move_group ); condition_met_lut: LUT4 generic map (INIT => X"5A3C") port map( I0 => carry_flag, I1 => zero_flag, I2 => instruction(10), I3 => instruction(11), O => condition_met ); normal_count_lut: LUT3 generic map (INIT => X"2F") port map( I0 => instruction(12), I1 => condition_met, I2 => move_group, O => normal_count ); call_type_lut: LUT4 generic map (INIT => X"1000") port map( I0 => instruction(14), I1 => instruction(15), I2 => instruction(16), I3 => instruction(17), O => call_type ); push_pop_lut: LUT4 generic map (INIT => X"5400") port map( I0 => instruction(14), I1 => instruction(15), I2 => instruction(16), I3 => instruction(17), O => push_or_pop_type ); valid_move_lut: LUT2 generic map (INIT => X"D") port map( I0 => instruction(12), I1 => condition_met, O => valid_to_move ); flag_type_lut: LUT4 generic map (INIT => X"41FC") port map( I0 => instruction(14), I1 => instruction(15), I2 => instruction(16), I3 => instruction(17), O => flag_type ); flag_write_flop: FD port map ( D => flag_type, Q => flag_write, C => clk); flag_enable_lut: LUT2 generic map (INIT => X"8") port map( I0 => t_state, I1 => flag_write, O => flag_enable ); low_zero_lut: LUT4 generic map (INIT => X"0001") port map( I0 => alu_result(0), I1 => alu_result(1), I2 => alu_result(2), I3 => alu_result(3), O => low_zero ); high_zero_lut: LUT4 generic map (INIT => X"0001") port map( I0 => alu_result(4), I1 => alu_result(5), I2 => alu_result(6), I3 => alu_result(7), O => high_zero ); low_zero_muxcy: MUXCY port map( DI => '0', CI => '1', S => low_zero, O => low_zero_carry ); high_zero_cymux: MUXCY port map( DI => '0', CI => low_zero_carry, S => high_zero, O => high_zero_carry ); sel_shadow_zero_lut: LUT3 generic map (INIT => X"3F") port map( I0 => shadow_zero, I1 => instruction(16), I2 => instruction(17), O => sel_shadow_zero ); zero_cymux: MUXCY port map( DI => shadow_zero, CI => high_zero_carry, S => sel_shadow_zero, O => zero_carry ); zero_xor: XORCY port map( LI => '0', CI => zero_carry, O => zero_fast_route); zero_flag_flop: FDRE port map ( D => zero_fast_route, Q => zero_flag, CE => flag_enable, R => internal_reset, C => clk); low_parity_lut: LUT4 generic map (INIT => X"6996") port map( I0 => logical_result(0), I1 => logical_result(1), I2 => logical_result(2), I3 => logical_result(3), O => low_parity ); high_parity_lut: LUT4 generic map (INIT => X"6996") port map( I0 => logical_result(4), I1 => logical_result(5), I2 => logical_result(6), I3 => logical_result(7), O => high_parity ); parity_muxcy: MUXCY port map( DI => '0', CI => '1', S => low_parity, O => parity_carry ); parity_xor: XORCY port map( LI => high_parity, CI => parity_carry, O => parity); sel_parity_lut: LUT4 generic map (INIT => X"F3FF") port map( I0 => parity, I1 => instruction(13), I2 => instruction(15), I3 => instruction(16), O => sel_parity ); sel_arith_carry_lut: LUT3 generic map (INIT => X"F3") port map( I0 => arith_carry, I1 => instruction(16), I2 => instruction(17), O => sel_arith_carry ); sel_shift_carry_lut: LUT2 generic map (INIT => X"C") port map( I0 => shift_carry, I1 => instruction(15), O => sel_shift_carry ); sel_shadow_carry_lut: LUT2 generic map (INIT => X"3") port map( I0 => shadow_carry, I1 => instruction(17), O => sel_shadow_carry ); sel_shadow_muxcy: MUXCY port map( DI => shadow_carry, CI => '0', S => sel_shadow_carry, O => sel_carry(0) ); sel_shift_muxcy: MUXCY port map( DI => shift_carry, CI => sel_carry(0), S => sel_shift_carry, O => sel_carry(1) ); sel_arith_muxcy: MUXCY port map( DI => arith_carry, CI => sel_carry(1), S => sel_arith_carry, O => sel_carry(2) ); sel_parity_muxcy: MUXCY port map( DI => parity, CI => sel_carry(2), S => sel_parity, O => sel_carry(3) ); carry_xor: XORCY port map( LI => '0', CI => sel_carry(3), O => carry_fast_route); carry_flag_flop: FDRE port map ( D => carry_fast_route, Q => carry_flag, CE => flag_enable, R => internal_reset, C => clk); invert_enable: INV port map( I => t_state, O => pc_enable); pc_loop: for i in 0 to 9 generate attribute INIT : string; attribute INIT of vector_select_mux : label is "E4"; attribute INIT of value_select_mux : label is "E4"; begin vector_select_mux: LUT3 generic map (INIT => X"E4") port map( I0 => instruction(15), I1 => instruction(i), I2 => stack_pop_data(i), O => pc_vector(i) ); value_select_mux: LUT3 generic map (INIT => X"E4") port map( I0 => normal_count, I1 => inc_pc_vector(i), I2 => pc(i), O => pc_value(i) ); register_bit: FDRSE port map ( D => inc_pc_value(i), Q => pc(i), R => internal_reset, S => active_interrupt, CE => pc_enable, C => clk); pc_lsb_carry: if i=0 generate begin pc_vector_muxcy: MUXCY port map( DI => '0', CI => instruction(13), S => pc_vector(i), O => pc_vector_carry(i)); pc_vector_xor: XORCY port map( LI => pc_vector(i), CI => instruction(13), O => inc_pc_vector(i)); pc_value_muxcy: MUXCY port map( DI => '0', CI => normal_count, S => pc_value(i), O => pc_value_carry(i)); pc_value_xor: XORCY port map( LI => pc_value(i), CI => normal_count, O => inc_pc_value(i)); end generate pc_lsb_carry; pc_mid_carry: if i>0 and i<9 generate begin pc_vector_muxcy: MUXCY port map( DI => '0', CI => pc_vector_carry(i-1), S => pc_vector(i), O => pc_vector_carry(i)); pc_vector_xor: XORCY port map( LI => pc_vector(i), CI => pc_vector_carry(i-1), O => inc_pc_vector(i)); pc_value_muxcy: MUXCY port map( DI => '0', CI => pc_value_carry(i-1), S => pc_value(i), O => pc_value_carry(i)); pc_value_xor: XORCY port map( LI => pc_value(i), CI => pc_value_carry(i-1), O => inc_pc_value(i)); end generate pc_mid_carry; pc_msb_carry: if i=9 generate begin pc_vector_xor: XORCY port map( LI => pc_vector(i), CI => pc_vector_carry(i-1), O => inc_pc_vector(i)); pc_value_xor: XORCY port map( LI => pc_value(i), CI => pc_value_carry(i-1), O => inc_pc_value(i)); end generate pc_msb_carry; end generate pc_loop; address <= pc; register_type_lut: LUT4 generic map (INIT => X"0145") port map( I0 => active_interrupt, I1 => instruction(15), I2 => instruction(16), I3 => instruction(17), O => register_type ); register_write_flop: FD port map ( D => register_type, Q => register_write, C => clk); register_enable_lut: LUT2 generic map (INIT => X"8") port map( I0 => t_state, I1 => register_write, O => register_enable ); reg_loop: for i in 0 to 7 generate attribute INIT : string; attribute INIT of register_bit : label is "0000"; attribute INIT of operand_select_mux : label is "E4"; begin register_bit: RAM16X1D generic map(INIT => X"0000") port map ( D => alu_result(i), WE => register_enable, WCLK => clk, A0 => instruction(8), A1 => instruction(9), A2 => instruction(10), A3 => instruction(11), DPRA0 => instruction(4), DPRA1 => instruction(5), DPRA2 => instruction(6), DPRA3 => instruction(7), SPO => sx(i), DPO => sy(i)); operand_select_mux: LUT3 generic map (INIT => X"E4") port map( I0 => instruction(12), I1 => instruction(i), I2 => sy(i), O => second_operand(i) ); end generate reg_loop; out_port <= sx; port_id <= second_operand; memory_type_lut: LUT4 generic map (INIT => X"0400") port map( I0 => active_interrupt, I1 => instruction(15), I2 => instruction(16), I3 => instruction(17), O => memory_type ); memory_write_flop: FD port map ( D => memory_type, Q => memory_write, C => clk); memory_enable_lut: LUT4 generic map (INIT => X"8000") port map( I0 => t_state, I1 => instruction(13), I2 => instruction(14), I3 => memory_write, O => memory_enable ); store_loop: for i in 0 to 7 generate attribute INIT : string; attribute INIT of memory_bit : label is "0000000000000000"; begin memory_bit: RAM64X1S generic map(INIT => X"0000000000000000") port map ( D => sx(i), WE => memory_enable, WCLK => clk, A0 => second_operand(0), A1 => second_operand(1), A2 => second_operand(2), A3 => second_operand(3), A4 => second_operand(4), A5 => second_operand(5), O => memory_data(i)); store_flop: FD port map ( D => memory_data(i), Q => store_data(i), C => clk); end generate store_loop; sel_logical_lut: LUT4 generic map (INIT => X"FFE2") port map( I0 => instruction(14), I1 => instruction(15), I2 => instruction(16), I3 => instruction(17), O => sel_logical ); logical_loop: for i in 0 to 7 generate attribute INIT : string; attribute INIT of logical_lut : label is "6E8A"; begin logical_lut: LUT4 generic map (INIT => X"6E8A") port map( I0 => second_operand(i), I1 => sx(i), I2 => instruction(13), I3 => instruction(14), O => logical_value(i)); logical_flop: FDR port map ( D => logical_value(i), Q => logical_result(i), R => sel_logical, C => clk); end generate logical_loop; sel_shift_inv: INV port map( I => instruction(17), O => sel_shift); high_shift_in_lut: LUT3 generic map (INIT => X"E4") port map( I0 => instruction(1), I1 => sx(0), I2 => instruction(0), O => high_shift_in ); low_shift_in_lut: LUT3 generic map (INIT => X"E4") port map( I0 => instruction(1), I1 => carry_flag, I2 => sx(7), O => low_shift_in ); shift_in_muxf5: MUXF5 port map( I1 => high_shift_in, I0 => low_shift_in, S => instruction(2), O => shift_in ); shift_carry_lut: LUT3 generic map (INIT => X"E4") port map( I0 => instruction(3), I1 => sx(7), I2 => sx(0), O => shift_carry_value ); pipeline_bit: FD port map ( D => shift_carry_value, Q => shift_carry, C => clk); shift_loop: for i in 0 to 7 generate begin lsb_shift: if i=0 generate attribute INIT : string; attribute INIT of shift_mux_lut : label is "E4"; begin shift_mux_lut: LUT3 generic map (INIT => X"E4") port map( I0 => instruction(3), I1 => shift_in, I2 => sx(i+1), O => shift_value(i) ); end generate lsb_shift; mid_shift: if i>0 and i<7 generate attribute INIT : string; attribute INIT of shift_mux_lut : label is "E4"; begin shift_mux_lut: LUT3 generic map (INIT => X"E4") port map( I0 => instruction(3), I1 => sx(i-1), I2 => sx(i+1), O => shift_value(i) ); end generate mid_shift; msb_shift: if i=7 generate attribute INIT : string; attribute INIT of shift_mux_lut : label is "E4"; begin shift_mux_lut: LUT3 generic map (INIT => X"E4") port map( I0 => instruction(3), I1 => sx(i-1), I2 => shift_in, O => shift_value(i) ); end generate msb_shift; shift_flop: FDR port map ( D => shift_value(i), Q => shift_result(i), R => sel_shift, C => clk); end generate shift_loop; sel_arith_lut: LUT3 generic map (INIT => X"1F") port map( I0 => instruction(14), I1 => instruction(15), I2 => instruction(16), O => sel_arith ); arith_loop: for i in 0 to 7 generate attribute INIT : string; attribute INIT of arith_lut : label is "96"; begin lsb_arith: if i=0 generate attribute INIT : string; attribute INIT of arith_carry_in_lut : label is "6C"; begin arith_carry_in_lut: LUT3 generic map (INIT => X"6C") port map( I0 => instruction(13), I1 => instruction(14), I2 => carry_flag, O => sel_arith_carry_in ); arith_carry_in_muxcy: MUXCY port map( DI => '0', CI => '1', S => sel_arith_carry_in, O => arith_carry_in); arith_muxcy: MUXCY port map( DI => sx(i), CI => arith_carry_in, S => half_arith(i), O => arith_internal_carry(i)); arith_xor: XORCY port map( LI => half_arith(i), CI => arith_carry_in, O => arith_value(i)); end generate lsb_arith; mid_arith: if i>0 and i<7 generate begin arith_muxcy: MUXCY port map( DI => sx(i), CI => arith_internal_carry(i-1), S => half_arith(i), O => arith_internal_carry(i)); arith_xor: XORCY port map( LI => half_arith(i), CI => arith_internal_carry(i-1), O => arith_value(i)); end generate mid_arith; msb_arith: if i=7 generate attribute INIT : string; attribute INIT of arith_carry_out_lut : label is "2"; begin arith_muxcy: MUXCY port map( DI => sx(i), CI => arith_internal_carry(i-1), S => half_arith(i), O => arith_internal_carry(i)); arith_xor: XORCY port map( LI => half_arith(i), CI => arith_internal_carry(i-1), O => arith_value(i)); arith_carry_out_lut: LUT1 generic map (INIT => "10") port map( I0 => instruction(14), O => invert_arith_carry ); arith_carry_out_xor: XORCY port map( LI => invert_arith_carry, CI => arith_internal_carry(i), O => arith_carry_out); arith_carry_flop: FDR port map ( D => arith_carry_out, Q => arith_carry, R => sel_arith, C => clk); end generate msb_arith; arith_lut: LUT3 generic map (INIT => X"96") port map( I0 => sx(i), I1 => second_operand(i), I2 => instruction(14), O => half_arith(i)); arith_flop: FDR port map ( D => arith_value(i), Q => arith_result(i), R => sel_arith, C => clk); end generate arith_loop; input_fetch_type_lut: LUT4 generic map (INIT => X"0002") port map( I0 => instruction(14), I1 => instruction(15), I2 => instruction(16), I3 => instruction(17), O => input_fetch_type ); sel_group_flop: FD port map ( D => input_fetch_type, Q => sel_group, C => clk); alu_mux_loop: for i in 0 to 7 generate attribute INIT : string; attribute INIT of or_lut : label is "FE"; attribute INIT of mux_lut : label is "E4"; begin or_lut: LUT3 generic map (INIT => X"FE") port map( I0 => logical_result(i), I1 => arith_result(i), I2 => shift_result(i), O => alu_group(i)); mux_lut: LUT3 generic map (INIT => X"E4") port map( I0 => instruction(13), I1 => in_port(i), I2 => store_data(i), O => input_group(i)); shift_in_muxf5: MUXF5 port map( I1 => input_group(i), I0 => alu_group(i), S => sel_group, O => alu_result(i) ); end generate alu_mux_loop; io_decode_lut: LUT4 generic map (INIT => X"0010") port map( I0 => active_interrupt, I1 => instruction(13), I2 => instruction(14), I3 => instruction(16), O => io_initial_decode ); write_active_lut: LUT4 generic map (INIT => X"4000") port map( I0 => t_state, I1 => instruction(15), I2 => instruction(17), I3 => io_initial_decode, O => write_active ); write_strobe_flop: FDR port map ( D => write_active, Q => write_strobe, R => internal_reset, C => clk); read_active_lut: LUT4 generic map (INIT => X"0100") port map( I0 => t_state, I1 => instruction(15), I2 => instruction(17), I3 => io_initial_decode, O => read_active ); read_strobe_flop: FDR port map ( D => read_active, Q => read_strobe, R => internal_reset, C => clk); stack_ram_inv: INV port map( I => t_state, O => stack_write_enable); stack_ram_loop: for i in 0 to 9 generate attribute INIT : string; attribute INIT of stack_bit : label is "00000000"; begin stack_bit: RAM32X1S generic map(INIT => X"00000000") port map ( D => pc(i), WE => stack_write_enable, WCLK => clk, A0 => stack_address(0), A1 => stack_address(1), A2 => stack_address(2), A3 => stack_address(3), A4 => stack_address(4), O => stack_ram_data(i)); stack_flop: FD port map ( D => stack_ram_data(i), Q => stack_pop_data(i), C => clk); end generate stack_ram_loop; stack_count_inv: INV port map( I => active_interrupt, O => not_active_interrupt); stack_count_loop: for i in 0 to 4 generate begin register_bit: FDRE port map ( D => next_stack_address(i), Q => stack_address(i), R => internal_reset, CE => not_active_interrupt, C => clk); lsb_stack_count: if i=0 generate attribute INIT : string; attribute INIT of count_lut : label is "6555"; begin count_lut: LUT4 generic map (INIT => X"6555") port map( I0 => stack_address(i), I1 => t_state, I2 => valid_to_move, I3 => push_or_pop_type, O => half_stack_address(i) ); count_muxcy: MUXCY port map( DI => stack_address(i), CI => '0', S => half_stack_address(i), O => stack_address_carry(i)); count_xor: XORCY port map( LI => half_stack_address(i), CI => '0', O => next_stack_address(i)); end generate lsb_stack_count; mid_stack_count: if i>0 and i<4 generate attribute INIT : string; attribute INIT of count_lut : label is "A999"; begin count_lut: LUT4 generic map (INIT => X"A999") port map( I0 => stack_address(i), I1 => t_state, I2 => valid_to_move, I3 => call_type, O => half_stack_address(i) ); count_muxcy: MUXCY port map( DI => stack_address(i), CI => stack_address_carry(i-1), S => half_stack_address(i), O => stack_address_carry(i)); count_xor: XORCY port map( LI => half_stack_address(i), CI => stack_address_carry(i-1), O => next_stack_address(i)); end generate mid_stack_count; msb_stack_count: if i=4 generate attribute INIT : string; attribute INIT of count_lut : label is "A999"; begin count_lut: LUT4 generic map (INIT => X"A999") port map( I0 => stack_address(i), I1 => t_state, I2 => valid_to_move, I3 => call_type, O => half_stack_address(i) ); count_xor: XORCY port map( LI => half_stack_address(i), CI => stack_address_carry(i-1), O => next_stack_address(i)); end generate msb_stack_count; end generate stack_count_loop; simulation: process (clk, instruction) variable kcpsm3_opcode : string(1 to 19); variable kcpsm3_status : string(1 to 13):= "NZ, NC, Reset"; variable s0_contents : std_logic_vector(7 downto 0):=X"00"; variable s1_contents : std_logic_vector(7 downto 0):=X"00"; variable s2_contents : std_logic_vector(7 downto 0):=X"00"; variable s3_contents : std_logic_vector(7 downto 0):=X"00"; variable s4_contents : std_logic_vector(7 downto 0):=X"00"; variable s5_contents : std_logic_vector(7 downto 0):=X"00"; variable s6_contents : std_logic_vector(7 downto 0):=X"00"; variable s7_contents : std_logic_vector(7 downto 0):=X"00"; variable s8_contents : std_logic_vector(7 downto 0):=X"00"; variable s9_contents : std_logic_vector(7 downto 0):=X"00"; variable sa_contents : std_logic_vector(7 downto 0):=X"00"; variable sb_contents : std_logic_vector(7 downto 0):=X"00"; variable sc_contents : std_logic_vector(7 downto 0):=X"00"; variable sd_contents : std_logic_vector(7 downto 0):=X"00"; variable se_contents : std_logic_vector(7 downto 0):=X"00"; variable sf_contents : std_logic_vector(7 downto 0):=X"00"; variable spm00_contents : std_logic_vector(7 downto 0):=X"00"; variable spm01_contents : std_logic_vector(7 downto 0):=X"00"; variable spm02_contents : std_logic_vector(7 downto 0):=X"00"; variable spm03_contents : std_logic_vector(7 downto 0):=X"00"; variable spm04_contents : std_logic_vector(7 downto 0):=X"00"; variable spm05_contents : std_logic_vector(7 downto 0):=X"00"; variable spm06_contents : std_logic_vector(7 downto 0):=X"00"; variable spm07_contents : std_logic_vector(7 downto 0):=X"00"; variable spm08_contents : std_logic_vector(7 downto 0):=X"00"; variable spm09_contents : std_logic_vector(7 downto 0):=X"00"; variable spm0a_contents : std_logic_vector(7 downto 0):=X"00"; variable spm0b_contents : std_logic_vector(7 downto 0):=X"00"; variable spm0c_contents : std_logic_vector(7 downto 0):=X"00"; variable spm0d_contents : std_logic_vector(7 downto 0):=X"00"; variable spm0e_contents : std_logic_vector(7 downto 0):=X"00"; variable spm0f_contents : std_logic_vector(7 downto 0):=X"00"; variable spm10_contents : std_logic_vector(7 downto 0):=X"00"; variable spm11_contents : std_logic_vector(7 downto 0):=X"00"; variable spm12_contents : std_logic_vector(7 downto 0):=X"00"; variable spm13_contents : std_logic_vector(7 downto 0):=X"00"; variable spm14_contents : std_logic_vector(7 downto 0):=X"00"; variable spm15_contents : std_logic_vector(7 downto 0):=X"00"; variable spm16_contents : std_logic_vector(7 downto 0):=X"00"; variable spm17_contents : std_logic_vector(7 downto 0):=X"00"; variable spm18_contents : std_logic_vector(7 downto 0):=X"00"; variable spm19_contents : std_logic_vector(7 downto 0):=X"00"; variable spm1a_contents : std_logic_vector(7 downto 0):=X"00"; variable spm1b_contents : std_logic_vector(7 downto 0):=X"00"; variable spm1c_contents : std_logic_vector(7 downto 0):=X"00"; variable spm1d_contents : std_logic_vector(7 downto 0):=X"00"; variable spm1e_contents : std_logic_vector(7 downto 0):=X"00"; variable spm1f_contents : std_logic_vector(7 downto 0):=X"00"; variable spm20_contents : std_logic_vector(7 downto 0):=X"00"; variable spm21_contents : std_logic_vector(7 downto 0):=X"00"; variable spm22_contents : std_logic_vector(7 downto 0):=X"00"; variable spm23_contents : std_logic_vector(7 downto 0):=X"00"; variable spm24_contents : std_logic_vector(7 downto 0):=X"00"; variable spm25_contents : std_logic_vector(7 downto 0):=X"00"; variable spm26_contents : std_logic_vector(7 downto 0):=X"00"; variable spm27_contents : std_logic_vector(7 downto 0):=X"00"; variable spm28_contents : std_logic_vector(7 downto 0):=X"00"; variable spm29_contents : std_logic_vector(7 downto 0):=X"00"; variable spm2a_contents : std_logic_vector(7 downto 0):=X"00"; variable spm2b_contents : std_logic_vector(7 downto 0):=X"00"; variable spm2c_contents : std_logic_vector(7 downto 0):=X"00"; variable spm2d_contents : std_logic_vector(7 downto 0):=X"00"; variable spm2e_contents : std_logic_vector(7 downto 0):=X"00"; variable spm2f_contents : std_logic_vector(7 downto 0):=X"00"; variable spm30_contents : std_logic_vector(7 downto 0):=X"00"; variable spm31_contents : std_logic_vector(7 downto 0):=X"00"; variable spm32_contents : std_logic_vector(7 downto 0):=X"00"; variable spm33_contents : std_logic_vector(7 downto 0):=X"00"; variable spm34_contents : std_logic_vector(7 downto 0):=X"00"; variable spm35_contents : std_logic_vector(7 downto 0):=X"00"; variable spm36_contents : std_logic_vector(7 downto 0):=X"00"; variable spm37_contents : std_logic_vector(7 downto 0):=X"00"; variable spm38_contents : std_logic_vector(7 downto 0):=X"00"; variable spm39_contents : std_logic_vector(7 downto 0):=X"00"; variable spm3a_contents : std_logic_vector(7 downto 0):=X"00"; variable spm3b_contents : std_logic_vector(7 downto 0):=X"00"; variable spm3c_contents : std_logic_vector(7 downto 0):=X"00"; variable spm3d_contents : std_logic_vector(7 downto 0):=X"00"; variable spm3e_contents : std_logic_vector(7 downto 0):=X"00"; variable spm3f_contents : std_logic_vector(7 downto 0):=X"00"; variable sx_decode : string(1 to 2); variable sy_decode : string(1 to 2); variable kk_decode : string(1 to 2); variable aaa_decode : string(1 to 3); function hexcharacter (nibble: std_logic_vector(3 downto 0)) return character is variable hex: character; begin case nibble is when "0000" => hex := '0'; when "0001" => hex := '1'; when "0010" => hex := '2'; when "0011" => hex := '3'; when "0100" => hex := '4'; when "0101" => hex := '5'; when "0110" => hex := '6'; when "0111" => hex := '7'; when "1000" => hex := '8'; when "1001" => hex := '9'; when "1010" => hex := 'A'; when "1011" => hex := 'B'; when "1100" => hex := 'C'; when "1101" => hex := 'D'; when "1110" => hex := 'E'; when "1111" => hex := 'F'; when others => hex := 'x'; end case; return hex; end hexcharacter; begin sx_decode(1) := 's'; sx_decode(2) := hexcharacter(instruction(11 downto 8)); sy_decode(1) := 's'; sy_decode(2) := hexcharacter(instruction(7 downto 4)); kk_decode(1) := hexcharacter(instruction(7 downto 4)); kk_decode(2) := hexcharacter(instruction(3 downto 0)); aaa_decode(1) := hexcharacter("00" & instruction(9 downto 8)); aaa_decode(2) := hexcharacter(instruction(7 downto 4)); aaa_decode(3) := hexcharacter(instruction(3 downto 0)); case instruction(17 downto 12) is when "000000" => kcpsm3_opcode := "LOAD " & sx_decode & ',' & kk_decode & " "; when "000001" => kcpsm3_opcode := "LOAD " & sx_decode & ',' & sy_decode & " "; when "001010" => kcpsm3_opcode := "AND " & sx_decode & ',' & kk_decode & " "; when "001011" => kcpsm3_opcode := "AND " & sx_decode & ',' & sy_decode & " "; when "001100" => kcpsm3_opcode := "OR " & sx_decode & ',' & kk_decode & " "; when "001101" => kcpsm3_opcode := "OR " & sx_decode & ',' & sy_decode & " "; when "001110" => kcpsm3_opcode := "XOR " & sx_decode & ',' & kk_decode & " "; when "001111" => kcpsm3_opcode := "XOR " & sx_decode & ',' & sy_decode & " "; when "010010" => kcpsm3_opcode := "TEST " & sx_decode & ',' & kk_decode & " "; when "010011" => kcpsm3_opcode := "TEST " & sx_decode & ',' & sy_decode & " "; when "011000" => kcpsm3_opcode := "ADD " & sx_decode & ',' & kk_decode & " "; when "011001" => kcpsm3_opcode := "ADD " & sx_decode & ',' & sy_decode & " "; when "011010" => kcpsm3_opcode := "ADDCY " & sx_decode & ',' & kk_decode & " "; when "011011" => kcpsm3_opcode := "ADDCY " & sx_decode & ',' & sy_decode & " "; when "011100" => kcpsm3_opcode := "SUB " & sx_decode & ',' & kk_decode & " "; when "011101" => kcpsm3_opcode := "SUB " & sx_decode & ',' & sy_decode & " "; when "011110" => kcpsm3_opcode := "SUBCY " & sx_decode & ',' & kk_decode & " "; when "011111" => kcpsm3_opcode := "SUBCY " & sx_decode & ',' & sy_decode & " "; when "010100" => kcpsm3_opcode := "COMPARE " & sx_decode & ',' & kk_decode & " "; when "010101" => kcpsm3_opcode := "COMPARE " & sx_decode & ',' & sy_decode & " "; when "100000" => case instruction(3 downto 0) is when "0110" => kcpsm3_opcode := "SL0 " & sx_decode & " "; when "0111" => kcpsm3_opcode := "SL1 " & sx_decode & " "; when "0100" => kcpsm3_opcode := "SLX " & sx_decode & " "; when "0000" => kcpsm3_opcode := "SLA " & sx_decode & " "; when "0010" => kcpsm3_opcode := "RL " & sx_decode & " "; when "1110" => kcpsm3_opcode := "SR0 " & sx_decode & " "; when "1111" => kcpsm3_opcode := "SR1 " & sx_decode & " "; when "1010" => kcpsm3_opcode := "SRX " & sx_decode & " "; when "1000" => kcpsm3_opcode := "SRA " & sx_decode & " "; when "1100" => kcpsm3_opcode := "RR " & sx_decode & " "; when others => kcpsm3_opcode := "Invalid Instruction"; end case; when "101100" => kcpsm3_opcode := "OUTPUT " & sx_decode & ',' & kk_decode & " "; when "101101" => kcpsm3_opcode := "OUTPUT " & sx_decode & ",(" & sy_decode & ") "; when "000100" => kcpsm3_opcode := "INPUT " & sx_decode & ',' & kk_decode & " "; when "000101" => kcpsm3_opcode := "INPUT " & sx_decode & ",(" & sy_decode & ") "; when "101110" => kcpsm3_opcode := "STORE " & sx_decode & ',' & kk_decode & " "; when "101111" => kcpsm3_opcode := "STORE " & sx_decode & ",(" & sy_decode & ") "; when "000110" => kcpsm3_opcode := "FETCH " & sx_decode & ',' & kk_decode & " "; when "000111" => kcpsm3_opcode := "FETCH " & sx_decode & ",(" & sy_decode & ") "; when "110100" => kcpsm3_opcode := "JUMP " & aaa_decode & " "; when "110101" => case instruction(11 downto 10) is when "00" => kcpsm3_opcode := "JUMP Z," & aaa_decode & " "; when "01" => kcpsm3_opcode := "JUMP NZ," & aaa_decode & " "; when "10" => kcpsm3_opcode := "JUMP C," & aaa_decode & " "; when "11" => kcpsm3_opcode := "JUMP NC," & aaa_decode & " "; when others => kcpsm3_opcode := "Invalid Instruction"; end case; when "110000" => kcpsm3_opcode := "CALL " & aaa_decode & " "; when "110001" => case instruction(11 downto 10) is when "00" => kcpsm3_opcode := "CALL Z," & aaa_decode & " "; when "01" => kcpsm3_opcode := "CALL NZ," & aaa_decode & " "; when "10" => kcpsm3_opcode := "CALL C," & aaa_decode & " "; when "11" => kcpsm3_opcode := "CALL NC," & aaa_decode & " "; when others => kcpsm3_opcode := "Invalid Instruction"; end case; when "101010" => kcpsm3_opcode := "RETURN "; when "101011" => case instruction(11 downto 10) is when "00" => kcpsm3_opcode := "RETURN Z "; when "01" => kcpsm3_opcode := "RETURN NZ "; when "10" => kcpsm3_opcode := "RETURN C "; when "11" => kcpsm3_opcode := "RETURN NC "; when others => kcpsm3_opcode := "Invalid Instruction"; end case; when "111000" => case instruction(0) is when '0' => kcpsm3_opcode := "RETURNI DISABLE "; when '1' => kcpsm3_opcode := "RETURNI ENABLE "; when others => kcpsm3_opcode := "Invalid Instruction"; end case; when "111100" => case instruction(0) is when '0' => kcpsm3_opcode := "DISABLE INTERRUPT "; when '1' => kcpsm3_opcode := "ENABLE INTERRUPT "; when others => kcpsm3_opcode := "Invalid Instruction"; end case; when others => kcpsm3_opcode := "Invalid Instruction"; end case; if clk'event and clk='1' then if reset='1' or reset_delay='1' then kcpsm3_status := "NZ, NC, Reset"; else kcpsm3_status(7 to 13) := " "; if flag_enable='1' then if zero_carry='1' then kcpsm3_status(1 to 4) := " Z, "; else kcpsm3_status(1 to 4) := "NZ, "; end if; if sel_carry(3)='1' then kcpsm3_status(5 to 6) := " C"; else kcpsm3_status(5 to 6) := "NC"; end if; end if; end if; if register_enable='1' then case instruction(11 downto 8) is when "0000" => s0_contents := alu_result; when "0001" => s1_contents := alu_result; when "0010" => s2_contents := alu_result; when "0011" => s3_contents := alu_result; when "0100" => s4_contents := alu_result; when "0101" => s5_contents := alu_result; when "0110" => s6_contents := alu_result; when "0111" => s7_contents := alu_result; when "1000" => s8_contents := alu_result; when "1001" => s9_contents := alu_result; when "1010" => sa_contents := alu_result; when "1011" => sb_contents := alu_result; when "1100" => sc_contents := alu_result; when "1101" => sd_contents := alu_result; when "1110" => se_contents := alu_result; when "1111" => sf_contents := alu_result; when others => null; end case; end if; if memory_enable='1' then case second_operand(5 downto 0) is when "000000" => spm00_contents := sx; when "000001" => spm01_contents := sx; when "000010" => spm02_contents := sx; when "000011" => spm03_contents := sx; when "000100" => spm04_contents := sx; when "000101" => spm05_contents := sx; when "000110" => spm06_contents := sx; when "000111" => spm07_contents := sx; when "001000" => spm08_contents := sx; when "001001" => spm09_contents := sx; when "001010" => spm0a_contents := sx; when "001011" => spm0b_contents := sx; when "001100" => spm0c_contents := sx; when "001101" => spm0d_contents := sx; when "001110" => spm0e_contents := sx; when "001111" => spm0f_contents := sx; when "010000" => spm10_contents := sx; when "010001" => spm11_contents := sx; when "010010" => spm12_contents := sx; when "010011" => spm13_contents := sx; when "010100" => spm14_contents := sx; when "010101" => spm15_contents := sx; when "010110" => spm16_contents := sx; when "010111" => spm17_contents := sx; when "011000" => spm18_contents := sx; when "011001" => spm19_contents := sx; when "011010" => spm1a_contents := sx; when "011011" => spm1b_contents := sx; when "011100" => spm1c_contents := sx; when "011101" => spm1d_contents := sx; when "011110" => spm1e_contents := sx; when "011111" => spm1f_contents := sx; when "100000" => spm20_contents := sx; when "100001" => spm21_contents := sx; when "100010" => spm22_contents := sx; when "100011" => spm23_contents := sx; when "100100" => spm24_contents := sx; when "100101" => spm25_contents := sx; when "100110" => spm26_contents := sx; when "100111" => spm27_contents := sx; when "101000" => spm28_contents := sx; when "101001" => spm29_contents := sx; when "101010" => spm2a_contents := sx; when "101011" => spm2b_contents := sx; when "101100" => spm2c_contents := sx; when "101101" => spm2d_contents := sx; when "101110" => spm2e_contents := sx; when "101111" => spm2f_contents := sx; when "110000" => spm30_contents := sx; when "110001" => spm31_contents := sx; when "110010" => spm32_contents := sx; when "110011" => spm33_contents := sx; when "110100" => spm34_contents := sx; when "110101" => spm35_contents := sx; when "110110" => spm36_contents := sx; when "110111" => spm37_contents := sx; when "111000" => spm38_contents := sx; when "111001" => spm39_contents := sx; when "111010" => spm3a_contents := sx; when "111011" => spm3b_contents := sx; when "111100" => spm3c_contents := sx; when "111101" => spm3d_contents := sx; when "111110" => spm3e_contents := sx; when "111111" => spm3f_contents := sx; when others => null; end case; end if; end if; end process simulation; end low_level_definition; ------------------------------------------------------------------- -- System Generator version 12.1 VHDL source file. -- -- Copyright(C) 2010 by Xilinx, Inc. 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You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2010 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; entity xlpb3 is port ( in_port: in std_logic_vector(7 downto 0); interrupt: in std_logic_vector(0 downto 0); reset: in std_logic_vector(0 downto 0); instruction: in std_logic_vector(17 downto 0); clk: in std_logic; ce: in std_logic; out_port: out std_logic_vector(7 downto 0); port_id: out std_logic_vector(7 downto 0); read_strobe: out std_logic_vector(0 downto 0); write_strobe: out std_logic_vector(0 downto 0); interrupt_ack: out std_logic_vector(0 downto 0); address: out std_logic_vector(9 downto 0) ); end xlpb3; architecture behavior of xlpb3 is component kcpsm3 Port ( address : out std_logic_vector(9 downto 0); instruction : in std_logic_vector(17 downto 0); port_id : out std_logic_vector(7 downto 0); write_strobe : out std_logic; out_port : out std_logic_vector(7 downto 0); read_strobe : out std_logic; in_port : in std_logic_vector(7 downto 0); interrupt : in std_logic; interrupt_ack : out std_logic; reset : in std_logic; clk : in std_logic); end component; begin proc_inst: kcpsm3 port map ( address => address, clk => clk, in_port => in_port, instruction => instruction, interrupt => interrupt(0), out_port => out_port, port_id => port_id, read_strobe => read_strobe(0), reset => reset(0), interrupt_ack => interrupt_ack(0), write_strobe => write_strobe(0) ); end architecture behavior; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; -- Generated from Simulink block "sg_i2c_controller_s6/EDK Processor" entity edk_processor_entity_f7392c68af is port ( from_fifo: in std_logic_vector(31 downto 0); from_fifo_x0: in std_logic; from_fifo_x1: in std_logic; plb_abus: in std_logic_vector(31 downto 0); plb_ce_1: in std_logic; plb_clk_1: in std_logic; plb_pavalid: in std_logic; plb_rnw: in std_logic; plb_wrdbus: in std_logic_vector(31 downto 0); sg_plb_addrpref: in std_logic_vector(19 downto 0); splb_rst: in std_logic; to_fifo: in std_logic; to_fifo_x0: in std_logic; to_register: in std_logic_vector(7 downto 0); constant5_x0: out std_logic; plb_decode_x0: out std_logic; plb_decode_x1: out std_logic; plb_decode_x2: out std_logic; plb_decode_x3: out std_logic; plb_decode_x4: out std_logic_vector(31 downto 0); plb_memmap_x0: out std_logic_vector(7 downto 0); plb_memmap_x1: out std_logic; plb_memmap_x2: out std_logic; plb_memmap_x3: out std_logic_vector(31 downto 0); plb_memmap_x4: out std_logic ); end edk_processor_entity_f7392c68af; architecture structural of edk_processor_entity_f7392c68af is signal bankaddr: std_logic_vector(1 downto 0); signal cmd_request_din_x0: std_logic_vector(31 downto 0); signal cmd_request_full_x0: std_logic; signal cmd_request_pfull_x0: std_logic; signal cmd_request_we_x0: std_logic; signal cmd_response_dout_x0: std_logic_vector(31 downto 0); signal cmd_response_empty_x0: std_logic; signal cmd_response_pfull_x0: std_logic; signal cmd_response_re_x0: std_logic; signal gpio_out8_din_x0: std_logic_vector(7 downto 0); signal gpio_out8_dout_x0: std_logic_vector(7 downto 0); signal gpio_out8_en_x0: std_logic; signal linearaddr: std_logic_vector(7 downto 0); signal plb_abus_net_x0: std_logic_vector(31 downto 0); signal plb_ce_1_sg_x0: std_logic; signal plb_clk_1_sg_x0: std_logic; signal plb_pavalid_net_x0: std_logic; signal plb_rnw_net_x0: std_logic; signal plb_wrdbus_net_x0: std_logic_vector(31 downto 0); signal rddata: std_logic_vector(31 downto 0); signal rnwreg: std_logic; signal sg_plb_addrpref_net_x0: std_logic_vector(19 downto 0); signal sl_addrack_x0: std_logic; signal sl_rdcomp_x0: std_logic; signal sl_rddack_x0: std_logic; signal sl_rddbus_x0: std_logic_vector(31 downto 0); signal sl_wait_x0: std_logic; signal sl_wrdack_x0: std_logic; signal splb_rst_net_x0: std_logic; signal wrdbusreg: std_logic_vector(31 downto 0); begin cmd_response_dout_x0 <= from_fifo; cmd_response_pfull_x0 <= from_fifo_x0; cmd_response_empty_x0 <= from_fifo_x1; plb_abus_net_x0 <= plb_abus; plb_ce_1_sg_x0 <= plb_ce_1; plb_clk_1_sg_x0 <= plb_clk_1; plb_pavalid_net_x0 <= plb_pavalid; plb_rnw_net_x0 <= plb_rnw; plb_wrdbus_net_x0 <= plb_wrdbus; sg_plb_addrpref_net_x0 <= sg_plb_addrpref; splb_rst_net_x0 <= splb_rst; cmd_request_pfull_x0 <= to_fifo; cmd_request_full_x0 <= to_fifo_x0; gpio_out8_dout_x0 <= to_register; constant5_x0 <= sl_wait_x0; plb_decode_x0 <= sl_addrack_x0; plb_decode_x1 <= sl_rdcomp_x0; plb_decode_x2 <= sl_wrdack_x0; plb_decode_x3 <= sl_rddack_x0; plb_decode_x4 <= sl_rddbus_x0; plb_memmap_x0 <= gpio_out8_din_x0; plb_memmap_x1 <= gpio_out8_en_x0; plb_memmap_x2 <= cmd_response_re_x0; plb_memmap_x3 <= cmd_request_din_x0; plb_memmap_x4 <= cmd_request_we_x0; constant5: entity work.constant_963ed6358a port map ( ce => '0', clk => '0', clr => '0', op(0) => sl_wait_x0 ); plb_decode: entity work.mcode_block_f4d0462e0e port map ( addrpref => sg_plb_addrpref_net_x0, ce => plb_ce_1_sg_x0, clk => plb_clk_1_sg_x0, clr => '0', plbabus => plb_abus_net_x0, plbpavalid(0) => plb_pavalid_net_x0, plbrnw(0) => plb_rnw_net_x0, plbrst(0) => splb_rst_net_x0, plbwrdbus => plb_wrdbus_net_x0, rddata => rddata, addrack(0) => sl_addrack_x0, bankaddr => bankaddr, linearaddr => linearaddr, rdcomp(0) => sl_rdcomp_x0, rddack(0) => sl_rddack_x0, rddbus => sl_rddbus_x0, rnwreg(0) => rnwreg, wrdack(0) => sl_wrdack_x0, wrdbusreg => wrdbusreg ); plb_memmap: entity work.mcode_block_57a988c97d port map ( addrack(0) => sl_addrack_x0, bankaddr => bankaddr, ce => plb_ce_1_sg_x0, clk => plb_clk_1_sg_x0, clr => '0', linearaddr => linearaddr, rnwreg(0) => rnwreg, sm_cmd_request_full(0) => cmd_request_full_x0, sm_cmd_request_pfull(0) => cmd_request_pfull_x0, sm_cmd_response => cmd_response_dout_x0, sm_cmd_response_empty(0) => cmd_response_empty_x0, sm_cmd_response_pfull(0) => cmd_response_pfull_x0, sm_gpio_out8 => gpio_out8_dout_x0, wrdbus => wrdbusreg, read_bank_out => rddata, sm_cmd_request_din => cmd_request_din_x0, sm_cmd_request_we(0) => cmd_request_we_x0, sm_cmd_response_re(0) => cmd_response_re_x0, sm_gpio_out8_din => gpio_out8_din_x0, sm_gpio_out8_en(0) => gpio_out8_en_x0 ); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; -- Generated from Simulink block "sg_i2c_controller_s6/i2c_controller" entity i2c_controller_entity_e098cd9e07 is port ( ce_1: in std_logic; clk_1: in std_logic; cmd_req_x0: in std_logic_vector(31 downto 0); from_fifo: in std_logic; sda_i: in std_logic; mcode_x0: out std_logic; mcode_x1: out std_logic_vector(31 downto 0); mcode_x2: out std_logic; scl_o_x0: out std_logic; sda_o_x0: out std_logic ); end i2c_controller_entity_e098cd9e07; architecture structural of i2c_controller_entity_e098cd9e07 is signal ce_1_sg_x0: std_logic; signal clk_1_sg_x0: std_logic; signal cmd_ack_x0: std_logic; signal cmd_get_x0: std_logic; signal cmd_rdy: std_logic; signal cmd_req_x1: std_logic_vector(31 downto 0); signal cmd_rsp_x0: std_logic_vector(31 downto 0); signal constant10_op_net: std_logic; signal constant1_op_net: std_logic; signal from_fifo_empty_net_x0: std_logic; signal i2c_sda_i_net_x0: std_logic; signal in_port: std_logic_vector(7 downto 0); signal out_port: std_logic_vector(7 downto 0); signal picoblaze_microcontroller_address_net: std_logic_vector(9 downto 0); signal picoblaze_rom_data_net: std_logic_vector(17 downto 0); signal port_id: std_logic_vector(7 downto 0); signal rs: std_logic; signal scl_o_x1: std_logic; signal sda_o_x1: std_logic; signal ws: std_logic; begin ce_1_sg_x0 <= ce_1; clk_1_sg_x0 <= clk_1; cmd_req_x1 <= cmd_req_x0; from_fifo_empty_net_x0 <= from_fifo; i2c_sda_i_net_x0 <= sda_i; mcode_x0 <= cmd_get_x0; mcode_x1 <= cmd_rsp_x0; mcode_x2 <= cmd_ack_x0; scl_o_x0 <= scl_o_x1; sda_o_x0 <= sda_o_x1; constant1: entity work.constant_963ed6358a port map ( ce => '0', clk => '0', clr => '0', op(0) => constant1_op_net ); constant10: entity work.constant_963ed6358a port map ( ce => '0', clk => '0', clr => '0', op(0) => constant10_op_net ); inverter: entity work.inverter_e5b38cca3b port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, clr => '0', ip(0) => from_fifo_empty_net_x0, op(0) => cmd_rdy ); mcode: entity work.mcode_block_f21d0469ad port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, clr => '0', cmd_rdy(0) => cmd_rdy, cmd_req => cmd_req_x1, out_port => out_port, port_id => port_id, rs(0) => rs, sda_i(0) => i2c_sda_i_net_x0, ws(0) => ws, cmd_ack(0) => cmd_ack_x0, cmd_get(0) => cmd_get_x0, cmd_rsp => cmd_rsp_x0, in_port => in_port, scl_o(0) => scl_o_x1, sda_o(0) => sda_o_x1 ); picoblaze_microcontroller: entity work.xlpb3 port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, in_port => in_port, instruction => picoblaze_rom_data_net, interrupt(0) => constant1_op_net, reset(0) => constant10_op_net, address => picoblaze_microcontroller_address_net, out_port => out_port, port_id => port_id, read_strobe(0) => rs, write_strobe(0) => ws ); picoblaze_rom: entity work.xlsprom generic map ( c_address_width => 10, c_width => 18, core_name0 => "bmg_41_99d18de731b34188", latency => 1 ) port map ( addr => picoblaze_microcontroller_address_net, ce => ce_1_sg_x0, clk => clk_1_sg_x0, en => "1", rst => "0", data => picoblaze_rom_data_net ); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; -- Generated from Simulink block "sg_i2c_controller_s6" entity sg_i2c_controller_s6 is port ( ce_1: in std_logic; clk_1: in std_logic; data_out: in std_logic_vector(7 downto 0); data_out_x0: in std_logic_vector(31 downto 0); data_out_x1: in std_logic_vector(31 downto 0); dout: in std_logic_vector(7 downto 0); empty: in std_logic; empty_x0: in std_logic; full: in std_logic; i2c_sda_i: in std_logic; percent_full: in std_logic; percent_full_x0: in std_logic; plb_abus: in std_logic_vector(31 downto 0); plb_ce_1: in std_logic; plb_clk_1: in std_logic; plb_pavalid: in std_logic; plb_rnw: in std_logic; plb_wrdbus: in std_logic_vector(31 downto 0); sg_plb_addrpref: in std_logic_vector(19 downto 0); splb_rst: in std_logic; data_in: out std_logic_vector(7 downto 0); data_in_x0: out std_logic_vector(31 downto 0); data_in_x1: out std_logic_vector(31 downto 0); en: out std_logic; gpio_out8_o: out std_logic_vector(7 downto 0); i2c_scl: out std_logic; i2c_sda_o: out std_logic; i2c_sda_t: out std_logic; re: out std_logic; re_x0: out std_logic; sl_addrack: out std_logic; sl_rdcomp: out std_logic; sl_rddack: out std_logic; sl_rddbus: out std_logic_vector(31 downto 0); sl_wait: out std_logic; sl_wrcomp: out std_logic; sl_wrdack: out std_logic; we: out std_logic; we_x0: out std_logic ); end sg_i2c_controller_s6; architecture structural of sg_i2c_controller_s6 is attribute core_generation_info: string; attribute core_generation_info of structural : architecture is "sg_i2c_controller_s6,sysgen_core,{clock_period=10.00000000,clocking=Clock_Enables,compilation=Export_as_a_pcore_to_EDK,sample_periods=1.00000000000 1.00000000000,testbench=0,total_blocks=73,xilinx_constant_block_block=4,xilinx_edk_processor_block=1,xilinx_gateway_in_block=7,xilinx_gateway_out_block=11,xilinx_inverter_block=1,xilinx_mcode_block_block=3,xilinx_picoblaze_microcontroller_block=1,xilinx_shared_memory_based_from_fifo_block=2,xilinx_shared_memory_based_from_register_block=1,xilinx_shared_memory_based_to_fifo_block=2,xilinx_shared_memory_based_to_register_block=1,xilinx_single_port_read_only_memory_block=1,xilinx_system_generator_block=1,}"; signal ce_1_sg_x1: std_logic; signal clk_1_sg_x1: std_logic; signal data_in_net: std_logic_vector(7 downto 0); signal data_in_x0_net: std_logic_vector(31 downto 0); signal data_in_x1_net: std_logic_vector(31 downto 0); signal data_out_x0_net: std_logic_vector(31 downto 0); signal data_out_x1_net: std_logic_vector(31 downto 0); signal dout_net: std_logic_vector(7 downto 0); signal empty_net: std_logic; signal empty_x0_net: std_logic; signal en_net: std_logic; signal from_register_data_out_net: std_logic_vector(7 downto 0); signal full_net: std_logic; signal i2c_scl_net: std_logic; signal i2c_sda_i_net: std_logic; signal i2c_sda_o_net: std_logic; signal i2c_sda_t_net: std_logic; signal percent_full_net: std_logic; signal percent_full_x0_net: std_logic; signal plb_abus_net: std_logic_vector(31 downto 0); signal plb_ce_1_sg_x1: std_logic; signal plb_clk_1_sg_x1: std_logic; signal plb_pavalid_net: std_logic; signal plb_rnw_net: std_logic; signal plb_wrdbus_net: std_logic_vector(31 downto 0); signal re_net: std_logic; signal re_x0_net: std_logic; signal sg_plb_addrpref_net: std_logic_vector(19 downto 0); signal sl_addrack_net: std_logic; signal sl_rdcomp_net: std_logic; signal sl_rddack_net: std_logic; signal sl_rddbus_net: std_logic_vector(31 downto 0); signal sl_wait_net: std_logic; signal sl_wrdack_x1: std_logic; signal splb_rst_net: std_logic; signal we_net: std_logic; signal we_x0_net: std_logic; begin ce_1_sg_x1 <= ce_1; clk_1_sg_x1 <= clk_1; from_register_data_out_net <= data_out; data_out_x0_net <= data_out_x0; data_out_x1_net <= data_out_x1; dout_net <= dout; empty_net <= empty; empty_x0_net <= empty_x0; full_net <= full; i2c_sda_i_net <= i2c_sda_i; percent_full_net <= percent_full; percent_full_x0_net <= percent_full_x0; plb_abus_net <= plb_abus; plb_ce_1_sg_x1 <= plb_ce_1; plb_clk_1_sg_x1 <= plb_clk_1; plb_pavalid_net <= plb_pavalid; plb_rnw_net <= plb_rnw; plb_wrdbus_net <= plb_wrdbus; sg_plb_addrpref_net <= sg_plb_addrpref; splb_rst_net <= splb_rst; data_in <= data_in_net; data_in_x0 <= data_in_x0_net; data_in_x1 <= data_in_x1_net; en <= en_net; gpio_out8_o <= from_register_data_out_net; i2c_scl <= i2c_scl_net; i2c_sda_o <= i2c_sda_o_net; i2c_sda_t <= i2c_sda_t_net; re <= re_net; re_x0 <= re_x0_net; sl_addrack <= sl_addrack_net; sl_rdcomp <= sl_rdcomp_net; sl_rddack <= sl_rddack_net; sl_rddbus <= sl_rddbus_net; sl_wait <= sl_wait_net; sl_wrcomp <= sl_wrdack_x1; sl_wrdack <= sl_wrdack_x1; we <= we_net; we_x0 <= we_x0_net; constant1: entity work.constant_963ed6358a port map ( ce => '0', clk => '0', clr => '0', op(0) => i2c_sda_o_net ); edk_processor_f7392c68af: entity work.edk_processor_entity_f7392c68af port map ( from_fifo => data_out_x0_net, from_fifo_x0 => percent_full_net, from_fifo_x1 => empty_net, plb_abus => plb_abus_net, plb_ce_1 => plb_ce_1_sg_x1, plb_clk_1 => plb_clk_1_sg_x1, plb_pavalid => plb_pavalid_net, plb_rnw => plb_rnw_net, plb_wrdbus => plb_wrdbus_net, sg_plb_addrpref => sg_plb_addrpref_net, splb_rst => splb_rst_net, to_fifo => percent_full_x0_net, to_fifo_x0 => full_net, to_register => dout_net, constant5_x0 => sl_wait_net, plb_decode_x0 => sl_addrack_net, plb_decode_x1 => sl_rdcomp_net, plb_decode_x2 => sl_wrdack_x1, plb_decode_x3 => sl_rddack_net, plb_decode_x4 => sl_rddbus_net, plb_memmap_x0 => data_in_net, plb_memmap_x1 => en_net, plb_memmap_x2 => re_net, plb_memmap_x3 => data_in_x0_net, plb_memmap_x4 => we_net ); i2c_controller_e098cd9e07: entity work.i2c_controller_entity_e098cd9e07 port map ( ce_1 => ce_1_sg_x1, clk_1 => clk_1_sg_x1, cmd_req_x0 => data_out_x1_net, from_fifo => empty_x0_net, sda_i => i2c_sda_i_net, mcode_x0 => re_x0_net, mcode_x1 => data_in_x1_net, mcode_x2 => we_x0_net, scl_o_x0 => i2c_scl_net, sda_o_x0 => i2c_sda_t_net ); end structural;
gpl-3.0
29e61ffd6ba0b32e77ab36738a9dfa17
0.572956
3.322137
false
false
false
false
GSimas/EEL5105
PROJETO-EEL5105/Projeto/map4.vhd
1
953
library ieee; use ieee.std_logic_1164.all; entity map4 is port ( F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13, F14, F15: out std_logic_vector(31 downto 0) ); end map4; architecture map4_struct of map4 is begin F0 <= "00100000001000100000110000010000"; F1 <= "00000000000000011000110000010000"; F2 <= "00010000110000111100000000000000"; F3 <= "00000000000000000000001100000000"; F4 <= "00010001100100001000001100000000"; F5 <= "00000000000000000000001100001000"; F6 <= "00010000010000010000000000000000"; F7 <= "00000000000000000000000000000010"; F8 <= "00000010000010000000110000000000"; F9 <= "00000000000001000000110001000100"; F10 <= "00001100000100110000000000100000"; F11 <= "00000000001000001000000000000000"; F12 <= "00000000011000000100000100000010"; F13 <= "00000010000000000000100000000100"; F14 <= "00000000010000100000000010000000"; F15 <= "00010100000010000100010000011000"; end map4_struct;
mit
26ab2c9c1ac4032b803f8120f395399c
0.75341
3.332168
false
false
false
false
GSimas/EEL5105
Eletr-Digital/Projeto Final/PROJETO COFRE FUNCIONANDO/clockbuzzer.vhd
1
4,595
-- megafunction wizard: %LPM_COUNTER% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: lpm_counter -- ============================================================ -- File Name: clockbuzzer.vhd -- Megafunction Name(s): -- lpm_counter -- -- Simulation Library Files(s): -- lpm -- ============================================================ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- -- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition -- ************************************************************ --Copyright (C) 1991-2010 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject --to the terms and conditions of the Altera Program License --Subscription Agreement, Altera MegaCore Function License --Agreement, or other applicable license agreement, including, --without limitation, that your use is for the sole purpose of --programming logic devices manufactured by Altera and sold by --Altera or its authorized distributors. Please refer to the --applicable agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY lpm; USE lpm.all; ENTITY clockbuzzer IS PORT ( clock : IN STD_LOGIC ; cout : OUT STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (29 DOWNTO 0) ); END clockbuzzer; ARCHITECTURE SYN OF clockbuzzer IS SIGNAL sub_wire0 : STD_LOGIC ; SIGNAL sub_wire1 : STD_LOGIC_VECTOR (29 DOWNTO 0); COMPONENT lpm_counter GENERIC ( lpm_direction : STRING; lpm_modulus : NATURAL; lpm_port_updown : STRING; lpm_type : STRING; lpm_width : NATURAL ); PORT ( clock : IN STD_LOGIC ; cout : OUT STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (29 DOWNTO 0) ); END COMPONENT; BEGIN cout <= sub_wire0; q <= sub_wire1(29 DOWNTO 0); lpm_counter_component : lpm_counter GENERIC MAP ( lpm_direction => "UP", lpm_modulus => 25000, lpm_port_updown => "PORT_UNUSED", lpm_type => "LPM_COUNTER", lpm_width => 30 ) PORT MAP ( clock => clock, cout => sub_wire0, q => sub_wire1 ); END SYN; -- ============================================================ -- CNX file retrieval info -- ============================================================ -- Retrieval info: PRIVATE: ACLR NUMERIC "0" -- Retrieval info: PRIVATE: ALOAD NUMERIC "0" -- Retrieval info: PRIVATE: ASET NUMERIC "0" -- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1" -- Retrieval info: PRIVATE: CLK_EN NUMERIC "0" -- Retrieval info: PRIVATE: CNT_EN NUMERIC "0" -- Retrieval info: PRIVATE: CarryIn NUMERIC "0" -- Retrieval info: PRIVATE: CarryOut NUMERIC "1" -- Retrieval info: PRIVATE: Direction NUMERIC "0" -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" -- Retrieval info: PRIVATE: ModulusCounter NUMERIC "1" -- Retrieval info: PRIVATE: ModulusValue NUMERIC "25000" -- Retrieval info: PRIVATE: SCLR NUMERIC "0" -- Retrieval info: PRIVATE: SLOAD NUMERIC "0" -- Retrieval info: PRIVATE: SSET NUMERIC "0" -- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: nBit NUMERIC "30" -- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP" -- Retrieval info: CONSTANT: LPM_MODULUS NUMERIC "25000" -- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER" -- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "30" -- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock -- Retrieval info: USED_PORT: cout 0 0 0 0 OUTPUT NODEFVAL cout -- Retrieval info: USED_PORT: q 0 0 30 0 OUTPUT NODEFVAL q[29..0] -- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 -- Retrieval info: CONNECT: q 0 0 30 0 @q 0 0 30 0 -- Retrieval info: CONNECT: cout 0 0 0 0 @cout 0 0 0 0 -- Retrieval info: LIBRARY: lpm lpm.lpm_components.all -- Retrieval info: GEN_FILE: TYPE_NORMAL clockbuzzer.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL clockbuzzer.inc TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL clockbuzzer.cmp TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL clockbuzzer.bsf TRUE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL clockbuzzer_inst.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL clockbuzzer_waveforms.html TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL clockbuzzer_wave*.jpg FALSE -- Retrieval info: LIB_FILE: lpm
mit
4fbca971f4aa5aa310615e93bbff6dd9
0.658107
3.729708
false
false
false
false
GSimas/EEL5105
PROJETO-EEL5105/Projeto/rot_32.vhd
1
1,210
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; --Rotacao de deslocamento 32 bits entity rot_32 is port( SET_ROLL, EN_TIME, CLOCK_M, RST: in std_logic; SPEED: in std_logic_vector(2 downto 0); REG_IN: in std_logic_vector(31 downto 0); REG_OUT: out std_logic_vector(31 downto 0) ); end rot_32; --Definicao de arquitetura architecture bhv of rot_32 is signal shl: std_logic_vector (31 downto 0); -- Registrador de 32 bits signal shl2: std_logic_vector (31 downto 0); -- Registrador de 32 bits signal speed_sig: std_logic := SPEED(0) or SPEED(1) or SPEED(2); begin process (CLOCK_M, RST, EN_TIME, SET_ROLL) begin if RST = '0' then -- Reset assíncrono do registrador shl <= (others => '0'); shl2 <= (others => '0'); elsif SET_ROLL = '0' then shl <= REG_IN; elsif rising_edge(CLOCK_M) then -- Sinal de clock do registrador (subida) if EN_TIME = '1' and speed_sig = '1' and SET_ROLL = '1' then -- Sinal de enable do registrador shl2 <= shl; shl(31 downto 1) <= shl2(30 downto 0);-- Deslocamento para esquerda shl(0) <= shl2(31); -- rotacao de deslocamento para a esquerda end if; end if; end process; REG_OUT <= shl; end bhv;
mit
d9800399ee4b2682ffe4551bae09612f
0.659222
2.885442
false
false
false
false
bertuccio/ARQ
Practica4/p4a_tb.vhd
1
8,425
------------------------------------------------------------------------------- -- Banco de pruebas para la cache ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity p4a_tb is end p4a_tb; architecture PRACTICA of p4a_tb is component DM_CACHE generic ( W : integer; -- Ancho bus direcciones L : integer; -- Ancho bus de datos ENTRIES : integer); -- Ancho direcciones de la cache port ( CLK : in std_logic; -- Reloj REQ_C : in std_logic; -- Solicitud de direccion M_WAIT : in std_logic; -- Esperar a la memoria RESET : in std_logic; -- Reset AD : in std_logic_vector(W-1 downto 0); -- Bus direcciones D : in std_logic_vector(L-1 downto 0); -- Bus de datos WAIT_C : out std_logic; -- Esperar a la cache M_REQ : out std_logic; -- Solicitud de acceso Q : out std_logic_vector(L-1 downto 0)); -- Salida de datos end component; ------------------------------------------------------------------------------- -- Parametros para la instanciacion ------------------------------------------------------------------------------- constant L : integer := 8; constant W : integer := 5; constant ENTRIES : integer := 4; ------------------------------------------------------------------------------- -- Otras constantes ------------------------------------------------------------------------------- constant CLK_PERIOD : time := 50 ns; constant tdelay : time := 10 ns; constant TAM_CACHE : integer:=(2**ENTRIES-1); -- Tiempo que la memoria tarda en devolver el dato solicitado -- En ciclos de reloj constant RETRASO : integer := 3; signal clk,req_c,M_wait,reset : std_logic; signal wait_c, m_req : std_logic; signal ad : std_logic_vector(W-1 downto 0):=(others =>'0'); signal d : std_logic_vector(L-1 downto 0); signal q : std_logic_vector(L-1 downto 0); signal contador_ciclos : integer := 0; signal inicializar : boolean := FALSE; signal end_sim : boolean := FALSE; begin -- PRACTICA ----------------------------------------------------------------------------- -- Instanciar la cache ----------------------------------------------------------------------------- UUT : DM_CACHE generic map ( W => W, L => L, ENTRIES => ENTRIES) port map ( CLK => clk, REQ_C => req_c, M_WAIT => m_wait, RESET => reset, AD => ad, D => d, WAIT_C => wait_c, M_REQ => m_req, Q => q); ----------------------------------------------------------------------------- -- Proceso de reloj ----------------------------------------------------------------------------- process begin while not end_sim loop clk <= '1'; wait for CLK_PERIOD/2; clk <= '0'; wait for CLK_PERIOD/2; end loop; wait; end process; ----------------------------------------------------------------------------- -- Proceso que simula la memoria principal -- El dato que hay almacenado en cada dirección es igual a la -- propia dirección. Así: -- * Direccion 0: Dato 0 -- * Direccion 1: Dato 1 -- etc ----------------------------------------------------------------------------- process(clk) variable dir : integer; variable counter : integer := 2; variable t_espera : integer := RETRASO; -- Tiempo de espera de la memoria begin -- Esta memoria funciona en flanco de bajada if falling_edge(clk) then -- Si dato solicitado if m_req='1' then -- y si ha transcurrido el tiempo de espera if t_espera=0 then m_wait<='0'; -- Leer la direccion dir:=to_integer(unsigned(AD)); -- Se devuelve como dato la propia direccion D<=std_logic_vector(to_unsigned(dir,L)); -- Para depuracion --report "Acceso a memoria principal"; -- Reiniciar el tiempo de esperera para la proxima -- lectura t_espera:=RETRASO; else -- Todavia no ha transcurrido el tiempo de espera -- No devolver dato -- Queda un ciclo menos t_espera:=t_espera-1; m_wait<='1'; end if; end if; end if; end process; ----------------------------------------------------------------------------- -- Proceso para contar ciclos ----------------------------------------------------------------------------- process(clk,inicializar) begin if inicializar=TRUE then contador_ciclos<=0; elsif rising_edge(clk) then -- Un ciclo mas contador_ciclos<=contador_ciclos + 1; end if; end process; ----------------------------------------------------------------------------- -- Proceso que simula el micro ----------------------------------------------------------------------------- process variable dato : integer; variable ciclos : integer := 0; -- Contador de ciclos begin RESET <= '1'; inicializar<=TRUE; -- Inicializar contador de ciclos wait for tdelay; --------------------------------------------------------------------------- -- Recorrer la memoria. Como es el primer acceso, la cache debe -- activar la senal de Wait_C, porque los datos no estan -- todavia cacheados y se debe acceder a la memoria principal --------------------------------------------------------------------------- RESET <= '0'; inicializar<=FALSE; for i in 0 to TAM_CACHE loop REQ_C <= '1'; AD <= std_logic_vector(to_unsigned(i,w)); wait until rising_edge(clk); wait for tdelay; assert wait_c='1' report "Error. deberia activarse wait_c" severity FAILURE; -- Esperear a que termine acceso a memoria wait until WAIT_C = '0'; -- Para depuracion: sacar el valor leido de la memoria -- Debe ser igual a la direccion accedida --report "Dato: " & integer'image(to_integer(unsigned(Q))); req_c <= '0'; wait until rising_edge(clk); wait for tdelay; end loop; -- Informar del numero de ciclos transcurridos la primera vez report "Ciclos la primera vez: " & integer'image(contador_ciclos); inicializar<=TRUE; -- Poner a cero contador ciclos wait for tdelay; inicializar<=FALSE; --------------------------------------------------------------------------- -- Volver a recorrer la memoria. Ahora los datos deben estar cacheados -- y por tanto no debe haber acceso a la memoria principal. La -- senal wait_c debe permanecer a '0' --------------------------------------------------------------------------- for i in 0 to TAM_CACHE loop REQ_C <= '1'; AD <= std_logic_vector(to_unsigned(i,w)); wait until rising_edge(clk); wait for tdelay; assert wait_c='0' report "Error. wait_c deberia estar a 0" severity FAILURE; -- Comprobar ademas que el dato leido es el correcto -- Debe ser igual a la direccion a la que se accede assert Q=std_logic_vector(to_unsigned(i,L)) report "Error en lectura de cache. Dato leido erroneo" severity FAILURE; -- Para depuracion: Imprimir el dato leido --dato:=to_integer(unsigned(Q)); --report "Dato: " & integer'image(dato); end loop; -- Informar del numero de ciclos transcurridos la segunda vez -- Como los datos estaban "cacheados" debe tardar menos report "Ciclos la segunda vez: " & integer'image(contador_ciclos); --------------------------------------------------------------------------- -- Fin de la simulacion --------------------------------------------------------------------------- report "Fin de la simulacion"; end_sim<=TRUE; wait; end process; end PRACTICA;
mit
8c31f720b78f7d9e853201d35d914b22
0.443323
4.629121
false
false
false
false
GSimas/EEL5105
Eletr-Digital/Projeto Final/PROJETO COFRE FUNCIONANDO/BuzzerFa.vhd
1
4,562
-- megafunction wizard: %LPM_COUNTER% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: lpm_counter -- ============================================================ -- File Name: BuzzerFa.vhd -- Megafunction Name(s): -- lpm_counter -- -- Simulation Library Files(s): -- lpm -- ============================================================ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- -- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition -- ************************************************************ --Copyright (C) 1991-2010 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject --to the terms and conditions of the Altera Program License --Subscription Agreement, Altera MegaCore Function License --Agreement, or other applicable license agreement, including, --without limitation, that your use is for the sole purpose of --programming logic devices manufactured by Altera and sold by --Altera or its authorized distributors. Please refer to the --applicable agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY lpm; USE lpm.all; ENTITY BuzzerFa IS PORT ( clock : IN STD_LOGIC ; cout : OUT STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (29 DOWNTO 0) ); END BuzzerFa; ARCHITECTURE SYN OF buzzerfa IS SIGNAL sub_wire0 : STD_LOGIC ; SIGNAL sub_wire1 : STD_LOGIC_VECTOR (29 DOWNTO 0); COMPONENT lpm_counter GENERIC ( lpm_direction : STRING; lpm_modulus : NATURAL; lpm_port_updown : STRING; lpm_type : STRING; lpm_width : NATURAL ); PORT ( clock : IN STD_LOGIC ; cout : OUT STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (29 DOWNTO 0) ); END COMPONENT; BEGIN cout <= sub_wire0; q <= sub_wire1(29 DOWNTO 0); lpm_counter_component : lpm_counter GENERIC MAP ( lpm_direction => "UP", lpm_modulus => 71023, lpm_port_updown => "PORT_UNUSED", lpm_type => "LPM_COUNTER", lpm_width => 30 ) PORT MAP ( clock => clock, cout => sub_wire0, q => sub_wire1 ); END SYN; -- ============================================================ -- CNX file retrieval info -- ============================================================ -- Retrieval info: PRIVATE: ACLR NUMERIC "0" -- Retrieval info: PRIVATE: ALOAD NUMERIC "0" -- Retrieval info: PRIVATE: ASET NUMERIC "0" -- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1" -- Retrieval info: PRIVATE: CLK_EN NUMERIC "0" -- Retrieval info: PRIVATE: CNT_EN NUMERIC "0" -- Retrieval info: PRIVATE: CarryIn NUMERIC "0" -- Retrieval info: PRIVATE: CarryOut NUMERIC "1" -- Retrieval info: PRIVATE: Direction NUMERIC "0" -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" -- Retrieval info: PRIVATE: ModulusCounter NUMERIC "1" -- Retrieval info: PRIVATE: ModulusValue NUMERIC "71023" -- Retrieval info: PRIVATE: SCLR NUMERIC "0" -- Retrieval info: PRIVATE: SLOAD NUMERIC "0" -- Retrieval info: PRIVATE: SSET NUMERIC "0" -- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: nBit NUMERIC "30" -- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP" -- Retrieval info: CONSTANT: LPM_MODULUS NUMERIC "71023" -- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER" -- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "30" -- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock -- Retrieval info: USED_PORT: cout 0 0 0 0 OUTPUT NODEFVAL cout -- Retrieval info: USED_PORT: q 0 0 30 0 OUTPUT NODEFVAL q[29..0] -- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 -- Retrieval info: CONNECT: q 0 0 30 0 @q 0 0 30 0 -- Retrieval info: CONNECT: cout 0 0 0 0 @cout 0 0 0 0 -- Retrieval info: LIBRARY: lpm lpm.lpm_components.all -- Retrieval info: GEN_FILE: TYPE_NORMAL BuzzerFa.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL BuzzerFa.inc TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL BuzzerFa.cmp TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL BuzzerFa.bsf TRUE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL BuzzerFa_inst.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL BuzzerFa_waveforms.html TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL BuzzerFa_wave*.jpg FALSE -- Retrieval info: LIB_FILE: lpm
mit
a44f274b5f281fe99c3e035ef8b16402
0.655633
3.664257
false
false
false
false
hoglet67/AtomFpga
src/common/AVR8/uC/ExtIRQ_Controller.vhd
4
6,619
--********************************************************************************************** -- External Interrupt Controller Block Peripheral for the AVR Core -- Version 1.00 -- Created 01.26.2013 -- Designed by Rob Brown --********************************************************************************************** library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use WORK.AVRuCPackage.all; entity ExtIRQ_Controller is Port( -- begin Signals required by AVR8 for this core, do not modify. nReset : in STD_LOGIC; clk : in STD_LOGIC; adr : in STD_LOGIC_VECTOR (15 downto 0); dbus_in : in STD_LOGIC_VECTOR (7 downto 0); dbus_out : out STD_LOGIC_VECTOR (7 downto 0); iore : in STD_LOGIC; iowe : in STD_LOGIC; out_en : out STD_LOGIC; -- end Signals required by AVR8 for this core, do not modify. clken : in STD_LOGIC; irq_clken : in STD_LOGIC; extpins : in STD_LOGIC_VECTOR(7 downto 0); INTx : out STD_LOGIC_VECTOR(7 downto 0) ); end ExtIRQ_Controller; ----------------------------------------------------------------------- architecture Behavioral of ExtIRQ_Controller is -- Registers signal EIMSK : std_logic_vector(7 downto 0); signal EIFR : std_logic_vector(7 downto 0); signal EICR : std_logic_vector(7 downto 0); -- EIMSK Bits alias INT0 : std_logic is EIMSK(0); alias INT1 : std_logic is EIMSK(1); alias INT2 : std_logic is EIMSK(2); alias INT3 : std_logic is EIMSK(3); alias INT4 : std_logic is EIMSK(4); alias INT5 : std_logic is EIMSK(5); alias INT6 : std_logic is EIMSK(6); alias INT7 : std_logic is EIMSK(7); -- EIFR Bits alias INTF0 : std_logic is EIFR(0); alias INTF1 : std_logic is EIFR(1); alias INTF2 : std_logic is EIFR(2); alias INTF3 : std_logic is EIFR(3); alias INTF4 : std_logic is EIFR(4); alias INTF5 : std_logic is EIFR(5); alias INTF6 : std_logic is EIFR(6); alias INTF7 : std_logic is EIFR(7); -- EICR Bits alias ISC40 : std_logic is EICR(0); alias ISC41 : std_logic is EICR(1); alias ISC50 : std_logic is EICR(2); alias ISC51 : std_logic is EICR(3); alias ISC60 : std_logic is EICR(4); alias ISC61 : std_logic is EICR(5); alias ISC70 : std_logic is EICR(6); alias ISC71 : std_logic is EICR(7); -- Risign/falling edge detectors signal INTxRE : std_logic_vector (7 downto 0); -- Rising edge of external input INTx signal INTxFE : std_logic_vector (7 downto 0); -- Falling edge of external input INT0 signal INTxLatched : std_logic_vector (7 downto 0); -- Synchronizer signals signal INTxSA : std_logic_vector (7 downto 0); signal INTxSB : std_logic_vector (7 downto 0); -- Output of the synchronizer for INTx signal TRGR : std_logic_vector(7 downto 0); --constant EIMSK_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#39#); --constant EIFR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#38#); --constant EICR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#3A#); begin -- Synchronizers SyncDFFs:process(clk,nReset) begin if (nReset='0') then -- Reset INTxSA <= (others => '0'); INTxSB <= (others => '0'); elsif (clk='1' and clk'event) then -- Clock if (irq_clken='1') then -- Clock Enable(Note 2) INTxSA <= extpins; INTxSB <= INTxSA; end if; end if; end process; -- Edge Detector edge_detect:for i in INTxSB'range generate INTxRE(i) <= (not INTxSB(i) and extpins(i)); INTxFE(i) <= (INTxSB(i) and not extpins(i)); INTxLatched(i) <= INTxSB(i); end generate; -- Interrupt Process INT_Proc:process(clk,nReset) begin if (nReset='0') then INTx(3 downto 0) <= (others => '0'); elsif (clk='1' and clk'event) then if (clken='1') then -- Clock Enable -- interrupts 0 through 3 do not set their corresponding EIFR flag! See Atmega103 Data Sheet top of page 31. -- these four interrupts also do not use EICR bits. They are always level triggered, active low. TRGR(0) <= (INT0 and not INTxLatched(0)); TRGR(1) <= (INT1 and not INTxLatched(1)); TRGR(2) <= (INT2 and not INTxLatched(2)); TRGR(3) <= (INT3 and not INTxLatched(3)); -- interrupts 4 through 7's triggers are sensitive to EICR bits -- 00 low level trigger, 10 falling edge trigger, 11 rising edge trigger, 01 is reserved. -- See Atmega103 Data Sheet page 30 and 31. TRGR(4) <= (INT4 and ((not ISC41 and not ISC40 and not INTxLatched(4)) or (ISC41 and not ISC40 and INTxFE(4)) or (ISC41 and ISC40 and INTxRE(4)))); TRGR(5) <= (INT5 and ((not ISC51 and not ISC50 and not INTxLatched(5)) or (ISC51 and not ISC50 and INTxFE(5)) or (ISC51 and ISC50 and INTxRE(5)))); TRGR(6) <= (INT6 and ((not ISC61 and not ISC60 and not INTxLatched(6)) or (ISC61 and not ISC60 and INTxFE(6)) or (ISC61 and ISC60 and INTxRE(6)))); TRGR(7) <= (INT7 and ((not ISC71 and not ISC70 and not INTxLatched(7)) or (ISC71 and not ISC70 and INTxFE(7)) or (ISC71 and ISC70 and INTxRE(7)))); INTx <= TRGR; end if; end if; end process; -- Write EIMSK bits EIMSK_Bits:process(clk,nReset) begin if (nReset='0') then EIMSK <= (others => '0'); elsif (clk='1' and clk'event) then if (clken='1') then -- Clock Enable if (adr=EIMSK_Address and iowe='1') then EIMSK <= dbus_in; end if; end if; end if; end process; -- Write EIFR bits EIFR_Bits:process(clk,nReset) begin if (nReset='0') then EIFR <= (others => '0'); elsif (clk='1' and clk'event) then if (clken='1') then -- Clock Enable if (adr=EIFR_Address and iowe='1') then EIFR(7 downto 4) <= EIFR(7 downto 4) and not dbus_in(7 downto 4); EIFR(3 downto 0) <= "0000"; -- in Atmega103, these bits are reserved and always read '0', See Atmega103 Data Sheet top of page 31. else EIFR(7 downto 4) <= EIFR(7 downto 4) or TRGR(7 downto 4); EIFR(3 downto 0) <= "0000"; -- in Atmega103, these bits are reserved and always read '0', See Atmega103 Data Sheet top of page 31. end if; end if; end if; end process; -- Write EICR bits EICR_Bits:process(clk,nReset) begin if (nReset='0') then EICR <= (others => '0'); elsif (clk='1' and clk'event) then if (clken='1') then -- Clock Enable if (adr=EICR_Address and iowe='1') then EICR <= dbus_in; end if; end if; end if; end process; -- Output Enable out_en <= '1' when ((adr=EIMSK_Address or adr=EIFR_Address or adr=EICR_Address) and iore='1') else '0'; -- Read register dbus_out <= EIMSK when (adr=EIMSK_Address) else EIFR when (adr=EIFR_Address) else EICR when (adr=EICR_Address) else "ZZZZZZZZ"; end Behavioral;
apache-2.0
503b8cde57b3fdcdcedcfa483528c853
0.632422
2.928761
false
false
false
false
hoglet67/AtomFpga
src/common/CpuWrapper.vhd
1
2,811
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; entity CpuWrapper is generic ( CImplDebugger : boolean := false; CImplCpu65c02 : boolean := false ); port ( clk_main : in std_logic; clk_avr : in std_logic; cpu_clken : in std_logic; IRQ_n : in std_logic; NMI_n : in std_logic; RST_n : in std_logic; PRST_n : in std_logic; SO : in std_logic; RDY : in std_logic; Din : in std_logic_vector(7 downto 0); Dout : out std_logic_vector(7 downto 0); R_W_n : out std_logic; Sync : out std_logic; Addr : out std_logic_vector(15 downto 0); avr_RxD : in std_logic; avr_TxD : out std_logic ); end CpuWrapper; architecture BEHAVIORAL of CpuWrapper is signal Addr_us : unsigned(15 downto 0); signal Dout_us : unsigned(7 downto 0); signal Din_us : unsigned(7 downto 0); begin --------------------------------------------------------------------- -- 6502 CPU (using T65 core) --------------------------------------------------------------------- nmos: if not CImplCpu65c02 generate cpu : entity work.T65 port map ( Mode => "00", Abort_n => '1', SO_n => SO, Res_n => RST_n, Enable => cpu_clken, Clk => clk_main, Rdy => RDY, IRQ_n => IRQ_n, NMI_n => NMI_n, R_W_n => R_W_n, Sync => Sync, A(23 downto 16) => open, A(15 downto 0) => Addr(15 downto 0), DI(7 downto 0) => Din(7 downto 0), DO(7 downto 0) => Dout(7 downto 0) ); avr_TxD <= '1'; end generate; --------------------------------------------------------------------- -- 65C02 CPU (using AlanD core) --------------------------------------------------------------------- -- TODO: Need to add RDY cmos: if CImplCpu65c02 generate inst_r65c02: entity work.r65c02 port map ( reset => RST_n, clk => clk_main, enable => cpu_clken, nmi_n => NMI_n, irq_n => IRQ_n, di => Din_us, do => Dout_us, addr => Addr_us, nwe => R_W_n, sync => Sync ); Din_us <= unsigned(Din); Dout <= std_logic_vector(Dout_us); Addr <= std_logic_vector(Addr_us); avr_TxD <= '1'; end generate; end BEHAVIORAL;
apache-2.0
18cb300dbecd83ac07b6c18ca30d0251
0.396656
3.898752
false
false
false
false
hoglet67/AtomFpga
src/common/AVR8/Peripheral/swap_pins.vhd
4
4,402
--********************************************************************************************** -- Quick and Dirty peripheral to connect pins for PWM etc to external pins -- Version 1.5 "Original" (Mega103) version -- Modified 14.06.20010 -- MOdified by Jack Gassett --********************************************************************************************** library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use WORK.AVRuCPackage.all; entity swap_pins is port( -- AVR Control ireset : in std_logic; cp2 : in std_logic; adr : in std_logic_vector(15 downto 0); dbus_in : in std_logic_vector(7 downto 0); iore : in std_logic; iowe : in std_logic; -- External connection OC0_PWM0_Loc : out integer; OC1A_PWM1A_Loc : out integer; OC1B_PWM1B_Loc : out integer; OC2_PWM2_Loc : out integer; mosi_Loc : out integer; miso_Loc : out integer; sck_Loc : out integer; spi_cs_n_Loc : out integer ); end swap_pins; architecture RTL of swap_pins is --PWM signals signal OC0_PWM0_Int : std_logic_vector(7 downto 0); signal OC0_PWM0_En : std_logic; signal OC1A_PWM1A_Int : std_logic_vector(7 downto 0); signal OC1A_PWM1A_En : std_logic; signal OC1B_PWM1B_Int : std_logic_vector(7 downto 0); signal OC1B_PWM1B_En : std_logic; signal OC2_PWM2_Int : std_logic_vector(7 downto 0); signal OC2_PWM2_En : std_logic; signal mosi_Int : std_logic_vector(7 downto 0); signal mosi_En : std_logic; signal miso_Int : std_logic_vector(7 downto 0); signal miso_En : std_logic; signal sck_Int : std_logic_vector(7 downto 0); signal sck_En : std_logic; signal spi_cs_n_Int : std_logic_vector(7 downto 0); signal spi_cs_n_En : std_logic; begin OC0_PWM0_En <= '1' when (adr=x"1000" and iowe='1') else '0'; -- Hijacks unused external SRAM space OC1A_PWM1A_En <= '1' when (adr=x"1001" and iowe='1') else '0'; -- Hijacks unused external SRAM space OC1B_PWM1B_En <= '1' when (adr=x"1002" and iowe='1') else '0'; -- Hijacks unused external SRAM space OC2_PWM2_En <= '1' when (adr=x"1003" and iowe='1') else '0'; -- Hijacks unused external SRAM space mosi_En <= '1' when (adr=x"1004" and iowe='1') else '0'; -- Hijacks unused external SRAM space miso_En <= '1' when (adr=x"1005" and iowe='1') else '0'; -- Hijacks unused external SRAM space sck_En <= '1' when (adr=x"1006" and iowe='1') else '0'; -- Hijacks unused external SRAM space spi_cs_n_En <= '1' when (adr=x"1007" and iowe='1') else '0'; -- Hijacks unused external SRAM space process(cp2,ireset) begin if (ireset='0') then -- Reset OC0_PWM0_Int <= (others => '0'); OC1A_PWM1A_Int <= (others => '0'); OC1B_PWM1B_Int <= (others => '0'); OC2_PWM2_Int <= (others => '0'); mosi_Int <= (others => '0'); miso_Int <= (others => '0'); sck_Int <= (others => '0'); spi_cs_n_Int <= (others => '0'); elsif (cp2='1' and cp2'event) then -- Clock if OC0_PWM0_En='1' and iowe='1' then -- Clock enable OC0_PWM0_Int <= dbus_in; elsif OC1A_PWM1A_En='1' and iowe='1' then -- Clock enable OC1A_PWM1A_Int <= dbus_in; elsif OC1B_PWM1B_En='1' and iowe='1' then -- Clock enable OC1B_PWM1B_Int <= dbus_in; elsif OC2_PWM2_En='1' and iowe='1' then -- Clock enable OC2_PWM2_Int <= dbus_in; elsif mosi_En='1' and iowe='1' then -- Clock enable mosi_Int <= dbus_in; elsif miso_En='1' and iowe='1' then -- Clock enable miso_Int <= dbus_in; elsif sck_En='1' and iowe='1' then -- Clock enable sck_Int <= dbus_in; elsif spi_cs_n_En='1' and iowe='1' then -- Clock enable spi_cs_n_Int <= dbus_in; end if; end if; end process; OC0_PWM0_Loc <= conv_integer(OC0_PWM0_Int); OC1A_PWM1A_Loc <= conv_integer(OC1A_PWM1A_Int); OC1B_PWM1B_Loc <= conv_integer(OC1B_PWM1B_Int); OC2_PWM2_Loc <= conv_integer(OC2_PWM2_Int); mosi_Loc <= conv_integer(mosi_Int); miso_Loc <= conv_integer(miso_Int); sck_Loc <= conv_integer(sck_Int); spi_cs_n_Loc <= conv_integer(spi_cs_n_Int); end RTL;
apache-2.0
50ec453ac506086593265f865cd5a41e
0.553612
2.932712
false
false
false
false
GSimas/EEL5105
PROJETO-EEL5105/Projeto/Conta_bonus.vhd
1
607
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; -- Contador descendente bonus entity Conta_bonus is port( EN_TIME, REG_ROM, CLK, RST: in std_logic; CNT_OUT: out std_logic_vector(4 downto 0) ); end Conta_bonus; -- Definicao de arquitetura architecture bhv of Conta_bonus is signal contador: std_logic_vector(4 downto 0); begin process(CLK, RST, REG_ROM, EN_TIME) begin if RST = '0' then contador <= "00011"; elsif rising_edge(CLK) and EN_TIME = '1' and REG_ROM = '1' then contador <= contador - '1'; end if; end process; CNT_OUT <= contador; end bhv;
mit
603d36678ad41834c90a4cd6d48cdc50
0.685338
2.734234
false
false
false
false