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hoglet67/AtomFpga
src/common/MC6522/m6522.vhd
1
36,543
-- -- A simulation model of VIC20 hardware - VIA implementation -- Copyright (c) MikeJ - March 2003 -- -- All rights reserved -- -- Redistribution and use in source and synthezised forms, with or without -- modification, are permitted provided that the following conditions are met: -- -- Redistributions of source code must retain the above copyright notice, -- this list of conditions and the following disclaimer. -- -- Redistributions in synthesized form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- Neither the name of the author nor the names of other contributors may -- be used to endorse or promote products derived from this software without -- specific prior written permission. -- -- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- -- You are responsible for any legal issues arising from your use of this code. -- -- The latest version of this file can be found at: www.fpgaarcade.com -- -- Email [email protected] -- -- -- Revision list -- -- version 005 Many fixes to all areas, VIA now passes all VICE tests -- version 004 fixes to PB7 T1 control and Mode 0 Shift Register operation -- version 003 fix reset of T1/T2 IFR flags if T1/T2 is reload via reg5/reg9 from wolfgang (WoS) -- Ported to numeric_std and simulation fix for signal initializations from arnim laeuger -- version 002 fix from Mark McDougall, untested -- version 001 initial release -- not very sure about the shift register, documentation is a bit light. library ieee ; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity M6522 is port ( I_RS : in std_logic_vector(3 downto 0); I_DATA : in std_logic_vector(7 downto 0); O_DATA : out std_logic_vector(7 downto 0); O_DATA_OE_L : out std_logic; I_RW_L : in std_logic; I_CS1 : in std_logic; I_CS2_L : in std_logic; O_IRQ_L : out std_logic; -- note, not open drain -- port a I_CA1 : in std_logic; I_CA2 : in std_logic; O_CA2 : out std_logic; O_CA2_OE_L : out std_logic; I_PA : in std_logic_vector(7 downto 0); O_PA : out std_logic_vector(7 downto 0); O_PA_OE_L : out std_logic_vector(7 downto 0); -- port b I_CB1 : in std_logic; O_CB1 : out std_logic; O_CB1_OE_L : out std_logic; I_CB2 : in std_logic; O_CB2 : out std_logic; O_CB2_OE_L : out std_logic; I_PB : in std_logic_vector(7 downto 0); O_PB : out std_logic_vector(7 downto 0); O_PB_OE_L : out std_logic_vector(7 downto 0); I_P2_H : in std_logic; -- high for phase 2 clock ____----__ RESET_L : in std_logic; ENA_4 : in std_logic; -- clk enable CLK : in std_logic ); end; architecture RTL of M6522 is signal phase : std_logic_vector(1 downto 0):="00"; signal p2_h_t1 : std_logic; signal cs : std_logic; -- registers signal r_ddra : std_logic_vector(7 downto 0); signal r_ora : std_logic_vector(7 downto 0); signal r_ira : std_logic_vector(7 downto 0); signal r_ddrb : std_logic_vector(7 downto 0); signal r_orb : std_logic_vector(7 downto 0); signal r_irb : std_logic_vector(7 downto 0); signal r_t1l_l : std_logic_vector(7 downto 0); signal r_t1l_h : std_logic_vector(7 downto 0); signal r_t2l_l : std_logic_vector(7 downto 0); signal r_t2l_h : std_logic_vector(7 downto 0); -- not in real chip signal r_sr : std_logic_vector(7 downto 0); signal r_acr : std_logic_vector(7 downto 0); signal r_pcr : std_logic_vector(7 downto 0); signal r_ifr : std_logic_vector(7 downto 0); signal r_ier : std_logic_vector(6 downto 0); signal sr_write_ena : boolean; signal sr_read_ena : boolean; signal ifr_write_ena : boolean; signal ier_write_ena : boolean; signal clear_irq : std_logic_vector(7 downto 0); signal load_data : std_logic_vector(7 downto 0); -- timer 1 signal t1c : std_logic_vector(15 downto 0) := (others => '1'); -- simulators may not catch up w/o init here... signal t1c_active : boolean; signal t1c_done : boolean; signal t1_w_reset_int : boolean; signal t1_r_reset_int : boolean; signal t1_load_counter : boolean; signal t1_reload_counter : boolean; signal t1_int_enable : boolean := false; signal t1_toggle : std_logic; signal t1_irq : std_logic := '0'; signal t1_pb7 : std_logic := '1'; signal t1_pb7_en_c : std_logic; signal t1_pb7_en_d : std_logic; -- timer 2 signal t2c : std_logic_vector(15 downto 0) := (others => '1'); -- simulators may not catch up w/o init here... signal t2c_active : boolean; signal t2c_done : boolean; signal t2_pb6 : std_logic; signal t2_pb6_t1 : std_logic; signal t2_cnt_clk : std_logic := '1'; signal t2_w_reset_int : boolean; signal t2_r_reset_int : boolean; signal t2_load_counter : boolean; signal t2_reload_counter : boolean; signal t2_int_enable : boolean := false; signal t2_irq : std_logic := '0'; signal t2_sr_ena : boolean; -- shift reg signal sr_cnt : std_logic_vector(3 downto 0); signal sr_cb1_oe_l : std_logic; signal sr_cb1_out : std_logic; signal sr_drive_cb2 : std_logic; signal sr_strobe : std_logic; signal sr_do_shift : boolean := false; signal sr_strobe_t1 : std_logic; signal sr_strobe_falling : boolean; signal sr_strobe_rising : boolean; signal sr_irq : std_logic; signal sr_out : std_logic; signal sr_active : boolean; -- io signal w_orb_hs : std_logic; signal w_ora_hs : std_logic; signal r_irb_hs : std_logic; signal r_ira_hs : std_logic; signal ca_hs_sr : std_logic; signal ca_hs_pulse : std_logic; signal cb_hs_sr : std_logic; signal cb_hs_pulse : std_logic; signal cb1_in_mux : std_logic; signal ca1_ip_reg_c : std_logic; signal ca1_ip_reg_d : std_logic; signal cb1_ip_reg_c : std_logic; signal cb1_ip_reg_d : std_logic; signal ca1_int : boolean; signal cb1_int : boolean; signal ca1_irq : std_logic; signal cb1_irq : std_logic; signal ca2_ip_reg_c : std_logic; signal ca2_ip_reg_d : std_logic; signal cb2_ip_reg_c : std_logic; signal cb2_ip_reg_d : std_logic; signal ca2_int : boolean; signal cb2_int : boolean; signal ca2_irq : std_logic; signal cb2_irq : std_logic; signal final_irq : std_logic; begin p_phase : process begin -- internal clock phase wait until rising_edge(CLK); if (ENA_4 = '1') then p2_h_t1 <= I_P2_H; if (p2_h_t1 = '0') and (I_P2_H = '1') then phase <= "11"; else phase <= std_logic_vector(unsigned(phase) + 1); end if; end if; end process; p_cs : process(I_CS1, I_CS2_L, I_P2_H) begin cs <= '0'; if (I_CS1 = '1') and (I_CS2_L = '0') and (I_P2_H = '1') then cs <= '1'; end if; end process; -- peripheral control reg (pcr) -- 0 ca1 interrupt control (0 +ve edge, 1 -ve edge) -- 3..1 ca2 operation -- 000 input -ve edge -- 001 independend interrupt input -ve edge -- 010 input +ve edge -- 011 independend interrupt input +ve edge -- 100 handshake output -- 101 pulse output -- 110 low output -- 111 high output -- 7..4 as 3..0 for cb1,cb2 -- auxiliary control reg (acr) -- 0 input latch PA (0 disable, 1 enable) -- 1 input latch PB (0 disable, 1 enable) -- 4..2 shift reg control -- 000 disable -- 001 shift in using t2 -- 010 shift in using o2 -- 011 shift in using ext clk -- 100 shift out free running t2 rate -- 101 shift out using t2 -- 101 shift out using o2 -- 101 shift out using ext clk -- 5 t2 timer control (0 timed interrupt, 1 count down with pulses on pb6) -- 7..6 t1 timer control -- 00 timed interrupt each time t1 is loaded pb7 disable -- 01 continuous interrupts pb7 disable -- 00 timed interrupt each time t1 is loaded pb7 one shot output -- 01 continuous interrupts pb7 square wave output -- p_write_reg_reset : process(RESET_L, CLK) begin if (RESET_L = '0') then r_ora <= x"00"; r_orb <= x"00"; r_ddra <= x"00"; r_ddrb <= x"00"; r_acr <= x"00"; r_pcr <= x"00"; w_orb_hs <= '0'; w_ora_hs <= '0'; elsif rising_edge(CLK) then if (ENA_4 = '1') then w_orb_hs <= '0'; w_ora_hs <= '0'; if (cs = '1') and (I_RW_L = '0') then case I_RS is when x"0" => r_orb <= I_DATA; w_orb_hs <= '1'; when x"1" => r_ora <= I_DATA; w_ora_hs <= '1'; when x"2" => r_ddrb <= I_DATA; when x"3" => r_ddra <= I_DATA; when x"B" => r_acr <= I_DATA; when x"C" => r_pcr <= I_DATA; when x"F" => r_ora <= I_DATA; when others => null; end case; end if; -- Set timer PB7 state, only on rising edge of setting ACR(7) if ((t1_pb7_en_d = '0') and (t1_pb7_en_c = '1')) then t1_pb7 <= '1'; end if; if t1_load_counter then t1_pb7 <= '0'; -- Reset internal timer 1 PB7 state on every timer load elsif t1_toggle = '1' then t1_pb7 <= not t1_pb7; end if; end if; end if; end process; p_write_reg : process (RESET_L, CLK) is begin if (RESET_L = '0') then -- The spec says, this is not reset. -- Fact is that the 1541 VIA1 timer won't work, -- as the firmware ONLY sets the r_t1l_h latch!!!! r_t1l_l <= (others => '1'); -- All latches default to FFFF r_t1l_h <= (others => '1'); r_t2l_l <= (others => '1'); r_t2l_h <= (others => '1'); elsif rising_edge(CLK) then if (ENA_4 = '1') then t1_w_reset_int <= false; t1_load_counter <= false; t2_w_reset_int <= false; t2_load_counter <= false; load_data <= x"00"; sr_write_ena <= false; ifr_write_ena <= false; ier_write_ena <= false; if (cs = '1') and (I_RW_L = '0') then load_data <= I_DATA; case I_RS is when x"4" => r_t1l_l <= I_DATA; when x"5" => r_t1l_h <= I_DATA; t1_w_reset_int <= true; t1_load_counter <= true; when x"6" => r_t1l_l <= I_DATA; when x"7" => r_t1l_h <= I_DATA; t1_w_reset_int <= true; when x"8" => r_t2l_l <= I_DATA; when x"9" => r_t2l_h <= I_DATA; t2_w_reset_int <= true; t2_load_counter <= true; when x"A" => sr_write_ena <= true; when x"D" => ifr_write_ena <= true; when x"E" => ier_write_ena <= true; when others => null; end case; end if; end if; end if; end process; p_oe : process(cs, I_RW_L) begin O_DATA_OE_L <= '1'; if (cs = '1') and (I_RW_L = '1') then O_DATA_OE_L <= '0'; end if; end process; p_read : process(cs, I_RW_L, I_RS, r_irb, r_ira, r_ddrb, r_ddra, t1c, r_t1l_l, r_t1l_h, t2c, r_sr, r_acr, r_pcr, r_ifr, r_ier, r_ora, r_orb, t1_pb7_en_d, t1_pb7) variable orb : std_logic_vector(7 downto 0); begin t1_r_reset_int <= false; t2_r_reset_int <= false; sr_read_ena <= false; r_irb_hs <= '0'; r_ira_hs <= '0'; O_DATA <= x"00"; -- default orb := (r_irb and not r_ddrb) or (r_orb and r_ddrb); -- If PB7 under timer control, assign value from timer if (t1_pb7_en_d = '1') then orb(7) := t1_pb7; end if; if (cs = '1') and (I_RW_L = '1') then case I_RS is when x"0" => O_DATA <= orb; r_irb_hs <= '1'; when x"1" => O_DATA <= (r_ira and not r_ddra) or (r_ora and r_ddra); r_ira_hs <= '1'; when x"2" => O_DATA <= r_ddrb; when x"3" => O_DATA <= r_ddra; when x"4" => O_DATA <= t1c( 7 downto 0); t1_r_reset_int <= true; when x"5" => O_DATA <= t1c(15 downto 8); when x"6" => O_DATA <= r_t1l_l; when x"7" => O_DATA <= r_t1l_h; when x"8" => O_DATA <= t2c( 7 downto 0); t2_r_reset_int <= true; when x"9" => O_DATA <= t2c(15 downto 8); when x"A" => O_DATA <= r_sr; sr_read_ena <= true; when x"B" => O_DATA <= r_acr; when x"C" => O_DATA <= r_pcr; when x"D" => O_DATA <= r_ifr; when x"E" => O_DATA <= ('0' & r_ier); when x"F" => O_DATA <= r_ira; when others => null; end case; end if; end process; -- -- IO -- p_ca1_cb1_sel : process(sr_cb1_oe_l, sr_cb1_out, I_CB1) begin -- if the shift register is enabled, cb1 may be an output -- in this case we should NOT listen to the input as -- CB1 interrupts are not generated by the shift register if (sr_cb1_oe_l = '1') then cb1_in_mux <= I_CB1; else cb1_in_mux <= '1'; end if; end process; p_ca1_cb1_int : process(r_pcr, ca1_ip_reg_c, ca1_ip_reg_d, cb1_ip_reg_c, cb1_ip_reg_d) begin if (r_pcr(0) = '0') then -- ca1 control -- negative edge ca1_int <= (ca1_ip_reg_d = '1') and (ca1_ip_reg_c = '0'); else -- positive edge ca1_int <= (ca1_ip_reg_d = '0') and (ca1_ip_reg_c = '1'); end if; if (r_pcr(4) = '0') then -- cb1 control -- negative edge cb1_int <= (cb1_ip_reg_d = '1') and (cb1_ip_reg_c = '0'); else -- positive edge cb1_int <= (cb1_ip_reg_d = '0') and (cb1_ip_reg_c = '1'); end if; end process; p_ca2_cb2_int : process(r_pcr, ca2_ip_reg_c, ca2_ip_reg_d, cb2_ip_reg_c, cb2_ip_reg_d) begin ca2_int <= false; if (r_pcr(3) = '0') then -- ca2 input if (r_pcr(2) = '0') then -- ca2 edge -- negative edge ca2_int <= (ca2_ip_reg_d = '1') and (ca2_ip_reg_c = '0'); else -- positive edge ca2_int <= (ca2_ip_reg_d = '0') and (ca2_ip_reg_c = '1'); end if; end if; cb2_int <= false; if (r_pcr(7) = '0') then -- cb2 input if (r_pcr(6) = '0') then -- cb2 edge -- negative edge cb2_int <= (cb2_ip_reg_d = '1') and (cb2_ip_reg_c = '0'); else -- positive edge cb2_int <= (cb2_ip_reg_d = '0') and (cb2_ip_reg_c = '1'); end if; end if; end process; p_ca2_cb2 : process(RESET_L, CLK) begin if (RESET_L = '0') then O_CA2 <= '1'; -- Pullup is default O_CA2_OE_L <= '1'; O_CB2 <= '1'; -- Pullup is default O_CB2_OE_L <= '1'; ca_hs_sr <= '0'; ca_hs_pulse <= '0'; cb_hs_sr <= '0'; cb_hs_pulse <= '0'; elsif rising_edge(CLK) then if (ENA_4 = '1') then -- ca if (phase = "00") and ((w_ora_hs = '1') or (r_ira_hs = '1')) then ca_hs_sr <= '1'; elsif ca1_int then ca_hs_sr <= '0'; end if; if (phase = "00") then ca_hs_pulse <= w_ora_hs or r_ira_hs; end if; O_CA2_OE_L <= not r_pcr(3); -- ca2 output case r_pcr(3 downto 1) is when "000" => O_CA2 <= I_CA2; -- input, output follows input when "001" => O_CA2 <= I_CA2; -- input, output follows input when "010" => O_CA2 <= I_CA2; -- input, output follows input when "011" => O_CA2 <= I_CA2; -- input, output follows input when "100" => O_CA2 <= not (ca_hs_sr); -- handshake when "101" => O_CA2 <= not (ca_hs_pulse); -- pulse when "110" => O_CA2 <= '0'; -- low when "111" => O_CA2 <= '1'; -- high when others => null; end case; -- cb if (phase = "00") and (w_orb_hs = '1') then cb_hs_sr <= '1'; elsif cb1_int then cb_hs_sr <= '0'; end if; if (phase = "00") then cb_hs_pulse <= w_orb_hs; end if; O_CB2_OE_L <= not (r_pcr(7) or sr_drive_cb2); -- cb2 output or serial if (sr_drive_cb2 = '1') then -- serial output O_CB2 <= sr_out; else case r_pcr(7 downto 5) is when "000" => O_CB2 <= I_CB2; -- input, output follows input when "001" => O_CB2 <= I_CB2; -- input, output follows input when "010" => O_CB2 <= I_CB2; -- input, output follows input when "011" => O_CB2 <= I_CB2; -- input, output follows input when "100" => O_CB2 <= not (cb_hs_sr); -- handshake when "101" => O_CB2 <= not (cb_hs_pulse); -- pulse when "110" => O_CB2 <= '0'; -- low when "111" => O_CB2 <= '1'; -- high when others => null; end case; end if; end if; end if; end process; O_CB1 <= sr_cb1_out; O_CB1_OE_L <= sr_cb1_oe_l; p_ca_cb_irq : process(RESET_L, CLK) begin if (RESET_L = '0') then ca1_irq <= '0'; ca2_irq <= '0'; cb1_irq <= '0'; cb2_irq <= '0'; elsif rising_edge(CLK) then if (ENA_4 = '1') then -- not pretty if ca1_int then ca1_irq <= '1'; elsif (r_ira_hs = '1') or (w_ora_hs = '1') or (clear_irq(1) = '1') then ca1_irq <= '0'; end if; if ca2_int then ca2_irq <= '1'; else if (((r_ira_hs = '1') or (w_ora_hs = '1')) and (r_pcr(1) = '0')) or (clear_irq(0) = '1') then ca2_irq <= '0'; end if; end if; if cb1_int then cb1_irq <= '1'; elsif (r_irb_hs = '1') or (w_orb_hs = '1') or (clear_irq(4) = '1') then cb1_irq <= '0'; end if; if cb2_int then cb2_irq <= '1'; else if (((r_irb_hs = '1') or (w_orb_hs = '1')) and (r_pcr(5) = '0')) or (clear_irq(3) = '1') then cb2_irq <= '0'; end if; end if; end if; end if; end process; p_input_reg : process(RESET_L, CLK) begin if (RESET_L = '0') then ca1_ip_reg_c <= '0'; ca1_ip_reg_d <= '0'; cb1_ip_reg_c <= '0'; cb1_ip_reg_d <= '0'; ca2_ip_reg_c <= '0'; ca2_ip_reg_d <= '0'; cb2_ip_reg_c <= '0'; cb2_ip_reg_d <= '0'; r_ira <= x"00"; r_irb <= x"00"; elsif rising_edge(CLK) then if (ENA_4 = '1') then -- we have a fast clock, so we can have input registers ca1_ip_reg_c <= I_CA1; ca1_ip_reg_d <= ca1_ip_reg_c; cb1_ip_reg_c <= cb1_in_mux; cb1_ip_reg_d <= cb1_ip_reg_c; ca2_ip_reg_c <= I_CA2; ca2_ip_reg_d <= ca2_ip_reg_c; cb2_ip_reg_c <= I_CB2; cb2_ip_reg_d <= cb2_ip_reg_c; if (r_acr(0) = '0') then r_ira <= I_PA; else -- enable latching if ca1_int then r_ira <= I_PA; end if; end if; if (r_acr(1) = '0') then r_irb <= I_PB; else -- enable latching if cb1_int then r_irb <= I_PB; end if; end if; end if; end if; end process; p_buffers : process(r_ddra, r_ora, r_ddrb, r_acr, r_orb, t1_pb7_en_d, t1_pb7) begin -- data direction reg (ddr) 0 = input, 1 = output O_PA <= r_ora; O_PA_OE_L <= not r_ddra; -- If PB7 is timer driven output set PB7 to the timer state, otherwise use value in ORB register if (t1_pb7_en_d = '1') then O_PB <= t1_pb7 & r_orb(6 downto 0); else O_PB <= r_orb; end if; -- NOTE: r_ddrb(7) must be set to enable T1 output on PB7 - [various datasheets specify this] O_PB_OE_L <= not r_ddrb; end process; -- -- Timer 1 -- -- Detect change in r_acr(7), timer 1 mode for PB7 p_pb7_enable : process begin wait until rising_edge(CLK); if (ENA_4 = '1') then t1_pb7_en_c <= r_acr(7); t1_pb7_en_d <= t1_pb7_en_c; end if; end process; p_timer1_done : process variable done : boolean; begin wait until rising_edge(CLK); if (ENA_4 = '1') then done := (t1c = x"0000"); t1c_done <= done and (phase = "11"); if (phase = "11") and not t1_load_counter then -- Don't set reload if T1L-H written t1_reload_counter <= done; elsif t1_load_counter then -- Cancel a reload when T1L-H written t1_reload_counter <= false; end if; if t1_load_counter then -- done reset on load! t1c_done <= false; end if; end if; end process; p_timer1 : process begin wait until rising_edge(CLK); if (ENA_4 = '1') then if t1_load_counter or (t1_reload_counter and phase = "11") then t1c( 7 downto 0) <= r_t1l_l; t1c(15 downto 8) <= r_t1l_h; -- There is a need to write to Latch HI to enable interrupts for both continuous and one-shot modes if t1_load_counter then t1_int_enable <= true; end if; elsif (phase="11") then t1c <= std_logic_vector(unsigned(t1c) - 1); end if; if t1_load_counter or t1_reload_counter then t1c_active <= true; elsif t1c_done then t1c_active <= false; end if; t1_toggle <= '0'; if t1c_active and t1c_done then if t1_int_enable then -- Set interrupt only if T1L-H has been written t1_toggle <= '1'; t1_irq <= '1'; if (r_acr(6) = '0') then -- Disable further interrupts if in one shot mode t1_int_enable <= false; end if; end if; elsif t1_w_reset_int or t1_r_reset_int or (clear_irq(6) = '1') then t1_irq <= '0'; end if; if t1_load_counter then -- irq reset on load! t1_irq <= '0'; end if; end if; end process; -- -- Timer2 -- p_timer2_pb6_input : process begin wait until rising_edge(CLK); if (ENA_4 = '1') then if (phase = "01") then -- leading edge p2_h t2_pb6 <= I_PB(6); t2_pb6_t1 <= t2_pb6; end if; end if; end process; -- Ensure we don't start counting until the P2 clock after r_acr is changed p_timer2_ena : process begin wait until rising_edge(I_P2_H); if r_acr(5) = '0' then t2_cnt_clk <= '1'; else t2_cnt_clk <= '0'; end if; end process; p_timer2_done : process variable done : boolean; variable done_sr : boolean; begin wait until rising_edge(CLK); if (ENA_4 = '1') then done := (t2c = x"0000"); -- Normal timer expires at 0000 done_sr := (t2c(7 downto 0) = x"00"); -- Shift register expires on low byte = 00 t2c_done <= done and (phase = "11"); if (phase = "11") then t2_reload_counter <= done_sr; -- Timer 2 is only reloaded when used for the shift register end if; if t2_load_counter then -- done reset on load! t2c_done <= false; end if; end if; end process; p_timer2 : process variable ena : boolean; begin wait until rising_edge(CLK); if (ENA_4 = '1') then if (t2_cnt_clk ='1') then ena := true; t2c_active <= true; t2_int_enable <= true; else ena := (t2_pb6_t1 = '1') and (t2_pb6 = '0'); -- falling edge end if; -- Shift register reload is only active when shift register mode using T2 is enabled if t2_reload_counter and (phase="11") and ((r_acr(4 downto 2) = "001") or (r_acr(4 downto 2) = "100") or (r_acr(4 downto 2) = "101")) then t2c(7 downto 0) <= r_t2l_l; -- For shift register only low latch is loaded! elsif t2_load_counter then t2_int_enable <= true; t2c( 7 downto 0) <= r_t2l_l; t2c(15 downto 8) <= r_t2l_h; else if (phase="11") and ena then -- or count mode t2c <= std_logic_vector(unsigned(t2c) - 1); end if; end if; -- Shift register strobe on T2 occurs one P2H clock after timer expires -- so enable the strobe when we roll over to FF t2_sr_ena <= (t2c(7 downto 0) = x"FF") and (phase = "11"); if t2_load_counter then t2c_active <= true; elsif t2c_done then t2c_active <= false; end if; if t2c_active and t2c_done and t2_int_enable then t2_int_enable <= false; t2_irq <= '1'; elsif t2_w_reset_int or t2_r_reset_int or (clear_irq(5) = '1') then t2_irq <= '0'; end if; if t2_load_counter then -- irq reset on load! t2_irq <= '0'; end if; end if; end process; -- -- Shift Register -- p_sr : process(RESET_L, CLK) variable dir_out : std_logic; variable ena : std_logic; variable cb1_op : std_logic; variable cb1_ip : std_logic; variable use_t2 : std_logic; variable free_run : std_logic; variable sr_count_ena : boolean; begin if (RESET_L = '0') then r_sr <= x"00"; sr_drive_cb2 <= '0'; sr_cb1_oe_l <= '1'; sr_cb1_out <= '0'; sr_do_shift <= false; sr_strobe <= '1'; sr_cnt <= "0000"; sr_irq <= '0'; sr_out <= '0'; sr_active <= false; elsif rising_edge(CLK) then if (ENA_4 = '1') then -- decode mode dir_out := r_acr(4); -- output on cb2 cb1_op := '0'; cb1_ip := '0'; use_t2 := '0'; free_run := '0'; -- DMB: SR still runs even in disabled mode (on rising edge of CB1). -- It just doesn't generate any interrupts. -- Ref BBC micro advanced user guide p409 case r_acr(4 downto 2) is -- DMB: in disabled mode, configure cb1 as an input when "000" => ena := '0'; cb1_ip := '1'; -- 0x00 Mode 0 SR disabled when "001" => ena := '1'; cb1_op := '1'; use_t2 := '1'; -- 0x04 Mode 1 Shift in under T2 control when "010" => ena := '1'; cb1_op := '1'; -- 0x08 Mode 2 Shift in under P2 control when "011" => ena := '1'; cb1_ip := '1'; -- 0x0C Mode 3 Shift in under control of ext clock when "100" => ena := '1'; cb1_op := '1'; use_t2 := '1'; free_run := '1'; -- 0x10 Mode 4 Shift out free running under T2 control when "101" => ena := '1'; cb1_op := '1'; use_t2 := '1'; -- 0x14 Mode 5 Shift out under T2 control when "110" => ena := '1'; cb1_op := '1'; -- 0x18 Mode 6 Shift out under P2 control when "111" => ena := '1'; cb1_ip := '1'; -- 0x1C Mode 7 Shift out under control of ext clock when others => null; end case; -- clock select -- DMB: in disabled mode, strobe from cb1 if (cb1_ip = '1') then sr_strobe <= I_CB1; else if (sr_cnt(3) = '0') and (free_run = '0') then sr_strobe <= '1'; else if ((use_t2 = '1') and t2_sr_ena) or ((use_t2 = '0') and (phase = "00")) then sr_strobe <= not sr_strobe; end if; end if; end if; -- latch on rising edge, shift on falling edge of P2 if sr_write_ena then r_sr <= load_data; sr_out <= r_sr(7); else -- DMB: allow shifting in all modes if (dir_out = '0') then -- input if (sr_cnt(3) = '1') or (cb1_ip = '1') then if sr_strobe_rising then sr_do_shift <= true; r_sr(0) <= I_CB2; elsif sr_do_shift then sr_do_shift <= false; r_sr(7 downto 1) <= r_sr(6 downto 0); end if; end if; else -- output if (sr_cnt(3) = '1') or (cb1_ip = '1') or (free_run = '1') then if sr_strobe_falling then sr_out <= r_sr(7); sr_do_shift <= true; elsif sr_do_shift then sr_do_shift <= false; r_sr <= r_sr(6 downto 0) & r_sr(7); end if; end if; end if; end if; -- Set shift enabled flag, note does not get set for free_run mode ! if (ena = '1') and (sr_cnt(3) = '1') then sr_active <= true; elsif (ena = '1') and (sr_cnt(3) = '0') and (phase="11") then sr_active <= false; end if; sr_count_ena := sr_strobe_rising; -- DMB: reseting sr_count when not enabled cause the sr to -- start running immediately it was enabled, which is incorrect -- and broke the latest SmartSPI ROM on the BBC Micro if (ena = '1') and (sr_write_ena or sr_read_ena) and (not sr_active) then -- some documentation says sr bit in IFR must be set as well ? sr_cnt <= "1000"; elsif sr_count_ena and (sr_cnt(3) = '1') then sr_cnt <= std_logic_vector(unsigned(sr_cnt) + 1); end if; if sr_count_ena and (sr_cnt = "1111") and (ena = '1') and (free_run = '0') then sr_irq <= '1'; elsif sr_write_ena or sr_read_ena or (clear_irq(2) = '1') then sr_irq <= '0'; end if; -- assign ops sr_drive_cb2 <= dir_out; sr_cb1_oe_l <= not cb1_op; sr_cb1_out <= sr_strobe; end if; end if; end process; p_sr_strobe_rise_fall : process begin wait until rising_edge(CLK); if (ENA_4 = '1') then sr_strobe_t1 <= sr_strobe; sr_strobe_rising <= (sr_strobe_t1 = '0') and (sr_strobe = '1'); sr_strobe_falling <= (sr_strobe_t1 = '1') and (sr_strobe = '0'); end if; end process; -- -- Interrupts -- p_ier : process(RESET_L, CLK) begin if (RESET_L = '0') then r_ier <= "0000000"; elsif rising_edge(CLK) then if (ENA_4 = '1') then if ier_write_ena then if (load_data(7) = '1') then -- set r_ier <= r_ier or load_data(6 downto 0); else -- clear r_ier <= r_ier and not load_data(6 downto 0); end if; end if; end if; end if; end process; p_ifr : process(t1_irq, t2_irq, final_irq, ca1_irq, ca2_irq, sr_irq, cb1_irq, cb2_irq) begin r_ifr(7) <= final_irq; r_ifr(6) <= t1_irq; r_ifr(5) <= t2_irq; r_ifr(4) <= cb1_irq; r_ifr(3) <= cb2_irq; r_ifr(2) <= sr_irq; r_ifr(1) <= ca1_irq; r_ifr(0) <= ca2_irq; O_IRQ_L <= not final_irq; end process; p_irq : process(RESET_L, CLK) begin if (RESET_L = '0') then final_irq <= '0'; elsif rising_edge(CLK) then if (ENA_4 = '1') then if ((r_ifr(6 downto 0) and r_ier(6 downto 0)) = "0000000") then final_irq <= '0'; -- no interrupts else final_irq <= '1'; end if; end if; end if; end process; p_clear_irq : process(ifr_write_ena, load_data) begin clear_irq <= x"00"; if ifr_write_ena then clear_irq <= load_data; end if; end process; end architecture RTL;
apache-2.0
0ca424aff531475dab98e44eee1935f3
0.457899
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false
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tghaefli/ADD
EDK/IVK_Repos/IVK_IPLib/pcores/sg_xsvi_fanout_plbw_v1_01_a/hdl/vhdl/sg_xsvi_fanout.vhd
1
102,280
------------------------------------------------------------------- -- System Generator version 13.2 VHDL source file. -- -- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; package conv_pkg is constant simulating : boolean := false -- synopsys translate_off or true -- synopsys translate_on ; constant xlUnsigned : integer := 1; constant xlSigned : integer := 2; constant xlFloat : integer := 3; constant xlWrap : integer := 1; constant xlSaturate : integer := 2; constant xlTruncate : integer := 1; constant xlRound : integer := 2; constant xlRoundBanker : integer := 3; constant xlAddMode : integer := 1; constant xlSubMode : integer := 2; attribute black_box : boolean; attribute syn_black_box : boolean; attribute fpga_dont_touch: string; attribute box_type : string; attribute keep : string; attribute syn_keep : boolean; function std_logic_vector_to_unsigned(inp : std_logic_vector) return unsigned; function unsigned_to_std_logic_vector(inp : unsigned) return std_logic_vector; function std_logic_vector_to_signed(inp : std_logic_vector) return signed; function signed_to_std_logic_vector(inp : signed) return std_logic_vector; function unsigned_to_signed(inp : unsigned) return signed; function signed_to_unsigned(inp : signed) return unsigned; function pos(inp : std_logic_vector; arith : INTEGER) return boolean; function all_same(inp: std_logic_vector) return boolean; function all_zeros(inp: std_logic_vector) return boolean; function is_point_five(inp: std_logic_vector) return boolean; function all_ones(inp: std_logic_vector) return boolean; function convert_type (inp : std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith, quantization, overflow : INTEGER) return std_logic_vector; function cast (inp : std_logic_vector; old_bin_pt, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector; function shift_division_result(quotient, fraction: std_logic_vector; fraction_width, shift_value, shift_dir: INTEGER) return std_logic_vector; function shift_op (inp: std_logic_vector; result_width, shift_value, shift_dir: INTEGER) return std_logic_vector; function vec_slice (inp : std_logic_vector; upper, lower : INTEGER) return std_logic_vector; function s2u_slice (inp : signed; upper, lower : INTEGER) return unsigned; function u2u_slice (inp : unsigned; upper, lower : INTEGER) return unsigned; function s2s_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER) return signed; function u2s_cast (inp : unsigned; old_bin_pt, new_width, new_bin_pt : INTEGER) return signed; function s2u_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER) return unsigned; function u2u_cast (inp : unsigned; old_bin_pt, new_width, new_bin_pt : INTEGER) return unsigned; function u2v_cast (inp : unsigned; old_bin_pt, new_width, new_bin_pt : INTEGER) return std_logic_vector; function s2v_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER) return std_logic_vector; function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector; function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector; function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector; function max_signed(width : INTEGER) return std_logic_vector; function min_signed(width : INTEGER) return std_logic_vector; function saturation_arith(inp: std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector; function wrap_arith(inp: std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector; function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER; function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER) return INTEGER; function sign_ext(inp : std_logic_vector; new_width : INTEGER) return std_logic_vector; function zero_ext(inp : std_logic_vector; new_width : INTEGER) return std_logic_vector; function zero_ext(inp : std_logic; new_width : INTEGER) return std_logic_vector; function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER) return std_logic_vector; function align_input(inp : std_logic_vector; old_width, delta, new_arith, new_width: INTEGER) return std_logic_vector; function pad_LSB(inp : std_logic_vector; new_width: integer) return std_logic_vector; function pad_LSB(inp : std_logic_vector; new_width, arith : integer) return std_logic_vector; function max(L, R: INTEGER) return INTEGER; function min(L, R: INTEGER) return INTEGER; function "="(left,right: STRING) return boolean; function boolean_to_signed (inp : boolean; width: integer) return signed; function boolean_to_unsigned (inp : boolean; width: integer) return unsigned; function boolean_to_vector (inp : boolean) return std_logic_vector; function std_logic_to_vector (inp : std_logic) return std_logic_vector; function integer_to_std_logic_vector (inp : integer; width, arith : integer) return std_logic_vector; function std_logic_vector_to_integer (inp : std_logic_vector; arith : integer) return integer; function std_logic_to_integer(constant inp : std_logic := '0') return integer; function bin_string_element_to_std_logic_vector (inp : string; width, index : integer) return std_logic_vector; function bin_string_to_std_logic_vector (inp : string) return std_logic_vector; function hex_string_to_std_logic_vector (inp : string; width : integer) return std_logic_vector; function makeZeroBinStr (width : integer) return STRING; function and_reduce(inp: std_logic_vector) return std_logic; -- synopsys translate_off function is_binary_string_invalid (inp : string) return boolean; function is_binary_string_undefined (inp : string) return boolean; function is_XorU(inp : std_logic_vector) return boolean; function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer) return real; function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer) return real; function real_to_std_logic_vector (inp : real; width, bin_pt, arith : integer) return std_logic_vector; function real_string_to_std_logic_vector (inp : string; width, bin_pt, arith : integer) return std_logic_vector; constant display_precision : integer := 20; function real_to_string (inp : real) return string; function valid_bin_string(inp : string) return boolean; function std_logic_vector_to_bin_string(inp : std_logic_vector) return string; function std_logic_to_bin_string(inp : std_logic) return string; function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer) return string; function real_to_bin_string(inp : real; width, bin_pt, arith : integer) return string; type stdlogic_to_char_t is array(std_logic) of character; constant to_char : stdlogic_to_char_t := ( 'U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z', 'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-'); -- synopsys translate_on end conv_pkg; package body conv_pkg is function std_logic_vector_to_unsigned(inp : std_logic_vector) return unsigned is begin return unsigned (inp); end; function unsigned_to_std_logic_vector(inp : unsigned) return std_logic_vector is begin return std_logic_vector(inp); end; function std_logic_vector_to_signed(inp : std_logic_vector) return signed is begin return signed (inp); end; function signed_to_std_logic_vector(inp : signed) return std_logic_vector is begin return std_logic_vector(inp); end; function unsigned_to_signed (inp : unsigned) return signed is begin return signed(std_logic_vector(inp)); end; function signed_to_unsigned (inp : signed) return unsigned is begin return unsigned(std_logic_vector(inp)); end; function pos(inp : std_logic_vector; arith : INTEGER) return boolean is constant width : integer := inp'length; variable vec : std_logic_vector(width-1 downto 0); begin vec := inp; if arith = xlUnsigned then return true; else if vec(width-1) = '0' then return true; else return false; end if; end if; return true; end; function max_signed(width : INTEGER) return std_logic_vector is variable ones : std_logic_vector(width-2 downto 0); variable result : std_logic_vector(width-1 downto 0); begin ones := (others => '1'); result(width-1) := '0'; result(width-2 downto 0) := ones; return result; end; function min_signed(width : INTEGER) return std_logic_vector is variable zeros : std_logic_vector(width-2 downto 0); variable result : std_logic_vector(width-1 downto 0); begin zeros := (others => '0'); result(width-1) := '1'; result(width-2 downto 0) := zeros; return result; end; function and_reduce(inp: std_logic_vector) return std_logic is variable result: std_logic; constant width : integer := inp'length; variable vec : std_logic_vector(width-1 downto 0); begin vec := inp; result := vec(0); if width > 1 then for i in 1 to width-1 loop result := result and vec(i); end loop; end if; return result; end; function all_same(inp: std_logic_vector) return boolean is variable result: boolean; constant width : integer := inp'length; variable vec : std_logic_vector(width-1 downto 0); begin vec := inp; result := true; if width > 0 then for i in 1 to width-1 loop if vec(i) /= vec(0) then result := false; end if; end loop; end if; return result; end; function all_zeros(inp: std_logic_vector) return boolean is constant width : integer := inp'length; variable vec : std_logic_vector(width-1 downto 0); variable zero : std_logic_vector(width-1 downto 0); variable result : boolean; begin zero := (others => '0'); vec := inp; -- synopsys translate_off if (is_XorU(vec)) then return false; end if; -- synopsys translate_on if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(zero)) then result := true; else result := false; end if; return result; end; function is_point_five(inp: std_logic_vector) return boolean is constant width : integer := inp'length; variable vec : std_logic_vector(width-1 downto 0); variable result : boolean; begin vec := inp; -- synopsys translate_off if (is_XorU(vec)) then return false; end if; -- synopsys translate_on if (width > 1) then if ((vec(width-1) = '1') and (all_zeros(vec(width-2 downto 0)) = true)) then result := true; else result := false; end if; else if (vec(width-1) = '1') then result := true; else result := false; end if; end if; return result; end; function all_ones(inp: std_logic_vector) return boolean is constant width : integer := inp'length; variable vec : std_logic_vector(width-1 downto 0); variable one : std_logic_vector(width-1 downto 0); variable result : boolean; begin one := (others => '1'); vec := inp; -- synopsys translate_off if (is_XorU(vec)) then return false; end if; -- synopsys translate_on if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(one)) then result := true; else result := false; end if; return result; end; function full_precision_num_width(quantization, overflow, old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return integer is variable result : integer; begin result := old_width + 2; return result; end; function quantized_num_width(quantization, overflow, old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return integer is variable right_of_dp, left_of_dp, result : integer; begin right_of_dp := max(new_bin_pt, old_bin_pt); left_of_dp := max((new_width - new_bin_pt), (old_width - old_bin_pt)); result := (old_width + 2) + (new_bin_pt - old_bin_pt); return result; end; function convert_type (inp : std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith, quantization, overflow : INTEGER) return std_logic_vector is constant fp_width : integer := full_precision_num_width(quantization, overflow, old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith); constant fp_bin_pt : integer := old_bin_pt; constant fp_arith : integer := old_arith; variable full_precision_result : std_logic_vector(fp_width-1 downto 0); constant q_width : integer := quantized_num_width(quantization, overflow, old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith); constant q_bin_pt : integer := new_bin_pt; constant q_arith : integer := old_arith; variable quantized_result : std_logic_vector(q_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); begin result := (others => '0'); full_precision_result := cast(inp, old_bin_pt, fp_width, fp_bin_pt, fp_arith); if (quantization = xlRound) then quantized_result := round_towards_inf(full_precision_result, fp_width, fp_bin_pt, fp_arith, q_width, q_bin_pt, q_arith); elsif (quantization = xlRoundBanker) then quantized_result := round_towards_even(full_precision_result, fp_width, fp_bin_pt, fp_arith, q_width, q_bin_pt, q_arith); else quantized_result := trunc(full_precision_result, fp_width, fp_bin_pt, fp_arith, q_width, q_bin_pt, q_arith); end if; if (overflow = xlSaturate) then result := saturation_arith(quantized_result, q_width, q_bin_pt, q_arith, new_width, new_bin_pt, new_arith); else result := wrap_arith(quantized_result, q_width, q_bin_pt, q_arith, new_width, new_bin_pt, new_arith); end if; return result; end; function cast (inp : std_logic_vector; old_bin_pt, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector is constant old_width : integer := inp'length; constant left_of_dp : integer := (new_width - new_bin_pt) - (old_width - old_bin_pt); constant right_of_dp : integer := (new_bin_pt - old_bin_pt); variable vec : std_logic_vector(old_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); variable j : integer; begin vec := inp; for i in new_width-1 downto 0 loop j := i - right_of_dp; if ( j > old_width-1) then if (new_arith = xlUnsigned) then result(i) := '0'; else result(i) := vec(old_width-1); end if; elsif ( j >= 0) then result(i) := vec(j); else result(i) := '0'; end if; end loop; return result; end; function shift_division_result(quotient, fraction: std_logic_vector; fraction_width, shift_value, shift_dir: INTEGER) return std_logic_vector is constant q_width : integer := quotient'length; constant f_width : integer := fraction'length; constant vec_MSB : integer := q_width+f_width-1; constant result_MSB : integer := q_width+fraction_width-1; constant result_LSB : integer := vec_MSB-result_MSB; variable vec : std_logic_vector(vec_MSB downto 0); variable result : std_logic_vector(result_MSB downto 0); begin vec := ( quotient & fraction ); if shift_dir = 1 then for i in vec_MSB downto 0 loop if (i < shift_value) then vec(i) := '0'; else vec(i) := vec(i-shift_value); end if; end loop; else for i in 0 to vec_MSB loop if (i > vec_MSB-shift_value) then vec(i) := vec(vec_MSB); else vec(i) := vec(i+shift_value); end if; end loop; end if; result := vec(vec_MSB downto result_LSB); return result; end; function shift_op (inp: std_logic_vector; result_width, shift_value, shift_dir: INTEGER) return std_logic_vector is constant inp_width : integer := inp'length; constant vec_MSB : integer := inp_width-1; constant result_MSB : integer := result_width-1; constant result_LSB : integer := vec_MSB-result_MSB; variable vec : std_logic_vector(vec_MSB downto 0); variable result : std_logic_vector(result_MSB downto 0); begin vec := inp; if shift_dir = 1 then for i in vec_MSB downto 0 loop if (i < shift_value) then vec(i) := '0'; else vec(i) := vec(i-shift_value); end if; end loop; else for i in 0 to vec_MSB loop if (i > vec_MSB-shift_value) then vec(i) := vec(vec_MSB); else vec(i) := vec(i+shift_value); end if; end loop; end if; result := vec(vec_MSB downto result_LSB); return result; end; function vec_slice (inp : std_logic_vector; upper, lower : INTEGER) return std_logic_vector is begin return inp(upper downto lower); end; function s2u_slice (inp : signed; upper, lower : INTEGER) return unsigned is begin return unsigned(vec_slice(std_logic_vector(inp), upper, lower)); end; function u2u_slice (inp : unsigned; upper, lower : INTEGER) return unsigned is begin return unsigned(vec_slice(std_logic_vector(inp), upper, lower)); end; function s2s_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER) return signed is begin return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned)); end; function s2u_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER) return unsigned is begin return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned)); end; function u2s_cast (inp : unsigned; old_bin_pt, new_width, new_bin_pt : INTEGER) return signed is begin return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned)); end; function u2u_cast (inp : unsigned; old_bin_pt, new_width, new_bin_pt : INTEGER) return unsigned is begin return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned)); end; function u2v_cast (inp : unsigned; old_bin_pt, new_width, new_bin_pt : INTEGER) return std_logic_vector is begin return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned); end; function s2v_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER) return std_logic_vector is begin return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned); end; function boolean_to_signed (inp : boolean; width : integer) return signed is variable result : signed(width - 1 downto 0); begin result := (others => '0'); if inp then result(0) := '1'; else result(0) := '0'; end if; return result; end; function boolean_to_unsigned (inp : boolean; width : integer) return unsigned is variable result : unsigned(width - 1 downto 0); begin result := (others => '0'); if inp then result(0) := '1'; else result(0) := '0'; end if; return result; end; function boolean_to_vector (inp : boolean) return std_logic_vector is variable result : std_logic_vector(1 - 1 downto 0); begin result := (others => '0'); if inp then result(0) := '1'; else result(0) := '0'; end if; return result; end; function std_logic_to_vector (inp : std_logic) return std_logic_vector is variable result : std_logic_vector(1 - 1 downto 0); begin result(0) := inp; return result; end; function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector is constant right_of_dp : integer := (old_bin_pt - new_bin_pt); variable vec : std_logic_vector(old_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); begin vec := inp; if right_of_dp >= 0 then if new_arith = xlUnsigned then result := zero_ext(vec(old_width-1 downto right_of_dp), new_width); else result := sign_ext(vec(old_width-1 downto right_of_dp), new_width); end if; else if new_arith = xlUnsigned then result := zero_ext(pad_LSB(vec, old_width + abs(right_of_dp)), new_width); else result := sign_ext(pad_LSB(vec, old_width + abs(right_of_dp)), new_width); end if; end if; return result; end; function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector is constant right_of_dp : integer := (old_bin_pt - new_bin_pt); constant expected_new_width : integer := old_width - right_of_dp + 1; variable vec : std_logic_vector(old_width-1 downto 0); variable one_or_zero : std_logic_vector(new_width-1 downto 0); variable truncated_val : std_logic_vector(new_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); begin vec := inp; if right_of_dp >= 0 then if new_arith = xlUnsigned then truncated_val := zero_ext(vec(old_width-1 downto right_of_dp), new_width); else truncated_val := sign_ext(vec(old_width-1 downto right_of_dp), new_width); end if; else if new_arith = xlUnsigned then truncated_val := zero_ext(pad_LSB(vec, old_width + abs(right_of_dp)), new_width); else truncated_val := sign_ext(pad_LSB(vec, old_width + abs(right_of_dp)), new_width); end if; end if; one_or_zero := (others => '0'); if (new_arith = xlSigned) then if (vec(old_width-1) = '0') then one_or_zero(0) := '1'; end if; if (right_of_dp >= 2) and (right_of_dp <= old_width) then if (all_zeros(vec(right_of_dp-2 downto 0)) = false) then one_or_zero(0) := '1'; end if; end if; if (right_of_dp >= 1) and (right_of_dp <= old_width) then if vec(right_of_dp-1) = '0' then one_or_zero(0) := '0'; end if; else one_or_zero(0) := '0'; end if; else if (right_of_dp >= 1) and (right_of_dp <= old_width) then one_or_zero(0) := vec(right_of_dp-1); end if; end if; if new_arith = xlSigned then result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) + std_logic_vector_to_signed(one_or_zero)); else result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) + std_logic_vector_to_unsigned(one_or_zero)); end if; return result; end; function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector is constant right_of_dp : integer := (old_bin_pt - new_bin_pt); constant expected_new_width : integer := old_width - right_of_dp + 1; variable vec : std_logic_vector(old_width-1 downto 0); variable one_or_zero : std_logic_vector(new_width-1 downto 0); variable truncated_val : std_logic_vector(new_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); begin vec := inp; if right_of_dp >= 0 then if new_arith = xlUnsigned then truncated_val := zero_ext(vec(old_width-1 downto right_of_dp), new_width); else truncated_val := sign_ext(vec(old_width-1 downto right_of_dp), new_width); end if; else if new_arith = xlUnsigned then truncated_val := zero_ext(pad_LSB(vec, old_width + abs(right_of_dp)), new_width); else truncated_val := sign_ext(pad_LSB(vec, old_width + abs(right_of_dp)), new_width); end if; end if; one_or_zero := (others => '0'); if (right_of_dp >= 1) and (right_of_dp <= old_width) then if (is_point_five(vec(right_of_dp-1 downto 0)) = false) then one_or_zero(0) := vec(right_of_dp-1); else one_or_zero(0) := vec(right_of_dp); end if; end if; if new_arith = xlSigned then result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) + std_logic_vector_to_signed(one_or_zero)); else result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) + std_logic_vector_to_unsigned(one_or_zero)); end if; return result; end; function saturation_arith(inp: std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector is constant left_of_dp : integer := (old_width - old_bin_pt) - (new_width - new_bin_pt); variable vec : std_logic_vector(old_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); variable overflow : boolean; begin vec := inp; overflow := true; result := (others => '0'); if (new_width >= old_width) then overflow := false; end if; if ((old_arith = xlSigned and new_arith = xlSigned) and (old_width > new_width)) then if all_same(vec(old_width-1 downto new_width-1)) then overflow := false; end if; end if; if (old_arith = xlSigned and new_arith = xlUnsigned) then if (old_width > new_width) then if all_zeros(vec(old_width-1 downto new_width)) then overflow := false; end if; else if (old_width = new_width) then if (vec(new_width-1) = '0') then overflow := false; end if; end if; end if; end if; if (old_arith = xlUnsigned and new_arith = xlUnsigned) then if (old_width > new_width) then if all_zeros(vec(old_width-1 downto new_width)) then overflow := false; end if; else if (old_width = new_width) then overflow := false; end if; end if; end if; if ((old_arith = xlUnsigned and new_arith = xlSigned) and (old_width > new_width)) then if all_same(vec(old_width-1 downto new_width-1)) then overflow := false; end if; end if; if overflow then if new_arith = xlSigned then if vec(old_width-1) = '0' then result := max_signed(new_width); else result := min_signed(new_width); end if; else if ((old_arith = xlSigned) and vec(old_width-1) = '1') then result := (others => '0'); else result := (others => '1'); end if; end if; else if (old_arith = xlSigned) and (new_arith = xlUnsigned) then if (vec(old_width-1) = '1') then vec := (others => '0'); end if; end if; if new_width <= old_width then result := vec(new_width-1 downto 0); else if new_arith = xlUnsigned then result := zero_ext(vec, new_width); else result := sign_ext(vec, new_width); end if; end if; end if; return result; end; function wrap_arith(inp: std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector is variable result : std_logic_vector(new_width-1 downto 0); variable result_arith : integer; begin if (old_arith = xlSigned) and (new_arith = xlUnsigned) then result_arith := xlSigned; end if; result := cast(inp, old_bin_pt, new_width, new_bin_pt, result_arith); return result; end; function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER is begin return max(a_bin_pt, b_bin_pt); end; function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER) return INTEGER is begin return max(a_width - a_bin_pt, b_width - b_bin_pt); end; function pad_LSB(inp : std_logic_vector; new_width: integer) return STD_LOGIC_VECTOR is constant orig_width : integer := inp'length; variable vec : std_logic_vector(orig_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); variable pos : integer; constant pad_pos : integer := new_width - orig_width - 1; begin vec := inp; pos := new_width-1; if (new_width >= orig_width) then for i in orig_width-1 downto 0 loop result(pos) := vec(i); pos := pos - 1; end loop; if pad_pos >= 0 then for i in pad_pos downto 0 loop result(i) := '0'; end loop; end if; end if; return result; end; function sign_ext(inp : std_logic_vector; new_width : INTEGER) return std_logic_vector is constant old_width : integer := inp'length; variable vec : std_logic_vector(old_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); begin vec := inp; if new_width >= old_width then result(old_width-1 downto 0) := vec; if new_width-1 >= old_width then for i in new_width-1 downto old_width loop result(i) := vec(old_width-1); end loop; end if; else result(new_width-1 downto 0) := vec(new_width-1 downto 0); end if; return result; end; function zero_ext(inp : std_logic_vector; new_width : INTEGER) return std_logic_vector is constant old_width : integer := inp'length; variable vec : std_logic_vector(old_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); begin vec := inp; if new_width >= old_width then result(old_width-1 downto 0) := vec; if new_width-1 >= old_width then for i in new_width-1 downto old_width loop result(i) := '0'; end loop; end if; else result(new_width-1 downto 0) := vec(new_width-1 downto 0); end if; return result; end; function zero_ext(inp : std_logic; new_width : INTEGER) return std_logic_vector is variable result : std_logic_vector(new_width-1 downto 0); begin result(0) := inp; for i in new_width-1 downto 1 loop result(i) := '0'; end loop; return result; end; function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER) return std_logic_vector is constant orig_width : integer := inp'length; variable vec : std_logic_vector(orig_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); begin vec := inp; if arith = xlUnsigned then result := zero_ext(vec, new_width); else result := sign_ext(vec, new_width); end if; return result; end; function pad_LSB(inp : std_logic_vector; new_width, arith: integer) return STD_LOGIC_VECTOR is constant orig_width : integer := inp'length; variable vec : std_logic_vector(orig_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); variable pos : integer; begin vec := inp; pos := new_width-1; if (arith = xlUnsigned) then result(pos) := '0'; pos := pos - 1; else result(pos) := vec(orig_width-1); pos := pos - 1; end if; if (new_width >= orig_width) then for i in orig_width-1 downto 0 loop result(pos) := vec(i); pos := pos - 1; end loop; if pos >= 0 then for i in pos downto 0 loop result(i) := '0'; end loop; end if; end if; return result; end; function align_input(inp : std_logic_vector; old_width, delta, new_arith, new_width: INTEGER) return std_logic_vector is variable vec : std_logic_vector(old_width-1 downto 0); variable padded_inp : std_logic_vector((old_width + delta)-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); begin vec := inp; if delta > 0 then padded_inp := pad_LSB(vec, old_width+delta); result := extend_MSB(padded_inp, new_width, new_arith); else result := extend_MSB(vec, new_width, new_arith); end if; return result; end; function max(L, R: INTEGER) return INTEGER is begin if L > R then return L; else return R; end if; end; function min(L, R: INTEGER) return INTEGER is begin if L < R then return L; else return R; end if; end; function "="(left,right: STRING) return boolean is begin if (left'length /= right'length) then return false; else test : for i in 1 to left'length loop if left(i) /= right(i) then return false; end if; end loop test; return true; end if; end; -- synopsys translate_off function is_binary_string_invalid (inp : string) return boolean is variable vec : string(1 to inp'length); variable result : boolean; begin vec := inp; result := false; for i in 1 to vec'length loop if ( vec(i) = 'X' ) then result := true; end if; end loop; return result; end; function is_binary_string_undefined (inp : string) return boolean is variable vec : string(1 to inp'length); variable result : boolean; begin vec := inp; result := false; for i in 1 to vec'length loop if ( vec(i) = 'U' ) then result := true; end if; end loop; return result; end; function is_XorU(inp : std_logic_vector) return boolean is constant width : integer := inp'length; variable vec : std_logic_vector(width-1 downto 0); variable result : boolean; begin vec := inp; result := false; for i in 0 to width-1 loop if (vec(i) = 'U') or (vec(i) = 'X') then result := true; end if; end loop; return result; end; function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer) return real is variable vec : std_logic_vector(inp'length-1 downto 0); variable result, shift_val, undefined_real : real; variable neg_num : boolean; begin vec := inp; result := 0.0; neg_num := false; if vec(inp'length-1) = '1' then neg_num := true; end if; for i in 0 to inp'length-1 loop if vec(i) = 'U' or vec(i) = 'X' then return undefined_real; end if; if arith = xlSigned then if neg_num then if vec(i) = '0' then result := result + 2.0**i; end if; else if vec(i) = '1' then result := result + 2.0**i; end if; end if; else if vec(i) = '1' then result := result + 2.0**i; end if; end if; end loop; if arith = xlSigned then if neg_num then result := result + 1.0; result := result * (-1.0); end if; end if; shift_val := 2.0**(-1*bin_pt); result := result * shift_val; return result; end; function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer) return real is variable result : real := 0.0; begin if inp = '1' then result := 1.0; end if; if arith = xlSigned then assert false report "It doesn't make sense to convert a 1 bit number to a signed real."; end if; return result; end; -- synopsys translate_on function integer_to_std_logic_vector (inp : integer; width, arith : integer) return std_logic_vector is variable result : std_logic_vector(width-1 downto 0); variable unsigned_val : unsigned(width-1 downto 0); variable signed_val : signed(width-1 downto 0); begin if (arith = xlSigned) then signed_val := to_signed(inp, width); result := signed_to_std_logic_vector(signed_val); else unsigned_val := to_unsigned(inp, width); result := unsigned_to_std_logic_vector(unsigned_val); end if; return result; end; function std_logic_vector_to_integer (inp : std_logic_vector; arith : integer) return integer is constant width : integer := inp'length; variable unsigned_val : unsigned(width-1 downto 0); variable signed_val : signed(width-1 downto 0); variable result : integer; begin if (arith = xlSigned) then signed_val := std_logic_vector_to_signed(inp); result := to_integer(signed_val); else unsigned_val := std_logic_vector_to_unsigned(inp); result := to_integer(unsigned_val); end if; return result; end; function std_logic_to_integer(constant inp : std_logic := '0') return integer is begin if inp = '1' then return 1; else return 0; end if; end; function makeZeroBinStr (width : integer) return STRING is variable result : string(1 to width+3); begin result(1) := '0'; result(2) := 'b'; for i in 3 to width+2 loop result(i) := '0'; end loop; result(width+3) := '.'; return result; end; -- synopsys translate_off function real_string_to_std_logic_vector (inp : string; width, bin_pt, arith : integer) return std_logic_vector is variable result : std_logic_vector(width-1 downto 0); begin result := (others => '0'); return result; end; function real_to_std_logic_vector (inp : real; width, bin_pt, arith : integer) return std_logic_vector is variable real_val : real; variable int_val : integer; variable result : std_logic_vector(width-1 downto 0) := (others => '0'); variable unsigned_val : unsigned(width-1 downto 0) := (others => '0'); variable signed_val : signed(width-1 downto 0) := (others => '0'); begin real_val := inp; int_val := integer(real_val * 2.0**(bin_pt)); if (arith = xlSigned) then signed_val := to_signed(int_val, width); result := signed_to_std_logic_vector(signed_val); else unsigned_val := to_unsigned(int_val, width); result := unsigned_to_std_logic_vector(unsigned_val); end if; return result; end; -- synopsys translate_on function valid_bin_string (inp : string) return boolean is variable vec : string(1 to inp'length); begin vec := inp; if (vec(1) = '0' and vec(2) = 'b') then return true; else return false; end if; end; function hex_string_to_std_logic_vector(inp: string; width : integer) return std_logic_vector is constant strlen : integer := inp'LENGTH; variable result : std_logic_vector(width-1 downto 0); variable bitval : std_logic_vector((strlen*4)-1 downto 0); variable posn : integer; variable ch : character; variable vec : string(1 to strlen); begin vec := inp; result := (others => '0'); posn := (strlen*4)-1; for i in 1 to strlen loop ch := vec(i); case ch is when '0' => bitval(posn downto posn-3) := "0000"; when '1' => bitval(posn downto posn-3) := "0001"; when '2' => bitval(posn downto posn-3) := "0010"; when '3' => bitval(posn downto posn-3) := "0011"; when '4' => bitval(posn downto posn-3) := "0100"; when '5' => bitval(posn downto posn-3) := "0101"; when '6' => bitval(posn downto posn-3) := "0110"; when '7' => bitval(posn downto posn-3) := "0111"; when '8' => bitval(posn downto posn-3) := "1000"; when '9' => bitval(posn downto posn-3) := "1001"; when 'A' | 'a' => bitval(posn downto posn-3) := "1010"; when 'B' | 'b' => bitval(posn downto posn-3) := "1011"; when 'C' | 'c' => bitval(posn downto posn-3) := "1100"; when 'D' | 'd' => bitval(posn downto posn-3) := "1101"; when 'E' | 'e' => bitval(posn downto posn-3) := "1110"; when 'F' | 'f' => bitval(posn downto posn-3) := "1111"; when others => bitval(posn downto posn-3) := "XXXX"; -- synopsys translate_off ASSERT false REPORT "Invalid hex value" SEVERITY ERROR; -- synopsys translate_on end case; posn := posn - 4; end loop; if (width <= strlen*4) then result := bitval(width-1 downto 0); else result((strlen*4)-1 downto 0) := bitval; end if; return result; end; function bin_string_to_std_logic_vector (inp : string) return std_logic_vector is variable pos : integer; variable vec : string(1 to inp'length); variable result : std_logic_vector(inp'length-1 downto 0); begin vec := inp; pos := inp'length-1; result := (others => '0'); for i in 1 to vec'length loop -- synopsys translate_off if (pos < 0) and (vec(i) = '0' or vec(i) = '1' or vec(i) = 'X' or vec(i) = 'U') then assert false report "Input string is larger than output std_logic_vector. Truncating output."; return result; end if; -- synopsys translate_on if vec(i) = '0' then result(pos) := '0'; pos := pos - 1; end if; if vec(i) = '1' then result(pos) := '1'; pos := pos - 1; end if; -- synopsys translate_off if (vec(i) = 'X' or vec(i) = 'U') then result(pos) := 'U'; pos := pos - 1; end if; -- synopsys translate_on end loop; return result; end; function bin_string_element_to_std_logic_vector (inp : string; width, index : integer) return std_logic_vector is constant str_width : integer := width + 4; constant inp_len : integer := inp'length; constant num_elements : integer := (inp_len + 1)/str_width; constant reverse_index : integer := (num_elements-1) - index; variable left_pos : integer; variable right_pos : integer; variable vec : string(1 to inp'length); variable result : std_logic_vector(width-1 downto 0); begin vec := inp; result := (others => '0'); if (reverse_index = 0) and (reverse_index < num_elements) and (inp_len-3 >= width) then left_pos := 1; right_pos := width + 3; result := bin_string_to_std_logic_vector(vec(left_pos to right_pos)); end if; if (reverse_index > 0) and (reverse_index < num_elements) and (inp_len-3 >= width) then left_pos := (reverse_index * str_width) + 1; right_pos := left_pos + width + 2; result := bin_string_to_std_logic_vector(vec(left_pos to right_pos)); end if; return result; end; -- synopsys translate_off function std_logic_vector_to_bin_string(inp : std_logic_vector) return string is variable vec : std_logic_vector(1 to inp'length); variable result : string(vec'range); begin vec := inp; for i in vec'range loop result(i) := to_char(vec(i)); end loop; return result; end; function std_logic_to_bin_string(inp : std_logic) return string is variable result : string(1 to 3); begin result(1) := '0'; result(2) := 'b'; result(3) := to_char(inp); return result; end; function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer) return string is variable width : integer := inp'length; variable vec : std_logic_vector(width-1 downto 0); variable str_pos : integer; variable result : string(1 to width+3); begin vec := inp; str_pos := 1; result(str_pos) := '0'; str_pos := 2; result(str_pos) := 'b'; str_pos := 3; for i in width-1 downto 0 loop if (((width+3) - bin_pt) = str_pos) then result(str_pos) := '.'; str_pos := str_pos + 1; end if; result(str_pos) := to_char(vec(i)); str_pos := str_pos + 1; end loop; if (bin_pt = 0) then result(str_pos) := '.'; end if; return result; end; function real_to_bin_string(inp : real; width, bin_pt, arith : integer) return string is variable result : string(1 to width); variable vec : std_logic_vector(width-1 downto 0); begin vec := real_to_std_logic_vector(inp, width, bin_pt, arith); result := std_logic_vector_to_bin_string(vec); return result; end; function real_to_string (inp : real) return string is variable result : string(1 to display_precision) := (others => ' '); begin result(real'image(inp)'range) := real'image(inp); return result; end; -- synopsys translate_on end conv_pkg; ------------------------------------------------------------------- -- System Generator version 13.2 VHDL source file. -- -- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- -- synopsys translate_off library unisim; use unisim.vcomponents.all; -- synopsys translate_on library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity srl17e is generic (width : integer:=16; latency : integer :=8); port (clk : in std_logic; ce : in std_logic; d : in std_logic_vector(width-1 downto 0); q : out std_logic_vector(width-1 downto 0)); end srl17e; architecture structural of srl17e is component SRL16E port (D : in STD_ULOGIC; CE : in STD_ULOGIC; CLK : in STD_ULOGIC; A0 : in STD_ULOGIC; A1 : in STD_ULOGIC; A2 : in STD_ULOGIC; A3 : in STD_ULOGIC; Q : out STD_ULOGIC); end component; attribute syn_black_box of SRL16E : component is true; attribute fpga_dont_touch of SRL16E : component is "true"; component FDE port( Q : out STD_ULOGIC; D : in STD_ULOGIC; C : in STD_ULOGIC; CE : in STD_ULOGIC); end component; attribute syn_black_box of FDE : component is true; attribute fpga_dont_touch of FDE : component is "true"; constant a : std_logic_vector(4 downto 0) := integer_to_std_logic_vector(latency-2,5,xlSigned); signal d_delayed : std_logic_vector(width-1 downto 0); signal srl16_out : std_logic_vector(width-1 downto 0); begin d_delayed <= d after 200 ps; reg_array : for i in 0 to width-1 generate srl16_used: if latency > 1 generate u1 : srl16e port map(clk => clk, d => d_delayed(i), q => srl16_out(i), ce => ce, a0 => a(0), a1 => a(1), a2 => a(2), a3 => a(3)); end generate; srl16_not_used: if latency <= 1 generate srl16_out(i) <= d_delayed(i); end generate; fde_used: if latency /= 0 generate u2 : fde port map(c => clk, d => srl16_out(i), q => q(i), ce => ce); end generate; fde_not_used: if latency = 0 generate q(i) <= srl16_out(i); end generate; end generate; end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity synth_reg is generic (width : integer := 8; latency : integer := 1); port (i : in std_logic_vector(width-1 downto 0); ce : in std_logic; clr : in std_logic; clk : in std_logic; o : out std_logic_vector(width-1 downto 0)); end synth_reg; architecture structural of synth_reg is component srl17e generic (width : integer:=16; latency : integer :=8); port (clk : in std_logic; ce : in std_logic; d : in std_logic_vector(width-1 downto 0); q : out std_logic_vector(width-1 downto 0)); end component; function calc_num_srl17es (latency : integer) return integer is variable remaining_latency : integer; variable result : integer; begin result := latency / 17; remaining_latency := latency - (result * 17); if (remaining_latency /= 0) then result := result + 1; end if; return result; end; constant complete_num_srl17es : integer := latency / 17; constant num_srl17es : integer := calc_num_srl17es(latency); constant remaining_latency : integer := latency - (complete_num_srl17es * 17); type register_array is array (num_srl17es downto 0) of std_logic_vector(width-1 downto 0); signal z : register_array; begin z(0) <= i; complete_ones : if complete_num_srl17es > 0 generate srl17e_array: for i in 0 to complete_num_srl17es-1 generate delay_comp : srl17e generic map (width => width, latency => 17) port map (clk => clk, ce => ce, d => z(i), q => z(i+1)); end generate; end generate; partial_one : if remaining_latency > 0 generate last_srl17e : srl17e generic map (width => width, latency => remaining_latency) port map (clk => clk, ce => ce, d => z(num_srl17es-1), q => z(num_srl17es)); end generate; o <= z(num_srl17es); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity synth_reg_reg is generic (width : integer := 8; latency : integer := 1); port (i : in std_logic_vector(width-1 downto 0); ce : in std_logic; clr : in std_logic; clk : in std_logic; o : out std_logic_vector(width-1 downto 0)); end synth_reg_reg; architecture behav of synth_reg_reg is type reg_array_type is array (latency-1 downto 0) of std_logic_vector(width -1 downto 0); signal reg_bank : reg_array_type := (others => (others => '0')); signal reg_bank_in : reg_array_type := (others => (others => '0')); attribute syn_allow_retiming : boolean; attribute syn_srlstyle : string; attribute syn_allow_retiming of reg_bank : signal is true; attribute syn_allow_retiming of reg_bank_in : signal is true; attribute syn_srlstyle of reg_bank : signal is "registers"; attribute syn_srlstyle of reg_bank_in : signal is "registers"; begin latency_eq_0: if latency = 0 generate o <= i; end generate latency_eq_0; latency_gt_0: if latency >= 1 generate o <= reg_bank(latency-1); reg_bank_in(0) <= i; loop_gen: for idx in latency-2 downto 0 generate reg_bank_in(idx+1) <= reg_bank(idx); end generate loop_gen; sync_loop: for sync_idx in latency-1 downto 0 generate sync_proc: process (clk) begin if clk'event and clk = '1' then if clr = '1' then reg_bank_in <= (others => (others => '0')); elsif ce = '1' then reg_bank(sync_idx) <= reg_bank_in(sync_idx); end if; end if; end process sync_proc; end generate sync_loop; end generate latency_gt_0; end behav; ------------------------------------------------------------------- -- System Generator version 13.2 VHDL source file. -- -- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- -- synopsys translate_off library unisim; use unisim.vcomponents.all; -- synopsys translate_on library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity single_reg_w_init is generic ( width: integer := 8; init_index: integer := 0; init_value: bit_vector := b"0000" ); port ( i: in std_logic_vector(width - 1 downto 0); ce: in std_logic; clr: in std_logic; clk: in std_logic; o: out std_logic_vector(width - 1 downto 0) ); end single_reg_w_init; architecture structural of single_reg_w_init is function build_init_const(width: integer; init_index: integer; init_value: bit_vector) return std_logic_vector is variable result: std_logic_vector(width - 1 downto 0); begin if init_index = 0 then result := (others => '0'); elsif init_index = 1 then result := (others => '0'); result(0) := '1'; else result := to_stdlogicvector(init_value); end if; return result; end; component fdre port ( q: out std_ulogic; d: in std_ulogic; c: in std_ulogic; ce: in std_ulogic; r: in std_ulogic ); end component; attribute syn_black_box of fdre: component is true; attribute fpga_dont_touch of fdre: component is "true"; component fdse port ( q: out std_ulogic; d: in std_ulogic; c: in std_ulogic; ce: in std_ulogic; s: in std_ulogic ); end component; attribute syn_black_box of fdse: component is true; attribute fpga_dont_touch of fdse: component is "true"; constant init_const: std_logic_vector(width - 1 downto 0) := build_init_const(width, init_index, init_value); begin fd_prim_array: for index in 0 to width - 1 generate bit_is_0: if (init_const(index) = '0') generate fdre_comp: fdre port map ( c => clk, d => i(index), q => o(index), ce => ce, r => clr ); end generate; bit_is_1: if (init_const(index) = '1') generate fdse_comp: fdse port map ( c => clk, d => i(index), q => o(index), ce => ce, s => clr ); end generate; end generate; end architecture structural; -- synopsys translate_off library unisim; use unisim.vcomponents.all; -- synopsys translate_on library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity synth_reg_w_init is generic ( width: integer := 8; init_index: integer := 0; init_value: bit_vector := b"0000"; latency: integer := 1 ); port ( i: in std_logic_vector(width - 1 downto 0); ce: in std_logic; clr: in std_logic; clk: in std_logic; o: out std_logic_vector(width - 1 downto 0) ); end synth_reg_w_init; architecture structural of synth_reg_w_init is component single_reg_w_init generic ( width: integer := 8; init_index: integer := 0; init_value: bit_vector := b"0000" ); port ( i: in std_logic_vector(width - 1 downto 0); ce: in std_logic; clr: in std_logic; clk: in std_logic; o: out std_logic_vector(width - 1 downto 0) ); end component; signal dly_i: std_logic_vector((latency + 1) * width - 1 downto 0); signal dly_clr: std_logic; begin latency_eq_0: if (latency = 0) generate o <= i; end generate; latency_gt_0: if (latency >= 1) generate dly_i((latency + 1) * width - 1 downto latency * width) <= i after 200 ps; dly_clr <= clr after 200 ps; fd_array: for index in latency downto 1 generate reg_comp: single_reg_w_init generic map ( width => width, init_index => init_index, init_value => init_value ) port map ( clk => clk, i => dly_i((index + 1) * width - 1 downto index * width), o => dly_i(index * width - 1 downto (index - 1) * width), ce => ce, clr => dly_clr ); end generate; o <= dly_i(width - 1 downto 0); end generate; end structural; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity constant_963ed6358a is port ( op : out std_logic_vector((1 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end constant_963ed6358a; architecture behavior of constant_963ed6358a is begin op <= "0"; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity mcode_block_f4d0462e0e is port ( plbrst : in std_logic_vector((1 - 1) downto 0); plbabus : in std_logic_vector((32 - 1) downto 0); plbpavalid : in std_logic_vector((1 - 1) downto 0); plbrnw : in std_logic_vector((1 - 1) downto 0); plbwrdbus : in std_logic_vector((32 - 1) downto 0); rddata : in std_logic_vector((32 - 1) downto 0); addrpref : in std_logic_vector((20 - 1) downto 0); wrdbusreg : out std_logic_vector((32 - 1) downto 0); addrack : out std_logic_vector((1 - 1) downto 0); rdcomp : out std_logic_vector((1 - 1) downto 0); wrdack : out std_logic_vector((1 - 1) downto 0); bankaddr : out std_logic_vector((2 - 1) downto 0); rnwreg : out std_logic_vector((1 - 1) downto 0); rddack : out std_logic_vector((1 - 1) downto 0); rddbus : out std_logic_vector((32 - 1) downto 0); linearaddr : out std_logic_vector((8 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end mcode_block_f4d0462e0e; architecture behavior of mcode_block_f4d0462e0e is signal plbrst_1_110: unsigned((1 - 1) downto 0); signal plbabus_1_118: unsigned((32 - 1) downto 0); signal plbpavalid_1_127: unsigned((1 - 1) downto 0); signal plbrnw_1_139: unsigned((1 - 1) downto 0); signal plbwrdbus_1_147: unsigned((32 - 1) downto 0); signal rddata_1_158: unsigned((32 - 1) downto 0); signal addrpref_1_166: unsigned((20 - 1) downto 0); signal plbrstreg_12_24_next: boolean; signal plbrstreg_12_24: boolean := false; signal plbabusreg_13_25_next: unsigned((32 - 1) downto 0); signal plbabusreg_13_25: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000"; signal plbpavalidreg_14_28_next: boolean; signal plbpavalidreg_14_28: boolean := false; signal plbrnwreg_15_24_next: unsigned((1 - 1) downto 0); signal plbrnwreg_15_24: unsigned((1 - 1) downto 0) := "0"; signal plbwrdbusreg_16_27_next: unsigned((32 - 1) downto 0); signal plbwrdbusreg_16_27: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000"; signal avalidreg_28_23_next: boolean; signal avalidreg_28_23: boolean := false; signal ps1reg_39_20_next: boolean; signal ps1reg_39_20: boolean := false; signal psreg_47_19_next: boolean; signal psreg_47_19: boolean := false; type array_type_rdcompdelay_58_25 is array (0 to (3 - 1)) of unsigned((1 - 1) downto 0); signal rdcompdelay_58_25: array_type_rdcompdelay_58_25 := ( "0", "0", "0"); signal rdcompdelay_58_25_front_din: unsigned((1 - 1) downto 0); signal rdcompdelay_58_25_back: unsigned((1 - 1) downto 0); signal rdcompdelay_58_25_push_front_pop_back_en: std_logic; signal rdcompreg_62_23_next: unsigned((1 - 1) downto 0); signal rdcompreg_62_23: unsigned((1 - 1) downto 0) := "0"; signal rddackreg_66_23_next: unsigned((1 - 1) downto 0); signal rddackreg_66_23: unsigned((1 - 1) downto 0) := "0"; signal wrdackreg_70_23_next: unsigned((1 - 1) downto 0); signal wrdackreg_70_23: unsigned((1 - 1) downto 0) := "0"; signal rddbusreg_84_23_next: unsigned((32 - 1) downto 0); signal rddbusreg_84_23: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000"; signal bankaddr_20_1_slice: unsigned((2 - 1) downto 0); signal linearaddr_21_1_slice: unsigned((8 - 1) downto 0); signal addrpref_in_32_1_slice: unsigned((20 - 1) downto 0); signal rel_33_4: boolean; signal ps1_join_33_1: boolean; signal ps_42_1_bit: boolean; signal bitnot_49_49: boolean; signal bitnot_49_73: boolean; signal bit_49_49: boolean; signal addrack_49_1_convert: unsigned((1 - 1) downto 0); signal bit_55_43: unsigned((1 - 1) downto 0); signal bitnot_72_35: unsigned((1 - 1) downto 0); signal wrdackreg_72_1_bit: unsigned((1 - 1) downto 0); signal rdsel_76_1_bit: unsigned((1 - 1) downto 0); signal rel_78_4: boolean; signal rddbus1_join_78_1: unsigned((32 - 1) downto 0); signal plbwrdbusreg_97_1_slice: unsigned((32 - 1) downto 0); signal plbrstreg_12_24_next_x_000000: boolean; signal plbpavalidreg_14_28_next_x_000000: boolean; begin plbrst_1_110 <= std_logic_vector_to_unsigned(plbrst); plbabus_1_118 <= std_logic_vector_to_unsigned(plbabus); plbpavalid_1_127 <= std_logic_vector_to_unsigned(plbpavalid); plbrnw_1_139 <= std_logic_vector_to_unsigned(plbrnw); plbwrdbus_1_147 <= std_logic_vector_to_unsigned(plbwrdbus); rddata_1_158 <= std_logic_vector_to_unsigned(rddata); addrpref_1_166 <= std_logic_vector_to_unsigned(addrpref); proc_plbrstreg_12_24: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then plbrstreg_12_24 <= plbrstreg_12_24_next; end if; end if; end process proc_plbrstreg_12_24; proc_plbabusreg_13_25: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then plbabusreg_13_25 <= plbabusreg_13_25_next; end if; end if; end process proc_plbabusreg_13_25; proc_plbpavalidreg_14_28: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then plbpavalidreg_14_28 <= plbpavalidreg_14_28_next; end if; end if; end process proc_plbpavalidreg_14_28; proc_plbrnwreg_15_24: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then plbrnwreg_15_24 <= plbrnwreg_15_24_next; end if; end if; end process proc_plbrnwreg_15_24; proc_plbwrdbusreg_16_27: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then plbwrdbusreg_16_27 <= plbwrdbusreg_16_27_next; end if; end if; end process proc_plbwrdbusreg_16_27; proc_avalidreg_28_23: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then avalidreg_28_23 <= avalidreg_28_23_next; end if; end if; end process proc_avalidreg_28_23; proc_ps1reg_39_20: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then ps1reg_39_20 <= ps1reg_39_20_next; end if; end if; end process proc_ps1reg_39_20; proc_psreg_47_19: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then psreg_47_19 <= psreg_47_19_next; end if; end if; end process proc_psreg_47_19; rdcompdelay_58_25_back <= rdcompdelay_58_25(2); proc_rdcompdelay_58_25: process (clk) is variable i: integer; begin if (clk'event and (clk = '1')) then if ((ce = '1') and (rdcompdelay_58_25_push_front_pop_back_en = '1')) then for i in 2 downto 1 loop rdcompdelay_58_25(i) <= rdcompdelay_58_25(i-1); end loop; rdcompdelay_58_25(0) <= rdcompdelay_58_25_front_din; end if; end if; end process proc_rdcompdelay_58_25; proc_rdcompreg_62_23: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then rdcompreg_62_23 <= rdcompreg_62_23_next; end if; end if; end process proc_rdcompreg_62_23; proc_rddackreg_66_23: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then rddackreg_66_23 <= rddackreg_66_23_next; end if; end if; end process proc_rddackreg_66_23; proc_wrdackreg_70_23: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then wrdackreg_70_23 <= wrdackreg_70_23_next; end if; end if; end process proc_wrdackreg_70_23; proc_rddbusreg_84_23: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then rddbusreg_84_23 <= rddbusreg_84_23_next; end if; end if; end process proc_rddbusreg_84_23; bankaddr_20_1_slice <= u2u_slice(plbabusreg_13_25, 11, 10); linearaddr_21_1_slice <= u2u_slice(plbabusreg_13_25, 9, 2); addrpref_in_32_1_slice <= u2u_slice(plbabusreg_13_25, 31, 12); rel_33_4 <= addrpref_in_32_1_slice = addrpref_1_166; proc_if_33_1: process (rel_33_4) is begin if rel_33_4 then ps1_join_33_1 <= true; else ps1_join_33_1 <= false; end if; end process proc_if_33_1; ps_42_1_bit <= ((boolean_to_vector(ps1_join_33_1) and boolean_to_vector(plbpavalidreg_14_28)) = "1"); bitnot_49_49 <= ((not boolean_to_vector(plbrstreg_12_24)) = "1"); bitnot_49_73 <= ((not boolean_to_vector(psreg_47_19)) = "1"); bit_49_49 <= ((boolean_to_vector(bitnot_49_49) and boolean_to_vector(ps_42_1_bit) and boolean_to_vector(bitnot_49_73)) = "1"); addrack_49_1_convert <= u2u_cast(std_logic_vector_to_unsigned(boolean_to_vector(bit_49_49)), 0, 1, 0); bit_55_43 <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(addrack_49_1_convert) and unsigned_to_std_logic_vector(plbrnwreg_15_24)); bitnot_72_35 <= std_logic_vector_to_unsigned(not unsigned_to_std_logic_vector(plbrnwreg_15_24)); wrdackreg_72_1_bit <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(addrack_49_1_convert) and unsigned_to_std_logic_vector(bitnot_72_35)); rdsel_76_1_bit <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(rdcompdelay_58_25_back) or unsigned_to_std_logic_vector(rdcompreg_62_23)); rel_78_4 <= rdsel_76_1_bit = std_logic_vector_to_unsigned("1"); proc_if_78_1: process (rddata_1_158, rel_78_4) is begin if rel_78_4 then rddbus1_join_78_1 <= rddata_1_158; else rddbus1_join_78_1 <= std_logic_vector_to_unsigned("00000000000000000000000000000000"); end if; end process proc_if_78_1; plbwrdbusreg_97_1_slice <= u2u_slice(plbwrdbus_1_147, 31, 0); plbrstreg_12_24_next_x_000000 <= (plbrst_1_110 /= "0"); plbrstreg_12_24_next <= plbrstreg_12_24_next_x_000000; plbabusreg_13_25_next <= plbabus_1_118; plbpavalidreg_14_28_next_x_000000 <= (plbpavalid_1_127 /= "0"); plbpavalidreg_14_28_next <= plbpavalidreg_14_28_next_x_000000; plbrnwreg_15_24_next <= plbrnw_1_139; plbwrdbusreg_16_27_next <= plbwrdbusreg_97_1_slice; avalidreg_28_23_next <= plbpavalidreg_14_28; ps1reg_39_20_next <= ps1_join_33_1; psreg_47_19_next <= ps_42_1_bit; rdcompdelay_58_25_front_din <= bit_55_43; rdcompdelay_58_25_push_front_pop_back_en <= '1'; rdcompreg_62_23_next <= rdcompdelay_58_25_back; rddackreg_66_23_next <= rdcompreg_62_23; wrdackreg_70_23_next <= wrdackreg_72_1_bit; rddbusreg_84_23_next <= rddbus1_join_78_1; wrdbusreg <= unsigned_to_std_logic_vector(plbwrdbusreg_16_27); addrack <= unsigned_to_std_logic_vector(addrack_49_1_convert); rdcomp <= unsigned_to_std_logic_vector(rdcompreg_62_23); wrdack <= unsigned_to_std_logic_vector(wrdackreg_70_23); bankaddr <= unsigned_to_std_logic_vector(bankaddr_20_1_slice); rnwreg <= unsigned_to_std_logic_vector(plbrnwreg_15_24); rddack <= unsigned_to_std_logic_vector(rddackreg_66_23); rddbus <= unsigned_to_std_logic_vector(rddbusreg_84_23); linearaddr <= unsigned_to_std_logic_vector(linearaddr_21_1_slice); end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity mcode_block_189a35de81 is port ( wrdbus : in std_logic_vector((32 - 1) downto 0); bankaddr : in std_logic_vector((2 - 1) downto 0); linearaddr : in std_logic_vector((8 - 1) downto 0); rnwreg : in std_logic_vector((1 - 1) downto 0); addrack : in std_logic_vector((1 - 1) downto 0); read_bank_out : out std_logic_vector((32 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end mcode_block_189a35de81; architecture behavior of mcode_block_189a35de81 is signal wrdbus_1_39: unsigned((32 - 1) downto 0); signal bankaddr_1_47: unsigned((2 - 1) downto 0); signal linearaddr_1_57: unsigned((8 - 1) downto 0); signal rnwreg_1_69: unsigned((1 - 1) downto 0); signal addrack_1_77: unsigned((1 - 1) downto 0); signal read_bank_out_reg_53_31_next: unsigned((32 - 1) downto 0); signal read_bank_out_reg_53_31: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000"; signal bankaddr_reg_56_26_next: unsigned((2 - 1) downto 0); signal bankaddr_reg_56_26: unsigned((2 - 1) downto 0) := "00"; signal opcode_21_1_concat: unsigned((12 - 1) downto 0); signal rel_58_4: boolean; signal rel_61_8: boolean; signal rel_64_8: boolean; signal rel_67_8: boolean; signal read_bank_out_reg_join_58_1: unsigned((32 - 1) downto 0); begin wrdbus_1_39 <= std_logic_vector_to_unsigned(wrdbus); bankaddr_1_47 <= std_logic_vector_to_unsigned(bankaddr); linearaddr_1_57 <= std_logic_vector_to_unsigned(linearaddr); rnwreg_1_69 <= std_logic_vector_to_unsigned(rnwreg); addrack_1_77 <= std_logic_vector_to_unsigned(addrack); proc_read_bank_out_reg_53_31: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then read_bank_out_reg_53_31 <= read_bank_out_reg_53_31_next; end if; end if; end process proc_read_bank_out_reg_53_31; proc_bankaddr_reg_56_26: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then bankaddr_reg_56_26 <= bankaddr_reg_56_26_next; end if; end if; end process proc_bankaddr_reg_56_26; opcode_21_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(addrack_1_77) & unsigned_to_std_logic_vector(rnwreg_1_69) & unsigned_to_std_logic_vector(bankaddr_1_47) & unsigned_to_std_logic_vector(linearaddr_1_57)); rel_58_4 <= bankaddr_reg_56_26 = std_logic_vector_to_unsigned("00"); rel_61_8 <= bankaddr_reg_56_26 = std_logic_vector_to_unsigned("01"); rel_64_8 <= bankaddr_reg_56_26 = std_logic_vector_to_unsigned("10"); rel_67_8 <= bankaddr_reg_56_26 = std_logic_vector_to_unsigned("11"); proc_if_58_1: process (read_bank_out_reg_53_31, rel_58_4, rel_61_8, rel_64_8, rel_67_8) is begin if rel_58_4 then read_bank_out_reg_join_58_1 <= std_logic_vector_to_unsigned("00000000000000000000000000000000"); elsif rel_61_8 then read_bank_out_reg_join_58_1 <= std_logic_vector_to_unsigned("00000000000000000000000000000000"); elsif rel_64_8 then read_bank_out_reg_join_58_1 <= std_logic_vector_to_unsigned("00000000000000000000000000000000"); elsif rel_67_8 then read_bank_out_reg_join_58_1 <= std_logic_vector_to_unsigned("00000000000000000000000000000000"); else read_bank_out_reg_join_58_1 <= read_bank_out_reg_53_31; end if; end process proc_if_58_1; read_bank_out_reg_53_31_next <= read_bank_out_reg_join_58_1; bankaddr_reg_56_26_next <= bankaddr_1_47; read_bank_out <= unsigned_to_std_logic_vector(read_bank_out_reg_53_31); end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity concat_d0d1b9533e is port ( in0 : in std_logic_vector((8 - 1) downto 0); in1 : in std_logic_vector((8 - 1) downto 0); in2 : in std_logic_vector((8 - 1) downto 0); y : out std_logic_vector((24 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end concat_d0d1b9533e; architecture behavior of concat_d0d1b9533e is signal in0_1_23: unsigned((8 - 1) downto 0); signal in1_1_27: unsigned((8 - 1) downto 0); signal in2_1_31: unsigned((8 - 1) downto 0); signal y_2_1_concat: unsigned((24 - 1) downto 0); begin in0_1_23 <= std_logic_vector_to_unsigned(in0); in1_1_27 <= std_logic_vector_to_unsigned(in1); in2_1_31 <= std_logic_vector_to_unsigned(in2); y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27) & unsigned_to_std_logic_vector(in2_1_31)); y <= unsigned_to_std_logic_vector(y_2_1_concat); end behavior; ------------------------------------------------------------------- -- System Generator version 13.2 VHDL source file. -- -- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity xlregister is generic (d_width : integer := 5; init_value : bit_vector := b"00"); port (d : in std_logic_vector (d_width-1 downto 0); rst : in std_logic_vector(0 downto 0) := "0"; en : in std_logic_vector(0 downto 0) := "1"; ce : in std_logic; clk : in std_logic; q : out std_logic_vector (d_width-1 downto 0)); end xlregister; architecture behavior of xlregister is component synth_reg_w_init generic (width : integer; init_index : integer; init_value : bit_vector; latency : integer); port (i : in std_logic_vector(width-1 downto 0); ce : in std_logic; clr : in std_logic; clk : in std_logic; o : out std_logic_vector(width-1 downto 0)); end component; -- synopsys translate_off signal real_d, real_q : real; -- synopsys translate_on signal internal_clr : std_logic; signal internal_ce : std_logic; begin internal_clr <= rst(0) and ce; internal_ce <= en(0) and ce; synth_reg_inst : synth_reg_w_init generic map (width => d_width, init_index => 2, init_value => init_value, latency => 1) port map (i => d, ce => internal_ce, clr => internal_clr, clk => clk, o => q); end architecture behavior; ------------------------------------------------------------------- -- System Generator version 13.2 VHDL source file. -- -- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use work.conv_pkg.all; entity xlslice is generic ( new_msb : integer := 9; new_lsb : integer := 1; x_width : integer := 16; y_width : integer := 8); port ( x : in std_logic_vector (x_width-1 downto 0); y : out std_logic_vector (y_width-1 downto 0)); end xlslice; architecture behavior of xlslice is begin y <= x(new_msb downto new_lsb); end behavior; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; -- Generated from Simulink block "sg_xsvi_fanout/EDK Processor" entity edk_processor_entity_0cfccb8238 is port ( plb_abus: in std_logic_vector(31 downto 0); plb_ce_1: in std_logic; plb_clk_1: in std_logic; plb_pavalid: in std_logic; plb_rnw: in std_logic; plb_wrdbus: in std_logic_vector(31 downto 0); sg_plb_addrpref: in std_logic_vector(19 downto 0); splb_rst: in std_logic; constant5_x0: out std_logic; plb_decode_x0: out std_logic; plb_decode_x1: out std_logic; plb_decode_x2: out std_logic; plb_decode_x3: out std_logic; plb_decode_x4: out std_logic_vector(31 downto 0) ); end edk_processor_entity_0cfccb8238; architecture structural of edk_processor_entity_0cfccb8238 is signal bankaddr: std_logic_vector(1 downto 0); signal linearaddr: std_logic_vector(7 downto 0); signal plb_abus_net_x0: std_logic_vector(31 downto 0); signal plb_ce_1_sg_x0: std_logic; signal plb_clk_1_sg_x0: std_logic; signal plb_pavalid_net_x0: std_logic; signal plb_rnw_net_x0: std_logic; signal plb_wrdbus_net_x0: std_logic_vector(31 downto 0); signal rddata: std_logic_vector(31 downto 0); signal rnwreg: std_logic; signal sg_plb_addrpref_net_x0: std_logic_vector(19 downto 0); signal sl_addrack_x0: std_logic; signal sl_rdcomp_x0: std_logic; signal sl_rddack_x0: std_logic; signal sl_rddbus_x0: std_logic_vector(31 downto 0); signal sl_wait_x0: std_logic; signal sl_wrdack_x0: std_logic; signal splb_rst_net_x0: std_logic; signal wrdbusreg: std_logic_vector(31 downto 0); begin plb_abus_net_x0 <= plb_abus; plb_ce_1_sg_x0 <= plb_ce_1; plb_clk_1_sg_x0 <= plb_clk_1; plb_pavalid_net_x0 <= plb_pavalid; plb_rnw_net_x0 <= plb_rnw; plb_wrdbus_net_x0 <= plb_wrdbus; sg_plb_addrpref_net_x0 <= sg_plb_addrpref; splb_rst_net_x0 <= splb_rst; constant5_x0 <= sl_wait_x0; plb_decode_x0 <= sl_addrack_x0; plb_decode_x1 <= sl_rdcomp_x0; plb_decode_x2 <= sl_wrdack_x0; plb_decode_x3 <= sl_rddack_x0; plb_decode_x4 <= sl_rddbus_x0; constant5: entity work.constant_963ed6358a port map ( ce => '0', clk => '0', clr => '0', op(0) => sl_wait_x0 ); plb_decode: entity work.mcode_block_f4d0462e0e port map ( addrpref => sg_plb_addrpref_net_x0, ce => plb_ce_1_sg_x0, clk => plb_clk_1_sg_x0, clr => '0', plbabus => plb_abus_net_x0, plbpavalid(0) => plb_pavalid_net_x0, plbrnw(0) => plb_rnw_net_x0, plbrst(0) => splb_rst_net_x0, plbwrdbus => plb_wrdbus_net_x0, rddata => rddata, addrack(0) => sl_addrack_x0, bankaddr => bankaddr, linearaddr => linearaddr, rdcomp(0) => sl_rdcomp_x0, rddack(0) => sl_rddack_x0, rddbus => sl_rddbus_x0, rnwreg(0) => rnwreg, wrdack(0) => sl_wrdack_x0, wrdbusreg => wrdbusreg ); plb_memmap: entity work.mcode_block_189a35de81 port map ( addrack(0) => sl_addrack_x0, bankaddr => bankaddr, ce => plb_ce_1_sg_x0, clk => plb_clk_1_sg_x0, clr => '0', linearaddr => linearaddr, rnwreg(0) => rnwreg, wrdbus => wrdbusreg, read_bank_out => rddata ); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; -- Generated from Simulink block "sg_xsvi_fanout" entity sg_xsvi_fanout is port ( active_video_i: in std_logic; ce_1: in std_logic; clk_1: in std_logic; hblank_i: in std_logic; hsync_i: in std_logic; plb_abus: in std_logic_vector(31 downto 0); plb_ce_1: in std_logic; plb_clk_1: in std_logic; plb_pavalid: in std_logic; plb_rnw: in std_logic; plb_wrdbus: in std_logic_vector(31 downto 0); sg_plb_addrpref: in std_logic_vector(19 downto 0); splb_rst: in std_logic; vblank_i: in std_logic; video_data_i: in std_logic_vector(23 downto 0); vsync_i: in std_logic; active_video_o: out std_logic; hblank_o: out std_logic; hsync_o: out std_logic; sl_addrack: out std_logic; sl_rdcomp: out std_logic; sl_rddack: out std_logic; sl_rddbus: out std_logic_vector(31 downto 0); sl_wait: out std_logic; sl_wrcomp: out std_logic; sl_wrdack: out std_logic; vblank_o: out std_logic; video_data_o: out std_logic_vector(23 downto 0); vsync_o: out std_logic ); end sg_xsvi_fanout; architecture structural of sg_xsvi_fanout is attribute core_generation_info: string; attribute core_generation_info of structural : architecture is "sg_xsvi_fanout,sysgen_core,{clock_period=10.00000000,clocking=Clock_Enables,sample_periods=1.00000000000 1.00000000000,testbench=0,total_blocks=102,xilinx_bit_slice_extractor_block=3,xilinx_bus_concatenator_block=1,xilinx_constant_block_block=1,xilinx_edk_processor_block=1,xilinx_gateway_in_block=12,xilinx_gateway_out_block=13,xilinx_mcode_block_block=2,xilinx_register_block=8,xilinx_system_generator_block=1,}"; signal active_video_i_net: std_logic; signal active_video_o_net: std_logic; signal blue: std_logic_vector(7 downto 0); signal ce_1_sg_x0: std_logic; signal clk_1_sg_x0: std_logic; signal green: std_logic_vector(7 downto 0); signal hblank_i_net: std_logic; signal hblank_o_net: std_logic; signal hsync_i_net: std_logic; signal hsync_o_net: std_logic; signal plb_abus_net: std_logic_vector(31 downto 0); signal plb_ce_1_sg_x1: std_logic; signal plb_clk_1_sg_x1: std_logic; signal plb_pavalid_net: std_logic; signal plb_rnw_net: std_logic; signal plb_wrdbus_net: std_logic_vector(31 downto 0); signal red: std_logic_vector(7 downto 0); signal register5_q_net: std_logic_vector(7 downto 0); signal register6_q_net: std_logic_vector(7 downto 0); signal register7_q_net: std_logic_vector(7 downto 0); signal sg_plb_addrpref_net: std_logic_vector(19 downto 0); signal sl_addrack_net: std_logic; signal sl_rdcomp_net: std_logic; signal sl_rddack_net: std_logic; signal sl_rddbus_net: std_logic_vector(31 downto 0); signal sl_wait_net: std_logic; signal sl_wrdack_x1: std_logic; signal splb_rst_net: std_logic; signal vblank_i_net: std_logic; signal vblank_o_net: std_logic; signal video_data_i_net: std_logic_vector(23 downto 0); signal video_data_o_net: std_logic_vector(23 downto 0); signal vsync_i_net: std_logic; signal vsync_o_net: std_logic; begin active_video_i_net <= active_video_i; ce_1_sg_x0 <= ce_1; clk_1_sg_x0 <= clk_1; hblank_i_net <= hblank_i; hsync_i_net <= hsync_i; plb_abus_net <= plb_abus; plb_ce_1_sg_x1 <= plb_ce_1; plb_clk_1_sg_x1 <= plb_clk_1; plb_pavalid_net <= plb_pavalid; plb_rnw_net <= plb_rnw; plb_wrdbus_net <= plb_wrdbus; sg_plb_addrpref_net <= sg_plb_addrpref; splb_rst_net <= splb_rst; vblank_i_net <= vblank_i; video_data_i_net <= video_data_i; vsync_i_net <= vsync_i; active_video_o <= active_video_o_net; hblank_o <= hblank_o_net; hsync_o <= hsync_o_net; sl_addrack <= sl_addrack_net; sl_rdcomp <= sl_rdcomp_net; sl_rddack <= sl_rddack_net; sl_rddbus <= sl_rddbus_net; sl_wait <= sl_wait_net; sl_wrcomp <= sl_wrdack_x1; sl_wrdack <= sl_wrdack_x1; vblank_o <= vblank_o_net; video_data_o <= video_data_o_net; vsync_o <= vsync_o_net; concat: entity work.concat_d0d1b9533e port map ( ce => '0', clk => '0', clr => '0', in0 => register5_q_net, in1 => register6_q_net, in2 => register7_q_net, y => video_data_o_net ); edk_processor_0cfccb8238: entity work.edk_processor_entity_0cfccb8238 port map ( plb_abus => plb_abus_net, plb_ce_1 => plb_ce_1_sg_x1, plb_clk_1 => plb_clk_1_sg_x1, plb_pavalid => plb_pavalid_net, plb_rnw => plb_rnw_net, plb_wrdbus => plb_wrdbus_net, sg_plb_addrpref => sg_plb_addrpref_net, splb_rst => splb_rst_net, constant5_x0 => sl_wait_net, plb_decode_x0 => sl_addrack_net, plb_decode_x1 => sl_rdcomp_net, plb_decode_x2 => sl_wrdack_x1, plb_decode_x3 => sl_rddack_net, plb_decode_x4 => sl_rddbus_net ); register1: entity work.xlregister generic map ( d_width => 1, init_value => b"0" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d(0) => vsync_i_net, en => "1", rst => "0", q(0) => vsync_o_net ); register2: entity work.xlregister generic map ( d_width => 1, init_value => b"0" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d(0) => hsync_i_net, en => "1", rst => "0", q(0) => hsync_o_net ); register3: entity work.xlregister generic map ( d_width => 1, init_value => b"0" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d(0) => vblank_i_net, en => "1", rst => "0", q(0) => vblank_o_net ); register4: entity work.xlregister generic map ( d_width => 1, init_value => b"0" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d(0) => hblank_i_net, en => "1", rst => "0", q(0) => hblank_o_net ); register5: entity work.xlregister generic map ( d_width => 8, init_value => b"00000000" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d => red, en => "1", rst => "0", q => register5_q_net ); register6: entity work.xlregister generic map ( d_width => 8, init_value => b"00000000" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d => green, en => "1", rst => "0", q => register6_q_net ); register7: entity work.xlregister generic map ( d_width => 8, init_value => b"00000000" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d => blue, en => "1", rst => "0", q => register7_q_net ); register_x0: entity work.xlregister generic map ( d_width => 1, init_value => b"0" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d(0) => active_video_i_net, en => "1", rst => "0", q(0) => active_video_o_net ); slice15downto8: entity work.xlslice generic map ( new_lsb => 8, new_msb => 15, x_width => 24, y_width => 8 ) port map ( x => video_data_i_net, y => green ); slice23downto16: entity work.xlslice generic map ( new_lsb => 16, new_msb => 23, x_width => 24, y_width => 8 ) port map ( x => video_data_i_net, y => red ); slice7downto0: entity work.xlslice generic map ( new_lsb => 0, new_msb => 7, x_width => 24, y_width => 8 ) port map ( x => video_data_i_net, y => blue ); end structural;
gpl-3.0
f46b74cda3df328aaaaf39b2d636b8da
0.572908
3.564384
false
false
false
false
tghaefli/ADD
ISE/FMC/bus.vhd
1
5,154
------------------------------------------------------------------------------- -- Entity: ram -- Author: Waj ------------------------------------------------------------------------------- -- Description: (ECS Uebung 9) -- Data/address/control bus for simple von-Neumann MCU. -- The bus master (CPU) can read/write in every cycle. The bus slaves are -- assumed to have registerd read data output with an address-in to data-out -- latency of 1 cc. The read data muxing from bus slaves to the bus master is -- done combinationally. Thus, at the bus master interface, there results a -- read data latency of 1 cc. ------------------------------------------------------------------------------- -- Note on code portability: ------------------------------------------------------------------------------- -- The address decoding logic as implemented in process P_dec below, shows how -- to write portable code by means of a user-defined enumaration type which is -- used as the index range for a constant array, see mcu_pkg. This allows to -- leave the local code (in process P_dec) unchanged when the number and/or -- base addresses of the bus slaves in the system change. Such changes then -- need only to be made in the global definition package. -- To generate such portable code for the rest of the functionality (e.g. for -- the read data mux) would require to organize all data input vectors in a -- signal array first. This would destroy the portability of the code, since it -- requires manual code adaption when design parameter change. ------------------------------------------------------------------------------- -- Total # of FFs: 3 ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.mcu_pkg.all; entity buss is port(rst : in std_logic; clk : in std_logic; -- CPU bus signals cpu_in : in t_cpu2bus; cpu_out : out t_bus2cpu; -- ROM bus signals rom_in : in t_ros2bus; rom_out : out t_bus2ros; -- RAM bus signals ram_in : in t_rws2bus; ram_out : out t_bus2rws; -- GPIO bus signals gpio_in : in t_rws2bus; gpio_out : out t_bus2rws; -- FMC TOP bus signals fmc_top_in : in t_rws2bus; fmc_top_out : out t_bus2rws ); end buss; architecture rtl of buss is -- currently addressed bus slave signal bus_slave, bus_slave_reg : t_bus_slave; begin ----------------------------------------------------------------------------- -- address decoding ----------------------------------------------------------------------------- -- convey lower address bist from CPU to all bus slaves rom_out.addr <= cpu_in.addr(AWL-1 downto 0); ram_out.addr <= cpu_in.addr(AWL-1 downto 0); gpio_out.addr <= cpu_in.addr(AWL-1 downto 0); fmc_top_out.addr <= cpu_in.addr(AWL-1 downto 0); -- combinational process: -- determine addressed slave by decoding higher address bits ----------------------------------------------------------------------------- P_dec: process(cpu_in) begin bus_slave <= ROM; -- default assignment for k in t_bus_slave loop if cpu_in.addr(AW-1 downto AW-AWH) = HBA(k) then bus_slave <= k; end if; end loop; end process; ----------------------------------------------------------------------------- -- write transfer logic ----------------------------------------------------------------------------- -- convey write data from CPU to all bus slaves -- rom is read-only slave ram_out.data <= cpu_in.data; gpio_out.data <= cpu_in.data; fmc_top_out.data <= cpu_in.data; -- convey write enable from CPU to addressed slave only ram_out.wr_enb <= cpu_in.wr_enb when bus_slave = RAM else '0'; gpio_out.wr_enb <= cpu_in.wr_enb when bus_slave = GPIO else '0'; fmc_top_out.wr_enb <= cpu_in.wr_enb when bus_slave = FMC else '0'; ----------------------------------------------------------------------------- -- read transfer logic ----------------------------------------------------------------------------- -- read data mux with bus_slave_reg select cpu_out.data <= rom_in.data when ROM, ram_in.data when RAM, gpio_in.data when GPIO, fmc_top_in.data when FMC, (others => '-') when others; -- convey read enable from CPU to addressed slave only ram_out.rd_enb <= cpu_in.rd_enb when bus_slave = RAM else '0'; gpio_out.rd_enb <= cpu_in.rd_enb when bus_slave = GPIO else '0'; fmc_top_out.rd_enb <= cpu_in.rd_enb when bus_slave = FMC else '0'; -- sequential process: -- register decode information to compensate read-latency of slaves ----------------------------------------------------------------------------- P_reg: process(rst, clk) begin if rst = '1' then bus_slave_reg <= ROM; elsif rising_edge(clk) then bus_slave_reg <= bus_slave; end if; end process; end rtl;
gpl-3.0
08416778c7c9cf2694ee708baabf38ef
0.497478
4.273632
false
false
false
false
abyrne55/my-little-processor
Adder.vhd
1
670
LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.ALL; LIBRARY STD; USE STD.textio.ALL; USE ieee.numeric_std.ALL; -- 16-bit Adder ENTITY Adder IS PORT ( A, B : IN STD_LOGIC_VECTOR(15 DOWNTO 0); output : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); flag : OUT STD_LOGIC ); END Adder; ARCHITECTURE behavioural OF Adder IS SIGNAL out_temp : INTEGER; BEGIN out_temp <= to_integer(unsigned(A)) + to_integer(unsigned(B)); PROCESS (out_temp) BEGIN IF out_temp <= 65535 THEN flag <= '0'; output <= STD_LOGIC_VECTOR(to_unsigned(out_temp, 16)); ELSE flag <= '1'; output <= "0000000000000000"; END IF; END PROCESS; END behavioural;
mit
a10d841715f6f2843727bdef1d514467
0.677612
2.887931
false
false
false
false
hoglet67/AtomFpga
src/common/AVR8/MemArbAndMux/RAMAdrDcd.vhd
4
1,989
--************************************************************************************************ -- Address decoder -- Version 0.11A -- Designed by Ruslan Lepetenok -- Modified 31.07.2005 --************************************************************************************************ library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use WORK.MemAccessCtrlPack.all; entity RAMAdrDcd is port( ramadr : in std_logic_vector(15 downto 0); ramre : in std_logic; ramwe : in std_logic; -- Memory mapped I/O i/f stb_IO : out std_logic; stb_IOmod : out std_logic_vector(CNumOfSlaves-1 downto 0); -- Data memory i/f ram_we : out std_logic; ram_ce : out std_logic; ram_sel : out std_logic ); end RAMAdrDcd; architecture RTL of RAMAdrDcd is signal ram_sel_int : std_logic; begin stb_IO <= '1' when (ramadr(ramadr'high downto ramadr'high-CMemMappedIOBaseAdr'high) = CMemMappedIOBaseAdr) else '0'; --MMIOAdrDcd:process(ramadr) --begin -- stb_IOmod <= (others => '0'); -- for i in 0 to CNumOfSlaves-1 loop -- if(ramadr(7 downto 4)=i) then -- stb_IOmod(i) <= '1'; -- end if; -- end loop; --end process; -- For the purpose of test only --stb_IOmod(0) <= '1' when ramadr(15 downto 4)=x"017" else '0'; --stb_IOmod(1) <= '1' when ramadr(15 downto 4)=x"018" else '0'; stb_IOmod(0) <= '1' when ramadr(7 downto 4)=x"0" else '0'; stb_IOmod(1) <= '1' when ramadr(7 downto 4)=x"1" else '0'; -- For the purpose of test only -- RAM i/f ram_sel_int <= '1'when (ramadr(ramadr'high downto ramadr'high-CDRAMBaseAdr'high) = CDRAMBaseAdr) else '0'; ram_sel <= ram_sel_int; ram_we <= ram_sel_int and ramwe; ram_ce <= ram_sel_int and (ramwe or ramre); end RTL;
apache-2.0
b9a08c67ce3dba3b9d1be4308f7b5bb5
0.502262
3.162162
false
false
false
false
hoglet67/AtomFpga
src/common/ROM/float_2015.vhd
1
172,738
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity atomfloat is port ( CLK : in std_logic; ADDR : in std_logic_vector(11 downto 0); DATA : out std_logic_vector(7 downto 0) ); end; architecture RTL of atomfloat is signal rom_addr : std_logic_vector(11 downto 0); begin p_addr : process(ADDR) begin rom_addr <= (others => '0'); rom_addr(11 downto 0) <= ADDR; end process; p_rom : process begin wait until rising_edge(CLK); DATA <= (others => '0'); case rom_addr is when x"000" => DATA <= x"AA"; when x"001" => DATA <= x"55"; when x"002" => DATA <= x"0E"; when x"003" => DATA <= x"D1"; when x"004" => DATA <= x"5E"; when x"005" => DATA <= x"D1"; when x"006" => DATA <= x"28"; when x"007" => DATA <= x"D0"; when x"008" => DATA <= x"E4"; when x"009" => DATA <= x"41"; when x"00A" => DATA <= x"43"; when x"00B" => DATA <= x"53"; when x"00C" => DATA <= x"D2"; when x"00D" => DATA <= x"1E"; when x"00E" => DATA <= x"41"; when x"00F" => DATA <= x"53"; when x"010" => DATA <= x"4E"; when x"011" => DATA <= x"D2"; when x"012" => DATA <= x"24"; when x"013" => DATA <= x"41"; when x"014" => DATA <= x"54"; when x"015" => DATA <= x"4E"; when x"016" => DATA <= x"DC"; when x"017" => DATA <= x"64"; when x"018" => DATA <= x"41"; when x"019" => DATA <= x"42"; when x"01A" => DATA <= x"53"; when x"01B" => DATA <= x"D2"; when x"01C" => DATA <= x"15"; when x"01D" => DATA <= x"43"; when x"01E" => DATA <= x"4F"; when x"01F" => DATA <= x"53"; when x"020" => DATA <= x"DC"; when x"021" => DATA <= x"E3"; when x"022" => DATA <= x"45"; when x"023" => DATA <= x"58"; when x"024" => DATA <= x"50"; when x"025" => DATA <= x"DD"; when x"026" => DATA <= x"D4"; when x"027" => DATA <= x"48"; when x"028" => DATA <= x"54"; when x"029" => DATA <= x"4E"; when x"02A" => DATA <= x"DE"; when x"02B" => DATA <= x"72"; when x"02C" => DATA <= x"4C"; when x"02D" => DATA <= x"4F"; when x"02E" => DATA <= x"47"; when x"02F" => DATA <= x"DB"; when x"030" => DATA <= x"B3"; when x"031" => DATA <= x"50"; when x"032" => DATA <= x"49"; when x"033" => DATA <= x"D2"; when x"034" => DATA <= x"C3"; when x"035" => DATA <= x"53"; when x"036" => DATA <= x"49"; when x"037" => DATA <= x"4E"; when x"038" => DATA <= x"DC"; when x"039" => DATA <= x"EE"; when x"03A" => DATA <= x"53"; when x"03B" => DATA <= x"51"; when x"03C" => DATA <= x"52"; when x"03D" => DATA <= x"DB"; when x"03E" => DATA <= x"6F"; when x"03F" => DATA <= x"54"; when x"040" => DATA <= x"41"; when x"041" => DATA <= x"4E"; when x"042" => DATA <= x"DA"; when x"043" => DATA <= x"C4"; when x"044" => DATA <= x"44"; when x"045" => DATA <= x"45"; when x"046" => DATA <= x"47"; when x"047" => DATA <= x"D2"; when x"048" => DATA <= x"73"; when x"049" => DATA <= x"52"; when x"04A" => DATA <= x"41"; when x"04B" => DATA <= x"44"; when x"04C" => DATA <= x"D2"; when x"04D" => DATA <= x"65"; when x"04E" => DATA <= x"53"; when x"04F" => DATA <= x"47"; when x"050" => DATA <= x"4E"; when x"051" => DATA <= x"D2"; when x"052" => DATA <= x"86"; when x"053" => DATA <= x"56"; when x"054" => DATA <= x"41"; when x"055" => DATA <= x"4C"; when x"056" => DATA <= x"D2"; when x"057" => DATA <= x"E0"; when x"058" => DATA <= x"46"; when x"059" => DATA <= x"4C"; when x"05A" => DATA <= x"54"; when x"05B" => DATA <= x"D2"; when x"05C" => DATA <= x"9A"; when x"05D" => DATA <= x"46"; when x"05E" => DATA <= x"47"; when x"05F" => DATA <= x"45"; when x"060" => DATA <= x"54"; when x"061" => DATA <= x"D2"; when x"062" => DATA <= x"CC"; when x"063" => DATA <= x"D2"; when x"064" => DATA <= x"96"; when x"065" => DATA <= x"25"; when x"066" => DATA <= x"D3"; when x"067" => DATA <= x"0B"; when x"068" => DATA <= x"46"; when x"069" => DATA <= x"49"; when x"06A" => DATA <= x"46"; when x"06B" => DATA <= x"D3"; when x"06C" => DATA <= x"A8"; when x"06D" => DATA <= x"46"; when x"06E" => DATA <= x"55"; when x"06F" => DATA <= x"4E"; when x"070" => DATA <= x"54"; when x"071" => DATA <= x"49"; when x"072" => DATA <= x"4C"; when x"073" => DATA <= x"D3"; when x"074" => DATA <= x"AE"; when x"075" => DATA <= x"43"; when x"076" => DATA <= x"4F"; when x"077" => DATA <= x"4C"; when x"078" => DATA <= x"4F"; when x"079" => DATA <= x"55"; when x"07A" => DATA <= x"52"; when x"07B" => DATA <= x"DF"; when x"07C" => DATA <= x"02"; when x"07D" => DATA <= x"46"; when x"07E" => DATA <= x"44"; when x"07F" => DATA <= x"49"; when x"080" => DATA <= x"4D"; when x"081" => DATA <= x"D3"; when x"082" => DATA <= x"D3"; when x"083" => DATA <= x"53"; when x"084" => DATA <= x"54"; when x"085" => DATA <= x"52"; when x"086" => DATA <= x"D3"; when x"087" => DATA <= x"1F"; when x"088" => DATA <= x"46"; when x"089" => DATA <= x"50"; when x"08A" => DATA <= x"52"; when x"08B" => DATA <= x"49"; when x"08C" => DATA <= x"4E"; when x"08D" => DATA <= x"54"; when x"08E" => DATA <= x"D3"; when x"08F" => DATA <= x"31"; when x"090" => DATA <= x"46"; when x"091" => DATA <= x"49"; when x"092" => DATA <= x"4E"; when x"093" => DATA <= x"50"; when x"094" => DATA <= x"55"; when x"095" => DATA <= x"54"; when x"096" => DATA <= x"D3"; when x"097" => DATA <= x"6A"; when x"098" => DATA <= x"46"; when x"099" => DATA <= x"50"; when x"09A" => DATA <= x"55"; when x"09B" => DATA <= x"54"; when x"09C" => DATA <= x"D3"; when x"09D" => DATA <= x"B4"; when x"09E" => DATA <= x"D4"; when x"09F" => DATA <= x"AF"; when x"0A0" => DATA <= x"2B"; when x"0A1" => DATA <= x"D1"; when x"0A2" => DATA <= x"77"; when x"0A3" => DATA <= x"2D"; when x"0A4" => DATA <= x"D1"; when x"0A5" => DATA <= x"83"; when x"0A6" => DATA <= x"FE"; when x"0A7" => DATA <= x"2A"; when x"0A8" => DATA <= x"D1"; when x"0A9" => DATA <= x"8F"; when x"0AA" => DATA <= x"2F"; when x"0AB" => DATA <= x"D1"; when x"0AC" => DATA <= x"9B"; when x"0AD" => DATA <= x"FE"; when x"0AE" => DATA <= x"5E"; when x"0AF" => DATA <= x"D1"; when x"0B0" => DATA <= x"A7"; when x"0B1" => DATA <= x"FE"; when x"0B2" => DATA <= x"2B"; when x"0B3" => DATA <= x"D1"; when x"0B4" => DATA <= x"CB"; when x"0B5" => DATA <= x"2D"; when x"0B6" => DATA <= x"D1"; when x"0B7" => DATA <= x"BC"; when x"0B8" => DATA <= x"D1"; when x"0B9" => DATA <= x"CB"; when x"0BA" => DATA <= x"29"; when x"0BB" => DATA <= x"C2"; when x"0BC" => DATA <= x"78"; when x"0BD" => DATA <= x"FF"; when x"0BE" => DATA <= x"3B"; when x"0BF" => DATA <= x"C5"; when x"0C0" => DATA <= x"4A"; when x"0C1" => DATA <= x"0D"; when x"0C2" => DATA <= x"C5"; when x"0C3" => DATA <= x"4A"; when x"0C4" => DATA <= x"2C"; when x"0C5" => DATA <= x"D3"; when x"0C6" => DATA <= x"31"; when x"0C7" => DATA <= x"D3"; when x"0C8" => DATA <= x"39"; when x"0C9" => DATA <= x"2C"; when x"0CA" => DATA <= x"D3"; when x"0CB" => DATA <= x"6A"; when x"0CC" => DATA <= x"C5"; when x"0CD" => DATA <= x"58"; when x"0CE" => DATA <= x"3D"; when x"0CF" => DATA <= x"D9"; when x"0D0" => DATA <= x"F6"; when x"0D1" => DATA <= x"3C"; when x"0D2" => DATA <= x"3E"; when x"0D3" => DATA <= x"D9"; when x"0D4" => DATA <= x"FE"; when x"0D5" => DATA <= x"3C"; when x"0D6" => DATA <= x"3D"; when x"0D7" => DATA <= x"D9"; when x"0D8" => DATA <= x"FA"; when x"0D9" => DATA <= x"3C"; when x"0DA" => DATA <= x"DA"; when x"0DB" => DATA <= x"02"; when x"0DC" => DATA <= x"3E"; when x"0DD" => DATA <= x"3D"; when x"0DE" => DATA <= x"DA"; when x"0DF" => DATA <= x"06"; when x"0E0" => DATA <= x"3E"; when x"0E1" => DATA <= x"DA"; when x"0E2" => DATA <= x"0A"; when x"0E3" => DATA <= x"FF"; when x"0E4" => DATA <= x"20"; when x"0E5" => DATA <= x"FC"; when x"0E6" => DATA <= x"D0"; when x"0E7" => DATA <= x"A2"; when x"0E8" => DATA <= x"B4"; when x"0E9" => DATA <= x"D0"; when x"0EA" => DATA <= x"20"; when x"0EB" => DATA <= x"18"; when x"0EC" => DATA <= x"66"; when x"0ED" => DATA <= x"73"; when x"0EE" => DATA <= x"A2"; when x"0EF" => DATA <= x"AC"; when x"0F0" => DATA <= x"D0"; when x"0F1" => DATA <= x"19"; when x"0F2" => DATA <= x"20"; when x"0F3" => DATA <= x"5D"; when x"0F4" => DATA <= x"D8"; when x"0F5" => DATA <= x"20"; when x"0F6" => DATA <= x"06"; when x"0F7" => DATA <= x"D1"; when x"0F8" => DATA <= x"A2"; when x"0F9" => DATA <= x"A1"; when x"0FA" => DATA <= x"D0"; when x"0FB" => DATA <= x"0F"; when x"0FC" => DATA <= x"20"; when x"0FD" => DATA <= x"F5"; when x"0FE" => DATA <= x"D0"; when x"0FF" => DATA <= x"A2"; when x"100" => DATA <= x"9A"; when x"101" => DATA <= x"D0"; when x"102" => DATA <= x"08"; when x"103" => DATA <= x"20"; when x"104" => DATA <= x"5D"; when x"105" => DATA <= x"D8"; when x"106" => DATA <= x"20"; when x"107" => DATA <= x"EB"; when x"108" => DATA <= x"D0"; when x"109" => DATA <= x"A2"; when x"10A" => DATA <= x"A8"; when x"10B" => DATA <= x"18"; when x"10C" => DATA <= x"90"; when x"10D" => DATA <= x"05"; when x"10E" => DATA <= x"A2"; when x"10F" => DATA <= x"5F"; when x"110" => DATA <= x"84"; when x"111" => DATA <= x"03"; when x"112" => DATA <= x"38"; when x"113" => DATA <= x"66"; when x"114" => DATA <= x"53"; when x"115" => DATA <= x"A4"; when x"116" => DATA <= x"03"; when x"117" => DATA <= x"88"; when x"118" => DATA <= x"C8"; when x"119" => DATA <= x"B1"; when x"11A" => DATA <= x"05"; when x"11B" => DATA <= x"C9"; when x"11C" => DATA <= x"20"; when x"11D" => DATA <= x"F0"; when x"11E" => DATA <= x"F9"; when x"11F" => DATA <= x"88"; when x"120" => DATA <= x"84"; when x"121" => DATA <= x"52"; when x"122" => DATA <= x"CA"; when x"123" => DATA <= x"A4"; when x"124" => DATA <= x"52"; when x"125" => DATA <= x"E8"; when x"126" => DATA <= x"C8"; when x"127" => DATA <= x"BD"; when x"128" => DATA <= x"06"; when x"129" => DATA <= x"D0"; when x"12A" => DATA <= x"30"; when x"12B" => DATA <= x"1A"; when x"12C" => DATA <= x"D1"; when x"12D" => DATA <= x"05"; when x"12E" => DATA <= x"F0"; when x"12F" => DATA <= x"F5"; when x"130" => DATA <= x"CA"; when x"131" => DATA <= x"E8"; when x"132" => DATA <= x"BD"; when x"133" => DATA <= x"06"; when x"134" => DATA <= x"D0"; when x"135" => DATA <= x"10"; when x"136" => DATA <= x"FA"; when x"137" => DATA <= x"E8"; when x"138" => DATA <= x"24"; when x"139" => DATA <= x"53"; when x"13A" => DATA <= x"10"; when x"13B" => DATA <= x"E7"; when x"13C" => DATA <= x"B1"; when x"13D" => DATA <= x"05"; when x"13E" => DATA <= x"C9"; when x"13F" => DATA <= x"2E"; when x"140" => DATA <= x"D0"; when x"141" => DATA <= x"E1"; when x"142" => DATA <= x"C8"; when x"143" => DATA <= x"CA"; when x"144" => DATA <= x"B0"; when x"145" => DATA <= x"E1"; when x"146" => DATA <= x"C9"; when x"147" => DATA <= x"FE"; when x"148" => DATA <= x"B0"; when x"149" => DATA <= x"11"; when x"14A" => DATA <= x"85"; when x"14B" => DATA <= x"53"; when x"14C" => DATA <= x"BD"; when x"14D" => DATA <= x"07"; when x"14E" => DATA <= x"D0"; when x"14F" => DATA <= x"85"; when x"150" => DATA <= x"52"; when x"151" => DATA <= x"84"; when x"152" => DATA <= x"03"; when x"153" => DATA <= x"A6"; when x"154" => DATA <= x"04"; when x"155" => DATA <= x"6C"; when x"156" => DATA <= x"52"; when x"157" => DATA <= x"00"; when x"158" => DATA <= x"A6"; when x"159" => DATA <= x"04"; when x"15A" => DATA <= x"60"; when x"15B" => DATA <= x"F0"; when x"15C" => DATA <= x"FB"; when x"15D" => DATA <= x"00"; when x"15E" => DATA <= x"84"; when x"15F" => DATA <= x"03"; when x"160" => DATA <= x"20"; when x"161" => DATA <= x"EC"; when x"162" => DATA <= x"D0"; when x"163" => DATA <= x"20"; when x"164" => DATA <= x"9A"; when x"165" => DATA <= x"D8"; when x"166" => DATA <= x"A5"; when x"167" => DATA <= x"5A"; when x"168" => DATA <= x"85"; when x"169" => DATA <= x"60"; when x"16A" => DATA <= x"A5"; when x"16B" => DATA <= x"5B"; when x"16C" => DATA <= x"85"; when x"16D" => DATA <= x"5F"; when x"16E" => DATA <= x"A5"; when x"16F" => DATA <= x"5C"; when x"170" => DATA <= x"85"; when x"171" => DATA <= x"5E"; when x"172" => DATA <= x"A0"; when x"173" => DATA <= x"5D"; when x"174" => DATA <= x"4C"; when x"175" => DATA <= x"9F"; when x"176" => DATA <= x"C9"; when x"177" => DATA <= x"20"; when x"178" => DATA <= x"F2"; when x"179" => DATA <= x"D0"; when x"17A" => DATA <= x"20"; when x"17B" => DATA <= x"70"; when x"17C" => DATA <= x"D8"; when x"17D" => DATA <= x"20"; when x"17E" => DATA <= x"3C"; when x"17F" => DATA <= x"D9"; when x"180" => DATA <= x"4C"; when x"181" => DATA <= x"FF"; when x"182" => DATA <= x"D0"; when x"183" => DATA <= x"20"; when x"184" => DATA <= x"F2"; when x"185" => DATA <= x"D0"; when x"186" => DATA <= x"20"; when x"187" => DATA <= x"70"; when x"188" => DATA <= x"D8"; when x"189" => DATA <= x"20"; when x"18A" => DATA <= x"39"; when x"18B" => DATA <= x"D9"; when x"18C" => DATA <= x"4C"; when x"18D" => DATA <= x"FF"; when x"18E" => DATA <= x"D0"; when x"18F" => DATA <= x"20"; when x"190" => DATA <= x"03"; when x"191" => DATA <= x"D1"; when x"192" => DATA <= x"20"; when x"193" => DATA <= x"70"; when x"194" => DATA <= x"D8"; when x"195" => DATA <= x"20"; when x"196" => DATA <= x"45"; when x"197" => DATA <= x"DA"; when x"198" => DATA <= x"4C"; when x"199" => DATA <= x"F8"; when x"19A" => DATA <= x"D0"; when x"19B" => DATA <= x"20"; when x"19C" => DATA <= x"03"; when x"19D" => DATA <= x"D1"; when x"19E" => DATA <= x"20"; when x"19F" => DATA <= x"70"; when x"1A0" => DATA <= x"D8"; when x"1A1" => DATA <= x"20"; when x"1A2" => DATA <= x"B6"; when x"1A3" => DATA <= x"DA"; when x"1A4" => DATA <= x"4C"; when x"1A5" => DATA <= x"F8"; when x"1A6" => DATA <= x"D0"; when x"1A7" => DATA <= x"20"; when x"1A8" => DATA <= x"B6"; when x"1A9" => DATA <= x"DB"; when x"1AA" => DATA <= x"20"; when x"1AB" => DATA <= x"5D"; when x"1AC" => DATA <= x"D8"; when x"1AD" => DATA <= x"20"; when x"1AE" => DATA <= x"EB"; when x"1AF" => DATA <= x"D0"; when x"1B0" => DATA <= x"20"; when x"1B1" => DATA <= x"70"; when x"1B2" => DATA <= x"D8"; when x"1B3" => DATA <= x"20"; when x"1B4" => DATA <= x"45"; when x"1B5" => DATA <= x"DA"; when x"1B6" => DATA <= x"20"; when x"1B7" => DATA <= x"D7"; when x"1B8" => DATA <= x"DD"; when x"1B9" => DATA <= x"4C"; when x"1BA" => DATA <= x"09"; when x"1BB" => DATA <= x"D1"; when x"1BC" => DATA <= x"20"; when x"1BD" => DATA <= x"CB"; when x"1BE" => DATA <= x"D1"; when x"1BF" => DATA <= x"20"; when x"1C0" => DATA <= x"86"; when x"1C1" => DATA <= x"D6"; when x"1C2" => DATA <= x"F0"; when x"1C3" => DATA <= x"06"; when x"1C4" => DATA <= x"A5"; when x"1C5" => DATA <= x"57"; when x"1C6" => DATA <= x"49"; when x"1C7" => DATA <= x"80"; when x"1C8" => DATA <= x"85"; when x"1C9" => DATA <= x"57"; when x"1CA" => DATA <= x"60"; when x"1CB" => DATA <= x"A4"; when x"1CC" => DATA <= x"03"; when x"1CD" => DATA <= x"88"; when x"1CE" => DATA <= x"C8"; when x"1CF" => DATA <= x"B1"; when x"1D0" => DATA <= x"05"; when x"1D1" => DATA <= x"C9"; when x"1D2" => DATA <= x"20"; when x"1D3" => DATA <= x"F0"; when x"1D4" => DATA <= x"F9"; when x"1D5" => DATA <= x"C9"; when x"1D6" => DATA <= x"25"; when x"1D7" => DATA <= x"D0"; when x"1D8" => DATA <= x"32"; when x"1D9" => DATA <= x"E6"; when x"1DA" => DATA <= x"03"; when x"1DB" => DATA <= x"20"; when x"1DC" => DATA <= x"44"; when x"1DD" => DATA <= x"D4"; when x"1DE" => DATA <= x"90"; when x"1DF" => DATA <= x"2B"; when x"1E0" => DATA <= x"A0"; when x"1E1" => DATA <= x"6F"; when x"1E2" => DATA <= x"20"; when x"1E3" => DATA <= x"CD"; when x"1E4" => DATA <= x"C3"; when x"1E5" => DATA <= x"A0"; when x"1E6" => DATA <= x"04"; when x"1E7" => DATA <= x"A9"; when x"1E8" => DATA <= x"00"; when x"1E9" => DATA <= x"85"; when x"1EA" => DATA <= x"5E"; when x"1EB" => DATA <= x"85"; when x"1EC" => DATA <= x"58"; when x"1ED" => DATA <= x"85"; when x"1EE" => DATA <= x"57"; when x"1EF" => DATA <= x"B1"; when x"1F0" => DATA <= x"6F"; when x"1F1" => DATA <= x"99"; when x"1F2" => DATA <= x"59"; when x"1F3" => DATA <= x"00"; when x"1F4" => DATA <= x"05"; when x"1F5" => DATA <= x"57"; when x"1F6" => DATA <= x"85"; when x"1F7" => DATA <= x"57"; when x"1F8" => DATA <= x"88"; when x"1F9" => DATA <= x"10"; when x"1FA" => DATA <= x"F4"; when x"1FB" => DATA <= x"AA"; when x"1FC" => DATA <= x"F0"; when x"1FD" => DATA <= x"09"; when x"1FE" => DATA <= x"A5"; when x"1FF" => DATA <= x"5A"; when x"200" => DATA <= x"85"; when x"201" => DATA <= x"57"; when x"202" => DATA <= x"09"; when x"203" => DATA <= x"80"; when x"204" => DATA <= x"85"; when x"205" => DATA <= x"5A"; when x"206" => DATA <= x"8A"; when x"207" => DATA <= x"60"; when x"208" => DATA <= x"84"; when x"209" => DATA <= x"03"; when x"20A" => DATA <= x"60"; when x"20B" => DATA <= x"20"; when x"20C" => DATA <= x"A5"; when x"20D" => DATA <= x"D5"; when x"20E" => DATA <= x"B0"; when x"20F" => DATA <= x"F8"; when x"210" => DATA <= x"A2"; when x"211" => DATA <= x"00"; when x"212" => DATA <= x"4C"; when x"213" => DATA <= x"12"; when x"214" => DATA <= x"D1"; when x"215" => DATA <= x"20"; when x"216" => DATA <= x"EB"; when x"217" => DATA <= x"D0"; when x"218" => DATA <= x"20"; when x"219" => DATA <= x"86"; when x"21A" => DATA <= x"D6"; when x"21B" => DATA <= x"30"; when x"21C" => DATA <= x"A7"; when x"21D" => DATA <= x"60"; when x"21E" => DATA <= x"20"; when x"21F" => DATA <= x"24"; when x"220" => DATA <= x"D2"; when x"221" => DATA <= x"4C"; when x"222" => DATA <= x"86"; when x"223" => DATA <= x"DC"; when x"224" => DATA <= x"20"; when x"225" => DATA <= x"EB"; when x"226" => DATA <= x"D0"; when x"227" => DATA <= x"20"; when x"228" => DATA <= x"86"; when x"229" => DATA <= x"D6"; when x"22A" => DATA <= x"10"; when x"22B" => DATA <= x"0A"; when x"22C" => DATA <= x"A9"; when x"22D" => DATA <= x"00"; when x"22E" => DATA <= x"85"; when x"22F" => DATA <= x"57"; when x"230" => DATA <= x"20"; when x"231" => DATA <= x"36"; when x"232" => DATA <= x"D2"; when x"233" => DATA <= x"4C"; when x"234" => DATA <= x"75"; when x"235" => DATA <= x"DC"; when x"236" => DATA <= x"20"; when x"237" => DATA <= x"2C"; when x"238" => DATA <= x"D8"; when x"239" => DATA <= x"20"; when x"23A" => DATA <= x"45"; when x"23B" => DATA <= x"DA"; when x"23C" => DATA <= x"20"; when x"23D" => DATA <= x"31"; when x"23E" => DATA <= x"D8"; when x"23F" => DATA <= x"20"; when x"240" => DATA <= x"8D"; when x"241" => DATA <= x"DE"; when x"242" => DATA <= x"20"; when x"243" => DATA <= x"33"; when x"244" => DATA <= x"D9"; when x"245" => DATA <= x"20"; when x"246" => DATA <= x"72"; when x"247" => DATA <= x"DB"; when x"248" => DATA <= x"20"; when x"249" => DATA <= x"86"; when x"24A" => DATA <= x"D6"; when x"24B" => DATA <= x"F0"; when x"24C" => DATA <= x"12"; when x"24D" => DATA <= x"20"; when x"24E" => DATA <= x"31"; when x"24F" => DATA <= x"D8"; when x"250" => DATA <= x"20"; when x"251" => DATA <= x"A6"; when x"252" => DATA <= x"DB"; when x"253" => DATA <= x"20"; when x"254" => DATA <= x"E5"; when x"255" => DATA <= x"D1"; when x"256" => DATA <= x"20"; when x"257" => DATA <= x"AA"; when x"258" => DATA <= x"DB"; when x"259" => DATA <= x"20"; when x"25A" => DATA <= x"DC"; when x"25B" => DATA <= x"DA"; when x"25C" => DATA <= x"4C"; when x"25D" => DATA <= x"67"; when x"25E" => DATA <= x"DC"; when x"25F" => DATA <= x"20"; when x"260" => DATA <= x"93"; when x"261" => DATA <= x"DD"; when x"262" => DATA <= x"4C"; when x"263" => DATA <= x"E5"; when x"264" => DATA <= x"D1"; when x"265" => DATA <= x"20"; when x"266" => DATA <= x"EB"; when x"267" => DATA <= x"D0"; when x"268" => DATA <= x"A0"; when x"269" => DATA <= x"7C"; when x"26A" => DATA <= x"A9"; when x"26B" => DATA <= x"D2"; when x"26C" => DATA <= x"84"; when x"26D" => DATA <= x"6F"; when x"26E" => DATA <= x"85"; when x"26F" => DATA <= x"70"; when x"270" => DATA <= x"4C"; when x"271" => DATA <= x"45"; when x"272" => DATA <= x"DA"; when x"273" => DATA <= x"20"; when x"274" => DATA <= x"EB"; when x"275" => DATA <= x"D0"; when x"276" => DATA <= x"A0"; when x"277" => DATA <= x"81"; when x"278" => DATA <= x"A9"; when x"279" => DATA <= x"D2"; when x"27A" => DATA <= x"D0"; when x"27B" => DATA <= x"F0"; when x"27C" => DATA <= x"7B"; when x"27D" => DATA <= x"0E"; when x"27E" => DATA <= x"FA"; when x"27F" => DATA <= x"35"; when x"280" => DATA <= x"12"; when x"281" => DATA <= x"86"; when x"282" => DATA <= x"65"; when x"283" => DATA <= x"2E"; when x"284" => DATA <= x"E0"; when x"285" => DATA <= x"D3"; when x"286" => DATA <= x"20"; when x"287" => DATA <= x"EB"; when x"288" => DATA <= x"D0"; when x"289" => DATA <= x"20"; when x"28A" => DATA <= x"86"; when x"28B" => DATA <= x"D6"; when x"28C" => DATA <= x"F0"; when x"28D" => DATA <= x"07"; when x"28E" => DATA <= x"48"; when x"28F" => DATA <= x"20"; when x"290" => DATA <= x"8D"; when x"291" => DATA <= x"DE"; when x"292" => DATA <= x"68"; when x"293" => DATA <= x"85"; when x"294" => DATA <= x"57"; when x"295" => DATA <= x"60"; when x"296" => DATA <= x"24"; when x"297" => DATA <= x"73"; when x"298" => DATA <= x"30"; when x"299" => DATA <= x"26"; when x"29A" => DATA <= x"20"; when x"29B" => DATA <= x"BC"; when x"29C" => DATA <= x"C8"; when x"29D" => DATA <= x"A0"; when x"29E" => DATA <= x"5D"; when x"29F" => DATA <= x"20"; when x"2A0" => DATA <= x"CD"; when x"2A1" => DATA <= x"C3"; when x"2A2" => DATA <= x"85"; when x"2A3" => DATA <= x"5A"; when x"2A4" => DATA <= x"A5"; when x"2A5" => DATA <= x"5F"; when x"2A6" => DATA <= x"85"; when x"2A7" => DATA <= x"5B"; when x"2A8" => DATA <= x"A5"; when x"2A9" => DATA <= x"5E"; when x"2AA" => DATA <= x"85"; when x"2AB" => DATA <= x"5C"; when x"2AC" => DATA <= x"A9"; when x"2AD" => DATA <= x"A0"; when x"2AE" => DATA <= x"85"; when x"2AF" => DATA <= x"59"; when x"2B0" => DATA <= x"A0"; when x"2B1" => DATA <= x"00"; when x"2B2" => DATA <= x"84"; when x"2B3" => DATA <= x"5E"; when x"2B4" => DATA <= x"A5"; when x"2B5" => DATA <= x"5A"; when x"2B6" => DATA <= x"85"; when x"2B7" => DATA <= x"57"; when x"2B8" => DATA <= x"10"; when x"2B9" => DATA <= x"03"; when x"2BA" => DATA <= x"20"; when x"2BB" => DATA <= x"D5"; when x"2BC" => DATA <= x"D8"; when x"2BD" => DATA <= x"4C"; when x"2BE" => DATA <= x"C8"; when x"2BF" => DATA <= x"D7"; when x"2C0" => DATA <= x"4C"; when x"2C1" => DATA <= x"1B"; when x"2C2" => DATA <= x"CA"; when x"2C3" => DATA <= x"20"; when x"2C4" => DATA <= x"93"; when x"2C5" => DATA <= x"DD"; when x"2C6" => DATA <= x"20"; when x"2C7" => DATA <= x"E5"; when x"2C8" => DATA <= x"D1"; when x"2C9" => DATA <= x"E6"; when x"2CA" => DATA <= x"59"; when x"2CB" => DATA <= x"60"; when x"2CC" => DATA <= x"20"; when x"2CD" => DATA <= x"3E"; when x"2CE" => DATA <= x"CF"; when x"2CF" => DATA <= x"A2"; when x"2D0" => DATA <= x"04"; when x"2D1" => DATA <= x"20"; when x"2D2" => DATA <= x"D4"; when x"2D3" => DATA <= x"FF"; when x"2D4" => DATA <= x"9D"; when x"2D5" => DATA <= x"C5"; when x"2D6" => DATA <= x"03"; when x"2D7" => DATA <= x"CA"; when x"2D8" => DATA <= x"10"; when x"2D9" => DATA <= x"F7"; when x"2DA" => DATA <= x"20"; when x"2DB" => DATA <= x"AA"; when x"2DC" => DATA <= x"DB"; when x"2DD" => DATA <= x"4C"; when x"2DE" => DATA <= x"E5"; when x"2DF" => DATA <= x"D1"; when x"2E0" => DATA <= x"20"; when x"2E1" => DATA <= x"B1"; when x"2E2" => DATA <= x"CE"; when x"2E3" => DATA <= x"A0"; when x"2E4" => DATA <= x"00"; when x"2E5" => DATA <= x"20"; when x"2E6" => DATA <= x"04"; when x"2E7" => DATA <= x"D3"; when x"2E8" => DATA <= x"C9"; when x"2E9" => DATA <= x"2B"; when x"2EA" => DATA <= x"F0"; when x"2EB" => DATA <= x"0F"; when x"2EC" => DATA <= x"C9"; when x"2ED" => DATA <= x"2D"; when x"2EE" => DATA <= x"D0"; when x"2EF" => DATA <= x"0E"; when x"2F0" => DATA <= x"20"; when x"2F1" => DATA <= x"03"; when x"2F2" => DATA <= x"D3"; when x"2F3" => DATA <= x"84"; when x"2F4" => DATA <= x"54"; when x"2F5" => DATA <= x"20"; when x"2F6" => DATA <= x"B1"; when x"2F7" => DATA <= x"D5"; when x"2F8" => DATA <= x"4C"; when x"2F9" => DATA <= x"BF"; when x"2FA" => DATA <= x"D1"; when x"2FB" => DATA <= x"20"; when x"2FC" => DATA <= x"03"; when x"2FD" => DATA <= x"D3"; when x"2FE" => DATA <= x"84"; when x"2FF" => DATA <= x"54"; when x"300" => DATA <= x"4C"; when x"301" => DATA <= x"B1"; when x"302" => DATA <= x"D5"; when x"303" => DATA <= x"C8"; when x"304" => DATA <= x"B1"; when x"305" => DATA <= x"52"; when x"306" => DATA <= x"C9"; when x"307" => DATA <= x"20"; when x"308" => DATA <= x"F0"; when x"309" => DATA <= x"F9"; when x"30A" => DATA <= x"60"; when x"30B" => DATA <= x"20"; when x"30C" => DATA <= x"44"; when x"30D" => DATA <= x"D4"; when x"30E" => DATA <= x"90"; when x"30F" => DATA <= x"D4"; when x"310" => DATA <= x"20"; when x"311" => DATA <= x"79"; when x"312" => DATA <= x"C2"; when x"313" => DATA <= x"20"; when x"314" => DATA <= x"FC"; when x"315" => DATA <= x"D0"; when x"316" => DATA <= x"20"; when x"317" => DATA <= x"E4"; when x"318" => DATA <= x"C4"; when x"319" => DATA <= x"20"; when x"31A" => DATA <= x"36"; when x"31B" => DATA <= x"D8"; when x"31C" => DATA <= x"4C"; when x"31D" => DATA <= x"5B"; when x"31E" => DATA <= x"C5"; when x"31F" => DATA <= x"20"; when x"320" => DATA <= x"FC"; when x"321" => DATA <= x"D0"; when x"322" => DATA <= x"20"; when x"323" => DATA <= x"31"; when x"324" => DATA <= x"C2"; when x"325" => DATA <= x"20"; when x"326" => DATA <= x"E1"; when x"327" => DATA <= x"C4"; when x"328" => DATA <= x"20"; when x"329" => DATA <= x"CB"; when x"32A" => DATA <= x"C3"; when x"32B" => DATA <= x"20"; when x"32C" => DATA <= x"D0"; when x"32D" => DATA <= x"D4"; when x"32E" => DATA <= x"4C"; when x"32F" => DATA <= x"5B"; when x"330" => DATA <= x"C5"; when x"331" => DATA <= x"20"; when x"332" => DATA <= x"72"; when x"333" => DATA <= x"C3"; when x"334" => DATA <= x"A2"; when x"335" => DATA <= x"B8"; when x"336" => DATA <= x"4C"; when x"337" => DATA <= x"0B"; when x"338" => DATA <= x"D1"; when x"339" => DATA <= x"20"; when x"33A" => DATA <= x"FC"; when x"33B" => DATA <= x"D0"; when x"33C" => DATA <= x"A9"; when x"33D" => DATA <= x"C5"; when x"33E" => DATA <= x"85"; when x"33F" => DATA <= x"52"; when x"340" => DATA <= x"A9"; when x"341" => DATA <= x"03"; when x"342" => DATA <= x"85"; when x"343" => DATA <= x"53"; when x"344" => DATA <= x"20"; when x"345" => DATA <= x"D0"; when x"346" => DATA <= x"D4"; when x"347" => DATA <= x"C6"; when x"348" => DATA <= x"6F"; when x"349" => DATA <= x"AD"; when x"34A" => DATA <= x"21"; when x"34B" => DATA <= x"03"; when x"34C" => DATA <= x"38"; when x"34D" => DATA <= x"E5"; when x"34E" => DATA <= x"6F"; when x"34F" => DATA <= x"90"; when x"350" => DATA <= x"0B"; when x"351" => DATA <= x"F0"; when x"352" => DATA <= x"09"; when x"353" => DATA <= x"A8"; when x"354" => DATA <= x"A9"; when x"355" => DATA <= x"20"; when x"356" => DATA <= x"20"; when x"357" => DATA <= x"4C"; when x"358" => DATA <= x"CA"; when x"359" => DATA <= x"88"; when x"35A" => DATA <= x"D0"; when x"35B" => DATA <= x"FA"; when x"35C" => DATA <= x"A0"; when x"35D" => DATA <= x"00"; when x"35E" => DATA <= x"B1"; when x"35F" => DATA <= x"52"; when x"360" => DATA <= x"C9"; when x"361" => DATA <= x"0D"; when x"362" => DATA <= x"F0"; when x"363" => DATA <= x"CD"; when x"364" => DATA <= x"20"; when x"365" => DATA <= x"4C"; when x"366" => DATA <= x"CA"; when x"367" => DATA <= x"C8"; when x"368" => DATA <= x"D0"; when x"369" => DATA <= x"F4"; when x"36A" => DATA <= x"20"; when x"36B" => DATA <= x"72"; when x"36C" => DATA <= x"C3"; when x"36D" => DATA <= x"B1"; when x"36E" => DATA <= x"05"; when x"36F" => DATA <= x"C9"; when x"370" => DATA <= x"25"; when x"371" => DATA <= x"D0"; when x"372" => DATA <= x"08"; when x"373" => DATA <= x"C8"; when x"374" => DATA <= x"84"; when x"375" => DATA <= x"03"; when x"376" => DATA <= x"20"; when x"377" => DATA <= x"44"; when x"378" => DATA <= x"D4"; when x"379" => DATA <= x"B0"; when x"37A" => DATA <= x"05"; when x"37B" => DATA <= x"A2"; when x"37C" => DATA <= x"C3"; when x"37D" => DATA <= x"4C"; when x"37E" => DATA <= x"0B"; when x"37F" => DATA <= x"D1"; when x"380" => DATA <= x"20"; when x"381" => DATA <= x"09"; when x"382" => DATA <= x"CD"; when x"383" => DATA <= x"A8"; when x"384" => DATA <= x"A5"; when x"385" => DATA <= x"05"; when x"386" => DATA <= x"48"; when x"387" => DATA <= x"A5"; when x"388" => DATA <= x"06"; when x"389" => DATA <= x"48"; when x"38A" => DATA <= x"A5"; when x"38B" => DATA <= x"03"; when x"38C" => DATA <= x"48"; when x"38D" => DATA <= x"84"; when x"38E" => DATA <= x"03"; when x"38F" => DATA <= x"C8"; when x"390" => DATA <= x"84"; when x"391" => DATA <= x"06"; when x"392" => DATA <= x"A9"; when x"393" => DATA <= x"40"; when x"394" => DATA <= x"85"; when x"395" => DATA <= x"05"; when x"396" => DATA <= x"20"; when x"397" => DATA <= x"FC"; when x"398" => DATA <= x"D0"; when x"399" => DATA <= x"68"; when x"39A" => DATA <= x"85"; when x"39B" => DATA <= x"03"; when x"39C" => DATA <= x"68"; when x"39D" => DATA <= x"85"; when x"39E" => DATA <= x"06"; when x"39F" => DATA <= x"68"; when x"3A0" => DATA <= x"85"; when x"3A1" => DATA <= x"05"; when x"3A2" => DATA <= x"20"; when x"3A3" => DATA <= x"36"; when x"3A4" => DATA <= x"D8"; when x"3A5" => DATA <= x"4C"; when x"3A6" => DATA <= x"7B"; when x"3A7" => DATA <= x"D3"; when x"3A8" => DATA <= x"20"; when x"3A9" => DATA <= x"EB"; when x"3AA" => DATA <= x"D9"; when x"3AB" => DATA <= x"4C"; when x"3AC" => DATA <= x"69"; when x"3AD" => DATA <= x"C5"; when x"3AE" => DATA <= x"20"; when x"3AF" => DATA <= x"EB"; when x"3B0" => DATA <= x"D9"; when x"3B1" => DATA <= x"4C"; when x"3B2" => DATA <= x"D5"; when x"3B3" => DATA <= x"CC"; when x"3B4" => DATA <= x"20"; when x"3B5" => DATA <= x"94"; when x"3B6" => DATA <= x"D4"; when x"3B7" => DATA <= x"20"; when x"3B8" => DATA <= x"FC"; when x"3B9" => DATA <= x"D0"; when x"3BA" => DATA <= x"20"; when x"3BB" => DATA <= x"E4"; when x"3BC" => DATA <= x"C4"; when x"3BD" => DATA <= x"20"; when x"3BE" => DATA <= x"31"; when x"3BF" => DATA <= x"D8"; when x"3C0" => DATA <= x"A6"; when x"3C1" => DATA <= x"04"; when x"3C2" => DATA <= x"20"; when x"3C3" => DATA <= x"41"; when x"3C4" => DATA <= x"CF"; when x"3C5" => DATA <= x"A2"; when x"3C6" => DATA <= x"04"; when x"3C7" => DATA <= x"BD"; when x"3C8" => DATA <= x"C5"; when x"3C9" => DATA <= x"03"; when x"3CA" => DATA <= x"20"; when x"3CB" => DATA <= x"D1"; when x"3CC" => DATA <= x"FF"; when x"3CD" => DATA <= x"CA"; when x"3CE" => DATA <= x"10"; when x"3CF" => DATA <= x"F7"; when x"3D0" => DATA <= x"4C"; when x"3D1" => DATA <= x"5B"; when x"3D2" => DATA <= x"C5"; when x"3D3" => DATA <= x"A5"; when x"3D4" => DATA <= x"01"; when x"3D5" => DATA <= x"05"; when x"3D6" => DATA <= x"02"; when x"3D7" => DATA <= x"F0"; when x"3D8" => DATA <= x"6A"; when x"3D9" => DATA <= x"20"; when x"3DA" => DATA <= x"34"; when x"3DB" => DATA <= x"C4"; when x"3DC" => DATA <= x"B0"; when x"3DD" => DATA <= x"65"; when x"3DE" => DATA <= x"A4"; when x"3DF" => DATA <= x"03"; when x"3E0" => DATA <= x"B1"; when x"3E1" => DATA <= x"05"; when x"3E2" => DATA <= x"C9"; when x"3E3" => DATA <= x"25"; when x"3E4" => DATA <= x"D0"; when x"3E5" => DATA <= x"5D"; when x"3E6" => DATA <= x"C8"; when x"3E7" => DATA <= x"B1"; when x"3E8" => DATA <= x"05"; when x"3E9" => DATA <= x"C8"; when x"3EA" => DATA <= x"D1"; when x"3EB" => DATA <= x"05"; when x"3EC" => DATA <= x"D0"; when x"3ED" => DATA <= x"55"; when x"3EE" => DATA <= x"C9"; when x"3EF" => DATA <= x"5B"; when x"3F0" => DATA <= x"B0"; when x"3F1" => DATA <= x"51"; when x"3F2" => DATA <= x"E9"; when x"3F3" => DATA <= x"3F"; when x"3F4" => DATA <= x"90"; when x"3F5" => DATA <= x"4D"; when x"3F6" => DATA <= x"C8"; when x"3F7" => DATA <= x"84"; when x"3F8" => DATA <= x"03"; when x"3F9" => DATA <= x"48"; when x"3FA" => DATA <= x"20"; when x"3FB" => DATA <= x"8B"; when x"3FC" => DATA <= x"C7"; when x"3FD" => DATA <= x"F6"; when x"3FE" => DATA <= x"15"; when x"3FF" => DATA <= x"D0"; when x"400" => DATA <= x"02"; when x"401" => DATA <= x"F6"; when x"402" => DATA <= x"24"; when x"403" => DATA <= x"20"; when x"404" => DATA <= x"9A"; when x"405" => DATA <= x"D4"; when x"406" => DATA <= x"68"; when x"407" => DATA <= x"A8"; when x"408" => DATA <= x"18"; when x"409" => DATA <= x"A5"; when x"40A" => DATA <= x"23"; when x"40B" => DATA <= x"99"; when x"40C" => DATA <= x"87"; when x"40D" => DATA <= x"28"; when x"40E" => DATA <= x"65"; when x"40F" => DATA <= x"16"; when x"410" => DATA <= x"85"; when x"411" => DATA <= x"23"; when x"412" => DATA <= x"A5"; when x"413" => DATA <= x"24"; when x"414" => DATA <= x"99"; when x"415" => DATA <= x"A2"; when x"416" => DATA <= x"28"; when x"417" => DATA <= x"65"; when x"418" => DATA <= x"25"; when x"419" => DATA <= x"85"; when x"41A" => DATA <= x"24"; when x"41B" => DATA <= x"A0"; when x"41C" => DATA <= x"00"; when x"41D" => DATA <= x"84"; when x"41E" => DATA <= x"04"; when x"41F" => DATA <= x"A9"; when x"420" => DATA <= x"AA"; when x"421" => DATA <= x"91"; when x"422" => DATA <= x"23"; when x"423" => DATA <= x"D1"; when x"424" => DATA <= x"23"; when x"425" => DATA <= x"D0"; when x"426" => DATA <= x"1C"; when x"427" => DATA <= x"4A"; when x"428" => DATA <= x"91"; when x"429" => DATA <= x"23"; when x"42A" => DATA <= x"D1"; when x"42B" => DATA <= x"23"; when x"42C" => DATA <= x"D0"; when x"42D" => DATA <= x"15"; when x"42E" => DATA <= x"20"; when x"42F" => DATA <= x"34"; when x"430" => DATA <= x"C4"; when x"431" => DATA <= x"B0"; when x"432" => DATA <= x"10"; when x"433" => DATA <= x"A4"; when x"434" => DATA <= x"03"; when x"435" => DATA <= x"B1"; when x"436" => DATA <= x"05"; when x"437" => DATA <= x"C9"; when x"438" => DATA <= x"2C"; when x"439" => DATA <= x"D0"; when x"43A" => DATA <= x"05"; when x"43B" => DATA <= x"E6"; when x"43C" => DATA <= x"03"; when x"43D" => DATA <= x"4C"; when x"43E" => DATA <= x"D3"; when x"43F" => DATA <= x"D3"; when x"440" => DATA <= x"4C"; when x"441" => DATA <= x"58"; when x"442" => DATA <= x"C5"; when x"443" => DATA <= x"00"; when x"444" => DATA <= x"20"; when x"445" => DATA <= x"34"; when x"446" => DATA <= x"C4"; when x"447" => DATA <= x"90"; when x"448" => DATA <= x"0E"; when x"449" => DATA <= x"B5"; when x"44A" => DATA <= x"15"; when x"44B" => DATA <= x"0A"; when x"44C" => DATA <= x"0A"; when x"44D" => DATA <= x"75"; when x"44E" => DATA <= x"15"; when x"44F" => DATA <= x"95"; when x"450" => DATA <= x"15"; when x"451" => DATA <= x"A9"; when x"452" => DATA <= x"28"; when x"453" => DATA <= x"95"; when x"454" => DATA <= x"24"; when x"455" => DATA <= x"38"; when x"456" => DATA <= x"60"; when x"457" => DATA <= x"A4"; when x"458" => DATA <= x"03"; when x"459" => DATA <= x"B1"; when x"45A" => DATA <= x"05"; when x"45B" => DATA <= x"C9"; when x"45C" => DATA <= x"21"; when x"45D" => DATA <= x"D0"; when x"45E" => DATA <= x"07"; when x"45F" => DATA <= x"E6"; when x"460" => DATA <= x"03"; when x"461" => DATA <= x"20"; when x"462" => DATA <= x"BC"; when x"463" => DATA <= x"C8"; when x"464" => DATA <= x"38"; when x"465" => DATA <= x"60"; when x"466" => DATA <= x"C8"; when x"467" => DATA <= x"D1"; when x"468" => DATA <= x"05"; when x"469" => DATA <= x"D0"; when x"46A" => DATA <= x"08"; when x"46B" => DATA <= x"C9"; when x"46C" => DATA <= x"5B"; when x"46D" => DATA <= x"B0"; when x"46E" => DATA <= x"04"; when x"46F" => DATA <= x"E9"; when x"470" => DATA <= x"3F"; when x"471" => DATA <= x"B0"; when x"472" => DATA <= x"02"; when x"473" => DATA <= x"18"; when x"474" => DATA <= x"60"; when x"475" => DATA <= x"C8"; when x"476" => DATA <= x"84"; when x"477" => DATA <= x"03"; when x"478" => DATA <= x"48"; when x"479" => DATA <= x"20"; when x"47A" => DATA <= x"BC"; when x"47B" => DATA <= x"C8"; when x"47C" => DATA <= x"20"; when x"47D" => DATA <= x"9A"; when x"47E" => DATA <= x"D4"; when x"47F" => DATA <= x"68"; when x"480" => DATA <= x"A8"; when x"481" => DATA <= x"B0"; when x"482" => DATA <= x"10"; when x"483" => DATA <= x"B9"; when x"484" => DATA <= x"87"; when x"485" => DATA <= x"28"; when x"486" => DATA <= x"75"; when x"487" => DATA <= x"15"; when x"488" => DATA <= x"95"; when x"489" => DATA <= x"15"; when x"48A" => DATA <= x"B9"; when x"48B" => DATA <= x"A2"; when x"48C" => DATA <= x"28"; when x"48D" => DATA <= x"75"; when x"48E" => DATA <= x"24"; when x"48F" => DATA <= x"95"; when x"490" => DATA <= x"24"; when x"491" => DATA <= x"90"; when x"492" => DATA <= x"D1"; when x"493" => DATA <= x"00"; when x"494" => DATA <= x"20"; when x"495" => DATA <= x"BC"; when x"496" => DATA <= x"C8"; when x"497" => DATA <= x"4C"; when x"498" => DATA <= x"31"; when x"499" => DATA <= x"C2"; when x"49A" => DATA <= x"B4"; when x"49B" => DATA <= x"24"; when x"49C" => DATA <= x"B5"; when x"49D" => DATA <= x"15"; when x"49E" => DATA <= x"0A"; when x"49F" => DATA <= x"36"; when x"4A0" => DATA <= x"24"; when x"4A1" => DATA <= x"0A"; when x"4A2" => DATA <= x"36"; when x"4A3" => DATA <= x"24"; when x"4A4" => DATA <= x"18"; when x"4A5" => DATA <= x"75"; when x"4A6" => DATA <= x"15"; when x"4A7" => DATA <= x"95"; when x"4A8" => DATA <= x"15"; when x"4A9" => DATA <= x"98"; when x"4AA" => DATA <= x"75"; when x"4AB" => DATA <= x"24"; when x"4AC" => DATA <= x"95"; when x"4AD" => DATA <= x"24"; when x"4AE" => DATA <= x"60"; when x"4AF" => DATA <= x"AD"; when x"4B0" => DATA <= x"20"; when x"4B1" => DATA <= x"EB"; when x"4B2" => DATA <= x"C9"; when x"4B3" => DATA <= x"40"; when x"4B4" => DATA <= x"F0"; when x"4B5" => DATA <= x"0A"; when x"4B6" => DATA <= x"AD"; when x"4B7" => DATA <= x"01"; when x"4B8" => DATA <= x"A0"; when x"4B9" => DATA <= x"C9"; when x"4BA" => DATA <= x"BF"; when x"4BB" => DATA <= x"D0"; when x"4BC" => DATA <= x"83"; when x"4BD" => DATA <= x"4C"; when x"4BE" => DATA <= x"02"; when x"4BF" => DATA <= x"A0"; when x"4C0" => DATA <= x"4C"; when x"4C1" => DATA <= x"22"; when x"4C2" => DATA <= x"EB"; when x"4C3" => DATA <= x"C9"; when x"4C4" => DATA <= x"3A"; when x"4C5" => DATA <= x"B0"; when x"4C6" => DATA <= x"07"; when x"4C7" => DATA <= x"C9"; when x"4C8" => DATA <= x"30"; when x"4C9" => DATA <= x"90"; when x"4CA" => DATA <= x"02"; when x"4CB" => DATA <= x"E9"; when x"4CC" => DATA <= x"30"; when x"4CD" => DATA <= x"60"; when x"4CE" => DATA <= x"18"; when x"4CF" => DATA <= x"60"; when x"4D0" => DATA <= x"A9"; when x"4D1" => DATA <= x"00"; when x"4D2" => DATA <= x"85"; when x"4D3" => DATA <= x"6F"; when x"4D4" => DATA <= x"20"; when x"4D5" => DATA <= x"86"; when x"4D6" => DATA <= x"D6"; when x"4D7" => DATA <= x"D0"; when x"4D8" => DATA <= x"12"; when x"4D9" => DATA <= x"A9"; when x"4DA" => DATA <= x"30"; when x"4DB" => DATA <= x"20"; when x"4DC" => DATA <= x"8D"; when x"4DD" => DATA <= x"D5"; when x"4DE" => DATA <= x"A9"; when x"4DF" => DATA <= x"2E"; when x"4E0" => DATA <= x"20"; when x"4E1" => DATA <= x"8D"; when x"4E2" => DATA <= x"D5"; when x"4E3" => DATA <= x"A9"; when x"4E4" => DATA <= x"30"; when x"4E5" => DATA <= x"20"; when x"4E6" => DATA <= x"8D"; when x"4E7" => DATA <= x"D5"; when x"4E8" => DATA <= x"4C"; when x"4E9" => DATA <= x"71"; when x"4EA" => DATA <= x"D5"; when x"4EB" => DATA <= x"10"; when x"4EC" => DATA <= x"05"; when x"4ED" => DATA <= x"A9"; when x"4EE" => DATA <= x"2D"; when x"4EF" => DATA <= x"20"; when x"4F0" => DATA <= x"8D"; when x"4F1" => DATA <= x"D5"; when x"4F2" => DATA <= x"A9"; when x"4F3" => DATA <= x"00"; when x"4F4" => DATA <= x"85"; when x"4F5" => DATA <= x"6D"; when x"4F6" => DATA <= x"A5"; when x"4F7" => DATA <= x"59"; when x"4F8" => DATA <= x"C9"; when x"4F9" => DATA <= x"81"; when x"4FA" => DATA <= x"B0"; when x"4FB" => DATA <= x"08"; when x"4FC" => DATA <= x"20"; when x"4FD" => DATA <= x"A0"; when x"4FE" => DATA <= x"D6"; when x"4FF" => DATA <= x"C6"; when x"500" => DATA <= x"6D"; when x"501" => DATA <= x"4C"; when x"502" => DATA <= x"F6"; when x"503" => DATA <= x"D4"; when x"504" => DATA <= x"C9"; when x"505" => DATA <= x"84"; when x"506" => DATA <= x"90"; when x"507" => DATA <= x"10"; when x"508" => DATA <= x"D0"; when x"509" => DATA <= x"06"; when x"50A" => DATA <= x"A5"; when x"50B" => DATA <= x"5A"; when x"50C" => DATA <= x"C9"; when x"50D" => DATA <= x"A0"; when x"50E" => DATA <= x"90"; when x"50F" => DATA <= x"08"; when x"510" => DATA <= x"20"; when x"511" => DATA <= x"1B"; when x"512" => DATA <= x"D7"; when x"513" => DATA <= x"E6"; when x"514" => DATA <= x"6D"; when x"515" => DATA <= x"4C"; when x"516" => DATA <= x"F6"; when x"517" => DATA <= x"D4"; when x"518" => DATA <= x"A5"; when x"519" => DATA <= x"59"; when x"51A" => DATA <= x"C9"; when x"51B" => DATA <= x"84"; when x"51C" => DATA <= x"B0"; when x"51D" => DATA <= x"07"; when x"51E" => DATA <= x"20"; when x"51F" => DATA <= x"D8"; when x"520" => DATA <= x"D6"; when x"521" => DATA <= x"E6"; when x"522" => DATA <= x"59"; when x"523" => DATA <= x"D0"; when x"524" => DATA <= x"F3"; when x"525" => DATA <= x"38"; when x"526" => DATA <= x"A9"; when x"527" => DATA <= x"FF"; when x"528" => DATA <= x"20"; when x"529" => DATA <= x"36"; when x"52A" => DATA <= x"D6"; when x"52B" => DATA <= x"A5"; when x"52C" => DATA <= x"5A"; when x"52D" => DATA <= x"C9"; when x"52E" => DATA <= x"A0"; when x"52F" => DATA <= x"B0"; when x"530" => DATA <= x"DF"; when x"531" => DATA <= x"A9"; when x"532" => DATA <= x"01"; when x"533" => DATA <= x"A4"; when x"534" => DATA <= x"6D"; when x"535" => DATA <= x"30"; when x"536" => DATA <= x"0A"; when x"537" => DATA <= x"C0"; when x"538" => DATA <= x"08"; when x"539" => DATA <= x"B0"; when x"53A" => DATA <= x"06"; when x"53B" => DATA <= x"C8"; when x"53C" => DATA <= x"A9"; when x"53D" => DATA <= x"00"; when x"53E" => DATA <= x"85"; when x"53F" => DATA <= x"6D"; when x"540" => DATA <= x"98"; when x"541" => DATA <= x"85"; when x"542" => DATA <= x"70"; when x"543" => DATA <= x"A2"; when x"544" => DATA <= x"09"; when x"545" => DATA <= x"86"; when x"546" => DATA <= x"54"; when x"547" => DATA <= x"20"; when x"548" => DATA <= x"75"; when x"549" => DATA <= x"D5"; when x"54A" => DATA <= x"C6"; when x"54B" => DATA <= x"70"; when x"54C" => DATA <= x"D0"; when x"54D" => DATA <= x"05"; when x"54E" => DATA <= x"A9"; when x"54F" => DATA <= x"2E"; when x"550" => DATA <= x"20"; when x"551" => DATA <= x"8D"; when x"552" => DATA <= x"D5"; when x"553" => DATA <= x"C6"; when x"554" => DATA <= x"54"; when x"555" => DATA <= x"D0"; when x"556" => DATA <= x"F0"; when x"557" => DATA <= x"A5"; when x"558" => DATA <= x"6D"; when x"559" => DATA <= x"F0"; when x"55A" => DATA <= x"16"; when x"55B" => DATA <= x"A9"; when x"55C" => DATA <= x"45"; when x"55D" => DATA <= x"20"; when x"55E" => DATA <= x"8D"; when x"55F" => DATA <= x"D5"; when x"560" => DATA <= x"A5"; when x"561" => DATA <= x"6D"; when x"562" => DATA <= x"10"; when x"563" => DATA <= x"0A"; when x"564" => DATA <= x"A9"; when x"565" => DATA <= x"2D"; when x"566" => DATA <= x"20"; when x"567" => DATA <= x"8D"; when x"568" => DATA <= x"D5"; when x"569" => DATA <= x"38"; when x"56A" => DATA <= x"A9"; when x"56B" => DATA <= x"00"; when x"56C" => DATA <= x"E5"; when x"56D" => DATA <= x"6D"; when x"56E" => DATA <= x"20"; when x"56F" => DATA <= x"87"; when x"570" => DATA <= x"D5"; when x"571" => DATA <= x"A9"; when x"572" => DATA <= x"0D"; when x"573" => DATA <= x"D0"; when x"574" => DATA <= x"18"; when x"575" => DATA <= x"A5"; when x"576" => DATA <= x"5A"; when x"577" => DATA <= x"4A"; when x"578" => DATA <= x"4A"; when x"579" => DATA <= x"4A"; when x"57A" => DATA <= x"4A"; when x"57B" => DATA <= x"20"; when x"57C" => DATA <= x"8B"; when x"57D" => DATA <= x"D5"; when x"57E" => DATA <= x"A5"; when x"57F" => DATA <= x"5A"; when x"580" => DATA <= x"29"; when x"581" => DATA <= x"0F"; when x"582" => DATA <= x"85"; when x"583" => DATA <= x"5A"; when x"584" => DATA <= x"4C"; when x"585" => DATA <= x"4E"; when x"586" => DATA <= x"D6"; when x"587" => DATA <= x"C9"; when x"588" => DATA <= x"0A"; when x"589" => DATA <= x"B0"; when x"58A" => DATA <= x"09"; when x"58B" => DATA <= x"09"; when x"58C" => DATA <= x"30"; when x"58D" => DATA <= x"A4"; when x"58E" => DATA <= x"6F"; when x"58F" => DATA <= x"91"; when x"590" => DATA <= x"52"; when x"591" => DATA <= x"E6"; when x"592" => DATA <= x"6F"; when x"593" => DATA <= x"60"; when x"594" => DATA <= x"A2"; when x"595" => DATA <= x"FF"; when x"596" => DATA <= x"E8"; when x"597" => DATA <= x"E9"; when x"598" => DATA <= x"0A"; when x"599" => DATA <= x"B0"; when x"59A" => DATA <= x"FB"; when x"59B" => DATA <= x"69"; when x"59C" => DATA <= x"0A"; when x"59D" => DATA <= x"48"; when x"59E" => DATA <= x"8A"; when x"59F" => DATA <= x"20"; when x"5A0" => DATA <= x"87"; when x"5A1" => DATA <= x"D5"; when x"5A2" => DATA <= x"68"; when x"5A3" => DATA <= x"10"; when x"5A4" => DATA <= x"E6"; when x"5A5" => DATA <= x"A5"; when x"5A6" => DATA <= x"03"; when x"5A7" => DATA <= x"85"; when x"5A8" => DATA <= x"54"; when x"5A9" => DATA <= x"A5"; when x"5AA" => DATA <= x"05"; when x"5AB" => DATA <= x"85"; when x"5AC" => DATA <= x"52"; when x"5AD" => DATA <= x"A5"; when x"5AE" => DATA <= x"06"; when x"5AF" => DATA <= x"85"; when x"5B0" => DATA <= x"53"; when x"5B1" => DATA <= x"20"; when x"5B2" => DATA <= x"A4"; when x"5B3" => DATA <= x"DA"; when x"5B4" => DATA <= x"85"; when x"5B5" => DATA <= x"6C"; when x"5B6" => DATA <= x"85"; when x"5B7" => DATA <= x"6D"; when x"5B8" => DATA <= x"20"; when x"5B9" => DATA <= x"7B"; when x"5BA" => DATA <= x"D6"; when x"5BB" => DATA <= x"C9"; when x"5BC" => DATA <= x"2E"; when x"5BD" => DATA <= x"F0"; when x"5BE" => DATA <= x"0E"; when x"5BF" => DATA <= x"20"; when x"5C0" => DATA <= x"C3"; when x"5C1" => DATA <= x"D4"; when x"5C2" => DATA <= x"90"; when x"5C3" => DATA <= x"71"; when x"5C4" => DATA <= x"85"; when x"5C5" => DATA <= x"5E"; when x"5C6" => DATA <= x"20"; when x"5C7" => DATA <= x"7B"; when x"5C8" => DATA <= x"D6"; when x"5C9" => DATA <= x"C9"; when x"5CA" => DATA <= x"2E"; when x"5CB" => DATA <= x"D0"; when x"5CC" => DATA <= x"09"; when x"5CD" => DATA <= x"A5"; when x"5CE" => DATA <= x"6C"; when x"5CF" => DATA <= x"18"; when x"5D0" => DATA <= x"D0"; when x"5D1" => DATA <= x"3A"; when x"5D2" => DATA <= x"E6"; when x"5D3" => DATA <= x"6C"; when x"5D4" => DATA <= x"D0"; when x"5D5" => DATA <= x"F0"; when x"5D6" => DATA <= x"C9"; when x"5D7" => DATA <= x"45"; when x"5D8" => DATA <= x"F0"; when x"5D9" => DATA <= x"27"; when x"5DA" => DATA <= x"20"; when x"5DB" => DATA <= x"C3"; when x"5DC" => DATA <= x"D4"; when x"5DD" => DATA <= x"90"; when x"5DE" => DATA <= x"2D"; when x"5DF" => DATA <= x"85"; when x"5E0" => DATA <= x"6E"; when x"5E1" => DATA <= x"A5"; when x"5E2" => DATA <= x"5A"; when x"5E3" => DATA <= x"C9"; when x"5E4" => DATA <= x"18"; when x"5E5" => DATA <= x"90"; when x"5E6" => DATA <= x"08"; when x"5E7" => DATA <= x"A5"; when x"5E8" => DATA <= x"6C"; when x"5E9" => DATA <= x"D0"; when x"5EA" => DATA <= x"DB"; when x"5EB" => DATA <= x"E6"; when x"5EC" => DATA <= x"6D"; when x"5ED" => DATA <= x"B0"; when x"5EE" => DATA <= x"D7"; when x"5EF" => DATA <= x"A5"; when x"5F0" => DATA <= x"6C"; when x"5F1" => DATA <= x"F0"; when x"5F2" => DATA <= x"02"; when x"5F3" => DATA <= x"C6"; when x"5F4" => DATA <= x"6D"; when x"5F5" => DATA <= x"20"; when x"5F6" => DATA <= x"4E"; when x"5F7" => DATA <= x"D6"; when x"5F8" => DATA <= x"18"; when x"5F9" => DATA <= x"A5"; when x"5FA" => DATA <= x"6E"; when x"5FB" => DATA <= x"20"; when x"5FC" => DATA <= x"36"; when x"5FD" => DATA <= x"D6"; when x"5FE" => DATA <= x"4C"; when x"5FF" => DATA <= x"C6"; when x"600" => DATA <= x"D5"; when x"601" => DATA <= x"20"; when x"602" => DATA <= x"7B"; when x"603" => DATA <= x"D6"; when x"604" => DATA <= x"20"; when x"605" => DATA <= x"78"; when x"606" => DATA <= x"D7"; when x"607" => DATA <= x"18"; when x"608" => DATA <= x"65"; when x"609" => DATA <= x"6D"; when x"60A" => DATA <= x"85"; when x"60B" => DATA <= x"6D"; when x"60C" => DATA <= x"A9"; when x"60D" => DATA <= x"A8"; when x"60E" => DATA <= x"85"; when x"60F" => DATA <= x"59"; when x"610" => DATA <= x"20"; when x"611" => DATA <= x"86"; when x"612" => DATA <= x"D6"; when x"613" => DATA <= x"F0"; when x"614" => DATA <= x"1C"; when x"615" => DATA <= x"20"; when x"616" => DATA <= x"C8"; when x"617" => DATA <= x"D7"; when x"618" => DATA <= x"A5"; when x"619" => DATA <= x"6D"; when x"61A" => DATA <= x"30"; when x"61B" => DATA <= x"0B"; when x"61C" => DATA <= x"F0"; when x"61D" => DATA <= x"10"; when x"61E" => DATA <= x"20"; when x"61F" => DATA <= x"A0"; when x"620" => DATA <= x"D6"; when x"621" => DATA <= x"C6"; when x"622" => DATA <= x"6D"; when x"623" => DATA <= x"D0"; when x"624" => DATA <= x"F9"; when x"625" => DATA <= x"F0"; when x"626" => DATA <= x"07"; when x"627" => DATA <= x"20"; when x"628" => DATA <= x"1B"; when x"629" => DATA <= x"D7"; when x"62A" => DATA <= x"E6"; when x"62B" => DATA <= x"6D"; when x"62C" => DATA <= x"D0"; when x"62D" => DATA <= x"F9"; when x"62E" => DATA <= x"20"; when x"62F" => DATA <= x"9B"; when x"630" => DATA <= x"DA"; when x"631" => DATA <= x"38"; when x"632" => DATA <= x"A4"; when x"633" => DATA <= x"54"; when x"634" => DATA <= x"88"; when x"635" => DATA <= x"60"; when x"636" => DATA <= x"A2"; when x"637" => DATA <= x"05"; when x"638" => DATA <= x"75"; when x"639" => DATA <= x"59"; when x"63A" => DATA <= x"95"; when x"63B" => DATA <= x"59"; when x"63C" => DATA <= x"A9"; when x"63D" => DATA <= x"00"; when x"63E" => DATA <= x"CA"; when x"63F" => DATA <= x"D0"; when x"640" => DATA <= x"F7"; when x"641" => DATA <= x"60"; when x"642" => DATA <= x"A2"; when x"643" => DATA <= x"05"; when x"644" => DATA <= x"B5"; when x"645" => DATA <= x"59"; when x"646" => DATA <= x"75"; when x"647" => DATA <= x"61"; when x"648" => DATA <= x"95"; when x"649" => DATA <= x"59"; when x"64A" => DATA <= x"CA"; when x"64B" => DATA <= x"D0"; when x"64C" => DATA <= x"F7"; when x"64D" => DATA <= x"60"; when x"64E" => DATA <= x"A2"; when x"64F" => DATA <= x"05"; when x"650" => DATA <= x"A9"; when x"651" => DATA <= x"00"; when x"652" => DATA <= x"85"; when x"653" => DATA <= x"67"; when x"654" => DATA <= x"A9"; when x"655" => DATA <= x"00"; when x"656" => DATA <= x"85"; when x"657" => DATA <= x"68"; when x"658" => DATA <= x"B5"; when x"659" => DATA <= x"59"; when x"65A" => DATA <= x"0A"; when x"65B" => DATA <= x"26"; when x"65C" => DATA <= x"68"; when x"65D" => DATA <= x"0A"; when x"65E" => DATA <= x"26"; when x"65F" => DATA <= x"68"; when x"660" => DATA <= x"18"; when x"661" => DATA <= x"75"; when x"662" => DATA <= x"59"; when x"663" => DATA <= x"90"; when x"664" => DATA <= x"02"; when x"665" => DATA <= x"E6"; when x"666" => DATA <= x"68"; when x"667" => DATA <= x"0A"; when x"668" => DATA <= x"26"; when x"669" => DATA <= x"68"; when x"66A" => DATA <= x"18"; when x"66B" => DATA <= x"65"; when x"66C" => DATA <= x"67"; when x"66D" => DATA <= x"90"; when x"66E" => DATA <= x"02"; when x"66F" => DATA <= x"E6"; when x"670" => DATA <= x"68"; when x"671" => DATA <= x"95"; when x"672" => DATA <= x"59"; when x"673" => DATA <= x"A5"; when x"674" => DATA <= x"68"; when x"675" => DATA <= x"85"; when x"676" => DATA <= x"67"; when x"677" => DATA <= x"CA"; when x"678" => DATA <= x"D0"; when x"679" => DATA <= x"DA"; when x"67A" => DATA <= x"60"; when x"67B" => DATA <= x"84"; when x"67C" => DATA <= x"55"; when x"67D" => DATA <= x"A4"; when x"67E" => DATA <= x"54"; when x"67F" => DATA <= x"B1"; when x"680" => DATA <= x"52"; when x"681" => DATA <= x"A4"; when x"682" => DATA <= x"55"; when x"683" => DATA <= x"E6"; when x"684" => DATA <= x"54"; when x"685" => DATA <= x"60"; when x"686" => DATA <= x"A5"; when x"687" => DATA <= x"5A"; when x"688" => DATA <= x"05"; when x"689" => DATA <= x"5B"; when x"68A" => DATA <= x"05"; when x"68B" => DATA <= x"5C"; when x"68C" => DATA <= x"05"; when x"68D" => DATA <= x"5D"; when x"68E" => DATA <= x"05"; when x"68F" => DATA <= x"5E"; when x"690" => DATA <= x"F0"; when x"691" => DATA <= x"07"; when x"692" => DATA <= x"A5"; when x"693" => DATA <= x"57"; when x"694" => DATA <= x"D0"; when x"695" => DATA <= x"09"; when x"696" => DATA <= x"A9"; when x"697" => DATA <= x"01"; when x"698" => DATA <= x"60"; when x"699" => DATA <= x"85"; when x"69A" => DATA <= x"57"; when x"69B" => DATA <= x"85"; when x"69C" => DATA <= x"59"; when x"69D" => DATA <= x"85"; when x"69E" => DATA <= x"58"; when x"69F" => DATA <= x"60"; when x"6A0" => DATA <= x"18"; when x"6A1" => DATA <= x"A5"; when x"6A2" => DATA <= x"59"; when x"6A3" => DATA <= x"69"; when x"6A4" => DATA <= x"03"; when x"6A5" => DATA <= x"85"; when x"6A6" => DATA <= x"59"; when x"6A7" => DATA <= x"90"; when x"6A8" => DATA <= x"02"; when x"6A9" => DATA <= x"E6"; when x"6AA" => DATA <= x"58"; when x"6AB" => DATA <= x"20"; when x"6AC" => DATA <= x"C3"; when x"6AD" => DATA <= x"D6"; when x"6AE" => DATA <= x"20"; when x"6AF" => DATA <= x"FB"; when x"6B0" => DATA <= x"D6"; when x"6B1" => DATA <= x"20"; when x"6B2" => DATA <= x"FB"; when x"6B3" => DATA <= x"D6"; when x"6B4" => DATA <= x"20"; when x"6B5" => DATA <= x"42"; when x"6B6" => DATA <= x"D6"; when x"6B7" => DATA <= x"90"; when x"6B8" => DATA <= x"09"; when x"6B9" => DATA <= x"20"; when x"6BA" => DATA <= x"D8"; when x"6BB" => DATA <= x"D6"; when x"6BC" => DATA <= x"E6"; when x"6BD" => DATA <= x"59"; when x"6BE" => DATA <= x"D0"; when x"6BF" => DATA <= x"02"; when x"6C0" => DATA <= x"E6"; when x"6C1" => DATA <= x"58"; when x"6C2" => DATA <= x"60"; when x"6C3" => DATA <= x"A2"; when x"6C4" => DATA <= x"08"; when x"6C5" => DATA <= x"B5"; when x"6C6" => DATA <= x"56"; when x"6C7" => DATA <= x"95"; when x"6C8" => DATA <= x"5E"; when x"6C9" => DATA <= x"CA"; when x"6CA" => DATA <= x"D0"; when x"6CB" => DATA <= x"F9"; when x"6CC" => DATA <= x"60"; when x"6CD" => DATA <= x"06"; when x"6CE" => DATA <= x"5E"; when x"6CF" => DATA <= x"26"; when x"6D0" => DATA <= x"5D"; when x"6D1" => DATA <= x"26"; when x"6D2" => DATA <= x"5C"; when x"6D3" => DATA <= x"26"; when x"6D4" => DATA <= x"5B"; when x"6D5" => DATA <= x"26"; when x"6D6" => DATA <= x"5A"; when x"6D7" => DATA <= x"60"; when x"6D8" => DATA <= x"66"; when x"6D9" => DATA <= x"5A"; when x"6DA" => DATA <= x"66"; when x"6DB" => DATA <= x"5B"; when x"6DC" => DATA <= x"66"; when x"6DD" => DATA <= x"5C"; when x"6DE" => DATA <= x"66"; when x"6DF" => DATA <= x"5D"; when x"6E0" => DATA <= x"66"; when x"6E1" => DATA <= x"5E"; when x"6E2" => DATA <= x"60"; when x"6E3" => DATA <= x"A5"; when x"6E4" => DATA <= x"5D"; when x"6E5" => DATA <= x"85"; when x"6E6" => DATA <= x"5E"; when x"6E7" => DATA <= x"A5"; when x"6E8" => DATA <= x"5C"; when x"6E9" => DATA <= x"85"; when x"6EA" => DATA <= x"5D"; when x"6EB" => DATA <= x"A5"; when x"6EC" => DATA <= x"5B"; when x"6ED" => DATA <= x"85"; when x"6EE" => DATA <= x"5C"; when x"6EF" => DATA <= x"A5"; when x"6F0" => DATA <= x"5A"; when x"6F1" => DATA <= x"85"; when x"6F2" => DATA <= x"5B"; when x"6F3" => DATA <= x"A9"; when x"6F4" => DATA <= x"00"; when x"6F5" => DATA <= x"85"; when x"6F6" => DATA <= x"5A"; when x"6F7" => DATA <= x"60"; when x"6F8" => DATA <= x"20"; when x"6F9" => DATA <= x"C3"; when x"6FA" => DATA <= x"D6"; when x"6FB" => DATA <= x"46"; when x"6FC" => DATA <= x"62"; when x"6FD" => DATA <= x"66"; when x"6FE" => DATA <= x"63"; when x"6FF" => DATA <= x"66"; when x"700" => DATA <= x"64"; when x"701" => DATA <= x"66"; when x"702" => DATA <= x"65"; when x"703" => DATA <= x"66"; when x"704" => DATA <= x"66"; when x"705" => DATA <= x"60"; when x"706" => DATA <= x"A5"; when x"707" => DATA <= x"65"; when x"708" => DATA <= x"85"; when x"709" => DATA <= x"66"; when x"70A" => DATA <= x"A5"; when x"70B" => DATA <= x"64"; when x"70C" => DATA <= x"85"; when x"70D" => DATA <= x"65"; when x"70E" => DATA <= x"A5"; when x"70F" => DATA <= x"63"; when x"710" => DATA <= x"85"; when x"711" => DATA <= x"64"; when x"712" => DATA <= x"A5"; when x"713" => DATA <= x"62"; when x"714" => DATA <= x"85"; when x"715" => DATA <= x"63"; when x"716" => DATA <= x"A9"; when x"717" => DATA <= x"00"; when x"718" => DATA <= x"85"; when x"719" => DATA <= x"62"; when x"71A" => DATA <= x"60"; when x"71B" => DATA <= x"38"; when x"71C" => DATA <= x"A5"; when x"71D" => DATA <= x"59"; when x"71E" => DATA <= x"E9"; when x"71F" => DATA <= x"04"; when x"720" => DATA <= x"85"; when x"721" => DATA <= x"59"; when x"722" => DATA <= x"B0"; when x"723" => DATA <= x"02"; when x"724" => DATA <= x"C6"; when x"725" => DATA <= x"58"; when x"726" => DATA <= x"20"; when x"727" => DATA <= x"F8"; when x"728" => DATA <= x"D6"; when x"729" => DATA <= x"20"; when x"72A" => DATA <= x"B4"; when x"72B" => DATA <= x"D6"; when x"72C" => DATA <= x"20"; when x"72D" => DATA <= x"F8"; when x"72E" => DATA <= x"D6"; when x"72F" => DATA <= x"20"; when x"730" => DATA <= x"FB"; when x"731" => DATA <= x"D6"; when x"732" => DATA <= x"20"; when x"733" => DATA <= x"FB"; when x"734" => DATA <= x"D6"; when x"735" => DATA <= x"20"; when x"736" => DATA <= x"FB"; when x"737" => DATA <= x"D6"; when x"738" => DATA <= x"20"; when x"739" => DATA <= x"B4"; when x"73A" => DATA <= x"D6"; when x"73B" => DATA <= x"A9"; when x"73C" => DATA <= x"00"; when x"73D" => DATA <= x"85"; when x"73E" => DATA <= x"62"; when x"73F" => DATA <= x"A5"; when x"740" => DATA <= x"5A"; when x"741" => DATA <= x"85"; when x"742" => DATA <= x"63"; when x"743" => DATA <= x"A5"; when x"744" => DATA <= x"5B"; when x"745" => DATA <= x"85"; when x"746" => DATA <= x"64"; when x"747" => DATA <= x"A5"; when x"748" => DATA <= x"5C"; when x"749" => DATA <= x"85"; when x"74A" => DATA <= x"65"; when x"74B" => DATA <= x"A5"; when x"74C" => DATA <= x"5D"; when x"74D" => DATA <= x"85"; when x"74E" => DATA <= x"66"; when x"74F" => DATA <= x"A5"; when x"750" => DATA <= x"5E"; when x"751" => DATA <= x"2A"; when x"752" => DATA <= x"20"; when x"753" => DATA <= x"B4"; when x"754" => DATA <= x"D6"; when x"755" => DATA <= x"A9"; when x"756" => DATA <= x"00"; when x"757" => DATA <= x"85"; when x"758" => DATA <= x"62"; when x"759" => DATA <= x"85"; when x"75A" => DATA <= x"63"; when x"75B" => DATA <= x"A5"; when x"75C" => DATA <= x"5A"; when x"75D" => DATA <= x"85"; when x"75E" => DATA <= x"64"; when x"75F" => DATA <= x"A5"; when x"760" => DATA <= x"5B"; when x"761" => DATA <= x"85"; when x"762" => DATA <= x"65"; when x"763" => DATA <= x"A5"; when x"764" => DATA <= x"5C"; when x"765" => DATA <= x"85"; when x"766" => DATA <= x"66"; when x"767" => DATA <= x"A5"; when x"768" => DATA <= x"5D"; when x"769" => DATA <= x"2A"; when x"76A" => DATA <= x"20"; when x"76B" => DATA <= x"B4"; when x"76C" => DATA <= x"D6"; when x"76D" => DATA <= x"A5"; when x"76E" => DATA <= x"5B"; when x"76F" => DATA <= x"2A"; when x"770" => DATA <= x"A5"; when x"771" => DATA <= x"5A"; when x"772" => DATA <= x"20"; when x"773" => DATA <= x"36"; when x"774" => DATA <= x"D6"; when x"775" => DATA <= x"4C"; when x"776" => DATA <= x"B7"; when x"777" => DATA <= x"D6"; when x"778" => DATA <= x"A0"; when x"779" => DATA <= x"FF"; when x"77A" => DATA <= x"C9"; when x"77B" => DATA <= x"2B"; when x"77C" => DATA <= x"F0"; when x"77D" => DATA <= x"05"; when x"77E" => DATA <= x"C9"; when x"77F" => DATA <= x"2D"; when x"780" => DATA <= x"D0"; when x"781" => DATA <= x"04"; when x"782" => DATA <= x"C8"; when x"783" => DATA <= x"20"; when x"784" => DATA <= x"7B"; when x"785" => DATA <= x"D6"; when x"786" => DATA <= x"20"; when x"787" => DATA <= x"C3"; when x"788" => DATA <= x"D4"; when x"789" => DATA <= x"90"; when x"78A" => DATA <= x"24"; when x"78B" => DATA <= x"AA"; when x"78C" => DATA <= x"20"; when x"78D" => DATA <= x"7B"; when x"78E" => DATA <= x"D6"; when x"78F" => DATA <= x"20"; when x"790" => DATA <= x"C3"; when x"791" => DATA <= x"D4"; when x"792" => DATA <= x"90"; when x"793" => DATA <= x"10"; when x"794" => DATA <= x"85"; when x"795" => DATA <= x"6E"; when x"796" => DATA <= x"20"; when x"797" => DATA <= x"7B"; when x"798" => DATA <= x"D6"; when x"799" => DATA <= x"8A"; when x"79A" => DATA <= x"85"; when x"79B" => DATA <= x"67"; when x"79C" => DATA <= x"0A"; when x"79D" => DATA <= x"0A"; when x"79E" => DATA <= x"65"; when x"79F" => DATA <= x"67"; when x"7A0" => DATA <= x"0A"; when x"7A1" => DATA <= x"65"; when x"7A2" => DATA <= x"6E"; when x"7A3" => DATA <= x"AA"; when x"7A4" => DATA <= x"98"; when x"7A5" => DATA <= x"D0"; when x"7A6" => DATA <= x"06"; when x"7A7" => DATA <= x"86"; when x"7A8" => DATA <= x"6E"; when x"7A9" => DATA <= x"38"; when x"7AA" => DATA <= x"E5"; when x"7AB" => DATA <= x"6E"; when x"7AC" => DATA <= x"60"; when x"7AD" => DATA <= x"8A"; when x"7AE" => DATA <= x"60"; when x"7AF" => DATA <= x"A9"; when x"7B0" => DATA <= x"00"; when x"7B1" => DATA <= x"60"; when x"7B2" => DATA <= x"48"; when x"7B3" => DATA <= x"20"; when x"7B4" => DATA <= x"A4"; when x"7B5" => DATA <= x"DA"; when x"7B6" => DATA <= x"68"; when x"7B7" => DATA <= x"F0"; when x"7B8" => DATA <= x"F8"; when x"7B9" => DATA <= x"10"; when x"7BA" => DATA <= x"07"; when x"7BB" => DATA <= x"85"; when x"7BC" => DATA <= x"57"; when x"7BD" => DATA <= x"A9"; when x"7BE" => DATA <= x"00"; when x"7BF" => DATA <= x"38"; when x"7C0" => DATA <= x"E5"; when x"7C1" => DATA <= x"57"; when x"7C2" => DATA <= x"85"; when x"7C3" => DATA <= x"5A"; when x"7C4" => DATA <= x"A9"; when x"7C5" => DATA <= x"88"; when x"7C6" => DATA <= x"85"; when x"7C7" => DATA <= x"59"; when x"7C8" => DATA <= x"20"; when x"7C9" => DATA <= x"86"; when x"7CA" => DATA <= x"D6"; when x"7CB" => DATA <= x"F0"; when x"7CC" => DATA <= x"E4"; when x"7CD" => DATA <= x"A5"; when x"7CE" => DATA <= x"5A"; when x"7CF" => DATA <= x"D0"; when x"7D0" => DATA <= x"21"; when x"7D1" => DATA <= x"A5"; when x"7D2" => DATA <= x"5B"; when x"7D3" => DATA <= x"85"; when x"7D4" => DATA <= x"5A"; when x"7D5" => DATA <= x"A5"; when x"7D6" => DATA <= x"5C"; when x"7D7" => DATA <= x"85"; when x"7D8" => DATA <= x"5B"; when x"7D9" => DATA <= x"A5"; when x"7DA" => DATA <= x"5D"; when x"7DB" => DATA <= x"85"; when x"7DC" => DATA <= x"5C"; when x"7DD" => DATA <= x"A5"; when x"7DE" => DATA <= x"5E"; when x"7DF" => DATA <= x"85"; when x"7E0" => DATA <= x"5D"; when x"7E1" => DATA <= x"A9"; when x"7E2" => DATA <= x"00"; when x"7E3" => DATA <= x"85"; when x"7E4" => DATA <= x"5E"; when x"7E5" => DATA <= x"38"; when x"7E6" => DATA <= x"A5"; when x"7E7" => DATA <= x"59"; when x"7E8" => DATA <= x"E9"; when x"7E9" => DATA <= x"08"; when x"7EA" => DATA <= x"85"; when x"7EB" => DATA <= x"59"; when x"7EC" => DATA <= x"B0"; when x"7ED" => DATA <= x"DF"; when x"7EE" => DATA <= x"C6"; when x"7EF" => DATA <= x"58"; when x"7F0" => DATA <= x"90"; when x"7F1" => DATA <= x"DB"; when x"7F2" => DATA <= x"A5"; when x"7F3" => DATA <= x"5A"; when x"7F4" => DATA <= x"30"; when x"7F5" => DATA <= x"BB"; when x"7F6" => DATA <= x"20"; when x"7F7" => DATA <= x"CD"; when x"7F8" => DATA <= x"D6"; when x"7F9" => DATA <= x"A5"; when x"7FA" => DATA <= x"59"; when x"7FB" => DATA <= x"D0"; when x"7FC" => DATA <= x"02"; when x"7FD" => DATA <= x"C6"; when x"7FE" => DATA <= x"58"; when x"7FF" => DATA <= x"C6"; when x"800" => DATA <= x"59"; when x"801" => DATA <= x"4C"; when x"802" => DATA <= x"F2"; when x"803" => DATA <= x"D7"; when x"804" => DATA <= x"A0"; when x"805" => DATA <= x"04"; when x"806" => DATA <= x"A9"; when x"807" => DATA <= x"00"; when x"808" => DATA <= x"85"; when x"809" => DATA <= x"66"; when x"80A" => DATA <= x"85"; when x"80B" => DATA <= x"60"; when x"80C" => DATA <= x"85"; when x"80D" => DATA <= x"5F"; when x"80E" => DATA <= x"B1"; when x"80F" => DATA <= x"6F"; when x"810" => DATA <= x"99"; when x"811" => DATA <= x"61"; when x"812" => DATA <= x"00"; when x"813" => DATA <= x"05"; when x"814" => DATA <= x"5F"; when x"815" => DATA <= x"85"; when x"816" => DATA <= x"5F"; when x"817" => DATA <= x"88"; when x"818" => DATA <= x"10"; when x"819" => DATA <= x"F4"; when x"81A" => DATA <= x"AA"; when x"81B" => DATA <= x"F0"; when x"81C" => DATA <= x"09"; when x"81D" => DATA <= x"A5"; when x"81E" => DATA <= x"62"; when x"81F" => DATA <= x"85"; when x"820" => DATA <= x"5F"; when x"821" => DATA <= x"09"; when x"822" => DATA <= x"80"; when x"823" => DATA <= x"85"; when x"824" => DATA <= x"62"; when x"825" => DATA <= x"8A"; when x"826" => DATA <= x"60"; when x"827" => DATA <= x"20"; when x"828" => DATA <= x"A2"; when x"829" => DATA <= x"DB"; when x"82A" => DATA <= x"D0"; when x"82B" => DATA <= x"11"; when x"82C" => DATA <= x"20"; when x"82D" => DATA <= x"A6"; when x"82E" => DATA <= x"DB"; when x"82F" => DATA <= x"D0"; when x"830" => DATA <= x"0C"; when x"831" => DATA <= x"20"; when x"832" => DATA <= x"AA"; when x"833" => DATA <= x"DB"; when x"834" => DATA <= x"D0"; when x"835" => DATA <= x"07"; when x"836" => DATA <= x"A6"; when x"837" => DATA <= x"04"; when x"838" => DATA <= x"A0"; when x"839" => DATA <= x"6F"; when x"83A" => DATA <= x"20"; when x"83B" => DATA <= x"CD"; when x"83C" => DATA <= x"C3"; when x"83D" => DATA <= x"A0"; when x"83E" => DATA <= x"00"; when x"83F" => DATA <= x"A5"; when x"840" => DATA <= x"59"; when x"841" => DATA <= x"91"; when x"842" => DATA <= x"6F"; when x"843" => DATA <= x"C8"; when x"844" => DATA <= x"A5"; when x"845" => DATA <= x"57"; when x"846" => DATA <= x"29"; when x"847" => DATA <= x"80"; when x"848" => DATA <= x"85"; when x"849" => DATA <= x"57"; when x"84A" => DATA <= x"A5"; when x"84B" => DATA <= x"5A"; when x"84C" => DATA <= x"29"; when x"84D" => DATA <= x"7F"; when x"84E" => DATA <= x"05"; when x"84F" => DATA <= x"57"; when x"850" => DATA <= x"91"; when x"851" => DATA <= x"6F"; when x"852" => DATA <= x"C8"; when x"853" => DATA <= x"B9"; when x"854" => DATA <= x"59"; when x"855" => DATA <= x"00"; when x"856" => DATA <= x"91"; when x"857" => DATA <= x"6F"; when x"858" => DATA <= x"C0"; when x"859" => DATA <= x"04"; when x"85A" => DATA <= x"D0"; when x"85B" => DATA <= x"F6"; when x"85C" => DATA <= x"60"; when x"85D" => DATA <= x"A0"; when x"85E" => DATA <= x"52"; when x"85F" => DATA <= x"84"; when x"860" => DATA <= x"6F"; when x"861" => DATA <= x"A9"; when x"862" => DATA <= x"00"; when x"863" => DATA <= x"85"; when x"864" => DATA <= x"70"; when x"865" => DATA <= x"20"; when x"866" => DATA <= x"3D"; when x"867" => DATA <= x"D8"; when x"868" => DATA <= x"20"; when x"869" => DATA <= x"D9"; when x"86A" => DATA <= x"C4"; when x"86B" => DATA <= x"A5"; when x"86C" => DATA <= x"56"; when x"86D" => DATA <= x"95"; when x"86E" => DATA <= x"73"; when x"86F" => DATA <= x"60"; when x"870" => DATA <= x"A6"; when x"871" => DATA <= x"04"; when x"872" => DATA <= x"20"; when x"873" => DATA <= x"CB"; when x"874" => DATA <= x"C3"; when x"875" => DATA <= x"B5"; when x"876" => DATA <= x"74"; when x"877" => DATA <= x"85"; when x"878" => DATA <= x"56"; when x"879" => DATA <= x"84"; when x"87A" => DATA <= x"6F"; when x"87B" => DATA <= x"A9"; when x"87C" => DATA <= x"00"; when x"87D" => DATA <= x"85"; when x"87E" => DATA <= x"70"; when x"87F" => DATA <= x"60"; when x"880" => DATA <= x"A5"; when x"881" => DATA <= x"5E"; when x"882" => DATA <= x"C9"; when x"883" => DATA <= x"80"; when x"884" => DATA <= x"90"; when x"885" => DATA <= x"07"; when x"886" => DATA <= x"F0"; when x"887" => DATA <= x"0A"; when x"888" => DATA <= x"A9"; when x"889" => DATA <= x"FF"; when x"88A" => DATA <= x"20"; when x"88B" => DATA <= x"72"; when x"88C" => DATA <= x"D7"; when x"88D" => DATA <= x"A9"; when x"88E" => DATA <= x"00"; when x"88F" => DATA <= x"85"; when x"890" => DATA <= x"5E"; when x"891" => DATA <= x"60"; when x"892" => DATA <= x"A5"; when x"893" => DATA <= x"5D"; when x"894" => DATA <= x"09"; when x"895" => DATA <= x"01"; when x"896" => DATA <= x"85"; when x"897" => DATA <= x"5D"; when x"898" => DATA <= x"D0"; when x"899" => DATA <= x"F3"; when x"89A" => DATA <= x"20"; when x"89B" => DATA <= x"C7"; when x"89C" => DATA <= x"D8"; when x"89D" => DATA <= x"F0"; when x"89E" => DATA <= x"06"; when x"89F" => DATA <= x"A5"; when x"8A0" => DATA <= x"59"; when x"8A1" => DATA <= x"C9"; when x"8A2" => DATA <= x"A0"; when x"8A3" => DATA <= x"B0"; when x"8A4" => DATA <= x"14"; when x"8A5" => DATA <= x"46"; when x"8A6" => DATA <= x"5A"; when x"8A7" => DATA <= x"66"; when x"8A8" => DATA <= x"5B"; when x"8A9" => DATA <= x"66"; when x"8AA" => DATA <= x"5C"; when x"8AB" => DATA <= x"66"; when x"8AC" => DATA <= x"5D"; when x"8AD" => DATA <= x"66"; when x"8AE" => DATA <= x"62"; when x"8AF" => DATA <= x"66"; when x"8B0" => DATA <= x"63"; when x"8B1" => DATA <= x"66"; when x"8B2" => DATA <= x"64"; when x"8B3" => DATA <= x"66"; when x"8B4" => DATA <= x"65"; when x"8B5" => DATA <= x"E6"; when x"8B6" => DATA <= x"59"; when x"8B7" => DATA <= x"D0"; when x"8B8" => DATA <= x"E6"; when x"8B9" => DATA <= x"F0"; when x"8BA" => DATA <= x"16"; when x"8BB" => DATA <= x"A9"; when x"8BC" => DATA <= x"7F"; when x"8BD" => DATA <= x"85"; when x"8BE" => DATA <= x"5A"; when x"8BF" => DATA <= x"A9"; when x"8C0" => DATA <= x"FF"; when x"8C1" => DATA <= x"85"; when x"8C2" => DATA <= x"5B"; when x"8C3" => DATA <= x"85"; when x"8C4" => DATA <= x"5C"; when x"8C5" => DATA <= x"85"; when x"8C6" => DATA <= x"5D"; when x"8C7" => DATA <= x"A2"; when x"8C8" => DATA <= x"08"; when x"8C9" => DATA <= x"A9"; when x"8CA" => DATA <= x"00"; when x"8CB" => DATA <= x"95"; when x"8CC" => DATA <= x"5F"; when x"8CD" => DATA <= x"CA"; when x"8CE" => DATA <= x"D0"; when x"8CF" => DATA <= x"FB"; when x"8D0" => DATA <= x"60"; when x"8D1" => DATA <= x"A5"; when x"8D2" => DATA <= x"57"; when x"8D3" => DATA <= x"10"; when x"8D4" => DATA <= x"0C"; when x"8D5" => DATA <= x"38"; when x"8D6" => DATA <= x"A2"; when x"8D7" => DATA <= x"04"; when x"8D8" => DATA <= x"A9"; when x"8D9" => DATA <= x"00"; when x"8DA" => DATA <= x"F5"; when x"8DB" => DATA <= x"59"; when x"8DC" => DATA <= x"95"; when x"8DD" => DATA <= x"59"; when x"8DE" => DATA <= x"CA"; when x"8DF" => DATA <= x"D0"; when x"8E0" => DATA <= x"F7"; when x"8E1" => DATA <= x"60"; when x"8E2" => DATA <= x"A5"; when x"8E3" => DATA <= x"62"; when x"8E4" => DATA <= x"10"; when x"8E5" => DATA <= x"23"; when x"8E6" => DATA <= x"A2"; when x"8E7" => DATA <= x"04"; when x"8E8" => DATA <= x"A9"; when x"8E9" => DATA <= x"00"; when x"8EA" => DATA <= x"F5"; when x"8EB" => DATA <= x"61"; when x"8EC" => DATA <= x"95"; when x"8ED" => DATA <= x"61"; when x"8EE" => DATA <= x"CA"; when x"8EF" => DATA <= x"D0"; when x"8F0" => DATA <= x"F7"; when x"8F1" => DATA <= x"A5"; when x"8F2" => DATA <= x"57"; when x"8F3" => DATA <= x"49"; when x"8F4" => DATA <= x"80"; when x"8F5" => DATA <= x"85"; when x"8F6" => DATA <= x"57"; when x"8F7" => DATA <= x"10"; when x"8F8" => DATA <= x"11"; when x"8F9" => DATA <= x"E6"; when x"8FA" => DATA <= x"5D"; when x"8FB" => DATA <= x"D0"; when x"8FC" => DATA <= x"0C"; when x"8FD" => DATA <= x"E6"; when x"8FE" => DATA <= x"5C"; when x"8FF" => DATA <= x"D0"; when x"900" => DATA <= x"08"; when x"901" => DATA <= x"E6"; when x"902" => DATA <= x"5B"; when x"903" => DATA <= x"D0"; when x"904" => DATA <= x"04"; when x"905" => DATA <= x"E6"; when x"906" => DATA <= x"5A"; when x"907" => DATA <= x"F0"; when x"908" => DATA <= x"B2"; when x"909" => DATA <= x"60"; when x"90A" => DATA <= x"20"; when x"90B" => DATA <= x"D5"; when x"90C" => DATA <= x"D8"; when x"90D" => DATA <= x"20"; when x"90E" => DATA <= x"F9"; when x"90F" => DATA <= x"D8"; when x"910" => DATA <= x"4C"; when x"911" => DATA <= x"D5"; when x"912" => DATA <= x"D8"; when x"913" => DATA <= x"A2"; when x"914" => DATA <= x"05"; when x"915" => DATA <= x"B5"; when x"916" => DATA <= x"61"; when x"917" => DATA <= x"95"; when x"918" => DATA <= x"59"; when x"919" => DATA <= x"CA"; when x"91A" => DATA <= x"D0"; when x"91B" => DATA <= x"F9"; when x"91C" => DATA <= x"A9"; when x"91D" => DATA <= x"80"; when x"91E" => DATA <= x"85"; when x"91F" => DATA <= x"59"; when x"920" => DATA <= x"4C"; when x"921" => DATA <= x"C8"; when x"922" => DATA <= x"D7"; when x"923" => DATA <= x"20"; when x"924" => DATA <= x"04"; when x"925" => DATA <= x"D8"; when x"926" => DATA <= x"20"; when x"927" => DATA <= x"3D"; when x"928" => DATA <= x"D8"; when x"929" => DATA <= x"A2"; when x"92A" => DATA <= x"08"; when x"92B" => DATA <= x"B5"; when x"92C" => DATA <= x"5E"; when x"92D" => DATA <= x"95"; when x"92E" => DATA <= x"56"; when x"92F" => DATA <= x"CA"; when x"930" => DATA <= x"D0"; when x"931" => DATA <= x"F9"; when x"932" => DATA <= x"60"; when x"933" => DATA <= x"20"; when x"934" => DATA <= x"39"; when x"935" => DATA <= x"D9"; when x"936" => DATA <= x"4C"; when x"937" => DATA <= x"BF"; when x"938" => DATA <= x"D1"; when x"939" => DATA <= x"20"; when x"93A" => DATA <= x"BF"; when x"93B" => DATA <= x"D1"; when x"93C" => DATA <= x"20"; when x"93D" => DATA <= x"04"; when x"93E" => DATA <= x"D8"; when x"93F" => DATA <= x"F0"; when x"940" => DATA <= x"F1"; when x"941" => DATA <= x"20"; when x"942" => DATA <= x"86"; when x"943" => DATA <= x"D6"; when x"944" => DATA <= x"F0"; when x"945" => DATA <= x"E3"; when x"946" => DATA <= x"A5"; when x"947" => DATA <= x"59"; when x"948" => DATA <= x"C5"; when x"949" => DATA <= x"61"; when x"94A" => DATA <= x"F0"; when x"94B" => DATA <= x"26"; when x"94C" => DATA <= x"90"; when x"94D" => DATA <= x"0F"; when x"94E" => DATA <= x"E5"; when x"94F" => DATA <= x"61"; when x"950" => DATA <= x"C9"; when x"951" => DATA <= x"21"; when x"952" => DATA <= x"B0"; when x"953" => DATA <= x"DE"; when x"954" => DATA <= x"AA"; when x"955" => DATA <= x"20"; when x"956" => DATA <= x"FB"; when x"957" => DATA <= x"D6"; when x"958" => DATA <= x"CA"; when x"959" => DATA <= x"D0"; when x"95A" => DATA <= x"FA"; when x"95B" => DATA <= x"F0"; when x"95C" => DATA <= x"15"; when x"95D" => DATA <= x"38"; when x"95E" => DATA <= x"A5"; when x"95F" => DATA <= x"61"; when x"960" => DATA <= x"E5"; when x"961" => DATA <= x"59"; when x"962" => DATA <= x"C9"; when x"963" => DATA <= x"21"; when x"964" => DATA <= x"B0"; when x"965" => DATA <= x"C3"; when x"966" => DATA <= x"AA"; when x"967" => DATA <= x"18"; when x"968" => DATA <= x"20"; when x"969" => DATA <= x"D8"; when x"96A" => DATA <= x"D6"; when x"96B" => DATA <= x"CA"; when x"96C" => DATA <= x"D0"; when x"96D" => DATA <= x"F9"; when x"96E" => DATA <= x"A5"; when x"96F" => DATA <= x"61"; when x"970" => DATA <= x"85"; when x"971" => DATA <= x"59"; when x"972" => DATA <= x"A5"; when x"973" => DATA <= x"57"; when x"974" => DATA <= x"45"; when x"975" => DATA <= x"5F"; when x"976" => DATA <= x"10"; when x"977" => DATA <= x"49"; when x"978" => DATA <= x"A5"; when x"979" => DATA <= x"5A"; when x"97A" => DATA <= x"C5"; when x"97B" => DATA <= x"62"; when x"97C" => DATA <= x"D0"; when x"97D" => DATA <= x"1B"; when x"97E" => DATA <= x"A5"; when x"97F" => DATA <= x"5B"; when x"980" => DATA <= x"C5"; when x"981" => DATA <= x"63"; when x"982" => DATA <= x"D0"; when x"983" => DATA <= x"15"; when x"984" => DATA <= x"A5"; when x"985" => DATA <= x"5C"; when x"986" => DATA <= x"C5"; when x"987" => DATA <= x"64"; when x"988" => DATA <= x"D0"; when x"989" => DATA <= x"0F"; when x"98A" => DATA <= x"A5"; when x"98B" => DATA <= x"5D"; when x"98C" => DATA <= x"C5"; when x"98D" => DATA <= x"65"; when x"98E" => DATA <= x"D0"; when x"98F" => DATA <= x"09"; when x"990" => DATA <= x"A5"; when x"991" => DATA <= x"5E"; when x"992" => DATA <= x"C5"; when x"993" => DATA <= x"66"; when x"994" => DATA <= x"D0"; when x"995" => DATA <= x"03"; when x"996" => DATA <= x"4C"; when x"997" => DATA <= x"A4"; when x"998" => DATA <= x"DA"; when x"999" => DATA <= x"B0"; when x"99A" => DATA <= x"2D"; when x"99B" => DATA <= x"38"; when x"99C" => DATA <= x"A5"; when x"99D" => DATA <= x"66"; when x"99E" => DATA <= x"E5"; when x"99F" => DATA <= x"5E"; when x"9A0" => DATA <= x"85"; when x"9A1" => DATA <= x"5E"; when x"9A2" => DATA <= x"A5"; when x"9A3" => DATA <= x"65"; when x"9A4" => DATA <= x"E5"; when x"9A5" => DATA <= x"5D"; when x"9A6" => DATA <= x"85"; when x"9A7" => DATA <= x"5D"; when x"9A8" => DATA <= x"A5"; when x"9A9" => DATA <= x"64"; when x"9AA" => DATA <= x"E5"; when x"9AB" => DATA <= x"5C"; when x"9AC" => DATA <= x"85"; when x"9AD" => DATA <= x"5C"; when x"9AE" => DATA <= x"A5"; when x"9AF" => DATA <= x"63"; when x"9B0" => DATA <= x"E5"; when x"9B1" => DATA <= x"5B"; when x"9B2" => DATA <= x"85"; when x"9B3" => DATA <= x"5B"; when x"9B4" => DATA <= x"A5"; when x"9B5" => DATA <= x"62"; when x"9B6" => DATA <= x"E5"; when x"9B7" => DATA <= x"5A"; when x"9B8" => DATA <= x"85"; when x"9B9" => DATA <= x"5A"; when x"9BA" => DATA <= x"A5"; when x"9BB" => DATA <= x"5F"; when x"9BC" => DATA <= x"85"; when x"9BD" => DATA <= x"57"; when x"9BE" => DATA <= x"4C"; when x"9BF" => DATA <= x"98"; when x"9C0" => DATA <= x"DA"; when x"9C1" => DATA <= x"18"; when x"9C2" => DATA <= x"20"; when x"9C3" => DATA <= x"B4"; when x"9C4" => DATA <= x"D6"; when x"9C5" => DATA <= x"4C"; when x"9C6" => DATA <= x"9B"; when x"9C7" => DATA <= x"DA"; when x"9C8" => DATA <= x"38"; when x"9C9" => DATA <= x"A5"; when x"9CA" => DATA <= x"5E"; when x"9CB" => DATA <= x"E5"; when x"9CC" => DATA <= x"66"; when x"9CD" => DATA <= x"85"; when x"9CE" => DATA <= x"5E"; when x"9CF" => DATA <= x"A5"; when x"9D0" => DATA <= x"5D"; when x"9D1" => DATA <= x"E5"; when x"9D2" => DATA <= x"65"; when x"9D3" => DATA <= x"85"; when x"9D4" => DATA <= x"5D"; when x"9D5" => DATA <= x"A5"; when x"9D6" => DATA <= x"5C"; when x"9D7" => DATA <= x"E5"; when x"9D8" => DATA <= x"64"; when x"9D9" => DATA <= x"85"; when x"9DA" => DATA <= x"5C"; when x"9DB" => DATA <= x"A5"; when x"9DC" => DATA <= x"5B"; when x"9DD" => DATA <= x"E5"; when x"9DE" => DATA <= x"63"; when x"9DF" => DATA <= x"85"; when x"9E0" => DATA <= x"5B"; when x"9E1" => DATA <= x"A5"; when x"9E2" => DATA <= x"5A"; when x"9E3" => DATA <= x"E5"; when x"9E4" => DATA <= x"62"; when x"9E5" => DATA <= x"85"; when x"9E6" => DATA <= x"5A"; when x"9E7" => DATA <= x"4C"; when x"9E8" => DATA <= x"98"; when x"9E9" => DATA <= x"DA"; when x"9EA" => DATA <= x"00"; when x"9EB" => DATA <= x"20"; when x"9EC" => DATA <= x"FC"; when x"9ED" => DATA <= x"D0"; when x"9EE" => DATA <= x"A9"; when x"9EF" => DATA <= x"C7"; when x"9F0" => DATA <= x"48"; when x"9F1" => DATA <= x"A2"; when x"9F2" => DATA <= x"C8"; when x"9F3" => DATA <= x"4C"; when x"9F4" => DATA <= x"0B"; when x"9F5" => DATA <= x"D1"; when x"9F6" => DATA <= x"A9"; when x"9F7" => DATA <= x"5D"; when x"9F8" => DATA <= x"D0"; when x"9F9" => DATA <= x"12"; when x"9FA" => DATA <= x"A9"; when x"9FB" => DATA <= x"66"; when x"9FC" => DATA <= x"D0"; when x"9FD" => DATA <= x"0E"; when x"9FE" => DATA <= x"A9"; when x"9FF" => DATA <= x"6F"; when x"A00" => DATA <= x"D0"; when x"A01" => DATA <= x"0A"; when x"A02" => DATA <= x"A9"; when x"A03" => DATA <= x"76"; when x"A04" => DATA <= x"D0"; when x"A05" => DATA <= x"06"; when x"A06" => DATA <= x"A9"; when x"A07" => DATA <= x"7D"; when x"A08" => DATA <= x"D0"; when x"A09" => DATA <= x"02"; when x"A0A" => DATA <= x"A9"; when x"A0B" => DATA <= x"84"; when x"A0C" => DATA <= x"48"; when x"A0D" => DATA <= x"20"; when x"A0E" => DATA <= x"5D"; when x"A0F" => DATA <= x"D8"; when x"A10" => DATA <= x"20"; when x"A11" => DATA <= x"FC"; when x"A12" => DATA <= x"D0"; when x"A13" => DATA <= x"20"; when x"A14" => DATA <= x"70"; when x"A15" => DATA <= x"D8"; when x"A16" => DATA <= x"E6"; when x"A17" => DATA <= x"04"; when x"A18" => DATA <= x"20"; when x"A19" => DATA <= x"04"; when x"A1A" => DATA <= x"D8"; when x"A1B" => DATA <= x"A5"; when x"A1C" => DATA <= x"5F"; when x"A1D" => DATA <= x"29"; when x"A1E" => DATA <= x"80"; when x"A1F" => DATA <= x"85"; when x"A20" => DATA <= x"5F"; when x"A21" => DATA <= x"A0"; when x"A22" => DATA <= x"00"; when x"A23" => DATA <= x"A5"; when x"A24" => DATA <= x"57"; when x"A25" => DATA <= x"29"; when x"A26" => DATA <= x"80"; when x"A27" => DATA <= x"C5"; when x"A28" => DATA <= x"5F"; when x"A29" => DATA <= x"D0"; when x"A2A" => DATA <= x"0D"; when x"A2B" => DATA <= x"A2"; when x"A2C" => DATA <= x"00"; when x"A2D" => DATA <= x"B5"; when x"A2E" => DATA <= x"61"; when x"A2F" => DATA <= x"D5"; when x"A30" => DATA <= x"59"; when x"A31" => DATA <= x"D0"; when x"A32" => DATA <= x"0A"; when x"A33" => DATA <= x"E8"; when x"A34" => DATA <= x"E0"; when x"A35" => DATA <= x"05"; when x"A36" => DATA <= x"D0"; when x"A37" => DATA <= x"F5"; when x"A38" => DATA <= x"08"; when x"A39" => DATA <= x"A6"; when x"A3A" => DATA <= x"04"; when x"A3B" => DATA <= x"28"; when x"A3C" => DATA <= x"60"; when x"A3D" => DATA <= x"6A"; when x"A3E" => DATA <= x"45"; when x"A3F" => DATA <= x"5F"; when x"A40" => DATA <= x"2A"; when x"A41" => DATA <= x"A9"; when x"A42" => DATA <= x"01"; when x"A43" => DATA <= x"D0"; when x"A44" => DATA <= x"F3"; when x"A45" => DATA <= x"20"; when x"A46" => DATA <= x"86"; when x"A47" => DATA <= x"D6"; when x"A48" => DATA <= x"F0"; when x"A49" => DATA <= x"F2"; when x"A4A" => DATA <= x"20"; when x"A4B" => DATA <= x"04"; when x"A4C" => DATA <= x"D8"; when x"A4D" => DATA <= x"D0"; when x"A4E" => DATA <= x"03"; when x"A4F" => DATA <= x"4C"; when x"A50" => DATA <= x"A4"; when x"A51" => DATA <= x"DA"; when x"A52" => DATA <= x"18"; when x"A53" => DATA <= x"A5"; when x"A54" => DATA <= x"59"; when x"A55" => DATA <= x"65"; when x"A56" => DATA <= x"61"; when x"A57" => DATA <= x"85"; when x"A58" => DATA <= x"59"; when x"A59" => DATA <= x"90"; when x"A5A" => DATA <= x"02"; when x"A5B" => DATA <= x"E6"; when x"A5C" => DATA <= x"58"; when x"A5D" => DATA <= x"38"; when x"A5E" => DATA <= x"A5"; when x"A5F" => DATA <= x"59"; when x"A60" => DATA <= x"E9"; when x"A61" => DATA <= x"80"; when x"A62" => DATA <= x"85"; when x"A63" => DATA <= x"59"; when x"A64" => DATA <= x"B0"; when x"A65" => DATA <= x"02"; when x"A66" => DATA <= x"C6"; when x"A67" => DATA <= x"58"; when x"A68" => DATA <= x"A2"; when x"A69" => DATA <= x"05"; when x"A6A" => DATA <= x"A0"; when x"A6B" => DATA <= x"00"; when x"A6C" => DATA <= x"B5"; when x"A6D" => DATA <= x"59"; when x"A6E" => DATA <= x"95"; when x"A6F" => DATA <= x"66"; when x"A70" => DATA <= x"94"; when x"A71" => DATA <= x"59"; when x"A72" => DATA <= x"CA"; when x"A73" => DATA <= x"D0"; when x"A74" => DATA <= x"F7"; when x"A75" => DATA <= x"A5"; when x"A76" => DATA <= x"57"; when x"A77" => DATA <= x"45"; when x"A78" => DATA <= x"5F"; when x"A79" => DATA <= x"85"; when x"A7A" => DATA <= x"57"; when x"A7B" => DATA <= x"A0"; when x"A7C" => DATA <= x"20"; when x"A7D" => DATA <= x"20"; when x"A7E" => DATA <= x"FB"; when x"A7F" => DATA <= x"D6"; when x"A80" => DATA <= x"A5"; when x"A81" => DATA <= x"67"; when x"A82" => DATA <= x"10"; when x"A83" => DATA <= x"04"; when x"A84" => DATA <= x"18"; when x"A85" => DATA <= x"20"; when x"A86" => DATA <= x"42"; when x"A87" => DATA <= x"D6"; when x"A88" => DATA <= x"20"; when x"A89" => DATA <= x"FB"; when x"A8A" => DATA <= x"D6"; when x"A8B" => DATA <= x"06"; when x"A8C" => DATA <= x"6B"; when x"A8D" => DATA <= x"26"; when x"A8E" => DATA <= x"6A"; when x"A8F" => DATA <= x"26"; when x"A90" => DATA <= x"69"; when x"A91" => DATA <= x"26"; when x"A92" => DATA <= x"68"; when x"A93" => DATA <= x"26"; when x"A94" => DATA <= x"67"; when x"A95" => DATA <= x"88"; when x"A96" => DATA <= x"D0"; when x"A97" => DATA <= x"E8"; when x"A98" => DATA <= x"20"; when x"A99" => DATA <= x"C8"; when x"A9A" => DATA <= x"D7"; when x"A9B" => DATA <= x"20"; when x"A9C" => DATA <= x"80"; when x"A9D" => DATA <= x"D8"; when x"A9E" => DATA <= x"A5"; when x"A9F" => DATA <= x"58"; when x"AA0" => DATA <= x"F0"; when x"AA1" => DATA <= x"0B"; when x"AA2" => DATA <= x"10"; when x"AA3" => DATA <= x"03"; when x"AA4" => DATA <= x"A2"; when x"AA5" => DATA <= x"08"; when x"AA6" => DATA <= x"A9"; when x"AA7" => DATA <= x"00"; when x"AA8" => DATA <= x"95"; when x"AA9" => DATA <= x"56"; when x"AAA" => DATA <= x"CA"; when x"AAB" => DATA <= x"D0"; when x"AAC" => DATA <= x"FB"; when x"AAD" => DATA <= x"60"; when x"AAE" => DATA <= x"20"; when x"AAF" => DATA <= x"31"; when x"AB0" => DATA <= x"D8"; when x"AB1" => DATA <= x"20"; when x"AB2" => DATA <= x"8D"; when x"AB3" => DATA <= x"DE"; when x"AB4" => DATA <= x"D0"; when x"AB5" => DATA <= x"26"; when x"AB6" => DATA <= x"20"; when x"AB7" => DATA <= x"86"; when x"AB8" => DATA <= x"D6"; when x"AB9" => DATA <= x"F0"; when x"ABA" => DATA <= x"EC"; when x"ABB" => DATA <= x"20"; when x"ABC" => DATA <= x"C3"; when x"ABD" => DATA <= x"D6"; when x"ABE" => DATA <= x"20"; when x"ABF" => DATA <= x"E5"; when x"AC0" => DATA <= x"D1"; when x"AC1" => DATA <= x"D0"; when x"AC2" => DATA <= x"23"; when x"AC3" => DATA <= x"60"; when x"AC4" => DATA <= x"20"; when x"AC5" => DATA <= x"EB"; when x"AC6" => DATA <= x"D0"; when x"AC7" => DATA <= x"20"; when x"AC8" => DATA <= x"9E"; when x"AC9" => DATA <= x"DB"; when x"ACA" => DATA <= x"20"; when x"ACB" => DATA <= x"3D"; when x"ACC" => DATA <= x"D8"; when x"ACD" => DATA <= x"20"; when x"ACE" => DATA <= x"E6"; when x"ACF" => DATA <= x"DC"; when x"AD0" => DATA <= x"20"; when x"AD1" => DATA <= x"9E"; when x"AD2" => DATA <= x"DB"; when x"AD3" => DATA <= x"20"; when x"AD4" => DATA <= x"23"; when x"AD5" => DATA <= x"D9"; when x"AD6" => DATA <= x"20"; when x"AD7" => DATA <= x"F1"; when x"AD8" => DATA <= x"DC"; when x"AD9" => DATA <= x"20"; when x"ADA" => DATA <= x"9E"; when x"ADB" => DATA <= x"DB"; when x"ADC" => DATA <= x"20"; when x"ADD" => DATA <= x"86"; when x"ADE" => DATA <= x"D6"; when x"ADF" => DATA <= x"F0"; when x"AE0" => DATA <= x"CC"; when x"AE1" => DATA <= x"20"; when x"AE2" => DATA <= x"04"; when x"AE3" => DATA <= x"D8"; when x"AE4" => DATA <= x"F0"; when x"AE5" => DATA <= x"C1"; when x"AE6" => DATA <= x"A5"; when x"AE7" => DATA <= x"57"; when x"AE8" => DATA <= x"45"; when x"AE9" => DATA <= x"5F"; when x"AEA" => DATA <= x"85"; when x"AEB" => DATA <= x"57"; when x"AEC" => DATA <= x"38"; when x"AED" => DATA <= x"A5"; when x"AEE" => DATA <= x"59"; when x"AEF" => DATA <= x"E5"; when x"AF0" => DATA <= x"61"; when x"AF1" => DATA <= x"85"; when x"AF2" => DATA <= x"59"; when x"AF3" => DATA <= x"B0"; when x"AF4" => DATA <= x"02"; when x"AF5" => DATA <= x"C6"; when x"AF6" => DATA <= x"58"; when x"AF7" => DATA <= x"18"; when x"AF8" => DATA <= x"A5"; when x"AF9" => DATA <= x"59"; when x"AFA" => DATA <= x"69"; when x"AFB" => DATA <= x"81"; when x"AFC" => DATA <= x"85"; when x"AFD" => DATA <= x"59"; when x"AFE" => DATA <= x"90"; when x"AFF" => DATA <= x"02"; when x"B00" => DATA <= x"E6"; when x"B01" => DATA <= x"58"; when x"B02" => DATA <= x"A2"; when x"B03" => DATA <= x"05"; when x"B04" => DATA <= x"B5"; when x"B05" => DATA <= x"59"; when x"B06" => DATA <= x"95"; when x"B07" => DATA <= x"66"; when x"B08" => DATA <= x"CA"; when x"B09" => DATA <= x"D0"; when x"B0A" => DATA <= x"F9"; when x"B0B" => DATA <= x"46"; when x"B0C" => DATA <= x"67"; when x"B0D" => DATA <= x"66"; when x"B0E" => DATA <= x"68"; when x"B0F" => DATA <= x"66"; when x"B10" => DATA <= x"69"; when x"B11" => DATA <= x"66"; when x"B12" => DATA <= x"6A"; when x"B13" => DATA <= x"66"; when x"B14" => DATA <= x"6B"; when x"B15" => DATA <= x"20"; when x"B16" => DATA <= x"FB"; when x"B17" => DATA <= x"D6"; when x"B18" => DATA <= x"A2"; when x"B19" => DATA <= x"27"; when x"B1A" => DATA <= x"A5"; when x"B1B" => DATA <= x"67"; when x"B1C" => DATA <= x"C5"; when x"B1D" => DATA <= x"62"; when x"B1E" => DATA <= x"D0"; when x"B1F" => DATA <= x"16"; when x"B20" => DATA <= x"A5"; when x"B21" => DATA <= x"68"; when x"B22" => DATA <= x"C5"; when x"B23" => DATA <= x"63"; when x"B24" => DATA <= x"D0"; when x"B25" => DATA <= x"10"; when x"B26" => DATA <= x"A5"; when x"B27" => DATA <= x"69"; when x"B28" => DATA <= x"C5"; when x"B29" => DATA <= x"64"; when x"B2A" => DATA <= x"D0"; when x"B2B" => DATA <= x"0A"; when x"B2C" => DATA <= x"A5"; when x"B2D" => DATA <= x"6A"; when x"B2E" => DATA <= x"C5"; when x"B2F" => DATA <= x"65"; when x"B30" => DATA <= x"D0"; when x"B31" => DATA <= x"04"; when x"B32" => DATA <= x"A5"; when x"B33" => DATA <= x"6B"; when x"B34" => DATA <= x"C5"; when x"B35" => DATA <= x"66"; when x"B36" => DATA <= x"90"; when x"B37" => DATA <= x"24"; when x"B38" => DATA <= x"A5"; when x"B39" => DATA <= x"6B"; when x"B3A" => DATA <= x"E5"; when x"B3B" => DATA <= x"66"; when x"B3C" => DATA <= x"85"; when x"B3D" => DATA <= x"6B"; when x"B3E" => DATA <= x"A5"; when x"B3F" => DATA <= x"6A"; when x"B40" => DATA <= x"E5"; when x"B41" => DATA <= x"65"; when x"B42" => DATA <= x"85"; when x"B43" => DATA <= x"6A"; when x"B44" => DATA <= x"A5"; when x"B45" => DATA <= x"69"; when x"B46" => DATA <= x"E5"; when x"B47" => DATA <= x"64"; when x"B48" => DATA <= x"85"; when x"B49" => DATA <= x"69"; when x"B4A" => DATA <= x"A5"; when x"B4B" => DATA <= x"68"; when x"B4C" => DATA <= x"E5"; when x"B4D" => DATA <= x"63"; when x"B4E" => DATA <= x"85"; when x"B4F" => DATA <= x"68"; when x"B50" => DATA <= x"A5"; when x"B51" => DATA <= x"67"; when x"B52" => DATA <= x"E5"; when x"B53" => DATA <= x"62"; when x"B54" => DATA <= x"85"; when x"B55" => DATA <= x"67"; when x"B56" => DATA <= x"A5"; when x"B57" => DATA <= x"5E"; when x"B58" => DATA <= x"09"; when x"B59" => DATA <= x"01"; when x"B5A" => DATA <= x"85"; when x"B5B" => DATA <= x"5E"; when x"B5C" => DATA <= x"20"; when x"B5D" => DATA <= x"CD"; when x"B5E" => DATA <= x"D6"; when x"B5F" => DATA <= x"06"; when x"B60" => DATA <= x"6B"; when x"B61" => DATA <= x"26"; when x"B62" => DATA <= x"6A"; when x"B63" => DATA <= x"26"; when x"B64" => DATA <= x"69"; when x"B65" => DATA <= x"26"; when x"B66" => DATA <= x"68"; when x"B67" => DATA <= x"26"; when x"B68" => DATA <= x"67"; when x"B69" => DATA <= x"CA"; when x"B6A" => DATA <= x"D0"; when x"B6B" => DATA <= x"AE"; when x"B6C" => DATA <= x"4C"; when x"B6D" => DATA <= x"98"; when x"B6E" => DATA <= x"DA"; when x"B6F" => DATA <= x"20"; when x"B70" => DATA <= x"EB"; when x"B71" => DATA <= x"D0"; when x"B72" => DATA <= x"20"; when x"B73" => DATA <= x"86"; when x"B74" => DATA <= x"D6"; when x"B75" => DATA <= x"F0"; when x"B76" => DATA <= x"26"; when x"B77" => DATA <= x"10"; when x"B78" => DATA <= x"01"; when x"B79" => DATA <= x"00"; when x"B7A" => DATA <= x"20"; when x"B7B" => DATA <= x"31"; when x"B7C" => DATA <= x"D8"; when x"B7D" => DATA <= x"A5"; when x"B7E" => DATA <= x"59"; when x"B7F" => DATA <= x"4A"; when x"B80" => DATA <= x"69"; when x"B81" => DATA <= x"40"; when x"B82" => DATA <= x"85"; when x"B83" => DATA <= x"59"; when x"B84" => DATA <= x"A9"; when x"B85" => DATA <= x"05"; when x"B86" => DATA <= x"85"; when x"B87" => DATA <= x"6E"; when x"B88" => DATA <= x"20"; when x"B89" => DATA <= x"27"; when x"B8A" => DATA <= x"D8"; when x"B8B" => DATA <= x"20"; when x"B8C" => DATA <= x"AA"; when x"B8D" => DATA <= x"DB"; when x"B8E" => DATA <= x"20"; when x"B8F" => DATA <= x"B6"; when x"B90" => DATA <= x"DA"; when x"B91" => DATA <= x"20"; when x"B92" => DATA <= x"A2"; when x"B93" => DATA <= x"DB"; when x"B94" => DATA <= x"20"; when x"B95" => DATA <= x"3C"; when x"B96" => DATA <= x"D9"; when x"B97" => DATA <= x"C6"; when x"B98" => DATA <= x"59"; when x"B99" => DATA <= x"C6"; when x"B9A" => DATA <= x"6E"; when x"B9B" => DATA <= x"D0"; when x"B9C" => DATA <= x"EB"; when x"B9D" => DATA <= x"60"; when x"B9E" => DATA <= x"A9"; when x"B9F" => DATA <= x"D4"; when x"BA0" => DATA <= x"D0"; when x"BA1" => DATA <= x"0A"; when x"BA2" => DATA <= x"A9"; when x"BA3" => DATA <= x"CA"; when x"BA4" => DATA <= x"D0"; when x"BA5" => DATA <= x"06"; when x"BA6" => DATA <= x"A9"; when x"BA7" => DATA <= x"CF"; when x"BA8" => DATA <= x"D0"; when x"BA9" => DATA <= x"02"; when x"BAA" => DATA <= x"A9"; when x"BAB" => DATA <= x"C5"; when x"BAC" => DATA <= x"85"; when x"BAD" => DATA <= x"6F"; when x"BAE" => DATA <= x"A9"; when x"BAF" => DATA <= x"03"; when x"BB0" => DATA <= x"85"; when x"BB1" => DATA <= x"70"; when x"BB2" => DATA <= x"60"; when x"BB3" => DATA <= x"20"; when x"BB4" => DATA <= x"EB"; when x"BB5" => DATA <= x"D0"; when x"BB6" => DATA <= x"20"; when x"BB7" => DATA <= x"86"; when x"BB8" => DATA <= x"D6"; when x"BB9" => DATA <= x"F0"; when x"BBA" => DATA <= x"02"; when x"BBB" => DATA <= x"10"; when x"BBC" => DATA <= x"01"; when x"BBD" => DATA <= x"00"; when x"BBE" => DATA <= x"A5"; when x"BBF" => DATA <= x"59"; when x"BC0" => DATA <= x"48"; when x"BC1" => DATA <= x"A9"; when x"BC2" => DATA <= x"81"; when x"BC3" => DATA <= x"85"; when x"BC4" => DATA <= x"59"; when x"BC5" => DATA <= x"20"; when x"BC6" => DATA <= x"C7"; when x"BC7" => DATA <= x"D8"; when x"BC8" => DATA <= x"A9"; when x"BC9" => DATA <= x"C0"; when x"BCA" => DATA <= x"85"; when x"BCB" => DATA <= x"62"; when x"BCC" => DATA <= x"A9"; when x"BCD" => DATA <= x"81"; when x"BCE" => DATA <= x"85"; when x"BCF" => DATA <= x"61"; when x"BD0" => DATA <= x"85"; when x"BD1" => DATA <= x"5F"; when x"BD2" => DATA <= x"20"; when x"BD3" => DATA <= x"41"; when x"BD4" => DATA <= x"D9"; when x"BD5" => DATA <= x"E6"; when x"BD6" => DATA <= x"59"; when x"BD7" => DATA <= x"A9"; when x"BD8" => DATA <= x"FE"; when x"BD9" => DATA <= x"A0"; when x"BDA" => DATA <= x"DB"; when x"BDB" => DATA <= x"20"; when x"BDC" => DATA <= x"27"; when x"BDD" => DATA <= x"DC"; when x"BDE" => DATA <= x"20"; when x"BDF" => DATA <= x"31"; when x"BE0" => DATA <= x"D8"; when x"BE1" => DATA <= x"68"; when x"BE2" => DATA <= x"38"; when x"BE3" => DATA <= x"E9"; when x"BE4" => DATA <= x"81"; when x"BE5" => DATA <= x"20"; when x"BE6" => DATA <= x"B2"; when x"BE7" => DATA <= x"D7"; when x"BE8" => DATA <= x"A9"; when x"BE9" => DATA <= x"F9"; when x"BEA" => DATA <= x"85"; when x"BEB" => DATA <= x"6F"; when x"BEC" => DATA <= x"A9"; when x"BED" => DATA <= x"DB"; when x"BEE" => DATA <= x"85"; when x"BEF" => DATA <= x"70"; when x"BF0" => DATA <= x"20"; when x"BF1" => DATA <= x"45"; when x"BF2" => DATA <= x"DA"; when x"BF3" => DATA <= x"20"; when x"BF4" => DATA <= x"AA"; when x"BF5" => DATA <= x"DB"; when x"BF6" => DATA <= x"4C"; when x"BF7" => DATA <= x"3C"; when x"BF8" => DATA <= x"D9"; when x"BF9" => DATA <= x"80"; when x"BFA" => DATA <= x"31"; when x"BFB" => DATA <= x"72"; when x"BFC" => DATA <= x"17"; when x"BFD" => DATA <= x"F8"; when x"BFE" => DATA <= x"07"; when x"BFF" => DATA <= x"85"; when x"C00" => DATA <= x"17"; when x"C01" => DATA <= x"6E"; when x"C02" => DATA <= x"D4"; when x"C03" => DATA <= x"85"; when x"C04" => DATA <= x"80"; when x"C05" => DATA <= x"28"; when x"C06" => DATA <= x"C7"; when x"C07" => DATA <= x"12"; when x"C08" => DATA <= x"A0"; when x"C09" => DATA <= x"84"; when x"C0A" => DATA <= x"70"; when x"C0B" => DATA <= x"4E"; when x"C0C" => DATA <= x"5F"; when x"C0D" => DATA <= x"F2"; when x"C0E" => DATA <= x"81"; when x"C0F" => DATA <= x"00"; when x"C10" => DATA <= x"00"; when x"C11" => DATA <= x"FE"; when x"C12" => DATA <= x"EF"; when x"C13" => DATA <= x"84"; when x"C14" => DATA <= x"0F"; when x"C15" => DATA <= x"FF"; when x"C16" => DATA <= x"DA"; when x"C17" => DATA <= x"E1"; when x"C18" => DATA <= x"81"; when x"C19" => DATA <= x"7F"; when x"C1A" => DATA <= x"FF"; when x"C1B" => DATA <= x"FF"; when x"C1C" => DATA <= x"93"; when x"C1D" => DATA <= x"82"; when x"C1E" => DATA <= x"40"; when x"C1F" => DATA <= x"00"; when x"C20" => DATA <= x"00"; when x"C21" => DATA <= x"0C"; when x"C22" => DATA <= x"7F"; when x"C23" => DATA <= x"4F"; when x"C24" => DATA <= x"99"; when x"C25" => DATA <= x"1F"; when x"C26" => DATA <= x"65"; when x"C27" => DATA <= x"85"; when x"C28" => DATA <= x"71"; when x"C29" => DATA <= x"84"; when x"C2A" => DATA <= x"72"; when x"C2B" => DATA <= x"20"; when x"C2C" => DATA <= x"31"; when x"C2D" => DATA <= x"D8"; when x"C2E" => DATA <= x"A0"; when x"C2F" => DATA <= x"00"; when x"C30" => DATA <= x"B1"; when x"C31" => DATA <= x"71"; when x"C32" => DATA <= x"85"; when x"C33" => DATA <= x"6C"; when x"C34" => DATA <= x"E6"; when x"C35" => DATA <= x"71"; when x"C36" => DATA <= x"D0"; when x"C37" => DATA <= x"02"; when x"C38" => DATA <= x"E6"; when x"C39" => DATA <= x"72"; when x"C3A" => DATA <= x"A5"; when x"C3B" => DATA <= x"71"; when x"C3C" => DATA <= x"85"; when x"C3D" => DATA <= x"6F"; when x"C3E" => DATA <= x"A5"; when x"C3F" => DATA <= x"72"; when x"C40" => DATA <= x"85"; when x"C41" => DATA <= x"70"; when x"C42" => DATA <= x"20"; when x"C43" => DATA <= x"E5"; when x"C44" => DATA <= x"D1"; when x"C45" => DATA <= x"20"; when x"C46" => DATA <= x"AA"; when x"C47" => DATA <= x"DB"; when x"C48" => DATA <= x"20"; when x"C49" => DATA <= x"B6"; when x"C4A" => DATA <= x"DA"; when x"C4B" => DATA <= x"18"; when x"C4C" => DATA <= x"A5"; when x"C4D" => DATA <= x"71"; when x"C4E" => DATA <= x"69"; when x"C4F" => DATA <= x"05"; when x"C50" => DATA <= x"85"; when x"C51" => DATA <= x"71"; when x"C52" => DATA <= x"85"; when x"C53" => DATA <= x"6F"; when x"C54" => DATA <= x"A5"; when x"C55" => DATA <= x"72"; when x"C56" => DATA <= x"69"; when x"C57" => DATA <= x"00"; when x"C58" => DATA <= x"85"; when x"C59" => DATA <= x"72"; when x"C5A" => DATA <= x"85"; when x"C5B" => DATA <= x"70"; when x"C5C" => DATA <= x"20"; when x"C5D" => DATA <= x"3C"; when x"C5E" => DATA <= x"D9"; when x"C5F" => DATA <= x"C6"; when x"C60" => DATA <= x"6C"; when x"C61" => DATA <= x"D0"; when x"C62" => DATA <= x"E2"; when x"C63" => DATA <= x"60"; when x"C64" => DATA <= x"20"; when x"C65" => DATA <= x"EB"; when x"C66" => DATA <= x"D0"; when x"C67" => DATA <= x"20"; when x"C68" => DATA <= x"86"; when x"C69" => DATA <= x"D6"; when x"C6A" => DATA <= x"F0"; when x"C6B" => DATA <= x"0D"; when x"C6C" => DATA <= x"10"; when x"C6D" => DATA <= x"0C"; when x"C6E" => DATA <= x"A9"; when x"C6F" => DATA <= x"00"; when x"C70" => DATA <= x"85"; when x"C71" => DATA <= x"57"; when x"C72" => DATA <= x"20"; when x"C73" => DATA <= x"7A"; when x"C74" => DATA <= x"DC"; when x"C75" => DATA <= x"A9"; when x"C76" => DATA <= x"80"; when x"C77" => DATA <= x"85"; when x"C78" => DATA <= x"57"; when x"C79" => DATA <= x"60"; when x"C7A" => DATA <= x"A5"; when x"C7B" => DATA <= x"59"; when x"C7C" => DATA <= x"C9"; when x"C7D" => DATA <= x"81"; when x"C7E" => DATA <= x"90"; when x"C7F" => DATA <= x"0C"; when x"C80" => DATA <= x"20"; when x"C81" => DATA <= x"AE"; when x"C82" => DATA <= x"DA"; when x"C83" => DATA <= x"20"; when x"C84" => DATA <= x"8C"; when x"C85" => DATA <= x"DC"; when x"C86" => DATA <= x"20"; when x"C87" => DATA <= x"93"; when x"C88" => DATA <= x"DD"; when x"C89" => DATA <= x"4C"; when x"C8A" => DATA <= x"39"; when x"C8B" => DATA <= x"D9"; when x"C8C" => DATA <= x"A5"; when x"C8D" => DATA <= x"59"; when x"C8E" => DATA <= x"C9"; when x"C8F" => DATA <= x"73"; when x"C90" => DATA <= x"90"; when x"C91" => DATA <= x"E7"; when x"C92" => DATA <= x"20"; when x"C93" => DATA <= x"2C"; when x"C94" => DATA <= x"D8"; when x"C95" => DATA <= x"20"; when x"C96" => DATA <= x"C7"; when x"C97" => DATA <= x"D8"; when x"C98" => DATA <= x"A9"; when x"C99" => DATA <= x"80"; when x"C9A" => DATA <= x"85"; when x"C9B" => DATA <= x"61"; when x"C9C" => DATA <= x"85"; when x"C9D" => DATA <= x"62"; when x"C9E" => DATA <= x"85"; when x"C9F" => DATA <= x"5F"; when x"CA0" => DATA <= x"20"; when x"CA1" => DATA <= x"41"; when x"CA2" => DATA <= x"D9"; when x"CA3" => DATA <= x"A9"; when x"CA4" => DATA <= x"B0"; when x"CA5" => DATA <= x"A0"; when x"CA6" => DATA <= x"DC"; when x"CA7" => DATA <= x"20"; when x"CA8" => DATA <= x"27"; when x"CA9" => DATA <= x"DC"; when x"CAA" => DATA <= x"20"; when x"CAB" => DATA <= x"A6"; when x"CAC" => DATA <= x"DB"; when x"CAD" => DATA <= x"4C"; when x"CAE" => DATA <= x"45"; when x"CAF" => DATA <= x"DA"; when x"CB0" => DATA <= x"09"; when x"CB1" => DATA <= x"85"; when x"CB2" => DATA <= x"A3"; when x"CB3" => DATA <= x"59"; when x"CB4" => DATA <= x"E8"; when x"CB5" => DATA <= x"67"; when x"CB6" => DATA <= x"80"; when x"CB7" => DATA <= x"1C"; when x"CB8" => DATA <= x"9D"; when x"CB9" => DATA <= x"07"; when x"CBA" => DATA <= x"36"; when x"CBB" => DATA <= x"80"; when x"CBC" => DATA <= x"57"; when x"CBD" => DATA <= x"BB"; when x"CBE" => DATA <= x"78"; when x"CBF" => DATA <= x"DF"; when x"CC0" => DATA <= x"80"; when x"CC1" => DATA <= x"CA"; when x"CC2" => DATA <= x"9A"; when x"CC3" => DATA <= x"0E"; when x"CC4" => DATA <= x"83"; when x"CC5" => DATA <= x"84"; when x"CC6" => DATA <= x"8C"; when x"CC7" => DATA <= x"BB"; when x"CC8" => DATA <= x"CA"; when x"CC9" => DATA <= x"6E"; when x"CCA" => DATA <= x"81"; when x"CCB" => DATA <= x"95"; when x"CCC" => DATA <= x"96"; when x"CCD" => DATA <= x"06"; when x"CCE" => DATA <= x"DE"; when x"CCF" => DATA <= x"81"; when x"CD0" => DATA <= x"0A"; when x"CD1" => DATA <= x"C7"; when x"CD2" => DATA <= x"6C"; when x"CD3" => DATA <= x"52"; when x"CD4" => DATA <= x"7F"; when x"CD5" => DATA <= x"7D"; when x"CD6" => DATA <= x"AD"; when x"CD7" => DATA <= x"90"; when x"CD8" => DATA <= x"A1"; when x"CD9" => DATA <= x"82"; when x"CDA" => DATA <= x"FB"; when x"CDB" => DATA <= x"62"; when x"CDC" => DATA <= x"57"; when x"CDD" => DATA <= x"2F"; when x"CDE" => DATA <= x"80"; when x"CDF" => DATA <= x"6D"; when x"CE0" => DATA <= x"63"; when x"CE1" => DATA <= x"38"; when x"CE2" => DATA <= x"2C"; when x"CE3" => DATA <= x"20"; when x"CE4" => DATA <= x"EB"; when x"CE5" => DATA <= x"D0"; when x"CE6" => DATA <= x"20"; when x"CE7" => DATA <= x"24"; when x"CE8" => DATA <= x"DD"; when x"CE9" => DATA <= x"E6"; when x"CEA" => DATA <= x"6E"; when x"CEB" => DATA <= x"4C"; when x"CEC" => DATA <= x"F4"; when x"CED" => DATA <= x"DC"; when x"CEE" => DATA <= x"20"; when x"CEF" => DATA <= x"EB"; when x"CF0" => DATA <= x"D0"; when x"CF1" => DATA <= x"20"; when x"CF2" => DATA <= x"24"; when x"CF3" => DATA <= x"DD"; when x"CF4" => DATA <= x"46"; when x"CF5" => DATA <= x"6E"; when x"CF6" => DATA <= x"90"; when x"CF7" => DATA <= x"03"; when x"CF8" => DATA <= x"20"; when x"CF9" => DATA <= x"86"; when x"CFA" => DATA <= x"DC"; when x"CFB" => DATA <= x"46"; when x"CFC" => DATA <= x"6E"; when x"CFD" => DATA <= x"90"; when x"CFE" => DATA <= x"06"; when x"CFF" => DATA <= x"20"; when x"D00" => DATA <= x"05"; when x"D01" => DATA <= x"DD"; when x"D02" => DATA <= x"4C"; when x"D03" => DATA <= x"BF"; when x"D04" => DATA <= x"D1"; when x"D05" => DATA <= x"20"; when x"D06" => DATA <= x"2C"; when x"D07" => DATA <= x"D8"; when x"D08" => DATA <= x"20"; when x"D09" => DATA <= x"93"; when x"D0A" => DATA <= x"DD"; when x"D0B" => DATA <= x"20"; when x"D0C" => DATA <= x"04"; when x"D0D" => DATA <= x"D8"; when x"D0E" => DATA <= x"C6"; when x"D0F" => DATA <= x"61"; when x"D10" => DATA <= x"A9"; when x"D11" => DATA <= x"80"; when x"D12" => DATA <= x"85"; when x"D13" => DATA <= x"5F"; when x"D14" => DATA <= x"20"; when x"D15" => DATA <= x"41"; when x"D16" => DATA <= x"D9"; when x"D17" => DATA <= x"A9"; when x"D18" => DATA <= x"A6"; when x"D19" => DATA <= x"A0"; when x"D1A" => DATA <= x"DD"; when x"D1B" => DATA <= x"20"; when x"D1C" => DATA <= x"27"; when x"D1D" => DATA <= x"DC"; when x"D1E" => DATA <= x"20"; when x"D1F" => DATA <= x"A6"; when x"D20" => DATA <= x"DB"; when x"D21" => DATA <= x"4C"; when x"D22" => DATA <= x"45"; when x"D23" => DATA <= x"DA"; when x"D24" => DATA <= x"A5"; when x"D25" => DATA <= x"59"; when x"D26" => DATA <= x"C9"; when x"D27" => DATA <= x"98"; when x"D28" => DATA <= x"B0"; when x"D29" => DATA <= x"54"; when x"D2A" => DATA <= x"20"; when x"D2B" => DATA <= x"31"; when x"D2C" => DATA <= x"D8"; when x"D2D" => DATA <= x"20"; when x"D2E" => DATA <= x"93"; when x"D2F" => DATA <= x"DD"; when x"D30" => DATA <= x"20"; when x"D31" => DATA <= x"DC"; when x"D32" => DATA <= x"DA"; when x"D33" => DATA <= x"20"; when x"D34" => DATA <= x"9A"; when x"D35" => DATA <= x"D8"; when x"D36" => DATA <= x"A5"; when x"D37" => DATA <= x"5D"; when x"D38" => DATA <= x"85"; when x"D39" => DATA <= x"6E"; when x"D3A" => DATA <= x"05"; when x"D3B" => DATA <= x"5C"; when x"D3C" => DATA <= x"05"; when x"D3D" => DATA <= x"5B"; when x"D3E" => DATA <= x"05"; when x"D3F" => DATA <= x"5A"; when x"D40" => DATA <= x"F0"; when x"D41" => DATA <= x"3E"; when x"D42" => DATA <= x"20"; when x"D43" => DATA <= x"AC"; when x"D44" => DATA <= x"D2"; when x"D45" => DATA <= x"20"; when x"D46" => DATA <= x"27"; when x"D47" => DATA <= x"D8"; when x"D48" => DATA <= x"20"; when x"D49" => DATA <= x"86"; when x"D4A" => DATA <= x"DD"; when x"D4B" => DATA <= x"20"; when x"D4C" => DATA <= x"45"; when x"D4D" => DATA <= x"DA"; when x"D4E" => DATA <= x"20"; when x"D4F" => DATA <= x"AA"; when x"D50" => DATA <= x"DB"; when x"D51" => DATA <= x"20"; when x"D52" => DATA <= x"3C"; when x"D53" => DATA <= x"D9"; when x"D54" => DATA <= x"20"; when x"D55" => DATA <= x"3D"; when x"D56" => DATA <= x"D8"; when x"D57" => DATA <= x"20"; when x"D58" => DATA <= x"A2"; when x"D59" => DATA <= x"DB"; when x"D5A" => DATA <= x"20"; when x"D5B" => DATA <= x"E5"; when x"D5C" => DATA <= x"D1"; when x"D5D" => DATA <= x"20"; when x"D5E" => DATA <= x"8A"; when x"D5F" => DATA <= x"DD"; when x"D60" => DATA <= x"20"; when x"D61" => DATA <= x"45"; when x"D62" => DATA <= x"DA"; when x"D63" => DATA <= x"20"; when x"D64" => DATA <= x"AA"; when x"D65" => DATA <= x"DB"; when x"D66" => DATA <= x"20"; when x"D67" => DATA <= x"3C"; when x"D68" => DATA <= x"D9"; when x"D69" => DATA <= x"A5"; when x"D6A" => DATA <= x"57"; when x"D6B" => DATA <= x"10"; when x"D6C" => DATA <= x"12"; when x"D6D" => DATA <= x"20"; when x"D6E" => DATA <= x"8A"; when x"D6F" => DATA <= x"DD"; when x"D70" => DATA <= x"20"; when x"D71" => DATA <= x"33"; when x"D72" => DATA <= x"D9"; when x"D73" => DATA <= x"20"; when x"D74" => DATA <= x"86"; when x"D75" => DATA <= x"DD"; when x"D76" => DATA <= x"20"; when x"D77" => DATA <= x"33"; when x"D78" => DATA <= x"D9"; when x"D79" => DATA <= x"C6"; when x"D7A" => DATA <= x"6E"; when x"D7B" => DATA <= x"4C"; when x"D7C" => DATA <= x"69"; when x"D7D" => DATA <= x"DD"; when x"D7E" => DATA <= x"00"; when x"D7F" => DATA <= x"60"; when x"D80" => DATA <= x"20"; when x"D81" => DATA <= x"DA"; when x"D82" => DATA <= x"D2"; when x"D83" => DATA <= x"4C"; when x"D84" => DATA <= x"69"; when x"D85" => DATA <= x"DD"; when x"D86" => DATA <= x"A9"; when x"D87" => DATA <= x"97"; when x"D88" => DATA <= x"D0"; when x"D89" => DATA <= x"02"; when x"D8A" => DATA <= x"A9"; when x"D8B" => DATA <= x"9C"; when x"D8C" => DATA <= x"85"; when x"D8D" => DATA <= x"6F"; when x"D8E" => DATA <= x"A9"; when x"D8F" => DATA <= x"DD"; when x"D90" => DATA <= x"85"; when x"D91" => DATA <= x"70"; when x"D92" => DATA <= x"60"; when x"D93" => DATA <= x"A9"; when x"D94" => DATA <= x"A1"; when x"D95" => DATA <= x"D0"; when x"D96" => DATA <= x"F5"; when x"D97" => DATA <= x"81"; when x"D98" => DATA <= x"C9"; when x"D99" => DATA <= x"00"; when x"D9A" => DATA <= x"00"; when x"D9B" => DATA <= x"00"; when x"D9C" => DATA <= x"75"; when x"D9D" => DATA <= x"FD"; when x"D9E" => DATA <= x"AA"; when x"D9F" => DATA <= x"22"; when x"DA0" => DATA <= x"17"; when x"DA1" => DATA <= x"81"; when x"DA2" => DATA <= x"49"; when x"DA3" => DATA <= x"0F"; when x"DA4" => DATA <= x"DA"; when x"DA5" => DATA <= x"A2"; when x"DA6" => DATA <= x"08"; when x"DA7" => DATA <= x"84"; when x"DA8" => DATA <= x"04"; when x"DA9" => DATA <= x"C7"; when x"DAA" => DATA <= x"3C"; when x"DAB" => DATA <= x"FB"; when x"DAC" => DATA <= x"81"; when x"DAD" => DATA <= x"E0"; when x"DAE" => DATA <= x"4F"; when x"DAF" => DATA <= x"5D"; when x"DB0" => DATA <= x"AD"; when x"DB1" => DATA <= x"82"; when x"DB2" => DATA <= x"80"; when x"DB3" => DATA <= x"00"; when x"DB4" => DATA <= x"69"; when x"DB5" => DATA <= x"B8"; when x"DB6" => DATA <= x"82"; when x"DB7" => DATA <= x"5B"; when x"DB8" => DATA <= x"CF"; when x"DB9" => DATA <= x"1D"; when x"DBA" => DATA <= x"B5"; when x"DBB" => DATA <= x"82"; when x"DBC" => DATA <= x"BF"; when x"DBD" => DATA <= x"CE"; when x"DBE" => DATA <= x"82"; when x"DBF" => DATA <= x"1E"; when x"DC0" => DATA <= x"82"; when x"DC1" => DATA <= x"45"; when x"DC2" => DATA <= x"44"; when x"DC3" => DATA <= x"7F"; when x"DC4" => DATA <= x"32"; when x"DC5" => DATA <= x"7F"; when x"DC6" => DATA <= x"62"; when x"DC7" => DATA <= x"44"; when x"DC8" => DATA <= x"5A"; when x"DC9" => DATA <= x"D2"; when x"DCA" => DATA <= x"83"; when x"DCB" => DATA <= x"82"; when x"DCC" => DATA <= x"14"; when x"DCD" => DATA <= x"8A"; when x"DCE" => DATA <= x"27"; when x"DCF" => DATA <= x"80"; when x"DD0" => DATA <= x"66"; when x"DD1" => DATA <= x"7B"; when x"DD2" => DATA <= x"21"; when x"DD3" => DATA <= x"4D"; when x"DD4" => DATA <= x"20"; when x"DD5" => DATA <= x"EB"; when x"DD6" => DATA <= x"D0"; when x"DD7" => DATA <= x"A5"; when x"DD8" => DATA <= x"59"; when x"DD9" => DATA <= x"C9"; when x"DDA" => DATA <= x"87"; when x"DDB" => DATA <= x"90"; when x"DDC" => DATA <= x"10"; when x"DDD" => DATA <= x"D0"; when x"DDE" => DATA <= x"06"; when x"DDF" => DATA <= x"A5"; when x"DE0" => DATA <= x"5A"; when x"DE1" => DATA <= x"C9"; when x"DE2" => DATA <= x"B3"; when x"DE3" => DATA <= x"90"; when x"DE4" => DATA <= x"08"; when x"DE5" => DATA <= x"A5"; when x"DE6" => DATA <= x"57"; when x"DE7" => DATA <= x"10"; when x"DE8" => DATA <= x"03"; when x"DE9" => DATA <= x"4C"; when x"DEA" => DATA <= x"A4"; when x"DEB" => DATA <= x"DA"; when x"DEC" => DATA <= x"00"; when x"DED" => DATA <= x"A5"; when x"DEE" => DATA <= x"59"; when x"DEF" => DATA <= x"C9"; when x"DF0" => DATA <= x"80"; when x"DF1" => DATA <= x"90"; when x"DF2" => DATA <= x"29"; when x"DF3" => DATA <= x"20"; when x"DF4" => DATA <= x"9A"; when x"DF5" => DATA <= x"D8"; when x"DF6" => DATA <= x"20"; when x"DF7" => DATA <= x"E2"; when x"DF8" => DATA <= x"D8"; when x"DF9" => DATA <= x"A5"; when x"DFA" => DATA <= x"5D"; when x"DFB" => DATA <= x"85"; when x"DFC" => DATA <= x"6E"; when x"DFD" => DATA <= x"20"; when x"DFE" => DATA <= x"13"; when x"DFF" => DATA <= x"D9"; when x"E00" => DATA <= x"20"; when x"E01" => DATA <= x"1C"; when x"E02" => DATA <= x"DE"; when x"E03" => DATA <= x"20"; when x"E04" => DATA <= x"2C"; when x"E05" => DATA <= x"D8"; when x"E06" => DATA <= x"A9"; when x"E07" => DATA <= x"23"; when x"E08" => DATA <= x"85"; when x"E09" => DATA <= x"6F"; when x"E0A" => DATA <= x"A9"; when x"E0B" => DATA <= x"DE"; when x"E0C" => DATA <= x"85"; when x"E0D" => DATA <= x"70"; when x"E0E" => DATA <= x"20"; when x"E0F" => DATA <= x"E5"; when x"E10" => DATA <= x"D1"; when x"E11" => DATA <= x"A5"; when x"E12" => DATA <= x"6E"; when x"E13" => DATA <= x"20"; when x"E14" => DATA <= x"51"; when x"E15" => DATA <= x"DE"; when x"E16" => DATA <= x"20"; when x"E17" => DATA <= x"A6"; when x"E18" => DATA <= x"DB"; when x"E19" => DATA <= x"4C"; when x"E1A" => DATA <= x"45"; when x"E1B" => DATA <= x"DA"; when x"E1C" => DATA <= x"A9"; when x"E1D" => DATA <= x"28"; when x"E1E" => DATA <= x"A0"; when x"E1F" => DATA <= x"DE"; when x"E20" => DATA <= x"4C"; when x"E21" => DATA <= x"27"; when x"E22" => DATA <= x"DC"; when x"E23" => DATA <= x"82"; when x"E24" => DATA <= x"2D"; when x"E25" => DATA <= x"F8"; when x"E26" => DATA <= x"54"; when x"E27" => DATA <= x"58"; when x"E28" => DATA <= x"07"; when x"E29" => DATA <= x"83"; when x"E2A" => DATA <= x"E0"; when x"E2B" => DATA <= x"20"; when x"E2C" => DATA <= x"86"; when x"E2D" => DATA <= x"5B"; when x"E2E" => DATA <= x"82"; when x"E2F" => DATA <= x"80"; when x"E30" => DATA <= x"53"; when x"E31" => DATA <= x"93"; when x"E32" => DATA <= x"B8"; when x"E33" => DATA <= x"83"; when x"E34" => DATA <= x"20"; when x"E35" => DATA <= x"00"; when x"E36" => DATA <= x"06"; when x"E37" => DATA <= x"A1"; when x"E38" => DATA <= x"82"; when x"E39" => DATA <= x"00"; when x"E3A" => DATA <= x"00"; when x"E3B" => DATA <= x"21"; when x"E3C" => DATA <= x"63"; when x"E3D" => DATA <= x"82"; when x"E3E" => DATA <= x"C0"; when x"E3F" => DATA <= x"00"; when x"E40" => DATA <= x"00"; when x"E41" => DATA <= x"02"; when x"E42" => DATA <= x"82"; when x"E43" => DATA <= x"80"; when x"E44" => DATA <= x"00"; when x"E45" => DATA <= x"00"; when x"E46" => DATA <= x"0C"; when x"E47" => DATA <= x"81"; when x"E48" => DATA <= x"00"; when x"E49" => DATA <= x"00"; when x"E4A" => DATA <= x"00"; when x"E4B" => DATA <= x"00"; when x"E4C" => DATA <= x"81"; when x"E4D" => DATA <= x"00"; when x"E4E" => DATA <= x"00"; when x"E4F" => DATA <= x"00"; when x"E50" => DATA <= x"00"; when x"E51" => DATA <= x"AA"; when x"E52" => DATA <= x"10"; when x"E53" => DATA <= x"09"; when x"E54" => DATA <= x"CA"; when x"E55" => DATA <= x"8A"; when x"E56" => DATA <= x"49"; when x"E57" => DATA <= x"FF"; when x"E58" => DATA <= x"48"; when x"E59" => DATA <= x"20"; when x"E5A" => DATA <= x"AE"; when x"E5B" => DATA <= x"DA"; when x"E5C" => DATA <= x"68"; when x"E5D" => DATA <= x"48"; when x"E5E" => DATA <= x"20"; when x"E5F" => DATA <= x"31"; when x"E60" => DATA <= x"D8"; when x"E61" => DATA <= x"20"; when x"E62" => DATA <= x"8D"; when x"E63" => DATA <= x"DE"; when x"E64" => DATA <= x"68"; when x"E65" => DATA <= x"F0"; when x"E66" => DATA <= x"0A"; when x"E67" => DATA <= x"38"; when x"E68" => DATA <= x"E9"; when x"E69" => DATA <= x"01"; when x"E6A" => DATA <= x"48"; when x"E6B" => DATA <= x"20"; when x"E6C" => DATA <= x"45"; when x"E6D" => DATA <= x"DA"; when x"E6E" => DATA <= x"4C"; when x"E6F" => DATA <= x"64"; when x"E70" => DATA <= x"DE"; when x"E71" => DATA <= x"60"; when x"E72" => DATA <= x"20"; when x"E73" => DATA <= x"EB"; when x"E74" => DATA <= x"D0"; when x"E75" => DATA <= x"A5"; when x"E76" => DATA <= x"57"; when x"E77" => DATA <= x"10"; when x"E78" => DATA <= x"0A"; when x"E79" => DATA <= x"A9"; when x"E7A" => DATA <= x"00"; when x"E7B" => DATA <= x"85"; when x"E7C" => DATA <= x"57"; when x"E7D" => DATA <= x"20"; when x"E7E" => DATA <= x"83"; when x"E7F" => DATA <= x"DE"; when x"E80" => DATA <= x"4C"; when x"E81" => DATA <= x"BF"; when x"E82" => DATA <= x"D1"; when x"E83" => DATA <= x"A5"; when x"E84" => DATA <= x"59"; when x"E85" => DATA <= x"C9"; when x"E86" => DATA <= x"81"; when x"E87" => DATA <= x"90"; when x"E88" => DATA <= x"33"; when x"E89" => DATA <= x"C9"; when x"E8A" => DATA <= x"85"; when x"E8B" => DATA <= x"90"; when x"E8C" => DATA <= x"0B"; when x"E8D" => DATA <= x"20"; when x"E8E" => DATA <= x"A4"; when x"E8F" => DATA <= x"DA"; when x"E90" => DATA <= x"A0"; when x"E91" => DATA <= x"80"; when x"E92" => DATA <= x"84"; when x"E93" => DATA <= x"5A"; when x"E94" => DATA <= x"C8"; when x"E95" => DATA <= x"84"; when x"E96" => DATA <= x"59"; when x"E97" => DATA <= x"60"; when x"E98" => DATA <= x"E6"; when x"E99" => DATA <= x"59"; when x"E9A" => DATA <= x"A9"; when x"E9B" => DATA <= x"80"; when x"E9C" => DATA <= x"85"; when x"E9D" => DATA <= x"57"; when x"E9E" => DATA <= x"20"; when x"E9F" => DATA <= x"D7"; when x"EA0" => DATA <= x"DD"; when x"EA1" => DATA <= x"20"; when x"EA2" => DATA <= x"31"; when x"EA3" => DATA <= x"D8"; when x"EA4" => DATA <= x"20"; when x"EA5" => DATA <= x"8D"; when x"EA6" => DATA <= x"DE"; when x"EA7" => DATA <= x"20"; when x"EA8" => DATA <= x"3C"; when x"EA9" => DATA <= x"D9"; when x"EAA" => DATA <= x"20"; when x"EAB" => DATA <= x"27"; when x"EAC" => DATA <= x"D8"; when x"EAD" => DATA <= x"20"; when x"EAE" => DATA <= x"8D"; when x"EAF" => DATA <= x"DE"; when x"EB0" => DATA <= x"20"; when x"EB1" => DATA <= x"AA"; when x"EB2" => DATA <= x"DB"; when x"EB3" => DATA <= x"20"; when x"EB4" => DATA <= x"33"; when x"EB5" => DATA <= x"D9"; when x"EB6" => DATA <= x"20"; when x"EB7" => DATA <= x"A2"; when x"EB8" => DATA <= x"DB"; when x"EB9" => DATA <= x"4C"; when x"EBA" => DATA <= x"DC"; when x"EBB" => DATA <= x"DA"; when x"EBC" => DATA <= x"20"; when x"EBD" => DATA <= x"2C"; when x"EBE" => DATA <= x"D8"; when x"EBF" => DATA <= x"20"; when x"EC0" => DATA <= x"8D"; when x"EC1" => DATA <= x"DE"; when x"EC2" => DATA <= x"C6"; when x"EC3" => DATA <= x"59"; when x"EC4" => DATA <= x"20"; when x"EC5" => DATA <= x"33"; when x"EC6" => DATA <= x"D9"; when x"EC7" => DATA <= x"A9"; when x"EC8" => DATA <= x"D4"; when x"EC9" => DATA <= x"A0"; when x"ECA" => DATA <= x"DE"; when x"ECB" => DATA <= x"20"; when x"ECC" => DATA <= x"27"; when x"ECD" => DATA <= x"DC"; when x"ECE" => DATA <= x"20"; when x"ECF" => DATA <= x"A6"; when x"ED0" => DATA <= x"DB"; when x"ED1" => DATA <= x"4C"; when x"ED2" => DATA <= x"45"; when x"ED3" => DATA <= x"DA"; when x"ED4" => DATA <= x"08"; when x"ED5" => DATA <= x"7E"; when x"ED6" => DATA <= x"85"; when x"ED7" => DATA <= x"51"; when x"ED8" => DATA <= x"B3"; when x"ED9" => DATA <= x"0C"; when x"EDA" => DATA <= x"86"; when x"EDB" => DATA <= x"DE"; when x"EDC" => DATA <= x"B0"; when x"EDD" => DATA <= x"7D"; when x"EDE" => DATA <= x"73"; when x"EDF" => DATA <= x"7C"; when x"EE0" => DATA <= x"23"; when x"EE1" => DATA <= x"D8"; when x"EE2" => DATA <= x"E9"; when x"EE3" => DATA <= x"9A"; when x"EE4" => DATA <= x"87"; when x"EE5" => DATA <= x"34"; when x"EE6" => DATA <= x"82"; when x"EE7" => DATA <= x"1D"; when x"EE8" => DATA <= x"80"; when x"EE9" => DATA <= x"81"; when x"EEA" => DATA <= x"9A"; when x"EEB" => DATA <= x"20"; when x"EEC" => DATA <= x"6C"; when x"EED" => DATA <= x"ED"; when x"EEE" => DATA <= x"81"; when x"EEF" => DATA <= x"BD"; when x"EF0" => DATA <= x"32"; when x"EF1" => DATA <= x"34"; when x"EF2" => DATA <= x"2E"; when x"EF3" => DATA <= x"7F"; when x"EF4" => DATA <= x"5D"; when x"EF5" => DATA <= x"46"; when x"EF6" => DATA <= x"87"; when x"EF7" => DATA <= x"B4"; when x"EF8" => DATA <= x"82"; when x"EF9" => DATA <= x"68"; when x"EFA" => DATA <= x"3E"; when x"EFB" => DATA <= x"43"; when x"EFC" => DATA <= x"F7"; when x"EFD" => DATA <= x"80"; when x"EFE" => DATA <= x"6C"; when x"EFF" => DATA <= x"9A"; when x"F00" => DATA <= x"9E"; when x"F01" => DATA <= x"BB"; when x"F02" => DATA <= x"20"; when x"F03" => DATA <= x"C8"; when x"F04" => DATA <= x"C3"; when x"F05" => DATA <= x"A5"; when x"F06" => DATA <= x"52"; when x"F07" => DATA <= x"29"; when x"F08" => DATA <= x"03"; when x"F09" => DATA <= x"A8"; when x"F0A" => DATA <= x"B9"; when x"F0B" => DATA <= x"4E"; when x"F0C" => DATA <= x"DF"; when x"F0D" => DATA <= x"8D"; when x"F0E" => DATA <= x"FD"; when x"F0F" => DATA <= x"03"; when x"F10" => DATA <= x"AD"; when x"F11" => DATA <= x"00"; when x"F12" => DATA <= x"B0"; when x"F13" => DATA <= x"29"; when x"F14" => DATA <= x"F0"; when x"F15" => DATA <= x"C9"; when x"F16" => DATA <= x"70"; when x"F17" => DATA <= x"D0"; when x"F18" => DATA <= x"0C"; when x"F19" => DATA <= x"A9"; when x"F1A" => DATA <= x"00"; when x"F1B" => DATA <= x"A8"; when x"F1C" => DATA <= x"99"; when x"F1D" => DATA <= x"00"; when x"F1E" => DATA <= x"86"; when x"F1F" => DATA <= x"99"; when x"F20" => DATA <= x"00"; when x"F21" => DATA <= x"87"; when x"F22" => DATA <= x"88"; when x"F23" => DATA <= x"D0"; when x"F24" => DATA <= x"F7"; when x"F25" => DATA <= x"AD"; when x"F26" => DATA <= x"00"; when x"F27" => DATA <= x"B0"; when x"F28" => DATA <= x"29"; when x"F29" => DATA <= x"DF"; when x"F2A" => DATA <= x"8D"; when x"F2B" => DATA <= x"00"; when x"F2C" => DATA <= x"B0"; when x"F2D" => DATA <= x"2A"; when x"F2E" => DATA <= x"2A"; when x"F2F" => DATA <= x"2A"; when x"F30" => DATA <= x"29"; when x"F31" => DATA <= x"03"; when x"F32" => DATA <= x"A8"; when x"F33" => DATA <= x"B9"; when x"F34" => DATA <= x"42"; when x"F35" => DATA <= x"DF"; when x"F36" => DATA <= x"8D"; when x"F37" => DATA <= x"FE"; when x"F38" => DATA <= x"03"; when x"F39" => DATA <= x"B9"; when x"F3A" => DATA <= x"46"; when x"F3B" => DATA <= x"DF"; when x"F3C" => DATA <= x"8D"; when x"F3D" => DATA <= x"FF"; when x"F3E" => DATA <= x"03"; when x"F3F" => DATA <= x"4C"; when x"F40" => DATA <= x"58"; when x"F41" => DATA <= x"C5"; when x"F42" => DATA <= x"52"; when x"F43" => DATA <= x"70"; when x"F44" => DATA <= x"88"; when x"F45" => DATA <= x"A0"; when x"F46" => DATA <= x"DF"; when x"F47" => DATA <= x"DF"; when x"F48" => DATA <= x"DF"; when x"F49" => DATA <= x"DF"; when x"F4A" => DATA <= x"3F"; when x"F4B" => DATA <= x"CF"; when x"F4C" => DATA <= x"F3"; when x"F4D" => DATA <= x"FC"; when x"F4E" => DATA <= x"00"; when x"F4F" => DATA <= x"55"; when x"F50" => DATA <= x"AA"; when x"F51" => DATA <= x"FF"; when x"F52" => DATA <= x"A5"; when x"F53" => DATA <= x"5B"; when x"F54" => DATA <= x"05"; when x"F55" => DATA <= x"5D"; when x"F56" => DATA <= x"D0"; when x"F57" => DATA <= x"47"; when x"F58" => DATA <= x"A5"; when x"F59" => DATA <= x"5A"; when x"F5A" => DATA <= x"C9"; when x"F5B" => DATA <= x"40"; when x"F5C" => DATA <= x"B0"; when x"F5D" => DATA <= x"41"; when x"F5E" => DATA <= x"4A"; when x"F5F" => DATA <= x"4A"; when x"F60" => DATA <= x"85"; when x"F61" => DATA <= x"5F"; when x"F62" => DATA <= x"A0"; when x"F63" => DATA <= x"00"; when x"F64" => DATA <= x"84"; when x"F65" => DATA <= x"60"; when x"F66" => DATA <= x"A9"; when x"F67" => DATA <= x"3F"; when x"F68" => DATA <= x"38"; when x"F69" => DATA <= x"E5"; when x"F6A" => DATA <= x"5C"; when x"F6B" => DATA <= x"C9"; when x"F6C" => DATA <= x"40"; when x"F6D" => DATA <= x"90"; when x"F6E" => DATA <= x"4F"; when x"F6F" => DATA <= x"60"; when x"F70" => DATA <= x"A5"; when x"F71" => DATA <= x"5B"; when x"F72" => DATA <= x"05"; when x"F73" => DATA <= x"5D"; when x"F74" => DATA <= x"D0"; when x"F75" => DATA <= x"29"; when x"F76" => DATA <= x"A5"; when x"F77" => DATA <= x"5A"; when x"F78" => DATA <= x"30"; when x"F79" => DATA <= x"25"; when x"F7A" => DATA <= x"4A"; when x"F7B" => DATA <= x"4A"; when x"F7C" => DATA <= x"85"; when x"F7D" => DATA <= x"5F"; when x"F7E" => DATA <= x"A9"; when x"F7F" => DATA <= x"3F"; when x"F80" => DATA <= x"38"; when x"F81" => DATA <= x"E5"; when x"F82" => DATA <= x"5C"; when x"F83" => DATA <= x"C9"; when x"F84" => DATA <= x"40"; when x"F85" => DATA <= x"90"; when x"F86" => DATA <= x"30"; when x"F87" => DATA <= x"60"; when x"F88" => DATA <= x"A5"; when x"F89" => DATA <= x"5B"; when x"F8A" => DATA <= x"05"; when x"F8B" => DATA <= x"5D"; when x"F8C" => DATA <= x"D0"; when x"F8D" => DATA <= x"11"; when x"F8E" => DATA <= x"A5"; when x"F8F" => DATA <= x"5A"; when x"F90" => DATA <= x"30"; when x"F91" => DATA <= x"0D"; when x"F92" => DATA <= x"4A"; when x"F93" => DATA <= x"4A"; when x"F94" => DATA <= x"85"; when x"F95" => DATA <= x"5F"; when x"F96" => DATA <= x"A9"; when x"F97" => DATA <= x"5F"; when x"F98" => DATA <= x"38"; when x"F99" => DATA <= x"E5"; when x"F9A" => DATA <= x"5C"; when x"F9B" => DATA <= x"C9"; when x"F9C" => DATA <= x"60"; when x"F9D" => DATA <= x"90"; when x"F9E" => DATA <= x"18"; when x"F9F" => DATA <= x"60"; when x"FA0" => DATA <= x"A5"; when x"FA1" => DATA <= x"5B"; when x"FA2" => DATA <= x"05"; when x"FA3" => DATA <= x"5D"; when x"FA4" => DATA <= x"D0"; when x"FA5" => DATA <= x"F9"; when x"FA6" => DATA <= x"A5"; when x"FA7" => DATA <= x"5A"; when x"FA8" => DATA <= x"30"; when x"FA9" => DATA <= x"F5"; when x"FAA" => DATA <= x"4A"; when x"FAB" => DATA <= x"4A"; when x"FAC" => DATA <= x"85"; when x"FAD" => DATA <= x"5F"; when x"FAE" => DATA <= x"A9"; when x"FAF" => DATA <= x"BF"; when x"FB0" => DATA <= x"38"; when x"FB1" => DATA <= x"E5"; when x"FB2" => DATA <= x"5C"; when x"FB3" => DATA <= x"C9"; when x"FB4" => DATA <= x"C0"; when x"FB5" => DATA <= x"B0"; when x"FB6" => DATA <= x"E8"; when x"FB7" => DATA <= x"A0"; when x"FB8" => DATA <= x"00"; when x"FB9" => DATA <= x"84"; when x"FBA" => DATA <= x"60"; when x"FBB" => DATA <= x"0A"; when x"FBC" => DATA <= x"26"; when x"FBD" => DATA <= x"60"; when x"FBE" => DATA <= x"0A"; when x"FBF" => DATA <= x"26"; when x"FC0" => DATA <= x"60"; when x"FC1" => DATA <= x"0A"; when x"FC2" => DATA <= x"26"; when x"FC3" => DATA <= x"60"; when x"FC4" => DATA <= x"0A"; when x"FC5" => DATA <= x"26"; when x"FC6" => DATA <= x"60"; when x"FC7" => DATA <= x"0A"; when x"FC8" => DATA <= x"26"; when x"FC9" => DATA <= x"60"; when x"FCA" => DATA <= x"65"; when x"FCB" => DATA <= x"5F"; when x"FCC" => DATA <= x"85"; when x"FCD" => DATA <= x"5F"; when x"FCE" => DATA <= x"A5"; when x"FCF" => DATA <= x"60"; when x"FD0" => DATA <= x"69"; when x"FD1" => DATA <= x"80"; when x"FD2" => DATA <= x"85"; when x"FD3" => DATA <= x"60"; when x"FD4" => DATA <= x"A5"; when x"FD5" => DATA <= x"5A"; when x"FD6" => DATA <= x"29"; when x"FD7" => DATA <= x"03"; when x"FD8" => DATA <= x"AA"; when x"FD9" => DATA <= x"BD"; when x"FDA" => DATA <= x"4A"; when x"FDB" => DATA <= x"DF"; when x"FDC" => DATA <= x"A6"; when x"FDD" => DATA <= x"5E"; when x"FDE" => DATA <= x"CA"; when x"FDF" => DATA <= x"F0"; when x"FE0" => DATA <= x"0F"; when x"FE1" => DATA <= x"CA"; when x"FE2" => DATA <= x"F0"; when x"FE3" => DATA <= x"05"; when x"FE4" => DATA <= x"31"; when x"FE5" => DATA <= x"5F"; when x"FE6" => DATA <= x"91"; when x"FE7" => DATA <= x"5F"; when x"FE8" => DATA <= x"60"; when x"FE9" => DATA <= x"49"; when x"FEA" => DATA <= x"FF"; when x"FEB" => DATA <= x"51"; when x"FEC" => DATA <= x"5F"; when x"FED" => DATA <= x"91"; when x"FEE" => DATA <= x"5F"; when x"FEF" => DATA <= x"60"; when x"FF0" => DATA <= x"AA"; when x"FF1" => DATA <= x"31"; when x"FF2" => DATA <= x"5F"; when x"FF3" => DATA <= x"91"; when x"FF4" => DATA <= x"5F"; when x"FF5" => DATA <= x"8A"; when x"FF6" => DATA <= x"49"; when x"FF7" => DATA <= x"FF"; when x"FF8" => DATA <= x"2D"; when x"FF9" => DATA <= x"FD"; when x"FFA" => DATA <= x"03"; when x"FFB" => DATA <= x"11"; when x"FFC" => DATA <= x"5F"; when x"FFD" => DATA <= x"91"; when x"FFE" => DATA <= x"5F"; when x"FFF" => DATA <= x"60"; when others => DATA <= (others => '0'); end case; end process; end RTL;
apache-2.0
49eebdaac33b848a3fdabe7a1ec601c5
0.357929
2.920733
false
false
false
false
hoglet67/AtomFpga
src/common/ROM/kernel_orig.vhd
1
172,874
-- generated with romgen v3.0.1r4 by MikeJ truhy and eD library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; library UNISIM; use UNISIM.Vcomponents.all; entity atomkernal is port ( CLK : in std_logic; ADDR : in std_logic_vector(11 downto 0); DATA : out std_logic_vector(7 downto 0) ); end; architecture RTL of atomkernal is signal rom_addr : std_logic_vector(11 downto 0); begin p_addr : process(ADDR) begin rom_addr <= (others => '0'); rom_addr(11 downto 0) <= ADDR; end process; p_rom : process begin wait until rising_edge(CLK); DATA <= (others => '0'); case rom_addr is when x"000" => DATA <= x"50"; when x"001" => DATA <= x"4C"; when x"002" => DATA <= x"4F"; when x"003" => DATA <= x"54"; when x"004" => DATA <= x"F5"; when x"005" => DATA <= x"4E"; when x"006" => DATA <= x"44"; when x"007" => DATA <= x"52"; when x"008" => DATA <= x"41"; when x"009" => DATA <= x"57"; when x"00A" => DATA <= x"F5"; when x"00B" => DATA <= x"42"; when x"00C" => DATA <= x"4D"; when x"00D" => DATA <= x"4F"; when x"00E" => DATA <= x"56"; when x"00F" => DATA <= x"45"; when x"010" => DATA <= x"F5"; when x"011" => DATA <= x"46"; when x"012" => DATA <= x"43"; when x"013" => DATA <= x"4C"; when x"014" => DATA <= x"45"; when x"015" => DATA <= x"41"; when x"016" => DATA <= x"52"; when x"017" => DATA <= x"F6"; when x"018" => DATA <= x"7B"; when x"019" => DATA <= x"44"; when x"01A" => DATA <= x"49"; when x"01B" => DATA <= x"4D"; when x"01C" => DATA <= x"F0"; when x"01D" => DATA <= x"AE"; when x"01E" => DATA <= x"5B"; when x"01F" => DATA <= x"F2"; when x"020" => DATA <= x"A1"; when x"021" => DATA <= x"4F"; when x"022" => DATA <= x"4C"; when x"023" => DATA <= x"44"; when x"024" => DATA <= x"F5"; when x"025" => DATA <= x"31"; when x"026" => DATA <= x"57"; when x"027" => DATA <= x"41"; when x"028" => DATA <= x"49"; when x"029" => DATA <= x"54"; when x"02A" => DATA <= x"F1"; when x"02B" => DATA <= x"4C"; when x"02C" => DATA <= x"C5"; when x"02D" => DATA <= x"50"; when x"02E" => DATA <= x"A4"; when x"02F" => DATA <= x"5E"; when x"030" => DATA <= x"B1"; when x"031" => DATA <= x"05"; when x"032" => DATA <= x"C9"; when x"033" => DATA <= x"40"; when x"034" => DATA <= x"90"; when x"035" => DATA <= x"12"; when x"036" => DATA <= x"C9"; when x"037" => DATA <= x"5B"; when x"038" => DATA <= x"B0"; when x"039" => DATA <= x"0E"; when x"03A" => DATA <= x"C8"; when x"03B" => DATA <= x"D1"; when x"03C" => DATA <= x"05"; when x"03D" => DATA <= x"D0"; when x"03E" => DATA <= x"09"; when x"03F" => DATA <= x"20"; when x"040" => DATA <= x"8B"; when x"041" => DATA <= x"F0"; when x"042" => DATA <= x"20"; when x"043" => DATA <= x"4F"; when x"044" => DATA <= x"C9"; when x"045" => DATA <= x"4C"; when x"046" => DATA <= x"62"; when x"047" => DATA <= x"C9"; when x"048" => DATA <= x"4C"; when x"049" => DATA <= x"24"; when x"04A" => DATA <= x"CA"; when x"04B" => DATA <= x"A2"; when x"04C" => DATA <= x"FF"; when x"04D" => DATA <= x"A4"; when x"04E" => DATA <= x"5E"; when x"04F" => DATA <= x"C6"; when x"050" => DATA <= x"5E"; when x"051" => DATA <= x"B1"; when x"052" => DATA <= x"05"; when x"053" => DATA <= x"C9"; when x"054" => DATA <= x"40"; when x"055" => DATA <= x"90"; when x"056" => DATA <= x"09"; when x"057" => DATA <= x"C9"; when x"058" => DATA <= x"5B"; when x"059" => DATA <= x"B0"; when x"05A" => DATA <= x"05"; when x"05B" => DATA <= x"C8"; when x"05C" => DATA <= x"D1"; when x"05D" => DATA <= x"05"; when x"05E" => DATA <= x"F0"; when x"05F" => DATA <= x"25"; when x"060" => DATA <= x"A4"; when x"061" => DATA <= x"5E"; when x"062" => DATA <= x"E8"; when x"063" => DATA <= x"C8"; when x"064" => DATA <= x"BD"; when x"065" => DATA <= x"00"; when x"066" => DATA <= x"F0"; when x"067" => DATA <= x"30"; when x"068" => DATA <= x"0C"; when x"069" => DATA <= x"D1"; when x"06A" => DATA <= x"05"; when x"06B" => DATA <= x"F0"; when x"06C" => DATA <= x"F5"; when x"06D" => DATA <= x"E8"; when x"06E" => DATA <= x"BD"; when x"06F" => DATA <= x"FF"; when x"070" => DATA <= x"EF"; when x"071" => DATA <= x"10"; when x"072" => DATA <= x"FA"; when x"073" => DATA <= x"D0"; when x"074" => DATA <= x"EB"; when x"075" => DATA <= x"85"; when x"076" => DATA <= x"53"; when x"077" => DATA <= x"BD"; when x"078" => DATA <= x"01"; when x"079" => DATA <= x"F0"; when x"07A" => DATA <= x"85"; when x"07B" => DATA <= x"52"; when x"07C" => DATA <= x"84"; when x"07D" => DATA <= x"03"; when x"07E" => DATA <= x"A6"; when x"07F" => DATA <= x"04"; when x"080" => DATA <= x"E6"; when x"081" => DATA <= x"5E"; when x"082" => DATA <= x"6C"; when x"083" => DATA <= x"52"; when x"084" => DATA <= x"00"; when x"085" => DATA <= x"20"; when x"086" => DATA <= x"8B"; when x"087" => DATA <= x"F0"; when x"088" => DATA <= x"4C"; when x"089" => DATA <= x"F1"; when x"08A" => DATA <= x"C3"; when x"08B" => DATA <= x"C8"; when x"08C" => DATA <= x"84"; when x"08D" => DATA <= x"03"; when x"08E" => DATA <= x"E9"; when x"08F" => DATA <= x"40"; when x"090" => DATA <= x"48"; when x"091" => DATA <= x"20"; when x"092" => DATA <= x"BC"; when x"093" => DATA <= x"C8"; when x"094" => DATA <= x"68"; when x"095" => DATA <= x"A8"; when x"096" => DATA <= x"B5"; when x"097" => DATA <= x"15"; when x"098" => DATA <= x"0A"; when x"099" => DATA <= x"36"; when x"09A" => DATA <= x"24"; when x"09B" => DATA <= x"0A"; when x"09C" => DATA <= x"36"; when x"09D" => DATA <= x"24"; when x"09E" => DATA <= x"18"; when x"09F" => DATA <= x"79"; when x"0A0" => DATA <= x"EB"; when x"0A1" => DATA <= x"02"; when x"0A2" => DATA <= x"95"; when x"0A3" => DATA <= x"15"; when x"0A4" => DATA <= x"B5"; when x"0A5" => DATA <= x"24"; when x"0A6" => DATA <= x"79"; when x"0A7" => DATA <= x"06"; when x"0A8" => DATA <= x"03"; when x"0A9" => DATA <= x"95"; when x"0AA" => DATA <= x"24"; when x"0AB" => DATA <= x"B0"; when x"0AC" => DATA <= x"D7"; when x"0AD" => DATA <= x"60"; when x"0AE" => DATA <= x"A5"; when x"0AF" => DATA <= x"01"; when x"0B0" => DATA <= x"05"; when x"0B1" => DATA <= x"02"; when x"0B2" => DATA <= x"F0"; when x"0B3" => DATA <= x"22"; when x"0B4" => DATA <= x"20"; when x"0B5" => DATA <= x"34"; when x"0B6" => DATA <= x"C4"; when x"0B7" => DATA <= x"90"; when x"0B8" => DATA <= x"1E"; when x"0B9" => DATA <= x"20"; when x"0BA" => DATA <= x"BC"; when x"0BB" => DATA <= x"C8"; when x"0BC" => DATA <= x"CA"; when x"0BD" => DATA <= x"CA"; when x"0BE" => DATA <= x"86"; when x"0BF" => DATA <= x"04"; when x"0C0" => DATA <= x"B4"; when x"0C1" => DATA <= x"16"; when x"0C2" => DATA <= x"38"; when x"0C3" => DATA <= x"A5"; when x"0C4" => DATA <= x"23"; when x"0C5" => DATA <= x"99"; when x"0C6" => DATA <= x"21"; when x"0C7" => DATA <= x"03"; when x"0C8" => DATA <= x"75"; when x"0C9" => DATA <= x"17"; when x"0CA" => DATA <= x"85"; when x"0CB" => DATA <= x"23"; when x"0CC" => DATA <= x"A5"; when x"0CD" => DATA <= x"24"; when x"0CE" => DATA <= x"99"; when x"0CF" => DATA <= x"3C"; when x"0D0" => DATA <= x"03"; when x"0D1" => DATA <= x"75"; when x"0D2" => DATA <= x"26"; when x"0D3" => DATA <= x"4C"; when x"0D4" => DATA <= x"19"; when x"0D5" => DATA <= x"F1"; when x"0D6" => DATA <= x"00"; when x"0D7" => DATA <= x"A4"; when x"0D8" => DATA <= x"03"; when x"0D9" => DATA <= x"B1"; when x"0DA" => DATA <= x"05"; when x"0DB" => DATA <= x"C9"; when x"0DC" => DATA <= x"40"; when x"0DD" => DATA <= x"90"; when x"0DE" => DATA <= x"F7"; when x"0DF" => DATA <= x"C9"; when x"0E0" => DATA <= x"5B"; when x"0E1" => DATA <= x"B0"; when x"0E2" => DATA <= x"F3"; when x"0E3" => DATA <= x"C8"; when x"0E4" => DATA <= x"D1"; when x"0E5" => DATA <= x"05"; when x"0E6" => DATA <= x"D0"; when x"0E7" => DATA <= x"EE"; when x"0E8" => DATA <= x"E9"; when x"0E9" => DATA <= x"40"; when x"0EA" => DATA <= x"48"; when x"0EB" => DATA <= x"C8"; when x"0EC" => DATA <= x"84"; when x"0ED" => DATA <= x"03"; when x"0EE" => DATA <= x"20"; when x"0EF" => DATA <= x"BC"; when x"0F0" => DATA <= x"C8"; when x"0F1" => DATA <= x"68"; when x"0F2" => DATA <= x"A8"; when x"0F3" => DATA <= x"A5"; when x"0F4" => DATA <= x"23"; when x"0F5" => DATA <= x"99"; when x"0F6" => DATA <= x"EB"; when x"0F7" => DATA <= x"02"; when x"0F8" => DATA <= x"A5"; when x"0F9" => DATA <= x"24"; when x"0FA" => DATA <= x"99"; when x"0FB" => DATA <= x"06"; when x"0FC" => DATA <= x"03"; when x"0FD" => DATA <= x"CA"; when x"0FE" => DATA <= x"86"; when x"0FF" => DATA <= x"04"; when x"100" => DATA <= x"B4"; when x"101" => DATA <= x"16"; when x"102" => DATA <= x"C8"; when x"103" => DATA <= x"D0"; when x"104" => DATA <= x"02"; when x"105" => DATA <= x"F6"; when x"106" => DATA <= x"25"; when x"107" => DATA <= x"98"; when x"108" => DATA <= x"0A"; when x"109" => DATA <= x"36"; when x"10A" => DATA <= x"25"; when x"10B" => DATA <= x"0A"; when x"10C" => DATA <= x"36"; when x"10D" => DATA <= x"25"; when x"10E" => DATA <= x"18"; when x"10F" => DATA <= x"65"; when x"110" => DATA <= x"23"; when x"111" => DATA <= x"85"; when x"112" => DATA <= x"23"; when x"113" => DATA <= x"B5"; when x"114" => DATA <= x"25"; when x"115" => DATA <= x"65"; when x"116" => DATA <= x"24"; when x"117" => DATA <= x"B0"; when x"118" => DATA <= x"BD"; when x"119" => DATA <= x"85"; when x"11A" => DATA <= x"24"; when x"11B" => DATA <= x"A0"; when x"11C" => DATA <= x"00"; when x"11D" => DATA <= x"A9"; when x"11E" => DATA <= x"AA"; when x"11F" => DATA <= x"91"; when x"120" => DATA <= x"23"; when x"121" => DATA <= x"D1"; when x"122" => DATA <= x"23"; when x"123" => DATA <= x"D0"; when x"124" => DATA <= x"F7"; when x"125" => DATA <= x"4A"; when x"126" => DATA <= x"91"; when x"127" => DATA <= x"23"; when x"128" => DATA <= x"D1"; when x"129" => DATA <= x"23"; when x"12A" => DATA <= x"D0"; when x"12B" => DATA <= x"F0"; when x"12C" => DATA <= x"20"; when x"12D" => DATA <= x"34"; when x"12E" => DATA <= x"C4"; when x"12F" => DATA <= x"B0"; when x"130" => DATA <= x"A5"; when x"131" => DATA <= x"A4"; when x"132" => DATA <= x"03"; when x"133" => DATA <= x"B1"; when x"134" => DATA <= x"05"; when x"135" => DATA <= x"C9"; when x"136" => DATA <= x"2C"; when x"137" => DATA <= x"D0"; when x"138" => DATA <= x"05"; when x"139" => DATA <= x"E6"; when x"13A" => DATA <= x"03"; when x"13B" => DATA <= x"4C"; when x"13C" => DATA <= x"AE"; when x"13D" => DATA <= x"F0"; when x"13E" => DATA <= x"4C"; when x"13F" => DATA <= x"58"; when x"140" => DATA <= x"C5"; when x"141" => DATA <= x"A5"; when x"142" => DATA <= x"0D"; when x"143" => DATA <= x"85"; when x"144" => DATA <= x"23"; when x"145" => DATA <= x"A5"; when x"146" => DATA <= x"0E"; when x"147" => DATA <= x"85"; when x"148" => DATA <= x"24"; when x"149" => DATA <= x"4C"; when x"14A" => DATA <= x"83"; when x"14B" => DATA <= x"CE"; when x"14C" => DATA <= x"20"; when x"14D" => DATA <= x"E4"; when x"14E" => DATA <= x"C4"; when x"14F" => DATA <= x"20"; when x"150" => DATA <= x"66"; when x"151" => DATA <= x"FE"; when x"152" => DATA <= x"4C"; when x"153" => DATA <= x"5B"; when x"154" => DATA <= x"C5"; when x"155" => DATA <= x"1C"; when x"156" => DATA <= x"8A"; when x"157" => DATA <= x"1C"; when x"158" => DATA <= x"23"; when x"159" => DATA <= x"5D"; when x"15A" => DATA <= x"8B"; when x"15B" => DATA <= x"1B"; when x"15C" => DATA <= x"A1"; when x"15D" => DATA <= x"9D"; when x"15E" => DATA <= x"8A"; when x"15F" => DATA <= x"1D"; when x"160" => DATA <= x"23"; when x"161" => DATA <= x"9D"; when x"162" => DATA <= x"8B"; when x"163" => DATA <= x"1D"; when x"164" => DATA <= x"A1"; when x"165" => DATA <= x"00"; when x"166" => DATA <= x"29"; when x"167" => DATA <= x"19"; when x"168" => DATA <= x"AE"; when x"169" => DATA <= x"69"; when x"16A" => DATA <= x"A8"; when x"16B" => DATA <= x"19"; when x"16C" => DATA <= x"23"; when x"16D" => DATA <= x"24"; when x"16E" => DATA <= x"53"; when x"16F" => DATA <= x"1B"; when x"170" => DATA <= x"23"; when x"171" => DATA <= x"24"; when x"172" => DATA <= x"53"; when x"173" => DATA <= x"19"; when x"174" => DATA <= x"A1"; when x"175" => DATA <= x"00"; when x"176" => DATA <= x"1A"; when x"177" => DATA <= x"5B"; when x"178" => DATA <= x"5B"; when x"179" => DATA <= x"A5"; when x"17A" => DATA <= x"69"; when x"17B" => DATA <= x"24"; when x"17C" => DATA <= x"24"; when x"17D" => DATA <= x"AE"; when x"17E" => DATA <= x"AE"; when x"17F" => DATA <= x"A8"; when x"180" => DATA <= x"AD"; when x"181" => DATA <= x"29"; when x"182" => DATA <= x"00"; when x"183" => DATA <= x"7C"; when x"184" => DATA <= x"00"; when x"185" => DATA <= x"15"; when x"186" => DATA <= x"9C"; when x"187" => DATA <= x"6D"; when x"188" => DATA <= x"9C"; when x"189" => DATA <= x"A5"; when x"18A" => DATA <= x"69"; when x"18B" => DATA <= x"29"; when x"18C" => DATA <= x"53"; when x"18D" => DATA <= x"84"; when x"18E" => DATA <= x"13"; when x"18F" => DATA <= x"34"; when x"190" => DATA <= x"11"; when x"191" => DATA <= x"A5"; when x"192" => DATA <= x"69"; when x"193" => DATA <= x"23"; when x"194" => DATA <= x"A0"; when x"195" => DATA <= x"D8"; when x"196" => DATA <= x"62"; when x"197" => DATA <= x"5A"; when x"198" => DATA <= x"48"; when x"199" => DATA <= x"26"; when x"19A" => DATA <= x"62"; when x"19B" => DATA <= x"94"; when x"19C" => DATA <= x"88"; when x"19D" => DATA <= x"54"; when x"19E" => DATA <= x"44"; when x"19F" => DATA <= x"C8"; when x"1A0" => DATA <= x"54"; when x"1A1" => DATA <= x"68"; when x"1A2" => DATA <= x"44"; when x"1A3" => DATA <= x"E8"; when x"1A4" => DATA <= x"94"; when x"1A5" => DATA <= x"00"; when x"1A6" => DATA <= x"B4"; when x"1A7" => DATA <= x"08"; when x"1A8" => DATA <= x"84"; when x"1A9" => DATA <= x"74"; when x"1AA" => DATA <= x"B4"; when x"1AB" => DATA <= x"28"; when x"1AC" => DATA <= x"6E"; when x"1AD" => DATA <= x"74"; when x"1AE" => DATA <= x"F4"; when x"1AF" => DATA <= x"CC"; when x"1B0" => DATA <= x"4A"; when x"1B1" => DATA <= x"72"; when x"1B2" => DATA <= x"F2"; when x"1B3" => DATA <= x"A4"; when x"1B4" => DATA <= x"8A"; when x"1B5" => DATA <= x"00"; when x"1B6" => DATA <= x"AA"; when x"1B7" => DATA <= x"A2"; when x"1B8" => DATA <= x"A2"; when x"1B9" => DATA <= x"74"; when x"1BA" => DATA <= x"74"; when x"1BB" => DATA <= x"74"; when x"1BC" => DATA <= x"72"; when x"1BD" => DATA <= x"44"; when x"1BE" => DATA <= x"68"; when x"1BF" => DATA <= x"B2"; when x"1C0" => DATA <= x"32"; when x"1C1" => DATA <= x"B2"; when x"1C2" => DATA <= x"00"; when x"1C3" => DATA <= x"22"; when x"1C4" => DATA <= x"00"; when x"1C5" => DATA <= x"1A"; when x"1C6" => DATA <= x"1A"; when x"1C7" => DATA <= x"26"; when x"1C8" => DATA <= x"26"; when x"1C9" => DATA <= x"72"; when x"1CA" => DATA <= x"72"; when x"1CB" => DATA <= x"88"; when x"1CC" => DATA <= x"C8"; when x"1CD" => DATA <= x"C4"; when x"1CE" => DATA <= x"CA"; when x"1CF" => DATA <= x"26"; when x"1D0" => DATA <= x"48"; when x"1D1" => DATA <= x"44"; when x"1D2" => DATA <= x"44"; when x"1D3" => DATA <= x"A2"; when x"1D4" => DATA <= x"C8"; when x"1D5" => DATA <= x"00"; when x"1D6" => DATA <= x"02"; when x"1D7" => DATA <= x"00"; when x"1D8" => DATA <= x"08"; when x"1D9" => DATA <= x"F2"; when x"1DA" => DATA <= x"FF"; when x"1DB" => DATA <= x"80"; when x"1DC" => DATA <= x"01"; when x"1DD" => DATA <= x"C0"; when x"1DE" => DATA <= x"E2"; when x"1DF" => DATA <= x"C0"; when x"1E0" => DATA <= x"C0"; when x"1E1" => DATA <= x"FF"; when x"1E2" => DATA <= x"00"; when x"1E3" => DATA <= x"00"; when x"1E4" => DATA <= x"08"; when x"1E5" => DATA <= x"00"; when x"1E6" => DATA <= x"10"; when x"1E7" => DATA <= x"80"; when x"1E8" => DATA <= x"40"; when x"1E9" => DATA <= x"C0"; when x"1EA" => DATA <= x"00"; when x"1EB" => DATA <= x"C0"; when x"1EC" => DATA <= x"00"; when x"1ED" => DATA <= x"40"; when x"1EE" => DATA <= x"00"; when x"1EF" => DATA <= x"00"; when x"1F0" => DATA <= x"E4"; when x"1F1" => DATA <= x"20"; when x"1F2" => DATA <= x"80"; when x"1F3" => DATA <= x"00"; when x"1F4" => DATA <= x"FC"; when x"1F5" => DATA <= x"00"; when x"1F6" => DATA <= x"08"; when x"1F7" => DATA <= x"08"; when x"1F8" => DATA <= x"F8"; when x"1F9" => DATA <= x"FC"; when x"1FA" => DATA <= x"F4"; when x"1FB" => DATA <= x"0C"; when x"1FC" => DATA <= x"10"; when x"1FD" => DATA <= x"04"; when x"1FE" => DATA <= x"F4"; when x"1FF" => DATA <= x"00"; when x"200" => DATA <= x"20"; when x"201" => DATA <= x"10"; when x"202" => DATA <= x"00"; when x"203" => DATA <= x"00"; when x"204" => DATA <= x"0F"; when x"205" => DATA <= x"01"; when x"206" => DATA <= x"01"; when x"207" => DATA <= x"01"; when x"208" => DATA <= x"11"; when x"209" => DATA <= x"11"; when x"20A" => DATA <= x"02"; when x"20B" => DATA <= x"02"; when x"20C" => DATA <= x"11"; when x"20D" => DATA <= x"11"; when x"20E" => DATA <= x"02"; when x"20F" => DATA <= x"12"; when x"210" => DATA <= x"02"; when x"211" => DATA <= x"00"; when x"212" => DATA <= x"08"; when x"213" => DATA <= x"10"; when x"214" => DATA <= x"18"; when x"215" => DATA <= x"20"; when x"216" => DATA <= x"28"; when x"217" => DATA <= x"30"; when x"218" => DATA <= x"38"; when x"219" => DATA <= x"40"; when x"21A" => DATA <= x"48"; when x"21B" => DATA <= x"50"; when x"21C" => DATA <= x"58"; when x"21D" => DATA <= x"60"; when x"21E" => DATA <= x"68"; when x"21F" => DATA <= x"70"; when x"220" => DATA <= x"78"; when x"221" => DATA <= x"80"; when x"222" => DATA <= x"88"; when x"223" => DATA <= x"90"; when x"224" => DATA <= x"98"; when x"225" => DATA <= x"A0"; when x"226" => DATA <= x"A8"; when x"227" => DATA <= x"B0"; when x"228" => DATA <= x"B8"; when x"229" => DATA <= x"C0"; when x"22A" => DATA <= x"C8"; when x"22B" => DATA <= x"D0"; when x"22C" => DATA <= x"D8"; when x"22D" => DATA <= x"E0"; when x"22E" => DATA <= x"E8"; when x"22F" => DATA <= x"F0"; when x"230" => DATA <= x"F8"; when x"231" => DATA <= x"0C"; when x"232" => DATA <= x"2C"; when x"233" => DATA <= x"4C"; when x"234" => DATA <= x"4C"; when x"235" => DATA <= x"8C"; when x"236" => DATA <= x"AC"; when x"237" => DATA <= x"CC"; when x"238" => DATA <= x"EC"; when x"239" => DATA <= x"8A"; when x"23A" => DATA <= x"9A"; when x"23B" => DATA <= x"AA"; when x"23C" => DATA <= x"BA"; when x"23D" => DATA <= x"CA"; when x"23E" => DATA <= x"DA"; when x"23F" => DATA <= x"EA"; when x"240" => DATA <= x"FA"; when x"241" => DATA <= x"0E"; when x"242" => DATA <= x"2E"; when x"243" => DATA <= x"4E"; when x"244" => DATA <= x"6E"; when x"245" => DATA <= x"8E"; when x"246" => DATA <= x"AE"; when x"247" => DATA <= x"CE"; when x"248" => DATA <= x"EE"; when x"249" => DATA <= x"0D"; when x"24A" => DATA <= x"2D"; when x"24B" => DATA <= x"4D"; when x"24C" => DATA <= x"6D"; when x"24D" => DATA <= x"8D"; when x"24E" => DATA <= x"AD"; when x"24F" => DATA <= x"CD"; when x"250" => DATA <= x"ED"; when x"251" => DATA <= x"0D"; when x"252" => DATA <= x"0D"; when x"253" => DATA <= x"0C"; when x"254" => DATA <= x"0D"; when x"255" => DATA <= x"0E"; when x"256" => DATA <= x"0D"; when x"257" => DATA <= x"0C"; when x"258" => DATA <= x"0D"; when x"259" => DATA <= x"0D"; when x"25A" => DATA <= x"0D"; when x"25B" => DATA <= x"0C"; when x"25C" => DATA <= x"0D"; when x"25D" => DATA <= x"0D"; when x"25E" => DATA <= x"0D"; when x"25F" => DATA <= x"0C"; when x"260" => DATA <= x"0D"; when x"261" => DATA <= x"0F"; when x"262" => DATA <= x"0D"; when x"263" => DATA <= x"0C"; when x"264" => DATA <= x"0D"; when x"265" => DATA <= x"09"; when x"266" => DATA <= x"0D"; when x"267" => DATA <= x"0C"; when x"268" => DATA <= x"0D"; when x"269" => DATA <= x"08"; when x"26A" => DATA <= x"0D"; when x"26B" => DATA <= x"0C"; when x"26C" => DATA <= x"0D"; when x"26D" => DATA <= x"08"; when x"26E" => DATA <= x"0D"; when x"26F" => DATA <= x"0C"; when x"270" => DATA <= x"0D"; when x"271" => DATA <= x"0F"; when x"272" => DATA <= x"06"; when x"273" => DATA <= x"0B"; when x"274" => DATA <= x"0B"; when x"275" => DATA <= x"04"; when x"276" => DATA <= x"0A"; when x"277" => DATA <= x"08"; when x"278" => DATA <= x"08"; when x"279" => DATA <= x"0D"; when x"27A" => DATA <= x"0D"; when x"27B" => DATA <= x"0D"; when x"27C" => DATA <= x"0D"; when x"27D" => DATA <= x"0D"; when x"27E" => DATA <= x"0F"; when x"27F" => DATA <= x"0D"; when x"280" => DATA <= x"0F"; when x"281" => DATA <= x"07"; when x"282" => DATA <= x"07"; when x"283" => DATA <= x"07"; when x"284" => DATA <= x"07"; when x"285" => DATA <= x"05"; when x"286" => DATA <= x"09"; when x"287" => DATA <= x"03"; when x"288" => DATA <= x"03"; when x"289" => DATA <= x"01"; when x"28A" => DATA <= x"01"; when x"28B" => DATA <= x"01"; when x"28C" => DATA <= x"01"; when x"28D" => DATA <= x"02"; when x"28E" => DATA <= x"01"; when x"28F" => DATA <= x"01"; when x"290" => DATA <= x"01"; when x"291" => DATA <= x"A4"; when x"292" => DATA <= x"03"; when x"293" => DATA <= x"B1"; when x"294" => DATA <= x"05"; when x"295" => DATA <= x"E6"; when x"296" => DATA <= x"03"; when x"297" => DATA <= x"C9"; when x"298" => DATA <= x"20"; when x"299" => DATA <= x"F0"; when x"29A" => DATA <= x"F6"; when x"29B" => DATA <= x"60"; when x"29C" => DATA <= x"E6"; when x"29D" => DATA <= x"03"; when x"29E" => DATA <= x"4C"; when x"29F" => DATA <= x"1B"; when x"2A0" => DATA <= x"C3"; when x"2A1" => DATA <= x"B1"; when x"2A2" => DATA <= x"05"; when x"2A3" => DATA <= x"C9"; when x"2A4" => DATA <= x"5D"; when x"2A5" => DATA <= x"F0"; when x"2A6" => DATA <= x"F5"; when x"2A7" => DATA <= x"20"; when x"2A8" => DATA <= x"F6"; when x"2A9" => DATA <= x"C4"; when x"2AA" => DATA <= x"C6"; when x"2AB" => DATA <= x"03"; when x"2AC" => DATA <= x"20"; when x"2AD" => DATA <= x"8E"; when x"2AE" => DATA <= x"F3"; when x"2AF" => DATA <= x"C6"; when x"2B0" => DATA <= x"03"; when x"2B1" => DATA <= x"A5"; when x"2B2" => DATA <= x"52"; when x"2B3" => DATA <= x"48"; when x"2B4" => DATA <= x"A5"; when x"2B5" => DATA <= x"53"; when x"2B6" => DATA <= x"48"; when x"2B7" => DATA <= x"AD"; when x"2B8" => DATA <= x"21"; when x"2B9" => DATA <= x"03"; when x"2BA" => DATA <= x"48"; when x"2BB" => DATA <= x"A9"; when x"2BC" => DATA <= x"00"; when x"2BD" => DATA <= x"85"; when x"2BE" => DATA <= x"34"; when x"2BF" => DATA <= x"85"; when x"2C0" => DATA <= x"43"; when x"2C1" => DATA <= x"A9"; when x"2C2" => DATA <= x"05"; when x"2C3" => DATA <= x"8D"; when x"2C4" => DATA <= x"21"; when x"2C5" => DATA <= x"03"; when x"2C6" => DATA <= x"A5"; when x"2C7" => DATA <= x"01"; when x"2C8" => DATA <= x"85"; when x"2C9" => DATA <= x"16"; when x"2CA" => DATA <= x"A5"; when x"2CB" => DATA <= x"02"; when x"2CC" => DATA <= x"85"; when x"2CD" => DATA <= x"25"; when x"2CE" => DATA <= x"20"; when x"2CF" => DATA <= x"89"; when x"2D0" => DATA <= x"C5"; when x"2D1" => DATA <= x"20"; when x"2D2" => DATA <= x"79"; when x"2D3" => DATA <= x"F3"; when x"2D4" => DATA <= x"68"; when x"2D5" => DATA <= x"8D"; when x"2D6" => DATA <= x"21"; when x"2D7" => DATA <= x"03"; when x"2D8" => DATA <= x"68"; when x"2D9" => DATA <= x"20"; when x"2DA" => DATA <= x"7E"; when x"2DB" => DATA <= x"F3"; when x"2DC" => DATA <= x"68"; when x"2DD" => DATA <= x"20"; when x"2DE" => DATA <= x"76"; when x"2DF" => DATA <= x"F3"; when x"2E0" => DATA <= x"A0"; when x"2E1" => DATA <= x"00"; when x"2E2" => DATA <= x"C4"; when x"2E3" => DATA <= x"00"; when x"2E4" => DATA <= x"F0"; when x"2E5" => DATA <= x"09"; when x"2E6" => DATA <= x"B9"; when x"2E7" => DATA <= x"66"; when x"2E8" => DATA <= x"00"; when x"2E9" => DATA <= x"20"; when x"2EA" => DATA <= x"76"; when x"2EB" => DATA <= x"F3"; when x"2EC" => DATA <= x"C8"; when x"2ED" => DATA <= x"D0"; when x"2EE" => DATA <= x"F3"; when x"2EF" => DATA <= x"C0"; when x"2F0" => DATA <= x"03"; when x"2F1" => DATA <= x"F0"; when x"2F2" => DATA <= x"0C"; when x"2F3" => DATA <= x"20"; when x"2F4" => DATA <= x"79"; when x"2F5" => DATA <= x"F3"; when x"2F6" => DATA <= x"20"; when x"2F7" => DATA <= x"4C"; when x"2F8" => DATA <= x"CA"; when x"2F9" => DATA <= x"20"; when x"2FA" => DATA <= x"4C"; when x"2FB" => DATA <= x"CA"; when x"2FC" => DATA <= x"C8"; when x"2FD" => DATA <= x"D0"; when x"2FE" => DATA <= x"F0"; when x"2FF" => DATA <= x"A0"; when x"300" => DATA <= x"00"; when x"301" => DATA <= x"B1"; when x"302" => DATA <= x"05"; when x"303" => DATA <= x"C9"; when x"304" => DATA <= x"3B"; when x"305" => DATA <= x"F0"; when x"306" => DATA <= x"0A"; when x"307" => DATA <= x"C9"; when x"308" => DATA <= x"0D"; when x"309" => DATA <= x"F0"; when x"30A" => DATA <= x"06"; when x"30B" => DATA <= x"20"; when x"30C" => DATA <= x"4C"; when x"30D" => DATA <= x"CA"; when x"30E" => DATA <= x"C8"; when x"30F" => DATA <= x"D0"; when x"310" => DATA <= x"F0"; when x"311" => DATA <= x"20"; when x"312" => DATA <= x"54"; when x"313" => DATA <= x"CD"; when x"314" => DATA <= x"20"; when x"315" => DATA <= x"E4"; when x"316" => DATA <= x"C4"; when x"317" => DATA <= x"88"; when x"318" => DATA <= x"B1"; when x"319" => DATA <= x"05"; when x"31A" => DATA <= x"C8"; when x"31B" => DATA <= x"C9"; when x"31C" => DATA <= x"3B"; when x"31D" => DATA <= x"F0"; when x"31E" => DATA <= x"0C"; when x"31F" => DATA <= x"A5"; when x"320" => DATA <= x"06"; when x"321" => DATA <= x"C9"; when x"322" => DATA <= x"01"; when x"323" => DATA <= x"D0"; when x"324" => DATA <= x"03"; when x"325" => DATA <= x"4C"; when x"326" => DATA <= x"CF"; when x"327" => DATA <= x"C2"; when x"328" => DATA <= x"20"; when x"329" => DATA <= x"1D"; when x"32A" => DATA <= x"C5"; when x"32B" => DATA <= x"4C"; when x"32C" => DATA <= x"A1"; when x"32D" => DATA <= x"F2"; when x"32E" => DATA <= x"20"; when x"32F" => DATA <= x"91"; when x"330" => DATA <= x"F2"; when x"331" => DATA <= x"85"; when x"332" => DATA <= x"66"; when x"333" => DATA <= x"20"; when x"334" => DATA <= x"91"; when x"335" => DATA <= x"F2"; when x"336" => DATA <= x"C5"; when x"337" => DATA <= x"66"; when x"338" => DATA <= x"D0"; when x"339" => DATA <= x"10"; when x"33A" => DATA <= x"C9"; when x"33B" => DATA <= x"40"; when x"33C" => DATA <= x"90"; when x"33D" => DATA <= x"0C"; when x"33E" => DATA <= x"C9"; when x"33F" => DATA <= x"5B"; when x"340" => DATA <= x"B0"; when x"341" => DATA <= x"08"; when x"342" => DATA <= x"38"; when x"343" => DATA <= x"20"; when x"344" => DATA <= x"8E"; when x"345" => DATA <= x"F0"; when x"346" => DATA <= x"20"; when x"347" => DATA <= x"CB"; when x"348" => DATA <= x"C3"; when x"349" => DATA <= x"A0"; when x"34A" => DATA <= x"00"; when x"34B" => DATA <= x"AD"; when x"34C" => DATA <= x"31"; when x"34D" => DATA <= x"03"; when x"34E" => DATA <= x"91"; when x"34F" => DATA <= x"52"; when x"350" => DATA <= x"AD"; when x"351" => DATA <= x"4C"; when x"352" => DATA <= x"03"; when x"353" => DATA <= x"C8"; when x"354" => DATA <= x"91"; when x"355" => DATA <= x"52"; when x"356" => DATA <= x"A9"; when x"357" => DATA <= x"00"; when x"358" => DATA <= x"C8"; when x"359" => DATA <= x"91"; when x"35A" => DATA <= x"52"; when x"35B" => DATA <= x"C8"; when x"35C" => DATA <= x"91"; when x"35D" => DATA <= x"52"; when x"35E" => DATA <= x"D0"; when x"35F" => DATA <= x"36"; when x"360" => DATA <= x"20"; when x"361" => DATA <= x"91"; when x"362" => DATA <= x"F2"; when x"363" => DATA <= x"C9"; when x"364" => DATA <= x"3B"; when x"365" => DATA <= x"F0"; when x"366" => DATA <= x"04"; when x"367" => DATA <= x"C9"; when x"368" => DATA <= x"0D"; when x"369" => DATA <= x"D0"; when x"36A" => DATA <= x"F5"; when x"36B" => DATA <= x"AD"; when x"36C" => DATA <= x"31"; when x"36D" => DATA <= x"03"; when x"36E" => DATA <= x"85"; when x"36F" => DATA <= x"52"; when x"370" => DATA <= x"AD"; when x"371" => DATA <= x"4C"; when x"372" => DATA <= x"03"; when x"373" => DATA <= x"85"; when x"374" => DATA <= x"53"; when x"375" => DATA <= x"60"; when x"376" => DATA <= x"20"; when x"377" => DATA <= x"7E"; when x"378" => DATA <= x"F3"; when x"379" => DATA <= x"A9"; when x"37A" => DATA <= x"20"; when x"37B" => DATA <= x"4C"; when x"37C" => DATA <= x"4C"; when x"37D" => DATA <= x"CA"; when x"37E" => DATA <= x"A2"; when x"37F" => DATA <= x"FF"; when x"380" => DATA <= x"48"; when x"381" => DATA <= x"4A"; when x"382" => DATA <= x"4A"; when x"383" => DATA <= x"4A"; when x"384" => DATA <= x"4A"; when x"385" => DATA <= x"20"; when x"386" => DATA <= x"F9"; when x"387" => DATA <= x"C5"; when x"388" => DATA <= x"68"; when x"389" => DATA <= x"29"; when x"38A" => DATA <= x"0F"; when x"38B" => DATA <= x"4C"; when x"38C" => DATA <= x"F9"; when x"38D" => DATA <= x"C5"; when x"38E" => DATA <= x"A2"; when x"38F" => DATA <= x"00"; when x"390" => DATA <= x"86"; when x"391" => DATA <= x"00"; when x"392" => DATA <= x"86"; when x"393" => DATA <= x"64"; when x"394" => DATA <= x"86"; when x"395" => DATA <= x"65"; when x"396" => DATA <= x"20"; when x"397" => DATA <= x"91"; when x"398" => DATA <= x"F2"; when x"399" => DATA <= x"C9"; when x"39A" => DATA <= x"3A"; when x"39B" => DATA <= x"F0"; when x"39C" => DATA <= x"91"; when x"39D" => DATA <= x"C9"; when x"39E" => DATA <= x"3B"; when x"39F" => DATA <= x"F0"; when x"3A0" => DATA <= x"CA"; when x"3A1" => DATA <= x"C9"; when x"3A2" => DATA <= x"0D"; when x"3A3" => DATA <= x"F0"; when x"3A4" => DATA <= x"C6"; when x"3A5" => DATA <= x"C9"; when x"3A6" => DATA <= x"5C"; when x"3A7" => DATA <= x"F0"; when x"3A8" => DATA <= x"B7"; when x"3A9" => DATA <= x"A0"; when x"3AA" => DATA <= x"05"; when x"3AB" => DATA <= x"38"; when x"3AC" => DATA <= x"69"; when x"3AD" => DATA <= x"00"; when x"3AE" => DATA <= x"0A"; when x"3AF" => DATA <= x"0A"; when x"3B0" => DATA <= x"0A"; when x"3B1" => DATA <= x"0A"; when x"3B2" => DATA <= x"26"; when x"3B3" => DATA <= x"6A"; when x"3B4" => DATA <= x"26"; when x"3B5" => DATA <= x"69"; when x"3B6" => DATA <= x"88"; when x"3B7" => DATA <= x"D0"; when x"3B8" => DATA <= x"F8"; when x"3B9" => DATA <= x"E8"; when x"3BA" => DATA <= x"E0"; when x"3BB" => DATA <= x"03"; when x"3BC" => DATA <= x"D0"; when x"3BD" => DATA <= x"D8"; when x"3BE" => DATA <= x"06"; when x"3BF" => DATA <= x"6A"; when x"3C0" => DATA <= x"26"; when x"3C1" => DATA <= x"69"; when x"3C2" => DATA <= x"A2"; when x"3C3" => DATA <= x"40"; when x"3C4" => DATA <= x"A5"; when x"3C5" => DATA <= x"69"; when x"3C6" => DATA <= x"DD"; when x"3C7" => DATA <= x"54"; when x"3C8" => DATA <= x"F1"; when x"3C9" => DATA <= x"F0"; when x"3CA" => DATA <= x"04"; when x"3CB" => DATA <= x"CA"; when x"3CC" => DATA <= x"D0"; when x"3CD" => DATA <= x"F8"; when x"3CE" => DATA <= x"00"; when x"3CF" => DATA <= x"BC"; when x"3D0" => DATA <= x"94"; when x"3D1" => DATA <= x"F1"; when x"3D2" => DATA <= x"C4"; when x"3D3" => DATA <= x"6A"; when x"3D4" => DATA <= x"D0"; when x"3D5" => DATA <= x"F5"; when x"3D6" => DATA <= x"BD"; when x"3D7" => DATA <= x"10"; when x"3D8" => DATA <= x"F2"; when x"3D9" => DATA <= x"85"; when x"3DA" => DATA <= x"66"; when x"3DB" => DATA <= x"BC"; when x"3DC" => DATA <= x"50"; when x"3DD" => DATA <= x"F2"; when x"3DE" => DATA <= x"84"; when x"3DF" => DATA <= x"0F"; when x"3E0" => DATA <= x"66"; when x"3E1" => DATA <= x"64"; when x"3E2" => DATA <= x"66"; when x"3E3" => DATA <= x"65"; when x"3E4" => DATA <= x"88"; when x"3E5" => DATA <= x"D0"; when x"3E6" => DATA <= x"F9"; when x"3E7" => DATA <= x"A4"; when x"3E8" => DATA <= x"0F"; when x"3E9" => DATA <= x"C0"; when x"3EA" => DATA <= x"0D"; when x"3EB" => DATA <= x"D0"; when x"3EC" => DATA <= x"05"; when x"3ED" => DATA <= x"A2"; when x"3EE" => DATA <= x"00"; when x"3EF" => DATA <= x"4C"; when x"3F0" => DATA <= x"9B"; when x"3F1" => DATA <= x"F4"; when x"3F2" => DATA <= x"20"; when x"3F3" => DATA <= x"91"; when x"3F4" => DATA <= x"F2"; when x"3F5" => DATA <= x"C9"; when x"3F6" => DATA <= x"40"; when x"3F7" => DATA <= x"F0"; when x"3F8" => DATA <= x"5B"; when x"3F9" => DATA <= x"C9"; when x"3FA" => DATA <= x"28"; when x"3FB" => DATA <= x"F0"; when x"3FC" => DATA <= x"65"; when x"3FD" => DATA <= x"A2"; when x"3FE" => DATA <= x"01"; when x"3FF" => DATA <= x"C9"; when x"400" => DATA <= x"41"; when x"401" => DATA <= x"F0"; when x"402" => DATA <= x"EC"; when x"403" => DATA <= x"C6"; when x"404" => DATA <= x"03"; when x"405" => DATA <= x"20"; when x"406" => DATA <= x"8B"; when x"407" => DATA <= x"C7"; when x"408" => DATA <= x"20"; when x"409" => DATA <= x"91"; when x"40A" => DATA <= x"F2"; when x"40B" => DATA <= x"C9"; when x"40C" => DATA <= x"2C"; when x"40D" => DATA <= x"D0"; when x"40E" => DATA <= x"31"; when x"40F" => DATA <= x"20"; when x"410" => DATA <= x"91"; when x"411" => DATA <= x"F2"; when x"412" => DATA <= x"A4"; when x"413" => DATA <= x"25"; when x"414" => DATA <= x"F0"; when x"415" => DATA <= x"15"; when x"416" => DATA <= x"A2"; when x"417" => DATA <= x"09"; when x"418" => DATA <= x"C9"; when x"419" => DATA <= x"58"; when x"41A" => DATA <= x"F0"; when x"41B" => DATA <= x"7F"; when x"41C" => DATA <= x"CA"; when x"41D" => DATA <= x"C9"; when x"41E" => DATA <= x"59"; when x"41F" => DATA <= x"D0"; when x"420" => DATA <= x"79"; when x"421" => DATA <= x"A5"; when x"422" => DATA <= x"0F"; when x"423" => DATA <= x"C9"; when x"424" => DATA <= x"09"; when x"425" => DATA <= x"D0"; when x"426" => DATA <= x"74"; when x"427" => DATA <= x"A2"; when x"428" => DATA <= x"0E"; when x"429" => DATA <= x"D0"; when x"42A" => DATA <= x"70"; when x"42B" => DATA <= x"A2"; when x"42C" => DATA <= x"04"; when x"42D" => DATA <= x"C9"; when x"42E" => DATA <= x"58"; when x"42F" => DATA <= x"F0"; when x"430" => DATA <= x"6A"; when x"431" => DATA <= x"C9"; when x"432" => DATA <= x"59"; when x"433" => DATA <= x"D0"; when x"434" => DATA <= x"65"; when x"435" => DATA <= x"CA"; when x"436" => DATA <= x"A4"; when x"437" => DATA <= x"0F"; when x"438" => DATA <= x"C0"; when x"439" => DATA <= x"03"; when x"43A" => DATA <= x"B0"; when x"43B" => DATA <= x"5F"; when x"43C" => DATA <= x"A2"; when x"43D" => DATA <= x"08"; when x"43E" => DATA <= x"D0"; when x"43F" => DATA <= x"5B"; when x"440" => DATA <= x"C6"; when x"441" => DATA <= x"03"; when x"442" => DATA <= x"A2"; when x"443" => DATA <= x"02"; when x"444" => DATA <= x"A4"; when x"445" => DATA <= x"0F"; when x"446" => DATA <= x"C0"; when x"447" => DATA <= x"0C"; when x"448" => DATA <= x"F0"; when x"449" => DATA <= x"51"; when x"44A" => DATA <= x"A2"; when x"44B" => DATA <= x"05"; when x"44C" => DATA <= x"A5"; when x"44D" => DATA <= x"25"; when x"44E" => DATA <= x"F0"; when x"44F" => DATA <= x"4B"; when x"450" => DATA <= x"A2"; when x"451" => DATA <= x"0C"; when x"452" => DATA <= x"D0"; when x"453" => DATA <= x"47"; when x"454" => DATA <= x"20"; when x"455" => DATA <= x"8B"; when x"456" => DATA <= x"C7"; when x"457" => DATA <= x"A5"; when x"458" => DATA <= x"0F"; when x"459" => DATA <= x"A2"; when x"45A" => DATA <= x"06"; when x"45B" => DATA <= x"C9"; when x"45C" => DATA <= x"01"; when x"45D" => DATA <= x"F0"; when x"45E" => DATA <= x"3C"; when x"45F" => DATA <= x"E8"; when x"460" => DATA <= x"D0"; when x"461" => DATA <= x"39"; when x"462" => DATA <= x"20"; when x"463" => DATA <= x"8B"; when x"464" => DATA <= x"C7"; when x"465" => DATA <= x"20"; when x"466" => DATA <= x"91"; when x"467" => DATA <= x"F2"; when x"468" => DATA <= x"C9"; when x"469" => DATA <= x"29"; when x"46A" => DATA <= x"F0"; when x"46B" => DATA <= x"16"; when x"46C" => DATA <= x"C9"; when x"46D" => DATA <= x"2C"; when x"46E" => DATA <= x"D0"; when x"46F" => DATA <= x"2A"; when x"470" => DATA <= x"20"; when x"471" => DATA <= x"91"; when x"472" => DATA <= x"F2"; when x"473" => DATA <= x"C9"; when x"474" => DATA <= x"58"; when x"475" => DATA <= x"D0"; when x"476" => DATA <= x"23"; when x"477" => DATA <= x"20"; when x"478" => DATA <= x"91"; when x"479" => DATA <= x"F2"; when x"47A" => DATA <= x"C9"; when x"47B" => DATA <= x"29"; when x"47C" => DATA <= x"D0"; when x"47D" => DATA <= x"1C"; when x"47E" => DATA <= x"A2"; when x"47F" => DATA <= x"0B"; when x"480" => DATA <= x"D0"; when x"481" => DATA <= x"19"; when x"482" => DATA <= x"A2"; when x"483" => DATA <= x"0D"; when x"484" => DATA <= x"A5"; when x"485" => DATA <= x"0F"; when x"486" => DATA <= x"C9"; when x"487" => DATA <= x"0B"; when x"488" => DATA <= x"F0"; when x"489" => DATA <= x"11"; when x"48A" => DATA <= x"A2"; when x"48B" => DATA <= x"0A"; when x"48C" => DATA <= x"20"; when x"48D" => DATA <= x"91"; when x"48E" => DATA <= x"F2"; when x"48F" => DATA <= x"C9"; when x"490" => DATA <= x"2C"; when x"491" => DATA <= x"D0"; when x"492" => DATA <= x"07"; when x"493" => DATA <= x"20"; when x"494" => DATA <= x"91"; when x"495" => DATA <= x"F2"; when x"496" => DATA <= x"C9"; when x"497" => DATA <= x"59"; when x"498" => DATA <= x"F0"; when x"499" => DATA <= x"01"; when x"49A" => DATA <= x"00"; when x"49B" => DATA <= x"20"; when x"49C" => DATA <= x"60"; when x"49D" => DATA <= x"F3"; when x"49E" => DATA <= x"BD"; when x"49F" => DATA <= x"D5"; when x"4A0" => DATA <= x"F1"; when x"4A1" => DATA <= x"F0"; when x"4A2" => DATA <= x"04"; when x"4A3" => DATA <= x"25"; when x"4A4" => DATA <= x"64"; when x"4A5" => DATA <= x"D0"; when x"4A6" => DATA <= x"07"; when x"4A7" => DATA <= x"BD"; when x"4A8" => DATA <= x"E4"; when x"4A9" => DATA <= x"F1"; when x"4AA" => DATA <= x"25"; when x"4AB" => DATA <= x"65"; when x"4AC" => DATA <= x"F0"; when x"4AD" => DATA <= x"EC"; when x"4AE" => DATA <= x"18"; when x"4AF" => DATA <= x"BD"; when x"4B0" => DATA <= x"F3"; when x"4B1" => DATA <= x"F1"; when x"4B2" => DATA <= x"65"; when x"4B3" => DATA <= x"66"; when x"4B4" => DATA <= x"85"; when x"4B5" => DATA <= x"66"; when x"4B6" => DATA <= x"BD"; when x"4B7" => DATA <= x"02"; when x"4B8" => DATA <= x"F2"; when x"4B9" => DATA <= x"A2"; when x"4BA" => DATA <= x"00"; when x"4BB" => DATA <= x"86"; when x"4BC" => DATA <= x"04"; when x"4BD" => DATA <= x"A4"; when x"4BE" => DATA <= x"16"; when x"4BF" => DATA <= x"84"; when x"4C0" => DATA <= x"67"; when x"4C1" => DATA <= x"A4"; when x"4C2" => DATA <= x"25"; when x"4C3" => DATA <= x"84"; when x"4C4" => DATA <= x"68"; when x"4C5" => DATA <= x"C9"; when x"4C6" => DATA <= x"0F"; when x"4C7" => DATA <= x"F0"; when x"4C8" => DATA <= x"23"; when x"4C9" => DATA <= x"29"; when x"4CA" => DATA <= x"0F"; when x"4CB" => DATA <= x"A8"; when x"4CC" => DATA <= x"C8"; when x"4CD" => DATA <= x"84"; when x"4CE" => DATA <= x"00"; when x"4CF" => DATA <= x"C0"; when x"4D0" => DATA <= x"02"; when x"4D1" => DATA <= x"D0"; when x"4D2" => DATA <= x"04"; when x"4D3" => DATA <= x"A4"; when x"4D4" => DATA <= x"68"; when x"4D5" => DATA <= x"D0"; when x"4D6" => DATA <= x"C3"; when x"4D7" => DATA <= x"A0"; when x"4D8" => DATA <= x"00"; when x"4D9" => DATA <= x"B9"; when x"4DA" => DATA <= x"66"; when x"4DB" => DATA <= x"00"; when x"4DC" => DATA <= x"91"; when x"4DD" => DATA <= x"52"; when x"4DE" => DATA <= x"C8"; when x"4DF" => DATA <= x"EE"; when x"4E0" => DATA <= x"31"; when x"4E1" => DATA <= x"03"; when x"4E2" => DATA <= x"D0"; when x"4E3" => DATA <= x"03"; when x"4E4" => DATA <= x"EE"; when x"4E5" => DATA <= x"4C"; when x"4E6" => DATA <= x"03"; when x"4E7" => DATA <= x"C4"; when x"4E8" => DATA <= x"00"; when x"4E9" => DATA <= x"D0"; when x"4EA" => DATA <= x"EE"; when x"4EB" => DATA <= x"60"; when x"4EC" => DATA <= x"A9"; when x"4ED" => DATA <= x"02"; when x"4EE" => DATA <= x"85"; when x"4EF" => DATA <= x"00"; when x"4F0" => DATA <= x"38"; when x"4F1" => DATA <= x"A5"; when x"4F2" => DATA <= x"67"; when x"4F3" => DATA <= x"ED"; when x"4F4" => DATA <= x"31"; when x"4F5" => DATA <= x"03"; when x"4F6" => DATA <= x"85"; when x"4F7" => DATA <= x"67"; when x"4F8" => DATA <= x"A5"; when x"4F9" => DATA <= x"68"; when x"4FA" => DATA <= x"ED"; when x"4FB" => DATA <= x"4C"; when x"4FC" => DATA <= x"03"; when x"4FD" => DATA <= x"85"; when x"4FE" => DATA <= x"68"; when x"4FF" => DATA <= x"38"; when x"500" => DATA <= x"A5"; when x"501" => DATA <= x"67"; when x"502" => DATA <= x"E9"; when x"503" => DATA <= x"02"; when x"504" => DATA <= x"85"; when x"505" => DATA <= x"67"; when x"506" => DATA <= x"A8"; when x"507" => DATA <= x"A5"; when x"508" => DATA <= x"68"; when x"509" => DATA <= x"E9"; when x"50A" => DATA <= x"00"; when x"50B" => DATA <= x"F0"; when x"50C" => DATA <= x"1F"; when x"50D" => DATA <= x"C9"; when x"50E" => DATA <= x"FF"; when x"50F" => DATA <= x"F0"; when x"510" => DATA <= x"16"; when x"511" => DATA <= x"20"; when x"512" => DATA <= x"D1"; when x"513" => DATA <= x"F7"; when x"514" => DATA <= x"4F"; when x"515" => DATA <= x"55"; when x"516" => DATA <= x"54"; when x"517" => DATA <= x"20"; when x"518" => DATA <= x"4F"; when x"519" => DATA <= x"46"; when x"51A" => DATA <= x"20"; when x"51B" => DATA <= x"52"; when x"51C" => DATA <= x"41"; when x"51D" => DATA <= x"4E"; when x"51E" => DATA <= x"47"; when x"51F" => DATA <= x"45"; when x"520" => DATA <= x"3A"; when x"521" => DATA <= x"0A"; when x"522" => DATA <= x"0D"; when x"523" => DATA <= x"84"; when x"524" => DATA <= x"67"; when x"525" => DATA <= x"30"; when x"526" => DATA <= x"B0"; when x"527" => DATA <= x"98"; when x"528" => DATA <= x"30"; when x"529" => DATA <= x"AD"; when x"52A" => DATA <= x"10"; when x"52B" => DATA <= x"E5"; when x"52C" => DATA <= x"98"; when x"52D" => DATA <= x"10"; when x"52E" => DATA <= x"A8"; when x"52F" => DATA <= x"30"; when x"530" => DATA <= x"E0"; when x"531" => DATA <= x"20"; when x"532" => DATA <= x"E4"; when x"533" => DATA <= x"C4"; when x"534" => DATA <= x"88"; when x"535" => DATA <= x"84"; when x"536" => DATA <= x"52"; when x"537" => DATA <= x"A5"; when x"538" => DATA <= x"12"; when x"539" => DATA <= x"85"; when x"53A" => DATA <= x"53"; when x"53B" => DATA <= x"98"; when x"53C" => DATA <= x"C8"; when x"53D" => DATA <= x"91"; when x"53E" => DATA <= x"52"; when x"53F" => DATA <= x"4C"; when x"540" => DATA <= x"9B"; when x"541" => DATA <= x"CD"; when x"542" => DATA <= x"A2"; when x"543" => DATA <= x"05"; when x"544" => DATA <= x"D0"; when x"545" => DATA <= x"02"; when x"546" => DATA <= x"A2"; when x"547" => DATA <= x"0C"; when x"548" => DATA <= x"86"; when x"549" => DATA <= x"16"; when x"54A" => DATA <= x"E6"; when x"54B" => DATA <= x"04"; when x"54C" => DATA <= x"D0"; when x"54D" => DATA <= x"06"; when x"54E" => DATA <= x"20"; when x"54F" => DATA <= x"BC"; when x"550" => DATA <= x"C8"; when x"551" => DATA <= x"20"; when x"552" => DATA <= x"31"; when x"553" => DATA <= x"C2"; when x"554" => DATA <= x"20"; when x"555" => DATA <= x"BC"; when x"556" => DATA <= x"C8"; when x"557" => DATA <= x"20"; when x"558" => DATA <= x"31"; when x"559" => DATA <= x"C2"; when x"55A" => DATA <= x"20"; when x"55B" => DATA <= x"BC"; when x"55C" => DATA <= x"C8"; when x"55D" => DATA <= x"20"; when x"55E" => DATA <= x"E4"; when x"55F" => DATA <= x"C4"; when x"560" => DATA <= x"B5"; when x"561" => DATA <= x"15"; when x"562" => DATA <= x"85"; when x"563" => DATA <= x"5C"; when x"564" => DATA <= x"B5"; when x"565" => DATA <= x"24"; when x"566" => DATA <= x"85"; when x"567" => DATA <= x"5D"; when x"568" => DATA <= x"B5"; when x"569" => DATA <= x"14"; when x"56A" => DATA <= x"85"; when x"56B" => DATA <= x"5A"; when x"56C" => DATA <= x"B5"; when x"56D" => DATA <= x"23"; when x"56E" => DATA <= x"85"; when x"56F" => DATA <= x"5B"; when x"570" => DATA <= x"A2"; when x"571" => DATA <= x"00"; when x"572" => DATA <= x"86"; when x"573" => DATA <= x"04"; when x"574" => DATA <= x"A2"; when x"575" => DATA <= x"03"; when x"576" => DATA <= x"BD"; when x"577" => DATA <= x"C1"; when x"578" => DATA <= x"03"; when x"579" => DATA <= x"95"; when x"57A" => DATA <= x"52"; when x"57B" => DATA <= x"CA"; when x"57C" => DATA <= x"10"; when x"57D" => DATA <= x"F8"; when x"57E" => DATA <= x"A5"; when x"57F" => DATA <= x"16"; when x"580" => DATA <= x"29"; when x"581" => DATA <= x"04"; when x"582" => DATA <= x"D0"; when x"583" => DATA <= x"13"; when x"584" => DATA <= x"A2"; when x"585" => DATA <= x"02"; when x"586" => DATA <= x"18"; when x"587" => DATA <= x"B5"; when x"588" => DATA <= x"5A"; when x"589" => DATA <= x"75"; when x"58A" => DATA <= x"52"; when x"58B" => DATA <= x"95"; when x"58C" => DATA <= x"5A"; when x"58D" => DATA <= x"B5"; when x"58E" => DATA <= x"5B"; when x"58F" => DATA <= x"75"; when x"590" => DATA <= x"53"; when x"591" => DATA <= x"95"; when x"592" => DATA <= x"5B"; when x"593" => DATA <= x"CA"; when x"594" => DATA <= x"CA"; when x"595" => DATA <= x"10"; when x"596" => DATA <= x"EF"; when x"597" => DATA <= x"A2"; when x"598" => DATA <= x"03"; when x"599" => DATA <= x"B5"; when x"59A" => DATA <= x"5A"; when x"59B" => DATA <= x"9D"; when x"59C" => DATA <= x"C1"; when x"59D" => DATA <= x"03"; when x"59E" => DATA <= x"CA"; when x"59F" => DATA <= x"10"; when x"5A0" => DATA <= x"F8"; when x"5A1" => DATA <= x"A5"; when x"5A2" => DATA <= x"16"; when x"5A3" => DATA <= x"29"; when x"5A4" => DATA <= x"03"; when x"5A5" => DATA <= x"F0"; when x"5A6" => DATA <= x"0B"; when x"5A7" => DATA <= x"85"; when x"5A8" => DATA <= x"5E"; when x"5A9" => DATA <= x"A5"; when x"5AA" => DATA <= x"16"; when x"5AB" => DATA <= x"29"; when x"5AC" => DATA <= x"08"; when x"5AD" => DATA <= x"F0"; when x"5AE" => DATA <= x"06"; when x"5AF" => DATA <= x"20"; when x"5B0" => DATA <= x"78"; when x"5B1" => DATA <= x"F6"; when x"5B2" => DATA <= x"4C"; when x"5B3" => DATA <= x"5B"; when x"5B4" => DATA <= x"C5"; when x"5B5" => DATA <= x"A2"; when x"5B6" => DATA <= x"02"; when x"5B7" => DATA <= x"38"; when x"5B8" => DATA <= x"B5"; when x"5B9" => DATA <= x"5A"; when x"5BA" => DATA <= x"F5"; when x"5BB" => DATA <= x"52"; when x"5BC" => DATA <= x"B4"; when x"5BD" => DATA <= x"52"; when x"5BE" => DATA <= x"94"; when x"5BF" => DATA <= x"5A"; when x"5C0" => DATA <= x"95"; when x"5C1" => DATA <= x"52"; when x"5C2" => DATA <= x"B4"; when x"5C3" => DATA <= x"53"; when x"5C4" => DATA <= x"B5"; when x"5C5" => DATA <= x"5B"; when x"5C6" => DATA <= x"F5"; when x"5C7" => DATA <= x"53"; when x"5C8" => DATA <= x"94"; when x"5C9" => DATA <= x"5B"; when x"5CA" => DATA <= x"95"; when x"5CB" => DATA <= x"53"; when x"5CC" => DATA <= x"95"; when x"5CD" => DATA <= x"56"; when x"5CE" => DATA <= x"10"; when x"5CF" => DATA <= x"0D"; when x"5D0" => DATA <= x"A9"; when x"5D1" => DATA <= x"00"; when x"5D2" => DATA <= x"38"; when x"5D3" => DATA <= x"F5"; when x"5D4" => DATA <= x"52"; when x"5D5" => DATA <= x"95"; when x"5D6" => DATA <= x"52"; when x"5D7" => DATA <= x"A9"; when x"5D8" => DATA <= x"00"; when x"5D9" => DATA <= x"F5"; when x"5DA" => DATA <= x"53"; when x"5DB" => DATA <= x"95"; when x"5DC" => DATA <= x"53"; when x"5DD" => DATA <= x"CA"; when x"5DE" => DATA <= x"CA"; when x"5DF" => DATA <= x"10"; when x"5E0" => DATA <= x"D6"; when x"5E1" => DATA <= x"A5"; when x"5E2" => DATA <= x"54"; when x"5E3" => DATA <= x"C5"; when x"5E4" => DATA <= x"52"; when x"5E5" => DATA <= x"A5"; when x"5E6" => DATA <= x"55"; when x"5E7" => DATA <= x"E5"; when x"5E8" => DATA <= x"53"; when x"5E9" => DATA <= x"90"; when x"5EA" => DATA <= x"31"; when x"5EB" => DATA <= x"A9"; when x"5EC" => DATA <= x"00"; when x"5ED" => DATA <= x"E5"; when x"5EE" => DATA <= x"54"; when x"5EF" => DATA <= x"85"; when x"5F0" => DATA <= x"57"; when x"5F1" => DATA <= x"A9"; when x"5F2" => DATA <= x"00"; when x"5F3" => DATA <= x"E5"; when x"5F4" => DATA <= x"55"; when x"5F5" => DATA <= x"38"; when x"5F6" => DATA <= x"6A"; when x"5F7" => DATA <= x"85"; when x"5F8" => DATA <= x"59"; when x"5F9" => DATA <= x"66"; when x"5FA" => DATA <= x"57"; when x"5FB" => DATA <= x"20"; when x"5FC" => DATA <= x"78"; when x"5FD" => DATA <= x"F6"; when x"5FE" => DATA <= x"A5"; when x"5FF" => DATA <= x"5C"; when x"600" => DATA <= x"CD"; when x"601" => DATA <= x"C3"; when x"602" => DATA <= x"03"; when x"603" => DATA <= x"D0"; when x"604" => DATA <= x"0A"; when x"605" => DATA <= x"A5"; when x"606" => DATA <= x"5D"; when x"607" => DATA <= x"CD"; when x"608" => DATA <= x"C4"; when x"609" => DATA <= x"03"; when x"60A" => DATA <= x"D0"; when x"60B" => DATA <= x"03"; when x"60C" => DATA <= x"4C"; when x"60D" => DATA <= x"5B"; when x"60E" => DATA <= x"C5"; when x"60F" => DATA <= x"20"; when x"610" => DATA <= x"55"; when x"611" => DATA <= x"F6"; when x"612" => DATA <= x"A5"; when x"613" => DATA <= x"59"; when x"614" => DATA <= x"30"; when x"615" => DATA <= x"E5"; when x"616" => DATA <= x"20"; when x"617" => DATA <= x"44"; when x"618" => DATA <= x"F6"; when x"619" => DATA <= x"4C"; when x"61A" => DATA <= x"FB"; when x"61B" => DATA <= x"F5"; when x"61C" => DATA <= x"A5"; when x"61D" => DATA <= x"53"; when x"61E" => DATA <= x"4A"; when x"61F" => DATA <= x"85"; when x"620" => DATA <= x"59"; when x"621" => DATA <= x"A5"; when x"622" => DATA <= x"52"; when x"623" => DATA <= x"6A"; when x"624" => DATA <= x"85"; when x"625" => DATA <= x"57"; when x"626" => DATA <= x"20"; when x"627" => DATA <= x"78"; when x"628" => DATA <= x"F6"; when x"629" => DATA <= x"A5"; when x"62A" => DATA <= x"5A"; when x"62B" => DATA <= x"CD"; when x"62C" => DATA <= x"C1"; when x"62D" => DATA <= x"03"; when x"62E" => DATA <= x"D0"; when x"62F" => DATA <= x"07"; when x"630" => DATA <= x"A5"; when x"631" => DATA <= x"5B"; when x"632" => DATA <= x"CD"; when x"633" => DATA <= x"C2"; when x"634" => DATA <= x"03"; when x"635" => DATA <= x"F0"; when x"636" => DATA <= x"D5"; when x"637" => DATA <= x"20"; when x"638" => DATA <= x"44"; when x"639" => DATA <= x"F6"; when x"63A" => DATA <= x"A5"; when x"63B" => DATA <= x"59"; when x"63C" => DATA <= x"10"; when x"63D" => DATA <= x"E8"; when x"63E" => DATA <= x"20"; when x"63F" => DATA <= x"55"; when x"640" => DATA <= x"F6"; when x"641" => DATA <= x"4C"; when x"642" => DATA <= x"26"; when x"643" => DATA <= x"F6"; when x"644" => DATA <= x"38"; when x"645" => DATA <= x"A5"; when x"646" => DATA <= x"57"; when x"647" => DATA <= x"E5"; when x"648" => DATA <= x"54"; when x"649" => DATA <= x"85"; when x"64A" => DATA <= x"57"; when x"64B" => DATA <= x"A5"; when x"64C" => DATA <= x"59"; when x"64D" => DATA <= x"E5"; when x"64E" => DATA <= x"55"; when x"64F" => DATA <= x"85"; when x"650" => DATA <= x"59"; when x"651" => DATA <= x"A2"; when x"652" => DATA <= x"00"; when x"653" => DATA <= x"F0"; when x"654" => DATA <= x"0F"; when x"655" => DATA <= x"18"; when x"656" => DATA <= x"A5"; when x"657" => DATA <= x"57"; when x"658" => DATA <= x"65"; when x"659" => DATA <= x"52"; when x"65A" => DATA <= x"85"; when x"65B" => DATA <= x"57"; when x"65C" => DATA <= x"A5"; when x"65D" => DATA <= x"59"; when x"65E" => DATA <= x"65"; when x"65F" => DATA <= x"53"; when x"660" => DATA <= x"85"; when x"661" => DATA <= x"59"; when x"662" => DATA <= x"A2"; when x"663" => DATA <= x"02"; when x"664" => DATA <= x"B5"; when x"665" => DATA <= x"56"; when x"666" => DATA <= x"10"; when x"667" => DATA <= x"09"; when x"668" => DATA <= x"B5"; when x"669" => DATA <= x"5A"; when x"66A" => DATA <= x"D0"; when x"66B" => DATA <= x"02"; when x"66C" => DATA <= x"D6"; when x"66D" => DATA <= x"5B"; when x"66E" => DATA <= x"D6"; when x"66F" => DATA <= x"5A"; when x"670" => DATA <= x"60"; when x"671" => DATA <= x"F6"; when x"672" => DATA <= x"5A"; when x"673" => DATA <= x"D0"; when x"674" => DATA <= x"FB"; when x"675" => DATA <= x"F6"; when x"676" => DATA <= x"5B"; when x"677" => DATA <= x"60"; when x"678" => DATA <= x"6C"; when x"679" => DATA <= x"FE"; when x"67A" => DATA <= x"03"; when x"67B" => DATA <= x"20"; when x"67C" => DATA <= x"C8"; when x"67D" => DATA <= x"C3"; when x"67E" => DATA <= x"A0"; when x"67F" => DATA <= x"00"; when x"680" => DATA <= x"A5"; when x"681" => DATA <= x"52"; when x"682" => DATA <= x"F0"; when x"683" => DATA <= x"3E"; when x"684" => DATA <= x"C9"; when x"685" => DATA <= x"05"; when x"686" => DATA <= x"90"; when x"687" => DATA <= x"02"; when x"688" => DATA <= x"A9"; when x"689" => DATA <= x"04"; when x"68A" => DATA <= x"A2"; when x"68B" => DATA <= x"80"; when x"68C" => DATA <= x"86"; when x"68D" => DATA <= x"54"; when x"68E" => DATA <= x"84"; when x"68F" => DATA <= x"53"; when x"690" => DATA <= x"85"; when x"691" => DATA <= x"52"; when x"692" => DATA <= x"AA"; when x"693" => DATA <= x"BD"; when x"694" => DATA <= x"CE"; when x"695" => DATA <= x"F6"; when x"696" => DATA <= x"A6"; when x"697" => DATA <= x"12"; when x"698" => DATA <= x"10"; when x"699" => DATA <= x"04"; when x"69A" => DATA <= x"C5"; when x"69B" => DATA <= x"12"; when x"69C" => DATA <= x"B0"; when x"69D" => DATA <= x"E1"; when x"69E" => DATA <= x"AA"; when x"69F" => DATA <= x"98"; when x"6A0" => DATA <= x"91"; when x"6A1" => DATA <= x"53"; when x"6A2" => DATA <= x"88"; when x"6A3" => DATA <= x"D0"; when x"6A4" => DATA <= x"FB"; when x"6A5" => DATA <= x"E6"; when x"6A6" => DATA <= x"54"; when x"6A7" => DATA <= x"E4"; when x"6A8" => DATA <= x"54"; when x"6A9" => DATA <= x"D0"; when x"6AA" => DATA <= x"F5"; when x"6AB" => DATA <= x"A4"; when x"6AC" => DATA <= x"52"; when x"6AD" => DATA <= x"B9"; when x"6AE" => DATA <= x"D8"; when x"6AF" => DATA <= x"F6"; when x"6B0" => DATA <= x"8D"; when x"6B1" => DATA <= x"FF"; when x"6B2" => DATA <= x"03"; when x"6B3" => DATA <= x"B9"; when x"6B4" => DATA <= x"D3"; when x"6B5" => DATA <= x"F6"; when x"6B6" => DATA <= x"8D"; when x"6B7" => DATA <= x"FE"; when x"6B8" => DATA <= x"03"; when x"6B9" => DATA <= x"B9"; when x"6BA" => DATA <= x"DD"; when x"6BB" => DATA <= x"F6"; when x"6BC" => DATA <= x"8D"; when x"6BD" => DATA <= x"00"; when x"6BE" => DATA <= x"B0"; when x"6BF" => DATA <= x"4C"; when x"6C0" => DATA <= x"58"; when x"6C1" => DATA <= x"C5"; when x"6C2" => DATA <= x"A9"; when x"6C3" => DATA <= x"40"; when x"6C4" => DATA <= x"99"; when x"6C5" => DATA <= x"00"; when x"6C6" => DATA <= x"80"; when x"6C7" => DATA <= x"99"; when x"6C8" => DATA <= x"00"; when x"6C9" => DATA <= x"81"; when x"6CA" => DATA <= x"88"; when x"6CB" => DATA <= x"D0"; when x"6CC" => DATA <= x"F7"; when x"6CD" => DATA <= x"F0"; when x"6CE" => DATA <= x"DC"; when x"6CF" => DATA <= x"84"; when x"6D0" => DATA <= x"86"; when x"6D1" => DATA <= x"8C"; when x"6D2" => DATA <= x"98"; when x"6D3" => DATA <= x"E2"; when x"6D4" => DATA <= x"3B"; when x"6D5" => DATA <= x"54"; when x"6D6" => DATA <= x"6D"; when x"6D7" => DATA <= x"AA"; when x"6D8" => DATA <= x"F6"; when x"6D9" => DATA <= x"F7"; when x"6DA" => DATA <= x"F7"; when x"6DB" => DATA <= x"F7"; when x"6DC" => DATA <= x"F7"; when x"6DD" => DATA <= x"00"; when x"6DE" => DATA <= x"30"; when x"6DF" => DATA <= x"70"; when x"6E0" => DATA <= x"B0"; when x"6E1" => DATA <= x"F0"; when x"6E2" => DATA <= x"A5"; when x"6E3" => DATA <= x"5B"; when x"6E4" => DATA <= x"05"; when x"6E5" => DATA <= x"5D"; when x"6E6" => DATA <= x"D0"; when x"6E7" => DATA <= x"52"; when x"6E8" => DATA <= x"A5"; when x"6E9" => DATA <= x"5A"; when x"6EA" => DATA <= x"C9"; when x"6EB" => DATA <= x"40"; when x"6EC" => DATA <= x"B0"; when x"6ED" => DATA <= x"4C"; when x"6EE" => DATA <= x"4A"; when x"6EF" => DATA <= x"85"; when x"6F0" => DATA <= x"5F"; when x"6F1" => DATA <= x"A9"; when x"6F2" => DATA <= x"2F"; when x"6F3" => DATA <= x"38"; when x"6F4" => DATA <= x"E5"; when x"6F5" => DATA <= x"5C"; when x"6F6" => DATA <= x"C9"; when x"6F7" => DATA <= x"30"; when x"6F8" => DATA <= x"B0"; when x"6F9" => DATA <= x"40"; when x"6FA" => DATA <= x"A2"; when x"6FB" => DATA <= x"FF"; when x"6FC" => DATA <= x"38"; when x"6FD" => DATA <= x"E8"; when x"6FE" => DATA <= x"E9"; when x"6FF" => DATA <= x"03"; when x"700" => DATA <= x"B0"; when x"701" => DATA <= x"FB"; when x"702" => DATA <= x"69"; when x"703" => DATA <= x"03"; when x"704" => DATA <= x"85"; when x"705" => DATA <= x"61"; when x"706" => DATA <= x"8A"; when x"707" => DATA <= x"0A"; when x"708" => DATA <= x"0A"; when x"709" => DATA <= x"0A"; when x"70A" => DATA <= x"0A"; when x"70B" => DATA <= x"0A"; when x"70C" => DATA <= x"05"; when x"70D" => DATA <= x"5F"; when x"70E" => DATA <= x"85"; when x"70F" => DATA <= x"5F"; when x"710" => DATA <= x"A9"; when x"711" => DATA <= x"80"; when x"712" => DATA <= x"69"; when x"713" => DATA <= x"00"; when x"714" => DATA <= x"85"; when x"715" => DATA <= x"60"; when x"716" => DATA <= x"A5"; when x"717" => DATA <= x"5A"; when x"718" => DATA <= x"4A"; when x"719" => DATA <= x"A5"; when x"71A" => DATA <= x"61"; when x"71B" => DATA <= x"2A"; when x"71C" => DATA <= x"A8"; when x"71D" => DATA <= x"B9"; when x"71E" => DATA <= x"CB"; when x"71F" => DATA <= x"F7"; when x"720" => DATA <= x"A0"; when x"721" => DATA <= x"00"; when x"722" => DATA <= x"A6"; when x"723" => DATA <= x"5E"; when x"724" => DATA <= x"CA"; when x"725" => DATA <= x"F0"; when x"726" => DATA <= x"0F"; when x"727" => DATA <= x"CA"; when x"728" => DATA <= x"F0"; when x"729" => DATA <= x"07"; when x"72A" => DATA <= x"49"; when x"72B" => DATA <= x"FF"; when x"72C" => DATA <= x"31"; when x"72D" => DATA <= x"5F"; when x"72E" => DATA <= x"91"; when x"72F" => DATA <= x"5F"; when x"730" => DATA <= x"60"; when x"731" => DATA <= x"51"; when x"732" => DATA <= x"5F"; when x"733" => DATA <= x"91"; when x"734" => DATA <= x"5F"; when x"735" => DATA <= x"60"; when x"736" => DATA <= x"11"; when x"737" => DATA <= x"5F"; when x"738" => DATA <= x"91"; when x"739" => DATA <= x"5F"; when x"73A" => DATA <= x"60"; when x"73B" => DATA <= x"A5"; when x"73C" => DATA <= x"5B"; when x"73D" => DATA <= x"05"; when x"73E" => DATA <= x"5D"; when x"73F" => DATA <= x"D0"; when x"740" => DATA <= x"F9"; when x"741" => DATA <= x"A5"; when x"742" => DATA <= x"5A"; when x"743" => DATA <= x"30"; when x"744" => DATA <= x"F5"; when x"745" => DATA <= x"4A"; when x"746" => DATA <= x"4A"; when x"747" => DATA <= x"4A"; when x"748" => DATA <= x"85"; when x"749" => DATA <= x"5F"; when x"74A" => DATA <= x"A9"; when x"74B" => DATA <= x"3F"; when x"74C" => DATA <= x"38"; when x"74D" => DATA <= x"E5"; when x"74E" => DATA <= x"5C"; when x"74F" => DATA <= x"C9"; when x"750" => DATA <= x"40"; when x"751" => DATA <= x"90"; when x"752" => DATA <= x"32"; when x"753" => DATA <= x"60"; when x"754" => DATA <= x"A5"; when x"755" => DATA <= x"5B"; when x"756" => DATA <= x"05"; when x"757" => DATA <= x"5D"; when x"758" => DATA <= x"D0"; when x"759" => DATA <= x"E0"; when x"75A" => DATA <= x"A5"; when x"75B" => DATA <= x"5A"; when x"75C" => DATA <= x"30"; when x"75D" => DATA <= x"DC"; when x"75E" => DATA <= x"4A"; when x"75F" => DATA <= x"4A"; when x"760" => DATA <= x"4A"; when x"761" => DATA <= x"85"; when x"762" => DATA <= x"5F"; when x"763" => DATA <= x"A9"; when x"764" => DATA <= x"5F"; when x"765" => DATA <= x"38"; when x"766" => DATA <= x"E5"; when x"767" => DATA <= x"5C"; when x"768" => DATA <= x"C9"; when x"769" => DATA <= x"60"; when x"76A" => DATA <= x"90"; when x"76B" => DATA <= x"19"; when x"76C" => DATA <= x"60"; when x"76D" => DATA <= x"A5"; when x"76E" => DATA <= x"5B"; when x"76F" => DATA <= x"05"; when x"770" => DATA <= x"5D"; when x"771" => DATA <= x"D0"; when x"772" => DATA <= x"C7"; when x"773" => DATA <= x"A5"; when x"774" => DATA <= x"5A"; when x"775" => DATA <= x"30"; when x"776" => DATA <= x"C3"; when x"777" => DATA <= x"4A"; when x"778" => DATA <= x"4A"; when x"779" => DATA <= x"4A"; when x"77A" => DATA <= x"85"; when x"77B" => DATA <= x"5F"; when x"77C" => DATA <= x"A9"; when x"77D" => DATA <= x"BF"; when x"77E" => DATA <= x"38"; when x"77F" => DATA <= x"E5"; when x"780" => DATA <= x"5C"; when x"781" => DATA <= x"C9"; when x"782" => DATA <= x"C0"; when x"783" => DATA <= x"B0"; when x"784" => DATA <= x"B5"; when x"785" => DATA <= x"A0"; when x"786" => DATA <= x"00"; when x"787" => DATA <= x"84"; when x"788" => DATA <= x"60"; when x"789" => DATA <= x"0A"; when x"78A" => DATA <= x"26"; when x"78B" => DATA <= x"60"; when x"78C" => DATA <= x"0A"; when x"78D" => DATA <= x"26"; when x"78E" => DATA <= x"60"; when x"78F" => DATA <= x"0A"; when x"790" => DATA <= x"26"; when x"791" => DATA <= x"60"; when x"792" => DATA <= x"0A"; when x"793" => DATA <= x"26"; when x"794" => DATA <= x"60"; when x"795" => DATA <= x"65"; when x"796" => DATA <= x"5F"; when x"797" => DATA <= x"85"; when x"798" => DATA <= x"5F"; when x"799" => DATA <= x"A5"; when x"79A" => DATA <= x"60"; when x"79B" => DATA <= x"69"; when x"79C" => DATA <= x"80"; when x"79D" => DATA <= x"85"; when x"79E" => DATA <= x"60"; when x"79F" => DATA <= x"A5"; when x"7A0" => DATA <= x"5A"; when x"7A1" => DATA <= x"29"; when x"7A2" => DATA <= x"07"; when x"7A3" => DATA <= x"A8"; when x"7A4" => DATA <= x"B9"; when x"7A5" => DATA <= x"C9"; when x"7A6" => DATA <= x"F7"; when x"7A7" => DATA <= x"4C"; when x"7A8" => DATA <= x"20"; when x"7A9" => DATA <= x"F7"; when x"7AA" => DATA <= x"A5"; when x"7AB" => DATA <= x"5B"; when x"7AC" => DATA <= x"05"; when x"7AD" => DATA <= x"5D"; when x"7AE" => DATA <= x"D0"; when x"7AF" => DATA <= x"BC"; when x"7B0" => DATA <= x"A5"; when x"7B1" => DATA <= x"5A"; when x"7B2" => DATA <= x"4A"; when x"7B3" => DATA <= x"4A"; when x"7B4" => DATA <= x"4A"; when x"7B5" => DATA <= x"85"; when x"7B6" => DATA <= x"5F"; when x"7B7" => DATA <= x"A9"; when x"7B8" => DATA <= x"BF"; when x"7B9" => DATA <= x"38"; when x"7BA" => DATA <= x"E5"; when x"7BB" => DATA <= x"5C"; when x"7BC" => DATA <= x"C9"; when x"7BD" => DATA <= x"C0"; when x"7BE" => DATA <= x"B0"; when x"7BF" => DATA <= x"AC"; when x"7C0" => DATA <= x"A0"; when x"7C1" => DATA <= x"00"; when x"7C2" => DATA <= x"84"; when x"7C3" => DATA <= x"60"; when x"7C4" => DATA <= x"0A"; when x"7C5" => DATA <= x"26"; when x"7C6" => DATA <= x"60"; when x"7C7" => DATA <= x"10"; when x"7C8" => DATA <= x"C0"; when x"7C9" => DATA <= x"80"; when x"7CA" => DATA <= x"40"; when x"7CB" => DATA <= x"20"; when x"7CC" => DATA <= x"10"; when x"7CD" => DATA <= x"08"; when x"7CE" => DATA <= x"04"; when x"7CF" => DATA <= x"02"; when x"7D0" => DATA <= x"01"; when x"7D1" => DATA <= x"68"; when x"7D2" => DATA <= x"85"; when x"7D3" => DATA <= x"E8"; when x"7D4" => DATA <= x"68"; when x"7D5" => DATA <= x"85"; when x"7D6" => DATA <= x"E9"; when x"7D7" => DATA <= x"A0"; when x"7D8" => DATA <= x"00"; when x"7D9" => DATA <= x"E6"; when x"7DA" => DATA <= x"E8"; when x"7DB" => DATA <= x"D0"; when x"7DC" => DATA <= x"02"; when x"7DD" => DATA <= x"E6"; when x"7DE" => DATA <= x"E9"; when x"7DF" => DATA <= x"B1"; when x"7E0" => DATA <= x"E8"; when x"7E1" => DATA <= x"30"; when x"7E2" => DATA <= x"06"; when x"7E3" => DATA <= x"20"; when x"7E4" => DATA <= x"F4"; when x"7E5" => DATA <= x"FF"; when x"7E6" => DATA <= x"4C"; when x"7E7" => DATA <= x"D7"; when x"7E8" => DATA <= x"F7"; when x"7E9" => DATA <= x"6C"; when x"7EA" => DATA <= x"E8"; when x"7EB" => DATA <= x"00"; when x"7EC" => DATA <= x"A2"; when x"7ED" => DATA <= x"D4"; when x"7EE" => DATA <= x"20"; when x"7EF" => DATA <= x"F1"; when x"7F0" => DATA <= x"F7"; when x"7F1" => DATA <= x"B5"; when x"7F2" => DATA <= x"01"; when x"7F3" => DATA <= x"20"; when x"7F4" => DATA <= x"02"; when x"7F5" => DATA <= x"F8"; when x"7F6" => DATA <= x"E8"; when x"7F7" => DATA <= x"E8"; when x"7F8" => DATA <= x"B5"; when x"7F9" => DATA <= x"FE"; when x"7FA" => DATA <= x"20"; when x"7FB" => DATA <= x"02"; when x"7FC" => DATA <= x"F8"; when x"7FD" => DATA <= x"A9"; when x"7FE" => DATA <= x"20"; when x"7FF" => DATA <= x"4C"; when x"800" => DATA <= x"F4"; when x"801" => DATA <= x"FF"; when x"802" => DATA <= x"48"; when x"803" => DATA <= x"4A"; when x"804" => DATA <= x"4A"; when x"805" => DATA <= x"4A"; when x"806" => DATA <= x"4A"; when x"807" => DATA <= x"20"; when x"808" => DATA <= x"0B"; when x"809" => DATA <= x"F8"; when x"80A" => DATA <= x"68"; when x"80B" => DATA <= x"29"; when x"80C" => DATA <= x"0F"; when x"80D" => DATA <= x"C9"; when x"80E" => DATA <= x"0A"; when x"80F" => DATA <= x"90"; when x"810" => DATA <= x"02"; when x"811" => DATA <= x"69"; when x"812" => DATA <= x"06"; when x"813" => DATA <= x"69"; when x"814" => DATA <= x"30"; when x"815" => DATA <= x"4C"; when x"816" => DATA <= x"F4"; when x"817" => DATA <= x"FF"; when x"818" => DATA <= x"20"; when x"819" => DATA <= x"76"; when x"81A" => DATA <= x"F8"; when x"81B" => DATA <= x"A2"; when x"81C" => DATA <= x"00"; when x"81D" => DATA <= x"C9"; when x"81E" => DATA <= x"22"; when x"81F" => DATA <= x"F0"; when x"820" => DATA <= x"06"; when x"821" => DATA <= x"E8"; when x"822" => DATA <= x"D0"; when x"823" => DATA <= x"1B"; when x"824" => DATA <= x"4C"; when x"825" => DATA <= x"7D"; when x"826" => DATA <= x"FA"; when x"827" => DATA <= x"C8"; when x"828" => DATA <= x"B9"; when x"829" => DATA <= x"00"; when x"82A" => DATA <= x"01"; when x"82B" => DATA <= x"C9"; when x"82C" => DATA <= x"0D"; when x"82D" => DATA <= x"F0"; when x"82E" => DATA <= x"F5"; when x"82F" => DATA <= x"9D"; when x"830" => DATA <= x"40"; when x"831" => DATA <= x"01"; when x"832" => DATA <= x"E8"; when x"833" => DATA <= x"C9"; when x"834" => DATA <= x"22"; when x"835" => DATA <= x"D0"; when x"836" => DATA <= x"F0"; when x"837" => DATA <= x"C8"; when x"838" => DATA <= x"B9"; when x"839" => DATA <= x"00"; when x"83A" => DATA <= x"01"; when x"83B" => DATA <= x"C9"; when x"83C" => DATA <= x"22"; when x"83D" => DATA <= x"F0"; when x"83E" => DATA <= x"E8"; when x"83F" => DATA <= x"A9"; when x"840" => DATA <= x"0D"; when x"841" => DATA <= x"9D"; when x"842" => DATA <= x"3F"; when x"843" => DATA <= x"01"; when x"844" => DATA <= x"A9"; when x"845" => DATA <= x"40"; when x"846" => DATA <= x"85"; when x"847" => DATA <= x"C9"; when x"848" => DATA <= x"A9"; when x"849" => DATA <= x"01"; when x"84A" => DATA <= x"85"; when x"84B" => DATA <= x"CA"; when x"84C" => DATA <= x"A2"; when x"84D" => DATA <= x"C9"; when x"84E" => DATA <= x"60"; when x"84F" => DATA <= x"A0"; when x"850" => DATA <= x"00"; when x"851" => DATA <= x"B5"; when x"852" => DATA <= x"00"; when x"853" => DATA <= x"99"; when x"854" => DATA <= x"C9"; when x"855" => DATA <= x"00"; when x"856" => DATA <= x"E8"; when x"857" => DATA <= x"C8"; when x"858" => DATA <= x"C0"; when x"859" => DATA <= x"0A"; when x"85A" => DATA <= x"90"; when x"85B" => DATA <= x"F5"; when x"85C" => DATA <= x"A0"; when x"85D" => DATA <= x"FF"; when x"85E" => DATA <= x"A9"; when x"85F" => DATA <= x"0D"; when x"860" => DATA <= x"C8"; when x"861" => DATA <= x"C0"; when x"862" => DATA <= x"0E"; when x"863" => DATA <= x"B0"; when x"864" => DATA <= x"07"; when x"865" => DATA <= x"D1"; when x"866" => DATA <= x"C9"; when x"867" => DATA <= x"D0"; when x"868" => DATA <= x"F7"; when x"869" => DATA <= x"C0"; when x"86A" => DATA <= x"00"; when x"86B" => DATA <= x"60"; when x"86C" => DATA <= x"20"; when x"86D" => DATA <= x"D1"; when x"86E" => DATA <= x"F7"; when x"86F" => DATA <= x"4E"; when x"870" => DATA <= x"41"; when x"871" => DATA <= x"4D"; when x"872" => DATA <= x"45"; when x"873" => DATA <= x"EA"; when x"874" => DATA <= x"00"; when x"875" => DATA <= x"C8"; when x"876" => DATA <= x"B9"; when x"877" => DATA <= x"00"; when x"878" => DATA <= x"01"; when x"879" => DATA <= x"C9"; when x"87A" => DATA <= x"20"; when x"87B" => DATA <= x"F0"; when x"87C" => DATA <= x"F8"; when x"87D" => DATA <= x"60"; when x"87E" => DATA <= x"C9"; when x"87F" => DATA <= x"30"; when x"880" => DATA <= x"90"; when x"881" => DATA <= x"0F"; when x"882" => DATA <= x"C9"; when x"883" => DATA <= x"3A"; when x"884" => DATA <= x"90"; when x"885" => DATA <= x"08"; when x"886" => DATA <= x"E9"; when x"887" => DATA <= x"07"; when x"888" => DATA <= x"90"; when x"889" => DATA <= x"07"; when x"88A" => DATA <= x"C9"; when x"88B" => DATA <= x"40"; when x"88C" => DATA <= x"B0"; when x"88D" => DATA <= x"02"; when x"88E" => DATA <= x"29"; when x"88F" => DATA <= x"0F"; when x"890" => DATA <= x"60"; when x"891" => DATA <= x"38"; when x"892" => DATA <= x"60"; when x"893" => DATA <= x"A9"; when x"894" => DATA <= x"00"; when x"895" => DATA <= x"95"; when x"896" => DATA <= x"00"; when x"897" => DATA <= x"95"; when x"898" => DATA <= x"01"; when x"899" => DATA <= x"95"; when x"89A" => DATA <= x"02"; when x"89B" => DATA <= x"20"; when x"89C" => DATA <= x"76"; when x"89D" => DATA <= x"F8"; when x"89E" => DATA <= x"B9"; when x"89F" => DATA <= x"00"; when x"8A0" => DATA <= x"01"; when x"8A1" => DATA <= x"20"; when x"8A2" => DATA <= x"7E"; when x"8A3" => DATA <= x"F8"; when x"8A4" => DATA <= x"B0"; when x"8A5" => DATA <= x"15"; when x"8A6" => DATA <= x"0A"; when x"8A7" => DATA <= x"0A"; when x"8A8" => DATA <= x"0A"; when x"8A9" => DATA <= x"0A"; when x"8AA" => DATA <= x"94"; when x"8AB" => DATA <= x"02"; when x"8AC" => DATA <= x"A0"; when x"8AD" => DATA <= x"04"; when x"8AE" => DATA <= x"0A"; when x"8AF" => DATA <= x"36"; when x"8B0" => DATA <= x"00"; when x"8B1" => DATA <= x"36"; when x"8B2" => DATA <= x"01"; when x"8B3" => DATA <= x"88"; when x"8B4" => DATA <= x"D0"; when x"8B5" => DATA <= x"F8"; when x"8B6" => DATA <= x"B4"; when x"8B7" => DATA <= x"02"; when x"8B8" => DATA <= x"C8"; when x"8B9" => DATA <= x"D0"; when x"8BA" => DATA <= x"E3"; when x"8BB" => DATA <= x"B5"; when x"8BC" => DATA <= x"02"; when x"8BD" => DATA <= x"60"; when x"8BE" => DATA <= x"43"; when x"8BF" => DATA <= x"41"; when x"8C0" => DATA <= x"54"; when x"8C1" => DATA <= x"FA"; when x"8C2" => DATA <= x"2A"; when x"8C3" => DATA <= x"4C"; when x"8C4" => DATA <= x"4F"; when x"8C5" => DATA <= x"41"; when x"8C6" => DATA <= x"44"; when x"8C7" => DATA <= x"F9"; when x"8C8" => DATA <= x"58"; when x"8C9" => DATA <= x"53"; when x"8CA" => DATA <= x"41"; when x"8CB" => DATA <= x"56"; when x"8CC" => DATA <= x"45"; when x"8CD" => DATA <= x"FA"; when x"8CE" => DATA <= x"BB"; when x"8CF" => DATA <= x"52"; when x"8D0" => DATA <= x"55"; when x"8D1" => DATA <= x"4E"; when x"8D2" => DATA <= x"FA"; when x"8D3" => DATA <= x"20"; when x"8D4" => DATA <= x"4D"; when x"8D5" => DATA <= x"4F"; when x"8D6" => DATA <= x"4E"; when x"8D7" => DATA <= x"FA"; when x"8D8" => DATA <= x"1A"; when x"8D9" => DATA <= x"4E"; when x"8DA" => DATA <= x"4F"; when x"8DB" => DATA <= x"4D"; when x"8DC" => DATA <= x"4F"; when x"8DD" => DATA <= x"4E"; when x"8DE" => DATA <= x"FA"; when x"8DF" => DATA <= x"19"; when x"8E0" => DATA <= x"46"; when x"8E1" => DATA <= x"4C"; when x"8E2" => DATA <= x"4F"; when x"8E3" => DATA <= x"41"; when x"8E4" => DATA <= x"44"; when x"8E5" => DATA <= x"F9"; when x"8E6" => DATA <= x"55"; when x"8E7" => DATA <= x"44"; when x"8E8" => DATA <= x"4F"; when x"8E9" => DATA <= x"53"; when x"8EA" => DATA <= x"0D"; when x"8EB" => DATA <= x"E0"; when x"8EC" => DATA <= x"00"; when x"8ED" => DATA <= x"F9"; when x"8EE" => DATA <= x"26"; when x"8EF" => DATA <= x"A2"; when x"8F0" => DATA <= x"FF"; when x"8F1" => DATA <= x"D8"; when x"8F2" => DATA <= x"A0"; when x"8F3" => DATA <= x"00"; when x"8F4" => DATA <= x"84"; when x"8F5" => DATA <= x"DD"; when x"8F6" => DATA <= x"20"; when x"8F7" => DATA <= x"76"; when x"8F8" => DATA <= x"F8"; when x"8F9" => DATA <= x"88"; when x"8FA" => DATA <= x"C8"; when x"8FB" => DATA <= x"E8"; when x"8FC" => DATA <= x"BD"; when x"8FD" => DATA <= x"BE"; when x"8FE" => DATA <= x"F8"; when x"8FF" => DATA <= x"30"; when x"900" => DATA <= x"18"; when x"901" => DATA <= x"D9"; when x"902" => DATA <= x"00"; when x"903" => DATA <= x"01"; when x"904" => DATA <= x"F0"; when x"905" => DATA <= x"F4"; when x"906" => DATA <= x"CA"; when x"907" => DATA <= x"E8"; when x"908" => DATA <= x"BD"; when x"909" => DATA <= x"BE"; when x"90A" => DATA <= x"F8"; when x"90B" => DATA <= x"10"; when x"90C" => DATA <= x"FA"; when x"90D" => DATA <= x"E8"; when x"90E" => DATA <= x"B9"; when x"90F" => DATA <= x"00"; when x"910" => DATA <= x"01"; when x"911" => DATA <= x"C9"; when x"912" => DATA <= x"2E"; when x"913" => DATA <= x"D0"; when x"914" => DATA <= x"DD"; when x"915" => DATA <= x"C8"; when x"916" => DATA <= x"CA"; when x"917" => DATA <= x"B0"; when x"918" => DATA <= x"E3"; when x"919" => DATA <= x"85"; when x"91A" => DATA <= x"CA"; when x"91B" => DATA <= x"BD"; when x"91C" => DATA <= x"BF"; when x"91D" => DATA <= x"F8"; when x"91E" => DATA <= x"85"; when x"91F" => DATA <= x"C9"; when x"920" => DATA <= x"18"; when x"921" => DATA <= x"A2"; when x"922" => DATA <= x"00"; when x"923" => DATA <= x"6C"; when x"924" => DATA <= x"C9"; when x"925" => DATA <= x"00"; when x"926" => DATA <= x"20"; when x"927" => DATA <= x"D1"; when x"928" => DATA <= x"F7"; when x"929" => DATA <= x"43"; when x"92A" => DATA <= x"4F"; when x"92B" => DATA <= x"4D"; when x"92C" => DATA <= x"3F"; when x"92D" => DATA <= x"EA"; when x"92E" => DATA <= x"00"; when x"92F" => DATA <= x"20"; when x"930" => DATA <= x"8E"; when x"931" => DATA <= x"FB"; when x"932" => DATA <= x"50"; when x"933" => DATA <= x"FA"; when x"934" => DATA <= x"F0"; when x"935" => DATA <= x"F9"; when x"936" => DATA <= x"20"; when x"937" => DATA <= x"2B"; when x"938" => DATA <= x"FC"; when x"939" => DATA <= x"A0"; when x"93A" => DATA <= x"00"; when x"93B" => DATA <= x"20"; when x"93C" => DATA <= x"D4"; when x"93D" => DATA <= x"FF"; when x"93E" => DATA <= x"91"; when x"93F" => DATA <= x"CB"; when x"940" => DATA <= x"E6"; when x"941" => DATA <= x"CB"; when x"942" => DATA <= x"D0"; when x"943" => DATA <= x"02"; when x"944" => DATA <= x"E6"; when x"945" => DATA <= x"CC"; when x"946" => DATA <= x"A2"; when x"947" => DATA <= x"D4"; when x"948" => DATA <= x"20"; when x"949" => DATA <= x"08"; when x"94A" => DATA <= x"FA"; when x"94B" => DATA <= x"D0"; when x"94C" => DATA <= x"EE"; when x"94D" => DATA <= x"38"; when x"94E" => DATA <= x"66"; when x"94F" => DATA <= x"DD"; when x"950" => DATA <= x"18"; when x"951" => DATA <= x"66"; when x"952" => DATA <= x"DD"; when x"953" => DATA <= x"28"; when x"954" => DATA <= x"60"; when x"955" => DATA <= x"38"; when x"956" => DATA <= x"66"; when x"957" => DATA <= x"DD"; when x"958" => DATA <= x"20"; when x"959" => DATA <= x"18"; when x"95A" => DATA <= x"F8"; when x"95B" => DATA <= x"A2"; when x"95C" => DATA <= x"CB"; when x"95D" => DATA <= x"20"; when x"95E" => DATA <= x"93"; when x"95F" => DATA <= x"F8"; when x"960" => DATA <= x"F0"; when x"961" => DATA <= x"04"; when x"962" => DATA <= x"A9"; when x"963" => DATA <= x"FF"; when x"964" => DATA <= x"85"; when x"965" => DATA <= x"CD"; when x"966" => DATA <= x"20"; when x"967" => DATA <= x"76"; when x"968" => DATA <= x"FA"; when x"969" => DATA <= x"A2"; when x"96A" => DATA <= x"C9"; when x"96B" => DATA <= x"6C"; when x"96C" => DATA <= x"0C"; when x"96D" => DATA <= x"02"; when x"96E" => DATA <= x"08"; when x"96F" => DATA <= x"78"; when x"970" => DATA <= x"20"; when x"971" => DATA <= x"4F"; when x"972" => DATA <= x"F8"; when x"973" => DATA <= x"08"; when x"974" => DATA <= x"20"; when x"975" => DATA <= x"3E"; when x"976" => DATA <= x"FC"; when x"977" => DATA <= x"28"; when x"978" => DATA <= x"F0"; when x"979" => DATA <= x"B5"; when x"97A" => DATA <= x"A9"; when x"97B" => DATA <= x"00"; when x"97C" => DATA <= x"85"; when x"97D" => DATA <= x"D0"; when x"97E" => DATA <= x"85"; when x"97F" => DATA <= x"D1"; when x"980" => DATA <= x"20"; when x"981" => DATA <= x"A2"; when x"982" => DATA <= x"F9"; when x"983" => DATA <= x"90"; when x"984" => DATA <= x"C9"; when x"985" => DATA <= x"E6"; when x"986" => DATA <= x"D0"; when x"987" => DATA <= x"E6"; when x"988" => DATA <= x"CC"; when x"989" => DATA <= x"D0"; when x"98A" => DATA <= x"F5"; when x"98B" => DATA <= x"18"; when x"98C" => DATA <= x"90"; when x"98D" => DATA <= x"C0"; when x"98E" => DATA <= x"20"; when x"98F" => DATA <= x"F4"; when x"990" => DATA <= x"FF"; when x"991" => DATA <= x"C8"; when x"992" => DATA <= x"B9"; when x"993" => DATA <= x"ED"; when x"994" => DATA <= x"00"; when x"995" => DATA <= x"C9"; when x"996" => DATA <= x"0D"; when x"997" => DATA <= x"D0"; when x"998" => DATA <= x"F5"; when x"999" => DATA <= x"C8"; when x"99A" => DATA <= x"20"; when x"99B" => DATA <= x"FD"; when x"99C" => DATA <= x"F7"; when x"99D" => DATA <= x"C0"; when x"99E" => DATA <= x"0E"; when x"99F" => DATA <= x"90"; when x"9A0" => DATA <= x"F8"; when x"9A1" => DATA <= x"60"; when x"9A2" => DATA <= x"A9"; when x"9A3" => DATA <= x"00"; when x"9A4" => DATA <= x"85"; when x"9A5" => DATA <= x"DC"; when x"9A6" => DATA <= x"20"; when x"9A7" => DATA <= x"8E"; when x"9A8" => DATA <= x"FB"; when x"9A9" => DATA <= x"50"; when x"9AA" => DATA <= x"F8"; when x"9AB" => DATA <= x"D0"; when x"9AC" => DATA <= x"F5"; when x"9AD" => DATA <= x"20"; when x"9AE" => DATA <= x"C9"; when x"9AF" => DATA <= x"FB"; when x"9B0" => DATA <= x"08"; when x"9B1" => DATA <= x"20"; when x"9B2" => DATA <= x"E2"; when x"9B3" => DATA <= x"FB"; when x"9B4" => DATA <= x"28"; when x"9B5" => DATA <= x"F0"; when x"9B6" => DATA <= x"10"; when x"9B7" => DATA <= x"A5"; when x"9B8" => DATA <= x"DB"; when x"9B9" => DATA <= x"29"; when x"9BA" => DATA <= x"20"; when x"9BB" => DATA <= x"05"; when x"9BC" => DATA <= x"EA"; when x"9BD" => DATA <= x"D0"; when x"9BE" => DATA <= x"E3"; when x"9BF" => DATA <= x"20"; when x"9C0" => DATA <= x"92"; when x"9C1" => DATA <= x"F9"; when x"9C2" => DATA <= x"20"; when x"9C3" => DATA <= x"ED"; when x"9C4" => DATA <= x"FF"; when x"9C5" => DATA <= x"D0"; when x"9C6" => DATA <= x"DB"; when x"9C7" => DATA <= x"A2"; when x"9C8" => DATA <= x"02"; when x"9C9" => DATA <= x"A5"; when x"9CA" => DATA <= x"DD"; when x"9CB" => DATA <= x"30"; when x"9CC" => DATA <= x"13"; when x"9CD" => DATA <= x"B5"; when x"9CE" => DATA <= x"CF"; when x"9CF" => DATA <= x"D5"; when x"9D0" => DATA <= x"D8"; when x"9D1" => DATA <= x"B0"; when x"9D2" => DATA <= x"08"; when x"9D3" => DATA <= x"A9"; when x"9D4" => DATA <= x"05"; when x"9D5" => DATA <= x"20"; when x"9D6" => DATA <= x"40"; when x"9D7" => DATA <= x"FC"; when x"9D8" => DATA <= x"20"; when x"9D9" => DATA <= x"3E"; when x"9DA" => DATA <= x"FC"; when x"9DB" => DATA <= x"D0"; when x"9DC" => DATA <= x"C5"; when x"9DD" => DATA <= x"CA"; when x"9DE" => DATA <= x"D0"; when x"9DF" => DATA <= x"ED"; when x"9E0" => DATA <= x"20"; when x"9E1" => DATA <= x"2B"; when x"9E2" => DATA <= x"FC"; when x"9E3" => DATA <= x"24"; when x"9E4" => DATA <= x"DB"; when x"9E5" => DATA <= x"50"; when x"9E6" => DATA <= x"0B"; when x"9E7" => DATA <= x"88"; when x"9E8" => DATA <= x"C8"; when x"9E9" => DATA <= x"20"; when x"9EA" => DATA <= x"D4"; when x"9EB" => DATA <= x"FF"; when x"9EC" => DATA <= x"91"; when x"9ED" => DATA <= x"CB"; when x"9EE" => DATA <= x"C4"; when x"9EF" => DATA <= x"D8"; when x"9F0" => DATA <= x"D0"; when x"9F1" => DATA <= x"F6"; when x"9F2" => DATA <= x"A5"; when x"9F3" => DATA <= x"DC"; when x"9F4" => DATA <= x"85"; when x"9F5" => DATA <= x"CE"; when x"9F6" => DATA <= x"20"; when x"9F7" => DATA <= x"D4"; when x"9F8" => DATA <= x"FF"; when x"9F9" => DATA <= x"C5"; when x"9FA" => DATA <= x"CE"; when x"9FB" => DATA <= x"F0"; when x"9FC" => DATA <= x"08"; when x"9FD" => DATA <= x"20"; when x"9FE" => DATA <= x"D1"; when x"9FF" => DATA <= x"F7"; when x"A00" => DATA <= x"53"; when x"A01" => DATA <= x"55"; when x"A02" => DATA <= x"4D"; when x"A03" => DATA <= x"EA"; when x"A04" => DATA <= x"00"; when x"A05" => DATA <= x"26"; when x"A06" => DATA <= x"DB"; when x"A07" => DATA <= x"60"; when x"A08" => DATA <= x"F6"; when x"A09" => DATA <= x"00"; when x"A0A" => DATA <= x"D0"; when x"A0B" => DATA <= x"02"; when x"A0C" => DATA <= x"F6"; when x"A0D" => DATA <= x"01"; when x"A0E" => DATA <= x"B5"; when x"A0F" => DATA <= x"00"; when x"A10" => DATA <= x"D5"; when x"A11" => DATA <= x"02"; when x"A12" => DATA <= x"D0"; when x"A13" => DATA <= x"04"; when x"A14" => DATA <= x"B5"; when x"A15" => DATA <= x"01"; when x"A16" => DATA <= x"D5"; when x"A17" => DATA <= x"03"; when x"A18" => DATA <= x"60"; when x"A19" => DATA <= x"CA"; when x"A1A" => DATA <= x"20"; when x"A1B" => DATA <= x"76"; when x"A1C" => DATA <= x"FA"; when x"A1D" => DATA <= x"86"; when x"A1E" => DATA <= x"EA"; when x"A1F" => DATA <= x"60"; when x"A20" => DATA <= x"20"; when x"A21" => DATA <= x"58"; when x"A22" => DATA <= x"F9"; when x"A23" => DATA <= x"24"; when x"A24" => DATA <= x"DD"; when x"A25" => DATA <= x"70"; when x"A26" => DATA <= x"4C"; when x"A27" => DATA <= x"6C"; when x"A28" => DATA <= x"D6"; when x"A29" => DATA <= x"00"; when x"A2A" => DATA <= x"08"; when x"A2B" => DATA <= x"20"; when x"A2C" => DATA <= x"76"; when x"A2D" => DATA <= x"FA"; when x"A2E" => DATA <= x"20"; when x"A2F" => DATA <= x"3E"; when x"A30" => DATA <= x"FC"; when x"A31" => DATA <= x"20"; when x"A32" => DATA <= x"8E"; when x"A33" => DATA <= x"FB"; when x"A34" => DATA <= x"70"; when x"A35" => DATA <= x"02"; when x"A36" => DATA <= x"28"; when x"A37" => DATA <= x"60"; when x"A38" => DATA <= x"F0"; when x"A39" => DATA <= x"0A"; when x"A3A" => DATA <= x"A0"; when x"A3B" => DATA <= x"00"; when x"A3C" => DATA <= x"20"; when x"A3D" => DATA <= x"99"; when x"A3E" => DATA <= x"F9"; when x"A3F" => DATA <= x"20"; when x"A40" => DATA <= x"EC"; when x"A41" => DATA <= x"F7"; when x"A42" => DATA <= x"D0"; when x"A43" => DATA <= x"19"; when x"A44" => DATA <= x"20"; when x"A45" => DATA <= x"C9"; when x"A46" => DATA <= x"FB"; when x"A47" => DATA <= x"20"; when x"A48" => DATA <= x"E2"; when x"A49" => DATA <= x"FB"; when x"A4A" => DATA <= x"20"; when x"A4B" => DATA <= x"92"; when x"A4C" => DATA <= x"F9"; when x"A4D" => DATA <= x"20"; when x"A4E" => DATA <= x"EC"; when x"A4F" => DATA <= x"F7"; when x"A50" => DATA <= x"26"; when x"A51" => DATA <= x"DB"; when x"A52" => DATA <= x"10"; when x"A53" => DATA <= x"09"; when x"A54" => DATA <= x"E8"; when x"A55" => DATA <= x"20"; when x"A56" => DATA <= x"F1"; when x"A57" => DATA <= x"F7"; when x"A58" => DATA <= x"B5"; when x"A59" => DATA <= x"FD"; when x"A5A" => DATA <= x"20"; when x"A5B" => DATA <= x"02"; when x"A5C" => DATA <= x"F8"; when x"A5D" => DATA <= x"20"; when x"A5E" => DATA <= x"ED"; when x"A5F" => DATA <= x"FF"; when x"A60" => DATA <= x"D0"; when x"A61" => DATA <= x"CF"; when x"A62" => DATA <= x"4C"; when x"A63" => DATA <= x"ED"; when x"A64" => DATA <= x"FF"; when x"A65" => DATA <= x"20"; when x"A66" => DATA <= x"93"; when x"A67" => DATA <= x"F8"; when x"A68" => DATA <= x"F0"; when x"A69" => DATA <= x"13"; when x"A6A" => DATA <= x"60"; when x"A6B" => DATA <= x"A2"; when x"A6C" => DATA <= x"CB"; when x"A6D" => DATA <= x"20"; when x"A6E" => DATA <= x"65"; when x"A6F" => DATA <= x"FA"; when x"A70" => DATA <= x"20"; when x"A71" => DATA <= x"76"; when x"A72" => DATA <= x"FA"; when x"A73" => DATA <= x"6C"; when x"A74" => DATA <= x"CB"; when x"A75" => DATA <= x"00"; when x"A76" => DATA <= x"20"; when x"A77" => DATA <= x"76"; when x"A78" => DATA <= x"F8"; when x"A79" => DATA <= x"C9"; when x"A7A" => DATA <= x"0D"; when x"A7B" => DATA <= x"F0"; when x"A7C" => DATA <= x"A2"; when x"A7D" => DATA <= x"20"; when x"A7E" => DATA <= x"D1"; when x"A7F" => DATA <= x"F7"; when x"A80" => DATA <= x"53"; when x"A81" => DATA <= x"59"; when x"A82" => DATA <= x"4E"; when x"A83" => DATA <= x"3F"; when x"A84" => DATA <= x"EA"; when x"A85" => DATA <= x"00"; when x"A86" => DATA <= x"38"; when x"A87" => DATA <= x"A5"; when x"A88" => DATA <= x"D1"; when x"A89" => DATA <= x"E5"; when x"A8A" => DATA <= x"CF"; when x"A8B" => DATA <= x"48"; when x"A8C" => DATA <= x"A5"; when x"A8D" => DATA <= x"D2"; when x"A8E" => DATA <= x"E5"; when x"A8F" => DATA <= x"D0"; when x"A90" => DATA <= x"A8"; when x"A91" => DATA <= x"68"; when x"A92" => DATA <= x"18"; when x"A93" => DATA <= x"65"; when x"A94" => DATA <= x"CB"; when x"A95" => DATA <= x"85"; when x"A96" => DATA <= x"CD"; when x"A97" => DATA <= x"98"; when x"A98" => DATA <= x"65"; when x"A99" => DATA <= x"CC"; when x"A9A" => DATA <= x"85"; when x"A9B" => DATA <= x"CE"; when x"A9C" => DATA <= x"A0"; when x"A9D" => DATA <= x"04"; when x"A9E" => DATA <= x"B9"; when x"A9F" => DATA <= x"CA"; when x"AA0" => DATA <= x"00"; when x"AA1" => DATA <= x"20"; when x"AA2" => DATA <= x"D1"; when x"AA3" => DATA <= x"FF"; when x"AA4" => DATA <= x"88"; when x"AA5" => DATA <= x"D0"; when x"AA6" => DATA <= x"F7"; when x"AA7" => DATA <= x"B1"; when x"AA8" => DATA <= x"CF"; when x"AA9" => DATA <= x"20"; when x"AAA" => DATA <= x"D1"; when x"AAB" => DATA <= x"FF"; when x"AAC" => DATA <= x"E6"; when x"AAD" => DATA <= x"CF"; when x"AAE" => DATA <= x"D0"; when x"AAF" => DATA <= x"02"; when x"AB0" => DATA <= x"E6"; when x"AB1" => DATA <= x"D0"; when x"AB2" => DATA <= x"A2"; when x"AB3" => DATA <= x"CB"; when x"AB4" => DATA <= x"20"; when x"AB5" => DATA <= x"08"; when x"AB6" => DATA <= x"FA"; when x"AB7" => DATA <= x"D0"; when x"AB8" => DATA <= x"EE"; when x"AB9" => DATA <= x"28"; when x"ABA" => DATA <= x"60"; when x"ABB" => DATA <= x"20"; when x"ABC" => DATA <= x"18"; when x"ABD" => DATA <= x"F8"; when x"ABE" => DATA <= x"A2"; when x"ABF" => DATA <= x"CB"; when x"AC0" => DATA <= x"20"; when x"AC1" => DATA <= x"65"; when x"AC2" => DATA <= x"FA"; when x"AC3" => DATA <= x"A2"; when x"AC4" => DATA <= x"D1"; when x"AC5" => DATA <= x"20"; when x"AC6" => DATA <= x"65"; when x"AC7" => DATA <= x"FA"; when x"AC8" => DATA <= x"A2"; when x"AC9" => DATA <= x"CD"; when x"ACA" => DATA <= x"20"; when x"ACB" => DATA <= x"93"; when x"ACC" => DATA <= x"F8"; when x"ACD" => DATA <= x"08"; when x"ACE" => DATA <= x"A5"; when x"ACF" => DATA <= x"CB"; when x"AD0" => DATA <= x"A6"; when x"AD1" => DATA <= x"CC"; when x"AD2" => DATA <= x"28"; when x"AD3" => DATA <= x"D0"; when x"AD4" => DATA <= x"04"; when x"AD5" => DATA <= x"85"; when x"AD6" => DATA <= x"CD"; when x"AD7" => DATA <= x"86"; when x"AD8" => DATA <= x"CE"; when x"AD9" => DATA <= x"85"; when x"ADA" => DATA <= x"CF"; when x"ADB" => DATA <= x"86"; when x"ADC" => DATA <= x"D0"; when x"ADD" => DATA <= x"20"; when x"ADE" => DATA <= x"76"; when x"ADF" => DATA <= x"FA"; when x"AE0" => DATA <= x"A2"; when x"AE1" => DATA <= x"C9"; when x"AE2" => DATA <= x"6C"; when x"AE3" => DATA <= x"0E"; when x"AE4" => DATA <= x"02"; when x"AE5" => DATA <= x"08"; when x"AE6" => DATA <= x"78"; when x"AE7" => DATA <= x"20"; when x"AE8" => DATA <= x"4F"; when x"AE9" => DATA <= x"F8"; when x"AEA" => DATA <= x"08"; when x"AEB" => DATA <= x"A9"; when x"AEC" => DATA <= x"06"; when x"AED" => DATA <= x"20"; when x"AEE" => DATA <= x"40"; when x"AEF" => DATA <= x"FC"; when x"AF0" => DATA <= x"A2"; when x"AF1" => DATA <= x"07"; when x"AF2" => DATA <= x"20"; when x"AF3" => DATA <= x"7A"; when x"AF4" => DATA <= x"FB"; when x"AF5" => DATA <= x"28"; when x"AF6" => DATA <= x"F0"; when x"AF7" => DATA <= x"8E"; when x"AF8" => DATA <= x"A2"; when x"AF9" => DATA <= x"04"; when x"AFA" => DATA <= x"B5"; when x"AFB" => DATA <= x"CE"; when x"AFC" => DATA <= x"95"; when x"AFD" => DATA <= x"D2"; when x"AFE" => DATA <= x"CA"; when x"AFF" => DATA <= x"D0"; when x"B00" => DATA <= x"F9"; when x"B01" => DATA <= x"86"; when x"B02" => DATA <= x"D0"; when x"B03" => DATA <= x"86"; when x"B04" => DATA <= x"D1"; when x"B05" => DATA <= x"A5"; when x"B06" => DATA <= x"D5"; when x"B07" => DATA <= x"D0"; when x"B08" => DATA <= x"02"; when x"B09" => DATA <= x"C6"; when x"B0A" => DATA <= x"D6"; when x"B0B" => DATA <= x"C6"; when x"B0C" => DATA <= x"D5"; when x"B0D" => DATA <= x"18"; when x"B0E" => DATA <= x"66"; when x"B0F" => DATA <= x"D2"; when x"B10" => DATA <= x"38"; when x"B11" => DATA <= x"A2"; when x"B12" => DATA <= x"FF"; when x"B13" => DATA <= x"A5"; when x"B14" => DATA <= x"D5"; when x"B15" => DATA <= x"E5"; when x"B16" => DATA <= x"D3"; when x"B17" => DATA <= x"85"; when x"B18" => DATA <= x"CF"; when x"B19" => DATA <= x"A5"; when x"B1A" => DATA <= x"D6"; when x"B1B" => DATA <= x"E5"; when x"B1C" => DATA <= x"D4"; when x"B1D" => DATA <= x"08"; when x"B1E" => DATA <= x"66"; when x"B1F" => DATA <= x"D2"; when x"B20" => DATA <= x"28"; when x"B21" => DATA <= x"90"; when x"B22" => DATA <= x"06"; when x"B23" => DATA <= x"18"; when x"B24" => DATA <= x"F0"; when x"B25" => DATA <= x"03"; when x"B26" => DATA <= x"86"; when x"B27" => DATA <= x"CF"; when x"B28" => DATA <= x"38"; when x"B29" => DATA <= x"66"; when x"B2A" => DATA <= x"D2"; when x"B2B" => DATA <= x"E8"; when x"B2C" => DATA <= x"20"; when x"B2D" => DATA <= x"3B"; when x"B2E" => DATA <= x"FB"; when x"B2F" => DATA <= x"E6"; when x"B30" => DATA <= x"D0"; when x"B31" => DATA <= x"E6"; when x"B32" => DATA <= x"D4"; when x"B33" => DATA <= x"E6"; when x"B34" => DATA <= x"CC"; when x"B35" => DATA <= x"26"; when x"B36" => DATA <= x"D2"; when x"B37" => DATA <= x"B0"; when x"B38" => DATA <= x"D5"; when x"B39" => DATA <= x"28"; when x"B3A" => DATA <= x"60"; when x"B3B" => DATA <= x"A2"; when x"B3C" => DATA <= x"07"; when x"B3D" => DATA <= x"20"; when x"B3E" => DATA <= x"7A"; when x"B3F" => DATA <= x"FB"; when x"B40" => DATA <= x"86"; when x"B41" => DATA <= x"DC"; when x"B42" => DATA <= x"A0"; when x"B43" => DATA <= x"04"; when x"B44" => DATA <= x"A9"; when x"B45" => DATA <= x"2A"; when x"B46" => DATA <= x"20"; when x"B47" => DATA <= x"D1"; when x"B48" => DATA <= x"FF"; when x"B49" => DATA <= x"88"; when x"B4A" => DATA <= x"D0"; when x"B4B" => DATA <= x"F8"; when x"B4C" => DATA <= x"B1"; when x"B4D" => DATA <= x"C9"; when x"B4E" => DATA <= x"20"; when x"B4F" => DATA <= x"D1"; when x"B50" => DATA <= x"FF"; when x"B51" => DATA <= x"C8"; when x"B52" => DATA <= x"C9"; when x"B53" => DATA <= x"0D"; when x"B54" => DATA <= x"D0"; when x"B55" => DATA <= x"F6"; when x"B56" => DATA <= x"A0"; when x"B57" => DATA <= x"08"; when x"B58" => DATA <= x"B9"; when x"B59" => DATA <= x"CA"; when x"B5A" => DATA <= x"00"; when x"B5B" => DATA <= x"20"; when x"B5C" => DATA <= x"D1"; when x"B5D" => DATA <= x"FF"; when x"B5E" => DATA <= x"88"; when x"B5F" => DATA <= x"D0"; when x"B60" => DATA <= x"F7"; when x"B61" => DATA <= x"20"; when x"B62" => DATA <= x"81"; when x"B63" => DATA <= x"FB"; when x"B64" => DATA <= x"24"; when x"B65" => DATA <= x"D2"; when x"B66" => DATA <= x"50"; when x"B67" => DATA <= x"0B"; when x"B68" => DATA <= x"88"; when x"B69" => DATA <= x"C8"; when x"B6A" => DATA <= x"B1"; when x"B6B" => DATA <= x"D3"; when x"B6C" => DATA <= x"20"; when x"B6D" => DATA <= x"D1"; when x"B6E" => DATA <= x"FF"; when x"B6F" => DATA <= x"C4"; when x"B70" => DATA <= x"CF"; when x"B71" => DATA <= x"D0"; when x"B72" => DATA <= x"F6"; when x"B73" => DATA <= x"A5"; when x"B74" => DATA <= x"DC"; when x"B75" => DATA <= x"20"; when x"B76" => DATA <= x"D1"; when x"B77" => DATA <= x"FF"; when x"B78" => DATA <= x"A2"; when x"B79" => DATA <= x"04"; when x"B7A" => DATA <= x"8E"; when x"B7B" => DATA <= x"02"; when x"B7C" => DATA <= x"B0"; when x"B7D" => DATA <= x"A2"; when x"B7E" => DATA <= x"78"; when x"B7F" => DATA <= x"D0"; when x"B80" => DATA <= x"02"; when x"B81" => DATA <= x"A2"; when x"B82" => DATA <= x"1E"; when x"B83" => DATA <= x"20"; when x"B84" => DATA <= x"66"; when x"B85" => DATA <= x"FE"; when x"B86" => DATA <= x"CA"; when x"B87" => DATA <= x"D0"; when x"B88" => DATA <= x"FA"; when x"B89" => DATA <= x"60"; when x"B8A" => DATA <= x"A2"; when x"B8B" => DATA <= x"06"; when x"B8C" => DATA <= x"D0"; when x"B8D" => DATA <= x"F5"; when x"B8E" => DATA <= x"2C"; when x"B8F" => DATA <= x"01"; when x"B90" => DATA <= x"B0"; when x"B91" => DATA <= x"10"; when x"B92" => DATA <= x"FB"; when x"B93" => DATA <= x"50"; when x"B94" => DATA <= x"F9"; when x"B95" => DATA <= x"A0"; when x"B96" => DATA <= x"00"; when x"B97" => DATA <= x"85"; when x"B98" => DATA <= x"C3"; when x"B99" => DATA <= x"A9"; when x"B9A" => DATA <= x"10"; when x"B9B" => DATA <= x"85"; when x"B9C" => DATA <= x"C2"; when x"B9D" => DATA <= x"2C"; when x"B9E" => DATA <= x"01"; when x"B9F" => DATA <= x"B0"; when x"BA0" => DATA <= x"10"; when x"BA1" => DATA <= x"0F"; when x"BA2" => DATA <= x"50"; when x"BA3" => DATA <= x"0D"; when x"BA4" => DATA <= x"20"; when x"BA5" => DATA <= x"BD"; when x"BA6" => DATA <= x"FC"; when x"BA7" => DATA <= x"B0"; when x"BA8" => DATA <= x"EC"; when x"BA9" => DATA <= x"C6"; when x"BAA" => DATA <= x"C3"; when x"BAB" => DATA <= x"D0"; when x"BAC" => DATA <= x"F0"; when x"BAD" => DATA <= x"C6"; when x"BAE" => DATA <= x"C2"; when x"BAF" => DATA <= x"D0"; when x"BB0" => DATA <= x"EC"; when x"BB1" => DATA <= x"70"; when x"BB2" => DATA <= x"01"; when x"BB3" => DATA <= x"60"; when x"BB4" => DATA <= x"A0"; when x"BB5" => DATA <= x"04"; when x"BB6" => DATA <= x"08"; when x"BB7" => DATA <= x"20"; when x"BB8" => DATA <= x"E4"; when x"BB9" => DATA <= x"FB"; when x"BBA" => DATA <= x"28"; when x"BBB" => DATA <= x"A0"; when x"BBC" => DATA <= x"04"; when x"BBD" => DATA <= x"A9"; when x"BBE" => DATA <= x"2A"; when x"BBF" => DATA <= x"D9"; when x"BC0" => DATA <= x"D3"; when x"BC1" => DATA <= x"00"; when x"BC2" => DATA <= x"D0"; when x"BC3" => DATA <= x"03"; when x"BC4" => DATA <= x"88"; when x"BC5" => DATA <= x"D0"; when x"BC6" => DATA <= x"F8"; when x"BC7" => DATA <= x"60"; when x"BC8" => DATA <= x"C8"; when x"BC9" => DATA <= x"20"; when x"BCA" => DATA <= x"D4"; when x"BCB" => DATA <= x"FF"; when x"BCC" => DATA <= x"99"; when x"BCD" => DATA <= x"ED"; when x"BCE" => DATA <= x"00"; when x"BCF" => DATA <= x"C9"; when x"BD0" => DATA <= x"0D"; when x"BD1" => DATA <= x"D0"; when x"BD2" => DATA <= x"F5"; when x"BD3" => DATA <= x"A0"; when x"BD4" => DATA <= x"FF"; when x"BD5" => DATA <= x"C8"; when x"BD6" => DATA <= x"B1"; when x"BD7" => DATA <= x"C9"; when x"BD8" => DATA <= x"D9"; when x"BD9" => DATA <= x"ED"; when x"BDA" => DATA <= x"00"; when x"BDB" => DATA <= x"D0"; when x"BDC" => DATA <= x"EA"; when x"BDD" => DATA <= x"C9"; when x"BDE" => DATA <= x"0D"; when x"BDF" => DATA <= x"D0"; when x"BE0" => DATA <= x"F4"; when x"BE1" => DATA <= x"60"; when x"BE2" => DATA <= x"A0"; when x"BE3" => DATA <= x"08"; when x"BE4" => DATA <= x"20"; when x"BE5" => DATA <= x"D4"; when x"BE6" => DATA <= x"FF"; when x"BE7" => DATA <= x"99"; when x"BE8" => DATA <= x"D3"; when x"BE9" => DATA <= x"00"; when x"BEA" => DATA <= x"88"; when x"BEB" => DATA <= x"D0"; when x"BEC" => DATA <= x"F7"; when x"BED" => DATA <= x"60"; when x"BEE" => DATA <= x"86"; when x"BEF" => DATA <= x"EC"; when x"BF0" => DATA <= x"84"; when x"BF1" => DATA <= x"C3"; when x"BF2" => DATA <= x"08"; when x"BF3" => DATA <= x"78"; when x"BF4" => DATA <= x"A9"; when x"BF5" => DATA <= x"78"; when x"BF6" => DATA <= x"85"; when x"BF7" => DATA <= x"C0"; when x"BF8" => DATA <= x"20"; when x"BF9" => DATA <= x"BD"; when x"BFA" => DATA <= x"FC"; when x"BFB" => DATA <= x"90"; when x"BFC" => DATA <= x"F7"; when x"BFD" => DATA <= x"E6"; when x"BFE" => DATA <= x"C0"; when x"BFF" => DATA <= x"10"; when x"C00" => DATA <= x"F7"; when x"C01" => DATA <= x"A9"; when x"C02" => DATA <= x"53"; when x"C03" => DATA <= x"85"; when x"C04" => DATA <= x"C4"; when x"C05" => DATA <= x"A2"; when x"C06" => DATA <= x"00"; when x"C07" => DATA <= x"AC"; when x"C08" => DATA <= x"02"; when x"C09" => DATA <= x"B0"; when x"C0A" => DATA <= x"20"; when x"C0B" => DATA <= x"CD"; when x"C0C" => DATA <= x"FC"; when x"C0D" => DATA <= x"F0"; when x"C0E" => DATA <= x"00"; when x"C0F" => DATA <= x"F0"; when x"C10" => DATA <= x"01"; when x"C11" => DATA <= x"E8"; when x"C12" => DATA <= x"C6"; when x"C13" => DATA <= x"C4"; when x"C14" => DATA <= x"D0"; when x"C15" => DATA <= x"F4"; when x"C16" => DATA <= x"E0"; when x"C17" => DATA <= x"0C"; when x"C18" => DATA <= x"66"; when x"C19" => DATA <= x"C0"; when x"C1A" => DATA <= x"90"; when x"C1B" => DATA <= x"E5"; when x"C1C" => DATA <= x"A5"; when x"C1D" => DATA <= x"C0"; when x"C1E" => DATA <= x"28"; when x"C1F" => DATA <= x"A4"; when x"C20" => DATA <= x"C3"; when x"C21" => DATA <= x"A6"; when x"C22" => DATA <= x"EC"; when x"C23" => DATA <= x"48"; when x"C24" => DATA <= x"18"; when x"C25" => DATA <= x"65"; when x"C26" => DATA <= x"DC"; when x"C27" => DATA <= x"85"; when x"C28" => DATA <= x"DC"; when x"C29" => DATA <= x"68"; when x"C2A" => DATA <= x"60"; when x"C2B" => DATA <= x"A5"; when x"C2C" => DATA <= x"CD"; when x"C2D" => DATA <= x"30"; when x"C2E" => DATA <= x"08"; when x"C2F" => DATA <= x"A5"; when x"C30" => DATA <= x"D4"; when x"C31" => DATA <= x"85"; when x"C32" => DATA <= x"CB"; when x"C33" => DATA <= x"A5"; when x"C34" => DATA <= x"D5"; when x"C35" => DATA <= x"85"; when x"C36" => DATA <= x"CC"; when x"C37" => DATA <= x"60"; when x"C38" => DATA <= x"B0"; when x"C39" => DATA <= x"04"; when x"C3A" => DATA <= x"A9"; when x"C3B" => DATA <= x"06"; when x"C3C" => DATA <= x"D0"; when x"C3D" => DATA <= x"02"; when x"C3E" => DATA <= x"A9"; when x"C3F" => DATA <= x"04"; when x"C40" => DATA <= x"A2"; when x"C41" => DATA <= x"07"; when x"C42" => DATA <= x"8E"; when x"C43" => DATA <= x"02"; when x"C44" => DATA <= x"B0"; when x"C45" => DATA <= x"24"; when x"C46" => DATA <= x"EA"; when x"C47" => DATA <= x"D0"; when x"C48" => DATA <= x"2D"; when x"C49" => DATA <= x"C9"; when x"C4A" => DATA <= x"05"; when x"C4B" => DATA <= x"F0"; when x"C4C" => DATA <= x"16"; when x"C4D" => DATA <= x"B0"; when x"C4E" => DATA <= x"09"; when x"C4F" => DATA <= x"20"; when x"C50" => DATA <= x"D1"; when x"C51" => DATA <= x"F7"; when x"C52" => DATA <= x"50"; when x"C53" => DATA <= x"4C"; when x"C54" => DATA <= x"41"; when x"C55" => DATA <= x"59"; when x"C56" => DATA <= x"D0"; when x"C57" => DATA <= x"15"; when x"C58" => DATA <= x"20"; when x"C59" => DATA <= x"D1"; when x"C5A" => DATA <= x"F7"; when x"C5B" => DATA <= x"52"; when x"C5C" => DATA <= x"45"; when x"C5D" => DATA <= x"43"; when x"C5E" => DATA <= x"4F"; when x"C5F" => DATA <= x"52"; when x"C60" => DATA <= x"44"; when x"C61" => DATA <= x"D0"; when x"C62" => DATA <= x"0A"; when x"C63" => DATA <= x"20"; when x"C64" => DATA <= x"D1"; when x"C65" => DATA <= x"F7"; when x"C66" => DATA <= x"52"; when x"C67" => DATA <= x"45"; when x"C68" => DATA <= x"57"; when x"C69" => DATA <= x"49"; when x"C6A" => DATA <= x"4E"; when x"C6B" => DATA <= x"44"; when x"C6C" => DATA <= x"EA"; when x"C6D" => DATA <= x"20"; when x"C6E" => DATA <= x"D1"; when x"C6F" => DATA <= x"F7"; when x"C70" => DATA <= x"20"; when x"C71" => DATA <= x"54"; when x"C72" => DATA <= x"41"; when x"C73" => DATA <= x"50"; when x"C74" => DATA <= x"45"; when x"C75" => DATA <= x"EA"; when x"C76" => DATA <= x"20"; when x"C77" => DATA <= x"E3"; when x"C78" => DATA <= x"FF"; when x"C79" => DATA <= x"4C"; when x"C7A" => DATA <= x"ED"; when x"C7B" => DATA <= x"FF"; when x"C7C" => DATA <= x"86"; when x"C7D" => DATA <= x"EC"; when x"C7E" => DATA <= x"84"; when x"C7F" => DATA <= x"C3"; when x"C80" => DATA <= x"08"; when x"C81" => DATA <= x"78"; when x"C82" => DATA <= x"48"; when x"C83" => DATA <= x"20"; when x"C84" => DATA <= x"23"; when x"C85" => DATA <= x"FC"; when x"C86" => DATA <= x"85"; when x"C87" => DATA <= x"C0"; when x"C88" => DATA <= x"20"; when x"C89" => DATA <= x"D8"; when x"C8A" => DATA <= x"FC"; when x"C8B" => DATA <= x"A9"; when x"C8C" => DATA <= x"0A"; when x"C8D" => DATA <= x"85"; when x"C8E" => DATA <= x"C1"; when x"C8F" => DATA <= x"18"; when x"C90" => DATA <= x"90"; when x"C91" => DATA <= x"0A"; when x"C92" => DATA <= x"A2"; when x"C93" => DATA <= x"07"; when x"C94" => DATA <= x"8E"; when x"C95" => DATA <= x"02"; when x"C96" => DATA <= x"B0"; when x"C97" => DATA <= x"20"; when x"C98" => DATA <= x"DA"; when x"C99" => DATA <= x"FC"; when x"C9A" => DATA <= x"30"; when x"C9B" => DATA <= x"13"; when x"C9C" => DATA <= x"A0"; when x"C9D" => DATA <= x"04"; when x"C9E" => DATA <= x"A9"; when x"C9F" => DATA <= x"04"; when x"CA0" => DATA <= x"8D"; when x"CA1" => DATA <= x"02"; when x"CA2" => DATA <= x"B0"; when x"CA3" => DATA <= x"20"; when x"CA4" => DATA <= x"D8"; when x"CA5" => DATA <= x"FC"; when x"CA6" => DATA <= x"EE"; when x"CA7" => DATA <= x"02"; when x"CA8" => DATA <= x"B0"; when x"CA9" => DATA <= x"20"; when x"CAA" => DATA <= x"D8"; when x"CAB" => DATA <= x"FC"; when x"CAC" => DATA <= x"88"; when x"CAD" => DATA <= x"D0"; when x"CAE" => DATA <= x"EF"; when x"CAF" => DATA <= x"38"; when x"CB0" => DATA <= x"66"; when x"CB1" => DATA <= x"C0"; when x"CB2" => DATA <= x"C6"; when x"CB3" => DATA <= x"C1"; when x"CB4" => DATA <= x"D0"; when x"CB5" => DATA <= x"DA"; when x"CB6" => DATA <= x"A4"; when x"CB7" => DATA <= x"C3"; when x"CB8" => DATA <= x"A6"; when x"CB9" => DATA <= x"EC"; when x"CBA" => DATA <= x"68"; when x"CBB" => DATA <= x"28"; when x"CBC" => DATA <= x"60"; when x"CBD" => DATA <= x"A2"; when x"CBE" => DATA <= x"00"; when x"CBF" => DATA <= x"AC"; when x"CC0" => DATA <= x"02"; when x"CC1" => DATA <= x"B0"; when x"CC2" => DATA <= x"E8"; when x"CC3" => DATA <= x"F0"; when x"CC4" => DATA <= x"07"; when x"CC5" => DATA <= x"20"; when x"CC6" => DATA <= x"CD"; when x"CC7" => DATA <= x"FC"; when x"CC8" => DATA <= x"F0"; when x"CC9" => DATA <= x"F8"; when x"CCA" => DATA <= x"E0"; when x"CCB" => DATA <= x"08"; when x"CCC" => DATA <= x"60"; when x"CCD" => DATA <= x"84"; when x"CCE" => DATA <= x"C5"; when x"CCF" => DATA <= x"AD"; when x"CD0" => DATA <= x"02"; when x"CD1" => DATA <= x"B0"; when x"CD2" => DATA <= x"A8"; when x"CD3" => DATA <= x"45"; when x"CD4" => DATA <= x"C5"; when x"CD5" => DATA <= x"29"; when x"CD6" => DATA <= x"20"; when x"CD7" => DATA <= x"60"; when x"CD8" => DATA <= x"A2"; when x"CD9" => DATA <= x"00"; when x"CDA" => DATA <= x"A9"; when x"CDB" => DATA <= x"10"; when x"CDC" => DATA <= x"2C"; when x"CDD" => DATA <= x"02"; when x"CDE" => DATA <= x"B0"; when x"CDF" => DATA <= x"F0"; when x"CE0" => DATA <= x"FB"; when x"CE1" => DATA <= x"2C"; when x"CE2" => DATA <= x"02"; when x"CE3" => DATA <= x"B0"; when x"CE4" => DATA <= x"D0"; when x"CE5" => DATA <= x"FB"; when x"CE6" => DATA <= x"CA"; when x"CE7" => DATA <= x"10"; when x"CE8" => DATA <= x"F3"; when x"CE9" => DATA <= x"60"; when x"CEA" => DATA <= x"C9"; when x"CEB" => DATA <= x"06"; when x"CEC" => DATA <= x"F0"; when x"CED" => DATA <= x"1D"; when x"CEE" => DATA <= x"C9"; when x"CEF" => DATA <= x"15"; when x"CF0" => DATA <= x"F0"; when x"CF1" => DATA <= x"1F"; when x"CF2" => DATA <= x"A4"; when x"CF3" => DATA <= x"E0"; when x"CF4" => DATA <= x"30"; when x"CF5" => DATA <= x"23"; when x"CF6" => DATA <= x"C9"; when x"CF7" => DATA <= x"1B"; when x"CF8" => DATA <= x"F0"; when x"CF9" => DATA <= x"11"; when x"CFA" => DATA <= x"C9"; when x"CFB" => DATA <= x"07"; when x"CFC" => DATA <= x"F0"; when x"CFD" => DATA <= x"1C"; when x"CFE" => DATA <= x"20"; when x"CFF" => DATA <= x"44"; when x"D00" => DATA <= x"FD"; when x"D01" => DATA <= x"A2"; when x"D02" => DATA <= x"0A"; when x"D03" => DATA <= x"20"; when x"D04" => DATA <= x"C5"; when x"D05" => DATA <= x"FE"; when x"D06" => DATA <= x"D0"; when x"D07" => DATA <= x"21"; when x"D08" => DATA <= x"4C"; when x"D09" => DATA <= x"B7"; when x"D0A" => DATA <= x"FE"; when x"D0B" => DATA <= x"18"; when x"D0C" => DATA <= x"A2"; when x"D0D" => DATA <= x"00"; when x"D0E" => DATA <= x"8E"; when x"D0F" => DATA <= x"00"; when x"D10" => DATA <= x"B0"; when x"D11" => DATA <= x"A2"; when x"D12" => DATA <= x"02"; when x"D13" => DATA <= x"08"; when x"D14" => DATA <= x"16"; when x"D15" => DATA <= x"DE"; when x"D16" => DATA <= x"28"; when x"D17" => DATA <= x"76"; when x"D18" => DATA <= x"DE"; when x"D19" => DATA <= x"60"; when x"D1A" => DATA <= x"A9"; when x"D1B" => DATA <= x"05"; when x"D1C" => DATA <= x"A8"; when x"D1D" => DATA <= x"8D"; when x"D1E" => DATA <= x"03"; when x"D1F" => DATA <= x"B0"; when x"D20" => DATA <= x"CA"; when x"D21" => DATA <= x"D0"; when x"D22" => DATA <= x"FD"; when x"D23" => DATA <= x"49"; when x"D24" => DATA <= x"01"; when x"D25" => DATA <= x"C8"; when x"D26" => DATA <= x"10"; when x"D27" => DATA <= x"F5"; when x"D28" => DATA <= x"60"; when x"D29" => DATA <= x"C9"; when x"D2A" => DATA <= x"20"; when x"D2B" => DATA <= x"90"; when x"D2C" => DATA <= x"17"; when x"D2D" => DATA <= x"69"; when x"D2E" => DATA <= x"1F"; when x"D2F" => DATA <= x"30"; when x"D30" => DATA <= x"02"; when x"D31" => DATA <= x"49"; when x"D32" => DATA <= x"60"; when x"D33" => DATA <= x"20"; when x"D34" => DATA <= x"6B"; when x"D35" => DATA <= x"FE"; when x"D36" => DATA <= x"91"; when x"D37" => DATA <= x"DE"; when x"D38" => DATA <= x"C8"; when x"D39" => DATA <= x"C0"; when x"D3A" => DATA <= x"20"; when x"D3B" => DATA <= x"90"; when x"D3C" => DATA <= x"05"; when x"D3D" => DATA <= x"20"; when x"D3E" => DATA <= x"EC"; when x"D3F" => DATA <= x"FD"; when x"D40" => DATA <= x"A0"; when x"D41" => DATA <= x"00"; when x"D42" => DATA <= x"84"; when x"D43" => DATA <= x"E0"; when x"D44" => DATA <= x"48"; when x"D45" => DATA <= x"20"; when x"D46" => DATA <= x"6B"; when x"D47" => DATA <= x"FE"; when x"D48" => DATA <= x"B1"; when x"D49" => DATA <= x"DE"; when x"D4A" => DATA <= x"45"; when x"D4B" => DATA <= x"E1"; when x"D4C" => DATA <= x"91"; when x"D4D" => DATA <= x"DE"; when x"D4E" => DATA <= x"68"; when x"D4F" => DATA <= x"60"; when x"D50" => DATA <= x"20"; when x"D51" => DATA <= x"35"; when x"D52" => DATA <= x"FE"; when x"D53" => DATA <= x"A9"; when x"D54" => DATA <= x"20"; when x"D55" => DATA <= x"20"; when x"D56" => DATA <= x"6B"; when x"D57" => DATA <= x"FE"; when x"D58" => DATA <= x"91"; when x"D59" => DATA <= x"DE"; when x"D5A" => DATA <= x"10"; when x"D5B" => DATA <= x"E6"; when x"D5C" => DATA <= x"20"; when x"D5D" => DATA <= x"35"; when x"D5E" => DATA <= x"FE"; when x"D5F" => DATA <= x"4C"; when x"D60" => DATA <= x"42"; when x"D61" => DATA <= x"FD"; when x"D62" => DATA <= x"20"; when x"D63" => DATA <= x"EC"; when x"D64" => DATA <= x"FD"; when x"D65" => DATA <= x"A4"; when x"D66" => DATA <= x"E0"; when x"D67" => DATA <= x"10"; when x"D68" => DATA <= x"D9"; when x"D69" => DATA <= x"A0"; when x"D6A" => DATA <= x"80"; when x"D6B" => DATA <= x"84"; when x"D6C" => DATA <= x"E1"; when x"D6D" => DATA <= x"A0"; when x"D6E" => DATA <= x"00"; when x"D6F" => DATA <= x"8C"; when x"D70" => DATA <= x"00"; when x"D71" => DATA <= x"B0"; when x"D72" => DATA <= x"A9"; when x"D73" => DATA <= x"20"; when x"D74" => DATA <= x"99"; when x"D75" => DATA <= x"00"; when x"D76" => DATA <= x"80"; when x"D77" => DATA <= x"99"; when x"D78" => DATA <= x"00"; when x"D79" => DATA <= x"81"; when x"D7A" => DATA <= x"C8"; when x"D7B" => DATA <= x"D0"; when x"D7C" => DATA <= x"F7"; when x"D7D" => DATA <= x"A9"; when x"D7E" => DATA <= x"80"; when x"D7F" => DATA <= x"A0"; when x"D80" => DATA <= x"00"; when x"D81" => DATA <= x"85"; when x"D82" => DATA <= x"DF"; when x"D83" => DATA <= x"84"; when x"D84" => DATA <= x"DE"; when x"D85" => DATA <= x"F0"; when x"D86" => DATA <= x"BB"; when x"D87" => DATA <= x"20"; when x"D88" => DATA <= x"3A"; when x"D89" => DATA <= x"FE"; when x"D8A" => DATA <= x"4C"; when x"D8B" => DATA <= x"42"; when x"D8C" => DATA <= x"FD"; when x"D8D" => DATA <= x"18"; when x"D8E" => DATA <= x"A9"; when x"D8F" => DATA <= x"10"; when x"D90" => DATA <= x"85"; when x"D91" => DATA <= x"E6"; when x"D92" => DATA <= x"A2"; when x"D93" => DATA <= x"08"; when x"D94" => DATA <= x"20"; when x"D95" => DATA <= x"13"; when x"D96" => DATA <= x"FD"; when x"D97" => DATA <= x"4C"; when x"D98" => DATA <= x"44"; when x"D99" => DATA <= x"FD"; when x"D9A" => DATA <= x"A5"; when x"D9B" => DATA <= x"E7"; when x"D9C" => DATA <= x"49"; when x"D9D" => DATA <= x"60"; when x"D9E" => DATA <= x"85"; when x"D9F" => DATA <= x"E7"; when x"DA0" => DATA <= x"B0"; when x"DA1" => DATA <= x"09"; when x"DA2" => DATA <= x"29"; when x"DA3" => DATA <= x"05"; when x"DA4" => DATA <= x"2E"; when x"DA5" => DATA <= x"01"; when x"DA6" => DATA <= x"B0"; when x"DA7" => DATA <= x"2A"; when x"DA8" => DATA <= x"20"; when x"DA9" => DATA <= x"EA"; when x"DAA" => DATA <= x"FC"; when x"DAB" => DATA <= x"4C"; when x"DAC" => DATA <= x"9A"; when x"DAD" => DATA <= x"FE"; when x"DAE" => DATA <= x"A4"; when x"DAF" => DATA <= x"E0"; when x"DB0" => DATA <= x"20"; when x"DB1" => DATA <= x"6B"; when x"DB2" => DATA <= x"FE"; when x"DB3" => DATA <= x"B1"; when x"DB4" => DATA <= x"DE"; when x"DB5" => DATA <= x"45"; when x"DB6" => DATA <= x"E1"; when x"DB7" => DATA <= x"30"; when x"DB8" => DATA <= x"02"; when x"DB9" => DATA <= x"49"; when x"DBA" => DATA <= x"60"; when x"DBB" => DATA <= x"E9"; when x"DBC" => DATA <= x"20"; when x"DBD" => DATA <= x"4C"; when x"DBE" => DATA <= x"E9"; when x"DBF" => DATA <= x"FD"; when x"DC0" => DATA <= x"A9"; when x"DC1" => DATA <= x"5F"; when x"DC2" => DATA <= x"49"; when x"DC3" => DATA <= x"20"; when x"DC4" => DATA <= x"D0"; when x"DC5" => DATA <= x"23"; when x"DC6" => DATA <= x"45"; when x"DC7" => DATA <= x"E7"; when x"DC8" => DATA <= x"2C"; when x"DC9" => DATA <= x"01"; when x"DCA" => DATA <= x"B0"; when x"DCB" => DATA <= x"30"; when x"DCC" => DATA <= x"02"; when x"DCD" => DATA <= x"49"; when x"DCE" => DATA <= x"60"; when x"DCF" => DATA <= x"4C"; when x"DD0" => DATA <= x"DF"; when x"DD1" => DATA <= x"FD"; when x"DD2" => DATA <= x"69"; when x"DD3" => DATA <= x"39"; when x"DD4" => DATA <= x"90"; when x"DD5" => DATA <= x"F2"; when x"DD6" => DATA <= x"49"; when x"DD7" => DATA <= x"10"; when x"DD8" => DATA <= x"2C"; when x"DD9" => DATA <= x"01"; when x"DDA" => DATA <= x"B0"; when x"DDB" => DATA <= x"30"; when x"DDC" => DATA <= x"02"; when x"DDD" => DATA <= x"49"; when x"DDE" => DATA <= x"10"; when x"DDF" => DATA <= x"18"; when x"DE0" => DATA <= x"69"; when x"DE1" => DATA <= x"20"; when x"DE2" => DATA <= x"2C"; when x"DE3" => DATA <= x"01"; when x"DE4" => DATA <= x"B0"; when x"DE5" => DATA <= x"70"; when x"DE6" => DATA <= x"02"; when x"DE7" => DATA <= x"29"; when x"DE8" => DATA <= x"1F"; when x"DE9" => DATA <= x"4C"; when x"DEA" => DATA <= x"60"; when x"DEB" => DATA <= x"FE"; when x"DEC" => DATA <= x"A5"; when x"DED" => DATA <= x"DE"; when x"DEE" => DATA <= x"A4"; when x"DEF" => DATA <= x"DF"; when x"DF0" => DATA <= x"C0"; when x"DF1" => DATA <= x"81"; when x"DF2" => DATA <= x"90"; when x"DF3" => DATA <= x"38"; when x"DF4" => DATA <= x"C9"; when x"DF5" => DATA <= x"E0"; when x"DF6" => DATA <= x"90"; when x"DF7" => DATA <= x"34"; when x"DF8" => DATA <= x"A4"; when x"DF9" => DATA <= x"E6"; when x"DFA" => DATA <= x"30"; when x"DFB" => DATA <= x"0C"; when x"DFC" => DATA <= x"88"; when x"DFD" => DATA <= x"D0"; when x"DFE" => DATA <= x"07"; when x"DFF" => DATA <= x"20"; when x"E00" => DATA <= x"71"; when x"E01" => DATA <= x"FE"; when x"E02" => DATA <= x"B0"; when x"E03" => DATA <= x"FB"; when x"E04" => DATA <= x"A0"; when x"E05" => DATA <= x"10"; when x"E06" => DATA <= x"84"; when x"E07" => DATA <= x"E6"; when x"E08" => DATA <= x"A0"; when x"E09" => DATA <= x"20"; when x"E0A" => DATA <= x"20"; when x"E0B" => DATA <= x"66"; when x"E0C" => DATA <= x"FE"; when x"E0D" => DATA <= x"B9"; when x"E0E" => DATA <= x"00"; when x"E0F" => DATA <= x"80"; when x"E10" => DATA <= x"99"; when x"E11" => DATA <= x"E0"; when x"E12" => DATA <= x"7F"; when x"E13" => DATA <= x"C8"; when x"E14" => DATA <= x"D0"; when x"E15" => DATA <= x"F7"; when x"E16" => DATA <= x"20"; when x"E17" => DATA <= x"6B"; when x"E18" => DATA <= x"FE"; when x"E19" => DATA <= x"B9"; when x"E1A" => DATA <= x"00"; when x"E1B" => DATA <= x"81"; when x"E1C" => DATA <= x"99"; when x"E1D" => DATA <= x"E0"; when x"E1E" => DATA <= x"80"; when x"E1F" => DATA <= x"C8"; when x"E20" => DATA <= x"D0"; when x"E21" => DATA <= x"F7"; when x"E22" => DATA <= x"A0"; when x"E23" => DATA <= x"1F"; when x"E24" => DATA <= x"A9"; when x"E25" => DATA <= x"20"; when x"E26" => DATA <= x"91"; when x"E27" => DATA <= x"DE"; when x"E28" => DATA <= x"88"; when x"E29" => DATA <= x"10"; when x"E2A" => DATA <= x"FB"; when x"E2B" => DATA <= x"60"; when x"E2C" => DATA <= x"69"; when x"E2D" => DATA <= x"20"; when x"E2E" => DATA <= x"85"; when x"E2F" => DATA <= x"DE"; when x"E30" => DATA <= x"D0"; when x"E31" => DATA <= x"02"; when x"E32" => DATA <= x"E6"; when x"E33" => DATA <= x"DF"; when x"E34" => DATA <= x"60"; when x"E35" => DATA <= x"88"; when x"E36" => DATA <= x"10"; when x"E37" => DATA <= x"19"; when x"E38" => DATA <= x"A0"; when x"E39" => DATA <= x"1F"; when x"E3A" => DATA <= x"A5"; when x"E3B" => DATA <= x"DE"; when x"E3C" => DATA <= x"D0"; when x"E3D" => DATA <= x"0B"; when x"E3E" => DATA <= x"A6"; when x"E3F" => DATA <= x"DF"; when x"E40" => DATA <= x"E0"; when x"E41" => DATA <= x"80"; when x"E42" => DATA <= x"D0"; when x"E43" => DATA <= x"05"; when x"E44" => DATA <= x"68"; when x"E45" => DATA <= x"68"; when x"E46" => DATA <= x"4C"; when x"E47" => DATA <= x"65"; when x"E48" => DATA <= x"FD"; when x"E49" => DATA <= x"E9"; when x"E4A" => DATA <= x"20"; when x"E4B" => DATA <= x"85"; when x"E4C" => DATA <= x"DE"; when x"E4D" => DATA <= x"B0"; when x"E4E" => DATA <= x"02"; when x"E4F" => DATA <= x"C6"; when x"E50" => DATA <= x"DF"; when x"E51" => DATA <= x"60"; when x"E52" => DATA <= x"20"; when x"E53" => DATA <= x"FB"; when x"E54" => DATA <= x"FE"; when x"E55" => DATA <= x"08"; when x"E56" => DATA <= x"48"; when x"E57" => DATA <= x"D8"; when x"E58" => DATA <= x"84"; when x"E59" => DATA <= x"E5"; when x"E5A" => DATA <= x"86"; when x"E5B" => DATA <= x"E4"; when x"E5C" => DATA <= x"20"; when x"E5D" => DATA <= x"EA"; when x"E5E" => DATA <= x"FC"; when x"E5F" => DATA <= x"68"; when x"E60" => DATA <= x"A6"; when x"E61" => DATA <= x"E4"; when x"E62" => DATA <= x"A4"; when x"E63" => DATA <= x"E5"; when x"E64" => DATA <= x"28"; when x"E65" => DATA <= x"60"; when x"E66" => DATA <= x"2C"; when x"E67" => DATA <= x"02"; when x"E68" => DATA <= x"B0"; when x"E69" => DATA <= x"10"; when x"E6A" => DATA <= x"FB"; when x"E6B" => DATA <= x"2C"; when x"E6C" => DATA <= x"02"; when x"E6D" => DATA <= x"B0"; when x"E6E" => DATA <= x"30"; when x"E6F" => DATA <= x"FB"; when x"E70" => DATA <= x"60"; when x"E71" => DATA <= x"A0"; when x"E72" => DATA <= x"3B"; when x"E73" => DATA <= x"18"; when x"E74" => DATA <= x"A9"; when x"E75" => DATA <= x"20"; when x"E76" => DATA <= x"A2"; when x"E77" => DATA <= x"0A"; when x"E78" => DATA <= x"2C"; when x"E79" => DATA <= x"01"; when x"E7A" => DATA <= x"B0"; when x"E7B" => DATA <= x"F0"; when x"E7C" => DATA <= x"08"; when x"E7D" => DATA <= x"EE"; when x"E7E" => DATA <= x"00"; when x"E7F" => DATA <= x"B0"; when x"E80" => DATA <= x"88"; when x"E81" => DATA <= x"CA"; when x"E82" => DATA <= x"D0"; when x"E83" => DATA <= x"F4"; when x"E84" => DATA <= x"4A"; when x"E85" => DATA <= x"08"; when x"E86" => DATA <= x"48"; when x"E87" => DATA <= x"AD"; when x"E88" => DATA <= x"00"; when x"E89" => DATA <= x"B0"; when x"E8A" => DATA <= x"29"; when x"E8B" => DATA <= x"F0"; when x"E8C" => DATA <= x"8D"; when x"E8D" => DATA <= x"00"; when x"E8E" => DATA <= x"B0"; when x"E8F" => DATA <= x"68"; when x"E90" => DATA <= x"28"; when x"E91" => DATA <= x"D0"; when x"E92" => DATA <= x"E3"; when x"E93" => DATA <= x"60"; when x"E94" => DATA <= x"08"; when x"E95" => DATA <= x"D8"; when x"E96" => DATA <= x"86"; when x"E97" => DATA <= x"E4"; when x"E98" => DATA <= x"84"; when x"E99" => DATA <= x"E5"; when x"E9A" => DATA <= x"2C"; when x"E9B" => DATA <= x"02"; when x"E9C" => DATA <= x"B0"; when x"E9D" => DATA <= x"50"; when x"E9E" => DATA <= x"05"; when x"E9F" => DATA <= x"20"; when x"EA0" => DATA <= x"71"; when x"EA1" => DATA <= x"FE"; when x"EA2" => DATA <= x"90"; when x"EA3" => DATA <= x"F6"; when x"EA4" => DATA <= x"20"; when x"EA5" => DATA <= x"8A"; when x"EA6" => DATA <= x"FB"; when x"EA7" => DATA <= x"20"; when x"EA8" => DATA <= x"71"; when x"EA9" => DATA <= x"FE"; when x"EAA" => DATA <= x"B0"; when x"EAB" => DATA <= x"FB"; when x"EAC" => DATA <= x"20"; when x"EAD" => DATA <= x"71"; when x"EAE" => DATA <= x"FE"; when x"EAF" => DATA <= x"B0"; when x"EB0" => DATA <= x"F6"; when x"EB1" => DATA <= x"98"; when x"EB2" => DATA <= x"A2"; when x"EB3" => DATA <= x"17"; when x"EB4" => DATA <= x"20"; when x"EB5" => DATA <= x"C5"; when x"EB6" => DATA <= x"FE"; when x"EB7" => DATA <= x"BD"; when x"EB8" => DATA <= x"E3"; when x"EB9" => DATA <= x"FE"; when x"EBA" => DATA <= x"85"; when x"EBB" => DATA <= x"E2"; when x"EBC" => DATA <= x"A9"; when x"EBD" => DATA <= x"FD"; when x"EBE" => DATA <= x"85"; when x"EBF" => DATA <= x"E3"; when x"EC0" => DATA <= x"98"; when x"EC1" => DATA <= x"6C"; when x"EC2" => DATA <= x"E2"; when x"EC3" => DATA <= x"00"; when x"EC4" => DATA <= x"CA"; when x"EC5" => DATA <= x"DD"; when x"EC6" => DATA <= x"CB"; when x"EC7" => DATA <= x"FE"; when x"EC8" => DATA <= x"90"; when x"EC9" => DATA <= x"FA"; when x"ECA" => DATA <= x"60"; when x"ECB" => DATA <= x"00"; when x"ECC" => DATA <= x"08"; when x"ECD" => DATA <= x"09"; when x"ECE" => DATA <= x"0A"; when x"ECF" => DATA <= x"0B"; when x"ED0" => DATA <= x"0C"; when x"ED1" => DATA <= x"0D"; when x"ED2" => DATA <= x"0E"; when x"ED3" => DATA <= x"0F"; when x"ED4" => DATA <= x"1E"; when x"ED5" => DATA <= x"7F"; when x"ED6" => DATA <= x"00"; when x"ED7" => DATA <= x"01"; when x"ED8" => DATA <= x"05"; when x"ED9" => DATA <= x"06"; when x"EDA" => DATA <= x"08"; when x"EDB" => DATA <= x"0E"; when x"EDC" => DATA <= x"0F"; when x"EDD" => DATA <= x"10"; when x"EDE" => DATA <= x"11"; when x"EDF" => DATA <= x"1C"; when x"EE0" => DATA <= x"20"; when x"EE1" => DATA <= x"21"; when x"EE2" => DATA <= x"3B"; when x"EE3" => DATA <= x"44"; when x"EE4" => DATA <= x"5C"; when x"EE5" => DATA <= x"38"; when x"EE6" => DATA <= x"62"; when x"EE7" => DATA <= x"87"; when x"EE8" => DATA <= x"69"; when x"EE9" => DATA <= x"40"; when x"EEA" => DATA <= x"8D"; when x"EEB" => DATA <= x"92"; when x"EEC" => DATA <= x"7D"; when x"EED" => DATA <= x"50"; when x"EEE" => DATA <= x"DF"; when x"EEF" => DATA <= x"D2"; when x"EF0" => DATA <= x"9A"; when x"EF1" => DATA <= x"A2"; when x"EF2" => DATA <= x"E2"; when x"EF3" => DATA <= x"AE"; when x"EF4" => DATA <= x"C0"; when x"EF5" => DATA <= x"DF"; when x"EF6" => DATA <= x"D8"; when x"EF7" => DATA <= x"D6"; when x"EF8" => DATA <= x"C8"; when x"EF9" => DATA <= x"C6"; when x"EFA" => DATA <= x"C2"; when x"EFB" => DATA <= x"48"; when x"EFC" => DATA <= x"C9"; when x"EFD" => DATA <= x"02"; when x"EFE" => DATA <= x"F0"; when x"EFF" => DATA <= x"27"; when x"F00" => DATA <= x"C9"; when x"F01" => DATA <= x"03"; when x"F02" => DATA <= x"F0"; when x"F03" => DATA <= x"34"; when x"F04" => DATA <= x"C5"; when x"F05" => DATA <= x"FE"; when x"F06" => DATA <= x"F0"; when x"F07" => DATA <= x"2E"; when x"F08" => DATA <= x"AD"; when x"F09" => DATA <= x"0C"; when x"F0A" => DATA <= x"B8"; when x"F0B" => DATA <= x"29"; when x"F0C" => DATA <= x"0E"; when x"F0D" => DATA <= x"F0"; when x"F0E" => DATA <= x"27"; when x"F0F" => DATA <= x"68"; when x"F10" => DATA <= x"2C"; when x"F11" => DATA <= x"01"; when x"F12" => DATA <= x"B8"; when x"F13" => DATA <= x"30"; when x"F14" => DATA <= x"FB"; when x"F15" => DATA <= x"8D"; when x"F16" => DATA <= x"01"; when x"F17" => DATA <= x"B8"; when x"F18" => DATA <= x"48"; when x"F19" => DATA <= x"AD"; when x"F1A" => DATA <= x"0C"; when x"F1B" => DATA <= x"B8"; when x"F1C" => DATA <= x"29"; when x"F1D" => DATA <= x"F0"; when x"F1E" => DATA <= x"09"; when x"F1F" => DATA <= x"0C"; when x"F20" => DATA <= x"8D"; when x"F21" => DATA <= x"0C"; when x"F22" => DATA <= x"B8"; when x"F23" => DATA <= x"09"; when x"F24" => DATA <= x"02"; when x"F25" => DATA <= x"D0"; when x"F26" => DATA <= x"0C"; when x"F27" => DATA <= x"A9"; when x"F28" => DATA <= x"7F"; when x"F29" => DATA <= x"8D"; when x"F2A" => DATA <= x"03"; when x"F2B" => DATA <= x"B8"; when x"F2C" => DATA <= x"AD"; when x"F2D" => DATA <= x"0C"; when x"F2E" => DATA <= x"B8"; when x"F2F" => DATA <= x"29"; when x"F30" => DATA <= x"F0"; when x"F31" => DATA <= x"09"; when x"F32" => DATA <= x"0E"; when x"F33" => DATA <= x"8D"; when x"F34" => DATA <= x"0C"; when x"F35" => DATA <= x"B8"; when x"F36" => DATA <= x"68"; when x"F37" => DATA <= x"60"; when x"F38" => DATA <= x"AD"; when x"F39" => DATA <= x"0C"; when x"F3A" => DATA <= x"B8"; when x"F3B" => DATA <= x"29"; when x"F3C" => DATA <= x"F0"; when x"F3D" => DATA <= x"B0"; when x"F3E" => DATA <= x"F4"; when x"F3F" => DATA <= x"A2"; when x"F40" => DATA <= x"17"; when x"F41" => DATA <= x"BD"; when x"F42" => DATA <= x"9A"; when x"F43" => DATA <= x"FF"; when x"F44" => DATA <= x"9D"; when x"F45" => DATA <= x"04"; when x"F46" => DATA <= x"02"; when x"F47" => DATA <= x"CA"; when x"F48" => DATA <= x"10"; when x"F49" => DATA <= x"F7"; when x"F4A" => DATA <= x"9A"; when x"F4B" => DATA <= x"8A"; when x"F4C" => DATA <= x"E8"; when x"F4D" => DATA <= x"86"; when x"F4E" => DATA <= x"EA"; when x"F4F" => DATA <= x"86"; when x"F50" => DATA <= x"E1"; when x"F51" => DATA <= x"86"; when x"F52" => DATA <= x"E7"; when x"F53" => DATA <= x"A2"; when x"F54" => DATA <= x"33"; when x"F55" => DATA <= x"9D"; when x"F56" => DATA <= x"EB"; when x"F57" => DATA <= x"02"; when x"F58" => DATA <= x"CA"; when x"F59" => DATA <= x"10"; when x"F5A" => DATA <= x"FA"; when x"F5B" => DATA <= x"A9"; when x"F5C" => DATA <= x"0A"; when x"F5D" => DATA <= x"85"; when x"F5E" => DATA <= x"FE"; when x"F5F" => DATA <= x"A9"; when x"F60" => DATA <= x"8A"; when x"F61" => DATA <= x"8D"; when x"F62" => DATA <= x"03"; when x"F63" => DATA <= x"B0"; when x"F64" => DATA <= x"A9"; when x"F65" => DATA <= x"07"; when x"F66" => DATA <= x"8D"; when x"F67" => DATA <= x"02"; when x"F68" => DATA <= x"B0"; when x"F69" => DATA <= x"20"; when x"F6A" => DATA <= x"D1"; when x"F6B" => DATA <= x"F7"; when x"F6C" => DATA <= x"06"; when x"F6D" => DATA <= x"0C"; when x"F6E" => DATA <= x"0F"; when x"F6F" => DATA <= x"41"; when x"F70" => DATA <= x"43"; when x"F71" => DATA <= x"4F"; when x"F72" => DATA <= x"52"; when x"F73" => DATA <= x"4E"; when x"F74" => DATA <= x"20"; when x"F75" => DATA <= x"41"; when x"F76" => DATA <= x"54"; when x"F77" => DATA <= x"4F"; when x"F78" => DATA <= x"4D"; when x"F79" => DATA <= x"0A"; when x"F7A" => DATA <= x"0A"; when x"F7B" => DATA <= x"0D"; when x"F7C" => DATA <= x"A9"; when x"F7D" => DATA <= x"82"; when x"F7E" => DATA <= x"85"; when x"F7F" => DATA <= x"12"; when x"F80" => DATA <= x"58"; when x"F81" => DATA <= x"A9"; when x"F82" => DATA <= x"55"; when x"F83" => DATA <= x"8D"; when x"F84" => DATA <= x"01"; when x"F85" => DATA <= x"29"; when x"F86" => DATA <= x"CD"; when x"F87" => DATA <= x"01"; when x"F88" => DATA <= x"29"; when x"F89" => DATA <= x"D0"; when x"F8A" => DATA <= x"0C"; when x"F8B" => DATA <= x"0A"; when x"F8C" => DATA <= x"8D"; when x"F8D" => DATA <= x"01"; when x"F8E" => DATA <= x"29"; when x"F8F" => DATA <= x"CD"; when x"F90" => DATA <= x"01"; when x"F91" => DATA <= x"29"; when x"F92" => DATA <= x"D0"; when x"F93" => DATA <= x"03"; when x"F94" => DATA <= x"4C"; when x"F95" => DATA <= x"B2"; when x"F96" => DATA <= x"C2"; when x"F97" => DATA <= x"4C"; when x"F98" => DATA <= x"B6"; when x"F99" => DATA <= x"C2"; when x"F9A" => DATA <= x"00"; when x"F9B" => DATA <= x"A0"; when x"F9C" => DATA <= x"EF"; when x"F9D" => DATA <= x"F8"; when x"F9E" => DATA <= x"52"; when x"F9F" => DATA <= x"FE"; when x"FA0" => DATA <= x"94"; when x"FA1" => DATA <= x"FE"; when x"FA2" => DATA <= x"6E"; when x"FA3" => DATA <= x"F9"; when x"FA4" => DATA <= x"E5"; when x"FA5" => DATA <= x"FA"; when x"FA6" => DATA <= x"AC"; when x"FA7" => DATA <= x"C2"; when x"FA8" => DATA <= x"AC"; when x"FA9" => DATA <= x"C2"; when x"FAA" => DATA <= x"EE"; when x"FAB" => DATA <= x"FB"; when x"FAC" => DATA <= x"7C"; when x"FAD" => DATA <= x"FC"; when x"FAE" => DATA <= x"38"; when x"FAF" => DATA <= x"FC"; when x"FB0" => DATA <= x"78"; when x"FB1" => DATA <= x"C2"; when x"FB2" => DATA <= x"85"; when x"FB3" => DATA <= x"FF"; when x"FB4" => DATA <= x"68"; when x"FB5" => DATA <= x"48"; when x"FB6" => DATA <= x"29"; when x"FB7" => DATA <= x"10"; when x"FB8" => DATA <= x"D0"; when x"FB9" => DATA <= x"06"; when x"FBA" => DATA <= x"A5"; when x"FBB" => DATA <= x"FF"; when x"FBC" => DATA <= x"48"; when x"FBD" => DATA <= x"6C"; when x"FBE" => DATA <= x"04"; when x"FBF" => DATA <= x"02"; when x"FC0" => DATA <= x"A5"; when x"FC1" => DATA <= x"FF"; when x"FC2" => DATA <= x"28"; when x"FC3" => DATA <= x"08"; when x"FC4" => DATA <= x"6C"; when x"FC5" => DATA <= x"02"; when x"FC6" => DATA <= x"02"; when x"FC7" => DATA <= x"48"; when x"FC8" => DATA <= x"6C"; when x"FC9" => DATA <= x"00"; when x"FCA" => DATA <= x"02"; when x"FCB" => DATA <= x"6C"; when x"FCC" => DATA <= x"1A"; when x"FCD" => DATA <= x"02"; when x"FCE" => DATA <= x"6C"; when x"FCF" => DATA <= x"18"; when x"FD0" => DATA <= x"02"; when x"FD1" => DATA <= x"6C"; when x"FD2" => DATA <= x"16"; when x"FD3" => DATA <= x"02"; when x"FD4" => DATA <= x"6C"; when x"FD5" => DATA <= x"14"; when x"FD6" => DATA <= x"02"; when x"FD7" => DATA <= x"6C"; when x"FD8" => DATA <= x"12"; when x"FD9" => DATA <= x"02"; when x"FDA" => DATA <= x"6C"; when x"FDB" => DATA <= x"10"; when x"FDC" => DATA <= x"02"; when x"FDD" => DATA <= x"6C"; when x"FDE" => DATA <= x"0E"; when x"FDF" => DATA <= x"02"; when x"FE0" => DATA <= x"6C"; when x"FE1" => DATA <= x"0C"; when x"FE2" => DATA <= x"02"; when x"FE3" => DATA <= x"6C"; when x"FE4" => DATA <= x"0A"; when x"FE5" => DATA <= x"02"; when x"FE6" => DATA <= x"20"; when x"FE7" => DATA <= x"E3"; when x"FE8" => DATA <= x"FF"; when x"FE9" => DATA <= x"C9"; when x"FEA" => DATA <= x"0D"; when x"FEB" => DATA <= x"D0"; when x"FEC" => DATA <= x"07"; when x"FED" => DATA <= x"A9"; when x"FEE" => DATA <= x"0A"; when x"FEF" => DATA <= x"20"; when x"FF0" => DATA <= x"F4"; when x"FF1" => DATA <= x"FF"; when x"FF2" => DATA <= x"A9"; when x"FF3" => DATA <= x"0D"; when x"FF4" => DATA <= x"6C"; when x"FF5" => DATA <= x"08"; when x"FF6" => DATA <= x"02"; when x"FF7" => DATA <= x"6C"; when x"FF8" => DATA <= x"06"; when x"FF9" => DATA <= x"02"; when x"FFA" => DATA <= x"C7"; when x"FFB" => DATA <= x"FF"; when x"FFC" => DATA <= x"3F"; when x"FFD" => DATA <= x"FF"; when x"FFE" => DATA <= x"B2"; when x"FFF" => DATA <= x"FF"; when others => DATA <= (others => '0'); end case; end process; end RTL;
apache-2.0
eb0357c99afc3f5a072215fdbf000472
0.358261
2.918986
false
false
false
false
tghaefli/ADD
EDK/IVK_Repos/IVK_IPLib/pcores/sg_2d_fir_plbw_v1_02_b/hdl/vhdl/block_memory_generator_spartan6_6_2_80846d0865f6122e.vhd
3
6,752
-------------------------------------------------------------------------------- -- This file is owned and controlled by Xilinx and must be used solely -- -- for design, simulation, implementation and creation of design files -- -- limited to Xilinx devices or technologies. Use with non-Xilinx -- -- devices or technologies is expressly prohibited and immediately -- -- terminates your license. -- -- -- -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY -- -- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -- -- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE -- -- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS -- -- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY -- -- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY -- -- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY -- -- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- -- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- -- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- -- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- -- PARTICULAR PURPOSE. -- -- -- -- Xilinx products are not intended for use in life support appliances, -- -- devices, or systems. Use in such applications are expressly -- -- prohibited. -- -- -- -- (c) Copyright 1995-2012 Xilinx, Inc. -- -- All rights reserved. -- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -- You must compile the wrapper file block_memory_generator_spartan6_6_2_80846d0865f6122e.vhd when simulating -- the core, block_memory_generator_spartan6_6_2_80846d0865f6122e. When compiling the wrapper file, be sure to -- reference the XilinxCoreLib VHDL simulation library. For detailed -- instructions, please refer to the "CORE Generator Help". -- The synthesis directives "translate_off/translate_on" specified -- below are supported by Xilinx, Mentor Graphics and Synplicity -- synthesis tools. Ensure they are correct for your synthesis tool(s). LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- synthesis translate_off LIBRARY XilinxCoreLib; -- synthesis translate_on ENTITY block_memory_generator_spartan6_6_2_80846d0865f6122e IS PORT ( clka : IN STD_LOGIC; ena : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(4 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(6 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); clkb : IN STD_LOGIC; enb : IN STD_LOGIC; web : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addrb : IN STD_LOGIC_VECTOR(4 DOWNTO 0); dinb : IN STD_LOGIC_VECTOR(6 DOWNTO 0); doutb : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) ); END block_memory_generator_spartan6_6_2_80846d0865f6122e; ARCHITECTURE block_memory_generator_spartan6_6_2_80846d0865f6122e_a OF block_memory_generator_spartan6_6_2_80846d0865f6122e IS -- synthesis translate_off COMPONENT wrapped_block_memory_generator_spartan6_6_2_80846d0865f6122e PORT ( clka : IN STD_LOGIC; ena : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(4 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(6 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); clkb : IN STD_LOGIC; enb : IN STD_LOGIC; web : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addrb : IN STD_LOGIC_VECTOR(4 DOWNTO 0); dinb : IN STD_LOGIC_VECTOR(6 DOWNTO 0); doutb : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) ); END COMPONENT; -- Configuration specification FOR ALL : wrapped_block_memory_generator_spartan6_6_2_80846d0865f6122e USE ENTITY XilinxCoreLib.blk_mem_gen_v6_2(behavioral) GENERIC MAP ( c_addra_width => 5, c_addrb_width => 5, c_algorithm => 1, c_axi_id_width => 4, c_axi_slave_type => 0, c_axi_type => 1, c_byte_size => 9, c_common_clk => 0, c_default_data => "0", c_disable_warn_bhv_coll => 0, c_disable_warn_bhv_range => 0, c_family => "spartan6", c_has_axi_id => 0, c_has_ena => 1, c_has_enb => 1, c_has_injecterr => 0, c_has_mem_output_regs_a => 0, c_has_mem_output_regs_b => 0, c_has_mux_output_regs_a => 0, c_has_mux_output_regs_b => 0, c_has_regcea => 0, c_has_regceb => 0, c_has_rsta => 0, c_has_rstb => 0, c_has_softecc_input_regs_a => 0, c_has_softecc_output_regs_b => 0, c_init_file_name => "block_memory_generator_spartan6_6_2_80846d0865f6122e.mif", c_inita_val => "0", c_initb_val => "0", c_interface_type => 0, c_load_init_file => 1, c_mem_type => 2, c_mux_pipeline_stages => 0, c_prim_type => 1, c_read_depth_a => 32, c_read_depth_b => 32, c_read_width_a => 7, c_read_width_b => 7, c_rst_priority_a => "CE", c_rst_priority_b => "CE", c_rst_type => "SYNC", c_rstram_a => 0, c_rstram_b => 0, c_sim_collision_check => "ALL", c_use_byte_wea => 0, c_use_byte_web => 0, c_use_default_data => 0, c_use_ecc => 0, c_use_softecc => 0, c_wea_width => 1, c_web_width => 1, c_write_depth_a => 32, c_write_depth_b => 32, c_write_mode_a => "WRITE_FIRST", c_write_mode_b => "READ_FIRST", c_write_width_a => 7, c_write_width_b => 7, c_xdevicefamily => "spartan6" ); -- synthesis translate_on BEGIN -- synthesis translate_off U0 : wrapped_block_memory_generator_spartan6_6_2_80846d0865f6122e PORT MAP ( clka => clka, ena => ena, wea => wea, addra => addra, dina => dina, douta => douta, clkb => clkb, enb => enb, web => web, addrb => addrb, dinb => dinb, doutb => doutb ); -- synthesis translate_on END block_memory_generator_spartan6_6_2_80846d0865f6122e_a;
gpl-3.0
326d7e10a9d1dd36978e18792205a218
0.546949
3.695676
false
false
false
false
hoglet67/AtomFpga
src/xilinx/AtomFpga_BeebAdapter.vhd
1
15,582
-------------------------------------------------------------------------------- -- Copyright (c) 2019 David Banks -- -- based on work by Alan Daly. Copyright(c) 2009. All rights reserved. -------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / -- \ \ \/ -- \ \ -- / / Filename : AtomFpga_BeebAdapter.vhd -- /___/ /\ Timestamp : 21/04/2019 -- \ \ / \ -- \___\/\___\ -- --Design Name: AtomFpga_BeebAdapter --Device: Spartan6 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; library unisim; use unisim.vcomponents.all; entity AtomFpga_BeebAdapter is port ( -- System oscillator clk50 : in std_logic; -- BBC 1MHZ Bus clke : in std_logic; rnw : in std_logic; rst_n : in std_logic; pgfc_n : in std_logic; pgfd_n : in std_logic; bus_addr : in std_logic_vector (7 downto 0); bus_data : inout std_logic_vector (7 downto 0); bus_data_dir : out std_logic; bus_data_oel : out std_logic; nmi : out std_logic; irq : out std_logic; -- SPI DAC dac_cs_n : out std_logic; dac_sck : out std_logic; dac_sdi : out std_logic; dac_ldac_n : out std_logic; -- RAM ram_addr : out std_logic_vector(18 downto 0); ram_data : inout std_logic_vector(7 downto 0); ram_cel : out std_logic; ram_oel : out std_logic; ram_wel : out std_logic; -- UART uart_rxd : in std_logic; uart_txd : out std_logic; -- Flash flash_cs : out std_logic; flash_ck : out std_logic; flash_si : out std_logic; flash_so : in std_logic; -- Misc pmod0 : out std_logic_vector(7 downto 0); pmod1 : inout std_logic_vector(7 downto 0); pmod2 : inout std_logic_vector(3 downto 0); sw1 : in std_logic; sw2 : in std_logic; led : out std_logic ); end AtomFpga_BeebAdapter; architecture behavioral of AtomFpga_BeebAdapter is -- Clock generation signal clk0 : std_logic; signal clk1 : std_logic; -- signal clk2 : std_logic; signal clkfb : std_logic; signal clkfb_buf : std_logic; signal clkin_buf : std_logic; signal clock_16 : std_logic; signal clock_25 : std_logic; signal clock_32 : std_logic; signal powerup_reset_n : std_logic; signal hard_reset_n : std_logic; signal reset_counter : std_logic_vector(9 downto 0); signal phi2 : std_logic; signal ext_A : std_logic_vector(18 downto 0); signal ext_Din : std_logic_vector(7 downto 0); signal ext_Dout : std_logic_vector(7 downto 0); signal ext_nWE : std_logic; signal ext_nOE : std_logic; signal ext_nCS : std_logic; signal ExternCE : std_logic; signal ExternWE : std_logic; signal ExternA : std_logic_vector (18 downto 0); signal ExternDin : std_logic_vector (7 downto 0); signal ExternDout : std_logic_vector (7 downto 0); signal red : std_logic_vector(2 downto 0); signal green : std_logic_vector(2 downto 0); signal blue : std_logic_vector(2 downto 0); signal hsync : std_logic; signal vsync : std_logic; -- Audio mixer and DAC constant dacwidth : integer := 16; -- this needs to match the MCP4822 frame size signal atom_audio : std_logic; signal sid_audio : std_logic_vector(17 downto 0); signal cycle : std_logic_vector(6 downto 0); signal audio_l : std_logic_vector(dacwidth - 1 downto 0); signal audio_r : std_logic_vector(dacwidth - 1 downto 0); signal dac_shift_reg_l : std_logic_vector(dacwidth - 1 downto 0); signal dac_shift_reg_r : std_logic_vector(dacwidth - 1 downto 0); signal mmc_clk : std_logic; signal mmc_ss : std_logic; signal mmc_mosi : std_logic; signal mmc_miso : std_logic; signal ps2_kbd_clk : std_logic; signal ps2_kbd_data : std_logic; ----------------------------------------------- -- Bootstrap ROM Image from SPI FLASH into SRAM ----------------------------------------------- -- start address of user data in FLASH as obtained from bitmerge.py -- this is safely beyond the end of the bitstream constant user_address : std_logic_vector(23 downto 0) := x"060000"; -- lenth of user data in FLASH = 128KB (32x 4KB ROM) images constant user_length : std_logic_vector(23 downto 0) := x"020000"; -- high when FLASH is being copied to SRAM, can be used by user as active high reset signal bootstrap_busy : std_logic; begin ------------------------------------------------ -- Clock generation -- -- from the on-board 50MHz Oscillator -- using a PLL for the 16/32 MHz -- using a DCM for the 25.175 MHz (approx) ------------------------------------------------ inst_clkin_buf : IBUFG port map ( I => clk50, O => clkin_buf ); inst_PLL : PLL_BASE generic map ( BANDWIDTH => "OPTIMIZED", CLK_FEEDBACK => "CLKFBOUT", COMPENSATION => "SYSTEM_SYNCHRONOUS", DIVCLK_DIVIDE => 1, CLKFBOUT_MULT => 16, -- 50 * 16 = 800 CLKFBOUT_PHASE => 0.000, CLKOUT0_DIVIDE => 50, -- 800 / 50 = 16MHz CLKOUT0_PHASE => 0.000, CLKOUT0_DUTY_CYCLE => 0.500, CLKOUT1_DIVIDE => 25, -- 800 / 25 = 32MHz CLKOUT1_PHASE => 0.000, CLKOUT1_DUTY_CYCLE => 0.500, -- CLKOUT2_DIVIDE => 32, -- 800 / 32 = 25MHz -- CLKOUT2_PHASE => 0.000, -- CLKOUT2_DUTY_CYCLE => 0.500, CLKIN_PERIOD => 20.000, REF_JITTER => 0.010 ) port map ( -- Output clocks CLKFBOUT => clkfb, CLKOUT0 => clk0, CLKOUT1 => clk1, -- CLKOUT2 => clk2, RST => '0', -- Input clock control CLKFBIN => clkfb_buf, CLKIN => clkin_buf ); inst_clkfb_buf : BUFG port map ( I => clkfb, O => clkfb_buf ); inst_clk0_buf : BUFG port map ( I => clk0, O => clock_16 ); inst_clk1_buf : BUFG port map ( I => clk1, O => clock_32 ); -- inst_clk2_buf : BUFG -- port map ( -- I => clk2, -- O => clock_25 -- ); inst_DCM : DCM generic map ( CLKFX_MULTIPLY => 11, CLKFX_DIVIDE => 14, CLKIN_PERIOD => 31.250, CLK_FEEDBACK => "NONE" ) port map ( CLKIN => clock_32, CLKFB => '0', RST => '0', DSSEN => '0', PSINCDEC => '0', PSEN => '0', PSCLK => '0', CLKFX => clock_25 ); -------------------------------------------------------- -- Power Up Reset Generation -------------------------------------------------------- -- The external reset signal is not asserted on power up -- This internal counter forces power up reset to happen -- This is needed by the GODIL to initialize some of the registers ResetProcess : process (clock_32) begin if rising_edge(clock_32) then if (reset_counter(reset_counter'high) = '0') then reset_counter <= reset_counter + 1; end if; powerup_reset_n <= (not SW1) and reset_counter(reset_counter'high); end if; end process; -- extend the version seen by the core to hold the 6502 reset during bootstrap hard_reset_n <= powerup_reset_n and not bootstrap_busy; -------------------------------------------------------- -- Atom Fpga Core -------------------------------------------------------- inst_AtomFpga_Core : entity work.AtomFpga_Core generic map ( CImplSDDOS => false, CImplAtoMMC2 => true, CImplGraphicsExt => true, CImplSoftChar => true, CImplSID => true, CImplVGA80x40 => true, CImplHWScrolling => true, CImplMouse => true, CImplUart => true, CImplDoubleVideo => true, CImplRamRomNone => false, CImplRamRomPhill => false, CImplRamRomAtom2015 => true, CImplRamRomSchakelKaart => false, MainClockSpeed => 32000000, DefaultBaud => 115200 ) port map ( clk_vga => clock_25, clk_main => clock_32, clk_avr => clock_32, clk_dac => clock_32, clk_32M00 => clock_32, ps2_clk => ps2_kbd_clk, ps2_data => ps2_kbd_data, ps2_mouse_clk => open, ps2_mouse_data => open, powerup_reset_n => powerup_reset_n, ext_reset_n => hard_reset_n, int_reset_n => open, red => red, green => green, blue => blue, vsync => vsync, hsync => hsync, phi2 => phi2, ExternCE => ExternCE, ExternWE => ExternWE, ExternA => ExternA, ExternDin => ExternDin, ExternDout => ExternDout, sid_audio => open, sid_audio_d => sid_audio, atom_audio => atom_audio, SDMISO => mmc_miso, SDSS => mmc_ss, SDCLK => mmc_clk, SDMOSI => mmc_mosi, uart_RxD => uart_rxd, uart_TxD => uart_txd, avr_RxD => '1', avr_TxD => open, LED1 => led, -- Green LED LED2 => open, -- Red LED charSet => '1', Joystick1 => (others => '1'), Joystick2 => (others => '1') ); ------------------------------------------------ -- Audio mixer ------------------------------------------------ process(atom_audio, sid_audio) variable l : std_logic_vector(dacwidth - 1 downto 0); variable r : std_logic_vector(dacwidth - 1 downto 0); begin -- Atom Audio is a single bit if (atom_audio = '1') then l := x"1000"; r := x"1000"; else l := x"EFFF"; r := x"EFFF"; end if; -- SID output is 18-bit unsigned l := l + sid_audio(17 downto 2); r := r + sid_audio(17 downto 2); -- Currently the left and right channels are identical audio_l <= l; audio_r <= r; end process; ------------------------------------------------ -- MCP4822 SPI 12-bit DAC -- -- note: this actually takes 16-bit samples ------------------------------------------------ process(clock_16) begin if rising_edge(clock_16) then cycle <= cycle + 1; if (unsigned(cycle(5 downto 0)) < 33) then dac_cs_n <= '0'; dac_sck <= cycle(0); else dac_cs_n <= '1'; dac_sck <= '0'; end if; if (cycle(0) = '0') then if (unsigned(cycle(5 downto 1)) = 0) then if (cycle(6) = '0') then dac_shift_reg_l <= audio_l; dac_shift_reg_r <= audio_r; end if; dac_sdi <= cycle(6); elsif (unsigned(cycle(5 downto 1)) < 4) then dac_sdi <= '1'; elsif (unsigned(cycle(5 downto 1)) < 16) then if (cycle(6) = '0') then dac_sdi <= dac_shift_reg_l(dacwidth - 1); dac_shift_reg_l <= dac_shift_reg_l(dacwidth - 2 downto 0) & '0'; else dac_sdi <= dac_shift_reg_r(dacwidth - 1); dac_shift_reg_r <= dac_shift_reg_r(dacwidth - 2 downto 0) & '0'; end if; else dac_sdi <= '0'; end if; if (unsigned(cycle(6 downto 1)) = 60) then dac_ldac_n <= '0'; else dac_ldac_n <= '1'; end if; end if; end if; end process; -------------------------------------------------------- -- BOOTSTRAP SPI FLASH to SRAM -------------------------------------------------------- inst_bootstrap: entity work.bootstrap generic map ( user_length => user_length ) port map( clock => clock_32, powerup_reset_n => powerup_reset_n, bootstrap_busy => bootstrap_busy, user_address => user_address, RAM_nOE => ext_nOE, RAM_nWE => ext_nWE, RAM_nCS => ext_nCS, RAM_A => ext_A, RAM_Din => ext_Din, RAM_Dout => ext_Dout, SRAM_nOE => ram_oel, SRAM_nWE => ram_wel, SRAM_nCS => ram_cel, SRAM_A(20 downto 19) => open, SRAM_A(18 downto 0) => ram_addr, SRAM_D => ram_data, FLASH_CS => flash_cs, FLASH_SI => flash_si, FLASH_CK => flash_ck, FLASH_SO => flash_so ); MemProcess : process (clock_32) begin if rising_edge(clock_32) then ext_A <= ExternA; ext_nCS <= not ExternCE; ext_nOE <= not ((not ExternWE) and ExternCE and phi2); ext_nWE <= not (ExternWE and ExternCE and phi2); ext_Din <= ExternDin; end if; end process; ExternDout <= ext_Dout; bus_data <= (others => 'Z'); bus_data_dir <= '1'; bus_data_oel <= '1'; nmi <= '0'; irq <= '0'; pmod0 <= blue & "0" & red & "0"; pmod1 <= "ZZ" & vsync & hsync & green & "0"; pmod2 <= "Z" & mmc_clk & mmc_mosi & mmc_ss; ps2_kbd_clk <= pmod1(6); ps2_kbd_data <= pmod1(7); mmc_miso <= pmod2(3); end behavioral;
apache-2.0
95c6b93185160a81518ca4745e4f255f
0.42241
4.103766
false
false
false
false
fquinto/Wireless_sensor_network
Avnet_UPC/hdl/dlmb_wrapper.vhd
1
3,169
------------------------------------------------------------------------------- -- dlmb_wrapper.vhd ------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; library lmb_v10_v1_00_a; use lmb_v10_v1_00_a.all; entity dlmb_wrapper is port ( LMB_Clk : in std_logic; SYS_Rst : in std_logic; LMB_Rst : out std_logic; M_ABus : in std_logic_vector(0 to 31); M_ReadStrobe : in std_logic; M_WriteStrobe : in std_logic; M_AddrStrobe : in std_logic; M_DBus : in std_logic_vector(0 to 31); M_BE : in std_logic_vector(0 to 3); Sl_DBus : in std_logic_vector(0 to 31); Sl_Ready : in std_logic_vector(0 to 0); LMB_ABus : out std_logic_vector(0 to 31); LMB_ReadStrobe : out std_logic; LMB_WriteStrobe : out std_logic; LMB_AddrStrobe : out std_logic; LMB_ReadDBus : out std_logic_vector(0 to 31); LMB_WriteDBus : out std_logic_vector(0 to 31); LMB_Ready : out std_logic; LMB_BE : out std_logic_vector(0 to 3) ); attribute x_core_info : STRING; attribute x_core_info of dlmb_wrapper : entity is "lmb_v10_v1_00_a"; end dlmb_wrapper; architecture STRUCTURE of dlmb_wrapper is component lmb_v10 is generic ( C_LMB_NUM_SLAVES : integer; C_LMB_AWIDTH : integer; C_LMB_DWIDTH : integer; C_EXT_RESET_HIGH : integer ); port ( LMB_Clk : in std_logic; SYS_Rst : in std_logic; LMB_Rst : out std_logic; M_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1); M_ReadStrobe : in std_logic; M_WriteStrobe : in std_logic; M_AddrStrobe : in std_logic; M_DBus : in std_logic_vector(0 to C_LMB_DWIDTH-1); M_BE : in std_logic_vector(0 to (C_LMB_DWIDTH+7)/8-1); Sl_DBus : in std_logic_vector(0 to (C_LMB_DWIDTH*C_LMB_NUM_SLAVES)-1); Sl_Ready : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1); LMB_ABus : out std_logic_vector(0 to C_LMB_AWIDTH-1); LMB_ReadStrobe : out std_logic; LMB_WriteStrobe : out std_logic; LMB_AddrStrobe : out std_logic; LMB_ReadDBus : out std_logic_vector(0 to C_LMB_DWIDTH-1); LMB_WriteDBus : out std_logic_vector(0 to C_LMB_DWIDTH-1); LMB_Ready : out std_logic; LMB_BE : out std_logic_vector(0 to (C_LMB_DWIDTH+7)/8-1) ); end component; begin dlmb : lmb_v10 generic map ( C_LMB_NUM_SLAVES => 1, C_LMB_AWIDTH => 32, C_LMB_DWIDTH => 32, C_EXT_RESET_HIGH => 1 ) port map ( LMB_Clk => LMB_Clk, SYS_Rst => SYS_Rst, LMB_Rst => LMB_Rst, M_ABus => M_ABus, M_ReadStrobe => M_ReadStrobe, M_WriteStrobe => M_WriteStrobe, M_AddrStrobe => M_AddrStrobe, M_DBus => M_DBus, M_BE => M_BE, Sl_DBus => Sl_DBus, Sl_Ready => Sl_Ready, LMB_ABus => LMB_ABus, LMB_ReadStrobe => LMB_ReadStrobe, LMB_WriteStrobe => LMB_WriteStrobe, LMB_AddrStrobe => LMB_AddrStrobe, LMB_ReadDBus => LMB_ReadDBus, LMB_WriteDBus => LMB_WriteDBus, LMB_Ready => LMB_Ready, LMB_BE => LMB_BE ); end architecture STRUCTURE;
mit
6638904460e8fae208b287dbeedf2657
0.575891
3.181727
false
true
false
false
hoglet67/AtomFpga
src/common/CpuWrapperDebugger.vhd
1
5,602
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; entity CpuWrapper is generic ( CImplDebugger : boolean := false; CImplCpu65c02 : boolean := false ); port ( clk_main : in std_logic; clk_avr : in std_logic; cpu_clken : in std_logic; IRQ_n : in std_logic; NMI_n : in std_logic; RST_n : in std_logic; PRST_n : in std_logic; SO : in std_logic; RDY : in std_logic; Din : in std_logic_vector(7 downto 0); Dout : out std_logic_vector(7 downto 0); R_W_n : out std_logic; Sync : out std_logic; Addr : out std_logic_vector(15 downto 0); avr_RxD : in std_logic; avr_TxD : out std_logic ); end CpuWrapper; architecture BEHAVIORAL of CpuWrapper is signal cpu_clken1 : std_logic; signal Addr_us : unsigned(15 downto 0); signal Dout_us : unsigned(7 downto 0); signal Din_us : unsigned(7 downto 0); begin process(clk_main) begin if rising_edge(clk_main) then cpu_clken1 <= cpu_clken; end if; end process; --------------------------------------------------------------------- -- 6502/65C02 CPU (using ICET65 Debugger) --------------------------------------------------------------------- debugger_nmos: if CImplDebugger and not CImplCpu65c02 generate core : entity work.MOS6502CpuMonCore generic map ( UseT65Core => true, UseAlanDCore => false, num_comparators => 8, filename => "avr_progmem_ice6502.data" ) port map ( clock_avr => clk_avr, busmon_clk => clk_main, busmon_clken => cpu_clken1, cpu_clk => clk_main, cpu_clken => cpu_clken, IRQ_n => IRQ_n, NMI_n => NMI_n, Sync => Sync, Addr => Addr, R_W_n => R_W_n, Din => Din, Dout => Dout, SO_n => SO, Res_n => RST_n, Rdy => RDY, trig => "00", avr_RxD => avr_RxD, avr_TxD => avr_TxD, sw_reset_cpu => '0', sw_reset_avr => not PRST_n ); end generate; debugger_cmos: if CImplDebugger and CImplCpu65c02 generate core : entity work.MOS6502CpuMonCore generic map ( UseT65Core => false, UseAlanDCore => true, num_comparators => 8, filename => "avr_progmem_ice65c02.data" ) port map ( clock_avr => clk_avr, busmon_clk => clk_main, busmon_clken => cpu_clken1, cpu_clk => clk_main, cpu_clken => cpu_clken, IRQ_n => IRQ_n, NMI_n => NMI_n, Sync => Sync, Addr => Addr, R_W_n => R_W_n, Din => Din, Dout => Dout, SO_n => SO, Res_n => RST_n, Rdy => RDY, trig => "00", avr_RxD => avr_RxD, avr_TxD => avr_TxD, sw_reset_cpu => '0', sw_reset_avr => not PRST_n ); end generate; --------------------------------------------------------------------- -- 6502 CPU (using T65 core) --------------------------------------------------------------------- not_debugger_nmos: if not CImplDebugger and not CImplCpu65c02 generate cpu : entity work.T65 port map ( Mode => "00", Abort_n => '1', SO_n => SO, Res_n => RST_n, Enable => cpu_clken, Clk => clk_main, Rdy => RDY, IRQ_n => IRQ_n, NMI_n => NMI_n, R_W_n => R_W_n, Sync => Sync, A(23 downto 16) => open, A(15 downto 0) => Addr(15 downto 0), DI(7 downto 0) => Din(7 downto 0), DO(7 downto 0) => Dout(7 downto 0) ); avr_TxD <= '1'; end generate; --------------------------------------------------------------------- -- 65C02 CPU (using AlanD core) --------------------------------------------------------------------- -- TODO: Need to add RDY not_debugger_cmos: if not CImplDebugger and CImplCpu65c02 generate inst_r65c02: entity work.r65c02 port map ( reset => RST_n, clk => clk_main, enable => cpu_clken, nmi_n => NMI_n, irq_n => IRQ_n, di => Din_us, do => Dout_us, addr => Addr_us, nwe => R_W_n, sync => Sync ); Din_us <= unsigned(Din); Dout <= std_logic_vector(Dout_us); Addr <= std_logic_vector(Addr_us); avr_TxD <= '1'; end generate; end BEHAVIORAL;
apache-2.0
d67dfa886b99c2f9a9a35af955e3c5fe
0.373974
4.205706
false
false
false
false
hoglet67/AtomFpga
src/common/T6502/T65.vhd
1
23,897
-- **** -- T65(b) core. In an effort to merge and maintain bug fixes .... -- -- Ver 313 WoS January 2015 -- Fixed issue that NMI has to be first if issued the same time as a BRK instruction is latched in -- Now all Lorenz CPU tests on FPGAARCADE C64 core (sources used: SVN version 1021) are OK! :D :D :D -- This is just a starting point to go for optimizations and detailed fixes (the Lorenz test can't find) -- -- Ver 312 WoS January 2015 -- Undoc opcode timing fixes for $B3 (LAX iy) and $BB (LAS ay) -- Added comments in MCode section to find handling of individual opcodes more easily -- All "basic" Lorenz instruction test (individual functional checks, CPUTIMING check) work now with -- actual FPGAARCADE C64 core (sources used: SVN version 1021). -- -- Ver 305, 306, 307, 308, 309, 310, 311 WoS January 2015 -- Undoc opcode fixes (now all Lorenz test on instruction functionality working, except timing issues on $B3 and $BB): -- SAX opcode -- SHA opcode -- SHX opcode -- SHY opcode -- SHS opcode -- LAS opcode -- alternate SBC opcode -- fixed NOP with immediate param (caused Lorenz trap test to fail) -- IRQ and NMI timing fixes (in conjuction with branches) -- -- Ver 304 WoS December 2014 -- Undoc opcode fixes: -- ARR opcode -- ANE/XAA opcode -- Corrected issue with NMI/IRQ prio (when asserted the same time) -- -- Ver 303 ost(ML) July 2014 -- (Sorry for some scratchpad comments that may make little sense) -- Mods and some 6502 undocumented instructions. -- Not correct opcodes acc. to Lorenz tests (incomplete list): -- NOPN (nop) -- NOPZX (nop + byte 172) -- NOPAX (nop + word da ... da: byte 0) -- ASOZ (byte $07 + byte 172) -- -- Ver 303,302 WoS April 2014 -- Bugfixes for NMI from foft -- Bugfix for BRK command (and its special flag) -- -- Ver 300,301 WoS January 2014 -- More merging -- Bugfixes by ehenciak added, started tidyup *bust* -- -- MikeJ March 2005 -- Latest version from www.fpgaarcade.com (original www.opencores.org) -- **** -- -- 65xx compatible microprocessor core -- -- FPGAARCADE SVN: $Id: T65.vhd 1347 2015-05-27 20:07:34Z wolfgang.scherr $ -- -- Copyright (c) 2002...2015 -- Daniel Wallner (jesus <at> opencores <dot> org) -- Mike Johnson (mikej <at> fpgaarcade <dot> com) -- Wolfgang Scherr (WoS <at> pin4 <dot> at> -- Morten Leikvoll () -- -- All rights reserved -- -- Redistribution and use in source and synthezised forms, with or without -- modification, are permitted provided that the following conditions are met: -- -- Redistributions of source code must retain the above copyright notice, -- this list of conditions and the following disclaimer. -- -- Redistributions in synthesized form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- Neither the name of the author nor the names of other contributors may -- be used to endorse or promote products derived from this software without -- specific prior written permission. -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- -- Please report bugs to the author(s), but before you do so, please -- make sure that this is not a derivative work and that -- you have the latest version of this file. -- -- ----- IMPORTANT NOTES ----- -- -- Limitations: -- 65C02 and 65C816 modes are incomplete (and definitely untested after all 6502 undoc fixes) -- 65C02 supported : inc, dec, phx, plx, phy, ply -- 65D02 missing : bra, ora, lda, cmp, sbc, tsb*2, trb*2, stz*2, bit*2, wai, stp, jmp, bbr*8, bbs*8 -- Some interface signals behave incorrect -- NMI interrupt handling not nice, needs further rework (to cycle-based encoding). -- -- Usage: -- The enable signal allows clock gating / throttling without using the ready signal. -- Set it to constant '1' when using the Clk input as the CPU clock directly. -- -- TAKE CARE you route the DO signal back to the DI signal while R_W_n='0', -- otherwise some undocumented opcodes won't work correctly. -- EXAMPLE: -- CPU : entity work.T65 -- port map ( -- R_W_n => cpu_rwn_s, -- [....all other ports....] -- DI => cpu_din_s, -- DO => cpu_dout_s -- ); -- cpu_din_s <= cpu_dout_s when cpu_rwn_s='0' else -- [....other sources from peripherals and memories...] -- -- ----- IMPORTANT NOTES ----- -- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.T65_Pack.all; entity T65 is port( Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65C816 Res_n : in std_logic; Enable : in std_logic; Clk : in std_logic; Rdy : in std_logic; Abort_n : in std_logic; IRQ_n : in std_logic; NMI_n : in std_logic; SO_n : in std_logic; R_W_n : out std_logic; Sync : out std_logic; EF : out std_logic; MF : out std_logic; XF : out std_logic; ML_n : out std_logic; VP_n : out std_logic; VDA : out std_logic; VPA : out std_logic; A : out std_logic_vector(23 downto 0); DI : in std_logic_vector(7 downto 0); DO : out std_logic_vector(7 downto 0); -- 6502 registers (MSB) PC, SP, P, Y, X, A (LSB) Regs : out std_logic_vector(63 downto 0); DEBUG : out T_t65_dbg ); end T65; architecture rtl of T65 is -- Registers signal ABC, X, Y, D : std_logic_vector(15 downto 0); signal P, AD, DL : std_logic_vector(7 downto 0) := x"00"; signal PwithB : std_logic_vector(7 downto 0);--ML:New way to push P with correct B state to stack signal BAH : std_logic_vector(7 downto 0); signal BAL : std_logic_vector(8 downto 0); signal PBR : std_logic_vector(7 downto 0); signal DBR : std_logic_vector(7 downto 0); signal PC : unsigned(15 downto 0); signal S : unsigned(15 downto 0); signal EF_i : std_logic; signal MF_i : std_logic; signal XF_i : std_logic; signal IR : std_logic_vector(7 downto 0); signal MCycle : std_logic_vector(2 downto 0); signal Mode_r : std_logic_vector(1 downto 0); signal ALU_Op_r : T_ALU_Op; signal Write_Data_r : T_Write_Data; signal Set_Addr_To_r : T_Set_Addr_To; signal PCAdder : unsigned(8 downto 0); signal RstCycle : std_logic; signal IRQCycle : std_logic; signal NMICycle : std_logic; signal SO_n_o : std_logic; signal IRQ_n_o : std_logic; signal NMI_n_o : std_logic; signal NMIAct : std_logic; signal Break : std_logic; -- ALU signals signal BusA : std_logic_vector(7 downto 0); signal BusA_r : std_logic_vector(7 downto 0); signal BusB : std_logic_vector(7 downto 0); signal BusB_r : std_logic_vector(7 downto 0); signal ALU_Q : std_logic_vector(7 downto 0); signal P_Out : std_logic_vector(7 downto 0); -- Micro code outputs signal LCycle : std_logic_vector(2 downto 0); signal ALU_Op : T_ALU_Op; signal Set_BusA_To : T_Set_BusA_To; signal Set_Addr_To : T_Set_Addr_To; signal Write_Data : T_Write_Data; signal Jump : std_logic_vector(1 downto 0); signal BAAdd : std_logic_vector(1 downto 0); signal BreakAtNA : std_logic; signal ADAdd : std_logic; signal AddY : std_logic; signal PCAdd : std_logic; signal Inc_S : std_logic; signal Dec_S : std_logic; signal LDA : std_logic; signal LDP : std_logic; signal LDX : std_logic; signal LDY : std_logic; signal LDS : std_logic; signal LDDI : std_logic; signal LDALU : std_logic; signal LDAD : std_logic; signal LDBAL : std_logic; signal LDBAH : std_logic; signal SaveP : std_logic; signal Write : std_logic; signal Res_n_i : std_logic; signal Res_n_d : std_logic; signal really_rdy : std_logic; signal WRn_i : std_logic; signal NMI_entered : std_logic; begin -- gate Rdy with read/write to make an "OK, it's really OK to stop the processor really_rdy <= Rdy or not(WRn_i); Sync <= '1' when MCycle = "000" else '0'; EF <= EF_i; MF <= MF_i; XF <= XF_i; R_W_n <= WRn_i; ML_n <= '0' when IR(7 downto 6) /= "10" and IR(2 downto 1) = "11" and MCycle(2 downto 1) /= "00" else '1'; VP_n <= '0' when IRQCycle = '1' and (MCycle = "101" or MCycle = "110") else '1'; VDA <= '1' when Set_Addr_To_r /= Set_Addr_To_PBR else '0'; VPA <= '1' when Jump(1) = '0' else '0'; -- debugging signals DEBUG.I <= IR; DEBUG.A <= ABC(7 downto 0); DEBUG.X <= X(7 downto 0); DEBUG.Y <= Y(7 downto 0); DEBUG.S <= std_logic_vector(S(7 downto 0)); DEBUG.P <= P; Regs <= std_logic_vector(PC) & std_logic_vector(S)& P & Y(7 downto 0) & X(7 downto 0) & ABC(7 downto 0); mcode : entity work.T65_MCode port map( --inputs Mode => Mode_r, IR => IR, MCycle => MCycle, P => P, --outputs LCycle => LCycle, ALU_Op => ALU_Op, Set_BusA_To => Set_BusA_To, Set_Addr_To => Set_Addr_To, Write_Data => Write_Data, Jump => Jump, BAAdd => BAAdd, BreakAtNA => BreakAtNA, ADAdd => ADAdd, AddY => AddY, PCAdd => PCAdd, Inc_S => Inc_S, Dec_S => Dec_S, LDA => LDA, LDP => LDP, LDX => LDX, LDY => LDY, LDS => LDS, LDDI => LDDI, LDALU => LDALU, LDAD => LDAD, LDBAL => LDBAL, LDBAH => LDBAH, SaveP => SaveP, Write => Write ); alu : entity work.T65_ALU port map( Mode => Mode_r, Op => ALU_Op_r, BusA => BusA_r, BusB => BusB, P_In => P, P_Out => P_Out, Q => ALU_Q ); -- the 65xx design requires at least two clock cycles before -- starting its reset sequence (according to datasheet) process (Res_n_i, Clk) begin if Res_n = '0' then Res_n_i <= '0'; Res_n_d <= '0'; elsif Clk'event and Clk = '1' then Res_n_i <= Res_n_d; Res_n_d <= '1'; end if; end process; process (Res_n_i, Clk) begin if Res_n_i = '0' then PC <= (others => '0'); -- Program Counter IR <= "00000000"; S <= (others => '0'); -- Dummy D <= (others => '0'); PBR <= (others => '0'); DBR <= (others => '0'); Mode_r <= (others => '0'); ALU_Op_r <= ALU_OP_BIT; Write_Data_r <= Write_Data_DL; Set_Addr_To_r <= Set_Addr_To_PBR; WRn_i <= '1'; EF_i <= '1'; MF_i <= '1'; XF_i <= '1'; elsif Clk'event and Clk = '1' then if (Enable = '1') then if (really_rdy = '1') then WRn_i <= not Write or RstCycle; D <= (others => '1'); -- Dummy PBR <= (others => '1'); -- Dummy DBR <= (others => '1'); -- Dummy EF_i <= '0'; -- Dummy MF_i <= '0'; -- Dummy XF_i <= '0'; -- Dummy if MCycle = "000" then Mode_r <= Mode; if IRQCycle = '0' and NMICycle = '0' then PC <= PC + 1; end if; if IRQCycle = '1' or NMICycle = '1' then IR <= "00000000"; else IR <= DI; end if; if LDS = '1' then -- LAS won't work properly if not limited to machine cycle 0 S(7 downto 0) <= unsigned(ALU_Q); end if; end if; ALU_Op_r <= ALU_Op; Write_Data_r <= Write_Data; if Break = '1' then Set_Addr_To_r <= Set_Addr_To_PBR; else Set_Addr_To_r <= Set_Addr_To; end if; if Inc_S = '1' then S <= S + 1; end if; if Dec_S = '1' and RstCycle = '0' then S <= S - 1; end if; if IR = "00000000" and MCycle = "001" and IRQCycle = '0' and NMICycle = '0' then PC <= PC + 1; end if; -- -- jump control logic -- case Jump is when "01" => PC <= PC + 1; when "10" => PC <= unsigned(DI & DL); when "11" => if PCAdder(8) = '1' then if DL(7) = '0' then PC(15 downto 8) <= PC(15 downto 8) + 1; else PC(15 downto 8) <= PC(15 downto 8) - 1; end if; end if; PC(7 downto 0) <= PCAdder(7 downto 0); when others => null; end case; end if; end if; end if; end process; PCAdder <= resize(PC(7 downto 0),9) + resize(unsigned(DL(7) & DL),9) when PCAdd = '1' else "0" & PC(7 downto 0); process (Res_n_i, Clk) variable tmpP:std_logic_vector(7 downto 0);--Lets try to handle loading P at mcycle=0 and set/clk flags at same cycle begin if Res_n_i = '0' then P <= x"00"; -- ensure we have nothing set on reset elsif Clk'event and Clk = '1' then tmpP:=P; if (Enable = '1') then if (really_rdy = '1') then if MCycle = "000" then if LDA = '1' then ABC(7 downto 0) <= ALU_Q; end if; if LDX = '1' then X(7 downto 0) <= ALU_Q; end if; if LDY = '1' then Y(7 downto 0) <= ALU_Q; end if; if (LDA or LDX or LDY) = '1' then tmpP:=P_Out; end if; end if; if SaveP = '1' then tmpP:=P_Out; end if; if LDP = '1' then tmpP:=ALU_Q; end if; if IR(4 downto 0) = "11000" then case IR(7 downto 5) is when "000" =>--0x18(clc) tmpP(Flag_C) := '0'; when "001" =>--0x38(sec) tmpP(Flag_C) := '1'; when "010" =>--0x58(cli) tmpP(Flag_I) := '0'; when "011" =>--0x78(sei) tmpP(Flag_I) := '1'; when "101" =>--0xb8(clv) tmpP(Flag_V) := '0'; when "110" =>--0xd8(cld) tmpP(Flag_D) := '0'; when "111" =>--0xf8(sed) tmpP(Flag_D) := '1'; when others => end case; end if; tmpP(Flag_B) := '1'; if IR = "00000000" and MCycle = "100" and RstCycle = '0' then --This should happen after P has been pushed to stack tmpP(Flag_I) := '1'; end if; if SO_n_o = '1' and SO_n = '0' then tmpP(Flag_V) := '1'; end if; if RstCycle = '1' then tmpP(Flag_I) := '1'; tmpP(Flag_D) := '0'; end if; tmpP(Flag_1) := '1'; P<=tmpP;--new way SO_n_o <= SO_n; if IR(4 downto 0)/="10000" or Jump/="01" then -- delay interrupts during branches (checked with Lorenz test and real 6510), not best way yet, though - but works... IRQ_n_o <= IRQ_n; end if; end if; -- detect nmi even if not rdy if IR(4 downto 0)/="10000" or Jump/="01" then -- delay interrupts during branches (checked with Lorenz test and real 6510) not best way yet, though - but works... NMI_n_o <= NMI_n; end if; end if; end if; end process; --------------------------------------------------------------------------- -- -- Buses -- --------------------------------------------------------------------------- process (Res_n_i, Clk) begin if Res_n_i = '0' then BusA_r <= (others => '0'); BusB <= (others => '0'); BusB_r <= (others => '0'); AD <= (others => '0'); BAL <= (others => '0'); BAH <= (others => '0'); DL <= (others => '0'); elsif Clk'event and Clk = '1' then if (Enable = '1') then NMI_entered <= '0'; if (really_rdy = '1') then BusA_r <= BusA; BusB <= DI; -- not really nice, but no better way found yet ! if Set_Addr_To_r = Set_Addr_To_PBR or Set_Addr_To_r = Set_Addr_To_ZPG then BusB_r <= std_logic_vector(unsigned(DI(7 downto 0)) + 1); -- required for SHA end if; case BAAdd is when "01" => -- BA Inc AD <= std_logic_vector(unsigned(AD) + 1); BAL <= std_logic_vector(unsigned(BAL) + 1); when "10" => -- BA Add BAL <= std_logic_vector(resize(unsigned(BAL(7 downto 0)),9) + resize(unsigned(BusA),9)); when "11" => -- BA Adj if BAL(8) = '1' then BAH <= std_logic_vector(unsigned(BAH) + 1); end if; when others => end case; -- modified to use Y register as well if ADAdd = '1' then if (AddY = '1') then AD <= std_logic_vector(unsigned(AD) + unsigned(Y(7 downto 0))); else AD <= std_logic_vector(unsigned(AD) + unsigned(X(7 downto 0))); end if; end if; if IR = "00000000" then BAL <= (others => '1'); BAH <= (others => '1'); if RstCycle = '1' then BAL(2 downto 0) <= "100"; elsif NMICycle = '1' or (NMIAct = '1' and MCycle="100") or NMI_entered='1' then BAL(2 downto 0) <= "010"; if MCycle="100" then NMI_entered <= '1'; end if; else BAL(2 downto 0) <= "110"; end if; if Set_addr_To_r = Set_Addr_To_BA then BAL(0) <= '1'; end if; end if; if LDDI = '1' then DL <= DI; end if; if LDALU = '1' then DL <= ALU_Q; end if; if LDAD = '1' then AD <= DI; end if; if LDBAL = '1' then BAL(7 downto 0) <= DI; end if; if LDBAH = '1' then BAH <= DI; end if; end if; end if; end if; end process; Break <= (BreakAtNA and not BAL(8)) or (PCAdd and not PCAdder(8)); with Set_BusA_To select BusA <= DI when Set_BusA_To_DI, ABC(7 downto 0) when Set_BusA_To_ABC, X(7 downto 0) when Set_BusA_To_X, Y(7 downto 0) when Set_BusA_To_Y, std_logic_vector(S(7 downto 0)) when Set_BusA_To_S, P when Set_BusA_To_P, ABC(7 downto 0) and DI when Set_BusA_To_DA, (ABC(7 downto 0) or x"ee") and DI when Set_BusA_To_DAO,--ee for OAL instruction. constant may be different on other platforms.TODO:Move to generics (ABC(7 downto 0) or x"ee") and DI and X(7 downto 0) when Set_BusA_To_DAX,--XAA, ee for OAL instruction. constant may be different on other platforms.TODO:Move to generics ABC(7 downto 0) and X(7 downto 0) when Set_BusA_To_AAX,--SAX, SHA (others => '-') when Set_BusA_To_DONTCARE;--Can probably remove this with Set_Addr_To_r select A <= "0000000000000001" & std_logic_vector(S(7 downto 0)) when Set_Addr_To_SP, DBR & "00000000" & AD when Set_Addr_To_ZPG, "00000000" & BAH & BAL(7 downto 0) when Set_Addr_To_BA, PBR & std_logic_vector(PC(15 downto 8)) & std_logic_vector(PCAdder(7 downto 0)) when Set_Addr_To_PBR; -- This is the P that gets pushed on stack with correct B flag. I'm not sure if NMI also clears B, but I guess it does. PwithB<=(P and x"ef") when (IRQCycle='1' or NMICycle='1') else P; with Write_Data_r select DO <= DL when Write_Data_DL, ABC(7 downto 0) when Write_Data_ABC, X(7 downto 0) when Write_Data_X, Y(7 downto 0) when Write_Data_Y, std_logic_vector(S(7 downto 0)) when Write_Data_S, PwithB when Write_Data_P, std_logic_vector(PC(7 downto 0)) when Write_Data_PCL, std_logic_vector(PC(15 downto 8)) when Write_Data_PCH, ABC(7 downto 0) and X(7 downto 0) when Write_Data_AX, ABC(7 downto 0) and X(7 downto 0) and BusB_r(7 downto 0) when Write_Data_AXB, -- no better way found yet... X(7 downto 0) and BusB_r(7 downto 0) when Write_Data_XB, -- no better way found yet... Y(7 downto 0) and BusB_r(7 downto 0) when Write_Data_YB, -- no better way found yet... (others=>'-') when Write_Data_DONTCARE;--Can probably remove this ------------------------------------------------------------------------- -- -- Main state machine -- ------------------------------------------------------------------------- process (Res_n_i, Clk) begin if Res_n_i = '0' then MCycle <= "001"; RstCycle <= '1'; IRQCycle <= '0'; NMICycle <= '0'; NMIAct <= '0'; elsif Clk'event and Clk = '1' then if (Enable = '1') then if (really_rdy = '1') then if MCycle = LCycle or Break = '1' then MCycle <= "000"; RstCycle <= '0'; IRQCycle <= '0'; NMICycle <= '0'; if NMIAct = '1' and IR/=x"00" then -- delay NMI further if we just executed a BRK NMICycle <= '1'; NMIAct <= '0'; -- reset NMI edge detector if we start processing the NMI elsif IRQ_n_o = '0' and P(Flag_I) = '0' then IRQCycle <= '1'; end if; else MCycle <= std_logic_vector(unsigned(MCycle) + 1); end if; end if; --detect NMI even if not rdy if NMI_n_o = '1' and (NMI_n = '0' and (IR(4 downto 0)/="10000" or Jump/="01")) then -- branches have influence on NMI start (not best way yet, though - but works...) NMIAct <= '1'; end if; -- we entered NMI during BRK instruction if NMI_entered='1' then NMIAct <= '0'; end if; end if; end if; end process; end;
apache-2.0
463dca919d1c28f5acb9c428799ca0d9
0.506256
3.56938
false
false
false
false
tghaefli/ADD
EDK/IVK_Repos/IVK_IPLib/pcores/sg_2d_fir_plbw_v1_02_a/hdl/vhdl/sg_2d_fir.vhd
1
284,008
-------------------------------------------------------------------------------- -- This file is owned and controlled by Xilinx and must be used solely -- -- for design, simulation, implementation and creation of design files -- -- limited to Xilinx devices or technologies. Use with non-Xilinx -- -- devices or technologies is expressly prohibited and immediately -- -- terminates your license. -- -- -- -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY -- -- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -- -- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE -- -- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS -- -- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY -- -- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY -- -- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY -- -- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- -- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- -- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- -- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- -- PARTICULAR PURPOSE. -- -- -- -- Xilinx products are not intended for use in life support appliances, -- -- devices, or systems. Use in such applications are expressly -- -- prohibited. -- -- -- -- (c) Copyright 1995-2012 Xilinx, Inc. -- -- All rights reserved. -- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -- You must compile the wrapper file addsb_11_0_48bcbc42a6774592.vhd when simulating -- the core, addsb_11_0_48bcbc42a6774592. When compiling the wrapper file, be sure to -- reference the XilinxCoreLib VHDL simulation library. For detailed -- instructions, please refer to the "CORE Generator Help". -- The synthesis directives "translate_off/translate_on" specified -- below are supported by Xilinx, Mentor Graphics and Synplicity -- synthesis tools. Ensure they are correct for your synthesis tool(s). LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- synthesis translate_off LIBRARY XilinxCoreLib; -- synthesis translate_on ENTITY addsb_11_0_48bcbc42a6774592 IS PORT ( a : IN STD_LOGIC_VECTOR(20 DOWNTO 0); b : IN STD_LOGIC_VECTOR(20 DOWNTO 0); clk : IN STD_LOGIC; ce : IN STD_LOGIC; s : OUT STD_LOGIC_VECTOR(20 DOWNTO 0) ); END addsb_11_0_48bcbc42a6774592; ARCHITECTURE addsb_11_0_48bcbc42a6774592_a OF addsb_11_0_48bcbc42a6774592 IS -- synthesis translate_off COMPONENT wrapped_addsb_11_0_48bcbc42a6774592 PORT ( a : IN STD_LOGIC_VECTOR(20 DOWNTO 0); b : IN STD_LOGIC_VECTOR(20 DOWNTO 0); clk : IN STD_LOGIC; ce : IN STD_LOGIC; s : OUT STD_LOGIC_VECTOR(20 DOWNTO 0) ); END COMPONENT; -- Configuration specification FOR ALL : wrapped_addsb_11_0_48bcbc42a6774592 USE ENTITY XilinxCoreLib.c_addsub_v11_0(behavioral) GENERIC MAP ( c_a_type => 0, c_a_width => 21, c_add_mode => 0, c_ainit_val => "0", c_b_constant => 0, c_b_type => 0, c_b_value => "000000000000000000000", c_b_width => 21, c_borrow_low => 1, c_bypass_low => 0, c_ce_overrides_bypass => 1, c_ce_overrides_sclr => 0, c_has_bypass => 0, c_has_c_in => 0, c_has_c_out => 0, c_has_ce => 1, c_has_sclr => 0, c_has_sinit => 0, c_has_sset => 0, c_implementation => 0, c_latency => 1, c_out_width => 21, c_sclr_overrides_sset => 0, c_sinit_val => "0", c_verbosity => 0, c_xdevicefamily => "spartan6" ); -- synthesis translate_on BEGIN -- synthesis translate_off U0 : wrapped_addsb_11_0_48bcbc42a6774592 PORT MAP ( a => a, b => b, clk => clk, ce => ce, s => s ); -- synthesis translate_on END addsb_11_0_48bcbc42a6774592_a; -------------------------------------------------------------------------------- -- This file is owned and controlled by Xilinx and must be used solely -- -- for design, simulation, implementation and creation of design files -- -- limited to Xilinx devices or technologies. Use with non-Xilinx -- -- devices or technologies is expressly prohibited and immediately -- -- terminates your license. -- -- -- -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY -- -- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -- -- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE -- -- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS -- -- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY -- -- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY -- -- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY -- -- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- -- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- -- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- -- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- -- PARTICULAR PURPOSE. -- -- -- -- Xilinx products are not intended for use in life support appliances, -- -- devices, or systems. Use in such applications are expressly -- -- prohibited. -- -- -- -- (c) Copyright 1995-2012 Xilinx, Inc. -- -- All rights reserved. -- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -- You must compile the wrapper file addsb_11_0_da33f2d4b3b54185.vhd when simulating -- the core, addsb_11_0_da33f2d4b3b54185. When compiling the wrapper file, be sure to -- reference the XilinxCoreLib VHDL simulation library. For detailed -- instructions, please refer to the "CORE Generator Help". -- The synthesis directives "translate_off/translate_on" specified -- below are supported by Xilinx, Mentor Graphics and Synplicity -- synthesis tools. Ensure they are correct for your synthesis tool(s). LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- synthesis translate_off LIBRARY XilinxCoreLib; -- synthesis translate_on ENTITY addsb_11_0_da33f2d4b3b54185 IS PORT ( a : IN STD_LOGIC_VECTOR(19 DOWNTO 0); b : IN STD_LOGIC_VECTOR(19 DOWNTO 0); clk : IN STD_LOGIC; ce : IN STD_LOGIC; s : OUT STD_LOGIC_VECTOR(19 DOWNTO 0) ); END addsb_11_0_da33f2d4b3b54185; ARCHITECTURE addsb_11_0_da33f2d4b3b54185_a OF addsb_11_0_da33f2d4b3b54185 IS -- synthesis translate_off COMPONENT wrapped_addsb_11_0_da33f2d4b3b54185 PORT ( a : IN STD_LOGIC_VECTOR(19 DOWNTO 0); b : IN STD_LOGIC_VECTOR(19 DOWNTO 0); clk : IN STD_LOGIC; ce : IN STD_LOGIC; s : OUT STD_LOGIC_VECTOR(19 DOWNTO 0) ); END COMPONENT; -- Configuration specification FOR ALL : wrapped_addsb_11_0_da33f2d4b3b54185 USE ENTITY XilinxCoreLib.c_addsub_v11_0(behavioral) GENERIC MAP ( c_a_type => 0, c_a_width => 20, c_add_mode => 0, c_ainit_val => "0", c_b_constant => 0, c_b_type => 0, c_b_value => "00000000000000000000", c_b_width => 20, c_borrow_low => 1, c_bypass_low => 0, c_ce_overrides_bypass => 1, c_ce_overrides_sclr => 0, c_has_bypass => 0, c_has_c_in => 0, c_has_c_out => 0, c_has_ce => 1, c_has_sclr => 0, c_has_sinit => 0, c_has_sset => 0, c_implementation => 0, c_latency => 1, c_out_width => 20, c_sclr_overrides_sset => 0, c_sinit_val => "0", c_verbosity => 0, c_xdevicefamily => "spartan6" ); -- synthesis translate_on BEGIN -- synthesis translate_off U0 : wrapped_addsb_11_0_da33f2d4b3b54185 PORT MAP ( a => a, b => b, clk => clk, ce => ce, s => s ); -- synthesis translate_on END addsb_11_0_da33f2d4b3b54185_a; -------------------------------------------------------------------------------- -- This file is owned and controlled by Xilinx and must be used solely -- -- for design, simulation, implementation and creation of design files -- -- limited to Xilinx devices or technologies. Use with non-Xilinx -- -- devices or technologies is expressly prohibited and immediately -- -- terminates your license. -- -- -- -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY -- -- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -- -- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE -- -- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS -- -- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY -- -- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY -- -- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY -- -- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- -- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- -- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- -- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- -- PARTICULAR PURPOSE. -- -- -- -- Xilinx products are not intended for use in life support appliances, -- -- devices, or systems. Use in such applications are expressly -- -- prohibited. -- -- -- -- (c) Copyright 1995-2012 Xilinx, Inc. -- -- All rights reserved. -- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -- You must compile the wrapper file addsb_11_0_e7b4231f2ca96446.vhd when simulating -- the core, addsb_11_0_e7b4231f2ca96446. When compiling the wrapper file, be sure to -- reference the XilinxCoreLib VHDL simulation library. For detailed -- instructions, please refer to the "CORE Generator Help". -- The synthesis directives "translate_off/translate_on" specified -- below are supported by Xilinx, Mentor Graphics and Synplicity -- synthesis tools. Ensure they are correct for your synthesis tool(s). LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- synthesis translate_off LIBRARY XilinxCoreLib; -- synthesis translate_on ENTITY addsb_11_0_e7b4231f2ca96446 IS PORT ( a : IN STD_LOGIC_VECTOR(21 DOWNTO 0); b : IN STD_LOGIC_VECTOR(21 DOWNTO 0); clk : IN STD_LOGIC; ce : IN STD_LOGIC; s : OUT STD_LOGIC_VECTOR(21 DOWNTO 0) ); END addsb_11_0_e7b4231f2ca96446; ARCHITECTURE addsb_11_0_e7b4231f2ca96446_a OF addsb_11_0_e7b4231f2ca96446 IS -- synthesis translate_off COMPONENT wrapped_addsb_11_0_e7b4231f2ca96446 PORT ( a : IN STD_LOGIC_VECTOR(21 DOWNTO 0); b : IN STD_LOGIC_VECTOR(21 DOWNTO 0); clk : IN STD_LOGIC; ce : IN STD_LOGIC; s : OUT STD_LOGIC_VECTOR(21 DOWNTO 0) ); END COMPONENT; -- Configuration specification FOR ALL : wrapped_addsb_11_0_e7b4231f2ca96446 USE ENTITY XilinxCoreLib.c_addsub_v11_0(behavioral) GENERIC MAP ( c_a_type => 0, c_a_width => 22, c_add_mode => 0, c_ainit_val => "0", c_b_constant => 0, c_b_type => 0, c_b_value => "0000000000000000000000", c_b_width => 22, c_borrow_low => 1, c_bypass_low => 0, c_ce_overrides_bypass => 1, c_ce_overrides_sclr => 0, c_has_bypass => 0, c_has_c_in => 0, c_has_c_out => 0, c_has_ce => 1, c_has_sclr => 0, c_has_sinit => 0, c_has_sset => 0, c_implementation => 0, c_latency => 1, c_out_width => 22, c_sclr_overrides_sset => 0, c_sinit_val => "0", c_verbosity => 0, c_xdevicefamily => "spartan6" ); -- synthesis translate_on BEGIN -- synthesis translate_off U0 : wrapped_addsb_11_0_e7b4231f2ca96446 PORT MAP ( a => a, b => b, clk => clk, ce => ce, s => s ); -- synthesis translate_on END addsb_11_0_e7b4231f2ca96446_a; -------------------------------------------------------------------------------- -- This file is owned and controlled by Xilinx and must be used solely -- -- for design, simulation, implementation and creation of design files -- -- limited to Xilinx devices or technologies. Use with non-Xilinx -- -- devices or technologies is expressly prohibited and immediately -- -- terminates your license. -- -- -- -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY -- -- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -- -- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE -- -- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS -- -- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY -- -- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY -- -- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY -- -- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- -- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- -- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- -- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- -- PARTICULAR PURPOSE. -- -- -- -- Xilinx products are not intended for use in life support appliances, -- -- devices, or systems. Use in such applications are expressly -- -- prohibited. -- -- -- -- (c) Copyright 1995-2012 Xilinx, Inc. -- -- All rights reserved. -- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -- You must compile the wrapper file bmg_62_05852d43925e39b8.vhd when simulating -- the core, bmg_62_05852d43925e39b8. When compiling the wrapper file, be sure to -- reference the XilinxCoreLib VHDL simulation library. For detailed -- instructions, please refer to the "CORE Generator Help". -- The synthesis directives "translate_off/translate_on" specified -- below are supported by Xilinx, Mentor Graphics and Synplicity -- synthesis tools. Ensure they are correct for your synthesis tool(s). LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- synthesis translate_off LIBRARY XilinxCoreLib; -- synthesis translate_on ENTITY bmg_62_05852d43925e39b8 IS PORT ( clka : IN STD_LOGIC; ena : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(4 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(4 DOWNTO 0) ); END bmg_62_05852d43925e39b8; ARCHITECTURE bmg_62_05852d43925e39b8_a OF bmg_62_05852d43925e39b8 IS -- synthesis translate_off COMPONENT wrapped_bmg_62_05852d43925e39b8 PORT ( clka : IN STD_LOGIC; ena : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(4 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(4 DOWNTO 0) ); END COMPONENT; -- Configuration specification FOR ALL : wrapped_bmg_62_05852d43925e39b8 USE ENTITY XilinxCoreLib.blk_mem_gen_v6_2(behavioral) GENERIC MAP ( c_addra_width => 12, c_addrb_width => 12, c_algorithm => 0, c_axi_id_width => 4, c_axi_slave_type => 0, c_axi_type => 1, c_byte_size => 9, c_common_clk => 0, c_default_data => "0", c_disable_warn_bhv_coll => 0, c_disable_warn_bhv_range => 0, c_family => "spartan6", c_has_axi_id => 0, c_has_ena => 1, c_has_enb => 0, c_has_injecterr => 0, c_has_mem_output_regs_a => 0, c_has_mem_output_regs_b => 0, c_has_mux_output_regs_a => 0, c_has_mux_output_regs_b => 0, c_has_regcea => 0, c_has_regceb => 0, c_has_rsta => 0, c_has_rstb => 0, c_has_softecc_input_regs_a => 0, c_has_softecc_output_regs_b => 0, c_init_file_name => "bmg_62_05852d43925e39b8.mif", c_inita_val => "0", c_initb_val => "0", c_interface_type => 0, c_load_init_file => 1, c_mem_type => 0, c_mux_pipeline_stages => 0, c_prim_type => 2, c_read_depth_a => 4096, c_read_depth_b => 4096, c_read_width_a => 5, c_read_width_b => 5, c_rst_priority_a => "CE", c_rst_priority_b => "CE", c_rst_type => "SYNC", c_rstram_a => 0, c_rstram_b => 0, c_sim_collision_check => "ALL", c_use_byte_wea => 0, c_use_byte_web => 0, c_use_default_data => 0, c_use_ecc => 0, c_use_softecc => 0, c_wea_width => 1, c_web_width => 1, c_write_depth_a => 4096, c_write_depth_b => 4096, c_write_mode_a => "READ_FIRST", c_write_mode_b => "WRITE_FIRST", c_write_width_a => 5, c_write_width_b => 5, c_xdevicefamily => "spartan6" ); -- synthesis translate_on BEGIN -- synthesis translate_off U0 : wrapped_bmg_62_05852d43925e39b8 PORT MAP ( clka => clka, ena => ena, wea => wea, addra => addra, dina => dina, douta => douta ); -- synthesis translate_on END bmg_62_05852d43925e39b8_a; -------------------------------------------------------------------------------- -- This file is owned and controlled by Xilinx and must be used solely -- -- for design, simulation, implementation and creation of design files -- -- limited to Xilinx devices or technologies. Use with non-Xilinx -- -- devices or technologies is expressly prohibited and immediately -- -- terminates your license. -- -- -- -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY -- -- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -- -- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE -- -- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS -- -- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY -- -- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY -- -- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY -- -- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- -- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- -- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- -- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- -- PARTICULAR PURPOSE. -- -- -- -- Xilinx products are not intended for use in life support appliances, -- -- devices, or systems. Use in such applications are expressly -- -- prohibited. -- -- -- -- (c) Copyright 1995-2012 Xilinx, Inc. -- -- All rights reserved. -- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -- You must compile the wrapper file bmg_62_54b11b852dca329b.vhd when simulating -- the core, bmg_62_54b11b852dca329b. When compiling the wrapper file, be sure to -- reference the XilinxCoreLib VHDL simulation library. For detailed -- instructions, please refer to the "CORE Generator Help". -- The synthesis directives "translate_off/translate_on" specified -- below are supported by Xilinx, Mentor Graphics and Synplicity -- synthesis tools. Ensure they are correct for your synthesis tool(s). LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- synthesis translate_off LIBRARY XilinxCoreLib; -- synthesis translate_on ENTITY bmg_62_54b11b852dca329b IS PORT ( clka : IN STD_LOGIC; ena : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END bmg_62_54b11b852dca329b; ARCHITECTURE bmg_62_54b11b852dca329b_a OF bmg_62_54b11b852dca329b IS -- synthesis translate_off COMPONENT wrapped_bmg_62_54b11b852dca329b PORT ( clka : IN STD_LOGIC; ena : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END COMPONENT; -- Configuration specification FOR ALL : wrapped_bmg_62_54b11b852dca329b USE ENTITY XilinxCoreLib.blk_mem_gen_v6_2(behavioral) GENERIC MAP ( c_addra_width => 12, c_addrb_width => 12, c_algorithm => 0, c_axi_id_width => 4, c_axi_slave_type => 0, c_axi_type => 1, c_byte_size => 9, c_common_clk => 0, c_default_data => "0", c_disable_warn_bhv_coll => 0, c_disable_warn_bhv_range => 0, c_family => "spartan6", c_has_axi_id => 0, c_has_ena => 1, c_has_enb => 0, c_has_injecterr => 0, c_has_mem_output_regs_a => 0, c_has_mem_output_regs_b => 0, c_has_mux_output_regs_a => 0, c_has_mux_output_regs_b => 0, c_has_regcea => 0, c_has_regceb => 0, c_has_rsta => 0, c_has_rstb => 0, c_has_softecc_input_regs_a => 0, c_has_softecc_output_regs_b => 0, c_init_file_name => "bmg_62_54b11b852dca329b.mif", c_inita_val => "0", c_initb_val => "0", c_interface_type => 0, c_load_init_file => 1, c_mem_type => 0, c_mux_pipeline_stages => 0, c_prim_type => 2, c_read_depth_a => 4096, c_read_depth_b => 4096, c_read_width_a => 8, c_read_width_b => 8, c_rst_priority_a => "CE", c_rst_priority_b => "CE", c_rst_type => "SYNC", c_rstram_a => 0, c_rstram_b => 0, c_sim_collision_check => "ALL", c_use_byte_wea => 0, c_use_byte_web => 0, c_use_default_data => 0, c_use_ecc => 0, c_use_softecc => 0, c_wea_width => 1, c_web_width => 1, c_write_depth_a => 4096, c_write_depth_b => 4096, c_write_mode_a => "READ_FIRST", c_write_mode_b => "WRITE_FIRST", c_write_width_a => 8, c_write_width_b => 8, c_xdevicefamily => "spartan6" ); -- synthesis translate_on BEGIN -- synthesis translate_off U0 : wrapped_bmg_62_54b11b852dca329b PORT MAP ( clka => clka, ena => ena, wea => wea, addra => addra, dina => dina, douta => douta ); -- synthesis translate_on END bmg_62_54b11b852dca329b_a; -------------------------------------------------------------------------------- -- This file is owned and controlled by Xilinx and must be used solely -- -- for design, simulation, implementation and creation of design files -- -- limited to Xilinx devices or technologies. Use with non-Xilinx -- -- devices or technologies is expressly prohibited and immediately -- -- terminates your license. -- -- -- -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY -- -- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -- -- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE -- -- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS -- -- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY -- -- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY -- -- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY -- -- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- -- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- -- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- -- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- -- PARTICULAR PURPOSE. -- -- -- -- Xilinx products are not intended for use in life support appliances, -- -- devices, or systems. Use in such applications are expressly -- -- prohibited. -- -- -- -- (c) Copyright 1995-2012 Xilinx, Inc. -- -- All rights reserved. -- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -- You must compile the wrapper file cntr_11_0_862f833518f4973a.vhd when simulating -- the core, cntr_11_0_862f833518f4973a. When compiling the wrapper file, be sure to -- reference the XilinxCoreLib VHDL simulation library. For detailed -- instructions, please refer to the "CORE Generator Help". -- The synthesis directives "translate_off/translate_on" specified -- below are supported by Xilinx, Mentor Graphics and Synplicity -- synthesis tools. Ensure they are correct for your synthesis tool(s). LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- synthesis translate_off LIBRARY XilinxCoreLib; -- synthesis translate_on ENTITY cntr_11_0_862f833518f4973a IS PORT ( clk : IN STD_LOGIC; ce : IN STD_LOGIC; sinit : IN STD_LOGIC; q : OUT STD_LOGIC_VECTOR(4 DOWNTO 0) ); END cntr_11_0_862f833518f4973a; ARCHITECTURE cntr_11_0_862f833518f4973a_a OF cntr_11_0_862f833518f4973a IS -- synthesis translate_off COMPONENT wrapped_cntr_11_0_862f833518f4973a PORT ( clk : IN STD_LOGIC; ce : IN STD_LOGIC; sinit : IN STD_LOGIC; q : OUT STD_LOGIC_VECTOR(4 DOWNTO 0) ); END COMPONENT; -- Configuration specification FOR ALL : wrapped_cntr_11_0_862f833518f4973a USE ENTITY XilinxCoreLib.c_counter_binary_v11_0(behavioral) GENERIC MAP ( c_ainit_val => "0", c_ce_overrides_sync => 0, c_count_by => "1", c_count_mode => 0, c_count_to => "1", c_fb_latency => 0, c_has_ce => 1, c_has_load => 0, c_has_sclr => 0, c_has_sinit => 1, c_has_sset => 0, c_has_thresh0 => 0, c_implementation => 0, c_latency => 1, c_load_low => 0, c_restrict_count => 0, c_sclr_overrides_sset => 1, c_sinit_val => "0", c_thresh0_value => "1", c_verbosity => 0, c_width => 5, c_xdevicefamily => "spartan6" ); -- synthesis translate_on BEGIN -- synthesis translate_off U0 : wrapped_cntr_11_0_862f833518f4973a PORT MAP ( clk => clk, ce => ce, sinit => sinit, q => q ); -- synthesis translate_on END cntr_11_0_862f833518f4973a_a; -------------------------------------------------------------------------------- -- This file is owned and controlled by Xilinx and must be used solely -- -- for design, simulation, implementation and creation of design files -- -- limited to Xilinx devices or technologies. Use with non-Xilinx -- -- devices or technologies is expressly prohibited and immediately -- -- terminates your license. -- -- -- -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY -- -- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -- -- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE -- -- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS -- -- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY -- -- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY -- -- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY -- -- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- -- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- -- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- -- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- -- PARTICULAR PURPOSE. -- -- -- -- Xilinx products are not intended for use in life support appliances, -- -- devices, or systems. Use in such applications are expressly -- -- prohibited. -- -- -- -- (c) Copyright 1995-2012 Xilinx, Inc. -- -- All rights reserved. -- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -- You must compile the wrapper file cntr_11_0_e859c6662c373192.vhd when simulating -- the core, cntr_11_0_e859c6662c373192. When compiling the wrapper file, be sure to -- reference the XilinxCoreLib VHDL simulation library. For detailed -- instructions, please refer to the "CORE Generator Help". -- The synthesis directives "translate_off/translate_on" specified -- below are supported by Xilinx, Mentor Graphics and Synplicity -- synthesis tools. Ensure they are correct for your synthesis tool(s). LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- synthesis translate_off LIBRARY XilinxCoreLib; -- synthesis translate_on ENTITY cntr_11_0_e859c6662c373192 IS PORT ( clk : IN STD_LOGIC; ce : IN STD_LOGIC; sinit : IN STD_LOGIC; q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) ); END cntr_11_0_e859c6662c373192; ARCHITECTURE cntr_11_0_e859c6662c373192_a OF cntr_11_0_e859c6662c373192 IS -- synthesis translate_off COMPONENT wrapped_cntr_11_0_e859c6662c373192 PORT ( clk : IN STD_LOGIC; ce : IN STD_LOGIC; sinit : IN STD_LOGIC; q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) ); END COMPONENT; -- Configuration specification FOR ALL : wrapped_cntr_11_0_e859c6662c373192 USE ENTITY XilinxCoreLib.c_counter_binary_v11_0(behavioral) GENERIC MAP ( c_ainit_val => "0", c_ce_overrides_sync => 0, c_count_by => "1", c_count_mode => 0, c_count_to => "1", c_fb_latency => 0, c_has_ce => 1, c_has_load => 0, c_has_sclr => 0, c_has_sinit => 1, c_has_sset => 0, c_has_thresh0 => 0, c_implementation => 0, c_latency => 1, c_load_low => 0, c_restrict_count => 0, c_sclr_overrides_sset => 1, c_sinit_val => "0", c_thresh0_value => "1", c_verbosity => 0, c_width => 3, c_xdevicefamily => "spartan6" ); -- synthesis translate_on BEGIN -- synthesis translate_off U0 : wrapped_cntr_11_0_e859c6662c373192 PORT MAP ( clk => clk, ce => ce, sinit => sinit, q => q ); -- synthesis translate_on END cntr_11_0_e859c6662c373192_a; -------------------------------------------------------------------------------- -- (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. -- -- -- -- This file contains confidential and proprietary information -- -- of Xilinx, Inc. and is protected under U.S. and -- -- international copyright and other intellectual property -- -- laws. -- -- -- -- DISCLAIMER -- -- This disclaimer is not a license and does not grant any -- -- rights to the materials distributed herewith. Except as -- -- otherwise provided in a valid license issued to you by -- -- Xilinx, and to the maximum extent permitted by applicable -- -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- -- (2) Xilinx shall not be liable (whether in contract or tort, -- -- including negligence, or under any other theory of -- -- liability) for any loss or damage of any kind or nature -- -- related to, arising under or in connection with these -- -- materials, including for any direct, or any indirect, -- -- special, incidental, or consequential loss or damage -- -- (including loss of data, profits, goodwill, or any type of -- -- loss or damage suffered as a result of any action brought -- -- by a third party) even if such damage or loss was -- -- reasonably foreseeable or Xilinx had been advised of the -- -- possibility of the same. -- -- -- -- CRITICAL APPLICATIONS -- -- Xilinx products are not designed or intended to be fail- -- -- safe, or for use in any application requiring fail-safe -- -- performance, such as life-support or safety devices or -- -- systems, Class III medical devices, nuclear facilities, -- -- applications related to the deployment of airbags, or any -- -- other applications that could lead to death, personal -- -- injury, or severe property or environmental damage -- -- (individually and collectively, "Critical -- -- Applications"). Customer assumes the sole risk and -- -- liability of any use of Xilinx products in Critical -- -- Applications, subject only to applicable laws and -- -- regulations governing limitations on product liability. -- -- -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- -- PART OF THIS FILE AT ALL TIMES. -- -------------------------------------------------------------------------------- -- Generated from component ID: xilinx.com:ip:fir_compiler:5.0 -- You must compile the wrapper file fr_cmplr_v5_0_70a7f64f38920660.vhd when simulating -- the core, fr_cmplr_v5_0_70a7f64f38920660. When compiling the wrapper file, be sure to -- reference the XilinxCoreLib VHDL simulation library. For detailed -- instructions, please refer to the "CORE Generator Help". -- The synthesis directives "translate_off/translate_on" specified -- below are supported by Xilinx, Mentor Graphics and Synplicity -- synthesis tools. Ensure they are correct for your synthesis tool(s). LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- synthesis translate_off Library XilinxCoreLib; -- synthesis translate_on ENTITY fr_cmplr_v5_0_70a7f64f38920660 IS port ( clk: in std_logic; ce: in std_logic; nd: in std_logic; coef_ld: in std_logic; coef_we: in std_logic; coef_din: in std_logic_vector(6 downto 0); rfd: out std_logic; rdy: out std_logic; din: in std_logic_vector(7 downto 0); dout: out std_logic_vector(18 downto 0)); END fr_cmplr_v5_0_70a7f64f38920660; ARCHITECTURE fr_cmplr_v5_0_70a7f64f38920660_a OF fr_cmplr_v5_0_70a7f64f38920660 IS -- synthesis translate_off component wrapped_fr_cmplr_v5_0_70a7f64f38920660 port ( clk: in std_logic; ce: in std_logic; nd: in std_logic; coef_ld: in std_logic; coef_we: in std_logic; coef_din: in std_logic_vector(6 downto 0); rfd: out std_logic; rdy: out std_logic; din: in std_logic_vector(7 downto 0); dout: out std_logic_vector(18 downto 0)); end component; -- Configuration specification for all : wrapped_fr_cmplr_v5_0_70a7f64f38920660 use entity XilinxCoreLib.fir_compiler_v5_0(behavioral) generic map( coef_width => 7, c_has_sclr => 0, datapath_memtype => 0, c_component_name => "fr_cmplr_v5_0_70a7f64f38920660", c_family => "spartan6", round_mode => 0, output_width => 19, sclr_deterministic => 0, col_config => "5", coef_memtype => 0, clock_freq => 1, symmetry => 0, col_pipe_len => 4, c_latency => 11, chan_sel_width => 1, c_xdevicefamily => "spartan6", c_has_nd => 1, allow_approx => 0, num_channels => 1, data_width => 8, filter_sel_width => 1, sample_freq => 1, coef_reload => 1, neg_symmetry => 0, filter_type => 0, data_type => 1, accum_width => 19, rate_change_type => 0, ipbuff_memtype => 0, c_optimization => 1, output_reg => 1, data_memtype => 0, c_has_data_valid => 0, decim_rate => 1, coef_type => 0, filter_arch => 1, interp_rate => 1, num_taps => 5, c_mem_init_file => "fr_cmplr_v5_0_70a7f64f38920660.mif", zero_packing_factor => 1, num_paths => 1, num_filts => 1, col_mode => 0, c_has_ce => 1, chan_in_adv => 0, opbuff_memtype => 0, odd_symmetry => 1); -- synthesis translate_on BEGIN -- synthesis translate_off U0 : wrapped_fr_cmplr_v5_0_70a7f64f38920660 port map ( clk => clk, ce => ce, nd => nd, coef_ld => coef_ld, coef_we => coef_we, coef_din => coef_din, rfd => rfd, rdy => rdy, din => din, dout => dout); -- synthesis translate_on END fr_cmplr_v5_0_70a7f64f38920660_a; -------------------------------------------------------------------------------- -- This file is owned and controlled by Xilinx and must be used solely -- -- for design, simulation, implementation and creation of design files -- -- limited to Xilinx devices or technologies. Use with non-Xilinx -- -- devices or technologies is expressly prohibited and immediately -- -- terminates your license. -- -- -- -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY -- -- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -- -- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE -- -- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS -- -- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY -- -- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY -- -- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY -- -- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- -- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- -- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- -- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- -- PARTICULAR PURPOSE. -- -- -- -- Xilinx products are not intended for use in life support appliances, -- -- devices, or systems. Use in such applications are expressly -- -- prohibited. -- -- -- -- (c) Copyright 1995-2012 Xilinx, Inc. -- -- All rights reserved. -- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -- You must compile the wrapper file mult_11_2_fe92ad55b7635191.vhd when simulating -- the core, mult_11_2_fe92ad55b7635191. When compiling the wrapper file, be sure to -- reference the XilinxCoreLib VHDL simulation library. For detailed -- instructions, please refer to the "CORE Generator Help". -- The synthesis directives "translate_off/translate_on" specified -- below are supported by Xilinx, Mentor Graphics and Synplicity -- synthesis tools. Ensure they are correct for your synthesis tool(s). LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- synthesis translate_off LIBRARY XilinxCoreLib; -- synthesis translate_on ENTITY mult_11_2_fe92ad55b7635191 IS PORT ( clk : IN STD_LOGIC; a : IN STD_LOGIC_VECTOR(22 DOWNTO 0); b : IN STD_LOGIC_VECTOR(19 DOWNTO 0); ce : IN STD_LOGIC; sclr : IN STD_LOGIC; p : OUT STD_LOGIC_VECTOR(42 DOWNTO 0) ); END mult_11_2_fe92ad55b7635191; ARCHITECTURE mult_11_2_fe92ad55b7635191_a OF mult_11_2_fe92ad55b7635191 IS -- synthesis translate_off COMPONENT wrapped_mult_11_2_fe92ad55b7635191 PORT ( clk : IN STD_LOGIC; a : IN STD_LOGIC_VECTOR(22 DOWNTO 0); b : IN STD_LOGIC_VECTOR(19 DOWNTO 0); ce : IN STD_LOGIC; sclr : IN STD_LOGIC; p : OUT STD_LOGIC_VECTOR(42 DOWNTO 0) ); END COMPONENT; -- Configuration specification FOR ALL : wrapped_mult_11_2_fe92ad55b7635191 USE ENTITY XilinxCoreLib.mult_gen_v11_2(behavioral) GENERIC MAP ( c_a_type => 0, c_a_width => 23, c_b_type => 1, c_b_value => "10000001", c_b_width => 20, c_ccm_imp => 0, c_ce_overrides_sclr => 1, c_has_ce => 1, c_has_sclr => 1, c_has_zero_detect => 0, c_latency => 4, c_model_type => 0, c_mult_type => 1, c_optimize_goal => 1, c_out_high => 42, c_out_low => 0, c_round_output => 0, c_round_pt => 0, c_verbosity => 0, c_xdevicefamily => "spartan6" ); -- synthesis translate_on BEGIN -- synthesis translate_off U0 : wrapped_mult_11_2_fe92ad55b7635191 PORT MAP ( clk => clk, a => a, b => b, ce => ce, sclr => sclr, p => p ); -- synthesis translate_on END mult_11_2_fe92ad55b7635191_a; ------------------------------------------------------------------- -- System Generator version 13.2 VHDL source file. -- -- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; package conv_pkg is constant simulating : boolean := false -- synopsys translate_off or true -- synopsys translate_on ; constant xlUnsigned : integer := 1; constant xlSigned : integer := 2; constant xlFloat : integer := 3; constant xlWrap : integer := 1; constant xlSaturate : integer := 2; constant xlTruncate : integer := 1; constant xlRound : integer := 2; constant xlRoundBanker : integer := 3; constant xlAddMode : integer := 1; constant xlSubMode : integer := 2; attribute black_box : boolean; attribute syn_black_box : boolean; attribute fpga_dont_touch: string; attribute box_type : string; attribute keep : string; attribute syn_keep : boolean; function std_logic_vector_to_unsigned(inp : std_logic_vector) return unsigned; function unsigned_to_std_logic_vector(inp : unsigned) return std_logic_vector; function std_logic_vector_to_signed(inp : std_logic_vector) return signed; function signed_to_std_logic_vector(inp : signed) return std_logic_vector; function unsigned_to_signed(inp : unsigned) return signed; function signed_to_unsigned(inp : signed) return unsigned; function pos(inp : std_logic_vector; arith : INTEGER) return boolean; function all_same(inp: std_logic_vector) return boolean; function all_zeros(inp: std_logic_vector) return boolean; function is_point_five(inp: std_logic_vector) return boolean; function all_ones(inp: std_logic_vector) return boolean; function convert_type (inp : std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith, quantization, overflow : INTEGER) return std_logic_vector; function cast (inp : std_logic_vector; old_bin_pt, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector; function shift_division_result(quotient, fraction: std_logic_vector; fraction_width, shift_value, shift_dir: INTEGER) return std_logic_vector; function shift_op (inp: std_logic_vector; result_width, shift_value, shift_dir: INTEGER) return std_logic_vector; function vec_slice (inp : std_logic_vector; upper, lower : INTEGER) return std_logic_vector; function s2u_slice (inp : signed; upper, lower : INTEGER) return unsigned; function u2u_slice (inp : unsigned; upper, lower : INTEGER) return unsigned; function s2s_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER) return signed; function u2s_cast (inp : unsigned; old_bin_pt, new_width, new_bin_pt : INTEGER) return signed; function s2u_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER) return unsigned; function u2u_cast (inp : unsigned; old_bin_pt, new_width, new_bin_pt : INTEGER) return unsigned; function u2v_cast (inp : unsigned; old_bin_pt, new_width, new_bin_pt : INTEGER) return std_logic_vector; function s2v_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER) return std_logic_vector; function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector; function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector; function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector; function max_signed(width : INTEGER) return std_logic_vector; function min_signed(width : INTEGER) return std_logic_vector; function saturation_arith(inp: std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector; function wrap_arith(inp: std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector; function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER; function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER) return INTEGER; function sign_ext(inp : std_logic_vector; new_width : INTEGER) return std_logic_vector; function zero_ext(inp : std_logic_vector; new_width : INTEGER) return std_logic_vector; function zero_ext(inp : std_logic; new_width : INTEGER) return std_logic_vector; function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER) return std_logic_vector; function align_input(inp : std_logic_vector; old_width, delta, new_arith, new_width: INTEGER) return std_logic_vector; function pad_LSB(inp : std_logic_vector; new_width: integer) return std_logic_vector; function pad_LSB(inp : std_logic_vector; new_width, arith : integer) return std_logic_vector; function max(L, R: INTEGER) return INTEGER; function min(L, R: INTEGER) return INTEGER; function "="(left,right: STRING) return boolean; function boolean_to_signed (inp : boolean; width: integer) return signed; function boolean_to_unsigned (inp : boolean; width: integer) return unsigned; function boolean_to_vector (inp : boolean) return std_logic_vector; function std_logic_to_vector (inp : std_logic) return std_logic_vector; function integer_to_std_logic_vector (inp : integer; width, arith : integer) return std_logic_vector; function std_logic_vector_to_integer (inp : std_logic_vector; arith : integer) return integer; function std_logic_to_integer(constant inp : std_logic := '0') return integer; function bin_string_element_to_std_logic_vector (inp : string; width, index : integer) return std_logic_vector; function bin_string_to_std_logic_vector (inp : string) return std_logic_vector; function hex_string_to_std_logic_vector (inp : string; width : integer) return std_logic_vector; function makeZeroBinStr (width : integer) return STRING; function and_reduce(inp: std_logic_vector) return std_logic; -- synopsys translate_off function is_binary_string_invalid (inp : string) return boolean; function is_binary_string_undefined (inp : string) return boolean; function is_XorU(inp : std_logic_vector) return boolean; function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer) return real; function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer) return real; function real_to_std_logic_vector (inp : real; width, bin_pt, arith : integer) return std_logic_vector; function real_string_to_std_logic_vector (inp : string; width, bin_pt, arith : integer) return std_logic_vector; constant display_precision : integer := 20; function real_to_string (inp : real) return string; function valid_bin_string(inp : string) return boolean; function std_logic_vector_to_bin_string(inp : std_logic_vector) return string; function std_logic_to_bin_string(inp : std_logic) return string; function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer) return string; function real_to_bin_string(inp : real; width, bin_pt, arith : integer) return string; type stdlogic_to_char_t is array(std_logic) of character; constant to_char : stdlogic_to_char_t := ( 'U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z', 'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-'); -- synopsys translate_on end conv_pkg; package body conv_pkg is function std_logic_vector_to_unsigned(inp : std_logic_vector) return unsigned is begin return unsigned (inp); end; function unsigned_to_std_logic_vector(inp : unsigned) return std_logic_vector is begin return std_logic_vector(inp); end; function std_logic_vector_to_signed(inp : std_logic_vector) return signed is begin return signed (inp); end; function signed_to_std_logic_vector(inp : signed) return std_logic_vector is begin return std_logic_vector(inp); end; function unsigned_to_signed (inp : unsigned) return signed is begin return signed(std_logic_vector(inp)); end; function signed_to_unsigned (inp : signed) return unsigned is begin return unsigned(std_logic_vector(inp)); end; function pos(inp : std_logic_vector; arith : INTEGER) return boolean is constant width : integer := inp'length; variable vec : std_logic_vector(width-1 downto 0); begin vec := inp; if arith = xlUnsigned then return true; else if vec(width-1) = '0' then return true; else return false; end if; end if; return true; end; function max_signed(width : INTEGER) return std_logic_vector is variable ones : std_logic_vector(width-2 downto 0); variable result : std_logic_vector(width-1 downto 0); begin ones := (others => '1'); result(width-1) := '0'; result(width-2 downto 0) := ones; return result; end; function min_signed(width : INTEGER) return std_logic_vector is variable zeros : std_logic_vector(width-2 downto 0); variable result : std_logic_vector(width-1 downto 0); begin zeros := (others => '0'); result(width-1) := '1'; result(width-2 downto 0) := zeros; return result; end; function and_reduce(inp: std_logic_vector) return std_logic is variable result: std_logic; constant width : integer := inp'length; variable vec : std_logic_vector(width-1 downto 0); begin vec := inp; result := vec(0); if width > 1 then for i in 1 to width-1 loop result := result and vec(i); end loop; end if; return result; end; function all_same(inp: std_logic_vector) return boolean is variable result: boolean; constant width : integer := inp'length; variable vec : std_logic_vector(width-1 downto 0); begin vec := inp; result := true; if width > 0 then for i in 1 to width-1 loop if vec(i) /= vec(0) then result := false; end if; end loop; end if; return result; end; function all_zeros(inp: std_logic_vector) return boolean is constant width : integer := inp'length; variable vec : std_logic_vector(width-1 downto 0); variable zero : std_logic_vector(width-1 downto 0); variable result : boolean; begin zero := (others => '0'); vec := inp; -- synopsys translate_off if (is_XorU(vec)) then return false; end if; -- synopsys translate_on if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(zero)) then result := true; else result := false; end if; return result; end; function is_point_five(inp: std_logic_vector) return boolean is constant width : integer := inp'length; variable vec : std_logic_vector(width-1 downto 0); variable result : boolean; begin vec := inp; -- synopsys translate_off if (is_XorU(vec)) then return false; end if; -- synopsys translate_on if (width > 1) then if ((vec(width-1) = '1') and (all_zeros(vec(width-2 downto 0)) = true)) then result := true; else result := false; end if; else if (vec(width-1) = '1') then result := true; else result := false; end if; end if; return result; end; function all_ones(inp: std_logic_vector) return boolean is constant width : integer := inp'length; variable vec : std_logic_vector(width-1 downto 0); variable one : std_logic_vector(width-1 downto 0); variable result : boolean; begin one := (others => '1'); vec := inp; -- synopsys translate_off if (is_XorU(vec)) then return false; end if; -- synopsys translate_on if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(one)) then result := true; else result := false; end if; return result; end; function full_precision_num_width(quantization, overflow, old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return integer is variable result : integer; begin result := old_width + 2; return result; end; function quantized_num_width(quantization, overflow, old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return integer is variable right_of_dp, left_of_dp, result : integer; begin right_of_dp := max(new_bin_pt, old_bin_pt); left_of_dp := max((new_width - new_bin_pt), (old_width - old_bin_pt)); result := (old_width + 2) + (new_bin_pt - old_bin_pt); return result; end; function convert_type (inp : std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith, quantization, overflow : INTEGER) return std_logic_vector is constant fp_width : integer := full_precision_num_width(quantization, overflow, old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith); constant fp_bin_pt : integer := old_bin_pt; constant fp_arith : integer := old_arith; variable full_precision_result : std_logic_vector(fp_width-1 downto 0); constant q_width : integer := quantized_num_width(quantization, overflow, old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith); constant q_bin_pt : integer := new_bin_pt; constant q_arith : integer := old_arith; variable quantized_result : std_logic_vector(q_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); begin result := (others => '0'); full_precision_result := cast(inp, old_bin_pt, fp_width, fp_bin_pt, fp_arith); if (quantization = xlRound) then quantized_result := round_towards_inf(full_precision_result, fp_width, fp_bin_pt, fp_arith, q_width, q_bin_pt, q_arith); elsif (quantization = xlRoundBanker) then quantized_result := round_towards_even(full_precision_result, fp_width, fp_bin_pt, fp_arith, q_width, q_bin_pt, q_arith); else quantized_result := trunc(full_precision_result, fp_width, fp_bin_pt, fp_arith, q_width, q_bin_pt, q_arith); end if; if (overflow = xlSaturate) then result := saturation_arith(quantized_result, q_width, q_bin_pt, q_arith, new_width, new_bin_pt, new_arith); else result := wrap_arith(quantized_result, q_width, q_bin_pt, q_arith, new_width, new_bin_pt, new_arith); end if; return result; end; function cast (inp : std_logic_vector; old_bin_pt, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector is constant old_width : integer := inp'length; constant left_of_dp : integer := (new_width - new_bin_pt) - (old_width - old_bin_pt); constant right_of_dp : integer := (new_bin_pt - old_bin_pt); variable vec : std_logic_vector(old_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); variable j : integer; begin vec := inp; for i in new_width-1 downto 0 loop j := i - right_of_dp; if ( j > old_width-1) then if (new_arith = xlUnsigned) then result(i) := '0'; else result(i) := vec(old_width-1); end if; elsif ( j >= 0) then result(i) := vec(j); else result(i) := '0'; end if; end loop; return result; end; function shift_division_result(quotient, fraction: std_logic_vector; fraction_width, shift_value, shift_dir: INTEGER) return std_logic_vector is constant q_width : integer := quotient'length; constant f_width : integer := fraction'length; constant vec_MSB : integer := q_width+f_width-1; constant result_MSB : integer := q_width+fraction_width-1; constant result_LSB : integer := vec_MSB-result_MSB; variable vec : std_logic_vector(vec_MSB downto 0); variable result : std_logic_vector(result_MSB downto 0); begin vec := ( quotient & fraction ); if shift_dir = 1 then for i in vec_MSB downto 0 loop if (i < shift_value) then vec(i) := '0'; else vec(i) := vec(i-shift_value); end if; end loop; else for i in 0 to vec_MSB loop if (i > vec_MSB-shift_value) then vec(i) := vec(vec_MSB); else vec(i) := vec(i+shift_value); end if; end loop; end if; result := vec(vec_MSB downto result_LSB); return result; end; function shift_op (inp: std_logic_vector; result_width, shift_value, shift_dir: INTEGER) return std_logic_vector is constant inp_width : integer := inp'length; constant vec_MSB : integer := inp_width-1; constant result_MSB : integer := result_width-1; constant result_LSB : integer := vec_MSB-result_MSB; variable vec : std_logic_vector(vec_MSB downto 0); variable result : std_logic_vector(result_MSB downto 0); begin vec := inp; if shift_dir = 1 then for i in vec_MSB downto 0 loop if (i < shift_value) then vec(i) := '0'; else vec(i) := vec(i-shift_value); end if; end loop; else for i in 0 to vec_MSB loop if (i > vec_MSB-shift_value) then vec(i) := vec(vec_MSB); else vec(i) := vec(i+shift_value); end if; end loop; end if; result := vec(vec_MSB downto result_LSB); return result; end; function vec_slice (inp : std_logic_vector; upper, lower : INTEGER) return std_logic_vector is begin return inp(upper downto lower); end; function s2u_slice (inp : signed; upper, lower : INTEGER) return unsigned is begin return unsigned(vec_slice(std_logic_vector(inp), upper, lower)); end; function u2u_slice (inp : unsigned; upper, lower : INTEGER) return unsigned is begin return unsigned(vec_slice(std_logic_vector(inp), upper, lower)); end; function s2s_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER) return signed is begin return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned)); end; function s2u_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER) return unsigned is begin return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned)); end; function u2s_cast (inp : unsigned; old_bin_pt, new_width, new_bin_pt : INTEGER) return signed is begin return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned)); end; function u2u_cast (inp : unsigned; old_bin_pt, new_width, new_bin_pt : INTEGER) return unsigned is begin return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned)); end; function u2v_cast (inp : unsigned; old_bin_pt, new_width, new_bin_pt : INTEGER) return std_logic_vector is begin return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned); end; function s2v_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER) return std_logic_vector is begin return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned); end; function boolean_to_signed (inp : boolean; width : integer) return signed is variable result : signed(width - 1 downto 0); begin result := (others => '0'); if inp then result(0) := '1'; else result(0) := '0'; end if; return result; end; function boolean_to_unsigned (inp : boolean; width : integer) return unsigned is variable result : unsigned(width - 1 downto 0); begin result := (others => '0'); if inp then result(0) := '1'; else result(0) := '0'; end if; return result; end; function boolean_to_vector (inp : boolean) return std_logic_vector is variable result : std_logic_vector(1 - 1 downto 0); begin result := (others => '0'); if inp then result(0) := '1'; else result(0) := '0'; end if; return result; end; function std_logic_to_vector (inp : std_logic) return std_logic_vector is variable result : std_logic_vector(1 - 1 downto 0); begin result(0) := inp; return result; end; function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector is constant right_of_dp : integer := (old_bin_pt - new_bin_pt); variable vec : std_logic_vector(old_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); begin vec := inp; if right_of_dp >= 0 then if new_arith = xlUnsigned then result := zero_ext(vec(old_width-1 downto right_of_dp), new_width); else result := sign_ext(vec(old_width-1 downto right_of_dp), new_width); end if; else if new_arith = xlUnsigned then result := zero_ext(pad_LSB(vec, old_width + abs(right_of_dp)), new_width); else result := sign_ext(pad_LSB(vec, old_width + abs(right_of_dp)), new_width); end if; end if; return result; end; function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector is constant right_of_dp : integer := (old_bin_pt - new_bin_pt); constant expected_new_width : integer := old_width - right_of_dp + 1; variable vec : std_logic_vector(old_width-1 downto 0); variable one_or_zero : std_logic_vector(new_width-1 downto 0); variable truncated_val : std_logic_vector(new_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); begin vec := inp; if right_of_dp >= 0 then if new_arith = xlUnsigned then truncated_val := zero_ext(vec(old_width-1 downto right_of_dp), new_width); else truncated_val := sign_ext(vec(old_width-1 downto right_of_dp), new_width); end if; else if new_arith = xlUnsigned then truncated_val := zero_ext(pad_LSB(vec, old_width + abs(right_of_dp)), new_width); else truncated_val := sign_ext(pad_LSB(vec, old_width + abs(right_of_dp)), new_width); end if; end if; one_or_zero := (others => '0'); if (new_arith = xlSigned) then if (vec(old_width-1) = '0') then one_or_zero(0) := '1'; end if; if (right_of_dp >= 2) and (right_of_dp <= old_width) then if (all_zeros(vec(right_of_dp-2 downto 0)) = false) then one_or_zero(0) := '1'; end if; end if; if (right_of_dp >= 1) and (right_of_dp <= old_width) then if vec(right_of_dp-1) = '0' then one_or_zero(0) := '0'; end if; else one_or_zero(0) := '0'; end if; else if (right_of_dp >= 1) and (right_of_dp <= old_width) then one_or_zero(0) := vec(right_of_dp-1); end if; end if; if new_arith = xlSigned then result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) + std_logic_vector_to_signed(one_or_zero)); else result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) + std_logic_vector_to_unsigned(one_or_zero)); end if; return result; end; function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector is constant right_of_dp : integer := (old_bin_pt - new_bin_pt); constant expected_new_width : integer := old_width - right_of_dp + 1; variable vec : std_logic_vector(old_width-1 downto 0); variable one_or_zero : std_logic_vector(new_width-1 downto 0); variable truncated_val : std_logic_vector(new_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); begin vec := inp; if right_of_dp >= 0 then if new_arith = xlUnsigned then truncated_val := zero_ext(vec(old_width-1 downto right_of_dp), new_width); else truncated_val := sign_ext(vec(old_width-1 downto right_of_dp), new_width); end if; else if new_arith = xlUnsigned then truncated_val := zero_ext(pad_LSB(vec, old_width + abs(right_of_dp)), new_width); else truncated_val := sign_ext(pad_LSB(vec, old_width + abs(right_of_dp)), new_width); end if; end if; one_or_zero := (others => '0'); if (right_of_dp >= 1) and (right_of_dp <= old_width) then if (is_point_five(vec(right_of_dp-1 downto 0)) = false) then one_or_zero(0) := vec(right_of_dp-1); else one_or_zero(0) := vec(right_of_dp); end if; end if; if new_arith = xlSigned then result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) + std_logic_vector_to_signed(one_or_zero)); else result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) + std_logic_vector_to_unsigned(one_or_zero)); end if; return result; end; function saturation_arith(inp: std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector is constant left_of_dp : integer := (old_width - old_bin_pt) - (new_width - new_bin_pt); variable vec : std_logic_vector(old_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); variable overflow : boolean; begin vec := inp; overflow := true; result := (others => '0'); if (new_width >= old_width) then overflow := false; end if; if ((old_arith = xlSigned and new_arith = xlSigned) and (old_width > new_width)) then if all_same(vec(old_width-1 downto new_width-1)) then overflow := false; end if; end if; if (old_arith = xlSigned and new_arith = xlUnsigned) then if (old_width > new_width) then if all_zeros(vec(old_width-1 downto new_width)) then overflow := false; end if; else if (old_width = new_width) then if (vec(new_width-1) = '0') then overflow := false; end if; end if; end if; end if; if (old_arith = xlUnsigned and new_arith = xlUnsigned) then if (old_width > new_width) then if all_zeros(vec(old_width-1 downto new_width)) then overflow := false; end if; else if (old_width = new_width) then overflow := false; end if; end if; end if; if ((old_arith = xlUnsigned and new_arith = xlSigned) and (old_width > new_width)) then if all_same(vec(old_width-1 downto new_width-1)) then overflow := false; end if; end if; if overflow then if new_arith = xlSigned then if vec(old_width-1) = '0' then result := max_signed(new_width); else result := min_signed(new_width); end if; else if ((old_arith = xlSigned) and vec(old_width-1) = '1') then result := (others => '0'); else result := (others => '1'); end if; end if; else if (old_arith = xlSigned) and (new_arith = xlUnsigned) then if (vec(old_width-1) = '1') then vec := (others => '0'); end if; end if; if new_width <= old_width then result := vec(new_width-1 downto 0); else if new_arith = xlUnsigned then result := zero_ext(vec, new_width); else result := sign_ext(vec, new_width); end if; end if; end if; return result; end; function wrap_arith(inp: std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector is variable result : std_logic_vector(new_width-1 downto 0); variable result_arith : integer; begin if (old_arith = xlSigned) and (new_arith = xlUnsigned) then result_arith := xlSigned; end if; result := cast(inp, old_bin_pt, new_width, new_bin_pt, result_arith); return result; end; function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER is begin return max(a_bin_pt, b_bin_pt); end; function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER) return INTEGER is begin return max(a_width - a_bin_pt, b_width - b_bin_pt); end; function pad_LSB(inp : std_logic_vector; new_width: integer) return STD_LOGIC_VECTOR is constant orig_width : integer := inp'length; variable vec : std_logic_vector(orig_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); variable pos : integer; constant pad_pos : integer := new_width - orig_width - 1; begin vec := inp; pos := new_width-1; if (new_width >= orig_width) then for i in orig_width-1 downto 0 loop result(pos) := vec(i); pos := pos - 1; end loop; if pad_pos >= 0 then for i in pad_pos downto 0 loop result(i) := '0'; end loop; end if; end if; return result; end; function sign_ext(inp : std_logic_vector; new_width : INTEGER) return std_logic_vector is constant old_width : integer := inp'length; variable vec : std_logic_vector(old_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); begin vec := inp; if new_width >= old_width then result(old_width-1 downto 0) := vec; if new_width-1 >= old_width then for i in new_width-1 downto old_width loop result(i) := vec(old_width-1); end loop; end if; else result(new_width-1 downto 0) := vec(new_width-1 downto 0); end if; return result; end; function zero_ext(inp : std_logic_vector; new_width : INTEGER) return std_logic_vector is constant old_width : integer := inp'length; variable vec : std_logic_vector(old_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); begin vec := inp; if new_width >= old_width then result(old_width-1 downto 0) := vec; if new_width-1 >= old_width then for i in new_width-1 downto old_width loop result(i) := '0'; end loop; end if; else result(new_width-1 downto 0) := vec(new_width-1 downto 0); end if; return result; end; function zero_ext(inp : std_logic; new_width : INTEGER) return std_logic_vector is variable result : std_logic_vector(new_width-1 downto 0); begin result(0) := inp; for i in new_width-1 downto 1 loop result(i) := '0'; end loop; return result; end; function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER) return std_logic_vector is constant orig_width : integer := inp'length; variable vec : std_logic_vector(orig_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); begin vec := inp; if arith = xlUnsigned then result := zero_ext(vec, new_width); else result := sign_ext(vec, new_width); end if; return result; end; function pad_LSB(inp : std_logic_vector; new_width, arith: integer) return STD_LOGIC_VECTOR is constant orig_width : integer := inp'length; variable vec : std_logic_vector(orig_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); variable pos : integer; begin vec := inp; pos := new_width-1; if (arith = xlUnsigned) then result(pos) := '0'; pos := pos - 1; else result(pos) := vec(orig_width-1); pos := pos - 1; end if; if (new_width >= orig_width) then for i in orig_width-1 downto 0 loop result(pos) := vec(i); pos := pos - 1; end loop; if pos >= 0 then for i in pos downto 0 loop result(i) := '0'; end loop; end if; end if; return result; end; function align_input(inp : std_logic_vector; old_width, delta, new_arith, new_width: INTEGER) return std_logic_vector is variable vec : std_logic_vector(old_width-1 downto 0); variable padded_inp : std_logic_vector((old_width + delta)-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); begin vec := inp; if delta > 0 then padded_inp := pad_LSB(vec, old_width+delta); result := extend_MSB(padded_inp, new_width, new_arith); else result := extend_MSB(vec, new_width, new_arith); end if; return result; end; function max(L, R: INTEGER) return INTEGER is begin if L > R then return L; else return R; end if; end; function min(L, R: INTEGER) return INTEGER is begin if L < R then return L; else return R; end if; end; function "="(left,right: STRING) return boolean is begin if (left'length /= right'length) then return false; else test : for i in 1 to left'length loop if left(i) /= right(i) then return false; end if; end loop test; return true; end if; end; -- synopsys translate_off function is_binary_string_invalid (inp : string) return boolean is variable vec : string(1 to inp'length); variable result : boolean; begin vec := inp; result := false; for i in 1 to vec'length loop if ( vec(i) = 'X' ) then result := true; end if; end loop; return result; end; function is_binary_string_undefined (inp : string) return boolean is variable vec : string(1 to inp'length); variable result : boolean; begin vec := inp; result := false; for i in 1 to vec'length loop if ( vec(i) = 'U' ) then result := true; end if; end loop; return result; end; function is_XorU(inp : std_logic_vector) return boolean is constant width : integer := inp'length; variable vec : std_logic_vector(width-1 downto 0); variable result : boolean; begin vec := inp; result := false; for i in 0 to width-1 loop if (vec(i) = 'U') or (vec(i) = 'X') then result := true; end if; end loop; return result; end; function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer) return real is variable vec : std_logic_vector(inp'length-1 downto 0); variable result, shift_val, undefined_real : real; variable neg_num : boolean; begin vec := inp; result := 0.0; neg_num := false; if vec(inp'length-1) = '1' then neg_num := true; end if; for i in 0 to inp'length-1 loop if vec(i) = 'U' or vec(i) = 'X' then return undefined_real; end if; if arith = xlSigned then if neg_num then if vec(i) = '0' then result := result + 2.0**i; end if; else if vec(i) = '1' then result := result + 2.0**i; end if; end if; else if vec(i) = '1' then result := result + 2.0**i; end if; end if; end loop; if arith = xlSigned then if neg_num then result := result + 1.0; result := result * (-1.0); end if; end if; shift_val := 2.0**(-1*bin_pt); result := result * shift_val; return result; end; function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer) return real is variable result : real := 0.0; begin if inp = '1' then result := 1.0; end if; if arith = xlSigned then assert false report "It doesn't make sense to convert a 1 bit number to a signed real."; end if; return result; end; -- synopsys translate_on function integer_to_std_logic_vector (inp : integer; width, arith : integer) return std_logic_vector is variable result : std_logic_vector(width-1 downto 0); variable unsigned_val : unsigned(width-1 downto 0); variable signed_val : signed(width-1 downto 0); begin if (arith = xlSigned) then signed_val := to_signed(inp, width); result := signed_to_std_logic_vector(signed_val); else unsigned_val := to_unsigned(inp, width); result := unsigned_to_std_logic_vector(unsigned_val); end if; return result; end; function std_logic_vector_to_integer (inp : std_logic_vector; arith : integer) return integer is constant width : integer := inp'length; variable unsigned_val : unsigned(width-1 downto 0); variable signed_val : signed(width-1 downto 0); variable result : integer; begin if (arith = xlSigned) then signed_val := std_logic_vector_to_signed(inp); result := to_integer(signed_val); else unsigned_val := std_logic_vector_to_unsigned(inp); result := to_integer(unsigned_val); end if; return result; end; function std_logic_to_integer(constant inp : std_logic := '0') return integer is begin if inp = '1' then return 1; else return 0; end if; end; function makeZeroBinStr (width : integer) return STRING is variable result : string(1 to width+3); begin result(1) := '0'; result(2) := 'b'; for i in 3 to width+2 loop result(i) := '0'; end loop; result(width+3) := '.'; return result; end; -- synopsys translate_off function real_string_to_std_logic_vector (inp : string; width, bin_pt, arith : integer) return std_logic_vector is variable result : std_logic_vector(width-1 downto 0); begin result := (others => '0'); return result; end; function real_to_std_logic_vector (inp : real; width, bin_pt, arith : integer) return std_logic_vector is variable real_val : real; variable int_val : integer; variable result : std_logic_vector(width-1 downto 0) := (others => '0'); variable unsigned_val : unsigned(width-1 downto 0) := (others => '0'); variable signed_val : signed(width-1 downto 0) := (others => '0'); begin real_val := inp; int_val := integer(real_val * 2.0**(bin_pt)); if (arith = xlSigned) then signed_val := to_signed(int_val, width); result := signed_to_std_logic_vector(signed_val); else unsigned_val := to_unsigned(int_val, width); result := unsigned_to_std_logic_vector(unsigned_val); end if; return result; end; -- synopsys translate_on function valid_bin_string (inp : string) return boolean is variable vec : string(1 to inp'length); begin vec := inp; if (vec(1) = '0' and vec(2) = 'b') then return true; else return false; end if; end; function hex_string_to_std_logic_vector(inp: string; width : integer) return std_logic_vector is constant strlen : integer := inp'LENGTH; variable result : std_logic_vector(width-1 downto 0); variable bitval : std_logic_vector((strlen*4)-1 downto 0); variable posn : integer; variable ch : character; variable vec : string(1 to strlen); begin vec := inp; result := (others => '0'); posn := (strlen*4)-1; for i in 1 to strlen loop ch := vec(i); case ch is when '0' => bitval(posn downto posn-3) := "0000"; when '1' => bitval(posn downto posn-3) := "0001"; when '2' => bitval(posn downto posn-3) := "0010"; when '3' => bitval(posn downto posn-3) := "0011"; when '4' => bitval(posn downto posn-3) := "0100"; when '5' => bitval(posn downto posn-3) := "0101"; when '6' => bitval(posn downto posn-3) := "0110"; when '7' => bitval(posn downto posn-3) := "0111"; when '8' => bitval(posn downto posn-3) := "1000"; when '9' => bitval(posn downto posn-3) := "1001"; when 'A' | 'a' => bitval(posn downto posn-3) := "1010"; when 'B' | 'b' => bitval(posn downto posn-3) := "1011"; when 'C' | 'c' => bitval(posn downto posn-3) := "1100"; when 'D' | 'd' => bitval(posn downto posn-3) := "1101"; when 'E' | 'e' => bitval(posn downto posn-3) := "1110"; when 'F' | 'f' => bitval(posn downto posn-3) := "1111"; when others => bitval(posn downto posn-3) := "XXXX"; -- synopsys translate_off ASSERT false REPORT "Invalid hex value" SEVERITY ERROR; -- synopsys translate_on end case; posn := posn - 4; end loop; if (width <= strlen*4) then result := bitval(width-1 downto 0); else result((strlen*4)-1 downto 0) := bitval; end if; return result; end; function bin_string_to_std_logic_vector (inp : string) return std_logic_vector is variable pos : integer; variable vec : string(1 to inp'length); variable result : std_logic_vector(inp'length-1 downto 0); begin vec := inp; pos := inp'length-1; result := (others => '0'); for i in 1 to vec'length loop -- synopsys translate_off if (pos < 0) and (vec(i) = '0' or vec(i) = '1' or vec(i) = 'X' or vec(i) = 'U') then assert false report "Input string is larger than output std_logic_vector. Truncating output."; return result; end if; -- synopsys translate_on if vec(i) = '0' then result(pos) := '0'; pos := pos - 1; end if; if vec(i) = '1' then result(pos) := '1'; pos := pos - 1; end if; -- synopsys translate_off if (vec(i) = 'X' or vec(i) = 'U') then result(pos) := 'U'; pos := pos - 1; end if; -- synopsys translate_on end loop; return result; end; function bin_string_element_to_std_logic_vector (inp : string; width, index : integer) return std_logic_vector is constant str_width : integer := width + 4; constant inp_len : integer := inp'length; constant num_elements : integer := (inp_len + 1)/str_width; constant reverse_index : integer := (num_elements-1) - index; variable left_pos : integer; variable right_pos : integer; variable vec : string(1 to inp'length); variable result : std_logic_vector(width-1 downto 0); begin vec := inp; result := (others => '0'); if (reverse_index = 0) and (reverse_index < num_elements) and (inp_len-3 >= width) then left_pos := 1; right_pos := width + 3; result := bin_string_to_std_logic_vector(vec(left_pos to right_pos)); end if; if (reverse_index > 0) and (reverse_index < num_elements) and (inp_len-3 >= width) then left_pos := (reverse_index * str_width) + 1; right_pos := left_pos + width + 2; result := bin_string_to_std_logic_vector(vec(left_pos to right_pos)); end if; return result; end; -- synopsys translate_off function std_logic_vector_to_bin_string(inp : std_logic_vector) return string is variable vec : std_logic_vector(1 to inp'length); variable result : string(vec'range); begin vec := inp; for i in vec'range loop result(i) := to_char(vec(i)); end loop; return result; end; function std_logic_to_bin_string(inp : std_logic) return string is variable result : string(1 to 3); begin result(1) := '0'; result(2) := 'b'; result(3) := to_char(inp); return result; end; function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer) return string is variable width : integer := inp'length; variable vec : std_logic_vector(width-1 downto 0); variable str_pos : integer; variable result : string(1 to width+3); begin vec := inp; str_pos := 1; result(str_pos) := '0'; str_pos := 2; result(str_pos) := 'b'; str_pos := 3; for i in width-1 downto 0 loop if (((width+3) - bin_pt) = str_pos) then result(str_pos) := '.'; str_pos := str_pos + 1; end if; result(str_pos) := to_char(vec(i)); str_pos := str_pos + 1; end loop; if (bin_pt = 0) then result(str_pos) := '.'; end if; return result; end; function real_to_bin_string(inp : real; width, bin_pt, arith : integer) return string is variable result : string(1 to width); variable vec : std_logic_vector(width-1 downto 0); begin vec := real_to_std_logic_vector(inp, width, bin_pt, arith); result := std_logic_vector_to_bin_string(vec); return result; end; function real_to_string (inp : real) return string is variable result : string(1 to display_precision) := (others => ' '); begin result(real'image(inp)'range) := real'image(inp); return result; end; -- synopsys translate_on end conv_pkg; ------------------------------------------------------------------- -- System Generator version 13.2 VHDL source file. -- -- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- -- synopsys translate_off library unisim; use unisim.vcomponents.all; -- synopsys translate_on library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity srl17e is generic (width : integer:=16; latency : integer :=8); port (clk : in std_logic; ce : in std_logic; d : in std_logic_vector(width-1 downto 0); q : out std_logic_vector(width-1 downto 0)); end srl17e; architecture structural of srl17e is component SRL16E port (D : in STD_ULOGIC; CE : in STD_ULOGIC; CLK : in STD_ULOGIC; A0 : in STD_ULOGIC; A1 : in STD_ULOGIC; A2 : in STD_ULOGIC; A3 : in STD_ULOGIC; Q : out STD_ULOGIC); end component; attribute syn_black_box of SRL16E : component is true; attribute fpga_dont_touch of SRL16E : component is "true"; component FDE port( Q : out STD_ULOGIC; D : in STD_ULOGIC; C : in STD_ULOGIC; CE : in STD_ULOGIC); end component; attribute syn_black_box of FDE : component is true; attribute fpga_dont_touch of FDE : component is "true"; constant a : std_logic_vector(4 downto 0) := integer_to_std_logic_vector(latency-2,5,xlSigned); signal d_delayed : std_logic_vector(width-1 downto 0); signal srl16_out : std_logic_vector(width-1 downto 0); begin d_delayed <= d after 200 ps; reg_array : for i in 0 to width-1 generate srl16_used: if latency > 1 generate u1 : srl16e port map(clk => clk, d => d_delayed(i), q => srl16_out(i), ce => ce, a0 => a(0), a1 => a(1), a2 => a(2), a3 => a(3)); end generate; srl16_not_used: if latency <= 1 generate srl16_out(i) <= d_delayed(i); end generate; fde_used: if latency /= 0 generate u2 : fde port map(c => clk, d => srl16_out(i), q => q(i), ce => ce); end generate; fde_not_used: if latency = 0 generate q(i) <= srl16_out(i); end generate; end generate; end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity synth_reg is generic (width : integer := 8; latency : integer := 1); port (i : in std_logic_vector(width-1 downto 0); ce : in std_logic; clr : in std_logic; clk : in std_logic; o : out std_logic_vector(width-1 downto 0)); end synth_reg; architecture structural of synth_reg is component srl17e generic (width : integer:=16; latency : integer :=8); port (clk : in std_logic; ce : in std_logic; d : in std_logic_vector(width-1 downto 0); q : out std_logic_vector(width-1 downto 0)); end component; function calc_num_srl17es (latency : integer) return integer is variable remaining_latency : integer; variable result : integer; begin result := latency / 17; remaining_latency := latency - (result * 17); if (remaining_latency /= 0) then result := result + 1; end if; return result; end; constant complete_num_srl17es : integer := latency / 17; constant num_srl17es : integer := calc_num_srl17es(latency); constant remaining_latency : integer := latency - (complete_num_srl17es * 17); type register_array is array (num_srl17es downto 0) of std_logic_vector(width-1 downto 0); signal z : register_array; begin z(0) <= i; complete_ones : if complete_num_srl17es > 0 generate srl17e_array: for i in 0 to complete_num_srl17es-1 generate delay_comp : srl17e generic map (width => width, latency => 17) port map (clk => clk, ce => ce, d => z(i), q => z(i+1)); end generate; end generate; partial_one : if remaining_latency > 0 generate last_srl17e : srl17e generic map (width => width, latency => remaining_latency) port map (clk => clk, ce => ce, d => z(num_srl17es-1), q => z(num_srl17es)); end generate; o <= z(num_srl17es); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity synth_reg_reg is generic (width : integer := 8; latency : integer := 1); port (i : in std_logic_vector(width-1 downto 0); ce : in std_logic; clr : in std_logic; clk : in std_logic; o : out std_logic_vector(width-1 downto 0)); end synth_reg_reg; architecture behav of synth_reg_reg is type reg_array_type is array (latency-1 downto 0) of std_logic_vector(width -1 downto 0); signal reg_bank : reg_array_type := (others => (others => '0')); signal reg_bank_in : reg_array_type := (others => (others => '0')); attribute syn_allow_retiming : boolean; attribute syn_srlstyle : string; attribute syn_allow_retiming of reg_bank : signal is true; attribute syn_allow_retiming of reg_bank_in : signal is true; attribute syn_srlstyle of reg_bank : signal is "registers"; attribute syn_srlstyle of reg_bank_in : signal is "registers"; begin latency_eq_0: if latency = 0 generate o <= i; end generate latency_eq_0; latency_gt_0: if latency >= 1 generate o <= reg_bank(latency-1); reg_bank_in(0) <= i; loop_gen: for idx in latency-2 downto 0 generate reg_bank_in(idx+1) <= reg_bank(idx); end generate loop_gen; sync_loop: for sync_idx in latency-1 downto 0 generate sync_proc: process (clk) begin if clk'event and clk = '1' then if clr = '1' then reg_bank_in <= (others => (others => '0')); elsif ce = '1' then reg_bank(sync_idx) <= reg_bank_in(sync_idx); end if; end if; end process sync_proc; end generate sync_loop; end generate latency_gt_0; end behav; ------------------------------------------------------------------- -- System Generator version 13.2 VHDL source file. -- -- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- -- synopsys translate_off library unisim; use unisim.vcomponents.all; -- synopsys translate_on library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity single_reg_w_init is generic ( width: integer := 8; init_index: integer := 0; init_value: bit_vector := b"0000" ); port ( i: in std_logic_vector(width - 1 downto 0); ce: in std_logic; clr: in std_logic; clk: in std_logic; o: out std_logic_vector(width - 1 downto 0) ); end single_reg_w_init; architecture structural of single_reg_w_init is function build_init_const(width: integer; init_index: integer; init_value: bit_vector) return std_logic_vector is variable result: std_logic_vector(width - 1 downto 0); begin if init_index = 0 then result := (others => '0'); elsif init_index = 1 then result := (others => '0'); result(0) := '1'; else result := to_stdlogicvector(init_value); end if; return result; end; component fdre port ( q: out std_ulogic; d: in std_ulogic; c: in std_ulogic; ce: in std_ulogic; r: in std_ulogic ); end component; attribute syn_black_box of fdre: component is true; attribute fpga_dont_touch of fdre: component is "true"; component fdse port ( q: out std_ulogic; d: in std_ulogic; c: in std_ulogic; ce: in std_ulogic; s: in std_ulogic ); end component; attribute syn_black_box of fdse: component is true; attribute fpga_dont_touch of fdse: component is "true"; constant init_const: std_logic_vector(width - 1 downto 0) := build_init_const(width, init_index, init_value); begin fd_prim_array: for index in 0 to width - 1 generate bit_is_0: if (init_const(index) = '0') generate fdre_comp: fdre port map ( c => clk, d => i(index), q => o(index), ce => ce, r => clr ); end generate; bit_is_1: if (init_const(index) = '1') generate fdse_comp: fdse port map ( c => clk, d => i(index), q => o(index), ce => ce, s => clr ); end generate; end generate; end architecture structural; -- synopsys translate_off library unisim; use unisim.vcomponents.all; -- synopsys translate_on library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity synth_reg_w_init is generic ( width: integer := 8; init_index: integer := 0; init_value: bit_vector := b"0000"; latency: integer := 1 ); port ( i: in std_logic_vector(width - 1 downto 0); ce: in std_logic; clr: in std_logic; clk: in std_logic; o: out std_logic_vector(width - 1 downto 0) ); end synth_reg_w_init; architecture structural of synth_reg_w_init is component single_reg_w_init generic ( width: integer := 8; init_index: integer := 0; init_value: bit_vector := b"0000" ); port ( i: in std_logic_vector(width - 1 downto 0); ce: in std_logic; clr: in std_logic; clk: in std_logic; o: out std_logic_vector(width - 1 downto 0) ); end component; signal dly_i: std_logic_vector((latency + 1) * width - 1 downto 0); signal dly_clr: std_logic; begin latency_eq_0: if (latency = 0) generate o <= i; end generate; latency_gt_0: if (latency >= 1) generate dly_i((latency + 1) * width - 1 downto latency * width) <= i after 200 ps; dly_clr <= clr after 200 ps; fd_array: for index in latency downto 1 generate reg_comp: single_reg_w_init generic map ( width => width, init_index => init_index, init_value => init_value ) port map ( clk => clk, i => dly_i((index + 1) * width - 1 downto index * width), o => dly_i(index * width - 1 downto (index - 1) * width), ce => ce, clr => dly_clr ); end generate; o <= dly_i(width - 1 downto 0); end generate; end structural; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity mux_029cd20aa9 is port ( sel : in std_logic_vector((1 - 1) downto 0); d0 : in std_logic_vector((22 - 1) downto 0); d1 : in std_logic_vector((23 - 1) downto 0); y : out std_logic_vector((23 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end mux_029cd20aa9; architecture behavior of mux_029cd20aa9 is signal sel_1_20: std_logic_vector((1 - 1) downto 0); signal d0_1_24: std_logic_vector((22 - 1) downto 0); signal d1_1_27: std_logic_vector((23 - 1) downto 0); type array_type_pipe_16_22 is array (0 to (1 - 1)) of std_logic_vector((23 - 1) downto 0); signal pipe_16_22: array_type_pipe_16_22 := ( 0 => "00000000000000000000000"); signal pipe_16_22_front_din: std_logic_vector((23 - 1) downto 0); signal pipe_16_22_back: std_logic_vector((23 - 1) downto 0); signal pipe_16_22_push_front_pop_back_en: std_logic; signal unregy_join_6_1: std_logic_vector((23 - 1) downto 0); begin sel_1_20 <= sel; d0_1_24 <= d0; d1_1_27 <= d1; pipe_16_22_back <= pipe_16_22(0); proc_pipe_16_22: process (clk) is variable i: integer; begin if (clk'event and (clk = '1')) then if ((ce = '1') and (pipe_16_22_push_front_pop_back_en = '1')) then pipe_16_22(0) <= pipe_16_22_front_din; end if; end if; end process proc_pipe_16_22; proc_switch_6_1: process (d0_1_24, d1_1_27, sel_1_20) is begin case sel_1_20 is when "0" => unregy_join_6_1 <= cast(d0_1_24, 0, 23, 0, xlSigned); when others => unregy_join_6_1 <= d1_1_27; end case; end process proc_switch_6_1; pipe_16_22_front_din <= unregy_join_6_1; pipe_16_22_push_front_pop_back_en <= '1'; y <= pipe_16_22_back; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity negate_142bd36a06 is port ( ip : in std_logic_vector((22 - 1) downto 0); op : out std_logic_vector((23 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end negate_142bd36a06; architecture behavior of negate_142bd36a06 is signal ip_18_25: signed((22 - 1) downto 0); type array_type_op_mem_42_20 is array (0 to (1 - 1)) of signed((23 - 1) downto 0); signal op_mem_42_20: array_type_op_mem_42_20 := ( 0 => "00000000000000000000000"); signal op_mem_42_20_front_din: signed((23 - 1) downto 0); signal op_mem_42_20_back: signed((23 - 1) downto 0); signal op_mem_42_20_push_front_pop_back_en: std_logic; signal cast_30_16: signed((23 - 1) downto 0); signal internal_ip_30_1_neg: signed((23 - 1) downto 0); begin ip_18_25 <= std_logic_vector_to_signed(ip); op_mem_42_20_back <= op_mem_42_20(0); proc_op_mem_42_20: process (clk) is variable i: integer; begin if (clk'event and (clk = '1')) then if ((ce = '1') and (op_mem_42_20_push_front_pop_back_en = '1')) then op_mem_42_20(0) <= op_mem_42_20_front_din; end if; end if; end process proc_op_mem_42_20; cast_30_16 <= s2s_cast(ip_18_25, 0, 23, 0); internal_ip_30_1_neg <= -cast_30_16; op_mem_42_20_front_din <= internal_ip_30_1_neg; op_mem_42_20_push_front_pop_back_en <= '1'; op <= signed_to_std_logic_vector(op_mem_42_20_back); end behavior; ------------------------------------------------------------------- -- System Generator version 13.2 VHDL source file. -- -- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity xlregister is generic (d_width : integer := 5; init_value : bit_vector := b"00"); port (d : in std_logic_vector (d_width-1 downto 0); rst : in std_logic_vector(0 downto 0) := "0"; en : in std_logic_vector(0 downto 0) := "1"; ce : in std_logic; clk : in std_logic; q : out std_logic_vector (d_width-1 downto 0)); end xlregister; architecture behavior of xlregister is component synth_reg_w_init generic (width : integer; init_index : integer; init_value : bit_vector; latency : integer); port (i : in std_logic_vector(width-1 downto 0); ce : in std_logic; clr : in std_logic; clk : in std_logic; o : out std_logic_vector(width-1 downto 0)); end component; -- synopsys translate_off signal real_d, real_q : real; -- synopsys translate_on signal internal_clr : std_logic; signal internal_ce : std_logic; begin internal_clr <= rst(0) and ce; internal_ce <= en(0) and ce; synth_reg_inst : synth_reg_w_init generic map (width => d_width, init_index => 2, init_value => init_value, latency => 1) port map (i => d, ce => internal_ce, clr => internal_clr, clk => clk, o => q); end architecture behavior; ------------------------------------------------------------------- -- System Generator version 13.2 VHDL source file. -- -- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use work.conv_pkg.all; entity xlslice is generic ( new_msb : integer := 9; new_lsb : integer := 1; x_width : integer := 16; y_width : integer := 8); port ( x : in std_logic_vector (x_width-1 downto 0); y : out std_logic_vector (y_width-1 downto 0)); end xlslice; architecture behavior of xlslice is begin y <= x(new_msb downto new_lsb); end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity inverter_e5b38cca3b is port ( ip : in std_logic_vector((1 - 1) downto 0); op : out std_logic_vector((1 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end inverter_e5b38cca3b; architecture behavior of inverter_e5b38cca3b is signal ip_1_26: boolean; type array_type_op_mem_22_20 is array (0 to (1 - 1)) of boolean; signal op_mem_22_20: array_type_op_mem_22_20 := ( 0 => false); signal op_mem_22_20_front_din: boolean; signal op_mem_22_20_back: boolean; signal op_mem_22_20_push_front_pop_back_en: std_logic; signal internal_ip_12_1_bitnot: boolean; begin ip_1_26 <= ((ip) = "1"); op_mem_22_20_back <= op_mem_22_20(0); proc_op_mem_22_20: process (clk) is variable i: integer; begin if (clk'event and (clk = '1')) then if ((ce = '1') and (op_mem_22_20_push_front_pop_back_en = '1')) then op_mem_22_20(0) <= op_mem_22_20_front_din; end if; end if; end process proc_op_mem_22_20; internal_ip_12_1_bitnot <= ((not boolean_to_vector(ip_1_26)) = "1"); op_mem_22_20_push_front_pop_back_en <= '0'; op <= boolean_to_vector(internal_ip_12_1_bitnot); end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity logical_80f90b97d0 is port ( d0 : in std_logic_vector((1 - 1) downto 0); d1 : in std_logic_vector((1 - 1) downto 0); y : out std_logic_vector((1 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end logical_80f90b97d0; architecture behavior of logical_80f90b97d0 is signal d0_1_24: std_logic; signal d1_1_27: std_logic; signal fully_2_1_bit: std_logic; begin d0_1_24 <= d0(0); d1_1_27 <= d1(0); fully_2_1_bit <= d0_1_24 and d1_1_27; y <= std_logic_to_vector(fully_2_1_bit); end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity xlfir_compiler_acc9ad12ef8a3d59fab07d7a4ad1b777 is port( ce:in std_logic; ce_logic_1:in std_logic; clk:in std_logic; clk_logic_1:in std_logic; coef_din:in std_logic_vector(6 downto 0); coef_ld:in std_logic; coef_we:in std_logic; din:in std_logic_vector(7 downto 0); dout:out std_logic_vector(18 downto 0); rdy:out std_logic; rfd:out std_logic; src_ce:in std_logic; src_clk:in std_logic ); end xlfir_compiler_acc9ad12ef8a3d59fab07d7a4ad1b777; architecture behavior of xlfir_compiler_acc9ad12ef8a3d59fab07d7a4ad1b777 is component fr_cmplr_v5_0_70a7f64f38920660 port( ce:in std_logic; clk:in std_logic; coef_din:in std_logic_vector(6 downto 0); coef_ld:in std_logic; coef_we:in std_logic; din:in std_logic_vector(7 downto 0); dout:out std_logic_vector(18 downto 0); nd:in std_logic; rdy:out std_logic; rfd:out std_logic ); end component; begin fr_cmplr_v5_0_70a7f64f38920660_instance : fr_cmplr_v5_0_70a7f64f38920660 port map( ce=>ce, clk=>clk, coef_din=>coef_din, coef_ld=>coef_ld, coef_we=>coef_we, din=>din, dout=>dout, nd=>ce_logic_1, rdy=>rdy, rfd=>rfd ); end behavior; ------------------------------------------------------------------- -- System Generator version 13.2 VHDL source file. -- -- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- -- synopsys translate_off library XilinxCoreLib; -- synopsys translate_on library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use work.conv_pkg.all; entity xladdsub is generic ( core_name0: string := ""; a_width: integer := 16; a_bin_pt: integer := 4; a_arith: integer := xlUnsigned; c_in_width: integer := 16; c_in_bin_pt: integer := 4; c_in_arith: integer := xlUnsigned; c_out_width: integer := 16; c_out_bin_pt: integer := 4; c_out_arith: integer := xlUnsigned; b_width: integer := 8; b_bin_pt: integer := 2; b_arith: integer := xlUnsigned; s_width: integer := 17; s_bin_pt: integer := 4; s_arith: integer := xlUnsigned; rst_width: integer := 1; rst_bin_pt: integer := 0; rst_arith: integer := xlUnsigned; en_width: integer := 1; en_bin_pt: integer := 0; en_arith: integer := xlUnsigned; full_s_width: integer := 17; full_s_arith: integer := xlUnsigned; mode: integer := xlAddMode; extra_registers: integer := 0; latency: integer := 0; quantization: integer := xlTruncate; overflow: integer := xlWrap; c_latency: integer := 0; c_output_width: integer := 17; c_has_c_in : integer := 0; c_has_c_out : integer := 0 ); port ( a: in std_logic_vector(a_width - 1 downto 0); b: in std_logic_vector(b_width - 1 downto 0); c_in : in std_logic_vector (0 downto 0) := "0"; ce: in std_logic; clr: in std_logic := '0'; clk: in std_logic; rst: in std_logic_vector(rst_width - 1 downto 0) := "0"; en: in std_logic_vector(en_width - 1 downto 0) := "1"; c_out : out std_logic_vector (0 downto 0); s: out std_logic_vector(s_width - 1 downto 0) ); end xladdsub; architecture behavior of xladdsub is component synth_reg generic ( width: integer := 16; latency: integer := 5 ); port ( i: in std_logic_vector(width - 1 downto 0); ce: in std_logic; clr: in std_logic; clk: in std_logic; o: out std_logic_vector(width - 1 downto 0) ); end component; function format_input(inp: std_logic_vector; old_width, delta, new_arith, new_width: integer) return std_logic_vector is variable vec: std_logic_vector(old_width-1 downto 0); variable padded_inp: std_logic_vector((old_width + delta)-1 downto 0); variable result: std_logic_vector(new_width-1 downto 0); begin vec := inp; if (delta > 0) then padded_inp := pad_LSB(vec, old_width+delta); result := extend_MSB(padded_inp, new_width, new_arith); else result := extend_MSB(vec, new_width, new_arith); end if; return result; end; constant full_s_bin_pt: integer := fractional_bits(a_bin_pt, b_bin_pt); constant full_a_width: integer := full_s_width; constant full_b_width: integer := full_s_width; signal full_a: std_logic_vector(full_a_width - 1 downto 0); signal full_b: std_logic_vector(full_b_width - 1 downto 0); signal core_s: std_logic_vector(full_s_width - 1 downto 0); signal conv_s: std_logic_vector(s_width - 1 downto 0); signal temp_cout : std_logic; signal internal_clr: std_logic; signal internal_ce: std_logic; signal extra_reg_ce: std_logic; signal override: std_logic; signal logic1: std_logic_vector(0 downto 0); component addsb_11_0_e7b4231f2ca96446 port ( a: in std_logic_vector(22 - 1 downto 0); clk: in std_logic:= '0'; ce: in std_logic:= '0'; s: out std_logic_vector(c_output_width - 1 downto 0); b: in std_logic_vector(22 - 1 downto 0) ); end component; attribute syn_black_box of addsb_11_0_e7b4231f2ca96446: component is true; attribute fpga_dont_touch of addsb_11_0_e7b4231f2ca96446: component is "true"; attribute box_type of addsb_11_0_e7b4231f2ca96446: component is "black_box"; component addsb_11_0_da33f2d4b3b54185 port ( a: in std_logic_vector(20 - 1 downto 0); clk: in std_logic:= '0'; ce: in std_logic:= '0'; s: out std_logic_vector(c_output_width - 1 downto 0); b: in std_logic_vector(20 - 1 downto 0) ); end component; attribute syn_black_box of addsb_11_0_da33f2d4b3b54185: component is true; attribute fpga_dont_touch of addsb_11_0_da33f2d4b3b54185: component is "true"; attribute box_type of addsb_11_0_da33f2d4b3b54185: component is "black_box"; component addsb_11_0_48bcbc42a6774592 port ( a: in std_logic_vector(21 - 1 downto 0); clk: in std_logic:= '0'; ce: in std_logic:= '0'; s: out std_logic_vector(c_output_width - 1 downto 0); b: in std_logic_vector(21 - 1 downto 0) ); end component; attribute syn_black_box of addsb_11_0_48bcbc42a6774592: component is true; attribute fpga_dont_touch of addsb_11_0_48bcbc42a6774592: component is "true"; attribute box_type of addsb_11_0_48bcbc42a6774592: component is "black_box"; begin internal_clr <= (clr or (rst(0))) and ce; internal_ce <= ce and en(0); logic1(0) <= '1'; addsub_process: process (a, b, core_s) begin full_a <= format_input (a, a_width, b_bin_pt - a_bin_pt, a_arith, full_a_width); full_b <= format_input (b, b_width, a_bin_pt - b_bin_pt, b_arith, full_b_width); conv_s <= convert_type (core_s, full_s_width, full_s_bin_pt, full_s_arith, s_width, s_bin_pt, s_arith, quantization, overflow); end process addsub_process; comp0: if ((core_name0 = "addsb_11_0_e7b4231f2ca96446")) generate core_instance0: addsb_11_0_e7b4231f2ca96446 port map ( a => full_a, clk => clk, ce => internal_ce, s => core_s, b => full_b ); end generate; comp1: if ((core_name0 = "addsb_11_0_da33f2d4b3b54185")) generate core_instance1: addsb_11_0_da33f2d4b3b54185 port map ( a => full_a, clk => clk, ce => internal_ce, s => core_s, b => full_b ); end generate; comp2: if ((core_name0 = "addsb_11_0_48bcbc42a6774592")) generate core_instance2: addsb_11_0_48bcbc42a6774592 port map ( a => full_a, clk => clk, ce => internal_ce, s => core_s, b => full_b ); end generate; latency_test: if (extra_registers > 0) generate override_test: if (c_latency > 1) generate override_pipe: synth_reg generic map ( width => 1, latency => c_latency ) port map ( i => logic1, ce => internal_ce, clr => internal_clr, clk => clk, o(0) => override); extra_reg_ce <= ce and en(0) and override; end generate override_test; no_override: if ((c_latency = 0) or (c_latency = 1)) generate extra_reg_ce <= ce and en(0); end generate no_override; extra_reg: synth_reg generic map ( width => s_width, latency => extra_registers ) port map ( i => conv_s, ce => extra_reg_ce, clr => internal_clr, clk => clk, o => s ); cout_test: if (c_has_c_out = 1) generate c_out_extra_reg: synth_reg generic map ( width => 1, latency => extra_registers ) port map ( i(0) => temp_cout, ce => extra_reg_ce, clr => internal_clr, clk => clk, o => c_out ); end generate cout_test; end generate; latency_s: if ((latency = 0) or (extra_registers = 0)) generate s <= conv_s; end generate latency_s; latency0: if (((latency = 0) or (extra_registers = 0)) and (c_has_c_out = 1)) generate c_out(0) <= temp_cout; end generate latency0; tie_dangling_cout: if (c_has_c_out = 0) generate c_out <= "0"; end generate tie_dangling_cout; end architecture behavior; ------------------------------------------------------------------- -- System Generator version 13.2 VHDL source file. -- -- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity xlpassthrough is generic ( din_width : integer := 16; dout_width : integer := 16 ); port ( din : in std_logic_vector (din_width-1 downto 0); dout : out std_logic_vector (dout_width-1 downto 0)); end xlpassthrough; architecture passthrough_arch of xlpassthrough is begin dout <= din; end passthrough_arch; ------------------------------------------------------------------- -- System Generator version 13.2 VHDL source file. -- -- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity convert_func_call is generic ( din_width : integer := 16; din_bin_pt : integer := 4; din_arith : integer := xlUnsigned; dout_width : integer := 8; dout_bin_pt : integer := 2; dout_arith : integer := xlUnsigned; quantization : integer := xlTruncate; overflow : integer := xlWrap); port ( din : in std_logic_vector (din_width-1 downto 0); result : out std_logic_vector (dout_width-1 downto 0)); end convert_func_call; architecture behavior of convert_func_call is begin result <= convert_type(din, din_width, din_bin_pt, din_arith, dout_width, dout_bin_pt, dout_arith, quantization, overflow); end behavior; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity xlconvert is generic ( din_width : integer := 16; din_bin_pt : integer := 4; din_arith : integer := xlUnsigned; dout_width : integer := 8; dout_bin_pt : integer := 2; dout_arith : integer := xlUnsigned; en_width : integer := 1; en_bin_pt : integer := 0; en_arith : integer := xlUnsigned; bool_conversion : integer :=0; latency : integer := 0; quantization : integer := xlTruncate; overflow : integer := xlWrap); port ( din : in std_logic_vector (din_width-1 downto 0); en : in std_logic_vector (en_width-1 downto 0); ce : in std_logic; clr : in std_logic; clk : in std_logic; dout : out std_logic_vector (dout_width-1 downto 0)); end xlconvert; architecture behavior of xlconvert is component synth_reg generic (width : integer; latency : integer); port (i : in std_logic_vector(width-1 downto 0); ce : in std_logic; clr : in std_logic; clk : in std_logic; o : out std_logic_vector(width-1 downto 0)); end component; component convert_func_call generic ( din_width : integer := 16; din_bin_pt : integer := 4; din_arith : integer := xlUnsigned; dout_width : integer := 8; dout_bin_pt : integer := 2; dout_arith : integer := xlUnsigned; quantization : integer := xlTruncate; overflow : integer := xlWrap); port ( din : in std_logic_vector (din_width-1 downto 0); result : out std_logic_vector (dout_width-1 downto 0)); end component; -- synopsys translate_off -- synopsys translate_on signal result : std_logic_vector(dout_width-1 downto 0); signal internal_ce : std_logic; begin -- synopsys translate_off -- synopsys translate_on internal_ce <= ce and en(0); bool_conversion_generate : if (bool_conversion = 1) generate result <= din; end generate; std_conversion_generate : if (bool_conversion = 0) generate convert : convert_func_call generic map ( din_width => din_width, din_bin_pt => din_bin_pt, din_arith => din_arith, dout_width => dout_width, dout_bin_pt => dout_bin_pt, dout_arith => dout_arith, quantization => quantization, overflow => overflow) port map ( din => din, result => result); end generate; latency_test : if (latency > 0) generate reg : synth_reg generic map ( width => dout_width, latency => latency ) port map ( i => result, ce => internal_ce, clr => clr, clk => clk, o => dout ); end generate; latency0 : if (latency = 0) generate dout <= result; end generate latency0; end behavior; ------------------------------------------------------------------- -- System Generator version 13.2 VHDL source file. -- -- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- -- synopsys translate_off library XilinxCoreLib; -- synopsys translate_on library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use work.conv_pkg.all; entity xlmult is generic ( core_name0: string := ""; a_width: integer := 4; a_bin_pt: integer := 2; a_arith: integer := xlSigned; b_width: integer := 4; b_bin_pt: integer := 1; b_arith: integer := xlSigned; p_width: integer := 8; p_bin_pt: integer := 2; p_arith: integer := xlSigned; rst_width: integer := 1; rst_bin_pt: integer := 0; rst_arith: integer := xlUnsigned; en_width: integer := 1; en_bin_pt: integer := 0; en_arith: integer := xlUnsigned; quantization: integer := xlTruncate; overflow: integer := xlWrap; extra_registers: integer := 0; c_a_width: integer := 7; c_b_width: integer := 7; c_type: integer := 0; c_a_type: integer := 0; c_b_type: integer := 0; c_pipelined: integer := 1; c_baat: integer := 4; multsign: integer := xlSigned; c_output_width: integer := 16 ); port ( a: in std_logic_vector(a_width - 1 downto 0); b: in std_logic_vector(b_width - 1 downto 0); ce: in std_logic; clr: in std_logic; clk: in std_logic; core_ce: in std_logic := '0'; core_clr: in std_logic := '0'; core_clk: in std_logic := '0'; rst: in std_logic_vector(rst_width - 1 downto 0); en: in std_logic_vector(en_width - 1 downto 0); p: out std_logic_vector(p_width - 1 downto 0) ); end xlmult; architecture behavior of xlmult is component synth_reg generic ( width: integer := 16; latency: integer := 5 ); port ( i: in std_logic_vector(width - 1 downto 0); ce: in std_logic; clr: in std_logic; clk: in std_logic; o: out std_logic_vector(width - 1 downto 0) ); end component; component mult_11_2_fe92ad55b7635191 port ( b: in std_logic_vector(c_b_width - 1 downto 0); p: out std_logic_vector(c_output_width - 1 downto 0); clk: in std_logic; ce: in std_logic; sclr: in std_logic; a: in std_logic_vector(c_a_width - 1 downto 0) ); end component; attribute syn_black_box of mult_11_2_fe92ad55b7635191: component is true; attribute fpga_dont_touch of mult_11_2_fe92ad55b7635191: component is "true"; attribute box_type of mult_11_2_fe92ad55b7635191: component is "black_box"; signal tmp_a: std_logic_vector(c_a_width - 1 downto 0); signal conv_a: std_logic_vector(c_a_width - 1 downto 0); signal tmp_b: std_logic_vector(c_b_width - 1 downto 0); signal conv_b: std_logic_vector(c_b_width - 1 downto 0); signal tmp_p: std_logic_vector(c_output_width - 1 downto 0); signal conv_p: std_logic_vector(p_width - 1 downto 0); -- synopsys translate_off signal real_a, real_b, real_p: real; -- synopsys translate_on signal rfd: std_logic; signal rdy: std_logic; signal nd: std_logic; signal internal_ce: std_logic; signal internal_clr: std_logic; signal internal_core_ce: std_logic; begin -- synopsys translate_off -- synopsys translate_on internal_ce <= ce and en(0); internal_core_ce <= core_ce and en(0); internal_clr <= (clr or rst(0)) and ce; nd <= internal_ce; input_process: process (a,b) begin tmp_a <= zero_ext(a, c_a_width); tmp_b <= zero_ext(b, c_b_width); end process; output_process: process (tmp_p) begin conv_p <= convert_type(tmp_p, c_output_width, a_bin_pt+b_bin_pt, multsign, p_width, p_bin_pt, p_arith, quantization, overflow); end process; comp0: if ((core_name0 = "mult_11_2_fe92ad55b7635191")) generate core_instance0: mult_11_2_fe92ad55b7635191 port map ( a => tmp_a, clk => clk, ce => internal_ce, sclr => internal_clr, p => tmp_p, b => tmp_b ); end generate; latency_gt_0: if (extra_registers > 0) generate reg: synth_reg generic map ( width => p_width, latency => extra_registers ) port map ( i => conv_p, ce => internal_ce, clr => internal_clr, clk => clk, o => p ); end generate; latency_eq_0: if (extra_registers = 0) generate p <= conv_p; end generate; end architecture behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity constant_822933f89b is port ( op : out std_logic_vector((3 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end constant_822933f89b; architecture behavior of constant_822933f89b is begin op <= "000"; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity constant_a1c496ea88 is port ( op : out std_logic_vector((3 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end constant_a1c496ea88; architecture behavior of constant_a1c496ea88 is begin op <= "001"; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity constant_1f5cc32f1e is port ( op : out std_logic_vector((3 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end constant_1f5cc32f1e; architecture behavior of constant_1f5cc32f1e is begin op <= "010"; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity constant_0f59f02ba5 is port ( op : out std_logic_vector((3 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end constant_0f59f02ba5; architecture behavior of constant_0f59f02ba5 is begin op <= "011"; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity constant_469094441c is port ( op : out std_logic_vector((3 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end constant_469094441c; architecture behavior of constant_469094441c is begin op <= "100"; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity relational_8fc7f5539b is port ( a : in std_logic_vector((3 - 1) downto 0); b : in std_logic_vector((3 - 1) downto 0); op : out std_logic_vector((1 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end relational_8fc7f5539b; architecture behavior of relational_8fc7f5539b is signal a_1_31: unsigned((3 - 1) downto 0); signal b_1_34: unsigned((3 - 1) downto 0); signal result_12_3_rel: boolean; begin a_1_31 <= std_logic_vector_to_unsigned(a); b_1_34 <= std_logic_vector_to_unsigned(b); result_12_3_rel <= a_1_31 = b_1_34; op <= boolean_to_vector(result_12_3_rel); end behavior; ------------------------------------------------------------------- -- System Generator version 13.2 VHDL source file. -- -- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- -- synopsys translate_off library XilinxCoreLib; -- synopsys translate_on library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity xlcounter_limit is generic ( core_name0: string := ""; op_width: integer := 5; op_arith: integer := xlSigned; cnt_63_48: integer:= 0; cnt_47_32: integer:= 0; cnt_31_16: integer:= 0; cnt_15_0: integer:= 0; count_limited: integer := 0 ); port ( ce: in std_logic; clr: in std_logic; clk: in std_logic; op: out std_logic_vector(op_width - 1 downto 0); up: in std_logic_vector(0 downto 0) := (others => '0'); en: in std_logic_vector(0 downto 0); rst: in std_logic_vector(0 downto 0) ); end xlcounter_limit ; architecture behavior of xlcounter_limit is signal high_cnt_to: std_logic_vector(31 downto 0); signal low_cnt_to: std_logic_vector(31 downto 0); signal cnt_to: std_logic_vector(63 downto 0); signal core_sinit, op_thresh0, core_ce: std_logic; signal rst_overrides_en: std_logic; signal op_net: std_logic_vector(op_width - 1 downto 0); -- synopsys translate_off signal real_op : real; -- synopsys translate_on function equals(op, cnt_to : std_logic_vector; width, arith : integer) return std_logic is variable signed_op, signed_cnt_to : signed (width - 1 downto 0); variable unsigned_op, unsigned_cnt_to : unsigned (width - 1 downto 0); variable result : std_logic; begin -- synopsys translate_off if ((is_XorU(op)) or (is_XorU(cnt_to)) ) then result := '0'; return result; end if; -- synopsys translate_on if (op = cnt_to) then result := '1'; else result := '0'; end if; return result; end; component cntr_11_0_e859c6662c373192 port ( clk: in std_logic; ce: in std_logic; SINIT: in std_logic; q: out std_logic_vector(op_width - 1 downto 0) ); end component; attribute syn_black_box of cntr_11_0_e859c6662c373192: component is true; attribute fpga_dont_touch of cntr_11_0_e859c6662c373192: component is "true"; attribute box_type of cntr_11_0_e859c6662c373192: component is "black_box"; component cntr_11_0_862f833518f4973a port ( clk: in std_logic; ce: in std_logic; SINIT: in std_logic; q: out std_logic_vector(op_width - 1 downto 0) ); end component; attribute syn_black_box of cntr_11_0_862f833518f4973a: component is true; attribute fpga_dont_touch of cntr_11_0_862f833518f4973a: component is "true"; attribute box_type of cntr_11_0_862f833518f4973a: component is "black_box"; -- synopsys translate_off constant zeroVec : std_logic_vector(op_width - 1 downto 0) := (others => '0'); constant oneVec : std_logic_vector(op_width - 1 downto 0) := (others => '1'); constant zeroStr : string(1 to op_width) := std_logic_vector_to_bin_string(zeroVec); constant oneStr : string(1 to op_width) := std_logic_vector_to_bin_string(oneVec); -- synopsys translate_on begin -- synopsys translate_off -- synopsys translate_on cnt_to(63 downto 48) <= integer_to_std_logic_vector(cnt_63_48, 16, op_arith); cnt_to(47 downto 32) <= integer_to_std_logic_vector(cnt_47_32, 16, op_arith); cnt_to(31 downto 16) <= integer_to_std_logic_vector(cnt_31_16, 16, op_arith); cnt_to(15 downto 0) <= integer_to_std_logic_vector(cnt_15_0, 16, op_arith); op <= op_net; core_ce <= ce and en(0); rst_overrides_en <= rst(0) or en(0); limit : if (count_limited = 1) generate eq_cnt_to : process (op_net, cnt_to) begin op_thresh0 <= equals(op_net, cnt_to(op_width - 1 downto 0), op_width, op_arith); end process; core_sinit <= (op_thresh0 or clr or rst(0)) and ce and rst_overrides_en; end generate; no_limit : if (count_limited = 0) generate core_sinit <= (clr or rst(0)) and ce and rst_overrides_en; end generate; comp0: if ((core_name0 = "cntr_11_0_e859c6662c373192")) generate core_instance0: cntr_11_0_e859c6662c373192 port map ( clk => clk, ce => core_ce, SINIT => core_sinit, q => op_net ); end generate; comp1: if ((core_name0 = "cntr_11_0_862f833518f4973a")) generate core_instance1: cntr_11_0_862f833518f4973a port map ( clk => clk, ce => core_ce, SINIT => core_sinit, q => op_net ); end generate; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity constant_6293007044 is port ( op : out std_logic_vector((1 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end constant_6293007044; architecture behavior of constant_6293007044 is begin op <= "1"; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity delay_23f848c85b is port ( d : in std_logic_vector((8 - 1) downto 0); q : out std_logic_vector((8 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end delay_23f848c85b; architecture behavior of delay_23f848c85b is signal d_1_22: std_logic_vector((8 - 1) downto 0); type array_type_op_mem_20_24 is array (0 to (2 - 1)) of std_logic_vector((8 - 1) downto 0); signal op_mem_20_24: array_type_op_mem_20_24 := ( "00000000", "00000000"); signal op_mem_20_24_front_din: std_logic_vector((8 - 1) downto 0); signal op_mem_20_24_back: std_logic_vector((8 - 1) downto 0); signal op_mem_20_24_push_front_pop_back_en: std_logic; begin d_1_22 <= d; op_mem_20_24_back <= op_mem_20_24(1); proc_op_mem_20_24: process (clk) is variable i: integer; begin if (clk'event and (clk = '1')) then if ((ce = '1') and (op_mem_20_24_push_front_pop_back_en = '1')) then for i in 1 downto 1 loop op_mem_20_24(i) <= op_mem_20_24(i-1); end loop; op_mem_20_24(0) <= op_mem_20_24_front_din; end if; end if; end process proc_op_mem_20_24; op_mem_20_24_front_din <= d_1_22; op_mem_20_24_push_front_pop_back_en <= '1'; q <= op_mem_20_24_back; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity delay_9565135955 is port ( d : in std_logic_vector((8 - 1) downto 0); q : out std_logic_vector((8 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end delay_9565135955; architecture behavior of delay_9565135955 is signal d_1_22: std_logic_vector((8 - 1) downto 0); type array_type_op_mem_20_24 is array (0 to (3 - 1)) of std_logic_vector((8 - 1) downto 0); signal op_mem_20_24: array_type_op_mem_20_24 := ( "00000000", "00000000", "00000000"); signal op_mem_20_24_front_din: std_logic_vector((8 - 1) downto 0); signal op_mem_20_24_back: std_logic_vector((8 - 1) downto 0); signal op_mem_20_24_push_front_pop_back_en: std_logic; begin d_1_22 <= d; op_mem_20_24_back <= op_mem_20_24(2); proc_op_mem_20_24: process (clk) is variable i: integer; begin if (clk'event and (clk = '1')) then if ((ce = '1') and (op_mem_20_24_push_front_pop_back_en = '1')) then for i in 2 downto 1 loop op_mem_20_24(i) <= op_mem_20_24(i-1); end loop; op_mem_20_24(0) <= op_mem_20_24_front_din; end if; end if; end process proc_op_mem_20_24; op_mem_20_24_front_din <= d_1_22; op_mem_20_24_push_front_pop_back_en <= '1'; q <= op_mem_20_24_back; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity delay_fb08f2e938 is port ( d : in std_logic_vector((8 - 1) downto 0); q : out std_logic_vector((8 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end delay_fb08f2e938; architecture behavior of delay_fb08f2e938 is signal d_1_22: std_logic_vector((8 - 1) downto 0); type array_type_op_mem_20_24 is array (0 to (4 - 1)) of std_logic_vector((8 - 1) downto 0); signal op_mem_20_24: array_type_op_mem_20_24 := ( "00000000", "00000000", "00000000", "00000000"); signal op_mem_20_24_front_din: std_logic_vector((8 - 1) downto 0); signal op_mem_20_24_back: std_logic_vector((8 - 1) downto 0); signal op_mem_20_24_push_front_pop_back_en: std_logic; begin d_1_22 <= d; op_mem_20_24_back <= op_mem_20_24(3); proc_op_mem_20_24: process (clk) is variable i: integer; begin if (clk'event and (clk = '1')) then if ((ce = '1') and (op_mem_20_24_push_front_pop_back_en = '1')) then for i in 3 downto 1 loop op_mem_20_24(i) <= op_mem_20_24(i-1); end loop; op_mem_20_24(0) <= op_mem_20_24_front_din; end if; end if; end process proc_op_mem_20_24; op_mem_20_24_front_din <= d_1_22; op_mem_20_24_push_front_pop_back_en <= '1'; q <= op_mem_20_24_back; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity delay_ebec135d8a is port ( d : in std_logic_vector((8 - 1) downto 0); q : out std_logic_vector((8 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end delay_ebec135d8a; architecture behavior of delay_ebec135d8a is signal d_1_22: std_logic_vector((8 - 1) downto 0); type array_type_op_mem_20_24 is array (0 to (1 - 1)) of std_logic_vector((8 - 1) downto 0); signal op_mem_20_24: array_type_op_mem_20_24 := ( 0 => "00000000"); signal op_mem_20_24_front_din: std_logic_vector((8 - 1) downto 0); signal op_mem_20_24_back: std_logic_vector((8 - 1) downto 0); signal op_mem_20_24_push_front_pop_back_en: std_logic; begin d_1_22 <= d; op_mem_20_24_back <= op_mem_20_24(0); proc_op_mem_20_24: process (clk) is variable i: integer; begin if (clk'event and (clk = '1')) then if ((ce = '1') and (op_mem_20_24_push_front_pop_back_en = '1')) then op_mem_20_24(0) <= op_mem_20_24_front_din; end if; end if; end process proc_op_mem_20_24; op_mem_20_24_front_din <= d_1_22; op_mem_20_24_push_front_pop_back_en <= '1'; q <= op_mem_20_24_back; end behavior; ------------------------------------------------------------------- -- System Generator version 13.2 VHDL source file. -- -- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity xlspram is generic ( core_name0: string := ""; c_width: integer := 12; c_address_width: integer := 4; latency: integer := 1 ); port ( data_in: in std_logic_vector(c_width - 1 downto 0); addr: in std_logic_vector(c_address_width - 1 downto 0); we: in std_logic_vector(0 downto 0); en: in std_logic_vector(0 downto 0); rst: in std_logic_vector(0 downto 0); ce: in std_logic; clk: in std_logic; data_out: out std_logic_vector(c_width - 1 downto 0) ); end xlspram ; architecture behavior of xlspram is component synth_reg generic ( width: integer; latency: integer ); port ( i: in std_logic_vector(width - 1 downto 0); ce: in std_logic; clr: in std_logic; clk: in std_logic; o: out std_logic_vector(width - 1 downto 0) ); end component; signal core_data_out, dly_data_out: std_logic_vector(c_width - 1 downto 0); signal core_we, core_ce, sinit: std_logic; component bmg_62_54b11b852dca329b port ( addra: in std_logic_vector(c_address_width - 1 downto 0); clka: in std_logic; dina: in std_logic_vector(c_width - 1 downto 0); wea: in std_logic_vector(0 downto 0); ena: in std_logic; douta: out std_logic_vector(c_width - 1 downto 0) ); end component; attribute syn_black_box of bmg_62_54b11b852dca329b: component is true; attribute fpga_dont_touch of bmg_62_54b11b852dca329b: component is "true"; attribute box_type of bmg_62_54b11b852dca329b: component is "black_box"; component bmg_62_05852d43925e39b8 port ( addra: in std_logic_vector(c_address_width - 1 downto 0); clka: in std_logic; dina: in std_logic_vector(c_width - 1 downto 0); wea: in std_logic_vector(0 downto 0); ena: in std_logic; douta: out std_logic_vector(c_width - 1 downto 0) ); end component; attribute syn_black_box of bmg_62_05852d43925e39b8: component is true; attribute fpga_dont_touch of bmg_62_05852d43925e39b8: component is "true"; attribute box_type of bmg_62_05852d43925e39b8: component is "black_box"; begin data_out <= dly_data_out; core_we <= we(0); core_ce <= ce and en(0); sinit <= rst(0) and ce; comp0: if ((core_name0 = "bmg_62_54b11b852dca329b")) generate core_instance0: bmg_62_54b11b852dca329b port map ( addra => addr, clka => clk, dina => data_in, wea(0) => core_we, ena => core_ce, douta => core_data_out ); end generate; comp1: if ((core_name0 = "bmg_62_05852d43925e39b8")) generate core_instance1: bmg_62_05852d43925e39b8 port map ( addra => addr, clka => clk, dina => data_in, wea(0) => core_we, ena => core_ce, douta => core_data_out ); end generate; latency_test: if (latency > 1) generate reg: synth_reg generic map ( width => c_width, latency => latency - 1 ) port map ( i => core_data_out, ce => core_ce, clr => '0', clk => clk, o => dly_data_out ); end generate; latency_1: if (latency <= 1) generate dly_data_out <= core_data_out; end generate; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity delay_38f665f8aa is port ( d : in std_logic_vector((5 - 1) downto 0); q : out std_logic_vector((5 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end delay_38f665f8aa; architecture behavior of delay_38f665f8aa is signal d_1_22: std_logic_vector((5 - 1) downto 0); type array_type_op_mem_20_24 is array (0 to (2 - 1)) of std_logic_vector((5 - 1) downto 0); signal op_mem_20_24: array_type_op_mem_20_24 := ( "00000", "00000"); signal op_mem_20_24_front_din: std_logic_vector((5 - 1) downto 0); signal op_mem_20_24_back: std_logic_vector((5 - 1) downto 0); signal op_mem_20_24_push_front_pop_back_en: std_logic; begin d_1_22 <= d; op_mem_20_24_back <= op_mem_20_24(1); proc_op_mem_20_24: process (clk) is variable i: integer; begin if (clk'event and (clk = '1')) then if ((ce = '1') and (op_mem_20_24_push_front_pop_back_en = '1')) then for i in 1 downto 1 loop op_mem_20_24(i) <= op_mem_20_24(i-1); end loop; op_mem_20_24(0) <= op_mem_20_24_front_din; end if; end if; end process proc_op_mem_20_24; op_mem_20_24_front_din <= d_1_22; op_mem_20_24_push_front_pop_back_en <= '1'; q <= op_mem_20_24_back; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity concat_2b3acb49f4 is port ( in0 : in std_logic_vector((1 - 1) downto 0); in1 : in std_logic_vector((1 - 1) downto 0); in2 : in std_logic_vector((1 - 1) downto 0); in3 : in std_logic_vector((1 - 1) downto 0); in4 : in std_logic_vector((1 - 1) downto 0); y : out std_logic_vector((5 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end concat_2b3acb49f4; architecture behavior of concat_2b3acb49f4 is signal in0_1_23: unsigned((1 - 1) downto 0); signal in1_1_27: unsigned((1 - 1) downto 0); signal in2_1_31: unsigned((1 - 1) downto 0); signal in3_1_35: unsigned((1 - 1) downto 0); signal in4_1_39: unsigned((1 - 1) downto 0); signal y_2_1_concat: unsigned((5 - 1) downto 0); begin in0_1_23 <= std_logic_vector_to_unsigned(in0); in1_1_27 <= std_logic_vector_to_unsigned(in1); in2_1_31 <= std_logic_vector_to_unsigned(in2); in3_1_35 <= std_logic_vector_to_unsigned(in3); in4_1_39 <= std_logic_vector_to_unsigned(in4); y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27) & unsigned_to_std_logic_vector(in2_1_31) & unsigned_to_std_logic_vector(in3_1_35) & unsigned_to_std_logic_vector(in4_1_39)); y <= unsigned_to_std_logic_vector(y_2_1_concat); end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity delay_4714bdf2a7 is port ( d : in std_logic_vector((5 - 1) downto 0); q : out std_logic_vector((5 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end delay_4714bdf2a7; architecture behavior of delay_4714bdf2a7 is signal d_1_22: std_logic_vector((5 - 1) downto 0); type array_type_op_mem_20_24 is array (0 to (26 - 1)) of std_logic_vector((5 - 1) downto 0); signal op_mem_20_24: array_type_op_mem_20_24 := ( "00000", "00000", "00000", "00000", "00000", "00000", "00000", "00000", "00000", "00000", "00000", "00000", "00000", "00000", "00000", "00000", "00000", "00000", "00000", "00000", "00000", "00000", "00000", "00000", "00000", "00000"); signal op_mem_20_24_front_din: std_logic_vector((5 - 1) downto 0); signal op_mem_20_24_back: std_logic_vector((5 - 1) downto 0); signal op_mem_20_24_push_front_pop_back_en: std_logic; begin d_1_22 <= d; op_mem_20_24_back <= op_mem_20_24(25); proc_op_mem_20_24: process (clk) is variable i: integer; begin if (clk'event and (clk = '1')) then if ((ce = '1') and (op_mem_20_24_push_front_pop_back_en = '1')) then for i in 25 downto 1 loop op_mem_20_24(i) <= op_mem_20_24(i-1); end loop; op_mem_20_24(0) <= op_mem_20_24_front_din; end if; end if; end process proc_op_mem_20_24; op_mem_20_24_front_din <= d_1_22; op_mem_20_24_push_front_pop_back_en <= '1'; q <= op_mem_20_24_back; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity constant_fdce3802d7 is port ( op : out std_logic_vector((5 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end constant_fdce3802d7; architecture behavior of constant_fdce3802d7 is begin op <= "11001"; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity constant_963ed6358a is port ( op : out std_logic_vector((1 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end constant_963ed6358a; architecture behavior of constant_963ed6358a is begin op <= "0"; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity constant_7244cd602b is port ( op : out std_logic_vector((7 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end constant_7244cd602b; architecture behavior of constant_7244cd602b is begin op <= "0000000"; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity expr_1e33fcde03 is port ( a : in std_logic_vector((1 - 1) downto 0); b : in std_logic_vector((1 - 1) downto 0); dout : out std_logic_vector((1 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end expr_1e33fcde03; architecture behavior of expr_1e33fcde03 is signal a_1_24: unsigned((1 - 1) downto 0); signal b_1_27: unsigned((1 - 1) downto 0); signal bitnot_5_35: unsigned((1 - 1) downto 0); signal fulldout_5_2_bit: unsigned((1 - 1) downto 0); begin a_1_24 <= std_logic_vector_to_unsigned(a); b_1_27 <= std_logic_vector_to_unsigned(b); bitnot_5_35 <= std_logic_vector_to_unsigned(not unsigned_to_std_logic_vector(a_1_24)); fulldout_5_2_bit <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(b_1_27) and unsigned_to_std_logic_vector(bitnot_5_35)); dout <= unsigned_to_std_logic_vector(fulldout_5_2_bit); end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity inverter_e2b989a05e is port ( ip : in std_logic_vector((1 - 1) downto 0); op : out std_logic_vector((1 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end inverter_e2b989a05e; architecture behavior of inverter_e2b989a05e is signal ip_1_26: unsigned((1 - 1) downto 0); type array_type_op_mem_22_20 is array (0 to (1 - 1)) of unsigned((1 - 1) downto 0); signal op_mem_22_20: array_type_op_mem_22_20 := ( 0 => "0"); signal op_mem_22_20_front_din: unsigned((1 - 1) downto 0); signal op_mem_22_20_back: unsigned((1 - 1) downto 0); signal op_mem_22_20_push_front_pop_back_en: std_logic; signal internal_ip_12_1_bitnot: unsigned((1 - 1) downto 0); begin ip_1_26 <= std_logic_vector_to_unsigned(ip); op_mem_22_20_back <= op_mem_22_20(0); proc_op_mem_22_20: process (clk) is variable i: integer; begin if (clk'event and (clk = '1')) then if ((ce = '1') and (op_mem_22_20_push_front_pop_back_en = '1')) then op_mem_22_20(0) <= op_mem_22_20_front_din; end if; end if; end process proc_op_mem_22_20; internal_ip_12_1_bitnot <= std_logic_vector_to_unsigned(not unsigned_to_std_logic_vector(ip_1_26)); op_mem_22_20_push_front_pop_back_en <= '0'; op <= unsigned_to_std_logic_vector(internal_ip_12_1_bitnot); end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity relational_dc5bc996c9 is port ( a : in std_logic_vector((5 - 1) downto 0); b : in std_logic_vector((5 - 1) downto 0); op : out std_logic_vector((1 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end relational_dc5bc996c9; architecture behavior of relational_dc5bc996c9 is signal a_1_31: unsigned((5 - 1) downto 0); signal b_1_34: unsigned((5 - 1) downto 0); signal result_14_3_rel: boolean; begin a_1_31 <= std_logic_vector_to_unsigned(a); b_1_34 <= std_logic_vector_to_unsigned(b); result_14_3_rel <= a_1_31 /= b_1_34; op <= boolean_to_vector(result_14_3_rel); end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity addsub_ba7fff8397 is port ( a : in std_logic_vector((13 - 1) downto 0); b : in std_logic_vector((12 - 1) downto 0); s : out std_logic_vector((12 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end addsub_ba7fff8397; architecture behavior of addsub_ba7fff8397 is signal a_17_32: signed((13 - 1) downto 0); signal b_17_35: unsigned((12 - 1) downto 0); type array_type_op_mem_91_20 is array (0 to (1 - 1)) of unsigned((12 - 1) downto 0); signal op_mem_91_20: array_type_op_mem_91_20 := ( 0 => "000000000000"); signal op_mem_91_20_front_din: unsigned((12 - 1) downto 0); signal op_mem_91_20_back: unsigned((12 - 1) downto 0); signal op_mem_91_20_push_front_pop_back_en: std_logic; type array_type_cout_mem_92_22 is array (0 to (1 - 1)) of unsigned((1 - 1) downto 0); signal cout_mem_92_22: array_type_cout_mem_92_22 := ( 0 => "0"); signal cout_mem_92_22_front_din: unsigned((1 - 1) downto 0); signal cout_mem_92_22_back: unsigned((1 - 1) downto 0); signal cout_mem_92_22_push_front_pop_back_en: std_logic; signal prev_mode_93_22_next: unsigned((3 - 1) downto 0); signal prev_mode_93_22: unsigned((3 - 1) downto 0); signal prev_mode_93_22_reg_i: std_logic_vector((3 - 1) downto 0); signal prev_mode_93_22_reg_o: std_logic_vector((3 - 1) downto 0); signal cast_69_18: signed((14 - 1) downto 0); signal cast_69_22: signed((14 - 1) downto 0); signal internal_s_69_5_addsub: signed((14 - 1) downto 0); signal cast_internal_s_83_3_convert: unsigned((12 - 1) downto 0); begin a_17_32 <= std_logic_vector_to_signed(a); b_17_35 <= std_logic_vector_to_unsigned(b); op_mem_91_20_back <= op_mem_91_20(0); proc_op_mem_91_20: process (clk) is variable i: integer; begin if (clk'event and (clk = '1')) then if ((ce = '1') and (op_mem_91_20_push_front_pop_back_en = '1')) then op_mem_91_20(0) <= op_mem_91_20_front_din; end if; end if; end process proc_op_mem_91_20; cout_mem_92_22_back <= cout_mem_92_22(0); proc_cout_mem_92_22: process (clk) is variable i_x_000000: integer; begin if (clk'event and (clk = '1')) then if ((ce = '1') and (cout_mem_92_22_push_front_pop_back_en = '1')) then cout_mem_92_22(0) <= cout_mem_92_22_front_din; end if; end if; end process proc_cout_mem_92_22; prev_mode_93_22_reg_i <= unsigned_to_std_logic_vector(prev_mode_93_22_next); prev_mode_93_22 <= std_logic_vector_to_unsigned(prev_mode_93_22_reg_o); prev_mode_93_22_reg_inst: entity work.synth_reg_w_init generic map ( init_index => 2, init_value => b"010", latency => 1, width => 3) port map ( ce => ce, clk => clk, clr => clr, i => prev_mode_93_22_reg_i, o => prev_mode_93_22_reg_o); cast_69_18 <= s2s_cast(a_17_32, 0, 14, 0); cast_69_22 <= u2s_cast(b_17_35, 0, 14, 0); internal_s_69_5_addsub <= cast_69_18 + cast_69_22; cast_internal_s_83_3_convert <= s2u_cast(internal_s_69_5_addsub, 0, 12, 0); op_mem_91_20_push_front_pop_back_en <= '0'; cout_mem_92_22_push_front_pop_back_en <= '0'; prev_mode_93_22_next <= std_logic_vector_to_unsigned("000"); s <= unsigned_to_std_logic_vector(cast_internal_s_83_3_convert); end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity constant_9b805894ff is port ( op : out std_logic_vector((12 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end constant_9b805894ff; architecture behavior of constant_9b805894ff is begin op <= "111111111111"; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity constant_7c91b1b314 is port ( op : out std_logic_vector((12 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end constant_7c91b1b314; architecture behavior of constant_7c91b1b314 is begin op <= "000000000001"; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity constant_be6eece885 is port ( op : out std_logic_vector((12 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end constant_be6eece885; architecture behavior of constant_be6eece885 is begin op <= "111111111101"; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity expr_f50101e101 is port ( reset : in std_logic_vector((1 - 1) downto 0); tc : in std_logic_vector((1 - 1) downto 0); dout : out std_logic_vector((1 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end expr_f50101e101; architecture behavior of expr_f50101e101 is signal reset_1_24: boolean; signal tc_1_31: boolean; signal bit_5_25: boolean; signal fulldout_5_2_bitnot: boolean; begin reset_1_24 <= ((reset) = "1"); tc_1_31 <= ((tc) = "1"); bit_5_25 <= ((boolean_to_vector(reset_1_24) or boolean_to_vector(tc_1_31)) = "1"); fulldout_5_2_bitnot <= ((not boolean_to_vector(bit_5_25)) = "1"); dout <= boolean_to_vector(fulldout_5_2_bitnot); end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity mux_b53670f063 is port ( sel : in std_logic_vector((1 - 1) downto 0); d0 : in std_logic_vector((12 - 1) downto 0); d1 : in std_logic_vector((13 - 1) downto 0); y : out std_logic_vector((13 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end mux_b53670f063; architecture behavior of mux_b53670f063 is signal sel_1_20: std_logic; signal d0_1_24: std_logic_vector((12 - 1) downto 0); signal d1_1_27: std_logic_vector((13 - 1) downto 0); signal sel_internal_2_1_convert: std_logic_vector((1 - 1) downto 0); signal unregy_join_6_1: std_logic_vector((13 - 1) downto 0); begin sel_1_20 <= sel(0); d0_1_24 <= d0; d1_1_27 <= d1; sel_internal_2_1_convert <= cast(std_logic_to_vector(sel_1_20), 0, 1, 0, xlUnsigned); proc_switch_6_1: process (d0_1_24, d1_1_27, sel_internal_2_1_convert) is begin case sel_internal_2_1_convert is when "0" => unregy_join_6_1 <= cast(d0_1_24, 0, 13, 0, xlSigned); when others => unregy_join_6_1 <= d1_1_27; end case; end process proc_switch_6_1; y <= unregy_join_6_1; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity relational_d36fe12c1c is port ( a : in std_logic_vector((12 - 1) downto 0); b : in std_logic_vector((12 - 1) downto 0); op : out std_logic_vector((1 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end relational_d36fe12c1c; architecture behavior of relational_d36fe12c1c is signal a_1_31: unsigned((12 - 1) downto 0); signal b_1_34: unsigned((12 - 1) downto 0); signal result_12_3_rel: boolean; begin a_1_31 <= std_logic_vector_to_unsigned(a); b_1_34 <= std_logic_vector_to_unsigned(b); result_12_3_rel <= a_1_31 = b_1_34; op <= boolean_to_vector(result_12_3_rel); end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity delay_9f02caa990 is port ( d : in std_logic_vector((1 - 1) downto 0); q : out std_logic_vector((1 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end delay_9f02caa990; architecture behavior of delay_9f02caa990 is signal d_1_22: std_logic; type array_type_op_mem_20_24 is array (0 to (1 - 1)) of std_logic; signal op_mem_20_24: array_type_op_mem_20_24 := ( 0 => '0'); signal op_mem_20_24_front_din: std_logic; signal op_mem_20_24_back: std_logic; signal op_mem_20_24_push_front_pop_back_en: std_logic; begin d_1_22 <= d(0); op_mem_20_24_back <= op_mem_20_24(0); proc_op_mem_20_24: process (clk) is variable i: integer; begin if (clk'event and (clk = '1')) then if ((ce = '1') and (op_mem_20_24_push_front_pop_back_en = '1')) then op_mem_20_24(0) <= op_mem_20_24_front_din; end if; end if; end process proc_op_mem_20_24; op_mem_20_24_front_din <= d_1_22; op_mem_20_24_push_front_pop_back_en <= '1'; q <= std_logic_to_vector(op_mem_20_24_back); end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity delay_5753e4c658 is port ( d : in std_logic_vector((1 - 1) downto 0); q : out std_logic_vector((1 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end delay_5753e4c658; architecture behavior of delay_5753e4c658 is signal d_1_22: std_logic_vector((1 - 1) downto 0); type array_type_op_mem_20_24 is array (0 to (1 - 1)) of std_logic_vector((1 - 1) downto 0); signal op_mem_20_24: array_type_op_mem_20_24 := ( 0 => "0"); signal op_mem_20_24_front_din: std_logic_vector((1 - 1) downto 0); signal op_mem_20_24_back: std_logic_vector((1 - 1) downto 0); signal op_mem_20_24_push_front_pop_back_en: std_logic; begin d_1_22 <= d; op_mem_20_24_back <= op_mem_20_24(0); proc_op_mem_20_24: process (clk) is variable i: integer; begin if (clk'event and (clk = '1')) then if ((ce = '1') and (op_mem_20_24_push_front_pop_back_en = '1')) then op_mem_20_24(0) <= op_mem_20_24_front_din; end if; end if; end process proc_op_mem_20_24; op_mem_20_24_front_din <= d_1_22; op_mem_20_24_push_front_pop_back_en <= '1'; q <= op_mem_20_24_back; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity expr_305312c97b is port ( d0 : in std_logic_vector((1 - 1) downto 0); d1 : in std_logic_vector((1 - 1) downto 0); rst : in std_logic_vector((1 - 1) downto 0); dout : out std_logic_vector((1 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end expr_305312c97b; architecture behavior of expr_305312c97b is signal d0_1_24: unsigned((1 - 1) downto 0); signal d1_1_28: unsigned((1 - 1) downto 0); signal rst_1_32: unsigned((1 - 1) downto 0); signal bitnot_6_54: unsigned((1 - 1) downto 0); signal bit_6_37: unsigned((1 - 1) downto 0); signal fulldout_6_2_bit: unsigned((1 - 1) downto 0); begin d0_1_24 <= std_logic_vector_to_unsigned(d0); d1_1_28 <= std_logic_vector_to_unsigned(d1); rst_1_32 <= std_logic_vector_to_unsigned(rst); bitnot_6_54 <= std_logic_vector_to_unsigned(not unsigned_to_std_logic_vector(d0_1_24)); bit_6_37 <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(d1_1_28) and unsigned_to_std_logic_vector(bitnot_6_54)); fulldout_6_2_bit <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(rst_1_32) or unsigned_to_std_logic_vector(bit_6_37)); dout <= unsigned_to_std_logic_vector(fulldout_6_2_bit); end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity mcode_block_f4d0462e0e is port ( plbrst : in std_logic_vector((1 - 1) downto 0); plbabus : in std_logic_vector((32 - 1) downto 0); plbpavalid : in std_logic_vector((1 - 1) downto 0); plbrnw : in std_logic_vector((1 - 1) downto 0); plbwrdbus : in std_logic_vector((32 - 1) downto 0); rddata : in std_logic_vector((32 - 1) downto 0); addrpref : in std_logic_vector((20 - 1) downto 0); wrdbusreg : out std_logic_vector((32 - 1) downto 0); addrack : out std_logic_vector((1 - 1) downto 0); rdcomp : out std_logic_vector((1 - 1) downto 0); wrdack : out std_logic_vector((1 - 1) downto 0); bankaddr : out std_logic_vector((2 - 1) downto 0); rnwreg : out std_logic_vector((1 - 1) downto 0); rddack : out std_logic_vector((1 - 1) downto 0); rddbus : out std_logic_vector((32 - 1) downto 0); linearaddr : out std_logic_vector((8 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end mcode_block_f4d0462e0e; architecture behavior of mcode_block_f4d0462e0e is signal plbrst_1_110: unsigned((1 - 1) downto 0); signal plbabus_1_118: unsigned((32 - 1) downto 0); signal plbpavalid_1_127: unsigned((1 - 1) downto 0); signal plbrnw_1_139: unsigned((1 - 1) downto 0); signal plbwrdbus_1_147: unsigned((32 - 1) downto 0); signal rddata_1_158: unsigned((32 - 1) downto 0); signal addrpref_1_166: unsigned((20 - 1) downto 0); signal plbrstreg_12_24_next: boolean; signal plbrstreg_12_24: boolean := false; signal plbabusreg_13_25_next: unsigned((32 - 1) downto 0); signal plbabusreg_13_25: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000"; signal plbpavalidreg_14_28_next: boolean; signal plbpavalidreg_14_28: boolean := false; signal plbrnwreg_15_24_next: unsigned((1 - 1) downto 0); signal plbrnwreg_15_24: unsigned((1 - 1) downto 0) := "0"; signal plbwrdbusreg_16_27_next: unsigned((32 - 1) downto 0); signal plbwrdbusreg_16_27: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000"; signal avalidreg_28_23_next: boolean; signal avalidreg_28_23: boolean := false; signal ps1reg_39_20_next: boolean; signal ps1reg_39_20: boolean := false; signal psreg_47_19_next: boolean; signal psreg_47_19: boolean := false; type array_type_rdcompdelay_58_25 is array (0 to (3 - 1)) of unsigned((1 - 1) downto 0); signal rdcompdelay_58_25: array_type_rdcompdelay_58_25 := ( "0", "0", "0"); signal rdcompdelay_58_25_front_din: unsigned((1 - 1) downto 0); signal rdcompdelay_58_25_back: unsigned((1 - 1) downto 0); signal rdcompdelay_58_25_push_front_pop_back_en: std_logic; signal rdcompreg_62_23_next: unsigned((1 - 1) downto 0); signal rdcompreg_62_23: unsigned((1 - 1) downto 0) := "0"; signal rddackreg_66_23_next: unsigned((1 - 1) downto 0); signal rddackreg_66_23: unsigned((1 - 1) downto 0) := "0"; signal wrdackreg_70_23_next: unsigned((1 - 1) downto 0); signal wrdackreg_70_23: unsigned((1 - 1) downto 0) := "0"; signal rddbusreg_84_23_next: unsigned((32 - 1) downto 0); signal rddbusreg_84_23: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000"; signal bankaddr_20_1_slice: unsigned((2 - 1) downto 0); signal linearaddr_21_1_slice: unsigned((8 - 1) downto 0); signal addrpref_in_32_1_slice: unsigned((20 - 1) downto 0); signal rel_33_4: boolean; signal ps1_join_33_1: boolean; signal ps_42_1_bit: boolean; signal bitnot_49_49: boolean; signal bitnot_49_73: boolean; signal bit_49_49: boolean; signal addrack_49_1_convert: unsigned((1 - 1) downto 0); signal bit_55_43: unsigned((1 - 1) downto 0); signal bitnot_72_35: unsigned((1 - 1) downto 0); signal wrdackreg_72_1_bit: unsigned((1 - 1) downto 0); signal rdsel_76_1_bit: unsigned((1 - 1) downto 0); signal rel_78_4: boolean; signal rddbus1_join_78_1: unsigned((32 - 1) downto 0); signal plbwrdbusreg_97_1_slice: unsigned((32 - 1) downto 0); signal plbrstreg_12_24_next_x_000000: boolean; signal plbpavalidreg_14_28_next_x_000000: boolean; begin plbrst_1_110 <= std_logic_vector_to_unsigned(plbrst); plbabus_1_118 <= std_logic_vector_to_unsigned(plbabus); plbpavalid_1_127 <= std_logic_vector_to_unsigned(plbpavalid); plbrnw_1_139 <= std_logic_vector_to_unsigned(plbrnw); plbwrdbus_1_147 <= std_logic_vector_to_unsigned(plbwrdbus); rddata_1_158 <= std_logic_vector_to_unsigned(rddata); addrpref_1_166 <= std_logic_vector_to_unsigned(addrpref); proc_plbrstreg_12_24: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then plbrstreg_12_24 <= plbrstreg_12_24_next; end if; end if; end process proc_plbrstreg_12_24; proc_plbabusreg_13_25: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then plbabusreg_13_25 <= plbabusreg_13_25_next; end if; end if; end process proc_plbabusreg_13_25; proc_plbpavalidreg_14_28: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then plbpavalidreg_14_28 <= plbpavalidreg_14_28_next; end if; end if; end process proc_plbpavalidreg_14_28; proc_plbrnwreg_15_24: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then plbrnwreg_15_24 <= plbrnwreg_15_24_next; end if; end if; end process proc_plbrnwreg_15_24; proc_plbwrdbusreg_16_27: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then plbwrdbusreg_16_27 <= plbwrdbusreg_16_27_next; end if; end if; end process proc_plbwrdbusreg_16_27; proc_avalidreg_28_23: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then avalidreg_28_23 <= avalidreg_28_23_next; end if; end if; end process proc_avalidreg_28_23; proc_ps1reg_39_20: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then ps1reg_39_20 <= ps1reg_39_20_next; end if; end if; end process proc_ps1reg_39_20; proc_psreg_47_19: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then psreg_47_19 <= psreg_47_19_next; end if; end if; end process proc_psreg_47_19; rdcompdelay_58_25_back <= rdcompdelay_58_25(2); proc_rdcompdelay_58_25: process (clk) is variable i: integer; begin if (clk'event and (clk = '1')) then if ((ce = '1') and (rdcompdelay_58_25_push_front_pop_back_en = '1')) then for i in 2 downto 1 loop rdcompdelay_58_25(i) <= rdcompdelay_58_25(i-1); end loop; rdcompdelay_58_25(0) <= rdcompdelay_58_25_front_din; end if; end if; end process proc_rdcompdelay_58_25; proc_rdcompreg_62_23: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then rdcompreg_62_23 <= rdcompreg_62_23_next; end if; end if; end process proc_rdcompreg_62_23; proc_rddackreg_66_23: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then rddackreg_66_23 <= rddackreg_66_23_next; end if; end if; end process proc_rddackreg_66_23; proc_wrdackreg_70_23: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then wrdackreg_70_23 <= wrdackreg_70_23_next; end if; end if; end process proc_wrdackreg_70_23; proc_rddbusreg_84_23: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then rddbusreg_84_23 <= rddbusreg_84_23_next; end if; end if; end process proc_rddbusreg_84_23; bankaddr_20_1_slice <= u2u_slice(plbabusreg_13_25, 11, 10); linearaddr_21_1_slice <= u2u_slice(plbabusreg_13_25, 9, 2); addrpref_in_32_1_slice <= u2u_slice(plbabusreg_13_25, 31, 12); rel_33_4 <= addrpref_in_32_1_slice = addrpref_1_166; proc_if_33_1: process (rel_33_4) is begin if rel_33_4 then ps1_join_33_1 <= true; else ps1_join_33_1 <= false; end if; end process proc_if_33_1; ps_42_1_bit <= ((boolean_to_vector(ps1_join_33_1) and boolean_to_vector(plbpavalidreg_14_28)) = "1"); bitnot_49_49 <= ((not boolean_to_vector(plbrstreg_12_24)) = "1"); bitnot_49_73 <= ((not boolean_to_vector(psreg_47_19)) = "1"); bit_49_49 <= ((boolean_to_vector(bitnot_49_49) and boolean_to_vector(ps_42_1_bit) and boolean_to_vector(bitnot_49_73)) = "1"); addrack_49_1_convert <= u2u_cast(std_logic_vector_to_unsigned(boolean_to_vector(bit_49_49)), 0, 1, 0); bit_55_43 <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(addrack_49_1_convert) and unsigned_to_std_logic_vector(plbrnwreg_15_24)); bitnot_72_35 <= std_logic_vector_to_unsigned(not unsigned_to_std_logic_vector(plbrnwreg_15_24)); wrdackreg_72_1_bit <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(addrack_49_1_convert) and unsigned_to_std_logic_vector(bitnot_72_35)); rdsel_76_1_bit <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(rdcompdelay_58_25_back) or unsigned_to_std_logic_vector(rdcompreg_62_23)); rel_78_4 <= rdsel_76_1_bit = std_logic_vector_to_unsigned("1"); proc_if_78_1: process (rddata_1_158, rel_78_4) is begin if rel_78_4 then rddbus1_join_78_1 <= rddata_1_158; else rddbus1_join_78_1 <= std_logic_vector_to_unsigned("00000000000000000000000000000000"); end if; end process proc_if_78_1; plbwrdbusreg_97_1_slice <= u2u_slice(plbwrdbus_1_147, 31, 0); plbrstreg_12_24_next_x_000000 <= (plbrst_1_110 /= "0"); plbrstreg_12_24_next <= plbrstreg_12_24_next_x_000000; plbabusreg_13_25_next <= plbabus_1_118; plbpavalidreg_14_28_next_x_000000 <= (plbpavalid_1_127 /= "0"); plbpavalidreg_14_28_next <= plbpavalidreg_14_28_next_x_000000; plbrnwreg_15_24_next <= plbrnw_1_139; plbwrdbusreg_16_27_next <= plbwrdbusreg_97_1_slice; avalidreg_28_23_next <= plbpavalidreg_14_28; ps1reg_39_20_next <= ps1_join_33_1; psreg_47_19_next <= ps_42_1_bit; rdcompdelay_58_25_front_din <= bit_55_43; rdcompdelay_58_25_push_front_pop_back_en <= '1'; rdcompreg_62_23_next <= rdcompdelay_58_25_back; rddackreg_66_23_next <= rdcompreg_62_23; wrdackreg_70_23_next <= wrdackreg_72_1_bit; rddbusreg_84_23_next <= rddbus1_join_78_1; wrdbusreg <= unsigned_to_std_logic_vector(plbwrdbusreg_16_27); addrack <= unsigned_to_std_logic_vector(addrack_49_1_convert); rdcomp <= unsigned_to_std_logic_vector(rdcompreg_62_23); wrdack <= unsigned_to_std_logic_vector(wrdackreg_70_23); bankaddr <= unsigned_to_std_logic_vector(bankaddr_20_1_slice); rnwreg <= unsigned_to_std_logic_vector(plbrnwreg_15_24); rddack <= unsigned_to_std_logic_vector(rddackreg_66_23); rddbus <= unsigned_to_std_logic_vector(rddbusreg_84_23); linearaddr <= unsigned_to_std_logic_vector(linearaddr_21_1_slice); end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity mcode_block_6fff803424 is port ( wrdbus : in std_logic_vector((32 - 1) downto 0); bankaddr : in std_logic_vector((2 - 1) downto 0); linearaddr : in std_logic_vector((8 - 1) downto 0); rnwreg : in std_logic_vector((1 - 1) downto 0); addrack : in std_logic_vector((1 - 1) downto 0); sm_coef_update : in std_logic_vector((1 - 1) downto 0); sm_coef_gain : in std_logic_vector((20 - 1) downto 0); sm_coef_buffer : in std_logic_vector((7 - 1) downto 0); read_bank_out : out std_logic_vector((32 - 1) downto 0); sm_coef_update_din : out std_logic_vector((1 - 1) downto 0); sm_coef_update_en : out std_logic_vector((1 - 1) downto 0); sm_coef_gain_din : out std_logic_vector((20 - 1) downto 0); sm_coef_gain_en : out std_logic_vector((1 - 1) downto 0); sm_coef_buffer_addr : out std_logic_vector((5 - 1) downto 0); sm_coef_buffer_din : out std_logic_vector((7 - 1) downto 0); sm_coef_buffer_we : out std_logic_vector((1 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end mcode_block_6fff803424; architecture behavior of mcode_block_6fff803424 is signal wrdbus_1_173: unsigned((32 - 1) downto 0); signal bankaddr_1_181: unsigned((2 - 1) downto 0); signal linearaddr_1_191: unsigned((8 - 1) downto 0); signal rnwreg_1_203: unsigned((1 - 1) downto 0); signal addrack_1_211: unsigned((1 - 1) downto 0); signal sm_coef_update_1_220: unsigned((1 - 1) downto 0); signal sm_coef_gain_1_236: unsigned((20 - 1) downto 0); signal sm_coef_buffer_1_250: signed((7 - 1) downto 0); signal reg_bank_out_reg_25_30_next: unsigned((32 - 1) downto 0); signal reg_bank_out_reg_25_30: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000"; signal ram_bank_out_reg_49_30_next: unsigned((32 - 1) downto 0); signal ram_bank_out_reg_49_30: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000"; signal sm_coef_buffer_we_reg_62_35_next: boolean; signal sm_coef_buffer_we_reg_62_35: boolean := false; signal sm_coef_buffer_addr_reg_74_1_next: unsigned((5 - 1) downto 0); signal sm_coef_buffer_addr_reg_74_1: unsigned((5 - 1) downto 0) := "00000"; signal read_bank_out_reg_112_31_next: unsigned((32 - 1) downto 0); signal read_bank_out_reg_112_31: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000"; signal bankaddr_reg_115_26_next: unsigned((2 - 1) downto 0); signal bankaddr_reg_115_26: unsigned((2 - 1) downto 0) := "00"; signal sm_coef_buffer_bus_19_1_force: unsigned((7 - 1) downto 0); signal rel_28_4: boolean; signal rel_30_8: boolean; signal reg_bank_out_reg_join_28_1: unsigned((32 - 1) downto 0); signal opcode_42_1_concat: unsigned((12 - 1) downto 0); signal slice_56_39: unsigned((7 - 1) downto 0); signal sm_coef_buffer_din_56_1_force: signed((7 - 1) downto 0); signal opcode_sm_coef_buffer_64_1_concat: unsigned((4 - 1) downto 0); signal rel_65_4: boolean; signal sm_coef_buffer_we_reg_join_65_1: boolean; signal rel_83_4: boolean; signal sm_coef_update_en_join_83_1: boolean; signal rel_89_4: boolean; signal sm_coef_gain_en_join_89_1: boolean; signal slice_104_39: unsigned((1 - 1) downto 0); signal slice_107_37: unsigned((20 - 1) downto 0); signal rel_117_4: boolean; signal rel_120_8: boolean; signal rel_123_8: boolean; signal rel_126_8: boolean; signal read_bank_out_reg_join_117_1: unsigned((32 - 1) downto 0); signal cast_ram_bank_out_reg_49_30_next: unsigned((32 - 1) downto 0); signal cast_sm_coef_buffer_addr_reg_74_1_next: unsigned((5 - 1) downto 0); begin wrdbus_1_173 <= std_logic_vector_to_unsigned(wrdbus); bankaddr_1_181 <= std_logic_vector_to_unsigned(bankaddr); linearaddr_1_191 <= std_logic_vector_to_unsigned(linearaddr); rnwreg_1_203 <= std_logic_vector_to_unsigned(rnwreg); addrack_1_211 <= std_logic_vector_to_unsigned(addrack); sm_coef_update_1_220 <= std_logic_vector_to_unsigned(sm_coef_update); sm_coef_gain_1_236 <= std_logic_vector_to_unsigned(sm_coef_gain); sm_coef_buffer_1_250 <= std_logic_vector_to_signed(sm_coef_buffer); proc_reg_bank_out_reg_25_30: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then reg_bank_out_reg_25_30 <= reg_bank_out_reg_25_30_next; end if; end if; end process proc_reg_bank_out_reg_25_30; proc_ram_bank_out_reg_49_30: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then ram_bank_out_reg_49_30 <= ram_bank_out_reg_49_30_next; end if; end if; end process proc_ram_bank_out_reg_49_30; proc_sm_coef_buffer_we_reg_62_35: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then sm_coef_buffer_we_reg_62_35 <= sm_coef_buffer_we_reg_62_35_next; end if; end if; end process proc_sm_coef_buffer_we_reg_62_35; proc_sm_coef_buffer_addr_reg_74_1: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then sm_coef_buffer_addr_reg_74_1 <= sm_coef_buffer_addr_reg_74_1_next; end if; end if; end process proc_sm_coef_buffer_addr_reg_74_1; proc_read_bank_out_reg_112_31: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then read_bank_out_reg_112_31 <= read_bank_out_reg_112_31_next; end if; end if; end process proc_read_bank_out_reg_112_31; proc_bankaddr_reg_115_26: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then bankaddr_reg_115_26 <= bankaddr_reg_115_26_next; end if; end if; end process proc_bankaddr_reg_115_26; sm_coef_buffer_bus_19_1_force <= signed_to_unsigned(sm_coef_buffer_1_250); rel_28_4 <= linearaddr_1_191 = std_logic_vector_to_unsigned("00000000"); rel_30_8 <= linearaddr_1_191 = std_logic_vector_to_unsigned("00000001"); proc_if_28_1: process (reg_bank_out_reg_25_30, rel_28_4, rel_30_8, sm_coef_gain_1_236, sm_coef_update_1_220) is begin if rel_28_4 then reg_bank_out_reg_join_28_1 <= u2u_cast(sm_coef_update_1_220, 0, 32, 0); elsif rel_30_8 then reg_bank_out_reg_join_28_1 <= u2u_cast(sm_coef_gain_1_236, 0, 32, 0); else reg_bank_out_reg_join_28_1 <= reg_bank_out_reg_25_30; end if; end process proc_if_28_1; opcode_42_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(addrack_1_211) & unsigned_to_std_logic_vector(rnwreg_1_203) & unsigned_to_std_logic_vector(bankaddr_1_181) & unsigned_to_std_logic_vector(linearaddr_1_191)); slice_56_39 <= u2u_slice(wrdbus_1_173, 6, 0); sm_coef_buffer_din_56_1_force <= unsigned_to_signed(slice_56_39); opcode_sm_coef_buffer_64_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(addrack_1_211) & unsigned_to_std_logic_vector(rnwreg_1_203) & unsigned_to_std_logic_vector(bankaddr_1_181)); rel_65_4 <= opcode_sm_coef_buffer_64_1_concat = std_logic_vector_to_unsigned("1000"); proc_if_65_1: process (rel_65_4) is begin if rel_65_4 then sm_coef_buffer_we_reg_join_65_1 <= true; else sm_coef_buffer_we_reg_join_65_1 <= false; end if; end process proc_if_65_1; rel_83_4 <= opcode_42_1_concat = std_logic_vector_to_unsigned("101000000000"); proc_if_83_1: process (rel_83_4) is begin if rel_83_4 then sm_coef_update_en_join_83_1 <= true; else sm_coef_update_en_join_83_1 <= false; end if; end process proc_if_83_1; rel_89_4 <= opcode_42_1_concat = std_logic_vector_to_unsigned("101000000001"); proc_if_89_1: process (rel_89_4) is begin if rel_89_4 then sm_coef_gain_en_join_89_1 <= true; else sm_coef_gain_en_join_89_1 <= false; end if; end process proc_if_89_1; slice_104_39 <= u2u_slice(wrdbus_1_173, 0, 0); slice_107_37 <= u2u_slice(wrdbus_1_173, 19, 0); rel_117_4 <= bankaddr_reg_115_26 = std_logic_vector_to_unsigned("00"); rel_120_8 <= bankaddr_reg_115_26 = std_logic_vector_to_unsigned("01"); rel_123_8 <= bankaddr_reg_115_26 = std_logic_vector_to_unsigned("10"); rel_126_8 <= bankaddr_reg_115_26 = std_logic_vector_to_unsigned("11"); proc_if_117_1: process (ram_bank_out_reg_49_30, read_bank_out_reg_112_31, reg_bank_out_reg_25_30, rel_117_4, rel_120_8, rel_123_8, rel_126_8) is begin if rel_117_4 then read_bank_out_reg_join_117_1 <= ram_bank_out_reg_49_30; elsif rel_120_8 then read_bank_out_reg_join_117_1 <= std_logic_vector_to_unsigned("00000000000000000000000000000000"); elsif rel_123_8 then read_bank_out_reg_join_117_1 <= reg_bank_out_reg_25_30; elsif rel_126_8 then read_bank_out_reg_join_117_1 <= std_logic_vector_to_unsigned("00000000000000000000000000000000"); else read_bank_out_reg_join_117_1 <= read_bank_out_reg_112_31; end if; end process proc_if_117_1; reg_bank_out_reg_25_30_next <= reg_bank_out_reg_join_28_1; cast_ram_bank_out_reg_49_30_next <= u2u_cast(sm_coef_buffer_bus_19_1_force, 0, 32, 0); ram_bank_out_reg_49_30_next <= cast_ram_bank_out_reg_49_30_next; sm_coef_buffer_we_reg_62_35_next <= sm_coef_buffer_we_reg_join_65_1; cast_sm_coef_buffer_addr_reg_74_1_next <= u2u_cast(linearaddr_1_191, 0, 5, 0); sm_coef_buffer_addr_reg_74_1_next <= cast_sm_coef_buffer_addr_reg_74_1_next; read_bank_out_reg_112_31_next <= read_bank_out_reg_join_117_1; bankaddr_reg_115_26_next <= bankaddr_1_181; read_bank_out <= unsigned_to_std_logic_vector(read_bank_out_reg_112_31); sm_coef_update_din <= unsigned_to_std_logic_vector(slice_104_39); sm_coef_update_en <= boolean_to_vector(sm_coef_update_en_join_83_1); sm_coef_gain_din <= unsigned_to_std_logic_vector(slice_107_37); sm_coef_gain_en <= boolean_to_vector(sm_coef_gain_en_join_89_1); sm_coef_buffer_addr <= unsigned_to_std_logic_vector(sm_coef_buffer_addr_reg_74_1); sm_coef_buffer_din <= signed_to_std_logic_vector(sm_coef_buffer_din_56_1_force); sm_coef_buffer_we <= boolean_to_vector(sm_coef_buffer_we_reg_62_35); end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity concat_d0d1b9533e is port ( in0 : in std_logic_vector((8 - 1) downto 0); in1 : in std_logic_vector((8 - 1) downto 0); in2 : in std_logic_vector((8 - 1) downto 0); y : out std_logic_vector((24 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end concat_d0d1b9533e; architecture behavior of concat_d0d1b9533e is signal in0_1_23: unsigned((8 - 1) downto 0); signal in1_1_27: unsigned((8 - 1) downto 0); signal in2_1_31: unsigned((8 - 1) downto 0); signal y_2_1_concat: unsigned((24 - 1) downto 0); begin in0_1_23 <= std_logic_vector_to_unsigned(in0); in1_1_27 <= std_logic_vector_to_unsigned(in1); in2_1_31 <= std_logic_vector_to_unsigned(in2); y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27) & unsigned_to_std_logic_vector(in2_1_31)); y <= unsigned_to_std_logic_vector(y_2_1_concat); end behavior; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; -- Generated from Simulink block "sg_2d_fir/5x5_Filters/Blue_Filter/5x5_Filter/2D_FIR/ABS" entity abs_entity_13c6ead9ca is port ( ce_1: in std_logic; clk_1: in std_logic; in1: in std_logic_vector(21 downto 0); out1: out std_logic_vector(22 downto 0) ); end abs_entity_13c6ead9ca; architecture structural of abs_entity_13c6ead9ca is signal addsub15_s_net_x0: std_logic_vector(21 downto 0); signal ce_1_sg_x0: std_logic; signal clk_1_sg_x0: std_logic; signal mux_y_net_x0: std_logic_vector(22 downto 0); signal negate_op_net: std_logic_vector(22 downto 0); signal register1_q_net: std_logic_vector(21 downto 0); signal register2_q_net: std_logic; signal slice_y_net: std_logic; begin ce_1_sg_x0 <= ce_1; clk_1_sg_x0 <= clk_1; addsub15_s_net_x0 <= in1; out1 <= mux_y_net_x0; mux: entity work.mux_029cd20aa9 port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, clr => '0', d0 => register1_q_net, d1 => negate_op_net, sel(0) => register2_q_net, y => mux_y_net_x0 ); negate: entity work.negate_142bd36a06 port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, clr => '0', ip => addsub15_s_net_x0, op => negate_op_net ); register1: entity work.xlregister generic map ( d_width => 22, init_value => b"0000000000000000000000" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d => addsub15_s_net_x0, en => "1", rst => "0", q => register1_q_net ); register2: entity work.xlregister generic map ( d_width => 1, init_value => b"0" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d(0) => slice_y_net, en => "1", rst => "0", q(0) => register2_q_net ); slice: entity work.xlslice generic map ( new_lsb => 21, new_msb => 21, x_width => 22, y_width => 1 ) port map ( x => addsub15_s_net_x0, y(0) => slice_y_net ); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; -- Generated from Simulink block "sg_2d_fir/5x5_Filters/Blue_Filter/5x5_Filter/2D_FIR/n-tap FIR Compiler Filter1/Rising Edge Detector1" entity rising_edge_detector1_entity_8b96cf7ac4 is port ( ce_1: in std_logic; clk_1: in std_logic; din: in std_logic; dout: out std_logic ); end rising_edge_detector1_entity_8b96cf7ac4; architecture structural of rising_edge_detector1_entity_8b96cf7ac4 is signal ce_1_sg_x1: std_logic; signal clk_1_sg_x1: std_logic; signal inverter_op_net: std_logic; signal logical_y_net_x1: std_logic; signal logical_y_net_x2: std_logic; signal register1_q_net: std_logic; begin ce_1_sg_x1 <= ce_1; clk_1_sg_x1 <= clk_1; logical_y_net_x1 <= din; dout <= logical_y_net_x2; inverter: entity work.inverter_e5b38cca3b port map ( ce => ce_1_sg_x1, clk => clk_1_sg_x1, clr => '0', ip(0) => register1_q_net, op(0) => inverter_op_net ); logical: entity work.logical_80f90b97d0 port map ( ce => '0', clk => '0', clr => '0', d0(0) => logical_y_net_x1, d1(0) => inverter_op_net, y(0) => logical_y_net_x2 ); register1: entity work.xlregister generic map ( d_width => 1, init_value => b"0" ) port map ( ce => ce_1_sg_x1, clk => clk_1_sg_x1, d(0) => logical_y_net_x1, en => "1", rst => "0", q(0) => register1_q_net ); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; -- Generated from Simulink block "sg_2d_fir/5x5_Filters/Blue_Filter/5x5_Filter/2D_FIR/n-tap FIR Compiler Filter1" --entity n_tap_fir_compiler_filter1_entity_2d915a7ccf is -- port ( -- ce_1: in std_logic; -- ce_logic_1: in std_logic; -- clk_1: in std_logic; -- coef: in std_logic_vector(6 downto 0); -- din: in std_logic_vector(7 downto 0); -- load: in std_logic; -- out_x0: out std_logic_vector(18 downto 0) -- ); --end n_tap_fir_compiler_filter1_entity_2d915a7ccf; --architecture structural of n_tap_fir_compiler_filter1_entity_2d915a7ccf is -- signal ce_1_sg_x2: std_logic; -- signal ce_logic_1_sg_x0: std_logic; -- signal clk_1_sg_x2: std_logic; -- signal fir_compiler_5_0_dout_net: std_logic_vector(18 downto 0); -- signal fir_compiler_5_0_rdy_net: std_logic; -- signal l1_x0: std_logic_vector(7 downto 0); -- signal logical_y_net_x2: std_logic; -- signal logical_y_net_x3: std_logic; -- signal register2_q_net: std_logic; -- signal register_q_net_x0: std_logic_vector(18 downto 0); -- signal shared_memory_data_out_net_x0: std_logic_vector(6 downto 0); --begin -- ce_1_sg_x2 <= ce_1; -- ce_logic_1_sg_x0 <= ce_logic_1; -- clk_1_sg_x2 <= clk_1; -- shared_memory_data_out_net_x0 <= coef; -- l1_x0 <= din; -- logical_y_net_x3 <= load; -- out_x0 <= register_q_net_x0; -- fir_compiler_5_0: entity work.xlfir_compiler_acc9ad12ef8a3d59fab07d7a4ad1b777 -- port map ( -- ce => ce_1_sg_x2, -- ce_logic_1 => ce_logic_1_sg_x0, -- clk => clk_1_sg_x2, -- clk_logic_1 => clk_1_sg_x2, -- coef_din => shared_memory_data_out_net_x0, -- coef_ld => logical_y_net_x2, -- coef_we => register2_q_net, -- din => l1_x0, -- src_ce => ce_1_sg_x2, -- src_clk => clk_1_sg_x2, -- dout => fir_compiler_5_0_dout_net, -- rdy => fir_compiler_5_0_rdy_net -- ); -- register2: entity work.xlregister -- generic map ( -- d_width => 1, -- init_value => b"0" -- ) -- port map ( -- ce => ce_1_sg_x2, -- clk => clk_1_sg_x2, -- d(0) => logical_y_net_x3, -- en => "1", -- rst => "0", -- q(0) => register2_q_net -- ); -- register_x0: entity work.xlregister -- generic map ( -- d_width => 19, -- init_value => b"0000000000000000000" -- ) -- port map ( -- ce => ce_1_sg_x2, -- clk => clk_1_sg_x2, -- d => fir_compiler_5_0_dout_net, -- en(0) => fir_compiler_5_0_rdy_net, -- rst => "0", -- q => register_q_net_x0 -- ); -- rising_edge_detector1_8b96cf7ac4: entity work.rising_edge_detector1_entity_8b96cf7ac4 -- port map ( -- ce_1 => ce_1_sg_x2, -- clk_1 => clk_1_sg_x2, -- din => logical_y_net_x3, -- dout => logical_y_net_x2 -- ); --end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; -- Generated from Simulink block "sg_2d_fir/5x5_Filters/Blue_Filter/5x5_Filter/2D_FIR" entity x2d_fir_entity_587bafe04d is port ( ce_1: in std_logic; ce_logic_1: in std_logic; clk_1: in std_logic; coef: in std_logic_vector(6 downto 0); gain: in std_logic_vector(19 downto 0); line1: in std_logic_vector(7 downto 0); line2: in std_logic_vector(7 downto 0); line3: in std_logic_vector(7 downto 0); line4: in std_logic_vector(7 downto 0); line5: in std_logic_vector(7 downto 0); load_1: in std_logic; load_2: in std_logic; load_3: in std_logic; load_4: in std_logic; load_5: in std_logic; dout: out std_logic_vector(7 downto 0) ); end x2d_fir_entity_587bafe04d; architecture structural of x2d_fir_entity_587bafe04d is signal addsub15_s_net_x0: std_logic_vector(21 downto 0); signal addsub2_s_net: std_logic_vector(19 downto 0); signal addsub3_s_net: std_logic_vector(19 downto 0); signal addsub4_s_net: std_logic_vector(20 downto 0); signal assert_dout_net: std_logic_vector(19 downto 0); signal ce_1_sg_x11: std_logic; signal ce_logic_1_sg_x5: std_logic; signal clk_1_sg_x11: std_logic; signal coef_gain_q_net: std_logic_vector(19 downto 0); signal convert1_dout_net_x0: std_logic_vector(7 downto 0); signal from_register_data_out_net_x0: std_logic_vector(19 downto 0); signal l1_x1: std_logic_vector(7 downto 0); signal l2_x1: std_logic_vector(7 downto 0); signal l3_x1: std_logic_vector(7 downto 0); signal l4_x1: std_logic_vector(7 downto 0); signal l5_x1: std_logic_vector(7 downto 0); signal logical1_y_net_x2: std_logic; signal logical2_y_net_x2: std_logic; signal logical3_y_net_x2: std_logic; signal logical4_y_net_x2: std_logic; signal logical_y_net_x4: std_logic; signal mult_p_net: std_logic_vector(42 downto 0); signal mux_y_net_x0: std_logic_vector(22 downto 0); signal register1_q_net: std_logic_vector(18 downto 0); signal register2_q_net: std_logic_vector(18 downto 0); signal register_q_net_x0: std_logic_vector(18 downto 0); signal register_q_net_x1: std_logic_vector(18 downto 0); signal register_q_net_x2: std_logic_vector(18 downto 0); signal register_q_net_x3: std_logic_vector(18 downto 0); signal register_q_net_x4: std_logic_vector(18 downto 0); signal shared_memory_data_out_net_x5: std_logic_vector(6 downto 0); begin ce_1_sg_x11 <= ce_1; ce_logic_1_sg_x5 <= ce_logic_1; clk_1_sg_x11 <= clk_1; shared_memory_data_out_net_x5 <= coef; from_register_data_out_net_x0 <= gain; l1_x1 <= line1; l2_x1 <= line2; l3_x1 <= line3; l4_x1 <= line4; l5_x1 <= line5; logical_y_net_x4 <= load_1; logical1_y_net_x2 <= load_2; logical2_y_net_x2 <= load_3; logical3_y_net_x2 <= load_4; logical4_y_net_x2 <= load_5; dout <= convert1_dout_net_x0; abs_13c6ead9ca: entity work.abs_entity_13c6ead9ca port map ( ce_1 => ce_1_sg_x11, clk_1 => clk_1_sg_x11, in1 => addsub15_s_net_x0, out1 => mux_y_net_x0 ); addsub15: entity work.xladdsub generic map ( a_arith => xlSigned, a_bin_pt => 0, a_width => 21, b_arith => xlSigned, b_bin_pt => 0, b_width => 19, c_has_c_out => 0, c_latency => 1, c_output_width => 22, core_name0 => "addsb_11_0_e7b4231f2ca96446", extra_registers => 0, full_s_arith => 2, full_s_width => 22, latency => 1, overflow => 1, quantization => 1, s_arith => xlSigned, s_bin_pt => 0, s_width => 22 ) port map ( a => addsub4_s_net, b => register2_q_net, ce => ce_1_sg_x11, clk => clk_1_sg_x11, clr => '0', en => "1", s => addsub15_s_net_x0 ); addsub2: entity work.xladdsub generic map ( a_arith => xlSigned, a_bin_pt => 0, a_width => 19, b_arith => xlSigned, b_bin_pt => 0, b_width => 19, c_has_c_out => 0, c_latency => 1, c_output_width => 20, core_name0 => "addsb_11_0_da33f2d4b3b54185", extra_registers => 0, full_s_arith => 2, full_s_width => 20, latency => 1, overflow => 1, quantization => 1, s_arith => xlSigned, s_bin_pt => 0, s_width => 20 ) port map ( a => register_q_net_x0, b => register_q_net_x1, ce => ce_1_sg_x11, clk => clk_1_sg_x11, clr => '0', en => "1", s => addsub2_s_net ); addsub3: entity work.xladdsub generic map ( a_arith => xlSigned, a_bin_pt => 0, a_width => 19, b_arith => xlSigned, b_bin_pt => 0, b_width => 19, c_has_c_out => 0, c_latency => 1, c_output_width => 20, core_name0 => "addsb_11_0_da33f2d4b3b54185", extra_registers => 0, full_s_arith => 2, full_s_width => 20, latency => 1, overflow => 1, quantization => 1, s_arith => xlSigned, s_bin_pt => 0, s_width => 20 ) port map ( a => register_q_net_x2, b => register_q_net_x3, ce => ce_1_sg_x11, clk => clk_1_sg_x11, clr => '0', en => "1", s => addsub3_s_net ); addsub4: entity work.xladdsub generic map ( a_arith => xlSigned, a_bin_pt => 0, a_width => 20, b_arith => xlSigned, b_bin_pt => 0, b_width => 20, c_has_c_out => 0, c_latency => 1, c_output_width => 21, core_name0 => "addsb_11_0_48bcbc42a6774592", extra_registers => 0, full_s_arith => 2, full_s_width => 21, latency => 1, overflow => 1, quantization => 1, s_arith => xlSigned, s_bin_pt => 0, s_width => 21 ) port map ( a => addsub2_s_net, b => addsub3_s_net, ce => ce_1_sg_x11, clk => clk_1_sg_x11, clr => '0', en => "1", s => addsub4_s_net ); assert_x0: entity work.xlpassthrough generic map ( din_width => 20, dout_width => 20 ) port map ( din => from_register_data_out_net_x0, dout => assert_dout_net ); coef_gain: entity work.xlregister generic map ( d_width => 20, init_value => b"00000000000000000000" ) port map ( ce => ce_1_sg_x11, clk => clk_1_sg_x11, d => assert_dout_net, en(0) => logical4_y_net_x2, rst => "0", q => coef_gain_q_net ); convert1: entity work.xlconvert generic map ( bool_conversion => 0, din_arith => 2, din_bin_pt => 17, din_width => 43, dout_arith => 1, dout_bin_pt => 0, dout_width => 8, latency => 1, overflow => xlSaturate, quantization => xlTruncate ) port map ( ce => ce_1_sg_x11, clk => clk_1_sg_x11, clr => '0', din => mult_p_net, en => "1", dout => convert1_dout_net_x0 ); mult: entity work.xlmult generic map ( a_arith => xlSigned, a_bin_pt => 0, a_width => 23, b_arith => xlUnsigned, b_bin_pt => 17, b_width => 20, c_a_type => 0, c_a_width => 23, c_b_type => 1, c_b_width => 20, c_baat => 23, c_output_width => 43, c_type => 0, core_name0 => "mult_11_2_fe92ad55b7635191", extra_registers => 0, multsign => 2, overflow => 1, p_arith => xlSigned, p_bin_pt => 17, p_width => 43, quantization => 1 ) port map ( a => mux_y_net_x0, b => coef_gain_q_net, ce => ce_1_sg_x11, clk => clk_1_sg_x11, clr => '0', core_ce => ce_1_sg_x11, core_clk => clk_1_sg_x11, core_clr => '1', en => "1", rst => "0", p => mult_p_net ); n_tap_fir_compiler_filter1_2d915a7ccf: entity work.fir_1d_trn_load generic map( IN_DW => 8, OUT_DW => 19, COEF_DW => 7, TAPS => 5, DELAY => 8 ) port map ( ce_1 => ce_1_sg_x11, clk_1 => clk_1_sg_x11, coef => shared_memory_data_out_net_x5, din => l1_x1, load => logical_y_net_x4, out_data => register_q_net_x0 ); n_tap_fir_compiler_filter2_89a7e4bb68: entity work.fir_1d_trn_load generic map( IN_DW => 8, OUT_DW => 19, COEF_DW => 7, TAPS => 5, DELAY => 8 ) port map ( ce_1 => ce_1_sg_x11, clk_1 => clk_1_sg_x11, coef => shared_memory_data_out_net_x5, din => l2_x1, load => logical1_y_net_x2, out_data => register_q_net_x1 ); n_tap_fir_compiler_filter3_2a2055e6f6: entity work.fir_1d_trn_load generic map( IN_DW => 8, OUT_DW => 19, COEF_DW => 7, TAPS => 5, DELAY => 8 ) port map ( ce_1 => ce_1_sg_x11, clk_1 => clk_1_sg_x11, coef => shared_memory_data_out_net_x5, din => l3_x1, load => logical2_y_net_x2, out_data => register_q_net_x2 ); n_tap_fir_compiler_filter4_777d8a504f: entity work.fir_1d_trn_load generic map( IN_DW => 8, OUT_DW => 19, COEF_DW => 7, TAPS => 5, DELAY => 8 ) port map ( ce_1 => ce_1_sg_x11, clk_1 => clk_1_sg_x11, coef => shared_memory_data_out_net_x5, din => l4_x1, load => logical3_y_net_x2, out_data => register_q_net_x3 ); n_tap_fir_compiler_filter5_552fc58734: entity work.fir_1d_trn_load generic map( IN_DW => 8, OUT_DW => 19, COEF_DW => 7, TAPS => 5, DELAY => 8 ) port map ( ce_1 => ce_1_sg_x11, clk_1 => clk_1_sg_x11, coef => shared_memory_data_out_net_x5, din => l5_x1, load => logical4_y_net_x2, out_data => register_q_net_x4 ); register1: entity work.xlregister generic map ( d_width => 19, init_value => b"0000000000000000000" ) port map ( ce => ce_1_sg_x11, clk => clk_1_sg_x11, d => register_q_net_x4, en => "1", rst => "0", q => register1_q_net ); register2: entity work.xlregister generic map ( d_width => 19, init_value => b"0000000000000000000" ) port map ( ce => ce_1_sg_x11, clk => clk_1_sg_x11, d => register1_q_net, en => "1", rst => "0", q => register2_q_net ); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; -- Generated from Simulink block "sg_2d_fir/5x5_Filters/Blue_Filter/5x5_Filter/load_sequencer" entity load_sequencer_entity_8724dffd75 is port ( ce_1: in std_logic; clk_1: in std_logic; load: in std_logic; load_1: out std_logic; load_2: out std_logic; load_3: out std_logic; load_4: out std_logic; load_5: out std_logic ); end load_sequencer_entity_8724dffd75; architecture structural of load_sequencer_entity_8724dffd75 is signal ce_1_sg_x12: std_logic; signal clk_1_sg_x12: std_logic; signal constant1_op_net: std_logic_vector(2 downto 0); signal constant2_op_net: std_logic_vector(2 downto 0); signal constant3_op_net: std_logic_vector(2 downto 0); signal constant4_op_net: std_logic_vector(2 downto 0); signal constant5_op_net: std_logic_vector(2 downto 0); signal constant7_op_net: std_logic_vector(2 downto 0); signal counter_op_net: std_logic_vector(2 downto 0); signal index_count_op_net: std_logic_vector(2 downto 0); signal logical1_y_net_x3: std_logic; signal logical2_y_net_x3: std_logic; signal logical3_y_net_x3: std_logic; signal logical4_y_net_x3: std_logic; signal logical5_y_net: std_logic; signal logical_y_net_x5: std_logic; signal relational1_op_net: std_logic; signal relational2_op_net: std_logic; signal relational3_op_net: std_logic; signal relational3_op_net_x1: std_logic; signal relational4_op_net: std_logic; signal relational5_op_net: std_logic; signal relational6_op_net: std_logic; signal relational_op_net: std_logic; begin ce_1_sg_x12 <= ce_1; clk_1_sg_x12 <= clk_1; relational3_op_net_x1 <= load; load_1 <= logical_y_net_x5; load_2 <= logical1_y_net_x3; load_3 <= logical2_y_net_x3; load_4 <= logical3_y_net_x3; load_5 <= logical4_y_net_x3; constant1: entity work.constant_822933f89b port map ( ce => '0', clk => '0', clr => '0', op => constant1_op_net ); constant2: entity work.constant_a1c496ea88 port map ( ce => '0', clk => '0', clr => '0', op => constant2_op_net ); constant3: entity work.constant_1f5cc32f1e port map ( ce => '0', clk => '0', clr => '0', op => constant3_op_net ); constant4: entity work.constant_0f59f02ba5 port map ( ce => '0', clk => '0', clr => '0', op => constant4_op_net ); constant5: entity work.constant_469094441c port map ( ce => '0', clk => '0', clr => '0', op => constant5_op_net ); constant7: entity work.constant_469094441c port map ( ce => '0', clk => '0', clr => '0', op => constant7_op_net ); counter: entity work.xlcounter_limit generic map ( cnt_15_0 => 4, cnt_31_16 => 0, cnt_47_32 => 0, cnt_63_48 => 0, core_name0 => "cntr_11_0_e859c6662c373192", count_limited => 1, op_arith => xlUnsigned, op_width => 3 ) port map ( ce => ce_1_sg_x12, clk => clk_1_sg_x12, clr => '0', en(0) => relational3_op_net_x1, rst(0) => relational6_op_net, op => counter_op_net ); index_count: entity work.xlcounter_limit generic map ( cnt_15_0 => 4, cnt_31_16 => 0, cnt_47_32 => 0, cnt_63_48 => 0, core_name0 => "cntr_11_0_e859c6662c373192", count_limited => 1, op_arith => xlUnsigned, op_width => 3 ) port map ( ce => ce_1_sg_x12, clk => clk_1_sg_x12, clr => '0', en(0) => relational6_op_net, rst(0) => logical5_y_net, op => index_count_op_net ); logical: entity work.logical_80f90b97d0 port map ( ce => '0', clk => '0', clr => '0', d0(0) => relational1_op_net, d1(0) => relational3_op_net_x1, y(0) => logical_y_net_x5 ); logical1: entity work.logical_80f90b97d0 port map ( ce => '0', clk => '0', clr => '0', d0(0) => relational2_op_net, d1(0) => relational3_op_net_x1, y(0) => logical1_y_net_x3 ); logical2: entity work.logical_80f90b97d0 port map ( ce => '0', clk => '0', clr => '0', d0(0) => relational3_op_net, d1(0) => relational3_op_net_x1, y(0) => logical2_y_net_x3 ); logical3: entity work.logical_80f90b97d0 port map ( ce => '0', clk => '0', clr => '0', d0(0) => relational4_op_net, d1(0) => relational3_op_net_x1, y(0) => logical3_y_net_x3 ); logical4: entity work.logical_80f90b97d0 port map ( ce => '0', clk => '0', clr => '0', d0(0) => relational5_op_net, d1(0) => relational3_op_net_x1, y(0) => logical4_y_net_x3 ); logical5: entity work.logical_80f90b97d0 port map ( ce => '0', clk => '0', clr => '0', d0(0) => relational_op_net, d1(0) => relational6_op_net, y(0) => logical5_y_net ); relational: entity work.relational_8fc7f5539b port map ( a => index_count_op_net, b => constant7_op_net, ce => '0', clk => '0', clr => '0', op(0) => relational_op_net ); relational1: entity work.relational_8fc7f5539b port map ( a => index_count_op_net, b => constant1_op_net, ce => '0', clk => '0', clr => '0', op(0) => relational1_op_net ); relational2: entity work.relational_8fc7f5539b port map ( a => index_count_op_net, b => constant2_op_net, ce => '0', clk => '0', clr => '0', op(0) => relational2_op_net ); relational3: entity work.relational_8fc7f5539b port map ( a => index_count_op_net, b => constant3_op_net, ce => '0', clk => '0', clr => '0', op(0) => relational3_op_net ); relational4: entity work.relational_8fc7f5539b port map ( a => index_count_op_net, b => constant4_op_net, ce => '0', clk => '0', clr => '0', op(0) => relational4_op_net ); relational5: entity work.relational_8fc7f5539b port map ( a => index_count_op_net, b => constant5_op_net, ce => '0', clk => '0', clr => '0', op(0) => relational5_op_net ); relational6: entity work.relational_8fc7f5539b port map ( a => counter_op_net, b => constant7_op_net, ce => '0', clk => '0', clr => '0', op(0) => relational6_op_net ); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; -- Generated from Simulink block "sg_2d_fir/5x5_Filters/Blue_Filter/5x5_Filter" entity x5x5_filter_entity_e192f59c95 is port ( ce_1: in std_logic; ce_logic_1: in std_logic; clk_1: in std_logic; coef: in std_logic_vector(6 downto 0); gain: in std_logic_vector(19 downto 0); line1: in std_logic_vector(7 downto 0); line2: in std_logic_vector(7 downto 0); line3: in std_logic_vector(7 downto 0); line4: in std_logic_vector(7 downto 0); line5: in std_logic_vector(7 downto 0); load: in std_logic; dout: out std_logic_vector(7 downto 0) ); end x5x5_filter_entity_e192f59c95; architecture structural of x5x5_filter_entity_e192f59c95 is signal ce_1_sg_x13: std_logic; signal ce_logic_1_sg_x6: std_logic; signal clk_1_sg_x13: std_logic; signal convert1_dout_net_x1: std_logic_vector(7 downto 0); signal from_register_data_out_net_x1: std_logic_vector(19 downto 0); signal l1_x2: std_logic_vector(7 downto 0); signal l2_x2: std_logic_vector(7 downto 0); signal l3_x2: std_logic_vector(7 downto 0); signal l4_x2: std_logic_vector(7 downto 0); signal l5_x2: std_logic_vector(7 downto 0); signal logical1_y_net_x3: std_logic; signal logical2_y_net_x3: std_logic; signal logical3_y_net_x3: std_logic; signal logical4_y_net_x3: std_logic; signal logical_y_net_x5: std_logic; signal relational3_op_net_x2: std_logic; signal shared_memory_data_out_net_x6: std_logic_vector(6 downto 0); begin ce_1_sg_x13 <= ce_1; ce_logic_1_sg_x6 <= ce_logic_1; clk_1_sg_x13 <= clk_1; shared_memory_data_out_net_x6 <= coef; from_register_data_out_net_x1 <= gain; l1_x2 <= line1; l2_x2 <= line2; l3_x2 <= line3; l4_x2 <= line4; l5_x2 <= line5; relational3_op_net_x2 <= load; dout <= convert1_dout_net_x1; load_sequencer_8724dffd75: entity work.load_sequencer_entity_8724dffd75 port map ( ce_1 => ce_1_sg_x13, clk_1 => clk_1_sg_x13, load => relational3_op_net_x2, load_1 => logical_y_net_x5, load_2 => logical1_y_net_x3, load_3 => logical2_y_net_x3, load_4 => logical3_y_net_x3, load_5 => logical4_y_net_x3 ); x2d_fir_587bafe04d: entity work.x2d_fir_entity_587bafe04d port map ( ce_1 => ce_1_sg_x13, ce_logic_1 => ce_logic_1_sg_x6, clk_1 => clk_1_sg_x13, coef => shared_memory_data_out_net_x6, gain => from_register_data_out_net_x1, line1 => l1_x2, line2 => l2_x2, line3 => l3_x2, line4 => l4_x2, line5 => l5_x2, load_1 => logical_y_net_x5, load_2 => logical1_y_net_x3, load_3 => logical2_y_net_x3, load_4 => logical3_y_net_x3, load_5 => logical4_y_net_x3, dout => convert1_dout_net_x1 ); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; -- Generated from Simulink block "sg_2d_fir/5x5_Filters/Blue_Filter/Line_Buffer" entity line_buffer_entity_edde027544 is port ( addr: in std_logic_vector(11 downto 0); ce_1: in std_logic; clk_1: in std_logic; data: in std_logic_vector(7 downto 0); l1: out std_logic_vector(7 downto 0); l2: out std_logic_vector(7 downto 0); l3: out std_logic_vector(7 downto 0); l4: out std_logic_vector(7 downto 0); l5: out std_logic_vector(7 downto 0) ); end line_buffer_entity_edde027544; architecture structural of line_buffer_entity_edde027544 is signal blue_x0: std_logic_vector(7 downto 0); signal ce_1_sg_x14: std_logic; signal clk_1_sg_x14: std_logic; signal constant6_op_net: std_logic; signal delay9_q_net: std_logic_vector(7 downto 0); signal l1_x3: std_logic_vector(7 downto 0); signal l2_x3: std_logic_vector(7 downto 0); signal l3_x3: std_logic_vector(7 downto 0); signal l4_x3: std_logic_vector(7 downto 0); signal l5_x3: std_logic_vector(7 downto 0); signal rctr_q_net_x0: std_logic_vector(11 downto 0); signal single_port_ram2_data_out_net: std_logic_vector(7 downto 0); signal single_port_ram3_data_out_net: std_logic_vector(7 downto 0); signal single_port_ram_data_out_net: std_logic_vector(7 downto 0); begin rctr_q_net_x0 <= addr; ce_1_sg_x14 <= ce_1; clk_1_sg_x14 <= clk_1; blue_x0 <= data; l1 <= l1_x3; l2 <= l2_x3; l3 <= l3_x3; l4 <= l4_x3; l5 <= l5_x3; constant6: entity work.constant_6293007044 port map ( ce => '0', clk => '0', clr => '0', op(0) => constant6_op_net ); delay1: entity work.delay_23f848c85b port map ( ce => ce_1_sg_x14, clk => clk_1_sg_x14, clr => '0', d => single_port_ram2_data_out_net, q => l3_x3 ); delay2: entity work.delay_9565135955 port map ( ce => ce_1_sg_x14, clk => clk_1_sg_x14, clr => '0', d => single_port_ram3_data_out_net, q => l4_x3 ); delay7: entity work.delay_fb08f2e938 port map ( ce => ce_1_sg_x14, clk => clk_1_sg_x14, clr => '0', d => delay9_q_net, q => l5_x3 ); delay8: entity work.delay_ebec135d8a port map ( ce => ce_1_sg_x14, clk => clk_1_sg_x14, clr => '0', d => single_port_ram_data_out_net, q => l2_x3 ); delay9: entity work.delay_23f848c85b port map ( ce => ce_1_sg_x14, clk => clk_1_sg_x14, clr => '0', d => blue_x0, q => delay9_q_net ); single_port_ram: entity work.xlspram generic map ( c_address_width => 12, c_width => 8, core_name0 => "bmg_62_54b11b852dca329b", latency => 1 ) port map ( addr => rctr_q_net_x0, ce => ce_1_sg_x14, clk => clk_1_sg_x14, data_in => single_port_ram2_data_out_net, en => "1", rst => "0", we(0) => constant6_op_net, data_out => single_port_ram_data_out_net ); single_port_ram1: entity work.xlspram generic map ( c_address_width => 12, c_width => 8, core_name0 => "bmg_62_54b11b852dca329b", latency => 1 ) port map ( addr => rctr_q_net_x0, ce => ce_1_sg_x14, clk => clk_1_sg_x14, data_in => single_port_ram_data_out_net, en => "1", rst => "0", we(0) => constant6_op_net, data_out => l1_x3 ); single_port_ram2: entity work.xlspram generic map ( c_address_width => 12, c_width => 8, core_name0 => "bmg_62_54b11b852dca329b", latency => 1 ) port map ( addr => rctr_q_net_x0, ce => ce_1_sg_x14, clk => clk_1_sg_x14, data_in => single_port_ram3_data_out_net, en => "1", rst => "0", we(0) => constant6_op_net, data_out => single_port_ram2_data_out_net ); single_port_ram3: entity work.xlspram generic map ( c_address_width => 12, c_width => 8, core_name0 => "bmg_62_54b11b852dca329b", latency => 1 ) port map ( addr => rctr_q_net_x0, ce => ce_1_sg_x14, clk => clk_1_sg_x14, data_in => delay9_q_net, en => "1", rst => "0", we(0) => constant6_op_net, data_out => single_port_ram3_data_out_net ); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; -- Generated from Simulink block "sg_2d_fir/5x5_Filters/Blue_Filter" entity blue_filter_entity_d29ca0c8b1 is port ( addr: in std_logic_vector(11 downto 0); ce_1: in std_logic; ce_logic_1: in std_logic; clk_1: in std_logic; coef: in std_logic_vector(6 downto 0); din: in std_logic_vector(7 downto 0); gain: in std_logic_vector(19 downto 0); load: in std_logic; dout: out std_logic_vector(7 downto 0) ); end blue_filter_entity_d29ca0c8b1; architecture structural of blue_filter_entity_d29ca0c8b1 is signal blue_x1: std_logic_vector(7 downto 0); signal ce_1_sg_x15: std_logic; signal ce_logic_1_sg_x7: std_logic; signal clk_1_sg_x15: std_logic; signal convert1_dout_net_x2: std_logic_vector(7 downto 0); signal from_register_data_out_net_x2: std_logic_vector(19 downto 0); signal l1_x3: std_logic_vector(7 downto 0); signal l2_x3: std_logic_vector(7 downto 0); signal l3_x3: std_logic_vector(7 downto 0); signal l4_x3: std_logic_vector(7 downto 0); signal l5_x3: std_logic_vector(7 downto 0); signal rctr_q_net_x1: std_logic_vector(11 downto 0); signal relational3_op_net_x3: std_logic; signal shared_memory_data_out_net_x7: std_logic_vector(6 downto 0); begin rctr_q_net_x1 <= addr; ce_1_sg_x15 <= ce_1; ce_logic_1_sg_x7 <= ce_logic_1; clk_1_sg_x15 <= clk_1; shared_memory_data_out_net_x7 <= coef; blue_x1 <= din; from_register_data_out_net_x2 <= gain; relational3_op_net_x3 <= load; dout <= convert1_dout_net_x2; line_buffer_edde027544: entity work.line_buffer_entity_edde027544 port map ( addr => rctr_q_net_x1, ce_1 => ce_1_sg_x15, clk_1 => clk_1_sg_x15, data => blue_x1, l1 => l1_x3, l2 => l2_x3, l3 => l3_x3, l4 => l4_x3, l5 => l5_x3 ); x5x5_filter_e192f59c95: entity work.x5x5_filter_entity_e192f59c95 port map ( ce_1 => ce_1_sg_x15, ce_logic_1 => ce_logic_1_sg_x7, clk_1 => clk_1_sg_x15, coef => shared_memory_data_out_net_x7, gain => from_register_data_out_net_x2, line1 => l1_x3, line2 => l2_x3, line3 => l3_x3, line4 => l4_x3, line5 => l5_x3, load => relational3_op_net_x3, dout => convert1_dout_net_x2 ); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; -- Generated from Simulink block "sg_2d_fir/5x5_Filters/Ctrl_Delay/Line_Buffer" entity line_buffer_entity_d14b7609fd is port ( addr: in std_logic_vector(11 downto 0); ce_1: in std_logic; clk_1: in std_logic; data: in std_logic_vector(4 downto 0); l3_x0: out std_logic_vector(4 downto 0) ); end line_buffer_entity_d14b7609fd; architecture structural of line_buffer_entity_d14b7609fd is signal ce_1_sg_x16: std_logic; signal clk_1_sg_x16: std_logic; signal concat_y_net_x0: std_logic_vector(4 downto 0); signal constant6_op_net: std_logic; signal delay9_q_net: std_logic_vector(4 downto 0); signal l3_x1: std_logic_vector(4 downto 0); signal rctr_q_net_x2: std_logic_vector(11 downto 0); signal single_port_ram2_data_out_net: std_logic_vector(4 downto 0); signal single_port_ram3_data_out_net: std_logic_vector(4 downto 0); begin rctr_q_net_x2 <= addr; ce_1_sg_x16 <= ce_1; clk_1_sg_x16 <= clk_1; concat_y_net_x0 <= data; l3_x0 <= l3_x1; constant6: entity work.constant_6293007044 port map ( ce => '0', clk => '0', clr => '0', op(0) => constant6_op_net ); delay1: entity work.delay_38f665f8aa port map ( ce => ce_1_sg_x16, clk => clk_1_sg_x16, clr => '0', d => single_port_ram2_data_out_net, q => l3_x1 ); delay9: entity work.delay_38f665f8aa port map ( ce => ce_1_sg_x16, clk => clk_1_sg_x16, clr => '0', d => concat_y_net_x0, q => delay9_q_net ); single_port_ram2: entity work.xlspram generic map ( c_address_width => 12, c_width => 5, core_name0 => "bmg_62_05852d43925e39b8", latency => 1 ) port map ( addr => rctr_q_net_x2, ce => ce_1_sg_x16, clk => clk_1_sg_x16, data_in => single_port_ram3_data_out_net, en => "1", rst => "0", we(0) => constant6_op_net, data_out => single_port_ram2_data_out_net ); single_port_ram3: entity work.xlspram generic map ( c_address_width => 12, c_width => 5, core_name0 => "bmg_62_05852d43925e39b8", latency => 1 ) port map ( addr => rctr_q_net_x2, ce => ce_1_sg_x16, clk => clk_1_sg_x16, data_in => delay9_q_net, en => "1", rst => "0", we(0) => constant6_op_net, data_out => single_port_ram3_data_out_net ); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; -- Generated from Simulink block "sg_2d_fir/5x5_Filters/Ctrl_Delay" entity ctrl_delay_entity_b2aeac3e46 is port ( addr: in std_logic_vector(11 downto 0); av_i: in std_logic; ce_1: in std_logic; clk_1: in std_logic; hb_i: in std_logic; hs_i: in std_logic; vb_i: in std_logic; vs_i: in std_logic; av_o: out std_logic; hb_o: out std_logic; hs_o: out std_logic; vb_o: out std_logic; vs_o: out std_logic ); end ctrl_delay_entity_b2aeac3e46; architecture structural of ctrl_delay_entity_b2aeac3e46 is signal active_video_i_net_x0: std_logic; signal bit0_y_net_x0: std_logic; signal bit1_y_net_x0: std_logic; signal bit2_y_net_x0: std_logic; signal bit3_y_net_x0: std_logic; signal bit4_y_net_x0: std_logic; signal ce_1_sg_x17: std_logic; signal clk_1_sg_x17: std_logic; signal concat_y_net_x0: std_logic_vector(4 downto 0); signal delay7_q_net: std_logic_vector(4 downto 0); signal hblank_i_net_x0: std_logic; signal hsync_i_net_x0: std_logic; signal l3_x1: std_logic_vector(4 downto 0); signal rctr_q_net_x3: std_logic_vector(11 downto 0); signal vblank_i_net_x0: std_logic; signal vsync_i_net_x0: std_logic; begin rctr_q_net_x3 <= addr; active_video_i_net_x0 <= av_i; ce_1_sg_x17 <= ce_1; clk_1_sg_x17 <= clk_1; hblank_i_net_x0 <= hb_i; hsync_i_net_x0 <= hs_i; vblank_i_net_x0 <= vb_i; vsync_i_net_x0 <= vs_i; av_o <= bit4_y_net_x0; hb_o <= bit0_y_net_x0; hs_o <= bit2_y_net_x0; vb_o <= bit1_y_net_x0; vs_o <= bit3_y_net_x0; bit0: entity work.xlslice generic map ( new_lsb => 0, new_msb => 0, x_width => 5, y_width => 1 ) port map ( x => delay7_q_net, y(0) => bit0_y_net_x0 ); bit1: entity work.xlslice generic map ( new_lsb => 1, new_msb => 1, x_width => 5, y_width => 1 ) port map ( x => delay7_q_net, y(0) => bit1_y_net_x0 ); bit2: entity work.xlslice generic map ( new_lsb => 2, new_msb => 2, x_width => 5, y_width => 1 ) port map ( x => delay7_q_net, y(0) => bit2_y_net_x0 ); bit3: entity work.xlslice generic map ( new_lsb => 3, new_msb => 3, x_width => 5, y_width => 1 ) port map ( x => delay7_q_net, y(0) => bit3_y_net_x0 ); bit4: entity work.xlslice generic map ( new_lsb => 4, new_msb => 4, x_width => 5, y_width => 1 ) port map ( x => delay7_q_net, y(0) => bit4_y_net_x0 ); concat: entity work.concat_2b3acb49f4 port map ( ce => '0', clk => '0', clr => '0', in0(0) => active_video_i_net_x0, in1(0) => vsync_i_net_x0, in2(0) => hsync_i_net_x0, in3(0) => vblank_i_net_x0, in4(0) => hblank_i_net_x0, y => concat_y_net_x0 ); delay7: entity work.delay_4714bdf2a7 port map ( ce => ce_1_sg_x17, clk => clk_1_sg_x17, clr => '0', d => l3_x1, q => delay7_q_net ); line_buffer_d14b7609fd: entity work.line_buffer_entity_d14b7609fd port map ( addr => rctr_q_net_x3, ce_1 => ce_1_sg_x17, clk_1 => clk_1_sg_x17, data => concat_y_net_x0, l3_x0 => l3_x1 ); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; -- Generated from Simulink block "sg_2d_fir/5x5_Filters/coefficient_memory" entity coefficient_memory_entity_d275723ee2 is port ( ce_1: in std_logic; clk_1: in std_logic; from_register1: in std_logic; vsync: in std_logic; constant1_x0: out std_logic; constant2_x0: out std_logic_vector(6 downto 0); counter_x0: out std_logic_vector(4 downto 0); load: out std_logic ); end coefficient_memory_entity_d275723ee2; architecture structural of coefficient_memory_entity_d275723ee2 is signal ce_1_sg_x50: std_logic; signal clk_1_sg_x50: std_logic; signal constant1_op_net_x0: std_logic; signal constant2_op_net_x0: std_logic_vector(6 downto 0); signal constant_op_net: std_logic_vector(4 downto 0); signal convert1_dout_net: std_logic; signal convert_dout_net: std_logic; signal counter_op_net_x0: std_logic_vector(4 downto 0); signal expression_dout_net: std_logic; signal from_register1_data_out_net_x0: std_logic; signal inverter_op_net: std_logic; signal register1_q_net: std_logic; signal register_q_net: std_logic; signal relational3_op_net_x10: std_logic; signal vsync_i_net_x1: std_logic; begin ce_1_sg_x50 <= ce_1; clk_1_sg_x50 <= clk_1; from_register1_data_out_net_x0 <= from_register1; vsync_i_net_x1 <= vsync; constant1_x0 <= constant1_op_net_x0; constant2_x0 <= constant2_op_net_x0; counter_x0 <= counter_op_net_x0; load <= relational3_op_net_x10; constant1: entity work.constant_963ed6358a port map ( ce => '0', clk => '0', clr => '0', op(0) => constant1_op_net_x0 ); constant2: entity work.constant_7244cd602b port map ( ce => '0', clk => '0', clr => '0', op => constant2_op_net_x0 ); constant_x0: entity work.constant_fdce3802d7 port map ( ce => '0', clk => '0', clr => '0', op => constant_op_net ); convert: entity work.xlconvert generic map ( bool_conversion => 1, din_arith => 1, din_bin_pt => 0, din_width => 1, dout_arith => 1, dout_bin_pt => 0, dout_width => 1, latency => 0, overflow => xlWrap, quantization => xlTruncate ) port map ( ce => ce_1_sg_x50, clk => clk_1_sg_x50, clr => '0', din(0) => register1_q_net, en => "1", dout(0) => convert_dout_net ); convert1: entity work.xlconvert generic map ( bool_conversion => 1, din_arith => 1, din_bin_pt => 0, din_width => 1, dout_arith => 1, dout_bin_pt => 0, dout_width => 1, latency => 0, overflow => xlWrap, quantization => xlTruncate ) port map ( ce => ce_1_sg_x50, clk => clk_1_sg_x50, clr => '0', din(0) => inverter_op_net, en => "1", dout(0) => convert1_dout_net ); counter: entity work.xlcounter_limit generic map ( cnt_15_0 => 25, cnt_31_16 => 0, cnt_47_32 => 0, cnt_63_48 => 0, core_name0 => "cntr_11_0_862f833518f4973a", count_limited => 1, op_arith => xlUnsigned, op_width => 5 ) port map ( ce => ce_1_sg_x50, clk => clk_1_sg_x50, clr => '0', en(0) => relational3_op_net_x10, rst(0) => convert_dout_net, op => counter_op_net_x0 ); expression: entity work.expr_1e33fcde03 port map ( a(0) => vsync_i_net_x1, b(0) => register_q_net, ce => '0', clk => '0', clr => '0', dout(0) => expression_dout_net ); inverter: entity work.inverter_e2b989a05e port map ( ce => ce_1_sg_x50, clk => clk_1_sg_x50, clr => '0', ip(0) => from_register1_data_out_net_x0, op(0) => inverter_op_net ); register1: entity work.xlregister generic map ( d_width => 1, init_value => b"0" ) port map ( ce => ce_1_sg_x50, clk => clk_1_sg_x50, d(0) => expression_dout_net, en => "1", rst(0) => convert1_dout_net, q(0) => register1_q_net ); register_x0: entity work.xlregister generic map ( d_width => 1, init_value => b"0" ) port map ( ce => ce_1_sg_x50, clk => clk_1_sg_x50, d(0) => vsync_i_net_x1, en => "1", rst => "0", q(0) => register_q_net ); relational3: entity work.relational_dc5bc996c9 port map ( a => constant_op_net, b => counter_op_net_x0, ce => '0', clk => '0', clr => '0', op(0) => relational3_op_net_x10 ); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; -- Generated from Simulink block "sg_2d_fir/5x5_Filters/line_ctrs/loop_ctr" entity loop_ctr_entity_861427efa6 is port ( ce_1: in std_logic; clk_1: in std_logic; reset: in std_logic; count: out std_logic_vector(11 downto 0) ); end loop_ctr_entity_861427efa6; architecture structural of loop_ctr_entity_861427efa6 is signal addsub1_s_net: std_logic_vector(11 downto 0); signal bool2_dout_net: std_logic_vector(12 downto 0); signal bool_dout_net: std_logic; signal ce_1_sg_x51: std_logic; signal clk_1_sg_x51: std_logic; signal constant1_op_net: std_logic_vector(11 downto 0); signal constant6_op_net: std_logic_vector(11 downto 0); signal constant7_op_net: std_logic_vector(11 downto 0); signal expression_dout_net_x0: std_logic; signal expression_dout_net_x1: std_logic; signal mux_y_net: std_logic_vector(12 downto 0); signal rctr_q_net_x8: std_logic_vector(11 downto 0); signal relational5_op_net: std_logic; signal tcfb1_q_net: std_logic; signal tcfb2_q_net: std_logic; begin ce_1_sg_x51 <= ce_1; clk_1_sg_x51 <= clk_1; expression_dout_net_x1 <= reset; count <= rctr_q_net_x8; addsub1: entity work.addsub_ba7fff8397 port map ( a => mux_y_net, b => constant6_op_net, ce => ce_1_sg_x51, clk => clk_1_sg_x51, clr => '0', s => addsub1_s_net ); bool: entity work.xlconvert generic map ( bool_conversion => 1, din_arith => 1, din_bin_pt => 0, din_width => 1, dout_arith => 1, dout_bin_pt => 0, dout_width => 1, latency => 0, overflow => xlWrap, quantization => xlTruncate ) port map ( ce => ce_1_sg_x51, clk => clk_1_sg_x51, clr => '0', din(0) => expression_dout_net_x1, en => "1", dout(0) => bool_dout_net ); bool2: entity work.xlconvert generic map ( bool_conversion => 0, din_arith => 1, din_bin_pt => 0, din_width => 12, dout_arith => 2, dout_bin_pt => 0, dout_width => 13, latency => 0, overflow => xlWrap, quantization => xlTruncate ) port map ( ce => ce_1_sg_x51, clk => clk_1_sg_x51, clr => '0', din => rctr_q_net_x8, en => "1", dout => bool2_dout_net ); constant1: entity work.constant_9b805894ff port map ( ce => '0', clk => '0', clr => '0', op => constant1_op_net ); constant6: entity work.constant_7c91b1b314 port map ( ce => '0', clk => '0', clr => '0', op => constant6_op_net ); constant7: entity work.constant_be6eece885 port map ( ce => '0', clk => '0', clr => '0', op => constant7_op_net ); expression: entity work.expr_f50101e101 port map ( ce => '0', clk => '0', clr => '0', reset(0) => tcfb2_q_net, tc(0) => tcfb1_q_net, dout(0) => expression_dout_net_x0 ); mux: entity work.mux_b53670f063 port map ( ce => '0', clk => '0', clr => '0', d0 => constant1_op_net, d1 => bool2_dout_net, sel(0) => expression_dout_net_x0, y => mux_y_net ); rctr: entity work.xlregister generic map ( d_width => 12, init_value => b"000000000000" ) port map ( ce => ce_1_sg_x51, clk => clk_1_sg_x51, d => addsub1_s_net, en => "1", rst => "0", q => rctr_q_net_x8 ); relational5: entity work.relational_d36fe12c1c port map ( a => rctr_q_net_x8, b => constant7_op_net, ce => '0', clk => '0', clr => '0', op(0) => relational5_op_net ); tcfb1: entity work.delay_9f02caa990 port map ( ce => ce_1_sg_x51, clk => clk_1_sg_x51, clr => '0', d(0) => relational5_op_net, q(0) => tcfb1_q_net ); tcfb2: entity work.delay_9f02caa990 port map ( ce => ce_1_sg_x51, clk => clk_1_sg_x51, clr => '0', d(0) => bool_dout_net, q(0) => tcfb2_q_net ); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; -- Generated from Simulink block "sg_2d_fir/5x5_Filters/line_ctrs" entity line_ctrs_entity_8878c4bf27 is port ( ce_1: in std_logic; clk_1: in std_logic; h: in std_logic; rst: in std_logic; addr: out std_logic_vector(11 downto 0) ); end line_ctrs_entity_8878c4bf27; architecture structural of line_ctrs_entity_8878c4bf27 is signal ce_1_sg_x52: std_logic; signal clk_1_sg_x52: std_logic; signal delay_q_net: std_logic; signal expression_dout_net_x1: std_logic; signal hsync_i_net_x1: std_logic; signal rctr_q_net_x9: std_logic_vector(11 downto 0); signal reset_net_x0: std_logic; begin ce_1_sg_x52 <= ce_1; clk_1_sg_x52 <= clk_1; hsync_i_net_x1 <= h; reset_net_x0 <= rst; addr <= rctr_q_net_x9; delay: entity work.delay_5753e4c658 port map ( ce => ce_1_sg_x52, clk => clk_1_sg_x52, clr => '0', d(0) => hsync_i_net_x1, q(0) => delay_q_net ); expression: entity work.expr_305312c97b port map ( ce => '0', clk => '0', clr => '0', d0(0) => hsync_i_net_x1, d1(0) => delay_q_net, rst(0) => reset_net_x0, dout(0) => expression_dout_net_x1 ); loop_ctr_861427efa6: entity work.loop_ctr_entity_861427efa6 port map ( ce_1 => ce_1_sg_x52, clk_1 => clk_1_sg_x52, reset => expression_dout_net_x1, count => rctr_q_net_x9 ); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; -- Generated from Simulink block "sg_2d_fir/5x5_Filters" entity x5x5_filters_entity_1ec75b0e3e is port ( av_i: in std_logic; b: in std_logic_vector(7 downto 0); ce_1: in std_logic; ce_logic_1: in std_logic; clk_1: in std_logic; from_register: in std_logic_vector(19 downto 0); from_register1: in std_logic; g: in std_logic_vector(7 downto 0); hb_i: in std_logic; hs_i: in std_logic; r: in std_logic_vector(7 downto 0); rst: in std_logic; shared_memory: in std_logic_vector(6 downto 0); vb_i: in std_logic; vs_i: in std_logic; b_o: out std_logic_vector(7 downto 0); coefficient_memory: out std_logic; coefficient_memory_x0: out std_logic_vector(6 downto 0); coefficient_memory_x1: out std_logic_vector(4 downto 0); de_o: out std_logic; g_o: out std_logic_vector(7 downto 0); hb_o: out std_logic; hs_o: out std_logic; r_o: out std_logic_vector(7 downto 0); vb_o: out std_logic; vs_o: out std_logic ); end x5x5_filters_entity_1ec75b0e3e; architecture structural of x5x5_filters_entity_1ec75b0e3e is signal active_video_i_net_x1: std_logic; signal bit0_y_net_x1: std_logic; signal bit1_y_net_x1: std_logic; signal bit2_y_net_x1: std_logic; signal bit3_y_net_x1: std_logic; signal bit4_y_net_x1: std_logic; signal blue_x2: std_logic_vector(7 downto 0); signal ce_1_sg_x53: std_logic; signal ce_logic_1_sg_x24: std_logic; signal clk_1_sg_x53: std_logic; signal constant1_op_net_x1: std_logic; signal constant2_op_net_x1: std_logic_vector(6 downto 0); signal convert1_dout_net_x5: std_logic_vector(7 downto 0); signal convert1_dout_net_x6: std_logic_vector(7 downto 0); signal convert1_dout_net_x7: std_logic_vector(7 downto 0); signal counter_op_net_x1: std_logic_vector(4 downto 0); signal from_register1_data_out_net_x1: std_logic; signal from_register_data_out_net_x9: std_logic_vector(19 downto 0); signal green_x2: std_logic_vector(7 downto 0); signal hblank_i_net_x1: std_logic; signal hsync_i_net_x2: std_logic; signal rctr_q_net_x9: std_logic_vector(11 downto 0); signal red_x2: std_logic_vector(7 downto 0); signal relational3_op_net_x10: std_logic; signal reset_net_x1: std_logic; signal shared_memory_data_out_net_x24: std_logic_vector(6 downto 0); signal vblank_i_net_x1: std_logic; signal vsync_i_net_x2: std_logic; begin active_video_i_net_x1 <= av_i; blue_x2 <= b; ce_1_sg_x53 <= ce_1; ce_logic_1_sg_x24 <= ce_logic_1; clk_1_sg_x53 <= clk_1; from_register_data_out_net_x9 <= from_register; from_register1_data_out_net_x1 <= from_register1; green_x2 <= g; hblank_i_net_x1 <= hb_i; hsync_i_net_x2 <= hs_i; red_x2 <= r; reset_net_x1 <= rst; shared_memory_data_out_net_x24 <= shared_memory; vblank_i_net_x1 <= vb_i; vsync_i_net_x2 <= vs_i; b_o <= convert1_dout_net_x5; coefficient_memory <= constant1_op_net_x1; coefficient_memory_x0 <= constant2_op_net_x1; coefficient_memory_x1 <= counter_op_net_x1; de_o <= bit4_y_net_x1; g_o <= convert1_dout_net_x6; hb_o <= bit0_y_net_x1; hs_o <= bit2_y_net_x1; r_o <= convert1_dout_net_x7; vb_o <= bit1_y_net_x1; vs_o <= bit3_y_net_x1; blue_filter_d29ca0c8b1: entity work.blue_filter_entity_d29ca0c8b1 port map ( addr => rctr_q_net_x9, ce_1 => ce_1_sg_x53, ce_logic_1 => ce_logic_1_sg_x24, clk_1 => clk_1_sg_x53, coef => shared_memory_data_out_net_x24, din => blue_x2, gain => from_register_data_out_net_x9, load => relational3_op_net_x10, dout => convert1_dout_net_x5 ); coefficient_memory_d275723ee2: entity work.coefficient_memory_entity_d275723ee2 port map ( ce_1 => ce_1_sg_x53, clk_1 => clk_1_sg_x53, from_register1 => from_register1_data_out_net_x1, vsync => vsync_i_net_x2, constant1_x0 => constant1_op_net_x1, constant2_x0 => constant2_op_net_x1, counter_x0 => counter_op_net_x1, load => relational3_op_net_x10 ); ctrl_delay_b2aeac3e46: entity work.ctrl_delay_entity_b2aeac3e46 port map ( addr => rctr_q_net_x9, av_i => active_video_i_net_x1, ce_1 => ce_1_sg_x53, clk_1 => clk_1_sg_x53, hb_i => hblank_i_net_x1, hs_i => hsync_i_net_x2, vb_i => vblank_i_net_x1, vs_i => vsync_i_net_x2, av_o => bit4_y_net_x1, hb_o => bit0_y_net_x1, hs_o => bit2_y_net_x1, vb_o => bit1_y_net_x1, vs_o => bit3_y_net_x1 ); green_filter_dc51fce7d5: entity work.blue_filter_entity_d29ca0c8b1 port map ( addr => rctr_q_net_x9, ce_1 => ce_1_sg_x53, ce_logic_1 => ce_logic_1_sg_x24, clk_1 => clk_1_sg_x53, coef => shared_memory_data_out_net_x24, din => green_x2, gain => from_register_data_out_net_x9, load => relational3_op_net_x10, dout => convert1_dout_net_x6 ); line_ctrs_8878c4bf27: entity work.line_ctrs_entity_8878c4bf27 port map ( ce_1 => ce_1_sg_x53, clk_1 => clk_1_sg_x53, h => hsync_i_net_x2, rst => reset_net_x1, addr => rctr_q_net_x9 ); red_filter_078d79d78e: entity work.blue_filter_entity_d29ca0c8b1 port map ( addr => rctr_q_net_x9, ce_1 => ce_1_sg_x53, ce_logic_1 => ce_logic_1_sg_x24, clk_1 => clk_1_sg_x53, coef => shared_memory_data_out_net_x24, din => red_x2, gain => from_register_data_out_net_x9, load => relational3_op_net_x10, dout => convert1_dout_net_x7 ); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; -- Generated from Simulink block "sg_2d_fir/EDK Processor" entity edk_processor_entity_45d14a6139 is port ( plb_abus: in std_logic_vector(31 downto 0); plb_ce_1: in std_logic; plb_clk_1: in std_logic; plb_pavalid: in std_logic; plb_rnw: in std_logic; plb_wrdbus: in std_logic_vector(31 downto 0); sg_plb_addrpref: in std_logic_vector(19 downto 0); shared_memory: in std_logic_vector(6 downto 0); splb_rst: in std_logic; to_register: in std_logic; to_register1: in std_logic_vector(19 downto 0); constant5_x0: out std_logic; plb_decode_x0: out std_logic; plb_decode_x1: out std_logic; plb_decode_x2: out std_logic; plb_decode_x3: out std_logic; plb_decode_x4: out std_logic_vector(31 downto 0); plb_memmap_x0: out std_logic; plb_memmap_x1: out std_logic; plb_memmap_x2: out std_logic_vector(19 downto 0); plb_memmap_x3: out std_logic; plb_memmap_x4: out std_logic_vector(4 downto 0); plb_memmap_x5: out std_logic_vector(6 downto 0); plb_memmap_x6: out std_logic ); end edk_processor_entity_45d14a6139; architecture structural of edk_processor_entity_45d14a6139 is signal bankaddr: std_logic_vector(1 downto 0); signal coef_buffer_addr_x0: std_logic_vector(4 downto 0); signal coef_buffer_din_x0: std_logic_vector(6 downto 0); signal coef_buffer_dout_x0: std_logic_vector(6 downto 0); signal coef_buffer_we_x0: std_logic; signal coef_gain_din_x0: std_logic_vector(19 downto 0); signal coef_gain_dout_x0: std_logic_vector(19 downto 0); signal coef_gain_en_x0: std_logic; signal coef_update_din_x0: std_logic; signal coef_update_dout_x0: std_logic; signal coef_update_en_x0: std_logic; signal linearaddr: std_logic_vector(7 downto 0); signal plb_abus_net_x0: std_logic_vector(31 downto 0); signal plb_ce_1_sg_x0: std_logic; signal plb_clk_1_sg_x0: std_logic; signal plb_pavalid_net_x0: std_logic; signal plb_rnw_net_x0: std_logic; signal plb_wrdbus_net_x0: std_logic_vector(31 downto 0); signal rddata: std_logic_vector(31 downto 0); signal rnwreg: std_logic; signal sg_plb_addrpref_net_x0: std_logic_vector(19 downto 0); signal sl_addrack_x0: std_logic; signal sl_rdcomp_x0: std_logic; signal sl_rddack_x0: std_logic; signal sl_rddbus_x0: std_logic_vector(31 downto 0); signal sl_wait_x0: std_logic; signal sl_wrdack_x0: std_logic; signal splb_rst_net_x0: std_logic; signal wrdbusreg: std_logic_vector(31 downto 0); begin plb_abus_net_x0 <= plb_abus; plb_ce_1_sg_x0 <= plb_ce_1; plb_clk_1_sg_x0 <= plb_clk_1; plb_pavalid_net_x0 <= plb_pavalid; plb_rnw_net_x0 <= plb_rnw; plb_wrdbus_net_x0 <= plb_wrdbus; sg_plb_addrpref_net_x0 <= sg_plb_addrpref; coef_buffer_dout_x0 <= shared_memory; splb_rst_net_x0 <= splb_rst; coef_update_dout_x0 <= to_register; coef_gain_dout_x0 <= to_register1; constant5_x0 <= sl_wait_x0; plb_decode_x0 <= sl_addrack_x0; plb_decode_x1 <= sl_rdcomp_x0; plb_decode_x2 <= sl_wrdack_x0; plb_decode_x3 <= sl_rddack_x0; plb_decode_x4 <= sl_rddbus_x0; plb_memmap_x0 <= coef_update_din_x0; plb_memmap_x1 <= coef_update_en_x0; plb_memmap_x2 <= coef_gain_din_x0; plb_memmap_x3 <= coef_gain_en_x0; plb_memmap_x4 <= coef_buffer_addr_x0; plb_memmap_x5 <= coef_buffer_din_x0; plb_memmap_x6 <= coef_buffer_we_x0; constant5: entity work.constant_963ed6358a port map ( ce => '0', clk => '0', clr => '0', op(0) => sl_wait_x0 ); plb_decode: entity work.mcode_block_f4d0462e0e port map ( addrpref => sg_plb_addrpref_net_x0, ce => plb_ce_1_sg_x0, clk => plb_clk_1_sg_x0, clr => '0', plbabus => plb_abus_net_x0, plbpavalid(0) => plb_pavalid_net_x0, plbrnw(0) => plb_rnw_net_x0, plbrst(0) => splb_rst_net_x0, plbwrdbus => plb_wrdbus_net_x0, rddata => rddata, addrack(0) => sl_addrack_x0, bankaddr => bankaddr, linearaddr => linearaddr, rdcomp(0) => sl_rdcomp_x0, rddack(0) => sl_rddack_x0, rddbus => sl_rddbus_x0, rnwreg(0) => rnwreg, wrdack(0) => sl_wrdack_x0, wrdbusreg => wrdbusreg ); plb_memmap: entity work.mcode_block_6fff803424 port map ( addrack(0) => sl_addrack_x0, bankaddr => bankaddr, ce => plb_ce_1_sg_x0, clk => plb_clk_1_sg_x0, clr => '0', linearaddr => linearaddr, rnwreg(0) => rnwreg, sm_coef_buffer => coef_buffer_dout_x0, sm_coef_gain => coef_gain_dout_x0, sm_coef_update(0) => coef_update_dout_x0, wrdbus => wrdbusreg, read_bank_out => rddata, sm_coef_buffer_addr => coef_buffer_addr_x0, sm_coef_buffer_din => coef_buffer_din_x0, sm_coef_buffer_we(0) => coef_buffer_we_x0, sm_coef_gain_din => coef_gain_din_x0, sm_coef_gain_en(0) => coef_gain_en_x0, sm_coef_update_din(0) => coef_update_din_x0, sm_coef_update_en(0) => coef_update_en_x0 ); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; -- Generated from Simulink block "sg_2d_fir" entity sg_2d_fir is port ( active_video_i: in std_logic; ce_1: in std_logic; ce_logic_1: in std_logic; clk_1: in std_logic; data_out: in std_logic_vector(19 downto 0); data_out_x0: in std_logic; data_out_x1: in std_logic_vector(6 downto 0); data_out_x2: in std_logic_vector(6 downto 0); dout: in std_logic; dout_x0: in std_logic_vector(19 downto 0); hblank_i: in std_logic; hsync_i: in std_logic; plb_abus: in std_logic_vector(31 downto 0); plb_ce_1: in std_logic; plb_clk_1: in std_logic; plb_pavalid: in std_logic; plb_rnw: in std_logic; plb_wrdbus: in std_logic_vector(31 downto 0); reset: in std_logic; sg_plb_addrpref: in std_logic_vector(19 downto 0); splb_rst: in std_logic; vblank_i: in std_logic; video_data_i: in std_logic_vector(23 downto 0); vsync_i: in std_logic; active_video_o: out std_logic; addr: out std_logic_vector(4 downto 0); addr_x0: out std_logic_vector(4 downto 0); data_in: out std_logic_vector(6 downto 0); data_in_x0: out std_logic; data_in_x1: out std_logic_vector(19 downto 0); data_in_x2: out std_logic_vector(6 downto 0); en: out std_logic; en_x0: out std_logic; hblank_o: out std_logic; hsync_o: out std_logic; sl_addrack: out std_logic; sl_rdcomp: out std_logic; sl_rddack: out std_logic; sl_rddbus: out std_logic_vector(31 downto 0); sl_wait: out std_logic; sl_wrcomp: out std_logic; sl_wrdack: out std_logic; vblank_o: out std_logic; video_data_o: out std_logic_vector(23 downto 0); vsync_o: out std_logic; we: out std_logic; we_x0: out std_logic ); end sg_2d_fir; architecture structural of sg_2d_fir is attribute core_generation_info: string; attribute core_generation_info of structural : architecture is "sg_2d_fir,sysgen_core,{clock_period=10.00000000,clocking=Clock_Enables,sample_periods=1.00000000000 1.00000000000,testbench=0,total_blocks=711,xilinx_adder_subtracter_block=13,xilinx_arithmetic_relational_operator_block=23,xilinx_assert_block=3,xilinx_bit_slice_extractor_block=11,xilinx_bitwise_expression_evaluator_block=3,xilinx_bus_concatenator_block=2,xilinx_bus_multiplexer_block=4,xilinx_constant_block_block=29,xilinx_counter_block=7,xilinx_delay_block=25,xilinx_edk_processor_block=1,xilinx_fir_compiler_5_0_block=15,xilinx_gateway_in_block=13,xilinx_gateway_out_block=13,xilinx_inverter_block=16,xilinx_logical_block_block=33,xilinx_mcode_block_block=2,xilinx_multiplier_block=3,xilinx_negate_block_block=3,xilinx_register_block=63,xilinx_shared_memory_based_from_register_block=2,xilinx_shared_memory_based_to_register_block=2,xilinx_shared_memory_random_access_memory_block=2,xilinx_single_port_random_access_memory_block=16,xilinx_system_generator_block=1,xilinx_type_converter_block=7,}"; signal active_video_i_net: std_logic; signal active_video_o_net: std_logic; signal addr_net: std_logic_vector(4 downto 0); signal addr_x0_net: std_logic_vector(4 downto 0); signal blue_x2: std_logic_vector(7 downto 0); signal ce_1_sg_x54: std_logic; signal ce_logic_1_sg_x25: std_logic; signal clk_1_sg_x54: std_logic; signal convert1_dout_net_x5: std_logic_vector(7 downto 0); signal convert1_dout_net_x6: std_logic_vector(7 downto 0); signal convert1_dout_net_x7: std_logic_vector(7 downto 0); signal data_in_net: std_logic_vector(6 downto 0); signal data_in_x0_net: std_logic; signal data_in_x1_net: std_logic_vector(19 downto 0); signal data_in_x2_net: std_logic_vector(6 downto 0); signal data_out_net: std_logic_vector(19 downto 0); signal data_out_x0_net: std_logic; signal data_out_x1_net: std_logic_vector(6 downto 0); signal data_out_x2_net: std_logic_vector(6 downto 0); signal dout_net: std_logic; signal dout_x0_net: std_logic_vector(19 downto 0); signal en_net: std_logic; signal en_x0_net: std_logic; signal green_x2: std_logic_vector(7 downto 0); signal hblank_i_net: std_logic; signal hblank_o_net: std_logic; signal hsync_i_net: std_logic; signal hsync_o_net: std_logic; signal plb_abus_net: std_logic_vector(31 downto 0); signal plb_ce_1_sg_x1: std_logic; signal plb_clk_1_sg_x1: std_logic; signal plb_pavalid_net: std_logic; signal plb_rnw_net: std_logic; signal plb_wrdbus_net: std_logic_vector(31 downto 0); signal red_x2: std_logic_vector(7 downto 0); signal reset_net: std_logic; signal sg_plb_addrpref_net: std_logic_vector(19 downto 0); signal sl_addrack_net: std_logic; signal sl_rdcomp_net: std_logic; signal sl_rddack_net: std_logic; signal sl_rddbus_net: std_logic_vector(31 downto 0); signal sl_wait_net: std_logic; signal sl_wrdack_x1: std_logic; signal splb_rst_net: std_logic; signal vblank_i_net: std_logic; signal vblank_o_net: std_logic; signal video_data_i_net: std_logic_vector(23 downto 0); signal video_data_o_net: std_logic_vector(23 downto 0); signal vsync_i_net: std_logic; signal vsync_o_net: std_logic; signal we_net: std_logic; signal we_x0_net: std_logic; begin active_video_i_net <= active_video_i; ce_1_sg_x54 <= ce_1; ce_logic_1_sg_x25 <= ce_logic_1; clk_1_sg_x54 <= clk_1; data_out_net <= data_out; data_out_x0_net <= data_out_x0; data_out_x1_net <= data_out_x1; data_out_x2_net <= data_out_x2; dout_net <= dout; dout_x0_net <= dout_x0; hblank_i_net <= hblank_i; hsync_i_net <= hsync_i; plb_abus_net <= plb_abus; plb_ce_1_sg_x1 <= plb_ce_1; plb_clk_1_sg_x1 <= plb_clk_1; plb_pavalid_net <= plb_pavalid; plb_rnw_net <= plb_rnw; plb_wrdbus_net <= plb_wrdbus; reset_net <= reset; sg_plb_addrpref_net <= sg_plb_addrpref; splb_rst_net <= splb_rst; vblank_i_net <= vblank_i; video_data_i_net <= video_data_i; vsync_i_net <= vsync_i; active_video_o <= active_video_o_net; addr <= addr_net; addr_x0 <= addr_x0_net; data_in <= data_in_net; data_in_x0 <= data_in_x0_net; data_in_x1 <= data_in_x1_net; data_in_x2 <= data_in_x2_net; en <= en_net; en_x0 <= en_x0_net; hblank_o <= hblank_o_net; hsync_o <= hsync_o_net; sl_addrack <= sl_addrack_net; sl_rdcomp <= sl_rdcomp_net; sl_rddack <= sl_rddack_net; sl_rddbus <= sl_rddbus_net; sl_wait <= sl_wait_net; sl_wrcomp <= sl_wrdack_x1; sl_wrdack <= sl_wrdack_x1; vblank_o <= vblank_o_net; video_data_o <= video_data_o_net; vsync_o <= vsync_o_net; we <= we_net; we_x0 <= we_x0_net; concat: entity work.concat_d0d1b9533e port map ( ce => '0', clk => '0', clr => '0', in0 => convert1_dout_net_x7, in1 => convert1_dout_net_x6, in2 => convert1_dout_net_x5, y => video_data_o_net ); edk_processor_45d14a6139: entity work.edk_processor_entity_45d14a6139 port map ( plb_abus => plb_abus_net, plb_ce_1 => plb_ce_1_sg_x1, plb_clk_1 => plb_clk_1_sg_x1, plb_pavalid => plb_pavalid_net, plb_rnw => plb_rnw_net, plb_wrdbus => plb_wrdbus_net, sg_plb_addrpref => sg_plb_addrpref_net, shared_memory => data_out_x2_net, splb_rst => splb_rst_net, to_register => dout_net, to_register1 => dout_x0_net, constant5_x0 => sl_wait_net, plb_decode_x0 => sl_addrack_net, plb_decode_x1 => sl_rdcomp_net, plb_decode_x2 => sl_wrdack_x1, plb_decode_x3 => sl_rddack_net, plb_decode_x4 => sl_rddbus_net, plb_memmap_x0 => data_in_x0_net, plb_memmap_x1 => en_net, plb_memmap_x2 => data_in_x1_net, plb_memmap_x3 => en_x0_net, plb_memmap_x4 => addr_x0_net, plb_memmap_x5 => data_in_x2_net, plb_memmap_x6 => we_x0_net ); slice15downto8: entity work.xlslice generic map ( new_lsb => 8, new_msb => 15, x_width => 24, y_width => 8 ) port map ( x => video_data_i_net, y => green_x2 ); slice23downto16: entity work.xlslice generic map ( new_lsb => 16, new_msb => 23, x_width => 24, y_width => 8 ) port map ( x => video_data_i_net, y => red_x2 ); slice7downto0: entity work.xlslice generic map ( new_lsb => 0, new_msb => 7, x_width => 24, y_width => 8 ) port map ( x => video_data_i_net, y => blue_x2 ); x5x5_filters_1ec75b0e3e: entity work.x5x5_filters_entity_1ec75b0e3e port map ( av_i => active_video_i_net, b => blue_x2, ce_1 => ce_1_sg_x54, ce_logic_1 => ce_logic_1_sg_x25, clk_1 => clk_1_sg_x54, from_register => data_out_net, from_register1 => data_out_x0_net, g => green_x2, hb_i => hblank_i_net, hs_i => hsync_i_net, r => red_x2, rst => reset_net, shared_memory => data_out_x1_net, vb_i => vblank_i_net, vs_i => vsync_i_net, b_o => convert1_dout_net_x5, coefficient_memory => we_net, coefficient_memory_x0 => data_in_net, coefficient_memory_x1 => addr_net, de_o => active_video_o_net, g_o => convert1_dout_net_x6, hb_o => hblank_o_net, hs_o => hsync_o_net, r_o => convert1_dout_net_x7, vb_o => vblank_o_net, vs_o => vsync_o_net ); end structural;
gpl-3.0
0f04741daa59271718c86b0d1f191eeb
0.584853
3.220045
false
false
false
false
hoglet67/AtomFpga
src/common/AVR8/JTAG_OCD_Prg/JTAGPack.vhd
4
3,224
--********************************************************************************************** -- Constants for OCD and "Flash" controller for AVR Core -- Version 0.31 -- Modified 04.06.2004 -- Designed by Ruslan Lepetenok --********************************************************************************************** library IEEE; use IEEE.std_logic_1164.all; package JTAGPack is constant CInstrLength : positive := 4; -- JTAG instructions constant C_BYPASS : std_logic_vector(CInstrLength-1 downto 0) := x"F"; constant C_SAMPLE_PRELOAD : std_logic_vector(CInstrLength-1 downto 0) := x"2"; constant C_EXTEST : std_logic_vector(CInstrLength-1 downto 0) := x"0"; constant C_IDCODE : std_logic_vector(CInstrLength-1 downto 0) := x"1"; constant C_AVR_RESET : std_logic_vector(CInstrLength-1 downto 0) := x"C"; -- Program constant C_PROG_ENABLE : std_logic_vector(CInstrLength-1 downto 0) := x"4"; constant C_PROG_COMMANDS : std_logic_vector(CInstrLength-1 downto 0) := x"5"; constant C_PROG_PAGELOAD : std_logic_vector(CInstrLength-1 downto 0) := x"6"; constant C_PROG_PAGEREAD : std_logic_vector(CInstrLength-1 downto 0) := x"7"; -- OCD (Private) constant C_FORCE_BREAK : std_logic_vector(CInstrLength-1 downto 0) := x"8"; constant C_RUN : std_logic_vector(CInstrLength-1 downto 0) := x"9"; constant C_EX_INST : std_logic_vector(CInstrLength-1 downto 0) := x"A"; constant C_OCD_ACCESS : std_logic_vector(CInstrLength-1 downto 0) := x"B"; constant C_UNUSED_3 : std_logic_vector(CInstrLength-1 downto 0) := x"3"; constant C_UNUSED_D : std_logic_vector(CInstrLength-1 downto 0) := x"D"; constant C_UNUSED_E : std_logic_vector(CInstrLength-1 downto 0) := x"E"; constant CInitInstrRegVal : std_logic_vector(CInstrLength-1 downto 0) := C_IDCODE; -- May be C_IDCODE or C_BYPASS -- IDCODE register fields --constant CVersion : std_logic_vector(3 downto 0) := x"E"; -- Version Number (ATmega16) --constant CPartNumber : std_logic_vector(15 downto 0) := x"9403"; -- Part Number (ATmega16) constant CVersion : std_logic_vector(3 downto 0) := x"6"; -- Version Number (ATmega128) constant CPartNumber : std_logic_vector(15 downto 0) := x"9702"; -- Part Number (ATmega128) constant CManufacturerId : std_logic_vector(10 downto 0) := "000"&x"1F"; -- Manufacturer ID(Atmel) constant C_ProgEnableVect : std_logic_vector(15 downto 0) := x"A370"; -- OCD register addresses constant C_OCDPSB0Adr : std_logic_vector(3 downto 0) := x"0"; constant C_OCDPSB1Adr : std_logic_vector(3 downto 0) := x"1"; constant C_OCDPDMSBAdr : std_logic_vector(3 downto 0) := x"2"; constant C_OCDPDSBAdr : std_logic_vector(3 downto 0) := x"3"; constant C_OCDBCRAdr : std_logic_vector(3 downto 0) := x"8"; constant C_OCDBSRAdr : std_logic_vector(3 downto 0) := x"9"; constant C_OCDOCDRAdr : std_logic_vector(3 downto 0) := x"C"; constant C_OCDCSRAdr : std_logic_vector(3 downto 0) := x"D"; constant C_AVRBreakInst : std_logic_vector(15 downto 0) := x"9598"; constant C_MaxEraseAdr : std_logic_vector(15 downto 0) := x"FFFF"; end JTAGPack;
apache-2.0
61533ab7830012f04ef5eaf06989a6cd
0.624069
3.001862
false
false
false
false
hoglet67/AtomFpga
src/common/AVR8/resync/rsnc_vect.vhd
4
2,053
--********************************************************************************************** -- Resynchronizer (for n-bit vector) -- Version 0.1 -- Modified 10.01.2007 -- Designed by Ruslan Lepetenok --********************************************************************************************** library IEEE; use IEEE.std_logic_1164.all; entity rsnc_vect is generic( width : integer := 8; add_stgs_num : integer := 0; inv_f_stgs : integer := 0 ); port( clk : in std_logic; di : in std_logic_vector(width-1 downto 0); do : out std_logic_vector(width-1 downto 0) ); end rsnc_vect; architecture rtl of rsnc_vect is type rsnc_vect_type is array(add_stgs_num+1 downto 0) of std_logic_vector(width-1 downto 0); signal rsnc_rg_current : rsnc_vect_type; signal rsnc_rg_next : rsnc_vect_type; begin inverted_first_stg:if (inv_f_stgs/=0) generate seq_f_fe_prc:process(clk) begin if(clk='0' and clk'event) then -- Clock (falling edge) rsnc_rg_current(rsnc_rg_current'low) <= rsnc_rg_next(rsnc_rg_next'low); end if; end process; end generate; norm_first_stg:if (inv_f_stgs=0) generate seq_f_re_prc:process(clk) begin if(clk='1' and clk'event) then -- Clock (rising edge) rsnc_rg_current(rsnc_rg_current'low) <= rsnc_rg_next(rsnc_rg_next'low); end if; end process; end generate; seq_re_prc:process(clk) begin if(clk='1' and clk'event) then -- Clock (rising edge) rsnc_rg_current(rsnc_rg_current'high downto rsnc_rg_current'low+1) <= rsnc_rg_next(rsnc_rg_current'high downto rsnc_rg_current'low+1); end if; end process; comb_prc:process(di,rsnc_rg_current) begin rsnc_rg_next(0) <= di; for i in 1 to rsnc_rg_next'high loop rsnc_rg_next(i) <= rsnc_rg_current(i-1); end loop; end process; do <= rsnc_rg_current(rsnc_rg_current'high); end rtl;
apache-2.0
b1d560ed3e388853178e0942217406eb
0.539211
3.05052
false
false
false
false
Alabamajack/Garfield
FPGA_Design/ip_intern/Rotary_Encoder/tb/rotary_encoder_avalon_tb.vhd
1
2,326
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity rotary_encoder_avalon_tb is end entity rotary_encoder_avalon_tb; architecture RTL of rotary_encoder_avalon_tb is constant datawidth : natural := 32; constant period : time := 10 ns; -- 100 Mhz signal clk : std_logic; signal rst : std_logic; signal address : std_logic_vector(0 downto 0) := (others => '0'); signal read : std_logic := '0'; signal write : std_logic := '0'; signal chipselect : std_logic := '0'; signal writedata : std_logic_vector(datawidth - 1 downto 0) := (others => '0'); signal readdata : std_logic_vector(datawidth - 1 downto 0); signal waitrequest : std_logic; signal rotary_signal : std_logic := '0'; begin clock_driver : process begin clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2; end process clock_driver; rotary_signal_proc : process begin rotary_signal <= '0'; wait for 1 ms; rotary_signal <= '1'; wait for 1 ms; end process rotary_signal_proc; av_rot_inst : entity work.rotary_encoder_avalon generic map( datawidth => datawidth ) port map( clk => clk, rst => rst, address => address, read => read, write => write, chipselect => chipselect, writedata => writedata, readdata => readdata, waitrequest => waitrequest, rotary_signal => rotary_signal ); stim_proc : process is begin rst <= '1'; wait until rising_edge(clk); rst <= '0'; address <= (others => '0'); write <= '1'; chipselect <= '1'; writedata <= x"00000001"; wait until falling_edge(waitrequest); chipselect <= '0'; write <= '0'; wait for 30 ms; wait until rising_edge(clk); chipselect <= '1'; read <= '1'; address <= "1"; wait until rising_edge(clk); chipselect <= '0'; read <= '0'; wait until rising_edge(clk); address <= "0"; chipselect <= '1'; write <= '1'; writedata <= x"00000003"; wait until falling_edge(waitrequest); chipselect <= '0'; wait; end process stim_proc; end architecture RTL;
gpl-3.0
cf7468f0defaa6b7b14205cbe64a5fb1
0.55417
3.361272
false
false
false
false
GSimas/EEL5105
PROJETO-EEL5105/Projeto/Mux8x1.vhd
2
515
library IEEE; use IEEE.Std_Logic_1164.all; --Multiplexador 8x1 entity mux8x1 is port (IN0,IN1,IN2,IN3,IN4,IN5,IN6,IN7: in std_logic; REG: out std_logic; SW: in std_logic_vector(2 downto 0) ); end mux8x1; --Definicao Arquitetura architecture circuito of mux8x1 is begin REG <= IN0 when SW = "000" else IN1 when SW = "001" else IN2 when SW = "010" else IN3 when SW = "011" else IN4 when SW = "100" else IN5 when SW = "101" else IN6 when SW = "110" else IN7; end circuito;
mit
ef369f6bc58d08be2e2aeb64463d7ed7
0.648544
2.512195
false
false
false
false
GSimas/EEL5105
Rep CAEE/11.2.Projeto/_PROJETO/expoente.vhd
1
3,167
-- ALUNOS: -- Bruno Luiz da Silva -- Gustavo Fernades -- -- -- TÍTULO: -- Expoente -- -- -- RESUMO: -- Calcula o expoente baseado na normalização e nos expoentes dados -- -- -- ENTRADAS/SAÍDAS (I/O): -- (I) a,b: entradas de 4 bits cada que serão os expoentes que o usuário dará -- (I) normal: entrada que receberá o número de vezes que a mantissa foi deslocada para ficar normalizada -- (I) arguments: argumentos que serão recebidos para realizar a soma dos expoentes dados ou o resultado -- dessa soma mais o número de deslocamentos realizados. -- (I) clk,rst: clock e reset, sendo que o reset zera todas saídas -- (O) q: saída do componente, sendo que será esse o expoente final -- -- -- DESCRIÇÃO: -- Esse componente será responsável por dar o expoente da multiplicação que será realizada. Para tal o -- usuário entrará com os expoentes (em a e b) e dará o valor "110" para o "argument" para realizar a -- soma de ambos. Para previnir casos onde houver uma soma que extrapole o valor "1111" (7 em decimal) -- então foi adicionado um bit extra na saída para armazenar o possível valor extra. Em algum momento -- será enviado o número de deslocamentos realizados para normalizar a mantissa (normal) e assim terá-se -- um valor negativo que deverá ser decrementado do atual expoente. Após essa decrementação então tem-se -- o expoente final, porém ele deve estar na faixa de "0000" a "1111" (0 a 15 em decimal), pois caso -- extrapole essa faixa ele não poderá apresentar o valor correto nos LEDs designados sendo assim um caso -- de overflow, que ativará o LED designado para tal. -- -- -- ANEXO - ARGUMENTS: -- O "arguments" será dado pela FSM e o mesmo é ligado ao bloco de multiplicação. Aproveitando essa mesma -- saída então usa-se o arguments aqui. Os sinais utilizados e o que fazem são: -- -- 110: realiza a soma entre os dois expoentes dados (a e b). -- 111: realiza a subtração do atual valor guardado (soma de a e b) com o número de deslocamentos realizados -- na normalização da mantissa. -- -- -- (I): INPUT / (O): OUTPUT library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity expoente is generic(N: natural := 4); port( a,b: in std_logic_vector((N-1) downto 0); -- Expoentes dados pelo usuário normal: in std_logic_vector((N-1) downto 0); -- Deslocamentos que foram necessários para normalizar a mantissa arguments: in std_logic_vector(2 downto 0); -- Argumentos que dará as ordens para o componente clk,rst: in std_logic; -- Clock e reset q: out std_logic_vector((N) downto 0) -- Expoente final ); end expoente; architecture func of expoente is signal aux: std_logic_vector(N downto 0); begin EXPOENTE: process(clk,rst) begin if(rst = '1') then aux <= (others => '0'); elsif(rising_edge(clk)) then if(arguments = "110") then -- Soma dos dois expoentes dados com o bit extra para o carry aux <= ('0'&a) + ('0'&b); elsif(arguments = "111") then -- Decremento do resultado da soma anterior com o número de deslocamentos da normalização aux <= aux - ('0'&normal); else aux <= aux; end if; end if; q <= aux; end process; end func;
mit
2a3669e2b9430dd301c23c4b08d2a06e
0.705715
2.962582
false
false
false
false
fquinto/Wireless_sensor_network
Avnet_UPC/hdl/elaborate/lmb_bram_elaborate_v1_00_a/hdl/vhdl/lmb_bram_elaborate.vhd
1
34,180
------------------------------------------------------------------------------- -- lmb_bram_elaborate.vhd ------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity lmb_bram_elaborate is generic ( C_MEMSIZE : integer; C_PORT_DWIDTH : integer; C_PORT_AWIDTH : integer; C_NUM_WE : integer; C_FAMILY : string ); port ( BRAM_Rst_A : in std_logic; BRAM_Clk_A : in std_logic; BRAM_EN_A : in std_logic; BRAM_WEN_A : in std_logic_vector(0 to C_NUM_WE-1); BRAM_Addr_A : in std_logic_vector(0 to C_PORT_AWIDTH-1); BRAM_Din_A : out std_logic_vector(0 to C_PORT_DWIDTH-1); BRAM_Dout_A : in std_logic_vector(0 to C_PORT_DWIDTH-1); BRAM_Rst_B : in std_logic; BRAM_Clk_B : in std_logic; BRAM_EN_B : in std_logic; BRAM_WEN_B : in std_logic_vector(0 to C_NUM_WE-1); BRAM_Addr_B : in std_logic_vector(0 to C_PORT_AWIDTH-1); BRAM_Din_B : out std_logic_vector(0 to C_PORT_DWIDTH-1); BRAM_Dout_B : in std_logic_vector(0 to C_PORT_DWIDTH-1) ); attribute keep_hierarchy : STRING; attribute keep_hierarchy of lmb_bram_elaborate : entity is "yes"; end lmb_bram_elaborate; architecture STRUCTURE of lmb_bram_elaborate is component RAMB16BWE is generic ( INIT_FILE : string; DATA_WIDTH_A : integer; DATA_WIDTH_B : integer ); port ( ADDRA : in std_logic_vector(13 downto 0); CLKA : in std_logic; DIA : in std_logic_vector(31 downto 0); DIPA : in std_logic_vector(3 downto 0); DOA : out std_logic_vector(31 downto 0); DOPA : out std_logic_vector(3 downto 0); ENA : in std_logic; SSRA : in std_logic; WEA : in std_logic_vector(3 downto 0); ADDRB : in std_logic_vector(13 downto 0); CLKB : in std_logic; DIB : in std_logic_vector(31 downto 0); DIPB : in std_logic_vector(3 downto 0); DOB : out std_logic_vector(31 downto 0); DOPB : out std_logic_vector(3 downto 0); ENB : in std_logic; SSRB : in std_logic; WEB : in std_logic_vector(3 downto 0) ); end component; attribute BMM_INFO : STRING; attribute BMM_INFO of ramb16bwe_0: label is " "; attribute BMM_INFO of ramb16bwe_1: label is " "; attribute BMM_INFO of ramb16bwe_2: label is " "; attribute BMM_INFO of ramb16bwe_3: label is " "; attribute BMM_INFO of ramb16bwe_4: label is " "; attribute BMM_INFO of ramb16bwe_5: label is " "; attribute BMM_INFO of ramb16bwe_6: label is " "; attribute BMM_INFO of ramb16bwe_7: label is " "; attribute BMM_INFO of ramb16bwe_8: label is " "; attribute BMM_INFO of ramb16bwe_9: label is " "; attribute BMM_INFO of ramb16bwe_10: label is " "; attribute BMM_INFO of ramb16bwe_11: label is " "; attribute BMM_INFO of ramb16bwe_12: label is " "; attribute BMM_INFO of ramb16bwe_13: label is " "; attribute BMM_INFO of ramb16bwe_14: label is " "; attribute BMM_INFO of ramb16bwe_15: label is " "; -- Internal signals signal net_gnd4 : std_logic_vector(3 downto 0); signal pgassign1 : std_logic_vector(0 to 0); signal pgassign2 : std_logic_vector(0 to 29); signal pgassign3 : std_logic_vector(13 downto 0); signal pgassign4 : std_logic_vector(31 downto 0); signal pgassign5 : std_logic_vector(31 downto 0); signal pgassign6 : std_logic_vector(3 downto 0); signal pgassign7 : std_logic_vector(13 downto 0); signal pgassign8 : std_logic_vector(31 downto 0); signal pgassign9 : std_logic_vector(31 downto 0); signal pgassign10 : std_logic_vector(3 downto 0); signal pgassign11 : std_logic_vector(13 downto 0); signal pgassign12 : std_logic_vector(31 downto 0); signal pgassign13 : std_logic_vector(31 downto 0); signal pgassign14 : std_logic_vector(3 downto 0); signal pgassign15 : std_logic_vector(13 downto 0); signal pgassign16 : std_logic_vector(31 downto 0); signal pgassign17 : std_logic_vector(31 downto 0); signal pgassign18 : std_logic_vector(3 downto 0); signal pgassign19 : std_logic_vector(13 downto 0); signal pgassign20 : std_logic_vector(31 downto 0); signal pgassign21 : std_logic_vector(31 downto 0); signal pgassign22 : std_logic_vector(3 downto 0); signal pgassign23 : std_logic_vector(13 downto 0); signal pgassign24 : std_logic_vector(31 downto 0); signal pgassign25 : std_logic_vector(31 downto 0); signal pgassign26 : std_logic_vector(3 downto 0); signal pgassign27 : std_logic_vector(13 downto 0); signal pgassign28 : std_logic_vector(31 downto 0); signal pgassign29 : std_logic_vector(31 downto 0); signal pgassign30 : std_logic_vector(3 downto 0); signal pgassign31 : std_logic_vector(13 downto 0); signal pgassign32 : std_logic_vector(31 downto 0); signal pgassign33 : std_logic_vector(31 downto 0); signal pgassign34 : std_logic_vector(3 downto 0); signal pgassign35 : std_logic_vector(13 downto 0); signal pgassign36 : std_logic_vector(31 downto 0); signal pgassign37 : std_logic_vector(31 downto 0); signal pgassign38 : std_logic_vector(3 downto 0); signal pgassign39 : std_logic_vector(13 downto 0); signal pgassign40 : std_logic_vector(31 downto 0); signal pgassign41 : std_logic_vector(31 downto 0); signal pgassign42 : std_logic_vector(3 downto 0); signal pgassign43 : std_logic_vector(13 downto 0); signal pgassign44 : std_logic_vector(31 downto 0); signal pgassign45 : std_logic_vector(31 downto 0); signal pgassign46 : std_logic_vector(3 downto 0); signal pgassign47 : std_logic_vector(13 downto 0); signal pgassign48 : std_logic_vector(31 downto 0); signal pgassign49 : std_logic_vector(31 downto 0); signal pgassign50 : std_logic_vector(3 downto 0); signal pgassign51 : std_logic_vector(13 downto 0); signal pgassign52 : std_logic_vector(31 downto 0); signal pgassign53 : std_logic_vector(31 downto 0); signal pgassign54 : std_logic_vector(3 downto 0); signal pgassign55 : std_logic_vector(13 downto 0); signal pgassign56 : std_logic_vector(31 downto 0); signal pgassign57 : std_logic_vector(31 downto 0); signal pgassign58 : std_logic_vector(3 downto 0); signal pgassign59 : std_logic_vector(13 downto 0); signal pgassign60 : std_logic_vector(31 downto 0); signal pgassign61 : std_logic_vector(31 downto 0); signal pgassign62 : std_logic_vector(3 downto 0); signal pgassign63 : std_logic_vector(13 downto 0); signal pgassign64 : std_logic_vector(31 downto 0); signal pgassign65 : std_logic_vector(31 downto 0); signal pgassign66 : std_logic_vector(3 downto 0); signal pgassign67 : std_logic_vector(13 downto 0); signal pgassign68 : std_logic_vector(31 downto 0); signal pgassign69 : std_logic_vector(31 downto 0); signal pgassign70 : std_logic_vector(3 downto 0); signal pgassign71 : std_logic_vector(13 downto 0); signal pgassign72 : std_logic_vector(31 downto 0); signal pgassign73 : std_logic_vector(31 downto 0); signal pgassign74 : std_logic_vector(3 downto 0); signal pgassign75 : std_logic_vector(13 downto 0); signal pgassign76 : std_logic_vector(31 downto 0); signal pgassign77 : std_logic_vector(31 downto 0); signal pgassign78 : std_logic_vector(3 downto 0); signal pgassign79 : std_logic_vector(13 downto 0); signal pgassign80 : std_logic_vector(31 downto 0); signal pgassign81 : std_logic_vector(31 downto 0); signal pgassign82 : std_logic_vector(3 downto 0); signal pgassign83 : std_logic_vector(13 downto 0); signal pgassign84 : std_logic_vector(31 downto 0); signal pgassign85 : std_logic_vector(31 downto 0); signal pgassign86 : std_logic_vector(3 downto 0); signal pgassign87 : std_logic_vector(13 downto 0); signal pgassign88 : std_logic_vector(31 downto 0); signal pgassign89 : std_logic_vector(31 downto 0); signal pgassign90 : std_logic_vector(3 downto 0); signal pgassign91 : std_logic_vector(13 downto 0); signal pgassign92 : std_logic_vector(31 downto 0); signal pgassign93 : std_logic_vector(31 downto 0); signal pgassign94 : std_logic_vector(3 downto 0); signal pgassign95 : std_logic_vector(13 downto 0); signal pgassign96 : std_logic_vector(31 downto 0); signal pgassign97 : std_logic_vector(31 downto 0); signal pgassign98 : std_logic_vector(3 downto 0); signal pgassign99 : std_logic_vector(13 downto 0); signal pgassign100 : std_logic_vector(31 downto 0); signal pgassign101 : std_logic_vector(31 downto 0); signal pgassign102 : std_logic_vector(3 downto 0); signal pgassign103 : std_logic_vector(13 downto 0); signal pgassign104 : std_logic_vector(31 downto 0); signal pgassign105 : std_logic_vector(31 downto 0); signal pgassign106 : std_logic_vector(3 downto 0); signal pgassign107 : std_logic_vector(13 downto 0); signal pgassign108 : std_logic_vector(31 downto 0); signal pgassign109 : std_logic_vector(31 downto 0); signal pgassign110 : std_logic_vector(3 downto 0); signal pgassign111 : std_logic_vector(13 downto 0); signal pgassign112 : std_logic_vector(31 downto 0); signal pgassign113 : std_logic_vector(31 downto 0); signal pgassign114 : std_logic_vector(3 downto 0); signal pgassign115 : std_logic_vector(13 downto 0); signal pgassign116 : std_logic_vector(31 downto 0); signal pgassign117 : std_logic_vector(31 downto 0); signal pgassign118 : std_logic_vector(3 downto 0); signal pgassign119 : std_logic_vector(13 downto 0); signal pgassign120 : std_logic_vector(31 downto 0); signal pgassign121 : std_logic_vector(31 downto 0); signal pgassign122 : std_logic_vector(3 downto 0); signal pgassign123 : std_logic_vector(13 downto 0); signal pgassign124 : std_logic_vector(31 downto 0); signal pgassign125 : std_logic_vector(31 downto 0); signal pgassign126 : std_logic_vector(3 downto 0); signal pgassign127 : std_logic_vector(13 downto 0); signal pgassign128 : std_logic_vector(31 downto 0); signal pgassign129 : std_logic_vector(31 downto 0); signal pgassign130 : std_logic_vector(3 downto 0); begin -- Internal assignments pgassign1(0 to 0) <= B"0"; pgassign2(0 to 29) <= B"000000000000000000000000000000"; pgassign3(13 downto 1) <= BRAM_Addr_A(17 to 29); pgassign3(0 downto 0) <= B"0"; pgassign4(31 downto 2) <= B"000000000000000000000000000000"; pgassign4(1 downto 0) <= BRAM_Dout_A(0 to 1); BRAM_Din_A(0 to 1) <= pgassign5(1 downto 0); pgassign6(3 downto 3) <= BRAM_WEN_A(0 to 0); pgassign6(2 downto 2) <= BRAM_WEN_A(0 to 0); pgassign6(1 downto 1) <= BRAM_WEN_A(0 to 0); pgassign6(0 downto 0) <= BRAM_WEN_A(0 to 0); pgassign7(13 downto 1) <= BRAM_Addr_B(17 to 29); pgassign7(0 downto 0) <= B"0"; pgassign8(31 downto 2) <= B"000000000000000000000000000000"; pgassign8(1 downto 0) <= BRAM_Dout_B(0 to 1); BRAM_Din_B(0 to 1) <= pgassign9(1 downto 0); pgassign10(3 downto 3) <= BRAM_WEN_B(0 to 0); pgassign10(2 downto 2) <= BRAM_WEN_B(0 to 0); pgassign10(1 downto 1) <= BRAM_WEN_B(0 to 0); pgassign10(0 downto 0) <= BRAM_WEN_B(0 to 0); pgassign11(13 downto 1) <= BRAM_Addr_A(17 to 29); pgassign11(0 downto 0) <= B"0"; pgassign12(31 downto 2) <= B"000000000000000000000000000000"; pgassign12(1 downto 0) <= BRAM_Dout_A(2 to 3); BRAM_Din_A(2 to 3) <= pgassign13(1 downto 0); pgassign14(3 downto 3) <= BRAM_WEN_A(0 to 0); pgassign14(2 downto 2) <= BRAM_WEN_A(0 to 0); pgassign14(1 downto 1) <= BRAM_WEN_A(0 to 0); pgassign14(0 downto 0) <= BRAM_WEN_A(0 to 0); pgassign15(13 downto 1) <= BRAM_Addr_B(17 to 29); pgassign15(0 downto 0) <= B"0"; pgassign16(31 downto 2) <= B"000000000000000000000000000000"; pgassign16(1 downto 0) <= BRAM_Dout_B(2 to 3); BRAM_Din_B(2 to 3) <= pgassign17(1 downto 0); pgassign18(3 downto 3) <= BRAM_WEN_B(0 to 0); pgassign18(2 downto 2) <= BRAM_WEN_B(0 to 0); pgassign18(1 downto 1) <= BRAM_WEN_B(0 to 0); pgassign18(0 downto 0) <= BRAM_WEN_B(0 to 0); pgassign19(13 downto 1) <= BRAM_Addr_A(17 to 29); pgassign19(0 downto 0) <= B"0"; pgassign20(31 downto 2) <= B"000000000000000000000000000000"; pgassign20(1 downto 0) <= BRAM_Dout_A(4 to 5); BRAM_Din_A(4 to 5) <= pgassign21(1 downto 0); pgassign22(3 downto 3) <= BRAM_WEN_A(0 to 0); pgassign22(2 downto 2) <= BRAM_WEN_A(0 to 0); pgassign22(1 downto 1) <= BRAM_WEN_A(0 to 0); pgassign22(0 downto 0) <= BRAM_WEN_A(0 to 0); pgassign23(13 downto 1) <= BRAM_Addr_B(17 to 29); pgassign23(0 downto 0) <= B"0"; pgassign24(31 downto 2) <= B"000000000000000000000000000000"; pgassign24(1 downto 0) <= BRAM_Dout_B(4 to 5); BRAM_Din_B(4 to 5) <= pgassign25(1 downto 0); pgassign26(3 downto 3) <= BRAM_WEN_B(0 to 0); pgassign26(2 downto 2) <= BRAM_WEN_B(0 to 0); pgassign26(1 downto 1) <= BRAM_WEN_B(0 to 0); pgassign26(0 downto 0) <= BRAM_WEN_B(0 to 0); pgassign27(13 downto 1) <= BRAM_Addr_A(17 to 29); pgassign27(0 downto 0) <= B"0"; pgassign28(31 downto 2) <= B"000000000000000000000000000000"; pgassign28(1 downto 0) <= BRAM_Dout_A(6 to 7); BRAM_Din_A(6 to 7) <= pgassign29(1 downto 0); pgassign30(3 downto 3) <= BRAM_WEN_A(0 to 0); pgassign30(2 downto 2) <= BRAM_WEN_A(0 to 0); pgassign30(1 downto 1) <= BRAM_WEN_A(0 to 0); pgassign30(0 downto 0) <= BRAM_WEN_A(0 to 0); pgassign31(13 downto 1) <= BRAM_Addr_B(17 to 29); pgassign31(0 downto 0) <= B"0"; pgassign32(31 downto 2) <= B"000000000000000000000000000000"; pgassign32(1 downto 0) <= BRAM_Dout_B(6 to 7); BRAM_Din_B(6 to 7) <= pgassign33(1 downto 0); pgassign34(3 downto 3) <= BRAM_WEN_B(0 to 0); pgassign34(2 downto 2) <= BRAM_WEN_B(0 to 0); pgassign34(1 downto 1) <= BRAM_WEN_B(0 to 0); pgassign34(0 downto 0) <= BRAM_WEN_B(0 to 0); pgassign35(13 downto 1) <= BRAM_Addr_A(17 to 29); pgassign35(0 downto 0) <= B"0"; pgassign36(31 downto 2) <= B"000000000000000000000000000000"; pgassign36(1 downto 0) <= BRAM_Dout_A(8 to 9); BRAM_Din_A(8 to 9) <= pgassign37(1 downto 0); pgassign38(3 downto 3) <= BRAM_WEN_A(1 to 1); pgassign38(2 downto 2) <= BRAM_WEN_A(1 to 1); pgassign38(1 downto 1) <= BRAM_WEN_A(1 to 1); pgassign38(0 downto 0) <= BRAM_WEN_A(1 to 1); pgassign39(13 downto 1) <= BRAM_Addr_B(17 to 29); pgassign39(0 downto 0) <= B"0"; pgassign40(31 downto 2) <= B"000000000000000000000000000000"; pgassign40(1 downto 0) <= BRAM_Dout_B(8 to 9); BRAM_Din_B(8 to 9) <= pgassign41(1 downto 0); pgassign42(3 downto 3) <= BRAM_WEN_B(1 to 1); pgassign42(2 downto 2) <= BRAM_WEN_B(1 to 1); pgassign42(1 downto 1) <= BRAM_WEN_B(1 to 1); pgassign42(0 downto 0) <= BRAM_WEN_B(1 to 1); pgassign43(13 downto 1) <= BRAM_Addr_A(17 to 29); pgassign43(0 downto 0) <= B"0"; pgassign44(31 downto 2) <= B"000000000000000000000000000000"; pgassign44(1 downto 0) <= BRAM_Dout_A(10 to 11); BRAM_Din_A(10 to 11) <= pgassign45(1 downto 0); pgassign46(3 downto 3) <= BRAM_WEN_A(1 to 1); pgassign46(2 downto 2) <= BRAM_WEN_A(1 to 1); pgassign46(1 downto 1) <= BRAM_WEN_A(1 to 1); pgassign46(0 downto 0) <= BRAM_WEN_A(1 to 1); pgassign47(13 downto 1) <= BRAM_Addr_B(17 to 29); pgassign47(0 downto 0) <= B"0"; pgassign48(31 downto 2) <= B"000000000000000000000000000000"; pgassign48(1 downto 0) <= BRAM_Dout_B(10 to 11); BRAM_Din_B(10 to 11) <= pgassign49(1 downto 0); pgassign50(3 downto 3) <= BRAM_WEN_B(1 to 1); pgassign50(2 downto 2) <= BRAM_WEN_B(1 to 1); pgassign50(1 downto 1) <= BRAM_WEN_B(1 to 1); pgassign50(0 downto 0) <= BRAM_WEN_B(1 to 1); pgassign51(13 downto 1) <= BRAM_Addr_A(17 to 29); pgassign51(0 downto 0) <= B"0"; pgassign52(31 downto 2) <= B"000000000000000000000000000000"; pgassign52(1 downto 0) <= BRAM_Dout_A(12 to 13); BRAM_Din_A(12 to 13) <= pgassign53(1 downto 0); pgassign54(3 downto 3) <= BRAM_WEN_A(1 to 1); pgassign54(2 downto 2) <= BRAM_WEN_A(1 to 1); pgassign54(1 downto 1) <= BRAM_WEN_A(1 to 1); pgassign54(0 downto 0) <= BRAM_WEN_A(1 to 1); pgassign55(13 downto 1) <= BRAM_Addr_B(17 to 29); pgassign55(0 downto 0) <= B"0"; pgassign56(31 downto 2) <= B"000000000000000000000000000000"; pgassign56(1 downto 0) <= BRAM_Dout_B(12 to 13); BRAM_Din_B(12 to 13) <= pgassign57(1 downto 0); pgassign58(3 downto 3) <= BRAM_WEN_B(1 to 1); pgassign58(2 downto 2) <= BRAM_WEN_B(1 to 1); pgassign58(1 downto 1) <= BRAM_WEN_B(1 to 1); pgassign58(0 downto 0) <= BRAM_WEN_B(1 to 1); pgassign59(13 downto 1) <= BRAM_Addr_A(17 to 29); pgassign59(0 downto 0) <= B"0"; pgassign60(31 downto 2) <= B"000000000000000000000000000000"; pgassign60(1 downto 0) <= BRAM_Dout_A(14 to 15); BRAM_Din_A(14 to 15) <= pgassign61(1 downto 0); pgassign62(3 downto 3) <= BRAM_WEN_A(1 to 1); pgassign62(2 downto 2) <= BRAM_WEN_A(1 to 1); pgassign62(1 downto 1) <= BRAM_WEN_A(1 to 1); pgassign62(0 downto 0) <= BRAM_WEN_A(1 to 1); pgassign63(13 downto 1) <= BRAM_Addr_B(17 to 29); pgassign63(0 downto 0) <= B"0"; pgassign64(31 downto 2) <= B"000000000000000000000000000000"; pgassign64(1 downto 0) <= BRAM_Dout_B(14 to 15); BRAM_Din_B(14 to 15) <= pgassign65(1 downto 0); pgassign66(3 downto 3) <= BRAM_WEN_B(1 to 1); pgassign66(2 downto 2) <= BRAM_WEN_B(1 to 1); pgassign66(1 downto 1) <= BRAM_WEN_B(1 to 1); pgassign66(0 downto 0) <= BRAM_WEN_B(1 to 1); pgassign67(13 downto 1) <= BRAM_Addr_A(17 to 29); pgassign67(0 downto 0) <= B"0"; pgassign68(31 downto 2) <= B"000000000000000000000000000000"; pgassign68(1 downto 0) <= BRAM_Dout_A(16 to 17); BRAM_Din_A(16 to 17) <= pgassign69(1 downto 0); pgassign70(3 downto 3) <= BRAM_WEN_A(2 to 2); pgassign70(2 downto 2) <= BRAM_WEN_A(2 to 2); pgassign70(1 downto 1) <= BRAM_WEN_A(2 to 2); pgassign70(0 downto 0) <= BRAM_WEN_A(2 to 2); pgassign71(13 downto 1) <= BRAM_Addr_B(17 to 29); pgassign71(0 downto 0) <= B"0"; pgassign72(31 downto 2) <= B"000000000000000000000000000000"; pgassign72(1 downto 0) <= BRAM_Dout_B(16 to 17); BRAM_Din_B(16 to 17) <= pgassign73(1 downto 0); pgassign74(3 downto 3) <= BRAM_WEN_B(2 to 2); pgassign74(2 downto 2) <= BRAM_WEN_B(2 to 2); pgassign74(1 downto 1) <= BRAM_WEN_B(2 to 2); pgassign74(0 downto 0) <= BRAM_WEN_B(2 to 2); pgassign75(13 downto 1) <= BRAM_Addr_A(17 to 29); pgassign75(0 downto 0) <= B"0"; pgassign76(31 downto 2) <= B"000000000000000000000000000000"; pgassign76(1 downto 0) <= BRAM_Dout_A(18 to 19); BRAM_Din_A(18 to 19) <= pgassign77(1 downto 0); pgassign78(3 downto 3) <= BRAM_WEN_A(2 to 2); pgassign78(2 downto 2) <= BRAM_WEN_A(2 to 2); pgassign78(1 downto 1) <= BRAM_WEN_A(2 to 2); pgassign78(0 downto 0) <= BRAM_WEN_A(2 to 2); pgassign79(13 downto 1) <= BRAM_Addr_B(17 to 29); pgassign79(0 downto 0) <= B"0"; pgassign80(31 downto 2) <= B"000000000000000000000000000000"; pgassign80(1 downto 0) <= BRAM_Dout_B(18 to 19); BRAM_Din_B(18 to 19) <= pgassign81(1 downto 0); pgassign82(3 downto 3) <= BRAM_WEN_B(2 to 2); pgassign82(2 downto 2) <= BRAM_WEN_B(2 to 2); pgassign82(1 downto 1) <= BRAM_WEN_B(2 to 2); pgassign82(0 downto 0) <= BRAM_WEN_B(2 to 2); pgassign83(13 downto 1) <= BRAM_Addr_A(17 to 29); pgassign83(0 downto 0) <= B"0"; pgassign84(31 downto 2) <= B"000000000000000000000000000000"; pgassign84(1 downto 0) <= BRAM_Dout_A(20 to 21); BRAM_Din_A(20 to 21) <= pgassign85(1 downto 0); pgassign86(3 downto 3) <= BRAM_WEN_A(2 to 2); pgassign86(2 downto 2) <= BRAM_WEN_A(2 to 2); pgassign86(1 downto 1) <= BRAM_WEN_A(2 to 2); pgassign86(0 downto 0) <= BRAM_WEN_A(2 to 2); pgassign87(13 downto 1) <= BRAM_Addr_B(17 to 29); pgassign87(0 downto 0) <= B"0"; pgassign88(31 downto 2) <= B"000000000000000000000000000000"; pgassign88(1 downto 0) <= BRAM_Dout_B(20 to 21); BRAM_Din_B(20 to 21) <= pgassign89(1 downto 0); pgassign90(3 downto 3) <= BRAM_WEN_B(2 to 2); pgassign90(2 downto 2) <= BRAM_WEN_B(2 to 2); pgassign90(1 downto 1) <= BRAM_WEN_B(2 to 2); pgassign90(0 downto 0) <= BRAM_WEN_B(2 to 2); pgassign91(13 downto 1) <= BRAM_Addr_A(17 to 29); pgassign91(0 downto 0) <= B"0"; pgassign92(31 downto 2) <= B"000000000000000000000000000000"; pgassign92(1 downto 0) <= BRAM_Dout_A(22 to 23); BRAM_Din_A(22 to 23) <= pgassign93(1 downto 0); pgassign94(3 downto 3) <= BRAM_WEN_A(2 to 2); pgassign94(2 downto 2) <= BRAM_WEN_A(2 to 2); pgassign94(1 downto 1) <= BRAM_WEN_A(2 to 2); pgassign94(0 downto 0) <= BRAM_WEN_A(2 to 2); pgassign95(13 downto 1) <= BRAM_Addr_B(17 to 29); pgassign95(0 downto 0) <= B"0"; pgassign96(31 downto 2) <= B"000000000000000000000000000000"; pgassign96(1 downto 0) <= BRAM_Dout_B(22 to 23); BRAM_Din_B(22 to 23) <= pgassign97(1 downto 0); pgassign98(3 downto 3) <= BRAM_WEN_B(2 to 2); pgassign98(2 downto 2) <= BRAM_WEN_B(2 to 2); pgassign98(1 downto 1) <= BRAM_WEN_B(2 to 2); pgassign98(0 downto 0) <= BRAM_WEN_B(2 to 2); pgassign99(13 downto 1) <= BRAM_Addr_A(17 to 29); pgassign99(0 downto 0) <= B"0"; pgassign100(31 downto 2) <= B"000000000000000000000000000000"; pgassign100(1 downto 0) <= BRAM_Dout_A(24 to 25); BRAM_Din_A(24 to 25) <= pgassign101(1 downto 0); pgassign102(3 downto 3) <= BRAM_WEN_A(3 to 3); pgassign102(2 downto 2) <= BRAM_WEN_A(3 to 3); pgassign102(1 downto 1) <= BRAM_WEN_A(3 to 3); pgassign102(0 downto 0) <= BRAM_WEN_A(3 to 3); pgassign103(13 downto 1) <= BRAM_Addr_B(17 to 29); pgassign103(0 downto 0) <= B"0"; pgassign104(31 downto 2) <= B"000000000000000000000000000000"; pgassign104(1 downto 0) <= BRAM_Dout_B(24 to 25); BRAM_Din_B(24 to 25) <= pgassign105(1 downto 0); pgassign106(3 downto 3) <= BRAM_WEN_B(3 to 3); pgassign106(2 downto 2) <= BRAM_WEN_B(3 to 3); pgassign106(1 downto 1) <= BRAM_WEN_B(3 to 3); pgassign106(0 downto 0) <= BRAM_WEN_B(3 to 3); pgassign107(13 downto 1) <= BRAM_Addr_A(17 to 29); pgassign107(0 downto 0) <= B"0"; pgassign108(31 downto 2) <= B"000000000000000000000000000000"; pgassign108(1 downto 0) <= BRAM_Dout_A(26 to 27); BRAM_Din_A(26 to 27) <= pgassign109(1 downto 0); pgassign110(3 downto 3) <= BRAM_WEN_A(3 to 3); pgassign110(2 downto 2) <= BRAM_WEN_A(3 to 3); pgassign110(1 downto 1) <= BRAM_WEN_A(3 to 3); pgassign110(0 downto 0) <= BRAM_WEN_A(3 to 3); pgassign111(13 downto 1) <= BRAM_Addr_B(17 to 29); pgassign111(0 downto 0) <= B"0"; pgassign112(31 downto 2) <= B"000000000000000000000000000000"; pgassign112(1 downto 0) <= BRAM_Dout_B(26 to 27); BRAM_Din_B(26 to 27) <= pgassign113(1 downto 0); pgassign114(3 downto 3) <= BRAM_WEN_B(3 to 3); pgassign114(2 downto 2) <= BRAM_WEN_B(3 to 3); pgassign114(1 downto 1) <= BRAM_WEN_B(3 to 3); pgassign114(0 downto 0) <= BRAM_WEN_B(3 to 3); pgassign115(13 downto 1) <= BRAM_Addr_A(17 to 29); pgassign115(0 downto 0) <= B"0"; pgassign116(31 downto 2) <= B"000000000000000000000000000000"; pgassign116(1 downto 0) <= BRAM_Dout_A(28 to 29); BRAM_Din_A(28 to 29) <= pgassign117(1 downto 0); pgassign118(3 downto 3) <= BRAM_WEN_A(3 to 3); pgassign118(2 downto 2) <= BRAM_WEN_A(3 to 3); pgassign118(1 downto 1) <= BRAM_WEN_A(3 to 3); pgassign118(0 downto 0) <= BRAM_WEN_A(3 to 3); pgassign119(13 downto 1) <= BRAM_Addr_B(17 to 29); pgassign119(0 downto 0) <= B"0"; pgassign120(31 downto 2) <= B"000000000000000000000000000000"; pgassign120(1 downto 0) <= BRAM_Dout_B(28 to 29); BRAM_Din_B(28 to 29) <= pgassign121(1 downto 0); pgassign122(3 downto 3) <= BRAM_WEN_B(3 to 3); pgassign122(2 downto 2) <= BRAM_WEN_B(3 to 3); pgassign122(1 downto 1) <= BRAM_WEN_B(3 to 3); pgassign122(0 downto 0) <= BRAM_WEN_B(3 to 3); pgassign123(13 downto 1) <= BRAM_Addr_A(17 to 29); pgassign123(0 downto 0) <= B"0"; pgassign124(31 downto 2) <= B"000000000000000000000000000000"; pgassign124(1 downto 0) <= BRAM_Dout_A(30 to 31); BRAM_Din_A(30 to 31) <= pgassign125(1 downto 0); pgassign126(3 downto 3) <= BRAM_WEN_A(3 to 3); pgassign126(2 downto 2) <= BRAM_WEN_A(3 to 3); pgassign126(1 downto 1) <= BRAM_WEN_A(3 to 3); pgassign126(0 downto 0) <= BRAM_WEN_A(3 to 3); pgassign127(13 downto 1) <= BRAM_Addr_B(17 to 29); pgassign127(0 downto 0) <= B"0"; pgassign128(31 downto 2) <= B"000000000000000000000000000000"; pgassign128(1 downto 0) <= BRAM_Dout_B(30 to 31); BRAM_Din_B(30 to 31) <= pgassign129(1 downto 0); pgassign130(3 downto 3) <= BRAM_WEN_B(3 to 3); pgassign130(2 downto 2) <= BRAM_WEN_B(3 to 3); pgassign130(1 downto 1) <= BRAM_WEN_B(3 to 3); pgassign130(0 downto 0) <= BRAM_WEN_B(3 to 3); net_gnd4(3 downto 0) <= B"0000"; ramb16bwe_0 : RAMB16BWE generic map ( INIT_FILE => "lmb_bram_combined_0.mem", DATA_WIDTH_A => 2, DATA_WIDTH_B => 2 ) port map ( ADDRA => pgassign3, CLKA => BRAM_Clk_A, DIA => pgassign4, DIPA => net_gnd4, DOA => pgassign5, DOPA => open, ENA => BRAM_EN_A, SSRA => BRAM_Rst_A, WEA => pgassign6, ADDRB => pgassign7, CLKB => BRAM_Clk_B, DIB => pgassign8, DIPB => net_gnd4, DOB => pgassign9, DOPB => open, ENB => BRAM_EN_B, SSRB => BRAM_Rst_B, WEB => pgassign10 ); ramb16bwe_1 : RAMB16BWE generic map ( INIT_FILE => "lmb_bram_combined_1.mem", DATA_WIDTH_A => 2, DATA_WIDTH_B => 2 ) port map ( ADDRA => pgassign11, CLKA => BRAM_Clk_A, DIA => pgassign12, DIPA => net_gnd4, DOA => pgassign13, DOPA => open, ENA => BRAM_EN_A, SSRA => BRAM_Rst_A, WEA => pgassign14, ADDRB => pgassign15, CLKB => BRAM_Clk_B, DIB => pgassign16, DIPB => net_gnd4, DOB => pgassign17, DOPB => open, ENB => BRAM_EN_B, SSRB => BRAM_Rst_B, WEB => pgassign18 ); ramb16bwe_2 : RAMB16BWE generic map ( INIT_FILE => "lmb_bram_combined_2.mem", DATA_WIDTH_A => 2, DATA_WIDTH_B => 2 ) port map ( ADDRA => pgassign19, CLKA => BRAM_Clk_A, DIA => pgassign20, DIPA => net_gnd4, DOA => pgassign21, DOPA => open, ENA => BRAM_EN_A, SSRA => BRAM_Rst_A, WEA => pgassign22, ADDRB => pgassign23, CLKB => BRAM_Clk_B, DIB => pgassign24, DIPB => net_gnd4, DOB => pgassign25, DOPB => open, ENB => BRAM_EN_B, SSRB => BRAM_Rst_B, WEB => pgassign26 ); ramb16bwe_3 : RAMB16BWE generic map ( INIT_FILE => "lmb_bram_combined_3.mem", DATA_WIDTH_A => 2, DATA_WIDTH_B => 2 ) port map ( ADDRA => pgassign27, CLKA => BRAM_Clk_A, DIA => pgassign28, DIPA => net_gnd4, DOA => pgassign29, DOPA => open, ENA => BRAM_EN_A, SSRA => BRAM_Rst_A, WEA => pgassign30, ADDRB => pgassign31, CLKB => BRAM_Clk_B, DIB => pgassign32, DIPB => net_gnd4, DOB => pgassign33, DOPB => open, ENB => BRAM_EN_B, SSRB => BRAM_Rst_B, WEB => pgassign34 ); ramb16bwe_4 : RAMB16BWE generic map ( INIT_FILE => "lmb_bram_combined_4.mem", DATA_WIDTH_A => 2, DATA_WIDTH_B => 2 ) port map ( ADDRA => pgassign35, CLKA => BRAM_Clk_A, DIA => pgassign36, DIPA => net_gnd4, DOA => pgassign37, DOPA => open, ENA => BRAM_EN_A, SSRA => BRAM_Rst_A, WEA => pgassign38, ADDRB => pgassign39, CLKB => BRAM_Clk_B, DIB => pgassign40, DIPB => net_gnd4, DOB => pgassign41, DOPB => open, ENB => BRAM_EN_B, SSRB => BRAM_Rst_B, WEB => pgassign42 ); ramb16bwe_5 : RAMB16BWE generic map ( INIT_FILE => "lmb_bram_combined_5.mem", DATA_WIDTH_A => 2, DATA_WIDTH_B => 2 ) port map ( ADDRA => pgassign43, CLKA => BRAM_Clk_A, DIA => pgassign44, DIPA => net_gnd4, DOA => pgassign45, DOPA => open, ENA => BRAM_EN_A, SSRA => BRAM_Rst_A, WEA => pgassign46, ADDRB => pgassign47, CLKB => BRAM_Clk_B, DIB => pgassign48, DIPB => net_gnd4, DOB => pgassign49, DOPB => open, ENB => BRAM_EN_B, SSRB => BRAM_Rst_B, WEB => pgassign50 ); ramb16bwe_6 : RAMB16BWE generic map ( INIT_FILE => "lmb_bram_combined_6.mem", DATA_WIDTH_A => 2, DATA_WIDTH_B => 2 ) port map ( ADDRA => pgassign51, CLKA => BRAM_Clk_A, DIA => pgassign52, DIPA => net_gnd4, DOA => pgassign53, DOPA => open, ENA => BRAM_EN_A, SSRA => BRAM_Rst_A, WEA => pgassign54, ADDRB => pgassign55, CLKB => BRAM_Clk_B, DIB => pgassign56, DIPB => net_gnd4, DOB => pgassign57, DOPB => open, ENB => BRAM_EN_B, SSRB => BRAM_Rst_B, WEB => pgassign58 ); ramb16bwe_7 : RAMB16BWE generic map ( INIT_FILE => "lmb_bram_combined_7.mem", DATA_WIDTH_A => 2, DATA_WIDTH_B => 2 ) port map ( ADDRA => pgassign59, CLKA => BRAM_Clk_A, DIA => pgassign60, DIPA => net_gnd4, DOA => pgassign61, DOPA => open, ENA => BRAM_EN_A, SSRA => BRAM_Rst_A, WEA => pgassign62, ADDRB => pgassign63, CLKB => BRAM_Clk_B, DIB => pgassign64, DIPB => net_gnd4, DOB => pgassign65, DOPB => open, ENB => BRAM_EN_B, SSRB => BRAM_Rst_B, WEB => pgassign66 ); ramb16bwe_8 : RAMB16BWE generic map ( INIT_FILE => "lmb_bram_combined_8.mem", DATA_WIDTH_A => 2, DATA_WIDTH_B => 2 ) port map ( ADDRA => pgassign67, CLKA => BRAM_Clk_A, DIA => pgassign68, DIPA => net_gnd4, DOA => pgassign69, DOPA => open, ENA => BRAM_EN_A, SSRA => BRAM_Rst_A, WEA => pgassign70, ADDRB => pgassign71, CLKB => BRAM_Clk_B, DIB => pgassign72, DIPB => net_gnd4, DOB => pgassign73, DOPB => open, ENB => BRAM_EN_B, SSRB => BRAM_Rst_B, WEB => pgassign74 ); ramb16bwe_9 : RAMB16BWE generic map ( INIT_FILE => "lmb_bram_combined_9.mem", DATA_WIDTH_A => 2, DATA_WIDTH_B => 2 ) port map ( ADDRA => pgassign75, CLKA => BRAM_Clk_A, DIA => pgassign76, DIPA => net_gnd4, DOA => pgassign77, DOPA => open, ENA => BRAM_EN_A, SSRA => BRAM_Rst_A, WEA => pgassign78, ADDRB => pgassign79, CLKB => BRAM_Clk_B, DIB => pgassign80, DIPB => net_gnd4, DOB => pgassign81, DOPB => open, ENB => BRAM_EN_B, SSRB => BRAM_Rst_B, WEB => pgassign82 ); ramb16bwe_10 : RAMB16BWE generic map ( INIT_FILE => "lmb_bram_combined_10.mem", DATA_WIDTH_A => 2, DATA_WIDTH_B => 2 ) port map ( ADDRA => pgassign83, CLKA => BRAM_Clk_A, DIA => pgassign84, DIPA => net_gnd4, DOA => pgassign85, DOPA => open, ENA => BRAM_EN_A, SSRA => BRAM_Rst_A, WEA => pgassign86, ADDRB => pgassign87, CLKB => BRAM_Clk_B, DIB => pgassign88, DIPB => net_gnd4, DOB => pgassign89, DOPB => open, ENB => BRAM_EN_B, SSRB => BRAM_Rst_B, WEB => pgassign90 ); ramb16bwe_11 : RAMB16BWE generic map ( INIT_FILE => "lmb_bram_combined_11.mem", DATA_WIDTH_A => 2, DATA_WIDTH_B => 2 ) port map ( ADDRA => pgassign91, CLKA => BRAM_Clk_A, DIA => pgassign92, DIPA => net_gnd4, DOA => pgassign93, DOPA => open, ENA => BRAM_EN_A, SSRA => BRAM_Rst_A, WEA => pgassign94, ADDRB => pgassign95, CLKB => BRAM_Clk_B, DIB => pgassign96, DIPB => net_gnd4, DOB => pgassign97, DOPB => open, ENB => BRAM_EN_B, SSRB => BRAM_Rst_B, WEB => pgassign98 ); ramb16bwe_12 : RAMB16BWE generic map ( INIT_FILE => "lmb_bram_combined_12.mem", DATA_WIDTH_A => 2, DATA_WIDTH_B => 2 ) port map ( ADDRA => pgassign99, CLKA => BRAM_Clk_A, DIA => pgassign100, DIPA => net_gnd4, DOA => pgassign101, DOPA => open, ENA => BRAM_EN_A, SSRA => BRAM_Rst_A, WEA => pgassign102, ADDRB => pgassign103, CLKB => BRAM_Clk_B, DIB => pgassign104, DIPB => net_gnd4, DOB => pgassign105, DOPB => open, ENB => BRAM_EN_B, SSRB => BRAM_Rst_B, WEB => pgassign106 ); ramb16bwe_13 : RAMB16BWE generic map ( INIT_FILE => "lmb_bram_combined_13.mem", DATA_WIDTH_A => 2, DATA_WIDTH_B => 2 ) port map ( ADDRA => pgassign107, CLKA => BRAM_Clk_A, DIA => pgassign108, DIPA => net_gnd4, DOA => pgassign109, DOPA => open, ENA => BRAM_EN_A, SSRA => BRAM_Rst_A, WEA => pgassign110, ADDRB => pgassign111, CLKB => BRAM_Clk_B, DIB => pgassign112, DIPB => net_gnd4, DOB => pgassign113, DOPB => open, ENB => BRAM_EN_B, SSRB => BRAM_Rst_B, WEB => pgassign114 ); ramb16bwe_14 : RAMB16BWE generic map ( INIT_FILE => "lmb_bram_combined_14.mem", DATA_WIDTH_A => 2, DATA_WIDTH_B => 2 ) port map ( ADDRA => pgassign115, CLKA => BRAM_Clk_A, DIA => pgassign116, DIPA => net_gnd4, DOA => pgassign117, DOPA => open, ENA => BRAM_EN_A, SSRA => BRAM_Rst_A, WEA => pgassign118, ADDRB => pgassign119, CLKB => BRAM_Clk_B, DIB => pgassign120, DIPB => net_gnd4, DOB => pgassign121, DOPB => open, ENB => BRAM_EN_B, SSRB => BRAM_Rst_B, WEB => pgassign122 ); ramb16bwe_15 : RAMB16BWE generic map ( INIT_FILE => "lmb_bram_combined_15.mem", DATA_WIDTH_A => 2, DATA_WIDTH_B => 2 ) port map ( ADDRA => pgassign123, CLKA => BRAM_Clk_A, DIA => pgassign124, DIPA => net_gnd4, DOA => pgassign125, DOPA => open, ENA => BRAM_EN_A, SSRA => BRAM_Rst_A, WEA => pgassign126, ADDRB => pgassign127, CLKB => BRAM_Clk_B, DIB => pgassign128, DIPB => net_gnd4, DOB => pgassign129, DOPB => open, ENB => BRAM_EN_B, SSRB => BRAM_Rst_B, WEB => pgassign130 ); end architecture STRUCTURE;
mit
cee9a36375dce056c3dcb4dc69fd2135
0.619339
3.118898
false
false
false
false
GSimas/EEL5105
Eletr-Digital/Projeto Final/PROJETO COFRE FUNCIONANDO/clock3hz.vhd
1
4,568
-- megafunction wizard: %LPM_COUNTER% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: lpm_counter -- ============================================================ -- File Name: clock3hz.vhd -- Megafunction Name(s): -- lpm_counter -- -- Simulation Library Files(s): -- lpm -- ============================================================ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- -- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition -- ************************************************************ --Copyright (C) 1991-2010 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject --to the terms and conditions of the Altera Program License --Subscription Agreement, Altera MegaCore Function License --Agreement, or other applicable license agreement, including, --without limitation, that your use is for the sole purpose of --programming logic devices manufactured by Altera and sold by --Altera or its authorized distributors. Please refer to the --applicable agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY lpm; USE lpm.all; ENTITY clock3hz IS PORT ( clock : IN STD_LOGIC ; cout : OUT STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (29 DOWNTO 0) ); END clock3hz; ARCHITECTURE SYN OF clock3hz IS SIGNAL sub_wire0 : STD_LOGIC ; SIGNAL sub_wire1 : STD_LOGIC_VECTOR (29 DOWNTO 0); COMPONENT lpm_counter GENERIC ( lpm_direction : STRING; lpm_modulus : NATURAL; lpm_port_updown : STRING; lpm_type : STRING; lpm_width : NATURAL ); PORT ( clock : IN STD_LOGIC ; cout : OUT STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (29 DOWNTO 0) ); END COMPONENT; BEGIN cout <= sub_wire0; q <= sub_wire1(29 DOWNTO 0); lpm_counter_component : lpm_counter GENERIC MAP ( lpm_direction => "UP", lpm_modulus => 8333333, lpm_port_updown => "PORT_UNUSED", lpm_type => "LPM_COUNTER", lpm_width => 30 ) PORT MAP ( clock => clock, cout => sub_wire0, q => sub_wire1 ); END SYN; -- ============================================================ -- CNX file retrieval info -- ============================================================ -- Retrieval info: PRIVATE: ACLR NUMERIC "0" -- Retrieval info: PRIVATE: ALOAD NUMERIC "0" -- Retrieval info: PRIVATE: ASET NUMERIC "0" -- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1" -- Retrieval info: PRIVATE: CLK_EN NUMERIC "0" -- Retrieval info: PRIVATE: CNT_EN NUMERIC "0" -- Retrieval info: PRIVATE: CarryIn NUMERIC "0" -- Retrieval info: PRIVATE: CarryOut NUMERIC "1" -- Retrieval info: PRIVATE: Direction NUMERIC "0" -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" -- Retrieval info: PRIVATE: ModulusCounter NUMERIC "1" -- Retrieval info: PRIVATE: ModulusValue NUMERIC "8333333" -- Retrieval info: PRIVATE: SCLR NUMERIC "0" -- Retrieval info: PRIVATE: SLOAD NUMERIC "0" -- Retrieval info: PRIVATE: SSET NUMERIC "0" -- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: nBit NUMERIC "30" -- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP" -- Retrieval info: CONSTANT: LPM_MODULUS NUMERIC "8333333" -- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER" -- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "30" -- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock -- Retrieval info: USED_PORT: cout 0 0 0 0 OUTPUT NODEFVAL cout -- Retrieval info: USED_PORT: q 0 0 30 0 OUTPUT NODEFVAL q[29..0] -- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 -- Retrieval info: CONNECT: q 0 0 30 0 @q 0 0 30 0 -- Retrieval info: CONNECT: cout 0 0 0 0 @cout 0 0 0 0 -- Retrieval info: LIBRARY: lpm lpm.lpm_components.all -- Retrieval info: GEN_FILE: TYPE_NORMAL clock3hz.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL clock3hz.inc TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL clock3hz.cmp TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL clock3hz.bsf TRUE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL clock3hz_inst.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL clock3hz_waveforms.html TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL clock3hz_wave*.jpg FALSE -- Retrieval info: LIB_FILE: lpm
mit
2fb519cb6540f7795e169d30365f7e43
0.656086
3.666132
false
false
false
false
tghaefli/ADD
EDK/IVK_Repos/IVK_IPLib/pcores/sg_i2c_controller_s6_plbw_v1_01_a/hdl/vhdl/sg_i2c_controller_s6_cw.vhd
1
27,462
------------------------------------------------------------------- -- System Generator version 12.1 VHDL source file. -- -- Copyright(C) 2010 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2010 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- ------------------------------------------------------------------- -- System Generator version 12.1 VHDL source file. -- -- Copyright(C) 2010 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2010 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; -- synopsys translate_off library unisim; use unisim.vcomponents.all; -- synopsys translate_on entity xlclockdriver is generic ( period: integer := 2; log_2_period: integer := 0; pipeline_regs: integer := 5; use_bufg: integer := 0 ); port ( sysclk: in std_logic; sysclr: in std_logic; sysce: in std_logic; clk: out std_logic; clr: out std_logic; ce: out std_logic; ce_logic: out std_logic ); end xlclockdriver; architecture behavior of xlclockdriver is component bufg port ( i: in std_logic; o: out std_logic ); end component; component synth_reg_w_init generic ( width: integer; init_index: integer; init_value: bit_vector; latency: integer ); port ( i: in std_logic_vector(width - 1 downto 0); ce: in std_logic; clr: in std_logic; clk: in std_logic; o: out std_logic_vector(width - 1 downto 0) ); end component; function size_of_uint(inp: integer; power_of_2: boolean) return integer is constant inp_vec: std_logic_vector(31 downto 0) := integer_to_std_logic_vector(inp,32, xlUnsigned); variable result: integer; begin result := 32; for i in 0 to 31 loop if inp_vec(i) = '1' then result := i; end if; end loop; if power_of_2 then return result; else return result+1; end if; end; function is_power_of_2(inp: std_logic_vector) return boolean is constant width: integer := inp'length; variable vec: std_logic_vector(width - 1 downto 0); variable single_bit_set: boolean; variable more_than_one_bit_set: boolean; variable result: boolean; begin vec := inp; single_bit_set := false; more_than_one_bit_set := false; -- synopsys translate_off if (is_XorU(vec)) then return false; end if; -- synopsys translate_on if width > 0 then for i in 0 to width - 1 loop if vec(i) = '1' then if single_bit_set then more_than_one_bit_set := true; end if; single_bit_set := true; end if; end loop; end if; if (single_bit_set and not(more_than_one_bit_set)) then result := true; else result := false; end if; return result; end; function ce_reg_init_val(index, period : integer) return integer is variable result: integer; begin result := 0; if ((index mod period) = 0) then result := 1; end if; return result; end; function remaining_pipe_regs(num_pipeline_regs, period : integer) return integer is variable factor, result: integer; begin factor := (num_pipeline_regs / period); result := num_pipeline_regs - (period * factor) + 1; return result; end; function sg_min(L, R: INTEGER) return INTEGER is begin if L < R then return L; else return R; end if; end; constant max_pipeline_regs : integer := 8; constant pipe_regs : integer := 5; constant num_pipeline_regs : integer := sg_min(pipeline_regs, max_pipeline_regs); constant rem_pipeline_regs : integer := remaining_pipe_regs(num_pipeline_regs,period); constant period_floor: integer := max(2, period); constant power_of_2_counter: boolean := is_power_of_2(integer_to_std_logic_vector(period_floor,32, xlUnsigned)); constant cnt_width: integer := size_of_uint(period_floor, power_of_2_counter); constant clk_for_ce_pulse_minus1: std_logic_vector(cnt_width - 1 downto 0) := integer_to_std_logic_vector((period_floor - 2),cnt_width, xlUnsigned); constant clk_for_ce_pulse_minus2: std_logic_vector(cnt_width - 1 downto 0) := integer_to_std_logic_vector(max(0,period - 3),cnt_width, xlUnsigned); constant clk_for_ce_pulse_minus_regs: std_logic_vector(cnt_width - 1 downto 0) := integer_to_std_logic_vector(max(0,period - rem_pipeline_regs),cnt_width, xlUnsigned); signal clk_num: unsigned(cnt_width - 1 downto 0) := (others => '0'); signal ce_vec : std_logic_vector(num_pipeline_regs downto 0); attribute MAX_FANOUT : string; attribute MAX_FANOUT of ce_vec:signal is "REDUCE"; signal ce_vec_logic : std_logic_vector(num_pipeline_regs downto 0); attribute MAX_FANOUT of ce_vec_logic:signal is "REDUCE"; signal internal_ce: std_logic_vector(0 downto 0); signal internal_ce_logic: std_logic_vector(0 downto 0); signal cnt_clr, cnt_clr_dly: std_logic_vector (0 downto 0); begin clk <= sysclk; clr <= sysclr; cntr_gen: process(sysclk) begin if sysclk'event and sysclk = '1' then if (sysce = '1') then if ((cnt_clr_dly(0) = '1') or (sysclr = '1')) then clk_num <= (others => '0'); else clk_num <= clk_num + 1; end if; end if; end if; end process; clr_gen: process(clk_num, sysclr) begin if power_of_2_counter then cnt_clr(0) <= sysclr; else if (unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus1 or sysclr = '1') then cnt_clr(0) <= '1'; else cnt_clr(0) <= '0'; end if; end if; end process; clr_reg: synth_reg_w_init generic map ( width => 1, init_index => 0, init_value => b"0000", latency => 1 ) port map ( i => cnt_clr, ce => sysce, clr => sysclr, clk => sysclk, o => cnt_clr_dly ); pipelined_ce : if period > 1 generate ce_gen: process(clk_num) begin if unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus_regs then ce_vec(num_pipeline_regs) <= '1'; else ce_vec(num_pipeline_regs) <= '0'; end if; end process; ce_pipeline: for index in num_pipeline_regs downto 1 generate ce_reg : synth_reg_w_init generic map ( width => 1, init_index => ce_reg_init_val(index, period), init_value => b"0000", latency => 1 ) port map ( i => ce_vec(index downto index), ce => sysce, clr => sysclr, clk => sysclk, o => ce_vec(index-1 downto index-1) ); end generate; internal_ce <= ce_vec(0 downto 0); end generate; pipelined_ce_logic: if period > 1 generate ce_gen_logic: process(clk_num) begin if unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus_regs then ce_vec_logic(num_pipeline_regs) <= '1'; else ce_vec_logic(num_pipeline_regs) <= '0'; end if; end process; ce_logic_pipeline: for index in num_pipeline_regs downto 1 generate ce_logic_reg : synth_reg_w_init generic map ( width => 1, init_index => ce_reg_init_val(index, period), init_value => b"0000", latency => 1 ) port map ( i => ce_vec_logic(index downto index), ce => sysce, clr => sysclr, clk => sysclk, o => ce_vec_logic(index-1 downto index-1) ); end generate; internal_ce_logic <= ce_vec_logic(0 downto 0); end generate; use_bufg_true: if period > 1 and use_bufg = 1 generate ce_bufg_inst: bufg port map ( i => internal_ce(0), o => ce ); ce_bufg_inst_logic: bufg port map ( i => internal_ce_logic(0), o => ce_logic ); end generate; use_bufg_false: if period > 1 and (use_bufg = 0) generate ce <= internal_ce(0); ce_logic <= internal_ce_logic(0); end generate; generate_system_clk: if period = 1 generate ce <= sysce; ce_logic <= sysce; end generate; end architecture behavior; ------------------------------------------------------------------- -- System Generator version 12.1 VHDL source file. -- -- Copyright(C) 2010 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2010 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; entity xland2 is port ( a : in std_logic; b : in std_logic; dout : out std_logic ); end xland2; architecture behavior of xland2 is begin dout <= a and b; end behavior; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity default_clock_driver is port ( sysce: in std_logic; sysce_clr: in std_logic; sysclk: in std_logic; ce_1: out std_logic; clk_1: out std_logic ); end default_clock_driver; architecture structural of default_clock_driver is attribute syn_noprune: boolean; attribute syn_noprune of structural : architecture is true; attribute optimize_primitives: boolean; attribute optimize_primitives of structural : architecture is false; attribute dont_touch: boolean; attribute dont_touch of structural : architecture is true; signal sysce_clr_x0: std_logic; signal sysce_x0: std_logic; signal sysclk_x0: std_logic; signal xlclockdriver_1_ce: std_logic; signal xlclockdriver_1_clk: std_logic; begin sysce_x0 <= sysce; sysce_clr_x0 <= sysce_clr; sysclk_x0 <= sysclk; ce_1 <= xlclockdriver_1_ce; clk_1 <= xlclockdriver_1_clk; xlclockdriver_1: entity work.xlclockdriver generic map ( log_2_period => 1, period => 1, use_bufg => 0 ) port map ( sysce => sysce_x0, sysclk => sysclk_x0, sysclr => sysce_clr_x0, ce => xlclockdriver_1_ce, clk => xlclockdriver_1_clk ); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity plb_clock_driver is port ( sysce: in std_logic; sysce_clr: in std_logic; sysclk: in std_logic; plb_ce_1: out std_logic; plb_clk_1: out std_logic ); end plb_clock_driver; architecture structural of plb_clock_driver is attribute syn_noprune: boolean; attribute syn_noprune of structural : architecture is true; attribute optimize_primitives: boolean; attribute optimize_primitives of structural : architecture is false; attribute dont_touch: boolean; attribute dont_touch of structural : architecture is true; signal sysce_clr_x0: std_logic; signal sysce_x0: std_logic; signal sysclk_x0: std_logic; signal xlclockdriver_1_ce: std_logic; signal xlclockdriver_1_clk: std_logic; begin sysce_x0 <= sysce; sysce_clr_x0 <= sysce_clr; sysclk_x0 <= sysclk; plb_ce_1 <= xlclockdriver_1_ce; plb_clk_1 <= xlclockdriver_1_clk; xlclockdriver_1: entity work.xlclockdriver generic map ( log_2_period => 1, period => 1, use_bufg => 0 ) port map ( sysce => sysce_x0, sysclk => sysclk_x0, sysclr => sysce_clr_x0, ce => xlclockdriver_1_ce, clk => xlclockdriver_1_clk ); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity sg_i2c_controller_s6_cw is port ( ce: in std_logic := '1'; clk: in std_logic; -- clock period = 10.0 ns (100.0 Mhz) i2c_sda_i: in std_logic; plb_abus: in std_logic_vector(31 downto 0); plb_pavalid: in std_logic; plb_rnw: in std_logic; plb_wrdbus: in std_logic_vector(31 downto 0); sg_plb_addrpref: in std_logic_vector(19 downto 0); splb_rst: in std_logic; xps_ce: in std_logic := '1'; xps_clk: in std_logic; -- clock period = 10.0 ns (100.0 Mhz) gpio_out8_o: out std_logic_vector(7 downto 0); i2c_scl: out std_logic; i2c_sda_o: out std_logic; i2c_sda_t: out std_logic; sl_addrack: out std_logic; sl_rdcomp: out std_logic; sl_rddack: out std_logic; sl_rddbus: out std_logic_vector(31 downto 0); sl_wait: out std_logic; sl_wrcomp: out std_logic; sl_wrdack: out std_logic ); end sg_i2c_controller_s6_cw; architecture structural of sg_i2c_controller_s6_cw is component fifo_generator_spartan6_6_1_a1065cba3626fc97 port ( din: in std_logic_vector(31 downto 0); rd_clk: in std_logic; rd_en: in std_logic; rst: in std_logic; wr_clk: in std_logic; wr_en: in std_logic; dout: out std_logic_vector(31 downto 0); empty: out std_logic; full: out std_logic; rd_data_count: out std_logic_vector(0 downto 0); wr_data_count: out std_logic_vector(0 downto 0) ); end component; attribute syn_black_box: boolean; attribute syn_black_box of fifo_generator_spartan6_6_1_a1065cba3626fc97: component is true; attribute box_type: string; attribute box_type of fifo_generator_spartan6_6_1_a1065cba3626fc97: component is "black_box"; attribute syn_noprune: boolean; attribute optimize_primitives: boolean; attribute dont_touch: boolean; attribute syn_noprune of fifo_generator_spartan6_6_1_a1065cba3626fc97: component is true; attribute optimize_primitives of fifo_generator_spartan6_6_1_a1065cba3626fc97: component is false; attribute dont_touch of fifo_generator_spartan6_6_1_a1065cba3626fc97: component is true; component fifo_generator_spartan6_6_1_ba61a4be12cec537 port ( din: in std_logic_vector(31 downto 0); rd_clk: in std_logic; rd_en: in std_logic; rst: in std_logic; wr_clk: in std_logic; wr_en: in std_logic; dout: out std_logic_vector(31 downto 0); empty: out std_logic; full: out std_logic; wr_data_count: out std_logic_vector(0 downto 0) ); end component; attribute syn_black_box of fifo_generator_spartan6_6_1_ba61a4be12cec537: component is true; attribute box_type of fifo_generator_spartan6_6_1_ba61a4be12cec537: component is "black_box"; attribute syn_noprune of fifo_generator_spartan6_6_1_ba61a4be12cec537: component is true; attribute optimize_primitives of fifo_generator_spartan6_6_1_ba61a4be12cec537: component is false; attribute dont_touch of fifo_generator_spartan6_6_1_ba61a4be12cec537: component is true; component xlpersistentdff port ( clk: in std_logic; d: in std_logic; q: out std_logic ); end component; attribute syn_black_box of xlpersistentdff: component is true; attribute box_type of xlpersistentdff: component is "black_box"; attribute syn_noprune of xlpersistentdff: component is true; attribute optimize_primitives of xlpersistentdff: component is false; attribute dont_touch of xlpersistentdff: component is true; signal ce_1_sg_x1: std_logic; attribute MAX_FANOUT: string; attribute MAX_FANOUT of ce_1_sg_x1: signal is "REDUCE"; signal clkNet: std_logic; signal clkNet_x0: std_logic; signal clk_1_sg_x1: std_logic; signal cmd_request_rd_en: std_logic; signal cmd_request_wr_en: std_logic; signal cmd_response_rd_en: std_logic; signal cmd_response_wr_en: std_logic; signal data_in_net: std_logic_vector(7 downto 0); signal data_in_x0_net: std_logic_vector(31 downto 0); signal data_in_x1_net: std_logic_vector(31 downto 0); signal data_out_x0_net: std_logic_vector(31 downto 0); signal data_out_x1_net: std_logic_vector(31 downto 0); signal empty_net: std_logic; signal empty_x0_net: std_logic; signal en_net: std_logic; signal from_register_data_out_net: std_logic_vector(7 downto 0); signal from_register_data_out_net_x0: std_logic_vector(7 downto 0); signal full_net: std_logic; signal gpio_out8_reg_ce: std_logic; signal i2c_scl_net: std_logic; signal i2c_sda_i_net: std_logic; signal i2c_sda_o_net: std_logic; signal i2c_sda_t_net: std_logic; signal percent_full_net: std_logic; signal percent_full_x0_net: std_logic; signal persistentdff_inst_q: std_logic; attribute syn_keep: boolean; attribute syn_keep of persistentdff_inst_q: signal is true; attribute keep: boolean; attribute keep of persistentdff_inst_q: signal is true; attribute preserve_signal: boolean; attribute preserve_signal of persistentdff_inst_q: signal is true; signal persistentdff_inst_x0_q: std_logic; attribute syn_keep of persistentdff_inst_x0_q: signal is true; attribute keep of persistentdff_inst_x0_q: signal is true; attribute preserve_signal of persistentdff_inst_x0_q: signal is true; signal plb_abus_net: std_logic_vector(31 downto 0); signal plb_ce_1_sg_x1: std_logic; attribute MAX_FANOUT of plb_ce_1_sg_x1: signal is "REDUCE"; signal plb_clk_1_sg_x1: std_logic; signal plb_pavalid_net: std_logic; signal plb_rnw_net: std_logic; signal plb_wrdbus_net: std_logic_vector(31 downto 0); signal re_net: std_logic; signal re_x0_net: std_logic; signal sg_plb_addrpref_net: std_logic_vector(19 downto 0); signal sl_addrack_net: std_logic; signal sl_rdcomp_net: std_logic; signal sl_rddack_net: std_logic; signal sl_rddbus_net: std_logic_vector(31 downto 0); signal sl_wait_net: std_logic; signal sl_wrdack_x1: std_logic; signal sl_wrdack_x2: std_logic; signal splb_rst_net: std_logic; signal to_fifo_full_net: std_logic; signal to_fifo_percent_full_net: std_logic; signal we_net: std_logic; signal we_x0_net: std_logic; begin clkNet <= clk; i2c_sda_i_net <= i2c_sda_i; plb_abus_net <= plb_abus; plb_pavalid_net <= plb_pavalid; plb_rnw_net <= plb_rnw; plb_wrdbus_net <= plb_wrdbus; sg_plb_addrpref_net <= sg_plb_addrpref; splb_rst_net <= splb_rst; clkNet_x0 <= xps_clk; gpio_out8_o <= from_register_data_out_net_x0; i2c_scl <= i2c_scl_net; i2c_sda_o <= i2c_sda_o_net; i2c_sda_t <= i2c_sda_t_net; sl_addrack <= sl_addrack_net; sl_rdcomp <= sl_rdcomp_net; sl_rddack <= sl_rddack_net; sl_rddbus <= sl_rddbus_net; sl_wait <= sl_wait_net; sl_wrcomp <= sl_wrdack_x2; sl_wrdack <= sl_wrdack_x1; cmd_request: fifo_generator_spartan6_6_1_ba61a4be12cec537 port map ( din => data_in_x0_net, rd_clk => clk_1_sg_x1, rd_en => cmd_request_rd_en, rst => '0', wr_clk => plb_clk_1_sg_x1, wr_en => cmd_request_wr_en, dout => data_out_x1_net, empty => empty_x0_net, full => full_net, wr_data_count(0) => percent_full_x0_net ); cmd_request_re_and2_comp: entity work.xland2 port map ( a => ce_1_sg_x1, b => re_x0_net, dout => cmd_request_rd_en ); cmd_request_we_and2_comp: entity work.xland2 port map ( a => plb_ce_1_sg_x1, b => we_net, dout => cmd_request_wr_en ); cmd_response: fifo_generator_spartan6_6_1_a1065cba3626fc97 port map ( din => data_in_x1_net, rd_clk => plb_clk_1_sg_x1, rd_en => cmd_response_rd_en, rst => '0', wr_clk => clk_1_sg_x1, wr_en => cmd_response_wr_en, dout => data_out_x0_net, empty => empty_net, full => to_fifo_full_net, rd_data_count(0) => percent_full_net, wr_data_count(0) => to_fifo_percent_full_net ); cmd_response_re_and2_comp: entity work.xland2 port map ( a => plb_ce_1_sg_x1, b => re_net, dout => cmd_response_rd_en ); cmd_response_we_and2_comp: entity work.xland2 port map ( a => ce_1_sg_x1, b => we_x0_net, dout => cmd_response_wr_en ); default_clock_driver_x0: entity work.default_clock_driver port map ( sysce => '1', sysce_clr => '0', sysclk => clkNet, ce_1 => ce_1_sg_x1, clk_1 => clk_1_sg_x1 ); gpio_out8: entity work.synth_reg_w_init generic map ( width => 8, init_index => 2, init_value => b"00000000", latency => 1 ) port map ( ce => gpio_out8_reg_ce, clk => plb_clk_1_sg_x1, clr => '0', i => data_in_net, o => from_register_data_out_net ); gpio_out8_ce_and2_comp: entity work.xland2 port map ( a => plb_ce_1_sg_x1, b => en_net, dout => gpio_out8_reg_ce ); persistentdff_inst: xlpersistentdff port map ( clk => clkNet, d => persistentdff_inst_q, q => persistentdff_inst_q ); persistentdff_inst_x0: xlpersistentdff port map ( clk => clkNet, d => persistentdff_inst_x0_q, q => persistentdff_inst_x0_q ); plb_clock_driver_x0: entity work.plb_clock_driver port map ( sysce => '1', sysce_clr => '0', sysclk => clkNet_x0, plb_ce_1 => plb_ce_1_sg_x1, plb_clk_1 => plb_clk_1_sg_x1 ); sg_i2c_controller_s6_x0: entity work.sg_i2c_controller_s6 port map ( ce_1 => ce_1_sg_x1, clk_1 => clk_1_sg_x1, data_out => from_register_data_out_net, data_out_x0 => data_out_x0_net, data_out_x1 => data_out_x1_net, dout => from_register_data_out_net, empty => empty_net, empty_x0 => empty_x0_net, full => full_net, i2c_sda_i => i2c_sda_i_net, percent_full => percent_full_net, percent_full_x0 => percent_full_x0_net, plb_abus => plb_abus_net, plb_ce_1 => plb_ce_1_sg_x1, plb_clk_1 => plb_clk_1_sg_x1, plb_pavalid => plb_pavalid_net, plb_rnw => plb_rnw_net, plb_wrdbus => plb_wrdbus_net, sg_plb_addrpref => sg_plb_addrpref_net, splb_rst => splb_rst_net, data_in => data_in_net, data_in_x0 => data_in_x0_net, data_in_x1 => data_in_x1_net, en => en_net, gpio_out8_o => from_register_data_out_net_x0, i2c_scl => i2c_scl_net, i2c_sda_o => i2c_sda_o_net, i2c_sda_t => i2c_sda_t_net, re => re_net, re_x0 => re_x0_net, sl_addrack => sl_addrack_net, sl_rdcomp => sl_rdcomp_net, sl_rddack => sl_rddack_net, sl_rddbus => sl_rddbus_net, sl_wait => sl_wait_net, sl_wrcomp => sl_wrdack_x2, sl_wrdack => sl_wrdack_x1, we => we_net, we_x0 => we_x0_net ); end structural;
gpl-3.0
bca920519ccfde4893bbd0c15c3499c6
0.637936
3.367505
false
false
false
false
tghaefli/ADD
EDK/IVK_Repos/IVK_IPLib/pcores/ivk_video_gen_v2_01_a/hdl/vhdl/colorbargen.vhd
1
8,603
------------------------------------------------------------------ -- _____ -- / \ -- /____ \____ -- / \===\ \==/ -- /___\===\___\/ AVNET -- \======/ -- \====/ ----------------------------------------------------------------- -- -- This design is the property of Avnet. Publication of this -- design is not authorized without written consent from Avnet. -- -- Please direct any questions to: [email protected] -- -- Disclaimer: -- Avnet, Inc. makes no warranty for the use of this code or design. -- This code is provided "As Is". Avnet, Inc assumes no responsibility for -- any errors, which may appear in this code, nor does it make a commitment -- to update the information contained herein. Avnet, Inc specifically -- disclaims any implied warranties of fitness for a particular purpose. -- Copyright(c) 2010 Avnet, Inc. -- All rights reserved. -- ------------------------------------------------------------------ -- -- Create Date: Dec 03, 2009 -- Design Name: IVK -- Module Name: ivk_video_gen\colorbargen.vhd -- Project Name: IVK -- Target Devices: Spartan-6 -- Avnet Boards: IVK -- -- Tool versions: ISE 11.4 -- -- Description: Color Bar Generator -- -- Dependencies: -- -- Revision: Dec 03, 2009: 1.00 Initial version -- ------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; -- NOTES : Generate 8 color bars -- -- R G B => Color -- === === === =========== -- 000 000 000 => K (black) -- 000 000 255 => B (blue) -- 000 255 000 => G (green) -- 000 255 255 => C (cyan) -- 255 000 000 => R (red) -- 255 000 255 => M (magenta) -- 255 255 000 => Y (yellow) -- 255 255 255 => W (white) -- -- Suggested Color Bar order : WYCGMRKB -- entity ColorBarGen is generic ( HWidth_g : integer := 16; VWidth_g : integer := 16 ); port ( -- Global Reset i_clk_p : in std_logic; i_Reset_p : in std_logic; -- Image Size iv_HActive_p : in std_logic_vector(HWidth_g-1 downto 0); iv_VActive_p : in std_logic_vector(VWidth_g-1 downto 0); -- Data Request strobe (1 cycle in advance of synchronization signals) iv_HCount_p : in std_logic_vector(HWidth_g-1 downto 0); iv_VCount_p : in std_logic_vector(VWidth_g-1 downto 0); i_PixelRequest_p : in std_logic; -- Pixel Output o_PixelValid_p : out std_logic; ov8_RPixel_p : out std_logic_vector(7 downto 0); ov8_GPixel_p : out std_logic_vector(7 downto 0); ov8_BPixel_p : out std_logic_vector(7 downto 0) ); end entity ColorBarGen; architecture Rtl of ColorBarGen is -- -- Intermediate signals for output ports -- -- Pixel Output signal PixelValid_s : std_logic; signal v8_RPixel_s : std_logic_vector(7 downto 0); signal v8_GPixel_s : std_logic_vector(7 downto 0); signal v8_BPixel_s : std_logic_vector(7 downto 0); -- -- Color Bar Generation -- type ColorState_t is ( White_c, Yellow_c, Cyan_c, Green_c, Magenta_c, Red_c, Black_c, Blue_c ); signal ColorState_s : ColorState_t; attribute fsm_encoding : string; attribute fsm_encoding of ColorState_s : signal is "sequential"; attribute safe_implementation : string; attribute safe_implementation of ColorState_s : signal is "yes"; alias v_HActiveDiv8_a : std_logic_vector(HWidth_g-4 downto 0) is iv_HActive_p(HWidth_g-1 downto 3); begin -- -- Output port assignments -- -- Pixel Output o_PixelValid_p <= PixelValid_s; ov8_RPixel_p <= v8_RPixel_s; ov8_GPixel_p <= v8_GPixel_s; ov8_BPixel_p <= v8_BPixel_s; -- -- Color Bar Generation -- ColorBar_l : process( i_Clk_p, i_Reset_p ) begin if ( i_Reset_p = '1' ) then PixelValid_s <= '0'; v8_RPixel_s <= (others => '0'); v8_GPixel_s <= (others => '0'); v8_BPixel_s <= (others => '0'); ColorState_s <= White_c; elsif rising_edge( i_Clk_p ) then -- Default values PixelValid_s <= '0'; v8_RPixel_s <= (others => '0'); v8_GPixel_s <= (others => '0'); v8_BPixel_s <= (others => '0'); -- Active Video if ( i_PixelRequest_p = '1' ) then PixelValid_s <= '1'; case ColorState_s is when White_c => if unsigned(iv_HCount_p) >= (unsigned(v_HActiveDiv8_a)-1) then ColorState_s <= Yellow_c; end if; v8_RPixel_s <= X"FF"; v8_GPixel_s <= X"FF"; v8_BPixel_s <= X"FF"; when Yellow_c => if unsigned(iv_HCount_p) >= (2*unsigned(v_HActiveDiv8_a)-1) then ColorState_s <= Cyan_c; end if; v8_RPixel_s <= X"FF"; v8_GPixel_s <= X"FF"; v8_BPixel_s <= (others => '0'); when Cyan_c => if unsigned(iv_HCount_p) >= (3*unsigned(v_HActiveDiv8_a)-1) then ColorState_s <= Green_c; end if; v8_RPixel_s <= (others => '0'); v8_GPixel_s <= X"FF"; v8_BPixel_s <= X"FF"; when Green_c => if unsigned(iv_HCount_p) >= (4*unsigned(v_HActiveDiv8_a)-1) then ColorState_s <= Magenta_c; end if; v8_RPixel_s <= (others => '0'); v8_GPixel_s <= X"FF"; v8_BPixel_s <= (others => '0'); when Magenta_c => if unsigned(iv_HCount_p) >= (5*unsigned(v_HActiveDiv8_a)-1) then ColorState_s <= Red_c; end if; v8_RPixel_s <= X"FF"; v8_GPixel_s <= (others => '0'); v8_BPixel_s <= X"FF"; when Red_c => if unsigned(iv_HCount_p) >= (6*unsigned(v_HActiveDiv8_a)-1) then ColorState_s <= Black_c; end if; v8_RPixel_s <= X"FF"; v8_GPixel_s <= (others => '0'); v8_BPixel_s <= (others => '0'); when Black_c => if unsigned(iv_HCount_p) >= (7*unsigned(v_HActiveDiv8_a)-1) then ColorState_s <= Blue_c; end if; v8_RPixel_s <= (others => '0'); v8_GPixel_s <= (others => '0'); v8_BPixel_s <= (others => '0'); when Blue_c => if unsigned(iv_HCount_p) >= (unsigned(iv_HActive_p)-1) then ColorState_s <= White_c; end if; v8_RPixel_s <= (others => '0'); v8_GPixel_s <= (others => '0'); v8_BPixel_s <= X"FF"; when others => PixelValid_s <= '0'; v8_RPixel_s <= (others => '0'); v8_GPixel_s <= (others => '0'); v8_BPixel_s <= (others => '0'); ColorState_s <= White_c; end case; end if; end if; end process ColorBar_l; end architecture Rtl;
gpl-3.0
ec1dba91012e88936d926e71152b14d6
0.407184
3.852665
false
false
false
false
tghaefli/ADD
EDK/IVK_Repos/IVK_IPLib/pcores/sg_cfa_gamma_plbw_v1_00_a/hdl/vhdl/sg_cfa_gamma.vhd
1
210,700
-------------------------------------------------------------------------------- -- This file is owned and controlled by Xilinx and must be used solely -- -- for design, simulation, implementation and creation of design files -- -- limited to Xilinx devices or technologies. Use with non-Xilinx -- -- devices or technologies is expressly prohibited and immediately -- -- terminates your license. -- -- -- -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY -- -- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -- -- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE -- -- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS -- -- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY -- -- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY -- -- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY -- -- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- -- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- -- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- -- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- -- PARTICULAR PURPOSE. -- -- -- -- Xilinx products are not intended for use in life support appliances, -- -- devices, or systems. Use in such applications are expressly -- -- prohibited. -- -- -- -- (c) Copyright 1995-2012 Xilinx, Inc. -- -- All rights reserved. -- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -- You must compile the wrapper file addsb_11_0_a629aff4db5bb1c8.vhd when simulating -- the core, addsb_11_0_a629aff4db5bb1c8. When compiling the wrapper file, be sure to -- reference the XilinxCoreLib VHDL simulation library. For detailed -- instructions, please refer to the "CORE Generator Help". -- The synthesis directives "translate_off/translate_on" specified -- below are supported by Xilinx, Mentor Graphics and Synplicity -- synthesis tools. Ensure they are correct for your synthesis tool(s). LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- synthesis translate_off LIBRARY XilinxCoreLib; -- synthesis translate_on ENTITY addsb_11_0_a629aff4db5bb1c8 IS PORT ( a : IN STD_LOGIC_VECTOR(11 DOWNTO 0); b : IN STD_LOGIC_VECTOR(11 DOWNTO 0); s : OUT STD_LOGIC_VECTOR(11 DOWNTO 0) ); END addsb_11_0_a629aff4db5bb1c8; ARCHITECTURE addsb_11_0_a629aff4db5bb1c8_a OF addsb_11_0_a629aff4db5bb1c8 IS -- synthesis translate_off COMPONENT wrapped_addsb_11_0_a629aff4db5bb1c8 PORT ( a : IN STD_LOGIC_VECTOR(11 DOWNTO 0); b : IN STD_LOGIC_VECTOR(11 DOWNTO 0); s : OUT STD_LOGIC_VECTOR(11 DOWNTO 0) ); END COMPONENT; -- Configuration specification FOR ALL : wrapped_addsb_11_0_a629aff4db5bb1c8 USE ENTITY XilinxCoreLib.c_addsub_v11_0(behavioral) GENERIC MAP ( c_a_type => 1, c_a_width => 12, c_add_mode => 0, c_ainit_val => "0", c_b_constant => 0, c_b_type => 1, c_b_value => "000000000000", c_b_width => 12, c_borrow_low => 1, c_bypass_low => 0, c_ce_overrides_bypass => 1, c_ce_overrides_sclr => 0, c_has_bypass => 0, c_has_c_in => 0, c_has_c_out => 0, c_has_ce => 0, c_has_sclr => 0, c_has_sinit => 0, c_has_sset => 0, c_implementation => 0, c_latency => 0, c_out_width => 12, c_sclr_overrides_sset => 0, c_sinit_val => "0", c_verbosity => 0, c_xdevicefamily => "spartan6" ); -- synthesis translate_on BEGIN -- synthesis translate_off U0 : wrapped_addsb_11_0_a629aff4db5bb1c8 PORT MAP ( a => a, b => b, s => s ); -- synthesis translate_on END addsb_11_0_a629aff4db5bb1c8_a; -------------------------------------------------------------------------------- -- This file is owned and controlled by Xilinx and must be used solely -- -- for design, simulation, implementation and creation of design files -- -- limited to Xilinx devices or technologies. Use with non-Xilinx -- -- devices or technologies is expressly prohibited and immediately -- -- terminates your license. -- -- -- -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY -- -- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -- -- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE -- -- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS -- -- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY -- -- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY -- -- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY -- -- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- -- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- -- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- -- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- -- PARTICULAR PURPOSE. -- -- -- -- Xilinx products are not intended for use in life support appliances, -- -- devices, or systems. Use in such applications are expressly -- -- prohibited. -- -- -- -- (c) Copyright 1995-2012 Xilinx, Inc. -- -- All rights reserved. -- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -- You must compile the wrapper file addsb_11_0_c25f95ce6b0868c9.vhd when simulating -- the core, addsb_11_0_c25f95ce6b0868c9. When compiling the wrapper file, be sure to -- reference the XilinxCoreLib VHDL simulation library. For detailed -- instructions, please refer to the "CORE Generator Help". -- The synthesis directives "translate_off/translate_on" specified -- below are supported by Xilinx, Mentor Graphics and Synplicity -- synthesis tools. Ensure they are correct for your synthesis tool(s). LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- synthesis translate_off LIBRARY XilinxCoreLib; -- synthesis translate_on ENTITY addsb_11_0_c25f95ce6b0868c9 IS PORT ( a : IN STD_LOGIC_VECTOR(10 DOWNTO 0); b : IN STD_LOGIC_VECTOR(10 DOWNTO 0); s : OUT STD_LOGIC_VECTOR(10 DOWNTO 0) ); END addsb_11_0_c25f95ce6b0868c9; ARCHITECTURE addsb_11_0_c25f95ce6b0868c9_a OF addsb_11_0_c25f95ce6b0868c9 IS -- synthesis translate_off COMPONENT wrapped_addsb_11_0_c25f95ce6b0868c9 PORT ( a : IN STD_LOGIC_VECTOR(10 DOWNTO 0); b : IN STD_LOGIC_VECTOR(10 DOWNTO 0); s : OUT STD_LOGIC_VECTOR(10 DOWNTO 0) ); END COMPONENT; -- Configuration specification FOR ALL : wrapped_addsb_11_0_c25f95ce6b0868c9 USE ENTITY XilinxCoreLib.c_addsub_v11_0(behavioral) GENERIC MAP ( c_a_type => 1, c_a_width => 11, c_add_mode => 0, c_ainit_val => "0", c_b_constant => 0, c_b_type => 1, c_b_value => "00000000000", c_b_width => 11, c_borrow_low => 1, c_bypass_low => 0, c_ce_overrides_bypass => 1, c_ce_overrides_sclr => 0, c_has_bypass => 0, c_has_c_in => 0, c_has_c_out => 0, c_has_ce => 0, c_has_sclr => 0, c_has_sinit => 0, c_has_sset => 0, c_implementation => 0, c_latency => 0, c_out_width => 11, c_sclr_overrides_sset => 0, c_sinit_val => "0", c_verbosity => 0, c_xdevicefamily => "spartan6" ); -- synthesis translate_on BEGIN -- synthesis translate_off U0 : wrapped_addsb_11_0_c25f95ce6b0868c9 PORT MAP ( a => a, b => b, s => s ); -- synthesis translate_on END addsb_11_0_c25f95ce6b0868c9_a; -------------------------------------------------------------------------------- -- This file is owned and controlled by Xilinx and must be used solely -- -- for design, simulation, implementation and creation of design files -- -- limited to Xilinx devices or technologies. Use with non-Xilinx -- -- devices or technologies is expressly prohibited and immediately -- -- terminates your license. -- -- -- -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY -- -- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -- -- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE -- -- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS -- -- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY -- -- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY -- -- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY -- -- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- -- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- -- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- -- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- -- PARTICULAR PURPOSE. -- -- -- -- Xilinx products are not intended for use in life support appliances, -- -- devices, or systems. Use in such applications are expressly -- -- prohibited. -- -- -- -- (c) Copyright 1995-2012 Xilinx, Inc. -- -- All rights reserved. -- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -- You must compile the wrapper file bmg_62_2be284cffc9a51ef.vhd when simulating -- the core, bmg_62_2be284cffc9a51ef. When compiling the wrapper file, be sure to -- reference the XilinxCoreLib VHDL simulation library. For detailed -- instructions, please refer to the "CORE Generator Help". -- The synthesis directives "translate_off/translate_on" specified -- below are supported by Xilinx, Mentor Graphics and Synplicity -- synthesis tools. Ensure they are correct for your synthesis tool(s). LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- synthesis translate_off LIBRARY XilinxCoreLib; -- synthesis translate_on ENTITY bmg_62_2be284cffc9a51ef IS PORT ( clka : IN STD_LOGIC; ena : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(9 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) ); END bmg_62_2be284cffc9a51ef; ARCHITECTURE bmg_62_2be284cffc9a51ef_a OF bmg_62_2be284cffc9a51ef IS -- synthesis translate_off COMPONENT wrapped_bmg_62_2be284cffc9a51ef PORT ( clka : IN STD_LOGIC; ena : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(9 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) ); END COMPONENT; -- Configuration specification FOR ALL : wrapped_bmg_62_2be284cffc9a51ef USE ENTITY XilinxCoreLib.blk_mem_gen_v6_2(behavioral) GENERIC MAP ( c_addra_width => 11, c_addrb_width => 11, c_algorithm => 1, c_axi_id_width => 4, c_axi_slave_type => 0, c_axi_type => 1, c_byte_size => 9, c_common_clk => 0, c_default_data => "0", c_disable_warn_bhv_coll => 0, c_disable_warn_bhv_range => 0, c_family => "spartan6", c_has_axi_id => 0, c_has_ena => 1, c_has_enb => 0, c_has_injecterr => 0, c_has_mem_output_regs_a => 0, c_has_mem_output_regs_b => 0, c_has_mux_output_regs_a => 0, c_has_mux_output_regs_b => 0, c_has_regcea => 0, c_has_regceb => 0, c_has_rsta => 0, c_has_rstb => 0, c_has_softecc_input_regs_a => 0, c_has_softecc_output_regs_b => 0, c_init_file_name => "bmg_62_2be284cffc9a51ef.mif", c_inita_val => "0", c_initb_val => "0", c_interface_type => 0, c_load_init_file => 1, c_mem_type => 0, c_mux_pipeline_stages => 0, c_prim_type => 1, c_read_depth_a => 2048, c_read_depth_b => 2048, c_read_width_a => 10, c_read_width_b => 10, c_rst_priority_a => "CE", c_rst_priority_b => "CE", c_rst_type => "SYNC", c_rstram_a => 0, c_rstram_b => 0, c_sim_collision_check => "ALL", c_use_byte_wea => 0, c_use_byte_web => 0, c_use_default_data => 0, c_use_ecc => 0, c_use_softecc => 0, c_wea_width => 1, c_web_width => 1, c_write_depth_a => 2048, c_write_depth_b => 2048, c_write_mode_a => "READ_FIRST", c_write_mode_b => "WRITE_FIRST", c_write_width_a => 10, c_write_width_b => 10, c_xdevicefamily => "spartan6" ); -- synthesis translate_on BEGIN -- synthesis translate_off U0 : wrapped_bmg_62_2be284cffc9a51ef PORT MAP ( clka => clka, ena => ena, wea => wea, addra => addra, dina => dina, douta => douta ); -- synthesis translate_on END bmg_62_2be284cffc9a51ef_a; -------------------------------------------------------------------------------- -- This file is owned and controlled by Xilinx and must be used solely -- -- for design, simulation, implementation and creation of design files -- -- limited to Xilinx devices or technologies. Use with non-Xilinx -- -- devices or technologies is expressly prohibited and immediately -- -- terminates your license. -- -- -- -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY -- -- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -- -- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE -- -- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS -- -- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY -- -- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY -- -- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY -- -- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- -- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- -- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- -- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- -- PARTICULAR PURPOSE. -- -- -- -- Xilinx products are not intended for use in life support appliances, -- -- devices, or systems. Use in such applications are expressly -- -- prohibited. -- -- -- -- (c) Copyright 1995-2012 Xilinx, Inc. -- -- All rights reserved. -- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -- You must compile the wrapper file bmg_62_efdcd0e54d01b373.vhd when simulating -- the core, bmg_62_efdcd0e54d01b373. When compiling the wrapper file, be sure to -- reference the XilinxCoreLib VHDL simulation library. For detailed -- instructions, please refer to the "CORE Generator Help". -- The synthesis directives "translate_off/translate_on" specified -- below are supported by Xilinx, Mentor Graphics and Synplicity -- synthesis tools. Ensure they are correct for your synthesis tool(s). LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- synthesis translate_off LIBRARY XilinxCoreLib; -- synthesis translate_on ENTITY bmg_62_efdcd0e54d01b373 IS PORT ( clka : IN STD_LOGIC; ena : IN STD_LOGIC; addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END bmg_62_efdcd0e54d01b373; ARCHITECTURE bmg_62_efdcd0e54d01b373_a OF bmg_62_efdcd0e54d01b373 IS -- synthesis translate_off COMPONENT wrapped_bmg_62_efdcd0e54d01b373 PORT ( clka : IN STD_LOGIC; ena : IN STD_LOGIC; addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END COMPONENT; -- Configuration specification FOR ALL : wrapped_bmg_62_efdcd0e54d01b373 USE ENTITY XilinxCoreLib.blk_mem_gen_v6_2(behavioral) GENERIC MAP ( c_addra_width => 8, c_addrb_width => 8, c_algorithm => 1, c_axi_id_width => 4, c_axi_slave_type => 0, c_axi_type => 1, c_byte_size => 9, c_common_clk => 0, c_default_data => "0", c_disable_warn_bhv_coll => 0, c_disable_warn_bhv_range => 0, c_family => "spartan6", c_has_axi_id => 0, c_has_ena => 1, c_has_enb => 0, c_has_injecterr => 0, c_has_mem_output_regs_a => 0, c_has_mem_output_regs_b => 0, c_has_mux_output_regs_a => 0, c_has_mux_output_regs_b => 0, c_has_regcea => 0, c_has_regceb => 0, c_has_rsta => 0, c_has_rstb => 0, c_has_softecc_input_regs_a => 0, c_has_softecc_output_regs_b => 0, c_init_file_name => "bmg_62_efdcd0e54d01b373.mif", c_inita_val => "0", c_initb_val => "0", c_interface_type => 0, c_load_init_file => 1, c_mem_type => 3, c_mux_pipeline_stages => 0, c_prim_type => 1, c_read_depth_a => 255, c_read_depth_b => 255, c_read_width_a => 8, c_read_width_b => 8, c_rst_priority_a => "CE", c_rst_priority_b => "CE", c_rst_type => "SYNC", c_rstram_a => 0, c_rstram_b => 0, c_sim_collision_check => "ALL", c_use_byte_wea => 0, c_use_byte_web => 0, c_use_default_data => 0, c_use_ecc => 0, c_use_softecc => 0, c_wea_width => 1, c_web_width => 1, c_write_depth_a => 255, c_write_depth_b => 255, c_write_mode_a => "WRITE_FIRST", c_write_mode_b => "WRITE_FIRST", c_write_width_a => 8, c_write_width_b => 8, c_xdevicefamily => "spartan6" ); -- synthesis translate_on BEGIN -- synthesis translate_off U0 : wrapped_bmg_62_efdcd0e54d01b373 PORT MAP ( clka => clka, ena => ena, addra => addra, douta => douta ); -- synthesis translate_on END bmg_62_efdcd0e54d01b373_a; -------------------------------------------------------------------------------- -- This file is owned and controlled by Xilinx and must be used solely -- -- for design, simulation, implementation and creation of design files -- -- limited to Xilinx devices or technologies. Use with non-Xilinx -- -- devices or technologies is expressly prohibited and immediately -- -- terminates your license. -- -- -- -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY -- -- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -- -- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE -- -- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS -- -- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY -- -- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY -- -- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY -- -- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- -- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- -- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- -- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- -- PARTICULAR PURPOSE. -- -- -- -- Xilinx products are not intended for use in life support appliances, -- -- devices, or systems. Use in such applications are expressly -- -- prohibited. -- -- -- -- (c) Copyright 1995-2012 Xilinx, Inc. -- -- All rights reserved. -- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -- You must compile the wrapper file cntr_11_0_3eb0c8dcd9c22b4d.vhd when simulating -- the core, cntr_11_0_3eb0c8dcd9c22b4d. When compiling the wrapper file, be sure to -- reference the XilinxCoreLib VHDL simulation library. For detailed -- instructions, please refer to the "CORE Generator Help". -- The synthesis directives "translate_off/translate_on" specified -- below are supported by Xilinx, Mentor Graphics and Synplicity -- synthesis tools. Ensure they are correct for your synthesis tool(s). LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- synthesis translate_off LIBRARY XilinxCoreLib; -- synthesis translate_on ENTITY cntr_11_0_3eb0c8dcd9c22b4d IS PORT ( clk : IN STD_LOGIC; ce : IN STD_LOGIC; sinit : IN STD_LOGIC; q : OUT STD_LOGIC_VECTOR(11 DOWNTO 0) ); END cntr_11_0_3eb0c8dcd9c22b4d; ARCHITECTURE cntr_11_0_3eb0c8dcd9c22b4d_a OF cntr_11_0_3eb0c8dcd9c22b4d IS -- synthesis translate_off COMPONENT wrapped_cntr_11_0_3eb0c8dcd9c22b4d PORT ( clk : IN STD_LOGIC; ce : IN STD_LOGIC; sinit : IN STD_LOGIC; q : OUT STD_LOGIC_VECTOR(11 DOWNTO 0) ); END COMPONENT; -- Configuration specification FOR ALL : wrapped_cntr_11_0_3eb0c8dcd9c22b4d USE ENTITY XilinxCoreLib.c_counter_binary_v11_0(behavioral) GENERIC MAP ( c_ainit_val => "0", c_ce_overrides_sync => 0, c_count_by => "1", c_count_mode => 0, c_count_to => "1", c_fb_latency => 0, c_has_ce => 1, c_has_load => 0, c_has_sclr => 0, c_has_sinit => 1, c_has_sset => 0, c_has_thresh0 => 0, c_implementation => 0, c_latency => 1, c_load_low => 0, c_restrict_count => 0, c_sclr_overrides_sset => 1, c_sinit_val => "0", c_thresh0_value => "1", c_verbosity => 0, c_width => 12, c_xdevicefamily => "spartan6" ); -- synthesis translate_on BEGIN -- synthesis translate_off U0 : wrapped_cntr_11_0_3eb0c8dcd9c22b4d PORT MAP ( clk => clk, ce => ce, sinit => sinit, q => q ); -- synthesis translate_on END cntr_11_0_3eb0c8dcd9c22b4d_a; ------------------------------------------------------------------- -- System Generator version 13.2 VHDL source file. -- -- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; package conv_pkg is constant simulating : boolean := false -- synopsys translate_off or true -- synopsys translate_on ; constant xlUnsigned : integer := 1; constant xlSigned : integer := 2; constant xlFloat : integer := 3; constant xlWrap : integer := 1; constant xlSaturate : integer := 2; constant xlTruncate : integer := 1; constant xlRound : integer := 2; constant xlRoundBanker : integer := 3; constant xlAddMode : integer := 1; constant xlSubMode : integer := 2; attribute black_box : boolean; attribute syn_black_box : boolean; attribute fpga_dont_touch: string; attribute box_type : string; attribute keep : string; attribute syn_keep : boolean; function std_logic_vector_to_unsigned(inp : std_logic_vector) return unsigned; function unsigned_to_std_logic_vector(inp : unsigned) return std_logic_vector; function std_logic_vector_to_signed(inp : std_logic_vector) return signed; function signed_to_std_logic_vector(inp : signed) return std_logic_vector; function unsigned_to_signed(inp : unsigned) return signed; function signed_to_unsigned(inp : signed) return unsigned; function pos(inp : std_logic_vector; arith : INTEGER) return boolean; function all_same(inp: std_logic_vector) return boolean; function all_zeros(inp: std_logic_vector) return boolean; function is_point_five(inp: std_logic_vector) return boolean; function all_ones(inp: std_logic_vector) return boolean; function convert_type (inp : std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith, quantization, overflow : INTEGER) return std_logic_vector; function cast (inp : std_logic_vector; old_bin_pt, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector; function shift_division_result(quotient, fraction: std_logic_vector; fraction_width, shift_value, shift_dir: INTEGER) return std_logic_vector; function shift_op (inp: std_logic_vector; result_width, shift_value, shift_dir: INTEGER) return std_logic_vector; function vec_slice (inp : std_logic_vector; upper, lower : INTEGER) return std_logic_vector; function s2u_slice (inp : signed; upper, lower : INTEGER) return unsigned; function u2u_slice (inp : unsigned; upper, lower : INTEGER) return unsigned; function s2s_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER) return signed; function u2s_cast (inp : unsigned; old_bin_pt, new_width, new_bin_pt : INTEGER) return signed; function s2u_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER) return unsigned; function u2u_cast (inp : unsigned; old_bin_pt, new_width, new_bin_pt : INTEGER) return unsigned; function u2v_cast (inp : unsigned; old_bin_pt, new_width, new_bin_pt : INTEGER) return std_logic_vector; function s2v_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER) return std_logic_vector; function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector; function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector; function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector; function max_signed(width : INTEGER) return std_logic_vector; function min_signed(width : INTEGER) return std_logic_vector; function saturation_arith(inp: std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector; function wrap_arith(inp: std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector; function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER; function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER) return INTEGER; function sign_ext(inp : std_logic_vector; new_width : INTEGER) return std_logic_vector; function zero_ext(inp : std_logic_vector; new_width : INTEGER) return std_logic_vector; function zero_ext(inp : std_logic; new_width : INTEGER) return std_logic_vector; function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER) return std_logic_vector; function align_input(inp : std_logic_vector; old_width, delta, new_arith, new_width: INTEGER) return std_logic_vector; function pad_LSB(inp : std_logic_vector; new_width: integer) return std_logic_vector; function pad_LSB(inp : std_logic_vector; new_width, arith : integer) return std_logic_vector; function max(L, R: INTEGER) return INTEGER; function min(L, R: INTEGER) return INTEGER; function "="(left,right: STRING) return boolean; function boolean_to_signed (inp : boolean; width: integer) return signed; function boolean_to_unsigned (inp : boolean; width: integer) return unsigned; function boolean_to_vector (inp : boolean) return std_logic_vector; function std_logic_to_vector (inp : std_logic) return std_logic_vector; function integer_to_std_logic_vector (inp : integer; width, arith : integer) return std_logic_vector; function std_logic_vector_to_integer (inp : std_logic_vector; arith : integer) return integer; function std_logic_to_integer(constant inp : std_logic := '0') return integer; function bin_string_element_to_std_logic_vector (inp : string; width, index : integer) return std_logic_vector; function bin_string_to_std_logic_vector (inp : string) return std_logic_vector; function hex_string_to_std_logic_vector (inp : string; width : integer) return std_logic_vector; function makeZeroBinStr (width : integer) return STRING; function and_reduce(inp: std_logic_vector) return std_logic; -- synopsys translate_off function is_binary_string_invalid (inp : string) return boolean; function is_binary_string_undefined (inp : string) return boolean; function is_XorU(inp : std_logic_vector) return boolean; function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer) return real; function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer) return real; function real_to_std_logic_vector (inp : real; width, bin_pt, arith : integer) return std_logic_vector; function real_string_to_std_logic_vector (inp : string; width, bin_pt, arith : integer) return std_logic_vector; constant display_precision : integer := 20; function real_to_string (inp : real) return string; function valid_bin_string(inp : string) return boolean; function std_logic_vector_to_bin_string(inp : std_logic_vector) return string; function std_logic_to_bin_string(inp : std_logic) return string; function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer) return string; function real_to_bin_string(inp : real; width, bin_pt, arith : integer) return string; type stdlogic_to_char_t is array(std_logic) of character; constant to_char : stdlogic_to_char_t := ( 'U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z', 'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-'); -- synopsys translate_on end conv_pkg; package body conv_pkg is function std_logic_vector_to_unsigned(inp : std_logic_vector) return unsigned is begin return unsigned (inp); end; function unsigned_to_std_logic_vector(inp : unsigned) return std_logic_vector is begin return std_logic_vector(inp); end; function std_logic_vector_to_signed(inp : std_logic_vector) return signed is begin return signed (inp); end; function signed_to_std_logic_vector(inp : signed) return std_logic_vector is begin return std_logic_vector(inp); end; function unsigned_to_signed (inp : unsigned) return signed is begin return signed(std_logic_vector(inp)); end; function signed_to_unsigned (inp : signed) return unsigned is begin return unsigned(std_logic_vector(inp)); end; function pos(inp : std_logic_vector; arith : INTEGER) return boolean is constant width : integer := inp'length; variable vec : std_logic_vector(width-1 downto 0); begin vec := inp; if arith = xlUnsigned then return true; else if vec(width-1) = '0' then return true; else return false; end if; end if; return true; end; function max_signed(width : INTEGER) return std_logic_vector is variable ones : std_logic_vector(width-2 downto 0); variable result : std_logic_vector(width-1 downto 0); begin ones := (others => '1'); result(width-1) := '0'; result(width-2 downto 0) := ones; return result; end; function min_signed(width : INTEGER) return std_logic_vector is variable zeros : std_logic_vector(width-2 downto 0); variable result : std_logic_vector(width-1 downto 0); begin zeros := (others => '0'); result(width-1) := '1'; result(width-2 downto 0) := zeros; return result; end; function and_reduce(inp: std_logic_vector) return std_logic is variable result: std_logic; constant width : integer := inp'length; variable vec : std_logic_vector(width-1 downto 0); begin vec := inp; result := vec(0); if width > 1 then for i in 1 to width-1 loop result := result and vec(i); end loop; end if; return result; end; function all_same(inp: std_logic_vector) return boolean is variable result: boolean; constant width : integer := inp'length; variable vec : std_logic_vector(width-1 downto 0); begin vec := inp; result := true; if width > 0 then for i in 1 to width-1 loop if vec(i) /= vec(0) then result := false; end if; end loop; end if; return result; end; function all_zeros(inp: std_logic_vector) return boolean is constant width : integer := inp'length; variable vec : std_logic_vector(width-1 downto 0); variable zero : std_logic_vector(width-1 downto 0); variable result : boolean; begin zero := (others => '0'); vec := inp; -- synopsys translate_off if (is_XorU(vec)) then return false; end if; -- synopsys translate_on if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(zero)) then result := true; else result := false; end if; return result; end; function is_point_five(inp: std_logic_vector) return boolean is constant width : integer := inp'length; variable vec : std_logic_vector(width-1 downto 0); variable result : boolean; begin vec := inp; -- synopsys translate_off if (is_XorU(vec)) then return false; end if; -- synopsys translate_on if (width > 1) then if ((vec(width-1) = '1') and (all_zeros(vec(width-2 downto 0)) = true)) then result := true; else result := false; end if; else if (vec(width-1) = '1') then result := true; else result := false; end if; end if; return result; end; function all_ones(inp: std_logic_vector) return boolean is constant width : integer := inp'length; variable vec : std_logic_vector(width-1 downto 0); variable one : std_logic_vector(width-1 downto 0); variable result : boolean; begin one := (others => '1'); vec := inp; -- synopsys translate_off if (is_XorU(vec)) then return false; end if; -- synopsys translate_on if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(one)) then result := true; else result := false; end if; return result; end; function full_precision_num_width(quantization, overflow, old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return integer is variable result : integer; begin result := old_width + 2; return result; end; function quantized_num_width(quantization, overflow, old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return integer is variable right_of_dp, left_of_dp, result : integer; begin right_of_dp := max(new_bin_pt, old_bin_pt); left_of_dp := max((new_width - new_bin_pt), (old_width - old_bin_pt)); result := (old_width + 2) + (new_bin_pt - old_bin_pt); return result; end; function convert_type (inp : std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith, quantization, overflow : INTEGER) return std_logic_vector is constant fp_width : integer := full_precision_num_width(quantization, overflow, old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith); constant fp_bin_pt : integer := old_bin_pt; constant fp_arith : integer := old_arith; variable full_precision_result : std_logic_vector(fp_width-1 downto 0); constant q_width : integer := quantized_num_width(quantization, overflow, old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith); constant q_bin_pt : integer := new_bin_pt; constant q_arith : integer := old_arith; variable quantized_result : std_logic_vector(q_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); begin result := (others => '0'); full_precision_result := cast(inp, old_bin_pt, fp_width, fp_bin_pt, fp_arith); if (quantization = xlRound) then quantized_result := round_towards_inf(full_precision_result, fp_width, fp_bin_pt, fp_arith, q_width, q_bin_pt, q_arith); elsif (quantization = xlRoundBanker) then quantized_result := round_towards_even(full_precision_result, fp_width, fp_bin_pt, fp_arith, q_width, q_bin_pt, q_arith); else quantized_result := trunc(full_precision_result, fp_width, fp_bin_pt, fp_arith, q_width, q_bin_pt, q_arith); end if; if (overflow = xlSaturate) then result := saturation_arith(quantized_result, q_width, q_bin_pt, q_arith, new_width, new_bin_pt, new_arith); else result := wrap_arith(quantized_result, q_width, q_bin_pt, q_arith, new_width, new_bin_pt, new_arith); end if; return result; end; function cast (inp : std_logic_vector; old_bin_pt, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector is constant old_width : integer := inp'length; constant left_of_dp : integer := (new_width - new_bin_pt) - (old_width - old_bin_pt); constant right_of_dp : integer := (new_bin_pt - old_bin_pt); variable vec : std_logic_vector(old_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); variable j : integer; begin vec := inp; for i in new_width-1 downto 0 loop j := i - right_of_dp; if ( j > old_width-1) then if (new_arith = xlUnsigned) then result(i) := '0'; else result(i) := vec(old_width-1); end if; elsif ( j >= 0) then result(i) := vec(j); else result(i) := '0'; end if; end loop; return result; end; function shift_division_result(quotient, fraction: std_logic_vector; fraction_width, shift_value, shift_dir: INTEGER) return std_logic_vector is constant q_width : integer := quotient'length; constant f_width : integer := fraction'length; constant vec_MSB : integer := q_width+f_width-1; constant result_MSB : integer := q_width+fraction_width-1; constant result_LSB : integer := vec_MSB-result_MSB; variable vec : std_logic_vector(vec_MSB downto 0); variable result : std_logic_vector(result_MSB downto 0); begin vec := ( quotient & fraction ); if shift_dir = 1 then for i in vec_MSB downto 0 loop if (i < shift_value) then vec(i) := '0'; else vec(i) := vec(i-shift_value); end if; end loop; else for i in 0 to vec_MSB loop if (i > vec_MSB-shift_value) then vec(i) := vec(vec_MSB); else vec(i) := vec(i+shift_value); end if; end loop; end if; result := vec(vec_MSB downto result_LSB); return result; end; function shift_op (inp: std_logic_vector; result_width, shift_value, shift_dir: INTEGER) return std_logic_vector is constant inp_width : integer := inp'length; constant vec_MSB : integer := inp_width-1; constant result_MSB : integer := result_width-1; constant result_LSB : integer := vec_MSB-result_MSB; variable vec : std_logic_vector(vec_MSB downto 0); variable result : std_logic_vector(result_MSB downto 0); begin vec := inp; if shift_dir = 1 then for i in vec_MSB downto 0 loop if (i < shift_value) then vec(i) := '0'; else vec(i) := vec(i-shift_value); end if; end loop; else for i in 0 to vec_MSB loop if (i > vec_MSB-shift_value) then vec(i) := vec(vec_MSB); else vec(i) := vec(i+shift_value); end if; end loop; end if; result := vec(vec_MSB downto result_LSB); return result; end; function vec_slice (inp : std_logic_vector; upper, lower : INTEGER) return std_logic_vector is begin return inp(upper downto lower); end; function s2u_slice (inp : signed; upper, lower : INTEGER) return unsigned is begin return unsigned(vec_slice(std_logic_vector(inp), upper, lower)); end; function u2u_slice (inp : unsigned; upper, lower : INTEGER) return unsigned is begin return unsigned(vec_slice(std_logic_vector(inp), upper, lower)); end; function s2s_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER) return signed is begin return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned)); end; function s2u_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER) return unsigned is begin return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned)); end; function u2s_cast (inp : unsigned; old_bin_pt, new_width, new_bin_pt : INTEGER) return signed is begin return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned)); end; function u2u_cast (inp : unsigned; old_bin_pt, new_width, new_bin_pt : INTEGER) return unsigned is begin return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned)); end; function u2v_cast (inp : unsigned; old_bin_pt, new_width, new_bin_pt : INTEGER) return std_logic_vector is begin return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned); end; function s2v_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER) return std_logic_vector is begin return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned); end; function boolean_to_signed (inp : boolean; width : integer) return signed is variable result : signed(width - 1 downto 0); begin result := (others => '0'); if inp then result(0) := '1'; else result(0) := '0'; end if; return result; end; function boolean_to_unsigned (inp : boolean; width : integer) return unsigned is variable result : unsigned(width - 1 downto 0); begin result := (others => '0'); if inp then result(0) := '1'; else result(0) := '0'; end if; return result; end; function boolean_to_vector (inp : boolean) return std_logic_vector is variable result : std_logic_vector(1 - 1 downto 0); begin result := (others => '0'); if inp then result(0) := '1'; else result(0) := '0'; end if; return result; end; function std_logic_to_vector (inp : std_logic) return std_logic_vector is variable result : std_logic_vector(1 - 1 downto 0); begin result(0) := inp; return result; end; function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector is constant right_of_dp : integer := (old_bin_pt - new_bin_pt); variable vec : std_logic_vector(old_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); begin vec := inp; if right_of_dp >= 0 then if new_arith = xlUnsigned then result := zero_ext(vec(old_width-1 downto right_of_dp), new_width); else result := sign_ext(vec(old_width-1 downto right_of_dp), new_width); end if; else if new_arith = xlUnsigned then result := zero_ext(pad_LSB(vec, old_width + abs(right_of_dp)), new_width); else result := sign_ext(pad_LSB(vec, old_width + abs(right_of_dp)), new_width); end if; end if; return result; end; function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector is constant right_of_dp : integer := (old_bin_pt - new_bin_pt); constant expected_new_width : integer := old_width - right_of_dp + 1; variable vec : std_logic_vector(old_width-1 downto 0); variable one_or_zero : std_logic_vector(new_width-1 downto 0); variable truncated_val : std_logic_vector(new_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); begin vec := inp; if right_of_dp >= 0 then if new_arith = xlUnsigned then truncated_val := zero_ext(vec(old_width-1 downto right_of_dp), new_width); else truncated_val := sign_ext(vec(old_width-1 downto right_of_dp), new_width); end if; else if new_arith = xlUnsigned then truncated_val := zero_ext(pad_LSB(vec, old_width + abs(right_of_dp)), new_width); else truncated_val := sign_ext(pad_LSB(vec, old_width + abs(right_of_dp)), new_width); end if; end if; one_or_zero := (others => '0'); if (new_arith = xlSigned) then if (vec(old_width-1) = '0') then one_or_zero(0) := '1'; end if; if (right_of_dp >= 2) and (right_of_dp <= old_width) then if (all_zeros(vec(right_of_dp-2 downto 0)) = false) then one_or_zero(0) := '1'; end if; end if; if (right_of_dp >= 1) and (right_of_dp <= old_width) then if vec(right_of_dp-1) = '0' then one_or_zero(0) := '0'; end if; else one_or_zero(0) := '0'; end if; else if (right_of_dp >= 1) and (right_of_dp <= old_width) then one_or_zero(0) := vec(right_of_dp-1); end if; end if; if new_arith = xlSigned then result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) + std_logic_vector_to_signed(one_or_zero)); else result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) + std_logic_vector_to_unsigned(one_or_zero)); end if; return result; end; function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector is constant right_of_dp : integer := (old_bin_pt - new_bin_pt); constant expected_new_width : integer := old_width - right_of_dp + 1; variable vec : std_logic_vector(old_width-1 downto 0); variable one_or_zero : std_logic_vector(new_width-1 downto 0); variable truncated_val : std_logic_vector(new_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); begin vec := inp; if right_of_dp >= 0 then if new_arith = xlUnsigned then truncated_val := zero_ext(vec(old_width-1 downto right_of_dp), new_width); else truncated_val := sign_ext(vec(old_width-1 downto right_of_dp), new_width); end if; else if new_arith = xlUnsigned then truncated_val := zero_ext(pad_LSB(vec, old_width + abs(right_of_dp)), new_width); else truncated_val := sign_ext(pad_LSB(vec, old_width + abs(right_of_dp)), new_width); end if; end if; one_or_zero := (others => '0'); if (right_of_dp >= 1) and (right_of_dp <= old_width) then if (is_point_five(vec(right_of_dp-1 downto 0)) = false) then one_or_zero(0) := vec(right_of_dp-1); else one_or_zero(0) := vec(right_of_dp); end if; end if; if new_arith = xlSigned then result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) + std_logic_vector_to_signed(one_or_zero)); else result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) + std_logic_vector_to_unsigned(one_or_zero)); end if; return result; end; function saturation_arith(inp: std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector is constant left_of_dp : integer := (old_width - old_bin_pt) - (new_width - new_bin_pt); variable vec : std_logic_vector(old_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); variable overflow : boolean; begin vec := inp; overflow := true; result := (others => '0'); if (new_width >= old_width) then overflow := false; end if; if ((old_arith = xlSigned and new_arith = xlSigned) and (old_width > new_width)) then if all_same(vec(old_width-1 downto new_width-1)) then overflow := false; end if; end if; if (old_arith = xlSigned and new_arith = xlUnsigned) then if (old_width > new_width) then if all_zeros(vec(old_width-1 downto new_width)) then overflow := false; end if; else if (old_width = new_width) then if (vec(new_width-1) = '0') then overflow := false; end if; end if; end if; end if; if (old_arith = xlUnsigned and new_arith = xlUnsigned) then if (old_width > new_width) then if all_zeros(vec(old_width-1 downto new_width)) then overflow := false; end if; else if (old_width = new_width) then overflow := false; end if; end if; end if; if ((old_arith = xlUnsigned and new_arith = xlSigned) and (old_width > new_width)) then if all_same(vec(old_width-1 downto new_width-1)) then overflow := false; end if; end if; if overflow then if new_arith = xlSigned then if vec(old_width-1) = '0' then result := max_signed(new_width); else result := min_signed(new_width); end if; else if ((old_arith = xlSigned) and vec(old_width-1) = '1') then result := (others => '0'); else result := (others => '1'); end if; end if; else if (old_arith = xlSigned) and (new_arith = xlUnsigned) then if (vec(old_width-1) = '1') then vec := (others => '0'); end if; end if; if new_width <= old_width then result := vec(new_width-1 downto 0); else if new_arith = xlUnsigned then result := zero_ext(vec, new_width); else result := sign_ext(vec, new_width); end if; end if; end if; return result; end; function wrap_arith(inp: std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector is variable result : std_logic_vector(new_width-1 downto 0); variable result_arith : integer; begin if (old_arith = xlSigned) and (new_arith = xlUnsigned) then result_arith := xlSigned; end if; result := cast(inp, old_bin_pt, new_width, new_bin_pt, result_arith); return result; end; function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER is begin return max(a_bin_pt, b_bin_pt); end; function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER) return INTEGER is begin return max(a_width - a_bin_pt, b_width - b_bin_pt); end; function pad_LSB(inp : std_logic_vector; new_width: integer) return STD_LOGIC_VECTOR is constant orig_width : integer := inp'length; variable vec : std_logic_vector(orig_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); variable pos : integer; constant pad_pos : integer := new_width - orig_width - 1; begin vec := inp; pos := new_width-1; if (new_width >= orig_width) then for i in orig_width-1 downto 0 loop result(pos) := vec(i); pos := pos - 1; end loop; if pad_pos >= 0 then for i in pad_pos downto 0 loop result(i) := '0'; end loop; end if; end if; return result; end; function sign_ext(inp : std_logic_vector; new_width : INTEGER) return std_logic_vector is constant old_width : integer := inp'length; variable vec : std_logic_vector(old_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); begin vec := inp; if new_width >= old_width then result(old_width-1 downto 0) := vec; if new_width-1 >= old_width then for i in new_width-1 downto old_width loop result(i) := vec(old_width-1); end loop; end if; else result(new_width-1 downto 0) := vec(new_width-1 downto 0); end if; return result; end; function zero_ext(inp : std_logic_vector; new_width : INTEGER) return std_logic_vector is constant old_width : integer := inp'length; variable vec : std_logic_vector(old_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); begin vec := inp; if new_width >= old_width then result(old_width-1 downto 0) := vec; if new_width-1 >= old_width then for i in new_width-1 downto old_width loop result(i) := '0'; end loop; end if; else result(new_width-1 downto 0) := vec(new_width-1 downto 0); end if; return result; end; function zero_ext(inp : std_logic; new_width : INTEGER) return std_logic_vector is variable result : std_logic_vector(new_width-1 downto 0); begin result(0) := inp; for i in new_width-1 downto 1 loop result(i) := '0'; end loop; return result; end; function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER) return std_logic_vector is constant orig_width : integer := inp'length; variable vec : std_logic_vector(orig_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); begin vec := inp; if arith = xlUnsigned then result := zero_ext(vec, new_width); else result := sign_ext(vec, new_width); end if; return result; end; function pad_LSB(inp : std_logic_vector; new_width, arith: integer) return STD_LOGIC_VECTOR is constant orig_width : integer := inp'length; variable vec : std_logic_vector(orig_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); variable pos : integer; begin vec := inp; pos := new_width-1; if (arith = xlUnsigned) then result(pos) := '0'; pos := pos - 1; else result(pos) := vec(orig_width-1); pos := pos - 1; end if; if (new_width >= orig_width) then for i in orig_width-1 downto 0 loop result(pos) := vec(i); pos := pos - 1; end loop; if pos >= 0 then for i in pos downto 0 loop result(i) := '0'; end loop; end if; end if; return result; end; function align_input(inp : std_logic_vector; old_width, delta, new_arith, new_width: INTEGER) return std_logic_vector is variable vec : std_logic_vector(old_width-1 downto 0); variable padded_inp : std_logic_vector((old_width + delta)-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); begin vec := inp; if delta > 0 then padded_inp := pad_LSB(vec, old_width+delta); result := extend_MSB(padded_inp, new_width, new_arith); else result := extend_MSB(vec, new_width, new_arith); end if; return result; end; function max(L, R: INTEGER) return INTEGER is begin if L > R then return L; else return R; end if; end; function min(L, R: INTEGER) return INTEGER is begin if L < R then return L; else return R; end if; end; function "="(left,right: STRING) return boolean is begin if (left'length /= right'length) then return false; else test : for i in 1 to left'length loop if left(i) /= right(i) then return false; end if; end loop test; return true; end if; end; -- synopsys translate_off function is_binary_string_invalid (inp : string) return boolean is variable vec : string(1 to inp'length); variable result : boolean; begin vec := inp; result := false; for i in 1 to vec'length loop if ( vec(i) = 'X' ) then result := true; end if; end loop; return result; end; function is_binary_string_undefined (inp : string) return boolean is variable vec : string(1 to inp'length); variable result : boolean; begin vec := inp; result := false; for i in 1 to vec'length loop if ( vec(i) = 'U' ) then result := true; end if; end loop; return result; end; function is_XorU(inp : std_logic_vector) return boolean is constant width : integer := inp'length; variable vec : std_logic_vector(width-1 downto 0); variable result : boolean; begin vec := inp; result := false; for i in 0 to width-1 loop if (vec(i) = 'U') or (vec(i) = 'X') then result := true; end if; end loop; return result; end; function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer) return real is variable vec : std_logic_vector(inp'length-1 downto 0); variable result, shift_val, undefined_real : real; variable neg_num : boolean; begin vec := inp; result := 0.0; neg_num := false; if vec(inp'length-1) = '1' then neg_num := true; end if; for i in 0 to inp'length-1 loop if vec(i) = 'U' or vec(i) = 'X' then return undefined_real; end if; if arith = xlSigned then if neg_num then if vec(i) = '0' then result := result + 2.0**i; end if; else if vec(i) = '1' then result := result + 2.0**i; end if; end if; else if vec(i) = '1' then result := result + 2.0**i; end if; end if; end loop; if arith = xlSigned then if neg_num then result := result + 1.0; result := result * (-1.0); end if; end if; shift_val := 2.0**(-1*bin_pt); result := result * shift_val; return result; end; function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer) return real is variable result : real := 0.0; begin if inp = '1' then result := 1.0; end if; if arith = xlSigned then assert false report "It doesn't make sense to convert a 1 bit number to a signed real."; end if; return result; end; -- synopsys translate_on function integer_to_std_logic_vector (inp : integer; width, arith : integer) return std_logic_vector is variable result : std_logic_vector(width-1 downto 0); variable unsigned_val : unsigned(width-1 downto 0); variable signed_val : signed(width-1 downto 0); begin if (arith = xlSigned) then signed_val := to_signed(inp, width); result := signed_to_std_logic_vector(signed_val); else unsigned_val := to_unsigned(inp, width); result := unsigned_to_std_logic_vector(unsigned_val); end if; return result; end; function std_logic_vector_to_integer (inp : std_logic_vector; arith : integer) return integer is constant width : integer := inp'length; variable unsigned_val : unsigned(width-1 downto 0); variable signed_val : signed(width-1 downto 0); variable result : integer; begin if (arith = xlSigned) then signed_val := std_logic_vector_to_signed(inp); result := to_integer(signed_val); else unsigned_val := std_logic_vector_to_unsigned(inp); result := to_integer(unsigned_val); end if; return result; end; function std_logic_to_integer(constant inp : std_logic := '0') return integer is begin if inp = '1' then return 1; else return 0; end if; end; function makeZeroBinStr (width : integer) return STRING is variable result : string(1 to width+3); begin result(1) := '0'; result(2) := 'b'; for i in 3 to width+2 loop result(i) := '0'; end loop; result(width+3) := '.'; return result; end; -- synopsys translate_off function real_string_to_std_logic_vector (inp : string; width, bin_pt, arith : integer) return std_logic_vector is variable result : std_logic_vector(width-1 downto 0); begin result := (others => '0'); return result; end; function real_to_std_logic_vector (inp : real; width, bin_pt, arith : integer) return std_logic_vector is variable real_val : real; variable int_val : integer; variable result : std_logic_vector(width-1 downto 0) := (others => '0'); variable unsigned_val : unsigned(width-1 downto 0) := (others => '0'); variable signed_val : signed(width-1 downto 0) := (others => '0'); begin real_val := inp; int_val := integer(real_val * 2.0**(bin_pt)); if (arith = xlSigned) then signed_val := to_signed(int_val, width); result := signed_to_std_logic_vector(signed_val); else unsigned_val := to_unsigned(int_val, width); result := unsigned_to_std_logic_vector(unsigned_val); end if; return result; end; -- synopsys translate_on function valid_bin_string (inp : string) return boolean is variable vec : string(1 to inp'length); begin vec := inp; if (vec(1) = '0' and vec(2) = 'b') then return true; else return false; end if; end; function hex_string_to_std_logic_vector(inp: string; width : integer) return std_logic_vector is constant strlen : integer := inp'LENGTH; variable result : std_logic_vector(width-1 downto 0); variable bitval : std_logic_vector((strlen*4)-1 downto 0); variable posn : integer; variable ch : character; variable vec : string(1 to strlen); begin vec := inp; result := (others => '0'); posn := (strlen*4)-1; for i in 1 to strlen loop ch := vec(i); case ch is when '0' => bitval(posn downto posn-3) := "0000"; when '1' => bitval(posn downto posn-3) := "0001"; when '2' => bitval(posn downto posn-3) := "0010"; when '3' => bitval(posn downto posn-3) := "0011"; when '4' => bitval(posn downto posn-3) := "0100"; when '5' => bitval(posn downto posn-3) := "0101"; when '6' => bitval(posn downto posn-3) := "0110"; when '7' => bitval(posn downto posn-3) := "0111"; when '8' => bitval(posn downto posn-3) := "1000"; when '9' => bitval(posn downto posn-3) := "1001"; when 'A' | 'a' => bitval(posn downto posn-3) := "1010"; when 'B' | 'b' => bitval(posn downto posn-3) := "1011"; when 'C' | 'c' => bitval(posn downto posn-3) := "1100"; when 'D' | 'd' => bitval(posn downto posn-3) := "1101"; when 'E' | 'e' => bitval(posn downto posn-3) := "1110"; when 'F' | 'f' => bitval(posn downto posn-3) := "1111"; when others => bitval(posn downto posn-3) := "XXXX"; -- synopsys translate_off ASSERT false REPORT "Invalid hex value" SEVERITY ERROR; -- synopsys translate_on end case; posn := posn - 4; end loop; if (width <= strlen*4) then result := bitval(width-1 downto 0); else result((strlen*4)-1 downto 0) := bitval; end if; return result; end; function bin_string_to_std_logic_vector (inp : string) return std_logic_vector is variable pos : integer; variable vec : string(1 to inp'length); variable result : std_logic_vector(inp'length-1 downto 0); begin vec := inp; pos := inp'length-1; result := (others => '0'); for i in 1 to vec'length loop -- synopsys translate_off if (pos < 0) and (vec(i) = '0' or vec(i) = '1' or vec(i) = 'X' or vec(i) = 'U') then assert false report "Input string is larger than output std_logic_vector. Truncating output."; return result; end if; -- synopsys translate_on if vec(i) = '0' then result(pos) := '0'; pos := pos - 1; end if; if vec(i) = '1' then result(pos) := '1'; pos := pos - 1; end if; -- synopsys translate_off if (vec(i) = 'X' or vec(i) = 'U') then result(pos) := 'U'; pos := pos - 1; end if; -- synopsys translate_on end loop; return result; end; function bin_string_element_to_std_logic_vector (inp : string; width, index : integer) return std_logic_vector is constant str_width : integer := width + 4; constant inp_len : integer := inp'length; constant num_elements : integer := (inp_len + 1)/str_width; constant reverse_index : integer := (num_elements-1) - index; variable left_pos : integer; variable right_pos : integer; variable vec : string(1 to inp'length); variable result : std_logic_vector(width-1 downto 0); begin vec := inp; result := (others => '0'); if (reverse_index = 0) and (reverse_index < num_elements) and (inp_len-3 >= width) then left_pos := 1; right_pos := width + 3; result := bin_string_to_std_logic_vector(vec(left_pos to right_pos)); end if; if (reverse_index > 0) and (reverse_index < num_elements) and (inp_len-3 >= width) then left_pos := (reverse_index * str_width) + 1; right_pos := left_pos + width + 2; result := bin_string_to_std_logic_vector(vec(left_pos to right_pos)); end if; return result; end; -- synopsys translate_off function std_logic_vector_to_bin_string(inp : std_logic_vector) return string is variable vec : std_logic_vector(1 to inp'length); variable result : string(vec'range); begin vec := inp; for i in vec'range loop result(i) := to_char(vec(i)); end loop; return result; end; function std_logic_to_bin_string(inp : std_logic) return string is variable result : string(1 to 3); begin result(1) := '0'; result(2) := 'b'; result(3) := to_char(inp); return result; end; function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer) return string is variable width : integer := inp'length; variable vec : std_logic_vector(width-1 downto 0); variable str_pos : integer; variable result : string(1 to width+3); begin vec := inp; str_pos := 1; result(str_pos) := '0'; str_pos := 2; result(str_pos) := 'b'; str_pos := 3; for i in width-1 downto 0 loop if (((width+3) - bin_pt) = str_pos) then result(str_pos) := '.'; str_pos := str_pos + 1; end if; result(str_pos) := to_char(vec(i)); str_pos := str_pos + 1; end loop; if (bin_pt = 0) then result(str_pos) := '.'; end if; return result; end; function real_to_bin_string(inp : real; width, bin_pt, arith : integer) return string is variable result : string(1 to width); variable vec : std_logic_vector(width-1 downto 0); begin vec := real_to_std_logic_vector(inp, width, bin_pt, arith); result := std_logic_vector_to_bin_string(vec); return result; end; function real_to_string (inp : real) return string is variable result : string(1 to display_precision) := (others => ' '); begin result(real'image(inp)'range) := real'image(inp); return result; end; -- synopsys translate_on end conv_pkg; ------------------------------------------------------------------- -- System Generator version 13.2 VHDL source file. -- -- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- -- synopsys translate_off library unisim; use unisim.vcomponents.all; -- synopsys translate_on library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity srl17e is generic (width : integer:=16; latency : integer :=8); port (clk : in std_logic; ce : in std_logic; d : in std_logic_vector(width-1 downto 0); q : out std_logic_vector(width-1 downto 0)); end srl17e; architecture structural of srl17e is component SRL16E port (D : in STD_ULOGIC; CE : in STD_ULOGIC; CLK : in STD_ULOGIC; A0 : in STD_ULOGIC; A1 : in STD_ULOGIC; A2 : in STD_ULOGIC; A3 : in STD_ULOGIC; Q : out STD_ULOGIC); end component; attribute syn_black_box of SRL16E : component is true; attribute fpga_dont_touch of SRL16E : component is "true"; component FDE port( Q : out STD_ULOGIC; D : in STD_ULOGIC; C : in STD_ULOGIC; CE : in STD_ULOGIC); end component; attribute syn_black_box of FDE : component is true; attribute fpga_dont_touch of FDE : component is "true"; constant a : std_logic_vector(4 downto 0) := integer_to_std_logic_vector(latency-2,5,xlSigned); signal d_delayed : std_logic_vector(width-1 downto 0); signal srl16_out : std_logic_vector(width-1 downto 0); begin d_delayed <= d after 200 ps; reg_array : for i in 0 to width-1 generate srl16_used: if latency > 1 generate u1 : srl16e port map(clk => clk, d => d_delayed(i), q => srl16_out(i), ce => ce, a0 => a(0), a1 => a(1), a2 => a(2), a3 => a(3)); end generate; srl16_not_used: if latency <= 1 generate srl16_out(i) <= d_delayed(i); end generate; fde_used: if latency /= 0 generate u2 : fde port map(c => clk, d => srl16_out(i), q => q(i), ce => ce); end generate; fde_not_used: if latency = 0 generate q(i) <= srl16_out(i); end generate; end generate; end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity synth_reg is generic (width : integer := 8; latency : integer := 1); port (i : in std_logic_vector(width-1 downto 0); ce : in std_logic; clr : in std_logic; clk : in std_logic; o : out std_logic_vector(width-1 downto 0)); end synth_reg; architecture structural of synth_reg is component srl17e generic (width : integer:=16; latency : integer :=8); port (clk : in std_logic; ce : in std_logic; d : in std_logic_vector(width-1 downto 0); q : out std_logic_vector(width-1 downto 0)); end component; function calc_num_srl17es (latency : integer) return integer is variable remaining_latency : integer; variable result : integer; begin result := latency / 17; remaining_latency := latency - (result * 17); if (remaining_latency /= 0) then result := result + 1; end if; return result; end; constant complete_num_srl17es : integer := latency / 17; constant num_srl17es : integer := calc_num_srl17es(latency); constant remaining_latency : integer := latency - (complete_num_srl17es * 17); type register_array is array (num_srl17es downto 0) of std_logic_vector(width-1 downto 0); signal z : register_array; begin z(0) <= i; complete_ones : if complete_num_srl17es > 0 generate srl17e_array: for i in 0 to complete_num_srl17es-1 generate delay_comp : srl17e generic map (width => width, latency => 17) port map (clk => clk, ce => ce, d => z(i), q => z(i+1)); end generate; end generate; partial_one : if remaining_latency > 0 generate last_srl17e : srl17e generic map (width => width, latency => remaining_latency) port map (clk => clk, ce => ce, d => z(num_srl17es-1), q => z(num_srl17es)); end generate; o <= z(num_srl17es); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity synth_reg_reg is generic (width : integer := 8; latency : integer := 1); port (i : in std_logic_vector(width-1 downto 0); ce : in std_logic; clr : in std_logic; clk : in std_logic; o : out std_logic_vector(width-1 downto 0)); end synth_reg_reg; architecture behav of synth_reg_reg is type reg_array_type is array (latency-1 downto 0) of std_logic_vector(width -1 downto 0); signal reg_bank : reg_array_type := (others => (others => '0')); signal reg_bank_in : reg_array_type := (others => (others => '0')); attribute syn_allow_retiming : boolean; attribute syn_srlstyle : string; attribute syn_allow_retiming of reg_bank : signal is true; attribute syn_allow_retiming of reg_bank_in : signal is true; attribute syn_srlstyle of reg_bank : signal is "registers"; attribute syn_srlstyle of reg_bank_in : signal is "registers"; begin latency_eq_0: if latency = 0 generate o <= i; end generate latency_eq_0; latency_gt_0: if latency >= 1 generate o <= reg_bank(latency-1); reg_bank_in(0) <= i; loop_gen: for idx in latency-2 downto 0 generate reg_bank_in(idx+1) <= reg_bank(idx); end generate loop_gen; sync_loop: for sync_idx in latency-1 downto 0 generate sync_proc: process (clk) begin if clk'event and clk = '1' then if clr = '1' then reg_bank_in <= (others => (others => '0')); elsif ce = '1' then reg_bank(sync_idx) <= reg_bank_in(sync_idx); end if; end if; end process sync_proc; end generate sync_loop; end generate latency_gt_0; end behav; ------------------------------------------------------------------- -- System Generator version 13.2 VHDL source file. -- -- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- -- synopsys translate_off library unisim; use unisim.vcomponents.all; -- synopsys translate_on library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity single_reg_w_init is generic ( width: integer := 8; init_index: integer := 0; init_value: bit_vector := b"0000" ); port ( i: in std_logic_vector(width - 1 downto 0); ce: in std_logic; clr: in std_logic; clk: in std_logic; o: out std_logic_vector(width - 1 downto 0) ); end single_reg_w_init; architecture structural of single_reg_w_init is function build_init_const(width: integer; init_index: integer; init_value: bit_vector) return std_logic_vector is variable result: std_logic_vector(width - 1 downto 0); begin if init_index = 0 then result := (others => '0'); elsif init_index = 1 then result := (others => '0'); result(0) := '1'; else result := to_stdlogicvector(init_value); end if; return result; end; component fdre port ( q: out std_ulogic; d: in std_ulogic; c: in std_ulogic; ce: in std_ulogic; r: in std_ulogic ); end component; attribute syn_black_box of fdre: component is true; attribute fpga_dont_touch of fdre: component is "true"; component fdse port ( q: out std_ulogic; d: in std_ulogic; c: in std_ulogic; ce: in std_ulogic; s: in std_ulogic ); end component; attribute syn_black_box of fdse: component is true; attribute fpga_dont_touch of fdse: component is "true"; constant init_const: std_logic_vector(width - 1 downto 0) := build_init_const(width, init_index, init_value); begin fd_prim_array: for index in 0 to width - 1 generate bit_is_0: if (init_const(index) = '0') generate fdre_comp: fdre port map ( c => clk, d => i(index), q => o(index), ce => ce, r => clr ); end generate; bit_is_1: if (init_const(index) = '1') generate fdse_comp: fdse port map ( c => clk, d => i(index), q => o(index), ce => ce, s => clr ); end generate; end generate; end architecture structural; -- synopsys translate_off library unisim; use unisim.vcomponents.all; -- synopsys translate_on library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity synth_reg_w_init is generic ( width: integer := 8; init_index: integer := 0; init_value: bit_vector := b"0000"; latency: integer := 1 ); port ( i: in std_logic_vector(width - 1 downto 0); ce: in std_logic; clr: in std_logic; clk: in std_logic; o: out std_logic_vector(width - 1 downto 0) ); end synth_reg_w_init; architecture structural of synth_reg_w_init is component single_reg_w_init generic ( width: integer := 8; init_index: integer := 0; init_value: bit_vector := b"0000" ); port ( i: in std_logic_vector(width - 1 downto 0); ce: in std_logic; clr: in std_logic; clk: in std_logic; o: out std_logic_vector(width - 1 downto 0) ); end component; signal dly_i: std_logic_vector((latency + 1) * width - 1 downto 0); signal dly_clr: std_logic; begin latency_eq_0: if (latency = 0) generate o <= i; end generate; latency_gt_0: if (latency >= 1) generate dly_i((latency + 1) * width - 1 downto latency * width) <= i after 200 ps; dly_clr <= clr after 200 ps; fd_array: for index in latency downto 1 generate reg_comp: single_reg_w_init generic map ( width => width, init_index => init_index, init_value => init_value ) port map ( clk => clk, i => dly_i((index + 1) * width - 1 downto index * width), o => dly_i(index * width - 1 downto (index - 1) * width), ce => ce, clr => dly_clr ); end generate; o <= dly_i(width - 1 downto 0); end generate; end structural; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity constant_963ed6358a is port ( op : out std_logic_vector((1 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end constant_963ed6358a; architecture behavior of constant_963ed6358a is begin op <= "0"; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity mcode_block_f4d0462e0e is port ( plbrst : in std_logic_vector((1 - 1) downto 0); plbabus : in std_logic_vector((32 - 1) downto 0); plbpavalid : in std_logic_vector((1 - 1) downto 0); plbrnw : in std_logic_vector((1 - 1) downto 0); plbwrdbus : in std_logic_vector((32 - 1) downto 0); rddata : in std_logic_vector((32 - 1) downto 0); addrpref : in std_logic_vector((20 - 1) downto 0); wrdbusreg : out std_logic_vector((32 - 1) downto 0); addrack : out std_logic_vector((1 - 1) downto 0); rdcomp : out std_logic_vector((1 - 1) downto 0); wrdack : out std_logic_vector((1 - 1) downto 0); bankaddr : out std_logic_vector((2 - 1) downto 0); rnwreg : out std_logic_vector((1 - 1) downto 0); rddack : out std_logic_vector((1 - 1) downto 0); rddbus : out std_logic_vector((32 - 1) downto 0); linearaddr : out std_logic_vector((8 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end mcode_block_f4d0462e0e; architecture behavior of mcode_block_f4d0462e0e is signal plbrst_1_110: unsigned((1 - 1) downto 0); signal plbabus_1_118: unsigned((32 - 1) downto 0); signal plbpavalid_1_127: unsigned((1 - 1) downto 0); signal plbrnw_1_139: unsigned((1 - 1) downto 0); signal plbwrdbus_1_147: unsigned((32 - 1) downto 0); signal rddata_1_158: unsigned((32 - 1) downto 0); signal addrpref_1_166: unsigned((20 - 1) downto 0); signal plbrstreg_12_24_next: boolean; signal plbrstreg_12_24: boolean := false; signal plbabusreg_13_25_next: unsigned((32 - 1) downto 0); signal plbabusreg_13_25: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000"; signal plbpavalidreg_14_28_next: boolean; signal plbpavalidreg_14_28: boolean := false; signal plbrnwreg_15_24_next: unsigned((1 - 1) downto 0); signal plbrnwreg_15_24: unsigned((1 - 1) downto 0) := "0"; signal plbwrdbusreg_16_27_next: unsigned((32 - 1) downto 0); signal plbwrdbusreg_16_27: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000"; signal avalidreg_28_23_next: boolean; signal avalidreg_28_23: boolean := false; signal ps1reg_39_20_next: boolean; signal ps1reg_39_20: boolean := false; signal psreg_47_19_next: boolean; signal psreg_47_19: boolean := false; type array_type_rdcompdelay_58_25 is array (0 to (3 - 1)) of unsigned((1 - 1) downto 0); signal rdcompdelay_58_25: array_type_rdcompdelay_58_25 := ( "0", "0", "0"); signal rdcompdelay_58_25_front_din: unsigned((1 - 1) downto 0); signal rdcompdelay_58_25_back: unsigned((1 - 1) downto 0); signal rdcompdelay_58_25_push_front_pop_back_en: std_logic; signal rdcompreg_62_23_next: unsigned((1 - 1) downto 0); signal rdcompreg_62_23: unsigned((1 - 1) downto 0) := "0"; signal rddackreg_66_23_next: unsigned((1 - 1) downto 0); signal rddackreg_66_23: unsigned((1 - 1) downto 0) := "0"; signal wrdackreg_70_23_next: unsigned((1 - 1) downto 0); signal wrdackreg_70_23: unsigned((1 - 1) downto 0) := "0"; signal rddbusreg_84_23_next: unsigned((32 - 1) downto 0); signal rddbusreg_84_23: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000"; signal bankaddr_20_1_slice: unsigned((2 - 1) downto 0); signal linearaddr_21_1_slice: unsigned((8 - 1) downto 0); signal addrpref_in_32_1_slice: unsigned((20 - 1) downto 0); signal rel_33_4: boolean; signal ps1_join_33_1: boolean; signal ps_42_1_bit: boolean; signal bitnot_49_49: boolean; signal bitnot_49_73: boolean; signal bit_49_49: boolean; signal addrack_49_1_convert: unsigned((1 - 1) downto 0); signal bit_55_43: unsigned((1 - 1) downto 0); signal bitnot_72_35: unsigned((1 - 1) downto 0); signal wrdackreg_72_1_bit: unsigned((1 - 1) downto 0); signal rdsel_76_1_bit: unsigned((1 - 1) downto 0); signal rel_78_4: boolean; signal rddbus1_join_78_1: unsigned((32 - 1) downto 0); signal plbwrdbusreg_97_1_slice: unsigned((32 - 1) downto 0); signal plbrstreg_12_24_next_x_000000: boolean; signal plbpavalidreg_14_28_next_x_000000: boolean; begin plbrst_1_110 <= std_logic_vector_to_unsigned(plbrst); plbabus_1_118 <= std_logic_vector_to_unsigned(plbabus); plbpavalid_1_127 <= std_logic_vector_to_unsigned(plbpavalid); plbrnw_1_139 <= std_logic_vector_to_unsigned(plbrnw); plbwrdbus_1_147 <= std_logic_vector_to_unsigned(plbwrdbus); rddata_1_158 <= std_logic_vector_to_unsigned(rddata); addrpref_1_166 <= std_logic_vector_to_unsigned(addrpref); proc_plbrstreg_12_24: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then plbrstreg_12_24 <= plbrstreg_12_24_next; end if; end if; end process proc_plbrstreg_12_24; proc_plbabusreg_13_25: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then plbabusreg_13_25 <= plbabusreg_13_25_next; end if; end if; end process proc_plbabusreg_13_25; proc_plbpavalidreg_14_28: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then plbpavalidreg_14_28 <= plbpavalidreg_14_28_next; end if; end if; end process proc_plbpavalidreg_14_28; proc_plbrnwreg_15_24: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then plbrnwreg_15_24 <= plbrnwreg_15_24_next; end if; end if; end process proc_plbrnwreg_15_24; proc_plbwrdbusreg_16_27: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then plbwrdbusreg_16_27 <= plbwrdbusreg_16_27_next; end if; end if; end process proc_plbwrdbusreg_16_27; proc_avalidreg_28_23: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then avalidreg_28_23 <= avalidreg_28_23_next; end if; end if; end process proc_avalidreg_28_23; proc_ps1reg_39_20: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then ps1reg_39_20 <= ps1reg_39_20_next; end if; end if; end process proc_ps1reg_39_20; proc_psreg_47_19: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then psreg_47_19 <= psreg_47_19_next; end if; end if; end process proc_psreg_47_19; rdcompdelay_58_25_back <= rdcompdelay_58_25(2); proc_rdcompdelay_58_25: process (clk) is variable i: integer; begin if (clk'event and (clk = '1')) then if ((ce = '1') and (rdcompdelay_58_25_push_front_pop_back_en = '1')) then for i in 2 downto 1 loop rdcompdelay_58_25(i) <= rdcompdelay_58_25(i-1); end loop; rdcompdelay_58_25(0) <= rdcompdelay_58_25_front_din; end if; end if; end process proc_rdcompdelay_58_25; proc_rdcompreg_62_23: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then rdcompreg_62_23 <= rdcompreg_62_23_next; end if; end if; end process proc_rdcompreg_62_23; proc_rddackreg_66_23: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then rddackreg_66_23 <= rddackreg_66_23_next; end if; end if; end process proc_rddackreg_66_23; proc_wrdackreg_70_23: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then wrdackreg_70_23 <= wrdackreg_70_23_next; end if; end if; end process proc_wrdackreg_70_23; proc_rddbusreg_84_23: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then rddbusreg_84_23 <= rddbusreg_84_23_next; end if; end if; end process proc_rddbusreg_84_23; bankaddr_20_1_slice <= u2u_slice(plbabusreg_13_25, 11, 10); linearaddr_21_1_slice <= u2u_slice(plbabusreg_13_25, 9, 2); addrpref_in_32_1_slice <= u2u_slice(plbabusreg_13_25, 31, 12); rel_33_4 <= addrpref_in_32_1_slice = addrpref_1_166; proc_if_33_1: process (rel_33_4) is begin if rel_33_4 then ps1_join_33_1 <= true; else ps1_join_33_1 <= false; end if; end process proc_if_33_1; ps_42_1_bit <= ((boolean_to_vector(ps1_join_33_1) and boolean_to_vector(plbpavalidreg_14_28)) = "1"); bitnot_49_49 <= ((not boolean_to_vector(plbrstreg_12_24)) = "1"); bitnot_49_73 <= ((not boolean_to_vector(psreg_47_19)) = "1"); bit_49_49 <= ((boolean_to_vector(bitnot_49_49) and boolean_to_vector(ps_42_1_bit) and boolean_to_vector(bitnot_49_73)) = "1"); addrack_49_1_convert <= u2u_cast(std_logic_vector_to_unsigned(boolean_to_vector(bit_49_49)), 0, 1, 0); bit_55_43 <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(addrack_49_1_convert) and unsigned_to_std_logic_vector(plbrnwreg_15_24)); bitnot_72_35 <= std_logic_vector_to_unsigned(not unsigned_to_std_logic_vector(plbrnwreg_15_24)); wrdackreg_72_1_bit <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(addrack_49_1_convert) and unsigned_to_std_logic_vector(bitnot_72_35)); rdsel_76_1_bit <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(rdcompdelay_58_25_back) or unsigned_to_std_logic_vector(rdcompreg_62_23)); rel_78_4 <= rdsel_76_1_bit = std_logic_vector_to_unsigned("1"); proc_if_78_1: process (rddata_1_158, rel_78_4) is begin if rel_78_4 then rddbus1_join_78_1 <= rddata_1_158; else rddbus1_join_78_1 <= std_logic_vector_to_unsigned("00000000000000000000000000000000"); end if; end process proc_if_78_1; plbwrdbusreg_97_1_slice <= u2u_slice(plbwrdbus_1_147, 31, 0); plbrstreg_12_24_next_x_000000 <= (plbrst_1_110 /= "0"); plbrstreg_12_24_next <= plbrstreg_12_24_next_x_000000; plbabusreg_13_25_next <= plbabus_1_118; plbpavalidreg_14_28_next_x_000000 <= (plbpavalid_1_127 /= "0"); plbpavalidreg_14_28_next <= plbpavalidreg_14_28_next_x_000000; plbrnwreg_15_24_next <= plbrnw_1_139; plbwrdbusreg_16_27_next <= plbwrdbusreg_97_1_slice; avalidreg_28_23_next <= plbpavalidreg_14_28; ps1reg_39_20_next <= ps1_join_33_1; psreg_47_19_next <= ps_42_1_bit; rdcompdelay_58_25_front_din <= bit_55_43; rdcompdelay_58_25_push_front_pop_back_en <= '1'; rdcompreg_62_23_next <= rdcompdelay_58_25_back; rddackreg_66_23_next <= rdcompreg_62_23; wrdackreg_70_23_next <= wrdackreg_72_1_bit; rddbusreg_84_23_next <= rddbus1_join_78_1; wrdbusreg <= unsigned_to_std_logic_vector(plbwrdbusreg_16_27); addrack <= unsigned_to_std_logic_vector(addrack_49_1_convert); rdcomp <= unsigned_to_std_logic_vector(rdcompreg_62_23); wrdack <= unsigned_to_std_logic_vector(wrdackreg_70_23); bankaddr <= unsigned_to_std_logic_vector(bankaddr_20_1_slice); rnwreg <= unsigned_to_std_logic_vector(plbrnwreg_15_24); rddack <= unsigned_to_std_logic_vector(rddackreg_66_23); rddbus <= unsigned_to_std_logic_vector(rddbusreg_84_23); linearaddr <= unsigned_to_std_logic_vector(linearaddr_21_1_slice); end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity mcode_block_2c4e41848b is port ( wrdbus : in std_logic_vector((32 - 1) downto 0); bankaddr : in std_logic_vector((2 - 1) downto 0); linearaddr : in std_logic_vector((8 - 1) downto 0); rnwreg : in std_logic_vector((1 - 1) downto 0); addrack : in std_logic_vector((1 - 1) downto 0); sm_bayer_ctrl : in std_logic_vector((32 - 1) downto 0); read_bank_out : out std_logic_vector((32 - 1) downto 0); sm_bayer_ctrl_din : out std_logic_vector((32 - 1) downto 0); sm_bayer_ctrl_en : out std_logic_vector((1 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end mcode_block_2c4e41848b; architecture behavior of mcode_block_2c4e41848b is signal wrdbus_1_76: unsigned((32 - 1) downto 0); signal bankaddr_1_84: unsigned((2 - 1) downto 0); signal linearaddr_1_94: unsigned((8 - 1) downto 0); signal rnwreg_1_106: unsigned((1 - 1) downto 0); signal addrack_1_114: unsigned((1 - 1) downto 0); signal sm_bayer_ctrl_1_123: unsigned((32 - 1) downto 0); signal reg_bank_out_reg_19_30_next: unsigned((32 - 1) downto 0); signal reg_bank_out_reg_19_30: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000"; signal read_bank_out_reg_72_31_next: unsigned((32 - 1) downto 0); signal read_bank_out_reg_72_31: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000"; signal bankaddr_reg_75_26_next: unsigned((2 - 1) downto 0); signal bankaddr_reg_75_26: unsigned((2 - 1) downto 0) := "00"; signal opcode_31_1_concat: unsigned((12 - 1) downto 0); signal rel_52_4: boolean; signal sm_bayer_ctrl_en_join_52_1: boolean; signal slice_67_38: unsigned((32 - 1) downto 0); signal rel_77_4: boolean; signal rel_80_8: boolean; signal rel_83_8: boolean; signal rel_86_8: boolean; signal read_bank_out_reg_join_77_1: unsigned((32 - 1) downto 0); begin wrdbus_1_76 <= std_logic_vector_to_unsigned(wrdbus); bankaddr_1_84 <= std_logic_vector_to_unsigned(bankaddr); linearaddr_1_94 <= std_logic_vector_to_unsigned(linearaddr); rnwreg_1_106 <= std_logic_vector_to_unsigned(rnwreg); addrack_1_114 <= std_logic_vector_to_unsigned(addrack); sm_bayer_ctrl_1_123 <= std_logic_vector_to_unsigned(sm_bayer_ctrl); proc_reg_bank_out_reg_19_30: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then reg_bank_out_reg_19_30 <= reg_bank_out_reg_19_30_next; end if; end if; end process proc_reg_bank_out_reg_19_30; proc_read_bank_out_reg_72_31: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then read_bank_out_reg_72_31 <= read_bank_out_reg_72_31_next; end if; end if; end process proc_read_bank_out_reg_72_31; proc_bankaddr_reg_75_26: process (clk) is begin if (clk'event and (clk = '1')) then if (ce = '1') then bankaddr_reg_75_26 <= bankaddr_reg_75_26_next; end if; end if; end process proc_bankaddr_reg_75_26; opcode_31_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(addrack_1_114) & unsigned_to_std_logic_vector(rnwreg_1_106) & unsigned_to_std_logic_vector(bankaddr_1_84) & unsigned_to_std_logic_vector(linearaddr_1_94)); rel_52_4 <= opcode_31_1_concat = std_logic_vector_to_unsigned("101000000000"); proc_if_52_1: process (rel_52_4) is begin if rel_52_4 then sm_bayer_ctrl_en_join_52_1 <= true; else sm_bayer_ctrl_en_join_52_1 <= false; end if; end process proc_if_52_1; slice_67_38 <= u2u_slice(wrdbus_1_76, 31, 0); rel_77_4 <= bankaddr_reg_75_26 = std_logic_vector_to_unsigned("00"); rel_80_8 <= bankaddr_reg_75_26 = std_logic_vector_to_unsigned("01"); rel_83_8 <= bankaddr_reg_75_26 = std_logic_vector_to_unsigned("10"); rel_86_8 <= bankaddr_reg_75_26 = std_logic_vector_to_unsigned("11"); proc_if_77_1: process (read_bank_out_reg_72_31, reg_bank_out_reg_19_30, rel_77_4, rel_80_8, rel_83_8, rel_86_8) is begin if rel_77_4 then read_bank_out_reg_join_77_1 <= std_logic_vector_to_unsigned("00000000000000000000000000000000"); elsif rel_80_8 then read_bank_out_reg_join_77_1 <= std_logic_vector_to_unsigned("00000000000000000000000000000000"); elsif rel_83_8 then read_bank_out_reg_join_77_1 <= reg_bank_out_reg_19_30; elsif rel_86_8 then read_bank_out_reg_join_77_1 <= std_logic_vector_to_unsigned("00000000000000000000000000000000"); else read_bank_out_reg_join_77_1 <= read_bank_out_reg_72_31; end if; end process proc_if_77_1; reg_bank_out_reg_19_30_next <= sm_bayer_ctrl_1_123; read_bank_out_reg_72_31_next <= read_bank_out_reg_join_77_1; bankaddr_reg_75_26_next <= bankaddr_1_84; read_bank_out <= unsigned_to_std_logic_vector(read_bank_out_reg_72_31); sm_bayer_ctrl_din <= unsigned_to_std_logic_vector(slice_67_38); sm_bayer_ctrl_en <= boolean_to_vector(sm_bayer_ctrl_en_join_52_1); end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity mux_1a0db76efe is port ( sel : in std_logic_vector((2 - 1) downto 0); d0 : in std_logic_vector((2 - 1) downto 0); d1 : in std_logic_vector((2 - 1) downto 0); d2 : in std_logic_vector((2 - 1) downto 0); d3 : in std_logic_vector((2 - 1) downto 0); y : out std_logic_vector((2 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end mux_1a0db76efe; architecture behavior of mux_1a0db76efe is signal sel_1_20: std_logic_vector((2 - 1) downto 0); signal d0_1_24: std_logic_vector((2 - 1) downto 0); signal d1_1_27: std_logic_vector((2 - 1) downto 0); signal d2_1_30: std_logic_vector((2 - 1) downto 0); signal d3_1_33: std_logic_vector((2 - 1) downto 0); signal unregy_join_6_1: std_logic_vector((2 - 1) downto 0); begin sel_1_20 <= sel; d0_1_24 <= d0; d1_1_27 <= d1; d2_1_30 <= d2; d3_1_33 <= d3; proc_switch_6_1: process (d0_1_24, d1_1_27, d2_1_30, d3_1_33, sel_1_20) is begin case sel_1_20 is when "00" => unregy_join_6_1 <= d0_1_24; when "01" => unregy_join_6_1 <= d1_1_27; when "10" => unregy_join_6_1 <= d2_1_30; when others => unregy_join_6_1 <= d3_1_33; end case; end process proc_switch_6_1; y <= unregy_join_6_1; end behavior; ------------------------------------------------------------------- -- System Generator version 13.2 VHDL source file. -- -- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use work.conv_pkg.all; entity xlslice is generic ( new_msb : integer := 9; new_lsb : integer := 1; x_width : integer := 16; y_width : integer := 8); port ( x : in std_logic_vector (x_width-1 downto 0); y : out std_logic_vector (y_width-1 downto 0)); end xlslice; architecture behavior of xlslice is begin y <= x(new_msb downto new_lsb); end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity delay_5753e4c658 is port ( d : in std_logic_vector((1 - 1) downto 0); q : out std_logic_vector((1 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end delay_5753e4c658; architecture behavior of delay_5753e4c658 is signal d_1_22: std_logic_vector((1 - 1) downto 0); type array_type_op_mem_20_24 is array (0 to (1 - 1)) of std_logic_vector((1 - 1) downto 0); signal op_mem_20_24: array_type_op_mem_20_24 := ( 0 => "0"); signal op_mem_20_24_front_din: std_logic_vector((1 - 1) downto 0); signal op_mem_20_24_back: std_logic_vector((1 - 1) downto 0); signal op_mem_20_24_push_front_pop_back_en: std_logic; begin d_1_22 <= d; op_mem_20_24_back <= op_mem_20_24(0); proc_op_mem_20_24: process (clk) is variable i: integer; begin if (clk'event and (clk = '1')) then if ((ce = '1') and (op_mem_20_24_push_front_pop_back_en = '1')) then op_mem_20_24(0) <= op_mem_20_24_front_din; end if; end if; end process proc_op_mem_20_24; op_mem_20_24_front_din <= d_1_22; op_mem_20_24_push_front_pop_back_en <= '1'; q <= op_mem_20_24_back; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity delay_a3ccf865c7 is port ( d : in std_logic_vector((1 - 1) downto 0); en : in std_logic_vector((1 - 1) downto 0); q : out std_logic_vector((1 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end delay_a3ccf865c7; architecture behavior of delay_a3ccf865c7 is signal d_1_22: std_logic_vector((1 - 1) downto 0); signal en_1_25: std_logic; type array_type_op_mem_20_24 is array (0 to (1 - 1)) of std_logic_vector((1 - 1) downto 0); signal op_mem_20_24: array_type_op_mem_20_24 := ( 0 => "0"); signal op_mem_20_24_front_din: std_logic_vector((1 - 1) downto 0); signal op_mem_20_24_back: std_logic_vector((1 - 1) downto 0); signal op_mem_20_24_push_front_pop_back_en: std_logic; signal op_mem_shift_join_27_9: std_logic_vector((1 - 1) downto 0); signal op_mem_shift_join_27_9_en: std_logic; begin d_1_22 <= d; en_1_25 <= en(0); op_mem_20_24_back <= op_mem_20_24(0); proc_op_mem_20_24: process (clk) is variable i: integer; begin if (clk'event and (clk = '1')) then if ((ce = '1') and (op_mem_20_24_push_front_pop_back_en = '1')) then op_mem_20_24(0) <= op_mem_20_24_front_din; end if; end if; end process proc_op_mem_20_24; proc_if_27_9: process (d_1_22, en_1_25) is begin if en_1_25 = '1' then op_mem_shift_join_27_9_en <= '1'; else op_mem_shift_join_27_9_en <= '0'; end if; op_mem_shift_join_27_9 <= d_1_22; end process proc_if_27_9; op_mem_20_24_front_din <= op_mem_shift_join_27_9; op_mem_20_24_push_front_pop_back_en <= op_mem_shift_join_27_9_en; q <= op_mem_20_24_back; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity expr_332f1d2335 is port ( d0 : in std_logic_vector((1 - 1) downto 0); d1 : in std_logic_vector((1 - 1) downto 0); dout : out std_logic_vector((1 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end expr_332f1d2335; architecture behavior of expr_332f1d2335 is signal d0_1_24: unsigned((1 - 1) downto 0); signal d1_1_28: unsigned((1 - 1) downto 0); signal bitnot_5_36: unsigned((1 - 1) downto 0); signal fulldout_5_2_bit: unsigned((1 - 1) downto 0); begin d0_1_24 <= std_logic_vector_to_unsigned(d0); d1_1_28 <= std_logic_vector_to_unsigned(d1); bitnot_5_36 <= std_logic_vector_to_unsigned(not unsigned_to_std_logic_vector(d0_1_24)); fulldout_5_2_bit <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(d1_1_28) and unsigned_to_std_logic_vector(bitnot_5_36)); dout <= unsigned_to_std_logic_vector(fulldout_5_2_bit); end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity expr_3c2515cf08 is port ( a : in std_logic_vector((1 - 1) downto 0); b : in std_logic_vector((1 - 1) downto 0); dout : out std_logic_vector((1 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end expr_3c2515cf08; architecture behavior of expr_3c2515cf08 is signal a_1_24: boolean; signal b_1_27: boolean; signal fulldout_5_2_bit: boolean; begin a_1_24 <= ((a) = "1"); b_1_27 <= ((b) = "1"); fulldout_5_2_bit <= ((boolean_to_vector(b_1_27) and boolean_to_vector(a_1_24)) = "1"); dout <= boolean_to_vector(fulldout_5_2_bit); end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity inverter_e5b38cca3b is port ( ip : in std_logic_vector((1 - 1) downto 0); op : out std_logic_vector((1 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end inverter_e5b38cca3b; architecture behavior of inverter_e5b38cca3b is signal ip_1_26: boolean; type array_type_op_mem_22_20 is array (0 to (1 - 1)) of boolean; signal op_mem_22_20: array_type_op_mem_22_20 := ( 0 => false); signal op_mem_22_20_front_din: boolean; signal op_mem_22_20_back: boolean; signal op_mem_22_20_push_front_pop_back_en: std_logic; signal internal_ip_12_1_bitnot: boolean; begin ip_1_26 <= ((ip) = "1"); op_mem_22_20_back <= op_mem_22_20(0); proc_op_mem_22_20: process (clk) is variable i: integer; begin if (clk'event and (clk = '1')) then if ((ce = '1') and (op_mem_22_20_push_front_pop_back_en = '1')) then op_mem_22_20(0) <= op_mem_22_20_front_din; end if; end if; end process proc_op_mem_22_20; internal_ip_12_1_bitnot <= ((not boolean_to_vector(ip_1_26)) = "1"); op_mem_22_20_push_front_pop_back_en <= '0'; op <= boolean_to_vector(internal_ip_12_1_bitnot); end behavior; ------------------------------------------------------------------- -- System Generator version 13.2 VHDL source file. -- -- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- -- synopsys translate_off library XilinxCoreLib; -- synopsys translate_on library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity xlcounter_free is generic ( core_name0: string := ""; op_width: integer := 5; op_arith: integer := xlSigned ); port ( ce: in std_logic; clr: in std_logic; clk: in std_logic; op: out std_logic_vector(op_width - 1 downto 0); up: in std_logic_vector(0 downto 0) := (others => '0'); load: in std_logic_vector(0 downto 0) := (others => '0'); din: in std_logic_vector(op_width - 1 downto 0) := (others => '0'); en: in std_logic_vector(0 downto 0); rst: in std_logic_vector(0 downto 0) ); end xlcounter_free ; architecture behavior of xlcounter_free is component cntr_11_0_3eb0c8dcd9c22b4d port ( clk: in std_logic; ce: in std_logic; SINIT: in std_logic; q: out std_logic_vector(op_width - 1 downto 0) ); end component; attribute syn_black_box of cntr_11_0_3eb0c8dcd9c22b4d: component is true; attribute fpga_dont_touch of cntr_11_0_3eb0c8dcd9c22b4d: component is "true"; attribute box_type of cntr_11_0_3eb0c8dcd9c22b4d: component is "black_box"; -- synopsys translate_off constant zeroVec: std_logic_vector(op_width - 1 downto 0) := (others => '0'); constant oneVec: std_logic_vector(op_width - 1 downto 0) := (others => '1'); constant zeroStr: string(1 to op_width) := std_logic_vector_to_bin_string(zeroVec); constant oneStr: string(1 to op_width) := std_logic_vector_to_bin_string(oneVec); -- synopsys translate_on signal core_sinit: std_logic; signal core_ce: std_logic; signal op_net: std_logic_vector(op_width - 1 downto 0); begin core_ce <= ce and en(0); core_sinit <= (clr or rst(0)) and ce; op <= op_net; comp0: if ((core_name0 = "cntr_11_0_3eb0c8dcd9c22b4d")) generate core_instance0: cntr_11_0_3eb0c8dcd9c22b4d port map ( clk => clk, ce => core_ce, SINIT => core_sinit, q => op_net ); end generate; end behavior; ------------------------------------------------------------------- -- System Generator version 13.2 VHDL source file. -- -- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity convert_func_call is generic ( din_width : integer := 16; din_bin_pt : integer := 4; din_arith : integer := xlUnsigned; dout_width : integer := 8; dout_bin_pt : integer := 2; dout_arith : integer := xlUnsigned; quantization : integer := xlTruncate; overflow : integer := xlWrap); port ( din : in std_logic_vector (din_width-1 downto 0); result : out std_logic_vector (dout_width-1 downto 0)); end convert_func_call; architecture behavior of convert_func_call is begin result <= convert_type(din, din_width, din_bin_pt, din_arith, dout_width, dout_bin_pt, dout_arith, quantization, overflow); end behavior; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity xlconvert is generic ( din_width : integer := 16; din_bin_pt : integer := 4; din_arith : integer := xlUnsigned; dout_width : integer := 8; dout_bin_pt : integer := 2; dout_arith : integer := xlUnsigned; en_width : integer := 1; en_bin_pt : integer := 0; en_arith : integer := xlUnsigned; bool_conversion : integer :=0; latency : integer := 0; quantization : integer := xlTruncate; overflow : integer := xlWrap); port ( din : in std_logic_vector (din_width-1 downto 0); en : in std_logic_vector (en_width-1 downto 0); ce : in std_logic; clr : in std_logic; clk : in std_logic; dout : out std_logic_vector (dout_width-1 downto 0)); end xlconvert; architecture behavior of xlconvert is component synth_reg generic (width : integer; latency : integer); port (i : in std_logic_vector(width-1 downto 0); ce : in std_logic; clr : in std_logic; clk : in std_logic; o : out std_logic_vector(width-1 downto 0)); end component; component convert_func_call generic ( din_width : integer := 16; din_bin_pt : integer := 4; din_arith : integer := xlUnsigned; dout_width : integer := 8; dout_bin_pt : integer := 2; dout_arith : integer := xlUnsigned; quantization : integer := xlTruncate; overflow : integer := xlWrap); port ( din : in std_logic_vector (din_width-1 downto 0); result : out std_logic_vector (dout_width-1 downto 0)); end component; -- synopsys translate_off -- synopsys translate_on signal result : std_logic_vector(dout_width-1 downto 0); signal internal_ce : std_logic; begin -- synopsys translate_off -- synopsys translate_on internal_ce <= ce and en(0); bool_conversion_generate : if (bool_conversion = 1) generate result <= din; end generate; std_conversion_generate : if (bool_conversion = 0) generate convert : convert_func_call generic map ( din_width => din_width, din_bin_pt => din_bin_pt, din_arith => din_arith, dout_width => dout_width, dout_bin_pt => dout_bin_pt, dout_arith => dout_arith, quantization => quantization, overflow => overflow) port map ( din => din, result => result); end generate; latency_test : if (latency > 0) generate reg : synth_reg generic map ( width => dout_width, latency => latency ) port map ( i => result, ce => internal_ce, clr => clr, clk => clk, o => dout ); end generate; latency0 : if (latency = 0) generate dout <= result; end generate latency0; end behavior; ------------------------------------------------------------------- -- System Generator version 13.2 VHDL source file. -- -- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- -- synopsys translate_off library XilinxCoreLib; -- synopsys translate_on library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use work.conv_pkg.all; entity xladdsub is generic ( core_name0: string := ""; a_width: integer := 16; a_bin_pt: integer := 4; a_arith: integer := xlUnsigned; c_in_width: integer := 16; c_in_bin_pt: integer := 4; c_in_arith: integer := xlUnsigned; c_out_width: integer := 16; c_out_bin_pt: integer := 4; c_out_arith: integer := xlUnsigned; b_width: integer := 8; b_bin_pt: integer := 2; b_arith: integer := xlUnsigned; s_width: integer := 17; s_bin_pt: integer := 4; s_arith: integer := xlUnsigned; rst_width: integer := 1; rst_bin_pt: integer := 0; rst_arith: integer := xlUnsigned; en_width: integer := 1; en_bin_pt: integer := 0; en_arith: integer := xlUnsigned; full_s_width: integer := 17; full_s_arith: integer := xlUnsigned; mode: integer := xlAddMode; extra_registers: integer := 0; latency: integer := 0; quantization: integer := xlTruncate; overflow: integer := xlWrap; c_latency: integer := 0; c_output_width: integer := 17; c_has_c_in : integer := 0; c_has_c_out : integer := 0 ); port ( a: in std_logic_vector(a_width - 1 downto 0); b: in std_logic_vector(b_width - 1 downto 0); c_in : in std_logic_vector (0 downto 0) := "0"; ce: in std_logic; clr: in std_logic := '0'; clk: in std_logic; rst: in std_logic_vector(rst_width - 1 downto 0) := "0"; en: in std_logic_vector(en_width - 1 downto 0) := "1"; c_out : out std_logic_vector (0 downto 0); s: out std_logic_vector(s_width - 1 downto 0) ); end xladdsub; architecture behavior of xladdsub is component synth_reg generic ( width: integer := 16; latency: integer := 5 ); port ( i: in std_logic_vector(width - 1 downto 0); ce: in std_logic; clr: in std_logic; clk: in std_logic; o: out std_logic_vector(width - 1 downto 0) ); end component; function format_input(inp: std_logic_vector; old_width, delta, new_arith, new_width: integer) return std_logic_vector is variable vec: std_logic_vector(old_width-1 downto 0); variable padded_inp: std_logic_vector((old_width + delta)-1 downto 0); variable result: std_logic_vector(new_width-1 downto 0); begin vec := inp; if (delta > 0) then padded_inp := pad_LSB(vec, old_width+delta); result := extend_MSB(padded_inp, new_width, new_arith); else result := extend_MSB(vec, new_width, new_arith); end if; return result; end; constant full_s_bin_pt: integer := fractional_bits(a_bin_pt, b_bin_pt); constant full_a_width: integer := full_s_width; constant full_b_width: integer := full_s_width; signal full_a: std_logic_vector(full_a_width - 1 downto 0); signal full_b: std_logic_vector(full_b_width - 1 downto 0); signal core_s: std_logic_vector(full_s_width - 1 downto 0); signal conv_s: std_logic_vector(s_width - 1 downto 0); signal temp_cout : std_logic; signal internal_clr: std_logic; signal internal_ce: std_logic; signal extra_reg_ce: std_logic; signal override: std_logic; signal logic1: std_logic_vector(0 downto 0); component addsb_11_0_c25f95ce6b0868c9 port ( a: in std_logic_vector(11 - 1 downto 0); s: out std_logic_vector(c_output_width - 1 downto 0); b: in std_logic_vector(11 - 1 downto 0) ); end component; attribute syn_black_box of addsb_11_0_c25f95ce6b0868c9: component is true; attribute fpga_dont_touch of addsb_11_0_c25f95ce6b0868c9: component is "true"; attribute box_type of addsb_11_0_c25f95ce6b0868c9: component is "black_box"; component addsb_11_0_a629aff4db5bb1c8 port ( a: in std_logic_vector(12 - 1 downto 0); s: out std_logic_vector(c_output_width - 1 downto 0); b: in std_logic_vector(12 - 1 downto 0) ); end component; attribute syn_black_box of addsb_11_0_a629aff4db5bb1c8: component is true; attribute fpga_dont_touch of addsb_11_0_a629aff4db5bb1c8: component is "true"; attribute box_type of addsb_11_0_a629aff4db5bb1c8: component is "black_box"; begin internal_clr <= (clr or (rst(0))) and ce; internal_ce <= ce and en(0); logic1(0) <= '1'; addsub_process: process (a, b, core_s) begin full_a <= format_input (a, a_width, b_bin_pt - a_bin_pt, a_arith, full_a_width); full_b <= format_input (b, b_width, a_bin_pt - b_bin_pt, b_arith, full_b_width); conv_s <= convert_type (core_s, full_s_width, full_s_bin_pt, full_s_arith, s_width, s_bin_pt, s_arith, quantization, overflow); end process addsub_process; comp0: if ((core_name0 = "addsb_11_0_c25f95ce6b0868c9")) generate core_instance0: addsb_11_0_c25f95ce6b0868c9 port map ( a => full_a, s => core_s, b => full_b ); end generate; comp1: if ((core_name0 = "addsb_11_0_a629aff4db5bb1c8")) generate core_instance1: addsb_11_0_a629aff4db5bb1c8 port map ( a => full_a, s => core_s, b => full_b ); end generate; latency_test: if (extra_registers > 0) generate override_test: if (c_latency > 1) generate override_pipe: synth_reg generic map ( width => 1, latency => c_latency ) port map ( i => logic1, ce => internal_ce, clr => internal_clr, clk => clk, o(0) => override); extra_reg_ce <= ce and en(0) and override; end generate override_test; no_override: if ((c_latency = 0) or (c_latency = 1)) generate extra_reg_ce <= ce and en(0); end generate no_override; extra_reg: synth_reg generic map ( width => s_width, latency => extra_registers ) port map ( i => conv_s, ce => extra_reg_ce, clr => internal_clr, clk => clk, o => s ); cout_test: if (c_has_c_out = 1) generate c_out_extra_reg: synth_reg generic map ( width => 1, latency => extra_registers ) port map ( i(0) => temp_cout, ce => extra_reg_ce, clr => internal_clr, clk => clk, o => c_out ); end generate cout_test; end generate; latency_s: if ((latency = 0) or (extra_registers = 0)) generate s <= conv_s; end generate latency_s; latency0: if (((latency = 0) or (extra_registers = 0)) and (c_has_c_out = 1)) generate c_out(0) <= temp_cout; end generate latency0; tie_dangling_cout: if (c_has_c_out = 0) generate c_out <= "0"; end generate tie_dangling_cout; end architecture behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity concat_e6f5ee726b is port ( in0 : in std_logic_vector((1 - 1) downto 0); in1 : in std_logic_vector((1 - 1) downto 0); y : out std_logic_vector((2 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end concat_e6f5ee726b; architecture behavior of concat_e6f5ee726b is signal in0_1_23: unsigned((1 - 1) downto 0); signal in1_1_27: unsigned((1 - 1) downto 0); signal y_2_1_concat: unsigned((2 - 1) downto 0); begin in0_1_23 <= std_logic_vector_to_unsigned(in0); in1_1_27 <= std_logic_vector_to_unsigned(in1); y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27)); y <= unsigned_to_std_logic_vector(y_2_1_concat); end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity concat_d0d1b9533e is port ( in0 : in std_logic_vector((8 - 1) downto 0); in1 : in std_logic_vector((8 - 1) downto 0); in2 : in std_logic_vector((8 - 1) downto 0); y : out std_logic_vector((24 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end concat_d0d1b9533e; architecture behavior of concat_d0d1b9533e is signal in0_1_23: unsigned((8 - 1) downto 0); signal in1_1_27: unsigned((8 - 1) downto 0); signal in2_1_31: unsigned((8 - 1) downto 0); signal y_2_1_concat: unsigned((24 - 1) downto 0); begin in0_1_23 <= std_logic_vector_to_unsigned(in0); in1_1_27 <= std_logic_vector_to_unsigned(in1); in2_1_31 <= std_logic_vector_to_unsigned(in2); y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27) & unsigned_to_std_logic_vector(in2_1_31)); y <= unsigned_to_std_logic_vector(y_2_1_concat); end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity delay_33cb3f7e58 is port ( d : in std_logic_vector((10 - 1) downto 0); en : in std_logic_vector((1 - 1) downto 0); q : out std_logic_vector((10 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end delay_33cb3f7e58; architecture behavior of delay_33cb3f7e58 is signal d_1_22: std_logic_vector((10 - 1) downto 0); signal en_1_25: std_logic; type array_type_op_mem_20_24 is array (0 to (1 - 1)) of std_logic_vector((10 - 1) downto 0); signal op_mem_20_24: array_type_op_mem_20_24 := ( 0 => "0000000000"); signal op_mem_20_24_front_din: std_logic_vector((10 - 1) downto 0); signal op_mem_20_24_back: std_logic_vector((10 - 1) downto 0); signal op_mem_20_24_push_front_pop_back_en: std_logic; signal op_mem_shift_join_27_9: std_logic_vector((10 - 1) downto 0); signal op_mem_shift_join_27_9_en: std_logic; begin d_1_22 <= d; en_1_25 <= en(0); op_mem_20_24_back <= op_mem_20_24(0); proc_op_mem_20_24: process (clk) is variable i: integer; begin if (clk'event and (clk = '1')) then if ((ce = '1') and (op_mem_20_24_push_front_pop_back_en = '1')) then op_mem_20_24(0) <= op_mem_20_24_front_din; end if; end if; end process proc_op_mem_20_24; proc_if_27_9: process (d_1_22, en_1_25) is begin if en_1_25 = '1' then op_mem_shift_join_27_9_en <= '1'; else op_mem_shift_join_27_9_en <= '0'; end if; op_mem_shift_join_27_9 <= d_1_22; end process proc_if_27_9; op_mem_20_24_front_din <= op_mem_shift_join_27_9; op_mem_20_24_push_front_pop_back_en <= op_mem_shift_join_27_9_en; q <= op_mem_20_24_back; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity delay_0025330cf4 is port ( d : in std_logic_vector((2 - 1) downto 0); en : in std_logic_vector((1 - 1) downto 0); q : out std_logic_vector((2 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end delay_0025330cf4; architecture behavior of delay_0025330cf4 is signal d_1_22: std_logic_vector((2 - 1) downto 0); signal en_1_25: std_logic; type array_type_op_mem_20_24 is array (0 to (1 - 1)) of std_logic_vector((2 - 1) downto 0); signal op_mem_20_24: array_type_op_mem_20_24 := ( 0 => "00"); signal op_mem_20_24_front_din: std_logic_vector((2 - 1) downto 0); signal op_mem_20_24_back: std_logic_vector((2 - 1) downto 0); signal op_mem_20_24_push_front_pop_back_en: std_logic; signal op_mem_shift_join_27_9: std_logic_vector((2 - 1) downto 0); signal op_mem_shift_join_27_9_en: std_logic; begin d_1_22 <= d; en_1_25 <= en(0); op_mem_20_24_back <= op_mem_20_24(0); proc_op_mem_20_24: process (clk) is variable i: integer; begin if (clk'event and (clk = '1')) then if ((ce = '1') and (op_mem_20_24_push_front_pop_back_en = '1')) then op_mem_20_24(0) <= op_mem_20_24_front_din; end if; end if; end process proc_op_mem_20_24; proc_if_27_9: process (d_1_22, en_1_25) is begin if en_1_25 = '1' then op_mem_shift_join_27_9_en <= '1'; else op_mem_shift_join_27_9_en <= '0'; end if; op_mem_shift_join_27_9 <= d_1_22; end process proc_if_27_9; op_mem_20_24_front_din <= op_mem_shift_join_27_9; op_mem_20_24_push_front_pop_back_en <= op_mem_shift_join_27_9_en; q <= op_mem_20_24_back; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity delay_ec78404abf is port ( d : in std_logic_vector((12 - 1) downto 0); en : in std_logic_vector((1 - 1) downto 0); q : out std_logic_vector((12 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end delay_ec78404abf; architecture behavior of delay_ec78404abf is signal d_1_22: std_logic_vector((12 - 1) downto 0); signal en_1_25: std_logic; type array_type_op_mem_20_24 is array (0 to (1 - 1)) of std_logic_vector((12 - 1) downto 0); signal op_mem_20_24: array_type_op_mem_20_24 := ( 0 => "000000000000"); signal op_mem_20_24_front_din: std_logic_vector((12 - 1) downto 0); signal op_mem_20_24_back: std_logic_vector((12 - 1) downto 0); signal op_mem_20_24_push_front_pop_back_en: std_logic; signal op_mem_shift_join_27_9: std_logic_vector((12 - 1) downto 0); signal op_mem_shift_join_27_9_en: std_logic; begin d_1_22 <= d; en_1_25 <= en(0); op_mem_20_24_back <= op_mem_20_24(0); proc_op_mem_20_24: process (clk) is variable i: integer; begin if (clk'event and (clk = '1')) then if ((ce = '1') and (op_mem_20_24_push_front_pop_back_en = '1')) then op_mem_20_24(0) <= op_mem_20_24_front_din; end if; end if; end process proc_op_mem_20_24; proc_if_27_9: process (d_1_22, en_1_25) is begin if en_1_25 = '1' then op_mem_shift_join_27_9_en <= '1'; else op_mem_shift_join_27_9_en <= '0'; end if; op_mem_shift_join_27_9 <= d_1_22; end process proc_if_27_9; op_mem_20_24_front_din <= op_mem_shift_join_27_9; op_mem_20_24_push_front_pop_back_en <= op_mem_shift_join_27_9_en; q <= op_mem_20_24_back; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity delay_0fbdd36101 is port ( d : in std_logic_vector((10 - 1) downto 0); en : in std_logic_vector((1 - 1) downto 0); q : out std_logic_vector((10 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end delay_0fbdd36101; architecture behavior of delay_0fbdd36101 is signal d_1_22: std_logic_vector((10 - 1) downto 0); signal en_1_25: std_logic; type array_type_op_mem_20_24 is array (0 to (2 - 1)) of std_logic_vector((10 - 1) downto 0); signal op_mem_20_24: array_type_op_mem_20_24 := ( "0000000000", "0000000000"); signal op_mem_20_24_front_din: std_logic_vector((10 - 1) downto 0); signal op_mem_20_24_back: std_logic_vector((10 - 1) downto 0); signal op_mem_20_24_push_front_pop_back_en: std_logic; signal op_mem_shift_join_27_9: std_logic_vector((10 - 1) downto 0); signal op_mem_shift_join_27_9_en: std_logic; begin d_1_22 <= d; en_1_25 <= en(0); op_mem_20_24_back <= op_mem_20_24(1); proc_op_mem_20_24: process (clk) is variable i: integer; begin if (clk'event and (clk = '1')) then if ((ce = '1') and (op_mem_20_24_push_front_pop_back_en = '1')) then for i in 1 downto 1 loop op_mem_20_24(i) <= op_mem_20_24(i-1); end loop; op_mem_20_24(0) <= op_mem_20_24_front_din; end if; end if; end process proc_op_mem_20_24; proc_if_27_9: process (d_1_22, en_1_25) is begin if en_1_25 = '1' then op_mem_shift_join_27_9_en <= '1'; else op_mem_shift_join_27_9_en <= '0'; end if; op_mem_shift_join_27_9 <= d_1_22; end process proc_if_27_9; op_mem_20_24_front_din <= op_mem_shift_join_27_9; op_mem_20_24_push_front_pop_back_en <= op_mem_shift_join_27_9_en; q <= op_mem_20_24_back; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity mux_4fe5face7f is port ( sel : in std_logic_vector((1 - 1) downto 0); d0 : in std_logic_vector((10 - 1) downto 0); d1 : in std_logic_vector((10 - 1) downto 0); y : out std_logic_vector((10 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end mux_4fe5face7f; architecture behavior of mux_4fe5face7f is signal sel_1_20: std_logic_vector((1 - 1) downto 0); signal d0_1_24: std_logic_vector((10 - 1) downto 0); signal d1_1_27: std_logic_vector((10 - 1) downto 0); signal unregy_join_6_1: std_logic_vector((10 - 1) downto 0); begin sel_1_20 <= sel; d0_1_24 <= d0; d1_1_27 <= d1; proc_switch_6_1: process (d0_1_24, d1_1_27, sel_1_20) is begin case sel_1_20 is when "0" => unregy_join_6_1 <= d0_1_24; when others => unregy_join_6_1 <= d1_1_27; end case; end process proc_switch_6_1; y <= unregy_join_6_1; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity mux_61418c8488 is port ( sel : in std_logic_vector((2 - 1) downto 0); d0 : in std_logic_vector((10 - 1) downto 0); d1 : in std_logic_vector((10 - 1) downto 0); d2 : in std_logic_vector((10 - 1) downto 0); d3 : in std_logic_vector((10 - 1) downto 0); y : out std_logic_vector((10 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end mux_61418c8488; architecture behavior of mux_61418c8488 is signal sel_1_20: std_logic_vector((2 - 1) downto 0); signal d0_1_24: std_logic_vector((10 - 1) downto 0); signal d1_1_27: std_logic_vector((10 - 1) downto 0); signal d2_1_30: std_logic_vector((10 - 1) downto 0); signal d3_1_33: std_logic_vector((10 - 1) downto 0); signal unregy_join_6_1: std_logic_vector((10 - 1) downto 0); begin sel_1_20 <= sel; d0_1_24 <= d0; d1_1_27 <= d1; d2_1_30 <= d2; d3_1_33 <= d3; proc_switch_6_1: process (d0_1_24, d1_1_27, d2_1_30, d3_1_33, sel_1_20) is begin case sel_1_20 is when "00" => unregy_join_6_1 <= d0_1_24; when "01" => unregy_join_6_1 <= d1_1_27; when "10" => unregy_join_6_1 <= d2_1_30; when others => unregy_join_6_1 <= d3_1_33; end case; end process proc_switch_6_1; y <= unregy_join_6_1; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity shift_d9577b2c80 is port ( ip : in std_logic_vector((11 - 1) downto 0); op : out std_logic_vector((12 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end shift_d9577b2c80; architecture behavior of shift_d9577b2c80 is signal ip_1_23: unsigned((11 - 1) downto 0); type array_type_op_mem_46_20 is array (0 to (1 - 1)) of unsigned((12 - 1) downto 0); signal op_mem_46_20: array_type_op_mem_46_20 := ( 0 => "000000000000"); signal op_mem_46_20_front_din: unsigned((12 - 1) downto 0); signal op_mem_46_20_back: unsigned((12 - 1) downto 0); signal op_mem_46_20_push_front_pop_back_en: std_logic; signal cast_internal_ip_25_3_lsh: unsigned((12 - 1) downto 0); begin ip_1_23 <= std_logic_vector_to_unsigned(ip); op_mem_46_20_back <= op_mem_46_20(0); proc_op_mem_46_20: process (clk) is variable i: integer; begin if (clk'event and (clk = '1')) then if ((ce = '1') and (op_mem_46_20_push_front_pop_back_en = '1')) then op_mem_46_20(0) <= op_mem_46_20_front_din; end if; end if; end process proc_op_mem_46_20; cast_internal_ip_25_3_lsh <= u2u_cast(ip_1_23, 0, 12, 1); op_mem_46_20_push_front_pop_back_en <= '0'; op <= unsigned_to_std_logic_vector(cast_internal_ip_25_3_lsh); end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity shift_0a73a8a346 is port ( ip : in std_logic_vector((10 - 1) downto 0); op : out std_logic_vector((12 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end shift_0a73a8a346; architecture behavior of shift_0a73a8a346 is signal ip_1_23: unsigned((10 - 1) downto 0); type array_type_op_mem_46_20 is array (0 to (1 - 1)) of unsigned((12 - 1) downto 0); signal op_mem_46_20: array_type_op_mem_46_20 := ( 0 => "000000000000"); signal op_mem_46_20_front_din: unsigned((12 - 1) downto 0); signal op_mem_46_20_back: unsigned((12 - 1) downto 0); signal op_mem_46_20_push_front_pop_back_en: std_logic; signal cast_internal_ip_25_3_lsh: unsigned((12 - 1) downto 0); begin ip_1_23 <= std_logic_vector_to_unsigned(ip); op_mem_46_20_back <= op_mem_46_20(0); proc_op_mem_46_20: process (clk) is variable i: integer; begin if (clk'event and (clk = '1')) then if ((ce = '1') and (op_mem_46_20_push_front_pop_back_en = '1')) then op_mem_46_20(0) <= op_mem_46_20_front_din; end if; end if; end process proc_op_mem_46_20; cast_internal_ip_25_3_lsh <= u2u_cast(ip_1_23, 0, 12, 2); op_mem_46_20_push_front_pop_back_en <= '0'; op <= unsigned_to_std_logic_vector(cast_internal_ip_25_3_lsh); end behavior; ------------------------------------------------------------------- -- System Generator version 13.2 VHDL source file. -- -- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity xlspram is generic ( core_name0: string := ""; c_width: integer := 12; c_address_width: integer := 4; latency: integer := 1 ); port ( data_in: in std_logic_vector(c_width - 1 downto 0); addr: in std_logic_vector(c_address_width - 1 downto 0); we: in std_logic_vector(0 downto 0); en: in std_logic_vector(0 downto 0); rst: in std_logic_vector(0 downto 0); ce: in std_logic; clk: in std_logic; data_out: out std_logic_vector(c_width - 1 downto 0) ); end xlspram ; architecture behavior of xlspram is component synth_reg generic ( width: integer; latency: integer ); port ( i: in std_logic_vector(width - 1 downto 0); ce: in std_logic; clr: in std_logic; clk: in std_logic; o: out std_logic_vector(width - 1 downto 0) ); end component; signal core_data_out, dly_data_out: std_logic_vector(c_width - 1 downto 0); signal core_we, core_ce, sinit: std_logic; component bmg_62_2be284cffc9a51ef port ( addra: in std_logic_vector(c_address_width - 1 downto 0); clka: in std_logic; dina: in std_logic_vector(c_width - 1 downto 0); wea: in std_logic_vector(0 downto 0); ena: in std_logic; douta: out std_logic_vector(c_width - 1 downto 0) ); end component; attribute syn_black_box of bmg_62_2be284cffc9a51ef: component is true; attribute fpga_dont_touch of bmg_62_2be284cffc9a51ef: component is "true"; attribute box_type of bmg_62_2be284cffc9a51ef: component is "black_box"; begin data_out <= dly_data_out; core_we <= we(0); core_ce <= ce and en(0); sinit <= rst(0) and ce; comp0: if ((core_name0 = "bmg_62_2be284cffc9a51ef")) generate core_instance0: bmg_62_2be284cffc9a51ef port map ( addra => addr, clka => clk, dina => data_in, wea(0) => core_we, ena => core_ce, douta => core_data_out ); end generate; latency_test: if (latency > 1) generate reg: synth_reg generic map ( width => c_width, latency => latency - 1 ) port map ( i => core_data_out, ce => core_ce, clr => '0', clk => clk, o => dly_data_out ); end generate; latency_1: if (latency <= 1) generate dly_data_out <= core_data_out; end generate; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity delay_1b0d89c05a is port ( d : in std_logic_vector((1 - 1) downto 0); q : out std_logic_vector((1 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end delay_1b0d89c05a; architecture behavior of delay_1b0d89c05a is signal d_1_22: std_logic_vector((1 - 1) downto 0); type array_type_op_mem_20_24 is array (0 to (7 - 1)) of std_logic_vector((1 - 1) downto 0); signal op_mem_20_24: array_type_op_mem_20_24 := ( "0", "0", "0", "0", "0", "0", "0"); signal op_mem_20_24_front_din: std_logic_vector((1 - 1) downto 0); signal op_mem_20_24_back: std_logic_vector((1 - 1) downto 0); signal op_mem_20_24_push_front_pop_back_en: std_logic; begin d_1_22 <= d; op_mem_20_24_back <= op_mem_20_24(6); proc_op_mem_20_24: process (clk) is variable i: integer; begin if (clk'event and (clk = '1')) then if ((ce = '1') and (op_mem_20_24_push_front_pop_back_en = '1')) then for i in 6 downto 1 loop op_mem_20_24(i) <= op_mem_20_24(i-1); end loop; op_mem_20_24(0) <= op_mem_20_24_front_din; end if; end if; end process proc_op_mem_20_24; op_mem_20_24_front_din <= d_1_22; op_mem_20_24_push_front_pop_back_en <= '1'; q <= op_mem_20_24_back; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity delay_e1f6cb3ad9 is port ( d : in std_logic_vector((24 - 1) downto 0); q : out std_logic_vector((24 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end delay_e1f6cb3ad9; architecture behavior of delay_e1f6cb3ad9 is signal d_1_22: std_logic_vector((24 - 1) downto 0); type array_type_op_mem_20_24 is array (0 to (1 - 1)) of std_logic_vector((24 - 1) downto 0); signal op_mem_20_24: array_type_op_mem_20_24 := ( 0 => "000000000000000000000000"); signal op_mem_20_24_front_din: std_logic_vector((24 - 1) downto 0); signal op_mem_20_24_back: std_logic_vector((24 - 1) downto 0); signal op_mem_20_24_push_front_pop_back_en: std_logic; begin d_1_22 <= d; op_mem_20_24_back <= op_mem_20_24(0); proc_op_mem_20_24: process (clk) is variable i: integer; begin if (clk'event and (clk = '1')) then if ((ce = '1') and (op_mem_20_24_push_front_pop_back_en = '1')) then op_mem_20_24(0) <= op_mem_20_24_front_din; end if; end if; end process proc_op_mem_20_24; op_mem_20_24_front_din <= d_1_22; op_mem_20_24_push_front_pop_back_en <= '1'; q <= op_mem_20_24_back; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity constant_6293007044 is port ( op : out std_logic_vector((1 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end constant_6293007044; architecture behavior of constant_6293007044 is begin op <= "1"; end behavior; ------------------------------------------------------------------- -- System Generator version 13.2 VHDL source file. -- -- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use work.conv_pkg.all; entity xlsprom is generic ( core_name0: string := ""; c_width: integer := 12; c_address_width: integer := 4; latency: integer := 1 ); port ( addr: in std_logic_vector(c_address_width - 1 downto 0); en: in std_logic_vector(0 downto 0); rst: in std_logic_vector(0 downto 0); ce: in std_logic; clk: in std_logic; data: out std_logic_vector(c_width - 1 downto 0) ); end xlsprom ; architecture behavior of xlsprom is component synth_reg generic ( width: integer; latency: integer ); port ( i: in std_logic_vector(width - 1 downto 0); ce: in std_logic; clr: in std_logic; clk: in std_logic; o: out std_logic_vector(width - 1 downto 0) ); end component; signal core_addr: std_logic_vector(c_address_width - 1 downto 0); signal core_data_out: std_logic_vector(c_width - 1 downto 0); signal core_ce, sinit: std_logic; component bmg_62_efdcd0e54d01b373 port ( addra: in std_logic_vector(c_address_width - 1 downto 0); clka: in std_logic; ena: in std_logic; douta: out std_logic_vector(c_width - 1 downto 0) ); end component; attribute syn_black_box of bmg_62_efdcd0e54d01b373: component is true; attribute fpga_dont_touch of bmg_62_efdcd0e54d01b373: component is "true"; attribute box_type of bmg_62_efdcd0e54d01b373: component is "black_box"; begin core_addr <= addr; core_ce <= ce and en(0); sinit <= rst(0) and ce; comp0: if ((core_name0 = "bmg_62_efdcd0e54d01b373")) generate core_instance0: bmg_62_efdcd0e54d01b373 port map ( addra => core_addr, clka => clk, ena => core_ce, douta => core_data_out ); end generate; latency_test: if (latency > 1) generate reg: synth_reg generic map ( width => c_width, latency => latency - 1 ) port map ( i => core_data_out, ce => core_ce, clr => '0', clk => clk, o => data ); end generate; latency_1: if (latency <= 1) generate data <= core_data_out; end generate; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity concat_8712d31083 is port ( in0 : in std_logic_vector((8 - 1) downto 0); in1 : in std_logic_vector((2 - 1) downto 0); y : out std_logic_vector((10 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end concat_8712d31083; architecture behavior of concat_8712d31083 is signal in0_1_23: unsigned((8 - 1) downto 0); signal in1_1_27: unsigned((2 - 1) downto 0); signal y_2_1_concat: unsigned((10 - 1) downto 0); begin in0_1_23 <= std_logic_vector_to_unsigned(in0); in1_1_27 <= std_logic_vector_to_unsigned(in1); y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27)); y <= unsigned_to_std_logic_vector(y_2_1_concat); end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity constant_cda50df78a is port ( op : out std_logic_vector((2 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end constant_cda50df78a; architecture behavior of constant_cda50df78a is begin op <= "00"; end behavior; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; -- Generated from Simulink block "sg_cfa_gamma/EDK Processor" entity edk_processor_entity_33f025737d is port ( plb_abus: in std_logic_vector(31 downto 0); plb_ce_1: in std_logic; plb_clk_1: in std_logic; plb_pavalid: in std_logic; plb_rnw: in std_logic; plb_wrdbus: in std_logic_vector(31 downto 0); sg_plb_addrpref: in std_logic_vector(19 downto 0); splb_rst: in std_logic; to_register: in std_logic_vector(31 downto 0); constant5_x0: out std_logic; plb_decode_x0: out std_logic; plb_decode_x1: out std_logic; plb_decode_x2: out std_logic; plb_decode_x3: out std_logic; plb_decode_x4: out std_logic_vector(31 downto 0); plb_memmap_x0: out std_logic_vector(31 downto 0); plb_memmap_x1: out std_logic ); end edk_processor_entity_33f025737d; architecture structural of edk_processor_entity_33f025737d is signal bankaddr: std_logic_vector(1 downto 0); signal bayer_ctrl_din_x0: std_logic_vector(31 downto 0); signal bayer_ctrl_dout_x0: std_logic_vector(31 downto 0); signal bayer_ctrl_en_x0: std_logic; signal linearaddr: std_logic_vector(7 downto 0); signal plb_abus_net_x0: std_logic_vector(31 downto 0); signal plb_ce_1_sg_x0: std_logic; signal plb_clk_1_sg_x0: std_logic; signal plb_pavalid_net_x0: std_logic; signal plb_rnw_net_x0: std_logic; signal plb_wrdbus_net_x0: std_logic_vector(31 downto 0); signal rddata: std_logic_vector(31 downto 0); signal rnwreg: std_logic; signal sg_plb_addrpref_net_x0: std_logic_vector(19 downto 0); signal sl_addrack_x0: std_logic; signal sl_rdcomp_x0: std_logic; signal sl_rddack_x0: std_logic; signal sl_rddbus_x0: std_logic_vector(31 downto 0); signal sl_wait_x0: std_logic; signal sl_wrdack_x0: std_logic; signal splb_rst_net_x0: std_logic; signal wrdbusreg: std_logic_vector(31 downto 0); begin plb_abus_net_x0 <= plb_abus; plb_ce_1_sg_x0 <= plb_ce_1; plb_clk_1_sg_x0 <= plb_clk_1; plb_pavalid_net_x0 <= plb_pavalid; plb_rnw_net_x0 <= plb_rnw; plb_wrdbus_net_x0 <= plb_wrdbus; sg_plb_addrpref_net_x0 <= sg_plb_addrpref; splb_rst_net_x0 <= splb_rst; bayer_ctrl_dout_x0 <= to_register; constant5_x0 <= sl_wait_x0; plb_decode_x0 <= sl_addrack_x0; plb_decode_x1 <= sl_rdcomp_x0; plb_decode_x2 <= sl_wrdack_x0; plb_decode_x3 <= sl_rddack_x0; plb_decode_x4 <= sl_rddbus_x0; plb_memmap_x0 <= bayer_ctrl_din_x0; plb_memmap_x1 <= bayer_ctrl_en_x0; constant5: entity work.constant_963ed6358a port map ( ce => '0', clk => '0', clr => '0', op(0) => sl_wait_x0 ); plb_decode: entity work.mcode_block_f4d0462e0e port map ( addrpref => sg_plb_addrpref_net_x0, ce => plb_ce_1_sg_x0, clk => plb_clk_1_sg_x0, clr => '0', plbabus => plb_abus_net_x0, plbpavalid(0) => plb_pavalid_net_x0, plbrnw(0) => plb_rnw_net_x0, plbrst(0) => splb_rst_net_x0, plbwrdbus => plb_wrdbus_net_x0, rddata => rddata, addrack(0) => sl_addrack_x0, bankaddr => bankaddr, linearaddr => linearaddr, rdcomp(0) => sl_rdcomp_x0, rddack(0) => sl_rddack_x0, rddbus => sl_rddbus_x0, rnwreg(0) => rnwreg, wrdack(0) => sl_wrdack_x0, wrdbusreg => wrdbusreg ); plb_memmap: entity work.mcode_block_2c4e41848b port map ( addrack(0) => sl_addrack_x0, bankaddr => bankaddr, ce => plb_ce_1_sg_x0, clk => plb_clk_1_sg_x0, clr => '0', linearaddr => linearaddr, rnwreg(0) => rnwreg, sm_bayer_ctrl => bayer_ctrl_dout_x0, wrdbus => wrdbusreg, read_bank_out => rddata, sm_bayer_ctrl_din => bayer_ctrl_din_x0, sm_bayer_ctrl_en(0) => bayer_ctrl_en_x0 ); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; -- Generated from Simulink block "sg_cfa_gamma/bayer/Subsystem" entity subsystem_entity_387011edf3 is port ( from_register: in std_logic_vector(31 downto 0); pos: in std_logic_vector(1 downto 0); bsel: out std_logic_vector(1 downto 0); gsel: out std_logic; rsel: out std_logic_vector(1 downto 0) ); end subsystem_entity_387011edf3; architecture structural of subsystem_entity_387011edf3 is signal delay15_q_net_x0: std_logic_vector(1 downto 0); signal from_register_data_out_net_x0: std_logic_vector(31 downto 0); signal mux7_y_net_x0: std_logic_vector(1 downto 0); signal mux8_y_net: std_logic_vector(1 downto 0); signal mux9_y_net_x0: std_logic_vector(1 downto 0); signal slice10_y_net: std_logic_vector(1 downto 0); signal slice11_y_net: std_logic_vector(1 downto 0); signal slice12_y_net: std_logic_vector(1 downto 0); signal slice13_y_net: std_logic_vector(1 downto 0); signal slice14_y_net: std_logic_vector(1 downto 0); signal slice17_y_net_x0: std_logic; signal slice3_y_net: std_logic_vector(1 downto 0); signal slice4_y_net: std_logic_vector(1 downto 0); signal slice5_y_net: std_logic_vector(1 downto 0); signal slice6_y_net: std_logic_vector(1 downto 0); signal slice7_y_net: std_logic_vector(1 downto 0); signal slice8_y_net: std_logic_vector(1 downto 0); signal slice9_y_net: std_logic_vector(1 downto 0); begin from_register_data_out_net_x0 <= from_register; delay15_q_net_x0 <= pos; bsel <= mux9_y_net_x0; gsel <= slice17_y_net_x0; rsel <= mux7_y_net_x0; mux7: entity work.mux_1a0db76efe port map ( ce => '0', clk => '0', clr => '0', d0 => slice5_y_net, d1 => slice4_y_net, d2 => slice3_y_net, d3 => slice6_y_net, sel => delay15_q_net_x0, y => mux7_y_net_x0 ); mux8: entity work.mux_1a0db76efe port map ( ce => '0', clk => '0', clr => '0', d0 => slice9_y_net, d1 => slice8_y_net, d2 => slice7_y_net, d3 => slice10_y_net, sel => delay15_q_net_x0, y => mux8_y_net ); mux9: entity work.mux_1a0db76efe port map ( ce => '0', clk => '0', clr => '0', d0 => slice14_y_net, d1 => slice13_y_net, d2 => slice12_y_net, d3 => slice11_y_net, sel => delay15_q_net_x0, y => mux9_y_net_x0 ); slice10: entity work.xlslice generic map ( new_lsb => 14, new_msb => 15, x_width => 32, y_width => 2 ) port map ( x => from_register_data_out_net_x0, y => slice10_y_net ); slice11: entity work.xlslice generic map ( new_lsb => 6, new_msb => 7, x_width => 32, y_width => 2 ) port map ( x => from_register_data_out_net_x0, y => slice11_y_net ); slice12: entity work.xlslice generic map ( new_lsb => 4, new_msb => 5, x_width => 32, y_width => 2 ) port map ( x => from_register_data_out_net_x0, y => slice12_y_net ); slice13: entity work.xlslice generic map ( new_lsb => 2, new_msb => 3, x_width => 32, y_width => 2 ) port map ( x => from_register_data_out_net_x0, y => slice13_y_net ); slice14: entity work.xlslice generic map ( new_lsb => 0, new_msb => 1, x_width => 32, y_width => 2 ) port map ( x => from_register_data_out_net_x0, y => slice14_y_net ); slice17: entity work.xlslice generic map ( new_lsb => 0, new_msb => 0, x_width => 2, y_width => 1 ) port map ( x => mux8_y_net, y(0) => slice17_y_net_x0 ); slice3: entity work.xlslice generic map ( new_lsb => 20, new_msb => 21, x_width => 32, y_width => 2 ) port map ( x => from_register_data_out_net_x0, y => slice3_y_net ); slice4: entity work.xlslice generic map ( new_lsb => 18, new_msb => 19, x_width => 32, y_width => 2 ) port map ( x => from_register_data_out_net_x0, y => slice4_y_net ); slice5: entity work.xlslice generic map ( new_lsb => 16, new_msb => 17, x_width => 32, y_width => 2 ) port map ( x => from_register_data_out_net_x0, y => slice5_y_net ); slice6: entity work.xlslice generic map ( new_lsb => 22, new_msb => 23, x_width => 32, y_width => 2 ) port map ( x => from_register_data_out_net_x0, y => slice6_y_net ); slice7: entity work.xlslice generic map ( new_lsb => 12, new_msb => 13, x_width => 32, y_width => 2 ) port map ( x => from_register_data_out_net_x0, y => slice7_y_net ); slice8: entity work.xlslice generic map ( new_lsb => 10, new_msb => 11, x_width => 32, y_width => 2 ) port map ( x => from_register_data_out_net_x0, y => slice8_y_net ); slice9: entity work.xlslice generic map ( new_lsb => 8, new_msb => 9, x_width => 32, y_width => 2 ) port map ( x => from_register_data_out_net_x0, y => slice9_y_net ); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; -- Generated from Simulink block "sg_cfa_gamma/bayer/xy_ctrs" entity xy_ctrs_entity_9e9b1c9cc9 is port ( av: in std_logic; ce_1: in std_logic; clk_1: in std_logic; en: in std_logic; vb: in std_logic; x: out std_logic_vector(11 downto 0); y: out std_logic_vector(11 downto 0) ); end xy_ctrs_entity_9e9b1c9cc9; architecture structural of xy_ctrs_entity_9e9b1c9cc9 is signal active_video_i_net_x0: std_logic; signal bool1_dout_net: std_logic; signal bool2_dout_net: std_logic; signal bool3_dout_net: std_logic; signal ce_1_sg_x0: std_logic; signal clk_1_sg_x0: std_logic; signal delay20_q_net: std_logic; signal delay21_q_net: std_logic; signal enable_op_net_x0: std_logic; signal expression1_dout_net: std_logic; signal expression3_dout_net: std_logic; signal expression_dout_net: std_logic; signal inverter_op_net: std_logic; signal vblank_i_net_x0: std_logic; signal xcounter_op_net_x0: std_logic_vector(11 downto 0); signal ycounter_op_net_x0: std_logic_vector(11 downto 0); begin active_video_i_net_x0 <= av; ce_1_sg_x0 <= ce_1; clk_1_sg_x0 <= clk_1; enable_op_net_x0 <= en; vblank_i_net_x0 <= vb; x <= xcounter_op_net_x0; y <= ycounter_op_net_x0; bool1: entity work.xlconvert generic map ( bool_conversion => 1, din_arith => 1, din_bin_pt => 0, din_width => 1, dout_arith => 1, dout_bin_pt => 0, dout_width => 1, latency => 0, overflow => xlWrap, quantization => xlTruncate ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, clr => '0', din(0) => expression3_dout_net, en => "1", dout(0) => bool1_dout_net ); bool2: entity work.xlconvert generic map ( bool_conversion => 1, din_arith => 1, din_bin_pt => 0, din_width => 1, dout_arith => 1, dout_bin_pt => 0, dout_width => 1, latency => 0, overflow => xlWrap, quantization => xlTruncate ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, clr => '0', din(0) => active_video_i_net_x0, en => "1", dout(0) => bool2_dout_net ); bool3: entity work.xlconvert generic map ( bool_conversion => 1, din_arith => 1, din_bin_pt => 0, din_width => 1, dout_arith => 1, dout_bin_pt => 0, dout_width => 1, latency => 0, overflow => xlWrap, quantization => xlTruncate ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, clr => '0', din(0) => expression_dout_net, en => "1", dout(0) => bool3_dout_net ); delay20: entity work.delay_5753e4c658 port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, clr => '0', d(0) => vblank_i_net_x0, q(0) => delay20_q_net ); delay21: entity work.delay_a3ccf865c7 port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, clr => '0', d(0) => active_video_i_net_x0, en(0) => enable_op_net_x0, q(0) => delay21_q_net ); expression: entity work.expr_332f1d2335 port map ( ce => '0', clk => '0', clr => '0', d0(0) => vblank_i_net_x0, d1(0) => delay20_q_net, dout(0) => expression_dout_net ); expression1: entity work.expr_3c2515cf08 port map ( a(0) => bool1_dout_net, b(0) => enable_op_net_x0, ce => '0', clk => '0', clr => '0', dout(0) => expression1_dout_net ); expression3: entity work.expr_332f1d2335 port map ( ce => '0', clk => '0', clr => '0', d0(0) => active_video_i_net_x0, d1(0) => delay21_q_net, dout(0) => expression3_dout_net ); inverter: entity work.inverter_e5b38cca3b port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, clr => '0', ip(0) => bool2_dout_net, op(0) => inverter_op_net ); xcounter: entity work.xlcounter_free generic map ( core_name0 => "cntr_11_0_3eb0c8dcd9c22b4d", op_arith => xlUnsigned, op_width => 12 ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, clr => '0', en(0) => enable_op_net_x0, rst(0) => inverter_op_net, op => xcounter_op_net_x0 ); ycounter: entity work.xlcounter_free generic map ( core_name0 => "cntr_11_0_3eb0c8dcd9c22b4d", op_arith => xlUnsigned, op_width => 12 ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, clr => '0', en(0) => expression1_dout_net, rst(0) => bool3_dout_net, op => ycounter_op_net_x0 ); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; -- Generated from Simulink block "sg_cfa_gamma/bayer" entity bayer_entity_7e9fc9cbc8 is port ( avi: in std_logic; ce_1: in std_logic; clk_1: in std_logic; from_register: in std_logic_vector(31 downto 0); hbi: in std_logic; hsi: in std_logic; vbi: in std_logic; vdi: in std_logic_vector(9 downto 0); vsi: in std_logic; avo: out std_logic; hbo: out std_logic; hso: out std_logic; vbo: out std_logic; vdo: out std_logic_vector(23 downto 0); vso: out std_logic ); end bayer_entity_7e9fc9cbc8; architecture structural of bayer_entity_7e9fc9cbc8 is signal active_video_delay_q_net_x0: std_logic; signal active_video_i_net_x1: std_logic; signal addsub1_s_net: std_logic_vector(10 downto 0); signal addsub5_s_net: std_logic_vector(10 downto 0); signal bayer_conv: std_logic_vector(9 downto 0); signal blue: std_logic_vector(9 downto 0); signal ce_1_sg_x1: std_logic; signal clk_1_sg_x1: std_logic; signal concat1_y_net: std_logic_vector(23 downto 0); signal concat2_y_net_x0: std_logic_vector(9 downto 0); signal concat_y_net: std_logic_vector(1 downto 0); signal convert_dout_net: std_logic; signal d0: std_logic_vector(9 downto 0); signal d1: std_logic_vector(9 downto 0); signal d3: std_logic_vector(9 downto 0); signal data_delay_q_net_x0: std_logic_vector(23 downto 0); signal davg: std_logic_vector(11 downto 0); signal davg_x0: std_logic_vector(11 downto 0); signal davg_x1: std_logic_vector(9 downto 0); signal delay10_q_net: std_logic_vector(9 downto 0); signal delay11_q_net: std_logic_vector(9 downto 0); signal delay12_q_net: std_logic_vector(9 downto 0); signal delay13_q_net: std_logic_vector(9 downto 0); signal delay14_q_net: std_logic_vector(9 downto 0); signal delay15_q_net_x0: std_logic_vector(1 downto 0); signal delay17_q_net: std_logic_vector(11 downto 0); signal delay19_q_net: std_logic_vector(11 downto 0); signal delay1_q_net: std_logic_vector(9 downto 0); signal delay20_q_net: std_logic_vector(11 downto 0); signal delay5_q_net: std_logic_vector(11 downto 0); signal delay6_q_net: std_logic_vector(11 downto 0); signal delay9_q_net: std_logic_vector(9 downto 0); signal dir: std_logic_vector(11 downto 0); signal dir_x0: std_logic_vector(9 downto 0); signal enable_op_net_x0: std_logic; signal from_register_data_out_net_x1: std_logic_vector(31 downto 0); signal green: std_logic_vector(9 downto 0); signal havg: std_logic_vector(10 downto 0); signal havg_x0: std_logic_vector(11 downto 0); signal havg_x1: std_logic_vector(9 downto 0); signal hblank_delay_q_net_x0: std_logic; signal hblank_i_net_x0: std_logic; signal hsync_delay_q_net_x0: std_logic; signal hsync_i_net_x0: std_logic; signal mux7_y_net_x0: std_logic_vector(1 downto 0); signal mux9_y_net_x0: std_logic_vector(1 downto 0); signal red: std_logic_vector(9 downto 0); signal single_port_ram_data_out_net: std_logic_vector(9 downto 0); signal slice15_y_net: std_logic_vector(10 downto 0); signal slice16_y_net: std_logic_vector(10 downto 0); signal slice17_y_net_x0: std_logic; signal slice6_y_net: std_logic; signal slice7_y_net: std_logic_vector(7 downto 0); signal slice8_y_net: std_logic_vector(7 downto 0); signal slice9_y_net: std_logic_vector(7 downto 0); signal slice_y_net: std_logic; signal vavg: std_logic_vector(10 downto 0); signal vavg_x0: std_logic_vector(11 downto 0); signal vavg_x1: std_logic_vector(9 downto 0); signal vblank_delay_q_net_x0: std_logic; signal vblank_i_net_x1: std_logic; signal vsync_delay_q_net_x0: std_logic; signal vsync_i_net_x0: std_logic; signal xavg: std_logic_vector(9 downto 0); signal xcounter_op_net_x0: std_logic_vector(11 downto 0); signal ycounter_op_net_x0: std_logic_vector(11 downto 0); begin active_video_i_net_x1 <= avi; ce_1_sg_x1 <= ce_1; clk_1_sg_x1 <= clk_1; from_register_data_out_net_x1 <= from_register; hblank_i_net_x0 <= hbi; hsync_i_net_x0 <= hsi; vblank_i_net_x1 <= vbi; concat2_y_net_x0 <= vdi; vsync_i_net_x0 <= vsi; avo <= active_video_delay_q_net_x0; hbo <= hblank_delay_q_net_x0; hso <= hsync_delay_q_net_x0; vbo <= vblank_delay_q_net_x0; vdo <= data_delay_q_net_x0; vso <= vsync_delay_q_net_x0; active_video_delay: entity work.delay_1b0d89c05a port map ( ce => ce_1_sg_x1, clk => clk_1_sg_x1, clr => '0', d(0) => active_video_i_net_x1, q(0) => active_video_delay_q_net_x0 ); addsub1: entity work.xladdsub generic map ( a_arith => xlUnsigned, a_bin_pt => 0, a_width => 10, b_arith => xlUnsigned, b_bin_pt => 0, b_width => 10, c_has_c_out => 0, c_latency => 0, c_output_width => 11, core_name0 => "addsb_11_0_c25f95ce6b0868c9", extra_registers => 0, full_s_arith => 1, full_s_width => 11, latency => 0, overflow => 1, quantization => 1, s_arith => xlUnsigned, s_bin_pt => 0, s_width => 11 ) port map ( a => d0, b => delay12_q_net, ce => ce_1_sg_x1, clk => clk_1_sg_x1, clr => '0', en => "1", s => addsub1_s_net ); addsub2: entity work.xladdsub generic map ( a_arith => xlUnsigned, a_bin_pt => 0, a_width => 10, b_arith => xlUnsigned, b_bin_pt => 0, b_width => 10, c_has_c_out => 0, c_latency => 0, c_output_width => 11, core_name0 => "addsb_11_0_c25f95ce6b0868c9", extra_registers => 0, full_s_arith => 1, full_s_width => 11, latency => 0, overflow => 1, quantization => 1, s_arith => xlUnsigned, s_bin_pt => 0, s_width => 11 ) port map ( a => delay1_q_net, b => delay11_q_net, ce => ce_1_sg_x1, clk => clk_1_sg_x1, clr => '0', en => "1", s => vavg ); addsub3: entity work.xladdsub generic map ( a_arith => xlUnsigned, a_bin_pt => 0, a_width => 11, b_arith => xlUnsigned, b_bin_pt => 0, b_width => 11, c_has_c_out => 0, c_latency => 0, c_output_width => 12, core_name0 => "addsb_11_0_a629aff4db5bb1c8", extra_registers => 0, full_s_arith => 1, full_s_width => 12, latency => 0, overflow => 1, quantization => 1, s_arith => xlUnsigned, s_bin_pt => 0, s_width => 12 ) port map ( a => havg, b => vavg, ce => ce_1_sg_x1, clk => clk_1_sg_x1, clr => '0', en => "1", s => davg ); addsub5: entity work.xladdsub generic map ( a_arith => xlUnsigned, a_bin_pt => 0, a_width => 10, b_arith => xlUnsigned, b_bin_pt => 0, b_width => 10, c_has_c_out => 0, c_latency => 0, c_output_width => 11, core_name0 => "addsb_11_0_c25f95ce6b0868c9", extra_registers => 0, full_s_arith => 1, full_s_width => 11, latency => 0, overflow => 1, quantization => 1, s_arith => xlUnsigned, s_bin_pt => 0, s_width => 11 ) port map ( a => d3, b => delay14_q_net, ce => ce_1_sg_x1, clk => clk_1_sg_x1, clr => '0', en => "1", s => addsub5_s_net ); addsub6: entity work.xladdsub generic map ( a_arith => xlUnsigned, a_bin_pt => 0, a_width => 10, b_arith => xlUnsigned, b_bin_pt => 0, b_width => 10, c_has_c_out => 0, c_latency => 0, c_output_width => 11, core_name0 => "addsb_11_0_c25f95ce6b0868c9", extra_registers => 0, full_s_arith => 1, full_s_width => 11, latency => 0, overflow => 1, quantization => 1, s_arith => xlUnsigned, s_bin_pt => 0, s_width => 11 ) port map ( a => d1, b => delay13_q_net, ce => ce_1_sg_x1, clk => clk_1_sg_x1, clr => '0', en => "1", s => havg ); addsub7: entity work.xladdsub generic map ( a_arith => xlUnsigned, a_bin_pt => 0, a_width => 11, b_arith => xlUnsigned, b_bin_pt => 0, b_width => 11, c_has_c_out => 0, c_latency => 0, c_output_width => 12, core_name0 => "addsb_11_0_a629aff4db5bb1c8", extra_registers => 0, full_s_arith => 1, full_s_width => 12, latency => 0, overflow => 1, quantization => 1, s_arith => xlUnsigned, s_bin_pt => 0, s_width => 12 ) port map ( a => addsub1_s_net, b => addsub5_s_net, ce => ce_1_sg_x1, clk => clk_1_sg_x1, clr => '0', en => "1", s => davg_x0 ); concat: entity work.concat_e6f5ee726b port map ( ce => '0', clk => '0', clr => '0', in0(0) => slice_y_net, in1(0) => slice6_y_net, y => concat_y_net ); concat1: entity work.concat_d0d1b9533e port map ( ce => '0', clk => '0', clr => '0', in0 => slice7_y_net, in1 => slice8_y_net, in2 => slice9_y_net, y => concat1_y_net ); convert: entity work.xlconvert generic map ( bool_conversion => 1, din_arith => 1, din_bin_pt => 0, din_width => 1, dout_arith => 1, dout_bin_pt => 0, dout_width => 1, latency => 0, overflow => xlWrap, quantization => xlTruncate ) port map ( ce => ce_1_sg_x1, clk => clk_1_sg_x1, clr => '0', din(0) => active_video_i_net_x1, en => "1", dout(0) => convert_dout_net ); data_delay: entity work.delay_e1f6cb3ad9 port map ( ce => ce_1_sg_x1, clk => clk_1_sg_x1, clr => '0', d => concat1_y_net, q => data_delay_q_net_x0 ); delay1: entity work.delay_33cb3f7e58 port map ( ce => ce_1_sg_x1, clk => clk_1_sg_x1, clr => '0', d => d0, en(0) => enable_op_net_x0, q => delay1_q_net ); delay10: entity work.delay_33cb3f7e58 port map ( ce => ce_1_sg_x1, clk => clk_1_sg_x1, clr => '0', d => d1, en(0) => enable_op_net_x0, q => delay10_q_net ); delay11: entity work.delay_33cb3f7e58 port map ( ce => ce_1_sg_x1, clk => clk_1_sg_x1, clr => '0', d => d3, en(0) => enable_op_net_x0, q => delay11_q_net ); delay12: entity work.delay_33cb3f7e58 port map ( ce => ce_1_sg_x1, clk => clk_1_sg_x1, clr => '0', d => delay1_q_net, en(0) => enable_op_net_x0, q => delay12_q_net ); delay13: entity work.delay_33cb3f7e58 port map ( ce => ce_1_sg_x1, clk => clk_1_sg_x1, clr => '0', d => delay10_q_net, en(0) => enable_op_net_x0, q => delay13_q_net ); delay14: entity work.delay_33cb3f7e58 port map ( ce => ce_1_sg_x1, clk => clk_1_sg_x1, clr => '0', d => delay11_q_net, en(0) => enable_op_net_x0, q => delay14_q_net ); delay15: entity work.delay_0025330cf4 port map ( ce => ce_1_sg_x1, clk => clk_1_sg_x1, clr => '0', d => concat_y_net, en(0) => enable_op_net_x0, q => delay15_q_net_x0 ); delay17: entity work.delay_ec78404abf port map ( ce => ce_1_sg_x1, clk => clk_1_sg_x1, clr => '0', d => davg_x0, en(0) => enable_op_net_x0, q => delay17_q_net ); delay19: entity work.delay_ec78404abf port map ( ce => ce_1_sg_x1, clk => clk_1_sg_x1, clr => '0', d => dir, en(0) => enable_op_net_x0, q => delay19_q_net ); delay20: entity work.delay_ec78404abf port map ( ce => ce_1_sg_x1, clk => clk_1_sg_x1, clr => '0', d => davg, en(0) => enable_op_net_x0, q => delay20_q_net ); delay5: entity work.delay_ec78404abf port map ( ce => ce_1_sg_x1, clk => clk_1_sg_x1, clr => '0', d => havg_x0, en(0) => enable_op_net_x0, q => delay5_q_net ); delay6: entity work.delay_ec78404abf port map ( ce => ce_1_sg_x1, clk => clk_1_sg_x1, clr => '0', d => vavg_x0, en(0) => enable_op_net_x0, q => delay6_q_net ); delay7: entity work.delay_0fbdd36101 port map ( ce => ce_1_sg_x1, clk => clk_1_sg_x1, clr => '0', d => delay9_q_net, en(0) => enable_op_net_x0, q => d0 ); delay8: entity work.delay_33cb3f7e58 port map ( ce => ce_1_sg_x1, clk => clk_1_sg_x1, clr => '0', d => single_port_ram_data_out_net, en(0) => enable_op_net_x0, q => d1 ); delay9: entity work.delay_0fbdd36101 port map ( ce => ce_1_sg_x1, clk => clk_1_sg_x1, clr => '0', d => bayer_conv, en(0) => enable_op_net_x0, q => delay9_q_net ); enable: entity work.constant_6293007044 port map ( ce => '0', clk => '0', clr => '0', op(0) => enable_op_net_x0 ); hblank_delay: entity work.delay_1b0d89c05a port map ( ce => ce_1_sg_x1, clk => clk_1_sg_x1, clr => '0', d(0) => hblank_i_net_x0, q(0) => hblank_delay_q_net_x0 ); hsync_delay: entity work.delay_1b0d89c05a port map ( ce => ce_1_sg_x1, clk => clk_1_sg_x1, clr => '0', d(0) => hsync_i_net_x0, q(0) => hsync_delay_q_net_x0 ); mux2: entity work.mux_4fe5face7f port map ( ce => '0', clk => '0', clr => '0', d0 => dir_x0, d1 => xavg, sel(0) => slice17_y_net_x0, y => green ); mux3: entity work.mux_61418c8488 port map ( ce => '0', clk => '0', clr => '0', d0 => dir_x0, d1 => havg_x1, d2 => vavg_x1, d3 => davg_x1, sel => mux9_y_net_x0, y => blue ); mux4: entity work.mux_61418c8488 port map ( ce => '0', clk => '0', clr => '0', d0 => dir_x0, d1 => havg_x1, d2 => vavg_x1, d3 => davg_x1, sel => mux7_y_net_x0, y => red ); shift: entity work.shift_d9577b2c80 port map ( ce => ce_1_sg_x1, clk => clk_1_sg_x1, clr => '0', ip => havg, op => havg_x0 ); shift1: entity work.shift_d9577b2c80 port map ( ce => ce_1_sg_x1, clk => clk_1_sg_x1, clr => '0', ip => vavg, op => vavg_x0 ); shift2: entity work.shift_0a73a8a346 port map ( ce => ce_1_sg_x1, clk => clk_1_sg_x1, clr => '0', ip => delay10_q_net, op => dir ); single_port_ram: entity work.xlspram generic map ( c_address_width => 11, c_width => 10, core_name0 => "bmg_62_2be284cffc9a51ef", latency => 1 ) port map ( addr => slice15_y_net, ce => ce_1_sg_x1, clk => clk_1_sg_x1, data_in => delay9_q_net, en(0) => enable_op_net_x0, rst => "0", we(0) => convert_dout_net, data_out => single_port_ram_data_out_net ); single_port_ram1: entity work.xlspram generic map ( c_address_width => 11, c_width => 10, core_name0 => "bmg_62_2be284cffc9a51ef", latency => 1 ) port map ( addr => slice16_y_net, ce => ce_1_sg_x1, clk => clk_1_sg_x1, data_in => single_port_ram_data_out_net, en(0) => enable_op_net_x0, rst => "0", we(0) => convert_dout_net, data_out => d3 ); slice: entity work.xlslice generic map ( new_lsb => 0, new_msb => 0, x_width => 12, y_width => 1 ) port map ( x => ycounter_op_net_x0, y(0) => slice_y_net ); slice1: entity work.xlslice generic map ( new_lsb => 2, new_msb => 11, x_width => 12, y_width => 10 ) port map ( x => delay17_q_net, y => davg_x1 ); slice10: entity work.xlslice generic map ( new_lsb => 0, new_msb => 9, x_width => 10, y_width => 10 ) port map ( x => concat2_y_net_x0, y => bayer_conv ); slice15: entity work.xlslice generic map ( new_lsb => 0, new_msb => 10, x_width => 12, y_width => 11 ) port map ( x => xcounter_op_net_x0, y => slice15_y_net ); slice16: entity work.xlslice generic map ( new_lsb => 0, new_msb => 10, x_width => 12, y_width => 11 ) port map ( x => xcounter_op_net_x0, y => slice16_y_net ); slice2: entity work.xlslice generic map ( new_lsb => 2, new_msb => 11, x_width => 12, y_width => 10 ) port map ( x => delay5_q_net, y => havg_x1 ); slice3: entity work.xlslice generic map ( new_lsb => 2, new_msb => 11, x_width => 12, y_width => 10 ) port map ( x => delay19_q_net, y => dir_x0 ); slice4: entity work.xlslice generic map ( new_lsb => 2, new_msb => 11, x_width => 12, y_width => 10 ) port map ( x => delay6_q_net, y => vavg_x1 ); slice5: entity work.xlslice generic map ( new_lsb => 2, new_msb => 11, x_width => 12, y_width => 10 ) port map ( x => delay20_q_net, y => xavg ); slice6: entity work.xlslice generic map ( new_lsb => 0, new_msb => 0, x_width => 12, y_width => 1 ) port map ( x => xcounter_op_net_x0, y(0) => slice6_y_net ); slice7: entity work.xlslice generic map ( new_lsb => 2, new_msb => 9, x_width => 10, y_width => 8 ) port map ( x => red, y => slice7_y_net ); slice8: entity work.xlslice generic map ( new_lsb => 2, new_msb => 9, x_width => 10, y_width => 8 ) port map ( x => green, y => slice8_y_net ); slice9: entity work.xlslice generic map ( new_lsb => 2, new_msb => 9, x_width => 10, y_width => 8 ) port map ( x => blue, y => slice9_y_net ); subsystem_387011edf3: entity work.subsystem_entity_387011edf3 port map ( from_register => from_register_data_out_net_x1, pos => delay15_q_net_x0, bsel => mux9_y_net_x0, gsel => slice17_y_net_x0, rsel => mux7_y_net_x0 ); vblank_delay: entity work.delay_1b0d89c05a port map ( ce => ce_1_sg_x1, clk => clk_1_sg_x1, clr => '0', d(0) => vblank_i_net_x1, q(0) => vblank_delay_q_net_x0 ); vsync_delay: entity work.delay_1b0d89c05a port map ( ce => ce_1_sg_x1, clk => clk_1_sg_x1, clr => '0', d(0) => vsync_i_net_x0, q(0) => vsync_delay_q_net_x0 ); xy_ctrs_9e9b1c9cc9: entity work.xy_ctrs_entity_9e9b1c9cc9 port map ( av => active_video_i_net_x1, ce_1 => ce_1_sg_x1, clk_1 => clk_1_sg_x1, en => enable_op_net_x0, vb => vblank_i_net_x1, x => xcounter_op_net_x0, y => ycounter_op_net_x0 ); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; -- Generated from Simulink block "sg_cfa_gamma/gamma" entity gamma_entity_43073d24ce is port ( ce_1: in std_logic; clk_1: in std_logic; in1: in std_logic_vector(23 downto 0); out1: out std_logic_vector(23 downto 0) ); end gamma_entity_43073d24ce; architecture structural of gamma_entity_43073d24ce is signal blue: std_logic_vector(7 downto 0); signal ce_1_sg_x2: std_logic; signal clk_1_sg_x2: std_logic; signal concat_y_net_x0: std_logic_vector(23 downto 0); signal data_delay_q_net_x1: std_logic_vector(23 downto 0); signal green: std_logic_vector(7 downto 0); signal red: std_logic_vector(7 downto 0); signal rom_blue_data_net: std_logic_vector(7 downto 0); signal rom_green_data_net: std_logic_vector(7 downto 0); signal rom_red_data_net: std_logic_vector(7 downto 0); begin ce_1_sg_x2 <= ce_1; clk_1_sg_x2 <= clk_1; data_delay_q_net_x1 <= in1; out1 <= concat_y_net_x0; concat: entity work.concat_d0d1b9533e port map ( ce => '0', clk => '0', clr => '0', in0 => rom_red_data_net, in1 => rom_green_data_net, in2 => rom_blue_data_net, y => concat_y_net_x0 ); rom_blue: entity work.xlsprom generic map ( c_address_width => 8, c_width => 8, core_name0 => "bmg_62_efdcd0e54d01b373", latency => 1 ) port map ( addr => blue, ce => ce_1_sg_x2, clk => clk_1_sg_x2, en => "1", rst => "0", data => rom_blue_data_net ); rom_green: entity work.xlsprom generic map ( c_address_width => 8, c_width => 8, core_name0 => "bmg_62_efdcd0e54d01b373", latency => 1 ) port map ( addr => green, ce => ce_1_sg_x2, clk => clk_1_sg_x2, en => "1", rst => "0", data => rom_green_data_net ); rom_red: entity work.xlsprom generic map ( c_address_width => 8, c_width => 8, core_name0 => "bmg_62_efdcd0e54d01b373", latency => 1 ) port map ( addr => red, ce => ce_1_sg_x2, clk => clk_1_sg_x2, en => "1", rst => "0", data => rom_red_data_net ); slice15downto8: entity work.xlslice generic map ( new_lsb => 8, new_msb => 15, x_width => 24, y_width => 8 ) port map ( x => data_delay_q_net_x1, y => green ); slice23downto16: entity work.xlslice generic map ( new_lsb => 16, new_msb => 23, x_width => 24, y_width => 8 ) port map ( x => data_delay_q_net_x1, y => red ); slice7downto0: entity work.xlslice generic map ( new_lsb => 0, new_msb => 7, x_width => 24, y_width => 8 ) port map ( x => data_delay_q_net_x1, y => blue ); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; -- Generated from Simulink block "sg_cfa_gamma" entity sg_cfa_gamma is port ( active_video_i: in std_logic; ce_1: in std_logic; clk_1: in std_logic; data_out: in std_logic_vector(31 downto 0); dout: in std_logic_vector(31 downto 0); hblank_i: in std_logic; hsync_i: in std_logic; plb_abus: in std_logic_vector(31 downto 0); plb_ce_1: in std_logic; plb_clk_1: in std_logic; plb_pavalid: in std_logic; plb_rnw: in std_logic; plb_wrdbus: in std_logic_vector(31 downto 0); sg_plb_addrpref: in std_logic_vector(19 downto 0); splb_rst: in std_logic; vblank_i: in std_logic; video_data_i: in std_logic_vector(7 downto 0); vsync_i: in std_logic; active_video_o: out std_logic; data_in: out std_logic_vector(31 downto 0); en: out std_logic; hblank_o: out std_logic; hsync_o: out std_logic; sl_addrack: out std_logic; sl_rdcomp: out std_logic; sl_rddack: out std_logic; sl_rddbus: out std_logic_vector(31 downto 0); sl_wait: out std_logic; sl_wrcomp: out std_logic; sl_wrdack: out std_logic; vblank_o: out std_logic; video_data_o: out std_logic_vector(23 downto 0); vsync_o: out std_logic ); end sg_cfa_gamma; architecture structural of sg_cfa_gamma is attribute core_generation_info: string; attribute core_generation_info of structural : architecture is "sg_cfa_gamma,sysgen_core,{clock_period=10.00000000,clocking=Clock_Enables,sample_periods=1.00000000000 1.00000000000,testbench=0,total_blocks=223,xilinx_adder_subtracter_block=6,xilinx_binary_shift_operator_block=3,xilinx_bit_slice_extractor_block=29,xilinx_bitwise_expression_evaluator_block=3,xilinx_bus_concatenator_block=4,xilinx_bus_multiplexer_block=6,xilinx_constant_block_block=3,xilinx_counter_block=2,xilinx_delay_block=28,xilinx_edk_processor_block=1,xilinx_gateway_in_block=12,xilinx_gateway_out_block=22,xilinx_inverter_block=1,xilinx_mcode_block_block=2,xilinx_shared_memory_based_from_register_block=1,xilinx_shared_memory_based_to_register_block=1,xilinx_single_port_random_access_memory_block=2,xilinx_single_port_read_only_memory_block=3,xilinx_system_generator_block=1,xilinx_type_converter_block=4,}"; signal active_video_delay_q_net_x0: std_logic; signal active_video_i_net: std_logic; signal active_video_o_net: std_logic; signal ce_1_sg_x3: std_logic; signal clk_1_sg_x3: std_logic; signal concat2_y_net_x0: std_logic_vector(9 downto 0); signal constant_op_net: std_logic_vector(1 downto 0); signal data_delay_q_net_x1: std_logic_vector(23 downto 0); signal data_in_net: std_logic_vector(31 downto 0); signal data_out_net: std_logic_vector(31 downto 0); signal dout_net: std_logic_vector(31 downto 0); signal en_net: std_logic; signal hblank_delay_q_net_x0: std_logic; signal hblank_i_net: std_logic; signal hblank_o_net: std_logic; signal hsync_delay_q_net_x0: std_logic; signal hsync_i_net: std_logic; signal hsync_o_net: std_logic; signal plb_abus_net: std_logic_vector(31 downto 0); signal plb_ce_1_sg_x1: std_logic; signal plb_clk_1_sg_x1: std_logic; signal plb_pavalid_net: std_logic; signal plb_rnw_net: std_logic; signal plb_wrdbus_net: std_logic_vector(31 downto 0); signal sg_plb_addrpref_net: std_logic_vector(19 downto 0); signal sl_addrack_net: std_logic; signal sl_rdcomp_net: std_logic; signal sl_rddack_net: std_logic; signal sl_rddbus_net: std_logic_vector(31 downto 0); signal sl_wait_net: std_logic; signal sl_wrdack_x1: std_logic; signal splb_rst_net: std_logic; signal vblank_delay_q_net_x0: std_logic; signal vblank_i_net: std_logic; signal vblank_o_net: std_logic; signal video_data_i_net: std_logic_vector(7 downto 0); signal video_data_o_net: std_logic_vector(23 downto 0); signal vsync_delay_q_net_x0: std_logic; signal vsync_i_net: std_logic; signal vsync_o_net: std_logic; begin active_video_i_net <= active_video_i; ce_1_sg_x3 <= ce_1; clk_1_sg_x3 <= clk_1; data_out_net <= data_out; dout_net <= dout; hblank_i_net <= hblank_i; hsync_i_net <= hsync_i; plb_abus_net <= plb_abus; plb_ce_1_sg_x1 <= plb_ce_1; plb_clk_1_sg_x1 <= plb_clk_1; plb_pavalid_net <= plb_pavalid; plb_rnw_net <= plb_rnw; plb_wrdbus_net <= plb_wrdbus; sg_plb_addrpref_net <= sg_plb_addrpref; splb_rst_net <= splb_rst; vblank_i_net <= vblank_i; video_data_i_net <= video_data_i; vsync_i_net <= vsync_i; active_video_o <= active_video_o_net; data_in <= data_in_net; en <= en_net; hblank_o <= hblank_o_net; hsync_o <= hsync_o_net; sl_addrack <= sl_addrack_net; sl_rdcomp <= sl_rdcomp_net; sl_rddack <= sl_rddack_net; sl_rddbus <= sl_rddbus_net; sl_wait <= sl_wait_net; sl_wrcomp <= sl_wrdack_x1; sl_wrdack <= sl_wrdack_x1; vblank_o <= vblank_o_net; video_data_o <= video_data_o_net; vsync_o <= vsync_o_net; bayer_7e9fc9cbc8: entity work.bayer_entity_7e9fc9cbc8 port map ( avi => active_video_i_net, ce_1 => ce_1_sg_x3, clk_1 => clk_1_sg_x3, from_register => data_out_net, hbi => hblank_i_net, hsi => hsync_i_net, vbi => vblank_i_net, vdi => concat2_y_net_x0, vsi => vsync_i_net, avo => active_video_delay_q_net_x0, hbo => hblank_delay_q_net_x0, hso => hsync_delay_q_net_x0, vbo => vblank_delay_q_net_x0, vdo => data_delay_q_net_x1, vso => vsync_delay_q_net_x0 ); concat2: entity work.concat_8712d31083 port map ( ce => '0', clk => '0', clr => '0', in0 => video_data_i_net, in1 => constant_op_net, y => concat2_y_net_x0 ); constant_x0: entity work.constant_cda50df78a port map ( ce => '0', clk => '0', clr => '0', op => constant_op_net ); delay1: entity work.delay_5753e4c658 port map ( ce => ce_1_sg_x3, clk => clk_1_sg_x3, clr => '0', d(0) => hsync_delay_q_net_x0, q(0) => hsync_o_net ); delay2: entity work.delay_5753e4c658 port map ( ce => ce_1_sg_x3, clk => clk_1_sg_x3, clr => '0', d(0) => vblank_delay_q_net_x0, q(0) => vblank_o_net ); delay3: entity work.delay_5753e4c658 port map ( ce => ce_1_sg_x3, clk => clk_1_sg_x3, clr => '0', d(0) => hblank_delay_q_net_x0, q(0) => hblank_o_net ); delay4: entity work.delay_5753e4c658 port map ( ce => ce_1_sg_x3, clk => clk_1_sg_x3, clr => '0', d(0) => vsync_delay_q_net_x0, q(0) => vsync_o_net ); delay5: entity work.delay_5753e4c658 port map ( ce => ce_1_sg_x3, clk => clk_1_sg_x3, clr => '0', d(0) => active_video_delay_q_net_x0, q(0) => active_video_o_net ); edk_processor_33f025737d: entity work.edk_processor_entity_33f025737d port map ( plb_abus => plb_abus_net, plb_ce_1 => plb_ce_1_sg_x1, plb_clk_1 => plb_clk_1_sg_x1, plb_pavalid => plb_pavalid_net, plb_rnw => plb_rnw_net, plb_wrdbus => plb_wrdbus_net, sg_plb_addrpref => sg_plb_addrpref_net, splb_rst => splb_rst_net, to_register => dout_net, constant5_x0 => sl_wait_net, plb_decode_x0 => sl_addrack_net, plb_decode_x1 => sl_rdcomp_net, plb_decode_x2 => sl_wrdack_x1, plb_decode_x3 => sl_rddack_net, plb_decode_x4 => sl_rddbus_net, plb_memmap_x0 => data_in_net, plb_memmap_x1 => en_net ); gamma_43073d24ce: entity work.gamma_entity_43073d24ce port map ( ce_1 => ce_1_sg_x3, clk_1 => clk_1_sg_x3, in1 => data_delay_q_net_x1, out1 => video_data_o_net ); end structural;
gpl-3.0
470d6a9f8cc3d2061fdde49a9204fe7a
0.575567
3.28045
false
false
false
false
GSimas/EEL5105
Eletr-Digital/Projeto Final/PROJETO COFRE FUNCIONANDO/clockbuzzer1k.vhd
1
4,617
-- megafunction wizard: %LPM_COUNTER% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: lpm_counter -- ============================================================ -- File Name: clockbuzzer1k.vhd -- Megafunction Name(s): -- lpm_counter -- -- Simulation Library Files(s): -- lpm -- ============================================================ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- -- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition -- ************************************************************ --Copyright (C) 1991-2010 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject --to the terms and conditions of the Altera Program License --Subscription Agreement, Altera MegaCore Function License --Agreement, or other applicable license agreement, including, --without limitation, that your use is for the sole purpose of --programming logic devices manufactured by Altera and sold by --Altera or its authorized distributors. Please refer to the --applicable agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY lpm; USE lpm.all; ENTITY clockbuzzer1k IS PORT ( clock : IN STD_LOGIC ; cout : OUT STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (29 DOWNTO 0) ); END clockbuzzer1k; ARCHITECTURE SYN OF clockbuzzer1k IS SIGNAL sub_wire0 : STD_LOGIC ; SIGNAL sub_wire1 : STD_LOGIC_VECTOR (29 DOWNTO 0); COMPONENT lpm_counter GENERIC ( lpm_direction : STRING; lpm_modulus : NATURAL; lpm_port_updown : STRING; lpm_type : STRING; lpm_width : NATURAL ); PORT ( clock : IN STD_LOGIC ; cout : OUT STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (29 DOWNTO 0) ); END COMPONENT; BEGIN cout <= sub_wire0; q <= sub_wire1(29 DOWNTO 0); lpm_counter_component : lpm_counter GENERIC MAP ( lpm_direction => "UP", lpm_modulus => 83333, lpm_port_updown => "PORT_UNUSED", lpm_type => "LPM_COUNTER", lpm_width => 30 ) PORT MAP ( clock => clock, cout => sub_wire0, q => sub_wire1 ); END SYN; -- ============================================================ -- CNX file retrieval info -- ============================================================ -- Retrieval info: PRIVATE: ACLR NUMERIC "0" -- Retrieval info: PRIVATE: ALOAD NUMERIC "0" -- Retrieval info: PRIVATE: ASET NUMERIC "0" -- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1" -- Retrieval info: PRIVATE: CLK_EN NUMERIC "0" -- Retrieval info: PRIVATE: CNT_EN NUMERIC "0" -- Retrieval info: PRIVATE: CarryIn NUMERIC "0" -- Retrieval info: PRIVATE: CarryOut NUMERIC "1" -- Retrieval info: PRIVATE: Direction NUMERIC "0" -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" -- Retrieval info: PRIVATE: ModulusCounter NUMERIC "1" -- Retrieval info: PRIVATE: ModulusValue NUMERIC "83333" -- Retrieval info: PRIVATE: SCLR NUMERIC "0" -- Retrieval info: PRIVATE: SLOAD NUMERIC "0" -- Retrieval info: PRIVATE: SSET NUMERIC "0" -- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: nBit NUMERIC "30" -- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP" -- Retrieval info: CONSTANT: LPM_MODULUS NUMERIC "83333" -- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER" -- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "30" -- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock -- Retrieval info: USED_PORT: cout 0 0 0 0 OUTPUT NODEFVAL cout -- Retrieval info: USED_PORT: q 0 0 30 0 OUTPUT NODEFVAL q[29..0] -- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 -- Retrieval info: CONNECT: q 0 0 30 0 @q 0 0 30 0 -- Retrieval info: CONNECT: cout 0 0 0 0 @cout 0 0 0 0 -- Retrieval info: LIBRARY: lpm lpm.lpm_components.all -- Retrieval info: GEN_FILE: TYPE_NORMAL clockbuzzer1k.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL clockbuzzer1k.inc TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL clockbuzzer1k.cmp TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL clockbuzzer1k.bsf TRUE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL clockbuzzer1k_inst.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL clockbuzzer1k_waveforms.html TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL clockbuzzer1k_wave*.jpg FALSE -- Retrieval info: LIB_FILE: lpm
mit
f8cb2fca9908926f5cec40ba5b1218ad
0.659736
3.675955
false
false
false
false
fquinto/Wireless_sensor_network
Avnet_UPC/hdl/system.vhd
1
126,708
------------------------------------------------------------------------------- -- system.vhd ------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity system is port ( fpga_0_USB_UART_RX_pin : in std_logic; fpga_0_USB_UART_TX_pin : out std_logic; fpga_0_LEDS_4BIT_GPIO_IO_pin : inout std_logic_vector(0 to 3); fpga_0_CS_PUSH_3BIT_GPIO_IO_I_pin : in std_logic_vector(0 to 2); fpga_0_TEMP_SENSOR_Sda_pin : inout std_logic; fpga_0_TEMP_SENSOR_Scl_pin : inout std_logic; fpga_0_FLASH_2Mx16_Mem_A_pin : out std_logic_vector(10 to 30); fpga_0_FLASH_2Mx16_Mem_RPN_pin : out std_logic; fpga_0_FLASH_2Mx16_Mem_CEN_pin : out std_logic; fpga_0_FLASH_2Mx16_Mem_OEN_pin : out std_logic; fpga_0_FLASH_2Mx16_Mem_WEN_pin : out std_logic; fpga_0_FLASH_2Mx16_Mem_DQ_pin : inout std_logic_vector(0 to 15); fpga_0_FLASH_2Mx16_MEM_BYTEn_pin : out std_logic; fpga_0_clk_1_sys_clk_pin : in std_logic; fpga_0_rst_1_sys_rst_pin : in std_logic; fpga_0_MSP430_UART_TX_pin : out std_logic; fpga_0_MSP430_UART_RX_pin : in std_logic ); end system; architecture STRUCTURE of system is component microblaze_0_wrapper is port ( CLK : in std_logic; RESET : in std_logic; MB_RESET : in std_logic; INTERRUPT : in std_logic; EXT_BRK : in std_logic; EXT_NM_BRK : in std_logic; DBG_STOP : in std_logic; MB_Halted : out std_logic; MB_Error : out std_logic; INSTR : in std_logic_vector(0 to 31); IREADY : in std_logic; IWAIT : in std_logic; ICE : in std_logic; IUE : in std_logic; INSTR_ADDR : out std_logic_vector(0 to 31); IFETCH : out std_logic; I_AS : out std_logic; IPLB_M_ABort : out std_logic; IPLB_M_ABus : out std_logic_vector(0 to 31); IPLB_M_UABus : out std_logic_vector(0 to 31); IPLB_M_BE : out std_logic_vector(0 to 3); IPLB_M_busLock : out std_logic; IPLB_M_lockErr : out std_logic; IPLB_M_MSize : out std_logic_vector(0 to 1); IPLB_M_priority : out std_logic_vector(0 to 1); IPLB_M_rdBurst : out std_logic; IPLB_M_request : out std_logic; IPLB_M_RNW : out std_logic; IPLB_M_size : out std_logic_vector(0 to 3); IPLB_M_TAttribute : out std_logic_vector(0 to 15); IPLB_M_type : out std_logic_vector(0 to 2); IPLB_M_wrBurst : out std_logic; IPLB_M_wrDBus : out std_logic_vector(0 to 31); IPLB_MBusy : in std_logic; IPLB_MRdErr : in std_logic; IPLB_MWrErr : in std_logic; IPLB_MIRQ : in std_logic; IPLB_MWrBTerm : in std_logic; IPLB_MWrDAck : in std_logic; IPLB_MAddrAck : in std_logic; IPLB_MRdBTerm : in std_logic; IPLB_MRdDAck : in std_logic; IPLB_MRdDBus : in std_logic_vector(0 to 31); IPLB_MRdWdAddr : in std_logic_vector(0 to 3); IPLB_MRearbitrate : in std_logic; IPLB_MSSize : in std_logic_vector(0 to 1); IPLB_MTimeout : in std_logic; DATA_READ : in std_logic_vector(0 to 31); DREADY : in std_logic; DWAIT : in std_logic; DCE : in std_logic; DUE : in std_logic; DATA_WRITE : out std_logic_vector(0 to 31); DATA_ADDR : out std_logic_vector(0 to 31); D_AS : out std_logic; READ_STROBE : out std_logic; WRITE_STROBE : out std_logic; BYTE_ENABLE : out std_logic_vector(0 to 3); DPLB_M_ABort : out std_logic; DPLB_M_ABus : out std_logic_vector(0 to 31); DPLB_M_UABus : out std_logic_vector(0 to 31); DPLB_M_BE : out std_logic_vector(0 to 3); DPLB_M_busLock : out std_logic; DPLB_M_lockErr : out std_logic; DPLB_M_MSize : out std_logic_vector(0 to 1); DPLB_M_priority : out std_logic_vector(0 to 1); DPLB_M_rdBurst : out std_logic; DPLB_M_request : out std_logic; DPLB_M_RNW : out std_logic; DPLB_M_size : out std_logic_vector(0 to 3); DPLB_M_TAttribute : out std_logic_vector(0 to 15); DPLB_M_type : out std_logic_vector(0 to 2); DPLB_M_wrBurst : out std_logic; DPLB_M_wrDBus : out std_logic_vector(0 to 31); DPLB_MBusy : in std_logic; DPLB_MRdErr : in std_logic; DPLB_MWrErr : in std_logic; DPLB_MIRQ : in std_logic; DPLB_MWrBTerm : in std_logic; DPLB_MWrDAck : in std_logic; DPLB_MAddrAck : in std_logic; DPLB_MRdBTerm : in std_logic; DPLB_MRdDAck : in std_logic; DPLB_MRdDBus : in std_logic_vector(0 to 31); DPLB_MRdWdAddr : in std_logic_vector(0 to 3); DPLB_MRearbitrate : in std_logic; DPLB_MSSize : in std_logic_vector(0 to 1); DPLB_MTimeout : in std_logic; M_AXI_IP_AWID : out std_logic_vector(0 downto 0); M_AXI_IP_AWADDR : out std_logic_vector(31 downto 0); M_AXI_IP_AWLEN : out std_logic_vector(7 downto 0); M_AXI_IP_AWSIZE : out std_logic_vector(2 downto 0); M_AXI_IP_AWBURST : out std_logic_vector(1 downto 0); M_AXI_IP_AWLOCK : out std_logic; M_AXI_IP_AWCACHE : out std_logic_vector(3 downto 0); M_AXI_IP_AWPROT : out std_logic_vector(2 downto 0); M_AXI_IP_AWQOS : out std_logic_vector(3 downto 0); M_AXI_IP_AWVALID : out std_logic; M_AXI_IP_AWREADY : in std_logic; M_AXI_IP_WDATA : out std_logic_vector(31 downto 0); M_AXI_IP_WSTRB : out std_logic_vector(3 downto 0); M_AXI_IP_WLAST : out std_logic; M_AXI_IP_WVALID : out std_logic; M_AXI_IP_WREADY : in std_logic; M_AXI_IP_BID : in std_logic_vector(0 downto 0); M_AXI_IP_BRESP : in std_logic_vector(1 downto 0); M_AXI_IP_BVALID : in std_logic; M_AXI_IP_BREADY : out std_logic; M_AXI_IP_ARID : out std_logic_vector(0 downto 0); M_AXI_IP_ARADDR : out std_logic_vector(31 downto 0); M_AXI_IP_ARLEN : out std_logic_vector(7 downto 0); M_AXI_IP_ARSIZE : out std_logic_vector(2 downto 0); M_AXI_IP_ARBURST : out std_logic_vector(1 downto 0); M_AXI_IP_ARLOCK : out std_logic; M_AXI_IP_ARCACHE : out std_logic_vector(3 downto 0); M_AXI_IP_ARPROT : out std_logic_vector(2 downto 0); M_AXI_IP_ARQOS : out std_logic_vector(3 downto 0); M_AXI_IP_ARVALID : out std_logic; M_AXI_IP_ARREADY : in std_logic; M_AXI_IP_RID : in std_logic_vector(0 downto 0); M_AXI_IP_RDATA : in std_logic_vector(31 downto 0); M_AXI_IP_RRESP : in std_logic_vector(1 downto 0); M_AXI_IP_RLAST : in std_logic; M_AXI_IP_RVALID : in std_logic; M_AXI_IP_RREADY : out std_logic; M_AXI_DP_AWID : out std_logic_vector(0 downto 0); M_AXI_DP_AWADDR : out std_logic_vector(31 downto 0); M_AXI_DP_AWLEN : out std_logic_vector(7 downto 0); M_AXI_DP_AWSIZE : out std_logic_vector(2 downto 0); M_AXI_DP_AWBURST : out std_logic_vector(1 downto 0); M_AXI_DP_AWLOCK : out std_logic; M_AXI_DP_AWCACHE : out std_logic_vector(3 downto 0); M_AXI_DP_AWPROT : out std_logic_vector(2 downto 0); M_AXI_DP_AWQOS : out std_logic_vector(3 downto 0); M_AXI_DP_AWVALID : out std_logic; M_AXI_DP_AWREADY : in std_logic; M_AXI_DP_WDATA : out std_logic_vector(31 downto 0); M_AXI_DP_WSTRB : out std_logic_vector(3 downto 0); M_AXI_DP_WLAST : out std_logic; M_AXI_DP_WVALID : out std_logic; M_AXI_DP_WREADY : in std_logic; M_AXI_DP_BID : in std_logic_vector(0 downto 0); M_AXI_DP_BRESP : in std_logic_vector(1 downto 0); M_AXI_DP_BVALID : in std_logic; M_AXI_DP_BREADY : out std_logic; M_AXI_DP_ARID : out std_logic_vector(0 downto 0); M_AXI_DP_ARADDR : out std_logic_vector(31 downto 0); M_AXI_DP_ARLEN : out std_logic_vector(7 downto 0); M_AXI_DP_ARSIZE : out std_logic_vector(2 downto 0); M_AXI_DP_ARBURST : out std_logic_vector(1 downto 0); M_AXI_DP_ARLOCK : out std_logic; M_AXI_DP_ARCACHE : out std_logic_vector(3 downto 0); M_AXI_DP_ARPROT : out std_logic_vector(2 downto 0); M_AXI_DP_ARQOS : out std_logic_vector(3 downto 0); M_AXI_DP_ARVALID : out std_logic; M_AXI_DP_ARREADY : in std_logic; M_AXI_DP_RID : in std_logic_vector(0 downto 0); M_AXI_DP_RDATA : in std_logic_vector(31 downto 0); M_AXI_DP_RRESP : in std_logic_vector(1 downto 0); M_AXI_DP_RLAST : in std_logic; M_AXI_DP_RVALID : in std_logic; M_AXI_DP_RREADY : out std_logic; M_AXI_IC_AWID : out std_logic_vector(0 downto 0); M_AXI_IC_AWADDR : out std_logic_vector(31 downto 0); M_AXI_IC_AWLEN : out std_logic_vector(7 downto 0); M_AXI_IC_AWSIZE : out std_logic_vector(2 downto 0); M_AXI_IC_AWBURST : out std_logic_vector(1 downto 0); M_AXI_IC_AWLOCK : out std_logic; M_AXI_IC_AWCACHE : out std_logic_vector(3 downto 0); M_AXI_IC_AWPROT : out std_logic_vector(2 downto 0); M_AXI_IC_AWQOS : out std_logic_vector(3 downto 0); M_AXI_IC_AWVALID : out std_logic; M_AXI_IC_AWREADY : in std_logic; M_AXI_IC_WDATA : out std_logic_vector(31 downto 0); M_AXI_IC_WSTRB : out std_logic_vector(3 downto 0); M_AXI_IC_WLAST : out std_logic; M_AXI_IC_WVALID : out std_logic; M_AXI_IC_WREADY : in std_logic; M_AXI_IC_BID : in std_logic_vector(0 downto 0); M_AXI_IC_BRESP : in std_logic_vector(1 downto 0); M_AXI_IC_BVALID : in std_logic; M_AXI_IC_BREADY : out std_logic; M_AXI_IC_ARID : out std_logic_vector(0 downto 0); M_AXI_IC_ARADDR : out std_logic_vector(31 downto 0); M_AXI_IC_ARLEN : out std_logic_vector(7 downto 0); M_AXI_IC_ARSIZE : out std_logic_vector(2 downto 0); M_AXI_IC_ARBURST : out std_logic_vector(1 downto 0); M_AXI_IC_ARLOCK : out std_logic; M_AXI_IC_ARCACHE : out std_logic_vector(3 downto 0); M_AXI_IC_ARPROT : out std_logic_vector(2 downto 0); M_AXI_IC_ARQOS : out std_logic_vector(3 downto 0); M_AXI_IC_ARVALID : out std_logic; M_AXI_IC_ARREADY : in std_logic; M_AXI_IC_RID : in std_logic_vector(0 downto 0); M_AXI_IC_RDATA : in std_logic_vector(31 downto 0); M_AXI_IC_RRESP : in std_logic_vector(1 downto 0); M_AXI_IC_RLAST : in std_logic; M_AXI_IC_RVALID : in std_logic; M_AXI_IC_RREADY : out std_logic; M_AXI_DC_AWID : out std_logic_vector(0 downto 0); M_AXI_DC_AWADDR : out std_logic_vector(31 downto 0); M_AXI_DC_AWLEN : out std_logic_vector(7 downto 0); M_AXI_DC_AWSIZE : out std_logic_vector(2 downto 0); M_AXI_DC_AWBURST : out std_logic_vector(1 downto 0); M_AXI_DC_AWLOCK : out std_logic; M_AXI_DC_AWCACHE : out std_logic_vector(3 downto 0); M_AXI_DC_AWPROT : out std_logic_vector(2 downto 0); M_AXI_DC_AWQOS : out std_logic_vector(3 downto 0); M_AXI_DC_AWVALID : out std_logic; M_AXI_DC_AWREADY : in std_logic; M_AXI_DC_WDATA : out std_logic_vector(31 downto 0); M_AXI_DC_WSTRB : out std_logic_vector(3 downto 0); M_AXI_DC_WLAST : out std_logic; M_AXI_DC_WVALID : out std_logic; M_AXI_DC_WREADY : in std_logic; M_AXI_DC_BID : in std_logic_vector(0 downto 0); M_AXI_DC_BRESP : in std_logic_vector(1 downto 0); M_AXI_DC_BVALID : in std_logic; M_AXI_DC_BREADY : out std_logic; M_AXI_DC_ARID : out std_logic_vector(0 downto 0); M_AXI_DC_ARADDR : out std_logic_vector(31 downto 0); M_AXI_DC_ARLEN : out std_logic_vector(7 downto 0); M_AXI_DC_ARSIZE : out std_logic_vector(2 downto 0); M_AXI_DC_ARBURST : out std_logic_vector(1 downto 0); M_AXI_DC_ARLOCK : out std_logic; M_AXI_DC_ARCACHE : out std_logic_vector(3 downto 0); M_AXI_DC_ARPROT : out std_logic_vector(2 downto 0); M_AXI_DC_ARQOS : out std_logic_vector(3 downto 0); M_AXI_DC_ARVALID : out std_logic; M_AXI_DC_ARREADY : in std_logic; M_AXI_DC_RID : in std_logic_vector(0 downto 0); M_AXI_DC_RDATA : in std_logic_vector(31 downto 0); M_AXI_DC_RRESP : in std_logic_vector(1 downto 0); M_AXI_DC_RLAST : in std_logic; M_AXI_DC_RVALID : in std_logic; M_AXI_DC_RREADY : out std_logic; DBG_CLK : in std_logic; DBG_TDI : in std_logic; DBG_TDO : out std_logic; DBG_REG_EN : in std_logic_vector(0 to 7); DBG_SHIFT : in std_logic; DBG_CAPTURE : in std_logic; DBG_UPDATE : in std_logic; DEBUG_RST : in std_logic; Trace_Instruction : out std_logic_vector(0 to 31); Trace_Valid_Instr : out std_logic; Trace_PC : out std_logic_vector(0 to 31); Trace_Reg_Write : out std_logic; Trace_Reg_Addr : out std_logic_vector(0 to 4); Trace_MSR_Reg : out std_logic_vector(0 to 14); Trace_PID_Reg : out std_logic_vector(0 to 7); Trace_New_Reg_Value : out std_logic_vector(0 to 31); Trace_Exception_Taken : out std_logic; Trace_Exception_Kind : out std_logic_vector(0 to 4); Trace_Jump_Taken : out std_logic; Trace_Delay_Slot : out std_logic; Trace_Data_Address : out std_logic_vector(0 to 31); Trace_Data_Access : out std_logic; Trace_Data_Read : out std_logic; Trace_Data_Write : out std_logic; Trace_Data_Write_Value : out std_logic_vector(0 to 31); Trace_Data_Byte_Enable : out std_logic_vector(0 to 3); Trace_DCache_Req : out std_logic; Trace_DCache_Hit : out std_logic; Trace_DCache_Rdy : out std_logic; Trace_DCache_Read : out std_logic; Trace_ICache_Req : out std_logic; Trace_ICache_Hit : out std_logic; Trace_ICache_Rdy : out std_logic; Trace_OF_PipeRun : out std_logic; Trace_EX_PipeRun : out std_logic; Trace_MEM_PipeRun : out std_logic; Trace_MB_Halted : out std_logic; Trace_Jump_Hit : out std_logic; FSL0_S_CLK : out std_logic; FSL0_S_READ : out std_logic; FSL0_S_DATA : in std_logic_vector(0 to 31); FSL0_S_CONTROL : in std_logic; FSL0_S_EXISTS : in std_logic; FSL0_M_CLK : out std_logic; FSL0_M_WRITE : out std_logic; FSL0_M_DATA : out std_logic_vector(0 to 31); FSL0_M_CONTROL : out std_logic; FSL0_M_FULL : in std_logic; FSL1_S_CLK : out std_logic; FSL1_S_READ : out std_logic; FSL1_S_DATA : in std_logic_vector(0 to 31); FSL1_S_CONTROL : in std_logic; FSL1_S_EXISTS : in std_logic; FSL1_M_CLK : out std_logic; FSL1_M_WRITE : out std_logic; FSL1_M_DATA : out std_logic_vector(0 to 31); FSL1_M_CONTROL : out std_logic; FSL1_M_FULL : in std_logic; FSL2_S_CLK : out std_logic; FSL2_S_READ : out std_logic; FSL2_S_DATA : in std_logic_vector(0 to 31); FSL2_S_CONTROL : in std_logic; FSL2_S_EXISTS : in std_logic; FSL2_M_CLK : out std_logic; FSL2_M_WRITE : out std_logic; FSL2_M_DATA : out std_logic_vector(0 to 31); FSL2_M_CONTROL : out std_logic; FSL2_M_FULL : in std_logic; FSL3_S_CLK : out std_logic; FSL3_S_READ : out std_logic; FSL3_S_DATA : in std_logic_vector(0 to 31); FSL3_S_CONTROL : in std_logic; FSL3_S_EXISTS : in std_logic; FSL3_M_CLK : out std_logic; FSL3_M_WRITE : out std_logic; FSL3_M_DATA : out std_logic_vector(0 to 31); FSL3_M_CONTROL : out std_logic; FSL3_M_FULL : in std_logic; FSL4_S_CLK : out std_logic; FSL4_S_READ : out std_logic; FSL4_S_DATA : in std_logic_vector(0 to 31); FSL4_S_CONTROL : in std_logic; FSL4_S_EXISTS : in std_logic; FSL4_M_CLK : out std_logic; FSL4_M_WRITE : out std_logic; FSL4_M_DATA : out std_logic_vector(0 to 31); FSL4_M_CONTROL : out std_logic; FSL4_M_FULL : in std_logic; FSL5_S_CLK : out std_logic; FSL5_S_READ : out std_logic; FSL5_S_DATA : in std_logic_vector(0 to 31); FSL5_S_CONTROL : in std_logic; FSL5_S_EXISTS : in std_logic; FSL5_M_CLK : out std_logic; FSL5_M_WRITE : out std_logic; FSL5_M_DATA : out std_logic_vector(0 to 31); FSL5_M_CONTROL : out std_logic; FSL5_M_FULL : in std_logic; FSL6_S_CLK : out std_logic; FSL6_S_READ : out std_logic; FSL6_S_DATA : in std_logic_vector(0 to 31); FSL6_S_CONTROL : in std_logic; FSL6_S_EXISTS : in std_logic; FSL6_M_CLK : out std_logic; FSL6_M_WRITE : out std_logic; FSL6_M_DATA : out std_logic_vector(0 to 31); FSL6_M_CONTROL : out std_logic; FSL6_M_FULL : in std_logic; FSL7_S_CLK : out std_logic; FSL7_S_READ : out std_logic; FSL7_S_DATA : in std_logic_vector(0 to 31); FSL7_S_CONTROL : in std_logic; FSL7_S_EXISTS : in std_logic; FSL7_M_CLK : out std_logic; FSL7_M_WRITE : out std_logic; FSL7_M_DATA : out std_logic_vector(0 to 31); FSL7_M_CONTROL : out std_logic; FSL7_M_FULL : in std_logic; FSL8_S_CLK : out std_logic; FSL8_S_READ : out std_logic; FSL8_S_DATA : in std_logic_vector(0 to 31); FSL8_S_CONTROL : in std_logic; FSL8_S_EXISTS : in std_logic; FSL8_M_CLK : out std_logic; FSL8_M_WRITE : out std_logic; FSL8_M_DATA : out std_logic_vector(0 to 31); FSL8_M_CONTROL : out std_logic; FSL8_M_FULL : in std_logic; FSL9_S_CLK : out std_logic; FSL9_S_READ : out std_logic; FSL9_S_DATA : in std_logic_vector(0 to 31); FSL9_S_CONTROL : in std_logic; FSL9_S_EXISTS : in std_logic; FSL9_M_CLK : out std_logic; FSL9_M_WRITE : out std_logic; FSL9_M_DATA : out std_logic_vector(0 to 31); FSL9_M_CONTROL : out std_logic; FSL9_M_FULL : in std_logic; FSL10_S_CLK : out std_logic; FSL10_S_READ : out std_logic; FSL10_S_DATA : in std_logic_vector(0 to 31); FSL10_S_CONTROL : in std_logic; FSL10_S_EXISTS : in std_logic; FSL10_M_CLK : out std_logic; FSL10_M_WRITE : out std_logic; FSL10_M_DATA : out std_logic_vector(0 to 31); FSL10_M_CONTROL : out std_logic; FSL10_M_FULL : in std_logic; FSL11_S_CLK : out std_logic; FSL11_S_READ : out std_logic; FSL11_S_DATA : in std_logic_vector(0 to 31); FSL11_S_CONTROL : in std_logic; FSL11_S_EXISTS : in std_logic; FSL11_M_CLK : out std_logic; FSL11_M_WRITE : out std_logic; FSL11_M_DATA : out std_logic_vector(0 to 31); FSL11_M_CONTROL : out std_logic; FSL11_M_FULL : in std_logic; FSL12_S_CLK : out std_logic; FSL12_S_READ : out std_logic; FSL12_S_DATA : in std_logic_vector(0 to 31); FSL12_S_CONTROL : in std_logic; FSL12_S_EXISTS : in std_logic; FSL12_M_CLK : out std_logic; FSL12_M_WRITE : out std_logic; FSL12_M_DATA : out std_logic_vector(0 to 31); FSL12_M_CONTROL : out std_logic; FSL12_M_FULL : in std_logic; FSL13_S_CLK : out std_logic; FSL13_S_READ : out std_logic; FSL13_S_DATA : in std_logic_vector(0 to 31); FSL13_S_CONTROL : in std_logic; FSL13_S_EXISTS : in std_logic; FSL13_M_CLK : out std_logic; FSL13_M_WRITE : out std_logic; FSL13_M_DATA : out std_logic_vector(0 to 31); FSL13_M_CONTROL : out std_logic; FSL13_M_FULL : in std_logic; FSL14_S_CLK : out std_logic; FSL14_S_READ : out std_logic; FSL14_S_DATA : in std_logic_vector(0 to 31); FSL14_S_CONTROL : in std_logic; FSL14_S_EXISTS : in std_logic; FSL14_M_CLK : out std_logic; FSL14_M_WRITE : out std_logic; FSL14_M_DATA : out std_logic_vector(0 to 31); FSL14_M_CONTROL : out std_logic; FSL14_M_FULL : in std_logic; FSL15_S_CLK : out std_logic; FSL15_S_READ : out std_logic; FSL15_S_DATA : in std_logic_vector(0 to 31); FSL15_S_CONTROL : in std_logic; FSL15_S_EXISTS : in std_logic; FSL15_M_CLK : out std_logic; FSL15_M_WRITE : out std_logic; FSL15_M_DATA : out std_logic_vector(0 to 31); FSL15_M_CONTROL : out std_logic; FSL15_M_FULL : in std_logic; M0_AXIS_TLAST : out std_logic; M0_AXIS_TDATA : out std_logic_vector(31 downto 0); M0_AXIS_TVALID : out std_logic; M0_AXIS_TREADY : in std_logic; S0_AXIS_TLAST : in std_logic; S0_AXIS_TDATA : in std_logic_vector(31 downto 0); S0_AXIS_TVALID : in std_logic; S0_AXIS_TREADY : out std_logic; M1_AXIS_TLAST : out std_logic; M1_AXIS_TDATA : out std_logic_vector(31 downto 0); M1_AXIS_TVALID : out std_logic; M1_AXIS_TREADY : in std_logic; S1_AXIS_TLAST : in std_logic; S1_AXIS_TDATA : in std_logic_vector(31 downto 0); S1_AXIS_TVALID : in std_logic; S1_AXIS_TREADY : out std_logic; M2_AXIS_TLAST : out std_logic; M2_AXIS_TDATA : out std_logic_vector(31 downto 0); M2_AXIS_TVALID : out std_logic; M2_AXIS_TREADY : in std_logic; S2_AXIS_TLAST : in std_logic; S2_AXIS_TDATA : in std_logic_vector(31 downto 0); S2_AXIS_TVALID : in std_logic; S2_AXIS_TREADY : out std_logic; M3_AXIS_TLAST : out std_logic; M3_AXIS_TDATA : out std_logic_vector(31 downto 0); M3_AXIS_TVALID : out std_logic; M3_AXIS_TREADY : in std_logic; S3_AXIS_TLAST : in std_logic; S3_AXIS_TDATA : in std_logic_vector(31 downto 0); S3_AXIS_TVALID : in std_logic; S3_AXIS_TREADY : out std_logic; M4_AXIS_TLAST : out std_logic; M4_AXIS_TDATA : out std_logic_vector(31 downto 0); M4_AXIS_TVALID : out std_logic; M4_AXIS_TREADY : in std_logic; S4_AXIS_TLAST : in std_logic; S4_AXIS_TDATA : in std_logic_vector(31 downto 0); S4_AXIS_TVALID : in std_logic; S4_AXIS_TREADY : out std_logic; M5_AXIS_TLAST : out std_logic; M5_AXIS_TDATA : out std_logic_vector(31 downto 0); M5_AXIS_TVALID : out std_logic; M5_AXIS_TREADY : in std_logic; S5_AXIS_TLAST : in std_logic; S5_AXIS_TDATA : in std_logic_vector(31 downto 0); S5_AXIS_TVALID : in std_logic; S5_AXIS_TREADY : out std_logic; M6_AXIS_TLAST : out std_logic; M6_AXIS_TDATA : out std_logic_vector(31 downto 0); M6_AXIS_TVALID : out std_logic; M6_AXIS_TREADY : in std_logic; S6_AXIS_TLAST : in std_logic; S6_AXIS_TDATA : in std_logic_vector(31 downto 0); S6_AXIS_TVALID : in std_logic; S6_AXIS_TREADY : out std_logic; M7_AXIS_TLAST : out std_logic; M7_AXIS_TDATA : out std_logic_vector(31 downto 0); M7_AXIS_TVALID : out std_logic; M7_AXIS_TREADY : in std_logic; S7_AXIS_TLAST : in std_logic; S7_AXIS_TDATA : in std_logic_vector(31 downto 0); S7_AXIS_TVALID : in std_logic; S7_AXIS_TREADY : out std_logic; M8_AXIS_TLAST : out std_logic; M8_AXIS_TDATA : out std_logic_vector(31 downto 0); M8_AXIS_TVALID : out std_logic; M8_AXIS_TREADY : in std_logic; S8_AXIS_TLAST : in std_logic; S8_AXIS_TDATA : in std_logic_vector(31 downto 0); S8_AXIS_TVALID : in std_logic; S8_AXIS_TREADY : out std_logic; M9_AXIS_TLAST : out std_logic; M9_AXIS_TDATA : out std_logic_vector(31 downto 0); M9_AXIS_TVALID : out std_logic; M9_AXIS_TREADY : in std_logic; S9_AXIS_TLAST : in std_logic; S9_AXIS_TDATA : in std_logic_vector(31 downto 0); S9_AXIS_TVALID : in std_logic; S9_AXIS_TREADY : out std_logic; M10_AXIS_TLAST : out std_logic; M10_AXIS_TDATA : out std_logic_vector(31 downto 0); M10_AXIS_TVALID : out std_logic; M10_AXIS_TREADY : in std_logic; S10_AXIS_TLAST : in std_logic; S10_AXIS_TDATA : in std_logic_vector(31 downto 0); S10_AXIS_TVALID : in std_logic; S10_AXIS_TREADY : out std_logic; M11_AXIS_TLAST : out std_logic; M11_AXIS_TDATA : out std_logic_vector(31 downto 0); M11_AXIS_TVALID : out std_logic; M11_AXIS_TREADY : in std_logic; S11_AXIS_TLAST : in std_logic; S11_AXIS_TDATA : in std_logic_vector(31 downto 0); S11_AXIS_TVALID : in std_logic; S11_AXIS_TREADY : out std_logic; M12_AXIS_TLAST : out std_logic; M12_AXIS_TDATA : out std_logic_vector(31 downto 0); M12_AXIS_TVALID : out std_logic; M12_AXIS_TREADY : in std_logic; S12_AXIS_TLAST : in std_logic; S12_AXIS_TDATA : in std_logic_vector(31 downto 0); S12_AXIS_TVALID : in std_logic; S12_AXIS_TREADY : out std_logic; M13_AXIS_TLAST : out std_logic; M13_AXIS_TDATA : out std_logic_vector(31 downto 0); M13_AXIS_TVALID : out std_logic; M13_AXIS_TREADY : in std_logic; S13_AXIS_TLAST : in std_logic; S13_AXIS_TDATA : in std_logic_vector(31 downto 0); S13_AXIS_TVALID : in std_logic; S13_AXIS_TREADY : out std_logic; M14_AXIS_TLAST : out std_logic; M14_AXIS_TDATA : out std_logic_vector(31 downto 0); M14_AXIS_TVALID : out std_logic; M14_AXIS_TREADY : in std_logic; S14_AXIS_TLAST : in std_logic; S14_AXIS_TDATA : in std_logic_vector(31 downto 0); S14_AXIS_TVALID : in std_logic; S14_AXIS_TREADY : out std_logic; M15_AXIS_TLAST : out std_logic; M15_AXIS_TDATA : out std_logic_vector(31 downto 0); M15_AXIS_TVALID : out std_logic; M15_AXIS_TREADY : in std_logic; S15_AXIS_TLAST : in std_logic; S15_AXIS_TDATA : in std_logic_vector(31 downto 0); S15_AXIS_TVALID : in std_logic; S15_AXIS_TREADY : out std_logic; ICACHE_FSL_IN_CLK : out std_logic; ICACHE_FSL_IN_READ : out std_logic; ICACHE_FSL_IN_DATA : in std_logic_vector(0 to 31); ICACHE_FSL_IN_CONTROL : in std_logic; ICACHE_FSL_IN_EXISTS : in std_logic; ICACHE_FSL_OUT_CLK : out std_logic; ICACHE_FSL_OUT_WRITE : out std_logic; ICACHE_FSL_OUT_DATA : out std_logic_vector(0 to 31); ICACHE_FSL_OUT_CONTROL : out std_logic; ICACHE_FSL_OUT_FULL : in std_logic; DCACHE_FSL_IN_CLK : out std_logic; DCACHE_FSL_IN_READ : out std_logic; DCACHE_FSL_IN_DATA : in std_logic_vector(0 to 31); DCACHE_FSL_IN_CONTROL : in std_logic; DCACHE_FSL_IN_EXISTS : in std_logic; DCACHE_FSL_OUT_CLK : out std_logic; DCACHE_FSL_OUT_WRITE : out std_logic; DCACHE_FSL_OUT_DATA : out std_logic_vector(0 to 31); DCACHE_FSL_OUT_CONTROL : out std_logic; DCACHE_FSL_OUT_FULL : in std_logic ); end component; component mb_plb_wrapper is port ( PLB_Clk : in std_logic; SYS_Rst : in std_logic; PLB_Rst : out std_logic; SPLB_Rst : out std_logic_vector(0 to 8); MPLB_Rst : out std_logic_vector(0 to 1); PLB_dcrAck : out std_logic; PLB_dcrDBus : out std_logic_vector(0 to 31); DCR_ABus : in std_logic_vector(0 to 9); DCR_DBus : in std_logic_vector(0 to 31); DCR_Read : in std_logic; DCR_Write : in std_logic; M_ABus : in std_logic_vector(0 to 63); M_UABus : in std_logic_vector(0 to 63); M_BE : in std_logic_vector(0 to 7); M_RNW : in std_logic_vector(0 to 1); M_abort : in std_logic_vector(0 to 1); M_busLock : in std_logic_vector(0 to 1); M_TAttribute : in std_logic_vector(0 to 31); M_lockErr : in std_logic_vector(0 to 1); M_MSize : in std_logic_vector(0 to 3); M_priority : in std_logic_vector(0 to 3); M_rdBurst : in std_logic_vector(0 to 1); M_request : in std_logic_vector(0 to 1); M_size : in std_logic_vector(0 to 7); M_type : in std_logic_vector(0 to 5); M_wrBurst : in std_logic_vector(0 to 1); M_wrDBus : in std_logic_vector(0 to 63); Sl_addrAck : in std_logic_vector(0 to 8); Sl_MRdErr : in std_logic_vector(0 to 17); Sl_MWrErr : in std_logic_vector(0 to 17); Sl_MBusy : in std_logic_vector(0 to 17); Sl_rdBTerm : in std_logic_vector(0 to 8); Sl_rdComp : in std_logic_vector(0 to 8); Sl_rdDAck : in std_logic_vector(0 to 8); Sl_rdDBus : in std_logic_vector(0 to 287); Sl_rdWdAddr : in std_logic_vector(0 to 35); Sl_rearbitrate : in std_logic_vector(0 to 8); Sl_SSize : in std_logic_vector(0 to 17); Sl_wait : in std_logic_vector(0 to 8); Sl_wrBTerm : in std_logic_vector(0 to 8); Sl_wrComp : in std_logic_vector(0 to 8); Sl_wrDAck : in std_logic_vector(0 to 8); Sl_MIRQ : in std_logic_vector(0 to 17); PLB_MIRQ : out std_logic_vector(0 to 1); PLB_ABus : out std_logic_vector(0 to 31); PLB_UABus : out std_logic_vector(0 to 31); PLB_BE : out std_logic_vector(0 to 3); PLB_MAddrAck : out std_logic_vector(0 to 1); PLB_MTimeout : out std_logic_vector(0 to 1); PLB_MBusy : out std_logic_vector(0 to 1); PLB_MRdErr : out std_logic_vector(0 to 1); PLB_MWrErr : out std_logic_vector(0 to 1); PLB_MRdBTerm : out std_logic_vector(0 to 1); PLB_MRdDAck : out std_logic_vector(0 to 1); PLB_MRdDBus : out std_logic_vector(0 to 63); PLB_MRdWdAddr : out std_logic_vector(0 to 7); PLB_MRearbitrate : out std_logic_vector(0 to 1); PLB_MWrBTerm : out std_logic_vector(0 to 1); PLB_MWrDAck : out std_logic_vector(0 to 1); PLB_MSSize : out std_logic_vector(0 to 3); PLB_PAValid : out std_logic; PLB_RNW : out std_logic; PLB_SAValid : out std_logic; PLB_abort : out std_logic; PLB_busLock : out std_logic; PLB_TAttribute : out std_logic_vector(0 to 15); PLB_lockErr : out std_logic; PLB_masterID : out std_logic_vector(0 to 0); PLB_MSize : out std_logic_vector(0 to 1); PLB_rdPendPri : out std_logic_vector(0 to 1); PLB_wrPendPri : out std_logic_vector(0 to 1); PLB_rdPendReq : out std_logic; PLB_wrPendReq : out std_logic; PLB_rdBurst : out std_logic; PLB_rdPrim : out std_logic_vector(0 to 8); PLB_reqPri : out std_logic_vector(0 to 1); PLB_size : out std_logic_vector(0 to 3); PLB_type : out std_logic_vector(0 to 2); PLB_wrBurst : out std_logic; PLB_wrDBus : out std_logic_vector(0 to 31); PLB_wrPrim : out std_logic_vector(0 to 8); PLB_SaddrAck : out std_logic; PLB_SMRdErr : out std_logic_vector(0 to 1); PLB_SMWrErr : out std_logic_vector(0 to 1); PLB_SMBusy : out std_logic_vector(0 to 1); PLB_SrdBTerm : out std_logic; PLB_SrdComp : out std_logic; PLB_SrdDAck : out std_logic; PLB_SrdDBus : out std_logic_vector(0 to 31); PLB_SrdWdAddr : out std_logic_vector(0 to 3); PLB_Srearbitrate : out std_logic; PLB_Sssize : out std_logic_vector(0 to 1); PLB_Swait : out std_logic; PLB_SwrBTerm : out std_logic; PLB_SwrComp : out std_logic; PLB_SwrDAck : out std_logic; Bus_Error_Det : out std_logic ); end component; component ilmb_wrapper is port ( LMB_Clk : in std_logic; SYS_Rst : in std_logic; LMB_Rst : out std_logic; M_ABus : in std_logic_vector(0 to 31); M_ReadStrobe : in std_logic; M_WriteStrobe : in std_logic; M_AddrStrobe : in std_logic; M_DBus : in std_logic_vector(0 to 31); M_BE : in std_logic_vector(0 to 3); Sl_DBus : in std_logic_vector(0 to 31); Sl_Ready : in std_logic_vector(0 to 0); LMB_ABus : out std_logic_vector(0 to 31); LMB_ReadStrobe : out std_logic; LMB_WriteStrobe : out std_logic; LMB_AddrStrobe : out std_logic; LMB_ReadDBus : out std_logic_vector(0 to 31); LMB_WriteDBus : out std_logic_vector(0 to 31); LMB_Ready : out std_logic; LMB_BE : out std_logic_vector(0 to 3) ); end component; component dlmb_wrapper is port ( LMB_Clk : in std_logic; SYS_Rst : in std_logic; LMB_Rst : out std_logic; M_ABus : in std_logic_vector(0 to 31); M_ReadStrobe : in std_logic; M_WriteStrobe : in std_logic; M_AddrStrobe : in std_logic; M_DBus : in std_logic_vector(0 to 31); M_BE : in std_logic_vector(0 to 3); Sl_DBus : in std_logic_vector(0 to 31); Sl_Ready : in std_logic_vector(0 to 0); LMB_ABus : out std_logic_vector(0 to 31); LMB_ReadStrobe : out std_logic; LMB_WriteStrobe : out std_logic; LMB_AddrStrobe : out std_logic; LMB_ReadDBus : out std_logic_vector(0 to 31); LMB_WriteDBus : out std_logic_vector(0 to 31); LMB_Ready : out std_logic; LMB_BE : out std_logic_vector(0 to 3) ); end component; component dlmb_cntlr_wrapper is port ( LMB_Clk : in std_logic; LMB_Rst : in std_logic; LMB_ABus : in std_logic_vector(0 to 31); LMB_WriteDBus : in std_logic_vector(0 to 31); LMB_AddrStrobe : in std_logic; LMB_ReadStrobe : in std_logic; LMB_WriteStrobe : in std_logic; LMB_BE : in std_logic_vector(0 to 3); Sl_DBus : out std_logic_vector(0 to 31); Sl_Ready : out std_logic; BRAM_Rst_A : out std_logic; BRAM_Clk_A : out std_logic; BRAM_EN_A : out std_logic; BRAM_WEN_A : out std_logic_vector(0 to 3); BRAM_Addr_A : out std_logic_vector(0 to 31); BRAM_Din_A : in std_logic_vector(0 to 31); BRAM_Dout_A : out std_logic_vector(0 to 31) ); end component; component ilmb_cntlr_wrapper is port ( LMB_Clk : in std_logic; LMB_Rst : in std_logic; LMB_ABus : in std_logic_vector(0 to 31); LMB_WriteDBus : in std_logic_vector(0 to 31); LMB_AddrStrobe : in std_logic; LMB_ReadStrobe : in std_logic; LMB_WriteStrobe : in std_logic; LMB_BE : in std_logic_vector(0 to 3); Sl_DBus : out std_logic_vector(0 to 31); Sl_Ready : out std_logic; BRAM_Rst_A : out std_logic; BRAM_Clk_A : out std_logic; BRAM_EN_A : out std_logic; BRAM_WEN_A : out std_logic_vector(0 to 3); BRAM_Addr_A : out std_logic_vector(0 to 31); BRAM_Din_A : in std_logic_vector(0 to 31); BRAM_Dout_A : out std_logic_vector(0 to 31) ); end component; component lmb_bram_wrapper is port ( BRAM_Rst_A : in std_logic; BRAM_Clk_A : in std_logic; BRAM_EN_A : in std_logic; BRAM_WEN_A : in std_logic_vector(0 to 3); BRAM_Addr_A : in std_logic_vector(0 to 31); BRAM_Din_A : out std_logic_vector(0 to 31); BRAM_Dout_A : in std_logic_vector(0 to 31); BRAM_Rst_B : in std_logic; BRAM_Clk_B : in std_logic; BRAM_EN_B : in std_logic; BRAM_WEN_B : in std_logic_vector(0 to 3); BRAM_Addr_B : in std_logic_vector(0 to 31); BRAM_Din_B : out std_logic_vector(0 to 31); BRAM_Dout_B : in std_logic_vector(0 to 31) ); end component; component usb_uart_wrapper is port ( SPLB_Clk : in std_logic; SPLB_Rst : in std_logic; PLB_ABus : in std_logic_vector(0 to 31); PLB_PAValid : in std_logic; PLB_masterID : in std_logic_vector(0 to 0); PLB_RNW : in std_logic; PLB_BE : in std_logic_vector(0 to 3); PLB_size : in std_logic_vector(0 to 3); PLB_type : in std_logic_vector(0 to 2); PLB_wrDBus : in std_logic_vector(0 to 31); PLB_UABus : in std_logic_vector(0 to 31); PLB_SAValid : in std_logic; PLB_rdPrim : in std_logic; PLB_wrPrim : in std_logic; PLB_abort : in std_logic; PLB_busLock : in std_logic; PLB_MSize : in std_logic_vector(0 to 1); PLB_lockErr : in std_logic; PLB_wrBurst : in std_logic; PLB_rdBurst : in std_logic; PLB_wrPendReq : in std_logic; PLB_rdPendReq : in std_logic; PLB_wrPendPri : in std_logic_vector(0 to 1); PLB_rdPendPri : in std_logic_vector(0 to 1); PLB_reqPri : in std_logic_vector(0 to 1); PLB_TAttribute : in std_logic_vector(0 to 15); Sl_addrAck : out std_logic; Sl_SSize : out std_logic_vector(0 to 1); Sl_wait : out std_logic; Sl_rearbitrate : out std_logic; Sl_wrDAck : out std_logic; Sl_wrComp : out std_logic; Sl_rdDBus : out std_logic_vector(0 to 31); Sl_rdDAck : out std_logic; Sl_rdComp : out std_logic; Sl_MBusy : out std_logic_vector(0 to 1); Sl_MWrErr : out std_logic_vector(0 to 1); Sl_MRdErr : out std_logic_vector(0 to 1); Sl_wrBTerm : out std_logic; Sl_rdWdAddr : out std_logic_vector(0 to 3); Sl_rdBTerm : out std_logic; Sl_MIRQ : out std_logic_vector(0 to 1); RX : in std_logic; TX : out std_logic; Interrupt : out std_logic ); end component; component leds_4bit_wrapper is port ( SPLB_Clk : in std_logic; SPLB_Rst : in std_logic; PLB_ABus : in std_logic_vector(0 to 31); PLB_UABus : in std_logic_vector(0 to 31); PLB_PAValid : in std_logic; PLB_SAValid : in std_logic; PLB_rdPrim : in std_logic; PLB_wrPrim : in std_logic; PLB_masterID : in std_logic_vector(0 to 0); PLB_abort : in std_logic; PLB_busLock : in std_logic; PLB_RNW : in std_logic; PLB_BE : in std_logic_vector(0 to 3); PLB_MSize : in std_logic_vector(0 to 1); PLB_size : in std_logic_vector(0 to 3); PLB_type : in std_logic_vector(0 to 2); PLB_lockErr : in std_logic; PLB_wrDBus : in std_logic_vector(0 to 31); PLB_wrBurst : in std_logic; PLB_rdBurst : in std_logic; PLB_wrPendReq : in std_logic; PLB_rdPendReq : in std_logic; PLB_wrPendPri : in std_logic_vector(0 to 1); PLB_rdPendPri : in std_logic_vector(0 to 1); PLB_reqPri : in std_logic_vector(0 to 1); PLB_TAttribute : in std_logic_vector(0 to 15); Sl_addrAck : out std_logic; Sl_SSize : out std_logic_vector(0 to 1); Sl_wait : out std_logic; Sl_rearbitrate : out std_logic; Sl_wrDAck : out std_logic; Sl_wrComp : out std_logic; Sl_wrBTerm : out std_logic; Sl_rdDBus : out std_logic_vector(0 to 31); Sl_rdWdAddr : out std_logic_vector(0 to 3); Sl_rdDAck : out std_logic; Sl_rdComp : out std_logic; Sl_rdBTerm : out std_logic; Sl_MBusy : out std_logic_vector(0 to 1); Sl_MWrErr : out std_logic_vector(0 to 1); Sl_MRdErr : out std_logic_vector(0 to 1); Sl_MIRQ : out std_logic_vector(0 to 1); IP2INTC_Irpt : out std_logic; GPIO_IO_I : in std_logic_vector(0 to 3); GPIO_IO_O : out std_logic_vector(0 to 3); GPIO_IO_T : out std_logic_vector(0 to 3); GPIO2_IO_I : in std_logic_vector(0 to 31); GPIO2_IO_O : out std_logic_vector(0 to 31); GPIO2_IO_T : out std_logic_vector(0 to 31) ); end component; component cs_push_3bit_wrapper is port ( SPLB_Clk : in std_logic; SPLB_Rst : in std_logic; PLB_ABus : in std_logic_vector(0 to 31); PLB_UABus : in std_logic_vector(0 to 31); PLB_PAValid : in std_logic; PLB_SAValid : in std_logic; PLB_rdPrim : in std_logic; PLB_wrPrim : in std_logic; PLB_masterID : in std_logic_vector(0 to 0); PLB_abort : in std_logic; PLB_busLock : in std_logic; PLB_RNW : in std_logic; PLB_BE : in std_logic_vector(0 to 3); PLB_MSize : in std_logic_vector(0 to 1); PLB_size : in std_logic_vector(0 to 3); PLB_type : in std_logic_vector(0 to 2); PLB_lockErr : in std_logic; PLB_wrDBus : in std_logic_vector(0 to 31); PLB_wrBurst : in std_logic; PLB_rdBurst : in std_logic; PLB_wrPendReq : in std_logic; PLB_rdPendReq : in std_logic; PLB_wrPendPri : in std_logic_vector(0 to 1); PLB_rdPendPri : in std_logic_vector(0 to 1); PLB_reqPri : in std_logic_vector(0 to 1); PLB_TAttribute : in std_logic_vector(0 to 15); Sl_addrAck : out std_logic; Sl_SSize : out std_logic_vector(0 to 1); Sl_wait : out std_logic; Sl_rearbitrate : out std_logic; Sl_wrDAck : out std_logic; Sl_wrComp : out std_logic; Sl_wrBTerm : out std_logic; Sl_rdDBus : out std_logic_vector(0 to 31); Sl_rdWdAddr : out std_logic_vector(0 to 3); Sl_rdDAck : out std_logic; Sl_rdComp : out std_logic; Sl_rdBTerm : out std_logic; Sl_MBusy : out std_logic_vector(0 to 1); Sl_MWrErr : out std_logic_vector(0 to 1); Sl_MRdErr : out std_logic_vector(0 to 1); Sl_MIRQ : out std_logic_vector(0 to 1); IP2INTC_Irpt : out std_logic; GPIO_IO_I : in std_logic_vector(0 to 2); GPIO_IO_O : out std_logic_vector(0 to 2); GPIO_IO_T : out std_logic_vector(0 to 2); GPIO2_IO_I : in std_logic_vector(0 to 31); GPIO2_IO_O : out std_logic_vector(0 to 31); GPIO2_IO_T : out std_logic_vector(0 to 31) ); end component; component temp_sensor_wrapper is port ( Sda_I : in std_logic; Sda_O : out std_logic; Sda_T : out std_logic; Scl_I : in std_logic; Scl_O : out std_logic; Scl_T : out std_logic; Gpo : out std_logic_vector(31 to 31); IIC2INTC_Irpt : out std_logic; SPLB_Clk : in std_logic; SPLB_Rst : in std_logic; PLB_ABus : in std_logic_vector(0 to 31); PLB_UABus : in std_logic_vector(0 to 31); PLB_PAValid : in std_logic; PLB_SAValid : in std_logic; PLB_rdPrim : in std_logic; PLB_wrPrim : in std_logic; PLB_masterID : in std_logic_vector(0 to 0); PLB_abort : in std_logic; PLB_busLock : in std_logic; PLB_RNW : in std_logic; PLB_BE : in std_logic_vector(0 to 3); PLB_MSize : in std_logic_vector(0 to 1); PLB_size : in std_logic_vector(0 to 3); PLB_type : in std_logic_vector(0 to 2); PLB_lockErr : in std_logic; PLB_wrDBus : in std_logic_vector(0 to 31); PLB_wrBurst : in std_logic; PLB_rdBurst : in std_logic; PLB_wrPendReq : in std_logic; PLB_rdPendReq : in std_logic; PLB_wrPendPri : in std_logic_vector(0 to 1); PLB_rdPendPri : in std_logic_vector(0 to 1); PLB_reqPri : in std_logic_vector(0 to 1); PLB_TAttribute : in std_logic_vector(0 to 15); Sl_addrAck : out std_logic; Sl_SSize : out std_logic_vector(0 to 1); Sl_wait : out std_logic; Sl_rearbitrate : out std_logic; Sl_wrDAck : out std_logic; Sl_wrComp : out std_logic; Sl_wrBTerm : out std_logic; Sl_rdDBus : out std_logic_vector(0 to 31); Sl_rdWdAddr : out std_logic_vector(0 to 3); Sl_rdDAck : out std_logic; Sl_rdComp : out std_logic; Sl_rdBTerm : out std_logic; Sl_MBusy : out std_logic_vector(0 to 1); Sl_MWrErr : out std_logic_vector(0 to 1); Sl_MRdErr : out std_logic_vector(0 to 1); Sl_MIRQ : out std_logic_vector(0 to 1) ); end component; component flash_2mx16_wrapper is port ( MCH_SPLB_Clk : in std_logic; RdClk : in std_logic; MCH_SPLB_Rst : in std_logic; MCH0_Access_Control : in std_logic; MCH0_Access_Data : in std_logic_vector(0 to 31); MCH0_Access_Write : in std_logic; MCH0_Access_Full : out std_logic; MCH0_ReadData_Control : out std_logic; MCH0_ReadData_Data : out std_logic_vector(0 to 31); MCH0_ReadData_Read : in std_logic; MCH0_ReadData_Exists : out std_logic; MCH1_Access_Control : in std_logic; MCH1_Access_Data : in std_logic_vector(0 to 31); MCH1_Access_Write : in std_logic; MCH1_Access_Full : out std_logic; MCH1_ReadData_Control : out std_logic; MCH1_ReadData_Data : out std_logic_vector(0 to 31); MCH1_ReadData_Read : in std_logic; MCH1_ReadData_Exists : out std_logic; MCH2_Access_Control : in std_logic; MCH2_Access_Data : in std_logic_vector(0 to 31); MCH2_Access_Write : in std_logic; MCH2_Access_Full : out std_logic; MCH2_ReadData_Control : out std_logic; MCH2_ReadData_Data : out std_logic_vector(0 to 31); MCH2_ReadData_Read : in std_logic; MCH2_ReadData_Exists : out std_logic; MCH3_Access_Control : in std_logic; MCH3_Access_Data : in std_logic_vector(0 to 31); MCH3_Access_Write : in std_logic; MCH3_Access_Full : out std_logic; MCH3_ReadData_Control : out std_logic; MCH3_ReadData_Data : out std_logic_vector(0 to 31); MCH3_ReadData_Read : in std_logic; MCH3_ReadData_Exists : out std_logic; PLB_ABus : in std_logic_vector(0 to 31); PLB_UABus : in std_logic_vector(0 to 31); PLB_PAValid : in std_logic; PLB_SAValid : in std_logic; PLB_rdPrim : in std_logic; PLB_wrPrim : in std_logic; PLB_masterID : in std_logic_vector(0 to 0); PLB_abort : in std_logic; PLB_busLock : in std_logic; PLB_RNW : in std_logic; PLB_BE : in std_logic_vector(0 to 3); PLB_MSize : in std_logic_vector(0 to 1); PLB_size : in std_logic_vector(0 to 3); PLB_type : in std_logic_vector(0 to 2); PLB_lockErr : in std_logic; PLB_wrDBus : in std_logic_vector(0 to 31); PLB_wrBurst : in std_logic; PLB_rdBurst : in std_logic; PLB_wrPendReq : in std_logic; PLB_rdPendReq : in std_logic; PLB_wrPendPri : in std_logic_vector(0 to 1); PLB_rdPendPri : in std_logic_vector(0 to 1); PLB_reqPri : in std_logic_vector(0 to 1); PLB_TAttribute : in std_logic_vector(0 to 15); Sl_addrAck : out std_logic; Sl_SSize : out std_logic_vector(0 to 1); Sl_wait : out std_logic; Sl_rearbitrate : out std_logic; Sl_wrDAck : out std_logic; Sl_wrComp : out std_logic; Sl_wrBTerm : out std_logic; Sl_rdDBus : out std_logic_vector(0 to 31); Sl_rdWdAddr : out std_logic_vector(0 to 3); Sl_rdDAck : out std_logic; Sl_rdComp : out std_logic; Sl_rdBTerm : out std_logic; Sl_MBusy : out std_logic_vector(0 to 1); Sl_MWrErr : out std_logic_vector(0 to 1); Sl_MRdErr : out std_logic_vector(0 to 1); Sl_MIRQ : out std_logic_vector(0 to 1); Mem_DQ_I : in std_logic_vector(0 to 15); Mem_DQ_O : out std_logic_vector(0 to 15); Mem_DQ_T : out std_logic_vector(0 to 15); Mem_A : out std_logic_vector(0 to 31); Mem_RPN : out std_logic; Mem_CEN : out std_logic_vector(0 to 0); Mem_OEN : out std_logic_vector(0 to 0); Mem_WEN : out std_logic; Mem_QWEN : out std_logic_vector(0 to 1); Mem_BEN : out std_logic_vector(0 to 1); Mem_CE : out std_logic_vector(0 to 0); Mem_ADV_LDN : out std_logic; Mem_LBON : out std_logic; Mem_CKEN : out std_logic; Mem_RNW : out std_logic ); end component; component xps_timer_0_wrapper is port ( CaptureTrig0 : in std_logic; CaptureTrig1 : in std_logic; GenerateOut0 : out std_logic; GenerateOut1 : out std_logic; PWM0 : out std_logic; Interrupt : out std_logic; Freeze : in std_logic; SPLB_Clk : in std_logic; SPLB_Rst : in std_logic; PLB_ABus : in std_logic_vector(0 to 31); PLB_PAValid : in std_logic; PLB_masterID : in std_logic_vector(0 to 0); PLB_RNW : in std_logic; PLB_BE : in std_logic_vector(0 to 3); PLB_size : in std_logic_vector(0 to 3); PLB_type : in std_logic_vector(0 to 2); PLB_wrDBus : in std_logic_vector(0 to 31); Sl_addrAck : out std_logic; Sl_SSize : out std_logic_vector(0 to 1); Sl_wait : out std_logic; Sl_rearbitrate : out std_logic; Sl_wrDAck : out std_logic; Sl_wrComp : out std_logic; Sl_rdDBus : out std_logic_vector(0 to 31); Sl_rdDAck : out std_logic; Sl_rdComp : out std_logic; Sl_MBusy : out std_logic_vector(0 to 1); Sl_MWrErr : out std_logic_vector(0 to 1); Sl_MRdErr : out std_logic_vector(0 to 1); PLB_UABus : in std_logic_vector(0 to 31); PLB_SAValid : in std_logic; PLB_rdPrim : in std_logic; PLB_wrPrim : in std_logic; PLB_abort : in std_logic; PLB_busLock : in std_logic; PLB_MSize : in std_logic_vector(0 to 1); PLB_lockErr : in std_logic; PLB_wrBurst : in std_logic; PLB_rdBurst : in std_logic; PLB_wrPendReq : in std_logic; PLB_rdPendReq : in std_logic; PLB_wrPendPri : in std_logic_vector(0 to 1); PLB_rdPendPri : in std_logic_vector(0 to 1); PLB_reqPri : in std_logic_vector(0 to 1); PLB_TAttribute : in std_logic_vector(0 to 15); Sl_wrBTerm : out std_logic; Sl_rdWdAddr : out std_logic_vector(0 to 3); Sl_rdBTerm : out std_logic; Sl_MIRQ : out std_logic_vector(0 to 1) ); end component; component clock_generator_0_wrapper is port ( CLKIN : in std_logic; CLKOUT0 : out std_logic; CLKOUT1 : out std_logic; CLKOUT2 : out std_logic; CLKOUT3 : out std_logic; CLKOUT4 : out std_logic; CLKOUT5 : out std_logic; CLKOUT6 : out std_logic; CLKOUT7 : out std_logic; CLKOUT8 : out std_logic; CLKOUT9 : out std_logic; CLKOUT10 : out std_logic; CLKOUT11 : out std_logic; CLKOUT12 : out std_logic; CLKOUT13 : out std_logic; CLKOUT14 : out std_logic; CLKOUT15 : out std_logic; CLKFBIN : in std_logic; CLKFBOUT : out std_logic; PSCLK : in std_logic; PSEN : in std_logic; PSINCDEC : in std_logic; PSDONE : out std_logic; RST : in std_logic; LOCKED : out std_logic ); end component; component mdm_0_wrapper is port ( Interrupt : out std_logic; Debug_SYS_Rst : out std_logic; Ext_BRK : out std_logic; Ext_NM_BRK : out std_logic; S_AXI_ACLK : in std_logic; S_AXI_ARESETN : in std_logic; S_AXI_AWADDR : in std_logic_vector(31 downto 0); S_AXI_AWVALID : in std_logic; S_AXI_AWREADY : out std_logic; S_AXI_WDATA : in std_logic_vector(31 downto 0); S_AXI_WSTRB : in std_logic_vector(3 downto 0); S_AXI_WVALID : in std_logic; S_AXI_WREADY : out std_logic; S_AXI_BRESP : out std_logic_vector(1 downto 0); S_AXI_BVALID : out std_logic; S_AXI_BREADY : in std_logic; S_AXI_ARADDR : in std_logic_vector(31 downto 0); S_AXI_ARVALID : in std_logic; S_AXI_ARREADY : out std_logic; S_AXI_RDATA : out std_logic_vector(31 downto 0); S_AXI_RRESP : out std_logic_vector(1 downto 0); S_AXI_RVALID : out std_logic; S_AXI_RREADY : in std_logic; SPLB_Clk : in std_logic; SPLB_Rst : in std_logic; PLB_ABus : in std_logic_vector(0 to 31); PLB_UABus : in std_logic_vector(0 to 31); PLB_PAValid : in std_logic; PLB_SAValid : in std_logic; PLB_rdPrim : in std_logic; PLB_wrPrim : in std_logic; PLB_masterID : in std_logic_vector(0 to 0); PLB_abort : in std_logic; PLB_busLock : in std_logic; PLB_RNW : in std_logic; PLB_BE : in std_logic_vector(0 to 3); PLB_MSize : in std_logic_vector(0 to 1); PLB_size : in std_logic_vector(0 to 3); PLB_type : in std_logic_vector(0 to 2); PLB_lockErr : in std_logic; PLB_wrDBus : in std_logic_vector(0 to 31); PLB_wrBurst : in std_logic; PLB_rdBurst : in std_logic; PLB_wrPendReq : in std_logic; PLB_rdPendReq : in std_logic; PLB_wrPendPri : in std_logic_vector(0 to 1); PLB_rdPendPri : in std_logic_vector(0 to 1); PLB_reqPri : in std_logic_vector(0 to 1); PLB_TAttribute : in std_logic_vector(0 to 15); Sl_addrAck : out std_logic; Sl_SSize : out std_logic_vector(0 to 1); Sl_wait : out std_logic; Sl_rearbitrate : out std_logic; Sl_wrDAck : out std_logic; Sl_wrComp : out std_logic; Sl_wrBTerm : out std_logic; Sl_rdDBus : out std_logic_vector(0 to 31); Sl_rdWdAddr : out std_logic_vector(0 to 3); Sl_rdDAck : out std_logic; Sl_rdComp : out std_logic; Sl_rdBTerm : out std_logic; Sl_MBusy : out std_logic_vector(0 to 1); Sl_MWrErr : out std_logic_vector(0 to 1); Sl_MRdErr : out std_logic_vector(0 to 1); Sl_MIRQ : out std_logic_vector(0 to 1); Dbg_Clk_0 : out std_logic; Dbg_TDI_0 : out std_logic; Dbg_TDO_0 : in std_logic; Dbg_Reg_En_0 : out std_logic_vector(0 to 7); Dbg_Capture_0 : out std_logic; Dbg_Shift_0 : out std_logic; Dbg_Update_0 : out std_logic; Dbg_Rst_0 : out std_logic; Dbg_Clk_1 : out std_logic; Dbg_TDI_1 : out std_logic; Dbg_TDO_1 : in std_logic; Dbg_Reg_En_1 : out std_logic_vector(0 to 7); Dbg_Capture_1 : out std_logic; Dbg_Shift_1 : out std_logic; Dbg_Update_1 : out std_logic; Dbg_Rst_1 : out std_logic; Dbg_Clk_2 : out std_logic; Dbg_TDI_2 : out std_logic; Dbg_TDO_2 : in std_logic; Dbg_Reg_En_2 : out std_logic_vector(0 to 7); Dbg_Capture_2 : out std_logic; Dbg_Shift_2 : out std_logic; Dbg_Update_2 : out std_logic; Dbg_Rst_2 : out std_logic; Dbg_Clk_3 : out std_logic; Dbg_TDI_3 : out std_logic; Dbg_TDO_3 : in std_logic; Dbg_Reg_En_3 : out std_logic_vector(0 to 7); Dbg_Capture_3 : out std_logic; Dbg_Shift_3 : out std_logic; Dbg_Update_3 : out std_logic; Dbg_Rst_3 : out std_logic; Dbg_Clk_4 : out std_logic; Dbg_TDI_4 : out std_logic; Dbg_TDO_4 : in std_logic; Dbg_Reg_En_4 : out std_logic_vector(0 to 7); Dbg_Capture_4 : out std_logic; Dbg_Shift_4 : out std_logic; Dbg_Update_4 : out std_logic; Dbg_Rst_4 : out std_logic; Dbg_Clk_5 : out std_logic; Dbg_TDI_5 : out std_logic; Dbg_TDO_5 : in std_logic; Dbg_Reg_En_5 : out std_logic_vector(0 to 7); Dbg_Capture_5 : out std_logic; Dbg_Shift_5 : out std_logic; Dbg_Update_5 : out std_logic; Dbg_Rst_5 : out std_logic; Dbg_Clk_6 : out std_logic; Dbg_TDI_6 : out std_logic; Dbg_TDO_6 : in std_logic; Dbg_Reg_En_6 : out std_logic_vector(0 to 7); Dbg_Capture_6 : out std_logic; Dbg_Shift_6 : out std_logic; Dbg_Update_6 : out std_logic; Dbg_Rst_6 : out std_logic; Dbg_Clk_7 : out std_logic; Dbg_TDI_7 : out std_logic; Dbg_TDO_7 : in std_logic; Dbg_Reg_En_7 : out std_logic_vector(0 to 7); Dbg_Capture_7 : out std_logic; Dbg_Shift_7 : out std_logic; Dbg_Update_7 : out std_logic; Dbg_Rst_7 : out std_logic; bscan_tdi : out std_logic; bscan_reset : out std_logic; bscan_shift : out std_logic; bscan_update : out std_logic; bscan_capture : out std_logic; bscan_sel1 : out std_logic; bscan_drck1 : out std_logic; bscan_tdo1 : in std_logic; Ext_JTAG_DRCK : out std_logic; Ext_JTAG_RESET : out std_logic; Ext_JTAG_SEL : out std_logic; Ext_JTAG_CAPTURE : out std_logic; Ext_JTAG_SHIFT : out std_logic; Ext_JTAG_UPDATE : out std_logic; Ext_JTAG_TDI : out std_logic; Ext_JTAG_TDO : in std_logic ); end component; component proc_sys_reset_0_wrapper is port ( Slowest_sync_clk : in std_logic; Ext_Reset_In : in std_logic; Aux_Reset_In : in std_logic; MB_Debug_Sys_Rst : in std_logic; Core_Reset_Req_0 : in std_logic; Chip_Reset_Req_0 : in std_logic; System_Reset_Req_0 : in std_logic; Core_Reset_Req_1 : in std_logic; Chip_Reset_Req_1 : in std_logic; System_Reset_Req_1 : in std_logic; Dcm_locked : in std_logic; RstcPPCresetcore_0 : out std_logic; RstcPPCresetchip_0 : out std_logic; RstcPPCresetsys_0 : out std_logic; RstcPPCresetcore_1 : out std_logic; RstcPPCresetchip_1 : out std_logic; RstcPPCresetsys_1 : out std_logic; MB_Reset : out std_logic; Bus_Struct_Reset : out std_logic_vector(0 to 0); Peripheral_Reset : out std_logic_vector(0 to 0); Interconnect_aresetn : out std_logic_vector(0 to 0); Peripheral_aresetn : out std_logic_vector(0 to 0) ); end component; component xps_intc_0_wrapper is port ( SPLB_Clk : in std_logic; SPLB_Rst : in std_logic; PLB_ABus : in std_logic_vector(0 to 31); PLB_PAValid : in std_logic; PLB_masterID : in std_logic_vector(0 to 0); PLB_RNW : in std_logic; PLB_BE : in std_logic_vector(0 to 3); PLB_size : in std_logic_vector(0 to 3); PLB_type : in std_logic_vector(0 to 2); PLB_wrDBus : in std_logic_vector(0 to 31); PLB_UABus : in std_logic_vector(0 to 31); PLB_SAValid : in std_logic; PLB_rdPrim : in std_logic; PLB_wrPrim : in std_logic; PLB_abort : in std_logic; PLB_busLock : in std_logic; PLB_MSize : in std_logic_vector(0 to 1); PLB_lockErr : in std_logic; PLB_wrBurst : in std_logic; PLB_rdBurst : in std_logic; PLB_wrPendReq : in std_logic; PLB_rdPendReq : in std_logic; PLB_wrPendPri : in std_logic_vector(0 to 1); PLB_rdPendPri : in std_logic_vector(0 to 1); PLB_reqPri : in std_logic_vector(0 to 1); PLB_TAttribute : in std_logic_vector(0 to 15); Sl_addrAck : out std_logic; Sl_SSize : out std_logic_vector(0 to 1); Sl_wait : out std_logic; Sl_rearbitrate : out std_logic; Sl_wrDAck : out std_logic; Sl_wrComp : out std_logic; Sl_rdDBus : out std_logic_vector(0 to 31); Sl_rdDAck : out std_logic; Sl_rdComp : out std_logic; Sl_MBusy : out std_logic_vector(0 to 1); Sl_MWrErr : out std_logic_vector(0 to 1); Sl_MRdErr : out std_logic_vector(0 to 1); Sl_wrBTerm : out std_logic; Sl_rdWdAddr : out std_logic_vector(0 to 3); Sl_rdBTerm : out std_logic; Sl_MIRQ : out std_logic_vector(0 to 1); Intr : in std_logic_vector(3 downto 0); Irq : out std_logic ); end component; component msp430_uart_wrapper is port ( SPLB_Clk : in std_logic; SPLB_Rst : in std_logic; PLB_ABus : in std_logic_vector(0 to 31); PLB_PAValid : in std_logic; PLB_masterID : in std_logic_vector(0 to 0); PLB_RNW : in std_logic; PLB_BE : in std_logic_vector(0 to 3); PLB_size : in std_logic_vector(0 to 3); PLB_type : in std_logic_vector(0 to 2); PLB_wrDBus : in std_logic_vector(0 to 31); PLB_UABus : in std_logic_vector(0 to 31); PLB_SAValid : in std_logic; PLB_rdPrim : in std_logic; PLB_wrPrim : in std_logic; PLB_abort : in std_logic; PLB_busLock : in std_logic; PLB_MSize : in std_logic_vector(0 to 1); PLB_lockErr : in std_logic; PLB_wrBurst : in std_logic; PLB_rdBurst : in std_logic; PLB_wrPendReq : in std_logic; PLB_rdPendReq : in std_logic; PLB_wrPendPri : in std_logic_vector(0 to 1); PLB_rdPendPri : in std_logic_vector(0 to 1); PLB_reqPri : in std_logic_vector(0 to 1); PLB_TAttribute : in std_logic_vector(0 to 15); Sl_addrAck : out std_logic; Sl_SSize : out std_logic_vector(0 to 1); Sl_wait : out std_logic; Sl_rearbitrate : out std_logic; Sl_wrDAck : out std_logic; Sl_wrComp : out std_logic; Sl_rdDBus : out std_logic_vector(0 to 31); Sl_rdDAck : out std_logic; Sl_rdComp : out std_logic; Sl_MBusy : out std_logic_vector(0 to 1); Sl_MWrErr : out std_logic_vector(0 to 1); Sl_MRdErr : out std_logic_vector(0 to 1); Sl_wrBTerm : out std_logic; Sl_rdWdAddr : out std_logic_vector(0 to 3); Sl_rdBTerm : out std_logic; Sl_MIRQ : out std_logic_vector(0 to 1); RX : in std_logic; TX : out std_logic; Interrupt : out std_logic ); end component; component IOBUF is port ( I : in std_logic; IO : inout std_logic; O : out std_logic; T : in std_logic ); end component; -- Internal signals signal Dcm_all_locked : std_logic; signal Debug_SYS_Rst : std_logic; signal Ext_BRK : std_logic; signal Ext_NM_BRK : std_logic; signal MSP430_UART_Interrupt : std_logic; signal MSP430_UART_RX : std_logic; signal MSP430_UART_TX : std_logic; signal TEMP_SENSOR_IIC2INTC_Irpt : std_logic; signal USB_UART_Interrupt : std_logic; signal clk_66_6667MHz : std_logic; signal dcm_clk_s : std_logic; signal dlmb_LMB_ABus : std_logic_vector(0 to 31); signal dlmb_LMB_AddrStrobe : std_logic; signal dlmb_LMB_BE : std_logic_vector(0 to 3); signal dlmb_LMB_ReadDBus : std_logic_vector(0 to 31); signal dlmb_LMB_ReadStrobe : std_logic; signal dlmb_LMB_Ready : std_logic; signal dlmb_LMB_Rst : std_logic; signal dlmb_LMB_WriteDBus : std_logic_vector(0 to 31); signal dlmb_LMB_WriteStrobe : std_logic; signal dlmb_M_ABus : std_logic_vector(0 to 31); signal dlmb_M_AddrStrobe : std_logic; signal dlmb_M_BE : std_logic_vector(0 to 3); signal dlmb_M_DBus : std_logic_vector(0 to 31); signal dlmb_M_ReadStrobe : std_logic; signal dlmb_M_WriteStrobe : std_logic; signal dlmb_Sl_DBus : std_logic_vector(0 to 31); signal dlmb_Sl_Ready : std_logic_vector(0 to 0); signal dlmb_port_BRAM_Addr : std_logic_vector(0 to 31); signal dlmb_port_BRAM_Clk : std_logic; signal dlmb_port_BRAM_Din : std_logic_vector(0 to 31); signal dlmb_port_BRAM_Dout : std_logic_vector(0 to 31); signal dlmb_port_BRAM_EN : std_logic; signal dlmb_port_BRAM_Rst : std_logic; signal dlmb_port_BRAM_WEN : std_logic_vector(0 to 3); signal fpga_0_FLASH_2Mx16_Mem_A_pin_vslice_10_30_concat : std_logic_vector(10 to 30); signal fpga_0_FLASH_2Mx16_Mem_DQ_pin_I : std_logic_vector(0 to 15); signal fpga_0_FLASH_2Mx16_Mem_DQ_pin_O : std_logic_vector(0 to 15); signal fpga_0_FLASH_2Mx16_Mem_DQ_pin_T : std_logic_vector(0 to 15); signal fpga_0_LEDS_4BIT_GPIO_IO_pin_I : std_logic_vector(0 to 3); signal fpga_0_LEDS_4BIT_GPIO_IO_pin_O : std_logic_vector(0 to 3); signal fpga_0_LEDS_4BIT_GPIO_IO_pin_T : std_logic_vector(0 to 3); signal fpga_0_TEMP_SENSOR_Scl_pin_I : std_logic; signal fpga_0_TEMP_SENSOR_Scl_pin_O : std_logic; signal fpga_0_TEMP_SENSOR_Scl_pin_T : std_logic; signal fpga_0_TEMP_SENSOR_Sda_pin_I : std_logic; signal fpga_0_TEMP_SENSOR_Sda_pin_O : std_logic; signal fpga_0_TEMP_SENSOR_Sda_pin_T : std_logic; signal ilmb_LMB_ABus : std_logic_vector(0 to 31); signal ilmb_LMB_AddrStrobe : std_logic; signal ilmb_LMB_BE : std_logic_vector(0 to 3); signal ilmb_LMB_ReadDBus : std_logic_vector(0 to 31); signal ilmb_LMB_ReadStrobe : std_logic; signal ilmb_LMB_Ready : std_logic; signal ilmb_LMB_Rst : std_logic; signal ilmb_LMB_WriteDBus : std_logic_vector(0 to 31); signal ilmb_LMB_WriteStrobe : std_logic; signal ilmb_M_ABus : std_logic_vector(0 to 31); signal ilmb_M_AddrStrobe : std_logic; signal ilmb_M_ReadStrobe : std_logic; signal ilmb_Sl_DBus : std_logic_vector(0 to 31); signal ilmb_Sl_Ready : std_logic_vector(0 to 0); signal ilmb_port_BRAM_Addr : std_logic_vector(0 to 31); signal ilmb_port_BRAM_Clk : std_logic; signal ilmb_port_BRAM_Din : std_logic_vector(0 to 31); signal ilmb_port_BRAM_Dout : std_logic_vector(0 to 31); signal ilmb_port_BRAM_EN : std_logic; signal ilmb_port_BRAM_Rst : std_logic; signal ilmb_port_BRAM_WEN : std_logic_vector(0 to 3); signal mb_plb_M_ABort : std_logic_vector(0 to 1); signal mb_plb_M_ABus : std_logic_vector(0 to 63); signal mb_plb_M_BE : std_logic_vector(0 to 7); signal mb_plb_M_MSize : std_logic_vector(0 to 3); signal mb_plb_M_RNW : std_logic_vector(0 to 1); signal mb_plb_M_TAttribute : std_logic_vector(0 to 31); signal mb_plb_M_UABus : std_logic_vector(0 to 63); signal mb_plb_M_busLock : std_logic_vector(0 to 1); signal mb_plb_M_lockErr : std_logic_vector(0 to 1); signal mb_plb_M_priority : std_logic_vector(0 to 3); signal mb_plb_M_rdBurst : std_logic_vector(0 to 1); signal mb_plb_M_request : std_logic_vector(0 to 1); signal mb_plb_M_size : std_logic_vector(0 to 7); signal mb_plb_M_type : std_logic_vector(0 to 5); signal mb_plb_M_wrBurst : std_logic_vector(0 to 1); signal mb_plb_M_wrDBus : std_logic_vector(0 to 63); signal mb_plb_PLB_ABus : std_logic_vector(0 to 31); signal mb_plb_PLB_BE : std_logic_vector(0 to 3); signal mb_plb_PLB_MAddrAck : std_logic_vector(0 to 1); signal mb_plb_PLB_MBusy : std_logic_vector(0 to 1); signal mb_plb_PLB_MIRQ : std_logic_vector(0 to 1); signal mb_plb_PLB_MRdBTerm : std_logic_vector(0 to 1); signal mb_plb_PLB_MRdDAck : std_logic_vector(0 to 1); signal mb_plb_PLB_MRdDBus : std_logic_vector(0 to 63); signal mb_plb_PLB_MRdErr : std_logic_vector(0 to 1); signal mb_plb_PLB_MRdWdAddr : std_logic_vector(0 to 7); signal mb_plb_PLB_MRearbitrate : std_logic_vector(0 to 1); signal mb_plb_PLB_MSSize : std_logic_vector(0 to 3); signal mb_plb_PLB_MSize : std_logic_vector(0 to 1); signal mb_plb_PLB_MTimeout : std_logic_vector(0 to 1); signal mb_plb_PLB_MWrBTerm : std_logic_vector(0 to 1); signal mb_plb_PLB_MWrDAck : std_logic_vector(0 to 1); signal mb_plb_PLB_MWrErr : std_logic_vector(0 to 1); signal mb_plb_PLB_PAValid : std_logic; signal mb_plb_PLB_RNW : std_logic; signal mb_plb_PLB_SAValid : std_logic; signal mb_plb_PLB_TAttribute : std_logic_vector(0 to 15); signal mb_plb_PLB_UABus : std_logic_vector(0 to 31); signal mb_plb_PLB_abort : std_logic; signal mb_plb_PLB_busLock : std_logic; signal mb_plb_PLB_lockErr : std_logic; signal mb_plb_PLB_masterID : std_logic_vector(0 to 0); signal mb_plb_PLB_rdBurst : std_logic; signal mb_plb_PLB_rdPendPri : std_logic_vector(0 to 1); signal mb_plb_PLB_rdPendReq : std_logic; signal mb_plb_PLB_rdPrim : std_logic_vector(0 to 8); signal mb_plb_PLB_reqPri : std_logic_vector(0 to 1); signal mb_plb_PLB_size : std_logic_vector(0 to 3); signal mb_plb_PLB_type : std_logic_vector(0 to 2); signal mb_plb_PLB_wrBurst : std_logic; signal mb_plb_PLB_wrDBus : std_logic_vector(0 to 31); signal mb_plb_PLB_wrPendPri : std_logic_vector(0 to 1); signal mb_plb_PLB_wrPendReq : std_logic; signal mb_plb_PLB_wrPrim : std_logic_vector(0 to 8); signal mb_plb_SPLB_Rst : std_logic_vector(0 to 8); signal mb_plb_Sl_MBusy : std_logic_vector(0 to 17); signal mb_plb_Sl_MIRQ : std_logic_vector(0 to 17); signal mb_plb_Sl_MRdErr : std_logic_vector(0 to 17); signal mb_plb_Sl_MWrErr : std_logic_vector(0 to 17); signal mb_plb_Sl_SSize : std_logic_vector(0 to 17); signal mb_plb_Sl_addrAck : std_logic_vector(0 to 8); signal mb_plb_Sl_rdBTerm : std_logic_vector(0 to 8); signal mb_plb_Sl_rdComp : std_logic_vector(0 to 8); signal mb_plb_Sl_rdDAck : std_logic_vector(0 to 8); signal mb_plb_Sl_rdDBus : std_logic_vector(0 to 287); signal mb_plb_Sl_rdWdAddr : std_logic_vector(0 to 35); signal mb_plb_Sl_rearbitrate : std_logic_vector(0 to 8); signal mb_plb_Sl_wait : std_logic_vector(0 to 8); signal mb_plb_Sl_wrBTerm : std_logic_vector(0 to 8); signal mb_plb_Sl_wrComp : std_logic_vector(0 to 8); signal mb_plb_Sl_wrDAck : std_logic_vector(0 to 8); signal mb_reset : std_logic; signal microblaze_0_IXCL_FSL_M_Control : std_logic; signal microblaze_0_IXCL_FSL_M_Data : std_logic_vector(0 to 31); signal microblaze_0_IXCL_FSL_M_Full : std_logic; signal microblaze_0_IXCL_FSL_M_Write : std_logic; signal microblaze_0_IXCL_FSL_S_Control : std_logic; signal microblaze_0_IXCL_FSL_S_Data : std_logic_vector(0 to 31); signal microblaze_0_IXCL_FSL_S_Exists : std_logic; signal microblaze_0_IXCL_FSL_S_Read : std_logic; signal microblaze_0_Interrupt : std_logic; signal microblaze_0_mdm_bus_Dbg_Capture : std_logic; signal microblaze_0_mdm_bus_Dbg_Clk : std_logic; signal microblaze_0_mdm_bus_Dbg_Reg_En : std_logic_vector(0 to 7); signal microblaze_0_mdm_bus_Dbg_Shift : std_logic; signal microblaze_0_mdm_bus_Dbg_TDI : std_logic; signal microblaze_0_mdm_bus_Dbg_TDO : std_logic; signal microblaze_0_mdm_bus_Dbg_Update : std_logic; signal microblaze_0_mdm_bus_Debug_Rst : std_logic; signal net_gnd0 : std_logic; signal net_gnd1 : std_logic_vector(0 downto 0); signal net_gnd2 : std_logic_vector(1 downto 0); signal net_gnd4 : std_logic_vector(0 to 3); signal net_gnd10 : std_logic_vector(0 to 9); signal net_gnd32 : std_logic_vector(0 to 31); signal net_vcc0 : std_logic; signal pgassign1 : std_logic_vector(0 to 0); signal pgassign2 : std_logic_vector(0 to 0); signal pgassign3 : std_logic_vector(0 to 9); signal pgassign4 : std_logic_vector(0 to 0); signal pgassign5 : std_logic_vector(0 to 31); signal pgassign6 : std_logic_vector(3 downto 0); signal sys_bus_reset : std_logic_vector(0 to 0); signal sys_rst_s : std_logic; signal xps_timer_0_Interrupt : std_logic; attribute BOX_TYPE : STRING; attribute BOX_TYPE of microblaze_0_wrapper : component is "user_black_box"; attribute BOX_TYPE of mb_plb_wrapper : component is "user_black_box"; attribute BOX_TYPE of ilmb_wrapper : component is "user_black_box"; attribute BOX_TYPE of dlmb_wrapper : component is "user_black_box"; attribute BOX_TYPE of dlmb_cntlr_wrapper : component is "user_black_box"; attribute BOX_TYPE of ilmb_cntlr_wrapper : component is "user_black_box"; attribute BOX_TYPE of lmb_bram_wrapper : component is "user_black_box"; attribute BOX_TYPE of usb_uart_wrapper : component is "user_black_box"; attribute BOX_TYPE of leds_4bit_wrapper : component is "user_black_box"; attribute BOX_TYPE of cs_push_3bit_wrapper : component is "user_black_box"; attribute BOX_TYPE of temp_sensor_wrapper : component is "user_black_box"; attribute BOX_TYPE of flash_2mx16_wrapper : component is "user_black_box"; attribute BOX_TYPE of xps_timer_0_wrapper : component is "user_black_box"; attribute BOX_TYPE of clock_generator_0_wrapper : component is "user_black_box"; attribute BOX_TYPE of mdm_0_wrapper : component is "user_black_box"; attribute BOX_TYPE of proc_sys_reset_0_wrapper : component is "user_black_box"; attribute BOX_TYPE of xps_intc_0_wrapper : component is "user_black_box"; attribute BOX_TYPE of msp430_uart_wrapper : component is "user_black_box"; begin -- Internal assignments fpga_0_FLASH_2Mx16_Mem_A_pin <= fpga_0_FLASH_2Mx16_Mem_A_pin_vslice_10_30_concat; dcm_clk_s <= fpga_0_clk_1_sys_clk_pin; sys_rst_s <= fpga_0_rst_1_sys_rst_pin; fpga_0_MSP430_UART_TX_pin <= MSP430_UART_TX; MSP430_UART_RX <= fpga_0_MSP430_UART_RX_pin; pgassign3(0 to 9) <= B"0000000000"; pgassign4(0 to 0) <= B"0"; fpga_0_FLASH_2Mx16_Mem_CEN_pin <= pgassign1(0); fpga_0_FLASH_2Mx16_Mem_OEN_pin <= pgassign2(0); fpga_0_FLASH_2Mx16_Mem_A_pin_vslice_10_30_concat(10 to 30) <= pgassign5(10 to 30); pgassign6(3) <= USB_UART_Interrupt; pgassign6(2) <= MSP430_UART_Interrupt; pgassign6(1) <= TEMP_SENSOR_IIC2INTC_Irpt; pgassign6(0) <= xps_timer_0_Interrupt; net_gnd0 <= '0'; net_gnd1(0 downto 0) <= B"0"; net_gnd10(0 to 9) <= B"0000000000"; net_gnd2(1 downto 0) <= B"00"; net_gnd32(0 to 31) <= B"00000000000000000000000000000000"; net_gnd4(0 to 3) <= B"0000"; net_vcc0 <= '1'; fpga_0_FLASH_2Mx16_MEM_BYTEn_pin <= net_vcc0; microblaze_0 : microblaze_0_wrapper port map ( CLK => clk_66_6667MHz, RESET => dlmb_LMB_Rst, MB_RESET => mb_reset, INTERRUPT => microblaze_0_Interrupt, EXT_BRK => Ext_BRK, EXT_NM_BRK => Ext_NM_BRK, DBG_STOP => net_gnd0, MB_Halted => open, MB_Error => open, INSTR => ilmb_LMB_ReadDBus, IREADY => ilmb_LMB_Ready, IWAIT => net_gnd0, ICE => net_gnd0, IUE => net_gnd0, INSTR_ADDR => ilmb_M_ABus, IFETCH => ilmb_M_ReadStrobe, I_AS => ilmb_M_AddrStrobe, IPLB_M_ABort => mb_plb_M_ABort(1), IPLB_M_ABus => mb_plb_M_ABus(32 to 63), IPLB_M_UABus => mb_plb_M_UABus(32 to 63), IPLB_M_BE => mb_plb_M_BE(4 to 7), IPLB_M_busLock => mb_plb_M_busLock(1), IPLB_M_lockErr => mb_plb_M_lockErr(1), IPLB_M_MSize => mb_plb_M_MSize(2 to 3), IPLB_M_priority => mb_plb_M_priority(2 to 3), IPLB_M_rdBurst => mb_plb_M_rdBurst(1), IPLB_M_request => mb_plb_M_request(1), IPLB_M_RNW => mb_plb_M_RNW(1), IPLB_M_size => mb_plb_M_size(4 to 7), IPLB_M_TAttribute => mb_plb_M_TAttribute(16 to 31), IPLB_M_type => mb_plb_M_type(3 to 5), IPLB_M_wrBurst => mb_plb_M_wrBurst(1), IPLB_M_wrDBus => mb_plb_M_wrDBus(32 to 63), IPLB_MBusy => mb_plb_PLB_MBusy(1), IPLB_MRdErr => mb_plb_PLB_MRdErr(1), IPLB_MWrErr => mb_plb_PLB_MWrErr(1), IPLB_MIRQ => mb_plb_PLB_MIRQ(1), IPLB_MWrBTerm => mb_plb_PLB_MWrBTerm(1), IPLB_MWrDAck => mb_plb_PLB_MWrDAck(1), IPLB_MAddrAck => mb_plb_PLB_MAddrAck(1), IPLB_MRdBTerm => mb_plb_PLB_MRdBTerm(1), IPLB_MRdDAck => mb_plb_PLB_MRdDAck(1), IPLB_MRdDBus => mb_plb_PLB_MRdDBus(32 to 63), IPLB_MRdWdAddr => mb_plb_PLB_MRdWdAddr(4 to 7), IPLB_MRearbitrate => mb_plb_PLB_MRearbitrate(1), IPLB_MSSize => mb_plb_PLB_MSSize(2 to 3), IPLB_MTimeout => mb_plb_PLB_MTimeout(1), DATA_READ => dlmb_LMB_ReadDBus, DREADY => dlmb_LMB_Ready, DWAIT => net_gnd0, DCE => net_gnd0, DUE => net_gnd0, DATA_WRITE => dlmb_M_DBus, DATA_ADDR => dlmb_M_ABus, D_AS => dlmb_M_AddrStrobe, READ_STROBE => dlmb_M_ReadStrobe, WRITE_STROBE => dlmb_M_WriteStrobe, BYTE_ENABLE => dlmb_M_BE, DPLB_M_ABort => mb_plb_M_ABort(0), DPLB_M_ABus => mb_plb_M_ABus(0 to 31), DPLB_M_UABus => mb_plb_M_UABus(0 to 31), DPLB_M_BE => mb_plb_M_BE(0 to 3), DPLB_M_busLock => mb_plb_M_busLock(0), DPLB_M_lockErr => mb_plb_M_lockErr(0), DPLB_M_MSize => mb_plb_M_MSize(0 to 1), DPLB_M_priority => mb_plb_M_priority(0 to 1), DPLB_M_rdBurst => mb_plb_M_rdBurst(0), DPLB_M_request => mb_plb_M_request(0), DPLB_M_RNW => mb_plb_M_RNW(0), DPLB_M_size => mb_plb_M_size(0 to 3), DPLB_M_TAttribute => mb_plb_M_TAttribute(0 to 15), DPLB_M_type => mb_plb_M_type(0 to 2), DPLB_M_wrBurst => mb_plb_M_wrBurst(0), DPLB_M_wrDBus => mb_plb_M_wrDBus(0 to 31), DPLB_MBusy => mb_plb_PLB_MBusy(0), DPLB_MRdErr => mb_plb_PLB_MRdErr(0), DPLB_MWrErr => mb_plb_PLB_MWrErr(0), DPLB_MIRQ => mb_plb_PLB_MIRQ(0), DPLB_MWrBTerm => mb_plb_PLB_MWrBTerm(0), DPLB_MWrDAck => mb_plb_PLB_MWrDAck(0), DPLB_MAddrAck => mb_plb_PLB_MAddrAck(0), DPLB_MRdBTerm => mb_plb_PLB_MRdBTerm(0), DPLB_MRdDAck => mb_plb_PLB_MRdDAck(0), DPLB_MRdDBus => mb_plb_PLB_MRdDBus(0 to 31), DPLB_MRdWdAddr => mb_plb_PLB_MRdWdAddr(0 to 3), DPLB_MRearbitrate => mb_plb_PLB_MRearbitrate(0), DPLB_MSSize => mb_plb_PLB_MSSize(0 to 1), DPLB_MTimeout => mb_plb_PLB_MTimeout(0), M_AXI_IP_AWID => open, M_AXI_IP_AWADDR => open, M_AXI_IP_AWLEN => open, M_AXI_IP_AWSIZE => open, M_AXI_IP_AWBURST => open, M_AXI_IP_AWLOCK => open, M_AXI_IP_AWCACHE => open, M_AXI_IP_AWPROT => open, M_AXI_IP_AWQOS => open, M_AXI_IP_AWVALID => open, M_AXI_IP_AWREADY => net_gnd0, M_AXI_IP_WDATA => open, M_AXI_IP_WSTRB => open, M_AXI_IP_WLAST => open, M_AXI_IP_WVALID => open, M_AXI_IP_WREADY => net_gnd0, M_AXI_IP_BID => net_gnd1(0 downto 0), M_AXI_IP_BRESP => net_gnd2, M_AXI_IP_BVALID => net_gnd0, M_AXI_IP_BREADY => open, M_AXI_IP_ARID => open, M_AXI_IP_ARADDR => open, M_AXI_IP_ARLEN => open, M_AXI_IP_ARSIZE => open, M_AXI_IP_ARBURST => open, M_AXI_IP_ARLOCK => open, M_AXI_IP_ARCACHE => open, M_AXI_IP_ARPROT => open, M_AXI_IP_ARQOS => open, M_AXI_IP_ARVALID => open, M_AXI_IP_ARREADY => net_gnd0, M_AXI_IP_RID => net_gnd1(0 downto 0), M_AXI_IP_RDATA => net_gnd32(0 to 31), M_AXI_IP_RRESP => net_gnd2, M_AXI_IP_RLAST => net_gnd0, M_AXI_IP_RVALID => net_gnd0, M_AXI_IP_RREADY => open, M_AXI_DP_AWID => open, M_AXI_DP_AWADDR => open, M_AXI_DP_AWLEN => open, M_AXI_DP_AWSIZE => open, M_AXI_DP_AWBURST => open, M_AXI_DP_AWLOCK => open, M_AXI_DP_AWCACHE => open, M_AXI_DP_AWPROT => open, M_AXI_DP_AWQOS => open, M_AXI_DP_AWVALID => open, M_AXI_DP_AWREADY => net_gnd0, M_AXI_DP_WDATA => open, M_AXI_DP_WSTRB => open, M_AXI_DP_WLAST => open, M_AXI_DP_WVALID => open, M_AXI_DP_WREADY => net_gnd0, M_AXI_DP_BID => net_gnd1(0 downto 0), M_AXI_DP_BRESP => net_gnd2, M_AXI_DP_BVALID => net_gnd0, M_AXI_DP_BREADY => open, M_AXI_DP_ARID => open, M_AXI_DP_ARADDR => open, M_AXI_DP_ARLEN => open, M_AXI_DP_ARSIZE => open, M_AXI_DP_ARBURST => open, M_AXI_DP_ARLOCK => open, M_AXI_DP_ARCACHE => open, M_AXI_DP_ARPROT => open, M_AXI_DP_ARQOS => open, M_AXI_DP_ARVALID => open, M_AXI_DP_ARREADY => net_gnd0, M_AXI_DP_RID => net_gnd1(0 downto 0), M_AXI_DP_RDATA => net_gnd32(0 to 31), M_AXI_DP_RRESP => net_gnd2, M_AXI_DP_RLAST => net_gnd0, M_AXI_DP_RVALID => net_gnd0, M_AXI_DP_RREADY => open, M_AXI_IC_AWID => open, M_AXI_IC_AWADDR => open, M_AXI_IC_AWLEN => open, M_AXI_IC_AWSIZE => open, M_AXI_IC_AWBURST => open, M_AXI_IC_AWLOCK => open, M_AXI_IC_AWCACHE => open, M_AXI_IC_AWPROT => open, M_AXI_IC_AWQOS => open, M_AXI_IC_AWVALID => open, M_AXI_IC_AWREADY => net_gnd0, M_AXI_IC_WDATA => open, M_AXI_IC_WSTRB => open, M_AXI_IC_WLAST => open, M_AXI_IC_WVALID => open, M_AXI_IC_WREADY => net_gnd0, M_AXI_IC_BID => net_gnd1(0 downto 0), M_AXI_IC_BRESP => net_gnd2, M_AXI_IC_BVALID => net_gnd0, M_AXI_IC_BREADY => open, M_AXI_IC_ARID => open, M_AXI_IC_ARADDR => open, M_AXI_IC_ARLEN => open, M_AXI_IC_ARSIZE => open, M_AXI_IC_ARBURST => open, M_AXI_IC_ARLOCK => open, M_AXI_IC_ARCACHE => open, M_AXI_IC_ARPROT => open, M_AXI_IC_ARQOS => open, M_AXI_IC_ARVALID => open, M_AXI_IC_ARREADY => net_gnd0, M_AXI_IC_RID => net_gnd1(0 downto 0), M_AXI_IC_RDATA => net_gnd32(0 to 31), M_AXI_IC_RRESP => net_gnd2, M_AXI_IC_RLAST => net_gnd0, M_AXI_IC_RVALID => net_gnd0, M_AXI_IC_RREADY => open, M_AXI_DC_AWID => open, M_AXI_DC_AWADDR => open, M_AXI_DC_AWLEN => open, M_AXI_DC_AWSIZE => open, M_AXI_DC_AWBURST => open, M_AXI_DC_AWLOCK => open, M_AXI_DC_AWCACHE => open, M_AXI_DC_AWPROT => open, M_AXI_DC_AWQOS => open, M_AXI_DC_AWVALID => open, M_AXI_DC_AWREADY => net_gnd0, M_AXI_DC_WDATA => open, M_AXI_DC_WSTRB => open, M_AXI_DC_WLAST => open, M_AXI_DC_WVALID => open, M_AXI_DC_WREADY => net_gnd0, M_AXI_DC_BID => net_gnd1(0 downto 0), M_AXI_DC_BRESP => net_gnd2, M_AXI_DC_BVALID => net_gnd0, M_AXI_DC_BREADY => open, M_AXI_DC_ARID => open, M_AXI_DC_ARADDR => open, M_AXI_DC_ARLEN => open, M_AXI_DC_ARSIZE => open, M_AXI_DC_ARBURST => open, M_AXI_DC_ARLOCK => open, M_AXI_DC_ARCACHE => open, M_AXI_DC_ARPROT => open, M_AXI_DC_ARQOS => open, M_AXI_DC_ARVALID => open, M_AXI_DC_ARREADY => net_gnd0, M_AXI_DC_RID => net_gnd1(0 downto 0), M_AXI_DC_RDATA => net_gnd32(0 to 31), M_AXI_DC_RRESP => net_gnd2, M_AXI_DC_RLAST => net_gnd0, M_AXI_DC_RVALID => net_gnd0, M_AXI_DC_RREADY => open, DBG_CLK => microblaze_0_mdm_bus_Dbg_Clk, DBG_TDI => microblaze_0_mdm_bus_Dbg_TDI, DBG_TDO => microblaze_0_mdm_bus_Dbg_TDO, DBG_REG_EN => microblaze_0_mdm_bus_Dbg_Reg_En, DBG_SHIFT => microblaze_0_mdm_bus_Dbg_Shift, DBG_CAPTURE => microblaze_0_mdm_bus_Dbg_Capture, DBG_UPDATE => microblaze_0_mdm_bus_Dbg_Update, DEBUG_RST => microblaze_0_mdm_bus_Debug_Rst, Trace_Instruction => open, Trace_Valid_Instr => open, Trace_PC => open, Trace_Reg_Write => open, Trace_Reg_Addr => open, Trace_MSR_Reg => open, Trace_PID_Reg => open, Trace_New_Reg_Value => open, Trace_Exception_Taken => open, Trace_Exception_Kind => open, Trace_Jump_Taken => open, Trace_Delay_Slot => open, Trace_Data_Address => open, Trace_Data_Access => open, Trace_Data_Read => open, Trace_Data_Write => open, Trace_Data_Write_Value => open, Trace_Data_Byte_Enable => open, Trace_DCache_Req => open, Trace_DCache_Hit => open, Trace_DCache_Rdy => open, Trace_DCache_Read => open, Trace_ICache_Req => open, Trace_ICache_Hit => open, Trace_ICache_Rdy => open, Trace_OF_PipeRun => open, Trace_EX_PipeRun => open, Trace_MEM_PipeRun => open, Trace_MB_Halted => open, Trace_Jump_Hit => open, FSL0_S_CLK => open, FSL0_S_READ => open, FSL0_S_DATA => net_gnd32, FSL0_S_CONTROL => net_gnd0, FSL0_S_EXISTS => net_gnd0, FSL0_M_CLK => open, FSL0_M_WRITE => open, FSL0_M_DATA => open, FSL0_M_CONTROL => open, FSL0_M_FULL => net_gnd0, FSL1_S_CLK => open, FSL1_S_READ => open, FSL1_S_DATA => net_gnd32, FSL1_S_CONTROL => net_gnd0, FSL1_S_EXISTS => net_gnd0, FSL1_M_CLK => open, FSL1_M_WRITE => open, FSL1_M_DATA => open, FSL1_M_CONTROL => open, FSL1_M_FULL => net_gnd0, FSL2_S_CLK => open, FSL2_S_READ => open, FSL2_S_DATA => net_gnd32, FSL2_S_CONTROL => net_gnd0, FSL2_S_EXISTS => net_gnd0, FSL2_M_CLK => open, FSL2_M_WRITE => open, FSL2_M_DATA => open, FSL2_M_CONTROL => open, FSL2_M_FULL => net_gnd0, FSL3_S_CLK => open, FSL3_S_READ => open, FSL3_S_DATA => net_gnd32, FSL3_S_CONTROL => net_gnd0, FSL3_S_EXISTS => net_gnd0, FSL3_M_CLK => open, FSL3_M_WRITE => open, FSL3_M_DATA => open, FSL3_M_CONTROL => open, FSL3_M_FULL => net_gnd0, FSL4_S_CLK => open, FSL4_S_READ => open, FSL4_S_DATA => net_gnd32, FSL4_S_CONTROL => net_gnd0, FSL4_S_EXISTS => net_gnd0, FSL4_M_CLK => open, FSL4_M_WRITE => open, FSL4_M_DATA => open, FSL4_M_CONTROL => open, FSL4_M_FULL => net_gnd0, FSL5_S_CLK => open, FSL5_S_READ => open, FSL5_S_DATA => net_gnd32, FSL5_S_CONTROL => net_gnd0, FSL5_S_EXISTS => net_gnd0, FSL5_M_CLK => open, FSL5_M_WRITE => open, FSL5_M_DATA => open, FSL5_M_CONTROL => open, FSL5_M_FULL => net_gnd0, FSL6_S_CLK => open, FSL6_S_READ => open, FSL6_S_DATA => net_gnd32, FSL6_S_CONTROL => net_gnd0, FSL6_S_EXISTS => net_gnd0, FSL6_M_CLK => open, FSL6_M_WRITE => open, FSL6_M_DATA => open, FSL6_M_CONTROL => open, FSL6_M_FULL => net_gnd0, FSL7_S_CLK => open, FSL7_S_READ => open, FSL7_S_DATA => net_gnd32, FSL7_S_CONTROL => net_gnd0, FSL7_S_EXISTS => net_gnd0, FSL7_M_CLK => open, FSL7_M_WRITE => open, FSL7_M_DATA => open, FSL7_M_CONTROL => open, FSL7_M_FULL => net_gnd0, FSL8_S_CLK => open, FSL8_S_READ => open, FSL8_S_DATA => net_gnd32, FSL8_S_CONTROL => net_gnd0, FSL8_S_EXISTS => net_gnd0, FSL8_M_CLK => open, FSL8_M_WRITE => open, FSL8_M_DATA => open, FSL8_M_CONTROL => open, FSL8_M_FULL => net_gnd0, FSL9_S_CLK => open, FSL9_S_READ => open, FSL9_S_DATA => net_gnd32, FSL9_S_CONTROL => net_gnd0, FSL9_S_EXISTS => net_gnd0, FSL9_M_CLK => open, FSL9_M_WRITE => open, FSL9_M_DATA => open, FSL9_M_CONTROL => open, FSL9_M_FULL => net_gnd0, FSL10_S_CLK => open, FSL10_S_READ => open, FSL10_S_DATA => net_gnd32, FSL10_S_CONTROL => net_gnd0, FSL10_S_EXISTS => net_gnd0, FSL10_M_CLK => open, FSL10_M_WRITE => open, FSL10_M_DATA => open, FSL10_M_CONTROL => open, FSL10_M_FULL => net_gnd0, FSL11_S_CLK => open, FSL11_S_READ => open, FSL11_S_DATA => net_gnd32, FSL11_S_CONTROL => net_gnd0, FSL11_S_EXISTS => net_gnd0, FSL11_M_CLK => open, FSL11_M_WRITE => open, FSL11_M_DATA => open, FSL11_M_CONTROL => open, FSL11_M_FULL => net_gnd0, FSL12_S_CLK => open, FSL12_S_READ => open, FSL12_S_DATA => net_gnd32, FSL12_S_CONTROL => net_gnd0, FSL12_S_EXISTS => net_gnd0, FSL12_M_CLK => open, FSL12_M_WRITE => open, FSL12_M_DATA => open, FSL12_M_CONTROL => open, FSL12_M_FULL => net_gnd0, FSL13_S_CLK => open, FSL13_S_READ => open, FSL13_S_DATA => net_gnd32, FSL13_S_CONTROL => net_gnd0, FSL13_S_EXISTS => net_gnd0, FSL13_M_CLK => open, FSL13_M_WRITE => open, FSL13_M_DATA => open, FSL13_M_CONTROL => open, FSL13_M_FULL => net_gnd0, FSL14_S_CLK => open, FSL14_S_READ => open, FSL14_S_DATA => net_gnd32, FSL14_S_CONTROL => net_gnd0, FSL14_S_EXISTS => net_gnd0, FSL14_M_CLK => open, FSL14_M_WRITE => open, FSL14_M_DATA => open, FSL14_M_CONTROL => open, FSL14_M_FULL => net_gnd0, FSL15_S_CLK => open, FSL15_S_READ => open, FSL15_S_DATA => net_gnd32, FSL15_S_CONTROL => net_gnd0, FSL15_S_EXISTS => net_gnd0, FSL15_M_CLK => open, FSL15_M_WRITE => open, FSL15_M_DATA => open, FSL15_M_CONTROL => open, FSL15_M_FULL => net_gnd0, M0_AXIS_TLAST => open, M0_AXIS_TDATA => open, M0_AXIS_TVALID => open, M0_AXIS_TREADY => net_gnd0, S0_AXIS_TLAST => net_gnd0, S0_AXIS_TDATA => net_gnd32(0 to 31), S0_AXIS_TVALID => net_gnd0, S0_AXIS_TREADY => open, M1_AXIS_TLAST => open, M1_AXIS_TDATA => open, M1_AXIS_TVALID => open, M1_AXIS_TREADY => net_gnd0, S1_AXIS_TLAST => net_gnd0, S1_AXIS_TDATA => net_gnd32(0 to 31), S1_AXIS_TVALID => net_gnd0, S1_AXIS_TREADY => open, M2_AXIS_TLAST => open, M2_AXIS_TDATA => open, M2_AXIS_TVALID => open, M2_AXIS_TREADY => net_gnd0, S2_AXIS_TLAST => net_gnd0, S2_AXIS_TDATA => net_gnd32(0 to 31), S2_AXIS_TVALID => net_gnd0, S2_AXIS_TREADY => open, M3_AXIS_TLAST => open, M3_AXIS_TDATA => open, M3_AXIS_TVALID => open, M3_AXIS_TREADY => net_gnd0, S3_AXIS_TLAST => net_gnd0, S3_AXIS_TDATA => net_gnd32(0 to 31), S3_AXIS_TVALID => net_gnd0, S3_AXIS_TREADY => open, M4_AXIS_TLAST => open, M4_AXIS_TDATA => open, M4_AXIS_TVALID => open, M4_AXIS_TREADY => net_gnd0, S4_AXIS_TLAST => net_gnd0, S4_AXIS_TDATA => net_gnd32(0 to 31), S4_AXIS_TVALID => net_gnd0, S4_AXIS_TREADY => open, M5_AXIS_TLAST => open, M5_AXIS_TDATA => open, M5_AXIS_TVALID => open, M5_AXIS_TREADY => net_gnd0, S5_AXIS_TLAST => net_gnd0, S5_AXIS_TDATA => net_gnd32(0 to 31), S5_AXIS_TVALID => net_gnd0, S5_AXIS_TREADY => open, M6_AXIS_TLAST => open, M6_AXIS_TDATA => open, M6_AXIS_TVALID => open, M6_AXIS_TREADY => net_gnd0, S6_AXIS_TLAST => net_gnd0, S6_AXIS_TDATA => net_gnd32(0 to 31), S6_AXIS_TVALID => net_gnd0, S6_AXIS_TREADY => open, M7_AXIS_TLAST => open, M7_AXIS_TDATA => open, M7_AXIS_TVALID => open, M7_AXIS_TREADY => net_gnd0, S7_AXIS_TLAST => net_gnd0, S7_AXIS_TDATA => net_gnd32(0 to 31), S7_AXIS_TVALID => net_gnd0, S7_AXIS_TREADY => open, M8_AXIS_TLAST => open, M8_AXIS_TDATA => open, M8_AXIS_TVALID => open, M8_AXIS_TREADY => net_gnd0, S8_AXIS_TLAST => net_gnd0, S8_AXIS_TDATA => net_gnd32(0 to 31), S8_AXIS_TVALID => net_gnd0, S8_AXIS_TREADY => open, M9_AXIS_TLAST => open, M9_AXIS_TDATA => open, M9_AXIS_TVALID => open, M9_AXIS_TREADY => net_gnd0, S9_AXIS_TLAST => net_gnd0, S9_AXIS_TDATA => net_gnd32(0 to 31), S9_AXIS_TVALID => net_gnd0, S9_AXIS_TREADY => open, M10_AXIS_TLAST => open, M10_AXIS_TDATA => open, M10_AXIS_TVALID => open, M10_AXIS_TREADY => net_gnd0, S10_AXIS_TLAST => net_gnd0, S10_AXIS_TDATA => net_gnd32(0 to 31), S10_AXIS_TVALID => net_gnd0, S10_AXIS_TREADY => open, M11_AXIS_TLAST => open, M11_AXIS_TDATA => open, M11_AXIS_TVALID => open, M11_AXIS_TREADY => net_gnd0, S11_AXIS_TLAST => net_gnd0, S11_AXIS_TDATA => net_gnd32(0 to 31), S11_AXIS_TVALID => net_gnd0, S11_AXIS_TREADY => open, M12_AXIS_TLAST => open, M12_AXIS_TDATA => open, M12_AXIS_TVALID => open, M12_AXIS_TREADY => net_gnd0, S12_AXIS_TLAST => net_gnd0, S12_AXIS_TDATA => net_gnd32(0 to 31), S12_AXIS_TVALID => net_gnd0, S12_AXIS_TREADY => open, M13_AXIS_TLAST => open, M13_AXIS_TDATA => open, M13_AXIS_TVALID => open, M13_AXIS_TREADY => net_gnd0, S13_AXIS_TLAST => net_gnd0, S13_AXIS_TDATA => net_gnd32(0 to 31), S13_AXIS_TVALID => net_gnd0, S13_AXIS_TREADY => open, M14_AXIS_TLAST => open, M14_AXIS_TDATA => open, M14_AXIS_TVALID => open, M14_AXIS_TREADY => net_gnd0, S14_AXIS_TLAST => net_gnd0, S14_AXIS_TDATA => net_gnd32(0 to 31), S14_AXIS_TVALID => net_gnd0, S14_AXIS_TREADY => open, M15_AXIS_TLAST => open, M15_AXIS_TDATA => open, M15_AXIS_TVALID => open, M15_AXIS_TREADY => net_gnd0, S15_AXIS_TLAST => net_gnd0, S15_AXIS_TDATA => net_gnd32(0 to 31), S15_AXIS_TVALID => net_gnd0, S15_AXIS_TREADY => open, ICACHE_FSL_IN_CLK => open, ICACHE_FSL_IN_READ => microblaze_0_IXCL_FSL_S_Read, ICACHE_FSL_IN_DATA => microblaze_0_IXCL_FSL_S_Data, ICACHE_FSL_IN_CONTROL => microblaze_0_IXCL_FSL_S_Control, ICACHE_FSL_IN_EXISTS => microblaze_0_IXCL_FSL_S_Exists, ICACHE_FSL_OUT_CLK => open, ICACHE_FSL_OUT_WRITE => microblaze_0_IXCL_FSL_M_Write, ICACHE_FSL_OUT_DATA => microblaze_0_IXCL_FSL_M_Data, ICACHE_FSL_OUT_CONTROL => microblaze_0_IXCL_FSL_M_Control, ICACHE_FSL_OUT_FULL => microblaze_0_IXCL_FSL_M_Full, DCACHE_FSL_IN_CLK => open, DCACHE_FSL_IN_READ => open, DCACHE_FSL_IN_DATA => net_gnd32, DCACHE_FSL_IN_CONTROL => net_gnd0, DCACHE_FSL_IN_EXISTS => net_gnd0, DCACHE_FSL_OUT_CLK => open, DCACHE_FSL_OUT_WRITE => open, DCACHE_FSL_OUT_DATA => open, DCACHE_FSL_OUT_CONTROL => open, DCACHE_FSL_OUT_FULL => net_gnd0 ); mb_plb : mb_plb_wrapper port map ( PLB_Clk => clk_66_6667MHz, SYS_Rst => sys_bus_reset(0), PLB_Rst => open, SPLB_Rst => mb_plb_SPLB_Rst, MPLB_Rst => open, PLB_dcrAck => open, PLB_dcrDBus => open, DCR_ABus => net_gnd10, DCR_DBus => net_gnd32, DCR_Read => net_gnd0, DCR_Write => net_gnd0, M_ABus => mb_plb_M_ABus, M_UABus => mb_plb_M_UABus, M_BE => mb_plb_M_BE, M_RNW => mb_plb_M_RNW, M_abort => mb_plb_M_ABort, M_busLock => mb_plb_M_busLock, M_TAttribute => mb_plb_M_TAttribute, M_lockErr => mb_plb_M_lockErr, M_MSize => mb_plb_M_MSize, M_priority => mb_plb_M_priority, M_rdBurst => mb_plb_M_rdBurst, M_request => mb_plb_M_request, M_size => mb_plb_M_size, M_type => mb_plb_M_type, M_wrBurst => mb_plb_M_wrBurst, M_wrDBus => mb_plb_M_wrDBus, Sl_addrAck => mb_plb_Sl_addrAck, Sl_MRdErr => mb_plb_Sl_MRdErr, Sl_MWrErr => mb_plb_Sl_MWrErr, Sl_MBusy => mb_plb_Sl_MBusy, Sl_rdBTerm => mb_plb_Sl_rdBTerm, Sl_rdComp => mb_plb_Sl_rdComp, Sl_rdDAck => mb_plb_Sl_rdDAck, Sl_rdDBus => mb_plb_Sl_rdDBus, Sl_rdWdAddr => mb_plb_Sl_rdWdAddr, Sl_rearbitrate => mb_plb_Sl_rearbitrate, Sl_SSize => mb_plb_Sl_SSize, Sl_wait => mb_plb_Sl_wait, Sl_wrBTerm => mb_plb_Sl_wrBTerm, Sl_wrComp => mb_plb_Sl_wrComp, Sl_wrDAck => mb_plb_Sl_wrDAck, Sl_MIRQ => mb_plb_Sl_MIRQ, PLB_MIRQ => mb_plb_PLB_MIRQ, PLB_ABus => mb_plb_PLB_ABus, PLB_UABus => mb_plb_PLB_UABus, PLB_BE => mb_plb_PLB_BE, PLB_MAddrAck => mb_plb_PLB_MAddrAck, PLB_MTimeout => mb_plb_PLB_MTimeout, PLB_MBusy => mb_plb_PLB_MBusy, PLB_MRdErr => mb_plb_PLB_MRdErr, PLB_MWrErr => mb_plb_PLB_MWrErr, PLB_MRdBTerm => mb_plb_PLB_MRdBTerm, PLB_MRdDAck => mb_plb_PLB_MRdDAck, PLB_MRdDBus => mb_plb_PLB_MRdDBus, PLB_MRdWdAddr => mb_plb_PLB_MRdWdAddr, PLB_MRearbitrate => mb_plb_PLB_MRearbitrate, PLB_MWrBTerm => mb_plb_PLB_MWrBTerm, PLB_MWrDAck => mb_plb_PLB_MWrDAck, PLB_MSSize => mb_plb_PLB_MSSize, PLB_PAValid => mb_plb_PLB_PAValid, PLB_RNW => mb_plb_PLB_RNW, PLB_SAValid => mb_plb_PLB_SAValid, PLB_abort => mb_plb_PLB_abort, PLB_busLock => mb_plb_PLB_busLock, PLB_TAttribute => mb_plb_PLB_TAttribute, PLB_lockErr => mb_plb_PLB_lockErr, PLB_masterID => mb_plb_PLB_masterID(0 to 0), PLB_MSize => mb_plb_PLB_MSize, PLB_rdPendPri => mb_plb_PLB_rdPendPri, PLB_wrPendPri => mb_plb_PLB_wrPendPri, PLB_rdPendReq => mb_plb_PLB_rdPendReq, PLB_wrPendReq => mb_plb_PLB_wrPendReq, PLB_rdBurst => mb_plb_PLB_rdBurst, PLB_rdPrim => mb_plb_PLB_rdPrim, PLB_reqPri => mb_plb_PLB_reqPri, PLB_size => mb_plb_PLB_size, PLB_type => mb_plb_PLB_type, PLB_wrBurst => mb_plb_PLB_wrBurst, PLB_wrDBus => mb_plb_PLB_wrDBus, PLB_wrPrim => mb_plb_PLB_wrPrim, PLB_SaddrAck => open, PLB_SMRdErr => open, PLB_SMWrErr => open, PLB_SMBusy => open, PLB_SrdBTerm => open, PLB_SrdComp => open, PLB_SrdDAck => open, PLB_SrdDBus => open, PLB_SrdWdAddr => open, PLB_Srearbitrate => open, PLB_Sssize => open, PLB_Swait => open, PLB_SwrBTerm => open, PLB_SwrComp => open, PLB_SwrDAck => open, Bus_Error_Det => open ); ilmb : ilmb_wrapper port map ( LMB_Clk => clk_66_6667MHz, SYS_Rst => sys_bus_reset(0), LMB_Rst => ilmb_LMB_Rst, M_ABus => ilmb_M_ABus, M_ReadStrobe => ilmb_M_ReadStrobe, M_WriteStrobe => net_gnd0, M_AddrStrobe => ilmb_M_AddrStrobe, M_DBus => net_gnd32, M_BE => net_gnd4, Sl_DBus => ilmb_Sl_DBus, Sl_Ready => ilmb_Sl_Ready(0 to 0), LMB_ABus => ilmb_LMB_ABus, LMB_ReadStrobe => ilmb_LMB_ReadStrobe, LMB_WriteStrobe => ilmb_LMB_WriteStrobe, LMB_AddrStrobe => ilmb_LMB_AddrStrobe, LMB_ReadDBus => ilmb_LMB_ReadDBus, LMB_WriteDBus => ilmb_LMB_WriteDBus, LMB_Ready => ilmb_LMB_Ready, LMB_BE => ilmb_LMB_BE ); dlmb : dlmb_wrapper port map ( LMB_Clk => clk_66_6667MHz, SYS_Rst => sys_bus_reset(0), LMB_Rst => dlmb_LMB_Rst, M_ABus => dlmb_M_ABus, M_ReadStrobe => dlmb_M_ReadStrobe, M_WriteStrobe => dlmb_M_WriteStrobe, M_AddrStrobe => dlmb_M_AddrStrobe, M_DBus => dlmb_M_DBus, M_BE => dlmb_M_BE, Sl_DBus => dlmb_Sl_DBus, Sl_Ready => dlmb_Sl_Ready(0 to 0), LMB_ABus => dlmb_LMB_ABus, LMB_ReadStrobe => dlmb_LMB_ReadStrobe, LMB_WriteStrobe => dlmb_LMB_WriteStrobe, LMB_AddrStrobe => dlmb_LMB_AddrStrobe, LMB_ReadDBus => dlmb_LMB_ReadDBus, LMB_WriteDBus => dlmb_LMB_WriteDBus, LMB_Ready => dlmb_LMB_Ready, LMB_BE => dlmb_LMB_BE ); dlmb_cntlr : dlmb_cntlr_wrapper port map ( LMB_Clk => clk_66_6667MHz, LMB_Rst => dlmb_LMB_Rst, LMB_ABus => dlmb_LMB_ABus, LMB_WriteDBus => dlmb_LMB_WriteDBus, LMB_AddrStrobe => dlmb_LMB_AddrStrobe, LMB_ReadStrobe => dlmb_LMB_ReadStrobe, LMB_WriteStrobe => dlmb_LMB_WriteStrobe, LMB_BE => dlmb_LMB_BE, Sl_DBus => dlmb_Sl_DBus, Sl_Ready => dlmb_Sl_Ready(0), BRAM_Rst_A => dlmb_port_BRAM_Rst, BRAM_Clk_A => dlmb_port_BRAM_Clk, BRAM_EN_A => dlmb_port_BRAM_EN, BRAM_WEN_A => dlmb_port_BRAM_WEN, BRAM_Addr_A => dlmb_port_BRAM_Addr, BRAM_Din_A => dlmb_port_BRAM_Din, BRAM_Dout_A => dlmb_port_BRAM_Dout ); ilmb_cntlr : ilmb_cntlr_wrapper port map ( LMB_Clk => clk_66_6667MHz, LMB_Rst => ilmb_LMB_Rst, LMB_ABus => ilmb_LMB_ABus, LMB_WriteDBus => ilmb_LMB_WriteDBus, LMB_AddrStrobe => ilmb_LMB_AddrStrobe, LMB_ReadStrobe => ilmb_LMB_ReadStrobe, LMB_WriteStrobe => ilmb_LMB_WriteStrobe, LMB_BE => ilmb_LMB_BE, Sl_DBus => ilmb_Sl_DBus, Sl_Ready => ilmb_Sl_Ready(0), BRAM_Rst_A => ilmb_port_BRAM_Rst, BRAM_Clk_A => ilmb_port_BRAM_Clk, BRAM_EN_A => ilmb_port_BRAM_EN, BRAM_WEN_A => ilmb_port_BRAM_WEN, BRAM_Addr_A => ilmb_port_BRAM_Addr, BRAM_Din_A => ilmb_port_BRAM_Din, BRAM_Dout_A => ilmb_port_BRAM_Dout ); lmb_bram : lmb_bram_wrapper port map ( BRAM_Rst_A => ilmb_port_BRAM_Rst, BRAM_Clk_A => ilmb_port_BRAM_Clk, BRAM_EN_A => ilmb_port_BRAM_EN, BRAM_WEN_A => ilmb_port_BRAM_WEN, BRAM_Addr_A => ilmb_port_BRAM_Addr, BRAM_Din_A => ilmb_port_BRAM_Din, BRAM_Dout_A => ilmb_port_BRAM_Dout, BRAM_Rst_B => dlmb_port_BRAM_Rst, BRAM_Clk_B => dlmb_port_BRAM_Clk, BRAM_EN_B => dlmb_port_BRAM_EN, BRAM_WEN_B => dlmb_port_BRAM_WEN, BRAM_Addr_B => dlmb_port_BRAM_Addr, BRAM_Din_B => dlmb_port_BRAM_Din, BRAM_Dout_B => dlmb_port_BRAM_Dout ); USB_UART : usb_uart_wrapper port map ( SPLB_Clk => clk_66_6667MHz, SPLB_Rst => mb_plb_SPLB_Rst(0), PLB_ABus => mb_plb_PLB_ABus, PLB_PAValid => mb_plb_PLB_PAValid, PLB_masterID => mb_plb_PLB_masterID(0 to 0), PLB_RNW => mb_plb_PLB_RNW, PLB_BE => mb_plb_PLB_BE, PLB_size => mb_plb_PLB_size, PLB_type => mb_plb_PLB_type, PLB_wrDBus => mb_plb_PLB_wrDBus, PLB_UABus => mb_plb_PLB_UABus, PLB_SAValid => mb_plb_PLB_SAValid, PLB_rdPrim => mb_plb_PLB_rdPrim(0), PLB_wrPrim => mb_plb_PLB_wrPrim(0), PLB_abort => mb_plb_PLB_abort, PLB_busLock => mb_plb_PLB_busLock, PLB_MSize => mb_plb_PLB_MSize, PLB_lockErr => mb_plb_PLB_lockErr, PLB_wrBurst => mb_plb_PLB_wrBurst, PLB_rdBurst => mb_plb_PLB_rdBurst, PLB_wrPendReq => mb_plb_PLB_wrPendReq, PLB_rdPendReq => mb_plb_PLB_rdPendReq, PLB_wrPendPri => mb_plb_PLB_wrPendPri, PLB_rdPendPri => mb_plb_PLB_rdPendPri, PLB_reqPri => mb_plb_PLB_reqPri, PLB_TAttribute => mb_plb_PLB_TAttribute, Sl_addrAck => mb_plb_Sl_addrAck(0), Sl_SSize => mb_plb_Sl_SSize(0 to 1), Sl_wait => mb_plb_Sl_wait(0), Sl_rearbitrate => mb_plb_Sl_rearbitrate(0), Sl_wrDAck => mb_plb_Sl_wrDAck(0), Sl_wrComp => mb_plb_Sl_wrComp(0), Sl_rdDBus => mb_plb_Sl_rdDBus(0 to 31), Sl_rdDAck => mb_plb_Sl_rdDAck(0), Sl_rdComp => mb_plb_Sl_rdComp(0), Sl_MBusy => mb_plb_Sl_MBusy(0 to 1), Sl_MWrErr => mb_plb_Sl_MWrErr(0 to 1), Sl_MRdErr => mb_plb_Sl_MRdErr(0 to 1), Sl_wrBTerm => mb_plb_Sl_wrBTerm(0), Sl_rdWdAddr => mb_plb_Sl_rdWdAddr(0 to 3), Sl_rdBTerm => mb_plb_Sl_rdBTerm(0), Sl_MIRQ => mb_plb_Sl_MIRQ(0 to 1), RX => fpga_0_USB_UART_RX_pin, TX => fpga_0_USB_UART_TX_pin, Interrupt => USB_UART_Interrupt ); LEDS_4BIT : leds_4bit_wrapper port map ( SPLB_Clk => clk_66_6667MHz, SPLB_Rst => mb_plb_SPLB_Rst(1), PLB_ABus => mb_plb_PLB_ABus, PLB_UABus => mb_plb_PLB_UABus, PLB_PAValid => mb_plb_PLB_PAValid, PLB_SAValid => mb_plb_PLB_SAValid, PLB_rdPrim => mb_plb_PLB_rdPrim(1), PLB_wrPrim => mb_plb_PLB_wrPrim(1), PLB_masterID => mb_plb_PLB_masterID(0 to 0), PLB_abort => mb_plb_PLB_abort, PLB_busLock => mb_plb_PLB_busLock, PLB_RNW => mb_plb_PLB_RNW, PLB_BE => mb_plb_PLB_BE, PLB_MSize => mb_plb_PLB_MSize, PLB_size => mb_plb_PLB_size, PLB_type => mb_plb_PLB_type, PLB_lockErr => mb_plb_PLB_lockErr, PLB_wrDBus => mb_plb_PLB_wrDBus, PLB_wrBurst => mb_plb_PLB_wrBurst, PLB_rdBurst => mb_plb_PLB_rdBurst, PLB_wrPendReq => mb_plb_PLB_wrPendReq, PLB_rdPendReq => mb_plb_PLB_rdPendReq, PLB_wrPendPri => mb_plb_PLB_wrPendPri, PLB_rdPendPri => mb_plb_PLB_rdPendPri, PLB_reqPri => mb_plb_PLB_reqPri, PLB_TAttribute => mb_plb_PLB_TAttribute, Sl_addrAck => mb_plb_Sl_addrAck(1), Sl_SSize => mb_plb_Sl_SSize(2 to 3), Sl_wait => mb_plb_Sl_wait(1), Sl_rearbitrate => mb_plb_Sl_rearbitrate(1), Sl_wrDAck => mb_plb_Sl_wrDAck(1), Sl_wrComp => mb_plb_Sl_wrComp(1), Sl_wrBTerm => mb_plb_Sl_wrBTerm(1), Sl_rdDBus => mb_plb_Sl_rdDBus(32 to 63), Sl_rdWdAddr => mb_plb_Sl_rdWdAddr(4 to 7), Sl_rdDAck => mb_plb_Sl_rdDAck(1), Sl_rdComp => mb_plb_Sl_rdComp(1), Sl_rdBTerm => mb_plb_Sl_rdBTerm(1), Sl_MBusy => mb_plb_Sl_MBusy(2 to 3), Sl_MWrErr => mb_plb_Sl_MWrErr(2 to 3), Sl_MRdErr => mb_plb_Sl_MRdErr(2 to 3), Sl_MIRQ => mb_plb_Sl_MIRQ(2 to 3), IP2INTC_Irpt => open, GPIO_IO_I => fpga_0_LEDS_4BIT_GPIO_IO_pin_I, GPIO_IO_O => fpga_0_LEDS_4BIT_GPIO_IO_pin_O, GPIO_IO_T => fpga_0_LEDS_4BIT_GPIO_IO_pin_T, GPIO2_IO_I => net_gnd32, GPIO2_IO_O => open, GPIO2_IO_T => open ); CS_PUSH_3BIT : cs_push_3bit_wrapper port map ( SPLB_Clk => clk_66_6667MHz, SPLB_Rst => mb_plb_SPLB_Rst(2), PLB_ABus => mb_plb_PLB_ABus, PLB_UABus => mb_plb_PLB_UABus, PLB_PAValid => mb_plb_PLB_PAValid, PLB_SAValid => mb_plb_PLB_SAValid, PLB_rdPrim => mb_plb_PLB_rdPrim(2), PLB_wrPrim => mb_plb_PLB_wrPrim(2), PLB_masterID => mb_plb_PLB_masterID(0 to 0), PLB_abort => mb_plb_PLB_abort, PLB_busLock => mb_plb_PLB_busLock, PLB_RNW => mb_plb_PLB_RNW, PLB_BE => mb_plb_PLB_BE, PLB_MSize => mb_plb_PLB_MSize, PLB_size => mb_plb_PLB_size, PLB_type => mb_plb_PLB_type, PLB_lockErr => mb_plb_PLB_lockErr, PLB_wrDBus => mb_plb_PLB_wrDBus, PLB_wrBurst => mb_plb_PLB_wrBurst, PLB_rdBurst => mb_plb_PLB_rdBurst, PLB_wrPendReq => mb_plb_PLB_wrPendReq, PLB_rdPendReq => mb_plb_PLB_rdPendReq, PLB_wrPendPri => mb_plb_PLB_wrPendPri, PLB_rdPendPri => mb_plb_PLB_rdPendPri, PLB_reqPri => mb_plb_PLB_reqPri, PLB_TAttribute => mb_plb_PLB_TAttribute, Sl_addrAck => mb_plb_Sl_addrAck(2), Sl_SSize => mb_plb_Sl_SSize(4 to 5), Sl_wait => mb_plb_Sl_wait(2), Sl_rearbitrate => mb_plb_Sl_rearbitrate(2), Sl_wrDAck => mb_plb_Sl_wrDAck(2), Sl_wrComp => mb_plb_Sl_wrComp(2), Sl_wrBTerm => mb_plb_Sl_wrBTerm(2), Sl_rdDBus => mb_plb_Sl_rdDBus(64 to 95), Sl_rdWdAddr => mb_plb_Sl_rdWdAddr(8 to 11), Sl_rdDAck => mb_plb_Sl_rdDAck(2), Sl_rdComp => mb_plb_Sl_rdComp(2), Sl_rdBTerm => mb_plb_Sl_rdBTerm(2), Sl_MBusy => mb_plb_Sl_MBusy(4 to 5), Sl_MWrErr => mb_plb_Sl_MWrErr(4 to 5), Sl_MRdErr => mb_plb_Sl_MRdErr(4 to 5), Sl_MIRQ => mb_plb_Sl_MIRQ(4 to 5), IP2INTC_Irpt => open, GPIO_IO_I => fpga_0_CS_PUSH_3BIT_GPIO_IO_I_pin, GPIO_IO_O => open, GPIO_IO_T => open, GPIO2_IO_I => net_gnd32, GPIO2_IO_O => open, GPIO2_IO_T => open ); TEMP_SENSOR : temp_sensor_wrapper port map ( Sda_I => fpga_0_TEMP_SENSOR_Sda_pin_I, Sda_O => fpga_0_TEMP_SENSOR_Sda_pin_O, Sda_T => fpga_0_TEMP_SENSOR_Sda_pin_T, Scl_I => fpga_0_TEMP_SENSOR_Scl_pin_I, Scl_O => fpga_0_TEMP_SENSOR_Scl_pin_O, Scl_T => fpga_0_TEMP_SENSOR_Scl_pin_T, Gpo => open, IIC2INTC_Irpt => TEMP_SENSOR_IIC2INTC_Irpt, SPLB_Clk => clk_66_6667MHz, SPLB_Rst => mb_plb_SPLB_Rst(3), PLB_ABus => mb_plb_PLB_ABus, PLB_UABus => mb_plb_PLB_UABus, PLB_PAValid => mb_plb_PLB_PAValid, PLB_SAValid => mb_plb_PLB_SAValid, PLB_rdPrim => mb_plb_PLB_rdPrim(3), PLB_wrPrim => mb_plb_PLB_wrPrim(3), PLB_masterID => mb_plb_PLB_masterID(0 to 0), PLB_abort => mb_plb_PLB_abort, PLB_busLock => mb_plb_PLB_busLock, PLB_RNW => mb_plb_PLB_RNW, PLB_BE => mb_plb_PLB_BE, PLB_MSize => mb_plb_PLB_MSize, PLB_size => mb_plb_PLB_size, PLB_type => mb_plb_PLB_type, PLB_lockErr => mb_plb_PLB_lockErr, PLB_wrDBus => mb_plb_PLB_wrDBus, PLB_wrBurst => mb_plb_PLB_wrBurst, PLB_rdBurst => mb_plb_PLB_rdBurst, PLB_wrPendReq => mb_plb_PLB_wrPendReq, PLB_rdPendReq => mb_plb_PLB_rdPendReq, PLB_wrPendPri => mb_plb_PLB_wrPendPri, PLB_rdPendPri => mb_plb_PLB_rdPendPri, PLB_reqPri => mb_plb_PLB_reqPri, PLB_TAttribute => mb_plb_PLB_TAttribute, Sl_addrAck => mb_plb_Sl_addrAck(3), Sl_SSize => mb_plb_Sl_SSize(6 to 7), Sl_wait => mb_plb_Sl_wait(3), Sl_rearbitrate => mb_plb_Sl_rearbitrate(3), Sl_wrDAck => mb_plb_Sl_wrDAck(3), Sl_wrComp => mb_plb_Sl_wrComp(3), Sl_wrBTerm => mb_plb_Sl_wrBTerm(3), Sl_rdDBus => mb_plb_Sl_rdDBus(96 to 127), Sl_rdWdAddr => mb_plb_Sl_rdWdAddr(12 to 15), Sl_rdDAck => mb_plb_Sl_rdDAck(3), Sl_rdComp => mb_plb_Sl_rdComp(3), Sl_rdBTerm => mb_plb_Sl_rdBTerm(3), Sl_MBusy => mb_plb_Sl_MBusy(6 to 7), Sl_MWrErr => mb_plb_Sl_MWrErr(6 to 7), Sl_MRdErr => mb_plb_Sl_MRdErr(6 to 7), Sl_MIRQ => mb_plb_Sl_MIRQ(6 to 7) ); FLASH_2Mx16 : flash_2mx16_wrapper port map ( MCH_SPLB_Clk => clk_66_6667MHz, RdClk => clk_66_6667MHz, MCH_SPLB_Rst => mb_plb_SPLB_Rst(4), MCH0_Access_Control => microblaze_0_IXCL_FSL_M_Control, MCH0_Access_Data => microblaze_0_IXCL_FSL_M_Data, MCH0_Access_Write => microblaze_0_IXCL_FSL_M_Write, MCH0_Access_Full => microblaze_0_IXCL_FSL_M_Full, MCH0_ReadData_Control => microblaze_0_IXCL_FSL_S_Control, MCH0_ReadData_Data => microblaze_0_IXCL_FSL_S_Data, MCH0_ReadData_Read => microblaze_0_IXCL_FSL_S_Read, MCH0_ReadData_Exists => microblaze_0_IXCL_FSL_S_Exists, MCH1_Access_Control => net_gnd0, MCH1_Access_Data => net_gnd32, MCH1_Access_Write => net_gnd0, MCH1_Access_Full => open, MCH1_ReadData_Control => open, MCH1_ReadData_Data => open, MCH1_ReadData_Read => net_gnd0, MCH1_ReadData_Exists => open, MCH2_Access_Control => net_gnd0, MCH2_Access_Data => net_gnd32, MCH2_Access_Write => net_gnd0, MCH2_Access_Full => open, MCH2_ReadData_Control => open, MCH2_ReadData_Data => open, MCH2_ReadData_Read => net_gnd0, MCH2_ReadData_Exists => open, MCH3_Access_Control => net_gnd0, MCH3_Access_Data => net_gnd32, MCH3_Access_Write => net_gnd0, MCH3_Access_Full => open, MCH3_ReadData_Control => open, MCH3_ReadData_Data => open, MCH3_ReadData_Read => net_gnd0, MCH3_ReadData_Exists => open, PLB_ABus => mb_plb_PLB_ABus, PLB_UABus => mb_plb_PLB_UABus, PLB_PAValid => mb_plb_PLB_PAValid, PLB_SAValid => mb_plb_PLB_SAValid, PLB_rdPrim => mb_plb_PLB_rdPrim(4), PLB_wrPrim => mb_plb_PLB_wrPrim(4), PLB_masterID => mb_plb_PLB_masterID(0 to 0), PLB_abort => mb_plb_PLB_abort, PLB_busLock => mb_plb_PLB_busLock, PLB_RNW => mb_plb_PLB_RNW, PLB_BE => mb_plb_PLB_BE, PLB_MSize => mb_plb_PLB_MSize, PLB_size => mb_plb_PLB_size, PLB_type => mb_plb_PLB_type, PLB_lockErr => mb_plb_PLB_lockErr, PLB_wrDBus => mb_plb_PLB_wrDBus, PLB_wrBurst => mb_plb_PLB_wrBurst, PLB_rdBurst => mb_plb_PLB_rdBurst, PLB_wrPendReq => mb_plb_PLB_wrPendReq, PLB_rdPendReq => mb_plb_PLB_rdPendReq, PLB_wrPendPri => mb_plb_PLB_wrPendPri, PLB_rdPendPri => mb_plb_PLB_rdPendPri, PLB_reqPri => mb_plb_PLB_reqPri, PLB_TAttribute => mb_plb_PLB_TAttribute, Sl_addrAck => mb_plb_Sl_addrAck(4), Sl_SSize => mb_plb_Sl_SSize(8 to 9), Sl_wait => mb_plb_Sl_wait(4), Sl_rearbitrate => mb_plb_Sl_rearbitrate(4), Sl_wrDAck => mb_plb_Sl_wrDAck(4), Sl_wrComp => mb_plb_Sl_wrComp(4), Sl_wrBTerm => mb_plb_Sl_wrBTerm(4), Sl_rdDBus => mb_plb_Sl_rdDBus(128 to 159), Sl_rdWdAddr => mb_plb_Sl_rdWdAddr(16 to 19), Sl_rdDAck => mb_plb_Sl_rdDAck(4), Sl_rdComp => mb_plb_Sl_rdComp(4), Sl_rdBTerm => mb_plb_Sl_rdBTerm(4), Sl_MBusy => mb_plb_Sl_MBusy(8 to 9), Sl_MWrErr => mb_plb_Sl_MWrErr(8 to 9), Sl_MRdErr => mb_plb_Sl_MRdErr(8 to 9), Sl_MIRQ => mb_plb_Sl_MIRQ(8 to 9), Mem_DQ_I => fpga_0_FLASH_2Mx16_Mem_DQ_pin_I, Mem_DQ_O => fpga_0_FLASH_2Mx16_Mem_DQ_pin_O, Mem_DQ_T => fpga_0_FLASH_2Mx16_Mem_DQ_pin_T, Mem_A => pgassign5, Mem_RPN => fpga_0_FLASH_2Mx16_Mem_RPN_pin, Mem_CEN => pgassign1(0 to 0), Mem_OEN => pgassign2(0 to 0), Mem_WEN => fpga_0_FLASH_2Mx16_Mem_WEN_pin, Mem_QWEN => open, Mem_BEN => open, Mem_CE => open, Mem_ADV_LDN => open, Mem_LBON => open, Mem_CKEN => open, Mem_RNW => open ); xps_timer_0 : xps_timer_0_wrapper port map ( CaptureTrig0 => net_gnd0, CaptureTrig1 => net_gnd0, GenerateOut0 => open, GenerateOut1 => open, PWM0 => open, Interrupt => xps_timer_0_Interrupt, Freeze => net_gnd0, SPLB_Clk => clk_66_6667MHz, SPLB_Rst => mb_plb_SPLB_Rst(5), PLB_ABus => mb_plb_PLB_ABus, PLB_PAValid => mb_plb_PLB_PAValid, PLB_masterID => mb_plb_PLB_masterID(0 to 0), PLB_RNW => mb_plb_PLB_RNW, PLB_BE => mb_plb_PLB_BE, PLB_size => mb_plb_PLB_size, PLB_type => mb_plb_PLB_type, PLB_wrDBus => mb_plb_PLB_wrDBus, Sl_addrAck => mb_plb_Sl_addrAck(5), Sl_SSize => mb_plb_Sl_SSize(10 to 11), Sl_wait => mb_plb_Sl_wait(5), Sl_rearbitrate => mb_plb_Sl_rearbitrate(5), Sl_wrDAck => mb_plb_Sl_wrDAck(5), Sl_wrComp => mb_plb_Sl_wrComp(5), Sl_rdDBus => mb_plb_Sl_rdDBus(160 to 191), Sl_rdDAck => mb_plb_Sl_rdDAck(5), Sl_rdComp => mb_plb_Sl_rdComp(5), Sl_MBusy => mb_plb_Sl_MBusy(10 to 11), Sl_MWrErr => mb_plb_Sl_MWrErr(10 to 11), Sl_MRdErr => mb_plb_Sl_MRdErr(10 to 11), PLB_UABus => mb_plb_PLB_UABus, PLB_SAValid => mb_plb_PLB_SAValid, PLB_rdPrim => mb_plb_PLB_rdPrim(5), PLB_wrPrim => mb_plb_PLB_wrPrim(5), PLB_abort => mb_plb_PLB_abort, PLB_busLock => mb_plb_PLB_busLock, PLB_MSize => mb_plb_PLB_MSize, PLB_lockErr => mb_plb_PLB_lockErr, PLB_wrBurst => mb_plb_PLB_wrBurst, PLB_rdBurst => mb_plb_PLB_rdBurst, PLB_wrPendReq => mb_plb_PLB_wrPendReq, PLB_rdPendReq => mb_plb_PLB_rdPendReq, PLB_wrPendPri => mb_plb_PLB_wrPendPri, PLB_rdPendPri => mb_plb_PLB_rdPendPri, PLB_reqPri => mb_plb_PLB_reqPri, PLB_TAttribute => mb_plb_PLB_TAttribute, Sl_wrBTerm => mb_plb_Sl_wrBTerm(5), Sl_rdWdAddr => mb_plb_Sl_rdWdAddr(20 to 23), Sl_rdBTerm => mb_plb_Sl_rdBTerm(5), Sl_MIRQ => mb_plb_Sl_MIRQ(10 to 11) ); clock_generator_0 : clock_generator_0_wrapper port map ( CLKIN => dcm_clk_s, CLKOUT0 => clk_66_6667MHz, CLKOUT1 => open, CLKOUT2 => open, CLKOUT3 => open, CLKOUT4 => open, CLKOUT5 => open, CLKOUT6 => open, CLKOUT7 => open, CLKOUT8 => open, CLKOUT9 => open, CLKOUT10 => open, CLKOUT11 => open, CLKOUT12 => open, CLKOUT13 => open, CLKOUT14 => open, CLKOUT15 => open, CLKFBIN => net_gnd0, CLKFBOUT => open, PSCLK => net_gnd0, PSEN => net_gnd0, PSINCDEC => net_gnd0, PSDONE => open, RST => sys_rst_s, LOCKED => Dcm_all_locked ); mdm_0 : mdm_0_wrapper port map ( Interrupt => open, Debug_SYS_Rst => Debug_SYS_Rst, Ext_BRK => Ext_BRK, Ext_NM_BRK => Ext_NM_BRK, S_AXI_ACLK => net_gnd0, S_AXI_ARESETN => net_gnd0, S_AXI_AWADDR => net_gnd32(0 to 31), S_AXI_AWVALID => net_gnd0, S_AXI_AWREADY => open, S_AXI_WDATA => net_gnd32(0 to 31), S_AXI_WSTRB => net_gnd4(0 to 3), S_AXI_WVALID => net_gnd0, S_AXI_WREADY => open, S_AXI_BRESP => open, S_AXI_BVALID => open, S_AXI_BREADY => net_gnd0, S_AXI_ARADDR => net_gnd32(0 to 31), S_AXI_ARVALID => net_gnd0, S_AXI_ARREADY => open, S_AXI_RDATA => open, S_AXI_RRESP => open, S_AXI_RVALID => open, S_AXI_RREADY => net_gnd0, SPLB_Clk => clk_66_6667MHz, SPLB_Rst => mb_plb_SPLB_Rst(6), PLB_ABus => mb_plb_PLB_ABus, PLB_UABus => mb_plb_PLB_UABus, PLB_PAValid => mb_plb_PLB_PAValid, PLB_SAValid => mb_plb_PLB_SAValid, PLB_rdPrim => mb_plb_PLB_rdPrim(6), PLB_wrPrim => mb_plb_PLB_wrPrim(6), PLB_masterID => mb_plb_PLB_masterID(0 to 0), PLB_abort => mb_plb_PLB_abort, PLB_busLock => mb_plb_PLB_busLock, PLB_RNW => mb_plb_PLB_RNW, PLB_BE => mb_plb_PLB_BE, PLB_MSize => mb_plb_PLB_MSize, PLB_size => mb_plb_PLB_size, PLB_type => mb_plb_PLB_type, PLB_lockErr => mb_plb_PLB_lockErr, PLB_wrDBus => mb_plb_PLB_wrDBus, PLB_wrBurst => mb_plb_PLB_wrBurst, PLB_rdBurst => mb_plb_PLB_rdBurst, PLB_wrPendReq => mb_plb_PLB_wrPendReq, PLB_rdPendReq => mb_plb_PLB_rdPendReq, PLB_wrPendPri => mb_plb_PLB_wrPendPri, PLB_rdPendPri => mb_plb_PLB_rdPendPri, PLB_reqPri => mb_plb_PLB_reqPri, PLB_TAttribute => mb_plb_PLB_TAttribute, Sl_addrAck => mb_plb_Sl_addrAck(6), Sl_SSize => mb_plb_Sl_SSize(12 to 13), Sl_wait => mb_plb_Sl_wait(6), Sl_rearbitrate => mb_plb_Sl_rearbitrate(6), Sl_wrDAck => mb_plb_Sl_wrDAck(6), Sl_wrComp => mb_plb_Sl_wrComp(6), Sl_wrBTerm => mb_plb_Sl_wrBTerm(6), Sl_rdDBus => mb_plb_Sl_rdDBus(192 to 223), Sl_rdWdAddr => mb_plb_Sl_rdWdAddr(24 to 27), Sl_rdDAck => mb_plb_Sl_rdDAck(6), Sl_rdComp => mb_plb_Sl_rdComp(6), Sl_rdBTerm => mb_plb_Sl_rdBTerm(6), Sl_MBusy => mb_plb_Sl_MBusy(12 to 13), Sl_MWrErr => mb_plb_Sl_MWrErr(12 to 13), Sl_MRdErr => mb_plb_Sl_MRdErr(12 to 13), Sl_MIRQ => mb_plb_Sl_MIRQ(12 to 13), Dbg_Clk_0 => microblaze_0_mdm_bus_Dbg_Clk, Dbg_TDI_0 => microblaze_0_mdm_bus_Dbg_TDI, Dbg_TDO_0 => microblaze_0_mdm_bus_Dbg_TDO, Dbg_Reg_En_0 => microblaze_0_mdm_bus_Dbg_Reg_En, Dbg_Capture_0 => microblaze_0_mdm_bus_Dbg_Capture, Dbg_Shift_0 => microblaze_0_mdm_bus_Dbg_Shift, Dbg_Update_0 => microblaze_0_mdm_bus_Dbg_Update, Dbg_Rst_0 => microblaze_0_mdm_bus_Debug_Rst, Dbg_Clk_1 => open, Dbg_TDI_1 => open, Dbg_TDO_1 => net_gnd0, Dbg_Reg_En_1 => open, Dbg_Capture_1 => open, Dbg_Shift_1 => open, Dbg_Update_1 => open, Dbg_Rst_1 => open, Dbg_Clk_2 => open, Dbg_TDI_2 => open, Dbg_TDO_2 => net_gnd0, Dbg_Reg_En_2 => open, Dbg_Capture_2 => open, Dbg_Shift_2 => open, Dbg_Update_2 => open, Dbg_Rst_2 => open, Dbg_Clk_3 => open, Dbg_TDI_3 => open, Dbg_TDO_3 => net_gnd0, Dbg_Reg_En_3 => open, Dbg_Capture_3 => open, Dbg_Shift_3 => open, Dbg_Update_3 => open, Dbg_Rst_3 => open, Dbg_Clk_4 => open, Dbg_TDI_4 => open, Dbg_TDO_4 => net_gnd0, Dbg_Reg_En_4 => open, Dbg_Capture_4 => open, Dbg_Shift_4 => open, Dbg_Update_4 => open, Dbg_Rst_4 => open, Dbg_Clk_5 => open, Dbg_TDI_5 => open, Dbg_TDO_5 => net_gnd0, Dbg_Reg_En_5 => open, Dbg_Capture_5 => open, Dbg_Shift_5 => open, Dbg_Update_5 => open, Dbg_Rst_5 => open, Dbg_Clk_6 => open, Dbg_TDI_6 => open, Dbg_TDO_6 => net_gnd0, Dbg_Reg_En_6 => open, Dbg_Capture_6 => open, Dbg_Shift_6 => open, Dbg_Update_6 => open, Dbg_Rst_6 => open, Dbg_Clk_7 => open, Dbg_TDI_7 => open, Dbg_TDO_7 => net_gnd0, Dbg_Reg_En_7 => open, Dbg_Capture_7 => open, Dbg_Shift_7 => open, Dbg_Update_7 => open, Dbg_Rst_7 => open, bscan_tdi => open, bscan_reset => open, bscan_shift => open, bscan_update => open, bscan_capture => open, bscan_sel1 => open, bscan_drck1 => open, bscan_tdo1 => net_gnd0, Ext_JTAG_DRCK => open, Ext_JTAG_RESET => open, Ext_JTAG_SEL => open, Ext_JTAG_CAPTURE => open, Ext_JTAG_SHIFT => open, Ext_JTAG_UPDATE => open, Ext_JTAG_TDI => open, Ext_JTAG_TDO => net_gnd0 ); proc_sys_reset_0 : proc_sys_reset_0_wrapper port map ( Slowest_sync_clk => clk_66_6667MHz, Ext_Reset_In => sys_rst_s, Aux_Reset_In => net_gnd0, MB_Debug_Sys_Rst => Debug_SYS_Rst, Core_Reset_Req_0 => net_gnd0, Chip_Reset_Req_0 => net_gnd0, System_Reset_Req_0 => net_gnd0, Core_Reset_Req_1 => net_gnd0, Chip_Reset_Req_1 => net_gnd0, System_Reset_Req_1 => net_gnd0, Dcm_locked => Dcm_all_locked, RstcPPCresetcore_0 => open, RstcPPCresetchip_0 => open, RstcPPCresetsys_0 => open, RstcPPCresetcore_1 => open, RstcPPCresetchip_1 => open, RstcPPCresetsys_1 => open, MB_Reset => mb_reset, Bus_Struct_Reset => sys_bus_reset(0 to 0), Peripheral_Reset => open, Interconnect_aresetn => open, Peripheral_aresetn => open ); xps_intc_0 : xps_intc_0_wrapper port map ( SPLB_Clk => clk_66_6667MHz, SPLB_Rst => mb_plb_SPLB_Rst(7), PLB_ABus => mb_plb_PLB_ABus, PLB_PAValid => mb_plb_PLB_PAValid, PLB_masterID => mb_plb_PLB_masterID(0 to 0), PLB_RNW => mb_plb_PLB_RNW, PLB_BE => mb_plb_PLB_BE, PLB_size => mb_plb_PLB_size, PLB_type => mb_plb_PLB_type, PLB_wrDBus => mb_plb_PLB_wrDBus, PLB_UABus => mb_plb_PLB_UABus, PLB_SAValid => mb_plb_PLB_SAValid, PLB_rdPrim => mb_plb_PLB_rdPrim(7), PLB_wrPrim => mb_plb_PLB_wrPrim(7), PLB_abort => mb_plb_PLB_abort, PLB_busLock => mb_plb_PLB_busLock, PLB_MSize => mb_plb_PLB_MSize, PLB_lockErr => mb_plb_PLB_lockErr, PLB_wrBurst => mb_plb_PLB_wrBurst, PLB_rdBurst => mb_plb_PLB_rdBurst, PLB_wrPendReq => mb_plb_PLB_wrPendReq, PLB_rdPendReq => mb_plb_PLB_rdPendReq, PLB_wrPendPri => mb_plb_PLB_wrPendPri, PLB_rdPendPri => mb_plb_PLB_rdPendPri, PLB_reqPri => mb_plb_PLB_reqPri, PLB_TAttribute => mb_plb_PLB_TAttribute, Sl_addrAck => mb_plb_Sl_addrAck(7), Sl_SSize => mb_plb_Sl_SSize(14 to 15), Sl_wait => mb_plb_Sl_wait(7), Sl_rearbitrate => mb_plb_Sl_rearbitrate(7), Sl_wrDAck => mb_plb_Sl_wrDAck(7), Sl_wrComp => mb_plb_Sl_wrComp(7), Sl_rdDBus => mb_plb_Sl_rdDBus(224 to 255), Sl_rdDAck => mb_plb_Sl_rdDAck(7), Sl_rdComp => mb_plb_Sl_rdComp(7), Sl_MBusy => mb_plb_Sl_MBusy(14 to 15), Sl_MWrErr => mb_plb_Sl_MWrErr(14 to 15), Sl_MRdErr => mb_plb_Sl_MRdErr(14 to 15), Sl_wrBTerm => mb_plb_Sl_wrBTerm(7), Sl_rdWdAddr => mb_plb_Sl_rdWdAddr(28 to 31), Sl_rdBTerm => mb_plb_Sl_rdBTerm(7), Sl_MIRQ => mb_plb_Sl_MIRQ(14 to 15), Intr => pgassign6, Irq => microblaze_0_Interrupt ); MSP430_UART : msp430_uart_wrapper port map ( SPLB_Clk => clk_66_6667MHz, SPLB_Rst => mb_plb_SPLB_Rst(8), PLB_ABus => mb_plb_PLB_ABus, PLB_PAValid => mb_plb_PLB_PAValid, PLB_masterID => mb_plb_PLB_masterID(0 to 0), PLB_RNW => mb_plb_PLB_RNW, PLB_BE => mb_plb_PLB_BE, PLB_size => mb_plb_PLB_size, PLB_type => mb_plb_PLB_type, PLB_wrDBus => mb_plb_PLB_wrDBus, PLB_UABus => mb_plb_PLB_UABus, PLB_SAValid => mb_plb_PLB_SAValid, PLB_rdPrim => mb_plb_PLB_rdPrim(8), PLB_wrPrim => mb_plb_PLB_wrPrim(8), PLB_abort => mb_plb_PLB_abort, PLB_busLock => mb_plb_PLB_busLock, PLB_MSize => mb_plb_PLB_MSize, PLB_lockErr => mb_plb_PLB_lockErr, PLB_wrBurst => mb_plb_PLB_wrBurst, PLB_rdBurst => mb_plb_PLB_rdBurst, PLB_wrPendReq => mb_plb_PLB_wrPendReq, PLB_rdPendReq => mb_plb_PLB_rdPendReq, PLB_wrPendPri => mb_plb_PLB_wrPendPri, PLB_rdPendPri => mb_plb_PLB_rdPendPri, PLB_reqPri => mb_plb_PLB_reqPri, PLB_TAttribute => mb_plb_PLB_TAttribute, Sl_addrAck => mb_plb_Sl_addrAck(8), Sl_SSize => mb_plb_Sl_SSize(16 to 17), Sl_wait => mb_plb_Sl_wait(8), Sl_rearbitrate => mb_plb_Sl_rearbitrate(8), Sl_wrDAck => mb_plb_Sl_wrDAck(8), Sl_wrComp => mb_plb_Sl_wrComp(8), Sl_rdDBus => mb_plb_Sl_rdDBus(256 to 287), Sl_rdDAck => mb_plb_Sl_rdDAck(8), Sl_rdComp => mb_plb_Sl_rdComp(8), Sl_MBusy => mb_plb_Sl_MBusy(16 to 17), Sl_MWrErr => mb_plb_Sl_MWrErr(16 to 17), Sl_MRdErr => mb_plb_Sl_MRdErr(16 to 17), Sl_wrBTerm => mb_plb_Sl_wrBTerm(8), Sl_rdWdAddr => mb_plb_Sl_rdWdAddr(32 to 35), Sl_rdBTerm => mb_plb_Sl_rdBTerm(8), Sl_MIRQ => mb_plb_Sl_MIRQ(16 to 17), RX => MSP430_UART_RX, TX => MSP430_UART_TX, Interrupt => MSP430_UART_Interrupt ); iobuf_0 : IOBUF port map ( I => fpga_0_LEDS_4BIT_GPIO_IO_pin_O(0), IO => fpga_0_LEDS_4BIT_GPIO_IO_pin(0), O => fpga_0_LEDS_4BIT_GPIO_IO_pin_I(0), T => fpga_0_LEDS_4BIT_GPIO_IO_pin_T(0) ); iobuf_1 : IOBUF port map ( I => fpga_0_LEDS_4BIT_GPIO_IO_pin_O(1), IO => fpga_0_LEDS_4BIT_GPIO_IO_pin(1), O => fpga_0_LEDS_4BIT_GPIO_IO_pin_I(1), T => fpga_0_LEDS_4BIT_GPIO_IO_pin_T(1) ); iobuf_2 : IOBUF port map ( I => fpga_0_LEDS_4BIT_GPIO_IO_pin_O(2), IO => fpga_0_LEDS_4BIT_GPIO_IO_pin(2), O => fpga_0_LEDS_4BIT_GPIO_IO_pin_I(2), T => fpga_0_LEDS_4BIT_GPIO_IO_pin_T(2) ); iobuf_3 : IOBUF port map ( I => fpga_0_LEDS_4BIT_GPIO_IO_pin_O(3), IO => fpga_0_LEDS_4BIT_GPIO_IO_pin(3), O => fpga_0_LEDS_4BIT_GPIO_IO_pin_I(3), T => fpga_0_LEDS_4BIT_GPIO_IO_pin_T(3) ); iobuf_4 : IOBUF port map ( I => fpga_0_TEMP_SENSOR_Sda_pin_O, IO => fpga_0_TEMP_SENSOR_Sda_pin, O => fpga_0_TEMP_SENSOR_Sda_pin_I, T => fpga_0_TEMP_SENSOR_Sda_pin_T ); iobuf_5 : IOBUF port map ( I => fpga_0_TEMP_SENSOR_Scl_pin_O, IO => fpga_0_TEMP_SENSOR_Scl_pin, O => fpga_0_TEMP_SENSOR_Scl_pin_I, T => fpga_0_TEMP_SENSOR_Scl_pin_T ); iobuf_6 : IOBUF port map ( I => fpga_0_FLASH_2Mx16_Mem_DQ_pin_O(0), IO => fpga_0_FLASH_2Mx16_Mem_DQ_pin(0), O => fpga_0_FLASH_2Mx16_Mem_DQ_pin_I(0), T => fpga_0_FLASH_2Mx16_Mem_DQ_pin_T(0) ); iobuf_7 : IOBUF port map ( I => fpga_0_FLASH_2Mx16_Mem_DQ_pin_O(1), IO => fpga_0_FLASH_2Mx16_Mem_DQ_pin(1), O => fpga_0_FLASH_2Mx16_Mem_DQ_pin_I(1), T => fpga_0_FLASH_2Mx16_Mem_DQ_pin_T(1) ); iobuf_8 : IOBUF port map ( I => fpga_0_FLASH_2Mx16_Mem_DQ_pin_O(2), IO => fpga_0_FLASH_2Mx16_Mem_DQ_pin(2), O => fpga_0_FLASH_2Mx16_Mem_DQ_pin_I(2), T => fpga_0_FLASH_2Mx16_Mem_DQ_pin_T(2) ); iobuf_9 : IOBUF port map ( I => fpga_0_FLASH_2Mx16_Mem_DQ_pin_O(3), IO => fpga_0_FLASH_2Mx16_Mem_DQ_pin(3), O => fpga_0_FLASH_2Mx16_Mem_DQ_pin_I(3), T => fpga_0_FLASH_2Mx16_Mem_DQ_pin_T(3) ); iobuf_10 : IOBUF port map ( I => fpga_0_FLASH_2Mx16_Mem_DQ_pin_O(4), IO => fpga_0_FLASH_2Mx16_Mem_DQ_pin(4), O => fpga_0_FLASH_2Mx16_Mem_DQ_pin_I(4), T => fpga_0_FLASH_2Mx16_Mem_DQ_pin_T(4) ); iobuf_11 : IOBUF port map ( I => fpga_0_FLASH_2Mx16_Mem_DQ_pin_O(5), IO => fpga_0_FLASH_2Mx16_Mem_DQ_pin(5), O => fpga_0_FLASH_2Mx16_Mem_DQ_pin_I(5), T => fpga_0_FLASH_2Mx16_Mem_DQ_pin_T(5) ); iobuf_12 : IOBUF port map ( I => fpga_0_FLASH_2Mx16_Mem_DQ_pin_O(6), IO => fpga_0_FLASH_2Mx16_Mem_DQ_pin(6), O => fpga_0_FLASH_2Mx16_Mem_DQ_pin_I(6), T => fpga_0_FLASH_2Mx16_Mem_DQ_pin_T(6) ); iobuf_13 : IOBUF port map ( I => fpga_0_FLASH_2Mx16_Mem_DQ_pin_O(7), IO => fpga_0_FLASH_2Mx16_Mem_DQ_pin(7), O => fpga_0_FLASH_2Mx16_Mem_DQ_pin_I(7), T => fpga_0_FLASH_2Mx16_Mem_DQ_pin_T(7) ); iobuf_14 : IOBUF port map ( I => fpga_0_FLASH_2Mx16_Mem_DQ_pin_O(8), IO => fpga_0_FLASH_2Mx16_Mem_DQ_pin(8), O => fpga_0_FLASH_2Mx16_Mem_DQ_pin_I(8), T => fpga_0_FLASH_2Mx16_Mem_DQ_pin_T(8) ); iobuf_15 : IOBUF port map ( I => fpga_0_FLASH_2Mx16_Mem_DQ_pin_O(9), IO => fpga_0_FLASH_2Mx16_Mem_DQ_pin(9), O => fpga_0_FLASH_2Mx16_Mem_DQ_pin_I(9), T => fpga_0_FLASH_2Mx16_Mem_DQ_pin_T(9) ); iobuf_16 : IOBUF port map ( I => fpga_0_FLASH_2Mx16_Mem_DQ_pin_O(10), IO => fpga_0_FLASH_2Mx16_Mem_DQ_pin(10), O => fpga_0_FLASH_2Mx16_Mem_DQ_pin_I(10), T => fpga_0_FLASH_2Mx16_Mem_DQ_pin_T(10) ); iobuf_17 : IOBUF port map ( I => fpga_0_FLASH_2Mx16_Mem_DQ_pin_O(11), IO => fpga_0_FLASH_2Mx16_Mem_DQ_pin(11), O => fpga_0_FLASH_2Mx16_Mem_DQ_pin_I(11), T => fpga_0_FLASH_2Mx16_Mem_DQ_pin_T(11) ); iobuf_18 : IOBUF port map ( I => fpga_0_FLASH_2Mx16_Mem_DQ_pin_O(12), IO => fpga_0_FLASH_2Mx16_Mem_DQ_pin(12), O => fpga_0_FLASH_2Mx16_Mem_DQ_pin_I(12), T => fpga_0_FLASH_2Mx16_Mem_DQ_pin_T(12) ); iobuf_19 : IOBUF port map ( I => fpga_0_FLASH_2Mx16_Mem_DQ_pin_O(13), IO => fpga_0_FLASH_2Mx16_Mem_DQ_pin(13), O => fpga_0_FLASH_2Mx16_Mem_DQ_pin_I(13), T => fpga_0_FLASH_2Mx16_Mem_DQ_pin_T(13) ); iobuf_20 : IOBUF port map ( I => fpga_0_FLASH_2Mx16_Mem_DQ_pin_O(14), IO => fpga_0_FLASH_2Mx16_Mem_DQ_pin(14), O => fpga_0_FLASH_2Mx16_Mem_DQ_pin_I(14), T => fpga_0_FLASH_2Mx16_Mem_DQ_pin_T(14) ); iobuf_21 : IOBUF port map ( I => fpga_0_FLASH_2Mx16_Mem_DQ_pin_O(15), IO => fpga_0_FLASH_2Mx16_Mem_DQ_pin(15), O => fpga_0_FLASH_2Mx16_Mem_DQ_pin_I(15), T => fpga_0_FLASH_2Mx16_Mem_DQ_pin_T(15) ); end architecture STRUCTURE;
mit
5ad6389fc11f00691b3d56d462741f28
0.591139
2.904149
false
false
false
false
abyrne55/my-little-processor
find_ns.vhd
1
3,341
LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY find_ns IS PORT ( state : IN INTEGER; reset : IN STD_LOGIC; instr : IN STD_LOGIC_VECTOR(3 DOWNTO 0); rx, ry : IN STD_LOGIC_VECTOR(3 DOWNTO 0); ns : OUT INTEGER ); END find_ns; ARCHITECTURE behavioural OF find_ns IS BEGIN PROCESS (state, instr, reset, rx, ry) BEGIN IF reset = '1' THEN ns <= 255; -- LOAD Rx ELSIF state = 0 AND instr = "0000" THEN ns <= 10; -- MOV Ry into Rx ELSIF state = 0 AND instr = "0001" THEN IF rx = "0000" AND ry = "0001" THEN ns <= 20; ELSIF rx = "0001" AND ry = "0000" THEN ns <= 21; ELSE ns <= 255; END IF; -- ADD, store in Rx ELSIF state = 0 AND instr = "0010" THEN ns <= 30; -- XOR, store in Rx ELSIF state = 0 AND instr = "0011" THEN IF rx = "0000" AND ry = "0001" THEN ns <= 40; ELSIF rx = "0001" AND ry = "0000" THEN ns <= 41; ELSE ns <= 255; END IF; -- LDPC, Store PC in Rx ELSIF state = 0 AND instr = "0100" THEN IF rx = "0000" THEN ns <= 50; ELSIF rx = "0001" THEN ns <= 51; ELSE ns <= 255; END IF; -- BRANCH, Load PC from Rx ELSIF state = 0 AND instr = "0101" THEN IF rx = "0000" THEN ns <= 60; ELSIF rx = "0001" THEN ns <= 61; ELSE ns <= 255; END IF; -- Double Ry, store in Rx ELSIF state = 0 AND instr = "0110" THEN IF rx = "0000" AND ry = "0000" THEN ns <= 701; ELSIF rx = "0001" AND ry = "0000" THEN ns <= 711; ELSIF rx = "0000" AND ry = "0001" THEN ns <= 721; ELSIF rx = "0001" AND ry = "0001" THEN ns <= 731; ELSE ns <= 255; END IF; -- LOAD ELSIF state = 10 THEN IF rx = "0000" THEN ns <= 11; ELSIF rx = "0001" THEN ns <= 12; ELSE ns <= 255; END IF; ELSIF state = 11 THEN ns <= 13; ELSIF state = 12 THEN ns <= 13; ELSIF state = 13 THEN ns <= 0; -- MOV ELSIF state = 20 THEN ns <= 22; ELSIF state = 21 THEN ns <= 22; ELSIF state = 22 THEN ns <= 0; -- ADD ELSIF state = 30 THEN ns <= 31; ELSIF state = 31 THEN IF rx = "0000" AND ry = "0001" THEN ns <= 32; ELSIF rx = "0001" AND ry = "0000" THEN ns <= 33; ELSE ns <= 255; END IF; ELSIF state = 32 THEN ns <= 34; ELSIF state = 32 THEN ns <= 34; ELSIF state = 34 THEN ns <= 0; -- XOR ELSIF state = 40 THEN ns <= 42; ELSIF state = 41 THEN ns <= 42; ELSIF state = 42 THEN ns <= 0; -- LDPC ELSIF state = 50 THEN ns <= 52; ELSIF state = 51 THEN ns <= 52; ELSIF state = 52 THEN ns <= 0; -- BRANCH ELSIF state = 60 THEN ns <= 62; ELSIF state = 61 THEN ns <= 62; ELSIF state = 62 THEN ns <= 0; -- Double Ry, store in Rx ELSIF state = 701 THEN ns <= 702; ELSIF state = 702 THEN ns <= 703; ELSIF state = 703 THEN ns <= 740; ELSIF state = 711 THEN ns <= 712; ELSIF state = 712 THEN ns <= 713; ELSIF state = 713 THEN ns <= 740; ELSIF state = 721 THEN ns <= 722; ELSIF state = 722 THEN ns <= 723; ELSIF state = 723 THEN ns <= 740; ELSIF state = 731 THEN ns <= 732; ELSIF state = 732 THEN ns <= 733; ELSIF state = 733 THEN ns <= 740; ELSIF state = 740 THEN ns <= 0; ELSIF state = 255 THEN ns <= 0; ELSE ns <= 255; END IF; END PROCESS; END behavioural;
mit
ca15c68a36d853b1909140979a9e3e32
0.537264
2.798157
false
false
false
false
GSimas/EEL5105
AULA7b/Moore.vhd
1
1,687
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity FSM_Conta is port( CLK, RST: in std_logic; NUM_clk: in std_logic_vector(2 downto 0); contagem: out std_logic_vector(3 downto 0) ); end FSM_Conta; architecture bhv of FSM_Conta is type states is (S0,S1,S2,S3,S4); signal C50: std_logic; signal contador: std_logic_vector(27 downto 0); signal EA, PE: states; begin P1: process(CLK, RST, NUM_clk) begin if RST = '0' then contador <= x"0000000"; EA <= S0; elsif CLK'event and CLK = '1' then contador <= contador + 1; if C50 = '1' then EA <= PE; end if; if NUM_clk = "001" and contador = x"2FAF080" then contador <= x"0000000"; C50 <= '1'; end if; if NUM_clk = "010" and contador = x"17D7840" then contador <= x"0000000"; C50 <= '1'; end if; if NUM_clk = "011" and contador = x"FE502B" then contador <= x"0000000"; C50 <= '1'; end if; if NUM_clk = "100" and contador = x"BEBC20" then contador <= x"0000000"; C50 <= '1'; end if; if NUM_clk = "100" and contador = x"989680" then contador <= x"0000000"; C50 <= '1'; end if; else C50 <= '0'; end if; end process; P2: process(EA) begin case EA is when S0 => contagem <= "0001"; PE <= S1; when S1 => contagem <= "0010"; PE <= S2; when S2 => contagem <= "0011"; PE <= S3; when S3 => contagem <= "0100"; PE <= S4; when S4 => contagem <= "0101"; PE <= S0; end case; end process; end bhv;
mit
c6f7244ae866d60bab0d3afae165942d
0.522229
2.835294
false
false
false
false
abyrne55/my-little-processor
register_16bit.vhd
1
801
LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- 16-bit Register w/ Async. Reset ENTITY register_16bit IS PORT ( input : IN STD_LOGIC_VECTOR(15 DOWNTO 0); enable : IN STD_LOGIC; reset : IN STD_LOGIC; -- async. reset clock : IN STD_LOGIC; do_xor : IN STD_LOGIC; output : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ); END register_16bit; ARCHITECTURE behavioural OF register_16bit IS SIGNAL outtemp : std_logic_vector(15 DOWNTO 0) := "0000000000000000"; BEGIN PROCESS (clock, reset, do_xor) BEGIN IF rising_edge(clock) THEN IF (reset = '1') THEN outtemp <= "0000000000000000"; ELSE IF do_xor = '1' THEN outtemp <= outtemp XOR input; ELSIF enable = '1' THEN outtemp <= input; END IF; END IF; END IF; END PROCESS; output <= outtemp; END behavioural;
mit
5babf0f2b1830b2044efbb532e93d39e
0.660424
2.988806
false
false
false
false
hoglet67/AtomFpga
src/common/AVR8/JTAG_OCD_Prg/OCDProgTCK.vhd
4
25,277
--********************************************************************************************** -- JTAG "Flash" programmer for AVR Core(TCK Clock Domain) -- Version 0.4 -- Modified 20.06.2006 -- Designed by Ruslan Lepetenok --********************************************************************************************** library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use WORK.JTAGPack.all; use WORK.JTAGProgrammerPack.all; use WORK.JTAGDataPack.all; use WORK.JTAGTAPCtrlSMPack.all; entity OCDProgTCK is port( -- JTAG related inputs/outputs TRSTn : in std_logic; -- Optional TMS : in std_logic; TCK : in std_logic; TDI : in std_logic; TDO : out std_logic; TDO_OE : out std_logic; -- From/To cp2 clock domain("Flash" programmer) FlEEPrgAdr : out std_logic_vector(15 downto 0); FlPrgRdData : in std_logic_vector(15 downto 0); EEPrgRdData : in std_logic_vector(7 downto 0); FlEEPrgWrData : out std_logic_vector(15 downto 0); ChipEraseStart : out std_logic; ChipEraseDone : in std_logic; ProgEnable : out std_logic; FlWrMStart : out std_logic; -- Multiple FlWrSStart : out std_logic; -- Single FlRdMStart : out std_logic; -- Multiple FlRdSStart : out std_logic; -- Single EEWrStart : out std_logic; EERdStart : out std_logic; TAPCtrlTLR : out std_logic; -- TAP Controller is in the Test-Logic/Reset state -- CPU reset jtag_rst : out std_logic ); end OCDProgTCK; architecture RTL of OCDProgTCK is signal CurrentTAPState : TAPCtrlState_Type; signal NextTAPState : TAPCtrlState_Type; -- JTAG Registers -- Instruction registers signal InstructionShRg : std_logic_vector(CInstrLength-1 downto 0); -- Shift signal InstructionRg : std_logic_vector(CInstrLength-1 downto 0); -- Update -- Bypass register signal BypassShRg : std_logic; -- Shift(only) -- ********************************************************************** signal IDCODEShRg : std_logic_vector(31 downto 0); signal DataRegsOutMux : std_logic; signal UnusedInstr : std_logic; -- Unsupported instruction -- Reset chain (1 bit length, no updade register) signal ResetShRg : std_logic; -- ************************* Programmer part ******************************************** -- Program chains signal PERSh : std_logic_vector(15 downto 0); -- Programming Enable Register (Shift part ?only?) signal PCRSh : std_logic_vector(14 downto 0); -- Programming Command Register (Shift part) signal PCRUd : std_logic_vector(PCRSh'range); -- Programming Command Register (Update part) signal PCRShIn : std_logic_vector(PCRSh'range); -- Programming Command Register Input signal VFPLSh : std_logic_vector(7 downto 0); -- Virtual Flash Page Load Register (Shift part only) signal VFPRSh : std_logic_vector(7 downto 0); -- Virtual Flash Page Read Register (Shift part only) signal VFPRShIn : std_logic_vector(VFPRSh'range); -- Virtual Flash Page Read Register Input signal ProgEnable_Int : std_logic; -- TCK counter for Virtual Flash Page Load/Read commands signal VFPCnt : std_logic_vector(3 downto 0); signal LdDataLow : std_logic; -- Load low byte of data signal LdDataHigh : std_logic; -- Load high byte of data and runs "Flash" write SM(cp2 clock domain) signal FlashAdrIncrEn : std_logic; -- Enables increment of VFPCnt (when LdDataHigh='1') signal LatchWrData : std_logic; -- Address(16-bit) and Instruction For Write (16-bit) registers located in TCK clock domaim signal FlEEPrgAdr_Int : std_logic_vector(15 downto 0); -- Copy of output -- Address counter length constant CPageAdrCntLength : positive range 7 to 8 := 7; -- 8 for ATmega128, 7 for ATmega16,... -- "Flash" programmer state machines (located in TCK clock domaim) type ChipEraseSMStType is (ChipEraseSMStIdle,ChipEraseSMSt1,ChipEraseSMSt2,ChipEraseSMSt3); signal ChipEraseSM_CurrentState : ChipEraseSMStType; -- Chip erase signal ChipEraseSM_NextState : ChipEraseSMStType; -- Chip erase (combinatorial) signal FlashWr_St : std_logic; -- 2 signal FlashRd_St : std_logic; -- 3 signal EEPROMWr_St : std_logic; -- 4 signal EEPROMRd_St : std_logic; -- 5 signal FuseWr_St : std_logic; -- 6 signal LockWr_St : std_logic; -- 7 signal FuseLockRd_St : std_logic; -- 8 signal SignByteRd_St : std_logic; -- 9 signal LoadNOP_St : std_logic; -- 11 -- EEPROM Write Support signal EEWrStart_Int : std_logic; signal EERdStart_Int : std_logic; begin TAPStateReg:process(TCK,TRSTn) begin if(TRSTn='0') then -- Reset CurrentTAPState <= TestLogicReset; elsif(TCK='1' and TCK'event) then -- Clock(rising edge) CurrentTAPState <= NextTAPState; end if; end process; NextTAPState <= FnTAPNextState(CurrentTAPState,TMS); -- Instruction register InstructionRegisterShift:process(TCK,TRSTn) begin if(TRSTn='0') then -- Reset InstructionShRg <= (others => '0'); elsif(TCK='1' and TCK'event) then -- Clock(rising edge) case CurrentTAPState is --when CaptureIR => InstructionShRg <= InstructionRg(InstructionRg'high downto 2)&"01"; -- !!! TBD !!! when CaptureIR => InstructionShRg <= InstructionRg; -- !!! TBD !!! when ShiftIR => InstructionShRg <= FnJTAGRgSh(InstructionShRg,TDI); when others => null; end case; end if; end process; InstructionRegisterUpdate:process(TCK,TRSTn) begin if (TRSTn='0') then -- Reset InstructionRg <= CInitInstrRegVal; elsif (TCK='0' and TCK'event) then -- Clock(falling edge) if (CurrentTAPState=TestLogicReset) then InstructionRg <= CInitInstrRegVal; -- Set to give IDCODE or BYPASS instruction elsif CurrentTAPState=UpdateIR then InstructionRg <= InstructionShRg; end if; end if; end process; -- Data registers -- ID Code register IDCodeRegisterShift:process(TCK,TRSTn) begin if (TRSTn='0') then -- Reset IDCODEShRg <= (others => '0'); elsif (TCK='1' and TCK'event) then -- Clock(rising edge) if (InstructionRg=C_IDCODE) then -- The Instruction register content enables The Data register shift case CurrentTAPState is when CaptureDR => IDCODEShRg <= CVersion&CPartNumber&CManufacturerId&'1'; when ShiftDR => IDCODEShRg <= FnJTAGRgSh(IDCODEShRg,TDI); when others => null; end case; end if; end if; end process; -- Bypass register BypassRegisterShift:process(TCK,TRSTn) begin if (TRSTn='0') then -- Reset BypassShRg <= '0'; elsif (TCK='1' and TCK'event) then -- Clock(rising edge) if (InstructionRg=C_BYPASS) then -- !!! TBD !!! case CurrentTAPState is when ShiftDR => BypassShRg <= TDI; when others => BypassShRg <= '0'; -- ??? TBD end case; end if; end if; end process; DORegAndTDOOE:process(TCK,TRSTn) begin if (TRSTn='0') then -- Reset TDO <= '0'; TDO_OE <= '0'; elsif (TCK='0' and TCK'event) then -- Clock(falling edge) TDO <= DataRegsOutMux; if (CurrentTAPState=ShiftIR or CurrentTAPState=ShiftDR) then TDO_OE <= '1'; else TDO_OE <= '0'; end if; end if; end process; -- *************************************************************************************** UnusedInstr <= '1' when (InstructionRg=C_UNUSED_3 or InstructionRg=C_UNUSED_D or InstructionRg=C_UNUSED_E or InstructionRg=C_OCD_ACCESS or InstructionRg= C_EX_INST) else '0'; DataRegsOutMux <= InstructionShRg(InstructionShRg'low) when CurrentTAPState=ShiftIR else -- !!! TBD !!! '0' when InstructionRg=C_SAMPLE_PRELOAD or InstructionRg=C_EXTEST else -- !!! TBD !!! IDCODEShRg(IDCODEShRg'low) when InstructionRg=C_IDCODE else ResetShRg when InstructionRg=C_AVR_RESET else PERSh(PERSh'low) when InstructionRg=C_PROG_ENABLE else PCRSh(PCRSh'low) when InstructionRg=C_PROG_COMMANDS else VFPLSh(VFPLSh'low) when InstructionRg=C_PROG_PAGELOAD else VFPRSh(VFPRSh'low) when InstructionRg=C_PROG_PAGEREAD else BypassShRg; -- *************************************************************************************** -- Reset chain (1 bit length, no updade register) ResetRegisterShift:process(TCK) begin if(TCK='1' and TCK'event) then -- Clock(rising edge) if(InstructionRg=C_AVR_RESET and CurrentTAPState=ShiftDR) then ResetShRg <= TDI; end if; end if; end process; jtag_rst <= ResetShRg; -- ************************************************************************************ -- ************************* Programmer part ******************************************** -- ************************************************************************************ -- Programming Enable Register(no update circuit) PER_Shift:process(TCK) begin if(TCK='1' and TCK'event) then -- Clock(rising edge) if(InstructionRg=C_PROG_ENABLE and CurrentTAPState=ShiftDR) then PERSh <= FnJTAGRgSh(PERSh,TDI); end if; end if; end process; -- Programming enable signal generation(!!! TBD !!!) PE_Gen_Rg:process(TCK) begin if(TCK='0' and TCK'event) then -- Clock(falling edge) if(InstructionRg=C_PROG_ENABLE and CurrentTAPState=UpdateDR) then -- ??? if(PERSh=C_ProgEnableVect) then ProgEnable_Int <= '1'; else ProgEnable_Int <= '0'; end if; end if; end if; end process; -- Programming Command Register PCR_Shift:process(TCK) begin if(TCK='1' and TCK'event) then -- Clock(rising edge) if(InstructionRg=C_PROG_COMMANDS) then case CurrentTAPState is when CaptureDR => PCRSh <= PCRShIn; -- Load data when ShiftDR => PCRSh <= FnJTAGRgSh(PCRSh,TDI); when others => null; end case; end if; end if; end process; PCRShIn(14 downto 10) <= PCRSh(14 downto 10); PCRShIn(8) <= PCRSh(8); -- Poll response !!!TBD!!! PCRShIn(9) <= '0' when (ChipEraseSM_CurrentState /= ChipEraseSMStIdle) else '1'; PCRReadSystem:process(TCK) begin if(TCK='1' and TCK'event) then -- Clock(rising edge) if(CurrentTAPState=UpdateDR and InstructionRg=C_PROG_COMMANDS) then if(FlashRd_St='1') then -- Flash read if(PCRSh=C_Prg_3D_1) then PCRShIn(7 downto 0) <= FlPrgRdData(7 downto 0); -- Read low flash byte elsif(PCRSh=C_Prg_3D_2) then PCRShIn(7 downto 0) <= FlPrgRdData(15 downto 8); -- Read high flash byte end if; elsif(EEPROMRd_St='1') then -- EEPROM read if(PCRSh=C_Prg_5D_2) then PCRShIn(7 downto 0) <= EEPrgRdData; end if; elsif(FuseLockRd_St='1') then -- Fuse/Lock bit Read Mode(8) case PCRSh is -- !!!TBD!!! (Length) when C_Prg_8B_1 => -- 8b(8f1) Read Extended Fuse Byte PCRShIn(7 downto 0) <= C_ExtFuseByte; when C_Prg_8C_1 => -- 8c(8f2) Read Fuse High Byte PCRShIn(7 downto 0) <= C_HighFuseByte; when C_Prg_8D_1 => -- 8d(8f3) Read Fuse Low Byte PCRShIn(7 downto 0) <= C_LowFuseByte; when C_Prg_8E_1 => -- 8e(8f4) Read Lock Bits PCRShIn(7 downto 0) <= C_LockBits; when others => null; end case; elsif (SignByteRd_St='1') then -- Signature Byte Read Mode(9/10) if(PCRSh=C_Prg_9C_1) then -- Read Signature Byte(9c) -> 0110010_00000000 case FlEEPrgAdr_Int(3 downto 0) is -- !!!TBD!!! (Length) when x"0" => PCRShIn(7 downto 0) <= C_SignByte1; when x"1" => PCRShIn(7 downto 0) <= C_SignByte2; when x"2" => PCRShIn(7 downto 0) <= C_SignByte3; when others => null; end case; elsif(PCRSh=C_Prg_10C_1) then -- Read Calibration Byte(10c) -> 0110110_00000000 case FlEEPrgAdr_Int(3 downto 0) is -- !!!TBD!!! (Length) when x"0" => PCRShIn(7 downto 0) <= C_CalibrByte1; when x"1" => PCRShIn(7 downto 0) <= C_CalibrByte2; when x"2" => PCRShIn(7 downto 0) <= C_CalibrByte3; when x"3" => PCRShIn(7 downto 0) <= C_CalibrByte4; when others => null; end case; end if; end if; end if; end if; end process; PCR_Update:process(TCK) begin if(TCK='0' and TCK'event) then -- Clock(falling edge) if (CurrentTAPState=UpdateDR and InstructionRg=C_PROG_COMMANDS) then -- Clock enable (!!!InstructionRg=C_PROG_COMMANDS!!!) PCRUd <= PCRSh; end if; end if; end process; -- Virtual Flash Page Load Register(!!!shift only!!!) VFPL_Shift:process(TCK) begin if(TCK='1' and TCK'event) then -- Clock(rising edge) if(InstructionRg=C_PROG_PAGELOAD and CurrentTAPState=ShiftDR) then VFPLSh <= FnJTAGRgSh(VFPLSh,TDI); end if; end if; end process; -- !!! TBD !!! VFPRShIn <= FlPrgRdData(7 downto 0) when VFPCnt(VFPCnt'high)='0' else -- Low Byte FlPrgRdData(15 downto 8); -- High Byte -- Virtual Flash Page Read Register VFPR_Shift:process(TCK) begin if(TCK='1' and TCK'event) then -- Clock(rising edge) if((VFPCnt=x"7" or VFPCnt=x"F"))then -- Load Data (Low/High Byte) !!!TBD!!! VFPRSh <= VFPRShIn; -- Load data elsif(InstructionRg=C_PROG_PAGEREAD and CurrentTAPState=ShiftDR) then VFPRSh <= FnJTAGRgSh(VFPRSh,TDI); end if; end if; end process; -- TCK counter for Virtual Flash Page Load/Read commands VFPCounterReg:process(TCK) begin if(TCK='1' and TCK'event) then -- Clock(rising edge) ??? if(CurrentTAPState=CaptureDR)then -- Clear VFPCnt <= (others => '0'); elsif(CurrentTAPState=ShiftDR and (InstructionRg=C_PROG_PAGELOAD or InstructionRg=C_PROG_PAGEREAD)and (FlashWr_St='1' or FlashRd_St='1')) then -- Was : FlashWr_St='1' only VFPCnt <= VFPCnt+1; -- Increment end if; end if; end process; VFPWrControl:process(TCK) begin if(TCK='1' and TCK'event) then -- Clock(rising edge) ??? if(CurrentTAPState=CaptureDR)then -- Clear LdDataLow <= '0'; LdDataHigh <= '0'; FlashAdrIncrEn <= '0'; elsif(CurrentTAPState=ShiftDR and InstructionRg=C_PROG_PAGELOAD and FlashWr_St='1') then -- Page Load if(VFPCnt=x"7") then LdDataLow <= '1'; else LdDataLow <= '0'; end if; if(VFPCnt=x"F") then LdDataHigh <= '1'; else LdDataHigh <= '0'; end if; if(LdDataHigh='1') then -- !!!TBD!!! FlashAdrIncrEn <= '1'; end if; end if; end if; end process; VFPRdControl:process(TCK) begin if(TCK='1' and TCK'event) then -- Clock(rising edge) if(CurrentTAPState=CaptureDR)then -- Clear FlRdMStart <= '0'; elsif(CurrentTAPState=ShiftDR and InstructionRg=C_PROG_PAGEREAD and FlashRd_St='1') then -- Page Read if(VFPCnt=x"1") then FlRdMStart <= '1'; else FlRdMStart <= '0'; end if; end if; end if; end process; LatchWriteData:process(TCK) begin if(TCK='0' and TCK'event) then -- Clock(falling edge) ??? if(CurrentTAPState=UpdateDR and InstructionRg=C_PROG_COMMANDS and FlashWr_St='1' and PCRSh=C_Prg_2F_2) then LatchWrData <= '1'; else LatchWrData <= '0'; end if; end if; end process; -- EEPROM EEPROMWrRdCtrl:process(TCK) begin if(TCK='1' and TCK'event) then -- Clock(rising edge) ??? if(CurrentTAPState=CaptureDR)then -- Clear EEWrStart_Int <= '0'; elsif(CurrentTAPState=UpdateDR and InstructionRg=C_PROG_COMMANDS and EEPROMWr_St='1' and PCRSh=C_Prg_4E_2) then -- EEPROM Write EEWrStart_Int <= '1'; else EEWrStart_Int <= '0'; end if; if(CurrentTAPState=CaptureDR)then -- Clear EERdStart_Int <= '0'; elsif(CurrentTAPState=UpdateDR and InstructionRg=C_PROG_COMMANDS and EEPROMRd_St='1' and PCRSh(14 downto 8)=C_Prg_5D_1) then -- EEPROM Read ! was C_Prg_5D_2 EERdStart_Int <= '1'; else EERdStart_Int <= '0'; end if; end if; end process; -- Flash single beat operations (Write/Read) FlashSingleWrRdCtrl:process(TCK) begin if(TCK='1' and TCK'event) then -- Clock(rising edge) ??? if(CurrentTAPState=CaptureDR)then FlWrSStart <= '0'; elsif(CurrentTAPState=UpdateDR and InstructionRg=C_PROG_COMMANDS and FlashWr_St='1' and PCRSh=C_Prg_2F_2) then -- Flash write (single) FlWrSStart <= '1'; else FlWrSStart <= '0'; end if; if(CurrentTAPState=CaptureDR)then FlRdSStart <= '0'; elsif(CurrentTAPState=UpdateDR and InstructionRg=C_PROG_COMMANDS and FlashRd_St='1' and PCRSh=C_Prg_3D_1) then -- Flash read (single) FlRdSStart <= '1'; else FlRdSStart <= '0'; end if; end if; end process; -- Address register FlashProgrammerAdrReg:process(TCK) begin if(TCK='0' and TCK'event) then -- Clock(falling edge) like udate reg ??? if(CurrentTAPState=UpdateDR and InstructionRg=C_PROG_COMMANDS) then if(PCRSh(14 downto 8)="0000011") then -- Load Address Low Byte(2c,3c,4c,5c,9b,10b) FlEEPrgAdr_Int(7 downto 0) <= PCRSh(7 downto 0); elsif(PCRSh(14 downto 8)="0000111")then -- Load Address High Byte(2b,3b,4b,5b) FlEEPrgAdr_Int(15 downto 8) <= PCRSh(7 downto 0); end if; elsif(((CurrentTAPState=ShiftDR or CurrentTAPState=Exit1DR)and InstructionRg=C_PROG_PAGELOAD and LdDataHigh='1' and FlashAdrIncrEn='1')or -- Write "Flash" (CurrentTAPState=ShiftDR and InstructionRg=C_PROG_PAGEREAD and FlashRd_St='1' and VFPCnt=x"E")) then -- Read "Flash" -- Increment address counter FlEEPrgAdr_Int(CPageAdrCntLength-1 downto 0)<=FlEEPrgAdr_Int(CPageAdrCntLength-1 downto 0)+1; end if; end if; end process; -- Data register FlashProgrammerDataReg:process(TCK) begin if(TCK='0' and TCK'event) then -- Clock(falling edge) like udate reg ??? if(CurrentTAPState=UpdateDR and InstructionRg=C_PROG_COMMANDS) then if(PCRSh(14 downto 8)="0010011") then -- Load Data Low Byte(2d,4d,6b,6e,6h,7b) FlEEPrgWrData(7 downto 0) <= PCRSh(7 downto 0); elsif(PCRSh(14 downto 8)="0010111") then -- Load Data High Byte(2e) FlEEPrgWrData(15 downto 8) <= PCRSh(7 downto 0); end if; elsif((CurrentTAPState=ShiftDR or CurrentTAPState=Exit1DR)and (InstructionRg=C_PROG_PAGELOAD)) then if(LdDataLow='1') then -- Load Data Low Byte(from the Virtual Flash Page Load Register) FlEEPrgWrData(7 downto 0) <= VFPLSh; elsif(LdDataHigh='1') then -- Load Data High Byte(from the Virtual Flash Page Load Register) FlEEPrgWrData(15 downto 8) <= VFPLSh; end if; end if; end if; end process; -- Programmer State Machines EraseSMRg:process(TCK,TRSTn) begin if(TRSTn='0') then -- Reset (!!!TBD!!!) ChipEraseSM_CurrentState <= ChipEraseSMStIdle; elsif(TCK='1' and TCK'event) then -- Clock(rising edge) if (CurrentTAPState=TestLogicReset) then -- Test-Logic-Reset state ChipEraseSM_CurrentState <= ChipEraseSMStIdle; elsif(CurrentTAPState=UpdateDR and InstructionRg=C_PROG_COMMANDS) then ChipEraseSM_CurrentState <= ChipEraseSM_NextState; end if; end if; end process; -- Programmer State Machines ChipEraseStartDFF:process(TCK,TRSTn) begin if(TRSTn='0') then -- Reset (!!!TBD!!!) ChipEraseStart <= '0'; elsif(TCK='1' and TCK'event) then -- Clock(rising edge) if(CurrentTAPState=UpdateDR and InstructionRg=C_PROG_COMMANDS and PCRSh=C_Prg_1A_1 and ProgEnable_Int='1') then ChipEraseStart <= '1'; else ChipEraseStart <= '0'; end if; end if; end process; EraseSMComb:process(ChipEraseSM_CurrentState,PCRUd,ChipEraseDone,ProgEnable_Int) -- Combinatorial begin case ChipEraseSM_CurrentState is when ChipEraseSMStIdle => if(PCRUd=C_Prg_1A_1 and ProgEnable_Int='1') then ChipEraseSM_NextState <= ChipEraseSMSt1; else ChipEraseSM_NextState <= ChipEraseSMStIdle; end if; when ChipEraseSMSt1 => if(PCRUd=C_Prg_1A_2) then ChipEraseSM_NextState <= ChipEraseSMSt2; else ChipEraseSM_NextState <= ChipEraseSMStIdle; -- Leaving Erase Mode end if; when ChipEraseSMSt2 => if(PCRUd=C_Prg_1A_3) then ChipEraseSM_NextState <= ChipEraseSMSt3; else ChipEraseSM_NextState <= ChipEraseSMStIdle; -- Leaving Erase Mode end if; when ChipEraseSMSt3 => if(ChipEraseDone='1') then ChipEraseSM_NextState <= ChipEraseSMStIdle; else ChipEraseSM_NextState <= ChipEraseSMSt3; end if; when others => ChipEraseSM_NextState <= ChipEraseSMStIdle; end case; end process; ProgSMsRegs:process(TCK,TRSTn) begin if(TRSTn='0') then -- Reset (!!!TBD!!!) FlashWr_St <= '0'; FlashRd_St <= '0'; EEPROMWr_St <= '0'; EEPROMRd_St <= '0'; FuseWr_St <= '0'; LockWr_St <= '0'; FuseLockRd_St <= '0'; SignByteRd_St <= '0'; LoadNOP_St <= '0'; elsif(TCK='1' and TCK'event) then -- Clock(rising edge) if(CurrentTAPState=TestLogicReset)then FlashWr_St <= '0'; FlashRd_St <= '0'; EEPROMWr_St <= '0'; EEPROMRd_St <= '0'; FuseWr_St <= '0'; LockWr_St <= '0'; FuseLockRd_St <= '0'; SignByteRd_St <= '0'; LoadNOP_St <= '0'; elsif(CurrentTAPState=UpdateDR and InstructionRg=C_PROG_COMMANDS) then case FlashWr_St is when '0' => if(PCRUd=C_Prg_2A and ProgEnable_Int='1')then FlashWr_St <= '1'; end if; when '1' => if(PCRUd(14 downto 8)=C_Prg_2A(14 downto 8) and PCRUd(7 downto 0)/=C_Prg_2A(7 downto 0))then FlashWr_St <= '0'; end if; when others => null; end case; case FlashRd_St is when '0' => if(PCRUd=C_Prg_3A and ProgEnable_Int='1')then FlashRd_St <= '1'; end if; when '1' => if(PCRUd(14 downto 8)=C_Prg_3A(14 downto 8) and PCRUd(7 downto 0)/=C_Prg_3A(7 downto 0))then FlashRd_St <= '0'; end if; when others => null; end case; case EEPROMWr_St is when '0' => if(PCRUd=C_Prg_4A and ProgEnable_Int='1')then EEPROMWr_St <= '1'; end if; when '1' => if(PCRUd(14 downto 8)=C_Prg_4A(14 downto 8) and PCRUd(7 downto 0)/=C_Prg_4A(7 downto 0))then EEPROMWr_St <= '0'; end if; when others => null; end case; case EEPROMRd_St is when '0' => if(PCRUd=C_Prg_5A and ProgEnable_Int='1')then EEPROMRd_St <= '1'; end if; when '1' => if(PCRUd(14 downto 8)=C_Prg_5A(14 downto 8) and PCRUd(7 downto 0)/=C_Prg_5A(7 downto 0))then EEPROMRd_St <= '0'; end if; when others => null; end case; case FuseWr_St is when '0' => if(PCRUd=C_Prg_6A and ProgEnable_Int='1')then FuseWr_St <= '1'; end if; when '1' => if(PCRUd(14 downto 8)=C_Prg_6A(14 downto 8) and PCRUd(7 downto 0)/=C_Prg_6A(7 downto 0))then FuseWr_St <= '0'; end if; when others => null; end case; case LockWr_St is when '0' => if(PCRUd=C_Prg_7A and ProgEnable_Int='1')then LockWr_St <= '1'; end if; when '1' => if(PCRUd(14 downto 8)=C_Prg_7A(14 downto 8) and PCRUd(7 downto 0)/=C_Prg_7A(7 downto 0))then LockWr_St <= '0'; end if; when others => null; end case; case FuseLockRd_St is when '0' => if(PCRUd=C_Prg_8A and ProgEnable_Int='1')then FuseLockRd_St <= '1'; end if; when '1' => if(PCRUd(14 downto 8)=C_Prg_8A(14 downto 8) and PCRUd(7 downto 0)/=C_Prg_8A(7 downto 0))then FuseLockRd_St <= '0'; end if; when others => null; end case; case SignByteRd_St is when '0' => if(PCRUd=C_Prg_9A and ProgEnable_Int='1')then SignByteRd_St <= '1'; end if; when '1' => if(PCRUd(14 downto 8)=C_Prg_9A(14 downto 8) and PCRUd(7 downto 0)/=C_Prg_9A(7 downto 0))then SignByteRd_St <= '0'; end if; when others => null; end case; case LoadNOP_St is when '0' => if(PCRUd=C_Prg_11A_1 and ProgEnable_Int='1')then LoadNOP_St <= '1'; end if; when '1' => if(PCRUd(14 downto 8)=C_Prg_11A_1(14 downto 8) and PCRUd(7 downto 0)/=C_Prg_11A_1(7 downto 0))then LoadNOP_St <= '0'; end if; when others => null; end case; end if; end if; end process; TAPResetFlag:process(TCK,TRSTn) begin if(TRSTn='0') then -- Reset (!!!TBD!!!) TAPCtrlTLR <= '1'; elsif(TCK='1' and TCK'event) then -- Clock(rising edge) if((CurrentTAPState=SelectIRScan and TMS='1')or(CurrentTAPState=TestLogicReset and TMS='0'))then TAPCtrlTLR <= '1'; else TAPCtrlTLR <= '0'; end if; end if; end process; -- *************************** End of programmer part ******************************* -- Outputs FlEEPrgAdr <= FlEEPrgAdr_Int; FlWrMStart <= LdDataHigh; ProgEnable <= ProgEnable_Int; end RTL;
apache-2.0
becf8cec502ddfd937c0c3a6e0eae4ed
0.604502
3.131054
false
false
false
false
bertuccio/ARQ
Practica5/ctrl_out.vhd
1
998
---------------------------------------------------------------------------------- -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity ctrl_out is generic(NUM_PERIF: integer:=3); Port ( dir : in STD_LOGIC_VECTOR (31 downto 0); data_write : in STD_LOGIC; perif_en : out STD_LOGIC_VECTOR (NUM_PERIF-1 downto 0)); end ctrl_out; architecture Behavioral of ctrl_out is begin process (data_write,dir) begin if (data_write='1') then if dir <= x"0000FFFF" and dir >= x"00000000" then perif_en<="001"; elsif dir <= x"600000FF" and dir >= x"60000000" then perif_en<="010"; elsif dir <= x"600001FF" and dir >= x"60000100" then perif_en<="100"; else perif_en<="000"; end if; else perif_en<="000"; end if; end process; end Behavioral;
mit
502eb19b1b45b7f8b2de512054ed959b
0.495992
3.417808
false
false
false
false
hoglet67/AtomFpga
src/common/AVR8/uC/RAMDataReg.vhd
4
1,032
--********************************************************************************************** -- RAM data register for the AVR Core -- Version 0.1 -- Modified 02.11.2002 -- Designed by Ruslan Lepetenok --********************************************************************************************** library IEEE; use IEEE.std_logic_1164.all; entity RAMDataReg is port( ireset : in std_logic; cp2 : in std_logic; cpuwait : in std_logic; RAMDataIn : in std_logic_vector(7 downto 0); RAMDataOut : out std_logic_vector(7 downto 0) ); end RAMDataReg; architecture RTL of RAMDataReg is begin RAMDataReg:process(cp2,ireset) begin if ireset='0' then -- Reset RAMDataOut <= (others => '0'); elsif cp2='1' and cp2'event then -- Clock if cpuwait='0' then -- Clock enable RAMDataOut <= RAMDataIn; end if; end if; end process; end RTL;
apache-2.0
deb46b960802ba749386a8c87644769a
0.444767
4.282158
false
false
false
false
hoglet67/AtomFpga
src/common/AVR8/resync/rsnc_bit.vhd
4
1,909
--********************************************************************************************** -- Resynchronizer (for bit) -- Version 0.1 -- Modified 10.01.2007 -- Designed by Ruslan Lepetenok --********************************************************************************************** library IEEE; use IEEE.std_logic_1164.all; entity rsnc_bit is generic( add_stgs_num : integer := 0; inv_f_stgs : integer := 0 ); port( clk : in std_logic; di : in std_logic; do : out std_logic ); end rsnc_bit; architecture rtl of rsnc_bit is type rsnc_vect_type is array(add_stgs_num+1 downto 0) of std_logic; signal rsnc_rg_current : rsnc_vect_type; signal rsnc_rg_next : rsnc_vect_type; begin inverted_first_stg:if (inv_f_stgs/=0) generate seq_f_fe_prc:process(clk) begin if(clk='0' and clk'event) then -- Clock (falling edge) rsnc_rg_current(rsnc_rg_current'low) <= rsnc_rg_next(rsnc_rg_next'low); end if; end process; end generate; norm_first_stg:if (inv_f_stgs=0) generate seq_f_re_prc:process(clk) begin if(clk='1' and clk'event) then -- Clock (rising edge) rsnc_rg_current(rsnc_rg_current'low) <= rsnc_rg_next(rsnc_rg_next'low); end if; end process; end generate; seq_re_prc:process(clk) begin if(clk='1' and clk'event) then -- Clock (rising edge) rsnc_rg_current(rsnc_rg_current'high downto rsnc_rg_current'low+1) <= rsnc_rg_next(rsnc_rg_current'high downto rsnc_rg_current'low+1); end if; end process; comb_prc:process(di,rsnc_rg_current) begin rsnc_rg_next(0) <= di; for i in 1 to rsnc_rg_next'high loop rsnc_rg_next(i) <= rsnc_rg_current(i-1); end loop; end process; do <= rsnc_rg_current(rsnc_rg_current'high); end rtl;
apache-2.0
f710d7576de4e20e316f9ff0a7b8ba9b
0.537978
3.001572
false
false
false
false
hoglet67/AtomFpga
src/common/AVR8/Peripheral/uart.vhd
4
19,648
--********************************************************************************************** -- UART Peripheral for the AVR Core -- Version 1.5 "Original" (Mega103) version -- Modified 14.06.2006 -- Designed by Ruslan Lepetenok -- UDRE bug found -- Transmitter bug (for 9 bit transmission) was found -- Bug in UART_RcDel_St state machine was fixed -- Bug in UART_RcDel_St state machine was fixed(2) (!!!simulation only!!!) --********************************************************************************************** library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use WORK.AVRuCPackage.all; entity uart is port( -- AVR Control ireset : in std_logic; cp2 : in std_logic; adr : in std_logic_vector(15 downto 0); dbus_in : in std_logic_vector(7 downto 0); dbus_out : out std_logic_vector(7 downto 0); iore : in std_logic; iowe : in std_logic; out_en : out std_logic; -- External connection rxd : in std_logic; rx_en : out std_logic; txd : out std_logic; tx_en : out std_logic; -- IRQ txcirq : out std_logic; txc_irqack : in std_logic; udreirq : out std_logic; rxcirq : out std_logic ); end uart; architecture RTL of uart is signal UDR_Tx : std_logic_vector(7 downto 0); signal UDR_Rx : std_logic_vector(7 downto 0); signal UBRR : std_logic_vector(7 downto 0); -- USR Bits signal USR : std_logic_vector(7 downto 0); signal USR_Wr_En : std_logic; alias RXC : std_logic is USR(7); alias TXC : std_logic is USR(6); alias UDRE : std_logic is USR(5); alias FE : std_logic is USR(4); alias DOR : std_logic is USR(3); -- OR in Atmel documents -- UCR Bits signal UCR : std_logic_vector(7 downto 0); signal UCR_Wr_En : std_logic; alias RXCIE : std_logic is UCR(7); alias TXCIE : std_logic is UCR(6); alias UDRIE : std_logic is UCR(5); alias RXEN : std_logic is UCR(4); alias TXEN : std_logic is UCR(3); alias CHR9 : std_logic is UCR(2); alias RXB8 : std_logic is UCR(1); alias TXB8 : std_logic is UCR(0); signal CHR9_Latched : std_logic; signal TXB8_Latched : std_logic; -- Common internal signals signal UART_Clk_En : std_logic; -- Internal signals for transmitter signal SR_Tx : std_logic_vector (7 downto 0); -- UART transmit shift register signal SR_Tx_In : std_logic_vector (7 downto 0); signal Tx_In : std_logic; -- Transmitter state machine signal nUART_Tr_St0 : std_logic; signal UART_Tr_St1 : std_logic; signal UART_Tr_St2 : std_logic; signal UART_Tr_St3 : std_logic; signal UART_Tr_St4 : std_logic; signal UART_Tr_St5 : std_logic; signal UART_Tr_St6 : std_logic; signal UART_Tr_St7 : std_logic; signal UART_Tr_St8 : std_logic; signal UART_Tr_St9 : std_logic; signal UART_Tr_St10 : std_logic; signal UART_Tr_St11 : std_logic; signal Flag_A : std_logic; signal Flag_B : std_logic; signal UDR_Wr_En : std_logic; signal UDR_Rd : std_logic; signal USR_Rd : std_logic; signal UCR_Rd : std_logic; signal UBRR_Rd : std_logic; -- Frequence divider signals signal Div16_Cnt : std_logic_vector (3 downto 0); signal Div16_In : std_logic_vector (Div16_Cnt'range); -- Counter Input signal Div16_Eq : std_logic; -- Combinatorial output of the comparator -- Baud generator signals signal UBRR_Wr_En : std_logic; signal Baud_Gen_Cnt : std_logic_vector (7 downto 0); -- Counter signal Baud_Gen_In : std_logic_vector (Baud_Gen_Cnt'range); -- Counter Input signal Baud_Gen_Eq : std_logic; -- Combinatorial output of the comparator signal Baud_Gen_Out : std_logic; -- Receiver signals signal nUART_RcDel_St0 : std_logic; signal UART_RcDel_St1 : std_logic; signal UART_RcDel_St2 : std_logic; signal UART_RcDel_St3 : std_logic; signal UART_RcDel_St4 : std_logic; signal UART_RcDel_St5 : std_logic; signal UART_RcDel_St6 : std_logic; signal UART_RcDel_St7 : std_logic; signal UART_RcDel_St8 : std_logic; signal UART_RcDel_St9 : std_logic; signal UART_RcDel_St10 : std_logic; signal UART_RcDel_St11 : std_logic; signal UART_RcDel_St12 : std_logic; signal UART_RcDel_St13 : std_logic; signal UART_RcDel_St14 : std_logic; signal UART_RcDel_St15 : std_logic; signal UART_RcDel_St16 : std_logic; signal nUART_Rc_St0 : std_logic; signal UART_Rc_St1 : std_logic; signal UART_Rc_St2 : std_logic; signal UART_Rc_St3 : std_logic; signal UART_Rc_St4 : std_logic; signal UART_Rc_St5 : std_logic; signal UART_Rc_St6 : std_logic; signal UART_Rc_St7 : std_logic; signal UART_Rc_St8 : std_logic; signal UART_Rc_St9 : std_logic; signal UART_Rc_St10 : std_logic; signal RXD_ResyncA : std_logic; signal RXD_ResyncB : std_logic; signal Detector_Out : std_logic; signal Detector_A : std_logic; signal Detector_B : std_logic; signal UART_Rc_SR : std_logic_vector(9 downto 0); signal UART_Rc_SR7_In : std_logic; signal UART_Rc_Delay : std_logic; begin -- Baud generator (First divider) Baud_Generator :process(cp2,ireset) begin if (ireset='0') then -- Reset Baud_Gen_Cnt <= (others => '0'); Baud_Gen_Out <= '0'; elsif (cp2='1' and cp2'event) then -- Clock Baud_Gen_Cnt <= Baud_Gen_In; Baud_Gen_Out <= Baud_Gen_Eq; end if; end process; Baud_Gen_Eq <= '1' when UBRR=Baud_Gen_Cnt else '0'; Baud_Gen_In <= Baud_Gen_Cnt+1 when Baud_Gen_Eq='0' else (others=>'0'); --Divide by 16 (Second divider) Divide_By_16:process(cp2,ireset) begin if (ireset='0') then -- Reset Div16_Cnt <= (others => '0'); -- UART_Clk_En <= '0'; elsif (cp2='1' and cp2'event) then -- Clock if Baud_Gen_Out='1' then -- Clock enable Div16_Cnt <= Div16_In; -- UART_Clk_En <= Div16_Eq; end if; end if; end process; Div16_Eq <= '1' when Div16_Cnt="1111" else '0'; Div16_In <= Div16_Cnt+1 when Div16_Eq='0' else (others=>'0'); Global_Clock_Enable:process(cp2,ireset) begin if (ireset='0') then -- Reset UART_Clk_En <= '0'; elsif (cp2='1' and cp2'event) then -- Clock UART_Clk_En <= Div16_Eq and Baud_Gen_Out; end if; end process; -- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- UBRR UBRR_Wr_En <= '1' when (adr=UBRR_Address and iowe='1') else '0'; -- UBRR write enable UBRR_Load:process(cp2,ireset) begin if ireset='0' then -- Reset UBRR <= ( others => '0'); elsif (cp2='1' and cp2'event) then -- Clock if UBRR_Wr_En='1' then -- Clock enable UBRR <= dbus_in; end if; end if; end process; UDR_Rd <= '1' when (adr=UDR_Address and iore='1') else '0'; -- UDR read enable -- UDR for transmitter UDR_Wr_En <= '1' when (adr=UDR_Address and iowe='1' and TXEN ='1') else '0'; -- UDR write enable UDR_Tx_Load:process(cp2,ireset) begin if (ireset='0') then -- Reset UDR_Tx <= ( others => '0'); CHR9_Latched <= '0'; TXB8_Latched <= '0'; elsif (cp2='1' and cp2'event) then -- Clock if (UDR_Wr_En and (Flag_A or nUART_Tr_St0))='1' then -- Clock enable UDR_Tx <= dbus_in; CHR9_Latched <= CHR9; TXB8_Latched <= TXB8; end if; end if; end process; -- Load flags Load_Flags:process(cp2,ireset) begin if (ireset='0') then -- Reset Flag_A <= '0'; Flag_B <= '0'; elsif (cp2='1' and cp2'event) then -- Clock Flag_A <= (not Flag_A and UDR_Wr_En and not nUART_Tr_St0)or (Flag_A and not (UART_Tr_St1 and UART_Clk_En)); Flag_B <= (not Flag_B and (UDR_Wr_En and (Flag_A or (nUART_Tr_St0 and not(UART_Tr_St11 and UART_Clk_En)))))or (Flag_B and not (UART_Clk_En and UART_Tr_St11)); end if; end process; Transmitter_Shifter:for i in 6 downto 0 generate SR_Tx_In(i) <= (dbus_in(i) and UDR_Wr_En and((not Flag_A and not nUART_Tr_St0)or(not Flag_B and UART_Tr_St11 and UART_Clk_En)))or -- Direct load from data bus (UDR_Tx(i) and UART_Tr_St11 and Flag_B)or -- Load from UDR(TX) (SR_Tx(i+1) and nUART_Tr_St0 and not UART_Tr_St11); -- Shift end generate; SR_Tx_In(7) <= (dbus_in(7) and UDR_Wr_En and((not Flag_A and not nUART_Tr_St0)or(not Flag_B and UART_Tr_St11 and UART_Clk_En)))or -- Direct load from data bus (UDR_Tx(7) and UART_Tr_St11 and Flag_B)or -- Load from UDR(TX) (TXB8_Latched and (UART_Tr_St2 and CHR9_Latched))or -- Shift first ('1' and not((not Flag_A and not nUART_Tr_St0 and UDR_Wr_En)or UART_Tr_St11 or(UART_Tr_St2 and CHR9_Latched))); -- All other cases TX_In <= ('0' and UART_Tr_St1)or -- Start bit (SR_Tx(0) and (nUART_Tr_St0 and not UART_Tr_St1))or -- Shift ('1' and not nUART_Tr_St0); -- Idle -- Transmitter shift register SR_Tx_Load_Sift:process(cp2,ireset) begin if (ireset='0') then -- Reset SR_Tx <= ( others => '0'); elsif (cp2='1' and cp2'event) then -- Clock if ((not Flag_A and not nUART_Tr_St0 and UDR_Wr_En)or(UART_Tr_St11 and UART_Clk_En)or (nUART_Tr_St0 and UART_Clk_En and not UART_Tr_St1))='1' then -- Clock enable SR_Tx <= SR_Tx_In; end if; end if; end process; -- Transmitter output register Tx_Out:process(cp2,ireset) begin if (ireset='0') then -- Reset txd <= '1'; elsif (cp2='1' and cp2'event) then -- Clock if (UART_Clk_En and (nUART_Tr_St0 or Flag_A))='1' then -- Clock enable txd <= TX_In; end if; end if; end process; Transmit_State_Machine:process(cp2,ireset) begin if (ireset='0') then -- Reset nUART_Tr_St0 <='0'; UART_Tr_St1 <='0'; UART_Tr_St2 <='0'; UART_Tr_St3 <='0'; UART_Tr_St4 <='0'; UART_Tr_St5 <='0'; UART_Tr_St6 <='0'; UART_Tr_St7 <='0'; UART_Tr_St8 <='0'; UART_Tr_St9 <='0'; UART_Tr_St10 <='0'; UART_Tr_St11 <='0'; elsif (cp2='1' and cp2'event) then -- Clock if (UART_Clk_En = '1') then -- Clock enable nUART_Tr_St0 <= (not nUART_Tr_St0 and Flag_A) or (nUART_Tr_St0 and not(UART_Tr_St11 and not Flag_B and not UDR_Wr_En)); UART_Tr_St1 <= not UART_Tr_St1 and ((not nUART_Tr_St0 and Flag_A)or(UART_Tr_St11 and (Flag_B or UDR_Wr_En))); -- Start bit UART_Tr_St2 <= UART_Tr_St1; -- Bit 0 UART_Tr_St3 <= UART_Tr_St2; -- Bit 1 UART_Tr_St4 <= UART_Tr_St3; -- Bit 2 UART_Tr_St5 <= UART_Tr_St4; -- Bit 3 UART_Tr_St6 <= UART_Tr_St5; -- Bit 4 UART_Tr_St7 <= UART_Tr_St6; -- Bit 5 UART_Tr_St8 <= UART_Tr_St7; -- Bit 6 UART_Tr_St9 <= UART_Tr_St8; -- Bit 7 UART_Tr_St10 <= UART_Tr_St9 and CHR9_Latched; -- Bit 8 (if enabled) UART_Tr_St11 <= (UART_Tr_St9 and not CHR9_Latched) or UART_Tr_St10; -- Stop bit end if; end if; end process; -- USR bits USR_UDRE:process(cp2,ireset) begin if (ireset='0') then -- Reset UDRE <= '1'; -- !! elsif (cp2='1' and cp2'event) then -- Clock UDRE <= (UDRE and not(UDR_Wr_En and (Flag_A or (nUART_Tr_St0 and not(UART_Tr_St11 and UART_Clk_En))))) or (not UDRE and (UART_Tr_St11 and Flag_B and UART_Clk_En)); end if; end process; USR_Wr_En <= '1' when (adr=USR_Address and iowe='1') else '0'; USR_TXC:process(cp2,ireset) begin if (ireset='0') then -- Reset TXC <= '0'; elsif (cp2='1' and cp2'event) then -- Clock TXC <= (not TXC and(UART_Tr_St11 and not Flag_B and UART_Clk_En and not UDR_Wr_En))or -- TXC set ??? (TXC and not(UDR_Wr_En or txc_irqack or (USR_Wr_En and dbus_in(6)))); -- TXC reset end if; end process; -- Transmitter IRQ txcirq <= TXC and TXCIE; udreirq <= UDRE and UDRIE; -- Output enable signal(for external multiplexer control) out_en <= '1' when ((adr=UDR_Address or adr=UBRR_Address or adr=USR_Address or adr=UCR_Address) and iore='1') else '0'; UCR_Wr_En <= '1' when (adr=UCR_Address and iowe='1') else '0'; UCR_Bits:process(cp2,ireset) begin if ireset='0' then -- Reset UCR(7 downto 2) <= (others => '0'); UCR(0) <= '0'; elsif (cp2='1' and cp2'event) then -- Clock if UCR_Wr_En='1' then -- Clock enable UCR(7 downto 2) <= dbus_in(7 downto 2); UCR(0) <= dbus_in(0); end if; end if; end process; --*********************************** Receiver ************************************** Receiver:process(cp2,ireset) begin if ireset='0' then -- Reset nUART_RcDel_St0 <='0'; UART_RcDel_St1 <='0'; UART_RcDel_St2 <='0'; UART_RcDel_St3 <='0'; UART_RcDel_St4 <='0'; UART_RcDel_St5 <='0'; UART_RcDel_St6 <='0'; UART_RcDel_St7 <='0'; UART_RcDel_St8 <='0'; UART_RcDel_St9 <='0'; UART_RcDel_St10 <='0'; UART_RcDel_St11 <='0'; UART_RcDel_St12 <='0'; UART_RcDel_St13 <='0'; UART_RcDel_St14 <='0'; UART_RcDel_St15 <='0'; UART_RcDel_St16 <='0'; elsif (cp2='1' and cp2'event) then -- Clock if Baud_Gen_Out='1' then -- Clock enable nUART_RcDel_St0 <= (not nUART_RcDel_St0 and not RXD_ResyncB)or -- Was :(nUART_RcDel_St0 and not((UART_RcDel_St10 and(Detector_Out and not nUART_Rc_St0))or -- Noise instead of start bit (nUART_RcDel_St0 and not((UART_RcDel_St9 and(Detector_Out and not nUART_Rc_St0))or -- Noise instead of start bit (UART_RcDel_St9 and UART_Rc_St10)or -- Stop bit was detected (UART_RcDel_St16 and not nUART_Rc_St0))); -- ?bug? UART_RcDel_St1 <= not UART_RcDel_St1 and((not nUART_RcDel_St0 and not RXD_ResyncB)or(UART_RcDel_St16 and nUART_Rc_St0)); UART_RcDel_St2 <= UART_RcDel_St1; UART_RcDel_St3 <= UART_RcDel_St2; UART_RcDel_St4 <= UART_RcDel_St3; UART_RcDel_St5 <= UART_RcDel_St4; UART_RcDel_St6 <= UART_RcDel_St5; UART_RcDel_St7 <= UART_RcDel_St6; UART_RcDel_St8 <= UART_RcDel_St7; UART_RcDel_St9 <= UART_RcDel_St8; UART_RcDel_St10 <= not UART_RcDel_St10 and UART_RcDel_St9 and ((not Detector_Out and not nUART_Rc_St0)or(nUART_Rc_St0 and not UART_Rc_St10)); UART_RcDel_St11 <= UART_RcDel_St10; UART_RcDel_St12 <= UART_RcDel_St11; UART_RcDel_St13 <= UART_RcDel_St12; UART_RcDel_St14 <= UART_RcDel_St13; UART_RcDel_St15 <= UART_RcDel_St14; UART_RcDel_St16 <= UART_RcDel_St15; end if; end if; end process; UART_Rc_SR7_In <= UART_Rc_SR(8) when CHR9='1' else UART_Rc_SR(9); Receiver_Shift:process(cp2,ireset) begin if ireset='0' then -- Reset nUART_Rc_St0 <='0'; UART_Rc_St1 <='0'; UART_Rc_St2 <='0'; UART_Rc_St3 <='0'; UART_Rc_St4 <='0'; UART_Rc_St5 <='0'; UART_Rc_St6 <='0'; UART_Rc_St7 <='0'; UART_Rc_St8 <='0'; UART_Rc_St9 <='0'; UART_Rc_St10 <='0'; UART_Rc_SR <= (others => '0'); elsif (cp2='1' and cp2'event) then -- Clock if (Baud_Gen_Out and UART_RcDel_St9)='1' then -- Clock enable nUART_Rc_St0 <= (not nUART_Rc_St0 and not RXD_ResyncB)or (nUART_Rc_St0 and not UART_Rc_St10); UART_Rc_St1 <= not UART_Rc_St1 and (not nUART_Rc_St0 and not RXD_ResyncB); -- D0 UART_Rc_St2 <= UART_Rc_St1; -- D1 UART_Rc_St3 <= UART_Rc_St2; -- D2 UART_Rc_St4 <= UART_Rc_St3; -- D3 UART_Rc_St5 <= UART_Rc_St4; -- D4 UART_Rc_St6 <= UART_Rc_St5; -- D5 UART_Rc_St7 <= UART_Rc_St6; -- D6 UART_Rc_St8 <= UART_Rc_St7; -- D7 UART_Rc_St9 <= UART_Rc_St8 and CHR9; -- D8 UART_Rc_St10 <= (UART_Rc_St8 and not CHR9) or UART_Rc_St9; -- Stop bit UART_Rc_SR(6 downto 0) <= UART_Rc_SR(7 downto 1); UART_Rc_SR(7) <= UART_Rc_SR7_In; UART_Rc_SR(8) <= UART_Rc_SR(9); UART_Rc_SR(9) <= Detector_Out; end if; end if; end process; RXD_Resinc:process(cp2,ireset) begin if ireset='0' then -- Reset RXD_ResyncA <= '1'; RXD_ResyncB <= '1'; elsif (cp2='1' and cp2'event) then -- Clock RXD_ResyncA <= rxd; RXD_ResyncB <= RXD_ResyncA; end if; end process; Receiver_Detect_A:process(cp2,ireset) begin if ireset='0' then -- Reset Detector_A <= '0'; elsif (cp2='1' and cp2'event) then -- Clock if (Baud_Gen_Out and UART_RcDel_St7)='1' then -- Clock enable Detector_A <= RXD_ResyncB; end if; end if; end process; Receiver_Detect_B:process(cp2,ireset) begin if ireset='0' then -- Reset Detector_B <= '0'; elsif (cp2='1' and cp2'event) then -- Clock if (Baud_Gen_Out and UART_RcDel_St8)='1' then -- Clock enable Detector_B <= RXD_ResyncB; end if; end if; end process; Detector_Out <= (Detector_A and Detector_B)or(Detector_B and RXD_ResyncB)or(Detector_A and RXD_ResyncB); UDR_Rx_Reg:process(cp2,ireset) begin if ireset='0' then -- Reset UDR_Rx <= (others => '0'); FE <= '0'; -- Framing error elsif (cp2='1' and cp2'event) then -- Clock if (UART_Rc_Delay and RXEN and not RXC)='1' then -- Clock enable ??? TBD UDR_Rx <= UART_Rc_SR(7 downto 0); FE <= not UART_Rc_SR(9); -- Framing error end if; end if; end process; UCR_RXB8:process(cp2,ireset) begin if ireset='0' then -- Reset RXB8 <= '1'; -- ??? Check the papers again elsif (cp2='1' and cp2'event) then -- Clock if (UART_Rc_Delay and RXEN and not RXC and CHR9)='1' then -- Clock enable ??? TBD RXB8 <= UART_Rc_SR(8); -- RXB8 end if; end if; end process; USR_Bits:process(cp2,ireset) begin if ireset='0' then -- Reset RXC <= '0'; DOR <= '0'; UART_Rc_Delay <='0'; elsif (cp2='1' and cp2'event) then -- Clock RXC <= (not RXC and (UART_Rc_Delay and RXEN))or(RXC and not UDR_Rd); DOR <= (not DOR and (UART_Rc_Delay and RXEN and RXC))or (DOR and not (UART_Rc_Delay and RXEN and not RXC)); UART_Rc_Delay <= not UART_Rc_Delay and (Baud_Gen_Out and UART_Rc_St10 and UART_RcDel_St9); end if; end process; -- Reserved USR bits USR(2 downto 0) <= (others => '0'); USR_Rd <= '1' when (adr=USR_Address and iore='1') else '0'; UCR_Rd <= '1' when (adr=UCR_Address and iore='1') else '0'; UBRR_Rd <= '1' when (adr=UBRR_Address and iore='1') else '0'; -- Output multiplexer Out_Mux: for i in dbus_out'range generate dbus_out(i) <= (UDR_Rx(i) and UDR_Rd)or (USR(i) and USR_Rd)or (UCR(i) and UCR_Rd)or (UBRR(i) and UBRR_Rd); end generate; -- Reciever IRQ rxcirq <= RXC and RXCIE; -- External lines rx_en <= RXEN; tx_en <= TXEN; end RTL;
apache-2.0
0e7054cb20845835ed9a15a09b9a3e39
0.554611
2.766155
false
false
false
false
hoglet67/AtomFpga
src/common/AVR8/Memory/XPM_Xilinx.vhd
1
1,680
library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; -- For f_log2 definition use WORK.SynthCtrlPack.all; library unisim; use unisim.vcomponents.all; entity XPM is generic ( WIDTH : integer; SIZE : integer; FILENAME : string -- ignored ); port( cp2 : in std_logic; ce : in std_logic; address : in std_logic_vector(f_log2(SIZE) - 1 downto 0); din : in std_logic_vector(WIDTH - 1 downto 0); dout : out std_logic_vector(WIDTH - 1 downto 0); we : in std_logic ); end; architecture RTL of XPM is -- number of bits in the RAMB16_S18 constant ramb16_size : integer := 16384; -- determine shape of memory constant block_size : integer := ramb16_size / WIDTH; constant block_bits : integer := f_log2(block_size); constant num_blocks : integer := (SIZE + block_size - 1) / block_size; type RAMBlDOut_Type is array(0 to num_blocks - 1) of std_logic_vector(dout'range); signal RAMBlDOut : RAMBlDOut_Type; begin RAM_Inst:for i in 0 to num_blocks - 1 generate Ram : RAMB16_S18 generic map ( INIT => X"00000", -- Value of output RAM registers at startup SRVAL => X"00000", -- Ouput value upon SSR assertion WRITE_MODE => "WRITE_FIRST" -- WRITE_FIRST, READ_FIRST or NO_CHANGE ) port map( DO => RAMBlDOut(i), ADDR => address(block_bits - 1 downto 0), DI => din, DIP => "11", EN => ce, SSR => '0', CLK => cp2, WE => '0' ); end generate; dout <= RAMBlDOut(CONV_INTEGER(address(address'high downto block_bits))); end RTL;
apache-2.0
28ae3d41435da021f2dd06d53f618470
0.595238
3.313609
false
false
false
false
abyrne55/my-little-processor
ram_16bit.vhd
1
2,215
LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_signed.ALL; USE ieee.numeric_std.ALL; -- Synchronous RAM ENTITY ram_16bit IS GENERIC (S, N : INTEGER := 16); PORT ( clock : IN STD_LOGIC; done : IN STD_LOGIC; data : IN STD_LOGIC_VECTOR (15 DOWNTO 0); write_addr : IN STD_LOGIC_VECTOR (N - 1 DOWNTO 0); read_addr : IN STD_LOGIC_VECTOR (N - 1 DOWNTO 0); write_enable : IN STD_LOGIC; q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0) ); END; ARCHITECTURE behavioural OF ram_16bit IS TYPE mem IS ARRAY (15 DOWNTO 0) OF STD_LOGIC_VECTOR(15 DOWNTO 0); FUNCTION initialize_ram RETURN mem IS VARIABLE result : mem; BEGIN -- THIS IS WHERE YOU WRITE THE INSTRUCTIONS -- result(0) := "0000000000000000"; --LOAD R0 result(1) := "1111000011110000"; --Data result(2) := "0000000100000000"; --LOAD R1 result(3) := "0001101100001100"; --Data result(4) := "0110000100000000"; --MOV R0 to R1 result(5) := "0000000100000000"; --LOAD R1 result(6) := "0000000000000000"; --Data result(7) := "0100000000000000"; --Load PC into R0 result(8) := "0101000100000000"; -- Load PC from R1 --result(4) := "0100000000000000"; -- Load PC into R0 --result(4) := "0010000100000000"; --Add, store in R0 --result(5) := "0000000100000000"; --LOAD R1 --result(6) := "0000000010001000"; --Data --result(7) := "0010000000010000"; --Add R0 + R1, store in R0 --result(8) := "0010000100000000"; --Add R0 + R1, store in R1 --result(5) := "0011000000010000"; --XOR R0, R1, store in R0 --result(10) := "0011000100000000"; --XOR R0, R1, store in R1 --result(11) := "0000000000000000"; --LOAD R0 --result(12) := "0000000000000000"; --Data --result(13) := "0000000000000000"; --LOAD R0 --result(14) := "0001100000000001"; --Data --result(15) := "0001000100000000"; --MOV R0 to R1 RETURN (result); END initialize_ram; SIGNAL raMem : mem := initialize_ram; BEGIN PROCESS (clock, done) BEGIN IF (rising_edge(clock) AND done = '1') THEN -- IF (write_enable = '1') THEN -- raMem(to_integer(unsigned(write_addr))) <= data; -- END IF; q <= raMem(to_integer(unsigned(read_addr))); END IF; END PROCESS; END behavioural;
mit
e7035a0b36b29538f0862326253af5c6
0.634763
3.050964
false
false
false
false
msiddalingaiah/TTA
VHDL/ControlUnit.vhd
1
7,311
-------------------------------------------------------------------------------- -- Copyright 2014 Madhu Siddalingaiah -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -- Entity: ControlUnit -- Date: 2014-10-31 -- Author: Madhu -- -- Description: -------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; -- Avoid using ieee.std_logic_arith.all use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; entity ControlUnit is generic ( DATA_WIDTH : integer := 16; PM_DEPTH : natural := 16 ); port ( reset : in std_logic; clock : in std_logic; load_enable : in std_logic; run_enable : in std_logic; pm_data_in : in std_logic_vector ( 16 - 1 downto 0 ); halt_flag : out std_logic ); end ControlUnit; -- f ddddddd ssssssss -- 1 module module -- 0 module immediate -- module 0 - prefix architecture arch of ControlUnit is component ProgramMemory generic ( DATA_WIDTH : integer; ADDRESS_WIDTH : integer; DEPTH : natural ); port ( reset : in std_logic; clock : in std_logic; data_in : in std_logic_vector(DATA_WIDTH-1 downto 0); pc_in : in std_logic_vector(ADDRESS_WIDTH-1 downto 0); data_out : out std_logic_vector(DATA_WIDTH-1 downto 0); pc_out : out std_logic_vector(ADDRESS_WIDTH-1 downto 0); memory_write : in std_logic; pc_write : in std_logic ); end component; component ArithmeticUnit generic ( DATA_WIDTH : integer; ADDRESS_WIDTH : integer; DEPTH : natural ); port ( reset : in std_logic; clock : in std_logic; address : in std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 ); data_in : in std_logic_vector ( DATA_WIDTH - 1 downto 0 ); data_out : out std_logic_vector ( DATA_WIDTH - 1 downto 0 ); read_enable : in std_logic; write_enable : in std_logic; busy : out std_logic ); end component; constant SUBSYSTEM_WIDTH : integer := 3; constant DEST_BASE : integer := 8; constant UNIT_WIDTH : integer := 4; constant IMM_BIT : integer := DEST_BASE+3; constant SHORT_IMM_BIT : integer := DEST_BASE-1; constant SHORT_IMM_WIDTH : integer := SHORT_IMM_BIT-1; constant UNIT_PM : integer := 1; constant UNIT_ARITH : integer := 2; constant NUM_UNITS : integer := 16; type DataBusArray is array (NUM_UNITS-1 downto 0) of std_logic_vector(DATA_WIDTH-1 downto 0); type AddrBusArray is array (NUM_UNITS-1 downto 0) of std_logic_vector(SUBSYSTEM_WIDTH-1 downto 0); signal data_in, data_out : DataBusArray; signal address : AddrBusArray; signal read_enable, write_enable, busy : std_logic_vector(0 to NUM_UNITS-1); signal instruction, code_data_out : std_logic_vector(DATA_WIDTH-1 downto 0); signal l_reset, l_clock, code_read_enable : std_logic; begin au : ArithmeticUnit generic map( DATA_WIDTH => DATA_WIDTH, ADDRESS_WIDTH => SUBSYSTEM_WIDTH, DEPTH => 32 ) port map( reset => l_reset, clock => l_clock, address => address(UNIT_ARITH), data_in => data_in(UNIT_ARITH), data_out => data_out(UNIT_ARITH), read_enable => read_enable(UNIT_ARITH), write_enable => write_enable(UNIT_ARITH), busy => busy(UNIT_ARITH) ); statemachine: block type state_type is (LOAD, PREFETCH, EXEC, HALT); signal state : state_type := LOAD; signal dest_sub_system, src_sub_system : std_logic_vector( SUBSYSTEM_WIDTH - 1 downto 0 ); signal short_immediate : std_logic_vector( SHORT_IMM_WIDTH - 1 downto 0 ); signal imm_flag, long_imm_flag : std_logic; begin l_reset <= reset; l_clock <= clock; imm_flag <= instruction(IMM_BIT); long_imm_flag <= instruction(SHORT_IMM_BIT); short_immediate <= instruction(SHORT_IMM_WIDTH - 1 downto 0); dest_sub_system <= instruction(IMM_BIT - 1 downto DEST_BASE); src_sub_system <= instruction(SUBSYSTEM_WIDTH - 1 downto 0); process(clock, reset) variable dest_unit, src_unit : integer; begin if reset = '1' then state <= LOAD; halt_flag <= '0'; code_read_enable <= '0'; read_enable <= (others => '0'); write_enable <= (others => '0'); elsif rising_edge(clock) then read_enable <= (others => '0'); write_enable <= (others => '0'); case state is when LOAD => if load_enable = '0' and run_enable = '1' then state <= PREFETCH; elsif load_enable = '1' then address(UNIT_PM) <= std_logic_vector(to_unsigned(1, address(UNIT_PM)'length)); data_in(UNIT_PM) <= pm_data_in; write_enable(UNIT_PM) <= '1'; end if; when PREFETCH => state <= EXEC; code_read_enable <= '1'; when EXEC => if to_integer(unsigned(instruction(DATA_WIDTH - 1 downto 0))) = 1 then state <= HALT; else state <= EXEC; src_unit := to_integer(unsigned(instruction(DEST_BASE - 1 downto UNIT_WIDTH))); dest_unit := to_integer(unsigned(instruction(DATA_WIDTH - 1 downto IMM_BIT+1))); address(dest_unit) <= dest_sub_system; if imm_flag = '1' then if long_imm_flag = '0' then data_in(dest_unit) <= std_logic_vector(resize(signed(short_immediate), data_in(dest_unit)'length)); else address(UNIT_PM) <= std_logic_vector(to_unsigned(1, address(UNIT_PM)'length)); read_enable(UNIT_PM) <= '1'; data_in(dest_unit) <= data_out(UNIT_PM); end if; else address(src_unit) <= src_sub_system; read_enable(src_unit) <= '1'; data_in(dest_unit) <= data_out(src_unit); end if; write_enable(dest_unit) <= '1'; end if; when HALT => halt_flag <= '1'; when others => state <= HALT; end case; end if; end process; end block; end arch;
apache-2.0
2a865ba937c8e01fdd6e607fe6298686
0.529886
4.014827
false
false
false
false
GSimas/EEL5105
Multiplicador_Quartus/controle.vhd
1
1,858
library ieee; use ieee.std_logic_1164.all; entity controle is port ( clk : in std_logic; reset : in std_logic; -- Entradas e saídas de controle s : in std_logic; b : out std_logic; -- comando e status ZR,LR,Sub,ZS,LS,ZN,EN : out std_logic; Nm : in std_logic ); end entity; architecture ctrl1 of controle is type ESTADOS is (Inicio, EsperaStart, RealizaSomas, MostraRes); signal EA,PE : ESTADOS; begin process(reset,clk) begin if reset = '1' then EA <= Inicio; elsif rising_edge(clk) then EA <= PE; end if; end process; process (EA,s,Nm) begin case EA is when Inicio => PE <= EsperaStart; ZR <= '0'; b <= '0'; LR <= '0'; Sub <= '0'; ZS <= '0'; LS <= '0'; ZN <= '0'; EN <= '0'; when EsperaStart => if (s = '0') then PE <= EsperaStart; else PE <= RealizaSomas; end if; ZN <= '1'; ZS <= '1'; b <= '0'; ZR <= '0'; LR <= '0'; Sub <= '0'; LS <= '0'; EN <= '0'; when RealizaSomas => if (Nm = '1') then PE <= RealizaSomas; else PE <= MostraRes; end if; Sub <= '0'; LS <= '1'; EN <= '1'; b <= '1'; ZR <= '0'; LR <= '0'; ZN <= '0'; ZS <= '0'; when MostraRes => PE <= EsperaStart; Sub <= '1'; LR <= '1'; b <= '0'; ZR <= '0'; LS <= '0'; EN <= '0'; ZN <= '0'; ZS <= '0'; end case; end process; end ctrl1;
mit
5d3292e0be8df2397604617db6f412b0
0.369413
3.376364
false
false
false
false
tghaefli/ADD
ISE/FMC_waj/bus.vhd
1
5,141
------------------------------------------------------------------------------- -- Entity: ram -- Author: Waj ------------------------------------------------------------------------------- -- Description: (ECS Uebung 9) -- Data/address/control bus for simple von-Neumann MCU. -- The bus master (CPU) can read/write in every cycle. The bus slaves are -- assumed to have registerd read data output with an address-in to data-out -- latency of 1 cc. The read data muxing from bus slaves to the bus master is -- done combinationally. Thus, at the bus master interface, there results a -- read data latency of 1 cc. ------------------------------------------------------------------------------- -- Note on code portability: ------------------------------------------------------------------------------- -- The address decoding logic as implemented in process P_dec below, shows how -- to write portable code by means of a user-defined enumaration type which is -- used as the index range for a constant array, see mcu_pkg. This allows to -- leave the local code (in process P_dec) unchanged when the number and/or -- base addresses of the bus slaves in the system change. Such changes then -- need only to be made in the global definition package. -- To generate such portable code for the rest of the functionality (e.g. for -- the read data mux) would require to organize all data input vectors in a -- signal array first. This would destroy the portability of the code, since it -- requires manual code adaption when design parameter change. ------------------------------------------------------------------------------- -- Total # of FFs: 3 ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.mcu_pkg.all; entity buss is port(rst : in std_logic; clk : in std_logic; -- CPU bus signals cpu_in : in t_cpu2bus; cpu_out : out t_bus2cpu; -- ROM bus signals rom_in : in t_ros2bus; rom_out : out t_bus2ros; -- RAM bus signals ram_in : in t_rws2bus; ram_out : out t_bus2rws; -- GPIO bus signals gpio_in : in t_rws2bus; gpio_out : out t_bus2rws; -- FMC bus signals fmc_in : in t_rws2bus; fmc_out : out t_bus2rws ); end buss; architecture rtl of buss is -- currently addressed bus slave signal bus_slave, bus_slave_reg : t_bus_slave; begin ----------------------------------------------------------------------------- -- address decoding ----------------------------------------------------------------------------- -- convey lower address bist from CPU to all bus slaves rom_out.addr <= cpu_in.addr(AWL-1 downto 0); ram_out.addr <= cpu_in.addr(AWL-1 downto 0); gpio_out.addr <= cpu_in.addr(AWL-1 downto 0); fmc_out.addr <= cpu_in.addr(AWL-1 downto 0); -- combinational process: -- determine addressed slave by decoding higher address bits ----------------------------------------------------------------------------- P_dec: process(cpu_in) begin bus_slave <= ROM; -- default assignment for k in t_bus_slave loop if cpu_in.addr(AW-1 downto AW-AWH) = HBA(k) then bus_slave <= k; end if; end loop; end process; ----------------------------------------------------------------------------- -- write transfer logic ----------------------------------------------------------------------------- -- convey write data from CPU to all bus slaves -- rom is read-only slave ram_out.data <= cpu_in.data; gpio_out.data <= cpu_in.data; fmc_out.data <= cpu_in.data; -- convey write enable from CPU to addressed slave only ram_out.wr_enb <= cpu_in.wr_enb when bus_slave = RAM else '0'; gpio_out.wr_enb <= cpu_in.wr_enb when bus_slave = GPIO else '0'; fmc_out.wr_enb <= cpu_in.wr_enb when bus_slave = FMC else '0'; ----------------------------------------------------------------------------- -- read transfer logic ----------------------------------------------------------------------------- -- read data mux with bus_slave_reg select cpu_out.data <= rom_in.data when ROM, ram_in.data when RAM, gpio_in.data when GPIO, fmc_in.data when FMC, (others => '-') when others; -- convey read enable from CPU to addressed slave only ram_out.rd_enb <= cpu_in.rd_enb when bus_slave = RAM else '0'; gpio_out.rd_enb <= cpu_in.rd_enb when bus_slave = GPIO else '0'; fmc_out.rd_enb <= cpu_in.rd_enb when bus_slave = FMC else '0'; -- sequential process: -- register decode information to compensate read-latency of slaves ----------------------------------------------------------------------------- P_reg: process(rst, clk) begin if rst = '1' then bus_slave_reg <= ROM; elsif rising_edge(clk) then bus_slave_reg <= bus_slave; end if; end process; end rtl;
gpl-3.0
d6b50e53f350bdebf07187cf3f8dd27a
0.494067
4.375319
false
false
false
false
fquinto/Wireless_sensor_network
Avnet_UPC/hdl/xps_intc_0_wrapper.vhd
1
7,085
------------------------------------------------------------------------------- -- xps_intc_0_wrapper.vhd ------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; library xps_intc_v2_01_a; use xps_intc_v2_01_a.all; entity xps_intc_0_wrapper is port ( SPLB_Clk : in std_logic; SPLB_Rst : in std_logic; PLB_ABus : in std_logic_vector(0 to 31); PLB_PAValid : in std_logic; PLB_masterID : in std_logic_vector(0 to 0); PLB_RNW : in std_logic; PLB_BE : in std_logic_vector(0 to 3); PLB_size : in std_logic_vector(0 to 3); PLB_type : in std_logic_vector(0 to 2); PLB_wrDBus : in std_logic_vector(0 to 31); PLB_UABus : in std_logic_vector(0 to 31); PLB_SAValid : in std_logic; PLB_rdPrim : in std_logic; PLB_wrPrim : in std_logic; PLB_abort : in std_logic; PLB_busLock : in std_logic; PLB_MSize : in std_logic_vector(0 to 1); PLB_lockErr : in std_logic; PLB_wrBurst : in std_logic; PLB_rdBurst : in std_logic; PLB_wrPendReq : in std_logic; PLB_rdPendReq : in std_logic; PLB_wrPendPri : in std_logic_vector(0 to 1); PLB_rdPendPri : in std_logic_vector(0 to 1); PLB_reqPri : in std_logic_vector(0 to 1); PLB_TAttribute : in std_logic_vector(0 to 15); Sl_addrAck : out std_logic; Sl_SSize : out std_logic_vector(0 to 1); Sl_wait : out std_logic; Sl_rearbitrate : out std_logic; Sl_wrDAck : out std_logic; Sl_wrComp : out std_logic; Sl_rdDBus : out std_logic_vector(0 to 31); Sl_rdDAck : out std_logic; Sl_rdComp : out std_logic; Sl_MBusy : out std_logic_vector(0 to 1); Sl_MWrErr : out std_logic_vector(0 to 1); Sl_MRdErr : out std_logic_vector(0 to 1); Sl_wrBTerm : out std_logic; Sl_rdWdAddr : out std_logic_vector(0 to 3); Sl_rdBTerm : out std_logic; Sl_MIRQ : out std_logic_vector(0 to 1); Intr : in std_logic_vector(3 downto 0); Irq : out std_logic ); attribute x_core_info : STRING; attribute x_core_info of xps_intc_0_wrapper : entity is "xps_intc_v2_01_a"; end xps_intc_0_wrapper; architecture STRUCTURE of xps_intc_0_wrapper is component xps_intc is generic ( C_FAMILY : STRING; C_BASEADDR : std_logic_vector(0 to 31); C_HIGHADDR : std_logic_vector(0 to 31); C_SPLB_AWIDTH : INTEGER; C_SPLB_DWIDTH : INTEGER; C_SPLB_P2P : INTEGER; C_SPLB_NUM_MASTERS : INTEGER; C_SPLB_MID_WIDTH : INTEGER; C_SPLB_NATIVE_DWIDTH : INTEGER; C_SPLB_SUPPORT_BURSTS : INTEGER; C_NUM_INTR_INPUTS : INTEGER; C_KIND_OF_INTR : std_logic_vector(31 downto 0); C_KIND_OF_EDGE : std_logic_vector(31 downto 0); C_KIND_OF_LVL : std_logic_vector(31 downto 0); C_HAS_IPR : INTEGER; C_HAS_SIE : INTEGER; C_HAS_CIE : INTEGER; C_HAS_IVR : INTEGER; C_IRQ_IS_LEVEL : INTEGER; C_IRQ_ACTIVE : std_logic ); port ( SPLB_Clk : in std_logic; SPLB_Rst : in std_logic; PLB_ABus : in std_logic_vector(0 to 31); PLB_PAValid : in std_logic; PLB_masterID : in std_logic_vector(0 to (C_SPLB_MID_WIDTH-1)); PLB_RNW : in std_logic; PLB_BE : in std_logic_vector(0 to ((C_SPLB_DWIDTH/8)-1)); PLB_size : in std_logic_vector(0 to 3); PLB_type : in std_logic_vector(0 to 2); PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_DWIDTH-1)); PLB_UABus : in std_logic_vector(0 to 31); PLB_SAValid : in std_logic; PLB_rdPrim : in std_logic; PLB_wrPrim : in std_logic; PLB_abort : in std_logic; PLB_busLock : in std_logic; PLB_MSize : in std_logic_vector(0 to 1); PLB_lockErr : in std_logic; PLB_wrBurst : in std_logic; PLB_rdBurst : in std_logic; PLB_wrPendReq : in std_logic; PLB_rdPendReq : in std_logic; PLB_wrPendPri : in std_logic_vector(0 to 1); PLB_rdPendPri : in std_logic_vector(0 to 1); PLB_reqPri : in std_logic_vector(0 to 1); PLB_TAttribute : in std_logic_vector(0 to 15); Sl_addrAck : out std_logic; Sl_SSize : out std_logic_vector(0 to 1); Sl_wait : out std_logic; Sl_rearbitrate : out std_logic; Sl_wrDAck : out std_logic; Sl_wrComp : out std_logic; Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_DWIDTH-1)); Sl_rdDAck : out std_logic; Sl_rdComp : out std_logic; Sl_MBusy : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1)); Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1)); Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1)); Sl_wrBTerm : out std_logic; Sl_rdWdAddr : out std_logic_vector(0 to 3); Sl_rdBTerm : out std_logic; Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1)); Intr : in std_logic_vector((C_NUM_INTR_INPUTS-1) downto 0); Irq : out std_logic ); end component; begin xps_intc_0 : xps_intc generic map ( C_FAMILY => "spartan3a", C_BASEADDR => X"81800000", C_HIGHADDR => X"8180ffff", C_SPLB_AWIDTH => 32, C_SPLB_DWIDTH => 32, C_SPLB_P2P => 0, C_SPLB_NUM_MASTERS => 2, C_SPLB_MID_WIDTH => 1, C_SPLB_NATIVE_DWIDTH => 32, C_SPLB_SUPPORT_BURSTS => 0, C_NUM_INTR_INPUTS => 4, C_KIND_OF_INTR => B"11111111111111111111111111111101", C_KIND_OF_EDGE => B"11111111111111111111111111111111", C_KIND_OF_LVL => B"11111111111111111111111111111111", C_HAS_IPR => 1, C_HAS_SIE => 1, C_HAS_CIE => 1, C_HAS_IVR => 1, C_IRQ_IS_LEVEL => 1, C_IRQ_ACTIVE => '1' ) port map ( SPLB_Clk => SPLB_Clk, SPLB_Rst => SPLB_Rst, PLB_ABus => PLB_ABus, PLB_PAValid => PLB_PAValid, PLB_masterID => PLB_masterID, PLB_RNW => PLB_RNW, PLB_BE => PLB_BE, PLB_size => PLB_size, PLB_type => PLB_type, PLB_wrDBus => PLB_wrDBus, PLB_UABus => PLB_UABus, PLB_SAValid => PLB_SAValid, PLB_rdPrim => PLB_rdPrim, PLB_wrPrim => PLB_wrPrim, PLB_abort => PLB_abort, PLB_busLock => PLB_busLock, PLB_MSize => PLB_MSize, PLB_lockErr => PLB_lockErr, PLB_wrBurst => PLB_wrBurst, PLB_rdBurst => PLB_rdBurst, PLB_wrPendReq => PLB_wrPendReq, PLB_rdPendReq => PLB_rdPendReq, PLB_wrPendPri => PLB_wrPendPri, PLB_rdPendPri => PLB_rdPendPri, PLB_reqPri => PLB_reqPri, PLB_TAttribute => PLB_TAttribute, Sl_addrAck => Sl_addrAck, Sl_SSize => Sl_SSize, Sl_wait => Sl_wait, Sl_rearbitrate => Sl_rearbitrate, Sl_wrDAck => Sl_wrDAck, Sl_wrComp => Sl_wrComp, Sl_rdDBus => Sl_rdDBus, Sl_rdDAck => Sl_rdDAck, Sl_rdComp => Sl_rdComp, Sl_MBusy => Sl_MBusy, Sl_MWrErr => Sl_MWrErr, Sl_MRdErr => Sl_MRdErr, Sl_wrBTerm => Sl_wrBTerm, Sl_rdWdAddr => Sl_rdWdAddr, Sl_rdBTerm => Sl_rdBTerm, Sl_MIRQ => Sl_MIRQ, Intr => Intr, Irq => Irq ); end architecture STRUCTURE;
mit
9fd40bef3b77a5c45b4d4b2f3a9153ef
0.582922
3.187135
false
false
false
false
hoglet67/AtomFpga
src/common/RamRom_Phill.vhd
1
6,733
-------------------------------------------------------------------------------- -- Copyright (c) 2016 David Banks -------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / -- \ \ \/ -- \ \ -- / / Filename : RamRom_Phill -- /___/ /\ Timestamp : 04/07/2016 -- \ \ / \ -- \___\/\___\ -- --Design Name: RamRom_Phill library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; entity RamRom_Phill is port (clock : in std_logic; reset_n : in std_logic; -- signals from/to 6502 cpu_addr : in std_logic_vector (15 downto 0); cpu_we : in std_logic; cpu_dout : in std_logic_vector (7 downto 0); cpu_din : out std_logic_vector (7 downto 0); -- signals from/to external memory system ExternCE : out std_logic; ExternWE : out std_logic; ExternA : out std_logic_vector (18 downto 0); ExternDin : out std_logic_vector (7 downto 0); ExternDout : in std_logic_vector (7 downto 0) ); end RamRom_Phill; architecture behavioral of RamRom_Phill is signal BFFE_Enable : std_logic; signal BFFF_Enable : std_logic; signal RegBFFE : std_logic_vector (7 downto 0); signal RegBFFF : std_logic_vector (7 downto 0); signal RamCE : std_logic; signal RomCE : std_logic; signal ExtRAMEN1 : std_logic; -- SwitchLatch[0] on Phill's board signal ExtRAMEN2 : std_logic; -- SwitchLatch[1] on Phill's board signal DskRAMEN : std_logic; -- SwitchLatch[1] on Phill's board, not currently used in AtomFPGA signal DskROMEN : std_logic; -- SwitchLatch[2] on Phill's board signal BeebMode : std_logic; -- SwitchLatch[3] on Phill's board signal RomLatch : std_logic_vector (4 downto 0); signal Addr6000RAM : std_logic; signal Addr6000ROM : std_logic; signal Addr7000RAM : std_logic; signal Addr7000ROM : std_logic; signal AddrA000RAM : std_logic; signal AddrA000ROM : std_logic; begin Addr6000ROM <= '1' when cpu_addr(15 downto 12) = "0110" and (BeebMode = '1' and (RomLatch /= "00000" or ExtRAMEN1 = '0')) else '0'; Addr6000RAM <= '1' when cpu_addr(15 downto 12) = "0110" and (BeebMode = '0' or (RomLatch = "00000" and ExtRAMEN1 = '1')) else '0'; Addr7000ROM <= '1' when cpu_addr(15 downto 12) = "0111" and (BeebMode = '1' and ExtRAMEN2 = '0') else '0'; Addr7000RAM <= '1' when cpu_addr(15 downto 12) = "0111" and (BeebMode = '0' or ExtRAMEN2 = '1') else '0'; AddrA000ROM <= '1' when cpu_addr(15 downto 12) = "1010" and (BeebMode = '1' or RomLatch /= "00000" or ExtRAMEN1 = '0') else '0'; AddrA000RAM <= '1' when cpu_addr(15 downto 12) = "1010" and (BeebMode = '0' and RomLatch = "00000" and ExtRAMEN1 = '1') else '0'; RamCE <= '1' when cpu_addr(15 downto 12) < "0110" or Addr6000RAM = '1' or Addr7000RAM = '1' or AddrA000RAM = '1' else '0'; RomCE <= '1' when cpu_addr(15 downto 14) = "11" or Addr6000ROM = '1' or Addr7000ROM = '1' or AddrA000ROM = '1' else '0'; ExternCE <= RamCE or RomCE; ExternWE <= cpu_we and RamCE; ExternDin <= cpu_dout; cpu_din <= RegBFFE when BFFE_Enable = '1' else RegBFFF when BFFF_Enable = '1' else ExternDout; ------------------------------------------------- -- External address decoding -- -- external address bus is 18..0 (512KB) -- bit 18 is always zero -- bit 17 selects between ROM (0) and RAM (1) -- bits 16..0 select with 128KB block ------------------------------------------------- ExternA <= -- 0x6000 comes from ROM address 0x08000-0x0F000 in Beeb Mode (Ext ROM 1) ( "0001" & RomLatch(2 downto 0) & cpu_addr(11 downto 0)) when Addr6000ROM = '1' else -- 0x6000 is 4K remappable RAM bank mapped to 0x6000 ( "01" & ExtRAMEN1 & cpu_addr(15 downto 0)) when Addr6000RAM = '1' else -- 0x7000 comes from ROM address 0x19000 in Beeb Mode (Ext ROM 2) ( "0011001" & cpu_addr(11 downto 0)) when Addr7000ROM = '1' else -- 0x7000 is 4K remappable RAM bank mapped to 0x7000 ( "01" & ExtRAMEN2 & cpu_addr(15 downto 0)) when Addr7000RAM = '1' else -- 0xA000 remappable RAM bank at 0x7000 re-mapped to 0xA000 ( "0100111" & cpu_addr(11 downto 0)) when AddrA000RAM = '1' else -- 0xA000 is bank switched by ROM Latch in Atom Mode -- 5 bits of RomLatch are used here, to allow any of the 32 pages of FLASH to A000 for in system programming ( "00" & RomLatch & cpu_addr(11 downto 0)) when AddrA000ROM = '1' and BeebMode = '0' else -- 0xA000 comes from ROM address 0x0A000 in Beeb Mode ( "0011010" & cpu_addr(11 downto 0)) when AddrA000ROM = '1' and BeebMode = '1' else -- 0xC000-0xFFFF comes from ROM address 0x1C000-0x1FFFF in Beeb Mode ( "001" & cpu_addr(15 downto 0)) when cpu_addr(15 downto 14) = "11" and BeebMode = '1' else -- 0xC000-0xFFFF comes from ROM address 0x10000-0x17FFF in Atom Mode (2x 16K banks selected SwitchLatch[2]) ( "0010" & DskROMEN & cpu_addr(13 downto 0)) when cpu_addr(15 downto 14) = "11" and BeebMode = '0' else -- RAM ( "010" & cpu_addr); ------------------------------------------------- -- RAM/ROM Board Registers ------------------------------------------------- BFFE_Enable <= '1' when cpu_addr(15 downto 0) = "1011111111111110" else '0'; BFFF_Enable <= '1' when cpu_addr(15 downto 0) = "1011111111111111" else '0'; RomLatchProcess : process (reset_n, clock) begin if reset_n = '0' then RegBFFE <= (others => '0'); RegBFFF <= (others => '0'); elsif rising_edge(clock) then if BFFE_Enable = '1' and cpu_we = '1' then RegBFFE <= cpu_dout; end if; if BFFF_Enable = '1' and cpu_we = '1' then RegBFFF <= cpu_dout; end if; end if; end process; ExtRAMEN1 <= RegBFFE(0); ExtRAMEN2 <= RegBFFE(1); DskRAMEN <= RegBFFE(1); -- currently unused DskROMEN <= RegBFFE(2); BeebMode <= RegBFFE(3); RomLatch <= RegBFFF(4 downto 0); end behavioral;
apache-2.0
157dbf787417266699a754295faa8845
0.525175
3.515927
false
false
false
false
tghaefli/ADD
EDK/IVK_Repos/IVK_IPLib/pcores/sg_cfa_gamma_plbw_v1_00_a/hdl/vhdl/sg_cfa_gamma_cw.vhd
1
23,447
------------------------------------------------------------------- -- System Generator version 13.2 VHDL source file. -- -- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- ------------------------------------------------------------------- -- System Generator version 13.2 VHDL source file. -- -- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; -- synopsys translate_off library unisim; use unisim.vcomponents.all; -- synopsys translate_on entity xlclockdriver is generic ( period: integer := 2; log_2_period: integer := 0; pipeline_regs: integer := 5; use_bufg: integer := 0 ); port ( sysclk: in std_logic; sysclr: in std_logic; sysce: in std_logic; clk: out std_logic; clr: out std_logic; ce: out std_logic; ce_logic: out std_logic ); end xlclockdriver; architecture behavior of xlclockdriver is component bufg port ( i: in std_logic; o: out std_logic ); end component; component synth_reg_w_init generic ( width: integer; init_index: integer; init_value: bit_vector; latency: integer ); port ( i: in std_logic_vector(width - 1 downto 0); ce: in std_logic; clr: in std_logic; clk: in std_logic; o: out std_logic_vector(width - 1 downto 0) ); end component; function size_of_uint(inp: integer; power_of_2: boolean) return integer is constant inp_vec: std_logic_vector(31 downto 0) := integer_to_std_logic_vector(inp,32, xlUnsigned); variable result: integer; begin result := 32; for i in 0 to 31 loop if inp_vec(i) = '1' then result := i; end if; end loop; if power_of_2 then return result; else return result+1; end if; end; function is_power_of_2(inp: std_logic_vector) return boolean is constant width: integer := inp'length; variable vec: std_logic_vector(width - 1 downto 0); variable single_bit_set: boolean; variable more_than_one_bit_set: boolean; variable result: boolean; begin vec := inp; single_bit_set := false; more_than_one_bit_set := false; -- synopsys translate_off if (is_XorU(vec)) then return false; end if; -- synopsys translate_on if width > 0 then for i in 0 to width - 1 loop if vec(i) = '1' then if single_bit_set then more_than_one_bit_set := true; end if; single_bit_set := true; end if; end loop; end if; if (single_bit_set and not(more_than_one_bit_set)) then result := true; else result := false; end if; return result; end; function ce_reg_init_val(index, period : integer) return integer is variable result: integer; begin result := 0; if ((index mod period) = 0) then result := 1; end if; return result; end; function remaining_pipe_regs(num_pipeline_regs, period : integer) return integer is variable factor, result: integer; begin factor := (num_pipeline_regs / period); result := num_pipeline_regs - (period * factor) + 1; return result; end; function sg_min(L, R: INTEGER) return INTEGER is begin if L < R then return L; else return R; end if; end; constant max_pipeline_regs : integer := 8; constant pipe_regs : integer := 5; constant num_pipeline_regs : integer := sg_min(pipeline_regs, max_pipeline_regs); constant rem_pipeline_regs : integer := remaining_pipe_regs(num_pipeline_regs,period); constant period_floor: integer := max(2, period); constant power_of_2_counter: boolean := is_power_of_2(integer_to_std_logic_vector(period_floor,32, xlUnsigned)); constant cnt_width: integer := size_of_uint(period_floor, power_of_2_counter); constant clk_for_ce_pulse_minus1: std_logic_vector(cnt_width - 1 downto 0) := integer_to_std_logic_vector((period_floor - 2),cnt_width, xlUnsigned); constant clk_for_ce_pulse_minus2: std_logic_vector(cnt_width - 1 downto 0) := integer_to_std_logic_vector(max(0,period - 3),cnt_width, xlUnsigned); constant clk_for_ce_pulse_minus_regs: std_logic_vector(cnt_width - 1 downto 0) := integer_to_std_logic_vector(max(0,period - rem_pipeline_regs),cnt_width, xlUnsigned); signal clk_num: unsigned(cnt_width - 1 downto 0) := (others => '0'); signal ce_vec : std_logic_vector(num_pipeline_regs downto 0); attribute MAX_FANOUT : string; attribute MAX_FANOUT of ce_vec:signal is "REDUCE"; signal ce_vec_logic : std_logic_vector(num_pipeline_regs downto 0); attribute MAX_FANOUT of ce_vec_logic:signal is "REDUCE"; signal internal_ce: std_logic_vector(0 downto 0); signal internal_ce_logic: std_logic_vector(0 downto 0); signal cnt_clr, cnt_clr_dly: std_logic_vector (0 downto 0); begin clk <= sysclk; clr <= sysclr; cntr_gen: process(sysclk) begin if sysclk'event and sysclk = '1' then if (sysce = '1') then if ((cnt_clr_dly(0) = '1') or (sysclr = '1')) then clk_num <= (others => '0'); else clk_num <= clk_num + 1; end if; end if; end if; end process; clr_gen: process(clk_num, sysclr) begin if power_of_2_counter then cnt_clr(0) <= sysclr; else if (unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus1 or sysclr = '1') then cnt_clr(0) <= '1'; else cnt_clr(0) <= '0'; end if; end if; end process; clr_reg: synth_reg_w_init generic map ( width => 1, init_index => 0, init_value => b"0000", latency => 1 ) port map ( i => cnt_clr, ce => sysce, clr => sysclr, clk => sysclk, o => cnt_clr_dly ); pipelined_ce : if period > 1 generate ce_gen: process(clk_num) begin if unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus_regs then ce_vec(num_pipeline_regs) <= '1'; else ce_vec(num_pipeline_regs) <= '0'; end if; end process; ce_pipeline: for index in num_pipeline_regs downto 1 generate ce_reg : synth_reg_w_init generic map ( width => 1, init_index => ce_reg_init_val(index, period), init_value => b"0000", latency => 1 ) port map ( i => ce_vec(index downto index), ce => sysce, clr => sysclr, clk => sysclk, o => ce_vec(index-1 downto index-1) ); end generate; internal_ce <= ce_vec(0 downto 0); end generate; pipelined_ce_logic: if period > 1 generate ce_gen_logic: process(clk_num) begin if unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus_regs then ce_vec_logic(num_pipeline_regs) <= '1'; else ce_vec_logic(num_pipeline_regs) <= '0'; end if; end process; ce_logic_pipeline: for index in num_pipeline_regs downto 1 generate ce_logic_reg : synth_reg_w_init generic map ( width => 1, init_index => ce_reg_init_val(index, period), init_value => b"0000", latency => 1 ) port map ( i => ce_vec_logic(index downto index), ce => sysce, clr => sysclr, clk => sysclk, o => ce_vec_logic(index-1 downto index-1) ); end generate; internal_ce_logic <= ce_vec_logic(0 downto 0); end generate; use_bufg_true: if period > 1 and use_bufg = 1 generate ce_bufg_inst: bufg port map ( i => internal_ce(0), o => ce ); ce_bufg_inst_logic: bufg port map ( i => internal_ce_logic(0), o => ce_logic ); end generate; use_bufg_false: if period > 1 and (use_bufg = 0) generate ce <= internal_ce(0); ce_logic <= internal_ce_logic(0); end generate; generate_system_clk: if period = 1 generate ce <= sysce; ce_logic <= sysce; end generate; end architecture behavior; ------------------------------------------------------------------- -- System Generator version 13.2 VHDL source file. -- -- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; entity xland2 is port ( a : in std_logic; b : in std_logic; dout : out std_logic ); end xland2; architecture behavior of xland2 is begin dout <= a and b; end behavior; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity default_clock_driver is port ( sysce: in std_logic; sysce_clr: in std_logic; sysclk: in std_logic; ce_1: out std_logic; clk_1: out std_logic ); end default_clock_driver; architecture structural of default_clock_driver is attribute syn_noprune: boolean; attribute syn_noprune of structural : architecture is true; attribute optimize_primitives: boolean; attribute optimize_primitives of structural : architecture is false; attribute dont_touch: boolean; attribute dont_touch of structural : architecture is true; signal sysce_clr_x0: std_logic; signal sysce_x0: std_logic; signal sysclk_x0: std_logic; signal xlclockdriver_1_ce: std_logic; signal xlclockdriver_1_clk: std_logic; begin sysce_x0 <= sysce; sysce_clr_x0 <= sysce_clr; sysclk_x0 <= sysclk; ce_1 <= xlclockdriver_1_ce; clk_1 <= xlclockdriver_1_clk; xlclockdriver_1: entity work.xlclockdriver generic map ( log_2_period => 1, period => 1, use_bufg => 0 ) port map ( sysce => sysce_x0, sysclk => sysclk_x0, sysclr => sysce_clr_x0, ce => xlclockdriver_1_ce, clk => xlclockdriver_1_clk ); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity plb_clock_driver is port ( sysce: in std_logic; sysce_clr: in std_logic; sysclk: in std_logic; plb_ce_1: out std_logic; plb_clk_1: out std_logic ); end plb_clock_driver; architecture structural of plb_clock_driver is attribute syn_noprune: boolean; attribute syn_noprune of structural : architecture is true; attribute optimize_primitives: boolean; attribute optimize_primitives of structural : architecture is false; attribute dont_touch: boolean; attribute dont_touch of structural : architecture is true; signal sysce_clr_x0: std_logic; signal sysce_x0: std_logic; signal sysclk_x0: std_logic; signal xlclockdriver_1_ce: std_logic; signal xlclockdriver_1_clk: std_logic; begin sysce_x0 <= sysce; sysce_clr_x0 <= sysce_clr; sysclk_x0 <= sysclk; plb_ce_1 <= xlclockdriver_1_ce; plb_clk_1 <= xlclockdriver_1_clk; xlclockdriver_1: entity work.xlclockdriver generic map ( log_2_period => 1, period => 1, use_bufg => 0 ) port map ( sysce => sysce_x0, sysclk => sysclk_x0, sysclr => sysce_clr_x0, ce => xlclockdriver_1_ce, clk => xlclockdriver_1_clk ); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity sg_cfa_gamma_cw is port ( active_video_i: in std_logic; ce: in std_logic := '1'; clk: in std_logic; -- clock period = 10.0 ns (100.0 Mhz) hblank_i: in std_logic; hsync_i: in std_logic; plb_abus: in std_logic_vector(31 downto 0); plb_pavalid: in std_logic; plb_rnw: in std_logic; plb_wrdbus: in std_logic_vector(31 downto 0); sg_plb_addrpref: in std_logic_vector(19 downto 0); splb_rst: in std_logic; vblank_i: in std_logic; video_data_i: in std_logic_vector(7 downto 0); vsync_i: in std_logic; xps_ce: in std_logic := '1'; xps_clk: in std_logic; -- clock period = 10.0 ns (100.0 Mhz) active_video_o: out std_logic; hblank_o: out std_logic; hsync_o: out std_logic; sl_addrack: out std_logic; sl_rdcomp: out std_logic; sl_rddack: out std_logic; sl_rddbus: out std_logic_vector(31 downto 0); sl_wait: out std_logic; sl_wrcomp: out std_logic; sl_wrdack: out std_logic; vblank_o: out std_logic; video_data_o: out std_logic_vector(23 downto 0); vsync_o: out std_logic ); end sg_cfa_gamma_cw; architecture structural of sg_cfa_gamma_cw is component xlpersistentdff port ( clk: in std_logic; d: in std_logic; q: out std_logic ); end component; attribute syn_black_box: boolean; attribute syn_black_box of xlpersistentdff: component is true; attribute box_type: string; attribute box_type of xlpersistentdff: component is "black_box"; attribute syn_noprune: boolean; attribute optimize_primitives: boolean; attribute dont_touch: boolean; attribute syn_noprune of xlpersistentdff: component is true; attribute optimize_primitives of xlpersistentdff: component is false; attribute dont_touch of xlpersistentdff: component is true; signal active_video_i_net: std_logic; signal active_video_o_net: std_logic; signal bayer_ctrl_reg_ce: std_logic; signal ce_1_sg_x3: std_logic; attribute MAX_FANOUT: string; attribute MAX_FANOUT of ce_1_sg_x3: signal is "REDUCE"; signal clkNet: std_logic; signal clkNet_x0: std_logic; signal clk_1_sg_x3: std_logic; signal data_in_net: std_logic_vector(31 downto 0); signal data_out_net: std_logic_vector(31 downto 0); signal en_net: std_logic; signal hblank_i_net: std_logic; signal hblank_o_net: std_logic; signal hsync_i_net: std_logic; signal hsync_o_net: std_logic; signal persistentdff_inst_q: std_logic; attribute syn_keep: boolean; attribute syn_keep of persistentdff_inst_q: signal is true; attribute keep: boolean; attribute keep of persistentdff_inst_q: signal is true; attribute preserve_signal: boolean; attribute preserve_signal of persistentdff_inst_q: signal is true; signal plb_abus_net: std_logic_vector(31 downto 0); signal plb_ce_1_sg_x1: std_logic; attribute MAX_FANOUT of plb_ce_1_sg_x1: signal is "REDUCE"; signal plb_clk_1_sg_x1: std_logic; signal plb_pavalid_net: std_logic; signal plb_rnw_net: std_logic; signal plb_wrdbus_net: std_logic_vector(31 downto 0); signal sg_plb_addrpref_net: std_logic_vector(19 downto 0); signal sl_addrack_net: std_logic; signal sl_rdcomp_net: std_logic; signal sl_rddack_net: std_logic; signal sl_rddbus_net: std_logic_vector(31 downto 0); signal sl_wait_net: std_logic; signal sl_wrdack_x1: std_logic; signal sl_wrdack_x2: std_logic; signal splb_rst_net: std_logic; signal vblank_i_net: std_logic; signal vblank_o_net: std_logic; signal video_data_i_net: std_logic_vector(7 downto 0); signal video_data_o_net: std_logic_vector(23 downto 0); signal vsync_i_net: std_logic; signal vsync_o_net: std_logic; begin active_video_i_net <= active_video_i; clkNet <= clk; hblank_i_net <= hblank_i; hsync_i_net <= hsync_i; plb_abus_net <= plb_abus; plb_pavalid_net <= plb_pavalid; plb_rnw_net <= plb_rnw; plb_wrdbus_net <= plb_wrdbus; sg_plb_addrpref_net <= sg_plb_addrpref; splb_rst_net <= splb_rst; vblank_i_net <= vblank_i; video_data_i_net <= video_data_i; vsync_i_net <= vsync_i; clkNet_x0 <= xps_clk; active_video_o <= active_video_o_net; hblank_o <= hblank_o_net; hsync_o <= hsync_o_net; sl_addrack <= sl_addrack_net; sl_rdcomp <= sl_rdcomp_net; sl_rddack <= sl_rddack_net; sl_rddbus <= sl_rddbus_net; sl_wait <= sl_wait_net; sl_wrcomp <= sl_wrdack_x2; sl_wrdack <= sl_wrdack_x1; vblank_o <= vblank_o_net; video_data_o <= video_data_o_net; vsync_o <= vsync_o_net; bayer_ctrl: entity work.synth_reg_w_init generic map ( width => 32, init_index => 2, init_value => b"00000001000110110100000111100100", latency => 1 ) port map ( ce => bayer_ctrl_reg_ce, clk => plb_clk_1_sg_x1, clr => '0', i => data_in_net, o => data_out_net ); bayer_ctrl_ce_and2_comp: entity work.xland2 port map ( a => plb_ce_1_sg_x1, b => en_net, dout => bayer_ctrl_reg_ce ); default_clock_driver_x0: entity work.default_clock_driver port map ( sysce => '1', sysce_clr => '0', sysclk => clkNet, ce_1 => ce_1_sg_x3, clk_1 => clk_1_sg_x3 ); persistentdff_inst: xlpersistentdff port map ( clk => clkNet, d => persistentdff_inst_q, q => persistentdff_inst_q ); plb_clock_driver_x0: entity work.plb_clock_driver port map ( sysce => '1', sysce_clr => '0', sysclk => clkNet_x0, plb_ce_1 => plb_ce_1_sg_x1, plb_clk_1 => plb_clk_1_sg_x1 ); sg_cfa_gamma_x0: entity work.sg_cfa_gamma port map ( active_video_i => active_video_i_net, ce_1 => ce_1_sg_x3, clk_1 => clk_1_sg_x3, data_out => data_out_net, dout => data_out_net, hblank_i => hblank_i_net, hsync_i => hsync_i_net, plb_abus => plb_abus_net, plb_ce_1 => plb_ce_1_sg_x1, plb_clk_1 => plb_clk_1_sg_x1, plb_pavalid => plb_pavalid_net, plb_rnw => plb_rnw_net, plb_wrdbus => plb_wrdbus_net, sg_plb_addrpref => sg_plb_addrpref_net, splb_rst => splb_rst_net, vblank_i => vblank_i_net, video_data_i => video_data_i_net, vsync_i => vsync_i_net, active_video_o => active_video_o_net, data_in => data_in_net, en => en_net, hblank_o => hblank_o_net, hsync_o => hsync_o_net, sl_addrack => sl_addrack_net, sl_rdcomp => sl_rdcomp_net, sl_rddack => sl_rddack_net, sl_rddbus => sl_rddbus_net, sl_wait => sl_wait_net, sl_wrcomp => sl_wrdack_x2, sl_wrdack => sl_wrdack_x1, vblank_o => vblank_o_net, video_data_o => video_data_o_net, vsync_o => vsync_o_net ); end structural;
gpl-3.0
4fc24cacd961081cc54eff6de7a23591
0.636627
3.518457
false
false
false
false
hoglet67/AtomFpga
src/common/ROM/kernel_2015.vhd
1
172,875
-- generated with romgen v3.0.1r4 by MikeJ truhy and eD library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; library UNISIM; use UNISIM.Vcomponents.all; entity atomkernal is port ( CLK : in std_logic; ADDR : in std_logic_vector(11 downto 0); DATA : out std_logic_vector(7 downto 0) ); end; architecture RTL of atomkernal is signal rom_addr : std_logic_vector(11 downto 0); begin p_addr : process(ADDR) begin rom_addr <= (others => '0'); rom_addr(11 downto 0) <= ADDR; end process; p_rom : process begin wait until rising_edge(CLK); DATA <= (others => '0'); case rom_addr is when x"000" => DATA <= x"50"; when x"001" => DATA <= x"4C"; when x"002" => DATA <= x"4F"; when x"003" => DATA <= x"54"; when x"004" => DATA <= x"F5"; when x"005" => DATA <= x"4E"; when x"006" => DATA <= x"44"; when x"007" => DATA <= x"52"; when x"008" => DATA <= x"41"; when x"009" => DATA <= x"57"; when x"00A" => DATA <= x"F5"; when x"00B" => DATA <= x"42"; when x"00C" => DATA <= x"4D"; when x"00D" => DATA <= x"4F"; when x"00E" => DATA <= x"56"; when x"00F" => DATA <= x"45"; when x"010" => DATA <= x"F5"; when x"011" => DATA <= x"46"; when x"012" => DATA <= x"43"; when x"013" => DATA <= x"4C"; when x"014" => DATA <= x"45"; when x"015" => DATA <= x"41"; when x"016" => DATA <= x"52"; when x"017" => DATA <= x"F6"; when x"018" => DATA <= x"7B"; when x"019" => DATA <= x"44"; when x"01A" => DATA <= x"49"; when x"01B" => DATA <= x"4D"; when x"01C" => DATA <= x"F0"; when x"01D" => DATA <= x"AE"; when x"01E" => DATA <= x"5B"; when x"01F" => DATA <= x"F2"; when x"020" => DATA <= x"A1"; when x"021" => DATA <= x"4F"; when x"022" => DATA <= x"4C"; when x"023" => DATA <= x"44"; when x"024" => DATA <= x"F5"; when x"025" => DATA <= x"31"; when x"026" => DATA <= x"57"; when x"027" => DATA <= x"41"; when x"028" => DATA <= x"49"; when x"029" => DATA <= x"54"; when x"02A" => DATA <= x"F1"; when x"02B" => DATA <= x"4C"; when x"02C" => DATA <= x"C5"; when x"02D" => DATA <= x"50"; when x"02E" => DATA <= x"A4"; when x"02F" => DATA <= x"5E"; when x"030" => DATA <= x"B1"; when x"031" => DATA <= x"05"; when x"032" => DATA <= x"C9"; when x"033" => DATA <= x"40"; when x"034" => DATA <= x"90"; when x"035" => DATA <= x"12"; when x"036" => DATA <= x"C9"; when x"037" => DATA <= x"5B"; when x"038" => DATA <= x"B0"; when x"039" => DATA <= x"0E"; when x"03A" => DATA <= x"C8"; when x"03B" => DATA <= x"D1"; when x"03C" => DATA <= x"05"; when x"03D" => DATA <= x"D0"; when x"03E" => DATA <= x"09"; when x"03F" => DATA <= x"20"; when x"040" => DATA <= x"8B"; when x"041" => DATA <= x"F0"; when x"042" => DATA <= x"20"; when x"043" => DATA <= x"4F"; when x"044" => DATA <= x"C9"; when x"045" => DATA <= x"4C"; when x"046" => DATA <= x"62"; when x"047" => DATA <= x"C9"; when x"048" => DATA <= x"4C"; when x"049" => DATA <= x"24"; when x"04A" => DATA <= x"CA"; when x"04B" => DATA <= x"A2"; when x"04C" => DATA <= x"FF"; when x"04D" => DATA <= x"A4"; when x"04E" => DATA <= x"5E"; when x"04F" => DATA <= x"C6"; when x"050" => DATA <= x"5E"; when x"051" => DATA <= x"B1"; when x"052" => DATA <= x"05"; when x"053" => DATA <= x"C9"; when x"054" => DATA <= x"40"; when x"055" => DATA <= x"90"; when x"056" => DATA <= x"09"; when x"057" => DATA <= x"C9"; when x"058" => DATA <= x"5B"; when x"059" => DATA <= x"B0"; when x"05A" => DATA <= x"05"; when x"05B" => DATA <= x"C8"; when x"05C" => DATA <= x"D1"; when x"05D" => DATA <= x"05"; when x"05E" => DATA <= x"F0"; when x"05F" => DATA <= x"25"; when x"060" => DATA <= x"A4"; when x"061" => DATA <= x"5E"; when x"062" => DATA <= x"E8"; when x"063" => DATA <= x"C8"; when x"064" => DATA <= x"BD"; when x"065" => DATA <= x"00"; when x"066" => DATA <= x"F0"; when x"067" => DATA <= x"30"; when x"068" => DATA <= x"0C"; when x"069" => DATA <= x"D1"; when x"06A" => DATA <= x"05"; when x"06B" => DATA <= x"F0"; when x"06C" => DATA <= x"F5"; when x"06D" => DATA <= x"E8"; when x"06E" => DATA <= x"BD"; when x"06F" => DATA <= x"FF"; when x"070" => DATA <= x"EF"; when x"071" => DATA <= x"10"; when x"072" => DATA <= x"FA"; when x"073" => DATA <= x"D0"; when x"074" => DATA <= x"EB"; when x"075" => DATA <= x"85"; when x"076" => DATA <= x"53"; when x"077" => DATA <= x"BD"; when x"078" => DATA <= x"01"; when x"079" => DATA <= x"F0"; when x"07A" => DATA <= x"85"; when x"07B" => DATA <= x"52"; when x"07C" => DATA <= x"84"; when x"07D" => DATA <= x"03"; when x"07E" => DATA <= x"A6"; when x"07F" => DATA <= x"04"; when x"080" => DATA <= x"E6"; when x"081" => DATA <= x"5E"; when x"082" => DATA <= x"6C"; when x"083" => DATA <= x"52"; when x"084" => DATA <= x"00"; when x"085" => DATA <= x"20"; when x"086" => DATA <= x"8B"; when x"087" => DATA <= x"F0"; when x"088" => DATA <= x"4C"; when x"089" => DATA <= x"F1"; when x"08A" => DATA <= x"C3"; when x"08B" => DATA <= x"C8"; when x"08C" => DATA <= x"84"; when x"08D" => DATA <= x"03"; when x"08E" => DATA <= x"E9"; when x"08F" => DATA <= x"40"; when x"090" => DATA <= x"48"; when x"091" => DATA <= x"20"; when x"092" => DATA <= x"BC"; when x"093" => DATA <= x"C8"; when x"094" => DATA <= x"68"; when x"095" => DATA <= x"A8"; when x"096" => DATA <= x"B5"; when x"097" => DATA <= x"15"; when x"098" => DATA <= x"0A"; when x"099" => DATA <= x"36"; when x"09A" => DATA <= x"24"; when x"09B" => DATA <= x"0A"; when x"09C" => DATA <= x"36"; when x"09D" => DATA <= x"24"; when x"09E" => DATA <= x"18"; when x"09F" => DATA <= x"79"; when x"0A0" => DATA <= x"EB"; when x"0A1" => DATA <= x"02"; when x"0A2" => DATA <= x"95"; when x"0A3" => DATA <= x"15"; when x"0A4" => DATA <= x"B5"; when x"0A5" => DATA <= x"24"; when x"0A6" => DATA <= x"79"; when x"0A7" => DATA <= x"06"; when x"0A8" => DATA <= x"03"; when x"0A9" => DATA <= x"95"; when x"0AA" => DATA <= x"24"; when x"0AB" => DATA <= x"B0"; when x"0AC" => DATA <= x"D7"; when x"0AD" => DATA <= x"60"; when x"0AE" => DATA <= x"A5"; when x"0AF" => DATA <= x"01"; when x"0B0" => DATA <= x"05"; when x"0B1" => DATA <= x"02"; when x"0B2" => DATA <= x"F0"; when x"0B3" => DATA <= x"22"; when x"0B4" => DATA <= x"20"; when x"0B5" => DATA <= x"34"; when x"0B6" => DATA <= x"C4"; when x"0B7" => DATA <= x"90"; when x"0B8" => DATA <= x"1E"; when x"0B9" => DATA <= x"20"; when x"0BA" => DATA <= x"BC"; when x"0BB" => DATA <= x"C8"; when x"0BC" => DATA <= x"CA"; when x"0BD" => DATA <= x"CA"; when x"0BE" => DATA <= x"86"; when x"0BF" => DATA <= x"04"; when x"0C0" => DATA <= x"B4"; when x"0C1" => DATA <= x"16"; when x"0C2" => DATA <= x"38"; when x"0C3" => DATA <= x"A5"; when x"0C4" => DATA <= x"23"; when x"0C5" => DATA <= x"99"; when x"0C6" => DATA <= x"21"; when x"0C7" => DATA <= x"03"; when x"0C8" => DATA <= x"75"; when x"0C9" => DATA <= x"17"; when x"0CA" => DATA <= x"85"; when x"0CB" => DATA <= x"23"; when x"0CC" => DATA <= x"A5"; when x"0CD" => DATA <= x"24"; when x"0CE" => DATA <= x"99"; when x"0CF" => DATA <= x"3C"; when x"0D0" => DATA <= x"03"; when x"0D1" => DATA <= x"75"; when x"0D2" => DATA <= x"26"; when x"0D3" => DATA <= x"4C"; when x"0D4" => DATA <= x"19"; when x"0D5" => DATA <= x"F1"; when x"0D6" => DATA <= x"00"; when x"0D7" => DATA <= x"A4"; when x"0D8" => DATA <= x"03"; when x"0D9" => DATA <= x"B1"; when x"0DA" => DATA <= x"05"; when x"0DB" => DATA <= x"C9"; when x"0DC" => DATA <= x"40"; when x"0DD" => DATA <= x"90"; when x"0DE" => DATA <= x"F7"; when x"0DF" => DATA <= x"C9"; when x"0E0" => DATA <= x"5B"; when x"0E1" => DATA <= x"B0"; when x"0E2" => DATA <= x"F3"; when x"0E3" => DATA <= x"C8"; when x"0E4" => DATA <= x"D1"; when x"0E5" => DATA <= x"05"; when x"0E6" => DATA <= x"D0"; when x"0E7" => DATA <= x"EE"; when x"0E8" => DATA <= x"E9"; when x"0E9" => DATA <= x"40"; when x"0EA" => DATA <= x"48"; when x"0EB" => DATA <= x"C8"; when x"0EC" => DATA <= x"84"; when x"0ED" => DATA <= x"03"; when x"0EE" => DATA <= x"20"; when x"0EF" => DATA <= x"BC"; when x"0F0" => DATA <= x"C8"; when x"0F1" => DATA <= x"68"; when x"0F2" => DATA <= x"A8"; when x"0F3" => DATA <= x"A5"; when x"0F4" => DATA <= x"23"; when x"0F5" => DATA <= x"99"; when x"0F6" => DATA <= x"EB"; when x"0F7" => DATA <= x"02"; when x"0F8" => DATA <= x"A5"; when x"0F9" => DATA <= x"24"; when x"0FA" => DATA <= x"99"; when x"0FB" => DATA <= x"06"; when x"0FC" => DATA <= x"03"; when x"0FD" => DATA <= x"CA"; when x"0FE" => DATA <= x"86"; when x"0FF" => DATA <= x"04"; when x"100" => DATA <= x"B4"; when x"101" => DATA <= x"16"; when x"102" => DATA <= x"C8"; when x"103" => DATA <= x"D0"; when x"104" => DATA <= x"02"; when x"105" => DATA <= x"F6"; when x"106" => DATA <= x"25"; when x"107" => DATA <= x"98"; when x"108" => DATA <= x"0A"; when x"109" => DATA <= x"36"; when x"10A" => DATA <= x"25"; when x"10B" => DATA <= x"0A"; when x"10C" => DATA <= x"36"; when x"10D" => DATA <= x"25"; when x"10E" => DATA <= x"18"; when x"10F" => DATA <= x"65"; when x"110" => DATA <= x"23"; when x"111" => DATA <= x"85"; when x"112" => DATA <= x"23"; when x"113" => DATA <= x"B5"; when x"114" => DATA <= x"25"; when x"115" => DATA <= x"65"; when x"116" => DATA <= x"24"; when x"117" => DATA <= x"B0"; when x"118" => DATA <= x"BD"; when x"119" => DATA <= x"85"; when x"11A" => DATA <= x"24"; when x"11B" => DATA <= x"A0"; when x"11C" => DATA <= x"00"; when x"11D" => DATA <= x"A9"; when x"11E" => DATA <= x"AA"; when x"11F" => DATA <= x"91"; when x"120" => DATA <= x"23"; when x"121" => DATA <= x"D1"; when x"122" => DATA <= x"23"; when x"123" => DATA <= x"D0"; when x"124" => DATA <= x"F7"; when x"125" => DATA <= x"4A"; when x"126" => DATA <= x"91"; when x"127" => DATA <= x"23"; when x"128" => DATA <= x"D1"; when x"129" => DATA <= x"23"; when x"12A" => DATA <= x"D0"; when x"12B" => DATA <= x"F0"; when x"12C" => DATA <= x"20"; when x"12D" => DATA <= x"34"; when x"12E" => DATA <= x"C4"; when x"12F" => DATA <= x"B0"; when x"130" => DATA <= x"A5"; when x"131" => DATA <= x"A4"; when x"132" => DATA <= x"03"; when x"133" => DATA <= x"B1"; when x"134" => DATA <= x"05"; when x"135" => DATA <= x"C9"; when x"136" => DATA <= x"2C"; when x"137" => DATA <= x"D0"; when x"138" => DATA <= x"05"; when x"139" => DATA <= x"E6"; when x"13A" => DATA <= x"03"; when x"13B" => DATA <= x"4C"; when x"13C" => DATA <= x"AE"; when x"13D" => DATA <= x"F0"; when x"13E" => DATA <= x"4C"; when x"13F" => DATA <= x"58"; when x"140" => DATA <= x"C5"; when x"141" => DATA <= x"A5"; when x"142" => DATA <= x"0D"; when x"143" => DATA <= x"85"; when x"144" => DATA <= x"23"; when x"145" => DATA <= x"A5"; when x"146" => DATA <= x"0E"; when x"147" => DATA <= x"85"; when x"148" => DATA <= x"24"; when x"149" => DATA <= x"4C"; when x"14A" => DATA <= x"83"; when x"14B" => DATA <= x"CE"; when x"14C" => DATA <= x"20"; when x"14D" => DATA <= x"E4"; when x"14E" => DATA <= x"C4"; when x"14F" => DATA <= x"20"; when x"150" => DATA <= x"66"; when x"151" => DATA <= x"FE"; when x"152" => DATA <= x"4C"; when x"153" => DATA <= x"5B"; when x"154" => DATA <= x"C5"; when x"155" => DATA <= x"1C"; when x"156" => DATA <= x"8A"; when x"157" => DATA <= x"1C"; when x"158" => DATA <= x"23"; when x"159" => DATA <= x"5D"; when x"15A" => DATA <= x"8B"; when x"15B" => DATA <= x"1B"; when x"15C" => DATA <= x"A1"; when x"15D" => DATA <= x"9D"; when x"15E" => DATA <= x"8A"; when x"15F" => DATA <= x"1D"; when x"160" => DATA <= x"23"; when x"161" => DATA <= x"9D"; when x"162" => DATA <= x"8B"; when x"163" => DATA <= x"1D"; when x"164" => DATA <= x"A1"; when x"165" => DATA <= x"00"; when x"166" => DATA <= x"29"; when x"167" => DATA <= x"19"; when x"168" => DATA <= x"AE"; when x"169" => DATA <= x"69"; when x"16A" => DATA <= x"A8"; when x"16B" => DATA <= x"19"; when x"16C" => DATA <= x"23"; when x"16D" => DATA <= x"24"; when x"16E" => DATA <= x"53"; when x"16F" => DATA <= x"1B"; when x"170" => DATA <= x"23"; when x"171" => DATA <= x"24"; when x"172" => DATA <= x"53"; when x"173" => DATA <= x"19"; when x"174" => DATA <= x"A1"; when x"175" => DATA <= x"00"; when x"176" => DATA <= x"1A"; when x"177" => DATA <= x"5B"; when x"178" => DATA <= x"5B"; when x"179" => DATA <= x"A5"; when x"17A" => DATA <= x"69"; when x"17B" => DATA <= x"24"; when x"17C" => DATA <= x"24"; when x"17D" => DATA <= x"AE"; when x"17E" => DATA <= x"AE"; when x"17F" => DATA <= x"A8"; when x"180" => DATA <= x"AD"; when x"181" => DATA <= x"29"; when x"182" => DATA <= x"00"; when x"183" => DATA <= x"7C"; when x"184" => DATA <= x"00"; when x"185" => DATA <= x"15"; when x"186" => DATA <= x"9C"; when x"187" => DATA <= x"6D"; when x"188" => DATA <= x"9C"; when x"189" => DATA <= x"A5"; when x"18A" => DATA <= x"69"; when x"18B" => DATA <= x"29"; when x"18C" => DATA <= x"53"; when x"18D" => DATA <= x"84"; when x"18E" => DATA <= x"13"; when x"18F" => DATA <= x"34"; when x"190" => DATA <= x"11"; when x"191" => DATA <= x"A5"; when x"192" => DATA <= x"69"; when x"193" => DATA <= x"23"; when x"194" => DATA <= x"A0"; when x"195" => DATA <= x"D8"; when x"196" => DATA <= x"62"; when x"197" => DATA <= x"5A"; when x"198" => DATA <= x"48"; when x"199" => DATA <= x"26"; when x"19A" => DATA <= x"62"; when x"19B" => DATA <= x"94"; when x"19C" => DATA <= x"88"; when x"19D" => DATA <= x"54"; when x"19E" => DATA <= x"44"; when x"19F" => DATA <= x"C8"; when x"1A0" => DATA <= x"54"; when x"1A1" => DATA <= x"68"; when x"1A2" => DATA <= x"44"; when x"1A3" => DATA <= x"E8"; when x"1A4" => DATA <= x"94"; when x"1A5" => DATA <= x"00"; when x"1A6" => DATA <= x"B4"; when x"1A7" => DATA <= x"08"; when x"1A8" => DATA <= x"84"; when x"1A9" => DATA <= x"74"; when x"1AA" => DATA <= x"B4"; when x"1AB" => DATA <= x"28"; when x"1AC" => DATA <= x"6E"; when x"1AD" => DATA <= x"74"; when x"1AE" => DATA <= x"F4"; when x"1AF" => DATA <= x"CC"; when x"1B0" => DATA <= x"4A"; when x"1B1" => DATA <= x"72"; when x"1B2" => DATA <= x"F2"; when x"1B3" => DATA <= x"A4"; when x"1B4" => DATA <= x"8A"; when x"1B5" => DATA <= x"00"; when x"1B6" => DATA <= x"AA"; when x"1B7" => DATA <= x"A2"; when x"1B8" => DATA <= x"A2"; when x"1B9" => DATA <= x"74"; when x"1BA" => DATA <= x"74"; when x"1BB" => DATA <= x"74"; when x"1BC" => DATA <= x"72"; when x"1BD" => DATA <= x"44"; when x"1BE" => DATA <= x"68"; when x"1BF" => DATA <= x"B2"; when x"1C0" => DATA <= x"32"; when x"1C1" => DATA <= x"B2"; when x"1C2" => DATA <= x"00"; when x"1C3" => DATA <= x"22"; when x"1C4" => DATA <= x"00"; when x"1C5" => DATA <= x"1A"; when x"1C6" => DATA <= x"1A"; when x"1C7" => DATA <= x"26"; when x"1C8" => DATA <= x"26"; when x"1C9" => DATA <= x"72"; when x"1CA" => DATA <= x"72"; when x"1CB" => DATA <= x"88"; when x"1CC" => DATA <= x"C8"; when x"1CD" => DATA <= x"C4"; when x"1CE" => DATA <= x"CA"; when x"1CF" => DATA <= x"26"; when x"1D0" => DATA <= x"48"; when x"1D1" => DATA <= x"44"; when x"1D2" => DATA <= x"44"; when x"1D3" => DATA <= x"A2"; when x"1D4" => DATA <= x"C8"; when x"1D5" => DATA <= x"00"; when x"1D6" => DATA <= x"02"; when x"1D7" => DATA <= x"00"; when x"1D8" => DATA <= x"08"; when x"1D9" => DATA <= x"F2"; when x"1DA" => DATA <= x"FF"; when x"1DB" => DATA <= x"80"; when x"1DC" => DATA <= x"01"; when x"1DD" => DATA <= x"C0"; when x"1DE" => DATA <= x"E2"; when x"1DF" => DATA <= x"C0"; when x"1E0" => DATA <= x"C0"; when x"1E1" => DATA <= x"FF"; when x"1E2" => DATA <= x"00"; when x"1E3" => DATA <= x"00"; when x"1E4" => DATA <= x"08"; when x"1E5" => DATA <= x"00"; when x"1E6" => DATA <= x"10"; when x"1E7" => DATA <= x"80"; when x"1E8" => DATA <= x"40"; when x"1E9" => DATA <= x"C0"; when x"1EA" => DATA <= x"00"; when x"1EB" => DATA <= x"C0"; when x"1EC" => DATA <= x"00"; when x"1ED" => DATA <= x"40"; when x"1EE" => DATA <= x"00"; when x"1EF" => DATA <= x"00"; when x"1F0" => DATA <= x"E4"; when x"1F1" => DATA <= x"20"; when x"1F2" => DATA <= x"80"; when x"1F3" => DATA <= x"00"; when x"1F4" => DATA <= x"FC"; when x"1F5" => DATA <= x"00"; when x"1F6" => DATA <= x"08"; when x"1F7" => DATA <= x"08"; when x"1F8" => DATA <= x"F8"; when x"1F9" => DATA <= x"FC"; when x"1FA" => DATA <= x"F4"; when x"1FB" => DATA <= x"0C"; when x"1FC" => DATA <= x"10"; when x"1FD" => DATA <= x"04"; when x"1FE" => DATA <= x"F4"; when x"1FF" => DATA <= x"00"; when x"200" => DATA <= x"20"; when x"201" => DATA <= x"10"; when x"202" => DATA <= x"00"; when x"203" => DATA <= x"00"; when x"204" => DATA <= x"0F"; when x"205" => DATA <= x"01"; when x"206" => DATA <= x"01"; when x"207" => DATA <= x"01"; when x"208" => DATA <= x"11"; when x"209" => DATA <= x"11"; when x"20A" => DATA <= x"02"; when x"20B" => DATA <= x"02"; when x"20C" => DATA <= x"11"; when x"20D" => DATA <= x"11"; when x"20E" => DATA <= x"02"; when x"20F" => DATA <= x"12"; when x"210" => DATA <= x"02"; when x"211" => DATA <= x"00"; when x"212" => DATA <= x"08"; when x"213" => DATA <= x"10"; when x"214" => DATA <= x"18"; when x"215" => DATA <= x"20"; when x"216" => DATA <= x"28"; when x"217" => DATA <= x"30"; when x"218" => DATA <= x"38"; when x"219" => DATA <= x"40"; when x"21A" => DATA <= x"48"; when x"21B" => DATA <= x"50"; when x"21C" => DATA <= x"58"; when x"21D" => DATA <= x"60"; when x"21E" => DATA <= x"68"; when x"21F" => DATA <= x"70"; when x"220" => DATA <= x"78"; when x"221" => DATA <= x"80"; when x"222" => DATA <= x"88"; when x"223" => DATA <= x"90"; when x"224" => DATA <= x"98"; when x"225" => DATA <= x"A0"; when x"226" => DATA <= x"A8"; when x"227" => DATA <= x"B0"; when x"228" => DATA <= x"B8"; when x"229" => DATA <= x"C0"; when x"22A" => DATA <= x"C8"; when x"22B" => DATA <= x"D0"; when x"22C" => DATA <= x"D8"; when x"22D" => DATA <= x"E0"; when x"22E" => DATA <= x"E8"; when x"22F" => DATA <= x"F0"; when x"230" => DATA <= x"F8"; when x"231" => DATA <= x"0C"; when x"232" => DATA <= x"2C"; when x"233" => DATA <= x"4C"; when x"234" => DATA <= x"4C"; when x"235" => DATA <= x"8C"; when x"236" => DATA <= x"AC"; when x"237" => DATA <= x"CC"; when x"238" => DATA <= x"EC"; when x"239" => DATA <= x"8A"; when x"23A" => DATA <= x"9A"; when x"23B" => DATA <= x"AA"; when x"23C" => DATA <= x"BA"; when x"23D" => DATA <= x"CA"; when x"23E" => DATA <= x"DA"; when x"23F" => DATA <= x"EA"; when x"240" => DATA <= x"FA"; when x"241" => DATA <= x"0E"; when x"242" => DATA <= x"2E"; when x"243" => DATA <= x"4E"; when x"244" => DATA <= x"6E"; when x"245" => DATA <= x"8E"; when x"246" => DATA <= x"AE"; when x"247" => DATA <= x"CE"; when x"248" => DATA <= x"EE"; when x"249" => DATA <= x"0D"; when x"24A" => DATA <= x"2D"; when x"24B" => DATA <= x"4D"; when x"24C" => DATA <= x"6D"; when x"24D" => DATA <= x"8D"; when x"24E" => DATA <= x"AD"; when x"24F" => DATA <= x"CD"; when x"250" => DATA <= x"ED"; when x"251" => DATA <= x"0D"; when x"252" => DATA <= x"0D"; when x"253" => DATA <= x"0C"; when x"254" => DATA <= x"0D"; when x"255" => DATA <= x"0E"; when x"256" => DATA <= x"0D"; when x"257" => DATA <= x"0C"; when x"258" => DATA <= x"0D"; when x"259" => DATA <= x"0D"; when x"25A" => DATA <= x"0D"; when x"25B" => DATA <= x"0C"; when x"25C" => DATA <= x"0D"; when x"25D" => DATA <= x"0D"; when x"25E" => DATA <= x"0D"; when x"25F" => DATA <= x"0C"; when x"260" => DATA <= x"0D"; when x"261" => DATA <= x"0F"; when x"262" => DATA <= x"0D"; when x"263" => DATA <= x"0C"; when x"264" => DATA <= x"0D"; when x"265" => DATA <= x"09"; when x"266" => DATA <= x"0D"; when x"267" => DATA <= x"0C"; when x"268" => DATA <= x"0D"; when x"269" => DATA <= x"08"; when x"26A" => DATA <= x"0D"; when x"26B" => DATA <= x"0C"; when x"26C" => DATA <= x"0D"; when x"26D" => DATA <= x"08"; when x"26E" => DATA <= x"0D"; when x"26F" => DATA <= x"0C"; when x"270" => DATA <= x"0D"; when x"271" => DATA <= x"0F"; when x"272" => DATA <= x"06"; when x"273" => DATA <= x"0B"; when x"274" => DATA <= x"0B"; when x"275" => DATA <= x"04"; when x"276" => DATA <= x"0A"; when x"277" => DATA <= x"08"; when x"278" => DATA <= x"08"; when x"279" => DATA <= x"0D"; when x"27A" => DATA <= x"0D"; when x"27B" => DATA <= x"0D"; when x"27C" => DATA <= x"0D"; when x"27D" => DATA <= x"0D"; when x"27E" => DATA <= x"0F"; when x"27F" => DATA <= x"0D"; when x"280" => DATA <= x"0F"; when x"281" => DATA <= x"07"; when x"282" => DATA <= x"07"; when x"283" => DATA <= x"07"; when x"284" => DATA <= x"07"; when x"285" => DATA <= x"05"; when x"286" => DATA <= x"09"; when x"287" => DATA <= x"03"; when x"288" => DATA <= x"03"; when x"289" => DATA <= x"01"; when x"28A" => DATA <= x"01"; when x"28B" => DATA <= x"01"; when x"28C" => DATA <= x"01"; when x"28D" => DATA <= x"02"; when x"28E" => DATA <= x"01"; when x"28F" => DATA <= x"01"; when x"290" => DATA <= x"01"; when x"291" => DATA <= x"A4"; when x"292" => DATA <= x"03"; when x"293" => DATA <= x"B1"; when x"294" => DATA <= x"05"; when x"295" => DATA <= x"E6"; when x"296" => DATA <= x"03"; when x"297" => DATA <= x"C9"; when x"298" => DATA <= x"20"; when x"299" => DATA <= x"F0"; when x"29A" => DATA <= x"F6"; when x"29B" => DATA <= x"60"; when x"29C" => DATA <= x"E6"; when x"29D" => DATA <= x"03"; when x"29E" => DATA <= x"4C"; when x"29F" => DATA <= x"1B"; when x"2A0" => DATA <= x"C3"; when x"2A1" => DATA <= x"B1"; when x"2A2" => DATA <= x"05"; when x"2A3" => DATA <= x"C9"; when x"2A4" => DATA <= x"5D"; when x"2A5" => DATA <= x"F0"; when x"2A6" => DATA <= x"F5"; when x"2A7" => DATA <= x"20"; when x"2A8" => DATA <= x"F6"; when x"2A9" => DATA <= x"C4"; when x"2AA" => DATA <= x"C6"; when x"2AB" => DATA <= x"03"; when x"2AC" => DATA <= x"20"; when x"2AD" => DATA <= x"8E"; when x"2AE" => DATA <= x"F3"; when x"2AF" => DATA <= x"C6"; when x"2B0" => DATA <= x"03"; when x"2B1" => DATA <= x"A5"; when x"2B2" => DATA <= x"52"; when x"2B3" => DATA <= x"48"; when x"2B4" => DATA <= x"A5"; when x"2B5" => DATA <= x"53"; when x"2B6" => DATA <= x"48"; when x"2B7" => DATA <= x"AD"; when x"2B8" => DATA <= x"21"; when x"2B9" => DATA <= x"03"; when x"2BA" => DATA <= x"48"; when x"2BB" => DATA <= x"A9"; when x"2BC" => DATA <= x"00"; when x"2BD" => DATA <= x"85"; when x"2BE" => DATA <= x"34"; when x"2BF" => DATA <= x"85"; when x"2C0" => DATA <= x"43"; when x"2C1" => DATA <= x"A9"; when x"2C2" => DATA <= x"05"; when x"2C3" => DATA <= x"8D"; when x"2C4" => DATA <= x"21"; when x"2C5" => DATA <= x"03"; when x"2C6" => DATA <= x"A5"; when x"2C7" => DATA <= x"01"; when x"2C8" => DATA <= x"85"; when x"2C9" => DATA <= x"16"; when x"2CA" => DATA <= x"A5"; when x"2CB" => DATA <= x"02"; when x"2CC" => DATA <= x"85"; when x"2CD" => DATA <= x"25"; when x"2CE" => DATA <= x"20"; when x"2CF" => DATA <= x"89"; when x"2D0" => DATA <= x"C5"; when x"2D1" => DATA <= x"20"; when x"2D2" => DATA <= x"79"; when x"2D3" => DATA <= x"F3"; when x"2D4" => DATA <= x"68"; when x"2D5" => DATA <= x"8D"; when x"2D6" => DATA <= x"21"; when x"2D7" => DATA <= x"03"; when x"2D8" => DATA <= x"68"; when x"2D9" => DATA <= x"20"; when x"2DA" => DATA <= x"7E"; when x"2DB" => DATA <= x"F3"; when x"2DC" => DATA <= x"68"; when x"2DD" => DATA <= x"20"; when x"2DE" => DATA <= x"76"; when x"2DF" => DATA <= x"F3"; when x"2E0" => DATA <= x"A0"; when x"2E1" => DATA <= x"00"; when x"2E2" => DATA <= x"C4"; when x"2E3" => DATA <= x"00"; when x"2E4" => DATA <= x"F0"; when x"2E5" => DATA <= x"09"; when x"2E6" => DATA <= x"B9"; when x"2E7" => DATA <= x"66"; when x"2E8" => DATA <= x"00"; when x"2E9" => DATA <= x"20"; when x"2EA" => DATA <= x"76"; when x"2EB" => DATA <= x"F3"; when x"2EC" => DATA <= x"C8"; when x"2ED" => DATA <= x"D0"; when x"2EE" => DATA <= x"F3"; when x"2EF" => DATA <= x"C0"; when x"2F0" => DATA <= x"03"; when x"2F1" => DATA <= x"F0"; when x"2F2" => DATA <= x"0C"; when x"2F3" => DATA <= x"20"; when x"2F4" => DATA <= x"79"; when x"2F5" => DATA <= x"F3"; when x"2F6" => DATA <= x"20"; when x"2F7" => DATA <= x"4C"; when x"2F8" => DATA <= x"CA"; when x"2F9" => DATA <= x"20"; when x"2FA" => DATA <= x"4C"; when x"2FB" => DATA <= x"CA"; when x"2FC" => DATA <= x"C8"; when x"2FD" => DATA <= x"D0"; when x"2FE" => DATA <= x"F0"; when x"2FF" => DATA <= x"A0"; when x"300" => DATA <= x"00"; when x"301" => DATA <= x"B1"; when x"302" => DATA <= x"05"; when x"303" => DATA <= x"C9"; when x"304" => DATA <= x"3B"; when x"305" => DATA <= x"F0"; when x"306" => DATA <= x"0A"; when x"307" => DATA <= x"C9"; when x"308" => DATA <= x"0D"; when x"309" => DATA <= x"F0"; when x"30A" => DATA <= x"06"; when x"30B" => DATA <= x"20"; when x"30C" => DATA <= x"4C"; when x"30D" => DATA <= x"CA"; when x"30E" => DATA <= x"C8"; when x"30F" => DATA <= x"D0"; when x"310" => DATA <= x"F0"; when x"311" => DATA <= x"20"; when x"312" => DATA <= x"54"; when x"313" => DATA <= x"CD"; when x"314" => DATA <= x"20"; when x"315" => DATA <= x"E4"; when x"316" => DATA <= x"C4"; when x"317" => DATA <= x"88"; when x"318" => DATA <= x"B1"; when x"319" => DATA <= x"05"; when x"31A" => DATA <= x"C8"; when x"31B" => DATA <= x"C9"; when x"31C" => DATA <= x"3B"; when x"31D" => DATA <= x"F0"; when x"31E" => DATA <= x"0C"; when x"31F" => DATA <= x"A5"; when x"320" => DATA <= x"06"; when x"321" => DATA <= x"C9"; when x"322" => DATA <= x"01"; when x"323" => DATA <= x"D0"; when x"324" => DATA <= x"03"; when x"325" => DATA <= x"4C"; when x"326" => DATA <= x"CF"; when x"327" => DATA <= x"C2"; when x"328" => DATA <= x"20"; when x"329" => DATA <= x"1D"; when x"32A" => DATA <= x"C5"; when x"32B" => DATA <= x"4C"; when x"32C" => DATA <= x"A1"; when x"32D" => DATA <= x"F2"; when x"32E" => DATA <= x"20"; when x"32F" => DATA <= x"91"; when x"330" => DATA <= x"F2"; when x"331" => DATA <= x"85"; when x"332" => DATA <= x"66"; when x"333" => DATA <= x"20"; when x"334" => DATA <= x"91"; when x"335" => DATA <= x"F2"; when x"336" => DATA <= x"C5"; when x"337" => DATA <= x"66"; when x"338" => DATA <= x"D0"; when x"339" => DATA <= x"10"; when x"33A" => DATA <= x"C9"; when x"33B" => DATA <= x"40"; when x"33C" => DATA <= x"90"; when x"33D" => DATA <= x"0C"; when x"33E" => DATA <= x"C9"; when x"33F" => DATA <= x"5B"; when x"340" => DATA <= x"B0"; when x"341" => DATA <= x"08"; when x"342" => DATA <= x"38"; when x"343" => DATA <= x"20"; when x"344" => DATA <= x"8E"; when x"345" => DATA <= x"F0"; when x"346" => DATA <= x"20"; when x"347" => DATA <= x"CB"; when x"348" => DATA <= x"C3"; when x"349" => DATA <= x"A0"; when x"34A" => DATA <= x"00"; when x"34B" => DATA <= x"AD"; when x"34C" => DATA <= x"31"; when x"34D" => DATA <= x"03"; when x"34E" => DATA <= x"91"; when x"34F" => DATA <= x"52"; when x"350" => DATA <= x"AD"; when x"351" => DATA <= x"4C"; when x"352" => DATA <= x"03"; when x"353" => DATA <= x"C8"; when x"354" => DATA <= x"91"; when x"355" => DATA <= x"52"; when x"356" => DATA <= x"A9"; when x"357" => DATA <= x"00"; when x"358" => DATA <= x"C8"; when x"359" => DATA <= x"91"; when x"35A" => DATA <= x"52"; when x"35B" => DATA <= x"C8"; when x"35C" => DATA <= x"91"; when x"35D" => DATA <= x"52"; when x"35E" => DATA <= x"D0"; when x"35F" => DATA <= x"36"; when x"360" => DATA <= x"20"; when x"361" => DATA <= x"91"; when x"362" => DATA <= x"F2"; when x"363" => DATA <= x"C9"; when x"364" => DATA <= x"3B"; when x"365" => DATA <= x"F0"; when x"366" => DATA <= x"04"; when x"367" => DATA <= x"C9"; when x"368" => DATA <= x"0D"; when x"369" => DATA <= x"D0"; when x"36A" => DATA <= x"F5"; when x"36B" => DATA <= x"AD"; when x"36C" => DATA <= x"31"; when x"36D" => DATA <= x"03"; when x"36E" => DATA <= x"85"; when x"36F" => DATA <= x"52"; when x"370" => DATA <= x"AD"; when x"371" => DATA <= x"4C"; when x"372" => DATA <= x"03"; when x"373" => DATA <= x"85"; when x"374" => DATA <= x"53"; when x"375" => DATA <= x"60"; when x"376" => DATA <= x"20"; when x"377" => DATA <= x"7E"; when x"378" => DATA <= x"F3"; when x"379" => DATA <= x"A9"; when x"37A" => DATA <= x"20"; when x"37B" => DATA <= x"4C"; when x"37C" => DATA <= x"4C"; when x"37D" => DATA <= x"CA"; when x"37E" => DATA <= x"A2"; when x"37F" => DATA <= x"FF"; when x"380" => DATA <= x"48"; when x"381" => DATA <= x"4A"; when x"382" => DATA <= x"4A"; when x"383" => DATA <= x"4A"; when x"384" => DATA <= x"4A"; when x"385" => DATA <= x"20"; when x"386" => DATA <= x"F9"; when x"387" => DATA <= x"C5"; when x"388" => DATA <= x"68"; when x"389" => DATA <= x"29"; when x"38A" => DATA <= x"0F"; when x"38B" => DATA <= x"4C"; when x"38C" => DATA <= x"F9"; when x"38D" => DATA <= x"C5"; when x"38E" => DATA <= x"A2"; when x"38F" => DATA <= x"00"; when x"390" => DATA <= x"86"; when x"391" => DATA <= x"00"; when x"392" => DATA <= x"86"; when x"393" => DATA <= x"64"; when x"394" => DATA <= x"86"; when x"395" => DATA <= x"65"; when x"396" => DATA <= x"20"; when x"397" => DATA <= x"91"; when x"398" => DATA <= x"F2"; when x"399" => DATA <= x"C9"; when x"39A" => DATA <= x"3A"; when x"39B" => DATA <= x"F0"; when x"39C" => DATA <= x"91"; when x"39D" => DATA <= x"C9"; when x"39E" => DATA <= x"3B"; when x"39F" => DATA <= x"F0"; when x"3A0" => DATA <= x"CA"; when x"3A1" => DATA <= x"C9"; when x"3A2" => DATA <= x"0D"; when x"3A3" => DATA <= x"F0"; when x"3A4" => DATA <= x"C6"; when x"3A5" => DATA <= x"C9"; when x"3A6" => DATA <= x"5C"; when x"3A7" => DATA <= x"F0"; when x"3A8" => DATA <= x"B7"; when x"3A9" => DATA <= x"A0"; when x"3AA" => DATA <= x"05"; when x"3AB" => DATA <= x"38"; when x"3AC" => DATA <= x"69"; when x"3AD" => DATA <= x"00"; when x"3AE" => DATA <= x"0A"; when x"3AF" => DATA <= x"0A"; when x"3B0" => DATA <= x"0A"; when x"3B1" => DATA <= x"0A"; when x"3B2" => DATA <= x"26"; when x"3B3" => DATA <= x"6A"; when x"3B4" => DATA <= x"26"; when x"3B5" => DATA <= x"69"; when x"3B6" => DATA <= x"88"; when x"3B7" => DATA <= x"D0"; when x"3B8" => DATA <= x"F8"; when x"3B9" => DATA <= x"E8"; when x"3BA" => DATA <= x"E0"; when x"3BB" => DATA <= x"03"; when x"3BC" => DATA <= x"D0"; when x"3BD" => DATA <= x"D8"; when x"3BE" => DATA <= x"06"; when x"3BF" => DATA <= x"6A"; when x"3C0" => DATA <= x"26"; when x"3C1" => DATA <= x"69"; when x"3C2" => DATA <= x"A2"; when x"3C3" => DATA <= x"40"; when x"3C4" => DATA <= x"A5"; when x"3C5" => DATA <= x"69"; when x"3C6" => DATA <= x"DD"; when x"3C7" => DATA <= x"54"; when x"3C8" => DATA <= x"F1"; when x"3C9" => DATA <= x"F0"; when x"3CA" => DATA <= x"04"; when x"3CB" => DATA <= x"CA"; when x"3CC" => DATA <= x"D0"; when x"3CD" => DATA <= x"F8"; when x"3CE" => DATA <= x"00"; when x"3CF" => DATA <= x"BC"; when x"3D0" => DATA <= x"94"; when x"3D1" => DATA <= x"F1"; when x"3D2" => DATA <= x"C4"; when x"3D3" => DATA <= x"6A"; when x"3D4" => DATA <= x"D0"; when x"3D5" => DATA <= x"F5"; when x"3D6" => DATA <= x"BD"; when x"3D7" => DATA <= x"10"; when x"3D8" => DATA <= x"F2"; when x"3D9" => DATA <= x"85"; when x"3DA" => DATA <= x"66"; when x"3DB" => DATA <= x"BC"; when x"3DC" => DATA <= x"50"; when x"3DD" => DATA <= x"F2"; when x"3DE" => DATA <= x"84"; when x"3DF" => DATA <= x"0F"; when x"3E0" => DATA <= x"66"; when x"3E1" => DATA <= x"64"; when x"3E2" => DATA <= x"66"; when x"3E3" => DATA <= x"65"; when x"3E4" => DATA <= x"88"; when x"3E5" => DATA <= x"D0"; when x"3E6" => DATA <= x"F9"; when x"3E7" => DATA <= x"A4"; when x"3E8" => DATA <= x"0F"; when x"3E9" => DATA <= x"C0"; when x"3EA" => DATA <= x"0D"; when x"3EB" => DATA <= x"D0"; when x"3EC" => DATA <= x"05"; when x"3ED" => DATA <= x"A2"; when x"3EE" => DATA <= x"00"; when x"3EF" => DATA <= x"4C"; when x"3F0" => DATA <= x"9B"; when x"3F1" => DATA <= x"F4"; when x"3F2" => DATA <= x"20"; when x"3F3" => DATA <= x"91"; when x"3F4" => DATA <= x"F2"; when x"3F5" => DATA <= x"C9"; when x"3F6" => DATA <= x"40"; when x"3F7" => DATA <= x"F0"; when x"3F8" => DATA <= x"5B"; when x"3F9" => DATA <= x"C9"; when x"3FA" => DATA <= x"28"; when x"3FB" => DATA <= x"F0"; when x"3FC" => DATA <= x"65"; when x"3FD" => DATA <= x"A2"; when x"3FE" => DATA <= x"01"; when x"3FF" => DATA <= x"C9"; when x"400" => DATA <= x"41"; when x"401" => DATA <= x"F0"; when x"402" => DATA <= x"EC"; when x"403" => DATA <= x"C6"; when x"404" => DATA <= x"03"; when x"405" => DATA <= x"20"; when x"406" => DATA <= x"8B"; when x"407" => DATA <= x"C7"; when x"408" => DATA <= x"20"; when x"409" => DATA <= x"91"; when x"40A" => DATA <= x"F2"; when x"40B" => DATA <= x"C9"; when x"40C" => DATA <= x"2C"; when x"40D" => DATA <= x"D0"; when x"40E" => DATA <= x"31"; when x"40F" => DATA <= x"20"; when x"410" => DATA <= x"91"; when x"411" => DATA <= x"F2"; when x"412" => DATA <= x"A4"; when x"413" => DATA <= x"25"; when x"414" => DATA <= x"F0"; when x"415" => DATA <= x"15"; when x"416" => DATA <= x"A2"; when x"417" => DATA <= x"09"; when x"418" => DATA <= x"C9"; when x"419" => DATA <= x"58"; when x"41A" => DATA <= x"F0"; when x"41B" => DATA <= x"7F"; when x"41C" => DATA <= x"CA"; when x"41D" => DATA <= x"C9"; when x"41E" => DATA <= x"59"; when x"41F" => DATA <= x"D0"; when x"420" => DATA <= x"79"; when x"421" => DATA <= x"A5"; when x"422" => DATA <= x"0F"; when x"423" => DATA <= x"C9"; when x"424" => DATA <= x"09"; when x"425" => DATA <= x"D0"; when x"426" => DATA <= x"74"; when x"427" => DATA <= x"A2"; when x"428" => DATA <= x"0E"; when x"429" => DATA <= x"D0"; when x"42A" => DATA <= x"70"; when x"42B" => DATA <= x"A2"; when x"42C" => DATA <= x"04"; when x"42D" => DATA <= x"C9"; when x"42E" => DATA <= x"58"; when x"42F" => DATA <= x"F0"; when x"430" => DATA <= x"6A"; when x"431" => DATA <= x"C9"; when x"432" => DATA <= x"59"; when x"433" => DATA <= x"D0"; when x"434" => DATA <= x"65"; when x"435" => DATA <= x"CA"; when x"436" => DATA <= x"A4"; when x"437" => DATA <= x"0F"; when x"438" => DATA <= x"C0"; when x"439" => DATA <= x"03"; when x"43A" => DATA <= x"B0"; when x"43B" => DATA <= x"5F"; when x"43C" => DATA <= x"A2"; when x"43D" => DATA <= x"08"; when x"43E" => DATA <= x"D0"; when x"43F" => DATA <= x"5B"; when x"440" => DATA <= x"C6"; when x"441" => DATA <= x"03"; when x"442" => DATA <= x"A2"; when x"443" => DATA <= x"02"; when x"444" => DATA <= x"A4"; when x"445" => DATA <= x"0F"; when x"446" => DATA <= x"C0"; when x"447" => DATA <= x"0C"; when x"448" => DATA <= x"F0"; when x"449" => DATA <= x"51"; when x"44A" => DATA <= x"A2"; when x"44B" => DATA <= x"05"; when x"44C" => DATA <= x"A5"; when x"44D" => DATA <= x"25"; when x"44E" => DATA <= x"F0"; when x"44F" => DATA <= x"4B"; when x"450" => DATA <= x"A2"; when x"451" => DATA <= x"0C"; when x"452" => DATA <= x"D0"; when x"453" => DATA <= x"47"; when x"454" => DATA <= x"20"; when x"455" => DATA <= x"8B"; when x"456" => DATA <= x"C7"; when x"457" => DATA <= x"A5"; when x"458" => DATA <= x"0F"; when x"459" => DATA <= x"A2"; when x"45A" => DATA <= x"06"; when x"45B" => DATA <= x"C9"; when x"45C" => DATA <= x"01"; when x"45D" => DATA <= x"F0"; when x"45E" => DATA <= x"3C"; when x"45F" => DATA <= x"E8"; when x"460" => DATA <= x"D0"; when x"461" => DATA <= x"39"; when x"462" => DATA <= x"20"; when x"463" => DATA <= x"8B"; when x"464" => DATA <= x"C7"; when x"465" => DATA <= x"20"; when x"466" => DATA <= x"91"; when x"467" => DATA <= x"F2"; when x"468" => DATA <= x"C9"; when x"469" => DATA <= x"29"; when x"46A" => DATA <= x"F0"; when x"46B" => DATA <= x"16"; when x"46C" => DATA <= x"C9"; when x"46D" => DATA <= x"2C"; when x"46E" => DATA <= x"D0"; when x"46F" => DATA <= x"2A"; when x"470" => DATA <= x"20"; when x"471" => DATA <= x"91"; when x"472" => DATA <= x"F2"; when x"473" => DATA <= x"C9"; when x"474" => DATA <= x"58"; when x"475" => DATA <= x"D0"; when x"476" => DATA <= x"23"; when x"477" => DATA <= x"20"; when x"478" => DATA <= x"91"; when x"479" => DATA <= x"F2"; when x"47A" => DATA <= x"C9"; when x"47B" => DATA <= x"29"; when x"47C" => DATA <= x"D0"; when x"47D" => DATA <= x"1C"; when x"47E" => DATA <= x"A2"; when x"47F" => DATA <= x"0B"; when x"480" => DATA <= x"D0"; when x"481" => DATA <= x"19"; when x"482" => DATA <= x"A2"; when x"483" => DATA <= x"0D"; when x"484" => DATA <= x"A5"; when x"485" => DATA <= x"0F"; when x"486" => DATA <= x"C9"; when x"487" => DATA <= x"0B"; when x"488" => DATA <= x"F0"; when x"489" => DATA <= x"11"; when x"48A" => DATA <= x"A2"; when x"48B" => DATA <= x"0A"; when x"48C" => DATA <= x"20"; when x"48D" => DATA <= x"91"; when x"48E" => DATA <= x"F2"; when x"48F" => DATA <= x"C9"; when x"490" => DATA <= x"2C"; when x"491" => DATA <= x"D0"; when x"492" => DATA <= x"07"; when x"493" => DATA <= x"20"; when x"494" => DATA <= x"91"; when x"495" => DATA <= x"F2"; when x"496" => DATA <= x"C9"; when x"497" => DATA <= x"59"; when x"498" => DATA <= x"F0"; when x"499" => DATA <= x"01"; when x"49A" => DATA <= x"00"; when x"49B" => DATA <= x"20"; when x"49C" => DATA <= x"60"; when x"49D" => DATA <= x"F3"; when x"49E" => DATA <= x"BD"; when x"49F" => DATA <= x"D5"; when x"4A0" => DATA <= x"F1"; when x"4A1" => DATA <= x"F0"; when x"4A2" => DATA <= x"04"; when x"4A3" => DATA <= x"25"; when x"4A4" => DATA <= x"64"; when x"4A5" => DATA <= x"D0"; when x"4A6" => DATA <= x"07"; when x"4A7" => DATA <= x"BD"; when x"4A8" => DATA <= x"E4"; when x"4A9" => DATA <= x"F1"; when x"4AA" => DATA <= x"25"; when x"4AB" => DATA <= x"65"; when x"4AC" => DATA <= x"F0"; when x"4AD" => DATA <= x"EC"; when x"4AE" => DATA <= x"18"; when x"4AF" => DATA <= x"BD"; when x"4B0" => DATA <= x"F3"; when x"4B1" => DATA <= x"F1"; when x"4B2" => DATA <= x"65"; when x"4B3" => DATA <= x"66"; when x"4B4" => DATA <= x"85"; when x"4B5" => DATA <= x"66"; when x"4B6" => DATA <= x"BD"; when x"4B7" => DATA <= x"02"; when x"4B8" => DATA <= x"F2"; when x"4B9" => DATA <= x"A2"; when x"4BA" => DATA <= x"00"; when x"4BB" => DATA <= x"86"; when x"4BC" => DATA <= x"04"; when x"4BD" => DATA <= x"A4"; when x"4BE" => DATA <= x"16"; when x"4BF" => DATA <= x"84"; when x"4C0" => DATA <= x"67"; when x"4C1" => DATA <= x"A4"; when x"4C2" => DATA <= x"25"; when x"4C3" => DATA <= x"84"; when x"4C4" => DATA <= x"68"; when x"4C5" => DATA <= x"C9"; when x"4C6" => DATA <= x"0F"; when x"4C7" => DATA <= x"F0"; when x"4C8" => DATA <= x"23"; when x"4C9" => DATA <= x"29"; when x"4CA" => DATA <= x"0F"; when x"4CB" => DATA <= x"A8"; when x"4CC" => DATA <= x"C8"; when x"4CD" => DATA <= x"84"; when x"4CE" => DATA <= x"00"; when x"4CF" => DATA <= x"C0"; when x"4D0" => DATA <= x"02"; when x"4D1" => DATA <= x"D0"; when x"4D2" => DATA <= x"04"; when x"4D3" => DATA <= x"A4"; when x"4D4" => DATA <= x"68"; when x"4D5" => DATA <= x"D0"; when x"4D6" => DATA <= x"C3"; when x"4D7" => DATA <= x"A0"; when x"4D8" => DATA <= x"00"; when x"4D9" => DATA <= x"B9"; when x"4DA" => DATA <= x"66"; when x"4DB" => DATA <= x"00"; when x"4DC" => DATA <= x"91"; when x"4DD" => DATA <= x"52"; when x"4DE" => DATA <= x"C8"; when x"4DF" => DATA <= x"EE"; when x"4E0" => DATA <= x"31"; when x"4E1" => DATA <= x"03"; when x"4E2" => DATA <= x"D0"; when x"4E3" => DATA <= x"03"; when x"4E4" => DATA <= x"EE"; when x"4E5" => DATA <= x"4C"; when x"4E6" => DATA <= x"03"; when x"4E7" => DATA <= x"C4"; when x"4E8" => DATA <= x"00"; when x"4E9" => DATA <= x"D0"; when x"4EA" => DATA <= x"EE"; when x"4EB" => DATA <= x"60"; when x"4EC" => DATA <= x"A9"; when x"4ED" => DATA <= x"02"; when x"4EE" => DATA <= x"85"; when x"4EF" => DATA <= x"00"; when x"4F0" => DATA <= x"38"; when x"4F1" => DATA <= x"A5"; when x"4F2" => DATA <= x"67"; when x"4F3" => DATA <= x"ED"; when x"4F4" => DATA <= x"31"; when x"4F5" => DATA <= x"03"; when x"4F6" => DATA <= x"85"; when x"4F7" => DATA <= x"67"; when x"4F8" => DATA <= x"A5"; when x"4F9" => DATA <= x"68"; when x"4FA" => DATA <= x"ED"; when x"4FB" => DATA <= x"4C"; when x"4FC" => DATA <= x"03"; when x"4FD" => DATA <= x"85"; when x"4FE" => DATA <= x"68"; when x"4FF" => DATA <= x"38"; when x"500" => DATA <= x"A5"; when x"501" => DATA <= x"67"; when x"502" => DATA <= x"E9"; when x"503" => DATA <= x"02"; when x"504" => DATA <= x"85"; when x"505" => DATA <= x"67"; when x"506" => DATA <= x"A8"; when x"507" => DATA <= x"A5"; when x"508" => DATA <= x"68"; when x"509" => DATA <= x"E9"; when x"50A" => DATA <= x"00"; when x"50B" => DATA <= x"F0"; when x"50C" => DATA <= x"1F"; when x"50D" => DATA <= x"C9"; when x"50E" => DATA <= x"FF"; when x"50F" => DATA <= x"F0"; when x"510" => DATA <= x"16"; when x"511" => DATA <= x"20"; when x"512" => DATA <= x"D1"; when x"513" => DATA <= x"F7"; when x"514" => DATA <= x"4F"; when x"515" => DATA <= x"55"; when x"516" => DATA <= x"54"; when x"517" => DATA <= x"20"; when x"518" => DATA <= x"4F"; when x"519" => DATA <= x"46"; when x"51A" => DATA <= x"20"; when x"51B" => DATA <= x"52"; when x"51C" => DATA <= x"41"; when x"51D" => DATA <= x"4E"; when x"51E" => DATA <= x"47"; when x"51F" => DATA <= x"45"; when x"520" => DATA <= x"3A"; when x"521" => DATA <= x"0A"; when x"522" => DATA <= x"0D"; when x"523" => DATA <= x"84"; when x"524" => DATA <= x"67"; when x"525" => DATA <= x"30"; when x"526" => DATA <= x"B0"; when x"527" => DATA <= x"98"; when x"528" => DATA <= x"30"; when x"529" => DATA <= x"AD"; when x"52A" => DATA <= x"10"; when x"52B" => DATA <= x"E5"; when x"52C" => DATA <= x"98"; when x"52D" => DATA <= x"10"; when x"52E" => DATA <= x"A8"; when x"52F" => DATA <= x"30"; when x"530" => DATA <= x"E0"; when x"531" => DATA <= x"20"; when x"532" => DATA <= x"E4"; when x"533" => DATA <= x"C4"; when x"534" => DATA <= x"88"; when x"535" => DATA <= x"84"; when x"536" => DATA <= x"52"; when x"537" => DATA <= x"A5"; when x"538" => DATA <= x"12"; when x"539" => DATA <= x"85"; when x"53A" => DATA <= x"53"; when x"53B" => DATA <= x"98"; when x"53C" => DATA <= x"C8"; when x"53D" => DATA <= x"91"; when x"53E" => DATA <= x"52"; when x"53F" => DATA <= x"4C"; when x"540" => DATA <= x"9B"; when x"541" => DATA <= x"CD"; when x"542" => DATA <= x"A2"; when x"543" => DATA <= x"05"; when x"544" => DATA <= x"D0"; when x"545" => DATA <= x"02"; when x"546" => DATA <= x"A2"; when x"547" => DATA <= x"0C"; when x"548" => DATA <= x"86"; when x"549" => DATA <= x"16"; when x"54A" => DATA <= x"E6"; when x"54B" => DATA <= x"04"; when x"54C" => DATA <= x"D0"; when x"54D" => DATA <= x"06"; when x"54E" => DATA <= x"20"; when x"54F" => DATA <= x"BC"; when x"550" => DATA <= x"C8"; when x"551" => DATA <= x"20"; when x"552" => DATA <= x"31"; when x"553" => DATA <= x"C2"; when x"554" => DATA <= x"20"; when x"555" => DATA <= x"BC"; when x"556" => DATA <= x"C8"; when x"557" => DATA <= x"20"; when x"558" => DATA <= x"31"; when x"559" => DATA <= x"C2"; when x"55A" => DATA <= x"20"; when x"55B" => DATA <= x"BC"; when x"55C" => DATA <= x"C8"; when x"55D" => DATA <= x"20"; when x"55E" => DATA <= x"E4"; when x"55F" => DATA <= x"C4"; when x"560" => DATA <= x"B5"; when x"561" => DATA <= x"15"; when x"562" => DATA <= x"85"; when x"563" => DATA <= x"5C"; when x"564" => DATA <= x"B5"; when x"565" => DATA <= x"24"; when x"566" => DATA <= x"85"; when x"567" => DATA <= x"5D"; when x"568" => DATA <= x"B5"; when x"569" => DATA <= x"14"; when x"56A" => DATA <= x"85"; when x"56B" => DATA <= x"5A"; when x"56C" => DATA <= x"B5"; when x"56D" => DATA <= x"23"; when x"56E" => DATA <= x"85"; when x"56F" => DATA <= x"5B"; when x"570" => DATA <= x"A2"; when x"571" => DATA <= x"00"; when x"572" => DATA <= x"86"; when x"573" => DATA <= x"04"; when x"574" => DATA <= x"A2"; when x"575" => DATA <= x"03"; when x"576" => DATA <= x"BD"; when x"577" => DATA <= x"C1"; when x"578" => DATA <= x"03"; when x"579" => DATA <= x"95"; when x"57A" => DATA <= x"52"; when x"57B" => DATA <= x"CA"; when x"57C" => DATA <= x"10"; when x"57D" => DATA <= x"F8"; when x"57E" => DATA <= x"A5"; when x"57F" => DATA <= x"16"; when x"580" => DATA <= x"29"; when x"581" => DATA <= x"04"; when x"582" => DATA <= x"D0"; when x"583" => DATA <= x"13"; when x"584" => DATA <= x"A2"; when x"585" => DATA <= x"02"; when x"586" => DATA <= x"18"; when x"587" => DATA <= x"B5"; when x"588" => DATA <= x"5A"; when x"589" => DATA <= x"75"; when x"58A" => DATA <= x"52"; when x"58B" => DATA <= x"95"; when x"58C" => DATA <= x"5A"; when x"58D" => DATA <= x"B5"; when x"58E" => DATA <= x"5B"; when x"58F" => DATA <= x"75"; when x"590" => DATA <= x"53"; when x"591" => DATA <= x"95"; when x"592" => DATA <= x"5B"; when x"593" => DATA <= x"CA"; when x"594" => DATA <= x"CA"; when x"595" => DATA <= x"10"; when x"596" => DATA <= x"EF"; when x"597" => DATA <= x"A2"; when x"598" => DATA <= x"03"; when x"599" => DATA <= x"B5"; when x"59A" => DATA <= x"5A"; when x"59B" => DATA <= x"9D"; when x"59C" => DATA <= x"C1"; when x"59D" => DATA <= x"03"; when x"59E" => DATA <= x"CA"; when x"59F" => DATA <= x"10"; when x"5A0" => DATA <= x"F8"; when x"5A1" => DATA <= x"A5"; when x"5A2" => DATA <= x"16"; when x"5A3" => DATA <= x"29"; when x"5A4" => DATA <= x"03"; when x"5A5" => DATA <= x"F0"; when x"5A6" => DATA <= x"0B"; when x"5A7" => DATA <= x"85"; when x"5A8" => DATA <= x"5E"; when x"5A9" => DATA <= x"A5"; when x"5AA" => DATA <= x"16"; when x"5AB" => DATA <= x"29"; when x"5AC" => DATA <= x"08"; when x"5AD" => DATA <= x"F0"; when x"5AE" => DATA <= x"06"; when x"5AF" => DATA <= x"20"; when x"5B0" => DATA <= x"78"; when x"5B1" => DATA <= x"F6"; when x"5B2" => DATA <= x"4C"; when x"5B3" => DATA <= x"5B"; when x"5B4" => DATA <= x"C5"; when x"5B5" => DATA <= x"A2"; when x"5B6" => DATA <= x"02"; when x"5B7" => DATA <= x"38"; when x"5B8" => DATA <= x"B5"; when x"5B9" => DATA <= x"5A"; when x"5BA" => DATA <= x"F5"; when x"5BB" => DATA <= x"52"; when x"5BC" => DATA <= x"B4"; when x"5BD" => DATA <= x"52"; when x"5BE" => DATA <= x"94"; when x"5BF" => DATA <= x"5A"; when x"5C0" => DATA <= x"95"; when x"5C1" => DATA <= x"52"; when x"5C2" => DATA <= x"B4"; when x"5C3" => DATA <= x"53"; when x"5C4" => DATA <= x"B5"; when x"5C5" => DATA <= x"5B"; when x"5C6" => DATA <= x"F5"; when x"5C7" => DATA <= x"53"; when x"5C8" => DATA <= x"94"; when x"5C9" => DATA <= x"5B"; when x"5CA" => DATA <= x"95"; when x"5CB" => DATA <= x"53"; when x"5CC" => DATA <= x"95"; when x"5CD" => DATA <= x"56"; when x"5CE" => DATA <= x"10"; when x"5CF" => DATA <= x"0D"; when x"5D0" => DATA <= x"A9"; when x"5D1" => DATA <= x"00"; when x"5D2" => DATA <= x"38"; when x"5D3" => DATA <= x"F5"; when x"5D4" => DATA <= x"52"; when x"5D5" => DATA <= x"95"; when x"5D6" => DATA <= x"52"; when x"5D7" => DATA <= x"A9"; when x"5D8" => DATA <= x"00"; when x"5D9" => DATA <= x"F5"; when x"5DA" => DATA <= x"53"; when x"5DB" => DATA <= x"95"; when x"5DC" => DATA <= x"53"; when x"5DD" => DATA <= x"CA"; when x"5DE" => DATA <= x"CA"; when x"5DF" => DATA <= x"10"; when x"5E0" => DATA <= x"D6"; when x"5E1" => DATA <= x"A5"; when x"5E2" => DATA <= x"54"; when x"5E3" => DATA <= x"C5"; when x"5E4" => DATA <= x"52"; when x"5E5" => DATA <= x"A5"; when x"5E6" => DATA <= x"55"; when x"5E7" => DATA <= x"E5"; when x"5E8" => DATA <= x"53"; when x"5E9" => DATA <= x"90"; when x"5EA" => DATA <= x"31"; when x"5EB" => DATA <= x"A9"; when x"5EC" => DATA <= x"00"; when x"5ED" => DATA <= x"E5"; when x"5EE" => DATA <= x"54"; when x"5EF" => DATA <= x"85"; when x"5F0" => DATA <= x"57"; when x"5F1" => DATA <= x"A9"; when x"5F2" => DATA <= x"00"; when x"5F3" => DATA <= x"E5"; when x"5F4" => DATA <= x"55"; when x"5F5" => DATA <= x"38"; when x"5F6" => DATA <= x"6A"; when x"5F7" => DATA <= x"85"; when x"5F8" => DATA <= x"59"; when x"5F9" => DATA <= x"66"; when x"5FA" => DATA <= x"57"; when x"5FB" => DATA <= x"20"; when x"5FC" => DATA <= x"78"; when x"5FD" => DATA <= x"F6"; when x"5FE" => DATA <= x"A5"; when x"5FF" => DATA <= x"5C"; when x"600" => DATA <= x"CD"; when x"601" => DATA <= x"C3"; when x"602" => DATA <= x"03"; when x"603" => DATA <= x"D0"; when x"604" => DATA <= x"0A"; when x"605" => DATA <= x"A5"; when x"606" => DATA <= x"5D"; when x"607" => DATA <= x"CD"; when x"608" => DATA <= x"C4"; when x"609" => DATA <= x"03"; when x"60A" => DATA <= x"D0"; when x"60B" => DATA <= x"03"; when x"60C" => DATA <= x"4C"; when x"60D" => DATA <= x"5B"; when x"60E" => DATA <= x"C5"; when x"60F" => DATA <= x"20"; when x"610" => DATA <= x"55"; when x"611" => DATA <= x"F6"; when x"612" => DATA <= x"A5"; when x"613" => DATA <= x"59"; when x"614" => DATA <= x"30"; when x"615" => DATA <= x"E5"; when x"616" => DATA <= x"20"; when x"617" => DATA <= x"44"; when x"618" => DATA <= x"F6"; when x"619" => DATA <= x"4C"; when x"61A" => DATA <= x"FB"; when x"61B" => DATA <= x"F5"; when x"61C" => DATA <= x"A5"; when x"61D" => DATA <= x"53"; when x"61E" => DATA <= x"4A"; when x"61F" => DATA <= x"85"; when x"620" => DATA <= x"59"; when x"621" => DATA <= x"A5"; when x"622" => DATA <= x"52"; when x"623" => DATA <= x"6A"; when x"624" => DATA <= x"85"; when x"625" => DATA <= x"57"; when x"626" => DATA <= x"20"; when x"627" => DATA <= x"78"; when x"628" => DATA <= x"F6"; when x"629" => DATA <= x"A5"; when x"62A" => DATA <= x"5A"; when x"62B" => DATA <= x"CD"; when x"62C" => DATA <= x"C1"; when x"62D" => DATA <= x"03"; when x"62E" => DATA <= x"D0"; when x"62F" => DATA <= x"07"; when x"630" => DATA <= x"A5"; when x"631" => DATA <= x"5B"; when x"632" => DATA <= x"CD"; when x"633" => DATA <= x"C2"; when x"634" => DATA <= x"03"; when x"635" => DATA <= x"F0"; when x"636" => DATA <= x"D5"; when x"637" => DATA <= x"20"; when x"638" => DATA <= x"44"; when x"639" => DATA <= x"F6"; when x"63A" => DATA <= x"A5"; when x"63B" => DATA <= x"59"; when x"63C" => DATA <= x"10"; when x"63D" => DATA <= x"E8"; when x"63E" => DATA <= x"20"; when x"63F" => DATA <= x"55"; when x"640" => DATA <= x"F6"; when x"641" => DATA <= x"4C"; when x"642" => DATA <= x"26"; when x"643" => DATA <= x"F6"; when x"644" => DATA <= x"38"; when x"645" => DATA <= x"A5"; when x"646" => DATA <= x"57"; when x"647" => DATA <= x"E5"; when x"648" => DATA <= x"54"; when x"649" => DATA <= x"85"; when x"64A" => DATA <= x"57"; when x"64B" => DATA <= x"A5"; when x"64C" => DATA <= x"59"; when x"64D" => DATA <= x"E5"; when x"64E" => DATA <= x"55"; when x"64F" => DATA <= x"85"; when x"650" => DATA <= x"59"; when x"651" => DATA <= x"A2"; when x"652" => DATA <= x"00"; when x"653" => DATA <= x"F0"; when x"654" => DATA <= x"0F"; when x"655" => DATA <= x"18"; when x"656" => DATA <= x"A5"; when x"657" => DATA <= x"57"; when x"658" => DATA <= x"65"; when x"659" => DATA <= x"52"; when x"65A" => DATA <= x"85"; when x"65B" => DATA <= x"57"; when x"65C" => DATA <= x"A5"; when x"65D" => DATA <= x"59"; when x"65E" => DATA <= x"65"; when x"65F" => DATA <= x"53"; when x"660" => DATA <= x"85"; when x"661" => DATA <= x"59"; when x"662" => DATA <= x"A2"; when x"663" => DATA <= x"02"; when x"664" => DATA <= x"B5"; when x"665" => DATA <= x"56"; when x"666" => DATA <= x"10"; when x"667" => DATA <= x"09"; when x"668" => DATA <= x"B5"; when x"669" => DATA <= x"5A"; when x"66A" => DATA <= x"D0"; when x"66B" => DATA <= x"02"; when x"66C" => DATA <= x"D6"; when x"66D" => DATA <= x"5B"; when x"66E" => DATA <= x"D6"; when x"66F" => DATA <= x"5A"; when x"670" => DATA <= x"60"; when x"671" => DATA <= x"F6"; when x"672" => DATA <= x"5A"; when x"673" => DATA <= x"D0"; when x"674" => DATA <= x"FB"; when x"675" => DATA <= x"F6"; when x"676" => DATA <= x"5B"; when x"677" => DATA <= x"60"; when x"678" => DATA <= x"6C"; when x"679" => DATA <= x"FE"; when x"67A" => DATA <= x"03"; when x"67B" => DATA <= x"20"; when x"67C" => DATA <= x"C8"; when x"67D" => DATA <= x"C3"; when x"67E" => DATA <= x"A0"; when x"67F" => DATA <= x"00"; when x"680" => DATA <= x"A5"; when x"681" => DATA <= x"52"; when x"682" => DATA <= x"F0"; when x"683" => DATA <= x"3E"; when x"684" => DATA <= x"C9"; when x"685" => DATA <= x"05"; when x"686" => DATA <= x"90"; when x"687" => DATA <= x"02"; when x"688" => DATA <= x"A9"; when x"689" => DATA <= x"04"; when x"68A" => DATA <= x"A2"; when x"68B" => DATA <= x"80"; when x"68C" => DATA <= x"86"; when x"68D" => DATA <= x"54"; when x"68E" => DATA <= x"84"; when x"68F" => DATA <= x"53"; when x"690" => DATA <= x"85"; when x"691" => DATA <= x"52"; when x"692" => DATA <= x"AA"; when x"693" => DATA <= x"BD"; when x"694" => DATA <= x"CE"; when x"695" => DATA <= x"F6"; when x"696" => DATA <= x"A6"; when x"697" => DATA <= x"12"; when x"698" => DATA <= x"10"; when x"699" => DATA <= x"04"; when x"69A" => DATA <= x"C5"; when x"69B" => DATA <= x"12"; when x"69C" => DATA <= x"B0"; when x"69D" => DATA <= x"E1"; when x"69E" => DATA <= x"AA"; when x"69F" => DATA <= x"98"; when x"6A0" => DATA <= x"91"; when x"6A1" => DATA <= x"53"; when x"6A2" => DATA <= x"88"; when x"6A3" => DATA <= x"D0"; when x"6A4" => DATA <= x"FB"; when x"6A5" => DATA <= x"E6"; when x"6A6" => DATA <= x"54"; when x"6A7" => DATA <= x"E4"; when x"6A8" => DATA <= x"54"; when x"6A9" => DATA <= x"D0"; when x"6AA" => DATA <= x"F5"; when x"6AB" => DATA <= x"A4"; when x"6AC" => DATA <= x"52"; when x"6AD" => DATA <= x"B9"; when x"6AE" => DATA <= x"D8"; when x"6AF" => DATA <= x"F6"; when x"6B0" => DATA <= x"8D"; when x"6B1" => DATA <= x"FF"; when x"6B2" => DATA <= x"03"; when x"6B3" => DATA <= x"B9"; when x"6B4" => DATA <= x"D3"; when x"6B5" => DATA <= x"F6"; when x"6B6" => DATA <= x"8D"; when x"6B7" => DATA <= x"FE"; when x"6B8" => DATA <= x"03"; when x"6B9" => DATA <= x"B9"; when x"6BA" => DATA <= x"DD"; when x"6BB" => DATA <= x"F6"; when x"6BC" => DATA <= x"8D"; when x"6BD" => DATA <= x"00"; when x"6BE" => DATA <= x"B0"; when x"6BF" => DATA <= x"4C"; when x"6C0" => DATA <= x"58"; when x"6C1" => DATA <= x"C5"; when x"6C2" => DATA <= x"A9"; when x"6C3" => DATA <= x"40"; when x"6C4" => DATA <= x"99"; when x"6C5" => DATA <= x"00"; when x"6C6" => DATA <= x"80"; when x"6C7" => DATA <= x"99"; when x"6C8" => DATA <= x"00"; when x"6C9" => DATA <= x"81"; when x"6CA" => DATA <= x"88"; when x"6CB" => DATA <= x"D0"; when x"6CC" => DATA <= x"F7"; when x"6CD" => DATA <= x"F0"; when x"6CE" => DATA <= x"DC"; when x"6CF" => DATA <= x"84"; when x"6D0" => DATA <= x"86"; when x"6D1" => DATA <= x"8C"; when x"6D2" => DATA <= x"98"; when x"6D3" => DATA <= x"E2"; when x"6D4" => DATA <= x"3B"; when x"6D5" => DATA <= x"54"; when x"6D6" => DATA <= x"6D"; when x"6D7" => DATA <= x"AA"; when x"6D8" => DATA <= x"F6"; when x"6D9" => DATA <= x"F7"; when x"6DA" => DATA <= x"F7"; when x"6DB" => DATA <= x"F7"; when x"6DC" => DATA <= x"F7"; when x"6DD" => DATA <= x"00"; when x"6DE" => DATA <= x"30"; when x"6DF" => DATA <= x"70"; when x"6E0" => DATA <= x"B0"; when x"6E1" => DATA <= x"F0"; when x"6E2" => DATA <= x"A5"; when x"6E3" => DATA <= x"5B"; when x"6E4" => DATA <= x"05"; when x"6E5" => DATA <= x"5D"; when x"6E6" => DATA <= x"D0"; when x"6E7" => DATA <= x"52"; when x"6E8" => DATA <= x"A5"; when x"6E9" => DATA <= x"5A"; when x"6EA" => DATA <= x"C9"; when x"6EB" => DATA <= x"40"; when x"6EC" => DATA <= x"B0"; when x"6ED" => DATA <= x"4C"; when x"6EE" => DATA <= x"4A"; when x"6EF" => DATA <= x"85"; when x"6F0" => DATA <= x"5F"; when x"6F1" => DATA <= x"A9"; when x"6F2" => DATA <= x"2F"; when x"6F3" => DATA <= x"38"; when x"6F4" => DATA <= x"E5"; when x"6F5" => DATA <= x"5C"; when x"6F6" => DATA <= x"C9"; when x"6F7" => DATA <= x"30"; when x"6F8" => DATA <= x"B0"; when x"6F9" => DATA <= x"40"; when x"6FA" => DATA <= x"A2"; when x"6FB" => DATA <= x"FF"; when x"6FC" => DATA <= x"38"; when x"6FD" => DATA <= x"E8"; when x"6FE" => DATA <= x"E9"; when x"6FF" => DATA <= x"03"; when x"700" => DATA <= x"B0"; when x"701" => DATA <= x"FB"; when x"702" => DATA <= x"69"; when x"703" => DATA <= x"03"; when x"704" => DATA <= x"85"; when x"705" => DATA <= x"61"; when x"706" => DATA <= x"8A"; when x"707" => DATA <= x"0A"; when x"708" => DATA <= x"0A"; when x"709" => DATA <= x"0A"; when x"70A" => DATA <= x"0A"; when x"70B" => DATA <= x"0A"; when x"70C" => DATA <= x"05"; when x"70D" => DATA <= x"5F"; when x"70E" => DATA <= x"85"; when x"70F" => DATA <= x"5F"; when x"710" => DATA <= x"A9"; when x"711" => DATA <= x"80"; when x"712" => DATA <= x"69"; when x"713" => DATA <= x"00"; when x"714" => DATA <= x"85"; when x"715" => DATA <= x"60"; when x"716" => DATA <= x"A5"; when x"717" => DATA <= x"5A"; when x"718" => DATA <= x"4A"; when x"719" => DATA <= x"A5"; when x"71A" => DATA <= x"61"; when x"71B" => DATA <= x"2A"; when x"71C" => DATA <= x"A8"; when x"71D" => DATA <= x"B9"; when x"71E" => DATA <= x"CB"; when x"71F" => DATA <= x"F7"; when x"720" => DATA <= x"A0"; when x"721" => DATA <= x"00"; when x"722" => DATA <= x"A6"; when x"723" => DATA <= x"5E"; when x"724" => DATA <= x"CA"; when x"725" => DATA <= x"F0"; when x"726" => DATA <= x"0F"; when x"727" => DATA <= x"CA"; when x"728" => DATA <= x"F0"; when x"729" => DATA <= x"07"; when x"72A" => DATA <= x"49"; when x"72B" => DATA <= x"FF"; when x"72C" => DATA <= x"31"; when x"72D" => DATA <= x"5F"; when x"72E" => DATA <= x"91"; when x"72F" => DATA <= x"5F"; when x"730" => DATA <= x"60"; when x"731" => DATA <= x"51"; when x"732" => DATA <= x"5F"; when x"733" => DATA <= x"91"; when x"734" => DATA <= x"5F"; when x"735" => DATA <= x"60"; when x"736" => DATA <= x"11"; when x"737" => DATA <= x"5F"; when x"738" => DATA <= x"91"; when x"739" => DATA <= x"5F"; when x"73A" => DATA <= x"60"; when x"73B" => DATA <= x"A5"; when x"73C" => DATA <= x"5B"; when x"73D" => DATA <= x"05"; when x"73E" => DATA <= x"5D"; when x"73F" => DATA <= x"D0"; when x"740" => DATA <= x"F9"; when x"741" => DATA <= x"A5"; when x"742" => DATA <= x"5A"; when x"743" => DATA <= x"30"; when x"744" => DATA <= x"F5"; when x"745" => DATA <= x"4A"; when x"746" => DATA <= x"4A"; when x"747" => DATA <= x"4A"; when x"748" => DATA <= x"85"; when x"749" => DATA <= x"5F"; when x"74A" => DATA <= x"A9"; when x"74B" => DATA <= x"3F"; when x"74C" => DATA <= x"38"; when x"74D" => DATA <= x"E5"; when x"74E" => DATA <= x"5C"; when x"74F" => DATA <= x"C9"; when x"750" => DATA <= x"40"; when x"751" => DATA <= x"90"; when x"752" => DATA <= x"32"; when x"753" => DATA <= x"60"; when x"754" => DATA <= x"A5"; when x"755" => DATA <= x"5B"; when x"756" => DATA <= x"05"; when x"757" => DATA <= x"5D"; when x"758" => DATA <= x"D0"; when x"759" => DATA <= x"E0"; when x"75A" => DATA <= x"A5"; when x"75B" => DATA <= x"5A"; when x"75C" => DATA <= x"30"; when x"75D" => DATA <= x"DC"; when x"75E" => DATA <= x"4A"; when x"75F" => DATA <= x"4A"; when x"760" => DATA <= x"4A"; when x"761" => DATA <= x"85"; when x"762" => DATA <= x"5F"; when x"763" => DATA <= x"A9"; when x"764" => DATA <= x"5F"; when x"765" => DATA <= x"38"; when x"766" => DATA <= x"E5"; when x"767" => DATA <= x"5C"; when x"768" => DATA <= x"C9"; when x"769" => DATA <= x"60"; when x"76A" => DATA <= x"90"; when x"76B" => DATA <= x"19"; when x"76C" => DATA <= x"60"; when x"76D" => DATA <= x"A5"; when x"76E" => DATA <= x"5B"; when x"76F" => DATA <= x"05"; when x"770" => DATA <= x"5D"; when x"771" => DATA <= x"D0"; when x"772" => DATA <= x"C7"; when x"773" => DATA <= x"A5"; when x"774" => DATA <= x"5A"; when x"775" => DATA <= x"30"; when x"776" => DATA <= x"C3"; when x"777" => DATA <= x"4A"; when x"778" => DATA <= x"4A"; when x"779" => DATA <= x"4A"; when x"77A" => DATA <= x"85"; when x"77B" => DATA <= x"5F"; when x"77C" => DATA <= x"A9"; when x"77D" => DATA <= x"BF"; when x"77E" => DATA <= x"38"; when x"77F" => DATA <= x"E5"; when x"780" => DATA <= x"5C"; when x"781" => DATA <= x"C9"; when x"782" => DATA <= x"C0"; when x"783" => DATA <= x"B0"; when x"784" => DATA <= x"B5"; when x"785" => DATA <= x"A0"; when x"786" => DATA <= x"00"; when x"787" => DATA <= x"84"; when x"788" => DATA <= x"60"; when x"789" => DATA <= x"0A"; when x"78A" => DATA <= x"26"; when x"78B" => DATA <= x"60"; when x"78C" => DATA <= x"0A"; when x"78D" => DATA <= x"26"; when x"78E" => DATA <= x"60"; when x"78F" => DATA <= x"0A"; when x"790" => DATA <= x"26"; when x"791" => DATA <= x"60"; when x"792" => DATA <= x"0A"; when x"793" => DATA <= x"26"; when x"794" => DATA <= x"60"; when x"795" => DATA <= x"65"; when x"796" => DATA <= x"5F"; when x"797" => DATA <= x"85"; when x"798" => DATA <= x"5F"; when x"799" => DATA <= x"A5"; when x"79A" => DATA <= x"60"; when x"79B" => DATA <= x"69"; when x"79C" => DATA <= x"80"; when x"79D" => DATA <= x"85"; when x"79E" => DATA <= x"60"; when x"79F" => DATA <= x"A5"; when x"7A0" => DATA <= x"5A"; when x"7A1" => DATA <= x"29"; when x"7A2" => DATA <= x"07"; when x"7A3" => DATA <= x"A8"; when x"7A4" => DATA <= x"B9"; when x"7A5" => DATA <= x"C9"; when x"7A6" => DATA <= x"F7"; when x"7A7" => DATA <= x"4C"; when x"7A8" => DATA <= x"20"; when x"7A9" => DATA <= x"F7"; when x"7AA" => DATA <= x"A5"; when x"7AB" => DATA <= x"5B"; when x"7AC" => DATA <= x"05"; when x"7AD" => DATA <= x"5D"; when x"7AE" => DATA <= x"D0"; when x"7AF" => DATA <= x"BC"; when x"7B0" => DATA <= x"A5"; when x"7B1" => DATA <= x"5A"; when x"7B2" => DATA <= x"4A"; when x"7B3" => DATA <= x"4A"; when x"7B4" => DATA <= x"4A"; when x"7B5" => DATA <= x"85"; when x"7B6" => DATA <= x"5F"; when x"7B7" => DATA <= x"A9"; when x"7B8" => DATA <= x"BF"; when x"7B9" => DATA <= x"38"; when x"7BA" => DATA <= x"E5"; when x"7BB" => DATA <= x"5C"; when x"7BC" => DATA <= x"C9"; when x"7BD" => DATA <= x"C0"; when x"7BE" => DATA <= x"B0"; when x"7BF" => DATA <= x"AC"; when x"7C0" => DATA <= x"A0"; when x"7C1" => DATA <= x"00"; when x"7C2" => DATA <= x"84"; when x"7C3" => DATA <= x"60"; when x"7C4" => DATA <= x"0A"; when x"7C5" => DATA <= x"26"; when x"7C6" => DATA <= x"60"; when x"7C7" => DATA <= x"10"; when x"7C8" => DATA <= x"C0"; when x"7C9" => DATA <= x"80"; when x"7CA" => DATA <= x"40"; when x"7CB" => DATA <= x"20"; when x"7CC" => DATA <= x"10"; when x"7CD" => DATA <= x"08"; when x"7CE" => DATA <= x"04"; when x"7CF" => DATA <= x"02"; when x"7D0" => DATA <= x"01"; when x"7D1" => DATA <= x"68"; when x"7D2" => DATA <= x"85"; when x"7D3" => DATA <= x"E8"; when x"7D4" => DATA <= x"68"; when x"7D5" => DATA <= x"85"; when x"7D6" => DATA <= x"E9"; when x"7D7" => DATA <= x"A0"; when x"7D8" => DATA <= x"00"; when x"7D9" => DATA <= x"E6"; when x"7DA" => DATA <= x"E8"; when x"7DB" => DATA <= x"D0"; when x"7DC" => DATA <= x"02"; when x"7DD" => DATA <= x"E6"; when x"7DE" => DATA <= x"E9"; when x"7DF" => DATA <= x"B1"; when x"7E0" => DATA <= x"E8"; when x"7E1" => DATA <= x"30"; when x"7E2" => DATA <= x"06"; when x"7E3" => DATA <= x"20"; when x"7E4" => DATA <= x"F4"; when x"7E5" => DATA <= x"FF"; when x"7E6" => DATA <= x"4C"; when x"7E7" => DATA <= x"D7"; when x"7E8" => DATA <= x"F7"; when x"7E9" => DATA <= x"6C"; when x"7EA" => DATA <= x"E8"; when x"7EB" => DATA <= x"00"; when x"7EC" => DATA <= x"A2"; when x"7ED" => DATA <= x"D4"; when x"7EE" => DATA <= x"20"; when x"7EF" => DATA <= x"F1"; when x"7F0" => DATA <= x"F7"; when x"7F1" => DATA <= x"B5"; when x"7F2" => DATA <= x"01"; when x"7F3" => DATA <= x"20"; when x"7F4" => DATA <= x"02"; when x"7F5" => DATA <= x"F8"; when x"7F6" => DATA <= x"E8"; when x"7F7" => DATA <= x"E8"; when x"7F8" => DATA <= x"B5"; when x"7F9" => DATA <= x"FE"; when x"7FA" => DATA <= x"20"; when x"7FB" => DATA <= x"02"; when x"7FC" => DATA <= x"F8"; when x"7FD" => DATA <= x"A9"; when x"7FE" => DATA <= x"20"; when x"7FF" => DATA <= x"4C"; when x"800" => DATA <= x"F4"; when x"801" => DATA <= x"FF"; when x"802" => DATA <= x"48"; when x"803" => DATA <= x"4A"; when x"804" => DATA <= x"4A"; when x"805" => DATA <= x"4A"; when x"806" => DATA <= x"4A"; when x"807" => DATA <= x"20"; when x"808" => DATA <= x"0B"; when x"809" => DATA <= x"F8"; when x"80A" => DATA <= x"68"; when x"80B" => DATA <= x"29"; when x"80C" => DATA <= x"0F"; when x"80D" => DATA <= x"C9"; when x"80E" => DATA <= x"0A"; when x"80F" => DATA <= x"90"; when x"810" => DATA <= x"02"; when x"811" => DATA <= x"69"; when x"812" => DATA <= x"06"; when x"813" => DATA <= x"69"; when x"814" => DATA <= x"30"; when x"815" => DATA <= x"4C"; when x"816" => DATA <= x"F4"; when x"817" => DATA <= x"FF"; when x"818" => DATA <= x"20"; when x"819" => DATA <= x"76"; when x"81A" => DATA <= x"F8"; when x"81B" => DATA <= x"A2"; when x"81C" => DATA <= x"00"; when x"81D" => DATA <= x"C9"; when x"81E" => DATA <= x"22"; when x"81F" => DATA <= x"F0"; when x"820" => DATA <= x"06"; when x"821" => DATA <= x"E8"; when x"822" => DATA <= x"D0"; when x"823" => DATA <= x"1B"; when x"824" => DATA <= x"4C"; when x"825" => DATA <= x"7D"; when x"826" => DATA <= x"FA"; when x"827" => DATA <= x"C8"; when x"828" => DATA <= x"B9"; when x"829" => DATA <= x"00"; when x"82A" => DATA <= x"01"; when x"82B" => DATA <= x"C9"; when x"82C" => DATA <= x"0D"; when x"82D" => DATA <= x"F0"; when x"82E" => DATA <= x"F5"; when x"82F" => DATA <= x"9D"; when x"830" => DATA <= x"40"; when x"831" => DATA <= x"01"; when x"832" => DATA <= x"E8"; when x"833" => DATA <= x"C9"; when x"834" => DATA <= x"22"; when x"835" => DATA <= x"D0"; when x"836" => DATA <= x"F0"; when x"837" => DATA <= x"C8"; when x"838" => DATA <= x"B9"; when x"839" => DATA <= x"00"; when x"83A" => DATA <= x"01"; when x"83B" => DATA <= x"C9"; when x"83C" => DATA <= x"22"; when x"83D" => DATA <= x"F0"; when x"83E" => DATA <= x"E8"; when x"83F" => DATA <= x"A9"; when x"840" => DATA <= x"0D"; when x"841" => DATA <= x"9D"; when x"842" => DATA <= x"3F"; when x"843" => DATA <= x"01"; when x"844" => DATA <= x"A9"; when x"845" => DATA <= x"40"; when x"846" => DATA <= x"85"; when x"847" => DATA <= x"C9"; when x"848" => DATA <= x"A9"; when x"849" => DATA <= x"01"; when x"84A" => DATA <= x"85"; when x"84B" => DATA <= x"CA"; when x"84C" => DATA <= x"A2"; when x"84D" => DATA <= x"C9"; when x"84E" => DATA <= x"60"; when x"84F" => DATA <= x"A0"; when x"850" => DATA <= x"00"; when x"851" => DATA <= x"B5"; when x"852" => DATA <= x"00"; when x"853" => DATA <= x"99"; when x"854" => DATA <= x"C9"; when x"855" => DATA <= x"00"; when x"856" => DATA <= x"E8"; when x"857" => DATA <= x"C8"; when x"858" => DATA <= x"C0"; when x"859" => DATA <= x"0A"; when x"85A" => DATA <= x"90"; when x"85B" => DATA <= x"F5"; when x"85C" => DATA <= x"A0"; when x"85D" => DATA <= x"FF"; when x"85E" => DATA <= x"A9"; when x"85F" => DATA <= x"0D"; when x"860" => DATA <= x"C8"; when x"861" => DATA <= x"C0"; when x"862" => DATA <= x"0E"; when x"863" => DATA <= x"B0"; when x"864" => DATA <= x"07"; when x"865" => DATA <= x"D1"; when x"866" => DATA <= x"C9"; when x"867" => DATA <= x"D0"; when x"868" => DATA <= x"F7"; when x"869" => DATA <= x"C0"; when x"86A" => DATA <= x"00"; when x"86B" => DATA <= x"60"; when x"86C" => DATA <= x"20"; when x"86D" => DATA <= x"D1"; when x"86E" => DATA <= x"F7"; when x"86F" => DATA <= x"4E"; when x"870" => DATA <= x"41"; when x"871" => DATA <= x"4D"; when x"872" => DATA <= x"45"; when x"873" => DATA <= x"EA"; when x"874" => DATA <= x"00"; when x"875" => DATA <= x"C8"; when x"876" => DATA <= x"B9"; when x"877" => DATA <= x"00"; when x"878" => DATA <= x"01"; when x"879" => DATA <= x"C9"; when x"87A" => DATA <= x"20"; when x"87B" => DATA <= x"F0"; when x"87C" => DATA <= x"F8"; when x"87D" => DATA <= x"60"; when x"87E" => DATA <= x"C9"; when x"87F" => DATA <= x"30"; when x"880" => DATA <= x"90"; when x"881" => DATA <= x"0F"; when x"882" => DATA <= x"C9"; when x"883" => DATA <= x"3A"; when x"884" => DATA <= x"90"; when x"885" => DATA <= x"08"; when x"886" => DATA <= x"E9"; when x"887" => DATA <= x"07"; when x"888" => DATA <= x"90"; when x"889" => DATA <= x"07"; when x"88A" => DATA <= x"C9"; when x"88B" => DATA <= x"40"; when x"88C" => DATA <= x"B0"; when x"88D" => DATA <= x"02"; when x"88E" => DATA <= x"29"; when x"88F" => DATA <= x"0F"; when x"890" => DATA <= x"60"; when x"891" => DATA <= x"38"; when x"892" => DATA <= x"60"; when x"893" => DATA <= x"A9"; when x"894" => DATA <= x"00"; when x"895" => DATA <= x"95"; when x"896" => DATA <= x"00"; when x"897" => DATA <= x"95"; when x"898" => DATA <= x"01"; when x"899" => DATA <= x"95"; when x"89A" => DATA <= x"02"; when x"89B" => DATA <= x"20"; when x"89C" => DATA <= x"76"; when x"89D" => DATA <= x"F8"; when x"89E" => DATA <= x"B9"; when x"89F" => DATA <= x"00"; when x"8A0" => DATA <= x"01"; when x"8A1" => DATA <= x"20"; when x"8A2" => DATA <= x"7E"; when x"8A3" => DATA <= x"F8"; when x"8A4" => DATA <= x"B0"; when x"8A5" => DATA <= x"15"; when x"8A6" => DATA <= x"0A"; when x"8A7" => DATA <= x"0A"; when x"8A8" => DATA <= x"0A"; when x"8A9" => DATA <= x"0A"; when x"8AA" => DATA <= x"94"; when x"8AB" => DATA <= x"02"; when x"8AC" => DATA <= x"A0"; when x"8AD" => DATA <= x"04"; when x"8AE" => DATA <= x"0A"; when x"8AF" => DATA <= x"36"; when x"8B0" => DATA <= x"00"; when x"8B1" => DATA <= x"36"; when x"8B2" => DATA <= x"01"; when x"8B3" => DATA <= x"88"; when x"8B4" => DATA <= x"D0"; when x"8B5" => DATA <= x"F8"; when x"8B6" => DATA <= x"B4"; when x"8B7" => DATA <= x"02"; when x"8B8" => DATA <= x"C8"; when x"8B9" => DATA <= x"D0"; when x"8BA" => DATA <= x"E3"; when x"8BB" => DATA <= x"B5"; when x"8BC" => DATA <= x"02"; when x"8BD" => DATA <= x"60"; when x"8BE" => DATA <= x"43"; when x"8BF" => DATA <= x"41"; when x"8C0" => DATA <= x"54"; when x"8C1" => DATA <= x"FA"; when x"8C2" => DATA <= x"2A"; when x"8C3" => DATA <= x"4C"; when x"8C4" => DATA <= x"4F"; when x"8C5" => DATA <= x"41"; when x"8C6" => DATA <= x"44"; when x"8C7" => DATA <= x"F9"; when x"8C8" => DATA <= x"58"; when x"8C9" => DATA <= x"53"; when x"8CA" => DATA <= x"41"; when x"8CB" => DATA <= x"56"; when x"8CC" => DATA <= x"45"; when x"8CD" => DATA <= x"FA"; when x"8CE" => DATA <= x"BB"; when x"8CF" => DATA <= x"52"; when x"8D0" => DATA <= x"55"; when x"8D1" => DATA <= x"4E"; when x"8D2" => DATA <= x"FA"; when x"8D3" => DATA <= x"20"; when x"8D4" => DATA <= x"4D"; when x"8D5" => DATA <= x"4F"; when x"8D6" => DATA <= x"4E"; when x"8D7" => DATA <= x"FA"; when x"8D8" => DATA <= x"1A"; when x"8D9" => DATA <= x"4E"; when x"8DA" => DATA <= x"4F"; when x"8DB" => DATA <= x"4D"; when x"8DC" => DATA <= x"4F"; when x"8DD" => DATA <= x"4E"; when x"8DE" => DATA <= x"FA"; when x"8DF" => DATA <= x"19"; when x"8E0" => DATA <= x"46"; when x"8E1" => DATA <= x"4C"; when x"8E2" => DATA <= x"4F"; when x"8E3" => DATA <= x"41"; when x"8E4" => DATA <= x"44"; when x"8E5" => DATA <= x"F9"; when x"8E6" => DATA <= x"55"; when x"8E7" => DATA <= x"44"; when x"8E8" => DATA <= x"4F"; when x"8E9" => DATA <= x"53"; when x"8EA" => DATA <= x"CC"; when x"8EB" => DATA <= x"EF"; when x"8EC" => DATA <= x"00"; when x"8ED" => DATA <= x"F9"; when x"8EE" => DATA <= x"26"; when x"8EF" => DATA <= x"A2"; when x"8F0" => DATA <= x"FF"; when x"8F1" => DATA <= x"D8"; when x"8F2" => DATA <= x"A0"; when x"8F3" => DATA <= x"00"; when x"8F4" => DATA <= x"84"; when x"8F5" => DATA <= x"DD"; when x"8F6" => DATA <= x"20"; when x"8F7" => DATA <= x"76"; when x"8F8" => DATA <= x"F8"; when x"8F9" => DATA <= x"88"; when x"8FA" => DATA <= x"C8"; when x"8FB" => DATA <= x"E8"; when x"8FC" => DATA <= x"BD"; when x"8FD" => DATA <= x"BE"; when x"8FE" => DATA <= x"F8"; when x"8FF" => DATA <= x"30"; when x"900" => DATA <= x"18"; when x"901" => DATA <= x"D9"; when x"902" => DATA <= x"00"; when x"903" => DATA <= x"01"; when x"904" => DATA <= x"F0"; when x"905" => DATA <= x"F4"; when x"906" => DATA <= x"CA"; when x"907" => DATA <= x"E8"; when x"908" => DATA <= x"BD"; when x"909" => DATA <= x"BE"; when x"90A" => DATA <= x"F8"; when x"90B" => DATA <= x"10"; when x"90C" => DATA <= x"FA"; when x"90D" => DATA <= x"E8"; when x"90E" => DATA <= x"B9"; when x"90F" => DATA <= x"00"; when x"910" => DATA <= x"01"; when x"911" => DATA <= x"C9"; when x"912" => DATA <= x"2E"; when x"913" => DATA <= x"D0"; when x"914" => DATA <= x"DD"; when x"915" => DATA <= x"C8"; when x"916" => DATA <= x"CA"; when x"917" => DATA <= x"B0"; when x"918" => DATA <= x"E3"; when x"919" => DATA <= x"85"; when x"91A" => DATA <= x"CA"; when x"91B" => DATA <= x"BD"; when x"91C" => DATA <= x"BF"; when x"91D" => DATA <= x"F8"; when x"91E" => DATA <= x"85"; when x"91F" => DATA <= x"C9"; when x"920" => DATA <= x"18"; when x"921" => DATA <= x"A2"; when x"922" => DATA <= x"00"; when x"923" => DATA <= x"6C"; when x"924" => DATA <= x"C9"; when x"925" => DATA <= x"00"; when x"926" => DATA <= x"20"; when x"927" => DATA <= x"D1"; when x"928" => DATA <= x"F7"; when x"929" => DATA <= x"43"; when x"92A" => DATA <= x"4F"; when x"92B" => DATA <= x"4D"; when x"92C" => DATA <= x"3F"; when x"92D" => DATA <= x"EA"; when x"92E" => DATA <= x"00"; when x"92F" => DATA <= x"20"; when x"930" => DATA <= x"8E"; when x"931" => DATA <= x"FB"; when x"932" => DATA <= x"50"; when x"933" => DATA <= x"FA"; when x"934" => DATA <= x"F0"; when x"935" => DATA <= x"F9"; when x"936" => DATA <= x"20"; when x"937" => DATA <= x"2B"; when x"938" => DATA <= x"FC"; when x"939" => DATA <= x"A0"; when x"93A" => DATA <= x"00"; when x"93B" => DATA <= x"20"; when x"93C" => DATA <= x"D4"; when x"93D" => DATA <= x"FF"; when x"93E" => DATA <= x"91"; when x"93F" => DATA <= x"CB"; when x"940" => DATA <= x"E6"; when x"941" => DATA <= x"CB"; when x"942" => DATA <= x"D0"; when x"943" => DATA <= x"02"; when x"944" => DATA <= x"E6"; when x"945" => DATA <= x"CC"; when x"946" => DATA <= x"A2"; when x"947" => DATA <= x"D4"; when x"948" => DATA <= x"20"; when x"949" => DATA <= x"08"; when x"94A" => DATA <= x"FA"; when x"94B" => DATA <= x"D0"; when x"94C" => DATA <= x"EE"; when x"94D" => DATA <= x"38"; when x"94E" => DATA <= x"66"; when x"94F" => DATA <= x"DD"; when x"950" => DATA <= x"18"; when x"951" => DATA <= x"66"; when x"952" => DATA <= x"DD"; when x"953" => DATA <= x"28"; when x"954" => DATA <= x"60"; when x"955" => DATA <= x"38"; when x"956" => DATA <= x"66"; when x"957" => DATA <= x"DD"; when x"958" => DATA <= x"20"; when x"959" => DATA <= x"18"; when x"95A" => DATA <= x"F8"; when x"95B" => DATA <= x"A2"; when x"95C" => DATA <= x"CB"; when x"95D" => DATA <= x"20"; when x"95E" => DATA <= x"93"; when x"95F" => DATA <= x"F8"; when x"960" => DATA <= x"F0"; when x"961" => DATA <= x"04"; when x"962" => DATA <= x"A9"; when x"963" => DATA <= x"FF"; when x"964" => DATA <= x"85"; when x"965" => DATA <= x"CD"; when x"966" => DATA <= x"20"; when x"967" => DATA <= x"76"; when x"968" => DATA <= x"FA"; when x"969" => DATA <= x"A2"; when x"96A" => DATA <= x"C9"; when x"96B" => DATA <= x"6C"; when x"96C" => DATA <= x"0C"; when x"96D" => DATA <= x"02"; when x"96E" => DATA <= x"08"; when x"96F" => DATA <= x"78"; when x"970" => DATA <= x"20"; when x"971" => DATA <= x"4F"; when x"972" => DATA <= x"F8"; when x"973" => DATA <= x"08"; when x"974" => DATA <= x"20"; when x"975" => DATA <= x"3E"; when x"976" => DATA <= x"FC"; when x"977" => DATA <= x"28"; when x"978" => DATA <= x"F0"; when x"979" => DATA <= x"B5"; when x"97A" => DATA <= x"A9"; when x"97B" => DATA <= x"00"; when x"97C" => DATA <= x"85"; when x"97D" => DATA <= x"D0"; when x"97E" => DATA <= x"85"; when x"97F" => DATA <= x"D1"; when x"980" => DATA <= x"20"; when x"981" => DATA <= x"A2"; when x"982" => DATA <= x"F9"; when x"983" => DATA <= x"90"; when x"984" => DATA <= x"C9"; when x"985" => DATA <= x"E6"; when x"986" => DATA <= x"D0"; when x"987" => DATA <= x"E6"; when x"988" => DATA <= x"CC"; when x"989" => DATA <= x"D0"; when x"98A" => DATA <= x"F5"; when x"98B" => DATA <= x"18"; when x"98C" => DATA <= x"90"; when x"98D" => DATA <= x"C0"; when x"98E" => DATA <= x"20"; when x"98F" => DATA <= x"F4"; when x"990" => DATA <= x"FF"; when x"991" => DATA <= x"C8"; when x"992" => DATA <= x"B9"; when x"993" => DATA <= x"ED"; when x"994" => DATA <= x"00"; when x"995" => DATA <= x"C9"; when x"996" => DATA <= x"0D"; when x"997" => DATA <= x"D0"; when x"998" => DATA <= x"F5"; when x"999" => DATA <= x"C8"; when x"99A" => DATA <= x"20"; when x"99B" => DATA <= x"FD"; when x"99C" => DATA <= x"F7"; when x"99D" => DATA <= x"C0"; when x"99E" => DATA <= x"0E"; when x"99F" => DATA <= x"90"; when x"9A0" => DATA <= x"F8"; when x"9A1" => DATA <= x"60"; when x"9A2" => DATA <= x"A9"; when x"9A3" => DATA <= x"00"; when x"9A4" => DATA <= x"85"; when x"9A5" => DATA <= x"DC"; when x"9A6" => DATA <= x"20"; when x"9A7" => DATA <= x"8E"; when x"9A8" => DATA <= x"FB"; when x"9A9" => DATA <= x"50"; when x"9AA" => DATA <= x"F8"; when x"9AB" => DATA <= x"D0"; when x"9AC" => DATA <= x"F5"; when x"9AD" => DATA <= x"20"; when x"9AE" => DATA <= x"C9"; when x"9AF" => DATA <= x"FB"; when x"9B0" => DATA <= x"08"; when x"9B1" => DATA <= x"20"; when x"9B2" => DATA <= x"E2"; when x"9B3" => DATA <= x"FB"; when x"9B4" => DATA <= x"28"; when x"9B5" => DATA <= x"F0"; when x"9B6" => DATA <= x"10"; when x"9B7" => DATA <= x"A5"; when x"9B8" => DATA <= x"DB"; when x"9B9" => DATA <= x"29"; when x"9BA" => DATA <= x"20"; when x"9BB" => DATA <= x"05"; when x"9BC" => DATA <= x"EA"; when x"9BD" => DATA <= x"D0"; when x"9BE" => DATA <= x"E3"; when x"9BF" => DATA <= x"20"; when x"9C0" => DATA <= x"92"; when x"9C1" => DATA <= x"F9"; when x"9C2" => DATA <= x"20"; when x"9C3" => DATA <= x"ED"; when x"9C4" => DATA <= x"FF"; when x"9C5" => DATA <= x"D0"; when x"9C6" => DATA <= x"DB"; when x"9C7" => DATA <= x"A2"; when x"9C8" => DATA <= x"02"; when x"9C9" => DATA <= x"A5"; when x"9CA" => DATA <= x"DD"; when x"9CB" => DATA <= x"30"; when x"9CC" => DATA <= x"13"; when x"9CD" => DATA <= x"B5"; when x"9CE" => DATA <= x"CF"; when x"9CF" => DATA <= x"D5"; when x"9D0" => DATA <= x"D8"; when x"9D1" => DATA <= x"B0"; when x"9D2" => DATA <= x"08"; when x"9D3" => DATA <= x"A9"; when x"9D4" => DATA <= x"05"; when x"9D5" => DATA <= x"20"; when x"9D6" => DATA <= x"40"; when x"9D7" => DATA <= x"FC"; when x"9D8" => DATA <= x"20"; when x"9D9" => DATA <= x"3E"; when x"9DA" => DATA <= x"FC"; when x"9DB" => DATA <= x"D0"; when x"9DC" => DATA <= x"C5"; when x"9DD" => DATA <= x"CA"; when x"9DE" => DATA <= x"D0"; when x"9DF" => DATA <= x"ED"; when x"9E0" => DATA <= x"20"; when x"9E1" => DATA <= x"2B"; when x"9E2" => DATA <= x"FC"; when x"9E3" => DATA <= x"24"; when x"9E4" => DATA <= x"DB"; when x"9E5" => DATA <= x"50"; when x"9E6" => DATA <= x"0B"; when x"9E7" => DATA <= x"88"; when x"9E8" => DATA <= x"C8"; when x"9E9" => DATA <= x"20"; when x"9EA" => DATA <= x"D4"; when x"9EB" => DATA <= x"FF"; when x"9EC" => DATA <= x"91"; when x"9ED" => DATA <= x"CB"; when x"9EE" => DATA <= x"C4"; when x"9EF" => DATA <= x"D8"; when x"9F0" => DATA <= x"D0"; when x"9F1" => DATA <= x"F6"; when x"9F2" => DATA <= x"A5"; when x"9F3" => DATA <= x"DC"; when x"9F4" => DATA <= x"85"; when x"9F5" => DATA <= x"CE"; when x"9F6" => DATA <= x"20"; when x"9F7" => DATA <= x"D4"; when x"9F8" => DATA <= x"FF"; when x"9F9" => DATA <= x"C5"; when x"9FA" => DATA <= x"CE"; when x"9FB" => DATA <= x"F0"; when x"9FC" => DATA <= x"08"; when x"9FD" => DATA <= x"20"; when x"9FE" => DATA <= x"D1"; when x"9FF" => DATA <= x"F7"; when x"A00" => DATA <= x"53"; when x"A01" => DATA <= x"55"; when x"A02" => DATA <= x"4D"; when x"A03" => DATA <= x"EA"; when x"A04" => DATA <= x"00"; when x"A05" => DATA <= x"26"; when x"A06" => DATA <= x"DB"; when x"A07" => DATA <= x"60"; when x"A08" => DATA <= x"F6"; when x"A09" => DATA <= x"00"; when x"A0A" => DATA <= x"D0"; when x"A0B" => DATA <= x"02"; when x"A0C" => DATA <= x"F6"; when x"A0D" => DATA <= x"01"; when x"A0E" => DATA <= x"B5"; when x"A0F" => DATA <= x"00"; when x"A10" => DATA <= x"D5"; when x"A11" => DATA <= x"02"; when x"A12" => DATA <= x"D0"; when x"A13" => DATA <= x"04"; when x"A14" => DATA <= x"B5"; when x"A15" => DATA <= x"01"; when x"A16" => DATA <= x"D5"; when x"A17" => DATA <= x"03"; when x"A18" => DATA <= x"60"; when x"A19" => DATA <= x"CA"; when x"A1A" => DATA <= x"20"; when x"A1B" => DATA <= x"76"; when x"A1C" => DATA <= x"FA"; when x"A1D" => DATA <= x"86"; when x"A1E" => DATA <= x"EA"; when x"A1F" => DATA <= x"60"; when x"A20" => DATA <= x"20"; when x"A21" => DATA <= x"58"; when x"A22" => DATA <= x"F9"; when x"A23" => DATA <= x"24"; when x"A24" => DATA <= x"DD"; when x"A25" => DATA <= x"70"; when x"A26" => DATA <= x"4C"; when x"A27" => DATA <= x"6C"; when x"A28" => DATA <= x"D6"; when x"A29" => DATA <= x"00"; when x"A2A" => DATA <= x"08"; when x"A2B" => DATA <= x"20"; when x"A2C" => DATA <= x"76"; when x"A2D" => DATA <= x"FA"; when x"A2E" => DATA <= x"20"; when x"A2F" => DATA <= x"3E"; when x"A30" => DATA <= x"FC"; when x"A31" => DATA <= x"20"; when x"A32" => DATA <= x"8E"; when x"A33" => DATA <= x"FB"; when x"A34" => DATA <= x"70"; when x"A35" => DATA <= x"02"; when x"A36" => DATA <= x"28"; when x"A37" => DATA <= x"60"; when x"A38" => DATA <= x"F0"; when x"A39" => DATA <= x"0A"; when x"A3A" => DATA <= x"A0"; when x"A3B" => DATA <= x"00"; when x"A3C" => DATA <= x"20"; when x"A3D" => DATA <= x"99"; when x"A3E" => DATA <= x"F9"; when x"A3F" => DATA <= x"20"; when x"A40" => DATA <= x"EC"; when x"A41" => DATA <= x"F7"; when x"A42" => DATA <= x"D0"; when x"A43" => DATA <= x"19"; when x"A44" => DATA <= x"20"; when x"A45" => DATA <= x"C9"; when x"A46" => DATA <= x"FB"; when x"A47" => DATA <= x"20"; when x"A48" => DATA <= x"E2"; when x"A49" => DATA <= x"FB"; when x"A4A" => DATA <= x"20"; when x"A4B" => DATA <= x"92"; when x"A4C" => DATA <= x"F9"; when x"A4D" => DATA <= x"20"; when x"A4E" => DATA <= x"EC"; when x"A4F" => DATA <= x"F7"; when x"A50" => DATA <= x"26"; when x"A51" => DATA <= x"DB"; when x"A52" => DATA <= x"10"; when x"A53" => DATA <= x"09"; when x"A54" => DATA <= x"E8"; when x"A55" => DATA <= x"20"; when x"A56" => DATA <= x"F1"; when x"A57" => DATA <= x"F7"; when x"A58" => DATA <= x"B5"; when x"A59" => DATA <= x"FD"; when x"A5A" => DATA <= x"20"; when x"A5B" => DATA <= x"02"; when x"A5C" => DATA <= x"F8"; when x"A5D" => DATA <= x"20"; when x"A5E" => DATA <= x"ED"; when x"A5F" => DATA <= x"FF"; when x"A60" => DATA <= x"D0"; when x"A61" => DATA <= x"CF"; when x"A62" => DATA <= x"4C"; when x"A63" => DATA <= x"ED"; when x"A64" => DATA <= x"FF"; when x"A65" => DATA <= x"20"; when x"A66" => DATA <= x"93"; when x"A67" => DATA <= x"F8"; when x"A68" => DATA <= x"F0"; when x"A69" => DATA <= x"13"; when x"A6A" => DATA <= x"60"; when x"A6B" => DATA <= x"A2"; when x"A6C" => DATA <= x"CB"; when x"A6D" => DATA <= x"20"; when x"A6E" => DATA <= x"65"; when x"A6F" => DATA <= x"FA"; when x"A70" => DATA <= x"20"; when x"A71" => DATA <= x"76"; when x"A72" => DATA <= x"FA"; when x"A73" => DATA <= x"6C"; when x"A74" => DATA <= x"CB"; when x"A75" => DATA <= x"00"; when x"A76" => DATA <= x"20"; when x"A77" => DATA <= x"76"; when x"A78" => DATA <= x"F8"; when x"A79" => DATA <= x"C9"; when x"A7A" => DATA <= x"0D"; when x"A7B" => DATA <= x"F0"; when x"A7C" => DATA <= x"A2"; when x"A7D" => DATA <= x"20"; when x"A7E" => DATA <= x"D1"; when x"A7F" => DATA <= x"F7"; when x"A80" => DATA <= x"53"; when x"A81" => DATA <= x"59"; when x"A82" => DATA <= x"4E"; when x"A83" => DATA <= x"3F"; when x"A84" => DATA <= x"EA"; when x"A85" => DATA <= x"00"; when x"A86" => DATA <= x"38"; when x"A87" => DATA <= x"A5"; when x"A88" => DATA <= x"D1"; when x"A89" => DATA <= x"E5"; when x"A8A" => DATA <= x"CF"; when x"A8B" => DATA <= x"48"; when x"A8C" => DATA <= x"A5"; when x"A8D" => DATA <= x"D2"; when x"A8E" => DATA <= x"E5"; when x"A8F" => DATA <= x"D0"; when x"A90" => DATA <= x"A8"; when x"A91" => DATA <= x"68"; when x"A92" => DATA <= x"18"; when x"A93" => DATA <= x"65"; when x"A94" => DATA <= x"CB"; when x"A95" => DATA <= x"85"; when x"A96" => DATA <= x"CD"; when x"A97" => DATA <= x"98"; when x"A98" => DATA <= x"65"; when x"A99" => DATA <= x"CC"; when x"A9A" => DATA <= x"85"; when x"A9B" => DATA <= x"CE"; when x"A9C" => DATA <= x"A0"; when x"A9D" => DATA <= x"04"; when x"A9E" => DATA <= x"B9"; when x"A9F" => DATA <= x"CA"; when x"AA0" => DATA <= x"00"; when x"AA1" => DATA <= x"20"; when x"AA2" => DATA <= x"D1"; when x"AA3" => DATA <= x"FF"; when x"AA4" => DATA <= x"88"; when x"AA5" => DATA <= x"D0"; when x"AA6" => DATA <= x"F7"; when x"AA7" => DATA <= x"B1"; when x"AA8" => DATA <= x"CF"; when x"AA9" => DATA <= x"20"; when x"AAA" => DATA <= x"D1"; when x"AAB" => DATA <= x"FF"; when x"AAC" => DATA <= x"E6"; when x"AAD" => DATA <= x"CF"; when x"AAE" => DATA <= x"D0"; when x"AAF" => DATA <= x"02"; when x"AB0" => DATA <= x"E6"; when x"AB1" => DATA <= x"D0"; when x"AB2" => DATA <= x"A2"; when x"AB3" => DATA <= x"CB"; when x"AB4" => DATA <= x"20"; when x"AB5" => DATA <= x"08"; when x"AB6" => DATA <= x"FA"; when x"AB7" => DATA <= x"D0"; when x"AB8" => DATA <= x"EE"; when x"AB9" => DATA <= x"28"; when x"ABA" => DATA <= x"60"; when x"ABB" => DATA <= x"20"; when x"ABC" => DATA <= x"18"; when x"ABD" => DATA <= x"F8"; when x"ABE" => DATA <= x"A2"; when x"ABF" => DATA <= x"CB"; when x"AC0" => DATA <= x"20"; when x"AC1" => DATA <= x"65"; when x"AC2" => DATA <= x"FA"; when x"AC3" => DATA <= x"A2"; when x"AC4" => DATA <= x"D1"; when x"AC5" => DATA <= x"20"; when x"AC6" => DATA <= x"65"; when x"AC7" => DATA <= x"FA"; when x"AC8" => DATA <= x"A2"; when x"AC9" => DATA <= x"CD"; when x"ACA" => DATA <= x"20"; when x"ACB" => DATA <= x"93"; when x"ACC" => DATA <= x"F8"; when x"ACD" => DATA <= x"08"; when x"ACE" => DATA <= x"A5"; when x"ACF" => DATA <= x"CB"; when x"AD0" => DATA <= x"A6"; when x"AD1" => DATA <= x"CC"; when x"AD2" => DATA <= x"28"; when x"AD3" => DATA <= x"D0"; when x"AD4" => DATA <= x"04"; when x"AD5" => DATA <= x"85"; when x"AD6" => DATA <= x"CD"; when x"AD7" => DATA <= x"86"; when x"AD8" => DATA <= x"CE"; when x"AD9" => DATA <= x"85"; when x"ADA" => DATA <= x"CF"; when x"ADB" => DATA <= x"86"; when x"ADC" => DATA <= x"D0"; when x"ADD" => DATA <= x"20"; when x"ADE" => DATA <= x"76"; when x"ADF" => DATA <= x"FA"; when x"AE0" => DATA <= x"A2"; when x"AE1" => DATA <= x"C9"; when x"AE2" => DATA <= x"6C"; when x"AE3" => DATA <= x"0E"; when x"AE4" => DATA <= x"02"; when x"AE5" => DATA <= x"08"; when x"AE6" => DATA <= x"78"; when x"AE7" => DATA <= x"20"; when x"AE8" => DATA <= x"4F"; when x"AE9" => DATA <= x"F8"; when x"AEA" => DATA <= x"08"; when x"AEB" => DATA <= x"A9"; when x"AEC" => DATA <= x"06"; when x"AED" => DATA <= x"20"; when x"AEE" => DATA <= x"40"; when x"AEF" => DATA <= x"FC"; when x"AF0" => DATA <= x"A2"; when x"AF1" => DATA <= x"07"; when x"AF2" => DATA <= x"20"; when x"AF3" => DATA <= x"7A"; when x"AF4" => DATA <= x"FB"; when x"AF5" => DATA <= x"28"; when x"AF6" => DATA <= x"F0"; when x"AF7" => DATA <= x"8E"; when x"AF8" => DATA <= x"A2"; when x"AF9" => DATA <= x"04"; when x"AFA" => DATA <= x"B5"; when x"AFB" => DATA <= x"CE"; when x"AFC" => DATA <= x"95"; when x"AFD" => DATA <= x"D2"; when x"AFE" => DATA <= x"CA"; when x"AFF" => DATA <= x"D0"; when x"B00" => DATA <= x"F9"; when x"B01" => DATA <= x"86"; when x"B02" => DATA <= x"D0"; when x"B03" => DATA <= x"86"; when x"B04" => DATA <= x"D1"; when x"B05" => DATA <= x"A5"; when x"B06" => DATA <= x"D5"; when x"B07" => DATA <= x"D0"; when x"B08" => DATA <= x"02"; when x"B09" => DATA <= x"C6"; when x"B0A" => DATA <= x"D6"; when x"B0B" => DATA <= x"C6"; when x"B0C" => DATA <= x"D5"; when x"B0D" => DATA <= x"18"; when x"B0E" => DATA <= x"66"; when x"B0F" => DATA <= x"D2"; when x"B10" => DATA <= x"38"; when x"B11" => DATA <= x"A2"; when x"B12" => DATA <= x"FF"; when x"B13" => DATA <= x"A5"; when x"B14" => DATA <= x"D5"; when x"B15" => DATA <= x"E5"; when x"B16" => DATA <= x"D3"; when x"B17" => DATA <= x"85"; when x"B18" => DATA <= x"CF"; when x"B19" => DATA <= x"A5"; when x"B1A" => DATA <= x"D6"; when x"B1B" => DATA <= x"E5"; when x"B1C" => DATA <= x"D4"; when x"B1D" => DATA <= x"08"; when x"B1E" => DATA <= x"66"; when x"B1F" => DATA <= x"D2"; when x"B20" => DATA <= x"28"; when x"B21" => DATA <= x"90"; when x"B22" => DATA <= x"06"; when x"B23" => DATA <= x"18"; when x"B24" => DATA <= x"F0"; when x"B25" => DATA <= x"03"; when x"B26" => DATA <= x"86"; when x"B27" => DATA <= x"CF"; when x"B28" => DATA <= x"38"; when x"B29" => DATA <= x"66"; when x"B2A" => DATA <= x"D2"; when x"B2B" => DATA <= x"E8"; when x"B2C" => DATA <= x"20"; when x"B2D" => DATA <= x"3B"; when x"B2E" => DATA <= x"FB"; when x"B2F" => DATA <= x"E6"; when x"B30" => DATA <= x"D0"; when x"B31" => DATA <= x"E6"; when x"B32" => DATA <= x"D4"; when x"B33" => DATA <= x"E6"; when x"B34" => DATA <= x"CC"; when x"B35" => DATA <= x"26"; when x"B36" => DATA <= x"D2"; when x"B37" => DATA <= x"B0"; when x"B38" => DATA <= x"D5"; when x"B39" => DATA <= x"28"; when x"B3A" => DATA <= x"60"; when x"B3B" => DATA <= x"A2"; when x"B3C" => DATA <= x"07"; when x"B3D" => DATA <= x"20"; when x"B3E" => DATA <= x"7A"; when x"B3F" => DATA <= x"FB"; when x"B40" => DATA <= x"86"; when x"B41" => DATA <= x"DC"; when x"B42" => DATA <= x"A0"; when x"B43" => DATA <= x"04"; when x"B44" => DATA <= x"A9"; when x"B45" => DATA <= x"2A"; when x"B46" => DATA <= x"20"; when x"B47" => DATA <= x"D1"; when x"B48" => DATA <= x"FF"; when x"B49" => DATA <= x"88"; when x"B4A" => DATA <= x"D0"; when x"B4B" => DATA <= x"F8"; when x"B4C" => DATA <= x"B1"; when x"B4D" => DATA <= x"C9"; when x"B4E" => DATA <= x"20"; when x"B4F" => DATA <= x"D1"; when x"B50" => DATA <= x"FF"; when x"B51" => DATA <= x"C8"; when x"B52" => DATA <= x"C9"; when x"B53" => DATA <= x"0D"; when x"B54" => DATA <= x"D0"; when x"B55" => DATA <= x"F6"; when x"B56" => DATA <= x"A0"; when x"B57" => DATA <= x"08"; when x"B58" => DATA <= x"B9"; when x"B59" => DATA <= x"CA"; when x"B5A" => DATA <= x"00"; when x"B5B" => DATA <= x"20"; when x"B5C" => DATA <= x"D1"; when x"B5D" => DATA <= x"FF"; when x"B5E" => DATA <= x"88"; when x"B5F" => DATA <= x"D0"; when x"B60" => DATA <= x"F7"; when x"B61" => DATA <= x"20"; when x"B62" => DATA <= x"81"; when x"B63" => DATA <= x"FB"; when x"B64" => DATA <= x"24"; when x"B65" => DATA <= x"D2"; when x"B66" => DATA <= x"50"; when x"B67" => DATA <= x"0B"; when x"B68" => DATA <= x"88"; when x"B69" => DATA <= x"C8"; when x"B6A" => DATA <= x"B1"; when x"B6B" => DATA <= x"D3"; when x"B6C" => DATA <= x"20"; when x"B6D" => DATA <= x"D1"; when x"B6E" => DATA <= x"FF"; when x"B6F" => DATA <= x"C4"; when x"B70" => DATA <= x"CF"; when x"B71" => DATA <= x"D0"; when x"B72" => DATA <= x"F6"; when x"B73" => DATA <= x"A5"; when x"B74" => DATA <= x"DC"; when x"B75" => DATA <= x"20"; when x"B76" => DATA <= x"D1"; when x"B77" => DATA <= x"FF"; when x"B78" => DATA <= x"A2"; when x"B79" => DATA <= x"04"; when x"B7A" => DATA <= x"8E"; when x"B7B" => DATA <= x"02"; when x"B7C" => DATA <= x"B0"; when x"B7D" => DATA <= x"A2"; when x"B7E" => DATA <= x"78"; when x"B7F" => DATA <= x"D0"; when x"B80" => DATA <= x"02"; when x"B81" => DATA <= x"A2"; when x"B82" => DATA <= x"1E"; when x"B83" => DATA <= x"20"; when x"B84" => DATA <= x"66"; when x"B85" => DATA <= x"FE"; when x"B86" => DATA <= x"CA"; when x"B87" => DATA <= x"D0"; when x"B88" => DATA <= x"FA"; when x"B89" => DATA <= x"60"; when x"B8A" => DATA <= x"A2"; when x"B8B" => DATA <= x"06"; when x"B8C" => DATA <= x"D0"; when x"B8D" => DATA <= x"F5"; when x"B8E" => DATA <= x"2C"; when x"B8F" => DATA <= x"01"; when x"B90" => DATA <= x"B0"; when x"B91" => DATA <= x"10"; when x"B92" => DATA <= x"FB"; when x"B93" => DATA <= x"50"; when x"B94" => DATA <= x"F9"; when x"B95" => DATA <= x"A0"; when x"B96" => DATA <= x"00"; when x"B97" => DATA <= x"85"; when x"B98" => DATA <= x"C3"; when x"B99" => DATA <= x"A9"; when x"B9A" => DATA <= x"10"; when x"B9B" => DATA <= x"85"; when x"B9C" => DATA <= x"C2"; when x"B9D" => DATA <= x"2C"; when x"B9E" => DATA <= x"01"; when x"B9F" => DATA <= x"B0"; when x"BA0" => DATA <= x"10"; when x"BA1" => DATA <= x"0F"; when x"BA2" => DATA <= x"50"; when x"BA3" => DATA <= x"0D"; when x"BA4" => DATA <= x"20"; when x"BA5" => DATA <= x"BD"; when x"BA6" => DATA <= x"FC"; when x"BA7" => DATA <= x"B0"; when x"BA8" => DATA <= x"EC"; when x"BA9" => DATA <= x"C6"; when x"BAA" => DATA <= x"C3"; when x"BAB" => DATA <= x"D0"; when x"BAC" => DATA <= x"F0"; when x"BAD" => DATA <= x"C6"; when x"BAE" => DATA <= x"C2"; when x"BAF" => DATA <= x"D0"; when x"BB0" => DATA <= x"EC"; when x"BB1" => DATA <= x"70"; when x"BB2" => DATA <= x"01"; when x"BB3" => DATA <= x"60"; when x"BB4" => DATA <= x"A0"; when x"BB5" => DATA <= x"04"; when x"BB6" => DATA <= x"08"; when x"BB7" => DATA <= x"20"; when x"BB8" => DATA <= x"E4"; when x"BB9" => DATA <= x"FB"; when x"BBA" => DATA <= x"28"; when x"BBB" => DATA <= x"A0"; when x"BBC" => DATA <= x"04"; when x"BBD" => DATA <= x"A9"; when x"BBE" => DATA <= x"2A"; when x"BBF" => DATA <= x"D9"; when x"BC0" => DATA <= x"D3"; when x"BC1" => DATA <= x"00"; when x"BC2" => DATA <= x"D0"; when x"BC3" => DATA <= x"03"; when x"BC4" => DATA <= x"88"; when x"BC5" => DATA <= x"D0"; when x"BC6" => DATA <= x"F8"; when x"BC7" => DATA <= x"60"; when x"BC8" => DATA <= x"C8"; when x"BC9" => DATA <= x"20"; when x"BCA" => DATA <= x"D4"; when x"BCB" => DATA <= x"FF"; when x"BCC" => DATA <= x"99"; when x"BCD" => DATA <= x"ED"; when x"BCE" => DATA <= x"00"; when x"BCF" => DATA <= x"C9"; when x"BD0" => DATA <= x"0D"; when x"BD1" => DATA <= x"D0"; when x"BD2" => DATA <= x"F5"; when x"BD3" => DATA <= x"A0"; when x"BD4" => DATA <= x"FF"; when x"BD5" => DATA <= x"C8"; when x"BD6" => DATA <= x"B1"; when x"BD7" => DATA <= x"C9"; when x"BD8" => DATA <= x"D9"; when x"BD9" => DATA <= x"ED"; when x"BDA" => DATA <= x"00"; when x"BDB" => DATA <= x"D0"; when x"BDC" => DATA <= x"EA"; when x"BDD" => DATA <= x"C9"; when x"BDE" => DATA <= x"0D"; when x"BDF" => DATA <= x"D0"; when x"BE0" => DATA <= x"F4"; when x"BE1" => DATA <= x"60"; when x"BE2" => DATA <= x"A0"; when x"BE3" => DATA <= x"08"; when x"BE4" => DATA <= x"20"; when x"BE5" => DATA <= x"D4"; when x"BE6" => DATA <= x"FF"; when x"BE7" => DATA <= x"99"; when x"BE8" => DATA <= x"D3"; when x"BE9" => DATA <= x"00"; when x"BEA" => DATA <= x"88"; when x"BEB" => DATA <= x"D0"; when x"BEC" => DATA <= x"F7"; when x"BED" => DATA <= x"60"; when x"BEE" => DATA <= x"86"; when x"BEF" => DATA <= x"EC"; when x"BF0" => DATA <= x"84"; when x"BF1" => DATA <= x"C3"; when x"BF2" => DATA <= x"08"; when x"BF3" => DATA <= x"78"; when x"BF4" => DATA <= x"A9"; when x"BF5" => DATA <= x"78"; when x"BF6" => DATA <= x"85"; when x"BF7" => DATA <= x"C0"; when x"BF8" => DATA <= x"20"; when x"BF9" => DATA <= x"BD"; when x"BFA" => DATA <= x"FC"; when x"BFB" => DATA <= x"90"; when x"BFC" => DATA <= x"F7"; when x"BFD" => DATA <= x"E6"; when x"BFE" => DATA <= x"C0"; when x"BFF" => DATA <= x"10"; when x"C00" => DATA <= x"F7"; when x"C01" => DATA <= x"A9"; when x"C02" => DATA <= x"53"; when x"C03" => DATA <= x"85"; when x"C04" => DATA <= x"C4"; when x"C05" => DATA <= x"A2"; when x"C06" => DATA <= x"00"; when x"C07" => DATA <= x"AC"; when x"C08" => DATA <= x"02"; when x"C09" => DATA <= x"B0"; when x"C0A" => DATA <= x"20"; when x"C0B" => DATA <= x"CD"; when x"C0C" => DATA <= x"FC"; when x"C0D" => DATA <= x"F0"; when x"C0E" => DATA <= x"00"; when x"C0F" => DATA <= x"F0"; when x"C10" => DATA <= x"01"; when x"C11" => DATA <= x"E8"; when x"C12" => DATA <= x"C6"; when x"C13" => DATA <= x"C4"; when x"C14" => DATA <= x"D0"; when x"C15" => DATA <= x"F4"; when x"C16" => DATA <= x"E0"; when x"C17" => DATA <= x"0C"; when x"C18" => DATA <= x"66"; when x"C19" => DATA <= x"C0"; when x"C1A" => DATA <= x"90"; when x"C1B" => DATA <= x"E5"; when x"C1C" => DATA <= x"A5"; when x"C1D" => DATA <= x"C0"; when x"C1E" => DATA <= x"28"; when x"C1F" => DATA <= x"A4"; when x"C20" => DATA <= x"C3"; when x"C21" => DATA <= x"A6"; when x"C22" => DATA <= x"EC"; when x"C23" => DATA <= x"48"; when x"C24" => DATA <= x"18"; when x"C25" => DATA <= x"65"; when x"C26" => DATA <= x"DC"; when x"C27" => DATA <= x"85"; when x"C28" => DATA <= x"DC"; when x"C29" => DATA <= x"68"; when x"C2A" => DATA <= x"60"; when x"C2B" => DATA <= x"A5"; when x"C2C" => DATA <= x"CD"; when x"C2D" => DATA <= x"30"; when x"C2E" => DATA <= x"08"; when x"C2F" => DATA <= x"A5"; when x"C30" => DATA <= x"D4"; when x"C31" => DATA <= x"85"; when x"C32" => DATA <= x"CB"; when x"C33" => DATA <= x"A5"; when x"C34" => DATA <= x"D5"; when x"C35" => DATA <= x"85"; when x"C36" => DATA <= x"CC"; when x"C37" => DATA <= x"60"; when x"C38" => DATA <= x"B0"; when x"C39" => DATA <= x"04"; when x"C3A" => DATA <= x"A9"; when x"C3B" => DATA <= x"06"; when x"C3C" => DATA <= x"D0"; when x"C3D" => DATA <= x"02"; when x"C3E" => DATA <= x"A9"; when x"C3F" => DATA <= x"04"; when x"C40" => DATA <= x"A2"; when x"C41" => DATA <= x"07"; when x"C42" => DATA <= x"8E"; when x"C43" => DATA <= x"02"; when x"C44" => DATA <= x"B0"; when x"C45" => DATA <= x"24"; when x"C46" => DATA <= x"EA"; when x"C47" => DATA <= x"D0"; when x"C48" => DATA <= x"2D"; when x"C49" => DATA <= x"C9"; when x"C4A" => DATA <= x"05"; when x"C4B" => DATA <= x"F0"; when x"C4C" => DATA <= x"16"; when x"C4D" => DATA <= x"B0"; when x"C4E" => DATA <= x"09"; when x"C4F" => DATA <= x"20"; when x"C50" => DATA <= x"D1"; when x"C51" => DATA <= x"F7"; when x"C52" => DATA <= x"50"; when x"C53" => DATA <= x"4C"; when x"C54" => DATA <= x"41"; when x"C55" => DATA <= x"59"; when x"C56" => DATA <= x"D0"; when x"C57" => DATA <= x"15"; when x"C58" => DATA <= x"20"; when x"C59" => DATA <= x"D1"; when x"C5A" => DATA <= x"F7"; when x"C5B" => DATA <= x"52"; when x"C5C" => DATA <= x"45"; when x"C5D" => DATA <= x"43"; when x"C5E" => DATA <= x"4F"; when x"C5F" => DATA <= x"52"; when x"C60" => DATA <= x"44"; when x"C61" => DATA <= x"D0"; when x"C62" => DATA <= x"0A"; when x"C63" => DATA <= x"20"; when x"C64" => DATA <= x"D1"; when x"C65" => DATA <= x"F7"; when x"C66" => DATA <= x"52"; when x"C67" => DATA <= x"45"; when x"C68" => DATA <= x"57"; when x"C69" => DATA <= x"49"; when x"C6A" => DATA <= x"4E"; when x"C6B" => DATA <= x"44"; when x"C6C" => DATA <= x"EA"; when x"C6D" => DATA <= x"20"; when x"C6E" => DATA <= x"D1"; when x"C6F" => DATA <= x"F7"; when x"C70" => DATA <= x"20"; when x"C71" => DATA <= x"54"; when x"C72" => DATA <= x"41"; when x"C73" => DATA <= x"50"; when x"C74" => DATA <= x"45"; when x"C75" => DATA <= x"EA"; when x"C76" => DATA <= x"20"; when x"C77" => DATA <= x"E3"; when x"C78" => DATA <= x"FF"; when x"C79" => DATA <= x"4C"; when x"C7A" => DATA <= x"ED"; when x"C7B" => DATA <= x"FF"; when x"C7C" => DATA <= x"86"; when x"C7D" => DATA <= x"EC"; when x"C7E" => DATA <= x"84"; when x"C7F" => DATA <= x"C3"; when x"C80" => DATA <= x"08"; when x"C81" => DATA <= x"78"; when x"C82" => DATA <= x"48"; when x"C83" => DATA <= x"20"; when x"C84" => DATA <= x"23"; when x"C85" => DATA <= x"FC"; when x"C86" => DATA <= x"85"; when x"C87" => DATA <= x"C0"; when x"C88" => DATA <= x"20"; when x"C89" => DATA <= x"D8"; when x"C8A" => DATA <= x"FC"; when x"C8B" => DATA <= x"A9"; when x"C8C" => DATA <= x"0A"; when x"C8D" => DATA <= x"85"; when x"C8E" => DATA <= x"C1"; when x"C8F" => DATA <= x"18"; when x"C90" => DATA <= x"90"; when x"C91" => DATA <= x"0A"; when x"C92" => DATA <= x"A2"; when x"C93" => DATA <= x"07"; when x"C94" => DATA <= x"8E"; when x"C95" => DATA <= x"02"; when x"C96" => DATA <= x"B0"; when x"C97" => DATA <= x"20"; when x"C98" => DATA <= x"DA"; when x"C99" => DATA <= x"FC"; when x"C9A" => DATA <= x"30"; when x"C9B" => DATA <= x"13"; when x"C9C" => DATA <= x"A0"; when x"C9D" => DATA <= x"04"; when x"C9E" => DATA <= x"A9"; when x"C9F" => DATA <= x"04"; when x"CA0" => DATA <= x"8D"; when x"CA1" => DATA <= x"02"; when x"CA2" => DATA <= x"B0"; when x"CA3" => DATA <= x"20"; when x"CA4" => DATA <= x"D8"; when x"CA5" => DATA <= x"FC"; when x"CA6" => DATA <= x"EE"; when x"CA7" => DATA <= x"02"; when x"CA8" => DATA <= x"B0"; when x"CA9" => DATA <= x"20"; when x"CAA" => DATA <= x"D8"; when x"CAB" => DATA <= x"FC"; when x"CAC" => DATA <= x"88"; when x"CAD" => DATA <= x"D0"; when x"CAE" => DATA <= x"EF"; when x"CAF" => DATA <= x"38"; when x"CB0" => DATA <= x"66"; when x"CB1" => DATA <= x"C0"; when x"CB2" => DATA <= x"C6"; when x"CB3" => DATA <= x"C1"; when x"CB4" => DATA <= x"D0"; when x"CB5" => DATA <= x"DA"; when x"CB6" => DATA <= x"A4"; when x"CB7" => DATA <= x"C3"; when x"CB8" => DATA <= x"A6"; when x"CB9" => DATA <= x"EC"; when x"CBA" => DATA <= x"68"; when x"CBB" => DATA <= x"28"; when x"CBC" => DATA <= x"60"; when x"CBD" => DATA <= x"A2"; when x"CBE" => DATA <= x"00"; when x"CBF" => DATA <= x"AC"; when x"CC0" => DATA <= x"02"; when x"CC1" => DATA <= x"B0"; when x"CC2" => DATA <= x"E8"; when x"CC3" => DATA <= x"F0"; when x"CC4" => DATA <= x"07"; when x"CC5" => DATA <= x"20"; when x"CC6" => DATA <= x"CD"; when x"CC7" => DATA <= x"FC"; when x"CC8" => DATA <= x"F0"; when x"CC9" => DATA <= x"F8"; when x"CCA" => DATA <= x"E0"; when x"CCB" => DATA <= x"08"; when x"CCC" => DATA <= x"60"; when x"CCD" => DATA <= x"84"; when x"CCE" => DATA <= x"C5"; when x"CCF" => DATA <= x"AD"; when x"CD0" => DATA <= x"02"; when x"CD1" => DATA <= x"B0"; when x"CD2" => DATA <= x"A8"; when x"CD3" => DATA <= x"45"; when x"CD4" => DATA <= x"C5"; when x"CD5" => DATA <= x"29"; when x"CD6" => DATA <= x"20"; when x"CD7" => DATA <= x"60"; when x"CD8" => DATA <= x"A2"; when x"CD9" => DATA <= x"00"; when x"CDA" => DATA <= x"A9"; when x"CDB" => DATA <= x"10"; when x"CDC" => DATA <= x"2C"; when x"CDD" => DATA <= x"02"; when x"CDE" => DATA <= x"B0"; when x"CDF" => DATA <= x"F0"; when x"CE0" => DATA <= x"FB"; when x"CE1" => DATA <= x"2C"; when x"CE2" => DATA <= x"02"; when x"CE3" => DATA <= x"B0"; when x"CE4" => DATA <= x"D0"; when x"CE5" => DATA <= x"FB"; when x"CE6" => DATA <= x"CA"; when x"CE7" => DATA <= x"10"; when x"CE8" => DATA <= x"F3"; when x"CE9" => DATA <= x"60"; when x"CEA" => DATA <= x"C9"; when x"CEB" => DATA <= x"06"; when x"CEC" => DATA <= x"F0"; when x"CED" => DATA <= x"1D"; when x"CEE" => DATA <= x"C9"; when x"CEF" => DATA <= x"15"; when x"CF0" => DATA <= x"F0"; when x"CF1" => DATA <= x"1F"; when x"CF2" => DATA <= x"A4"; when x"CF3" => DATA <= x"E0"; when x"CF4" => DATA <= x"30"; when x"CF5" => DATA <= x"23"; when x"CF6" => DATA <= x"C9"; when x"CF7" => DATA <= x"1B"; when x"CF8" => DATA <= x"F0"; when x"CF9" => DATA <= x"11"; when x"CFA" => DATA <= x"C9"; when x"CFB" => DATA <= x"07"; when x"CFC" => DATA <= x"F0"; when x"CFD" => DATA <= x"1C"; when x"CFE" => DATA <= x"20"; when x"CFF" => DATA <= x"44"; when x"D00" => DATA <= x"FD"; when x"D01" => DATA <= x"A2"; when x"D02" => DATA <= x"0A"; when x"D03" => DATA <= x"20"; when x"D04" => DATA <= x"C5"; when x"D05" => DATA <= x"FE"; when x"D06" => DATA <= x"D0"; when x"D07" => DATA <= x"21"; when x"D08" => DATA <= x"4C"; when x"D09" => DATA <= x"B7"; when x"D0A" => DATA <= x"FE"; when x"D0B" => DATA <= x"18"; when x"D0C" => DATA <= x"A2"; when x"D0D" => DATA <= x"00"; when x"D0E" => DATA <= x"8E"; when x"D0F" => DATA <= x"00"; when x"D10" => DATA <= x"B0"; when x"D11" => DATA <= x"A2"; when x"D12" => DATA <= x"02"; when x"D13" => DATA <= x"08"; when x"D14" => DATA <= x"16"; when x"D15" => DATA <= x"DE"; when x"D16" => DATA <= x"28"; when x"D17" => DATA <= x"76"; when x"D18" => DATA <= x"DE"; when x"D19" => DATA <= x"60"; when x"D1A" => DATA <= x"A9"; when x"D1B" => DATA <= x"05"; when x"D1C" => DATA <= x"A8"; when x"D1D" => DATA <= x"8D"; when x"D1E" => DATA <= x"03"; when x"D1F" => DATA <= x"B0"; when x"D20" => DATA <= x"CA"; when x"D21" => DATA <= x"D0"; when x"D22" => DATA <= x"FD"; when x"D23" => DATA <= x"49"; when x"D24" => DATA <= x"01"; when x"D25" => DATA <= x"C8"; when x"D26" => DATA <= x"10"; when x"D27" => DATA <= x"F5"; when x"D28" => DATA <= x"60"; when x"D29" => DATA <= x"C9"; when x"D2A" => DATA <= x"20"; when x"D2B" => DATA <= x"90"; when x"D2C" => DATA <= x"17"; when x"D2D" => DATA <= x"69"; when x"D2E" => DATA <= x"1F"; when x"D2F" => DATA <= x"30"; when x"D30" => DATA <= x"02"; when x"D31" => DATA <= x"49"; when x"D32" => DATA <= x"60"; when x"D33" => DATA <= x"20"; when x"D34" => DATA <= x"6B"; when x"D35" => DATA <= x"FE"; when x"D36" => DATA <= x"91"; when x"D37" => DATA <= x"DE"; when x"D38" => DATA <= x"C8"; when x"D39" => DATA <= x"C0"; when x"D3A" => DATA <= x"20"; when x"D3B" => DATA <= x"90"; when x"D3C" => DATA <= x"05"; when x"D3D" => DATA <= x"20"; when x"D3E" => DATA <= x"EC"; when x"D3F" => DATA <= x"FD"; when x"D40" => DATA <= x"A0"; when x"D41" => DATA <= x"00"; when x"D42" => DATA <= x"84"; when x"D43" => DATA <= x"E0"; when x"D44" => DATA <= x"48"; when x"D45" => DATA <= x"20"; when x"D46" => DATA <= x"6B"; when x"D47" => DATA <= x"FE"; when x"D48" => DATA <= x"B1"; when x"D49" => DATA <= x"DE"; when x"D4A" => DATA <= x"45"; when x"D4B" => DATA <= x"E1"; when x"D4C" => DATA <= x"91"; when x"D4D" => DATA <= x"DE"; when x"D4E" => DATA <= x"68"; when x"D4F" => DATA <= x"60"; when x"D50" => DATA <= x"20"; when x"D51" => DATA <= x"35"; when x"D52" => DATA <= x"FE"; when x"D53" => DATA <= x"A9"; when x"D54" => DATA <= x"20"; when x"D55" => DATA <= x"20"; when x"D56" => DATA <= x"6B"; when x"D57" => DATA <= x"FE"; when x"D58" => DATA <= x"91"; when x"D59" => DATA <= x"DE"; when x"D5A" => DATA <= x"10"; when x"D5B" => DATA <= x"E6"; when x"D5C" => DATA <= x"20"; when x"D5D" => DATA <= x"35"; when x"D5E" => DATA <= x"FE"; when x"D5F" => DATA <= x"4C"; when x"D60" => DATA <= x"42"; when x"D61" => DATA <= x"FD"; when x"D62" => DATA <= x"20"; when x"D63" => DATA <= x"EC"; when x"D64" => DATA <= x"FD"; when x"D65" => DATA <= x"A4"; when x"D66" => DATA <= x"E0"; when x"D67" => DATA <= x"10"; when x"D68" => DATA <= x"D9"; when x"D69" => DATA <= x"A0"; when x"D6A" => DATA <= x"80"; when x"D6B" => DATA <= x"84"; when x"D6C" => DATA <= x"E1"; when x"D6D" => DATA <= x"A0"; when x"D6E" => DATA <= x"00"; when x"D6F" => DATA <= x"8C"; when x"D70" => DATA <= x"00"; when x"D71" => DATA <= x"B0"; when x"D72" => DATA <= x"A9"; when x"D73" => DATA <= x"20"; when x"D74" => DATA <= x"99"; when x"D75" => DATA <= x"00"; when x"D76" => DATA <= x"80"; when x"D77" => DATA <= x"99"; when x"D78" => DATA <= x"00"; when x"D79" => DATA <= x"81"; when x"D7A" => DATA <= x"C8"; when x"D7B" => DATA <= x"D0"; when x"D7C" => DATA <= x"F7"; when x"D7D" => DATA <= x"A9"; when x"D7E" => DATA <= x"80"; when x"D7F" => DATA <= x"A0"; when x"D80" => DATA <= x"00"; when x"D81" => DATA <= x"85"; when x"D82" => DATA <= x"DF"; when x"D83" => DATA <= x"84"; when x"D84" => DATA <= x"DE"; when x"D85" => DATA <= x"F0"; when x"D86" => DATA <= x"BB"; when x"D87" => DATA <= x"20"; when x"D88" => DATA <= x"3A"; when x"D89" => DATA <= x"FE"; when x"D8A" => DATA <= x"4C"; when x"D8B" => DATA <= x"42"; when x"D8C" => DATA <= x"FD"; when x"D8D" => DATA <= x"18"; when x"D8E" => DATA <= x"A9"; when x"D8F" => DATA <= x"10"; when x"D90" => DATA <= x"85"; when x"D91" => DATA <= x"E6"; when x"D92" => DATA <= x"A2"; when x"D93" => DATA <= x"08"; when x"D94" => DATA <= x"20"; when x"D95" => DATA <= x"13"; when x"D96" => DATA <= x"FD"; when x"D97" => DATA <= x"4C"; when x"D98" => DATA <= x"44"; when x"D99" => DATA <= x"FD"; when x"D9A" => DATA <= x"A5"; when x"D9B" => DATA <= x"E7"; when x"D9C" => DATA <= x"49"; when x"D9D" => DATA <= x"60"; when x"D9E" => DATA <= x"85"; when x"D9F" => DATA <= x"E7"; when x"DA0" => DATA <= x"B0"; when x"DA1" => DATA <= x"09"; when x"DA2" => DATA <= x"29"; when x"DA3" => DATA <= x"05"; when x"DA4" => DATA <= x"2E"; when x"DA5" => DATA <= x"01"; when x"DA6" => DATA <= x"B0"; when x"DA7" => DATA <= x"2A"; when x"DA8" => DATA <= x"20"; when x"DA9" => DATA <= x"EA"; when x"DAA" => DATA <= x"FC"; when x"DAB" => DATA <= x"4C"; when x"DAC" => DATA <= x"9A"; when x"DAD" => DATA <= x"FE"; when x"DAE" => DATA <= x"A4"; when x"DAF" => DATA <= x"E0"; when x"DB0" => DATA <= x"20"; when x"DB1" => DATA <= x"6B"; when x"DB2" => DATA <= x"FE"; when x"DB3" => DATA <= x"B1"; when x"DB4" => DATA <= x"DE"; when x"DB5" => DATA <= x"45"; when x"DB6" => DATA <= x"E1"; when x"DB7" => DATA <= x"30"; when x"DB8" => DATA <= x"02"; when x"DB9" => DATA <= x"49"; when x"DBA" => DATA <= x"60"; when x"DBB" => DATA <= x"E9"; when x"DBC" => DATA <= x"20"; when x"DBD" => DATA <= x"4C"; when x"DBE" => DATA <= x"E9"; when x"DBF" => DATA <= x"FD"; when x"DC0" => DATA <= x"A9"; when x"DC1" => DATA <= x"5F"; when x"DC2" => DATA <= x"49"; when x"DC3" => DATA <= x"20"; when x"DC4" => DATA <= x"D0"; when x"DC5" => DATA <= x"23"; when x"DC6" => DATA <= x"45"; when x"DC7" => DATA <= x"E7"; when x"DC8" => DATA <= x"2C"; when x"DC9" => DATA <= x"01"; when x"DCA" => DATA <= x"B0"; when x"DCB" => DATA <= x"30"; when x"DCC" => DATA <= x"02"; when x"DCD" => DATA <= x"49"; when x"DCE" => DATA <= x"60"; when x"DCF" => DATA <= x"4C"; when x"DD0" => DATA <= x"DF"; when x"DD1" => DATA <= x"FD"; when x"DD2" => DATA <= x"69"; when x"DD3" => DATA <= x"39"; when x"DD4" => DATA <= x"90"; when x"DD5" => DATA <= x"F2"; when x"DD6" => DATA <= x"49"; when x"DD7" => DATA <= x"10"; when x"DD8" => DATA <= x"2C"; when x"DD9" => DATA <= x"01"; when x"DDA" => DATA <= x"B0"; when x"DDB" => DATA <= x"30"; when x"DDC" => DATA <= x"02"; when x"DDD" => DATA <= x"49"; when x"DDE" => DATA <= x"10"; when x"DDF" => DATA <= x"18"; when x"DE0" => DATA <= x"69"; when x"DE1" => DATA <= x"20"; when x"DE2" => DATA <= x"2C"; when x"DE3" => DATA <= x"01"; when x"DE4" => DATA <= x"B0"; when x"DE5" => DATA <= x"70"; when x"DE6" => DATA <= x"02"; when x"DE7" => DATA <= x"29"; when x"DE8" => DATA <= x"1F"; when x"DE9" => DATA <= x"4C"; when x"DEA" => DATA <= x"60"; when x"DEB" => DATA <= x"FE"; when x"DEC" => DATA <= x"A5"; when x"DED" => DATA <= x"DE"; when x"DEE" => DATA <= x"A4"; when x"DEF" => DATA <= x"DF"; when x"DF0" => DATA <= x"C0"; when x"DF1" => DATA <= x"81"; when x"DF2" => DATA <= x"90"; when x"DF3" => DATA <= x"38"; when x"DF4" => DATA <= x"C9"; when x"DF5" => DATA <= x"E0"; when x"DF6" => DATA <= x"90"; when x"DF7" => DATA <= x"34"; when x"DF8" => DATA <= x"A4"; when x"DF9" => DATA <= x"E6"; when x"DFA" => DATA <= x"30"; when x"DFB" => DATA <= x"0C"; when x"DFC" => DATA <= x"88"; when x"DFD" => DATA <= x"D0"; when x"DFE" => DATA <= x"07"; when x"DFF" => DATA <= x"20"; when x"E00" => DATA <= x"71"; when x"E01" => DATA <= x"FE"; when x"E02" => DATA <= x"B0"; when x"E03" => DATA <= x"FB"; when x"E04" => DATA <= x"A0"; when x"E05" => DATA <= x"10"; when x"E06" => DATA <= x"84"; when x"E07" => DATA <= x"E6"; when x"E08" => DATA <= x"A0"; when x"E09" => DATA <= x"20"; when x"E0A" => DATA <= x"20"; when x"E0B" => DATA <= x"66"; when x"E0C" => DATA <= x"FE"; when x"E0D" => DATA <= x"B9"; when x"E0E" => DATA <= x"00"; when x"E0F" => DATA <= x"80"; when x"E10" => DATA <= x"99"; when x"E11" => DATA <= x"E0"; when x"E12" => DATA <= x"7F"; when x"E13" => DATA <= x"C8"; when x"E14" => DATA <= x"D0"; when x"E15" => DATA <= x"F7"; when x"E16" => DATA <= x"20"; when x"E17" => DATA <= x"6B"; when x"E18" => DATA <= x"FE"; when x"E19" => DATA <= x"B9"; when x"E1A" => DATA <= x"00"; when x"E1B" => DATA <= x"81"; when x"E1C" => DATA <= x"99"; when x"E1D" => DATA <= x"E0"; when x"E1E" => DATA <= x"80"; when x"E1F" => DATA <= x"C8"; when x"E20" => DATA <= x"D0"; when x"E21" => DATA <= x"F7"; when x"E22" => DATA <= x"A0"; when x"E23" => DATA <= x"1F"; when x"E24" => DATA <= x"A9"; when x"E25" => DATA <= x"20"; when x"E26" => DATA <= x"91"; when x"E27" => DATA <= x"DE"; when x"E28" => DATA <= x"88"; when x"E29" => DATA <= x"10"; when x"E2A" => DATA <= x"FB"; when x"E2B" => DATA <= x"60"; when x"E2C" => DATA <= x"69"; when x"E2D" => DATA <= x"20"; when x"E2E" => DATA <= x"85"; when x"E2F" => DATA <= x"DE"; when x"E30" => DATA <= x"D0"; when x"E31" => DATA <= x"02"; when x"E32" => DATA <= x"E6"; when x"E33" => DATA <= x"DF"; when x"E34" => DATA <= x"60"; when x"E35" => DATA <= x"88"; when x"E36" => DATA <= x"10"; when x"E37" => DATA <= x"19"; when x"E38" => DATA <= x"A0"; when x"E39" => DATA <= x"1F"; when x"E3A" => DATA <= x"A5"; when x"E3B" => DATA <= x"DE"; when x"E3C" => DATA <= x"D0"; when x"E3D" => DATA <= x"0B"; when x"E3E" => DATA <= x"A6"; when x"E3F" => DATA <= x"DF"; when x"E40" => DATA <= x"E0"; when x"E41" => DATA <= x"80"; when x"E42" => DATA <= x"D0"; when x"E43" => DATA <= x"05"; when x"E44" => DATA <= x"68"; when x"E45" => DATA <= x"68"; when x"E46" => DATA <= x"4C"; when x"E47" => DATA <= x"65"; when x"E48" => DATA <= x"FD"; when x"E49" => DATA <= x"E9"; when x"E4A" => DATA <= x"20"; when x"E4B" => DATA <= x"85"; when x"E4C" => DATA <= x"DE"; when x"E4D" => DATA <= x"B0"; when x"E4E" => DATA <= x"02"; when x"E4F" => DATA <= x"C6"; when x"E50" => DATA <= x"DF"; when x"E51" => DATA <= x"60"; when x"E52" => DATA <= x"20"; when x"E53" => DATA <= x"FB"; when x"E54" => DATA <= x"FE"; when x"E55" => DATA <= x"08"; when x"E56" => DATA <= x"48"; when x"E57" => DATA <= x"D8"; when x"E58" => DATA <= x"84"; when x"E59" => DATA <= x"E5"; when x"E5A" => DATA <= x"86"; when x"E5B" => DATA <= x"E4"; when x"E5C" => DATA <= x"20"; when x"E5D" => DATA <= x"EA"; when x"E5E" => DATA <= x"FC"; when x"E5F" => DATA <= x"68"; when x"E60" => DATA <= x"A6"; when x"E61" => DATA <= x"E4"; when x"E62" => DATA <= x"A4"; when x"E63" => DATA <= x"E5"; when x"E64" => DATA <= x"28"; when x"E65" => DATA <= x"60"; when x"E66" => DATA <= x"2C"; when x"E67" => DATA <= x"02"; when x"E68" => DATA <= x"B0"; when x"E69" => DATA <= x"10"; when x"E6A" => DATA <= x"FB"; when x"E6B" => DATA <= x"2C"; when x"E6C" => DATA <= x"02"; when x"E6D" => DATA <= x"B0"; when x"E6E" => DATA <= x"30"; when x"E6F" => DATA <= x"FB"; when x"E70" => DATA <= x"60"; when x"E71" => DATA <= x"A0"; when x"E72" => DATA <= x"3B"; when x"E73" => DATA <= x"18"; when x"E74" => DATA <= x"A9"; when x"E75" => DATA <= x"20"; when x"E76" => DATA <= x"A2"; when x"E77" => DATA <= x"0A"; when x"E78" => DATA <= x"2C"; when x"E79" => DATA <= x"01"; when x"E7A" => DATA <= x"B0"; when x"E7B" => DATA <= x"F0"; when x"E7C" => DATA <= x"08"; when x"E7D" => DATA <= x"EE"; when x"E7E" => DATA <= x"00"; when x"E7F" => DATA <= x"B0"; when x"E80" => DATA <= x"88"; when x"E81" => DATA <= x"CA"; when x"E82" => DATA <= x"D0"; when x"E83" => DATA <= x"F4"; when x"E84" => DATA <= x"4A"; when x"E85" => DATA <= x"08"; when x"E86" => DATA <= x"48"; when x"E87" => DATA <= x"AD"; when x"E88" => DATA <= x"00"; when x"E89" => DATA <= x"B0"; when x"E8A" => DATA <= x"29"; when x"E8B" => DATA <= x"F0"; when x"E8C" => DATA <= x"8D"; when x"E8D" => DATA <= x"00"; when x"E8E" => DATA <= x"B0"; when x"E8F" => DATA <= x"68"; when x"E90" => DATA <= x"28"; when x"E91" => DATA <= x"D0"; when x"E92" => DATA <= x"E3"; when x"E93" => DATA <= x"60"; when x"E94" => DATA <= x"08"; when x"E95" => DATA <= x"D8"; when x"E96" => DATA <= x"86"; when x"E97" => DATA <= x"E4"; when x"E98" => DATA <= x"84"; when x"E99" => DATA <= x"E5"; when x"E9A" => DATA <= x"2C"; when x"E9B" => DATA <= x"02"; when x"E9C" => DATA <= x"B0"; when x"E9D" => DATA <= x"50"; when x"E9E" => DATA <= x"05"; when x"E9F" => DATA <= x"20"; when x"EA0" => DATA <= x"71"; when x"EA1" => DATA <= x"FE"; when x"EA2" => DATA <= x"90"; when x"EA3" => DATA <= x"F6"; when x"EA4" => DATA <= x"20"; when x"EA5" => DATA <= x"8A"; when x"EA6" => DATA <= x"FB"; when x"EA7" => DATA <= x"20"; when x"EA8" => DATA <= x"71"; when x"EA9" => DATA <= x"FE"; when x"EAA" => DATA <= x"B0"; when x"EAB" => DATA <= x"FB"; when x"EAC" => DATA <= x"20"; when x"EAD" => DATA <= x"71"; when x"EAE" => DATA <= x"FE"; when x"EAF" => DATA <= x"B0"; when x"EB0" => DATA <= x"F6"; when x"EB1" => DATA <= x"98"; when x"EB2" => DATA <= x"A2"; when x"EB3" => DATA <= x"17"; when x"EB4" => DATA <= x"20"; when x"EB5" => DATA <= x"C5"; when x"EB6" => DATA <= x"FE"; when x"EB7" => DATA <= x"BD"; when x"EB8" => DATA <= x"E3"; when x"EB9" => DATA <= x"FE"; when x"EBA" => DATA <= x"85"; when x"EBB" => DATA <= x"E2"; when x"EBC" => DATA <= x"A9"; when x"EBD" => DATA <= x"FD"; when x"EBE" => DATA <= x"85"; when x"EBF" => DATA <= x"E3"; when x"EC0" => DATA <= x"98"; when x"EC1" => DATA <= x"6C"; when x"EC2" => DATA <= x"E2"; when x"EC3" => DATA <= x"00"; when x"EC4" => DATA <= x"CA"; when x"EC5" => DATA <= x"DD"; when x"EC6" => DATA <= x"CB"; when x"EC7" => DATA <= x"FE"; when x"EC8" => DATA <= x"90"; when x"EC9" => DATA <= x"FA"; when x"ECA" => DATA <= x"60"; when x"ECB" => DATA <= x"00"; when x"ECC" => DATA <= x"08"; when x"ECD" => DATA <= x"09"; when x"ECE" => DATA <= x"0A"; when x"ECF" => DATA <= x"0B"; when x"ED0" => DATA <= x"0C"; when x"ED1" => DATA <= x"0D"; when x"ED2" => DATA <= x"0E"; when x"ED3" => DATA <= x"0F"; when x"ED4" => DATA <= x"1E"; when x"ED5" => DATA <= x"7F"; when x"ED6" => DATA <= x"00"; when x"ED7" => DATA <= x"01"; when x"ED8" => DATA <= x"05"; when x"ED9" => DATA <= x"06"; when x"EDA" => DATA <= x"08"; when x"EDB" => DATA <= x"0E"; when x"EDC" => DATA <= x"0F"; when x"EDD" => DATA <= x"10"; when x"EDE" => DATA <= x"11"; when x"EDF" => DATA <= x"1C"; when x"EE0" => DATA <= x"20"; when x"EE1" => DATA <= x"21"; when x"EE2" => DATA <= x"3B"; when x"EE3" => DATA <= x"44"; when x"EE4" => DATA <= x"5C"; when x"EE5" => DATA <= x"38"; when x"EE6" => DATA <= x"62"; when x"EE7" => DATA <= x"87"; when x"EE8" => DATA <= x"69"; when x"EE9" => DATA <= x"40"; when x"EEA" => DATA <= x"8D"; when x"EEB" => DATA <= x"92"; when x"EEC" => DATA <= x"7D"; when x"EED" => DATA <= x"50"; when x"EEE" => DATA <= x"DF"; when x"EEF" => DATA <= x"D2"; when x"EF0" => DATA <= x"9A"; when x"EF1" => DATA <= x"A2"; when x"EF2" => DATA <= x"E2"; when x"EF3" => DATA <= x"AE"; when x"EF4" => DATA <= x"C0"; when x"EF5" => DATA <= x"DF"; when x"EF6" => DATA <= x"D8"; when x"EF7" => DATA <= x"D6"; when x"EF8" => DATA <= x"C8"; when x"EF9" => DATA <= x"C6"; when x"EFA" => DATA <= x"C2"; when x"EFB" => DATA <= x"48"; when x"EFC" => DATA <= x"C9"; when x"EFD" => DATA <= x"02"; when x"EFE" => DATA <= x"F0"; when x"EFF" => DATA <= x"27"; when x"F00" => DATA <= x"C9"; when x"F01" => DATA <= x"03"; when x"F02" => DATA <= x"F0"; when x"F03" => DATA <= x"34"; when x"F04" => DATA <= x"C5"; when x"F05" => DATA <= x"FE"; when x"F06" => DATA <= x"F0"; when x"F07" => DATA <= x"2E"; when x"F08" => DATA <= x"AD"; when x"F09" => DATA <= x"0C"; when x"F0A" => DATA <= x"B8"; when x"F0B" => DATA <= x"29"; when x"F0C" => DATA <= x"0E"; when x"F0D" => DATA <= x"F0"; when x"F0E" => DATA <= x"27"; when x"F0F" => DATA <= x"68"; when x"F10" => DATA <= x"2C"; when x"F11" => DATA <= x"01"; when x"F12" => DATA <= x"B8"; when x"F13" => DATA <= x"30"; when x"F14" => DATA <= x"FB"; when x"F15" => DATA <= x"8D"; when x"F16" => DATA <= x"01"; when x"F17" => DATA <= x"B8"; when x"F18" => DATA <= x"48"; when x"F19" => DATA <= x"AD"; when x"F1A" => DATA <= x"0C"; when x"F1B" => DATA <= x"B8"; when x"F1C" => DATA <= x"29"; when x"F1D" => DATA <= x"F0"; when x"F1E" => DATA <= x"09"; when x"F1F" => DATA <= x"0C"; when x"F20" => DATA <= x"8D"; when x"F21" => DATA <= x"0C"; when x"F22" => DATA <= x"B8"; when x"F23" => DATA <= x"09"; when x"F24" => DATA <= x"02"; when x"F25" => DATA <= x"D0"; when x"F26" => DATA <= x"0C"; when x"F27" => DATA <= x"A9"; when x"F28" => DATA <= x"7F"; when x"F29" => DATA <= x"8D"; when x"F2A" => DATA <= x"03"; when x"F2B" => DATA <= x"B8"; when x"F2C" => DATA <= x"AD"; when x"F2D" => DATA <= x"0C"; when x"F2E" => DATA <= x"B8"; when x"F2F" => DATA <= x"29"; when x"F30" => DATA <= x"F0"; when x"F31" => DATA <= x"09"; when x"F32" => DATA <= x"0E"; when x"F33" => DATA <= x"8D"; when x"F34" => DATA <= x"0C"; when x"F35" => DATA <= x"B8"; when x"F36" => DATA <= x"68"; when x"F37" => DATA <= x"60"; when x"F38" => DATA <= x"AD"; when x"F39" => DATA <= x"0C"; when x"F3A" => DATA <= x"B8"; when x"F3B" => DATA <= x"29"; when x"F3C" => DATA <= x"F0"; when x"F3D" => DATA <= x"B0"; when x"F3E" => DATA <= x"F4"; when x"F3F" => DATA <= x"A2"; when x"F40" => DATA <= x"17"; when x"F41" => DATA <= x"BD"; when x"F42" => DATA <= x"9A"; when x"F43" => DATA <= x"FF"; when x"F44" => DATA <= x"9D"; when x"F45" => DATA <= x"04"; when x"F46" => DATA <= x"02"; when x"F47" => DATA <= x"CA"; when x"F48" => DATA <= x"10"; when x"F49" => DATA <= x"F7"; when x"F4A" => DATA <= x"9A"; when x"F4B" => DATA <= x"8A"; when x"F4C" => DATA <= x"E8"; when x"F4D" => DATA <= x"86"; when x"F4E" => DATA <= x"EA"; when x"F4F" => DATA <= x"86"; when x"F50" => DATA <= x"E1"; when x"F51" => DATA <= x"86"; when x"F52" => DATA <= x"E7"; when x"F53" => DATA <= x"A2"; when x"F54" => DATA <= x"33"; when x"F55" => DATA <= x"9D"; when x"F56" => DATA <= x"EB"; when x"F57" => DATA <= x"02"; when x"F58" => DATA <= x"CA"; when x"F59" => DATA <= x"10"; when x"F5A" => DATA <= x"FA"; when x"F5B" => DATA <= x"A9"; when x"F5C" => DATA <= x"0A"; when x"F5D" => DATA <= x"85"; when x"F5E" => DATA <= x"FE"; when x"F5F" => DATA <= x"A9"; when x"F60" => DATA <= x"8A"; when x"F61" => DATA <= x"8D"; when x"F62" => DATA <= x"03"; when x"F63" => DATA <= x"B0"; when x"F64" => DATA <= x"A9"; when x"F65" => DATA <= x"07"; when x"F66" => DATA <= x"8D"; when x"F67" => DATA <= x"02"; when x"F68" => DATA <= x"B0"; when x"F69" => DATA <= x"2C"; when x"F6A" => DATA <= x"01"; when x"F6B" => DATA <= x"B0"; when x"F6C" => DATA <= x"50"; when x"F6D" => DATA <= x"11"; when x"F6E" => DATA <= x"AD"; when x"F6F" => DATA <= x"FE"; when x"F70" => DATA <= x"BF"; when x"F71" => DATA <= x"29"; when x"F72" => DATA <= x"10"; when x"F73" => DATA <= x"F0"; when x"F74" => DATA <= x"0A"; when x"F75" => DATA <= x"A9"; when x"F76" => DATA <= x"83"; when x"F77" => DATA <= x"8D"; when x"F78" => DATA <= x"FE"; when x"F79" => DATA <= x"BF"; when x"F7A" => DATA <= x"6C"; when x"F7B" => DATA <= x"FE"; when x"F7C" => DATA <= x"7F"; when x"F7D" => DATA <= x"EA"; when x"F7E" => DATA <= x"EA"; when x"F7F" => DATA <= x"20"; when x"F80" => DATA <= x"D1"; when x"F81" => DATA <= x"F7"; when x"F82" => DATA <= x"06"; when x"F83" => DATA <= x"0C"; when x"F84" => DATA <= x"0F"; when x"F85" => DATA <= x"41"; when x"F86" => DATA <= x"43"; when x"F87" => DATA <= x"4F"; when x"F88" => DATA <= x"52"; when x"F89" => DATA <= x"4E"; when x"F8A" => DATA <= x"20"; when x"F8B" => DATA <= x"41"; when x"F8C" => DATA <= x"54"; when x"F8D" => DATA <= x"4F"; when x"F8E" => DATA <= x"4D"; when x"F8F" => DATA <= x"0A"; when x"F90" => DATA <= x"0A"; when x"F91" => DATA <= x"0D"; when x"F92" => DATA <= x"EA"; when x"F93" => DATA <= x"58"; when x"F94" => DATA <= x"4C"; when x"F95" => DATA <= x"00"; when x"F96" => DATA <= x"E0"; when x"F97" => DATA <= x"EA"; when x"F98" => DATA <= x"EA"; when x"F99" => DATA <= x"EA"; when x"F9A" => DATA <= x"00"; when x"F9B" => DATA <= x"A0"; when x"F9C" => DATA <= x"EF"; when x"F9D" => DATA <= x"F8"; when x"F9E" => DATA <= x"52"; when x"F9F" => DATA <= x"FE"; when x"FA0" => DATA <= x"94"; when x"FA1" => DATA <= x"FE"; when x"FA2" => DATA <= x"6E"; when x"FA3" => DATA <= x"F9"; when x"FA4" => DATA <= x"E5"; when x"FA5" => DATA <= x"FA"; when x"FA6" => DATA <= x"AC"; when x"FA7" => DATA <= x"C2"; when x"FA8" => DATA <= x"AC"; when x"FA9" => DATA <= x"C2"; when x"FAA" => DATA <= x"EE"; when x"FAB" => DATA <= x"FB"; when x"FAC" => DATA <= x"7C"; when x"FAD" => DATA <= x"FC"; when x"FAE" => DATA <= x"38"; when x"FAF" => DATA <= x"FC"; when x"FB0" => DATA <= x"78"; when x"FB1" => DATA <= x"C2"; when x"FB2" => DATA <= x"85"; when x"FB3" => DATA <= x"FF"; when x"FB4" => DATA <= x"68"; when x"FB5" => DATA <= x"48"; when x"FB6" => DATA <= x"29"; when x"FB7" => DATA <= x"10"; when x"FB8" => DATA <= x"D0"; when x"FB9" => DATA <= x"06"; when x"FBA" => DATA <= x"A5"; when x"FBB" => DATA <= x"FF"; when x"FBC" => DATA <= x"48"; when x"FBD" => DATA <= x"6C"; when x"FBE" => DATA <= x"04"; when x"FBF" => DATA <= x"02"; when x"FC0" => DATA <= x"A5"; when x"FC1" => DATA <= x"FF"; when x"FC2" => DATA <= x"28"; when x"FC3" => DATA <= x"08"; when x"FC4" => DATA <= x"6C"; when x"FC5" => DATA <= x"02"; when x"FC6" => DATA <= x"02"; when x"FC7" => DATA <= x"48"; when x"FC8" => DATA <= x"6C"; when x"FC9" => DATA <= x"00"; when x"FCA" => DATA <= x"02"; when x"FCB" => DATA <= x"6C"; when x"FCC" => DATA <= x"1A"; when x"FCD" => DATA <= x"02"; when x"FCE" => DATA <= x"6C"; when x"FCF" => DATA <= x"18"; when x"FD0" => DATA <= x"02"; when x"FD1" => DATA <= x"6C"; when x"FD2" => DATA <= x"16"; when x"FD3" => DATA <= x"02"; when x"FD4" => DATA <= x"6C"; when x"FD5" => DATA <= x"14"; when x"FD6" => DATA <= x"02"; when x"FD7" => DATA <= x"6C"; when x"FD8" => DATA <= x"12"; when x"FD9" => DATA <= x"02"; when x"FDA" => DATA <= x"6C"; when x"FDB" => DATA <= x"10"; when x"FDC" => DATA <= x"02"; when x"FDD" => DATA <= x"6C"; when x"FDE" => DATA <= x"0E"; when x"FDF" => DATA <= x"02"; when x"FE0" => DATA <= x"6C"; when x"FE1" => DATA <= x"0C"; when x"FE2" => DATA <= x"02"; when x"FE3" => DATA <= x"6C"; when x"FE4" => DATA <= x"0A"; when x"FE5" => DATA <= x"02"; when x"FE6" => DATA <= x"20"; when x"FE7" => DATA <= x"E3"; when x"FE8" => DATA <= x"FF"; when x"FE9" => DATA <= x"C9"; when x"FEA" => DATA <= x"0D"; when x"FEB" => DATA <= x"D0"; when x"FEC" => DATA <= x"07"; when x"FED" => DATA <= x"A9"; when x"FEE" => DATA <= x"0A"; when x"FEF" => DATA <= x"20"; when x"FF0" => DATA <= x"F4"; when x"FF1" => DATA <= x"FF"; when x"FF2" => DATA <= x"A9"; when x"FF3" => DATA <= x"0D"; when x"FF4" => DATA <= x"6C"; when x"FF5" => DATA <= x"08"; when x"FF6" => DATA <= x"02"; when x"FF7" => DATA <= x"6C"; when x"FF8" => DATA <= x"06"; when x"FF9" => DATA <= x"02"; when x"FFA" => DATA <= x"C7"; when x"FFB" => DATA <= x"FF"; when x"FFC" => DATA <= x"3F"; when x"FFD" => DATA <= x"FF"; when x"FFE" => DATA <= x"B2"; when x"FFF" => DATA <= x"FF"; when others => DATA <= (others => '0'); end case; end process; end RTL;
apache-2.0
d3cd250e729f6adfa4a73d53345e859a
0.358259
2.919298
false
false
false
false
msiddalingaiah/TTA
VHDL/ProgramMemory.vhd
1
2,650
-------------------------------------------------------------------------------- -- Copyright 2014 Madhu Siddalingaiah -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -- Entity: ProgramMemory -- Date: 2014-10-09 -- Author: Madhu -- -- Description: -------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; -- Avoid using ieee.std_logic_arith.all use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; entity ProgramMemory is generic ( DATA_WIDTH : integer := 16; ADDRESS_WIDTH : integer := 16; DEPTH : natural := 8192 ); port ( reset : in std_logic; clock : in std_logic; data_in : in std_logic_vector(DATA_WIDTH-1 downto 0); pc_in : in std_logic_vector(ADDRESS_WIDTH-1 downto 0); data_out : out std_logic_vector(DATA_WIDTH-1 downto 0); pc_out : out std_logic_vector(ADDRESS_WIDTH-1 downto 0); memory_write : in std_logic; pc_write : in std_logic ); end ProgramMemory; architecture arch of ProgramMemory is type MemoryType is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0); signal store : MemoryType; -- Initialization to '0' avoids NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 signal program_counter : std_logic_vector(DATA_WIDTH-1 downto 0) := (others => '0'); begin top: block begin -- Asynchronous assignments pc_out <= program_counter; data_out <= store(to_integer(unsigned(program_counter))); process(clock, reset) begin if reset = '1' then program_counter <= (others => '0'); elsif rising_edge(clock) then if pc_write = '1' then program_counter <= pc_in; else program_counter <= program_counter + 1; end if; if memory_write = '1' then store(to_integer(unsigned(program_counter))) <= data_in; end if; end if; end process; end block; end arch;
apache-2.0
54b1128cc54f427abe1dcf3b0db4e588
0.578491
4.021244
false
false
false
false
tghaefli/ADD
EDK/IVK_Repos/IVK_IPLib/pcores/sg_xsvi_fanin_plbw_v1_01_a/hdl/vhdl/sg_xsvi_fanin_plbw.vhd
1
10,003
------------------------------------------------------------------- -- System Generator version 11.1.00 VHDL source file. -- -- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2007 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; entity plbaddrpref is generic ( C_BASEADDR : std_logic_vector(31 downto 0) := X"80000000"; C_HIGHADDR : std_logic_vector(31 downto 0) := X"8000FFFF"; C_SPLB_DWIDTH : integer range 32 to 128 := 32; C_SPLB_NATIVE_DWIDTH : integer range 32 to 32 := 32 ); port ( addrpref : out std_logic_vector(20-1 downto 0); sl_rddbus : out std_logic_vector(0 to C_SPLB_DWIDTH-1); plb_wrdbus : in std_logic_vector(0 to C_SPLB_DWIDTH-1); sgsl_rddbus : in std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH-1); sgplb_wrdbus : out std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH-1) ); end plbaddrpref; architecture behavior of plbaddrpref is signal sl_rddbus_i : std_logic_vector(0 to C_SPLB_DWIDTH-1); begin addrpref <= C_BASEADDR(32-1 downto 12); ------------------------------------------------------------------------------- -- Mux/Steer data/be's correctly for connect 32-bit slave to 128-bit plb ------------------------------------------------------------------------------- GEN_128_TO_32_SLAVE : if C_SPLB_NATIVE_DWIDTH = 32 and C_SPLB_DWIDTH = 128 generate begin ----------------------------------------------------------------------- -- Map lower rd data to each quarter of the plb slave read bus ----------------------------------------------------------------------- sl_rddbus_i(0 to 31) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1); sl_rddbus_i(32 to 63) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1); sl_rddbus_i(64 to 95) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1); sl_rddbus_i(96 to 127) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1); end generate GEN_128_TO_32_SLAVE; ------------------------------------------------------------------------------- -- Mux/Steer data/be's correctly for connect 32-bit slave to 64-bit plb ------------------------------------------------------------------------------- GEN_64_TO_32_SLAVE : if C_SPLB_NATIVE_DWIDTH = 32 and C_SPLB_DWIDTH = 64 generate begin --------------------------------------------------------------------------- -- Map lower rd data to upper and lower halves of plb slave read bus --------------------------------------------------------------------------- sl_rddbus_i(0 to 31) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1); sl_rddbus_i(32 to 63) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1); end generate GEN_64_TO_32_SLAVE; ------------------------------------------------------------------------------- -- IPIF DWidth = PLB DWidth -- If IPIF Slave Data width is equal to the PLB Bus Data Width -- Then BE and Read Data Bus map directly to eachother. ------------------------------------------------------------------------------- GEN_FOR_EQUAL_SLAVE : if C_SPLB_NATIVE_DWIDTH = C_SPLB_DWIDTH generate sl_rddbus_i <= sgsl_rddbus; end generate GEN_FOR_EQUAL_SLAVE; sl_rddbus <= sl_rddbus_i; sgplb_wrdbus <= plb_wrdbus(0 to C_SPLB_NATIVE_DWIDTH-1); end behavior; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity sg_xsvi_fanin_plbw is generic ( C_BASEADDR: std_logic_vector(31 downto 0) := X"80000000"; C_HIGHADDR: std_logic_vector(31 downto 0) := X"80000FFF"; C_SPLB_AWIDTH: integer := 0; C_SPLB_DWIDTH: integer := 0; C_SPLB_MID_WIDTH: integer := 0; C_SPLB_NATIVE_DWIDTH: integer := 0; C_SPLB_NUM_MASTERS: integer := 0; C_SPLB_SUPPORT_BURSTS: integer := 0 ); port ( active_video_i: in std_logic; hblank_i: in std_logic; hsync_i: in std_logic; plb_abus: in std_logic_vector(0 to 31); plb_pavalid: in std_logic; plb_rnw: in std_logic; plb_wrdbus: in std_logic_vector(0 to C_SPLB_DWIDTH-1); splb_clk: in std_logic; splb_rst: in std_logic; sysgen_clk: in std_logic; vblank_i: in std_logic; video_data_i: in std_logic_vector(0 to 23); vsync_i: in std_logic; active_video_o: out std_logic; hblank_o: out std_logic; hsync_o: out std_logic; sl_addrack: out std_logic; sl_rdcomp: out std_logic; sl_rddack: out std_logic; sl_rddbus: out std_logic_vector(0 to C_SPLB_DWIDTH-1); sl_wait: out std_logic; sl_wrcomp: out std_logic; sl_wrdack: out std_logic; vblank_o: out std_logic; video_data_o: out std_logic_vector(0 to 23); vsync_o: out std_logic ); end sg_xsvi_fanin_plbw; architecture structural of sg_xsvi_fanin_plbw is signal active_video_i_x0: std_logic; signal active_video_o_x0: std_logic; signal clk: std_logic; signal hblank_i_x0: std_logic; signal hblank_o_x0: std_logic; signal hsync_i_x0: std_logic; signal hsync_o_x0: std_logic; signal plb_abus_x0: std_logic_vector(31 downto 0); signal plb_pavalid_x0: std_logic; signal plb_rnw_x0: std_logic; signal plbaddrpref_addrpref_net: std_logic_vector(19 downto 0); signal plbaddrpref_plb_wrdbus_net: std_logic_vector(C_SPLB_DWIDTH-1 downto 0); signal plbaddrpref_sgplb_wrdbus_net: std_logic_vector(31 downto 0); signal plbaddrpref_sgsl_rddbus_net: std_logic_vector(31 downto 0); signal plbaddrpref_sl_rddbus_net: std_logic_vector(C_SPLB_DWIDTH-1 downto 0); signal sl_addrack_x0: std_logic; signal sl_rdcomp_x0: std_logic; signal sl_rddack_x0: std_logic; signal sl_wait_x0: std_logic; signal sl_wrcomp_x0: std_logic; signal sl_wrdack_x0: std_logic; signal splb_rst_x0: std_logic; signal vblank_i_x0: std_logic; signal vblank_o_x0: std_logic; signal video_data_i_x0: std_logic_vector(23 downto 0); signal video_data_o_x0: std_logic_vector(23 downto 0); signal vsync_i_x0: std_logic; signal vsync_o_x0: std_logic; signal xps_clk: std_logic; begin active_video_i_x0 <= active_video_i; hblank_i_x0 <= hblank_i; hsync_i_x0 <= hsync_i; plb_abus_x0 <= plb_abus; plb_pavalid_x0 <= plb_pavalid; plb_rnw_x0 <= plb_rnw; plbaddrpref_plb_wrdbus_net <= plb_wrdbus; xps_clk <= splb_clk; splb_rst_x0 <= splb_rst; clk <= sysgen_clk; vblank_i_x0 <= vblank_i; video_data_i_x0 <= video_data_i; vsync_i_x0 <= vsync_i; active_video_o <= active_video_o_x0; hblank_o <= hblank_o_x0; hsync_o <= hsync_o_x0; sl_addrack <= sl_addrack_x0; sl_rdcomp <= sl_rdcomp_x0; sl_rddack <= sl_rddack_x0; sl_rddbus <= plbaddrpref_sl_rddbus_net; sl_wait <= sl_wait_x0; sl_wrcomp <= sl_wrcomp_x0; sl_wrdack <= sl_wrdack_x0; vblank_o <= vblank_o_x0; video_data_o <= video_data_o_x0; vsync_o <= vsync_o_x0; plbaddrpref_x0: entity work.plbaddrpref generic map ( C_BASEADDR => C_BASEADDR, C_HIGHADDR => C_HIGHADDR, C_SPLB_DWIDTH => C_SPLB_DWIDTH, C_SPLB_NATIVE_DWIDTH => C_SPLB_NATIVE_DWIDTH ) port map ( plb_wrdbus => plbaddrpref_plb_wrdbus_net, sgsl_rddbus => plbaddrpref_sgsl_rddbus_net, addrpref => plbaddrpref_addrpref_net, sgplb_wrdbus => plbaddrpref_sgplb_wrdbus_net, sl_rddbus => plbaddrpref_sl_rddbus_net ); sysgen_dut: entity work.sg_xsvi_fanin_cw port map ( active_video_i => active_video_i_x0, clk => clk, hblank_i => hblank_i_x0, hsync_i => hsync_i_x0, plb_abus => plb_abus_x0, plb_pavalid => plb_pavalid_x0, plb_rnw => plb_rnw_x0, plb_wrdbus => plbaddrpref_sgplb_wrdbus_net, sg_plb_addrpref => plbaddrpref_addrpref_net, splb_rst => splb_rst_x0, vblank_i => vblank_i_x0, video_data_i => video_data_i_x0, vsync_i => vsync_i_x0, xps_clk => xps_clk, active_video_o => active_video_o_x0, hblank_o => hblank_o_x0, hsync_o => hsync_o_x0, sl_addrack => sl_addrack_x0, sl_rdcomp => sl_rdcomp_x0, sl_rddack => sl_rddack_x0, sl_rddbus => plbaddrpref_sgsl_rddbus_net, sl_wait => sl_wait_x0, sl_wrcomp => sl_wrcomp_x0, sl_wrdack => sl_wrdack_x0, vblank_o => vblank_o_x0, video_data_o => video_data_o_x0, vsync_o => vsync_o_x0 ); end structural;
gpl-3.0
4607d64acd10e187cbb2acaa903b0248
0.603419
3.316645
false
false
false
false
hoglet67/AtomFpga
src/common/RAM/RAM_2K.vhd
2
986
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity RAM_2K is port ( clk : in std_logic; we_uP : in std_logic; ce : in std_logic; addr_uP : in std_logic_vector (10 downto 0); D_uP : in std_logic_vector (7 downto 0); Q_uP : out std_logic_vector (7 downto 0)); end RAM_2K; architecture BEHAVIORAL of RAM_2K is type ram_type is array (2047 downto 0) of std_logic_vector (7 downto 0); signal RAM : ram_type := (2047 downto 0 => X"ff"); attribute RAM_STYLE : string; attribute RAM_STYLE of RAM : signal is "BLOCK"; begin process (clk) begin if rising_edge(clk) then if (we_UP = '1' and ce = '1') then RAM(conv_integer(addr_uP(10 downto 0))) <= D_up; end if; Q_up <= RAM(conv_integer(addr_uP(10 downto 0))); end if; end process; end BEHAVIORAL;
apache-2.0
f24a0d2feb45ecf9072f1f9d4f7e8a4a
0.541582
3.342373
false
false
false
false
tghaefli/ADD
ISE/FMC/fmc_chn.vhd
1
4,200
------------------------------------------------------------------------------- -- Entity: fmc_chn -- Author: Waj ------------------------------------------------------------------------------- -- Description: -- Floppy-Music Controller (1 channel) ------------------------------------------------------------------------------- -- Total # of FFs: ... tbd ... ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.mcu_pkg.all; entity fmc_chn is generic(N : natural := 0 -- channel number ); port(rst : in std_logic; clk : in std_logic; -- control inputs tick_dur : in std_logic; -- nominal period = 1 ms tick_nco : in std_logic; -- nominal period = 1 us chn_enb : in std_logic; -- outputs to pins fmc_enb : out std_logic; fmc_dir : out std_logic; fmc_stp : out std_logic ); end fmc_chn; architecture rtl of fmc_chn is -- ROM and addressing signal rom_addr : std_logic_vector(FMC_ROM_AW-1 downto 0); signal rom_data : std_logic_vector(FMC_ROM_DW-1 downto 0); signal duration_cnt, tone_duration: unsigned(FMC_DUR_WW-1 downto 0); signal tone_number : std_logic_vector(FMC_TON_WW-1 downto 0); signal tone_end_evt : std_logic; -- LUT: tone number ==> NCO seed type t_nco_lut is array (0 to 2**FMC_TON_WW-1) of natural; constant nco_lut : t_nco_lut := ( 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,7382,6968,6577,6207,5859,5530,5220,4927,4650,4389,4143,3910,3691, 3484,3288,3104,2930,2765,2610,2463,2325,2195,2071,1955,1845,1742,1644,1552,1465,1383,1305,1232, 1163,1097,1036,978,923,871,822,776,732,691,652,616,581,549,518,489,461); -- NCO signals signal seed : unsigned(12 downto 0); -- 13 bit seed signal nco_reg : unsigned(23 downto 0); -- 24 bit NCO begin -- dummy!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! fmc_enb <= tone_duration(0); fmc_dir <= tone_duration(2); fmc_stp <= std_logic(nco_reg(nco_reg'left)); -- MSB of NCO is desired frequency ----------------------------------------------------------------------------- -- ROM addressing and tick counting ----------------------------------------------------------------------------- P_read: process(rst, clk) begin if rst = '1' then duration_cnt <= (others => '0'); tone_end_evt <= '0'; rom_addr <= (others => '0'); elsif rising_edge(clk) then -- maintain tone duration counter if tick_dur = '1' then if duration_cnt = tone_duration then duration_cnt <= (others => '0'); tone_end_evt <= '1'; else duration_cnt <= duration_cnt + 1; end if; end if; -- maintain ROM address if chn_enb = '0' then rom_addr <= (others => '0'); elsif tone_end_evt = '1' then if tone_duration = FMC_LAST_TONE then -- restart playing from 1st tone rom_addr <= (others => '0'); else rom_addr <= std_logic_vector(unsigned(rom_addr)+1); end if; end if; end if; end process; ----------------------------------------------------------------------------- -- channel number dependent FMC ROM instance ----------------------------------------------------------------------------- rom : entity work.fmc_rom generic map(N => N) port map (clk => clk, addr => rom_addr, data => rom_data ); tone_duration <= unsigned(rom_data(FMC_DUR_WW+FMC_TON_WW-1 downto FMC_TON_WW)); tone_number <= rom_data(FMC_TON_WW-1 downto 0); ----------------------------------------------------------------------------- -- NCO (tone frequency generation) ----------------------------------------------------------------------------- P_nco: process(rst, clk) begin if rst = '1' then seed <= (others => '0'); nco_reg <= (others => '0'); elsif rising_edge(clk) then seed <= to_unsigned(nco_lut(to_integer(unsigned(tone_number))),13); nco_reg <= nco_reg + seed; end if; end process; end rtl;
gpl-3.0
adc0627b20979499b4b73210d4b99867
0.462619
3.939962
false
false
false
false
hoglet67/AtomFpga
src/common/AVR8/FrqDiv/FrqDiv.vhd
3
1,388
--********************************************************************************************** -- Frequency divider for AVR uC (40 MHz -> 4 MHz or 40 MHz -> 20 MHz) -- Version 1.52(Dust Inc version) -- Modified 16.01.2006 -- Designed by Ruslan Lepetenok --********************************************************************************************** library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use WORK.AVRuCPackage.all; entity FrqDiv is port( clk_in : in std_logic; clk_out : out std_logic ); end FrqDiv; architecture RTL of FrqDiv is signal DivCnt : std_logic_vector(3 downto 0); signal clk_out_int : std_logic; constant Div2 : boolean := TRUE; begin -- Must be sequentially encoded DivideBy10_1:if not Div2 generate Gen:process(clk_in) begin if(clk_in='1' and clk_in'event) then -- Clock if(DivCnt=x"4") then DivCnt <= x"0"; else DivCnt <= DivCnt + 1; end if; if(DivCnt=x"4") then clk_out_int <= not clk_out_int; end if; end if; end process; end generate; DivideBy10_2:if Div2 generate Gen:process(clk_in) begin if(clk_in='1' and clk_in'event) then -- Clock clk_out_int <= not clk_out_int; end if; end process; end generate; clk_out <= clk_out_int; end RTL;
apache-2.0
b8494de554bf693a7ddc4c86edca4629
0.51585
3.377129
false
false
false
false
hoglet67/AtomFpga
src/common/AVR8/Peripheral/Timer_Counter.vhd
4
31,542
--********************************************************************************************** -- Timers/Counters Block Peripheral for the AVR Core -- Version 1.37? (Special version for the JTAG OCD) -- Modified 11.06.2004 -- Synchronizer for EXT1/EXT2 inputs was added -- Designed by Ruslan Lepetenok -- Note : Only T/C0 and T/C2 are implemented --********************************************************************************************** library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use WORK.AVRuCPackage.all; entity Timer_Counter is port( -- AVR Control ireset : in std_logic; cp2 : in std_logic; cp2en : in std_logic; tmr_cp2en : in std_logic; stopped_mode : in std_logic; -- ?? tmr_running : in std_logic; -- ?? adr : in std_logic_vector(15 downto 0); dbus_in : in std_logic_vector(7 downto 0); dbus_out : out std_logic_vector(7 downto 0); iore : in std_logic; iowe : in std_logic; out_en : out std_logic; -- External inputs/outputs EXT1 : in std_logic; EXT2 : in std_logic; OC0_PWM0 : out std_logic; OC1A_PWM1A : out std_logic; OC1B_PWM1B : out std_logic; OC2_PWM2 : out std_logic; -- Interrupt related signals TC0OvfIRQ : out std_logic; TC0OvfIRQ_Ack : in std_logic; TC0CmpIRQ : out std_logic; TC0CmpIRQ_Ack : in std_logic; TC2OvfIRQ : out std_logic; TC2OvfIRQ_Ack : in std_logic; TC2CmpIRQ : out std_logic; TC2CmpIRQ_Ack : in std_logic; TC1OvfIRQ : out std_logic; TC1OvfIRQ_Ack : in std_logic; TC1CmpAIRQ : out std_logic; TC1CmpAIRQ_Ack : in std_logic; TC1CmpBIRQ : out std_logic; TC1CmpBIRQ_Ack : in std_logic; TC1ICIRQ : out std_logic; TC1ICIRQ_Ack : in std_logic; --Status bits PWM2bit : out std_logic; PWM0bit : out std_logic; PWM10bit : out std_logic; PWM11bit : out std_logic ); end Timer_Counter; architecture RTL of Timer_Counter is -- Copies of the external signals signal OC0_PWM0_Int : std_logic; signal OC2_PWM2_Int : std_logic; -- Registers signal TCCR0 : std_logic_vector(7 downto 0); signal TCCR1A : std_logic_vector(7 downto 0); signal TCCR1B : std_logic_vector(7 downto 0); signal TCCR2 : std_logic_vector(7 downto 0); signal ASSR : std_logic_vector(7 downto 0); -- Asynchronous status register (for TCNT0) signal TIMSK : std_logic_vector(7 downto 0); signal TIFR : std_logic_vector(7 downto 0); signal TCNT0 : std_logic_vector(7 downto 0); signal TCNT2 : std_logic_vector(7 downto 0); signal OCR0 : std_logic_vector(7 downto 0); signal OCR2 : std_logic_vector(7 downto 0); signal TCNT1H : std_logic_vector(7 downto 0); signal TCNT1L : std_logic_vector(7 downto 0); signal OCR1AH : std_logic_vector(7 downto 0); signal OCR1AL : std_logic_vector(7 downto 0); signal OCR1BH : std_logic_vector(7 downto 0); signal OCR1BL : std_logic_vector(7 downto 0); signal ICR1AH : std_logic_vector(7 downto 0); signal ICR1AL : std_logic_vector(7 downto 0); -- TCCR0 Bits alias CS00 : std_logic is TCCR0(0); alias CS01 : std_logic is TCCR0(1); alias CS02 : std_logic is TCCR0(2); alias CTC0 : std_logic is TCCR0(3); alias COM00 : std_logic is TCCR0(4); alias COM01 : std_logic is TCCR0(5); alias PWM0 : std_logic is TCCR0(6); -- TCCR1A Bits alias PWM10 : std_logic is TCCR1A(0); alias PWM11 : std_logic is TCCR1A(1); alias COM1B0 : std_logic is TCCR1A(4); alias COM1B1 : std_logic is TCCR1A(5); alias COM1A0 : std_logic is TCCR1A(4); alias COM1A1 : std_logic is TCCR1A(5); -- TCCR1B Bits alias CS10 : std_logic is TCCR1A(0); alias CS11 : std_logic is TCCR1A(1); alias CS12 : std_logic is TCCR1A(2); alias CTC1 : std_logic is TCCR1A(3); alias ICES1 : std_logic is TCCR1A(6); alias ICNC1 : std_logic is TCCR1A(7); -- TCCR2 Bits alias CS20 : std_logic is TCCR2(0); alias CS21 : std_logic is TCCR2(1); alias CS22 : std_logic is TCCR2(2); alias CTC2 : std_logic is TCCR2(3); alias COM20 : std_logic is TCCR2(4); alias COM21 : std_logic is TCCR2(5); alias PWM2 : std_logic is TCCR2(6); -- ASSR bits alias TCR0UB : std_logic is ASSR(0); alias OCR0UB : std_logic is ASSR(1); alias TCN0UB : std_logic is ASSR(2); alias AS0 : std_logic is ASSR(3); -- TIMSK bits alias TOIE0 : std_logic is TIMSK(0); alias OCIE0 : std_logic is TIMSK(1); alias TOIE1 : std_logic is TIMSK(2); alias OCIE1B : std_logic is TIMSK(3); alias OCIE1A : std_logic is TIMSK(4); alias TICIE1 : std_logic is TIMSK(5); alias TOIE2 : std_logic is TIMSK(6); alias OCIE2 : std_logic is TIMSK(7); -- TIFR bits alias TOV0 : std_logic is TIFR(0); alias OCF0 : std_logic is TIFR(1); alias TOV1 : std_logic is TIFR(2); alias OCF1B : std_logic is TIFR(3); alias OCF1A : std_logic is TIFR(4); alias ICF1 : std_logic is TIFR(5); alias TOV2 : std_logic is TIFR(6); alias OCF2 : std_logic is TIFR(7); -- Prescaler1 signals signal CK8 : std_logic; signal CK64 : std_logic; signal CK256 : std_logic; signal CK1024 : std_logic; signal Pre1Cnt : std_logic_vector(9 downto 0); -- Prescaler 1 counter (10-bit) signal EXT1RE : std_logic; -- Rising edge of external input EXT1 (for TCNT1 only) signal EXT1FE : std_logic; -- Falling edge of external input EXT1 (for TCNT1 only) signal EXT2RE : std_logic; -- Rising edge of external input EXT2 (for TCNT2 only) signal EXT2FE : std_logic; -- Falling edge of external input EXT2 (for TCNT2 only) -- Risign/falling edge detectors signal EXT1Latched : std_logic; signal EXT2Latched : std_logic; -- Prescalers outputs signal TCNT0_En : std_logic; -- Output of the prescaler 0 signal TCNT1_En : std_logic; -- Output of the prescaler 1 signal TCNT2_En : std_logic; -- Output of the prescaler 1 -- Prescaler0 signals signal PCK08 : std_logic; signal PCK032 : std_logic; signal PCK064 : std_logic; signal PCK0128 : std_logic; signal PCK0256 : std_logic; signal PCK01024 : std_logic; signal Pre0Cnt : std_logic_vector(9 downto 0); -- Prescaler 0 counter (10-bit) -- Synchronizer signals signal EXT1SA : std_logic; signal EXT1SB : std_logic; -- Output of the synchronizer for EXT1 signal EXT2SA : std_logic; signal EXT2SB : std_logic; -- Output of the synchronizer for EXT1 -- Temporary registers signal OCR0_Tmp : std_logic_vector(OCR0'range); signal OCR2_Tmp : std_logic_vector(OCR2'range); -- Counters control(Inc/Dec) signal Cnt0Dir : std_logic; signal Cnt2Dir : std_logic; -- signal TCNT0WrFl : std_logic; signal TCNT0CmpBl : std_logic; signal TCNT2WrFl : std_logic; signal TCNT2CmpBl : std_logic; begin -- Synchronizers SyncDFFs:process(cp2,ireset) begin if (ireset='0') then -- Reset EXT1SA <= '0'; EXT1SB <= '0'; EXT2SA <= '0'; EXT2SB <= '0'; elsif (cp2='1' and cp2'event) then -- Clock if (tmr_cp2en='1') then -- Clock Enable(Note 2) EXT1SA <= EXT1; EXT1SB <= EXT1SA; EXT2SA <= EXT2; EXT2SB <= EXT2SA; end if; end if; end process; -- ------------------------------------------------------------------------------------------- -- Prescalers -- ------------------------------------------------------------------------------------------- -- Prescaler 1 for TCNT1 and TCNT2 Prescaler_1:process(cp2,ireset) begin if (ireset='0') then -- Reset Pre1Cnt <= (others => '0'); CK8 <= '0'; CK64 <= '0'; CK256 <= '0'; CK1024 <= '0'; EXT1RE <= '0'; EXT1FE <= '0'; EXT2RE <= '0'; EXT2FE <= '0'; EXT1Latched <= '0'; EXT2Latched <= '0'; elsif (cp2='1' and cp2'event) then -- Clock if (tmr_cp2en='1') then -- Clock Enable Pre1Cnt <= Pre1Cnt+1; CK8 <= not CK8 and(Pre1Cnt(0) and Pre1Cnt(1)and Pre1Cnt(2)); CK64 <= not CK64 and(Pre1Cnt(0) and Pre1Cnt(1) and Pre1Cnt(2) and Pre1Cnt(3) and Pre1Cnt(4) and Pre1Cnt(5)); CK256 <= not CK256 and(Pre1Cnt(0) and Pre1Cnt(1) and Pre1Cnt(2) and Pre1Cnt(3) and Pre1Cnt(4) and Pre1Cnt(5) and Pre1Cnt(6) and Pre1Cnt(7)); CK1024 <= not CK1024 and(Pre1Cnt(0) and Pre1Cnt(1) and Pre1Cnt(2) and Pre1Cnt(3) and Pre1Cnt(4) and Pre1Cnt(5) and Pre1Cnt(6) and Pre1Cnt(7) and Pre1Cnt(8) and Pre1Cnt(9)); EXT1RE <= not EXT1RE and (EXT1SB and not EXT1Latched); EXT1FE <= not EXT1FE and (not EXT1SB and EXT1Latched); EXT2RE <= not EXT2RE and (EXT2SB and not EXT2Latched); EXT2FE <= not EXT2FE and (not EXT2SB and EXT2Latched); EXT1Latched <= EXT1SB; EXT2Latched <= EXT2SB; end if; end if; end process; TCNT1_En <= (not CS12 and not CS11 and CS10) or -- CK "001" (CK8 and not CS12 and CS11 and not CS10) or -- CK/8 "010" (CK64 and not CS12 and CS11 and CS10) or -- CK/64 "011" (CK256 and CS12 and not CS11 and not CS10) or -- CK/256 "100" (CK1024 and CS12 and not CS11 and CS10) or -- CK/1024 "101" (EXT1FE and CS12 and CS11 and not CS10) or -- Falling edge "110" (EXT1RE and CS12 and CS11 and CS10); -- Rising edge "111" TCNT2_En <= (not CS22 and not CS21 and CS20) or -- CK "001" (CK8 and not CS22 and CS21 and not CS20) or -- CK/8 "010" (CK64 and not CS22 and CS21 and CS20) or -- CK/64 "011" (CK256 and CS22 and not CS21 and not CS20) or -- CK/256 "100" (CK1024 and CS22 and not CS21 and CS20) or -- CK/1024 "101" (EXT2FE and CS22 and CS21 and not CS20) or -- Falling edge "110" (EXT2RE and CS22 and CS21 and CS20); -- Rising edge "111" Prescaler_0_Cnt:process(cp2,ireset) begin if(ireset='0') then -- Reset Pre0Cnt <= (others => '0'); elsif (cp2='1' and cp2'event) then -- Clock if (tmr_cp2en='1') then -- Clock Enable(Note 2) Pre0Cnt <= Pre0Cnt+1; end if; end if; end process; Prescaler_0:process(cp2,ireset) begin if (ireset='0') then -- Reset PCK08 <= '0'; PCK032 <= '0'; PCK064 <= '0'; PCK0128 <= '0'; PCK0256 <= '0'; PCK01024 <= '0'; elsif (cp2='1' and cp2'event) then -- Clock if (tmr_cp2en='1') then -- Clock Enable PCK08 <= (not PCK08 and(Pre0Cnt(0) and Pre0Cnt(1)and Pre0Cnt(2))); PCK032 <= (not PCK032 and(Pre0Cnt(0) and Pre0Cnt(1) and Pre0Cnt(2) and Pre0Cnt(3) and Pre0Cnt(4))); PCK064 <= (not PCK064 and(Pre0Cnt(0) and Pre0Cnt(1) and Pre0Cnt(2) and Pre0Cnt(3) and Pre0Cnt(4) and Pre0Cnt(5))); PCK0128 <= (not PCK0128 and(Pre0Cnt(0) and Pre0Cnt(1) and Pre0Cnt(2) and Pre0Cnt(3) and Pre0Cnt(4) and Pre0Cnt(5) and Pre0Cnt(6))); PCK0256 <= (not PCK0256 and(Pre0Cnt(0) and Pre0Cnt(1) and Pre0Cnt(2) and Pre0Cnt(3) and Pre0Cnt(4) and Pre0Cnt(5) and Pre0Cnt(6) and Pre0Cnt(7))); PCK01024 <= (not PCK01024 and(Pre0Cnt(0) and Pre0Cnt(1) and Pre0Cnt(2) and Pre0Cnt(3) and Pre0Cnt(4) and Pre0Cnt(5) and Pre0Cnt(6) and Pre0Cnt(7) and Pre0Cnt(8) and Pre0Cnt(9))); end if; end if; end process; TCNT0_En <= (not CS02 and not CS01 and CS00) or -- PCK "001" (PCK08 and not CS02 and CS01 and not CS00) or -- PCK/8 "010" (PCK032 and not CS02 and CS01 and CS00)or -- PCK/32 "011" (PCK064 and CS02 and not CS01 and not CS00)or -- PCK/64 "100" (PCK0128 and CS02 and not CS01 and CS00)or -- PCK/64 "101" (PCK0256 and CS02 and CS01 and not CS00)or -- PCK/256 "110" (PCK01024 and CS02 and CS01 and CS00); -- PCK/1024 "111" -- ------------------------------------------------------------------------------------------- -- End of prescalers -- ------------------------------------------------------------------------------------------- -- ------------------------------------------------------------------------------------------- -- Timer/Counter 0 -- ------------------------------------------------------------------------------------------- TimerCounter0Cnt:process(cp2,ireset) begin if (ireset='0') then -- Reset TCNT0 <= (others => '0'); elsif (cp2='1' and cp2'event) then -- Clock if(adr=TCNT0_Address and iowe='1' and cp2en='1') then -- Write to TCNT0 TCNT0 <= dbus_in; elsif(tmr_cp2en='1') then case PWM0 is when '0' => -- Non-PWM mode if(CTC0='1' and TCNT0=OCR0) then -- Clear T/C on compare match TCNT0 <= (others => '0'); elsif(TCNT0_En='1') then TCNT0 <= TCNT0 + 1; -- Increment TCNT0 end if; when '1' => -- PWM mode if(TCNT0_En='1') then case Cnt0Dir is when '0' => -- Counts up if(TCNT0=x"FF") then TCNT0<=x"FE"; else TCNT0 <= TCNT0 + 1; -- Increment TCNT0 (0 to FF) end if; when '1' => -- Counts down if(TCNT0=x"00") then TCNT0 <= x"01"; else TCNT0 <= TCNT0 - 1; -- Decrement TCNT0 (FF to 0) end if; when others => null; end case; end if; when others => null; end case; end if; end if; end process; Cnt0DirectionControl:process(cp2,ireset) begin if (ireset='0') then -- Reset Cnt0Dir <= '0'; elsif (cp2='1' and cp2'event) then -- Clock if(tmr_cp2en='1') then -- Clock enable if(TCNT0_En='1') then if (PWM0='1') then case Cnt0Dir is when '0' => if(TCNT0=x"FF") then Cnt0Dir <= '1'; end if; when '1' => if(TCNT0=x"00") then Cnt0Dir <= '0'; end if; when others => null; end case; end if; end if; end if; end if; end process; TCnt0OutputControl:process(cp2,ireset) begin if (ireset='0') then -- Reset OC0_PWM0_Int <= '0'; elsif (cp2='1' and cp2'event) then -- Clock if(tmr_cp2en='1') then -- Clock enable if(TCNT0_En='1') then case PWM0 is when '0' => -- Non PWM Mode if(TCNT0=OCR0 and TCNT0CmpBl='0') then if(COM01='0' and COM00='1') then -- Toggle OC0_PWM0_Int <= not OC0_PWM0_Int; end if; end if; when '1' => -- PWM Mode case TCCR0(5 downto 4) is -- -> COM01&COM00 when "10" => -- Non-inverted PWM if(TCNT0=x"FF") then -- Update OCR0 if (OCR0_Tmp=x"00") then OC0_PWM0_Int <= '0'; -- Clear elsif (OCR0_Tmp=x"FF") then OC0_PWM0_Int <= '1'; -- Set end if; elsif(TCNT0=OCR0 and OCR0/=x"00") then if(Cnt0Dir='0') then -- Up-counting OC0_PWM0_Int <= '0'; -- Clear else -- Down-counting OC0_PWM0_Int <= '1'; -- Set end if; end if; when "11" => -- Inverted PWM if(TCNT0=x"FF") then -- Update OCR0 if (OCR0_Tmp=x"00") then OC0_PWM0_Int <= '1'; -- Set elsif (OCR0_Tmp=x"FF") then OC0_PWM0_Int <= '0'; -- Clear end if; elsif(TCNT0=OCR0 and OCR0/=x"00") then if(Cnt0Dir='0') then -- Up-counting OC0_PWM0_Int <= '1'; -- Set else -- Down-counting OC0_PWM0_Int <= '0'; -- Clear end if; end if; when others => null; end case; when others => null; end case; end if; end if; end if; end process; OC0_PWM0 <= OC0_PWM0_Int; TCnt0_TIFR_Bits:process(cp2,ireset) begin if (ireset='0') then -- Reset TOV0 <= '0'; OCF0 <= '0'; elsif (cp2='1' and cp2'event) then -- Clock -- TOV0 if(stopped_mode='1' and tmr_running='0' and cp2en='1') then -- !!!Special mode!!! if(adr=TIFR_Address and iowe='1') then TOV0 <= dbus_in(0); -- !!! end if; else case TOV0 is when '0' => if (tmr_cp2en='1' and TCNT0_En='1') then if (PWM0='0') then -- Non PWM Mode if (TCNT0=x"FF") then TOV0 <= '1'; end if; else -- PWM Mode if(TCNT0=x"00") then TOV0 <= '1'; end if; end if; end if; when '1' => if((TC0OvfIRQ_Ack='1' or (adr=TIFR_Address and iowe='1' and dbus_in(0)='1')) and cp2en='1') then -- Clear TOV0 flag TOV0 <= '0'; end if; when others => null; end case; end if; -- OCF0 if(stopped_mode='1' and tmr_running='0' and cp2en='1') then -- !!!Special mode!!! if(adr=TIFR_Address and iowe='1') then OCF0 <= dbus_in(1); -- !!! end if; else case OCF0 is when '0' => if (tmr_cp2en='1' and TCNT0_En='1') then if (TCNT0=OCR0 and TCNT0CmpBl='0') then OCF0 <= '1'; end if; end if; when '1' => if((TC0CmpIRQ_Ack='1' or (adr=TIFR_Address and iowe='1' and dbus_in(1)='1')) and cp2en='1') then -- Clear OCF2 flag OCF0 <= '0'; end if; when others => null; end case; end if; end if; end process; TCCR0(7) <= '0'; TCCR0_Reg:process(cp2,ireset) begin if (ireset='0') then -- Reset TCCR0(6 downto 0) <= (others => '0'); elsif (cp2='1' and cp2'event) then -- Clock if (cp2en='1') then -- Clock Enable if (adr=TCCR0_Address and iowe='1') then TCCR0(6 downto 0) <= dbus_in(6 downto 0); end if; end if; end if; end process; OCR0_Write:process(cp2,ireset) begin if (ireset='0') then -- Reset OCR0 <= (others => '0'); elsif (cp2='1' and cp2'event) then -- Clock case PWM0 is when '0' => -- Non-PWM mode if (adr=OCR0_Address and iowe='1' and cp2en='1') then -- Load data from the data bus OCR0 <= dbus_in; end if; when '1' => -- PWM mode if(TCNT0=x"FF" and tmr_cp2en='1' and TCNT0_En='1') then -- Load data from the temporary register OCR0 <= OCR0_Tmp; end if; when others => null; end case; end if; end process; OCR0_Tmp_Write:process(cp2,ireset) begin if (ireset='0') then -- Reset OCR0_Tmp <= (others => '0'); elsif (cp2='1' and cp2'event) then -- Clock if (cp2en='1') then if (adr=OCR0_Address and iowe='1') then -- Load data from the data bus OCR0_Tmp <= dbus_in; end if; end if; end if; end process; -- TCNT0WriteControl:process(cp2,ireset) begin if (ireset='0') then -- Reset TCNT0WrFl <= '0'; elsif (cp2='1' and cp2'event) then -- Clock if (cp2en='1') then case TCNT0WrFl is when '0' => if (adr=TCNT0_Address and iowe='1' and TCNT0_En='0') then -- Load data from the data bus TCNT0WrFl <= '1'; end if; when '1' => if(TCNT0_En='0') then TCNT0WrFl <= '0'; end if; when others => null; end case; end if; end if; end process; -- Operations on compare match(OCF0 and Toggling) disabled for TCNT0 TCNT0CmpBl <= '1' when (TCNT0WrFl='1' or (adr=TCNT0_Address and iowe='1')) else '0'; -- ------------------------------------------------------------------------------------------- -- Timer/Counter 2 -- ------------------------------------------------------------------------------------------- TimerCounter2Cnt:process(cp2,ireset) begin if (ireset='0') then -- Reset TCNT2 <= (others => '0'); elsif (cp2='1' and cp2'event) then -- Clock if(adr=TCNT2_Address and iowe='1' and cp2en='1') then -- Write to TCNT2 TCNT2 <= dbus_in; elsif(tmr_cp2en='1') then case PWM2 is when '0' => -- Non-PWM mode if(CTC2='1' and TCNT2=OCR2) then -- Clear T/C on compare match TCNT2 <= (others => '0'); elsif(TCNT2_En='1') then TCNT2 <= TCNT2 + 1; -- Increment TCNT2 end if; when '1' => -- PWM mode if(TCNT2_En='1') then case Cnt2Dir is when '0' => -- Counts up if(TCNT2=x"FF") then TCNT2 <= x"FE"; else TCNT2 <= TCNT2 + 1; -- Increment TCNT2 (0 to FF) end if; when '1' => -- Counts down if(TCNT2=x"00") then TCNT2 <= x"01"; else TCNT2 <= TCNT2 - 1; -- Decrement TCNT0 (FF to 0) end if; when others => null; end case; end if; when others => null; end case; end if; end if; end process; Cnt2DirectionControl:process(cp2,ireset) begin if (ireset='0') then -- Reset Cnt2Dir <= '0'; elsif (cp2='1' and cp2'event) then -- Clock if(tmr_cp2en='1') then -- Clock enable if(TCNT2_En='1') then if (PWM2='1') then case Cnt2Dir is when '0' => if(TCNT2=x"FF") then Cnt2Dir <= '1'; end if; when '1' => if(TCNT2=x"00") then Cnt2Dir <= '0'; end if; when others => null; end case; end if; end if; end if; end if; end process; TCnt2OutputControl:process(cp2,ireset) begin if (ireset='0') then -- Reset OC2_PWM2_Int <= '0'; elsif (cp2='1' and cp2'event) then -- Clock if(tmr_cp2en='1') then -- Clock enable if(TCNT2_En='1') then case PWM2 is when '0' => -- Non PWM Mode if(TCNT2=OCR2 and TCNT2CmpBl='0') then if(COM21='0' and COM20='1') then -- Toggle OC2_PWM2_Int <= not OC2_PWM2_Int; end if; end if; when '1' => -- PWM Mode case TCCR2(5 downto 4) is -- -> COM21&COM20 when "10" => -- Non-inverted PWM if(TCNT2=x"FF") then -- Update OCR2 if (OCR2_Tmp=x"00") then OC2_PWM2_Int <= '0'; -- Clear elsif (OCR2_Tmp=x"FF") then OC2_PWM2_Int <= '1'; -- Set end if; elsif(TCNT2=OCR2 and OCR2/=x"00") then if(Cnt2Dir='0') then -- Up-counting OC2_PWM2_Int <= '0'; -- Clear else -- Down-counting OC2_PWM2_Int <= '1'; -- Set end if; end if; when "11" => -- Inverted PWM if(TCNT2=x"FF") then -- Update OCR2 if (OCR2_Tmp=x"00") then OC2_PWM2_Int <= '1'; -- Set elsif (OCR2_Tmp=x"FF") then OC2_PWM2_Int <= '0'; -- Clear end if; elsif(TCNT2=OCR2 and OCR2/=x"00") then if(Cnt2Dir='0') then -- Up-counting OC2_PWM2_Int <= '1'; -- Set else -- Down-counting OC2_PWM2_Int <= '0'; -- Clear end if; end if; when others => null; end case; when others => null; end case; end if; end if; end if; end process; OC2_PWM2 <= OC2_PWM2_Int; TCnt2_TIFR_Bits:process(cp2,ireset) begin if (ireset='0') then -- Reset TOV2 <= '0'; OCF2 <= '0'; elsif (cp2='1' and cp2'event) then -- Clock -- TOV2 if(stopped_mode='1' and tmr_running='0' and cp2en='1') then -- !!!Special mode!!! if(adr=TIFR_Address and iowe='1') then TOV2 <= dbus_in(6); -- !!! end if; else case TOV2 is when '0' => if (tmr_cp2en='1' and TCNT2_En='1') then if (PWM2='0') then -- Non PWM Mode if (TCNT2=x"FF") then TOV2 <= '1'; end if; else -- PWM Mode if(TCNT2=x"00") then TOV2 <= '1'; end if; end if; end if; when '1' => if((TC2OvfIRQ_Ack='1' or (adr=TIFR_Address and iowe='1' and dbus_in(6)='1')) and cp2en='1') then -- Clear TOV2 flag TOV2 <= '0'; end if; when others => null; end case; end if; -- OCF2 if(stopped_mode='1' and tmr_running='0' and cp2en='1') then -- !!!Special mode!!! if(adr=TIFR_Address and iowe='1') then OCF2 <= dbus_in(7); -- !!! end if; else case OCF2 is when '0' => if (tmr_cp2en='1' and TCNT2_En='1') then if (TCNT2=OCR2 and TCNT2CmpBl='0') then OCF2 <= '1'; end if; end if; when '1' => if((TC2CmpIRQ_Ack='1' or (adr=TIFR_Address and iowe='1' and dbus_in(7)='1')) and cp2en='1') then -- Clear OCF2 flag OCF2 <= '0'; end if; when others => null; end case; end if; end if; end process; TCCR2(7) <= '0'; TCCR2_Reg:process(cp2,ireset) begin if (ireset='0') then -- Reset TCCR2(6 downto 0) <= (others => '0'); elsif (cp2='1' and cp2'event) then -- Clock if (cp2en='1') then -- Clock Enable if (adr=TCCR2_Address and iowe='1') then TCCR2(6 downto 0) <= dbus_in(6 downto 0); end if; end if; end if; end process; OCR2_Write:process(cp2,ireset) begin if (ireset='0') then -- Reset OCR2 <= (others => '0'); elsif (cp2='1' and cp2'event) then -- Clock case PWM2 is when '0' => -- Non-PWM mode if (adr=OCR2_Address and iowe='1' and cp2en='1') then -- Load data from the data bus OCR2 <= dbus_in; end if; when '1' => -- PWM mode if(TCNT2=x"FF" and tmr_cp2en='1' and TCNT2_En='1') then -- Load data from the temporary register OCR2 <= OCR2_Tmp; end if; when others => null; end case; end if; end process; OCR2_Tmp_Write:process(cp2,ireset) begin if (ireset='0') then -- Reset OCR2_Tmp <= (others => '0'); elsif (cp2='1' and cp2'event) then -- Clock if (cp2en='1') then if (adr=OCR2_Address and iowe='1') then -- Load data from the data bus OCR2_Tmp <= dbus_in; end if; end if; end if; end process; -- TCNT2WriteControl:process(cp2,ireset) begin if (ireset='0') then -- Reset TCNT2WrFl <= '0'; elsif (cp2='1' and cp2'event) then -- Clock if (cp2en='1') then case TCNT2WrFl is when '0' => if (adr=TCNT2_Address and iowe='1' and TCNT2_En='0') then -- Load data from the data bus TCNT2WrFl <= '1'; end if; when '1' => if(TCNT2_En='0') then TCNT2WrFl <= '0'; end if; when others => null; end case; end if; end if; end process; -- Operations on compare match(OCF2 and Toggling) disabled for TCNT2 TCNT2CmpBl <= '1' when (TCNT2WrFl='1' or (adr=TCNT2_Address and iowe='1')) else '0'; -- ------------------------------------------------------------------------------------------- -- Common (Control/Interrupt) bits -- ------------------------------------------------------------------------------------------- TIMSK_Bits:process(cp2,ireset) begin if (ireset='0') then TIMSK <= (others => '0'); elsif (cp2='1' and cp2'event) then if (cp2en='1') then -- Clock Enable if (adr=TIMSK_Address and iowe='1') then TIMSK <= dbus_in; end if; end if; end if; end process; -- Interrupt flags of Timer/Counter0 TC0OvfIRQ <= TOV0 and TOIE0; -- Interrupt on overflow of TCNT0 TC0CmpIRQ <= OCF0 and OCIE0; -- Interrupt on compare match of TCNT0 -- Interrupt flags of Timer/Counter0 TC2OvfIRQ <= TOV2 and TOIE2; -- Interrupt on overflow of TCNT2 TC2CmpIRQ <= OCF2 and OCIE2; -- Interrupt on compare match of TCNT2 -- Unused interrupt requests(for T/C1) TC1OvfIRQ <= TOV1 and TOIE1; TC1CmpAIRQ <= OCF1A and OCIE1A; TC1CmpBIRQ <= OCF1B and OCIE1B; TC1ICIRQ <= ICF1 and TICIE1; -- Unused TIFR flags(for T/C1) TOV1 <= '0'; OCF1A <= '0'; OCF1B <= '0'; ICF1 <= '0'; -- ------------------------------------------------------------------------------------------- -- End of common (Control/Interrupt) bits -- ------------------------------------------------------------------------------------------- -- ------------------------------------------------------------------------------------------- -- Bus interface -- ------------------------------------------------------------------------------------------- out_en <= '1' when ((adr=TCCR0_Address or adr=TCCR1A_Address or adr=TCCR1B_Address or adr=TCCR2_Address or adr=ASSR_Address or adr=TIMSK_Address or adr=TIFR_Address or adr=TCNT0_Address or adr=TCNT2_Address or adr=OCR0_Address or adr=OCR2_Address or adr=TCNT1H_Address or adr=TCNT1L_Address or adr=OCR1AH_Address or adr=OCR1AL_Address or adr=OCR1BH_Address or adr=OCR1BL_Address or adr=ICR1AH_Address or adr=ICR1AL_Address) and iore='1') else '0'; -- Output multilexer --Output_Mux:process(adr,TCCR0,OCR0,OCR0_Tmp,TCNT0,TCCR2,OCR2,OCR2_Tmp,TCNT2,TIFR,TIMSK) -- Combinatorial --begin -- case adr is -- when TCCR0_Address => dbus_out <= TCCR0; -- when OCR0_Address => -- if (PWM0='0') then -- dbus_out <= OCR0; -- else -- dbus_out <= OCR0_Tmp; -- end if; -- when TCNT0_Address => dbus_out <= TCNT0; -- when TCCR2_Address => dbus_out <= TCCR2; -- when OCR2_Address => -- if (PWM2='0') then -- dbus_out <= OCR2; -- else -- dbus_out <= OCR2_Tmp; -- end if; -- when TCNT2_Address => dbus_out <= TCNT2; -- when TIFR_Address => dbus_out <= TIFR; -- when TIMSK_Address => dbus_out <= TIMSK; -- when others => dbus_out <= (others => '0'); -- end case; --end process; PWM0bit <= PWM0; PWM10bit <= PWM10; PWM11bit <= PWM11; PWM2bit <= PWM2; -- Synopsys version dbus_out <= TCCR0 when (adr=TCCR0_Address) else OCR0 when (adr=OCR0_Address and PWM0='0') else -- Non PWM mode of T/C0 OCR0_Tmp when (adr=OCR0_Address and PWM0='1') else -- PWM mode of T/C0 TCNT0 when (adr=TCNT0_Address) else TCCR2 when (adr=TCCR2_Address) else OCR2 when (adr=OCR2_Address and PWM2='0') else -- Non PWM mode of T/C2 OCR2_Tmp when (adr=OCR2_Address and PWM2='1') else -- PWM mode of T/C2 TCNT2 when (adr=TCNT2_Address) else TIFR when (adr=TIFR_Address) else TIMSK when (adr=TIMSK_Address) else (others => '0'); -- ------------------------------------------------------------------------------------------- -- End of bus interface -- ------------------------------------------------------------------------------------------- end RTL;
apache-2.0
9e0b2ced11dc797250eb70400b8880d1
0.510145
3.026482
false
false
false
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tghaefli/ADD
ISE/FMC_waj/rom.vhd
1
5,851
------------------------------------------------------------------------------- -- Entity: rom -- Author: Waj -- Date : 11-May-13, 26-May-13 ------------------------------------------------------------------------------- -- Description: (ECS Uebung 9) -- Program memory for simple von-Neumann MCU with registerd read data output. ------------------------------------------------------------------------------- -- Total # of FFs: DW ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.mcu_pkg.all; entity rom is port(clk : in std_logic; -- ROM bus signals bus_in : in t_bus2ros; bus_out : out t_ros2bus ); end rom; architecture rtl of rom is type t_rom is array (0 to 2**AWL-1) of std_logic_vector(DW-1 downto 0); constant rom_table : t_rom := ( --------------------------------------------------------------------------- -- program code ----------------------------------------------------------- --------------------------------------------------------------------------- -- Opcode Rdest Rsrc1 Rsrc2 description --------------------------------------------------------------------------- -- configure FMC_CHN_ENB(7:0) to enable all channels OPC(setil) & reg(3) & n2slv(16#40#, DW/2), -- setil r3, 0x40 OPC(setih) & reg(3) & n2slv(16#03#, DW/2), -- setih r3, 0x03 OPC(setil) & reg(4) & n2slv(16#FF#, DW/2), -- setil r4, 0xFF OPC(st) & reg(4) & reg(3) & "00000", -- CHN_ENB(7:0) = 0xFF -- configure FMC_TMP_CTRL to speed-up factor of 1 OPC(setil) & reg(3) & n2slv(16#41#, DW/2), -- setil r3, 0x41 OPC(setih) & reg(3) & n2slv(16#03#, DW/2), -- setih r3, 0x03 OPC(setil) & reg(4) & n2slv(16#30#, DW/2), -- setil r4, 0x40 OPC(setih) & reg(4) & n2slv(16#00#, DW/2), -- setih r4, 0x00 OPC(st) & reg(4) & reg(3) & "00000", -- SPD_FAC(9:0)=0x040=1.00 OPC(jmp) & "-00" & n2slv(16#09#, AW-2), -- jmp 0x009 -- set GPIO(7:0) = LED(7:0) to Output OPC(setil) & reg(3) & n2slv(16#02#, DW/2), -- setil r3, 0x02 OPC(setih) & reg(3) & n2slv(16#03#, DW/2), -- setih r3, 0x03 OPC(setil) & reg(4) & n2slv(16#FF#, DW/2), -- setil r4, 0xFF OPC(st) & reg(4) & reg(3) & "00000", -- GPIO_OUT_ENB = 0xFF -- initialize GPIO data output values (permanently stored in r4) OPC(setil) & reg(3) & n2slv(16#01#, DW/2), -- setil r3, 0x01 OPC(setil) & reg(4) & n2slv(16#2A#, DW/2), -- setil r4, 0x2A (LED(7:0)=00101010) OPC(st) & reg(4) & reg(3) & "00000", -- GPIO_DATA_OUT = 0x2A -- initilize bit masks for toggling specific bits OPC(setil) & reg(5) & n2slv(16#03#, DW/2), -- setil r5, 0x03 (LED(1:0)) OPC(setil) & reg(6) & n2slv(16#0C#, DW/2), -- setil r6, 0x0C (LED(3:2)) OPC(setil) & reg(7) & n2slv(16#30#, DW/2), -- setil r7, 0x30 (LED(5:4)) --------------------------------------------------------------------------- -- addr 0x00A: start of end-less loop -- outer for-loop (r2) -- init r2 = 0x0064 => 10 * 500 ms = 5 s OPC(setil) & reg(2) & n2slv(16#0A#, DW/2), -- setil r2, 0x0A OPC(setih) & reg(2) & n2slv(16#00#, DW/2), -- setih r2, 0x00 -- middle for-loop (r1) -- init r1 = 0x0064 => 100 * 5 ms = 500 ms OPC(setil) & reg(1) & n2slv(16#64#, DW/2), -- setil r1, 0x64 OPC(setih) & reg(1) & n2slv(16#00#, DW/2), -- setih r1, 0x00 -- inner for-loop (r0) -- init r0 = 0x5161 => 20833 * 4 * 3 cc = 5 ms OPC(setil) & reg(0) & n2slv(16#61#, DW/2), -- setil r0, 0x61 OPC(setih) & reg(0) & n2slv(16#51#, DW/2), -- setih r0, 0x51 -- execute iw_nop, iw_nop, -- check condition OPC(addil) & reg(0) & n2slv(16#FF#, DW/2), -- addil r0, 0xFF OPC(bne) & "-11" & n2slv(16#FD#, AW-2), -- bne 0x3FD (-3) -- toggle LED(1:0) OPC(xori) & reg(4) & reg(4) & reg(5)& "00", -- apply bit mask OPC(st) & reg(4) & reg(3) & "00000", -- write new value to GPIO_DATA_OUT -- check condition OPC(addil) & reg(1) & n2slv(16#FF#, DW/2), -- addil r1, 0xFF OPC(bne) & "-11" & n2slv(16#F7#, AW-2), -- bne 0x3F7 (-9) -- toggle LED(3:2) OPC(xori) & reg(4) & reg(4) & reg(6)& "00", -- apply bit mask OPC(st) & reg(4) & reg(3) & "00000", -- write new value to GPIO_DATA_OUT -- check condition OPC(addil) & reg(2) & n2slv(16#FF#, DW/2), -- addil r2, 0xFF OPC(bne) & "-11" & n2slv(16#F1#, AW-2), -- bne 0x3F1 (-15) -- toggle LED(3:2) OPC(xori) & reg(4) & reg(4) & reg(7)& "00", -- apply bit mask OPC(st) & reg(4) & reg(3) & "00000", -- write new value to GPIO_DATA_OUT -- end of end-less loop OPC(jmp) & "-00" & n2slv(16#0A#, AW-2), -- jmp 0x00A --------------------------------------------------------------------------- others => iw_nop -- NOP ); begin ----------------------------------------------------------------------------- -- sequential process: ROM table with registerd output ----------------------------------------------------------------------------- P_rom: process(clk) begin if rising_edge(clk) then bus_out.data <= rom_table(to_integer(unsigned(bus_in.addr))); end if; end process; end rtl;
gpl-3.0
4ca759d2a73b650868b53774b7275096
0.407794
3.193777
false
false
false
false
abyrne55/my-little-processor
binaryto4hex.vhd
1
964
LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY binaryto4hex IS PORT ( binary : IN STD_LOGIC_VECTOR(15 DOWNTO 0); output0, output1, output2, output3 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) ); END binaryto4hex; ARCHITECTURE Behavioural OF binaryto4hex IS COMPONENT binary_to_sevenSeg PORT ( binary_value : IN STD_LOGIC_VECTOR(3 DOWNTO 0); sevenSeg : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) ); END COMPONENT; BEGIN bintoseg1 : binary_to_sevenSeg PORT MAP( binary_value => binary(15 DOWNTO 12), sevenSeg => output3 ); bintoseg2 : binary_to_sevenSeg PORT MAP( binary_value => binary(11 DOWNTO 8), sevenSeg => output2 ); bintoseg3 : binary_to_sevenSeg PORT MAP( binary_value => binary(7 DOWNTO 4), sevenSeg => output1 ); bintoseg4 : binary_to_sevenSeg PORT MAP( binary_value => binary(3 DOWNTO 0), sevenSeg => output0 ); END Behavioural;
mit
bd35454d1fdef302ee65729063dac9dd
0.657676
2.948012
false
false
false
false
GSimas/EEL5105
AULA9/reg8.vhd
2
410
library ieee; use ieee.std_logic_1164.all; entity D_8FF is port ( CLK, RST: in std_logic; EN: in std_logic; D: in std_logic_vector(7 downto 0); Q: out std_logic_vector(7 downto 0) ); end D_8FF; architecture behv of D_8FF is begin process(CLK, D, RST) begin if RST = '0' then Q <= "00000000"; elsif (CLK'event and CLK = '1') then if EN = '1' then Q <= D; end if; end if; end process; end behv;
mit
d4062e437172bdb8370b98b30223e115
0.643902
2.369942
false
false
false
false
GSimas/EEL5105
Rep CAEE/11.2.Projeto/_PROJETO/somador.vhd
1
1,636
-- ALUNOS: -- Bruno Luiz da Silva -- Gustavo Fernades -- -- -- TÍTULO: -- Somador do multiplicador -- -- -- RESUMO: -- Soma do registrador de 8 bits (multiplicando) com parte alta do de 16 bits, dependendo apenas do MSB do reg_16 -- -- -- ENTRADAS/SAÍDAS (I/O): -- (I) a,b: Valor do registrador de 8 bits (multiplicando) e da parte alta do registrador de 16 bits -- (I) control: é o MSB do registrador de 16 bits. Será utilizado como condição para realizar ou não a adição -- (I) enable: ativa ou desativa o somador -- (O) q: saída da possível soma, porém com 9 bits. O bit extra deve-se a um possível carry que pode ser gerado. -- -- -- DESCRIÇÃO: -- Realizará a soma dos valores do registrador de 8 bits e parte alta do registrador de 16 bits quando "enable" for alto -- respeitando a condição de somente somar ambos se o "control" (MSB do registrador de 16 bits) for 1. Caso contrário a -- saída será somente o valor da parte alta do registrador de 16 bits, não executando nenhuma operação. -- -- -- (I): INPUT / (O): OUTPUT library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity somador is generic(N: natural := 8); port( a,b: in std_logic_vector((N-1) downto 0); -- Valor do registrador de 8 bits e da parte alta do de 16 bits control,enable: in std_logic; -- Clock e enable (l2) q: out std_logic_vector(N downto 0) -- Soma ); end somador; architecture func of somador is begin SOMA: process(enable) begin if(enable = '1') then if(control = '1') then q <= ('0' & a) + ('0' & b); elsif(control = '0') then q <= '0' & b; end if; end if; end process; end func;
mit
9628caa54b08d07a7f234984db7e7f41
0.677873
2.870175
false
false
false
false
tghaefli/ADD
EDK/IVK_Repos/IVK_IPLib/pcores/sg_i2c_controller_s6_plbw_v1_01_a/hdl/vhdl/sg_i2c_controller_s6_plbw.vhd
1
9,681
------------------------------------------------------------------- -- System Generator version 11.1.00 VHDL source file. -- -- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2007 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; entity plbaddrpref is generic ( C_BASEADDR : std_logic_vector(31 downto 0) := X"80000000"; C_HIGHADDR : std_logic_vector(31 downto 0) := X"8000FFFF"; C_SPLB_DWIDTH : integer range 32 to 128 := 32; C_SPLB_NATIVE_DWIDTH : integer range 32 to 32 := 32 ); port ( addrpref : out std_logic_vector(20-1 downto 0); sl_rddbus : out std_logic_vector(0 to C_SPLB_DWIDTH-1); plb_wrdbus : in std_logic_vector(0 to C_SPLB_DWIDTH-1); sgsl_rddbus : in std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH-1); sgplb_wrdbus : out std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH-1) ); end plbaddrpref; architecture behavior of plbaddrpref is signal sl_rddbus_i : std_logic_vector(0 to C_SPLB_DWIDTH-1); begin addrpref <= C_BASEADDR(32-1 downto 12); ------------------------------------------------------------------------------- -- Mux/Steer data/be's correctly for connect 32-bit slave to 128-bit plb ------------------------------------------------------------------------------- GEN_128_TO_32_SLAVE : if C_SPLB_NATIVE_DWIDTH = 32 and C_SPLB_DWIDTH = 128 generate begin ----------------------------------------------------------------------- -- Map lower rd data to each quarter of the plb slave read bus ----------------------------------------------------------------------- sl_rddbus_i(0 to 31) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1); sl_rddbus_i(32 to 63) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1); sl_rddbus_i(64 to 95) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1); sl_rddbus_i(96 to 127) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1); end generate GEN_128_TO_32_SLAVE; ------------------------------------------------------------------------------- -- Mux/Steer data/be's correctly for connect 32-bit slave to 64-bit plb ------------------------------------------------------------------------------- GEN_64_TO_32_SLAVE : if C_SPLB_NATIVE_DWIDTH = 32 and C_SPLB_DWIDTH = 64 generate begin --------------------------------------------------------------------------- -- Map lower rd data to upper and lower halves of plb slave read bus --------------------------------------------------------------------------- sl_rddbus_i(0 to 31) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1); sl_rddbus_i(32 to 63) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1); end generate GEN_64_TO_32_SLAVE; ------------------------------------------------------------------------------- -- IPIF DWidth = PLB DWidth -- If IPIF Slave Data width is equal to the PLB Bus Data Width -- Then BE and Read Data Bus map directly to eachother. ------------------------------------------------------------------------------- GEN_FOR_EQUAL_SLAVE : if C_SPLB_NATIVE_DWIDTH = C_SPLB_DWIDTH generate sl_rddbus_i <= sgsl_rddbus; end generate GEN_FOR_EQUAL_SLAVE; sl_rddbus <= sl_rddbus_i; sgplb_wrdbus <= plb_wrdbus(0 to C_SPLB_NATIVE_DWIDTH-1); end behavior; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity sg_i2c_controller_s6_plbw is generic ( C_BASEADDR: std_logic_vector(31 downto 0) := X"80000000"; C_HIGHADDR: std_logic_vector(31 downto 0) := X"80000FFF"; C_SPLB_AWIDTH: integer := 0; C_SPLB_DWIDTH: integer := 0; C_SPLB_MID_WIDTH: integer := 0; C_SPLB_NATIVE_DWIDTH: integer := 0; C_SPLB_NUM_MASTERS: integer := 0; C_SPLB_SUPPORT_BURSTS: integer := 0; C_MEMMAP_CMD_RESPONSE: integer := 0; C_MEMMAP_CMD_RESPONSE_N_BITS: integer := 0; C_MEMMAP_CMD_RESPONSE_BIN_PT: integer := 0; C_MEMMAP_CMD_RESPONSE_PERCENTFULL: integer := 0; C_MEMMAP_CMD_RESPONSE_EMPTY: integer := 0; C_MEMMAP_CMD_REQUEST: integer := 0; C_MEMMAP_CMD_REQUEST_N_BITS: integer := 0; C_MEMMAP_CMD_REQUEST_BIN_PT: integer := 0; C_MEMMAP_CMD_REQUEST_PERCENTFULL: integer := 0; C_MEMMAP_CMD_REQUEST_FULL: integer := 0; C_MEMMAP_GPIO_OUT8: integer := 0; C_MEMMAP_GPIO_OUT8_N_BITS: integer := 0; C_MEMMAP_GPIO_OUT8_BIN_PT: integer := 0 ); port ( i2c_sda_i: in std_logic; plb_abus: in std_logic_vector(0 to 31); plb_pavalid: in std_logic; plb_rnw: in std_logic; plb_wrdbus: in std_logic_vector(0 to C_SPLB_DWIDTH-1); splb_clk: in std_logic; splb_rst: in std_logic; sysgen_clk: in std_logic; gpio_out8_o: out std_logic_vector(0 to 7); i2c_scl: out std_logic; i2c_sda_o: out std_logic; i2c_sda_t: out std_logic; sl_addrack: out std_logic; sl_rdcomp: out std_logic; sl_rddack: out std_logic; sl_rddbus: out std_logic_vector(0 to C_SPLB_DWIDTH-1); sl_wait: out std_logic; sl_wrcomp: out std_logic; sl_wrdack: out std_logic ); end sg_i2c_controller_s6_plbw; architecture structural of sg_i2c_controller_s6_plbw is signal clk: std_logic; signal gpio_out8_o_x0: std_logic_vector(7 downto 0); signal i2c_scl_x0: std_logic; signal i2c_sda_i_x0: std_logic; signal i2c_sda_o_x0: std_logic; signal i2c_sda_t_x0: std_logic; signal plb_abus_x0: std_logic_vector(31 downto 0); signal plb_pavalid_x0: std_logic; signal plb_rnw_x0: std_logic; signal plbaddrpref_addrpref_net: std_logic_vector(19 downto 0); signal plbaddrpref_plb_wrdbus_net: std_logic_vector(C_SPLB_DWIDTH-1 downto 0); signal plbaddrpref_sgplb_wrdbus_net: std_logic_vector(31 downto 0); signal plbaddrpref_sgsl_rddbus_net: std_logic_vector(31 downto 0); signal plbaddrpref_sl_rddbus_net: std_logic_vector(C_SPLB_DWIDTH-1 downto 0); signal sl_addrack_x0: std_logic; signal sl_rdcomp_x0: std_logic; signal sl_rddack_x0: std_logic; signal sl_wait_x0: std_logic; signal sl_wrcomp_x0: std_logic; signal sl_wrdack_x0: std_logic; signal splb_rst_x0: std_logic; signal xps_clk: std_logic; begin i2c_sda_i_x0 <= i2c_sda_i; plb_abus_x0 <= plb_abus; plb_pavalid_x0 <= plb_pavalid; plb_rnw_x0 <= plb_rnw; plbaddrpref_plb_wrdbus_net <= plb_wrdbus; xps_clk <= splb_clk; splb_rst_x0 <= splb_rst; clk <= sysgen_clk; gpio_out8_o <= gpio_out8_o_x0; i2c_scl <= i2c_scl_x0; i2c_sda_o <= i2c_sda_o_x0; i2c_sda_t <= i2c_sda_t_x0; sl_addrack <= sl_addrack_x0; sl_rdcomp <= sl_rdcomp_x0; sl_rddack <= sl_rddack_x0; sl_rddbus <= plbaddrpref_sl_rddbus_net; sl_wait <= sl_wait_x0; sl_wrcomp <= sl_wrcomp_x0; sl_wrdack <= sl_wrdack_x0; plbaddrpref_x0: entity work.plbaddrpref generic map ( C_BASEADDR => C_BASEADDR, C_HIGHADDR => C_HIGHADDR, C_SPLB_DWIDTH => C_SPLB_DWIDTH, C_SPLB_NATIVE_DWIDTH => C_SPLB_NATIVE_DWIDTH ) port map ( plb_wrdbus => plbaddrpref_plb_wrdbus_net, sgsl_rddbus => plbaddrpref_sgsl_rddbus_net, addrpref => plbaddrpref_addrpref_net, sgplb_wrdbus => plbaddrpref_sgplb_wrdbus_net, sl_rddbus => plbaddrpref_sl_rddbus_net ); sysgen_dut: entity work.sg_i2c_controller_s6_cw port map ( clk => clk, i2c_sda_i => i2c_sda_i_x0, plb_abus => plb_abus_x0, plb_pavalid => plb_pavalid_x0, plb_rnw => plb_rnw_x0, plb_wrdbus => plbaddrpref_sgplb_wrdbus_net, sg_plb_addrpref => plbaddrpref_addrpref_net, splb_rst => splb_rst_x0, xps_clk => xps_clk, gpio_out8_o => gpio_out8_o_x0, i2c_scl => i2c_scl_x0, i2c_sda_o => i2c_sda_o_x0, i2c_sda_t => i2c_sda_t_x0, sl_addrack => sl_addrack_x0, sl_rdcomp => sl_rdcomp_x0, sl_rddack => sl_rddack_x0, sl_rddbus => plbaddrpref_sgsl_rddbus_net, sl_wait => sl_wait_x0, sl_wrcomp => sl_wrcomp_x0, sl_wrdack => sl_wrdack_x0 ); end structural;
gpl-3.0
cc33eb4fbbed9db555586b693bce2872
0.60376
3.270608
false
false
false
false
tghaefli/ADD
EDK/IVK_Repos/IVK_IPLib/pcores/sg_i2c_controller_s6_plbw_v1_01_a/hdl/vhdl/fifo_generator_spartan6_6_1_ba61a4be12cec537.vhd
1
6,195
-------------------------------------------------------------------------------- -- This file is owned and controlled by Xilinx and must be used -- -- solely for design, simulation, implementation and creation of -- -- design files limited to Xilinx devices or technologies. Use -- -- with non-Xilinx devices or technologies is expressly prohibited -- -- and immediately terminates your license. -- -- -- -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- -- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- -- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- -- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- -- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- -- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- -- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- -- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- -- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- -- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- -- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- -- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- -- FOR A PARTICULAR PURPOSE. -- -- -- -- Xilinx products are not intended for use in life support -- -- appliances, devices, or systems. Use in such applications are -- -- expressly prohibited. -- -- -- -- (c) Copyright 1995-2009 Xilinx, Inc. -- -- All rights reserved. -- -------------------------------------------------------------------------------- -- You must compile the wrapper file fifo_generator_spartan6_6_1_ba61a4be12cec537.vhd when simulating -- the core, fifo_generator_spartan6_6_1_ba61a4be12cec537. When compiling the wrapper file, be sure to -- reference the XilinxCoreLib VHDL simulation library. For detailed -- instructions, please refer to the "CORE Generator Help". -- The synthesis directives "translate_off/translate_on" specified -- below are supported by Xilinx, Mentor Graphics and Synplicity -- synthesis tools. Ensure they are correct for your synthesis tool(s). LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- synthesis translate_off Library XilinxCoreLib; -- synthesis translate_on ENTITY fifo_generator_spartan6_6_1_ba61a4be12cec537 IS port ( rst: IN std_logic; wr_clk: IN std_logic; rd_clk: IN std_logic; din: IN std_logic_VECTOR(31 downto 0); wr_en: IN std_logic; rd_en: IN std_logic; dout: OUT std_logic_VECTOR(31 downto 0); full: OUT std_logic; empty: OUT std_logic; wr_data_count: OUT std_logic_VECTOR(0 downto 0)); END fifo_generator_spartan6_6_1_ba61a4be12cec537; ARCHITECTURE fifo_generator_spartan6_6_1_ba61a4be12cec537_a OF fifo_generator_spartan6_6_1_ba61a4be12cec537 IS -- synthesis translate_off component wrapped_fifo_generator_spartan6_6_1_ba61a4be12cec537 port ( rst: IN std_logic; wr_clk: IN std_logic; rd_clk: IN std_logic; din: IN std_logic_VECTOR(31 downto 0); wr_en: IN std_logic; rd_en: IN std_logic; dout: OUT std_logic_VECTOR(31 downto 0); full: OUT std_logic; empty: OUT std_logic; wr_data_count: OUT std_logic_VECTOR(0 downto 0)); end component; -- Configuration specification for all : wrapped_fifo_generator_spartan6_6_1_ba61a4be12cec537 use entity XilinxCoreLib.fifo_generator_v6_1(behavioral) generic map( c_has_int_clk => 0, c_wr_response_latency => 1, c_rd_freq => 1, c_has_srst => 0, c_enable_rst_sync => 1, c_has_rd_data_count => 0, c_din_width => 32, c_has_wr_data_count => 1, c_full_flags_rst_val => 1, c_implementation_type => 2, c_family => "spartan6", c_use_embedded_reg => 0, c_has_wr_rst => 0, c_wr_freq => 1, c_use_dout_rst => 1, c_underflow_low => 0, c_has_meminit_file => 0, c_has_overflow => 0, c_preload_latency => 1, c_dout_width => 32, c_msgon_val => 1, c_rd_depth => 32, c_default_value => "BlankString", c_mif_file_name => "BlankString", c_error_injection_type => 0, c_has_underflow => 0, c_has_rd_rst => 0, c_has_almost_full => 0, c_has_rst => 1, c_data_count_width => 5, c_has_wr_ack => 0, c_use_ecc => 0, c_wr_ack_low => 0, c_common_clock => 0, c_rd_pntr_width => 5, c_use_fwft_data_count => 0, c_has_almost_empty => 0, c_rd_data_count_width => 5, c_enable_rlocs => 0, c_wr_pntr_width => 5, c_overflow_low => 0, c_prog_empty_type => 0, c_optimization_mode => 0, c_wr_data_count_width => 1, c_preload_regs => 0, c_dout_rst_val => "0", c_has_data_count => 0, c_prog_full_thresh_negate_val => 28, c_wr_depth => 32, c_prog_empty_thresh_negate_val => 3, c_prog_empty_thresh_assert_val => 2, c_has_valid => 0, c_init_wr_pntr_val => 0, c_prog_full_thresh_assert_val => 29, c_use_fifo16_flags => 0, c_has_backup => 0, c_valid_low => 0, c_prim_fifo_type => "512x36", c_count_type => 0, c_prog_full_type => 0, c_memory_type => 2); -- synthesis translate_on BEGIN -- synthesis translate_off U0 : wrapped_fifo_generator_spartan6_6_1_ba61a4be12cec537 port map ( rst => rst, wr_clk => wr_clk, rd_clk => rd_clk, din => din, wr_en => wr_en, rd_en => rd_en, dout => dout, full => full, empty => empty, wr_data_count => wr_data_count); -- synthesis translate_on END fifo_generator_spartan6_6_1_ba61a4be12cec537_a;
gpl-3.0
04a850d3a6131fe8b4051e0db50423aa
0.566263
3.345032
false
false
false
false
GSimas/EEL5105
AULA9/C3.vhd
1
798
library IEEE; use IEEE.Std_Logic_1164.all; entity desloc_1_bit_esq is port( CLK: in std_logic; ENABLE : in std_logic; RST: in std_logic; sr_in: in std_logic_vector(7 downto 0); sr_out: out std_logic_vector(7 downto 0) ); end entity; architecture rtl of desloc_1_bit_esq is signal sr: std_logic_vector (7 downto 0); -- Registrador de N bits begin process (CLK, RST) begin if (RST = '0') then -- Reset assíncrono do registrador sr <= (others => '0'); elsif (rising_edge(CLK)) then -- Sinal de clock do registrador (subida) if (ENABLE = '1') then -- Sinal de enable do registrador sr(7 downto 1) <= sr_in(6 downto 0);-- Desloca 1 bit para a esquerda. Bit mais significativo é perdido. sr(0) <= '0'; end if; end if; end process; sr_out <= sr; end rtl;
mit
57f8457d63505edb7c5ac063a83b62f5
0.653266
2.802817
false
false
false
false
Alabamajack/Garfield
FPGA_Design/ip_intern/Rotary_Encoder/rotary_encoder.vhdl
1
2,353
--! @file library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity rotary_encoder is generic( --! the nominal frequency of the clock core_frequency : natural := 100_000_000; --! the width of the outputed counter register counter_width : natural := 32 ); port( --! the clk from the core clk : in std_logic; --! general reset from the core rst : in std_logic; --! for clearing the internal counter, this signal must be HIGH --! it only counts rising edges on the signal line! clear_counter : in std_logic; --! enable signal, if low, the counter will not count anymore enable : in std_logic; --! the counter register which contains counts since the last clear_counter or rst counter : out std_logic_vector(counter_width - 1 downto 0); --! shows if there was an error with the counting; if there was an error, the counter starts from zero counter_error : out boolean; --! the signal from outside the fpga system which comes from a led or rotary sensor rotary_signal : in std_logic ); end entity rotary_encoder; architecture RTL of rotary_encoder is signal old_signal : bit := '0'; signal internal_counter : unsigned(counter_width - 1 downto 0) := (others => '0'); signal reset_counter : boolean := false; begin reset_counter <= true when rst = '1' or clear_counter = '1' else false; counter <= std_logic_vector(internal_counter); signal_counting : process(clk) is begin if rising_edge(clk) then if reset_counter = true then internal_counter <= (others => '0'); else if enable = '1' then old_signal <= '0'; if rotary_signal = '0' and old_signal = '0' then -- nothing changed old_signal <= '0'; elsif rotary_signal = '0' and old_signal = '1' then -- falling edge old_signal <= '0'; elsif rotary_signal = '1' and old_signal = '0' then -- now there was a rising edge on the rotary_signal old_signal <= '1'; internal_counter <= internal_counter + 1; elsif rotary_signal = '1' and old_signal = '1' then -- there was and is high level old_signal <= '1'; else counter_error <= true; internal_counter <= (others => '0'); end if; end if; end if; end if; end process signal_counting; end architecture RTL;
gpl-3.0
e49ec444c97cda907c6b4c09c282e1b8
0.639609
3.435036
false
false
false
false
hoglet67/AtomFpga
src/common/AVR8/MemArbAndMux/ArbiterAndMux.vhd
4
3,240
--************************************************************************************************ -- Arrbiter and Address/Data multiplexer for AVR core -- Version 0.2 -- Designed by Ruslan Lepetenok -- Modified 27.07.2005 --************************************************************************************************ library IEEE; use IEEE.std_logic_1164.all; use WORK.MemAccessCtrlPack.all; entity ArbiterAndMux is port( --Clock and reset ireset : in std_logic; cp2 : in std_logic; -- Bus masters busmin : in MastersOutBus_Type; busmwait : out std_logic_vector(CNumOfBusMasters-1 downto 0); -- Memory Address,Data and Control ramadr : out std_logic_vector(15 downto 0); ramdout : out std_logic_vector(7 downto 0); ramre : out std_logic; ramwe : out std_logic; cpuwait : in std_logic ); end ArbiterAndMux; architecture RTL of ArbiterAndMux is signal sel_mast : std_logic_vector(CNumOfBusMasters-1 downto 0); signal sel_mast_rg : std_logic_vector(sel_mast'range); constant c_zero_vect : std_logic_vector(CNumOfBusMasters-1 downto 0) := (others => '0'); begin StoreBusMNum:process(ireset,cp2) begin if (ireset='0') then -- Reset sel_mast_rg <= (others => '0'); elsif (cp2='1' and cp2'event) then -- Clock if(cpuwait='1') then -- Store selected bus master number sel_mast_rg <= sel_mast; end if; end if; end process; -- Fixed priority arbitration ArbitrationComb:process(busmin) -- Combinatorial begin sel_mast <= (others => '0'); for i in 0 to CNumOfBusMasters-1 loop if(busmin(i).ramre='1' or busmin(i).ramwe='1') then sel_mast(i) <= '1'; exit; end if; end loop; end process; MuxComb:process(busmin,sel_mast,sel_mast_rg,cpuwait) -- Combinatorial begin ramadr <= (others => '0'); ramdout <= (others => '0'); ramre <= '0'; ramwe <= '0'; for i in 0 to CNumOfBusMasters-1 loop if(cpuwait='1') then if(sel_mast_rg(i)='1') then ramadr <= busmin(i).ramadr; ramdout <= busmin(i).dout; ramre <= busmin(i).ramre; ramwe <= busmin(i).ramwe; end if; else -- cpuwait='0' if(sel_mast(i)='1') then ramadr <= busmin(i).ramadr; ramdout <= busmin(i).dout; ramre <= busmin(i).ramre; ramwe <= busmin(i).ramwe; end if; end if; end loop; end process; WaitGenComb:process(cpuwait,busmin,sel_mast) -- Combinatorial begin busmwait <= (others => '0'); if((busmin(busmwait'low).ramre='1' or busmin(busmwait'low).ramwe='1') and cpuwait='1') then busmwait(busmwait'low) <= '1'; end if; for i in 1 to CNumOfBusMasters-1 loop if((busmin(i).ramre='1' or busmin(i).ramwe='1')and(sel_mast(i-1 downto 0)/=c_zero_vect(i-1 downto 0) or cpuwait='1')) then busmwait(i) <= '1'; end if; end loop; end process; -- For the purpose of test only --ramdout(sel_mast'range) <= sel_mast; -- For the purpose of test only end RTL;
apache-2.0
b426cdfa3513c4c16ee740a4d5e7cd40
0.540741
3.340206
false
false
false
false
GSimas/EEL5105
Eletr-Digital/Relatório4/Controle de Motor de Passo/divisor10.vhd
1
4,579
-- megafunction wizard: %LPM_COUNTER% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: lpm_counter -- ============================================================ -- File Name: divisor10.vhd -- Megafunction Name(s): -- lpm_counter -- -- Simulation Library Files(s): -- lpm -- ============================================================ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- -- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition -- ************************************************************ --Copyright (C) 1991-2010 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject --to the terms and conditions of the Altera Program License --Subscription Agreement, Altera MegaCore Function License --Agreement, or other applicable license agreement, including, --without limitation, that your use is for the sole purpose of --programming logic devices manufactured by Altera and sold by --Altera or its authorized distributors. Please refer to the --applicable agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY lpm; USE lpm.all; ENTITY divisor10 IS PORT ( clock : IN STD_LOGIC ; cout : OUT STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (29 DOWNTO 0) ); END divisor10; ARCHITECTURE SYN OF divisor10 IS SIGNAL sub_wire0 : STD_LOGIC ; SIGNAL sub_wire1 : STD_LOGIC_VECTOR (29 DOWNTO 0); COMPONENT lpm_counter GENERIC ( lpm_direction : STRING; lpm_modulus : NATURAL; lpm_port_updown : STRING; lpm_type : STRING; lpm_width : NATURAL ); PORT ( clock : IN STD_LOGIC ; cout : OUT STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (29 DOWNTO 0) ); END COMPONENT; BEGIN cout <= sub_wire0; q <= sub_wire1(29 DOWNTO 0); lpm_counter_component : lpm_counter GENERIC MAP ( lpm_direction => "UP", lpm_modulus => 2500000, lpm_port_updown => "PORT_UNUSED", lpm_type => "LPM_COUNTER", lpm_width => 30 ) PORT MAP ( clock => clock, cout => sub_wire0, q => sub_wire1 ); END SYN; -- ============================================================ -- CNX file retrieval info -- ============================================================ -- Retrieval info: PRIVATE: ACLR NUMERIC "0" -- Retrieval info: PRIVATE: ALOAD NUMERIC "0" -- Retrieval info: PRIVATE: ASET NUMERIC "0" -- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1" -- Retrieval info: PRIVATE: CLK_EN NUMERIC "0" -- Retrieval info: PRIVATE: CNT_EN NUMERIC "0" -- Retrieval info: PRIVATE: CarryIn NUMERIC "0" -- Retrieval info: PRIVATE: CarryOut NUMERIC "1" -- Retrieval info: PRIVATE: Direction NUMERIC "0" -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" -- Retrieval info: PRIVATE: ModulusCounter NUMERIC "1" -- Retrieval info: PRIVATE: ModulusValue NUMERIC "2500000" -- Retrieval info: PRIVATE: SCLR NUMERIC "0" -- Retrieval info: PRIVATE: SLOAD NUMERIC "0" -- Retrieval info: PRIVATE: SSET NUMERIC "0" -- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: nBit NUMERIC "30" -- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP" -- Retrieval info: CONSTANT: LPM_MODULUS NUMERIC "2500000" -- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER" -- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "30" -- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock -- Retrieval info: USED_PORT: cout 0 0 0 0 OUTPUT NODEFVAL cout -- Retrieval info: USED_PORT: q 0 0 30 0 OUTPUT NODEFVAL q[29..0] -- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 -- Retrieval info: CONNECT: q 0 0 30 0 @q 0 0 30 0 -- Retrieval info: CONNECT: cout 0 0 0 0 @cout 0 0 0 0 -- Retrieval info: LIBRARY: lpm lpm.lpm_components.all -- Retrieval info: GEN_FILE: TYPE_NORMAL divisor10.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL divisor10.inc TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL divisor10.cmp TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL divisor10.bsf TRUE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL divisor10_inst.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL divisor10_waveforms.html TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL divisor10_wave*.jpg FALSE -- Retrieval info: LIB_FILE: lpm
mit
a7869efca75b797e4cfdc0df8f588319
0.656912
3.710697
false
false
false
false
fquinto/Wireless_sensor_network
Avnet_UPC/hdl/xps_timer_0_wrapper.vhd
1
7,219
------------------------------------------------------------------------------- -- xps_timer_0_wrapper.vhd ------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; library xps_timer_v1_02_a; use xps_timer_v1_02_a.all; entity xps_timer_0_wrapper is port ( CaptureTrig0 : in std_logic; CaptureTrig1 : in std_logic; GenerateOut0 : out std_logic; GenerateOut1 : out std_logic; PWM0 : out std_logic; Interrupt : out std_logic; Freeze : in std_logic; SPLB_Clk : in std_logic; SPLB_Rst : in std_logic; PLB_ABus : in std_logic_vector(0 to 31); PLB_PAValid : in std_logic; PLB_masterID : in std_logic_vector(0 to 0); PLB_RNW : in std_logic; PLB_BE : in std_logic_vector(0 to 3); PLB_size : in std_logic_vector(0 to 3); PLB_type : in std_logic_vector(0 to 2); PLB_wrDBus : in std_logic_vector(0 to 31); Sl_addrAck : out std_logic; Sl_SSize : out std_logic_vector(0 to 1); Sl_wait : out std_logic; Sl_rearbitrate : out std_logic; Sl_wrDAck : out std_logic; Sl_wrComp : out std_logic; Sl_rdDBus : out std_logic_vector(0 to 31); Sl_rdDAck : out std_logic; Sl_rdComp : out std_logic; Sl_MBusy : out std_logic_vector(0 to 1); Sl_MWrErr : out std_logic_vector(0 to 1); Sl_MRdErr : out std_logic_vector(0 to 1); PLB_UABus : in std_logic_vector(0 to 31); PLB_SAValid : in std_logic; PLB_rdPrim : in std_logic; PLB_wrPrim : in std_logic; PLB_abort : in std_logic; PLB_busLock : in std_logic; PLB_MSize : in std_logic_vector(0 to 1); PLB_lockErr : in std_logic; PLB_wrBurst : in std_logic; PLB_rdBurst : in std_logic; PLB_wrPendReq : in std_logic; PLB_rdPendReq : in std_logic; PLB_wrPendPri : in std_logic_vector(0 to 1); PLB_rdPendPri : in std_logic_vector(0 to 1); PLB_reqPri : in std_logic_vector(0 to 1); PLB_TAttribute : in std_logic_vector(0 to 15); Sl_wrBTerm : out std_logic; Sl_rdWdAddr : out std_logic_vector(0 to 3); Sl_rdBTerm : out std_logic; Sl_MIRQ : out std_logic_vector(0 to 1) ); attribute x_core_info : STRING; attribute x_core_info of xps_timer_0_wrapper : entity is "xps_timer_v1_02_a"; end xps_timer_0_wrapper; architecture STRUCTURE of xps_timer_0_wrapper is component xps_timer is generic ( C_FAMILY : STRING; C_COUNT_WIDTH : INTEGER; C_ONE_TIMER_ONLY : INTEGER; C_TRIG0_ASSERT : std_logic; C_TRIG1_ASSERT : std_logic; C_GEN0_ASSERT : std_logic; C_GEN1_ASSERT : std_logic; C_BASEADDR : std_logic_vector; C_HIGHADDR : std_logic_vector; C_SPLB_AWIDTH : INTEGER; C_SPLB_DWIDTH : INTEGER; C_SPLB_P2P : INTEGER; C_SPLB_MID_WIDTH : INTEGER; C_SPLB_NUM_MASTERS : INTEGER; C_SPLB_SUPPORT_BURSTS : INTEGER; C_SPLB_NATIVE_DWIDTH : INTEGER ); port ( CaptureTrig0 : in std_logic; CaptureTrig1 : in std_logic; GenerateOut0 : out std_logic; GenerateOut1 : out std_logic; PWM0 : out std_logic; Interrupt : out std_logic; Freeze : in std_logic; SPLB_Clk : in std_logic; SPLB_Rst : in std_logic; PLB_ABus : in std_logic_vector(0 to C_SPLB_AWIDTH-1); PLB_PAValid : in std_logic; PLB_masterID : in std_logic_vector(0 to (C_SPLB_MID_WIDTH-1)); PLB_RNW : in std_logic; PLB_BE : in std_logic_vector(0 to ((C_SPLB_DWIDTH/8)-1)); PLB_size : in std_logic_vector(0 to 3); PLB_type : in std_logic_vector(0 to 2); PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_DWIDTH-1)); Sl_addrAck : out std_logic; Sl_SSize : out std_logic_vector(0 to 1); Sl_wait : out std_logic; Sl_rearbitrate : out std_logic; Sl_wrDAck : out std_logic; Sl_wrComp : out std_logic; Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_DWIDTH-1)); Sl_rdDAck : out std_logic; Sl_rdComp : out std_logic; Sl_MBusy : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1)); Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1)); Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1)); PLB_UABus : in std_logic_vector(0 to C_SPLB_AWIDTH-1); PLB_SAValid : in std_logic; PLB_rdPrim : in std_logic; PLB_wrPrim : in std_logic; PLB_abort : in std_logic; PLB_busLock : in std_logic; PLB_MSize : in std_logic_vector(0 to 1); PLB_lockErr : in std_logic; PLB_wrBurst : in std_logic; PLB_rdBurst : in std_logic; PLB_wrPendReq : in std_logic; PLB_rdPendReq : in std_logic; PLB_wrPendPri : in std_logic_vector(0 to 1); PLB_rdPendPri : in std_logic_vector(0 to 1); PLB_reqPri : in std_logic_vector(0 to 1); PLB_TAttribute : in std_logic_vector(0 to 15); Sl_wrBTerm : out std_logic; Sl_rdWdAddr : out std_logic_vector(0 to 3); Sl_rdBTerm : out std_logic; Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1)) ); end component; begin xps_timer_0 : xps_timer generic map ( C_FAMILY => "spartan3a", C_COUNT_WIDTH => 32, C_ONE_TIMER_ONLY => 1, C_TRIG0_ASSERT => '1', C_TRIG1_ASSERT => '1', C_GEN0_ASSERT => '1', C_GEN1_ASSERT => '1', C_BASEADDR => X"83c00000", C_HIGHADDR => X"83c0ffff", C_SPLB_AWIDTH => 32, C_SPLB_DWIDTH => 32, C_SPLB_P2P => 0, C_SPLB_MID_WIDTH => 1, C_SPLB_NUM_MASTERS => 2, C_SPLB_SUPPORT_BURSTS => 0, C_SPLB_NATIVE_DWIDTH => 32 ) port map ( CaptureTrig0 => CaptureTrig0, CaptureTrig1 => CaptureTrig1, GenerateOut0 => GenerateOut0, GenerateOut1 => GenerateOut1, PWM0 => PWM0, Interrupt => Interrupt, Freeze => Freeze, SPLB_Clk => SPLB_Clk, SPLB_Rst => SPLB_Rst, PLB_ABus => PLB_ABus, PLB_PAValid => PLB_PAValid, PLB_masterID => PLB_masterID, PLB_RNW => PLB_RNW, PLB_BE => PLB_BE, PLB_size => PLB_size, PLB_type => PLB_type, PLB_wrDBus => PLB_wrDBus, Sl_addrAck => Sl_addrAck, Sl_SSize => Sl_SSize, Sl_wait => Sl_wait, Sl_rearbitrate => Sl_rearbitrate, Sl_wrDAck => Sl_wrDAck, Sl_wrComp => Sl_wrComp, Sl_rdDBus => Sl_rdDBus, Sl_rdDAck => Sl_rdDAck, Sl_rdComp => Sl_rdComp, Sl_MBusy => Sl_MBusy, Sl_MWrErr => Sl_MWrErr, Sl_MRdErr => Sl_MRdErr, PLB_UABus => PLB_UABus, PLB_SAValid => PLB_SAValid, PLB_rdPrim => PLB_rdPrim, PLB_wrPrim => PLB_wrPrim, PLB_abort => PLB_abort, PLB_busLock => PLB_busLock, PLB_MSize => PLB_MSize, PLB_lockErr => PLB_lockErr, PLB_wrBurst => PLB_wrBurst, PLB_rdBurst => PLB_rdBurst, PLB_wrPendReq => PLB_wrPendReq, PLB_rdPendReq => PLB_rdPendReq, PLB_wrPendPri => PLB_wrPendPri, PLB_rdPendPri => PLB_rdPendPri, PLB_reqPri => PLB_reqPri, PLB_TAttribute => PLB_TAttribute, Sl_wrBTerm => Sl_wrBTerm, Sl_rdWdAddr => Sl_rdWdAddr, Sl_rdBTerm => Sl_rdBTerm, Sl_MIRQ => Sl_MIRQ ); end architecture STRUCTURE;
mit
568d19c1a58d17f40d4bc5bfdfb035a3
0.586369
3.231423
false
false
false
false
hoglet67/AtomFpga
src/common/ROM/float.vhd
2
172,738
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity atomfloat is port ( CLK : in std_logic; ADDR : in std_logic_vector(11 downto 0); DATA : out std_logic_vector(7 downto 0) ); end; architecture RTL of atomfloat is signal rom_addr : std_logic_vector(11 downto 0); begin p_addr : process(ADDR) begin rom_addr <= (others => '0'); rom_addr(11 downto 0) <= ADDR; end process; p_rom : process begin wait until rising_edge(CLK); DATA <= (others => '0'); case rom_addr is when x"000" => DATA <= x"AA"; when x"001" => DATA <= x"55"; when x"002" => DATA <= x"0E"; when x"003" => DATA <= x"D1"; when x"004" => DATA <= x"5E"; when x"005" => DATA <= x"D1"; when x"006" => DATA <= x"28"; when x"007" => DATA <= x"D0"; when x"008" => DATA <= x"E4"; when x"009" => DATA <= x"41"; when x"00A" => DATA <= x"43"; when x"00B" => DATA <= x"53"; when x"00C" => DATA <= x"D2"; when x"00D" => DATA <= x"1E"; when x"00E" => DATA <= x"41"; when x"00F" => DATA <= x"53"; when x"010" => DATA <= x"4E"; when x"011" => DATA <= x"D2"; when x"012" => DATA <= x"24"; when x"013" => DATA <= x"41"; when x"014" => DATA <= x"54"; when x"015" => DATA <= x"4E"; when x"016" => DATA <= x"DC"; when x"017" => DATA <= x"64"; when x"018" => DATA <= x"41"; when x"019" => DATA <= x"42"; when x"01A" => DATA <= x"53"; when x"01B" => DATA <= x"D2"; when x"01C" => DATA <= x"15"; when x"01D" => DATA <= x"43"; when x"01E" => DATA <= x"4F"; when x"01F" => DATA <= x"53"; when x"020" => DATA <= x"DC"; when x"021" => DATA <= x"E3"; when x"022" => DATA <= x"45"; when x"023" => DATA <= x"58"; when x"024" => DATA <= x"50"; when x"025" => DATA <= x"DD"; when x"026" => DATA <= x"D4"; when x"027" => DATA <= x"48"; when x"028" => DATA <= x"54"; when x"029" => DATA <= x"4E"; when x"02A" => DATA <= x"DE"; when x"02B" => DATA <= x"72"; when x"02C" => DATA <= x"4C"; when x"02D" => DATA <= x"4F"; when x"02E" => DATA <= x"47"; when x"02F" => DATA <= x"DB"; when x"030" => DATA <= x"B3"; when x"031" => DATA <= x"50"; when x"032" => DATA <= x"49"; when x"033" => DATA <= x"D2"; when x"034" => DATA <= x"C3"; when x"035" => DATA <= x"53"; when x"036" => DATA <= x"49"; when x"037" => DATA <= x"4E"; when x"038" => DATA <= x"DC"; when x"039" => DATA <= x"EE"; when x"03A" => DATA <= x"53"; when x"03B" => DATA <= x"51"; when x"03C" => DATA <= x"52"; when x"03D" => DATA <= x"DB"; when x"03E" => DATA <= x"6F"; when x"03F" => DATA <= x"54"; when x"040" => DATA <= x"41"; when x"041" => DATA <= x"4E"; when x"042" => DATA <= x"DA"; when x"043" => DATA <= x"C4"; when x"044" => DATA <= x"44"; when x"045" => DATA <= x"45"; when x"046" => DATA <= x"47"; when x"047" => DATA <= x"D2"; when x"048" => DATA <= x"73"; when x"049" => DATA <= x"52"; when x"04A" => DATA <= x"41"; when x"04B" => DATA <= x"44"; when x"04C" => DATA <= x"D2"; when x"04D" => DATA <= x"65"; when x"04E" => DATA <= x"53"; when x"04F" => DATA <= x"47"; when x"050" => DATA <= x"4E"; when x"051" => DATA <= x"D2"; when x"052" => DATA <= x"86"; when x"053" => DATA <= x"56"; when x"054" => DATA <= x"41"; when x"055" => DATA <= x"4C"; when x"056" => DATA <= x"D2"; when x"057" => DATA <= x"E0"; when x"058" => DATA <= x"46"; when x"059" => DATA <= x"4C"; when x"05A" => DATA <= x"54"; when x"05B" => DATA <= x"D2"; when x"05C" => DATA <= x"9A"; when x"05D" => DATA <= x"46"; when x"05E" => DATA <= x"47"; when x"05F" => DATA <= x"45"; when x"060" => DATA <= x"54"; when x"061" => DATA <= x"D2"; when x"062" => DATA <= x"CC"; when x"063" => DATA <= x"D2"; when x"064" => DATA <= x"96"; when x"065" => DATA <= x"25"; when x"066" => DATA <= x"D3"; when x"067" => DATA <= x"0B"; when x"068" => DATA <= x"46"; when x"069" => DATA <= x"49"; when x"06A" => DATA <= x"46"; when x"06B" => DATA <= x"D3"; when x"06C" => DATA <= x"A8"; when x"06D" => DATA <= x"46"; when x"06E" => DATA <= x"55"; when x"06F" => DATA <= x"4E"; when x"070" => DATA <= x"54"; when x"071" => DATA <= x"49"; when x"072" => DATA <= x"4C"; when x"073" => DATA <= x"D3"; when x"074" => DATA <= x"AE"; when x"075" => DATA <= x"43"; when x"076" => DATA <= x"4F"; when x"077" => DATA <= x"4C"; when x"078" => DATA <= x"4F"; when x"079" => DATA <= x"55"; when x"07A" => DATA <= x"52"; when x"07B" => DATA <= x"DF"; when x"07C" => DATA <= x"02"; when x"07D" => DATA <= x"46"; when x"07E" => DATA <= x"44"; when x"07F" => DATA <= x"49"; when x"080" => DATA <= x"4D"; when x"081" => DATA <= x"D3"; when x"082" => DATA <= x"D3"; when x"083" => DATA <= x"53"; when x"084" => DATA <= x"54"; when x"085" => DATA <= x"52"; when x"086" => DATA <= x"D3"; when x"087" => DATA <= x"1F"; when x"088" => DATA <= x"46"; when x"089" => DATA <= x"50"; when x"08A" => DATA <= x"52"; when x"08B" => DATA <= x"49"; when x"08C" => DATA <= x"4E"; when x"08D" => DATA <= x"54"; when x"08E" => DATA <= x"D3"; when x"08F" => DATA <= x"31"; when x"090" => DATA <= x"46"; when x"091" => DATA <= x"49"; when x"092" => DATA <= x"4E"; when x"093" => DATA <= x"50"; when x"094" => DATA <= x"55"; when x"095" => DATA <= x"54"; when x"096" => DATA <= x"D3"; when x"097" => DATA <= x"6A"; when x"098" => DATA <= x"46"; when x"099" => DATA <= x"50"; when x"09A" => DATA <= x"55"; when x"09B" => DATA <= x"54"; when x"09C" => DATA <= x"D3"; when x"09D" => DATA <= x"B4"; when x"09E" => DATA <= x"D4"; when x"09F" => DATA <= x"AF"; when x"0A0" => DATA <= x"2B"; when x"0A1" => DATA <= x"D1"; when x"0A2" => DATA <= x"77"; when x"0A3" => DATA <= x"2D"; when x"0A4" => DATA <= x"D1"; when x"0A5" => DATA <= x"83"; when x"0A6" => DATA <= x"FE"; when x"0A7" => DATA <= x"2A"; when x"0A8" => DATA <= x"D1"; when x"0A9" => DATA <= x"8F"; when x"0AA" => DATA <= x"2F"; when x"0AB" => DATA <= x"D1"; when x"0AC" => DATA <= x"9B"; when x"0AD" => DATA <= x"FE"; when x"0AE" => DATA <= x"5E"; when x"0AF" => DATA <= x"D1"; when x"0B0" => DATA <= x"A7"; when x"0B1" => DATA <= x"FE"; when x"0B2" => DATA <= x"2B"; when x"0B3" => DATA <= x"D1"; when x"0B4" => DATA <= x"CB"; when x"0B5" => DATA <= x"2D"; when x"0B6" => DATA <= x"D1"; when x"0B7" => DATA <= x"BC"; when x"0B8" => DATA <= x"D1"; when x"0B9" => DATA <= x"CB"; when x"0BA" => DATA <= x"29"; when x"0BB" => DATA <= x"C2"; when x"0BC" => DATA <= x"78"; when x"0BD" => DATA <= x"FF"; when x"0BE" => DATA <= x"3B"; when x"0BF" => DATA <= x"C5"; when x"0C0" => DATA <= x"4A"; when x"0C1" => DATA <= x"0D"; when x"0C2" => DATA <= x"C5"; when x"0C3" => DATA <= x"4A"; when x"0C4" => DATA <= x"2C"; when x"0C5" => DATA <= x"D3"; when x"0C6" => DATA <= x"31"; when x"0C7" => DATA <= x"D3"; when x"0C8" => DATA <= x"39"; when x"0C9" => DATA <= x"2C"; when x"0CA" => DATA <= x"D3"; when x"0CB" => DATA <= x"6A"; when x"0CC" => DATA <= x"C5"; when x"0CD" => DATA <= x"58"; when x"0CE" => DATA <= x"3D"; when x"0CF" => DATA <= x"D9"; when x"0D0" => DATA <= x"F6"; when x"0D1" => DATA <= x"3C"; when x"0D2" => DATA <= x"3E"; when x"0D3" => DATA <= x"D9"; when x"0D4" => DATA <= x"FE"; when x"0D5" => DATA <= x"3C"; when x"0D6" => DATA <= x"3D"; when x"0D7" => DATA <= x"D9"; when x"0D8" => DATA <= x"FA"; when x"0D9" => DATA <= x"3C"; when x"0DA" => DATA <= x"DA"; when x"0DB" => DATA <= x"02"; when x"0DC" => DATA <= x"3E"; when x"0DD" => DATA <= x"3D"; when x"0DE" => DATA <= x"DA"; when x"0DF" => DATA <= x"06"; when x"0E0" => DATA <= x"3E"; when x"0E1" => DATA <= x"DA"; when x"0E2" => DATA <= x"0A"; when x"0E3" => DATA <= x"FF"; when x"0E4" => DATA <= x"20"; when x"0E5" => DATA <= x"FC"; when x"0E6" => DATA <= x"D0"; when x"0E7" => DATA <= x"A2"; when x"0E8" => DATA <= x"B4"; when x"0E9" => DATA <= x"D0"; when x"0EA" => DATA <= x"20"; when x"0EB" => DATA <= x"18"; when x"0EC" => DATA <= x"66"; when x"0ED" => DATA <= x"73"; when x"0EE" => DATA <= x"A2"; when x"0EF" => DATA <= x"AC"; when x"0F0" => DATA <= x"D0"; when x"0F1" => DATA <= x"19"; when x"0F2" => DATA <= x"20"; when x"0F3" => DATA <= x"5D"; when x"0F4" => DATA <= x"D8"; when x"0F5" => DATA <= x"20"; when x"0F6" => DATA <= x"06"; when x"0F7" => DATA <= x"D1"; when x"0F8" => DATA <= x"A2"; when x"0F9" => DATA <= x"A1"; when x"0FA" => DATA <= x"D0"; when x"0FB" => DATA <= x"0F"; when x"0FC" => DATA <= x"20"; when x"0FD" => DATA <= x"F5"; when x"0FE" => DATA <= x"D0"; when x"0FF" => DATA <= x"A2"; when x"100" => DATA <= x"9A"; when x"101" => DATA <= x"D0"; when x"102" => DATA <= x"08"; when x"103" => DATA <= x"20"; when x"104" => DATA <= x"5D"; when x"105" => DATA <= x"D8"; when x"106" => DATA <= x"20"; when x"107" => DATA <= x"EB"; when x"108" => DATA <= x"D0"; when x"109" => DATA <= x"A2"; when x"10A" => DATA <= x"A8"; when x"10B" => DATA <= x"18"; when x"10C" => DATA <= x"90"; when x"10D" => DATA <= x"05"; when x"10E" => DATA <= x"A2"; when x"10F" => DATA <= x"5F"; when x"110" => DATA <= x"84"; when x"111" => DATA <= x"03"; when x"112" => DATA <= x"38"; when x"113" => DATA <= x"66"; when x"114" => DATA <= x"53"; when x"115" => DATA <= x"A4"; when x"116" => DATA <= x"03"; when x"117" => DATA <= x"88"; when x"118" => DATA <= x"C8"; when x"119" => DATA <= x"B1"; when x"11A" => DATA <= x"05"; when x"11B" => DATA <= x"C9"; when x"11C" => DATA <= x"20"; when x"11D" => DATA <= x"F0"; when x"11E" => DATA <= x"F9"; when x"11F" => DATA <= x"88"; when x"120" => DATA <= x"84"; when x"121" => DATA <= x"52"; when x"122" => DATA <= x"CA"; when x"123" => DATA <= x"A4"; when x"124" => DATA <= x"52"; when x"125" => DATA <= x"E8"; when x"126" => DATA <= x"C8"; when x"127" => DATA <= x"BD"; when x"128" => DATA <= x"06"; when x"129" => DATA <= x"D0"; when x"12A" => DATA <= x"30"; when x"12B" => DATA <= x"1A"; when x"12C" => DATA <= x"D1"; when x"12D" => DATA <= x"05"; when x"12E" => DATA <= x"F0"; when x"12F" => DATA <= x"F5"; when x"130" => DATA <= x"CA"; when x"131" => DATA <= x"E8"; when x"132" => DATA <= x"BD"; when x"133" => DATA <= x"06"; when x"134" => DATA <= x"D0"; when x"135" => DATA <= x"10"; when x"136" => DATA <= x"FA"; when x"137" => DATA <= x"E8"; when x"138" => DATA <= x"24"; when x"139" => DATA <= x"53"; when x"13A" => DATA <= x"10"; when x"13B" => DATA <= x"E7"; when x"13C" => DATA <= x"B1"; when x"13D" => DATA <= x"05"; when x"13E" => DATA <= x"C9"; when x"13F" => DATA <= x"2E"; when x"140" => DATA <= x"D0"; when x"141" => DATA <= x"E1"; when x"142" => DATA <= x"C8"; when x"143" => DATA <= x"CA"; when x"144" => DATA <= x"B0"; when x"145" => DATA <= x"E1"; when x"146" => DATA <= x"C9"; when x"147" => DATA <= x"FE"; when x"148" => DATA <= x"B0"; when x"149" => DATA <= x"11"; when x"14A" => DATA <= x"85"; when x"14B" => DATA <= x"53"; when x"14C" => DATA <= x"BD"; when x"14D" => DATA <= x"07"; when x"14E" => DATA <= x"D0"; when x"14F" => DATA <= x"85"; when x"150" => DATA <= x"52"; when x"151" => DATA <= x"84"; when x"152" => DATA <= x"03"; when x"153" => DATA <= x"A6"; when x"154" => DATA <= x"04"; when x"155" => DATA <= x"6C"; when x"156" => DATA <= x"52"; when x"157" => DATA <= x"00"; when x"158" => DATA <= x"A6"; when x"159" => DATA <= x"04"; when x"15A" => DATA <= x"60"; when x"15B" => DATA <= x"F0"; when x"15C" => DATA <= x"FB"; when x"15D" => DATA <= x"00"; when x"15E" => DATA <= x"84"; when x"15F" => DATA <= x"03"; when x"160" => DATA <= x"20"; when x"161" => DATA <= x"EC"; when x"162" => DATA <= x"D0"; when x"163" => DATA <= x"20"; when x"164" => DATA <= x"9A"; when x"165" => DATA <= x"D8"; when x"166" => DATA <= x"A5"; when x"167" => DATA <= x"5A"; when x"168" => DATA <= x"85"; when x"169" => DATA <= x"60"; when x"16A" => DATA <= x"A5"; when x"16B" => DATA <= x"5B"; when x"16C" => DATA <= x"85"; when x"16D" => DATA <= x"5F"; when x"16E" => DATA <= x"A5"; when x"16F" => DATA <= x"5C"; when x"170" => DATA <= x"85"; when x"171" => DATA <= x"5E"; when x"172" => DATA <= x"A0"; when x"173" => DATA <= x"5D"; when x"174" => DATA <= x"4C"; when x"175" => DATA <= x"9F"; when x"176" => DATA <= x"C9"; when x"177" => DATA <= x"20"; when x"178" => DATA <= x"F2"; when x"179" => DATA <= x"D0"; when x"17A" => DATA <= x"20"; when x"17B" => DATA <= x"70"; when x"17C" => DATA <= x"D8"; when x"17D" => DATA <= x"20"; when x"17E" => DATA <= x"3C"; when x"17F" => DATA <= x"D9"; when x"180" => DATA <= x"4C"; when x"181" => DATA <= x"FF"; when x"182" => DATA <= x"D0"; when x"183" => DATA <= x"20"; when x"184" => DATA <= x"F2"; when x"185" => DATA <= x"D0"; when x"186" => DATA <= x"20"; when x"187" => DATA <= x"70"; when x"188" => DATA <= x"D8"; when x"189" => DATA <= x"20"; when x"18A" => DATA <= x"39"; when x"18B" => DATA <= x"D9"; when x"18C" => DATA <= x"4C"; when x"18D" => DATA <= x"FF"; when x"18E" => DATA <= x"D0"; when x"18F" => DATA <= x"20"; when x"190" => DATA <= x"03"; when x"191" => DATA <= x"D1"; when x"192" => DATA <= x"20"; when x"193" => DATA <= x"70"; when x"194" => DATA <= x"D8"; when x"195" => DATA <= x"20"; when x"196" => DATA <= x"45"; when x"197" => DATA <= x"DA"; when x"198" => DATA <= x"4C"; when x"199" => DATA <= x"F8"; when x"19A" => DATA <= x"D0"; when x"19B" => DATA <= x"20"; when x"19C" => DATA <= x"03"; when x"19D" => DATA <= x"D1"; when x"19E" => DATA <= x"20"; when x"19F" => DATA <= x"70"; when x"1A0" => DATA <= x"D8"; when x"1A1" => DATA <= x"20"; when x"1A2" => DATA <= x"B6"; when x"1A3" => DATA <= x"DA"; when x"1A4" => DATA <= x"4C"; when x"1A5" => DATA <= x"F8"; when x"1A6" => DATA <= x"D0"; when x"1A7" => DATA <= x"20"; when x"1A8" => DATA <= x"B6"; when x"1A9" => DATA <= x"DB"; when x"1AA" => DATA <= x"20"; when x"1AB" => DATA <= x"5D"; when x"1AC" => DATA <= x"D8"; when x"1AD" => DATA <= x"20"; when x"1AE" => DATA <= x"EB"; when x"1AF" => DATA <= x"D0"; when x"1B0" => DATA <= x"20"; when x"1B1" => DATA <= x"70"; when x"1B2" => DATA <= x"D8"; when x"1B3" => DATA <= x"20"; when x"1B4" => DATA <= x"45"; when x"1B5" => DATA <= x"DA"; when x"1B6" => DATA <= x"20"; when x"1B7" => DATA <= x"D7"; when x"1B8" => DATA <= x"DD"; when x"1B9" => DATA <= x"4C"; when x"1BA" => DATA <= x"09"; when x"1BB" => DATA <= x"D1"; when x"1BC" => DATA <= x"20"; when x"1BD" => DATA <= x"CB"; when x"1BE" => DATA <= x"D1"; when x"1BF" => DATA <= x"20"; when x"1C0" => DATA <= x"86"; when x"1C1" => DATA <= x"D6"; when x"1C2" => DATA <= x"F0"; when x"1C3" => DATA <= x"06"; when x"1C4" => DATA <= x"A5"; when x"1C5" => DATA <= x"57"; when x"1C6" => DATA <= x"49"; when x"1C7" => DATA <= x"80"; when x"1C8" => DATA <= x"85"; when x"1C9" => DATA <= x"57"; when x"1CA" => DATA <= x"60"; when x"1CB" => DATA <= x"A4"; when x"1CC" => DATA <= x"03"; when x"1CD" => DATA <= x"88"; when x"1CE" => DATA <= x"C8"; when x"1CF" => DATA <= x"B1"; when x"1D0" => DATA <= x"05"; when x"1D1" => DATA <= x"C9"; when x"1D2" => DATA <= x"20"; when x"1D3" => DATA <= x"F0"; when x"1D4" => DATA <= x"F9"; when x"1D5" => DATA <= x"C9"; when x"1D6" => DATA <= x"25"; when x"1D7" => DATA <= x"D0"; when x"1D8" => DATA <= x"32"; when x"1D9" => DATA <= x"E6"; when x"1DA" => DATA <= x"03"; when x"1DB" => DATA <= x"20"; when x"1DC" => DATA <= x"44"; when x"1DD" => DATA <= x"D4"; when x"1DE" => DATA <= x"90"; when x"1DF" => DATA <= x"2B"; when x"1E0" => DATA <= x"A0"; when x"1E1" => DATA <= x"6F"; when x"1E2" => DATA <= x"20"; when x"1E3" => DATA <= x"CD"; when x"1E4" => DATA <= x"C3"; when x"1E5" => DATA <= x"A0"; when x"1E6" => DATA <= x"04"; when x"1E7" => DATA <= x"A9"; when x"1E8" => DATA <= x"00"; when x"1E9" => DATA <= x"85"; when x"1EA" => DATA <= x"5E"; when x"1EB" => DATA <= x"85"; when x"1EC" => DATA <= x"58"; when x"1ED" => DATA <= x"85"; when x"1EE" => DATA <= x"57"; when x"1EF" => DATA <= x"B1"; when x"1F0" => DATA <= x"6F"; when x"1F1" => DATA <= x"99"; when x"1F2" => DATA <= x"59"; when x"1F3" => DATA <= x"00"; when x"1F4" => DATA <= x"05"; when x"1F5" => DATA <= x"57"; when x"1F6" => DATA <= x"85"; when x"1F7" => DATA <= x"57"; when x"1F8" => DATA <= x"88"; when x"1F9" => DATA <= x"10"; when x"1FA" => DATA <= x"F4"; when x"1FB" => DATA <= x"AA"; when x"1FC" => DATA <= x"F0"; when x"1FD" => DATA <= x"09"; when x"1FE" => DATA <= x"A5"; when x"1FF" => DATA <= x"5A"; when x"200" => DATA <= x"85"; when x"201" => DATA <= x"57"; when x"202" => DATA <= x"09"; when x"203" => DATA <= x"80"; when x"204" => DATA <= x"85"; when x"205" => DATA <= x"5A"; when x"206" => DATA <= x"8A"; when x"207" => DATA <= x"60"; when x"208" => DATA <= x"84"; when x"209" => DATA <= x"03"; when x"20A" => DATA <= x"60"; when x"20B" => DATA <= x"20"; when x"20C" => DATA <= x"A5"; when x"20D" => DATA <= x"D5"; when x"20E" => DATA <= x"B0"; when x"20F" => DATA <= x"F8"; when x"210" => DATA <= x"A2"; when x"211" => DATA <= x"00"; when x"212" => DATA <= x"4C"; when x"213" => DATA <= x"12"; when x"214" => DATA <= x"D1"; when x"215" => DATA <= x"20"; when x"216" => DATA <= x"EB"; when x"217" => DATA <= x"D0"; when x"218" => DATA <= x"20"; when x"219" => DATA <= x"86"; when x"21A" => DATA <= x"D6"; when x"21B" => DATA <= x"30"; when x"21C" => DATA <= x"A7"; when x"21D" => DATA <= x"60"; when x"21E" => DATA <= x"20"; when x"21F" => DATA <= x"24"; when x"220" => DATA <= x"D2"; when x"221" => DATA <= x"4C"; when x"222" => DATA <= x"86"; when x"223" => DATA <= x"DC"; when x"224" => DATA <= x"20"; when x"225" => DATA <= x"EB"; when x"226" => DATA <= x"D0"; when x"227" => DATA <= x"20"; when x"228" => DATA <= x"86"; when x"229" => DATA <= x"D6"; when x"22A" => DATA <= x"10"; when x"22B" => DATA <= x"0A"; when x"22C" => DATA <= x"A9"; when x"22D" => DATA <= x"00"; when x"22E" => DATA <= x"85"; when x"22F" => DATA <= x"57"; when x"230" => DATA <= x"20"; when x"231" => DATA <= x"36"; when x"232" => DATA <= x"D2"; when x"233" => DATA <= x"4C"; when x"234" => DATA <= x"75"; when x"235" => DATA <= x"DC"; when x"236" => DATA <= x"20"; when x"237" => DATA <= x"2C"; when x"238" => DATA <= x"D8"; when x"239" => DATA <= x"20"; when x"23A" => DATA <= x"45"; when x"23B" => DATA <= x"DA"; when x"23C" => DATA <= x"20"; when x"23D" => DATA <= x"31"; when x"23E" => DATA <= x"D8"; when x"23F" => DATA <= x"20"; when x"240" => DATA <= x"8D"; when x"241" => DATA <= x"DE"; when x"242" => DATA <= x"20"; when x"243" => DATA <= x"33"; when x"244" => DATA <= x"D9"; when x"245" => DATA <= x"20"; when x"246" => DATA <= x"72"; when x"247" => DATA <= x"DB"; when x"248" => DATA <= x"20"; when x"249" => DATA <= x"86"; when x"24A" => DATA <= x"D6"; when x"24B" => DATA <= x"F0"; when x"24C" => DATA <= x"12"; when x"24D" => DATA <= x"20"; when x"24E" => DATA <= x"31"; when x"24F" => DATA <= x"D8"; when x"250" => DATA <= x"20"; when x"251" => DATA <= x"A6"; when x"252" => DATA <= x"DB"; when x"253" => DATA <= x"20"; when x"254" => DATA <= x"E5"; when x"255" => DATA <= x"D1"; when x"256" => DATA <= x"20"; when x"257" => DATA <= x"AA"; when x"258" => DATA <= x"DB"; when x"259" => DATA <= x"20"; when x"25A" => DATA <= x"DC"; when x"25B" => DATA <= x"DA"; when x"25C" => DATA <= x"4C"; when x"25D" => DATA <= x"67"; when x"25E" => DATA <= x"DC"; when x"25F" => DATA <= x"20"; when x"260" => DATA <= x"93"; when x"261" => DATA <= x"DD"; when x"262" => DATA <= x"4C"; when x"263" => DATA <= x"E5"; when x"264" => DATA <= x"D1"; when x"265" => DATA <= x"20"; when x"266" => DATA <= x"EB"; when x"267" => DATA <= x"D0"; when x"268" => DATA <= x"A0"; when x"269" => DATA <= x"7C"; when x"26A" => DATA <= x"A9"; when x"26B" => DATA <= x"D2"; when x"26C" => DATA <= x"84"; when x"26D" => DATA <= x"6F"; when x"26E" => DATA <= x"85"; when x"26F" => DATA <= x"70"; when x"270" => DATA <= x"4C"; when x"271" => DATA <= x"45"; when x"272" => DATA <= x"DA"; when x"273" => DATA <= x"20"; when x"274" => DATA <= x"EB"; when x"275" => DATA <= x"D0"; when x"276" => DATA <= x"A0"; when x"277" => DATA <= x"81"; when x"278" => DATA <= x"A9"; when x"279" => DATA <= x"D2"; when x"27A" => DATA <= x"D0"; when x"27B" => DATA <= x"F0"; when x"27C" => DATA <= x"7B"; when x"27D" => DATA <= x"0E"; when x"27E" => DATA <= x"FA"; when x"27F" => DATA <= x"35"; when x"280" => DATA <= x"12"; when x"281" => DATA <= x"86"; when x"282" => DATA <= x"65"; when x"283" => DATA <= x"2E"; when x"284" => DATA <= x"E0"; when x"285" => DATA <= x"D3"; when x"286" => DATA <= x"20"; when x"287" => DATA <= x"EB"; when x"288" => DATA <= x"D0"; when x"289" => DATA <= x"20"; when x"28A" => DATA <= x"86"; when x"28B" => DATA <= x"D6"; when x"28C" => DATA <= x"F0"; when x"28D" => DATA <= x"07"; when x"28E" => DATA <= x"48"; when x"28F" => DATA <= x"20"; when x"290" => DATA <= x"8D"; when x"291" => DATA <= x"DE"; when x"292" => DATA <= x"68"; when x"293" => DATA <= x"85"; when x"294" => DATA <= x"57"; when x"295" => DATA <= x"60"; when x"296" => DATA <= x"24"; when x"297" => DATA <= x"73"; when x"298" => DATA <= x"30"; when x"299" => DATA <= x"26"; when x"29A" => DATA <= x"20"; when x"29B" => DATA <= x"BC"; when x"29C" => DATA <= x"C8"; when x"29D" => DATA <= x"A0"; when x"29E" => DATA <= x"5D"; when x"29F" => DATA <= x"20"; when x"2A0" => DATA <= x"CD"; when x"2A1" => DATA <= x"C3"; when x"2A2" => DATA <= x"85"; when x"2A3" => DATA <= x"5A"; when x"2A4" => DATA <= x"A5"; when x"2A5" => DATA <= x"5F"; when x"2A6" => DATA <= x"85"; when x"2A7" => DATA <= x"5B"; when x"2A8" => DATA <= x"A5"; when x"2A9" => DATA <= x"5E"; when x"2AA" => DATA <= x"85"; when x"2AB" => DATA <= x"5C"; when x"2AC" => DATA <= x"A9"; when x"2AD" => DATA <= x"A0"; when x"2AE" => DATA <= x"85"; when x"2AF" => DATA <= x"59"; when x"2B0" => DATA <= x"A0"; when x"2B1" => DATA <= x"00"; when x"2B2" => DATA <= x"84"; when x"2B3" => DATA <= x"5E"; when x"2B4" => DATA <= x"A5"; when x"2B5" => DATA <= x"5A"; when x"2B6" => DATA <= x"85"; when x"2B7" => DATA <= x"57"; when x"2B8" => DATA <= x"10"; when x"2B9" => DATA <= x"03"; when x"2BA" => DATA <= x"20"; when x"2BB" => DATA <= x"D5"; when x"2BC" => DATA <= x"D8"; when x"2BD" => DATA <= x"4C"; when x"2BE" => DATA <= x"C8"; when x"2BF" => DATA <= x"D7"; when x"2C0" => DATA <= x"4C"; when x"2C1" => DATA <= x"1B"; when x"2C2" => DATA <= x"CA"; when x"2C3" => DATA <= x"20"; when x"2C4" => DATA <= x"93"; when x"2C5" => DATA <= x"DD"; when x"2C6" => DATA <= x"20"; when x"2C7" => DATA <= x"E5"; when x"2C8" => DATA <= x"D1"; when x"2C9" => DATA <= x"E6"; when x"2CA" => DATA <= x"59"; when x"2CB" => DATA <= x"60"; when x"2CC" => DATA <= x"20"; when x"2CD" => DATA <= x"3E"; when x"2CE" => DATA <= x"CF"; when x"2CF" => DATA <= x"A2"; when x"2D0" => DATA <= x"04"; when x"2D1" => DATA <= x"20"; when x"2D2" => DATA <= x"D4"; when x"2D3" => DATA <= x"FF"; when x"2D4" => DATA <= x"9D"; when x"2D5" => DATA <= x"C5"; when x"2D6" => DATA <= x"03"; when x"2D7" => DATA <= x"CA"; when x"2D8" => DATA <= x"10"; when x"2D9" => DATA <= x"F7"; when x"2DA" => DATA <= x"20"; when x"2DB" => DATA <= x"AA"; when x"2DC" => DATA <= x"DB"; when x"2DD" => DATA <= x"4C"; when x"2DE" => DATA <= x"E5"; when x"2DF" => DATA <= x"D1"; when x"2E0" => DATA <= x"20"; when x"2E1" => DATA <= x"B1"; when x"2E2" => DATA <= x"CE"; when x"2E3" => DATA <= x"A0"; when x"2E4" => DATA <= x"00"; when x"2E5" => DATA <= x"20"; when x"2E6" => DATA <= x"04"; when x"2E7" => DATA <= x"D3"; when x"2E8" => DATA <= x"C9"; when x"2E9" => DATA <= x"2B"; when x"2EA" => DATA <= x"F0"; when x"2EB" => DATA <= x"0F"; when x"2EC" => DATA <= x"C9"; when x"2ED" => DATA <= x"2D"; when x"2EE" => DATA <= x"D0"; when x"2EF" => DATA <= x"0E"; when x"2F0" => DATA <= x"20"; when x"2F1" => DATA <= x"03"; when x"2F2" => DATA <= x"D3"; when x"2F3" => DATA <= x"84"; when x"2F4" => DATA <= x"54"; when x"2F5" => DATA <= x"20"; when x"2F6" => DATA <= x"B1"; when x"2F7" => DATA <= x"D5"; when x"2F8" => DATA <= x"4C"; when x"2F9" => DATA <= x"BF"; when x"2FA" => DATA <= x"D1"; when x"2FB" => DATA <= x"20"; when x"2FC" => DATA <= x"03"; when x"2FD" => DATA <= x"D3"; when x"2FE" => DATA <= x"84"; when x"2FF" => DATA <= x"54"; when x"300" => DATA <= x"4C"; when x"301" => DATA <= x"B1"; when x"302" => DATA <= x"D5"; when x"303" => DATA <= x"C8"; when x"304" => DATA <= x"B1"; when x"305" => DATA <= x"52"; when x"306" => DATA <= x"C9"; when x"307" => DATA <= x"20"; when x"308" => DATA <= x"F0"; when x"309" => DATA <= x"F9"; when x"30A" => DATA <= x"60"; when x"30B" => DATA <= x"20"; when x"30C" => DATA <= x"44"; when x"30D" => DATA <= x"D4"; when x"30E" => DATA <= x"90"; when x"30F" => DATA <= x"D4"; when x"310" => DATA <= x"20"; when x"311" => DATA <= x"79"; when x"312" => DATA <= x"C2"; when x"313" => DATA <= x"20"; when x"314" => DATA <= x"FC"; when x"315" => DATA <= x"D0"; when x"316" => DATA <= x"20"; when x"317" => DATA <= x"E4"; when x"318" => DATA <= x"C4"; when x"319" => DATA <= x"20"; when x"31A" => DATA <= x"36"; when x"31B" => DATA <= x"D8"; when x"31C" => DATA <= x"4C"; when x"31D" => DATA <= x"5B"; when x"31E" => DATA <= x"C5"; when x"31F" => DATA <= x"20"; when x"320" => DATA <= x"FC"; when x"321" => DATA <= x"D0"; when x"322" => DATA <= x"20"; when x"323" => DATA <= x"31"; when x"324" => DATA <= x"C2"; when x"325" => DATA <= x"20"; when x"326" => DATA <= x"E1"; when x"327" => DATA <= x"C4"; when x"328" => DATA <= x"20"; when x"329" => DATA <= x"CB"; when x"32A" => DATA <= x"C3"; when x"32B" => DATA <= x"20"; when x"32C" => DATA <= x"D0"; when x"32D" => DATA <= x"D4"; when x"32E" => DATA <= x"4C"; when x"32F" => DATA <= x"5B"; when x"330" => DATA <= x"C5"; when x"331" => DATA <= x"20"; when x"332" => DATA <= x"72"; when x"333" => DATA <= x"C3"; when x"334" => DATA <= x"A2"; when x"335" => DATA <= x"B8"; when x"336" => DATA <= x"4C"; when x"337" => DATA <= x"0B"; when x"338" => DATA <= x"D1"; when x"339" => DATA <= x"20"; when x"33A" => DATA <= x"FC"; when x"33B" => DATA <= x"D0"; when x"33C" => DATA <= x"A9"; when x"33D" => DATA <= x"C5"; when x"33E" => DATA <= x"85"; when x"33F" => DATA <= x"52"; when x"340" => DATA <= x"A9"; when x"341" => DATA <= x"03"; when x"342" => DATA <= x"85"; when x"343" => DATA <= x"53"; when x"344" => DATA <= x"20"; when x"345" => DATA <= x"D0"; when x"346" => DATA <= x"D4"; when x"347" => DATA <= x"C6"; when x"348" => DATA <= x"6F"; when x"349" => DATA <= x"AD"; when x"34A" => DATA <= x"21"; when x"34B" => DATA <= x"03"; when x"34C" => DATA <= x"38"; when x"34D" => DATA <= x"E5"; when x"34E" => DATA <= x"6F"; when x"34F" => DATA <= x"90"; when x"350" => DATA <= x"0B"; when x"351" => DATA <= x"F0"; when x"352" => DATA <= x"09"; when x"353" => DATA <= x"A8"; when x"354" => DATA <= x"A9"; when x"355" => DATA <= x"20"; when x"356" => DATA <= x"20"; when x"357" => DATA <= x"4C"; when x"358" => DATA <= x"CA"; when x"359" => DATA <= x"88"; when x"35A" => DATA <= x"D0"; when x"35B" => DATA <= x"FA"; when x"35C" => DATA <= x"A0"; when x"35D" => DATA <= x"00"; when x"35E" => DATA <= x"B1"; when x"35F" => DATA <= x"52"; when x"360" => DATA <= x"C9"; when x"361" => DATA <= x"0D"; when x"362" => DATA <= x"F0"; when x"363" => DATA <= x"CD"; when x"364" => DATA <= x"20"; when x"365" => DATA <= x"4C"; when x"366" => DATA <= x"CA"; when x"367" => DATA <= x"C8"; when x"368" => DATA <= x"D0"; when x"369" => DATA <= x"F4"; when x"36A" => DATA <= x"20"; when x"36B" => DATA <= x"72"; when x"36C" => DATA <= x"C3"; when x"36D" => DATA <= x"B1"; when x"36E" => DATA <= x"05"; when x"36F" => DATA <= x"C9"; when x"370" => DATA <= x"25"; when x"371" => DATA <= x"D0"; when x"372" => DATA <= x"08"; when x"373" => DATA <= x"C8"; when x"374" => DATA <= x"84"; when x"375" => DATA <= x"03"; when x"376" => DATA <= x"20"; when x"377" => DATA <= x"44"; when x"378" => DATA <= x"D4"; when x"379" => DATA <= x"B0"; when x"37A" => DATA <= x"05"; when x"37B" => DATA <= x"A2"; when x"37C" => DATA <= x"C3"; when x"37D" => DATA <= x"4C"; when x"37E" => DATA <= x"0B"; when x"37F" => DATA <= x"D1"; when x"380" => DATA <= x"20"; when x"381" => DATA <= x"09"; when x"382" => DATA <= x"CD"; when x"383" => DATA <= x"A8"; when x"384" => DATA <= x"A5"; when x"385" => DATA <= x"05"; when x"386" => DATA <= x"48"; when x"387" => DATA <= x"A5"; when x"388" => DATA <= x"06"; when x"389" => DATA <= x"48"; when x"38A" => DATA <= x"A5"; when x"38B" => DATA <= x"03"; when x"38C" => DATA <= x"48"; when x"38D" => DATA <= x"84"; when x"38E" => DATA <= x"03"; when x"38F" => DATA <= x"C8"; when x"390" => DATA <= x"84"; when x"391" => DATA <= x"06"; when x"392" => DATA <= x"A9"; when x"393" => DATA <= x"40"; when x"394" => DATA <= x"85"; when x"395" => DATA <= x"05"; when x"396" => DATA <= x"20"; when x"397" => DATA <= x"FC"; when x"398" => DATA <= x"D0"; when x"399" => DATA <= x"68"; when x"39A" => DATA <= x"85"; when x"39B" => DATA <= x"03"; when x"39C" => DATA <= x"68"; when x"39D" => DATA <= x"85"; when x"39E" => DATA <= x"06"; when x"39F" => DATA <= x"68"; when x"3A0" => DATA <= x"85"; when x"3A1" => DATA <= x"05"; when x"3A2" => DATA <= x"20"; when x"3A3" => DATA <= x"36"; when x"3A4" => DATA <= x"D8"; when x"3A5" => DATA <= x"4C"; when x"3A6" => DATA <= x"7B"; when x"3A7" => DATA <= x"D3"; when x"3A8" => DATA <= x"20"; when x"3A9" => DATA <= x"EB"; when x"3AA" => DATA <= x"D9"; when x"3AB" => DATA <= x"4C"; when x"3AC" => DATA <= x"69"; when x"3AD" => DATA <= x"C5"; when x"3AE" => DATA <= x"20"; when x"3AF" => DATA <= x"EB"; when x"3B0" => DATA <= x"D9"; when x"3B1" => DATA <= x"4C"; when x"3B2" => DATA <= x"D5"; when x"3B3" => DATA <= x"CC"; when x"3B4" => DATA <= x"20"; when x"3B5" => DATA <= x"94"; when x"3B6" => DATA <= x"D4"; when x"3B7" => DATA <= x"20"; when x"3B8" => DATA <= x"FC"; when x"3B9" => DATA <= x"D0"; when x"3BA" => DATA <= x"20"; when x"3BB" => DATA <= x"E4"; when x"3BC" => DATA <= x"C4"; when x"3BD" => DATA <= x"20"; when x"3BE" => DATA <= x"31"; when x"3BF" => DATA <= x"D8"; when x"3C0" => DATA <= x"A6"; when x"3C1" => DATA <= x"04"; when x"3C2" => DATA <= x"20"; when x"3C3" => DATA <= x"41"; when x"3C4" => DATA <= x"CF"; when x"3C5" => DATA <= x"A2"; when x"3C6" => DATA <= x"04"; when x"3C7" => DATA <= x"BD"; when x"3C8" => DATA <= x"C5"; when x"3C9" => DATA <= x"03"; when x"3CA" => DATA <= x"20"; when x"3CB" => DATA <= x"D1"; when x"3CC" => DATA <= x"FF"; when x"3CD" => DATA <= x"CA"; when x"3CE" => DATA <= x"10"; when x"3CF" => DATA <= x"F7"; when x"3D0" => DATA <= x"4C"; when x"3D1" => DATA <= x"5B"; when x"3D2" => DATA <= x"C5"; when x"3D3" => DATA <= x"A5"; when x"3D4" => DATA <= x"01"; when x"3D5" => DATA <= x"05"; when x"3D6" => DATA <= x"02"; when x"3D7" => DATA <= x"F0"; when x"3D8" => DATA <= x"6A"; when x"3D9" => DATA <= x"20"; when x"3DA" => DATA <= x"34"; when x"3DB" => DATA <= x"C4"; when x"3DC" => DATA <= x"B0"; when x"3DD" => DATA <= x"65"; when x"3DE" => DATA <= x"A4"; when x"3DF" => DATA <= x"03"; when x"3E0" => DATA <= x"B1"; when x"3E1" => DATA <= x"05"; when x"3E2" => DATA <= x"C9"; when x"3E3" => DATA <= x"25"; when x"3E4" => DATA <= x"D0"; when x"3E5" => DATA <= x"5D"; when x"3E6" => DATA <= x"C8"; when x"3E7" => DATA <= x"B1"; when x"3E8" => DATA <= x"05"; when x"3E9" => DATA <= x"C8"; when x"3EA" => DATA <= x"D1"; when x"3EB" => DATA <= x"05"; when x"3EC" => DATA <= x"D0"; when x"3ED" => DATA <= x"55"; when x"3EE" => DATA <= x"C9"; when x"3EF" => DATA <= x"5B"; when x"3F0" => DATA <= x"B0"; when x"3F1" => DATA <= x"51"; when x"3F2" => DATA <= x"E9"; when x"3F3" => DATA <= x"3F"; when x"3F4" => DATA <= x"90"; when x"3F5" => DATA <= x"4D"; when x"3F6" => DATA <= x"C8"; when x"3F7" => DATA <= x"84"; when x"3F8" => DATA <= x"03"; when x"3F9" => DATA <= x"48"; when x"3FA" => DATA <= x"20"; when x"3FB" => DATA <= x"8B"; when x"3FC" => DATA <= x"C7"; when x"3FD" => DATA <= x"F6"; when x"3FE" => DATA <= x"15"; when x"3FF" => DATA <= x"D0"; when x"400" => DATA <= x"02"; when x"401" => DATA <= x"F6"; when x"402" => DATA <= x"24"; when x"403" => DATA <= x"20"; when x"404" => DATA <= x"9A"; when x"405" => DATA <= x"D4"; when x"406" => DATA <= x"68"; when x"407" => DATA <= x"A8"; when x"408" => DATA <= x"18"; when x"409" => DATA <= x"A5"; when x"40A" => DATA <= x"23"; when x"40B" => DATA <= x"99"; when x"40C" => DATA <= x"87"; when x"40D" => DATA <= x"28"; when x"40E" => DATA <= x"65"; when x"40F" => DATA <= x"16"; when x"410" => DATA <= x"85"; when x"411" => DATA <= x"23"; when x"412" => DATA <= x"A5"; when x"413" => DATA <= x"24"; when x"414" => DATA <= x"99"; when x"415" => DATA <= x"A2"; when x"416" => DATA <= x"28"; when x"417" => DATA <= x"65"; when x"418" => DATA <= x"25"; when x"419" => DATA <= x"85"; when x"41A" => DATA <= x"24"; when x"41B" => DATA <= x"A0"; when x"41C" => DATA <= x"00"; when x"41D" => DATA <= x"84"; when x"41E" => DATA <= x"04"; when x"41F" => DATA <= x"A9"; when x"420" => DATA <= x"AA"; when x"421" => DATA <= x"91"; when x"422" => DATA <= x"23"; when x"423" => DATA <= x"D1"; when x"424" => DATA <= x"23"; when x"425" => DATA <= x"D0"; when x"426" => DATA <= x"1C"; when x"427" => DATA <= x"4A"; when x"428" => DATA <= x"91"; when x"429" => DATA <= x"23"; when x"42A" => DATA <= x"D1"; when x"42B" => DATA <= x"23"; when x"42C" => DATA <= x"D0"; when x"42D" => DATA <= x"15"; when x"42E" => DATA <= x"20"; when x"42F" => DATA <= x"34"; when x"430" => DATA <= x"C4"; when x"431" => DATA <= x"B0"; when x"432" => DATA <= x"10"; when x"433" => DATA <= x"A4"; when x"434" => DATA <= x"03"; when x"435" => DATA <= x"B1"; when x"436" => DATA <= x"05"; when x"437" => DATA <= x"C9"; when x"438" => DATA <= x"2C"; when x"439" => DATA <= x"D0"; when x"43A" => DATA <= x"05"; when x"43B" => DATA <= x"E6"; when x"43C" => DATA <= x"03"; when x"43D" => DATA <= x"4C"; when x"43E" => DATA <= x"D3"; when x"43F" => DATA <= x"D3"; when x"440" => DATA <= x"4C"; when x"441" => DATA <= x"58"; when x"442" => DATA <= x"C5"; when x"443" => DATA <= x"00"; when x"444" => DATA <= x"20"; when x"445" => DATA <= x"34"; when x"446" => DATA <= x"C4"; when x"447" => DATA <= x"90"; when x"448" => DATA <= x"0E"; when x"449" => DATA <= x"B5"; when x"44A" => DATA <= x"15"; when x"44B" => DATA <= x"0A"; when x"44C" => DATA <= x"0A"; when x"44D" => DATA <= x"75"; when x"44E" => DATA <= x"15"; when x"44F" => DATA <= x"95"; when x"450" => DATA <= x"15"; when x"451" => DATA <= x"A9"; when x"452" => DATA <= x"28"; when x"453" => DATA <= x"95"; when x"454" => DATA <= x"24"; when x"455" => DATA <= x"38"; when x"456" => DATA <= x"60"; when x"457" => DATA <= x"A4"; when x"458" => DATA <= x"03"; when x"459" => DATA <= x"B1"; when x"45A" => DATA <= x"05"; when x"45B" => DATA <= x"C9"; when x"45C" => DATA <= x"21"; when x"45D" => DATA <= x"D0"; when x"45E" => DATA <= x"07"; when x"45F" => DATA <= x"E6"; when x"460" => DATA <= x"03"; when x"461" => DATA <= x"20"; when x"462" => DATA <= x"BC"; when x"463" => DATA <= x"C8"; when x"464" => DATA <= x"38"; when x"465" => DATA <= x"60"; when x"466" => DATA <= x"C8"; when x"467" => DATA <= x"D1"; when x"468" => DATA <= x"05"; when x"469" => DATA <= x"D0"; when x"46A" => DATA <= x"08"; when x"46B" => DATA <= x"C9"; when x"46C" => DATA <= x"5B"; when x"46D" => DATA <= x"B0"; when x"46E" => DATA <= x"04"; when x"46F" => DATA <= x"E9"; when x"470" => DATA <= x"3F"; when x"471" => DATA <= x"B0"; when x"472" => DATA <= x"02"; when x"473" => DATA <= x"18"; when x"474" => DATA <= x"60"; when x"475" => DATA <= x"C8"; when x"476" => DATA <= x"84"; when x"477" => DATA <= x"03"; when x"478" => DATA <= x"48"; when x"479" => DATA <= x"20"; when x"47A" => DATA <= x"BC"; when x"47B" => DATA <= x"C8"; when x"47C" => DATA <= x"20"; when x"47D" => DATA <= x"9A"; when x"47E" => DATA <= x"D4"; when x"47F" => DATA <= x"68"; when x"480" => DATA <= x"A8"; when x"481" => DATA <= x"B0"; when x"482" => DATA <= x"10"; when x"483" => DATA <= x"B9"; when x"484" => DATA <= x"87"; when x"485" => DATA <= x"28"; when x"486" => DATA <= x"75"; when x"487" => DATA <= x"15"; when x"488" => DATA <= x"95"; when x"489" => DATA <= x"15"; when x"48A" => DATA <= x"B9"; when x"48B" => DATA <= x"A2"; when x"48C" => DATA <= x"28"; when x"48D" => DATA <= x"75"; when x"48E" => DATA <= x"24"; when x"48F" => DATA <= x"95"; when x"490" => DATA <= x"24"; when x"491" => DATA <= x"90"; when x"492" => DATA <= x"D1"; when x"493" => DATA <= x"00"; when x"494" => DATA <= x"20"; when x"495" => DATA <= x"BC"; when x"496" => DATA <= x"C8"; when x"497" => DATA <= x"4C"; when x"498" => DATA <= x"31"; when x"499" => DATA <= x"C2"; when x"49A" => DATA <= x"B4"; when x"49B" => DATA <= x"24"; when x"49C" => DATA <= x"B5"; when x"49D" => DATA <= x"15"; when x"49E" => DATA <= x"0A"; when x"49F" => DATA <= x"36"; when x"4A0" => DATA <= x"24"; when x"4A1" => DATA <= x"0A"; when x"4A2" => DATA <= x"36"; when x"4A3" => DATA <= x"24"; when x"4A4" => DATA <= x"18"; when x"4A5" => DATA <= x"75"; when x"4A6" => DATA <= x"15"; when x"4A7" => DATA <= x"95"; when x"4A8" => DATA <= x"15"; when x"4A9" => DATA <= x"98"; when x"4AA" => DATA <= x"75"; when x"4AB" => DATA <= x"24"; when x"4AC" => DATA <= x"95"; when x"4AD" => DATA <= x"24"; when x"4AE" => DATA <= x"60"; when x"4AF" => DATA <= x"AD"; when x"4B0" => DATA <= x"04"; when x"4B1" => DATA <= x"E0"; when x"4B2" => DATA <= x"C9"; when x"4B3" => DATA <= x"BF"; when x"4B4" => DATA <= x"F0"; when x"4B5" => DATA <= x"0A"; when x"4B6" => DATA <= x"AD"; when x"4B7" => DATA <= x"00"; when x"4B8" => DATA <= x"A0"; when x"4B9" => DATA <= x"C9"; when x"4BA" => DATA <= x"40"; when x"4BB" => DATA <= x"D0"; when x"4BC" => DATA <= x"83"; when x"4BD" => DATA <= x"4C"; when x"4BE" => DATA <= x"02"; when x"4BF" => DATA <= x"A0"; when x"4C0" => DATA <= x"4C"; when x"4C1" => DATA <= x"05"; when x"4C2" => DATA <= x"E0"; when x"4C3" => DATA <= x"C9"; when x"4C4" => DATA <= x"3A"; when x"4C5" => DATA <= x"B0"; when x"4C6" => DATA <= x"07"; when x"4C7" => DATA <= x"C9"; when x"4C8" => DATA <= x"30"; when x"4C9" => DATA <= x"90"; when x"4CA" => DATA <= x"02"; when x"4CB" => DATA <= x"E9"; when x"4CC" => DATA <= x"30"; when x"4CD" => DATA <= x"60"; when x"4CE" => DATA <= x"18"; when x"4CF" => DATA <= x"60"; when x"4D0" => DATA <= x"A9"; when x"4D1" => DATA <= x"00"; when x"4D2" => DATA <= x"85"; when x"4D3" => DATA <= x"6F"; when x"4D4" => DATA <= x"20"; when x"4D5" => DATA <= x"86"; when x"4D6" => DATA <= x"D6"; when x"4D7" => DATA <= x"D0"; when x"4D8" => DATA <= x"12"; when x"4D9" => DATA <= x"A9"; when x"4DA" => DATA <= x"30"; when x"4DB" => DATA <= x"20"; when x"4DC" => DATA <= x"8D"; when x"4DD" => DATA <= x"D5"; when x"4DE" => DATA <= x"A9"; when x"4DF" => DATA <= x"2E"; when x"4E0" => DATA <= x"20"; when x"4E1" => DATA <= x"8D"; when x"4E2" => DATA <= x"D5"; when x"4E3" => DATA <= x"A9"; when x"4E4" => DATA <= x"30"; when x"4E5" => DATA <= x"20"; when x"4E6" => DATA <= x"8D"; when x"4E7" => DATA <= x"D5"; when x"4E8" => DATA <= x"4C"; when x"4E9" => DATA <= x"71"; when x"4EA" => DATA <= x"D5"; when x"4EB" => DATA <= x"10"; when x"4EC" => DATA <= x"05"; when x"4ED" => DATA <= x"A9"; when x"4EE" => DATA <= x"2D"; when x"4EF" => DATA <= x"20"; when x"4F0" => DATA <= x"8D"; when x"4F1" => DATA <= x"D5"; when x"4F2" => DATA <= x"A9"; when x"4F3" => DATA <= x"00"; when x"4F4" => DATA <= x"85"; when x"4F5" => DATA <= x"6D"; when x"4F6" => DATA <= x"A5"; when x"4F7" => DATA <= x"59"; when x"4F8" => DATA <= x"C9"; when x"4F9" => DATA <= x"81"; when x"4FA" => DATA <= x"B0"; when x"4FB" => DATA <= x"08"; when x"4FC" => DATA <= x"20"; when x"4FD" => DATA <= x"A0"; when x"4FE" => DATA <= x"D6"; when x"4FF" => DATA <= x"C6"; when x"500" => DATA <= x"6D"; when x"501" => DATA <= x"4C"; when x"502" => DATA <= x"F6"; when x"503" => DATA <= x"D4"; when x"504" => DATA <= x"C9"; when x"505" => DATA <= x"84"; when x"506" => DATA <= x"90"; when x"507" => DATA <= x"10"; when x"508" => DATA <= x"D0"; when x"509" => DATA <= x"06"; when x"50A" => DATA <= x"A5"; when x"50B" => DATA <= x"5A"; when x"50C" => DATA <= x"C9"; when x"50D" => DATA <= x"A0"; when x"50E" => DATA <= x"90"; when x"50F" => DATA <= x"08"; when x"510" => DATA <= x"20"; when x"511" => DATA <= x"1B"; when x"512" => DATA <= x"D7"; when x"513" => DATA <= x"E6"; when x"514" => DATA <= x"6D"; when x"515" => DATA <= x"4C"; when x"516" => DATA <= x"F6"; when x"517" => DATA <= x"D4"; when x"518" => DATA <= x"A5"; when x"519" => DATA <= x"59"; when x"51A" => DATA <= x"C9"; when x"51B" => DATA <= x"84"; when x"51C" => DATA <= x"B0"; when x"51D" => DATA <= x"07"; when x"51E" => DATA <= x"20"; when x"51F" => DATA <= x"D8"; when x"520" => DATA <= x"D6"; when x"521" => DATA <= x"E6"; when x"522" => DATA <= x"59"; when x"523" => DATA <= x"D0"; when x"524" => DATA <= x"F3"; when x"525" => DATA <= x"38"; when x"526" => DATA <= x"A9"; when x"527" => DATA <= x"FF"; when x"528" => DATA <= x"20"; when x"529" => DATA <= x"36"; when x"52A" => DATA <= x"D6"; when x"52B" => DATA <= x"A5"; when x"52C" => DATA <= x"5A"; when x"52D" => DATA <= x"C9"; when x"52E" => DATA <= x"A0"; when x"52F" => DATA <= x"B0"; when x"530" => DATA <= x"DF"; when x"531" => DATA <= x"A9"; when x"532" => DATA <= x"01"; when x"533" => DATA <= x"A4"; when x"534" => DATA <= x"6D"; when x"535" => DATA <= x"30"; when x"536" => DATA <= x"0A"; when x"537" => DATA <= x"C0"; when x"538" => DATA <= x"08"; when x"539" => DATA <= x"B0"; when x"53A" => DATA <= x"06"; when x"53B" => DATA <= x"C8"; when x"53C" => DATA <= x"A9"; when x"53D" => DATA <= x"00"; when x"53E" => DATA <= x"85"; when x"53F" => DATA <= x"6D"; when x"540" => DATA <= x"98"; when x"541" => DATA <= x"85"; when x"542" => DATA <= x"70"; when x"543" => DATA <= x"A2"; when x"544" => DATA <= x"09"; when x"545" => DATA <= x"86"; when x"546" => DATA <= x"54"; when x"547" => DATA <= x"20"; when x"548" => DATA <= x"75"; when x"549" => DATA <= x"D5"; when x"54A" => DATA <= x"C6"; when x"54B" => DATA <= x"70"; when x"54C" => DATA <= x"D0"; when x"54D" => DATA <= x"05"; when x"54E" => DATA <= x"A9"; when x"54F" => DATA <= x"2E"; when x"550" => DATA <= x"20"; when x"551" => DATA <= x"8D"; when x"552" => DATA <= x"D5"; when x"553" => DATA <= x"C6"; when x"554" => DATA <= x"54"; when x"555" => DATA <= x"D0"; when x"556" => DATA <= x"F0"; when x"557" => DATA <= x"A5"; when x"558" => DATA <= x"6D"; when x"559" => DATA <= x"F0"; when x"55A" => DATA <= x"16"; when x"55B" => DATA <= x"A9"; when x"55C" => DATA <= x"45"; when x"55D" => DATA <= x"20"; when x"55E" => DATA <= x"8D"; when x"55F" => DATA <= x"D5"; when x"560" => DATA <= x"A5"; when x"561" => DATA <= x"6D"; when x"562" => DATA <= x"10"; when x"563" => DATA <= x"0A"; when x"564" => DATA <= x"A9"; when x"565" => DATA <= x"2D"; when x"566" => DATA <= x"20"; when x"567" => DATA <= x"8D"; when x"568" => DATA <= x"D5"; when x"569" => DATA <= x"38"; when x"56A" => DATA <= x"A9"; when x"56B" => DATA <= x"00"; when x"56C" => DATA <= x"E5"; when x"56D" => DATA <= x"6D"; when x"56E" => DATA <= x"20"; when x"56F" => DATA <= x"87"; when x"570" => DATA <= x"D5"; when x"571" => DATA <= x"A9"; when x"572" => DATA <= x"0D"; when x"573" => DATA <= x"D0"; when x"574" => DATA <= x"18"; when x"575" => DATA <= x"A5"; when x"576" => DATA <= x"5A"; when x"577" => DATA <= x"4A"; when x"578" => DATA <= x"4A"; when x"579" => DATA <= x"4A"; when x"57A" => DATA <= x"4A"; when x"57B" => DATA <= x"20"; when x"57C" => DATA <= x"8B"; when x"57D" => DATA <= x"D5"; when x"57E" => DATA <= x"A5"; when x"57F" => DATA <= x"5A"; when x"580" => DATA <= x"29"; when x"581" => DATA <= x"0F"; when x"582" => DATA <= x"85"; when x"583" => DATA <= x"5A"; when x"584" => DATA <= x"4C"; when x"585" => DATA <= x"4E"; when x"586" => DATA <= x"D6"; when x"587" => DATA <= x"C9"; when x"588" => DATA <= x"0A"; when x"589" => DATA <= x"B0"; when x"58A" => DATA <= x"09"; when x"58B" => DATA <= x"09"; when x"58C" => DATA <= x"30"; when x"58D" => DATA <= x"A4"; when x"58E" => DATA <= x"6F"; when x"58F" => DATA <= x"91"; when x"590" => DATA <= x"52"; when x"591" => DATA <= x"E6"; when x"592" => DATA <= x"6F"; when x"593" => DATA <= x"60"; when x"594" => DATA <= x"A2"; when x"595" => DATA <= x"FF"; when x"596" => DATA <= x"E8"; when x"597" => DATA <= x"E9"; when x"598" => DATA <= x"0A"; when x"599" => DATA <= x"B0"; when x"59A" => DATA <= x"FB"; when x"59B" => DATA <= x"69"; when x"59C" => DATA <= x"0A"; when x"59D" => DATA <= x"48"; when x"59E" => DATA <= x"8A"; when x"59F" => DATA <= x"20"; when x"5A0" => DATA <= x"87"; when x"5A1" => DATA <= x"D5"; when x"5A2" => DATA <= x"68"; when x"5A3" => DATA <= x"10"; when x"5A4" => DATA <= x"E6"; when x"5A5" => DATA <= x"A5"; when x"5A6" => DATA <= x"03"; when x"5A7" => DATA <= x"85"; when x"5A8" => DATA <= x"54"; when x"5A9" => DATA <= x"A5"; when x"5AA" => DATA <= x"05"; when x"5AB" => DATA <= x"85"; when x"5AC" => DATA <= x"52"; when x"5AD" => DATA <= x"A5"; when x"5AE" => DATA <= x"06"; when x"5AF" => DATA <= x"85"; when x"5B0" => DATA <= x"53"; when x"5B1" => DATA <= x"20"; when x"5B2" => DATA <= x"A4"; when x"5B3" => DATA <= x"DA"; when x"5B4" => DATA <= x"85"; when x"5B5" => DATA <= x"6C"; when x"5B6" => DATA <= x"85"; when x"5B7" => DATA <= x"6D"; when x"5B8" => DATA <= x"20"; when x"5B9" => DATA <= x"7B"; when x"5BA" => DATA <= x"D6"; when x"5BB" => DATA <= x"C9"; when x"5BC" => DATA <= x"2E"; when x"5BD" => DATA <= x"F0"; when x"5BE" => DATA <= x"0E"; when x"5BF" => DATA <= x"20"; when x"5C0" => DATA <= x"C3"; when x"5C1" => DATA <= x"D4"; when x"5C2" => DATA <= x"90"; when x"5C3" => DATA <= x"71"; when x"5C4" => DATA <= x"85"; when x"5C5" => DATA <= x"5E"; when x"5C6" => DATA <= x"20"; when x"5C7" => DATA <= x"7B"; when x"5C8" => DATA <= x"D6"; when x"5C9" => DATA <= x"C9"; when x"5CA" => DATA <= x"2E"; when x"5CB" => DATA <= x"D0"; when x"5CC" => DATA <= x"09"; when x"5CD" => DATA <= x"A5"; when x"5CE" => DATA <= x"6C"; when x"5CF" => DATA <= x"18"; when x"5D0" => DATA <= x"D0"; when x"5D1" => DATA <= x"3A"; when x"5D2" => DATA <= x"E6"; when x"5D3" => DATA <= x"6C"; when x"5D4" => DATA <= x"D0"; when x"5D5" => DATA <= x"F0"; when x"5D6" => DATA <= x"C9"; when x"5D7" => DATA <= x"45"; when x"5D8" => DATA <= x"F0"; when x"5D9" => DATA <= x"27"; when x"5DA" => DATA <= x"20"; when x"5DB" => DATA <= x"C3"; when x"5DC" => DATA <= x"D4"; when x"5DD" => DATA <= x"90"; when x"5DE" => DATA <= x"2D"; when x"5DF" => DATA <= x"85"; when x"5E0" => DATA <= x"6E"; when x"5E1" => DATA <= x"A5"; when x"5E2" => DATA <= x"5A"; when x"5E3" => DATA <= x"C9"; when x"5E4" => DATA <= x"18"; when x"5E5" => DATA <= x"90"; when x"5E6" => DATA <= x"08"; when x"5E7" => DATA <= x"A5"; when x"5E8" => DATA <= x"6C"; when x"5E9" => DATA <= x"D0"; when x"5EA" => DATA <= x"DB"; when x"5EB" => DATA <= x"E6"; when x"5EC" => DATA <= x"6D"; when x"5ED" => DATA <= x"B0"; when x"5EE" => DATA <= x"D7"; when x"5EF" => DATA <= x"A5"; when x"5F0" => DATA <= x"6C"; when x"5F1" => DATA <= x"F0"; when x"5F2" => DATA <= x"02"; when x"5F3" => DATA <= x"C6"; when x"5F4" => DATA <= x"6D"; when x"5F5" => DATA <= x"20"; when x"5F6" => DATA <= x"4E"; when x"5F7" => DATA <= x"D6"; when x"5F8" => DATA <= x"18"; when x"5F9" => DATA <= x"A5"; when x"5FA" => DATA <= x"6E"; when x"5FB" => DATA <= x"20"; when x"5FC" => DATA <= x"36"; when x"5FD" => DATA <= x"D6"; when x"5FE" => DATA <= x"4C"; when x"5FF" => DATA <= x"C6"; when x"600" => DATA <= x"D5"; when x"601" => DATA <= x"20"; when x"602" => DATA <= x"7B"; when x"603" => DATA <= x"D6"; when x"604" => DATA <= x"20"; when x"605" => DATA <= x"78"; when x"606" => DATA <= x"D7"; when x"607" => DATA <= x"18"; when x"608" => DATA <= x"65"; when x"609" => DATA <= x"6D"; when x"60A" => DATA <= x"85"; when x"60B" => DATA <= x"6D"; when x"60C" => DATA <= x"A9"; when x"60D" => DATA <= x"A8"; when x"60E" => DATA <= x"85"; when x"60F" => DATA <= x"59"; when x"610" => DATA <= x"20"; when x"611" => DATA <= x"86"; when x"612" => DATA <= x"D6"; when x"613" => DATA <= x"F0"; when x"614" => DATA <= x"1C"; when x"615" => DATA <= x"20"; when x"616" => DATA <= x"C8"; when x"617" => DATA <= x"D7"; when x"618" => DATA <= x"A5"; when x"619" => DATA <= x"6D"; when x"61A" => DATA <= x"30"; when x"61B" => DATA <= x"0B"; when x"61C" => DATA <= x"F0"; when x"61D" => DATA <= x"10"; when x"61E" => DATA <= x"20"; when x"61F" => DATA <= x"A0"; when x"620" => DATA <= x"D6"; when x"621" => DATA <= x"C6"; when x"622" => DATA <= x"6D"; when x"623" => DATA <= x"D0"; when x"624" => DATA <= x"F9"; when x"625" => DATA <= x"F0"; when x"626" => DATA <= x"07"; when x"627" => DATA <= x"20"; when x"628" => DATA <= x"1B"; when x"629" => DATA <= x"D7"; when x"62A" => DATA <= x"E6"; when x"62B" => DATA <= x"6D"; when x"62C" => DATA <= x"D0"; when x"62D" => DATA <= x"F9"; when x"62E" => DATA <= x"20"; when x"62F" => DATA <= x"9B"; when x"630" => DATA <= x"DA"; when x"631" => DATA <= x"38"; when x"632" => DATA <= x"A4"; when x"633" => DATA <= x"54"; when x"634" => DATA <= x"88"; when x"635" => DATA <= x"60"; when x"636" => DATA <= x"A2"; when x"637" => DATA <= x"05"; when x"638" => DATA <= x"75"; when x"639" => DATA <= x"59"; when x"63A" => DATA <= x"95"; when x"63B" => DATA <= x"59"; when x"63C" => DATA <= x"A9"; when x"63D" => DATA <= x"00"; when x"63E" => DATA <= x"CA"; when x"63F" => DATA <= x"D0"; when x"640" => DATA <= x"F7"; when x"641" => DATA <= x"60"; when x"642" => DATA <= x"A2"; when x"643" => DATA <= x"05"; when x"644" => DATA <= x"B5"; when x"645" => DATA <= x"59"; when x"646" => DATA <= x"75"; when x"647" => DATA <= x"61"; when x"648" => DATA <= x"95"; when x"649" => DATA <= x"59"; when x"64A" => DATA <= x"CA"; when x"64B" => DATA <= x"D0"; when x"64C" => DATA <= x"F7"; when x"64D" => DATA <= x"60"; when x"64E" => DATA <= x"A2"; when x"64F" => DATA <= x"05"; when x"650" => DATA <= x"A9"; when x"651" => DATA <= x"00"; when x"652" => DATA <= x"85"; when x"653" => DATA <= x"67"; when x"654" => DATA <= x"A9"; when x"655" => DATA <= x"00"; when x"656" => DATA <= x"85"; when x"657" => DATA <= x"68"; when x"658" => DATA <= x"B5"; when x"659" => DATA <= x"59"; when x"65A" => DATA <= x"0A"; when x"65B" => DATA <= x"26"; when x"65C" => DATA <= x"68"; when x"65D" => DATA <= x"0A"; when x"65E" => DATA <= x"26"; when x"65F" => DATA <= x"68"; when x"660" => DATA <= x"18"; when x"661" => DATA <= x"75"; when x"662" => DATA <= x"59"; when x"663" => DATA <= x"90"; when x"664" => DATA <= x"02"; when x"665" => DATA <= x"E6"; when x"666" => DATA <= x"68"; when x"667" => DATA <= x"0A"; when x"668" => DATA <= x"26"; when x"669" => DATA <= x"68"; when x"66A" => DATA <= x"18"; when x"66B" => DATA <= x"65"; when x"66C" => DATA <= x"67"; when x"66D" => DATA <= x"90"; when x"66E" => DATA <= x"02"; when x"66F" => DATA <= x"E6"; when x"670" => DATA <= x"68"; when x"671" => DATA <= x"95"; when x"672" => DATA <= x"59"; when x"673" => DATA <= x"A5"; when x"674" => DATA <= x"68"; when x"675" => DATA <= x"85"; when x"676" => DATA <= x"67"; when x"677" => DATA <= x"CA"; when x"678" => DATA <= x"D0"; when x"679" => DATA <= x"DA"; when x"67A" => DATA <= x"60"; when x"67B" => DATA <= x"84"; when x"67C" => DATA <= x"55"; when x"67D" => DATA <= x"A4"; when x"67E" => DATA <= x"54"; when x"67F" => DATA <= x"B1"; when x"680" => DATA <= x"52"; when x"681" => DATA <= x"A4"; when x"682" => DATA <= x"55"; when x"683" => DATA <= x"E6"; when x"684" => DATA <= x"54"; when x"685" => DATA <= x"60"; when x"686" => DATA <= x"A5"; when x"687" => DATA <= x"5A"; when x"688" => DATA <= x"05"; when x"689" => DATA <= x"5B"; when x"68A" => DATA <= x"05"; when x"68B" => DATA <= x"5C"; when x"68C" => DATA <= x"05"; when x"68D" => DATA <= x"5D"; when x"68E" => DATA <= x"05"; when x"68F" => DATA <= x"5E"; when x"690" => DATA <= x"F0"; when x"691" => DATA <= x"07"; when x"692" => DATA <= x"A5"; when x"693" => DATA <= x"57"; when x"694" => DATA <= x"D0"; when x"695" => DATA <= x"09"; when x"696" => DATA <= x"A9"; when x"697" => DATA <= x"01"; when x"698" => DATA <= x"60"; when x"699" => DATA <= x"85"; when x"69A" => DATA <= x"57"; when x"69B" => DATA <= x"85"; when x"69C" => DATA <= x"59"; when x"69D" => DATA <= x"85"; when x"69E" => DATA <= x"58"; when x"69F" => DATA <= x"60"; when x"6A0" => DATA <= x"18"; when x"6A1" => DATA <= x"A5"; when x"6A2" => DATA <= x"59"; when x"6A3" => DATA <= x"69"; when x"6A4" => DATA <= x"03"; when x"6A5" => DATA <= x"85"; when x"6A6" => DATA <= x"59"; when x"6A7" => DATA <= x"90"; when x"6A8" => DATA <= x"02"; when x"6A9" => DATA <= x"E6"; when x"6AA" => DATA <= x"58"; when x"6AB" => DATA <= x"20"; when x"6AC" => DATA <= x"C3"; when x"6AD" => DATA <= x"D6"; when x"6AE" => DATA <= x"20"; when x"6AF" => DATA <= x"FB"; when x"6B0" => DATA <= x"D6"; when x"6B1" => DATA <= x"20"; when x"6B2" => DATA <= x"FB"; when x"6B3" => DATA <= x"D6"; when x"6B4" => DATA <= x"20"; when x"6B5" => DATA <= x"42"; when x"6B6" => DATA <= x"D6"; when x"6B7" => DATA <= x"90"; when x"6B8" => DATA <= x"09"; when x"6B9" => DATA <= x"20"; when x"6BA" => DATA <= x"D8"; when x"6BB" => DATA <= x"D6"; when x"6BC" => DATA <= x"E6"; when x"6BD" => DATA <= x"59"; when x"6BE" => DATA <= x"D0"; when x"6BF" => DATA <= x"02"; when x"6C0" => DATA <= x"E6"; when x"6C1" => DATA <= x"58"; when x"6C2" => DATA <= x"60"; when x"6C3" => DATA <= x"A2"; when x"6C4" => DATA <= x"08"; when x"6C5" => DATA <= x"B5"; when x"6C6" => DATA <= x"56"; when x"6C7" => DATA <= x"95"; when x"6C8" => DATA <= x"5E"; when x"6C9" => DATA <= x"CA"; when x"6CA" => DATA <= x"D0"; when x"6CB" => DATA <= x"F9"; when x"6CC" => DATA <= x"60"; when x"6CD" => DATA <= x"06"; when x"6CE" => DATA <= x"5E"; when x"6CF" => DATA <= x"26"; when x"6D0" => DATA <= x"5D"; when x"6D1" => DATA <= x"26"; when x"6D2" => DATA <= x"5C"; when x"6D3" => DATA <= x"26"; when x"6D4" => DATA <= x"5B"; when x"6D5" => DATA <= x"26"; when x"6D6" => DATA <= x"5A"; when x"6D7" => DATA <= x"60"; when x"6D8" => DATA <= x"66"; when x"6D9" => DATA <= x"5A"; when x"6DA" => DATA <= x"66"; when x"6DB" => DATA <= x"5B"; when x"6DC" => DATA <= x"66"; when x"6DD" => DATA <= x"5C"; when x"6DE" => DATA <= x"66"; when x"6DF" => DATA <= x"5D"; when x"6E0" => DATA <= x"66"; when x"6E1" => DATA <= x"5E"; when x"6E2" => DATA <= x"60"; when x"6E3" => DATA <= x"A5"; when x"6E4" => DATA <= x"5D"; when x"6E5" => DATA <= x"85"; when x"6E6" => DATA <= x"5E"; when x"6E7" => DATA <= x"A5"; when x"6E8" => DATA <= x"5C"; when x"6E9" => DATA <= x"85"; when x"6EA" => DATA <= x"5D"; when x"6EB" => DATA <= x"A5"; when x"6EC" => DATA <= x"5B"; when x"6ED" => DATA <= x"85"; when x"6EE" => DATA <= x"5C"; when x"6EF" => DATA <= x"A5"; when x"6F0" => DATA <= x"5A"; when x"6F1" => DATA <= x"85"; when x"6F2" => DATA <= x"5B"; when x"6F3" => DATA <= x"A9"; when x"6F4" => DATA <= x"00"; when x"6F5" => DATA <= x"85"; when x"6F6" => DATA <= x"5A"; when x"6F7" => DATA <= x"60"; when x"6F8" => DATA <= x"20"; when x"6F9" => DATA <= x"C3"; when x"6FA" => DATA <= x"D6"; when x"6FB" => DATA <= x"46"; when x"6FC" => DATA <= x"62"; when x"6FD" => DATA <= x"66"; when x"6FE" => DATA <= x"63"; when x"6FF" => DATA <= x"66"; when x"700" => DATA <= x"64"; when x"701" => DATA <= x"66"; when x"702" => DATA <= x"65"; when x"703" => DATA <= x"66"; when x"704" => DATA <= x"66"; when x"705" => DATA <= x"60"; when x"706" => DATA <= x"A5"; when x"707" => DATA <= x"65"; when x"708" => DATA <= x"85"; when x"709" => DATA <= x"66"; when x"70A" => DATA <= x"A5"; when x"70B" => DATA <= x"64"; when x"70C" => DATA <= x"85"; when x"70D" => DATA <= x"65"; when x"70E" => DATA <= x"A5"; when x"70F" => DATA <= x"63"; when x"710" => DATA <= x"85"; when x"711" => DATA <= x"64"; when x"712" => DATA <= x"A5"; when x"713" => DATA <= x"62"; when x"714" => DATA <= x"85"; when x"715" => DATA <= x"63"; when x"716" => DATA <= x"A9"; when x"717" => DATA <= x"00"; when x"718" => DATA <= x"85"; when x"719" => DATA <= x"62"; when x"71A" => DATA <= x"60"; when x"71B" => DATA <= x"38"; when x"71C" => DATA <= x"A5"; when x"71D" => DATA <= x"59"; when x"71E" => DATA <= x"E9"; when x"71F" => DATA <= x"04"; when x"720" => DATA <= x"85"; when x"721" => DATA <= x"59"; when x"722" => DATA <= x"B0"; when x"723" => DATA <= x"02"; when x"724" => DATA <= x"C6"; when x"725" => DATA <= x"58"; when x"726" => DATA <= x"20"; when x"727" => DATA <= x"F8"; when x"728" => DATA <= x"D6"; when x"729" => DATA <= x"20"; when x"72A" => DATA <= x"B4"; when x"72B" => DATA <= x"D6"; when x"72C" => DATA <= x"20"; when x"72D" => DATA <= x"F8"; when x"72E" => DATA <= x"D6"; when x"72F" => DATA <= x"20"; when x"730" => DATA <= x"FB"; when x"731" => DATA <= x"D6"; when x"732" => DATA <= x"20"; when x"733" => DATA <= x"FB"; when x"734" => DATA <= x"D6"; when x"735" => DATA <= x"20"; when x"736" => DATA <= x"FB"; when x"737" => DATA <= x"D6"; when x"738" => DATA <= x"20"; when x"739" => DATA <= x"B4"; when x"73A" => DATA <= x"D6"; when x"73B" => DATA <= x"A9"; when x"73C" => DATA <= x"00"; when x"73D" => DATA <= x"85"; when x"73E" => DATA <= x"62"; when x"73F" => DATA <= x"A5"; when x"740" => DATA <= x"5A"; when x"741" => DATA <= x"85"; when x"742" => DATA <= x"63"; when x"743" => DATA <= x"A5"; when x"744" => DATA <= x"5B"; when x"745" => DATA <= x"85"; when x"746" => DATA <= x"64"; when x"747" => DATA <= x"A5"; when x"748" => DATA <= x"5C"; when x"749" => DATA <= x"85"; when x"74A" => DATA <= x"65"; when x"74B" => DATA <= x"A5"; when x"74C" => DATA <= x"5D"; when x"74D" => DATA <= x"85"; when x"74E" => DATA <= x"66"; when x"74F" => DATA <= x"A5"; when x"750" => DATA <= x"5E"; when x"751" => DATA <= x"2A"; when x"752" => DATA <= x"20"; when x"753" => DATA <= x"B4"; when x"754" => DATA <= x"D6"; when x"755" => DATA <= x"A9"; when x"756" => DATA <= x"00"; when x"757" => DATA <= x"85"; when x"758" => DATA <= x"62"; when x"759" => DATA <= x"85"; when x"75A" => DATA <= x"63"; when x"75B" => DATA <= x"A5"; when x"75C" => DATA <= x"5A"; when x"75D" => DATA <= x"85"; when x"75E" => DATA <= x"64"; when x"75F" => DATA <= x"A5"; when x"760" => DATA <= x"5B"; when x"761" => DATA <= x"85"; when x"762" => DATA <= x"65"; when x"763" => DATA <= x"A5"; when x"764" => DATA <= x"5C"; when x"765" => DATA <= x"85"; when x"766" => DATA <= x"66"; when x"767" => DATA <= x"A5"; when x"768" => DATA <= x"5D"; when x"769" => DATA <= x"2A"; when x"76A" => DATA <= x"20"; when x"76B" => DATA <= x"B4"; when x"76C" => DATA <= x"D6"; when x"76D" => DATA <= x"A5"; when x"76E" => DATA <= x"5B"; when x"76F" => DATA <= x"2A"; when x"770" => DATA <= x"A5"; when x"771" => DATA <= x"5A"; when x"772" => DATA <= x"20"; when x"773" => DATA <= x"36"; when x"774" => DATA <= x"D6"; when x"775" => DATA <= x"4C"; when x"776" => DATA <= x"B7"; when x"777" => DATA <= x"D6"; when x"778" => DATA <= x"A0"; when x"779" => DATA <= x"FF"; when x"77A" => DATA <= x"C9"; when x"77B" => DATA <= x"2B"; when x"77C" => DATA <= x"F0"; when x"77D" => DATA <= x"05"; when x"77E" => DATA <= x"C9"; when x"77F" => DATA <= x"2D"; when x"780" => DATA <= x"D0"; when x"781" => DATA <= x"04"; when x"782" => DATA <= x"C8"; when x"783" => DATA <= x"20"; when x"784" => DATA <= x"7B"; when x"785" => DATA <= x"D6"; when x"786" => DATA <= x"20"; when x"787" => DATA <= x"C3"; when x"788" => DATA <= x"D4"; when x"789" => DATA <= x"90"; when x"78A" => DATA <= x"24"; when x"78B" => DATA <= x"AA"; when x"78C" => DATA <= x"20"; when x"78D" => DATA <= x"7B"; when x"78E" => DATA <= x"D6"; when x"78F" => DATA <= x"20"; when x"790" => DATA <= x"C3"; when x"791" => DATA <= x"D4"; when x"792" => DATA <= x"90"; when x"793" => DATA <= x"10"; when x"794" => DATA <= x"85"; when x"795" => DATA <= x"6E"; when x"796" => DATA <= x"20"; when x"797" => DATA <= x"7B"; when x"798" => DATA <= x"D6"; when x"799" => DATA <= x"8A"; when x"79A" => DATA <= x"85"; when x"79B" => DATA <= x"67"; when x"79C" => DATA <= x"0A"; when x"79D" => DATA <= x"0A"; when x"79E" => DATA <= x"65"; when x"79F" => DATA <= x"67"; when x"7A0" => DATA <= x"0A"; when x"7A1" => DATA <= x"65"; when x"7A2" => DATA <= x"6E"; when x"7A3" => DATA <= x"AA"; when x"7A4" => DATA <= x"98"; when x"7A5" => DATA <= x"D0"; when x"7A6" => DATA <= x"06"; when x"7A7" => DATA <= x"86"; when x"7A8" => DATA <= x"6E"; when x"7A9" => DATA <= x"38"; when x"7AA" => DATA <= x"E5"; when x"7AB" => DATA <= x"6E"; when x"7AC" => DATA <= x"60"; when x"7AD" => DATA <= x"8A"; when x"7AE" => DATA <= x"60"; when x"7AF" => DATA <= x"A9"; when x"7B0" => DATA <= x"00"; when x"7B1" => DATA <= x"60"; when x"7B2" => DATA <= x"48"; when x"7B3" => DATA <= x"20"; when x"7B4" => DATA <= x"A4"; when x"7B5" => DATA <= x"DA"; when x"7B6" => DATA <= x"68"; when x"7B7" => DATA <= x"F0"; when x"7B8" => DATA <= x"F8"; when x"7B9" => DATA <= x"10"; when x"7BA" => DATA <= x"07"; when x"7BB" => DATA <= x"85"; when x"7BC" => DATA <= x"57"; when x"7BD" => DATA <= x"A9"; when x"7BE" => DATA <= x"00"; when x"7BF" => DATA <= x"38"; when x"7C0" => DATA <= x"E5"; when x"7C1" => DATA <= x"57"; when x"7C2" => DATA <= x"85"; when x"7C3" => DATA <= x"5A"; when x"7C4" => DATA <= x"A9"; when x"7C5" => DATA <= x"88"; when x"7C6" => DATA <= x"85"; when x"7C7" => DATA <= x"59"; when x"7C8" => DATA <= x"20"; when x"7C9" => DATA <= x"86"; when x"7CA" => DATA <= x"D6"; when x"7CB" => DATA <= x"F0"; when x"7CC" => DATA <= x"E4"; when x"7CD" => DATA <= x"A5"; when x"7CE" => DATA <= x"5A"; when x"7CF" => DATA <= x"D0"; when x"7D0" => DATA <= x"21"; when x"7D1" => DATA <= x"A5"; when x"7D2" => DATA <= x"5B"; when x"7D3" => DATA <= x"85"; when x"7D4" => DATA <= x"5A"; when x"7D5" => DATA <= x"A5"; when x"7D6" => DATA <= x"5C"; when x"7D7" => DATA <= x"85"; when x"7D8" => DATA <= x"5B"; when x"7D9" => DATA <= x"A5"; when x"7DA" => DATA <= x"5D"; when x"7DB" => DATA <= x"85"; when x"7DC" => DATA <= x"5C"; when x"7DD" => DATA <= x"A5"; when x"7DE" => DATA <= x"5E"; when x"7DF" => DATA <= x"85"; when x"7E0" => DATA <= x"5D"; when x"7E1" => DATA <= x"A9"; when x"7E2" => DATA <= x"00"; when x"7E3" => DATA <= x"85"; when x"7E4" => DATA <= x"5E"; when x"7E5" => DATA <= x"38"; when x"7E6" => DATA <= x"A5"; when x"7E7" => DATA <= x"59"; when x"7E8" => DATA <= x"E9"; when x"7E9" => DATA <= x"08"; when x"7EA" => DATA <= x"85"; when x"7EB" => DATA <= x"59"; when x"7EC" => DATA <= x"B0"; when x"7ED" => DATA <= x"DF"; when x"7EE" => DATA <= x"C6"; when x"7EF" => DATA <= x"58"; when x"7F0" => DATA <= x"90"; when x"7F1" => DATA <= x"DB"; when x"7F2" => DATA <= x"A5"; when x"7F3" => DATA <= x"5A"; when x"7F4" => DATA <= x"30"; when x"7F5" => DATA <= x"BB"; when x"7F6" => DATA <= x"20"; when x"7F7" => DATA <= x"CD"; when x"7F8" => DATA <= x"D6"; when x"7F9" => DATA <= x"A5"; when x"7FA" => DATA <= x"59"; when x"7FB" => DATA <= x"D0"; when x"7FC" => DATA <= x"02"; when x"7FD" => DATA <= x"C6"; when x"7FE" => DATA <= x"58"; when x"7FF" => DATA <= x"C6"; when x"800" => DATA <= x"59"; when x"801" => DATA <= x"4C"; when x"802" => DATA <= x"F2"; when x"803" => DATA <= x"D7"; when x"804" => DATA <= x"A0"; when x"805" => DATA <= x"04"; when x"806" => DATA <= x"A9"; when x"807" => DATA <= x"00"; when x"808" => DATA <= x"85"; when x"809" => DATA <= x"66"; when x"80A" => DATA <= x"85"; when x"80B" => DATA <= x"60"; when x"80C" => DATA <= x"85"; when x"80D" => DATA <= x"5F"; when x"80E" => DATA <= x"B1"; when x"80F" => DATA <= x"6F"; when x"810" => DATA <= x"99"; when x"811" => DATA <= x"61"; when x"812" => DATA <= x"00"; when x"813" => DATA <= x"05"; when x"814" => DATA <= x"5F"; when x"815" => DATA <= x"85"; when x"816" => DATA <= x"5F"; when x"817" => DATA <= x"88"; when x"818" => DATA <= x"10"; when x"819" => DATA <= x"F4"; when x"81A" => DATA <= x"AA"; when x"81B" => DATA <= x"F0"; when x"81C" => DATA <= x"09"; when x"81D" => DATA <= x"A5"; when x"81E" => DATA <= x"62"; when x"81F" => DATA <= x"85"; when x"820" => DATA <= x"5F"; when x"821" => DATA <= x"09"; when x"822" => DATA <= x"80"; when x"823" => DATA <= x"85"; when x"824" => DATA <= x"62"; when x"825" => DATA <= x"8A"; when x"826" => DATA <= x"60"; when x"827" => DATA <= x"20"; when x"828" => DATA <= x"A2"; when x"829" => DATA <= x"DB"; when x"82A" => DATA <= x"D0"; when x"82B" => DATA <= x"11"; when x"82C" => DATA <= x"20"; when x"82D" => DATA <= x"A6"; when x"82E" => DATA <= x"DB"; when x"82F" => DATA <= x"D0"; when x"830" => DATA <= x"0C"; when x"831" => DATA <= x"20"; when x"832" => DATA <= x"AA"; when x"833" => DATA <= x"DB"; when x"834" => DATA <= x"D0"; when x"835" => DATA <= x"07"; when x"836" => DATA <= x"A6"; when x"837" => DATA <= x"04"; when x"838" => DATA <= x"A0"; when x"839" => DATA <= x"6F"; when x"83A" => DATA <= x"20"; when x"83B" => DATA <= x"CD"; when x"83C" => DATA <= x"C3"; when x"83D" => DATA <= x"A0"; when x"83E" => DATA <= x"00"; when x"83F" => DATA <= x"A5"; when x"840" => DATA <= x"59"; when x"841" => DATA <= x"91"; when x"842" => DATA <= x"6F"; when x"843" => DATA <= x"C8"; when x"844" => DATA <= x"A5"; when x"845" => DATA <= x"57"; when x"846" => DATA <= x"29"; when x"847" => DATA <= x"80"; when x"848" => DATA <= x"85"; when x"849" => DATA <= x"57"; when x"84A" => DATA <= x"A5"; when x"84B" => DATA <= x"5A"; when x"84C" => DATA <= x"29"; when x"84D" => DATA <= x"7F"; when x"84E" => DATA <= x"05"; when x"84F" => DATA <= x"57"; when x"850" => DATA <= x"91"; when x"851" => DATA <= x"6F"; when x"852" => DATA <= x"C8"; when x"853" => DATA <= x"B9"; when x"854" => DATA <= x"59"; when x"855" => DATA <= x"00"; when x"856" => DATA <= x"91"; when x"857" => DATA <= x"6F"; when x"858" => DATA <= x"C0"; when x"859" => DATA <= x"04"; when x"85A" => DATA <= x"D0"; when x"85B" => DATA <= x"F6"; when x"85C" => DATA <= x"60"; when x"85D" => DATA <= x"A0"; when x"85E" => DATA <= x"52"; when x"85F" => DATA <= x"84"; when x"860" => DATA <= x"6F"; when x"861" => DATA <= x"A9"; when x"862" => DATA <= x"00"; when x"863" => DATA <= x"85"; when x"864" => DATA <= x"70"; when x"865" => DATA <= x"20"; when x"866" => DATA <= x"3D"; when x"867" => DATA <= x"D8"; when x"868" => DATA <= x"20"; when x"869" => DATA <= x"D9"; when x"86A" => DATA <= x"C4"; when x"86B" => DATA <= x"A5"; when x"86C" => DATA <= x"56"; when x"86D" => DATA <= x"95"; when x"86E" => DATA <= x"73"; when x"86F" => DATA <= x"60"; when x"870" => DATA <= x"A6"; when x"871" => DATA <= x"04"; when x"872" => DATA <= x"20"; when x"873" => DATA <= x"CB"; when x"874" => DATA <= x"C3"; when x"875" => DATA <= x"B5"; when x"876" => DATA <= x"74"; when x"877" => DATA <= x"85"; when x"878" => DATA <= x"56"; when x"879" => DATA <= x"84"; when x"87A" => DATA <= x"6F"; when x"87B" => DATA <= x"A9"; when x"87C" => DATA <= x"00"; when x"87D" => DATA <= x"85"; when x"87E" => DATA <= x"70"; when x"87F" => DATA <= x"60"; when x"880" => DATA <= x"A5"; when x"881" => DATA <= x"5E"; when x"882" => DATA <= x"C9"; when x"883" => DATA <= x"80"; when x"884" => DATA <= x"90"; when x"885" => DATA <= x"07"; when x"886" => DATA <= x"F0"; when x"887" => DATA <= x"0A"; when x"888" => DATA <= x"A9"; when x"889" => DATA <= x"FF"; when x"88A" => DATA <= x"20"; when x"88B" => DATA <= x"72"; when x"88C" => DATA <= x"D7"; when x"88D" => DATA <= x"A9"; when x"88E" => DATA <= x"00"; when x"88F" => DATA <= x"85"; when x"890" => DATA <= x"5E"; when x"891" => DATA <= x"60"; when x"892" => DATA <= x"A5"; when x"893" => DATA <= x"5D"; when x"894" => DATA <= x"09"; when x"895" => DATA <= x"01"; when x"896" => DATA <= x"85"; when x"897" => DATA <= x"5D"; when x"898" => DATA <= x"D0"; when x"899" => DATA <= x"F3"; when x"89A" => DATA <= x"20"; when x"89B" => DATA <= x"C7"; when x"89C" => DATA <= x"D8"; when x"89D" => DATA <= x"F0"; when x"89E" => DATA <= x"06"; when x"89F" => DATA <= x"A5"; when x"8A0" => DATA <= x"59"; when x"8A1" => DATA <= x"C9"; when x"8A2" => DATA <= x"A0"; when x"8A3" => DATA <= x"B0"; when x"8A4" => DATA <= x"14"; when x"8A5" => DATA <= x"46"; when x"8A6" => DATA <= x"5A"; when x"8A7" => DATA <= x"66"; when x"8A8" => DATA <= x"5B"; when x"8A9" => DATA <= x"66"; when x"8AA" => DATA <= x"5C"; when x"8AB" => DATA <= x"66"; when x"8AC" => DATA <= x"5D"; when x"8AD" => DATA <= x"66"; when x"8AE" => DATA <= x"62"; when x"8AF" => DATA <= x"66"; when x"8B0" => DATA <= x"63"; when x"8B1" => DATA <= x"66"; when x"8B2" => DATA <= x"64"; when x"8B3" => DATA <= x"66"; when x"8B4" => DATA <= x"65"; when x"8B5" => DATA <= x"E6"; when x"8B6" => DATA <= x"59"; when x"8B7" => DATA <= x"D0"; when x"8B8" => DATA <= x"E6"; when x"8B9" => DATA <= x"F0"; when x"8BA" => DATA <= x"16"; when x"8BB" => DATA <= x"A9"; when x"8BC" => DATA <= x"7F"; when x"8BD" => DATA <= x"85"; when x"8BE" => DATA <= x"5A"; when x"8BF" => DATA <= x"A9"; when x"8C0" => DATA <= x"FF"; when x"8C1" => DATA <= x"85"; when x"8C2" => DATA <= x"5B"; when x"8C3" => DATA <= x"85"; when x"8C4" => DATA <= x"5C"; when x"8C5" => DATA <= x"85"; when x"8C6" => DATA <= x"5D"; when x"8C7" => DATA <= x"A2"; when x"8C8" => DATA <= x"08"; when x"8C9" => DATA <= x"A9"; when x"8CA" => DATA <= x"00"; when x"8CB" => DATA <= x"95"; when x"8CC" => DATA <= x"5F"; when x"8CD" => DATA <= x"CA"; when x"8CE" => DATA <= x"D0"; when x"8CF" => DATA <= x"FB"; when x"8D0" => DATA <= x"60"; when x"8D1" => DATA <= x"A5"; when x"8D2" => DATA <= x"57"; when x"8D3" => DATA <= x"10"; when x"8D4" => DATA <= x"0C"; when x"8D5" => DATA <= x"38"; when x"8D6" => DATA <= x"A2"; when x"8D7" => DATA <= x"04"; when x"8D8" => DATA <= x"A9"; when x"8D9" => DATA <= x"00"; when x"8DA" => DATA <= x"F5"; when x"8DB" => DATA <= x"59"; when x"8DC" => DATA <= x"95"; when x"8DD" => DATA <= x"59"; when x"8DE" => DATA <= x"CA"; when x"8DF" => DATA <= x"D0"; when x"8E0" => DATA <= x"F7"; when x"8E1" => DATA <= x"60"; when x"8E2" => DATA <= x"A5"; when x"8E3" => DATA <= x"62"; when x"8E4" => DATA <= x"10"; when x"8E5" => DATA <= x"23"; when x"8E6" => DATA <= x"A2"; when x"8E7" => DATA <= x"04"; when x"8E8" => DATA <= x"A9"; when x"8E9" => DATA <= x"00"; when x"8EA" => DATA <= x"F5"; when x"8EB" => DATA <= x"61"; when x"8EC" => DATA <= x"95"; when x"8ED" => DATA <= x"61"; when x"8EE" => DATA <= x"CA"; when x"8EF" => DATA <= x"D0"; when x"8F0" => DATA <= x"F7"; when x"8F1" => DATA <= x"A5"; when x"8F2" => DATA <= x"57"; when x"8F3" => DATA <= x"49"; when x"8F4" => DATA <= x"80"; when x"8F5" => DATA <= x"85"; when x"8F6" => DATA <= x"57"; when x"8F7" => DATA <= x"10"; when x"8F8" => DATA <= x"11"; when x"8F9" => DATA <= x"E6"; when x"8FA" => DATA <= x"5D"; when x"8FB" => DATA <= x"D0"; when x"8FC" => DATA <= x"0C"; when x"8FD" => DATA <= x"E6"; when x"8FE" => DATA <= x"5C"; when x"8FF" => DATA <= x"D0"; when x"900" => DATA <= x"08"; when x"901" => DATA <= x"E6"; when x"902" => DATA <= x"5B"; when x"903" => DATA <= x"D0"; when x"904" => DATA <= x"04"; when x"905" => DATA <= x"E6"; when x"906" => DATA <= x"5A"; when x"907" => DATA <= x"F0"; when x"908" => DATA <= x"B2"; when x"909" => DATA <= x"60"; when x"90A" => DATA <= x"20"; when x"90B" => DATA <= x"D5"; when x"90C" => DATA <= x"D8"; when x"90D" => DATA <= x"20"; when x"90E" => DATA <= x"F9"; when x"90F" => DATA <= x"D8"; when x"910" => DATA <= x"4C"; when x"911" => DATA <= x"D5"; when x"912" => DATA <= x"D8"; when x"913" => DATA <= x"A2"; when x"914" => DATA <= x"05"; when x"915" => DATA <= x"B5"; when x"916" => DATA <= x"61"; when x"917" => DATA <= x"95"; when x"918" => DATA <= x"59"; when x"919" => DATA <= x"CA"; when x"91A" => DATA <= x"D0"; when x"91B" => DATA <= x"F9"; when x"91C" => DATA <= x"A9"; when x"91D" => DATA <= x"80"; when x"91E" => DATA <= x"85"; when x"91F" => DATA <= x"59"; when x"920" => DATA <= x"4C"; when x"921" => DATA <= x"C8"; when x"922" => DATA <= x"D7"; when x"923" => DATA <= x"20"; when x"924" => DATA <= x"04"; when x"925" => DATA <= x"D8"; when x"926" => DATA <= x"20"; when x"927" => DATA <= x"3D"; when x"928" => DATA <= x"D8"; when x"929" => DATA <= x"A2"; when x"92A" => DATA <= x"08"; when x"92B" => DATA <= x"B5"; when x"92C" => DATA <= x"5E"; when x"92D" => DATA <= x"95"; when x"92E" => DATA <= x"56"; when x"92F" => DATA <= x"CA"; when x"930" => DATA <= x"D0"; when x"931" => DATA <= x"F9"; when x"932" => DATA <= x"60"; when x"933" => DATA <= x"20"; when x"934" => DATA <= x"39"; when x"935" => DATA <= x"D9"; when x"936" => DATA <= x"4C"; when x"937" => DATA <= x"BF"; when x"938" => DATA <= x"D1"; when x"939" => DATA <= x"20"; when x"93A" => DATA <= x"BF"; when x"93B" => DATA <= x"D1"; when x"93C" => DATA <= x"20"; when x"93D" => DATA <= x"04"; when x"93E" => DATA <= x"D8"; when x"93F" => DATA <= x"F0"; when x"940" => DATA <= x"F1"; when x"941" => DATA <= x"20"; when x"942" => DATA <= x"86"; when x"943" => DATA <= x"D6"; when x"944" => DATA <= x"F0"; when x"945" => DATA <= x"E3"; when x"946" => DATA <= x"A5"; when x"947" => DATA <= x"59"; when x"948" => DATA <= x"C5"; when x"949" => DATA <= x"61"; when x"94A" => DATA <= x"F0"; when x"94B" => DATA <= x"26"; when x"94C" => DATA <= x"90"; when x"94D" => DATA <= x"0F"; when x"94E" => DATA <= x"E5"; when x"94F" => DATA <= x"61"; when x"950" => DATA <= x"C9"; when x"951" => DATA <= x"21"; when x"952" => DATA <= x"B0"; when x"953" => DATA <= x"DE"; when x"954" => DATA <= x"AA"; when x"955" => DATA <= x"20"; when x"956" => DATA <= x"FB"; when x"957" => DATA <= x"D6"; when x"958" => DATA <= x"CA"; when x"959" => DATA <= x"D0"; when x"95A" => DATA <= x"FA"; when x"95B" => DATA <= x"F0"; when x"95C" => DATA <= x"15"; when x"95D" => DATA <= x"38"; when x"95E" => DATA <= x"A5"; when x"95F" => DATA <= x"61"; when x"960" => DATA <= x"E5"; when x"961" => DATA <= x"59"; when x"962" => DATA <= x"C9"; when x"963" => DATA <= x"21"; when x"964" => DATA <= x"B0"; when x"965" => DATA <= x"C3"; when x"966" => DATA <= x"AA"; when x"967" => DATA <= x"18"; when x"968" => DATA <= x"20"; when x"969" => DATA <= x"D8"; when x"96A" => DATA <= x"D6"; when x"96B" => DATA <= x"CA"; when x"96C" => DATA <= x"D0"; when x"96D" => DATA <= x"F9"; when x"96E" => DATA <= x"A5"; when x"96F" => DATA <= x"61"; when x"970" => DATA <= x"85"; when x"971" => DATA <= x"59"; when x"972" => DATA <= x"A5"; when x"973" => DATA <= x"57"; when x"974" => DATA <= x"45"; when x"975" => DATA <= x"5F"; when x"976" => DATA <= x"10"; when x"977" => DATA <= x"49"; when x"978" => DATA <= x"A5"; when x"979" => DATA <= x"5A"; when x"97A" => DATA <= x"C5"; when x"97B" => DATA <= x"62"; when x"97C" => DATA <= x"D0"; when x"97D" => DATA <= x"1B"; when x"97E" => DATA <= x"A5"; when x"97F" => DATA <= x"5B"; when x"980" => DATA <= x"C5"; when x"981" => DATA <= x"63"; when x"982" => DATA <= x"D0"; when x"983" => DATA <= x"15"; when x"984" => DATA <= x"A5"; when x"985" => DATA <= x"5C"; when x"986" => DATA <= x"C5"; when x"987" => DATA <= x"64"; when x"988" => DATA <= x"D0"; when x"989" => DATA <= x"0F"; when x"98A" => DATA <= x"A5"; when x"98B" => DATA <= x"5D"; when x"98C" => DATA <= x"C5"; when x"98D" => DATA <= x"65"; when x"98E" => DATA <= x"D0"; when x"98F" => DATA <= x"09"; when x"990" => DATA <= x"A5"; when x"991" => DATA <= x"5E"; when x"992" => DATA <= x"C5"; when x"993" => DATA <= x"66"; when x"994" => DATA <= x"D0"; when x"995" => DATA <= x"03"; when x"996" => DATA <= x"4C"; when x"997" => DATA <= x"A4"; when x"998" => DATA <= x"DA"; when x"999" => DATA <= x"B0"; when x"99A" => DATA <= x"2D"; when x"99B" => DATA <= x"38"; when x"99C" => DATA <= x"A5"; when x"99D" => DATA <= x"66"; when x"99E" => DATA <= x"E5"; when x"99F" => DATA <= x"5E"; when x"9A0" => DATA <= x"85"; when x"9A1" => DATA <= x"5E"; when x"9A2" => DATA <= x"A5"; when x"9A3" => DATA <= x"65"; when x"9A4" => DATA <= x"E5"; when x"9A5" => DATA <= x"5D"; when x"9A6" => DATA <= x"85"; when x"9A7" => DATA <= x"5D"; when x"9A8" => DATA <= x"A5"; when x"9A9" => DATA <= x"64"; when x"9AA" => DATA <= x"E5"; when x"9AB" => DATA <= x"5C"; when x"9AC" => DATA <= x"85"; when x"9AD" => DATA <= x"5C"; when x"9AE" => DATA <= x"A5"; when x"9AF" => DATA <= x"63"; when x"9B0" => DATA <= x"E5"; when x"9B1" => DATA <= x"5B"; when x"9B2" => DATA <= x"85"; when x"9B3" => DATA <= x"5B"; when x"9B4" => DATA <= x"A5"; when x"9B5" => DATA <= x"62"; when x"9B6" => DATA <= x"E5"; when x"9B7" => DATA <= x"5A"; when x"9B8" => DATA <= x"85"; when x"9B9" => DATA <= x"5A"; when x"9BA" => DATA <= x"A5"; when x"9BB" => DATA <= x"5F"; when x"9BC" => DATA <= x"85"; when x"9BD" => DATA <= x"57"; when x"9BE" => DATA <= x"4C"; when x"9BF" => DATA <= x"98"; when x"9C0" => DATA <= x"DA"; when x"9C1" => DATA <= x"18"; when x"9C2" => DATA <= x"20"; when x"9C3" => DATA <= x"B4"; when x"9C4" => DATA <= x"D6"; when x"9C5" => DATA <= x"4C"; when x"9C6" => DATA <= x"9B"; when x"9C7" => DATA <= x"DA"; when x"9C8" => DATA <= x"38"; when x"9C9" => DATA <= x"A5"; when x"9CA" => DATA <= x"5E"; when x"9CB" => DATA <= x"E5"; when x"9CC" => DATA <= x"66"; when x"9CD" => DATA <= x"85"; when x"9CE" => DATA <= x"5E"; when x"9CF" => DATA <= x"A5"; when x"9D0" => DATA <= x"5D"; when x"9D1" => DATA <= x"E5"; when x"9D2" => DATA <= x"65"; when x"9D3" => DATA <= x"85"; when x"9D4" => DATA <= x"5D"; when x"9D5" => DATA <= x"A5"; when x"9D6" => DATA <= x"5C"; when x"9D7" => DATA <= x"E5"; when x"9D8" => DATA <= x"64"; when x"9D9" => DATA <= x"85"; when x"9DA" => DATA <= x"5C"; when x"9DB" => DATA <= x"A5"; when x"9DC" => DATA <= x"5B"; when x"9DD" => DATA <= x"E5"; when x"9DE" => DATA <= x"63"; when x"9DF" => DATA <= x"85"; when x"9E0" => DATA <= x"5B"; when x"9E1" => DATA <= x"A5"; when x"9E2" => DATA <= x"5A"; when x"9E3" => DATA <= x"E5"; when x"9E4" => DATA <= x"62"; when x"9E5" => DATA <= x"85"; when x"9E6" => DATA <= x"5A"; when x"9E7" => DATA <= x"4C"; when x"9E8" => DATA <= x"98"; when x"9E9" => DATA <= x"DA"; when x"9EA" => DATA <= x"00"; when x"9EB" => DATA <= x"20"; when x"9EC" => DATA <= x"FC"; when x"9ED" => DATA <= x"D0"; when x"9EE" => DATA <= x"A9"; when x"9EF" => DATA <= x"C7"; when x"9F0" => DATA <= x"48"; when x"9F1" => DATA <= x"A2"; when x"9F2" => DATA <= x"C8"; when x"9F3" => DATA <= x"4C"; when x"9F4" => DATA <= x"0B"; when x"9F5" => DATA <= x"D1"; when x"9F6" => DATA <= x"A9"; when x"9F7" => DATA <= x"5D"; when x"9F8" => DATA <= x"D0"; when x"9F9" => DATA <= x"12"; when x"9FA" => DATA <= x"A9"; when x"9FB" => DATA <= x"66"; when x"9FC" => DATA <= x"D0"; when x"9FD" => DATA <= x"0E"; when x"9FE" => DATA <= x"A9"; when x"9FF" => DATA <= x"6F"; when x"A00" => DATA <= x"D0"; when x"A01" => DATA <= x"0A"; when x"A02" => DATA <= x"A9"; when x"A03" => DATA <= x"76"; when x"A04" => DATA <= x"D0"; when x"A05" => DATA <= x"06"; when x"A06" => DATA <= x"A9"; when x"A07" => DATA <= x"7D"; when x"A08" => DATA <= x"D0"; when x"A09" => DATA <= x"02"; when x"A0A" => DATA <= x"A9"; when x"A0B" => DATA <= x"84"; when x"A0C" => DATA <= x"48"; when x"A0D" => DATA <= x"20"; when x"A0E" => DATA <= x"5D"; when x"A0F" => DATA <= x"D8"; when x"A10" => DATA <= x"20"; when x"A11" => DATA <= x"FC"; when x"A12" => DATA <= x"D0"; when x"A13" => DATA <= x"20"; when x"A14" => DATA <= x"70"; when x"A15" => DATA <= x"D8"; when x"A16" => DATA <= x"E6"; when x"A17" => DATA <= x"04"; when x"A18" => DATA <= x"20"; when x"A19" => DATA <= x"04"; when x"A1A" => DATA <= x"D8"; when x"A1B" => DATA <= x"A5"; when x"A1C" => DATA <= x"5F"; when x"A1D" => DATA <= x"29"; when x"A1E" => DATA <= x"80"; when x"A1F" => DATA <= x"85"; when x"A20" => DATA <= x"5F"; when x"A21" => DATA <= x"A0"; when x"A22" => DATA <= x"00"; when x"A23" => DATA <= x"A5"; when x"A24" => DATA <= x"57"; when x"A25" => DATA <= x"29"; when x"A26" => DATA <= x"80"; when x"A27" => DATA <= x"C5"; when x"A28" => DATA <= x"5F"; when x"A29" => DATA <= x"D0"; when x"A2A" => DATA <= x"0D"; when x"A2B" => DATA <= x"A2"; when x"A2C" => DATA <= x"00"; when x"A2D" => DATA <= x"B5"; when x"A2E" => DATA <= x"61"; when x"A2F" => DATA <= x"D5"; when x"A30" => DATA <= x"59"; when x"A31" => DATA <= x"D0"; when x"A32" => DATA <= x"0A"; when x"A33" => DATA <= x"E8"; when x"A34" => DATA <= x"E0"; when x"A35" => DATA <= x"05"; when x"A36" => DATA <= x"D0"; when x"A37" => DATA <= x"F5"; when x"A38" => DATA <= x"08"; when x"A39" => DATA <= x"A6"; when x"A3A" => DATA <= x"04"; when x"A3B" => DATA <= x"28"; when x"A3C" => DATA <= x"60"; when x"A3D" => DATA <= x"6A"; when x"A3E" => DATA <= x"45"; when x"A3F" => DATA <= x"5F"; when x"A40" => DATA <= x"2A"; when x"A41" => DATA <= x"A9"; when x"A42" => DATA <= x"01"; when x"A43" => DATA <= x"D0"; when x"A44" => DATA <= x"F3"; when x"A45" => DATA <= x"20"; when x"A46" => DATA <= x"86"; when x"A47" => DATA <= x"D6"; when x"A48" => DATA <= x"F0"; when x"A49" => DATA <= x"F2"; when x"A4A" => DATA <= x"20"; when x"A4B" => DATA <= x"04"; when x"A4C" => DATA <= x"D8"; when x"A4D" => DATA <= x"D0"; when x"A4E" => DATA <= x"03"; when x"A4F" => DATA <= x"4C"; when x"A50" => DATA <= x"A4"; when x"A51" => DATA <= x"DA"; when x"A52" => DATA <= x"18"; when x"A53" => DATA <= x"A5"; when x"A54" => DATA <= x"59"; when x"A55" => DATA <= x"65"; when x"A56" => DATA <= x"61"; when x"A57" => DATA <= x"85"; when x"A58" => DATA <= x"59"; when x"A59" => DATA <= x"90"; when x"A5A" => DATA <= x"02"; when x"A5B" => DATA <= x"E6"; when x"A5C" => DATA <= x"58"; when x"A5D" => DATA <= x"38"; when x"A5E" => DATA <= x"A5"; when x"A5F" => DATA <= x"59"; when x"A60" => DATA <= x"E9"; when x"A61" => DATA <= x"80"; when x"A62" => DATA <= x"85"; when x"A63" => DATA <= x"59"; when x"A64" => DATA <= x"B0"; when x"A65" => DATA <= x"02"; when x"A66" => DATA <= x"C6"; when x"A67" => DATA <= x"58"; when x"A68" => DATA <= x"A2"; when x"A69" => DATA <= x"05"; when x"A6A" => DATA <= x"A0"; when x"A6B" => DATA <= x"00"; when x"A6C" => DATA <= x"B5"; when x"A6D" => DATA <= x"59"; when x"A6E" => DATA <= x"95"; when x"A6F" => DATA <= x"66"; when x"A70" => DATA <= x"94"; when x"A71" => DATA <= x"59"; when x"A72" => DATA <= x"CA"; when x"A73" => DATA <= x"D0"; when x"A74" => DATA <= x"F7"; when x"A75" => DATA <= x"A5"; when x"A76" => DATA <= x"57"; when x"A77" => DATA <= x"45"; when x"A78" => DATA <= x"5F"; when x"A79" => DATA <= x"85"; when x"A7A" => DATA <= x"57"; when x"A7B" => DATA <= x"A0"; when x"A7C" => DATA <= x"20"; when x"A7D" => DATA <= x"20"; when x"A7E" => DATA <= x"FB"; when x"A7F" => DATA <= x"D6"; when x"A80" => DATA <= x"A5"; when x"A81" => DATA <= x"67"; when x"A82" => DATA <= x"10"; when x"A83" => DATA <= x"04"; when x"A84" => DATA <= x"18"; when x"A85" => DATA <= x"20"; when x"A86" => DATA <= x"42"; when x"A87" => DATA <= x"D6"; when x"A88" => DATA <= x"20"; when x"A89" => DATA <= x"FB"; when x"A8A" => DATA <= x"D6"; when x"A8B" => DATA <= x"06"; when x"A8C" => DATA <= x"6B"; when x"A8D" => DATA <= x"26"; when x"A8E" => DATA <= x"6A"; when x"A8F" => DATA <= x"26"; when x"A90" => DATA <= x"69"; when x"A91" => DATA <= x"26"; when x"A92" => DATA <= x"68"; when x"A93" => DATA <= x"26"; when x"A94" => DATA <= x"67"; when x"A95" => DATA <= x"88"; when x"A96" => DATA <= x"D0"; when x"A97" => DATA <= x"E8"; when x"A98" => DATA <= x"20"; when x"A99" => DATA <= x"C8"; when x"A9A" => DATA <= x"D7"; when x"A9B" => DATA <= x"20"; when x"A9C" => DATA <= x"80"; when x"A9D" => DATA <= x"D8"; when x"A9E" => DATA <= x"A5"; when x"A9F" => DATA <= x"58"; when x"AA0" => DATA <= x"F0"; when x"AA1" => DATA <= x"0B"; when x"AA2" => DATA <= x"10"; when x"AA3" => DATA <= x"03"; when x"AA4" => DATA <= x"A2"; when x"AA5" => DATA <= x"08"; when x"AA6" => DATA <= x"A9"; when x"AA7" => DATA <= x"00"; when x"AA8" => DATA <= x"95"; when x"AA9" => DATA <= x"56"; when x"AAA" => DATA <= x"CA"; when x"AAB" => DATA <= x"D0"; when x"AAC" => DATA <= x"FB"; when x"AAD" => DATA <= x"60"; when x"AAE" => DATA <= x"20"; when x"AAF" => DATA <= x"31"; when x"AB0" => DATA <= x"D8"; when x"AB1" => DATA <= x"20"; when x"AB2" => DATA <= x"8D"; when x"AB3" => DATA <= x"DE"; when x"AB4" => DATA <= x"D0"; when x"AB5" => DATA <= x"26"; when x"AB6" => DATA <= x"20"; when x"AB7" => DATA <= x"86"; when x"AB8" => DATA <= x"D6"; when x"AB9" => DATA <= x"F0"; when x"ABA" => DATA <= x"EC"; when x"ABB" => DATA <= x"20"; when x"ABC" => DATA <= x"C3"; when x"ABD" => DATA <= x"D6"; when x"ABE" => DATA <= x"20"; when x"ABF" => DATA <= x"E5"; when x"AC0" => DATA <= x"D1"; when x"AC1" => DATA <= x"D0"; when x"AC2" => DATA <= x"23"; when x"AC3" => DATA <= x"60"; when x"AC4" => DATA <= x"20"; when x"AC5" => DATA <= x"EB"; when x"AC6" => DATA <= x"D0"; when x"AC7" => DATA <= x"20"; when x"AC8" => DATA <= x"9E"; when x"AC9" => DATA <= x"DB"; when x"ACA" => DATA <= x"20"; when x"ACB" => DATA <= x"3D"; when x"ACC" => DATA <= x"D8"; when x"ACD" => DATA <= x"20"; when x"ACE" => DATA <= x"E6"; when x"ACF" => DATA <= x"DC"; when x"AD0" => DATA <= x"20"; when x"AD1" => DATA <= x"9E"; when x"AD2" => DATA <= x"DB"; when x"AD3" => DATA <= x"20"; when x"AD4" => DATA <= x"23"; when x"AD5" => DATA <= x"D9"; when x"AD6" => DATA <= x"20"; when x"AD7" => DATA <= x"F1"; when x"AD8" => DATA <= x"DC"; when x"AD9" => DATA <= x"20"; when x"ADA" => DATA <= x"9E"; when x"ADB" => DATA <= x"DB"; when x"ADC" => DATA <= x"20"; when x"ADD" => DATA <= x"86"; when x"ADE" => DATA <= x"D6"; when x"ADF" => DATA <= x"F0"; when x"AE0" => DATA <= x"CC"; when x"AE1" => DATA <= x"20"; when x"AE2" => DATA <= x"04"; when x"AE3" => DATA <= x"D8"; when x"AE4" => DATA <= x"F0"; when x"AE5" => DATA <= x"C1"; when x"AE6" => DATA <= x"A5"; when x"AE7" => DATA <= x"57"; when x"AE8" => DATA <= x"45"; when x"AE9" => DATA <= x"5F"; when x"AEA" => DATA <= x"85"; when x"AEB" => DATA <= x"57"; when x"AEC" => DATA <= x"38"; when x"AED" => DATA <= x"A5"; when x"AEE" => DATA <= x"59"; when x"AEF" => DATA <= x"E5"; when x"AF0" => DATA <= x"61"; when x"AF1" => DATA <= x"85"; when x"AF2" => DATA <= x"59"; when x"AF3" => DATA <= x"B0"; when x"AF4" => DATA <= x"02"; when x"AF5" => DATA <= x"C6"; when x"AF6" => DATA <= x"58"; when x"AF7" => DATA <= x"18"; when x"AF8" => DATA <= x"A5"; when x"AF9" => DATA <= x"59"; when x"AFA" => DATA <= x"69"; when x"AFB" => DATA <= x"81"; when x"AFC" => DATA <= x"85"; when x"AFD" => DATA <= x"59"; when x"AFE" => DATA <= x"90"; when x"AFF" => DATA <= x"02"; when x"B00" => DATA <= x"E6"; when x"B01" => DATA <= x"58"; when x"B02" => DATA <= x"A2"; when x"B03" => DATA <= x"05"; when x"B04" => DATA <= x"B5"; when x"B05" => DATA <= x"59"; when x"B06" => DATA <= x"95"; when x"B07" => DATA <= x"66"; when x"B08" => DATA <= x"CA"; when x"B09" => DATA <= x"D0"; when x"B0A" => DATA <= x"F9"; when x"B0B" => DATA <= x"46"; when x"B0C" => DATA <= x"67"; when x"B0D" => DATA <= x"66"; when x"B0E" => DATA <= x"68"; when x"B0F" => DATA <= x"66"; when x"B10" => DATA <= x"69"; when x"B11" => DATA <= x"66"; when x"B12" => DATA <= x"6A"; when x"B13" => DATA <= x"66"; when x"B14" => DATA <= x"6B"; when x"B15" => DATA <= x"20"; when x"B16" => DATA <= x"FB"; when x"B17" => DATA <= x"D6"; when x"B18" => DATA <= x"A2"; when x"B19" => DATA <= x"27"; when x"B1A" => DATA <= x"A5"; when x"B1B" => DATA <= x"67"; when x"B1C" => DATA <= x"C5"; when x"B1D" => DATA <= x"62"; when x"B1E" => DATA <= x"D0"; when x"B1F" => DATA <= x"16"; when x"B20" => DATA <= x"A5"; when x"B21" => DATA <= x"68"; when x"B22" => DATA <= x"C5"; when x"B23" => DATA <= x"63"; when x"B24" => DATA <= x"D0"; when x"B25" => DATA <= x"10"; when x"B26" => DATA <= x"A5"; when x"B27" => DATA <= x"69"; when x"B28" => DATA <= x"C5"; when x"B29" => DATA <= x"64"; when x"B2A" => DATA <= x"D0"; when x"B2B" => DATA <= x"0A"; when x"B2C" => DATA <= x"A5"; when x"B2D" => DATA <= x"6A"; when x"B2E" => DATA <= x"C5"; when x"B2F" => DATA <= x"65"; when x"B30" => DATA <= x"D0"; when x"B31" => DATA <= x"04"; when x"B32" => DATA <= x"A5"; when x"B33" => DATA <= x"6B"; when x"B34" => DATA <= x"C5"; when x"B35" => DATA <= x"66"; when x"B36" => DATA <= x"90"; when x"B37" => DATA <= x"24"; when x"B38" => DATA <= x"A5"; when x"B39" => DATA <= x"6B"; when x"B3A" => DATA <= x"E5"; when x"B3B" => DATA <= x"66"; when x"B3C" => DATA <= x"85"; when x"B3D" => DATA <= x"6B"; when x"B3E" => DATA <= x"A5"; when x"B3F" => DATA <= x"6A"; when x"B40" => DATA <= x"E5"; when x"B41" => DATA <= x"65"; when x"B42" => DATA <= x"85"; when x"B43" => DATA <= x"6A"; when x"B44" => DATA <= x"A5"; when x"B45" => DATA <= x"69"; when x"B46" => DATA <= x"E5"; when x"B47" => DATA <= x"64"; when x"B48" => DATA <= x"85"; when x"B49" => DATA <= x"69"; when x"B4A" => DATA <= x"A5"; when x"B4B" => DATA <= x"68"; when x"B4C" => DATA <= x"E5"; when x"B4D" => DATA <= x"63"; when x"B4E" => DATA <= x"85"; when x"B4F" => DATA <= x"68"; when x"B50" => DATA <= x"A5"; when x"B51" => DATA <= x"67"; when x"B52" => DATA <= x"E5"; when x"B53" => DATA <= x"62"; when x"B54" => DATA <= x"85"; when x"B55" => DATA <= x"67"; when x"B56" => DATA <= x"A5"; when x"B57" => DATA <= x"5E"; when x"B58" => DATA <= x"09"; when x"B59" => DATA <= x"01"; when x"B5A" => DATA <= x"85"; when x"B5B" => DATA <= x"5E"; when x"B5C" => DATA <= x"20"; when x"B5D" => DATA <= x"CD"; when x"B5E" => DATA <= x"D6"; when x"B5F" => DATA <= x"06"; when x"B60" => DATA <= x"6B"; when x"B61" => DATA <= x"26"; when x"B62" => DATA <= x"6A"; when x"B63" => DATA <= x"26"; when x"B64" => DATA <= x"69"; when x"B65" => DATA <= x"26"; when x"B66" => DATA <= x"68"; when x"B67" => DATA <= x"26"; when x"B68" => DATA <= x"67"; when x"B69" => DATA <= x"CA"; when x"B6A" => DATA <= x"D0"; when x"B6B" => DATA <= x"AE"; when x"B6C" => DATA <= x"4C"; when x"B6D" => DATA <= x"98"; when x"B6E" => DATA <= x"DA"; when x"B6F" => DATA <= x"20"; when x"B70" => DATA <= x"EB"; when x"B71" => DATA <= x"D0"; when x"B72" => DATA <= x"20"; when x"B73" => DATA <= x"86"; when x"B74" => DATA <= x"D6"; when x"B75" => DATA <= x"F0"; when x"B76" => DATA <= x"26"; when x"B77" => DATA <= x"10"; when x"B78" => DATA <= x"01"; when x"B79" => DATA <= x"00"; when x"B7A" => DATA <= x"20"; when x"B7B" => DATA <= x"31"; when x"B7C" => DATA <= x"D8"; when x"B7D" => DATA <= x"A5"; when x"B7E" => DATA <= x"59"; when x"B7F" => DATA <= x"4A"; when x"B80" => DATA <= x"69"; when x"B81" => DATA <= x"40"; when x"B82" => DATA <= x"85"; when x"B83" => DATA <= x"59"; when x"B84" => DATA <= x"A9"; when x"B85" => DATA <= x"05"; when x"B86" => DATA <= x"85"; when x"B87" => DATA <= x"6E"; when x"B88" => DATA <= x"20"; when x"B89" => DATA <= x"27"; when x"B8A" => DATA <= x"D8"; when x"B8B" => DATA <= x"20"; when x"B8C" => DATA <= x"AA"; when x"B8D" => DATA <= x"DB"; when x"B8E" => DATA <= x"20"; when x"B8F" => DATA <= x"B6"; when x"B90" => DATA <= x"DA"; when x"B91" => DATA <= x"20"; when x"B92" => DATA <= x"A2"; when x"B93" => DATA <= x"DB"; when x"B94" => DATA <= x"20"; when x"B95" => DATA <= x"3C"; when x"B96" => DATA <= x"D9"; when x"B97" => DATA <= x"C6"; when x"B98" => DATA <= x"59"; when x"B99" => DATA <= x"C6"; when x"B9A" => DATA <= x"6E"; when x"B9B" => DATA <= x"D0"; when x"B9C" => DATA <= x"EB"; when x"B9D" => DATA <= x"60"; when x"B9E" => DATA <= x"A9"; when x"B9F" => DATA <= x"D4"; when x"BA0" => DATA <= x"D0"; when x"BA1" => DATA <= x"0A"; when x"BA2" => DATA <= x"A9"; when x"BA3" => DATA <= x"CA"; when x"BA4" => DATA <= x"D0"; when x"BA5" => DATA <= x"06"; when x"BA6" => DATA <= x"A9"; when x"BA7" => DATA <= x"CF"; when x"BA8" => DATA <= x"D0"; when x"BA9" => DATA <= x"02"; when x"BAA" => DATA <= x"A9"; when x"BAB" => DATA <= x"C5"; when x"BAC" => DATA <= x"85"; when x"BAD" => DATA <= x"6F"; when x"BAE" => DATA <= x"A9"; when x"BAF" => DATA <= x"03"; when x"BB0" => DATA <= x"85"; when x"BB1" => DATA <= x"70"; when x"BB2" => DATA <= x"60"; when x"BB3" => DATA <= x"20"; when x"BB4" => DATA <= x"EB"; when x"BB5" => DATA <= x"D0"; when x"BB6" => DATA <= x"20"; when x"BB7" => DATA <= x"86"; when x"BB8" => DATA <= x"D6"; when x"BB9" => DATA <= x"F0"; when x"BBA" => DATA <= x"02"; when x"BBB" => DATA <= x"10"; when x"BBC" => DATA <= x"01"; when x"BBD" => DATA <= x"00"; when x"BBE" => DATA <= x"A5"; when x"BBF" => DATA <= x"59"; when x"BC0" => DATA <= x"48"; when x"BC1" => DATA <= x"A9"; when x"BC2" => DATA <= x"81"; when x"BC3" => DATA <= x"85"; when x"BC4" => DATA <= x"59"; when x"BC5" => DATA <= x"20"; when x"BC6" => DATA <= x"C7"; when x"BC7" => DATA <= x"D8"; when x"BC8" => DATA <= x"A9"; when x"BC9" => DATA <= x"C0"; when x"BCA" => DATA <= x"85"; when x"BCB" => DATA <= x"62"; when x"BCC" => DATA <= x"A9"; when x"BCD" => DATA <= x"81"; when x"BCE" => DATA <= x"85"; when x"BCF" => DATA <= x"61"; when x"BD0" => DATA <= x"85"; when x"BD1" => DATA <= x"5F"; when x"BD2" => DATA <= x"20"; when x"BD3" => DATA <= x"41"; when x"BD4" => DATA <= x"D9"; when x"BD5" => DATA <= x"E6"; when x"BD6" => DATA <= x"59"; when x"BD7" => DATA <= x"A9"; when x"BD8" => DATA <= x"FE"; when x"BD9" => DATA <= x"A0"; when x"BDA" => DATA <= x"DB"; when x"BDB" => DATA <= x"20"; when x"BDC" => DATA <= x"27"; when x"BDD" => DATA <= x"DC"; when x"BDE" => DATA <= x"20"; when x"BDF" => DATA <= x"31"; when x"BE0" => DATA <= x"D8"; when x"BE1" => DATA <= x"68"; when x"BE2" => DATA <= x"38"; when x"BE3" => DATA <= x"E9"; when x"BE4" => DATA <= x"81"; when x"BE5" => DATA <= x"20"; when x"BE6" => DATA <= x"B2"; when x"BE7" => DATA <= x"D7"; when x"BE8" => DATA <= x"A9"; when x"BE9" => DATA <= x"F9"; when x"BEA" => DATA <= x"85"; when x"BEB" => DATA <= x"6F"; when x"BEC" => DATA <= x"A9"; when x"BED" => DATA <= x"DB"; when x"BEE" => DATA <= x"85"; when x"BEF" => DATA <= x"70"; when x"BF0" => DATA <= x"20"; when x"BF1" => DATA <= x"45"; when x"BF2" => DATA <= x"DA"; when x"BF3" => DATA <= x"20"; when x"BF4" => DATA <= x"AA"; when x"BF5" => DATA <= x"DB"; when x"BF6" => DATA <= x"4C"; when x"BF7" => DATA <= x"3C"; when x"BF8" => DATA <= x"D9"; when x"BF9" => DATA <= x"80"; when x"BFA" => DATA <= x"31"; when x"BFB" => DATA <= x"72"; when x"BFC" => DATA <= x"17"; when x"BFD" => DATA <= x"F8"; when x"BFE" => DATA <= x"07"; when x"BFF" => DATA <= x"85"; when x"C00" => DATA <= x"17"; when x"C01" => DATA <= x"6E"; when x"C02" => DATA <= x"D4"; when x"C03" => DATA <= x"85"; when x"C04" => DATA <= x"80"; when x"C05" => DATA <= x"28"; when x"C06" => DATA <= x"C7"; when x"C07" => DATA <= x"12"; when x"C08" => DATA <= x"A0"; when x"C09" => DATA <= x"84"; when x"C0A" => DATA <= x"70"; when x"C0B" => DATA <= x"4E"; when x"C0C" => DATA <= x"5F"; when x"C0D" => DATA <= x"F2"; when x"C0E" => DATA <= x"81"; when x"C0F" => DATA <= x"00"; when x"C10" => DATA <= x"00"; when x"C11" => DATA <= x"FE"; when x"C12" => DATA <= x"EF"; when x"C13" => DATA <= x"84"; when x"C14" => DATA <= x"0F"; when x"C15" => DATA <= x"FF"; when x"C16" => DATA <= x"DA"; when x"C17" => DATA <= x"E1"; when x"C18" => DATA <= x"81"; when x"C19" => DATA <= x"7F"; when x"C1A" => DATA <= x"FF"; when x"C1B" => DATA <= x"FF"; when x"C1C" => DATA <= x"93"; when x"C1D" => DATA <= x"82"; when x"C1E" => DATA <= x"40"; when x"C1F" => DATA <= x"00"; when x"C20" => DATA <= x"00"; when x"C21" => DATA <= x"0C"; when x"C22" => DATA <= x"7F"; when x"C23" => DATA <= x"4F"; when x"C24" => DATA <= x"99"; when x"C25" => DATA <= x"1F"; when x"C26" => DATA <= x"65"; when x"C27" => DATA <= x"85"; when x"C28" => DATA <= x"71"; when x"C29" => DATA <= x"84"; when x"C2A" => DATA <= x"72"; when x"C2B" => DATA <= x"20"; when x"C2C" => DATA <= x"31"; when x"C2D" => DATA <= x"D8"; when x"C2E" => DATA <= x"A0"; when x"C2F" => DATA <= x"00"; when x"C30" => DATA <= x"B1"; when x"C31" => DATA <= x"71"; when x"C32" => DATA <= x"85"; when x"C33" => DATA <= x"6C"; when x"C34" => DATA <= x"E6"; when x"C35" => DATA <= x"71"; when x"C36" => DATA <= x"D0"; when x"C37" => DATA <= x"02"; when x"C38" => DATA <= x"E6"; when x"C39" => DATA <= x"72"; when x"C3A" => DATA <= x"A5"; when x"C3B" => DATA <= x"71"; when x"C3C" => DATA <= x"85"; when x"C3D" => DATA <= x"6F"; when x"C3E" => DATA <= x"A5"; when x"C3F" => DATA <= x"72"; when x"C40" => DATA <= x"85"; when x"C41" => DATA <= x"70"; when x"C42" => DATA <= x"20"; when x"C43" => DATA <= x"E5"; when x"C44" => DATA <= x"D1"; when x"C45" => DATA <= x"20"; when x"C46" => DATA <= x"AA"; when x"C47" => DATA <= x"DB"; when x"C48" => DATA <= x"20"; when x"C49" => DATA <= x"B6"; when x"C4A" => DATA <= x"DA"; when x"C4B" => DATA <= x"18"; when x"C4C" => DATA <= x"A5"; when x"C4D" => DATA <= x"71"; when x"C4E" => DATA <= x"69"; when x"C4F" => DATA <= x"05"; when x"C50" => DATA <= x"85"; when x"C51" => DATA <= x"71"; when x"C52" => DATA <= x"85"; when x"C53" => DATA <= x"6F"; when x"C54" => DATA <= x"A5"; when x"C55" => DATA <= x"72"; when x"C56" => DATA <= x"69"; when x"C57" => DATA <= x"00"; when x"C58" => DATA <= x"85"; when x"C59" => DATA <= x"72"; when x"C5A" => DATA <= x"85"; when x"C5B" => DATA <= x"70"; when x"C5C" => DATA <= x"20"; when x"C5D" => DATA <= x"3C"; when x"C5E" => DATA <= x"D9"; when x"C5F" => DATA <= x"C6"; when x"C60" => DATA <= x"6C"; when x"C61" => DATA <= x"D0"; when x"C62" => DATA <= x"E2"; when x"C63" => DATA <= x"60"; when x"C64" => DATA <= x"20"; when x"C65" => DATA <= x"EB"; when x"C66" => DATA <= x"D0"; when x"C67" => DATA <= x"20"; when x"C68" => DATA <= x"86"; when x"C69" => DATA <= x"D6"; when x"C6A" => DATA <= x"F0"; when x"C6B" => DATA <= x"0D"; when x"C6C" => DATA <= x"10"; when x"C6D" => DATA <= x"0C"; when x"C6E" => DATA <= x"A9"; when x"C6F" => DATA <= x"00"; when x"C70" => DATA <= x"85"; when x"C71" => DATA <= x"57"; when x"C72" => DATA <= x"20"; when x"C73" => DATA <= x"7A"; when x"C74" => DATA <= x"DC"; when x"C75" => DATA <= x"A9"; when x"C76" => DATA <= x"80"; when x"C77" => DATA <= x"85"; when x"C78" => DATA <= x"57"; when x"C79" => DATA <= x"60"; when x"C7A" => DATA <= x"A5"; when x"C7B" => DATA <= x"59"; when x"C7C" => DATA <= x"C9"; when x"C7D" => DATA <= x"81"; when x"C7E" => DATA <= x"90"; when x"C7F" => DATA <= x"0C"; when x"C80" => DATA <= x"20"; when x"C81" => DATA <= x"AE"; when x"C82" => DATA <= x"DA"; when x"C83" => DATA <= x"20"; when x"C84" => DATA <= x"8C"; when x"C85" => DATA <= x"DC"; when x"C86" => DATA <= x"20"; when x"C87" => DATA <= x"93"; when x"C88" => DATA <= x"DD"; when x"C89" => DATA <= x"4C"; when x"C8A" => DATA <= x"39"; when x"C8B" => DATA <= x"D9"; when x"C8C" => DATA <= x"A5"; when x"C8D" => DATA <= x"59"; when x"C8E" => DATA <= x"C9"; when x"C8F" => DATA <= x"73"; when x"C90" => DATA <= x"90"; when x"C91" => DATA <= x"E7"; when x"C92" => DATA <= x"20"; when x"C93" => DATA <= x"2C"; when x"C94" => DATA <= x"D8"; when x"C95" => DATA <= x"20"; when x"C96" => DATA <= x"C7"; when x"C97" => DATA <= x"D8"; when x"C98" => DATA <= x"A9"; when x"C99" => DATA <= x"80"; when x"C9A" => DATA <= x"85"; when x"C9B" => DATA <= x"61"; when x"C9C" => DATA <= x"85"; when x"C9D" => DATA <= x"62"; when x"C9E" => DATA <= x"85"; when x"C9F" => DATA <= x"5F"; when x"CA0" => DATA <= x"20"; when x"CA1" => DATA <= x"41"; when x"CA2" => DATA <= x"D9"; when x"CA3" => DATA <= x"A9"; when x"CA4" => DATA <= x"B0"; when x"CA5" => DATA <= x"A0"; when x"CA6" => DATA <= x"DC"; when x"CA7" => DATA <= x"20"; when x"CA8" => DATA <= x"27"; when x"CA9" => DATA <= x"DC"; when x"CAA" => DATA <= x"20"; when x"CAB" => DATA <= x"A6"; when x"CAC" => DATA <= x"DB"; when x"CAD" => DATA <= x"4C"; when x"CAE" => DATA <= x"45"; when x"CAF" => DATA <= x"DA"; when x"CB0" => DATA <= x"09"; when x"CB1" => DATA <= x"85"; when x"CB2" => DATA <= x"A3"; when x"CB3" => DATA <= x"59"; when x"CB4" => DATA <= x"E8"; when x"CB5" => DATA <= x"67"; when x"CB6" => DATA <= x"80"; when x"CB7" => DATA <= x"1C"; when x"CB8" => DATA <= x"9D"; when x"CB9" => DATA <= x"07"; when x"CBA" => DATA <= x"36"; when x"CBB" => DATA <= x"80"; when x"CBC" => DATA <= x"57"; when x"CBD" => DATA <= x"BB"; when x"CBE" => DATA <= x"78"; when x"CBF" => DATA <= x"DF"; when x"CC0" => DATA <= x"80"; when x"CC1" => DATA <= x"CA"; when x"CC2" => DATA <= x"9A"; when x"CC3" => DATA <= x"0E"; when x"CC4" => DATA <= x"83"; when x"CC5" => DATA <= x"84"; when x"CC6" => DATA <= x"8C"; when x"CC7" => DATA <= x"BB"; when x"CC8" => DATA <= x"CA"; when x"CC9" => DATA <= x"6E"; when x"CCA" => DATA <= x"81"; when x"CCB" => DATA <= x"95"; when x"CCC" => DATA <= x"96"; when x"CCD" => DATA <= x"06"; when x"CCE" => DATA <= x"DE"; when x"CCF" => DATA <= x"81"; when x"CD0" => DATA <= x"0A"; when x"CD1" => DATA <= x"C7"; when x"CD2" => DATA <= x"6C"; when x"CD3" => DATA <= x"52"; when x"CD4" => DATA <= x"7F"; when x"CD5" => DATA <= x"7D"; when x"CD6" => DATA <= x"AD"; when x"CD7" => DATA <= x"90"; when x"CD8" => DATA <= x"A1"; when x"CD9" => DATA <= x"82"; when x"CDA" => DATA <= x"FB"; when x"CDB" => DATA <= x"62"; when x"CDC" => DATA <= x"57"; when x"CDD" => DATA <= x"2F"; when x"CDE" => DATA <= x"80"; when x"CDF" => DATA <= x"6D"; when x"CE0" => DATA <= x"63"; when x"CE1" => DATA <= x"38"; when x"CE2" => DATA <= x"2C"; when x"CE3" => DATA <= x"20"; when x"CE4" => DATA <= x"EB"; when x"CE5" => DATA <= x"D0"; when x"CE6" => DATA <= x"20"; when x"CE7" => DATA <= x"24"; when x"CE8" => DATA <= x"DD"; when x"CE9" => DATA <= x"E6"; when x"CEA" => DATA <= x"6E"; when x"CEB" => DATA <= x"4C"; when x"CEC" => DATA <= x"F4"; when x"CED" => DATA <= x"DC"; when x"CEE" => DATA <= x"20"; when x"CEF" => DATA <= x"EB"; when x"CF0" => DATA <= x"D0"; when x"CF1" => DATA <= x"20"; when x"CF2" => DATA <= x"24"; when x"CF3" => DATA <= x"DD"; when x"CF4" => DATA <= x"46"; when x"CF5" => DATA <= x"6E"; when x"CF6" => DATA <= x"90"; when x"CF7" => DATA <= x"03"; when x"CF8" => DATA <= x"20"; when x"CF9" => DATA <= x"86"; when x"CFA" => DATA <= x"DC"; when x"CFB" => DATA <= x"46"; when x"CFC" => DATA <= x"6E"; when x"CFD" => DATA <= x"90"; when x"CFE" => DATA <= x"06"; when x"CFF" => DATA <= x"20"; when x"D00" => DATA <= x"05"; when x"D01" => DATA <= x"DD"; when x"D02" => DATA <= x"4C"; when x"D03" => DATA <= x"BF"; when x"D04" => DATA <= x"D1"; when x"D05" => DATA <= x"20"; when x"D06" => DATA <= x"2C"; when x"D07" => DATA <= x"D8"; when x"D08" => DATA <= x"20"; when x"D09" => DATA <= x"93"; when x"D0A" => DATA <= x"DD"; when x"D0B" => DATA <= x"20"; when x"D0C" => DATA <= x"04"; when x"D0D" => DATA <= x"D8"; when x"D0E" => DATA <= x"C6"; when x"D0F" => DATA <= x"61"; when x"D10" => DATA <= x"A9"; when x"D11" => DATA <= x"80"; when x"D12" => DATA <= x"85"; when x"D13" => DATA <= x"5F"; when x"D14" => DATA <= x"20"; when x"D15" => DATA <= x"41"; when x"D16" => DATA <= x"D9"; when x"D17" => DATA <= x"A9"; when x"D18" => DATA <= x"A6"; when x"D19" => DATA <= x"A0"; when x"D1A" => DATA <= x"DD"; when x"D1B" => DATA <= x"20"; when x"D1C" => DATA <= x"27"; when x"D1D" => DATA <= x"DC"; when x"D1E" => DATA <= x"20"; when x"D1F" => DATA <= x"A6"; when x"D20" => DATA <= x"DB"; when x"D21" => DATA <= x"4C"; when x"D22" => DATA <= x"45"; when x"D23" => DATA <= x"DA"; when x"D24" => DATA <= x"A5"; when x"D25" => DATA <= x"59"; when x"D26" => DATA <= x"C9"; when x"D27" => DATA <= x"98"; when x"D28" => DATA <= x"B0"; when x"D29" => DATA <= x"54"; when x"D2A" => DATA <= x"20"; when x"D2B" => DATA <= x"31"; when x"D2C" => DATA <= x"D8"; when x"D2D" => DATA <= x"20"; when x"D2E" => DATA <= x"93"; when x"D2F" => DATA <= x"DD"; when x"D30" => DATA <= x"20"; when x"D31" => DATA <= x"DC"; when x"D32" => DATA <= x"DA"; when x"D33" => DATA <= x"20"; when x"D34" => DATA <= x"9A"; when x"D35" => DATA <= x"D8"; when x"D36" => DATA <= x"A5"; when x"D37" => DATA <= x"5D"; when x"D38" => DATA <= x"85"; when x"D39" => DATA <= x"6E"; when x"D3A" => DATA <= x"05"; when x"D3B" => DATA <= x"5C"; when x"D3C" => DATA <= x"05"; when x"D3D" => DATA <= x"5B"; when x"D3E" => DATA <= x"05"; when x"D3F" => DATA <= x"5A"; when x"D40" => DATA <= x"F0"; when x"D41" => DATA <= x"3E"; when x"D42" => DATA <= x"20"; when x"D43" => DATA <= x"AC"; when x"D44" => DATA <= x"D2"; when x"D45" => DATA <= x"20"; when x"D46" => DATA <= x"27"; when x"D47" => DATA <= x"D8"; when x"D48" => DATA <= x"20"; when x"D49" => DATA <= x"86"; when x"D4A" => DATA <= x"DD"; when x"D4B" => DATA <= x"20"; when x"D4C" => DATA <= x"45"; when x"D4D" => DATA <= x"DA"; when x"D4E" => DATA <= x"20"; when x"D4F" => DATA <= x"AA"; when x"D50" => DATA <= x"DB"; when x"D51" => DATA <= x"20"; when x"D52" => DATA <= x"3C"; when x"D53" => DATA <= x"D9"; when x"D54" => DATA <= x"20"; when x"D55" => DATA <= x"3D"; when x"D56" => DATA <= x"D8"; when x"D57" => DATA <= x"20"; when x"D58" => DATA <= x"A2"; when x"D59" => DATA <= x"DB"; when x"D5A" => DATA <= x"20"; when x"D5B" => DATA <= x"E5"; when x"D5C" => DATA <= x"D1"; when x"D5D" => DATA <= x"20"; when x"D5E" => DATA <= x"8A"; when x"D5F" => DATA <= x"DD"; when x"D60" => DATA <= x"20"; when x"D61" => DATA <= x"45"; when x"D62" => DATA <= x"DA"; when x"D63" => DATA <= x"20"; when x"D64" => DATA <= x"AA"; when x"D65" => DATA <= x"DB"; when x"D66" => DATA <= x"20"; when x"D67" => DATA <= x"3C"; when x"D68" => DATA <= x"D9"; when x"D69" => DATA <= x"A5"; when x"D6A" => DATA <= x"57"; when x"D6B" => DATA <= x"10"; when x"D6C" => DATA <= x"12"; when x"D6D" => DATA <= x"20"; when x"D6E" => DATA <= x"8A"; when x"D6F" => DATA <= x"DD"; when x"D70" => DATA <= x"20"; when x"D71" => DATA <= x"33"; when x"D72" => DATA <= x"D9"; when x"D73" => DATA <= x"20"; when x"D74" => DATA <= x"86"; when x"D75" => DATA <= x"DD"; when x"D76" => DATA <= x"20"; when x"D77" => DATA <= x"33"; when x"D78" => DATA <= x"D9"; when x"D79" => DATA <= x"C6"; when x"D7A" => DATA <= x"6E"; when x"D7B" => DATA <= x"4C"; when x"D7C" => DATA <= x"69"; when x"D7D" => DATA <= x"DD"; when x"D7E" => DATA <= x"00"; when x"D7F" => DATA <= x"60"; when x"D80" => DATA <= x"20"; when x"D81" => DATA <= x"DA"; when x"D82" => DATA <= x"D2"; when x"D83" => DATA <= x"4C"; when x"D84" => DATA <= x"69"; when x"D85" => DATA <= x"DD"; when x"D86" => DATA <= x"A9"; when x"D87" => DATA <= x"97"; when x"D88" => DATA <= x"D0"; when x"D89" => DATA <= x"02"; when x"D8A" => DATA <= x"A9"; when x"D8B" => DATA <= x"9C"; when x"D8C" => DATA <= x"85"; when x"D8D" => DATA <= x"6F"; when x"D8E" => DATA <= x"A9"; when x"D8F" => DATA <= x"DD"; when x"D90" => DATA <= x"85"; when x"D91" => DATA <= x"70"; when x"D92" => DATA <= x"60"; when x"D93" => DATA <= x"A9"; when x"D94" => DATA <= x"A1"; when x"D95" => DATA <= x"D0"; when x"D96" => DATA <= x"F5"; when x"D97" => DATA <= x"81"; when x"D98" => DATA <= x"C9"; when x"D99" => DATA <= x"00"; when x"D9A" => DATA <= x"00"; when x"D9B" => DATA <= x"00"; when x"D9C" => DATA <= x"75"; when x"D9D" => DATA <= x"FD"; when x"D9E" => DATA <= x"AA"; when x"D9F" => DATA <= x"22"; when x"DA0" => DATA <= x"17"; when x"DA1" => DATA <= x"81"; when x"DA2" => DATA <= x"49"; when x"DA3" => DATA <= x"0F"; when x"DA4" => DATA <= x"DA"; when x"DA5" => DATA <= x"A2"; when x"DA6" => DATA <= x"08"; when x"DA7" => DATA <= x"84"; when x"DA8" => DATA <= x"04"; when x"DA9" => DATA <= x"C7"; when x"DAA" => DATA <= x"3C"; when x"DAB" => DATA <= x"FB"; when x"DAC" => DATA <= x"81"; when x"DAD" => DATA <= x"E0"; when x"DAE" => DATA <= x"4F"; when x"DAF" => DATA <= x"5D"; when x"DB0" => DATA <= x"AD"; when x"DB1" => DATA <= x"82"; when x"DB2" => DATA <= x"80"; when x"DB3" => DATA <= x"00"; when x"DB4" => DATA <= x"69"; when x"DB5" => DATA <= x"B8"; when x"DB6" => DATA <= x"82"; when x"DB7" => DATA <= x"5B"; when x"DB8" => DATA <= x"CF"; when x"DB9" => DATA <= x"1D"; when x"DBA" => DATA <= x"B5"; when x"DBB" => DATA <= x"82"; when x"DBC" => DATA <= x"BF"; when x"DBD" => DATA <= x"CE"; when x"DBE" => DATA <= x"82"; when x"DBF" => DATA <= x"1E"; when x"DC0" => DATA <= x"82"; when x"DC1" => DATA <= x"45"; when x"DC2" => DATA <= x"44"; when x"DC3" => DATA <= x"7F"; when x"DC4" => DATA <= x"32"; when x"DC5" => DATA <= x"7F"; when x"DC6" => DATA <= x"62"; when x"DC7" => DATA <= x"44"; when x"DC8" => DATA <= x"5A"; when x"DC9" => DATA <= x"D2"; when x"DCA" => DATA <= x"83"; when x"DCB" => DATA <= x"82"; when x"DCC" => DATA <= x"14"; when x"DCD" => DATA <= x"8A"; when x"DCE" => DATA <= x"27"; when x"DCF" => DATA <= x"80"; when x"DD0" => DATA <= x"66"; when x"DD1" => DATA <= x"7B"; when x"DD2" => DATA <= x"21"; when x"DD3" => DATA <= x"4D"; when x"DD4" => DATA <= x"20"; when x"DD5" => DATA <= x"EB"; when x"DD6" => DATA <= x"D0"; when x"DD7" => DATA <= x"A5"; when x"DD8" => DATA <= x"59"; when x"DD9" => DATA <= x"C9"; when x"DDA" => DATA <= x"87"; when x"DDB" => DATA <= x"90"; when x"DDC" => DATA <= x"10"; when x"DDD" => DATA <= x"D0"; when x"DDE" => DATA <= x"06"; when x"DDF" => DATA <= x"A5"; when x"DE0" => DATA <= x"5A"; when x"DE1" => DATA <= x"C9"; when x"DE2" => DATA <= x"B3"; when x"DE3" => DATA <= x"90"; when x"DE4" => DATA <= x"08"; when x"DE5" => DATA <= x"A5"; when x"DE6" => DATA <= x"57"; when x"DE7" => DATA <= x"10"; when x"DE8" => DATA <= x"03"; when x"DE9" => DATA <= x"4C"; when x"DEA" => DATA <= x"A4"; when x"DEB" => DATA <= x"DA"; when x"DEC" => DATA <= x"00"; when x"DED" => DATA <= x"A5"; when x"DEE" => DATA <= x"59"; when x"DEF" => DATA <= x"C9"; when x"DF0" => DATA <= x"80"; when x"DF1" => DATA <= x"90"; when x"DF2" => DATA <= x"29"; when x"DF3" => DATA <= x"20"; when x"DF4" => DATA <= x"9A"; when x"DF5" => DATA <= x"D8"; when x"DF6" => DATA <= x"20"; when x"DF7" => DATA <= x"E2"; when x"DF8" => DATA <= x"D8"; when x"DF9" => DATA <= x"A5"; when x"DFA" => DATA <= x"5D"; when x"DFB" => DATA <= x"85"; when x"DFC" => DATA <= x"6E"; when x"DFD" => DATA <= x"20"; when x"DFE" => DATA <= x"13"; when x"DFF" => DATA <= x"D9"; when x"E00" => DATA <= x"20"; when x"E01" => DATA <= x"1C"; when x"E02" => DATA <= x"DE"; when x"E03" => DATA <= x"20"; when x"E04" => DATA <= x"2C"; when x"E05" => DATA <= x"D8"; when x"E06" => DATA <= x"A9"; when x"E07" => DATA <= x"23"; when x"E08" => DATA <= x"85"; when x"E09" => DATA <= x"6F"; when x"E0A" => DATA <= x"A9"; when x"E0B" => DATA <= x"DE"; when x"E0C" => DATA <= x"85"; when x"E0D" => DATA <= x"70"; when x"E0E" => DATA <= x"20"; when x"E0F" => DATA <= x"E5"; when x"E10" => DATA <= x"D1"; when x"E11" => DATA <= x"A5"; when x"E12" => DATA <= x"6E"; when x"E13" => DATA <= x"20"; when x"E14" => DATA <= x"51"; when x"E15" => DATA <= x"DE"; when x"E16" => DATA <= x"20"; when x"E17" => DATA <= x"A6"; when x"E18" => DATA <= x"DB"; when x"E19" => DATA <= x"4C"; when x"E1A" => DATA <= x"45"; when x"E1B" => DATA <= x"DA"; when x"E1C" => DATA <= x"A9"; when x"E1D" => DATA <= x"28"; when x"E1E" => DATA <= x"A0"; when x"E1F" => DATA <= x"DE"; when x"E20" => DATA <= x"4C"; when x"E21" => DATA <= x"27"; when x"E22" => DATA <= x"DC"; when x"E23" => DATA <= x"82"; when x"E24" => DATA <= x"2D"; when x"E25" => DATA <= x"F8"; when x"E26" => DATA <= x"54"; when x"E27" => DATA <= x"58"; when x"E28" => DATA <= x"07"; when x"E29" => DATA <= x"83"; when x"E2A" => DATA <= x"E0"; when x"E2B" => DATA <= x"20"; when x"E2C" => DATA <= x"86"; when x"E2D" => DATA <= x"5B"; when x"E2E" => DATA <= x"82"; when x"E2F" => DATA <= x"80"; when x"E30" => DATA <= x"53"; when x"E31" => DATA <= x"93"; when x"E32" => DATA <= x"B8"; when x"E33" => DATA <= x"83"; when x"E34" => DATA <= x"20"; when x"E35" => DATA <= x"00"; when x"E36" => DATA <= x"06"; when x"E37" => DATA <= x"A1"; when x"E38" => DATA <= x"82"; when x"E39" => DATA <= x"00"; when x"E3A" => DATA <= x"00"; when x"E3B" => DATA <= x"21"; when x"E3C" => DATA <= x"63"; when x"E3D" => DATA <= x"82"; when x"E3E" => DATA <= x"C0"; when x"E3F" => DATA <= x"00"; when x"E40" => DATA <= x"00"; when x"E41" => DATA <= x"02"; when x"E42" => DATA <= x"82"; when x"E43" => DATA <= x"80"; when x"E44" => DATA <= x"00"; when x"E45" => DATA <= x"00"; when x"E46" => DATA <= x"0C"; when x"E47" => DATA <= x"81"; when x"E48" => DATA <= x"00"; when x"E49" => DATA <= x"00"; when x"E4A" => DATA <= x"00"; when x"E4B" => DATA <= x"00"; when x"E4C" => DATA <= x"81"; when x"E4D" => DATA <= x"00"; when x"E4E" => DATA <= x"00"; when x"E4F" => DATA <= x"00"; when x"E50" => DATA <= x"00"; when x"E51" => DATA <= x"AA"; when x"E52" => DATA <= x"10"; when x"E53" => DATA <= x"09"; when x"E54" => DATA <= x"CA"; when x"E55" => DATA <= x"8A"; when x"E56" => DATA <= x"49"; when x"E57" => DATA <= x"FF"; when x"E58" => DATA <= x"48"; when x"E59" => DATA <= x"20"; when x"E5A" => DATA <= x"AE"; when x"E5B" => DATA <= x"DA"; when x"E5C" => DATA <= x"68"; when x"E5D" => DATA <= x"48"; when x"E5E" => DATA <= x"20"; when x"E5F" => DATA <= x"31"; when x"E60" => DATA <= x"D8"; when x"E61" => DATA <= x"20"; when x"E62" => DATA <= x"8D"; when x"E63" => DATA <= x"DE"; when x"E64" => DATA <= x"68"; when x"E65" => DATA <= x"F0"; when x"E66" => DATA <= x"0A"; when x"E67" => DATA <= x"38"; when x"E68" => DATA <= x"E9"; when x"E69" => DATA <= x"01"; when x"E6A" => DATA <= x"48"; when x"E6B" => DATA <= x"20"; when x"E6C" => DATA <= x"45"; when x"E6D" => DATA <= x"DA"; when x"E6E" => DATA <= x"4C"; when x"E6F" => DATA <= x"64"; when x"E70" => DATA <= x"DE"; when x"E71" => DATA <= x"60"; when x"E72" => DATA <= x"20"; when x"E73" => DATA <= x"EB"; when x"E74" => DATA <= x"D0"; when x"E75" => DATA <= x"A5"; when x"E76" => DATA <= x"57"; when x"E77" => DATA <= x"10"; when x"E78" => DATA <= x"0A"; when x"E79" => DATA <= x"A9"; when x"E7A" => DATA <= x"00"; when x"E7B" => DATA <= x"85"; when x"E7C" => DATA <= x"57"; when x"E7D" => DATA <= x"20"; when x"E7E" => DATA <= x"83"; when x"E7F" => DATA <= x"DE"; when x"E80" => DATA <= x"4C"; when x"E81" => DATA <= x"BF"; when x"E82" => DATA <= x"D1"; when x"E83" => DATA <= x"A5"; when x"E84" => DATA <= x"59"; when x"E85" => DATA <= x"C9"; when x"E86" => DATA <= x"81"; when x"E87" => DATA <= x"90"; when x"E88" => DATA <= x"33"; when x"E89" => DATA <= x"C9"; when x"E8A" => DATA <= x"85"; when x"E8B" => DATA <= x"90"; when x"E8C" => DATA <= x"0B"; when x"E8D" => DATA <= x"20"; when x"E8E" => DATA <= x"A4"; when x"E8F" => DATA <= x"DA"; when x"E90" => DATA <= x"A0"; when x"E91" => DATA <= x"80"; when x"E92" => DATA <= x"84"; when x"E93" => DATA <= x"5A"; when x"E94" => DATA <= x"C8"; when x"E95" => DATA <= x"84"; when x"E96" => DATA <= x"59"; when x"E97" => DATA <= x"60"; when x"E98" => DATA <= x"E6"; when x"E99" => DATA <= x"59"; when x"E9A" => DATA <= x"A9"; when x"E9B" => DATA <= x"80"; when x"E9C" => DATA <= x"85"; when x"E9D" => DATA <= x"57"; when x"E9E" => DATA <= x"20"; when x"E9F" => DATA <= x"D7"; when x"EA0" => DATA <= x"DD"; when x"EA1" => DATA <= x"20"; when x"EA2" => DATA <= x"31"; when x"EA3" => DATA <= x"D8"; when x"EA4" => DATA <= x"20"; when x"EA5" => DATA <= x"8D"; when x"EA6" => DATA <= x"DE"; when x"EA7" => DATA <= x"20"; when x"EA8" => DATA <= x"3C"; when x"EA9" => DATA <= x"D9"; when x"EAA" => DATA <= x"20"; when x"EAB" => DATA <= x"27"; when x"EAC" => DATA <= x"D8"; when x"EAD" => DATA <= x"20"; when x"EAE" => DATA <= x"8D"; when x"EAF" => DATA <= x"DE"; when x"EB0" => DATA <= x"20"; when x"EB1" => DATA <= x"AA"; when x"EB2" => DATA <= x"DB"; when x"EB3" => DATA <= x"20"; when x"EB4" => DATA <= x"33"; when x"EB5" => DATA <= x"D9"; when x"EB6" => DATA <= x"20"; when x"EB7" => DATA <= x"A2"; when x"EB8" => DATA <= x"DB"; when x"EB9" => DATA <= x"4C"; when x"EBA" => DATA <= x"DC"; when x"EBB" => DATA <= x"DA"; when x"EBC" => DATA <= x"20"; when x"EBD" => DATA <= x"2C"; when x"EBE" => DATA <= x"D8"; when x"EBF" => DATA <= x"20"; when x"EC0" => DATA <= x"8D"; when x"EC1" => DATA <= x"DE"; when x"EC2" => DATA <= x"C6"; when x"EC3" => DATA <= x"59"; when x"EC4" => DATA <= x"20"; when x"EC5" => DATA <= x"33"; when x"EC6" => DATA <= x"D9"; when x"EC7" => DATA <= x"A9"; when x"EC8" => DATA <= x"D4"; when x"EC9" => DATA <= x"A0"; when x"ECA" => DATA <= x"DE"; when x"ECB" => DATA <= x"20"; when x"ECC" => DATA <= x"27"; when x"ECD" => DATA <= x"DC"; when x"ECE" => DATA <= x"20"; when x"ECF" => DATA <= x"A6"; when x"ED0" => DATA <= x"DB"; when x"ED1" => DATA <= x"4C"; when x"ED2" => DATA <= x"45"; when x"ED3" => DATA <= x"DA"; when x"ED4" => DATA <= x"08"; when x"ED5" => DATA <= x"7E"; when x"ED6" => DATA <= x"85"; when x"ED7" => DATA <= x"51"; when x"ED8" => DATA <= x"B3"; when x"ED9" => DATA <= x"0C"; when x"EDA" => DATA <= x"86"; when x"EDB" => DATA <= x"DE"; when x"EDC" => DATA <= x"B0"; when x"EDD" => DATA <= x"7D"; when x"EDE" => DATA <= x"73"; when x"EDF" => DATA <= x"7C"; when x"EE0" => DATA <= x"23"; when x"EE1" => DATA <= x"D8"; when x"EE2" => DATA <= x"E9"; when x"EE3" => DATA <= x"9A"; when x"EE4" => DATA <= x"87"; when x"EE5" => DATA <= x"34"; when x"EE6" => DATA <= x"82"; when x"EE7" => DATA <= x"1D"; when x"EE8" => DATA <= x"80"; when x"EE9" => DATA <= x"81"; when x"EEA" => DATA <= x"9A"; when x"EEB" => DATA <= x"20"; when x"EEC" => DATA <= x"6C"; when x"EED" => DATA <= x"ED"; when x"EEE" => DATA <= x"81"; when x"EEF" => DATA <= x"BD"; when x"EF0" => DATA <= x"32"; when x"EF1" => DATA <= x"34"; when x"EF2" => DATA <= x"2E"; when x"EF3" => DATA <= x"7F"; when x"EF4" => DATA <= x"5D"; when x"EF5" => DATA <= x"46"; when x"EF6" => DATA <= x"87"; when x"EF7" => DATA <= x"B4"; when x"EF8" => DATA <= x"82"; when x"EF9" => DATA <= x"68"; when x"EFA" => DATA <= x"3E"; when x"EFB" => DATA <= x"43"; when x"EFC" => DATA <= x"F7"; when x"EFD" => DATA <= x"80"; when x"EFE" => DATA <= x"6C"; when x"EFF" => DATA <= x"9A"; when x"F00" => DATA <= x"9E"; when x"F01" => DATA <= x"BB"; when x"F02" => DATA <= x"20"; when x"F03" => DATA <= x"C8"; when x"F04" => DATA <= x"C3"; when x"F05" => DATA <= x"A5"; when x"F06" => DATA <= x"52"; when x"F07" => DATA <= x"29"; when x"F08" => DATA <= x"03"; when x"F09" => DATA <= x"A8"; when x"F0A" => DATA <= x"B9"; when x"F0B" => DATA <= x"4E"; when x"F0C" => DATA <= x"DF"; when x"F0D" => DATA <= x"8D"; when x"F0E" => DATA <= x"FD"; when x"F0F" => DATA <= x"03"; when x"F10" => DATA <= x"AD"; when x"F11" => DATA <= x"00"; when x"F12" => DATA <= x"B0"; when x"F13" => DATA <= x"29"; when x"F14" => DATA <= x"F0"; when x"F15" => DATA <= x"C9"; when x"F16" => DATA <= x"70"; when x"F17" => DATA <= x"D0"; when x"F18" => DATA <= x"0C"; when x"F19" => DATA <= x"A9"; when x"F1A" => DATA <= x"00"; when x"F1B" => DATA <= x"A8"; when x"F1C" => DATA <= x"99"; when x"F1D" => DATA <= x"00"; when x"F1E" => DATA <= x"86"; when x"F1F" => DATA <= x"99"; when x"F20" => DATA <= x"00"; when x"F21" => DATA <= x"87"; when x"F22" => DATA <= x"88"; when x"F23" => DATA <= x"D0"; when x"F24" => DATA <= x"F7"; when x"F25" => DATA <= x"AD"; when x"F26" => DATA <= x"00"; when x"F27" => DATA <= x"B0"; when x"F28" => DATA <= x"29"; when x"F29" => DATA <= x"DF"; when x"F2A" => DATA <= x"8D"; when x"F2B" => DATA <= x"00"; when x"F2C" => DATA <= x"B0"; when x"F2D" => DATA <= x"2A"; when x"F2E" => DATA <= x"2A"; when x"F2F" => DATA <= x"2A"; when x"F30" => DATA <= x"29"; when x"F31" => DATA <= x"03"; when x"F32" => DATA <= x"A8"; when x"F33" => DATA <= x"B9"; when x"F34" => DATA <= x"42"; when x"F35" => DATA <= x"DF"; when x"F36" => DATA <= x"8D"; when x"F37" => DATA <= x"FE"; when x"F38" => DATA <= x"03"; when x"F39" => DATA <= x"B9"; when x"F3A" => DATA <= x"46"; when x"F3B" => DATA <= x"DF"; when x"F3C" => DATA <= x"8D"; when x"F3D" => DATA <= x"FF"; when x"F3E" => DATA <= x"03"; when x"F3F" => DATA <= x"4C"; when x"F40" => DATA <= x"58"; when x"F41" => DATA <= x"C5"; when x"F42" => DATA <= x"52"; when x"F43" => DATA <= x"70"; when x"F44" => DATA <= x"88"; when x"F45" => DATA <= x"A0"; when x"F46" => DATA <= x"DF"; when x"F47" => DATA <= x"DF"; when x"F48" => DATA <= x"DF"; when x"F49" => DATA <= x"DF"; when x"F4A" => DATA <= x"3F"; when x"F4B" => DATA <= x"CF"; when x"F4C" => DATA <= x"F3"; when x"F4D" => DATA <= x"FC"; when x"F4E" => DATA <= x"00"; when x"F4F" => DATA <= x"55"; when x"F50" => DATA <= x"AA"; when x"F51" => DATA <= x"FF"; when x"F52" => DATA <= x"A5"; when x"F53" => DATA <= x"5B"; when x"F54" => DATA <= x"05"; when x"F55" => DATA <= x"5D"; when x"F56" => DATA <= x"D0"; when x"F57" => DATA <= x"47"; when x"F58" => DATA <= x"A5"; when x"F59" => DATA <= x"5A"; when x"F5A" => DATA <= x"C9"; when x"F5B" => DATA <= x"40"; when x"F5C" => DATA <= x"B0"; when x"F5D" => DATA <= x"41"; when x"F5E" => DATA <= x"4A"; when x"F5F" => DATA <= x"4A"; when x"F60" => DATA <= x"85"; when x"F61" => DATA <= x"5F"; when x"F62" => DATA <= x"A0"; when x"F63" => DATA <= x"00"; when x"F64" => DATA <= x"84"; when x"F65" => DATA <= x"60"; when x"F66" => DATA <= x"A9"; when x"F67" => DATA <= x"3F"; when x"F68" => DATA <= x"38"; when x"F69" => DATA <= x"E5"; when x"F6A" => DATA <= x"5C"; when x"F6B" => DATA <= x"C9"; when x"F6C" => DATA <= x"40"; when x"F6D" => DATA <= x"90"; when x"F6E" => DATA <= x"4F"; when x"F6F" => DATA <= x"60"; when x"F70" => DATA <= x"A5"; when x"F71" => DATA <= x"5B"; when x"F72" => DATA <= x"05"; when x"F73" => DATA <= x"5D"; when x"F74" => DATA <= x"D0"; when x"F75" => DATA <= x"29"; when x"F76" => DATA <= x"A5"; when x"F77" => DATA <= x"5A"; when x"F78" => DATA <= x"30"; when x"F79" => DATA <= x"25"; when x"F7A" => DATA <= x"4A"; when x"F7B" => DATA <= x"4A"; when x"F7C" => DATA <= x"85"; when x"F7D" => DATA <= x"5F"; when x"F7E" => DATA <= x"A9"; when x"F7F" => DATA <= x"3F"; when x"F80" => DATA <= x"38"; when x"F81" => DATA <= x"E5"; when x"F82" => DATA <= x"5C"; when x"F83" => DATA <= x"C9"; when x"F84" => DATA <= x"40"; when x"F85" => DATA <= x"90"; when x"F86" => DATA <= x"30"; when x"F87" => DATA <= x"60"; when x"F88" => DATA <= x"A5"; when x"F89" => DATA <= x"5B"; when x"F8A" => DATA <= x"05"; when x"F8B" => DATA <= x"5D"; when x"F8C" => DATA <= x"D0"; when x"F8D" => DATA <= x"11"; when x"F8E" => DATA <= x"A5"; when x"F8F" => DATA <= x"5A"; when x"F90" => DATA <= x"30"; when x"F91" => DATA <= x"0D"; when x"F92" => DATA <= x"4A"; when x"F93" => DATA <= x"4A"; when x"F94" => DATA <= x"85"; when x"F95" => DATA <= x"5F"; when x"F96" => DATA <= x"A9"; when x"F97" => DATA <= x"5F"; when x"F98" => DATA <= x"38"; when x"F99" => DATA <= x"E5"; when x"F9A" => DATA <= x"5C"; when x"F9B" => DATA <= x"C9"; when x"F9C" => DATA <= x"60"; when x"F9D" => DATA <= x"90"; when x"F9E" => DATA <= x"18"; when x"F9F" => DATA <= x"60"; when x"FA0" => DATA <= x"A5"; when x"FA1" => DATA <= x"5B"; when x"FA2" => DATA <= x"05"; when x"FA3" => DATA <= x"5D"; when x"FA4" => DATA <= x"D0"; when x"FA5" => DATA <= x"F9"; when x"FA6" => DATA <= x"A5"; when x"FA7" => DATA <= x"5A"; when x"FA8" => DATA <= x"30"; when x"FA9" => DATA <= x"F5"; when x"FAA" => DATA <= x"4A"; when x"FAB" => DATA <= x"4A"; when x"FAC" => DATA <= x"85"; when x"FAD" => DATA <= x"5F"; when x"FAE" => DATA <= x"A9"; when x"FAF" => DATA <= x"BF"; when x"FB0" => DATA <= x"38"; when x"FB1" => DATA <= x"E5"; when x"FB2" => DATA <= x"5C"; when x"FB3" => DATA <= x"C9"; when x"FB4" => DATA <= x"C0"; when x"FB5" => DATA <= x"B0"; when x"FB6" => DATA <= x"E8"; when x"FB7" => DATA <= x"A0"; when x"FB8" => DATA <= x"00"; when x"FB9" => DATA <= x"84"; when x"FBA" => DATA <= x"60"; when x"FBB" => DATA <= x"0A"; when x"FBC" => DATA <= x"26"; when x"FBD" => DATA <= x"60"; when x"FBE" => DATA <= x"0A"; when x"FBF" => DATA <= x"26"; when x"FC0" => DATA <= x"60"; when x"FC1" => DATA <= x"0A"; when x"FC2" => DATA <= x"26"; when x"FC3" => DATA <= x"60"; when x"FC4" => DATA <= x"0A"; when x"FC5" => DATA <= x"26"; when x"FC6" => DATA <= x"60"; when x"FC7" => DATA <= x"0A"; when x"FC8" => DATA <= x"26"; when x"FC9" => DATA <= x"60"; when x"FCA" => DATA <= x"65"; when x"FCB" => DATA <= x"5F"; when x"FCC" => DATA <= x"85"; when x"FCD" => DATA <= x"5F"; when x"FCE" => DATA <= x"A5"; when x"FCF" => DATA <= x"60"; when x"FD0" => DATA <= x"69"; when x"FD1" => DATA <= x"80"; when x"FD2" => DATA <= x"85"; when x"FD3" => DATA <= x"60"; when x"FD4" => DATA <= x"A5"; when x"FD5" => DATA <= x"5A"; when x"FD6" => DATA <= x"29"; when x"FD7" => DATA <= x"03"; when x"FD8" => DATA <= x"AA"; when x"FD9" => DATA <= x"BD"; when x"FDA" => DATA <= x"4A"; when x"FDB" => DATA <= x"DF"; when x"FDC" => DATA <= x"A6"; when x"FDD" => DATA <= x"5E"; when x"FDE" => DATA <= x"CA"; when x"FDF" => DATA <= x"F0"; when x"FE0" => DATA <= x"0F"; when x"FE1" => DATA <= x"CA"; when x"FE2" => DATA <= x"F0"; when x"FE3" => DATA <= x"05"; when x"FE4" => DATA <= x"31"; when x"FE5" => DATA <= x"5F"; when x"FE6" => DATA <= x"91"; when x"FE7" => DATA <= x"5F"; when x"FE8" => DATA <= x"60"; when x"FE9" => DATA <= x"49"; when x"FEA" => DATA <= x"FF"; when x"FEB" => DATA <= x"51"; when x"FEC" => DATA <= x"5F"; when x"FED" => DATA <= x"91"; when x"FEE" => DATA <= x"5F"; when x"FEF" => DATA <= x"60"; when x"FF0" => DATA <= x"AA"; when x"FF1" => DATA <= x"31"; when x"FF2" => DATA <= x"5F"; when x"FF3" => DATA <= x"91"; when x"FF4" => DATA <= x"5F"; when x"FF5" => DATA <= x"8A"; when x"FF6" => DATA <= x"49"; when x"FF7" => DATA <= x"FF"; when x"FF8" => DATA <= x"2D"; when x"FF9" => DATA <= x"FD"; when x"FFA" => DATA <= x"03"; when x"FFB" => DATA <= x"11"; when x"FFC" => DATA <= x"5F"; when x"FFD" => DATA <= x"91"; when x"FFE" => DATA <= x"5F"; when x"FFF" => DATA <= x"60"; when others => DATA <= (others => '0'); end case; end process; end RTL;
apache-2.0
0a2b216c524e9d566d34b8acc8e9bc62
0.357929
2.920634
false
false
false
false
hoglet67/AtomFpga
src/common/RAM/RAM_16K.vhd
2
991
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity RAM_16K is port ( clk : in std_logic; we_uP : in std_logic; ce : in std_logic; addr_uP : in std_logic_vector (13 downto 0); D_uP : in std_logic_vector (7 downto 0); Q_uP : out std_logic_vector (7 downto 0)); end RAM_16K; architecture BEHAVIORAL of RAM_16K is type ram_type is array (16383 downto 0) of std_logic_vector (7 downto 0); signal RAM : ram_type := (16383 downto 0 => X"ff"); attribute RAM_STYLE : string; attribute RAM_STYLE of RAM : signal is "BLOCK"; begin process (clk) begin if rising_edge(clk) then if (we_UP = '1' and ce = '1') then RAM(conv_integer(addr_uP(13 downto 0))) <= D_up; end if; Q_up <= RAM(conv_integer(addr_uP(13 downto 0))); end if; end process; end BEHAVIORAL;
apache-2.0
fd18a0aab506ff430a5bfd8e47dbf9a7
0.543895
3.359322
false
false
false
false
hoglet67/AtomFpga
src/common/AVR8/Core/reg_file.vhd
4
10,644
--********************************************************************************************** -- General purpose register file for the AVR Core -- Version 1.4 (Special version for the JTAG OCD) -- Modified 22.04.2004 -- Designed by Ruslan Lepetenok --********************************************************************************************** library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use WORK.SynthCtrlPack.all; -- Synthesis control entity reg_file is port ( --Clock and reset cp2 : in std_logic; cp2en : in std_logic; ireset : in std_logic; reg_rd_in : in std_logic_vector(7 downto 0); reg_rd_out : out std_logic_vector(7 downto 0); reg_rd_adr : in std_logic_vector(4 downto 0); reg_rr_out : out std_logic_vector(7 downto 0); reg_rr_adr : in std_logic_vector(4 downto 0); reg_rd_wr : in std_logic; post_inc : in std_logic; -- POST INCREMENT FOR LD/ST INSTRUCTIONS pre_dec : in std_logic; -- PRE DECREMENT FOR LD/ST INSTRUCTIONS reg_h_wr : in std_logic; reg_h_out : out std_logic_vector(15 downto 0); reg_h_adr : in std_logic_vector(2 downto 0); -- x,y,z reg_z_out : out std_logic_vector(15 downto 0) -- OUTPUT OF R31:R30 FOR LPM/ELPM/IJMP INSTRUCTIONS ); end reg_file; architecture RTL of reg_file is type register_file_type is array(0 to 25) of std_logic_vector(7 downto 0); type register_mux_type is array(0 to 31) of std_logic_vector(7 downto 0); signal register_file : register_file_type; signal r26h : std_logic_vector(7 downto 0); signal r27h : std_logic_vector(7 downto 0); signal r28h : std_logic_vector(7 downto 0); signal r29h : std_logic_vector(7 downto 0); signal r30h : std_logic_vector(7 downto 0); signal r31h : std_logic_vector(7 downto 0); signal register_wr_en : std_logic_vector(31 downto 0); signal sg_rd_decode : std_logic_vector (31 downto 0); signal sg_rr_decode : std_logic_vector (31 downto 0); signal sg_tmp_rd_data : register_mux_type; signal sg_tmp_rr_data : register_mux_type; signal sg_adr16_postinc : std_logic_vector (15 downto 0); signal sg_adr16_predec : std_logic_vector (15 downto 0); signal reg_h_in : std_logic_vector (15 downto 0); signal sg_tmp_h_data : std_logic_vector (15 downto 0); begin write_decode: for i in 0 to 31 generate register_wr_en(i) <= '1' when (i=reg_rd_adr and reg_rd_wr='1') else '0'; end generate; rd_mux_decode: for i in 0 to 31 generate sg_rd_decode(i) <= '1' when (reg_rd_adr=i) else '0'; end generate; rr_mux_decode: for i in 0 to 31 generate sg_rr_decode(i) <= '1' when (reg_rr_adr=i) else '0'; end generate; reg_z_out <= r31h&r30h; -- R31:R30 OUTPUT FOR LPM/ELPM INSTRUCTIONS sg_tmp_rd_data(0) <= register_file(0) when sg_rd_decode(0)='1' else (others=>'0'); read_rd_mux: for i in 1 to 25 generate sg_tmp_rd_data(i) <= register_file(i) when sg_rd_decode(i)='1' else sg_tmp_rd_data(i-1); end generate; sg_tmp_rd_data(26) <= r26h when sg_rd_decode(26)='1' else sg_tmp_rd_data(25); sg_tmp_rd_data(27) <= r27h when sg_rd_decode(27)='1' else sg_tmp_rd_data(26); sg_tmp_rd_data(28) <= r28h when sg_rd_decode(28)='1' else sg_tmp_rd_data(27); sg_tmp_rd_data(29) <= r29h when sg_rd_decode(29)='1' else sg_tmp_rd_data(28); sg_tmp_rd_data(30) <= r30h when sg_rd_decode(30)='1' else sg_tmp_rd_data(29); sg_tmp_rd_data(31) <= r31h when sg_rd_decode(31)='1' else sg_tmp_rd_data(30); reg_rd_out <= sg_tmp_rd_data(31); sg_tmp_rr_data(0) <= register_file(0) when sg_rr_decode(0)='1' else (others=>'0'); read_rr_mux: for i in 1 to 25 generate sg_tmp_rr_data(i) <= register_file(i) when sg_rr_decode(i)='1' else sg_tmp_rr_data(i-1); end generate; sg_tmp_rr_data(26) <= r26h when sg_rr_decode(26)='1' else sg_tmp_rr_data(25); sg_tmp_rr_data(27) <= r27h when sg_rr_decode(27)='1' else sg_tmp_rr_data(26); sg_tmp_rr_data(28) <= r28h when sg_rr_decode(28)='1' else sg_tmp_rr_data(27); sg_tmp_rr_data(29) <= r29h when sg_rr_decode(29)='1' else sg_tmp_rr_data(28); sg_tmp_rr_data(30) <= r30h when sg_rr_decode(30)='1' else sg_tmp_rr_data(29); sg_tmp_rr_data(31) <= r31h when sg_rr_decode(31)='1' else sg_tmp_rr_data(30); reg_rr_out <= sg_tmp_rr_data(31); h_dat_mux_l:for i in 0 to 7 generate sg_tmp_h_data(i) <= (r26h(i) and reg_h_adr(0)) or (r28h(i) and reg_h_adr(1)) or (r30h(i) and reg_h_adr(2)); end generate; h_dat_mux_h:for i in 8 to 15 generate sg_tmp_h_data(i) <= (r27h(i-8) and reg_h_adr(0)) or (r29h(i-8) and reg_h_adr(1)) or (r31h(i-8) and reg_h_adr(2)); end generate; sg_adr16_postinc <= sg_tmp_h_data +1; sg_adr16_predec <= sg_tmp_h_data -1; -- OUTPUT TO THE ADDRESS BUS reg_h_out <= sg_adr16_predec when (pre_dec='1') else -- PREDECREMENT sg_tmp_h_data; -- NO PREDECREMENT -- TO REGISTERS reg_h_in <= sg_adr16_postinc when (post_inc='1') else -- POST INC sg_adr16_predec; -- PRE DEC -- Register file with global reset (for simulation) RegFileWithRst:if CResetRegFile generate R0_R25:process(cp2,ireset) begin if ireset='0' then for i in 0 to 25 loop register_file(i) <= (others =>'0'); end loop; elsif (cp2='1' and cp2'event) then if (cp2en='1') then -- Clock enable for i in 0 to 25 loop if register_wr_en(i)='1' then register_file(i) <= reg_rd_in; end if; end loop; end if; end if; end process; -- R26 (LOW) R26:process(cp2,ireset) begin if ireset='0' then r26h <= (others =>'0'); elsif (cp2='1' and cp2'event) then if (cp2en='1') then -- Clock enable if register_wr_en(26)='1' then r26h <= reg_rd_in; elsif (reg_h_adr(0)='1'and reg_h_wr='1') then r26h <= reg_h_in(7 downto 0); end if; end if; end if; end process; -- R27 (HIGH) R27:process(cp2,ireset) begin if ireset='0' then r27h <= (others =>'0'); elsif (cp2='1' and cp2'event) then if (cp2en='1') then -- Clock enable if register_wr_en(27)='1' then r27h <= reg_rd_in; elsif (reg_h_adr(0)='1'and reg_h_wr='1') then r27h <= reg_h_in(15 downto 8); end if; end if; end if; end process; -- R28 (LOW) R28:process(cp2,ireset) begin if ireset='0' then r28h <= (others =>'0'); elsif (cp2='1' and cp2'event) then if (cp2en='1') then -- Clock enable if register_wr_en(28)='1' then r28h <= reg_rd_in; elsif (reg_h_adr(1)='1'and reg_h_wr='1') then r28h <= reg_h_in(7 downto 0); end if; end if; end if; end process; -- R29 (HIGH) R29:process(cp2,ireset) begin if ireset='0' then r29h <= (others =>'0'); elsif (cp2='1' and cp2'event) then if (cp2en='1') then -- Clock enable if register_wr_en(29)='1' then r29h <= reg_rd_in; elsif (reg_h_adr(1)='1'and reg_h_wr='1') then r29h <= reg_h_in(15 downto 8); end if; end if; end if; end process; -- R30 (LOW) R30:process(cp2,ireset) begin if ireset='0' then r30h <= (others =>'0'); elsif (cp2='1' and cp2'event) then if (cp2en='1') then -- Clock enable if register_wr_en(30)='1' then r30h <= reg_rd_in; elsif (reg_h_adr(2)='1'and reg_h_wr='1') then r30h <= reg_h_in(7 downto 0); end if; end if; end if; end process; -- R31 (HIGH) R31:process(cp2,ireset) begin if ireset='0' then r31h <= (others =>'0'); elsif (cp2='1' and cp2'event) then if (cp2en='1') then -- Clock enable if register_wr_en(31)='1' then r31h <= reg_rd_in; elsif (reg_h_adr(2)='1'and reg_h_wr='1') then r31h <= reg_h_in(15 downto 8); end if; end if; end if; end process; end generate; -- Register file without global reset (for synthesis) RegFileWithoutRst:if not CResetRegFile generate R0_R25:process(cp2) begin if (cp2='1' and cp2'event) then if (cp2en='1') then -- Clock enable for i in 0 to 25 loop if register_wr_en(i)='1' then register_file(i) <= reg_rd_in; end if; end loop; end if; end if; end process; -- R26 (LOW) R26:process(cp2) begin if (cp2='1' and cp2'event) then if (cp2en='1') then -- Clock enable if register_wr_en(26)='1' then r26h <= reg_rd_in; elsif (reg_h_adr(0)='1'and reg_h_wr='1') then r26h <= reg_h_in(7 downto 0); end if; end if; end if; end process; -- R27 (HIGH) R27:process(cp2) begin if (cp2='1' and cp2'event) then if (cp2en='1') then -- Clock enable if register_wr_en(27)='1' then r27h <= reg_rd_in; elsif (reg_h_adr(0)='1'and reg_h_wr='1') then r27h <= reg_h_in(15 downto 8); end if; end if; end if; end process; -- R28 (LOW) R28:process(cp2) begin if (cp2='1' and cp2'event) then if (cp2en='1') then -- Clock enable if register_wr_en(28)='1' then r28h <= reg_rd_in; elsif (reg_h_adr(1)='1'and reg_h_wr='1') then r28h <= reg_h_in(7 downto 0); end if; end if; end if; end process; -- R29 (HIGH) R29:process(cp2) begin if (cp2='1' and cp2'event) then if (cp2en='1') then -- Clock enable if register_wr_en(29)='1' then r29h <= reg_rd_in; elsif (reg_h_adr(1)='1'and reg_h_wr='1') then r29h <= reg_h_in(15 downto 8); end if; end if; end if; end process; -- R30 (LOW) R30:process(cp2) begin if (cp2='1' and cp2'event) then if (cp2en='1') then -- Clock enable if register_wr_en(30)='1' then r30h <= reg_rd_in; elsif (reg_h_adr(2)='1'and reg_h_wr='1') then r30h <= reg_h_in(7 downto 0); end if; end if; end if; end process; -- R31 (HIGH) R31:process(cp2) begin if (cp2='1' and cp2'event) then if (cp2en='1') then -- Clock enable if register_wr_en(31)='1' then r31h <= reg_rd_in; elsif (reg_h_adr(2)='1'and reg_h_wr='1') then r31h <= reg_h_in(15 downto 8); end if; end if; end if; end process; end generate; end RTL;
apache-2.0
8f52366a384175a3fb587d3acd4e8cd1
0.554585
2.689917
false
false
false
false
hoglet67/AtomFpga
src/common/ROM/AtoMMC.vhd
1
148,224
-- generated with romgen v3.0.1r4 by MikeJ truhy and eD library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; library UNISIM; use UNISIM.Vcomponents.all; entity e000 is port ( CLK : in std_logic; ADDR : in std_logic_vector(11 downto 0); DATA : out std_logic_vector(7 downto 0) ); end; architecture RTL of e000 is signal rom_addr : std_logic_vector(11 downto 0); begin p_addr : process(ADDR) begin rom_addr <= (others => '0'); rom_addr(11 downto 0) <= ADDR; end process; p_rom : process begin wait until rising_edge(CLK); DATA <= (others => '0'); case rom_addr is when x"000" => DATA <= x"2C"; when x"001" => DATA <= x"01"; when x"002" => DATA <= x"B0"; when x"003" => DATA <= x"70"; when x"004" => DATA <= x"03"; when x"005" => DATA <= x"4C"; when x"006" => DATA <= x"B2"; when x"007" => DATA <= x"C2"; when x"008" => DATA <= x"98"; when x"009" => DATA <= x"48"; when x"00A" => DATA <= x"8A"; when x"00B" => DATA <= x"48"; when x"00C" => DATA <= x"20"; when x"00D" => DATA <= x"97"; when x"00E" => DATA <= x"E0"; when x"00F" => DATA <= x"A8"; when x"010" => DATA <= x"A2"; when x"011" => DATA <= x"00"; when x"012" => DATA <= x"8E"; when x"013" => DATA <= x"CA"; when x"014" => DATA <= x"03"; when x"015" => DATA <= x"A9"; when x"016" => DATA <= x"2B"; when x"017" => DATA <= x"8D"; when x"018" => DATA <= x"0B"; when x"019" => DATA <= x"80"; when x"01A" => DATA <= x"BD"; when x"01B" => DATA <= x"D0"; when x"01C" => DATA <= x"EF"; when x"01D" => DATA <= x"29"; when x"01E" => DATA <= x"BF"; when x"01F" => DATA <= x"9D"; when x"020" => DATA <= x"0D"; when x"021" => DATA <= x"80"; when x"022" => DATA <= x"E8"; when x"023" => DATA <= x"C9"; when x"024" => DATA <= x"20"; when x"025" => DATA <= x"D0"; when x"026" => DATA <= x"F3"; when x"027" => DATA <= x"2C"; when x"028" => DATA <= x"02"; when x"029" => DATA <= x"B0"; when x"02A" => DATA <= x"70"; when x"02B" => DATA <= x"22"; when x"02C" => DATA <= x"CA"; when x"02D" => DATA <= x"29"; when x"02E" => DATA <= x"BF"; when x"02F" => DATA <= x"9D"; when x"030" => DATA <= x"0D"; when x"031" => DATA <= x"80"; when x"032" => DATA <= x"E8"; when x"033" => DATA <= x"BD"; when x"034" => DATA <= x"D0"; when x"035" => DATA <= x"EF"; when x"036" => DATA <= x"C9"; when x"037" => DATA <= x"0D"; when x"038" => DATA <= x"D0"; when x"039" => DATA <= x"F3"; when x"03A" => DATA <= x"98"; when x"03B" => DATA <= x"20"; when x"03C" => DATA <= x"6F"; when x"03D" => DATA <= x"E0"; when x"03E" => DATA <= x"A0"; when x"03F" => DATA <= x"00"; when x"040" => DATA <= x"BD"; when x"041" => DATA <= x"3D"; when x"042" => DATA <= x"E9"; when x"043" => DATA <= x"29"; when x"044" => DATA <= x"BF"; when x"045" => DATA <= x"99"; when x"046" => DATA <= x"1C"; when x"047" => DATA <= x"80"; when x"048" => DATA <= x"E8"; when x"049" => DATA <= x"C8"; when x"04A" => DATA <= x"C0"; when x"04B" => DATA <= x"04"; when x"04C" => DATA <= x"D0"; when x"04D" => DATA <= x"F2"; when x"04E" => DATA <= x"20"; when x"04F" => DATA <= x"8B"; when x"050" => DATA <= x"E0"; when x"051" => DATA <= x"A9"; when x"052" => DATA <= x"F0"; when x"053" => DATA <= x"20"; when x"054" => DATA <= x"48"; when x"055" => DATA <= x"E6"; when x"056" => DATA <= x"0A"; when x"057" => DATA <= x"4D"; when x"058" => DATA <= x"01"; when x"059" => DATA <= x"B0"; when x"05A" => DATA <= x"10"; when x"05B" => DATA <= x"0A"; when x"05C" => DATA <= x"A9"; when x"05D" => DATA <= x"AF"; when x"05E" => DATA <= x"8D"; when x"05F" => DATA <= x"0A"; when x"060" => DATA <= x"02"; when x"061" => DATA <= x"A9"; when x"062" => DATA <= x"E0"; when x"063" => DATA <= x"8D"; when x"064" => DATA <= x"0B"; when x"065" => DATA <= x"02"; when x"066" => DATA <= x"68"; when x"067" => DATA <= x"AA"; when x"068" => DATA <= x"68"; when x"069" => DATA <= x"A8"; when x"06A" => DATA <= x"4C"; when x"06B" => DATA <= x"B2"; when x"06C" => DATA <= x"C2"; when x"06D" => DATA <= x"68"; when x"06E" => DATA <= x"40"; when x"06F" => DATA <= x"09"; when x"070" => DATA <= x"08"; when x"071" => DATA <= x"85"; when x"072" => DATA <= x"AE"; when x"073" => DATA <= x"A9"; when x"074" => DATA <= x"FC"; when x"075" => DATA <= x"18"; when x"076" => DATA <= x"69"; when x"077" => DATA <= x"04"; when x"078" => DATA <= x"46"; when x"079" => DATA <= x"AE"; when x"07A" => DATA <= x"90"; when x"07B" => DATA <= x"FA"; when x"07C" => DATA <= x"AA"; when x"07D" => DATA <= x"60"; when x"07E" => DATA <= x"A2"; when x"07F" => DATA <= x"00"; when x"080" => DATA <= x"BD"; when x"081" => DATA <= x"D0"; when x"082" => DATA <= x"EF"; when x"083" => DATA <= x"20"; when x"084" => DATA <= x"F4"; when x"085" => DATA <= x"FF"; when x"086" => DATA <= x"E8"; when x"087" => DATA <= x"E0"; when x"088" => DATA <= x"10"; when x"089" => DATA <= x"D0"; when x"08A" => DATA <= x"F5"; when x"08B" => DATA <= x"A2"; when x"08C" => DATA <= x"17"; when x"08D" => DATA <= x"BD"; when x"08E" => DATA <= x"4D"; when x"08F" => DATA <= x"E9"; when x"090" => DATA <= x"9D"; when x"091" => DATA <= x"04"; when x"092" => DATA <= x"02"; when x"093" => DATA <= x"CA"; when x"094" => DATA <= x"10"; when x"095" => DATA <= x"F7"; when x"096" => DATA <= x"60"; when x"097" => DATA <= x"A9"; when x"098" => DATA <= x"FE"; when x"099" => DATA <= x"20"; when x"09A" => DATA <= x"48"; when x"09B" => DATA <= x"E6"; when x"09C" => DATA <= x"C9"; when x"09D" => DATA <= x"AA"; when x"09E" => DATA <= x"D0"; when x"09F" => DATA <= x"F7"; when x"0A0" => DATA <= x"A9"; when x"0A1" => DATA <= x"FE"; when x"0A2" => DATA <= x"20"; when x"0A3" => DATA <= x"48"; when x"0A4" => DATA <= x"E6"; when x"0A5" => DATA <= x"C9"; when x"0A6" => DATA <= x"55"; when x"0A7" => DATA <= x"D0"; when x"0A8" => DATA <= x"EE"; when x"0A9" => DATA <= x"A9"; when x"0AA" => DATA <= x"80"; when x"0AB" => DATA <= x"20"; when x"0AC" => DATA <= x"48"; when x"0AD" => DATA <= x"E6"; when x"0AE" => DATA <= x"60"; when x"0AF" => DATA <= x"08"; when x"0B0" => DATA <= x"D8"; when x"0B1" => DATA <= x"86"; when x"0B2" => DATA <= x"E4"; when x"0B3" => DATA <= x"84"; when x"0B4" => DATA <= x"E5"; when x"0B5" => DATA <= x"AE"; when x"0B6" => DATA <= x"CA"; when x"0B7" => DATA <= x"03"; when x"0B8" => DATA <= x"BD"; when x"0B9" => DATA <= x"65"; when x"0BA" => DATA <= x"E9"; when x"0BB" => DATA <= x"C9"; when x"0BC" => DATA <= x"0D"; when x"0BD" => DATA <= x"F0"; when x"0BE" => DATA <= x"0A"; when x"0BF" => DATA <= x"E8"; when x"0C0" => DATA <= x"8E"; when x"0C1" => DATA <= x"CA"; when x"0C2" => DATA <= x"03"; when x"0C3" => DATA <= x"A6"; when x"0C4" => DATA <= x"E4"; when x"0C5" => DATA <= x"A4"; when x"0C6" => DATA <= x"E5"; when x"0C7" => DATA <= x"28"; when x"0C8" => DATA <= x"60"; when x"0C9" => DATA <= x"A9"; when x"0CA" => DATA <= x"94"; when x"0CB" => DATA <= x"8D"; when x"0CC" => DATA <= x"0A"; when x"0CD" => DATA <= x"02"; when x"0CE" => DATA <= x"A9"; when x"0CF" => DATA <= x"FE"; when x"0D0" => DATA <= x"8D"; when x"0D1" => DATA <= x"0B"; when x"0D2" => DATA <= x"02"; when x"0D3" => DATA <= x"A9"; when x"0D4" => DATA <= x"0D"; when x"0D5" => DATA <= x"48"; when x"0D6" => DATA <= x"4C"; when x"0D7" => DATA <= x"5C"; when x"0D8" => DATA <= x"FE"; when x"0D9" => DATA <= x"A2"; when x"0DA" => DATA <= x"FF"; when x"0DB" => DATA <= x"D8"; when x"0DC" => DATA <= x"A0"; when x"0DD" => DATA <= x"00"; when x"0DE" => DATA <= x"20"; when x"0DF" => DATA <= x"76"; when x"0E0" => DATA <= x"F8"; when x"0E1" => DATA <= x"88"; when x"0E2" => DATA <= x"C8"; when x"0E3" => DATA <= x"E8"; when x"0E4" => DATA <= x"BD"; when x"0E5" => DATA <= x"6C"; when x"0E6" => DATA <= x"E9"; when x"0E7" => DATA <= x"30"; when x"0E8" => DATA <= x"18"; when x"0E9" => DATA <= x"D9"; when x"0EA" => DATA <= x"00"; when x"0EB" => DATA <= x"01"; when x"0EC" => DATA <= x"F0"; when x"0ED" => DATA <= x"F4"; when x"0EE" => DATA <= x"CA"; when x"0EF" => DATA <= x"E8"; when x"0F0" => DATA <= x"BD"; when x"0F1" => DATA <= x"6C"; when x"0F2" => DATA <= x"E9"; when x"0F3" => DATA <= x"10"; when x"0F4" => DATA <= x"FA"; when x"0F5" => DATA <= x"E8"; when x"0F6" => DATA <= x"B9"; when x"0F7" => DATA <= x"00"; when x"0F8" => DATA <= x"01"; when x"0F9" => DATA <= x"C9"; when x"0FA" => DATA <= x"2E"; when x"0FB" => DATA <= x"D0"; when x"0FC" => DATA <= x"DF"; when x"0FD" => DATA <= x"C8"; when x"0FE" => DATA <= x"CA"; when x"0FF" => DATA <= x"B0"; when x"100" => DATA <= x"E3"; when x"101" => DATA <= x"84"; when x"102" => DATA <= x"9A"; when x"103" => DATA <= x"A4"; when x"104" => DATA <= x"03"; when x"105" => DATA <= x"84"; when x"106" => DATA <= x"D5"; when x"107" => DATA <= x"A4"; when x"108" => DATA <= x"05"; when x"109" => DATA <= x"84"; when x"10A" => DATA <= x"D6"; when x"10B" => DATA <= x"A4"; when x"10C" => DATA <= x"06"; when x"10D" => DATA <= x"84"; when x"10E" => DATA <= x"D7"; when x"10F" => DATA <= x"A0"; when x"110" => DATA <= x"00"; when x"111" => DATA <= x"84"; when x"112" => DATA <= x"05"; when x"113" => DATA <= x"A0"; when x"114" => DATA <= x"01"; when x"115" => DATA <= x"84"; when x"116" => DATA <= x"06"; when x"117" => DATA <= x"A4"; when x"118" => DATA <= x"9A"; when x"119" => DATA <= x"84"; when x"11A" => DATA <= x"03"; when x"11B" => DATA <= x"85"; when x"11C" => DATA <= x"53"; when x"11D" => DATA <= x"BD"; when x"11E" => DATA <= x"6D"; when x"11F" => DATA <= x"E9"; when x"120" => DATA <= x"85"; when x"121" => DATA <= x"52"; when x"122" => DATA <= x"A2"; when x"123" => DATA <= x"00"; when x"124" => DATA <= x"20"; when x"125" => DATA <= x"38"; when x"126" => DATA <= x"E1"; when x"127" => DATA <= x"A4"; when x"128" => DATA <= x"D6"; when x"129" => DATA <= x"84"; when x"12A" => DATA <= x"05"; when x"12B" => DATA <= x"A4"; when x"12C" => DATA <= x"D7"; when x"12D" => DATA <= x"84"; when x"12E" => DATA <= x"06"; when x"12F" => DATA <= x"A4"; when x"130" => DATA <= x"D5"; when x"131" => DATA <= x"84"; when x"132" => DATA <= x"03"; when x"133" => DATA <= x"A9"; when x"134" => DATA <= x"0D"; when x"135" => DATA <= x"91"; when x"136" => DATA <= x"05"; when x"137" => DATA <= x"60"; when x"138" => DATA <= x"6C"; when x"139" => DATA <= x"52"; when x"13A" => DATA <= x"00"; when x"13B" => DATA <= x"A9"; when x"13C" => DATA <= x"00"; when x"13D" => DATA <= x"8D"; when x"13E" => DATA <= x"CD"; when x"13F" => DATA <= x"03"; when x"140" => DATA <= x"A9"; when x"141" => DATA <= x"0D"; when x"142" => DATA <= x"8D"; when x"143" => DATA <= x"40"; when x"144" => DATA <= x"01"; when x"145" => DATA <= x"20"; when x"146" => DATA <= x"76"; when x"147" => DATA <= x"F8"; when x"148" => DATA <= x"C9"; when x"149" => DATA <= x"0D"; when x"14A" => DATA <= x"F0"; when x"14B" => DATA <= x"2D"; when x"14C" => DATA <= x"C9"; when x"14D" => DATA <= x"40"; when x"14E" => DATA <= x"F0"; when x"14F" => DATA <= x"1B"; when x"150" => DATA <= x"A2"; when x"151" => DATA <= x"00"; when x"152" => DATA <= x"9D"; when x"153" => DATA <= x"40"; when x"154" => DATA <= x"01"; when x"155" => DATA <= x"C9"; when x"156" => DATA <= x"0D"; when x"157" => DATA <= x"F0"; when x"158" => DATA <= x"20"; when x"159" => DATA <= x"C9"; when x"15A" => DATA <= x"20"; when x"15B" => DATA <= x"F0"; when x"15C" => DATA <= x"07"; when x"15D" => DATA <= x"C8"; when x"15E" => DATA <= x"B9"; when x"15F" => DATA <= x"00"; when x"160" => DATA <= x"01"; when x"161" => DATA <= x"E8"; when x"162" => DATA <= x"D0"; when x"163" => DATA <= x"EE"; when x"164" => DATA <= x"A9"; when x"165" => DATA <= x"0D"; when x"166" => DATA <= x"9D"; when x"167" => DATA <= x"40"; when x"168" => DATA <= x"01"; when x"169" => DATA <= x"D0"; when x"16A" => DATA <= x"DA"; when x"16B" => DATA <= x"C8"; when x"16C" => DATA <= x"B9"; when x"16D" => DATA <= x"00"; when x"16E" => DATA <= x"01"; when x"16F" => DATA <= x"C9"; when x"170" => DATA <= x"0D"; when x"171" => DATA <= x"F0"; when x"172" => DATA <= x"06"; when x"173" => DATA <= x"8D"; when x"174" => DATA <= x"CD"; when x"175" => DATA <= x"03"; when x"176" => DATA <= x"C8"; when x"177" => DATA <= x"D0"; when x"178" => DATA <= x"CC"; when x"179" => DATA <= x"20"; when x"17A" => DATA <= x"50"; when x"17B" => DATA <= x"E5"; when x"17C" => DATA <= x"A9"; when x"17D" => DATA <= x"00"; when x"17E" => DATA <= x"20"; when x"17F" => DATA <= x"48"; when x"180" => DATA <= x"E6"; when x"181" => DATA <= x"20"; when x"182" => DATA <= x"A7"; when x"183" => DATA <= x"E6"; when x"184" => DATA <= x"A9"; when x"185" => DATA <= x"01"; when x"186" => DATA <= x"20"; when x"187" => DATA <= x"48"; when x"188" => DATA <= x"E6"; when x"189" => DATA <= x"20"; when x"18A" => DATA <= x"A7"; when x"18B" => DATA <= x"E6"; when x"18C" => DATA <= x"C9"; when x"18D" => DATA <= x"40"; when x"18E" => DATA <= x"D0"; when x"18F" => DATA <= x"01"; when x"190" => DATA <= x"60"; when x"191" => DATA <= x"20"; when x"192" => DATA <= x"83"; when x"193" => DATA <= x"E6"; when x"194" => DATA <= x"20"; when x"195" => DATA <= x"73"; when x"196" => DATA <= x"E6"; when x"197" => DATA <= x"AD"; when x"198" => DATA <= x"02"; when x"199" => DATA <= x"B4"; when x"19A" => DATA <= x"29"; when x"19B" => DATA <= x"02"; when x"19C" => DATA <= x"D0"; when x"19D" => DATA <= x"1B"; when x"19E" => DATA <= x"AD"; when x"19F" => DATA <= x"40"; when x"1A0" => DATA <= x"01"; when x"1A1" => DATA <= x"A0"; when x"1A2" => DATA <= x"00"; when x"1A3" => DATA <= x"AE"; when x"1A4" => DATA <= x"CD"; when x"1A5" => DATA <= x"03"; when x"1A6" => DATA <= x"F0"; when x"1A7" => DATA <= x"05"; when x"1A8" => DATA <= x"EC"; when x"1A9" => DATA <= x"40"; when x"1AA" => DATA <= x"01"; when x"1AB" => DATA <= x"D0"; when x"1AC" => DATA <= x"D7"; when x"1AD" => DATA <= x"20"; when x"1AE" => DATA <= x"F4"; when x"1AF" => DATA <= x"FF"; when x"1B0" => DATA <= x"C8"; when x"1B1" => DATA <= x"B9"; when x"1B2" => DATA <= x"40"; when x"1B3" => DATA <= x"01"; when x"1B4" => DATA <= x"D0"; when x"1B5" => DATA <= x"F7"; when x"1B6" => DATA <= x"20"; when x"1B7" => DATA <= x"ED"; when x"1B8" => DATA <= x"FF"; when x"1B9" => DATA <= x"2C"; when x"1BA" => DATA <= x"02"; when x"1BB" => DATA <= x"B0"; when x"1BC" => DATA <= x"50"; when x"1BD" => DATA <= x"FB"; when x"1BE" => DATA <= x"AD"; when x"1BF" => DATA <= x"01"; when x"1C0" => DATA <= x"B0"; when x"1C1" => DATA <= x"2A"; when x"1C2" => DATA <= x"90"; when x"1C3" => DATA <= x"F5"; when x"1C4" => DATA <= x"2A"; when x"1C5" => DATA <= x"90"; when x"1C6" => DATA <= x"F2"; when x"1C7" => DATA <= x"2A"; when x"1C8" => DATA <= x"B0"; when x"1C9" => DATA <= x"BA"; when x"1CA" => DATA <= x"4C"; when x"1CB" => DATA <= x"ED"; when x"1CC" => DATA <= x"FF"; when x"1CD" => DATA <= x"60"; when x"1CE" => DATA <= x"20"; when x"1CF" => DATA <= x"76"; when x"1D0" => DATA <= x"F8"; when x"1D1" => DATA <= x"D0"; when x"1D2" => DATA <= x"03"; when x"1D3" => DATA <= x"4C"; when x"1D4" => DATA <= x"7D"; when x"1D5" => DATA <= x"FA"; when x"1D6" => DATA <= x"20"; when x"1D7" => DATA <= x"39"; when x"1D8" => DATA <= x"E7"; when x"1D9" => DATA <= x"20"; when x"1DA" => DATA <= x"44"; when x"1DB" => DATA <= x"F8"; when x"1DC" => DATA <= x"20"; when x"1DD" => DATA <= x"76"; when x"1DE" => DATA <= x"FA"; when x"1DF" => DATA <= x"A2"; when x"1E0" => DATA <= x"C9"; when x"1E1" => DATA <= x"20"; when x"1E2" => DATA <= x"4F"; when x"1E3" => DATA <= x"F8"; when x"1E4" => DATA <= x"20"; when x"1E5" => DATA <= x"50"; when x"1E6" => DATA <= x"E5"; when x"1E7" => DATA <= x"A9"; when x"1E8" => DATA <= x"02"; when x"1E9" => DATA <= x"20"; when x"1EA" => DATA <= x"48"; when x"1EB" => DATA <= x"E6"; when x"1EC" => DATA <= x"4C"; when x"1ED" => DATA <= x"A7"; when x"1EE" => DATA <= x"E6"; when x"1EF" => DATA <= x"60"; when x"1F0" => DATA <= x"A9"; when x"1F1" => DATA <= x"A0"; when x"1F2" => DATA <= x"85"; when x"1F3" => DATA <= x"CE"; when x"1F4" => DATA <= x"4C"; when x"1F5" => DATA <= x"02"; when x"1F6" => DATA <= x"E2"; when x"1F7" => DATA <= x"A9"; when x"1F8" => DATA <= x"A2"; when x"1F9" => DATA <= x"85"; when x"1FA" => DATA <= x"CE"; when x"1FB" => DATA <= x"4C"; when x"1FC" => DATA <= x"02"; when x"1FD" => DATA <= x"E2"; when x"1FE" => DATA <= x"A9"; when x"1FF" => DATA <= x"F0"; when x"200" => DATA <= x"85"; when x"201" => DATA <= x"CE"; when x"202" => DATA <= x"A2"; when x"203" => DATA <= x"CB"; when x"204" => DATA <= x"20"; when x"205" => DATA <= x"93"; when x"206" => DATA <= x"F8"; when x"207" => DATA <= x"D0"; when x"208" => DATA <= x"0B"; when x"209" => DATA <= x"A5"; when x"20A" => DATA <= x"CE"; when x"20B" => DATA <= x"20"; when x"20C" => DATA <= x"48"; when x"20D" => DATA <= x"E6"; when x"20E" => DATA <= x"20"; when x"20F" => DATA <= x"02"; when x"210" => DATA <= x"F8"; when x"211" => DATA <= x"4C"; when x"212" => DATA <= x"ED"; when x"213" => DATA <= x"FF"; when x"214" => DATA <= x"A5"; when x"215" => DATA <= x"CB"; when x"216" => DATA <= x"8D"; when x"217" => DATA <= x"01"; when x"218" => DATA <= x"B4"; when x"219" => DATA <= x"20"; when x"21A" => DATA <= x"6B"; when x"21B" => DATA <= x"E6"; when x"21C" => DATA <= x"20"; when x"21D" => DATA <= x"47"; when x"21E" => DATA <= x"E6"; when x"21F" => DATA <= x"A6"; when x"220" => DATA <= x"CE"; when x"221" => DATA <= x"E8"; when x"222" => DATA <= x"8A"; when x"223" => DATA <= x"8D"; when x"224" => DATA <= x"00"; when x"225" => DATA <= x"B4"; when x"226" => DATA <= x"20"; when x"227" => DATA <= x"6B"; when x"228" => DATA <= x"E6"; when x"229" => DATA <= x"60"; when x"22A" => DATA <= x"A2"; when x"22B" => DATA <= x"CF"; when x"22C" => DATA <= x"20"; when x"22D" => DATA <= x"65"; when x"22E" => DATA <= x"FA"; when x"22F" => DATA <= x"A2"; when x"230" => DATA <= x"D1"; when x"231" => DATA <= x"20"; when x"232" => DATA <= x"65"; when x"233" => DATA <= x"FA"; when x"234" => DATA <= x"A0"; when x"235" => DATA <= x"FF"; when x"236" => DATA <= x"84"; when x"237" => DATA <= x"C9"; when x"238" => DATA <= x"84"; when x"239" => DATA <= x"CA"; when x"23A" => DATA <= x"C8"; when x"23B" => DATA <= x"F0"; when x"23C" => DATA <= x"09"; when x"23D" => DATA <= x"A9"; when x"23E" => DATA <= x"00"; when x"23F" => DATA <= x"20"; when x"240" => DATA <= x"59"; when x"241" => DATA <= x"E2"; when x"242" => DATA <= x"E6"; when x"243" => DATA <= x"D0"; when x"244" => DATA <= x"C6"; when x"245" => DATA <= x"D2"; when x"246" => DATA <= x"A5"; when x"247" => DATA <= x"D2"; when x"248" => DATA <= x"D0"; when x"249" => DATA <= x"F3"; when x"24A" => DATA <= x"A5"; when x"24B" => DATA <= x"D1"; when x"24C" => DATA <= x"F0"; when x"24D" => DATA <= x"03"; when x"24E" => DATA <= x"20"; when x"24F" => DATA <= x"59"; when x"250" => DATA <= x"E2"; when x"251" => DATA <= x"A2"; when x"252" => DATA <= x"C9"; when x"253" => DATA <= x"20"; when x"254" => DATA <= x"F1"; when x"255" => DATA <= x"F7"; when x"256" => DATA <= x"4C"; when x"257" => DATA <= x"ED"; when x"258" => DATA <= x"FF"; when x"259" => DATA <= x"85"; when x"25A" => DATA <= x"CB"; when x"25B" => DATA <= x"B1"; when x"25C" => DATA <= x"CF"; when x"25D" => DATA <= x"84"; when x"25E" => DATA <= x"CC"; when x"25F" => DATA <= x"45"; when x"260" => DATA <= x"CA"; when x"261" => DATA <= x"85"; when x"262" => DATA <= x"CA"; when x"263" => DATA <= x"4A"; when x"264" => DATA <= x"4A"; when x"265" => DATA <= x"4A"; when x"266" => DATA <= x"4A"; when x"267" => DATA <= x"AA"; when x"268" => DATA <= x"0A"; when x"269" => DATA <= x"45"; when x"26A" => DATA <= x"C9"; when x"26B" => DATA <= x"85"; when x"26C" => DATA <= x"C9"; when x"26D" => DATA <= x"8A"; when x"26E" => DATA <= x"45"; when x"26F" => DATA <= x"CA"; when x"270" => DATA <= x"85"; when x"271" => DATA <= x"CA"; when x"272" => DATA <= x"0A"; when x"273" => DATA <= x"0A"; when x"274" => DATA <= x"0A"; when x"275" => DATA <= x"AA"; when x"276" => DATA <= x"0A"; when x"277" => DATA <= x"0A"; when x"278" => DATA <= x"45"; when x"279" => DATA <= x"CA"; when x"27A" => DATA <= x"A8"; when x"27B" => DATA <= x"8A"; when x"27C" => DATA <= x"2A"; when x"27D" => DATA <= x"45"; when x"27E" => DATA <= x"C9"; when x"27F" => DATA <= x"85"; when x"280" => DATA <= x"CA"; when x"281" => DATA <= x"84"; when x"282" => DATA <= x"C9"; when x"283" => DATA <= x"A4"; when x"284" => DATA <= x"CC"; when x"285" => DATA <= x"C8"; when x"286" => DATA <= x"C6"; when x"287" => DATA <= x"CB"; when x"288" => DATA <= x"D0"; when x"289" => DATA <= x"D1"; when x"28A" => DATA <= x"60"; when x"28B" => DATA <= x"20"; when x"28C" => DATA <= x"39"; when x"28D" => DATA <= x"E7"; when x"28E" => DATA <= x"20"; when x"28F" => DATA <= x"3D"; when x"290" => DATA <= x"E5"; when x"291" => DATA <= x"20"; when x"292" => DATA <= x"A2"; when x"293" => DATA <= x"E2"; when x"294" => DATA <= x"48"; when x"295" => DATA <= x"20"; when x"296" => DATA <= x"ED"; when x"297" => DATA <= x"FF"; when x"298" => DATA <= x"68"; when x"299" => DATA <= x"C9"; when x"29A" => DATA <= x"59"; when x"29B" => DATA <= x"F0"; when x"29C" => DATA <= x"01"; when x"29D" => DATA <= x"60"; when x"29E" => DATA <= x"20"; when x"29F" => DATA <= x"3F"; when x"2A0" => DATA <= x"E6"; when x"2A1" => DATA <= x"60"; when x"2A2" => DATA <= x"20"; when x"2A3" => DATA <= x"D1"; when x"2A4" => DATA <= x"F7"; when x"2A5" => DATA <= x"43"; when x"2A6" => DATA <= x"4F"; when x"2A7" => DATA <= x"4E"; when x"2A8" => DATA <= x"46"; when x"2A9" => DATA <= x"49"; when x"2AA" => DATA <= x"52"; when x"2AB" => DATA <= x"4D"; when x"2AC" => DATA <= x"20"; when x"2AD" => DATA <= x"28"; when x"2AE" => DATA <= x"59"; when x"2AF" => DATA <= x"29"; when x"2B0" => DATA <= x"3A"; when x"2B1" => DATA <= x"EA"; when x"2B2" => DATA <= x"20"; when x"2B3" => DATA <= x"E3"; when x"2B4" => DATA <= x"FF"; when x"2B5" => DATA <= x"4C"; when x"2B6" => DATA <= x"F4"; when x"2B7" => DATA <= x"FF"; when x"2B8" => DATA <= x"20"; when x"2B9" => DATA <= x"39"; when x"2BA" => DATA <= x"E7"; when x"2BB" => DATA <= x"20"; when x"2BC" => DATA <= x"3D"; when x"2BD" => DATA <= x"E5"; when x"2BE" => DATA <= x"A9"; when x"2BF" => DATA <= x"40"; when x"2C0" => DATA <= x"85"; when x"2C1" => DATA <= x"AC"; when x"2C2" => DATA <= x"A9"; when x"2C3" => DATA <= x"01"; when x"2C4" => DATA <= x"85"; when x"2C5" => DATA <= x"AD"; when x"2C6" => DATA <= x"A9"; when x"2C7" => DATA <= x"15"; when x"2C8" => DATA <= x"20"; when x"2C9" => DATA <= x"48"; when x"2CA" => DATA <= x"E6"; when x"2CB" => DATA <= x"A2"; when x"2CC" => DATA <= x"0D"; when x"2CD" => DATA <= x"20"; when x"2CE" => DATA <= x"95"; when x"2CF" => DATA <= x"E6"; when x"2D0" => DATA <= x"AD"; when x"2D1" => DATA <= x"40"; when x"2D2" => DATA <= x"01"; when x"2D3" => DATA <= x"85"; when x"2D4" => DATA <= x"CA"; when x"2D5" => DATA <= x"AD"; when x"2D6" => DATA <= x"41"; when x"2D7" => DATA <= x"01"; when x"2D8" => DATA <= x"85"; when x"2D9" => DATA <= x"CB"; when x"2DA" => DATA <= x"A9"; when x"2DB" => DATA <= x"00"; when x"2DC" => DATA <= x"85"; when x"2DD" => DATA <= x"C9"; when x"2DE" => DATA <= x"A9"; when x"2DF" => DATA <= x"E9"; when x"2E0" => DATA <= x"8D"; when x"2E1" => DATA <= x"0A"; when x"2E2" => DATA <= x"02"; when x"2E3" => DATA <= x"A9"; when x"2E4" => DATA <= x"E2"; when x"2E5" => DATA <= x"8D"; when x"2E6" => DATA <= x"0B"; when x"2E7" => DATA <= x"02"; when x"2E8" => DATA <= x"60"; when x"2E9" => DATA <= x"08"; when x"2EA" => DATA <= x"D8"; when x"2EB" => DATA <= x"A5"; when x"2EC" => DATA <= x"C9"; when x"2ED" => DATA <= x"D0"; when x"2EE" => DATA <= x"33"; when x"2EF" => DATA <= x"A5"; when x"2F0" => DATA <= x"CB"; when x"2F1" => DATA <= x"D0"; when x"2F2" => DATA <= x"06"; when x"2F3" => DATA <= x"A5"; when x"2F4" => DATA <= x"CA"; when x"2F5" => DATA <= x"C9"; when x"2F6" => DATA <= x"11"; when x"2F7" => DATA <= x"90"; when x"2F8" => DATA <= x"02"; when x"2F9" => DATA <= x"A9"; when x"2FA" => DATA <= x"10"; when x"2FB" => DATA <= x"85"; when x"2FC" => DATA <= x"C9"; when x"2FD" => DATA <= x"A5"; when x"2FE" => DATA <= x"CA"; when x"2FF" => DATA <= x"38"; when x"300" => DATA <= x"E5"; when x"301" => DATA <= x"C9"; when x"302" => DATA <= x"85"; when x"303" => DATA <= x"CA"; when x"304" => DATA <= x"B0"; when x"305" => DATA <= x"02"; when x"306" => DATA <= x"C6"; when x"307" => DATA <= x"CB"; when x"308" => DATA <= x"A5"; when x"309" => DATA <= x"C9"; when x"30A" => DATA <= x"8D"; when x"30B" => DATA <= x"01"; when x"30C" => DATA <= x"B4"; when x"30D" => DATA <= x"20"; when x"30E" => DATA <= x"6B"; when x"30F" => DATA <= x"E6"; when x"310" => DATA <= x"20"; when x"311" => DATA <= x"47"; when x"312" => DATA <= x"E6"; when x"313" => DATA <= x"A9"; when x"314" => DATA <= x"22"; when x"315" => DATA <= x"20"; when x"316" => DATA <= x"48"; when x"317" => DATA <= x"E6"; when x"318" => DATA <= x"C9"; when x"319" => DATA <= x"40"; when x"31A" => DATA <= x"F0"; when x"31B" => DATA <= x"03"; when x"31C" => DATA <= x"4C"; when x"31D" => DATA <= x"C9"; when x"31E" => DATA <= x"E0"; when x"31F" => DATA <= x"20"; when x"320" => DATA <= x"55"; when x"321" => DATA <= x"E6"; when x"322" => DATA <= x"C6"; when x"323" => DATA <= x"C9"; when x"324" => DATA <= x"D0"; when x"325" => DATA <= x"18"; when x"326" => DATA <= x"A5"; when x"327" => DATA <= x"CA"; when x"328" => DATA <= x"05"; when x"329" => DATA <= x"CB"; when x"32A" => DATA <= x"D0"; when x"32B" => DATA <= x"12"; when x"32C" => DATA <= x"A9"; when x"32D" => DATA <= x"94"; when x"32E" => DATA <= x"8D"; when x"32F" => DATA <= x"0A"; when x"330" => DATA <= x"02"; when x"331" => DATA <= x"A9"; when x"332" => DATA <= x"FE"; when x"333" => DATA <= x"8D"; when x"334" => DATA <= x"0B"; when x"335" => DATA <= x"02"; when x"336" => DATA <= x"20"; when x"337" => DATA <= x"73"; when x"338" => DATA <= x"E6"; when x"339" => DATA <= x"AD"; when x"33A" => DATA <= x"02"; when x"33B" => DATA <= x"B4"; when x"33C" => DATA <= x"28"; when x"33D" => DATA <= x"60"; when x"33E" => DATA <= x"20"; when x"33F" => DATA <= x"73"; when x"340" => DATA <= x"E6"; when x"341" => DATA <= x"AD"; when x"342" => DATA <= x"02"; when x"343" => DATA <= x"B4"; when x"344" => DATA <= x"C9"; when x"345" => DATA <= x"0A"; when x"346" => DATA <= x"F0"; when x"347" => DATA <= x"A3"; when x"348" => DATA <= x"28"; when x"349" => DATA <= x"60"; when x"34A" => DATA <= x"20"; when x"34B" => DATA <= x"39"; when x"34C" => DATA <= x"E7"; when x"34D" => DATA <= x"20"; when x"34E" => DATA <= x"3D"; when x"34F" => DATA <= x"E5"; when x"350" => DATA <= x"A9"; when x"351" => DATA <= x"40"; when x"352" => DATA <= x"85"; when x"353" => DATA <= x"AC"; when x"354" => DATA <= x"A9"; when x"355" => DATA <= x"01"; when x"356" => DATA <= x"85"; when x"357" => DATA <= x"AD"; when x"358" => DATA <= x"A9"; when x"359" => DATA <= x"15"; when x"35A" => DATA <= x"20"; when x"35B" => DATA <= x"48"; when x"35C" => DATA <= x"E6"; when x"35D" => DATA <= x"A2"; when x"35E" => DATA <= x"0D"; when x"35F" => DATA <= x"20"; when x"360" => DATA <= x"95"; when x"361" => DATA <= x"E6"; when x"362" => DATA <= x"24"; when x"363" => DATA <= x"EA"; when x"364" => DATA <= x"10"; when x"365" => DATA <= x"01"; when x"366" => DATA <= x"60"; when x"367" => DATA <= x"A2"; when x"368" => DATA <= x"03"; when x"369" => DATA <= x"20"; when x"36A" => DATA <= x"7F"; when x"36B" => DATA <= x"E3"; when x"36C" => DATA <= x"A2"; when x"36D" => DATA <= x"07"; when x"36E" => DATA <= x"20"; when x"36F" => DATA <= x"7F"; when x"370" => DATA <= x"E3"; when x"371" => DATA <= x"A2"; when x"372" => DATA <= x"0B"; when x"373" => DATA <= x"20"; when x"374" => DATA <= x"7F"; when x"375" => DATA <= x"E3"; when x"376" => DATA <= x"AD"; when x"377" => DATA <= x"4C"; when x"378" => DATA <= x"01"; when x"379" => DATA <= x"20"; when x"37A" => DATA <= x"02"; when x"37B" => DATA <= x"F8"; when x"37C" => DATA <= x"4C"; when x"37D" => DATA <= x"ED"; when x"37E" => DATA <= x"FF"; when x"37F" => DATA <= x"BD"; when x"380" => DATA <= x"40"; when x"381" => DATA <= x"01"; when x"382" => DATA <= x"20"; when x"383" => DATA <= x"02"; when x"384" => DATA <= x"F8"; when x"385" => DATA <= x"CA"; when x"386" => DATA <= x"BD"; when x"387" => DATA <= x"40"; when x"388" => DATA <= x"01"; when x"389" => DATA <= x"20"; when x"38A" => DATA <= x"02"; when x"38B" => DATA <= x"F8"; when x"38C" => DATA <= x"CA"; when x"38D" => DATA <= x"BD"; when x"38E" => DATA <= x"40"; when x"38F" => DATA <= x"01"; when x"390" => DATA <= x"20"; when x"391" => DATA <= x"02"; when x"392" => DATA <= x"F8"; when x"393" => DATA <= x"CA"; when x"394" => DATA <= x"BD"; when x"395" => DATA <= x"40"; when x"396" => DATA <= x"01"; when x"397" => DATA <= x"4C"; when x"398" => DATA <= x"FA"; when x"399" => DATA <= x"F7"; when x"39A" => DATA <= x"A2"; when x"39B" => DATA <= x"00"; when x"39C" => DATA <= x"BD"; when x"39D" => DATA <= x"D0"; when x"39E" => DATA <= x"EF"; when x"39F" => DATA <= x"20"; when x"3A0" => DATA <= x"F4"; when x"3A1" => DATA <= x"FF"; when x"3A2" => DATA <= x"E8"; when x"3A3" => DATA <= x"E0"; when x"3A4" => DATA <= x"30"; when x"3A5" => DATA <= x"D0"; when x"3A6" => DATA <= x"F5"; when x"3A7" => DATA <= x"20"; when x"3A8" => DATA <= x"ED"; when x"3A9" => DATA <= x"FF"; when x"3AA" => DATA <= x"20"; when x"3AB" => DATA <= x"D1"; when x"3AC" => DATA <= x"F7"; when x"3AD" => DATA <= x"49"; when x"3AE" => DATA <= x"4E"; when x"3AF" => DATA <= x"54"; when x"3B0" => DATA <= x"45"; when x"3B1" => DATA <= x"52"; when x"3B2" => DATA <= x"46"; when x"3B3" => DATA <= x"41"; when x"3B4" => DATA <= x"43"; when x"3B5" => DATA <= x"45"; when x"3B6" => DATA <= x"20"; when x"3B7" => DATA <= x"46"; when x"3B8" => DATA <= x"2F"; when x"3B9" => DATA <= x"57"; when x"3BA" => DATA <= x"20"; when x"3BB" => DATA <= x"56"; when x"3BC" => DATA <= x"45"; when x"3BD" => DATA <= x"52"; when x"3BE" => DATA <= x"53"; when x"3BF" => DATA <= x"49"; when x"3C0" => DATA <= x"4F"; when x"3C1" => DATA <= x"4E"; when x"3C2" => DATA <= x"20"; when x"3C3" => DATA <= x"EA"; when x"3C4" => DATA <= x"A9"; when x"3C5" => DATA <= x"E0"; when x"3C6" => DATA <= x"20"; when x"3C7" => DATA <= x"48"; when x"3C8" => DATA <= x"E6"; when x"3C9" => DATA <= x"20"; when x"3CA" => DATA <= x"1B"; when x"3CB" => DATA <= x"E4"; when x"3CC" => DATA <= x"20"; when x"3CD" => DATA <= x"ED"; when x"3CE" => DATA <= x"FF"; when x"3CF" => DATA <= x"20"; when x"3D0" => DATA <= x"D1"; when x"3D1" => DATA <= x"F7"; when x"3D2" => DATA <= x"42"; when x"3D3" => DATA <= x"4F"; when x"3D4" => DATA <= x"4F"; when x"3D5" => DATA <= x"54"; when x"3D6" => DATA <= x"4C"; when x"3D7" => DATA <= x"4F"; when x"3D8" => DATA <= x"41"; when x"3D9" => DATA <= x"44"; when x"3DA" => DATA <= x"45"; when x"3DB" => DATA <= x"52"; when x"3DC" => DATA <= x"20"; when x"3DD" => DATA <= x"56"; when x"3DE" => DATA <= x"45"; when x"3DF" => DATA <= x"52"; when x"3E0" => DATA <= x"53"; when x"3E1" => DATA <= x"49"; when x"3E2" => DATA <= x"4F"; when x"3E3" => DATA <= x"4E"; when x"3E4" => DATA <= x"20"; when x"3E5" => DATA <= x"EA"; when x"3E6" => DATA <= x"A9"; when x"3E7" => DATA <= x"E1"; when x"3E8" => DATA <= x"20"; when x"3E9" => DATA <= x"48"; when x"3EA" => DATA <= x"E6"; when x"3EB" => DATA <= x"20"; when x"3EC" => DATA <= x"1B"; when x"3ED" => DATA <= x"E4"; when x"3EE" => DATA <= x"20"; when x"3EF" => DATA <= x"ED"; when x"3F0" => DATA <= x"FF"; when x"3F1" => DATA <= x"20"; when x"3F2" => DATA <= x"D1"; when x"3F3" => DATA <= x"F7"; when x"3F4" => DATA <= x"43"; when x"3F5" => DATA <= x"41"; when x"3F6" => DATA <= x"52"; when x"3F7" => DATA <= x"44"; when x"3F8" => DATA <= x"20"; when x"3F9" => DATA <= x"54"; when x"3FA" => DATA <= x"59"; when x"3FB" => DATA <= x"50"; when x"3FC" => DATA <= x"45"; when x"3FD" => DATA <= x"3A"; when x"3FE" => DATA <= x"20"; when x"3FF" => DATA <= x"EA"; when x"400" => DATA <= x"A9"; when x"401" => DATA <= x"80"; when x"402" => DATA <= x"20"; when x"403" => DATA <= x"48"; when x"404" => DATA <= x"E6"; when x"405" => DATA <= x"20"; when x"406" => DATA <= x"6F"; when x"407" => DATA <= x"E0"; when x"408" => DATA <= x"A0"; when x"409" => DATA <= x"04"; when x"40A" => DATA <= x"BD"; when x"40B" => DATA <= x"3D"; when x"40C" => DATA <= x"E9"; when x"40D" => DATA <= x"C9"; when x"40E" => DATA <= x"20"; when x"40F" => DATA <= x"F0"; when x"410" => DATA <= x"03"; when x"411" => DATA <= x"20"; when x"412" => DATA <= x"F4"; when x"413" => DATA <= x"FF"; when x"414" => DATA <= x"E8"; when x"415" => DATA <= x"88"; when x"416" => DATA <= x"D0"; when x"417" => DATA <= x"F2"; when x"418" => DATA <= x"4C"; when x"419" => DATA <= x"ED"; when x"41A" => DATA <= x"FF"; when x"41B" => DATA <= x"48"; when x"41C" => DATA <= x"4A"; when x"41D" => DATA <= x"4A"; when x"41E" => DATA <= x"4A"; when x"41F" => DATA <= x"4A"; when x"420" => DATA <= x"20"; when x"421" => DATA <= x"0B"; when x"422" => DATA <= x"F8"; when x"423" => DATA <= x"A9"; when x"424" => DATA <= x"2E"; when x"425" => DATA <= x"20"; when x"426" => DATA <= x"F4"; when x"427" => DATA <= x"FF"; when x"428" => DATA <= x"68"; when x"429" => DATA <= x"4C"; when x"42A" => DATA <= x"0B"; when x"42B" => DATA <= x"F8"; when x"42C" => DATA <= x"A9"; when x"42D" => DATA <= x"00"; when x"42E" => DATA <= x"85"; when x"42F" => DATA <= x"CD"; when x"430" => DATA <= x"20"; when x"431" => DATA <= x"39"; when x"432" => DATA <= x"E7"; when x"433" => DATA <= x"20"; when x"434" => DATA <= x"3D"; when x"435" => DATA <= x"E5"; when x"436" => DATA <= x"20"; when x"437" => DATA <= x"70"; when x"438" => DATA <= x"E5"; when x"439" => DATA <= x"20"; when x"43A" => DATA <= x"FC"; when x"43B" => DATA <= x"E6"; when x"43C" => DATA <= x"20"; when x"43D" => DATA <= x"1B"; when x"43E" => DATA <= x"E7"; when x"43F" => DATA <= x"4C"; when x"440" => DATA <= x"ED"; when x"441" => DATA <= x"FF"; when x"442" => DATA <= x"20"; when x"443" => DATA <= x"39"; when x"444" => DATA <= x"E7"; when x"445" => DATA <= x"20"; when x"446" => DATA <= x"44"; when x"447" => DATA <= x"F8"; when x"448" => DATA <= x"4C"; when x"449" => DATA <= x"5B"; when x"44A" => DATA <= x"F9"; when x"44B" => DATA <= x"20"; when x"44C" => DATA <= x"4F"; when x"44D" => DATA <= x"F8"; when x"44E" => DATA <= x"20"; when x"44F" => DATA <= x"3D"; when x"450" => DATA <= x"E5"; when x"451" => DATA <= x"20"; when x"452" => DATA <= x"70"; when x"453" => DATA <= x"E5"; when x"454" => DATA <= x"24"; when x"455" => DATA <= x"EA"; when x"456" => DATA <= x"30"; when x"457" => DATA <= x"06"; when x"458" => DATA <= x"20"; when x"459" => DATA <= x"1B"; when x"45A" => DATA <= x"E7"; when x"45B" => DATA <= x"20"; when x"45C" => DATA <= x"ED"; when x"45D" => DATA <= x"FF"; when x"45E" => DATA <= x"4C"; when x"45F" => DATA <= x"9B"; when x"460" => DATA <= x"E5"; when x"461" => DATA <= x"20"; when x"462" => DATA <= x"39"; when x"463" => DATA <= x"E7"; when x"464" => DATA <= x"20"; when x"465" => DATA <= x"76"; when x"466" => DATA <= x"F8"; when x"467" => DATA <= x"A2"; when x"468" => DATA <= x"00"; when x"469" => DATA <= x"B9"; when x"46A" => DATA <= x"00"; when x"46B" => DATA <= x"01"; when x"46C" => DATA <= x"9D"; when x"46D" => DATA <= x"00"; when x"46E" => DATA <= x"01"; when x"46F" => DATA <= x"E8"; when x"470" => DATA <= x"C8"; when x"471" => DATA <= x"C9"; when x"472" => DATA <= x"0D"; when x"473" => DATA <= x"D0"; when x"474" => DATA <= x"F4"; when x"475" => DATA <= x"88"; when x"476" => DATA <= x"A5"; when x"477" => DATA <= x"EA"; when x"478" => DATA <= x"48"; when x"479" => DATA <= x"A9"; when x"47A" => DATA <= x"FF"; when x"47B" => DATA <= x"85"; when x"47C" => DATA <= x"EA"; when x"47D" => DATA <= x"20"; when x"47E" => DATA <= x"44"; when x"47F" => DATA <= x"F8"; when x"480" => DATA <= x"20"; when x"481" => DATA <= x"5B"; when x"482" => DATA <= x"F9"; when x"483" => DATA <= x"68"; when x"484" => DATA <= x"85"; when x"485" => DATA <= x"EA"; when x"486" => DATA <= x"A5"; when x"487" => DATA <= x"CD"; when x"488" => DATA <= x"C9"; when x"489" => DATA <= x"B2"; when x"48A" => DATA <= x"D0"; when x"48B" => DATA <= x"11"; when x"48C" => DATA <= x"A5"; when x"48D" => DATA <= x"CE"; when x"48E" => DATA <= x"C9"; when x"48F" => DATA <= x"C2"; when x"490" => DATA <= x"D0"; when x"491" => DATA <= x"0B"; when x"492" => DATA <= x"A9"; when x"493" => DATA <= x"A0"; when x"494" => DATA <= x"85"; when x"495" => DATA <= x"05"; when x"496" => DATA <= x"A9"; when x"497" => DATA <= x"E4"; when x"498" => DATA <= x"85"; when x"499" => DATA <= x"06"; when x"49A" => DATA <= x"4C"; when x"49B" => DATA <= x"F2"; when x"49C" => DATA <= x"C2"; when x"49D" => DATA <= x"6C"; when x"49E" => DATA <= x"CD"; when x"49F" => DATA <= x"00"; when x"4A0" => DATA <= x"52"; when x"4A1" => DATA <= x"55"; when x"4A2" => DATA <= x"4E"; when x"4A3" => DATA <= x"0D"; when x"4A4" => DATA <= x"20"; when x"4A5" => DATA <= x"39"; when x"4A6" => DATA <= x"E7"; when x"4A7" => DATA <= x"20"; when x"4A8" => DATA <= x"44"; when x"4A9" => DATA <= x"F8"; when x"4AA" => DATA <= x"4C"; when x"4AB" => DATA <= x"BE"; when x"4AC" => DATA <= x"FA"; when x"4AD" => DATA <= x"20"; when x"4AE" => DATA <= x"4F"; when x"4AF" => DATA <= x"F8"; when x"4B0" => DATA <= x"20"; when x"4B1" => DATA <= x"45"; when x"4B2" => DATA <= x"E5"; when x"4B3" => DATA <= x"29"; when x"4B4" => DATA <= x"3F"; when x"4B5" => DATA <= x"F0"; when x"4B6" => DATA <= x"1D"; when x"4B7" => DATA <= x"C9"; when x"4B8" => DATA <= x"08"; when x"4B9" => DATA <= x"F0"; when x"4BA" => DATA <= x"03"; when x"4BB" => DATA <= x"4C"; when x"4BC" => DATA <= x"A7"; when x"4BD" => DATA <= x"E6"; when x"4BE" => DATA <= x"20"; when x"4BF" => DATA <= x"25"; when x"4C0" => DATA <= x"E5"; when x"4C1" => DATA <= x"48"; when x"4C2" => DATA <= x"20"; when x"4C3" => DATA <= x"ED"; when x"4C4" => DATA <= x"FF"; when x"4C5" => DATA <= x"68"; when x"4C6" => DATA <= x"C9"; when x"4C7" => DATA <= x"59"; when x"4C8" => DATA <= x"F0"; when x"4C9" => DATA <= x"01"; when x"4CA" => DATA <= x"60"; when x"4CB" => DATA <= x"20"; when x"4CC" => DATA <= x"3F"; when x"4CD" => DATA <= x"E6"; when x"4CE" => DATA <= x"20"; when x"4CF" => DATA <= x"45"; when x"4D0" => DATA <= x"E5"; when x"4D1" => DATA <= x"20"; when x"4D2" => DATA <= x"A7"; when x"4D3" => DATA <= x"E6"; when x"4D4" => DATA <= x"A5"; when x"4D5" => DATA <= x"CB"; when x"4D6" => DATA <= x"8D"; when x"4D7" => DATA <= x"50"; when x"4D8" => DATA <= x"01"; when x"4D9" => DATA <= x"A5"; when x"4DA" => DATA <= x"CC"; when x"4DB" => DATA <= x"8D"; when x"4DC" => DATA <= x"51"; when x"4DD" => DATA <= x"01"; when x"4DE" => DATA <= x"A5"; when x"4DF" => DATA <= x"CD"; when x"4E0" => DATA <= x"8D"; when x"4E1" => DATA <= x"52"; when x"4E2" => DATA <= x"01"; when x"4E3" => DATA <= x"A5"; when x"4E4" => DATA <= x"CE"; when x"4E5" => DATA <= x"8D"; when x"4E6" => DATA <= x"53"; when x"4E7" => DATA <= x"01"; when x"4E8" => DATA <= x"38"; when x"4E9" => DATA <= x"A5"; when x"4EA" => DATA <= x"D2"; when x"4EB" => DATA <= x"E5"; when x"4EC" => DATA <= x"D0"; when x"4ED" => DATA <= x"8D"; when x"4EE" => DATA <= x"55"; when x"4EF" => DATA <= x"01"; when x"4F0" => DATA <= x"A5"; when x"4F1" => DATA <= x"D1"; when x"4F2" => DATA <= x"E5"; when x"4F3" => DATA <= x"CF"; when x"4F4" => DATA <= x"8D"; when x"4F5" => DATA <= x"54"; when x"4F6" => DATA <= x"01"; when x"4F7" => DATA <= x"A2"; when x"4F8" => DATA <= x"FF"; when x"4F9" => DATA <= x"E8"; when x"4FA" => DATA <= x"BD"; when x"4FB" => DATA <= x"40"; when x"4FC" => DATA <= x"01"; when x"4FD" => DATA <= x"C9"; when x"4FE" => DATA <= x"0D"; when x"4FF" => DATA <= x"D0"; when x"500" => DATA <= x"F8"; when x"501" => DATA <= x"A9"; when x"502" => DATA <= x"00"; when x"503" => DATA <= x"9D"; when x"504" => DATA <= x"40"; when x"505" => DATA <= x"01"; when x"506" => DATA <= x"E8"; when x"507" => DATA <= x"E0"; when x"508" => DATA <= x"10"; when x"509" => DATA <= x"D0"; when x"50A" => DATA <= x"F8"; when x"50B" => DATA <= x"20"; when x"50C" => DATA <= x"E4"; when x"50D" => DATA <= x"E5"; when x"50E" => DATA <= x"20"; when x"50F" => DATA <= x"F8"; when x"510" => DATA <= x"E5"; when x"511" => DATA <= x"24"; when x"512" => DATA <= x"EA"; when x"513" => DATA <= x"30"; when x"514" => DATA <= x"0D"; when x"515" => DATA <= x"A2"; when x"516" => DATA <= x"05"; when x"517" => DATA <= x"BD"; when x"518" => DATA <= x"50"; when x"519" => DATA <= x"01"; when x"51A" => DATA <= x"95"; when x"51B" => DATA <= x"CB"; when x"51C" => DATA <= x"CA"; when x"51D" => DATA <= x"10"; when x"51E" => DATA <= x"F8"; when x"51F" => DATA <= x"20"; when x"520" => DATA <= x"1B"; when x"521" => DATA <= x"E7"; when x"522" => DATA <= x"4C"; when x"523" => DATA <= x"ED"; when x"524" => DATA <= x"FF"; when x"525" => DATA <= x"20"; when x"526" => DATA <= x"D1"; when x"527" => DATA <= x"F7"; when x"528" => DATA <= x"4F"; when x"529" => DATA <= x"56"; when x"52A" => DATA <= x"45"; when x"52B" => DATA <= x"52"; when x"52C" => DATA <= x"57"; when x"52D" => DATA <= x"52"; when x"52E" => DATA <= x"49"; when x"52F" => DATA <= x"54"; when x"530" => DATA <= x"45"; when x"531" => DATA <= x"20"; when x"532" => DATA <= x"28"; when x"533" => DATA <= x"59"; when x"534" => DATA <= x"29"; when x"535" => DATA <= x"3A"; when x"536" => DATA <= x"EA"; when x"537" => DATA <= x"20"; when x"538" => DATA <= x"E3"; when x"539" => DATA <= x"FF"; when x"53A" => DATA <= x"4C"; when x"53B" => DATA <= x"F4"; when x"53C" => DATA <= x"FF"; when x"53D" => DATA <= x"A9"; when x"53E" => DATA <= x"11"; when x"53F" => DATA <= x"20"; when x"540" => DATA <= x"47"; when x"541" => DATA <= x"E5"; when x"542" => DATA <= x"4C"; when x"543" => DATA <= x"A7"; when x"544" => DATA <= x"E6"; when x"545" => DATA <= x"A9"; when x"546" => DATA <= x"13"; when x"547" => DATA <= x"48"; when x"548" => DATA <= x"20"; when x"549" => DATA <= x"50"; when x"54A" => DATA <= x"E5"; when x"54B" => DATA <= x"68"; when x"54C" => DATA <= x"20"; when x"54D" => DATA <= x"48"; when x"54E" => DATA <= x"E6"; when x"54F" => DATA <= x"60"; when x"550" => DATA <= x"20"; when x"551" => DATA <= x"60"; when x"552" => DATA <= x"E6"; when x"553" => DATA <= x"A2"; when x"554" => DATA <= x"00"; when x"555" => DATA <= x"F0"; when x"556" => DATA <= x"07"; when x"557" => DATA <= x"8D"; when x"558" => DATA <= x"03"; when x"559" => DATA <= x"B4"; when x"55A" => DATA <= x"20"; when x"55B" => DATA <= x"6B"; when x"55C" => DATA <= x"E6"; when x"55D" => DATA <= x"E8"; when x"55E" => DATA <= x"BD"; when x"55F" => DATA <= x"40"; when x"560" => DATA <= x"01"; when x"561" => DATA <= x"C9"; when x"562" => DATA <= x"0D"; when x"563" => DATA <= x"D0"; when x"564" => DATA <= x"F2"; when x"565" => DATA <= x"A9"; when x"566" => DATA <= x"00"; when x"567" => DATA <= x"8D"; when x"568" => DATA <= x"03"; when x"569" => DATA <= x"B4"; when x"56A" => DATA <= x"20"; when x"56B" => DATA <= x"6B"; when x"56C" => DATA <= x"E6"; when x"56D" => DATA <= x"4C"; when x"56E" => DATA <= x"47"; when x"56F" => DATA <= x"E6"; when x"570" => DATA <= x"A9"; when x"571" => DATA <= x"40"; when x"572" => DATA <= x"85"; when x"573" => DATA <= x"AC"; when x"574" => DATA <= x"A9"; when x"575" => DATA <= x"01"; when x"576" => DATA <= x"85"; when x"577" => DATA <= x"AD"; when x"578" => DATA <= x"A9"; when x"579" => DATA <= x"16"; when x"57A" => DATA <= x"20"; when x"57B" => DATA <= x"C0"; when x"57C" => DATA <= x"E5"; when x"57D" => DATA <= x"A0"; when x"57E" => DATA <= x"05"; when x"57F" => DATA <= x"A2"; when x"580" => DATA <= x"03"; when x"581" => DATA <= x"24"; when x"582" => DATA <= x"CD"; when x"583" => DATA <= x"30"; when x"584" => DATA <= x"02"; when x"585" => DATA <= x"A2"; when x"586" => DATA <= x"05"; when x"587" => DATA <= x"B9"; when x"588" => DATA <= x"50"; when x"589" => DATA <= x"01"; when x"58A" => DATA <= x"99"; when x"58B" => DATA <= x"CB"; when x"58C" => DATA <= x"00"; when x"58D" => DATA <= x"88"; when x"58E" => DATA <= x"CA"; when x"58F" => DATA <= x"10"; when x"590" => DATA <= x"F6"; when x"591" => DATA <= x"60"; when x"592" => DATA <= x"A9"; when x"593" => DATA <= x"00"; when x"594" => DATA <= x"20"; when x"595" => DATA <= x"B6"; when x"596" => DATA <= x"E5"; when x"597" => DATA <= x"E6"; when x"598" => DATA <= x"CC"; when x"599" => DATA <= x"C6"; when x"59A" => DATA <= x"D0"; when x"59B" => DATA <= x"A5"; when x"59C" => DATA <= x"D0"; when x"59D" => DATA <= x"D0"; when x"59E" => DATA <= x"F3"; when x"59F" => DATA <= x"A5"; when x"5A0" => DATA <= x"CF"; when x"5A1" => DATA <= x"F0"; when x"5A2" => DATA <= x"10"; when x"5A3" => DATA <= x"20"; when x"5A4" => DATA <= x"B6"; when x"5A5" => DATA <= x"E5"; when x"5A6" => DATA <= x"A5"; when x"5A7" => DATA <= x"CB"; when x"5A8" => DATA <= x"18"; when x"5A9" => DATA <= x"65"; when x"5AA" => DATA <= x"CF"; when x"5AB" => DATA <= x"85"; when x"5AC" => DATA <= x"CB"; when x"5AD" => DATA <= x"90"; when x"5AE" => DATA <= x"02"; when x"5AF" => DATA <= x"E6"; when x"5B0" => DATA <= x"CC"; when x"5B1" => DATA <= x"86"; when x"5B2" => DATA <= x"CF"; when x"5B3" => DATA <= x"4C"; when x"5B4" => DATA <= x"0A"; when x"5B5" => DATA <= x"E6"; when x"5B6" => DATA <= x"48"; when x"5B7" => DATA <= x"A5"; when x"5B8" => DATA <= x"CB"; when x"5B9" => DATA <= x"85"; when x"5BA" => DATA <= x"AC"; when x"5BB" => DATA <= x"A5"; when x"5BC" => DATA <= x"CC"; when x"5BD" => DATA <= x"85"; when x"5BE" => DATA <= x"AD"; when x"5BF" => DATA <= x"68"; when x"5C0" => DATA <= x"AA"; when x"5C1" => DATA <= x"8D"; when x"5C2" => DATA <= x"01"; when x"5C3" => DATA <= x"B4"; when x"5C4" => DATA <= x"20"; when x"5C5" => DATA <= x"6B"; when x"5C6" => DATA <= x"E6"; when x"5C7" => DATA <= x"20"; when x"5C8" => DATA <= x"47"; when x"5C9" => DATA <= x"E6"; when x"5CA" => DATA <= x"A9"; when x"5CB" => DATA <= x"22"; when x"5CC" => DATA <= x"20"; when x"5CD" => DATA <= x"48"; when x"5CE" => DATA <= x"E6"; when x"5CF" => DATA <= x"20"; when x"5D0" => DATA <= x"A7"; when x"5D1" => DATA <= x"E6"; when x"5D2" => DATA <= x"20"; when x"5D3" => DATA <= x"55"; when x"5D4" => DATA <= x"E6"; when x"5D5" => DATA <= x"A0"; when x"5D6" => DATA <= x"00"; when x"5D7" => DATA <= x"20"; when x"5D8" => DATA <= x"73"; when x"5D9" => DATA <= x"E6"; when x"5DA" => DATA <= x"AD"; when x"5DB" => DATA <= x"02"; when x"5DC" => DATA <= x"B4"; when x"5DD" => DATA <= x"91"; when x"5DE" => DATA <= x"AC"; when x"5DF" => DATA <= x"C8"; when x"5E0" => DATA <= x"CA"; when x"5E1" => DATA <= x"D0"; when x"5E2" => DATA <= x"F4"; when x"5E3" => DATA <= x"60"; when x"5E4" => DATA <= x"A9"; when x"5E5" => DATA <= x"40"; when x"5E6" => DATA <= x"85"; when x"5E7" => DATA <= x"AC"; when x"5E8" => DATA <= x"A9"; when x"5E9" => DATA <= x"01"; when x"5EA" => DATA <= x"85"; when x"5EB" => DATA <= x"AD"; when x"5EC" => DATA <= x"A9"; when x"5ED" => DATA <= x"16"; when x"5EE" => DATA <= x"4C"; when x"5EF" => DATA <= x"1A"; when x"5F0" => DATA <= x"E6"; when x"5F1" => DATA <= x"A9"; when x"5F2" => DATA <= x"00"; when x"5F3" => DATA <= x"20"; when x"5F4" => DATA <= x"12"; when x"5F5" => DATA <= x"E6"; when x"5F6" => DATA <= x"E6"; when x"5F7" => DATA <= x"D0"; when x"5F8" => DATA <= x"A5"; when x"5F9" => DATA <= x"D0"; when x"5FA" => DATA <= x"C5"; when x"5FB" => DATA <= x"D2"; when x"5FC" => DATA <= x"D0"; when x"5FD" => DATA <= x"F3"; when x"5FE" => DATA <= x"A5"; when x"5FF" => DATA <= x"D1"; when x"600" => DATA <= x"C5"; when x"601" => DATA <= x"CF"; when x"602" => DATA <= x"F0"; when x"603" => DATA <= x"06"; when x"604" => DATA <= x"38"; when x"605" => DATA <= x"E5"; when x"606" => DATA <= x"CF"; when x"607" => DATA <= x"20"; when x"608" => DATA <= x"12"; when x"609" => DATA <= x"E6"; when x"60A" => DATA <= x"A9"; when x"60B" => DATA <= x"10"; when x"60C" => DATA <= x"20"; when x"60D" => DATA <= x"48"; when x"60E" => DATA <= x"E6"; when x"60F" => DATA <= x"4C"; when x"610" => DATA <= x"A7"; when x"611" => DATA <= x"E6"; when x"612" => DATA <= x"A4"; when x"613" => DATA <= x"CF"; when x"614" => DATA <= x"84"; when x"615" => DATA <= x"AC"; when x"616" => DATA <= x"A4"; when x"617" => DATA <= x"D0"; when x"618" => DATA <= x"84"; when x"619" => DATA <= x"AD"; when x"61A" => DATA <= x"AA"; when x"61B" => DATA <= x"48"; when x"61C" => DATA <= x"20"; when x"61D" => DATA <= x"60"; when x"61E" => DATA <= x"E6"; when x"61F" => DATA <= x"A0"; when x"620" => DATA <= x"00"; when x"621" => DATA <= x"B1"; when x"622" => DATA <= x"AC"; when x"623" => DATA <= x"8D"; when x"624" => DATA <= x"03"; when x"625" => DATA <= x"B4"; when x"626" => DATA <= x"20"; when x"627" => DATA <= x"6B"; when x"628" => DATA <= x"E6"; when x"629" => DATA <= x"C8"; when x"62A" => DATA <= x"CA"; when x"62B" => DATA <= x"D0"; when x"62C" => DATA <= x"F4"; when x"62D" => DATA <= x"68"; when x"62E" => DATA <= x"8D"; when x"62F" => DATA <= x"01"; when x"630" => DATA <= x"B4"; when x"631" => DATA <= x"20"; when x"632" => DATA <= x"6B"; when x"633" => DATA <= x"E6"; when x"634" => DATA <= x"20"; when x"635" => DATA <= x"47"; when x"636" => DATA <= x"E6"; when x"637" => DATA <= x"A9"; when x"638" => DATA <= x"23"; when x"639" => DATA <= x"20"; when x"63A" => DATA <= x"48"; when x"63B" => DATA <= x"E6"; when x"63C" => DATA <= x"4C"; when x"63D" => DATA <= x"A7"; when x"63E" => DATA <= x"E6"; when x"63F" => DATA <= x"A9"; when x"640" => DATA <= x"14"; when x"641" => DATA <= x"20"; when x"642" => DATA <= x"48"; when x"643" => DATA <= x"E6"; when x"644" => DATA <= x"4C"; when x"645" => DATA <= x"A7"; when x"646" => DATA <= x"E6"; when x"647" => DATA <= x"60"; when x"648" => DATA <= x"8D"; when x"649" => DATA <= x"00"; when x"64A" => DATA <= x"B4"; when x"64B" => DATA <= x"20"; when x"64C" => DATA <= x"6B"; when x"64D" => DATA <= x"E6"; when x"64E" => DATA <= x"20"; when x"64F" => DATA <= x"7B"; when x"650" => DATA <= x"E6"; when x"651" => DATA <= x"AD"; when x"652" => DATA <= x"00"; when x"653" => DATA <= x"B4"; when x"654" => DATA <= x"60"; when x"655" => DATA <= x"A9"; when x"656" => DATA <= x"20"; when x"657" => DATA <= x"8D"; when x"658" => DATA <= x"00"; when x"659" => DATA <= x"B4"; when x"65A" => DATA <= x"20"; when x"65B" => DATA <= x"6B"; when x"65C" => DATA <= x"E6"; when x"65D" => DATA <= x"4C"; when x"65E" => DATA <= x"47"; when x"65F" => DATA <= x"E6"; when x"660" => DATA <= x"A9"; when x"661" => DATA <= x"21"; when x"662" => DATA <= x"8D"; when x"663" => DATA <= x"00"; when x"664" => DATA <= x"B4"; when x"665" => DATA <= x"20"; when x"666" => DATA <= x"6B"; when x"667" => DATA <= x"E6"; when x"668" => DATA <= x"4C"; when x"669" => DATA <= x"47"; when x"66A" => DATA <= x"E6"; when x"66B" => DATA <= x"AD"; when x"66C" => DATA <= x"04"; when x"66D" => DATA <= x"B4"; when x"66E" => DATA <= x"29"; when x"66F" => DATA <= x"02"; when x"670" => DATA <= x"D0"; when x"671" => DATA <= x"F9"; when x"672" => DATA <= x"60"; when x"673" => DATA <= x"AD"; when x"674" => DATA <= x"04"; when x"675" => DATA <= x"B4"; when x"676" => DATA <= x"29"; when x"677" => DATA <= x"04"; when x"678" => DATA <= x"F0"; when x"679" => DATA <= x"F9"; when x"67A" => DATA <= x"60"; when x"67B" => DATA <= x"AD"; when x"67C" => DATA <= x"04"; when x"67D" => DATA <= x"B4"; when x"67E" => DATA <= x"29"; when x"67F" => DATA <= x"01"; when x"680" => DATA <= x"D0"; when x"681" => DATA <= x"F9"; when x"682" => DATA <= x"60"; when x"683" => DATA <= x"20"; when x"684" => DATA <= x"55"; when x"685" => DATA <= x"E6"; when x"686" => DATA <= x"A0"; when x"687" => DATA <= x"FF"; when x"688" => DATA <= x"C8"; when x"689" => DATA <= x"20"; when x"68A" => DATA <= x"73"; when x"68B" => DATA <= x"E6"; when x"68C" => DATA <= x"AD"; when x"68D" => DATA <= x"02"; when x"68E" => DATA <= x"B4"; when x"68F" => DATA <= x"99"; when x"690" => DATA <= x"40"; when x"691" => DATA <= x"01"; when x"692" => DATA <= x"D0"; when x"693" => DATA <= x"F4"; when x"694" => DATA <= x"60"; when x"695" => DATA <= x"20"; when x"696" => DATA <= x"55"; when x"697" => DATA <= x"E6"; when x"698" => DATA <= x"A0"; when x"699" => DATA <= x"00"; when x"69A" => DATA <= x"20"; when x"69B" => DATA <= x"73"; when x"69C" => DATA <= x"E6"; when x"69D" => DATA <= x"AD"; when x"69E" => DATA <= x"02"; when x"69F" => DATA <= x"B4"; when x"6A0" => DATA <= x"91"; when x"6A1" => DATA <= x"AC"; when x"6A2" => DATA <= x"C8"; when x"6A3" => DATA <= x"CA"; when x"6A4" => DATA <= x"D0"; when x"6A5" => DATA <= x"F4"; when x"6A6" => DATA <= x"60"; when x"6A7" => DATA <= x"C9"; when x"6A8" => DATA <= x"41"; when x"6A9" => DATA <= x"B0"; when x"6AA" => DATA <= x"29"; when x"6AB" => DATA <= x"60"; when x"6AC" => DATA <= x"20"; when x"6AD" => DATA <= x"BC"; when x"6AE" => DATA <= x"E6"; when x"6AF" => DATA <= x"29"; when x"6B0" => DATA <= x"DF"; when x"6B1" => DATA <= x"4C"; when x"6B2" => DATA <= x"C2"; when x"6B3" => DATA <= x"E6"; when x"6B4" => DATA <= x"20"; when x"6B5" => DATA <= x"BC"; when x"6B6" => DATA <= x"E6"; when x"6B7" => DATA <= x"09"; when x"6B8" => DATA <= x"20"; when x"6B9" => DATA <= x"4C"; when x"6BA" => DATA <= x"C2"; when x"6BB" => DATA <= x"E6"; when x"6BC" => DATA <= x"A9"; when x"6BD" => DATA <= x"F0"; when x"6BE" => DATA <= x"20"; when x"6BF" => DATA <= x"48"; when x"6C0" => DATA <= x"E6"; when x"6C1" => DATA <= x"60"; when x"6C2" => DATA <= x"8D"; when x"6C3" => DATA <= x"01"; when x"6C4" => DATA <= x"B4"; when x"6C5" => DATA <= x"20"; when x"6C6" => DATA <= x"6B"; when x"6C7" => DATA <= x"E6"; when x"6C8" => DATA <= x"20"; when x"6C9" => DATA <= x"47"; when x"6CA" => DATA <= x"E6"; when x"6CB" => DATA <= x"A9"; when x"6CC" => DATA <= x"F1"; when x"6CD" => DATA <= x"8D"; when x"6CE" => DATA <= x"00"; when x"6CF" => DATA <= x"B4"; when x"6D0" => DATA <= x"20"; when x"6D1" => DATA <= x"6B"; when x"6D2" => DATA <= x"E6"; when x"6D3" => DATA <= x"60"; when x"6D4" => DATA <= x"29"; when x"6D5" => DATA <= x"3F"; when x"6D6" => DATA <= x"AA"; when x"6D7" => DATA <= x"A0"; when x"6D8" => DATA <= x"FF"; when x"6D9" => DATA <= x"C8"; when x"6DA" => DATA <= x"B9"; when x"6DB" => DATA <= x"D3"; when x"6DC" => DATA <= x"E9"; when x"6DD" => DATA <= x"C9"; when x"6DE" => DATA <= x"0D"; when x"6DF" => DATA <= x"D0"; when x"6E0" => DATA <= x"F8"; when x"6E1" => DATA <= x"CA"; when x"6E2" => DATA <= x"D0"; when x"6E3" => DATA <= x"F5"; when x"6E4" => DATA <= x"C8"; when x"6E5" => DATA <= x"98"; when x"6E6" => DATA <= x"18"; when x"6E7" => DATA <= x"69"; when x"6E8" => DATA <= x"D3"; when x"6E9" => DATA <= x"85"; when x"6EA" => DATA <= x"D5"; when x"6EB" => DATA <= x"A9"; when x"6EC" => DATA <= x"E9"; when x"6ED" => DATA <= x"69"; when x"6EE" => DATA <= x"00"; when x"6EF" => DATA <= x"85"; when x"6F0" => DATA <= x"D6"; when x"6F1" => DATA <= x"A9"; when x"6F2" => DATA <= x"9F"; when x"6F3" => DATA <= x"85"; when x"6F4" => DATA <= x"05"; when x"6F5" => DATA <= x"A9"; when x"6F6" => DATA <= x"EA"; when x"6F7" => DATA <= x"85"; when x"6F8" => DATA <= x"06"; when x"6F9" => DATA <= x"4C"; when x"6FA" => DATA <= x"F2"; when x"6FB" => DATA <= x"C2"; when x"6FC" => DATA <= x"A2"; when x"6FD" => DATA <= x"00"; when x"6FE" => DATA <= x"F0"; when x"6FF" => DATA <= x"04"; when x"700" => DATA <= x"20"; when x"701" => DATA <= x"F4"; when x"702" => DATA <= x"FF"; when x"703" => DATA <= x"E8"; when x"704" => DATA <= x"BD"; when x"705" => DATA <= x"40"; when x"706" => DATA <= x"01"; when x"707" => DATA <= x"C9"; when x"708" => DATA <= x"20"; when x"709" => DATA <= x"90"; when x"70A" => DATA <= x"0B"; when x"70B" => DATA <= x"E0"; when x"70C" => DATA <= x"10"; when x"70D" => DATA <= x"D0"; when x"70E" => DATA <= x"F1"; when x"70F" => DATA <= x"60"; when x"710" => DATA <= x"A9"; when x"711" => DATA <= x"20"; when x"712" => DATA <= x"20"; when x"713" => DATA <= x"F4"; when x"714" => DATA <= x"FF"; when x"715" => DATA <= x"E8"; when x"716" => DATA <= x"E0"; when x"717" => DATA <= x"10"; when x"718" => DATA <= x"D0"; when x"719" => DATA <= x"F6"; when x"71A" => DATA <= x"60"; when x"71B" => DATA <= x"A5"; when x"71C" => DATA <= x"CC"; when x"71D" => DATA <= x"20"; when x"71E" => DATA <= x"02"; when x"71F" => DATA <= x"F8"; when x"720" => DATA <= x"A5"; when x"721" => DATA <= x"CB"; when x"722" => DATA <= x"20"; when x"723" => DATA <= x"FA"; when x"724" => DATA <= x"F7"; when x"725" => DATA <= x"A5"; when x"726" => DATA <= x"CE"; when x"727" => DATA <= x"20"; when x"728" => DATA <= x"02"; when x"729" => DATA <= x"F8"; when x"72A" => DATA <= x"A5"; when x"72B" => DATA <= x"CD"; when x"72C" => DATA <= x"20"; when x"72D" => DATA <= x"FA"; when x"72E" => DATA <= x"F7"; when x"72F" => DATA <= x"A5"; when x"730" => DATA <= x"D0"; when x"731" => DATA <= x"20"; when x"732" => DATA <= x"02"; when x"733" => DATA <= x"F8"; when x"734" => DATA <= x"A5"; when x"735" => DATA <= x"CF"; when x"736" => DATA <= x"4C"; when x"737" => DATA <= x"FA"; when x"738" => DATA <= x"F7"; when x"739" => DATA <= x"A2"; when x"73A" => DATA <= x"00"; when x"73B" => DATA <= x"A4"; when x"73C" => DATA <= x"9A"; when x"73D" => DATA <= x"20"; when x"73E" => DATA <= x"76"; when x"73F" => DATA <= x"F8"; when x"740" => DATA <= x"C9"; when x"741" => DATA <= x"22"; when x"742" => DATA <= x"F0"; when x"743" => DATA <= x"1A"; when x"744" => DATA <= x"C9"; when x"745" => DATA <= x"0D"; when x"746" => DATA <= x"F0"; when x"747" => DATA <= x"0C"; when x"748" => DATA <= x"9D"; when x"749" => DATA <= x"40"; when x"74A" => DATA <= x"01"; when x"74B" => DATA <= x"E8"; when x"74C" => DATA <= x"C8"; when x"74D" => DATA <= x"B9"; when x"74E" => DATA <= x"00"; when x"74F" => DATA <= x"01"; when x"750" => DATA <= x"C9"; when x"751" => DATA <= x"20"; when x"752" => DATA <= x"D0"; when x"753" => DATA <= x"F0"; when x"754" => DATA <= x"A9"; when x"755" => DATA <= x"0D"; when x"756" => DATA <= x"9D"; when x"757" => DATA <= x"40"; when x"758" => DATA <= x"01"; when x"759" => DATA <= x"E0"; when x"75A" => DATA <= x"00"; when x"75B" => DATA <= x"F0"; when x"75C" => DATA <= x"1D"; when x"75D" => DATA <= x"60"; when x"75E" => DATA <= x"C8"; when x"75F" => DATA <= x"B9"; when x"760" => DATA <= x"00"; when x"761" => DATA <= x"01"; when x"762" => DATA <= x"C9"; when x"763" => DATA <= x"0D"; when x"764" => DATA <= x"F0"; when x"765" => DATA <= x"14"; when x"766" => DATA <= x"9D"; when x"767" => DATA <= x"40"; when x"768" => DATA <= x"01"; when x"769" => DATA <= x"E8"; when x"76A" => DATA <= x"C9"; when x"76B" => DATA <= x"22"; when x"76C" => DATA <= x"D0"; when x"76D" => DATA <= x"F0"; when x"76E" => DATA <= x"CA"; when x"76F" => DATA <= x"C8"; when x"770" => DATA <= x"B9"; when x"771" => DATA <= x"00"; when x"772" => DATA <= x"01"; when x"773" => DATA <= x"C9"; when x"774" => DATA <= x"22"; when x"775" => DATA <= x"D0"; when x"776" => DATA <= x"DD"; when x"777" => DATA <= x"E8"; when x"778" => DATA <= x"B0"; when x"779" => DATA <= x"E4"; when x"77A" => DATA <= x"4C"; when x"77B" => DATA <= x"7D"; when x"77C" => DATA <= x"FA"; when x"77D" => DATA <= x"20"; when x"77E" => DATA <= x"76"; when x"77F" => DATA <= x"F8"; when x"780" => DATA <= x"20"; when x"781" => DATA <= x"7E"; when x"782" => DATA <= x"F8"; when x"783" => DATA <= x"B0"; when x"784" => DATA <= x"1B"; when x"785" => DATA <= x"85"; when x"786" => DATA <= x"CB"; when x"787" => DATA <= x"C8"; when x"788" => DATA <= x"B9"; when x"789" => DATA <= x"00"; when x"78A" => DATA <= x"01"; when x"78B" => DATA <= x"20"; when x"78C" => DATA <= x"7E"; when x"78D" => DATA <= x"F8"; when x"78E" => DATA <= x"B0"; when x"78F" => DATA <= x"0D"; when x"790" => DATA <= x"C8"; when x"791" => DATA <= x"06"; when x"792" => DATA <= x"CB"; when x"793" => DATA <= x"06"; when x"794" => DATA <= x"CB"; when x"795" => DATA <= x"06"; when x"796" => DATA <= x"CB"; when x"797" => DATA <= x"06"; when x"798" => DATA <= x"CB"; when x"799" => DATA <= x"05"; when x"79A" => DATA <= x"CB"; when x"79B" => DATA <= x"85"; when x"79C" => DATA <= x"CB"; when x"79D" => DATA <= x"A5"; when x"79E" => DATA <= x"CB"; when x"79F" => DATA <= x"18"; when x"7A0" => DATA <= x"60"; when x"7A1" => DATA <= x"20"; when x"7A2" => DATA <= x"D1"; when x"7A3" => DATA <= x"F7"; when x"7A4" => DATA <= x"3C"; when x"7A5" => DATA <= x"50"; when x"7A6" => DATA <= x"52"; when x"7A7" => DATA <= x"45"; when x"7A8" => DATA <= x"53"; when x"7A9" => DATA <= x"53"; when x"7AA" => DATA <= x"20"; when x"7AB" => DATA <= x"41"; when x"7AC" => DATA <= x"20"; when x"7AD" => DATA <= x"4B"; when x"7AE" => DATA <= x"45"; when x"7AF" => DATA <= x"59"; when x"7B0" => DATA <= x"3E"; when x"7B1" => DATA <= x"EA"; when x"7B2" => DATA <= x"20"; when x"7B3" => DATA <= x"E3"; when x"7B4" => DATA <= x"FF"; when x"7B5" => DATA <= x"48"; when x"7B6" => DATA <= x"A9"; when x"7B7" => DATA <= x"00"; when x"7B8" => DATA <= x"85"; when x"7B9" => DATA <= x"E0"; when x"7BA" => DATA <= x"20"; when x"7BB" => DATA <= x"D1"; when x"7BC" => DATA <= x"F7"; when x"7BD" => DATA <= x"20"; when x"7BE" => DATA <= x"20"; when x"7BF" => DATA <= x"20"; when x"7C0" => DATA <= x"20"; when x"7C1" => DATA <= x"20"; when x"7C2" => DATA <= x"20"; when x"7C3" => DATA <= x"20"; when x"7C4" => DATA <= x"20"; when x"7C5" => DATA <= x"20"; when x"7C6" => DATA <= x"20"; when x"7C7" => DATA <= x"20"; when x"7C8" => DATA <= x"20"; when x"7C9" => DATA <= x"20"; when x"7CA" => DATA <= x"EA"; when x"7CB" => DATA <= x"A9"; when x"7CC" => DATA <= x"00"; when x"7CD" => DATA <= x"85"; when x"7CE" => DATA <= x"E0"; when x"7CF" => DATA <= x"68"; when x"7D0" => DATA <= x"60"; when x"7D1" => DATA <= x"A9"; when x"7D2" => DATA <= x"20"; when x"7D3" => DATA <= x"20"; when x"7D4" => DATA <= x"F4"; when x"7D5" => DATA <= x"FF"; when x"7D6" => DATA <= x"E4"; when x"7D7" => DATA <= x"E0"; when x"7D8" => DATA <= x"B0"; when x"7D9" => DATA <= x"F7"; when x"7DA" => DATA <= x"60"; when x"7DB" => DATA <= x"A2"; when x"7DC" => DATA <= x"0A"; when x"7DD" => DATA <= x"4C"; when x"7DE" => DATA <= x"D6"; when x"7DF" => DATA <= x"E7"; when x"7E0" => DATA <= x"A2"; when x"7E1" => DATA <= x"10"; when x"7E2" => DATA <= x"4C"; when x"7E3" => DATA <= x"D6"; when x"7E4" => DATA <= x"E7"; when x"7E5" => DATA <= x"20"; when x"7E6" => DATA <= x"42"; when x"7E7" => DATA <= x"E4"; when x"7E8" => DATA <= x"20"; when x"7E9" => DATA <= x"FA"; when x"7EA" => DATA <= x"E7"; when x"7EB" => DATA <= x"A5"; when x"7EC" => DATA <= x"70"; when x"7ED" => DATA <= x"85"; when x"7EE" => DATA <= x"0D"; when x"7EF" => DATA <= x"85"; when x"7F0" => DATA <= x"23"; when x"7F1" => DATA <= x"A5"; when x"7F2" => DATA <= x"71"; when x"7F3" => DATA <= x"85"; when x"7F4" => DATA <= x"0E"; when x"7F5" => DATA <= x"85"; when x"7F6" => DATA <= x"24"; when x"7F7" => DATA <= x"4C"; when x"7F8" => DATA <= x"86"; when x"7F9" => DATA <= x"CE"; when x"7FA" => DATA <= x"A5"; when x"7FB" => DATA <= x"12"; when x"7FC" => DATA <= x"85"; when x"7FD" => DATA <= x"71"; when x"7FE" => DATA <= x"A0"; when x"7FF" => DATA <= x"00"; when x"800" => DATA <= x"84"; when x"801" => DATA <= x"70"; when x"802" => DATA <= x"A4"; when x"803" => DATA <= x"03"; when x"804" => DATA <= x"B1"; when x"805" => DATA <= x"70"; when x"806" => DATA <= x"C8"; when x"807" => DATA <= x"C9"; when x"808" => DATA <= x"0D"; when x"809" => DATA <= x"D0"; when x"80A" => DATA <= x"F9"; when x"80B" => DATA <= x"88"; when x"80C" => DATA <= x"18"; when x"80D" => DATA <= x"98"; when x"80E" => DATA <= x"65"; when x"80F" => DATA <= x"70"; when x"810" => DATA <= x"85"; when x"811" => DATA <= x"70"; when x"812" => DATA <= x"90"; when x"813" => DATA <= x"02"; when x"814" => DATA <= x"E6"; when x"815" => DATA <= x"71"; when x"816" => DATA <= x"A0"; when x"817" => DATA <= x"01"; when x"818" => DATA <= x"B1"; when x"819" => DATA <= x"70"; when x"81A" => DATA <= x"10"; when x"81B" => DATA <= x"E6"; when x"81C" => DATA <= x"18"; when x"81D" => DATA <= x"A5"; when x"81E" => DATA <= x"70"; when x"81F" => DATA <= x"69"; when x"820" => DATA <= x"02"; when x"821" => DATA <= x"85"; when x"822" => DATA <= x"70"; when x"823" => DATA <= x"90"; when x"824" => DATA <= x"02"; when x"825" => DATA <= x"E6"; when x"826" => DATA <= x"71"; when x"827" => DATA <= x"60"; when x"828" => DATA <= x"08"; when x"829" => DATA <= x"B5"; when x"82A" => DATA <= x"00"; when x"82B" => DATA <= x"85"; when x"82C" => DATA <= x"C9"; when x"82D" => DATA <= x"B5"; when x"82E" => DATA <= x"01"; when x"82F" => DATA <= x"85"; when x"830" => DATA <= x"CA"; when x"831" => DATA <= x"A0"; when x"832" => DATA <= x"00"; when x"833" => DATA <= x"B1"; when x"834" => DATA <= x"C9"; when x"835" => DATA <= x"99"; when x"836" => DATA <= x"40"; when x"837" => DATA <= x"01"; when x"838" => DATA <= x"C8"; when x"839" => DATA <= x"C9"; when x"83A" => DATA <= x"0D"; when x"83B" => DATA <= x"D0"; when x"83C" => DATA <= x"F6"; when x"83D" => DATA <= x"28"; when x"83E" => DATA <= x"08"; when x"83F" => DATA <= x"B0"; when x"840" => DATA <= x"05"; when x"841" => DATA <= x"A9"; when x"842" => DATA <= x"37"; when x"843" => DATA <= x"4C"; when x"844" => DATA <= x"48"; when x"845" => DATA <= x"E8"; when x"846" => DATA <= x"A9"; when x"847" => DATA <= x"31"; when x"848" => DATA <= x"20"; when x"849" => DATA <= x"47"; when x"84A" => DATA <= x"E5"; when x"84B" => DATA <= x"C9"; when x"84C" => DATA <= x"61"; when x"84D" => DATA <= x"B0"; when x"84E" => DATA <= x"09"; when x"84F" => DATA <= x"28"; when x"850" => DATA <= x"90"; when x"851" => DATA <= x"03"; when x"852" => DATA <= x"4C"; when x"853" => DATA <= x"A7"; when x"854" => DATA <= x"E6"; when x"855" => DATA <= x"A9"; when x"856" => DATA <= x"00"; when x"857" => DATA <= x"60"; when x"858" => DATA <= x"28"; when x"859" => DATA <= x"60"; when x"85A" => DATA <= x"48"; when x"85B" => DATA <= x"98"; when x"85C" => DATA <= x"F0"; when x"85D" => DATA <= x"03"; when x"85E" => DATA <= x"4C"; when x"85F" => DATA <= x"6D"; when x"860" => DATA <= x"E8"; when x"861" => DATA <= x"A0"; when x"862" => DATA <= x"61"; when x"863" => DATA <= x"20"; when x"864" => DATA <= x"72"; when x"865" => DATA <= x"E8"; when x"866" => DATA <= x"A0"; when x"867" => DATA <= x"62"; when x"868" => DATA <= x"20"; when x"869" => DATA <= x"72"; when x"86A" => DATA <= x"E8"; when x"86B" => DATA <= x"A0"; when x"86C" => DATA <= x"63"; when x"86D" => DATA <= x"20"; when x"86E" => DATA <= x"72"; when x"86F" => DATA <= x"E8"; when x"870" => DATA <= x"68"; when x"871" => DATA <= x"60"; when x"872" => DATA <= x"20"; when x"873" => DATA <= x"14"; when x"874" => DATA <= x"E9"; when x"875" => DATA <= x"69"; when x"876" => DATA <= x"10"; when x"877" => DATA <= x"20"; when x"878" => DATA <= x"48"; when x"879" => DATA <= x"E6"; when x"87A" => DATA <= x"60"; when x"87B" => DATA <= x"48"; when x"87C" => DATA <= x"98"; when x"87D" => DATA <= x"F0"; when x"87E" => DATA <= x"17"; when x"87F" => DATA <= x"20"; when x"880" => DATA <= x"60"; when x"881" => DATA <= x"E6"; when x"882" => DATA <= x"68"; when x"883" => DATA <= x"20"; when x"884" => DATA <= x"2D"; when x"885" => DATA <= x"E9"; when x"886" => DATA <= x"A9"; when x"887" => DATA <= x"01"; when x"888" => DATA <= x"20"; when x"889" => DATA <= x"24"; when x"88A" => DATA <= x"E9"; when x"88B" => DATA <= x"20"; when x"88C" => DATA <= x"1E"; when x"88D" => DATA <= x"E9"; when x"88E" => DATA <= x"69"; when x"88F" => DATA <= x"23"; when x"890" => DATA <= x"20"; when x"891" => DATA <= x"48"; when x"892" => DATA <= x"E6"; when x"893" => DATA <= x"4C"; when x"894" => DATA <= x"A7"; when x"895" => DATA <= x"E6"; when x"896" => DATA <= x"68"; when x"897" => DATA <= x"4C"; when x"898" => DATA <= x"E9"; when x"899" => DATA <= x"FF"; when x"89A" => DATA <= x"98"; when x"89B" => DATA <= x"F0"; when x"89C" => DATA <= x"23"; when x"89D" => DATA <= x"A9"; when x"89E" => DATA <= x"01"; when x"89F" => DATA <= x"20"; when x"8A0" => DATA <= x"24"; when x"8A1" => DATA <= x"E9"; when x"8A2" => DATA <= x"20"; when x"8A3" => DATA <= x"1E"; when x"8A4" => DATA <= x"E9"; when x"8A5" => DATA <= x"69"; when x"8A6" => DATA <= x"22"; when x"8A7" => DATA <= x"20"; when x"8A8" => DATA <= x"48"; when x"8A9" => DATA <= x"E6"; when x"8AA" => DATA <= x"C9"; when x"8AB" => DATA <= x"60"; when x"8AC" => DATA <= x"F0"; when x"8AD" => DATA <= x"06"; when x"8AE" => DATA <= x"20"; when x"8AF" => DATA <= x"A7"; when x"8B0" => DATA <= x"E6"; when x"8B1" => DATA <= x"4C"; when x"8B2" => DATA <= x"B8"; when x"8B3" => DATA <= x"E8"; when x"8B4" => DATA <= x"A9"; when x"8B5" => DATA <= x"FF"; when x"8B6" => DATA <= x"38"; when x"8B7" => DATA <= x"60"; when x"8B8" => DATA <= x"20"; when x"8B9" => DATA <= x"55"; when x"8BA" => DATA <= x"E6"; when x"8BB" => DATA <= x"20"; when x"8BC" => DATA <= x"36"; when x"8BD" => DATA <= x"E9"; when x"8BE" => DATA <= x"18"; when x"8BF" => DATA <= x"60"; when x"8C0" => DATA <= x"20"; when x"8C1" => DATA <= x"E6"; when x"8C2" => DATA <= x"FF"; when x"8C3" => DATA <= x"60"; when x"8C4" => DATA <= x"48"; when x"8C5" => DATA <= x"20"; when x"8C6" => DATA <= x"14"; when x"8C7" => DATA <= x"E9"; when x"8C8" => DATA <= x"69"; when x"8C9" => DATA <= x"15"; when x"8CA" => DATA <= x"20"; when x"8CB" => DATA <= x"48"; when x"8CC" => DATA <= x"E6"; when x"8CD" => DATA <= x"20"; when x"8CE" => DATA <= x"55"; when x"8CF" => DATA <= x"E6"; when x"8D0" => DATA <= x"20"; when x"8D1" => DATA <= x"DD"; when x"8D2" => DATA <= x"E8"; when x"8D3" => DATA <= x"68"; when x"8D4" => DATA <= x"D0"; when x"8D5" => DATA <= x"06"; when x"8D6" => DATA <= x"20"; when x"8D7" => DATA <= x"DD"; when x"8D8" => DATA <= x"E8"; when x"8D9" => DATA <= x"20"; when x"8DA" => DATA <= x"DD"; when x"8DB" => DATA <= x"E8"; when x"8DC" => DATA <= x"60"; when x"8DD" => DATA <= x"20"; when x"8DE" => DATA <= x"36"; when x"8DF" => DATA <= x"E9"; when x"8E0" => DATA <= x"95"; when x"8E1" => DATA <= x"00"; when x"8E2" => DATA <= x"20"; when x"8E3" => DATA <= x"36"; when x"8E4" => DATA <= x"E9"; when x"8E5" => DATA <= x"95"; when x"8E6" => DATA <= x"01"; when x"8E7" => DATA <= x"20"; when x"8E8" => DATA <= x"36"; when x"8E9" => DATA <= x"E9"; when x"8EA" => DATA <= x"95"; when x"8EB" => DATA <= x"02"; when x"8EC" => DATA <= x"20"; when x"8ED" => DATA <= x"36"; when x"8EE" => DATA <= x"E9"; when x"8EF" => DATA <= x"60"; when x"8F0" => DATA <= x"98"; when x"8F1" => DATA <= x"F0"; when x"8F2" => DATA <= x"20"; when x"8F3" => DATA <= x"20"; when x"8F4" => DATA <= x"60"; when x"8F5" => DATA <= x"E6"; when x"8F6" => DATA <= x"B5"; when x"8F7" => DATA <= x"00"; when x"8F8" => DATA <= x"20"; when x"8F9" => DATA <= x"2D"; when x"8FA" => DATA <= x"E9"; when x"8FB" => DATA <= x"B5"; when x"8FC" => DATA <= x"01"; when x"8FD" => DATA <= x"20"; when x"8FE" => DATA <= x"2D"; when x"8FF" => DATA <= x"E9"; when x"900" => DATA <= x"B5"; when x"901" => DATA <= x"02"; when x"902" => DATA <= x"20"; when x"903" => DATA <= x"2D"; when x"904" => DATA <= x"E9"; when x"905" => DATA <= x"A9"; when x"906" => DATA <= x"00"; when x"907" => DATA <= x"20"; when x"908" => DATA <= x"2D"; when x"909" => DATA <= x"E9"; when x"90A" => DATA <= x"20"; when x"90B" => DATA <= x"14"; when x"90C" => DATA <= x"E9"; when x"90D" => DATA <= x"69"; when x"90E" => DATA <= x"16"; when x"90F" => DATA <= x"20"; when x"910" => DATA <= x"48"; when x"911" => DATA <= x"E6"; when x"912" => DATA <= x"60"; when x"913" => DATA <= x"00"; when x"914" => DATA <= x"98"; when x"915" => DATA <= x"29"; when x"916" => DATA <= x"03"; when x"917" => DATA <= x"0A"; when x"918" => DATA <= x"0A"; when x"919" => DATA <= x"0A"; when x"91A" => DATA <= x"0A"; when x"91B" => DATA <= x"0A"; when x"91C" => DATA <= x"18"; when x"91D" => DATA <= x"60"; when x"91E" => DATA <= x"98"; when x"91F" => DATA <= x"29"; when x"920" => DATA <= x"03"; when x"921" => DATA <= x"4C"; when x"922" => DATA <= x"1A"; when x"923" => DATA <= x"E9"; when x"924" => DATA <= x"8D"; when x"925" => DATA <= x"01"; when x"926" => DATA <= x"B4"; when x"927" => DATA <= x"20"; when x"928" => DATA <= x"6B"; when x"929" => DATA <= x"E6"; when x"92A" => DATA <= x"4C"; when x"92B" => DATA <= x"47"; when x"92C" => DATA <= x"E6"; when x"92D" => DATA <= x"8D"; when x"92E" => DATA <= x"03"; when x"92F" => DATA <= x"B4"; when x"930" => DATA <= x"20"; when x"931" => DATA <= x"6B"; when x"932" => DATA <= x"E6"; when x"933" => DATA <= x"4C"; when x"934" => DATA <= x"47"; when x"935" => DATA <= x"E6"; when x"936" => DATA <= x"20"; when x"937" => DATA <= x"47"; when x"938" => DATA <= x"E6"; when x"939" => DATA <= x"AD"; when x"93A" => DATA <= x"02"; when x"93B" => DATA <= x"B4"; when x"93C" => DATA <= x"60"; when x"93D" => DATA <= x"20"; when x"93E" => DATA <= x"4D"; when x"93F" => DATA <= x"4D"; when x"940" => DATA <= x"43"; when x"941" => DATA <= x"20"; when x"942" => DATA <= x"20"; when x"943" => DATA <= x"53"; when x"944" => DATA <= x"44"; when x"945" => DATA <= x"53"; when x"946" => DATA <= x"44"; when x"947" => DATA <= x"48"; when x"948" => DATA <= x"43"; when x"949" => DATA <= x"20"; when x"94A" => DATA <= x"4E"; when x"94B" => DATA <= x"2F"; when x"94C" => DATA <= x"41"; when x"94D" => DATA <= x"6D"; when x"94E" => DATA <= x"E0"; when x"94F" => DATA <= x"D9"; when x"950" => DATA <= x"E0"; when x"951" => DATA <= x"52"; when x"952" => DATA <= x"FE"; when x"953" => DATA <= x"94"; when x"954" => DATA <= x"FE"; when x"955" => DATA <= x"4B"; when x"956" => DATA <= x"E4"; when x"957" => DATA <= x"AD"; when x"958" => DATA <= x"E4"; when x"959" => DATA <= x"C4"; when x"95A" => DATA <= x"E8"; when x"95B" => DATA <= x"F0"; when x"95C" => DATA <= x"E8"; when x"95D" => DATA <= x"9A"; when x"95E" => DATA <= x"E8"; when x"95F" => DATA <= x"7B"; when x"960" => DATA <= x"E8"; when x"961" => DATA <= x"28"; when x"962" => DATA <= x"E8"; when x"963" => DATA <= x"5A"; when x"964" => DATA <= x"E8"; when x"965" => DATA <= x"2A"; when x"966" => DATA <= x"4D"; when x"967" => DATA <= x"45"; when x"968" => DATA <= x"4E"; when x"969" => DATA <= x"55"; when x"96A" => DATA <= x"0D"; when x"96B" => DATA <= x"00"; when x"96C" => DATA <= x"43"; when x"96D" => DATA <= x"41"; when x"96E" => DATA <= x"54"; when x"96F" => DATA <= x"E1"; when x"970" => DATA <= x"3B"; when x"971" => DATA <= x"43"; when x"972" => DATA <= x"57"; when x"973" => DATA <= x"44"; when x"974" => DATA <= x"E1"; when x"975" => DATA <= x"CE"; when x"976" => DATA <= x"44"; when x"977" => DATA <= x"45"; when x"978" => DATA <= x"4C"; when x"979" => DATA <= x"45"; when x"97A" => DATA <= x"54"; when x"97B" => DATA <= x"45"; when x"97C" => DATA <= x"E2"; when x"97D" => DATA <= x"8B"; when x"97E" => DATA <= x"45"; when x"97F" => DATA <= x"58"; when x"980" => DATA <= x"45"; when x"981" => DATA <= x"43"; when x"982" => DATA <= x"E2"; when x"983" => DATA <= x"B8"; when x"984" => DATA <= x"52"; when x"985" => DATA <= x"55"; when x"986" => DATA <= x"4E"; when x"987" => DATA <= x"E4"; when x"988" => DATA <= x"61"; when x"989" => DATA <= x"48"; when x"98A" => DATA <= x"45"; when x"98B" => DATA <= x"4C"; when x"98C" => DATA <= x"50"; when x"98D" => DATA <= x"E3"; when x"98E" => DATA <= x"9A"; when x"98F" => DATA <= x"49"; when x"990" => DATA <= x"4E"; when x"991" => DATA <= x"46"; when x"992" => DATA <= x"4F"; when x"993" => DATA <= x"E4"; when x"994" => DATA <= x"2C"; when x"995" => DATA <= x"4C"; when x"996" => DATA <= x"4F"; when x"997" => DATA <= x"41"; when x"998" => DATA <= x"44"; when x"999" => DATA <= x"E4"; when x"99A" => DATA <= x"42"; when x"99B" => DATA <= x"4D"; when x"99C" => DATA <= x"4F"; when x"99D" => DATA <= x"4E"; when x"99E" => DATA <= x"FA"; when x"99F" => DATA <= x"1A"; when x"9A0" => DATA <= x"4E"; when x"9A1" => DATA <= x"4F"; when x"9A2" => DATA <= x"4D"; when x"9A3" => DATA <= x"4F"; when x"9A4" => DATA <= x"4E"; when x"9A5" => DATA <= x"FA"; when x"9A6" => DATA <= x"19"; when x"9A7" => DATA <= x"43"; when x"9A8" => DATA <= x"46"; when x"9A9" => DATA <= x"47"; when x"9AA" => DATA <= x"E1"; when x"9AB" => DATA <= x"FE"; when x"9AC" => DATA <= x"50"; when x"9AD" => DATA <= x"42"; when x"9AE" => DATA <= x"44"; when x"9AF" => DATA <= x"E1"; when x"9B0" => DATA <= x"F0"; when x"9B1" => DATA <= x"50"; when x"9B2" => DATA <= x"42"; when x"9B3" => DATA <= x"56"; when x"9B4" => DATA <= x"E1"; when x"9B5" => DATA <= x"F7"; when x"9B6" => DATA <= x"53"; when x"9B7" => DATA <= x"41"; when x"9B8" => DATA <= x"56"; when x"9B9" => DATA <= x"45"; when x"9BA" => DATA <= x"E4"; when x"9BB" => DATA <= x"A4"; when x"9BC" => DATA <= x"46"; when x"9BD" => DATA <= x"41"; when x"9BE" => DATA <= x"54"; when x"9BF" => DATA <= x"49"; when x"9C0" => DATA <= x"4E"; when x"9C1" => DATA <= x"46"; when x"9C2" => DATA <= x"4F"; when x"9C3" => DATA <= x"E3"; when x"9C4" => DATA <= x"4A"; when x"9C5" => DATA <= x"43"; when x"9C6" => DATA <= x"52"; when x"9C7" => DATA <= x"43"; when x"9C8" => DATA <= x"E2"; when x"9C9" => DATA <= x"2A"; when x"9CA" => DATA <= x"43"; when x"9CB" => DATA <= x"48"; when x"9CC" => DATA <= x"41"; when x"9CD" => DATA <= x"49"; when x"9CE" => DATA <= x"4E"; when x"9CF" => DATA <= x"E7"; when x"9D0" => DATA <= x"E5"; when x"9D1" => DATA <= x"E4"; when x"9D2" => DATA <= x"61"; when x"9D3" => DATA <= x"0D"; when x"9D4" => DATA <= x"44"; when x"9D5" => DATA <= x"49"; when x"9D6" => DATA <= x"53"; when x"9D7" => DATA <= x"4B"; when x"9D8" => DATA <= x"20"; when x"9D9" => DATA <= x"46"; when x"9DA" => DATA <= x"41"; when x"9DB" => DATA <= x"55"; when x"9DC" => DATA <= x"4C"; when x"9DD" => DATA <= x"54"; when x"9DE" => DATA <= x"0D"; when x"9DF" => DATA <= x"49"; when x"9E0" => DATA <= x"4E"; when x"9E1" => DATA <= x"54"; when x"9E2" => DATA <= x"45"; when x"9E3" => DATA <= x"52"; when x"9E4" => DATA <= x"4E"; when x"9E5" => DATA <= x"41"; when x"9E6" => DATA <= x"4C"; when x"9E7" => DATA <= x"20"; when x"9E8" => DATA <= x"45"; when x"9E9" => DATA <= x"52"; when x"9EA" => DATA <= x"52"; when x"9EB" => DATA <= x"4F"; when x"9EC" => DATA <= x"52"; when x"9ED" => DATA <= x"0D"; when x"9EE" => DATA <= x"4E"; when x"9EF" => DATA <= x"4F"; when x"9F0" => DATA <= x"54"; when x"9F1" => DATA <= x"20"; when x"9F2" => DATA <= x"52"; when x"9F3" => DATA <= x"45"; when x"9F4" => DATA <= x"41"; when x"9F5" => DATA <= x"44"; when x"9F6" => DATA <= x"59"; when x"9F7" => DATA <= x"0D"; when x"9F8" => DATA <= x"4E"; when x"9F9" => DATA <= x"4F"; when x"9FA" => DATA <= x"54"; when x"9FB" => DATA <= x"20"; when x"9FC" => DATA <= x"46"; when x"9FD" => DATA <= x"4F"; when x"9FE" => DATA <= x"55"; when x"9FF" => DATA <= x"4E"; when x"A00" => DATA <= x"44"; when x"A01" => DATA <= x"0D"; when x"A02" => DATA <= x"4E"; when x"A03" => DATA <= x"4F"; when x"A04" => DATA <= x"20"; when x"A05" => DATA <= x"50"; when x"A06" => DATA <= x"41"; when x"A07" => DATA <= x"54"; when x"A08" => DATA <= x"48"; when x"A09" => DATA <= x"0D"; when x"A0A" => DATA <= x"49"; when x"A0B" => DATA <= x"4E"; when x"A0C" => DATA <= x"56"; when x"A0D" => DATA <= x"41"; when x"A0E" => DATA <= x"4C"; when x"A0F" => DATA <= x"49"; when x"A10" => DATA <= x"44"; when x"A11" => DATA <= x"20"; when x"A12" => DATA <= x"4E"; when x"A13" => DATA <= x"41"; when x"A14" => DATA <= x"4D"; when x"A15" => DATA <= x"45"; when x"A16" => DATA <= x"0D"; when x"A17" => DATA <= x"41"; when x"A18" => DATA <= x"43"; when x"A19" => DATA <= x"43"; when x"A1A" => DATA <= x"45"; when x"A1B" => DATA <= x"53"; when x"A1C" => DATA <= x"53"; when x"A1D" => DATA <= x"20"; when x"A1E" => DATA <= x"44"; when x"A1F" => DATA <= x"45"; when x"A20" => DATA <= x"4E"; when x"A21" => DATA <= x"49"; when x"A22" => DATA <= x"45"; when x"A23" => DATA <= x"44"; when x"A24" => DATA <= x"0D"; when x"A25" => DATA <= x"45"; when x"A26" => DATA <= x"58"; when x"A27" => DATA <= x"49"; when x"A28" => DATA <= x"53"; when x"A29" => DATA <= x"54"; when x"A2A" => DATA <= x"53"; when x"A2B" => DATA <= x"0D"; when x"A2C" => DATA <= x"49"; when x"A2D" => DATA <= x"4E"; when x"A2E" => DATA <= x"56"; when x"A2F" => DATA <= x"41"; when x"A30" => DATA <= x"4C"; when x"A31" => DATA <= x"49"; when x"A32" => DATA <= x"44"; when x"A33" => DATA <= x"20"; when x"A34" => DATA <= x"4F"; when x"A35" => DATA <= x"42"; when x"A36" => DATA <= x"4A"; when x"A37" => DATA <= x"45"; when x"A38" => DATA <= x"43"; when x"A39" => DATA <= x"54"; when x"A3A" => DATA <= x"0D"; when x"A3B" => DATA <= x"57"; when x"A3C" => DATA <= x"52"; when x"A3D" => DATA <= x"49"; when x"A3E" => DATA <= x"54"; when x"A3F" => DATA <= x"45"; when x"A40" => DATA <= x"20"; when x"A41" => DATA <= x"50"; when x"A42" => DATA <= x"52"; when x"A43" => DATA <= x"4F"; when x"A44" => DATA <= x"54"; when x"A45" => DATA <= x"45"; when x"A46" => DATA <= x"43"; when x"A47" => DATA <= x"54"; when x"A48" => DATA <= x"45"; when x"A49" => DATA <= x"44"; when x"A4A" => DATA <= x"0D"; when x"A4B" => DATA <= x"49"; when x"A4C" => DATA <= x"4E"; when x"A4D" => DATA <= x"56"; when x"A4E" => DATA <= x"41"; when x"A4F" => DATA <= x"4C"; when x"A50" => DATA <= x"49"; when x"A51" => DATA <= x"44"; when x"A52" => DATA <= x"20"; when x"A53" => DATA <= x"44"; when x"A54" => DATA <= x"52"; when x"A55" => DATA <= x"49"; when x"A56" => DATA <= x"56"; when x"A57" => DATA <= x"45"; when x"A58" => DATA <= x"0D"; when x"A59" => DATA <= x"4E"; when x"A5A" => DATA <= x"4F"; when x"A5B" => DATA <= x"54"; when x"A5C" => DATA <= x"20"; when x"A5D" => DATA <= x"45"; when x"A5E" => DATA <= x"4E"; when x"A5F" => DATA <= x"41"; when x"A60" => DATA <= x"42"; when x"A61" => DATA <= x"4C"; when x"A62" => DATA <= x"45"; when x"A63" => DATA <= x"44"; when x"A64" => DATA <= x"0D"; when x"A65" => DATA <= x"4E"; when x"A66" => DATA <= x"4F"; when x"A67" => DATA <= x"20"; when x"A68" => DATA <= x"46"; when x"A69" => DATA <= x"49"; when x"A6A" => DATA <= x"4C"; when x"A6B" => DATA <= x"45"; when x"A6C" => DATA <= x"53"; when x"A6D" => DATA <= x"59"; when x"A6E" => DATA <= x"53"; when x"A6F" => DATA <= x"54"; when x"A70" => DATA <= x"45"; when x"A71" => DATA <= x"4D"; when x"A72" => DATA <= x"0D"; when x"A73" => DATA <= x"0D"; when x"A74" => DATA <= x"54"; when x"A75" => DATA <= x"49"; when x"A76" => DATA <= x"4D"; when x"A77" => DATA <= x"45"; when x"A78" => DATA <= x"4F"; when x"A79" => DATA <= x"55"; when x"A7A" => DATA <= x"54"; when x"A7B" => DATA <= x"0D"; when x"A7C" => DATA <= x"45"; when x"A7D" => DATA <= x"45"; when x"A7E" => DATA <= x"50"; when x"A7F" => DATA <= x"52"; when x"A80" => DATA <= x"4F"; when x"A81" => DATA <= x"4D"; when x"A82" => DATA <= x"20"; when x"A83" => DATA <= x"45"; when x"A84" => DATA <= x"52"; when x"A85" => DATA <= x"52"; when x"A86" => DATA <= x"4F"; when x"A87" => DATA <= x"52"; when x"A88" => DATA <= x"0D"; when x"A89" => DATA <= x"46"; when x"A8A" => DATA <= x"41"; when x"A8B" => DATA <= x"49"; when x"A8C" => DATA <= x"4C"; when x"A8D" => DATA <= x"45"; when x"A8E" => DATA <= x"44"; when x"A8F" => DATA <= x"0D"; when x"A90" => DATA <= x"54"; when x"A91" => DATA <= x"4F"; when x"A92" => DATA <= x"4F"; when x"A93" => DATA <= x"20"; when x"A94" => DATA <= x"4D"; when x"A95" => DATA <= x"41"; when x"A96" => DATA <= x"4E"; when x"A97" => DATA <= x"59"; when x"A98" => DATA <= x"0D"; when x"A99" => DATA <= x"53"; when x"A9A" => DATA <= x"49"; when x"A9B" => DATA <= x"4C"; when x"A9C" => DATA <= x"4C"; when x"A9D" => DATA <= x"59"; when x"A9E" => DATA <= x"0D"; when x"A9F" => DATA <= x"40"; when x"AA0" => DATA <= x"3D"; when x"AA1" => DATA <= x"38"; when x"AA2" => DATA <= x"3B"; when x"AA3" => DATA <= x"50"; when x"AA4" => DATA <= x"2E"; when x"AA5" => DATA <= x"24"; when x"AA6" => DATA <= x"36"; when x"AA7" => DATA <= x"24"; when x"AA8" => DATA <= x"37"; when x"AA9" => DATA <= x"27"; when x"AAA" => DATA <= x"22"; when x"AAB" => DATA <= x"45"; when x"AAC" => DATA <= x"52"; when x"AAD" => DATA <= x"52"; when x"AAE" => DATA <= x"4F"; when x"AAF" => DATA <= x"52"; when x"AB0" => DATA <= x"20"; when x"AB1" => DATA <= x"2D"; when x"AB2" => DATA <= x"20"; when x"AB3" => DATA <= x"22"; when x"AB4" => DATA <= x"24"; when x"AB5" => DATA <= x"21"; when x"AB6" => DATA <= x"23"; when x"AB7" => DATA <= x"44"; when x"AB8" => DATA <= x"35"; when x"AB9" => DATA <= x"26"; when x"ABA" => DATA <= x"23"; when x"ABB" => DATA <= x"46"; when x"ABC" => DATA <= x"46"; when x"ABD" => DATA <= x"46"; when x"ABE" => DATA <= x"46"; when x"ABF" => DATA <= x"3B"; when x"AC0" => DATA <= x"49"; when x"AC1" => DATA <= x"46"; when x"AC2" => DATA <= x"3F"; when x"AC3" => DATA <= x"31"; when x"AC4" => DATA <= x"7C"; when x"AC5" => DATA <= x"3F"; when x"AC6" => DATA <= x"32"; when x"AC7" => DATA <= x"50"; when x"AC8" => DATA <= x"2E"; when x"AC9" => DATA <= x"22"; when x"ACA" => DATA <= x"20"; when x"ACB" => DATA <= x"2D"; when x"ACC" => DATA <= x"20"; when x"ACD" => DATA <= x"4C"; when x"ACE" => DATA <= x"49"; when x"ACF" => DATA <= x"4E"; when x"AD0" => DATA <= x"45"; when x"AD1" => DATA <= x"20"; when x"AD2" => DATA <= x"22"; when x"AD3" => DATA <= x"21"; when x"AD4" => DATA <= x"31"; when x"AD5" => DATA <= x"26"; when x"AD6" => DATA <= x"20"; when x"AD7" => DATA <= x"23"; when x"AD8" => DATA <= x"46"; when x"AD9" => DATA <= x"46"; when x"ADA" => DATA <= x"46"; when x"ADB" => DATA <= x"46"; when x"ADC" => DATA <= x"0D"; when x"ADD" => DATA <= x"00"; when x"ADE" => DATA <= x"00"; when x"ADF" => DATA <= x"50"; when x"AE0" => DATA <= x"2E"; when x"AE1" => DATA <= x"27"; when x"AE2" => DATA <= x"3B"; when x"AE3" => DATA <= x"45"; when x"AE4" => DATA <= x"2E"; when x"AE5" => DATA <= x"0D"; when x"AE6" => DATA <= x"FF"; when x"AE7" => DATA <= x"FF"; when x"AE8" => DATA <= x"FF"; when x"AE9" => DATA <= x"FF"; when x"AEA" => DATA <= x"FF"; when x"AEB" => DATA <= x"FF"; when x"AEC" => DATA <= x"FF"; when x"AED" => DATA <= x"FF"; when x"AEE" => DATA <= x"FF"; when x"AEF" => DATA <= x"FF"; when x"AF0" => DATA <= x"FF"; when x"AF1" => DATA <= x"FF"; when x"AF2" => DATA <= x"FF"; when x"AF3" => DATA <= x"FF"; when x"AF4" => DATA <= x"FF"; when x"AF5" => DATA <= x"FF"; when x"AF6" => DATA <= x"FF"; when x"AF7" => DATA <= x"FF"; when x"AF8" => DATA <= x"FF"; when x"AF9" => DATA <= x"FF"; when x"AFA" => DATA <= x"FF"; when x"AFB" => DATA <= x"FF"; when x"AFC" => DATA <= x"FF"; when x"AFD" => DATA <= x"FF"; when x"AFE" => DATA <= x"FF"; when x"AFF" => DATA <= x"FF"; when x"B00" => DATA <= x"FF"; when x"B01" => DATA <= x"FF"; when x"B02" => DATA <= x"FF"; when x"B03" => DATA <= x"FF"; when x"B04" => DATA <= x"FF"; when x"B05" => DATA <= x"FF"; when x"B06" => DATA <= x"FF"; when x"B07" => DATA <= x"FF"; when x"B08" => DATA <= x"FF"; when x"B09" => DATA <= x"FF"; when x"B0A" => DATA <= x"FF"; when x"B0B" => DATA <= x"FF"; when x"B0C" => DATA <= x"FF"; when x"B0D" => DATA <= x"FF"; when x"B0E" => DATA <= x"FF"; when x"B0F" => DATA <= x"FF"; when x"B10" => DATA <= x"FF"; when x"B11" => DATA <= x"FF"; when x"B12" => DATA <= x"FF"; when x"B13" => DATA <= x"FF"; when x"B14" => DATA <= x"FF"; when x"B15" => DATA <= x"FF"; when x"B16" => DATA <= x"FF"; when x"B17" => DATA <= x"FF"; when x"B18" => DATA <= x"FF"; when x"B19" => DATA <= x"FF"; when x"B1A" => DATA <= x"FF"; when x"B1B" => DATA <= x"FF"; when x"B1C" => DATA <= x"FF"; when x"B1D" => DATA <= x"FF"; when x"B1E" => DATA <= x"FF"; when x"B1F" => DATA <= x"FF"; when x"B20" => DATA <= x"40"; when x"B21" => DATA <= x"BF"; when x"B22" => DATA <= x"A5"; when x"B23" => DATA <= x"06"; when x"B24" => DATA <= x"C9"; when x"B25" => DATA <= x"01"; when x"B26" => DATA <= x"D0"; when x"B27" => DATA <= x"10"; when x"B28" => DATA <= x"2C"; when x"B29" => DATA <= x"01"; when x"B2A" => DATA <= x"B0"; when x"B2B" => DATA <= x"30"; when x"B2C" => DATA <= x"0B"; when x"B2D" => DATA <= x"A2"; when x"B2E" => DATA <= x"00"; when x"B2F" => DATA <= x"A1"; when x"B30" => DATA <= x"05"; when x"B31" => DATA <= x"C9"; when x"B32" => DATA <= x"0D"; when x"B33" => DATA <= x"D0"; when x"B34" => DATA <= x"03"; when x"B35" => DATA <= x"4C"; when x"B36" => DATA <= x"72"; when x"B37" => DATA <= x"ED"; when x"B38" => DATA <= x"24"; when x"B39" => DATA <= x"FD"; when x"B3A" => DATA <= x"50"; when x"B3B" => DATA <= x"03"; when x"B3C" => DATA <= x"4C"; when x"B3D" => DATA <= x"85"; when x"B3E" => DATA <= x"EC"; when x"B3F" => DATA <= x"A5"; when x"B40" => DATA <= x"FD"; when x"B41" => DATA <= x"8D"; when x"B42" => DATA <= x"03"; when x"B43" => DATA <= x"04"; when x"B44" => DATA <= x"20"; when x"B45" => DATA <= x"8E"; when x"B46" => DATA <= x"ED"; when x"B47" => DATA <= x"20"; when x"B48" => DATA <= x"4D"; when x"B49" => DATA <= x"EC"; when x"B4A" => DATA <= x"AD"; when x"B4B" => DATA <= x"03"; when x"B4C" => DATA <= x"02"; when x"B4D" => DATA <= x"C9"; when x"B4E" => DATA <= x"EB"; when x"B4F" => DATA <= x"F0"; when x"B50" => DATA <= x"0E"; when x"B51" => DATA <= x"8D"; when x"B52" => DATA <= x"01"; when x"B53" => DATA <= x"04"; when x"B54" => DATA <= x"AD"; when x"B55" => DATA <= x"02"; when x"B56" => DATA <= x"02"; when x"B57" => DATA <= x"8D"; when x"B58" => DATA <= x"00"; when x"B59" => DATA <= x"04"; when x"B5A" => DATA <= x"A5"; when x"B5B" => DATA <= x"FD"; when x"B5C" => DATA <= x"8D"; when x"B5D" => DATA <= x"02"; when x"B5E" => DATA <= x"04"; when x"B5F" => DATA <= x"4C"; when x"B60" => DATA <= x"81"; when x"B61" => DATA <= x"EB"; when x"B62" => DATA <= x"E6"; when x"B63" => DATA <= x"FD"; when x"B64" => DATA <= x"A5"; when x"B65" => DATA <= x"FD"; when x"B66" => DATA <= x"8D"; when x"B67" => DATA <= x"FF"; when x"B68" => DATA <= x"BF"; when x"B69" => DATA <= x"C9"; when x"B6A" => DATA <= x"08"; when x"B6B" => DATA <= x"D0"; when x"B6C" => DATA <= x"07"; when x"B6D" => DATA <= x"A9"; when x"B6E" => DATA <= x"00"; when x"B6F" => DATA <= x"85"; when x"B70" => DATA <= x"FD"; when x"B71" => DATA <= x"8D"; when x"B72" => DATA <= x"FF"; when x"B73" => DATA <= x"BF"; when x"B74" => DATA <= x"20"; when x"B75" => DATA <= x"69"; when x"B76" => DATA <= x"EC"; when x"B77" => DATA <= x"A5"; when x"B78" => DATA <= x"FD"; when x"B79" => DATA <= x"CD"; when x"B7A" => DATA <= x"03"; when x"B7B" => DATA <= x"04"; when x"B7C" => DATA <= x"D0"; when x"B7D" => DATA <= x"03"; when x"B7E" => DATA <= x"4C"; when x"B7F" => DATA <= x"B8"; when x"B80" => DATA <= x"EC"; when x"B81" => DATA <= x"A9"; when x"B82" => DATA <= x"EB"; when x"B83" => DATA <= x"8D"; when x"B84" => DATA <= x"03"; when x"B85" => DATA <= x"02"; when x"B86" => DATA <= x"A9"; when x"B87" => DATA <= x"9C"; when x"B88" => DATA <= x"8D"; when x"B89" => DATA <= x"02"; when x"B8A" => DATA <= x"02"; when x"B8B" => DATA <= x"AD"; when x"B8C" => DATA <= x"00"; when x"B8D" => DATA <= x"A0"; when x"B8E" => DATA <= x"C9"; when x"B8F" => DATA <= x"40"; when x"B90" => DATA <= x"D0"; when x"B91" => DATA <= x"D0"; when x"B92" => DATA <= x"AD"; when x"B93" => DATA <= x"01"; when x"B94" => DATA <= x"A0"; when x"B95" => DATA <= x"C9"; when x"B96" => DATA <= x"BF"; when x"B97" => DATA <= x"D0"; when x"B98" => DATA <= x"C9"; when x"B99" => DATA <= x"4C"; when x"B9A" => DATA <= x"02"; when x"B9B" => DATA <= x"A0"; when x"B9C" => DATA <= x"68"; when x"B9D" => DATA <= x"8D"; when x"B9E" => DATA <= x"04"; when x"B9F" => DATA <= x"04"; when x"BA0" => DATA <= x"68"; when x"BA1" => DATA <= x"85"; when x"BA2" => DATA <= x"00"; when x"BA3" => DATA <= x"24"; when x"BA4" => DATA <= x"FD"; when x"BA5" => DATA <= x"50"; when x"BA6" => DATA <= x"03"; when x"BA7" => DATA <= x"4C"; when x"BA8" => DATA <= x"39"; when x"BA9" => DATA <= x"EC"; when x"BAA" => DATA <= x"C9"; when x"BAB" => DATA <= x"5E"; when x"BAC" => DATA <= x"D0"; when x"BAD" => DATA <= x"11"; when x"BAE" => DATA <= x"A4"; when x"BAF" => DATA <= x"5E"; when x"BB0" => DATA <= x"B1"; when x"BB1" => DATA <= x"05"; when x"BB2" => DATA <= x"C9"; when x"BB3" => DATA <= x"2E"; when x"BB4" => DATA <= x"D0"; when x"BB5" => DATA <= x"03"; when x"BB6" => DATA <= x"4C"; when x"BB7" => DATA <= x"B8"; when x"BB8" => DATA <= x"EC"; when x"BB9" => DATA <= x"A2"; when x"BBA" => DATA <= x"FF"; when x"BBB" => DATA <= x"9A"; when x"BBC" => DATA <= x"4C"; when x"BBD" => DATA <= x"62"; when x"BBE" => DATA <= x"EB"; when x"BBF" => DATA <= x"AD"; when x"BC0" => DATA <= x"00"; when x"BC1" => DATA <= x"04"; when x"BC2" => DATA <= x"8D"; when x"BC3" => DATA <= x"02"; when x"BC4" => DATA <= x"02"; when x"BC5" => DATA <= x"AD"; when x"BC6" => DATA <= x"01"; when x"BC7" => DATA <= x"04"; when x"BC8" => DATA <= x"8D"; when x"BC9" => DATA <= x"03"; when x"BCA" => DATA <= x"02"; when x"BCB" => DATA <= x"A5"; when x"BCC" => DATA <= x"00"; when x"BCD" => DATA <= x"C9"; when x"BCE" => DATA <= x"AE"; when x"BCF" => DATA <= x"F0"; when x"BD0" => DATA <= x"04"; when x"BD1" => DATA <= x"C9"; when x"BD2" => DATA <= x"1D"; when x"BD3" => DATA <= x"D0"; when x"BD4" => DATA <= x"49"; when x"BD5" => DATA <= x"BA"; when x"BD6" => DATA <= x"8E"; when x"BD7" => DATA <= x"B7"; when x"BD8" => DATA <= x"04"; when x"BD9" => DATA <= x"A2"; when x"BDA" => DATA <= x"FF"; when x"BDB" => DATA <= x"BD"; when x"BDC" => DATA <= x"00"; when x"BDD" => DATA <= x"01"; when x"BDE" => DATA <= x"EC"; when x"BDF" => DATA <= x"B7"; when x"BE0" => DATA <= x"04"; when x"BE1" => DATA <= x"90"; when x"BE2" => DATA <= x"3B"; when x"BE3" => DATA <= x"F0"; when x"BE4" => DATA <= x"39"; when x"BE5" => DATA <= x"CA"; when x"BE6" => DATA <= x"CA"; when x"BE7" => DATA <= x"29"; when x"BE8" => DATA <= x"F0"; when x"BE9" => DATA <= x"C9"; when x"BEA" => DATA <= x"A0"; when x"BEB" => DATA <= x"F0"; when x"BEC" => DATA <= x"EE"; when x"BED" => DATA <= x"E0"; when x"BEE" => DATA <= x"FD"; when x"BEF" => DATA <= x"F0"; when x"BF0" => DATA <= x"2D"; when x"BF1" => DATA <= x"8A"; when x"BF2" => DATA <= x"18"; when x"BF3" => DATA <= x"69"; when x"BF4" => DATA <= x"03"; when x"BF5" => DATA <= x"8D"; when x"BF6" => DATA <= x"B7"; when x"BF7" => DATA <= x"04"; when x"BF8" => DATA <= x"48"; when x"BF9" => DATA <= x"48"; when x"BFA" => DATA <= x"48"; when x"BFB" => DATA <= x"BA"; when x"BFC" => DATA <= x"BD"; when x"BFD" => DATA <= x"03"; when x"BFE" => DATA <= x"01"; when x"BFF" => DATA <= x"9D"; when x"C00" => DATA <= x"00"; when x"C01" => DATA <= x"01"; when x"C02" => DATA <= x"E8"; when x"C03" => DATA <= x"EC"; when x"C04" => DATA <= x"B7"; when x"C05" => DATA <= x"04"; when x"C06" => DATA <= x"D0"; when x"C07" => DATA <= x"F4"; when x"C08" => DATA <= x"AD"; when x"C09" => DATA <= x"B7"; when x"C0A" => DATA <= x"04"; when x"C0B" => DATA <= x"AA"; when x"C0C" => DATA <= x"CA"; when x"C0D" => DATA <= x"A5"; when x"C0E" => DATA <= x"FD"; when x"C0F" => DATA <= x"9D"; when x"C10" => DATA <= x"00"; when x"C11" => DATA <= x"01"; when x"C12" => DATA <= x"CA"; when x"C13" => DATA <= x"A9"; when x"C14" => DATA <= x"EF"; when x"C15" => DATA <= x"9D"; when x"C16" => DATA <= x"00"; when x"C17" => DATA <= x"01"; when x"C18" => DATA <= x"A9"; when x"C19" => DATA <= x"9E"; when x"C1A" => DATA <= x"CA"; when x"C1B" => DATA <= x"9D"; when x"C1C" => DATA <= x"00"; when x"C1D" => DATA <= x"01"; when x"C1E" => DATA <= x"20"; when x"C1F" => DATA <= x"4D"; when x"C20" => DATA <= x"EC"; when x"C21" => DATA <= x"20"; when x"C22" => DATA <= x"8E"; when x"C23" => DATA <= x"ED"; when x"C24" => DATA <= x"AD"; when x"C25" => DATA <= x"02"; when x"C26" => DATA <= x"04"; when x"C27" => DATA <= x"85"; when x"C28" => DATA <= x"FD"; when x"C29" => DATA <= x"8D"; when x"C2A" => DATA <= x"FF"; when x"C2B" => DATA <= x"BF"; when x"C2C" => DATA <= x"20"; when x"C2D" => DATA <= x"69"; when x"C2E" => DATA <= x"EC"; when x"C2F" => DATA <= x"A5"; when x"C30" => DATA <= x"00"; when x"C31" => DATA <= x"48"; when x"C32" => DATA <= x"AD"; when x"C33" => DATA <= x"04"; when x"C34" => DATA <= x"04"; when x"C35" => DATA <= x"48"; when x"C36" => DATA <= x"6C"; when x"C37" => DATA <= x"02"; when x"C38" => DATA <= x"02"; when x"C39" => DATA <= x"A5"; when x"C3A" => DATA <= x"FD"; when x"C3B" => DATA <= x"8D"; when x"C3C" => DATA <= x"02"; when x"C3D" => DATA <= x"04"; when x"C3E" => DATA <= x"A5"; when x"C3F" => DATA <= x"00"; when x"C40" => DATA <= x"C9"; when x"C41" => DATA <= x"5E"; when x"C42" => DATA <= x"F0"; when x"C43" => DATA <= x"03"; when x"C44" => DATA <= x"4C"; when x"C45" => DATA <= x"BF"; when x"C46" => DATA <= x"EB"; when x"C47" => DATA <= x"A2"; when x"C48" => DATA <= x"FF"; when x"C49" => DATA <= x"9A"; when x"C4A" => DATA <= x"4C"; when x"C4B" => DATA <= x"B8"; when x"C4C" => DATA <= x"EC"; when x"C4D" => DATA <= x"A5"; when x"C4E" => DATA <= x"FD"; when x"C4F" => DATA <= x"29"; when x"C50" => DATA <= x"0F"; when x"C51" => DATA <= x"AA"; when x"C52" => DATA <= x"E8"; when x"C53" => DATA <= x"A9"; when x"C54" => DATA <= x"00"; when x"C55" => DATA <= x"18"; when x"C56" => DATA <= x"69"; when x"C57" => DATA <= x"10"; when x"C58" => DATA <= x"CA"; when x"C59" => DATA <= x"D0"; when x"C5A" => DATA <= x"FA"; when x"C5B" => DATA <= x"A2"; when x"C5C" => DATA <= x"0F"; when x"C5D" => DATA <= x"A8"; when x"C5E" => DATA <= x"88"; when x"C5F" => DATA <= x"B5"; when x"C60" => DATA <= x"90"; when x"C61" => DATA <= x"99"; when x"C62" => DATA <= x"05"; when x"C63" => DATA <= x"04"; when x"C64" => DATA <= x"88"; when x"C65" => DATA <= x"CA"; when x"C66" => DATA <= x"10"; when x"C67" => DATA <= x"F7"; when x"C68" => DATA <= x"60"; when x"C69" => DATA <= x"A5"; when x"C6A" => DATA <= x"FD"; when x"C6B" => DATA <= x"29"; when x"C6C" => DATA <= x"0F"; when x"C6D" => DATA <= x"AA"; when x"C6E" => DATA <= x"E8"; when x"C6F" => DATA <= x"A9"; when x"C70" => DATA <= x"00"; when x"C71" => DATA <= x"18"; when x"C72" => DATA <= x"69"; when x"C73" => DATA <= x"10"; when x"C74" => DATA <= x"CA"; when x"C75" => DATA <= x"D0"; when x"C76" => DATA <= x"FA"; when x"C77" => DATA <= x"A2"; when x"C78" => DATA <= x"0F"; when x"C79" => DATA <= x"A8"; when x"C7A" => DATA <= x"88"; when x"C7B" => DATA <= x"B9"; when x"C7C" => DATA <= x"05"; when x"C7D" => DATA <= x"04"; when x"C7E" => DATA <= x"95"; when x"C7F" => DATA <= x"90"; when x"C80" => DATA <= x"88"; when x"C81" => DATA <= x"CA"; when x"C82" => DATA <= x"10"; when x"C83" => DATA <= x"F7"; when x"C84" => DATA <= x"60"; when x"C85" => DATA <= x"AD"; when x"C86" => DATA <= x"03"; when x"C87" => DATA <= x"02"; when x"C88" => DATA <= x"C9"; when x"C89" => DATA <= x"EB"; when x"C8A" => DATA <= x"F0"; when x"C8B" => DATA <= x"18"; when x"C8C" => DATA <= x"8D"; when x"C8D" => DATA <= x"01"; when x"C8E" => DATA <= x"04"; when x"C8F" => DATA <= x"AD"; when x"C90" => DATA <= x"02"; when x"C91" => DATA <= x"02"; when x"C92" => DATA <= x"8D"; when x"C93" => DATA <= x"00"; when x"C94" => DATA <= x"04"; when x"C95" => DATA <= x"A9"; when x"C96" => DATA <= x"EB"; when x"C97" => DATA <= x"8D"; when x"C98" => DATA <= x"03"; when x"C99" => DATA <= x"02"; when x"C9A" => DATA <= x"A9"; when x"C9B" => DATA <= x"9C"; when x"C9C" => DATA <= x"8D"; when x"C9D" => DATA <= x"02"; when x"C9E" => DATA <= x"02"; when x"C9F" => DATA <= x"A5"; when x"CA0" => DATA <= x"FD"; when x"CA1" => DATA <= x"8D"; when x"CA2" => DATA <= x"02"; when x"CA3" => DATA <= x"04"; when x"CA4" => DATA <= x"AD"; when x"CA5" => DATA <= x"00"; when x"CA6" => DATA <= x"A0"; when x"CA7" => DATA <= x"C9"; when x"CA8" => DATA <= x"40"; when x"CA9" => DATA <= x"D0"; when x"CAA" => DATA <= x"0A"; when x"CAB" => DATA <= x"AD"; when x"CAC" => DATA <= x"01"; when x"CAD" => DATA <= x"A0"; when x"CAE" => DATA <= x"C9"; when x"CAF" => DATA <= x"BF"; when x"CB0" => DATA <= x"D0"; when x"CB1" => DATA <= x"03"; when x"CB2" => DATA <= x"4C"; when x"CB3" => DATA <= x"02"; when x"CB4" => DATA <= x"A0"; when x"CB5" => DATA <= x"4C"; when x"CB6" => DATA <= x"58"; when x"CB7" => DATA <= x"C5"; when x"CB8" => DATA <= x"AD"; when x"CB9" => DATA <= x"00"; when x"CBA" => DATA <= x"04"; when x"CBB" => DATA <= x"8D"; when x"CBC" => DATA <= x"02"; when x"CBD" => DATA <= x"02"; when x"CBE" => DATA <= x"AD"; when x"CBF" => DATA <= x"01"; when x"CC0" => DATA <= x"04"; when x"CC1" => DATA <= x"8D"; when x"CC2" => DATA <= x"03"; when x"CC3" => DATA <= x"02"; when x"CC4" => DATA <= x"20"; when x"CC5" => DATA <= x"4D"; when x"CC6" => DATA <= x"EC"; when x"CC7" => DATA <= x"AD"; when x"CC8" => DATA <= x"02"; when x"CC9" => DATA <= x"04"; when x"CCA" => DATA <= x"85"; when x"CCB" => DATA <= x"FD"; when x"CCC" => DATA <= x"8D"; when x"CCD" => DATA <= x"FF"; when x"CCE" => DATA <= x"BF"; when x"CCF" => DATA <= x"20"; when x"CD0" => DATA <= x"69"; when x"CD1" => DATA <= x"EC"; when x"CD2" => DATA <= x"A2"; when x"CD3" => DATA <= x"FF"; when x"CD4" => DATA <= x"A4"; when x"CD5" => DATA <= x"5E"; when x"CD6" => DATA <= x"B1"; when x"CD7" => DATA <= x"05"; when x"CD8" => DATA <= x"C9"; when x"CD9" => DATA <= x"2E"; when x"CDA" => DATA <= x"D0"; when x"CDB" => DATA <= x"03"; when x"CDC" => DATA <= x"4C"; when x"CDD" => DATA <= x"58"; when x"CDE" => DATA <= x"C5"; when x"CDF" => DATA <= x"88"; when x"CE0" => DATA <= x"E8"; when x"CE1" => DATA <= x"C8"; when x"CE2" => DATA <= x"BD"; when x"CE3" => DATA <= x"7E"; when x"CE4" => DATA <= x"ED"; when x"CE5" => DATA <= x"C9"; when x"CE6" => DATA <= x"FF"; when x"CE7" => DATA <= x"F0"; when x"CE8" => DATA <= x"F3"; when x"CE9" => DATA <= x"C9"; when x"CEA" => DATA <= x"FE"; when x"CEB" => DATA <= x"F0"; when x"CEC" => DATA <= x"21"; when x"CED" => DATA <= x"D1"; when x"CEE" => DATA <= x"05"; when x"CEF" => DATA <= x"F0"; when x"CF0" => DATA <= x"EF"; when x"CF1" => DATA <= x"CA"; when x"CF2" => DATA <= x"B1"; when x"CF3" => DATA <= x"05"; when x"CF4" => DATA <= x"C9"; when x"CF5" => DATA <= x"2E"; when x"CF6" => DATA <= x"F0"; when x"CF7" => DATA <= x"0D"; when x"CF8" => DATA <= x"E8"; when x"CF9" => DATA <= x"BD"; when x"CFA" => DATA <= x"7E"; when x"CFB" => DATA <= x"ED"; when x"CFC" => DATA <= x"C9"; when x"CFD" => DATA <= x"FE"; when x"CFE" => DATA <= x"D0"; when x"CFF" => DATA <= x"F8"; when x"D00" => DATA <= x"E8"; when x"D01" => DATA <= x"E8"; when x"D02" => DATA <= x"4C"; when x"D03" => DATA <= x"D4"; when x"D04" => DATA <= x"EC"; when x"D05" => DATA <= x"E8"; when x"D06" => DATA <= x"BD"; when x"D07" => DATA <= x"7E"; when x"D08" => DATA <= x"ED"; when x"D09" => DATA <= x"C9"; when x"D0A" => DATA <= x"FE"; when x"D0B" => DATA <= x"D0"; when x"D0C" => DATA <= x"F8"; when x"D0D" => DATA <= x"C8"; when x"D0E" => DATA <= x"BD"; when x"D0F" => DATA <= x"7F"; when x"D10" => DATA <= x"ED"; when x"D11" => DATA <= x"85"; when x"D12" => DATA <= x"53"; when x"D13" => DATA <= x"BD"; when x"D14" => DATA <= x"80"; when x"D15" => DATA <= x"ED"; when x"D16" => DATA <= x"85"; when x"D17" => DATA <= x"52"; when x"D18" => DATA <= x"84"; when x"D19" => DATA <= x"03"; when x"D1A" => DATA <= x"A6"; when x"D1B" => DATA <= x"04"; when x"D1C" => DATA <= x"6C"; when x"D1D" => DATA <= x"52"; when x"D1E" => DATA <= x"00"; when x"D1F" => DATA <= x"20"; when x"D20" => DATA <= x"E1"; when x"D21" => DATA <= x"C4"; when x"D22" => DATA <= x"20"; when x"D23" => DATA <= x"8E"; when x"D24" => DATA <= x"ED"; when x"D25" => DATA <= x"A6"; when x"D26" => DATA <= x"04"; when x"D27" => DATA <= x"CA"; when x"D28" => DATA <= x"86"; when x"D29" => DATA <= x"04"; when x"D2A" => DATA <= x"B5"; when x"D2B" => DATA <= x"16"; when x"D2C" => DATA <= x"29"; when x"D2D" => DATA <= x"0F"; when x"D2E" => DATA <= x"09"; when x"D2F" => DATA <= x"40"; when x"D30" => DATA <= x"85"; when x"D31" => DATA <= x"FD"; when x"D32" => DATA <= x"8D"; when x"D33" => DATA <= x"FF"; when x"D34" => DATA <= x"BF"; when x"D35" => DATA <= x"AD"; when x"D36" => DATA <= x"00"; when x"D37" => DATA <= x"A0"; when x"D38" => DATA <= x"C9"; when x"D39" => DATA <= x"40"; when x"D3A" => DATA <= x"D0"; when x"D3B" => DATA <= x"07"; when x"D3C" => DATA <= x"AD"; when x"D3D" => DATA <= x"01"; when x"D3E" => DATA <= x"A0"; when x"D3F" => DATA <= x"C9"; when x"D40" => DATA <= x"BF"; when x"D41" => DATA <= x"F0"; when x"D42" => DATA <= x"16"; when x"D43" => DATA <= x"20"; when x"D44" => DATA <= x"D1"; when x"D45" => DATA <= x"F7"; when x"D46" => DATA <= x"4E"; when x"D47" => DATA <= x"4F"; when x"D48" => DATA <= x"20"; when x"D49" => DATA <= x"52"; when x"D4A" => DATA <= x"4F"; when x"D4B" => DATA <= x"4D"; when x"D4C" => DATA <= x"20"; when x"D4D" => DATA <= x"41"; when x"D4E" => DATA <= x"56"; when x"D4F" => DATA <= x"41"; when x"D50" => DATA <= x"49"; when x"D51" => DATA <= x"4C"; when x"D52" => DATA <= x"41"; when x"D53" => DATA <= x"42"; when x"D54" => DATA <= x"4C"; when x"D55" => DATA <= x"45"; when x"D56" => DATA <= x"0D"; when x"D57" => DATA <= x"0A"; when x"D58" => DATA <= x"EA"; when x"D59" => DATA <= x"AD"; when x"D5A" => DATA <= x"02"; when x"D5B" => DATA <= x"04"; when x"D5C" => DATA <= x"09"; when x"D5D" => DATA <= x"40"; when x"D5E" => DATA <= x"C5"; when x"D5F" => DATA <= x"FD"; when x"D60" => DATA <= x"F0"; when x"D61" => DATA <= x"0A"; when x"D62" => DATA <= x"A9"; when x"D63" => DATA <= x"D8"; when x"D64" => DATA <= x"8D"; when x"D65" => DATA <= x"02"; when x"D66" => DATA <= x"02"; when x"D67" => DATA <= x"A9"; when x"D68" => DATA <= x"C9"; when x"D69" => DATA <= x"8D"; when x"D6A" => DATA <= x"03"; when x"D6B" => DATA <= x"02"; when x"D6C" => DATA <= x"4C"; when x"D6D" => DATA <= x"5B"; when x"D6E" => DATA <= x"C5"; when x"D6F" => DATA <= x"20"; when x"D70" => DATA <= x"E4"; when x"D71" => DATA <= x"C4"; when x"D72" => DATA <= x"A5"; when x"D73" => DATA <= x"FD"; when x"D74" => DATA <= x"29"; when x"D75" => DATA <= x"0F"; when x"D76" => DATA <= x"85"; when x"D77" => DATA <= x"FD"; when x"D78" => DATA <= x"8D"; when x"D79" => DATA <= x"FF"; when x"D7A" => DATA <= x"BF"; when x"D7B" => DATA <= x"4C"; when x"D7C" => DATA <= x"5B"; when x"D7D" => DATA <= x"C5"; when x"D7E" => DATA <= x"52"; when x"D7F" => DATA <= x"4F"; when x"D80" => DATA <= x"4D"; when x"D81" => DATA <= x"FE"; when x"D82" => DATA <= x"ED"; when x"D83" => DATA <= x"1F"; when x"D84" => DATA <= x"55"; when x"D85" => DATA <= x"4E"; when x"D86" => DATA <= x"4C"; when x"D87" => DATA <= x"4F"; when x"D88" => DATA <= x"43"; when x"D89" => DATA <= x"4B"; when x"D8A" => DATA <= x"FE"; when x"D8B" => DATA <= x"ED"; when x"D8C" => DATA <= x"6F"; when x"D8D" => DATA <= x"FF"; when x"D8E" => DATA <= x"08"; when x"D8F" => DATA <= x"78"; when x"D90" => DATA <= x"A2"; when x"D91" => DATA <= x"00"; when x"D92" => DATA <= x"A0"; when x"D93" => DATA <= x"00"; when x"D94" => DATA <= x"BD"; when x"D95" => DATA <= x"01"; when x"D96" => DATA <= x"02"; when x"D97" => DATA <= x"29"; when x"D98" => DATA <= x"F0"; when x"D99" => DATA <= x"C9"; when x"D9A" => DATA <= x"A0"; when x"D9B" => DATA <= x"D0"; when x"D9C" => DATA <= x"25"; when x"D9D" => DATA <= x"E0"; when x"D9E" => DATA <= x"02"; when x"D9F" => DATA <= x"F0"; when x"DA0" => DATA <= x"21"; when x"DA1" => DATA <= x"BD"; when x"DA2" => DATA <= x"00"; when x"DA3" => DATA <= x"02"; when x"DA4" => DATA <= x"99"; when x"DA5" => DATA <= x"87"; when x"DA6" => DATA <= x"04"; when x"DA7" => DATA <= x"BD"; when x"DA8" => DATA <= x"01"; when x"DA9" => DATA <= x"02"; when x"DAA" => DATA <= x"99"; when x"DAB" => DATA <= x"86"; when x"DAC" => DATA <= x"04"; when x"DAD" => DATA <= x"A5"; when x"DAE" => DATA <= x"FD"; when x"DAF" => DATA <= x"99"; when x"DB0" => DATA <= x"88"; when x"DB1" => DATA <= x"04"; when x"DB2" => DATA <= x"8A"; when x"DB3" => DATA <= x"0A"; when x"DB4" => DATA <= x"0A"; when x"DB5" => DATA <= x"18"; when x"DB6" => DATA <= x"69"; when x"DB7" => DATA <= x"F1"; when x"DB8" => DATA <= x"9D"; when x"DB9" => DATA <= x"00"; when x"DBA" => DATA <= x"02"; when x"DBB" => DATA <= x"A9"; when x"DBC" => DATA <= x"ED"; when x"DBD" => DATA <= x"69"; when x"DBE" => DATA <= x"00"; when x"DBF" => DATA <= x"9D"; when x"DC0" => DATA <= x"01"; when x"DC1" => DATA <= x"02"; when x"DC2" => DATA <= x"E8"; when x"DC3" => DATA <= x"E8"; when x"DC4" => DATA <= x"C8"; when x"DC5" => DATA <= x"C8"; when x"DC6" => DATA <= x"C8"; when x"DC7" => DATA <= x"E0"; when x"DC8" => DATA <= x"1C"; when x"DC9" => DATA <= x"D0"; when x"DCA" => DATA <= x"C9"; when x"DCB" => DATA <= x"AD"; when x"DCC" => DATA <= x"FF"; when x"DCD" => DATA <= x"03"; when x"DCE" => DATA <= x"29"; when x"DCF" => DATA <= x"F0"; when x"DD0" => DATA <= x"C9"; when x"DD1" => DATA <= x"A0"; when x"DD2" => DATA <= x"D0"; when x"DD3" => DATA <= x"1B"; when x"DD4" => DATA <= x"AD"; when x"DD5" => DATA <= x"FF"; when x"DD6" => DATA <= x"03"; when x"DD7" => DATA <= x"99"; when x"DD8" => DATA <= x"86"; when x"DD9" => DATA <= x"04"; when x"DDA" => DATA <= x"AD"; when x"DDB" => DATA <= x"FE"; when x"DDC" => DATA <= x"03"; when x"DDD" => DATA <= x"99"; when x"DDE" => DATA <= x"87"; when x"DDF" => DATA <= x"04"; when x"DE0" => DATA <= x"A9"; when x"DE1" => DATA <= x"EE"; when x"DE2" => DATA <= x"8D"; when x"DE3" => DATA <= x"FF"; when x"DE4" => DATA <= x"03"; when x"DE5" => DATA <= x"A9"; when x"DE6" => DATA <= x"61"; when x"DE7" => DATA <= x"8D"; when x"DE8" => DATA <= x"FE"; when x"DE9" => DATA <= x"03"; when x"DEA" => DATA <= x"A5"; when x"DEB" => DATA <= x"FD"; when x"DEC" => DATA <= x"99"; when x"DED" => DATA <= x"88"; when x"DEE" => DATA <= x"04"; when x"DEF" => DATA <= x"28"; when x"DF0" => DATA <= x"60"; when x"DF1" => DATA <= x"20"; when x"DF2" => DATA <= x"78"; when x"DF3" => DATA <= x"EE"; when x"DF4" => DATA <= x"A2"; when x"DF5" => DATA <= x"00"; when x"DF6" => DATA <= x"4C"; when x"DF7" => DATA <= x"A5"; when x"DF8" => DATA <= x"EE"; when x"DF9" => DATA <= x"EA"; when x"DFA" => DATA <= x"EA"; when x"DFB" => DATA <= x"EA"; when x"DFC" => DATA <= x"EA"; when x"DFD" => DATA <= x"EA"; when x"DFE" => DATA <= x"4C"; when x"DFF" => DATA <= x"58"; when x"E00" => DATA <= x"C5"; when x"E01" => DATA <= x"20"; when x"E02" => DATA <= x"78"; when x"E03" => DATA <= x"EE"; when x"E04" => DATA <= x"A2"; when x"E05" => DATA <= x"06"; when x"E06" => DATA <= x"4C"; when x"E07" => DATA <= x"A5"; when x"E08" => DATA <= x"EE"; when x"E09" => DATA <= x"20"; when x"E0A" => DATA <= x"69"; when x"E0B" => DATA <= x"EE"; when x"E0C" => DATA <= x"A2"; when x"E0D" => DATA <= x"09"; when x"E0E" => DATA <= x"4C"; when x"E0F" => DATA <= x"EB"; when x"E10" => DATA <= x"EE"; when x"E11" => DATA <= x"20"; when x"E12" => DATA <= x"69"; when x"E13" => DATA <= x"EE"; when x"E14" => DATA <= x"A2"; when x"E15" => DATA <= x"0C"; when x"E16" => DATA <= x"4C"; when x"E17" => DATA <= x"EB"; when x"E18" => DATA <= x"EE"; when x"E19" => DATA <= x"20"; when x"E1A" => DATA <= x"69"; when x"E1B" => DATA <= x"EE"; when x"E1C" => DATA <= x"A2"; when x"E1D" => DATA <= x"0F"; when x"E1E" => DATA <= x"4C"; when x"E1F" => DATA <= x"EB"; when x"E20" => DATA <= x"EE"; when x"E21" => DATA <= x"20"; when x"E22" => DATA <= x"69"; when x"E23" => DATA <= x"EE"; when x"E24" => DATA <= x"A2"; when x"E25" => DATA <= x"12"; when x"E26" => DATA <= x"4C"; when x"E27" => DATA <= x"EB"; when x"E28" => DATA <= x"EE"; when x"E29" => DATA <= x"20"; when x"E2A" => DATA <= x"69"; when x"E2B" => DATA <= x"EE"; when x"E2C" => DATA <= x"A2"; when x"E2D" => DATA <= x"15"; when x"E2E" => DATA <= x"4C"; when x"E2F" => DATA <= x"EB"; when x"E30" => DATA <= x"EE"; when x"E31" => DATA <= x"20"; when x"E32" => DATA <= x"69"; when x"E33" => DATA <= x"EE"; when x"E34" => DATA <= x"A2"; when x"E35" => DATA <= x"18"; when x"E36" => DATA <= x"4C"; when x"E37" => DATA <= x"EB"; when x"E38" => DATA <= x"EE"; when x"E39" => DATA <= x"20"; when x"E3A" => DATA <= x"69"; when x"E3B" => DATA <= x"EE"; when x"E3C" => DATA <= x"A2"; when x"E3D" => DATA <= x"1B"; when x"E3E" => DATA <= x"4C"; when x"E3F" => DATA <= x"EB"; when x"E40" => DATA <= x"EE"; when x"E41" => DATA <= x"20"; when x"E42" => DATA <= x"69"; when x"E43" => DATA <= x"EE"; when x"E44" => DATA <= x"A2"; when x"E45" => DATA <= x"1E"; when x"E46" => DATA <= x"4C"; when x"E47" => DATA <= x"EB"; when x"E48" => DATA <= x"EE"; when x"E49" => DATA <= x"20"; when x"E4A" => DATA <= x"69"; when x"E4B" => DATA <= x"EE"; when x"E4C" => DATA <= x"A2"; when x"E4D" => DATA <= x"21"; when x"E4E" => DATA <= x"4C"; when x"E4F" => DATA <= x"EB"; when x"E50" => DATA <= x"EE"; when x"E51" => DATA <= x"20"; when x"E52" => DATA <= x"69"; when x"E53" => DATA <= x"EE"; when x"E54" => DATA <= x"A2"; when x"E55" => DATA <= x"24"; when x"E56" => DATA <= x"4C"; when x"E57" => DATA <= x"EB"; when x"E58" => DATA <= x"EE"; when x"E59" => DATA <= x"20"; when x"E5A" => DATA <= x"69"; when x"E5B" => DATA <= x"EE"; when x"E5C" => DATA <= x"A2"; when x"E5D" => DATA <= x"27"; when x"E5E" => DATA <= x"4C"; when x"E5F" => DATA <= x"EB"; when x"E60" => DATA <= x"EE"; when x"E61" => DATA <= x"20"; when x"E62" => DATA <= x"69"; when x"E63" => DATA <= x"EE"; when x"E64" => DATA <= x"A2"; when x"E65" => DATA <= x"2A"; when x"E66" => DATA <= x"4C"; when x"E67" => DATA <= x"EB"; when x"E68" => DATA <= x"EE"; when x"E69" => DATA <= x"08"; when x"E6A" => DATA <= x"8D"; when x"E6B" => DATA <= x"B4"; when x"E6C" => DATA <= x"04"; when x"E6D" => DATA <= x"68"; when x"E6E" => DATA <= x"8D"; when x"E6F" => DATA <= x"B5"; when x"E70" => DATA <= x"04"; when x"E71" => DATA <= x"8E"; when x"E72" => DATA <= x"B7"; when x"E73" => DATA <= x"04"; when x"E74" => DATA <= x"8C"; when x"E75" => DATA <= x"B6"; when x"E76" => DATA <= x"04"; when x"E77" => DATA <= x"60"; when x"E78" => DATA <= x"08"; when x"E79" => DATA <= x"8D"; when x"E7A" => DATA <= x"BC"; when x"E7B" => DATA <= x"04"; when x"E7C" => DATA <= x"68"; when x"E7D" => DATA <= x"8D"; when x"E7E" => DATA <= x"BD"; when x"E7F" => DATA <= x"04"; when x"E80" => DATA <= x"8E"; when x"E81" => DATA <= x"BF"; when x"E82" => DATA <= x"04"; when x"E83" => DATA <= x"8C"; when x"E84" => DATA <= x"C0"; when x"E85" => DATA <= x"04"; when x"E86" => DATA <= x"60"; when x"E87" => DATA <= x"AC"; when x"E88" => DATA <= x"B6"; when x"E89" => DATA <= x"04"; when x"E8A" => DATA <= x"AE"; when x"E8B" => DATA <= x"B7"; when x"E8C" => DATA <= x"04"; when x"E8D" => DATA <= x"AD"; when x"E8E" => DATA <= x"B5"; when x"E8F" => DATA <= x"04"; when x"E90" => DATA <= x"48"; when x"E91" => DATA <= x"AD"; when x"E92" => DATA <= x"B4"; when x"E93" => DATA <= x"04"; when x"E94" => DATA <= x"28"; when x"E95" => DATA <= x"60"; when x"E96" => DATA <= x"AE"; when x"E97" => DATA <= x"BF"; when x"E98" => DATA <= x"04"; when x"E99" => DATA <= x"AC"; when x"E9A" => DATA <= x"C0"; when x"E9B" => DATA <= x"04"; when x"E9C" => DATA <= x"AD"; when x"E9D" => DATA <= x"BD"; when x"E9E" => DATA <= x"04"; when x"E9F" => DATA <= x"48"; when x"EA0" => DATA <= x"AD"; when x"EA1" => DATA <= x"BC"; when x"EA2" => DATA <= x"04"; when x"EA3" => DATA <= x"28"; when x"EA4" => DATA <= x"60"; when x"EA5" => DATA <= x"68"; when x"EA6" => DATA <= x"8D"; when x"EA7" => DATA <= x"BC"; when x"EA8" => DATA <= x"04"; when x"EA9" => DATA <= x"68"; when x"EAA" => DATA <= x"48"; when x"EAB" => DATA <= x"8D"; when x"EAC" => DATA <= x"BE"; when x"EAD" => DATA <= x"04"; when x"EAE" => DATA <= x"A5"; when x"EAF" => DATA <= x"FD"; when x"EB0" => DATA <= x"48"; when x"EB1" => DATA <= x"BD"; when x"EB2" => DATA <= x"88"; when x"EB3" => DATA <= x"04"; when x"EB4" => DATA <= x"85"; when x"EB5" => DATA <= x"FD"; when x"EB6" => DATA <= x"8D"; when x"EB7" => DATA <= x"FF"; when x"EB8" => DATA <= x"BF"; when x"EB9" => DATA <= x"BD"; when x"EBA" => DATA <= x"86"; when x"EBB" => DATA <= x"04"; when x"EBC" => DATA <= x"8D"; when x"EBD" => DATA <= x"BB"; when x"EBE" => DATA <= x"04"; when x"EBF" => DATA <= x"BD"; when x"EC0" => DATA <= x"87"; when x"EC1" => DATA <= x"04"; when x"EC2" => DATA <= x"8D"; when x"EC3" => DATA <= x"BA"; when x"EC4" => DATA <= x"04"; when x"EC5" => DATA <= x"A9"; when x"EC6" => DATA <= x"EE"; when x"EC7" => DATA <= x"48"; when x"EC8" => DATA <= x"A9"; when x"EC9" => DATA <= x"D9"; when x"ECA" => DATA <= x"48"; when x"ECB" => DATA <= x"AD"; when x"ECC" => DATA <= x"BE"; when x"ECD" => DATA <= x"04"; when x"ECE" => DATA <= x"48"; when x"ECF" => DATA <= x"AD"; when x"ED0" => DATA <= x"BC"; when x"ED1" => DATA <= x"04"; when x"ED2" => DATA <= x"48"; when x"ED3" => DATA <= x"20"; when x"ED4" => DATA <= x"96"; when x"ED5" => DATA <= x"EE"; when x"ED6" => DATA <= x"6C"; when x"ED7" => DATA <= x"BA"; when x"ED8" => DATA <= x"04"; when x"ED9" => DATA <= x"20"; when x"EDA" => DATA <= x"78"; when x"EDB" => DATA <= x"EE"; when x"EDC" => DATA <= x"68"; when x"EDD" => DATA <= x"85"; when x"EDE" => DATA <= x"FD"; when x"EDF" => DATA <= x"8D"; when x"EE0" => DATA <= x"FF"; when x"EE1" => DATA <= x"BF"; when x"EE2" => DATA <= x"28"; when x"EE3" => DATA <= x"AD"; when x"EE4" => DATA <= x"BE"; when x"EE5" => DATA <= x"04"; when x"EE6" => DATA <= x"48"; when x"EE7" => DATA <= x"20"; when x"EE8" => DATA <= x"96"; when x"EE9" => DATA <= x"EE"; when x"EEA" => DATA <= x"40"; when x"EEB" => DATA <= x"8E"; when x"EEC" => DATA <= x"04"; when x"EED" => DATA <= x"04"; when x"EEE" => DATA <= x"8A"; when x"EEF" => DATA <= x"48"; when x"EF0" => DATA <= x"A5"; when x"EF1" => DATA <= x"60"; when x"EF2" => DATA <= x"8D"; when x"EF3" => DATA <= x"C1"; when x"EF4" => DATA <= x"04"; when x"EF5" => DATA <= x"BD"; when x"EF6" => DATA <= x"88"; when x"EF7" => DATA <= x"04"; when x"EF8" => DATA <= x"C5"; when x"EF9" => DATA <= x"FD"; when x"EFA" => DATA <= x"F0"; when x"EFB" => DATA <= x"6B"; when x"EFC" => DATA <= x"E0"; when x"EFD" => DATA <= x"15"; when x"EFE" => DATA <= x"D0"; when x"EFF" => DATA <= x"06"; when x"F00" => DATA <= x"20"; when x"F01" => DATA <= x"8E"; when x"F02" => DATA <= x"ED"; when x"F03" => DATA <= x"AE"; when x"F04" => DATA <= x"04"; when x"F05" => DATA <= x"04"; when x"F06" => DATA <= x"E0"; when x"F07" => DATA <= x"1E"; when x"F08" => DATA <= x"F0"; when x"F09" => DATA <= x"5D"; when x"F0A" => DATA <= x"E0"; when x"F0B" => DATA <= x"21"; when x"F0C" => DATA <= x"F0"; when x"F0D" => DATA <= x"59"; when x"F0E" => DATA <= x"20"; when x"F0F" => DATA <= x"4D"; when x"F10" => DATA <= x"EC"; when x"F11" => DATA <= x"AE"; when x"F12" => DATA <= x"04"; when x"F13" => DATA <= x"04"; when x"F14" => DATA <= x"A5"; when x"F15" => DATA <= x"FD"; when x"F16" => DATA <= x"48"; when x"F17" => DATA <= x"BD"; when x"F18" => DATA <= x"87"; when x"F19" => DATA <= x"04"; when x"F1A" => DATA <= x"8D"; when x"F1B" => DATA <= x"B8"; when x"F1C" => DATA <= x"04"; when x"F1D" => DATA <= x"BD"; when x"F1E" => DATA <= x"86"; when x"F1F" => DATA <= x"04"; when x"F20" => DATA <= x"8D"; when x"F21" => DATA <= x"B9"; when x"F22" => DATA <= x"04"; when x"F23" => DATA <= x"BD"; when x"F24" => DATA <= x"88"; when x"F25" => DATA <= x"04"; when x"F26" => DATA <= x"85"; when x"F27" => DATA <= x"FD"; when x"F28" => DATA <= x"8D"; when x"F29" => DATA <= x"FF"; when x"F2A" => DATA <= x"BF"; when x"F2B" => DATA <= x"20"; when x"F2C" => DATA <= x"69"; when x"F2D" => DATA <= x"EC"; when x"F2E" => DATA <= x"20"; when x"F2F" => DATA <= x"87"; when x"F30" => DATA <= x"EE"; when x"F31" => DATA <= x"20"; when x"F32" => DATA <= x"37"; when x"F33" => DATA <= x"EF"; when x"F34" => DATA <= x"4C"; when x"F35" => DATA <= x"3A"; when x"F36" => DATA <= x"EF"; when x"F37" => DATA <= x"6C"; when x"F38" => DATA <= x"B8"; when x"F39" => DATA <= x"04"; when x"F3A" => DATA <= x"20"; when x"F3B" => DATA <= x"69"; when x"F3C" => DATA <= x"EE"; when x"F3D" => DATA <= x"20"; when x"F3E" => DATA <= x"4D"; when x"F3F" => DATA <= x"EC"; when x"F40" => DATA <= x"68"; when x"F41" => DATA <= x"85"; when x"F42" => DATA <= x"FD"; when x"F43" => DATA <= x"8D"; when x"F44" => DATA <= x"FF"; when x"F45" => DATA <= x"BF"; when x"F46" => DATA <= x"20"; when x"F47" => DATA <= x"69"; when x"F48" => DATA <= x"EC"; when x"F49" => DATA <= x"AD"; when x"F4A" => DATA <= x"C1"; when x"F4B" => DATA <= x"04"; when x"F4C" => DATA <= x"85"; when x"F4D" => DATA <= x"60"; when x"F4E" => DATA <= x"68"; when x"F4F" => DATA <= x"C9"; when x"F50" => DATA <= x"15"; when x"F51" => DATA <= x"D0"; when x"F52" => DATA <= x"11"; when x"F53" => DATA <= x"AD"; when x"F54" => DATA <= x"93"; when x"F55" => DATA <= x"04"; when x"F56" => DATA <= x"C9"; when x"F57" => DATA <= x"CE"; when x"F58" => DATA <= x"D0"; when x"F59" => DATA <= x"0A"; when x"F5A" => DATA <= x"A9"; when x"F5B" => DATA <= x"CE"; when x"F5C" => DATA <= x"8D"; when x"F5D" => DATA <= x"08"; when x"F5E" => DATA <= x"02"; when x"F5F" => DATA <= x"A9"; when x"F60" => DATA <= x"AC"; when x"F61" => DATA <= x"8D"; when x"F62" => DATA <= x"09"; when x"F63" => DATA <= x"02"; when x"F64" => DATA <= x"4C"; when x"F65" => DATA <= x"87"; when x"F66" => DATA <= x"EE"; when x"F67" => DATA <= x"68"; when x"F68" => DATA <= x"AE"; when x"F69" => DATA <= x"04"; when x"F6A" => DATA <= x"04"; when x"F6B" => DATA <= x"A5"; when x"F6C" => DATA <= x"FD"; when x"F6D" => DATA <= x"48"; when x"F6E" => DATA <= x"BD"; when x"F6F" => DATA <= x"88"; when x"F70" => DATA <= x"04"; when x"F71" => DATA <= x"85"; when x"F72" => DATA <= x"FD"; when x"F73" => DATA <= x"8D"; when x"F74" => DATA <= x"FF"; when x"F75" => DATA <= x"BF"; when x"F76" => DATA <= x"BD"; when x"F77" => DATA <= x"86"; when x"F78" => DATA <= x"04"; when x"F79" => DATA <= x"8D"; when x"F7A" => DATA <= x"B9"; when x"F7B" => DATA <= x"04"; when x"F7C" => DATA <= x"BD"; when x"F7D" => DATA <= x"87"; when x"F7E" => DATA <= x"04"; when x"F7F" => DATA <= x"8D"; when x"F80" => DATA <= x"B8"; when x"F81" => DATA <= x"04"; when x"F82" => DATA <= x"20"; when x"F83" => DATA <= x"87"; when x"F84" => DATA <= x"EE"; when x"F85" => DATA <= x"20"; when x"F86" => DATA <= x"8B"; when x"F87" => DATA <= x"EF"; when x"F88" => DATA <= x"4C"; when x"F89" => DATA <= x"8E"; when x"F8A" => DATA <= x"EF"; when x"F8B" => DATA <= x"6C"; when x"F8C" => DATA <= x"B8"; when x"F8D" => DATA <= x"04"; when x"F8E" => DATA <= x"20"; when x"F8F" => DATA <= x"69"; when x"F90" => DATA <= x"EE"; when x"F91" => DATA <= x"68"; when x"F92" => DATA <= x"85"; when x"F93" => DATA <= x"FD"; when x"F94" => DATA <= x"8D"; when x"F95" => DATA <= x"FF"; when x"F96" => DATA <= x"BF"; when x"F97" => DATA <= x"AD"; when x"F98" => DATA <= x"C1"; when x"F99" => DATA <= x"04"; when x"F9A" => DATA <= x"85"; when x"F9B" => DATA <= x"60"; when x"F9C" => DATA <= x"4C"; when x"F9D" => DATA <= x"87"; when x"F9E" => DATA <= x"EE"; when x"F9F" => DATA <= x"20"; when x"FA0" => DATA <= x"69"; when x"FA1" => DATA <= x"EE"; when x"FA2" => DATA <= x"20"; when x"FA3" => DATA <= x"4D"; when x"FA4" => DATA <= x"EC"; when x"FA5" => DATA <= x"68"; when x"FA6" => DATA <= x"85"; when x"FA7" => DATA <= x"FD"; when x"FA8" => DATA <= x"8D"; when x"FA9" => DATA <= x"FF"; when x"FAA" => DATA <= x"BF"; when x"FAB" => DATA <= x"20"; when x"FAC" => DATA <= x"69"; when x"FAD" => DATA <= x"EC"; when x"FAE" => DATA <= x"A9"; when x"FAF" => DATA <= x"EB"; when x"FB0" => DATA <= x"8D"; when x"FB1" => DATA <= x"03"; when x"FB2" => DATA <= x"02"; when x"FB3" => DATA <= x"A9"; when x"FB4" => DATA <= x"9C"; when x"FB5" => DATA <= x"8D"; when x"FB6" => DATA <= x"02"; when x"FB7" => DATA <= x"02"; when x"FB8" => DATA <= x"4C"; when x"FB9" => DATA <= x"87"; when x"FBA" => DATA <= x"EE"; when x"FBB" => DATA <= x"FF"; when x"FBC" => DATA <= x"FF"; when x"FBD" => DATA <= x"FF"; when x"FBE" => DATA <= x"FF"; when x"FBF" => DATA <= x"FF"; when x"FC0" => DATA <= x"FF"; when x"FC1" => DATA <= x"FF"; when x"FC2" => DATA <= x"FF"; when x"FC3" => DATA <= x"FF"; when x"FC4" => DATA <= x"FF"; when x"FC5" => DATA <= x"FF"; when x"FC6" => DATA <= x"FF"; when x"FC7" => DATA <= x"FF"; when x"FC8" => DATA <= x"FF"; when x"FC9" => DATA <= x"FF"; when x"FCA" => DATA <= x"FF"; when x"FCB" => DATA <= x"FF"; when x"FCC" => DATA <= x"4C"; when x"FCD" => DATA <= x"7E"; when x"FCE" => DATA <= x"E0"; when x"FCF" => DATA <= x"FF"; when x"FD0" => DATA <= x"41"; when x"FD1" => DATA <= x"54"; when x"FD2" => DATA <= x"4F"; when x"FD3" => DATA <= x"4D"; when x"FD4" => DATA <= x"4D"; when x"FD5" => DATA <= x"43"; when x"FD6" => DATA <= x"32"; when x"FD7" => DATA <= x"20"; when x"FD8" => DATA <= x"56"; when x"FD9" => DATA <= x"32"; when x"FDA" => DATA <= x"2E"; when x"FDB" => DATA <= x"39"; when x"FDC" => DATA <= x"37"; when x"FDD" => DATA <= x"45"; when x"FDE" => DATA <= x"0D"; when x"FDF" => DATA <= x"0A"; when x"FE0" => DATA <= x"20"; when x"FE1" => DATA <= x"28"; when x"FE2" => DATA <= x"43"; when x"FE3" => DATA <= x"29"; when x"FE4" => DATA <= x"20"; when x"FE5" => DATA <= x"32"; when x"FE6" => DATA <= x"30"; when x"FE7" => DATA <= x"30"; when x"FE8" => DATA <= x"38"; when x"FE9" => DATA <= x"2D"; when x"FEA" => DATA <= x"32"; when x"FEB" => DATA <= x"30"; when x"FEC" => DATA <= x"31"; when x"FED" => DATA <= x"33"; when x"FEE" => DATA <= x"20"; when x"FEF" => DATA <= x"20"; when x"FF0" => DATA <= x"43"; when x"FF1" => DATA <= x"48"; when x"FF2" => DATA <= x"41"; when x"FF3" => DATA <= x"52"; when x"FF4" => DATA <= x"4C"; when x"FF5" => DATA <= x"49"; when x"FF6" => DATA <= x"45"; when x"FF7" => DATA <= x"20"; when x"FF8" => DATA <= x"52"; when x"FF9" => DATA <= x"4F"; when x"FFA" => DATA <= x"42"; when x"FFB" => DATA <= x"53"; when x"FFC" => DATA <= x"4F"; when x"FFD" => DATA <= x"4E"; when x"FFE" => DATA <= x"2E"; when x"FFF" => DATA <= x"20"; when others => DATA <= (others => '0'); end case; end process; end RTL;
apache-2.0
db32d8c4c88b8dc438d937b750a8b8c0
0.41776
2.51125
false
false
false
false
hoglet67/AtomFpga
src/common/AVR8/uC/ResetGenerator.vhd
4
3,181
--********************************************************************************************** -- Reset generator for the AVR Core -- Version 0.7 -- Modified 23.07.2003 -- Designed by Ruslan Lepetenok --********************************************************************************************** library IEEE; use IEEE.std_logic_1164.all; use WORK.SynthCtrlPack.all; entity ResetGenerator is port( -- Clock inputs cp2 : in std_logic; cp64m : in std_logic; -- Reset inputs nrst : in std_logic; npwrrst : in std_logic; wdovf : in std_logic; jtagrst : in std_logic; -- Reset outputs nrst_cp2 : out std_logic; nrst_cp64m : out std_logic; nrst_clksw : out std_logic ); end ResetGenerator; architecture RTL of ResetGenerator is signal cp2RstA : std_logic; signal cp2RstB : std_logic; signal cp2RstC : std_logic; signal cp64mRstA : std_logic; signal cp64mRstB : std_logic; signal nrst_ResyncA : std_logic; signal nrst_ResyncB : std_logic; signal ClrRstDFF : std_logic; signal ClrRstDFF_Tmp : std_logic; signal RstDelayA : std_logic; signal RstDelayB : std_logic; begin nrst_Resync_DFFs:process(cp2) begin if cp2='1' and cp2'event then -- Clock nrst_ResyncA <= nrst; nrst_ResyncB <= nrst_ResyncA; end if; end process; ResetDFF:process(cp2) begin if cp2='1' and cp2'event then -- Clock if wdovf='1' or jtagrst='1' or nrst_ResyncB='0' or npwrrst='0' then ClrRstDFF_Tmp <= '0'; -- Reset else ClrRstDFF_Tmp <= '1'; -- Normal state end if; end if; end process; ClrRstDFF <= ClrRstDFF_Tmp; -- !!!TBD!!! GLOBAL primitive may be used !!! -- High speed clock domain reset(if exists) SecondClock:if CSecondClockUsed generate Reset_cp64m_DFFs:process(ClrRstDFF,cp64m) begin if ClrRstDFF='0' then -- Reset cp64mRstA <= '0'; cp64mRstB <= '0'; elsif cp64m='1' and cp64m'event then -- Clock cp64mRstA <= '1'; cp64mRstB <= cp64mRstA; end if; end process; -- Reset signal for 64 MHz clock domain nrst_cp64m <= cp64mRstB; end generate; -- High speed clock domain doesn't exist NoSecondClock:if not CSecondClockUsed generate cp64mRstB <= '1'; nrst_cp64m <= '0'; end generate; -- Low speed clock domain reset Reset_cp2_DFFs:process(ClrRstDFF,cp2) begin if ClrRstDFF='0' then -- Reset cp2RstA <= '0'; cp2RstB <= '0'; cp2RstC <= '0'; elsif cp2='1' and cp2'event then -- Clock -- cp2RstA <= cp64mRstB; cp2RstA <= RstDelayB; cp2RstB <= cp2RstA; cp2RstC <= cp2RstB; end if; end process; -- Reset delay line Reset_Delay_DFFs:process(ClrRstDFF,cp2) begin if ClrRstDFF='0' then -- Reset RstDelayA <= '0'; RstDelayB <= '0'; elsif cp2='1' and cp2'event then -- Clock RstDelayA <= cp64mRstB; RstDelayB <= RstDelayA; end if; end process; -- Reset signal for cp2 clock domain nrst_cp2 <= cp2RstC; -- Separate reset for clock enable module nrst_clksw <= RstDelayB; end RTL;
apache-2.0
b76661ac6841bb0713378da89e4d0ab1
0.577806
3.103415
false
false
false
false
msiddalingaiah/TTA
VHDL/ControlUnitTest.vhd
1
3,135
-------------------------------------------------------------------------------- -- Copyright 2014 Madhu Siddalingaiah -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -- Entity: ControlUnitTest -- Date: 2014-11-26 -- Author: Madhu -- -- Description: -------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; -- Avoid using ieee.std_logic_arith.all use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; entity ControlUnitTest is end ControlUnitTest; architecture arch of ControlUnitTest is component ControlUnit generic ( DATA_WIDTH : integer; PM_DEPTH : natural ); port ( reset : in std_logic; clock : in std_logic; load_enable : in std_logic; run_enable : in std_logic; pm_data_in : in std_logic_vector ( 16 - 1 downto 0 ); halt_flag : out std_logic ); end component; signal reset : std_logic := '0'; signal clock : std_logic := '0'; signal load_enable, run_enable, halt_flag : std_logic := '0'; signal pm_data_in : std_logic_vector ( 16 - 1 downto 0 ); signal runSimulation : std_logic := '1'; begin c : ControlUnit generic map( DATA_WIDTH => 16, PM_DEPTH => 16 ) port map( reset => reset, clock => clock, load_enable => load_enable, run_enable => run_enable, pm_data_in => pm_data_in, halt_flag => halt_flag ); process begin wait for 5 ns; clock <= not clock; if runSimulation = '0' then wait; end if; end process; stimulus : process procedure doReset is begin pm_data_in <= (others => '0'); load_enable <= '0'; run_enable <= '0'; wait for 2 ns; reset <= '1'; wait for 6 ns; reset <= '0'; end doReset; procedure write_inst(dIn : std_logic_vector(16-1 downto 0)) is begin wait until rising_edge(clock); pm_data_in <= dIn; end write_inst; begin doReset; load_enable <= '1'; write_inst(x"f001"); write_inst(x"f802"); write_inst(x"f003"); write_inst(x"1a00"); write_inst(x"f004"); write_inst(x"0001"); write_inst(x"0000"); write_inst(x"0000"); load_enable <= '0'; run_enable <= '1'; wait for 200 ns; -- wait until halt_flag = '1'; runSimulation <= '0'; wait; end process stimulus; end arch;
apache-2.0
210ae89119ce0061c3642ace9f6d7266
0.539713
3.875155
false
false
false
false
hoglet67/AtomFpga
src/common/AVR8/spi_mod/spi_mod.vhd
4
20,772
--********************************************************************************************** -- SPI Peripheral for the AVR Core -- Version 1.2 -- Modified 10.01.2007 -- Designed by Ruslan Lepetenok -- Internal resynchronizers for scki and ss_b inputs were added --********************************************************************************************** library IEEE; use IEEE.std_logic_1164.all; use WORK.std_library.all; use WORK.avr_adr_pack.all; use WORK.rsnc_comp_pack.all; entity spi_mod is port( -- AVR Control ireset : in std_logic; cp2 : in std_logic; adr : in std_logic_vector(15 downto 0); dbus_in : in std_logic_vector(7 downto 0); dbus_out : out std_logic_vector(7 downto 0); iore : in std_logic; iowe : in std_logic; out_en : out std_logic; -- SPI i/f misoi : in std_logic; mosii : in std_logic; scki : in std_logic; -- Resynch ss_b : in std_logic; -- Resynch misoo : out std_logic; mosio : out std_logic; scko : out std_logic; spe : out std_logic; spimaster : out std_logic; -- IRQ spiirq : out std_logic; spiack : in std_logic; -- Slave Programming Mode por : in std_logic; spiextload : in std_logic; spidwrite : out std_logic; spiload : out std_logic ); end spi_mod; architecture RTL of spi_mod is -- Resynch signal scki_resync : std_logic; signal ss_b_resync : std_logic; -- Registers signal SPCR : std_logic_vector(7 downto 0); alias SPIE : std_logic is SPCR(7); alias SPEB : std_logic is SPCR(6); -- SPE in Atmel's doc alias DORD : std_logic is SPCR(5); alias MSTR : std_logic is SPCR(4); alias CPOL : std_logic is SPCR(3); alias CPHA : std_logic is SPCR(2); alias SPR : std_logic_vector(1 downto 0) is SPCR(1 downto 0); signal SPSR : std_logic_vector(7 downto 0); alias SPIF : std_logic is SPSR(7); alias WCOL : std_logic is SPSR(6); alias SPI2X : std_logic is SPSR(0); signal SPIE_Next : std_logic; signal SPEB_Next : std_logic; signal DORD_Next : std_logic; signal CPOL_Next : std_logic; signal CPHA_Next : std_logic; signal SPR_Next : std_logic_vector(SPR'range); signal SPI2X_Next : std_logic; signal SPDR_Rc : std_logic_vector(7 downto 0); signal SPDR_Rc_Next : std_logic_vector(7 downto 0); signal SPDR_Sh_Current : std_logic_vector(7 downto 0); signal SPDR_Sh_Next : std_logic_vector(7 downto 0); signal Div_Next : std_logic_vector(5 downto 0); signal Div_Current : std_logic_vector(5 downto 0); signal Div_Toggle : std_logic; signal DivCntMsb_Current : std_logic; signal DivCntMsb_Next : std_logic; type MstSMSt_Type is (MstSt_Idle,MstSt_B0,MstSt_B1,MstSt_B2,MstSt_B3,MstSt_B4,MstSt_B5,MstSt_B6,MstSt_B7); signal MstSMSt_Current : MstSMSt_Type; signal MstSMSt_Next : MstSMSt_Type; signal TrStart : std_logic; signal scko_Next : std_logic; signal scko_Current : std_logic; --!!! signal UpdRcDataRg_Current : std_logic; signal UpdRcDataRg_Next : std_logic; signal TmpIn_Current : std_logic; signal TmpIn_Next : std_logic; -- Slave signal sck_EdgeDetDFF : std_logic; signal SlvSampleSt : std_logic; signal SlvSMChangeSt : std_logic; type SlvSMSt_Type is (SlvSt_Idle,SlvSt_B0I,SlvSt_B0,SlvSt_B1,SlvSt_B2,SlvSt_B3,SlvSt_B4,SlvSt_B5,SlvSt_B6,SlvSt_B6W); signal SlvSMSt_Current : SlvSMSt_Type; signal SlvSMSt_Next : SlvSMSt_Type; -- SIF clear SM signal SPIFClrSt_Current : std_logic; signal SPIFClrSt_Next : std_logic; -- WCOL clear SM signal WCOLClrSt_Current : std_logic; signal WCOLClrSt_Next : std_logic; signal MSTR_Next : std_logic; signal SPIF_Next : std_logic; signal WCOL_Next : std_logic; signal MstDSamp_Next : std_logic; signal MstDSamp_Current : std_logic; function Fn_RevBitVector(InVector : std_logic_vector) return std_logic_vector is variable TmpVect : std_logic_vector(InVector'range); begin for i in TmpVect'range loop TmpVect(i) := InVector(InVector'high-i); end loop; return TmpVect; end Fn_RevBitVector; begin -- ******************** Resynchronizers ************************************ scki_resync_inst:component rsnc_bit generic map( add_stgs_num => 0, inv_f_stgs => 0 ) port map( clk => cp2, di => scki, do => scki_resync ); ss_b_resync_inst:component rsnc_bit generic map( add_stgs_num => 0, inv_f_stgs => 0 ) port map( clk => cp2, di => ss_b, do => ss_b_resync ); -- ******************** Resynchronizers ************************************ SeqPrc:process(ireset,cp2) begin if (ireset='0') then -- Reset SPCR <= (others => '0'); SPIF <= '0'; WCOL <= '0'; SPI2X <= '0'; Div_Current <= (others => '0'); DivCntMsb_Current <= '0'; MstSMSt_Current <= MstSt_Idle; SlvSMSt_Current <= SlvSt_Idle; SPDR_Sh_Current <= (others => '1'); SPDR_Rc <= (others => '0'); sck_EdgeDetDFF <= '0'; SPIFClrSt_Current <= '0'; WCOLClrSt_Current <= '0'; scko <= '0'; scko_Current <= '0'; misoo <= '0'; mosio <= '0'; TmpIn_Current <= '0'; UpdRcDataRg_Current <= '0'; MstDSamp_Current <= '0'; elsif (cp2='1' and cp2'event) then -- Clock SPIE <= SPIE_Next; SPEB <= SPEB_Next; DORD <= DORD_Next; CPOL <= CPOL_Next; CPHA <= CPHA_Next; SPR <= SPR_Next; MSTR <= MSTR_Next; SPIF <= SPIF_Next; SPI2X <= SPI2X_Next; WCOL <= WCOL_Next; Div_Current <= Div_Next; DivCntMsb_Current <= DivCntMsb_Next; MstSMSt_Current <= MstSMSt_Next; SlvSMSt_Current <= SlvSMSt_Next; SPDR_Sh_Current <= SPDR_Sh_Next; SPDR_Rc <= SPDR_Rc_Next; sck_EdgeDetDFF <= scki_resync; SPIFClrSt_Current <= SPIFClrSt_Next; WCOLClrSt_Current <= WCOLClrSt_Next; scko_Current <= scko_Next; scko <= scko_Next; misoo <= SPDR_Sh_Next(SPDR_Sh_Next'high); mosio <= SPDR_Sh_Next(SPDR_Sh_Next'high); TmpIn_Current <= TmpIn_Next; UpdRcDataRg_Current <= UpdRcDataRg_Next; MstDSamp_Current <= MstDSamp_Next; end if; end process; IORegWriteComb:process(adr,iowe,SPCR,SPSR,dbus_in) begin SPIE_Next <= SPIE; SPEB_Next <= SPEB; DORD_Next <= DORD; CPOL_Next <= CPOL; CPHA_Next <= CPHA; SPR_Next <= SPR; SPI2X_Next <= SPI2X; if(fn_to_integer(adr)=SPCR_Address and iowe='1') then SPIE_Next <= dbus_in(7); SPEB_Next <= dbus_in(6); DORD_Next <= dbus_in(5); CPOL_Next <= dbus_in(3); CPHA_Next <= dbus_in(2); SPR_Next <= dbus_in(1 downto 0); end if; if(fn_to_integer(adr)=SPSR_Address and iowe='1') then SPI2X_Next <= dbus_in(0); end if; end process; SPSR(5 downto 1) <= (others => '0'); -- Divider -- SPI2X | SPR1 | SPR0 | SCK Frequency -- 0 | 0 | 0 | fosc /4 (2) -- 0 | 0 | 1 | fosc /16 (8) -- 0 | 1 | 0 | fosc /64 (32) -- 0 | 1 | 1 | fosc /128 (64) -- ------+------+------+------------- -- 1 | 0 | 0 | fosc /2 (1) -- 1 | 0 | 1 | fosc /8 (4) -- 1 | 1 | 0 | fosc /32 (16) -- 1 | 1 | 1 | fosc /64 (32) DividerToggleComb:process(MstSMSt_Current,Div_Current,SPCR,SPSR) begin Div_Toggle <= '0'; if(MstSMSt_Current /= MstSt_Idle) then if(SPI2X='1') then -- Extended mode case SPR is when "00" => if (Div_Current="000001") then Div_Toggle <= '1'; end if; -- fosc /2 when "01" => if (Div_Current="000011") then Div_Toggle <= '1'; end if; -- fosc /8 when "10" => if (Div_Current="001111") then Div_Toggle <= '1'; end if; -- fosc /32 when "11" => if (Div_Current="011111") then Div_Toggle <= '1'; end if; -- fosc /64 when others => Div_Toggle <= '0'; end case; else -- Normal mode case SPR is when "00" => if (Div_Current="000001") then Div_Toggle <= '1'; end if; -- fosc /4 when "01" => if (Div_Current="000111") then Div_Toggle <= '1'; end if; -- fosc /16 when "10" => if (Div_Current="011111") then Div_Toggle <= '1'; end if; -- fosc /64 when "11" => if (Div_Current="111111") then Div_Toggle <= '1'; end if; -- fosc /128 when others => Div_Toggle <= '0'; end case; end if; end if; end process; DividerNextComb:process(MstSMSt_Current,Div_Current,DivCntMsb_Current,Div_Toggle) begin Div_Next <= Div_Current; DivCntMsb_Next <= DivCntMsb_Current; if(MstSMSt_Current /= MstSt_Idle) then if(Div_Toggle='1') then Div_Next <= (others => '0'); DivCntMsb_Next <= not DivCntMsb_Current; else Div_Next <= Div_Current + 1; end if; end if; end process; TrStart <= '1' when (fn_to_integer(adr)=SPDR_Address and iowe='1' and SPEB='1') else '0'; -- Transmitter Master Mode Shift Control SM MstSmNextComb:process(MstSMSt_Current,DivCntMsb_Current,Div_Toggle,TrStart,SPCR) begin MstSMSt_Next <= MstSMSt_Current; case MstSMSt_Current is when MstSt_Idle => if(TrStart='1' and MSTR='1') then MstSMSt_Next <= MstSt_B0; end if; when MstSt_B0 => if(DivCntMsb_Current='1' and Div_Toggle='1') then MstSMSt_Next <= MstSt_B1; end if; when MstSt_B1 => if(DivCntMsb_Current='1' and Div_Toggle='1') then MstSMSt_Next <= MstSt_B2; end if; when MstSt_B2 => if(DivCntMsb_Current='1' and Div_Toggle='1') then MstSMSt_Next <= MstSt_B3; end if; when MstSt_B3 => if(DivCntMsb_Current='1' and Div_Toggle='1') then MstSMSt_Next <= MstSt_B4; end if; when MstSt_B4 => if(DivCntMsb_Current='1' and Div_Toggle='1') then MstSMSt_Next <= MstSt_B5; end if; when MstSt_B5 => if(DivCntMsb_Current='1' and Div_Toggle='1') then MstSMSt_Next <= MstSt_B6; end if; when MstSt_B6 => if(DivCntMsb_Current='1' and Div_Toggle='1') then MstSMSt_Next <= MstSt_B7; end if; when MstSt_B7 => if(DivCntMsb_Current='1' and Div_Toggle='1') then MstSMSt_Next <= MstSt_Idle; end if; when others => MstSMSt_Next <= MstSt_Idle; end case; end process; SPIFClrCombProc:process(SPIFClrSt_Current,SPCR,SPSR,adr,iore,iowe) begin SPIFClrSt_Next <= SPIFClrSt_Current; case SPIFClrSt_Current is when '0' => if(fn_to_integer(adr)=SPSR_Address and iore='1' and SPIF='1' and SPEB='1') then SPIFClrSt_Next <= '1'; end if; when '1' => if(fn_to_integer(adr)=SPDR_Address and (iore='1' or iowe='1')) then SPIFClrSt_Next <= '0'; end if; when others => SPIFClrSt_Next <= SPIFClrSt_Current; end case; end process; --SPIFClrCombProc WCOLClrCombProc:process(WCOLClrSt_Current,SPSR,adr,iore,iowe) begin WCOLClrSt_Next <= WCOLClrSt_Current; case WCOLClrSt_Current is when '0' => if(fn_to_integer(adr)=SPSR_Address and iore='1' and WCOL='1') then WCOLClrSt_Next <= '1'; end if; when '1' => if(fn_to_integer(adr)=SPDR_Address and (iore='1' or iowe='1')) then WCOLClrSt_Next <= '0'; end if; when others => WCOLClrSt_Next <= WCOLClrSt_Current; end case; end process; --WCOLClrCombProc MstDataSamplingComb:process(SPCR,scko_Current,scko_Next,MstDSamp_Current,MstSMSt_Current) begin MstDSamp_Next <= '0'; case MstDSamp_Current is when '0' => if(MstSMSt_Current/=MstSt_Idle) then if(CPHA=CPOL) then if(scko_Next='1' and scko_Current='0') then -- Rising edge MstDSamp_Next <= '1'; end if; else -- CPHA/=CPOL if(scko_Next='0' and scko_Current='1') then -- Falling edge MstDSamp_Next <= '1'; end if; end if; end if; when '1' => MstDSamp_Next <= '0'; when others => MstDSamp_Next <= '0'; end case; end process; -- MstDataSamplingComb -- DRLatchComb:process(UpdRcDataRg_Current,MstSMSt_Current,MstSMSt_Next,SlvSMSt_Current,SlvSMSt_Next,SPCR) begin UpdRcDataRg_Next <= '0'; case UpdRcDataRg_Current is when '0' => if((MSTR='1' and MstSMSt_Current/=MstSt_Idle and MstSMSt_Next=MstSt_Idle)or (MSTR='0' and SlvSMSt_Current/=SlvSt_Idle and SlvSMSt_Next=SlvSt_Idle)) then UpdRcDataRg_Next <= '1'; end if; when '1' => UpdRcDataRg_Next <= '0'; when others => UpdRcDataRg_Next <= '0'; end case; end process; TmpInComb:process(TmpIn_Current,mosii,misoi,MstDSamp_Current,SlvSampleSt,SPCR,ss_b_resync) begin TmpIn_Next <= TmpIn_Current; if(MSTR='1' and MstDSamp_Current='1') then -- Master mode TmpIn_Next <= misoi; elsif(MSTR='0' and SlvSampleSt='1' and ss_b_resync='0') then -- Slave mode ??? TmpIn_Next <= mosii; end if; end process; ShiftRgComb:process(MstSMSt_Current,SlvSMSt_Current,SPDR_Sh_Current,SPCR,DivCntMsb_Current,Div_Toggle,TrStart,dbus_in,ss_b_resync,TmpIn_Current,SlvSMChangeSt,SlvSampleSt,UpdRcDataRg_Current) begin SPDR_Sh_Next <= SPDR_Sh_Current; if(TrStart='1' and (MstSMSt_Current=MstSt_Idle and SlvSMSt_Current = SlvSt_Idle and not(MSTR='0' and SlvSampleSt='1' and ss_b_resync='0') )) then -- Load if (DORD='1') then -- the LSB of the data word is transmitted first SPDR_Sh_Next <= Fn_RevBitVector(dbus_in); else -- the MSB of the data word is transmitted first SPDR_Sh_Next <= dbus_in; end if; elsif(MSTR='1' and UpdRcDataRg_Current='1') then -- ??? SPDR_Sh_Next(SPDR_Sh_Next'high) <= '1'; elsif((MSTR='1' and MstSMSt_Current/=MstSt_Idle and DivCntMsb_Current='1' and Div_Toggle='1') or (MSTR='0' and SlvSMSt_Current/=SlvSt_Idle and SlvSMChangeSt='1' and ss_b_resync='0')) then -- Shift SPDR_Sh_Next <= SPDR_Sh_Current(SPDR_Sh_Current'high-1 downto SPDR_Sh_Current'low)&TmpIn_Current; end if; end process; --ShiftRgComb sckoGenComb:process(scko_Current,SPCR,adr,iowe,dbus_in,DivCntMsb_Next,DivCntMsb_Current,TrStart,MstSMSt_Current,MstSMSt_Next) begin scko_Next <= scko_Current; if(fn_to_integer(adr)=SPCR_Address and iowe='1') then -- Write to SPCR scko_Next <= dbus_in(3); -- CPOL elsif(TrStart='1' and CPHA='1' and MstSMSt_Current=MstSt_Idle) then scko_Next <= not CPOL; elsif(MstSMSt_Current/=MstSt_Idle and MstSMSt_Next=MstSt_Idle) then -- "Parking" scko_Next <= CPOL; elsif(MstSMSt_Current/=MstSt_Idle and DivCntMsb_Current/=DivCntMsb_Next) then scko_Next <= not scko_Current; end if; end process; -- Receiver data register SPDRRcComb:process(SPDR_Rc,SPCR,SPDR_Sh_Current,UpdRcDataRg_Current,TmpIn_Current) begin SPDR_Rc_Next <= SPDR_Rc; if(UpdRcDataRg_Current='1') then if(MSTR='0' and CPHA='1') then if (DORD='1') then -- the LSB of the data word is transmitted first SPDR_Rc_Next <= Fn_RevBitVector(SPDR_Sh_Current(SPDR_Sh_Current'high-1 downto 0)&TmpIn_Current); else -- the MSB of the data word is transmitted first SPDR_Rc_Next <= SPDR_Sh_Current(SPDR_Sh_Current'high-1 downto 0)&TmpIn_Current; end if; else if (DORD='1') then -- the LSB of the data word is transmitted first SPDR_Rc_Next <= Fn_RevBitVector(SPDR_Sh_Current); else -- the MSB of the data word is transmitted first SPDR_Rc_Next <= SPDR_Sh_Current; end if; end if; end if; end process; --**************************************************************************************** -- Slave --**************************************************************************************** SlvSampleSt <= '1' when ((sck_EdgeDetDFF='0' and scki_resync='1' and CPOL=CPHA)or -- Rising edge (sck_EdgeDetDFF='1' and scki_resync='0' and CPOL/=CPHA))else '0'; -- Falling edge SlvSMChangeSt <= '1' when ((sck_EdgeDetDFF='1' and scki_resync='0' and CPOL=CPHA)or -- Falling edge (sck_EdgeDetDFF='0' and scki_resync='1' and CPOL/=CPHA))else '0'; -- Rising edge -- Slave Master Mode Shift Control SM SlvSMNextComb:process(SlvSMSt_Current,SPCR,SlvSampleSt,SlvSMChangeSt,ss_b_resync) begin SlvSMSt_Next <= SlvSMSt_Current; if(ss_b_resync='0') then case SlvSMSt_Current is when SlvSt_Idle => if(MSTR='0') then if(CPHA='1') then if(SlvSMChangeSt='1') then SlvSMSt_Next <= SlvSt_B0; end if; else -- CPHA='0' if(SlvSampleSt='1') then SlvSMSt_Next <= SlvSt_B0I; end if; end if; end if; when SlvSt_B0I => if(SlvSMChangeSt='1') then SlvSMSt_Next <= SlvSt_B0; end if; when SlvSt_B0 => if(SlvSMChangeSt='1') then SlvSMSt_Next <= SlvSt_B1; end if; when SlvSt_B1 => if(SlvSMChangeSt='1') then SlvSMSt_Next <= SlvSt_B2; end if; when SlvSt_B2 => if(SlvSMChangeSt='1') then SlvSMSt_Next <= SlvSt_B3; end if; when SlvSt_B3 => if(SlvSMChangeSt='1') then SlvSMSt_Next <= SlvSt_B4; end if; when SlvSt_B4 => if(SlvSMChangeSt='1') then SlvSMSt_Next <= SlvSt_B5; end if; when SlvSt_B5 => if(SlvSMChangeSt='1') then SlvSMSt_Next <= SlvSt_B6; end if; when SlvSt_B6 => if(SlvSMChangeSt='1') then if(CPHA='0') then SlvSMSt_Next <= SlvSt_Idle; else -- CPHA='1' SlvSMSt_Next <= SlvSt_B6W; end if; end if; when SlvSt_B6W => if(SlvSampleSt='1')then SlvSMSt_Next <= SlvSt_Idle; end if; when others => SlvSMSt_Next <= SlvSt_Idle; end case; end if; end process; MSTRGenComb:process(adr,iowe,dbus_in,ss_b_resync,SPCR) begin MSTR_Next <= MSTR; case MSTR is when '0' => if(fn_to_integer(adr)=SPCR_Address and iowe='1' and dbus_in(4)='1') then -- TBD (ss_b_resync='0') MSTR_Next <= '1'; end if; when '1' => if((fn_to_integer(adr)=SPCR_Address and iowe='1' and dbus_in(4)='0') or (ss_b_resync='0')) then MSTR_Next <= '0'; end if; when others => MSTR_Next <= MSTR; end case; end process; WCOLGenComb:process(WCOLClrSt_Current,SlvSMSt_Current,MstSMSt_Current,adr,iowe,iore,SPCR,SPSR,SlvSampleSt,ss_b_resync) begin WCOL_Next <= WCOL; case WCOL is when '0' => if(fn_to_integer(adr)=SPDR_Address and iowe='1' and ((MSTR='0' and (SlvSMSt_Current/=SlvSt_Idle or (SlvSampleSt='1' and ss_b_resync='0'))) or (MSTR='1' and MstSMSt_Current/=MstSt_Idle))) then WCOL_Next <= '1'; end if; when '1' => if(((fn_to_integer(adr)=SPDR_Address and (iowe='1' or iore='1')) and WCOLClrSt_Current='1') and not (fn_to_integer(adr)=SPDR_Address and iowe='1' and ((MSTR='0' and (SlvSMSt_Current/=SlvSt_Idle or (SlvSampleSt='1' and ss_b_resync='0'))) or (MSTR='1' and MstSMSt_Current/=MstSt_Idle)))) then WCOL_Next <= '0'; end if; when others => WCOL_Next <= WCOL; end case; end process; SPIFGenComb:process(SPIFClrSt_Current,adr,iowe,iore,SPCR,SPSR,SlvSMSt_Current,SlvSMSt_Next,MstSMSt_Current,MstSMSt_Next,spiack) begin SPIF_Next <= SPIF; case SPIF is when '0' => if((MSTR='0' and SlvSMSt_Current/=SlvSt_Idle and SlvSMSt_Next=SlvSt_Idle) or (MSTR='1' and MstSMSt_Current/=MstSt_Idle and MstSMSt_Next=MstSt_Idle))then SPIF_Next <= '1'; end if; when '1' => if((fn_to_integer(adr)=SPDR_Address and (iowe='1' or iore='1') and SPIFClrSt_Current='1') or spiack='1') then SPIF_Next <= '0'; end if; when others => SPIF_Next <= SPIF; end case; end process; --************************************************************************************* spimaster <= MSTR; spe <= SPEB; -- IRQ spiirq <= SPIE and SPIF; OutMuxComb:process(adr,iore,SPDR_Rc,SPSR,SPCR) begin case(fn_to_integer(adr)) is when SPDR_Address => dbus_out <= SPDR_Rc; out_en <= iore; when SPSR_Address => dbus_out <= SPSR; out_en <= iore; when SPCR_Address => dbus_out <= SPCR; out_en <= iore; when others => dbus_out <= (others => '0'); out_en <= '0'; end case; end process; -- OutMuxComb -- spidwrite <= '0'; spiload <= '0'; end RTL;
apache-2.0
a38acc581633cc910c9cc1cb35f5238f
0.574042
2.926046
false
false
false
false
GSimas/EEL5105
PROJETO-EEL5105/Projeto/Mux16x1.vhd
1
954
library IEEE; use IEEE.Std_Logic_1164.all; --Multiplexador 16x1 32bits entity mux16x1_32 is port (IN0,IN1,IN2,IN3,IN4,IN5,IN6,IN7,IN8,IN9,IN10,IN11,IN12,IN13,IN14,IN15: in std_logic_vector(31 downto 0); REG: out std_logic_vector(31 downto 0); UP_DOWN: in std_logic_vector(3 downto 0) ); end mux16x1_32; --Definicao Arquitetura architecture circuito of mux16x1_32 is begin REG <= IN0 when UP_DOWN = "0000" else IN1 when UP_DOWN = "0001" else IN2 when UP_DOWN = "0010" else IN3 when UP_DOWN = "0011" else IN4 when UP_DOWN = "0100" else IN5 when UP_DOWN = "0101" else IN6 when UP_DOWN = "0110" else IN7 when UP_DOWN = "0111" else IN8 when UP_DOWN = "1000" else IN9 when UP_DOWN = "1001" else IN10 when UP_DOWN = "1010" else IN11 when UP_DOWN = "1011" else IN12 when UP_DOWN = "1100" else IN13 when UP_DOWN = "1101" else IN14 when UP_DOWN = "1110" else IN15; end circuito;
mit
fb38a760c37563ff4641c849b9c59868
0.65304
2.585366
false
false
false
false
tghaefli/ADD
EDK/IVK_Repos/IVK_IPLib/pcores/sg_xsvi_fanout_plbw_v1_01_a/hdl/vhdl/sg_xsvi_fanout_plbw.vhd
1
10,007
------------------------------------------------------------------- -- System Generator version 11.1.00 VHDL source file. -- -- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2007 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; entity plbaddrpref is generic ( C_BASEADDR : std_logic_vector(31 downto 0) := X"80000000"; C_HIGHADDR : std_logic_vector(31 downto 0) := X"8000FFFF"; C_SPLB_DWIDTH : integer range 32 to 128 := 32; C_SPLB_NATIVE_DWIDTH : integer range 32 to 32 := 32 ); port ( addrpref : out std_logic_vector(20-1 downto 0); sl_rddbus : out std_logic_vector(0 to C_SPLB_DWIDTH-1); plb_wrdbus : in std_logic_vector(0 to C_SPLB_DWIDTH-1); sgsl_rddbus : in std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH-1); sgplb_wrdbus : out std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH-1) ); end plbaddrpref; architecture behavior of plbaddrpref is signal sl_rddbus_i : std_logic_vector(0 to C_SPLB_DWIDTH-1); begin addrpref <= C_BASEADDR(32-1 downto 12); ------------------------------------------------------------------------------- -- Mux/Steer data/be's correctly for connect 32-bit slave to 128-bit plb ------------------------------------------------------------------------------- GEN_128_TO_32_SLAVE : if C_SPLB_NATIVE_DWIDTH = 32 and C_SPLB_DWIDTH = 128 generate begin ----------------------------------------------------------------------- -- Map lower rd data to each quarter of the plb slave read bus ----------------------------------------------------------------------- sl_rddbus_i(0 to 31) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1); sl_rddbus_i(32 to 63) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1); sl_rddbus_i(64 to 95) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1); sl_rddbus_i(96 to 127) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1); end generate GEN_128_TO_32_SLAVE; ------------------------------------------------------------------------------- -- Mux/Steer data/be's correctly for connect 32-bit slave to 64-bit plb ------------------------------------------------------------------------------- GEN_64_TO_32_SLAVE : if C_SPLB_NATIVE_DWIDTH = 32 and C_SPLB_DWIDTH = 64 generate begin --------------------------------------------------------------------------- -- Map lower rd data to upper and lower halves of plb slave read bus --------------------------------------------------------------------------- sl_rddbus_i(0 to 31) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1); sl_rddbus_i(32 to 63) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1); end generate GEN_64_TO_32_SLAVE; ------------------------------------------------------------------------------- -- IPIF DWidth = PLB DWidth -- If IPIF Slave Data width is equal to the PLB Bus Data Width -- Then BE and Read Data Bus map directly to eachother. ------------------------------------------------------------------------------- GEN_FOR_EQUAL_SLAVE : if C_SPLB_NATIVE_DWIDTH = C_SPLB_DWIDTH generate sl_rddbus_i <= sgsl_rddbus; end generate GEN_FOR_EQUAL_SLAVE; sl_rddbus <= sl_rddbus_i; sgplb_wrdbus <= plb_wrdbus(0 to C_SPLB_NATIVE_DWIDTH-1); end behavior; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity sg_xsvi_fanout_plbw is generic ( C_BASEADDR: std_logic_vector(31 downto 0) := X"80000000"; C_HIGHADDR: std_logic_vector(31 downto 0) := X"80000FFF"; C_SPLB_AWIDTH: integer := 0; C_SPLB_DWIDTH: integer := 0; C_SPLB_MID_WIDTH: integer := 0; C_SPLB_NATIVE_DWIDTH: integer := 0; C_SPLB_NUM_MASTERS: integer := 0; C_SPLB_SUPPORT_BURSTS: integer := 0 ); port ( active_video_i: in std_logic; hblank_i: in std_logic; hsync_i: in std_logic; plb_abus: in std_logic_vector(0 to 31); plb_pavalid: in std_logic; plb_rnw: in std_logic; plb_wrdbus: in std_logic_vector(0 to C_SPLB_DWIDTH-1); splb_clk: in std_logic; splb_rst: in std_logic; sysgen_clk: in std_logic; vblank_i: in std_logic; video_data_i: in std_logic_vector(0 to 23); vsync_i: in std_logic; active_video_o: out std_logic; hblank_o: out std_logic; hsync_o: out std_logic; sl_addrack: out std_logic; sl_rdcomp: out std_logic; sl_rddack: out std_logic; sl_rddbus: out std_logic_vector(0 to C_SPLB_DWIDTH-1); sl_wait: out std_logic; sl_wrcomp: out std_logic; sl_wrdack: out std_logic; vblank_o: out std_logic; video_data_o: out std_logic_vector(0 to 23); vsync_o: out std_logic ); end sg_xsvi_fanout_plbw; architecture structural of sg_xsvi_fanout_plbw is signal active_video_i_x0: std_logic; signal active_video_o_x0: std_logic; signal clk: std_logic; signal hblank_i_x0: std_logic; signal hblank_o_x0: std_logic; signal hsync_i_x0: std_logic; signal hsync_o_x0: std_logic; signal plb_abus_x0: std_logic_vector(31 downto 0); signal plb_pavalid_x0: std_logic; signal plb_rnw_x0: std_logic; signal plbaddrpref_addrpref_net: std_logic_vector(19 downto 0); signal plbaddrpref_plb_wrdbus_net: std_logic_vector(C_SPLB_DWIDTH-1 downto 0); signal plbaddrpref_sgplb_wrdbus_net: std_logic_vector(31 downto 0); signal plbaddrpref_sgsl_rddbus_net: std_logic_vector(31 downto 0); signal plbaddrpref_sl_rddbus_net: std_logic_vector(C_SPLB_DWIDTH-1 downto 0); signal sl_addrack_x0: std_logic; signal sl_rdcomp_x0: std_logic; signal sl_rddack_x0: std_logic; signal sl_wait_x0: std_logic; signal sl_wrcomp_x0: std_logic; signal sl_wrdack_x0: std_logic; signal splb_rst_x0: std_logic; signal vblank_i_x0: std_logic; signal vblank_o_x0: std_logic; signal video_data_i_x0: std_logic_vector(23 downto 0); signal video_data_o_x0: std_logic_vector(23 downto 0); signal vsync_i_x0: std_logic; signal vsync_o_x0: std_logic; signal xps_clk: std_logic; begin active_video_i_x0 <= active_video_i; hblank_i_x0 <= hblank_i; hsync_i_x0 <= hsync_i; plb_abus_x0 <= plb_abus; plb_pavalid_x0 <= plb_pavalid; plb_rnw_x0 <= plb_rnw; plbaddrpref_plb_wrdbus_net <= plb_wrdbus; xps_clk <= splb_clk; splb_rst_x0 <= splb_rst; clk <= sysgen_clk; vblank_i_x0 <= vblank_i; video_data_i_x0 <= video_data_i; vsync_i_x0 <= vsync_i; active_video_o <= active_video_o_x0; hblank_o <= hblank_o_x0; hsync_o <= hsync_o_x0; sl_addrack <= sl_addrack_x0; sl_rdcomp <= sl_rdcomp_x0; sl_rddack <= sl_rddack_x0; sl_rddbus <= plbaddrpref_sl_rddbus_net; sl_wait <= sl_wait_x0; sl_wrcomp <= sl_wrcomp_x0; sl_wrdack <= sl_wrdack_x0; vblank_o <= vblank_o_x0; video_data_o <= video_data_o_x0; vsync_o <= vsync_o_x0; plbaddrpref_x0: entity work.plbaddrpref generic map ( C_BASEADDR => C_BASEADDR, C_HIGHADDR => C_HIGHADDR, C_SPLB_DWIDTH => C_SPLB_DWIDTH, C_SPLB_NATIVE_DWIDTH => C_SPLB_NATIVE_DWIDTH ) port map ( plb_wrdbus => plbaddrpref_plb_wrdbus_net, sgsl_rddbus => plbaddrpref_sgsl_rddbus_net, addrpref => plbaddrpref_addrpref_net, sgplb_wrdbus => plbaddrpref_sgplb_wrdbus_net, sl_rddbus => plbaddrpref_sl_rddbus_net ); sysgen_dut: entity work.sg_xsvi_fanout_cw port map ( active_video_i => active_video_i_x0, clk => clk, hblank_i => hblank_i_x0, hsync_i => hsync_i_x0, plb_abus => plb_abus_x0, plb_pavalid => plb_pavalid_x0, plb_rnw => plb_rnw_x0, plb_wrdbus => plbaddrpref_sgplb_wrdbus_net, sg_plb_addrpref => plbaddrpref_addrpref_net, splb_rst => splb_rst_x0, vblank_i => vblank_i_x0, video_data_i => video_data_i_x0, vsync_i => vsync_i_x0, xps_clk => xps_clk, active_video_o => active_video_o_x0, hblank_o => hblank_o_x0, hsync_o => hsync_o_x0, sl_addrack => sl_addrack_x0, sl_rdcomp => sl_rdcomp_x0, sl_rddack => sl_rddack_x0, sl_rddbus => plbaddrpref_sgsl_rddbus_net, sl_wait => sl_wait_x0, sl_wrcomp => sl_wrcomp_x0, sl_wrdack => sl_wrdack_x0, vblank_o => vblank_o_x0, video_data_o => video_data_o_x0, vsync_o => vsync_o_x0 ); end structural;
gpl-3.0
d31f4b10f90e08d51f49ceaefe276c2c
0.603577
3.322377
false
false
false
false
fquinto/Wireless_sensor_network
Avnet_UPC/hdl/system_stub.vhd
1
3,568
------------------------------------------------------------------------------- -- system_stub.vhd ------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity system_stub is port ( fpga_0_USB_UART_RX_pin : in std_logic; fpga_0_USB_UART_TX_pin : out std_logic; fpga_0_LEDS_4BIT_GPIO_IO_pin : inout std_logic_vector(0 to 3); fpga_0_CS_PUSH_3BIT_GPIO_IO_I_pin : in std_logic_vector(0 to 2); fpga_0_TEMP_SENSOR_Sda_pin : inout std_logic; fpga_0_TEMP_SENSOR_Scl_pin : inout std_logic; fpga_0_FLASH_2Mx16_Mem_A_pin : out std_logic_vector(10 to 30); fpga_0_FLASH_2Mx16_Mem_RPN_pin : out std_logic; fpga_0_FLASH_2Mx16_Mem_CEN_pin : out std_logic; fpga_0_FLASH_2Mx16_Mem_OEN_pin : out std_logic; fpga_0_FLASH_2Mx16_Mem_WEN_pin : out std_logic; fpga_0_FLASH_2Mx16_Mem_DQ_pin : inout std_logic_vector(0 to 15); fpga_0_FLASH_2Mx16_MEM_BYTEn_pin : out std_logic; fpga_0_clk_1_sys_clk_pin : in std_logic; fpga_0_rst_1_sys_rst_pin : in std_logic; fpga_0_MSP430_UART_TX_pin : out std_logic; fpga_0_MSP430_UART_RX_pin : in std_logic ); end system_stub; architecture STRUCTURE of system_stub is component system is port ( fpga_0_USB_UART_RX_pin : in std_logic; fpga_0_USB_UART_TX_pin : out std_logic; fpga_0_LEDS_4BIT_GPIO_IO_pin : inout std_logic_vector(0 to 3); fpga_0_CS_PUSH_3BIT_GPIO_IO_I_pin : in std_logic_vector(0 to 2); fpga_0_TEMP_SENSOR_Sda_pin : inout std_logic; fpga_0_TEMP_SENSOR_Scl_pin : inout std_logic; fpga_0_FLASH_2Mx16_Mem_A_pin : out std_logic_vector(10 to 30); fpga_0_FLASH_2Mx16_Mem_RPN_pin : out std_logic; fpga_0_FLASH_2Mx16_Mem_CEN_pin : out std_logic; fpga_0_FLASH_2Mx16_Mem_OEN_pin : out std_logic; fpga_0_FLASH_2Mx16_Mem_WEN_pin : out std_logic; fpga_0_FLASH_2Mx16_Mem_DQ_pin : inout std_logic_vector(0 to 15); fpga_0_FLASH_2Mx16_MEM_BYTEn_pin : out std_logic; fpga_0_clk_1_sys_clk_pin : in std_logic; fpga_0_rst_1_sys_rst_pin : in std_logic; fpga_0_MSP430_UART_TX_pin : out std_logic; fpga_0_MSP430_UART_RX_pin : in std_logic ); end component; attribute BOX_TYPE : STRING; attribute BOX_TYPE of system : component is "user_black_box"; begin system_i : system port map ( fpga_0_USB_UART_RX_pin => fpga_0_USB_UART_RX_pin, fpga_0_USB_UART_TX_pin => fpga_0_USB_UART_TX_pin, fpga_0_LEDS_4BIT_GPIO_IO_pin => fpga_0_LEDS_4BIT_GPIO_IO_pin, fpga_0_CS_PUSH_3BIT_GPIO_IO_I_pin => fpga_0_CS_PUSH_3BIT_GPIO_IO_I_pin, fpga_0_TEMP_SENSOR_Sda_pin => fpga_0_TEMP_SENSOR_Sda_pin, fpga_0_TEMP_SENSOR_Scl_pin => fpga_0_TEMP_SENSOR_Scl_pin, fpga_0_FLASH_2Mx16_Mem_A_pin => fpga_0_FLASH_2Mx16_Mem_A_pin, fpga_0_FLASH_2Mx16_Mem_RPN_pin => fpga_0_FLASH_2Mx16_Mem_RPN_pin, fpga_0_FLASH_2Mx16_Mem_CEN_pin => fpga_0_FLASH_2Mx16_Mem_CEN_pin, fpga_0_FLASH_2Mx16_Mem_OEN_pin => fpga_0_FLASH_2Mx16_Mem_OEN_pin, fpga_0_FLASH_2Mx16_Mem_WEN_pin => fpga_0_FLASH_2Mx16_Mem_WEN_pin, fpga_0_FLASH_2Mx16_Mem_DQ_pin => fpga_0_FLASH_2Mx16_Mem_DQ_pin, fpga_0_FLASH_2Mx16_MEM_BYTEn_pin => fpga_0_FLASH_2Mx16_MEM_BYTEn_pin, fpga_0_clk_1_sys_clk_pin => fpga_0_clk_1_sys_clk_pin, fpga_0_rst_1_sys_rst_pin => fpga_0_rst_1_sys_rst_pin, fpga_0_MSP430_UART_TX_pin => fpga_0_MSP430_UART_TX_pin, fpga_0_MSP430_UART_RX_pin => fpga_0_MSP430_UART_RX_pin ); end architecture STRUCTURE;
mit
e0dbc207239b7c55db1fcf625e30c78e
0.625841
2.570605
false
false
false
false
tghaefli/ADD
EDK/IVK_Repos/IVK_IPLib/pcores/sg_xsvi_fanin_plbw_v1_01_a/hdl/vhdl/sg_xsvi_fanin_cw.vhd
1
20,509
------------------------------------------------------------------- -- System Generator version 13.2 VHDL source file. -- -- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- ------------------------------------------------------------------- -- System Generator version 13.2 VHDL source file. -- -- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; -- synopsys translate_off library unisim; use unisim.vcomponents.all; -- synopsys translate_on entity xlclockdriver is generic ( period: integer := 2; log_2_period: integer := 0; pipeline_regs: integer := 5; use_bufg: integer := 0 ); port ( sysclk: in std_logic; sysclr: in std_logic; sysce: in std_logic; clk: out std_logic; clr: out std_logic; ce: out std_logic; ce_logic: out std_logic ); end xlclockdriver; architecture behavior of xlclockdriver is component bufg port ( i: in std_logic; o: out std_logic ); end component; component synth_reg_w_init generic ( width: integer; init_index: integer; init_value: bit_vector; latency: integer ); port ( i: in std_logic_vector(width - 1 downto 0); ce: in std_logic; clr: in std_logic; clk: in std_logic; o: out std_logic_vector(width - 1 downto 0) ); end component; function size_of_uint(inp: integer; power_of_2: boolean) return integer is constant inp_vec: std_logic_vector(31 downto 0) := integer_to_std_logic_vector(inp,32, xlUnsigned); variable result: integer; begin result := 32; for i in 0 to 31 loop if inp_vec(i) = '1' then result := i; end if; end loop; if power_of_2 then return result; else return result+1; end if; end; function is_power_of_2(inp: std_logic_vector) return boolean is constant width: integer := inp'length; variable vec: std_logic_vector(width - 1 downto 0); variable single_bit_set: boolean; variable more_than_one_bit_set: boolean; variable result: boolean; begin vec := inp; single_bit_set := false; more_than_one_bit_set := false; -- synopsys translate_off if (is_XorU(vec)) then return false; end if; -- synopsys translate_on if width > 0 then for i in 0 to width - 1 loop if vec(i) = '1' then if single_bit_set then more_than_one_bit_set := true; end if; single_bit_set := true; end if; end loop; end if; if (single_bit_set and not(more_than_one_bit_set)) then result := true; else result := false; end if; return result; end; function ce_reg_init_val(index, period : integer) return integer is variable result: integer; begin result := 0; if ((index mod period) = 0) then result := 1; end if; return result; end; function remaining_pipe_regs(num_pipeline_regs, period : integer) return integer is variable factor, result: integer; begin factor := (num_pipeline_regs / period); result := num_pipeline_regs - (period * factor) + 1; return result; end; function sg_min(L, R: INTEGER) return INTEGER is begin if L < R then return L; else return R; end if; end; constant max_pipeline_regs : integer := 8; constant pipe_regs : integer := 5; constant num_pipeline_regs : integer := sg_min(pipeline_regs, max_pipeline_regs); constant rem_pipeline_regs : integer := remaining_pipe_regs(num_pipeline_regs,period); constant period_floor: integer := max(2, period); constant power_of_2_counter: boolean := is_power_of_2(integer_to_std_logic_vector(period_floor,32, xlUnsigned)); constant cnt_width: integer := size_of_uint(period_floor, power_of_2_counter); constant clk_for_ce_pulse_minus1: std_logic_vector(cnt_width - 1 downto 0) := integer_to_std_logic_vector((period_floor - 2),cnt_width, xlUnsigned); constant clk_for_ce_pulse_minus2: std_logic_vector(cnt_width - 1 downto 0) := integer_to_std_logic_vector(max(0,period - 3),cnt_width, xlUnsigned); constant clk_for_ce_pulse_minus_regs: std_logic_vector(cnt_width - 1 downto 0) := integer_to_std_logic_vector(max(0,period - rem_pipeline_regs),cnt_width, xlUnsigned); signal clk_num: unsigned(cnt_width - 1 downto 0) := (others => '0'); signal ce_vec : std_logic_vector(num_pipeline_regs downto 0); attribute MAX_FANOUT : string; attribute MAX_FANOUT of ce_vec:signal is "REDUCE"; signal ce_vec_logic : std_logic_vector(num_pipeline_regs downto 0); attribute MAX_FANOUT of ce_vec_logic:signal is "REDUCE"; signal internal_ce: std_logic_vector(0 downto 0); signal internal_ce_logic: std_logic_vector(0 downto 0); signal cnt_clr, cnt_clr_dly: std_logic_vector (0 downto 0); begin clk <= sysclk; clr <= sysclr; cntr_gen: process(sysclk) begin if sysclk'event and sysclk = '1' then if (sysce = '1') then if ((cnt_clr_dly(0) = '1') or (sysclr = '1')) then clk_num <= (others => '0'); else clk_num <= clk_num + 1; end if; end if; end if; end process; clr_gen: process(clk_num, sysclr) begin if power_of_2_counter then cnt_clr(0) <= sysclr; else if (unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus1 or sysclr = '1') then cnt_clr(0) <= '1'; else cnt_clr(0) <= '0'; end if; end if; end process; clr_reg: synth_reg_w_init generic map ( width => 1, init_index => 0, init_value => b"0000", latency => 1 ) port map ( i => cnt_clr, ce => sysce, clr => sysclr, clk => sysclk, o => cnt_clr_dly ); pipelined_ce : if period > 1 generate ce_gen: process(clk_num) begin if unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus_regs then ce_vec(num_pipeline_regs) <= '1'; else ce_vec(num_pipeline_regs) <= '0'; end if; end process; ce_pipeline: for index in num_pipeline_regs downto 1 generate ce_reg : synth_reg_w_init generic map ( width => 1, init_index => ce_reg_init_val(index, period), init_value => b"0000", latency => 1 ) port map ( i => ce_vec(index downto index), ce => sysce, clr => sysclr, clk => sysclk, o => ce_vec(index-1 downto index-1) ); end generate; internal_ce <= ce_vec(0 downto 0); end generate; pipelined_ce_logic: if period > 1 generate ce_gen_logic: process(clk_num) begin if unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus_regs then ce_vec_logic(num_pipeline_regs) <= '1'; else ce_vec_logic(num_pipeline_regs) <= '0'; end if; end process; ce_logic_pipeline: for index in num_pipeline_regs downto 1 generate ce_logic_reg : synth_reg_w_init generic map ( width => 1, init_index => ce_reg_init_val(index, period), init_value => b"0000", latency => 1 ) port map ( i => ce_vec_logic(index downto index), ce => sysce, clr => sysclr, clk => sysclk, o => ce_vec_logic(index-1 downto index-1) ); end generate; internal_ce_logic <= ce_vec_logic(0 downto 0); end generate; use_bufg_true: if period > 1 and use_bufg = 1 generate ce_bufg_inst: bufg port map ( i => internal_ce(0), o => ce ); ce_bufg_inst_logic: bufg port map ( i => internal_ce_logic(0), o => ce_logic ); end generate; use_bufg_false: if period > 1 and (use_bufg = 0) generate ce <= internal_ce(0); ce_logic <= internal_ce_logic(0); end generate; generate_system_clk: if period = 1 generate ce <= sysce; ce_logic <= sysce; end generate; end architecture behavior; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity default_clock_driver is port ( sysce: in std_logic; sysce_clr: in std_logic; sysclk: in std_logic; ce_1: out std_logic; clk_1: out std_logic ); end default_clock_driver; architecture structural of default_clock_driver is attribute syn_noprune: boolean; attribute syn_noprune of structural : architecture is true; attribute optimize_primitives: boolean; attribute optimize_primitives of structural : architecture is false; attribute dont_touch: boolean; attribute dont_touch of structural : architecture is true; signal sysce_clr_x0: std_logic; signal sysce_x0: std_logic; signal sysclk_x0: std_logic; signal xlclockdriver_1_ce: std_logic; signal xlclockdriver_1_clk: std_logic; begin sysce_x0 <= sysce; sysce_clr_x0 <= sysce_clr; sysclk_x0 <= sysclk; ce_1 <= xlclockdriver_1_ce; clk_1 <= xlclockdriver_1_clk; xlclockdriver_1: entity work.xlclockdriver generic map ( log_2_period => 1, period => 1, use_bufg => 0 ) port map ( sysce => sysce_x0, sysclk => sysclk_x0, sysclr => sysce_clr_x0, ce => xlclockdriver_1_ce, clk => xlclockdriver_1_clk ); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity plb_clock_driver is port ( sysce: in std_logic; sysce_clr: in std_logic; sysclk: in std_logic; plb_ce_1: out std_logic; plb_clk_1: out std_logic ); end plb_clock_driver; architecture structural of plb_clock_driver is attribute syn_noprune: boolean; attribute syn_noprune of structural : architecture is true; attribute optimize_primitives: boolean; attribute optimize_primitives of structural : architecture is false; attribute dont_touch: boolean; attribute dont_touch of structural : architecture is true; signal sysce_clr_x0: std_logic; signal sysce_x0: std_logic; signal sysclk_x0: std_logic; signal xlclockdriver_1_ce: std_logic; signal xlclockdriver_1_clk: std_logic; begin sysce_x0 <= sysce; sysce_clr_x0 <= sysce_clr; sysclk_x0 <= sysclk; plb_ce_1 <= xlclockdriver_1_ce; plb_clk_1 <= xlclockdriver_1_clk; xlclockdriver_1: entity work.xlclockdriver generic map ( log_2_period => 1, period => 1, use_bufg => 0 ) port map ( sysce => sysce_x0, sysclk => sysclk_x0, sysclr => sysce_clr_x0, ce => xlclockdriver_1_ce, clk => xlclockdriver_1_clk ); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity sg_xsvi_fanin_cw is port ( active_video_i: in std_logic; ce: in std_logic := '1'; clk: in std_logic; -- clock period = 10.0 ns (100.0 Mhz) hblank_i: in std_logic; hsync_i: in std_logic; plb_abus: in std_logic_vector(31 downto 0); plb_pavalid: in std_logic; plb_rnw: in std_logic; plb_wrdbus: in std_logic_vector(31 downto 0); sg_plb_addrpref: in std_logic_vector(19 downto 0); splb_rst: in std_logic; vblank_i: in std_logic; video_data_i: in std_logic_vector(23 downto 0); vsync_i: in std_logic; xps_ce: in std_logic := '1'; xps_clk: in std_logic; -- clock period = 10.0 ns (100.0 Mhz) active_video_o: out std_logic; hblank_o: out std_logic; hsync_o: out std_logic; sl_addrack: out std_logic; sl_rdcomp: out std_logic; sl_rddack: out std_logic; sl_rddbus: out std_logic_vector(31 downto 0); sl_wait: out std_logic; sl_wrcomp: out std_logic; sl_wrdack: out std_logic; vblank_o: out std_logic; video_data_o: out std_logic_vector(23 downto 0); vsync_o: out std_logic ); end sg_xsvi_fanin_cw; architecture structural of sg_xsvi_fanin_cw is component xlpersistentdff port ( clk: in std_logic; d: in std_logic; q: out std_logic ); end component; attribute syn_black_box: boolean; attribute syn_black_box of xlpersistentdff: component is true; attribute box_type: string; attribute box_type of xlpersistentdff: component is "black_box"; attribute syn_noprune: boolean; attribute optimize_primitives: boolean; attribute dont_touch: boolean; attribute syn_noprune of xlpersistentdff: component is true; attribute optimize_primitives of xlpersistentdff: component is false; attribute dont_touch of xlpersistentdff: component is true; signal active_video_i_net: std_logic; signal active_video_o_net: std_logic; signal ce_1_sg_x0: std_logic; attribute MAX_FANOUT: string; attribute MAX_FANOUT of ce_1_sg_x0: signal is "REDUCE"; signal clkNet: std_logic; signal clkNet_x0: std_logic; signal clk_1_sg_x0: std_logic; signal hblank_i_net: std_logic; signal hblank_o_net: std_logic; signal hsync_i_net: std_logic; signal hsync_o_net: std_logic; signal persistentdff_inst_q: std_logic; attribute syn_keep: boolean; attribute syn_keep of persistentdff_inst_q: signal is true; attribute keep: boolean; attribute keep of persistentdff_inst_q: signal is true; attribute preserve_signal: boolean; attribute preserve_signal of persistentdff_inst_q: signal is true; signal plb_abus_net: std_logic_vector(31 downto 0); signal plb_ce_1_sg_x1: std_logic; attribute MAX_FANOUT of plb_ce_1_sg_x1: signal is "REDUCE"; signal plb_clk_1_sg_x1: std_logic; signal plb_pavalid_net: std_logic; signal plb_rnw_net: std_logic; signal plb_wrdbus_net: std_logic_vector(31 downto 0); signal sg_plb_addrpref_net: std_logic_vector(19 downto 0); signal sl_addrack_net: std_logic; signal sl_rdcomp_net: std_logic; signal sl_rddack_net: std_logic; signal sl_rddbus_net: std_logic_vector(31 downto 0); signal sl_wait_net: std_logic; signal sl_wrdack_x1: std_logic; signal sl_wrdack_x2: std_logic; signal splb_rst_net: std_logic; signal vblank_i_net: std_logic; signal vblank_o_net: std_logic; signal video_data_i_net: std_logic_vector(23 downto 0); signal video_data_o_net: std_logic_vector(23 downto 0); signal vsync_i_net: std_logic; signal vsync_o_net: std_logic; begin active_video_i_net <= active_video_i; clkNet <= clk; hblank_i_net <= hblank_i; hsync_i_net <= hsync_i; plb_abus_net <= plb_abus; plb_pavalid_net <= plb_pavalid; plb_rnw_net <= plb_rnw; plb_wrdbus_net <= plb_wrdbus; sg_plb_addrpref_net <= sg_plb_addrpref; splb_rst_net <= splb_rst; vblank_i_net <= vblank_i; video_data_i_net <= video_data_i; vsync_i_net <= vsync_i; clkNet_x0 <= xps_clk; active_video_o <= active_video_o_net; hblank_o <= hblank_o_net; hsync_o <= hsync_o_net; sl_addrack <= sl_addrack_net; sl_rdcomp <= sl_rdcomp_net; sl_rddack <= sl_rddack_net; sl_rddbus <= sl_rddbus_net; sl_wait <= sl_wait_net; sl_wrcomp <= sl_wrdack_x2; sl_wrdack <= sl_wrdack_x1; vblank_o <= vblank_o_net; video_data_o <= video_data_o_net; vsync_o <= vsync_o_net; default_clock_driver_x0: entity work.default_clock_driver port map ( sysce => '1', sysce_clr => '0', sysclk => clkNet, ce_1 => ce_1_sg_x0, clk_1 => clk_1_sg_x0 ); persistentdff_inst: xlpersistentdff port map ( clk => clkNet, d => persistentdff_inst_q, q => persistentdff_inst_q ); plb_clock_driver_x0: entity work.plb_clock_driver port map ( sysce => '1', sysce_clr => '0', sysclk => clkNet_x0, plb_ce_1 => plb_ce_1_sg_x1, plb_clk_1 => plb_clk_1_sg_x1 ); sg_xsvi_fanin_x0: entity work.sg_xsvi_fanin port map ( active_video_i => active_video_i_net, ce_1 => ce_1_sg_x0, clk_1 => clk_1_sg_x0, hblank_i => hblank_i_net, hsync_i => hsync_i_net, plb_abus => plb_abus_net, plb_ce_1 => plb_ce_1_sg_x1, plb_clk_1 => plb_clk_1_sg_x1, plb_pavalid => plb_pavalid_net, plb_rnw => plb_rnw_net, plb_wrdbus => plb_wrdbus_net, sg_plb_addrpref => sg_plb_addrpref_net, splb_rst => splb_rst_net, vblank_i => vblank_i_net, video_data_i => video_data_i_net, vsync_i => vsync_i_net, active_video_o => active_video_o_net, hblank_o => hblank_o_net, hsync_o => hsync_o_net, sl_addrack => sl_addrack_net, sl_rdcomp => sl_rdcomp_net, sl_rddack => sl_rddack_net, sl_rddbus => sl_rddbus_net, sl_wait => sl_wait_net, sl_wrcomp => sl_wrdack_x2, sl_wrdack => sl_wrdack_x1, vblank_o => vblank_o_net, video_data_o => video_data_o_net, vsync_o => vsync_o_net ); end structural;
gpl-3.0
0583ed37de6a5f99ec1d7869244f3ca5
0.632064
3.45037
false
false
false
false
GSimas/EEL5105
AULA9/C4.vhd
1
824
library IEEE; use IEEE.Std_Logic_1164.all; entity desloc_1_bit_dir is generic(N: natural := 64); port( CLK: in std_logic; ENABLE : in std_logic; RST: in std_logic; sr_in: in std_logic_vector(7 downto 0); sr_out: out std_logic_vector(7 downto 0) ); end entity; architecture rtl of desloc_1_bit_dir is signal sr: std_logic_vector (7 downto 0); -- Registrador de N bits begin process (CLK, RST) begin if (RST = '0') then -- Reset assíncrono do registrador sr <= (others => '0'); elsif (rising_edge(CLK)) then -- Sinal de clock do registrador (subida) if (ENABLE = '1') then -- Sinal de enable do registrador sr(6 downto 0) <= sr_in(7 downto 1);-- Desloca 1 bit para a direita. Bit menos significativo é perdido. sr(7) <= '1'; end if; end if; end process; sr_out <= sr; end rtl;
mit
d9aa00ac12828383d24640a8cc1f0044
0.653285
2.815068
false
false
false
false
hoglet67/AtomFpga
src/common/AVR8/Core/pm_fetch_dec.vhd
4
70,670
--************************************************************************************************ -- PM_FETCH_DEC(internal module) for AVR core -- Version 2.6! (Special version for the JTAG OCD) -- Designed by Ruslan Lepetenok 14.11.2001 -- Modified 31.05.06 -- Modification: -- Registered ramre/ramwe outputs -- cpu_busy logic modified(affects RCALL/ICALL/CALL instruction interract with interrupt) -- SLEEP and CLRWDT instructions support was added -- V-flag bug fixed (AND/ANDI/OR/ORI/EOR) -- V-flag bug fixed (ADIW/SBIW) -- Unused outputs(sreg_bit_num[2..0],idc_sbi_out,idc_cbi_out,idc_bld_out) were removed. -- Output alu_data_d_in[7..0] was removed. -- Gloabal clock enable(cp2en) was added -- cpu_busy(push/pop) + irq bug was fixed 14.07.05 -- BRXX+IRQ interaction was modified -> cpu_busy -- LDS/STS now requires only two cycles for execution (13.01.06 -> last modificatioon) --************************************************************************************************ library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use WORK.AVRuCPackage.all; entity pm_fetch_dec is port( -- Clock and reset cp2 : in std_logic; cp2en : in std_logic; ireset : in std_logic; -- JTAG OCD support valid_instr : out std_logic; insert_nop : in std_logic; block_irq : in std_logic; change_flow : out std_logic; -- Program memory pc : out std_logic_vector (15 downto 0); inst : in std_logic_vector (15 downto 0); -- I/O control adr : out std_logic_vector (15 downto 0); iore : out std_logic; iowe : out std_logic; -- Data memory control ramadr : out std_logic_vector (15 downto 0); ramre : out std_logic; ramwe : out std_logic; cpuwait : in std_logic; -- Data paths dbusin : in std_logic_vector (7 downto 0); dbusout : out std_logic_vector (7 downto 0); -- Interrupt irqlines : in std_logic_vector (22 downto 0); irqack : out std_logic; irqackad : out std_logic_vector(4 downto 0); --Sleep sleepi : out std_logic; irqok : out std_logic; --Watchdog wdri : out std_logic; -- ALU interface(Data inputs) alu_data_r_in : out std_logic_vector(7 downto 0); -- ALU interface(Instruction inputs) idc_add_out : out std_logic; idc_adc_out : out std_logic; idc_adiw_out : out std_logic; idc_sub_out : out std_logic; idc_subi_out : out std_logic; idc_sbc_out : out std_logic; idc_sbci_out : out std_logic; idc_sbiw_out : out std_logic; adiw_st_out : out std_logic; sbiw_st_out : out std_logic; idc_and_out : out std_logic; idc_andi_out : out std_logic; idc_or_out : out std_logic; idc_ori_out : out std_logic; idc_eor_out : out std_logic; idc_com_out : out std_logic; idc_neg_out : out std_logic; idc_inc_out : out std_logic; idc_dec_out : out std_logic; idc_cp_out : out std_logic; idc_cpc_out : out std_logic; idc_cpi_out : out std_logic; idc_cpse_out : out std_logic; idc_lsr_out : out std_logic; idc_ror_out : out std_logic; idc_asr_out : out std_logic; idc_swap_out : out std_logic; -- ALU interface(Data output) alu_data_out : in std_logic_vector(7 downto 0); -- ALU interface(Flag outputs) alu_c_flag_out : in std_logic; alu_z_flag_out : in std_logic; alu_n_flag_out : in std_logic; alu_v_flag_out : in std_logic; alu_s_flag_out : in std_logic; alu_h_flag_out : in std_logic; -- General purpose register file interface reg_rd_in : out std_logic_vector (7 downto 0); reg_rd_out : in std_logic_vector (7 downto 0); reg_rd_adr : out std_logic_vector (4 downto 0); reg_rr_out : in std_logic_vector (7 downto 0); reg_rr_adr : out std_logic_vector (4 downto 0); reg_rd_wr : out std_logic; post_inc : out std_logic; -- POST INCREMENT FOR LD/ST INSTRUCTIONS pre_dec : out std_logic; -- PRE DECREMENT FOR LD/ST INSTRUCTIONS reg_h_wr : out std_logic; reg_h_out : in std_logic_vector (15 downto 0); reg_h_adr : out std_logic_vector (2 downto 0); -- x,y,z reg_z_out : in std_logic_vector (15 downto 0); -- OUTPUT OF R31:R30 FOR LPM/ELPM/IJMP INSTRUCTIONS -- I/O register file interface sreg_fl_in : out std_logic_vector(7 downto 0); globint : in std_logic; -- SREG I flag sreg_fl_wr_en : out std_logic_vector(7 downto 0); --FLAGS WRITE ENABLE SIGNALS spl_out : in std_logic_vector(7 downto 0); sph_out : in std_logic_vector(7 downto 0); sp_ndown_up : out std_logic; -- DIRECTION OF CHANGING OF STACK POINTER SPH:SPL 0->UP(+) 1->DOWN(-) sp_en : out std_logic; -- WRITE ENABLE(COUNT ENABLE) FOR SPH AND SPL REGISTERS rampz_out : in std_logic_vector(7 downto 0); -- Bit processor interface bit_num_r_io : out std_logic_vector (2 downto 0); -- BIT NUMBER FOR CBI/SBI/BLD/BST/SBRS/SBRC/SBIC/SBIS INSTRUCTIONS bitpr_io_out : in std_logic_vector(7 downto 0); -- SBI/CBI OUT branch : out std_logic_vector (2 downto 0); -- NUMBER (0..7) OF BRANCH CONDITION FOR BRBS/BRBC INSTRUCTION bit_pr_sreg_out : in std_logic_vector(7 downto 0); -- BCLR/BSET/BST(T-FLAG ONLY) bld_op_out : in std_logic_vector(7 downto 0); -- BLD OUT (T FLAG) bit_test_op_out : in std_logic; -- OUTPUT OF SBIC/SBIS/SBRS/SBRC sbi_st_out : out std_logic; cbi_st_out : out std_logic; idc_bst_out : out std_logic; idc_bset_out : out std_logic; idc_bclr_out : out std_logic; idc_sbic_out : out std_logic; idc_sbis_out : out std_logic; idc_sbrs_out : out std_logic; idc_sbrc_out : out std_logic; idc_brbs_out : out std_logic; idc_brbc_out : out std_logic; idc_reti_out : out std_logic); end pm_fetch_dec; architecture RTL of pm_fetch_dec is -- COPIES OF OUTPUTS signal ramadr_reg_in : std_logic_vector(15 downto 0); -- INPUT OF THE ADDRESS REGISTER signal ramadr_reg_en : std_logic; -- ADRESS REGISTER CLOCK ENABLE SIGNAL signal irqack_int : std_logic; signal irqackad_int : std_logic_vector(irqackad'range); -- #################################################### -- INTERNAL SIGNALS -- #################################################### -- NEW SIGNALS signal two_word_inst : std_logic; -- CALL/JMP/STS/LDS INSTRUCTION INDICATOR signal ram_adr_int : std_logic_vector (15 downto 0); constant const_ram_to_reg : std_logic_vector := "00000000000"; -- LD/LDS/LDD/ST/STS/STD ADDRESSING GENERAL PURPOSE REGISTER (R0-R31) 0x00..0x19 constant const_ram_to_io_a : std_logic_vector := "00000000001"; -- LD/LDS/LDD/ST/STS/STD ADDRESSING GENERAL I/O PORT 0x20 0x3F constant const_ram_to_io_b : std_logic_vector := "00000000010"; -- LD/LDS/LDD/ST/STS/STD ADDRESSING GENERAL I/O PORT 0x20 0x3F --constant const_ram_to_io_c : std_logic_vector := "0001"; -- LD/LDS/LDD/ST/STS/STD ADDRESSING GENERAL I/O PORT 0x1000 0x1FFF constant const_ram_to_io_c : std_logic_vector := "0010"; -- LD/LDS/LDD/ST/STS/STD ADDRESSING GENERAL I/O PORT 0x2000 0x2FFF -> change by Zvonimir Bandic constant const_ram_to_io_d : std_logic_vector := "00100000000"; -- LD/LDS/LDD/ST/STS/STD ADDRESSING GENERAL I/O PORT 0x1000 0x3FFF -- LD/LDD/ST/STD SIGNALS signal adiw_sbiw_encoder_out : std_logic_vector (4 downto 0); signal adiw_sbiw_encoder_mux_out : std_logic_vector (4 downto 0); -- PROGRAM COUNTER SIGNALS signal program_counter_tmp : std_logic_vector (15 downto 0); -- TO STORE PC DURING LPM/ELPM INSTRUCTIONS signal program_counter : std_logic_vector (15 downto 0); signal program_counter_in : std_logic_vector (15 downto 0); signal program_counter_high_fr : std_logic_vector (7 downto 0); -- TO STORE PC FOR CALL,IRQ,RCALL,ICALL signal pc_low : std_logic_vector (7 downto 0); signal pc_high : std_logic_vector (7 downto 0); signal pc_low_en : std_logic; signal pc_high_en : std_logic; signal offset_brbx : std_logic_vector (15 downto 0); -- OFFSET FOR BRCS/BRCC INSTRUCTION !!CHECKED signal offset_rxx : std_logic_vector (15 downto 0); -- OFFSET FOR RJMP/RCALL INSTRUCTION !!CHECKED signal pa15_pm : std_logic; -- ADDRESS LINE 15 FOR LPM/ELPM INSTRUCTIONS ('0' FOR LPM,RAMPZ(0) FOR ELPM) signal alu_reg_wr : std_logic; -- ALU INSTRUCTIONS PRODUCING WRITE TO THE GENERAL PURPOSE REGISTER FILE -- DATA MEMORY,GENERAL PURPOSE REGISTERS AND I/O REGISTERS LOGIC --! IMPORTANT NOTICE : OPERATIONS WHICH USE STACK POINTER (SPH:SPL) CAN NOT ACCCSESS GENERAL -- PURPOSE REGISTER FILE AND INPUT/OUTPUT REGISTER FILE ! -- THESE OPERATIONS ARE : RCALL/ICALL/CALL/RET/RETI/PUSH/POP INSTRUCTIONS AND INTERRUPT signal reg_file_adr_space : std_logic; -- ACCSESS TO THE REGISTER FILE signal io_file_adr_space : std_logic; -- ACCSESS TO THE I/O FILE -- STATE MACHINES SIGNALS signal irq_start : std_logic; signal nirq_st0 : std_logic; signal irq_st1 : std_logic; signal irq_st2 : std_logic; signal irq_st3 : std_logic; signal ncall_st0 : std_logic; signal call_st1 : std_logic; signal call_st2 : std_logic; signal call_st3 : std_logic; signal nrcall_st0 : std_logic; signal rcall_st1 : std_logic; signal rcall_st2 : std_logic; signal nicall_st0 : std_logic; signal icall_st1 : std_logic; signal icall_st2 : std_logic; signal njmp_st0 : std_logic; signal jmp_st1 : std_logic; signal jmp_st2 : std_logic; signal ijmp_st : std_logic; signal rjmp_st : std_logic; signal nret_st0 : std_logic; signal ret_st1 : std_logic; signal ret_st2 : std_logic; signal ret_st3 : std_logic; signal nreti_st0 : std_logic; signal reti_st1 : std_logic; signal reti_st2 : std_logic; signal reti_st3 : std_logic; signal brxx_st : std_logic; -- BRANCHES signal adiw_st : std_logic; signal sbiw_st : std_logic; signal nskip_inst_st0 : std_logic; signal skip_inst_st1 : std_logic; signal skip_inst_st2 : std_logic; -- ALL SKIP INSTRUCTIONS SBRS/SBRC/SBIS/SBIC/CPSE signal skip_inst_start : std_logic; signal nlpm_st0 : std_logic; signal lpm_st1 : std_logic; signal lpm_st2 : std_logic; signal nelpm_st0 : std_logic; signal elpm_st1 : std_logic; signal elpm_st2 : std_logic; --signal nsts_st0 : std_logic; --signal sts_st1 : std_logic; --signal sts_st2 : std_logic; signal sts_st : std_logic; --signal nlds_st0 : std_logic; --signal lds_st1 : std_logic; --signal lds_st2 : std_logic; signal lds_st : std_logic; signal st_st : std_logic; signal ld_st : std_logic; signal sbi_st : std_logic; signal cbi_st : std_logic; signal push_st : std_logic; signal pop_st : std_logic; -- INTERNAL STATE MACHINES signal nop_insert_st : std_logic; signal cpu_busy : std_logic; -- INTERNAL COPIES OF OUTPUTS signal pc_int : std_logic_vector (15 downto 0); signal adr_int : std_logic_vector (15 downto 0); signal iore_int : std_logic; signal iowe_int : std_logic; signal ramadr_int : std_logic_vector (15 downto 0); signal ramre_int : std_logic; signal ramwe_int : std_logic; signal dbusout_int : std_logic_vector (7 downto 0); -- COMMAND REGISTER signal instruction_reg : std_logic_vector (15 downto 0); -- OUTPUT OF THE INSTRUCTION REGISTER signal instruction_code_reg : std_logic_vector (15 downto 0); -- OUTPUT OF THE INSTRUCTION REGISTER WITH NOP INSERTION signal instruction_reg_ena : std_logic; -- CLOCK ENABLE -- IRQ INTERNAL LOGIC signal irq_int : std_logic; signal irq_vector_adr : std_logic_vector(15 downto 0); -- INTERRUPT RELATING REGISTERS signal pc_for_interrupt : std_logic_vector(15 downto 0); -- DATA EXTRACTOR SIGNALS signal dex_dat8_immed : std_logic_vector (7 downto 0); -- IMMEDIATE CONSTANT (DATA) -> ANDI,ORI,SUBI,SBCI,CPI,LDI signal dex_dat6_immed : std_logic_vector (5 downto 0); -- IMMEDIATE CONSTANT (DATA) -> ADIW,SBIW signal dex_adr12mem_s : std_logic_vector (11 downto 0); -- RELATIVE ADDRESS (SIGNED) -> RCALL,RJMP signal dex_adr6port : std_logic_vector (5 downto 0); -- I/O PORT ADDRESS -> IN,OUT signal dex_adr5port : std_logic_vector (4 downto 0); -- I/O PORT ADDRESS -> CBI,SBI,SBIC,SBIS signal dex_adr_disp : std_logic_vector (5 downto 0); -- DISPLACEMENT FO ADDDRESS -> STD,LDD signal dex_condition : std_logic_vector (2 downto 0); -- CONDITION -> BRBC,BRBS signal dex_bitnum_sreg : std_logic_vector (2 downto 0); -- NUMBER OF BIT IN SREG -> BCLR,BSET signal dex_adrreg_r : std_logic_vector (4 downto 0); -- SOURCE REGISTER ADDRESS -> ....... signal dex_adrreg_d : std_logic_vector (4 downto 0); -- DESTINATION REGISTER ADDRESS -> ...... signal dex_bitop_bitnum : std_logic_vector(2 downto 0); -- NUMBER OF BIT FOR BIT ORIENTEDE OPERATION -> BST/BLD+SBI/CBI+SBIC/SBIS+SBRC/SBRS !! CHECKED signal dex_brxx_offset : std_logic_vector (6 downto 0); -- RELATIVE ADDRESS (SIGNED) -> BRBC,BRBS !! CHECKED signal dex_adiw_sbiw_reg_adr : std_logic_vector (1 downto 0); -- ADDRESS OF THE LOW REGISTER FOR ADIW/SBIW INSTRUCTIONS signal dex_adrreg_d_latched : std_logic_vector (4 downto 0); -- STORE ADDRESS OF DESTINATION REGISTER FOR LDS/STS/POP INSTRUCTIONS signal gp_reg_tmp : std_logic_vector (7 downto 0); -- STORE DATA FROM THE REGISTERS FOR STS,ST INSTRUCTIONS signal cbi_sbi_io_adr_tmp : std_logic_vector (4 downto 0); -- STORE ADDRESS OF I/O PORT FOR CBI/SBI INSTRUCTION signal cbi_sbi_bit_num_tmp : std_logic_vector (2 downto 0); -- STORE ADDRESS OF I/O PORT FOR CBI/SBI INSTRUCTION -- INSTRUCTIONS DECODER SIGNALS signal idc_adc : std_logic; -- INSTRUCTION ADC signal idc_add : std_logic; -- INSTRUCTION ADD signal idc_adiw : std_logic; -- INSTRUCTION ADIW signal idc_and : std_logic; -- INSTRUCTION AND signal idc_andi : std_logic; -- INSTRUCTION ANDI signal idc_asr : std_logic; -- INSTRUCTION ASR signal idc_bclr : std_logic; -- INSTRUCTION BCLR signal idc_bld : std_logic; -- INSTRUCTION BLD signal idc_brbc : std_logic; -- INSTRUCTION BRBC signal idc_brbs : std_logic; -- INSTRUCTION BRBS signal idc_bset : std_logic; -- INSTRUCTION BSET signal idc_bst : std_logic; -- INSTRUCTION BST signal idc_call : std_logic; -- INSTRUCTION CALL signal idc_cbi : std_logic; -- INSTRUCTION CBI signal idc_com : std_logic; -- INSTRUCTION COM signal idc_cp : std_logic; -- INSTRUCTION CP signal idc_cpc : std_logic; -- INSTRUCTION CPC signal idc_cpi : std_logic; -- INSTRUCTION CPI signal idc_cpse : std_logic; -- INSTRUCTION CPSE signal idc_dec : std_logic; -- INSTRUCTION DEC signal idc_elpm : std_logic; -- INSTRUCTION ELPM signal idc_eor : std_logic; -- INSTRUCTION EOR signal idc_icall : std_logic; -- INSTRUCTION ICALL signal idc_ijmp : std_logic; -- INSTRUCTION IJMP signal idc_in : std_logic; -- INSTRUCTION IN signal idc_inc : std_logic; -- INSTRUCTION INC signal idc_jmp : std_logic; -- INSTRUCTION JMP signal idc_ld_x : std_logic; -- INSTRUCTION LD Rx,X ; LD Rx,X+ ;LD Rx,-X signal idc_ld_y : std_logic; -- INSTRUCTION LD Rx,Y ; LD Rx,Y+ ;LD Rx,-Y signal idc_ldd_y : std_logic; -- INSTRUCTION LDD Rx,Y+q signal idc_ld_z : std_logic; -- INSTRUCTION LD Rx,Z ; LD Rx,Z+ ;LD Rx,-Z signal idc_ldd_z : std_logic; -- INSTRUCTION LDD Rx,Z+q signal idc_ldi : std_logic; -- INSTRUCTION LDI signal idc_lds : std_logic; -- INSTRUCTION LDS signal idc_lpm : std_logic; -- INSTRUCTION LPM signal idc_lsr : std_logic; -- INSTRUCTION LSR signal idc_mov : std_logic; -- INSTRUCTION MOV signal idc_mul : std_logic; -- INSTRUCTION MUL signal idc_neg : std_logic; -- INSTRUCTION NEG signal idc_nop : std_logic; -- INSTRUCTION NOP signal idc_or : std_logic; -- INSTRUCTION OR signal idc_ori : std_logic; -- INSTRUCTION ORI signal idc_out : std_logic; -- INSTRUCTION OUT signal idc_pop : std_logic; -- INSTRUCTION POP signal idc_push : std_logic; -- INSTRUCTION PUSH signal idc_rcall : std_logic; -- INSTRUCTION RCALL signal idc_ret : std_logic; -- INSTRUCTION RET signal idc_reti : std_logic; -- INSTRUCTION RETI signal idc_rjmp : std_logic; -- INSTRUCTION RJMP signal idc_ror : std_logic; -- INSTRUCTION ROR signal idc_sbc : std_logic; -- INSTRUCTION SBC signal idc_sbci : std_logic; -- INSTRUCTION SBCI signal idc_sbi : std_logic; -- INSTRUCTION SBI signal idc_sbic : std_logic; -- INSTRUCTION SBIC signal idc_sbis : std_logic; -- INSTRUCTION SBIS signal idc_sbiw : std_logic; -- INSTRUCTION SBIW signal idc_sbrc : std_logic; -- INSTRUCTION SBRC signal idc_sbrs : std_logic; -- INSTRUCTION SBRS signal idc_sleep : std_logic; -- INSTRUCTION SLEEP signal idc_st_x : std_logic; -- INSTRUCTION LD X,Rx ; LD X+,Rx ;LD -X,Rx signal idc_st_y : std_logic; -- INSTRUCTION LD Y,Rx ; LD Y+,Rx ;LD -Y,Rx signal idc_std_y : std_logic; -- INSTRUCTION LDD Y+q,Rx signal idc_st_z : std_logic; -- INSTRUCTION LD Z,Rx ; LD Z+,Rx ;LD -Z,Rx signal idc_std_z : std_logic; -- INSTRUCTION LDD Z+q,Rx signal idc_sts : std_logic; -- INSTRUCTION STS signal idc_sub : std_logic; -- INSTRUCTION SUB signal idc_subi : std_logic; -- INSTRUCTION SUBI signal idc_swap : std_logic; -- INSTRUCTION SWAP signal idc_wdr : std_logic; -- INSTRUCTION WDR -- ADDITIONAL SIGNALS signal idc_psinc : std_logic; -- POST INCREMENT FLAG FOR LD,ST INSTRUCTIONS signal idc_prdec : std_logic; -- PRE DECREMENT FLAG FOR LD,ST INSTRUCTIONS -- ################################################## -- SREG FLAGS WRITE ENABLE SIGNALS alias sreg_c_wr_en : std_logic is sreg_fl_wr_en(0); alias sreg_z_wr_en : std_logic is sreg_fl_wr_en(1); alias sreg_n_wr_en : std_logic is sreg_fl_wr_en(2); alias sreg_v_wr_en : std_logic is sreg_fl_wr_en(3); alias sreg_s_wr_en : std_logic is sreg_fl_wr_en(4); alias sreg_h_wr_en : std_logic is sreg_fl_wr_en(5); alias sreg_t_wr_en : std_logic is sreg_fl_wr_en(6); alias sreg_i_wr_en : std_logic is sreg_fl_wr_en(7); signal sreg_bop_wr_en : std_logic_vector (7 downto 0); signal sreg_adr_eq : std_logic; -- &&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&& begin -- INSTRUCTION FETCH instruction_reg_ena <= '1'; -- FOR TEST instruction_fetch:process(cp2,ireset) begin if ireset='0' then -- RESET instruction_reg <= (others => '0'); elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable if instruction_reg_ena='1' then instruction_reg <= inst; end if; end if; end if; end process; -- TWO WORDS INSTRUCTION DETECTOR (CONNECTED DIRECTLY TO THE INSTRUCTION REGISTER) two_word_inst <= '1' when ((instruction_reg(15 downto 9)&instruction_reg(3 downto 1)="1001010111") or -- CALL (instruction_reg(15 downto 9)&instruction_reg(3 downto 1)="1001010110")) or -- JMP (instruction_reg(15 downto 9)&instruction_reg(3 downto 0) = "10010000000") or -- LDS (instruction_reg(15 downto 9)&instruction_reg(3 downto 0) = "10010010000") -- STS else '0'; -- TO DETECT CALL/JMP/LDS/STS INSTRUCTIONS FOR SBRS/SBRC/SBIS/SBIC/CPSE -- DATA EXTRACTOR (CONNECTED DIRECTLY TO THE INSTRUCTION REGISTER) dex_dat8_immed <= instruction_reg(11 downto 8) & instruction_reg(3 downto 0); dex_dat6_immed <= instruction_reg(7 downto 6) & instruction_reg(3 downto 0); dex_adr12mem_s <= instruction_reg(11 downto 0); dex_adr6port <= instruction_reg(10 downto 9) & instruction_reg(3 downto 0); dex_adr5port <= instruction_reg(7 downto 3); dex_adr_disp <= instruction_reg(13) & instruction_reg(11 downto 10) & instruction_reg(2 downto 0); dex_condition <= instruction_reg(2 downto 0); dex_bitop_bitnum <= instruction_reg(2 downto 0); -- NUMBER(POSITION) OF TESTING BIT IN SBRC/SBRS/SBIC/SBIS INSTRUCTION dex_bitnum_sreg <= instruction_reg(6 downto 4); dex_adrreg_r <= instruction_reg(9) & instruction_reg(3 downto 0); dex_adrreg_d <= instruction_reg(8 downto 4); dex_brxx_offset <= instruction_reg(9 downto 3); -- OFFSET FOR BRBC/BRBS dex_adiw_sbiw_reg_adr <= instruction_reg(5 downto 4); -- ADDRESS OF THE LOW REGISTER FOR ADIW/SBIW INSTRUCTIONS --dex_adrindreg <= instruction_reg(3 downto 2); -- LATCH Rd ADDDRESS FOR LDS/STS/POP INSTRUCTIONS latcht_rd_adr:process(cp2,ireset) begin if ireset ='0' then dex_adrreg_d_latched <= (others => '0'); elsif (cp2='1' and cp2'event) then if (cp2en='1') then -- Clock enable if ((idc_ld_x or idc_ld_y or idc_ldd_y or idc_ld_z or idc_ldd_z) or idc_sts or (idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z)or idc_lds or idc_pop)='1' then dex_adrreg_d_latched <= dex_adrreg_d; end if; end if; end if; end process; -- +++++++++++++++++++++++++++++++++++++++++++++++++ -- R24:R25/R26:R27/R28:R29/R30:R31 ADIW/SBIW ADDRESS CONTROL LOGIC adiw_sbiw_encoder_out <= "11"&dex_adiw_sbiw_reg_adr&'0'; adiw_sbiw_high_reg_adr:process(cp2,ireset) begin if ireset ='0' then adiw_sbiw_encoder_mux_out <= (others=>'0'); elsif(cp2='1' and cp2'event) then if (cp2en='1') then -- Clock enable adiw_sbiw_encoder_mux_out <= adiw_sbiw_encoder_out +1; end if; end if; end process; -- ########################## -- NOP INSERTION --instruction_code_reg <= instruction_reg when nop_insert_st='0' else (others => '0'); instruction_code_reg <= (others => '0') when (nop_insert_st='1') else -- NOP instruction_reg; -- Instruction nop_insert_st <= adiw_st or sbiw_st or cbi_st or sbi_st or rjmp_st or ijmp_st or pop_st or push_st or brxx_st or ld_st or st_st or ncall_st0 or nirq_st0 or nret_st0 or nreti_st0 or nlpm_st0 or njmp_st0 or nrcall_st0 or nicall_st0 or sts_st or lds_st or nskip_inst_st0; -- INSTRUCTION DECODER (CONNECTED AFTER NOP INSERTION LOGIC) idc_adc <= '1' when instruction_code_reg(15 downto 10) = "000111" else '0'; -- 000111XXXXXXXXXX idc_add <= '1' when instruction_code_reg(15 downto 10) = "000011" else '0'; -- 000011XXXXXXXXXX idc_adiw <= '1' when instruction_code_reg(15 downto 8) = "10010110" else '0'; -- 10010110XXXXXXXX idc_and <= '1' when instruction_code_reg(15 downto 10) = "001000" else '0'; -- 001000XXXXXXXXXX idc_andi <= '1' when instruction_code_reg(15 downto 12) = "0111" else '0'; -- 0111XXXXXXXXXXXX idc_asr <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010100101" else '0'; -- 1001010XXXXX0101 idc_bclr <= '1' when instruction_code_reg(15 downto 7)&instruction_code_reg(3 downto 0) = "1001010011000" else '0'; -- 100101001XXX1000 idc_bld <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3) = "11111000" else '0'; -- 1111100XXXXX0XXX idc_brbc <= '1' when instruction_code_reg(15 downto 10) = "111101" else '0'; -- 111101XXXXXXXXXX idc_brbs <= '1' when instruction_code_reg(15 downto 10) = "111100" else '0'; -- 111100XXXXXXXXXX idc_bset <= '1' when instruction_code_reg(15 downto 7)&instruction_code_reg(3 downto 0) = "1001010001000" else '0'; -- 100101000XXX1000 idc_bst <= '1' when instruction_code_reg(15 downto 9) = "1111101" else '0'; -- 1111101XXXXXXXXX idc_call <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 1) = "1001010111" else '0'; -- 1001010XXXXX111X idc_cbi <= '1' when instruction_code_reg(15 downto 8) = "10011000" else '0'; -- 10011000XXXXXXXX idc_com <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010100000" else '0'; -- 1001010XXXXX0000 idc_cp <= '1' when instruction_code_reg(15 downto 10) = "000101" else '0'; -- 000101XXXXXXXXXX idc_cpc <= '1' when instruction_code_reg(15 downto 10) = "000001" else '0'; -- 000001XXXXXXXXXX idc_cpi <= '1' when instruction_code_reg(15 downto 12) = "0011" else '0'; -- 0011XXXXXXXXXXXX idc_cpse <= '1' when instruction_code_reg(15 downto 10) = "000100" else '0'; -- 000100XXXXXXXXXX idc_dec <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010101010" else '0'; -- 1001010XXXXX1010 idc_elpm <= '1' when instruction_code_reg = "1001010111011000" else '0'; -- 1001010111011000 idc_eor <= '1' when instruction_code_reg(15 downto 10) = "001001" else '0'; -- 001001XXXXXXXXXX idc_icall<= '1' when instruction_code_reg(15 downto 8)&instruction_code_reg(3 downto 0) = "100101011001" else '0'; -- 10010101XXXX1001 idc_ijmp <= '1' when instruction_code_reg(15 downto 8)&instruction_code_reg(3 downto 0) = "100101001001" else '0'; -- 10010100XXXX1001 idc_in <= '1' when instruction_code_reg(15 downto 11) = "10110" else '0'; -- 10110XXXXXXXXXXX idc_inc <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010100011" else '0'; -- 1001010XXXXX0011 idc_jmp <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 1) = "1001010110" else '0'; -- 1001010XXXXX110X -- LD,LDD idc_ld_x <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010001100" or instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010001101" or instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010001110" else '0'; idc_ld_y <= '1' when (instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010001001" or instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010001010") else '0'; idc_ldd_y<= '1' when instruction_code_reg(15 downto 14)&instruction_code_reg(12)&instruction_code_reg(9)&instruction_code_reg(3) = "10001" else '0'; -- 10X0XX0XXXXX1XXX idc_ld_z <= '1' when (instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010000001" or instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010000010") else '0'; idc_ldd_z<= '1' when instruction_code_reg(15 downto 14)&instruction_code_reg(12)&instruction_code_reg(9)&instruction_code_reg(3) = "10000" else '0'; -- 10X0XX0XXXXX0XXX -- ###### idc_ldi <= '1' when instruction_code_reg(15 downto 12) = "1110" else '0'; -- 1110XXXXXXXXXXXX idc_lds <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010000000" else '0'; -- 1001000XXXXX0000 idc_lpm <= '1' when instruction_code_reg = "1001010111001000" else '0'; -- 1001010111001000 idc_lsr <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010100110" else '0'; -- 1001010XXXXX0110 idc_mov <= '1' when instruction_code_reg(15 downto 10) = "001011" else '0'; -- 001011XXXXXXXXXX idc_mul <= '1' when instruction_code_reg(15 downto 10) = "100111" else '0'; -- 100111XXXXXXXXXX idc_neg <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010100001" else '0'; -- 1001010XXXXX0001 idc_nop <= '1' when instruction_code_reg = "0000000000000000" else '0'; -- 0000000000000000 idc_or <= '1' when instruction_code_reg(15 downto 10) = "001010" else '0'; -- 001010XXXXXXXXXX idc_ori <= '1' when instruction_code_reg(15 downto 12) = "0110" else '0'; -- 0110XXXXXXXXXXXX idc_out <= '1' when instruction_code_reg(15 downto 11) = "10111" else '0'; -- 10111XXXXXXXXXXX idc_pop <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010001111" else '0'; -- 1001000XXXXX1111 idc_push<= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010011111" else '0'; -- 1001001XXXXX1111 idc_rcall<= '1' when instruction_code_reg(15 downto 12) = "1101" else '0'; -- 1101XXXXXXXXXXXX idc_ret <= '1' when instruction_code_reg(15 downto 7)&instruction_code_reg(4 downto 0) = "10010101001000" else '0'; -- 100101010XX01000 idc_reti <= '1' when instruction_code_reg(15 downto 7)&instruction_code_reg(4 downto 0) = "10010101011000" else '0'; -- 100101010XX11000 idc_rjmp <= '1' when instruction_code_reg(15 downto 12) = "1100" else '0'; -- 1100XXXXXXXXXXXX idc_ror <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010100111" else '0'; -- 1001010XXXXX0111 idc_sbc <= '1' when instruction_code_reg(15 downto 10) = "000010" else '0'; -- 000010XXXXXXXXXX idc_sbci <= '1' when instruction_code_reg(15 downto 12) = "0100" else '0'; -- 0100XXXXXXXXXXXX idc_sbi <= '1' when instruction_code_reg(15 downto 8) = "10011010" else '0'; -- 10011010XXXXXXXX idc_sbic <= '1' when instruction_code_reg(15 downto 8) = "10011001" else '0'; -- 10011001XXXXXXXX idc_sbis <= '1' when instruction_code_reg(15 downto 8) = "10011011" else '0'; -- 10011011XXXXXXXX idc_sbiw <= '1' when instruction_code_reg(15 downto 8) = "10010111" else '0'; -- 10010111XXXXXXXX idc_sbrc <= '1' when instruction_code_reg(15 downto 9) = "1111110" else '0'; -- 1111110XXXXXXXXX idc_sbrs <= '1' when instruction_code_reg(15 downto 9) = "1111111" else '0'; -- 1111111XXXXXXXXX idc_sleep<= '1' when instruction_code_reg(15 downto 5)&instruction_code_reg(3 downto 0) = "100101011001000" else '0'; -- 10010101100X1000 -- ST,STD idc_st_x <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010011100" or instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010011101" or instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010011110" else '0'; idc_st_y <= '1' when (instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010011001" or instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010011010") else '0'; idc_std_y<= '1' when instruction_code_reg(15 downto 14)&instruction_code_reg(12)&instruction_code_reg(9)&instruction_code_reg(3) = "10011" else '0'; -- 10X0XX1XXXXX1XXX idc_st_z <= '1' when (instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010010001" or instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010010010") else '0'; idc_std_z<= '1' when instruction_code_reg(15 downto 14)&instruction_code_reg(12)&instruction_code_reg(9)&instruction_code_reg(3) = "10010" else '0'; -- 10X0XX1XXXXX0XXX -- ###### idc_sts <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010010000" else '0'; -- 1001001XXXXX0000 idc_sub <= '1' when instruction_code_reg(15 downto 10) = "000110" else '0'; -- 000110XXXXXXXXXX idc_subi <= '1' when instruction_code_reg(15 downto 12) = "0101" else '0'; -- 0101XXXXXXXXXXXX idc_swap <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010100010" else '0'; -- 1001010XXXXX0010 idc_wdr <= '1' when instruction_code_reg(15 downto 5)&instruction_code_reg(3 downto 0) = "100101011011000" else '0'; -- 10010101101X1000 -- ADDITIONAL SIGNALS idc_psinc <= '1' when (instruction_code_reg(1 downto 0) = "01" and (idc_st_x or idc_st_y or idc_st_z or idc_ld_x or idc_ld_y or idc_ld_z)='1') else '0'; -- POST INCREMENT FOR LD/ST INSTRUCTIONS idc_prdec <= '1' when (instruction_code_reg(1 downto 0) = "10" and (idc_st_x or idc_st_y or idc_st_z or idc_ld_x or idc_ld_y or idc_ld_z)='1') else '0'; -- PRE DECREMENT FOR LD/ST INSTRUCTIONS -- ########################################################################################################## -- WRITE ENABLE SIGNALS FOR ramadr_reg ramadr_reg_en <= idc_ld_x or idc_ld_y or idc_ldd_y or idc_ld_z or idc_ldd_z or idc_lds or -- LD/LDD/LDS(two cycle execution) idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z or idc_sts or -- ST/STS/STS(two cycle execution) idc_push or idc_pop or idc_rcall or (rcall_st1 and not cpuwait) or idc_icall or (icall_st1 and not cpuwait) or -- RCALL/ICALL call_st1 or (call_st2 and not cpuwait) or irq_st1 or (irq_st2 and not cpuwait) or -- CALL/IRQ idc_ret or (ret_st1 and not cpuwait ) or idc_reti or (reti_st1 and not cpuwait); -- RET/RETI -- ?? -- RAMADR MUX ramadr_reg_in <= sph_out&spl_out when (idc_rcall or (rcall_st1 and not cpuwait)or idc_icall or (icall_st1 and not cpuwait)or -- RCALL/ICALL call_st1 or (call_st2 and not cpuwait) or irq_st1 or (irq_st2 and not cpuwait) or -- CALL/IRQ idc_push )='1' else -- PUSH (sph_out&spl_out)+1 when (idc_ret or (ret_st1 and not cpuwait) or idc_reti or (reti_st1 and not cpuwait) or idc_pop)='1' else -- RET/RETI/POP inst when (idc_lds or idc_sts) ='1' else -- LDS/STS (two cycle execution) reg_h_out when (idc_ld_x or idc_ld_y or idc_ld_z or idc_st_x or idc_st_y or idc_st_z)='1' else -- LD/ST (reg_h_out + ("000000000"&dex_adr_disp)); -- LDD/STD -- ADDRESS REGISTER ramadr_reg:process(cp2,ireset) begin if ireset='0' then ramadr_int <= (others => '0'); elsif(cp2='1' and cp2'event) then if (cp2en='1') then -- Clock enable if (ramadr_reg_en='1') then ramadr_int <= ramadr_reg_in; end if; end if; end if; end process; ramadr <= ramadr_int; -- GENERAL PURPOSE REGISTERS ADDRESSING FLAG FOR ST/STD/STS INSTRUCTIONS gp_reg_adr:process(cp2,ireset) begin if ireset='0' then reg_file_adr_space <='0'; elsif(cp2='1' and cp2'event) then if (cp2en='1') then -- Clock enable if (ramadr_reg_en='1') then if (ramadr_reg_in(15 downto 5)=const_ram_to_reg) then reg_file_adr_space <= '1'; -- ADRESS RANGE 0x0000-0x001F -> REGISTERS (R0-R31) else reg_file_adr_space <= '0'; end if; end if; end if; end if; end process; -- I/O REGISTERS ADDRESSING FLAG FOR ST/STD/STS INSTRUCTIONS io_reg_adr:process(cp2,ireset) begin if ireset='0' then io_file_adr_space<='0'; elsif(cp2='1' and cp2'event) then if (cp2en='1') then -- Clock enable if (ramadr_reg_en='1') then if (ramadr_reg_in(15 downto 5)=const_ram_to_io_a or ramadr_reg_in(15 downto 5)=const_ram_to_io_b or ramadr_reg_in(15 downto 12)=const_ram_to_io_c) then io_file_adr_space <= '1'; -- ADRESS RANGE 0x0020-0x005F -> I/O PORTS (0x00-0x3F) and ADRESS RANGE 0x1000-0x1FFF -> I/O PORTS (0x0FE0-0x1FDF) User Ports else io_file_adr_space <= '0'; end if; end if; end if; end if; end process; -- ########################################################################################################## -- REGRE/REGWE LOGIC (5 BIT ADDSRESS BUS (INTERNAL ONLY) 32 LOCATIONS (R0-R31)) -- WRITE ENABLE FOR Rd REGISTERS alu_reg_wr <= idc_adc or idc_add or idc_adiw or adiw_st or idc_sub or idc_subi or idc_sbc or idc_sbci or idc_sbiw or sbiw_st or idc_and or idc_andi or idc_or or idc_ori or idc_eor or idc_com or idc_neg or idc_inc or idc_dec or idc_lsr or idc_ror or idc_asr or idc_swap; reg_rd_wr <= idc_in or alu_reg_wr or idc_bld or -- ALU INSTRUCTIONS + IN/BLD INSRTRUCTION (pop_st or ld_st or lds_st)or -- POP/LD/LDD/LDS INSTRUCTIONS ((st_st or sts_st) and reg_file_adr_space)or -- ST/STD/STS INSTRUCTION lpm_st2 or idc_ldi or idc_mov; -- LPM/LDI/MOV INSTRUCTION reg_rd_adr <= '1'&dex_adrreg_d(3 downto 0) when (idc_subi or idc_sbci or idc_andi or idc_ori or idc_cpi or idc_ldi)='1' else "00000" when lpm_st2='1' else adiw_sbiw_encoder_out when (idc_adiw or idc_sbiw)='1' else adiw_sbiw_encoder_mux_out when (adiw_st or sbiw_st)='1' else dex_adrreg_d_latched when (((st_st or sts_st) and not reg_file_adr_space) or ld_st or lds_st or pop_st)='1' else ramadr_int(4 downto 0) when ((st_st or sts_st) and reg_file_adr_space)='1'else --!!?? dex_adrreg_d; reg_rr_adr <= ramadr_int(4 downto 0) when ((ld_st or lds_st) and reg_file_adr_space)='1'else --!!?? dex_adrreg_d_latched when ((st_st or sts_st) and reg_file_adr_space)='1'else --!!?? dex_adrreg_r; -- MULTIPLEXER FOR REGISTER FILE Rd INPUT reg_rd_in <= dbusin when (idc_in or ((lds_st or ld_st)and not reg_file_adr_space) or pop_st)='1' else -- FROM INPUT DATA BUS reg_rr_out when ((lds_st or ld_st) and reg_file_adr_space)='1' else gp_reg_tmp when ((st_st or sts_st) and reg_file_adr_space)='1' else -- ST/STD/STS & ADDRESS FROM 0 TO 31 (REGISTER FILE) bld_op_out when (idc_bld='1')else -- FROM BIT PROCESSOR BLD COMMAND reg_rr_out when (idc_mov='1')else -- FOR MOV INSTRUCTION instruction_reg(15 downto 8) when (lpm_st2='1' and reg_z_out(0)='1') else -- LPM/ELPM instruction_reg(7 downto 0) when (lpm_st2='1' and reg_z_out(0)='0') else -- LPM/ELPM dex_dat8_immed when idc_ldi='1' else alu_data_out; -- FROM ALU DATA OUT -- IORE/IOWE LOGIC (6 BIT ADDRESS adr[5..0] FOR I/O PORTS(64 LOCATIONS)) iore_int <= idc_in or idc_sbi or idc_cbi or idc_sbic or idc_sbis or ((ld_st or lds_st) and io_file_adr_space); -- IN/SBI/CBI iowe_int <= '1' when ((idc_out or sbi_st or cbi_st) or ((st_st or sts_st) and io_file_adr_space))='1' else '0'; -- OUT/SBI/CBI + !! ST/STS/STD -- adr[5..0] BUS MULTIPLEXER adr_int <= "0000000000"&dex_adr6port when (idc_in or idc_out) = '1' else -- IN/OUT INSTRUCTIONS "0000000000"&'0'&dex_adr5port when (idc_cbi or idc_sbi or idc_sbic or idc_sbis) ='1' else -- CBI/SBI (READ PHASE) + SBIS/SBIC "0000000000"&'0'&cbi_sbi_io_adr_tmp when (cbi_st or sbi_st)='1' else -- CBI/SBI (WRITE PHASE) ramadr_int-x"20"; --(6)&ramadr_int(4 downto 0); -- LD/LDS/LDD/ST/STS/STD -- ramre LOGIC (16 BIT ADDRESS ramadr[15..0] FOR DATA RAM (64*1024-64-32 LOCATIONS)) --ramre_int <= not(reg_file_adr_space or io_file_adr_space) and -- (ld_st or lds_st2 or pop_st or -- LD/LDD/LDS/POP/ -- ret_st1 or ret_st2 or reti_st1 or reti_st2); -- RET/RETI DataMemoryRead:process(cp2,ireset) begin if ireset='0' then -- Reset ramre_int <= '0'; elsif (cp2='1' and cp2'event) then -- Clock if (cp2en='1') then -- Clock enable case ramre_int is when '0' => if(ramadr_reg_in(15 downto 5)/=const_ram_to_io_a and ramadr_reg_in(15 downto 5)/=const_ram_to_io_b and ramadr_reg_in(15 downto 12)/=const_ram_to_io_c and ramadr_reg_in(15 downto 5)/=const_ram_to_reg and (idc_ld_x or idc_ld_y or idc_ldd_y or idc_ld_z or idc_ldd_z or -- LD/LDD instruction idc_lds or -- LDS instruction(two cycle execution) idc_pop or -- POP instruction idc_ret or -- RET instruction idc_reti)='1') -- RETI instruction then ramre_int <='1'; end if; when '1' => if ((ld_st or lds_st or pop_st or ret_st2 or reti_st2)and not cpuwait)='1' then ramre_int <='0'; end if; when others => null; end case; end if; end if; end process; -- ramwe LOGIC (16 BIT ADDRESS ramadr[15..0] FOR DATA RAM (64*1024-64-32 LOCATIONS)) --ramwe_int <= not(reg_file_adr_space or io_file_adr_space) and -- (st_st or sts_st2 or push_st or rcall_st1 or rcall_st2 or -- ST/STD/STS/PUSH/RCALL -- icall_st1 or icall_st2 or -- ICALL -- call_st2 or call_st3 or -- CALL -- irq_st2 or irq_st3); -- INTERRUPT DataMemoryWrite:process(cp2,ireset) begin if ireset='0' then -- Reset ramwe_int <= '0'; elsif (cp2='1' and cp2'event) then -- Clock if (cp2en='1') then -- Clock enable case ramwe_int is when '0' => if(ramadr_reg_in(15 downto 5)/=const_ram_to_io_a and ramadr_reg_in(15 downto 5)/=const_ram_to_io_b and ramadr_reg_in(15 downto 12)/=const_ram_to_io_c and ramadr_reg_in(15 downto 5)/=const_ram_to_reg and (idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z or -- ST/STD instruction idc_sts or -- STS instruction (two cycle execution) idc_push or -- PUSH instruction idc_rcall or -- RCALL instruction idc_icall or -- ICALL instruction call_st1 or -- CALL instruction irq_st1)='1') -- Interrupt then ramwe_int <='1'; end if; when '1' => if ((st_st or sts_st or push_st or rcall_st2 or icall_st2 or call_st3 or irq_st3)and not cpuwait)='1' then ramwe_int <='0'; end if; when others => null; end case; end if; end if; end process; -- DBUSOUT MULTIPLEXER dbusout_mux_logic: for i in dbusout_int'range generate dbusout_int(i)<= (reg_rd_out(i) and (idc_push or idc_sts or (idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z)))or -- PUSH/ST/STD/STS INSTRUCTIONS (gp_reg_tmp(i) and (st_st or sts_st))or -- NEW (bitpr_io_out(i) and (cbi_st or sbi_st))or -- CBI/SBI INSTRUCTIONS (program_counter(i) and (idc_rcall or idc_icall or call_st1))or -- LOW PART OF PC (program_counter_high_fr(i) and (rcall_st1 or icall_st1 or call_st2))or -- HIGH PART OF PC (pc_for_interrupt(i) and irq_st1) or (pc_for_interrupt(i+8) and irq_st2) or (reg_rd_out(i) and idc_out); -- OUT end generate; -- ALU CONNECTION -- ALU Rr INPUT MUX alu_data_r_in <= dex_dat8_immed when (idc_subi or idc_sbci or idc_andi or idc_ori or idc_cpi)='1' else "00"&dex_dat6_immed when (idc_adiw or idc_sbiw) ='1' else "00000000" when (adiw_st or sbiw_st) ='1' else reg_rr_out; -- gp_reg_tmp STORES TEMPREOARY THE VALUE OF SOURCE REGISTER DURING ST/STD/STS INSTRUCTION gp_registers_trig:process(cp2,ireset) begin if (ireset='0') then gp_reg_tmp <= (others=>'0'); elsif (cp2='1' and cp2'event) then if (cp2en='1') then -- Clock enable -- if ((idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z) or sts_st1)='1' then -- CLOCK ENABLE if ((idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z) or idc_sts)='1' then -- CLOCK ENABLE gp_reg_tmp <= reg_rd_out; end if; end if; end if; end process; -- ********************************************************************************************************** -- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- +++++++++++++++++++++++++++++++++++++++ PROGRAM COUNTER ++++++++++++++++++++++++++++++++++++++++++++++++++ -- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ program_counter_high_store:process(cp2,ireset) begin if ireset='0' then -- RESET program_counter_high_fr <=(others => '0'); elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable if (idc_rcall or idc_icall or call_st1 or irq_st1) ='1' then program_counter_high_fr <= program_counter(15 downto 8); -- STORE HIGH BYTE OF THE PROGRAMM COUNTER FOR RCALL/ICALL/CALL INSTRUCTIONS AND INTERRUPTS end if; end if; end if; end process; program_counter_for_lpm_elpm:process(cp2,ireset) begin if ireset='0' then -- RESET program_counter_tmp<=(others => '0'); elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable if (idc_lpm or idc_elpm) ='1' then program_counter_tmp <= program_counter; end if; end if; end if; end process; pa15_pm <= rampz_out(0) and idc_elpm; -- '0' WHEN LPM INSTRUCTIONS RAMPZ(0) WHEN ELPM INSTRUCTION -- OFFSET FOR BRBC/BRBS INSTRUCTIONS +63/-64 offset_brbx <= "0000000000"&dex_brxx_offset(5 downto 0) when (dex_brxx_offset(6)='0') else -- + "1111111111"&dex_brxx_offset(5 downto 0); -- - -- OFFSET FOR RJMP/RCALL INSTRUCTIONS +2047/-2048 offset_rxx <= "00000"&dex_adr12mem_s(10 downto 0) when (dex_adr12mem_s(11)='0') else -- + "11111"&dex_adr12mem_s(10 downto 0); -- - program_counter <= pc_high&pc_low; program_counter_in <= program_counter + offset_brbx when ((idc_brbc or idc_brbs) and bit_test_op_out) ='1'else -- BRBC/BRBS program_counter + offset_rxx when (idc_rjmp or idc_rcall)='1'else -- RJMP/RCALL reg_z_out when (idc_ijmp or idc_icall)='1'else -- IJMP/ICALL pa15_pm&reg_z_out(15 downto 1) when (idc_lpm or idc_elpm) ='1'else -- LPM/ELPM instruction_reg when (jmp_st1 or call_st1)='1'else -- JMP/CALL "0000000000"&irqackad_int&'0' when irq_st1 ='1' else -- INTERRUPT dbusin&"00000000" when (ret_st1 or reti_st1)='1' else -- RET/RETI -> PC HIGH BYTE "00000000"&dbusin when (ret_st2 or reti_st2)='1' else -- RET/RETI -> PC LOW BYTE program_counter_tmp when (lpm_st1)='1' -- AFTER LPM/ELPM INSTRUCTION else program_counter+1; -- THE MOST USUAL CASE pc_low_en <= not (idc_ld_x or idc_ld_y or idc_ld_z or idc_ldd_y or idc_ldd_z or idc_st_x or idc_st_y or idc_st_z or idc_std_y or idc_std_z or ((sts_st or lds_st) and cpuwait)or idc_adiw or idc_sbiw or idc_push or idc_pop or idc_cbi or idc_sbi or rcall_st1 or icall_st1 or call_st2 or irq_st2 or cpuwait or ret_st1 or reti_st1); pc_high_en <= not (idc_ld_x or idc_ld_y or idc_ld_z or idc_ldd_y or idc_ldd_z or idc_st_x or idc_st_y or idc_st_z or idc_std_y or idc_std_z or ((sts_st or lds_st) and cpuwait) or idc_adiw or idc_sbiw or idc_push or idc_pop or idc_cbi or idc_sbi or rcall_st1 or icall_st1 or call_st2 or irq_st2 or cpuwait or ret_st2 or reti_st2); program_counter_low:process(cp2,ireset) begin if ireset='0' then -- RESET pc_low<=(others => '0'); elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable if pc_low_en ='1' then pc_low <= program_counter_in(7 downto 0); end if; end if; end if; end process; program_counter_high:process(cp2,ireset) begin if ireset='0' then -- RESET pc_high<=(others => '0'); elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable if pc_high_en ='1' then pc_high <= program_counter_in(15 downto 8); end if; end if; end if; end process; pc <= program_counter; program_counter_for_interrupt:process(cp2,ireset) begin if ireset='0' then -- RESET pc_for_interrupt <=(others => '0'); elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable if irq_start ='1' then pc_for_interrupt <= program_counter; end if; end if; end if; end process; -- END OF PROGRAM COUNTER -- STATE MACHINES skip_inst_start <= ((idc_sbrc or idc_sbrs or idc_sbic or idc_sbis) and bit_test_op_out)or (idc_cpse and alu_z_flag_out); skip_instruction_sm:process(cp2,ireset) begin if ireset='0' then -- RESET nskip_inst_st0 <= '0'; skip_inst_st1 <= '0'; skip_inst_st2 <= '0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable nskip_inst_st0 <= (not nskip_inst_st0 and skip_inst_start) or (nskip_inst_st0 and not((skip_inst_st1 and not two_word_inst) or skip_inst_st2)); skip_inst_st1 <= (not skip_inst_st1 and not nskip_inst_st0 and skip_inst_start); skip_inst_st2 <= not skip_inst_st2 and skip_inst_st1 and two_word_inst; end if; end if; end process; alu_state_machines:process(cp2,ireset) begin if ireset='0' then -- RESET adiw_st <= '0'; sbiw_st <= '0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable adiw_st <= not adiw_st and idc_adiw; sbiw_st <= not sbiw_st and idc_sbiw; end if; end if; end process; lpm_state_machine:process(cp2,ireset) begin if ireset='0' then -- RESET nlpm_st0 <= '0'; lpm_st1 <= '0'; lpm_st2 <= '0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable nlpm_st0 <= (not nlpm_st0 and (idc_lpm or idc_elpm)) or (nlpm_st0 and not lpm_st2); lpm_st1 <= (not lpm_st1 and not nlpm_st0 and (idc_lpm or idc_elpm)); -- ?? lpm_st2 <= not lpm_st2 and lpm_st1; end if; end if; end process; lds_state_machine:process(cp2,ireset) begin if ireset='0' then -- RESET lds_st <= '0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable lds_st <= (not lds_st and idc_lds) or (lds_st and cpuwait); end if; end if; end process; sts_state_machine:process(cp2,ireset) begin if ireset='0' then -- RESET sts_st <= '0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable sts_st <= (not sts_st and idc_sts) or (sts_st and cpuwait); end if; end if; end process; jmp_state_machine:process(cp2,ireset) begin if ireset='0' then -- RESET njmp_st0 <= '0'; jmp_st1 <= '0'; jmp_st2 <= '0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable njmp_st0 <= (not njmp_st0 and idc_jmp) or (njmp_st0 and not jmp_st2); jmp_st1 <= not jmp_st1 and not njmp_st0 and idc_jmp; -- ?? jmp_st2 <= not jmp_st2 and jmp_st1; end if; end if; end process; rcall_state_machine:process(cp2,ireset) begin if ireset='0' then -- RESET nrcall_st0 <= '0'; rcall_st1 <= '0'; rcall_st2 <= '0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable nrcall_st0 <= (not nrcall_st0 and idc_rcall) or (nrcall_st0 and not (rcall_st2 and not cpuwait)); rcall_st1 <= (not rcall_st1 and not nrcall_st0 and idc_rcall) or (rcall_st1 and cpuwait); rcall_st2 <= (not rcall_st2 and rcall_st1 and not cpuwait) or (rcall_st2 and cpuwait); end if; end if; end process; icall_state_machine:process(cp2,ireset) begin if ireset='0' then -- RESET nicall_st0 <= '0'; icall_st1 <= '0'; icall_st2 <= '0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable nicall_st0 <= (not nicall_st0 and idc_icall) or (nicall_st0 and not (icall_st2 and not cpuwait)); icall_st1 <= (not icall_st1 and not nicall_st0 and idc_icall) or (icall_st1 and cpuwait); icall_st2 <= (not icall_st2 and icall_st1 and not cpuwait) or (icall_st2 and cpuwait); end if; end if; end process; call_state_machine:process(cp2,ireset) begin if ireset='0' then -- RESET ncall_st0 <= '0'; call_st1 <= '0'; call_st2 <= '0'; call_st3 <= '0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable ncall_st0 <= (not ncall_st0 and idc_call) or (ncall_st0 and not( call_st3 and not cpuwait)); call_st1 <= not call_st1 and not ncall_st0 and idc_call; call_st2 <= (not call_st2 and call_st1) or (call_st2 and cpuwait); call_st3 <= (not call_st3 and call_st2 and not cpuwait) or (call_st3 and cpuwait); end if; end if; end process; ret_state_machine:process(cp2,ireset) begin if ireset='0' then -- RESET nret_st0 <= '0'; ret_st1 <= '0'; ret_st2 <= '0'; ret_st3 <= '0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable nret_st0 <= (not nret_st0 and idc_ret) or (nret_st0 and not ret_st3); ret_st1 <= (not ret_st1 and not nret_st0 and idc_ret) or (ret_st1 and cpuwait); ret_st2 <= (not ret_st2 and ret_st1 and not cpuwait) or (ret_st2 and cpuwait) ; ret_st3 <= not ret_st3 and ret_st2 and not cpuwait; end if; end if; end process; reti_state_machine:process(cp2,ireset) begin if ireset='0' then -- RESET nreti_st0 <= '0'; reti_st1 <= '0'; reti_st2 <= '0'; reti_st3 <= '0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable nreti_st0 <= (not nreti_st0 and idc_reti) or (nreti_st0 and not reti_st3); reti_st1 <= (not reti_st1 and not nreti_st0 and idc_reti) or (reti_st1 and cpuwait); reti_st2 <= (not reti_st2 and reti_st1 and not cpuwait) or (reti_st2 and cpuwait) ; reti_st3 <= not reti_st3 and reti_st2 and not cpuwait; end if; end if; end process; -- INTERRUPT LOGIC AND STATE MACHINE irq_int <= '0' when irqlines="00000000000000000000000" else '1'; irq_vector_adr(15 downto 6)<=(others => '0'); irq_vector_adr(0) <= '0'; -- PRIORITY ENCODER irq_vector_adr(5 downto 1) <= "00001" when irqlines(0)='1' else -- 0x0002 "00010" when irqlines(1)='1' else -- 0x0004 "00011" when irqlines(2)='1' else -- 0x0006 "00100" when irqlines(3)='1' else -- 0x0008 "00101" when irqlines(4)='1' else -- 0x000A "00110" when irqlines(5)='1' else -- 0x000C "00111" when irqlines(6)='1' else -- 0x000E "01000" when irqlines(7)='1' else -- 0x0010 "01001" when irqlines(8)='1' else -- 0x0012 "01010" when irqlines(9)='1' else -- 0x0014 "01011" when irqlines(10)='1' else -- 0x0016 "01100" when irqlines(11)='1' else -- 0x0018 "01101" when irqlines(12)='1' else -- 0x001A "01110" when irqlines(13)='1' else -- 0x001C "01111" when irqlines(14)='1' else -- 0x001E "10000" when irqlines(15)='1' else -- 0x0020 "10001" when irqlines(16)='1' else -- 0x0022 "10010" when irqlines(17)='1' else -- 0x0024 "10011" when irqlines(18)='1' else -- 0x0026 "10100" when irqlines(19)='1' else -- 0x0028 "10101" when irqlines(20)='1' else -- 0x002A "10110" when irqlines(21)='1' else -- 0x002C "10111" when irqlines(22)='1' else -- 0x002E "00000"; -- MULTI CYCLE INSTRUCTION FLAG FOR IRQ cpu_busy <= idc_adiw or idc_sbiw or idc_cbi or idc_sbi or idc_rjmp or idc_ijmp or idc_jmp or jmp_st1 or -- idc_brbs or idc_brbc or -- Old variant ((idc_brbc or idc_brbs) and bit_test_op_out) or idc_lpm or lpm_st1 or skip_inst_start or (skip_inst_st1 and two_word_inst) or idc_ld_x or idc_ld_y or idc_ldd_y or idc_ld_z or idc_ldd_z or (ld_st and cpuwait) or idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z or (st_st and cpuwait) or idc_lds or (lds_st and cpuwait) or idc_sts or (sts_st and cpuwait) or idc_rcall or rcall_st1 or (rcall_st2 and cpuwait) or -- RCALL idc_icall or icall_st1 or (icall_st2 and cpuwait) or -- ICALL idc_call or call_st1 or call_st2 or (call_st3 and cpuwait) or -- CALL idc_push or (push_st and cpuwait) or -- PUSH (added 14.07.05) idc_pop or (pop_st and cpuwait) or -- POP (added 14.07.05) (idc_bclr and sreg_bop_wr_en(7)) or -- ??? CLI (iowe_int and sreg_adr_eq and not dbusout_int(7))or -- ??? Writing '0' to I flag (OUT/STD/ST/STD) nirq_st0 or -- idc_ret or nret_st0 or -- Old variant idc_ret or ret_st1 or ret_st2 or -- idc_reti or nreti_st0; -- At least one instruction must be executed after RETI and before the new interrupt. idc_reti or reti_st1 or reti_st2; sreg_adr_eq <= '1' when adr_int=SREG_Address else '0'; --irq_start <= irq_int and not cpu_busy and globint; irq_start <= irq_int and not cpu_busy and globint; irq_state_machine:process(cp2,ireset) begin if ireset='0' then -- RESET nirq_st0 <= '0'; irq_st1 <= '0'; irq_st2 <= '0'; irq_st3 <= '0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable nirq_st0 <= (not nirq_st0 and irq_start) or (nirq_st0 and not (irq_st3 and not cpuwait)); irq_st1 <= (not irq_st1 and not nirq_st0 and irq_start); irq_st2 <= (not irq_st2 and irq_st1) or (irq_st2 and cpuwait); irq_st3 <= (not irq_st3 and irq_st2 and not cpuwait) or (irq_st3 and cpuwait); end if; end if; end process; irqack_reg:process(cp2,ireset) begin if ireset='0' then -- RESET irqack_int<='0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable irqack_int<= not irqack_int and irq_start; end if; end if; end process; irqack <= irqack_int; irqackad_reg:process(cp2,ireset) begin if ireset='0' then -- RESET irqackad_int<=(others=>'0'); elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable irqackad_int<=irq_vector_adr(5 downto 1); end if; end if; end process; irqackad <= irqackad_int; -- ******************************************************************************************* rjmp_push_pop_ijmp_state_brxx_machine:process(cp2,ireset) begin if ireset='0' then -- RESET rjmp_st <= '0'; ijmp_st <= '0'; push_st <= '0'; pop_st <= '0'; brxx_st <= '0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable rjmp_st <= idc_rjmp; -- ?? ijmp_st <= idc_ijmp; push_st <= (not push_st and idc_push) or (push_st and cpuwait); pop_st <= (not pop_st and idc_pop) or (pop_st and cpuwait); brxx_st <= not brxx_st and (idc_brbc or idc_brbs) and bit_test_op_out; end if; end if; end process; -- LD/LDD/ST/STD ld_st_state_machine:process(cp2,ireset) begin if ireset='0' then -- RESET ld_st <= '0'; st_st <= '0'; elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable ld_st <= (not ld_st and (idc_ld_x or idc_ld_y or idc_ldd_y or idc_ld_z or idc_ldd_z)) or (ld_st and cpuwait); st_st <= (not st_st and (idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z)) or (st_st and cpuwait); end if; end if; end process; -- SBI/CBI sbi_cbi_machine:process(cp2,ireset) begin if ireset='0' then -- RESET sbi_st <= '0'; cbi_st <= '0'; cbi_sbi_io_adr_tmp <= (others => '0'); cbi_sbi_bit_num_tmp <= (others => '0'); elsif (cp2='1' and cp2'event) then -- CLOCK if (cp2en='1') then -- Clock enable sbi_st <= not sbi_st and idc_sbi; cbi_st <= not cbi_st and idc_cbi; cbi_sbi_io_adr_tmp <= dex_adr5port; cbi_sbi_bit_num_tmp <= dex_bitop_bitnum; end if; end if; end process; -- ######################################################################################## -- SREG FLAGS WRITE ENABLE LOGIC bclr_bset_op_en_logic:for i in sreg_bop_wr_en'range generate sreg_bop_wr_en(i) <= '1' when (dex_bitnum_sreg=i and (idc_bclr or idc_bset)='1') else '0'; end generate; sreg_c_wr_en <= idc_add or idc_adc or (idc_adiw or adiw_st) or idc_sub or idc_subi or idc_sbc or idc_sbci or (idc_sbiw or sbiw_st) or idc_com or idc_neg or idc_cp or idc_cpc or idc_cpi or idc_lsr or idc_ror or idc_asr or sreg_bop_wr_en(0); sreg_z_wr_en <= idc_add or idc_adc or (idc_adiw or adiw_st) or idc_sub or idc_subi or idc_sbc or idc_sbci or (idc_sbiw or sbiw_st) or idc_cp or idc_cpc or idc_cpi or idc_and or idc_andi or idc_or or idc_ori or idc_eor or idc_com or idc_neg or idc_inc or idc_dec or idc_lsr or idc_ror or idc_asr or sreg_bop_wr_en(1); sreg_n_wr_en <= idc_add or idc_adc or adiw_st or idc_sub or idc_subi or idc_sbc or idc_sbci or sbiw_st or idc_cp or idc_cpc or idc_cpi or idc_and or idc_andi or idc_or or idc_ori or idc_eor or idc_com or idc_neg or idc_inc or idc_dec or idc_lsr or idc_ror or idc_asr or sreg_bop_wr_en(2); sreg_v_wr_en <= idc_add or idc_adc or adiw_st or idc_sub or idc_subi or -- idc_adiw idc_sbc or idc_sbci or sbiw_st or idc_neg or idc_com or -- idc_sbiw idc_inc or idc_dec or idc_cp or idc_cpc or idc_cpi or idc_lsr or idc_ror or idc_asr or sreg_bop_wr_en(3) or idc_and or idc_andi or idc_or or idc_ori or idc_eor; -- V-flag bug fixing sreg_s_wr_en <= idc_add or idc_adc or adiw_st or idc_sub or idc_subi or idc_sbc or idc_sbci or sbiw_st or idc_cp or idc_cpc or idc_cpi or idc_and or idc_andi or idc_or or idc_ori or idc_eor or idc_com or idc_neg or idc_inc or idc_dec or idc_lsr or idc_ror or idc_asr or sreg_bop_wr_en(4); sreg_h_wr_en <= idc_add or idc_adc or idc_sub or idc_subi or idc_cp or idc_cpc or idc_cpi or idc_sbc or idc_sbci or idc_neg or sreg_bop_wr_en(5); sreg_t_wr_en <= idc_bst or sreg_bop_wr_en(6); sreg_i_wr_en <= irq_st1 or reti_st3 or sreg_bop_wr_en(7); -- WAS "irq_start" sreg_fl_in <= bit_pr_sreg_out when (idc_bst or idc_bclr or idc_bset)='1' else -- TO THE SREG reti_st3&'0'&alu_h_flag_out&alu_s_flag_out&alu_v_flag_out&alu_n_flag_out&alu_z_flag_out&alu_c_flag_out; -- ################################################################################################################# -- ********************************************************************************************* -- ************** INSTRUCTION DECODER OUTPUTS FOR THE OTHER BLOCKS **************************** -- ********************************************************************************************* -- FOR ALU idc_add_out <= idc_add; idc_adc_out <= idc_adc; idc_adiw_out <= idc_adiw; idc_sub_out <= idc_sub; idc_subi_out <= idc_subi; idc_sbc_out <= idc_sbc; idc_sbci_out <= idc_sbci; idc_sbiw_out <= idc_sbiw; adiw_st_out <= adiw_st; sbiw_st_out <= sbiw_st; idc_and_out <= idc_and; idc_andi_out <= idc_andi; idc_or_out <= idc_or; idc_ori_out <= idc_ori; idc_eor_out <= idc_eor; idc_com_out <= idc_com; idc_neg_out <= idc_neg; idc_inc_out <= idc_inc; idc_dec_out <= idc_dec; idc_cp_out <= idc_cp; idc_cpc_out <= idc_cpc; idc_cpi_out <= idc_cpi; idc_cpse_out <= idc_cpse; idc_lsr_out <= idc_lsr; idc_ror_out <= idc_ror; idc_asr_out <= idc_asr; idc_swap_out <= idc_swap; -- FOR THE BIT PROCESSOR sbi_st_out <= sbi_st; cbi_st_out <= cbi_st; idc_bst_out <= idc_bst; idc_bset_out <= idc_bset; idc_bclr_out <= idc_bclr; idc_sbic_out <= idc_sbic; idc_sbis_out <= idc_sbis; idc_sbrs_out <= idc_sbrs; idc_sbrc_out <= idc_sbrc; idc_brbs_out <= idc_brbs; idc_brbc_out <= idc_brbc; idc_reti_out <= idc_reti; -- POST INCREMENT/PRE DECREMENT FOR THE X,Y,Z REGISTERS post_inc <= idc_psinc; pre_dec <= idc_prdec; reg_h_wr <= (idc_st_x or idc_st_y or idc_st_z or idc_ld_x or idc_ld_y or idc_ld_z) and (idc_psinc or idc_prdec); reg_h_adr(0)<= idc_st_x or idc_ld_x; reg_h_adr(1)<= idc_st_y or idc_std_y or idc_ld_y or idc_ldd_y; reg_h_adr(2)<= idc_st_z or idc_std_z or idc_ld_z or idc_ldd_z; -- STACK POINTER CONTROL sp_ndown_up <= idc_pop or idc_ret or (ret_st1 and not cpuwait) or idc_reti or (reti_st1 and not cpuwait); -- ????????? sp_en <= idc_push or idc_pop or idc_rcall or (rcall_st1 and not cpuwait) or idc_icall or (icall_st1 and not cpuwait) or idc_ret or (ret_st1 and not cpuwait) or idc_reti or (reti_st1 and not cpuwait) or call_st1 or (call_st2 and not cpuwait) or irq_st1 or (irq_st2 and not cpuwait); --???????? branch <= dex_condition; bit_num_r_io <= cbi_sbi_bit_num_tmp when (cbi_st or sbi_st)='1' else dex_bitop_bitnum; adr <= adr_int; ramre <= ramre_int; ramwe <= ramwe_int; iore <= iore_int; iowe <= iowe_int; dbusout <= dbusout_int; -- Sleep Control sleepi <= idc_sleep; irqok <= irq_int; -- Watchdog wdri <= idc_wdr; -- ************************** JTAG OCD support ************************************ -- Change of flow change_flow <= '0'; valid_instr <= '0'; end RTL;
apache-2.0
e63d678ad044bc36a71a72ef59aac649
0.556148
3.094946
false
false
false
false
hoglet67/AtomFpga
src/xilinx/DCM/dcm3.vhd
2
2,057
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library UNISIM; use UNISIM.Vcomponents.all; entity dcm3 is port (CLKIN_IN : in std_logic; CLK0_OUT : out std_logic; CLK0_OUT1 : out std_logic; CLK2X_OUT : out std_logic); end dcm3; architecture BEHAVIORAL of dcm3 is signal CLKFX_BUF : std_logic; signal CLKIN_IBUFG : std_logic; signal GND_BIT : std_logic; begin GND_BIT <= '0'; CLKFX_BUFG_INST : BUFG port map (I => CLKFX_BUF, O => CLK0_OUT); DCM_INST : DCM generic map(CLK_FEEDBACK => "NONE", CLKDV_DIVIDE => 4.0, -- 16.000 = 16MHz * 10 / 5 CLKFX_DIVIDE => 5, CLKFX_MULTIPLY => 10, CLKIN_DIVIDE_BY_2 => false, CLKIN_PERIOD => 62.5, CLKOUT_PHASE_SHIFT => "NONE", DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW", DUTY_CYCLE_CORRECTION => true, FACTORY_JF => x"C080", PHASE_SHIFT => 0, STARTUP_WAIT => false) port map (CLKFB => GND_BIT, CLKIN => CLKIN_IN, DSSEN => GND_BIT, PSCLK => GND_BIT, PSEN => GND_BIT, PSINCDEC => GND_BIT, RST => GND_BIT, CLKDV => open, CLKFX => CLKFX_BUF, CLKFX180 => open, CLK0 => open, CLK2X => CLK2X_OUT, CLK2X180 => open, CLK90 => open, CLK180 => open, CLK270 => open, LOCKED => open, PSDONE => open, STATUS => open); end BEHAVIORAL;
apache-2.0
5f4986e6fed8dbc8c16b9ad2d13687fa
0.4035
4.267635
false
false
false
false
hoglet67/AtomFpga
src/common/AVR8/JTAG_OCD_Prg/OCDProgcp2.vhd
4
10,499
--********************************************************************************************** -- JTAG "Flash" programmer for AVR Core(cp2 Clock Domain) -- Version 0.5 -- Modified 20.06.2006 -- Designed by Ruslan Lepetenok --********************************************************************************************** library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use WORK.JTAGPack.all; use WORK.AVRuCPackage.all; entity OCDProgcp2 is port( -- AVR Control ireset : in std_logic; cp2 : in std_logic; -- From/To TCK clock domain("Flash" programmer) FlEEPrgAdr : in std_logic_vector(15 downto 0); FlPrgRdData : out std_logic_vector(15 downto 0); EEPrgRdData : out std_logic_vector(7 downto 0); FlEEPrgWrData : in std_logic_vector(15 downto 0); ChipEraseStart : in std_logic; ChipEraseDone : out std_logic; ProgEnable : in std_logic; FlWrMStart : in std_logic; -- Multiple FlWrSStart : in std_logic; -- Single FlRdMStart : in std_logic; -- Multiple FlRdSStart : in std_logic; -- Single EEWrStart : in std_logic; EERdStart : in std_logic; TAPCtrlTLR : in std_logic; -- TAP Controller is in the Test-Logic/Reset state -- From the core PC : in std_logic_vector(15 downto 0); -- To the PM("Flash") pm_adr : out std_logic_vector(15 downto 0); pm_h_we : out std_logic; pm_l_we : out std_logic; pm_dout : in std_logic_vector(15 downto 0); pm_din : out std_logic_vector(15 downto 0); -- To the "EEPROM" EEPrgSel : out std_logic; EEAdr : out std_logic_vector(11 downto 0); EEWrData : out std_logic_vector(7 downto 0); EERdData : in std_logic_vector(7 downto 0); EEWr : out std_logic ); end OCDProgcp2; architecture RTL of OCDProgcp2 is -- ********************************************************************************** -- *************************** Programmer part ********************************************* -- ********************************************************************************** -- Edge detectors signal TAPCtrlTLRDel : std_logic; -- TAP Run-Test/Idle -- Chip Erase Start edge detector signal ChipEraseStartDel : std_logic; -- Flash Write Start(using Virtual Flash Page Load Register) edge detector signal FlWrMStartDel : std_logic; -- Flash Write Start(using Load Data Low(2d)/Load Data High(2e)) edge detector signal FlWrSStartDel : std_logic; -- Flash Read Start(using Virtual Flash Page Read Register) edge detector signal FlRdMStartDel : std_logic; -- Flash Read Start(using Load Data Low and High Byte(3d)) edge detector signal FlRdSStartDel : std_logic; -- "Flash" programmer state machines signal FlWrCnt : std_logic_vector(1 downto 0) ; -- Write signal FlRdCnt : std_logic_vector(1 downto 0) ; -- Read (Low andHigh bytes) signal FlRd_St : std_logic; -- "Flash" read(Latch data) -- "Flash" address and data registers signal FlashPrgAdrRg : std_logic_vector(15 downto 0); -- Address(Write/Read) signal FlashPrgDataRg : std_logic_vector(15 downto 0); -- Data(for Write) -- Output copies signal pm_h_we_Int : std_logic; signal pm_l_we_Int : std_logic; -- Chip erase signal ChipErase_St : std_logic; -- "EEPROM" support -- Edge detectors signal EEWrStartDel : std_logic; signal EERdStartDel : std_logic; -- EEPROM address and data registers signal EEPrgAdrRg : std_logic_vector(EEAdr'range); -- Address(Write/Read) signal EEPrgDataRg : std_logic_vector(EEWrData'range); -- Data(for Write) signal EEWr_Int : std_logic; -- EEPROM programmer state machines signal EEWrCnt : std_logic_vector(1 downto 0) ; -- Write signal EERdCnt : std_logic_vector(1 downto 0) ; -- Read signal EERd_St : std_logic; begin -- ***************************** Programmer part ******************************** FlashWriteCntAndCtrl:process(cp2) begin if(cp2='1' and cp2'event) then -- Clock cp2(Rising edge) -- Edge detectors TAPCtrlTLRDel <= TAPCtrlTLR; FlWrMStartDel <= FlWrMStart; FlWrSStartDel <= FlWrSStart; -- Delay counter if(TAPCtrlTLR='1') then -- Reset counter FlWrCnt <= (others => '0'); elsif((FlWrMStart='0' and FlWrMStartDel='1')or (FlWrSStart='0' and FlWrSStartDel='1')) then FlWrCnt <= "01"; elsif(FlWrCnt/="00") then FlWrCnt <= FlWrCnt + 1; end if; -- Control if(TAPCtrlTLR='1') then -- Reset control signals pm_h_we_Int <= '0'; pm_l_we_Int <= '0'; else case pm_h_we_Int is when '0' => if((ChipEraseStart='1' and ChipEraseStartDel='0') or FlWrCnt="11") then pm_h_we_Int <= '1'; end if; when '1' => if(ChipErase_St='0' or (ChipErase_St='1' and FlashPrgAdrRg=C_MaxEraseAdr)) then pm_h_we_Int <= '0'; end if; when others => null; end case; case pm_l_we_Int is when '0' => if((ChipEraseStart='1' and ChipEraseStartDel='0') or FlWrCnt="11") then pm_l_we_Int <= '1'; end if; when '1' => if(ChipErase_St='0' or (ChipErase_St='1' and FlashPrgAdrRg=C_MaxEraseAdr)) then pm_l_we_Int <= '0'; end if; when others => null; end case; end if; -- Address (for Erase,Write and Read!!!) if(ChipEraseStart='1' and ChipEraseStartDel='0') then -- Start of chip erase -> Clear address counter FlashPrgAdrRg <= (others => '0'); elsif(ChipErase_St='1') then -- Chip erase -> increment aaddress FlashPrgAdrRg <= FlashPrgAdrRg + 1; elsif(FlWrCnt="11" or FlRdCnt="11") then -- Normal mode FlashPrgAdrRg <= FlEEPrgAdr; end if; -- Data if(ChipEraseStart='1' and ChipEraseStartDel='0') then -- Start of chip erase FlashPrgDataRg <= (others => '1'); elsif(FlWrCnt="11") then -- Write to flash FlashPrgDataRg <= FlEEPrgWrData; end if; -- EEPROM Address (for Erase,Write and Read!!!) if(ChipEraseStart='1' and ChipEraseStartDel='0') then -- Start of chip erase -> Clear address counter EEPrgAdrRg <= (others => '0'); elsif(ChipErase_St='1') then -- Chip erase -> increment aaddress EEPrgAdrRg <= EEPrgAdrRg + 1; elsif(EEWrCnt="11" or EERdCnt="11") then -- Normal mode EEPrgAdrRg <= FlEEPrgAdr(EEPrgAdrRg'range); end if; -- EEPROM Data if(ChipEraseStart='1' and ChipEraseStartDel='0') then -- Start of chip erase EEPrgDataRg <= (others => '1'); elsif(EEWrCnt="11") then -- Write to EEPROM EEPrgDataRg <= FlEEPrgWrData(EEPrgDataRg'range); end if; -- EEPROM Write case EEWr_Int is when '0' => if((ChipEraseStart='1' and ChipEraseStartDel='0') or EEWrCnt="11") then EEWr_Int <= '1'; end if; when '1' => if(ChipErase_St='0' or (ChipErase_St='1' and FlashPrgAdrRg=C_MaxEraseAdr)) then EEWr_Int <= '0'; end if; when others => EEWr_Int <= '0'; end case; -- EEPROM Read state if(EERdCnt="11") then EERd_St <= '1'; else EERd_St <= '0'; end if; end if; end process; -- "Flash" write enables pm_l_we <= pm_l_we_Int; pm_h_we <= pm_h_we_Int; -- "Flash" data inputs pm_din <= FlashPrgDataRg; -- EEPROM EEAdr <= EEPrgAdrRg; EEWrData <= EEPrgDataRg; EEWr <= EEWr_Int; EEPrgSel <= ProgEnable; -- !!!TBD!!! (Add EESAVE) -- Flash read FlashReadCntAndCtrl:process(cp2) begin if(cp2='1' and cp2'event) then -- Clock cp2(Rising edge) -- Edge detectors FlRdMStartDel <= FlRdMStart; FlRdSStartDel <= FlRdSStart; -- EEPROM edge detectors EEWrStartDel <= EEWrStart; EERdStartDel <= EERdStart; -- Delay counter (for read) if(TAPCtrlTLR='1') then -- Reset counter FlRdCnt <= (others => '0'); elsif((FlRdMStart='0' and FlRdMStartDel='1')or (FlRdSStart='0' and FlRdSStartDel='1')) then FlRdCnt <= "01"; elsif(FlRdCnt/="00") then FlRdCnt <= FlRdCnt + 1; end if; if(FlRdCnt="11") then FlRd_St <= '1'; else FlRd_St <= '0'; end if; if(FlRd_St='1') then -- Latch read data FlPrgRdData <= pm_dout; end if; -- EEPROM Read delay counter if(TAPCtrlTLR='1') then -- Reset counter EERdCnt <= (others => '0'); elsif(EERdStart='0' and EERdStartDel='1') then -- Falling edge EERdCnt <= "01"; elsif(EERdCnt/="00") then EERdCnt <= EERdCnt + 1; end if; -- EEPROM Write delay counter if(TAPCtrlTLR='1') then -- Reset counter EEWrCnt <= (others => '0'); elsif(EEWrStart='0' and EEWrStartDel='1') then -- Falling edge EEWrCnt <= "01"; elsif(EEWrCnt/="00") then EEWrCnt <= EEWrCnt + 1; end if; -- EEPROM Read latch if(EERd_St='1') then EEPrgRdData <= EERdData; end if; end if; end process; -- Chip Erase ChipEraseState:process(cp2) begin if(cp2='1' and cp2'event) then -- Clock cp2(Rising edge) ChipEraseStartDel <= ChipEraseStart; -- Edge detector if (TAPCtrlTLR='1') then -- Reset ChipErase_St <= '0'; else case ChipErase_St is when '0' => if(ChipEraseStart='1' and ChipEraseStartDel='0') then -- Start of chip erase ChipErase_St <= '1'; end if; when '1' => if (FlashPrgAdrRg=C_MaxEraseAdr) then ChipErase_St <= '0'; end if; when others => null; end case; end if; end if; end process; -- !!!TBD!!! ChipEraseDone <= not ChipErase_St; -- *************************** End of programmer part ******************************* pm_adr <= FlashPrgAdrRg when (ProgEnable='1') else -- Programming Mode PC; -- Normal Operations end RTL;
apache-2.0
0e84fbda835b37a6dfa14360b1c6793e
0.539861
3.38241
false
false
false
false
hoglet67/AtomFpga
src/common/RamRom_SchakelKaart.vhd
1
3,597
-------------------------------------------------------------------------------- -- Copyright (c) 2016 David Banks -------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / -- \ \ \/ -- \ \ -- / / Filename : RamRom_SchakelKaart -- /___/ /\ Timestamp : 04/07/2016 -- \ \ / \ -- \___\/\___\ -- --Design Name: RamRom_SchakelKaart library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; entity RamRom_SchakelKaart is port (clock : in std_logic; reset_n : in std_logic; -- signals from/to 6502 cpu_addr : in std_logic_vector (15 downto 0); cpu_we : in std_logic; cpu_dout : in std_logic_vector (7 downto 0); cpu_din : out std_logic_vector (7 downto 0); -- signals from/to external memory system ExternCE : out std_logic; ExternWE : out std_logic; ExternA : out std_logic_vector (18 downto 0); ExternDin : out std_logic_vector (7 downto 0); ExternDout : in std_logic_vector (7 downto 0) ); end RamRom_SchakelKaart; architecture behavioral of RamRom_SchakelKaart is signal BFFF_Enable : std_logic; signal RegBFFF : std_logic_vector (7 downto 0); signal RomLatch : std_logic_vector (2 downto 0); -- #A000-#AFFF bank select begin -- Mapping to External SRAM... -- 0x00000 - Atom #A000 Bank 0 -- 0x01000 - Atom #A000 Bank 1 -- 0x02000 - Atom #A000 Bank 2 -- 0x03000 - Atom #A000 Bank 3 -- 0x04000 - Atom #A000 Bank 4 -- 0x05000 - Atom #A000 Bank 5 -- 0x06000 - Atom #A000 Bank 6 -- 0x07000 - Atom #A000 Bank 7 -- 0x08000 - Unused -- 0x09000 - Atom #1000 (BRAN) -- 0x0A000 - Unused -- 0x0B000 - Unused -- 0x0C000 - Atom #C000 (Atom Basic) -- 0x0D000 - Atom #D000 (Atom Float patched for BRAN) -- 0x0E000 - Atom #E000 (Atom SDDOS) -- 0x0F000 - Atom #F000 (Atom Kernel patched) ExternCE <= '1' when cpu_addr(15 downto 14) = "11" else '1' when cpu_addr(15 downto 12) = "1010" else '1' when cpu_addr(15) = '0' else '0'; ExternWE <= '0' when cpu_addr(15) = '1' else '0' when cpu_addr(15 downto 12) = "0001" else cpu_we; ExternA <= "000" & cpu_addr(15 downto 0) when cpu_addr(15 downto 14) = "11" else "0000" & RomLatch & cpu_addr(11 downto 0) when cpu_addr(15 downto 12) = "1010" else "0001" & cpu_addr(14 downto 0) when cpu_addr(15 downto 12) = "0001" else "0100" & cpu_addr(14 downto 0); ExternDin <= cpu_dout; cpu_din <= RegBFFF when BFFF_Enable = '1' else ExternDout; ------------------------------------------------- -- RAM/ROM Board Registers ------------------------------------------------- BFFF_Enable <= '1' when cpu_addr(15 downto 0) = "1011111111111111" else '0'; RomLatchProcess : process (reset_n, clock) begin if reset_n = '0' then RegBFFF <= (others => '0'); elsif rising_edge(clock) then if BFFF_Enable = '1' and cpu_we = '1' then RegBFFF <= cpu_dout; end if; end if; end process; RomLatch <= RegBFFF(2 downto 0); end behavioral;
apache-2.0
c76a3d017afadb2fd2813056f8ce7f91
0.476786
3.482091
false
false
false
false
fquinto/Wireless_sensor_network
Avnet_UPC/hdl/dlmb_cntlr_wrapper.vhd
1
3,132
------------------------------------------------------------------------------- -- dlmb_cntlr_wrapper.vhd ------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; library lmb_bram_if_cntlr_v2_10_b; use lmb_bram_if_cntlr_v2_10_b.all; entity dlmb_cntlr_wrapper is port ( LMB_Clk : in std_logic; LMB_Rst : in std_logic; LMB_ABus : in std_logic_vector(0 to 31); LMB_WriteDBus : in std_logic_vector(0 to 31); LMB_AddrStrobe : in std_logic; LMB_ReadStrobe : in std_logic; LMB_WriteStrobe : in std_logic; LMB_BE : in std_logic_vector(0 to 3); Sl_DBus : out std_logic_vector(0 to 31); Sl_Ready : out std_logic; BRAM_Rst_A : out std_logic; BRAM_Clk_A : out std_logic; BRAM_EN_A : out std_logic; BRAM_WEN_A : out std_logic_vector(0 to 3); BRAM_Addr_A : out std_logic_vector(0 to 31); BRAM_Din_A : in std_logic_vector(0 to 31); BRAM_Dout_A : out std_logic_vector(0 to 31) ); attribute x_core_info : STRING; attribute x_core_info of dlmb_cntlr_wrapper : entity is "lmb_bram_if_cntlr_v2_10_b"; end dlmb_cntlr_wrapper; architecture STRUCTURE of dlmb_cntlr_wrapper is component lmb_bram_if_cntlr is generic ( C_BASEADDR : std_logic_vector(0 to 31); C_HIGHADDR : std_logic_vector(0 to 31); C_MASK : std_logic_vector(0 to 31); C_LMB_AWIDTH : integer; C_LMB_DWIDTH : integer ); port ( LMB_Clk : in std_logic; LMB_Rst : in std_logic; LMB_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1); LMB_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1); LMB_AddrStrobe : in std_logic; LMB_ReadStrobe : in std_logic; LMB_WriteStrobe : in std_logic; LMB_BE : in std_logic_vector(0 to C_LMB_DWIDTH/8-1); Sl_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1); Sl_Ready : out std_logic; BRAM_Rst_A : out std_logic; BRAM_Clk_A : out std_logic; BRAM_EN_A : out std_logic; BRAM_WEN_A : out std_logic_vector(0 to (C_LMB_DWIDTH/8)-1); BRAM_Addr_A : out std_logic_vector(0 to C_LMB_AWIDTH-1); BRAM_Din_A : in std_logic_vector(0 to C_LMB_DWIDTH-1); BRAM_Dout_A : out std_logic_vector(0 to C_LMB_DWIDTH-1) ); end component; begin dlmb_cntlr : lmb_bram_if_cntlr generic map ( C_BASEADDR => X"00000000", C_HIGHADDR => X"00007fff", C_MASK => X"80000000", C_LMB_AWIDTH => 32, C_LMB_DWIDTH => 32 ) port map ( LMB_Clk => LMB_Clk, LMB_Rst => LMB_Rst, LMB_ABus => LMB_ABus, LMB_WriteDBus => LMB_WriteDBus, LMB_AddrStrobe => LMB_AddrStrobe, LMB_ReadStrobe => LMB_ReadStrobe, LMB_WriteStrobe => LMB_WriteStrobe, LMB_BE => LMB_BE, Sl_DBus => Sl_DBus, Sl_Ready => Sl_Ready, BRAM_Rst_A => BRAM_Rst_A, BRAM_Clk_A => BRAM_Clk_A, BRAM_EN_A => BRAM_EN_A, BRAM_WEN_A => BRAM_WEN_A, BRAM_Addr_A => BRAM_Addr_A, BRAM_Din_A => BRAM_Din_A, BRAM_Dout_A => BRAM_Dout_A ); end architecture STRUCTURE;
mit
228cf8729133029b39860df88591b572
0.576948
3.082677
false
false
false
false
fquinto/Wireless_sensor_network
Avnet_UPC/hdl/clock_generator_0_wrapper.vhd
1
3,228
------------------------------------------------------------------------------- -- clock_generator_0_wrapper.vhd ------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; library clock_generator_0_v4_00_a; use clock_generator_0_v4_00_a.all; library clock_generator_v4_00_a; use clock_generator_v4_00_a.all; entity clock_generator_0_wrapper is port ( CLKIN : in std_logic; CLKOUT0 : out std_logic; CLKOUT1 : out std_logic; CLKOUT2 : out std_logic; CLKOUT3 : out std_logic; CLKOUT4 : out std_logic; CLKOUT5 : out std_logic; CLKOUT6 : out std_logic; CLKOUT7 : out std_logic; CLKOUT8 : out std_logic; CLKOUT9 : out std_logic; CLKOUT10 : out std_logic; CLKOUT11 : out std_logic; CLKOUT12 : out std_logic; CLKOUT13 : out std_logic; CLKOUT14 : out std_logic; CLKOUT15 : out std_logic; CLKFBIN : in std_logic; CLKFBOUT : out std_logic; PSCLK : in std_logic; PSEN : in std_logic; PSINCDEC : in std_logic; PSDONE : out std_logic; RST : in std_logic; LOCKED : out std_logic ); attribute x_core_info : STRING; attribute x_core_info of clock_generator_0_wrapper : entity is "clock_generator_v4_00_a"; end clock_generator_0_wrapper; architecture STRUCTURE of clock_generator_0_wrapper is component clock_generator is generic ( C_FAMILY : STRING; C_DEVICE : STRING; C_PACKAGE : STRING; C_SPEEDGRADE : STRING ); port ( CLKIN : in std_logic; CLKOUT0 : out std_logic; CLKOUT1 : out std_logic; CLKOUT2 : out std_logic; CLKOUT3 : out std_logic; CLKOUT4 : out std_logic; CLKOUT5 : out std_logic; CLKOUT6 : out std_logic; CLKOUT7 : out std_logic; CLKOUT8 : out std_logic; CLKOUT9 : out std_logic; CLKOUT10 : out std_logic; CLKOUT11 : out std_logic; CLKOUT12 : out std_logic; CLKOUT13 : out std_logic; CLKOUT14 : out std_logic; CLKOUT15 : out std_logic; CLKFBIN : in std_logic; CLKFBOUT : out std_logic; PSCLK : in std_logic; PSEN : in std_logic; PSINCDEC : in std_logic; PSDONE : out std_logic; RST : in std_logic; LOCKED : out std_logic ); end component; begin clock_generator_0 : clock_generator generic map ( C_FAMILY => "spartan3a", C_DEVICE => "3s400a", C_PACKAGE => "ft256", C_SPEEDGRADE => "-4" ) port map ( CLKIN => CLKIN, CLKOUT0 => CLKOUT0, CLKOUT1 => CLKOUT1, CLKOUT2 => CLKOUT2, CLKOUT3 => CLKOUT3, CLKOUT4 => CLKOUT4, CLKOUT5 => CLKOUT5, CLKOUT6 => CLKOUT6, CLKOUT7 => CLKOUT7, CLKOUT8 => CLKOUT8, CLKOUT9 => CLKOUT9, CLKOUT10 => CLKOUT10, CLKOUT11 => CLKOUT11, CLKOUT12 => CLKOUT12, CLKOUT13 => CLKOUT13, CLKOUT14 => CLKOUT14, CLKOUT15 => CLKOUT15, CLKFBIN => CLKFBIN, CLKFBOUT => CLKFBOUT, PSCLK => PSCLK, PSEN => PSEN, PSINCDEC => PSINCDEC, PSDONE => PSDONE, RST => RST, LOCKED => LOCKED ); end architecture STRUCTURE;
mit
c9bcde9c32a096a2f1b973c1914d903e
0.5728
3.635135
false
false
false
false
GSimas/EEL5105
PROJETO-EEL5105/Projeto/FSM_speed.vhd
1
1,707
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; --FSM para controlar velocidade do carro entity FSM_speed is port( CLK, RST, BRK, ACC, EN_TIME: in std_logic; speed: out std_logic_vector(2 downto 0) ); end FSM_speed; --Definir arquitetura architecture bhv of FSM_speed is type states is (S0,S1,S2,S3,S4,S5); signal EA, PE: states; begin --Processo 1 para Clock e Reset P1: process(CLK, RST, EN_TIME) begin if RST = '0' then EA <= S0; elsif CLK'event and CLK = '1' and EN_TIME = '1' then EA <= PE; end if; end process; --Processo 2 para acelerar e frear P2: process(EA, BRK, ACC) begin case EA is when S0 => speed <= "000"; if BRK = '1' and ACC = '0' then PE <= S1; else PE <= S0; end if; when S1 => speed <= "001"; if BRK = '1' and ACC = '0' then PE <= S2; elsif BRK = '0' and ACC = '1' then PE <= S0; else PE <= S1; end if; when S2 => speed <= "010"; if BRK = '1' and ACC = '0' then PE <= S3; elsif BRK = '0' and ACC = '1' then PE <= S1; else PE <= S2; end if; when S3 => speed <= "011"; if BRK = '1' and ACC = '0' then PE <= S4; elsif BRK = '0' and ACC = '1' then PE <= S2; else PE <= S3; end if; when S4 => speed <= "100"; if BRK = '1' and ACC = '0' then PE <= S5; elsif BRK = '0' and ACC = '1' then PE <= S3; else PE <= S4; end if; when S5 => speed <= "101"; if BRK = '0' and ACC = '1' then PE <= S4; else PE <= S5; end if; end case; end process; end bhv;
mit
68302202875e0fad74d734b841814138
0.499121
2.590288
false
false
false
false
msiddalingaiah/TTA
VHDL/ProgramMemoryTest.vhd
1
3,958
-------------------------------------------------------------------------------- -- Copyright 2014 Madhu Siddalingaiah -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -- Entity: ProgramMemoryTest -- Date: 2014-10-09 -- Author: Madhu -- -- Description: -------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; -- Avoid using ieee.std_logic_arith.all use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; entity ProgramMemoryTest is generic ( DATA_WIDTH : integer := 16; ADDRESS_WIDTH : integer := 16; DEPTH : natural := 1024 ); end ProgramMemoryTest; architecture arch of ProgramMemoryTest is component ProgramMemory generic ( DATA_WIDTH : integer; ADDRESS_WIDTH : integer; DEPTH : natural ); port ( reset : in std_logic; clock : in std_logic; data_in : in std_logic_vector(DATA_WIDTH-1 downto 0); pc_in : in std_logic_vector(ADDRESS_WIDTH-1 downto 0); data_out : out std_logic_vector(DATA_WIDTH-1 downto 0); pc_out : out std_logic_vector(ADDRESS_WIDTH-1 downto 0); memory_write : in std_logic; pc_write : in std_logic ); end component; signal reset : std_logic := '0'; signal clock : std_logic := '0'; signal data_in : std_logic_vector (DATA_WIDTH - 1 downto 0 ); signal pc_in : std_logic_vector (ADDRESS_WIDTH - 1 downto 0 ); signal data_out : std_logic_vector (DATA_WIDTH - 1 downto 0 ); signal pc_out : std_logic_vector (ADDRESS_WIDTH - 1 downto 0 ); signal memory_write : std_logic; signal pc_write : std_logic; signal runSimulation : std_logic := '1'; begin dut : ProgramMemory generic map( DATA_WIDTH => DATA_WIDTH, ADDRESS_WIDTH => ADDRESS_WIDTH, DEPTH => DEPTH ) port map( reset => reset, clock => clock, data_in => data_in, pc_in => pc_in, data_out => data_out, pc_out => pc_out, memory_write => memory_write, pc_write => pc_write ); process begin wait for 5 ns; clock <= not clock; if runSimulation = '0' then wait; end if; end process; stimulus : process procedure doReset is begin pc_in <= (others => '0'); data_in <= (others => '0'); pc_write <= '0'; memory_write <= '0'; wait for 2 ns; reset <= '1'; wait for 6 ns; reset <= '0'; end doReset; procedure write_inst(dIn : std_logic_vector(DATA_WIDTH-1 downto 0)) is begin data_in <= dIn; memory_write <= '1'; wait until rising_edge(clock); memory_write <= '0'; end write_inst; begin doReset; wait until rising_edge(clock); write_inst(x"000a"); write_inst(x"000b"); write_inst(x"000c"); write_inst(x"000d"); pc_in <= (others => '0'); pc_write <= '1'; wait until rising_edge(clock); pc_write <= '0'; wait until rising_edge(clock); wait until rising_edge(clock); wait until rising_edge(clock); wait until rising_edge(clock); wait until rising_edge(clock); runSimulation <= '0'; wait; end process stimulus; end arch;
apache-2.0
594e1d6adcfc189a957458a780e4b9d2
0.553562
3.888016
false
false
false
false
hoglet67/AtomFpga
src/xilinx/DCM/dcm2.vhd
1
2,355
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library UNISIM; use UNISIM.Vcomponents.all; entity dcm2 is port (CLKIN_IN : in std_logic; CLK0_OUT : out std_logic; CLKFX_OUT : out std_logic); end dcm2; architecture BEHAVIORAL of dcm2 is signal GND_BIT : std_logic; signal CLKIN : std_logic; signal CLKFX : std_logic; signal CLKFX_BUF : std_logic; signal CLK0 : std_logic; signal CLK0_BUF : std_logic; signal CLKFB : std_logic; begin GND_BIT <= '0'; -- CLK0 output buffer CLK0_BUFG_INST : BUFG port map (I => CLK0, O => CLK0_BUF); CLK0_OUT <= CLK0_BUF; -- CLKFX output buffer CLKFX_BUFG_INST : BUFG port map (I => CLKFX, O => CLKFX_BUF); CLKFX_OUT <= CLKFX_BUF; DCM_INST : DCM generic map(CLK_FEEDBACK => "1X", CLKDV_DIVIDE => 4.0, -- 16.000 = 25MHz * 16 / 25 CLKFX_DIVIDE => 25, CLKFX_MULTIPLY => 16, CLKIN_DIVIDE_BY_2 => false, CLKIN_PERIOD => 40.000, CLKOUT_PHASE_SHIFT => "NONE", DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW", DUTY_CYCLE_CORRECTION => true, FACTORY_JF => x"C080", PHASE_SHIFT => 0, STARTUP_WAIT => false) port map (CLKFB => CLK0_BUF, CLKIN => CLKIN_IN, DSSEN => GND_BIT, PSCLK => GND_BIT, PSEN => GND_BIT, PSINCDEC => GND_BIT, RST => GND_BIT, CLKDV => open, CLKFX => CLKFX, CLKFX180 => open, CLK0 => CLK0, CLK2X => open, CLK2X180 => open, CLK90 => open, CLK180 => open, CLK270 => open, LOCKED => open, PSDONE => open, STATUS => open); end BEHAVIORAL;
apache-2.0
ca3d08dc8ef42349c66270eebd1f2d82
0.414437
4.228007
false
false
false
false
hoglet67/AtomFpga
src/common/ps2kybrd/keyboard.vhd
1
9,805
library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use ieee.std_logic_unsigned.all; entity keyboard is port ( CLOCK : in std_logic; nRESET : in std_logic; CLKEN_1MHZ : in std_logic; PS2_CLK : in std_logic; PS2_DATA : in std_logic; KEYOUT : out std_logic_vector(5 downto 0); ROW : in std_logic_vector(3 downto 0); ESC_IN : in std_logic; BREAK_IN : in std_logic; SHIFT_OUT : out std_logic; CTRL_OUT : out std_logic; REPEAT_OUT : out std_logic; BREAK_OUT : out std_logic; TURBO : out std_logic_vector(1 downto 0); ESC_OUT : out std_logic; Joystick1 : in std_logic_vector (7 downto 0); Joystick2 : in std_logic_vector (7 downto 0) ); end entity; architecture rtl of keyboard is component ps2_intf is generic (filter_length : positive := 8); port( CLK : in std_logic; nRESET : in std_logic; PS2_CLK : in std_logic; PS2_DATA : in std_logic; DATA : out std_logic_vector(7 downto 0); VALID : out std_logic; error : out std_logic ); end component; signal keyb_data : std_logic_vector(7 downto 0); signal keyb_valid : std_logic; signal keyb_error : std_logic; type key_matrix is array(0 to 15) of std_logic_vector(7 downto 0); signal keys : key_matrix; signal col : unsigned(3 downto 0); signal release : std_logic; signal extended : std_logic; signal key_data : std_logic_vector(7 downto 0); signal ESC_IN1 : std_logic; signal BREAK_IN1 : std_logic; begin ps2 : ps2_intf port map ( CLOCK, nRESET, PS2_CLK, PS2_DATA, keyb_data, keyb_valid, keyb_error); process(keys, ROW) begin key_data <= keys(conv_integer(ROW(3 downto 0))); -- 0 U R D L F if (ROW = "0000") then KEYOUT <= key_data(5 downto 0) and ('1' & Joystick1(0) & Joystick1(3) & Joystick1(1) & Joystick1(2) & Joystick1(5)); elsif (ROW = "0001") then KEYOUT <= key_data(5 downto 0) and ('1' & Joystick2(0) & Joystick2(3) & Joystick2(1) & Joystick2(2) & Joystick2(5)); else KEYOUT <= key_data(5 downto 0); end if; end process; process(CLOCK, nRESET) begin if nRESET = '0' then release <= '0'; extended <= '0'; TURBO <= "00"; BREAK_OUT <= '1'; SHIFT_OUT <= '1'; CTRL_OUT <= '1'; REPEAT_OUT <= '1'; ESC_IN1 <= ESC_IN; BREAK_IN1 <= BREAK_IN; keys(0) <= (others => '1'); keys(1) <= (others => '1'); keys(2) <= (others => '1'); keys(3) <= (others => '1'); keys(4) <= (others => '1'); keys(5) <= (others => '1'); keys(6) <= (others => '1'); keys(7) <= (others => '1'); keys(8) <= (others => '1'); keys(9) <= (others => '1'); keys(10) <= (others => '1'); keys(11) <= (others => '1'); keys(12) <= (others => '1'); keys(13) <= (others => '1'); keys(14) <= (others => '1'); keys(15) <= (others => '1'); elsif rising_edge(CLOCK) then -- handle the escape key seperately, as it's value also depends on ESC_IN if keyb_valid = '1' and keyb_data = X"76" then keys(0)(5) <= release; elsif ESC_IN /= ESC_IN1 then keys(0)(5) <= ESC_IN; end if; ESC_IN1 <= ESC_IN; -- handle the break key seperately, as it's value also depends on BREAK_IN if keyb_valid = '1' and keyb_data = X"09" then BREAK_OUT <= release; elsif BREAK_IN /= BREAK_IN1 then BREAK_OUT <= BREAK_IN; end if; BREAK_IN1 <= BREAK_IN; if keyb_valid = '1' then if keyb_data = X"e0" then extended <= '1'; elsif keyb_data = X"f0" then release <= '1'; else release <= '0'; extended <= '0'; case keyb_data is when X"05" => TURBO <= "00"; -- F1 (1MHz) when X"06" => TURBO <= "01"; -- F2 (2MMz) when X"04" => TURBO <= "10"; -- F3 (4MHz) when X"0C" => TURBO <= "11"; -- F4 (8MHz) -- when X"09" => BREAK_OUT <= release; -- F10 (BREAK) when X"11" => REPEAT_OUT <= release; -- LEFT ALT (SHIFT LOCK) when X"12" | X"59" => if (extended = '0') then -- Ignore fake shifts SHIFT_OUT <= release; -- Left SHIFT -- Right SHIFT end if; when X"14" => CTRL_OUT <= release; -- LEFT/RIGHT CTRL (CTRL) ----------------------------------------------------- -- process matrix ----------------------------------------------------- when X"29" => keys(9)(0) <= release; -- SPACE when X"54" => keys(8)(0) <= release; -- [ when X"5D" => keys(7)(0) <= release; -- \ when X"5B" => keys(6)(0) <= release; -- ] when X"0D" => keys(5)(0) <= release; -- UP when X"58" => keys(4)(0) <= release; -- CAPS LOCK when X"74" => keys(3)(0) <= release; -- RIGHT when X"75" => keys(2)(0) <= release; -- UP when X"5A" => keys(6)(1) <= release; -- RETURN when X"69" => keys(5)(1) <= release; -- END (COPY) when X"66" => keys(4)(1) <= release; -- BACKSPACE (DELETE) when X"45" => keys(3)(1) <= release; -- 0 when X"16" => keys(2)(1) <= release; -- 1 when X"1E" => keys(1)(1) <= release; -- 2 when X"26" => keys(0)(1) <= release; -- 3 when X"25" => keys(9)(2) <= release; -- 4 when X"2E" => keys(8)(2) <= release; -- 5 when X"36" => keys(7)(2) <= release; -- 6 when X"3D" => keys(6)(2) <= release; -- 7 when X"3E" => keys(5)(2) <= release; -- 8 when X"46" => keys(4)(2) <= release; -- 9 when X"52" => keys(3)(2) <= release; -- ' full colon substitute when X"4C" => keys(2)(2) <= release; -- ; when X"41" => keys(1)(2) <= release; -- , when X"4E" => keys(0)(2) <= release; -- - when X"49" => keys(9)(3) <= release; -- . when X"4A" => keys(8)(3) <= release; -- / when X"55" => keys(7)(3) <= release; -- @ (TAB) when X"1C" => keys(6)(3) <= release; -- A when X"32" => keys(5)(3) <= release; -- B when X"21" => keys(4)(3) <= release; -- C when X"23" => keys(3)(3) <= release; -- D when X"24" => keys(2)(3) <= release; -- E when X"2B" => keys(1)(3) <= release; -- F when X"34" => keys(0)(3) <= release; -- G when X"33" => keys(9)(4) <= release; -- H when X"43" => keys(8)(4) <= release; -- I when X"3B" => keys(7)(4) <= release; -- J when X"42" => keys(6)(4) <= release; -- K when X"4B" => keys(5)(4) <= release; -- L when X"3A" => keys(4)(4) <= release; -- M when X"31" => keys(3)(4) <= release; -- N when X"44" => keys(2)(4) <= release; -- O when X"4D" => keys(1)(4) <= release; -- P when X"15" => keys(0)(4) <= release; -- Q when X"2D" => keys(9)(5) <= release; -- R when X"1B" => keys(8)(5) <= release; -- S when X"2C" => keys(7)(5) <= release; -- T when X"3C" => keys(6)(5) <= release; -- U when X"2A" => keys(5)(5) <= release; -- V when X"1D" => keys(4)(5) <= release; -- W when X"22" => keys(3)(5) <= release; -- X when X"35" => keys(2)(5) <= release; -- Y when X"1A" => keys(1)(5) <= release; -- Z -- when X"76" => keys(0)(5) <= release; -- ESCAPE when others => null; end case; end if; end if; end if; end process; ESC_OUT <= keys(0)(5); end architecture;
apache-2.0
1563967640649195a8709e1e73a68008
0.372157
3.758145
false
false
false
false
hoglet67/AtomFpga
src/common/AVR8/JTAG_OCD_Prg/JTAGOCDPrgTop.vhd
4
8,331
--********************************************************************************************** -- Top entity for "Flash" programmer (for AVR Core) -- Version 0.3A -- Modified 31.05.2006 -- Designed by Ruslan Lepetenok --********************************************************************************************** library IEEE; use IEEE.std_logic_1164.all; use WORK.JTAGCompPack.all; entity JTAGOCDPrgTop is port( -- AVR Control ireset : in std_logic; cp2 : in std_logic; -- JTAG related inputs/outputs TRSTn : in std_logic; -- Optional TMS : in std_logic; TCK : in std_logic; TDI : in std_logic; TDO : out std_logic; TDO_OE : out std_logic; -- From the core PC : in std_logic_vector(15 downto 0); -- To the PM("Flash") pm_adr : out std_logic_vector(15 downto 0); pm_h_we : out std_logic; pm_l_we : out std_logic; pm_dout : in std_logic_vector(15 downto 0); pm_din : out std_logic_vector(15 downto 0); -- To the "EEPROM" EEPrgSel : out std_logic; EEAdr : out std_logic_vector(11 downto 0); EEWrData : out std_logic_vector(7 downto 0); EERdData : in std_logic_vector(7 downto 0); EEWr : out std_logic; -- CPU reset jtag_rst : out std_logic ); end JTAGOCDPrgTop; architecture RTL of JTAGOCDPrgTop is -- From TCK clock domain to cp2 clock domain with resynchronization signal ChipEraseStart_TCK : std_logic; signal ChipEraseStart_cp2 : std_logic; signal ProgEnable_TCK : std_logic; signal ProgEnable_cp2 : std_logic; signal FlWrMStart_TCK : std_logic; signal FlWrMStart_cp2 : std_logic; signal FlWrSStart_TCK : std_logic; signal FlWrSStart_cp2 : std_logic; signal FlRdMStart_TCK : std_logic; signal FlRdMStart_cp2 : std_logic; signal FlRdSStart_TCK : std_logic; signal FlRdSStart_cp2 : std_logic; signal EEWrStart_TCK : std_logic; signal EEWrStart_cp2 : std_logic; signal EERdStart_TCK : std_logic; signal EERdStart_cp2 : std_logic; signal TAPCtrlTLR_TCK : std_logic; signal TAPCtrlTLR_cp2 : std_logic; -- From TCK clock domain to cp2 clock domain without resynchronization signal FlEEPrgAdr_TCK : std_logic_vector(15 downto 0); -- Flash/EEPROM Address signal FlEEPrgWrData_TCK : std_logic_vector(15 downto 0); -- Flash/EEPROM Data for write -- From cp2 clock domain to TCK clock domain with resynchronization signal ChipEraseDone_cp2 : std_logic; signal ChipEraseDone_TCK : std_logic; -- From cp2 clock domain to TCK clock domain without resynchronization signal FlPrgRdData_cp2 : std_logic_vector(15 downto 0); -- Flash Read Data signal EEPrgRdData_cp2 : std_logic_vector(7 downto 0); -- EEPROM Read Data begin OCDProgTCK_Inst:component OCDProgTCK port map( -- JTAG related inputs/outputs TRSTn => TRSTn, TMS => TMS, TCK => TCK, TDI => TDI, TDO => TDO, TDO_OE => TDO_OE, -- From/To cp2 clock domain("Flash" programmer) FlEEPrgAdr => FlEEPrgAdr_TCK, FlPrgRdData => FlPrgRdData_cp2, EEPrgRdData => EEPrgRdData_cp2, FlEEPrgWrData => FlEEPrgWrData_TCK, ChipEraseStart => ChipEraseStart_TCK, ChipEraseDone => ChipEraseDone_TCK, ProgEnable => ProgEnable_TCK, FlWrMStart => FlWrMStart_TCK, FlWrSStart => FlWrSStart_TCK, FlRdMStart => FlRdMStart_TCK, FlRdSStart => FlRdSStart_TCK, EEWrStart => EEWrStart_TCK, EERdStart => EERdStart_TCK, TAPCtrlTLR => TAPCtrlTLR_TCK, -- CPU reset jtag_rst => jtag_rst ); OCDProgcp2_Inst:component OCDProgcp2 port map( -- AVR Control ireset => ireset, cp2 => cp2, -- From/To TCK clock domain("Flash" programmer) FlEEPrgAdr => FlEEPrgAdr_TCK, FlPrgRdData => FlPrgRdData_cp2, EEPrgRdData => EEPrgRdData_cp2, FlEEPrgWrData => FlEEPrgWrData_TCK, ChipEraseStart => ChipEraseStart_cp2, ChipEraseDone => ChipEraseDone_cp2, ProgEnable => ProgEnable_cp2, FlWrMStart => FlWrMStart_cp2, FlWrSStart => FlWrSStart_cp2, FlRdMStart => FlRdMStart_cp2, FlRdSStart => FlRdSStart_cp2, EEWrStart => EEWrStart_cp2, EERdStart => EERdStart_cp2, TAPCtrlTLR => TAPCtrlTLR_cp2, -- From the core PC => PC, -- To the PM("Flash") pm_adr => pm_adr, pm_h_we => pm_h_we, pm_l_we => pm_l_we, pm_dout => pm_dout, pm_din => pm_din, -- To the "EEPROM" EEPrgSel => EEPrgSel, EEAdr => EEAdr, EEWrData => EEWrData, EERdData => EERdData, EEWr => EEWr ); -- Resynchronizers (TCK to cp2) ChipEraseStart_Resync_Inst:component Resync1b_cp2 port map( cp2 => cp2, DIn => ChipEraseStart_TCK, DOut => ChipEraseStart_cp2 ); ProgEnable_Resync_Inst:component Resync1b_cp2 port map( cp2 => cp2, DIn => ProgEnable_TCK, DOut => ProgEnable_cp2 ); FlWrMStart_Resync_Inst:component Resync1b_cp2 port map( cp2 => cp2, DIn => FlWrMStart_TCK, DOut => FlWrMStart_cp2 ); FlWrSStart_Resync_Inst:component Resync1b_cp2 port map( cp2 => cp2, DIn => FlWrSStart_TCK, DOut => FlWrSStart_cp2 ); FlRdMStart_Resync_Inst:component Resync1b_cp2 port map( cp2 => cp2, DIn => FlRdMStart_TCK, DOut => FlRdMStart_cp2 ); FlRdSStart_Resync_Inst:component Resync1b_cp2 port map( cp2 => cp2, DIn => FlRdSStart_TCK, DOut => FlRdSStart_cp2 ); EEWrStart_Resync_Inst:component Resync1b_cp2 port map( cp2 => cp2, DIn => EEWrStart_TCK, DOut => EEWrStart_cp2 ); EERdStart_Resync_Inst:component Resync1b_cp2 port map( cp2 => cp2, DIn => EERdStart_TCK, DOut => EERdStart_cp2 ); TAPCtrlTLR_Resync_Inst:component Resync1b_cp2 port map( cp2 => cp2, DIn => TAPCtrlTLR_TCK, DOut => TAPCtrlTLR_cp2 ); -- Resynchronizers (cp2 to TCK) ChipEraseDone_Resync_Inst:component Resync1b_TCK port map( TCK => TCK, DIn => ChipEraseDone_cp2, DOut => ChipEraseDone_TCK ); end RTL;
apache-2.0
a9dc2ea2f47bb461a0d2f9b94a3d0fcf
0.452407
3.937146
false
false
false
false
hoglet67/AtomFpga
src/common/AlanD/R65Cx2.vhd
2
61,147
-- ----------------------------------------------------------------------- -- -- This is a table driven 65Cx2 core by A.Daly -- This is a derivative of the excellent FPGA64 core see below -- -- ----------------------------------------------------------------------- -- Copyright 2005-2008 by Peter Wendrich ([email protected]) -- http://www.syntiac.com/fpga64.html -- ----------------------------------------------------------------------- library IEEE; use ieee.std_logic_1164.ALL; use ieee.numeric_std.ALL; entity R65C02 is port ( reset : in std_logic; clk : in std_logic; enable : in std_logic; nmi_n : in std_logic; irq_n : in std_logic; di : in unsigned(7 downto 0); do : out unsigned(7 downto 0); addr : out unsigned(15 downto 0); nwe : out std_logic; sync : out std_logic; sync_irq : out std_logic; -- 6502 registers (MSB) PC, SP, P, Y, X, A (LSB) Regs : out std_logic_vector(63 downto 0) ); end R65C02; -- Store Zp (3) => fetch, cycle2, cycleEnd -- Store Zp,x (4) => fetch, cycle2, preWrite, cycleEnd -- Read Zp,x (4) => fetch, cycle2, cycleRead, cycleRead2 -- Rmw Zp,x (6) => fetch, cycle2, cycleRead, cycleRead2, cycleRmw, cycleEnd -- Store Abs (4) => fetch, cycle2, cycle3, cycleEnd -- Store Abs,x (5) => fetch, cycle2, cycle3, preWrite, cycleEnd -- Rts (6) => fetch, cycle2, cycle3, cycleRead, cycleJump, cycleIncrEnd -- Rti (6) => fetch, cycle2, stack1, stack2, stack3, cycleJump -- Jsr (6) => fetch, cycle2, .. cycle5, cycle6, cycleJump -- Jmp abs (-) => fetch, cycle2, .., cycleJump -- Jmp (ind) (-) => fetch, cycle2, .., cycleJump -- Brk / irq (6) => fetch, cycle2, stack2, stack3, stack4 -- ----------------------------------------------------------------------- architecture Behavioral of R65C02 is -- signal counter : unsigned(27 downto 0); -- signal mask_irq : std_logic; -- signal mask_enable : std_logic; -- Statemachine type cpuCycles is ( opcodeFetch, -- New opcode is read and registers updated cycle2, cycle3, cyclePreIndirect, cycleIndirect, cycleBranchTaken, cycleBranchPage, cyclePreRead, -- Cycle before read while doing zeropage indexed addressing. cycleRead, -- Read cycle cycleRead2, -- Second read cycle after page-boundary crossing. cycleRmw, -- Calculate ALU output for read-modify-write instr. cyclePreWrite, -- Cycle before write when doing indexed addressing. cycleWrite, -- Write cycle for zeropage or absolute addressing. cycleStack1, cycleStack2, cycleStack3, cycleStack4, cycleJump, -- Last cycle of Jsr, Jmp. Next fetch address is target addr. cycleEnd ); signal theCpuCycle : cpuCycles; signal nextCpuCycle : cpuCycles; signal updateRegisters : boolean; signal processIrq : std_logic; signal nmiReg: std_logic; signal nmiEdge: std_logic; signal irqReg : std_logic; -- Delay IRQ input with one clock cycle. signal soReg : std_logic; -- SO pin edge detection -- Opcode decoding constant opcUpdateA : integer := 0; constant opcUpdateX : integer := 1; constant opcUpdateY : integer := 2; constant opcUpdateS : integer := 3; constant opcUpdateN : integer := 4; constant opcUpdateV : integer := 5; constant opcUpdateD : integer := 6; constant opcUpdateI : integer := 7; constant opcUpdateZ : integer := 8; constant opcUpdateC : integer := 9; constant opcSecondByte : integer := 10; constant opcAbsolute : integer := 11; constant opcZeroPage : integer := 12; constant opcIndirect : integer := 13; constant opcStackAddr : integer := 14; -- Push/Pop address constant opcStackData : integer := 15; -- Push/Pop status/data constant opcJump : integer := 16; constant opcBranch : integer := 17; constant indexX : integer := 18; constant indexY : integer := 19; constant opcStackUp : integer := 20; constant opcWrite : integer := 21; constant opcRmw : integer := 22; constant opcIncrAfter : integer := 23; -- Insert extra cycle to increment PC (RTS) constant opcRti : integer := 24; constant opcIRQ : integer := 25; constant opcInA : integer := 26; constant opcInBrk : integer := 27; constant opcInX : integer := 28; constant opcInY : integer := 29; constant opcInS : integer := 30; constant opcInT : integer := 31; constant opcInH : integer := 32; constant opcInClear : integer := 33; constant aluMode1From : integer := 34; -- constant aluMode1To : integer := 37; constant aluMode2From : integer := 38; -- constant aluMode2To : integer := 40; -- constant opcInCmp : integer := 41; constant opcInCpx : integer := 42; constant opcInCpy : integer := 43; subtype addrDef is unsigned(0 to 15); -- -- is Interrupt -----------------+ -- instruction is RTI ----------------+| -- PC++ on last cycle (RTS) ---------------+|| -- RMW --------------+||| -- Write -------------+|||| -- Pop/Stack up -------------+||||| -- Branch ---------+ |||||| -- Jump ----------+| |||||| -- Push or Pop data -------+|| |||||| -- Push or Pop addr ------+||| |||||| -- Indirect -----+|||| |||||| -- ZeroPage ----+||||| |||||| -- Absolute ---+|||||| |||||| -- PC++ on cycle2 --+||||||| |||||| -- |AZI||JBXY|WM||| constant immediate : addrDef := "1000000000000000"; constant implied : addrDef := "0000000000000000"; -- Zero page constant readZp : addrDef := "1010000000000000"; constant writeZp : addrDef := "1010000000010000"; constant rmwZp : addrDef := "1010000000001000"; -- Zero page indexed constant readZpX : addrDef := "1010000010000000"; constant writeZpX : addrDef := "1010000010010000"; constant rmwZpX : addrDef := "1010000010001000"; constant readZpY : addrDef := "1010000001000000"; constant writeZpY : addrDef := "1010000001010000"; constant rmwZpY : addrDef := "1010000001001000"; -- Zero page indirect constant readIndX : addrDef := "1001000010000000"; constant writeIndX : addrDef := "1001000010010000"; constant rmwIndX : addrDef := "1001000010001000"; constant readIndY : addrDef := "1001000001000000"; constant writeIndY : addrDef := "1001000001010000"; constant rmwIndY : addrDef := "1001000001001000"; constant rmwInd : addrDef := "1001000000001000"; constant readInd : addrDef := "1001000000000000"; constant writeInd : addrDef := "1001000000010000"; -- |AZI||JBXY|WM|| -- Absolute constant readAbs : addrDef := "1100000000000000"; constant writeAbs : addrDef := "1100000000010000"; constant rmwAbs : addrDef := "1100000000001000"; constant readAbsX : addrDef := "1100000010000000"; constant writeAbsX : addrDef := "1100000010010000"; constant rmwAbsX : addrDef := "1100000010001000"; constant readAbsY : addrDef := "1100000001000000"; constant writeAbsY : addrDef := "1100000001010000"; constant rmwAbsY : addrDef := "1100000001001000"; -- PHA PHP constant push : addrDef := "0000010000000000"; -- PLA PLP constant pop : addrDef := "0000010000100000"; -- Jumps constant jsr : addrDef := "1000101000000000"; constant jumpAbs : addrDef := "1000001000000000"; constant jumpInd : addrDef := "1100001000000000"; constant jumpIndX : addrDef := "1100001010000000"; constant relative : addrDef := "1000000100000000"; -- Specials constant rts : addrDef := "0000101000100100"; constant rti : addrDef := "0000111000100010"; constant brk : addrDef := "1000111000000001"; -- constant irq : addrDef := "0000111000000001"; -- constant : unsigned(0 to 0) := "0"; constant xxxxxxxx : addrDef := "----------0---00"; -- A = accu -- X = index X -- Y = index Y -- S = Stack pointer -- H = indexH -- -- AEXYSTHc constant aluInA : unsigned(0 to 7) := "10000000"; constant aluInBrk : unsigned(0 to 7) := "01000000"; constant aluInX : unsigned(0 to 7) := "00100000"; constant aluInY : unsigned(0 to 7) := "00010000"; constant aluInS : unsigned(0 to 7) := "00001000"; constant aluInT : unsigned(0 to 7) := "00000100"; constant aluInClr : unsigned(0 to 7) := "00000001"; constant aluInSet : unsigned(0 to 7) := "00000000"; constant aluInXXX : unsigned(0 to 7) := "--------"; -- Most of the aluModes are just like the opcodes. -- aluModeInp -> input is output. calculate N and Z -- aluModeCmp -> Compare for CMP, CPX, CPY -- aluModeFlg -> input to flags needed for PLP, RTI and CLC, SEC, CLV -- aluModeInc -> for INC but also INX, INY -- aluModeDec -> for DEC but also DEX, DEY subtype aluMode1 is unsigned(0 to 3); subtype aluMode2 is unsigned(0 to 2); subtype aluMode is unsigned(0 to 9); -- Logic/Shift ALU constant aluModeInp : aluMode1 := "0000"; constant aluModeP : aluMode1 := "0001"; constant aluModeInc : aluMode1 := "0010"; constant aluModeDec : aluMode1 := "0011"; constant aluModeFlg : aluMode1 := "0100"; constant aluModeBit : aluMode1 := "0101"; -- 0110 -- 0111 constant aluModeLsr : aluMode1 := "1000"; constant aluModeRor : aluMode1 := "1001"; constant aluModeAsl : aluMode1 := "1010"; constant aluModeRol : aluMode1 := "1011"; constant aluModeTSB : aluMode1 := "1100"; constant aluModeTRB : aluMode1 := "1101"; -- 1110 -- 1111; -- Arithmetic ALU constant aluModePss : aluMode2 := "000"; constant aluModeCmp : aluMode2 := "001"; constant aluModeAdc : aluMode2 := "010"; constant aluModeSbc : aluMode2 := "011"; constant aluModeAnd : aluMode2 := "100"; constant aluModeOra : aluMode2 := "101"; constant aluModeEor : aluMode2 := "110"; constant aluModeNoF : aluMode2 := "111"; --aluModeBRK --constant aluBrk : aluMode := aluModeBRK & aluModePss & "---"; --constant aluFix : aluMode := aluModeInp & aluModeNoF & "---"; constant aluInp : aluMode := aluModeInp & aluModePss & "---"; constant aluP : aluMode := aluModeP & aluModePss & "---"; constant aluInc : aluMode := aluModeInc & aluModePss & "---"; constant aluDec : aluMode := aluModeDec & aluModePss & "---"; constant aluFlg : aluMode := aluModeFlg & aluModePss & "---"; constant aluBit : aluMode := aluModeBit & aluModeAnd & "---"; constant aluRor : aluMode := aluModeRor & aluModePss & "---"; constant aluLsr : aluMode := aluModeLsr & aluModePss & "---"; constant aluRol : aluMode := aluModeRol & aluModePss & "---"; constant aluAsl : aluMode := aluModeAsl & aluModePss & "---"; constant aluTSB : aluMode := aluModeTSB & aluModePss & "---"; constant aluTRB : aluMode := aluModeTRB & aluModePss & "---"; constant aluCmp : aluMode := aluModeInp & aluModeCmp & "100"; constant aluCpx : aluMode := aluModeInp & aluModeCmp & "010"; constant aluCpy : aluMode := aluModeInp & aluModeCmp & "001"; constant aluAdc : aluMode := aluModeInp & aluModeAdc & "---"; constant aluSbc : aluMode := aluModeInp & aluModeSbc & "---"; constant aluAnd : aluMode := aluModeInp & aluModeAnd & "---"; constant aluOra : aluMode := aluModeInp & aluModeOra & "---"; constant aluEor : aluMode := aluModeInp & aluModeEor & "---"; constant aluXXX : aluMode := (others => '-'); -- Stack operations. Push/Pop/None constant stackInc : unsigned(0 to 0) := "0"; constant stackDec : unsigned(0 to 0) := "1"; constant stackXXX : unsigned(0 to 0) := "-"; subtype decodedBitsDef is unsigned(0 to 43); type opcodeInfoTableDef is array(0 to 255) of decodedBitsDef; constant opcodeInfoTable : opcodeInfoTableDef := ( -- +------- Update register A -- |+------ Update register X -- ||+----- Update register Y -- |||+---- Update register S -- |||| +-- Update Flags -- |||| | -- |||| _|__ -- |||| / \ -- AXYS NVDIZC addressing aluInput aluMode -- AXYS NVDIZC addressing aluInput aluMode "0000" & "001100" & brk & aluInBrk & aluP, -- 00 BRK "1000" & "100010" & readIndX & aluInT & aluOra, -- 01 ORA (zp,x) "0000" & "000000" & immediate & aluInXXX & aluXXX, -- 02 NOP ------- 65C02 "0000" & "000000" & implied & aluInXXX & aluXXX, -- 03 NOP ------- 65C02 "0000" & "000010" & rmwZp & aluInT & aluTSB, -- 04 TSB zp ----------- 65C02 "1000" & "100010" & readZp & aluInT & aluOra, -- 05 ORA zp "0000" & "100011" & rmwZp & aluInT & aluAsl, -- 06 ASL zp "0000" & "000000" & implied & aluInXXX & aluXXX, -- 07 NOP ------- 65C02 "0000" & "000000" & push & aluInXXX & aluP, -- 08 PHP "1000" & "100010" & immediate & aluInT & aluOra, -- 09 ORA imm "1000" & "100011" & implied & aluInA & aluAsl, -- 0A ASL accu "0000" & "000000" & implied & aluInXXX & aluXXX, -- 0B NOP ------- 65C02 "0000" & "000010" & rmwAbs & aluInT & aluTSB, -- 0C TSB abs ---------- 65C02 "1000" & "100010" & readAbs & aluInT & aluOra, -- 0D ORA abs "0000" & "100011" & rmwAbs & aluInT & aluAsl, -- 0E ASL abs "0000" & "000000" & implied & aluInXXX & aluXXX, -- 0F NOP ------- 65C02 "0000" & "000000" & relative & aluInXXX & aluXXX, -- 10 BPL "1000" & "100010" & readIndY & aluInT & aluOra, -- 11 ORA (zp),y "1000" & "100010" & readInd & aluInT & aluOra, -- 12 ORA (zp) --------- 65C02 "0000" & "000000" & implied & aluInXXX & aluXXX, -- 13 NOP ------- 65C02 "0000" & "000010" & rmwZp & aluInT & aluTRB, -- 14 TRB zp ~---------- 65C02 "1000" & "100010" & readZpX & aluInT & aluOra, -- 15 ORA zp,x "0000" & "100011" & rmwZpX & aluInT & aluAsl, -- 16 ASL zp,x "0000" & "000000" & implied & aluInXXX & aluXXX, -- 17 NOP ------- 65C02 "0000" & "000001" & implied & aluInClr & aluFlg, -- 18 CLC "1000" & "100010" & readAbsY & aluInT & aluOra, -- 19 ORA abs,y "1000" & "100010" & implied & aluInA & aluInc, -- 1A INC accu --------- 65C02 "0000" & "000000" & implied & aluInXXX & aluXXX, -- 1B NOP ------- 65C02 "0000" & "000010" & rmwAbs & aluInT & aluTRB, -- 1C TRB abs ~----- --- 65C02 "1000" & "100010" & readAbsX & aluInT & aluOra, -- 1D ORA abs,x "0000" & "100011" & rmwAbsX & aluInT & aluAsl, -- 1E ASL abs,x "0000" & "000000" & implied & aluInXXX & aluXXX, -- 1F NOP ------- 65C02 -- AXYS NVDIZC addressing aluInput aluMode "0000" & "000000" & jsr & aluInXXX & aluXXX, -- 20 JSR "1000" & "100010" & readIndX & aluInT & aluAnd, -- 21 AND (zp,x) "0000" & "000000" & immediate & aluInXXX & aluXXX, -- 22 NOP ------- 65C02 "0000" & "000000" & implied & aluInXXX & aluXXX, -- 23 NOP ------- 65C02 "0000" & "110010" & readZp & aluInT & aluBit, -- 24 BIT zp "1000" & "100010" & readZp & aluInT & aluAnd, -- 25 AND zp "0000" & "100011" & rmwZp & aluInT & aluRol, -- 26 ROL zp "0000" & "000000" & implied & aluInXXX & aluXXX, -- 27 NOP ------- 65C02 "0000" & "111111" & pop & aluInT & aluFlg, -- 28 PLP "1000" & "100010" & immediate & aluInT & aluAnd, -- 29 AND imm "1000" & "100011" & implied & aluInA & aluRol, -- 2A ROL accu "0000" & "000000" & implied & aluInXXX & aluXXX, -- 2B NOP ------- 65C02 "0000" & "110010" & readAbs & aluInT & aluBit, -- 2C BIT abs "1000" & "100010" & readAbs & aluInT & aluAnd, -- 2D AND abs "0000" & "100011" & rmwAbs & aluInT & aluRol, -- 2E ROL abs "0000" & "000000" & implied & aluInXXX & aluXXX, -- 2F NOP ------- 65C02 "0000" & "000000" & relative & aluInXXX & aluXXX, -- 30 BMI "1000" & "100010" & readIndY & aluInT & aluAnd, -- 31 AND (zp),y "1000" & "100010" & readInd & aluInT & aluAnd, -- 32 AND (zp) -------- 65C02 "0000" & "000000" & implied & aluInXXX & aluXXX, -- 33 NOP ------- 65C02 "0000" & "110010" & readZpX & aluInT & aluBit, -- 34 BIT zp,x -------- 65C02 "1000" & "100010" & readZpX & aluInT & aluAnd, -- 35 AND zp,x "0000" & "100011" & rmwZpX & aluInT & aluRol, -- 36 ROL zp,x "0000" & "000000" & implied & aluInXXX & aluXXX, -- 37 NOP ------- 65C02 "0000" & "000001" & implied & aluInSet & aluFlg, -- 38 SEC "1000" & "100010" & readAbsY & aluInT & aluAnd, -- 39 AND abs,y "1000" & "100010" & implied & aluInA & aluDec, -- 3A DEC accu -------- 65C12 "0000" & "000000" & implied & aluInXXX & aluXXX, -- 3B NOP ------- 65C02 "0000" & "110010" & readAbsX & aluInT & aluBit, -- 3C BIT abs,x ------- 65C02 "1000" & "100010" & readAbsX & aluInT & aluAnd, -- 3D AND abs,x "0000" & "100011" & rmwAbsX & aluInT & aluRol, -- 3E ROL abs,x "0000" & "000000" & implied & aluInXXX & aluXXX, -- 3F NOP ------- 65C02 -- AXYS NVDIZC addressing aluInput aluMode "0000" & "111111" & rti & aluInT & aluFlg, -- 40 RTI "1000" & "100010" & readIndX & aluInT & aluEor, -- 41 EOR (zp,x) "0000" & "000000" & immediate & aluInXXX & aluXXX, -- 42 NOP ------- 65C02 "0000" & "000000" & implied & aluInXXX & aluXXX, -- 43 NOP ------- 65C02 "0000" & "000000" & immediate & aluInXXX & aluXXX, -- 44 NOP ------- 65C02 "1000" & "100010" & readZp & aluInT & aluEor, -- 45 EOR zp "0000" & "100011" & rmwZp & aluInT & aluLsr, -- 46 LSR zp "0000" & "000000" & implied & aluInXXX & aluXXX, -- 47 NOP ------- 65C02 "0000" & "000000" & push & aluInA & aluInp, -- 48 PHA "1000" & "100010" & immediate & aluInT & aluEor, -- 49 EOR imm "1000" & "100011" & implied & aluInA & aluLsr, -- 4A LSR accu -------- 65C02 "0000" & "000000" & implied & aluInXXX & aluXXX, -- 4B NOP ------- 65C02 "0000" & "000000" & jumpAbs & aluInXXX & aluXXX, -- 4C JMP abs "1000" & "100010" & readAbs & aluInT & aluEor, -- 4D EOR abs "0000" & "100011" & rmwAbs & aluInT & aluLsr, -- 4E LSR abs "0000" & "000000" & implied & aluInXXX & aluXXX, -- 4F NOP ------- 65C02 "0000" & "000000" & relative & aluInXXX & aluXXX, -- 50 BVC "1000" & "100010" & readIndY & aluInT & aluEor, -- 51 EOR (zp),y "1000" & "100010" & readInd & aluInT & aluEor, -- 52 EOR (zp) -------- 65C02 "0000" & "000000" & implied & aluInXXX & aluXXX, -- 53 NOP ------- 65C02 "0000" & "000000" & immediate & aluInXXX & aluXXX, -- 54 NOP ------- 65C02 "1000" & "100010" & readZpX & aluInT & aluEor, -- 55 EOR zp,x "0000" & "100011" & rmwZpX & aluInT & aluLsr, -- 56 LSR zp,x "0000" & "000000" & implied & aluInXXX & aluXXX, -- 57 NOP ------- 65C02 "0000" & "000100" & implied & aluInClr & aluXXX, -- 58 CLI "1000" & "100010" & readAbsY & aluInT & aluEor, -- 59 EOR abs,y "0000" & "000000" & push & aluInY & aluInp, -- 5A PHY ------------- 65C02 "0000" & "000000" & implied & aluInXXX & aluXXX, -- 5B NOP ------- 65C02 "0000" & "000000" & readAbs & aluInXXX & aluXXX, -- 5C NOP ------- 65C02 "1000" & "100010" & readAbsX & aluInT & aluEor, -- 5D EOR abs,x "0000" & "100011" & rmwAbsX & aluInT & aluLsr, -- 5E LSR abs,x "0000" & "000000" & implied & aluInXXX & aluXXX, -- 5F NOP ------- 65C02 -- AXYS NVDIZC addressing aluInput aluMode "0000" & "000000" & rts & aluInXXX & aluXXX, -- 60 RTS "1000" & "110011" & readIndX & aluInT & aluAdc, -- 61 ADC (zp,x) "0000" & "000000" & immediate & aluInXXX & aluXXX, -- 62 NOP ------- 65C02 "0000" & "000000" & implied & aluInXXX & aluXXX, -- 63 NOP ------- 65C02 "0000" & "000000" & writeZp & aluInClr & aluInp, -- 64 STZ zp ---------- 65C02 "1000" & "110011" & readZp & aluInT & aluAdc, -- 65 ADC zp "0000" & "100011" & rmwZp & aluInT & aluRor, -- 66 ROR zp "0000" & "000000" & implied & aluInXXX & aluXXX, -- 67 NOP ------- 65C02 "1000" & "100010" & pop & aluInT & aluInp, -- 68 PLA "1000" & "110011" & immediate & aluInT & aluAdc, -- 69 ADC imm "1000" & "100011" & implied & aluInA & aluRor, -- 6A ROR accu "0000" & "000000" & implied & aluInXXX & aluXXX, -- 6B NOP ------ 65C02 "0000" & "000000" & jumpInd & aluInXXX & aluXXX, -- 6C JMP indirect "1000" & "110011" & readAbs & aluInT & aluAdc, -- 6D ADC abs "0000" & "100011" & rmwAbs & aluInT & aluRor, -- 6E ROR abs "0000" & "000000" & implied & aluInXXX & aluXXX, -- 6F NOP ------ 65C02 "0000" & "000000" & relative & aluInXXX & aluXXX, -- 70 BVS "1000" & "110011" & readIndY & aluInT & aluAdc, -- 71 ADC (zp),y "1000" & "110011" & readInd & aluInT & aluAdc, -- 72 ADC (zp) -------- 65C02 "0000" & "000000" & implied & aluInXXX & aluXXX, -- 73 NOP ------ 65C02 "0000" & "000000" & writeZpX & aluInClr & aluInp, -- 74 STZ zp,x -------- 65C02 "1000" & "110011" & readZpX & aluInT & aluAdc, -- 75 ADC zp,x "0000" & "100011" & rmwZpX & aluInT & aluRor, -- 76 ROR zp,x "0000" & "000000" & implied & aluInXXX & aluXXX, -- 77 NOP ----- 65C02 "0000" & "000100" & implied & aluInSet & aluXXX, -- 78 SEI "1000" & "110011" & readAbsY & aluInT & aluAdc, -- 79 ADC abs,y "0010" & "100010" & pop & aluInT & aluInp, -- 7A PLY ------------- 65C02 "0000" & "000000" & implied & aluInXXX & aluXXX, -- 7B NOP ----- 65C02 "0000" & "000000" & jumpIndX & aluInXXX & aluXXX, -- 7C JMP indirect,x -- 65C02 --"0000" & "000000" & jumpInd & aluInXXX & aluXXX, -- 6C JMP indirect "1000" & "110011" & readAbsX & aluInT & aluAdc, -- 7D ADC abs,x "0000" & "100011" & rmwAbsX & aluInT & aluRor, -- 7E ROR abs,x "0000" & "000000" & implied & aluInXXX & aluXXX, -- 7F NOP ----- 65C02 -- AXYS NVDIZC addressing aluInput aluMode "0000" & "000000" & relative & aluInXXX & aluXXX, -- 80 BRA ----------- 65C02 "0000" & "000000" & writeIndX & aluInA & aluInp, -- 81 STA (zp,x) "0000" & "000000" & immediate & aluInXXX & aluXXX, -- 82 NOP ----- 65C02 "0000" & "000000" & implied & aluInXXX & aluXXX, -- 83 NOP ----- 65C02 "0000" & "000000" & writeZp & aluInY & aluInp, -- 84 STY zp "0000" & "000000" & writeZp & aluInA & aluInp, -- 85 STA zp "0000" & "000000" & writeZp & aluInX & aluInp, -- 86 STX zp "0000" & "000000" & implied & aluInXXX & aluXXX, -- 87 NOP ----- 65C02 "0010" & "100010" & implied & aluInY & aluDec, -- 88 DEY "0000" & "000010" & immediate & aluInT & aluBit, -- 89 BIT imm ------- 65C02 "1000" & "100010" & implied & aluInX & aluInp, -- 8A TXA "0000" & "000000" & implied & aluInXXX & aluXXX, -- 8B NOP ----- 65C02 "0000" & "000000" & writeAbs & aluInY & aluInp, -- 8C STY abs ------- 65C02 "0000" & "000000" & writeAbs & aluInA & aluInp, -- 8D STA abs "0000" & "000000" & writeAbs & aluInX & aluInp, -- 8E STX abs "0000" & "000000" & implied & aluInXXX & aluXXX, -- 8F NOP ----- 65C02 "0000" & "000000" & relative & aluInXXX & aluXXX, -- 90 BCC "0000" & "000000" & writeIndY & aluInA & aluInp, -- 91 STA (zp),y "0000" & "000000" & writeInd & aluInA & aluInp, -- 92 STA (zp) ------ 65C02 "0000" & "000000" & implied & aluInXXX & aluXXX, -- 93 NOP ----- 65C02 "0000" & "000000" & writeZpX & aluInY & aluInp, -- 94 STY zp,x "0000" & "000000" & writeZpX & aluInA & aluInp, -- 95 STA zp,x "0000" & "000000" & writeZpY & aluInX & aluInp, -- 96 STX zp,y "0000" & "000000" & implied & aluInXXX & aluXXX, -- 97 NOP ----- 65C02 "1000" & "100010" & implied & aluInY & aluInp, -- 98 TYA "0000" & "000000" & writeAbsY & aluInA & aluInp, -- 99 STA abs,y "0001" & "000000" & implied & aluInX & aluInp, -- 9A TXS "0000" & "000000" & implied & aluInXXX & aluXXX, -- 9B NOP ----- 65C02 "0000" & "000000" & writeAbs & aluInClr & aluInp, -- 9C STZ Abs ------- 65C02 "0000" & "000000" & writeAbsX & aluInA & aluInp, -- 9D STA abs,x "0000" & "000000" & writeAbsX & aluInClr & aluInp, -- 9C STZ Abs,x ----- 65C02 "0000" & "000000" & implied & aluInXXX & aluXXX, -- 9F NOP ----- 65C02 -- AXYS NVDIZC addressing aluInput aluMode "0010" & "100010" & immediate & aluInT & aluInp, -- A0 LDY imm "1000" & "100010" & readIndX & aluInT & aluInp, -- A1 LDA (zp,x) "0100" & "100010" & immediate & aluInT & aluInp, -- A2 LDX imm "0000" & "000000" & implied & aluInXXX & aluXXX, -- A3 NOP ----- 65C02 "0010" & "100010" & readZp & aluInT & aluInp, -- A4 LDY zp "1000" & "100010" & readZp & aluInT & aluInp, -- A5 LDA zp "0100" & "100010" & readZp & aluInT & aluInp, -- A6 LDX zp "0000" & "000000" & implied & aluInXXX & aluXXX, -- A7 NOP ----- 65C02 "0010" & "100010" & implied & aluInA & aluInp, -- A8 TAY "1000" & "100010" & immediate & aluInT & aluInp, -- A9 LDA imm "0100" & "100010" & implied & aluInA & aluInp, -- AA TAX "0000" & "000000" & implied & aluInXXX & aluXXX, -- AB NOP ----- 65C02 "0010" & "100010" & readAbs & aluInT & aluInp, -- AC LDY abs "1000" & "100010" & readAbs & aluInT & aluInp, -- AD LDA abs "0100" & "100010" & readAbs & aluInT & aluInp, -- AE LDX abs "0000" & "000000" & implied & aluInXXX & aluXXX, -- AF NOP ----- 65C02 "0000" & "000000" & relative & aluInXXX & aluXXX, -- B0 BCS "1000" & "100010" & readIndY & aluInT & aluInp, -- B1 LDA (zp),y "1000" & "100010" & readInd & aluInT & aluInp, -- B2 LDA (zp) ------ 65C02 "0000" & "000000" & implied & aluInXXX & aluXXX, -- B3 NOP ----- 65C02 "0010" & "100010" & readZpX & aluInT & aluInp, -- B4 LDY zp,x "1000" & "100010" & readZpX & aluInT & aluInp, -- B5 LDA zp,x "0100" & "100010" & readZpY & aluInT & aluInp, -- B6 LDX zp,y "0000" & "000000" & implied & aluInXXX & aluXXX, -- B7 NOP ----- 65C02 "0000" & "010000" & implied & aluInClr & aluFlg, -- B8 CLV "1000" & "100010" & readAbsY & aluInT & aluInp, -- B9 LDA abs,y "0100" & "100010" & implied & aluInS & aluInp, -- BA TSX "0000" & "000000" & implied & aluInXXX & aluXXX, -- BB NOP ----- 65C02 "0010" & "100010" & readAbsX & aluInT & aluInp, -- BC LDY abs,x "1000" & "100010" & readAbsX & aluInT & aluInp, -- BD LDA abs,x "0100" & "100010" & readAbsY & aluInT & aluInp, -- BE LDX abs,y "0000" & "000000" & implied & aluInXXX & aluXXX, -- BF NOP ----- 65C02 -- AXYS NVDIZC addressing aluInput aluMode "0000" & "100011" & immediate & aluInT & aluCpy, -- C0 CPY imm "0000" & "100011" & readIndX & aluInT & aluCmp, -- C1 CMP (zp,x) "0000" & "000000" & immediate & aluInXXX & aluXXX, -- C2 NOP ----- 65C02 "0000" & "000000" & implied & aluInXXX & aluXXX, -- C3 NOP ----- 65C02 "0000" & "100011" & readZp & aluInT & aluCpy, -- C4 CPY zp "0000" & "100011" & readZp & aluInT & aluCmp, -- C5 CMP zp "0000" & "100010" & rmwZp & aluInT & aluDec, -- C6 DEC zp "0000" & "000000" & implied & aluInXXX & aluXXX, -- C7 NOP ----- 65C02 "0010" & "100010" & implied & aluInY & aluInc, -- C8 INY "0000" & "100011" & immediate & aluInT & aluCmp, -- C9 CMP imm "0100" & "100010" & implied & aluInX & aluDec, -- CA DEX "0000" & "000000" & implied & aluInXXX & aluXXX, -- CB NOP ----- 65C02 "0000" & "100011" & readAbs & aluInT & aluCpy, -- CC CPY abs "0000" & "100011" & readAbs & aluInT & aluCmp, -- CD CMP abs "0000" & "100010" & rmwAbs & aluInT & aluDec, -- CE DEC abs "0000" & "000000" & implied & aluInXXX & aluXXX, -- CF NOP ----- 65C02 "0000" & "000000" & relative & aluInXXX & aluXXX, -- D0 BNE "0000" & "100011" & readIndY & aluInT & aluCmp, -- D1 CMP (zp),y "0000" & "100011" & readInd & aluInT & aluCmp, -- D2 CMP (zp) ------ 65C02 "0000" & "000000" & implied & aluInXXX & aluXXX, -- D3 NOP ----- 65C02 "0000" & "000000" & immediate & aluInXXX & aluXXX, -- D4 NOP ----- 65C02 "0000" & "100011" & readZpX & aluInT & aluCmp, -- D5 CMP zp,x "0000" & "100010" & rmwZpX & aluInT & aluDec, -- D6 DEC zp,x "0000" & "000000" & implied & aluInXXX & aluXXX, -- D7 NOP ----- 65C02 "0000" & "001000" & implied & aluInClr & aluXXX, -- D8 CLD "0000" & "100011" & readAbsY & aluInT & aluCmp, -- D9 CMP abs,y "0000" & "000000" & push & aluInX & aluInp, -- DA PHX ----------- 65C02 "0000" & "000000" & implied & aluInXXX & aluXXX, -- DB NOP ----- 65C02 "0000" & "000000" & readAbs & aluInXXX & aluXXX, -- DC NOP ----- 65C02 "0000" & "100011" & readAbsX & aluInT & aluCmp, -- DD CMP abs,x "0000" & "100010" & rmwAbsX & aluInT & aluDec, -- DE DEC abs,x "0000" & "000000" & implied & aluInXXX & aluXXX, -- DF NOP ----- 65C02 -- AXYS NVDIZC addressing aluInput aluMode "0000" & "100011" & immediate & aluInT & aluCpx, -- E0 CPX imm "1000" & "110011" & readIndX & aluInT & aluSbc, -- E1 SBC (zp,x) "0000" & "000000" & immediate & aluInXXX & aluXXX, -- E2 NOP ----- 65C02 "0000" & "000000" & implied & aluInXXX & aluXXX, -- E3 NOP ----- 65C02 "0000" & "100011" & readZp & aluInT & aluCpx, -- E4 CPX zp "1000" & "110011" & readZp & aluInT & aluSbc, -- E5 SBC zp "0000" & "100010" & rmwZp & aluInT & aluInc, -- E6 INC zp "0000" & "000000" & implied & aluInXXX & aluXXX, -- E7 NOP ----- 65C02 "0100" & "100010" & implied & aluInX & aluInc, -- E8 INX "1000" & "110011" & immediate & aluInT & aluSbc, -- E9 SBC imm "0000" & "000000" & implied & aluInXXX & aluXXX, -- EA NOP "0000" & "000000" & implied & aluInXXX & aluXXX, -- EB NOP ----- 65C02 "0000" & "100011" & readAbs & aluInT & aluCpx, -- EC CPX abs "1000" & "110011" & readAbs & aluInT & aluSbc, -- ED SBC abs "0000" & "100010" & rmwAbs & aluInT & aluInc, -- EE INC abs "0000" & "000000" & implied & aluInXXX & aluXXX, -- EF NOP ----- 65C02 "0000" & "000000" & relative & aluInXXX & aluXXX, -- F0 BEQ "1000" & "110011" & readIndY & aluInT & aluSbc, -- F1 SBC (zp),y "1000" & "110011" & readInd & aluInT & aluSbc, -- F2 SBC (zp) ------ 65C02 "0000" & "000000" & implied & aluInXXX & aluXXX, -- F3 NOP ----- 65C02 "0000" & "000000" & immediate & aluInXXX & aluXXX, -- F4 NOP ----- 65C02 "1000" & "110011" & readZpX & aluInT & aluSbc, -- F5 SBC zp,x "0000" & "100010" & rmwZpX & aluInT & aluInc, -- F6 INC zp,x "0000" & "000000" & implied & aluInXXX & aluXXX, -- F7 NOP ---- 65C02 "0000" & "001000" & implied & aluInSet & aluXXX, -- F8 SED "1000" & "110011" & readAbsY & aluInT & aluSbc, -- F9 SBC abs,y "0100" & "100010" & pop & aluInT & aluInp, -- FA PLX ----------- 65C02 "0000" & "000000" & implied & aluInXXX & aluXXX, -- FB NOP ----- 65C02 "0000" & "000000" & readAbs & aluInXXX & aluXXX, -- FC NOP ----- 65C02 "1000" & "110011" & readAbsX & aluInT & aluSbc, -- FD SBC abs,x "0000" & "100010" & rmwAbsX & aluInT & aluInc, -- FE INC abs,x "0000" & "000000" & implied & aluInXXX & aluXXX -- FF NOP ----- 65C02 ); signal opcInfo : decodedBitsDef; signal nextOpcInfo : decodedBitsDef; -- Next opcode (decoded) signal nextOpcInfoReg : decodedBitsDef; -- Next opcode (decoded) pipelined signal theOpcode : unsigned(7 downto 0); signal nextOpcode : unsigned(7 downto 0); -- Program counter signal PC : unsigned(15 downto 0); -- Program counter -- Address generation type nextAddrDef is ( nextAddrHold, nextAddrIncr, nextAddrIncrL, -- Increment low bits only (zeropage accesses) nextAddrIncrH, -- Increment high bits only (page-boundary) nextAddrDecrH, -- Decrement high bits (branch backwards) nextAddrPc, nextAddrIrq, nextAddrReset, nextAddrAbs, nextAddrAbsIndexed, nextAddrZeroPage, nextAddrZPIndexed, nextAddrStack, nextAddrRelative ); signal nextAddr : nextAddrDef; signal myAddr : unsigned(15 downto 0); signal myAddrIncr : unsigned(15 downto 0); signal myAddrIncrH : unsigned(7 downto 0); signal myAddrDecrH : unsigned(7 downto 0); signal theWe : std_logic; signal irqActive : std_logic; -- Output register signal doReg : unsigned(7 downto 0); -- Buffer register signal T : unsigned(7 downto 0); -- General registers signal A: unsigned(7 downto 0); -- Accumulator signal X: unsigned(7 downto 0); -- Index X signal Y: unsigned(7 downto 0); -- Index Y signal S: unsigned(7 downto 0); -- stack pointer -- Status register signal C: std_logic; -- Carry signal Z: std_logic; -- Zero flag signal I: std_logic; -- Interrupt flag signal D: std_logic; -- Decimal mode signal B: std_logic; -- Break software interrupt signal R: std_logic; -- always 1 signal V: std_logic; -- Overflow signal N: std_logic; -- Negative -- ALU -- ALU input signal aluInput : unsigned(7 downto 0); signal aluCmpInput : unsigned(7 downto 0); -- ALU output signal aluRegisterOut : unsigned(7 downto 0); signal aluRmwOut : unsigned(7 downto 0); signal aluC : std_logic; signal aluZ : std_logic; signal aluV : std_logic; signal aluN : std_logic; -- Indexing signal indexOut : unsigned(8 downto 0); signal realbrk : std_logic; begin processAluInput: process(clk, opcInfo, A, X, Y, T, S) variable temp : unsigned(7 downto 0); begin temp := (others => '1'); if opcInfo(opcInA) = '1' then temp := temp and A; end if; if opcInfo(opcInX) = '1' then temp := temp and X; end if; if opcInfo(opcInY) = '1' then temp := temp and Y; end if; if opcInfo(opcInS) = '1' then temp := temp and S; end if; if opcInfo(opcInT) = '1' then temp := temp and T; end if; if opcInfo(opcInBrk) = '1' then temp := temp and "11100111"; -- also DMB clear D (bit 3) end if; if opcInfo(opcInClear) = '1' then temp := (others => '0'); end if; aluInput <= temp; end process; processCmpInput: process(clk, opcInfo, A, X, Y) variable temp : unsigned(7 downto 0); begin temp := (others => '1'); if opcInfo(opcInCmp) = '1' then temp := temp and A; end if; if opcInfo(opcInCpx) = '1' then temp := temp and X; end if; if opcInfo(opcInCpy) = '1' then temp := temp and Y; end if; aluCmpInput <= temp; end process; -- ALU consists of two parts -- Read-Modify-Write or index instructions: INC/DEC/ASL/LSR/ROR/ROL -- Accumulator instructions: ADC, SBC, EOR, AND, EOR, ORA -- Some instructions are both RMW and accumulator so for most -- instructions the rmw results are routed through accu alu too. -- The B flag ------------ --No actual "B" flag exists inside the 6502's processor status register. The B --flag only exists in the status flag byte pushed to the stack. Naturally, --when the flags are restored (via PLP or RTI), the B bit is discarded. -- --Depending on the means, the B status flag will be pushed to the stack as --either 0 or 1. -- --software instructions BRK & PHP will push the B flag as being 1. --hardware interrupts IRQ & NMI will push the B flag as being 0. processAlu: process(clk, opcInfo, aluInput, aluCmpInput, A, T, irqActive, N, V, D, I, Z, C) variable lowBits: unsigned(5 downto 0); variable nineBits: unsigned(8 downto 0); variable rmwBits: unsigned(8 downto 0); variable tsxBits: unsigned(8 downto 0); variable varC : std_logic; variable varZ : std_logic; variable varV : std_logic; variable varN : std_logic; begin lowBits := (others => '-'); nineBits := (others => '-'); rmwBits := (others => '-'); tsxBits := (others => '-'); R <= '1'; -- Shift unit case opcInfo(aluMode1From to aluMode1To) is when aluModeInp => rmwBits := C & aluInput; when aluModeP => rmwBits := C & N & V & R & (not irqActive) & D & I & Z & C; -- irqActive when aluModeInc => rmwBits := C & (aluInput + 1); when aluModeDec => rmwBits := C & (aluInput - 1); when aluModeAsl => rmwBits := aluInput & "0"; when aluModeTSB => rmwBits := "0" & (aluInput(7 downto 0) or A); -- added by alan for 65c02 tsxBits := "0" & (aluInput(7 downto 0) and A); when aluModeTRB => rmwBits := "0" & (aluInput(7 downto 0) and (not A)); -- added by alan for 65c02 tsxBits := "0" & (aluInput(7 downto 0) and A); when aluModeFlg => rmwBits := aluInput(0) & aluInput; when aluModeLsr => rmwBits := aluInput(0) & "0" & aluInput(7 downto 1); when aluModeRol => rmwBits := aluInput & C; when aluModeRoR => rmwBits := aluInput(0) & C & aluInput(7 downto 1); when others => rmwBits := C & aluInput; end case; -- ALU case opcInfo(aluMode2From to aluMode2To) is when aluModeAdc => lowBits := ("0" & A(3 downto 0) & rmwBits(8)) + ("0" & rmwBits(3 downto 0) & "1"); ninebits := ("0" & A) + ("0" & rmwBits(7 downto 0)) + (B"00000000" & rmwBits(8)); when aluModeSbc => lowBits := ("0" & A(3 downto 0) & rmwBits(8)) + ("0" & (not rmwBits(3 downto 0)) & "1"); ninebits := ("0" & A) + ("0" & (not rmwBits(7 downto 0))) + (B"00000000" & rmwBits(8)); when aluModeCmp => ninebits := ("0" & aluCmpInput) + ("0" & (not rmwBits(7 downto 0))) + "000000001"; when aluModeAnd => ninebits := rmwBits(8) & (A and rmwBits(7 downto 0)); when aluModeEor => ninebits := rmwBits(8) & (A xor rmwBits(7 downto 0)); when aluModeOra => ninebits := rmwBits(8) & (A or rmwBits(7 downto 0)); when aluModeNoF => ninebits := "000110000"; when others => ninebits := rmwBits; end case; varV := aluInput(6); -- Default for BIT / PLP / RTI if (opcInfo(aluMode1From to aluMode1To) = aluModeFlg) then varZ := rmwBits(1); elsif (opcInfo(aluMode1From to aluMode1To) = aluModeTSB) or (opcInfo(aluMode1From to aluMode1To) = aluModeTRB) then if tsxBits(7 downto 0) = X"00" then varZ := '1'; else varZ := '0'; end if; elsif ninebits(7 downto 0) = X"00" then varZ := '1'; else varZ := '0'; end if; if (opcInfo(aluMode1From to aluMode1To) = aluModeBit) or (opcInfo(aluMode1From to aluMode1To) = aluModeFlg) then varN := rmwBits(7); else varN := nineBits(7); end if; varC := ninebits(8); case opcInfo(aluMode2From to aluMode2To) is -- Flags Affected: n v — — — — z c -- n Set if most significant bit of result is set; else cleared. -- v Set if signed overflow; cleared if valid signed result. -- z Set if result is zero; else cleared. -- c Set if unsigned overflow; cleared if valid unsigned result when aluModeAdc => -- decimal mode low bits correction, is done after setting Z flag. if D = '1' then if lowBits(5 downto 1) > 9 then ninebits(3 downto 0) := ninebits(3 downto 0) + 6; if lowBits(5) = '0' then ninebits(8 downto 4) := ninebits(8 downto 4) + 1; end if; end if; end if; when others => null; end case; case opcInfo(aluMode2From to aluMode2To) is when aluModeAdc => -- decimal mode high bits correction, is done after setting Z and N flags varV := (A(7) xor ninebits(7)) and (rmwBits(7) xor ninebits(7)); if D = '1' then if ninebits(8 downto 4) > 9 then ninebits(8 downto 4) := ninebits(8 downto 4) + 6; varC := '1'; end if; end if; when aluModeSbc => varV := (A(7) xor ninebits(7)) and ((not rmwBits(7)) xor ninebits(7)); if D = '1' then -- Check for borrow (lower 4 bits) if lowBits(5) = '0' then ninebits(7 downto 0) := ninebits(7 downto 0) - 6; end if; -- Check for borrow (upper 4 bits) if ninebits(8) = '0' then ninebits(8 downto 4) := ninebits(8 downto 4) - 6; end if; end if; when others => null; end case; -- fix n and z flag for 65c02 adc sbc instructions in decimal mode case opcInfo(aluMode2From to aluMode2To) is when aluModeAdc => if D = '1' then if ninebits(7 downto 0) = X"00" then varZ := '1'; else varZ := '0'; end if; varN := ninebits(7); end if; when aluModeSbc => if D = '1' then if ninebits(7 downto 0) = X"00" then varZ := '1'; else varZ := '0'; end if; varN := ninebits(7); end if; when others => null; end case; -- DMB Remove Pipelining -- if rising_edge(clk) then aluRmwOut <= rmwBits(7 downto 0); aluRegisterOut <= ninebits(7 downto 0); aluC <= varC; aluZ <= varZ; aluV <= varV; aluN <= varN; -- end if; end process; calcInterrupt: process(clk) begin if rising_edge(clk) then if enable = '1' then if theCpuCycle = cycleStack4 or reset = '0' then nmiReg <= '1'; end if; if nextCpuCycle /= cycleBranchTaken and nextCpuCycle /= opcodeFetch then irqReg <= irq_n; nmiEdge <= nmi_n; if (nmiEdge = '1') and (nmi_n = '0') then nmiReg <= '0'; end if; end if; -- The 'or opcInfo(opcSetI)' prevents NMI immediately after BRK or IRQ. -- Presumably this is done in the real 6502/6510 to prevent a double IRQ. processIrq <= not ((nmiReg and (irqReg or I)) or opcInfo(opcIRQ)); end if; end if; end process; --pipeirq: process(clk) -- begin -- if rising_edge(clk) then -- if enable = '1' then -- if (reset = '0') or (theCpuCycle = opcodeFetch) then -- -- The 'or opcInfo(opcSetI)' prevents NMI immediately after BRK or IRQ. -- -- Presumably this is done in the real 6502/6510 to prevent a double IRQ. -- processIrq <= not ((nmiReg and (irqReg or I)) or opcInfo(opcIRQ)); -- end if; -- end if; -- end if; -- end process; calcNextOpcode: process(clk, di, reset, processIrq) variable myNextOpcode : unsigned(7 downto 0); begin -- Next opcode is read from input unless a reset or IRQ is pending. myNextOpcode := di; if reset = '0' then myNextOpcode := X"4C"; elsif processIrq = '1' then myNextOpcode := X"00"; end if; nextOpcode <= myNextOpcode; end process; nextOpcInfo <= opcodeInfoTable(to_integer(nextOpcode)); -- DMB Remove Pipelining -- process(clk) -- begin -- if rising_edge(clk) then nextOpcInfoReg <= nextOpcInfo; -- end if; -- end process; -- Read bits and flags from opcodeInfoTable and store in opcInfo. -- This info is used to control the execution of the opcode. calcOpcInfo: process(clk) begin if rising_edge(clk) then if enable = '1' then if (reset = '0') or (theCpuCycle = opcodeFetch) then opcInfo <= nextOpcInfo; end if; end if; end if; end process; calcTheOpcode: process(clk) begin if rising_edge(clk) then if enable = '1' then if theCpuCycle = opcodeFetch then irqActive <= '0'; if processIrq = '1' then irqActive <= '1'; end if; -- Fetch opcode theOpcode <= nextOpcode; end if; end if; end if; end process; -- ----------------------------------------------------------------------- -- State machine -- ----------------------------------------------------------------------- process(enable, theCpuCycle, opcInfo) begin updateRegisters <= false; if enable = '1' then if opcInfo(opcRti) = '1' then if theCpuCycle = cycleRead then updateRegisters <= true; end if; elsif theCpuCycle = opcodeFetch then updateRegisters <= true; end if; end if; end process; process(clk) begin if rising_edge(clk) then if enable = '1' then theCpuCycle <= nextCpuCycle; end if; if reset = '0' then theCpuCycle <= cycle2; end if; end if; end process; -- Determine the next cpu cycle. After the last cycle we always -- go to opcodeFetch to get the next opcode. calcNextCpuCycle: process(theCpuCycle, opcInfo, theOpcode, indexOut, T, N, V, C, Z) begin nextCpuCycle <= opcodeFetch; case theCpuCycle is when opcodeFetch => nextCpuCycle <= cycle2; when cycle2 => if opcInfo(opcBranch) = '1' then if (N = theOpcode(5) and theOpcode(7 downto 6) = "00") or (V = theOpcode(5) and theOpcode(7 downto 6) = "01") or (C = theOpcode(5) and theOpcode(7 downto 6) = "10") or (Z = theOpcode(5) and theOpcode(7 downto 6) = "11") or (theOpcode(7 downto 0) = x"80") then -- Branch condition is true nextCpuCycle <= cycleBranchTaken; end if; elsif (opcInfo(opcStackUp) = '1') then nextCpuCycle <= cycleStack1; elsif opcInfo(opcStackAddr) = '1' and opcInfo(opcStackData) = '1' then nextCpuCycle <= cycleStack2; elsif opcInfo(opcStackAddr) = '1' then nextCpuCycle <= cycleStack1; elsif opcInfo(opcStackData) = '1' then nextCpuCycle <= cycleWrite; elsif opcInfo(opcAbsolute) = '1' then nextCpuCycle <= cycle3; elsif opcInfo(opcIndirect) = '1' then if opcInfo(indexX) = '1' then nextCpuCycle <= cyclePreIndirect; else nextCpuCycle <= cycleIndirect; end if; elsif opcInfo(opcZeroPage) = '1' then if opcInfo(opcWrite) = '1' then if (opcInfo(indexX) = '1') or (opcInfo(indexY) = '1') then nextCpuCycle <= cyclePreWrite; else nextCpuCycle <= cycleWrite; end if; else if (opcInfo(indexX) = '1') or (opcInfo(indexY) = '1') then nextCpuCycle <= cyclePreRead; else nextCpuCycle <= cycleRead2; end if; end if; elsif opcInfo(opcJump) = '1' then nextCpuCycle <= cycleJump; end if; when cycle3 => nextCpuCycle <= cycleRead; if opcInfo(opcWrite) = '1' then if (opcInfo(indexX) = '1') or (opcInfo(indexY) = '1') then nextCpuCycle <= cyclePreWrite; else nextCpuCycle <= cycleWrite; end if; end if; if (opcInfo(opcIndirect) = '1') and (opcInfo(indexX) = '1') then if opcInfo(opcWrite) = '1' then nextCpuCycle <= cycleWrite; else nextCpuCycle <= cycleRead2; end if; end if; when cyclePreIndirect => nextCpuCycle <= cycleIndirect; when cycleIndirect => nextCpuCycle <= cycle3; when cycleBranchTaken => if indexOut(8) /= T(7) then nextCpuCycle <= cycleBranchPage; end if; when cyclePreRead => if opcInfo(opcZeroPage) = '1' then nextCpuCycle <= cycleRead2; end if; when cycleRead => if opcInfo(opcJump) = '1' then nextCpuCycle <= cycleJump; elsif indexOut(8) = '1' then nextCpuCycle <= cycleRead2; elsif opcInfo(opcRmw) = '1' then nextCpuCycle <= cycleRmw; if opcInfo(indexX) = '1' or opcInfo(indexY) = '1' then nextCpuCycle <= cycleRead2; end if; end if; when cycleRead2 => if opcInfo(opcRmw) = '1' then nextCpuCycle <= cycleRmw; end if; when cycleRmw => nextCpuCycle <= cycleWrite; when cyclePreWrite => nextCpuCycle <= cycleWrite; when cycleStack1 => nextCpuCycle <= cycleRead; if opcInfo(opcStackAddr) = '1' then nextCpuCycle <= cycleStack2; end if; when cycleStack2 => nextCpuCycle <= cycleStack3; if opcInfo(opcRti) = '1' then nextCpuCycle <= cycleRead; end if; if opcInfo(opcStackData) = '0' and opcInfo(opcStackUp) = '1' then nextCpuCycle <= cycleJump; end if; when cycleStack3 => nextCpuCycle <= cycleRead; if opcInfo(opcStackData) = '0' or opcInfo(opcStackUp) = '1' then nextCpuCycle <= cycleJump; elsif opcInfo(opcStackAddr) = '1' then nextCpuCycle <= cycleStack4; end if; when cycleStack4 => nextCpuCycle <= cycleRead; when cycleJump => if opcInfo(opcIncrAfter) = '1' then nextCpuCycle <= cycleEnd; end if; when others => null; end case; end process; -- ----------------------------------------------------------------------- -- T register -- ----------------------------------------------------------------------- calcT: process(clk) begin if rising_edge(clk) then if enable = '1' then case theCpuCycle is when cycle2 => T <= di; when cycleStack1 | cycleStack2 => if opcInfo(opcStackUp) = '1' then if theOpcode = x"28" or theOpcode = x"40" then -- plp or rti pulling the flags off the stack T <= (di or "00110000"); -- Read from stack else T <= di; end if; end if; when cycleIndirect | cycleRead | cycleRead2 => T <= di; when others => null; end case; end if; end if; end process; -- ----------------------------------------------------------------------- -- A register -- ----------------------------------------------------------------------- process(clk) begin if rising_edge(clk) then if updateRegisters then if opcInfo(opcUpdateA) = '1' then A <= aluRegisterOut; end if; end if; end if; end process; -- ----------------------------------------------------------------------- -- X register -- ----------------------------------------------------------------------- process(clk) begin if rising_edge(clk) then if updateRegisters then if opcInfo(opcUpdateX) = '1' then X <= aluRegisterOut; end if; end if; end if; end process; -- ----------------------------------------------------------------------- -- Y register -- ----------------------------------------------------------------------- process(clk) begin if rising_edge(clk) then if updateRegisters then if opcInfo(opcUpdateY) = '1' then Y <= aluRegisterOut; end if; end if; end if; end process; -- ----------------------------------------------------------------------- -- C flag -- ----------------------------------------------------------------------- process(clk) begin if rising_edge(clk) then if updateRegisters then if opcInfo(opcUpdateC) = '1' then C <= aluC; end if; end if; end if; end process; -- ----------------------------------------------------------------------- -- Z flag -- ----------------------------------------------------------------------- process(clk) begin if rising_edge(clk) then if updateRegisters then if opcInfo(opcUpdateZ) = '1' then Z <= aluZ; end if; end if; end if; end process; -- ----------------------------------------------------------------------- -- I flag interupt flag -- ----------------------------------------------------------------------- process(clk, reset) begin if reset = '0' then I <= '1'; elsif rising_edge(clk) then if updateRegisters then if opcInfo(opcUpdateI) = '1' then I <= aluInput(2); end if; end if; end if; end process; -- ----------------------------------------------------------------------- -- D flag -- ----------------------------------------------------------------------- process(clk, reset) begin if reset = '0' then D <= '0'; elsif rising_edge(clk) then if updateRegisters then if opcInfo(opcUpdateD) = '1' then D <= aluInput(3); end if; end if; end if; end process; -- ----------------------------------------------------------------------- -- V flag -- ----------------------------------------------------------------------- process(clk) begin if rising_edge(clk) then if updateRegisters then if opcInfo(opcUpdateV) = '1' then V <= aluV; end if; end if; end if; end process; -- ----------------------------------------------------------------------- -- N flag -- ----------------------------------------------------------------------- process(clk) begin if rising_edge(clk) then if updateRegisters then if opcInfo(opcUpdateN) = '1' then N <= aluN; end if; end if; end if; end process; -- ----------------------------------------------------------------------- -- Stack pointer -- ----------------------------------------------------------------------- process(clk) variable sIncDec : unsigned(7 downto 0); variable updateFlag : boolean; begin if rising_edge(clk) then if opcInfo(opcStackUp) = '1' then sIncDec := S + 1; else sIncDec := S - 1; end if; if enable = '1' then updateFlag := false; case nextCpuCycle is when cycleStack1 => if (opcInfo(opcStackUp) = '1') or (opcInfo(opcStackData) = '1') then updateFlag := true; end if; when cycleStack2 => updateFlag := true; when cycleStack3 => updateFlag := true; when cycleStack4 => updateFlag := true; when cycleRead => if opcInfo(opcRti) = '1' then updateFlag := true; end if; when cycleWrite => if opcInfo(opcStackData) = '1' then updateFlag := true; end if; when others => null; end case; if updateFlag then S <= sIncDec; end if; end if; if updateRegisters then if opcInfo(opcUpdateS) = '1' then S <= aluRegisterOut; end if; end if; end if; end process; -- ----------------------------------------------------------------------- -- Data out -- ----------------------------------------------------------------------- calcDo: process(clk) begin if rising_edge(clk) then if enable = '1' then doReg <= aluRmwOut; case nextCpuCycle is when cycleStack2 => if opcInfo(opcIRQ) = '1' and irqActive = '0' then doReg <= myAddrIncr(15 downto 8); else doReg <= PC(15 downto 8); end if; when cycleStack3 => doReg <= PC(7 downto 0); when cycleRmw => doReg <= di; -- Read-modify-write write old value first. when others => null; end case; end if; end if; end process; do <= doReg; -- ----------------------------------------------------------------------- -- Write enable -- ----------------------------------------------------------------------- calcWe: process(clk) begin if rising_edge(clk) then if enable = '1' then theWe <= '1'; case nextCpuCycle is when cycleStack1 => if opcInfo(opcStackUp) = '0' and ((opcInfo(opcStackAddr) = '0') or (opcInfo(opcStackData) = '1')) then theWe <= '0'; end if; when cycleStack2 | cycleStack3 | cycleStack4 => if opcInfo(opcStackUp) = '0' then theWe <= '0'; end if; when cycleRmw => theWe <= '0'; when cycleWrite => theWe <= '0'; when others => null; end case; end if; end if; --nwe <= theWe; end process; nwe <= theWe; -- ----------------------------------------------------------------------- -- Program counter -- ----------------------------------------------------------------------- calcPC: process(clk) begin if rising_edge(clk) then if enable = '1' then case theCpuCycle is when opcodeFetch => PC <= myAddr; when cycle2 => if irqActive = '0' then if opcInfo(opcSecondByte) = '1' then PC <= myAddrIncr; else PC <= myAddr; end if; end if; when cycle3 => if opcInfo(opcAbsolute) = '1' then PC <= myAddrIncr; end if; when others => null; end case; end if; end if; end process; -- ----------------------------------------------------------------------- -- Address generation -- ----------------------------------------------------------------------- calcNextAddr: process(theCpuCycle, opcInfo, indexOut, T, reset) begin nextAddr <= nextAddrIncr; case theCpuCycle is when cycle2 => if opcInfo(opcStackAddr) = '1' or opcInfo(opcStackData) = '1' then nextAddr <= nextAddrStack; elsif opcInfo(opcAbsolute) = '1' then nextAddr <= nextAddrIncr; elsif opcInfo(opcZeroPage) = '1' then nextAddr <= nextAddrZeroPage; elsif opcInfo(opcIndirect) = '1' then nextAddr <= nextAddrZeroPage; elsif opcInfo(opcSecondByte) = '1' then nextAddr <= nextAddrIncr; else nextAddr <= nextAddrHold; end if; when cycle3 => if (opcInfo(opcIndirect) = '1') and (opcInfo(indexX) = '1') then nextAddr <= nextAddrAbs; else nextAddr <= nextAddrAbsIndexed; end if; when cyclePreIndirect => nextAddr <= nextAddrZPIndexed; when cycleIndirect => nextAddr <= nextAddrIncrL; when cycleBranchTaken => nextAddr <= nextAddrRelative; when cycleBranchPage => if T(7) = '0' then nextAddr <= nextAddrIncrH; else nextAddr <= nextAddrDecrH; end if; when cyclePreRead => nextAddr <= nextAddrZPIndexed; when cycleRead => nextAddr <= nextAddrPc; if opcInfo(opcJump) = '1' then -- Emulate 6510 bug, jmp(xxFF) fetches from same page. -- Replace with nextAddrIncr if emulating 65C02 or later cpu. nextAddr <= nextAddrIncr; --nextAddr <= nextAddrIncrL; elsif indexOut(8) = '1' then nextAddr <= nextAddrIncrH; elsif opcInfo(opcRmw) = '1' then nextAddr <= nextAddrHold; end if; when cycleRead2 => nextAddr <= nextAddrPc; if opcInfo(opcRmw) = '1' then nextAddr <= nextAddrHold; end if; when cycleRmw => nextAddr <= nextAddrHold; when cyclePreWrite => nextAddr <= nextAddrHold; if opcInfo(opcZeroPage) = '1' then nextAddr <= nextAddrZPIndexed; elsif indexOut(8) = '1' then nextAddr <= nextAddrIncrH; end if; when cycleWrite => nextAddr <= nextAddrPc; when cycleStack1 => nextAddr <= nextAddrStack; when cycleStack2 => nextAddr <= nextAddrStack; when cycleStack3 => nextAddr <= nextAddrStack; if opcInfo(opcStackData) = '0' then nextAddr <= nextAddrPc; end if; when cycleStack4 => nextAddr <= nextAddrIrq; when cycleJump => nextAddr <= nextAddrAbs; when others => null; end case; if reset = '0' then nextAddr <= nextAddrReset; end if; end process; indexAlu: process(opcInfo, myAddr, T, X, Y) begin if opcInfo(indexX) = '1' then indexOut <= (B"0" & T) + (B"0" & X); elsif opcInfo(indexY) = '1' then indexOut <= (B"0" & T) + (B"0" & Y); elsif opcInfo(opcBranch) = '1' then indexOut <= (B"0" & T) + (B"0" & myAddr(7 downto 0)); else indexOut <= B"0" & T; end if; end process; calcAddr: process(clk) begin if rising_edge(clk) then if enable = '1' then case nextAddr is when nextAddrIncr => myAddr <= myAddrIncr; when nextAddrIncrL => myAddr(7 downto 0) <= myAddrIncr(7 downto 0); when nextAddrIncrH => myAddr(15 downto 8) <= myAddrIncrH; when nextAddrDecrH => myAddr(15 downto 8) <= myAddrDecrH; when nextAddrPc => myAddr <= PC; when nextAddrIrq =>myAddr <= X"FFFE"; if nmiReg = '0' then myAddr <= X"FFFA"; end if; when nextAddrReset => myAddr <= X"FFFC"; when nextAddrAbs => myAddr <= di & T; when nextAddrAbsIndexed =>--myAddr <= di & indexOut(7 downto 0); if theOpcode = x"7C" then myAddr <= (di & T) + (x"00"& X); else myAddr <= di & indexOut(7 downto 0); end if; when nextAddrZeroPage => myAddr <= "00000000" & di; when nextAddrZPIndexed => myAddr <= "00000000" & indexOut(7 downto 0); when nextAddrStack => myAddr <= "00000001" & S; when nextAddrRelative => myAddr(7 downto 0) <= indexOut(7 downto 0); when others => null; end case; end if; end if; end process; myAddrIncr <= myAddr + 1; myAddrIncrH <= myAddr(15 downto 8) + 1; myAddrDecrH <= myAddr(15 downto 8) - 1; addr <= myAddr; -- DMB This looked plain broken and inferred a latch -- -- calcsync: process(clk) -- begin -- -- if enable = '1' then -- case theCpuCycle is -- when opcodeFetch => sync <= '1'; -- when others => sync <= '0'; -- end case; -- end if; -- end process; sync <= '1' when theCpuCycle = opcodeFetch else '0'; sync_irq <= irqActive; Regs <= std_logic_vector(myAddr) & "00000001" & std_logic_vector(S)& N & V & R & B & D & I & Z & C & std_logic_vector(Y) & std_logic_vector(X) & std_logic_vector(A); end architecture;
apache-2.0
cb6937b6331009dcb9b17fd53fa2c86d
0.549976
3.442511
false
false
false
false
hoglet67/AtomFpga
src/common/AVR8/Core/alu_avr.vhd
4
13,455
--************************************************************************************************ -- ALU(internal module) for AVR core -- Version 1.2 -- Designed by Ruslan Lepetenok -- Modified 02.08.2003 -- (CPC/SBC/SBCI Z-flag bug found) -- H-flag with NEG instruction found --************************************************************************************************ library IEEE; use IEEE.std_logic_1164.all; entity alu_avr is port( alu_data_r_in : in std_logic_vector(7 downto 0); alu_data_d_in : in std_logic_vector(7 downto 0); alu_c_flag_in : in std_logic; alu_z_flag_in : in std_logic; -- OPERATION SIGNALS INPUTS idc_add :in std_logic; idc_adc :in std_logic; idc_adiw :in std_logic; idc_sub :in std_logic; idc_subi :in std_logic; idc_sbc :in std_logic; idc_sbci :in std_logic; idc_sbiw :in std_logic; adiw_st : in std_logic; sbiw_st : in std_logic; idc_and :in std_logic; idc_andi :in std_logic; idc_or :in std_logic; idc_ori :in std_logic; idc_eor :in std_logic; idc_com :in std_logic; idc_neg :in std_logic; idc_inc :in std_logic; idc_dec :in std_logic; idc_cp :in std_logic; idc_cpc :in std_logic; idc_cpi :in std_logic; idc_cpse :in std_logic; idc_lsr :in std_logic; idc_ror :in std_logic; idc_asr :in std_logic; idc_swap :in std_logic; -- DATA OUTPUT alu_data_out : out std_logic_vector(7 downto 0); -- FLAGS OUTPUT alu_c_flag_out : out std_logic; alu_z_flag_out : out std_logic; alu_n_flag_out : out std_logic; alu_v_flag_out : out std_logic; alu_s_flag_out : out std_logic; alu_h_flag_out : out std_logic ); end alu_avr; architecture rtl of alu_avr is -- #################################################### -- INTERNAL SIGNALS -- #################################################### signal alu_data_out_int : std_logic_vector (7 downto 0); -- ALU FLAGS (INTERNAL) signal alu_z_flag_out_int : std_logic; signal alu_c_flag_in_int : std_logic; -- INTERNAL CARRY FLAG signal alu_n_flag_out_int : std_logic; signal alu_v_flag_out_int : std_logic; signal alu_c_flag_out_int : std_logic; -- ADDER SIGNALS -- signal adder_nadd_sub : std_logic; -- 0 -> ADD ,1 -> SUB signal adder_v_flag_out : std_logic; signal adder_carry : std_logic_vector(8 downto 0); signal adder_d_in : std_logic_vector(8 downto 0); signal adder_r_in : std_logic_vector(8 downto 0); signal adder_out : std_logic_vector(8 downto 0); -- NEG OPERATOR SIGNALS signal neg_op_in : std_logic_vector(7 downto 0); signal neg_op_carry : std_logic_vector(8 downto 0); signal neg_op_out : std_logic_vector(8 downto 0); -- INC, DEC OPERATOR SIGNALS signal incdec_op_in : std_logic_vector (7 downto 0); signal incdec_op_carry : std_logic_vector(7 downto 0); signal incdec_op_out : std_logic_vector(7 downto 0); signal com_op_out : std_logic_vector(7 downto 0); signal and_op_out : std_logic_vector(7 downto 0); signal or_op_out : std_logic_vector(7 downto 0); signal eor_op_out : std_logic_vector(7 downto 0); -- SHIFT SIGNALS signal right_shift_out : std_logic_vector(7 downto 0); -- SWAP SIGNALS signal swap_out : std_logic_vector(7 downto 0); begin -- ######################################################################## -- ############### ALU -- ######################################################################## adder_nadd_sub <=(idc_sub or idc_subi or idc_sbc or idc_sbci or idc_sbiw or sbiw_st or idc_cp or idc_cpc or idc_cpi or idc_cpse ); -- '0' -> '+'; '1' -> '-' -- SREG C FLAG (ALU INPUT) alu_c_flag_in_int <= alu_c_flag_in and (idc_adc or adiw_st or idc_sbc or idc_sbci or sbiw_st or idc_cpc or idc_ror); -- SREG Z FLAG () -- alu_z_flag_out <= (alu_z_flag_out_int and not(adiw_st or sbiw_st)) or -- ((alu_z_flag_in and alu_z_flag_out_int) and (adiw_st or sbiw_st)); alu_z_flag_out <= (alu_z_flag_out_int and not(adiw_st or sbiw_st or idc_cpc or idc_sbc or idc_sbci)) or ((alu_z_flag_in and alu_z_flag_out_int) and (adiw_st or sbiw_st))or (alu_z_flag_in and alu_z_flag_out_int and(idc_cpc or idc_sbc or idc_sbci)); -- Previous value (for CPC/SBC/SBCI instructions) -- SREG N FLAG alu_n_flag_out <= alu_n_flag_out_int; -- SREG V FLAG alu_v_flag_out <= alu_v_flag_out_int; alu_c_flag_out <= alu_c_flag_out_int; alu_data_out <= alu_data_out_int; -- ######################################################################################### adder_d_in <= '0'&alu_data_d_in; adder_r_in <= '0'&alu_data_r_in; --########################## ADDEER ################################### adder_out(0) <= adder_d_in(0) xor adder_r_in(0) xor alu_c_flag_in_int; adder_carry(0) <= ((adder_d_in(0) xor adder_nadd_sub) and adder_r_in(0)) or (((adder_d_in(0) xor adder_nadd_sub) or adder_r_in(0)) and alu_c_flag_in_int); summator:for i in 1 to 8 generate adder_out(i) <= adder_d_in(i) xor adder_r_in(i) xor adder_carry(i-1); adder_carry(i) <= ((adder_d_in(i) xor adder_nadd_sub) and adder_r_in(i)) or (((adder_d_in(i) xor adder_nadd_sub) or adder_r_in(i)) and adder_carry(i-1)); end generate; -- FLAGS FOR ADDER INSTRUCTIONS: -- CARRY FLAG (C) -> adder_out(8) -- HALF CARRY FLAG (H) -> adder_carry(3) -- TOW'S COMPLEMENT OVERFLOW (V) -> adder_v_flag_out <= (((adder_d_in(7) and adder_r_in(7) and not adder_out(7)) or (not adder_d_in(7) and not adder_r_in(7) and adder_out(7))) and not adder_nadd_sub) or -- ADD (((adder_d_in(7) and not adder_r_in(7) and not adder_out(7)) or (not adder_d_in(7) and adder_r_in(7) and adder_out(7))) and adder_nadd_sub); -- SUB --##################################################################### -- LOGICAL OPERATIONS FOR ONE OPERAND --########################## NEG OPERATION #################### neg_op_out(0) <= not alu_data_d_in(0) xor '1'; neg_op_carry(0) <= not alu_data_d_in(0) and '1'; neg_op:for i in 1 to 7 generate neg_op_out(i) <= not alu_data_d_in(i) xor neg_op_carry(i-1); neg_op_carry(i) <= not alu_data_d_in(i) and neg_op_carry(i-1); end generate; neg_op_out(8) <= neg_op_carry(7) xor '1'; neg_op_carry(8) <= neg_op_carry(7); -- ??!! -- CARRY FLAGS FOR NEG INSTRUCTION: -- CARRY FLAG -> neg_op_out(8) -- HALF CARRY FLAG -> neg_op_carry(3) -- TOW's COMPLEMENT OVERFLOW FLAG -> alu_data_d_in(7) and neg_op_carry(6) --############################################################################ --########################## INC, DEC OPERATIONS #################### incdec_op_out(0) <= alu_data_d_in(0) xor '1'; incdec_op_carry(0) <= alu_data_d_in(0) xor idc_dec; inc_dec:for i in 1 to 7 generate incdec_op_out(i) <= alu_data_d_in(i) xor incdec_op_carry(i-1); incdec_op_carry(i) <= (alu_data_d_in(i) xor idc_dec) and incdec_op_carry(i-1); end generate; -- TOW's COMPLEMENT OVERFLOW FLAG -> (alu_data_d_in(7) xor idc_dec) and incdec_op_carry(6) --#################################################################### --########################## COM OPERATION ################################### com_op_out <= not alu_data_d_in; -- FLAGS -- TOW's COMPLEMENT OVERFLOW FLAG (V) -> '0' -- CARRY FLAG (C) -> '1' --############################################################################ -- LOGICAL OPERATIONS FOR TWO OPERANDS --########################## AND OPERATION ################################### and_op_out <= alu_data_d_in and alu_data_r_in; -- FLAGS -- TOW's COMPLEMENT OVERFLOW FLAG (V) -> '0' --############################################################################ --########################## OR OPERATION ################################### or_op_out <= alu_data_d_in or alu_data_r_in; -- FLAGS -- TOW's COMPLEMENT OVERFLOW FLAG (V) -> '0' --############################################################################ --########################## EOR OPERATION ################################### eor_op_out <= alu_data_d_in xor alu_data_r_in; -- FLAGS -- TOW's COMPLEMENT OVERFLOW FLAG (V) -> '0' --############################################################################ -- SHIFT OPERATIONS -- ########################## RIGHT(LSR, ROR, ASR) ####################### right_shift_out(7) <= (idc_ror and alu_c_flag_in_int) or (idc_asr and alu_data_d_in(7)); -- right_shift_out(7) shift_right:for i in 6 downto 0 generate right_shift_out(i) <= alu_data_d_in(i+1); end generate; -- FLAGS -- CARRY FLAG (C) -> alu_data_d_in(0) -- NEGATIVE FLAG (N) -> right_shift_out(7) -- TOW's COMPLEMENT OVERFLOW FLAG (V) -> N xor C (left_shift_out(7) xor alu_data_d_in(0)) -- ####################################################################### -- ################################## SWAP ############################### swap_h:for i in 7 downto 4 generate swap_out(i) <= alu_data_d_in(i-4); end generate; swap_l:for i in 3 downto 0 generate swap_out(i) <= alu_data_d_in(i+4); end generate; -- ####################################################################### -- ALU OUTPUT MUX alu_data_out_mux:for i in alu_data_out_int'range generate alu_data_out_int(i) <= (adder_out(i) and (idc_add or idc_adc or (idc_adiw or adiw_st) or -- !!!!! idc_sub or idc_subi or idc_sbc or idc_sbci or (idc_sbiw or sbiw_st) or -- !!!!! idc_cpse or idc_cp or idc_cpc or idc_cpi)) or (neg_op_out(i) and idc_neg) or -- NEG (incdec_op_out(i) and (idc_inc or idc_dec)) or -- INC/DEC (com_op_out(i) and idc_com) or -- COM (and_op_out(i) and (idc_and or idc_andi)) or -- AND/ANDI (or_op_out(i) and (idc_or or idc_ori)) or -- OR/ORI (eor_op_out(i) and idc_eor) or -- EOR (right_shift_out(i) and (idc_lsr or idc_ror or idc_asr)) or -- LSR/ROR/ASR (swap_out(i) and idc_swap); -- SWAP end generate; --@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ ALU FLAGS OUTPUTS @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ alu_h_flag_out <= (adder_carry(3) and -- ADDER INSTRUCTIONS (idc_add or idc_adc or idc_sub or idc_subi or idc_sbc or idc_sbci or idc_cp or idc_cpc or idc_cpi)) or (not neg_op_carry(3) and idc_neg); -- H-flag problem with NEG instruction fixing -- NEG alu_s_flag_out <= alu_n_flag_out_int xor alu_v_flag_out_int; alu_v_flag_out_int <= (adder_v_flag_out and (idc_add or idc_adc or idc_sub or idc_subi or idc_sbc or idc_sbci or adiw_st or sbiw_st or idc_cp or idc_cpi or idc_cpc)) or ((alu_data_d_in(7) and neg_op_carry(6)) and idc_neg) or -- NEG (not alu_data_d_in(7) and incdec_op_carry(6) and idc_inc) or -- INC (alu_data_d_in(7) and incdec_op_carry(6) and idc_dec) or -- DEC ((alu_n_flag_out_int xor alu_c_flag_out_int) and (idc_lsr or idc_ror or idc_asr)); -- LSR,ROR,ASR alu_n_flag_out_int <= alu_data_out_int(7); alu_z_flag_out_int <= '1' when alu_data_out_int="00000000" else '0'; alu_c_flag_out_int <= (adder_out(8) and (idc_add or idc_adc or (idc_adiw or adiw_st) or idc_sub or idc_subi or idc_sbc or idc_sbci or (idc_sbiw or sbiw_st) or idc_cp or idc_cpc or idc_cpi)) or -- ADDER (not alu_z_flag_out_int and idc_neg) or -- NEG (alu_data_d_in(0) and (idc_lsr or idc_ror or idc_asr)) or idc_com; -- @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ end rtl;
apache-2.0
e7e7f7063ad737160cd0865304ce97d1
0.437755
3.260237
false
false
false
false
hoglet67/AtomFpga
src/xilinx/AtomFpga_OlimexModVGA.vhd
1
8,532
-------------------------------------------------------------------------------- -- Copyright (c) 2009 Alan Daly. All rights reserved. -------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / -- \ \ \/ -- \ \ -- / / Filename : AtomFpga_OlimexModVGA.vhd -- /___/ /\ Timestamp : 02/03/2013 06:17:50 -- \ \ / \ -- \___\/\___\ -- --Design Name: AtomFpga_OlimexModVGA --Device: spartan3A library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; entity AtomFpga_OlimexModVGA is port (clk_25M00 : in std_logic; ps2_clk : in std_logic; ps2_data : in std_logic; ERSTn : in std_logic; red : out std_logic_vector (2 downto 0); green : out std_logic_vector (2 downto 0); blue : out std_logic_vector (2 downto 0); vsync : out std_logic; hsync : out std_logic; CE1 : out std_logic; RAMWRn : out std_logic; RAMOEn : out std_logic; RamA : out std_logic_vector (15 downto 0); RamD : inout std_logic_vector (15 downto 0); audiol : out std_logic; audioR : out std_logic; FLASH_CS : out std_logic; -- Active low FLASH chip select FLASH_SI : out std_logic; -- Serial output to FLASH chip SI pin FLASH_CK : out std_logic; -- FLASH clock FLASH_SO : in std_logic; -- Serial input from FLASH chip SO SDMISO : in std_logic; SDSS : out std_logic; SDCLK : out std_logic; SDMOSI : out std_logic); end AtomFpga_OlimexModVGA; architecture behavioral of AtomFpga_OlimexModVGA is signal clock_16 : std_logic; signal clock_25 : std_logic; signal clock_32 : std_logic; signal Phi2 : std_logic; signal powerup_reset_n : std_logic; signal hard_reset_n : std_logic; signal reset_counter : std_logic_vector(15 downto 0); signal RAM_A : std_logic_vector(18 downto 0); signal RAM_Din : std_logic_vector(7 downto 0); signal RAM_Dout : std_logic_vector(7 downto 0); signal RAM_nWE : std_logic; signal RAM_nOE : std_logic; signal RAM_nCS : std_logic; signal ExternCE : std_logic; signal ExternWE : std_logic; signal ExternA : std_logic_vector(18 downto 0); signal ExternDin : std_logic_vector(7 downto 0); signal ExternDout : std_logic_vector(7 downto 0); ----------------------------------------------- -- Bootstrap ROM Image from SPI FLASH into SRAM ----------------------------------------------- -- TODO: The user_ values below are a hack -- specifying 030000/008000 did not work, although it should! -- there seems to be something different about the way the AT45DB041D is addressed -- but that's not obvious in the data sheet -- https://www.adestotech.com/wp-content/uploads/doc3595.pdf -- start address of user data in FLASH as obtained from bitmerge.py constant user_address : std_logic_vector(23 downto 0) := x"000000"; -- lenth of user data in FLASH = 32KB (8x 4KB ROM) images constant user_length : std_logic_vector(23 downto 0) := x"038000"; -- high when FLASH is being copied to SRAM, can be used by user as active high reset signal bootstrap_busy : std_logic; begin inst_dcm2 : entity work.dcm2 port map( CLKIN_IN => clk_25M00, CLK0_OUT => clock_25, CLKFX_OUT => clock_16); inst_dcm3 : entity work.dcm3 port map ( CLKIN_IN => clock_16, CLK0_OUT => clock_32, CLK0_OUT1 => open, CLK2X_OUT => open); inst_AtomFpga_Core : entity work.AtomFpga_Core generic map ( CImplSDDOS => true, CImplAtoMMC2 => false, CImplGraphicsExt => false, CImplSoftChar => false, CImplSID => false, CImplVGA80x40 => false, CImplHWScrolling => false, CImplMouse => false, CImplUart => false, CImplDoubleVideo => false, CImplRamRomNone => true, CImplRamRomPhill => false, CImplRamRomAtom2015 => false, CImplRamRomSchakelKaart => false, MainClockSpeed => 16000000, DefaultBaud => 115200 ) port map( clk_vga => clock_25, clk_main => clock_16, clk_avr => clock_16, clk_dac => clock_32, clk_32M00 => clock_32, ps2_clk => ps2_clk, ps2_data => ps2_data, ps2_mouse_clk => open, ps2_mouse_data => open, powerup_reset_n => powerup_reset_n, ext_reset_n => hard_reset_n, int_reset_n => open, red => red, green => green, blue => blue, vsync => vsync, hsync => hsync, Phi2 => Phi2, ExternCE => ExternCE, ExternWE => ExternWE, ExternA => ExternA, ExternDin => ExternDin, ExternDout => ExternDout, sid_audio => audiol, sid_audio_d => open, atom_audio => audioR, SDMISO => SDMISO, SDSS => SDSS, SDCLK => SDCLK, SDMOSI => SDMOSI, uart_RxD => '1', uart_TxD => open, avr_RxD => '1', avr_TxD => open, LED1 => open, LED2 => open, charSet => '0' ); -------------------------------------------------------- -- Power Up Reset Generation -------------------------------------------------------- -- On the Duo the external reset signal is not asserted on power up -- This internal counter forces power up reset to happen -- This is needed by the GODIL to initialize some of the registers ResetProcess : process (clock_16) begin if rising_edge(clock_16) then if (reset_counter(reset_counter'high) = '0') then reset_counter <= reset_counter + 1; end if; powerup_reset_n <= ERSTn and reset_counter(reset_counter'high); end if; end process; -- extend the version seen by the core to hold the 6502 reset during bootstrap hard_reset_n <= powerup_reset_n and not bootstrap_busy; -------------------------------------------------------- -- BOOTSTRAP SPI FLASH to SRAM -------------------------------------------------------- inst_bootstrap: entity work.bootstrap generic map ( gated_write => false, user_length => user_length ) port map( clock => clock_16, powerup_reset_n => powerup_reset_n, bootstrap_busy => bootstrap_busy, user_address => user_address, RAM_nOE => RAM_nOE, RAM_nWE => RAM_nWE, RAM_nCS => RAM_nCS, RAM_A => RAM_A, RAM_Din => RAM_Din, RAM_Dout => RAM_Dout, SRAM_nOE => RamOEn, SRAM_nWE => RamWRn, SRAM_nCS => CE1, SRAM_A(20 downto 16) => open, SRAM_A(15 downto 0) => RamA, SRAM_D => RamD(7 downto 0), FLASH_CS => FLASH_CS, FLASH_SI => FLASH_SI, FLASH_CK => FLASH_CK, FLASH_SO => FLASH_SO ); RamD(15 downto 8) <= (others => 'Z'); MemProcess : process (clock_16) begin if rising_edge(clock_16) then RAM_A <= ExternA xor ("000" & x"8000"); RAM_nCS <= not ExternCE; RAM_nOE <= not ((not ExternWE) and ExternCE); RAM_nWE <= not (ExternWE and ExternCE and phi2); RAM_Din <= ExternDin; end if; end process; ExternDout <= RAM_Dout; end behavioral;
apache-2.0
46e62b7bec8a98465f752e473c4c652d
0.467182
3.98878
false
false
false
false
Alabamajack/Garfield
FPGA_Design/ip_intern/PWM_Generator/pwm_generator.vhdl
1
1,244
-- inspired from Lothar Millers example on his homepage library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity pwm_generator is Generic(width : natural := 8; -- Breite freq_clock : integer := 50000000; -- Taktfrequenz freq_pwm : integer := 1000 -- PWM-Frequenz ); Port(clk : in std_logic; pwmvalue : in std_logic_vector(width - 1 downto 0); pwmout : out std_logic ); end pwm_generator; architecture RTL of pwm_generator is signal cnt : integer range 0 to 2 ** width - 2 := 0; signal pre : integer range 0 to freq_clock / (freq_pwm * (2 ** width - 2)) := 0; begin -- prescaler process begin wait until rising_edge(clk); if (pre < freq_clock / (freq_pwm * (2 ** width))) then pre <= pre + 1; else pre <= 0; end if; end process; -- pwm counter process begin wait until rising_edge(clk); if (pre = 0) then if (cnt < 2 ** width - 2) then cnt <= cnt + 1; else cnt <= 0; end if; end if; end process; -- output without glitches process begin wait until rising_edge(clk); if (cnt >= to_integer(unsigned(pwmvalue))) then pwmout <= '0'; else pwmout <= '1'; end if; end process; end RTL;
gpl-3.0
dbd537bd292a1c88b558b6b3741b79b3
0.601286
2.983213
false
false
false
false
hoglet67/AtomFpga
src/altera/AtomFpga_AlteraDE1.vhd
1
15,293
-- Acorn Atom FPGA for the Altera/Terasic DE1 -- -- Copright (c) 2016 David Banks -- -- Based on previous work by Alan Daly -- -- Copyright (c) 2013 Alan Daly -- -- All rights reserved -- -- Redistribution and use in source and synthezised forms, with or without -- modification, are permitted provided that the following conditions are met: -- -- * Redistributions of source code must retain the above copyright notice, -- this list of conditions and the following disclaimer. -- -- * Redistributions in synthesized form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- * Neither the name of the author nor the names of other contributors may -- be used to endorse or promote products derived from this software without -- specific prior written agreement from the author. -- -- * License is granted for non-commercial use only. A fee may not be charged -- for redistributions as source code or in synthesized/hardware form without -- specific prior written agreement from the author. -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- -- Altera/Terasic DE1 top-level -- -- (c) 2016 David Banks -- (C) 2013 Alan Daly library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; -- Generic top-level entity for Altera DE1 board entity AtomFpga_AlteraDE1 is port ( -- Clocks CLOCK_24_0 : in std_logic; CLOCK_24_1 : in std_logic; CLOCK_27_0 : in std_logic; CLOCK_27_1 : in std_logic; CLOCK_50 : in std_logic; EXT_CLOCK : in std_logic; -- Switches SW : in std_logic_vector(9 downto 0); -- Buttons KEY : in std_logic_vector(3 downto 0); -- 7 segment displays HEX0 : out std_logic_vector(6 downto 0); HEX1 : out std_logic_vector(6 downto 0); HEX2 : out std_logic_vector(6 downto 0); HEX3 : out std_logic_vector(6 downto 0); -- Red LEDs LEDR : out std_logic_vector(9 downto 0); -- Green LEDs LEDG : out std_logic_vector(7 downto 0); -- VGA VGA_R : out std_logic_vector(3 downto 0); VGA_G : out std_logic_vector(3 downto 0); VGA_B : out std_logic_vector(3 downto 0); VGA_HS : out std_logic; VGA_VS : out std_logic; -- Serial UART_RXD : in std_logic; UART_TXD : out std_logic; -- PS/2 Keyboard PS2_CLK : in std_logic; PS2_DAT : in std_logic; -- I2C I2C_SCLK : inout std_logic; I2C_SDAT : inout std_logic; -- Audio AUD_XCK : out std_logic; AUD_BCLK : out std_logic; AUD_ADCLRCK : out std_logic; AUD_ADCDAT : in std_logic; AUD_DACLRCK : out std_logic; AUD_DACDAT : out std_logic; -- SRAM SRAM_ADDR : out std_logic_vector(17 downto 0); SRAM_DQ : inout std_logic_vector(15 downto 0); SRAM_CE_N : out std_logic; SRAM_OE_N : out std_logic; SRAM_WE_N : out std_logic; SRAM_UB_N : out std_logic; SRAM_LB_N : out std_logic; -- SDRAM DRAM_ADDR : out std_logic_vector(11 downto 0); DRAM_DQ : inout std_logic_vector(15 downto 0); DRAM_BA_0 : in std_logic; DRAM_BA_1 : in std_logic; DRAM_CAS_N : in std_logic; DRAM_CKE : in std_logic; DRAM_CLK : in std_logic; DRAM_CS_N : in std_logic; DRAM_LDQM : in std_logic; DRAM_RAS_N : in std_logic; DRAM_UDQM : in std_logic; DRAM_WE_N : in std_logic; -- Flash FL_ADDR : out std_logic_vector(21 downto 0); FL_DQ : in std_logic_vector(7 downto 0); FL_RST_N : out std_logic; FL_OE_N : out std_logic; FL_WE_N : out std_logic; FL_CE_N : out std_logic; -- SD card (SPI mode) SD_nCS : out std_logic; SD_MOSI : out std_logic; SD_SCLK : out std_logic; SD_MISO : in std_logic; -- GPIO GPIO_0 : inout std_logic_vector(35 downto 0); GPIO_1 : inout std_logic_vector(35 downto 0) ); end entity; architecture rtl of AtomFpga_AlteraDE1 is ------------- -- Signals ------------- signal clock_16 : std_logic; signal clock_25 : std_logic; signal clock_32 : std_logic; signal led1 : std_logic; signal led2 : std_logic; signal Phi2 : std_logic; signal uart_Rx : std_logic; signal uart_Tx : std_logic; signal avr_Tx : std_logic; signal ExternCE : std_logic; signal ExternWE : std_logic; signal ExternA : std_logic_vector (18 downto 0); signal ExternDin : std_logic_vector (7 downto 0); signal ExternDout : std_logic_vector (7 downto 0); -- A registered version to allow slow flash to be used signal ExternA_r : std_logic_vector (18 downto 0); signal atom_audio : std_logic; signal sid_audio : std_logic_vector(17 downto 0); signal audio_l : std_logic_vector(15 downto 0); signal audio_r : std_logic_vector(15 downto 0); signal powerup_reset_n : std_logic; signal hard_reset_n : std_logic; signal reset_counter : std_logic_vector(15 downto 0); signal pll_reset : std_logic; signal pll_1_locked : std_logic; signal pll_2_locked : std_logic; signal is_done : std_logic; signal is_error : std_logic; function hex_to_seven_seg(hex: std_logic_vector(3 downto 0)) return std_logic_vector is begin case hex is -- abcdefg when x"0" => return "0111111"; when x"1" => return "0000110"; when x"2" => return "1011011"; when x"3" => return "1001111"; when x"4" => return "1100110"; when x"5" => return "1101101"; when x"6" => return "1111101"; when x"7" => return "0000111"; when x"8" => return "1111111"; when x"9" => return "1101111"; when x"a" => return "1110111"; when x"b" => return "1111100"; when x"c" => return "0111001"; when x"d" => return "1011110"; when x"e" => return "1111001"; when x"f" => return "1110001"; when others => return "0000000"; end case; end; begin -------------------------------------------------------- -- Atom FPGA Core -------------------------------------------------------- inst_AtomFpga_Core : entity work.AtomFpga_Core generic map ( CImplSDDOS => true, CImplAtoMMC2 => false, CImplGraphicsExt => true, CImplSoftChar => true, CImplSID => true, CImplVGA80x40 => true, CImplHWScrolling => true, CImplMouse => true, CImplUart => true, CImplDoubleVideo => false, CImplRamRomNone => false, CImplRamRomPhill => false, CImplRamRomAtom2015 => false, CImplRamRomSchakelKaart => true, MainClockSpeed => 16000000, DefaultBaud => 115200 ) port map( clk_vga => clock_25, clk_main => clock_16, clk_avr => clock_16, clk_dac => clock_32, clk_32M00 => clock_32, ps2_clk => PS2_CLK, ps2_data => PS2_DAT, ps2_mouse_clk => GPIO_1(18), ps2_mouse_data => GPIO_1(19), powerup_reset_n => powerup_reset_n, ext_reset_n => hard_reset_n, int_reset_n => open, red => VGA_R(3 downto 1), green => VGA_G(3 downto 1), blue => VGA_B(3 downto 1), vsync => VGA_VS, hsync => VGA_HS, Phi2 => Phi2, ExternCE => ExternCE, ExternWE => ExternWE, ExternA => ExternA, ExternDin => ExternDin, ExternDout => ExternDout, sid_audio => open, sid_audio_d => sid_audio, atom_audio => atom_audio, SDMISO => SD_MISO, SDSS => SD_nCS, SDCLK => SD_SCLK, SDMOSI => SD_MOSI, uart_RxD => uart_Rx, uart_TxD => uart_Tx, avr_RxD => '1', avr_TxD => avr_Tx, LED1 => led1, LED2 => led2, charSet => SW(0) ); uart_Rx <= UART_RXD; -- Idle state is high, logically OR the active low signals UART_TXD <= uart_Tx and avr_Tx; -------------------------------------------------------- -- Clock Generation -------------------------------------------------------- -- 16 MHz master clock and 32MHz SID clock from 24MHz input clock pll_1: entity work.pll32 port map ( areset => pll_reset, inclk0 => CLOCK_24_0, c0 => clock_16, c1 => clock_32, locked => pll_1_locked ); -- 25 MHz VGA clock from 50MHz input clock pll_2: entity work.pll25 port map ( areset => pll_reset, inclk0 => CLOCK_50, c0 => clock_25, locked => pll_2_locked ); -------------------------------------------------------- -- Power Up Reset Generation -------------------------------------------------------- -- PLL is reset by external reset switch pll_reset <= not KEY(0); -- Generate a reliable power up reset reset_gen : process(clock_16) begin if rising_edge(clock_16) then if (reset_counter(reset_counter'high) = '0') then reset_counter <= reset_counter + 1; end if; powerup_reset_n <= reset_counter(reset_counter'high); end if; end process; hard_reset_n <= not (pll_reset or not pll_1_locked or not pll_2_locked or not powerup_reset_n); -------------------------------------------------------- -- Audio DACs -------------------------------------------------------- -- This version assumes only one source is playing at once process(atom_audio, sid_audio) variable l : std_logic_vector(15 downto 0); variable r : std_logic_vector(15 downto 0); begin -- Atom Audio is a single bit if (atom_audio = '1') then l := x"1000"; r := x"1000"; else l := x"EFFF"; r := x"EFFF"; end if; -- SID output is 18-bit unsigned l := l + (sid_audio(17 downto 2) - x"8000"); r := r + (sid_audio(17 downto 2) - x"8000"); audio_l <= l; audio_r <= r; end process; i2s : entity work.i2s_intf port map ( CLK => clock_32, nRESET => hard_reset_n, PCM_INL => open, PCM_INR => open, PCM_OUTL => audio_l, PCM_OUTR => audio_r, I2S_MCLK => AUD_XCK, I2S_LRCLK => AUD_DACLRCK, I2S_BCLK => AUD_BCLK, I2S_DOUT => AUD_DACDAT, I2S_DIN => AUD_ADCDAT ); -- This is to avoid a possible conflict if the codec is in master mode AUD_ADCLRCK <= 'Z'; i2c : entity work.i2c_loader generic map ( log2_divider => 7 ) port map ( CLK => clock_32, nRESET => hard_reset_n, I2C_SCL => I2C_SCLK, I2C_SDA => I2C_SDAT, IS_DONE => is_done, IS_ERROR => is_error ); -------------------------------------------------------- -- Map external memory bus to SRAM/FLASH -------------------------------------------------------- -- Hold the ExternA for multiple clock cycles to allow slow FLASH to be used -- This is necessary because currently FLASH and SRAM accesses are -- interleaved every cycle. process(clock_16) begin if rising_edge(clock_16) then if ExternA(17) = '0' then ExternA_r <= ExternA; end if; end if; end process; -- 0x00000-0x1FFFF -> FLASH -- 0x20000-0x3FFFF -> SRAM ExternDout <= SRAM_DQ(7 downto 0) when ExternA(17) = '1' else FL_DQ; FL_RST_N <= hard_reset_n; FL_CE_N <= '0'; FL_OE_N <= '0'; FL_WE_N <= '1'; -- Flash address change every at most every 16 cycles (2MHz) -- Use the latched version to maximise access time -- Start at address at 0x100000 FL_ADDR <= "010000" & ExternA_r(15 downto 0); -- SRAM bus SRAM_UB_N <= '1'; SRAM_LB_N <= '0'; SRAM_CE_N <= '0'; SRAM_OE_N <= (not ExternCE) or ExternWE; -- Gate the WE with clock to provide more address/data hold time SRAM_WE_N <= (not ExternCE) or (not ExternWE) or (not Phi2) or (not clock_16); SRAM_ADDR <= ExternA(17 downto 0); SRAM_DQ(15 downto 8) <= (others => 'Z'); SRAM_DQ(7 downto 0) <= ExternDin when ExternCE = '1' and ExternWE = '1' and Phi2 = '1' else (others => 'Z'); -- HEX Displays (active low) HEX3 <= hex_to_seven_seg(ExternA(15 downto 12)) xor "1111111"; HEX2 <= hex_to_seven_seg(ExternA(11 downto 8)) xor "1111111"; HEX1 <= hex_to_seven_seg(ExternA( 7 downto 4)) xor "1111111"; HEX0 <= hex_to_seven_seg(ExternA( 3 downto 0)) xor "1111111"; -- LEDs (active high) LEDG(0) <= pll_1_locked; LEDG(1) <= pll_2_locked; LEDG(7 downto 2) <= (others => '0'); LEDR(0) <= led1; LEDR(1) <= led2; LEDR(2) <= is_error; LEDR(3) <= not is_done; LEDR(9 downto 4) <= (others => '0'); -- Unused outputs DRAM_ADDR <= (others => 'Z'); DRAM_DQ <= (others => 'Z'); GPIO_0(35 downto 0) <= (others => 'Z'); GPIO_1(35 downto 20) <= (others => 'Z'); GPIO_1(17 downto 0) <= (others => 'Z'); end architecture;
apache-2.0
a4d04df36d5cd5b8f7e02256cd1ad9cc
0.50958
3.660364
false
false
false
false
abyrne55/my-little-processor
my_little_processor.vhd
1
4,424
LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; -- "My Little Processor(TM)" -- Top Level Entity ENTITY my_little_processor IS PORT ( clock, reset : IN STD_LOGIC; data_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0); flag_out : OUT STD_LOGIC; done_out : OUT STD_LOGIC; c_state : OUT INTEGER; read_addr, reg0_out, reg1_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ); END; ARCHITECTURE behavioural OF my_little_processor IS SIGNAL read_addr_temp, main_bus, R0_output, R1_output, A_output, G_output, Adder_output : STD_LOGIC_VECTOR(15 DOWNTO 0); SIGNAL R0_in, R1_in, R0_out, R1_out, R0_xor, R1_xor, A_in, G_in, G_out, extern, done_temp, PC_in, PC_out : STD_LOGIC; SIGNAL read_addr_int : INTEGER; COMPONENT register_16bit PORT ( input : IN STD_LOGIC_VECTOR(15 DOWNTO 0); enable : IN STD_LOGIC; reset : IN STD_LOGIC; clock : IN STD_LOGIC; do_xor : IN STD_LOGIC; output : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ); END COMPONENT; COMPONENT PC PORT ( input : IN std_logic_vector(15 DOWNTO 0); en_in, clock, done, reset : IN std_logic; read_addr : OUT INTEGER ); END COMPONENT; COMPONENT control_circuit PORT ( clock, reset : IN STD_LOGIC; func : IN STD_LOGIC_VECTOR (15 DOWNTO 0); R0_in, R1_in : OUT STD_LOGIC; R0_out, R1_out : OUT STD_LOGIC; R0_xor, R1_xor : OUT STD_LOGIC; PC_in : OUT STD_LOGIC; PC_out : OUT STD_LOGIC; A_in, G_in, G_out, extern : OUT STD_LOGIC; done : OUT STD_LOGIC; c_state : OUT INTEGER ); END COMPONENT; COMPONENT tristate_16bit PORT ( input : IN STD_LOGIC_VECTOR(15 DOWNTO 0); enable : IN STD_LOGIC; output : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ); END COMPONENT; COMPONENT Adder PORT ( A, B : IN STD_LOGIC_VECTOR(15 DOWNTO 0); output : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); flag : OUT STD_LOGIC ); END COMPONENT; BEGIN PC0 : PC PORT MAP( input => main_bus, en_in => PC_in, clock => clock, done => done_temp, reset => reset, read_addr => read_addr_int ); control_circuit0 : control_circuit PORT MAP( reset => reset, clock => clock, func => data_in, R0_in => R0_in, R1_in => R1_in, R0_out => R0_out, R1_out => R1_out, R0_xor => R0_xor, R1_xor => R1_xor, A_in => A_in, G_in => G_in, G_out => G_out, extern => extern, done => done_temp, PC_in => PC_in, PC_out => PC_out, c_state => c_state ); register0 : register_16bit PORT MAP( input => main_bus, enable => R0_in, reset => reset, clock => clock, do_xor => R0_xor, output => R0_output ); register1 : register_16bit PORT MAP( input => main_bus, enable => R1_in, reset => reset, clock => clock, do_xor => R1_xor, output => R1_output ); registerA : register_16bit PORT MAP( input => main_bus, enable => A_in, reset => reset, clock => clock, do_xor => '0', output => A_output ); registerG : register_16bit PORT MAP( input => Adder_output, enable => G_in, reset => reset, clock => clock, do_xor => '0', output => G_output ); tristate_PC : tristate_16bit PORT MAP( input => read_addr_temp, enable => PC_out, output => main_bus ); tristate0 : tristate_16bit PORT MAP( input => R0_output, enable => R0_out, output => main_bus ); tristate1 : tristate_16bit PORT MAP( input => R1_output, enable => R1_out, output => main_bus ); tristateG : tristate_16bit PORT MAP( input => G_output, enable => G_out, output => main_bus ); tristateX : tristate_16bit PORT MAP(-- External Data input => data_in, enable => extern, output => main_bus ); Adder0 : Adder PORT MAP( A => A_output, B => main_bus, output => Adder_output, flag => flag_out ); read_addr_temp <= std_logic_vector(to_unsigned(read_addr_int, read_addr_temp'length)); read_addr <= read_addr_temp; done_out <= done_temp; reg0_out <= R0_output; reg1_out <= R1_output; END behavioural;
mit
262d5dcae5c34cff98253a94a3d3783d
0.549051
2.73424
false
false
false
false
hoglet67/AtomFpga
src/common/AVR8/resync/rsnc_comp_pack.vhd
4
2,088
--********************************************************************************************** -- Resynchronizers -- Version 0.1 -- Modified 10.01.2007 -- Designed by Ruslan Lepetenok --********************************************************************************************** library IEEE; use IEEE.std_logic_1164.all; package rsnc_comp_pack is component rsnc_vect is generic( width : integer := 8; add_stgs_num : integer := 0; inv_f_stgs : integer := 0 ); port( clk : in std_logic; di : in std_logic_vector(width-1 downto 0); do : out std_logic_vector(width-1 downto 0) ); end component; component rsnc_bit is generic( add_stgs_num : integer := 0; inv_f_stgs : integer := 0 ); port( clk : in std_logic; di : in std_logic; do : out std_logic ); end component; component rsnc_l_vect is generic( tech : integer := 0; width : integer := 8; add_stgs_num : integer := 0 ); port( clk : in std_logic; di : in std_logic_vector(width-1 downto 0); do : out std_logic_vector(width-1 downto 0) ); end component; component rsnc_l_bit is generic( tech : integer := 0; add_stgs_num : integer := 0 ); port( clk : in std_logic; di : in std_logic; do : out std_logic ); end component; end rsnc_comp_pack;
apache-2.0
18b6eddfcfa6b2a792f2cc7ed6e76052
0.327586
4.650334
false
false
false
false
quicky2000/IP_sharp_driver
sharp_driver.vhd
1
8,005
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; entity driver_sharp is port ( clk : in std_logic; -- Clock input rst : in std_logic; -- Reset input -- Signals to drive the screen vsync : out std_logic; hsync : out std_logic; enable : out std_logic; -- Signals to communicate with block giving color x_out : out std_logic_vector ( 9 downto 0); y_out : out std_logic_vector ( 8 downto 0) ); end driver_sharp; architecture behavorial of driver_sharp is -- Constants defined by specification constant THd : positive := 640; -- Width of display constant TVd : positive := 480; -- Height of display constant TH : positive := 799; -- Horizontal sync signal cycle width in clock cycle constant TV : positive := 524; -- Vertical sync signal period in clock cycle constant THp : positive := 95; -- Horizontal sync signal pulse width in clock cyle constant TVp : positive := 1; -- Vertical sync signal pulse width in hsync cyle constant TVs : positive := 34; -- Vertical start period in clock cycle -- Constants for internal use -- X axis constant x_counter_low : positive := 1024 - THp ; constant x_counter_low_start : positive := x_counter_low+1; -- constant x_counter_low_start : positive := x_counter_low; constant x_counter_valid : positive := 1024 - THd + 1; constant x_counter_fill : positive := 1024 - (TH - THp - THd) + 1; -- Y axis constant y_counter_low : positive := 512 - TVp + 1; constant y_counter_low_start : positive := y_counter_low; constant y_counter_pre_fill : positive := 512 - (TVs - TVp) + 1; constant y_counter_valid : positive := 512 - TVd + 1; constant y_counter_post_fill : positive := 512 - (TV - TVp - TVs - TVd + 1) ; -- Internal signals related to X axis signal x_counter: std_logic_vector( 10 downto 0) := std_logic_vector(to_unsigned(x_counter_low_start,11)); -- counter for x axis signal x_counter_init: std_logic_vector( 10 downto 0) := (others => '0'); signal hsyncP : std_logic := '0'; signal enableP : std_logic := '0'; type x_fsm_state_type is (x_low,x_valid,x_fill); signal x_fsm_stateP : x_fsm_state_type := x_low; signal x_fsm_stateN : x_fsm_state_type := x_valid; signal x : std_logic_vector(9 downto 0) := (others => '0'); -- Internal signals related to Y axis signal y_counter: std_logic_vector(9 downto 0) := std_logic_vector(to_unsigned(y_counter_low_start,10)); -- counter for x axis signal y_counter_init: std_logic_vector(9 downto 0) := (others => '0'); signal vsyncP : std_logic := '0'; type y_fsm_state_type is (y_low,y_pre_fill,y_valid,y_post_fill); signal y_fsm_stateP : y_fsm_state_type; signal y_fsm_stateN : y_fsm_state_type; signal y : std_logic_vector(8 downto 0) := (others => '0'); begin -- behavorial -- Process managing outputs output_management : process(clk,rst) begin if rst = '1' then hsync <= '0'; vsync <= '0'; enable <= '0'; x_out <= (others => '0'); y_out <= (others => '0'); elsif rising_edge(clk) then vsync <= vsyncP; hsync <= hsyncP; enable <= enableP; x_out <= x; y_out <= y; end if; end process; -- process managing x_counter increment x_counter_increment : process(clk,rst) begin if rst = '1' then x_counter <= std_logic_vector(to_unsigned(x_counter_low_start,11)); elsif rising_edge(clk) then if x_counter(10) = '1' then x_counter <= x_counter_init; else x_counter <= std_logic_vector(unsigned(x_counter)+1); end if; end if; end process; -- process computing x_counter_init prepare_x_counter_init : process (x_fsm_stateP) begin case x_fsm_stateP is when x_low => x_counter_init <= std_logic_vector(to_unsigned(x_counter_valid,11)); when x_valid => x_counter_init <= std_logic_vector(to_unsigned(x_counter_fill,11)); when x_fill => x_counter_init <= std_logic_vector(to_unsigned(x_counter_low,11)); when others => x_counter_init <= (others => '0'); end case; end process; -- process computing next x_fsm_state prepare_next_x_fsm_state : process (x_fsm_stateP) begin case x_fsm_stateP is when x_low => x_fsm_stateN <= x_valid; when x_valid => x_fsm_stateN <= x_fill; when x_fill => x_fsm_stateN <= x_low; when others => x_fsm_stateN <= x_low; end case; end process; -- process managing x_fsm_state register x_fsm_state_register : process(clk,rst) begin if rst = '1' then x_fsm_stateP <= x_low; elsif rising_edge(clk) then if x_counter(10) = '1' then x_fsm_stateP <= x_fsm_stateN; else x_fsm_stateP <= x_fsm_stateP; end if; end if; end process; apply_hsync : hsyncP <= '0' when x_fsm_stateP = x_low else '1'; -- process managing ycounter increment ycounter_increment : process(clk,rst) begin if rst = '1' then y_counter <= std_logic_vector(to_unsigned(y_counter_low_start,10)); elsif rising_edge(clk) then if x_counter(10) = '1' and x_fsm_stateP = x_fill then if y_counter(9) = '1' then y_counter <= y_counter_init; else y_counter <= std_logic_vector(unsigned(y_counter) + 1); end if; else y_counter <= y_counter; end if; end if; end process; -- prepare the init value for ycounter prepare_ycounter_init : process(y_fsm_stateP) begin case y_fsm_stateP is when y_low => y_counter_init <= std_logic_vector(to_unsigned(y_counter_pre_fill,10)); when y_pre_fill => y_counter_init <= std_logic_vector(to_unsigned(y_counter_valid,10)); when y_valid => y_counter_init <= std_logic_vector(to_unsigned(y_counter_post_fill,10)); when y_post_fill => y_counter_init <= std_logic_vector(to_unsigned(y_counter_low,10)); when others => y_counter_init <= std_logic_vector(to_unsigned(y_counter_low,10)); end case; end process; -- process computing next y_fsm_state vsync_state_transition_process : process(y_fsm_stateP) begin case y_fsm_stateP is when y_low => y_fsm_stateN <= y_pre_fill; when y_pre_fill => y_fsm_stateN <= y_valid; when y_valid => y_fsm_stateN <= y_post_fill; when y_post_fill => y_fsm_stateN <= y_low; when others => y_fsm_stateN <= y_low; end case; end process; -- process managing y_fsm_state_register y_fsm_state_register : process(clk,rst) begin if rst = '1' then y_fsm_stateP <= y_low; elsif rising_edge(clk) then if y_counter(9) = '1' and x_counter(10) = '1' and x_fsm_stateP = x_fill then y_fsm_stateP <= y_fsm_stateN; else y_fsm_stateP <= y_fsm_stateP; end if; end if; end process; --vsync output function apply_vsync : vsyncP <= '0' when y_fsm_stateP = y_low else '1'; -- enable output function apply_enable : enableP <= '1' when y_fsm_stateP = y_valid and x_fsm_stateP = x_valid else '0'; --process managing x increment x_increment : process(clk,rst) begin if rst = '1' then x <= (others => '0'); elsif rising_edge(clk) then if x_fsm_stateP = x_valid and y_fsm_statep = y_valid then if x_counter(10) = '0' then x <= std_logic_vector(unsigned(x) + 1); else x <= (others => '0'); end if; else x <= x; end if; end if; end process; -- process managing y increment y_increment : process(clk,rst) begin if rst = '1' then y <= (others => '0'); elsif rising_edge(clk) then if y_fsm_stateP = y_valid and x_fsm_stateP = x_fill then if x_counter(10) = '1'then if y_counter(9) = '0' then y <= std_logic_vector(unsigned(y) + 1); else y <= (others => '0'); end if; end if; else y <= y; end if; end if; end process; end behavorial;
gpl-3.0
e20dfc31aafdbf390b047eee4852310d
0.606371
3.196885
false
false
false
false
msiddalingaiah/TTA
VHDL/ArithmeticUnit.vhd
1
4,508
-------------------------------------------------------------------------------- -- Copyright 2014 Madhu Siddalingaiah -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -- Entity: ArithmeticUnit -- Date: 2014-12-02 -- Author: user -- -- Description: -------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; -- Avoid using ieee.std_logic_arith.all use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; entity ArithmeticUnit is generic ( DATA_WIDTH : integer := 16; ADDRESS_WIDTH : integer := 3; DEPTH : natural := 32 ); port ( reset : in std_logic; clock : in std_logic; address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0); data_in : in std_logic_vector(DATA_WIDTH-1 downto 0); data_out : out std_logic_vector(DATA_WIDTH-1 downto 0); read_enable : in std_logic; write_enable : in std_logic; busy : out std_logic ); end ArithmeticUnit; architecture arch of ArithmeticUnit is type StackType is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0); signal stack : StackType; signal s0 : std_logic_vector(DATA_WIDTH-1 downto 0); signal sp : std_logic_vector(10-1 downto 0); -- sp minus 1, avoids sp predecriment delay signal spm1 : std_logic_vector(10-1 downto 0); begin data_out <= s0; statemachine: block type state_type is (IDLE, RUNNING, DONE); signal state : state_type := IDLE; begin process(clock, reset) begin if reset = '1' then state <= IDLE; sp <= (others => '0'); spm1 <= (others => '1'); s0 <= (others => '0'); elsif rising_edge(clock) then case state is when IDLE => state <= RUNNING; when RUNNING => if read_enable = '1' then case to_integer(unsigned(address)) is -- pop when 0 => s0 <= stack(to_integer(unsigned(spm1))); sp <= sp - 1; spm1 <= spm1 - 1; when others => end case; elsif write_enable = '1' then case to_integer(unsigned(address)) is -- push when 0 => s0 <= data_in; stack(to_integer(unsigned(sp))) <= s0; sp <= sp + 1; spm1 <= spm1 + 1; -- operation when 1 => case to_integer(unsigned(data_in)) is -- add when 0 => s0 <= stack(to_integer(unsigned(spm1))) + s0; sp <= sp - 1; spm1 <= spm1 - 1; -- subtract when 1 => s0 <= stack(to_integer(unsigned(spm1))) - s0; sp <= sp - 1; spm1 <= spm1 - 1; when others => end case; when others => end case; end if; when DONE => state <= IDLE; when others => state <= IDLE; end case; end if; end process; end block; end arch;
apache-2.0
24afefab06d231fe27997e91828e832a
0.418811
4.970232
false
false
false
false
GSimas/EEL5105
Rep CAEE/11.2.Projeto/_PROJETO/consumo_combustivel.vhd
1
4,255
-- ALUNOS: -- Bruno Luiz da Silva -- Gustavo Fernades -- -- -- TÍTULO: -- Consumo instantâneo de combustível -- -- -- RESUMO: -- Calculará o consumo instantâneo de combustível de um carro -- -- -- ENTRADAS/SAÍDAS (I/O): -- (I) SW: oito chaves, cada uma de um bit, onde serão inseridos os dados (multiplicando, multiplicador -- e expoentes. -- (I) CLOCK_50: clock de 50 Mhz. -- (I) KEY: dois botões, sendo KEY(1) para realizar as operações e KEY(0) para dar reset nos dados. -- (O) LEDG: nove LEDs, sendo que LED(8) indicará se houve overflow ou não e os outros oite LEDs (7 -- downto 0) serão utilizados para exibir o valor da mantissa. -- (O) LEDR: quatro LEDs que serão utilizados para exibir o valor do expoente. -- -- -- DESCRIÇÃO: -- O usuário colocará um valor de oito bits inicialmente (multiplicando) e apertará o botão KEY(1) que -- amazenará tal valor no registrador de 8 bits. Após o usuário soltar o botão então o componente -- aguardará a inserção do outro valor (multiplicador) e consequente pressionamento de KEY(1). Após feito -- isso então o componente aguardará os valores dos expoentes, sendo de 4 bits cada e ambos serão inseridos -- nas mesmas chaves (SW). Para tal SW(7 downto 4) será um expoente e SW(3 downto 0) será outro. Assim que for -- apertado KEY(1) então as operações de multiplicação serão realizadas. Somará-se os dois expoentes, -- realizará-se o processo de multiplicação da mantissa e posterior normalização e por fim haverá a soma -- do número de deslocamentos que foram necessários na normalização com o atual valor da soma dos dois -- expoentes. Tem-se assim o valor final. Caso houver overflow ele será indicado em LEDG(8). As saídas serão -- representadas em LEDG(7 downto 0) - mantissa e LEDR - expoente. -- -- -- ANEXO: -- Todos os passos colocados na descrição são controlados por uma FSM e para maiores detalhes pode-se consultar -- o componente "fsm". Caso houver maior interesse no multiplicador ou no expoente então deve-se consultar -- "multiplicador" ou "expoente". -- -- -- (I): INPUT / (O): OUTPUT library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity consumo_combustivel is port( SW: in std_logic_vector(7 downto 0); CLOCK_50: in std_logic; KEY: in std_logic_vector(1 downto 0); LEDG: out std_logic_vector(8 downto 0); LEDR: out std_logic_vector(3 downto 0) ); end consumo_combustivel; architecture func of consumo_combustivel is component multiplicador is generic(N: natural := 8); port( a: in std_logic_vector((N-1) downto 0); -- Multiplicando e multiplicador arguments: in std_logic_vector(2 downto 0); -- Argumentos que dará as ordens para o componente clk,rst: in std_logic; -- Clock e reset q: out std_logic_vector(((2*N)-1) downto 0); -- Produto normalizado exp_nor: out std_logic_vector(3 downto 0) -- Expoente da normalização ); end component; component fsm is port( reg_control, press, clk, rst: in std_logic; argument: out std_logic_vector(2 downto 0) ); end component; component expoente is generic(N: natural := 4); port( a,b: in std_logic_vector((N-1) downto 0); -- Expoentes dados pelo usuário normal: in std_logic_vector((N-1) downto 0); -- Deslocamentos que foram necessários para normalizar a mantissa arguments: in std_logic_vector(2 downto 0); -- Argumentos que dará as ordens para o componente clk,rst: in std_logic; -- Clock e reset q: out std_logic_vector(N downto 0) -- Expoente ); end component; signal mantissa_out: std_logic_vector(15 downto 0); signal cntnormal_out, exp_nor_out: std_logic_vector(3 downto 0); signal exponent_out: std_logic_vector(4 downto 0); signal arg: std_logic_vector(2 downto 0); begin FSM_COMPONENT: fsm port map (mantissa_out(15), not(KEY(1)), CLOCK_50, not(KEY(0)), arg); MULTIPLICADOR_COMPONENT: multiplicador port map(SW(7 downto 0), arg, CLOCK_50, not(KEY(0)), mantissa_out, cntnormal_out); EXPOENTE_COMPONENT: expoente port map(SW(7 downto 4), SW(3 downto 0), cntnormal_out, arg, CLOCK_50, not(KEY(0)), exponent_out); LEDG(7 downto 0) <= mantissa_out(15 downto 8); -- Mantissa LEDR <= exponent_out(3 downto 0); -- Expoente LEDG(8)<= exponent_out(4); -- Overflow do expoente end func;
mit
b8f16175613c45626a00b315ab2e5450
0.713514
2.896528
false
false
false
false
tghaefli/ADD
EDK/IVK_Repos/IVK_IPLib/pcores/sg_2d_fir_plbw_v1_02_b/hdl/vhdl/sg_2d_fir_cw.vhd
2
26,710
------------------------------------------------------------------- -- System Generator version 13.2 VHDL source file. -- -- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- ------------------------------------------------------------------- -- System Generator version 13.2 VHDL source file. -- -- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; -- synopsys translate_off library unisim; use unisim.vcomponents.all; -- synopsys translate_on entity xlclockdriver is generic ( period: integer := 2; log_2_period: integer := 0; pipeline_regs: integer := 5; use_bufg: integer := 0 ); port ( sysclk: in std_logic; sysclr: in std_logic; sysce: in std_logic; clk: out std_logic; clr: out std_logic; ce: out std_logic; ce_logic: out std_logic ); end xlclockdriver; architecture behavior of xlclockdriver is component bufg port ( i: in std_logic; o: out std_logic ); end component; component synth_reg_w_init generic ( width: integer; init_index: integer; init_value: bit_vector; latency: integer ); port ( i: in std_logic_vector(width - 1 downto 0); ce: in std_logic; clr: in std_logic; clk: in std_logic; o: out std_logic_vector(width - 1 downto 0) ); end component; function size_of_uint(inp: integer; power_of_2: boolean) return integer is constant inp_vec: std_logic_vector(31 downto 0) := integer_to_std_logic_vector(inp,32, xlUnsigned); variable result: integer; begin result := 32; for i in 0 to 31 loop if inp_vec(i) = '1' then result := i; end if; end loop; if power_of_2 then return result; else return result+1; end if; end; function is_power_of_2(inp: std_logic_vector) return boolean is constant width: integer := inp'length; variable vec: std_logic_vector(width - 1 downto 0); variable single_bit_set: boolean; variable more_than_one_bit_set: boolean; variable result: boolean; begin vec := inp; single_bit_set := false; more_than_one_bit_set := false; -- synopsys translate_off if (is_XorU(vec)) then return false; end if; -- synopsys translate_on if width > 0 then for i in 0 to width - 1 loop if vec(i) = '1' then if single_bit_set then more_than_one_bit_set := true; end if; single_bit_set := true; end if; end loop; end if; if (single_bit_set and not(more_than_one_bit_set)) then result := true; else result := false; end if; return result; end; function ce_reg_init_val(index, period : integer) return integer is variable result: integer; begin result := 0; if ((index mod period) = 0) then result := 1; end if; return result; end; function remaining_pipe_regs(num_pipeline_regs, period : integer) return integer is variable factor, result: integer; begin factor := (num_pipeline_regs / period); result := num_pipeline_regs - (period * factor) + 1; return result; end; function sg_min(L, R: INTEGER) return INTEGER is begin if L < R then return L; else return R; end if; end; constant max_pipeline_regs : integer := 8; constant pipe_regs : integer := 5; constant num_pipeline_regs : integer := sg_min(pipeline_regs, max_pipeline_regs); constant rem_pipeline_regs : integer := remaining_pipe_regs(num_pipeline_regs,period); constant period_floor: integer := max(2, period); constant power_of_2_counter: boolean := is_power_of_2(integer_to_std_logic_vector(period_floor,32, xlUnsigned)); constant cnt_width: integer := size_of_uint(period_floor, power_of_2_counter); constant clk_for_ce_pulse_minus1: std_logic_vector(cnt_width - 1 downto 0) := integer_to_std_logic_vector((period_floor - 2),cnt_width, xlUnsigned); constant clk_for_ce_pulse_minus2: std_logic_vector(cnt_width - 1 downto 0) := integer_to_std_logic_vector(max(0,period - 3),cnt_width, xlUnsigned); constant clk_for_ce_pulse_minus_regs: std_logic_vector(cnt_width - 1 downto 0) := integer_to_std_logic_vector(max(0,period - rem_pipeline_regs),cnt_width, xlUnsigned); signal clk_num: unsigned(cnt_width - 1 downto 0) := (others => '0'); signal ce_vec : std_logic_vector(num_pipeline_regs downto 0); attribute MAX_FANOUT : string; attribute MAX_FANOUT of ce_vec:signal is "REDUCE"; signal ce_vec_logic : std_logic_vector(num_pipeline_regs downto 0); attribute MAX_FANOUT of ce_vec_logic:signal is "REDUCE"; signal internal_ce: std_logic_vector(0 downto 0); signal internal_ce_logic: std_logic_vector(0 downto 0); signal cnt_clr, cnt_clr_dly: std_logic_vector (0 downto 0); begin clk <= sysclk; clr <= sysclr; cntr_gen: process(sysclk) begin if sysclk'event and sysclk = '1' then if (sysce = '1') then if ((cnt_clr_dly(0) = '1') or (sysclr = '1')) then clk_num <= (others => '0'); else clk_num <= clk_num + 1; end if; end if; end if; end process; clr_gen: process(clk_num, sysclr) begin if power_of_2_counter then cnt_clr(0) <= sysclr; else if (unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus1 or sysclr = '1') then cnt_clr(0) <= '1'; else cnt_clr(0) <= '0'; end if; end if; end process; clr_reg: synth_reg_w_init generic map ( width => 1, init_index => 0, init_value => b"0000", latency => 1 ) port map ( i => cnt_clr, ce => sysce, clr => sysclr, clk => sysclk, o => cnt_clr_dly ); pipelined_ce : if period > 1 generate ce_gen: process(clk_num) begin if unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus_regs then ce_vec(num_pipeline_regs) <= '1'; else ce_vec(num_pipeline_regs) <= '0'; end if; end process; ce_pipeline: for index in num_pipeline_regs downto 1 generate ce_reg : synth_reg_w_init generic map ( width => 1, init_index => ce_reg_init_val(index, period), init_value => b"0000", latency => 1 ) port map ( i => ce_vec(index downto index), ce => sysce, clr => sysclr, clk => sysclk, o => ce_vec(index-1 downto index-1) ); end generate; internal_ce <= ce_vec(0 downto 0); end generate; pipelined_ce_logic: if period > 1 generate ce_gen_logic: process(clk_num) begin if unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus_regs then ce_vec_logic(num_pipeline_regs) <= '1'; else ce_vec_logic(num_pipeline_regs) <= '0'; end if; end process; ce_logic_pipeline: for index in num_pipeline_regs downto 1 generate ce_logic_reg : synth_reg_w_init generic map ( width => 1, init_index => ce_reg_init_val(index, period), init_value => b"0000", latency => 1 ) port map ( i => ce_vec_logic(index downto index), ce => sysce, clr => sysclr, clk => sysclk, o => ce_vec_logic(index-1 downto index-1) ); end generate; internal_ce_logic <= ce_vec_logic(0 downto 0); end generate; use_bufg_true: if period > 1 and use_bufg = 1 generate ce_bufg_inst: bufg port map ( i => internal_ce(0), o => ce ); ce_bufg_inst_logic: bufg port map ( i => internal_ce_logic(0), o => ce_logic ); end generate; use_bufg_false: if period > 1 and (use_bufg = 0) generate ce <= internal_ce(0); ce_logic <= internal_ce_logic(0); end generate; generate_system_clk: if period = 1 generate ce <= sysce; ce_logic <= sysce; end generate; end architecture behavior; ------------------------------------------------------------------- -- System Generator version 13.2 VHDL source file. -- -- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; entity xland2 is port ( a : in std_logic; b : in std_logic; dout : out std_logic ); end xland2; architecture behavior of xland2 is begin dout <= a and b; end behavior; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity default_clock_driver is port ( sysce: in std_logic; sysce_clr: in std_logic; sysclk: in std_logic; ce_1: out std_logic; ce_logic_1: out std_logic; clk_1: out std_logic ); end default_clock_driver; architecture structural of default_clock_driver is attribute syn_noprune: boolean; attribute syn_noprune of structural : architecture is true; attribute optimize_primitives: boolean; attribute optimize_primitives of structural : architecture is false; attribute dont_touch: boolean; attribute dont_touch of structural : architecture is true; signal sysce_clr_x0: std_logic; signal sysce_x0: std_logic; signal sysclk_x0: std_logic; signal xlclockdriver_1_ce: std_logic; signal xlclockdriver_1_ce_logic: std_logic; signal xlclockdriver_1_clk: std_logic; begin sysce_x0 <= sysce; sysce_clr_x0 <= sysce_clr; sysclk_x0 <= sysclk; ce_1 <= xlclockdriver_1_ce; ce_logic_1 <= xlclockdriver_1_ce_logic; clk_1 <= xlclockdriver_1_clk; xlclockdriver_1: entity work.xlclockdriver generic map ( log_2_period => 1, period => 1, use_bufg => 0 ) port map ( sysce => sysce_x0, sysclk => sysclk_x0, sysclr => sysce_clr_x0, ce => xlclockdriver_1_ce, ce_logic => xlclockdriver_1_ce_logic, clk => xlclockdriver_1_clk ); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity plb_clock_driver is port ( sysce: in std_logic; sysce_clr: in std_logic; sysclk: in std_logic; plb_ce_1: out std_logic; plb_clk_1: out std_logic ); end plb_clock_driver; architecture structural of plb_clock_driver is attribute syn_noprune: boolean; attribute syn_noprune of structural : architecture is true; attribute optimize_primitives: boolean; attribute optimize_primitives of structural : architecture is false; attribute dont_touch: boolean; attribute dont_touch of structural : architecture is true; signal sysce_clr_x0: std_logic; signal sysce_x0: std_logic; signal sysclk_x0: std_logic; signal xlclockdriver_1_ce: std_logic; signal xlclockdriver_1_clk: std_logic; begin sysce_x0 <= sysce; sysce_clr_x0 <= sysce_clr; sysclk_x0 <= sysclk; plb_ce_1 <= xlclockdriver_1_ce; plb_clk_1 <= xlclockdriver_1_clk; xlclockdriver_1: entity work.xlclockdriver generic map ( log_2_period => 1, period => 1, use_bufg => 0 ) port map ( sysce => sysce_x0, sysclk => sysclk_x0, sysclr => sysce_clr_x0, ce => xlclockdriver_1_ce, clk => xlclockdriver_1_clk ); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity sg_2d_fir_cw is port ( active_video_i: in std_logic; ce: in std_logic := '1'; clk: in std_logic; -- clock period = 10.0 ns (100.0 Mhz) hblank_i: in std_logic; hsync_i: in std_logic; plb_abus: in std_logic_vector(31 downto 0); plb_pavalid: in std_logic; plb_rnw: in std_logic; plb_wrdbus: in std_logic_vector(31 downto 0); reset: in std_logic; sg_plb_addrpref: in std_logic_vector(19 downto 0); splb_rst: in std_logic; vblank_i: in std_logic; video_data_i: in std_logic_vector(23 downto 0); vsync_i: in std_logic; xps_ce: in std_logic := '1'; xps_clk: in std_logic; -- clock period = 10.0 ns (100.0 Mhz) active_video_o: out std_logic; hblank_o: out std_logic; hsync_o: out std_logic; sl_addrack: out std_logic; sl_rdcomp: out std_logic; sl_rddack: out std_logic; sl_rddbus: out std_logic_vector(31 downto 0); sl_wait: out std_logic; sl_wrcomp: out std_logic; sl_wrdack: out std_logic; vblank_o: out std_logic; video_data_o: out std_logic_vector(23 downto 0); vsync_o: out std_logic ); end sg_2d_fir_cw; architecture structural of sg_2d_fir_cw is component block_memory_generator_spartan6_6_2_80846d0865f6122e port ( addra: in std_logic_vector(4 downto 0); addrb: in std_logic_vector(4 downto 0); clka: in std_logic; clkb: in std_logic; dina: in std_logic_vector(6 downto 0); dinb: in std_logic_vector(6 downto 0); ena: in std_logic; enb: in std_logic; wea: in std_logic_vector(0 downto 0); web: in std_logic_vector(0 downto 0); douta: out std_logic_vector(6 downto 0); doutb: out std_logic_vector(6 downto 0) ); end component; attribute syn_black_box: boolean; attribute syn_black_box of block_memory_generator_spartan6_6_2_80846d0865f6122e: component is true; attribute box_type: string; attribute box_type of block_memory_generator_spartan6_6_2_80846d0865f6122e: component is "black_box"; attribute syn_noprune: boolean; attribute optimize_primitives: boolean; attribute dont_touch: boolean; attribute syn_noprune of block_memory_generator_spartan6_6_2_80846d0865f6122e: component is true; attribute optimize_primitives of block_memory_generator_spartan6_6_2_80846d0865f6122e: component is false; attribute dont_touch of block_memory_generator_spartan6_6_2_80846d0865f6122e: component is true; component xlpersistentdff port ( clk: in std_logic; d: in std_logic; q: out std_logic ); end component; attribute syn_black_box of xlpersistentdff: component is true; attribute box_type of xlpersistentdff: component is "black_box"; attribute syn_noprune of xlpersistentdff: component is true; attribute optimize_primitives of xlpersistentdff: component is false; attribute dont_touch of xlpersistentdff: component is true; signal active_video_i_net: std_logic; signal active_video_o_net: std_logic; signal addr_net: std_logic_vector(4 downto 0); signal addr_x0_net: std_logic_vector(4 downto 0); signal ce_1_sg_x54: std_logic; attribute MAX_FANOUT: string; attribute MAX_FANOUT of ce_1_sg_x54: signal is "REDUCE"; signal ce_logic_1_sg_x25: std_logic; signal clkNet: std_logic; signal clkNet_x0: std_logic; signal clk_1_sg_x54: std_logic; signal coef_gain_reg_ce: std_logic; signal coef_update_reg_ce: std_logic; signal data_in_net: std_logic_vector(6 downto 0); signal data_in_x0_net: std_logic; signal data_in_x1_net: std_logic_vector(19 downto 0); signal data_in_x2_net: std_logic_vector(6 downto 0); signal data_out_net: std_logic_vector(19 downto 0); signal data_out_x0_net: std_logic; signal data_out_x1_net: std_logic_vector(6 downto 0); signal data_out_x2_net: std_logic_vector(6 downto 0); signal en_net: std_logic; signal en_x0_net: std_logic; signal hblank_i_net: std_logic; signal hblank_o_net: std_logic; signal hsync_i_net: std_logic; signal hsync_o_net: std_logic; signal persistentdff_inst_q: std_logic; attribute syn_keep: boolean; attribute syn_keep of persistentdff_inst_q: signal is true; attribute keep: boolean; attribute keep of persistentdff_inst_q: signal is true; attribute preserve_signal: boolean; attribute preserve_signal of persistentdff_inst_q: signal is true; signal plb_abus_net: std_logic_vector(31 downto 0); signal plb_ce_1_sg_x1: std_logic; attribute MAX_FANOUT of plb_ce_1_sg_x1: signal is "REDUCE"; signal plb_clk_1_sg_x1: std_logic; signal plb_pavalid_net: std_logic; signal plb_rnw_net: std_logic; signal plb_wrdbus_net: std_logic_vector(31 downto 0); signal reset_net: std_logic; signal sg_plb_addrpref_net: std_logic_vector(19 downto 0); signal sl_addrack_net: std_logic; signal sl_rdcomp_net: std_logic; signal sl_rddack_net: std_logic; signal sl_rddbus_net: std_logic_vector(31 downto 0); signal sl_wait_net: std_logic; signal sl_wrdack_x1: std_logic; signal sl_wrdack_x2: std_logic; signal splb_rst_net: std_logic; signal vblank_i_net: std_logic; signal vblank_o_net: std_logic; signal video_data_i_net: std_logic_vector(23 downto 0); signal video_data_o_net: std_logic_vector(23 downto 0); signal vsync_i_net: std_logic; signal vsync_o_net: std_logic; signal we_net: std_logic; signal we_x0_net: std_logic; begin active_video_i_net <= active_video_i; clkNet <= clk; hblank_i_net <= hblank_i; hsync_i_net <= hsync_i; plb_abus_net <= plb_abus; plb_pavalid_net <= plb_pavalid; plb_rnw_net <= plb_rnw; plb_wrdbus_net <= plb_wrdbus; reset_net <= reset; sg_plb_addrpref_net <= sg_plb_addrpref; splb_rst_net <= splb_rst; vblank_i_net <= vblank_i; video_data_i_net <= video_data_i; vsync_i_net <= vsync_i; clkNet_x0 <= xps_clk; active_video_o <= active_video_o_net; hblank_o <= hblank_o_net; hsync_o <= hsync_o_net; sl_addrack <= sl_addrack_net; sl_rdcomp <= sl_rdcomp_net; sl_rddack <= sl_rddack_net; sl_rddbus <= sl_rddbus_net; sl_wait <= sl_wait_net; sl_wrcomp <= sl_wrdack_x2; sl_wrdack <= sl_wrdack_x1; vblank_o <= vblank_o_net; video_data_o <= video_data_o_net; vsync_o <= vsync_o_net; coef_buffer: block_memory_generator_spartan6_6_2_80846d0865f6122e port map ( addra => addr_net, addrb => addr_x0_net, clka => clk_1_sg_x54, clkb => plb_clk_1_sg_x1, dina => data_in_net, dinb => data_in_x2_net, ena => ce_1_sg_x54, enb => plb_ce_1_sg_x1, wea(0) => we_net, web(0) => we_x0_net, douta => data_out_x1_net, doutb => data_out_x2_net ); coef_gain: entity work.synth_reg_w_init generic map ( width => 20, init_index => 2, init_value => b"11111111111111111111", latency => 1 ) port map ( ce => coef_gain_reg_ce, clk => plb_clk_1_sg_x1, clr => '0', i => data_in_x1_net, o => data_out_net ); coef_gain_ce_and2_comp: entity work.xland2 port map ( a => plb_ce_1_sg_x1, b => en_x0_net, dout => coef_gain_reg_ce ); coef_update: entity work.synth_reg_w_init generic map ( width => 1, init_index => 2, init_value => b"1", latency => 1 ) port map ( ce => coef_update_reg_ce, clk => plb_clk_1_sg_x1, clr => '0', i(0) => data_in_x0_net, o(0) => data_out_x0_net ); coef_update_ce_and2_comp: entity work.xland2 port map ( a => plb_ce_1_sg_x1, b => en_net, dout => coef_update_reg_ce ); default_clock_driver_x0: entity work.default_clock_driver port map ( sysce => '1', sysce_clr => '0', sysclk => clkNet, ce_1 => ce_1_sg_x54, ce_logic_1 => ce_logic_1_sg_x25, clk_1 => clk_1_sg_x54 ); persistentdff_inst: xlpersistentdff port map ( clk => clkNet, d => persistentdff_inst_q, q => persistentdff_inst_q ); plb_clock_driver_x0: entity work.plb_clock_driver port map ( sysce => '1', sysce_clr => '0', sysclk => clkNet_x0, plb_ce_1 => plb_ce_1_sg_x1, plb_clk_1 => plb_clk_1_sg_x1 ); sg_2d_fir_x0: entity work.sg_2d_fir port map ( active_video_i => active_video_i_net, ce_1 => ce_1_sg_x54, ce_logic_1 => ce_logic_1_sg_x25, clk_1 => clk_1_sg_x54, data_out => data_out_net, data_out_x0 => data_out_x0_net, data_out_x1 => data_out_x1_net, data_out_x2 => data_out_x2_net, dout => data_out_x0_net, dout_x0 => data_out_net, hblank_i => hblank_i_net, hsync_i => hsync_i_net, plb_abus => plb_abus_net, plb_ce_1 => plb_ce_1_sg_x1, plb_clk_1 => plb_clk_1_sg_x1, plb_pavalid => plb_pavalid_net, plb_rnw => plb_rnw_net, plb_wrdbus => plb_wrdbus_net, reset => reset_net, sg_plb_addrpref => sg_plb_addrpref_net, splb_rst => splb_rst_net, vblank_i => vblank_i_net, video_data_i => video_data_i_net, vsync_i => vsync_i_net, active_video_o => active_video_o_net, addr => addr_net, addr_x0 => addr_x0_net, data_in => data_in_net, data_in_x0 => data_in_x0_net, data_in_x1 => data_in_x1_net, data_in_x2 => data_in_x2_net, en => en_net, en_x0 => en_x0_net, hblank_o => hblank_o_net, hsync_o => hsync_o_net, sl_addrack => sl_addrack_net, sl_rdcomp => sl_rdcomp_net, sl_rddack => sl_rddack_net, sl_rddbus => sl_rddbus_net, sl_wait => sl_wait_net, sl_wrcomp => sl_wrdack_x2, sl_wrdack => sl_wrdack_x1, vblank_o => vblank_o_net, video_data_o => video_data_o_net, vsync_o => vsync_o_net, we => we_net, we_x0 => we_x0_net ); end structural;
gpl-3.0
08c9b4d60bafa3ef1f164e9df2400c11
0.634107
3.399516
false
false
false
false
bertuccio/ARQ
Practica5/HazardUnit.vhd
2
797
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity Hazard is Port ( PC_Write : out STD_LOGIC; IFID_Write : out STD_LOGIC; IDEX_Memread : in STD_LOGIC; MUX_sel : out STD_LOGIC; IDEX_Rt : in STD_LOGIC_VECTOR (4 downto 0); IFID_Rs : in STD_LOGIC_VECTOR (4 downto 0); IFID_Rt : in STD_LOGIC_VECTOR (4 downto 0)); end Hazard; architecture Behavioral of HAZARD is begin process(IDEX_Memread,IFID_Rs,IFID_Rt,IDEX_Rt) begin if IDEX_Memread='1' AND (IDEX_Rt=IFID_Rs OR IDEX_Rt=IFID_Rt) then PC_Write<='0'; IFID_Write<='0'; Mux_sel<='1'; else PC_Write<='1'; IFID_Write<='1'; Mux_sel<='0'; end if; end process; end Behavioral;
mit
83c668da2b23af0cbc3854b9e5f7f9b2
0.604768
2.877256
false
false
false
false
tghaefli/ADD
ISE/FMC_waj/tb_mcu.vhd
1
802
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.mcu_pkg.all; entity tb_mcu is end tb_mcu; architecture TB of tb_mcu is signal rst : std_logic := '1'; signal clk : std_logic := '0'; signal Switch : std_logic_vector(3 downto 0); signal LED : std_logic_vector(7 downto 0); constant SIM_CF : natural := CF/10; -- 50 MHz/10 for simulation begin -- instantiate MUT MUT : entity work.mcu generic map(CLK_FRQ => SIM_CF) port map( rst => rst, clk => clk, LED => LED, Switch => Switch ); -- generate reset rst <= '1', '0' after 5us; -- clock generation p_clk: process begin wait for 1 sec / SIM_CF/2; clk <= not clk; end process; end TB;
gpl-3.0
1b683d9bdbdadd756b781ccaff56b0d6
0.55985
3.273469
false
false
false
false
tghaefli/ADD
ISE/FMC/gpio.vhd
1
3,716
------------------------------------------------------------------------------- -- Entity: fmc_top -- Author: Sandro Arnold ------------------------------------------------------------------------------- -- Description: Testatübung ADD -- FMC Block for Floppy Music Controller. ------------------------------------------------------------------------------- -- Total # of FFs: ... tbd ... ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.mcu_pkg.all; entity gpio is port(rst : in std_logic; clk : in std_logic; -- GPIO bus signals bus_in : in t_bus2rws; bus_out : out t_rws2bus; -- GPIO pin signals gpio_in : in std_logic_vector(DW-1 downto 0); gpio_out : out std_logic_vector(DW-1 downto 0); gpio_out_enb : out std_logic_vector(DW-1 downto 0) ); end gpio; architecture rtl of gpio is -- address select signal signal addr_sel : t_gpio_addr_sel; -- peripheral registers signal data_in_reg : std_logic_vector(DW-1 downto 0); signal data_out_reg : std_logic_vector(DW-1 downto 0); signal out_enb_reg : std_logic_vector(DW-1 downto 0); begin -- output ssignment gpio_out <= data_out_reg; gpio_out_enb <= out_enb_reg; ----------------------------------------------------------------------------- -- Input register ----------------------------------------------------------------------------- P_in: process(clk) begin if rising_edge(clk) then data_in_reg <= gpio_in; end if; end process; ----------------------------------------------------------------------------- -- Address Decoding (combinationally) ----------------------------------------------------------------------------- process(bus_in.addr) begin case bus_in.addr is -- Port 1 addresses ----------------------------------------------------- when c_addr_gpio_data_in => addr_sel <= gpio_data_in; when c_addr_gpio_data_out => addr_sel <= gpio_data_out; when c_addr_gpio_out_enb => addr_sel <= gpio_enb; -- unused addresses ----------------------------------------------------- when others => addr_sel <= none; end case; end process; ----------------------------------------------------------------------------- -- Read Access (R and R/W registers) ----------------------------------------------------------------------------- P_read: process(clk) begin if rising_edge(clk) then -- default assignment bus_out.data <= (others => '0'); -- use address select signal case addr_sel is when gpio_data_in => bus_out.data <= data_in_reg; when gpio_data_out => bus_out.data <= data_out_reg; when gpio_enb => bus_out.data <= out_enb_reg; when others => null; end case; end if; end process; ----------------------------------------------------------------------------- -- Write Access (R/W regsiters only) ----------------------------------------------------------------------------- P_write: process(clk, rst) begin if rst = '1' then data_out_reg <= (others => '0'); out_enb_reg <= (others => '0'); -- output disabled per default elsif rising_edge(clk) then if bus_in.wr_enb = '1' then -- use address select signal case addr_sel is when gpio_data_out => data_out_reg <= bus_in.data; when gpio_enb => out_enb_reg <= bus_in.data; when others => null; end case; end if; end if; end process; end rtl;
gpl-3.0
2b4d53598921394f6ea248405ba6c4fd
0.411464
4.455635
false
false
false
false
tghaefli/ADD
ISE/FMC_waj/mcu.vhd
1
5,075
------------------------------------------------------------------------------- -- Entity: mcu -- Author: Waj -- Date : 11-May-13 ------------------------------------------------------------------------------- -- Description: (ECS Uebung 9) -- Top-level description of a simple von-Neumann MCU. -- All top-level component are instantiated here. Also, tri-state buffers for -- bi-directional GPIO pins are described here. ------------------------------------------------------------------------------- -- Total # of FFs: 0 ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.mcu_pkg.all; entity mcu is generic(CLK_FRQ : natural := CF ); port(rst : in std_logic; clk : in std_logic; -- LED(8:0) on S3E-Board (demonstrate tri-state buffers) LED : inout std_logic_vector(7 downto 0); -- SW(3:0) on S3E-Board Switch : in std_logic_vector(3 downto 0); -- 3 pins per FMC channels fmc_enable : out std_logic_vector(FMC_NUM_CHN-1 downto 0); fmc_direct : out std_logic_vector(FMC_NUM_CHN-1 downto 0); fmc_step : out std_logic_vector(FMC_NUM_CHN-1 downto 0) ); end mcu; architecture rtl of mcu is -- CPU signals signal cpu2bus : t_cpu2bus; signal bus2cpu : t_bus2cpu; -- ROM signals signal bus2rom : t_bus2ros; signal rom2bus : t_ros2bus; -- ROM signals signal bus2ram : t_bus2rws; signal ram2bus : t_rws2bus; -- GPIO signals signal bus2gpio : t_bus2rws; signal gpio2bus : t_rws2bus; signal gpio_in : std_logic_vector(DW-1 downto 0); signal gpio_out : std_logic_vector(DW-1 downto 0); signal gpio_out_enb : std_logic_vector(DW-1 downto 0); -- FMC signals signal bus2fmc : t_bus2rws; signal fmc2bus : t_rws2bus; begin ----------------------------------------------------------------------------- -- Connect GPIO(7:0) to LED(7:0) -- Demonstrates the usage of tri-state buffers although this not required for -- LED functionality. ----------------------------------------------------------------------------- gpio_in(7 downto 0) <= LED; gen_led_3state: for k in 0 to 7 generate LED(k) <= gpio_out(k) when gpio_out_enb(k) = '1' else 'Z'; end generate; ----------------------------------------------------------------------------- -- Connect SW(3:0) to GPIO(11:8) -- NOTE: GPIO(11:8) is only connected as input, since the SITE TYPE of the 4 -- Switch pins is IBUF, which prevents the usage of tri-state IOBs. -- Furthermore, even if IOBs were available, it would be dangerous to -- use them here, since a wrong SW configuration could then cause -- driver conflicts on these pins!! ----------------------------------------------------------------------------- gpio_in(11 downto 8) <= Switch; -- gen_sw_3state: for k in 8 to 11 generate -- SW(k-8) <= gpio_out(k) when gpio_out_enb(k) = '1' else 'Z'; -- end generate; ----------------------------------------------------------------------------- -- Instantiation of top-level components (assumed to be in library work) ----------------------------------------------------------------------------- -- CPU ---------------------------------------------------------------------- i_cpu: entity work.cpu port map( rst => rst, clk => clk, bus_in => bus2cpu, bus_out => cpu2bus ); -- BUS ---------------------------------------------------------------------- i_bus: entity work.buss port map( rst => rst, clk => clk, cpu_in => cpu2bus, cpu_out => bus2cpu, rom_in => rom2bus, rom_out => bus2rom, ram_in => ram2bus, ram_out => bus2ram, gpio_in => gpio2bus, gpio_out => bus2gpio, fmc_in => fmc2bus, fmc_out => bus2fmc ); -- ROM ---------------------------------------------------------------------- i_rom: entity work.rom port map( clk => clk, bus_in => bus2rom, bus_out => rom2bus ); -- RAM ---------------------------------------------------------------------- i_ram: entity work.ram port map( clk => clk, bus_in => bus2ram, bus_out => ram2bus ); -- GPIO --------------------------------------------------------------------- i_gpio: entity work.gpio port map( rst => rst, clk => clk, bus_in => bus2gpio, bus_out => gpio2bus, gpio_in => gpio_in, gpio_out => gpio_out, gpio_out_enb => gpio_out_enb ); -- FMC ---------------------------------------------------------------------- i_fmc: entity work.fmc_top generic map(CLK_FRQ => CLK_FRQ) port map( rst => rst, clk => clk, bus_in => bus2fmc, bus_out => fmc2bus, fmc_enable => fmc_enable, fmc_direct => fmc_direct, fmc_step => fmc_step ); end rtl;
gpl-3.0
6ff02acc9b0977065d18d199dc238196
0.435468
4.037391
false
false
false
false
GSimas/EEL5105
Eletr-Digital/Relatório4/Controle de Motor de Passo/divisor100.vhd
1
4,587
-- megafunction wizard: %LPM_COUNTER% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: lpm_counter -- ============================================================ -- File Name: divisor100.vhd -- Megafunction Name(s): -- lpm_counter -- -- Simulation Library Files(s): -- lpm -- ============================================================ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- -- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition -- ************************************************************ --Copyright (C) 1991-2010 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject --to the terms and conditions of the Altera Program License --Subscription Agreement, Altera MegaCore Function License --Agreement, or other applicable license agreement, including, --without limitation, that your use is for the sole purpose of --programming logic devices manufactured by Altera and sold by --Altera or its authorized distributors. Please refer to the --applicable agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY lpm; USE lpm.all; ENTITY divisor100 IS PORT ( clock : IN STD_LOGIC ; cout : OUT STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (29 DOWNTO 0) ); END divisor100; ARCHITECTURE SYN OF divisor100 IS SIGNAL sub_wire0 : STD_LOGIC ; SIGNAL sub_wire1 : STD_LOGIC_VECTOR (29 DOWNTO 0); COMPONENT lpm_counter GENERIC ( lpm_direction : STRING; lpm_modulus : NATURAL; lpm_port_updown : STRING; lpm_type : STRING; lpm_width : NATURAL ); PORT ( clock : IN STD_LOGIC ; cout : OUT STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (29 DOWNTO 0) ); END COMPONENT; BEGIN cout <= sub_wire0; q <= sub_wire1(29 DOWNTO 0); lpm_counter_component : lpm_counter GENERIC MAP ( lpm_direction => "UP", lpm_modulus => 250000, lpm_port_updown => "PORT_UNUSED", lpm_type => "LPM_COUNTER", lpm_width => 30 ) PORT MAP ( clock => clock, cout => sub_wire0, q => sub_wire1 ); END SYN; -- ============================================================ -- CNX file retrieval info -- ============================================================ -- Retrieval info: PRIVATE: ACLR NUMERIC "0" -- Retrieval info: PRIVATE: ALOAD NUMERIC "0" -- Retrieval info: PRIVATE: ASET NUMERIC "0" -- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1" -- Retrieval info: PRIVATE: CLK_EN NUMERIC "0" -- Retrieval info: PRIVATE: CNT_EN NUMERIC "0" -- Retrieval info: PRIVATE: CarryIn NUMERIC "0" -- Retrieval info: PRIVATE: CarryOut NUMERIC "1" -- Retrieval info: PRIVATE: Direction NUMERIC "0" -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" -- Retrieval info: PRIVATE: ModulusCounter NUMERIC "1" -- Retrieval info: PRIVATE: ModulusValue NUMERIC "250000" -- Retrieval info: PRIVATE: SCLR NUMERIC "0" -- Retrieval info: PRIVATE: SLOAD NUMERIC "0" -- Retrieval info: PRIVATE: SSET NUMERIC "0" -- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: nBit NUMERIC "30" -- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP" -- Retrieval info: CONSTANT: LPM_MODULUS NUMERIC "250000" -- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER" -- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "30" -- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock -- Retrieval info: USED_PORT: cout 0 0 0 0 OUTPUT NODEFVAL cout -- Retrieval info: USED_PORT: q 0 0 30 0 OUTPUT NODEFVAL q[29..0] -- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 -- Retrieval info: CONNECT: q 0 0 30 0 @q 0 0 30 0 -- Retrieval info: CONNECT: cout 0 0 0 0 @cout 0 0 0 0 -- Retrieval info: LIBRARY: lpm lpm.lpm_components.all -- Retrieval info: GEN_FILE: TYPE_NORMAL divisor100.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL divisor100.inc TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL divisor100.cmp TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL divisor100.bsf TRUE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL divisor100_inst.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL divisor100_waveforms.html TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL divisor100_wave*.jpg FALSE -- Retrieval info: LIB_FILE: lpm
mit
2fb5d3b7b78e703de99424727858ac67
0.65751
3.723214
false
false
false
false
GSimas/EEL5105
Eletr-Digital/Projeto Final/PROJETO COFRE FUNCIONANDO/clock1hz.vhd
1
4,565
-- megafunction wizard: %LPM_COUNTER% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: lpm_counter -- ============================================================ -- File Name: clock1hz.vhd -- Megafunction Name(s): -- lpm_counter -- -- Simulation Library Files(s): -- lpm -- ============================================================ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- -- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition -- ************************************************************ --Copyright (C) 1991-2010 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject --to the terms and conditions of the Altera Program License --Subscription Agreement, Altera MegaCore Function License --Agreement, or other applicable license agreement, including, --without limitation, that your use is for the sole purpose of --programming logic devices manufactured by Altera and sold by --Altera or its authorized distributors. Please refer to the --applicable agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY lpm; USE lpm.all; ENTITY clock1hz IS PORT ( clock : IN STD_LOGIC ; cout : OUT STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (29 DOWNTO 0) ); END clock1hz; ARCHITECTURE SYN OF clock1hz IS SIGNAL sub_wire0 : STD_LOGIC ; SIGNAL sub_wire1 : STD_LOGIC_VECTOR (29 DOWNTO 0); COMPONENT lpm_counter GENERIC ( lpm_direction : STRING; lpm_modulus : NATURAL; lpm_port_updown : STRING; lpm_type : STRING; lpm_width : NATURAL ); PORT ( clock : IN STD_LOGIC ; cout : OUT STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (29 DOWNTO 0) ); END COMPONENT; BEGIN cout <= sub_wire0; q <= sub_wire1(29 DOWNTO 0); lpm_counter_component : lpm_counter GENERIC MAP ( lpm_direction => "UP", lpm_modulus => 200000, lpm_port_updown => "PORT_UNUSED", lpm_type => "LPM_COUNTER", lpm_width => 30 ) PORT MAP ( clock => clock, cout => sub_wire0, q => sub_wire1 ); END SYN; -- ============================================================ -- CNX file retrieval info -- ============================================================ -- Retrieval info: PRIVATE: ACLR NUMERIC "0" -- Retrieval info: PRIVATE: ALOAD NUMERIC "0" -- Retrieval info: PRIVATE: ASET NUMERIC "0" -- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1" -- Retrieval info: PRIVATE: CLK_EN NUMERIC "0" -- Retrieval info: PRIVATE: CNT_EN NUMERIC "0" -- Retrieval info: PRIVATE: CarryIn NUMERIC "0" -- Retrieval info: PRIVATE: CarryOut NUMERIC "1" -- Retrieval info: PRIVATE: Direction NUMERIC "0" -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" -- Retrieval info: PRIVATE: ModulusCounter NUMERIC "1" -- Retrieval info: PRIVATE: ModulusValue NUMERIC "200000" -- Retrieval info: PRIVATE: SCLR NUMERIC "0" -- Retrieval info: PRIVATE: SLOAD NUMERIC "0" -- Retrieval info: PRIVATE: SSET NUMERIC "0" -- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: nBit NUMERIC "30" -- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP" -- Retrieval info: CONSTANT: LPM_MODULUS NUMERIC "200000" -- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER" -- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "30" -- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock -- Retrieval info: USED_PORT: cout 0 0 0 0 OUTPUT NODEFVAL cout -- Retrieval info: USED_PORT: q 0 0 30 0 OUTPUT NODEFVAL q[29..0] -- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 -- Retrieval info: CONNECT: q 0 0 30 0 @q 0 0 30 0 -- Retrieval info: CONNECT: cout 0 0 0 0 @cout 0 0 0 0 -- Retrieval info: LIBRARY: lpm lpm.lpm_components.all -- Retrieval info: GEN_FILE: TYPE_NORMAL clock1hz.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL clock1hz.inc TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL clock1hz.cmp TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL clock1hz.bsf TRUE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL clock1hz_inst.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL clock1hz_waveforms.html TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL clock1hz_wave*.jpg FALSE -- Retrieval info: LIB_FILE: lpm
mit
505914fe9d04102bace11ed1a29c95d0
0.65586
3.672566
false
false
false
false
arteymix/lmc
lmc.vhd
1
5,195
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity lmc is port( clk: in std_logic; rst: in std_logic; input: in signed(11 downto 0); output: out signed(11 downto 0) := x"000"; input_warn: out std_logic; output_warn: out std_logic; halt_warn: out std_logic ); end entity; architecture lmc of lmc is subtype word_t is std_logic_vector(11 downto 0); subtype instruction_t is std_logic_vector(3 downto 0); type memory_t is array(255 downto 0) of word_t; constant HLT: instruction_t := x"0"; -- halt (coffee break) constant ADD: instruction_t := x"1"; -- add constant SUB: instruction_t := x"2"; constant STA: instruction_t := x"3"; constant NOP: instruction_t := x"4"; constant LDA: instruction_t := x"5"; constant BRA: instruction_t := x"6"; constant BRZ: instruction_t := x"7"; constant BRP: instruction_t := x"8"; constant IO: instruction_t := x"9"; -- 901 in, 902 out signal memory: memory_t := ( 0 => x"901", 1 => x"1FF", 2 => x"902", 3 => x"901", 4 => x"2FF", 5 => x"902", 6 => x"901", 7 => x"3F0", 8 => x"901", 9 => x"400", 10 => x"5F0", 11 => x"902", 12 => x"901", 13 => x"70C", 14 => x"5FE", 15 => x"902", 16 => x"901", 17 => x"810", 18 => x"5FD", 19 => x"902", 20 => x"600", -- data 253 => x"00A", -- fd 254 => x"00B", -- fe 255 => x"005", -- ff others => x"000" ); signal ordinal_counter: unsigned(7 downto 0) := x"00"; signal accumulator: signed(11 downto 0) := x"000"; signal instruction_register: word_t := memory(to_integer(ordinal_counter)); signal instruction: instruction_t := instruction_register(11 downto 8); signal address: unsigned(7 downto 0) := unsigned(instruction_register(7 downto 0)); begin instruction_register <= memory(to_integer(ordinal_counter)); instruction <= instruction_register(11 downto 8); address <= unsigned(instruction_register(7 downto 0)); -- output combinatory input_warn <= '1' when instruction = IO and address = x"01" else '0'; output_warn <= '1' when instruction = IO and address = x"02" else '0'; halt_warn <= '1' when instruction = HLT else '0'; output <= accumulator when instruction = IO and address = x"02" else x"000"; process (clk, rst) is begin if rst = '0' then -- le reset est inversé avec KEY1 ordinal_counter <= x"00"; accumulator <= x"000"; elsif falling_edge(clk) then -- l'horloge est inversé avec KEY0 case instruction is when HLT => -- terminate the program (counter will not increase) report "Program halted." severity NOTE; when ADD => accumulator <= accumulator + signed(memory(to_integer(address))); ordinal_counter <= ordinal_counter + 1; when SUB => accumulator <= accumulator - signed(memory(to_integer(address))); ordinal_counter <= ordinal_counter + 1; when LDA => accumulator <= signed(memory(to_integer(address))); ordinal_counter <= ordinal_counter + 1; when NOP => ordinal_counter <= ordinal_counter + 1; when STA => memory(to_integer(address)) <= std_logic_vector(accumulator); ordinal_counter <= ordinal_counter + 1; when BRA => ordinal_counter <= address; when BRZ => if accumulator = 0 then ordinal_counter <= address; else ordinal_counter <= ordinal_counter + 1; end if; when BRP => if accumulator >= 0 then ordinal_counter <= address; else ordinal_counter <= ordinal_counter + 1; end if; when IO => case address is when x"01" => -- 901 accumulator <= input; when x"02" => -- 902 null; -- gérée dans la combinatoire de l'output when others => assert FALSE report "Illegal i/o instruction." severity ERROR; end case; ordinal_counter <= ordinal_counter + 1; when others => assert FALSE report "Illegal instruction." severity ERROR; end case; end if; end process; end architecture;
bsd-3-clause
a19699b53f89b1e9073fa8ff55f7cd74
0.474668
4.261905
false
false
false
false