repo_name
stringlengths 6
79
| path
stringlengths 6
236
| copies
int64 1
472
| size
int64 137
1.04M
| content
stringlengths 137
1.04M
| license
stringclasses 15
values | hash
stringlengths 32
32
| alpha_frac
float64 0.25
0.96
| ratio
float64 1.51
17.5
| autogenerated
bool 1
class | config_or_test
bool 2
classes | has_no_keywords
bool 1
class | has_few_assignments
bool 1
class |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
MAV-RT-testbed/MAV-testbed | Syma_Flight_Final/Syma_Flight_Final.srcs/sources_1/bd/Test_AXI_Master_simple_v1_0_hw_1/ip/Test_AXI_Master_simple_v1_0_hw_1_axi_quad_spi_0_0_2/synth/Test_AXI_Master_simple_v1_0_hw_1_axi_quad_spi_0_0.vhd | 1 | 15,819 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_quad_spi:3.2
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_quad_spi_v3_2;
USE axi_quad_spi_v3_2.axi_quad_spi;
ENTITY Test_AXI_Master_simple_v1_0_hw_1_axi_quad_spi_0_0 IS
PORT (
ext_spi_clk : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
io0_i : IN STD_LOGIC;
io0_o : OUT STD_LOGIC;
io0_t : OUT STD_LOGIC;
io1_i : IN STD_LOGIC;
io1_o : OUT STD_LOGIC;
io1_t : OUT STD_LOGIC;
sck_i : IN STD_LOGIC;
sck_o : OUT STD_LOGIC;
sck_t : OUT STD_LOGIC;
ss_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_t : OUT STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC
);
END Test_AXI_Master_simple_v1_0_hw_1_axi_quad_spi_0_0;
ARCHITECTURE Test_AXI_Master_simple_v1_0_hw_1_axi_quad_spi_0_0_arch OF Test_AXI_Master_simple_v1_0_hw_1_axi_quad_spi_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF Test_AXI_Master_simple_v1_0_hw_1_axi_quad_spi_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_quad_spi IS
GENERIC (
Async_Clk : INTEGER;
C_FAMILY : STRING;
C_SUB_FAMILY : STRING;
C_INSTANCE : STRING;
C_SPI_MEM_ADDR_BITS : INTEGER;
C_TYPE_OF_AXI4_INTERFACE : INTEGER;
C_XIP_MODE : INTEGER;
C_FIFO_DEPTH : INTEGER;
C_SCK_RATIO : INTEGER;
C_NUM_SS_BITS : INTEGER;
C_NUM_TRANSFER_BITS : INTEGER;
C_SPI_MODE : INTEGER;
C_USE_STARTUP : INTEGER;
C_SPI_MEMORY : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI4_ADDR_WIDTH : INTEGER;
C_S_AXI4_DATA_WIDTH : INTEGER;
C_S_AXI4_ID_WIDTH : INTEGER;
C_S_AXI4_BASEADDR : STD_LOGIC_VECTOR;
C_S_AXI4_HIGHADDR : STD_LOGIC_VECTOR
);
PORT (
ext_spi_clk : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi4_aclk : IN STD_LOGIC;
s_axi4_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi4_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi4_awaddr : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axi4_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi4_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_awlock : IN STD_LOGIC;
s_axi4_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi4_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_awvalid : IN STD_LOGIC;
s_axi4_awready : OUT STD_LOGIC;
s_axi4_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi4_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi4_wlast : IN STD_LOGIC;
s_axi4_wvalid : IN STD_LOGIC;
s_axi4_wready : OUT STD_LOGIC;
s_axi4_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi4_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_bvalid : OUT STD_LOGIC;
s_axi4_bready : IN STD_LOGIC;
s_axi4_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi4_araddr : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axi4_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi4_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_arlock : IN STD_LOGIC;
s_axi4_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi4_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_arvalid : IN STD_LOGIC;
s_axi4_arready : OUT STD_LOGIC;
s_axi4_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi4_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi4_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_rlast : OUT STD_LOGIC;
s_axi4_rvalid : OUT STD_LOGIC;
s_axi4_rready : IN STD_LOGIC;
io0_i : IN STD_LOGIC;
io0_o : OUT STD_LOGIC;
io0_t : OUT STD_LOGIC;
io1_i : IN STD_LOGIC;
io1_o : OUT STD_LOGIC;
io1_t : OUT STD_LOGIC;
io2_i : IN STD_LOGIC;
io2_o : OUT STD_LOGIC;
io2_t : OUT STD_LOGIC;
io3_i : IN STD_LOGIC;
io3_o : OUT STD_LOGIC;
io3_t : OUT STD_LOGIC;
spisel : IN STD_LOGIC;
sck_i : IN STD_LOGIC;
sck_o : OUT STD_LOGIC;
sck_t : OUT STD_LOGIC;
ss_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_t : OUT STD_LOGIC;
cfgclk : OUT STD_LOGIC;
cfgmclk : OUT STD_LOGIC;
eos : OUT STD_LOGIC;
preq : OUT STD_LOGIC;
di : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
ip2intc_irpt : OUT STD_LOGIC
);
END COMPONENT axi_quad_spi;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF Test_AXI_Master_simple_v1_0_hw_1_axi_quad_spi_0_0_arch: ARCHITECTURE IS "axi_quad_spi,Vivado 2014.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF Test_AXI_Master_simple_v1_0_hw_1_axi_quad_spi_0_0_arch : ARCHITECTURE IS "Test_AXI_Master_simple_v1_0_hw_1_axi_quad_spi_0_0,axi_quad_spi,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF Test_AXI_Master_simple_v1_0_hw_1_axi_quad_spi_0_0_arch: ARCHITECTURE IS "Test_AXI_Master_simple_v1_0_hw_1_axi_quad_spi_0_0,axi_quad_spi,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_quad_spi,x_ipVersion=3.2,x_ipCoreRevision=2,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,Async_Clk=1,C_FAMILY=zynq,C_SUB_FAMILY=zynq,C_INSTANCE=axi_quad_spi_inst,C_SPI_MEM_ADDR_BITS=24,C_TYPE_OF_AXI4_INTERFACE=0,C_XIP_MODE=0,C_FIFO_DEPTH=16,C_SCK_RATIO=32,C_NUM_SS_BITS=1,C_NUM_TRANSFER_BITS=8,C_SPI_MODE=0,C_USE_STARTUP=0,C_SPI_MEMORY=1,C_S_AXI_ADDR_WIDTH=7,C_S_AXI_DATA_WIDTH=32,C_S_AXI4_ADDR_WIDTH=24,C_S_AXI4_DATA_WIDTH=32,C_S_AXI4_ID_WIDTH=1,C_S_AXI4_BASEADDR=0xFFFFFFFF,C_S_AXI4_HIGHADDR=0x00000000}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF ext_spi_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 spi_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 lite_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 lite_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RREADY";
ATTRIBUTE X_INTERFACE_INFO OF io0_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO0_I";
ATTRIBUTE X_INTERFACE_INFO OF io0_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO0_O";
ATTRIBUTE X_INTERFACE_INFO OF io0_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO0_T";
ATTRIBUTE X_INTERFACE_INFO OF io1_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO1_I";
ATTRIBUTE X_INTERFACE_INFO OF io1_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO1_O";
ATTRIBUTE X_INTERFACE_INFO OF io1_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO1_T";
ATTRIBUTE X_INTERFACE_INFO OF sck_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SCK_I";
ATTRIBUTE X_INTERFACE_INFO OF sck_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SCK_O";
ATTRIBUTE X_INTERFACE_INFO OF sck_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SCK_T";
ATTRIBUTE X_INTERFACE_INFO OF ss_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SS_I";
ATTRIBUTE X_INTERFACE_INFO OF ss_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SS_O";
ATTRIBUTE X_INTERFACE_INFO OF ss_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SS_T";
ATTRIBUTE X_INTERFACE_INFO OF ip2intc_irpt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT";
BEGIN
U0 : axi_quad_spi
GENERIC MAP (
Async_Clk => 1,
C_FAMILY => "zynq",
C_SUB_FAMILY => "zynq",
C_INSTANCE => "axi_quad_spi_inst",
C_SPI_MEM_ADDR_BITS => 24,
C_TYPE_OF_AXI4_INTERFACE => 0,
C_XIP_MODE => 0,
C_FIFO_DEPTH => 16,
C_SCK_RATIO => 32,
C_NUM_SS_BITS => 1,
C_NUM_TRANSFER_BITS => 8,
C_SPI_MODE => 0,
C_USE_STARTUP => 0,
C_SPI_MEMORY => 1,
C_S_AXI_ADDR_WIDTH => 7,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI4_ADDR_WIDTH => 24,
C_S_AXI4_DATA_WIDTH => 32,
C_S_AXI4_ID_WIDTH => 1,
C_S_AXI4_BASEADDR => X"FFFFFFFF",
C_S_AXI4_HIGHADDR => X"00000000"
)
PORT MAP (
ext_spi_clk => ext_spi_clk,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi4_aclk => '0',
s_axi4_aresetn => '0',
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
s_axi4_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi4_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 24)),
s_axi4_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi4_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi4_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi4_awlock => '0',
s_axi4_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi4_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi4_awvalid => '0',
s_axi4_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi4_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi4_wlast => '0',
s_axi4_wvalid => '0',
s_axi4_bready => '0',
s_axi4_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi4_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 24)),
s_axi4_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi4_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi4_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi4_arlock => '0',
s_axi4_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi4_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi4_arvalid => '0',
s_axi4_rready => '0',
io0_i => io0_i,
io0_o => io0_o,
io0_t => io0_t,
io1_i => io1_i,
io1_o => io1_o,
io1_t => io1_t,
io2_i => '0',
io3_i => '0',
spisel => '1',
sck_i => sck_i,
sck_o => sck_o,
sck_t => sck_t,
ss_i => ss_i,
ss_o => ss_o,
ss_t => ss_t,
ip2intc_irpt => ip2intc_irpt
);
END Test_AXI_Master_simple_v1_0_hw_1_axi_quad_spi_0_0_arch;
| gpl-2.0 | 21ebacbe0f4ea25991cec2c011edbccc | 0.657627 | 2.944713 | false | false | false | false |
dpolad/dlx | DLX_vhd/a.i.a.c-LOGICUNIT.vhd | 2 | 674 |
-- logic_unit.vhd --
-- TODO: replace this with a better structural LOGIC UNIT.
library ieee;
use ieee.std_logic_1164.all;
--use work.myTypes.all;
entity logic_unit is
generic (
SIZE : integer := 32
);
port (
IN1 : in std_logic_vector(SIZE - 1 downto 0);
IN2 : in std_logic_vector(SIZE - 1 downto 0);
CTRL : in std_logic_vector(1 downto 0); -- need to do only and, or and xor
OUT1 : out std_logic_vector(SIZE - 1 downto 0)
);
end logic_unit;
architecture Bhe of logic_unit is
begin
OUT1 <= IN1 and IN2 when CTRL = "00" else
IN1 or IN2 when CTRL = "01" else
IN1 xor IN2 when CTRL = "10" else
(others => '0'); -- should never appear
end Bhe;
| bsd-2-clause | 6ef027f1c20dd0917d75157966421cbd | 0.654303 | 2.717742 | false | false | false | false |
manosaloscables/vhdl | circuitos_secuenciales/ffden/ffden_bp.vhd | 1 | 1,583 | -- *******************************************************
-- * Banco de prueba para Flip Flop tipo D con activador *
-- *******************************************************
library ieee; use ieee.std_logic_1164.all;
entity ffden_bp is
end ffden_bp;
architecture arq_bp of ffden_bp is
constant T: time := 20 ns; -- Período del reloj
signal clk, rst, en: std_logic; -- Reloj, reinicio y activador
signal prueba_e: std_logic; -- Entradas
signal prueba_s: std_logic; -- Salida
begin
-- Instanciar la unidad bajo prueba
ubp: entity work.ffden(arq)
port map(
clk => clk,
rst => rst,
en => en,
d => prueba_e,
q => prueba_s
);
-- Reloj
process begin
clk <= '0';
wait for T/2;
clk <= '1';
wait for T/2;
end process;
-- Reinicio
rst <= '1', '0' after T/2;
-- Otros estímulos
process begin
en <= '0';
for i in 1 to 5 loop -- Esperar 5 transisiones del Flip Flop tipo D
prueba_e <= '0';
wait until falling_edge(clk);
prueba_e <= '1';
wait until falling_edge(clk);
end loop;
en <= '1';
for i in 1 to 5 loop -- Esperar 5 transisiones del Flip Flop tipo D
prueba_e <= '0';
wait until falling_edge(clk);
prueba_e <= '1';
wait until falling_edge(clk);
end loop;
-- Terminar la simulación
assert false
report "Simulación Completada"
severity failure;
end process;
end arq_bp;
| gpl-3.0 | d7cf799abedf945bd9579bb145296f66 | 0.497157 | 3.83293 | false | false | false | false |
MAV-RT-testbed/MAV-testbed | Syma_Flight_Final/Syma_Flight_Final.srcs/sources_1/ipshared/xilinx.com/axi_quad_spi_v3_2/c64e9f22/hdl/src/vhdl/qspi_status_slave_sel_reg.vhd | 3 | 14,986 | -------------------------------------------------------------------------------
-- SPI Status Register Module - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: spi_status_reg.vhd
-- Version: v3.0
-- Description: Serial Peripheral Interface (SPI) Module for interfacing
-- with a 32-bit AXI4 Bus. The file defines the logic for
-- status and slave select register.
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.FDRE;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_SPI_NUM_BITS_REG -- Width of SPI registers
-- C_S_AXI_DATA_WIDTH -- Native data bus width 32 bits only
-- C_NUM_SS_BITS -- Number of bits in slave select
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- SYSTEM
-- Bus2IP_Clk -- Bus to IP clock
-- Soft_Reset_op -- Soft_Reset_op Signal
-- STATUS REGISTER RELATED SIGNALS
--================================
-- REGISTER/FIFO INTERFACE
-- Bus2IP_SPISR_RdCE -- Status register Read Chip Enable
-- IP2Bus_SPISR_Data -- Status register data to PLB based on PLB read
-- SR_3_modf -- Mode fault error status flag
-- SR_4_Tx_Full -- Transmit register full status flag
-- SR_5_Tx_Empty -- Transmit register empty status flag
-- SR_6_Rx_Full -- Receive register full status flag
-- SR_7_Rx_Empty -- Receive register empty stauts flag
-- ModeFault_Strobe -- Mode fault strobe
-- SLAVE REGISTER RELATED SIGNALS
--===============================
-- Bus2IP_SPISSR_WrCE -- slave select register write chip enable
-- Bus2IP_SPISSR_RdCE -- slave select register read chip enable
-- Bus2IP_SPISSR_Data -- slave register data from PLB Bus
-- IP2Bus_SPISSR_Data -- Data from slave select register during PLB rd
-- SPISSR_Data_reg_op -- Data to SPI Module
-- Wr_ce_reduce_ack_gen -- commaon write ack generation signal
-- Rd_ce_reduce_ack_gen -- commaon read ack generation signal
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Declaration
-------------------------------------------------------------------------------
entity qspi_status_slave_sel_reg is
generic
(
C_SPI_NUM_BITS_REG : integer; -- Number of bits in SR
------------------------
C_S_AXI_DATA_WIDTH : integer; -- 32 bits
------------------------
C_NUM_SS_BITS : integer; -- Number of bits in slave select
------------------------
C_SPISR_REG_WIDTH : integer
);
port
(
Bus2IP_Clk : in std_logic;
Soft_Reset_op : in std_logic;
-- I/P from control register
SPISR_0_Command_Error : in std_logic; -- bit0 of SPISR
SPISR_1_LOOP_Back_Error : in std_logic; -- bit1 of SPISR
SPISR_2_MSB_Error : in std_logic;
SPISR_3_Slave_Mode_Error : in std_logic;
SPISR_4_CPOL_CPHA_Error : in std_logic; -- bit 4 of SPISR
-- I/P from other modules
SPISR_Ext_SPISEL_slave : in std_logic; -- bit 5 of SPISR
SPISR_7_Tx_Full : in std_logic; -- bit 7 of SPISR
SPISR_8_Tx_Empty : in std_logic;
SPISR_9_Rx_Full : in std_logic;
SPISR_10_Rx_Empty : in std_logic; -- bit 10 of SPISR
-- Slave attachment ports
ModeFault_Strobe : in std_logic;
Rd_ce_reduce_ack_gen : in std_logic;
Bus2IP_SPISR_RdCE : in std_logic;
IP2Bus_SPISR_Data : out std_logic_vector(0 to (C_SPISR_REG_WIDTH-1));
SR_3_modf : out std_logic;
-- Reg/FIFO ports
-- SPI module ports
-----------------------------------
-- Slave Select Register ports
Bus2IP_SPISSR_WrCE : in std_logic;
Wr_ce_reduce_ack_gen : in std_logic;
Bus2IP_SPISSR_RdCE : in std_logic;
Bus2IP_SPISSR_Data : in std_logic_vector(0 to (C_S_AXI_DATA_WIDTH-1));
IP2Bus_SPISSR_Data : out std_logic_vector(0 to (C_NUM_SS_BITS-1));
-- SPI module ports
SPISSR_Data_reg_op : out std_logic_vector(0 to (C_NUM_SS_BITS-1))
);
end qspi_status_slave_sel_reg;
-------------------------------------------------------------------------------
-- Architecture
---------------
architecture imp of qspi_status_slave_sel_reg is
----------------------------------------------------------
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-- Signal Declarations
----------------------
signal SPISR_reg : std_logic_vector(0 to (C_SPISR_REG_WIDTH-1));
signal modf : std_logic;
signal modf_Reset : std_logic;
----------------------
signal SPISSR_Data_reg : std_logic_vector(0 to (C_NUM_SS_BITS-1));
signal spissr_reg_en : std_logic;
constant RESET_ACTIVE : std_logic := '1';
----------------------
begin
-----
-- SPISR - 0 1 2 3 4 5 6 7 8 9 10
-- Command Loop BK MSB Slv Mode CPOL_CPHA Slave Mode MODF Tx_Full Tx_Empty Rx_Full Rx_Empty
-- Error Error Error Error Error Select
-- Default 0 0 0 1 0 1 0 0 1 0 1
-------------------------------------------------------------------------------
-- Combinatorial operations
-------------------------------------------------------------------------------
SPISR_reg(C_SPISR_REG_WIDTH - 11) <= SPISR_0_Command_Error; -- SPISR bit 0 @ C_SPISR_REG_WIDTH = 11
SPISR_reg(C_SPISR_REG_WIDTH - 10) <= SPISR_1_LOOP_Back_Error; -- SPISR bit 1
SPISR_reg(C_SPISR_REG_WIDTH - 9) <= SPISR_2_MSB_Error; -- SPISR bit 2
SPISR_reg(C_SPISR_REG_WIDTH - 8) <= SPISR_3_Slave_Mode_Error; -- SPISR bit 3
SPISR_reg(C_SPISR_REG_WIDTH - 7) <= SPISR_4_CPOL_CPHA_Error; -- SPISR bit 4
SPISR_reg(C_SPISR_REG_WIDTH - 6) <= SPISR_Ext_SPISEL_slave; -- SPISR bit 5
SPISR_reg(C_SPISR_REG_WIDTH - 5) <= modf; -- SPISR bit 6
SPISR_reg(C_SPISR_REG_WIDTH - 4) <= SPISR_7_Tx_Full; -- SPISR bit 7
SPISR_reg(C_SPISR_REG_WIDTH - 3) <= SPISR_8_Tx_Empty; -- SPISR bit 8
SPISR_reg(C_SPISR_REG_WIDTH - 2) <= SPISR_9_Rx_Full; -- SPISR bit 9
SPISR_reg(C_SPISR_REG_WIDTH - 1) <= SPISR_10_Rx_Empty; -- SPISR bit 10
SR_3_modf <= modf;
-------------------------------------------------------------------------------
-- STATUS_REG_RD_GENERATE : Status Register Read Generate
----------------------------
STATUS_REG_RD_GENERATE: for i in 0 to C_SPISR_REG_WIDTH-1 generate
-----
begin
-----
IP2Bus_SPISR_Data(i) <= SPISR_reg(i) and Bus2IP_SPISR_RdCE;
end generate STATUS_REG_RD_GENERATE;
-------------------------------------------------------------------------------
-- MODF_REG_PROCESS : Set and Clear modf
------------------------
MODF_REG_PROCESS:process(Bus2IP_Clk) is
-----
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (modf_Reset = RESET_ACTIVE) then
modf <= '0';
elsif (ModeFault_Strobe = '1') then
modf <= '1';
end if;
end if;
end process MODF_REG_PROCESS;
modf_Reset <= (Rd_ce_reduce_ack_gen and Bus2IP_SPISR_RdCE) or Soft_Reset_op;
--******************************************************************************
-- logic for Slave Select Register
-- Combinatorial operations
----------------------------
SPISSR_Data_reg_op <= SPISSR_Data_reg;
-------------------------------------------------------------------------------
-- SPISSR_WR_GEN : Slave Select Register Write Operation
----------------------------
SPISSR_WR_GEN: for i in 0 to C_NUM_SS_BITS-1 generate
-----
begin
-----
spissr_reg_en <= Wr_ce_reduce_ack_gen and Bus2IP_SPISSR_WrCE;
SPISSR_WR_PROCESS:process(Bus2IP_Clk) is
-----
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
SPISSR_Data_reg(i) <= '1';
elsif ((Wr_ce_reduce_ack_gen and Bus2IP_SPISSR_WrCE) = '1') then
SPISSR_Data_reg(i) <=
Bus2IP_SPISSR_Data(C_S_AXI_DATA_WIDTH-C_NUM_SS_BITS+i);
end if;
end if;
end process SPISSR_WR_PROCESS;
--SPISSR_WR_PROCESS_I: component FDRE
-- generic map(
-- INIT => '1'
-- )
-- port map
-- (
-- Q => SPISSR_Data_reg(i) ,-- out:
-- C => Bus2IP_Clk ,--: in
-- CE => spissr_reg_en ,--: in
-- R => Soft_Reset_op ,-- : in
-- D => Bus2IP_SPISSR_Data(C_S_AXI_DATA_WIDTH-C_NUM_SS_BITS+i) --: in
-- );
---------------------------------
-----
end generate SPISSR_WR_GEN;
-------------------------------------------------------------------------------
-- SLAVE_SEL_REG_RD_GENERATE : Slave Select Register Read Generate
-------------------------------
SLAVE_SEL_REG_RD_GENERATE: for i in 0 to C_NUM_SS_BITS-1 generate
-----
begin
-----
IP2Bus_SPISSR_Data(i) <= SPISSR_Data_reg(i) and
Bus2IP_SPISSR_RdCE;
end generate SLAVE_SEL_REG_RD_GENERATE;
---------------------------------------
end imp;
--------------------------------------------------------------------------------
| gpl-2.0 | dc5a4949eb2e0b6499056fbe6d50d63c | 0.44675 | 4.5193 | false | false | false | false |
rodrigofegui/UnB | 2017.1/Organização e Arquitetura de Computadores/Trabalhos/Trabalho 3/Codificação/reg_tb.vhd | 1 | 2,018 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY reg_tb IS
END reg_tb;
generic (
DATA_WIDTH : natural := 32;
ADDRESS_WIDTH : natural := 5
);
ARCHITECTURE reg_arch OF reg_tb IS
SIGNAL: S_clk : std_logic;
SIGNAL: S_wren : std_logic;
SIGNAL: S_radd1 : std_logic_vector(ADDRESS_WIDTH-1 downto 0);
SIGNAL: S_radd2 : std_logic_vector(ADDRESS_WIDTH-1 downto 0);
SIGNAL: S_wadd : std_logic_vector(ADDRESS_WIDTH-1 downto 0);
SIGNAL: S_wdata : std_logic_vector(DATA_WIDTH -1 downto 0);
SIGNAL: S_rdata1 : std_logic_vector(DATA_WIDTH -1 downto 0);
SIGNAL: S_rdata2 : std_logic_vector(DATA_WIDTH -1 downto 0);
COMPONENT reg
port (
clk, wren : in std_logic;
radd1, radd2, wadd : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
wdata : in std_logic_vector(DATA_WIDTH -1 downto 0);
rdata1, rdata2 : out std_logic_vector(DATA_WIDTH -1 downto 0)
);
END COMPONENT;
BEGIN
i1 : reg
PORT MAP (
clk => S_clk;
wren => S_wren;
radd1 => S_radd1;
radd2 => S_radd2;
wadd => S_wadd;
wdata => S_wdata;
rdata1 => S_rdata1;
rdata2 => S_rdata2);
Clk_process : PROCESS
BEGIN
S_clk <= '0';
wait for 5 ns;
S_clk <= '1';
wait for 5 ns;
END PROCESS Clk_process;
Wrt_process : PROCESS
BEGIN
S_wren <= '0';
wait for 5 ns;
S_wren <= '1';
wait for 5 ns;
end process Wrt_process;
Stimulus : PROCESS;
BEGIN;
wait for 5 ns;
S_radd1 <=
S_radd2 <=
S_wadd <=
S_wdata <=
wait for 5 ns;
-- case 2
wait for 5 ns;
-- case 3
wait for 5 ns;
-- case 4
wait for 5 ns;
END PROCESS Stimulus;
WAIT;
END PROCESS;
END reg_arch; | gpl-3.0 | ef7badeac063f8c80f47b08cad24ab26 | 0.509415 | 3.128682 | false | false | false | false |
jobisoft/jTDC | modules/VFB6/bus_interface_vfb6.vhdl | 1 | 4,671 | -------------------------------------------------------------------------
---- ----
---- Engineer: A. Winnebeck ----
---- Company: ELB-Elektroniklaboratorien Bonn UG ----
---- (haftungsbeschränkt) ----
---- ----
-------------------------------------------------------------------------
---- ----
---- Copyright (C) 2015 ELB ----
---- ----
---- This program is free software; you can redistribute it and/or ----
---- modify it under the terms of the GNU General Public License as ----
---- published by the Free Software Foundation; either version 3 of ----
---- the License, or (at your option) any later version. ----
---- ----
---- This program is distributed in the hope that it will be useful, ----
---- but WITHOUT ANY WARRANTY; without even the implied warranty of ----
---- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ----
---- GNU General Public License for more details. ----
---- ----
---- You should have received a copy of the GNU General Public ----
---- License along with this program; if not, see ----
---- <http://www.gnu.org/licenses>. ----
---- ----
-------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity bus_interface_vfb6 is
Port (
board_databus : inout STD_LOGIC_VECTOR(31 downto 0);
board_address : in STD_LOGIC_VECTOR(15 downto 0);
board_read : in STD_LOGIC;
board_write : in STD_LOGIC;
board_dtack : out STD_LOGIC := '0';
CLK : in STD_LOGIC;
statusregister : in STD_LOGIC_VECTOR(31 downto 0);
internal_databus : inout STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
internal_address : out STD_LOGIC_VECTOR(15 downto 0) := (others => '0');
internal_read : out STD_LOGIC := '0';
internal_write : out STD_LOGIC := '0');
end bus_interface_vfb6;
architecture Behavioral of bus_interface_vfb6 is
---- Signals for VME-Interface ----
signal test_register : STD_LOGIC_VECTOR(31 downto 0):=X"DEADBEEF";
signal le_write_int : STD_LOGIC;
signal board_read_sync : STD_LOGIC;
signal board_read_pre_sync : STD_LOGIC;
---- Component declaration ----
COMPONENT leading_edge_clipper
PORT(
input : IN std_logic;
CLK : IN std_logic;
output : OUT std_logic
);
END COMPONENT;
begin
---- Instantiation of Pulseclipper ----
le_w_int: leading_edge_clipper
PORT MAP( input => board_write,
CLK => CLK,
output => le_write_int);
---- Sync board read
synchronize_read_int: Process (CLK) is
begin
if rising_edge(CLK) then
board_read_pre_sync <= board_read;
board_read_sync <= board_read_pre_sync;
end if;
end process;
process (CLK) is
begin
if rising_edge(CLK) then
if (le_write_int = '1') then
case board_address is
when X"0014" => test_register <= board_databus;
when others => NULL;
end case;
elsif (board_read_sync = '1') then
case board_address is
when X"0010" => board_databus <= statusregister;
when X"0014" => board_databus <= test_register;
when others => board_databus <= (others => 'Z');
end case;
else
board_databus <= (others=>'Z');
end if;
end if;
end process;
dtack_process: process (CLK) is
begin
if rising_edge(CLK) then
-- generate Data Acknowlege, if Module is addressed, but CPLD registers are not addressed
if ((board_read_sync = '1' OR board_write = '1') AND (NOT(board_address = X"0000" OR board_address = X"0004" OR board_address = X"0008")))then
board_dtack <= '1';
else
board_dtack <= '0';
end if;
end if;
end process;
internal_write <= le_write_int;
internal_read <= board_read_sync;
internal_address <= board_address(15 downto 2) & "00";
internal_databus <= board_databus;
end Behavioral;
| gpl-3.0 | db1128ddd079d36a5febc9f27c2f6781 | 0.513809 | 4.129973 | false | false | false | false |
dpolad/dlx | DLX_vhd/a.c.a-2BITPREDICTOR.vhd | 2 | 1,943 | -- *** 2_bit_predictor.vhd *** --
-- this block is a simple 2 bit predictor.
-- it implements the canonical FSM for 2 bit preditcors
-- look at the scheme on Hennessy Patterson 5th Ed., figure C-18
-- this needs to be implemented for each line of the BTB cache
-- Future improvements: integrate this into the BTB in order to instatiate only one
library ieee;
use ieee.std_logic_1164.all;
entity predictor_2 is
port (
clock : in std_logic;
reset : in std_logic;
enable : in std_logic; -- if 1 FSM advances, 0 is frozen
taken_i : in std_logic; -- input bit -> 1 taken, 0 not taken
prediction_o : out std_logic -- output but -> 1 taken, 0 not taken
);
end predictor_2;
architecture bhe of predictor_2 is
-- state is on 2 bits
-- 00 strong NT
-- 01 weak NT
-- 10 weak T
-- 11 strong T
signal STATE : std_logic_vector(1 downto 0);
signal next_STATE : std_logic_vector(1 downto 0);
begin
-- output of the circuit is the MSB of the state
prediction_o <= STATE(1);
-- sequential process for state update
process(clock,reset)
begin
if reset='1' then
STATE <= "00";
elsif clock = '1' and clock'event and enable = '1' then
STATE <= next_STATE;
end if;
end process;
-- combinatorial process for next_STATE computation
-- Future improvements : do this by hand
process(taken_i, enable)
begin
if enable = '1' then
if taken_i = '1' then
case STATE is
when "00" => next_STATE <= "01";
when "01" => next_STATE <= "10";
when "10" => next_STATE <= "11";
when "11" => next_STATE <= "11";
when others => next_STATE <= "00"; -- might not be synthesizable
end case;
else
case STATE is
when "00" => next_STATE <= "00";
when "01" => next_STATE <= "00";
when "10" => next_STATE <= "01";
when "11" => next_STATE <= "10";
when others => next_STATE <= "00"; -- might not be synthesizable
end case;
end if;
end if;
end process;
end bhe;
| bsd-2-clause | 8ef28b3c5c1e16ee65f0e2862322bc00 | 0.634586 | 2.966412 | false | false | false | false |
manosaloscables/vhdl | circuitos_secuenciales/sram_doble_puerto/sram_dp.vhd | 1 | 1,862 | -- ******************************************************************
-- * RAM síncrona de doble puerto simplificada para FPGAs de Altera *
-- ******************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sram_dp is
generic(
DIR_ANCHO : integer:=2;
DATOS_ANCHO: integer:=8
);
port(
clk: in std_logic;
we : in std_logic; -- Activador de escritura
-- Direcciones de escritura y lectura
w_dir: in std_logic_vector(DIR_ANCHO-1 downto 0); -- Escritura
r_dir: in std_logic_vector(DIR_ANCHO-1 downto 0); -- Lectura
-- Registros que reflejan cómo los módulos de memoria embebida están
-- empaquetados con una interfaz síncrona en los chips Cyclone.
d: in std_logic_vector(DATOS_ANCHO-1 downto 0);
q: out std_logic_vector(DATOS_ANCHO-1 downto 0)
);
end sram_dp;
-- ****************************************************************************
-- Si w_addr y r_addr son iguales, q adquiere los datos actuales (nuevos datos)
-- ****************************************************************************
architecture arq_dir_reg of sram_dp is
--------------------------------------------------------------------
-- Crear un tipo de datos de dos dimensiones definido por el usuario
type mem_tipo_2d is array (0 to 2**DIR_ANCHO-1)
of std_logic_vector (DATOS_ANCHO-1 downto 0);
signal sram: mem_tipo_2d;
--------------------------------------------------------------------
signal dir_reg: std_logic_vector(DIR_ANCHO-1 downto 0);
begin
process (clk) begin
if(rising_edge(clk)) then
if (we='1') then
sram(to_integer(unsigned(w_dir))) <= d;
end if;
dir_reg <= r_dir;
end if;
end process;
-- Salida
q <= sram(to_integer(unsigned(dir_reg)));
end arq_dir_reg;
| gpl-3.0 | 65b9a82225591d936bc2909a873444c5 | 0.504577 | 3.766734 | false | false | false | false |
dpolad/dlx | DLX_vhd/a.i.a.d-P4ADD.vhd | 2 | 1,729 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity p4add is
generic (
N : integer := 32;
logN : integer := 5);
Port ( A : In std_logic_vector(N-1 downto 0);
B : In std_logic_vector(N-1 downto 0);
Cin : In std_logic;
sign : In std_logic;
S : Out std_logic_vector(N-1 downto 0);
Cout : Out std_logic);
end p4add;
architecture STRUCTURAL of p4add is
component xor_gen is
generic (
N : integer
);
Port (
A : In std_logic_vector(N-1 downto 0);
B : In std_logic;
S : Out std_logic_vector(N-1 downto 0)
);
end component;
component sum_gen
generic( N : integer := 32);
Port ( A: In std_logic_vector(N-1 downto 0);
B: In std_logic_vector(N-1 downto 0);
Cin: In std_logic_vector((N/4) downto 0);
S: Out std_logic_vector(N-1 downto 0));
end component;
component carry_tree
generic (
N : integer := 32;
logN : integer := 5);
Port ( A: In std_logic_vector(N-1 downto 0);
B: In std_logic_vector(N-1 downto 0);
Cin: In std_logic;
Cout: Out std_logic_vector(N/4-1 downto 0));
end component;
signal carry_pro : std_logic_vector(N/4 downto 0);
signal new_B : std_logic_vector(N-1 downto 0);
begin
xor32: xor_gen
generic map(N=>N)
port map(B,sign,new_B);
ct: carry_tree
generic map(N=>N,logN=>logN)
port map(A,new_B,carry_pro(0),carry_pro(N/4 downto 1));
add: sum_gen
generic map(N=>N)
port map(A,new_B,carry_pro(N/4 downto 0),S);
carry_pro(0)<=Cin xor sign;
Cout<= carry_pro(N/4);
end STRUCTURAL;
| bsd-2-clause | 04bf10f794e6cc472f7afc8c6966566a | 0.561596 | 2.7664 | false | false | false | false |
rodrigofegui/UnB | 2017.1/Organização e Arquitetura de Computadores/Trabalhos/Projeto Final/Codificação/somador_tb.vhd | 2 | 1,531 | ----------------------------------------------------------------------------------
-- Organizacao e Arquitetura de Computadores
-- Professor: Marcelo Grandi Mandelli
-- Responsaveis: Danillo Neves
-- Luiz Gustavo
-- Rodrigo Guimarães
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY somador_tb IS
GENERIC (DATA_WIDTH : natural := 32);
END somador_tb;
ARCHITECTURE somador_arch OF somador_tb IS
COMPONENT somador --componente que sera testado
port (dataIn1, dataIn2 : in std_logic_vector (DATA_WIDTH - 1 downto 0);
dataOut : out std_logic_vector (DATA_WIDTH - 1 downto 0));
END COMPONENT;
SIGNAL ent1, ent2, saida : std_logic_vector (DATA_WIDTH - 1 downto 0) := (others => '0');
BEGIN
SomadorTB : somador PORT MAP (ent1, ent2, saida);
Stimulus : PROCESS
BEGIN
wait for 5 ns;
ent1 <= x"00000000000000000000000000000101";
ent2 <= x"00000000000000000000000000000101";
wait for 10 ns;
ent1 <= x"00000000000000000000000000000101";
ent2 <= x"00000000000000000000000000001010";
wait for 10 ns;
ent1 <= x"00000000000000000000000000011001";
ent2 <= x"00000000000000000000000001001001";
wait for 10 ns;
ent1 <= x"00000000000010000000000000011001";
ent2 <= x"00000000000010000000000001001001";
END PROCESS Stimulus;
END somador_arch; --fim do testbench | gpl-3.0 | 85b276b51304f9daaec80cf871d45677 | 0.593852 | 4.066489 | false | false | false | false |
MAV-RT-testbed/MAV-testbed | Syma_Flight_Final/Syma_Flight_Final.srcs/sources_1/ipshared/xilinx.com/axi_quad_spi_v3_2/c64e9f22/hdl/src/vhdl/cross_clk_sync_fifo_0.vhd | 1 | 84,438 | -------------------------------------------------------------------------------
-- cross_clk_sync_fifo_0.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: cross_clk_sync_fifo_0.vhd
-- Version: v3.1
-- Description: This is the CDC logic when FIFO = 0.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.conv_std_logic_vector;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_misc.all;
-- library unsigned is used for overloading of "=" which allows integer to
-- be compared to std_logic_vector
use ieee.std_logic_unsigned.all;
library axi_lite_ipif_v3_0;
use axi_lite_ipif_v3_0.axi_lite_ipif;
use axi_lite_ipif_v3_0.ipif_pkg.all;
library lib_cdc_v1_0;
use lib_cdc_v1_0.cdc_sync;
library axi_quad_spi_v3_2;
use axi_quad_spi_v3_2.all;
library unisim;
use unisim.vcomponents.FDRE;
use unisim.vcomponents.FDR;
-------------------------------------------------------------------------------
entity cross_clk_sync_fifo_0 is
generic (
C_NUM_TRANSFER_BITS : integer;
Async_Clk : integer;
C_NUM_SS_BITS : integer--;
--C_AXI_SPI_CLK_EQ_DIFF : integer
);
port (
EXT_SPI_CLK : in std_logic;
Bus2IP_Clk : in std_logic;
Soft_Reset_op : in std_logic;
Rst_from_axi_cdc_to_spi : in std_logic;
----------------------------
Tx_FIFO_Empty_cdc_from_axi : in std_logic;
Tx_FIFO_Empty_cdc_to_spi : out std_logic;
----------------------------------------------------------
Tx_FIFO_Empty_SPISR_cdc_from_spi : in std_logic;
Tx_FIFO_Empty_SPISR_cdc_to_axi : out std_logic;
----------------------------------------------------------
spisel_d1_reg_cdc_from_spi : in std_logic; -- = spisel_pulse_cdc_from_spi_clk , -- in
spisel_d1_reg_cdc_to_axi : out std_logic; -- = spisel_pulse_cdc_to_axi_clk , -- out
--------------------------:-------------------------------
spisel_pulse_cdc_from_spi : in std_logic; -- = spisel_pulse_cdc_from_spi_clk , -- in
spisel_pulse_cdc_to_axi : out std_logic; -- = spisel_pulse_cdc_to_axi_clk , -- out
--------------------------:-------------------------------
spiXfer_done_cdc_from_spi : in std_logic; -- = spiXfer_done_cdc_from_spi_clk, -- in
spiXfer_done_cdc_to_axi : out std_logic; -- = spiXfer_done_cdc_to_axi_clk , -- out
--------------------------:-------------------------------
modf_strobe_cdc_from_spi : in std_logic; -- = modf_strobe_cdc_from_spi_clk, -- in
modf_strobe_cdc_to_axi : out std_logic; -- = modf_strobe_cdc_to_axi_clk , -- out
--------------------------:-------------------------------
Slave_MODF_strobe_cdc_from_spi : in std_logic; -- = slave_MODF_strobe_cdc_from_spi_clk,-- in
Slave_MODF_strobe_cdc_to_axi : out std_logic; -- = slave_MODF_strobe_cdc_to_axi_clk ,-- out
--------------------------:-------------------------------
receive_Data_cdc_from_spi : in std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1)); -- = receive_Data_cdc_from_spi_clk, -- in
receive_Data_cdc_to_axi : out std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1)); -- = receive_data_cdc_to_axi_clk, -- out
--------------------------:-------------------------------
drr_Overrun_int_cdc_from_spi : in std_logic;
drr_Overrun_int_cdc_to_axi : out std_logic;
--------------------------:-------------------------------
dtr_underrun_cdc_from_spi : in std_logic; -- = dtr_underrun_cdc_from_spi_clk, -- in
dtr_underrun_cdc_to_axi : out std_logic; -- = dtr_underrun_cdc_to_axi_clk, -- out
--------------------------:-------------------------------
transmit_Data_cdc_from_axi : in std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1)); -- = transmit_Data_cdc_from_axi_clk, -- in
transmit_Data_cdc_to_spi : out std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1)); -- = transmit_Data_cdc_to_spi_clk -- out
----------------------------
SPICR_0_LOOP_cdc_from_axi : in std_logic;
SPICR_0_LOOP_cdc_to_spi : out std_logic;
----------------------------
SPICR_1_SPE_cdc_from_axi : in std_logic;
SPICR_1_SPE_cdc_to_spi : out std_logic;
----------------------------
SPICR_2_MST_N_SLV_cdc_from_axi : in std_logic;
SPICR_2_MST_N_SLV_cdc_to_spi : out std_logic;
----------------------------
SPICR_3_CPOL_cdc_from_axi : in std_logic;
SPICR_3_CPOL_cdc_to_spi : out std_logic;
----------------------------
SPICR_4_CPHA_cdc_from_axi : in std_logic;
SPICR_4_CPHA_cdc_to_spi : out std_logic;
----------------------------
SPICR_5_TXFIFO_cdc_from_axi : in std_logic;
SPICR_5_TXFIFO_cdc_to_spi : out std_logic;
----------------------------
SPICR_6_RXFIFO_RST_cdc_from_axi: in std_logic;
SPICR_6_RXFIFO_RST_cdc_to_spi : out std_logic;
----------------------------
SPICR_7_SS_cdc_from_axi : in std_logic;
SPICR_7_SS_cdc_to_spi : out std_logic;
----------------------------
SPICR_8_TR_INHIBIT_cdc_from_axi: in std_logic;
SPICR_8_TR_INHIBIT_cdc_to_spi : out std_logic;
----------------------------
SPICR_9_LSB_cdc_from_axi : in std_logic;
SPICR_9_LSB_cdc_to_spi : out std_logic;
----------------------------
SPICR_bits_7_8_cdc_from_axi : in std_logic_vector(1 downto 0); -- in std_logic_vector
SPICR_bits_7_8_cdc_to_spi : out std_logic_vector(1 downto 0);
----------------------------
SR_3_modf_cdc_from_axi : in std_logic;
SR_3_modf_cdc_to_spi : out std_logic;
----------------------------
SPISSR_cdc_from_axi : in std_logic_vector(0 to (C_NUM_SS_BITS-1));
SPISSR_cdc_to_spi : out std_logic_vector(0 to (C_NUM_SS_BITS-1))
----------------------------
);
end entity cross_clk_sync_fifo_0;
architecture imp of cross_clk_sync_fifo_0 is
--------------------------------------------
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-- signal declaration
signal spisel_d1_reg_cdc_from_spi_d1 : std_logic;
signal spisel_d1_reg_cdc_from_spi_d2 : std_logic;
signal spiXfer_done_cdc_from_spi_d1 : std_logic;
signal spiXfer_done_cdc_from_spi_d2 : std_logic;
signal modf_strobe_cdc_from_spi_d1 : std_logic;
signal modf_strobe_cdc_from_spi_d2 : std_logic;
signal modf_strobe_cdc_from_spi_d3 : std_logic;
signal Slave_MODF_strobe_cdc_from_spi_d1 : std_logic;
signal Slave_MODF_strobe_cdc_from_spi_d2 : std_logic;
signal Slave_MODF_strobe_cdc_from_spi_d3 : std_logic;
signal receive_Data_cdc_from_spi_d1 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal receive_Data_cdc_from_spi_d2 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal dtr_underrun_cdc_from_spi_d1 : std_logic;
signal dtr_underrun_cdc_from_spi_d2 : std_logic;
signal transmit_Data_cdc_from_axi_d1 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal transmit_Data_cdc_from_axi_d2 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal spisel_pulse_cdc_from_spi_d1 : std_logic;
signal spisel_pulse_cdc_from_spi_d2 : std_logic;
signal spisel_pulse_cdc_from_spi_d3 : std_logic;
signal SPICR_0_LOOP_cdc_from_axi_d1 : std_logic;
signal SPICR_0_LOOP_cdc_from_axi_d2 : std_logic;
signal SPICR_1_SPE_cdc_from_axi_d1 : std_logic;
signal SPICR_1_SPE_cdc_from_axi_d2 : std_logic;
signal SPICR_2_MST_N_SLV_cdc_from_axi_d1 : std_logic;
signal SPICR_2_MST_N_SLV_cdc_from_axi_d2 : std_logic;
signal SPICR_3_CPOL_cdc_from_axi_d1 : std_logic;
signal SPICR_3_CPOL_cdc_from_axi_d2 : std_logic;
signal SPICR_4_CPHA_cdc_from_axi_d1 : std_logic;
signal SPICR_4_CPHA_cdc_from_axi_d2 : std_logic;
signal SPICR_5_TXFIFO_cdc_from_axi_d1 : std_logic;
signal SPICR_5_TXFIFO_cdc_from_axi_d2 : std_logic;
signal SPICR_7_SS_cdc_from_axi_d1 : std_logic;
signal SPICR_7_SS_cdc_from_axi_d2 : std_logic;
signal SPICR_8_TR_INHIBIT_cdc_from_axi_d1 : std_logic;
signal SPICR_8_TR_INHIBIT_cdc_from_axi_d2 : std_logic;
signal SPICR_9_LSB_cdc_from_axi_d1 : std_logic;
signal SPICR_9_LSB_cdc_from_axi_d2 : std_logic;
signal SPICR_bits_7_8_cdc_from_axi_d1 : std_logic_vector(1 downto 0);
signal SPICR_bits_7_8_cdc_from_axi_d2 : std_logic_vector(1 downto 0);
signal SPICR_6_RXFIFO_RST_cdc_from_axi_d1 : std_logic;
signal SPICR_6_RXFIFO_RST_cdc_from_axi_d2 : std_logic;
signal Tx_FIFO_Empty_cdc_from_axi_d1 : std_logic;
signal Tx_FIFO_Empty_cdc_from_axi_d2 : std_logic;
signal Tx_FIFO_Empty_SPISR_cdc_from_spi_d1 : std_logic;
signal Tx_FIFO_Empty_SPISR_cdc_from_spi_d2 : std_logic;
signal drr_Overrun_int_cdc_from_spi_d1 : std_logic;
signal drr_Overrun_int_cdc_from_spi_d2 : std_logic;
signal drr_Overrun_int_cdc_from_spi_d3 : std_logic;
signal drr_Overrun_int_cdc_from_spi_d4 : std_logic;
signal SR_3_modf_cdc_from_axi_d1 : std_logic;
signal SR_3_modf_cdc_from_axi_d2 : std_logic;
signal SPISSR_cdc_from_axi_d1 : std_logic_vector(0 to (C_NUM_SS_BITS-1));
signal SPISSR_cdc_from_axi_d2 : std_logic_vector(0 to (C_NUM_SS_BITS-1));
signal spiXfer_done_cdc_from_spi_int_2 : std_logic;
signal spiXfer_done_d1 : std_logic;
signal spiXfer_done_d2, spiXfer_done_d3 : std_logic;
signal spisel_pulse_cdc_from_spi_int_2 : std_logic;
signal Tx_FIFO_Empty_cdc_from_axi_int_2 : std_logic;
signal Tx_FIFO_Empty_cdc_from_axi_d3 : std_logic;
signal drr_Overrun_int_cdc_from_spi_int_2 : std_logic;
signal Slave_MODF_strobe_cdc_from_spi_int_2 : std_logic;
signal modf_strobe_cdc_from_spi_int_2 : std_logic;
-- signal declaration
-- signal spisel_d1_reg_cdc_from_spi_d1 : std_logic;
-- signal spisel_d1_reg_cdc_from_spi_d2 : std_logic;
-- signal spiXfer_done_cdc_from_spi_d1 : std_logic;
-- signal spiXfer_done_cdc_from_spi_d2 : std_logic;
-- signal modf_strobe_cdc_from_spi_d1 : std_logic;
-- signal modf_strobe_cdc_from_spi_d2 : std_logic;
-- signal modf_strobe_cdc_from_spi_d3 : std_logic;
-- signal Slave_MODF_strobe_cdc_from_spi_d1 : std_logic;
-- signal Slave_MODF_strobe_cdc_from_spi_d2 : std_logic;
-- signal Slave_MODF_strobe_cdc_from_spi_d3 : std_logic;
-- signal receive_Data_cdc_from_spi_d1 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
-- signal receive_Data_cdc_from_spi_d2 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
-- signal dtr_underrun_cdc_from_spi_d1 : std_logic;
-- signal dtr_underrun_cdc_from_spi_d2 : std_logic;
-- signal transmit_Data_cdc_from_axi_d1 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
-- signal transmit_Data_cdc_from_axi_d2 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
-- signal spisel_pulse_cdc_from_spi_d1 : std_logic;
-- signal spisel_pulse_cdc_from_spi_d2 : std_logic;
-- signal spisel_pulse_cdc_from_spi_d3 : std_logic;
-- signal SPICR_0_LOOP_cdc_from_axi_d1 : std_logic;
-- signal SPICR_0_LOOP_cdc_from_axi_d2 : std_logic;
-- signal SPICR_1_SPE_cdc_from_axi_d1 : std_logic;
-- signal SPICR_1_SPE_cdc_from_axi_d2 : std_logic;
-- signal SPICR_2_MST_N_SLV_cdc_from_axi_d1 : std_logic;
-- signal SPICR_2_MST_N_SLV_cdc_from_axi_d2 : std_logic;
-- signal SPICR_3_CPOL_cdc_from_axi_d1 : std_logic;
-- signal SPICR_3_CPOL_cdc_from_axi_d2 : std_logic;
-- signal SPICR_4_CPHA_cdc_from_axi_d1 : std_logic;
-- signal SPICR_4_CPHA_cdc_from_axi_d2 : std_logic;
-- signal SPICR_5_TXFIFO_cdc_from_axi_d1 : std_logic;
-- signal SPICR_5_TXFIFO_cdc_from_axi_d2 : std_logic;
-- signal SPICR_7_SS_cdc_from_axi_d1 : std_logic;
-- signal SPICR_7_SS_cdc_from_axi_d2 : std_logic;
-- signal SPICR_8_TR_INHIBIT_cdc_from_axi_d1 : std_logic;
-- signal SPICR_8_TR_INHIBIT_cdc_from_axi_d2 : std_logic;
-- signal SPICR_9_LSB_cdc_from_axi_d1 : std_logic;
-- signal SPICR_9_LSB_cdc_from_axi_d2 : std_logic;
-- signal SPICR_bits_7_8_cdc_from_axi_d1 : std_logic_vector(1 downto 0);
-- signal SPICR_bits_7_8_cdc_from_axi_d2 : std_logic_vector(1 downto 0);
-- signal SPICR_6_RXFIFO_RST_cdc_from_axi_d1 : std_logic;
-- signal SPICR_6_RXFIFO_RST_cdc_from_axi_d2 : std_logic;
-- signal Tx_FIFO_Empty_cdc_from_axi_d1 : std_logic;
-- signal Tx_FIFO_Empty_cdc_from_axi_d2 : std_logic;
-- signal Tx_FIFO_Empty_SPISR_cdc_from_spi_d1 : std_logic;
-- signal Tx_FIFO_Empty_SPISR_cdc_from_spi_d2 : std_logic;
-- signal Tx_FIFO_Empty_SPISR_cdc_from_spi_d3 : std_logic;
-- signal Tx_FIFO_Empty_SPISR_cdc_from_spi_d4 : std_logic;
-- signal drr_Overrun_int_cdc_from_spi_d1 : std_logic;
-- signal drr_Overrun_int_cdc_from_spi_d2 : std_logic;
-- signal drr_Overrun_int_cdc_from_spi_d3 : std_logic;
-- signal SR_3_modf_cdc_from_axi_d1 : std_logic;
-- signal SR_3_modf_cdc_from_axi_d2 : std_logic;
-- signal SPISSR_cdc_from_axi_d1 : std_logic_vector(0 to (C_NUM_SS_BITS-1));
-- signal SPISSR_cdc_from_axi_d2 : std_logic_vector(0 to (C_NUM_SS_BITS-1));
-- signal spiXfer_done_cdc_from_spi_int_2 : std_logic;
-- signal spiXfer_done_d1 : std_logic;
-- signal spiXfer_done_d2, spiXfer_done_d3 : std_logic;
-- signal spisel_pulse_cdc_from_spi_int_2 : std_logic;
-- signal Tx_FIFO_Empty_cdc_from_axi_int_2 : std_logic;
-- signal Tx_FIFO_Empty_cdc_from_axi_d3 : std_logic;
-- signal drr_Overrun_int_cdc_from_spi_int_2 : std_logic;
-- signal Slave_MODF_strobe_cdc_from_spi_int_2 : std_logic;
-- signal modf_strobe_cdc_from_spi_int_2 : std_logic;
-- attribute ASYNC_REG : string;
-- attribute ASYNC_REG of SPISEL_D1_REG_SYNC_SPI_2_AXI_1 : label is "TRUE";
-- attribute ASYNC_REG of SYNC_SPIXFER_DONE_SYNC_SPI_2_AXI_1 : label is "TRUE";
-- attribute ASYNC_REG of TX_FIFO_EMPTY_SYNC_AXI_2_SPI_1 : label is "TRUE";
-- attribute ASYNC_REG of SLAVE_MODF_STROBE_SYNC_SPI_cdc_to_AXI_1: label is "TRUE";
-- attribute ASYNC_REG of MODF_STROBE_SYNC_SPI_cdc_to_AXI_1 : label is "TRUE";
-- attribute ASYNC_REG of DRR_OVERRUN_SYNC_SPI_cdc_to_AXI_1 : label is "TRUE";
-- attribute ASYNC_REG of SPICR_9_LSB_AX2S_1 : label is "TRUE";
-- attribute ASYNC_REG of SPICR_8_TR_INHIBIT_AX2S_1 : label is "TRUE";
-- attribute ASYNC_REG of SPICR_7_SS_AX2S_1 : label is "TRUE";
-- attribute ASYNC_REG of SPICR_6_RXFIFO_RST_AX2S_1 : label is "TRUE";
-- attribute ASYNC_REG of SPICR_5_TXFIFO_AX2S_1 : label is "TRUE";
-- attribute ASYNC_REG of SPICR_4_CPHA_AX2S_1 : label is "TRUE";
-- attribute ASYNC_REG of SPICR_3_CPOL_AX2S_1 : label is "TRUE";
-- attribute ASYNC_REG of SPICR_2_MST_N_SLV_AX2S_1 : label is "TRUE";
-- attribute ASYNC_REG of SPICR_1_SPE_AX2S_1 : label is "TRUE";
-- attribute ASYNC_REG of SPICR_0_LOOP_AX2S_1 : label is "TRUE";
-- attribute ASYNC_REG of SR_3_MODF_AX2S_1 : label is "TRUE";
constant LOGIC_CHANGE : integer range 0 to 1 := 1;
constant MTBF_STAGES_AXI2S : integer range 0 to 6 := 3 ;
constant MTBF_STAGES_S2AXI : integer range 0 to 6 := 4 ;
-----
begin
-----
-- SPI_AXI_EQUAL_GEN: AXI and SPI domain clocks are same
---------------------
--SPI_AXI_EQUAL_GEN: if C_AXI_SPI_CLK_EQ_DIFF = 0 generate
-----
--begin
-----
LOGIC_GENERATION_FDR : if (Async_Clk =0) generate
TX_FIFO_EMPTY_FOR_SPISR_SYNC_SPI_2_AXI: process(Bus2IP_Clk) is
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = '1')then
Tx_FIFO_Empty_SPISR_cdc_from_spi_d1 <= '1';
Tx_FIFO_Empty_SPISR_cdc_from_spi_d2 <= '1';
else
Tx_FIFO_Empty_SPISR_cdc_from_spi_d1 <= Tx_FIFO_Empty_SPISR_cdc_from_spi;
Tx_FIFO_Empty_SPISR_cdc_from_spi_d2 <= Tx_FIFO_Empty_SPISR_cdc_from_spi_d1;
end if;
end if;
end process TX_FIFO_EMPTY_FOR_SPISR_SYNC_SPI_2_AXI;
-----------------------------------------
Tx_FIFO_Empty_SPISR_cdc_to_axi <= Tx_FIFO_Empty_SPISR_cdc_from_spi_d2;
-------------------------------------------------
TX_FIFO_EMPTY_STRETCH_1: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_from_axi_cdc_to_spi = '1') then
Tx_FIFO_Empty_cdc_from_axi_int_2 <= '1';
else
Tx_FIFO_Empty_cdc_from_axi_int_2 <= Tx_FIFO_Empty_cdc_from_axi xor
Tx_FIFO_Empty_cdc_from_axi_int_2;
end if;
end if;
end process TX_FIFO_EMPTY_STRETCH_1;
TX_FIFO_EMPTY_SYNC_AXI_2_SPI_1: component FDR
generic map(INIT => '1'
)port map (
Q => Tx_FIFO_Empty_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => Tx_FIFO_Empty_cdc_from_axi_int_2,
R => Rst_from_axi_cdc_to_spi
);
TX_FIFO_EMPTY_SYNC_AXI_2_SPI_2: component FDR
generic map(INIT => '1'
)port map (
Q => Tx_FIFO_Empty_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => Tx_FIFO_Empty_cdc_from_axi_d1,
R => Rst_from_axi_cdc_to_spi
);
-- Tx_FIFO_Empty_cdc_to_spi <= Tx_FIFO_Empty_cdc_from_axi_d2 xor Tx_FIFO_Empty_cdc_from_axi_d1;
TX_FIFO_EMPTY_SYNC_AXI_2_SPI_3: component FDR
generic map(INIT => '1'
)port map (
Q => Tx_FIFO_Empty_cdc_from_axi_d3,
C => EXT_SPI_CLK,
D => Tx_FIFO_Empty_cdc_from_axi_d2,
R => Rst_from_axi_cdc_to_spi
);
Tx_FIFO_Empty_cdc_to_spi <= Tx_FIFO_Empty_cdc_from_axi_d2 xor Tx_FIFO_Empty_cdc_from_axi_d3;
-------------------------------------------------
SPISEL_D1_REG_SYNC_SPI_2_AXI_1: component FDR
port map (
Q => spisel_d1_reg_cdc_from_spi_d1,
C => Bus2IP_Clk,
D => spisel_d1_reg_cdc_from_spi,
R => Soft_Reset_op
);
SPISEL_D1_REG_SYNC_SPI_2_AXI_2: component FDR
port map (
Q => spisel_d1_reg_cdc_from_spi_d2,
C => Bus2IP_Clk,
D => spisel_d1_reg_cdc_from_spi_d1,
R => Soft_Reset_op
);
spisel_d1_reg_cdc_to_axi <= spisel_d1_reg_cdc_from_spi_d2;
SPISEL_PULSE_STRETCH_1: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_from_axi_cdc_to_spi = '1') then
spisel_pulse_cdc_from_spi_int_2 <= '0';
else
spisel_pulse_cdc_from_spi_int_2 <= spisel_pulse_cdc_from_spi xor
spisel_pulse_cdc_from_spi_int_2;
end if;
end if;
end process SPISEL_PULSE_STRETCH_1;
SPISEL_PULSE_SPI_2_AXI_1: component FDR
port map (
Q => spisel_pulse_cdc_from_spi_d1,
C => Bus2IP_Clk,
D => spisel_pulse_cdc_from_spi_int_2,
R => Soft_Reset_op
);
SPISEL_PULSE_SPI_2_AXI_2: component FDR
port map (
Q => spisel_pulse_cdc_from_spi_d2,
C => Bus2IP_Clk,
D => spisel_pulse_cdc_from_spi_d1,
R => Soft_Reset_op
);
SPISEL_PULSE_SPI_2_AXI_3: component FDR
port map (
Q => spisel_pulse_cdc_from_spi_d3,
C => Bus2IP_Clk,
D => spisel_pulse_cdc_from_spi_d2,
R => Soft_Reset_op
);
spisel_pulse_cdc_to_axi <= spisel_pulse_cdc_from_spi_d2 xor spisel_pulse_cdc_from_spi_d3;
---------------------------------------------
SPI_XFER_DONE_STRETCH_1: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_from_axi_cdc_to_spi = '1') then
spiXfer_done_cdc_from_spi_int_2 <= '0';
else
spiXfer_done_cdc_from_spi_int_2 <= spiXfer_done_cdc_from_spi xor
spiXfer_done_cdc_from_spi_int_2;
end if;
end if;
end process SPI_XFER_DONE_STRETCH_1;
SYNC_SPIXFER_DONE_SYNC_SPI_2_AXI_1: component FDR
generic map(INIT => '0'
)port map (
Q => spiXfer_done_d1,
C => Bus2IP_Clk,
D => spiXfer_done_cdc_from_spi_int_2,
R => Soft_Reset_op
);
SYNC_SPIXFER_DONE_SYNC_SPI_2_AXI_2: component FDR
generic map(INIT => '0'
)port map (
Q => spiXfer_done_d2,
C => Bus2IP_Clk,
D => spiXfer_done_d1,
R => Soft_Reset_op
);
SYNC_SPIXFER_DONE_SYNC_SPI_2_AXI_3: component FDR
generic map(INIT => '0'
)port map (
Q => spiXfer_done_d3,
C => Bus2IP_Clk,
D => spiXfer_done_d2,
R => Soft_Reset_op
);
spiXfer_done_cdc_to_axi <= spiXfer_done_d2 xor spiXfer_done_d3; --spiXfer_done_cdc_from_spi_d2;
-----------------------------------------------
MODF_STROBE_STRETCH_1: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_from_axi_cdc_to_spi = '1') then
modf_strobe_cdc_from_spi_int_2 <= '0';
else
modf_strobe_cdc_from_spi_int_2 <= modf_strobe_cdc_from_spi xor
modf_strobe_cdc_from_spi_int_2;
end if;
end if;
end process MODF_STROBE_STRETCH_1;
MODF_STROBE_SYNC_SPI_cdc_to_AXI_1: component FDR
generic map(INIT => '0'
)port map (
Q => modf_strobe_cdc_from_spi_d1,
C => Bus2IP_Clk,
D => modf_strobe_cdc_from_spi_int_2,
R => Soft_Reset_op
);
MODF_STROBE_SYNC_SPI_cdc_to_AXI_2: component FDR
generic map(INIT => '0'
)port map (
Q => modf_strobe_cdc_from_spi_d2,
C => Bus2IP_Clk,
D => modf_strobe_cdc_from_spi_d1,
R => Soft_Reset_op
);
MODF_STROBE_SYNC_SPI_cdc_to_AXI_3: component FDR
generic map(INIT => '0'
)port map (
Q => modf_strobe_cdc_from_spi_d3,
C => Bus2IP_Clk,
D => modf_strobe_cdc_from_spi_d2,
R => Soft_Reset_op
);
modf_strobe_cdc_to_axi <= modf_strobe_cdc_from_spi_d2 xor modf_strobe_cdc_from_spi_d3; --spiXfer_done_cdc_from_spi_d2;
---------------------------------------------------------
SLAVE_MODF_STROBE_STRETCH_1: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_from_axi_cdc_to_spi = '1') then
Slave_MODF_strobe_cdc_from_spi_int_2 <= '0';
else
Slave_MODF_strobe_cdc_from_spi_int_2 <= Slave_MODF_strobe_cdc_from_spi xor
Slave_MODF_strobe_cdc_from_spi_int_2;
end if;
end if;
end process SLAVE_MODF_STROBE_STRETCH_1;
SLAVE_MODF_STROBE_SYNC_SPI_cdc_to_AXI_1: component FDR
generic map(INIT => '0'
)port map (
Q => Slave_MODF_strobe_cdc_from_spi_d1,
C => Bus2IP_Clk,
D => Slave_MODF_strobe_cdc_from_spi_int_2,
R => Soft_Reset_op
);
SLAVE_MODF_STROBE_SYNC_SPI_cdc_to_AXI_2: component FDR
generic map(INIT => '0'
)port map (
Q => Slave_MODF_strobe_cdc_from_spi_d2,
C => Bus2IP_Clk,
D => Slave_MODF_strobe_cdc_from_spi_d1,
R => Soft_Reset_op
);
SLAVE_MODF_STROBE_SYNC_SPI_cdc_to_AXI_3: component FDR
generic map(INIT => '0'
)port map (
Q => Slave_MODF_strobe_cdc_from_spi_d3,
C => Bus2IP_Clk,
D => Slave_MODF_strobe_cdc_from_spi_d2,
R => Soft_Reset_op
);
Slave_MODF_strobe_cdc_to_axi <= Slave_MODF_strobe_cdc_from_spi_d2 xor
Slave_MODF_strobe_cdc_from_spi_d3; --spiXfer_done_cdc_from_spi_d2;
-----------------------------------------------
---------------------------------------------------------
RECEIVE_DATA_SYNC_SPI_cdc_to_AXI_P: process(Bus2IP_Clk) is
-------------------------
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1')then
receive_Data_cdc_from_spi_d1 <= receive_Data_cdc_from_spi;
receive_Data_cdc_from_spi_d2 <= receive_Data_cdc_from_spi_d1;
end if;
end process RECEIVE_DATA_SYNC_SPI_cdc_to_AXI_P;
-------------------------------------------
receive_Data_cdc_to_axi <= receive_Data_cdc_from_spi_d2;
-----------------------------------------------
DRR_OVERRUN_STRETCH_1: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_from_axi_cdc_to_spi = '1') then
drr_Overrun_int_cdc_from_spi_int_2 <= '0';
else
drr_Overrun_int_cdc_from_spi_int_2 <= drr_Overrun_int_cdc_from_spi xor
drr_Overrun_int_cdc_from_spi_int_2;
end if;
end if;
end process DRR_OVERRUN_STRETCH_1;
DRR_OVERRUN_SYNC_SPI_cdc_to_AXI_1: component FDR
generic map(INIT => '0'
)port map (
Q => drr_Overrun_int_cdc_from_spi_d1,
C => Bus2IP_Clk,
D => drr_Overrun_int_cdc_from_spi_int_2,
R => Soft_Reset_op
);
DRR_OVERRUN_SYNC_SPI_cdc_to_AXI_2: component FDR
generic map(INIT => '0'
)port map (
Q => drr_Overrun_int_cdc_from_spi_d2,
C => Bus2IP_Clk,
D => drr_Overrun_int_cdc_from_spi_d1,
R => Soft_Reset_op
);
DRR_OVERRUN_SYNC_SPI_cdc_to_AXI_3: component FDR
generic map(INIT => '0'
)port map (
Q => drr_Overrun_int_cdc_from_spi_d3,
C => Bus2IP_Clk,
D => drr_Overrun_int_cdc_from_spi_d2,
R => Soft_Reset_op
);
drr_Overrun_int_cdc_to_axi <= drr_Overrun_int_cdc_from_spi_d2 xor drr_Overrun_int_cdc_from_spi_d3; --spiXfer_done_cdc_from_spi_d2;
-----------------------------------------------
DTR_UNDERRUN_SYNC_SPI_2_AXI_1: component FDR
generic map(INIT => '0'
)port map (
Q => dtr_underrun_cdc_from_spi_d1,
C => Bus2IP_Clk,
D => dtr_underrun_cdc_from_spi,
R => Soft_Reset_op
);
DTR_UNDERRUN_SYNC_SPI_2_AXI_2: component FDR
generic map(INIT => '0'
)port map (
Q => dtr_underrun_cdc_from_spi_d2,
C => Bus2IP_Clk,
D => dtr_underrun_cdc_from_spi_d1,
R => Soft_Reset_op
);
dtr_underrun_cdc_to_axi <= dtr_underrun_cdc_from_spi_d2;
-----------------------------------------------
TR_DATA_SYNC_AX2SP_GEN: for i in 0 to (C_NUM_TRANSFER_BITS-1) generate
attribute ASYNC_REG : string;
attribute ASYNC_REG of TR_DATA_SYNC_AX2SP_1: label is "TRUE";
-----
begin
-----
TR_DATA_SYNC_AX2SP_1: component FDR
generic map(INIT => '0'
)port map (
Q => transmit_Data_cdc_from_axi_d1(i),
C => EXT_SPI_CLK,
D => transmit_Data_cdc_from_axi(i),
R => Rst_from_axi_cdc_to_spi
);
TR_DATA_SYNC_AX2SP_2: component FDR
generic map(INIT => '0'
)port map (
Q => transmit_Data_cdc_from_axi_d2(i),
C => EXT_SPI_CLK,
D => transmit_Data_cdc_from_axi_d1(i),
R => Rst_from_axi_cdc_to_spi
);
end generate TR_DATA_SYNC_AX2SP_GEN;
transmit_Data_cdc_to_spi <= transmit_Data_cdc_from_axi_d2;
-----------------------------------------------
SPICR_0_LOOP_AX2S_1: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_0_LOOP_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_0_LOOP_cdc_from_axi,
R => Rst_from_axi_cdc_to_spi
);
SPICR_0_LOOP_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_0_LOOP_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SPICR_0_LOOP_cdc_from_axi_d1,
R => Rst_from_axi_cdc_to_spi
);
SPICR_0_LOOP_cdc_to_spi <= SPICR_0_LOOP_cdc_from_axi_d2;
-----------------------------------------------
SPICR_1_SPE_AX2S_1: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_1_SPE_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_1_SPE_cdc_from_axi,
R => Rst_from_axi_cdc_to_spi
);
SPICR_1_SPE_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_1_SPE_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SPICR_1_SPE_cdc_from_axi_d1,
R => Rst_from_axi_cdc_to_spi
);
SPICR_1_SPE_cdc_to_spi <= SPICR_1_SPE_cdc_from_axi_d2;
---------------------------------------------
SPICR_2_MST_N_SLV_AX2S_1: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_2_MST_N_SLV_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_2_MST_N_SLV_cdc_from_axi,
R => Rst_from_axi_cdc_to_spi
);
SPICR_2_MST_N_SLV_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_2_MST_N_SLV_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SPICR_2_MST_N_SLV_cdc_from_axi_d1,
R => Rst_from_axi_cdc_to_spi
);
SPICR_2_MST_N_SLV_cdc_to_spi <= SPICR_2_MST_N_SLV_cdc_from_axi_d2;
---------------------------------------------------------
SPICR_3_CPOL_AX2S_1: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_3_CPOL_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_3_CPOL_cdc_from_axi,
R => Rst_from_axi_cdc_to_spi
);
SPICR_3_CPOL_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_3_CPOL_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SPICR_3_CPOL_cdc_from_axi_d1,
R => Rst_from_axi_cdc_to_spi
);
SPICR_3_CPOL_cdc_to_spi <= SPICR_3_CPOL_cdc_from_axi_d2;
-----------------------------------------------
SPICR_4_CPHA_AX2S_1: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_4_CPHA_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_4_CPHA_cdc_from_axi,
R => Rst_from_axi_cdc_to_spi
);
SPICR_4_CPHA_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_4_CPHA_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SPICR_4_CPHA_cdc_from_axi_d1,
R => Rst_from_axi_cdc_to_spi
);
SPICR_4_CPHA_cdc_to_spi <= SPICR_4_CPHA_cdc_from_axi_d2;
-----------------------------------------------
SPICR_5_TXFIFO_AX2S_1: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_5_TXFIFO_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_5_TXFIFO_cdc_from_axi,
R => Rst_from_axi_cdc_to_spi
);
SPICR_5_TXFIFO_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_5_TXFIFO_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SPICR_5_TXFIFO_cdc_from_axi_d1,
R => Rst_from_axi_cdc_to_spi
);
SPICR_5_TXFIFO_cdc_to_spi <= SPICR_5_TXFIFO_cdc_from_axi_d2;
---------------------------------------------------
SPICR_6_RXFIFO_RST_AX2S_1: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_6_RXFIFO_RST_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_6_RXFIFO_RST_cdc_from_axi,
R => Rst_from_axi_cdc_to_spi
);
SPICR_6_RXFIFO_RST_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_6_RXFIFO_RST_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SPICR_6_RXFIFO_RST_cdc_from_axi_d1,
R => Rst_from_axi_cdc_to_spi
);
SPICR_6_RXFIFO_RST_cdc_to_spi <= SPICR_6_RXFIFO_RST_cdc_from_axi_d2;
-----------------------------------------------------------
SPICR_7_SS_AX2S_1: component FDR
generic map(INIT => '1'
)port map (
Q => SPICR_7_SS_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_7_SS_cdc_from_axi,
R => Rst_from_axi_cdc_to_spi
);
SPICR_7_SS_AX2S_2: component FDR
generic map(INIT => '1'
)port map (
Q => SPICR_7_SS_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SPICR_7_SS_cdc_from_axi_d1,
R => Rst_from_axi_cdc_to_spi
);
SPICR_7_SS_cdc_to_spi <= SPICR_7_SS_cdc_from_axi_d2;
-------------------------------------------
SPICR_8_TR_INHIBIT_AX2S_1: component FDR
generic map(INIT => '1'
)port map (
Q => SPICR_8_TR_INHIBIT_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_8_TR_INHIBIT_cdc_from_axi,
R => Rst_from_axi_cdc_to_spi
);
SPICR_8_TR_INHIBIT_AX2S_2: component FDR
generic map(INIT => '1'
)port map (
Q => SPICR_8_TR_INHIBIT_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SPICR_8_TR_INHIBIT_cdc_from_axi_d1,
R => Rst_from_axi_cdc_to_spi
);
SPICR_8_TR_INHIBIT_cdc_to_spi <= SPICR_8_TR_INHIBIT_cdc_from_axi_d2;
-----------------------------------------------------------
SPICR_9_LSB_AX2S_1: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_9_LSB_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_9_LSB_cdc_from_axi,
R => Rst_from_axi_cdc_to_spi
);
SPICR_9_LSB_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_9_LSB_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SPICR_9_LSB_cdc_from_axi_d1,
R => Rst_from_axi_cdc_to_spi
);
SPICR_9_LSB_cdc_to_spi <= SPICR_9_LSB_cdc_from_axi_d2;
---------------------------------------------
SPICR_BITS_7_8_SYNC_GEN: for i in 1 downto 0 generate
attribute ASYNC_REG : string;
attribute ASYNC_REG of SPICR_BITS_7_8_AX2S_1 : label is "TRUE";
begin
-----
SPICR_BITS_7_8_AX2S_1: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_bits_7_8_cdc_from_axi_d1(i),
C => EXT_SPI_CLK,
D => SPICR_bits_7_8_cdc_from_axi(i),
R => Rst_from_axi_cdc_to_spi
);
SPICR_BITS_7_8_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_bits_7_8_cdc_from_axi_d2(i),
C => EXT_SPI_CLK,
D => SPICR_bits_7_8_cdc_from_axi_d1(i),
R => Rst_from_axi_cdc_to_spi
);
end generate SPICR_BITS_7_8_SYNC_GEN;
-------------------------------------
SPICR_bits_7_8_cdc_to_spi <= SPICR_bits_7_8_cdc_from_axi_d2;
---------------------------------------------------
SR_3_MODF_AX2S_1: component FDR
generic map(INIT => '0'
)port map (
Q => SR_3_modf_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SR_3_modf_cdc_from_axi,
R => Rst_from_axi_cdc_to_spi
);
SR_3_MODF_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => SR_3_modf_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SR_3_modf_cdc_from_axi_d1,
R => Rst_from_axi_cdc_to_spi
);
SR_3_modf_cdc_to_spi <= SR_3_modf_cdc_from_axi_d2;
-----------------------------------------
SPISSR_SYNC_GEN: for i in 0 to C_NUM_SS_BITS-1 generate
attribute ASYNC_REG : string;
attribute ASYNC_REG of SPISSR_AX2S_1 : label is "TRUE";
-----
begin
-----
SPISSR_AX2S_1: component FDR
generic map(INIT => '1'
)port map (
Q => SPISSR_cdc_from_axi_d1(i),
C => EXT_SPI_CLK,
D => SPISSR_cdc_from_axi(i),
R => Rst_from_axi_cdc_to_spi
);
SPISSR_SYNC_AXI_2_SPI_2: component FDR
generic map(INIT => '1'
)port map (
Q => SPISSR_cdc_from_axi_d2(i),
C => EXT_SPI_CLK,
D => SPISSR_cdc_from_axi_d1(i),
R => Rst_from_axi_cdc_to_spi
);
end generate SPISSR_SYNC_GEN;
SPISSR_cdc_to_spi <= SPISSR_cdc_from_axi_d2;
-----------------------------------
end generate LOGIC_GENERATION_FDR ;
--============================================================================================================
LOGIC_GENERATION_CDC : if (Async_Clk =1) generate
--============================================================================================================
-- Tx_FIFO_Empty_cdc_from_axi <= Tx_FIFO_Empty_cdc_from_axi;
-- Tx_FIFO_Empty_cdc_to_spi <= Tx_FIFO_Empty_cdc_cdc_to_spi;
-- Tx_FIFO_Empty_SPISR_cdc_from_spi <= Tx_FIFO_Empty_SPISR_cdc_from_spi;
-- Tx_FIFO_Empty_SPISR_cdc_to_axi <= Tx_FIFO_Empty_SPISR_cdc_cdc_to_axi;
-- spisel_d1_reg_cdc_from_spi <= spisel_d1_reg_cdc_from_spi;
-- spisel_d1_reg_cdc_to_axi <= spisel_d1_reg_cdc_cdc_to_axi;
-- spisel_pulse_cdc_from_spi <= spisel_pulse_cdc_from_spi;
-- spisel_pulse_cdc_to_axi <= spisel_pulse_cdc_cdc_to_axi;
-- spiXfer_done_cdc_from_spi <= spiXfer_done_cdc_from_spi;
-- spiXfer_done_cdc_to_axi <= spiXfer_done_cdc_cdc_to_axi;
-- modf_strobe_cdc_from_spi <= modf_strobe_cdc_from_spi;
-- modf_strobe_cdc_to_axi <= modf_strobe_cdc_cdc_to_axi;
-- Slave_MODF_strobe_cdc_from_spi <= Slave_MODF_strobe_cdc_from_spi;
-- Slave_MODF_strobe_cdc_to_axi <= Slave_MODF_strobe_cdc_cdc_to_axi;
-- receive_Data_cdc_from_spi <= receive_Data_cdc_from_spi;
-- receive_Data_cdc_to_axi <= receive_Data_cdc_cdc_to_axi;
-- drr_Overrun_int_cdc_from_spi <= drr_Overrun_int_cdc_from_spi;
-- drr_Overrun_int_cdc_to_axi <= drr_Overrun_int_cdc_cdc_to_axi;
-- dtr_underrun_cdc_from_spi <= dtr_underrun_cdc_from_spi;
-- dtr_underrun_cdc_to_axi <= dtr_underrun_cdc_cdc_to_axi;
-- transmit_Data_cdc_from_axi <= transmit_Data_cdc_from_axi;
-- transmit_Data_cdc_to_spi <= transmit_Data_cdc_cdc_to_spi;
-- SPICR_0_LOOP_cdc_from_axi <= SPICR_0_LOOP_cdc_from_axi;
-- SPICR_0_LOOP_cdc_to_spi <= SPICR_0_LOOP_cdc_cdc_to_spi;
-- SPICR_1_SPE_cdc_from_axi <= SPICR_1_SPE_cdc_from_axi;
-- SPICR_1_SPE_cdc_to_spi <= SPICR_1_SPE_cdc_cdc_to_spi;
-- SPICR_2_MST_N_SLV_cdc_from_axi <= SPICR_2_MST_N_SLV_cdc_from_axi;
-- SPICR_2_MST_N_SLV_cdc_to_spi <= SPICR_2_MST_N_SLV_cdc_cdc_to_spi;
-- SPICR_3_CPOL_cdc_from_axi <= SPICR_3_CPOL_cdc_from_axi;
-- SPICR_3_CPOL_cdc_to_spi <= SPICR_3_CPOL_cdc_cdc_to_spi;
-- SPICR_4_CPHA_cdc_from_axi <= SPICR_4_CPHA_cdc_from_axi;
-- SPICR_4_CPHA_cdc_to_spi <= SPICR_4_CPHA_cdc_cdc_to_spi;
-- SPICR_5_TXFIFO_cdc_from_axi <= SPICR_5_TXFIFO_cdc_from_axi;
-- SPICR_5_TXFIFO_cdc_to_spi <= SPICR_5_TXFIFO_cdc_cdc_to_spi;
-- SPICR_6_RXFIFO_RST_cdc_from_axi <= SPICR_6_RXFIFO_RST_cdc_from_axi;
-- SPICR_6_RXFIFO_RST_cdc_to_spi <= SPICR_6_RXFIFO_RST_cdc_cdc_to_spi;
-- SPICR_7_SS_cdc_from_axi <= SPICR_7_SS_cdc_from_axi;
-- SPICR_7_SS_cdc_to_spi <= SPICR_7_SS_cdc_cdc_to_spi;
-- SPICR_8_TR_INHIBIT_cdc_from_axi <= SPICR_8_TR_INHIBIT_cdc_from_axi;
-- SPICR_8_TR_INHIBIT_cdc_to_spi <= SPICR_8_TR_INHIBIT_cdc_cdc_to_spi;
-- SPICR_9_LSB_cdc_from_axi <= SPICR_9_LSB_cdc_from_axi;
-- SPICR_9_LSB_cdc_to_spi <= SPICR_9_LSB_cdc_cdc_to_spi;
-- SPICR_bits_7_8_cdc_from_axi <= SPICR_bits_7_8_cdc_from_axi;
-- SPICR_bits_7_8_cdc_to_spi <= SPICR_bits_7_8_cdc_cdc_to_spi;
-- SR_3_modf_cdc_from_axi <= SR_3_modf_cdc_from_axi;
-- SR_3_modf_cdc_to_spi <= SR_3_modf_cdc_cdc_to_spi;
-- SPISSR_cdc_from_axi <= SPISSR_cdc_from_axi;
-- SPISSR_cdc_to_spi <= SPISSR_cdc_cdc_to_spi;
--============================================================================================================
-- all the signals pass through FF with reset before CDC_SYNC module to initialise the value of the signal
-- at its reset state. As many signals coming from bram have initial value of XX.
TX_FIFO_EMPTY_FOR_SPISR_SYNC_SPI_2_AXI_CDC : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_from_axi_cdc_to_spi ,
prmry_in => Tx_FIFO_Empty_SPISR_cdc_from_spi ,
scndry_aclk => Bus2IP_Clk ,
prmry_vect_in => (others => '0') ,
scndry_resetn => Soft_Reset_op ,
scndry_out => Tx_FIFO_Empty_SPISR_cdc_to_axi
);
----------------------------------------------------------------------------------------------------------
TX_FIFO_EMPTY_STRETCH_1: process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk= '1') then
if(Soft_Reset_op = '1') then
Tx_FIFO_Empty_cdc_from_axi_int_2 <= '1';
else
Tx_FIFO_Empty_cdc_from_axi_int_2 <= Tx_FIFO_Empty_cdc_from_axi xor
Tx_FIFO_Empty_cdc_from_axi_int_2;
end if;
end if;
end process TX_FIFO_EMPTY_STRETCH_1;
TX_FIFO_EMPTY_SYNC_AXI_2_SPI_CDC : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1, -- 2 is ack based level sync
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => Tx_FIFO_Empty_cdc_from_axi_int_2,--Tx_FIFO_Empty_cdc_from_axi_d1 ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => Tx_FIFO_Empty_cdc_from_axi_d2--Tx_FIFO_Empty_cdc_to_spi
);
TX_FIFO_EMPTY_STRETCH_1_CDC: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
Tx_FIFO_Empty_cdc_from_axi_d3 <= Tx_FIFO_Empty_cdc_from_axi_d2;
end if;
end process TX_FIFO_EMPTY_STRETCH_1_CDC;
Tx_FIFO_Empty_cdc_to_spi <= Tx_FIFO_Empty_cdc_from_axi_d2 xor Tx_FIFO_Empty_cdc_from_axi_d3;
----------------------------------------------------------------------------------------------------------
SPISEL_D1_REG_SYNC_SPI_2_AXI_1_CDC: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_from_axi_cdc_to_spi ,
prmry_in => spisel_d1_reg_cdc_from_spi ,
scndry_aclk => Bus2IP_Clk ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Soft_Reset_op ,
scndry_out => spisel_d1_reg_cdc_to_axi
);
-----------------------------------------------------------------------------------------------------------
SPISEL_PULSE_STRETCH_1_CDC: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_from_axi_cdc_to_spi = '1') then
spisel_pulse_cdc_from_spi_int_2 <= '0';
--spisel_pulse_cdc_from_spi_d1 <= '0';
else
spisel_pulse_cdc_from_spi_int_2 <= spisel_pulse_cdc_from_spi xor
spisel_pulse_cdc_from_spi_int_2;
--spisel_pulse_cdc_from_spi_d1 <= spisel_pulse_cdc_from_spi_int_2;
end if;
end if;
end process SPISEL_PULSE_STRETCH_1_CDC;
SPISEL_PULSE_SPI_2_AXI_1_CDC: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 2 is ack based level sync
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_from_axi_cdc_to_spi ,
prmry_in => spisel_pulse_cdc_from_spi_int_2 ,
scndry_aclk => Bus2IP_Clk ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Soft_Reset_op ,
scndry_out => spisel_pulse_cdc_from_spi_d2
);
SPISEL_PULSE_STRETCH_1: process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
spisel_pulse_cdc_from_spi_d3 <= spisel_pulse_cdc_from_spi_d2;
end if;
end process SPISEL_PULSE_STRETCH_1;
spisel_pulse_cdc_to_axi <= spisel_pulse_cdc_from_spi_d2 xor spisel_pulse_cdc_from_spi_d3;
--------------------------------------------------------------------------------------------------------------
SPI_XFER_DONE_STRETCH_1_CDC: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_from_axi_cdc_to_spi = '1') then
spiXfer_done_cdc_from_spi_int_2 <= '0';
-- spiXfer_done_d2 <= '0';
else
spiXfer_done_cdc_from_spi_int_2 <= spiXfer_done_cdc_from_spi xor
spiXfer_done_cdc_from_spi_int_2;
-- spiXfer_done_d2 <= spiXfer_done_cdc_from_spi_int_2;
end if;
end if;
end process SPI_XFER_DONE_STRETCH_1_CDC;
SYNC_SPIXFER_DONE_SYNC_SPI_2_AXI_1_CDC: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 2 is ack based level sync
C_RESET_STATE => 0 ,-- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_from_axi_cdc_to_spi ,
prmry_in => spiXfer_done_cdc_from_spi_int_2,--spiXfer_done_d2 ,
scndry_aclk => Bus2IP_Clk ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Soft_Reset_op ,
scndry_out => spiXfer_done_d2--spiXfer_done_cdc_to_axi
);
SPI_XFER_DONE_STRETCH_1: process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk= '1') then
spiXfer_done_d3 <= spiXfer_done_d2 ;
end if;
end process SPI_XFER_DONE_STRETCH_1;
spiXfer_done_cdc_to_axi <= spiXfer_done_d2 xor spiXfer_done_d3;
--------------------------------------------------------------------------------------------------------------
MODF_STROBE_STRETCH_1_CDC: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_from_axi_cdc_to_spi = '1') then
modf_strobe_cdc_from_spi_int_2 <= '0';
--modf_strobe_cdc_from_spi_d1 <= '0';
else
modf_strobe_cdc_from_spi_int_2 <= modf_strobe_cdc_from_spi xor
modf_strobe_cdc_from_spi_int_2;
-- modf_strobe_cdc_from_spi_d1 <= modf_strobe_cdc_from_spi_int_2;
end if;
end if;
end process MODF_STROBE_STRETCH_1_CDC;
MODF_STROBE_SYNC_SPI_cdc_to_AXI_1_CDC: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 2 is ack based level sync
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_from_axi_cdc_to_spi ,
prmry_in => modf_strobe_cdc_from_spi_int_2,--modf_strobe_cdc_from_spi_d1 ,
scndry_aclk => Bus2IP_Clk ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Soft_Reset_op ,
scndry_out => modf_strobe_cdc_from_spi_d2--modf_strobe_cdc_to_axi
);
MODF_STROBE_STRETCH_1: process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk= '1') then
modf_strobe_cdc_from_spi_d3 <= modf_strobe_cdc_from_spi_d2 ;
end if;
end process MODF_STROBE_STRETCH_1;
modf_strobe_cdc_to_axi <= modf_strobe_cdc_from_spi_d2 xor modf_strobe_cdc_from_spi_d3;
----------------------------------------------------------------------------------------------------------------
SLAVE_MODF_STROBE_STRETCH_1_CDC: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_from_axi_cdc_to_spi = '1') then
Slave_MODF_strobe_cdc_from_spi_int_2 <= '0';
-- Slave_MODF_strobe_cdc_from_spi_d1 <= '0';
else
Slave_MODF_strobe_cdc_from_spi_int_2 <= Slave_MODF_strobe_cdc_from_spi xor
Slave_MODF_strobe_cdc_from_spi_int_2;
-- Slave_MODF_strobe_cdc_from_spi_d1 <= Slave_MODF_strobe_cdc_from_spi_int_2;
end if;
end if;
end process SLAVE_MODF_STROBE_STRETCH_1_CDC;
SLAVE_MODF_STROBE_SYNC_SPI_cdc_to_AXI_1_CDC: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 2 is ack based level sync
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_from_axi_cdc_to_spi ,
prmry_in => Slave_MODF_strobe_cdc_from_spi_int_2 ,
scndry_aclk => Bus2IP_Clk ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Soft_Reset_op ,
scndry_out => Slave_MODF_strobe_cdc_from_spi_d2
);
SLAVE_MODF_STROBE_STRETCH_1: process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk= '1') then
Slave_MODF_strobe_cdc_from_spi_d3 <= Slave_MODF_strobe_cdc_from_spi_d2 ;
end if;
end process SLAVE_MODF_STROBE_STRETCH_1;
Slave_MODF_strobe_cdc_to_axi <= Slave_MODF_strobe_cdc_from_spi_d2 xor
Slave_MODF_strobe_cdc_from_spi_d3;
-----------------------------------------------------------------------------------------------------
RECEIVE_DATA_SYNC_SPI_cdc_to_AXI_P_CDC: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 0 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => C_NUM_TRANSFER_BITS ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => EXT_SPI_CLK,
prmry_resetn => Rst_from_axi_cdc_to_spi,
prmry_vect_in => receive_Data_cdc_from_spi,
scndry_aclk => Bus2IP_Clk,
prmry_in => '0',
scndry_resetn => Soft_Reset_op,
scndry_vect_out => receive_Data_cdc_to_axi
);
-------------------------------------------------------------------------------------------------------
DRR_OVERRUN_STRETCH_1: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_from_axi_cdc_to_spi = '1') then
drr_Overrun_int_cdc_from_spi_int_2 <= '0';
else
drr_Overrun_int_cdc_from_spi_int_2 <= drr_Overrun_int_cdc_from_spi xor
drr_Overrun_int_cdc_from_spi_int_2;
end if;
end if;
end process DRR_OVERRUN_STRETCH_1;
DRR_OVERRUN_SYNC_SPI_cdc_to_AXI_1: component FDR
generic map(INIT => '0'
)port map (
Q => drr_Overrun_int_cdc_from_spi_d1,
C => Bus2IP_Clk,
D => drr_Overrun_int_cdc_from_spi_int_2,
R => Soft_Reset_op
);
DRR_OVERRUN_SYNC_SPI_cdc_to_AXI_2: component FDR
generic map(INIT => '0'
)port map (
Q => drr_Overrun_int_cdc_from_spi_d2,
C => Bus2IP_Clk,
D => drr_Overrun_int_cdc_from_spi_d1,
R => Soft_Reset_op
);
DRR_OVERRUN_SYNC_SPI_cdc_to_AXI_3: component FDR
generic map(INIT => '0'
)port map (
Q => drr_Overrun_int_cdc_from_spi_d3,
C => Bus2IP_Clk,
D => drr_Overrun_int_cdc_from_spi_d2,
R => Soft_Reset_op
);
DRR_OVERRUN_SYNC_SPI_cdc_to_AXI_4: component FDR
generic map(INIT => '0'
)port map (
Q => drr_Overrun_int_cdc_from_spi_d4,
C => Bus2IP_Clk,
D => drr_Overrun_int_cdc_from_spi_d3,
R => Soft_Reset_op
);
drr_Overrun_int_cdc_to_axi <= drr_Overrun_int_cdc_from_spi_d4 xor drr_Overrun_int_cdc_from_spi_d3;
-------------------------------------------------------------------------------------------------------
DTR_UNDERRUN_SYNC_SPI_2_AXI_1_CDC: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1 ,-- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_from_axi_cdc_to_spi ,
prmry_in => dtr_underrun_cdc_from_spi ,
scndry_aclk => Bus2IP_Clk ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Soft_Reset_op ,
scndry_out => dtr_underrun_cdc_to_axi
);
-------------------------------------------------------------------------------------------------------
SPICR_0_LOOP_AX2S_1_CDC: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SPICR_0_LOOP_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => SPICR_0_LOOP_cdc_to_spi
);
------------------------------------------------------------------------------------------------------
SPICR_1_SPE_AX2S_1_CDC: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SPICR_1_SPE_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => SPICR_1_SPE_cdc_to_spi
);
----------------------------------------------------------------------------------------------------
SPICR_2_MST_N_SLV_AX2S_1_CDC: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SPICR_2_MST_N_SLV_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => SPICR_2_MST_N_SLV_cdc_to_spi
);
--------------------------------------------------------------------------------------------------
SPICR_3_CPOL_AX2S_1_CDC: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SPICR_3_CPOL_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => SPICR_3_CPOL_cdc_to_spi
);
--------------------------------------------------------------------------------------------------
SPICR_4_CPHA_AX2S_1_CDC: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SPICR_4_CPHA_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => SPICR_4_CPHA_cdc_to_spi
);
--------------------------------------------------------------------------------------------------
SPICR_5_TXFIFO_AX2S_1_CDC: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SPICR_5_TXFIFO_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => SPICR_5_TXFIFO_cdc_to_spi
);
--------------------------------------------------------------------------------------------------
SPICR_6_RXFIFO_RST_AX2S_1_CDC: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SPICR_6_RXFIFO_RST_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => SPICR_6_RXFIFO_RST_cdc_to_spi
);
--------------------------------------------------------------------------------------------------
SPICR_7_SS_AX2S_1_CDC: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SPICR_7_SS_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => SPICR_7_SS_cdc_to_spi
);
--------------------------------------------------------------------------------------------------
SPICR_8_TR_INHIBIT_AX2S_1_CDC: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SPICR_8_TR_INHIBIT_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => SPICR_8_TR_INHIBIT_cdc_to_spi
);
--------------------------------------------------------------------------------------------------
SPICR_9_LSB_AX2S_1_CDC: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SPICR_9_LSB_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => SPICR_9_LSB_cdc_to_spi
);
-----------------------------------------------------------------------------------------------------
TR_DATA_SYNC_AX2SP_GEN_CDC: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 0 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => C_NUM_TRANSFER_BITS ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk,
prmry_resetn => Soft_Reset_op,
prmry_vect_in => transmit_Data_cdc_from_axi,
scndry_aclk => EXT_SPI_CLK,
prmry_in => '0' ,
scndry_resetn => Rst_from_axi_cdc_to_spi,
scndry_vect_out => transmit_Data_cdc_to_spi
);
--------------------------------------------------------------------------------------------------
SR_3_MODF_AX2S_1_CDC: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SR_3_modf_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => SR_3_modf_cdc_to_spi
);
-----------------------------------------------------------------------------------------------------
SPISSR_SYNC_GEN_CDC: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 0 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => C_NUM_SS_BITS ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk,
prmry_resetn => Soft_Reset_op,
prmry_vect_in => SPISSR_cdc_from_axi,
scndry_aclk => EXT_SPI_CLK,
prmry_in => '0' ,
scndry_resetn => Rst_from_axi_cdc_to_spi,
scndry_vect_out => SPISSR_cdc_to_spi
);
---------------------------------------------
SPICR_BITS_7_8_SYNC_GEN_CDC: for i in 1 downto 0 generate
attribute ASYNC_REG : string;
attribute ASYNC_REG of SPICR_BITS_7_8_AX2S_1_CDC : label is "TRUE";
begin
SPICR_BITS_7_8_AX2S_1_CDC: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk,
prmry_resetn => Soft_Reset_op,
prmry_in => SPICR_bits_7_8_cdc_from_axi(i),
scndry_aclk => EXT_SPI_CLK,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi,
scndry_out => SPICR_bits_7_8_cdc_from_axi_d2(i)
);
-----------------------------------------
end generate SPICR_BITS_7_8_SYNC_GEN_CDC;
SPICR_bits_7_8_cdc_to_spi <= SPICR_bits_7_8_cdc_from_axi_d2;
end generate LOGIC_GENERATION_CDC;
end architecture imp;
| gpl-2.0 | 7d76727bf7319b0a8500909eee5d35de | 0.421208 | 3.767535 | false | false | false | false |
airabinovich/finalArquitectura | RAM/ipcore_dir/RAM_ram_bank/example_design/RAM_ram_bank_prod.vhd | 1 | 10,092 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: RAM_ram_bank_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan6
-- C_XDEVICEFAMILY : spartan6
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 0
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 0
-- C_INIT_FILE_NAME : no_coe_file_loaded
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 4
-- C_READ_WIDTH_A : 4
-- C_WRITE_DEPTH_A : 16
-- C_READ_DEPTH_A : 16
-- C_ADDRA_WIDTH : 4
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 4
-- C_READ_WIDTH_B : 4
-- C_WRITE_DEPTH_B : 16
-- C_READ_DEPTH_B : 16
-- C_ADDRB_WIDTH : 4
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY RAM_ram_bank_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END RAM_ram_bank_prod;
ARCHITECTURE xilinx OF RAM_ram_bank_prod IS
COMPONENT RAM_ram_bank_exdes IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : RAM_ram_bank_exdes
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
| lgpl-2.1 | 13a038b6c1d5214e5486d207c4e8d9c5 | 0.492767 | 3.812618 | false | false | false | false |
INTI-CMNB/Lattuino_IP_Core | devices/tmcounter.vhdl | 1 | 14,608 | ------------------------------------------------------------------------------
---- ----
---- WISHBONE miscellaneous timer ----
---- ----
---- This file is part FPGA Libre project http://fpgalibre.sf.net/ ----
---- ----
---- Description: ----
---- Implements the micro and milliseconds timers. Also a CPU blocker, ----
---- used for small time delays. ----
---- This module also implements the 6 PWMs. ----
---- Lower 32 bits is a 32 bits microseconds counter ----
---- Upper 32 bits is a milliseconds counter ----
---- ----
---- Port Read Write ----
---- 0 µs B0 PWM0 ----
---- 1 µs B1 PWM1 ----
---- 2 µs B2 PWM2 ----
---- 3 µs B3 PWM3 ----
---- 4 ms B0 PWM4 ----
---- 5 ms B1 PWM5 ----
---- 6 ms B2 PWM Pin Enable ----
---- 7 ms B3 Block CPU µs ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Salvador E. Tropea, salvador en inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2017 Salvador E. Tropea <salvador en inti.gob.ar> ----
---- Copyright (c) 2017 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the GPL v2 or newer license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: TMCounter(RTL) (Entity and architecture) ----
---- File name: tmcounter.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: lattuino ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- Target FPGA: iCE40HX4K-TQ144 ----
---- Language: VHDL ----
---- Wishbone: None ----
---- Synthesis tools: Lattice iCECube2 2016.02.27810 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Wishbone Datasheet ----
---- ----
---- 1 Revision level B.3 ----
---- 2 Type of interface SLAVE ----
---- 3 Defined signal names RST_I => wb_rst_i ----
---- CLK_I => wb_clk_i ----
---- ADR_I => wb_adr_i ----
---- DAT_I => wb_dat_i ----
---- DAT_O => wb_dat_o ----
---- WE_I => wb_we_i ----
---- ACK_O => wb_ack_o ----
---- STB_I => wb_stb_i ----
---- 4 ERR_I Unsupported ----
---- 5 RTY_I Unsupported ----
---- 6 TAGs None ----
---- 7 Port size 8-bit ----
---- 8 Port granularity 8-bit ----
---- 9 Maximum operand size 8-bit ----
---- 10 Data transfer ordering N/A ----
---- 11 Data transfer sequencing Undefined ----
---- 12 Constraints on the CLK_I signal None ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity TMCounter is
generic(
CNT_PRESC : natural:=24;
ENA_TMR : std_logic:='1');
port(
-- WISHBONE signals
wb_clk_i : in std_logic; -- Clock
wb_rst_i : in std_logic; -- Reset input
wb_adr_i : in std_logic_vector(2 downto 0); -- Adress bus
wb_dat_o : out std_logic_vector(7 downto 0); -- DataOut Bus
wb_dat_i : in std_logic_vector(7 downto 0); -- DataIn Bus
wb_we_i : in std_logic; -- Write Enable
wb_stb_i : in std_logic; -- Strobe
wb_ack_o : out std_logic; -- Acknowledge
pwm_o : out std_logic_vector(5 downto 0); -- 6 PWMs
pwm_e_o : out std_logic_vector(5 downto 0)); -- Pin enable for the PWMs
end entity TMCounter;
architecture RTL of TMCounter is
-- Microseconds counter
signal cnt_us_r : unsigned(31 downto 0):=(others => '0');
-- Microseconds counter for the ms counter
signal cnt_us2_r : unsigned(9 downto 0):=(others => '0');
signal tc_cnt_us2: std_logic;
-- Milliseconds counter
signal cnt_ms_r : unsigned(31 downto 0):=(others => '0');
-- Latched value
signal latched_r : unsigned(31 downto 0):=(others => '0');
-- Prescaler for the Microseconds counters
signal ena_cnt : std_logic;
signal pre_cnt_r : integer range 0 to CNT_PRESC-1;
-- Microseconds blocker counter
signal cnt_blk_r : unsigned(7 downto 0):=(others => '0');
-- Prescaler for the Microseconds blocker counter
signal ena_blk_cnt : std_logic;
signal pre_bk_r : integer range 0 to CNT_PRESC-1;
-- Blocker FSM
type state_t is (idle, delay);
signal state : state_t;
-- Blocker WE
signal blk_we : std_logic;
-- PWM values
type pwm_val_t is array (0 to 5) of unsigned(7 downto 0);
signal pwm_val_r : pwm_val_t;
-- PWM counter
signal pwm_count : unsigned(7 downto 0);
-- Auxiliar for config
signal wb_dat : std_logic_vector(7 downto 0); -- DataOut Bus
begin
----------------------------------------------------------------------------
-- 32 bits Microseconds counter
----------------------------------------------------------------------------
-- Microseconds time source for the counters
tmr_prescaler:
process (wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
pre_cnt_r <= 0;
else
pre_cnt_r <= pre_cnt_r+1;
if pre_cnt_r=CNT_PRESC-1 then
pre_cnt_r <= 0;
end if;
end if;
end if;
end process tmr_prescaler;
ena_cnt <= '1' when pre_cnt_r=CNT_PRESC-1 else '0';
-- Microseconds counter, 32 bits
do_cnt_us:
process (wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
cnt_us_r <= (others => '0');
elsif ena_cnt='1' then
cnt_us_r <= cnt_us_r+1;
end if;
end if;
end process do_cnt_us;
----------------------------------------------------------------------------
-- 32 bits Milliseconds counter
----------------------------------------------------------------------------
-- Microseconds counter, 10 bits (0 to 999)
do_cnt_us2:
process (wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' or tc_cnt_us2='1' then
cnt_us2_r <= (others => '0');
elsif ena_cnt='1' then
cnt_us2_r <= cnt_us2_r+1;
end if;
end if;
end process do_cnt_us2;
tc_cnt_us2 <= '1' when ena_cnt='1' and cnt_us2_r=999 else '0';
-- Milliseconds counter, 32 bits
do_cnt_ms:
process (wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
cnt_ms_r <= (others => '0');
elsif tc_cnt_us2='1' then
cnt_ms_r <= cnt_ms_r+1;
end if;
end if;
end process do_cnt_ms;
----------------------------------------------------------------------------
-- WISHBONE read
----------------------------------------------------------------------------
-- Latched value
do_cnt_usr:
process (wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
latched_r <= (others => '0');
elsif wb_stb_i='1' then
if wb_adr_i="000" then
latched_r <= cnt_us_r;
elsif wb_adr_i="100" then
latched_r <= cnt_ms_r;
end if;
end if;
end if;
end process do_cnt_usr;
with wb_adr_i select wb_dat <=
std_logic_vector( cnt_us_r( 7 downto 0)) when "000",
std_logic_vector(latched_r(15 downto 8)) when "001",
std_logic_vector(latched_r(23 downto 16)) when "010",
std_logic_vector(latched_r(31 downto 24)) when "011",
std_logic_vector( cnt_ms_r( 7 downto 0)) when "100",
std_logic_vector(latched_r(15 downto 8)) when "101",
std_logic_vector(latched_r(23 downto 16)) when "110",
std_logic_vector(latched_r(31 downto 24)) when "111",
(others => '0') when others;
wb_dat_o <= wb_dat when ENA_TMR='1' else (others => '0');
blk_we <= '1' when (wb_stb_i and wb_we_i)='1' and wb_adr_i="111" and ENA_TMR='1' else '0';
-- ACK all reads and writes when the counter is 0
wb_ack_o <= '1' when wb_stb_i='1' and (blk_we='0' or (state=delay and cnt_blk_r=0)) else '0';
----------------------------------------------------------------------------
-- Microseconds CPU blocker
----------------------------------------------------------------------------
-- Blocker FSM (idle and delay)
do_fsm:
process (wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
state <= idle;
else
case state is
when idle =>
if blk_we='1' then
state <= delay;
end if;
when others => -- delay
if cnt_blk_r=0 then
state <= idle;
end if;
end case;
end if;
end if;
end process do_fsm;
-- Blocker counter (down counter)
do_bk_cnt:
process (wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
cnt_blk_r <= (others => '0');
elsif state=idle and blk_we='1' then
cnt_blk_r <= unsigned(wb_dat_i);
elsif ena_blk_cnt='1' then
cnt_blk_r <= cnt_blk_r-1;
end if;
end if;
end process do_bk_cnt;
-- Microseconds time source for the Blocker counter
tmr_prescaler_bk:
process (wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' or
(state=idle and blk_we='1') then
pre_bk_r <= CNT_PRESC-1;
else
pre_bk_r <= pre_bk_r-1;
if pre_bk_r=0 then
pre_bk_r <= CNT_PRESC-1;
end if;
end if;
end if;
end process tmr_prescaler_bk;
ena_blk_cnt <= '1' when pre_bk_r=0 else '0';
----------------------------------------------------------------------------
-- 6 PWMs (8 bits, 250 kHz clock, 976.56 Hz carrier)
----------------------------------------------------------------------------
-- PWM value write
do_pwm_val_write:
process (wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='0' then
if (wb_stb_i and wb_we_i)='1' and
wb_adr_i/="111" and
wb_adr_i/="110" then
pwm_val_r(to_integer(unsigned(wb_adr_i))) <= unsigned(wb_dat_i);
end if;
end if;
end if;
end process do_pwm_val_write;
-- 8 bits counter (1 MHz/4)
pwm_count <= cnt_us_r(9 downto 2);
-- PWM outputs (comparators)
do_pwm_outs:
for i in 0 to 5 generate
pwm_o(i) <= '0' when pwm_count>pwm_val_r(i) else '1';
end generate do_pwm_outs;
-- PWM Pin Enable (1 the pin should use the PWM output)
do_pwm_ena_write:
process (wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
pwm_e_o <= (others => '0');
else
if (wb_stb_i and wb_we_i)='1' and wb_adr_i="110" then
pwm_e_o <= wb_dat_i(5 downto 0);
end if;
end if;
end if;
end process do_pwm_ena_write;
end architecture RTL; -- Entity: TMCounter
| gpl-2.0 | 75a318a319ee3ff0e862fab051980806 | 0.362541 | 4.485109 | false | false | false | false |
jobisoft/jTDC | modules/VFB6/I2C/i2c_master_byte_ctrl.vhd | 1 | 12,685 | ---------------------------------------------------------------------
---- ----
---- WISHBONE revB2 compl. I2C Master Core; byte-controller ----
---- ----
---- ----
---- Author: Richard Herveille ----
---- [email protected] ----
---- www.asics.ws ----
---- ----
---- Downloaded from: http://www.opencores.org/projects/i2c/ ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2000 Richard Herveille ----
---- [email protected] ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
-- CVS Log
--
-- $Id: i2c_master_byte_ctrl.vhd,v 1.5 2004-02-18 11:41:48 rherveille Exp $
--
-- $Date: 2004-02-18 11:41:48 $
-- $Revision: 1.5 $
-- $Author: rherveille $
-- $Locker: $
-- $State: Exp $
--
-- Change History:
-- $Log: not supported by cvs2svn $
-- Revision 1.4 2003/08/09 07:01:13 rherveille
-- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
-- Fixed a potential bug in the byte controller's host-acknowledge generation.
--
-- Revision 1.3 2002/12/26 16:05:47 rherveille
-- Core is now a Multimaster I2C controller.
--
-- Revision 1.2 2002/11/30 22:24:37 rherveille
-- Cleaned up code
--
-- Revision 1.1 2001/11/05 12:02:33 rherveille
-- Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
-- Code updated, is now up-to-date to doc. rev.0.4.
-- Added headers.
--
--
------------------------------------------
-- Byte controller section
------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity i2c_master_byte_ctrl is
port (
clk : in std_logic;
rst : in std_logic; -- synchronous active high reset (WISHBONE compatible)
nReset : in std_logic; -- asynchornous active low reset (FPGA compatible)
ena : in std_logic; -- core enable signal
clk_cnt : in std_logic_vector(15 downto 0); -- 4x SCL
-- input signals
start,
stop,
read,
write,
ack_in : std_logic;
din : in std_logic_vector(7 downto 0);
-- output signals
cmd_ack : out std_logic:='0'; -- command done
ack_out : out std_logic:='0';
i2c_busy : out std_logic:='0'; -- arbitration lost
i2c_al : out std_logic:='0'; -- i2c bus busy
dout : out std_logic_vector(7 downto 0);
-- i2c lines
scl_i : in std_logic; -- i2c clock line input
scl_o : out std_logic:='0'; -- i2c clock line output
scl_oen : out std_logic:='0'; -- i2c clock line output enable, active low
sda_i : in std_logic; -- i2c data line input
sda_o : out std_logic:='0'; -- i2c data line output
sda_oen : out std_logic:='0' -- i2c data line output enable, active low
);
end entity i2c_master_byte_ctrl;
architecture structural of i2c_master_byte_ctrl is
component i2c_master_bit_ctrl is
port (
clk : in std_logic;
rst : in std_logic;
nReset : in std_logic;
ena : in std_logic; -- core enable signal
clk_cnt : in std_logic_vector(15 downto 0); -- clock prescale value
cmd : in std_logic_vector(3 downto 0);
cmd_ack : out std_logic; -- command done
busy : out std_logic; -- i2c bus busy
al : out std_logic; -- arbitration lost
din : in std_logic;
dout : out std_logic;
-- i2c lines
scl_i : in std_logic; -- i2c clock line input
scl_o : out std_logic; -- i2c clock line output
scl_oen : out std_logic; -- i2c clock line output enable, active low
sda_i : in std_logic; -- i2c data line input
sda_o : out std_logic; -- i2c data line output
sda_oen : out std_logic -- i2c data line output enable, active low
);
end component i2c_master_bit_ctrl;
-- commands for bit_controller block
constant I2C_CMD_NOP : std_logic_vector(3 downto 0) := "0000";
constant I2C_CMD_START : std_logic_vector(3 downto 0) := "0001";
constant I2C_CMD_STOP : std_logic_vector(3 downto 0) := "0010";
constant I2C_CMD_READ : std_logic_vector(3 downto 0) := "0100";
constant I2C_CMD_WRITE : std_logic_vector(3 downto 0) := "1000";
-- signals for bit_controller
signal core_cmd : std_logic_vector(3 downto 0);
signal core_ack, core_txd, core_rxd : std_logic;
signal al : std_logic;
-- signals for shift register
signal sr : std_logic_vector(7 downto 0); -- 8bit shift register
signal shift, ld : std_logic;
-- signals for state machine
signal go, host_ack : std_logic;
signal dcnt : unsigned(2 downto 0); -- data counter
signal cnt_done : std_logic;
begin
-- hookup bit_controller
bit_ctrl: i2c_master_bit_ctrl port map(
clk => clk,
rst => rst,
nReset => nReset,
ena => ena,
clk_cnt => clk_cnt,
cmd => core_cmd,
cmd_ack => core_ack,
busy => i2c_busy,
al => al,
din => core_txd,
dout => core_rxd,
scl_i => scl_i,
scl_o => scl_o,
scl_oen => scl_oen,
sda_i => sda_i,
sda_o => sda_o,
sda_oen => sda_oen
);
i2c_al <= al;
-- generate host-command-acknowledge
cmd_ack <= host_ack;
-- generate go-signal
go <= (read or write or stop) and not host_ack;
-- assign Dout output to shift-register
dout <= sr;
-- generate shift register
shift_register: process(clk, nReset)
begin
if (nReset = '0') then
sr <= (others => '0');
elsif (clk'event and clk = '1') then
if (rst = '1') then
sr <= (others => '0');
elsif (ld = '1') then
sr <= din;
elsif (shift = '1') then
sr <= (sr(6 downto 0) & core_rxd);
end if;
end if;
end process shift_register;
-- generate data-counter
data_cnt: process(clk, nReset)
begin
if (nReset = '0') then
dcnt <= (others => '0');
elsif (clk'event and clk = '1') then
if (rst = '1') then
dcnt <= (others => '0');
elsif (ld = '1') then
dcnt <= (others => '1'); -- load counter with 7
elsif (shift = '1') then
dcnt <= dcnt -1;
end if;
end if;
end process data_cnt;
cnt_done <= '1' when (dcnt = 0) else '0';
--
-- state machine
--
statemachine : block
type states is (st_idle, st_start, st_read, st_write, st_ack, st_stop);
signal c_state : states;
begin
--
-- command interpreter, translate complex commands into simpler I2C commands
--
nxt_state_decoder: process(clk, nReset)
begin
if (nReset = '0') then
core_cmd <= I2C_CMD_NOP;
core_txd <= '0';
shift <= '0';
ld <= '0';
host_ack <= '0';
c_state <= st_idle;
ack_out <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1' or al = '1') then
core_cmd <= I2C_CMD_NOP;
core_txd <= '0';
shift <= '0';
ld <= '0';
host_ack <= '0';
c_state <= st_idle;
ack_out <= '0';
else
-- initialy reset all signal
core_txd <= sr(7);
shift <= '0';
ld <= '0';
host_ack <= '0';
case c_state is
when st_idle =>
if (go = '1') then
if (start = '1') then
c_state <= st_start;
core_cmd <= I2C_CMD_START;
elsif (read = '1') then
c_state <= st_read;
core_cmd <= I2C_CMD_READ;
elsif (write = '1') then
c_state <= st_write;
core_cmd <= I2C_CMD_WRITE;
else -- stop
c_state <= st_stop;
core_cmd <= I2C_CMD_STOP;
end if;
ld <= '1';
end if;
when st_start =>
if (core_ack = '1') then
if (read = '1') then
c_state <= st_read;
core_cmd <= I2C_CMD_READ;
else
c_state <= st_write;
core_cmd <= I2C_CMD_WRITE;
end if;
ld <= '1';
end if;
when st_write =>
if (core_ack = '1') then
if (cnt_done = '1') then
c_state <= st_ack;
core_cmd <= I2C_CMD_READ;
else
c_state <= st_write; -- stay in same state
core_cmd <= I2C_CMD_WRITE; -- write next bit
shift <= '1';
end if;
end if;
when st_read =>
if (core_ack = '1') then
if (cnt_done = '1') then
c_state <= st_ack;
core_cmd <= I2C_CMD_WRITE;
else
c_state <= st_read; -- stay in same state
core_cmd <= I2C_CMD_READ; -- read next bit
end if;
shift <= '1';
core_txd <= ack_in;
end if;
when st_ack =>
if (core_ack = '1') then
-- check for stop; Should a STOP command be generated ?
if (stop = '1') then
c_state <= st_stop;
core_cmd <= I2C_CMD_STOP;
else
c_state <= st_idle;
core_cmd <= I2C_CMD_NOP;
-- generate command acknowledge signal
host_ack <= '1';
end if;
-- assign ack_out output to core_rxd (contains last received bit)
ack_out <= core_rxd;
core_txd <= '1';
else
core_txd <= ack_in;
end if;
when st_stop =>
if (core_ack = '1') then
c_state <= st_idle;
core_cmd <= I2C_CMD_NOP;
-- generate command acknowledge signal
host_ack <= '1';
end if;
when others => -- illegal states
c_state <= st_idle;
core_cmd <= I2C_CMD_NOP;
report ("Byte controller entered illegal state.");
end case;
end if;
end if;
end process nxt_state_decoder;
end block statemachine;
end architecture structural;
| gpl-3.0 | e3c102892dc878b14587fac7a4e06ba4 | 0.459756 | 3.855623 | false | false | false | false |
dpolad/dlx | DLX_vhd/a.a.a-CW_MEM.vhd | 2 | 7,942 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.myTypes.all;
entity cw_mem is
generic (
MICROCODE_MEM_SIZE : integer := 64; -- Microcode Memory Size
OP_CODE_SIZE : integer := 6; -- Op Code Size
CW_SIZE : integer := 13); -- Control Word Size
port (
OPCODE_IN : in std_logic_vector(5 downto 0); -- Instruction Register
CW_OUT : out std_logic_vector(CW_SIZE - 1 downto 0)
);
end cw_mem;
architecture bhe of cw_mem is
-- signal OPC : std_logic_vector(OP_CODE_SIZE -1 downto 0);
-- this is the microcode memory, it works as a LUT -> to decode an instruction it's opcode indexes this memory
type mem_array is array (integer range 0 to 63) of std_logic_vector(12 downto 0);
signal cw_mem : mem_array := ( "0000000010001", -- (0X00) R type
"0000000010001", -- (0X01) F type
"1011000000000", -- (0X02) J
"1011011110001", -- (0X03) JAL
"1101000000000", -- (0X04) BEQZ
"1101100000000", -- (0X05) BNEZ
"0000000000000", -- (0X06) BFPT
"0000000000000", -- (0X07) BFPT
"0001001100001", -- (0X08) ADDI
"0000001100001", -- (0X09) ADDUI
"0001001100001", -- (0X0A) SUBI
"0000001100001", -- (0X0B) SUBUI
"0000001100001", -- (0X0C) ANDI
"0000001100001", -- (0X0D) ORI
"0000001100001", -- (0X0E) XORI
"0000000000000", -- (0X0F) LHI -- NOT IMPLEMENTED
"0000000000000", -- (0X10) RFE -- NOT IMPLEMENTED
"0000000000000", -- (0X11) TRAP -- NOT IMPLEMENTED
"0100000000000", -- (0X12) JR
"0100011100001", -- (0X13) JALR
"0000001100001", -- (0X14) SLLI
"0000000000000", -- (0X15) NOP
"0000001100001", -- (0X16) SRLI
"0000001100001", -- (0X17) SRAI
"0000001100001", -- (0X18) SEQI
"0000001100001", -- (0X19) SNEI
"0000001100001", -- (0X1A) SLTI
"0000001100001", -- (0X1B) SGTI
"0000001100001", -- (0X1C) SLEI
"0000001100001", -- (0X1D) SGEI
"0000000000000", -- (0X1E)
"0000000000000", -- (0X1F)
"0000000000000", -- (0X20) LB -- NOT IMPLEMENTED
"0000000000000", -- (0X21) LH -- NOT IMPLEMENTED
"0000000000000", -- (0X22)
"0000001101011", -- (0X23) LW
"0000000000000", -- (0X24) LBU -- NOT IMPLEMENTED
"0000000000000", -- (0X25) LHU -- NOT IMPLEMENTED
"0000000000000", -- (0X26) LF -- NOT IMPLEMENTED
"0000000000000", -- (0X27) LD -- NOT IMPLEMENTED
"0000000000000", -- (0X28) SB -- NOT IMPLEMENTED
"0000000000000", -- (0X29) SH -- NOT IMPLEMENTED
"0000000000000", -- (0X2A)
"0000001101100", -- (0X2B) SW
"0000000000000", -- (0X2C)
"0000000000000", -- (0X2D)
"0000000000000", -- (0X2E) SF -- NOT IMPLEMENTED
"0000000000000", -- (0X2F) SD -- NOT IMPLEMENTED
"0000000000000", -- (0X30)
"0000000000000", -- (0X31)
"0000000000000", -- (0X32)
"0000000000000", -- (0X33)
"0000000000000", -- (0X34)
"0000000000000", -- (0X35)
"0000000000000", -- (0X36)
"0000000000000", -- (0X37)
"0000000000000", -- (0X38) ITLB -- NOT IMPLEMENTED
"0000000000000", -- (0X39)
"0000001100001", -- (0X3A) SLTUI
"0000001100001", -- (0X3B) SGTUI
"0000001100001", -- (0X3C) SLEUI
"0000001100001", -- (0X3D) SGEUI
"0000000000000", -- (0X3E)
"0000000000000" -- (0X3F)
);
begin
-- CW_OUT <= cw_mem(to_integer(unsigned(OPCODE_IN)));
-- CW_OUT <= cw_mem(0) when OPCODE_IN = "0X00" else
-- cw_mem(1) when OPCODE_IN = "0X01" else
-- NULL;
process (OPCODE_IN)
begin
case to_integer(unsigned(OPCODE_IN)) is
when 0 => CW_OUT <= "0000000010001";
when 1 => CW_OUT <= "0000000010001";
when 2 => CW_OUT <= "1011000000000";
when 3 => CW_OUT <= "1011011110001";
when 4 => CW_OUT <= "1101000000000";
when 5 => CW_OUT <= "1101100000000";
when 6 => CW_OUT <= "0000000000000";
when 7 => CW_OUT <= "0000000000000";
when 8 => CW_OUT <= "0001001100001";
when 9 => CW_OUT <= "0000001100001";
when 10 => CW_OUT <="0001001100001";
when 11 => CW_OUT <="0000001100001";
when 12 => CW_OUT <="0000001100001";
when 13 => CW_OUT <="0000001100001";
when 14 => CW_OUT <="0000001100001";
when 15 => CW_OUT <="0000000000000";
when 16 => CW_OUT <="0000000000000";
when 17 => CW_OUT <="0000000000000";
when 18 => CW_OUT <="0100000000000";
when 19 => CW_OUT <="0100011100001";
when 20 => CW_OUT <="0000001100001";
when 21 => CW_OUT <="0000000000000";
when 22 => CW_OUT <="0000001100001";
when 23 => CW_OUT <="0000001100001";
when 24 => CW_OUT <="0000001100001";
when 25 => CW_OUT <="0000001100001";
when 26 => CW_OUT <="0000001100001";
when 27 => CW_OUT <="0000001100001";
when 28 => CW_OUT <="0000001100001";
when 29 => CW_OUT <="0000001100001";
when 30 => CW_OUT <="0000000000000";
when 31 => CW_OUT <="0000000000000";
when 32 => CW_OUT <="0000000000000";
when 33 => CW_OUT <="0000000000000";
when 34 => CW_OUT <="0000000000000";
when 35 => CW_OUT <="0000001101011";
when 36 => CW_OUT <="0000000000000";
when 37 => CW_OUT <="0000000000000";
when 38 => CW_OUT <="0000000000000";
when 39 => CW_OUT <="0000000000000";
when 40 => CW_OUT <="0000000000000";
when 41 => CW_OUT <="0000000000000";
when 42 => CW_OUT <="0000000000000";
when 43 => CW_OUT <="0000001101100";
when 44 => CW_OUT <="0000000000000";
when 45 => CW_OUT <="0000000000000";
when 46 => CW_OUT <="0000000000000";
when 47 => CW_OUT <="0000000000000";
when 48 => CW_OUT <="0000000000000";
when 49 => CW_OUT <="0000000000000";
when 50 => CW_OUT <="0000000000000";
when 51 => CW_OUT <="0000000000000";
when 52 => CW_OUT <="0000000000000";
when 53 => CW_OUT <="0000000000000";
when 54 => CW_OUT <="0000000000000";
when 55 => CW_OUT <="0000000000000";
when 56 => CW_OUT <="0000000000000";
when 57 => CW_OUT <="0000000000000";
when 58 => CW_OUT <="0000001100001";
when 59 => CW_OUT <="0000001100001";
when 60 => CW_OUT <="0000001100001";
when 61 => CW_OUT <="0000001100001";
when 62 => CW_OUT <="0000000000000";
when 63 => CW_OUT <="0000000000000";
when others => NULL;
end case;
end process;
end bhe;
| bsd-2-clause | f303474a55be014ffd083f13365cc80a | 0.463737 | 4.098039 | false | false | false | false |
MAV-RT-testbed/MAV-testbed | Syma_Flight_Final/Syma_Flight_Final.srcs/sources_1/ipshared/xilinx.com/axi_quad_spi_v3_2/c64e9f22/hdl/src/vhdl/qspi_core_interface.vhd | 1 | 153,120 | -------------------------------------------------------------------------------
-- qspi_core_interface Module - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: qspi_core_interface.vhd
-- Version: v3.0
-- Description: Serial Peripheral Interface (SPI) Module for interfacing
-- with a 32-bit AXI bus.
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
Library UNISIM;
use UNISIM.vcomponents.all;
library axi_lite_ipif_v3_0;
use axi_lite_ipif_v3_0.axi_lite_ipif;
use axi_lite_ipif_v3_0.ipif_pkg.all;
library lib_fifo_v1_0;
use lib_fifo_v1_0.async_fifo_fg;
library lib_srl_fifo_v1_0;
use lib_srl_fifo_v1_0.srl_fifo_f;
library lib_cdc_v1_0;
use lib_cdc_v1_0.cdc_sync;
library lib_pkg_v1_0;
use lib_pkg_v1_0.all;
use lib_pkg_v1_0.lib_pkg.log2;
-- use lib_pkg_v1_0.lib_pkg.clog2;
use lib_pkg_v1_0.lib_pkg.max2;
use lib_pkg_v1_0.lib_pkg.RESET_ACTIVE;
library interrupt_control_v3_1;
library axi_quad_spi_v3_2;
use axi_quad_spi_v3_2.all;
-------------------------------------------------------------------------------
entity qspi_core_interface is
generic(
C_FAMILY : string;
C_SUB_FAMILY : string;
C_S_AXI_DATA_WIDTH : integer;
Async_Clk : integer;
----------------------
-- local parameters
C_NUM_CE_SIGNALS : integer;
----------------------
-- SPI parameters
--C_AXI4_CLK_PS : integer;
--C_EXT_SPI_CLK_PS : integer;
C_FIFO_DEPTH : integer;
C_SCK_RATIO : integer;
C_NUM_SS_BITS : integer;
C_NUM_TRANSFER_BITS : integer;
C_SPI_MODE : integer;
C_USE_STARTUP : integer;
C_SPI_MEMORY : integer;
C_TYPE_OF_AXI4_INTERFACE : integer;
----------------------
-- local constants
C_FIFO_EXIST : integer;
C_SPI_NUM_BITS_REG : integer;
C_OCCUPANCY_NUM_BITS : integer;
----------------------
-- local constants
C_IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE;
----------------------
-- local constants
C_SPICR_REG_WIDTH : integer;
C_SPISR_REG_WIDTH : integer
);
port(
EXT_SPI_CLK : in std_logic;
------------------------------------------------
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
------------------------------------------------
Bus2IP_BE : in std_logic_vector(0 to ((C_S_AXI_DATA_WIDTH/8)-1));
Bus2IP_RdCE : in std_logic_vector(0 to (C_NUM_CE_SIGNALS-1));
Bus2IP_WrCE : in std_logic_vector(0 to (C_NUM_CE_SIGNALS-1));
Bus2IP_Data : in std_logic_vector(0 to (C_S_AXI_DATA_WIDTH-1));
------------------------------------------------
IP2Bus_Data : out std_logic_vector(0 to (C_S_AXI_DATA_WIDTH-1));
IP2Bus_WrAck : out std_logic;
IP2Bus_RdAck : out std_logic;
IP2Bus_Error : out std_logic;
------------------------------------------------
burst_tr : in std_logic;
rready : in std_logic;
WVALID : in std_logic;
--SPI Ports
SCK_I : in std_logic;
SCK_O : out std_logic;
SCK_T : out std_logic;
------------------------------------------------
IO0_I : in std_logic;
IO0_O : out std_logic;
IO0_T : out std_logic;
------------------------------------------------
IO1_I : in std_logic;
IO1_O : out std_logic;
IO1_T : out std_logic;
------------------------------------------------
IO2_I : in std_logic;
IO2_O : out std_logic;
IO2_T : out std_logic;
------------------------------------------------
IO3_I : in std_logic;
IO3_O : out std_logic;
IO3_T : out std_logic;
------------------------------------------------
SPISEL : in std_logic;
------------------------------------------------
SS_I : in std_logic_vector((C_NUM_SS_BITS-1) downto 0);
SS_O : out std_logic_vector((C_NUM_SS_BITS-1) downto 0);
SS_T : out std_logic;
------------------------------------------------
IP2INTC_Irpt : out std_logic;
------------------------------------------------
------------------------
-- STARTUP INTERFACE
------------------------
cfgclk : out std_logic; -- FGCLK , -- 1-bit output: Configuration main clock output
cfgmclk : out std_logic; -- FGMCLK , -- 1-bit output: Configuration internal oscillator clock output
eos : out std_logic; -- OS , -- 1-bit output: Active high output signal indicating the End Of Startup.
preq : out std_logic; -- REQ , -- 1-bit output: PROGRAM request to fabric output
di : out std_logic_vector(3 downto 0) -- output
);
end entity qspi_core_interface;
-------------------------------------------------------------------------------
------------
architecture imp of qspi_core_interface is
------------
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-- function definition
----------------------
function clog2(x : positive) return natural is
variable r : natural := 0;
variable rp : natural := 1; -- rp tracks the value 2**r
begin
while rp < x loop -- Termination condition T: x <= 2**r
-- Loop invariant L: 2**(r-1) < x
r := r + 1;
if rp > integer'high - rp then exit; end if; -- If doubling rp overflows
-- the integer range, the doubled value would exceed x, so safe to exit.
rp := rp + rp;
end loop;
-- L and T <-> 2**(r-1) < x <= 2**r <-> (r-1) < log2(x) <= r
return r; --
end clog2;
-------------------------------------------------------------------------------
-- constant definition
constant NEW_LOGIC : integer := 0;
-- These constants are indices into the "CE" arrays for the various registers.
constant INTR_LO : natural := 0;
constant INTR_HI : natural := 15;
constant SWRESET : natural := 16; -- at address C_BASEADDR + 40 h
constant SPICR : natural := 24; -- 17; -- at address C_BASEADDR + 60 h
constant SPISR : natural := 25; -- 18;
constant SPIDTR : natural := 26; -- 19;
constant SPIDRR : natural := 27; -- 20;
constant SPISSR : natural := 28; -- 21;
constant SPITFOR : natural := 29; -- 22;
constant SPIRFOR : natural := 30; -- 23; -- at address C_BASEADDR + 78 h
constant REG_HOLE : natural := 31; -- 24; -- at address C_BASEADDR + 7C h
--SPI MODULE SIGNALS
signal spiXfer_done_int : std_logic;
signal dtr_underrun_int : std_logic;
signal modf_strobe_int : std_logic;
signal slave_MODF_strobe_int : std_logic;
--OR REGISTER/FIFO SIGNALS
--TO/FROM REG/FIFO DATA
signal receive_Data_int : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal transmit_Data_int : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
--Extra bit required for signal Register_Data_ctrl
signal register_Data_cntrl_int :std_logic_vector(0 to (C_SPI_NUM_BITS_REG+1));
signal register_Data_slvsel_int:std_logic_vector(0 to (C_NUM_SS_BITS-1));
signal IP2Bus_SPICR_Data_int :std_logic_vector(0 to (C_SPICR_REG_WIDTH-1));
signal IP2Bus_SPISR_Data_int :std_logic_vector(0 to (C_SPISR_REG_WIDTH-1));
signal IP2Bus_Receive_Reg_Data_int :std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal IP2Bus_Data_received_int:
std_logic_vector(0 to (C_S_AXI_DATA_WIDTH-1));
signal IP2Bus_SPISSR_Data_int : std_logic_vector(0 to (C_NUM_SS_BITS-1));
signal IP2Bus_Tx_FIFO_OCC_Reg_Data_int:
std_logic_vector(0 to (C_OCCUPANCY_NUM_BITS-1));
signal IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1:
std_logic_vector((C_OCCUPANCY_NUM_BITS-1) downto 0);
signal IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1:
std_logic_vector((C_OCCUPANCY_NUM_BITS-1) downto 0);
signal IP2Bus_Rx_FIFO_OCC_Reg_Data_int:
std_logic_vector(0 to (C_OCCUPANCY_NUM_BITS-1));
--STATUS REGISTER SIGNALS
signal sr_3_MODF_int : std_logic;
signal Tx_FIFO_Full_int : std_logic;
signal sr_5_Tx_Empty_int : std_logic;
signal sr_6_Rx_Full_int : std_logic;
signal Rc_FIFO_Empty_int : std_logic;
--RECEIVE AND TRANSMIT REGISTER SIGNALS
signal drr_Overrun_int : std_logic;
signal dtr_Underrun_strobe_int : std_logic;
--FIFO SIGNALS
signal rc_FIFO_Full_strobe_int : std_logic;
signal rc_FIFO_occ_Reversed_int :std_logic_vector
((C_OCCUPANCY_NUM_BITS-1) downto 0);
signal rc_FIFO_occ_Reversed_int_2 :std_logic_vector
((C_OCCUPANCY_NUM_BITS-1) downto 0);
signal rc_FIFO_Data_Out_int : std_logic_vector
(0 to (C_NUM_TRANSFER_BITS-1));
signal sr_6_Rx_Full_int_1 : std_logic;
signal FIFO_Empty_rx_1 : std_logic;
signal FIFO_Empty_rx : std_logic;
signal data_Exists_RcFIFO_int : std_logic;
signal tx_FIFO_Empty_strobe_int : std_logic;
signal tx_FIFO_occ_Reversed_int : std_logic_vector
((C_OCCUPANCY_NUM_BITS-1) downto 0);
signal tx_FIFO_occ_Reversed_int_2 : std_logic_vector
((C_OCCUPANCY_NUM_BITS-1) downto 0);
signal data_Exists_TxFIFO_int : std_logic;
signal data_Exists_TxFIFO_int_1 : std_logic;
signal data_From_TxFIFO_int : std_logic_vector
(0 to (C_NUM_TRANSFER_BITS-1));
signal tx_FIFO_less_half_int : std_logic;
signal Tx_FIFO_Full_int_1 : std_logic;
signal FIFO_Empty_tx : std_logic;
signal data_From_TxFIFO_int_1 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal tx_occ_msb : std_logic;
signal tx_occ_msb_1 : std_logic:= '0';
signal tx_occ_msb_2 : std_logic;
signal tx_occ_msb_3 : std_logic;
signal tx_occ_msb_4 : std_logic;
signal reset_TxFIFO_ptr_int : std_logic;
signal reset_TxFIFO_ptr_int_to_spi : std_logic;
signal reset_RcFIFO_ptr_int : std_logic;
signal reset_RcFIFO_ptr_to_spi_clk : std_logic;
signal ip2Bus_Data_Reg_int : std_logic_vector
(0 to (C_S_AXI_DATA_WIDTH-1));
signal ip2Bus_Data_occupancy_int: std_logic_vector
(0 to (C_S_AXI_DATA_WIDTH-1));
signal ip2Bus_Data_SS_int : std_logic_vector
(0 to (C_S_AXI_DATA_WIDTH-1));
-- interface between signals on instance basis
signal bus2IP_Reset_int : std_logic;
signal bus2IP_Data_for_interrupt_core : std_logic_vector
(0 to C_S_AXI_DATA_WIDTH-1);
signal ip2Bus_Error_int : std_logic;
signal ip2Bus_WrAck_int : std_logic;-- := '0';
signal ip2Bus_RdAck_int : std_logic;-- := '0';
signal ip2Bus_IntrEvent_int : std_logic_vector
(0 to (C_IP_INTR_MODE_ARRAY'length-1));
signal transmit_ip2bus_error : std_logic;
signal receive_ip2bus_error : std_logic;
-- SOFT RESET SIGNALS
signal reset2ip_reset_int : std_logic;
signal rst_ip2bus_wrack : std_logic;
signal rst_ip2bus_error : std_logic;
signal rst_ip2bus_rdack : std_logic;
-- INTERRUPT SIGNALS
signal intr_ip2bus_data : std_logic_vector
(0 to (C_S_AXI_DATA_WIDTH-1));
signal intr_ip2bus_rdack : std_logic;
signal intr_ip2bus_wrack : std_logic;
signal intr_ip2bus_error : std_logic;
signal ip2bus_error_RdWr : std_logic;
--
signal wr_ce_reduce_ack_gen: std_logic;
--
signal rd_ce_reduce_ack_gen : std_logic;
--
signal control_bit_7_8_int : std_logic_vector(0 to 1);
signal spisel_pulse_o_int : std_logic;
signal Interrupt_WrCE_sig : std_logic_vector(0 to 1);
signal IPIF_Lvl_Interrupts_sig : std_logic;
signal spisel_d1_reg : std_logic;
signal Mst_N_Slv_mode : std_logic;
-----
signal bus2ip_intr_rdce : std_logic_vector(INTR_LO to INTR_HI);
signal bus2ip_intr_wrce : std_logic_vector(INTR_LO to INTR_HI);
signal ip2Bus_RdAck_intr_reg_hole : std_logic;
signal ip2Bus_RdAck_intr_reg_hole_d1 : std_logic;
signal ip2Bus_WrAck_intr_reg_hole : std_logic;
signal ip2Bus_WrAck_intr_reg_hole_d1 : std_logic;
signal intr_controller_rd_ce_or_reduce : std_logic;
signal intr_controller_wr_ce_or_reduce : std_logic;
signal wr_ce_or_reduce_core_cmb : std_logic;
signal ip2Bus_WrAck_core_reg_d1 : std_logic;
signal ip2Bus_WrAck_core_reg : std_logic;
signal rd_ce_or_reduce_core_cmb : std_logic;
signal ip2Bus_RdAck_core_reg_d1 : std_logic;
signal ip2Bus_RdAck_core_reg : std_logic;
signal SPISR_0_CMD_Error_int : std_logic;
signal SPISR_1_LOOP_Back_Error_int : std_logic;
signal SPISR_2_MSB_Error_int : std_logic;
signal SPISR_3_Slave_Mode_Error_int : std_logic;
signal SPISR_4_CPOL_CPHA_Error_int : std_logic;
signal SPISR_Ext_SPISEL_slave_int : std_logic;
signal SPICR_5_TXFIFO_RST_int : std_logic;
-- signal SPICR_6_RXFIFO_RST_int : std_logic;
signal pr_state_idle_int : std_logic;
signal Quad_Phase_int : std_logic;
signal SPICR_0_LOOP_frm_axi :std_logic;
signal SPICR_0_LOOP_to_spi :std_logic;
signal SPICR_1_SPE_frm_axi :std_logic;
signal SPICR_1_SPE_to_spi :std_logic;
signal SPICR_2_MST_N_SLV_frm_axi :std_logic;
signal SPICR_2_MST_N_SLV_to_spi :std_logic;
signal SPICR_3_CPOL_frm_axi :std_logic;
signal SPICR_3_CPOL_to_spi :std_logic;
signal SPICR_4_CPHA_frm_axi :std_logic;
signal SPICR_4_CPHA_to_spi :std_logic;
signal SPICR_5_TXFIFO_frm_axi :std_logic;
signal SPICR_5_TXFIFO_to_spi :std_logic;
--signal SPICR_6_RXFIFO_RST_frm_axi:std_logic;
--signal SPICR_6_RXFIFO_RST_to_spi :std_logic;
signal SPICR_7_SS_frm_axi :std_logic;
signal SPICR_7_SS_to_spi :std_logic;
signal SPICR_8_TR_INHIBIT_frm_axi:std_logic;
signal SPICR_8_TR_INHIBIT_to_spi :std_logic;
signal SPICR_9_LSB_frm_axi :std_logic;
signal SPICR_9_LSB_to_spi :std_logic;
signal SPICR_bits_7_8_frm_spi :std_logic;
signal SPICR_bits_7_8_to_axi :std_logic;
signal Rx_FIFO_Empty : std_logic;
signal rx_fifo_full_to_spi_clk : std_logic;
signal tx_fifo_empty_to_axi_clk : std_logic;
signal tx_fifo_full : std_logic;
signal spisel_d1_reg_to_axi_clk : std_logic;
signal spicr_bits_7_8_frm_axi_clk : std_logic_vector(1 downto 0);
signal spicr_8_tr_inhibit_to_spi_clk : std_logic;
signal spicr_9_lsb_to_spi_clk : std_logic;
signal spicr_bits_7_8_to_spi_clk : std_logic_vector(0 to 1);
signal spicr_0_loop_frm_axi_clk : std_logic;
signal spicr_1_spe_frm_axi_clk : std_logic;
signal spicr_2_mst_n_slv_frm_axi_clk : std_logic;
signal spicr_3_cpol_frm_axi_clk : std_logic;
signal spicr_4_cpha_frm_axi_clk : std_logic;
signal spicr_5_txfifo_rst_frm_axi_clk : std_logic;
signal spicr_6_rxfifo_rst_frm_axi_clk : std_logic;
signal spicr_7_ss_frm_axi_clk : std_logic;
signal spicr_8_tr_inhibit_frm_axi_clk : std_logic;
signal spicr_9_lsb_frm_axi_clk : std_logic;
signal Tx_FIFO_wr_ack_1 : std_logic;
signal rst_to_spi_int : std_logic;
signal spicr_0_loop_to_spi_clk : std_logic;
signal spicr_1_spe_to_spi_clk : std_logic;
signal spicr_2_mas_n_slv_to_spi_clk : std_logic;
signal spicr_3_cpol_to_spi_clk : std_logic;
signal spicr_4_cpha_to_spi_clk : std_logic;
signal spicr_5_txfifo_rst_to_spi_clk : std_logic;
signal spicr_6_rxfifo_rst_to_spi_clk : std_logic;
signal spicr_7_ss_to_spi_clk : std_logic;
signal sr_3_modf_to_spi_clk : std_logic;
signal sr_3_modf_frm_axi_clk : std_logic;
signal data_from_txfifo : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal Bus2IP_WrCE_d1 : std_logic;
signal Bus2IP_WrCE_d2 : std_logic;
signal Bus2IP_WrCE_d3 : std_logic;
signal Bus2IP_WrCE_pulse_1 : std_logic;
signal Bus2IP_WrCE_pulse_2 : std_logic;
signal Bus2IP_WrCE_pulse_3 : std_logic;
signal data_to_txfifo : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal tx_fifo_wr_ack : std_logic;
-- signal ext_spi_clk : std_logic;
signal tx_fifo_rd_ack_open : std_logic;
signal tx_fifo_empty : std_logic;
signal tx_fifo_almost_full : std_logic;
signal tx_fifo_almost_empty : std_logic;
signal tx_fifo_occ_reversed : std_logic_vector((C_OCCUPANCY_NUM_BITS-1) downto 0);
signal c_wr_count_width : std_logic;
signal rx_fifo_wr_ack_open : std_logic;
signal data_from_rx_fifo : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal rx_fifo_rd_ack : std_logic;
signal rx_fifo_full : std_logic;
signal rx_fifo_almost_full : std_logic;
signal rx_fifo_almost_empty : std_logic;
signal rx_fifo_occ_reversed : std_logic_vector((C_OCCUPANCY_NUM_BITS-1) downto 0);
signal SPISSR_frm_axi_clk : std_logic_vector(0 to (C_NUM_SS_BITS-1));
signal modf_strobe_frm_spi_clk : std_logic;
signal modf_strobe_to_axi_clk : std_logic;
signal dtr_underrun_frm_spi_clk : std_logic;
signal dtr_underrun_to_axi_clk : std_logic;
signal data_to_rx_fifo : std_logic_vector
(0 to (C_NUM_TRANSFER_BITS-1));
signal spisel_d1_reg_frm_spi_clk : std_logic;
signal Mst_N_Slv_mode_frm_spi_clk: std_logic;
signal Mst_N_Slv_mode_to_axi_clk : std_logic;
signal SPICR_2_MST_N_SLV_to_spi_clk : std_logic;
signal spicr_5_txfifo_frm_axi_clk : std_logic;
signal spicr_5_txfifo_to_spi_clk: std_logic;
signal reset_RcFIFO_ptr_frm_axi_clk : std_logic;
-- signal reset_RcFIFO_ptr_to_spi_clk : std_logic;
signal Data_To_Rx_FIFO_1 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal SPIXfer_done_Rx_Wr_en, SPIXfer_done_rd_tx_en: std_logic;
signal Tx_FIFO_Empty_SPISR_frm_spi_clk : std_logic;
signal Tx_FIFO_Empty_SPISR_to_axi_clk : std_logic;
signal Tx_FIFO_Empty_frm_spi_clk : std_logic;
signal Rx_FIFO_Full_frm_axi_clk : std_logic;
signal Rx_FIFO_Full_int,Rx_FIFO_Full_i,RX_one_less_than_full, not_Tx_FIFO_FULL : std_logic;
signal updown_cnt_en_tx, updown_cnt_en_rx : std_logic;
signal TX_one_less_than_full : std_logic;
signal tx_cntr_xfer_done : std_logic;
signal Tx_FIFO_one_less_to_Empty, Tx_FIFO_Full_i: std_logic;
signal Tx_FIFO_Empty_i, Tx_FIFO_Empty_int : std_logic;
signal Tx_FIFO_Empty_frm_axi_clk : std_logic;
signal rx_fifo_empty_i : std_logic;
signal Rx_FIFO_Empty_int : std_logic;
signal IP2Bus_WrAck_1 : std_logic;
signal ip2Bus_WrAck_core_reg_1 : std_logic;
signal IP2Bus_RdAck_1 : std_logic;
signal ip2Bus_RdAck_core_reg_1 : std_logic;
signal IP2Bus_Error_1 : std_logic;
signal ip2Bus_Data_1 : std_logic_vector(0 to (C_S_AXI_DATA_WIDTH-1)) ;
signal SPISR_0_CMD_Error_frm_spi_clk : std_logic;
signal SPISR_0_CMD_Error_to_axi_clk : std_logic;
signal rx_fifo_reset, tx_fifo_reset : std_logic;
signal reg_hole_wr_ack: std_logic;
signal reg_hole_rd_ack: std_logic;
signal read_ack_delay_1: std_logic;
signal read_ack_delay_2: std_logic;
signal read_ack_delay_3: std_logic;
signal read_ack_delay_4: std_logic;
signal read_ack_delay_5: std_logic;
signal read_ack_delay_6: std_logic;
signal read_ack_delay_7: std_logic;
signal read_ack_delay_8: std_logic;
signal write_ack_delay_1: std_logic;
signal write_ack_delay_2: std_logic;
signal write_ack_delay_3: std_logic;
signal write_ack_delay_4: std_logic;
signal write_ack_delay_5: std_logic;
signal write_ack_delay_6: std_logic;
signal write_ack_delay_7: std_logic;
signal write_ack_delay_8: std_logic;
signal error_ack_delay_1: std_logic;
signal error_ack_delay_2: std_logic;
signal error_ack_delay_3: std_logic;
signal error_ack_delay_4: std_logic;
signal error_ack_delay_5: std_logic;
signal error_ack_delay_6: std_logic;
signal error_ack_delay_7: std_logic;
signal error_ack_delay_8: std_logic;
--------------------------------------------------------------------------------
begin
-----
-----------------------------------
-- Combinatorial operations for SPI
-----------------------------------
---- A write to read only register wont have any effect on register.
---- The transaction is completed by generating WrAck only.
not_Tx_FIFO_FULL <= not Tx_FIFO_Full;
Interrupt_WrCE_sig <= "00";
IPIF_Lvl_Interrupts_sig <= '0';
LEGACY_MD_WR_RD_ACK_GEN: if C_TYPE_OF_AXI4_INTERFACE = 0 generate
-----
begin
-----
-- A write to read only register wont have any effect on register.
-- The transaction is completed by generating WrAck only.
--------------------------------------------------------
-- IP2Bus_Error is generated under following conditions:
-- 1. If an full transmit register/FIFO is written into.
-- 2. If an empty receive register/FIFO is read from.
-- Due to software driver legacy, the register rule test is not applied to SPI.
--------------------------------------------------------
IP2Bus_Error_1 <= intr_ip2bus_error or
rst_ip2bus_error or
transmit_ip2bus_error or
receive_ip2bus_error;
REG_ERR_ACK_P:process(Bus2IP_Clk)is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
IP2Bus_Error <= '0';
else
IP2Bus_Error <= IP2Bus_Error_1;
end if;
end if;
end process REG_ERR_ACK_P;
wr_ce_or_reduce_core_cmb <= Bus2IP_WrCE(SPISR) or -- read only register
Bus2IP_WrCE(SPIDRR) or -- read only register
(Bus2IP_WrCE(SPIDTR) and not_Tx_FIFO_FULL) or -- common to
-- spi_fifo_ifmodule_1 and
-- spi_receive_reg_1
-- (FROM TRANSMITTER) module
Bus2IP_WrCE(SPICR) or
Bus2IP_WrCE(SPISSR) or
Bus2IP_WrCE(SPITFOR)or -- locally generated
Bus2IP_WrCE(SPIRFOR)or -- locally generated
Bus2IP_WrCE(REG_HOLE) or -- register hole
or_reduce(Bus2IP_WrCE(17 to 23)); -- holes between reset end and start of SPICR register
--------------------------------------------------
WRITE_ACK_SPIDTR_REG_PROCESS: process(Bus2IP_Clk) is
---------------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
Bus2IP_WrCE_d1 <= '0';
Bus2IP_WrCE_d2 <= '0';
Bus2IP_WrCE_d3 <= '0';
else
Bus2IP_WrCE_d1 <= Bus2IP_WrCE(SPIDTR);
Bus2IP_WrCE_d2 <= Bus2IP_WrCE_d1;
Bus2IP_WrCE_d3 <= Bus2IP_WrCE_d2;
end if; end if;
end process WRITE_ACK_SPIDTR_REG_PROCESS;
Bus2IP_WrCE_pulse_1 <= Bus2IP_WrCE(SPIDTR) and not Bus2IP_WrCE_d1;
Bus2IP_WrCE_pulse_2 <= Bus2IP_WrCE_d1 and not Bus2IP_WrCE_d2;
Bus2IP_WrCE_pulse_3 <= Bus2IP_WrCE_d2 and not Bus2IP_WrCE_d3;
--end generate WR_ACK_OR_REDUCE_FIFO_1_GEN;
-----------------------------------------
-- WRITE_ACK_CORE_REG_PROCESS : The commong write ACK generation logic when FIFO is
-- ------------------------ not included in the design.
--------------------------------------------------
-- _____|-----|__________ wr_ce_or_reduce_fifo_no
-- ________|-----|_______ ip2Bus_WrAck_fifo_no_d1
-- ________|--|__________ ip2Bus_WrAck_fifo_no from common write ack register
-- this ack will be used in register files for
-- reference.
--------------------------------------------------
WRITE_ACK_CORE_REG_PROCESS: process(Bus2IP_Clk) is
---------------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
ip2Bus_WrAck_core_reg_d1 <= '0';
ip2Bus_WrAck_core_reg <= '0';
ip2Bus_WrAck_core_reg_1 <= '0';
else
ip2Bus_WrAck_core_reg_d1 <= wr_ce_or_reduce_core_cmb;
ip2Bus_WrAck_core_reg <= wr_ce_or_reduce_core_cmb and
(not ip2Bus_WrAck_core_reg_d1);
ip2Bus_WrAck_core_reg_1 <= ip2Bus_WrAck_core_reg;
end if;
end if;
end process WRITE_ACK_CORE_REG_PROCESS;
-------------------------------------------------
-- internal logic uses this signal
wr_ce_reduce_ack_gen <= ip2Bus_WrAck_core_reg_1;
-------------------------------------------------
-- common WrAck to IPIF
IP2Bus_WrAck_1 <= intr_ip2bus_wrack or -- common
rst_ip2bus_wrack or -- common
ip2Bus_WrAck_intr_reg_hole or -- newly added to target the holes in register space
ip2Bus_WrAck_core_reg;-- or
--Tx_FIFO_wr_ack; -- newly added
REG_WR_ACK_P:process(Bus2IP_Clk)is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
IP2Bus_WrAck <= '0';
else
IP2Bus_WrAck <= IP2Bus_WrAck_1;
end if;
end if;
end process REG_WR_ACK_P;
-------------------------------------------------
--end generate LEGACY_MD_WR_ACK_GEN;
-------------------------------------------------
--LEGACY_MD_RD_ACK_GEN: if C_TYPE_OF_AXI4_INTERFACE = 0 generate
-----
--begin
-----
rd_ce_or_reduce_core_cmb <= Bus2IP_RdCE(SWRESET) or --common locally generated
Bus2IP_RdCE(SPIDTR) or --common locally generated
Bus2IP_RdCE(SPISR) or --common from status register
Bus2IP_RdCE(SPIDRR) or --common to
--spi_fifo_ifmodule_1
--and spi_receive_reg_1
--(FROM RECEIVER) module
Bus2IP_RdCE(SPICR) or --common spi_cntrl_reg_1
Bus2IP_RdCE(SPISSR) or --common spi_status_reg_1
Bus2IP_RdCE(SPITFOR) or --only for fifo_occu TX reg
Bus2IP_RdCE(SPIRFOR) or --only for fifo_occu RX reg
Bus2IP_RdCE(REG_HOLE) or -- register hole
or_reduce(Bus2IP_RdCE(17 to 23)); -- holes between reset end and start of SPICR register; --reg hole
-- READ_ACK_CORE_REG_PROCESS : The commong write ACK generation logic
--------------------------------------------------
-- _____|-----|__________ wr_ce_or_reduce_fifo_no
-- ________|-----|_______ ip2Bus_WrAck_fifo_no_d1
-- ________|--|__________ ip2Bus_WrAck_fifo_no from common write ack register
-- this ack will be used in register files for
-- reference.
--------------------------------------------------
READ_ACK_CORE_REG_PROCESS: process(Bus2IP_Clk) is
-------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
ip2Bus_RdAck_core_reg_d1 <= '0';
ip2Bus_RdAck_core_reg <= '0';
ip2Bus_RdAck_core_reg_1 <= '0';
read_ack_delay_1 <= '0';
read_ack_delay_2 <= '0';
read_ack_delay_3 <= '0';
read_ack_delay_4 <= '0';
read_ack_delay_5 <= '0';
read_ack_delay_6 <= '0';
read_ack_delay_7 <= '0';
else
--ip2Bus_RdAck_core_reg_d1 <= rd_ce_or_reduce_core_cmb;
--ip2Bus_RdAck_core_reg <= rd_ce_or_reduce_core_cmb and
-- (not ip2Bus_RdAck_core_reg_d1);
read_ack_delay_1 <= rd_ce_or_reduce_core_cmb;
read_ack_delay_2 <= read_ack_delay_1;
read_ack_delay_3 <= read_ack_delay_2;
read_ack_delay_4 <= read_ack_delay_3;
read_ack_delay_5 <= read_ack_delay_4;
read_ack_delay_6 <= read_ack_delay_5;
read_ack_delay_7 <= read_ack_delay_6;
ip2Bus_RdAck_core_reg <= read_ack_delay_6 and (not read_ack_delay_7);
ip2Bus_RdAck_core_reg_1 <= ip2Bus_RdAck_core_reg;
end if;
end if;
end process READ_ACK_CORE_REG_PROCESS;
-------------------------------------------------
-- internal logic uses this signal
rd_ce_reduce_ack_gen <= ip2Bus_RdAck_core_reg;
-------------------------------------------------
-- common RdAck to IPIF
IP2Bus_RdAck_1 <= intr_ip2bus_rdack or -- common
ip2Bus_RdAck_intr_reg_hole or
ip2Bus_RdAck_core_reg;
REG_RD_ACK_P:process(Bus2IP_Clk)is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
IP2Bus_RdAck <= '0';
else
IP2Bus_RdAck <= IP2Bus_RdAck_1;
end if;
end if;
end process REG_RD_ACK_P;
---------------------------------------------------
end generate LEGACY_MD_WR_RD_ACK_GEN;
-------------------------------------------------
ENHANCED_MD_WR_RD_ACK_GEN: if C_TYPE_OF_AXI4_INTERFACE = 1 generate
-----
begin
-----
-- A write to read only register wont have any effect on register.
-- The transaction is completed by generating WrAck only.
--------------------------------------------------------
-- IP2Bus_Error is generated under following conditions:
-- 1. If an full transmit register/FIFO is written into.
-- 2. If an empty receive register/FIFO is read from.
-- Due to software driver legacy, the register rule test is not applied to SPI.
--------------------------------------------------------
IP2Bus_Error <= intr_ip2bus_error or
rst_ip2bus_error or
transmit_ip2bus_error or
receive_ip2bus_error;
wr_ce_or_reduce_core_cmb <= Bus2IP_WrCE(SPISR) or -- read only register
Bus2IP_WrCE(SPIDRR) or -- read only register
(Bus2IP_WrCE(SPIDTR) and not_Tx_FIFO_FULL) or -- common to
-- spi_fifo_ifmodule_1 and
-- spi_receive_reg_1
-- (FROM TRANSMITTER) module
Bus2IP_WrCE(SPICR) or
Bus2IP_WrCE(SPISSR) or
Bus2IP_WrCE(SPITFOR)or -- locally generated
Bus2IP_WrCE(SPIRFOR)or -- locally generated
Bus2IP_WrCE(REG_HOLE) or -- register hole
or_reduce(Bus2IP_WrCE(17 to 23)); -- holes between reset end and start of SPICR register; -- register hole
--------------------------------------------------
WRITE_ACK_SPIDTR_REG_PROCESS: process(Bus2IP_Clk) is
---------------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
Bus2IP_WrCE_d1 <= '0';
Bus2IP_WrCE_d2 <= '0';
Bus2IP_WrCE_d3 <= '0';
else
Bus2IP_WrCE_d1 <= Bus2IP_WrCE(SPIDTR);
Bus2IP_WrCE_d2 <= Bus2IP_WrCE_d1;
Bus2IP_WrCE_d3 <= Bus2IP_WrCE_d2;
end if; end if;
end process WRITE_ACK_SPIDTR_REG_PROCESS;
Bus2IP_WrCE_pulse_1 <= Bus2IP_WrCE(SPIDTR) and not Bus2IP_WrCE_d1;
Bus2IP_WrCE_pulse_2 <= Bus2IP_WrCE_d1 and not Bus2IP_WrCE_d2;
Bus2IP_WrCE_pulse_3 <= Bus2IP_WrCE_d2 and not Bus2IP_WrCE_d3;
-- WRITE_ACK_CORE_REG_PROCESS : The commong write ACK generation logic when FIFO is
-- ------------------------ not included in the design.
--------------------------------------------------
-- _____|-----|__________ wr_ce_or_reduce_fifo_no
-- ________|-----|_______ ip2Bus_WrAck_fifo_no_d1
-- ________|--|__________ ip2Bus_WrAck_fifo_no from common write ack register
-- this ack will be used in register files for
-- reference.
--------------------------------------------------
WRITE_ACK_CORE_REG_PROCESS: process(Bus2IP_Clk) is
---------------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
ip2Bus_WrAck_core_reg_d1 <= '0';
ip2Bus_WrAck_core_reg <= '0';
ip2Bus_WrAck_core_reg_1 <= '0';
else
ip2Bus_WrAck_core_reg_d1 <= wr_ce_or_reduce_core_cmb;
ip2Bus_WrAck_core_reg <= wr_ce_or_reduce_core_cmb and
(not ip2Bus_WrAck_core_reg_d1);
ip2Bus_WrAck_core_reg_1 <= ip2Bus_WrAck_core_reg;
end if;
end if;
end process WRITE_ACK_CORE_REG_PROCESS;
-------------------------------------------------
-- internal logic uses this signal
wr_ce_reduce_ack_gen <= ip2Bus_WrAck_core_reg;--_1;
-------------------------------------------------
-- common WrAck to IPIF
-- in the enhanced mode for FIFO, the IP2bus_Wrack is provided by the enhanced mode statemachine only.
IP2Bus_WrAck <= intr_ip2bus_wrack or -- common
rst_ip2bus_wrack or -- common
ip2Bus_WrAck_intr_reg_hole or -- newly added to target the holes in register space
(ip2Bus_WrAck_core_reg and (not burst_tr));-- or
--(Tx_FIFO_wr_ack and burst_tr); -- newly added
-------------------------------------------------
--ENHANCED_MD_RD_ACK_GEN: if C_TYPE_OF_AXI4_INTERFACE = 1 generate
-----
--begin
-----
FIFO_NO_RD_CE_GEN: if C_FIFO_EXIST = 0 generate
begin
rd_ce_or_reduce_core_cmb <= Bus2IP_RdCE(SWRESET) or --common locally generated
Bus2IP_RdCE(SPIDTR) or --common locally generated
Bus2IP_RdCE(SPISR) or --common from status register
Bus2IP_RdCE(SPIDRR) or --common to
--spi_fifo_ifmodule_1
--and spi_receive_reg_1
--(FROM RECEIVER) module
Bus2IP_RdCE(SPICR) or --common spi_cntrl_reg_1
Bus2IP_RdCE(SPISSR) or --common spi_status_reg_1
Bus2IP_RdCE(SPITFOR) or --only for fifo_occu TX reg
Bus2IP_RdCE(SPIRFOR) or --only for fifo_occu RX reg
Bus2IP_RdCE(REG_HOLE) or -- register hole
or_reduce(Bus2IP_RdCE(17 to 23)); -- holes between reset end and start of SPICR register; --reg hole
end generate FIFO_NO_RD_CE_GEN;
FIFO_YES_RD_CE_GEN: if C_FIFO_EXIST = 1 generate
begin
rd_ce_or_reduce_core_cmb <= Bus2IP_RdCE(SWRESET) or --common locally generated
Bus2IP_RdCE(SPIDTR) or --common locally generated
Bus2IP_RdCE(SPISR) or --common from status register
--Bus2IP_RdCE(SPIDRR) or --common to
--spi_fifo_ifmodule_1
--and spi_receive_reg_1
--(FROM RECEIVER) module
Bus2IP_RdCE(SPICR) or --common spi_cntrl_reg_1
Bus2IP_RdCE(SPISSR) or --common spi_status_reg_1
Bus2IP_RdCE(SPITFOR) or --only for fifo_occu TX reg
Bus2IP_RdCE(SPIRFOR) or --only for fifo_occu RX reg
Bus2IP_RdCE(REG_HOLE) or -- register hole
or_reduce(Bus2IP_RdCE(17 to 23)); -- holes between reset end and start of SPICR register; --reg hole
end generate FIFO_YES_RD_CE_GEN;
-- READ_ACK_CORE_REG_PROCESS : The commong write ACK generation logic
--------------------------------------------------
-- _____|-----|__________ wr_ce_or_reduce_fifo_no
-- ________|-----|_______ ip2Bus_WrAck_fifo_no_d1
-- ________|--|__________ ip2Bus_WrAck_fifo_no from common write ack register
-- this ack will be used in register files for
-- reference.
--------------------------------------------------
READ_ACK_CORE_REG_PROCESS: process(Bus2IP_Clk) is
-------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
ip2Bus_RdAck_core_reg_d1 <= '0';
ip2Bus_RdAck_core_reg <= '0';
ip2Bus_RdAck_core_reg_1 <= '0';
read_ack_delay_1 <= '0';
read_ack_delay_2 <= '0';
read_ack_delay_3 <= '0';
read_ack_delay_4 <= '0';
read_ack_delay_5 <= '0';
read_ack_delay_6 <= '0';
read_ack_delay_7 <= '0';
else
--ip2Bus_RdAck_core_reg_d1 <= rd_ce_or_reduce_core_cmb;
--ip2Bus_RdAck_core_reg <= rd_ce_or_reduce_core_cmb and
-- (not ip2Bus_RdAck_core_reg_d1);
--ip2Bus_RdAck_core_reg_1 <= ip2Bus_RdAck_core_reg;
read_ack_delay_1 <= rd_ce_or_reduce_core_cmb;
read_ack_delay_2 <= read_ack_delay_1;
read_ack_delay_3 <= read_ack_delay_2;
read_ack_delay_4 <= read_ack_delay_3;
read_ack_delay_5 <= read_ack_delay_4;
read_ack_delay_6 <= read_ack_delay_5;
read_ack_delay_7 <= read_ack_delay_6;
ip2Bus_RdAck_core_reg <= read_ack_delay_6 and (not read_ack_delay_7);
ip2Bus_RdAck_core_reg_1 <= ip2Bus_RdAck_core_reg;
end if;
end if;
end process READ_ACK_CORE_REG_PROCESS;
-------------------------------------------------
-- internal logic uses this signal
rd_ce_reduce_ack_gen <= ip2Bus_RdAck_core_reg; --_1;
-------------------------------------------------
-- common RdAck to IPIF
IP2Bus_RdAck <= intr_ip2bus_rdack or -- common
ip2Bus_RdAck_intr_reg_hole or
ip2Bus_RdAck_core_reg or
(Rx_FIFO_rd_ack and rready);
-----------------------------------------------------
end generate ENHANCED_MD_WR_RD_ACK_GEN;
-------------------------------------------------
--=============================================================================
TX_FIFO_OCC_DATA_FIFO_16: if C_FIFO_DEPTH = 16 generate
-------------------------
begin
-----
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1(0) <= IP2Bus_Tx_FIFO_OCC_Reg_Data_int(0)
and not (Tx_FIFO_Empty_SPISR_to_axi_clk); -- (Tx_FIFO_Empty);
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1(1) <= IP2Bus_Tx_FIFO_OCC_Reg_Data_int(1)
and not (Tx_FIFO_Empty_SPISR_to_axi_clk); -- (Tx_FIFO_Empty);
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1(2) <= IP2Bus_Tx_FIFO_OCC_Reg_Data_int(2)
and not (Tx_FIFO_Empty_SPISR_to_axi_clk); -- (Tx_FIFO_Empty);
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1(3) <= IP2Bus_Tx_FIFO_OCC_Reg_Data_int(3)
and not (Tx_FIFO_Empty_SPISR_to_axi_clk); -- (Tx_FIFO_Empty); --(FIFO_Empty_tx);
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1(0) <= IP2Bus_Rx_FIFO_OCC_Reg_Data_int(0)
and not (Rx_FIFO_Empty);
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1(1) <= IP2Bus_Rx_FIFO_OCC_Reg_Data_int(1)
and not (Rx_FIFO_Empty);
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1(2) <= IP2Bus_Rx_FIFO_OCC_Reg_Data_int(2)
and not (Rx_FIFO_Empty);
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1(3) <= IP2Bus_Rx_FIFO_OCC_Reg_Data_int(3)
and not (Rx_FIFO_Empty); --(FIFO_Empty_rx);
end generate TX_FIFO_OCC_DATA_FIFO_16;
--------------------------------------
TX_FIFO_OCC_DATA_FIFO_256: if C_FIFO_DEPTH = 256 generate
-------------------------
begin
-----
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1(0) <= IP2Bus_Tx_FIFO_OCC_Reg_Data_int(0)
and not (Tx_FIFO_Empty_SPISR_to_axi_clk); -- (Tx_FIFO_Empty);
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1(1) <= IP2Bus_Tx_FIFO_OCC_Reg_Data_int(1)
and not (Tx_FIFO_Empty_SPISR_to_axi_clk); -- (Tx_FIFO_Empty);
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1(2) <= IP2Bus_Tx_FIFO_OCC_Reg_Data_int(2)
and not (Tx_FIFO_Empty_SPISR_to_axi_clk); -- (Tx_FIFO_Empty);
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1(3) <= IP2Bus_Tx_FIFO_OCC_Reg_Data_int(3)
and not (Tx_FIFO_Empty_SPISR_to_axi_clk); -- (Tx_FIFO_Empty);
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1(4) <= IP2Bus_Tx_FIFO_OCC_Reg_Data_int(4)
and not (Tx_FIFO_Empty_SPISR_to_axi_clk); -- (Tx_FIFO_Empty);
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1(5) <= IP2Bus_Tx_FIFO_OCC_Reg_Data_int(5)
and not (Tx_FIFO_Empty_SPISR_to_axi_clk); -- (Tx_FIFO_Empty);
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1(6) <= IP2Bus_Tx_FIFO_OCC_Reg_Data_int(6)
and not (Tx_FIFO_Empty_SPISR_to_axi_clk); -- (Tx_FIFO_Empty);
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1(7) <= IP2Bus_Tx_FIFO_OCC_Reg_Data_int(7)
and not (Tx_FIFO_Empty_SPISR_to_axi_clk); -- (Tx_FIFO_Empty);-- (FIFO_Empty_tx);
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1(0) <= IP2Bus_Rx_FIFO_OCC_Reg_Data_int(0)
and not (Rx_FIFO_Empty);
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1(1) <= IP2Bus_Rx_FIFO_OCC_Reg_Data_int(1)
and not (Rx_FIFO_Empty);
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1(2) <= IP2Bus_Rx_FIFO_OCC_Reg_Data_int(2)
and not (Rx_FIFO_Empty);
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1(3) <= IP2Bus_Rx_FIFO_OCC_Reg_Data_int(3)
and not (Rx_FIFO_Empty);
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1(4) <= IP2Bus_Rx_FIFO_OCC_Reg_Data_int(4)
and not (Rx_FIFO_Empty);
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1(5) <= IP2Bus_Rx_FIFO_OCC_Reg_Data_int(5)
and not (Rx_FIFO_Empty);
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1(6) <= IP2Bus_Rx_FIFO_OCC_Reg_Data_int(6)
and not (Rx_FIFO_Empty);
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1(7) <= IP2Bus_Rx_FIFO_OCC_Reg_Data_int(7)
and not (Rx_FIFO_Empty); --(FIFO_Empty_rx);
end generate TX_FIFO_OCC_DATA_FIFO_256;
--*****************************************************************************
ip2Bus_Data_occupancy_int(0 to (C_S_AXI_DATA_WIDTH-C_OCCUPANCY_NUM_BITS-1))
<= (others => '0');
ip2Bus_Data_occupancy_int((C_S_AXI_DATA_WIDTH-C_OCCUPANCY_NUM_BITS)
to (C_S_AXI_DATA_WIDTH-1))
<= IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1 or
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1;
-------------------------------------------------------------------------------
-- SPECIAL_CASE_WHEN_SS_NOT_EQL_32 : The Special case is executed whenever
-- C_NUM_SS_BITS is less than 32
-------------------------------------------------------------------------------
SPECIAL_CASE_WHEN_SS_NOT_EQL_32: if(C_NUM_SS_BITS /= 32) generate
-----
begin
-----
ip2Bus_Data_SS_int(0 to (C_S_AXI_DATA_WIDTH-C_NUM_SS_BITS-1))
<= (others => '0');
end generate SPECIAL_CASE_WHEN_SS_NOT_EQL_32;
---------------------------------------------
ip2Bus_Data_SS_int((C_S_AXI_DATA_WIDTH-C_NUM_SS_BITS) to
(C_S_AXI_DATA_WIDTH-1)) <= IP2Bus_SPISSR_Data_int;
-------------------------------------------------------------------------------
ip2Bus_Data_Reg_int(0 to C_S_AXI_DATA_WIDTH-C_SPISR_REG_WIDTH-1) <= (others => '0');
ip2Bus_Data_Reg_int(C_S_AXI_DATA_WIDTH-C_SPISR_REG_WIDTH to C_S_AXI_DATA_WIDTH-1)
<= IP2Bus_SPISR_Data_int or -- SPISR - 11 bit
('0' & IP2Bus_SPICR_Data_int); -- SPICR - 10 bit
-------------------------------------------------------------------------------
-----------------------
Receive_Reg_width_is_32: if(C_NUM_TRANSFER_BITS = 32) generate
-----------------------
begin
-----
IP2Bus_Data_received_int <= IP2Bus_Receive_Reg_Data_int;
end generate Receive_Reg_width_is_32;
-----------------------------------------
---------------------------
Receive_Reg_width_is_not_32: if(C_NUM_TRANSFER_BITS /= 32) generate
---------------------------
begin
-----
IP2Bus_Data_received_int(0 to C_S_AXI_DATA_WIDTH-C_NUM_TRANSFER_BITS-1)
<= (others => '0');
IP2Bus_Data_received_int((C_S_AXI_DATA_WIDTH-C_NUM_TRANSFER_BITS) to
(C_S_AXI_DATA_WIDTH-1))
<= IP2Bus_Receive_Reg_Data_int;
end generate Receive_Reg_width_is_not_32;
-----------------------------------------
-------------------------------------------------------------------------------
LEGACY_MD_IP2BUS_DATA_GEN: if C_TYPE_OF_AXI4_INTERFACE = 0 generate
-----
begin
-----
ip2Bus_Data_1 <= ip2Bus_Data_occupancy_int or -- occupancy reg data
ip2Bus_Data_SS_int or -- Slave select reg data
ip2Bus_Data_Reg_int or -- SPI CR & SR reg data
IP2Bus_Data_received_int or -- SPI received data
intr_ip2bus_data ;
REG_IP2BUS_DATA_P:process(Bus2IP_Clk)is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
ip2Bus_Data <= (others => '0');
else
ip2Bus_Data <= ip2Bus_Data_1;
end if;
end if;
end process REG_IP2BUS_DATA_P;
end generate LEGACY_MD_IP2BUS_DATA_GEN;
-------------------------------------------------------------------------------
ENHANCED_MD_IP2BUS_DATA_GEN: if C_TYPE_OF_AXI4_INTERFACE = 1 generate
-----
begin
-----
ip2Bus_Data <= ip2Bus_Data_occupancy_int or -- occupancy reg data
ip2Bus_Data_SS_int or -- Slave select reg data
ip2Bus_Data_Reg_int or -- SPI CR & SR reg data
IP2Bus_Data_received_int or -- SPI received data
intr_ip2bus_data ;
end generate ENHANCED_MD_IP2BUS_DATA_GEN;
-------------------------------------------------------------------------------
RESET_SYNC_AXI_SPI_CLK_INST:entity axi_quad_spi_v3_2.reset_sync_module
port map(
EXT_SPI_CLK => EXT_SPI_CLK ,-- in std_logic;
--Bus2IP_Clk => Bus2IP_Clk ,-- in std_logic;
Soft_Reset_frm_axi => reset2ip_reset_int,-- in std_logic;
Rst_to_spi => Rst_to_spi_int -- out std_logic;
);
--------------------------------------
-- NO_FIFO_EXISTS : Signals initialisation and module
-- instantiation when C_FIFO_EXIST = 0
--------------------------------------
NO_FIFO_EXISTS: if(C_FIFO_EXIST = 0) generate
----------------------------------
signal spisel_pulse_frm_spi_clk : std_logic;
signal spisel_pulse_to_axi_clk : std_logic;
signal spiXfer_done_frm_spi_clk : std_logic;
signal spiXfer_done_to_axi_clk : std_logic;
signal modf_strobe_frm_spi_clk : std_logic;
-- signal modf_strobe_to_axi_clk : std_logic;
signal slave_MODF_strobe_frm_spi_clk : std_logic;
signal slave_MODF_strobe_to_axi_clk : std_logic;
signal receive_data_frm_spi_clk : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal receive_data_to_axi_clk : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal transmit_Data_frm_axi_clk: std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal transmit_Data_to_spi_clk : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal transmit_Data_fifo_0 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal drr_Overrun_int_frm_spi_clk: std_logic;
signal drr_Overrun_int_to_axi_clk : std_logic;
-----
begin
-----
Rx_FIFO_rd_ack <= '0';
Tx_FIFO_Full <= '0';
--------------------------------------------------------------------------
-- I_RECEIVE_REG : INSTANTIATE RECEIVE REGISTER
--------------------------------------------------------------------------
QSPI_RX_TX_REG: entity axi_quad_spi_v3_2.qspi_receive_transmit_reg
generic map
(
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_NUM_TRANSFER_BITS => C_NUM_TRANSFER_BITS
)
port map
(
Bus2IP_Clk => Bus2IP_Clk, -- in
Soft_Reset_op => reset2ip_reset_int, -- in
--SPI Receiver signals -- From AXI clock
Bus2IP_Receive_Reg_RdCE => Bus2IP_RdCE(SPIDRR), -- in
Receive_ip2bus_error => receive_ip2bus_error, -- out
IP2Bus_Receive_Reg_Data => IP2Bus_Receive_Reg_Data_int, -- out
--SPI module ports From SPI clock
SPIXfer_done => spiXfer_done_to_axi_clk,--spiXfer_done_int,-- in
SPI_Received_Data => receive_data_to_axi_clk,--receive_Data_int,-- in vec
-- receive & transmit reg signals
-- DRR_Overrun => drr_Overrun_int,-- drr_Overrun_int,-- out
SR_7_Rx_Empty => Rx_FIFO_Empty_i, -- out
-- From AXI clock
Bus2IP_Transmit_Reg_Data=> Bus2IP_Data, -- in vec
Bus2IP_Transmit_Reg_WrCE=> Bus2IP_WrCE(SPIDTR), -- in
Wr_ce_reduce_ack_gen => wr_ce_reduce_ack_gen, -- in
Rd_ce_reduce_ack_gen => rd_ce_reduce_ack_gen, -- in
--SPI Transmitter signals from AXI clock
Transmit_ip2bus_error => transmit_ip2bus_error, -- out
--SPI module ports
DTR_underrun => dtr_underrun_to_axi_clk,--dtr_underrun_int,-- in
SR_5_Tx_Empty => sr_5_Tx_Empty_int, -- out
DTR_Underrun_strobe => dtr_Underrun_strobe_int, -- out
Transmit_Reg_Data_Out => transmit_Data_fifo_0--transmit_Data_int -- out vec
);
spisel_d1_reg_frm_spi_clk <= spisel_d1_reg;
spisel_pulse_frm_spi_clk <= spisel_pulse_o_int;-- from SPI module
spiXfer_done_frm_spi_clk <= spiXfer_done_int ;-- from SPI module
modf_strobe_frm_spi_clk <= modf_strobe_int ;-- from SPI module
slave_MODF_strobe_frm_spi_clk <= slave_MODF_strobe_int;-- from SPI module
receive_data_frm_spi_clk <= Data_To_Rx_FIFO ; -- from SPI module
dtr_underrun_frm_spi_clk <= dtr_underrun_int; -- from SPI module
transmit_Data_frm_axi_clk <= transmit_Data_fifo_0; -- From AXI clock
Tx_FIFO_Empty_frm_axi_clk <= sr_5_Tx_Empty_int;
Tx_FIFO_Empty_SPISR_frm_spi_clk <= sr_5_Tx_Empty_int;
--Rx_FIFO_Empty_int <= Rx_FIFO_Empty;
Rx_FIFO_Empty_int <= Rx_FIFO_Empty_i;
drr_Overrun_int_frm_spi_clk <= drr_Overrun_int;
SR_3_modf_frm_axi_clk <= SR_3_modf_int;
CROSS_CLK_FIFO_0_INST:entity axi_quad_spi_v3_2.cross_clk_sync_fifo_0
generic map(
C_NUM_TRANSFER_BITS => C_NUM_TRANSFER_BITS,
Async_Clk => Async_Clk ,
--C_AXI_SPI_CLK_EQ_DIFF => C_AXI_SPI_CLK_EQ_DIFF,
C_NUM_SS_BITS => C_NUM_SS_BITS
)
port map(
EXT_SPI_CLK => EXT_SPI_CLK,
Bus2IP_Clk => Bus2IP_Clk ,
Soft_Reset_op => reset2ip_reset_int,
Rst_from_axi_cdc_to_spi => Rst_to_spi_int, -- out std_logic;
----------------------------------------------------------
Tx_FIFO_Empty_cdc_from_axi => Tx_FIFO_Empty_frm_axi_clk,
Tx_FIFO_Empty_cdc_to_spi => Tx_FIFO_Empty,
----------------------------------------------------------
Tx_FIFO_Empty_SPISR_cdc_from_spi => Tx_FIFO_Empty_SPISR_frm_spi_clk,
Tx_FIFO_Empty_SPISR_cdc_to_axi => Tx_FIFO_Empty_SPISR_to_axi_clk,
----------------------------------------------------------
spisel_d1_reg_cdc_from_spi => spisel_d1_reg_frm_spi_clk , -- in
spisel_d1_reg_cdc_to_axi => spisel_d1_reg_to_axi_clk , -- out
----------------------------------------------------------
spisel_pulse_cdc_from_spi => spisel_pulse_frm_spi_clk , -- in
spisel_pulse_cdc_to_axi => spisel_pulse_to_axi_clk , -- out
----------------------------------------------------------
spiXfer_done_cdc_from_spi => spiXfer_done_frm_spi_clk , -- in
spiXfer_done_cdc_to_axi => spiXfer_done_to_axi_clk , -- out
----------------------------------------------------------
modf_strobe_cdc_from_spi => modf_strobe_frm_spi_clk, -- in
modf_strobe_cdc_to_axi => modf_strobe_to_axi_clk , -- out
----------------------------------------------------------
Slave_MODF_strobe_cdc_from_spi => slave_MODF_strobe_frm_spi_clk,-- in
Slave_MODF_strobe_cdc_to_axi => slave_MODF_strobe_to_axi_clk ,-- out
----------------------------------------------------------
receive_Data_cdc_from_spi => receive_Data_frm_spi_clk, -- in
receive_Data_cdc_to_axi => receive_data_to_axi_clk, -- out
----------------------------------------------------------
drr_Overrun_int_cdc_from_spi => drr_Overrun_int_frm_spi_clk, -- in
drr_Overrun_int_cdc_to_axi => drr_Overrun_int_to_axi_clk, -- out
----------------------------------------------------------
dtr_underrun_cdc_from_spi => dtr_underrun_frm_spi_clk, -- in
dtr_underrun_cdc_to_axi => dtr_underrun_to_axi_clk, -- out
----------------------------------------------------------
transmit_Data_cdc_from_axi => transmit_Data_frm_axi_clk, -- in
transmit_Data_cdc_to_spi => transmit_Data_to_spi_clk, -- out
----------------------------
SPICR_0_LOOP_cdc_from_axi => SPICR_0_LOOP_frm_axi_clk,-- in std_logic;
SPICR_0_LOOP_cdc_to_spi => SPICR_0_LOOP_to_spi_clk ,-- out
----------------------------
SPICR_1_SPE_cdc_from_axi => SPICR_1_SPE_frm_axi_clk ,-- in std_logic;
SPICR_1_SPE_cdc_to_spi => SPICR_1_SPE_to_spi_clk ,-- out
----------------------------
SPICR_2_MST_N_SLV_cdc_from_axi => SPICR_2_MST_N_SLV_frm_axi_clk,-- in std_logic;
SPICR_2_MST_N_SLV_cdc_to_spi => SPICR_2_MST_N_SLV_to_spi_clk, -- out
----------------------------
SPICR_3_CPOL_cdc_from_axi => SPICR_3_CPOL_frm_axi_clk,-- in std_logic;
SPICR_3_CPOL_cdc_to_spi => SPICR_3_CPOL_to_spi_clk ,-- out
----------------------------
SPICR_4_CPHA_cdc_from_axi => SPICR_4_CPHA_frm_axi_clk,-- in std_logic;
SPICR_4_CPHA_cdc_to_spi => SPICR_4_CPHA_to_spi_clk ,-- out
----------------------------
SPICR_5_TXFIFO_cdc_from_axi => SPICR_5_TXFIFO_frm_axi_clk,-- in std_logic;
SPICR_5_TXFIFO_cdc_to_spi => SPICR_5_TXFIFO_to_spi_clk, -- out
----------------------------
SPICR_6_RXFIFO_RST_cdc_from_axi=> SPICR_6_RXFIFO_RST_frm_axi_clk,-- in std_logic;
SPICR_6_RXFIFO_RST_cdc_to_spi => SPICR_6_RXFIFO_RST_to_spi_clk ,-- out
----------------------------
SPICR_7_SS_cdc_from_axi => SPICR_7_SS_frm_axi_clk ,-- in std_logic;
SPICR_7_SS_cdc_to_spi => SPICR_7_SS_to_spi_clk ,-- out
----------------------------
SPICR_8_TR_INHIBIT_cdc_from_axi=> SPICR_8_TR_INHIBIT_frm_axi_clk,-- in std_logic;
SPICR_8_TR_INHIBIT_cdc_to_spi => SPICR_8_TR_INHIBIT_to_spi_clk,-- out
----------------------------
SPICR_9_LSB_cdc_from_axi => SPICR_9_LSB_frm_axi_clk,-- in std_logic;
SPICR_9_LSB_cdc_to_spi => SPICR_9_LSB_to_spi_clk,-- out
----------------------------
SPICR_bits_7_8_cdc_from_axi => SPICR_bits_7_8_frm_axi_clk,-- in std_logic_vector
SPICR_bits_7_8_cdc_to_spi => SPICR_bits_7_8_to_spi_clk,-- out
----------------------------
SR_3_modf_cdc_from_axi => SR_3_modf_frm_axi_clk, -- in
SR_3_modf_cdc_to_spi => SR_3_modf_to_spi_clk , -- out
----------------------------
SPISSR_cdc_from_axi => SPISSR_frm_axi_clk, -- in
SPISSR_cdc_to_spi => register_Data_slvsel_int -- out
----------------------------
);
Data_From_TxFIFO <= transmit_Data_to_spi_clk;
rc_FIFO_Full_strobe_int <= '0';
rc_FIFO_occ_Reversed_int <= (others => '0');
rc_FIFO_Data_Out_int <= (others => '0');
data_Exists_RcFIFO_int <= '0';
tx_FIFO_Empty_strobe_int <= '0';
tx_FIFO_occ_Reversed_int <= (others => '0');
data_Exists_TxFIFO_int <= '0';
data_From_TxFIFO_int <= (others => '0');
tx_FIFO_less_half_int <= '0';
reset_TxFIFO_ptr_int <= '0';
reset_RcFIFO_ptr_int <= '0';
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1 <= (others => '0');
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1 <= (others => '0');
Tx_FIFO_Full_int <= not(sr_5_Tx_Empty_int); -- Tx_FIFO_Empty_to_axi_clk);
Rx_FIFO_Full_int <= not(Rx_FIFO_Empty_i);
--------------------------------------------------------------------------
bus2IP_Data_for_interrupt_core(0 to 14) <= Bus2IP_Data(0 to 14);
bus2IP_Data_for_interrupt_core(15 to 22) <= (others => '0');
-- below code manipulates the bus2ip_data going towards interrupt control
-- unit. In FIFO=0, case bit 23 and 25 of IPIER are not applicable.
-- Bu2IP Data to Interrupt Registers - IPISR and IPIER
-- Bus2IP_Data - 0 31
-- IPISR/IPIER - 0 22 23 31
-- <---NA---> <-used->
-- 23 24 25 26 27 28 29 30 31
-- DRR_Not Slave Tx_FIFO DRR_ DRR_ DTR_ DTR Slave MODF
-- _Empty Select_mode Half_Empty Over_Run Full Underrun Empty MODF
-- NA-fifo-0 NA -fifo-0
bus2IP_Data_for_interrupt_core(23) <= '0'; -- DRR_Not_Empty bit in IPIER/IPISR
bus2IP_Data_for_interrupt_core(24) <= Bus2IP_Data(24);
bus2IP_Data_for_interrupt_core(25) <= '0'; -- Tx FIFO Half Empty
bus2IP_Data_for_interrupt_core(26 to (C_S_AXI_DATA_WIDTH-1)) <=
Bus2IP_Data(26 to (C_S_AXI_DATA_WIDTH-1));
--------------------------------------------------------------------------
-- Interrupt Status Register(IPISR) Mapping
ip2Bus_IntrEvent_int(13) <= '0'; -- doesnt exist in the FIFO = 0 case
ip2Bus_IntrEvent_int(12) <= '0'; -- doesnt exist in the FIFO = 0 case
ip2Bus_IntrEvent_int(11) <= '0'; -- doesnt exist in the FIFO = 0 case
ip2Bus_IntrEvent_int(10) <= '0'; -- doesnt exist in the FIFO = 0 case
ip2Bus_IntrEvent_int(9) <= '0'; -- doesnt exist in the FIFO = 0 case
ip2Bus_IntrEvent_int(8) <= '0'; -- doesnt exist in the FIFO = 0 case
ip2Bus_IntrEvent_int(7) <= spisel_pulse_to_axi_clk; -- spisel_pulse_o_int;
ip2Bus_IntrEvent_int(6) <= '0'; --
ip2Bus_IntrEvent_int(5) <= drr_Overrun_int_to_axi_clk; -- drr_Overrun_int_to_axi_clk;
ip2Bus_IntrEvent_int(4) <= spiXfer_done_to_axi_clk; -- spiXfer_done_int;
ip2Bus_IntrEvent_int(3) <= dtr_Underrun_strobe_int;
ip2Bus_IntrEvent_int(2) <= spiXfer_done_to_axi_clk; -- spiXfer_done_int;
ip2Bus_IntrEvent_int(1) <= slave_MODF_strobe_to_axi_clk; -- slave_MODF_strobe_int;
ip2Bus_IntrEvent_int(0) <= modf_strobe_to_axi_clk; -- modf_strobe_int;
end generate NO_FIFO_EXISTS;
-------------------------------------------------------------------------------
-- FIFO_EXISTS : Signals initialisation and module
-- instantiation when C_FIFO_EXIST = 1
-------------------------------------------------------------------------------
FIFO_EXISTS: if(C_FIFO_EXIST = 1) generate
------------------------------
constant C_RD_COUNT_WIDTH_INT : integer := clog2(C_FIFO_DEPTH);
constant C_WR_COUNT_WIDTH_INT : integer := clog2(C_FIFO_DEPTH);
constant RX_FIFO_CNTR_WIDTH: integer := clog2(C_FIFO_DEPTH);
constant TX_FIFO_CNTR_WIDTH: integer := clog2(C_FIFO_DEPTH);
constant ZERO_RX_FIFO_CNT : std_logic_vector(RX_FIFO_CNTR_WIDTH-1 downto 0) := (others => '0');
constant ZERO_TX_FIFO_CNT : std_logic_vector(TX_FIFO_CNTR_WIDTH-1 downto 0) := (others => '0');
signal rx_fifo_count: std_logic_vector(RX_FIFO_CNTR_WIDTH-1 downto 0);
signal tx_fifo_count: std_logic_vector(TX_FIFO_CNTR_WIDTH-1 downto 0);
signal tx_fifo_count_d1: std_logic_vector(TX_FIFO_CNTR_WIDTH-1 downto 0);
signal tx_fifo_count_d2: std_logic_vector(TX_FIFO_CNTR_WIDTH-1 downto 0);
signal Tx_FIFO_Empty_1 : std_logic;
signal Tx_FIFO_Empty_intr : std_logic;
signal IP2Bus_RdAck_receive_enable : std_logic;
signal IP2Bus_WrAck_transmit_enable : std_logic;
constant ALL_0 : std_logic_vector(0 to TX_FIFO_CNTR_WIDTH-1)
:= (others => '1');
signal data_Exists_RcFIFO_int_d1: std_logic;
signal data_Exists_RcFIFO_pulse : std_logic;
--signal FIFO_Empty_rx : std_logic;
--signal SPISR_0_CMD_Error_frm_spi_clk : std_logic;
--signal SPISR_0_CMD_Error_to_axi_clk : std_logic;
--signal spisel_d1_reg_frm_spi_clk : std_logic;
--signal spisel_d1_reg_to_axi_clk : std_logic;
signal tx_occ_msb_111 : std_logic:= '0';
signal tx_occ_msb_11 : std_logic_vector(TX_FIFO_CNTR_WIDTH-1 downto 0);
signal spisel_pulse_frm_spi_clk : std_logic;
signal spisel_pulse_to_axi_clk : std_logic;
signal slave_MODF_strobe_frm_spi_clk : std_logic;
signal slave_MODF_strobe_to_axi_clk : std_logic;
signal Rx_FIFO_Empty_frm_axi_clk : std_logic;
signal Rx_FIFO_Empty_to_spi_clk : std_logic;
signal Tx_FIFO_Full_frm_axi_clk : std_logic;
signal Tx_FIFO_Full_to_spi_clk : std_logic;
signal spiXfer_done_frm_spi_clk : std_logic;
signal spiXfer_done_to_axi_clk : std_logic;
signal SR_3_modf_frm_axi_clk : std_logic;
signal spiXfer_done_to_axi_1 : std_logic;
signal spiXfer_done_to_axi_d1 : std_logic;
signal updown_cnt_en : std_logic;
signal drr_Overrun_int_to_axi_clk : std_logic;
signal drr_Overrun_int_frm_spi_clk: std_logic;
-----
begin
-----
SPISR_0_CMD_Error_frm_spi_clk <= SPISR_0_CMD_Error_int;
spisel_d1_reg_frm_spi_clk <= spisel_d1_reg;
spisel_pulse_frm_spi_clk <= spisel_pulse_o_int;-- from SPI module
slave_MODF_strobe_frm_spi_clk <= slave_MODF_strobe_int; -- from SPI module
modf_strobe_frm_spi_clk <= modf_strobe_int; -- spi module
Rx_FIFO_Full_frm_axi_clk <= Rx_FIFO_Full; -- from Async Receive FIFO
Tx_FIFO_Empty_frm_spi_clk <= Tx_FIFO_Empty_intr; -- Tx_FIFO_Empty; -- from Async Transmit FIFO
spiXfer_done_frm_spi_clk <= spiXfer_done_int; -- from SPI module
dtr_underrun_frm_spi_clk <= dtr_underrun_int; -- from SPI module
Tx_FIFO_Empty_SPISR_frm_spi_clk <= Tx_FIFO_Empty;-- from TX FIFO for SPI Status register
drr_Overrun_int_frm_spi_clk <= drr_Overrun_int;
-- SPICR_6_RXFIFO_RST_frm_axi_clk<= SPICR_6_RXFIFO_RST_frm_axi_clk; -- from SPICR
reset_RcFIFO_ptr_frm_axi_clk <= reset_RcFIFO_ptr_int; -- from AXI clock
Rx_FIFO_Empty_frm_axi_clk <= Rx_FIFO_Empty; -- from Async Receive FIFO AXI side
Tx_FIFO_Full_frm_axi_clk <= Tx_FIFO_Full; -- from Async Transmit FIFO AXI side
SR_3_modf_frm_axi_clk <= SR_3_modf_int;
--CLK_CROSS_I:
CLK_CROSS_I:entity axi_quad_spi_v3_2.cross_clk_sync_fifo_1
generic map(
C_FAMILY => C_FAMILY ,
C_FIFO_DEPTH => C_FIFO_DEPTH ,
Async_Clk => Async_Clk ,
C_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
C_NUM_TRANSFER_BITS => C_NUM_TRANSFER_BITS,
C_NUM_SS_BITS => C_NUM_SS_BITS
)
port map(
EXT_SPI_CLK => EXT_SPI_CLK , -- in std_logic;
Bus2IP_Clk => Bus2IP_Clk , -- in std_logic;
Soft_Reset_op => reset2ip_reset_int ,
--Soft_Reset_op => Soft_Reset_op , -- in std_logic;
Rst_cdc_to_spi => Rst_to_spi_int , -- out std_logic;
----------------------------
SPISR_0_CMD_Error_cdc_from_spi => SPISR_0_CMD_Error_frm_spi_clk ,
SPISR_0_CMD_Error_cdc_to_axi => SPISR_0_CMD_Error_to_axi_clk ,
----------------------------------------------------------
spisel_d1_reg_cdc_from_spi => spisel_d1_reg_frm_spi_clk , -- in
spisel_d1_reg_cdc_to_axi => spisel_d1_reg_to_axi_clk , -- out
----------------------------------------------------------
spisel_pulse_cdc_from_spi => spisel_pulse_frm_spi_clk , -- in
spisel_pulse_cdc_to_axi => spisel_pulse_to_axi_clk , -- out
----------------------------
Mst_N_Slv_mode_cdc_from_spi => Mst_N_Slv_mode_frm_spi_clk , -- in
Mst_N_Slv_mode_cdc_to_axi => Mst_N_Slv_mode_to_axi_clk , -- out
----------------------------
slave_MODF_strobe_cdc_from_spi => slave_MODF_strobe_frm_spi_clk, -- in
slave_MODF_strobe_cdc_to_axi => slave_MODF_strobe_to_axi_clk , -- out
----------------------------
modf_strobe_cdc_from_spi => modf_strobe_frm_spi_clk , -- in
modf_strobe_cdc_to_axi => modf_strobe_to_axi_clk , -- out
----------------------------
SPICR_6_RXFIFO_RST_cdc_from_axi=> SPICR_6_RXFIFO_RST_frm_axi_clk, -- in
SPICR_6_RXFIFO_RST_cdc_to_spi => SPICR_6_RXFIFO_RST_to_spi_clk , -- out
----------------------------
Rx_FIFO_Full_cdc_from_axi => Rx_FIFO_Full_frm_axi_clk, -- in
Rx_FIFO_Full_cdc_to_spi => Rx_FIFO_Full_to_spi_clk , -- out
----------------------------
reset_RcFIFO_ptr_cdc_from_axi => reset_RcFIFO_ptr_frm_axi_clk, -- in
reset_RcFIFO_ptr_cdc_to_spi => reset_RcFIFO_ptr_to_spi_clk , -- out
----------------------------
Rx_FIFO_Empty_cdc_from_axi => Rx_FIFO_Empty_frm_axi_clk , -- in
Rx_FIFO_Empty_cdc_to_spi => Rx_FIFO_Empty_to_spi_clk , -- out
----------------------------
Tx_FIFO_Empty_cdc_from_spi => Tx_FIFO_Empty_frm_spi_clk, -- in
Tx_FIFO_Empty_cdc_to_axi => Tx_FIFO_Empty_to_Axi_clk, -- out
----------------------------
Tx_FIFO_Empty_SPISR_cdc_from_spi => Tx_FIFO_Empty_SPISR_frm_spi_clk,
Tx_FIFO_Empty_SPISR_cdc_to_axi => Tx_FIFO_Empty_SPISR_to_axi_clk,
Tx_FIFO_Full_cdc_from_axi => Tx_FIFO_Full_frm_axi_clk,-- in
Tx_FIFO_Full_cdc_to_spi => Tx_FIFO_Full_to_spi_clk ,-- out
----------------------------
spiXfer_done_cdc_from_spi => spiXfer_done_frm_spi_clk, -- in
spiXfer_done_cdc_to_axi => spiXfer_done_to_axi_clk, -- out
----------------------------
dtr_underrun_cdc_from_spi => dtr_underrun_frm_spi_clk, -- in
dtr_underrun_cdc_to_axi => dtr_underrun_to_axi_clk , -- out
----------------------------
SPICR_0_LOOP_cdc_from_axi => SPICR_0_LOOP_frm_axi_clk,-- in std_logic;
SPICR_0_LOOP_cdc_to_spi => SPICR_0_LOOP_to_spi_clk ,-- out
----------------------------
SPICR_1_SPE_cdc_from_axi => SPICR_1_SPE_frm_axi_clk ,-- in std_logic;
SPICR_1_SPE_cdc_to_spi => SPICR_1_SPE_to_spi_clk ,-- out
----------------------------
SPICR_2_MST_N_SLV_cdc_from_axi => SPICR_2_MST_N_SLV_frm_axi_clk,-- in std_logic;
SPICR_2_MST_N_SLV_cdc_to_spi => SPICR_2_MST_N_SLV_to_spi_clk, -- out
----------------------------
SPICR_3_CPOL_cdc_from_axi => SPICR_3_CPOL_frm_axi_clk,-- in std_logic;
SPICR_3_CPOL_cdc_to_spi => SPICR_3_CPOL_to_spi_clk ,-- out
----------------------------
SPICR_4_CPHA_cdc_from_axi => SPICR_4_CPHA_frm_axi_clk,-- in std_logic;
SPICR_4_CPHA_cdc_to_spi => SPICR_4_CPHA_to_spi_clk ,-- out
----------------------------
SPICR_5_TXFIFO_cdc_from_axi => SPICR_5_TXFIFO_RST_frm_axi_clk,-- in std_logic;
SPICR_5_TXFIFO_cdc_to_spi => SPICR_5_TXFIFO_to_spi_clk, -- out
----------------------------
SPICR_7_SS_cdc_from_axi => SPICR_7_SS_frm_axi_clk ,-- in std_logic;
SPICR_7_SS_cdc_to_spi => SPICR_7_SS_to_spi_clk ,-- out
----------------------------
SPICR_8_TR_INHIBIT_cdc_from_axi=> SPICR_8_TR_INHIBIT_frm_axi_clk,-- in std_logic;
SPICR_8_TR_INHIBIT_cdc_to_spi => SPICR_8_TR_INHIBIT_to_spi_clk,-- out
----------------------------
SPICR_9_LSB_cdc_from_axi => SPICR_9_LSB_frm_axi_clk,-- in std_logic;
SPICR_9_LSB_cdc_to_spi => SPICR_9_LSB_to_spi_clk,-- out
----------------------------
SPICR_bits_7_8_cdc_from_axi => SPICR_bits_7_8_frm_axi_clk,-- in std_logic_vector
SPICR_bits_7_8_cdc_to_spi => SPICR_bits_7_8_to_spi_clk,-- out
----------------------------
SR_3_modf_cdc_from_axi => SR_3_modf_frm_axi_clk, -- in
SR_3_modf_cdc_to_spi => SR_3_modf_to_spi_clk , -- out
----------------------------
SPISSR_cdc_from_axi => SPISSR_frm_axi_clk, -- in
SPISSR_cdc_to_spi => register_Data_slvsel_int, -- out
----------------------------
spiXfer_done_cdc_to_axi_1 => spiXfer_done_to_axi_1,
----------------------------
drr_Overrun_int_cdc_from_spi => drr_Overrun_int_frm_spi_clk,
drr_Overrun_int_cdc_to_axi => drr_Overrun_int_to_axi_clk
----------------------------
);
-- Bu2IP Data to Interrupt Registers - IPISR and IPIER
-- Bus2IP_Data - 0 31
-- IPISR/IPIER - 0 17 18 31
-- <---NA---> <-used->
-- 18 19 20 21 22 23 24 25 26 27 28 29 30 31
-- CMD_ Loop_Bk MSB Slave_Mode CPOL_CPHA DRR_Not Slave Tx_FIFO DRR_ DRR_ DTR_ DTR Slave MODF
-- Error Error Error Error Error _Empty Select_mode Half_Empty Over_Run Full Underrun Empty MODF
-- In Slave
-- mode_only
-- <---------------------------------------> <------------------------------------------------------------->
-- In C_SPI_MODE 1 or 2 only Present in all conditions
-- IPISR Write
-- when FIFO = 1,all other the IPIER, IPISR interrupt bits are applicable based upon the SPI mode.
-- DRR_Not_Empty bit (bit 23) - available only in case of core is selected in
-- slave mode and control register mst_n_slv bit is '0'.
-- Slave_select_mode bit-available only in case of core is selected in slave mode
-- common assignment to SPI_MODE 1/2 and SPI_MODE = 0
bus2IP_Data_for_interrupt_core(0 to 17) <= Bus2IP_Data(0 to 17);
DUAL_MD_IPISR_GEN: if C_SPI_MODE = 1 or C_SPI_MODE = 2 generate
-----------------------
begin
-----
bus2IP_Data_for_interrupt_core(18 to 22) <= Bus2IP_Data(18 to 22);
end generate DUAL_MD_IPISR_GEN;
---------------------------------------------
STD_MD_IPISR_GEN: if C_SPI_MODE = 0 generate
-----------------------------------
begin
-----
bus2IP_Data_for_interrupt_core(18 to 22)<= (others => '0');
end generate STD_MD_IPISR_GEN;
------------------------------------------------
bus2IP_Data_for_interrupt_core(23) <= Bus2IP_Data(23) and -- exists only when FIFO = exists AND
((not spisel_d1_reg_to_axi_clk) --spisel_d1_reg)
or -- core is selected by asserting SPISEL by ext. master AND
(not SPICR_2_MST_N_SLV_frm_axi_clk) --Mst_N_Slv_mode) -- core is in slave mode
);
bus2IP_Data_for_interrupt_core(24 to (C_S_AXI_DATA_WIDTH-1)) <=
Bus2IP_Data(24 to (C_S_AXI_DATA_WIDTH-1));
--
----------------------------------------------------
-- _____|------------- data_Exists_RcFIFO_int
-- ________|---------- data_Exists_RcFIFO_int_d1
-- _____|--|__________ data_Exists_RcFIFO_pulse
----------------------------------------------------
DRR_NOT_EMPTY_PULSE_P: process(Bus2IP_Clk) is
-----
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
data_Exists_RcFIFO_int_d1 <= '0';
else
data_Exists_RcFIFO_int_d1 <= not rx_fifo_empty_i; -- data_Exists_RcFIFO_int;
end if;
end if;
end process DRR_NOT_EMPTY_PULSE_P;
------------------------------------
data_Exists_RcFIFO_pulse <= not rx_fifo_empty_i and
(not data_Exists_RcFIFO_int_d1);
------------------------------------
---------------------------------------------------------------------------
DUAL_MD_INTR_GEN: if C_SPI_MODE = 1 or C_SPI_MODE = 2 generate
-----------------------
signal SPISR_4_CPOL_CPHA_Error_d1 : std_logic;
signal SPISR_3_Slave_Mode_Error_d1 : std_logic;
signal SPISR_2_MSB_Error_d1 : std_logic;
signal SPISR_1_LOOP_Back_Error_d1 : std_logic;
signal SPISR_0_CMD_Error_d1 : std_logic;
signal SPISR_4_CPOL_CPHA_Error_pulse : std_logic;
signal SPISR_3_Slave_Mode_Error_pulse: std_logic;
signal SPISR_2_MSB_Error_pulse : std_logic;
signal SPISR_1_LOOP_Back_Error_pulse : std_logic;
signal SPISR_0_CMD_Error_pulse : std_logic;
-----
begin
-----
INTR_UPPER_BITS_P: process(Bus2IP_Clk) is
-----
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
SPISR_0_CMD_Error_d1 <= '0';
SPISR_1_LOOP_Back_Error_d1 <= '0';
SPISR_2_MSB_Error_d1 <= '0';
SPISR_3_Slave_Mode_Error_d1 <= '0';
SPISR_4_CPOL_CPHA_Error_d1 <= '0';
else
SPISR_0_CMD_Error_d1 <= SPISR_0_CMD_Error_to_axi_clk; -- SPISR_0_CMD_Error_int;
SPISR_1_LOOP_Back_Error_d1 <= SPISR_1_LOOP_Back_Error_int; -- from SPICR
SPISR_2_MSB_Error_d1 <= SPISR_2_MSB_Error_int; -- from SPICR
SPISR_3_Slave_Mode_Error_d1 <= SPISR_3_Slave_Mode_Error_int;-- from SPICR
SPISR_4_CPOL_CPHA_Error_d1 <= SPISR_4_CPOL_CPHA_Error_int; -- from SPICR
end if;
end if;
end process INTR_UPPER_BITS_P;
------------------------------------
SPISR_0_CMD_Error_pulse <= SPISR_0_CMD_Error_to_axi_clk -- SPISR_0_CMD_Error_int
and (not SPISR_0_CMD_Error_d1);
SPISR_1_LOOP_Back_Error_pulse <= SPISR_1_LOOP_Back_Error_int
and (not SPISR_1_LOOP_Back_Error_d1);
SPISR_2_MSB_Error_pulse <= SPISR_2_MSB_Error_int
and (not SPISR_2_MSB_Error_d1);
SPISR_3_Slave_Mode_Error_pulse <= SPISR_3_Slave_Mode_Error_int
and (not SPISR_3_Slave_Mode_Error_d1);
SPISR_4_CPOL_CPHA_Error_pulse <= SPISR_4_CPOL_CPHA_Error_int
and (not SPISR_4_CPOL_CPHA_Error_d1);
-- Interrupt Status Register(IPISR) Mapping
ip2Bus_IntrEvent_int(13) <= SPISR_0_CMD_Error_pulse;
ip2Bus_IntrEvent_int(12) <= SPISR_1_LOOP_Back_Error_pulse;
ip2Bus_IntrEvent_int(11) <= SPISR_2_MSB_Error_pulse;
ip2Bus_IntrEvent_int(10) <= SPISR_3_Slave_Mode_Error_pulse;
ip2Bus_IntrEvent_int(9) <= SPISR_4_CPOL_CPHA_Error_pulse ;
end generate DUAL_MD_INTR_GEN;
--------------------------------------------
STD_MD_INTR_GEN: if C_SPI_MODE = 0 generate
-----------------------
begin
-----
ip2Bus_IntrEvent_int(13) <= '0';
ip2Bus_IntrEvent_int(12) <= '0';
ip2Bus_IntrEvent_int(11) <= '0';
ip2Bus_IntrEvent_int(10) <= '0';
ip2Bus_IntrEvent_int(9) <= '0';
end generate STD_MD_INTR_GEN;
-----------------------------------------------
ip2Bus_IntrEvent_int(8) <= data_Exists_RcFIFO_pulse and
((not spisel_d1_reg_to_axi_clk) -- spisel_d1_reg)
or
(not SPICR_2_MST_N_SLV_frm_axi_clk) -- Mst_N_Slv_mode)
);
ip2Bus_IntrEvent_int(7) <= spisel_pulse_to_axi_clk;-- and not SPICR_2_MST_N_SLV_frm_axi_clk; -- spisel_pulse_o_int;-- spi_module
ip2Bus_IntrEvent_int(6) <= tx_FIFO_less_half_int; -- qspi_fifo_ifmodule
ip2Bus_IntrEvent_int(5) <= drr_Overrun_int_to_axi_clk; -- drr_Overrun_int; -- qspi_fifo_ifmodule
ip2Bus_IntrEvent_int(4) <= rc_FIFO_Full_strobe_int; -- qspi_fifo_ifmodule
ip2Bus_IntrEvent_int(3) <= dtr_Underrun_strobe_int; -- qspi_fifo_ifmodule
ip2Bus_IntrEvent_int(2) <= tx_FIFO_Empty_strobe_int; -- qspi_fifo_ifmodule
ip2Bus_IntrEvent_int(1) <= slave_MODF_strobe_to_axi_clk; --slave_MODF_strobe_int;-- spi_module
ip2Bus_IntrEvent_int(0) <= modf_strobe_to_axi_clk; -- modf_strobe_int; -- spi_module
--Combinatorial operations
reset_TxFIFO_ptr_int <= reset2ip_reset_int or SPICR_5_TXFIFO_RST_frm_axi_clk;
reset_TxFIFO_ptr_int_to_spi <= Rst_to_spi_int or SPICR_5_TXFIFO_to_spi_clk;
--reset_RcFIFO_ptr_int <= Rst_to_spi_int or SPICR_6_RXFIFO_RST_to_spi_clk; -- SPICR_6_RXFIFO_RST_int;
reset_RcFIFO_ptr_int <= reset2ip_reset_int or SPICR_6_RXFIFO_RST_frm_axi_clk;
sr_5_Tx_Empty_int <= not (data_Exists_TxFIFO_int);
Rc_FIFO_Empty_int <= Rx_FIFO_Empty;--not (data_Exists_RcFIFO_int);
-- AXI Clk domain -- __________________ SPI clk domain
--Dout --|AXI clk |-- Din
--Rd_en --| |-- Wr_en
--Rd_clk --| |-- Wr_clk
--| |--
--Rx_FIFO_Empty --| Rx FIFO |-- Rx_FIFO_Full
--Rx_FIFO_almost_Empty --| |-- Rx_FIFO_almost_Full
--Rx_FIFO_occ_Reversed --| |--
--Rx_FIFO_rd_ack --| |--
--| |--
--| |--
--| |--
--|__________________|--
RX_RD_EN_LEG_MD_GEN: if C_TYPE_OF_AXI4_INTERFACE = 0 generate
begin
-----
IP2Bus_RdAck_receive_enable <= (rd_ce_reduce_ack_gen and
Bus2IP_RdCE(SPIDRR)
)and
(not Rx_FIFO_Empty);
end generate RX_RD_EN_LEG_MD_GEN;
RX_RD_EN_ENHAN_MD_GEN: if C_TYPE_OF_AXI4_INTERFACE = 1 generate
begin
-----
IP2Bus_RdAck_receive_enable <= --(rd_ce_reduce_ack_gen and
(rready and
Bus2IP_RdCE(SPIDRR)
)and
(not Rx_FIFO_Empty);
end generate RX_RD_EN_ENHAN_MD_GEN;
-- Receive FIFO Logic
rx_fifo_reset <= Rst_to_spi_int or reset_RcFIFO_ptr_to_spi_clk;
RX_FIFO_II: entity lib_fifo_v1_0.async_fifo_fg --axi_quad_spi_v3_2.async_fifo_fg --lib_fifo_v1_0.async_fifo_fg
generic map(
-- for first word fall through FIFO below two parameters setting is must please dont change
C_PRELOAD_LATENCY => 0 ,-- this is newly added and async_fifo_fg is referred from proc common v4_0
C_PRELOAD_REGS => 1 ,-- this is newly added and async_fifo_fg is referred from proc common v4_0
-- variables
C_ALLOW_2N_DEPTH => 1 , -- : Integer := 0; -- New paramter to leverage FIFO Gen 2**N depth
C_FAMILY => C_FAMILY , -- : String := "virtex5"; -- new for FIFO Gen
C_DATA_WIDTH => C_NUM_TRANSFER_BITS, -- : integer := 16;
C_FIFO_DEPTH => C_FIFO_DEPTH , -- : integer := 15;
C_RD_COUNT_WIDTH => C_RD_COUNT_WIDTH_INT,-- : integer := 3 ;
C_WR_COUNT_WIDTH => C_WR_COUNT_WIDTH_INT,-- : integer := 3 ;
C_HAS_ALMOST_EMPTY => 1 , -- : integer := 1 ;
C_HAS_ALMOST_FULL => 1 , -- : integer := 1 ;
C_HAS_RD_ACK => 1 , -- : integer := 0 ;
C_HAS_RD_COUNT => 1 , -- : integer := 1 ;
C_HAS_WR_ACK => 1 , -- : integer := 0 ;
C_HAS_WR_COUNT => 1 , -- : integer := 1 ;
-- constants
C_HAS_RD_ERR => 0 , -- : integer := 0 ;
C_HAS_WR_ERR => 0 , -- : integer := 0 ;
C_RD_ACK_LOW => 0 , -- : integer := 0 ;
C_RD_ERR_LOW => 0 , -- : integer := 0 ;
C_WR_ACK_LOW => 0 , -- : integer := 0 ;
C_WR_ERR_LOW => 0 , -- : integer := 0
C_ENABLE_RLOCS => 0 , -- : integer := 0 ; -- not supported in FG
C_USE_BLOCKMEM => 0 -- : integer := 1 ; -- 0 = distributed RAM, 1 = BRAM
)
port map(
Din => Data_To_Rx_FIFO , -- : in std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0');
Wr_en => spiXfer_done_int, --SPIXfer_done_Rx_Wr_en, -- , -- : in std_logic := '1';
Wr_clk => EXT_SPI_CLK , -- : in std_logic := '1';
Wr_ack => Rx_FIFO_wr_ack_open , -- : out std_logic;
------
Dout => Data_From_Rx_FIFO , -- : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
Rd_en => IP2Bus_RdAck_receive_enable , -- : in std_logic := '0';
Rd_clk => Bus2IP_Clk , -- : in std_logic := '1';
Rd_ack => Rx_FIFO_rd_ack , -- : out std_logic;
------
Full => open, --Rx_FIFO_Full , -- : out std_logic;
Empty => Rx_FIFO_Empty , -- : out std_logic;
Almost_full => Rx_FIFO_almost_Full , -- : out std_logic;
Almost_empty => Rx_FIFO_almost_Empty , -- : out std_logic;
Rd_count => Rx_FIFO_occ_Reversed , -- : out std_logic_vector(C_RD_COUNT_WIDTH-1 downto 0);
------
Ainit => rx_fifo_reset, -- reset_RcFIFO_ptr_to_spi_clk ,--reset_RcFIFO_ptr_int, -- reset_RcFIFO_ptr_to_spi_clk ,--Rx_FIFO_ptr_RST , -- : in std_logic := '1';
Wr_count => open , -- : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0);
Rd_err => open , -- : out std_logic;
Wr_err => open -- : out std_logic
);
RX_FIFO_FULL_CNTR_I : entity axi_quad_spi_v3_2.counter_f
generic map(
C_NUM_BITS => RX_FIFO_CNTR_WIDTH,
C_FAMILY => "nofamily"
)
port map(
Clk => Bus2IP_Clk, -- in
Rst => '0', -- in
Load_In => ALL_0, -- in
Count_Enable => updown_cnt_en_rx, -- in
----------------
Count_Load => reset_RcFIFO_ptr_int, -- in
----------------
Count_Down => IP2Bus_RdAck_receive_enable, -- in
Count_Out => rx_fifo_count, -- out std_logic_vector
Carry_Out => open -- out
);
updown_cnt_en_rx <= IP2Bus_RdAck_receive_enable or spiXfer_done_to_axi_1;
RX_one_less_than_full <= and_reduce(rx_fifo_count(RX_FIFO_CNTR_WIDTH-1 downto RX_FIFO_CNTR_WIDTH-RX_FIFO_CNTR_WIDTH+1)) and
(not rx_fifo_count(0))and spiXfer_done_to_axi_1;
RX_FULL_EMP_MD_12_INTR_GEN: if C_SPI_MODE /= 0 generate
-----
--signal rx_fifo_empty_i : std_logic;
begin
-----
RX_FIFO_EMPTY_P:process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(reset2ip_reset_int = RESET_ACTIVE)then
rx_fifo_empty_i <= '1';
elsif(reset_RcFIFO_ptr_int = '1')then
rx_fifo_empty_i <= '1';
elsif(spiXfer_done_to_axi_1 = '1')then
rx_fifo_empty_i <= '0';
end if;
end if;
end process RX_FIFO_EMPTY_P;
RX_FIFO_FULL_P:process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(reset2ip_reset_int = RESET_ACTIVE)then
Rx_FIFO_Full_int <= '0';
elsif(reset_RcFIFO_ptr_int = '1') or (drr_Overrun_int_to_axi_clk = '1') then --(drr_Overrun_int = '1')then
Rx_FIFO_Full_int <= '0';
elsif(RX_one_less_than_full = '1' and
spiXfer_done_to_axi_1 = '1' and
rx_fifo_empty_i = '0')then
Rx_FIFO_Full_int <= '1';
end if;
end if;
end process RX_FIFO_FULL_P;
end generate RX_FULL_EMP_MD_12_INTR_GEN;
------------------------------------
RX_FULL_EMP_MD_0_GEN: if C_SPI_MODE = 0 generate
--signal rx_fifo_empty_i : std_logic;
-----
begin
-----
RX_FIFO_EMPTY_P:process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(reset2ip_reset_int = RESET_ACTIVE)then
rx_fifo_empty_i <= '1';
elsif(reset_RcFIFO_ptr_int = '1')then
rx_fifo_empty_i <= '1';
elsif(spiXfer_done_to_axi_1 = '1')then
rx_fifo_empty_i <= '0';
end if;
end if;
end process RX_FIFO_EMPTY_P;
-------------------------------------------
RX_FIFO_ABT_TO_FULL_P:process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(reset2ip_reset_int = RESET_ACTIVE)then
Rx_FIFO_Full_i <= '0';
elsif(reset_RcFIFO_ptr_int = '1') or (drr_Overrun_int_to_axi_clk = '1') then -- (drr_Overrun_int = '1')then
Rx_FIFO_Full_i <= '0';
elsif(Rx_FIFO_Full_int = '1')then
Rx_FIFO_Full_i <= '0';
elsif(RX_one_less_than_full = '1')then
Rx_FIFO_Full_i <= '1';
end if;
end if;
end process RX_FIFO_ABT_TO_FULL_P;
-------------------------------------
RX_FIFO_FULL_P: process(Bus2IP_Clk)is
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(reset2ip_reset_int = RESET_ACTIVE)then
Rx_FIFO_Full_int <= '0';
elsif(reset_RcFIFO_ptr_int = '1') or (drr_Overrun_int_to_axi_clk = '1') then -- (drr_Overrun_int = '1')then
Rx_FIFO_Full_int <= '0';
elsif(Rx_FIFO_Full_int = '1' and IP2Bus_RdAck_receive_enable = '1') then -- IP2Bus_RdAck_receive_enable = '1')then
Rx_FIFO_Full_int <= '0';
elsif(Rx_FIFO_Full_i = '1')then
Rx_FIFO_Full_int <= '1';
end if;
end if;
end process RX_FIFO_FULL_P;
---------------------------------
Rx_FIFO_Full <= Rx_FIFO_Full_int;
end generate RX_FULL_EMP_MD_0_GEN;
Rx_FIFO_Empty_int <= Rx_FIFO_Empty or Rx_FIFO_Empty_i;
-----------------------------------------------------------------------------
-- AXI Clk domain -- __________________ SPI clk domain
--Din --|AXI clk |-- Dout
--Wr_en --| |-- Rd_en
--Wr_clk --| |-- Rd_clk
--| |--
--Tx_FIFO_Full --| Tx FIFO |-- Tx_FIFO_Empty
--Tx_FIFO_almost_Full --| |-- Tx_FIFO_almost_Empty
--Tx_FIFO_occ_Reversed --| |-- Tx_FIFO_rd_ack
--Tx_FIFO_wr_ack --| |--
--| |--
--| |--
--| |--
--|__________________|--
TX_TR_EN_LEG_MD_GEN: if C_TYPE_OF_AXI4_INTERFACE = 0 generate
begin
-----
IP2Bus_WrAck_transmit_enable <= (wr_ce_reduce_ack_gen and
Bus2IP_WrCE(SPIDTR)
) and
(not Tx_FIFO_Full);-- after 100 ps;
end generate TX_TR_EN_LEG_MD_GEN;
TX_TR_EN_ENHAN_MD_GEN: if C_TYPE_OF_AXI4_INTERFACE = 1 generate
signal local_tr_en : std_logic;
begin
-----
--IP2Bus_WrAck_transmit_enable <= (wr_ce_reduce_ack_gen and
-- Bus2IP_WrCE(SPIDTR)
-- ) and
-- (not Tx_FIFO_Full)
-- when burst_tr = '0' else
-- (Bus2IP_WrCE(SPIDTR)
-- and
-- (not Tx_FIFO_Full));-- after 100 ps;
local_tr_en <= Bus2IP_WrCE(SPIDTR) and (not Tx_FIFO_Full);
--local_tr_en1 <= Bus2IP_WrCE_d1 and (not Tx_FIFO_Full);
TR_EN_P:process(wr_ce_reduce_ack_gen,
local_tr_en,
burst_tr,
WVALID)is
begin
if(burst_tr = '1') then
IP2Bus_WrAck_transmit_enable <= local_tr_en and WVALID; -- Bus2IP_WrCE_d1 and (not Tx_FIFO_Full); --local_tr_en;
else
IP2Bus_WrAck_transmit_enable <= local_tr_en and wr_ce_reduce_ack_gen;
end if;
end process TR_EN_P;
end generate TX_TR_EN_ENHAN_MD_GEN;
Data_To_TxFIFO <= Bus2IP_Data((C_S_AXI_DATA_WIDTH-C_NUM_TRANSFER_BITS) to(C_S_AXI_DATA_WIDTH-1));-- after 100 ps;
-- Transmit FIFO Logic
tx_fifo_reset <= reset2ip_reset_int or reset_TxFIFO_ptr_int;
TX_FIFO_II: entity lib_fifo_v1_0.async_fifo_fg -- entity axi_quad_spi_v3_2.async_fifo_fg -- lib_fifo_v1_0.async_fifo_fg
generic map
(
-- for first word fall through FIFO below two parameters setting is must please dont change
C_PRELOAD_LATENCY => 0 ,-- this is newly added and async_fifo_fg is referred from proc common v4_0
C_PRELOAD_REGS => 1 ,-- this is newly added and async_fifo_fg is referred from proc common v4_0
-- variables
C_ALLOW_2N_DEPTH => 1 , -- : Integer := 0; -- New paramter to leverage FIFO Gen 2**N depth
C_FAMILY => C_FAMILY , -- : String := "virtex5"; -- new for FIFO Gen
C_DATA_WIDTH => C_NUM_TRANSFER_BITS, -- : integer := 16;
C_FIFO_DEPTH => C_FIFO_DEPTH , -- : integer := 15;
C_RD_COUNT_WIDTH => C_RD_COUNT_WIDTH_INT,-- : integer := 3 ;
C_WR_COUNT_WIDTH => C_WR_COUNT_WIDTH_INT,-- : integer := 3 ;
C_HAS_ALMOST_EMPTY => 1 , -- : integer := 1 ;
C_HAS_ALMOST_FULL => 1 , -- : integer := 1 ;
C_HAS_RD_ACK => 1 , -- : integer := 0 ;
C_HAS_RD_COUNT => 1 , -- : integer := 1 ;
C_HAS_WR_ACK => 1 , -- : integer := 0 ;
C_HAS_WR_COUNT => 1 , -- : integer := 1 ;
-- constants
C_HAS_RD_ERR => 0 , -- : integer := 0 ;
C_HAS_WR_ERR => 0 , -- : integer := 0 ;
C_RD_ACK_LOW => 0 , -- : integer := 0 ;
C_RD_ERR_LOW => 0 , -- : integer := 0 ;
C_WR_ACK_LOW => 0 , -- : integer := 0 ;
C_WR_ERR_LOW => 0 , -- : integer := 0
C_ENABLE_RLOCS => 0 , -- : integer := 0 ; -- not supported in FG
C_USE_BLOCKMEM => 0 -- : integer := 1 ; -- 0 = distributed RAM, 1 = BRAM
)
port map
(
-- writing will be through AXI clock
Wr_clk => Bus2IP_Clk , -- : in std_logic := '1';
Din => Data_To_TxFIFO , -- : in std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0');
Wr_en => IP2Bus_WrAck_transmit_enable, -- : in std_logic := '1';
Wr_ack => Tx_FIFO_wr_ack , -- : out std_logic;
------
-- reading will be through SPI clock
Rd_clk => EXT_SPI_CLK , -- : in std_logic := '1';
Dout => Data_From_TxFIFO , -- : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
Rd_en => SPIXfer_done_rd_tx_en , -- : in std_logic := '0';
Rd_ack => Tx_FIFO_rd_ack_open , -- : out std_logic;
------
Full => Tx_FIFO_Full , -- : out std_logic;
Empty => Tx_FIFO_Empty , -- : out std_logic;
Almost_full => Tx_FIFO_almost_Full , -- : out std_logic;
Almost_empty => Tx_FIFO_almost_Empty , -- : out std_logic;
Rd_count => open , -- : out std_logic_vector(C_RD_COUNT_WIDTH-1 downto 0);
------
Ainit => reset_TxFIFO_ptr_int ,--Tx_FIFO_ptr_RST , -- : in std_logic := '1';
Wr_count => Tx_FIFO_occ_Reversed , -- : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0);
Rd_err => open , -- : out std_logic;
Wr_err => open -- : out std_logic
);
--tx_occ_msb <= tx_fifo_count(TX_FIFO_CNTR_WIDTH-1); -- --Tx_FIFO_occ_Reversed(C_WR_COUNT_WIDTH_INT-1);
--tx_occ_msb_1 <= (tx_fifo_count(TX_FIFO_CNTR_WIDTH-1));-- and not(or_reduce(tx_fifo_count(TX_FIFO_CNTR_WIDTH-2 downto 0))) ;--
--and not Tx_FIFO_Empty_SPISR_to_axi_clk;-- and not Tx_FIFO_Full_int; -- --Tx_FIFO_occ_Reversed(C_WR_COUNT_WIDTH_INT-1);
tx_occ_msb_11 <= (tx_fifo_count);
FIFO_16_OCC_MSB_GEN: if C_FIFO_DEPTH = 16 generate
begin
tx_occ_msb_1 <= tx_occ_msb_11(3);
end generate FIFO_16_OCC_MSB_GEN;
FIFO_256_OCC_MSB_GEN: if C_FIFO_DEPTH = 256 generate
begin
tx_occ_msb_1 <= tx_occ_msb_11(7);
end generate FIFO_256_OCC_MSB_GEN;
TX_OCC_MSB_P: process (Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(reset2ip_reset_int = RESET_ACTIVE)then
tx_occ_msb_2 <= '0';
tx_occ_msb_3 <= '0';
tx_occ_msb_4 <= '0';
else
tx_occ_msb_2 <= tx_occ_msb_1;
tx_occ_msb_3 <= tx_occ_msb_2;
tx_occ_msb_4 <= tx_occ_msb_3;
end if;
end if;
end process TX_OCC_MSB_P;
tx_occ_msb <= tx_occ_msb_4 and not Tx_FIFO_Empty_SPISR_to_axi_clk;
data_Exists_TxFIFO_int <= not (Tx_FIFO_Empty);
-----------------------------------------------------------
TX_FIFO_EMPTY_CNTR_I : entity axi_quad_spi_v3_2.counter_f
generic map(
C_NUM_BITS => TX_FIFO_CNTR_WIDTH,
C_FAMILY => "nofamily"
)
port map(
Clk => Bus2IP_Clk, -- in
Rst => '0', -- in
Load_In => ALL_0, -- in
Count_Enable => updown_cnt_en, -- in
----------------
Count_Load => reset_TxFIFO_ptr_int, -- in
----------------
Count_Down => spiXfer_done_to_axi_1, -- in
Count_Out => tx_fifo_count, -- out std_logic_vector
Carry_Out => open -- out
);
updown_cnt_en <= IP2Bus_WrAck_transmit_enable or spiXfer_done_to_axi_1;
----------------------------------------
TX_FULL_EMP_INTR_MD_12_GEN: if C_SPI_MODE /=0 generate
-----
begin
-----
Tx_FIFO_Empty_intr <= not (or_reduce(tx_fifo_count(TX_FIFO_CNTR_WIDTH-1 downto 0)))
-- and (tx_fifo_count(0))
and spiXfer_done_to_axi_1
and ( Tx_FIFO_Empty_SPISR_to_axi_clk); -- and ( Tx_FIFO_Empty);
Tx_FIFO_Full_int <= Tx_FIFO_Full;
end generate TX_FULL_EMP_INTR_MD_12_GEN;
----------------------------------------
----------------------------------------
TX_FULL_EMP_INTR_MD_0_GEN: if C_SPI_MODE =0 generate
-----
begin
-----
-- Tx_FIFO_one_less_to_Empty <= not(or_reduce(tx_fifo_count(TX_FIFO_CNTR_WIDTH-1 downto 0)))
-- --and (tx_fifo_count(0))
-- and spiXfer_done_to_axi_1;--tx_cntr_xfer_done_to_axi_1_clk; --
-- --------------------------------------------
-- TX_FIFO_ABT_TO_EMPTY_P:process(Bus2IP_Clk)is
-- begin
-- if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
-- if(reset2ip_reset_int = RESET_ACTIVE)then
-- Tx_FIFO_Empty_i <= '0';
-- elsif(Tx_FIFO_Empty_int = '1')then
-- Tx_FIFO_Empty_i <= '0';
-- elsif(Tx_FIFO_one_less_to_Empty = '1') or then
-- Tx_FIFO_Empty_i <= '1';
-- end if;
-- end if;
-- end process TX_FIFO_ABT_TO_EMPTY_P;
-- --------------------------------------
-- TX_FIFO_EMPTY_P: process(Bus2IP_Clk)is
-- begin
-- -----
-- if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
-- if(reset2ip_reset_int = RESET_ACTIVE)then
-- Tx_FIFO_Empty_int <= '0';
-- elsif(Tx_FIFO_Empty_int = '1' and spiXfer_done_to_axi_1 = '1')then
-- Tx_FIFO_Empty_int <= '0';
-- elsif(Tx_FIFO_Empty_i = '1')then
-- Tx_FIFO_Empty_int <= '1';
-- end if;
-- end if;
-- end process TX_FIFO_EMPTY_P;
--------------------------------
-- Tx_FIFO_Empty_intr <= Tx_FIFO_Empty_int and spiXfer_done_to_axi_1;
--------------------------------
TX_FIFO_CNTR_DELAY_P: process(Bus2IP_Clk)is
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(reset2ip_reset_int = RESET_ACTIVE)then
tx_fifo_count_d1 <= (others => '0');
tx_fifo_count_d2 <= (others => '0');
spiXfer_done_to_axi_d1 <= '0';
else
tx_fifo_count_d1 <= tx_fifo_count;
tx_fifo_count_d2 <= tx_fifo_count_d1;
spiXfer_done_to_axi_d1 <= spiXfer_done_to_axi_1;
end if;
end if;
end process TX_FIFO_CNTR_DELAY_P;
Tx_FIFO_Empty_intr <= (not (or_reduce(tx_fifo_count_d2(TX_FIFO_CNTR_WIDTH-1 downto 0)))
-- and (tx_fifo_count(0))
and spiXfer_done_to_axi_d1
and ( Tx_FIFO_Empty_SPISR_to_axi_clk));
TX_one_less_than_full <= and_reduce(tx_fifo_count(TX_FIFO_CNTR_WIDTH-1 downto TX_FIFO_CNTR_WIDTH-TX_FIFO_CNTR_WIDTH+1)) and
(not tx_fifo_count(0))and IP2Bus_WrAck_transmit_enable;
-------------------------------------------
TX_FIFO_ABT_TO_FULL_P:process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(reset2ip_reset_int = RESET_ACTIVE)then
Tx_FIFO_Full_i <= '0';
elsif(reset_TxFIFO_ptr_int = '1')then
Tx_FIFO_Full_i <= '0';
elsif(Tx_FIFO_Full_int = '1')then
Tx_FIFO_Full_i <= '0';
elsif(TX_one_less_than_full = '1')then
Tx_FIFO_Full_i <= '1';
end if;
end if;
end process TX_FIFO_ABT_TO_FULL_P;
----------------------------------
TX_FIFO_FULL_P: process(Bus2IP_Clk)is
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(reset2ip_reset_int = RESET_ACTIVE)then
Tx_FIFO_Full_int <= '0';
elsif(reset_TxFIFO_ptr_int = '1')then
Tx_FIFO_Full_int <= '0';
elsif(Tx_FIFO_Full_int = '1' and spiXfer_done_to_axi_1 = '1')then
Tx_FIFO_Full_int <= '0';
elsif(Tx_FIFO_Full_i = '1') then -- and spiXfer_done_to_axi_1 = '1')then
Tx_FIFO_Full_int <= '1';
end if;
end if;
end process TX_FIFO_FULL_P;
---------------------------
end generate TX_FULL_EMP_INTR_MD_0_GEN;
----------------------------------------
-------------------------------------------------------------------------------
-- I_FIFO_IF_MODULE : INSTANTIATE FIFO INTERFACE MODULE
-------------------------------------------------------------------------------
FIFO_IF_MODULE_I: entity axi_quad_spi_v3_2.qspi_fifo_ifmodule
generic map
(
C_NUM_TRANSFER_BITS => C_NUM_TRANSFER_BITS
)
port map
(
Bus2IP_Clk => Bus2IP_Clk , -- in
Soft_Reset_op => reset2ip_reset_int, -- in
-- Slave attachment ports from AXI clock
Bus2IP_RcFIFO_RdCE => Bus2IP_RdCE(SPIDRR),-- axiclk -- in
Bus2IP_TxFIFO_WrCE => Bus2IP_WrCE(SPIDTR),-- axi clk -- in
Rd_ce_reduce_ack_gen => rd_ce_reduce_ack_gen,-- axi clk -- in
-- FIFO ports
Data_From_TxFIFO => Data_From_TxFIFO ,-- spi clk -- in vec
Data_From_Rc_FIFO => Data_From_Rx_FIFO ,-- axi clk -- in vec
Tx_FIFO_Data_WithZero => transmit_Data_int ,-- spi clk -- out vec
IP2Bus_RX_FIFO_Data => IP2Bus_Receive_Reg_Data_int, -- out vec
---------------------
Rc_FIFO_Full => Rx_FIFO_Full_int, -- Rx_FIFO_Full_to_axi_clk, -- in
Rc_FIFO_Full_strobe => rc_FIFO_Full_strobe_int, -- out
---------------------
Tx_FIFO_Empty => Tx_FIFO_Empty_intr , -- Tx_FIFO_Empty_to_Axi_clk, -- sr_5_Tx_Empty_int,-- spi clk -- in
Tx_FIFO_Empty_strobe => tx_FIFO_Empty_strobe_int, -- out
---------------------
Rc_FIFO_Empty => Rx_FIFO_Empty_int, -- 13-09-2012 rx_fifo_empty_i, -- Rx_FIFO_Empty , -- Rc_FIFO_Empty_int, -- in
Receive_ip2bus_error => receive_ip2bus_error, -- out
Tx_FIFO_Full => Tx_FIFO_Full_int, -- in
Transmit_ip2bus_error => transmit_ip2bus_error, -- out
---------------------
Tx_FIFO_Occpncy_MSB => tx_occ_msb, -- in
Tx_FIFO_less_half => tx_FIFO_less_half_int, -- out
---------------------
DTR_underrun => dtr_underrun_to_axi_clk,-- dtr_underrun_int,-- in
DTR_Underrun_strobe => dtr_Underrun_strobe_int, -- out
---------------------
SPIXfer_done => spiXfer_done_to_axi_1, -- spiXfer_done_int, -- in
rready => rready
-- DRR_Overrun_reg => drr_Overrun_int -- out
);
-------------------------------------------------------------------------------
-- TX_OCCUPANCY_I : INSTANTIATE TRANSMIT OCCUPANCY REGISTER
-------------------------------------------------------------------------------
TX_OCCUPANCY_I: entity axi_quad_spi_v3_2.qspi_occupancy_reg
generic map
(
C_OCCUPANCY_NUM_BITS => C_OCCUPANCY_NUM_BITS
)
port map
(
--Slave attachment ports
Bus2IP_OCC_REG_RdCE => Bus2IP_RdCE(SPITFOR), -- in
--FIFO port
IP2Reg_OCC_Data => tx_fifo_count, -- tx_FIFO_occ_Reversed, -- in vec
IP2Bus_OCC_REG_Data => IP2Bus_Tx_FIFO_OCC_Reg_Data_int -- out vec
);
-------------------------------------------------------------------------------
-- RX_OCCUPANCY_I : INSTANTIATE RECEIVE OCCUPANCY REGISTER
-------------------------------------------------------------------------------
RX_OCCUPANCY_I: entity axi_quad_spi_v3_2.qspi_occupancy_reg
generic map
(
C_OCCUPANCY_NUM_BITS => C_OCCUPANCY_NUM_BITS--,
)
port map
(
--Slave attachment ports
Bus2IP_OCC_REG_RdCE => Bus2IP_RdCE(SPIRFOR), -- in
--FIFO port
IP2Reg_OCC_Data => rx_fifo_count, --rx_FIFO_occ_Reversed, -- in vec
IP2Bus_OCC_REG_Data => IP2Bus_Rx_FIFO_OCC_Reg_Data_int -- out vec
);
end generate FIFO_EXISTS;
--------------------------------------------
-- LOGIC_FOR_MD_0_GEN: in stantiate the original SPI module when the core is configured in Standard SPI mode.
------------------------------
LOGIC_FOR_MD_0_GEN: if C_SPI_MODE = 0 generate
---------------------------
signal SCK_O_int : std_logic;
signal MISO_I_int: std_logic;
-----
begin
-----
-- un used IO2 and IO3 O/P ports are tied to 0 and T ports are tied to '1'
IO2_O <= '0';
IO2_T <= '1';
IO3_O <= '0';
IO3_T <= '1';
SPISR_0_CMD_Error_int <= '0'; -- no command error when C_SPI_MODE= 0
-------------------------------------------------------
SCK_MISO_NO_STARTUP_USED: if C_USE_STARTUP = 0 generate
-----
begin
-----
SCK_O <= SCK_O_int; -- output from the core
MISO_I_int <= IO1_I; -- input to the core
end generate SCK_MISO_NO_STARTUP_USED;
-------------------------------------------------------
-------------------------------------------------------
SCK_MISO_STARTUP_USED: if C_USE_STARTUP = 1 generate
-----
begin
-----
QSPI_STARTUP_BLOCK_I: entity axi_quad_spi_v3_2.qspi_startup_block
---------------------
generic map
(
C_SUB_FAMILY => C_SUB_FAMILY , -- support for V6/V7/K7/A7 families only
-----------------
C_USE_STARTUP => C_USE_STARTUP,
-----------------
C_SPI_MODE => C_SPI_MODE
-----------------
)
port map
(
SCK_O => SCK_O_int, -- : in std_logic; -- input from the qspi_mode_0_module
IO1_I_startup => IO1_I, -- : in std_logic; -- input from the top level port list
IO1_Int => MISO_I_int,-- : out std_logic
Bus2IP_Clk => Bus2IP_Clk,
reset2ip_reset => reset2ip_reset_int,
CFGCLK => cfgclk, -- FGCLK , -- 1-bit output: Configuration main clock output
CFGMCLK => cfgmclk, -- FGMCLK , -- 1-bit output: Configuration internal oscillator clock output
EOS => eos, -- OS , -- 1-bit output: Active high output signal indicating the End Of Startup.
PREQ => preq, -- REQ , -- 1-bit output: PROGRAM request to fabric output
DI => di -- output
);
--------------------
end generate SCK_MISO_STARTUP_USED;
-------------------------------------------------------
----------------------------------------------------------------------------
-- SPI_MODULE_I : INSTANTIATE SPI MODULE
----------------------------------------------------------------------------
SPI_MODULE_I: entity axi_quad_spi_v3_2.qspi_mode_0_module
-------------
generic map
(
C_SCK_RATIO => C_SCK_RATIO ,
C_USE_STARTUP => C_USE_STARTUP ,
C_SPICR_REG_WIDTH => C_SPICR_REG_WIDTH ,
C_NUM_SS_BITS => C_NUM_SS_BITS ,
C_NUM_TRANSFER_BITS => C_NUM_TRANSFER_BITS ,
C_SUB_FAMILY => C_SUB_FAMILY ,
C_FIFO_EXIST => C_FIFO_EXIST
)
port map
(
Bus2IP_Clk => EXT_SPI_CLK, -- in
Soft_Reset_op => Rst_to_spi_int, -- in
------------------------
SPICR_0_LOOP => SPICR_0_LOOP_to_spi_clk,--_int,
SPICR_1_SPE => SPICR_1_SPE_to_spi_clk,--_int,
SPICR_2_MASTER_N_SLV => SPICR_2_MST_N_SLV_to_spi_clk,--_int,
SPICR_3_CPOL => SPICR_3_CPOL_to_spi_clk,--_int,
SPICR_4_CPHA => SPICR_4_CPHA_to_spi_clk,--_int,
SPICR_5_TXFIFO_RST => SPICR_5_TXFIFO_to_spi_clk, -- SPICR_5_TXFIFO_RST_to_spi_clk,--_int,
SPICR_6_RXFIFO_RST => SPICR_6_RXFIFO_RST_to_spi_clk,--_int,
SPICR_7_SS => SPICR_7_SS_to_spi_clk,--_int,
SPICR_8_TR_INHIBIT => SPICR_8_TR_INHIBIT_to_spi_clk,--_int,
SPICR_9_LSB => SPICR_9_LSB_to_spi_clk,--_int,
------------------------
SR_3_MODF => SR_3_modf_to_spi_clk, -- in
SR_5_Tx_Empty => Tx_FIFO_Empty, -- sr_5_Tx_Empty_int, -- in
Slave_MODF_strobe => slave_MODF_strobe_int, -- out
MODF_strobe => modf_strobe_int, -- out
Slave_Select_Reg => register_Data_slvsel_int, -- already updated -- in vec
Transmit_Data => Data_From_TxFIFO, -- transmit_Data_int, -- in vec
Receive_Data => Data_To_Rx_FIFO, -- receive_Data_int, -- out vec
SPIXfer_done => spiXfer_done_int, -- out
-- SPIXfer_done_Rx_Wr_en=> SPIXfer_done_Rx_Wr_en,
DTR_underrun => dtr_underrun_int, -- out
SPIXfer_done_rd_tx_en=> SPIXfer_done_rd_tx_en,
--SPI Ports
SCK_I => SCK_I, -- in
SCK_O_reg => SCK_O_int, -- out
SCK_T => SCK_T, -- out
MISO_I => MISO_I_int, -- IO1_I, -- MISO_I, -- in
MISO_O => IO1_O, -- MISO_O, -- out
MISO_T => IO1_T, -- MISO_T, -- out
MOSI_I => IO0_I, -- MOSI_I, -- in
MOSI_O => IO0_O, -- MOSI_O, -- out
MOSI_T => IO0_T, -- MOSI_T, -- out
SPISEL => SPISEL, -- in
SS_I => SS_I, -- in
SS_O => SS_O, -- out
SS_T => SS_T, -- out
SPISEL_pulse_op => spisel_pulse_o_int , -- out std_logic;
SPISEL_d1_reg => spisel_d1_reg , -- out std_logic;
control_bit_7_8 => SPICR_bits_7_8_to_spi_clk, -- in vec
Mst_N_Slv_mode => Mst_N_Slv_mode ,
Rx_FIFO_Full => Rx_FIFO_Full_to_spi_clk,
DRR_Overrun_reg => drr_Overrun_int, -- out
reset_RcFIFO_ptr_to_spi => reset_RcFIFO_ptr_to_spi_clk,
tx_cntr_xfer_done => tx_cntr_xfer_done
);
-------------
end generate LOGIC_FOR_MD_0_GEN;
----------------------------------------
-- LOGIC_FOR_MD_12_GEN: to generate the functionality for mode 1 and 2.
------------------------------
LOGIC_FOR_MD_12_GEN: if C_SPI_MODE /= 0 generate
---------------------------
signal SCK_O_int : std_logic;
signal MISO_I_int: std_logic;
signal Data_Dir_int : std_logic;
signal Data_Mode_1_int : std_logic;
signal Data_Mode_0_int : std_logic;
signal Data_Phase_int : std_logic;
signal Addr_Mode_1_int : std_logic;
signal Addr_Mode_0_int : std_logic;
signal Addr_Bit_int : std_logic;
signal Addr_Phase_int : std_logic;
signal CMD_Mode_1_int : std_logic;
signal CMD_Mode_0_int : std_logic;
signal CMD_Error_int : std_logic;
signal CMD_decoded_int : std_logic;
signal Dummy_Bits_int : std_logic_vector(3 downto 0);
signal IO2_O_int : std_logic;
signal IO2_T_int : std_logic;
signal IO3_O_int : std_logic;
signal IO3_T_int : std_logic;
signal IO2_I_int : std_logic;
signal IO3_I_int : std_logic;
-----
begin
-----
LOGIC_FOR_C_SPI_MODE_1_GEN: if C_SPI_MODE = 1 generate
-------
begin
-------
IO2_O <= '0'; -- not used in the logic
IO3_O <= '0'; -- not used in the logic
IO2_T <= '1'; -- disable the tri-state buffers
IO3_T <= '1'; -- disable the tri-state buffers
IO2_I_int <= '0';-- assign default value as this bit is not used in thid mode
IO3_I_int <= '0';-- assign default value as this bit is not used in thid mode
end generate LOGIC_FOR_C_SPI_MODE_1_GEN;
---------------------------------------
LOGIC_FOR_C_SPI_MODE_2_GEN: if C_SPI_MODE = 2 generate
-------
begin
-------
IO2_I_int <= IO2_I; -- assign this bit from the top level port
IO2_O <= IO2_O_int;
IO2_T <= IO2_T_int;
IO3_I_int <= IO3_I; -- assign this bit from the top level port
IO3_O <= IO3_O_int;
IO3_T <= IO3_T_int;
end generate LOGIC_FOR_C_SPI_MODE_2_GEN;
---------------------------------------
SPISR_0_CMD_Error_int <= CMD_Error_int;
dtr_underrun_int <= '0'; -- SPI MODE 1 & 2 are master modes, so DTR under run wont be present
slave_MODF_strobe_int <= '0'; -- SPI MODE 1 & 2 are master modes, so the slave mode fault error wont appear
Mst_N_Slv_mode <= '1';
-------------------------------------------------------
-- SCK_O <= SCK_O_int; -- output from the core
-- MISO_I_int <= IO1_I; -- input to the core
-- *
-------------------------------------------------------
SCK_MISO_NO_STARTUP_USED: if C_USE_STARTUP = 0 generate
-----
begin
-----
SCK_O <= SCK_O_int; -- output from the core
MISO_I_int <= IO1_I; -- input to the core
end generate SCK_MISO_NO_STARTUP_USED;
-------------------------------------------------------
-------------------------------------------------------
SCK_MISO_STARTUP_USED: if C_USE_STARTUP = 1 generate
-----
begin
-----
QSPI_STARTUP_BLOCK_I: entity axi_quad_spi_v3_2.qspi_startup_block
---------------------
generic map
(
C_SUB_FAMILY => C_SUB_FAMILY , -- support for V6/V7/K7/A7 families only
-----------------
C_USE_STARTUP => C_USE_STARTUP,
-----------------
C_SPI_MODE => C_SPI_MODE
-----------------
)
port map
(
SCK_O => SCK_O_int, -- : in std_logic; -- input from the qspi_mode_0_module
IO1_I_startup => IO1_I, -- : in std_logic; -- input from the top level port list
IO1_Int => MISO_I_int,-- : out std_logic
Bus2IP_Clk => Bus2IP_Clk,
reset2ip_reset => reset2ip_reset_int,
CFGCLK => cfgclk, -- FGCLK , -- 1-bit output: Configuration main clock output
CFGMCLK => cfgmclk, -- FGMCLK , -- 1-bit output: Configuration internal oscillator clock output
EOS => eos, -- OS , -- 1-bit output: Active high output signal indicating the End Of Startup.
PREQ => preq, -- REQ , -- 1-bit output: PROGRAM request to fabric output
DI => di -- output
);
--------------------
end generate SCK_MISO_STARTUP_USED;
-------------------------------------------------------
-- *
-- Add instance for Look up table logic
SPI_MODE_1_LUT_LOGIC_I: entity axi_quad_spi_v3_2.qspi_look_up_logic
-------------
generic map
(
C_FAMILY => C_FAMILY ,
C_SPI_MODE => C_SPI_MODE ,
C_SPI_MEMORY => C_SPI_MEMORY ,
C_NUM_TRANSFER_BITS => C_NUM_TRANSFER_BITS
)
port map
(
EXT_SPI_CLK => EXT_SPI_CLK , -- : in std_logic;
Rst_to_spi => Rst_to_spi_int , -- : in std_logic;
TXFIFO_RST => reset_TxFIFO_ptr_int_to_spi, -- : in std_logic;
-------------------- --
DTR_FIFO_Data_Exists=> data_Exists_TxFIFO_int, -- : in std_logic;
Data_From_TxFIFO => Data_From_TxFIFO , -- : in std_logic_vector
-- (0 to (C_NUM_TRANSFER_BITS-1))
pr_state_idle => pr_state_idle_int , --
-------------------- --
Data_Dir => Data_Dir_int , -- : out std_logic;
Data_Mode_1 => Data_Mode_1_int , -- : out std_logic;
Data_Mode_0 => Data_Mode_0_int , -- : out std_logic;
Data_Phase => Data_Phase_int , -- : out std_logic;
-------------------- --
Quad_Phase => Quad_Phase_int ,
-------------------- --
Addr_Mode_1 => Addr_Mode_1_int , -- : out std_logic;
Addr_Mode_0 => Addr_Mode_0_int , -- : out std_logic;
Addr_Bit => Addr_Bit_int , -- : out std_logic;
Addr_Phase => Addr_Phase_int , -- : out std_logic;
-------------------- --
CMD_Mode_1 => CMD_Mode_1_int , -- : out std_logic;
CMD_Mode_0 => CMD_Mode_0_int , -- : out std_logic;
CMD_Error => CMD_Error_int , -- : out std_logic;
-------------------- -- -
CMD_decoded => CMD_decoded_int -- : out std_logic
);
---------
SPI_MODE_CONTROL_LOGIC_I: entity axi_quad_spi_v3_2.qspi_mode_control_logic
-------------
generic map
(
C_SCK_RATIO => C_SCK_RATIO ,
C_NUM_TRANSFER_BITS => C_NUM_TRANSFER_BITS ,
C_SPI_MODE => C_SPI_MODE ,
C_USE_STARTUP => C_USE_STARTUP ,
C_NUM_SS_BITS => C_NUM_SS_BITS ,
C_SPI_MEMORY => C_SPI_MEMORY ,
C_SUB_FAMILY => C_SUB_FAMILY
)
port map
(
Bus2IP_Clk => EXT_SPI_CLK , -- Bus2IP_Clk , -- in std_logic;
Soft_Reset_op => Rst_to_spi_int , -- in std_logic;
-------------------- , --
DTR_FIFO_Data_Exists => data_Exists_TxFIFO_int , -- in std_logic;
Slave_Select_Reg => register_Data_slvsel_int , -- already updated -- in std_logic_vector(0 to (C_NUM_SS_BITS-1));
Transmit_Data => Data_From_TxFIFO,--transmit_Data_int , -- already updated -- in std_logic_vector(0 to (C_NUM_TRANSFER_BITS
Receive_Data => Data_To_Rx_FIFO , -- out std_logic_vector(0 to (C_NUM_TRANSFER_BITS
--Data_To_Rx_FIFO_1 => Data_To_Rx_FIFO_1,
SPIXfer_done => spiXfer_done_int , -- already updated -- out std_logic;
SPIXfer_done_Rx_Wr_en=> SPIXfer_done_Rx_Wr_en,
MODF_strobe => modf_strobe_int , -- already updated
SPIXfer_done_rd_tx_en=> SPIXfer_done_rd_tx_en,
--------------------- --
SR_3_MODF => SR_3_modf_to_spi_clk , -- in std_logic;
SR_5_Tx_Empty => Tx_FIFO_Empty , -- sr_5_Tx_Empty_int -- in std_logic;
--SR_6_Rx_Full => Rx_FIFO_Full , -- in
pr_state_idle => pr_state_idle_int , --
--------------------- -- from control register
SPICR_0_LOOP => SPICR_0_LOOP_to_spi_clk ,--SPICR_0_LOOP_int , -- in std_logic;
SPICR_1_SPE => SPICR_1_SPE_to_spi_clk ,--_int , -- in std_logic;
SPICR_2_MASTER_N_SLV => SPICR_2_MST_N_SLV_to_spi_clk,--_int , -- in std_logic;
SPICR_3_CPOL => SPICR_3_CPOL_to_spi_clk ,--_int , -- in std_logic;
SPICR_4_CPHA => SPICR_4_CPHA_to_spi_clk ,--_int , -- in std_logic;
SPICR_5_TXFIFO_RST => SPICR_5_TXFIFO_RST_to_spi_clk,--_int , -- in std_logic;
SPICR_6_RXFIFO_RST => SPICR_6_RXFIFO_RST_to_spi_clk,--_int , -- in std_logic;
SPICR_7_SS => SPICR_7_SS_to_spi_clk ,--_int , -- in std_logic;
SPICR_8_TR_INHIBIT => SPICR_8_TR_INHIBIT_to_spi_clk,--_int , -- in std_logic;
SPICR_9_LSB => SPICR_9_LSB_to_spi_clk ,--_int , -- in std_logic;
--------------------- --
--------------------- -- from look up table
Data_Dir => Data_Dir_int , -- in std_logic;
Data_Mode_1 => Data_Mode_1_int , -- in std_logic;
Data_Mode_0 => Data_Mode_0_int , -- in std_logic;
Data_Phase => Data_Phase_int ,
---------------------
--Dummy_Bits => Dummy_Bits_int , -- in std_logic_vector(3 downto 0);
Quad_Phase => Quad_Phase_int ,
--------------------- -- in std_logic;
Addr_Mode_1 => Addr_Mode_1_int , -- in std_logic;
Addr_Mode_0 => Addr_Mode_0_int , -- in std_logic;
Addr_Bit => Addr_Bit_int , -- in std_logic;
Addr_Phase => Addr_Phase_int , -- in std_logic;
---------------------
CMD_Mode_1 => CMD_Mode_1_int , -- in std_logic;
CMD_Mode_0 => CMD_Mode_0_int , -- in std_logic;
CMD_Error => CMD_Error_int , -- in std_logic;
--------------------- --
CMD_decoded => CMD_decoded_int , -- in std_logic;
--SPI Interface --
SCK_I => SCK_I, -- in std_logic;
SCK_O_reg => SCK_O_int, -- out std_logic;
SCK_T => SCK_T, -- out std_logic;
--
IO0_I => IO0_I, -- MOSI_I, -- in std_logic; -- MISO
IO0_O => IO0_O, -- MOSI_O, -- out std_logic;
IO0_T => IO0_T, -- MOSI_T, -- out std_logic;
IO1_I => MISO_I_int, -- IO1_I, -- MISO_I, -- in std_logic;
IO1_O => IO1_O, -- MISO_O, -- out std_logic; -- MOSI
IO1_T => IO1_T, -- MISO_T, -- out std_logic;
--
IO2_I => IO2_I_int, -- -- in std_logic;
IO2_O => IO2_O_int, -- -- out std_logic;
IO2_T => IO2_T_int, -- -- out std_logic;
--
IO3_I => IO3_I_int, -- -- in std_logic;
IO3_O => IO3_O_int, -- -- out std_logic;
IO3_T => IO3_T_int, -- -- out std_logic;
--
SPISEL => SPISEL, -- in std_logic;
--
SS_I => SS_I, -- in std_logic_vector(0 to (C_NUM_SS_BITS-1));
SS_O => SS_O, -- out std_logic_vector(0 to (C_NUM_SS_BITS-1));
SS_T => SS_T, -- out std_logic;
--
SPISEL_pulse_op => spisel_pulse_o_int , -- out std_logic;
SPISEL_d1_reg => spisel_d1_reg , -- out std_logic;
Control_bit_7_8 => SPICR_bits_7_8_to_spi_clk , -- in std_logic_vector(0 to 1) --(7 to 8)
Rx_FIFO_Full => Rx_FIFO_Full,
DRR_Overrun_reg => drr_Overrun_int,
reset_RcFIFO_ptr_to_spi => reset_RcFIFO_ptr_to_spi_clk
);
-------------
end generate LOGIC_FOR_MD_12_GEN;
------------------------------------------
--------------------------------------------------------------------------------
CONTROL_REG_I: entity axi_quad_spi_v3_2.qspi_cntrl_reg
generic map
(
--------------------------
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
--------------------------
-- Number of bits in regis
C_SPI_NUM_BITS_REG => C_SPI_NUM_BITS_REG,
--------------------------
C_SPICR_REG_WIDTH => C_SPICR_REG_WIDTH,
--------------------------
C_SPI_MODE => C_SPI_MODE
--------------------------
)
port map
( -- in
Bus2IP_Clk => Bus2IP_Clk, -- in
Soft_Reset_op => reset2ip_reset_int,
---------------------------
Wr_ce_reduce_ack_gen => Wr_ce_reduce_ack_gen, -- in
Bus2IP_SPICR_WrCE => Bus2IP_WrCE(SPICR), -- in
Bus2IP_SPICR_RdCE => Bus2IP_RdCE(SPICR), -- in
Bus2IP_SPICR_data => Bus2IP_Data, -- in vec
---------------------------
SPICR_0_LOOP => SPICR_0_LOOP_frm_axi_clk, -- out
SPICR_1_SPE => SPICR_1_SPE_frm_axi_clk, -- out
SPICR_2_MASTER_N_SLV => SPICR_2_MST_N_SLV_frm_axi_clk, -- out
SPICR_3_CPOL => SPICR_3_CPOL_frm_axi_clk, -- out
SPICR_4_CPHA => SPICR_4_CPHA_frm_axi_clk, -- out
SPICR_5_TXFIFO_RST => SPICR_5_TXFIFO_RST_frm_axi_clk, -- out
SPICR_6_RXFIFO_RST => SPICR_6_RXFIFO_RST_frm_axi_clk, -- out
SPICR_7_SS => SPICR_7_SS_frm_axi_clk, -- out
SPICR_8_TR_INHIBIT => SPICR_8_TR_INHIBIT_frm_axi_clk, -- out
SPICR_9_LSB => SPICR_9_LSB_frm_axi_clk, -- out
-- to Status Register
SPISR_1_LOOP_Back_Error => SPISR_1_LOOP_Back_Error_int, -- out
SPISR_2_MSB_Error => SPISR_2_MSB_Error_int, -- out
SPISR_3_Slave_Mode_Error => SPISR_3_Slave_Mode_Error_int, -- out
SPISR_4_CPOL_CPHA_Error => SPISR_4_CPOL_CPHA_Error_int, -- out
---------------------------
IP2Bus_SPICR_Data => IP2Bus_SPICR_Data_int, -- out vec
---------------------------
Control_bit_7_8 => SPICR_bits_7_8_frm_axi_clk -- out vec
---------------------------
);
-------------------------------------------------------------------------------
-- STATUS_REG_I : INSTANTIATE STATUS REGISTER
-------------------------------------------------------------------------------
STATUS_REG_MODE_0_GEN: if C_SPI_MODE = 0 generate
begin
STATUS_SLAVE_SEL_REG_I: entity axi_quad_spi_v3_2.qspi_status_slave_sel_reg
generic map(
C_SPI_NUM_BITS_REG => C_SPI_NUM_BITS_REG ,
------------------------ ------------------------
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
------------------------ ------------------------
C_NUM_SS_BITS => C_NUM_SS_BITS ,
------------------------ ------------------------
C_SPISR_REG_WIDTH => C_SPISR_REG_WIDTH
)
port map(
Bus2IP_Clk => Bus2IP_Clk , -- in
Soft_Reset_op => reset2ip_reset_int , -- in
-- I/P from control regis
SPISR_0_Command_Error => '0' , -- SPISR_0_CMD_Error_int , -- in-- should come from look up table
SPISR_1_LOOP_Back_Error => SPISR_1_LOOP_Back_Error_int , -- in
SPISR_2_MSB_Error => SPISR_2_MSB_Error_int , -- in
SPISR_3_Slave_Mode_Error => SPISR_3_Slave_Mode_Error_int , -- in
SPISR_4_CPOL_CPHA_Error => SPISR_4_CPOL_CPHA_Error_int , -- in
-- I/P from other modules
SPISR_Ext_SPISEL_slave => spisel_d1_reg_to_axi_clk , -- in
SPISR_7_Tx_Full => Tx_FIFO_Full_int , -- in
SPISR_8_Tx_Empty => Tx_FIFO_Empty_SPISR_to_axi_clk, -- Tx_FIFO_Empty_to_Axi_clk , -- in
SPISR_9_Rx_Full => Rx_FIFO_Full_int, -- Rx_FIFO_Full_to_axi_clk , -- in
SPISR_10_Rx_Empty => Rx_FIFO_Empty_int , -- in
-- Slave attachment ports
ModeFault_Strobe => modf_strobe_to_axi_clk , -- in
Rd_ce_reduce_ack_gen => rd_ce_reduce_ack_gen , -- in
Bus2IP_SPISR_RdCE => Bus2IP_RdCE(SPISR) , -- in
IP2Bus_SPISR_Data => IP2Bus_SPISR_Data_int , -- out vec
SR_3_modf => SR_3_modf_int , -- out
-- Slave Select Register
Bus2IP_SPISSR_WrCE => Bus2IP_WrCE(SPISSR) , -- in
Wr_ce_reduce_ack_gen => Wr_ce_reduce_ack_gen , -- in
Bus2IP_SPISSR_RdCE => Bus2IP_RdCE(SPISSR) , -- in
Bus2IP_SPISSR_Data => Bus2IP_Data , -- in vec
IP2Bus_SPISSR_Data => IP2Bus_SPISSR_Data_int , -- out vec
SPISSR_Data_reg_op => SPISSR_frm_axi_clk -- out vec
);
end generate STATUS_REG_MODE_0_GEN;
STATUS_REG_MODE_12_GEN: if C_SPI_MODE /= 0 generate
begin
STATUS_SLAVE_SEL_REG_I: entity axi_quad_spi_v3_2.qspi_status_slave_sel_reg
generic map(
C_SPI_NUM_BITS_REG => C_SPI_NUM_BITS_REG ,
------------------------ ------------------------
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
------------------------ ------------------------
C_NUM_SS_BITS => C_NUM_SS_BITS ,
------------------------ ------------------------
C_SPISR_REG_WIDTH => C_SPISR_REG_WIDTH
)
port map(
Bus2IP_Clk => Bus2IP_Clk , -- in
Soft_Reset_op => reset2ip_reset_int , -- in
-- I/P from control regis
SPISR_0_Command_Error => SPISR_0_CMD_Error_to_axi_clk , -- SPISR_0_CMD_Error_int , -- in-- should come from look up table
SPISR_1_LOOP_Back_Error => SPISR_1_LOOP_Back_Error_int , -- in
SPISR_2_MSB_Error => SPISR_2_MSB_Error_int , -- in
SPISR_3_Slave_Mode_Error => SPISR_3_Slave_Mode_Error_int , -- in
SPISR_4_CPOL_CPHA_Error => SPISR_4_CPOL_CPHA_Error_int , -- in
-- I/P from other modules
SPISR_Ext_SPISEL_slave => spisel_d1_reg_to_axi_clk , -- in
SPISR_7_Tx_Full => Tx_FIFO_Full_int , -- in
SPISR_8_Tx_Empty => Tx_FIFO_Empty_SPISR_to_axi_clk, -- Tx_FIFO_Empty_to_Axi_clk , -- in
SPISR_9_Rx_Full => Rx_FIFO_Full_int, -- Rx_FIFO_Full_to_axi_clk , -- in
SPISR_10_Rx_Empty => Rx_FIFO_Empty_int , -- in
-- Slave attachment ports
ModeFault_Strobe => modf_strobe_to_axi_clk , -- in
Rd_ce_reduce_ack_gen => rd_ce_reduce_ack_gen , -- in
Bus2IP_SPISR_RdCE => Bus2IP_RdCE(SPISR) , -- in
IP2Bus_SPISR_Data => IP2Bus_SPISR_Data_int , -- out vec
SR_3_modf => SR_3_modf_int , -- out
-- Slave Select Register
Bus2IP_SPISSR_WrCE => Bus2IP_WrCE(SPISSR) , -- in
Wr_ce_reduce_ack_gen => Wr_ce_reduce_ack_gen , -- in
Bus2IP_SPISSR_RdCE => Bus2IP_RdCE(SPISSR) , -- in
Bus2IP_SPISSR_Data => Bus2IP_Data , -- in vec
IP2Bus_SPISSR_Data => IP2Bus_SPISSR_Data_int , -- out vec
SPISSR_Data_reg_op => SPISSR_frm_axi_clk -- out vec
);
end generate STATUS_REG_MODE_12_GEN;
-------------------------------------------------------------------------------
-- SOFT_RESET_I : INSTANTIATE SOFT RESET
-------------------------------------------------------------------------------
SOFT_RESET_I: entity axi_quad_spi_v3_2.soft_reset
generic map
(
C_SIPIF_DWIDTH => C_S_AXI_DATA_WIDTH,
-- Width of triggered reset in Bus Clocks
C_RESET_WIDTH => 16
)
port map
(
-- Inputs From the PLBv46 Slave Single Bus
Bus2IP_Clk => Bus2IP_Clk, -- in
Bus2IP_Reset => Bus2IP_Reset, -- in
Bus2IP_WrCE => Bus2IP_WrCE(SWRESET), -- in
Bus2IP_Data => Bus2IP_Data, -- in
Bus2IP_BE => Bus2IP_BE, -- in
-- Final Device Reset Output
Reset2IP_Reset => reset2ip_reset_int, -- out
-- Status Reply Outputs to the Bus
Reset2Bus_WrAck => rst_ip2bus_wrack, -- out
Reset2Bus_Error => rst_ip2bus_error, -- out
Reset2Bus_ToutSup => open -- out
);
-------------------------------------------------------------------------------
-- INTERRUPT_CONTROL_I : INSTANTIATE INTERRUPT CONTROLLER
-------------------------------------------------------------------------------
bus2ip_intr_rdce <= "0000000" &
Bus2IP_RdCE(7) &
Bus2IP_RdCE(8) &
'0' &
Bus2IP_RdCE(10)&
"00000";
bus2ip_intr_wrce <= "0000000" &
Bus2IP_WrCE(7) &
Bus2IP_WrCE(8) &
'0' &
Bus2IP_WrCE(10)&
"00000";
------------------------------------------------------------------------------
intr_controller_rd_ce_or_reduce <= or_reduce(Bus2IP_RdCE(0 to 6)) or
Bus2IP_RdCE(9) or
or_reduce(Bus2IP_RdCE(11 to 15));
------------------------------------------------------------------------------
I_READ_ACK_INTR_HOLES: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
ip2Bus_RdAck_intr_reg_hole <= '0';
ip2Bus_RdAck_intr_reg_hole_d1 <= '0';
else
ip2Bus_RdAck_intr_reg_hole_d1 <= intr_controller_rd_ce_or_reduce;
ip2Bus_RdAck_intr_reg_hole <= intr_controller_rd_ce_or_reduce and
(not ip2Bus_RdAck_intr_reg_hole_d1);
end if;
end if;
end process I_READ_ACK_INTR_HOLES;
------------------------------------------------------------------------------
intr_controller_wr_ce_or_reduce <= or_reduce(Bus2IP_WrCE(0 to 6)) or
Bus2IP_WrCE(9) or
or_reduce(Bus2IP_WrCE(11 to 15));
------------------------------------------------------------------------------
I_WRITE_ACK_INTR_HOLES: process(Bus2IP_Clk) is
-----
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
ip2Bus_WrAck_intr_reg_hole <= '0';
ip2Bus_WrAck_intr_reg_hole_d1 <= '0';
else
ip2Bus_WrAck_intr_reg_hole_d1 <= intr_controller_wr_ce_or_reduce;
ip2Bus_WrAck_intr_reg_hole <= intr_controller_wr_ce_or_reduce and
(not ip2Bus_WrAck_intr_reg_hole_d1);
end if;
end if;
end process I_WRITE_ACK_INTR_HOLES;
------------------------------------------------------------------------------
INTERRUPT_CONTROL_I: entity interrupt_control_v3_1.interrupt_control
generic map
(
C_NUM_CE => 16,
C_NUM_IPIF_IRPT_SRC => 1, -- Set to 1 to avoid null array
C_IP_INTR_MODE_ARRAY => C_IP_INTR_MODE_ARRAY,
-- Specifies device Priority Encoder function
C_INCLUDE_DEV_PENCODER => false,
-- Specifies device ISC hierarchy
C_INCLUDE_DEV_ISC => false,
C_IPIF_DWIDTH => C_S_AXI_DATA_WIDTH
)
port map
(
Bus2IP_Clk => Bus2IP_Clk, -- in
Bus2IP_Reset => reset2ip_reset_int, -- in
Bus2IP_Data => bus2IP_Data_for_interrupt_core, -- in vec
Bus2IP_BE => Bus2IP_BE, -- in vec
Interrupt_RdCE => bus2ip_intr_rdce, -- in vec
Interrupt_WrCE => bus2ip_intr_wrce, -- in vec
IPIF_Reg_Interrupts => "00", -- Tie off the unused reg intrs
IPIF_Lvl_Interrupts => "0", -- Tie off the dummy lvl intr
IP2Bus_IntrEvent => ip2Bus_IntrEvent_int, -- in
Intr2Bus_DevIntr => IP2INTC_Irpt, -- out
Intr2Bus_DBus => intr_ip2bus_data, -- out vec
Intr2Bus_WrAck => intr_ip2bus_wrack, -- out
Intr2Bus_RdAck => intr_ip2bus_rdack, -- out
Intr2Bus_Error => intr_ip2bus_error, -- out
Intr2Bus_Retry => open,
Intr2Bus_ToutSup => open
);
--------------------------------------------------------------------------------
end imp;
--------------------------------------------------------------------------------
| gpl-2.0 | 39b71e945e78c4420a1eca6361ec0c34 | 0.44471 | 3.730176 | false | false | false | false |
Hyperion302/omega-cpu | Core/Constants.vhdl | 1 | 6,133 | -- This file is part of the Omega CPU Core
-- Copyright 2015 - 2016 Joseph Shetaye
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as
-- published by the Free Software Foundation, either version 3 of the
-- License, or (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
package Constants is
subtype Byte is std_logic_vector (7 downto 0);
-- FIXME: Change "16" to "4095" when using GHDL simulator.
type MemoryArray is array(0 to 110) of Byte;
subtype Word is std_logic_vector (31 downto 0);
subtype Opcode is std_logic_vector (2 downto 0);
subtype Operator is std_logic_vector (2 downto 0);
subtype RegisterReference is std_logic_vector (4 downto 0);
subtype ImmediateValue is std_logic_vector (15 downto 0);
subtype ImmediateAddress is std_logic_vector (25 downto 0);
subtype ImmediateConditionalAddress is std_logic_vector(20 downto 0);
function GetOpcode (
W : Word)
return std_logic_vector; --Opcode
function GetOperator (
W : Word)
return std_logic_vector; --Operator
function GetRegisterReferenceA (
W : Word)
return std_logic_vector; --RegisterReference
function GetRegisterReferenceB (
W : Word)
return std_logic_vector; --RegisterReference
function GetRegisterReferenceC (
W : Word)
return std_logic_vector; --RegisterReference
function GetRegisterReferenceD (
W : Word)
return std_logic_vector; --RegisterReference
function GetImmediateValue (
W : Word)
return std_logic_vector; --ImmediateValue
function GetImmediateAddress (
W : Word)
return std_logic_vector; --ImmediateAddress
function GetImmediateConditionalAddress
( W : Word)
return std_logic_vector; --ImmediateConditionalAddress
function SignExtendImmediateValue (
VALUE : ImmediateValue)
return std_logic_vector; --Word
function SignExtendImmediateAddress (
ADDR : ImmediateAddress)
return std_logic_vector; --Word
function SignExtendImmediateConditionalAddress (
ADDR : ImmediateConditionalAddress)
return std_logic_vector; --Word
function GetIRQ (
IRQ : std_logic_vector(23 downto 0))
return integer;
constant OpcodeLogical : opcode := "000";
constant OpcodeArithmetic : opcode := "001";
constant OpcodeShift : opcode := "010";
constant OpcodeRelational : opcode := "011";
constant OpcodeMemory : opcode := "100";
constant OpcodePort : opcode := "101";
constant OpcodeBranch : opcode := "110";
constant RegisterMode : std_logic := '0';
constant ImmediateMode : std_logic := '1';
constant LoadByteUnsigned : Operator := "000";
constant LoadByteSigned : Operator := "001";
constant LoadHalfWordUnsigned : Operator := "010";
constant LoadHalfWordSigned : Operator := "011";
constant LoadWord : Operator := "100";
constant StoreByte : Operator := "101";
constant StoreHalfWord : Operator := "110";
constant StoreWord : Operator := "111";
constant NormalAOnly : std_logic_vector(1 downto 0) := "00";
constant DivideOverflow : std_logic_vector(1 downto 0) := "01";
constant NormalAAndD : std_logic_vector(1 downto 0) := "10";
constant GenericError : std_logic_vector(1 downto 0) := "11";
constant InterruptTableADDR : Word := "11111111111111111111111110000000";
constant JumpToReg29 : Word := "11000000000111010000000000000000";
end Constants;
package body Constants is
function GetOpcode (
W : Word)
return std_logic_vector is --Opcode
begin
return w (31 downto 29);
end;
function GetOperator (
W : Word)
return std_logic_vector is --Operator
begin
return w (28 downto 26);
end;
function GetRegisterReferenceA (
W : Word)
return std_logic_vector is --RegisterReference
begin
return w (25 downto 21);
end;
function GetRegisterReferenceB (
W : Word)
return std_logic_vector is --RegisterReference
begin
return w (20 downto 16);
end;
function GetRegisterReferenceC (
W : Word)
return std_logic_vector is --RegisterReference
begin
return w (15 downto 11);
end;
function GetRegisterReferenceD (
W : Word)
return std_logic_vector is --RegisterReference
begin
return w (10 downto 6);
end;
function GetImmediateValue (
W : Word)
return std_logic_vector is --ImmediateValue
begin
return w (15 downto 0);
end;
function GetImmediateAddress (
W : Word)
return std_logic_vector is --ImmediateAddress
begin
return w (25 downto 0);
end;
function GetImmediateConditionalAddress (
W : Word)
return std_logic_vector is --ImmediateConditionalAddress
begin
return w (20 downto 0);
end;
function SignExtendImmediateValue (
VALUE : ImmediateValue)
return std_logic_vector is --Word
begin -- SignExtendImmediate
return std_logic_vector(resize(signed(VALUE), 32));
end SignExtendImmediateValue;
function SignExtendImmediateAddress (
ADDR : ImmediateAddress)
return std_logic_vector is --Word
begin -- SignExtendImmediateAddress
return std_logic_vector(resize(signed(unsigned(ADDR) & "00"), 32));
end SignExtendImmediateAddress;
function SignExtendImmediateConditionalAddress (
ADDR : ImmediateConditionalAddress)
return std_logic_vector is --Word
begin -- SignExtendImmediateAddress
return std_logic_vector(resize(signed(unsigned(ADDR) & "00"), 32));
end SignExtendImmediateConditionalAddress;
function GetIRQ(
IRQ : std_logic_vector(23 downto 0))
return integer is
begin
for i in 0 to 23 loop
if IRQ (i) /= '0' then
return i;
end if;
end loop; -- i
return -1;
end GetIRQ;
end Constants;
| lgpl-3.0 | bbb5642fe03618d030df94165dadbc57 | 0.712213 | 4.061589 | false | false | false | false |
manosaloscables/vhdl | a-intro/ig2_bp.vhd | 1 | 1,507 | -- **********************************************
-- Banco de prueba para Circuitos combinacionales
-- **********************************************
-- En inglés se llama testbench
library ieee;
use ieee.std_logic_1164.all;
entity ig2_bp is
end ig2_bp;
architecture arq_bp of ig2_bp is
signal prueba_e1, prueba_e2: std_logic_vector(1 downto 0); -- Entradas
signal prueba_s: std_logic; -- Salida
begin
-- Instanciar la unidad bajo prueba
ubp: entity work.ig2(arq_est)
port map(
a => prueba_e1,
b => prueba_e2,
aigb => prueba_s
);
process begin
-- Vector de prueba 1
prueba_e1 <= "00";
prueba_e2 <= "00";
wait for 200 ns;
-- Vector de prueba 2
prueba_e1 <= "01";
prueba_e2 <= "00";
wait for 200 ns;
-- Vector de prueba 3
prueba_e1 <= "01";
prueba_e2 <= "11";
wait for 200 ns;
-- Vector de prueba 4
prueba_e1 <= "10";
prueba_e2 <= "10";
wait for 200 ns;
-- Vector de prueba 5
prueba_e1 <= "10";
prueba_e2 <= "00";
wait for 200 ns;
-- Vector de prueba 6
prueba_e1 <= "11";
prueba_e2 <= "11";
wait for 200 ns;
-- Vector de prueba 7
prueba_e1 <= "11";
prueba_e2 <= "01";
wait for 200 ns;
-- Terminar la simulación
assert false
report "Simulación Completada"
severity failure;
end process;
end arq_bp;
| gpl-3.0 | c96143bb952e1a813c3869dbac102c4e | 0.496011 | 3.668293 | false | false | false | false |
dpolad/dlx | DLX_vhd/a.i.a.d.b.a-CARRYSELGEN.vhd | 2 | 1,428 | library ieee;
use ieee.std_logic_1164.all;
entity carry_sel_gen is
generic( N : integer := 4);
Port ( A: In std_logic_vector(N-1 downto 0);
B: In std_logic_vector(N-1 downto 0);
Ci: In std_logic;
S: Out std_logic_vector(N-1 downto 0);
Co: Out std_logic);
end carry_sel_gen;
architecture STRUCTURAL of carry_sel_gen is
component rca
generic ( N : integer := 4);
Port ( A: In std_logic_vector(N-1 downto 0);
B: In std_logic_vector(N-1 downto 0);
Ci: In std_logic;
S: Out std_logic_vector(N-1 downto 0);
Co: Out std_logic);
end component;
component mux21
generic (
SIZE : integer
);
Port ( IN0: In std_logic_vector(N-1 downto 0);
IN1: In std_logic_vector(N-1 downto 0);
CTRL: In std_logic;
OUT1: Out std_logic_vector(N-1 downto 0));
end component;
constant zero : std_logic := '0';
constant one : std_logic := '1';
signal nocarry_sum_to_mux : std_logic_vector(N-1 downto 0);
signal carry_sum_to_mux : std_logic_vector(N-1 downto 0);
signal carry_carry_out : std_logic;
signal nocarry_carry_out : std_logic;
begin
rca_nocarry : rca
generic map (N => N)
port map (A,B,zero,nocarry_sum_to_mux,nocarry_carry_out);
rca_carry : rca
generic map (N => N)
port map (A,B,one,carry_sum_to_mux,carry_carry_out);
outmux : mux21
generic map (SIZE => N)
port map (nocarry_sum_to_mux,carry_sum_to_mux,Ci,S);
end STRUCTURAL;
| bsd-2-clause | 50dc1459ac025f1091610f97c75e92a7 | 0.642157 | 2.601093 | false | false | false | false |
dpolad/dlx | DLX_vhd/006-MUX81.vhd | 2 | 829 | library ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity mux8to1_gen is
generic ( M: integer := 64);
port(
A : in std_logic_vector (M-1 downto 0);
B : in std_logic_vector (M-1 downto 0);
C : in std_logic_vector (M-1 downto 0);
D : in std_logic_vector (M-1 downto 0);
E : in std_logic_vector (M-1 downto 0);
F : in std_logic_vector (M-1 downto 0);
G : in std_logic_vector (M-1 downto 0);
H : in std_logic_vector (M-1 downto 0);
S : in std_logic_vector (2 downto 0);
Y : out std_logic_vector (M-1 downto 0)
);
end mux8to1_gen;
architecture behavior of mux8to1_gen is
begin
Y <= A when S = "000" else
B when S = "001" else
C when S = "010" else
D when S = "011" else
E when S = "100" else
F when S = "101" else
G when S = "110" else
H when S = "111";
end behavior;
| bsd-2-clause | 25e4b6da5e726d328bee5cfb9f715fcb | 0.629674 | 2.409884 | false | false | false | false |
airabinovich/finalArquitectura | TestDatapathPart1/PipeAndDebug/ipcore_dir/RAM/simulation/RAM_tb.vhd | 2 | 4,292 | --------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: RAM_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY RAM_tb IS
END ENTITY;
ARCHITECTURE RAM_tb_ARCH OF RAM_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
RAM_synth_inst:ENTITY work.RAM_synth
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
| lgpl-2.1 | e565b06e1adc1c9326d646465f67611e | 0.617894 | 4.675381 | false | false | false | false |
dpolad/dlx | DLX_vhd/000-globals.vhd | 2 | 11,926 | library ieee;
use ieee.std_logic_1164.all;
package myTypes is
constant OP_CODE_SIZE : integer := 6; -- OPCODE field size
constant FUNC_SIZE : integer := 11;
constant PRED_SIZE : integer := 4;
type aluOp is (
NOP, SLLS, SRLS, SRAS, ADDS, ADDUS, SUBS, SUBUS, ANDS, ORS, XORS, SEQS, SNES,
SLTS,SGTS,SLES,SGES,MOVI2SS,MOVS2IS,MOVFS,MOVDS,MOVFP2IS,MOVI2FP,MOVI2TS,MOVT2IS,
SLTUS,SGTUS,SLEUS,SGEUS,
MULTU,MULTS
);
constant RTYPE : std_logic_vector(OP_CODE_SIZE - 1 downto 0) := "00"&X"0";
constant FTYPE : std_logic_vector(OP_CODE_SIZE - 1 downto 0) := "00"&X"1";
constant ITYPE_J : std_logic_vector(OP_CODE_SIZE - 1 downto 0) := "00"&X"2"; -- ADDI1 RS2,RD,INP1
constant ITYPE_JAL : std_logic_vector(OP_CODE_SIZE - 1 downto 0) := "00"&X"3"; -- ADDI1 RS2,RD,INP1
constant ITYPE_BEQZ : std_logic_vector(OP_CODE_SIZE - 1 downto 0) := "00"&X"4"; -- ADDI1 RS2,RD,INP1
constant ITYPE_BNEZ : std_logic_vector(OP_CODE_SIZE - 1 downto 0) := "00"&X"5"; -- ADDI1 RS2,RD,INP1
constant ITYPE_BFTP : std_logic_vector(OP_CODE_SIZE - 1 downto 0) := "00"&X"6"; -- ADDI1 RS2,RD,INP1
constant ITYPE_BFPF : std_logic_vector(OP_CODE_SIZE - 1 downto 0) := "00"&X"7"; -- ADDI1 RS2,RD,INP1
constant ITYPE_ADDI : std_logic_vector(OP_CODE_SIZE - 1 downto 0) := "00"&X"8"; -- ADDI1 RS2,RD,INP1
constant ITYPE_ADDUI : std_logic_vector(OP_CODE_SIZE - 1 downto 0) := "00"&X"9"; -- ADDI1 RS2,RD,INP1
constant ITYPE_SUBI : std_logic_vector(OP_CODE_SIZE - 1 downto 0) := "00"&X"A"; -- ADDI1 RS2,RD,INP1
constant ITYPE_SUBUI : std_logic_vector(OP_CODE_SIZE - 1 downto 0) := "00"&X"B"; -- ADDI1 RS2,RD,INP1
constant ITYPE_ANDI : std_logic_vector(OP_CODE_SIZE - 1 downto 0) := "00"&X"C"; -- ADDI1 RS2,RD,INP1
constant ITYPE_ORI : std_logic_vector(OP_CODE_SIZE - 1 downto 0) := "00"&X"D"; -- ADDI1 RS2,RD,INP1
constant ITYPE_XORI : std_logic_vector(OP_CODE_SIZE - 1 downto 0) := "00"&X"E"; -- ADDI1 RS2,RD,INP1
constant ITYPE_LHI : std_logic_vector(OP_CODE_SIZE - 1 downto 0) := "00"&X"F"; -- ADDI1 RS2,RD,INP1
constant ITYPE_RFE : std_logic_vector(OP_CODE_SIZE - 1 downto 0) := "01"&X"0"; -- SUBI1 RS2,RD,INP1
constant ITYPE_TRAP : std_logic_vector(OP_CODE_SIZE - 1 downto 0) := "01"&X"1"; -- ANDI1 RS2,RD,INP1
constant ITYPE_JR : std_logic_vector(OP_CODE_SIZE - 1 downto 0) := "01"&X"2"; -- ORI1 RS2,RD,INP1
constant ITYPE_JALR : std_logic_vector(OP_CODE_SIZE - 1 downto 0) := "01"&X"3"; -- ORI1 RS2,RD,INP1
constant ITYPE_SLLI : std_logic_vector(OP_CODE_SIZE - 1 downto 0) := "01"&X"4"; -- ADDI1 RS2,RD,INP1
constant ITYPE_NOP : std_logic_vector(OP_CODE_SIZE - 1 downto 0) := "01"&X"5"; -- ADDI1 RS2,RD,INP1
constant ITYPE_SRLI : std_logic_vector(OP_CODE_SIZE - 1 downto 0) := "01"&X"6"; -- ORI1 RS2,RD,INP1
constant ITYPE_SRAI : std_logic_vector(OP_CODE_SIZE - 1 downto 0) := "01"&X"7"; -- ORI1 RS2,RD,INP1
constant ITYPE_SEQI : std_logic_vector(OP_CODE_SIZE - 1 downto 0) := "01"&X"8"; -- ADDI1 RS2,RD,INP1
constant ITYPE_SNEI : std_logic_vector(OP_CODE_SIZE - 1 downto 0) := "01"&X"9"; -- ANDI1 RS2,RD,INP1
constant ITYPE_SLTI : std_logic_vector(OP_CODE_SIZE - 1 downto 0) := "01"&X"A"; -- ORI1 RS2,RD,INP1
constant ITYPE_SGTI : std_logic_vector(OP_CODE_SIZE - 1 downto 0) := "01"&X"B"; -- ORI1 RS2,RD,INP1
constant ITYPE_SLEI : std_logic_vector(OP_CODE_SIZE - 1 downto 0) := "01"&X"C"; -- ORI1 RS2,RD,INP1
constant ITYPE_SGEI : std_logic_vector(OP_CODE_SIZE - 1 downto 0) := "01"&X"D"; -- ORI1 RS2,RD,INP1
constant ITYPE_LB : std_logic_vector(OP_CODE_SIZE - 1 downto 0) := "10"&X"0"; -- ORI1 RS2,RD,INP1
constant ITYPE_LH : std_logic_vector(OP_CODE_SIZE - 1 downto 0) := "10"&X"1"; -- ORI1 RS2,RD,INP1
constant ITYPE_LW : std_logic_vector(OP_CODE_SIZE - 1 downto 0) := "10"&X"3"; -- ORI1 RS2,RD,INP1
constant ITYPE_LBU : std_logic_vector(OP_CODE_SIZE - 1 downto 0) := "10"&X"4"; -- ORI1 RS2,RD,INP1
constant ITYPE_LHU : std_logic_vector(OP_CODE_SIZE - 1 downto 0) := "10"&X"5"; -- ORI1 RS2,RD,INP1
constant ITYPE_LF : std_logic_vector(OP_CODE_SIZE - 1 downto 0) := "10"&X"6"; -- ORI1 RS2,RD,INP1
constant ITYPE_LD : std_logic_vector(OP_CODE_SIZE - 1 downto 0) := "10"&X"7"; -- ORI1 RS2,RD,INP1
constant ITYPE_SB : std_logic_vector(OP_CODE_SIZE - 1 downto 0) := "10"&X"8"; -- ORI1 RS2,RD,INP1
constant ITYPE_SH : std_logic_vector(OP_CODE_SIZE - 1 downto 0) := "10"&X"9"; -- ORI1 RS2,RD,INP1
constant ITYPE_SW : std_logic_vector(OP_CODE_SIZE - 1 downto 0) := "10"&X"B"; -- ORI1 RS2,RD,INP1
constant ITYPE_SF : std_logic_vector(OP_CODE_SIZE - 1 downto 0) := "10"&X"E"; -- ORI1 RS2,RD,INP1
constant ITYPE_SD : std_logic_vector(OP_CODE_SIZE - 1 downto 0) := "10"&X"F"; -- ORI1 RS2,RD,INP1
constant ITYPE_ITLB : std_logic_vector(OP_CODE_SIZE - 1 downto 0) := "11"&X"8"; -- ORI1 RS2,RD,INP1
constant ITYPE_SLTUI : std_logic_vector(OP_CODE_SIZE - 1 downto 0) := "11"&X"A"; -- ORI1 RS2,RD,INP1
constant ITYPE_SGTUI : std_logic_vector(OP_CODE_SIZE - 1 downto 0) := "11"&X"B"; -- ORI1 RS2,RD,INP1
constant ITYPE_SLEUI : std_logic_vector(OP_CODE_SIZE - 1 downto 0) := "11"&X"C"; -- ORI1 RS2,RD,INP1
constant ITYPE_SGEUI : std_logic_vector(OP_CODE_SIZE - 1 downto 0) := "11"&X"D"; -- ORI1 RS2,RD,INP1
constant RFUNC_SLL : std_logic_vector(FUNC_SIZE - 1 downto 0) := "000"&X"04"; -- ADD RS1,RS2,RD
constant RFUNC_SRL : std_logic_vector(FUNC_SIZE - 1 downto 0) := "000"&X"06"; -- ADD RS1,RS2,RD
constant RFUNC_SRA : std_logic_vector(FUNC_SIZE - 1 downto 0) := "000"&X"07"; -- ADD RS1,RS2,RD
constant RFUNC_ADD : std_logic_vector(FUNC_SIZE - 1 downto 0) := "000"&X"20"; -- ADD RS1,RS2,RD
constant RFUNC_ADDU : std_logic_vector(FUNC_SIZE - 1 downto 0) := "000"&X"21"; -- ADD RS1,RS2,RD
constant RFUNC_SUB : std_logic_vector(FUNC_SIZE - 1 downto 0) := "000"&X"22"; -- ADD RS1,RS2,RD
constant RFUNC_SUBU : std_logic_vector(FUNC_SIZE - 1 downto 0) := "000"&X"23"; -- ADD RS1,RS2,RD
constant RFUNC_AND : std_logic_vector(FUNC_SIZE - 1 downto 0) := "000"&X"24"; -- ADD RS1,RS2,RD
constant RFUNC_OR : std_logic_vector(FUNC_SIZE - 1 downto 0) := "000"&X"25"; -- ADD RS1,RS2,RD
constant RFUNC_XOR : std_logic_vector(FUNC_SIZE - 1 downto 0) := "000"&X"26"; -- ADD RS1,RS2,RD
constant RFUNC_SEQ : std_logic_vector(FUNC_SIZE - 1 downto 0) := "000"&X"28"; -- ADD RS1,RS2,RD
constant RFUNC_SNE : std_logic_vector(FUNC_SIZE - 1 downto 0) := "000"&X"29"; -- ADD RS1,RS2,RD
constant RFUNC_SLT : std_logic_vector(FUNC_SIZE - 1 downto 0) := "000"&X"2A"; -- ADD RS1,RS2,RD
constant RFUNC_SGT : std_logic_vector(FUNC_SIZE - 1 downto 0) := "000"&X"2B"; -- ADD RS1,RS2,RD
constant RFUNC_SLE : std_logic_vector(FUNC_SIZE - 1 downto 0) := "000"&X"2C"; -- ADD RS1,RS2,RD
constant RFUNC_SGE : std_logic_vector(FUNC_SIZE - 1 downto 0) := "000"&X"2D"; -- ADD RS1,RS2,RD
constant RFUNC_MOVI2S : std_logic_vector(FUNC_SIZE - 1 downto 0) := "000"&X"30"; -- ADD RS1,RS2,RD
constant RFUNC_MOVS2I : std_logic_vector(FUNC_SIZE - 1 downto 0) := "000"&X"31"; -- ADD RS1,RS2,RD
constant RFUNC_MOVF : std_logic_vector(FUNC_SIZE - 1 downto 0) := "000"&X"32"; -- ADD RS1,RS2,RD
constant RFUNC_MOVD : std_logic_vector(FUNC_SIZE - 1 downto 0) := "000"&X"33"; -- ADD RS1,RS2,RD
constant RFUNC_MOVFP2I : std_logic_vector(FUNC_SIZE - 1 downto 0) := "000"&X"34"; -- ADD RS1,RS2,RD
constant RFUNC_MOVI2FP : std_logic_vector(FUNC_SIZE - 1 downto 0) := "000"&X"35"; -- ADD RS1,RS2,RD
constant RFUNC_MOVI2T : std_logic_vector(FUNC_SIZE - 1 downto 0) := "000"&X"36"; -- ADD RS1,RS2,RD
constant RFUNC_MOVT2I : std_logic_vector(FUNC_SIZE - 1 downto 0) := "000"&X"37"; -- ADD RS1,RS2,RD
constant RFUNC_SLTU : std_logic_vector(FUNC_SIZE - 1 downto 0) := "000"&X"3A"; -- ADD RS1,RS2,RD
constant RFUNC_SGTU : std_logic_vector(FUNC_SIZE - 1 downto 0) := "000"&X"3B"; -- ADD RS1,RS2,RD
constant RFUNC_SLEU : std_logic_vector(FUNC_SIZE - 1 downto 0) := "000"&X"3C"; -- ADD RS1,RS2,RD
constant RFUNC_SGEU : std_logic_vector(FUNC_SIZE - 1 downto 0) := "000"&X"3D"; -- ADD RS1,RS2,RD
constant FFUNC_ADDF : std_logic_vector(FUNC_SIZE - 1 downto 0) := "000"&X"00"; -- ADD RS1,RS2,RD
constant FFUNC_SUBF : std_logic_vector(FUNC_SIZE - 1 downto 0) := "000"&X"01"; -- ADD RS1,RS2,RD
constant FFUNC_MULTF : std_logic_vector(FUNC_SIZE - 1 downto 0) := "000"&X"02"; -- ADD RS1,RS2,RD
constant FFUNC_DIVF : std_logic_vector(FUNC_SIZE - 1 downto 0) := "000"&X"03"; -- ADD RS1,RS2,RD
constant FFUNC_ADDD : std_logic_vector(FUNC_SIZE - 1 downto 0) := "000"&X"04"; -- ADD RS1,RS2,RD
constant FFUNC_SUBD : std_logic_vector(FUNC_SIZE - 1 downto 0) := "000"&X"05"; -- ADD RS1,RS2,RD
constant FFUNC_MULTD : std_logic_vector(FUNC_SIZE - 1 downto 0) := "000"&X"06"; -- ADD RS1,RS2,RD
constant FFUNC_DIVD : std_logic_vector(FUNC_SIZE - 1 downto 0) := "000"&X"07"; -- ADD RS1,RS2,RD
constant FFUNC_CVTF2D : std_logic_vector(FUNC_SIZE - 1 downto 0) := "000"&X"08"; -- ADD RS1,RS2,RD
constant FFUNC_CVTF2I : std_logic_vector(FUNC_SIZE - 1 downto 0) := "000"&X"09"; -- ADD RS1,RS2,RD
constant FFUNC_CVTD2F : std_logic_vector(FUNC_SIZE - 1 downto 0) := "000"&X"0A"; -- ADD RS1,RS2,RD
constant FFUNC_CVTD2I : std_logic_vector(FUNC_SIZE - 1 downto 0) := "000"&X"0B"; -- ADD RS1,RS2,RD
constant FFUNC_CVTI2F : std_logic_vector(FUNC_SIZE - 1 downto 0) := "000"&X"0C"; -- ADD RS1,RS2,RD
constant FFUNC_CVTI2D : std_logic_vector(FUNC_SIZE - 1 downto 0) := "000"&X"0D"; -- ADD RS1,RS2,RD
constant FFUNC_MULT : std_logic_vector(FUNC_SIZE - 1 downto 0) := "000"&X"0E"; -- ADD RS1,RS2,RD
constant FFUNC_DIV : std_logic_vector(FUNC_SIZE - 1 downto 0) := "000"&X"0F"; -- ADD RS1,RS2,RD
constant FFUNC_EQF : std_logic_vector(FUNC_SIZE - 1 downto 0) := "000"&X"10"; -- ADD RS1,RS2,RD
constant FFUNC_NEF : std_logic_vector(FUNC_SIZE - 1 downto 0) := "000"&X"11"; -- ADD RS1,RS2,RD
constant FFUNC_LFT : std_logic_vector(FUNC_SIZE - 1 downto 0) := "000"&X"12"; -- ADD RS1,RS2,RD
constant FFUNC_GTF : std_logic_vector(FUNC_SIZE - 1 downto 0) := "000"&X"13"; -- ADD RS1,RS2,RD
constant FFUNC_LEF : std_logic_vector(FUNC_SIZE - 1 downto 0) := "000"&X"14"; -- ADD RS1,RS2,RD
constant FFUNC_GEF : std_logic_vector(FUNC_SIZE - 1 downto 0) := "000"&X"15"; -- ADD RS1,RS2,RD
constant FFUNC_MULTU : std_logic_vector(FUNC_SIZE - 1 downto 0) := "000"&X"16"; -- ADD RS1,RS2,RD
constant FFUNC_DIVU : std_logic_vector(FUNC_SIZE - 1 downto 0) := "000"&X"17"; -- ADD RS1,RS2,RD
constant FFUNC_EQD : std_logic_vector(FUNC_SIZE - 1 downto 0) := "000"&X"18"; -- ADD RS1,RS2,RD
constant FFUNC_NED : std_logic_vector(FUNC_SIZE - 1 downto 0) := "000"&X"19"; -- ADD RS1,RS2,RD
constant FFUNC_LTD : std_logic_vector(FUNC_SIZE - 1 downto 0) := "000"&X"1A"; -- ADD RS1,RS2,RD
constant FFUNC_GTD : std_logic_vector(FUNC_SIZE - 1 downto 0) := "000"&X"1B"; -- ADD RS1,RS2,RD
constant FFUNC_LED : std_logic_vector(FUNC_SIZE - 1 downto 0) := "000"&X"1C"; -- ADD RS1,RS2,RD
constant FFUNC_GED : std_logic_vector(FUNC_SIZE - 1 downto 0) := "000"&X"1D"; -- ADD RS1,RS2,RD
constant TAKE_PC4 : std_logic_vector(1 downto 0) := "00";
constant TAKE_BRANCH : std_logic_vector(1 downto 0) := "11";
constant TAKE_A : std_logic_vector(1 downto 0) := "01";
constant TAKE_SUM : std_logic_vector(1 downto 0) := "10";
end myTypes;
| bsd-2-clause | 83d66ba268c232ee15648ea3caf58a84 | 0.607329 | 2.440851 | false | false | false | false |
dpolad/dlx | DLX_vhd/a.a.c-STALLLOGIC.vhd | 1 | 4,148 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
use work.myTypes.all;
--use ieee.numeric_std.all;
--use work.all;
entity stall_logic is
generic (
FUNC_SIZE : integer := 11; -- Func Field Size for R-Type Ops
OP_CODE_SIZE : integer := 6 -- Op Code Size
);
port (
-- Instruction Register
OPCODE_i : in std_logic_vector(OP_CODE_SIZE-1 downto 0);
FUNC_i : in std_logic_vector(FUNC_SIZE-1 downto 0);
rA_i : in std_logic_vector(4 downto 0);
rB_i : in std_logic_vector(4 downto 0);
D1_i : in std_logic_vector(4 downto 0); -- taken from output of destination mux in EXE stage
D2_i : in std_logic_vector(4 downto 0);
S_mem_LOAD_i : in std_logic;
S_exe_LOAD_i : in std_logic;
S_exe_WRITE_i : in std_logic;
S_MUX_PC_BUS_i : in std_logic_vector(1 downto 0);
mispredict_i : in std_logic;
bubble_dec_o : out std_logic;
bubble_exe_o : out std_logic;
stall_exe_o : out std_logic;
stall_dec_o : out std_logic;
stall_btb_o : out std_logic;
stall_fetch_o : out std_logic
);
end stall_logic;
architecture stall_logic_hw of stall_logic is
signal IS_JMP_BRANCH : std_logic;
signal STALL_JMP_BRANCH_DECODE : std_logic;
signal STALL_JMP_BRANCH_LOAD : std_logic;
signal STALL_LOAD_RTYPE : std_logic;
signal STALL_LOAD_ITYPE : std_logic;
signal IS_NO_STALL : std_logic;
signal IS_JMP : std_logic;
signal stall_dec_help : std_logic;
begin
-- every jump operation but branches
IS_JMP <= S_MUX_PC_BUS_i(1) xor S_MUX_PC_BUS_i(0);
-- TODO: need to add JALR???
-- this operation might have an hazard on decode stage ( need to access A )
IS_JMP_BRANCH <= (not or_reduce(OPCODE_i xor ITYPE_JR)) or (not or_reduce(OPCODE_i xor ITYPE_JALR)) or (not or_reduce(OPCODE_i xor ITYPE_BEQZ)) or (not or_reduce(OPCODE_i xor ITYPE_BNEZ));
-- jump operation that wont trigger any hazard ( do not require data from registers )
IS_NO_STALL <= (not or_reduce(OPCODE_i xor ITYPE_J)) or (not or_reduce(OPCODE_i xor ITYPE_JAL)) or (not or_reduce(OPCODE_i xor ITYPE_TRAP)) or (not or_reduce(OPCODE_i xor ITYPE_RFE)) or (not or_reduce(OPCODE_i xor ITYPE_NOP));
-- stall if current decoded instruction is JMP/BRANCH and it needs the same register as the one that will be written by current op in EXE
STALL_JMP_BRANCH_DECODE <= IS_JMP_BRANCH and S_exe_WRITE_i and (not or_reduce(rA_i xor D1_i));
-- stall if current decoded instruction is JMP/BRANCH and it needs the same register as the one that will be written by current LOAD
STALL_JMP_BRANCH_LOAD <= IS_JMP_BRANCH and S_mem_LOAD_i and (not or_reduce(rA_i xor D2_i));
-- TODO: check if all R type operations need both A and B
-- stall if there is data dependency between current op in dec and the next is a LOAD
STALL_LOAD_RTYPE <= S_exe_LOAD_i and ((not or_reduce(OPCODE_i xor RTYPE)) or (not or_reduce(OPCODE_i xor FTYPE))) and ( (not or_reduce(rA_i xor D1_i)) or (not or_reduce(rB_i xor D1_i))) ;
-- TODO: check if all ITYPE operation require A ( also already checked in IS_NO_STALL )
-- ITYPE instructions only need to look at A
-- TODO: IS RTYPE HERE CORRECT OR NOT??? CHECK WITH A TESTBENCH
STALL_LOAD_ITYPE <= S_exe_LOAD_i and (or_reduce(OPCODE_i xor RTYPE) and or_reduce(OPCODE_i xor FTYPE)) and (not IS_NO_STALL) and (not or_reduce(rA_i xor D1_i)) ;
--TODO: add stall for MULT and MULTU
--exe is never stopped at the moment
stall_exe_o <= '0';
-- stalls for ALL hazards + jumps
stall_dec_o <= stall_dec_help;
stall_dec_help <= STALL_JMP_BRANCH_LOAD or STALL_JMP_BRANCH_DECODE or STALL_LOAD_RTYPE or STALL_LOAD_ITYPE;
-- stalls for ALL hazards + jumps
stall_btb_o <= STALL_JMP_BRANCH_LOAD or STALL_JMP_BRANCH_DECODE or STALL_LOAD_RTYPE or STALL_LOAD_ITYPE ;
-- stall only in case of hazard, not for jumps
stall_fetch_o <= STALL_JMP_BRANCH_LOAD or STALL_JMP_BRANCH_DECODE or STALL_LOAD_RTYPE or STALL_LOAD_ITYPE;
-- bubble is triggered only for mispredictions or unpredictable jumps
bubble_dec_o <= mispredict_i and (not stall_dec_help);
bubble_exe_o <= stall_dec_help;
end stall_logic_hw;
| bsd-2-clause | 655798a35fc66dea161383da636bb8b6 | 0.695275 | 2.910877 | false | false | false | false |
airabinovich/finalArquitectura | TestDatapathPart1/DatapathPart1/ipcore_dir/blk_mem_gen_v7_3/simulation/bmg_stim_gen.vhd | 1 | 12,582 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port ROM
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SROM
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SROM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SROM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SROM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST /= '0' ) THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
GENERIC ( C_ROM_SYNTH : INTEGER := 0
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA: OUT STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
DATA_IN : IN STD_LOGIC_VECTOR (31 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
FUNCTION hex_to_std_logic_vector(
hex_str : STRING;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR((hex_str'LENGTH*4)+return_width-1
DOWNTO 0);
BEGIN
tmp := (OTHERS => '0');
FOR i IN 1 TO hex_str'LENGTH LOOP
CASE hex_str((hex_str'LENGTH+1)-i) IS
WHEN '0' => tmp(i*4-1 DOWNTO (i-1)*4) := "0000";
WHEN '1' => tmp(i*4-1 DOWNTO (i-1)*4) := "0001";
WHEN '2' => tmp(i*4-1 DOWNTO (i-1)*4) := "0010";
WHEN '3' => tmp(i*4-1 DOWNTO (i-1)*4) := "0011";
WHEN '4' => tmp(i*4-1 DOWNTO (i-1)*4) := "0100";
WHEN '5' => tmp(i*4-1 DOWNTO (i-1)*4) := "0101";
WHEN '6' => tmp(i*4-1 DOWNTO (i-1)*4) := "0110";
WHEN '7' => tmp(i*4-1 DOWNTO (i-1)*4) := "0111";
WHEN '8' => tmp(i*4-1 DOWNTO (i-1)*4) := "1000";
WHEN '9' => tmp(i*4-1 DOWNTO (i-1)*4) := "1001";
WHEN 'a' | 'A' => tmp(i*4-1 DOWNTO (i-1)*4) := "1010";
WHEN 'b' | 'B' => tmp(i*4-1 DOWNTO (i-1)*4) := "1011";
WHEN 'c' | 'C' => tmp(i*4-1 DOWNTO (i-1)*4) := "1100";
WHEN 'd' | 'D' => tmp(i*4-1 DOWNTO (i-1)*4) := "1101";
WHEN 'e' | 'E' => tmp(i*4-1 DOWNTO (i-1)*4) := "1110";
WHEN 'f' | 'F' => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
WHEN OTHERS => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
END CASE;
END LOOP;
RETURN tmp(return_width-1 DOWNTO 0);
END hex_to_std_logic_vector;
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECK_READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL CHECK_DATA : STD_LOGIC := '0';
SIGNAL CHECK_DATA_R : STD_LOGIC := '0';
SIGNAL CHECK_DATA_2R : STD_LOGIC := '0';
SIGNAL DO_READ_REG: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(31 DOWNTO 0):= hex_to_std_logic_vector("0",32);
BEGIN
SYNTH_COE: IF(C_ROM_SYNTH =0 ) GENERATE
type mem_type is array (255 downto 0) of std_logic_vector(31 downto 0);
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
function char_to_std_logic (
char : in character)
return std_logic is
variable data : std_logic;
begin
if char = '0' then
data := '0';
elsif char = '1' then
data := '1';
elsif char = 'X' then
data := 'X';
else
assert false
report "character which is not '0', '1' or 'X'."
severity warning;
data := 'U';
end if;
return data;
end char_to_std_logic;
impure FUNCTION init_memory( C_USE_DEFAULT_DATA : INTEGER;
C_LOAD_INIT_FILE : INTEGER ;
C_INIT_FILE_NAME : STRING ;
DEFAULT_DATA : STD_LOGIC_VECTOR(31 DOWNTO 0);
width : INTEGER;
depth : INTEGER)
RETURN mem_type IS
VARIABLE init_return : mem_type := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(width-1 DOWNTO 0);
VARIABLE bitline : LINE;
variable bitsgood : boolean := true;
variable bitchar : character;
VARIABLE i : INTEGER;
VARIABLE j : INTEGER;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Block Memory Generator CORE Generator module loading initial data..." SEVERITY NOTE;
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
FOR i IN 0 TO depth-1 LOOP
init_return(i) := DEFAULT_DATA;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, bitline);
-- read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO width-1 LOOP
read(bitline,bitchar,bitsgood);
init_return(i)(width-1-j) := char_to_std_logic(bitchar);
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
constant c_init : mem_type := init_memory(0,
1,
"blk_mem_gen_v7_3.mif",
DEFAULT_DATA,
32,
256);
constant rom : mem_type := c_init;
BEGIN
EXPECTED_DATA <= rom(conv_integer(unsigned(check_read_addr)));
CHECKER_RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH =>256 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => CHECK_DATA_2R,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => CHECK_READ_ADDR
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R ='1') THEN
IF(EXPECTED_DATA = DATA_IN) THEN
STATUS<='0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- Simulatable ROM
--Synthesizable ROM
SYNTH_CHECKER: IF(C_ROM_SYNTH = 1) GENERATE
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R='1') THEN
IF(DATA_IN=DEFAULT_DATA) THEN
STATUS <= '0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
READ_ADDR_INT(7 DOWNTO 0) <= READ_ADDR(7 DOWNTO 0);
ADDRA <= READ_ADDR_INT ;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 256 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
RD_PROCESS: PROCESS (CLK)
BEGIN
IF (RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_READ <= '0';
ELSE
DO_READ <= '1';
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(0),
CLK =>CLK,
RST=>RST,
D =>DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(I),
CLK =>CLK,
RST=>RST,
D =>DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
CHECK_DATA_REG_1: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_2R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA_R
);
CHECK_DATA_REG: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA
);
END ARCHITECTURE;
| lgpl-2.1 | c88fb47fa1e915e13177a399a613d0ef | 0.547528 | 3.678947 | false | false | false | false |
airabinovich/finalArquitectura | TestDatapathPart1/PipeAndDebug/ipcore_dir/RAM/simulation/RAM_synth.vhd | 2 | 7,853 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: RAM_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY RAM_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE RAM_synth_ARCH OF RAM_synth IS
COMPONENT RAM_exdes
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 32,
READ_WIDTH => 32 )
PORT MAP (
CLK => CLKA,
RST => RSTA,
EN => CHECKER_EN_R,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RSTA='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECKER_EN AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
WEA => WEA,
CHECK_DATA => CHECKER_EN
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: RAM_exdes PORT MAP (
--Port A
WEA => WEA_R,
ADDRA => ADDRA_R,
DINA => DINA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
| lgpl-2.1 | 9e4f156cb349a78228f81e55323202e8 | 0.563988 | 3.779115 | false | false | false | false |
rodrigofegui/UnB | 2017.1/Organização e Arquitetura de Computadores/Trabalhos/Trabalho 3/Codificação/Banco Registradores/RegBank.vhd | 1 | 3,446 | ----------------------------------------------------------------------------------
-- Responsáveis: Danillo Neves
-- Luiz Gustavo
-- Rodrigo Guimarães
-- Ultima mod.: 03/jun/2017
-- Nome do Módulo: Banco de Registradores
-- Descrição: Conjunto de registradores com largura de palavra parametrizável
-- e com habilitação
----------------------------------------------------------------------------------
----------------------------------
-- Importando a biblioteca IEEE e especificando o uso dos estados lógicos
-- padrão
----------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
----------------------------------
-- Definiçao da entidade:
-- DATA_WIDTH - palavra
-- ADDRESS_WIDTH - enderecamento dos registradores
-- AMOUNT_REG - qnt de registradores possiveis
-- clk - clock de sincronizacao
-- wren - habilitar escrita
-- radd1 - endereço leitura 1
-- radd2 - endereço leitura 2
-- wadd - endereço escrita
-- wdata - dado escrita
-- rdata1 - dado escrita 1
-- rdata2 - dado escrita 2
----------------------------------
entity RegBank is
Generic (DATA_WIDTH : natural := 32;
ADDRESS_WIDTH : natural := 5;
AMOUNT_REG : natural := 32);
Port (clk, wren : in std_logic;
radd1, radd2 : in std_logic_vector(ADDRESS_WIDTH - 1 downto 0);
wadd : in std_logic_vector(ADDRESS_WIDTH - 1 downto 0);
wdata : in std_logic_vector(DATA_WIDTH - 1 downto 0);
rdata1, rdata2: out std_logic_vector(DATA_WIDTH - 1 downto 0));
end entity RegBank;
----------------------------------
-- Descritivo da operacionalidade da entidade
----------------------------------
architecture RegBank_Op of RegBank is
-- Componente descrito no proprio arquivo *.vhd
component Registrador_Nbits is
Generic (N : integer := DATA_WIDTH);
Port (clk : in std_logic;
D : in std_logic_vector(N - 1 downto 0) := (others => '0');
Q : out std_logic_vector(N - 1 downto 0));
end component;
-- Manipuladores dos registradores do banco
type vector_array is array (natural range <>) of std_logic_vector(DATA_WIDTH - 1 downto 0);
signal D : vector_array(0 to AMOUNT_REG - 1);
signal Q : vector_array(0 to AMOUNT_REG - 1);
begin
-- Geraçao do banco de registradores
Reg_Index: for i in 0 to AMOUNT_REG - 1 generate
Regx : Registrador_Nbits port map
(clk, D(i), Q(i));
end generate Reg_Index;
Sincronizacao: process (clk)
begin
-- Sincronizado com o flanco de subida
if rising_edge(clk) then
-- Nao havendo escrita habilitada, so le
if wren = '0' then
rdata1 <= Q(to_integer(unsigned(radd1)));
rdata2 <= Q(to_integer(unsigned(radd2)));
-- Com a escrita habilitada
else
-- Sendo diferente do $zero, escreve-se
if to_integer(unsigned(wadd)) /= 0 then
D(to_integer(unsigned(wadd))) <= wdata;
end if;
-- Se WADD != RADD1, se le; senao le 0
if to_integer(unsigned(wadd)) /= to_integer(unsigned(radd1)) then
rdata1 <= Q(to_integer(unsigned(radd1)));
else
rdata1 <= (others => '0');
end if;
-- Leitura: WADD != RADD2; senao le 0
if to_integer(unsigned(wadd)) /= to_integer(unsigned(radd2)) then
rdata2 <= Q(to_integer(unsigned(radd2)));
else
rdata2 <= (others => '0');
end if;
end if;
end if;
end process Sincronizacao;
end architecture RegBank_Op; | gpl-3.0 | ec86230663c7268c0866c2b5267f8a73 | 0.585252 | 3.212547 | false | false | false | false |
dpolad/dlx | DLX_vhd/a.f.b-EXTENDER32.vhd | 2 | 890 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--use work.myTypes.all;
entity extender_32 is
generic (
SIZE : integer := 32
);
port (
IN1 : in std_logic_vector(SIZE - 1 downto 0);
CTRL : in std_logic; -- when 0 extend on 16 bits , when 1 extend on 26 bits
SIGN : in std_logic; -- when 0 unsigned, when 1 signed
OUT1 : out std_logic_vector(SIZE - 1 downto 0)
);
end extender_32;
architecture Bhe of extender_32 is
signal TEMP16 : std_logic_vector(15 downto 0);
signal TEMP26 : std_logic_vector(25 downto 0);
begin
TEMP16 <= IN1(15 downto 0);
TEMP26 <= IN1(25 downto 0);
OUT1 <= std_logic_vector(resize(signed(TEMP26),SIZE)) when CTRL = '1' else
std_logic_vector(resize(signed(TEMP16),SIZE)) when CTRL = '0' and SIGN = '1' else
std_logic_vector(resize(unsigned(TEMP16),SIZE)); -- CTRL = 0 SIGN = 0
end Bhe;
| bsd-2-clause | dc5716a6fe407d7cb0f464f840be1a8f | 0.655056 | 2.825397 | false | false | false | false |
MAV-RT-testbed/MAV-testbed | Syma_Flight_Final/Syma_Flight_Final.srcs/sources_1/ipshared/xilinx.com/axi_quad_spi_v3_2/c64e9f22/hdl/src/vhdl/qspi_fifo_ifmodule.vhd | 1 | 16,786 | -------------------------------------------------------------------------------
-- qspi_fifo_ifmodule.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: qspi_fifo_ifmodule.vhd
-- Version: v3.0
-- Description: Quad Serial Peripheral Interface (QSPI) Module for interfacing
-- with a 32-bit axi Bus. FIFO Interface module
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library lib_pkg_v1_0;
use lib_pkg_v1_0.all;
use lib_pkg_v1_0.lib_pkg.RESET_ACTIVE;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_NUM_TRANSFER_BITS -- SPI Serial transfer width.
-- Can be 8, 16 or 32 bit wide
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- SYSTEM
-- Bus2IP_Clk -- Bus to IP clock
-- Soft_Reset_op -- Soft_Reset_op Signal
-- SLAVE ATTACHMENT INTERFACE
-- Bus2IP_RcFIFO_RdCE -- Bus2IP receive FIFO read CE
-- Bus2IP_TxFIFO_WrCE -- Bus2IP transmit FIFO write CE
-- Rd_ce_reduce_ack_gen -- commong logid to generate the write ACK
-- Wr_ce_reduce_ack_gen -- commong logid to generate the write ACK
-- IP2Bus_RX_FIFO_Data -- Data to send on the bus
-- Transmit_ip2bus_error -- Transmit FIFO error signal
-- Receive_ip2bus_error -- Receive FIFO error signal
-- FIFO INTERFACE
-- Data_From_TxFIFO -- Data from transmit FIFO
-- Tx_FIFO_Data_WithZero -- Components to put zeros on input
-- to Shift Register when FIFO is empty
-- Data_From_Rc_FIFO -- Receive FIFO data output
-- Rc_FIFO_Empty -- Receive FIFO empty
-- Rc_FIFO_Full -- Receive FIFO full
-- Rc_FIFO_Full_strobe -- 1 cycle wide receive FIFO full strobe
-- Tx_FIFO_Empty -- Transmit FIFO empty
-- Tx_FIFO_Empty_strobe -- 1 cycle wide transmit FIFO full strobe
-- Tx_FIFO_Full -- Transmit FIFO full
-- Tx_FIFO_Occpncy_MSB -- Transmit FIFO occupancy register
-- MSB bit
-- Tx_FIFO_less_half -- Transmit FIFO less than half empty
-- SPI MODULE INTERFACE
-- DRR_Overrun -- DRR Overrun bit
-- SPIXfer_done -- SPI transfer done flag
-- DTR_Underrun_strobe -- DTR Underrun Strobe bit
-- DTR_underrun -- DTR underrun generation signal
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Declaration
-------------------------------------------------------------------------------
entity qspi_fifo_ifmodule is
generic
(
C_NUM_TRANSFER_BITS : integer
----------------------------
);
port
(
Bus2IP_Clk : in std_logic;
Soft_Reset_op : in std_logic;
-- Slave attachment ports
Bus2IP_RcFIFO_RdCE : in std_logic;
Bus2IP_TxFIFO_WrCE : in std_logic;
Rd_ce_reduce_ack_gen : in std_logic;
-- FIFO ports
Data_From_TxFIFO : in std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
Data_From_Rc_FIFO : in std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
Tx_FIFO_Data_WithZero: out std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
IP2Bus_RX_FIFO_Data : out std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
---------------------
Rc_FIFO_Full : in std_logic;
Rc_FIFO_Full_strobe : out std_logic;
---------------------
Tx_FIFO_Empty : in std_logic;
Tx_FIFO_Empty_strobe : out std_logic;
---------------------
Rc_FIFO_Empty : in std_logic;
Receive_ip2bus_error : out std_logic;
Tx_FIFO_Full : in std_logic;
Transmit_ip2bus_error: out std_logic;
---------------------
Tx_FIFO_Occpncy_MSB : in std_logic;
Tx_FIFO_less_half : out std_logic;
---------------------
DTR_underrun : in std_logic;
DTR_Underrun_strobe : out std_logic;
---------------------
SPIXfer_done : in std_logic;
rready : in std_logic
--DRR_Overrun_reg : out std_logic
---------------------
);
end qspi_fifo_ifmodule;
-------------------------------------------------------------------------------
-- Architecture
---------------
architecture imp of qspi_fifo_ifmodule is
---------------------------------------------------
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-- Signal Declarations
----------------------
-- signal drr_Overrun_i : std_logic;
signal rc_FIFO_Full_d1 : std_logic;
signal dtr_Underrun_strobe_i : std_logic;
signal tx_FIFO_Empty_d1 : std_logic;
signal tx_FIFO_Occpncy_MSB_d1 : std_logic;
signal dtr_underrun_d1 : std_logic;
signal RST_TxFIFO_ptr_int : std_logic;
signal DRR_Overrun_reg_int : std_logic;
---------------------------------------------
begin
-----
-- Combinatorial operations
-------------------------------------------------------------------------------
-- DRR_Overrun_reg <= DRR_Overrun_reg_int;
-------------------------------------------------------------------------------
-- SPI_RECEIVE_FIFO_RD_GENERATE : Read of SPI receive FIFO
----------------------------------
SPI_RECEIVE_FIFO_RD_GENERATE: for i in 0 to C_NUM_TRANSFER_BITS-1 generate
-----
begin
-----
IP2Bus_RX_FIFO_Data(i) <= Data_From_Rc_FIFO(i) and
(
(Rd_ce_reduce_ack_gen or rready) and
Bus2IP_RcFIFO_RdCE
);
end generate SPI_RECEIVE_FIFO_RD_GENERATE;
-------------------------------------------------------------------------------
-- PUT_ZEROS_IN_SR_GENERATE : Put zeros on input to SR when FIFO is empty.
-- Requested by software designers
------------------------------
PUT_ZEROS_IN_SR_GENERATE: for i in 0 to C_NUM_TRANSFER_BITS-1 generate
begin
-----
Tx_FIFO_Data_WithZero(i) <= Data_From_TxFIFO(i) and (not Tx_FIFO_Empty);
end generate PUT_ZEROS_IN_SR_GENERATE;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- RX_ERROR_ACK_REG_PROCESS : Strobe error when receive FIFO is empty.
-------------------------------- This signal will be OR'ed to generate IP2Bus_Error signal.
RX_ERROR_ACK_REG_PROCESS:process(Bus2IP_Clk) is
-----
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
Receive_ip2bus_error <= '0';
else
Receive_ip2bus_error <= Rc_FIFO_Empty and Bus2IP_RcFIFO_RdCE;
end if;
end if;
end process RX_ERROR_ACK_REG_PROCESS;
-------------------------------------------------------------------------------
-- TX_ERROR_ACK_REG_PROCESS : Strobe error when transmit FIFO is full
-------------------------------- This signal will be OR'ed to generate IP2Bus_Error signal.
TX_ERROR_ACK_REG_PROCESS:process(Bus2IP_Clk) is
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
Transmit_ip2bus_error <= '0';
else
Transmit_ip2bus_error <= Tx_FIFO_Full and Bus2IP_TxFIFO_WrCE;
end if;
end if;
end process TX_ERROR_ACK_REG_PROCESS;
-------------------------------------------------------------------------------
-- **********************************************************
-- Below logic will generate the inputs to the Interrupt bits
-- **********************************************************
-------------------------------------------------------------------------------
-- I_DRR_OVERRUN_REG_PROCESS:DRR overrun strobe-1 cycle strobe will be generated
-----------------------------
DRR_OVERRUN_REG_PROCESS:process(Bus2IP_Clk) is
-----
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
DRR_Overrun_reg_int <= '0';
else
DRR_Overrun_reg_int <= not(DRR_Overrun_reg_int or Soft_Reset_op) and
Rc_FIFO_Full and
SPIXfer_done;
end if;
end if;
end process DRR_OVERRUN_REG_PROCESS;
-------------------------------------------------------------------------------
-- RX_FIFO_STROBE_REG_PROCESS : Strobe when receive FIFO is full
----------------------------------
RX_FIFO_STROBE_REG_PROCESS:process(Bus2IP_Clk) is
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
rc_FIFO_Full_d1 <= '0';
else
rc_FIFO_Full_d1 <= Rc_FIFO_Full;
end if;
end if;
end process RX_FIFO_STROBE_REG_PROCESS;
-----------------------------------------
Rc_FIFO_Full_strobe <= (not rc_FIFO_Full_d1) and Rc_FIFO_Full;
-- TX_FIFO_STROBE_REG_PROCESS : Strobe when transmit FIFO is empty
----------------------------------
TX_FIFO_STROBE_REG_PROCESS:process(Bus2IP_Clk)is
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
tx_FIFO_Empty_d1 <= '1';
else
tx_FIFO_Empty_d1 <= Tx_FIFO_Empty;
end if;
end if;
end process TX_FIFO_STROBE_REG_PROCESS;
-----------------------------------------
Tx_FIFO_Empty_strobe <= (not tx_FIFO_Empty_d1) and Tx_FIFO_Empty;
-------------------------------------------------------------------------------
-- DTR_UNDERRUN_REG_PROCESS_P : Strobe to interrupt for transmit data underrun
-- which happens only in slave mode
-----------------------------
DTR_UNDERRUN_REG_PROCESS_P:process(Bus2IP_Clk)is
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
dtr_underrun_d1 <= '0';
else
dtr_underrun_d1 <= DTR_underrun;
end if;
end if;
end process DTR_UNDERRUN_REG_PROCESS_P;
---------------------------------------
DTR_Underrun_strobe <= DTR_underrun and (not dtr_underrun_d1);
-------------------------------------------------------------------------------
-- TX_FIFO_HALFFULL_STROBE_REG_PROCESS_P : Strobe for when transmit FIFO is
-- less than half full
-------------------------------------------
TX_FIFO_HALFFULL_STROBE_REG_PROCESS_P:process(Bus2IP_Clk) is
-----
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
tx_FIFO_Occpncy_MSB_d1 <= '0';
else
tx_FIFO_Occpncy_MSB_d1 <= Tx_FIFO_Occpncy_MSB;
end if;
end if;
end process TX_FIFO_HALFFULL_STROBE_REG_PROCESS_P;
--------------------------------------------------
Tx_FIFO_less_half <= tx_FIFO_Occpncy_MSB_d1 and (not Tx_FIFO_Occpncy_MSB);
--------------------------------------------------------------------------
end imp;
--------------------------------------------------------------------------------
| gpl-2.0 | 1e45a280cef5a8cf823701950d11fccf | 0.440307 | 4.709877 | false | false | false | false |
Hyperion302/omega-cpu | Core/ALU.vhdl | 1 | 20,570 | -- This file is part of the Omega CPU Core
-- Copyright 2015 - 2016 Joseph Shetaye
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as
-- published by the Free Software Foundation, either version 3 of the
-- License, or (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library IEEE;
use IEEE.std_logic_1164.all;
use work.Constants.all;
use IEEE.Numeric_std.all;
entity ALU is
port (
RegisterB : in Word;
RegisterC : in Word;
Instruction : in Word;
RegisterA : out Word;
RegisterD : out Word;
Carry : out std_logic;
OutputReady : out std_logic;
Status : out std_logic_vector(1 downto 0));
end ALU;
architecture Behavioral of ALU is
constant OperatorOr : std_logic_vector(1 downto 0) := "00";
constant OperatorAnd : std_logic_vector(1 downto 0) := "01";
constant OperatorXor : std_logic_vector(1 downto 0) := "10";
constant OperatorAdd : std_logic_vector(1 downto 0) := "00";
constant OperatorSub : std_logic_vector(1 downto 0) := "01";
constant OperatorMultiply : std_logic_vector(1 downto 0) := "10";
constant OperatorDivide : std_logic_vector(1 downto 0) := "11";
constant OperatorShiftRight : std_logic := '0';
constant OperatorShiftLeft : std_logic := '1';
constant OpSigned : std_logic := '0';
constant OpUnsigned : std_logic := '1';
constant OperatorEqual : std_logic := '0';
constant OperatorLessThan : std_logic := '1';
constant NormalAOnly : std_logic_vector(1 downto 0) := "00";
constant DivideOverflow : std_logic_vector(1 downto 0) := "01";
constant NormalAAndD : std_logic_vector(1 downto 0) := "10";
constant GenericError : std_logic_vector(1 downto 0) := "11";
signal Opcode_S : Opcode;
signal Operator_S : Operator;
signal RegisterReferenceA : RegisterReference;
signal RegisterReferenceB : RegisterReference;
signal RegisterReferenceC : RegisterReference;
signal RegisterReferenceD : RegisterReference;
signal ImmediateValue_S : ImmediateValue;
signal RegisterA_S : std_logic_vector(32 downto 0);
signal RegisterD_S : std_logic_vector(32 downto 0);
signal Carry_S : std_logic;
begin -- Behavioral
Opcode_S <= GetOpcode(Instruction);
Operator_S <= GetOperator(Instruction);
RegisterReferenceA <= GetRegisterReferenceA(Instruction);
RegisterReferenceB <= GetRegisterReferenceB(Instruction);
RegisterReferenceC <= GetRegisterReferenceC(Instruction);
RegisterReferenceD <= GetRegisterReferenceD(Instruction);
ImmediateValue_S <= GetImmediateValue(Instruction);
RegisterA <= RegisterA_S(31 downto 0);
RegisterD <= RegisterD_S(31 downto 0);
Carry <= Carry_S;
Math: process (Opcode_S, Operator_S, RegisterReferenceA, RegisterReferenceB, RegisterReferenceC, RegisterReferenceD, ImmediateValue_S, RegisterB, RegisterC)
variable Product : std_logic_vector(63 downto 0);
variable SignExtendedImmediate : std_logic_vector(31 downto 0);
variable Result : std_logic_vector(32 downto 0);
begin -- process Math
case Opcode_S is
when OpcodeLogical =>
case Operator_S(2 downto 1) is
when OperatorOr => -- Or
case Operator_S(0) is
when RegisterMode =>
RegisterD_S <= (others => '0');
RegisterA_S <= "0" & (RegisterB or RegisterC);
Carry_S <= '0';
OutputReady <= '1';
Status <= NormalAOnly;
when ImmediateMode =>
RegisterD_S <= (others => '0');
RegisterA_S <= "0" & (RegisterB or ("0000000000000000" & ImmediateValue_S));
OutputReady <= '1';
Carry_S <= '0';
Status <= NormalAOnly;
when others =>
Carry_S <= '0';
OutputReady <= '1';
Status <= GenericError;
end case;
when OperatorAnd => -- And
case Operator_S(0) is
when RegisterMode =>
RegisterD_S <= (others => '0');
RegisterA_S <= "0" & (RegisterB and RegisterC);
OutputReady <= '1';
Carry_S <= '0';
Status <= NormalAOnly;
when ImmediateMode =>
RegisterD_S <= (others => '0');
RegisterA_S <= "0" & (RegisterB and ("0000000000000000" & ImmediateValue_S));
OutputReady <= '1';
Carry_S <= '0';
Status <= NormalAOnly;
when others =>
Carry_S <= '0';
OutputReady <= '1';
Status <= GenericError;
end case;
when OperatorXor => --Xor
case Operator_S(0) is
when RegisterMode =>
RegisterD_S <= (others => '0');
RegisterA_S <= "0" & (RegisterB xor RegisterC);
OutputReady <= '1';
Carry_S <= '0';
Status <= NormalAOnly;
when ImmediateMode =>
RegisterD_S <= (others => '0');
RegisterA_S <= "0" & (RegisterB xor ("0000000000000000" & ImmediateValue_S));
OutputReady <= '1';
Carry_S <= '0';
Status <= NormalAOnly;
when others =>
Carry_S <= '0';
OutputReady <= '1';
Status <= GenericError;
end case;
when others =>
OutputReady <= '1';
Status <= GenericError;
end case;
when OpcodeArithmetic =>
case Operator_S(2 downto 1) is
when OperatorAdd => -- Add
case Operator_S(0) is
when RegisterMode =>
RegisterD_S <= (others => '0');
Result := std_logic_vector(("0" & unsigned(RegisterB)) + ("0" & unsigned(RegisterC)));
RegisterA_S <= Result;
OutputReady <= '1';
Carry_S <= Result(32);
Status <= NormalAOnly;
when ImmediateMode =>
SignExtendedImmediate:= std_logic_vector(resize(signed(ImmediateValue_S), 32));
RegisterD_S <= (others => '0');
Result := std_logic_vector(("0" & unsigned(RegisterB)) + ("0" & unsigned(SignExtendedImmediate)));
OutputReady <= '1';
RegisterA_S <= Result;
Carry_S <= Result(32);
Status <= NormalAOnly;
when others =>
Carry_S <= '0';
OutputReady <= '1';
Status <= GenericError;
end case;
when OperatorSub => -- Sub
case Operator_S(0) is
when RegisterMode =>
RegisterD_S <= (others => '0');
Result := std_logic_vector(("0" & unsigned(RegisterB)) - ("0" & unsigned(RegisterC)));
OutputReady <= '1';
RegisterA_S <= Result;
Carry_S <= Result(32);
Status <= NormalAOnly;
when ImmediateMode =>
SignExtendedImmediate:= std_logic_vector(resize(signed(ImmediateValue_S), 32));--std_logic_vector(not(resize(signed(ImmediateValue_S), 32)) + 1);
RegisterD_S <= (others => '0');
Result := std_logic_vector(("0" & unsigned(RegisterB)) - ("0" & unsigned(SignExtendedImmediate)));
RegisterA_S <= Result;
OutputReady <= '1';
Carry_S <= Result(32);
Status <= NormalAOnly;
when others =>
Carry_S <= '0';
OutputReady <= '1';
Status <= GenericError;
end case;
when OperatorMultiply => -- Multiply
case Operator_S(0) is
when RegisterMode =>
Product:= std_logic_vector(unsigned(RegisterB) * unsigned(RegisterC));
RegisterD_S <= (others => '0');
RegisterA_S <= Product(32 downto 0);
OutputReady <= '1';
Carry_S <= '0';
Status <= NormalAOnly;
when ImmediateMode =>
SignExtendedImmediate:= std_logic_vector(resize(signed(ImmediateValue_S), 32));
Product:= std_logic_vector(unsigned(RegisterB) * unsigned(SignExtendedImmediate));
RegisterD_S <= "0" & Product(63 downto 32);
RegisterA_S <= Product(32 downto 0);
OutputReady <= '1';
Carry_S <= '0';
Status <= NormalAOnly;
when others =>
Carry_S <= '0';
OutputReady <= '1';
Status <= GenericError;
end case;
-- when OperatorDivide => -- Divide And Remainder
-- case Operator_S(0) is
-- when RegisterMode =>
--
-- OutputReady <= '1';
-- if signed(RegisterC) = 0 then
-- OutputReady <= '1';
-- Carry_S <= '0';
-- Status <= DivideOverflow;
-- RegisterA_S <= (others => '0');
-- RegisterD_S <= (others => '0');
-- else
-- Carry_S <= '0';
-- RegisterA_S <= "0" & std_logic_vector(signed(RegisterB) / signed(RegisterC));
-- RegisterD_S <= "0" & std_logic_vector(signed(RegisterB) rem signed(RegisterC));
-- OutputReady <= '1';
-- Status <= NormalAAndD;
-- end if;
-- when ImmediateMode =>
-- SignExtendedImmediate := std_logic_vector(resize(signed(ImmediateValue_S), 32));
-- OutputReady <= '1';
-- if signed(SignExtendedImmediate) = 0 then
-- OutputReady <= '1';
-- Carry_S <= '0';
-- Status <= DivideOverflow;
-- RegisterA_S <= (others => '0');
-- RegisterD_S <= (others => '0');
-- else
-- Carry_S <= '0';
-- RegisterA_S <= "0" & std_logic_vector(signed(RegisterB) / signed(SignExtendedImmediate));
-- RegisterD_S <= "0" & std_logic_vector(signed(RegisterB) rem signed(SignExtendedImmediate));
-- OutputReady <= '1';
-- Status <= NormalAAndD;
-- end if;
-- when others =>
-- Carry_S <= '0';
-- OutputReady <= '1';
-- Status <= GenericError;
-- end case;
when others =>
Carry_S <= '0';
OutputReady <= '1';
Status <= GenericError;
end case;
when OpcodeShift =>
case Operator_S(2) is
when OperatorShiftRight =>
case Operator_S(1) is
when OpUnsigned =>
case Operator_S(0) is
when RegisterMode =>
RegisterD_S <= (others => '0');
RegisterA_S <= std_logic_vector(shift_right("0" & unsigned(RegisterB),to_integer("0" & unsigned(RegisterC))));
OutputReady <= '1';
Status <= NormalAOnly;
when ImmediateMode =>
RegisterD_S <= (others => '0');
RegisterA_S <= std_logic_vector(shift_right("0" & unsigned(RegisterB),to_integer(unsigned(ImmediateValue_S))));
OutputReady <= '1';
Status <= NormalAOnly;
when others =>
Carry_S <= '0';
OutputReady <= '1';
Status <= GenericError;
end case;
when OpSigned =>
case Operator_S(0) is
when RegisterMode =>
RegisterD_S <= (others => '0');
RegisterA_S <= std_logic_vector(shift_right("0" & signed(RegisterB),to_integer("0" & unsigned(RegisterC))));
OutputReady <= '1';
Status <= NormalAOnly;
when ImmediateMode =>
RegisterD_S <= (others => '0');
RegisterA_S <= std_logic_vector(shift_right("0" & signed(RegisterB),to_integer(unsigned(ImmediateValue_S))));
OutputReady <= '1';
Status <= NormalAOnly;
Carry_S <= '0';
when others =>
Carry_S <= '0';
OutputReady <= '1';
Status <= GenericError;
end case;
when others =>
OutputReady <= '1';
Carry_S <= '0';
Status <= GenericError;
end case;
when OperatorShiftLeft =>
case Operator_S(1) is
when OpUnsigned =>
case Operator_S(0) is
when RegisterMode =>
RegisterD_S <= (others => '0');
RegisterA_S <= std_logic_vector(shift_left("0" & unsigned(RegisterB),to_integer("0" & unsigned(RegisterC))));
OutputReady <= '1';
Carry_S <= '0';
Status <= NormalAOnly;
when ImmediateMode =>
RegisterD_S <= (others => '0');
RegisterA_S <= std_logic_vector(shift_left("0" & unsigned(RegisterB),to_integer(unsigned(ImmediateValue_S))));
OutputReady <= '1';
Carry_S <= '0';
Status <= NormalAOnly;
when others =>
Carry_S <= '0';
OutputReady <= '1';
Status <= GenericError;
end case;
when OpSigned =>
case Operator_S(0) is
when RegisterMode =>
RegisterD_S <= (others => '0');
RegisterA_S <= std_logic_vector(shift_left("0" & signed(RegisterB),to_integer("0" & unsigned(RegisterC))));
OutputReady <= '1';
Carry_S <= '0';
Status <= NormalAOnly;
when ImmediateMode =>
RegisterD_S <= (others => '0');
RegisterA_S <= std_logic_vector(shift_left("0" & signed(RegisterB),to_integer(unsigned(ImmediateValue_S))));
OutputReady <= '1';
Carry_S <= '0';
Status <= NormalAOnly;
when others =>
OutputReady <= '1';
Carry_S <= '0';
Status <= GenericError;
end case;
when others =>
OutputReady <= '1';
Carry_S <= '0';
Status <= GenericError;
end case;
when others =>
OutputReady <= '1';
Carry_S <= '0';
Status <= GenericError;
end case;
when OpcodeRelational =>
case Operator_S(2) is
when OperatorLessThan =>
case Operator_S(1) is
when OpUnsigned =>
case Operator_S(0) is
when RegisterMode =>
if ("0" & unsigned(RegisterB)) < ("0" & unsigned(RegisterC)) then
RegisterD_S <= (others => '0');
RegisterA_S <= (0 => '1', others => '0');
else
RegisterD_S <= (others => '0');
RegisterA_S <= (0 => '0', others => '0');
end if;
OutputReady <= '1';
Carry_S <= '0';
Status <= NormalAOnly;
when ImmediateMode =>
if ("0" & unsigned(RegisterB)) < unsigned(ImmediateValue_S) then
RegisterD_S <= (others => '0');
RegisterA_S <= (0 => '1', others => '0');
else
RegisterD_S <= (others => '0');
RegisterA_S <= (0 => '0', others => '0');
OutputReady <= '1';
Carry_S <= '0';
Status <= NormalAOnly;
end if;
when others =>
OutputReady <= '1';
Carry_S <= '0';
Status <= GenericError;
end case;
when OpSigned =>
case Operator_S(0) is
when RegisterMode =>
if signed(RegisterB) < signed(RegisterC) then
RegisterD_S <= (others => '0');
RegisterA_S <= (0 => '1', others => '0');
else
RegisterD_S <= (others => '0');
RegisterA_S <= (0 => '0', others => '0');
end if;
OutputReady <= '1';
Carry_S <= '0';
Status <= NormalAOnly;
when ImmediateMode =>
if signed(RegisterB) < signed(ImmediateValue_S) then
RegisterD_S <= (others => '0');
RegisterA_S <= (0 => '1', others => '0');
else
RegisterD_S <= (others => '0');
RegisterA_S <= (0 => '0', others => '0');
end if;
OutputReady <= '1';
Carry_S <= '0';
Status <= NormalAOnly;
when others =>
OutputReady <= '1';
Carry_S <= '0';
Status <= GenericError;
end case;
when others =>
OutputReady <= '1';
Carry_S <= '0';
Status <= GenericError;
end case;
when OperatorEqual =>
case Operator_S(0) is
when RegisterMode =>
if RegisterB = RegisterC then
RegisterD_S <= (others => '0');
RegisterA_S <= (0 => '1', others => '0');
else
RegisterD_S <= (others => '0');
RegisterA_S <= (0 => '0', others => '0');
end if;
Carry_S <= '0';
OutputReady <= '1';
Status <= NormalAOnly;
when ImmediateMode =>
case Operator_S(1) is
when OpUnsigned =>
if ("0" & unsigned(RegisterB)) = unsigned(ImmediateValue_S) then
RegisterD_S <= (others => '0');
RegisterA_S <= (0 => '1', others => '0');
else
RegisterD_S <= (others => '0');
RegisterA_S <= (0 => '0', others => '0');
end if;
Carry_S <= '0';
OutputReady <= '1';
Status <= NormalAOnly;
when OpSigned =>
if ("0" & signed(RegisterB)) = signed(ImmediateValue_S) then
RegisterD_S <= (others => '0');
RegisterA_S <= (0 => '1', others => '0');
else
RegisterD_S <= (others => '0');
RegisterA_S <= (0 => '0', others => '0');
end if;
OutputReady <= '1';
Carry_S <= '0';
Status <= NormalAOnly;
when others =>
OutputReady <= '1';
Carry_S <= '0';
Status <= GenericError;
end case;
when others =>
OutputReady <= '1';
Carry_S <= '0';
Status <= GenericError;
end case;
when others =>
OutputReady <= '1';
Carry_S <= '0';
Status <= GenericError;
end case;
when others =>
OutputReady <= '1';
Carry_S <= '0';
Status <= GenericError;
end case;
end process Math;
end Behavioral;
| lgpl-3.0 | cfb63d3429788216b6e583e08aeead3c | 0.458337 | 4.537834 | false | false | false | false |
rodrigofegui/UnB | 2017.1/Organização e Arquitetura de Computadores/Trabalhos/Projeto Final/Codificação/dec_mi.vhd | 2 | 1,978 | --Módulo para definir instrução armazenada em determinado endereço de MI. A instrução irá seguir para display 7 segmentos
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity dec_mi is
generic(N: integer := 7; M: integer := 32);
port(
clk : in std_logic;
SW : in STD_LOGIC_VECTOR(N-1 downto 0);
HEX0 : out STD_LOGIC_VECTOR(6 downto 0);
HEX1 : out STD_LOGIC_VECTOR(6 downto 0);
HEX2 : out STD_LOGIC_VECTOR(6 downto 0);
HEX3 : out STD_LOGIC_VECTOR(6 downto 0);
HEX4 : out STD_LOGIC_VECTOR(6 downto 0);
HEX5 : out STD_LOGIC_VECTOR(6 downto 0);
HEX6 : out STD_LOGIC_VECTOR(6 downto 0);
HEX7 : out STD_LOGIC_VECTOR(6 downto 0)
);
end;
architecture dec_mi_arch of dec_mi is
-- signals
signal dout : STD_LOGIC_VECTOR(31 DOWNTO 0);
begin
i1 : entity work.mi
generic map(N => N, M => M)
port map (
address => SW,
clk => clk,
instruction => dout
);
i2 : entity work.seven_seg_decoder
port map (
data => dout(3 downto 0),
segments => HEX0
);
i3 : entity work.seven_seg_decoder
port map (
data => dout(7 downto 4),
segments => HEX1
);
i4 : entity work.seven_seg_decoder
port map (
data => dout(11 downto 8),
segments => HEX2
);
i5 : entity work.seven_seg_decoder
port map (
data => dout(15 downto 12),
segments => HEX3
);
i6 : entity work.seven_seg_decoder
port map (
data => dout(19 downto 16),
segments => HEX4
);
i7 : entity work.seven_seg_decoder
port map (
data => dout(23 downto 20),
segments => HEX5
);
i8 : entity work.seven_seg_decoder
port map (
data => dout(27 downto 24),
segments => HEX6
);
i9 : entity work.seven_seg_decoder
port map (
data => dout(31 downto 28),
segments => HEX7
);
end; | gpl-3.0 | c4077c279bbcc6d55d678d7d4309545c | 0.569254 | 3.032308 | false | false | false | false |
INTI-CMNB/Lattuino_IP_Core | Work/lattuino_1_bl_2.vhdl | 1 | 11,197 | ------------------------------------------------------------------------------
---- ----
---- Single Port RAM that maps to a Xilinx/Lattice BRAM ----
---- ----
---- This file is part FPGA Libre project http://fpgalibre.sf.net/ ----
---- ----
---- Description: ----
---- This is a program memory for the AVR. It maps to a Xilinx/Lattice ----
---- BRAM. ----
---- This version can be modified by the CPU (i. e. SPM instruction) ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008-2017 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008-2017 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: SinglePortPM(Xilinx) (Entity and architecture) ----
---- File name: pm_s_rw.in.vhdl (template used) ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: work ----
---- Dependencies: IEEE.std_logic_1164 ----
---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ----
---- iCE40 (iCE40HX4K) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
---- iCEcube2.2016.02 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity lattuino_1_blPM_2 is
generic(
WORD_SIZE : integer:=16; -- Word Size
FALL_EDGE : std_logic:='0'; -- Ram clock falling edge
ADDR_W : integer:=13); -- Address Width
port(
clk_i : in std_logic;
addr_i : in std_logic_vector(ADDR_W-1 downto 0);
data_o : out std_logic_vector(WORD_SIZE-1 downto 0);
we_i : in std_logic;
data_i : in std_logic_vector(WORD_SIZE-1 downto 0));
end entity lattuino_1_blPM_2;
architecture Xilinx of lattuino_1_blPM_2 is
constant ROM_SIZE : natural:=2**ADDR_W;
type rom_t is array(natural range 0 to ROM_SIZE-1) of std_logic_vector(WORD_SIZE-1 downto 0);
signal addr_r : std_logic_vector(ADDR_W-1 downto 0);
signal rom : rom_t :=
(
696 => x"c00e",
697 => x"c01b",
698 => x"c01a",
699 => x"c019",
700 => x"c018",
701 => x"c017",
702 => x"c016",
703 => x"c015",
704 => x"c014",
705 => x"c013",
706 => x"c012",
707 => x"c011",
708 => x"c010",
709 => x"c00f",
710 => x"c00e",
711 => x"2411",
712 => x"be1f",
713 => x"edcf",
714 => x"bfcd",
715 => x"e020",
716 => x"e6a0",
717 => x"e0b0",
718 => x"c001",
719 => x"921d",
720 => x"36a5",
721 => x"07b2",
722 => x"f7e1",
723 => x"d036",
724 => x"c125",
725 => x"cfe2",
726 => x"e081",
727 => x"bb8f",
728 => x"e681",
729 => x"ee93",
730 => x"e1a6",
731 => x"e0b0",
732 => x"99f1",
733 => x"c00a",
734 => x"9701",
735 => x"09a1",
736 => x"09b1",
737 => x"9700",
738 => x"05a1",
739 => x"05b1",
740 => x"f7b9",
741 => x"e0e0",
742 => x"e0f0",
743 => x"9509",
744 => x"ba1f",
745 => x"b38e",
746 => x"9508",
747 => x"e091",
748 => x"bb9f",
749 => x"9bf0",
750 => x"cffe",
751 => x"ba1f",
752 => x"bb8e",
753 => x"e080",
754 => x"e090",
755 => x"9508",
756 => x"dfe1",
757 => x"3280",
758 => x"f421",
759 => x"e184",
760 => x"dff2",
761 => x"e180",
762 => x"cff0",
763 => x"9508",
764 => x"93cf",
765 => x"2fc8",
766 => x"dfd7",
767 => x"3280",
768 => x"f439",
769 => x"e184",
770 => x"dfe8",
771 => x"2f8c",
772 => x"dfe6",
773 => x"e180",
774 => x"91cf",
775 => x"cfe3",
776 => x"91cf",
777 => x"9508",
778 => x"9abe",
779 => x"e044",
780 => x"e450",
781 => x"e020",
782 => x"e030",
783 => x"b388",
784 => x"2785",
785 => x"bb88",
786 => x"01c9",
787 => x"9701",
788 => x"f7f1",
789 => x"5041",
790 => x"f7c1",
791 => x"e011",
792 => x"dfbd",
793 => x"3380",
794 => x"f0c9",
795 => x"3381",
796 => x"f499",
797 => x"dfb8",
798 => x"3280",
799 => x"f7c1",
800 => x"e184",
801 => x"dfc9",
802 => x"e481",
803 => x"dfc7",
804 => x"e586",
805 => x"dfc5",
806 => x"e582",
807 => x"dfc3",
808 => x"e280",
809 => x"dfc1",
810 => x"e489",
811 => x"dfbf",
812 => x"e583",
813 => x"dfbd",
814 => x"e580",
815 => x"c0c2",
816 => x"3480",
817 => x"f421",
818 => x"dfa3",
819 => x"dfa2",
820 => x"dfbf",
821 => x"cfe2",
822 => x"3481",
823 => x"f469",
824 => x"df9d",
825 => x"3880",
826 => x"f411",
827 => x"e082",
828 => x"c029",
829 => x"3881",
830 => x"f411",
831 => x"e081",
832 => x"c025",
833 => x"3882",
834 => x"f511",
835 => x"e182",
836 => x"c021",
837 => x"3482",
838 => x"f429",
839 => x"e1c4",
840 => x"df8d",
841 => x"50c1",
842 => x"f7e9",
843 => x"cfe8",
844 => x"3485",
845 => x"f421",
846 => x"df87",
847 => x"df86",
848 => x"df85",
849 => x"cfe0",
850 => x"eb90",
851 => x"0f98",
852 => x"3093",
853 => x"f2f0",
854 => x"3585",
855 => x"f439",
856 => x"df7d",
857 => x"9380",
858 => x"0063",
859 => x"df7a",
860 => x"9380",
861 => x"0064",
862 => x"cfd5",
863 => x"3586",
864 => x"f439",
865 => x"df74",
866 => x"df73",
867 => x"df72",
868 => x"df71",
869 => x"e080",
870 => x"df95",
871 => x"cfb0",
872 => x"3684",
873 => x"f009",
874 => x"c039",
875 => x"df6a",
876 => x"9380",
877 => x"0062",
878 => x"df67",
879 => x"9380",
880 => x"0061",
881 => x"9210",
882 => x"0060",
883 => x"df62",
884 => x"3485",
885 => x"f419",
886 => x"9310",
887 => x"0060",
888 => x"c00a",
889 => x"9180",
890 => x"0063",
891 => x"9190",
892 => x"0064",
893 => x"0f88",
894 => x"1f99",
895 => x"9390",
896 => x"0064",
897 => x"9380",
898 => x"0063",
899 => x"e0c0",
900 => x"e0d0",
901 => x"9180",
902 => x"0061",
903 => x"9190",
904 => x"0062",
905 => x"17c8",
906 => x"07d9",
907 => x"f008",
908 => x"cfa7",
909 => x"df48",
910 => x"2f08",
911 => x"df46",
912 => x"9190",
913 => x"0060",
914 => x"91e0",
915 => x"0063",
916 => x"91f0",
917 => x"0064",
918 => x"1191",
919 => x"c005",
920 => x"921f",
921 => x"2e00",
922 => x"2e18",
923 => x"95e8",
924 => x"901f",
925 => x"9632",
926 => x"93f0",
927 => x"0064",
928 => x"93e0",
929 => x"0063",
930 => x"9622",
931 => x"cfe1",
932 => x"3784",
933 => x"f009",
934 => x"c03e",
935 => x"df2e",
936 => x"9380",
937 => x"0062",
938 => x"df2b",
939 => x"9380",
940 => x"0061",
941 => x"9210",
942 => x"0060",
943 => x"df26",
944 => x"3485",
945 => x"f419",
946 => x"9310",
947 => x"0060",
948 => x"c00a",
949 => x"9180",
950 => x"0063",
951 => x"9190",
952 => x"0064",
953 => x"0f88",
954 => x"1f99",
955 => x"9390",
956 => x"0064",
957 => x"9380",
958 => x"0063",
959 => x"df16",
960 => x"3280",
961 => x"f009",
962 => x"cf55",
963 => x"e184",
964 => x"df26",
965 => x"e0c0",
966 => x"e0d0",
967 => x"9180",
968 => x"0061",
969 => x"9190",
970 => x"0062",
971 => x"17c8",
972 => x"07d9",
973 => x"f528",
974 => x"9180",
975 => x"0060",
976 => x"2388",
977 => x"f011",
978 => x"e080",
979 => x"c005",
980 => x"91e0",
981 => x"0063",
982 => x"91f0",
983 => x"0064",
984 => x"9184",
985 => x"df11",
986 => x"9180",
987 => x"0063",
988 => x"9190",
989 => x"0064",
990 => x"9601",
991 => x"9390",
992 => x"0064",
993 => x"9380",
994 => x"0063",
995 => x"9621",
996 => x"cfe2",
997 => x"3785",
998 => x"f479",
999 => x"deee",
1000 => x"3280",
1001 => x"f009",
1002 => x"cf2d",
1003 => x"e184",
1004 => x"defe",
1005 => x"e18e",
1006 => x"defc",
1007 => x"e981",
1008 => x"defa",
1009 => x"e088",
1010 => x"def8",
1011 => x"e180",
1012 => x"def6",
1013 => x"cf22",
1014 => x"3786",
1015 => x"f009",
1016 => x"cf1f",
1017 => x"cf6b",
1018 => x"94f8",
1019 => x"cfff",
others => x"0000"
);
begin
use_rising_edge:
if FALL_EDGE='0' generate
do_rom:
process (clk_i)
begin
if rising_edge(clk_i)then
addr_r <= addr_i;
if we_i='1' then
rom(to_integer(unsigned(addr_i))) <= data_i;
end if;
end if;
end process do_rom;
end generate use_rising_edge;
use_falling_edge:
if FALL_EDGE='1' generate
do_rom:
process (clk_i)
begin
if falling_edge(clk_i)then
addr_r <= addr_i;
if we_i='1' then
rom(to_integer(unsigned(addr_i))) <= data_i;
end if;
end if;
end process do_rom;
end generate use_falling_edge;
data_o <= rom(to_integer(unsigned(addr_r)));
end architecture Xilinx; -- Entity: lattuino_1_blPM_2
| gpl-2.0 | e12b88e15de061c850065660fe882b0e | 0.382335 | 3.117205 | false | false | false | false |
achan1989/SlowWorm | sim/memory/ram_256x16/testbench.vhd | 1 | 2,719 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 24.08.2016 15:22:18
-- Design Name:
-- Module Name: testbench - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity testbench is
end testbench;
architecture Behavioral of testbench is
component ram_256x16 is port (
dout : out std_ulogic_vector (15 downto 0);
din : in std_ulogic_vector (15 downto 0);
addr : in unsigned (7 downto 0);
we : in std_ulogic;
clk : in std_ulogic);
end component;
signal clk : std_ulogic := '0';
signal we : std_ulogic := '0';
signal addr : unsigned (7 downto 0);
signal din : std_ulogic_vector (15 downto 0);
signal dout : std_ulogic_vector (15 downto 0);
constant ClockPeriod : TIME := 50 ns;
begin
UUT: ram_256x16 port map (
dout => dout,
din => din,
addr => addr,
we => we,
clk => clk
);
clock: process begin
clk <= '0';
wait for ClockPeriod;
loop
clk <= not clk;
wait for (ClockPeriod / 2);
end loop;
end process;
stimulus: process begin
-- Starting values.
addr <= TO_UNSIGNED(0, addr'length);
we <= '0';
wait until falling_edge(clk);
-- Write to address 1.
wait until rising_edge(clk);
addr <= TO_UNSIGNED(1, addr'length);
din <= x"ABCD";
we <= '1';
-- Write to address 2.
wait until rising_edge(clk);
we <= '1';
addr <= TO_UNSIGNED(2, addr'length);
din <= x"FACE";
-- Do nothing for 3 ticks.
wait until rising_edge(clk);
we <= '0';
addr <= TO_UNSIGNED(10, addr'length);
din <= x"0000";
wait until rising_edge(clk);
wait until rising_edge(clk);
-- Read address 1.
wait until rising_edge(clk);
addr <= TO_UNSIGNED(1, addr'length);
we <= '0';
-- Read address 2.
wait until rising_edge(clk);
addr <= TO_UNSIGNED(2, addr'length);
we <= '0';
-- Do nothing more.
wait until rising_edge(clk);
we <= '0';
addr <= TO_UNSIGNED(10, addr'length);
din <= x"0000";
wait;
end process;
end Behavioral;
| mit | 626ae75f526e8334df2262f513a222a1 | 0.571166 | 3.719562 | false | false | false | false |
SWORDfpga/ComputerOrganizationDesign | labs/lab08/lab08/ipcore_dir/ROM_D/simulation/ROM_D_tb_agen.vhd | 8 | 4,316 |
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Address Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: ROM_D_tb_agen.vhd
--
-- Description:
-- Address Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY ROM_D_TB_AGEN IS
GENERIC (
C_MAX_DEPTH : INTEGER := 1024 ;
RST_VALUE : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS=> '0');
RST_INC : INTEGER := 0);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
LOAD :IN STD_LOGIC;
LOAD_VALUE : IN STD_LOGIC_VECTOR (31 DOWNTO 0) := (OTHERS => '0');
ADDR_OUT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) --OUTPUT VECTOR
);
END ROM_D_TB_AGEN;
ARCHITECTURE BEHAVIORAL OF ROM_D_TB_AGEN IS
SIGNAL ADDR_TEMP : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS =>'0');
BEGIN
ADDR_OUT <= ADDR_TEMP;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
ELSE
IF(EN='1') THEN
IF(LOAD='1') THEN
ADDR_TEMP <=LOAD_VALUE;
ELSE
IF(ADDR_TEMP = C_MAX_DEPTH-1) THEN
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
ELSE
ADDR_TEMP <= ADDR_TEMP + '1';
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE;
| gpl-3.0 | c00883c2e4a8a9bb73e159f80ed21eb5 | 0.5943 | 4.426667 | false | false | false | false |
dpolad/dlx | DLX_vhd/a.i.a-ALU.vhd | 1 | 6,453 | -- real_alu.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.myTypes.all;
entity real_alu is
generic (
DATA_SIZE : integer := 32);
port (
IN1 : in std_logic_vector(DATA_SIZE - 1 downto 0);
IN2 : in std_logic_vector(DATA_SIZE - 1 downto 0);
-- OP : in AluOp;
ALUW_i : in std_logic_vector(12 downto 0);
DOUT : out std_logic_vector(DATA_SIZE - 1 downto 0);
stall_o : out std_logic;
Clock : in std_logic;
Reset : in std_logic
);
end real_alu;
architecture Bhe of real_alu is
component simple_booth_add_ext
generic (N : integer);
port(
Clock : in std_logic;
Reset : in std_logic;
sign : in std_logic;
enable : in std_logic;
valid : out std_logic;
A : in std_logic_vector (N-1 downto 0);
B : in std_logic_vector (N-1 downto 0);
A_to_add : out std_logic_vector (2*N-1 downto 0);
B_to_add : out std_logic_vector (2*N-1 downto 0);
final_out : out std_logic_vector (2*N-1 downto 0);
sign_to_add : out std_logic;
ACC_from_add : in std_logic_vector (2*N-1 downto 0)
);
end component;
component p4add
generic (
N : integer := 32;
logN : integer := 5);
Port (
A : in std_logic_vector(N-1 downto 0);
B : in std_logic_vector(N-1 downto 0);
Cin : in std_logic;
sign : In std_logic;
S : out std_logic_vector(N-1 downto 0);
Cout : out std_logic);
end component;
component comparator
generic (M : integer := 32);
port (
C : in std_logic; -- carry out
V : in std_logic; -- overflow
SUM : in std_logic_vector(M-1 downto 0);
sel : in std_logic_vector(2 downto 0); -- selection
sign : in std_logic; -- 0 unsigned / signed 1
S : out std_logic
);
end component;
component bhe_comparator is
generic (M : integer := 32);
port (
A : in std_logic_vector(M-1 downto 0); -- carry out
B : in std_logic_vector(M-1 downto 0);
sign : in std_logic;
sel : in std_logic_vector(2 downto 0); -- selection
S : out std_logic
);
end component;
component shifter
port(
A : in std_logic_vector(31 downto 0);
B : in std_logic_vector(4 downto 0);
LOGIC_ARITH : in std_logic; -- 1 = logic, 0 = arith
LEFT_RIGHT : in std_logic; -- 1 = left, 0 = right
OUTPUT : out std_logic_vector(31 downto 0)
);
end component;
component logic_unit
generic ( SIZE : integer := 32 );
port (
IN1 : in std_logic_vector(SIZE - 1 downto 0);
IN2 : in std_logic_vector(SIZE - 1 downto 0);
CTRL : in std_logic_vector(1 downto 0); -- need to do only and, or and xor
OUT1 : out std_logic_vector(SIZE - 1 downto 0)
);
end component;
signal sign_to_booth : std_logic;
signal enable_to_booth : std_logic;
signal valid_from_booth : std_logic;
signal A_booth_to_add : std_logic_vector(DATA_SIZE-1 downto 0);
signal B_booth_to_add : std_logic_vector(DATA_SIZE-1 downto 0);
signal sign_booth_to_add : std_logic;
signal sum_out : std_logic_vector(DATA_SIZE-1 downto 0);
signal comp_out : std_logic;
signal shift_out : std_logic_vector(DATA_SIZE-1 downto 0);
signal mult_out : std_logic_vector(DATA_SIZE-1 downto 0);
signal mux_A : std_logic_vector(DATA_SIZE-1 downto 0);
signal mux_B : std_logic_vector(DATA_SIZE-1 downto 0);
signal mux_sign : std_logic;
signal carry_from_adder : std_logic;
signal overflow : std_logic;
signal sign_bit_to_comp : std_logic;
signal out_mux_sel : std_logic_vector(2 downto 0);
signal comp_sel : std_logic_vector(2 downto 0);
signal sign_to_adder : std_logic;
signal left_right : std_logic; -- 1 = logic, 0 = arith
signal logic_arith : std_logic; -- 1 = left, 0 = right
signal lu_ctrl : std_logic_vector(1 downto 0);
signal lu_out : std_logic_vector(DATA_SIZE-1 downto 0);
signal ALU_WORD_TEST :std_logic_vector(12 downto 0);
begin
ALU_WORD_TEST <= out_mux_sel&left_right&logic_arith&sign_to_adder&lu_ctrl&comp_sel&enable_to_booth&sign_to_booth;
out_mux_sel <= ALUW_i(12 downto 10);
left_right <= ALUW_i(9);
logic_arith <= ALUW_i(8);
sign_to_adder <= ALUW_i(7);
lu_ctrl <= ALUW_i(6 downto 5);
comp_sel <= ALUW_i(4 downto 2);
enable_to_booth <= ALUW_i(1);
sign_to_booth <= ALUW_i(0);
mux_A <= IN1 when enable_to_booth = '0' else
A_booth_to_add when enable_to_booth = '1' else
(others => 'X');
mux_B <= IN2 when enable_to_booth = '0' else
B_booth_to_add when enable_to_booth = '1' else
(others => 'X');
mux_sign <= sign_to_adder when enable_to_booth = '0' else
sign_booth_to_add when enable_to_booth = '1' else
'X';
sign_bit_to_comp <= IN1(DATA_SIZE-1) xor IN2(DATA_SIZE-1);
MULT: simple_booth_add_ext
generic map ( N => DATA_SIZE/2)
port Map(
Clock => Clock,
Reset => Reset,
sign => sign_to_booth,
enable => enable_to_booth,
valid => valid_from_booth,
A => IN1(DATA_SIZE/2-1 downto 0),
B => IN2(DATA_SIZE/2-1 downto 0),
A_to_add => A_booth_to_add,
B_to_add => B_booth_to_add,
final_out => mult_out,
sign_to_add => sign_booth_to_add,
ACC_from_add => sum_out
);
ADDER: p4add
generic map (
N => DATA_SIZE,
logN => 5
)
port map (
A => mux_A,
B => mux_B,
Cin => '0',
sign => mux_sign,
S => sum_out,
Cout => carry_from_adder
);
COMP: comparator
generic map ( M => DATA_SIZE)
port map (
C => carry_from_adder,
V => overflow,
SUM => sum_out,
sel => comp_sel,
sign => sign_to_booth,
S => comp_out
);
-- NO MORE USED, IMPROVES SPEED, INCREASES AREA
-- BHE_COMP: bhe_comparator
-- generic map ( M => DATA_SIZE)
-- port map (
-- A => IN1,
-- B => IN2,
-- sel => comp_sel,
-- sign => sign_to_booth,
-- S => comp_out
-- );
SHIFT: shifter
port map(
A => IN1,
B => IN2(4 downto 0),
LOGIC_ARITH => logic_arith,
LEFT_RIGHT => left_right,
OUTPUT => shift_out
);
LU: logic_unit
generic map( SIZE => DATA_SIZE)
port map(
IN1 => IN1,
IN2 => IN2,
CTRL => lu_ctrl,
OUT1 => lu_out
);
overflow <= (IN2(DATA_SIZE-1) xnor sum_out(DATA_SIZE-1)) and (IN1(DATA_SIZE-1) xor IN2(DATA_SIZE-1));
-- stalling while booth is in process
stall_o <= enable_to_booth and not(valid_from_booth);
DOUT <= sum_out when out_mux_sel = "000" else
lu_out when out_mux_sel = "001" else
shift_out when out_mux_sel = "010" else
"000"&X"0000000"&comp_out when out_mux_sel = "011" else
IN2 when out_mux_sel = "100" else
mult_out when out_mux_sel = "101" else
(others => 'X');
end bhe;
| bsd-2-clause | 03589a454dbed30ccda7860aed073e54 | 0.617077 | 2.429593 | false | false | false | false |
rodrigofegui/UnB | 2017.1/Organização e Arquitetura de Computadores/Trabalhos/Trabalho 3/Codificação/RegBank/RegBank.vhd | 1 | 2,609 | ----------------------------------------------------------------------------------
-- Responsáveis: Danillo Neves
-- Luiz Gustavo
-- Rodrigo Guimarães
-- Ultima mod.: 03/jun/2017
-- Nome do Módulo: Banco de Registradores
-- Descrição: Conjunto de registradores com largura de palavra parametrizável
-- e com habilitação
----------------------------------------------------------------------------------
----------------------------------
-- Importando a biblioteca IEEE e especificando o uso dos estados lógicos
-- padrão
----------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
----------------------------------
-- Definiçao da entidade
----------------------------------
entity RegBank is
Generic (DATA_WIDTH : natural := 32;
ADDRESS_WIDTH : natural := 5;
AMOUNT_REG : natural := 32);
Port (clk, wren : in std_logic;
radd1, radd2 : in std_logic_vector(ADDRESS_WIDTH - 1 downto 0);
wadd : in std_logic_vector(ADDRESS_WIDTH - 1 downto 0);
wdata : in std_logic_vector(DATA_WIDTH - 1 downto 0);
rdata1, rdata2: out std_logic_vector(DATA_WIDTH - 1 downto 0));
end entity RegBank;
----------------------------------
-- Descritivo da operacionalidade da entidade
----------------------------------
architecture RegBank_Op of RegBank is
-- Modelo de Registrador a ser utilizado no banco
component Registrador_Nbits is
Generic (N : integer := DATA_WIDTH);
Port (clk, rst, ce : in std_logic;
D : in std_logic_vector(N - 1 downto 0);
Q : out std_logic_vector(N - 1 downto 0));
end component;
-- Manipuladores dos registradores do banco
type vector_array is array (natural range <>) of std_logic_vector(DATA_WIDTH - 1 downto 0);
signal RST : std_logic_vector(AMOUNT_REG - 1 downto 0);
signal CE : std_logic_vector(AMOUNT_REG - 1 downto 0);
signal D : vector_array(AMOUNT_REG - 1 downto 0);
signal Q : vector_array(AMOUNT_REG - 1 downto 0);
begin
-- Geraçao do banco de registradores
Reg_Index: for i in 0 to AMOUNT_REG - 1 generate
Regx : Registrador_Nbits port map
(clk, RST(i), CE(i), D(i), Q(i));
end generate Reg_Index;
Sincronizacao: process (clk)
begin
if rising_edge(clk) then
if wren = '1' and to_integer(unsigned(wadd)) /= 0 then -- (unsigned(wadd))
D(to_integer(unsigned(wadd))) <= wdata;
end if;
rdata1 <= Q(to_integer(unsigned(radd1)));
rdata2 <= Q(to_integer(unsigned(radd2)));
end if;
end process Sincronizacao;
end architecture RegBank_Op; | gpl-3.0 | ec37cdce7eb585e793e0e24880c8ba3f | 0.575664 | 3.329487 | false | false | false | false |
airabinovich/finalArquitectura | TestDatapathPart1/PipeAndDebug/ipcore_dir/instructionROM/simulation/instructionROM_synth.vhd | 2 | 6,863 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: instructionROM_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY instructionROM_synth IS
GENERIC (
C_ROM_SYNTH : INTEGER := 1
);
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE instructionROM_synth_ARCH OF instructionROM_synth IS
COMPONENT instructionROM_exdes
PORT (
--Inputs - Port A
ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL ADDRA: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
GENERIC MAP( C_ROM_SYNTH => C_ROM_SYNTH
)
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(ADDRA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ELSE
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: instructionROM_exdes PORT MAP (
--Port A
ADDRA => ADDRA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
| lgpl-2.1 | 38bd12734aeca4e8dc8dd1ef24605d22 | 0.582981 | 3.829799 | false | false | false | false |
hugofragata/euromillions-keygen-vhdl | clkdivider.vhd | 1 | 594 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity ClkDividerN is
generic(divFactor : integer := 10);
port(clkIn : in std_logic;
clkOut : out std_logic);
end ClkDividerN;
architecture Behav of ClkDividerN is
signal s_divCounter : integer := 0;
begin
process(clkIn)
begin
if (rising_edge(clkIn)) then
if (s_divCounter = (divFactor - 1)) then
clkOut <= '0';
s_divCounter <= 0;
else
if (s_divCounter = (divFactor / 2 - 1)) then
clkOut <= '1';
end if;
s_divCounter <= s_divCounter + 1;
end if;
end if;
end process;
end Behav; | mit | fd41d543bf59e5701014e49e4e8436c0 | 0.653199 | 3.245902 | false | false | false | false |
manosaloscables/vhdl | a-intro/ctos_comb.vhd | 1 | 1,024 | -- *************************
-- Circuitos combinacionales
-- *************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY work;
ENTITY comb_circuits IS
PORT
(
e1: IN STD_LOGIC;
e2: IN STD_LOGIC;
ig: OUT STD_LOGIC;
a1: IN STD_LOGIC_VECTOR(1 DOWNTO 0);
b1: IN STD_LOGIC_VECTOR(1 DOWNTO 0);
aigb1: OUT STD_LOGIC;
a2: IN STD_LOGIC_VECTOR(1 DOWNTO 0);
b2: IN STD_LOGIC_VECTOR(1 DOWNTO 0);
aigb2: OUT STD_LOGIC
);
END comb_circuits;
ARCHITECTURE arq_est OF comb_circuits IS
BEGIN
unidad_ig1_1: entity work.ig1(arq_sdp)
port map(
e1=>e1,
e2=>e2,
ig=>ig
);
uni_ig2_1: entity work.ig2(arq_sdp) -- Arquitectura de suma de productos
port map(
a=>a1,
b=>b1,
aigb=>aigb1
);
uni_ig2_2: entity work.ig2(arq_est) -- Arquitectura estructural
port map(
a=>a2,
b=>b2,
aigb=>aigb2
);
END arq_est; | gpl-3.0 | 9ed88c002841369fe1b0ce2d4dc81d2d | 0.511719 | 2.934097 | false | false | false | false |
Hyperion302/omega-cpu | Hardware/Omega/OmegaTopTB.vhd | 1 | 3,259 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:44:52 10/01/2016
-- Design Name:
-- Module Name: /home/student1/Documents/Omega/CPU/Hardware/Omega/OmegaTopTB.vhd
-- Project Name: Omega
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: OmegaTop
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
library work;
use work.Constants.ALL;
ENTITY OmegaTopTB IS
END OmegaTopTB;
ARCHITECTURE behavior OF OmegaTopTB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT OmegaTop
PORT(
CLK : IN std_logic;
RX : IN std_logic;
TX : OUT std_logic;
LEDS : out std_logic_vector(7 downto 0);
SRAM_addr : out std_logic_vector(20 downto 0);
SRAM_OE : out std_logic;
SRAM_CE : out std_logic;
SRAM_WE : out std_logic;
SRAM_data : inout std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal RX : std_logic := '0';
--Outputs
signal TX : std_logic;
signal LEDS : std_logic_vector(7 downto 0);
signal SRAM_addr : std_logic_vector(20 downto 0);
signal SRAM_OE : std_logic;
signal SRAM_CE : std_logic;
signal SRAM_WE : std_logic;
signal SRAM_data : std_logic_vector(7 downto 0);
signal memory : MemoryArray := (others => (others => '0'));
-- Clock period definitions
constant CLK_period : time := 31.25 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: OmegaTop PORT MAP (
CLK => CLK,
RX => RX,
TX => TX,
LEDS => LEDS,
SRAM_addr => SRAM_addr,
SRAM_OE => SRAM_OE,
SRAM_CE => SRAM_CE,
SRAM_WE => SRAM_WE,
SRAM_data => SRAM_data
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
read_proc: process(SRAM_oe,SRAM_addr)
begin
if SRAM_oe = '1' then
sram_data <= (others => 'Z');
else
sram_data <= memory(to_integer(unsigned(SRAM_ADDR)));
end if;
end process read_proc;
write_proc: process(SRAM_we,SRAM_addr)
begin
if SRAM_we = '0' then
memory(to_integer(unsigned(SRAM_ADDR))) <= sram_data;
end if;
end process write_proc;
-- Stimulus process
-- stim_proc: process
-- begin
-- -- hold reset state for 100 ns.
-- wait for 100 ns;
--
-- wait for CLK_period*10;
--
-- -- insert stimulus here
--
-- wait;
-- end process;
END;
| lgpl-3.0 | 23e54c0656dcbbf28c74d5f0b2a4188b | 0.598343 | 3.412565 | false | false | false | false |
MAV-RT-testbed/MAV-testbed | Syma_Ctrl_core_1.1/hdl/Syma_Ctrl_core_v1_1_S_AXI_INTR.vhd | 1 | 26,246 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Syma_Ctrl_core_v1_1_S_AXI_INTR is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 5;
-- Number of Interrupts
C_NUM_OF_INTR : integer := 1;
-- Each bit corresponds to Sensitivity of interrupt : 0 - EDGE, 1 - LEVEL
C_INTR_SENSITIVITY : std_logic_vector := x"FFFFFFFF";
-- Each bit corresponds to Sub-type of INTR: [0 - FALLING_EDGE, 1 - RISING_EDGE : if C_INTR_SENSITIVITY is EDGE(0)] and [ 0 - LEVEL_LOW, 1 - LEVEL_LOW : if C_INTR_SENSITIVITY is LEVEL(1) ]
C_INTR_ACTIVE_STATE : std_logic_vector := x"FFFFFFFF";
-- Sensitivity of IRQ: 0 - EDGE, 1 - LEVEL
C_IRQ_SENSITIVITY : integer := 1;
-- Sub-type of IRQ: [0 - FALLING_EDGE, 1 - RISING_EDGE : if C_IRQ_SENSITIVITY is EDGE(0)] and [ 0 - LEVEL_LOW, 1 - LEVEL_LOW : if C_IRQ_SENSITIVITY is LEVEL(1) ]
C_IRQ_ACTIVE_STATE : integer := 1
);
port (
-- Users to add ports here
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write address (issued by master, acceped by Slave)
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type. This signal indicates the
-- privilege and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
S_AXI_AWREADY : out std_logic;
-- Write data (issued by master, acceped by Slave)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the channel
-- is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address (issued by master, acceped by Slave)
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether the
-- transaction is a data access or an instruction access.
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
S_AXI_ARREADY : out std_logic;
-- Read data (issued by slave)
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the
-- read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is
-- signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic;
-- interrupt out port
irq : out std_logic
);
end Syma_Ctrl_core_v1_1_S_AXI_INTR;
architecture arch_imp of Syma_Ctrl_core_v1_1_S_AXI_INTR is
-- AXI4LITE signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
--------------------------------------------------
---- Signals for Interrupt register space
--------------------------------------------------
---- Number of Slave Registers 5
signal reg_global_intr_en :std_logic_vector(0 downto 0);
signal reg_intr_en :std_logic_vector(C_NUM_OF_INTR-1 downto 0);
signal reg_intr_sts :std_logic_vector(C_NUM_OF_INTR-1 downto 0);
signal reg_intr_ack :std_logic_vector(C_NUM_OF_INTR-1 downto 0);
signal reg_intr_pending :std_logic_vector(C_NUM_OF_INTR-1 downto 0);
signal intr_reg_rden :std_logic;
signal intr_reg_wren :std_logic;
signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal intr : std_logic;
signal s_irq : std_logic;
signal intr_all_ff : std_logic;
signal s_irq_lvl_ff:std_logic;
begin
-- I/O Connections assignments
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RVALID <= axi_rvalid;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- slave is ready to accept write address when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_awready <= '1';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1') then
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_wready <= '1';
else
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-- select byte enables of slave registers while writing.
-- These registers are cleared when reset (active low) is applied.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data.
intr_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVAintrLID ;
gen_intr_reg : for i in 0 to (C_NUM_OF_INTR - 1) generate
begin
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
reg_global_intr_en <= (others => '0');
else
if (intr_reg_wren = '1' and axi_awaddr(4 downto 2) = "000") then
reg_global_intr_en(0) <= S_AXI_WDATA(0);
end if;
end if;
end if;
end process;
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
reg_intr_en(i) <= '0';
else
if (intr_reg_wren = '1' and axi_awaddr(4 downto 2) = "001") then
reg_intr_en(i) <= S_AXI_WDATA(i);
end if;
end if;
end if;
end process;
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if (S_AXI_ARESETN = '0' or reg_intr_ack(i) = '1') then
reg_intr_sts(i) <= '0';
else
reg_intr_sts(i) <= det_intr(i);
end if;
end if;
end process;
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if (S_AXI_ARESETN = '0' or reg_intr_ack(i) = '1') then
reg_intr_ack(i) <= '0';
else
if (intr_reg_wren = '1' and axi_awaddr(4 downto 2) = "011") then
reg_intr_ack(i) <= S_AXI_WDATA(i);
end if;
end if;
end if;
end process;
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if (S_AXI_ARESETN = '0' or reg_intr_ack(i) = '1') then
reg_intr_pending(i) <= '0';
else
reg_intr_pending(i) <= reg_intr_sts(i) and reg_intr_en(i);
end if;
end if;
end process;
end generate gen_intr_reg;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_araddr <= (others => '1');
else
if (axi_arready = '0' and S_AXI_ARVALID = '1') then
-- indicates that the slave has acceped the valid read address
axi_arready <= '1';
-- Read Address latching
axi_araddr <= S_AXI_ARADDR;
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
-- Read data is accepted by the master
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and read logic generation
-- Slave register read enable is asserted when valid address is available
-- and the slave is ready to accept the read address.
intr_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
RDATA_INTR_NUM_32: if (C_NUM_OF_INTR=32) generate
begin
process (reg_global_intr_en, reg_intr_en, reg_intr_sts, reg_intr_ack, reg_intr_pending, axi_araddr, S_AXI_ARESETN, intr_reg_rden)
variable loc_addr :std_logic_vector(2 downto 0);
begin
if S_AXI_ARESETN = '0' then
reg_data_out <= (others => '0');
else
-- Address decoding for reading registers
loc_addr := axi_araddr(4 downto 2);
case loc_addr is
when "000" =>
reg_data_out <= x"0000000" & "000" & reg_global_intr_en(0);
when "001" =>
reg_data_out <= reg_intr_en;
when "010" =>
reg_data_out <= reg_intr_sts;
when "011" =>
reg_data_out <= reg_intr_ack;
when "100" =>
reg_data_out <= reg_intr_pending;
when others =>
reg_data_out <= (others => '0');
end case;
end if;
end process;
end generate RDATA_INTR_NUM_32;
RDATA_INTR_NUM_LESS_32: if (C_NUM_OF_INTR/=32) generate
begin
process (reg_global_intr_en, reg_intr_en, reg_intr_sts, reg_intr_ack, reg_intr_pending, axi_araddr, S_AXI_ARESETN, intr_reg_rden)
variable loc_addr :std_logic_vector(2 downto 0);
variable zero : std_logic_vector (C_S_AXI_DATA_WIDTH-C_NUM_OF_INTR-1 downto 0);
begin
if S_AXI_ARESETN = '0' then
reg_data_out <= (others => '0');
zero := (others=>'0');
else
zero := (others=>'0');
-- Address decoding for reading registers
loc_addr := axi_araddr(4 downto 2);
case loc_addr is
when "000" =>
reg_data_out <= x"0000000" & "000" & reg_global_intr_en(0);
when "001" =>
reg_data_out <= zero & reg_intr_en;
when "010" =>
reg_data_out <= zero & reg_intr_sts;
when "011" =>
reg_data_out <= zero & reg_intr_ack;
when "100" =>
reg_data_out <= zero & reg_intr_pending;
when others =>
reg_data_out <= (others => '0');
end case;
end if;
end process;
end generate RDATA_INTR_NUM_LESS_32;
-- Output register or memory read data
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' ) then
axi_rdata <= (others => '0');
else
if (intr_reg_rden = '1') then
-- When there is a valid read address (S_AXI_ARVALID) with
-- acceptance of read address by the slave (axi_arready),
-- output the read dada
-- Read address mux
axi_rdata <= reg_data_out; -- register read data
end if;
end if;
end if;
end process;
------------------------------------------------------
--Example code to generate user logic interrupts
--Note: The example code presented here is to show you one way of generating
-- interrupts from the user logic. This code snippet generates a level
-- triggered interrupt when the intr_counter_reg counts down to zero.
-- while intr_control_reg[0] is asserted. Deasserting the intr_control_reg[0]
-- disables the counter and clears the interrupt signal.
------------------------------------------------------
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0') then
s_irq_lvl <= '0';
s_irq_lvl_ff <= '0';
elsif (intr = '1' and reg_global_intr_en(0) = '1') then
s_irq_lvl <= '1';
s_irq_lvl_ff <= s_irq_lvl;
end if;
end if;
end process;
s_irq <= s_irq_lvl and (not s_irq_lvl_ff);
irq <= s_irq;
-- Add user logic here
-- User logic ends
end arch_imp;
| gpl-2.0 | d2c328c29d30334fa4784ca36a1e96ac | 0.403414 | 4.892078 | false | false | false | false |
INTI-CMNB/Lattuino_IP_Core | Work/lattuino_1_bl_8.vhdl | 1 | 11,235 | ------------------------------------------------------------------------------
---- ----
---- Single Port RAM that maps to a Xilinx/Lattice BRAM ----
---- ----
---- This file is part FPGA Libre project http://fpgalibre.sf.net/ ----
---- ----
---- Description: ----
---- This is a program memory for the AVR. It maps to a Xilinx/Lattice ----
---- BRAM. ----
---- This version can be modified by the CPU (i. e. SPM instruction) ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008-2017 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008-2017 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: SinglePortPM(Xilinx) (Entity and architecture) ----
---- File name: pm_s_rw.in.vhdl (template used) ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: work ----
---- Dependencies: IEEE.std_logic_1164 ----
---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ----
---- iCE40 (iCE40HX4K) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
---- iCEcube2.2016.02 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity lattuino_1_blPM_8 is
generic(
WORD_SIZE : integer:=16; -- Word Size
FALL_EDGE : std_logic:='0'; -- Ram clock falling edge
ADDR_W : integer:=13); -- Address Width
port(
clk_i : in std_logic;
addr_i : in std_logic_vector(ADDR_W-1 downto 0);
data_o : out std_logic_vector(WORD_SIZE-1 downto 0);
we_i : in std_logic;
data_i : in std_logic_vector(WORD_SIZE-1 downto 0));
end entity lattuino_1_blPM_8;
architecture Xilinx of lattuino_1_blPM_8 is
constant ROM_SIZE : natural:=2**ADDR_W;
type rom_t is array(natural range 0 to ROM_SIZE-1) of std_logic_vector(WORD_SIZE-1 downto 0);
signal addr_r : std_logic_vector(ADDR_W-1 downto 0);
signal rom : rom_t :=
(
3768 => x"c00e",
3769 => x"c01d",
3770 => x"c01c",
3771 => x"c01b",
3772 => x"c01a",
3773 => x"c019",
3774 => x"c018",
3775 => x"c017",
3776 => x"c016",
3777 => x"c015",
3778 => x"c014",
3779 => x"c013",
3780 => x"c012",
3781 => x"c011",
3782 => x"c010",
3783 => x"2411",
3784 => x"be1f",
3785 => x"e5cf",
3786 => x"e0d2",
3787 => x"bfde",
3788 => x"bfcd",
3789 => x"e020",
3790 => x"e6a0",
3791 => x"e0b0",
3792 => x"c001",
3793 => x"921d",
3794 => x"36a5",
3795 => x"07b2",
3796 => x"f7e1",
3797 => x"d036",
3798 => x"c125",
3799 => x"cfe0",
3800 => x"e081",
3801 => x"bb8f",
3802 => x"e681",
3803 => x"ee93",
3804 => x"e1a6",
3805 => x"e0b0",
3806 => x"99f1",
3807 => x"c00a",
3808 => x"9701",
3809 => x"09a1",
3810 => x"09b1",
3811 => x"9700",
3812 => x"05a1",
3813 => x"05b1",
3814 => x"f7b9",
3815 => x"e0e0",
3816 => x"e0f0",
3817 => x"9509",
3818 => x"ba1f",
3819 => x"b38e",
3820 => x"9508",
3821 => x"e091",
3822 => x"bb9f",
3823 => x"9bf0",
3824 => x"cffe",
3825 => x"ba1f",
3826 => x"bb8e",
3827 => x"e080",
3828 => x"e090",
3829 => x"9508",
3830 => x"dfe1",
3831 => x"3280",
3832 => x"f421",
3833 => x"e184",
3834 => x"dff2",
3835 => x"e180",
3836 => x"cff0",
3837 => x"9508",
3838 => x"93cf",
3839 => x"2fc8",
3840 => x"dfd7",
3841 => x"3280",
3842 => x"f439",
3843 => x"e184",
3844 => x"dfe8",
3845 => x"2f8c",
3846 => x"dfe6",
3847 => x"e180",
3848 => x"91cf",
3849 => x"cfe3",
3850 => x"91cf",
3851 => x"9508",
3852 => x"9abe",
3853 => x"e044",
3854 => x"e450",
3855 => x"e020",
3856 => x"e030",
3857 => x"b388",
3858 => x"2785",
3859 => x"bb88",
3860 => x"01c9",
3861 => x"9701",
3862 => x"f7f1",
3863 => x"5041",
3864 => x"f7c1",
3865 => x"e011",
3866 => x"dfbd",
3867 => x"3380",
3868 => x"f0c9",
3869 => x"3381",
3870 => x"f499",
3871 => x"dfb8",
3872 => x"3280",
3873 => x"f7c1",
3874 => x"e184",
3875 => x"dfc9",
3876 => x"e481",
3877 => x"dfc7",
3878 => x"e586",
3879 => x"dfc5",
3880 => x"e582",
3881 => x"dfc3",
3882 => x"e280",
3883 => x"dfc1",
3884 => x"e489",
3885 => x"dfbf",
3886 => x"e583",
3887 => x"dfbd",
3888 => x"e580",
3889 => x"c0c2",
3890 => x"3480",
3891 => x"f421",
3892 => x"dfa3",
3893 => x"dfa2",
3894 => x"dfbf",
3895 => x"cfe2",
3896 => x"3481",
3897 => x"f469",
3898 => x"df9d",
3899 => x"3880",
3900 => x"f411",
3901 => x"e082",
3902 => x"c029",
3903 => x"3881",
3904 => x"f411",
3905 => x"e081",
3906 => x"c025",
3907 => x"3882",
3908 => x"f511",
3909 => x"e182",
3910 => x"c021",
3911 => x"3482",
3912 => x"f429",
3913 => x"e1c4",
3914 => x"df8d",
3915 => x"50c1",
3916 => x"f7e9",
3917 => x"cfe8",
3918 => x"3485",
3919 => x"f421",
3920 => x"df87",
3921 => x"df86",
3922 => x"df85",
3923 => x"cfe0",
3924 => x"eb90",
3925 => x"0f98",
3926 => x"3093",
3927 => x"f2f0",
3928 => x"3585",
3929 => x"f439",
3930 => x"df7d",
3931 => x"9380",
3932 => x"0063",
3933 => x"df7a",
3934 => x"9380",
3935 => x"0064",
3936 => x"cfd5",
3937 => x"3586",
3938 => x"f439",
3939 => x"df74",
3940 => x"df73",
3941 => x"df72",
3942 => x"df71",
3943 => x"e080",
3944 => x"df95",
3945 => x"cfb0",
3946 => x"3684",
3947 => x"f009",
3948 => x"c039",
3949 => x"df6a",
3950 => x"9380",
3951 => x"0062",
3952 => x"df67",
3953 => x"9380",
3954 => x"0061",
3955 => x"9210",
3956 => x"0060",
3957 => x"df62",
3958 => x"3485",
3959 => x"f419",
3960 => x"9310",
3961 => x"0060",
3962 => x"c00a",
3963 => x"9180",
3964 => x"0063",
3965 => x"9190",
3966 => x"0064",
3967 => x"0f88",
3968 => x"1f99",
3969 => x"9390",
3970 => x"0064",
3971 => x"9380",
3972 => x"0063",
3973 => x"e0c0",
3974 => x"e0d0",
3975 => x"9180",
3976 => x"0061",
3977 => x"9190",
3978 => x"0062",
3979 => x"17c8",
3980 => x"07d9",
3981 => x"f008",
3982 => x"cfa7",
3983 => x"df48",
3984 => x"2f08",
3985 => x"df46",
3986 => x"9190",
3987 => x"0060",
3988 => x"91e0",
3989 => x"0063",
3990 => x"91f0",
3991 => x"0064",
3992 => x"1191",
3993 => x"c005",
3994 => x"921f",
3995 => x"2e00",
3996 => x"2e18",
3997 => x"95e8",
3998 => x"901f",
3999 => x"9632",
4000 => x"93f0",
4001 => x"0064",
4002 => x"93e0",
4003 => x"0063",
4004 => x"9622",
4005 => x"cfe1",
4006 => x"3784",
4007 => x"f009",
4008 => x"c03e",
4009 => x"df2e",
4010 => x"9380",
4011 => x"0062",
4012 => x"df2b",
4013 => x"9380",
4014 => x"0061",
4015 => x"9210",
4016 => x"0060",
4017 => x"df26",
4018 => x"3485",
4019 => x"f419",
4020 => x"9310",
4021 => x"0060",
4022 => x"c00a",
4023 => x"9180",
4024 => x"0063",
4025 => x"9190",
4026 => x"0064",
4027 => x"0f88",
4028 => x"1f99",
4029 => x"9390",
4030 => x"0064",
4031 => x"9380",
4032 => x"0063",
4033 => x"df16",
4034 => x"3280",
4035 => x"f009",
4036 => x"cf55",
4037 => x"e184",
4038 => x"df26",
4039 => x"e0c0",
4040 => x"e0d0",
4041 => x"9180",
4042 => x"0061",
4043 => x"9190",
4044 => x"0062",
4045 => x"17c8",
4046 => x"07d9",
4047 => x"f528",
4048 => x"9180",
4049 => x"0060",
4050 => x"2388",
4051 => x"f011",
4052 => x"e080",
4053 => x"c005",
4054 => x"91e0",
4055 => x"0063",
4056 => x"91f0",
4057 => x"0064",
4058 => x"9184",
4059 => x"df11",
4060 => x"9180",
4061 => x"0063",
4062 => x"9190",
4063 => x"0064",
4064 => x"9601",
4065 => x"9390",
4066 => x"0064",
4067 => x"9380",
4068 => x"0063",
4069 => x"9621",
4070 => x"cfe2",
4071 => x"3785",
4072 => x"f479",
4073 => x"deee",
4074 => x"3280",
4075 => x"f009",
4076 => x"cf2d",
4077 => x"e184",
4078 => x"defe",
4079 => x"e18e",
4080 => x"defc",
4081 => x"e983",
4082 => x"defa",
4083 => x"e08b",
4084 => x"def8",
4085 => x"e180",
4086 => x"def6",
4087 => x"cf22",
4088 => x"3786",
4089 => x"f009",
4090 => x"cf1f",
4091 => x"cf6b",
4092 => x"94f8",
4093 => x"cfff",
others => x"0000"
);
begin
use_rising_edge:
if FALL_EDGE='0' generate
do_rom:
process (clk_i)
begin
if rising_edge(clk_i)then
addr_r <= addr_i;
if we_i='1' then
rom(to_integer(unsigned(addr_i))) <= data_i;
end if;
end if;
end process do_rom;
end generate use_rising_edge;
use_falling_edge:
if FALL_EDGE='1' generate
do_rom:
process (clk_i)
begin
if falling_edge(clk_i)then
addr_r <= addr_i;
if we_i='1' then
rom(to_integer(unsigned(addr_i))) <= data_i;
end if;
end if;
end process do_rom;
end generate use_falling_edge;
data_o <= rom(to_integer(unsigned(addr_r)));
end architecture Xilinx; -- Entity: lattuino_1_blPM_8
| gpl-2.0 | 5a9c24a93edfbc97f92d922b57259bf7 | 0.409702 | 2.86242 | false | false | false | false |
airabinovich/finalArquitectura | TestDatapathPart1/PipeAndDebug/ipcore_dir/RAM/example_design/RAM_prod.vhd | 2 | 10,054 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: RAM_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan6
-- C_XDEVICEFAMILY : spartan6
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 0
-- C_BYTE_SIZE : 8
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 0
-- C_INIT_FILE_NAME : no_coe_file_loaded
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 1
-- C_WEA_WIDTH : 4
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 32
-- C_READ_WIDTH_A : 32
-- C_WRITE_DEPTH_A : 256
-- C_READ_DEPTH_A : 256
-- C_ADDRA_WIDTH : 8
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 1
-- C_WEB_WIDTH : 4
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 32
-- C_READ_WIDTH_B : 32
-- C_WRITE_DEPTH_B : 256
-- C_READ_DEPTH_B : 256
-- C_ADDRB_WIDTH : 8
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY RAM_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END RAM_prod;
ARCHITECTURE xilinx OF RAM_prod IS
COMPONENT RAM_exdes IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : RAM_exdes
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
| lgpl-2.1 | f98fde1c5cc15035e91c7083bdc55374 | 0.492043 | 3.833016 | false | false | false | false |
MAV-RT-testbed/MAV-testbed | Syma_Flight_Final/Syma_Flight_Final.srcs/sources_1/ipshared/rcs.ei.tum.de/Syma_Ctrl_core_v1_2/5d78a94c/hdl/Syma_Ctrl_core_v1_1_M01_AXI.vhd | 2 | 50,340 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Syma_Ctrl_Core_v1_1_M01_AXI is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- The master will start generating data from the C_M_START_DATA_VALUE value
C_M_START_DATA_VALUE : std_logic_vector := x"AA000000";
-- The master requires a target slave base address.
-- The master will initiate read and write transactions on the slave with base address specified here as a parameter.
C_M_TARGET_SLAVE_BASE_ADDR : std_logic_vector := x"44A0_0000";
-- Width of M_AXI address bus.
-- The master generates the read and write addresses of width specified as C_M_AXI_ADDR_WIDTH.
C_M_AXI_ADDR_WIDTH : integer := 32;
-- Width of M_AXI data bus.
-- The master issues write data and accept read data where the width of the data bus is C_M_AXI_DATA_WIDTH
C_M_AXI_DATA_WIDTH : integer := 32;
-- Transaction number is the number of write
-- and read transactions the master will perform as a part of this example memory test.
C_M_TRANSACTIONS_NUM : integer := 1
);
port (
-- Users to add ports here
-- User ports ends
-- Do not modify the ports beyond this line
-- Initiate AXI transactions
INIT_AXI_TXN : in std_logic;
-- Asserts when ERROR is detected
ERROR : out std_logic;
-- Asserts when AXI transactions is complete
TXN_DONE : out std_logic;
-- AXI clock signal
M_AXI_ACLK : in std_logic;
-- AXI active low reset signal
M_AXI_ARESETN : in std_logic;
-- Master Interface Write Address Channel ports. Write address (issued by master)
M_AXI_AWADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type.
-- This signal indicates the privilege and security level of the transaction,
-- and whether the transaction is a data access or an instruction access.
M_AXI_AWPROT : out std_logic_vector(2 downto 0);
-- Write address valid.
-- This signal indicates that the master signaling valid write address and control information.
M_AXI_AWVALID : out std_logic;
-- Write address ready.
-- This signal indicates that the slave is ready to accept an address and associated control signals.
M_AXI_AWREADY : in std_logic;
-- Master Interface Write Data Channel ports. Write data (issued by master)
M_AXI_WDATA : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes.
-- This signal indicates which byte lanes hold valid data.
-- There is one write strobe bit for each eight bits of the write data bus.
M_AXI_WSTRB : out std_logic_vector(C_M_AXI_DATA_WIDTH/8-1 downto 0);
-- Write valid. This signal indicates that valid write data and strobes are available.
M_AXI_WVALID : out std_logic;
-- Write ready. This signal indicates that the slave can accept the write data.
M_AXI_WREADY : in std_logic;
-- Master Interface Write Response Channel ports.
-- This signal indicates the status of the write transaction.
M_AXI_BRESP : in std_logic_vector(1 downto 0);
-- Write response valid.
-- This signal indicates that the channel is signaling a valid write response
M_AXI_BVALID : in std_logic;
-- Response ready. This signal indicates that the master can accept a write response.
M_AXI_BREADY : out std_logic;
-- Master Interface Read Address Channel ports. Read address (issued by master)
M_AXI_ARADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type.
-- This signal indicates the privilege and security level of the transaction,
-- and whether the transaction is a data access or an instruction access.
M_AXI_ARPROT : out std_logic_vector(2 downto 0);
-- Read address valid.
-- This signal indicates that the channel is signaling valid read address and control information.
M_AXI_ARVALID : out std_logic;
-- Read address ready.
-- This signal indicates that the slave is ready to accept an address and associated control signals.
M_AXI_ARREADY : in std_logic;
-- Master Interface Read Data Channel ports. Read data (issued by slave)
M_AXI_RDATA : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the read transfer.
M_AXI_RRESP : in std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is signaling the required read data.
M_AXI_RVALID : in std_logic;
-- Read ready. This signal indicates that the master can accept the read data and response information.
M_AXI_RREADY : out std_logic;
-- SPI data. Data to be sent over the SPI interface
M_AXI_SPI_DATA : in std_logic_vector(7 downto 0);
-- SPI address offset. The address offset of the SPI-Core register to be written to
M_AXI_SPI_ADDR : in std_logic_vector(7 downto 0)
);
end Syma_Ctrl_Core_v1_1_M01_AXI;
architecture implementation of Syma_Ctrl_Core_v1_1_M01_AXI is
-- function called clogb2 that returns an integer which has the
-- value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
-- Example user application signals
-- TRANS_NUM_BITS is the width of the index counter for
-- number of write or read transaction..
constant TRANS_NUM_BITS : integer := clogb2(C_M_TRANSACTIONS_NUM-1);
-- Example State machine to initialize counter, initialize write transactions,
-- initialize read transactions and comparison of read data with the
-- written data words.
type state is ( IDLE, -- This state initiates AXI4Lite transaction
-- after the state machine changes state to INIT_WRITE
-- when there is 0 to 1 transition on INIT_AXI_TXN
INIT_WRITE, -- This state initializes write transaction,
-- once writes are done, the state machine
-- changes state to INIT_READ
INIT_READ, -- This state initializes read transaction
-- once reads are done, the state machine
-- changes state to INIT_COMPARE
INIT_COMPARE);-- This state issues the status of comparison
-- of the written data with the read data
signal mst_exec_state : state ;
-- AXI4LITE signals
--write address valid
signal axi_awvalid : std_logic;
--write data valid
signal axi_wvalid : std_logic;
--read address valid
signal axi_arvalid : std_logic;
--read data acceptance
signal axi_rready : std_logic;
--write response acceptance
signal axi_bready : std_logic;
--write address
signal axi_awaddr : std_logic_vector(7 downto 0);
--write data
signal axi_wdata : std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
--read addresss
signal axi_araddr : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
--Asserts when there is a write response error
signal write_resp_error : std_logic;
--Asserts when there is a read response error
signal read_resp_error : std_logic;
--A pulse to initiate a write transaction
signal start_single_write : std_logic;
--A pulse to initiate a read transaction
signal start_single_read : std_logic;
--Asserts when a single beat write transaction is issued and remains asserted till the completion of write trasaction.
signal write_issued : std_logic;
--Asserts when a single beat read transaction is issued and remains asserted till the completion of read trasaction.
signal read_issued : std_logic;
--flag that marks the completion of write trasactions. The number of write transaction is user selected by the parameter C_M_TRANSACTIONS_NUM.
signal writes_done : std_logic;
--flag that marks the completion of read trasactions. The number of read transaction is user selected by the parameter C_M_TRANSACTIONS_NUM
signal reads_done : std_logic;
--The error register is asserted when any of the write response error, read response error or the data mismatch flags are asserted.
signal error_reg : std_logic;
--index counter to track the number of write transaction issued
signal write_index : std_logic_vector(TRANS_NUM_BITS downto 0);
--index counter to track the number of read transaction issued
signal read_index : std_logic_vector(TRANS_NUM_BITS downto 0);
--Expected read data used to compare with the read data.
signal expected_rdata : std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
--Flag marks the completion of comparison of the read data with the expected read data
signal compare_done : std_logic;
--This flag is asserted when there is a mismatch of the read data with the expected read data.
signal read_mismatch : std_logic;
--Flag is asserted when the write index reaches the last write transction number
signal last_write : std_logic;
--Flag is asserted when the read index reaches the last read transction number
signal last_read : std_logic;
signal init_txn_ff : std_logic;
signal init_txn_ff2 : std_logic;
signal init_txn_edge : std_logic;
signal init_txn_pulse : std_logic;
begin
-- I/O Connections assignments
--Adding the offset address to the base addr of the slave
M_AXI_AWADDR <= std_logic_vector (unsigned(C_M_TARGET_SLAVE_BASE_ADDR) + unsigned(axi_awaddr));
--AXI 4 write data
M_AXI_WDATA <= axi_wdata;
M_AXI_AWPROT <= "000";
M_AXI_AWVALID <= axi_awvalid;
--Write Data(W)
M_AXI_WVALID <= axi_wvalid;
--Set all byte strobes in this example
M_AXI_WSTRB <= "1111";
--Write Response (B)
M_AXI_BREADY <= axi_bready;
--Read Address (AR)
M_AXI_ARADDR <= std_logic_vector(unsigned(C_M_TARGET_SLAVE_BASE_ADDR) + unsigned(axi_araddr));
M_AXI_ARVALID <= axi_arvalid;
M_AXI_ARPROT <= "001";
--Read and Read Response (R)
M_AXI_RREADY <= axi_rready;
--Example design I/O
TXN_DONE <= compare_done;
init_txn_pulse <= ( not init_txn_ff2) and init_txn_ff;
--Generate a pulse to initiate AXI transaction.
process(M_AXI_ACLK)
begin
if (rising_edge (M_AXI_ACLK)) then
-- Initiates AXI transaction delay
if (M_AXI_ARESETN = '0' ) then
init_txn_ff <= '0';
init_txn_ff2 <= '0';
else
init_txn_ff <= INIT_AXI_TXN;
init_txn_ff2 <= init_txn_ff;
end if;
end if;
end process;
----------------------
--Write Address Channel
----------------------
-- The purpose of the write address channel is to request the address and
-- command information for the entire transaction. It is a single beat
-- of information.
-- Note for this example the axi_awvalid/axi_wvalid are asserted at the same
-- time, and then each is deasserted independent from each other.
-- This is a lower-performance, but simplier control scheme.
-- AXI VALID signals must be held active until accepted by the partner.
-- A data transfer is accepted by the slave when a master has
-- VALID data and the slave acknoledges it is also READY. While the master
-- is allowed to generated multiple, back-to-back requests by not
-- deasserting VALID, this design will add rest cycle for
-- simplicity.
-- Since only one outstanding transaction is issued by the user design,
-- there will not be a collision between a new request and an accepted
-- request on the same clock cycle.
process(M_AXI_ACLK)
begin
if (rising_edge (M_AXI_ACLK)) then
--Only VALID signals must be deasserted during reset per AXI spec
--Consider inverting then registering active-low reset for higher fmax
if (M_AXI_ARESETN = '0' or init_txn_pulse = '1') then
axi_awvalid <= '0';
else
--Signal a new address/data command is available by user logic
if (start_single_write = '1') then
axi_awvalid <= '1';
elsif (M_AXI_AWREADY = '1' and axi_awvalid = '1') then
--Address accepted by interconnect/slave (issue of M_AXI_AWREADY by slave)
axi_awvalid <= '0';
end if;
end if;
end if;
end process;
-- start_single_write triggers a new write
-- transaction. write_index is a counter to
-- keep track with number of write transaction
-- issued/initiated
process(M_AXI_ACLK)
begin
if (rising_edge (M_AXI_ACLK)) then
if (M_AXI_ARESETN = '0' or init_txn_pulse = '1') then
write_index <= (others => '0');
elsif (start_single_write = '1') then
-- Signals a new write address/ write data is
-- available by user logic
write_index <= std_logic_vector (unsigned(write_index) + 1);
end if;
end if;
end process;
----------------------
--Write Data Channel
----------------------
--The write data channel is for transfering the actual data.
--The data generation is speific to the example design, and
--so only the WVALID/WREADY handshake is shown here
process(M_AXI_ACLK)
begin
if (rising_edge (M_AXI_ACLK)) then
if (M_AXI_ARESETN = '0' or init_txn_pulse = '1' ) then
axi_wvalid <= '0';
else
if (start_single_write = '1') then
--Signal a new address/data command is available by user logic
axi_wvalid <= '1';
elsif (M_AXI_WREADY = '1' and axi_wvalid = '1') then
--Data accepted by interconnect/slave (issue of M_AXI_WREADY by slave)
axi_wvalid <= '0';
end if;
end if;
end if;
end process;
------------------------------
--Write Response (B) Channel
------------------------------
--The write response channel provides feedback that the write has committed
--to memory. BREADY will occur after both the data and the write address
--has arrived and been accepted by the slave, and can guarantee that no
--other accesses launched afterwards will be able to be reordered before it.
--The BRESP bit [1] is used indicate any errors from the interconnect or
--slave for the entire write burst. This example will capture the error.
--While not necessary per spec, it is advisable to reset READY signals in
--case of differing reset latencies between master/slave.
process(M_AXI_ACLK)
begin
if (rising_edge (M_AXI_ACLK)) then
if (M_AXI_ARESETN = '0' or init_txn_pulse = '1') then
axi_bready <= '0';
else
if (M_AXI_BVALID = '1' and axi_bready = '0') then
-- accept/acknowledge bresp with axi_bready by the master
-- when M_AXI_BVALID is asserted by slave
axi_bready <= '1';
elsif (axi_bready = '1') then
-- deassert after one clock cycle
axi_bready <= '0';
end if;
end if;
end if;
end process;
--Flag write errors
write_resp_error <= (axi_bready and M_AXI_BVALID and M_AXI_BRESP(1));
------------------------------
--Read Address Channel
------------------------------
--start_single_read triggers a new read transaction. read_index is a counter to
--keep track with number of read transaction issued/initiated
process(M_AXI_ACLK)
begin
if (rising_edge (M_AXI_ACLK)) then
if (M_AXI_ARESETN = '0' or init_txn_pulse = '1') then
read_index <= (others => '0');
else
if (start_single_read = '1') then
-- Signals a new read address is
-- available by user logic
read_index <= std_logic_vector (unsigned(read_index) + 1);
end if;
end if;
end if;
end process;
-- A new axi_arvalid is asserted when there is a valid read address
-- available by the master. start_single_read triggers a new read
-- transaction
process(M_AXI_ACLK)
begin
if (rising_edge (M_AXI_ACLK)) then
if (M_AXI_ARESETN = '0' or init_txn_pulse = '1') then
axi_arvalid <= '0';
else
if (start_single_read = '1') then
--Signal a new read address command is available by user logic
axi_arvalid <= '1';
elsif (M_AXI_ARREADY = '1' and axi_arvalid = '1') then
--RAddress accepted by interconnect/slave (issue of M_AXI_ARREADY by slave)
axi_arvalid <= '0';
end if;
end if;
end if;
end process;
----------------------------------
--Read Data (and Response) Channel
----------------------------------
--The Read Data channel returns the results of the read request
--The master will accept the read data by asserting axi_rready
--when there is a valid read data available.
--While not necessary per spec, it is advisable to reset READY signals in
--case of differing reset latencies between master/slave.
process(M_AXI_ACLK)
begin
if (rising_edge (M_AXI_ACLK)) then
if (M_AXI_ARESETN = '0' or init_txn_pulse = '1') then
axi_rready <= '1';
else
if (M_AXI_RVALID = '1' and axi_rready = '0') then
-- accept/acknowledge rdata/rresp with axi_rready by the master
-- when M_AXI_RVALID is asserted by slave
axi_rready <= '1';
elsif (axi_rready = '1') then
-- deassert after one clock cycle
axi_rready <= '0';
end if;
end if;
end if;
end process;
--Flag write errors
read_resp_error <= (axi_rready and M_AXI_RVALID and M_AXI_RRESP(1));
----------------------------------
--User Logic
----------------------------------
--Address/Data Stimulus
--Address/data pairs for this example. The read and write values should
--match.
--Modify these as desired for different address patterns.
-- Write Addresses
process(M_AXI_ACLK)
begin
if (rising_edge (M_AXI_ACLK)) then
if (M_AXI_ARESETN = '0' or init_txn_pulse = '1') then
axi_awaddr <= M_AXI_SPI_ADDR;
elsif (M_AXI_AWREADY = '1' and axi_awvalid = '1') then
-- Signals a new write address/ write data is
-- available by user logic
axi_awaddr <= (others => '0');
end if;
end if;
end process;
-- Read Addresses
process(M_AXI_ACLK)
begin
if (rising_edge (M_AXI_ACLK)) then
if (M_AXI_ARESETN = '0' or init_txn_pulse = '1' ) then
axi_araddr <= x"0000_0064";
elsif (M_AXI_ARREADY = '1' and axi_arvalid = '1') then
-- Signals a new write address/ write data is
-- available by user logic
axi_araddr <= x"0000_0064";
end if;
end if;
end process;
-- Write data
process(M_AXI_ACLK)
begin
if (rising_edge (M_AXI_ACLK)) then
if (M_AXI_ARESETN = '0' or init_txn_pulse = '1') then
axi_wdata <= x"00_00_00" & M_AXI_SPI_DATA;
elsif (M_AXI_WREADY = '1' and axi_wvalid = '1') then
-- Signals a new write address/ write data is
-- available by user logic
axi_wdata <= x"00_00_00" & M_AXI_SPI_DATA;
end if;
end if;
end process;
-- Expected read data
process(M_AXI_ACLK)
begin
if (rising_edge (M_AXI_ACLK)) then
if (M_AXI_ARESETN = '0' or init_txn_pulse = '1' ) then
expected_rdata <= C_M_START_DATA_VALUE;
elsif (M_AXI_RVALID = '1' and axi_rready = '1') then
-- Signals a new write address/ write data is
-- available by user logic
expected_rdata <= std_logic_vector (unsigned(C_M_START_DATA_VALUE) + unsigned(read_index));
end if;
end if;
end process;
--implement master command interface state machine
MASTER_EXECUTION_PROC:process(M_AXI_ACLK)
begin
if (rising_edge (M_AXI_ACLK)) then
if (M_AXI_ARESETN = '0' ) then
-- reset condition
-- All the signals are ed default values under reset condition
mst_exec_state <= IDLE;
start_single_write <= '0';
write_issued <= '0';
start_single_read <= '0';
read_issued <= '0';
compare_done <= '0';
ERROR <= '0';
else
-- state transition
case (mst_exec_state) is
when IDLE =>
-- This state is responsible to initiate
-- AXI transaction when init_txn_pulse is asserted
if ( init_txn_pulse = '1') then
mst_exec_state <= INIT_WRITE;
ERROR <= '0';
compare_done <= '0';
else
mst_exec_state <= IDLE;
end if;
when INIT_WRITE =>
-- This state is responsible to issue start_single_write pulse to
-- initiate a write transaction. Write transactions will be
-- issued until last_write signal is asserted.
-- write controller
if (writes_done = '1') then
mst_exec_state <= INIT_READ;
else
mst_exec_state <= INIT_WRITE;
if (axi_awvalid = '0' and axi_wvalid = '0' and M_AXI_BVALID = '0' and
last_write = '0' and start_single_write = '0' and write_issued = '0') then
start_single_write <= '1';
write_issued <= '1';
elsif (axi_bready = '1') then
write_issued <= '0';
else
start_single_write <= '0'; --Negate to generate a pulse
end if;
end if;
when INIT_READ =>
-- This state is responsible to issue start_single_read pulse to
-- initiate a read transaction. Read transactions will be
-- issued until last_read signal is asserted.
-- read controller
if (reads_done = '1') then
mst_exec_state <= INIT_COMPARE;
else
mst_exec_state <= INIT_READ;
if (axi_arvalid = '0' and M_AXI_RVALID = '0' and last_read = '0' and
start_single_read = '0' and read_issued = '0') then
start_single_read <= '1';
read_issued <= '1';
elsif (axi_rready = '1') then
read_issued <= '0';
else
start_single_read <= '0'; --Negate to generate a pulse
end if;
end if;
when INIT_COMPARE =>
-- This state is responsible to issue the state of comparison
-- of written data with the read data. If no error flags are set,
-- compare_done signal will be asseted to indicate success.
ERROR <= error_reg;
mst_exec_state <= IDLE;
compare_done <= '1';
when others =>
mst_exec_state <= IDLE;
end case ;
end if;
end if;
end process;
--Terminal write count
process(M_AXI_ACLK)
begin
if (rising_edge (M_AXI_ACLK)) then
if (M_AXI_ARESETN = '0' or init_txn_pulse = '1') then
-- reset condition
last_write <= '0';
else
--The last write should be associated with a write address ready response
if (write_index = STD_LOGIC_VECTOR(TO_UNSIGNED(C_M_TRANSACTIONS_NUM, TRANS_NUM_BITS+1)) and M_AXI_AWREADY = '1') then
last_write <= '1';
end if;
end if;
end if;
end process;
--/*
-- Check for last write completion.
--
-- This logic is to qualify the last write count with the final write
-- response. This demonstrates how to confirm that a write has been
-- committed.
-- */
process(M_AXI_ACLK)
begin
if (rising_edge (M_AXI_ACLK)) then
if (M_AXI_ARESETN = '0' or init_txn_pulse = '1') then
-- reset condition
writes_done <= '0';
else
if (last_write = '1' and M_AXI_BVALID = '1' and axi_bready = '1') then
--The writes_done should be associated with a bready response
writes_done <= '1';
end if;
end if;
end if;
end process;
--------------
--Read example
--------------
--Terminal Read Count
process(M_AXI_ACLK)
begin
if (rising_edge (M_AXI_ACLK)) then
if (M_AXI_ARESETN = '0' or init_txn_pulse = '1') then
last_read <= '0';
else
if (read_index = STD_LOGIC_VECTOR(TO_UNSIGNED(C_M_TRANSACTIONS_NUM, TRANS_NUM_BITS+1)) and (M_AXI_ARREADY = '1') ) then
--The last read should be associated with a read address ready response
last_read <= '1';
end if;
end if;
end if;
end process;
--/*
-- Check for last read completion.
--
-- This logic is to qualify the last read count with the final read
-- response/data.
-- */
process(M_AXI_ACLK)
begin
if (rising_edge (M_AXI_ACLK)) then
if (M_AXI_ARESETN = '0' or init_txn_pulse = '1') then
reads_done <= '0';
else
if (last_read = '1' and M_AXI_RVALID = '1' and axi_rready = '1') then
--The reads_done should be associated with a read ready response
reads_done <= '1';
end if;
end if;
end if;
end process;
------------------------------/
--Example design error register
------------------------------/
--Data Comparison
process(M_AXI_ACLK)
begin
if (rising_edge (M_AXI_ACLK)) then
if (M_AXI_ARESETN = '0' or init_txn_pulse = '1') then
read_mismatch <= '0';
else
if ((M_AXI_RVALID = '1' and axi_rready = '1') and M_AXI_RDATA /= expected_rdata) then
--The read data when available (on axi_rready) is compared with the expected data
read_mismatch <= '1';
end if;
end if;
end if;
end process;
-- Register and hold any data mismatches, or read/write interface errors
process(M_AXI_ACLK)
begin
if (rising_edge (M_AXI_ACLK)) then
if (M_AXI_ARESETN = '0' or init_txn_pulse = '1') then
error_reg <= '0';
else
if (read_mismatch = '1' or write_resp_error = '1' or read_resp_error = '1') then
--Capture any error types
error_reg <= '1';
end if;
end if;
end if;
end process;
-- Add user logic here
-- User logic ends
end implementation; | gpl-2.0 | 9a9b13e4815528fe290748ef52ad2e58 | 0.321136 | 6.768858 | false | false | false | false |
jobisoft/jTDC | modules/VFB6/mez_disc16.vhdl | 1 | 27,985 | -------------------------------------------------------------------------
---- ----
---- Company : ELB-Elektroniklaboratorien Bonn UG ----
---- (haftungsbeschränkt) ----
---- ----
---- Description : Disc16T ----
---- ----
-------------------------------------------------------------------------
---- ----
---- Copyright (C) 2015 ELB ----
---- ----
---- This program is free software; you can redistribute it and/or ----
---- modify it under the terms of the GNU General Public License as ----
---- published by the Free Software Foundation; either version 3 of ----
---- the License, or (at your option) any later version. ----
---- ----
---- This program is distributed in the hope that it will be useful, ----
---- but WITHOUT ANY WARRANTY; without even the implied warranty of ----
---- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ----
---- GNU General Public License for more details. ----
---- ----
---- You should have received a copy of the GNU General Public ----
---- License along with this program; if not, see ----
---- <http://www.gnu.org/licenses>. ----
---- ----
-------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL; -- needed to be able to do math
library UNISIM;
use UNISIM.VComponents.all;
entity mez_disc16 is
Generic (mybaseaddress: natural := 16#0000#; use_clk_buf: STD_LOGIC_VECTOR (15 downto 0) := (others=>'0'));
Port (databus : inout STD_LOGIC_VECTOR (31 downto 0) := (others=>'Z');
addressbus : in STD_LOGIC_VECTOR (15 downto 0);
writesignal : in STD_LOGIC;
readsignal : in STD_LOGIC;
CLK : in STD_LOGIC;
Discriminator_Channel : out STD_LOGIC_VECTOR (16 downto 1);
MEZ : inout STD_LOGIC_VECTOR (79 downto 0) := (others=>'Z'));
end mez_disc16;
architecture Behavioral of mez_disc16 is
-- IO ports
Signal DiscP, DiscN : STD_LOGIC_VECTOR(16 downto 1);
Signal Channel : STD_LOGIC_VECTOR (16 downto 1) := (others=>'0');
-- ELBDISC16T wires
signal DAC_SDI, DAC_SCLK, DAC_CS : STD_LOGIC_VECTOR(2 downto 1) := "11";
signal DAC_SDO : STD_LOGIC_VECTOR(2 downto 1) := "11";
signal HDAC_CLK, HDAC_Load, HDAC_SDI : STD_LOGIC_VECTOR(2 downto 1) := "11";
signal ADC_SDO, ADC_CLK : STD_LOGIC;
signal ADC_F0 : std_logic;
signal ADC_CS : std_logic;
signal DAC_WAKEUP : std_logic_vector(2 downto 1);
signal DAC_LDAC : std_logic_vector(2 downto 1);
signal DAC_Data_Format : std_logic_vector(2 downto 1);
signal DAC_RST : std_logic_vector(2 downto 1);
signal DAC_CLR : std_logic_vector(2 downto 1);
signal ID_MISO : STD_LOGIC;
signal ID_CS : STD_LOGIC:='1';
signal ID_CLK, ID_MOSI : STD_LOGIC:='0';
ATTRIBUTE OUT_TERM: STRING;
ATTRIBUTE OUT_TERM of ADC_F0 : SIGNAL is "UNTUNED_50";
ATTRIBUTE OUT_TERM of ADC_CS : SIGNAL is "UNTUNED_50";
ATTRIBUTE OUT_TERM of DAC_SDI : SIGNAL is "UNTUNED_50";
ATTRIBUTE OUT_TERM of DAC_WAKEUP : SIGNAL is "UNTUNED_50";
ATTRIBUTE OUT_TERM of DAC_LDAC : SIGNAL is "UNTUNED_50";
ATTRIBUTE OUT_TERM of DAC_CLR : SIGNAL is "UNTUNED_50";
ATTRIBUTE OUT_TERM of DAC_RST : SIGNAL is "UNTUNED_50";
ATTRIBUTE OUT_TERM of DAC_SCLK : SIGNAL is "UNTUNED_50";
ATTRIBUTE OUT_TERM of DAC_Data_Format : SIGNAL is "UNTUNED_50";
ATTRIBUTE OUT_TERM of DAC_CS : SIGNAL is "UNTUNED_50";
ATTRIBUTE OUT_TERM of HDAC_CLK : SIGNAL is "UNTUNED_50";
ATTRIBUTE OUT_TERM of HDAC_SDI : SIGNAL is "UNTUNED_50";
ATTRIBUTE OUT_TERM of HDAC_Load : SIGNAL is "UNTUNED_50";
--new firmware
ATTRIBUTE OUT_TERM of ID_CS : SIGNAL is "UNTUNED_50";
ATTRIBUTE OUT_TERM of ID_CLK : SIGNAL is "UNTUNED_50";
ATTRIBUTE OUT_TERM of ID_MOSI : SIGNAL is "UNTUNED_50";
--for mode 1: automatic digitizing of all channels:
signal Enable_Automatic_Measurement : STD_LOGIC := '1';
--Signal discriminator_channel : STD_LOGIC_VECTOR (16 downto 1);
Signal THR1, THR2, THR3, THR4, THR5, THR6, THR7, THR8, THR9, THR10, THR11, THR12, THR13, THR14, THR15, THR16,
HYS1, HYS2, HYS3, HYS4, HYS5, HYS6, HYS7, HYS8, HYS9, HYS10, HYS11, HYS12, HYS13, HYS14, HYS15, HYS16,
DAC1_OFFSETA, DAC1_OFFSETB, DAC2_OFFSETA, DAC2_OFFSETB, DAC1_REFA, DAC1_REFB, DAC2_REFA, DAC2_REFB, DAC_GND : STD_LOGIC_VECTOR (15 downto 0) := X"DEAD";
-- for mode2: writing dac values
signal DAC_write_index : STD_LOGIC_VECTOR (4 downto 0) := "01110"; -- initial 0E -> error
signal DAC_write_value : STD_LOGIC_VECTOR (15 downto 0) := X"DEAD";
signal DAC_Write_enable : STD_LOGIC := '0';
-- for mode3: writing arbitrary dac registers:
signal ARB_W_WE1, ARB_W_WE2 : STD_LOGIC := '0';
signal ARB_W_ADDR : STD_LOGIC_VECTOR (4 downto 0) := "01110"; -- initial 0E -> error
signal ARB_W_Value : STD_LOGIC_VECTOR (15 downto 0) := X"DEAD";
-- for mode 4: read DAC register (complementary to mode 2)
signal DAC_Index_R : STD_LOGIC_VECTOR (4 downto 0); -- 0...15 =channels, 16..19 = offsetdacs
signal DAC_Value_R : STD_LOGIC_VECTOR (15 downto 0) := X"DEAD";-- output
signal DAC_Index_Read : STD_LOGIC_VECTOR (4 downto 0) := "11110"; -- index from witch value was read, initial 1E
signal RE_DAC_Register : STD_LOGIC; -- read command
signal RE_DAC_Reg_Valid : STD_LOGIC := '0'; -- data valid
--for mode 5: reading arbitrary register
signal ARB_R_Value1,ARB_R_Value2 : std_logic_vector(15 downto 0);
signal ARB_R_Valid1,ARB_R_Valid2 : std_logic;
signal ARB_R_Read_Addr1,ARB_R_Read_Addr2 : std_logic_vector(4 downto 0);
signal ARB_R_ADDR : std_logic_vector(4 downto 0);
signal ARB_R_RD1,ARB_R_RD2 : std_logic;
-- for mode 6: read arbitragy analog channel
signal RAA_WR : STD_LOGIC := '0'; -- write command
signal RAA_Index: STD_LOGIC_VECTOR (5 downto 0) := "001110";-- channel that has to be digitized.
signal RAA_Value : STD_LOGIC_VECTOR (15 downto 0) := X"DEAD"; -- measured value
signal RAA_Valid : STD_LOGIC := '0'; -- data valid
signal RAA_read_index : STD_LOGIC_VECTOR (5 downto 0); -- channel which was read
-- for hysteresis setting:
signal HDAC_Data : STD_LOGIC_VECTOR (7 downto 0);
signal HDAC_Channel : STD_LOGIC_VECTOR (4 downto 0);
signal HDAC_WE : STD_LOGIC;
signal HDAC_INIT : STD_LOGIC;
signal HDAC_Busy : STD_LOGIC;
-- new Busy-flag
signal TDAC_ADC_Busy : STD_LOGIC;
--new ID function
signal DeviceID : STD_LOGIC_VECTOR (47 downto 0);
signal ReadID : STD_LOGIC;
-- adc frequency selection:
signal ADC_Frequency : std_logic_vector(15 downto 0) := X"0030";
-- initializatin command:
signal initialize_DACs : STD_LOGIC := '1'; -- '1' to initialize dacs on powerup
COMPONENT Disc16T_ADC_DAC_Controller
PORT(
CLK : IN std_logic;
initialize_DACs : in STD_LOGIC;
Enable_Automatic_Measurement : IN std_logic;
DAC_Index_W : IN std_logic_vector(4 downto 0);
DAC_Value_W : IN std_logic_vector(15 downto 0);
WE_DAC_Register : IN std_logic;
--ARB_W_DAC1 : IN std_logic;
ARB_W_ADDR : IN std_logic_vector(4 downto 0);
ARB_W_Value : IN std_logic_vector(15 downto 0);
ARB_W_WE1, ARB_W_WE2 : IN std_logic;
DAC_Index_R : IN std_logic_vector(4 downto 0);
RE_DAC_Register : IN std_logic;
ARB_R_ADDR : IN std_logic_vector(4 downto 0);
ARB_R_RD1,ARB_R_RD2 : IN std_logic;
--new in/out for missing ELB_DISK16T
ADC_Frequency : in std_logic_vector(15 downto 0);
DAC_SDI, DAC_SCLK, DAC_CS : out STD_LOGIC_VECTOR(2 downto 1) ;
DAC_SDO : in STD_LOGIC_VECTOR(2 downto 1) ;
HDAC_CLK, HDAC_Load, HDAC_SDI : out STD_LOGIC_VECTOR(2 downto 1) ;
ADC_SDO, ADC_CLK : in STD_LOGIC;
ADC_F0 : OUT std_logic;
ADC_CS : OUT std_logic;
DAC_WAKEUP : OUT std_logic_vector(2 downto 1);
DAC_LDAC : OUT std_logic_vector(2 downto 1);
DAC_Data_Format : OUT std_logic_vector(2 downto 1);
DAC_RST : OUT std_logic_vector(2 downto 1);
DAC_CLR : OUT std_logic_vector(2 downto 1);
-- new firmware addition: ID readout
ID_MISO : IN STD_LOGIC;
ID_CS : OUT STD_LOGIC:='1';
ID_CLK, ID_MOSI : OUT STD_LOGIC:='0';
--
THR1 : OUT std_logic_vector(15 downto 0);
THR2 : OUT std_logic_vector(15 downto 0);
THR3 : OUT std_logic_vector(15 downto 0);
THR4 : OUT std_logic_vector(15 downto 0);
THR5 : OUT std_logic_vector(15 downto 0);
THR6 : OUT std_logic_vector(15 downto 0);
THR7 : OUT std_logic_vector(15 downto 0);
THR8 : OUT std_logic_vector(15 downto 0);
THR9 : OUT std_logic_vector(15 downto 0);
THR10 : OUT std_logic_vector(15 downto 0);
THR11 : OUT std_logic_vector(15 downto 0);
THR12 : OUT std_logic_vector(15 downto 0);
THR13 : OUT std_logic_vector(15 downto 0);
THR14 : OUT std_logic_vector(15 downto 0);
THR15 : OUT std_logic_vector(15 downto 0);
THR16 : OUT std_logic_vector(15 downto 0);
HYS1 : OUT std_logic_vector(15 downto 0);
HYS2 : OUT std_logic_vector(15 downto 0);
HYS3 : OUT std_logic_vector(15 downto 0);
HYS4 : OUT std_logic_vector(15 downto 0);
HYS5 : OUT std_logic_vector(15 downto 0);
HYS6 : OUT std_logic_vector(15 downto 0);
HYS7 : OUT std_logic_vector(15 downto 0);
HYS8 : OUT std_logic_vector(15 downto 0);
HYS9 : OUT std_logic_vector(15 downto 0);
HYS10 : OUT std_logic_vector(15 downto 0);
HYS11 : OUT std_logic_vector(15 downto 0);
HYS12 : OUT std_logic_vector(15 downto 0);
HYS13 : OUT std_logic_vector(15 downto 0);
HYS14 : OUT std_logic_vector(15 downto 0);
HYS15 : OUT std_logic_vector(15 downto 0);
HYS16 : OUT std_logic_vector(15 downto 0);
DAC1_OFFSETA : OUT std_logic_vector(15 downto 0);
DAC1_OFFSETB : OUT std_logic_vector(15 downto 0);
DAC2_OFFSETA : OUT std_logic_vector(15 downto 0);
DAC2_OFFSETB : OUT std_logic_vector(15 downto 0);
DAC1_REFA : OUT std_logic_vector(15 downto 0);
DAC1_REFB : OUT std_logic_vector(15 downto 0);
DAC2_REFA : OUT std_logic_vector(15 downto 0);
DAC2_REFB : OUT std_logic_vector(15 downto 0);
DAC_GND : OUT std_logic_vector(15 downto 0);
DAC_Value_R : OUT std_logic_vector(15 downto 0);
DAC_Index_Read : OUT std_logic_vector(4 downto 0);
RE_DAC_Reg_Valid : OUT std_logic;
ARB_R_Value1,ARB_R_Value2 : OUT std_logic_vector(15 downto 0);
ARB_R_Valid1,ARB_R_Valid2 : OUT std_logic;
ARB_R_Read_Addr1,ARB_R_Read_Addr2 : OUT std_logic_vector(4 downto 0);
--for hysteresis setting:
HDAC_Data : in STD_LOGIC_VECTOR (7 downto 0);
HDAC_Channel : in STD_LOGIC_VECTOR (4 downto 0);
HDAC_WE : in STD_LOGIC;
HDAC_INIT : in STD_LOGIC;
HDAC_Busy : OUT STD_LOGIC;
TDAC_ADC_Busy : out STD_LOGIC;
MuteChannelDuringTrhesholdChange : IN STD_LOGIC;
--new ID function
DeviceID : OUT STD_LOGIC_VECTOR (47 downto 0);
ReadID : in STD_LOGIC;
RAA_WR : in STD_LOGIC; -- write command
RAA_Index: in STD_LOGIC_VECTOR (5 downto 0);-- channel that has to be digitized.
RAA_Value : out STD_LOGIC_VECTOR (15 downto 0) := X"DEAD"; -- measured value
RAA_Valid : out STD_LOGIC := '0'; -- data valid
RAA_read_index : out STD_LOGIC_VECTOR (5 downto 0) := X"EDEAD" -- channel which was read
);
END COMPONENT;
begin
-----------------------------------------------------
---------- Instantiate all req. buffers -------------
-----------------------------------------------------
-- single outputs
OBUF_MEZ10 : OBUF generic map ( IOSTANDARD => "LVCMOS33") port map ( O => MEZ(10), I => ADC_F0 );
OBUF_MEZ11 : OBUF generic map ( IOSTANDARD => "LVCMOS33") port map ( O => MEZ(11), I => ADC_CS );
OBUF_MEZ25 : OBUF generic map ( IOSTANDARD => "LVCMOS33") port map ( O => MEZ(25), I => DAC_SDI(1) );
OBUF_MEZ23 : OBUF generic map ( IOSTANDARD => "LVCMOS33") port map ( O => MEZ(23), I => DAC_WAKEUP(1) );
OBUF_MEZ24 : OBUF generic map ( IOSTANDARD => "LVCMOS33") port map ( O => MEZ(24), I => DAC_LDAC(1) );
OBUF_MEZ26 : OBUF generic map ( IOSTANDARD => "LVCMOS33") port map ( O => MEZ(26), I => DAC_CLR(1) );
OBUF_MEZ27 : OBUF generic map ( IOSTANDARD => "LVCMOS33") port map ( O => MEZ(27), I => DAC_RST(1) );
OBUF_MEZ33 : OBUF generic map ( IOSTANDARD => "LVCMOS33") port map ( O => MEZ(33), I => DAC_SCLK(1) );
OBUF_MEZ36 : OBUF generic map ( IOSTANDARD => "LVCMOS33") port map ( O => MEZ(36), I => DAC_Data_Format(1) );
OBUF_MEZ37 : OBUF generic map ( IOSTANDARD => "LVCMOS33") port map ( O => MEZ(37), I => DAC_CS(1) );
OBUF_MEZ46 : OBUF generic map ( IOSTANDARD => "LVCMOS33") port map ( O => MEZ(46), I => DAC_SDI(2) );
OBUF_MEZ47 : OBUF generic map ( IOSTANDARD => "LVCMOS33") port map ( O => MEZ(47), I => DAC_SCLK(2) );
OBUF_MEZ50 : OBUF generic map ( IOSTANDARD => "LVCMOS33") port map ( O => MEZ(50), I => DAC_Data_Format(2) );
OBUF_MEZ68 : OBUF generic map ( IOSTANDARD => "LVCMOS33") port map ( O => MEZ(68), I => DAC_CLR(2) );
OBUF_MEZ69 : OBUF generic map ( IOSTANDARD => "LVCMOS33") port map ( O => MEZ(69), I => DAC_RST(2) );
OBUF_MEZ70 : OBUF generic map ( IOSTANDARD => "LVCMOS33") port map ( O => MEZ(70), I => DAC_WAKEUP(2) );
OBUF_MEZ71 : OBUF generic map ( IOSTANDARD => "LVCMOS33") port map ( O => MEZ(71), I => DAC_LDAC(2) );
OBUF_MEZ67 : OBUF generic map ( IOSTANDARD => "LVCMOS33") port map ( O => MEZ(67), I => DAC_CS(2) );
OBUF_MEZ28 : OBUF generic map ( IOSTANDARD => "LVCMOS33") port map ( O => MEZ(28), I => HDAC_SDI(1) );
OBUF_MEZ29 : OBUF generic map ( IOSTANDARD => "LVCMOS33") port map ( O => MEZ(29), I => HDAC_CLK(1) );
OBUF_MEZ30 : OBUF generic map ( IOSTANDARD => "LVCMOS33") port map ( O => MEZ(30), I => HDAC_Load(1) );
OBUF_MEZ51 : OBUF generic map ( IOSTANDARD => "LVCMOS33") port map ( O => MEZ(51), I => HDAC_Load(2) );
OBUF_MEZ52 : OBUF generic map ( IOSTANDARD => "LVCMOS33") port map ( O => MEZ(52), I => HDAC_CLK(2) );
OBUF_MEZ53 : OBUF generic map ( IOSTANDARD => "LVCMOS33") port map ( O => MEZ(53), I => HDAC_SDI(2) );
-- single inputs
IBUF_MEZ31 : IBUF generic map ( IOSTANDARD => "LVCMOS33") port map ( O => ADC_CLK, I => MEZ(31) );
IBUF_MEZ32 : IBUF generic map ( IOSTANDARD => "LVCMOS33") port map ( O => ADC_SDO, I => MEZ(32) );
IBUF_MEZ22 : IBUF generic map ( IOSTANDARD => "LVCMOS33") port map ( O => DAC_SDO(1), I => MEZ(22) );
IBUF_MEZ72 : IBUF generic map ( IOSTANDARD => "LVCMOS33") port map ( O => DAC_SDO(2), I => MEZ(72) );
-- new firmware outputs
OBUF_MEZ17 : OBUF generic map ( IOSTANDARD => "LVCMOS33") port map ( O => MEZ(17), I => ID_CS );
OBUF_MEZ61 : OBUF generic map ( IOSTANDARD => "LVCMOS33") port map ( O => MEZ(61), I => ID_CLK );
OBUF_MEZ60 : OBUF generic map ( IOSTANDARD => "LVCMOS33") port map ( O => MEZ(60), I => ID_MOSI );
-- new firmware inputs
IBUF_MEZ16 : IBUF generic map ( IOSTANDARD => "LVCMOS33") port map ( O => ID_MISO, I =>MEZ(16) );
-- differential inputs
DiscP(2) <= MEZ(0);
DiscN(2) <= MEZ(1);
DiscP(1) <= MEZ(2);
DiscN(1) <= MEZ(3);
DiscP(3) <= MEZ(4);
DiscN(3) <= MEZ(5);
DiscP(4) <= MEZ(6);
DiscN(4) <= MEZ(7);
DiscP(7) <= MEZ(12);
DiscN(7) <= MEZ(13);
DiscP(6) <= MEZ(14);
DiscN(6) <= MEZ(15);
DiscP(5) <= MEZ(18);
DiscN(5) <= MEZ(19);
DiscP(8) <= MEZ(34);
DiscN(8) <= MEZ(35);
DiscP(11) <= MEZ(40);
DiscN(11) <= MEZ(41);
DiscP(10) <= MEZ(42);
DiscN(10) <= MEZ(43);
DiscP(9) <= MEZ(44);
DiscN(9) <= MEZ(45);
DiscP(12) <= MEZ(48);
DiscN(12) <= MEZ(49);
DiscP(15) <= MEZ(54);
DiscN(15) <= MEZ(55);
DiscP(14) <= MEZ(56);
DiscN(14) <= MEZ(57);
DiscP(13) <= MEZ(58);
DiscN(13) <= MEZ(59);
DiscN(16) <= MEZ(79);
DiscP(16) <= MEZ(78);
buffers: for i in 1 to 16 generate
CLKBUF: if (use_clk_buf(i-1) = '1') generate -- clk bit is high
Disc_IBUFGDS: IBUFGDS
GENERIC MAP ( DIFF_TERM => TRUE, -- Differential Termination
IOSTANDARD => "LVPECL_25")
PORT MAP ( O => Channel(i),
I => DiscP(i),
IB => DiscN(i) );
Discriminator_Channel(i) <= Channel(i);
end generate CLKBUF;
DATABUF: if (use_clk_buf(i-1) = '0') generate -- clk bit is low
Disc_IBUFDS: IBUFDS
GENERIC MAP ( DIFF_TERM => TRUE, -- Differential Termination
IBUF_LOW_PWR => FALSE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "LVPECL_25")
PORT MAP ( O => Channel(i),
I => DiscP(i),
IB => DiscN(i) );
Discriminator_Channel(i) <= not Channel(i); -- signals in the pyhsical world are negative
end generate DATABUF;
end generate buffers;
-----------------------------------------------------
---------- Communication with VME interface ---------
-----------------------------------------------------
process (CLK) begin
if (rising_edge(CLK)) then
-- Set defaults
DAC_Write_enable <= '0';
ARB_W_WE1 <= '0';
ARB_W_WE2 <= '0';
HDAC_WE <= '0';
HDAC_Init <= '0';
RE_DAC_Register <= '0';
ARB_R_RD1 <= '0';
ARB_R_RD2 <= '0';
RAA_WR <= '0';
initialize_DACs <= '0';
ReadID <= '0';
-- Register write/read
-- do nothing by default
databus <= (others => 'Z');
case (addressbus) is -- addr arranged such an offset of 0x40 between differnt MEZ is sufficient -> read all THR in one row
when(mybaseaddress+X"0004") => -- initialization command
if(writesignal='1') then
initialize_DACs <= '1';
end if;
when(mybaseaddress+X"0008") => -- Set and Read ADC_Frequency
if(readsignal='1') then
databus(15 downto 0) <= ADC_Frequency;
elsif (writesignal='1') then
ADC_Frequency <= databus(15 downto 0);
end if;
when(mybaseaddress+X"000C") => -- Set and Read automatic measurement
if (writesignal='1') then
Enable_Automatic_Measurement <= databus(0);
elsif(readsignal='1') then
databus(0) <= Enable_Automatic_Measurement;
end if;
when (mybaseaddress+X"0010") => -- set dac value for index: 0= broadcast (=all channels), 1...16 =channels, 17..20 = offsetdacs(1a,1b,2a,2b)
if (writesignal='1') then
DAC_Write_enable <= '1';
DAC_write_index <= databus(20 downto 16);
DAC_write_value <= databus(15 downto 0);
elsif(readsignal='1') then
databus(20 downto 16) <= DAC_write_index;
databus(15 downto 0) <= DAC_write_value;
end if;
when(mybaseaddress+X"0014") => -- read digital written dac value (1. write desired index 2. readback value)
if(writesignal='1') then
RE_DAC_Register <= '1';
DAC_Index_R <= databus(20 downto 16);
elsif(readsignal='1') then
databus(15 downto 0) <= DAC_Value_R;
databus(20 downto 16) <= DAC_Index_Read;
databus(28) <= RE_DAC_Reg_Valid;
databus(24) <= RE_DAC_Reg_Valid;
end if;
when(mybaseaddress+X"0020") => -- write hysteresis dac
if(readsignal='1') then
databus(7 downto 0) <= HDAC_Data;
databus(12 downto 8) <= HDAC_Channel;
elsif(writesignal='1') then
if (databus(31)='1') then
HDAC_Init <= '1';
else
HDAC_Data <= databus(7 downto 0);
HDAC_Channel <= databus(12 downto 8);
HDAC_WE <= '1';
end if;
end if;
when(mybaseaddress+X"0030") => -- ARB WRITE
if(writesignal='1') then
ARB_W_WE1 <= '1';
ARB_W_WE2 <= '1';
ARB_W_ADDR <= databus(20 downto 16);
ARB_W_Value <= databus(15 downto 0);
end if;
when(mybaseaddress+X"0034") => -- ARB READ (write desired index)
if(writesignal='1') then
ARB_R_RD1 <= databus(24);
ARB_R_RD2 <= databus(28);
ARB_R_ADDR <= databus(20 downto 16);
end if;
when(mybaseaddress+X"0038") => -- ARB READ (read value1)
if(readsignal='1') then
databus(24) <= ARB_R_Valid1;
databus(20 downto 16) <= ARB_R_Read_Addr1;
databus(15 downto 0) <= ARB_R_Value1;
end if;
when(mybaseaddress+X"003C") => -- ARB READ (read value2)
if(readsignal='1') then
databus(28) <= ARB_R_Valid2;
databus(20 downto 16) <= ARB_R_Read_Addr2;
databus(15 downto 0) <= ARB_R_Value2;
end if;
when(mybaseaddress+X"0100") => -- analog readbacks of THR and HYS
if(readsignal='1') then
databus <= HYS1 & THR1;
end if;
when(mybaseaddress+X"0104") =>
if(readsignal='1') then
databus <= HYS2 & THR2;
end if;
when(mybaseaddress+X"0108") =>
if(readsignal='1') then
databus <= HYS3 & THR3;
end if;
when(mybaseaddress+X"010C") =>
if(readsignal='1') then
databus <= HYS4 & THR4;
end if;
when(mybaseaddress+X"0110") =>
if(readsignal='1') then
databus <= HYS5 & THR5;
end if;
when(mybaseaddress+X"0114") =>
if(readsignal='1') then
databus <= HYS6 & THR6;
end if;
when(mybaseaddress+X"0118") =>
if(readsignal='1') then
databus <= HYS7 & THR7;
end if;
when(mybaseaddress+X"011C") =>
if(readsignal='1') then
databus <= HYS8 & THR8;
end if;
when(mybaseaddress+X"0120") =>
if(readsignal='1') then
databus <= HYS9 & THR9;
end if;
when(mybaseaddress+X"0124") =>
if(readsignal='1') then
databus <= HYS10 & THR10;
end if;
when(mybaseaddress+X"0128") =>
if(readsignal='1') then
databus <= HYS11 & THR11;
end if;
when(mybaseaddress+X"012C") =>
if(readsignal='1') then
databus <= HYS12 & THR12;
end if;
when(mybaseaddress+X"0130") =>
if(readsignal='1') then
databus <= HYS13 & THR13;
end if;
when(mybaseaddress+X"0134") =>
if(readsignal='1') then
databus <= HYS14 & THR14;
end if;
when(mybaseaddress+X"0138") =>
if(readsignal='1') then
databus <= HYS15 & THR15;
end if;
when(mybaseaddress+X"013C") =>
if(readsignal='1') then
databus <= HYS16 & THR16;
end if;
when(mybaseaddress+X"0200") => -- other analog readbacks
if(readsignal='1') then
databus <= DAC1_OFFSETA & DAC1_OFFSETB;
end if;
when(mybaseaddress+X"0204") =>
if(readsignal='1') then
databus <= DAC2_OFFSETA & DAC2_OFFSETB;
end if;
when(mybaseaddress+X"0208") =>
if(readsignal='1') then
databus <= DAC1_REFA & DAC1_REFB;
end if;
when(mybaseaddress+X"020C") =>
if(readsignal='1') then
databus <= DAC2_REFA & DAC2_REFB;
end if;
when(mybaseaddress+X"0210") =>
if(readsignal='1') then
databus <= X"0000" & DAC_GND;
end if;
when(mybaseaddress+X"0220") => -- read arbitrary analog channel (1. Write desired index 2. Readback value)
if(writesignal='1') then
RAA_WR <= '1';
RAA_Index <= databus(21 downto 16);
elsif(readsignal='1') then
databus(15 downto 0) <= RAA_Value;
databus(21 downto 16) <= RAA_read_index;
databus(28) <= RAA_Valid;
databus(24) <= RAA_Valid;
end if;
when(mybaseaddress+X"0224") => -- (1. Write signal to Address 0x0224 2. Readback value from Address 0x0224 and 0x228)
if(writesignal='1') then
ReadID <= '1';
elsif(readsignal='1') then
databus(23 downto 0) <= DeviceID (23 downto 0);
end if;
when(mybaseaddress+X"0228") =>
if(writesignal='1') then
ReadID <= '1';
elsif(readsignal='1') then
databus(23 downto 0) <= DeviceID (47 downto 24);
end if;
when others => NULL;
end case;
end if;
end process;
Inst_Disc16T_ADC_DAC_Controller: Disc16T_ADC_DAC_Controller PORT MAP(
CLK => CLK,
ADC_Frequency => ADC_Frequency,
initialize_DACs=>initialize_DACs,
THR1 => THR1,
THR2 => THR2,
THR3 => THR3,
THR4 => THR4,
THR5 => THR5,
THR6 => THR6,
THR7 => THR7,
THR8 => THR8,
THR9 => THR9,
THR10 => THR10,
THR11 => THR11,
THR12 => THR12,
THR13 => THR13,
THR14 => THR14,
THR15 => THR15,
THR16 => THR16,
HYS1 => HYS1,
HYS2 => HYS2,
HYS3 => HYS3,
HYS4 => HYS4,
HYS5 => HYS5,
HYS6 => HYS6,
HYS7 => HYS7,
HYS8 => HYS8,
HYS9 => HYS9,
HYS10 => HYS10,
HYS11 => HYS11,
HYS12 => HYS12,
HYS13 => HYS13,
HYS14 => HYS14,
HYS15 => HYS15,
HYS16 => HYS16,
DAC1_OFFSETA => DAC1_OFFSETA,
DAC1_OFFSETB => DAC1_OFFSETB,
DAC2_OFFSETA => DAC2_OFFSETA,
DAC2_OFFSETB => DAC2_OFFSETB,
DAC1_REFA => DAC1_REFA,
DAC1_REFB => DAC1_REFB,
DAC2_REFA => DAC2_REFA,
DAC2_REFB => DAC2_REFB,
DAC_GND => DAC_GND,
Enable_Automatic_Measurement => Enable_Automatic_Measurement,
-- mode 2: write value in dac voltage register
DAC_Index_W =>DAC_write_index,
DAC_Value_W=>DAC_write_value,
we_dac_register=>DAC_Write_enable,
-- mode 3: write arbitraty DAC register
ARB_W_ADDR => ARB_W_ADDR,
ARB_W_Value => ARB_W_Value,
ARB_W_WE1 => ARB_W_WE1,
ARB_W_WE2 => ARB_W_WE2,
DAC_Index_R => DAC_Index_R,
DAC_Value_R => DAC_Value_R,
DAC_Index_Read=>DAC_Index_Read,
RE_DAC_Register => RE_DAC_Register,
RE_DAC_Reg_Valid => RE_DAC_Reg_Valid,
-- mode 5: arbitrary dac register read
ARB_R_Value1=>ARB_R_Value1,
ARB_R_Value2=>ARB_R_Value2,
ARB_R_Valid1=>ARB_R_Valid1,
ARB_R_Valid2=>ARB_R_Valid2,
ARB_R_Read_Addr1=>ARB_R_Read_Addr1,
ARB_R_Read_Addr2=>ARB_R_Read_Addr2,
ARB_R_ADDR=>ARB_R_ADDR,
ARB_R_RD1=>ARB_R_RD1,
ARB_R_RD2=>ARB_R_RD2,
-- for hysteresis setting:
HDAC_Data=>HDAC_Data,
HDAC_Channel=>HDAC_Channel,
HDAC_WE=>HDAC_WE,
HDAC_Init=>HDAC_Init,
HDAC_Busy=>HDAC_Busy,
DeviceID=>DeviceID,
ReadID=>ReadID,
MuteChannelDuringTrhesholdChange=>'0',
TDAC_ADC_Busy=>TDAC_ADC_Busy,
RAA_WR=>RAA_WR,
RAA_Index=>RAA_Index,
RAA_Value=>RAA_Value,
RAA_Valid=>RAA_Valid,
RAA_read_index=>RAA_read_index,
-- RAA_DAC1_Mux => (others=>'0'),
-- RAA_DAC2_Mux => (others=>'0'),
-- RAA_DAC1_IO => (others=>'0'),
-- RAA_DAC2_IO => (others=>'0'),
-- RAA_WR => '0',
-- RAA_Value =>open ,
-- RAA_Valid => open,
-- RAA_DAC1_Mux_V => open,
-- RAA_DAC2_Mux_V => open,
-- new in/out for missing ELB_DISK16
DAC_SDI => DAC_SDI,
DAC_SCLK => DAC_SCLK,
DAC_CS => DAC_CS,
DAC_SDO => DAC_SDO,
HDAC_CLK => HDAC_CLK,
HDAC_Load => HDAC_Load,
HDAC_SDI => HDAC_SDI,
ADC_SDO => ADC_SDO,
ADC_CLK => ADC_CLK,
ADC_F0 => ADC_F0,
ADC_CS => ADC_CS,
DAC_WAKEUP => DAC_WAKEUP,
DAC_LDAC => DAC_LDAC,
DAC_CLR => DAC_CLR,
DAC_RST => DAC_RST ,
DAC_Data_Format => DAC_Data_Format,
ID_MISO => ID_MISO,
ID_CS => ID_CS,
ID_CLK => ID_CLK,
ID_MOSI => ID_MOSI
);
end Behavioral;
| gpl-3.0 | e2ded63868817a171f7f714d22d3fc6e | 0.568646 | 3.034154 | false | false | false | false |
manosaloscables/vhdl | circuitos_secuenciales/sram_un_puerto/sram_up.vhd | 1 | 1,556 | -- ************************************
-- * RAM síncrona de un puerto Altera *
-- ************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sram_up is
generic(
DIR_ANCHO: integer:=2;
DATOS_ANCHO: integer:=8
);
port(
clk: in std_logic;
we: in std_logic; -- Activador de escritura
-- Dirección de memoria
dir: in std_logic_vector(DIR_ANCHO-1 downto 0);
-- Registros que reflejan cómo los módulos de memoria embebida están
-- empaquetados con una interfaz síncrona en los chips Cyclone.
d: in std_logic_vector(DATOS_ANCHO-1 downto 0);
q: out std_logic_vector(DATOS_ANCHO-1 downto 0)
);
end sram_up;
-- Arquitectura que registra la dirección de lectura
architecture arq_dir_reg of sram_up is
--------------------------------------------------------------------
-- Crear un tipo de datos de dos dimensiones definido por el usuario
type mem_tipo_2d is array (0 to 2**DIR_ANCHO-1)
of std_logic_vector (DATOS_ANCHO-1 downto 0);
signal sram: mem_tipo_2d;
--------------------------------------------------------------------
signal dir_reg: std_logic_vector(DIR_ANCHO-1 downto 0);
begin
process (clk)
begin
if (clk'event and clk = '1') then
if (we='1') then
sram(to_integer(unsigned(dir))) <= d;
end if;
dir_reg <= dir;
end if;
end process;
-- Salida
q <= sram(to_integer(unsigned(dir_reg)));
end arq_dir_reg;
| gpl-3.0 | f01f35d3f622ef22f5cf5e60a109fcbf | 0.53583 | 3.627635 | false | false | false | false |
rodrigofegui/UnB | 2017.1/Organização e Arquitetura de Computadores/Trabalhos/Projeto Final/Codificação/controleAlu.vhd | 2 | 1,680 | --Módulo para controle da ULA. Definirá a operação a ser realizada pela ula, e também identifica se deve ocorrer JR
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity controleAlu is
port(
funct : in std_logic_vector(5 downto 0);
ALUOp : in std_logic_vector(2 downto 0);
CTRLOut : out std_logic_vector(3 downto 0);
Jr : out std_logic
);
end controleAlu;
architecture Behavioral of controleAlu is
signal aux : std_logic_vector(3 downto 0);
begin
CTRLOut <= aux;
process (funct, ALUOp, aux)
begin
Jr <= '0';
case ALUOp is
when "000" => -- LW e SW
aux <= "0010"; -- ADD
when "001" => -- BEQ e BNE
aux <= "0011"; -- SUB
when "010" =>
case funct is
when "100000" =>
aux <= "0010"; -- ADD
when "100010" =>
aux <= "0011"; -- SUB
when "100100" =>
aux <= "0000"; -- AND
when "100101" =>
aux <= "0001"; -- OR
when "101010" =>
aux <= "0100"; -- SLT
when "100111" =>
aux <= "0101"; -- NOR
when "100110" =>
aux <= "0110"; -- XOR
when "000000" =>
aux <= "0111"; -- SLL
when "000010" =>
aux <= "1000"; -- SRL
when "000011" =>
aux <= "1001"; -- SRA
when "001000" => -- JR
Jr <= '1';
aux <= "1111";
when others =>
aux <= (others => 'X');
end case;
when "011" =>
aux <= "0010"; -- ADDI
when "100" =>
aux <= "0000"; --ANDI
when "101" =>
aux <= "0001"; --ORI
when "110" =>
aux <= "0110"; --XORI
when "111" =>
aux <= "0100"; --SLTI
when others =>
aux <= (others => 'X');
end case;
end process;
end Behavioral; | gpl-3.0 | ba026a38c5bf4f786561380aef0b09c1 | 0.512239 | 2.991071 | false | false | false | false |
jobisoft/jTDC | modules/register/toggle_register.vhdl | 1 | 3,022 | -------------------------------------------------------------------------
---- ----
---- Company: University of Bonn ----
---- Engineer: John Bieling ----
---- ----
-------------------------------------------------------------------------
---- ----
---- Copyright (C) 2015 John Bieling ----
---- ----
---- This program is free software; you can redistribute it and/or ----
---- modify it under the terms of the GNU General Public License as ----
---- published by the Free Software Foundation; either version 3 of ----
---- the License, or (at your option) any later version. ----
---- ----
---- This program is distributed in the hope that it will be useful, ----
---- but WITHOUT ANY WARRANTY; without even the implied warranty of ----
---- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ----
---- GNU General Public License for more details. ----
---- ----
---- You should have received a copy of the GNU General Public ----
---- License along with this program; if not, see ----
---- <http://www.gnu.org/licenses>. ----
---- ----
-------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity toggle_register is
Generic (myaddress: natural);
Port ( databus : inout STD_LOGIC_VECTOR (31 downto 0);
addressbus : in STD_LOGIC_VECTOR (15 downto 0);
info : in STD_LOGIC_VECTOR (31 downto 0);
writesignal : in STD_LOGIC;
readsignal : in STD_LOGIC;
CLK : in STD_LOGIC;
registerbits : out STD_LOGIC_VECTOR (31 downto 0));
end toggle_register;
architecture Behavioral of toggle_register is
signal memory : STD_LOGIC_VECTOR (31 downto 0) := (others => '0');
begin
registerbits <= memory;
process (CLK) begin
if (rising_edge(CLK)) then
memory <= (others => '0');
if (addressbus = myaddress)
then
if (writesignal = '1') then
memory <= databus;
elsif (readsignal = '1') then
databus(31 downto 0) <= info;
else
databus <= (others => 'Z');
end if;
else
databus <= (others => 'Z');
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | 48320128bd54b99a7325cd86d93bbdfb | 0.441099 | 5.087542 | false | false | false | false |
rodrigofegui/UnB | 2017.1/Organização e Arquitetura de Computadores/Trabalhos/Projeto Final/Referências/dec_mem/memory.vhd | 1 | 1,123 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity memory is
generic(N: integer := 7; M: integer := 32);
port(
clk: in STD_LOGIC := '0';
we: in STD_LOGIC := '0';
adr: in STD_LOGIC_VECTOR(N-1 downto 0) := (others => '0');
din: in STD_LOGIC_VECTOR(M-1 downto 0) := (others => '0');
dout: out STD_LOGIC_VECTOR(M-1 downto 0)
);
end;
architecture memory_arch of memory is
type mem_array is array(0 to (2**N-1)) of STD_LOGIC_VECTOR(M-1 downto 0);
signal mem: mem_array := (
x"abababab",
x"efefefef",
x"02146545",
x"85781546",
x"69782314",
x"25459789",
x"245a65c5",
x"ac5b4b5b",
x"ebebebeb",
x"cacacaca",
x"ecececec",
x"facfcafc",
x"ecaecaaa",
x"dadadeac",
others => (others => '1')
);
begin
process(clk) begin
if clk'event and clk='1' then
if we='1' then
mem(to_integer(unsigned(adr))) <= din;
end if;
end if;
end process;
dout <= mem(to_integer(unsigned(adr)));
end; | gpl-3.0 | 0746f1a0e5264d6907de36dcc8527a02 | 0.526269 | 2.739024 | false | false | false | false |
airabinovich/finalArquitectura | RAM/ipcore_dir/RAM_ram_bank/simulation/bmg_stim_gen.vhd | 1 | 7,560 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port Ram
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SRAM
-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
-- simulation ends
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SRAM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SRAM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SRAM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST ='1') THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
DINA : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
WEA : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
CHECK_DATA: OUT STD_LOGIC:='0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
CONSTANT DATA_PART_CNT_A: INTEGER:= DIVROUNDUP(4,4);
SIGNAL WRITE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_INT : STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_INT : STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_WRITE : STD_LOGIC := '0';
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL COUNT_NO : INTEGER :=0;
SIGNAL DO_READ_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
BEGIN
WRITE_ADDR_INT(3 DOWNTO 0) <= WRITE_ADDR(3 DOWNTO 0);
READ_ADDR_INT(3 DOWNTO 0) <= READ_ADDR(3 DOWNTO 0);
ADDRA <= IF_THEN_ELSE(DO_WRITE='1',WRITE_ADDR_INT,READ_ADDR_INT) ;
DINA <= DINA_INT ;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 16
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
WR_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 16 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_WRITE,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR
);
WR_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP (
DATA_GEN_WIDTH => 4,
DOUT_WIDTH => 4,
DATA_PART_CNT => DATA_PART_CNT_A,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => DO_WRITE,
DATA_OUT => DINA_INT
);
WR_RD_PROCESS: PROCESS (CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
ELSIF(COUNT_NO < 4) THEN
DO_WRITE <= '1';
DO_READ <= '0';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO< 8) THEN
DO_WRITE <= '0';
DO_READ <= '1';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO=8) THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(0),
CLK => CLK,
RST => RST,
D => DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(I),
CLK => CLK,
RST => RST,
D => DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
WEA(0) <= IF_THEN_ELSE(DO_WRITE='1','1','0') ;
END ARCHITECTURE;
| lgpl-2.1 | 684fa55bddb309a06e3ee0986f4154fa | 0.55754 | 3.770574 | false | false | false | false |
MAV-RT-testbed/MAV-testbed | Syma_Flight_Final/Syma_Flight_Final.srcs/sources_1/ipshared/xilinx.com/axi_quad_spi_v3_2/c64e9f22/hdl/src/vhdl/reset_sync_module.vhd | 1 | 7,941 | -------------------------------------------------------------------------------
-- reset_sync_module.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: reset_sync_module.vhd
-- Version: v3.0
-- Description: This is the reset sync module.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.conv_std_logic_vector;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_misc.all;
-- library unsigned is used for overloading of "=" which allows integer to
-- be compared to std_logic_vector
use ieee.std_logic_unsigned.all;
library axi_lite_ipif_v3_0;
use axi_lite_ipif_v3_0.axi_lite_ipif;
use axi_lite_ipif_v3_0.ipif_pkg.all;
library axi_quad_spi_v3_2;
use axi_quad_spi_v3_2.all;
library unisim;
use unisim.vcomponents.FDR;
-------------------------------------------------------------------------------
entity reset_sync_module is
--generic();
port(EXT_SPI_CLK : in std_logic;
Soft_Reset_frm_axi: in std_logic;
Rst_to_spi : out std_logic
);
end entity reset_sync_module;
architecture imp of reset_sync_module is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-- signal declaration
signal Soft_Reset_frm_axi_d1 : std_logic;
signal Soft_Reset_frm_axi_d2 : std_logic;
signal Soft_Reset_frm_axi_d3 : std_logic;
attribute ASYNC_REG : string;
attribute ASYNC_REG of RESET_SYNC_AX2S_1 : label is "TRUE";
-----
begin
-----
--RESET_SYNC_FROM_AXI_TO_SPI: process(EXT_SPI_CLK)is
-------
--begin
-------
-- if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
-- Soft_Reset_frm_axi_d1 <= Soft_Reset_frm_axi;
-- Soft_Reset_frm_axi_d2 <= Soft_Reset_frm_axi_d1;
-- Soft_Reset_frm_axi_d3 <= Soft_Reset_frm_axi_d2;
-- end if;
--end process RESET_SYNC_FROM_AXI_TO_SPI;
-----------------------------------------
RESET_SYNC_AX2S_1: component FDR
generic map(INIT => '0'
)port map (
Q => Soft_Reset_frm_axi_d1,
C => EXT_SPI_CLK,
D => Soft_Reset_frm_axi,
R => '0'
);
RESET_SYNC_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => Soft_Reset_frm_axi_d2,
C => EXT_SPI_CLK,
D => Soft_Reset_frm_axi_d1,
R => '0'
);
Rst_to_spi <= Soft_Reset_frm_axi_d2;
---------------------------------------
end architecture imp;
-------------------------------------------------------------------------------
| gpl-2.0 | 875a5fd518ce3d2f87e0c9981434e939 | 0.444906 | 4.584873 | false | false | false | false |
SWORDfpga/ComputerOrganizationDesign | labs/lab08/lab08/ipcore_dir/ROM_D/simulation/ROM_D_tb.vhd | 8 | 4,201 | --------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: ROM_D_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY ROM_D_tb IS
END ENTITY;
ARCHITECTURE ROM_D_tb_ARCH OF ROM_D_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
ROM_D_tb_synth_inst:ENTITY work.ROM_D_tb_synth
GENERIC MAP (C_ROM_SYNTH => 0)
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
| gpl-3.0 | fe66a210963ad0d949568e0332b5b38c | 0.621519 | 4.566304 | false | false | false | false |
jmarcelof/Phoenix | NoC/HammingPack16.vhd | 2 | 2,750 | library ieee;
use ieee.std_logic_1164.all;
use work.NoCPackage.all;
package HammingPack16 is
--define sizes and types
--constant TAM_FLIT : integer range 1 to 64 := 16;
constant TAM_HAMM : integer range 1 to 64 := 6;
constant TAM_PHIT : integer range 1 to 64 := TAM_FLIT + TAM_HAMM;
constant HAMM_NPORT: integer := 4; -- 4 portas (EAST,WEST,NORTH,SOUTH)
constant COUNTERS_SIZE: integer := 5; -- 5 bits cada contador
subtype reghamm is std_logic_vector((TAM_HAMM-1) downto 0);
subtype regphit is std_logic_vector((TAM_PHIT-1) downto 0);
subtype regHamm_Nport is std_logic_vector((HAMM_NPORT-1) downto 0);
subtype row_FaultTable is std_logic_vector((3*COUNTERS_SIZE+1) downto 0);
type row_FaultTable_Ports is array ((HAMM_NPORT-1) downto 0) of row_FaultTable;
type row_FaultTable_Nport_Ports is array ((NPORT-1) downto 0) of row_FaultTable_Ports;
type array_statusHamming is array ((HAMM_NPORT-1) downto 0) of reg3;
type arrayNport_regphit is array ((NPORT-1) downto 0) of regphit;
type arrayNrot_regphit is array ((NROT-1) downto 0) of regphit;
type matrixNrot_Nport_regphit is array((NROT-1) downto 0) of arrayNport_regphit; -- a -- array(NROT)(NPORT)(TAM_FLIT)
type arrayNport_reghamm is array((NPORT-1) downto 0) of reghamm;
type arrayNrot_reghamm is array((NROT-1) downto 0) of reghamm;
type matrixNrot_Nport_reghamm is array((NROT-1) downto 0) of arrayNport_reghamm; -- a -- array(NROT)(NPORT)(TAM_FLIT)
--define maks to select bits to xor for each parity
constant MaskP1 : std_logic_vector(15 downto 0) := "1010110101011011";
constant MaskP2 : std_logic_vector(15 downto 0) := "0011011001101101";
constant MaskP4 : std_logic_vector(15 downto 0) := "1100011110001110";
constant MaskP8 : std_logic_vector(15 downto 0) := "0000011111110000";
constant MaskP16 : std_logic_vector(15 downto 0) := "1111100000000000";
constant NE: std_logic_vector (2 downto 0) := "101"; -- no error
constant EC: std_logic_vector (2 downto 0) := "011"; -- error corrected
constant ED: std_logic_vector (2 downto 0) := "111"; -- error detected
constant BF: std_logic_vector (2 downto 0) := "000"; -- "stand by" or buffer full
--function to exclusive-OR all the bits in a std_logic_vector
function xor_reduce(arg : std_logic_vector) return std_logic;
end HammingPack16;
package body HammingPack16 is
--function to exclusive-OR all the bits in a std_logic_vector
function xor_reduce(arg : std_logic_vector) return std_logic is
variable result : std_logic;
begin
result := '0';
for b in arg'range loop
result := result xor arg(b);
end loop;
return result;
end function xor_reduce;
end HammingPack16; | lgpl-3.0 | 2441ec9825fabdcc6376854934d234f1 | 0.694545 | 3.512133 | false | false | false | false |
Hyperion302/omega-cpu | Hardware/Omega/ipcore_dir/UARTClockManager.vhd | 1 | 6,351 | -- file: UARTClockManager.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____15.360______0.000______50.0______407.321____200.759
-- CLK_OUT2____32.000______0.000______50.0______348.651____200.759
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary__________32.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity UARTClockManager is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic;
-- Status and control signals
RESET : in std_logic
);
end UARTClockManager;
architecture xilinx of UARTClockManager is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "UARTClockManager,clk_wiz_v3_6,{component_name=UARTClockManager,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=2,clkin1_period=31.250,clkin2_period=31.250,use_power_down=false,use_reset=true,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkout0 : std_logic;
signal clkout1 : std_logic;
signal clkout2_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
-- Unused status signals
signal locked_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK_IN1);
-- Clocking primitive
--------------------------------------
-- Instantiation of the PLL primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
pll_base_inst : PLL_BASE
generic map
(BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 24,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 50,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 24,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 31.250,
REF_JITTER => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKOUT0 => clkout0,
CLKOUT1 => clkout1,
CLKOUT2 => clkout2_unused,
CLKOUT3 => clkout3_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
-- Status and control signals
LOCKED => locked_unused,
RST => RESET,
-- Input clock control
CLKFBIN => clkfbout,
CLKIN => clkin1);
-- Output buffering
-------------------------------------
clkout1_buf : BUFG
port map
(O => CLK_OUT1,
I => clkout0);
clkout2_buf : BUFG
port map
(O => CLK_OUT2,
I => clkout1);
end xilinx;
| lgpl-3.0 | 8d40ff07175b3fa728e39d54861508b3 | 0.599748 | 4.20596 | false | false | false | false |
INTI-CMNB/Lattuino_IP_Core | FPGA/lattuino_1/wb_dev_intercon.vhdl | 1 | 4,734 | -----------------------------------------------------------------------------------------
-- Generated by WISHBONE Builder. Do not edit this file.
--
-- For defines see wb_devices.defines
--
-- Package: WBDevInterconPkg (WBDevIntercon_package.vhdl)
--
-- Generated Tue May 30 10:23:57 2017
--
-- Wishbone masters:
-- cpu
--
-- Wishbone slaves:
-- rs2
-- baseadr 0x00000000 - size 0x40
-- ad
-- baseadr 0x00000040 - size 0x40
-- tmr
-- baseadr 0x00000080 - size 0x40
-- t16
-- baseadr 0x000000C0 - size 0x40
-----------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
package WBDevInterconIntPackage is
function "and"(l : std_logic_vector;
r : std_logic) return std_logic_vector;
end package WBDevInterconIntPackage;
package body WBDevInterconIntPackage is
function "and"(l : std_logic_vector;
r : std_logic) return std_logic_vector is
variable result : std_logic_vector(l'range);
begin -- "and"
for i in l'range loop
result(i):=l(i) and r;
end loop; -- i
return result;
end function "and";
end package body WBDevInterconIntPackage;
library IEEE;
use IEEE.std_logic_1164.all;
use work.WBDevInterconIntPackage.all;
entity WBDevIntercon is
port(
-- wishbone master port(s)
-- cpu
cpu_dat_o : out std_logic_vector(7 downto 0);
cpu_ack_o : out std_logic;
cpu_dat_i : in std_logic_vector(7 downto 0);
cpu_we_i : in std_logic;
cpu_adr_i : in std_logic_vector(7 downto 0);
cpu_cyc_i : in std_logic;
cpu_stb_i : in std_logic;
-- wishbone slave port(s)
-- rs2
rs2_dat_i : in std_logic_vector(7 downto 0);
rs2_ack_i : in std_logic;
rs2_dat_o : out std_logic_vector(7 downto 0);
rs2_we_o : out std_logic;
rs2_adr_o : out std_logic_vector(0 downto 0);
rs2_stb_o : out std_logic;
-- ad
ad_dat_i : in std_logic_vector(7 downto 0);
ad_ack_i : in std_logic;
ad_dat_o : out std_logic_vector(7 downto 0);
ad_we_o : out std_logic;
ad_adr_o : out std_logic_vector(0 downto 0);
ad_stb_o : out std_logic;
-- tmr
tmr_dat_i : in std_logic_vector(7 downto 0);
tmr_ack_i : in std_logic;
tmr_dat_o : out std_logic_vector(7 downto 0);
tmr_we_o : out std_logic;
tmr_adr_o : out std_logic_vector(2 downto 0);
tmr_stb_o : out std_logic;
-- t16
t16_dat_i : in std_logic_vector(7 downto 0);
t16_ack_i : in std_logic;
t16_dat_o : out std_logic_vector(7 downto 0);
t16_we_o : out std_logic;
t16_adr_o : out std_logic_vector(0 downto 0);
t16_stb_o : out std_logic;
-- clock and reset
wb_clk_i : in std_logic;
wb_rst_i : in std_logic);
end entity WBDevIntercon;
architecture RTL of WBDevIntercon is
signal rs2_ss : std_logic; -- slave select
signal ad_ss : std_logic; -- slave select
signal tmr_ss : std_logic; -- slave select
signal t16_ss : std_logic; -- slave select
begin -- RTL
decoder:
block
signal adr : std_logic_vector(7 downto 0);
begin
adr <= cpu_adr_i;
rs2_ss <= '1' when adr(7 downto 6)="00" else '0';
ad_ss <= '1' when adr(7 downto 6)="01" else '0';
tmr_ss <= '1' when adr(7 downto 6)="10" else '0';
t16_ss <= '1' when adr(7 downto 6)="11" else '0';
rs2_adr_o <= adr(0 downto 0);
ad_adr_o <= adr(0 downto 0);
tmr_adr_o <= adr(2 downto 0);
t16_adr_o <= adr(0 downto 0);
end block decoder;
mux:
block
signal stb_m2s : std_logic;
signal we_m2s : std_logic;
signal ack_s2m : std_logic;
signal dat_m2s : std_logic_vector(7 downto 0);
signal dat_s2m : std_logic_vector(7 downto 0);
begin
-- stb Master -> Slave [Selection]
stb_m2s <= cpu_stb_i;
rs2_stb_o <= rs2_ss and stb_m2s;
ad_stb_o <= ad_ss and stb_m2s;
tmr_stb_o <= tmr_ss and stb_m2s;
t16_stb_o <= t16_ss and stb_m2s;
-- we Master -> Slave
we_m2s <= cpu_we_i;
rs2_we_o <= we_m2s;
ad_we_o <= we_m2s;
tmr_we_o <= we_m2s;
t16_we_o <= we_m2s;
-- ack Slave -> Master
ack_s2m <= rs2_ack_i or ad_ack_i or tmr_ack_i or t16_ack_i;
cpu_ack_o <= ack_s2m;
-- dat Master -> Slave
dat_m2s <= cpu_dat_i;
rs2_dat_o <= dat_m2s;
ad_dat_o <= dat_m2s;
tmr_dat_o <= dat_m2s;
t16_dat_o <= dat_m2s;
-- dat Slave -> Master [and/or]
dat_s2m <= (rs2_dat_i and rs2_ss) or (ad_dat_i and ad_ss) or (tmr_dat_i and tmr_ss) or (t16_dat_i and t16_ss);
cpu_dat_o <= dat_s2m;
end block mux;
end architecture RTL; | gpl-2.0 | 118094383b3dd09d772f156b3b708a93 | 0.558513 | 2.879562 | false | false | false | false |
MAV-RT-testbed/MAV-testbed | Syma_Flight_Final/Syma_Flight_Final.srcs/sources_1/ipshared/xilinx.com/axi_quad_spi_v3_2/c64e9f22/hdl/src/vhdl/pselect_f.vhd | 3 | 9,861 | -- pselect_f.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pselect_f.vhd
--
-- Description:
-- (Note: At least as early as I.31, XST implements a carry-
-- chain structure for most decoders when these are coded in
-- inferrable VHLD. An example of such code can be seen
-- below in the "INFERRED_GEN" Generate Statement.
--
-- -> New code should not need to instantiate pselect-type
-- components.
--
-- -> Existing code can be ported to Virtex5 and later by
-- replacing pselect instances by pselect_f instances.
-- As long as the C_FAMILY parameter is not included
-- in the Generic Map, an inferred implementation
-- will result.
--
-- -> If the designer wishes to force an explicit carry-
-- chain implementation, pselect_f can be used with
-- the C_FAMILY parameter set to the target
-- Xilinx FPGA family.
-- )
--
-- Parameterizeable peripheral select (address decode).
-- AValid qualifier comes in on Carry In at bottom
-- of carry chain.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_AB -- number of address bits to decode
-- C_AW -- width of address bus
-- C_BAR -- base address of peripheral (peripheral select
-- is asserted when the C_AB most significant
-- address bits match the C_AB most significant
-- C_BAR bits
-- Definition of Ports:
-- A -- address input
-- AValid -- address qualifier
-- CS -- peripheral select
-------------------------------------------------------------------------------
entity pselect_f is
generic (
C_AB : integer := 9;
C_AW : integer := 32;
C_BAR : std_logic_vector;
C_FAMILY : string := "nofamily"
);
port (
A : in std_logic_vector(0 to C_AW-1);
AValid : in std_logic;
CS : out std_logic
);
end entity pselect_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of pselect_f is
component MUXCY is
port (
O : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component MUXCY;
-----------------------------------------------------------------------------
-- C_BAR may not be indexed from 0 and may not be ascending;
-- BAR recasts C_BAR to have these properties.
-----------------------------------------------------------------------------
constant BAR : std_logic_vector(0 to C_BAR'length-1) := C_BAR;
type bo2sl_type is array (boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
function min(i, j: integer) return integer is
begin
if i<j then return i; else return j; end if;
end;
begin
------------------------------------------------------------------------------
-- Check that the generics are valid.
------------------------------------------------------------------------------
-- synthesis translate_off
assert (C_AB <= C_BAR'length) and (C_AB <= C_AW)
report "pselect_f generic error: " &
"(C_AB <= C_BAR'length) and (C_AB <= C_AW)" &
" does not hold."
severity failure;
-- synthesis translate_on
------------------------------------------------------------------------------
-- Build a behavioral decoder
------------------------------------------------------------------------------
XST_WA:if C_AB > 0 generate
CS <= AValid when A(0 to C_AB-1) = BAR (0 to C_AB-1) else
'0' ;
end generate XST_WA;
PASS_ON_GEN:if C_AB = 0 generate
CS <= AValid ;
end generate PASS_ON_GEN;
end imp;
| gpl-2.0 | 2e439170e6835fd613238ed2b462a0e0 | 0.408782 | 5.612408 | false | false | false | false |
INTI-CMNB/Lattuino_IP_Core | Work/pm_pkg.vhdl | 1 | 8,052 | ------------------------------------------------------------------------------
---- ----
---- Lattuino program memories and peripherals package ----
---- ----
---- This file is part FPGA Libre project http://fpgalibre.sf.net/ ----
---- ----
---- Description: ----
---- This is a package with the PMs used for Lattuino. ----
---- It also includes the Lattuino peripherals. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2017 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2017 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the GPL v2 or newer license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: PrgMems (Package) ----
---- File name: pm_pkg.in.vhdl (template used) ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: lattuino ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- Target FPGA: iCE40HX4K-TQ144 ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Lattice iCECube2 2016.02.27810 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
package PrgMems is
component lattuino_1_blPM_8 is
generic(
WORD_SIZE : integer:=16; -- Word Size
FALL_EDGE : std_logic:='0'; -- Ram clock falling edge
ADDR_W : integer:=13); -- Address Width
port(
clk_i : in std_logic;
addr_i : in std_logic_vector(ADDR_W-1 downto 0);
data_o : out std_logic_vector(WORD_SIZE-1 downto 0);
we_i : in std_logic;
data_i : in std_logic_vector(WORD_SIZE-1 downto 0));
end component lattuino_1_blPM_8;
component lattuino_1_blPM_4 is
generic(
WORD_SIZE : integer:=16; -- Word Size
FALL_EDGE : std_logic:='0'; -- Ram clock falling edge
ADDR_W : integer:=13); -- Address Width
port(
clk_i : in std_logic;
addr_i : in std_logic_vector(ADDR_W-1 downto 0);
data_o : out std_logic_vector(WORD_SIZE-1 downto 0);
we_i : in std_logic;
data_i : in std_logic_vector(WORD_SIZE-1 downto 0));
end component lattuino_1_blPM_4;
component lattuino_1_blPM_2 is
generic(
WORD_SIZE : integer:=16; -- Word Size
FALL_EDGE : std_logic:='0'; -- Ram clock falling edge
ADDR_W : integer:=13); -- Address Width
port(
clk_i : in std_logic;
addr_i : in std_logic_vector(ADDR_W-1 downto 0);
data_o : out std_logic_vector(WORD_SIZE-1 downto 0);
we_i : in std_logic;
data_i : in std_logic_vector(WORD_SIZE-1 downto 0));
end component lattuino_1_blPM_2;
component lattuino_1_blPM_2S is
generic(
WORD_SIZE : integer:=16; -- Word Size
FALL_EDGE : std_logic:='0'; -- Ram clock falling edge
ADDR_W : integer:=13); -- Address Width
port(
clk_i : in std_logic;
addr_i : in std_logic_vector(ADDR_W-1 downto 0);
data_o : out std_logic_vector(WORD_SIZE-1 downto 0);
we_i : in std_logic;
data_i : in std_logic_vector(WORD_SIZE-1 downto 0));
end component lattuino_1_blPM_2S;
component TMCounter is
generic(
CNT_PRESC : natural:=24;
ENA_TMR : std_logic:='1');
port(
-- WISHBONE signals
wb_clk_i : in std_logic; -- Clock
wb_rst_i : in std_logic; -- Reset input
wb_adr_i : in std_logic_vector(2 downto 0); -- Adress bus
wb_dat_o : out std_logic_vector(7 downto 0); -- DataOut Bus
wb_dat_i : in std_logic_vector(7 downto 0); -- DataIn Bus
wb_we_i : in std_logic; -- Write Enable
wb_stb_i : in std_logic; -- Strobe
wb_ack_o : out std_logic; -- Acknowledge
pwm_o : out std_logic_vector(5 downto 0); -- 6 PWMs
pwm_e_o : out std_logic_vector(5 downto 0)); -- Pin enable for the PWMs
end component TMCounter;
component TM16bits is
generic(
CNT_PRESC : natural:=24;
ENA_TMR : std_logic:='1');
port(
-- WISHBONE signals
wb_clk_i : in std_logic; -- Clock
wb_rst_i : in std_logic; -- Reset input
wb_adr_i : in std_logic_vector(0 downto 0); -- Adress bus
wb_dat_o : out std_logic_vector(7 downto 0); -- DataOut Bus
wb_dat_i : in std_logic_vector(7 downto 0); -- DataIn Bus
wb_we_i : in std_logic; -- Write Enable
wb_stb_i : in std_logic; -- Strobe
wb_ack_o : out std_logic; -- Acknowledge
-- Interface
irq_req_o : out std_logic;
irq_ack_i : in std_logic);
end component TM16bits;
component AD_Conv is
generic(
DIVIDER : positive:=12;
INTERNAL_CLK : std_logic:='1'; -- not boolean for Verilog compat
ENABLE : std_logic:='1'); -- not boolean for Verilog compat
port(
-- WISHBONE signals
wb_clk_i : in std_logic; -- Clock
wb_rst_i : in std_logic; -- Reset input
wb_adr_i : in std_logic_vector(0 downto 0); -- Adress bus
wb_dat_o : out std_logic_vector(7 downto 0); -- DataOut Bus
wb_dat_i : in std_logic_vector(7 downto 0); -- DataIn Bus
wb_we_i : in std_logic; -- Write Enable
wb_stb_i : in std_logic; -- Strobe
wb_ack_o : out std_logic; -- Acknowledge
-- SPI rate (2x)
-- Note: with 2 MHz spi_ena_i we get 1 MHz SPI clock => 55,6 ks/s
spi_ena_i: in std_logic; -- 2xSPI clock
-- A/D interface
ad_ncs_o : out std_logic; -- SPI /CS
ad_clk_o : out std_logic; -- SPI clock
ad_din_o : out std_logic; -- SPI A/D Din (MOSI)
ad_dout_i: in std_logic); -- SPI A/D Dout (MISO)
end component AD_Conv;
end package PrgMems;
| gpl-2.0 | b15b2651893bafb9c4b564760c4ae286 | 0.40611 | 4.187207 | false | false | false | false |
dpolad/dlx | DLX_vhd/a.i.a.a.a-BOOTHENCODER.vhd | 2 | 753 | -- booth_encoder.vhd --
-- booth encoder as described in Prof. Graziano documents
library ieee;
use ieee.std_logic_1164.all;
entity booth_encoder is
port(
B_in : in std_logic_vector (2 downto 0);
A_out : out std_logic_vector (2 downto 0)
);
end booth_encoder;
architecture bhe of booth_encoder is
begin
A_out <= "000" when B_in = "000" else -- 0 position 000
"100" when B_in = "001" else -- A position 001
"100" when B_in = "010" else -- A position 001
"101" when B_in = "011" else -- 2A position 011
"111" when B_in = "100" else -- -2A position 100
"110" when B_in = "101" else -- -A position 010
"110" when B_in = "110" else -- -A position 010
"000" when B_in = "111"; -- 0 position 000
end bhe;
| bsd-2-clause | da32af75990029bb841e00175e613b85 | 0.61753 | 2.660777 | false | false | false | false |
achan1989/SlowWorm | sim/memory/stack_256x16/testbench.vhd | 1 | 2,627 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 24.08.2016 15:22:18
-- Design Name:
-- Module Name: testbench - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity testbench is
end testbench;
architecture Behavioral of testbench is
component stack_256x16 is port (
push : in std_ulogic;
pop : in std_ulogic;
dout : out std_ulogic_vector (15 downto 0);
din : in std_ulogic_vector (15 downto 0);
clk : in std_ulogic);
end component;
signal clk : std_ulogic := '0';
signal din, dout : std_ulogic_vector (15 downto 0);
signal push, pop : std_ulogic;
constant ClockPeriod : TIME := 50 ns;
begin
Stack: stack_256x16 port map (
push => push,
pop => pop,
dout => dout,
din => din,
clk => clk
);
clock: process begin
clk <= '0';
wait for ClockPeriod;
loop
clk <= not clk;
wait for (ClockPeriod / 2);
end loop;
end process;
stimulus: process begin
-- Starting values.
push <= '0';
pop <= '0';
din <= (others => '0');
wait until falling_edge(clk);
-- Attempt invalid op.
wait until rising_edge(clk);
push <= '1';
pop <= '1';
din <= x"0123";
-- Attempt no op.
wait until rising_edge(clk);
push <= '0';
pop <= '0';
din <= x"4567";
-- Push first.
wait until rising_edge(clk);
push <= '1';
pop <= '0';
din <= x"89AB";
-- Push second.
wait until rising_edge(clk);
push <= '1';
pop <= '0';
din <= x"CDEF";
-- No op.
wait until rising_edge(clk);
push <= '0';
pop <= '0';
din <= x"0000";
-- Pop second.
wait until rising_edge(clk);
push <= '0';
pop <= '1';
-- Pop first.
wait until rising_edge(clk);
push <= '0';
pop <= '1';
-- No op.
wait until rising_edge(clk);
push <= '0';
pop <= '0';
din <= x"0000";
-- Do nothing more.
wait;
end process;
end Behavioral;
| mit | 608585ddf132d0434447ab1aae999ea7 | 0.537115 | 3.684432 | false | false | false | false |
dpolad/dlx | DLX_vhd/a.j-EXECUTEREGS.vhd | 2 | 1,225 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--use work.myTypes.all;
entity execute_regs is
generic (
SIZE : integer := 32
);
port (
X_i : in std_logic_vector(SIZE - 1 downto 0);
S_i : in std_logic_vector(SIZE - 1 downto 0);
D2_i : in std_logic_vector(4 downto 0);
X_o : out std_logic_vector(SIZE - 1 downto 0);
S_o : out std_logic_vector(SIZE - 1 downto 0);
D2_o : out std_logic_vector(4 downto 0);
stall_i : in std_logic;
clk : in std_logic;
rst : in std_logic
);
end execute_regs;
architecture struct of execute_regs is
signal enable : std_logic;
component ff32_en
generic(
SIZE : integer
);
port(
D : in std_logic_vector(SIZE - 1 downto 0);
Q : out std_logic_vector(SIZE - 1 downto 0);
en : in std_logic;
clk : in std_logic;
rst : in std_logic
);
end component;
begin
enable <= not stall_i;
X: ff32_en generic map(
SIZE => 32
)port map(
D => X_i,
Q => X_o,
en => enable,
clk => clk,
rst => rst);
S: ff32_en generic map(
SIZE => 32
)port map(
D => S_i,
Q => S_o,
en => enable,
clk => clk,
rst => rst);
D2: ff32_en generic map(
SIZE => 5
)port map(
D => D2_i,
Q => D2_o,
en => enable,
clk => clk,
rst => rst);
end struct;
| bsd-2-clause | 2b6937e4e0d17492cb6541791751162d | 0.607347 | 2.24359 | false | false | false | false |
jmarcelof/Phoenix | NoC/FaultDetection.vhd | 2 | 7,535 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:39:07 06/27/2013
-- Design Name:
-- Module Name: FaultDetection - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use ieee.numeric_std.all;
use work.NoCPackage.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
--
-- IN ____________ OUT
-- | |
-- data_inA|------------| dataInB
-- | |
-- |____________|
-- compTest test_link_in test_link_out <---sinais de controle
-- ____________\/____________\/___________\/________
-- | |
-- data_out'|
--
--
entity FaultDetection is
Port(
clock : in std_logic;
reset : in std_logic;
c_strLinkTst: in regNport; -- (start link test) indica que houve um pacote de controle do tipo TEST_LINKS para testar os links. Comentario antigo:sinal de teste local para exterior
c_strLinkTstAll: out std_logic; -- se algum buffer fez o pedido de teste de link
c_stpLinkTst: out regNport; -- (stop link test) indica o fim do teste do link
test_link_inA : in regNport; -- sinal testLink_i dos roteadores vizinhos que indica teste de link (desta maneira o roteador sabe que precisa revolver o dado recebido durante o teste do link). Comentario antigo: sinal de teste exterior para local
data_outA : in arrayNport_regflit; -- data_out normal. Dado que sera encaminhado para as portas de saida, caso nao esteja em teste
data_inA : in arrayNport_regflit; -- dado(flit) recebido nas portas de entrada dos buffers (para analisar o dado recebido no teste de links)
credit_inA : in regNport;
credit_outA : in regNport;
data_outB : out arrayNport_regflit; -- dado que sera encaminhado para as portas de saida (pode ser encaminhado data_out normal ou dados para teste de link)
credit_inB : out regNport;
c_faultTableFDM : out regNPort; -- tabela de falhas ('0' indica sem falha, '1' indica falha)
credit_outB : out regNport);
end FaultDetection;
-- str(send to router)
architecture Behavioral of FaultDetection is
signal stopLinkTest: std_logic;
type testLinks is (S_INIT, S_FIRSTDATA, S_SECONDDATA,S_END);
signal EA : testLinks;
signal compTest : std_logic := '0';
signal tmp : regNport := (others=>'Z');
signal fillOne : regFlit := (others=>'1');
signal fillZero : regFlit := (others=>'0');
signal strLinkTstAll : std_logic := '0';
signal faultTableReg : regNPort :=(others=>'0');
begin
c_stpLinkTst <= (others=>'1') when stopLinkTest = '1' else (others=>'0');
c_faultTableFDM <= faultTableReg;
c_strLinkTstAll <= strLinkTstAll;
-- '1' se em algum buffer houve o pedido de teste de link (por causa do pacote de controle do tipo TEST_LINKS)
strLinkTstAll <= c_strLinkTst(EAST) or c_strLinkTst(WEST) or c_strLinkTst(NORTH) or c_strLinkTst(SOUTH) or c_strLinkTst(LOCAL);
-- link LOCAL eh considerado sempre sem falha. Nao passa pelo teste de links
credit_outB(LOCAL) <= credit_outA(LOCAL);
credit_inB(LOCAL) <= credit_inA(LOCAL);
data_outB(LOCAL) <= data_outA(LOCAL);
ALL_MUX : for i in 0 to (NPORT-2) generate -- para 4 portas (EAST, WEST, NORTH, SOUTH)
credit_outB(i) <= credit_outA(i) when (strLinkTstAll or test_link_inA(i)) = '0' else '0';
credit_inB(i) <= credit_inA(i) when (strLinkTstAll or test_link_inA(i)) = '0' else '0';
data_outB(i) <= data_outA(i) when strLinkTstAll = '0' and test_link_inA(i) = '0' else --passagem do data_out normal
data_inA(i) when test_link_inA(i) = '1' and strLinkTstAll = '0' else -- retransmissao do dado de test_link
(others=>'1') when strLinkTstAll ='1' and compTest = '1' else --envio do dado(1) de test_link
(others=>'0') when strLinkTstAll ='1' and compTest = '0' else --envio do dado(2) de test_link
(others=>'Z');
tmp(i) <= '0' when compTest = '1' and (data_inA(i) xor fillOne) = std_logic_vector(to_unsigned(0, fillOne'length)) else -- '0' QUANDO estiver enviando dado com todos os bits em '1' E receber o mesmo dado que enviou (todos os bits em '1')
'1' when compTest = '1' else -- '1' QUANDO estiver enviando dado com todos os bits em '1' (nao recebe o mesmo dado que enviou, logo tem falha)
'0' when compTest = '0' and (data_inA(i) xor fillZero) = std_logic_vector(to_unsigned(0, fillZero'length)) else -- '0' QUANDO estiver enviando dado com todos os bits em '0' E receber o mesmo dado que enviou (todos os bits em '0')
'1' when compTest = '0' else -- '1' QUANDO estiver enviando dado com todos os bits em '1' (nao recebe o mesmo dado que enviou, logo tem falha)
'Z';
end generate ALL_MUX;
--maquina de estados para transmitir e receber os dados
process(clock,reset)
begin
if reset = '1' then
stopLinkTest <= '0';
compTest <= '0';
EA <= S_INIT;
elsif (clock'event and clock='1') then
case EA is
when S_INIT =>
-- verifica em algum buffer houve o pedido de teste de link
if strLinkTstAll = '1' then
stopLinkTest <= '0';
compTest <= '0'; --auxiliar (indica que os dados enviados serao tudo '0')
EA <= S_FIRSTDATA;
end if;
-- envio do primeiro dado (todos os bits em 0). Caso receber os mesmos dados enviados (todos os bits em 0), armazeno '0' na tabela. '1' indica falha
when S_FIRSTDATA =>
faultTableReg(EAST) <= tmp(EAST);
faultTableReg(WEST) <= tmp(WEST);
faultTableReg(NORTH) <= tmp(NORTH);
faultTableReg(SOUTH) <= tmp(SOUTH);
--faultTableReg(LOCAL) <= tmp(LOCAL);
faultTableReg(LOCAL) <= '0';
compTest <= '1'; --auxiliar (indica que os dados enviados serao tudo '1')
EA <= S_SECONDDATA;
-- envio do segundo dado (todos os bits em 1). Caso receber os mesmos dados enviados (todos os bits em 0) e se nao tiver tido problema no primeiro envio, a tabela sera '0'. '1' indica falha
when S_SECONDDATA =>
faultTableReg(EAST) <= faultTableReg(EAST) or tmp(EAST);
faultTableReg(WEST) <= faultTableReg(WEST) or tmp(WEST);
faultTableReg(NORTH) <= faultTableReg(NORTH) or tmp(NORTH);
faultTableReg(SOUTH) <= faultTableReg(SOUTH) or tmp(SOUTH);
faultTableReg(LOCAL) <= '0';
--faultTableReg(LOCAL) <= faultTableReg(LOCAL) or tmp(LOCAL);
stopLinkTest <= '1'; -- indica fim
EA <= S_END;
when S_END =>
stopLinkTest <= '0';
EA <= S_INIT;
when others =>
EA <= S_INIT;
end case;
end if;
end process;
end Behavioral; | lgpl-3.0 | 902b3d4ee50275e284ec56b23ec4061a | 0.588587 | 3.922436 | false | true | false | false |
airabinovich/finalArquitectura | RAM/ipcore_dir/RAM_ram_bank/example_design/RAM_ram_bank_exdes.vhd | 1 | 4,631 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: RAM_ram_bank_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY RAM_ram_bank_exdes IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END RAM_ram_bank_exdes;
ARCHITECTURE xilinx OF RAM_ram_bank_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT RAM_ram_bank IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : RAM_ram_bank
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
| lgpl-2.1 | 6bf5f8c8da65df8f8f48972b0657078f | 0.56748 | 4.691996 | false | false | false | false |
INTI-CMNB/Lattuino_IP_Core | FPGA/lattuino_1/cpuconfig.vhdl | 1 | 4,695 | ------------------------------------------------------------------------------
---- ----
---- Lattuino CPU configuration ----
---- ----
---- This file is part FPGA Libre project http://fpgalibre.sf.net/ ----
---- ----
---- Description: ----
---- Configuration parameters for the Lattuino CPU. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Salvador E. Tropea, salvador en inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2017 Salvador E. Tropea <salvador en inti.gob.ar> ----
---- Copyright (c) 2017 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the GPL v2 or newer license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: CPUConfig (Package) ----
---- File name: cpuconfig.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: lattuino ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- SPI.Devices ----
---- Target FPGA: iCE40HX4K-TQ144 ----
---- Language: VHDL ----
---- Wishbone: None ----
---- Synthesis tools: Lattice iCECube2 2016.02.27810 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
package CPUConfig is
-- SPI support
constant ENABLE_SPI : std_logic:='1';
-- Use a PLL to achieve SCK<=F_CLK and not half
constant ENA_2xSCK : boolean:=true;
-- Clock Frequency
-- IMPORTANT! any change here needs a review of the PLL FILTER_RANGE
constant F_CLK : natural:=24e6;
-- UART baudrate
constant BAUD_RATE : natural:=115200;
-- Starting address for the bootloader (in words)
constant RESET_JUMP : natural:=3768; -- tn25: 696, 45: 1720, 85: 3768
-- RAM address width
constant RAM_ADDR_W : positive:=9; -- tn25: 7 45: 8 85: 9 (128 to 512 b)
-- ROM address width
constant ROM_ADDR_W : positive:=12; -- tn25: 10 45: 11 85: 12 (2/4/8 kib)
-- CapSense button 1 is used as RESET
constant ENABLE_B1_RESET : boolean:=true;
-- PWMs support
constant ENA_PWM0 : boolean:=true;
constant ENA_PWM1 : boolean:=true;
constant ENA_PWM2 : boolean:=true;
constant ENA_PWM3 : boolean:=true;
constant ENA_PWM4 : boolean:=true;
constant ENA_PWM5 : boolean:=true;
-- Interrupt pins support
constant ENA_INT0 : boolean:=true;
constant ENA_INT1 : boolean:=true;
-- Micro and miliseconds timer
constant ENA_TIME_CNT : std_logic:='1';
-- 16 bits timer (for Tone generation)
constant ENA_TMR16 : std_logic:='1';
-- A/D converter support
constant ENABLE_AD : std_logic:='1';
end package CPUConfig;
| gpl-2.0 | e70dee50efe87a7c3ddaf654c8d371dc | 0.331203 | 5.690909 | false | true | false | false |
dpolad/dlx | DLX_synth/a.i-EXECUTEBLOCK.vhd | 1 | 3,248 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.myTypes.all;
entity execute_block is
generic (
SIZE : integer := 32
);
port (
IMM_i : in std_logic_vector(SIZE - 1 downto 0);
A_i : in std_logic_vector(SIZE - 1 downto 0);
rB_i : in std_logic_vector(4 downto 0);
rC_i : in std_logic_vector(4 downto 0);
MUXED_B_i : in std_logic_vector(SIZE - 1 downto 0);
S_MUX_ALUIN_i : in std_logic;
FW_X_i : in std_logic_vector(SIZE - 1 downto 0);
FW_W_i : in std_logic_vector(SIZE - 1 downto 0);
S_FW_A_i : in std_logic_vector(1 downto 0);
S_FW_B_i : in std_logic_vector(1 downto 0);
muxed_dest : out std_logic_vector(4 downto 0);
muxed_B : out std_logic_vector(SIZE -1 downto 0);
S_MUX_DEST_i : in std_logic_vector(1 downto 0);
OP : in AluOp;
ALUW_i : in std_logic_vector(12 downto 0);
DOUT : out std_logic_vector(SIZE - 1 downto 0);
stall_o : out std_logic;
Clock : in std_logic;
Reset : in std_logic
);
end execute_block;
architecture struct of execute_block is
component mux21
port (
IN0 : in std_logic_vector(SIZE - 1 downto 0);
IN1 : in std_logic_vector(SIZE - 1 downto 0);
CTRL : in std_logic;
OUT1 : out std_logic_vector(SIZE - 1 downto 0)
);
end component;
component mux41
generic (
MUX_SIZE : integer := 5
);
port (
IN0 : in std_logic_vector(MUX_SIZE - 1 downto 0);
IN1 : in std_logic_vector(MUX_SIZE - 1 downto 0);
IN2 : in std_logic_vector(MUX_SIZE - 1 downto 0);
IN3 : in std_logic_vector(MUX_SIZE - 1 downto 0);
CTRL : in std_logic_vector(1 downto 0);
OUT1 : out std_logic_vector(MUX_SIZE - 1 downto 0)
);
end component;
component real_alu
generic (
DATA_SIZE : integer := 32);
port (
IN1 : in std_logic_vector(DATA_SIZE - 1 downto 0);
IN2 : in std_logic_vector(DATA_SIZE - 1 downto 0);
--OP : in AluOp;
ALUW_i : in std_logic_vector(12 downto 0);
DOUT : out std_logic_vector(DATA_SIZE - 1 downto 0);
stall_o : out std_logic;
Clock : in std_logic;
Reset : in std_logic
);
end component;
signal FWB2mux : std_logic_vector(SIZE - 1 downto 0);
signal FWA2alu : std_logic_vector(SIZE - 1 downto 0);
signal FWB2alu : std_logic_vector(SIZE - 1 downto 0);
begin
ALUIN_MUX: mux21 port map(
IN0 => FWB2mux,
IN1 => IMM_i,
CTRL => S_MUX_ALUIN_i,
OUT1 => FWB2alu);
ALU: real_alu generic map (
DATA_SIZE => 32
)
port map (
IN1 => FWA2alu,
IN2 => FWB2alu,
-- OP => OP,
ALUW_i => ALUW_i,
DOUT => DOUT,
stall_o => stall_o,
Clock => Clock,
Reset => Reset
);
MUXDEST: mux41 generic map(
MUX_SIZE => 5
)
port map(
IN0 => "00000", -- THIS VALUE SHOULD NEVER APPEAR!!
IN1 => rC_i,
IN2 => rB_i,
IN3 => "11111",
CTRL => S_MUX_DEST_i,
OUT1 => muxed_dest
);
MUX_FWA: mux41 generic map(
MUX_SIZE => 32
)
port map(
IN0 => A_i,
IN1 => FW_X_i,
IN2 => FW_W_i,
IN3 => "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX", -- TODO: remove this, avoid meta state during synth
CTRL => S_FW_A_i,
OUT1 => FWA2alu
);
MUX_FWB: mux41 generic map(
MUX_SIZE => 32
)
port map(
IN0 => MUXED_B_i,
IN1 => FW_X_i,
IN2 => FW_W_i,
IN3 => "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX", -- TODO: remove this, avoid meta state during synth
CTRL => S_FW_B_i,
OUT1 => FWB2mux
);
muxed_B <= FWB2mux;
end struct;
| bsd-2-clause | 03839ac0d2e0175e2e5897185504d86a | 0.633005 | 2.329986 | false | false | false | false |
dpolad/dlx | DLX_vhd/c-DRAM.vhd | 1 | 1,979 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use ieee.std_logic_textio.all;
-- Data memory for DLX
-- Memory filled by a process which reads from a file
-- file name is "data.mem"
entity DRAM is
generic (
RAM_DEPTH : natural := 4096;
I_SIZE : integer := 32);
port (
Clk : in std_logic;
Rst : in std_logic;
Enable : in std_logic;
WR : in std_logic;
Din : in std_logic_vector(I_SIZE - 1 downto 0);
Addr : in std_logic_vector(I_SIZE - 1 downto 0);
Dout : out std_logic_vector(I_SIZE - 1 downto 0)
);
end DRAM;
architecture DRam_Bhe of DRAM is
type RAMtype is array (0 to RAM_DEPTH - 1) of std_logic_vector(I_SIZE - 1 downto 0);-- std_logic_vector(I_SIZE - 1 downto 0);
signal DRAM_mem : RAMtype;
begin -- DRam_Bhe
-- Dout <= DRAM_mem(to_integer(unsigned(Addr))/4) when WR = '0' and Enable = '1' else (others => 'Z');
-- purpose: This process is in charge of filling the Instruction RAM with the firmware
-- type : combinational
-- inputs : Rst
-- outputs: DRAM_mem
FILL_MEM_P: process (Rst,Clk)
file mem_fp2: text;
variable file_line2 : line;
variable index2 : integer := 0;
variable tmp_data_u2 : std_logic_vector(I_SIZE-1 downto 0);
begin -- process FILL_MEM_P
if (Rst = '1') then
file_open(mem_fp2,"DLX_vhd/test_bench/data.mem",READ_MODE);
report "RESETTT:";
while (not endfile(mem_fp2)) loop
readline(mem_fp2,file_line2);
hread(file_line2,tmp_data_u2);
DRAM_mem(index2) <= tmp_data_u2;
index2 := index2 + 1;
end loop;
else
if(clk'event and clk = '0') then
if(Enable = '1' and Wr = '1') then
DRAM_mem(to_integer(unsigned(Addr))/4) <= Din;
report "i = " & integer'image(to_integer(unsigned(Addr)));
elsif ( Enable = '1' and WR='0' ) then
Dout <= DRAM_mem(to_integer(unsigned(Addr))/4);
end if;
end if;
end if;
end process FILL_MEM_P;
end DRam_Bhe;
| bsd-2-clause | 156a4006a99ef8636cef07acd8c4d999 | 0.623042 | 2.97594 | false | false | false | false |
Hyperion302/omega-cpu | Hardware/Open16750/UART.vhdl | 1 | 14,245 | --************************************************************************
--
-- Copyright (C) August Schwerdfeger
-- September 30, 2015
--
--************************************************************************
-- This program is free software: you can redistribute it and/or modify--
-- it under the terms of the GNU Lesser General Public License as --
-- published by the Free Software Foundation, either version 3 of the --
-- License, or (at your option) any later version. --
-- --
-- This program is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU Lesser General Public License <http://www.gnu.org/licenses/> --
-- for more details. --
--************************************************************************
--
-- This circuit serves as a simplifying wrapper to the 'uart_16750' UART
-- core available on OpenCores.org.
-- It provides a hard-wired generic interface to set the word length, parity,
-- and stop bit count. Upon initialization it will enable and reset the
-- UART's receive and transmit FIFOs, and configure the interrupts such that
-- a signal is received iff the receive FIFO is non-empty.
-- It places the UART behind the following interface:
-- * When a byte is received, it is output on 'dout' and 'recv_data_ready'
-- goes high.
-- * Setting 'was_read' high signals that this byte has been read and the
-- next one in the FIFO can be advanced.
-- * Receiving bytes takes priority over transmitting. When the circuit is
-- ready to transmit a byte, 'xmit_buffer_ready' goes high.
-- * Setting 'xmit_enable' high queues the byte on 'din' for transmission.
-- * If the transmit FIFO is full, this byte will be discarded silently;
-- no error state from the UART is conveyed out of the circuit.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity UART is
generic (
word_length : integer range 5 to 8 := 8;
stop_bits : integer range 1 to 2 := 1;
has_parity : boolean := false;
parity_is_even : boolean := false;
baud_divisor : integer range 1 to 65535 := 1);
port (
clk : in std_logic;
rst : in std_logic;
-- This clock should run at 16 times the baud rate.
clk_16x : in std_logic;
serial_out : out std_logic;
serial_in : in std_logic;
din : in std_logic_vector(7 downto 0);
xmit_buffer_ready : out std_logic;
xmit_enable : in std_logic;
was_read : in std_logic;
recv_data_ready : out std_logic;
dout : out std_logic_vector(7 downto 0));
end UART;
architecture Behavioral of UART is
component uart_16750 is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
BAUDCE : in std_logic; -- Baudrate generator clock enable
CS : in std_logic; -- Chip select
WR : in std_logic; -- Write to UART
RD : in std_logic; -- Read from UART
A : in std_logic_vector(2 downto 0); -- Register select
DIN : in std_logic_vector(7 downto 0); -- Data bus input
DOUT : out std_logic_vector(7 downto 0); -- Data bus output
DDIS : out std_logic; -- Driver disable
INT : out std_logic; -- Interrupt output
OUT1N : out std_logic; -- Output 1
OUT2N : out std_logic; -- Output 2
RCLK : in std_logic; -- Receiver clock (16x baudrate)
BAUDOUTN : out std_logic; -- Baudrate generator output (16x baudrate)
RTSN : out std_logic; -- RTS output
DTRN : out std_logic; -- DTR output
CTSN : in std_logic; -- CTS input
DSRN : in std_logic; -- DSR input
DCDN : in std_logic; -- DCD input
RIN : in std_logic; -- RI input
SIN : in std_logic; -- Receiver input
SOUT : out std_logic -- Transmitter output
);
end component uart_16750;
type init_stages is (start,open_divisor_latch,set_baud_divisor_lsb,set_baud_divisor_msb,close_divisor_latch,set_trigger_levels,set_interrupts,waiting,reading,writing);
type write_stages is (write_set_addr, write_enable, write_end);
type read_stages is (read_set_addr, read_enable, read_get_data, read_end);
signal init_stage : init_stages := start;
signal write_stage : write_stages := write_set_addr;
signal read_stage : read_stages := read_set_addr;
signal data_in_s : std_logic_vector(7 downto 0) := (others => '0');
signal uart_dout : std_logic_vector(7 downto 0) := (others => '0');
signal data_out_s : std_logic_vector(7 downto 0) := (others => '0');
signal data_out_waiting : std_logic := '0';
signal recv_data_ready_s : std_logic := '0';
signal xmit_buffer_ready_s : std_logic := '0';
signal rst_s : std_logic := '0';
signal CS_s : std_logic := '0';
signal WR_s : std_logic := '0';
signal RD_s : std_logic := '0';
signal baudout_s : std_logic := '1';
signal addr_s : std_logic_vector(2 downto 0) := "000";
signal CTS_s : std_logic := '1';
signal DSR_s : std_logic := '1';
signal DTR_s : std_logic;
signal RTS_s : std_logic;
signal IRQ_s : std_logic;
constant baud_divisor_c : std_logic_vector(15 downto 0) := std_logic_vector(to_unsigned(baud_divisor,16));
begin
uart_wrapped: uart_16750 port map (
CLK => clk,
RST => '0',
BAUDCE => clk_16x,
CS => CS_s,
WR => WR_s,
RD => RD_s,
A => ADDR_s,
DIN => data_in_s,
DOUT => uart_dout,
DDIS => OPEN,
INT => IRQ_s,
OUT1N => OPEN,
OUT2N => OPEN,
RCLK => baudout_s,
BAUDOUTN=> baudout_s,
RTSN => RTS_s,
DTRN => DTR_s,
CTSN => '1',
DSRN => '1',
DCDN => '1',
RIN => '1',
SIN => serial_in,
SOUT => serial_out
);
dout <= data_out_s;
recv_data_ready <= recv_data_ready_s;
xmit_buffer_ready <= xmit_buffer_ready_s;
init: process (clk)
function LCR_lower_7 return std_logic_vector is
variable rv : std_logic_vector(6 downto 0) := "0000000";
begin
rv(6 downto 5) := "00";
if parity_is_even then
rv(4) := '1';
else
rv(4) := '0';
end if;
if has_parity then
rv(3) := '1';
else
rv(3) := '0';
end if;
if stop_bits = 2 then
rv(2) := '1';
else
rv(2) := '0';
end if;
rv(1 downto 0) := std_logic_vector(to_unsigned(word_length - 5,2));
return rv;
end function LCR_lower_7;
procedure uart_read(addr : in std_logic_vector(2 downto 0)) is
-- To effect a read from the UART:
-- 1. Set the address of the register to read from and set CS.
-- 2. Wait one clock cycle.
-- 3. Set RD.
-- 4. Wait one clock cycle.
-- 5. Read the data from DOUT and clear CS and RD.
begin
case read_stage is
when read_set_addr =>
ADDR_s <= addr;
CS_s <= '1';
read_stage <= read_enable;
when read_enable =>
RD_s <= '1';
read_stage <= read_get_data;
when read_get_data =>
data_out_waiting <= '1';
data_out_s <= uart_dout;
read_stage <= read_end;
when read_end =>
CS_s <= '0';
RD_s <= '0';
when others => null;
end case;
end procedure uart_read;
procedure uart_write(addr : in std_logic_vector(2 downto 0);
data : in std_logic_vector(7 downto 0)) is
-- To effect a write to the UART:
-- 1. Set the address of the register to read from, put the data to write
-- on DIN (to persist for at least 2 clock cycles), and set CS.
-- 2. Wait one clock cycle.
-- 3. Set WR.
-- 4. Wait one clock cycle.
-- 5. Clear CS and WR.
begin
case write_stage is
when write_set_addr =>
ADDR_s <= addr;
data_in_s <= data;
CS_s <= '1';
write_stage <= write_enable;
when write_enable =>
WR_s <= '1';
write_stage <= write_end;
when write_end =>
CS_s <= '0';
WR_s <= '0';
data_in_s <= (others => '0');
when others => null;
end case;
end procedure uart_write;
begin -- process init
-- if rising_edge(clk) then
-- if rst = '1' then
-- rst_s <= '1';
-- init_stage <= start;
-- xmit_buffer_ready_s <= '0';
-- recv_data_ready_s <= '0';
-- end if;
-- els
if falling_edge(clk) then
case init_stage is
when start =>
rst_s <= '1';
xmit_buffer_ready_s <= '0';
recv_data_ready_s <= '0';
init_stage <= open_divisor_latch;
when open_divisor_latch =>
rst_s <= '0';
-- Set line control register (LCR) to enable setting the baud
-- divisor.
uart_write("011","10000000");
if write_stage = write_end then
write_stage <= write_set_addr;
init_stage <= set_baud_divisor_lsb;
end if;
when set_baud_divisor_lsb =>
-- Set divisor latch LSB (DLL). Default: "00000001"
uart_write("000",baud_divisor_c(7 downto 0));
if write_stage = write_end then
write_stage <= write_set_addr;
init_stage <= set_baud_divisor_msb;
end if;
when set_baud_divisor_msb =>
-- Set divisor latch MSB (DLM). Default: "00000000"
uart_write("001","00000000");
if write_stage = write_end then
write_stage <= write_set_addr;
init_stage <= close_divisor_latch;
end if;
when close_divisor_latch =>
-- Set line control register (LCR) to disable setting the baud
-- divisor, and to set the word length, parity, and stop bit
-- configuration to the proper values.
uart_write("011","0" & LCR_lower_7);
if write_stage = write_end then
write_stage <= write_set_addr;
init_stage <= set_trigger_levels;
end if;
when set_trigger_levels =>
-- Set FIFO control register (FCR) to enable and reset the FIFOs.
uart_write("010","00000111");
if write_stage = write_end then
write_stage <= write_set_addr;
init_stage <= set_interrupts;
end if;
when set_interrupts =>
-- Set interrupt enable register (IER) to disable all interrupts
-- except "Received Data Available."
uart_write("001","00000001");
if write_stage = write_end then
write_stage <= write_set_addr;
init_stage <= waiting;
end if;
when waiting =>
ADDR_s <= "000";
-- If the FIFO has a byte available and the local buffer is
-- empty, put the byte in the local buffer.
if data_out_waiting = '0' and IRQ_s = '1' then
init_stage <= reading;
data_in_s <= (others => '0');
xmit_buffer_ready_s <= '0';
recv_data_ready_s <= '0';
-- If the local buffer is full and 'was_read' is high,
-- empty the buffer.
elsif data_out_waiting <= '1' and was_read = '1' then
data_out_waiting <= '0';
recv_data_ready_s <= '0';
data_in_s <= (others => '0');
-- If no read activity is occurring and 'xmit_enable'
-- is high, queue DIN for transmission.
elsif was_read = '0' and xmit_enable = '1' then
init_stage <= writing;
data_in_s <= din;
recv_data_ready_s <= '0';
xmit_buffer_ready_s <= '0';
else
recv_data_ready_s <= data_out_waiting;
xmit_buffer_ready_s <= '1';
data_in_s <= (others => '0');
if data_out_waiting = '0' then
data_out_s <= (others => '0');
end if;
end if;
when reading =>
uart_read("000");
if read_stage = read_end then
if was_read = '0' then
read_stage <= read_set_addr;
init_stage <= waiting;
end if;
end if;
when writing =>
uart_write("000",data_in_s);
if write_stage = write_end and xmit_enable = '0' then
data_in_s <= (others => '0');
write_stage <= write_set_addr;
init_stage <= waiting;
end if;
when others => null;
end case;
end if;
end process init;
end Behavioral;
| lgpl-3.0 | c2d1f7973b09c3ddf8748953592b4600 | 0.482134 | 4.087518 | false | false | false | false |
dpolad/dlx | DLX_vhd/useless/fakealu.vhd | 1 | 3,133 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.myTypes.all;
entity fakeALU is
generic (
DATA_SIZE : integer := 32);
port (
IN1 : in std_logic_vector(DATA_SIZE - 1 downto 0);
IN2 : in std_logic_vector(DATA_SIZE - 1 downto 0);
OP : in AluOp;
DOUT : out std_logic_vector(DATA_SIZE - 1 downto 0);
ZEROUT : out std_logic;
stall_o : out std_logic;
Clock : in std_logic;
Reset : in std_logic
);
end fakeALU;
architecture Bhe of fakealu is
component fake_mult
port (
IN1 : in std_logic_vector(31 downto 0);
IN2 : in std_logic_vector(31 downto 0);
DOUT : out std_logic_vector(31 downto 0);
stall_o : out std_logic;
enable : in std_logic;
Clock : in std_logic;
Reset : in std_logic
);
end component;
signal enable2mult : std_logic := '0';
signal multDATA : std_logic_vector(31 downto 0);
begin
MULT: fake_mult port Map(
IN1 => IN1,
IN2 => IN2,
DOUT => multDATA,
stall_o => stall_o,
enable => enable2mult,
Clock => Clock,
Reset => Reset
);
ZEROUT <= '0';
process(IN1,IN2,OP,multDATA)
begin
case OP is
when NOP => DOUT <= (others => '0');
when SLLS => DOUT <= (others => '0');
when SRLS => DOUT <= (others => '0');
when SRAS => DOUT <= (others => '0');
when ADDS => DOUT <= std_logic_vector(signed(IN1)+signed(IN2));
when ADDUS => DOUT <= std_logic_vector(unsigned(IN1)+unsigned(IN2));
when SUBS => DOUT <= std_logic_vector(signed(IN1)-signed(IN2));
when SUBUS => DOUT <= std_logic_vector(unsigned(IN1)-unsigned(IN2));
when ANDS => DOUT <= IN1 and IN2;
when ORS => DOUT <= IN1 or IN2;
when XORS => DOUT <= IN1 xor IN2;
when SEQS =>
if(IN1 = IN2) then
DOUT <= X"00000001";
else
DOUT <= X"00000000";
end if;
when SNES =>
if(IN1 /= IN2) then
DOUT <= X"00000001";
else
DOUT <= X"00000000";
end if;
when SLTS =>
if(signed(IN1) < signed(IN2)) then
DOUT <= X"00000001";
else
DOUT <= X"00000000";
end if;
when SGTS => DOUT <= (others => '0');
when SLES =>
if(signed(IN1) <= signed(IN2)) then
DOUT <= X"00000001";
else
DOUT <= X"00000000";
end if;
when SGES =>
if(signed(IN1) >= signed(IN2)) then
DOUT <= X"00000001";
else
DOUT <= X"00000000";
end if;
when MOVI2SS => DOUT <= (others => '0');
when MOVS2IS => DOUT <= (others => '0');
when MOVFS => DOUT <= (others => '0');
when MOVDS => DOUT <= (others => '0');
when MOVFP2IS => DOUT <= (others => '0');
when MOVI2FP => DOUT <= (others => '0');
when MOVI2TS => DOUT <= (others => '0');
when MOVT2IS => DOUT <= (others => '0');
when SLTUS => DOUT <= (others => '0');
when SGTUS => DOUT <= (others => '0');
when SLEUS => DOUT <= (others => '0');
when SGEUS => DOUT <= (others => '0');
when MULTU =>
DOUT <= multDATA;
enable2mult <= '1';
when others => DOUT <= (others => '0');
end case;
end process;
end Bhe;
| bsd-2-clause | da74e52f133f7efb1fe4311621988a56 | 0.541334 | 3.190428 | false | false | false | false |
rodrigofegui/UnB | 2017.1/Organização e Arquitetura de Computadores/Trabalhos/Projeto Final/Codificação/alu.vhd | 2 | 5,591 | --Módulo para ULA
--Declaracao de bibliotecas
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--Declaracao da entidade ALU (ULA)
entity alu is
generic (DATA_WIDTH : natural := 32); --ULA faz operacoes com dados de 32 bits
port (
--entrada de dados com 32 bits
input1, input2, input3 : in std_logic_vector(DATA_WIDTH-1 downto 0) :=(others =>'0');
--codigo da operacao formado de 4 bits
operation : in std_logic_vector(3 downto 0) :=(others =>'0');
--saida de dados com 32 bits
output : out std_logic_vector(DATA_WIDTH-1 downto 0) :=(others =>'0');
--saidas zero (indica se output vale zero) e negative (indica se output e negativo)
zero, negative : out std_logic;
--saidas carry(ultimo carry na soma) e overflow(ativa quando resultado da soma
--ou subtracao excede o tamanho da palavra)
carry, overflow : out std_logic
);
end entity alu;
--Declaracao da arquitetura
architecture Behavioral of alu is
--ambos os sinais declarados abaixo sao utilizados na operacao SLT
signal slt_set_1 : integer := 1;
signal slt_set_0 : integer := 0;
begin
process(input1, input2, operation)--processo para operacoes e sua lista de sensibilidade
variable aux_aritm: std_ulogic_vector(DATA_WIDTH downto 0);--vetor de 33 bits, o MSB armazena carry da soma
variable aux_overflow: std_logic_vector(2 downto 0); --armazena os bits mais significativos do input1, input 2 e output
--na seguinte ordem (MSB_input1,MSB_input2,MSB_output)
variable aux_output: std_logic_vector(DATA_WIDTH-1 downto 0);--armazena momentaneamente a saida output
begin
--inicializacao das saidas com 0
negative <= '0';
zero <= '0';
carry <= '0';
overflow <= '0';
case operation is
when "0000" => --AND
aux_output := input1 and input2;
output <= aux_output;
when "0001" => --OR
aux_output := input1 or input2;
output <= aux_output;
when "0010" => --ADD
--conversoes entre tipos sao necessarias para obter aux_output
aux_output := std_logic_vector(signed(input1) + signed(input2));
--define output
output <= aux_output;
--conversoes entre tipos sao necessarias para obter aux_aritm
--aux_aritm faz a operacao e armazena o carry em seu MSB
aux_aritm := std_ulogic_vector(resize(signed(input1), aux_aritm'length) + resize(signed(input2), aux_aritm'length));
--CARRY OUT sera o MSB de aux_aritm
carry <= aux_aritm(DATA_WIDTH);
--Montar vetor para analisar overflow
aux_overflow := input1(input1'high) & input2(input2'high) & aux_aritm(DATA_WIDTH-1);
case aux_overflow is
when "001"|"110" =>
--overflow, na soma, ocorre quando
-- soma de dois positivos resulta em negativo ou
-- soma de dois negativos resulta em positivo
overflow <= '1';
when others =>
overflow <= '0';--nao ocorre overflow
end case;
when "0011" => --SUB
--conversoes entre tipos sao necessarias para obter aux_output
aux_output := std_logic_vector(signed(input1) - signed(input2));
--define output
output <= aux_output;
aux_aritm := std_ulogic_vector(resize(signed(input1), aux_aritm'length) - resize(signed(input2), aux_aritm'length));
--Montar vetor para analisar overflow
aux_overflow := input1(input1'high) & input2(input2'high) & aux_aritm(DATA_WIDTH-1);
case aux_overflow is
when "011"|"100" =>
--overflow, na subtracao, ocorre quando
-- subtraimos um negativo de um positivo e obtemos negativo ou
-- subtraimos um positivo de um negativo e obtemos positivo
overflow <= '1';
when others =>
overflow <= '0';--nao ocorre overflow
end case;
when "0100" => --SLT
if signed(input1) < signed(input2) then
aux_output := std_logic_vector(to_unsigned(slt_set_1, aux_output'length));
output <= aux_output; --SLT valido, setar output com 1
else
aux_output := std_logic_vector(to_unsigned(slt_set_0, aux_output'length));
output <= aux_output; --SLT nao valido, setar output com 0
end if;
when "0101" => --NOR
aux_output := input1 nor input2;
output <= aux_output;
when "0110" => --XOR
aux_output := input1 xor input2;
output <= aux_output;
when "0111" => --SLL
--sao necessarias conversoes para efetuar shift_left
aux_output := std_logic_vector(shift_left(unsigned(input2), to_integer(unsigned(input3))));
output <= aux_output;
when "1000" => --SRL
--sao necessarias conversoes para efetuar shift_right
aux_output := std_logic_vector(shift_right(unsigned(input2), to_integer(unsigned(input3))));
output <= aux_output;
when "1001" => --SRA
--funcao "sra" so funciona com vetores de bits, logo precisa de conversao entre tipos
aux_output := to_stdlogicvector(to_bitvector(input2) sra to_integer(unsigned(input3)));
output <= aux_output;
when others => --Demais casos
NULL;
end case;
--analise do sinal e valor da saida
if (to_integer(signed(aux_output)) <= 0) then
if (to_integer(signed(aux_output)) = 0) then
--saida zero ativa quando output for nulo
zero <= '1';
else
--saida negative ativa quando output for negativo
negative <= '1';
end if;
end if;
end process; --termino do processo
end Behavioral; | gpl-3.0 | 55b37fd63ca31e20f971ea78e2fba368 | 0.632021 | 3.38173 | false | false | false | false |
Hyperion302/omega-cpu | Hardware/Omega/MemoryController_TB.vhd | 1 | 3,945 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:29:38 11/03/2016
-- Design Name:
-- Module Name: /home/student1/Documents/Omega/CPU/Hardware/Omega/MemoryController_TB.vhd
-- Project Name: Omega
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: MemoryController
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY MemoryController_TB IS
END MemoryController_TB;
ARCHITECTURE behavior OF MemoryController_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT MemoryController
PORT(
CLK : IN std_logic;
Address : IN std_logic_vector(31 downto 0);
Enable : IN std_logic;
ToWrite : IN std_logic_vector(31 downto 0);
FromRead : OUT std_logic_vector(31 downto 0);
Instruction : IN std_logic_vector(31 downto 0);
Reset : IN std_logic;
Done : OUT std_logic;
SRAM_addr : OUT std_logic_vector(20 downto 0);
SRAM_OE : OUT std_logic;
SRAM_CE : OUT std_logic;
SRAM_WE : OUT std_logic;
SRAM_data : INOUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal Address : std_logic_vector(31 downto 0) := (others => '0');
signal Enable : std_logic := '0';
signal ToWrite : std_logic_vector(31 downto 0) := (others => '0');
signal Instruction : std_logic_vector(31 downto 0) := (others => '0');
signal Reset : std_logic := '0';
--BiDirs
signal SRAM_data : std_logic_vector(7 downto 0);
--Outputs
signal FromRead : std_logic_vector(31 downto 0);
signal Done : std_logic;
signal SRAM_addr : std_logic_vector(20 downto 0);
signal SRAM_OE : std_logic;
signal SRAM_CE : std_logic;
signal SRAM_WE : std_logic;
-- Clock period definitions
constant CLK_period : time := 31.25 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: MemoryController PORT MAP (
CLK => CLK,
Address => Address,
Enable => Enable,
ToWrite => ToWrite,
FromRead => FromRead,
Instruction => Instruction,
Reset => Reset,
Done => Done,
SRAM_addr => SRAM_addr,
SRAM_OE => SRAM_OE,
SRAM_CE => SRAM_CE,
SRAM_WE => SRAM_WE,
SRAM_data => SRAM_data
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
data_proc: process
begin
sram_data <= (others => 'Z');
wait until falling_edge(SRAM_oe);
sram_data <= "00000000";
wait for 9 ns;
sram_data <= "01011010";
wait until SRAM_oe = '1';
end process data_proc;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait until SRAM_we = '1';
wait for CLK_period*10;
enable <= '1';
instruction <= "00010000000000000000000000000000";
address <= "00000000000000000000000000000100";
wait until done = '1';
enable <= '0';
-- insert stimulus here
wait;
end process;
END;
| lgpl-3.0 | d3bc8f68276ad0162c3bd781c51a8a7e | 0.593156 | 3.841285 | false | false | false | false |
Hyperion302/omega-cpu | Hardware/Omega/ipcore_dir/UARTClockManager/example_design/UARTClockManager_exdes.vhd | 1 | 6,747 | -- file: UARTClockManager_exdes.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard example design
------------------------------------------------------------------------------
-- This example design instantiates the created clocking network, where each
-- output clock drives a counter. The high bit of each counter is ported.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity UARTClockManager_exdes is
generic (
TCQ : in time := 100 ps);
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
CLK_OUT : out std_logic_vector(2 downto 1) ;
-- High bits of counters driven by clocks
COUNT : out std_logic_vector(2 downto 1);
-- Status and control signals
RESET : in std_logic
);
end UARTClockManager_exdes;
architecture xilinx of UARTClockManager_exdes is
-- Parameters for the counters
---------------------------------
-- Counter width
constant C_W : integer := 16;
-- Number of counters
constant NUM_C : integer := 2;
-- Array typedef
type ctrarr is array (1 to NUM_C) of std_logic_vector(C_W-1 downto 0);
-- Reset for counters when lock status changes
signal reset_int : std_logic := '0';
-- Declare the clocks and counters
signal clk : std_logic_vector(NUM_C downto 1);
signal clk_int : std_logic_vector(NUM_C downto 1);
signal clk_n : std_logic_vector(NUM_C downto 1);
signal counter : ctrarr := (( others => (others => '0')));
signal rst_sync : std_logic_vector(NUM_C downto 1);
signal rst_sync_int : std_logic_vector(NUM_C downto 1);
signal rst_sync_int1 : std_logic_vector(NUM_C downto 1);
signal rst_sync_int2 : std_logic_vector(NUM_C downto 1);
component UARTClockManager is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic;
-- Status and control signals
RESET : in std_logic
);
end component;
begin
-- Create reset for the counters
reset_int <= RESET or COUNTER_RESET;
counters_1: for count_gen in 1 to NUM_C generate begin
process (clk(count_gen), reset_int) begin
if (reset_int = '1') then
rst_sync(count_gen) <= '1';
rst_sync_int(count_gen) <= '1';
rst_sync_int1(count_gen) <= '1';
rst_sync_int2(count_gen) <= '1';
elsif (clk(count_gen) 'event and clk(count_gen)='1') then
rst_sync(count_gen) <= '0';
rst_sync_int(count_gen) <= rst_sync(count_gen);
rst_sync_int1(count_gen) <= rst_sync_int(count_gen);
rst_sync_int2(count_gen) <= rst_sync_int1(count_gen);
end if;
end process;
end generate counters_1;
-- Instantiation of the clocking network
----------------------------------------
clknetwork : UARTClockManager
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
-- Clock out ports
CLK_OUT1 => clk_int(1),
CLK_OUT2 => clk_int(2),
-- Status and control signals
RESET => RESET);
gen_outclk_oddr:
for clk_out_pins in 1 to NUM_C generate
begin
clk_n(clk_out_pins) <= not clk(clk_out_pins);
clkout_oddr : ODDR2
port map
(Q => CLK_OUT(clk_out_pins),
C0 => clk(clk_out_pins),
C1 => clk_n(clk_out_pins),
CE => '1',
D0 => '1',
D1 => '0',
R => '0',
S => '0');
end generate;
-- Connect the output clocks to the design
-------------------------------------------
clk(1) <= clk_int(1);
clk(2) <= clk_int(2);
-- Output clock sampling
-------------------------------------
counters: for count_gen in 1 to NUM_C generate begin
process (clk(count_gen), rst_sync_int2(count_gen)) begin
if (rst_sync_int2(count_gen) = '1') then
counter(count_gen) <= (others => '0') after TCQ;
elsif (rising_edge (clk(count_gen))) then
counter(count_gen) <= counter(count_gen) + 1 after TCQ;
end if;
end process;
-- alias the high bit of each counter to the corresponding
-- bit in the output bus
COUNT(count_gen) <= counter(count_gen)(C_W-1);
end generate counters;
end xilinx;
| lgpl-3.0 | 37620e00e29debea67f1f19cfe19066c | 0.625167 | 3.882048 | false | false | false | false |
dpolad/dlx | DLX_vhd/a.d-FETCHREGS.vhd | 2 | 1,163 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--use work.myTypes.all;
entity fetch_regs is
generic (
SIZE : integer := 32
);
port (
NPCF_i : in std_logic_vector(SIZE - 1 downto 0);
IR_i : in std_logic_vector(SIZE - 1 downto 0);
NPCF_o : out std_logic_vector(SIZE - 1 downto 0);
IR_o : out std_logic_vector(SIZE - 1 downto 0);
stall_i : in std_logic;
clk : in std_logic;
rst : in std_logic
);
end fetch_regs;
architecture struct of fetch_regs is
component ff32_en
port(
D : in std_logic_vector(SIZE - 1 downto 0);
Q : out std_logic_vector(SIZE - 1 downto 0);
en : in std_logic;
clk : in std_logic;
rst : in std_logic
);
end component;
component ff32_en_IR
port(
D : in std_logic_vector(SIZE - 1 downto 0);
Q : out std_logic_vector(SIZE - 1 downto 0);
en : in std_logic;
clk : in std_logic;
rst : in std_logic
);
end component;
signal enable : std_logic;
begin
enable <= not stall_i;
NPCF: ff32_en port map(
D => NPCF_i,
Q => NPCF_o,
en => enable,
clk => clk,
rst => rst);
IR: ff32_en_IR port map(
D => IR_i,
Q => IR_o,
en => enable,
clk => clk,
rst => rst);
end struct;
| bsd-2-clause | 1823568bd35c435dd279125210bc3b87 | 0.625107 | 2.316733 | false | false | false | false |
dpolad/dlx | DLX_synth/postsynth/execute_block_1300.vhdl | 1 | 449,069 |
library IEEE;
use IEEE.std_logic_1164.all;
package CONV_PACK_execute_block is
-- define attributes
attribute ENUM_ENCODING : STRING;
-- define any necessary types
type aluOp is (NOP, SLLS, SRLS, SRAS, ADDS, ADDUS, SUBS, SUBUS, ANDS, ORS,
XORS, SEQS, SNES, SLTS, SGTS, SLES, SGES, MOVI2SS, MOVS2IS, MOVFS, MOVDS,
MOVFP2IS, MOVI2FP, MOVI2TS, MOVT2IS, SLTUS, SGTUS, SLEUS, SGEUS, MULTU,
MULTS);
attribute ENUM_ENCODING of aluOp : type is
"00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110";
-- Declarations for conversion functions.
function aluOp_to_std_logic_vector(arg : in aluOp) return std_logic_vector;
end CONV_PACK_execute_block;
package body CONV_PACK_execute_block is
-- enum type to std_logic_vector function
function aluOp_to_std_logic_vector(arg : in aluOp) return std_logic_vector
is
-- synopsys built_in SYN_FEED_THRU;
begin
case arg is
when NOP => return "00000";
when SLLS => return "00001";
when SRLS => return "00010";
when SRAS => return "00011";
when ADDS => return "00100";
when ADDUS => return "00101";
when SUBS => return "00110";
when SUBUS => return "00111";
when ANDS => return "01000";
when ORS => return "01001";
when XORS => return "01010";
when SEQS => return "01011";
when SNES => return "01100";
when SLTS => return "01101";
when SGTS => return "01110";
when SLES => return "01111";
when SGES => return "10000";
when MOVI2SS => return "10001";
when MOVS2IS => return "10010";
when MOVFS => return "10011";
when MOVDS => return "10100";
when MOVFP2IS => return "10101";
when MOVI2FP => return "10110";
when MOVI2TS => return "10111";
when MOVT2IS => return "11000";
when SLTUS => return "11001";
when SGTUS => return "11010";
when SLEUS => return "11011";
when SGEUS => return "11100";
when MULTU => return "11101";
when MULTS => return "11110";
when others => assert FALSE -- this should not happen.
report "un-convertible value"
severity warning;
return "00000";
end case;
end;
end CONV_PACK_execute_block;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_63 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_63;
architecture SYN_BEHAVIORAL of FA_63 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_62 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_62;
architecture SYN_BEHAVIORAL of FA_62 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_61 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_61;
architecture SYN_BEHAVIORAL of FA_61 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U1 : XNOR2_X1 port map( A => Ci, B => n3, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n3);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_60 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_60;
architecture SYN_BEHAVIORAL of FA_60 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component OR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
begin
U1 : OR2_X1 port map( A1 => A, A2 => B, ZN => Co);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => S);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_59 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_59;
architecture SYN_BEHAVIORAL of FA_59 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component OR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
signal n3, n4, n5, n6 : std_logic;
begin
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U2 : OR2_X1 port map( A1 => B, A2 => A, ZN => n5);
U3 : NAND2_X1 port map( A1 => Ci, A2 => n5, ZN => n3);
U4 : NAND2_X1 port map( A1 => n3, A2 => n4, ZN => Co);
U5 : NAND2_X1 port map( A1 => B, A2 => A, ZN => n4);
U6 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_58 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_58;
architecture SYN_BEHAVIORAL of FA_58 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U3 : NAND2_X1 port map( A1 => n4, A2 => n5, ZN => Co);
U2 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n5);
U4 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n4);
U5 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_57 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_57;
architecture SYN_BEHAVIORAL of FA_57 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U1 : XNOR2_X1 port map( A => Ci, B => n3, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n3);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_56 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_56;
architecture SYN_BEHAVIORAL of FA_56 is
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
begin
U1 : AND2_X1 port map( A1 => A, A2 => B, ZN => Co);
U2 : XOR2_X1 port map( A => B, B => A, Z => S);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_55 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_55;
architecture SYN_BEHAVIORAL of FA_55 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_54 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_54;
architecture SYN_BEHAVIORAL of FA_54 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_53 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_53;
architecture SYN_BEHAVIORAL of FA_53 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U1 : XNOR2_X1 port map( A => Ci, B => n3, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n3);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_52 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_52;
architecture SYN_BEHAVIORAL of FA_52 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component OR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
begin
U1 : OR2_X1 port map( A1 => B, A2 => A, ZN => Co);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => S);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_51 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_51;
architecture SYN_BEHAVIORAL of FA_51 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_50 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_50;
architecture SYN_BEHAVIORAL of FA_50 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_49 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_49;
architecture SYN_BEHAVIORAL of FA_49 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U1 : XNOR2_X1 port map( A => Ci, B => n3, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n3);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_48 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_48;
architecture SYN_BEHAVIORAL of FA_48 is
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
begin
U1 : AND2_X1 port map( A1 => A, A2 => B, ZN => Co);
U2 : XOR2_X1 port map( A => A, B => B, Z => S);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_47 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_47;
architecture SYN_BEHAVIORAL of FA_47 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n5, n6, n7 : std_logic;
begin
U3 : NAND2_X1 port map( A1 => n6, A2 => n5, ZN => Co);
U1 : XNOR2_X1 port map( A => Ci, B => n7, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n7);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n5);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n6);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_46 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_46;
architecture SYN_BEHAVIORAL of FA_46 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_45 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_45;
architecture SYN_BEHAVIORAL of FA_45 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U1 : XNOR2_X1 port map( A => Ci, B => n3, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n3);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_44 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_44;
architecture SYN_BEHAVIORAL of FA_44 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component OR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
begin
U1 : OR2_X1 port map( A1 => A, A2 => B, ZN => Co);
U2 : XNOR2_X1 port map( A => A, B => B, ZN => S);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_43 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_43;
architecture SYN_BEHAVIORAL of FA_43 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_42 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_42;
architecture SYN_BEHAVIORAL of FA_42 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_41 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_41;
architecture SYN_BEHAVIORAL of FA_41 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U1 : XNOR2_X1 port map( A => Ci, B => n3, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n3);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_40 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_40;
architecture SYN_BEHAVIORAL of FA_40 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U1 : XOR2_X1 port map( A => B, B => A, Z => S);
U2 : AND2_X1 port map( A1 => B, A2 => A, ZN => Co);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_39 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_39;
architecture SYN_BEHAVIORAL of FA_39 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_38 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_38;
architecture SYN_BEHAVIORAL of FA_38 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_37 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_37;
architecture SYN_BEHAVIORAL of FA_37 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n4 : std_logic;
begin
U1 : XNOR2_X1 port map( A => Ci, B => n4, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n4);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_36 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_36;
architecture SYN_BEHAVIORAL of FA_36 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component OR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
begin
U1 : OR2_X1 port map( A1 => A, A2 => B, ZN => Co);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => S);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_35 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_35;
architecture SYN_BEHAVIORAL of FA_35 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_34 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_34;
architecture SYN_BEHAVIORAL of FA_34 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_33 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_33;
architecture SYN_BEHAVIORAL of FA_33 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n4 : std_logic;
begin
U1 : XNOR2_X1 port map( A => Ci, B => n4, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n4);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_32 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_32;
architecture SYN_BEHAVIORAL of FA_32 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U1 : XOR2_X1 port map( A => B, B => A, Z => S);
U2 : AND2_X1 port map( A1 => B, A2 => A, ZN => Co);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_31 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_31;
architecture SYN_BEHAVIORAL of FA_31 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_30 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_30;
architecture SYN_BEHAVIORAL of FA_30 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U2 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U4 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_29 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_29;
architecture SYN_BEHAVIORAL of FA_29 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U1 : XNOR2_X1 port map( A => Ci, B => n3, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n3);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_28 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_28;
architecture SYN_BEHAVIORAL of FA_28 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component OR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
begin
U1 : OR2_X1 port map( A1 => A, A2 => B, ZN => Co);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => S);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_27 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_27;
architecture SYN_BEHAVIORAL of FA_27 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_26 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_26;
architecture SYN_BEHAVIORAL of FA_26 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U2 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U4 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_25 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_25;
architecture SYN_BEHAVIORAL of FA_25 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U1 : XNOR2_X1 port map( A => Ci, B => n3, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n3);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_24 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_24;
architecture SYN_BEHAVIORAL of FA_24 is
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
begin
U1 : AND2_X1 port map( A1 => A, A2 => B, ZN => Co);
U2 : XOR2_X1 port map( A => B, B => A, Z => S);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_23 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_23;
architecture SYN_BEHAVIORAL of FA_23 is
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U2 : OAI21_X1 port map( B1 => B, B2 => A, A => Ci, ZN => n5);
U4 : XNOR2_X1 port map( A => A, B => B, ZN => n6);
U5 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_22 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_22;
architecture SYN_BEHAVIORAL of FA_22 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_21 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_21;
architecture SYN_BEHAVIORAL of FA_21 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U1 : XNOR2_X1 port map( A => Ci, B => n3, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n3);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_20 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_20;
architecture SYN_BEHAVIORAL of FA_20 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component OR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
begin
U1 : OR2_X1 port map( A1 => B, A2 => A, ZN => Co);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => S);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_19 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_19;
architecture SYN_BEHAVIORAL of FA_19 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U1 : OAI21_X1 port map( B1 => B, B2 => A, A => Ci, ZN => n5);
U2 : XNOR2_X1 port map( A => A, B => B, ZN => n6);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U5 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_18 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_18;
architecture SYN_BEHAVIORAL of FA_18 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_17 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_17;
architecture SYN_BEHAVIORAL of FA_17 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U1 : XNOR2_X1 port map( A => Ci, B => n3, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n3);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_16 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_16;
architecture SYN_BEHAVIORAL of FA_16 is
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
begin
U1 : AND2_X1 port map( A1 => A, A2 => B, ZN => Co);
U2 : XOR2_X1 port map( A => B, B => A, Z => S);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_15 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_15;
architecture SYN_BEHAVIORAL of FA_15 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_14 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_14;
architecture SYN_BEHAVIORAL of FA_14 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_13 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_13;
architecture SYN_BEHAVIORAL of FA_13 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U1 : XNOR2_X1 port map( A => Ci, B => n3, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n3);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_12 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_12;
architecture SYN_BEHAVIORAL of FA_12 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component OR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
begin
U1 : OR2_X1 port map( A1 => B, A2 => A, ZN => Co);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => S);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_11 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_11;
architecture SYN_BEHAVIORAL of FA_11 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_10 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_10;
architecture SYN_BEHAVIORAL of FA_10 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_9 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_9;
architecture SYN_BEHAVIORAL of FA_9 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U1 : XNOR2_X1 port map( A => Ci, B => n3, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n3);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_8 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_8;
architecture SYN_BEHAVIORAL of FA_8 is
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
begin
U1 : AND2_X1 port map( A1 => A, A2 => B, ZN => Co);
U2 : XOR2_X1 port map( A => B, B => A, Z => S);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_7 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_7;
architecture SYN_BEHAVIORAL of FA_7 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_6 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_6;
architecture SYN_BEHAVIORAL of FA_6 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_5 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_5;
architecture SYN_BEHAVIORAL of FA_5 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n3);
U1 : XNOR2_X1 port map( A => Ci, B => n3, ZN => S);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_4 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_4;
architecture SYN_BEHAVIORAL of FA_4 is
component OR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
begin
U2 : XNOR2_X1 port map( A => B, B => A, ZN => S);
U1 : OR2_X1 port map( A1 => B, A2 => A, ZN => Co);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_3 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_3;
architecture SYN_BEHAVIORAL of FA_3 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_2 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_2;
architecture SYN_BEHAVIORAL of FA_2 is
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_1 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_1;
architecture SYN_BEHAVIORAL of FA_1 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n3);
U1 : XNOR2_X1 port map( A => Ci, B => n3, ZN => S);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity mux21_SIZE4_7 is
port( IN0, IN1 : in std_logic_vector (3 downto 0); CTRL : in std_logic;
OUT1 : out std_logic_vector (3 downto 0));
end mux21_SIZE4_7;
architecture SYN_Bhe of mux21_SIZE4_7 is
component MUX2_X1
port( A, B, S : in std_logic; Z : out std_logic);
end component;
begin
U1 : MUX2_X1 port map( A => IN0(3), B => IN1(3), S => CTRL, Z => OUT1(3));
U2 : MUX2_X1 port map( A => IN0(2), B => IN1(2), S => CTRL, Z => OUT1(2));
U3 : MUX2_X1 port map( A => IN0(1), B => IN1(1), S => CTRL, Z => OUT1(1));
U4 : MUX2_X1 port map( A => IN0(0), B => IN1(0), S => CTRL, Z => OUT1(0));
end SYN_Bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity mux21_SIZE4_6 is
port( IN0, IN1 : in std_logic_vector (3 downto 0); CTRL : in std_logic;
OUT1 : out std_logic_vector (3 downto 0));
end mux21_SIZE4_6;
architecture SYN_Bhe of mux21_SIZE4_6 is
component MUX2_X1
port( A, B, S : in std_logic; Z : out std_logic);
end component;
begin
U1 : MUX2_X1 port map( A => IN0(3), B => IN1(3), S => CTRL, Z => OUT1(3));
U2 : MUX2_X1 port map( A => IN0(2), B => IN1(2), S => CTRL, Z => OUT1(2));
U3 : MUX2_X1 port map( A => IN0(1), B => IN1(1), S => CTRL, Z => OUT1(1));
U4 : MUX2_X1 port map( A => IN0(0), B => IN1(0), S => CTRL, Z => OUT1(0));
end SYN_Bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity mux21_SIZE4_5 is
port( IN0, IN1 : in std_logic_vector (3 downto 0); CTRL : in std_logic;
OUT1 : out std_logic_vector (3 downto 0));
end mux21_SIZE4_5;
architecture SYN_Bhe of mux21_SIZE4_5 is
component MUX2_X1
port( A, B, S : in std_logic; Z : out std_logic);
end component;
begin
U1 : MUX2_X1 port map( A => IN0(3), B => IN1(3), S => CTRL, Z => OUT1(3));
U2 : MUX2_X1 port map( A => IN0(2), B => IN1(2), S => CTRL, Z => OUT1(2));
U3 : MUX2_X1 port map( A => IN0(1), B => IN1(1), S => CTRL, Z => OUT1(1));
U4 : MUX2_X1 port map( A => IN0(0), B => IN1(0), S => CTRL, Z => OUT1(0));
end SYN_Bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity mux21_SIZE4_4 is
port( IN0, IN1 : in std_logic_vector (3 downto 0); CTRL : in std_logic;
OUT1 : out std_logic_vector (3 downto 0));
end mux21_SIZE4_4;
architecture SYN_Bhe of mux21_SIZE4_4 is
component MUX2_X1
port( A, B, S : in std_logic; Z : out std_logic);
end component;
begin
U2 : MUX2_X1 port map( A => IN0(2), B => IN1(2), S => CTRL, Z => OUT1(2));
U4 : MUX2_X1 port map( A => IN0(0), B => IN1(0), S => CTRL, Z => OUT1(0));
U3 : MUX2_X1 port map( A => IN0(1), B => IN1(1), S => CTRL, Z => OUT1(1));
U1 : MUX2_X1 port map( A => IN0(3), B => IN1(3), S => CTRL, Z => OUT1(3));
end SYN_Bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity mux21_SIZE4_3 is
port( IN0, IN1 : in std_logic_vector (3 downto 0); CTRL : in std_logic;
OUT1 : out std_logic_vector (3 downto 0));
end mux21_SIZE4_3;
architecture SYN_Bhe of mux21_SIZE4_3 is
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component OR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component MUX2_X1
port( A, B, S : in std_logic; Z : out std_logic);
end component;
signal n1, n2, n3, n4, n5 : std_logic;
begin
U1 : MUX2_X1 port map( A => IN0(3), B => IN1(3), S => CTRL, Z => OUT1(3));
U2 : MUX2_X1 port map( A => IN0(2), B => IN1(2), S => CTRL, Z => OUT1(2));
U3 : INV_X1 port map( A => IN0(0), ZN => n2);
U4 : OR2_X1 port map( A1 => CTRL, A2 => n4, ZN => n1);
U5 : NAND2_X1 port map( A1 => n1, A2 => n5, ZN => OUT1(1));
U6 : INV_X1 port map( A => IN0(1), ZN => n4);
U7 : NAND2_X1 port map( A1 => CTRL, A2 => IN1(0), ZN => n3);
U8 : OAI21_X1 port map( B1 => CTRL, B2 => n2, A => n3, ZN => OUT1(0));
U9 : NAND2_X1 port map( A1 => CTRL, A2 => IN1(1), ZN => n5);
end SYN_Bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity mux21_SIZE4_2 is
port( IN0, IN1 : in std_logic_vector (3 downto 0); CTRL : in std_logic;
OUT1 : out std_logic_vector (3 downto 0));
end mux21_SIZE4_2;
architecture SYN_Bhe of mux21_SIZE4_2 is
component MUX2_X1
port( A, B, S : in std_logic; Z : out std_logic);
end component;
begin
U1 : MUX2_X1 port map( A => IN0(3), B => IN1(3), S => CTRL, Z => OUT1(3));
U2 : MUX2_X1 port map( A => IN0(2), B => IN1(2), S => CTRL, Z => OUT1(2));
U3 : MUX2_X1 port map( A => IN0(0), B => IN1(0), S => CTRL, Z => OUT1(0));
U4 : MUX2_X1 port map( A => IN0(1), B => IN1(1), S => CTRL, Z => OUT1(1));
end SYN_Bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity mux21_SIZE4_1 is
port( IN0, IN1 : in std_logic_vector (3 downto 0); CTRL : in std_logic;
OUT1 : out std_logic_vector (3 downto 0));
end mux21_SIZE4_1;
architecture SYN_Bhe of mux21_SIZE4_1 is
component MUX2_X1
port( A, B, S : in std_logic; Z : out std_logic);
end component;
begin
U1 : MUX2_X1 port map( A => IN0(0), B => IN1(0), S => CTRL, Z => OUT1(0));
U2 : MUX2_X1 port map( A => IN0(3), B => IN1(3), S => CTRL, Z => OUT1(3));
U3 : MUX2_X1 port map( A => IN0(2), B => IN1(2), S => CTRL, Z => OUT1(2));
U4 : MUX2_X1 port map( A => IN0(1), B => IN1(1), S => CTRL, Z => OUT1(1));
end SYN_Bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity RCA_N4_15 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end RCA_N4_15;
architecture SYN_STRUCTURAL of RCA_N4_15 is
component FA_57
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_58
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_59
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_60
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
signal n1, CTMP_3_port, CTMP_2_port, CTMP_1_port, net561359 : std_logic;
begin
FAI_1 : FA_60 port map( A => A(0), B => B(0), Ci => n1, S => S(0), Co =>
CTMP_1_port);
FAI_2 : FA_59 port map( A => A(1), B => B(1), Ci => CTMP_1_port, S => S(1),
Co => CTMP_2_port);
FAI_3 : FA_58 port map( A => A(2), B => B(2), Ci => CTMP_2_port, S => S(2),
Co => CTMP_3_port);
FAI_4 : FA_57 port map( A => A(3), B => B(3), Ci => CTMP_3_port, S => S(3),
Co => net561359);
n1 <= '1';
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity RCA_N4_14 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end RCA_N4_14;
architecture SYN_STRUCTURAL of RCA_N4_14 is
component FA_53
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_54
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_55
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_56
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
signal n1, CTMP_3_port, CTMP_2_port, CTMP_1_port, net561358 : std_logic;
begin
FAI_1 : FA_56 port map( A => A(0), B => B(0), Ci => n1, S => S(0), Co =>
CTMP_1_port);
FAI_2 : FA_55 port map( A => A(1), B => B(1), Ci => CTMP_1_port, S => S(1),
Co => CTMP_2_port);
FAI_3 : FA_54 port map( A => A(2), B => B(2), Ci => CTMP_2_port, S => S(2),
Co => CTMP_3_port);
FAI_4 : FA_53 port map( A => A(3), B => B(3), Ci => CTMP_3_port, S => S(3),
Co => net561358);
n1 <= '0';
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity RCA_N4_13 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end RCA_N4_13;
architecture SYN_STRUCTURAL of RCA_N4_13 is
component FA_49
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_50
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_51
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_52
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
signal n1, CTMP_3_port, CTMP_2_port, CTMP_1_port, net561357 : std_logic;
begin
FAI_1 : FA_52 port map( A => A(0), B => B(0), Ci => n1, S => S(0), Co =>
CTMP_1_port);
FAI_2 : FA_51 port map( A => A(1), B => B(1), Ci => CTMP_1_port, S => S(1),
Co => CTMP_2_port);
FAI_3 : FA_50 port map( A => A(2), B => B(2), Ci => CTMP_2_port, S => S(2),
Co => CTMP_3_port);
FAI_4 : FA_49 port map( A => A(3), B => B(3), Ci => CTMP_3_port, S => S(3),
Co => net561357);
n1 <= '1';
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity RCA_N4_12 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end RCA_N4_12;
architecture SYN_STRUCTURAL of RCA_N4_12 is
component FA_45
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_46
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_47
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_48
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
signal n2, CTMP_3_port, CTMP_2_port, n1, net561356 : std_logic;
begin
FAI_1 : FA_48 port map( A => A(0), B => B(0), Ci => n2, S => S(0), Co => n1)
;
FAI_2 : FA_47 port map( A => A(1), B => B(1), Ci => n1, S => S(1), Co =>
CTMP_2_port);
FAI_3 : FA_46 port map( A => A(2), B => B(2), Ci => CTMP_2_port, S => S(2),
Co => CTMP_3_port);
FAI_4 : FA_45 port map( A => A(3), B => B(3), Ci => CTMP_3_port, S => S(3),
Co => net561356);
n2 <= '0';
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity RCA_N4_11 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end RCA_N4_11;
architecture SYN_STRUCTURAL of RCA_N4_11 is
component FA_41
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_42
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_43
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_44
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
signal n1, CTMP_3_port, CTMP_2_port, CTMP_1_port, net561355 : std_logic;
begin
FAI_1 : FA_44 port map( A => A(0), B => B(0), Ci => n1, S => S(0), Co =>
CTMP_1_port);
FAI_2 : FA_43 port map( A => A(1), B => B(1), Ci => CTMP_1_port, S => S(1),
Co => CTMP_2_port);
FAI_3 : FA_42 port map( A => A(2), B => B(2), Ci => CTMP_2_port, S => S(2),
Co => CTMP_3_port);
FAI_4 : FA_41 port map( A => A(3), B => B(3), Ci => CTMP_3_port, S => S(3),
Co => net561355);
n1 <= '1';
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity RCA_N4_10 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end RCA_N4_10;
architecture SYN_STRUCTURAL of RCA_N4_10 is
component FA_37
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_38
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_39
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_40
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
signal n2, CTMP_3_port, CTMP_2_port, CTMP_1_port, net561354 : std_logic;
begin
FAI_1 : FA_40 port map( A => A(0), B => B(0), Ci => n2, S => S(0), Co =>
CTMP_1_port);
FAI_2 : FA_39 port map( A => A(1), B => B(1), Ci => CTMP_1_port, S => S(1),
Co => CTMP_2_port);
FAI_3 : FA_38 port map( A => A(2), B => B(2), Ci => CTMP_2_port, S => S(2),
Co => CTMP_3_port);
FAI_4 : FA_37 port map( A => A(3), B => B(3), Ci => CTMP_3_port, S => S(3),
Co => net561354);
n2 <= '0';
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity RCA_N4_9 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end RCA_N4_9;
architecture SYN_STRUCTURAL of RCA_N4_9 is
component FA_33
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_34
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_35
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_36
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
signal n2, CTMP_3_port, CTMP_2_port, CTMP_1_port, net561353 : std_logic;
begin
FAI_1 : FA_36 port map( A => A(0), B => B(0), Ci => n2, S => S(0), Co =>
CTMP_1_port);
FAI_2 : FA_35 port map( A => A(1), B => B(1), Ci => CTMP_1_port, S => S(1),
Co => CTMP_2_port);
FAI_3 : FA_34 port map( A => A(2), B => B(2), Ci => CTMP_2_port, S => S(2),
Co => CTMP_3_port);
FAI_4 : FA_33 port map( A => A(3), B => B(3), Ci => CTMP_3_port, S => S(3),
Co => net561353);
n2 <= '1';
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity RCA_N4_8 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end RCA_N4_8;
architecture SYN_STRUCTURAL of RCA_N4_8 is
component FA_29
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_30
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_31
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_32
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
signal n1, CTMP_3_port, CTMP_2_port, CTMP_1_port, net561352 : std_logic;
begin
FAI_1 : FA_32 port map( A => A(0), B => B(0), Ci => n1, S => S(0), Co =>
CTMP_1_port);
FAI_2 : FA_31 port map( A => A(1), B => B(1), Ci => CTMP_1_port, S => S(1),
Co => CTMP_2_port);
FAI_3 : FA_30 port map( A => A(2), B => B(2), Ci => CTMP_2_port, S => S(2),
Co => CTMP_3_port);
FAI_4 : FA_29 port map( A => A(3), B => B(3), Ci => CTMP_3_port, S => S(3),
Co => net561352);
n1 <= '0';
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity RCA_N4_7 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end RCA_N4_7;
architecture SYN_STRUCTURAL of RCA_N4_7 is
component FA_25
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_26
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_27
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_28
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
signal n1, CTMP_3_port, CTMP_2_port, CTMP_1_port, net561351 : std_logic;
begin
FAI_1 : FA_28 port map( A => A(0), B => B(0), Ci => n1, S => S(0), Co =>
CTMP_1_port);
FAI_2 : FA_27 port map( A => A(1), B => B(1), Ci => CTMP_1_port, S => S(1),
Co => CTMP_2_port);
FAI_3 : FA_26 port map( A => A(2), B => B(2), Ci => CTMP_2_port, S => S(2),
Co => CTMP_3_port);
FAI_4 : FA_25 port map( A => A(3), B => B(3), Ci => CTMP_3_port, S => S(3),
Co => net561351);
n1 <= '1';
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity RCA_N4_6 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end RCA_N4_6;
architecture SYN_STRUCTURAL of RCA_N4_6 is
component FA_21
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_22
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_23
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_24
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
signal n1, CTMP_3_port, CTMP_2_port, CTMP_1_port, net561350 : std_logic;
begin
FAI_1 : FA_24 port map( A => A(0), B => B(0), Ci => n1, S => S(0), Co =>
CTMP_1_port);
FAI_2 : FA_23 port map( A => A(1), B => B(1), Ci => CTMP_1_port, S => S(1),
Co => CTMP_2_port);
FAI_3 : FA_22 port map( A => A(2), B => B(2), Ci => CTMP_2_port, S => S(2),
Co => CTMP_3_port);
FAI_4 : FA_21 port map( A => A(3), B => B(3), Ci => CTMP_3_port, S => S(3),
Co => net561350);
n1 <= '0';
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity RCA_N4_5 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end RCA_N4_5;
architecture SYN_STRUCTURAL of RCA_N4_5 is
component FA_17
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_18
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_19
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_20
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
signal n1, CTMP_3_port, CTMP_2_port, CTMP_1_port, net561349 : std_logic;
begin
FAI_1 : FA_20 port map( A => A(0), B => B(0), Ci => n1, S => S(0), Co =>
CTMP_1_port);
FAI_2 : FA_19 port map( A => A(1), B => B(1), Ci => CTMP_1_port, S => S(1),
Co => CTMP_2_port);
FAI_3 : FA_18 port map( A => A(2), B => B(2), Ci => CTMP_2_port, S => S(2),
Co => CTMP_3_port);
FAI_4 : FA_17 port map( A => A(3), B => B(3), Ci => CTMP_3_port, S => S(3),
Co => net561349);
n1 <= '1';
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity RCA_N4_4 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end RCA_N4_4;
architecture SYN_STRUCTURAL of RCA_N4_4 is
component FA_13
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_14
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_15
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_16
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
signal n1, CTMP_3_port, CTMP_2_port, CTMP_1_port, net561348 : std_logic;
begin
FAI_1 : FA_16 port map( A => A(0), B => B(0), Ci => n1, S => S(0), Co =>
CTMP_1_port);
FAI_2 : FA_15 port map( A => A(1), B => B(1), Ci => CTMP_1_port, S => S(1),
Co => CTMP_2_port);
FAI_3 : FA_14 port map( A => A(2), B => B(2), Ci => CTMP_2_port, S => S(2),
Co => CTMP_3_port);
FAI_4 : FA_13 port map( A => A(3), B => B(3), Ci => CTMP_3_port, S => S(3),
Co => net561348);
n1 <= '0';
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity RCA_N4_3 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end RCA_N4_3;
architecture SYN_STRUCTURAL of RCA_N4_3 is
component FA_9
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_10
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_11
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_12
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
signal n1, CTMP_3_port, CTMP_2_port, CTMP_1_port, net561347 : std_logic;
begin
FAI_1 : FA_12 port map( A => A(0), B => B(0), Ci => n1, S => S(0), Co =>
CTMP_1_port);
FAI_2 : FA_11 port map( A => A(1), B => B(1), Ci => CTMP_1_port, S => S(1),
Co => CTMP_2_port);
FAI_3 : FA_10 port map( A => A(2), B => B(2), Ci => CTMP_2_port, S => S(2),
Co => CTMP_3_port);
FAI_4 : FA_9 port map( A => A(3), B => B(3), Ci => CTMP_3_port, S => S(3),
Co => net561347);
n1 <= '1';
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity RCA_N4_2 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end RCA_N4_2;
architecture SYN_STRUCTURAL of RCA_N4_2 is
component FA_5
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_6
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_7
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_8
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
signal n1, CTMP_3_port, CTMP_2_port, CTMP_1_port, net561346 : std_logic;
begin
FAI_1 : FA_8 port map( A => A(0), B => B(0), Ci => n1, S => S(0), Co =>
CTMP_1_port);
FAI_2 : FA_7 port map( A => A(1), B => B(1), Ci => CTMP_1_port, S => S(1),
Co => CTMP_2_port);
FAI_3 : FA_6 port map( A => A(2), B => B(2), Ci => CTMP_2_port, S => S(2),
Co => CTMP_3_port);
FAI_4 : FA_5 port map( A => A(3), B => B(3), Ci => CTMP_3_port, S => S(3),
Co => net561346);
n1 <= '0';
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity RCA_N4_1 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end RCA_N4_1;
architecture SYN_STRUCTURAL of RCA_N4_1 is
component FA_1
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_2
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_3
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_4
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
signal n1, CTMP_3_port, CTMP_2_port, CTMP_1_port, net561345 : std_logic;
begin
FAI_1 : FA_4 port map( A => A(0), B => B(0), Ci => n1, S => S(0), Co =>
CTMP_1_port);
FAI_2 : FA_3 port map( A => A(1), B => B(1), Ci => CTMP_1_port, S => S(1),
Co => CTMP_2_port);
FAI_3 : FA_2 port map( A => A(2), B => B(2), Ci => CTMP_2_port, S => S(2),
Co => CTMP_3_port);
FAI_4 : FA_1 port map( A => A(3), B => B(3), Ci => CTMP_3_port, S => S(3),
Co => net561345);
n1 <= '1';
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity shift_N9_1 is
port( Clock, ALOAD : in std_logic; D : in std_logic_vector (8 downto 0);
SO : out std_logic);
end shift_N9_1;
architecture SYN_archi of shift_N9_1 is
component SDFF_X2
port( D, SI, SE, CK : in std_logic; Q, QN : out std_logic);
end component;
component SDFF_X1
port( D, SI, SE, CK : in std_logic; Q, QN : out std_logic);
end component;
signal tmp_8_port, tmp_7_port, tmp_6_port, tmp_5_port, tmp_4_port,
tmp_3_port, tmp_2_port, tmp_1_port, n2, n3, n4, n5, n6, n7, n8, n9, n10,
n11 : std_logic;
begin
tmp_reg_3_inst : SDFF_X1 port map( D => tmp_4_port, SI => D(3), SE => ALOAD,
CK => Clock, Q => tmp_3_port, QN => n11);
tmp_reg_7_inst : SDFF_X1 port map( D => tmp_8_port, SI => D(7), SE => ALOAD,
CK => Clock, Q => tmp_7_port, QN => n10);
tmp_reg_5_inst : SDFF_X1 port map( D => tmp_6_port, SI => D(5), SE => ALOAD,
CK => Clock, Q => tmp_5_port, QN => n9);
tmp_reg_4_inst : SDFF_X1 port map( D => tmp_5_port, SI => D(4), SE => ALOAD,
CK => Clock, Q => tmp_4_port, QN => n8);
tmp_reg_8_inst : SDFF_X1 port map( D => n6, SI => D(8), SE => ALOAD, CK =>
Clock, Q => tmp_8_port, QN => n7);
tmp_reg_6_inst : SDFF_X1 port map( D => tmp_7_port, SI => D(6), SE => ALOAD,
CK => Clock, Q => tmp_6_port, QN => n5);
tmp_reg_1_inst : SDFF_X1 port map( D => tmp_2_port, SI => D(1), SE => ALOAD,
CK => Clock, Q => tmp_1_port, QN => n4);
tmp_reg_2_inst : SDFF_X1 port map( D => tmp_3_port, SI => D(2), SE => ALOAD,
CK => Clock, Q => tmp_2_port, QN => n3);
tmp_reg_0_inst : SDFF_X2 port map( D => tmp_1_port, SI => D(0), SE => ALOAD,
CK => Clock, Q => SO, QN => n2);
n6 <= '0';
end SYN_archi;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity booth_encoder_8 is
port( B_in : in std_logic_vector (2 downto 0); A_out : out std_logic_vector
(2 downto 0));
end booth_encoder_8;
architecture SYN_bhe of booth_encoder_8 is
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component OAI221_X1
port( B1, B2, C1, C2, A : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component OAI33_X1
port( A1, A2, A3, B1, B2, B3 : in std_logic; ZN : out std_logic);
end component;
signal n9, n10, n11, n12 : std_logic;
begin
U9 : OAI33_X1 port map( A1 => B_in(0), A2 => B_in(1), A3 => n9, B1 => n12,
B2 => n11, B3 => B_in(2), ZN => A_out(0));
U6 : INV_X1 port map( A => B_in(1), ZN => n11);
U3 : INV_X1 port map( A => B_in(2), ZN => n9);
U4 : INV_X1 port map( A => B_in(0), ZN => n12);
U5 : OAI221_X1 port map( B1 => B_in(1), B2 => n12, C1 => n11, C2 => B_in(2),
A => n10, ZN => A_out(2));
U7 : NAND2_X1 port map( A1 => B_in(2), A2 => n12, ZN => n10);
U8 : AOI21_X1 port map( B1 => B_in(0), B2 => B_in(1), A => n9, ZN =>
A_out(1));
end SYN_bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity booth_encoder_7 is
port( B_in : in std_logic_vector (2 downto 0); A_out : out std_logic_vector
(2 downto 0));
end booth_encoder_7;
architecture SYN_bhe of booth_encoder_7 is
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component OAI221_X1
port( B1, B2, C1, C2, A : in std_logic; ZN : out std_logic);
end component;
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component OAI33_X1
port( A1, A2, A3, B1, B2, B3 : in std_logic; ZN : out std_logic);
end component;
signal n8, n9, n10, n11 : std_logic;
begin
U9 : OAI33_X1 port map( A1 => B_in(0), A2 => B_in(1), A3 => n8, B1 => n11,
B2 => n10, B3 => B_in(2), ZN => A_out(0));
U6 : INV_X1 port map( A => B_in(1), ZN => n10);
U3 : INV_X1 port map( A => B_in(0), ZN => n11);
U4 : INV_X1 port map( A => B_in(2), ZN => n8);
U5 : AOI21_X1 port map( B1 => B_in(0), B2 => B_in(1), A => n8, ZN =>
A_out(1));
U7 : OAI221_X1 port map( B1 => B_in(1), B2 => n11, C1 => n10, C2 => B_in(2),
A => n9, ZN => A_out(2));
U8 : NAND2_X1 port map( A1 => B_in(2), A2 => n11, ZN => n9);
end SYN_bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity booth_encoder_6 is
port( B_in : in std_logic_vector (2 downto 0); A_out : out std_logic_vector
(2 downto 0));
end booth_encoder_6;
architecture SYN_bhe of booth_encoder_6 is
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component OAI221_X1
port( B1, B2, C1, C2, A : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component OAI33_X1
port( A1, A2, A3, B1, B2, B3 : in std_logic; ZN : out std_logic);
end component;
signal n8, n9, n10, n11 : std_logic;
begin
U9 : OAI33_X1 port map( A1 => B_in(0), A2 => B_in(1), A3 => n8, B1 => n11,
B2 => n10, B3 => B_in(2), ZN => A_out(0));
U3 : INV_X1 port map( A => B_in(2), ZN => n8);
U4 : INV_X1 port map( A => B_in(1), ZN => n10);
U5 : INV_X1 port map( A => B_in(0), ZN => n11);
U6 : OAI221_X1 port map( B1 => B_in(1), B2 => n11, C1 => n10, C2 => B_in(2),
A => n9, ZN => A_out(2));
U7 : NAND2_X1 port map( A1 => B_in(2), A2 => n11, ZN => n9);
U8 : AOI21_X1 port map( B1 => B_in(0), B2 => B_in(1), A => n8, ZN =>
A_out(1));
end SYN_bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity booth_encoder_5 is
port( B_in : in std_logic_vector (2 downto 0); A_out : out std_logic_vector
(2 downto 0));
end booth_encoder_5;
architecture SYN_bhe of booth_encoder_5 is
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component OAI221_X1
port( B1, B2, C1, C2, A : in std_logic; ZN : out std_logic);
end component;
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component OAI33_X1
port( A1, A2, A3, B1, B2, B3 : in std_logic; ZN : out std_logic);
end component;
signal n8, n9, n10, n11 : std_logic;
begin
U9 : OAI33_X1 port map( A1 => B_in(0), A2 => B_in(1), A3 => n8, B1 => n11,
B2 => n10, B3 => B_in(2), ZN => A_out(0));
U3 : INV_X1 port map( A => B_in(2), ZN => n8);
U4 : INV_X1 port map( A => B_in(1), ZN => n10);
U5 : INV_X1 port map( A => B_in(0), ZN => n11);
U6 : AOI21_X1 port map( B1 => B_in(0), B2 => B_in(1), A => n8, ZN =>
A_out(1));
U7 : OAI221_X1 port map( B1 => B_in(1), B2 => n11, C1 => n10, C2 => B_in(2),
A => n9, ZN => A_out(2));
U8 : NAND2_X1 port map( A1 => B_in(2), A2 => n11, ZN => n9);
end SYN_bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity booth_encoder_4 is
port( B_in : in std_logic_vector (2 downto 0); A_out : out std_logic_vector
(2 downto 0));
end booth_encoder_4;
architecture SYN_bhe of booth_encoder_4 is
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component OAI221_X1
port( B1, B2, C1, C2, A : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component OAI33_X1
port( A1, A2, A3, B1, B2, B3 : in std_logic; ZN : out std_logic);
end component;
signal n8, n9, n10, n11 : std_logic;
begin
U9 : OAI33_X1 port map( A1 => B_in(0), A2 => B_in(1), A3 => n8, B1 => n11,
B2 => n10, B3 => B_in(2), ZN => A_out(0));
U3 : INV_X1 port map( A => B_in(2), ZN => n8);
U4 : INV_X1 port map( A => B_in(1), ZN => n10);
U5 : INV_X1 port map( A => B_in(0), ZN => n11);
U6 : OAI221_X1 port map( B1 => B_in(1), B2 => n11, C1 => n10, C2 => B_in(2),
A => n9, ZN => A_out(2));
U7 : NAND2_X1 port map( A1 => B_in(2), A2 => n11, ZN => n9);
U8 : AOI21_X1 port map( B1 => B_in(0), B2 => B_in(1), A => n8, ZN =>
A_out(1));
end SYN_bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity booth_encoder_3 is
port( B_in : in std_logic_vector (2 downto 0); A_out : out std_logic_vector
(2 downto 0));
end booth_encoder_3;
architecture SYN_bhe of booth_encoder_3 is
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component OAI221_X1
port( B1, B2, C1, C2, A : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component OAI33_X1
port( A1, A2, A3, B1, B2, B3 : in std_logic; ZN : out std_logic);
end component;
signal n8, n9, n10, n11 : std_logic;
begin
U9 : OAI33_X1 port map( A1 => B_in(0), A2 => B_in(1), A3 => n8, B1 => n11,
B2 => n10, B3 => B_in(2), ZN => A_out(0));
U3 : INV_X1 port map( A => B_in(1), ZN => n10);
U4 : INV_X1 port map( A => B_in(0), ZN => n11);
U5 : INV_X1 port map( A => B_in(2), ZN => n8);
U6 : OAI221_X1 port map( B1 => B_in(1), B2 => n11, C1 => n10, C2 => B_in(2),
A => n9, ZN => A_out(2));
U7 : NAND2_X1 port map( A1 => B_in(2), A2 => n11, ZN => n9);
U8 : AOI21_X1 port map( B1 => B_in(0), B2 => B_in(1), A => n8, ZN =>
A_out(1));
end SYN_bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity booth_encoder_2 is
port( B_in : in std_logic_vector (2 downto 0); A_out : out std_logic_vector
(2 downto 0));
end booth_encoder_2;
architecture SYN_bhe of booth_encoder_2 is
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component OAI221_X1
port( B1, B2, C1, C2, A : in std_logic; ZN : out std_logic);
end component;
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component OAI33_X1
port( A1, A2, A3, B1, B2, B3 : in std_logic; ZN : out std_logic);
end component;
signal n8, n9, n10, n11 : std_logic;
begin
U9 : OAI33_X1 port map( A1 => B_in(0), A2 => B_in(1), A3 => n8, B1 => n11,
B2 => n10, B3 => B_in(2), ZN => A_out(0));
U3 : INV_X1 port map( A => B_in(1), ZN => n10);
U4 : INV_X1 port map( A => B_in(0), ZN => n11);
U5 : INV_X1 port map( A => B_in(2), ZN => n8);
U6 : AOI21_X1 port map( B1 => B_in(0), B2 => B_in(1), A => n8, ZN =>
A_out(1));
U7 : OAI221_X1 port map( B1 => B_in(1), B2 => n11, C1 => n10, C2 => B_in(2),
A => n9, ZN => A_out(2));
U8 : NAND2_X1 port map( A1 => B_in(2), A2 => n11, ZN => n9);
end SYN_bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity booth_encoder_1 is
port( B_in : in std_logic_vector (2 downto 0); A_out : out std_logic_vector
(2 downto 0));
end booth_encoder_1;
architecture SYN_bhe of booth_encoder_1 is
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component OAI221_X1
port( B1, B2, C1, C2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component OAI33_X1
port( A1, A2, A3, B1, B2, B3 : in std_logic; ZN : out std_logic);
end component;
signal n7, n8, n9 : std_logic;
begin
U9 : OAI33_X1 port map( A1 => B_in(0), A2 => B_in(1), A3 => n8, B1 => n9, B2
=> n8, B3 => B_in(2), ZN => A_out(0));
U4 : NAND2_X1 port map( A1 => B_in(2), A2 => n9, ZN => n7);
U3 : OAI221_X1 port map( B1 => B_in(1), B2 => n9, C1 => n8, C2 => B_in(2), A
=> n7, ZN => A_out(2));
U5 : INV_X1 port map( A => B_in(0), ZN => n9);
U6 : INV_X1 port map( A => B_in(1), ZN => n8);
U7 : AOI21_X1 port map( B1 => B_in(0), B2 => B_in(1), A => n8, ZN =>
A_out(1));
end SYN_bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity carry_sel_gen_N4_7 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end carry_sel_gen_N4_7;
architecture SYN_STRUCTURAL of carry_sel_gen_N4_7 is
component mux21_SIZE4_7
port( IN0, IN1 : in std_logic_vector (3 downto 0); CTRL : in std_logic;
OUT1 : out std_logic_vector (3 downto 0));
end component;
component RCA_N4_13
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
component RCA_N4_14
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
signal X_Logic1_port, X_Logic0_port, nocarry_sum_to_mux_3_port,
nocarry_sum_to_mux_2_port, nocarry_sum_to_mux_1_port,
nocarry_sum_to_mux_0_port, carry_sum_to_mux_3_port,
carry_sum_to_mux_2_port, carry_sum_to_mux_1_port, carry_sum_to_mux_0_port
, net561343, net561344 : std_logic;
begin
X_Logic1_port <= '1';
X_Logic0_port <= '0';
rca_nocarry : RCA_N4_14 port map( A(3) => A(3), A(2) => A(2), A(1) => A(1),
A(0) => A(0), B(3) => B(3), B(2) => B(2), B(1) =>
B(1), B(0) => B(0), Ci => X_Logic0_port, S(3) =>
nocarry_sum_to_mux_3_port, S(2) =>
nocarry_sum_to_mux_2_port, S(1) =>
nocarry_sum_to_mux_1_port, S(0) =>
nocarry_sum_to_mux_0_port, Co => net561344);
rca_carry : RCA_N4_13 port map( A(3) => A(3), A(2) => A(2), A(1) => A(1),
A(0) => A(0), B(3) => B(3), B(2) => B(2), B(1) =>
B(1), B(0) => B(0), Ci => X_Logic1_port, S(3) =>
carry_sum_to_mux_3_port, S(2) =>
carry_sum_to_mux_2_port, S(1) =>
carry_sum_to_mux_1_port, S(0) =>
carry_sum_to_mux_0_port, Co => net561343);
outmux : mux21_SIZE4_7 port map( IN0(3) => nocarry_sum_to_mux_3_port, IN0(2)
=> nocarry_sum_to_mux_2_port, IN0(1) =>
nocarry_sum_to_mux_1_port, IN0(0) =>
nocarry_sum_to_mux_0_port, IN1(3) =>
carry_sum_to_mux_3_port, IN1(2) =>
carry_sum_to_mux_2_port, IN1(1) =>
carry_sum_to_mux_1_port, IN1(0) =>
carry_sum_to_mux_0_port, CTRL => Ci, OUT1(3) => S(3)
, OUT1(2) => S(2), OUT1(1) => S(1), OUT1(0) => S(0))
;
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity carry_sel_gen_N4_6 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end carry_sel_gen_N4_6;
architecture SYN_STRUCTURAL of carry_sel_gen_N4_6 is
component mux21_SIZE4_6
port( IN0, IN1 : in std_logic_vector (3 downto 0); CTRL : in std_logic;
OUT1 : out std_logic_vector (3 downto 0));
end component;
component RCA_N4_11
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
component RCA_N4_12
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
signal X_Logic1_port, X_Logic0_port, nocarry_sum_to_mux_3_port,
nocarry_sum_to_mux_2_port, nocarry_sum_to_mux_1_port,
nocarry_sum_to_mux_0_port, carry_sum_to_mux_3_port,
carry_sum_to_mux_2_port, carry_sum_to_mux_1_port, carry_sum_to_mux_0_port
, net561341, net561342 : std_logic;
begin
X_Logic1_port <= '1';
X_Logic0_port <= '0';
rca_nocarry : RCA_N4_12 port map( A(3) => A(3), A(2) => A(2), A(1) => A(1),
A(0) => A(0), B(3) => B(3), B(2) => B(2), B(1) =>
B(1), B(0) => B(0), Ci => X_Logic0_port, S(3) =>
nocarry_sum_to_mux_3_port, S(2) =>
nocarry_sum_to_mux_2_port, S(1) =>
nocarry_sum_to_mux_1_port, S(0) =>
nocarry_sum_to_mux_0_port, Co => net561342);
rca_carry : RCA_N4_11 port map( A(3) => A(3), A(2) => A(2), A(1) => A(1),
A(0) => A(0), B(3) => B(3), B(2) => B(2), B(1) =>
B(1), B(0) => B(0), Ci => X_Logic1_port, S(3) =>
carry_sum_to_mux_3_port, S(2) =>
carry_sum_to_mux_2_port, S(1) =>
carry_sum_to_mux_1_port, S(0) =>
carry_sum_to_mux_0_port, Co => net561341);
outmux : mux21_SIZE4_6 port map( IN0(3) => nocarry_sum_to_mux_3_port, IN0(2)
=> nocarry_sum_to_mux_2_port, IN0(1) =>
nocarry_sum_to_mux_1_port, IN0(0) =>
nocarry_sum_to_mux_0_port, IN1(3) =>
carry_sum_to_mux_3_port, IN1(2) =>
carry_sum_to_mux_2_port, IN1(1) =>
carry_sum_to_mux_1_port, IN1(0) =>
carry_sum_to_mux_0_port, CTRL => Ci, OUT1(3) => S(3)
, OUT1(2) => S(2), OUT1(1) => S(1), OUT1(0) => S(0))
;
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity carry_sel_gen_N4_5 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end carry_sel_gen_N4_5;
architecture SYN_STRUCTURAL of carry_sel_gen_N4_5 is
component mux21_SIZE4_5
port( IN0, IN1 : in std_logic_vector (3 downto 0); CTRL : in std_logic;
OUT1 : out std_logic_vector (3 downto 0));
end component;
component RCA_N4_9
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
component RCA_N4_10
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
signal X_Logic1_port, X_Logic0_port, nocarry_sum_to_mux_3_port,
nocarry_sum_to_mux_2_port, nocarry_sum_to_mux_1_port,
nocarry_sum_to_mux_0_port, carry_sum_to_mux_3_port,
carry_sum_to_mux_2_port, carry_sum_to_mux_1_port, carry_sum_to_mux_0_port
, net561339, net561340 : std_logic;
begin
X_Logic1_port <= '1';
X_Logic0_port <= '0';
rca_nocarry : RCA_N4_10 port map( A(3) => A(3), A(2) => A(2), A(1) => A(1),
A(0) => A(0), B(3) => B(3), B(2) => B(2), B(1) =>
B(1), B(0) => B(0), Ci => X_Logic0_port, S(3) =>
nocarry_sum_to_mux_3_port, S(2) =>
nocarry_sum_to_mux_2_port, S(1) =>
nocarry_sum_to_mux_1_port, S(0) =>
nocarry_sum_to_mux_0_port, Co => net561340);
rca_carry : RCA_N4_9 port map( A(3) => A(3), A(2) => A(2), A(1) => A(1),
A(0) => A(0), B(3) => B(3), B(2) => B(2), B(1) =>
B(1), B(0) => B(0), Ci => X_Logic1_port, S(3) =>
carry_sum_to_mux_3_port, S(2) =>
carry_sum_to_mux_2_port, S(1) =>
carry_sum_to_mux_1_port, S(0) =>
carry_sum_to_mux_0_port, Co => net561339);
outmux : mux21_SIZE4_5 port map( IN0(3) => nocarry_sum_to_mux_3_port, IN0(2)
=> nocarry_sum_to_mux_2_port, IN0(1) =>
nocarry_sum_to_mux_1_port, IN0(0) =>
nocarry_sum_to_mux_0_port, IN1(3) =>
carry_sum_to_mux_3_port, IN1(2) =>
carry_sum_to_mux_2_port, IN1(1) =>
carry_sum_to_mux_1_port, IN1(0) =>
carry_sum_to_mux_0_port, CTRL => Ci, OUT1(3) => S(3)
, OUT1(2) => S(2), OUT1(1) => S(1), OUT1(0) => S(0))
;
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity carry_sel_gen_N4_4 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end carry_sel_gen_N4_4;
architecture SYN_STRUCTURAL of carry_sel_gen_N4_4 is
component mux21_SIZE4_4
port( IN0, IN1 : in std_logic_vector (3 downto 0); CTRL : in std_logic;
OUT1 : out std_logic_vector (3 downto 0));
end component;
component RCA_N4_7
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
component RCA_N4_8
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
signal X_Logic1_port, X_Logic0_port, nocarry_sum_to_mux_3_port,
nocarry_sum_to_mux_2_port, nocarry_sum_to_mux_1_port,
nocarry_sum_to_mux_0_port, carry_sum_to_mux_3_port,
carry_sum_to_mux_2_port, carry_sum_to_mux_1_port, carry_sum_to_mux_0_port
, net561337, net561338 : std_logic;
begin
X_Logic1_port <= '1';
X_Logic0_port <= '0';
rca_nocarry : RCA_N4_8 port map( A(3) => A(3), A(2) => A(2), A(1) => A(1),
A(0) => A(0), B(3) => B(3), B(2) => B(2), B(1) =>
B(1), B(0) => B(0), Ci => X_Logic0_port, S(3) =>
nocarry_sum_to_mux_3_port, S(2) =>
nocarry_sum_to_mux_2_port, S(1) =>
nocarry_sum_to_mux_1_port, S(0) =>
nocarry_sum_to_mux_0_port, Co => net561338);
rca_carry : RCA_N4_7 port map( A(3) => A(3), A(2) => A(2), A(1) => A(1),
A(0) => A(0), B(3) => B(3), B(2) => B(2), B(1) =>
B(1), B(0) => B(0), Ci => X_Logic1_port, S(3) =>
carry_sum_to_mux_3_port, S(2) =>
carry_sum_to_mux_2_port, S(1) =>
carry_sum_to_mux_1_port, S(0) =>
carry_sum_to_mux_0_port, Co => net561337);
outmux : mux21_SIZE4_4 port map( IN0(3) => nocarry_sum_to_mux_3_port, IN0(2)
=> nocarry_sum_to_mux_2_port, IN0(1) =>
nocarry_sum_to_mux_1_port, IN0(0) =>
nocarry_sum_to_mux_0_port, IN1(3) =>
carry_sum_to_mux_3_port, IN1(2) =>
carry_sum_to_mux_2_port, IN1(1) =>
carry_sum_to_mux_1_port, IN1(0) =>
carry_sum_to_mux_0_port, CTRL => Ci, OUT1(3) => S(3)
, OUT1(2) => S(2), OUT1(1) => S(1), OUT1(0) => S(0))
;
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity carry_sel_gen_N4_3 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end carry_sel_gen_N4_3;
architecture SYN_STRUCTURAL of carry_sel_gen_N4_3 is
component mux21_SIZE4_3
port( IN0, IN1 : in std_logic_vector (3 downto 0); CTRL : in std_logic;
OUT1 : out std_logic_vector (3 downto 0));
end component;
component RCA_N4_5
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
component RCA_N4_6
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
signal X_Logic1_port, X_Logic0_port, nocarry_sum_to_mux_3_port,
nocarry_sum_to_mux_2_port, nocarry_sum_to_mux_1_port,
nocarry_sum_to_mux_0_port, carry_sum_to_mux_3_port,
carry_sum_to_mux_2_port, carry_sum_to_mux_1_port, carry_sum_to_mux_0_port
, net561335, net561336 : std_logic;
begin
X_Logic1_port <= '1';
X_Logic0_port <= '0';
rca_nocarry : RCA_N4_6 port map( A(3) => A(3), A(2) => A(2), A(1) => A(1),
A(0) => A(0), B(3) => B(3), B(2) => B(2), B(1) =>
B(1), B(0) => B(0), Ci => X_Logic0_port, S(3) =>
nocarry_sum_to_mux_3_port, S(2) =>
nocarry_sum_to_mux_2_port, S(1) =>
nocarry_sum_to_mux_1_port, S(0) =>
nocarry_sum_to_mux_0_port, Co => net561336);
rca_carry : RCA_N4_5 port map( A(3) => A(3), A(2) => A(2), A(1) => A(1),
A(0) => A(0), B(3) => B(3), B(2) => B(2), B(1) =>
B(1), B(0) => B(0), Ci => X_Logic1_port, S(3) =>
carry_sum_to_mux_3_port, S(2) =>
carry_sum_to_mux_2_port, S(1) =>
carry_sum_to_mux_1_port, S(0) =>
carry_sum_to_mux_0_port, Co => net561335);
outmux : mux21_SIZE4_3 port map( IN0(3) => nocarry_sum_to_mux_3_port, IN0(2)
=> nocarry_sum_to_mux_2_port, IN0(1) =>
nocarry_sum_to_mux_1_port, IN0(0) =>
nocarry_sum_to_mux_0_port, IN1(3) =>
carry_sum_to_mux_3_port, IN1(2) =>
carry_sum_to_mux_2_port, IN1(1) =>
carry_sum_to_mux_1_port, IN1(0) =>
carry_sum_to_mux_0_port, CTRL => Ci, OUT1(3) => S(3)
, OUT1(2) => S(2), OUT1(1) => S(1), OUT1(0) => S(0))
;
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity carry_sel_gen_N4_2 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end carry_sel_gen_N4_2;
architecture SYN_STRUCTURAL of carry_sel_gen_N4_2 is
component mux21_SIZE4_2
port( IN0, IN1 : in std_logic_vector (3 downto 0); CTRL : in std_logic;
OUT1 : out std_logic_vector (3 downto 0));
end component;
component RCA_N4_3
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
component RCA_N4_4
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
signal X_Logic1_port, X_Logic0_port, nocarry_sum_to_mux_3_port,
nocarry_sum_to_mux_2_port, nocarry_sum_to_mux_1_port,
nocarry_sum_to_mux_0_port, carry_sum_to_mux_3_port,
carry_sum_to_mux_2_port, carry_sum_to_mux_1_port, carry_sum_to_mux_0_port
, net561333, net561334 : std_logic;
begin
X_Logic1_port <= '1';
X_Logic0_port <= '0';
rca_nocarry : RCA_N4_4 port map( A(3) => A(3), A(2) => A(2), A(1) => A(1),
A(0) => A(0), B(3) => B(3), B(2) => B(2), B(1) =>
B(1), B(0) => B(0), Ci => X_Logic0_port, S(3) =>
nocarry_sum_to_mux_3_port, S(2) =>
nocarry_sum_to_mux_2_port, S(1) =>
nocarry_sum_to_mux_1_port, S(0) =>
nocarry_sum_to_mux_0_port, Co => net561334);
rca_carry : RCA_N4_3 port map( A(3) => A(3), A(2) => A(2), A(1) => A(1),
A(0) => A(0), B(3) => B(3), B(2) => B(2), B(1) =>
B(1), B(0) => B(0), Ci => X_Logic1_port, S(3) =>
carry_sum_to_mux_3_port, S(2) =>
carry_sum_to_mux_2_port, S(1) =>
carry_sum_to_mux_1_port, S(0) =>
carry_sum_to_mux_0_port, Co => net561333);
outmux : mux21_SIZE4_2 port map( IN0(3) => nocarry_sum_to_mux_3_port, IN0(2)
=> nocarry_sum_to_mux_2_port, IN0(1) =>
nocarry_sum_to_mux_1_port, IN0(0) =>
nocarry_sum_to_mux_0_port, IN1(3) =>
carry_sum_to_mux_3_port, IN1(2) =>
carry_sum_to_mux_2_port, IN1(1) =>
carry_sum_to_mux_1_port, IN1(0) =>
carry_sum_to_mux_0_port, CTRL => Ci, OUT1(3) => S(3)
, OUT1(2) => S(2), OUT1(1) => S(1), OUT1(0) => S(0))
;
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity carry_sel_gen_N4_1 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end carry_sel_gen_N4_1;
architecture SYN_STRUCTURAL of carry_sel_gen_N4_1 is
component mux21_SIZE4_1
port( IN0, IN1 : in std_logic_vector (3 downto 0); CTRL : in std_logic;
OUT1 : out std_logic_vector (3 downto 0));
end component;
component RCA_N4_1
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
component RCA_N4_2
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
signal X_Logic1_port, X_Logic0_port, nocarry_sum_to_mux_3_port,
nocarry_sum_to_mux_2_port, nocarry_sum_to_mux_1_port,
nocarry_sum_to_mux_0_port, carry_sum_to_mux_3_port,
carry_sum_to_mux_2_port, carry_sum_to_mux_1_port, carry_sum_to_mux_0_port
, net561331, net561332 : std_logic;
begin
X_Logic1_port <= '1';
X_Logic0_port <= '0';
rca_nocarry : RCA_N4_2 port map( A(3) => A(3), A(2) => A(2), A(1) => A(1),
A(0) => A(0), B(3) => B(3), B(2) => B(2), B(1) =>
B(1), B(0) => B(0), Ci => X_Logic0_port, S(3) =>
nocarry_sum_to_mux_3_port, S(2) =>
nocarry_sum_to_mux_2_port, S(1) =>
nocarry_sum_to_mux_1_port, S(0) =>
nocarry_sum_to_mux_0_port, Co => net561332);
rca_carry : RCA_N4_1 port map( A(3) => A(3), A(2) => A(2), A(1) => A(1),
A(0) => A(0), B(3) => B(3), B(2) => B(2), B(1) =>
B(1), B(0) => B(0), Ci => X_Logic1_port, S(3) =>
carry_sum_to_mux_3_port, S(2) =>
carry_sum_to_mux_2_port, S(1) =>
carry_sum_to_mux_1_port, S(0) =>
carry_sum_to_mux_0_port, Co => net561331);
outmux : mux21_SIZE4_1 port map( IN0(3) => nocarry_sum_to_mux_3_port, IN0(2)
=> nocarry_sum_to_mux_2_port, IN0(1) =>
nocarry_sum_to_mux_1_port, IN0(0) =>
nocarry_sum_to_mux_0_port, IN1(3) =>
carry_sum_to_mux_3_port, IN1(2) =>
carry_sum_to_mux_2_port, IN1(1) =>
carry_sum_to_mux_1_port, IN1(0) =>
carry_sum_to_mux_0_port, CTRL => Ci, OUT1(3) => S(3)
, OUT1(2) => S(2), OUT1(1) => S(1), OUT1(0) => S(0))
;
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_26 is
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic);
end pg_26;
architecture SYN_beh of pg_26 is
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U1 : INV_X1 port map( A => n3, ZN => g_out);
U2 : AND2_X1 port map( A1 => p, A2 => p_prec, ZN => p_out);
U3 : AOI21_X1 port map( B1 => p, B2 => g_prec, A => g, ZN => n3);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_25 is
port( g, p, g_prec, p_prec : in std_logic; p_out, g_out_BAR : out std_logic
);
end pg_25;
architecture SYN_beh of pg_25 is
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
begin
U1 : AND2_X1 port map( A1 => p_prec, A2 => p, ZN => p_out);
U2 : AOI21_X1 port map( B1 => g_prec, B2 => p, A => g, ZN => g_out_BAR);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_24 is
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic);
end pg_24;
architecture SYN_beh of pg_24 is
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
signal n2, n3 : std_logic;
begin
U1 : INV_X1 port map( A => g, ZN => n3);
U2 : AND2_X1 port map( A1 => p_prec, A2 => p, ZN => p_out);
U3 : NAND2_X1 port map( A1 => g_prec, A2 => p, ZN => n2);
U4 : NAND2_X1 port map( A1 => n2, A2 => n3, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_23 is
port( g, p, g_prec, p_prec : in std_logic; p_out, g_out_BAR : out std_logic
);
end pg_23;
architecture SYN_beh of pg_23 is
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
begin
U1 : AND2_X1 port map( A1 => p, A2 => p_prec, ZN => p_out);
U2 : AOI21_X1 port map( B1 => p, B2 => g_prec, A => g, ZN => g_out_BAR);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_22 is
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic);
end pg_22;
architecture SYN_beh of pg_22 is
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
signal n2, n3 : std_logic;
begin
U1 : AND2_X1 port map( A1 => p_prec, A2 => p, ZN => p_out);
U2 : INV_X1 port map( A => g, ZN => n3);
U3 : NAND2_X1 port map( A1 => g_prec, A2 => p, ZN => n2);
U4 : NAND2_X1 port map( A1 => n2, A2 => n3, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_21 is
port( g, p, g_prec, p_prec : in std_logic; p_out, g_out_BAR : out std_logic
);
end pg_21;
architecture SYN_beh of pg_21 is
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
begin
U1 : AND2_X1 port map( A1 => p, A2 => p_prec, ZN => p_out);
U2 : AOI21_X1 port map( B1 => p, B2 => g_prec, A => g, ZN => g_out_BAR);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_20 is
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic);
end pg_20;
architecture SYN_beh of pg_20 is
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component CLKBUF_X1
port( A : in std_logic; Z : out std_logic);
end component;
signal n3, n4 : std_logic;
begin
U1 : CLKBUF_X1 port map( A => p, Z => n3);
U2 : INV_X1 port map( A => n4, ZN => g_out);
U3 : AND2_X1 port map( A1 => n3, A2 => p_prec, ZN => p_out);
U4 : AOI21_X1 port map( B1 => p, B2 => g_prec, A => g, ZN => n4);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_19 is
port( g, p, g_prec, p_prec : in std_logic; p_out, g_out_BAR : out std_logic
);
end pg_19;
architecture SYN_beh of pg_19 is
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
begin
U1 : AND2_X1 port map( A1 => p, A2 => p_prec, ZN => p_out);
U2 : AOI21_X1 port map( B1 => p, B2 => g_prec, A => g, ZN => g_out_BAR);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_18 is
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic);
end pg_18;
architecture SYN_beh of pg_18 is
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U1 : AND2_X1 port map( A1 => p_prec, A2 => p, ZN => p_out);
U2 : INV_X1 port map( A => n3, ZN => g_out);
U3 : AOI21_X1 port map( B1 => p, B2 => g_prec, A => g, ZN => n3);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_17 is
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic);
end pg_17;
architecture SYN_beh of pg_17 is
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U1 : INV_X1 port map( A => n3, ZN => g_out);
U2 : AND2_X1 port map( A1 => p_prec, A2 => p, ZN => p_out);
U3 : AOI21_X1 port map( B1 => g_prec, B2 => p, A => g, ZN => n3);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_16 is
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic);
end pg_16;
architecture SYN_beh of pg_16 is
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U3 : AOI21_X1 port map( B1 => g_prec, B2 => p, A => g, ZN => n3);
U1 : AND2_X1 port map( A1 => p, A2 => p_prec, ZN => p_out);
U2 : INV_X1 port map( A => n3, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_15 is
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic);
end pg_15;
architecture SYN_beh of pg_15 is
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U1 : INV_X1 port map( A => n3, ZN => g_out);
U2 : AND2_X1 port map( A1 => p, A2 => p_prec, ZN => p_out);
U3 : AOI21_X1 port map( B1 => g_prec, B2 => p, A => g, ZN => n3);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_14 is
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic);
end pg_14;
architecture SYN_beh of pg_14 is
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U3 : AOI21_X1 port map( B1 => g_prec, B2 => p, A => g, ZN => n3);
U1 : AND2_X1 port map( A1 => p, A2 => p_prec, ZN => p_out);
U2 : INV_X1 port map( A => n3, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_13 is
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic);
end pg_13;
architecture SYN_beh of pg_13 is
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U3 : AOI21_X1 port map( B1 => g_prec, B2 => p, A => g, ZN => n3);
U1 : AND2_X1 port map( A1 => p, A2 => p_prec, ZN => p_out);
U2 : INV_X1 port map( A => n3, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_12 is
port( p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic;
g_BAR : in std_logic);
end pg_12;
architecture SYN_beh of pg_12 is
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U1 : AND2_X1 port map( A1 => p, A2 => p_prec, ZN => p_out);
U2 : NAND2_X1 port map( A1 => n3, A2 => g_BAR, ZN => g_out);
U3 : NAND2_X1 port map( A1 => p, A2 => g_prec, ZN => n3);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_11 is
port( p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic;
g_BAR : in std_logic);
end pg_11;
architecture SYN_beh of pg_11 is
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
signal n2 : std_logic;
begin
U1 : AND2_X1 port map( A1 => p, A2 => p_prec, ZN => p_out);
U2 : NAND2_X1 port map( A1 => g_prec, A2 => p, ZN => n2);
U3 : NAND2_X1 port map( A1 => n2, A2 => g_BAR, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_10 is
port( p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic;
g_BAR : in std_logic);
end pg_10;
architecture SYN_beh of pg_10 is
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
signal n2 : std_logic;
begin
U1 : AND2_X1 port map( A1 => p_prec, A2 => p, ZN => p_out);
U2 : NAND2_X1 port map( A1 => g_prec, A2 => p, ZN => n2);
U3 : NAND2_X1 port map( A1 => n2, A2 => g_BAR, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_9 is
port( p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic;
g_BAR : in std_logic);
end pg_9;
architecture SYN_beh of pg_9 is
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
signal n2 : std_logic;
begin
U1 : AND2_X1 port map( A1 => p, A2 => p_prec, ZN => p_out);
U2 : NAND2_X1 port map( A1 => n2, A2 => g_BAR, ZN => g_out);
U3 : NAND2_X1 port map( A1 => g_prec, A2 => p, ZN => n2);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_8 is
port( g, p, g_prec, p_prec : in std_logic; p_out, g_out_BAR : out std_logic
);
end pg_8;
architecture SYN_beh of pg_8 is
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
begin
U1 : AND2_X1 port map( A1 => p_prec, A2 => p, ZN => p_out);
U2 : AOI21_X1 port map( B1 => g_prec, B2 => p, A => g, ZN => g_out_BAR);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_7 is
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic);
end pg_7;
architecture SYN_beh of pg_7 is
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U1 : AND2_X1 port map( A1 => p, A2 => p_prec, ZN => p_out);
U2 : INV_X1 port map( A => n3, ZN => g_out);
U3 : AOI21_X1 port map( B1 => g_prec, B2 => p, A => g, ZN => n3);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_6 is
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic);
end pg_6;
architecture SYN_beh of pg_6 is
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U3 : AOI21_X1 port map( B1 => g_prec, B2 => p, A => g, ZN => n3);
U1 : AND2_X1 port map( A1 => p, A2 => p_prec, ZN => p_out);
U2 : INV_X1 port map( A => n3, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_5 is
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic);
end pg_5;
architecture SYN_beh of pg_5 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
signal n2, n3 : std_logic;
begin
U1 : INV_X1 port map( A => g, ZN => n2);
U2 : NAND2_X1 port map( A1 => n3, A2 => n2, ZN => g_out);
U3 : NAND2_X1 port map( A1 => g_prec, A2 => p, ZN => n3);
U4 : AND2_X1 port map( A1 => p, A2 => p_prec, ZN => p_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_4 is
port( p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic;
g_BAR : in std_logic);
end pg_4;
architecture SYN_beh of pg_4 is
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
signal n2 : std_logic;
begin
U1 : AND2_X1 port map( A1 => p, A2 => p_prec, ZN => p_out);
U2 : NAND2_X1 port map( A1 => g_prec, A2 => p, ZN => n2);
U3 : NAND2_X1 port map( A1 => n2, A2 => g_BAR, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_3 is
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic);
end pg_3;
architecture SYN_beh of pg_3 is
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U1 : AND2_X1 port map( A1 => p, A2 => p_prec, ZN => p_out);
U2 : INV_X1 port map( A => n3, ZN => g_out);
U3 : AOI21_X1 port map( B1 => g_prec, B2 => p, A => g, ZN => n3);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_2 is
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic);
end pg_2;
architecture SYN_beh of pg_2 is
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
signal n2, n3 : std_logic;
begin
U1 : AND2_X1 port map( A1 => p, A2 => p_prec, ZN => p_out);
U2 : INV_X1 port map( A => g, ZN => n3);
U3 : NAND2_X1 port map( A1 => g_prec, A2 => p, ZN => n2);
U4 : NAND2_X1 port map( A1 => n2, A2 => n3, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_1 is
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic);
end pg_1;
architecture SYN_beh of pg_1 is
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U3 : AOI21_X1 port map( B1 => g_prec, B2 => p, A => g, ZN => n3);
U1 : AND2_X1 port map( A1 => p, A2 => p_prec, ZN => p_out);
U2 : INV_X1 port map( A => n3, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity g_9 is
port( g, p, g_prec : in std_logic; g_out : out std_logic);
end g_9;
architecture SYN_beh of g_9 is
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
signal n2 : std_logic;
begin
U1 : AOI21_X1 port map( B1 => g_prec, B2 => p, A => g, ZN => n2);
U2 : INV_X1 port map( A => n2, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity g_8 is
port( g, p, g_prec : in std_logic; g_out : out std_logic);
end g_8;
architecture SYN_beh of g_8 is
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
signal n2, n3 : std_logic;
begin
U1 : NAND2_X1 port map( A1 => n3, A2 => n2, ZN => g_out);
U2 : INV_X1 port map( A => g, ZN => n2);
U3 : NAND2_X1 port map( A1 => g_prec, A2 => p, ZN => n3);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity g_7 is
port( g, p, g_prec : in std_logic; g_out : out std_logic);
end g_7;
architecture SYN_beh of g_7 is
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
signal n2, n3 : std_logic;
begin
U1 : NAND2_X1 port map( A1 => n3, A2 => n2, ZN => g_out);
U2 : INV_X1 port map( A => g, ZN => n2);
U3 : NAND2_X1 port map( A1 => g_prec, A2 => p, ZN => n3);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity g_6 is
port( g, p, g_prec : in std_logic; g_out : out std_logic);
end g_6;
architecture SYN_beh of g_6 is
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U1 : INV_X1 port map( A => n3, ZN => g_out);
U2 : AOI21_X1 port map( B1 => p, B2 => g_prec, A => g, ZN => n3);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity g_5 is
port( g, p, g_prec : in std_logic; g_out : out std_logic);
end g_5;
architecture SYN_beh of g_5 is
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
signal n2, n3 : std_logic;
begin
U1 : NAND2_X1 port map( A1 => n2, A2 => n3, ZN => g_out);
U2 : INV_X1 port map( A => g, ZN => n3);
U3 : NAND2_X1 port map( A1 => g_prec, A2 => p, ZN => n2);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity g_4 is
port( g, p, g_prec : in std_logic; g_out : out std_logic);
end g_4;
architecture SYN_beh of g_4 is
component NAND2_X2
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
signal n2, n3 : std_logic;
begin
U1 : INV_X1 port map( A => g, ZN => n3);
U2 : NAND2_X1 port map( A1 => g_prec, A2 => p, ZN => n2);
U3 : NAND2_X2 port map( A1 => n2, A2 => n3, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity g_3 is
port( g, p, g_prec : in std_logic; g_out : out std_logic);
end g_3;
architecture SYN_beh of g_3 is
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
signal n2, n3 : std_logic;
begin
U1 : INV_X1 port map( A => g, ZN => n2);
U2 : NAND2_X1 port map( A1 => n3, A2 => n2, ZN => g_out);
U3 : NAND2_X1 port map( A1 => g_prec, A2 => p, ZN => n3);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity g_2 is
port( g, p, g_prec : in std_logic; g_out : out std_logic);
end g_2;
architecture SYN_beh of g_2 is
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
signal n2, n3 : std_logic;
begin
U1 : NAND2_X1 port map( A1 => p, A2 => g_prec, ZN => n3);
U2 : INV_X1 port map( A => g, ZN => n2);
U3 : NAND2_X1 port map( A1 => n2, A2 => n3, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity g_1 is
port( g, p, g_prec : in std_logic; g_out : out std_logic);
end g_1;
architecture SYN_beh of g_1 is
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U1 : INV_X1 port map( A => n3, ZN => g_out);
U2 : AOI21_X1 port map( B1 => p, B2 => g_prec, A => g, ZN => n3);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_31 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_31;
architecture SYN_beh of pg_net_31 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U1 : XOR2_X1 port map( A => a, B => b, Z => p_out);
U2 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_30 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_30;
architecture SYN_beh of pg_net_30 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
signal n1 : std_logic;
begin
U1 : INV_X1 port map( A => a, ZN => n1);
U2 : XNOR2_X1 port map( A => b, B => n1, ZN => p_out);
U3 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_29 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_29;
architecture SYN_beh of pg_net_29 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U2 : XOR2_X1 port map( A => b, B => a, Z => p_out);
U1 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_28 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_28;
architecture SYN_beh of pg_net_28 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U2 : XOR2_X1 port map( A => b, B => a, Z => p_out);
U1 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_27 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_27;
architecture SYN_beh of pg_net_27 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
signal n1 : std_logic;
begin
U1 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
U2 : INV_X1 port map( A => a, ZN => n1);
U3 : XNOR2_X1 port map( A => b, B => n1, ZN => p_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_26 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_26;
architecture SYN_beh of pg_net_26 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U2 : XOR2_X1 port map( A => b, B => a, Z => p_out);
U1 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_25 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_25;
architecture SYN_beh of pg_net_25 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U1 : XOR2_X1 port map( A => a, B => b, Z => p_out);
U2 : AND2_X1 port map( A1 => a, A2 => b, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_24 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_24;
architecture SYN_beh of pg_net_24 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U2 : XOR2_X1 port map( A => b, B => a, Z => p_out);
U1 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_23 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_23;
architecture SYN_beh of pg_net_23 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U2 : XOR2_X1 port map( A => b, B => a, Z => p_out);
U1 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_22 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_22;
architecture SYN_beh of pg_net_22 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U2 : XOR2_X1 port map( A => b, B => a, Z => p_out);
U1 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_21 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_21;
architecture SYN_beh of pg_net_21 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
signal n1 : std_logic;
begin
U1 : INV_X1 port map( A => a, ZN => n1);
U2 : XNOR2_X1 port map( A => b, B => n1, ZN => p_out);
U3 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_20 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_20;
architecture SYN_beh of pg_net_20 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
signal n1 : std_logic;
begin
U1 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
U2 : INV_X1 port map( A => a, ZN => n1);
U3 : XNOR2_X1 port map( A => b, B => n1, ZN => p_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_19 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_19;
architecture SYN_beh of pg_net_19 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U2 : XOR2_X1 port map( A => b, B => a, Z => p_out);
U1 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_18 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_18;
architecture SYN_beh of pg_net_18 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U2 : XOR2_X1 port map( A => b, B => a, Z => p_out);
U1 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_17 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_17;
architecture SYN_beh of pg_net_17 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U1 : XOR2_X1 port map( A => b, B => a, Z => p_out);
U2 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_16 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_16;
architecture SYN_beh of pg_net_16 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U1 : XOR2_X1 port map( A => b, B => a, Z => p_out);
U2 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_15 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_15;
architecture SYN_beh of pg_net_15 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U2 : XOR2_X1 port map( A => b, B => a, Z => p_out);
U1 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_14 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_14;
architecture SYN_beh of pg_net_14 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U1 : XOR2_X1 port map( A => b, B => a, Z => p_out);
U2 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_13 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_13;
architecture SYN_beh of pg_net_13 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U2 : XOR2_X1 port map( A => b, B => a, Z => p_out);
U1 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_12 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_12;
architecture SYN_beh of pg_net_12 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U1 : XOR2_X1 port map( A => a, B => b, Z => p_out);
U2 : AND2_X1 port map( A1 => a, A2 => b, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_11 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_11;
architecture SYN_beh of pg_net_11 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U2 : XOR2_X1 port map( A => b, B => a, Z => p_out);
U1 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_10 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_10;
architecture SYN_beh of pg_net_10 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U2 : XOR2_X1 port map( A => b, B => a, Z => p_out);
U1 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_9 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_9;
architecture SYN_beh of pg_net_9 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U2 : XOR2_X1 port map( A => b, B => a, Z => p_out);
U1 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_8 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_8;
architecture SYN_beh of pg_net_8 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U2 : XOR2_X1 port map( A => b, B => a, Z => p_out);
U1 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_7 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_7;
architecture SYN_beh of pg_net_7 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U2 : XOR2_X1 port map( A => b, B => a, Z => p_out);
U1 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_6 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_6;
architecture SYN_beh of pg_net_6 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U1 : XOR2_X1 port map( A => b, B => a, Z => p_out);
U2 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_5 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_5;
architecture SYN_beh of pg_net_5 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U2 : XOR2_X1 port map( A => b, B => a, Z => p_out);
U1 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_4 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_4;
architecture SYN_beh of pg_net_4 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U2 : XOR2_X1 port map( A => b, B => a, Z => p_out);
U1 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_3 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_3;
architecture SYN_beh of pg_net_3 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U2 : XOR2_X1 port map( A => b, B => a, Z => p_out);
U1 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_2 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_2;
architecture SYN_beh of pg_net_2 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U2 : XOR2_X1 port map( A => b, B => a, Z => p_out);
U1 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_1 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_1;
architecture SYN_beh of pg_net_1 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n1 : std_logic;
begin
U1 : XNOR2_X1 port map( A => b, B => n1, ZN => p_out);
U2 : INV_X1 port map( A => a, ZN => n1);
U3 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity mux41_MUX_SIZE32_1 is
port( IN0, IN1, IN2, IN3 : in std_logic_vector (31 downto 0); CTRL : in
std_logic_vector (1 downto 0); OUT1 : out std_logic_vector (31 downto
0));
end mux41_MUX_SIZE32_1;
architecture SYN_bhe of mux41_MUX_SIZE32_1 is
component AOI222_X1
port( A1, A2, B1, B2, C1, C2 : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component NAND3_X1
port( A1, A2, A3 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component BUF_X2
port( A : in std_logic; Z : out std_logic);
end component;
component AND2_X2
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component CLKBUF_X3
port( A : in std_logic; Z : out std_logic);
end component;
component NOR2_X2
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component AOI22_X1
port( A1, A2, B1, B2 : in std_logic; ZN : out std_logic);
end component;
component NOR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component BUF_X1
port( A : in std_logic; Z : out std_logic);
end component;
component CLKBUF_X1
port( A : in std_logic; Z : out std_logic);
end component;
component OR3_X1
port( A1, A2, A3 : in std_logic; ZN : out std_logic);
end component;
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
signal n38, n39, n40, n41, n53, n54, n55, n57, n61, n63, n64, n65, n66, n68,
n69, n70, n71, n81, n82, n83, n84, n85, n86, n87, n88, n89, n90, n91, n92
, n93, n94, n95, n96, n97, n98, n99, n100, n101, n102, n103, n104, n105,
n106, n107, n108, n109, n110, n111, n112, n113, n114, n115, n116, n117,
n119, n120, n121, n122, n123, n124, n125, n126, n127, n128, n129, n130,
n131, n132, n135, n136, n137, n138, n139, n141, n142, n143, n144, n145,
n146, n147, n148, n149 : std_logic;
begin
U21 : INV_X1 port map( A => n143, ZN => OUT1(29));
U15 : INV_X1 port map( A => n145, ZN => OUT1(31));
U1 : BUF_X2 port map( A => n148, Z => n128);
U2 : NAND2_X1 port map( A1 => n83, A2 => IN2(12), ZN => n38);
U3 : AOI21_X1 port map( B1 => n127, B2 => IN0(12), A => n96, ZN => n39);
U4 : NAND2_X1 port map( A1 => n38, A2 => n39, ZN => OUT1(12));
U5 : AOI222_X1 port map( A1 => n130, A2 => IN1(23), B1 => n127, B2 =>
IN0(23), C1 => IN2(23), C2 => n83, ZN => n40);
U6 : INV_X1 port map( A => n40, ZN => OUT1(23));
U7 : AOI222_X1 port map( A1 => n126, A2 => IN0(30), B1 => n125, B2 =>
IN2(30), C1 => IN1(30), C2 => n71, ZN => n41);
U8 : INV_X1 port map( A => n41, ZN => OUT1(30));
U9 : BUF_X1 port map( A => n148, Z => n127);
U10 : NOR2_X2 port map( A1 => n81, A2 => CTRL(0), ZN => n83);
U11 : OR3_X1 port map( A1 => n93, A2 => n94, A3 => n95, ZN => OUT1(16));
U12 : NAND3_X1 port map( A1 => n53, A2 => n54, A3 => n55, ZN => OUT1(15));
U13 : OR3_X1 port map( A1 => n112, A2 => n113, A3 => n114, ZN => OUT1(17));
U14 : OR3_X1 port map( A1 => n97, A2 => n98, A3 => n99, ZN => OUT1(26));
U16 : BUF_X2 port map( A => n61, Z => n125);
U17 : NAND2_X1 port map( A1 => n131, A2 => IN1(15), ZN => n53);
U18 : NAND2_X1 port map( A1 => n83, A2 => IN2(15), ZN => n54);
U19 : NAND2_X1 port map( A1 => n127, A2 => IN0(15), ZN => n55);
U20 : AOI222_X1 port map( A1 => n57, A2 => IN1(29), B1 => n128, B2 =>
IN0(29), C1 => n125, C2 => IN2(29), ZN => n143);
U22 : AOI222_X1 port map( A1 => n57, A2 => IN1(31), B1 => n128, B2 =>
IN0(31), C1 => n125, C2 => IN2(31), ZN => n145);
U23 : CLKBUF_X1 port map( A => n129, Z => n57);
U24 : BUF_X1 port map( A => n149, Z => n131);
U25 : NOR2_X1 port map( A1 => n64, A2 => CTRL(0), ZN => n61);
U26 : BUF_X2 port map( A => n61, Z => n63);
U27 : NAND2_X1 port map( A1 => n63, A2 => IN2(0), ZN => n68);
U28 : NAND2_X1 port map( A1 => n125, A2 => IN2(1), ZN => n70);
U29 : NAND2_X1 port map( A1 => n125, A2 => IN2(21), ZN => n90);
U30 : NAND2_X1 port map( A1 => n125, A2 => IN2(13), ZN => n124);
U31 : AND2_X1 port map( A1 => n63, A2 => IN2(16), ZN => n95);
U32 : AOI222_X1 port map( A1 => n130, A2 => IN1(4), B1 => n127, B2 => IN0(4)
, C1 => n63, C2 => IN2(4), ZN => n147);
U33 : AOI222_X1 port map( A1 => n71, A2 => IN1(19), B1 => n127, B2 =>
IN0(19), C1 => n63, C2 => IN2(19), ZN => n136);
U34 : NAND2_X1 port map( A1 => n125, A2 => IN2(8), ZN => n85);
U35 : NAND3_X1 port map( A1 => n66, A2 => n68, A3 => n65, ZN => OUT1(0));
U36 : INV_X1 port map( A => CTRL(1), ZN => n64);
U37 : NAND2_X1 port map( A1 => n131, A2 => IN1(0), ZN => n65);
U38 : NAND2_X1 port map( A1 => n128, A2 => IN0(0), ZN => n66);
U39 : AOI22_X1 port map( A1 => n131, A2 => IN1(1), B1 => n127, B2 => IN0(1),
ZN => n69);
U40 : NAND2_X1 port map( A1 => n69, A2 => n70, ZN => OUT1(1));
U41 : INV_X1 port map( A => n146, ZN => OUT1(3));
U42 : AOI222_X1 port map( A1 => n130, A2 => IN1(28), B1 => n126, B2 =>
IN0(28), C1 => n83, C2 => IN2(28), ZN => n142);
U43 : BUF_X2 port map( A => n149, Z => n71);
U44 : NOR2_X2 port map( A1 => CTRL(1), A2 => CTRL(0), ZN => n148);
U45 : CLKBUF_X3 port map( A => n148, Z => n126);
U46 : BUF_X2 port map( A => n149, Z => n130);
U47 : AND2_X2 port map( A1 => CTRL(0), A2 => n82, ZN => n149);
U48 : BUF_X2 port map( A => n149, Z => n129);
U49 : INV_X1 port map( A => n138, ZN => OUT1(24));
U50 : INV_X1 port map( A => n139, ZN => OUT1(25));
U51 : AND2_X1 port map( A1 => n83, A2 => IN2(26), ZN => n99);
U52 : AND2_X1 port map( A1 => n127, A2 => IN0(26), ZN => n98);
U53 : AND2_X1 port map( A1 => n129, A2 => IN1(26), ZN => n97);
U54 : INV_X1 port map( A => n141, ZN => OUT1(27));
U55 : INV_X1 port map( A => n142, ZN => OUT1(28));
U56 : INV_X1 port map( A => n137, ZN => OUT1(20));
U57 : AND2_X1 port map( A1 => n129, A2 => IN1(12), ZN => n96);
U58 : INV_X1 port map( A => n147, ZN => OUT1(4));
U59 : INV_X1 port map( A => n144, ZN => OUT1(2));
U60 : INV_X1 port map( A => n136, ZN => OUT1(19));
U61 : AND2_X1 port map( A1 => n127, A2 => IN0(16), ZN => n94);
U62 : AND2_X1 port map( A1 => n130, A2 => IN1(16), ZN => n93);
U63 : AND2_X1 port map( A1 => n83, A2 => IN2(17), ZN => n114);
U64 : AND2_X1 port map( A1 => n127, A2 => IN0(17), ZN => n113);
U65 : AND2_X1 port map( A1 => n129, A2 => IN1(17), ZN => n112);
U66 : INV_X1 port map( A => n135, ZN => OUT1(18));
U67 : INV_X1 port map( A => CTRL(1), ZN => n81);
U68 : INV_X1 port map( A => CTRL(1), ZN => n82);
U69 : INV_X1 port map( A => n132, ZN => OUT1(10));
U70 : NAND3_X1 port map( A1 => n106, A2 => n107, A3 => n108, ZN => OUT1(6));
U71 : NAND3_X1 port map( A1 => n109, A2 => n110, A3 => n111, ZN => OUT1(7));
U72 : NAND3_X1 port map( A1 => n119, A2 => n120, A3 => n121, ZN => OUT1(9));
U73 : NAND3_X1 port map( A1 => n115, A2 => n116, A3 => n117, ZN => OUT1(14))
;
U74 : NAND3_X1 port map( A1 => n100, A2 => n101, A3 => n102, ZN => OUT1(11))
;
U75 : NAND3_X1 port map( A1 => n122, A2 => n123, A3 => n124, ZN => OUT1(13))
;
U76 : NAND3_X1 port map( A1 => n103, A2 => n104, A3 => n105, ZN => OUT1(5));
U77 : AOI222_X1 port map( A1 => n129, A2 => IN1(25), B1 => n128, B2 =>
IN0(25), C1 => n125, C2 => IN2(25), ZN => n139);
U78 : AOI222_X1 port map( A1 => n71, A2 => IN1(3), B1 => n126, B2 => IN0(3),
C1 => n83, C2 => IN2(3), ZN => n146);
U79 : AOI222_X1 port map( A1 => n130, A2 => IN1(18), B1 => n126, B2 =>
IN0(18), C1 => n63, C2 => IN2(18), ZN => n135);
U80 : NAND3_X1 port map( A1 => n84, A2 => n85, A3 => n86, ZN => OUT1(8));
U81 : NAND2_X1 port map( A1 => n130, A2 => IN1(8), ZN => n84);
U82 : NAND2_X1 port map( A1 => n126, A2 => IN0(8), ZN => n86);
U83 : NAND3_X1 port map( A1 => n87, A2 => n88, A3 => n89, ZN => OUT1(22));
U84 : NAND2_X1 port map( A1 => n125, A2 => IN2(22), ZN => n87);
U85 : NAND2_X1 port map( A1 => n71, A2 => IN1(22), ZN => n88);
U86 : NAND2_X1 port map( A1 => n126, A2 => IN0(22), ZN => n89);
U87 : NAND3_X1 port map( A1 => n90, A2 => n91, A3 => n92, ZN => OUT1(21));
U88 : NAND2_X1 port map( A1 => n71, A2 => IN1(21), ZN => n91);
U89 : NAND2_X1 port map( A1 => n126, A2 => IN0(21), ZN => n92);
U90 : NAND2_X1 port map( A1 => n71, A2 => IN1(11), ZN => n100);
U91 : NAND2_X1 port map( A1 => n126, A2 => IN0(11), ZN => n101);
U92 : NAND2_X1 port map( A1 => n125, A2 => IN2(11), ZN => n102);
U93 : NAND2_X1 port map( A1 => n129, A2 => IN1(5), ZN => n103);
U94 : NAND2_X1 port map( A1 => n126, A2 => IN0(5), ZN => n104);
U95 : NAND2_X1 port map( A1 => n63, A2 => IN2(5), ZN => n105);
U96 : NAND2_X1 port map( A1 => n129, A2 => IN1(6), ZN => n106);
U97 : NAND2_X1 port map( A1 => n128, A2 => IN0(6), ZN => n107);
U98 : NAND2_X1 port map( A1 => n83, A2 => IN2(6), ZN => n108);
U99 : NAND2_X1 port map( A1 => n130, A2 => IN1(7), ZN => n109);
U100 : NAND2_X1 port map( A1 => n126, A2 => IN0(7), ZN => n110);
U101 : NAND2_X1 port map( A1 => n83, A2 => IN2(7), ZN => n111);
U102 : NAND2_X1 port map( A1 => n129, A2 => IN1(14), ZN => n115);
U103 : NAND2_X1 port map( A1 => n128, A2 => IN0(14), ZN => n116);
U104 : NAND2_X1 port map( A1 => n125, A2 => IN2(14), ZN => n117);
U105 : NAND2_X1 port map( A1 => n129, A2 => IN1(9), ZN => n119);
U106 : NAND2_X1 port map( A1 => n128, A2 => IN0(9), ZN => n120);
U107 : NAND2_X1 port map( A1 => n125, A2 => IN2(9), ZN => n121);
U108 : NAND2_X1 port map( A1 => n130, A2 => IN1(13), ZN => n122);
U109 : NAND2_X1 port map( A1 => n126, A2 => IN0(13), ZN => n123);
U110 : AOI222_X1 port map( A1 => n130, A2 => IN1(24), B1 => n128, B2 =>
IN0(24), C1 => n125, C2 => IN2(24), ZN => n138);
U111 : AOI222_X1 port map( A1 => n71, A2 => IN1(2), B1 => n126, B2 => IN0(2)
, C1 => n125, C2 => IN2(2), ZN => n144);
U112 : AOI222_X1 port map( A1 => n71, A2 => IN1(27), B1 => n126, B2 =>
IN0(27), C1 => n83, C2 => IN2(27), ZN => n141);
U113 : AOI222_X1 port map( A1 => n130, A2 => IN1(20), B1 => n127, B2 =>
IN0(20), C1 => n83, C2 => IN2(20), ZN => n137);
U114 : AOI222_X1 port map( A1 => n129, A2 => IN1(10), B1 => n127, B2 =>
IN0(10), C1 => n83, C2 => IN2(10), ZN => n132);
end SYN_bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity mux21_1 is
port( IN0, IN1 : in std_logic_vector (31 downto 0); CTRL : in std_logic;
OUT1 : out std_logic_vector (31 downto 0));
end mux21_1;
architecture SYN_Bhe of mux21_1 is
component NOR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component MUX2_X1
port( A, B, S : in std_logic; Z : out std_logic);
end component;
signal n1 : std_logic;
begin
U1 : MUX2_X1 port map( A => IN0(9), B => IN1(9), S => CTRL, Z => OUT1(9));
U2 : MUX2_X1 port map( A => IN0(8), B => IN1(8), S => CTRL, Z => OUT1(8));
U3 : MUX2_X1 port map( A => IN0(7), B => IN1(7), S => CTRL, Z => OUT1(7));
U4 : MUX2_X1 port map( A => IN0(6), B => IN1(6), S => CTRL, Z => OUT1(6));
U5 : MUX2_X1 port map( A => IN0(5), B => IN1(5), S => CTRL, Z => OUT1(5));
U6 : MUX2_X1 port map( A => IN0(4), B => IN1(4), S => CTRL, Z => OUT1(4));
U7 : MUX2_X1 port map( A => IN0(3), B => IN1(3), S => CTRL, Z => OUT1(3));
U8 : MUX2_X1 port map( A => IN0(31), B => IN1(31), S => CTRL, Z => OUT1(31))
;
U9 : MUX2_X1 port map( A => IN0(30), B => IN1(30), S => CTRL, Z => OUT1(30))
;
U10 : MUX2_X1 port map( A => IN0(2), B => IN1(2), S => CTRL, Z => OUT1(2));
U12 : MUX2_X1 port map( A => IN0(28), B => IN1(28), S => CTRL, Z => OUT1(28)
);
U13 : MUX2_X1 port map( A => IN0(27), B => IN1(27), S => CTRL, Z => OUT1(27)
);
U14 : MUX2_X1 port map( A => IN0(26), B => IN1(26), S => CTRL, Z => OUT1(26)
);
U15 : MUX2_X1 port map( A => IN0(25), B => IN1(25), S => CTRL, Z => OUT1(25)
);
U16 : MUX2_X1 port map( A => IN0(24), B => IN1(24), S => CTRL, Z => OUT1(24)
);
U17 : MUX2_X1 port map( A => IN0(23), B => IN1(23), S => CTRL, Z => OUT1(23)
);
U18 : MUX2_X1 port map( A => IN0(22), B => IN1(22), S => CTRL, Z => OUT1(22)
);
U19 : MUX2_X1 port map( A => IN0(21), B => IN1(21), S => CTRL, Z => OUT1(21)
);
U20 : MUX2_X1 port map( A => IN0(20), B => IN1(20), S => CTRL, Z => OUT1(20)
);
U21 : MUX2_X1 port map( A => IN0(1), B => IN1(1), S => CTRL, Z => OUT1(1));
U22 : MUX2_X1 port map( A => IN0(19), B => IN1(19), S => CTRL, Z => OUT1(19)
);
U23 : MUX2_X1 port map( A => IN0(18), B => IN1(18), S => CTRL, Z => OUT1(18)
);
U24 : MUX2_X1 port map( A => IN0(17), B => IN1(17), S => CTRL, Z => OUT1(17)
);
U25 : MUX2_X1 port map( A => IN0(16), B => IN1(16), S => CTRL, Z => OUT1(16)
);
U26 : MUX2_X1 port map( A => IN0(15), B => IN1(15), S => CTRL, Z => OUT1(15)
);
U27 : MUX2_X1 port map( A => IN0(14), B => IN1(14), S => CTRL, Z => OUT1(14)
);
U28 : MUX2_X1 port map( A => IN0(13), B => IN1(13), S => CTRL, Z => OUT1(13)
);
U29 : MUX2_X1 port map( A => IN0(12), B => IN1(12), S => CTRL, Z => OUT1(12)
);
U30 : MUX2_X1 port map( A => IN0(11), B => IN1(11), S => CTRL, Z => OUT1(11)
);
U31 : MUX2_X1 port map( A => IN0(10), B => IN1(10), S => CTRL, Z => OUT1(10)
);
U11 : MUX2_X1 port map( A => IN0(29), B => IN1(29), S => CTRL, Z => OUT1(29)
);
U32 : INV_X1 port map( A => IN0(0), ZN => n1);
U33 : NOR2_X1 port map( A1 => CTRL, A2 => n1, ZN => OUT1(0));
end SYN_Bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_0 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_0;
architecture SYN_BEHAVIORAL of FA_0 is
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
begin
U1 : AND2_X1 port map( A1 => B, A2 => A, ZN => Co);
U2 : XOR2_X1 port map( A => B, B => A, Z => S);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity mux21_SIZE4_0 is
port( IN0, IN1 : in std_logic_vector (3 downto 0); CTRL : in std_logic;
OUT1 : out std_logic_vector (3 downto 0));
end mux21_SIZE4_0;
architecture SYN_Bhe of mux21_SIZE4_0 is
component MUX2_X1
port( A, B, S : in std_logic; Z : out std_logic);
end component;
begin
U2 : MUX2_X1 port map( A => IN0(2), B => IN1(2), S => CTRL, Z => OUT1(2));
U3 : MUX2_X1 port map( A => IN0(1), B => IN1(1), S => CTRL, Z => OUT1(1));
U4 : MUX2_X1 port map( A => IN0(0), B => IN1(0), S => CTRL, Z => OUT1(0));
U1 : MUX2_X1 port map( A => IN0(3), B => IN1(3), S => CTRL, Z => OUT1(3));
end SYN_Bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity RCA_N4_0 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end RCA_N4_0;
architecture SYN_STRUCTURAL of RCA_N4_0 is
component FA_61
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_62
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_63
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_0
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
signal n1, CTMP_3_port, CTMP_2_port, CTMP_1_port, net561330 : std_logic;
begin
FAI_1 : FA_0 port map( A => A(0), B => B(0), Ci => n1, S => S(0), Co =>
CTMP_1_port);
FAI_2 : FA_63 port map( A => A(1), B => B(1), Ci => CTMP_1_port, S => S(1),
Co => CTMP_2_port);
FAI_3 : FA_62 port map( A => A(2), B => B(2), Ci => CTMP_2_port, S => S(2),
Co => CTMP_3_port);
FAI_4 : FA_61 port map( A => A(3), B => B(3), Ci => CTMP_3_port, S => S(3),
Co => net561330);
n1 <= '0';
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity carry_sel_gen_N4_0 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end carry_sel_gen_N4_0;
architecture SYN_STRUCTURAL of carry_sel_gen_N4_0 is
component mux21_SIZE4_0
port( IN0, IN1 : in std_logic_vector (3 downto 0); CTRL : in std_logic;
OUT1 : out std_logic_vector (3 downto 0));
end component;
component RCA_N4_15
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
component RCA_N4_0
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
signal X_Logic1_port, X_Logic0_port, nocarry_sum_to_mux_3_port,
nocarry_sum_to_mux_2_port, nocarry_sum_to_mux_1_port,
nocarry_sum_to_mux_0_port, carry_sum_to_mux_3_port,
carry_sum_to_mux_2_port, carry_sum_to_mux_1_port, carry_sum_to_mux_0_port
, net561328, net561329 : std_logic;
begin
X_Logic1_port <= '1';
X_Logic0_port <= '0';
rca_nocarry : RCA_N4_0 port map( A(3) => A(3), A(2) => A(2), A(1) => A(1),
A(0) => A(0), B(3) => B(3), B(2) => B(2), B(1) =>
B(1), B(0) => B(0), Ci => X_Logic0_port, S(3) =>
nocarry_sum_to_mux_3_port, S(2) =>
nocarry_sum_to_mux_2_port, S(1) =>
nocarry_sum_to_mux_1_port, S(0) =>
nocarry_sum_to_mux_0_port, Co => net561329);
rca_carry : RCA_N4_15 port map( A(3) => A(3), A(2) => A(2), A(1) => A(1),
A(0) => A(0), B(3) => B(3), B(2) => B(2), B(1) =>
B(1), B(0) => B(0), Ci => X_Logic1_port, S(3) =>
carry_sum_to_mux_3_port, S(2) =>
carry_sum_to_mux_2_port, S(1) =>
carry_sum_to_mux_1_port, S(0) =>
carry_sum_to_mux_0_port, Co => net561328);
outmux : mux21_SIZE4_0 port map( IN0(3) => nocarry_sum_to_mux_3_port, IN0(2)
=> nocarry_sum_to_mux_2_port, IN0(1) =>
nocarry_sum_to_mux_1_port, IN0(0) =>
nocarry_sum_to_mux_0_port, IN1(3) =>
carry_sum_to_mux_3_port, IN1(2) =>
carry_sum_to_mux_2_port, IN1(1) =>
carry_sum_to_mux_1_port, IN1(0) =>
carry_sum_to_mux_0_port, CTRL => Ci, OUT1(3) => S(3)
, OUT1(2) => S(2), OUT1(1) => S(1), OUT1(0) => S(0))
;
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_0 is
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic);
end pg_0;
architecture SYN_beh of pg_0 is
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
signal n2, n3 : std_logic;
begin
U1 : AND2_X1 port map( A1 => p, A2 => p_prec, ZN => p_out);
U2 : INV_X1 port map( A => g, ZN => n3);
U3 : NAND2_X1 port map( A1 => p, A2 => g_prec, ZN => n2);
U4 : NAND2_X1 port map( A1 => n2, A2 => n3, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity g_0 is
port( g, p, g_prec : in std_logic; g_out : out std_logic);
end g_0;
architecture SYN_beh of g_0 is
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
signal n2 : std_logic;
begin
U1 : AOI21_X1 port map( B1 => p, B2 => g_prec, A => g, ZN => n2);
U2 : INV_X1 port map( A => n2, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_0 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_0;
architecture SYN_beh of pg_net_0 is
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component NOR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
signal n1, n2 : std_logic;
begin
U1 : NOR2_X1 port map( A1 => n2, A2 => n1, ZN => g_out);
U2 : XNOR2_X1 port map( A => n1, B => b, ZN => p_out);
U3 : INV_X1 port map( A => a, ZN => n1);
U4 : INV_X1 port map( A => b, ZN => n2);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity shift_thirdLevel is
port( sel : in std_logic_vector (2 downto 0); A : in std_logic_vector (38
downto 0); Y : out std_logic_vector (31 downto 0));
end shift_thirdLevel;
architecture SYN_behav of shift_thirdLevel is
component NOR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component BUF_X1
port( A : in std_logic; Z : out std_logic);
end component;
component AOI22_X1
port( A1, A2, B1, B2 : in std_logic; ZN : out std_logic);
end component;
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component OAI22_X1
port( A1, A2, B1, B2 : in std_logic; ZN : out std_logic);
end component;
component OAI222_X1
port( A1, A2, B1, B2, C1, C2 : in std_logic; ZN : out std_logic);
end component;
signal n17, n18, n20, n21, n22, n23, n24, n25, n26, n28, n29, n31, n32, n33,
n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44, n45, n46, n48, n49
, n50, n51, n52, n53, n54, n55, n56, n57, n58, n59, n60, n61, n62, n63,
n64, n65, n66, n67, n68, n69, n70, n71, n72, n73, n74, n75, n76, n77, n78
, n79, n80, n81, n82, n83, n84, n85, n86, n87, n88, n89, n90, n91, n92,
n93, n94, n95, n96, n97, n98, n99, n100, n101, n102, n103, n104, n105,
n106, n107, n108, n109, n110, n111, n112, n113, n114, n115, n116, n117,
n118, n119, n120, n121, n122, n123, n124, n125, n126, n127, n128, n129,
n130, n131, n132, n133, n134, n135, n136, n137, n138, n139, n140, n141 :
std_logic;
begin
U144 : AOI22_X1 port map( A1 => n135, A2 => A(0), B1 => n40, B2 => A(2), ZN
=> n129);
U140 : AOI22_X1 port map( A1 => n137, A2 => A(4), B1 => n23, B2 => A(6), ZN
=> n130);
U137 : OAI22_X1 port map( A1 => A(1), A2 => n134, B1 => A(3), B2 => n26, ZN
=> n132);
U136 : AOI21_X1 port map( B1 => n23, B2 => n36, A => n132, ZN => n131);
U135 : OAI21_X1 port map( B1 => A(5), B2 => n136, A => n131, ZN => n93);
U134 : OAI222_X1 port map( A1 => n141, A2 => n129, B1 => n141, B2 => n130,
C1 => n138, C2 => n93, ZN => Y(0));
U29 : AOI22_X1 port map( A1 => n135, A2 => A(32), B1 => n40, B2 => A(34), ZN
=> n49);
U28 : AOI22_X1 port map( A1 => n137, A2 => A(36), B1 => n23, B2 => A(38), ZN
=> n50);
U33 : OAI22_X1 port map( A1 => A(33), A2 => n26, B1 => A(37), B2 => n33, ZN
=> n55);
U32 : AOI21_X1 port map( B1 => n135, B2 => n54, A => n55, ZN => n53);
U31 : OAI21_X1 port map( B1 => A(35), B2 => n136, A => n53, ZN => n51);
U27 : OAI222_X1 port map( A1 => n138, A2 => n49, B1 => n138, B2 => n50, C1
=> n51, C2 => n141, ZN => Y(31));
U93 : OAI22_X1 port map( A1 => A(19), A2 => n134, B1 => A(21), B2 => n26, ZN
=> n101);
U92 : AOI21_X1 port map( B1 => n23, B2 => n78, A => n101, ZN => n100);
U91 : OAI21_X1 port map( B1 => A(23), B2 => n136, A => n100, ZN => n96);
U89 : OAI22_X1 port map( A1 => A(20), A2 => n134, B1 => A(22), B2 => n26, ZN
=> n98);
U88 : AOI21_X1 port map( B1 => n137, B2 => n82, A => n98, ZN => n97);
U87 : OAI21_X1 port map( B1 => A(26), B2 => n33, A => n97, ZN => n90);
U86 : AOI22_X1 port map( A1 => sel(0), A2 => n96, B1 => n90, B2 => n140, ZN
=> Y(19));
U80 : OAI22_X1 port map( A1 => A(21), A2 => n134, B1 => A(23), B2 => n26, ZN
=> n92);
U79 : AOI21_X1 port map( B1 => n137, B2 => n78, A => n92, ZN => n91);
U78 : OAI21_X1 port map( B1 => A(27), B2 => n33, A => n91, ZN => n87);
U77 : AOI22_X1 port map( A1 => n139, A2 => n90, B1 => n87, B2 => n140, ZN =>
Y(20));
U76 : OAI22_X1 port map( A1 => A(22), A2 => n134, B1 => A(28), B2 => n33, ZN
=> n89);
U75 : AOI21_X1 port map( B1 => n40, B2 => n82, A => n89, ZN => n88);
U74 : OAI21_X1 port map( B1 => A(26), B2 => n21, A => n88, ZN => n84);
U73 : AOI22_X1 port map( A1 => n139, A2 => n87, B1 => n84, B2 => n140, ZN =>
Y(21));
U38 : OAI22_X1 port map( A1 => A(5), A2 => n26, B1 => A(3), B2 => n134, ZN
=> n58);
U37 : AOI21_X1 port map( B1 => n137, B2 => n36, A => n58, ZN => n57);
U36 : OAI21_X1 port map( B1 => A(9), B2 => n33, A => n57, ZN => n45);
U26 : OAI22_X1 port map( A1 => A(6), A2 => n26, B1 => A(4), B2 => n134, ZN
=> n48);
U25 : AOI21_X1 port map( B1 => n137, B2 => n31, A => n48, ZN => n46);
U24 : OAI21_X1 port map( B1 => A(10), B2 => n33, A => n46, ZN => n42);
U23 : AOI22_X1 port map( A1 => n138, A2 => n45, B1 => n42, B2 => n140, ZN =>
Y(3));
U72 : OAI22_X1 port map( A1 => A(23), A2 => n134, B1 => A(29), B2 => n33, ZN
=> n86);
U71 : AOI21_X1 port map( B1 => n40, B2 => n78, A => n86, ZN => n85);
U70 : OAI21_X1 port map( B1 => A(27), B2 => n21, A => n85, ZN => n80);
U69 : AOI22_X1 port map( A1 => n139, A2 => n84, B1 => n80, B2 => n140, ZN =>
Y(22));
U68 : OAI22_X1 port map( A1 => A(26), A2 => n26, B1 => A(30), B2 => n33, ZN
=> n83);
U67 : AOI21_X1 port map( B1 => n135, B2 => n82, A => n83, ZN => n81);
U66 : OAI21_X1 port map( B1 => A(28), B2 => n136, A => n81, ZN => n76);
U64 : OAI22_X1 port map( A1 => A(27), A2 => n26, B1 => A(31), B2 => n33, ZN
=> n79);
U63 : AOI21_X1 port map( B1 => n135, B2 => n78, A => n79, ZN => n77);
U62 : OAI21_X1 port map( B1 => A(29), B2 => n136, A => n77, ZN => n73);
U61 : AOI22_X1 port map( A1 => sel(0), A2 => n76, B1 => n73, B2 => n140, ZN
=> Y(24));
U111 : OAI22_X1 port map( A1 => A(15), A2 => n134, B1 => A(21), B2 => n33,
ZN => n115);
U110 : AOI21_X1 port map( B1 => n40, B2 => n107, A => n115, ZN => n114);
U109 : OAI21_X1 port map( B1 => A(19), B2 => n21, A => n114, ZN => n109);
U107 : OAI22_X1 port map( A1 => A(18), A2 => n26, B1 => A(22), B2 => n33, ZN
=> n112);
U106 : AOI21_X1 port map( B1 => n135, B2 => n111, A => n112, ZN => n110);
U105 : OAI21_X1 port map( B1 => A(20), B2 => n21, A => n110, ZN => n105);
U104 : AOI22_X1 port map( A1 => n139, A2 => n109, B1 => n105, B2 => n141, ZN
=> Y(15));
U10 : OAI22_X1 port map( A1 => A(14), A2 => n33, B1 => A(10), B2 => n26, ZN
=> n32);
U9 : AOI21_X1 port map( B1 => n135, B2 => n31, A => n32, ZN => n29);
U8 : OAI21_X1 port map( B1 => A(12), B2 => n136, A => n29, ZN => n20);
U5 : OAI22_X1 port map( A1 => A(11), A2 => n26, B1 => A(9), B2 => n134, ZN
=> n25);
U4 : AOI21_X1 port map( B1 => n23, B2 => n24, A => n25, ZN => n22);
U3 : OAI21_X1 port map( B1 => A(13), B2 => n136, A => n22, ZN => n17);
U2 : AOI22_X1 port map( A1 => n138, A2 => n20, B1 => n17, B2 => n140, ZN =>
Y(8));
U18 : OAI22_X1 port map( A1 => A(6), A2 => n134, B1 => A(12), B2 => n33, ZN
=> n41);
U17 : AOI21_X1 port map( B1 => n40, B2 => n31, A => n41, ZN => n39);
U16 : OAI21_X1 port map( B1 => A(10), B2 => n136, A => n39, ZN => n34);
U14 : OAI22_X1 port map( A1 => A(13), A2 => n33, B1 => A(9), B2 => n26, ZN
=> n37);
U13 : AOI21_X1 port map( B1 => n135, B2 => n36, A => n37, ZN => n35);
U12 : OAI21_X1 port map( B1 => A(11), B2 => n136, A => n35, ZN => n28);
U11 : AOI22_X1 port map( A1 => n138, A2 => n34, B1 => n28, B2 => n140, ZN =>
Y(6));
U59 : OAI22_X1 port map( A1 => A(26), A2 => n134, B1 => A(28), B2 => n26, ZN
=> n75);
U58 : AOI21_X1 port map( B1 => n23, B2 => n61, A => n75, ZN => n74);
U57 : OAI21_X1 port map( B1 => A(30), B2 => n136, A => n74, ZN => n70);
U56 : AOI22_X1 port map( A1 => sel(0), A2 => n73, B1 => n70, B2 => n140, ZN
=> Y(25));
U103 : OAI22_X1 port map( A1 => A(19), A2 => n26, B1 => A(23), B2 => n33, ZN
=> n108);
U102 : AOI21_X1 port map( B1 => n135, B2 => n107, A => n108, ZN => n106);
U101 : OAI21_X1 port map( B1 => A(21), B2 => n21, A => n106, ZN => n102);
U98 : OAI22_X1 port map( A1 => A(18), A2 => n134, B1 => A(20), B2 => n26, ZN
=> n104);
U97 : AOI21_X1 port map( B1 => n23, B2 => n82, A => n104, ZN => n103);
U96 : OAI21_X1 port map( B1 => A(22), B2 => n21, A => n103, ZN => n99);
U95 : AOI22_X1 port map( A1 => n139, A2 => n102, B1 => n99, B2 => n140, ZN
=> Y(17));
U123 : OAI22_X1 port map( A1 => A(14), A2 => n26, B1 => A(12), B2 => n134,
ZN => n124);
U122 : AOI21_X1 port map( B1 => n137, B2 => n111, A => n124, ZN => n123);
U121 : OAI21_X1 port map( B1 => A(18), B2 => n33, A => n123, ZN => n119);
U119 : OAI22_X1 port map( A1 => A(15), A2 => n26, B1 => A(13), B2 => n134,
ZN => n121);
U118 : AOI21_X1 port map( B1 => n137, B2 => n107, A => n121, ZN => n120);
U117 : OAI21_X1 port map( B1 => A(19), B2 => n33, A => n120, ZN => n116);
U116 : AOI22_X1 port map( A1 => n139, A2 => n119, B1 => n116, B2 => n141, ZN
=> Y(12));
U100 : AOI22_X1 port map( A1 => n139, A2 => n105, B1 => n102, B2 => n140, ZN
=> Y(16));
U50 : OAI22_X1 port map( A1 => A(28), A2 => n134, B1 => A(30), B2 => n26, ZN
=> n69);
U49 : AOI21_X1 port map( B1 => n137, B2 => n61, A => n69, ZN => n68);
U48 : OAI21_X1 port map( B1 => A(34), B2 => n33, A => n68, ZN => n63);
U46 : OAI22_X1 port map( A1 => A(31), A2 => n26, B1 => A(35), B2 => n33, ZN
=> n66);
U45 : AOI21_X1 port map( B1 => n135, B2 => n65, A => n66, ZN => n64);
U44 : OAI21_X1 port map( B1 => A(33), B2 => n136, A => n64, ZN => n59);
U43 : AOI22_X1 port map( A1 => n139, A2 => n63, B1 => n59, B2 => n140, ZN =>
Y(28));
U22 : OAI22_X1 port map( A1 => A(5), A2 => n134, B1 => A(11), B2 => n33, ZN
=> n44);
U21 : AOI21_X1 port map( B1 => n40, B2 => n36, A => n44, ZN => n43);
U20 : OAI21_X1 port map( B1 => A(9), B2 => n136, A => n43, ZN => n38);
U19 : AOI22_X1 port map( A1 => n138, A2 => n42, B1 => n38, B2 => n140, ZN =>
Y(4));
U54 : OAI22_X1 port map( A1 => A(27), A2 => n134, B1 => A(33), B2 => n33, ZN
=> n72);
U53 : AOI21_X1 port map( B1 => n40, B2 => n65, A => n72, ZN => n71);
U52 : OAI21_X1 port map( B1 => A(31), B2 => n136, A => n71, ZN => n67);
U47 : AOI22_X1 port map( A1 => n139, A2 => n67, B1 => n63, B2 => n140, ZN =>
Y(27));
U15 : AOI22_X1 port map( A1 => n138, A2 => n38, B1 => n34, B2 => n140, ZN =>
Y(5));
U115 : OAI22_X1 port map( A1 => A(14), A2 => n134, B1 => A(20), B2 => n33,
ZN => n118);
U114 : AOI21_X1 port map( B1 => n40, B2 => n111, A => n118, ZN => n117);
U113 : OAI21_X1 port map( B1 => A(18), B2 => n21, A => n117, ZN => n113);
U112 : AOI22_X1 port map( A1 => n139, A2 => n116, B1 => n113, B2 => n141, ZN
=> Y(13));
U132 : OAI22_X1 port map( A1 => A(12), A2 => n26, B1 => A(10), B2 => n134,
ZN => n128);
U131 : AOI21_X1 port map( B1 => n23, B2 => n111, A => n128, ZN => n127);
U130 : OAI21_X1 port map( B1 => A(14), B2 => n21, A => n127, ZN => n18);
U1 : AOI22_X1 port map( A1 => n139, A2 => n17, B1 => n18, B2 => n140, ZN =>
Y(9));
U7 : AOI22_X1 port map( A1 => n138, A2 => n28, B1 => n20, B2 => n140, ZN =>
Y(7));
U108 : AOI22_X1 port map( A1 => n139, A2 => n113, B1 => n109, B2 => n141, ZN
=> Y(14));
U90 : AOI22_X1 port map( A1 => n139, A2 => n99, B1 => n96, B2 => n140, ZN =>
Y(18));
U65 : AOI22_X1 port map( A1 => sel(0), A2 => n80, B1 => n76, B2 => n140, ZN
=> Y(23));
U51 : AOI22_X1 port map( A1 => n139, A2 => n70, B1 => n67, B2 => n140, ZN =>
Y(26));
U42 : OAI22_X1 port map( A1 => A(30), A2 => n134, B1 => A(36), B2 => n33, ZN
=> n62);
U41 : AOI21_X1 port map( B1 => n40, B2 => n61, A => n62, ZN => n60);
U40 : OAI21_X1 port map( B1 => A(34), B2 => n136, A => n60, ZN => n52);
U39 : AOI22_X1 port map( A1 => n138, A2 => n59, B1 => n52, B2 => n140, ZN =>
Y(29));
U84 : OAI22_X1 port map( A1 => A(4), A2 => n26, B1 => A(2), B2 => n134, ZN
=> n95);
U83 : AOI21_X1 port map( B1 => n23, B2 => n31, A => n95, ZN => n94);
U82 : OAI21_X1 port map( B1 => A(6), B2 => n136, A => n94, ZN => n56);
U35 : AOI22_X1 port map( A1 => n138, A2 => n56, B1 => n45, B2 => n140, ZN =>
Y(2));
U81 : AOI22_X1 port map( A1 => sel(0), A2 => n93, B1 => n56, B2 => n140, ZN
=> Y(1));
U30 : AOI22_X1 port map( A1 => n138, A2 => n52, B1 => n51, B2 => n140, ZN =>
Y(30));
U128 : OAI22_X1 port map( A1 => A(13), A2 => n26, B1 => A(11), B2 => n134,
ZN => n126);
U127 : AOI21_X1 port map( B1 => n23, B2 => n107, A => n126, ZN => n125);
U126 : OAI21_X1 port map( B1 => A(15), B2 => n21, A => n125, ZN => n122);
U120 : AOI22_X1 port map( A1 => n139, A2 => n122, B1 => n119, B2 => n141, ZN
=> Y(11));
U125 : AOI22_X1 port map( A1 => n139, A2 => n18, B1 => n122, B2 => n141, ZN
=> Y(10));
U146 : INV_X1 port map( A => sel(2), ZN => n133);
U138 : INV_X1 port map( A => n40, ZN => n26);
U34 : INV_X1 port map( A => A(31), ZN => n54);
U124 : INV_X1 port map( A => n23, ZN => n33);
U94 : INV_X1 port map( A => A(25), ZN => n78);
U99 : INV_X1 port map( A => A(24), ZN => n82);
U85 : INV_X1 port map( A => A(8), ZN => n31);
U129 : INV_X1 port map( A => A(17), ZN => n107);
U133 : INV_X1 port map( A => A(16), ZN => n111);
U6 : INV_X1 port map( A => A(15), ZN => n24);
U60 : INV_X1 port map( A => A(32), ZN => n61);
U55 : INV_X1 port map( A => A(29), ZN => n65);
U139 : INV_X1 port map( A => A(7), ZN => n36);
U141 : INV_X1 port map( A => n135, ZN => n134);
U142 : BUF_X1 port map( A => sel(0), Z => n138);
U143 : BUF_X1 port map( A => sel(0), Z => n139);
U145 : INV_X1 port map( A => n138, ZN => n140);
U147 : INV_X1 port map( A => n137, ZN => n136);
U148 : INV_X1 port map( A => n21, ZN => n137);
U149 : NAND2_X1 port map( A1 => n133, A2 => sel(1), ZN => n21);
U150 : NOR2_X1 port map( A1 => sel(1), A2 => n133, ZN => n40);
U151 : AND2_X1 port map( A1 => sel(2), A2 => sel(1), ZN => n135);
U152 : INV_X1 port map( A => n139, ZN => n141);
U153 : NOR2_X1 port map( A1 => sel(2), A2 => sel(1), ZN => n23);
end SYN_behav;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity shift_secondLevel is
port( sel : in std_logic_vector (1 downto 0); mask00, mask08, mask16 : in
std_logic_vector (38 downto 0); Y : out std_logic_vector (38 downto
0));
end shift_secondLevel;
architecture SYN_behav of shift_secondLevel is
component NOR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component NOR2_X2
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component AND2_X2
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component BUF_X1
port( A : in std_logic; Z : out std_logic);
end component;
component BUF_X2
port( A : in std_logic; Z : out std_logic);
end component;
component AOI222_X1
port( A1, A2, B1, B2, C1, C2 : in std_logic; ZN : out std_logic);
end component;
signal n41, n42, n43, n44, n45, n47, n48, n49, n50, n51, n52, n53, n54, n55,
n56, n57, n58, n59, n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, n70
, n71, n72, n73, n74, n75, n76, n77, n78, n79, n80, n81, n82, n83, n46,
n84, n92 : std_logic;
begin
U79 : AOI222_X1 port map( A1 => n84, A2 => mask00(0), B1 => n43, B2 =>
mask16(0), C1 => n44, C2 => mask08(0), ZN => n82);
U35 : AOI222_X1 port map( A1 => n84, A2 => mask00(2), B1 => n43, B2 =>
mask16(2), C1 => n92, C2 => mask08(2), ZN => n60);
U13 : AOI222_X1 port map( A1 => n84, A2 => mask00(4), B1 => n43, B2 =>
mask16(4), C1 => n92, C2 => mask08(4), ZN => n49);
U9 : AOI222_X1 port map( A1 => n84, A2 => mask00(6), B1 => n43, B2 =>
mask16(6), C1 => n92, C2 => mask08(6), ZN => n47);
U11 : AOI222_X1 port map( A1 => n84, A2 => mask00(5), B1 => n43, B2 =>
mask16(5), C1 => n92, C2 => mask08(5), ZN => n48);
U57 : AOI222_X1 port map( A1 => n84, A2 => mask00(1), B1 => n43, B2 =>
mask16(1), C1 => n44, C2 => mask08(1), ZN => n71);
U15 : AOI222_X1 port map( A1 => n84, A2 => mask00(3), B1 => n43, B2 =>
mask16(3), C1 => n92, C2 => mask08(3), ZN => n50);
U29 : AOI222_X1 port map( A1 => n84, A2 => mask00(32), B1 => n43, B2 =>
mask16(32), C1 => n92, C2 => mask08(32), ZN => n57);
U25 : AOI222_X1 port map( A1 => n84, A2 => mask00(34), B1 => n43, B2 =>
mask16(34), C1 => n92, C2 => mask08(34), ZN => n55);
U21 : AOI222_X1 port map( A1 => n84, A2 => mask00(36), B1 => n43, B2 =>
mask16(36), C1 => n92, C2 => mask08(36), ZN => n53);
U17 : AOI222_X1 port map( A1 => n84, A2 => mask00(38), B1 => n43, B2 =>
mask16(38), C1 => n92, C2 => mask08(38), ZN => n51);
U23 : AOI222_X1 port map( A1 => n84, A2 => mask00(35), B1 => n43, B2 =>
mask16(35), C1 => n92, C2 => mask08(35), ZN => n54);
U31 : AOI222_X1 port map( A1 => n84, A2 => mask00(31), B1 => n43, B2 =>
mask16(31), C1 => n92, C2 => mask08(31), ZN => n58);
U27 : AOI222_X1 port map( A1 => n84, A2 => mask00(33), B1 => n43, B2 =>
mask16(33), C1 => n92, C2 => mask08(33), ZN => n56);
U19 : AOI222_X1 port map( A1 => n84, A2 => mask00(37), B1 => n43, B2 =>
mask16(37), C1 => n92, C2 => mask08(37), ZN => n52);
U49 : AOI222_X1 port map( A1 => n84, A2 => mask00(23), B1 => n43, B2 =>
mask16(23), C1 => n44, C2 => mask08(23), ZN => n67);
U45 : AOI222_X1 port map( A1 => n84, A2 => mask00(25), B1 => n43, B2 =>
mask16(25), C1 => n92, C2 => mask08(25), ZN => n65);
U59 : AOI222_X1 port map( A1 => n84, A2 => mask00(19), B1 => n43, B2 =>
mask16(19), C1 => n44, C2 => mask08(19), ZN => n72);
U53 : AOI222_X1 port map( A1 => n84, A2 => mask00(21), B1 => n43, B2 =>
mask16(21), C1 => n44, C2 => mask08(21), ZN => n69);
U43 : AOI222_X1 port map( A1 => n84, A2 => mask00(26), B1 => n43, B2 =>
mask16(26), C1 => n92, C2 => mask08(26), ZN => n64);
U47 : AOI222_X1 port map( A1 => n84, A2 => mask00(24), B1 => n43, B2 =>
mask16(24), C1 => n92, C2 => mask08(24), ZN => n66);
U55 : AOI222_X1 port map( A1 => n84, A2 => mask00(20), B1 => n43, B2 =>
mask16(20), C1 => n44, C2 => mask08(20), ZN => n70);
U51 : AOI222_X1 port map( A1 => n84, A2 => mask00(22), B1 => n43, B2 =>
mask16(22), C1 => n92, C2 => mask08(22), ZN => n68);
U41 : AOI222_X1 port map( A1 => n84, A2 => mask00(27), B1 => n43, B2 =>
mask16(27), C1 => n92, C2 => mask08(27), ZN => n63);
U39 : AOI222_X1 port map( A1 => n84, A2 => mask00(28), B1 => n43, B2 =>
mask16(28), C1 => n92, C2 => mask08(28), ZN => n62);
U3 : AOI222_X1 port map( A1 => n84, A2 => mask00(9), B1 => n43, B2 =>
mask16(9), C1 => n92, C2 => mask08(9), ZN => n41);
U77 : AOI222_X1 port map( A1 => n84, A2 => mask00(10), B1 => n43, B2 =>
mask16(10), C1 => n44, C2 => mask08(10), ZN => n81);
U5 : AOI222_X1 port map( A1 => n84, A2 => mask00(8), B1 => n43, B2 =>
mask16(8), C1 => n92, C2 => mask08(8), ZN => n45);
U37 : AOI222_X1 port map( A1 => n84, A2 => mask00(29), B1 => n43, B2 =>
mask16(29), C1 => n92, C2 => mask08(29), ZN => n61);
U33 : AOI222_X1 port map( A1 => n84, A2 => mask00(30), B1 => n43, B2 =>
mask16(30), C1 => n44, C2 => mask08(30), ZN => n59);
U63 : AOI222_X1 port map( A1 => n84, A2 => mask00(17), B1 => n43, B2 =>
mask16(17), C1 => n44, C2 => mask08(17), ZN => n74);
U67 : AOI222_X1 port map( A1 => n84, A2 => mask00(15), B1 => n43, B2 =>
mask16(15), C1 => n92, C2 => mask08(15), ZN => n76);
U65 : AOI222_X1 port map( A1 => n84, A2 => mask00(16), B1 => n43, B2 =>
mask16(16), C1 => n44, C2 => mask08(16), ZN => n75);
U61 : AOI222_X1 port map( A1 => n84, A2 => mask00(18), B1 => n43, B2 =>
mask16(18), C1 => n92, C2 => mask08(18), ZN => n73);
U73 : AOI222_X1 port map( A1 => n84, A2 => mask00(12), B1 => n43, B2 =>
mask16(12), C1 => n44, C2 => mask08(12), ZN => n79);
U69 : AOI222_X1 port map( A1 => n84, A2 => mask00(14), B1 => n43, B2 =>
mask16(14), C1 => n44, C2 => mask08(14), ZN => n77);
U71 : AOI222_X1 port map( A1 => n84, A2 => mask00(13), B1 => n43, B2 =>
mask16(13), C1 => n44, C2 => mask08(13), ZN => n78);
U75 : AOI222_X1 port map( A1 => n84, A2 => mask00(11), B1 => n43, B2 =>
mask16(11), C1 => n44, C2 => mask08(11), ZN => n80);
U78 : INV_X1 port map( A => n82, ZN => Y(0));
U34 : INV_X1 port map( A => n60, ZN => Y(2));
U12 : INV_X1 port map( A => n49, ZN => Y(4));
U8 : INV_X1 port map( A => n47, ZN => Y(6));
U10 : INV_X1 port map( A => n48, ZN => Y(5));
U56 : INV_X1 port map( A => n71, ZN => Y(1));
U14 : INV_X1 port map( A => n50, ZN => Y(3));
U28 : INV_X1 port map( A => n57, ZN => Y(32));
U24 : INV_X1 port map( A => n55, ZN => Y(34));
U20 : INV_X1 port map( A => n53, ZN => Y(36));
U16 : INV_X1 port map( A => n51, ZN => Y(38));
U22 : INV_X1 port map( A => n54, ZN => Y(35));
U30 : INV_X1 port map( A => n58, ZN => Y(31));
U26 : INV_X1 port map( A => n56, ZN => Y(33));
U18 : INV_X1 port map( A => n52, ZN => Y(37));
U48 : INV_X1 port map( A => n67, ZN => Y(23));
U44 : INV_X1 port map( A => n65, ZN => Y(25));
U58 : INV_X1 port map( A => n72, ZN => Y(19));
U52 : INV_X1 port map( A => n69, ZN => Y(21));
U42 : INV_X1 port map( A => n64, ZN => Y(26));
U46 : INV_X1 port map( A => n66, ZN => Y(24));
U54 : INV_X1 port map( A => n70, ZN => Y(20));
U50 : INV_X1 port map( A => n68, ZN => Y(22));
U40 : INV_X1 port map( A => n63, ZN => Y(27));
U38 : INV_X1 port map( A => n62, ZN => Y(28));
U2 : INV_X1 port map( A => n41, ZN => Y(9));
U76 : INV_X1 port map( A => n81, ZN => Y(10));
U4 : INV_X1 port map( A => n45, ZN => Y(8));
U36 : INV_X1 port map( A => n61, ZN => Y(29));
U32 : INV_X1 port map( A => n59, ZN => Y(30));
U62 : INV_X1 port map( A => n74, ZN => Y(17));
U66 : INV_X1 port map( A => n76, ZN => Y(15));
U64 : INV_X1 port map( A => n75, ZN => Y(16));
U60 : INV_X1 port map( A => n73, ZN => Y(18));
U72 : INV_X1 port map( A => n79, ZN => Y(12));
U68 : INV_X1 port map( A => n77, ZN => Y(14));
U70 : INV_X1 port map( A => n78, ZN => Y(13));
U74 : INV_X1 port map( A => n80, ZN => Y(11));
U6 : AOI222_X1 port map( A1 => n92, A2 => mask08(7), B1 => mask00(7), B2 =>
n84, C1 => mask16(7), C2 => n43, ZN => n46);
U7 : INV_X1 port map( A => n46, ZN => Y(7));
U80 : BUF_X2 port map( A => n42, Z => n84);
U81 : BUF_X1 port map( A => n44, Z => n92);
U82 : AND2_X2 port map( A1 => n83, A2 => sel(1), ZN => n43);
U83 : NOR2_X2 port map( A1 => sel(1), A2 => n83, ZN => n44);
U84 : INV_X1 port map( A => sel(0), ZN => n83);
U85 : NOR2_X1 port map( A1 => sel(1), A2 => sel(0), ZN => n42);
end SYN_behav;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity shift_firstLevel is
port( A : in std_logic_vector (31 downto 0); sel : in std_logic_vector (1
downto 0); mask00, mask08, mask16 : out std_logic_vector (38 downto
0));
end shift_firstLevel;
architecture SYN_behav of shift_firstLevel is
component NOR2_X2
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component BUF_X1
port( A : in std_logic; Z : out std_logic);
end component;
component INV_X2
port( A : in std_logic; ZN : out std_logic);
end component;
component AND2_X2
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
signal mask08_38_port, mask08_37_port, mask08_36_port, mask08_35_port,
mask08_34_port, mask08_33_port, mask08_32_port, mask08_31_port,
mask08_23_port, mask08_22_port, mask08_21_port, mask08_20_port,
mask08_19_port, mask08_18_port, mask08_17_port, mask08_16_port,
mask08_15_port, mask08_7_port, mask08_6_port, mask08_5_port,
mask08_4_port, mask08_3_port, mask08_2_port, mask08_1_port, mask08_0_port
, mask16_38_port, mask16_37_port, mask16_36_port, mask16_35_port,
mask16_34_port, mask16_33_port, mask16_32_port, mask16_31_port,
mask16_30_port, mask16_29_port, mask16_28_port, mask16_27_port,
mask16_26_port, mask16_25_port, mask16_24_port, mask16_23_port,
mask16_15_port, mask16_14_port, mask16_13_port, mask16_12_port,
mask16_11_port, mask16_10_port, mask16_9_port, mask16_8_port,
mask16_7_port, mask16_6_port, mask16_5_port, mask16_4_port, mask16_3_port
, mask16_2_port, mask16_1_port, mask16_0_port, n36, n37, n38, n39, n40,
n41, n42, n43, mask16_18_port, n45, n46, n47, n48, n49, n50, n51, n52,
n53, n54, n55, n56, n57, n58, n59, n60, n61, n62, n63, n64, n65, n66, n67
, n68, n69, n70, n71, n72, n73, n74, n75, n76, n77, n78, n79, n80, n81,
n82, n83, n84, n85, n88, n89, n90, n91, n92, n93, n94, n95, n86, n87, n96
: std_logic;
begin
mask08 <= ( mask08_38_port, mask08_37_port, mask08_36_port, mask08_35_port,
mask08_34_port, mask08_33_port, mask08_32_port, mask08_31_port,
mask16_38_port, mask16_37_port, mask16_36_port, mask16_35_port,
mask16_34_port, mask16_33_port, mask16_32_port, mask08_23_port,
mask08_22_port, mask08_21_port, mask08_20_port, mask08_19_port,
mask08_18_port, mask08_17_port, mask08_16_port, mask08_15_port,
mask16_6_port, mask16_5_port, mask16_4_port, mask16_3_port, mask16_2_port
, mask16_1_port, mask16_0_port, mask08_7_port, mask08_6_port,
mask08_5_port, mask08_4_port, mask08_3_port, mask08_2_port, mask08_1_port
, mask08_0_port );
mask16 <= ( mask16_38_port, mask16_37_port, mask16_36_port, mask16_35_port,
mask16_34_port, mask16_33_port, mask16_32_port, mask16_31_port,
mask16_30_port, mask16_29_port, mask16_28_port, mask16_27_port,
mask16_26_port, mask16_25_port, mask16_24_port, mask16_23_port,
mask16_18_port, mask16_18_port, mask16_18_port, mask16_18_port,
mask16_18_port, mask16_18_port, mask16_18_port, mask16_15_port,
mask16_14_port, mask16_13_port, mask16_12_port, mask16_11_port,
mask16_10_port, mask16_9_port, mask16_8_port, mask16_7_port,
mask16_6_port, mask16_5_port, mask16_4_port, mask16_3_port, mask16_2_port
, mask16_1_port, mask16_0_port );
U137 : NAND2_X1 port map( A1 => sel(0), A2 => A(16), ZN => n67);
U62 : NAND2_X1 port map( A1 => sel(0), A2 => A(8), ZN => n84);
U131 : NAND2_X1 port map( A1 => sel(0), A2 => A(18), ZN => n53);
U155 : NAND2_X1 port map( A1 => sel(0), A2 => A(10), ZN => n81);
U125 : NAND2_X1 port map( A1 => sel(0), A2 => A(20), ZN => n41);
U149 : NAND2_X1 port map( A1 => sel(0), A2 => A(12), ZN => n71);
U119 : NAND2_X1 port map( A1 => sel(0), A2 => A(22), ZN => n39);
U143 : NAND2_X1 port map( A1 => sel(0), A2 => A(14), ZN => n69);
U122 : NAND2_X1 port map( A1 => sel(0), A2 => A(21), ZN => n40);
U146 : NAND2_X1 port map( A1 => sel(0), A2 => A(13), ZN => n70);
U67 : NAND2_X1 port map( A1 => n87, A2 => A(0), ZN => n60);
U116 : NAND2_X1 port map( A1 => sel(0), A2 => A(23), ZN => n38);
U140 : NAND2_X1 port map( A1 => sel(0), A2 => A(15), ZN => n68);
U134 : NAND2_X1 port map( A1 => sel(0), A2 => A(17), ZN => n61);
U59 : NAND2_X1 port map( A1 => sel(0), A2 => A(9), ZN => n83);
U129 : NAND2_X1 port map( A1 => sel(0), A2 => A(19), ZN => n42);
U152 : NAND2_X1 port map( A1 => sel(0), A2 => A(11), ZN => n72);
U91 : NAND2_X1 port map( A1 => sel(0), A2 => A(31), ZN => n82);
U85 : AOI21_X1 port map( B1 => A(25), B2 => n85, A => mask16_18_port, ZN =>
n94);
U138 : NAND2_X1 port map( A1 => n85, A2 => A(9), ZN => n50);
U15 : NAND2_X1 port map( A1 => n50, A2 => n96, ZN => mask16_32_port);
U112 : NAND2_X1 port map( A1 => n87, A2 => A(17), ZN => n79);
U44 : NAND2_X1 port map( A1 => n79, A2 => n96, ZN => mask08_32_port);
U81 : AOI21_X1 port map( B1 => A(27), B2 => n85, A => mask16_18_port, ZN =>
n92);
U132 : NAND2_X1 port map( A1 => n87, A2 => A(11), ZN => n48);
U13 : NAND2_X1 port map( A1 => n48, A2 => n96, ZN => mask16_34_port);
U106 : NAND2_X1 port map( A1 => n87, A2 => A(19), ZN => n77);
U42 : NAND2_X1 port map( A1 => n77, A2 => n96, ZN => mask08_34_port);
U77 : AOI21_X1 port map( B1 => A(29), B2 => n85, A => mask16_18_port, ZN =>
n90);
U124 : NAND2_X1 port map( A1 => n87, A2 => A(13), ZN => n46);
U11 : NAND2_X1 port map( A1 => n46, A2 => n96, ZN => mask16_36_port);
U100 : NAND2_X1 port map( A1 => n87, A2 => A(21), ZN => n75);
U40 : NAND2_X1 port map( A1 => n75, A2 => n96, ZN => mask08_36_port);
U73 : AOI21_X1 port map( B1 => A(31), B2 => n85, A => mask16_18_port, ZN =>
n88);
U118 : NAND2_X1 port map( A1 => n87, A2 => A(15), ZN => n43);
U9 : NAND2_X1 port map( A1 => n43, A2 => n96, ZN => mask16_38_port);
U93 : NAND2_X1 port map( A1 => n85, A2 => A(23), ZN => n73);
U38 : NAND2_X1 port map( A1 => n73, A2 => n96, ZN => mask08_38_port);
U79 : AOI21_X1 port map( B1 => A(28), B2 => n85, A => mask16_18_port, ZN =>
n91);
U128 : NAND2_X1 port map( A1 => n87, A2 => A(12), ZN => n47);
U12 : NAND2_X1 port map( A1 => n47, A2 => n96, ZN => mask16_35_port);
U103 : NAND2_X1 port map( A1 => n87, A2 => A(20), ZN => n76);
U41 : NAND2_X1 port map( A1 => n76, A2 => n96, ZN => mask08_35_port);
U89 : AOI21_X1 port map( B1 => A(24), B2 => n85, A => mask16_15_port, ZN =>
n95);
U141 : NAND2_X1 port map( A1 => n87, A2 => A(8), ZN => n51);
U16 : NAND2_X1 port map( A1 => n51, A2 => n96, ZN => mask16_31_port);
U115 : NAND2_X1 port map( A1 => n87, A2 => A(16), ZN => n80);
U45 : NAND2_X1 port map( A1 => n80, A2 => n96, ZN => mask08_31_port);
U83 : AOI21_X1 port map( B1 => A(26), B2 => n85, A => mask16_18_port, ZN =>
n93);
U135 : NAND2_X1 port map( A1 => n85, A2 => A(10), ZN => n49);
U14 : NAND2_X1 port map( A1 => n49, A2 => n96, ZN => mask16_33_port);
U109 : NAND2_X1 port map( A1 => n87, A2 => A(18), ZN => n78);
U43 : NAND2_X1 port map( A1 => n78, A2 => n96, ZN => mask08_33_port);
U75 : AOI21_X1 port map( B1 => A(30), B2 => n85, A => mask16_18_port, ZN =>
n89);
U121 : NAND2_X1 port map( A1 => n87, A2 => A(14), ZN => n45);
U10 : NAND2_X1 port map( A1 => n45, A2 => n96, ZN => mask16_37_port);
U97 : NAND2_X1 port map( A1 => n87, A2 => A(22), ZN => n74);
U39 : NAND2_X1 port map( A1 => n74, A2 => n96, ZN => mask08_37_port);
U114 : NAND2_X1 port map( A1 => n38, A2 => n80, ZN => mask00(23));
U25 : NAND2_X1 port map( A1 => n96, A2 => n60, ZN => mask16_23_port);
U47 : NAND2_X1 port map( A1 => n51, A2 => n82, ZN => mask08_23_port);
U110 : NAND2_X1 port map( A1 => sel(0), A2 => A(25), ZN => n36);
U108 : NAND2_X1 port map( A1 => n36, A2 => n78, ZN => mask00(25));
U60 : NAND2_X1 port map( A1 => n85, A2 => A(2), ZN => n58);
U23 : NAND2_X1 port map( A1 => n96, A2 => n58, ZN => mask16_25_port);
U127 : NAND2_X1 port map( A1 => n42, A2 => n47, ZN => mask00(19));
U153 : NAND2_X1 port map( A1 => n85, A2 => A(4), ZN => n56);
U104 : NAND2_X1 port map( A1 => sel(0), A2 => A(27), ZN => n65);
U52 : NAND2_X1 port map( A1 => n56, A2 => n65, ZN => mask08_19_port);
U120 : NAND2_X1 port map( A1 => n40, A2 => n45, ZN => mask00(21));
U147 : NAND2_X1 port map( A1 => n85, A2 => A(6), ZN => n54);
U98 : NAND2_X1 port map( A1 => sel(0), A2 => A(29), ZN => n63);
U49 : NAND2_X1 port map( A1 => n54, A2 => n63, ZN => mask08_21_port);
U107 : NAND2_X1 port map( A1 => sel(0), A2 => A(26), ZN => n66);
U105 : NAND2_X1 port map( A1 => n66, A2 => n77, ZN => mask00(26));
U156 : NAND2_X1 port map( A1 => n87, A2 => A(3), ZN => n57);
U22 : NAND2_X1 port map( A1 => n57, A2 => n96, ZN => mask16_26_port);
U113 : NAND2_X1 port map( A1 => sel(0), A2 => A(24), ZN => n37);
U111 : NAND2_X1 port map( A1 => n37, A2 => n79, ZN => mask00(24));
U63 : NAND2_X1 port map( A1 => n85, A2 => A(1), ZN => n59);
U24 : NAND2_X1 port map( A1 => n96, A2 => n59, ZN => mask16_24_port);
U123 : NAND2_X1 port map( A1 => n41, A2 => n46, ZN => mask00(20));
U150 : NAND2_X1 port map( A1 => n85, A2 => A(5), ZN => n55);
U101 : NAND2_X1 port map( A1 => sel(0), A2 => A(28), ZN => n64);
U50 : NAND2_X1 port map( A1 => n55, A2 => n64, ZN => mask08_20_port);
U117 : NAND2_X1 port map( A1 => n39, A2 => n43, ZN => mask00(22));
U144 : NAND2_X1 port map( A1 => n85, A2 => A(7), ZN => n52);
U94 : NAND2_X1 port map( A1 => sel(0), A2 => A(30), ZN => n62);
U48 : NAND2_X1 port map( A1 => n52, A2 => n62, ZN => mask08_22_port);
U102 : NAND2_X1 port map( A1 => n65, A2 => n76, ZN => mask00(27));
U21 : NAND2_X1 port map( A1 => n56, A2 => n96, ZN => mask16_27_port);
U99 : NAND2_X1 port map( A1 => n64, A2 => n75, ZN => mask00(28));
U20 : NAND2_X1 port map( A1 => n55, A2 => n96, ZN => mask16_28_port);
U58 : NAND2_X1 port map( A1 => n58, A2 => n83, ZN => mask00(9));
U154 : NAND2_X1 port map( A1 => n57, A2 => n81, ZN => mask00(10));
U61 : NAND2_X1 port map( A1 => n59, A2 => n84, ZN => mask00(8));
U96 : NAND2_X1 port map( A1 => n63, A2 => n74, ZN => mask00(29));
U19 : NAND2_X1 port map( A1 => n54, A2 => n96, ZN => mask16_29_port);
U92 : NAND2_X1 port map( A1 => n62, A2 => n73, ZN => mask00(30));
U17 : NAND2_X1 port map( A1 => n52, A2 => n96, ZN => mask16_30_port);
U133 : NAND2_X1 port map( A1 => n49, A2 => n61, ZN => mask00(17));
U54 : NAND2_X1 port map( A1 => n36, A2 => n58, ZN => mask08_17_port);
U139 : NAND2_X1 port map( A1 => n51, A2 => n68, ZN => mask00(15));
U56 : NAND2_X1 port map( A1 => n38, A2 => n60, ZN => mask08_15_port);
U136 : NAND2_X1 port map( A1 => n50, A2 => n67, ZN => mask00(16));
U55 : NAND2_X1 port map( A1 => n37, A2 => n59, ZN => mask08_16_port);
U130 : NAND2_X1 port map( A1 => n48, A2 => n53, ZN => mask00(18));
U53 : NAND2_X1 port map( A1 => n57, A2 => n66, ZN => mask08_18_port);
U148 : NAND2_X1 port map( A1 => n55, A2 => n71, ZN => mask00(12));
U142 : NAND2_X1 port map( A1 => n52, A2 => n69, ZN => mask00(14));
U145 : NAND2_X1 port map( A1 => n54, A2 => n70, ZN => mask00(13));
U151 : NAND2_X1 port map( A1 => n56, A2 => n72, ZN => mask00(11));
U158 : AND2_X1 port map( A1 => sel(0), A2 => A(0), ZN => mask00(0));
U32 : INV_X1 port map( A => n67, ZN => mask16_0_port);
U57 : INV_X1 port map( A => n84, ZN => mask08_0_port);
U95 : AND2_X1 port map( A1 => sel(0), A2 => A(2), ZN => mask00(2));
U18 : INV_X1 port map( A => n53, ZN => mask16_2_port);
U46 : INV_X1 port map( A => n81, ZN => mask08_2_port);
U70 : AND2_X1 port map( A1 => sel(0), A2 => A(4), ZN => mask00(4));
U7 : INV_X1 port map( A => n41, ZN => mask16_4_port);
U36 : INV_X1 port map( A => n71, ZN => mask08_4_port);
U68 : AND2_X1 port map( A1 => sel(0), A2 => A(6), ZN => mask00(6));
U5 : INV_X1 port map( A => n39, ZN => mask16_6_port);
U34 : INV_X1 port map( A => n69, ZN => mask08_6_port);
U69 : AND2_X1 port map( A1 => sel(0), A2 => A(5), ZN => mask00(5));
U6 : INV_X1 port map( A => n40, ZN => mask16_5_port);
U35 : INV_X1 port map( A => n70, ZN => mask08_5_port);
U126 : AND2_X1 port map( A1 => sel(0), A2 => A(1), ZN => mask00(1));
U26 : INV_X1 port map( A => n61, ZN => mask16_1_port);
U51 : INV_X1 port map( A => n83, ZN => mask08_1_port);
U71 : AND2_X1 port map( A1 => sel(0), A2 => A(3), ZN => mask00(3));
U8 : INV_X1 port map( A => n42, ZN => mask16_3_port);
U37 : INV_X1 port map( A => n72, ZN => mask08_3_port);
U90 : INV_X1 port map( A => n82, ZN => mask16_15_port);
U84 : INV_X1 port map( A => n94, ZN => mask00(32));
U80 : INV_X1 port map( A => n92, ZN => mask00(34));
U76 : INV_X1 port map( A => n90, ZN => mask00(36));
U72 : INV_X1 port map( A => n88, ZN => mask00(38));
U78 : INV_X1 port map( A => n91, ZN => mask00(35));
U88 : INV_X1 port map( A => n95, ZN => mask00(31));
U82 : INV_X1 port map( A => n93, ZN => mask00(33));
U74 : INV_X1 port map( A => n89, ZN => mask00(37));
U2 : INV_X1 port map( A => n36, ZN => mask16_9_port);
U31 : INV_X1 port map( A => n66, ZN => mask16_10_port);
U3 : INV_X1 port map( A => n37, ZN => mask16_8_port);
U29 : INV_X1 port map( A => n64, ZN => mask16_12_port);
U27 : INV_X1 port map( A => n62, ZN => mask16_14_port);
U28 : INV_X1 port map( A => n63, ZN => mask16_13_port);
U30 : INV_X1 port map( A => n65, ZN => mask16_11_port);
U4 : INV_X1 port map( A => n68, ZN => mask08_7_port);
U33 : INV_X1 port map( A => n38, ZN => mask16_7_port);
U64 : NAND2_X1 port map( A1 => sel(0), A2 => A(7), ZN => n86);
U65 : NAND2_X1 port map( A1 => n60, A2 => n86, ZN => mask00(7));
U66 : AND2_X2 port map( A1 => sel(1), A2 => mask16_15_port, ZN =>
mask16_18_port);
U86 : INV_X2 port map( A => mask16_18_port, ZN => n96);
U87 : BUF_X1 port map( A => n85, Z => n87);
U157 : NOR2_X2 port map( A1 => sel(0), A2 => sel(1), ZN => n85);
end SYN_behav;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity sum_gen_N32 is
port( A, B : in std_logic_vector (31 downto 0); Cin : in std_logic_vector
(8 downto 0); S : out std_logic_vector (31 downto 0));
end sum_gen_N32;
architecture SYN_STRUCTURAL of sum_gen_N32 is
component carry_sel_gen_N4_1
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
component carry_sel_gen_N4_2
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
component carry_sel_gen_N4_3
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
component carry_sel_gen_N4_4
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
component carry_sel_gen_N4_5
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
component carry_sel_gen_N4_6
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
component carry_sel_gen_N4_7
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
component carry_sel_gen_N4_0
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
signal net539424, net539425, net539426, net539427, net539428, net539429,
net539430, net539431 : std_logic;
begin
csel_N_0 : carry_sel_gen_N4_0 port map( A(3) => A(3), A(2) => A(2), A(1) =>
A(1), A(0) => A(0), B(3) => B(3), B(2) => B(2), B(1)
=> B(1), B(0) => B(0), Ci => Cin(0), S(3) => S(3),
S(2) => S(2), S(1) => S(1), S(0) => S(0), Co =>
net539431);
csel_N_1 : carry_sel_gen_N4_7 port map( A(3) => A(7), A(2) => A(6), A(1) =>
A(5), A(0) => A(4), B(3) => B(7), B(2) => B(6), B(1)
=> B(5), B(0) => B(4), Ci => Cin(1), S(3) => S(7),
S(2) => S(6), S(1) => S(5), S(0) => S(4), Co =>
net539430);
csel_N_2 : carry_sel_gen_N4_6 port map( A(3) => A(11), A(2) => A(10), A(1)
=> A(9), A(0) => A(8), B(3) => B(11), B(2) => B(10),
B(1) => B(9), B(0) => B(8), Ci => Cin(2), S(3) =>
S(11), S(2) => S(10), S(1) => S(9), S(0) => S(8), Co
=> net539429);
csel_N_3 : carry_sel_gen_N4_5 port map( A(3) => A(15), A(2) => A(14), A(1)
=> A(13), A(0) => A(12), B(3) => B(15), B(2) =>
B(14), B(1) => B(13), B(0) => B(12), Ci => Cin(3),
S(3) => S(15), S(2) => S(14), S(1) => S(13), S(0) =>
S(12), Co => net539428);
csel_N_4 : carry_sel_gen_N4_4 port map( A(3) => A(19), A(2) => A(18), A(1)
=> A(17), A(0) => A(16), B(3) => B(19), B(2) =>
B(18), B(1) => B(17), B(0) => B(16), Ci => Cin(4),
S(3) => S(19), S(2) => S(18), S(1) => S(17), S(0) =>
S(16), Co => net539427);
csel_N_5 : carry_sel_gen_N4_3 port map( A(3) => A(23), A(2) => A(22), A(1)
=> A(21), A(0) => A(20), B(3) => B(23), B(2) =>
B(22), B(1) => B(21), B(0) => B(20), Ci => Cin(5),
S(3) => S(23), S(2) => S(22), S(1) => S(21), S(0) =>
S(20), Co => net539426);
csel_N_6 : carry_sel_gen_N4_2 port map( A(3) => A(27), A(2) => A(26), A(1)
=> A(25), A(0) => A(24), B(3) => B(27), B(2) =>
B(26), B(1) => B(25), B(0) => B(24), Ci => Cin(6),
S(3) => S(27), S(2) => S(26), S(1) => S(25), S(0) =>
S(24), Co => net539425);
csel_N_7 : carry_sel_gen_N4_1 port map( A(3) => A(31), A(2) => A(30), A(1)
=> A(29), A(0) => A(28), B(3) => B(31), B(2) =>
B(30), B(1) => B(29), B(0) => B(28), Ci => Cin(7),
S(3) => S(31), S(2) => S(30), S(1) => S(29), S(0) =>
S(28), Co => net539424);
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity carry_tree_N32_logN5 is
port( A, B : in std_logic_vector (31 downto 0); Cin : in std_logic; Cout :
out std_logic_vector (7 downto 0));
end carry_tree_N32_logN5;
architecture SYN_arch of carry_tree_N32_logN5 is
component CLKBUF_X1
port( A : in std_logic; Z : out std_logic);
end component;
component BUF_X1
port( A : in std_logic; Z : out std_logic);
end component;
component pg_1
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic
);
end component;
component pg_2
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic
);
end component;
component pg_3
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic
);
end component;
component pg_4
port( p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic;
g_BAR : in std_logic);
end component;
component pg_5
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic
);
end component;
component g_1
port( g, p, g_prec : in std_logic; g_out : out std_logic);
end component;
component g_2
port( g, p, g_prec : in std_logic; g_out : out std_logic);
end component;
component g_3
port( g, p, g_prec : in std_logic; g_out : out std_logic);
end component;
component g_4
port( g, p, g_prec : in std_logic; g_out : out std_logic);
end component;
component g_5
port( g, p, g_prec : in std_logic; g_out : out std_logic);
end component;
component g_6
port( g, p, g_prec : in std_logic; g_out : out std_logic);
end component;
component g_7
port( g, p, g_prec : in std_logic; g_out : out std_logic);
end component;
component pg_6
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic
);
end component;
component pg_7
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic
);
end component;
component pg_8
port( g, p, g_prec, p_prec : in std_logic; p_out, g_out_BAR : out
std_logic);
end component;
component pg_9
port( p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic;
g_BAR : in std_logic);
end component;
component pg_10
port( p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic;
g_BAR : in std_logic);
end component;
component pg_11
port( p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic;
g_BAR : in std_logic);
end component;
component pg_12
port( p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic;
g_BAR : in std_logic);
end component;
component g_8
port( g, p, g_prec : in std_logic; g_out : out std_logic);
end component;
component pg_13
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic
);
end component;
component pg_14
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic
);
end component;
component pg_15
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic
);
end component;
component pg_16
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic
);
end component;
component pg_17
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic
);
end component;
component pg_18
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic
);
end component;
component pg_19
port( g, p, g_prec, p_prec : in std_logic; p_out, g_out_BAR : out
std_logic);
end component;
component pg_20
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic
);
end component;
component pg_21
port( g, p, g_prec, p_prec : in std_logic; p_out, g_out_BAR : out
std_logic);
end component;
component pg_22
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic
);
end component;
component pg_23
port( g, p, g_prec, p_prec : in std_logic; p_out, g_out_BAR : out
std_logic);
end component;
component pg_24
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic
);
end component;
component pg_25
port( g, p, g_prec, p_prec : in std_logic; p_out, g_out_BAR : out
std_logic);
end component;
component pg_26
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic
);
end component;
component pg_0
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic
);
end component;
component g_9
port( g, p, g_prec : in std_logic; g_out : out std_logic);
end component;
component g_0
port( g, p, g_prec : in std_logic; g_out : out std_logic);
end component;
component pg_net_1
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_2
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_3
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_4
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_5
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_6
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_7
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_8
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_9
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_10
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_11
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_12
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_13
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_14
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_15
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_16
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_17
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_18
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_19
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_20
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_21
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_22
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_23
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_24
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_25
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_26
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_27
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_28
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_29
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_30
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_31
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_0
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
signal Cout_7_port, Cout_6_port, Cout_5_port, Cout_4_port, n9, Cout_2_port,
n10, n11, p_net_31_port, p_net_30_port, p_net_29_port, p_net_28_port,
p_net_27_port, p_net_26_port, p_net_25_port, p_net_24_port, p_net_23_port
, p_net_22_port, p_net_21_port, p_net_20_port, p_net_19_port,
p_net_18_port, p_net_17_port, p_net_16_port, p_net_15_port, p_net_14_port
, p_net_13_port, p_net_12_port, p_net_11_port, p_net_10_port,
p_net_9_port, p_net_8_port, p_net_7_port, p_net_6_port, p_net_5_port,
p_net_4_port, p_net_3_port, p_net_2_port, p_net_1_port, g_net_31_port,
g_net_30_port, g_net_29_port, g_net_28_port, g_net_27_port, g_net_26_port
, g_net_25_port, g_net_24_port, g_net_23_port, g_net_22_port,
g_net_21_port, g_net_20_port, g_net_19_port, g_net_18_port, g_net_17_port
, g_net_16_port, g_net_15_port, g_net_14_port, g_net_13_port,
g_net_12_port, g_net_11_port, g_net_10_port, g_net_9_port, g_net_8_port,
g_net_7_port, g_net_6_port, g_net_5_port, g_net_4_port, g_net_3_port,
g_net_2_port, g_net_1_port, g_net_0_port, magic_pro_1_port,
magic_pro_0_port, pg_1_15_1_port, pg_1_15_0_port, pg_1_14_1_port,
pg_1_14_0_port, pg_1_13_1_port, pg_1_13_0_port, pg_1_12_1_port,
pg_1_12_0_port, pg_1_11_1_port, pg_1_11_0_port, pg_1_10_1_port,
pg_1_10_0_port, pg_1_9_1_port, pg_1_9_0_port, pg_1_8_1_port,
pg_1_8_0_port, pg_1_7_1_port, pg_1_7_0_port, pg_1_6_1_port, pg_1_6_0_port
, pg_1_5_1_port, pg_1_5_0_port, pg_1_4_1_port, pg_1_4_0_port,
pg_1_3_1_port, pg_1_3_0_port, pg_1_2_1_port, pg_1_2_0_port, pg_1_1_1_port
, pg_1_1_0_port, pg_1_0_0_port, pg_n_4_7_1_port, pg_n_4_7_0_port,
pg_n_4_6_1_port, pg_n_4_6_0_port, pg_n_3_7_1_port, pg_n_3_7_0_port,
pg_n_3_5_1_port, pg_n_3_5_0_port, pg_n_3_3_1_port, pg_n_3_3_0_port,
pg_n_2_7_1_port, pg_n_2_7_0_port, pg_n_2_6_1_port, pg_n_2_6_0_port,
pg_n_2_5_1_port, pg_n_2_5_0_port, pg_n_2_4_1_port, pg_n_2_4_0_port,
pg_n_2_3_1_port, pg_n_2_3_0_port, pg_n_2_2_1_port, pg_n_2_2_0_port,
pg_n_2_1_1_port, pg_n_2_1_0_port, n1, Cout_3_port, Cout_1_port, n5,
Cout_0_port, n7, n8 : std_logic;
begin
Cout <= ( Cout_7_port, Cout_6_port, Cout_5_port, Cout_4_port, Cout_3_port,
Cout_2_port, Cout_1_port, Cout_0_port );
pg_net_x_1 : pg_net_0 port map( a => A(1), b => B(1), g_out => g_net_1_port,
p_out => p_net_1_port);
pg_net_x_2 : pg_net_31 port map( a => A(2), b => B(2), g_out => g_net_2_port
, p_out => p_net_2_port);
pg_net_x_3 : pg_net_30 port map( a => A(3), b => B(3), g_out => g_net_3_port
, p_out => p_net_3_port);
pg_net_x_4 : pg_net_29 port map( a => A(4), b => B(4), g_out => g_net_4_port
, p_out => p_net_4_port);
pg_net_x_5 : pg_net_28 port map( a => A(5), b => B(5), g_out => g_net_5_port
, p_out => p_net_5_port);
pg_net_x_6 : pg_net_27 port map( a => A(6), b => B(6), g_out => g_net_6_port
, p_out => p_net_6_port);
pg_net_x_7 : pg_net_26 port map( a => A(7), b => B(7), g_out => g_net_7_port
, p_out => p_net_7_port);
pg_net_x_8 : pg_net_25 port map( a => A(8), b => B(8), g_out => g_net_8_port
, p_out => p_net_8_port);
pg_net_x_9 : pg_net_24 port map( a => A(9), b => B(9), g_out => g_net_9_port
, p_out => p_net_9_port);
pg_net_x_10 : pg_net_23 port map( a => A(10), b => B(10), g_out =>
g_net_10_port, p_out => p_net_10_port);
pg_net_x_11 : pg_net_22 port map( a => A(11), b => B(11), g_out =>
g_net_11_port, p_out => p_net_11_port);
pg_net_x_12 : pg_net_21 port map( a => A(12), b => B(12), g_out =>
g_net_12_port, p_out => p_net_12_port);
pg_net_x_13 : pg_net_20 port map( a => A(13), b => B(13), g_out =>
g_net_13_port, p_out => p_net_13_port);
pg_net_x_14 : pg_net_19 port map( a => A(14), b => B(14), g_out =>
g_net_14_port, p_out => p_net_14_port);
pg_net_x_15 : pg_net_18 port map( a => A(15), b => B(15), g_out =>
g_net_15_port, p_out => p_net_15_port);
pg_net_x_16 : pg_net_17 port map( a => A(16), b => B(16), g_out =>
g_net_16_port, p_out => p_net_16_port);
pg_net_x_17 : pg_net_16 port map( a => A(17), b => B(17), g_out =>
g_net_17_port, p_out => p_net_17_port);
pg_net_x_18 : pg_net_15 port map( a => A(18), b => B(18), g_out =>
g_net_18_port, p_out => p_net_18_port);
pg_net_x_19 : pg_net_14 port map( a => A(19), b => B(19), g_out =>
g_net_19_port, p_out => p_net_19_port);
pg_net_x_20 : pg_net_13 port map( a => A(20), b => B(20), g_out =>
g_net_20_port, p_out => p_net_20_port);
pg_net_x_21 : pg_net_12 port map( a => A(21), b => B(21), g_out =>
g_net_21_port, p_out => p_net_21_port);
pg_net_x_22 : pg_net_11 port map( a => A(22), b => B(22), g_out =>
g_net_22_port, p_out => p_net_22_port);
pg_net_x_23 : pg_net_10 port map( a => A(23), b => B(23), g_out =>
g_net_23_port, p_out => p_net_23_port);
pg_net_x_24 : pg_net_9 port map( a => A(24), b => B(24), g_out =>
g_net_24_port, p_out => p_net_24_port);
pg_net_x_25 : pg_net_8 port map( a => A(25), b => B(25), g_out =>
g_net_25_port, p_out => p_net_25_port);
pg_net_x_26 : pg_net_7 port map( a => A(26), b => B(26), g_out =>
g_net_26_port, p_out => p_net_26_port);
pg_net_x_27 : pg_net_6 port map( a => A(27), b => B(27), g_out =>
g_net_27_port, p_out => p_net_27_port);
pg_net_x_28 : pg_net_5 port map( a => A(28), b => B(28), g_out =>
g_net_28_port, p_out => p_net_28_port);
pg_net_x_29 : pg_net_4 port map( a => A(29), b => B(29), g_out =>
g_net_29_port, p_out => p_net_29_port);
pg_net_x_30 : pg_net_3 port map( a => A(30), b => B(30), g_out =>
g_net_30_port, p_out => p_net_30_port);
pg_net_x_31 : pg_net_2 port map( a => A(31), b => B(31), g_out =>
g_net_31_port, p_out => p_net_31_port);
pg_net_0_MAGIC : pg_net_1 port map( a => A(0), b => B(0), g_out =>
magic_pro_0_port, p_out => magic_pro_1_port);
xG_0_0_MAGIC : g_0 port map( g => magic_pro_0_port, p => magic_pro_1_port,
g_prec => Cin, g_out => g_net_0_port);
xG_1_0 : g_9 port map( g => g_net_1_port, p => p_net_1_port, g_prec =>
g_net_0_port, g_out => pg_1_0_0_port);
xPG_1_1 : pg_0 port map( g => g_net_3_port, p => p_net_3_port, g_prec =>
g_net_2_port, p_prec => p_net_2_port, g_out =>
pg_1_1_0_port, p_out => pg_1_1_1_port);
xPG_1_2 : pg_26 port map( g => g_net_5_port, p => p_net_5_port, g_prec =>
g_net_4_port, p_prec => p_net_4_port, g_out =>
pg_1_2_0_port, p_out => pg_1_2_1_port);
xPG_1_3 : pg_25 port map( g => g_net_7_port, p => p_net_7_port, g_prec =>
g_net_6_port, p_prec => p_net_6_port, p_out =>
pg_1_3_1_port, g_out_BAR => pg_1_3_0_port);
xPG_1_4 : pg_24 port map( g => g_net_9_port, p => p_net_9_port, g_prec =>
g_net_8_port, p_prec => p_net_8_port, g_out =>
pg_1_4_0_port, p_out => pg_1_4_1_port);
xPG_1_5 : pg_23 port map( g => g_net_11_port, p => p_net_11_port, g_prec =>
g_net_10_port, p_prec => p_net_10_port, p_out =>
pg_1_5_1_port, g_out_BAR => pg_1_5_0_port);
xPG_1_6 : pg_22 port map( g => g_net_13_port, p => p_net_13_port, g_prec =>
g_net_12_port, p_prec => p_net_12_port, g_out =>
pg_1_6_0_port, p_out => pg_1_6_1_port);
xPG_1_7 : pg_21 port map( g => g_net_15_port, p => p_net_15_port, g_prec =>
g_net_14_port, p_prec => p_net_14_port, p_out =>
pg_1_7_1_port, g_out_BAR => pg_1_7_0_port);
xPG_1_8 : pg_20 port map( g => g_net_17_port, p => p_net_17_port, g_prec =>
g_net_16_port, p_prec => p_net_16_port, g_out =>
pg_1_8_0_port, p_out => pg_1_8_1_port);
xPG_1_9 : pg_19 port map( g => g_net_19_port, p => p_net_19_port, g_prec =>
g_net_18_port, p_prec => p_net_18_port, p_out =>
pg_1_9_1_port, g_out_BAR => pg_1_9_0_port);
xPG_1_10 : pg_18 port map( g => g_net_21_port, p => p_net_21_port, g_prec =>
g_net_20_port, p_prec => p_net_20_port, g_out =>
pg_1_10_0_port, p_out => pg_1_10_1_port);
xPG_1_11 : pg_17 port map( g => g_net_23_port, p => p_net_23_port, g_prec =>
g_net_22_port, p_prec => p_net_22_port, g_out =>
pg_1_11_0_port, p_out => pg_1_11_1_port);
xPG_1_12 : pg_16 port map( g => g_net_25_port, p => p_net_25_port, g_prec =>
g_net_24_port, p_prec => p_net_24_port, g_out =>
pg_1_12_0_port, p_out => pg_1_12_1_port);
xPG_1_13 : pg_15 port map( g => g_net_27_port, p => p_net_27_port, g_prec =>
g_net_26_port, p_prec => p_net_26_port, g_out =>
pg_1_13_0_port, p_out => pg_1_13_1_port);
xPG_1_14 : pg_14 port map( g => g_net_29_port, p => p_net_29_port, g_prec =>
g_net_28_port, p_prec => p_net_28_port, g_out =>
pg_1_14_0_port, p_out => pg_1_14_1_port);
xPG_1_15 : pg_13 port map( g => g_net_31_port, p => p_net_31_port, g_prec =>
g_net_30_port, p_prec => p_net_30_port, g_out =>
pg_1_15_0_port, p_out => pg_1_15_1_port);
xG_2_0 : g_8 port map( g => pg_1_1_0_port, p => pg_1_1_1_port, g_prec =>
pg_1_0_0_port, g_out => n11);
xPG_2_1 : pg_12 port map( p => pg_1_3_1_port, g_prec => pg_1_2_0_port,
p_prec => pg_1_2_1_port, g_out => pg_n_2_1_0_port,
p_out => pg_n_2_1_1_port, g_BAR => pg_1_3_0_port);
xPG_2_2 : pg_11 port map( p => pg_1_5_1_port, g_prec => pg_1_4_0_port,
p_prec => pg_1_4_1_port, g_out => pg_n_2_2_0_port,
p_out => pg_n_2_2_1_port, g_BAR => pg_1_5_0_port);
xPG_2_3 : pg_10 port map( p => pg_1_7_1_port, g_prec => pg_1_6_0_port,
p_prec => pg_1_6_1_port, g_out => pg_n_2_3_0_port,
p_out => pg_n_2_3_1_port, g_BAR => pg_1_7_0_port);
xPG_2_4 : pg_9 port map( p => pg_1_9_1_port, g_prec => pg_1_8_0_port, p_prec
=> pg_1_8_1_port, g_out => pg_n_2_4_0_port, p_out =>
pg_n_2_4_1_port, g_BAR => pg_1_9_0_port);
xPG_2_5 : pg_8 port map( g => pg_1_11_0_port, p => pg_1_11_1_port, g_prec =>
pg_1_10_0_port, p_prec => pg_1_10_1_port, p_out =>
pg_n_2_5_1_port, g_out_BAR => pg_n_2_5_0_port);
xPG_2_6 : pg_7 port map( g => pg_1_13_0_port, p => pg_1_13_1_port, g_prec =>
pg_1_12_0_port, p_prec => pg_1_12_1_port, g_out =>
pg_n_2_6_0_port, p_out => pg_n_2_6_1_port);
xPG_2_7 : pg_6 port map( g => pg_1_15_0_port, p => pg_1_15_1_port, g_prec =>
pg_1_14_0_port, p_prec => pg_1_14_1_port, g_out =>
pg_n_2_7_0_port, p_out => pg_n_2_7_1_port);
xG_3_1 : g_7 port map( g => pg_n_2_1_0_port, p => pg_n_2_1_1_port, g_prec =>
n11, g_out => n10);
xG_4_2 : g_6 port map( g => pg_n_2_2_0_port, p => pg_n_2_2_1_port, g_prec =>
n8, g_out => Cout_2_port);
xG_4_3 : g_5 port map( g => pg_n_3_3_0_port, p => pg_n_3_3_1_port, g_prec =>
n10, g_out => n9);
xG_5_4 : g_4 port map( g => n5, p => pg_n_2_4_1_port, g_prec => n9, g_out =>
Cout_4_port);
xG_5_5 : g_3 port map( g => n7, p => pg_n_3_5_1_port, g_prec => n9, g_out =>
Cout_5_port);
xG_5_6 : g_2 port map( g => pg_n_4_6_0_port, p => pg_n_4_6_1_port, g_prec =>
n9, g_out => Cout_6_port);
xG_5_7 : g_1 port map( g => pg_n_4_7_0_port, p => pg_n_4_7_1_port, g_prec =>
n1, g_out => Cout_7_port);
xPG_3_3 : pg_5 port map( g => pg_n_2_3_0_port, p => pg_n_2_3_1_port, g_prec
=> pg_n_2_2_0_port, p_prec => pg_n_2_2_1_port, g_out
=> pg_n_3_3_0_port, p_out => pg_n_3_3_1_port);
xPG_3_5 : pg_4 port map( p => pg_n_2_5_1_port, g_prec => pg_n_2_4_0_port,
p_prec => pg_n_2_4_1_port, g_out => pg_n_3_5_0_port,
p_out => pg_n_3_5_1_port, g_BAR => pg_n_2_5_0_port);
xPG_3_7 : pg_3 port map( g => pg_n_2_7_0_port, p => pg_n_2_7_1_port, g_prec
=> pg_n_2_6_0_port, p_prec => pg_n_2_6_1_port, g_out
=> pg_n_3_7_0_port, p_out => pg_n_3_7_1_port);
xPG_4_6 : pg_2 port map( g => pg_n_2_6_0_port, p => pg_n_2_6_1_port, g_prec
=> pg_n_3_5_0_port, p_prec => pg_n_3_5_1_port, g_out
=> pg_n_4_6_0_port, p_out => pg_n_4_6_1_port);
xPG_4_7 : pg_1 port map( g => pg_n_3_7_0_port, p => pg_n_3_7_1_port, g_prec
=> n7, p_prec => pg_n_3_5_1_port, g_out =>
pg_n_4_7_0_port, p_out => pg_n_4_7_1_port);
U1 : CLKBUF_X1 port map( A => Cout_3_port, Z => n1);
U2 : BUF_X1 port map( A => n9, Z => Cout_3_port);
U3 : CLKBUF_X1 port map( A => pg_n_3_5_0_port, Z => n7);
U4 : CLKBUF_X1 port map( A => n11, Z => Cout_0_port);
U5 : CLKBUF_X1 port map( A => pg_n_2_4_0_port, Z => n5);
U6 : CLKBUF_X1 port map( A => n8, Z => Cout_1_port);
U7 : CLKBUF_X1 port map( A => n10, Z => n8);
end SYN_arch;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity xor_gen_N32 is
port( A : in std_logic_vector (31 downto 0); B : in std_logic; S : out
std_logic_vector (31 downto 0));
end xor_gen_N32;
architecture SYN_bhe of xor_gen_N32 is
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component BUF_X2
port( A : in std_logic; Z : out std_logic);
end component;
component XNOR2_X2
port( A, B : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component INV_X2
port( A : in std_logic; ZN : out std_logic);
end component;
component XOR2_X2
port( A, B : in std_logic; Z : out std_logic);
end component;
component MUX2_X1
port( A, B, S : in std_logic; Z : out std_logic);
end component;
signal n13, n1, n2, n3, n4, n6, n7, n8, n9, n10, n11 : std_logic;
begin
U8 : XOR2_X1 port map( A => B, B => A(31), Z => S(31));
U9 : XOR2_X1 port map( A => B, B => A(30), Z => S(30));
U12 : XOR2_X1 port map( A => B, B => A(28), Z => S(28));
U15 : XOR2_X1 port map( A => B, B => A(25), Z => S(25));
U17 : XOR2_X1 port map( A => B, B => A(23), Z => S(23));
U26 : XOR2_X1 port map( A => A(15), B => B, Z => S(15));
U30 : XOR2_X1 port map( A => B, B => A(11), Z => S(11));
U16 : XOR2_X1 port map( A => B, B => A(24), Z => S(24));
U1 : XOR2_X1 port map( A => A(20), B => B, Z => S(20));
U2 : XNOR2_X1 port map( A => n2, B => A(3), ZN => S(3));
U3 : MUX2_X1 port map( A => B, B => n2, S => A(7), Z => S(7));
U4 : XNOR2_X1 port map( A => A(8), B => n2, ZN => S(8));
U5 : XOR2_X1 port map( A => B, B => A(29), Z => S(29));
U6 : XOR2_X1 port map( A => B, B => A(26), Z => S(26));
U7 : XNOR2_X1 port map( A => A(27), B => n2, ZN => S(27));
U10 : XOR2_X2 port map( A => B, B => A(22), Z => S(22));
U11 : OAI21_X1 port map( B1 => A(13), B2 => n2, A => n4, ZN => S(13));
U13 : OAI21_X1 port map( B1 => n2, B2 => A(0), A => n1, ZN => S(0));
U14 : NAND2_X1 port map( A1 => A(0), A2 => n2, ZN => n1);
U18 : XNOR2_X2 port map( A => A(19), B => n2, ZN => S(19));
U19 : INV_X2 port map( A => B, ZN => n2);
U20 : XNOR2_X2 port map( A => A(12), B => n2, ZN => S(12));
U21 : XNOR2_X2 port map( A => A(21), B => n2, ZN => S(21));
U22 : XNOR2_X1 port map( A => A(17), B => n2, ZN => S(17));
U23 : XNOR2_X2 port map( A => A(16), B => n2, ZN => S(16));
U24 : XOR2_X1 port map( A => B, B => A(18), Z => S(18));
U25 : XOR2_X1 port map( A => A(2), B => B, Z => S(2));
U27 : BUF_X2 port map( A => n13, Z => S(6));
U28 : INV_X1 port map( A => A(9), ZN => n9);
U29 : INV_X1 port map( A => A(14), ZN => n6);
U31 : NAND2_X1 port map( A1 => A(1), A2 => n2, ZN => n3);
U32 : OAI21_X1 port map( B1 => A(1), B2 => n2, A => n3, ZN => S(1));
U33 : NAND2_X1 port map( A1 => A(13), A2 => n2, ZN => n4);
U34 : NAND2_X1 port map( A1 => n10, A2 => n11, ZN => S(9));
U35 : NAND2_X1 port map( A1 => n7, A2 => n8, ZN => S(14));
U36 : XOR2_X1 port map( A => B, B => A(10), Z => S(10));
U37 : XOR2_X1 port map( A => B, B => A(5), Z => S(5));
U38 : XOR2_X1 port map( A => B, B => A(6), Z => n13);
U39 : XOR2_X1 port map( A => A(4), B => B, Z => S(4));
U40 : NAND2_X1 port map( A1 => B, A2 => n6, ZN => n7);
U41 : NAND2_X1 port map( A1 => A(14), A2 => n2, ZN => n8);
U42 : NAND2_X1 port map( A1 => B, A2 => n9, ZN => n10);
U43 : NAND2_X1 port map( A1 => n2, A2 => A(9), ZN => n11);
end SYN_bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity ff32_en_SIZE32 is
port( D : in std_logic_vector (31 downto 0); en, clk, rst : in std_logic;
Q : out std_logic_vector (31 downto 0));
end ff32_en_SIZE32;
architecture SYN_behavioral of ff32_en_SIZE32 is
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component INV_X2
port( A : in std_logic; ZN : out std_logic);
end component;
component DFFR_X1
port( D, CK, RN : in std_logic; Q, QN : out std_logic);
end component;
signal n65, n66, n67, n68, n69, n70, n71, n72, n73, n74, n75, n76, n77, n78,
n79, n80, n81, n82, n83, n84, n85, n86, n87, n88, n89, n90, n91, n92, n93
, n94, n95, n97, net549739, net549740, net549741, net549742, net549743,
net549744, net549745, net549746, net549747, net549748, net549749,
net549750, net549751, net549752, net549753, net549754, net549755,
net549756, net549757, net549758, net549759, net549760, net549761,
net549762, net549763, net549764, net549765, net549766, net549767,
net549768, net549769, net549770, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11
, n13, n14, n15, n16, n17, n18, n19, n20, n21, n22, n23, n24, n25, n26,
n27, n28, n29, n30, n31, n32, n33, n1, n34 : std_logic;
begin
Q_reg_31_inst : DFFR_X1 port map( D => n97, CK => clk, RN => n34, Q => Q(31)
, QN => net549770);
Q_reg_30_inst : DFFR_X1 port map( D => n95, CK => clk, RN => n34, Q => Q(30)
, QN => net549769);
Q_reg_29_inst : DFFR_X1 port map( D => n94, CK => clk, RN => n34, Q => Q(29)
, QN => net549768);
Q_reg_28_inst : DFFR_X1 port map( D => n93, CK => clk, RN => n34, Q => Q(28)
, QN => net549767);
Q_reg_27_inst : DFFR_X1 port map( D => n92, CK => clk, RN => n34, Q => Q(27)
, QN => net549766);
Q_reg_26_inst : DFFR_X1 port map( D => n91, CK => clk, RN => n34, Q => Q(26)
, QN => net549765);
Q_reg_25_inst : DFFR_X1 port map( D => n90, CK => clk, RN => n34, Q => Q(25)
, QN => net549764);
Q_reg_24_inst : DFFR_X1 port map( D => n89, CK => clk, RN => n34, Q => Q(24)
, QN => net549763);
Q_reg_23_inst : DFFR_X1 port map( D => n88, CK => clk, RN => n34, Q => Q(23)
, QN => net549762);
Q_reg_22_inst : DFFR_X1 port map( D => n87, CK => clk, RN => n34, Q => Q(22)
, QN => net549761);
Q_reg_21_inst : DFFR_X1 port map( D => n86, CK => clk, RN => n34, Q => Q(21)
, QN => net549760);
Q_reg_19_inst : DFFR_X1 port map( D => n84, CK => clk, RN => n34, Q => Q(19)
, QN => net549758);
Q_reg_18_inst : DFFR_X1 port map( D => n83, CK => clk, RN => n34, Q => Q(18)
, QN => net549757);
Q_reg_17_inst : DFFR_X1 port map( D => n82, CK => clk, RN => n34, Q => Q(17)
, QN => net549756);
Q_reg_16_inst : DFFR_X1 port map( D => n81, CK => clk, RN => n34, Q => Q(16)
, QN => net549755);
Q_reg_15_inst : DFFR_X1 port map( D => n80, CK => clk, RN => n34, Q => Q(15)
, QN => net549754);
Q_reg_14_inst : DFFR_X1 port map( D => n79, CK => clk, RN => n34, Q => Q(14)
, QN => net549753);
Q_reg_13_inst : DFFR_X1 port map( D => n78, CK => clk, RN => n34, Q => Q(13)
, QN => net549752);
Q_reg_12_inst : DFFR_X1 port map( D => n77, CK => clk, RN => n34, Q => Q(12)
, QN => net549751);
Q_reg_11_inst : DFFR_X1 port map( D => n76, CK => clk, RN => n34, Q => Q(11)
, QN => net549750);
Q_reg_10_inst : DFFR_X1 port map( D => n75, CK => clk, RN => n34, Q => Q(10)
, QN => net549749);
Q_reg_9_inst : DFFR_X1 port map( D => n74, CK => clk, RN => n34, Q => Q(9),
QN => net549748);
Q_reg_8_inst : DFFR_X1 port map( D => n73, CK => clk, RN => n34, Q => Q(8),
QN => net549747);
Q_reg_7_inst : DFFR_X1 port map( D => n72, CK => clk, RN => n34, Q => Q(7),
QN => net549746);
Q_reg_6_inst : DFFR_X1 port map( D => n71, CK => clk, RN => n34, Q => Q(6),
QN => net549745);
Q_reg_5_inst : DFFR_X1 port map( D => n70, CK => clk, RN => n34, Q => Q(5),
QN => net549744);
Q_reg_4_inst : DFFR_X1 port map( D => n69, CK => clk, RN => n34, Q => Q(4),
QN => net549743);
Q_reg_3_inst : DFFR_X1 port map( D => n68, CK => clk, RN => n34, Q => Q(3),
QN => net549742);
Q_reg_2_inst : DFFR_X1 port map( D => n67, CK => clk, RN => n34, Q => Q(2),
QN => net549741);
Q_reg_1_inst : DFFR_X1 port map( D => n66, CK => clk, RN => n34, Q => Q(1),
QN => net549740);
Q_reg_0_inst : DFFR_X1 port map( D => n65, CK => clk, RN => n34, Q => Q(0),
QN => net549739);
U9 : OAI21_X1 port map( B1 => en, B2 => net549767, A => n5, ZN => n93);
U21 : OAI21_X1 port map( B1 => en, B2 => net549761, A => n11, ZN => n87);
U7 : OAI21_X1 port map( B1 => en, B2 => net549768, A => n4, ZN => n94);
U2 : OAI21_X1 port map( B1 => en, B2 => net549770, A => n2, ZN => n97);
U17 : OAI21_X1 port map( B1 => en, B2 => net549763, A => n9, ZN => n89);
U11 : OAI21_X1 port map( B1 => en, B2 => net549766, A => n6, ZN => n92);
U19 : OAI21_X1 port map( B1 => en, B2 => net549762, A => n10, ZN => n88);
U13 : OAI21_X1 port map( B1 => en, B2 => net549765, A => n7, ZN => n91);
U40 : NAND2_X1 port map( A1 => en, A2 => D(13), ZN => n20);
U39 : OAI21_X1 port map( B1 => en, B2 => net549752, A => n20, ZN => n78);
U36 : NAND2_X1 port map( A1 => en, A2 => D(15), ZN => n18);
U35 : OAI21_X1 port map( B1 => en, B2 => net549754, A => n18, ZN => n80);
U32 : NAND2_X1 port map( A1 => en, A2 => D(17), ZN => n16);
U31 : OAI21_X1 port map( B1 => en, B2 => net549756, A => n16, ZN => n82);
U30 : NAND2_X1 port map( A1 => en, A2 => D(18), ZN => n15);
U29 : OAI21_X1 port map( B1 => en, B2 => net549757, A => n15, ZN => n83);
U34 : NAND2_X1 port map( A1 => en, A2 => D(16), ZN => n17);
U33 : OAI21_X1 port map( B1 => en, B2 => net549755, A => n17, ZN => n81);
U27 : OAI21_X1 port map( B1 => en, B2 => net549758, A => n14, ZN => n84);
U38 : NAND2_X1 port map( A1 => en, A2 => D(14), ZN => n19);
U37 : OAI21_X1 port map( B1 => en, B2 => net549753, A => n19, ZN => n79);
U42 : NAND2_X1 port map( A1 => en, A2 => D(12), ZN => n21);
U41 : OAI21_X1 port map( B1 => en, B2 => net549751, A => n21, ZN => n77);
U44 : NAND2_X1 port map( A1 => en, A2 => D(11), ZN => n22);
U43 : OAI21_X1 port map( B1 => en, B2 => net549750, A => n22, ZN => n76);
U50 : NAND2_X1 port map( A1 => en, A2 => D(8), ZN => n25);
U49 : OAI21_X1 port map( B1 => en, B2 => net549747, A => n25, ZN => n73);
U48 : NAND2_X1 port map( A1 => en, A2 => D(9), ZN => n24);
U47 : OAI21_X1 port map( B1 => en, B2 => net549748, A => n24, ZN => n74);
U46 : NAND2_X1 port map( A1 => en, A2 => D(10), ZN => n23);
U45 : OAI21_X1 port map( B1 => en, B2 => net549749, A => n23, ZN => n75);
U52 : NAND2_X1 port map( A1 => en, A2 => D(7), ZN => n26);
U51 : OAI21_X1 port map( B1 => en, B2 => net549746, A => n26, ZN => n72);
U54 : NAND2_X1 port map( A1 => en, A2 => D(6), ZN => n27);
U53 : OAI21_X1 port map( B1 => en, B2 => net549745, A => n27, ZN => n71);
U60 : NAND2_X1 port map( A1 => en, A2 => D(3), ZN => n30);
U59 : OAI21_X1 port map( B1 => en, B2 => net549742, A => n30, ZN => n68);
U56 : NAND2_X1 port map( A1 => en, A2 => D(5), ZN => n28);
U55 : OAI21_X1 port map( B1 => en, B2 => net549744, A => n28, ZN => n70);
U58 : NAND2_X1 port map( A1 => en, A2 => D(4), ZN => n29);
U57 : OAI21_X1 port map( B1 => en, B2 => net549743, A => n29, ZN => n69);
U62 : NAND2_X1 port map( A1 => en, A2 => D(2), ZN => n31);
U61 : OAI21_X1 port map( B1 => en, B2 => net549741, A => n31, ZN => n67);
U64 : NAND2_X1 port map( A1 => en, A2 => D(1), ZN => n32);
U63 : OAI21_X1 port map( B1 => en, B2 => net549740, A => n32, ZN => n66);
U66 : NAND2_X1 port map( A1 => en, A2 => D(0), ZN => n33);
U65 : OAI21_X1 port map( B1 => en, B2 => net549739, A => n33, ZN => n65);
Q_reg_20_inst : DFFR_X1 port map( D => n85, CK => clk, RN => n34, Q => Q(20)
, QN => net549759);
U3 : NAND2_X1 port map( A1 => en, A2 => D(21), ZN => n1);
U4 : OAI21_X1 port map( B1 => en, B2 => net549760, A => n1, ZN => n86);
U5 : INV_X2 port map( A => rst, ZN => n34);
U6 : OAI21_X1 port map( B1 => en, B2 => net549769, A => n3, ZN => n95);
U8 : NAND2_X1 port map( A1 => en, A2 => D(30), ZN => n3);
U10 : OAI21_X1 port map( B1 => en, B2 => net549764, A => n8, ZN => n90);
U12 : NAND2_X1 port map( A1 => en, A2 => D(25), ZN => n8);
U14 : NAND2_X1 port map( A1 => en, A2 => D(24), ZN => n9);
U15 : NAND2_X1 port map( A1 => en, A2 => D(26), ZN => n7);
U16 : OAI21_X1 port map( B1 => en, B2 => net549759, A => n13, ZN => n85);
U18 : NAND2_X1 port map( A1 => en, A2 => D(20), ZN => n13);
U20 : NAND2_X1 port map( A1 => en, A2 => D(27), ZN => n6);
U22 : NAND2_X1 port map( A1 => en, A2 => D(23), ZN => n10);
U23 : NAND2_X1 port map( A1 => en, A2 => D(19), ZN => n14);
U24 : NAND2_X1 port map( A1 => en, A2 => D(22), ZN => n11);
U25 : NAND2_X1 port map( A1 => en, A2 => D(28), ZN => n5);
U26 : NAND2_X1 port map( A1 => en, A2 => D(29), ZN => n4);
U28 : NAND2_X1 port map( A1 => en, A2 => D(31), ZN => n2);
end SYN_behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity piso_r_2_N32 is
port( Clock, ALOAD : in std_logic; D : in std_logic_vector (31 downto 0);
SO : out std_logic_vector (31 downto 0));
end piso_r_2_N32;
architecture SYN_archi of piso_r_2_N32 is
component SDFF_X1
port( D, SI, SE, CK : in std_logic; Q, QN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component DFF_X1
port( D, CK : in std_logic; Q, QN : out std_logic);
end component;
signal SO_31_port, SO_30_port, SO_29_port, SO_28_port, SO_27_port,
SO_26_port, SO_25_port, SO_24_port, SO_23_port, SO_22_port, SO_21_port,
SO_20_port, SO_19_port, SO_18_port, SO_17_port, SO_16_port, SO_15_port,
SO_14_port, SO_13_port, SO_12_port, SO_11_port, SO_10_port, SO_9_port,
SO_8_port, SO_7_port, SO_6_port, SO_5_port, SO_4_port, SO_3_port,
SO_2_port, SO_1_port, SO_0_port, N3, N4, N5, N6, N7, N8, N9, N10, N11,
N12, N13, N14, N15, N16, N17, N18, N19, N20, N21, N22, N23, N24, N25, N26
, N27, N28, N29, N30, N31, N32, net549709, net549710, net549711,
net549712, net549713, net549714, net549715, net549716, net549717,
net549718, net549719, net549720, net549721, net549722, net549723,
net549724, net549725, net549726, net549727, net549728, net549729,
net549730, net549731, net549732, net549733, net549734, net549735,
net549736, net549737, net549738, n1, n3_port, n4_port, n5_port, n6_port,
n9_port, n10_port, n11_port, n12_port, n13_port, n14_port, n15_port,
n16_port, n17_port, n19_port, n20_port, n21_port, n22_port, n23_port,
n24_port, n25_port, n26_port, n27_port, n28_port, n29_port, n30_port,
n31_port, n32_port, n2, n7_port : std_logic;
begin
SO <= ( SO_31_port, SO_30_port, SO_29_port, SO_28_port, SO_27_port,
SO_26_port, SO_25_port, SO_24_port, SO_23_port, SO_22_port, SO_21_port,
SO_20_port, SO_19_port, SO_18_port, SO_17_port, SO_16_port, SO_15_port,
SO_14_port, SO_13_port, SO_12_port, SO_11_port, SO_10_port, SO_9_port,
SO_8_port, SO_7_port, SO_6_port, SO_5_port, SO_4_port, SO_3_port,
SO_2_port, SO_1_port, SO_0_port );
tmp_reg_1_inst : DFF_X1 port map( D => N4, CK => Clock, Q => SO_1_port, QN
=> net549738);
tmp_reg_3_inst : DFF_X1 port map( D => N6, CK => Clock, Q => SO_3_port, QN
=> net549737);
tmp_reg_5_inst : DFF_X1 port map( D => N8, CK => Clock, Q => SO_5_port, QN
=> net549736);
tmp_reg_7_inst : DFF_X1 port map( D => N10, CK => Clock, Q => SO_7_port, QN
=> net549735);
tmp_reg_9_inst : DFF_X1 port map( D => N12, CK => Clock, Q => SO_9_port, QN
=> net549734);
tmp_reg_11_inst : DFF_X1 port map( D => N14, CK => Clock, Q => SO_11_port,
QN => net549733);
tmp_reg_13_inst : DFF_X1 port map( D => N16, CK => Clock, Q => SO_13_port,
QN => net549732);
tmp_reg_15_inst : DFF_X1 port map( D => N18, CK => Clock, Q => SO_15_port,
QN => net549731);
tmp_reg_17_inst : DFF_X1 port map( D => N20, CK => Clock, Q => SO_17_port,
QN => net549730);
tmp_reg_19_inst : DFF_X1 port map( D => N22, CK => Clock, Q => SO_19_port,
QN => net549729);
tmp_reg_21_inst : DFF_X1 port map( D => N24, CK => Clock, Q => SO_21_port,
QN => net549728);
tmp_reg_23_inst : DFF_X1 port map( D => N26, CK => Clock, Q => SO_23_port,
QN => net549727);
tmp_reg_25_inst : DFF_X1 port map( D => N28, CK => Clock, Q => SO_25_port,
QN => net549726);
tmp_reg_27_inst : DFF_X1 port map( D => N30, CK => Clock, Q => SO_27_port,
QN => net549725);
tmp_reg_29_inst : DFF_X1 port map( D => N32, CK => Clock, Q => SO_29_port,
QN => net549724);
tmp_reg_0_inst : DFF_X1 port map( D => N3, CK => Clock, Q => SO_0_port, QN
=> net549723);
tmp_reg_2_inst : DFF_X1 port map( D => N5, CK => Clock, Q => SO_2_port, QN
=> net549722);
tmp_reg_4_inst : DFF_X1 port map( D => N7, CK => Clock, Q => SO_4_port, QN
=> net549721);
tmp_reg_6_inst : DFF_X1 port map( D => N9, CK => Clock, Q => SO_6_port, QN
=> net549720);
tmp_reg_8_inst : DFF_X1 port map( D => N11, CK => Clock, Q => SO_8_port, QN
=> net549719);
tmp_reg_10_inst : DFF_X1 port map( D => N13, CK => Clock, Q => SO_10_port,
QN => net549718);
tmp_reg_12_inst : DFF_X1 port map( D => N15, CK => Clock, Q => SO_12_port,
QN => net549717);
tmp_reg_14_inst : DFF_X1 port map( D => N17, CK => Clock, Q => SO_14_port,
QN => net549716);
tmp_reg_16_inst : DFF_X1 port map( D => N19, CK => Clock, Q => SO_16_port,
QN => net549715);
tmp_reg_18_inst : DFF_X1 port map( D => N21, CK => Clock, Q => SO_18_port,
QN => net549714);
tmp_reg_20_inst : DFF_X1 port map( D => N23, CK => Clock, Q => SO_20_port,
QN => net549713);
tmp_reg_22_inst : DFF_X1 port map( D => N25, CK => Clock, Q => SO_22_port,
QN => net549712);
tmp_reg_24_inst : DFF_X1 port map( D => N27, CK => Clock, Q => SO_24_port,
QN => net549711);
tmp_reg_26_inst : DFF_X1 port map( D => N29, CK => Clock, Q => SO_26_port,
QN => net549710);
tmp_reg_28_inst : DFF_X1 port map( D => N31, CK => Clock, Q => SO_28_port,
QN => net549709);
U26 : NAND2_X1 port map( A1 => ALOAD, A2 => D(26), ZN => n12_port);
U25 : OAI21_X1 port map( B1 => ALOAD, B2 => net549711, A => n12_port, ZN =>
N29);
U30 : NAND2_X1 port map( A1 => ALOAD, A2 => D(24), ZN => n14_port);
U29 : OAI21_X1 port map( B1 => ALOAD, B2 => net549712, A => n14_port, ZN =>
N27);
U32 : NAND2_X1 port map( A1 => ALOAD, A2 => D(23), ZN => n15_port);
U31 : OAI21_X1 port map( B1 => ALOAD, B2 => net549728, A => n15_port, ZN =>
N26);
U36 : NAND2_X1 port map( A1 => ALOAD, A2 => D(21), ZN => n17_port);
U35 : OAI21_X1 port map( B1 => ALOAD, B2 => net549729, A => n17_port, ZN =>
N24);
U38 : NAND2_X1 port map( A1 => ALOAD, A2 => D(20), ZN => n19_port);
U37 : OAI21_X1 port map( B1 => ALOAD, B2 => net549714, A => n19_port, ZN =>
N23);
U42 : NAND2_X1 port map( A1 => ALOAD, A2 => D(18), ZN => n21_port);
U41 : OAI21_X1 port map( B1 => ALOAD, B2 => net549715, A => n21_port, ZN =>
N21);
U44 : NAND2_X1 port map( A1 => ALOAD, A2 => D(17), ZN => n22_port);
U43 : OAI21_X1 port map( B1 => ALOAD, B2 => net549731, A => n22_port, ZN =>
N20);
U34 : NAND2_X1 port map( A1 => ALOAD, A2 => D(22), ZN => n16_port);
U33 : OAI21_X1 port map( B1 => ALOAD, B2 => net549713, A => n16_port, ZN =>
N25);
U46 : NAND2_X1 port map( A1 => ALOAD, A2 => D(16), ZN => n23_port);
U45 : OAI21_X1 port map( B1 => ALOAD, B2 => net549716, A => n23_port, ZN =>
N19);
U19 : NAND2_X1 port map( A1 => ALOAD, A2 => D(29), ZN => n9_port);
U18 : OAI21_X1 port map( B1 => ALOAD, B2 => net549725, A => n9_port, ZN =>
N32);
U23 : NAND2_X1 port map( A1 => ALOAD, A2 => D(27), ZN => n11_port);
U22 : OAI21_X1 port map( B1 => ALOAD, B2 => net549726, A => n11_port, ZN =>
N30);
U28 : NAND2_X1 port map( A1 => ALOAD, A2 => D(25), ZN => n13_port);
U27 : OAI21_X1 port map( B1 => ALOAD, B2 => net549727, A => n13_port, ZN =>
N28);
U21 : NAND2_X1 port map( A1 => ALOAD, A2 => D(28), ZN => n10_port);
U20 : OAI21_X1 port map( B1 => ALOAD, B2 => net549710, A => n10_port, ZN =>
N31);
U40 : NAND2_X1 port map( A1 => ALOAD, A2 => D(19), ZN => n20_port);
U39 : OAI21_X1 port map( B1 => ALOAD, B2 => net549730, A => n20_port, ZN =>
N22);
U12 : NAND2_X1 port map( A1 => ALOAD, A2 => D(2), ZN => n6_port);
U11 : OAI21_X1 port map( B1 => ALOAD, B2 => net549723, A => n6_port, ZN =>
N5);
U50 : NAND2_X1 port map( A1 => ALOAD, A2 => D(14), ZN => n25_port);
U49 : OAI21_X1 port map( B1 => ALOAD, B2 => net549717, A => n25_port, ZN =>
N17);
U54 : NAND2_X1 port map( A1 => ALOAD, A2 => D(12), ZN => n27_port);
U53 : OAI21_X1 port map( B1 => ALOAD, B2 => net549718, A => n27_port, ZN =>
N15);
U58 : NAND2_X1 port map( A1 => ALOAD, A2 => D(10), ZN => n29_port);
U57 : OAI21_X1 port map( B1 => ALOAD, B2 => net549719, A => n29_port, ZN =>
N13);
U62 : NAND2_X1 port map( A1 => ALOAD, A2 => D(8), ZN => n31_port);
U61 : OAI21_X1 port map( B1 => ALOAD, B2 => net549720, A => n31_port, ZN =>
N11);
U4 : NAND2_X1 port map( A1 => ALOAD, A2 => D(6), ZN => n1);
U3 : OAI21_X1 port map( B1 => ALOAD, B2 => net549721, A => n1, ZN => N9);
U8 : NAND2_X1 port map( A1 => ALOAD, A2 => D(4), ZN => n4_port);
U7 : OAI21_X1 port map( B1 => ALOAD, B2 => net549722, A => n4_port, ZN => N7
);
U64 : NAND2_X1 port map( A1 => ALOAD, A2 => D(7), ZN => n32_port);
U63 : OAI21_X1 port map( B1 => ALOAD, B2 => net549736, A => n32_port, ZN =>
N10);
U48 : NAND2_X1 port map( A1 => ALOAD, A2 => D(15), ZN => n24_port);
U47 : OAI21_X1 port map( B1 => ALOAD, B2 => net549732, A => n24_port, ZN =>
N18);
U52 : NAND2_X1 port map( A1 => ALOAD, A2 => D(13), ZN => n26_port);
U51 : OAI21_X1 port map( B1 => ALOAD, B2 => net549733, A => n26_port, ZN =>
N16);
U56 : NAND2_X1 port map( A1 => ALOAD, A2 => D(11), ZN => n28_port);
U55 : OAI21_X1 port map( B1 => ALOAD, B2 => net549734, A => n28_port, ZN =>
N14);
U60 : NAND2_X1 port map( A1 => ALOAD, A2 => D(9), ZN => n30_port);
U59 : OAI21_X1 port map( B1 => ALOAD, B2 => net549735, A => n30_port, ZN =>
N12);
U10 : NAND2_X1 port map( A1 => ALOAD, A2 => D(3), ZN => n5_port);
U9 : OAI21_X1 port map( B1 => ALOAD, B2 => net549738, A => n5_port, ZN => N6
);
U6 : NAND2_X1 port map( A1 => ALOAD, A2 => D(5), ZN => n3_port);
U5 : OAI21_X1 port map( B1 => ALOAD, B2 => net549737, A => n3_port, ZN => N8
);
U24 : AND2_X1 port map( A1 => ALOAD, A2 => D(0), ZN => N3);
U13 : AND2_X1 port map( A1 => ALOAD, A2 => D(1), ZN => N4);
tmp_reg_31_inst : SDFF_X1 port map( D => SO_29_port, SI => D(31), SE =>
ALOAD, CK => Clock, Q => SO_31_port, QN => n7_port);
tmp_reg_30_inst : SDFF_X1 port map( D => SO_28_port, SI => D(30), SE =>
ALOAD, CK => Clock, Q => SO_30_port, QN => n2);
end SYN_archi;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity shift_N9_2 is
port( Clock, ALOAD : in std_logic; D : in std_logic_vector (8 downto 0);
SO : out std_logic);
end shift_N9_2;
architecture SYN_archi of shift_N9_2 is
component SDFF_X1
port( D, SI, SE, CK : in std_logic; Q, QN : out std_logic);
end component;
signal tmp_8_port, tmp_7_port, tmp_6_port, tmp_5_port, tmp_4_port,
tmp_3_port, tmp_2_port, tmp_1_port, n2, n3, n4, n5, n6, n7, n8, n9, n10,
n11 : std_logic;
begin
tmp_reg_7_inst : SDFF_X1 port map( D => tmp_8_port, SI => D(7), SE => ALOAD,
CK => Clock, Q => tmp_7_port, QN => n11);
tmp_reg_0_inst : SDFF_X1 port map( D => tmp_1_port, SI => D(0), SE => ALOAD,
CK => Clock, Q => SO, QN => n10);
tmp_reg_6_inst : SDFF_X1 port map( D => tmp_7_port, SI => D(6), SE => ALOAD,
CK => Clock, Q => tmp_6_port, QN => n9);
tmp_reg_2_inst : SDFF_X1 port map( D => tmp_3_port, SI => D(2), SE => ALOAD,
CK => Clock, Q => tmp_2_port, QN => n8);
tmp_reg_5_inst : SDFF_X1 port map( D => tmp_6_port, SI => D(5), SE => ALOAD,
CK => Clock, Q => tmp_5_port, QN => n7);
tmp_reg_4_inst : SDFF_X1 port map( D => tmp_5_port, SI => D(4), SE => ALOAD,
CK => Clock, Q => tmp_4_port, QN => n6);
tmp_reg_3_inst : SDFF_X1 port map( D => tmp_4_port, SI => D(3), SE => ALOAD,
CK => Clock, Q => tmp_3_port, QN => n5);
tmp_reg_8_inst : SDFF_X1 port map( D => n3, SI => D(8), SE => ALOAD, CK =>
Clock, Q => tmp_8_port, QN => n4);
tmp_reg_1_inst : SDFF_X1 port map( D => tmp_2_port, SI => D(1), SE => ALOAD,
CK => Clock, Q => tmp_1_port, QN => n2);
n3 <= '0';
end SYN_archi;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity shift_N9_0 is
port( Clock, ALOAD : in std_logic; D : in std_logic_vector (8 downto 0);
SO : out std_logic);
end shift_N9_0;
architecture SYN_archi of shift_N9_0 is
component SDFF_X2
port( D, SI, SE, CK : in std_logic; Q, QN : out std_logic);
end component;
component SDFF_X1
port( D, SI, SE, CK : in std_logic; Q, QN : out std_logic);
end component;
signal tmp_8_port, tmp_7_port, tmp_6_port, tmp_5_port, tmp_4_port,
tmp_3_port, tmp_2_port, tmp_1_port, n2, n3, n4, n5, n6, n7, n8, n9, n10,
n11 : std_logic;
begin
tmp_reg_7_inst : SDFF_X1 port map( D => tmp_8_port, SI => D(7), SE => ALOAD,
CK => Clock, Q => tmp_7_port, QN => n11);
tmp_reg_3_inst : SDFF_X1 port map( D => tmp_4_port, SI => D(3), SE => ALOAD,
CK => Clock, Q => tmp_3_port, QN => n10);
tmp_reg_4_inst : SDFF_X1 port map( D => tmp_5_port, SI => D(4), SE => ALOAD,
CK => Clock, Q => tmp_4_port, QN => n9);
tmp_reg_5_inst : SDFF_X1 port map( D => tmp_6_port, SI => D(5), SE => ALOAD,
CK => Clock, Q => tmp_5_port, QN => n8);
tmp_reg_6_inst : SDFF_X1 port map( D => tmp_7_port, SI => D(6), SE => ALOAD,
CK => Clock, Q => tmp_6_port, QN => n7);
tmp_reg_1_inst : SDFF_X1 port map( D => tmp_2_port, SI => D(1), SE => ALOAD,
CK => Clock, Q => tmp_1_port, QN => n6);
tmp_reg_2_inst : SDFF_X1 port map( D => tmp_3_port, SI => D(2), SE => ALOAD,
CK => Clock, Q => tmp_2_port, QN => n5);
tmp_reg_8_inst : SDFF_X1 port map( D => n3, SI => D(8), SE => ALOAD, CK =>
Clock, Q => tmp_8_port, QN => n4);
tmp_reg_0_inst : SDFF_X2 port map( D => tmp_1_port, SI => D(0), SE => ALOAD,
CK => Clock, Q => SO, QN => n2);
n3 <= '0';
end SYN_archi;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity booth_encoder_0 is
port( B_in : in std_logic_vector (2 downto 0); A_out : out std_logic_vector
(2 downto 0));
end booth_encoder_0;
architecture SYN_bhe of booth_encoder_0 is
component NOR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
signal N53, N57, n5, n6 : std_logic;
begin
A_out <= ( N57, B_in(2), N53 );
U3 : INV_X1 port map( A => B_in(1), ZN => n5);
U4 : INV_X1 port map( A => B_in(2), ZN => n6);
U5 : NAND2_X1 port map( A1 => n6, A2 => n5, ZN => N57);
U6 : NOR2_X1 port map( A1 => B_in(1), A2 => n6, ZN => N53);
end SYN_bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity logic_unit_SIZE32 is
port( IN1, IN2 : in std_logic_vector (31 downto 0); CTRL : in
std_logic_vector (1 downto 0); OUT1 : out std_logic_vector (31 downto
0));
end logic_unit_SIZE32;
architecture SYN_Bhe of logic_unit_SIZE32 is
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component OAI22_X1
port( A1, A2, B1, B2 : in std_logic; ZN : out std_logic);
end component;
component BUF_X2
port( A : in std_logic; Z : out std_logic);
end component;
component INV_X2
port( A : in std_logic; ZN : out std_logic);
end component;
signal n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16,
n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30, n31
, n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44, n45,
n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58, n59, n60
, n61, n62, n63, n64, n166, n167, n169 : std_logic;
begin
U25 : AOI21_X1 port map( B1 => IN2(31), B2 => IN1(31), A => CTRL(0), ZN =>
n17);
U24 : OAI22_X1 port map( A1 => IN1(31), A2 => IN2(31), B1 => n2, B2 => n17,
ZN => n18);
U23 : AOI21_X1 port map( B1 => n169, B2 => n17, A => n18, ZN => OUT1(31));
U65 : AOI21_X1 port map( B1 => n2, B2 => n45, A => n46, ZN => OUT1(19));
U61 : AOI21_X1 port map( B1 => IN2(20), B2 => IN1(20), A => CTRL(0), ZN =>
n41);
U60 : OAI22_X1 port map( A1 => IN1(20), A2 => IN2(20), B1 => n169, B2 => n41
, ZN => n42);
U59 : AOI21_X1 port map( B1 => n169, B2 => n41, A => n42, ZN => OUT1(20));
U56 : AOI21_X1 port map( B1 => n2, B2 => n39, A => n40, ZN => OUT1(21));
U20 : AOI21_X1 port map( B1 => n169, B2 => n15, A => n16, ZN => OUT1(3));
U54 : OAI22_X1 port map( A1 => IN1(22), A2 => IN2(22), B1 => n169, B2 => n37
, ZN => n38);
U53 : AOI21_X1 port map( B1 => n169, B2 => n37, A => n38, ZN => OUT1(22));
U49 : AOI21_X1 port map( B1 => IN2(24), B2 => IN1(24), A => CTRL(0), ZN =>
n33);
U48 : OAI22_X1 port map( A1 => IN1(24), A2 => IN2(24), B1 => n2, B2 => n33,
ZN => n34);
U47 : AOI21_X1 port map( B1 => n169, B2 => n33, A => n34, ZN => OUT1(24));
U77 : AOI21_X1 port map( B1 => n169, B2 => n53, A => n54, ZN => OUT1(15));
U5 : AOI21_X1 port map( B1 => n2, B2 => n5, A => n6, ZN => OUT1(8));
U11 : AOI21_X1 port map( B1 => n2, B2 => n9, A => n10, ZN => OUT1(6));
U46 : AOI21_X1 port map( B1 => IN2(25), B2 => IN1(25), A => CTRL(0), ZN =>
n31);
U45 : OAI22_X1 port map( A1 => IN1(25), A2 => IN2(25), B1 => n2, B2 => n31,
ZN => n32);
U44 : AOI21_X1 port map( B1 => n169, B2 => n31, A => n32, ZN => OUT1(25));
U71 : AOI21_X1 port map( B1 => n169, B2 => n49, A => n50, ZN => OUT1(17));
U86 : AOI21_X1 port map( B1 => n2, B2 => n59, A => n60, ZN => OUT1(12));
U76 : AOI21_X1 port map( B1 => IN2(16), B2 => IN1(16), A => CTRL(0), ZN =>
n51);
U75 : OAI22_X1 port map( A1 => IN1(16), A2 => IN2(16), B1 => n2, B2 => n51,
ZN => n52);
U74 : AOI21_X1 port map( B1 => n169, B2 => n51, A => n52, ZN => OUT1(16));
U37 : AOI21_X1 port map( B1 => IN2(28), B2 => IN1(28), A => CTRL(0), ZN =>
n25);
U36 : OAI22_X1 port map( A1 => IN1(28), A2 => IN2(28), B1 => n2, B2 => n25,
ZN => n26);
U35 : AOI21_X1 port map( B1 => n169, B2 => n25, A => n26, ZN => OUT1(28));
U19 : AOI21_X1 port map( B1 => IN2(4), B2 => IN1(4), A => CTRL(0), ZN => n13
);
U18 : OAI22_X1 port map( A1 => IN1(4), A2 => IN2(4), B1 => n169, B2 => n13,
ZN => n14);
U17 : AOI21_X1 port map( B1 => n169, B2 => n13, A => n14, ZN => OUT1(4));
U40 : AOI21_X1 port map( B1 => IN2(27), B2 => IN1(27), A => CTRL(0), ZN =>
n27);
U39 : OAI22_X1 port map( A1 => IN1(27), A2 => IN2(27), B1 => n2, B2 => n27,
ZN => n28);
U38 : AOI21_X1 port map( B1 => n2, B2 => n27, A => n28, ZN => OUT1(27));
U14 : AOI21_X1 port map( B1 => n2, B2 => n11, A => n12, ZN => OUT1(5));
U83 : AOI21_X1 port map( B1 => n169, B2 => n57, A => n58, ZN => OUT1(13));
U2 : AOI21_X1 port map( B1 => n2, B2 => n3, A => n4, ZN => OUT1(9));
U8 : AOI21_X1 port map( B1 => n169, B2 => n7, A => n8, ZN => OUT1(7));
U80 : AOI21_X1 port map( B1 => n2, B2 => n55, A => n56, ZN => OUT1(14));
U68 : AOI21_X1 port map( B1 => n169, B2 => n47, A => n48, ZN => OUT1(18));
U50 : AOI21_X1 port map( B1 => n169, B2 => n35, A => n36, ZN => OUT1(23));
U41 : AOI21_X1 port map( B1 => n2, B2 => n29, A => n30, ZN => OUT1(26));
U34 : AOI21_X1 port map( B1 => IN2(29), B2 => IN1(29), A => CTRL(0), ZN =>
n23);
U33 : OAI22_X1 port map( A1 => IN1(29), A2 => IN2(29), B1 => n2, B2 => n23,
ZN => n24);
U32 : AOI21_X1 port map( B1 => n169, B2 => n23, A => n24, ZN => OUT1(29));
U31 : AOI21_X1 port map( B1 => IN2(2), B2 => IN1(2), A => CTRL(0), ZN => n21
);
U30 : OAI22_X1 port map( A1 => IN1(2), A2 => IN2(2), B1 => n2, B2 => n21, ZN
=> n22);
U29 : AOI21_X1 port map( B1 => n2, B2 => n21, A => n22, ZN => OUT1(2));
U62 : AOI21_X1 port map( B1 => n169, B2 => n43, A => n44, ZN => OUT1(1));
U28 : AOI21_X1 port map( B1 => IN2(30), B2 => IN1(30), A => CTRL(0), ZN =>
n19);
U27 : OAI22_X1 port map( A1 => IN1(30), A2 => IN2(30), B1 => n2, B2 => n19,
ZN => n20);
U26 : AOI21_X1 port map( B1 => n2, B2 => n19, A => n20, ZN => OUT1(30));
U89 : AOI21_X1 port map( B1 => n169, B2 => n61, A => n62, ZN => OUT1(11));
U92 : AOI21_X1 port map( B1 => n169, B2 => n63, A => n64, ZN => OUT1(10));
U3 : AOI21_X1 port map( B1 => IN1(0), B2 => IN2(0), A => CTRL(0), ZN => n166
);
U4 : OAI22_X1 port map( A1 => IN2(0), A2 => IN1(0), B1 => n2, B2 => n166, ZN
=> n167);
U6 : AOI21_X1 port map( B1 => n2, B2 => n166, A => n167, ZN => OUT1(0));
U7 : INV_X2 port map( A => CTRL(1), ZN => n2);
U9 : BUF_X2 port map( A => n2, Z => n169);
U10 : OAI22_X1 port map( A1 => IN1(18), A2 => IN2(18), B1 => n169, B2 => n47
, ZN => n48);
U12 : AOI21_X1 port map( B1 => IN2(18), B2 => IN1(18), A => CTRL(0), ZN =>
n47);
U13 : OAI22_X1 port map( A1 => IN1(10), A2 => IN2(10), B1 => n2, B2 => n63,
ZN => n64);
U15 : AOI21_X1 port map( B1 => IN2(10), B2 => IN1(10), A => CTRL(0), ZN =>
n63);
U16 : OAI22_X1 port map( A1 => IN1(21), A2 => IN2(21), B1 => n169, B2 => n39
, ZN => n40);
U21 : AOI21_X1 port map( B1 => IN2(21), B2 => IN1(21), A => CTRL(0), ZN =>
n39);
U22 : OAI22_X1 port map( A1 => IN1(26), A2 => IN2(26), B1 => n169, B2 => n29
, ZN => n30);
U42 : AOI21_X1 port map( B1 => IN2(26), B2 => IN1(26), A => CTRL(0), ZN =>
n29);
U43 : OAI22_X1 port map( A1 => IN1(12), A2 => IN2(12), B1 => n2, B2 => n59,
ZN => n60);
U51 : AOI21_X1 port map( B1 => IN2(12), B2 => IN1(12), A => CTRL(0), ZN =>
n59);
U52 : OAI22_X1 port map( A1 => IN1(3), A2 => IN2(3), B1 => n169, B2 => n15,
ZN => n16);
U55 : AOI21_X1 port map( B1 => IN2(3), B2 => IN1(3), A => CTRL(0), ZN => n15
);
U57 : OAI22_X1 port map( A1 => IN1(1), A2 => IN2(1), B1 => n169, B2 => n43,
ZN => n44);
U58 : AOI21_X1 port map( B1 => IN2(1), B2 => IN1(1), A => CTRL(0), ZN => n43
);
U63 : OAI22_X1 port map( A1 => IN1(17), A2 => IN2(17), B1 => n169, B2 => n49
, ZN => n50);
U64 : AOI21_X1 port map( B1 => IN2(17), B2 => IN1(17), A => CTRL(0), ZN =>
n49);
U66 : OAI22_X1 port map( A1 => IN1(14), A2 => IN2(14), B1 => n2, B2 => n55,
ZN => n56);
U67 : AOI21_X1 port map( B1 => IN2(14), B2 => IN1(14), A => CTRL(0), ZN =>
n55);
U69 : OAI22_X1 port map( A1 => IN1(23), A2 => IN2(23), B1 => n169, B2 => n35
, ZN => n36);
U70 : AOI21_X1 port map( B1 => IN2(23), B2 => IN1(23), A => CTRL(0), ZN =>
n35);
U72 : OAI22_X1 port map( A1 => IN1(13), A2 => IN2(13), B1 => n2, B2 => n57,
ZN => n58);
U73 : AOI21_X1 port map( B1 => IN2(13), B2 => IN1(13), A => CTRL(0), ZN =>
n57);
U78 : OAI22_X1 port map( A1 => IN1(8), A2 => IN2(8), B1 => n2, B2 => n5, ZN
=> n6);
U79 : AOI21_X1 port map( B1 => IN2(8), B2 => IN1(8), A => CTRL(0), ZN => n5)
;
U81 : OAI22_X1 port map( A1 => IN1(6), A2 => IN2(6), B1 => n2, B2 => n9, ZN
=> n10);
U82 : AOI21_X1 port map( B1 => IN2(6), B2 => IN1(6), A => CTRL(0), ZN => n9)
;
U84 : OAI22_X1 port map( A1 => IN1(19), A2 => IN2(19), B1 => n169, B2 => n45
, ZN => n46);
U85 : AOI21_X1 port map( B1 => IN2(19), B2 => IN1(19), A => CTRL(0), ZN =>
n45);
U87 : OAI22_X1 port map( A1 => IN1(15), A2 => IN2(15), B1 => n2, B2 => n53,
ZN => n54);
U88 : AOI21_X1 port map( B1 => IN2(15), B2 => IN1(15), A => CTRL(0), ZN =>
n53);
U90 : AOI21_X1 port map( B1 => IN2(22), B2 => IN1(22), A => CTRL(0), ZN =>
n37);
U91 : OAI22_X1 port map( A1 => IN1(11), A2 => IN2(11), B1 => n2, B2 => n61,
ZN => n62);
U93 : AOI21_X1 port map( B1 => IN2(11), B2 => IN1(11), A => CTRL(0), ZN =>
n61);
U94 : OAI22_X1 port map( A1 => IN1(7), A2 => IN2(7), B1 => n2, B2 => n7, ZN
=> n8);
U95 : AOI21_X1 port map( B1 => IN2(7), B2 => IN1(7), A => CTRL(0), ZN => n7)
;
U96 : OAI22_X1 port map( A1 => IN1(9), A2 => IN2(9), B1 => n2, B2 => n3, ZN
=> n4);
U97 : AOI21_X1 port map( B1 => IN2(9), B2 => IN1(9), A => CTRL(0), ZN => n3)
;
U98 : OAI22_X1 port map( A1 => IN1(5), A2 => IN2(5), B1 => n169, B2 => n11,
ZN => n12);
U99 : AOI21_X1 port map( B1 => IN2(5), B2 => IN1(5), A => CTRL(0), ZN => n11
);
end SYN_Bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity shifter is
port( A : in std_logic_vector (31 downto 0); B : in std_logic_vector (4
downto 0); LOGIC_ARITH, LEFT_RIGHT : in std_logic; OUTPUT : out
std_logic_vector (31 downto 0));
end shifter;
architecture SYN_struct of shifter is
component AOI22_X1
port( A1, A2, B1, B2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component OR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component shift_thirdLevel
port( sel : in std_logic_vector (2 downto 0); A : in std_logic_vector
(38 downto 0); Y : out std_logic_vector (31 downto 0));
end component;
component shift_secondLevel
port( sel : in std_logic_vector (1 downto 0); mask00, mask08, mask16 :
in std_logic_vector (38 downto 0); Y : out std_logic_vector (38
downto 0));
end component;
component shift_firstLevel
port( A : in std_logic_vector (31 downto 0); sel : in std_logic_vector
(1 downto 0); mask00, mask08, mask16 : out std_logic_vector (38
downto 0));
end component;
signal s3_2_port, s3_1_port, s3_0_port, m0_38_port, m0_37_port, m0_36_port,
m0_35_port, m0_34_port, m0_33_port, m0_32_port, m0_31_port, m0_30_port,
m0_29_port, m0_28_port, m0_27_port, m0_26_port, m0_25_port, m0_24_port,
m0_23_port, m0_22_port, m0_21_port, m0_20_port, m0_19_port, m0_18_port,
m0_17_port, m0_16_port, m0_15_port, m0_14_port, m0_13_port, m0_12_port,
m0_11_port, m0_10_port, m0_9_port, m0_8_port, m0_7_port, m0_6_port,
m0_5_port, m0_4_port, m0_3_port, m0_2_port, m0_1_port, m0_0_port,
m8_38_port, m8_37_port, m8_36_port, m8_35_port, m8_34_port, m8_33_port,
m8_32_port, m8_31_port, m8_30_port, m8_29_port, m8_28_port, m8_27_port,
m8_26_port, m8_25_port, m8_24_port, m8_23_port, m8_22_port, m8_21_port,
m8_20_port, m8_19_port, m8_18_port, m8_17_port, m8_16_port, m8_15_port,
m8_14_port, m8_13_port, m8_12_port, m8_11_port, m8_10_port, m8_9_port,
m8_8_port, m8_7_port, m8_6_port, m8_5_port, m8_4_port, m8_3_port,
m8_2_port, m8_1_port, m8_0_port, m16_38_port, m16_37_port, m16_36_port,
m16_35_port, m16_34_port, m16_33_port, m16_32_port, m16_31_port,
m16_30_port, m16_29_port, m16_28_port, m16_27_port, m16_26_port,
m16_25_port, m16_24_port, m16_23_port, m16_15_port, m16_14_port,
m16_13_port, m16_12_port, m16_11_port, m16_10_port, m16_9_port,
m16_8_port, m16_7_port, m16_6_port, m16_5_port, m16_4_port, m16_3_port,
m16_2_port, m16_1_port, m16_0_port, y_38_port, y_37_port, y_36_port,
y_35_port, y_34_port, y_33_port, y_32_port, y_31_port, y_30_port,
y_29_port, y_28_port, y_27_port, y_26_port, y_25_port, y_24_port,
y_23_port, y_22_port, y_21_port, y_20_port, y_19_port, y_18_port,
y_17_port, y_16_port, y_15_port, y_14_port, y_13_port, y_12_port,
y_11_port, y_10_port, y_9_port, y_8_port, y_7_port, y_6_port, y_5_port,
y_4_port, y_3_port, y_2_port, y_1_port, y_0_port, n5, n7, n8, n9, n2, n3,
n4, n6, n10, n11, n12, n14 : std_logic;
begin
IL : shift_firstLevel port map( A(31) => A(31), A(30) => A(30), A(29) =>
A(29), A(28) => A(28), A(27) => A(27), A(26) =>
A(26), A(25) => A(25), A(24) => A(24), A(23) =>
A(23), A(22) => A(22), A(21) => A(21), A(20) =>
A(20), A(19) => A(19), A(18) => A(18), A(17) =>
A(17), A(16) => A(16), A(15) => A(15), A(14) =>
A(14), A(13) => A(13), A(12) => A(12), A(11) =>
A(11), A(10) => A(10), A(9) => A(9), A(8) => A(8),
A(7) => A(7), A(6) => A(6), A(5) => A(5), A(4) =>
A(4), A(3) => A(3), A(2) => A(2), A(1) => A(1), A(0)
=> A(0), sel(1) => LOGIC_ARITH, sel(0) => LEFT_RIGHT
, mask00(38) => m0_38_port, mask00(37) => m0_37_port
, mask00(36) => m0_36_port, mask00(35) => m0_35_port
, mask00(34) => m0_34_port, mask00(33) => m0_33_port
, mask00(32) => m0_32_port, mask00(31) => m0_31_port
, mask00(30) => m0_30_port, mask00(29) => m0_29_port
, mask00(28) => m0_28_port, mask00(27) => m0_27_port
, mask00(26) => m0_26_port, mask00(25) => m0_25_port
, mask00(24) => m0_24_port, mask00(23) => m0_23_port
, mask00(22) => m0_22_port, mask00(21) => m0_21_port
, mask00(20) => m0_20_port, mask00(19) => m0_19_port
, mask00(18) => m0_18_port, mask00(17) => m0_17_port
, mask00(16) => m0_16_port, mask00(15) => m0_15_port
, mask00(14) => m0_14_port, mask00(13) => m0_13_port
, mask00(12) => m0_12_port, mask00(11) => m0_11_port
, mask00(10) => m0_10_port, mask00(9) => m0_9_port,
mask00(8) => m0_8_port, mask00(7) => m0_7_port,
mask00(6) => m0_6_port, mask00(5) => m0_5_port,
mask00(4) => m0_4_port, mask00(3) => m0_3_port,
mask00(2) => m0_2_port, mask00(1) => m0_1_port,
mask00(0) => m0_0_port, mask08(38) => m8_38_port,
mask08(37) => m8_37_port, mask08(36) => m8_36_port,
mask08(35) => m8_35_port, mask08(34) => m8_34_port,
mask08(33) => m8_33_port, mask08(32) => m8_32_port,
mask08(31) => m8_31_port, mask08(30) => m8_30_port,
mask08(29) => m8_29_port, mask08(28) => m8_28_port,
mask08(27) => m8_27_port, mask08(26) => m8_26_port,
mask08(25) => m8_25_port, mask08(24) => m8_24_port,
mask08(23) => m8_23_port, mask08(22) => m8_22_port,
mask08(21) => m8_21_port, mask08(20) => m8_20_port,
mask08(19) => m8_19_port, mask08(18) => m8_18_port,
mask08(17) => m8_17_port, mask08(16) => m8_16_port,
mask08(15) => m8_15_port, mask08(14) => m8_14_port,
mask08(13) => m8_13_port, mask08(12) => m8_12_port,
mask08(11) => m8_11_port, mask08(10) => m8_10_port,
mask08(9) => m8_9_port, mask08(8) => m8_8_port,
mask08(7) => m8_7_port, mask08(6) => m8_6_port,
mask08(5) => m8_5_port, mask08(4) => m8_4_port,
mask08(3) => m8_3_port, mask08(2) => m8_2_port,
mask08(1) => m8_1_port, mask08(0) => m8_0_port,
mask16(38) => m16_38_port, mask16(37) => m16_37_port
, mask16(36) => m16_36_port, mask16(35) =>
m16_35_port, mask16(34) => m16_34_port, mask16(33)
=> m16_33_port, mask16(32) => m16_32_port,
mask16(31) => m16_31_port, mask16(30) => m16_30_port
, mask16(29) => m16_29_port, mask16(28) =>
m16_28_port, mask16(27) => m16_27_port, mask16(26)
=> m16_26_port, mask16(25) => m16_25_port,
mask16(24) => m16_24_port, mask16(23) => m16_23_port
, mask16(22) => n3, mask16(21) => n11, mask16(20) =>
n6, mask16(19) => n2, mask16(18) => n12, mask16(17)
=> n4, mask16(16) => n10, mask16(15) => m16_15_port,
mask16(14) => m16_14_port, mask16(13) => m16_13_port
, mask16(12) => m16_12_port, mask16(11) =>
m16_11_port, mask16(10) => m16_10_port, mask16(9) =>
m16_9_port, mask16(8) => m16_8_port, mask16(7) =>
m16_7_port, mask16(6) => m16_6_port, mask16(5) =>
m16_5_port, mask16(4) => m16_4_port, mask16(3) =>
m16_3_port, mask16(2) => m16_2_port, mask16(1) =>
m16_1_port, mask16(0) => m16_0_port);
IIL : shift_secondLevel port map( sel(1) => B(4), sel(0) => B(3), mask00(38)
=> m0_38_port, mask00(37) => m0_37_port, mask00(36)
=> m0_36_port, mask00(35) => m0_35_port, mask00(34)
=> m0_34_port, mask00(33) => m0_33_port, mask00(32)
=> m0_32_port, mask00(31) => m0_31_port, mask00(30)
=> m0_30_port, mask00(29) => m0_29_port, mask00(28)
=> m0_28_port, mask00(27) => m0_27_port, mask00(26)
=> m0_26_port, mask00(25) => m0_25_port, mask00(24)
=> m0_24_port, mask00(23) => m0_23_port, mask00(22)
=> m0_22_port, mask00(21) => m0_21_port, mask00(20)
=> m0_20_port, mask00(19) => m0_19_port, mask00(18)
=> m0_18_port, mask00(17) => m0_17_port, mask00(16)
=> m0_16_port, mask00(15) => m0_15_port, mask00(14)
=> m0_14_port, mask00(13) => m0_13_port, mask00(12)
=> m0_12_port, mask00(11) => m0_11_port, mask00(10)
=> m0_10_port, mask00(9) => m0_9_port, mask00(8) =>
m0_8_port, mask00(7) => m0_7_port, mask00(6) =>
m0_6_port, mask00(5) => m0_5_port, mask00(4) =>
m0_4_port, mask00(3) => m0_3_port, mask00(2) =>
m0_2_port, mask00(1) => m0_1_port, mask00(0) =>
m0_0_port, mask08(38) => m8_38_port, mask08(37) =>
m8_37_port, mask08(36) => m8_36_port, mask08(35) =>
m8_35_port, mask08(34) => m8_34_port, mask08(33) =>
m8_33_port, mask08(32) => m8_32_port, mask08(31) =>
m8_31_port, mask08(30) => m8_30_port, mask08(29) =>
m8_29_port, mask08(28) => m8_28_port, mask08(27) =>
m8_27_port, mask08(26) => m8_26_port, mask08(25) =>
m8_25_port, mask08(24) => m8_24_port, mask08(23) =>
m8_23_port, mask08(22) => m8_22_port, mask08(21) =>
m8_21_port, mask08(20) => m8_20_port, mask08(19) =>
m8_19_port, mask08(18) => m8_18_port, mask08(17) =>
m8_17_port, mask08(16) => m8_16_port, mask08(15) =>
m8_15_port, mask08(14) => m8_14_port, mask08(13) =>
m8_13_port, mask08(12) => m8_12_port, mask08(11) =>
m8_11_port, mask08(10) => m8_10_port, mask08(9) =>
m8_9_port, mask08(8) => m8_8_port, mask08(7) =>
m8_7_port, mask08(6) => m8_6_port, mask08(5) =>
m8_5_port, mask08(4) => m8_4_port, mask08(3) =>
m8_3_port, mask08(2) => m8_2_port, mask08(1) =>
m8_1_port, mask08(0) => m8_0_port, mask16(38) =>
m16_38_port, mask16(37) => m16_37_port, mask16(36)
=> m16_36_port, mask16(35) => m16_35_port,
mask16(34) => m16_34_port, mask16(33) => m16_33_port
, mask16(32) => m16_32_port, mask16(31) =>
m16_31_port, mask16(30) => m16_30_port, mask16(29)
=> m16_29_port, mask16(28) => m16_28_port,
mask16(27) => m16_27_port, mask16(26) => m16_26_port
, mask16(25) => m16_25_port, mask16(24) =>
m16_24_port, mask16(23) => m16_23_port, mask16(22)
=> n3, mask16(21) => n11, mask16(20) => n6,
mask16(19) => n2, mask16(18) => n12, mask16(17) =>
n4, mask16(16) => n10, mask16(15) => m16_15_port,
mask16(14) => m16_14_port, mask16(13) => m16_13_port
, mask16(12) => m16_12_port, mask16(11) =>
m16_11_port, mask16(10) => m16_10_port, mask16(9) =>
m16_9_port, mask16(8) => m16_8_port, mask16(7) =>
m16_7_port, mask16(6) => m16_6_port, mask16(5) =>
m16_5_port, mask16(4) => m16_4_port, mask16(3) =>
m16_3_port, mask16(2) => m16_2_port, mask16(1) =>
m16_1_port, mask16(0) => m16_0_port, Y(38) =>
y_38_port, Y(37) => y_37_port, Y(36) => y_36_port,
Y(35) => y_35_port, Y(34) => y_34_port, Y(33) =>
y_33_port, Y(32) => y_32_port, Y(31) => y_31_port,
Y(30) => y_30_port, Y(29) => y_29_port, Y(28) =>
y_28_port, Y(27) => y_27_port, Y(26) => y_26_port,
Y(25) => y_25_port, Y(24) => y_24_port, Y(23) =>
y_23_port, Y(22) => y_22_port, Y(21) => y_21_port,
Y(20) => y_20_port, Y(19) => y_19_port, Y(18) =>
y_18_port, Y(17) => y_17_port, Y(16) => y_16_port,
Y(15) => y_15_port, Y(14) => y_14_port, Y(13) =>
y_13_port, Y(12) => y_12_port, Y(11) => y_11_port,
Y(10) => y_10_port, Y(9) => y_9_port, Y(8) =>
y_8_port, Y(7) => y_7_port, Y(6) => y_6_port, Y(5)
=> y_5_port, Y(4) => y_4_port, Y(3) => y_3_port,
Y(2) => y_2_port, Y(1) => y_1_port, Y(0) => y_0_port
);
IIIL : shift_thirdLevel port map( sel(2) => s3_2_port, sel(1) => s3_1_port,
sel(0) => s3_0_port, A(38) => y_38_port, A(37) =>
y_37_port, A(36) => y_36_port, A(35) => y_35_port,
A(34) => y_34_port, A(33) => y_33_port, A(32) =>
y_32_port, A(31) => y_31_port, A(30) => y_30_port,
A(29) => y_29_port, A(28) => y_28_port, A(27) =>
y_27_port, A(26) => y_26_port, A(25) => y_25_port,
A(24) => y_24_port, A(23) => y_23_port, A(22) =>
y_22_port, A(21) => y_21_port, A(20) => y_20_port,
A(19) => y_19_port, A(18) => y_18_port, A(17) =>
y_17_port, A(16) => y_16_port, A(15) => y_15_port,
A(14) => y_14_port, A(13) => y_13_port, A(12) =>
y_12_port, A(11) => y_11_port, A(10) => y_10_port,
A(9) => y_9_port, A(8) => y_8_port, A(7) => y_7_port
, A(6) => y_6_port, A(5) => y_5_port, A(4) =>
y_4_port, A(3) => y_3_port, A(2) => y_2_port, A(1)
=> y_1_port, A(0) => y_0_port, Y(31) => OUTPUT(31),
Y(30) => OUTPUT(30), Y(29) => OUTPUT(29), Y(28) =>
OUTPUT(28), Y(27) => OUTPUT(27), Y(26) => OUTPUT(26)
, Y(25) => OUTPUT(25), Y(24) => OUTPUT(24), Y(23) =>
OUTPUT(23), Y(22) => OUTPUT(22), Y(21) => OUTPUT(21)
, Y(20) => OUTPUT(20), Y(19) => OUTPUT(19), Y(18) =>
OUTPUT(18), Y(17) => OUTPUT(17), Y(16) => OUTPUT(16)
, Y(15) => OUTPUT(15), Y(14) => OUTPUT(14), Y(13) =>
OUTPUT(13), Y(12) => OUTPUT(12), Y(11) => OUTPUT(11)
, Y(10) => OUTPUT(10), Y(9) => OUTPUT(9), Y(8) =>
OUTPUT(8), Y(7) => OUTPUT(7), Y(6) => OUTPUT(6),
Y(5) => OUTPUT(5), Y(4) => OUTPUT(4), Y(3) =>
OUTPUT(3), Y(2) => OUTPUT(2), Y(1) => OUTPUT(1),
Y(0) => OUTPUT(0));
U1 : AOI22_X1 port map( A1 => B(2), A2 => n5, B1 => n14, B2 => n7, ZN =>
s3_2_port);
U8 : OR2_X1 port map( A1 => LOGIC_ARITH, A2 => LEFT_RIGHT, ZN => n5);
U2 : INV_X1 port map( A => B(2), ZN => n7);
U3 : INV_X1 port map( A => B(1), ZN => n8);
U4 : INV_X1 port map( A => B(0), ZN => n9);
U5 : INV_X1 port map( A => LEFT_RIGHT, ZN => n14);
U6 : AOI22_X1 port map( A1 => B(0), A2 => n5, B1 => n14, B2 => n9, ZN =>
s3_0_port);
U7 : AOI22_X1 port map( A1 => B(1), A2 => n5, B1 => n14, B2 => n8, ZN =>
s3_1_port);
end SYN_struct;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity comparator_M32 is
port( C, V : in std_logic; SUM : in std_logic_vector (31 downto 0); sel :
in std_logic_vector (2 downto 0); sign : in std_logic; S : out
std_logic);
end comparator_M32;
architecture SYN_BEHAVIORAL of comparator_M32 is
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component OAI211_X1
port( C1, C2, A, B : in std_logic; ZN : out std_logic);
end component;
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component OR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component OAI22_X1
port( A1, A2, B1, B2 : in std_logic; ZN : out std_logic);
end component;
component CLKBUF_X1
port( A : in std_logic; Z : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component AND4_X1
port( A1, A2, A3, A4 : in std_logic; ZN : out std_logic);
end component;
component AND3_X1
port( A1, A2, A3 : in std_logic; ZN : out std_logic);
end component;
component NOR4_X1
port( A1, A2, A3, A4 : in std_logic; ZN : out std_logic);
end component;
component NOR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component OR3_X1
port( A1, A2, A3 : in std_logic; ZN : out std_logic);
end component;
signal n3, n11, n12, n23, n22, n21, n20, n19, n18, n17, n16, n25, n26, n27,
n28, n29, n30, n31, n32, n33, n34, n35, n36, n37, n38, n39, n40, n41 :
std_logic;
begin
U21 : NOR2_X1 port map( A1 => sel(2), A2 => sel(1), ZN => n3);
U1 : INV_X1 port map( A => sel(2), ZN => n36);
U2 : OR2_X1 port map( A1 => sel(0), A2 => sel(2), ZN => n25);
U3 : NAND2_X1 port map( A1 => n38, A2 => n25, ZN => n34);
U4 : OR3_X1 port map( A1 => SUM(4), A2 => SUM(5), A3 => SUM(3), ZN => n29);
U5 : NOR4_X1 port map( A1 => SUM(9), A2 => SUM(8), A3 => SUM(7), A4 =>
SUM(6), ZN => n17);
U6 : NOR2_X1 port map( A1 => SUM(31), A2 => n29, ZN => n16);
U7 : NOR4_X1 port map( A1 => SUM(30), A2 => SUM(2), A3 => SUM(29), A4 =>
SUM(28), ZN => n19);
U8 : NOR4_X1 port map( A1 => SUM(27), A2 => SUM(26), A3 => SUM(25), A4 =>
SUM(24), ZN => n18);
U9 : AND2_X1 port map( A1 => n16, A2 => n17, ZN => n28);
U10 : NOR4_X1 port map( A1 => SUM(17), A2 => SUM(19), A3 => SUM(18), A4 =>
SUM(1), ZN => n20);
U11 : NOR4_X1 port map( A1 => SUM(12), A2 => SUM(11), A3 => SUM(10), A4 =>
SUM(0), ZN => n22);
U12 : NOR4_X1 port map( A1 => SUM(16), A2 => SUM(15), A3 => SUM(14), A4 =>
SUM(13), ZN => n23);
U13 : NOR4_X1 port map( A1 => SUM(23), A2 => SUM(22), A3 => SUM(20), A4 =>
SUM(21), ZN => n21);
U14 : AND3_X1 port map( A1 => n28, A2 => n18, A3 => n19, ZN => n27);
U15 : AND4_X1 port map( A1 => n21, A2 => n23, A3 => n22, A4 => n20, ZN =>
n26);
U16 : NAND2_X1 port map( A1 => n26, A2 => n27, ZN => n30);
U17 : XNOR2_X1 port map( A => n30, B => n40, ZN => n38);
U18 : OAI21_X1 port map( B1 => n31, B2 => sel(0), A => n3, ZN => n33);
U19 : CLKBUF_X1 port map( A => n30, Z => n31);
U20 : OAI22_X1 port map( A1 => n37, A2 => n3, B1 => n32, B2 => n33, ZN => S)
;
U22 : NAND2_X1 port map( A1 => n11, A2 => n41, ZN => n32);
U23 : NAND2_X1 port map( A1 => n32, A2 => n36, ZN => n35);
U24 : AND2_X1 port map( A1 => n34, A2 => n35, ZN => n37);
U25 : OR2_X1 port map( A1 => C, A2 => sign, ZN => n41);
U26 : INV_X1 port map( A => n39, ZN => n40);
U27 : OAI21_X1 port map( B1 => sel(0), B2 => sel(1), A => sel(2), ZN => n39)
;
U28 : OAI211_X1 port map( C1 => SUM(31), C2 => V, A => n12, B => sign, ZN =>
n11);
U29 : NAND2_X1 port map( A1 => SUM(31), A2 => V, ZN => n12);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity p4add_N32_logN5 is
port( A, B : in std_logic_vector (31 downto 0); Cin, sign : in std_logic;
S : out std_logic_vector (31 downto 0); Cout : out std_logic);
end p4add_N32_logN5;
architecture SYN_STRUCTURAL of p4add_N32_logN5 is
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component CLKBUF_X1
port( A : in std_logic; Z : out std_logic);
end component;
component BUF_X1
port( A : in std_logic; Z : out std_logic);
end component;
component sum_gen_N32
port( A, B : in std_logic_vector (31 downto 0); Cin : in
std_logic_vector (8 downto 0); S : out std_logic_vector (31 downto
0));
end component;
component carry_tree_N32_logN5
port( A, B : in std_logic_vector (31 downto 0); Cin : in std_logic;
Cout : out std_logic_vector (7 downto 0));
end component;
component xor_gen_N32
port( A : in std_logic_vector (31 downto 0); B : in std_logic; S : out
std_logic_vector (31 downto 0));
end component;
signal new_B_31_port, new_B_30_port, new_B_29_port, new_B_28_port,
new_B_27_port, new_B_26_port, new_B_25_port, new_B_24_port, new_B_23_port
, new_B_22_port, new_B_21_port, new_B_20_port, new_B_18_port,
new_B_16_port, new_B_14_port, new_B_13_port, new_B_12_port, new_B_11_port
, new_B_10_port, new_B_9_port, new_B_8_port, new_B_7_port, new_B_6_port,
new_B_5_port, new_B_4_port, new_B_3_port, new_B_2_port, new_B_1_port,
new_B_0_port, carry_pro_7_port, carry_pro_6_port, carry_pro_5_port,
carry_pro_4_port, carry_pro_3_port, carry_pro_2_port, carry_pro_1_port,
n1, n2, n3, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16, n17,
n18, n19, n20, n21, n22, n23, n24, n25, n26 : std_logic;
begin
xor32 : xor_gen_N32 port map( A(31) => B(31), A(30) => B(30), A(29) => B(29)
, A(28) => B(28), A(27) => B(27), A(26) => B(26),
A(25) => B(25), A(24) => B(24), A(23) => B(23),
A(22) => B(22), A(21) => B(21), A(20) => B(20),
A(19) => B(19), A(18) => B(18), A(17) => B(17),
A(16) => B(16), A(15) => B(15), A(14) => B(14),
A(13) => B(13), A(12) => B(12), A(11) => B(11),
A(10) => B(10), A(9) => B(9), A(8) => B(8), A(7) =>
B(7), A(6) => B(6), A(5) => B(5), A(4) => B(4), A(3)
=> B(3), A(2) => B(2), A(1) => B(1), A(0) => B(0), B
=> sign, S(31) => new_B_31_port, S(30) =>
new_B_30_port, S(29) => new_B_29_port, S(28) =>
new_B_28_port, S(27) => new_B_27_port, S(26) =>
new_B_26_port, S(25) => new_B_25_port, S(24) =>
new_B_24_port, S(23) => new_B_23_port, S(22) =>
new_B_22_port, S(21) => new_B_21_port, S(20) =>
new_B_20_port, S(19) => n13, S(18) => new_B_18_port,
S(17) => n9, S(16) => new_B_16_port, S(15) => n3,
S(14) => new_B_14_port, S(13) => new_B_13_port,
S(12) => new_B_12_port, S(11) => new_B_11_port,
S(10) => new_B_10_port, S(9) => new_B_9_port, S(8)
=> new_B_8_port, S(7) => new_B_7_port, S(6) =>
new_B_6_port, S(5) => new_B_5_port, S(4) =>
new_B_4_port, S(3) => new_B_3_port, S(2) =>
new_B_2_port, S(1) => new_B_1_port, S(0) =>
new_B_0_port);
ct : carry_tree_N32_logN5 port map( A(31) => A(31), A(30) => A(30), A(29) =>
A(29), A(28) => A(28), A(27) => A(27), A(26) =>
A(26), A(25) => A(25), A(24) => A(24), A(23) =>
A(23), A(22) => A(22), A(21) => A(21), A(20) =>
A(20), A(19) => A(19), A(18) => A(18), A(17) =>
A(17), A(16) => A(16), A(15) => A(15), A(14) =>
A(14), A(13) => A(13), A(12) => A(12), A(11) =>
A(11), A(10) => A(10), A(9) => A(9), A(8) => A(8),
A(7) => A(7), A(6) => A(6), A(5) => A(5), A(4) =>
A(4), A(3) => A(3), A(2) => A(2), A(1) => A(1), A(0)
=> A(0), B(31) => new_B_31_port, B(30) =>
new_B_30_port, B(29) => new_B_29_port, B(28) =>
new_B_28_port, B(27) => new_B_27_port, B(26) =>
new_B_26_port, B(25) => new_B_25_port, B(24) =>
new_B_24_port, B(23) => new_B_23_port, B(22) =>
new_B_22_port, B(21) => new_B_21_port, B(20) =>
new_B_20_port, B(19) => n13, B(18) => new_B_18_port,
B(17) => n9, B(16) => new_B_16_port, B(15) => n3,
B(14) => new_B_14_port, B(13) => new_B_13_port,
B(12) => new_B_12_port, B(11) => new_B_11_port,
B(10) => new_B_10_port, B(9) => new_B_9_port, B(8)
=> new_B_8_port, B(7) => new_B_7_port, B(6) =>
new_B_6_port, B(5) => new_B_5_port, B(4) =>
new_B_4_port, B(3) => new_B_3_port, B(2) =>
new_B_2_port, B(1) => new_B_1_port, B(0) =>
new_B_0_port, Cin => n20, Cout(7) => Cout, Cout(6)
=> carry_pro_7_port, Cout(5) => carry_pro_6_port,
Cout(4) => carry_pro_5_port, Cout(3) =>
carry_pro_4_port, Cout(2) => carry_pro_3_port,
Cout(1) => carry_pro_2_port, Cout(0) =>
carry_pro_1_port);
add : sum_gen_N32 port map( A(31) => A(31), A(30) => A(30), A(29) => A(29),
A(28) => A(28), A(27) => A(27), A(26) => A(26),
A(25) => A(25), A(24) => A(24), A(23) => A(23),
A(22) => A(22), A(21) => A(21), A(20) => A(20),
A(19) => A(19), A(18) => A(18), A(17) => A(17),
A(16) => A(16), A(15) => A(15), A(14) => A(14),
A(13) => A(13), A(12) => A(12), A(11) => A(11),
A(10) => A(10), A(9) => A(9), A(8) => A(8), A(7) =>
A(7), A(6) => A(6), A(5) => A(5), A(4) => A(4), A(3)
=> A(3), A(2) => A(2), A(1) => A(1), A(0) => A(0),
B(31) => new_B_31_port, B(30) => new_B_30_port,
B(29) => new_B_29_port, B(28) => new_B_28_port,
B(27) => new_B_27_port, B(26) => n1, B(25) => n14,
B(24) => new_B_24_port, B(23) => new_B_23_port,
B(22) => new_B_22_port, B(21) => new_B_21_port,
B(20) => new_B_20_port, B(19) => n13, B(18) => n8,
B(17) => n22, B(16) => new_B_16_port, B(15) => n3,
B(14) => n16, B(13) => n6, B(12) => new_B_12_port,
B(11) => n2, B(10) => n17, B(9) => n15, B(8) => n5,
B(7) => n25, B(6) => new_B_6_port, B(5) => n19, B(4)
=> n23, B(3) => n12, B(2) => n11, B(1) => n24, B(0)
=> n10, Cin(8) => n26, Cin(7) => carry_pro_7_port,
Cin(6) => carry_pro_6_port, Cin(5) =>
carry_pro_5_port, Cin(4) => carry_pro_4_port, Cin(3)
=> carry_pro_3_port, Cin(2) => carry_pro_2_port,
Cin(1) => carry_pro_1_port, Cin(0) => n20, S(31) =>
S(31), S(30) => S(30), S(29) => S(29), S(28) =>
S(28), S(27) => S(27), S(26) => S(26), S(25) =>
S(25), S(24) => S(24), S(23) => S(23), S(22) =>
S(22), S(21) => S(21), S(20) => S(20), S(19) =>
S(19), S(18) => S(18), S(17) => S(17), S(16) =>
S(16), S(15) => S(15), S(14) => S(14), S(13) =>
S(13), S(12) => S(12), S(11) => S(11), S(10) =>
S(10), S(9) => S(9), S(8) => S(8), S(7) => S(7),
S(6) => S(6), S(5) => S(5), S(4) => S(4), S(3) =>
S(3), S(2) => S(2), S(1) => S(1), S(0) => S(0));
U1 : BUF_X1 port map( A => new_B_26_port, Z => n1);
U2 : CLKBUF_X1 port map( A => new_B_11_port, Z => n2);
U3 : INV_X1 port map( A => new_B_1_port, ZN => n7);
U4 : BUF_X1 port map( A => new_B_14_port, Z => n16);
U5 : BUF_X1 port map( A => new_B_4_port, Z => n23);
U6 : BUF_X1 port map( A => sign, Z => n20);
U7 : BUF_X1 port map( A => new_B_8_port, Z => n5);
U8 : BUF_X1 port map( A => new_B_13_port, Z => n6);
U9 : CLKBUF_X1 port map( A => new_B_0_port, Z => n10);
U10 : CLKBUF_X1 port map( A => new_B_18_port, Z => n8);
U11 : BUF_X1 port map( A => new_B_2_port, Z => n11);
U12 : CLKBUF_X1 port map( A => new_B_3_port, Z => n12);
U13 : CLKBUF_X1 port map( A => new_B_25_port, Z => n14);
U14 : CLKBUF_X1 port map( A => new_B_7_port, Z => n25);
U15 : INV_X1 port map( A => n18, ZN => n19);
U16 : INV_X1 port map( A => new_B_5_port, ZN => n18);
U17 : CLKBUF_X1 port map( A => new_B_9_port, Z => n15);
U18 : CLKBUF_X1 port map( A => new_B_10_port, Z => n17);
U19 : INV_X1 port map( A => n21, ZN => n22);
U20 : INV_X1 port map( A => n9, ZN => n21);
U21 : INV_X1 port map( A => n7, ZN => n24);
n26 <= '0';
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity simple_booth_add_ext_N16 is
port( Clock, Reset, sign, enable : in std_logic; valid : out std_logic; A,
B : in std_logic_vector (15 downto 0); A_to_add, B_to_add : out
std_logic_vector (31 downto 0); sign_to_add : out std_logic;
final_out : out std_logic_vector (31 downto 0); ACC_from_add : in
std_logic_vector (31 downto 0));
end simple_booth_add_ext_N16;
architecture SYN_struct of simple_booth_add_ext_N16 is
component NOR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component OR2_X4
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component NOR3_X1
port( A1, A2, A3 : in std_logic; ZN : out std_logic);
end component;
component BUF_X8
port( A : in std_logic; Z : out std_logic);
end component;
component OAI22_X1
port( A1, A2, B1, B2 : in std_logic; ZN : out std_logic);
end component;
component OAI221_X1
port( B1, B2, C1, C2, A : in std_logic; ZN : out std_logic);
end component;
component MUX2_X1
port( A, B, S : in std_logic; Z : out std_logic);
end component;
component OAI211_X1
port( C1, C2, A, B : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component DFFS_X1
port( D, CK, SN : in std_logic; Q, QN : out std_logic);
end component;
component NAND3_X1
port( A1, A2, A3 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component AND3_X1
port( A1, A2, A3 : in std_logic; ZN : out std_logic);
end component;
component ff32_en_SIZE32
port( D : in std_logic_vector (31 downto 0); en, clk, rst : in std_logic
; Q : out std_logic_vector (31 downto 0));
end component;
component mux21_1
port( IN0, IN1 : in std_logic_vector (31 downto 0); CTRL : in std_logic;
OUT1 : out std_logic_vector (31 downto 0));
end component;
component piso_r_2_N32
port( Clock, ALOAD : in std_logic; D : in std_logic_vector (31 downto 0)
; SO : out std_logic_vector (31 downto 0));
end component;
component shift_N9_1
port( Clock, ALOAD : in std_logic; D : in std_logic_vector (8 downto 0);
SO : out std_logic);
end component;
component shift_N9_2
port( Clock, ALOAD : in std_logic; D : in std_logic_vector (8 downto 0);
SO : out std_logic);
end component;
component shift_N9_0
port( Clock, ALOAD : in std_logic; D : in std_logic_vector (8 downto 0);
SO : out std_logic);
end component;
component booth_encoder_1
port( B_in : in std_logic_vector (2 downto 0); A_out : out
std_logic_vector (2 downto 0));
end component;
component booth_encoder_2
port( B_in : in std_logic_vector (2 downto 0); A_out : out
std_logic_vector (2 downto 0));
end component;
component booth_encoder_3
port( B_in : in std_logic_vector (2 downto 0); A_out : out
std_logic_vector (2 downto 0));
end component;
component booth_encoder_4
port( B_in : in std_logic_vector (2 downto 0); A_out : out
std_logic_vector (2 downto 0));
end component;
component booth_encoder_5
port( B_in : in std_logic_vector (2 downto 0); A_out : out
std_logic_vector (2 downto 0));
end component;
component booth_encoder_6
port( B_in : in std_logic_vector (2 downto 0); A_out : out
std_logic_vector (2 downto 0));
end component;
component booth_encoder_7
port( B_in : in std_logic_vector (2 downto 0); A_out : out
std_logic_vector (2 downto 0));
end component;
component booth_encoder_8
port( B_in : in std_logic_vector (2 downto 0); A_out : out
std_logic_vector (2 downto 0));
end component;
component booth_encoder_0
port( B_in : in std_logic_vector (2 downto 0); A_out : out
std_logic_vector (2 downto 0));
end component;
component DFFR_X1
port( D, CK, RN : in std_logic; Q, QN : out std_logic);
end component;
signal X_Logic0_port, valid_port, A_to_add_31_port, A_to_add_30_port,
A_to_add_29_port, A_to_add_28_port, A_to_add_27_port, A_to_add_26_port,
A_to_add_25_port, A_to_add_24_port, A_to_add_23_port, A_to_add_22_port,
A_to_add_21_port, A_to_add_20_port, A_to_add_19_port, A_to_add_18_port,
A_to_add_17_port, A_to_add_16_port, A_to_add_15_port, A_to_add_14_port,
A_to_add_13_port, A_to_add_12_port, A_to_add_11_port, A_to_add_10_port,
A_to_add_9_port, A_to_add_8_port, A_to_add_7_port, A_to_add_6_port,
A_to_add_5_port, A_to_add_4_port, A_to_add_3_port, A_to_add_2_port,
A_to_add_1_port, A_to_add_0_port, enc_N2_in_2_port, piso_0_in_8_port,
piso_0_in_7_port, piso_0_in_6_port, piso_0_in_5_port, piso_0_in_4_port,
piso_0_in_3_port, piso_0_in_2_port, piso_0_in_1_port, piso_0_in_0_port,
piso_1_in_8_port, piso_1_in_7_port, piso_1_in_6_port, piso_1_in_5_port,
piso_1_in_4_port, piso_1_in_3_port, piso_1_in_2_port, piso_1_in_1_port,
piso_1_in_0_port, piso_2_in_8_port, piso_2_in_7_port, piso_2_in_6_port,
piso_2_in_5_port, piso_2_in_4_port, piso_2_in_3_port, piso_2_in_2_port,
piso_2_in_1_port, piso_2_in_0_port, load, extend_vector_15_port,
A_to_mux_31_port, A_to_mux_30_port, A_to_mux_29_port, A_to_mux_28_port,
A_to_mux_27_port, A_to_mux_26_port, A_to_mux_25_port, A_to_mux_24_port,
A_to_mux_23_port, A_to_mux_22_port, A_to_mux_21_port, A_to_mux_20_port,
A_to_mux_19_port, A_to_mux_18_port, A_to_mux_17_port, A_to_mux_16_port,
A_to_mux_15_port, A_to_mux_14_port, A_to_mux_13_port, A_to_mux_12_port,
A_to_mux_11_port, A_to_mux_10_port, A_to_mux_9_port, A_to_mux_8_port,
A_to_mux_7_port, A_to_mux_6_port, A_to_mux_5_port, A_to_mux_4_port,
A_to_mux_3_port, A_to_mux_2_port, A_to_mux_1_port, A_to_mux_0_port,
input_mux_sel_2_port, input_mux_sel_0, next_accumulate_31_port,
next_accumulate_30_port, next_accumulate_29_port, next_accumulate_28_port
, next_accumulate_27_port, next_accumulate_26_port,
next_accumulate_25_port, next_accumulate_24_port, next_accumulate_23_port
, next_accumulate_22_port, next_accumulate_21_port,
next_accumulate_20_port, next_accumulate_19_port, next_accumulate_18_port
, next_accumulate_17_port, next_accumulate_16_port,
next_accumulate_15_port, next_accumulate_14_port, next_accumulate_13_port
, next_accumulate_12_port, next_accumulate_11_port,
next_accumulate_10_port, next_accumulate_9_port, next_accumulate_8_port,
next_accumulate_7_port, next_accumulate_6_port, next_accumulate_5_port,
next_accumulate_4_port, next_accumulate_3_port, next_accumulate_2_port,
next_accumulate_1_port, next_accumulate_0_port, reg_enable, count_4_port,
count_3_port, count_1_port, count_0_port, N21, N23, N24, n49, n50, n51,
n52, n54, n11, n12, n13, net549699, n38, n39, n40, n41, n42, n43, n44,
n45, n46, n47, n48, n55, n56, n57, n58, n59, n60, n61, n63, n64, n65, n66
, n67, n68, n69, n70, n71, n72, n73, n74, n75, n76, n77, n79, n81, n82,
sub_213_n3, sub_213_n2, n14, n15, n16, n17, n18, n22, n23_port, net561327
: std_logic;
begin
valid <= valid_port;
A_to_add <= ( A_to_add_31_port, A_to_add_30_port, A_to_add_29_port,
A_to_add_28_port, A_to_add_27_port, A_to_add_26_port, A_to_add_25_port,
A_to_add_24_port, A_to_add_23_port, A_to_add_22_port, A_to_add_21_port,
A_to_add_20_port, A_to_add_19_port, A_to_add_18_port, A_to_add_17_port,
A_to_add_16_port, A_to_add_15_port, A_to_add_14_port, A_to_add_13_port,
A_to_add_12_port, A_to_add_11_port, A_to_add_10_port, A_to_add_9_port,
A_to_add_8_port, A_to_add_7_port, A_to_add_6_port, A_to_add_5_port,
A_to_add_4_port, A_to_add_3_port, A_to_add_2_port, A_to_add_1_port,
A_to_add_0_port );
X_Logic0_port <= '0';
count_reg_1_inst : DFFR_X1 port map( D => n51, CK => Clock, RN => n23_port,
Q => count_1_port, QN => n13);
count_reg_2_inst : DFFR_X1 port map( D => n50, CK => Clock, RN => n23_port,
Q => net561327, QN => n11);
count_reg_4_inst : DFFR_X1 port map( D => n49, CK => Clock, RN => n23_port,
Q => count_4_port, QN => n12);
U85 : MUX2_X1 port map( A => A_to_add_9_port, B => ACC_from_add(9), S =>
input_mux_sel_2_port, Z => final_out(9));
U86 : MUX2_X1 port map( A => A_to_add_8_port, B => ACC_from_add(8), S =>
input_mux_sel_2_port, Z => final_out(8));
U87 : MUX2_X1 port map( A => A_to_add_7_port, B => ACC_from_add(7), S =>
input_mux_sel_2_port, Z => final_out(7));
U88 : MUX2_X1 port map( A => A_to_add_6_port, B => ACC_from_add(6), S =>
input_mux_sel_2_port, Z => final_out(6));
U89 : MUX2_X1 port map( A => A_to_add_5_port, B => ACC_from_add(5), S =>
input_mux_sel_2_port, Z => final_out(5));
U90 : MUX2_X1 port map( A => A_to_add_4_port, B => ACC_from_add(4), S =>
input_mux_sel_2_port, Z => final_out(4));
U91 : MUX2_X1 port map( A => A_to_add_3_port, B => ACC_from_add(3), S =>
input_mux_sel_2_port, Z => final_out(3));
U92 : MUX2_X1 port map( A => A_to_add_31_port, B => ACC_from_add(31), S =>
input_mux_sel_2_port, Z => final_out(31));
U93 : MUX2_X1 port map( A => A_to_add_30_port, B => ACC_from_add(30), S =>
input_mux_sel_2_port, Z => final_out(30));
U94 : MUX2_X1 port map( A => A_to_add_2_port, B => ACC_from_add(2), S =>
input_mux_sel_2_port, Z => final_out(2));
U95 : MUX2_X1 port map( A => A_to_add_29_port, B => ACC_from_add(29), S =>
input_mux_sel_2_port, Z => final_out(29));
U96 : MUX2_X1 port map( A => A_to_add_28_port, B => ACC_from_add(28), S =>
input_mux_sel_2_port, Z => final_out(28));
U97 : MUX2_X1 port map( A => A_to_add_27_port, B => ACC_from_add(27), S =>
input_mux_sel_2_port, Z => final_out(27));
U98 : MUX2_X1 port map( A => A_to_add_26_port, B => ACC_from_add(26), S =>
input_mux_sel_2_port, Z => final_out(26));
U99 : MUX2_X1 port map( A => A_to_add_25_port, B => ACC_from_add(25), S =>
input_mux_sel_2_port, Z => final_out(25));
U100 : MUX2_X1 port map( A => A_to_add_24_port, B => ACC_from_add(24), S =>
input_mux_sel_2_port, Z => final_out(24));
U101 : MUX2_X1 port map( A => A_to_add_23_port, B => ACC_from_add(23), S =>
input_mux_sel_2_port, Z => final_out(23));
U102 : MUX2_X1 port map( A => A_to_add_22_port, B => ACC_from_add(22), S =>
input_mux_sel_2_port, Z => final_out(22));
U103 : MUX2_X1 port map( A => A_to_add_21_port, B => ACC_from_add(21), S =>
input_mux_sel_2_port, Z => final_out(21));
U104 : MUX2_X1 port map( A => A_to_add_20_port, B => ACC_from_add(20), S =>
input_mux_sel_2_port, Z => final_out(20));
U105 : MUX2_X1 port map( A => A_to_add_1_port, B => ACC_from_add(1), S =>
input_mux_sel_2_port, Z => final_out(1));
U106 : MUX2_X1 port map( A => A_to_add_19_port, B => ACC_from_add(19), S =>
input_mux_sel_2_port, Z => final_out(19));
U107 : MUX2_X1 port map( A => A_to_add_18_port, B => ACC_from_add(18), S =>
input_mux_sel_2_port, Z => final_out(18));
U108 : MUX2_X1 port map( A => A_to_add_17_port, B => ACC_from_add(17), S =>
input_mux_sel_2_port, Z => final_out(17));
U109 : MUX2_X1 port map( A => A_to_add_16_port, B => ACC_from_add(16), S =>
input_mux_sel_2_port, Z => final_out(16));
U110 : MUX2_X1 port map( A => A_to_add_15_port, B => ACC_from_add(15), S =>
input_mux_sel_2_port, Z => final_out(15));
U111 : MUX2_X1 port map( A => A_to_add_14_port, B => ACC_from_add(14), S =>
input_mux_sel_2_port, Z => final_out(14));
U112 : MUX2_X1 port map( A => A_to_add_13_port, B => ACC_from_add(13), S =>
input_mux_sel_2_port, Z => final_out(13));
U113 : MUX2_X1 port map( A => A_to_add_12_port, B => ACC_from_add(12), S =>
input_mux_sel_2_port, Z => final_out(12));
U114 : MUX2_X1 port map( A => A_to_add_11_port, B => ACC_from_add(11), S =>
input_mux_sel_2_port, Z => final_out(11));
U115 : MUX2_X1 port map( A => A_to_add_10_port, B => ACC_from_add(10), S =>
input_mux_sel_2_port, Z => final_out(10));
encod_0_0 : booth_encoder_0 port map( B_in(2) => B(1), B_in(1) => B(0),
B_in(0) => X_Logic0_port, A_out(2) =>
piso_2_in_0_port, A_out(1) => piso_1_in_0_port,
A_out(0) => piso_0_in_0_port);
encod_i_1 : booth_encoder_8 port map( B_in(2) => B(3), B_in(1) => B(2),
B_in(0) => B(1), A_out(2) => piso_2_in_1_port,
A_out(1) => piso_1_in_1_port, A_out(0) =>
piso_0_in_1_port);
encod_i_2 : booth_encoder_7 port map( B_in(2) => B(5), B_in(1) => B(4),
B_in(0) => B(3), A_out(2) => piso_2_in_2_port,
A_out(1) => piso_1_in_2_port, A_out(0) =>
piso_0_in_2_port);
encod_i_3 : booth_encoder_6 port map( B_in(2) => B(7), B_in(1) => B(6),
B_in(0) => B(5), A_out(2) => piso_2_in_3_port,
A_out(1) => piso_1_in_3_port, A_out(0) =>
piso_0_in_3_port);
encod_i_4 : booth_encoder_5 port map( B_in(2) => B(9), B_in(1) => B(8),
B_in(0) => B(7), A_out(2) => piso_2_in_4_port,
A_out(1) => piso_1_in_4_port, A_out(0) =>
piso_0_in_4_port);
encod_i_5 : booth_encoder_4 port map( B_in(2) => B(11), B_in(1) => B(10),
B_in(0) => B(9), A_out(2) => piso_2_in_5_port,
A_out(1) => piso_1_in_5_port, A_out(0) =>
piso_0_in_5_port);
encod_i_6 : booth_encoder_3 port map( B_in(2) => B(13), B_in(1) => B(12),
B_in(0) => B(11), A_out(2) => piso_2_in_6_port,
A_out(1) => piso_1_in_6_port, A_out(0) =>
piso_0_in_6_port);
encod_i_7 : booth_encoder_2 port map( B_in(2) => B(15), B_in(1) => B(14),
B_in(0) => B(13), A_out(2) => piso_2_in_7_port,
A_out(1) => piso_1_in_7_port, A_out(0) =>
piso_0_in_7_port);
encod_i_8 : booth_encoder_1 port map( B_in(2) => enc_N2_in_2_port, B_in(1)
=> enc_N2_in_2_port, B_in(0) => B(15), A_out(2) =>
piso_2_in_8_port, A_out(1) => piso_1_in_8_port,
A_out(0) => piso_0_in_8_port);
piso_0 : shift_N9_0 port map( Clock => Clock, ALOAD => n22, D(8) =>
piso_0_in_8_port, D(7) => piso_0_in_7_port, D(6) =>
piso_0_in_6_port, D(5) => piso_0_in_5_port, D(4) =>
piso_0_in_4_port, D(3) => piso_0_in_3_port, D(2) =>
piso_0_in_2_port, D(1) => piso_0_in_1_port, D(0) =>
piso_0_in_0_port, SO => input_mux_sel_0);
piso_1 : shift_N9_2 port map( Clock => Clock, ALOAD => n22, D(8) =>
piso_1_in_8_port, D(7) => piso_1_in_7_port, D(6) =>
piso_1_in_6_port, D(5) => piso_1_in_5_port, D(4) =>
piso_1_in_4_port, D(3) => piso_1_in_3_port, D(2) =>
piso_1_in_2_port, D(1) => piso_1_in_1_port, D(0) =>
piso_1_in_0_port, SO => sign_to_add);
piso_2 : shift_N9_1 port map( Clock => Clock, ALOAD => n22, D(8) =>
piso_2_in_8_port, D(7) => piso_2_in_7_port, D(6) =>
piso_2_in_6_port, D(5) => piso_2_in_5_port, D(4) =>
piso_2_in_4_port, D(3) => piso_2_in_3_port, D(2) =>
piso_2_in_2_port, D(1) => piso_2_in_1_port, D(0) =>
piso_2_in_0_port, SO => input_mux_sel_2_port);
A_reg : piso_r_2_N32 port map( Clock => Clock, ALOAD => n22, D(31) =>
extend_vector_15_port, D(30) =>
extend_vector_15_port, D(29) =>
extend_vector_15_port, D(28) =>
extend_vector_15_port, D(27) =>
extend_vector_15_port, D(26) =>
extend_vector_15_port, D(25) =>
extend_vector_15_port, D(24) =>
extend_vector_15_port, D(23) =>
extend_vector_15_port, D(22) =>
extend_vector_15_port, D(21) =>
extend_vector_15_port, D(20) =>
extend_vector_15_port, D(19) =>
extend_vector_15_port, D(18) =>
extend_vector_15_port, D(17) =>
extend_vector_15_port, D(16) =>
extend_vector_15_port, D(15) => A(15), D(14) =>
A(14), D(13) => A(13), D(12) => A(12), D(11) =>
A(11), D(10) => A(10), D(9) => A(9), D(8) => A(8),
D(7) => A(7), D(6) => A(6), D(5) => A(5), D(4) =>
A(4), D(3) => A(3), D(2) => A(2), D(1) => A(1), D(0)
=> A(0), SO(31) => A_to_mux_31_port, SO(30) =>
A_to_mux_30_port, SO(29) => A_to_mux_29_port, SO(28)
=> A_to_mux_28_port, SO(27) => A_to_mux_27_port,
SO(26) => A_to_mux_26_port, SO(25) =>
A_to_mux_25_port, SO(24) => A_to_mux_24_port, SO(23)
=> A_to_mux_23_port, SO(22) => A_to_mux_22_port,
SO(21) => A_to_mux_21_port, SO(20) =>
A_to_mux_20_port, SO(19) => A_to_mux_19_port, SO(18)
=> A_to_mux_18_port, SO(17) => A_to_mux_17_port,
SO(16) => A_to_mux_16_port, SO(15) =>
A_to_mux_15_port, SO(14) => A_to_mux_14_port, SO(13)
=> A_to_mux_13_port, SO(12) => A_to_mux_12_port,
SO(11) => A_to_mux_11_port, SO(10) =>
A_to_mux_10_port, SO(9) => A_to_mux_9_port, SO(8) =>
A_to_mux_8_port, SO(7) => A_to_mux_7_port, SO(6) =>
A_to_mux_6_port, SO(5) => A_to_mux_5_port, SO(4) =>
A_to_mux_4_port, SO(3) => A_to_mux_3_port, SO(2) =>
A_to_mux_2_port, SO(1) => A_to_mux_1_port, SO(0) =>
A_to_mux_0_port);
INPUTMUX : mux21_1 port map( IN0(31) => A_to_mux_31_port, IN0(30) =>
A_to_mux_30_port, IN0(29) => A_to_mux_29_port,
IN0(28) => A_to_mux_28_port, IN0(27) =>
A_to_mux_27_port, IN0(26) => A_to_mux_26_port,
IN0(25) => A_to_mux_25_port, IN0(24) =>
A_to_mux_24_port, IN0(23) => A_to_mux_23_port,
IN0(22) => A_to_mux_22_port, IN0(21) =>
A_to_mux_21_port, IN0(20) => A_to_mux_20_port,
IN0(19) => A_to_mux_19_port, IN0(18) =>
A_to_mux_18_port, IN0(17) => A_to_mux_17_port,
IN0(16) => A_to_mux_16_port, IN0(15) =>
A_to_mux_15_port, IN0(14) => A_to_mux_14_port,
IN0(13) => A_to_mux_13_port, IN0(12) =>
A_to_mux_12_port, IN0(11) => A_to_mux_11_port,
IN0(10) => A_to_mux_10_port, IN0(9) =>
A_to_mux_9_port, IN0(8) => A_to_mux_8_port, IN0(7)
=> A_to_mux_7_port, IN0(6) => A_to_mux_6_port,
IN0(5) => A_to_mux_5_port, IN0(4) => A_to_mux_4_port
, IN0(3) => A_to_mux_3_port, IN0(2) =>
A_to_mux_2_port, IN0(1) => A_to_mux_1_port, IN0(0)
=> A_to_mux_0_port, IN1(31) => A_to_mux_30_port,
IN1(30) => A_to_mux_29_port, IN1(29) =>
A_to_mux_28_port, IN1(28) => A_to_mux_27_port,
IN1(27) => A_to_mux_26_port, IN1(26) =>
A_to_mux_25_port, IN1(25) => A_to_mux_24_port,
IN1(24) => A_to_mux_23_port, IN1(23) =>
A_to_mux_22_port, IN1(22) => A_to_mux_21_port,
IN1(21) => A_to_mux_20_port, IN1(20) =>
A_to_mux_19_port, IN1(19) => A_to_mux_18_port,
IN1(18) => A_to_mux_17_port, IN1(17) =>
A_to_mux_16_port, IN1(16) => A_to_mux_15_port,
IN1(15) => A_to_mux_14_port, IN1(14) =>
A_to_mux_13_port, IN1(13) => A_to_mux_12_port,
IN1(12) => A_to_mux_11_port, IN1(11) =>
A_to_mux_10_port, IN1(10) => A_to_mux_9_port, IN1(9)
=> A_to_mux_8_port, IN1(8) => A_to_mux_7_port,
IN1(7) => A_to_mux_6_port, IN1(6) => A_to_mux_5_port
, IN1(5) => A_to_mux_4_port, IN1(4) =>
A_to_mux_3_port, IN1(3) => A_to_mux_2_port, IN1(2)
=> A_to_mux_1_port, IN1(1) => A_to_mux_0_port,
IN1(0) => X_Logic0_port, CTRL => input_mux_sel_0,
OUT1(31) => B_to_add(31), OUT1(30) => B_to_add(30),
OUT1(29) => B_to_add(29), OUT1(28) => B_to_add(28),
OUT1(27) => B_to_add(27), OUT1(26) => B_to_add(26),
OUT1(25) => B_to_add(25), OUT1(24) => B_to_add(24),
OUT1(23) => B_to_add(23), OUT1(22) => B_to_add(22),
OUT1(21) => B_to_add(21), OUT1(20) => B_to_add(20),
OUT1(19) => B_to_add(19), OUT1(18) => B_to_add(18),
OUT1(17) => B_to_add(17), OUT1(16) => B_to_add(16),
OUT1(15) => B_to_add(15), OUT1(14) => B_to_add(14),
OUT1(13) => B_to_add(13), OUT1(12) => B_to_add(12),
OUT1(11) => B_to_add(11), OUT1(10) => B_to_add(10),
OUT1(9) => B_to_add(9), OUT1(8) => B_to_add(8),
OUT1(7) => B_to_add(7), OUT1(6) => B_to_add(6),
OUT1(5) => B_to_add(5), OUT1(4) => B_to_add(4),
OUT1(3) => B_to_add(3), OUT1(2) => B_to_add(2),
OUT1(1) => B_to_add(1), OUT1(0) => B_to_add(0));
ACCUMULATOR : ff32_en_SIZE32 port map( D(31) => next_accumulate_31_port,
D(30) => next_accumulate_30_port, D(29) =>
next_accumulate_29_port, D(28) =>
next_accumulate_28_port, D(27) =>
next_accumulate_27_port, D(26) =>
next_accumulate_26_port, D(25) =>
next_accumulate_25_port, D(24) =>
next_accumulate_24_port, D(23) =>
next_accumulate_23_port, D(22) =>
next_accumulate_22_port, D(21) =>
next_accumulate_21_port, D(20) =>
next_accumulate_20_port, D(19) =>
next_accumulate_19_port, D(18) =>
next_accumulate_18_port, D(17) =>
next_accumulate_17_port, D(16) =>
next_accumulate_16_port, D(15) =>
next_accumulate_15_port, D(14) =>
next_accumulate_14_port, D(13) =>
next_accumulate_13_port, D(12) =>
next_accumulate_12_port, D(11) =>
next_accumulate_11_port, D(10) =>
next_accumulate_10_port, D(9) =>
next_accumulate_9_port, D(8) =>
next_accumulate_8_port, D(7) =>
next_accumulate_7_port, D(6) =>
next_accumulate_6_port, D(5) =>
next_accumulate_5_port, D(4) =>
next_accumulate_4_port, D(3) =>
next_accumulate_3_port, D(2) =>
next_accumulate_2_port, D(1) =>
next_accumulate_1_port, D(0) =>
next_accumulate_0_port, en => reg_enable, clk =>
Clock, rst => Reset, Q(31) => A_to_add_31_port,
Q(30) => A_to_add_30_port, Q(29) => A_to_add_29_port
, Q(28) => A_to_add_28_port, Q(27) =>
A_to_add_27_port, Q(26) => A_to_add_26_port, Q(25)
=> A_to_add_25_port, Q(24) => A_to_add_24_port,
Q(23) => A_to_add_23_port, Q(22) => A_to_add_22_port
, Q(21) => A_to_add_21_port, Q(20) =>
A_to_add_20_port, Q(19) => A_to_add_19_port, Q(18)
=> A_to_add_18_port, Q(17) => A_to_add_17_port,
Q(16) => A_to_add_16_port, Q(15) => A_to_add_15_port
, Q(14) => A_to_add_14_port, Q(13) =>
A_to_add_13_port, Q(12) => A_to_add_12_port, Q(11)
=> A_to_add_11_port, Q(10) => A_to_add_10_port, Q(9)
=> A_to_add_9_port, Q(8) => A_to_add_8_port, Q(7) =>
A_to_add_7_port, Q(6) => A_to_add_6_port, Q(5) =>
A_to_add_5_port, Q(4) => A_to_add_4_port, Q(3) =>
A_to_add_3_port, Q(2) => A_to_add_2_port, Q(1) =>
A_to_add_1_port, Q(0) => A_to_add_0_port);
U34 : NOR2_X1 port map( A1 => n22, A2 => n59, ZN => next_accumulate_24_port)
;
U36 : NOR2_X1 port map( A1 => n22, A2 => n60, ZN => next_accumulate_23_port)
;
U58 : NOR2_X1 port map( A1 => n22, A2 => n71, ZN => next_accumulate_13_port)
;
U54 : NOR2_X1 port map( A1 => n22, A2 => n69, ZN => next_accumulate_15_port)
;
U48 : NOR2_X1 port map( A1 => n22, A2 => n66, ZN => next_accumulate_18_port)
;
U46 : NOR2_X1 port map( A1 => n22, A2 => n65, ZN => next_accumulate_19_port)
;
U60 : NOR2_X1 port map( A1 => n22, A2 => n72, ZN => next_accumulate_12_port)
;
U62 : NOR2_X1 port map( A1 => n22, A2 => n73, ZN => next_accumulate_11_port)
;
U6 : NOR2_X1 port map( A1 => n22, A2 => n39, ZN => next_accumulate_8_port);
U4 : NOR2_X1 port map( A1 => n22, A2 => n38, ZN => next_accumulate_9_port);
U64 : NOR2_X1 port map( A1 => n22, A2 => n74, ZN => next_accumulate_10_port)
;
U8 : NOR2_X1 port map( A1 => n22, A2 => n40, ZN => next_accumulate_7_port);
U10 : NOR2_X1 port map( A1 => n22, A2 => n41, ZN => next_accumulate_6_port);
U16 : NOR2_X1 port map( A1 => n22, A2 => n44, ZN => next_accumulate_3_port);
U12 : NOR2_X1 port map( A1 => n22, A2 => n42, ZN => next_accumulate_5_port);
U14 : NOR2_X1 port map( A1 => n22, A2 => n43, ZN => next_accumulate_4_port);
U22 : NOR2_X1 port map( A1 => n22, A2 => n47, ZN => next_accumulate_2_port);
U44 : NOR2_X1 port map( A1 => n22, A2 => n64, ZN => next_accumulate_1_port);
U66 : NOR2_X1 port map( A1 => n22, A2 => n75, ZN => next_accumulate_0_port);
U78 : AND3_X1 port map( A1 => n81, A2 => N21, A3 => net549699, ZN =>
valid_port);
U72 : AOI21_X1 port map( B1 => enable, B2 => N24, A => valid_port, ZN => n77
);
U71 : OAI21_X1 port map( B1 => net549699, B2 => enable, A => n77, ZN => n52)
;
U76 : NAND2_X1 port map( A1 => enable, A2 => N23, ZN => n79);
U75 : OAI22_X1 port map( A1 => n79, A2 => valid_port, B1 => enable, B2 =>
n11, ZN => n50);
U69 : AOI21_X1 port map( B1 => enable, B2 => N21, A => valid_port, ZN => n76
);
U68 : OAI21_X1 port map( B1 => N21, B2 => enable, A => n76, ZN => n54);
U59 : INV_X1 port map( A => ACC_from_add(13), ZN => n71);
U55 : INV_X1 port map( A => ACC_from_add(15), ZN => n69);
U63 : INV_X1 port map( A => ACC_from_add(11), ZN => n73);
U7 : INV_X1 port map( A => ACC_from_add(8), ZN => n39);
U5 : INV_X1 port map( A => ACC_from_add(9), ZN => n38);
U65 : INV_X1 port map( A => ACC_from_add(10), ZN => n74);
U9 : INV_X1 port map( A => ACC_from_add(7), ZN => n40);
U11 : INV_X1 port map( A => ACC_from_add(6), ZN => n41);
U17 : INV_X1 port map( A => ACC_from_add(3), ZN => n44);
U13 : INV_X1 port map( A => ACC_from_add(5), ZN => n42);
U15 : INV_X1 port map( A => ACC_from_add(4), ZN => n43);
U23 : INV_X1 port map( A => ACC_from_add(2), ZN => n47);
U45 : INV_X1 port map( A => ACC_from_add(1), ZN => n64);
U67 : INV_X1 port map( A => ACC_from_add(0), ZN => n75);
U79 : INV_X1 port map( A => n82, ZN => n81);
sub_213_U4 : OAI21_X1 port map( B1 => sub_213_n3, B2 => n11, A => sub_213_n2
, ZN => N23);
sub_213_U3 : XNOR2_X1 port map( A => count_3_port, B => sub_213_n2, ZN =>
N24);
sub_213_U5 : NAND2_X1 port map( A1 => sub_213_n3, A2 => n11, ZN =>
sub_213_n2);
sub_213_U9 : NOR2_X1 port map( A1 => count_1_port, A2 => count_0_port, ZN =>
sub_213_n3);
U84 : NAND3_X1 port map( A1 => n13, A2 => n11, A3 => n12, ZN => n82);
count_reg_0_inst : DFFS_X1 port map( D => n54, CK => Clock, SN => n23_port,
Q => count_0_port, QN => N21);
count_reg_3_inst : DFFS_X1 port map( D => n52, CK => Clock, SN => n23_port,
Q => count_3_port, QN => net549699);
U3 : NOR2_X1 port map( A1 => sub_213_n2, A2 => count_3_port, ZN => n14);
U18 : NAND2_X1 port map( A1 => n14, A2 => count_4_port, ZN => n15);
U19 : OAI211_X1 port map( C1 => n14, C2 => count_4_port, A => n15, B =>
enable, ZN => n16);
U20 : OAI22_X1 port map( A1 => enable, A2 => n12, B1 => valid_port, B2 =>
n16, ZN => n49);
U21 : MUX2_X1 port map( A => A_to_add_0_port, B => ACC_from_add(0), S =>
input_mux_sel_2_port, Z => final_out(0));
U24 : INV_X1 port map( A => ACC_from_add(21), ZN => n17);
U25 : NOR2_X1 port map( A1 => n22, A2 => n17, ZN => next_accumulate_21_port)
;
U26 : OAI221_X1 port map( B1 => sub_213_n3, B2 => count_1_port, C1 =>
sub_213_n3, C2 => count_0_port, A => enable, ZN =>
n18);
U27 : OAI22_X1 port map( A1 => enable, A2 => n13, B1 => valid_port, B2 =>
n18, ZN => n51);
U28 : BUF_X8 port map( A => load, Z => n22);
U29 : NOR3_X1 port map( A1 => N21, A2 => net549699, A3 => n82, ZN => load);
U30 : INV_X1 port map( A => Reset, ZN => n23_port);
U31 : AND2_X1 port map( A1 => sign, A2 => A(15), ZN => extend_vector_15_port
);
U32 : AND2_X1 port map( A1 => sign, A2 => B(15), ZN => enc_N2_in_2_port);
U33 : INV_X1 port map( A => ACC_from_add(12), ZN => n72);
U35 : NOR2_X1 port map( A1 => n22, A2 => n46, ZN => next_accumulate_30_port)
;
U37 : INV_X1 port map( A => ACC_from_add(30), ZN => n46);
U38 : INV_X1 port map( A => ACC_from_add(14), ZN => n70);
U39 : INV_X1 port map( A => ACC_from_add(19), ZN => n65);
U40 : INV_X1 port map( A => ACC_from_add(16), ZN => n68);
U41 : INV_X1 port map( A => ACC_from_add(25), ZN => n58);
U42 : INV_X1 port map( A => ACC_from_add(18), ZN => n66);
U43 : INV_X1 port map( A => ACC_from_add(17), ZN => n67);
U47 : INV_X1 port map( A => ACC_from_add(26), ZN => n57);
U49 : INV_X1 port map( A => ACC_from_add(23), ZN => n60);
U50 : INV_X1 port map( A => ACC_from_add(27), ZN => n56);
U51 : INV_X1 port map( A => ACC_from_add(24), ZN => n59);
U52 : INV_X1 port map( A => ACC_from_add(31), ZN => n45);
U53 : INV_X1 port map( A => ACC_from_add(20), ZN => n63);
U56 : INV_X1 port map( A => ACC_from_add(29), ZN => n48);
U57 : INV_X1 port map( A => ACC_from_add(22), ZN => n61);
U61 : INV_X1 port map( A => ACC_from_add(28), ZN => n55);
U70 : OR2_X4 port map( A1 => n22, A2 => input_mux_sel_2_port, ZN =>
reg_enable);
U73 : NOR2_X1 port map( A1 => n22, A2 => n70, ZN => next_accumulate_14_port)
;
U74 : NOR2_X1 port map( A1 => n22, A2 => n68, ZN => next_accumulate_16_port)
;
U77 : NOR2_X1 port map( A1 => n22, A2 => n58, ZN => next_accumulate_25_port)
;
U80 : NOR2_X1 port map( A1 => n22, A2 => n67, ZN => next_accumulate_17_port)
;
U81 : NOR2_X1 port map( A1 => n22, A2 => n57, ZN => next_accumulate_26_port)
;
U82 : NOR2_X1 port map( A1 => n22, A2 => n56, ZN => next_accumulate_27_port)
;
U83 : NOR2_X1 port map( A1 => n22, A2 => n61, ZN => next_accumulate_22_port)
;
U116 : NOR2_X1 port map( A1 => n22, A2 => n48, ZN => next_accumulate_29_port
);
U117 : NOR2_X1 port map( A1 => n22, A2 => n55, ZN => next_accumulate_28_port
);
U118 : NOR2_X1 port map( A1 => n22, A2 => n63, ZN => next_accumulate_20_port
);
U119 : NOR2_X1 port map( A1 => n22, A2 => n45, ZN => next_accumulate_31_port
);
end SYN_struct;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity mux41_MUX_SIZE32_0 is
port( IN0, IN1, IN2, IN3 : in std_logic_vector (31 downto 0); CTRL : in
std_logic_vector (1 downto 0); OUT1 : out std_logic_vector (31 downto
0));
end mux41_MUX_SIZE32_0;
architecture SYN_bhe of mux41_MUX_SIZE32_0 is
component AOI22_X1
port( A1, A2, B1, B2 : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component NOR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component BUF_X2
port( A : in std_logic; Z : out std_logic);
end component;
component AOI222_X1
port( A1, A2, B1, B2, C1, C2 : in std_logic; ZN : out std_logic);
end component;
component BUF_X1
port( A : in std_logic; Z : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
signal n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44, n45, n46, n47,
n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58, n59, n60, n61, n62
, n63, n64, n65, n66, n67, n69, n68, n70, n71, n72, n73, n74, n75, n76,
n77 : std_logic;
begin
U42 : AOI222_X1 port map( A1 => n77, A2 => IN1(1), B1 => n76, B2 => IN0(1),
C1 => n73, C2 => IN2(1), ZN => n57);
U46 : AOI222_X1 port map( A1 => n77, A2 => IN1(18), B1 => n76, B2 => IN0(18)
, C1 => n73, C2 => IN2(18), ZN => n59);
U48 : AOI222_X1 port map( A1 => n77, A2 => IN1(17), B1 => n76, B2 => IN0(17)
, C1 => n73, C2 => IN2(17), ZN => n60);
U50 : AOI222_X1 port map( A1 => n77, A2 => IN1(16), B1 => n76, B2 => IN0(16)
, C1 => n73, C2 => IN2(16), ZN => n61);
U44 : AOI222_X1 port map( A1 => n77, A2 => IN1(19), B1 => n76, B2 => IN0(19)
, C1 => n73, C2 => IN2(19), ZN => n58);
U20 : AOI222_X1 port map( A1 => n68, A2 => IN1(2), B1 => n70, B2 => IN0(2),
C1 => n74, C2 => IN2(2), ZN => n46);
U14 : AOI222_X1 port map( A1 => n68, A2 => IN1(3), B1 => n70, B2 => IN0(3),
C1 => n75, C2 => IN2(3), ZN => n43);
U6 : AOI222_X1 port map( A1 => n68, A2 => IN1(7), B1 => n70, B2 => IN0(7),
C1 => n75, C2 => IN2(7), ZN => n39);
U10 : AOI222_X1 port map( A1 => n68, A2 => IN1(5), B1 => n70, B2 => IN0(5),
C1 => n75, C2 => IN2(5), ZN => n41);
U12 : AOI222_X1 port map( A1 => n68, A2 => IN1(4), B1 => n70, B2 => IN0(4),
C1 => n75, C2 => IN2(4), ZN => n42);
U58 : AOI222_X1 port map( A1 => n77, A2 => IN1(12), B1 => n76, B2 => IN0(12)
, C1 => n73, C2 => IN2(12), ZN => n65);
U56 : AOI222_X1 port map( A1 => n77, A2 => IN1(13), B1 => n76, B2 => IN0(13)
, C1 => n73, C2 => IN2(13), ZN => n64);
U52 : AOI222_X1 port map( A1 => n77, A2 => IN1(15), B1 => n76, B2 => IN0(15)
, C1 => n73, C2 => IN2(15), ZN => n62);
U54 : AOI222_X1 port map( A1 => n77, A2 => IN1(14), B1 => n76, B2 => IN0(14)
, C1 => n73, C2 => IN2(14), ZN => n63);
U62 : AOI222_X1 port map( A1 => n77, A2 => IN1(10), B1 => n76, B2 => IN0(10)
, C1 => n73, C2 => IN2(10), ZN => n67);
U60 : AOI222_X1 port map( A1 => n77, A2 => IN1(11), B1 => n76, B2 => IN0(11)
, C1 => n73, C2 => IN2(11), ZN => n66);
U4 : AOI222_X1 port map( A1 => n68, A2 => IN1(8), B1 => n70, B2 => IN0(8),
C1 => n75, C2 => IN2(8), ZN => n38);
U2 : AOI222_X1 port map( A1 => n68, A2 => IN1(9), B1 => n70, B2 => IN0(9),
C1 => n75, C2 => IN2(9), ZN => n34);
U36 : AOI222_X1 port map( A1 => n68, A2 => IN1(22), B1 => n70, B2 => IN0(22)
, C1 => n74, C2 => IN2(22), ZN => n54);
U38 : AOI222_X1 port map( A1 => n68, A2 => IN1(21), B1 => n70, B2 => IN0(21)
, C1 => n74, C2 => IN2(21), ZN => n55);
U40 : AOI222_X1 port map( A1 => n68, A2 => IN1(20), B1 => n70, B2 => IN0(20)
, C1 => n74, C2 => IN2(20), ZN => n56);
U34 : AOI222_X1 port map( A1 => n68, A2 => IN1(23), B1 => n70, B2 => IN0(23)
, C1 => n74, C2 => IN2(23), ZN => n53);
U18 : AOI222_X1 port map( A1 => n68, A2 => IN1(30), B1 => n70, B2 => IN0(30)
, C1 => n74, C2 => IN2(30), ZN => n45);
U22 : AOI222_X1 port map( A1 => n68, A2 => IN1(29), B1 => n70, B2 => IN0(29)
, C1 => n74, C2 => IN2(29), ZN => n47);
U24 : AOI222_X1 port map( A1 => n68, A2 => IN1(28), B1 => n70, B2 => IN0(28)
, C1 => n74, C2 => IN2(28), ZN => n48);
U16 : AOI222_X1 port map( A1 => n68, A2 => IN1(31), B1 => n70, B2 => IN0(31)
, C1 => n75, C2 => IN2(31), ZN => n44);
U26 : AOI222_X1 port map( A1 => n68, A2 => IN1(27), B1 => n70, B2 => IN0(27)
, C1 => n74, C2 => IN2(27), ZN => n49);
U28 : AOI222_X1 port map( A1 => n68, A2 => IN1(26), B1 => n70, B2 => IN0(26)
, C1 => n74, C2 => IN2(26), ZN => n50);
U30 : AOI222_X1 port map( A1 => n68, A2 => IN1(25), B1 => n70, B2 => IN0(25)
, C1 => n74, C2 => IN2(25), ZN => n51);
U32 : AOI222_X1 port map( A1 => n68, A2 => IN1(24), B1 => n70, B2 => IN0(24)
, C1 => n74, C2 => IN2(24), ZN => n52);
U66 : NOR2_X1 port map( A1 => CTRL(1), A2 => CTRL(0), ZN => n36);
U68 : INV_X1 port map( A => CTRL(1), ZN => n69);
U67 : AND2_X1 port map( A1 => n69, A2 => CTRL(0), ZN => n35);
U41 : INV_X1 port map( A => n57, ZN => OUT1(1));
U45 : INV_X1 port map( A => n59, ZN => OUT1(18));
U47 : INV_X1 port map( A => n60, ZN => OUT1(17));
U49 : INV_X1 port map( A => n61, ZN => OUT1(16));
U43 : INV_X1 port map( A => n58, ZN => OUT1(19));
U19 : INV_X1 port map( A => n46, ZN => OUT1(2));
U13 : INV_X1 port map( A => n43, ZN => OUT1(3));
U7 : INV_X1 port map( A => n40, ZN => OUT1(6));
U5 : INV_X1 port map( A => n39, ZN => OUT1(7));
U9 : INV_X1 port map( A => n41, ZN => OUT1(5));
U11 : INV_X1 port map( A => n42, ZN => OUT1(4));
U57 : INV_X1 port map( A => n65, ZN => OUT1(12));
U55 : INV_X1 port map( A => n64, ZN => OUT1(13));
U51 : INV_X1 port map( A => n62, ZN => OUT1(15));
U53 : INV_X1 port map( A => n63, ZN => OUT1(14));
U61 : INV_X1 port map( A => n67, ZN => OUT1(10));
U59 : INV_X1 port map( A => n66, ZN => OUT1(11));
U3 : INV_X1 port map( A => n38, ZN => OUT1(8));
U1 : INV_X1 port map( A => n34, ZN => OUT1(9));
U35 : INV_X1 port map( A => n54, ZN => OUT1(22));
U37 : INV_X1 port map( A => n55, ZN => OUT1(21));
U39 : INV_X1 port map( A => n56, ZN => OUT1(20));
U33 : INV_X1 port map( A => n53, ZN => OUT1(23));
U17 : INV_X1 port map( A => n45, ZN => OUT1(30));
U21 : INV_X1 port map( A => n47, ZN => OUT1(29));
U23 : INV_X1 port map( A => n48, ZN => OUT1(28));
U15 : INV_X1 port map( A => n44, ZN => OUT1(31));
U25 : INV_X1 port map( A => n49, ZN => OUT1(27));
U27 : INV_X1 port map( A => n50, ZN => OUT1(26));
U29 : INV_X1 port map( A => n51, ZN => OUT1(25));
U31 : INV_X1 port map( A => n52, ZN => OUT1(24));
U8 : BUF_X2 port map( A => n35, Z => n68);
U63 : BUF_X1 port map( A => n36, Z => n76);
U64 : BUF_X2 port map( A => n36, Z => n70);
U65 : BUF_X2 port map( A => n35, Z => n77);
U69 : AOI222_X1 port map( A1 => n68, A2 => IN1(6), B1 => n70, B2 => IN0(6),
C1 => n75, C2 => IN2(6), ZN => n40);
U70 : BUF_X2 port map( A => n37, Z => n75);
U71 : BUF_X2 port map( A => n37, Z => n74);
U72 : BUF_X2 port map( A => n37, Z => n73);
U73 : NOR2_X1 port map( A1 => CTRL(0), A2 => n69, ZN => n37);
U74 : NAND2_X1 port map( A1 => n73, A2 => IN2(0), ZN => n71);
U75 : NAND2_X1 port map( A1 => n71, A2 => n72, ZN => OUT1(0));
U76 : AOI22_X1 port map( A1 => n77, A2 => IN1(0), B1 => n76, B2 => IN0(0),
ZN => n72);
end SYN_bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity mux41_MUX_SIZE5 is
port( IN0, IN1, IN2, IN3 : in std_logic_vector (4 downto 0); CTRL : in
std_logic_vector (1 downto 0); OUT1 : out std_logic_vector (4 downto
0));
end mux41_MUX_SIZE5;
architecture SYN_bhe of mux41_MUX_SIZE5 is
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component NOR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component AOI22_X1
port( A1, A2, B1, B2 : in std_logic; ZN : out std_logic);
end component;
signal n2, n3, n4, n5, n6, n8, n9, n10, n11, n12, n13, n14, n15, n16 :
std_logic;
begin
U1 : NAND2_X1 port map( A1 => n2, A2 => n3, ZN => OUT1(4));
U4 : NAND2_X1 port map( A1 => n8, A2 => n9, ZN => OUT1(3));
U7 : NAND2_X1 port map( A1 => n10, A2 => n11, ZN => OUT1(2));
U10 : NAND2_X1 port map( A1 => n12, A2 => n13, ZN => OUT1(1));
U17 : AOI22_X1 port map( A1 => n5, A2 => IN2(0), B1 => n6, B2 => IN1(0), ZN
=> n14);
U13 : NAND2_X1 port map( A1 => n14, A2 => n15, ZN => OUT1(0));
U19 : NOR2_X1 port map( A1 => CTRL(0), A2 => n16, ZN => n5);
U20 : INV_X1 port map( A => CTRL(1), ZN => n16);
U18 : AND2_X1 port map( A1 => n16, A2 => CTRL(0), ZN => n6);
U16 : AND2_X1 port map( A1 => CTRL(0), A2 => CTRL(1), ZN => n4);
U2 : INV_X1 port map( A => n4, ZN => n15);
U3 : AOI21_X1 port map( B1 => n5, B2 => IN2(1), A => n4, ZN => n13);
U5 : NAND2_X1 port map( A1 => n6, A2 => IN1(1), ZN => n12);
U6 : AOI21_X1 port map( B1 => n5, B2 => IN2(2), A => n4, ZN => n11);
U8 : NAND2_X1 port map( A1 => n6, A2 => IN1(2), ZN => n10);
U9 : AOI21_X1 port map( B1 => n5, B2 => IN2(3), A => n4, ZN => n9);
U11 : NAND2_X1 port map( A1 => n6, A2 => IN1(3), ZN => n8);
U12 : AOI21_X1 port map( B1 => n5, B2 => IN2(4), A => n4, ZN => n3);
U14 : NAND2_X1 port map( A1 => n6, A2 => IN1(4), ZN => n2);
end SYN_bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity real_alu_DATA_SIZE32 is
port( IN1, IN2 : in std_logic_vector (31 downto 0); ALUW_i : in
std_logic_vector (12 downto 0); DOUT : out std_logic_vector (31
downto 0); stall_o : out std_logic; Clock, Reset : in std_logic);
end real_alu_DATA_SIZE32;
architecture SYN_Bhe of real_alu_DATA_SIZE32 is
component AOI22_X1
port( A1, A2, B1, B2 : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component AOI222_X1
port( A1, A2, B1, B2, C1, C2 : in std_logic; ZN : out std_logic);
end component;
component NOR3_X1
port( A1, A2, A3 : in std_logic; ZN : out std_logic);
end component;
component NOR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component OR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component CLKBUF_X1
port( A : in std_logic; Z : out std_logic);
end component;
component BUF_X1
port( A : in std_logic; Z : out std_logic);
end component;
component NAND2_X4
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component BUF_X2
port( A : in std_logic; Z : out std_logic);
end component;
component MUX2_X1
port( A, B, S : in std_logic; Z : out std_logic);
end component;
component INV_X2
port( A : in std_logic; ZN : out std_logic);
end component;
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component logic_unit_SIZE32
port( IN1, IN2 : in std_logic_vector (31 downto 0); CTRL : in
std_logic_vector (1 downto 0); OUT1 : out std_logic_vector (31
downto 0));
end component;
component shifter
port( A : in std_logic_vector (31 downto 0); B : in std_logic_vector (4
downto 0); LOGIC_ARITH, LEFT_RIGHT : in std_logic; OUTPUT : out
std_logic_vector (31 downto 0));
end component;
component comparator_M32
port( C, V : in std_logic; SUM : in std_logic_vector (31 downto 0); sel
: in std_logic_vector (2 downto 0); sign : in std_logic; S : out
std_logic);
end component;
component p4add_N32_logN5
port( A, B : in std_logic_vector (31 downto 0); Cin, sign : in std_logic
; S : out std_logic_vector (31 downto 0); Cout : out std_logic);
end component;
component simple_booth_add_ext_N16
port( Clock, Reset, sign, enable : in std_logic; valid : out std_logic;
A, B : in std_logic_vector (15 downto 0); A_to_add, B_to_add : out
std_logic_vector (31 downto 0); sign_to_add : out std_logic;
final_out : out std_logic_vector (31 downto 0); ACC_from_add : in
std_logic_vector (31 downto 0));
end component;
component NAND3_X1
port( A1, A2, A3 : in std_logic; ZN : out std_logic);
end component;
component OAI33_X1
port( A1, A2, A3, B1, B2, B3 : in std_logic; ZN : out std_logic);
end component;
signal X_Logic0_port, mux_A_31_port, mux_A_30_port, mux_A_29_port,
mux_A_28_port, mux_A_27_port, mux_A_26_port, mux_A_25_port, mux_A_24_port
, mux_A_23_port, mux_A_22_port, mux_A_21_port, mux_A_20_port,
mux_A_19_port, mux_A_18_port, mux_A_17_port, mux_A_16_port, mux_A_15_port
, mux_A_14_port, mux_A_13_port, mux_A_12_port, mux_A_11_port,
mux_A_10_port, mux_A_9_port, mux_A_8_port, mux_A_7_port, mux_A_6_port,
mux_A_5_port, mux_A_4_port, mux_A_3_port, mux_A_2_port, mux_A_1_port,
mux_A_0_port, A_booth_to_add_31_port, A_booth_to_add_30_port,
A_booth_to_add_29_port, A_booth_to_add_28_port, A_booth_to_add_27_port,
A_booth_to_add_26_port, A_booth_to_add_25_port, A_booth_to_add_24_port,
A_booth_to_add_23_port, A_booth_to_add_22_port, A_booth_to_add_21_port,
A_booth_to_add_20_port, A_booth_to_add_19_port, A_booth_to_add_18_port,
A_booth_to_add_17_port, A_booth_to_add_16_port, A_booth_to_add_15_port,
A_booth_to_add_14_port, A_booth_to_add_13_port, A_booth_to_add_12_port,
A_booth_to_add_11_port, A_booth_to_add_10_port, A_booth_to_add_9_port,
A_booth_to_add_8_port, A_booth_to_add_7_port, A_booth_to_add_6_port,
A_booth_to_add_5_port, A_booth_to_add_4_port, A_booth_to_add_3_port,
A_booth_to_add_2_port, A_booth_to_add_1_port, A_booth_to_add_0_port,
mux_B_31_port, mux_B_30_port, mux_B_29_port, mux_B_28_port, mux_B_27_port
, mux_B_26_port, mux_B_25_port, mux_B_24_port, mux_B_23_port,
mux_B_22_port, mux_B_21_port, mux_B_20_port, mux_B_19_port, mux_B_18_port
, mux_B_17_port, mux_B_16_port, mux_B_15_port, mux_B_14_port,
mux_B_13_port, mux_B_12_port, mux_B_11_port, mux_B_10_port, mux_B_9_port,
mux_B_8_port, mux_B_7_port, mux_B_6_port, mux_B_5_port, mux_B_4_port,
mux_B_3_port, mux_B_2_port, mux_B_1_port, mux_B_0_port,
B_booth_to_add_31_port, B_booth_to_add_30_port, B_booth_to_add_29_port,
B_booth_to_add_28_port, B_booth_to_add_27_port, B_booth_to_add_26_port,
B_booth_to_add_25_port, B_booth_to_add_24_port, B_booth_to_add_23_port,
B_booth_to_add_22_port, B_booth_to_add_21_port, B_booth_to_add_20_port,
B_booth_to_add_19_port, B_booth_to_add_18_port, B_booth_to_add_17_port,
B_booth_to_add_16_port, B_booth_to_add_15_port, B_booth_to_add_14_port,
B_booth_to_add_13_port, B_booth_to_add_12_port, B_booth_to_add_11_port,
B_booth_to_add_10_port, B_booth_to_add_9_port, B_booth_to_add_8_port,
B_booth_to_add_7_port, B_booth_to_add_6_port, B_booth_to_add_5_port,
B_booth_to_add_4_port, B_booth_to_add_3_port, B_booth_to_add_2_port,
B_booth_to_add_1_port, B_booth_to_add_0_port, mux_sign, sign_booth_to_add
, valid_from_booth, mult_out_31_port, mult_out_30_port, mult_out_29_port,
mult_out_28_port, mult_out_27_port, mult_out_26_port, mult_out_25_port,
mult_out_24_port, mult_out_23_port, mult_out_22_port, mult_out_21_port,
mult_out_20_port, mult_out_19_port, mult_out_18_port, mult_out_17_port,
mult_out_16_port, mult_out_15_port, mult_out_14_port, mult_out_13_port,
mult_out_12_port, mult_out_11_port, mult_out_10_port, mult_out_9_port,
mult_out_8_port, mult_out_7_port, mult_out_6_port, mult_out_5_port,
mult_out_4_port, mult_out_3_port, mult_out_2_port, mult_out_1_port,
mult_out_0_port, sum_out_31_port, sum_out_30_port, sum_out_29_port,
sum_out_28_port, sum_out_27_port, sum_out_26_port, sum_out_25_port,
sum_out_24_port, sum_out_23_port, sum_out_22_port, sum_out_21_port,
sum_out_20_port, sum_out_18_port, sum_out_17_port, sum_out_16_port,
sum_out_15_port, sum_out_14_port, sum_out_13_port, sum_out_12_port,
sum_out_11_port, sum_out_10_port, sum_out_9_port, sum_out_8_port,
sum_out_7_port, sum_out_6_port, sum_out_5_port, sum_out_4_port,
sum_out_3_port, sum_out_2_port, sum_out_1_port, sum_out_0_port,
carry_from_adder, overflow, comp_out, shift_out_31_port,
shift_out_30_port, shift_out_29_port, shift_out_28_port,
shift_out_27_port, shift_out_26_port, shift_out_25_port,
shift_out_24_port, shift_out_23_port, shift_out_22_port,
shift_out_21_port, shift_out_20_port, shift_out_19_port,
shift_out_18_port, shift_out_17_port, shift_out_16_port,
shift_out_15_port, shift_out_14_port, shift_out_13_port,
shift_out_12_port, shift_out_11_port, shift_out_10_port, shift_out_9_port
, shift_out_8_port, shift_out_7_port, shift_out_6_port, shift_out_5_port,
shift_out_4_port, shift_out_3_port, shift_out_2_port, shift_out_1_port,
shift_out_0_port, lu_out_31_port, lu_out_30_port, lu_out_29_port,
lu_out_28_port, lu_out_27_port, lu_out_26_port, lu_out_25_port,
lu_out_24_port, lu_out_23_port, lu_out_22_port, lu_out_21_port,
lu_out_20_port, lu_out_19_port, lu_out_18_port, lu_out_17_port,
lu_out_16_port, lu_out_15_port, lu_out_14_port, lu_out_13_port,
lu_out_12_port, lu_out_11_port, lu_out_10_port, lu_out_9_port,
lu_out_8_port, lu_out_7_port, lu_out_6_port, lu_out_5_port, lu_out_4_port
, lu_out_3_port, lu_out_2_port, lu_out_1_port, lu_out_0_port, n9, n10,
n11, n12, n13, n14, n15, n16, n17, n18, n19, n20, n21, n22, n23, n24, n25
, n26, n27, n28, n29, n30, n31, n32, n33, n34, n35, n36, n37, n38, n39,
n40, n41, n42, n43, n44, n45, n46, n47, n48, n49, n50, n51, n52, n53, n54
, n55, n56, n57, n58, n59, n60, n61, n62, n63, n64, n65, n66, n67, n68,
n69, n70, n71, n72, n73, n74, n75, n76, n77, n78, n79, n80, n81, n82, n83
, n84, n85, n86, n87, n88, n89, n90, n91, n92, n93, n94, n95, n96, n97,
n98, n99, n100, n101, n102, n103, n104, n105, n106, n107, n108, n112,
n113, n115, n109, n110, n111, n114, n116, n117, n118, n119, n120, n121,
n122, n123, n124, n125, n126, n127, n128, n129, n130, n131, n132, n133,
n134, n135, n136, n137, n138, n139, n140, n141, n142, n143, n144, n145,
n146, n147, n148, n149, n150, n151, n152, n153, n154, n155, n156, n157,
n158, n159, n160, n161, n162, n163, n164, n165, n166, n167, n168, n169,
n170, n171, n172, n173, n174, n175, n176, n177, n178, n179, n180, n181,
n182, n183, n184, n185, n186, n187 : std_logic;
begin
X_Logic0_port <= '0';
U112 : OAI33_X1 port map( A1 => n9, A2 => n10, A3 => IN1(31), B1 =>
sum_out_31_port, B2 => n11, B3 => IN2(31), ZN =>
overflow);
U140 : MUX2_X1 port map( A => IN2(14), B => B_booth_to_add_14_port, S =>
ALUW_i(1), Z => mux_B_14_port);
U143 : MUX2_X1 port map( A => IN2(11), B => B_booth_to_add_11_port, S =>
ALUW_i(1), Z => mux_B_11_port);
U146 : MUX2_X1 port map( A => IN1(9), B => A_booth_to_add_9_port, S =>
ALUW_i(1), Z => mux_A_9_port);
U147 : MUX2_X1 port map( A => IN1(8), B => A_booth_to_add_8_port, S =>
ALUW_i(1), Z => mux_A_8_port);
U148 : MUX2_X1 port map( A => IN1(7), B => A_booth_to_add_7_port, S =>
ALUW_i(1), Z => mux_A_7_port);
U151 : MUX2_X1 port map( A => IN1(4), B => A_booth_to_add_4_port, S =>
ALUW_i(1), Z => mux_A_4_port);
U152 : MUX2_X1 port map( A => IN1(3), B => A_booth_to_add_3_port, S =>
ALUW_i(1), Z => mux_A_3_port);
U153 : MUX2_X1 port map( A => IN1(31), B => A_booth_to_add_31_port, S =>
ALUW_i(1), Z => mux_A_31_port);
U154 : MUX2_X1 port map( A => IN1(30), B => A_booth_to_add_30_port, S =>
ALUW_i(1), Z => mux_A_30_port);
U156 : MUX2_X1 port map( A => IN1(29), B => A_booth_to_add_29_port, S =>
ALUW_i(1), Z => mux_A_29_port);
U157 : MUX2_X1 port map( A => IN1(28), B => A_booth_to_add_28_port, S =>
ALUW_i(1), Z => mux_A_28_port);
U158 : MUX2_X1 port map( A => IN1(27), B => A_booth_to_add_27_port, S =>
ALUW_i(1), Z => mux_A_27_port);
U159 : MUX2_X1 port map( A => IN1(26), B => A_booth_to_add_26_port, S =>
ALUW_i(1), Z => mux_A_26_port);
U160 : MUX2_X1 port map( A => IN1(25), B => A_booth_to_add_25_port, S =>
ALUW_i(1), Z => mux_A_25_port);
U161 : MUX2_X1 port map( A => IN1(24), B => A_booth_to_add_24_port, S =>
ALUW_i(1), Z => mux_A_24_port);
U162 : MUX2_X1 port map( A => IN1(23), B => A_booth_to_add_23_port, S =>
ALUW_i(1), Z => mux_A_23_port);
U163 : MUX2_X1 port map( A => IN1(22), B => A_booth_to_add_22_port, S =>
ALUW_i(1), Z => mux_A_22_port);
U164 : MUX2_X1 port map( A => IN1(21), B => A_booth_to_add_21_port, S =>
ALUW_i(1), Z => mux_A_21_port);
U165 : MUX2_X1 port map( A => IN1(20), B => A_booth_to_add_20_port, S =>
ALUW_i(1), Z => mux_A_20_port);
U167 : MUX2_X1 port map( A => IN1(19), B => A_booth_to_add_19_port, S =>
ALUW_i(1), Z => mux_A_19_port);
U169 : MUX2_X1 port map( A => IN1(17), B => A_booth_to_add_17_port, S =>
ALUW_i(1), Z => mux_A_17_port);
U170 : MUX2_X1 port map( A => IN1(16), B => A_booth_to_add_16_port, S =>
ALUW_i(1), Z => mux_A_16_port);
U171 : MUX2_X1 port map( A => IN1(15), B => A_booth_to_add_15_port, S =>
ALUW_i(1), Z => mux_A_15_port);
U172 : MUX2_X1 port map( A => IN1(14), B => A_booth_to_add_14_port, S =>
ALUW_i(1), Z => mux_A_14_port);
U174 : MUX2_X1 port map( A => IN1(12), B => A_booth_to_add_12_port, S =>
ALUW_i(1), Z => mux_A_12_port);
U175 : MUX2_X1 port map( A => IN1(11), B => A_booth_to_add_11_port, S =>
ALUW_i(1), Z => mux_A_11_port);
U178 : NAND3_X1 port map( A1 => n12, A2 => n13, A3 => n14, ZN => DOUT(9));
U179 : NAND3_X1 port map( A1 => n20, A2 => n21, A3 => n22, ZN => DOUT(8));
U180 : NAND3_X1 port map( A1 => n23, A2 => n24, A3 => n25, ZN => DOUT(7));
U181 : NAND3_X1 port map( A1 => n26, A2 => n27, A3 => n28, ZN => DOUT(6));
U182 : NAND3_X1 port map( A1 => n29, A2 => n30, A3 => n31, ZN => DOUT(5));
U183 : NAND3_X1 port map( A1 => n32, A2 => n33, A3 => n34, ZN => DOUT(4));
U184 : NAND3_X1 port map( A1 => n35, A2 => n36, A3 => n37, ZN => DOUT(3));
U185 : NAND3_X1 port map( A1 => n40, A2 => n41, A3 => n42, ZN => DOUT(30));
U186 : NAND3_X1 port map( A1 => n43, A2 => n44, A3 => n45, ZN => DOUT(2));
U187 : NAND3_X1 port map( A1 => n46, A2 => n47, A3 => n48, ZN => DOUT(29));
U188 : NAND3_X1 port map( A1 => n49, A2 => n50, A3 => n51, ZN => DOUT(28));
U189 : NAND3_X1 port map( A1 => n52, A2 => n53, A3 => n54, ZN => DOUT(27));
U190 : NAND3_X1 port map( A1 => n55, A2 => n56, A3 => n57, ZN => DOUT(26));
U191 : NAND3_X1 port map( A1 => n58, A2 => n59, A3 => n60, ZN => DOUT(25));
U192 : NAND3_X1 port map( A1 => n61, A2 => n62, A3 => n63, ZN => DOUT(24));
U193 : NAND3_X1 port map( A1 => n64, A2 => n65, A3 => n66, ZN => DOUT(23));
U194 : NAND3_X1 port map( A1 => n67, A2 => n68, A3 => n69, ZN => DOUT(22));
U195 : NAND3_X1 port map( A1 => n70, A2 => n71, A3 => n72, ZN => DOUT(21));
U196 : NAND3_X1 port map( A1 => n73, A2 => n74, A3 => n75, ZN => DOUT(20));
U197 : NAND3_X1 port map( A1 => n76, A2 => n77, A3 => n78, ZN => DOUT(1));
U198 : NAND3_X1 port map( A1 => n79, A2 => n80, A3 => n81, ZN => DOUT(19));
U199 : NAND3_X1 port map( A1 => n82, A2 => n83, A3 => n84, ZN => DOUT(18));
U200 : NAND3_X1 port map( A1 => n85, A2 => n86, A3 => n87, ZN => DOUT(17));
U201 : NAND3_X1 port map( A1 => n88, A2 => n89, A3 => n90, ZN => DOUT(16));
U202 : NAND3_X1 port map( A1 => n91, A2 => n92, A3 => n93, ZN => DOUT(15));
U203 : NAND3_X1 port map( A1 => n94, A2 => n95, A3 => n96, ZN => DOUT(14));
U204 : NAND3_X1 port map( A1 => n97, A2 => n98, A3 => n99, ZN => DOUT(13));
U205 : NAND3_X1 port map( A1 => n100, A2 => n101, A3 => n102, ZN => DOUT(12)
);
U206 : NAND3_X1 port map( A1 => n103, A2 => n104, A3 => n105, ZN => DOUT(11)
);
U207 : NAND3_X1 port map( A1 => n106, A2 => n107, A3 => n108, ZN => DOUT(10)
);
MULT : simple_booth_add_ext_N16 port map( Clock => Clock, Reset => Reset,
sign => ALUW_i(0), enable => ALUW_i(1), valid =>
valid_from_booth, A(15) => IN1(15), A(14) => IN1(14)
, A(13) => IN1(13), A(12) => IN1(12), A(11) =>
IN1(11), A(10) => IN1(10), A(9) => IN1(9), A(8) =>
IN1(8), A(7) => IN1(7), A(6) => IN1(6), A(5) =>
IN1(5), A(4) => IN1(4), A(3) => IN1(3), A(2) =>
IN1(2), A(1) => IN1(1), A(0) => IN1(0), B(15) =>
n177, B(14) => IN2(14), B(13) => IN2(13), B(12) =>
n170, B(11) => n175, B(10) => n147, B(9) => n176,
B(8) => IN2(8), B(7) => n171, B(6) => n173, B(5) =>
n183, B(4) => n178, B(3) => n180, B(2) => n186, B(1)
=> n181, B(0) => n184, A_to_add(31) =>
A_booth_to_add_31_port, A_to_add(30) =>
A_booth_to_add_30_port, A_to_add(29) =>
A_booth_to_add_29_port, A_to_add(28) =>
A_booth_to_add_28_port, A_to_add(27) =>
A_booth_to_add_27_port, A_to_add(26) =>
A_booth_to_add_26_port, A_to_add(25) =>
A_booth_to_add_25_port, A_to_add(24) =>
A_booth_to_add_24_port, A_to_add(23) =>
A_booth_to_add_23_port, A_to_add(22) =>
A_booth_to_add_22_port, A_to_add(21) =>
A_booth_to_add_21_port, A_to_add(20) =>
A_booth_to_add_20_port, A_to_add(19) =>
A_booth_to_add_19_port, A_to_add(18) =>
A_booth_to_add_18_port, A_to_add(17) =>
A_booth_to_add_17_port, A_to_add(16) =>
A_booth_to_add_16_port, A_to_add(15) =>
A_booth_to_add_15_port, A_to_add(14) =>
A_booth_to_add_14_port, A_to_add(13) =>
A_booth_to_add_13_port, A_to_add(12) =>
A_booth_to_add_12_port, A_to_add(11) =>
A_booth_to_add_11_port, A_to_add(10) =>
A_booth_to_add_10_port, A_to_add(9) =>
A_booth_to_add_9_port, A_to_add(8) =>
A_booth_to_add_8_port, A_to_add(7) =>
A_booth_to_add_7_port, A_to_add(6) =>
A_booth_to_add_6_port, A_to_add(5) =>
A_booth_to_add_5_port, A_to_add(4) =>
A_booth_to_add_4_port, A_to_add(3) =>
A_booth_to_add_3_port, A_to_add(2) =>
A_booth_to_add_2_port, A_to_add(1) =>
A_booth_to_add_1_port, A_to_add(0) =>
A_booth_to_add_0_port, B_to_add(31) =>
B_booth_to_add_31_port, B_to_add(30) =>
B_booth_to_add_30_port, B_to_add(29) =>
B_booth_to_add_29_port, B_to_add(28) =>
B_booth_to_add_28_port, B_to_add(27) =>
B_booth_to_add_27_port, B_to_add(26) =>
B_booth_to_add_26_port, B_to_add(25) =>
B_booth_to_add_25_port, B_to_add(24) =>
B_booth_to_add_24_port, B_to_add(23) =>
B_booth_to_add_23_port, B_to_add(22) =>
B_booth_to_add_22_port, B_to_add(21) =>
B_booth_to_add_21_port, B_to_add(20) =>
B_booth_to_add_20_port, B_to_add(19) =>
B_booth_to_add_19_port, B_to_add(18) =>
B_booth_to_add_18_port, B_to_add(17) =>
B_booth_to_add_17_port, B_to_add(16) =>
B_booth_to_add_16_port, B_to_add(15) =>
B_booth_to_add_15_port, B_to_add(14) =>
B_booth_to_add_14_port, B_to_add(13) =>
B_booth_to_add_13_port, B_to_add(12) =>
B_booth_to_add_12_port, B_to_add(11) =>
B_booth_to_add_11_port, B_to_add(10) =>
B_booth_to_add_10_port, B_to_add(9) =>
B_booth_to_add_9_port, B_to_add(8) =>
B_booth_to_add_8_port, B_to_add(7) =>
B_booth_to_add_7_port, B_to_add(6) =>
B_booth_to_add_6_port, B_to_add(5) =>
B_booth_to_add_5_port, B_to_add(4) =>
B_booth_to_add_4_port, B_to_add(3) =>
B_booth_to_add_3_port, B_to_add(2) =>
B_booth_to_add_2_port, B_to_add(1) =>
B_booth_to_add_1_port, B_to_add(0) =>
B_booth_to_add_0_port, sign_to_add =>
sign_booth_to_add, final_out(31) => mult_out_31_port
, final_out(30) => mult_out_30_port, final_out(29)
=> mult_out_29_port, final_out(28) =>
mult_out_28_port, final_out(27) => mult_out_27_port,
final_out(26) => mult_out_26_port, final_out(25) =>
mult_out_25_port, final_out(24) => mult_out_24_port,
final_out(23) => mult_out_23_port, final_out(22) =>
mult_out_22_port, final_out(21) => mult_out_21_port,
final_out(20) => mult_out_20_port, final_out(19) =>
mult_out_19_port, final_out(18) => mult_out_18_port,
final_out(17) => mult_out_17_port, final_out(16) =>
mult_out_16_port, final_out(15) => mult_out_15_port,
final_out(14) => mult_out_14_port, final_out(13) =>
mult_out_13_port, final_out(12) => mult_out_12_port,
final_out(11) => mult_out_11_port, final_out(10) =>
mult_out_10_port, final_out(9) => mult_out_9_port,
final_out(8) => mult_out_8_port, final_out(7) =>
mult_out_7_port, final_out(6) => mult_out_6_port,
final_out(5) => mult_out_5_port, final_out(4) =>
mult_out_4_port, final_out(3) => mult_out_3_port,
final_out(2) => mult_out_2_port, final_out(1) =>
mult_out_1_port, final_out(0) => mult_out_0_port,
ACC_from_add(31) => n185, ACC_from_add(30) =>
sum_out_30_port, ACC_from_add(29) => n168,
ACC_from_add(28) => n172, ACC_from_add(27) =>
sum_out_27_port, ACC_from_add(26) => sum_out_26_port
, ACC_from_add(25) => n149, ACC_from_add(24) => n150
, ACC_from_add(23) => sum_out_23_port,
ACC_from_add(22) => n169, ACC_from_add(21) => n174,
ACC_from_add(20) => n179, ACC_from_add(19) => n120,
ACC_from_add(18) => sum_out_18_port,
ACC_from_add(17) => sum_out_17_port,
ACC_from_add(16) => sum_out_16_port,
ACC_from_add(15) => sum_out_15_port,
ACC_from_add(14) => sum_out_14_port,
ACC_from_add(13) => sum_out_13_port,
ACC_from_add(12) => sum_out_12_port,
ACC_from_add(11) => sum_out_11_port,
ACC_from_add(10) => sum_out_10_port, ACC_from_add(9)
=> sum_out_9_port, ACC_from_add(8) => sum_out_8_port
, ACC_from_add(7) => sum_out_7_port, ACC_from_add(6)
=> sum_out_6_port, ACC_from_add(5) => sum_out_5_port
, ACC_from_add(4) => sum_out_4_port, ACC_from_add(3)
=> sum_out_3_port, ACC_from_add(2) => sum_out_2_port
, ACC_from_add(1) => sum_out_1_port, ACC_from_add(0)
=> sum_out_0_port);
ADDER : p4add_N32_logN5 port map( A(31) => mux_A_31_port, A(30) =>
mux_A_30_port, A(29) => mux_A_29_port, A(28) =>
mux_A_28_port, A(27) => mux_A_27_port, A(26) =>
mux_A_26_port, A(25) => mux_A_25_port, A(24) =>
mux_A_24_port, A(23) => mux_A_23_port, A(22) =>
mux_A_22_port, A(21) => mux_A_21_port, A(20) =>
mux_A_20_port, A(19) => mux_A_19_port, A(18) =>
mux_A_18_port, A(17) => mux_A_17_port, A(16) =>
mux_A_16_port, A(15) => mux_A_15_port, A(14) =>
mux_A_14_port, A(13) => mux_A_13_port, A(12) =>
mux_A_12_port, A(11) => mux_A_11_port, A(10) =>
mux_A_10_port, A(9) => mux_A_9_port, A(8) =>
mux_A_8_port, A(7) => mux_A_7_port, A(6) =>
mux_A_6_port, A(5) => mux_A_5_port, A(4) =>
mux_A_4_port, A(3) => mux_A_3_port, A(2) =>
mux_A_2_port, A(1) => mux_A_1_port, A(0) =>
mux_A_0_port, B(31) => mux_B_31_port, B(30) =>
mux_B_30_port, B(29) => mux_B_29_port, B(28) =>
mux_B_28_port, B(27) => mux_B_27_port, B(26) =>
mux_B_26_port, B(25) => mux_B_25_port, B(24) =>
mux_B_24_port, B(23) => mux_B_23_port, B(22) =>
mux_B_22_port, B(21) => mux_B_21_port, B(20) =>
mux_B_20_port, B(19) => mux_B_19_port, B(18) =>
mux_B_18_port, B(17) => mux_B_17_port, B(16) =>
mux_B_16_port, B(15) => mux_B_15_port, B(14) =>
mux_B_14_port, B(13) => mux_B_13_port, B(12) =>
mux_B_12_port, B(11) => mux_B_11_port, B(10) =>
mux_B_10_port, B(9) => mux_B_9_port, B(8) =>
mux_B_8_port, B(7) => mux_B_7_port, B(6) =>
mux_B_6_port, B(5) => mux_B_5_port, B(4) =>
mux_B_4_port, B(3) => mux_B_3_port, B(2) =>
mux_B_2_port, B(1) => mux_B_1_port, B(0) =>
mux_B_0_port, Cin => X_Logic0_port, sign => mux_sign
, S(31) => sum_out_31_port, S(30) => sum_out_30_port
, S(29) => sum_out_29_port, S(28) => sum_out_28_port
, S(27) => sum_out_27_port, S(26) => sum_out_26_port
, S(25) => sum_out_25_port, S(24) => sum_out_24_port
, S(23) => sum_out_23_port, S(22) => sum_out_22_port
, S(21) => sum_out_21_port, S(20) => sum_out_20_port
, S(19) => n120, S(18) => sum_out_18_port, S(17) =>
sum_out_17_port, S(16) => sum_out_16_port, S(15) =>
sum_out_15_port, S(14) => sum_out_14_port, S(13) =>
sum_out_13_port, S(12) => sum_out_12_port, S(11) =>
sum_out_11_port, S(10) => sum_out_10_port, S(9) =>
sum_out_9_port, S(8) => sum_out_8_port, S(7) =>
sum_out_7_port, S(6) => sum_out_6_port, S(5) =>
sum_out_5_port, S(4) => sum_out_4_port, S(3) =>
sum_out_3_port, S(2) => sum_out_2_port, S(1) =>
sum_out_1_port, S(0) => sum_out_0_port, Cout =>
carry_from_adder);
COMP : comparator_M32 port map( C => carry_from_adder, V => overflow,
SUM(31) => sum_out_31_port, SUM(30) =>
sum_out_30_port, SUM(29) => sum_out_29_port, SUM(28)
=> sum_out_28_port, SUM(27) => sum_out_27_port,
SUM(26) => sum_out_26_port, SUM(25) =>
sum_out_25_port, SUM(24) => sum_out_24_port, SUM(23)
=> sum_out_23_port, SUM(22) => sum_out_22_port,
SUM(21) => sum_out_21_port, SUM(20) =>
sum_out_20_port, SUM(19) => n120, SUM(18) =>
sum_out_18_port, SUM(17) => sum_out_17_port, SUM(16)
=> sum_out_16_port, SUM(15) => sum_out_15_port,
SUM(14) => sum_out_14_port, SUM(13) =>
sum_out_13_port, SUM(12) => sum_out_12_port, SUM(11)
=> sum_out_11_port, SUM(10) => sum_out_10_port,
SUM(9) => sum_out_9_port, SUM(8) => sum_out_8_port,
SUM(7) => sum_out_7_port, SUM(6) => sum_out_6_port,
SUM(5) => sum_out_5_port, SUM(4) => sum_out_4_port,
SUM(3) => sum_out_3_port, SUM(2) => sum_out_2_port,
SUM(1) => sum_out_1_port, SUM(0) => sum_out_0_port,
sel(2) => ALUW_i(4), sel(1) => ALUW_i(3), sel(0) =>
ALUW_i(2), sign => ALUW_i(0), S => comp_out);
SHIFT : shifter port map( A(31) => IN1(31), A(30) => IN1(30), A(29) =>
IN1(29), A(28) => IN1(28), A(27) => IN1(27), A(26)
=> IN1(26), A(25) => IN1(25), A(24) => IN1(24),
A(23) => IN1(23), A(22) => IN1(22), A(21) => IN1(21)
, A(20) => IN1(20), A(19) => IN1(19), A(18) =>
IN1(18), A(17) => IN1(17), A(16) => IN1(16), A(15)
=> IN1(15), A(14) => IN1(14), A(13) => IN1(13),
A(12) => IN1(12), A(11) => IN1(11), A(10) => IN1(10)
, A(9) => IN1(9), A(8) => IN1(8), A(7) => IN1(7),
A(6) => IN1(6), A(5) => IN1(5), A(4) => IN1(4), A(3)
=> IN1(3), A(2) => IN1(2), A(1) => IN1(1), A(0) =>
IN1(0), B(4) => n178, B(3) => n180, B(2) => n186,
B(1) => n181, B(0) => n184, LOGIC_ARITH => ALUW_i(8)
, LEFT_RIGHT => ALUW_i(9), OUTPUT(31) =>
shift_out_31_port, OUTPUT(30) => shift_out_30_port,
OUTPUT(29) => shift_out_29_port, OUTPUT(28) =>
shift_out_28_port, OUTPUT(27) => shift_out_27_port,
OUTPUT(26) => shift_out_26_port, OUTPUT(25) =>
shift_out_25_port, OUTPUT(24) => shift_out_24_port,
OUTPUT(23) => shift_out_23_port, OUTPUT(22) =>
shift_out_22_port, OUTPUT(21) => shift_out_21_port,
OUTPUT(20) => shift_out_20_port, OUTPUT(19) =>
shift_out_19_port, OUTPUT(18) => shift_out_18_port,
OUTPUT(17) => shift_out_17_port, OUTPUT(16) =>
shift_out_16_port, OUTPUT(15) => shift_out_15_port,
OUTPUT(14) => shift_out_14_port, OUTPUT(13) =>
shift_out_13_port, OUTPUT(12) => shift_out_12_port,
OUTPUT(11) => shift_out_11_port, OUTPUT(10) =>
shift_out_10_port, OUTPUT(9) => shift_out_9_port,
OUTPUT(8) => shift_out_8_port, OUTPUT(7) =>
shift_out_7_port, OUTPUT(6) => shift_out_6_port,
OUTPUT(5) => shift_out_5_port, OUTPUT(4) =>
shift_out_4_port, OUTPUT(3) => shift_out_3_port,
OUTPUT(2) => shift_out_2_port, OUTPUT(1) =>
shift_out_1_port, OUTPUT(0) => shift_out_0_port);
LU : logic_unit_SIZE32 port map( IN1(31) => IN1(31), IN1(30) => IN1(30),
IN1(29) => IN1(29), IN1(28) => IN1(28), IN1(27) =>
IN1(27), IN1(26) => IN1(26), IN1(25) => IN1(25),
IN1(24) => IN1(24), IN1(23) => IN1(23), IN1(22) =>
IN1(22), IN1(21) => IN1(21), IN1(20) => IN1(20),
IN1(19) => IN1(19), IN1(18) => IN1(18), IN1(17) =>
IN1(17), IN1(16) => IN1(16), IN1(15) => IN1(15),
IN1(14) => IN1(14), IN1(13) => IN1(13), IN1(12) =>
IN1(12), IN1(11) => IN1(11), IN1(10) => IN1(10),
IN1(9) => IN1(9), IN1(8) => IN1(8), IN1(7) => IN1(7)
, IN1(6) => IN1(6), IN1(5) => IN1(5), IN1(4) =>
IN1(4), IN1(3) => IN1(3), IN1(2) => IN1(2), IN1(1)
=> IN1(1), IN1(0) => IN1(0), IN2(31) => IN2(31),
IN2(30) => IN2(30), IN2(29) => IN2(29), IN2(28) =>
IN2(28), IN2(27) => IN2(27), IN2(26) => IN2(26),
IN2(25) => IN2(25), IN2(24) => IN2(24), IN2(23) =>
IN2(23), IN2(22) => IN2(22), IN2(21) => IN2(21),
IN2(20) => IN2(20), IN2(19) => n148, IN2(18) =>
IN2(18), IN2(17) => n146, IN2(16) => IN2(16),
IN2(15) => n177, IN2(14) => IN2(14), IN2(13) =>
IN2(13), IN2(12) => n170, IN2(11) => n175, IN2(10)
=> n147, IN2(9) => n176, IN2(8) => IN2(8), IN2(7) =>
n171, IN2(6) => n173, IN2(5) => n183, IN2(4) => n178
, IN2(3) => n180, IN2(2) => n186, IN2(1) => n181,
IN2(0) => n184, CTRL(1) => ALUW_i(6), CTRL(0) =>
ALUW_i(5), OUT1(31) => lu_out_31_port, OUT1(30) =>
lu_out_30_port, OUT1(29) => lu_out_29_port, OUT1(28)
=> lu_out_28_port, OUT1(27) => lu_out_27_port,
OUT1(26) => lu_out_26_port, OUT1(25) =>
lu_out_25_port, OUT1(24) => lu_out_24_port, OUT1(23)
=> lu_out_23_port, OUT1(22) => lu_out_22_port,
OUT1(21) => lu_out_21_port, OUT1(20) =>
lu_out_20_port, OUT1(19) => lu_out_19_port, OUT1(18)
=> lu_out_18_port, OUT1(17) => lu_out_17_port,
OUT1(16) => lu_out_16_port, OUT1(15) =>
lu_out_15_port, OUT1(14) => lu_out_14_port, OUT1(13)
=> lu_out_13_port, OUT1(12) => lu_out_12_port,
OUT1(11) => lu_out_11_port, OUT1(10) =>
lu_out_10_port, OUT1(9) => lu_out_9_port, OUT1(8) =>
lu_out_8_port, OUT1(7) => lu_out_7_port, OUT1(6) =>
lu_out_6_port, OUT1(5) => lu_out_5_port, OUT1(4) =>
lu_out_4_port, OUT1(3) => lu_out_3_port, OUT1(2) =>
lu_out_2_port, OUT1(1) => lu_out_1_port, OUT1(0) =>
lu_out_0_port);
U141 : MUX2_X1 port map( A => IN2(13), B => B_booth_to_add_13_port, S =>
ALUW_i(1), Z => mux_B_13_port);
U137 : MUX2_X1 port map( A => IN2(17), B => B_booth_to_add_17_port, S =>
ALUW_i(1), Z => mux_B_17_port);
U129 : MUX2_X1 port map( A => IN2(24), B => B_booth_to_add_24_port, S =>
ALUW_i(1), Z => mux_B_24_port);
U128 : MUX2_X1 port map( A => IN2(25), B => B_booth_to_add_25_port, S =>
ALUW_i(1), Z => mux_B_25_port);
U127 : MUX2_X1 port map( A => IN2(26), B => B_booth_to_add_26_port, S =>
ALUW_i(1), Z => mux_B_26_port);
U126 : MUX2_X1 port map( A => IN2(27), B => B_booth_to_add_27_port, S =>
ALUW_i(1), Z => mux_B_27_port);
U125 : MUX2_X1 port map( A => IN2(28), B => B_booth_to_add_28_port, S =>
ALUW_i(1), Z => mux_B_28_port);
U122 : MUX2_X1 port map( A => IN2(30), B => B_booth_to_add_30_port, S =>
ALUW_i(1), Z => mux_B_30_port);
U121 : MUX2_X1 port map( A => IN2(31), B => B_booth_to_add_31_port, S =>
ALUW_i(1), Z => mux_B_31_port);
U118 : MUX2_X1 port map( A => IN2(5), B => B_booth_to_add_5_port, S =>
ALUW_i(1), Z => mux_B_5_port);
U117 : MUX2_X1 port map( A => IN2(6), B => B_booth_to_add_6_port, S =>
ALUW_i(1), Z => mux_B_6_port);
U135 : MUX2_X1 port map( A => IN2(19), B => B_booth_to_add_19_port, S =>
ALUW_i(1), Z => mux_B_19_port);
U131 : MUX2_X1 port map( A => IN2(22), B => B_booth_to_add_22_port, S =>
ALUW_i(1), Z => mux_B_22_port);
U29 : AOI22_X1 port map( A1 => n187, A2 => lu_out_31_port, B1 => n123, B2 =>
IN2(31), ZN => n39);
U28 : NAND2_X1 port map( A1 => n38, A2 => n39, ZN => DOUT(31));
U70 : AOI22_X1 port map( A1 => n122, A2 => shift_out_19_port, B1 => n121, B2
=> mult_out_19_port, ZN => n81);
U65 : AOI22_X1 port map( A1 => n187, A2 => lu_out_20_port, B1 => n123, B2 =>
IN2(20), ZN => n74);
U64 : AOI22_X1 port map( A1 => n122, A2 => shift_out_20_port, B1 => n121, B2
=> mult_out_20_port, ZN => n75);
U61 : AOI22_X1 port map( A1 => n122, A2 => shift_out_21_port, B1 => n121, B2
=> mult_out_21_port, ZN => n72);
U27 : NAND2_X1 port map( A1 => sum_out_3_port, A2 => n124, ZN => n35);
U25 : AOI22_X1 port map( A1 => n15, A2 => shift_out_3_port, B1 => n121, B2
=> mult_out_3_port, ZN => n37);
U59 : AOI22_X1 port map( A1 => n187, A2 => lu_out_22_port, B1 => n123, B2 =>
IN2(22), ZN => n68);
U58 : AOI22_X1 port map( A1 => n122, A2 => shift_out_22_port, B1 => n121, B2
=> mult_out_22_port, ZN => n69);
U53 : AOI22_X1 port map( A1 => n187, A2 => lu_out_24_port, B1 => n123, B2 =>
IN2(24), ZN => n62);
U52 : AOI22_X1 port map( A1 => n122, A2 => shift_out_24_port, B1 => n121, B2
=> mult_out_24_port, ZN => n63);
U84 : NAND2_X1 port map( A1 => sum_out_15_port, A2 => n124, ZN => n91);
U82 : AOI22_X1 port map( A1 => n122, A2 => shift_out_15_port, B1 => n121, B2
=> mult_out_15_port, ZN => n93);
U12 : NAND2_X1 port map( A1 => sum_out_8_port, A2 => n124, ZN => n20);
U10 : AOI22_X1 port map( A1 => n122, A2 => shift_out_8_port, B1 => n121, B2
=> mult_out_8_port, ZN => n22);
U18 : NAND2_X1 port map( A1 => sum_out_6_port, A2 => n124, ZN => n26);
U16 : AOI22_X1 port map( A1 => n15, A2 => shift_out_6_port, B1 => n121, B2
=> mult_out_6_port, ZN => n28);
U50 : AOI22_X1 port map( A1 => n187, A2 => lu_out_25_port, B1 => n123, B2 =>
IN2(25), ZN => n59);
U49 : AOI22_X1 port map( A1 => n122, A2 => shift_out_25_port, B1 => n121, B2
=> mult_out_25_port, ZN => n60);
U78 : NAND2_X1 port map( A1 => sum_out_17_port, A2 => n124, ZN => n85);
U76 : AOI22_X1 port map( A1 => n122, A2 => shift_out_17_port, B1 => n16, B2
=> mult_out_17_port, ZN => n87);
U91 : AOI22_X1 port map( A1 => n122, A2 => shift_out_12_port, B1 => n121, B2
=> mult_out_12_port, ZN => n102);
U80 : AOI22_X1 port map( A1 => n187, A2 => lu_out_16_port, B1 => n123, B2 =>
IN2(16), ZN => n89);
U79 : AOI22_X1 port map( A1 => n122, A2 => shift_out_16_port, B1 => n121, B2
=> mult_out_16_port, ZN => n90);
U42 : NAND2_X1 port map( A1 => n172, A2 => n124, ZN => n49);
U41 : AOI22_X1 port map( A1 => n187, A2 => lu_out_28_port, B1 => n123, B2 =>
IN2(28), ZN => n50);
U40 : AOI22_X1 port map( A1 => n15, A2 => shift_out_28_port, B1 => n121, B2
=> mult_out_28_port, ZN => n51);
U24 : NAND2_X1 port map( A1 => sum_out_4_port, A2 => n124, ZN => n32);
U23 : AOI22_X1 port map( A1 => n187, A2 => lu_out_4_port, B1 => n123, B2 =>
n178, ZN => n33);
U22 : AOI22_X1 port map( A1 => n122, A2 => shift_out_4_port, B1 => n121, B2
=> mult_out_4_port, ZN => n34);
U45 : NAND2_X1 port map( A1 => sum_out_27_port, A2 => n124, ZN => n52);
U44 : AOI22_X1 port map( A1 => n187, A2 => lu_out_27_port, B1 => n123, B2 =>
IN2(27), ZN => n53);
U43 : AOI22_X1 port map( A1 => n122, A2 => shift_out_27_port, B1 => n121, B2
=> mult_out_27_port, ZN => n54);
U21 : NAND2_X1 port map( A1 => sum_out_5_port, A2 => n124, ZN => n29);
U19 : AOI22_X1 port map( A1 => n122, A2 => shift_out_5_port, B1 => n121, B2
=> mult_out_5_port, ZN => n31);
U90 : NAND2_X1 port map( A1 => sum_out_13_port, A2 => n124, ZN => n97);
U88 : AOI22_X1 port map( A1 => n122, A2 => shift_out_13_port, B1 => n121, B2
=> mult_out_13_port, ZN => n99);
U9 : NAND2_X1 port map( A1 => sum_out_9_port, A2 => n124, ZN => n12);
U7 : AOI22_X1 port map( A1 => n122, A2 => shift_out_9_port, B1 => n121, B2
=> mult_out_9_port, ZN => n14);
U15 : NAND2_X1 port map( A1 => sum_out_7_port, A2 => n124, ZN => n23);
U13 : AOI22_X1 port map( A1 => n122, A2 => shift_out_7_port, B1 => n121, B2
=> mult_out_7_port, ZN => n25);
U87 : NAND2_X1 port map( A1 => sum_out_14_port, A2 => n124, ZN => n94);
U85 : AOI22_X1 port map( A1 => n122, A2 => shift_out_14_port, B1 => n121, B2
=> mult_out_14_port, ZN => n96);
U73 : AOI22_X1 port map( A1 => n122, A2 => shift_out_18_port, B1 => n16, B2
=> mult_out_18_port, ZN => n84);
U55 : AOI22_X1 port map( A1 => n122, A2 => shift_out_23_port, B1 => n121, B2
=> mult_out_23_port, ZN => n66);
U46 : AOI22_X1 port map( A1 => n122, A2 => shift_out_26_port, B1 => n16, B2
=> mult_out_26_port, ZN => n57);
U38 : AOI22_X1 port map( A1 => n187, A2 => lu_out_29_port, B1 => n123, B2 =>
IN2(29), ZN => n47);
U37 : AOI22_X1 port map( A1 => n122, A2 => shift_out_29_port, B1 => n121, B2
=> mult_out_29_port, ZN => n48);
U36 : NAND2_X1 port map( A1 => sum_out_2_port, A2 => n124, ZN => n43);
U35 : AOI22_X1 port map( A1 => n187, A2 => lu_out_2_port, B1 => n123, B2 =>
n186, ZN => n44);
U34 : AOI22_X1 port map( A1 => n122, A2 => shift_out_2_port, B1 => n121, B2
=> mult_out_2_port, ZN => n45);
U69 : NAND2_X1 port map( A1 => sum_out_1_port, A2 => n124, ZN => n76);
U67 : AOI22_X1 port map( A1 => n122, A2 => shift_out_1_port, B1 => n121, B2
=> mult_out_1_port, ZN => n78);
U32 : AOI22_X1 port map( A1 => n187, A2 => lu_out_30_port, B1 => n123, B2 =>
IN2(30), ZN => n41);
U31 : AOI22_X1 port map( A1 => n122, A2 => shift_out_30_port, B1 => n121, B2
=> mult_out_30_port, ZN => n42);
U96 : NAND2_X1 port map( A1 => sum_out_11_port, A2 => n124, ZN => n103);
U94 : AOI22_X1 port map( A1 => n122, A2 => shift_out_11_port, B1 => n121, B2
=> mult_out_11_port, ZN => n105);
U99 : NAND2_X1 port map( A1 => sum_out_10_port, A2 => n124, ZN => n106);
U97 : AOI22_X1 port map( A1 => n122, A2 => shift_out_10_port, B1 => n121, B2
=> mult_out_10_port, ZN => n108);
U108 : NOR3_X1 port map( A1 => ALUW_i(12), A2 => ALUW_i(11), A3 => n115, ZN
=> n17);
U166 : MUX2_X1 port map( A => IN1(1), B => A_booth_to_add_1_port, S =>
ALUW_i(1), Z => mux_A_1_port);
U168 : MUX2_X1 port map( A => IN1(18), B => A_booth_to_add_18_port, S =>
ALUW_i(1), Z => mux_A_18_port);
U173 : MUX2_X1 port map( A => IN1(13), B => A_booth_to_add_13_port, S =>
ALUW_i(1), Z => mux_A_13_port);
U176 : MUX2_X1 port map( A => IN1(10), B => A_booth_to_add_10_port, S =>
ALUW_i(1), Z => mux_A_10_port);
U149 : MUX2_X1 port map( A => IN1(6), B => A_booth_to_add_6_port, S =>
ALUW_i(1), Z => mux_A_6_port);
U5 : INV_X1 port map( A => IN2(31), ZN => n10);
U4 : INV_X1 port map( A => IN1(31), ZN => n11);
U111 : INV_X1 port map( A => ALUW_i(10), ZN => n115);
U105 : INV_X1 port map( A => ALUW_i(12), ZN => n112);
U2 : NAND2_X1 port map( A1 => ALUW_i(1), A2 => B_booth_to_add_3_port, ZN =>
n109);
U3 : NAND2_X1 port map( A1 => n132, A2 => n109, ZN => mux_B_3_port);
U6 : AOI22_X1 port map( A1 => ALUW_i(1), A2 => B_booth_to_add_8_port, B1 =>
n127, B2 => IN2(8), ZN => n110);
U8 : INV_X1 port map( A => n110, ZN => mux_B_8_port);
U11 : INV_X1 port map( A => ALUW_i(1), ZN => n111);
U14 : NOR2_X1 port map( A1 => valid_from_booth, A2 => n111, ZN => stall_o);
U17 : AOI22_X1 port map( A1 => ALUW_i(1), A2 => B_booth_to_add_29_port, B1
=> n127, B2 => IN2(29), ZN => n114);
U20 : INV_X1 port map( A => n114, ZN => mux_B_29_port);
U26 : INV_X1 port map( A => ALUW_i(11), ZN => n116);
U30 : NOR3_X1 port map( A1 => ALUW_i(12), A2 => n115, A3 => n116, ZN => n143
);
U33 : AOI22_X1 port map( A1 => A_booth_to_add_2_port, A2 => ALUW_i(1), B1 =>
n127, B2 => IN1(2), ZN => n117);
U39 : INV_X1 port map( A => n117, ZN => mux_A_2_port);
U47 : AOI222_X1 port map( A1 => sum_out_0_port, A2 => n124, B1 => n184, B2
=> n123, C1 => n17, C2 => lu_out_0_port, ZN => n118)
;
U48 : INV_X1 port map( A => n118, ZN => n119);
U51 : AOI21_X1 port map( B1 => n121, B2 => mult_out_0_port, A => n119, ZN =>
n141);
U54 : CLKBUF_X1 port map( A => sum_out_20_port, Z => n179);
U56 : INV_X2 port map( A => ALUW_i(1), ZN => n127);
U57 : BUF_X1 port map( A => sum_out_21_port, Z => n174);
U60 : BUF_X1 port map( A => IN2(1), Z => n181);
U62 : MUX2_X1 port map( A => IN1(0), B => A_booth_to_add_0_port, S =>
ALUW_i(1), Z => mux_A_0_port);
U63 : BUF_X2 port map( A => n16, Z => n121);
U66 : BUF_X2 port map( A => n18, Z => n123);
U68 : BUF_X2 port map( A => n19, Z => n124);
U71 : BUF_X1 port map( A => IN2(2), Z => n186);
U72 : BUF_X1 port map( A => IN2(15), Z => n177);
U74 : MUX2_X1 port map( A => IN1(5), B => A_booth_to_add_5_port, S =>
ALUW_i(1), Z => mux_A_5_port);
U75 : BUF_X2 port map( A => n17, Z => n187);
U77 : BUF_X2 port map( A => n15, Z => n122);
U81 : BUF_X1 port map( A => IN2(4), Z => n178);
U83 : NAND2_X1 port map( A1 => n139, A2 => n140, ZN => mux_B_0_port);
U86 : NAND2_X1 port map( A1 => n144, A2 => n145, ZN => DOUT(0));
U89 : NAND2_X1 port map( A1 => IN2(4), A2 => n127, ZN => n125);
U92 : NAND2_X1 port map( A1 => n125, A2 => n126, ZN => mux_B_4_port);
U93 : NAND2_X1 port map( A1 => B_booth_to_add_4_port, A2 => ALUW_i(1), ZN =>
n126);
U95 : NAND2_X1 port map( A1 => B_booth_to_add_20_port, A2 => ALUW_i(1), ZN
=> n129);
U98 : NAND2_X1 port map( A1 => IN2(20), A2 => n127, ZN => n128);
U100 : NAND2_X1 port map( A1 => n128, A2 => n129, ZN => mux_B_20_port);
U101 : NAND2_X1 port map( A1 => B_booth_to_add_7_port, A2 => ALUW_i(1), ZN
=> n130);
U102 : NAND2_X1 port map( A1 => n131, A2 => n130, ZN => mux_B_7_port);
U103 : NAND2_X1 port map( A1 => IN2(7), A2 => n127, ZN => n131);
U104 : NAND2_X1 port map( A1 => IN2(3), A2 => n127, ZN => n132);
U106 : NAND2_X1 port map( A1 => B_booth_to_add_9_port, A2 => ALUW_i(1), ZN
=> n133);
U107 : NAND2_X1 port map( A1 => n134, A2 => n133, ZN => mux_B_9_port);
U109 : NAND2_X1 port map( A1 => IN2(9), A2 => n127, ZN => n134);
U110 : NAND2_X1 port map( A1 => B_booth_to_add_12_port, A2 => ALUW_i(1), ZN
=> n136);
U113 : NAND2_X1 port map( A1 => IN2(12), A2 => n127, ZN => n135);
U114 : NAND2_X1 port map( A1 => n135, A2 => n136, ZN => mux_B_12_port);
U115 : NAND2_X1 port map( A1 => B_booth_to_add_23_port, A2 => ALUW_i(1), ZN
=> n138);
U116 : NAND2_X1 port map( A1 => IN2(23), A2 => n127, ZN => n137);
U119 : NAND2_X1 port map( A1 => n137, A2 => n138, ZN => mux_B_23_port);
U120 : NAND2_X1 port map( A1 => B_booth_to_add_0_port, A2 => ALUW_i(1), ZN
=> n140);
U123 : NAND2_X1 port map( A1 => IN2(0), A2 => n127, ZN => n139);
U124 : NAND2_X1 port map( A1 => shift_out_0_port, A2 => n15, ZN => n142);
U130 : AND2_X1 port map( A1 => n142, A2 => n141, ZN => n145);
U132 : NAND2_X1 port map( A1 => comp_out, A2 => n143, ZN => n144);
U133 : NAND2_X4 port map( A1 => n156, A2 => n157, ZN => mux_sign);
U134 : CLKBUF_X1 port map( A => IN2(17), Z => n146);
U136 : CLKBUF_X1 port map( A => IN2(10), Z => n147);
U138 : CLKBUF_X1 port map( A => IN2(19), Z => n148);
U139 : BUF_X1 port map( A => sum_out_25_port, Z => n149);
U142 : BUF_X1 port map( A => sum_out_24_port, Z => n150);
U144 : CLKBUF_X1 port map( A => IN2(11), Z => n175);
U145 : CLKBUF_X1 port map( A => IN2(7), Z => n171);
U150 : CLKBUF_X1 port map( A => IN2(9), Z => n176);
U155 : CLKBUF_X1 port map( A => IN2(5), Z => n183);
U177 : CLKBUF_X1 port map( A => IN2(12), Z => n170);
U208 : CLKBUF_X1 port map( A => IN2(6), Z => n173);
U209 : INV_X1 port map( A => n182, ZN => n185);
U210 : CLKBUF_X1 port map( A => n9, Z => n182);
U211 : CLKBUF_X1 port map( A => sum_out_29_port, Z => n168);
U212 : CLKBUF_X1 port map( A => sum_out_22_port, Z => n169);
U213 : CLKBUF_X1 port map( A => sum_out_28_port, Z => n172);
U214 : INV_X1 port map( A => ALUW_i(11), ZN => n113);
U215 : CLKBUF_X1 port map( A => IN2(3), Z => n180);
U216 : CLKBUF_X1 port map( A => IN2(0), Z => n184);
U217 : INV_X1 port map( A => sum_out_31_port, ZN => n9);
U218 : OR2_X1 port map( A1 => ALUW_i(1), A2 => n155, ZN => n157);
U219 : INV_X1 port map( A => ALUW_i(7), ZN => n155);
U220 : NOR2_X1 port map( A1 => n123, A2 => n112, ZN => n16);
U221 : NOR3_X1 port map( A1 => ALUW_i(10), A2 => ALUW_i(12), A3 => n113, ZN
=> n15);
U222 : NAND2_X1 port map( A1 => ALUW_i(1), A2 => sign_booth_to_add, ZN =>
n156);
U223 : NOR3_X1 port map( A1 => ALUW_i(10), A2 => ALUW_i(12), A3 =>
ALUW_i(11), ZN => n19);
U224 : NOR3_X1 port map( A1 => ALUW_i(10), A2 => ALUW_i(11), A3 => n112, ZN
=> n18);
U225 : NAND2_X1 port map( A1 => IN2(16), A2 => n127, ZN => n151);
U226 : NAND2_X1 port map( A1 => n151, A2 => n152, ZN => mux_B_16_port);
U227 : NAND2_X1 port map( A1 => B_booth_to_add_16_port, A2 => ALUW_i(1), ZN
=> n152);
U228 : NAND2_X1 port map( A1 => IN2(18), A2 => n127, ZN => n153);
U229 : NAND2_X1 port map( A1 => n153, A2 => n154, ZN => mux_B_18_port);
U230 : NAND2_X1 port map( A1 => B_booth_to_add_18_port, A2 => ALUW_i(1), ZN
=> n154);
U231 : NAND2_X1 port map( A1 => B_booth_to_add_1_port, A2 => ALUW_i(1), ZN
=> n159);
U232 : NAND2_X1 port map( A1 => B_booth_to_add_2_port, A2 => ALUW_i(1), ZN
=> n161);
U233 : NAND2_X1 port map( A1 => B_booth_to_add_21_port, A2 => ALUW_i(1), ZN
=> n165);
U234 : NAND2_X1 port map( A1 => B_booth_to_add_15_port, A2 => ALUW_i(1), ZN
=> n167);
U235 : NAND2_X1 port map( A1 => IN2(1), A2 => n127, ZN => n158);
U236 : NAND2_X1 port map( A1 => n158, A2 => n159, ZN => mux_B_1_port);
U237 : NAND2_X1 port map( A1 => IN2(2), A2 => n127, ZN => n160);
U238 : NAND2_X1 port map( A1 => n160, A2 => n161, ZN => mux_B_2_port);
U239 : NAND2_X1 port map( A1 => IN2(10), A2 => n127, ZN => n162);
U240 : NAND2_X1 port map( A1 => n162, A2 => n163, ZN => mux_B_10_port);
U241 : NAND2_X1 port map( A1 => B_booth_to_add_10_port, A2 => ALUW_i(1), ZN
=> n163);
U242 : NAND2_X1 port map( A1 => IN2(21), A2 => n127, ZN => n164);
U243 : NAND2_X1 port map( A1 => n164, A2 => n165, ZN => mux_B_21_port);
U244 : NAND2_X1 port map( A1 => IN2(15), A2 => n127, ZN => n166);
U245 : NAND2_X1 port map( A1 => n166, A2 => n167, ZN => mux_B_15_port);
U246 : AOI22_X1 port map( A1 => n187, A2 => lu_out_18_port, B1 => n123, B2
=> IN2(18), ZN => n83);
U247 : NAND2_X1 port map( A1 => n169, A2 => n124, ZN => n67);
U248 : AOI22_X1 port map( A1 => n17, A2 => lu_out_10_port, B1 => n123, B2 =>
n147, ZN => n107);
U249 : NAND2_X1 port map( A1 => sum_out_26_port, A2 => n124, ZN => n55);
U250 : AOI22_X1 port map( A1 => n187, A2 => lu_out_21_port, B1 => n123, B2
=> IN2(21), ZN => n71);
U251 : AOI22_X1 port map( A1 => n187, A2 => lu_out_26_port, B1 => n123, B2
=> IN2(26), ZN => n56);
U252 : NAND2_X1 port map( A1 => n168, A2 => n124, ZN => n46);
U253 : AOI22_X1 port map( A1 => n187, A2 => lu_out_12_port, B1 => n123, B2
=> n170, ZN => n101);
U254 : NAND2_X1 port map( A1 => n179, A2 => n124, ZN => n73);
U255 : NAND2_X1 port map( A1 => n174, A2 => n124, ZN => n70);
U256 : NAND2_X1 port map( A1 => sum_out_12_port, A2 => n124, ZN => n100);
U257 : AOI22_X1 port map( A1 => n187, A2 => lu_out_3_port, B1 => n123, B2 =>
n180, ZN => n36);
U258 : AOI22_X1 port map( A1 => n187, A2 => lu_out_1_port, B1 => n123, B2 =>
n181, ZN => n77);
U259 : AOI22_X1 port map( A1 => n187, A2 => lu_out_17_port, B1 => n123, B2
=> n146, ZN => n86);
U260 : AOI22_X1 port map( A1 => n17, A2 => lu_out_14_port, B1 => n123, B2 =>
IN2(14), ZN => n95);
U261 : AOI22_X1 port map( A1 => n187, A2 => lu_out_23_port, B1 => n123, B2
=> IN2(23), ZN => n65);
U262 : AOI22_X1 port map( A1 => n187, A2 => lu_out_13_port, B1 => n123, B2
=> IN2(13), ZN => n98);
U263 : NAND2_X1 port map( A1 => n120, A2 => n124, ZN => n79);
U264 : AOI22_X1 port map( A1 => n187, A2 => lu_out_8_port, B1 => n123, B2 =>
IN2(8), ZN => n21);
U265 : AOI22_X1 port map( A1 => n187, A2 => lu_out_6_port, B1 => n123, B2 =>
n173, ZN => n27);
U266 : AOI22_X1 port map( A1 => n187, A2 => lu_out_19_port, B1 => n123, B2
=> n148, ZN => n80);
U267 : NAND2_X1 port map( A1 => sum_out_16_port, A2 => n124, ZN => n88);
U268 : NAND2_X1 port map( A1 => sum_out_18_port, A2 => n124, ZN => n82);
U269 : AOI22_X1 port map( A1 => n187, A2 => lu_out_15_port, B1 => n123, B2
=> n177, ZN => n92);
U270 : AOI22_X1 port map( A1 => n187, A2 => lu_out_11_port, B1 => n123, B2
=> n175, ZN => n104);
U271 : AOI22_X1 port map( A1 => n187, A2 => lu_out_7_port, B1 => n123, B2 =>
n171, ZN => n24);
U272 : NAND2_X1 port map( A1 => n149, A2 => n124, ZN => n58);
U273 : NAND2_X1 port map( A1 => sum_out_23_port, A2 => n124, ZN => n64);
U274 : NAND2_X1 port map( A1 => sum_out_30_port, A2 => n124, ZN => n40);
U275 : AOI222_X1 port map( A1 => n185, A2 => n124, B1 => n122, B2 =>
shift_out_31_port, C1 => n121, C2 =>
mult_out_31_port, ZN => n38);
U276 : AOI22_X1 port map( A1 => n187, A2 => lu_out_9_port, B1 => n123, B2 =>
n176, ZN => n13);
U277 : NAND2_X1 port map( A1 => n150, A2 => n124, ZN => n61);
U278 : AOI22_X1 port map( A1 => n187, A2 => lu_out_5_port, B1 => n123, B2 =>
n183, ZN => n30);
end SYN_Bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity mux21_0 is
port( IN0, IN1 : in std_logic_vector (31 downto 0); CTRL : in std_logic;
OUT1 : out std_logic_vector (31 downto 0));
end mux21_0;
architecture SYN_Bhe of mux21_0 is
component MUX2_X1
port( A, B, S : in std_logic; Z : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component MUX2_X2
port( A, B, S : in std_logic; Z : out std_logic);
end component;
signal n4, n5, n6, n7, n8, n9, n10, n11, n12 : std_logic;
begin
U5 : MUX2_X1 port map( A => IN0(5), B => IN1(5), S => CTRL, Z => OUT1(5));
U6 : MUX2_X1 port map( A => IN0(4), B => IN1(4), S => CTRL, Z => OUT1(4));
U8 : MUX2_X1 port map( A => IN0(31), B => IN1(31), S => CTRL, Z => OUT1(31))
;
U9 : MUX2_X1 port map( A => IN0(30), B => IN1(30), S => CTRL, Z => OUT1(30))
;
U11 : MUX2_X1 port map( A => IN0(29), B => IN1(29), S => CTRL, Z => OUT1(29)
);
U13 : MUX2_X1 port map( A => IN0(27), B => IN1(27), S => CTRL, Z => OUT1(27)
);
U14 : MUX2_X1 port map( A => IN0(26), B => IN1(26), S => CTRL, Z => OUT1(26)
);
U15 : MUX2_X1 port map( A => IN0(25), B => IN1(25), S => CTRL, Z => OUT1(25)
);
U16 : MUX2_X1 port map( A => IN0(24), B => IN1(24), S => CTRL, Z => OUT1(24)
);
U20 : MUX2_X1 port map( A => IN0(20), B => IN1(20), S => CTRL, Z => OUT1(20)
);
U23 : MUX2_X1 port map( A => IN0(18), B => IN1(18), S => CTRL, Z => OUT1(18)
);
U1 : MUX2_X1 port map( A => IN0(16), B => IN1(16), S => CTRL, Z => OUT1(16))
;
U2 : MUX2_X1 port map( A => IN0(22), B => IN1(22), S => CTRL, Z => OUT1(22))
;
U3 : MUX2_X2 port map( A => IN0(23), B => IN1(23), S => CTRL, Z => OUT1(23))
;
U4 : MUX2_X2 port map( A => IN0(13), B => IN1(13), S => CTRL, Z => OUT1(13))
;
U7 : MUX2_X2 port map( A => IN0(14), B => IN1(14), S => CTRL, Z => OUT1(14))
;
U10 : MUX2_X1 port map( A => IN0(17), B => IN1(17), S => CTRL, Z => OUT1(17)
);
U12 : MUX2_X1 port map( A => IN0(15), B => IN1(15), S => CTRL, Z => OUT1(15)
);
U17 : MUX2_X1 port map( A => IN0(10), B => IN1(10), S => CTRL, Z => OUT1(10)
);
U18 : MUX2_X1 port map( A => IN0(8), B => IN1(8), S => CTRL, Z => OUT1(8));
U19 : MUX2_X1 port map( A => IN0(19), B => IN1(19), S => CTRL, Z => OUT1(19)
);
U21 : INV_X1 port map( A => CTRL, ZN => n4);
U22 : NAND2_X1 port map( A1 => n5, A2 => n6, ZN => OUT1(0));
U24 : NAND2_X1 port map( A1 => CTRL, A2 => IN1(0), ZN => n6);
U25 : NAND2_X1 port map( A1 => IN0(0), A2 => n4, ZN => n5);
U26 : NAND2_X1 port map( A1 => IN0(3), A2 => n4, ZN => n7);
U27 : NAND2_X1 port map( A1 => CTRL, A2 => IN1(3), ZN => n8);
U28 : NAND2_X1 port map( A1 => n7, A2 => n8, ZN => OUT1(3));
U29 : NAND2_X1 port map( A1 => n9, A2 => n10, ZN => OUT1(2));
U30 : MUX2_X1 port map( A => IN0(28), B => IN1(28), S => CTRL, Z => OUT1(28)
);
U31 : MUX2_X1 port map( A => IN0(21), B => IN1(21), S => CTRL, Z => OUT1(21)
);
U32 : NAND2_X1 port map( A1 => CTRL, A2 => IN1(2), ZN => n10);
U33 : NAND2_X1 port map( A1 => IN0(2), A2 => n4, ZN => n9);
U34 : MUX2_X1 port map( A => IN0(12), B => IN1(12), S => CTRL, Z => OUT1(12)
);
U35 : MUX2_X1 port map( A => IN0(7), B => IN1(7), S => CTRL, Z => OUT1(7));
U36 : NAND2_X1 port map( A1 => n11, A2 => n12, ZN => OUT1(6));
U37 : MUX2_X1 port map( A => IN0(11), B => IN1(11), S => CTRL, Z => OUT1(11)
);
U38 : MUX2_X1 port map( A => IN0(9), B => IN1(9), S => CTRL, Z => OUT1(9));
U39 : NAND2_X1 port map( A1 => IN0(6), A2 => n4, ZN => n11);
U40 : NAND2_X1 port map( A1 => IN1(6), A2 => CTRL, ZN => n12);
U41 : MUX2_X1 port map( A => IN0(1), B => IN1(1), S => CTRL, Z => OUT1(1));
end SYN_Bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity execute_block is
port( IMM_i, A_i : in std_logic_vector (31 downto 0); rB_i, rC_i : in
std_logic_vector (4 downto 0); MUXED_B_i : in std_logic_vector (31
downto 0); S_MUX_ALUIN_i : in std_logic; FW_X_i, FW_W_i : in
std_logic_vector (31 downto 0); S_FW_A_i, S_FW_B_i : in
std_logic_vector (1 downto 0); muxed_dest : out std_logic_vector (4
downto 0); muxed_B : out std_logic_vector (31 downto 0);
S_MUX_DEST_i : in std_logic_vector (1 downto 0); OP : in aluOp;
ALUW_i : in std_logic_vector (12 downto 0); DOUT : out
std_logic_vector (31 downto 0); stall_o : out std_logic; Clock,
Reset : in std_logic);
end execute_block;
architecture SYN_struct of execute_block is
component mux41_MUX_SIZE32_1
port( IN0, IN1, IN2, IN3 : in std_logic_vector (31 downto 0); CTRL : in
std_logic_vector (1 downto 0); OUT1 : out std_logic_vector (31
downto 0));
end component;
component mux41_MUX_SIZE32_0
port( IN0, IN1, IN2, IN3 : in std_logic_vector (31 downto 0); CTRL : in
std_logic_vector (1 downto 0); OUT1 : out std_logic_vector (31
downto 0));
end component;
component mux41_MUX_SIZE5
port( IN0, IN1, IN2, IN3 : in std_logic_vector (4 downto 0); CTRL : in
std_logic_vector (1 downto 0); OUT1 : out std_logic_vector (4
downto 0));
end component;
component real_alu_DATA_SIZE32
port( IN1, IN2 : in std_logic_vector (31 downto 0); ALUW_i : in
std_logic_vector (12 downto 0); DOUT : out std_logic_vector (31
downto 0); stall_o : out std_logic; Clock, Reset : in std_logic);
end component;
component mux21_0
port( IN0, IN1 : in std_logic_vector (31 downto 0); CTRL : in std_logic;
OUT1 : out std_logic_vector (31 downto 0));
end component;
signal X_Logic1_port, X_Logic0_port, muxed_B_31_port, muxed_B_30_port,
muxed_B_29_port, muxed_B_28_port, muxed_B_27_port, muxed_B_25_port,
muxed_B_24_port, muxed_B_23_port, muxed_B_22_port, muxed_B_21_port,
muxed_B_20_port, muxed_B_19_port, muxed_B_18_port, muxed_B_16_port,
muxed_B_14_port, muxed_B_13_port, muxed_B_12_port, muxed_B_11_port,
muxed_B_10_port, muxed_B_9_port, muxed_B_8_port, muxed_B_7_port,
muxed_B_6_port, muxed_B_5_port, muxed_B_4_port, muxed_B_3_port,
muxed_B_2_port, muxed_B_1_port, muxed_B_0_port, FWB2alu_31_port,
FWB2alu_30_port, FWB2alu_29_port, FWB2alu_28_port, FWB2alu_27_port,
FWB2alu_26_port, FWB2alu_25_port, FWB2alu_24_port, FWB2alu_23_port,
FWB2alu_22_port, FWB2alu_21_port, FWB2alu_20_port, FWB2alu_19_port,
FWB2alu_18_port, FWB2alu_17_port, FWB2alu_16_port, FWB2alu_15_port,
FWB2alu_14_port, FWB2alu_13_port, FWB2alu_12_port, FWB2alu_11_port,
FWB2alu_10_port, FWB2alu_9_port, FWB2alu_8_port, FWB2alu_7_port,
FWB2alu_6_port, FWB2alu_5_port, FWB2alu_4_port, FWB2alu_3_port,
FWB2alu_2_port, FWB2alu_1_port, FWB2alu_0_port, FWA2alu_31_port,
FWA2alu_30_port, FWA2alu_29_port, FWA2alu_28_port, FWA2alu_27_port,
FWA2alu_26_port, FWA2alu_25_port, FWA2alu_24_port, FWA2alu_23_port,
FWA2alu_22_port, FWA2alu_21_port, FWA2alu_20_port, FWA2alu_19_port,
FWA2alu_18_port, FWA2alu_17_port, FWA2alu_16_port, FWA2alu_15_port,
FWA2alu_14_port, FWA2alu_13_port, FWA2alu_12_port, FWA2alu_11_port,
FWA2alu_10_port, FWA2alu_9_port, FWA2alu_8_port, FWA2alu_7_port,
FWA2alu_6_port, FWA2alu_5_port, FWA2alu_4_port, FWA2alu_3_port,
FWA2alu_2_port, FWA2alu_1_port, FWA2alu_0_port, net536481, net536482,
net536483, net536484, net536485, n1, muxed_B_15_port, muxed_B_17_port,
muxed_B_26_port : std_logic;
begin
muxed_B <= ( muxed_B_31_port, muxed_B_30_port, muxed_B_29_port,
muxed_B_28_port, muxed_B_27_port, muxed_B_26_port, muxed_B_25_port,
muxed_B_24_port, muxed_B_23_port, muxed_B_22_port, muxed_B_21_port,
muxed_B_20_port, muxed_B_19_port, muxed_B_18_port, muxed_B_17_port,
muxed_B_16_port, muxed_B_15_port, muxed_B_14_port, muxed_B_13_port,
muxed_B_12_port, muxed_B_11_port, muxed_B_10_port, muxed_B_9_port,
muxed_B_8_port, muxed_B_7_port, muxed_B_6_port, muxed_B_5_port,
muxed_B_4_port, muxed_B_3_port, muxed_B_2_port, muxed_B_1_port,
muxed_B_0_port );
(net536481, net536482, net536483, net536484, net536485) <=
aluOp_to_std_logic_vector(OP);
X_Logic1_port <= '1';
X_Logic0_port <= '0';
n1 <= '0';
ALUIN_MUX : mux21_0 port map( IN0(31) => muxed_B_31_port, IN0(30) =>
muxed_B_30_port, IN0(29) => muxed_B_29_port, IN0(28)
=> muxed_B_28_port, IN0(27) => muxed_B_27_port,
IN0(26) => muxed_B_26_port, IN0(25) =>
muxed_B_25_port, IN0(24) => muxed_B_24_port, IN0(23)
=> muxed_B_23_port, IN0(22) => muxed_B_22_port,
IN0(21) => muxed_B_21_port, IN0(20) =>
muxed_B_20_port, IN0(19) => muxed_B_19_port, IN0(18)
=> muxed_B_18_port, IN0(17) => muxed_B_17_port,
IN0(16) => muxed_B_16_port, IN0(15) =>
muxed_B_15_port, IN0(14) => muxed_B_14_port, IN0(13)
=> muxed_B_13_port, IN0(12) => muxed_B_12_port,
IN0(11) => muxed_B_11_port, IN0(10) =>
muxed_B_10_port, IN0(9) => muxed_B_9_port, IN0(8) =>
muxed_B_8_port, IN0(7) => muxed_B_7_port, IN0(6) =>
muxed_B_6_port, IN0(5) => muxed_B_5_port, IN0(4) =>
muxed_B_4_port, IN0(3) => muxed_B_3_port, IN0(2) =>
muxed_B_2_port, IN0(1) => muxed_B_1_port, IN0(0) =>
muxed_B_0_port, IN1(31) => IMM_i(31), IN1(30) =>
IMM_i(30), IN1(29) => IMM_i(29), IN1(28) =>
IMM_i(28), IN1(27) => IMM_i(27), IN1(26) =>
IMM_i(26), IN1(25) => IMM_i(25), IN1(24) =>
IMM_i(24), IN1(23) => IMM_i(23), IN1(22) =>
IMM_i(22), IN1(21) => IMM_i(21), IN1(20) =>
IMM_i(20), IN1(19) => IMM_i(19), IN1(18) =>
IMM_i(18), IN1(17) => IMM_i(17), IN1(16) =>
IMM_i(16), IN1(15) => IMM_i(15), IN1(14) =>
IMM_i(14), IN1(13) => IMM_i(13), IN1(12) =>
IMM_i(12), IN1(11) => IMM_i(11), IN1(10) =>
IMM_i(10), IN1(9) => IMM_i(9), IN1(8) => IMM_i(8),
IN1(7) => IMM_i(7), IN1(6) => IMM_i(6), IN1(5) =>
IMM_i(5), IN1(4) => IMM_i(4), IN1(3) => IMM_i(3),
IN1(2) => IMM_i(2), IN1(1) => IMM_i(1), IN1(0) =>
IMM_i(0), CTRL => S_MUX_ALUIN_i, OUT1(31) =>
FWB2alu_31_port, OUT1(30) => FWB2alu_30_port,
OUT1(29) => FWB2alu_29_port, OUT1(28) =>
FWB2alu_28_port, OUT1(27) => FWB2alu_27_port,
OUT1(26) => FWB2alu_26_port, OUT1(25) =>
FWB2alu_25_port, OUT1(24) => FWB2alu_24_port,
OUT1(23) => FWB2alu_23_port, OUT1(22) =>
FWB2alu_22_port, OUT1(21) => FWB2alu_21_port,
OUT1(20) => FWB2alu_20_port, OUT1(19) =>
FWB2alu_19_port, OUT1(18) => FWB2alu_18_port,
OUT1(17) => FWB2alu_17_port, OUT1(16) =>
FWB2alu_16_port, OUT1(15) => FWB2alu_15_port,
OUT1(14) => FWB2alu_14_port, OUT1(13) =>
FWB2alu_13_port, OUT1(12) => FWB2alu_12_port,
OUT1(11) => FWB2alu_11_port, OUT1(10) =>
FWB2alu_10_port, OUT1(9) => FWB2alu_9_port, OUT1(8)
=> FWB2alu_8_port, OUT1(7) => FWB2alu_7_port,
OUT1(6) => FWB2alu_6_port, OUT1(5) => FWB2alu_5_port
, OUT1(4) => FWB2alu_4_port, OUT1(3) =>
FWB2alu_3_port, OUT1(2) => FWB2alu_2_port, OUT1(1)
=> FWB2alu_1_port, OUT1(0) => FWB2alu_0_port);
ALU : real_alu_DATA_SIZE32 port map( IN1(31) => FWA2alu_31_port, IN1(30) =>
FWA2alu_30_port, IN1(29) => FWA2alu_29_port, IN1(28)
=> FWA2alu_28_port, IN1(27) => FWA2alu_27_port,
IN1(26) => FWA2alu_26_port, IN1(25) =>
FWA2alu_25_port, IN1(24) => FWA2alu_24_port, IN1(23)
=> FWA2alu_23_port, IN1(22) => FWA2alu_22_port,
IN1(21) => FWA2alu_21_port, IN1(20) =>
FWA2alu_20_port, IN1(19) => FWA2alu_19_port, IN1(18)
=> FWA2alu_18_port, IN1(17) => FWA2alu_17_port,
IN1(16) => FWA2alu_16_port, IN1(15) =>
FWA2alu_15_port, IN1(14) => FWA2alu_14_port, IN1(13)
=> FWA2alu_13_port, IN1(12) => FWA2alu_12_port,
IN1(11) => FWA2alu_11_port, IN1(10) =>
FWA2alu_10_port, IN1(9) => FWA2alu_9_port, IN1(8) =>
FWA2alu_8_port, IN1(7) => FWA2alu_7_port, IN1(6) =>
FWA2alu_6_port, IN1(5) => FWA2alu_5_port, IN1(4) =>
FWA2alu_4_port, IN1(3) => FWA2alu_3_port, IN1(2) =>
FWA2alu_2_port, IN1(1) => FWA2alu_1_port, IN1(0) =>
FWA2alu_0_port, IN2(31) => FWB2alu_31_port, IN2(30)
=> FWB2alu_30_port, IN2(29) => FWB2alu_29_port,
IN2(28) => FWB2alu_28_port, IN2(27) =>
FWB2alu_27_port, IN2(26) => FWB2alu_26_port, IN2(25)
=> FWB2alu_25_port, IN2(24) => FWB2alu_24_port,
IN2(23) => FWB2alu_23_port, IN2(22) =>
FWB2alu_22_port, IN2(21) => FWB2alu_21_port, IN2(20)
=> FWB2alu_20_port, IN2(19) => FWB2alu_19_port,
IN2(18) => FWB2alu_18_port, IN2(17) =>
FWB2alu_17_port, IN2(16) => FWB2alu_16_port, IN2(15)
=> FWB2alu_15_port, IN2(14) => FWB2alu_14_port,
IN2(13) => FWB2alu_13_port, IN2(12) =>
FWB2alu_12_port, IN2(11) => FWB2alu_11_port, IN2(10)
=> FWB2alu_10_port, IN2(9) => FWB2alu_9_port, IN2(8)
=> FWB2alu_8_port, IN2(7) => FWB2alu_7_port, IN2(6)
=> FWB2alu_6_port, IN2(5) => FWB2alu_5_port, IN2(4)
=> FWB2alu_4_port, IN2(3) => FWB2alu_3_port, IN2(2)
=> FWB2alu_2_port, IN2(1) => FWB2alu_1_port, IN2(0)
=> FWB2alu_0_port, ALUW_i(12) => ALUW_i(12),
ALUW_i(11) => ALUW_i(11), ALUW_i(10) => ALUW_i(10),
ALUW_i(9) => ALUW_i(9), ALUW_i(8) => ALUW_i(8),
ALUW_i(7) => ALUW_i(7), ALUW_i(6) => ALUW_i(6),
ALUW_i(5) => ALUW_i(5), ALUW_i(4) => ALUW_i(4),
ALUW_i(3) => ALUW_i(3), ALUW_i(2) => ALUW_i(2),
ALUW_i(1) => ALUW_i(1), ALUW_i(0) => ALUW_i(0),
DOUT(31) => DOUT(31), DOUT(30) => DOUT(30), DOUT(29)
=> DOUT(29), DOUT(28) => DOUT(28), DOUT(27) =>
DOUT(27), DOUT(26) => DOUT(26), DOUT(25) => DOUT(25)
, DOUT(24) => DOUT(24), DOUT(23) => DOUT(23),
DOUT(22) => DOUT(22), DOUT(21) => DOUT(21), DOUT(20)
=> DOUT(20), DOUT(19) => DOUT(19), DOUT(18) =>
DOUT(18), DOUT(17) => DOUT(17), DOUT(16) => DOUT(16)
, DOUT(15) => DOUT(15), DOUT(14) => DOUT(14),
DOUT(13) => DOUT(13), DOUT(12) => DOUT(12), DOUT(11)
=> DOUT(11), DOUT(10) => DOUT(10), DOUT(9) =>
DOUT(9), DOUT(8) => DOUT(8), DOUT(7) => DOUT(7),
DOUT(6) => DOUT(6), DOUT(5) => DOUT(5), DOUT(4) =>
DOUT(4), DOUT(3) => DOUT(3), DOUT(2) => DOUT(2),
DOUT(1) => DOUT(1), DOUT(0) => DOUT(0), stall_o =>
stall_o, Clock => Clock, Reset => Reset);
MUXDEST : mux41_MUX_SIZE5 port map( IN0(4) => X_Logic0_port, IN0(3) =>
X_Logic0_port, IN0(2) => X_Logic0_port, IN0(1) =>
X_Logic0_port, IN0(0) => X_Logic0_port, IN1(4) =>
rC_i(4), IN1(3) => rC_i(3), IN1(2) => rC_i(2),
IN1(1) => rC_i(1), IN1(0) => rC_i(0), IN2(4) =>
rB_i(4), IN2(3) => rB_i(3), IN2(2) => rB_i(2),
IN2(1) => rB_i(1), IN2(0) => rB_i(0), IN3(4) =>
X_Logic1_port, IN3(3) => X_Logic1_port, IN3(2) =>
X_Logic1_port, IN3(1) => X_Logic1_port, IN3(0) =>
X_Logic1_port, CTRL(1) => S_MUX_DEST_i(1), CTRL(0)
=> S_MUX_DEST_i(0), OUT1(4) => muxed_dest(4),
OUT1(3) => muxed_dest(3), OUT1(2) => muxed_dest(2),
OUT1(1) => muxed_dest(1), OUT1(0) => muxed_dest(0));
MUX_FWA : mux41_MUX_SIZE32_0 port map( IN0(31) => A_i(31), IN0(30) =>
A_i(30), IN0(29) => A_i(29), IN0(28) => A_i(28),
IN0(27) => A_i(27), IN0(26) => A_i(26), IN0(25) =>
A_i(25), IN0(24) => A_i(24), IN0(23) => A_i(23),
IN0(22) => A_i(22), IN0(21) => A_i(21), IN0(20) =>
A_i(20), IN0(19) => A_i(19), IN0(18) => A_i(18),
IN0(17) => A_i(17), IN0(16) => A_i(16), IN0(15) =>
A_i(15), IN0(14) => A_i(14), IN0(13) => A_i(13),
IN0(12) => A_i(12), IN0(11) => A_i(11), IN0(10) =>
A_i(10), IN0(9) => A_i(9), IN0(8) => A_i(8), IN0(7)
=> A_i(7), IN0(6) => A_i(6), IN0(5) => A_i(5),
IN0(4) => A_i(4), IN0(3) => A_i(3), IN0(2) => A_i(2)
, IN0(1) => A_i(1), IN0(0) => A_i(0), IN1(31) =>
FW_X_i(31), IN1(30) => FW_X_i(30), IN1(29) =>
FW_X_i(29), IN1(28) => FW_X_i(28), IN1(27) =>
FW_X_i(27), IN1(26) => FW_X_i(26), IN1(25) =>
FW_X_i(25), IN1(24) => FW_X_i(24), IN1(23) =>
FW_X_i(23), IN1(22) => FW_X_i(22), IN1(21) =>
FW_X_i(21), IN1(20) => FW_X_i(20), IN1(19) =>
FW_X_i(19), IN1(18) => FW_X_i(18), IN1(17) =>
FW_X_i(17), IN1(16) => FW_X_i(16), IN1(15) =>
FW_X_i(15), IN1(14) => FW_X_i(14), IN1(13) =>
FW_X_i(13), IN1(12) => FW_X_i(12), IN1(11) =>
FW_X_i(11), IN1(10) => FW_X_i(10), IN1(9) =>
FW_X_i(9), IN1(8) => FW_X_i(8), IN1(7) => FW_X_i(7),
IN1(6) => FW_X_i(6), IN1(5) => FW_X_i(5), IN1(4) =>
FW_X_i(4), IN1(3) => FW_X_i(3), IN1(2) => FW_X_i(2),
IN1(1) => FW_X_i(1), IN1(0) => FW_X_i(0), IN2(31) =>
FW_W_i(31), IN2(30) => FW_W_i(30), IN2(29) =>
FW_W_i(29), IN2(28) => FW_W_i(28), IN2(27) =>
FW_W_i(27), IN2(26) => FW_W_i(26), IN2(25) =>
FW_W_i(25), IN2(24) => FW_W_i(24), IN2(23) =>
FW_W_i(23), IN2(22) => FW_W_i(22), IN2(21) =>
FW_W_i(21), IN2(20) => FW_W_i(20), IN2(19) =>
FW_W_i(19), IN2(18) => FW_W_i(18), IN2(17) =>
FW_W_i(17), IN2(16) => FW_W_i(16), IN2(15) =>
FW_W_i(15), IN2(14) => FW_W_i(14), IN2(13) =>
FW_W_i(13), IN2(12) => FW_W_i(12), IN2(11) =>
FW_W_i(11), IN2(10) => FW_W_i(10), IN2(9) =>
FW_W_i(9), IN2(8) => FW_W_i(8), IN2(7) => FW_W_i(7),
IN2(6) => FW_W_i(6), IN2(5) => FW_W_i(5), IN2(4) =>
FW_W_i(4), IN2(3) => FW_W_i(3), IN2(2) => FW_W_i(2),
IN2(1) => FW_W_i(1), IN2(0) => FW_W_i(0), IN3(31) =>
n1, IN3(30) => n1, IN3(29) => n1, IN3(28) => n1,
IN3(27) => n1, IN3(26) => n1, IN3(25) => n1, IN3(24)
=> n1, IN3(23) => n1, IN3(22) => n1, IN3(21) => n1,
IN3(20) => n1, IN3(19) => n1, IN3(18) => n1, IN3(17)
=> n1, IN3(16) => n1, IN3(15) => n1, IN3(14) => n1,
IN3(13) => n1, IN3(12) => n1, IN3(11) => n1, IN3(10)
=> n1, IN3(9) => n1, IN3(8) => n1, IN3(7) => n1,
IN3(6) => n1, IN3(5) => n1, IN3(4) => n1, IN3(3) =>
n1, IN3(2) => n1, IN3(1) => n1, IN3(0) => n1,
CTRL(1) => S_FW_A_i(1), CTRL(0) => S_FW_A_i(0),
OUT1(31) => FWA2alu_31_port, OUT1(30) =>
FWA2alu_30_port, OUT1(29) => FWA2alu_29_port,
OUT1(28) => FWA2alu_28_port, OUT1(27) =>
FWA2alu_27_port, OUT1(26) => FWA2alu_26_port,
OUT1(25) => FWA2alu_25_port, OUT1(24) =>
FWA2alu_24_port, OUT1(23) => FWA2alu_23_port,
OUT1(22) => FWA2alu_22_port, OUT1(21) =>
FWA2alu_21_port, OUT1(20) => FWA2alu_20_port,
OUT1(19) => FWA2alu_19_port, OUT1(18) =>
FWA2alu_18_port, OUT1(17) => FWA2alu_17_port,
OUT1(16) => FWA2alu_16_port, OUT1(15) =>
FWA2alu_15_port, OUT1(14) => FWA2alu_14_port,
OUT1(13) => FWA2alu_13_port, OUT1(12) =>
FWA2alu_12_port, OUT1(11) => FWA2alu_11_port,
OUT1(10) => FWA2alu_10_port, OUT1(9) =>
FWA2alu_9_port, OUT1(8) => FWA2alu_8_port, OUT1(7)
=> FWA2alu_7_port, OUT1(6) => FWA2alu_6_port,
OUT1(5) => FWA2alu_5_port, OUT1(4) => FWA2alu_4_port
, OUT1(3) => FWA2alu_3_port, OUT1(2) =>
FWA2alu_2_port, OUT1(1) => FWA2alu_1_port, OUT1(0)
=> FWA2alu_0_port);
MUX_FWB : mux41_MUX_SIZE32_1 port map( IN0(31) => MUXED_B_i(31), IN0(30) =>
MUXED_B_i(30), IN0(29) => MUXED_B_i(29), IN0(28) =>
MUXED_B_i(28), IN0(27) => MUXED_B_i(27), IN0(26) =>
MUXED_B_i(26), IN0(25) => MUXED_B_i(25), IN0(24) =>
MUXED_B_i(24), IN0(23) => MUXED_B_i(23), IN0(22) =>
MUXED_B_i(22), IN0(21) => MUXED_B_i(21), IN0(20) =>
MUXED_B_i(20), IN0(19) => MUXED_B_i(19), IN0(18) =>
MUXED_B_i(18), IN0(17) => MUXED_B_i(17), IN0(16) =>
MUXED_B_i(16), IN0(15) => MUXED_B_i(15), IN0(14) =>
MUXED_B_i(14), IN0(13) => MUXED_B_i(13), IN0(12) =>
MUXED_B_i(12), IN0(11) => MUXED_B_i(11), IN0(10) =>
MUXED_B_i(10), IN0(9) => MUXED_B_i(9), IN0(8) =>
MUXED_B_i(8), IN0(7) => MUXED_B_i(7), IN0(6) =>
MUXED_B_i(6), IN0(5) => MUXED_B_i(5), IN0(4) =>
MUXED_B_i(4), IN0(3) => MUXED_B_i(3), IN0(2) =>
MUXED_B_i(2), IN0(1) => MUXED_B_i(1), IN0(0) =>
MUXED_B_i(0), IN1(31) => FW_X_i(31), IN1(30) =>
FW_X_i(30), IN1(29) => FW_X_i(29), IN1(28) =>
FW_X_i(28), IN1(27) => FW_X_i(27), IN1(26) =>
FW_X_i(26), IN1(25) => FW_X_i(25), IN1(24) =>
FW_X_i(24), IN1(23) => FW_X_i(23), IN1(22) =>
FW_X_i(22), IN1(21) => FW_X_i(21), IN1(20) =>
FW_X_i(20), IN1(19) => FW_X_i(19), IN1(18) =>
FW_X_i(18), IN1(17) => FW_X_i(17), IN1(16) =>
FW_X_i(16), IN1(15) => FW_X_i(15), IN1(14) =>
FW_X_i(14), IN1(13) => FW_X_i(13), IN1(12) =>
FW_X_i(12), IN1(11) => FW_X_i(11), IN1(10) =>
FW_X_i(10), IN1(9) => FW_X_i(9), IN1(8) => FW_X_i(8)
, IN1(7) => FW_X_i(7), IN1(6) => FW_X_i(6), IN1(5)
=> FW_X_i(5), IN1(4) => FW_X_i(4), IN1(3) =>
FW_X_i(3), IN1(2) => FW_X_i(2), IN1(1) => FW_X_i(1),
IN1(0) => FW_X_i(0), IN2(31) => FW_W_i(31), IN2(30)
=> FW_W_i(30), IN2(29) => FW_W_i(29), IN2(28) =>
FW_W_i(28), IN2(27) => FW_W_i(27), IN2(26) =>
FW_W_i(26), IN2(25) => FW_W_i(25), IN2(24) =>
FW_W_i(24), IN2(23) => FW_W_i(23), IN2(22) =>
FW_W_i(22), IN2(21) => FW_W_i(21), IN2(20) =>
FW_W_i(20), IN2(19) => FW_W_i(19), IN2(18) =>
FW_W_i(18), IN2(17) => FW_W_i(17), IN2(16) =>
FW_W_i(16), IN2(15) => FW_W_i(15), IN2(14) =>
FW_W_i(14), IN2(13) => FW_W_i(13), IN2(12) =>
FW_W_i(12), IN2(11) => FW_W_i(11), IN2(10) =>
FW_W_i(10), IN2(9) => FW_W_i(9), IN2(8) => FW_W_i(8)
, IN2(7) => FW_W_i(7), IN2(6) => FW_W_i(6), IN2(5)
=> FW_W_i(5), IN2(4) => FW_W_i(4), IN2(3) =>
FW_W_i(3), IN2(2) => FW_W_i(2), IN2(1) => FW_W_i(1),
IN2(0) => FW_W_i(0), IN3(31) => n1, IN3(30) => n1,
IN3(29) => n1, IN3(28) => n1, IN3(27) => n1, IN3(26)
=> n1, IN3(25) => n1, IN3(24) => n1, IN3(23) => n1,
IN3(22) => n1, IN3(21) => n1, IN3(20) => n1, IN3(19)
=> n1, IN3(18) => n1, IN3(17) => n1, IN3(16) => n1,
IN3(15) => n1, IN3(14) => n1, IN3(13) => n1, IN3(12)
=> n1, IN3(11) => n1, IN3(10) => n1, IN3(9) => n1,
IN3(8) => n1, IN3(7) => n1, IN3(6) => n1, IN3(5) =>
n1, IN3(4) => n1, IN3(3) => n1, IN3(2) => n1, IN3(1)
=> n1, IN3(0) => n1, CTRL(1) => S_FW_B_i(1), CTRL(0)
=> S_FW_B_i(0), OUT1(31) => muxed_B_31_port,
OUT1(30) => muxed_B_30_port, OUT1(29) =>
muxed_B_29_port, OUT1(28) => muxed_B_28_port,
OUT1(27) => muxed_B_27_port, OUT1(26) =>
muxed_B_26_port, OUT1(25) => muxed_B_25_port,
OUT1(24) => muxed_B_24_port, OUT1(23) =>
muxed_B_23_port, OUT1(22) => muxed_B_22_port,
OUT1(21) => muxed_B_21_port, OUT1(20) =>
muxed_B_20_port, OUT1(19) => muxed_B_19_port,
OUT1(18) => muxed_B_18_port, OUT1(17) =>
muxed_B_17_port, OUT1(16) => muxed_B_16_port,
OUT1(15) => muxed_B_15_port, OUT1(14) =>
muxed_B_14_port, OUT1(13) => muxed_B_13_port,
OUT1(12) => muxed_B_12_port, OUT1(11) =>
muxed_B_11_port, OUT1(10) => muxed_B_10_port,
OUT1(9) => muxed_B_9_port, OUT1(8) => muxed_B_8_port
, OUT1(7) => muxed_B_7_port, OUT1(6) =>
muxed_B_6_port, OUT1(5) => muxed_B_5_port, OUT1(4)
=> muxed_B_4_port, OUT1(3) => muxed_B_3_port,
OUT1(2) => muxed_B_2_port, OUT1(1) => muxed_B_1_port
, OUT1(0) => muxed_B_0_port);
end SYN_struct;
| bsd-2-clause | ce9ddab5e11bfdd4eafb45001c78e610 | 0.490606 | 2.571384 | false | false | false | false |
MAV-RT-testbed/MAV-testbed | Syma_Flight_Final/Syma_Flight_Final.srcs/sources_1/ipshared/xilinx.com/axi_quad_spi_v3_2/c64e9f22/hdl/src/vhdl/xip_cross_clk_sync.vhd | 1 | 57,053 | -------------------------------------------------------------------------------
-- xip_cross_clk_sync.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
-------------------------------------------------------------------------------
-- Filename: xip_cross_clk_sync.vhd
-- Version: v3.0
-- Description: This is the CDC file for XIP mode
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
-- History:
-- ~~~~~~
-- SK 19/01/11 -- created v2.00.a version
-- ^^^^^^
-- 1. Created second version of the core.
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.conv_std_logic_vector;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_misc.all;
-- library unsigned is used for overloading of "=" which allows integer to
-- be compared to std_logic_vector
use ieee.std_logic_unsigned.all;
library axi_lite_ipif_v3_0;
use axi_lite_ipif_v3_0.axi_lite_ipif;
use axi_lite_ipif_v3_0.ipif_pkg.all;
library lib_fifo_v1_0;
use lib_fifo_v1_0.async_fifo_fg;
library lib_cdc_v1_0;
use lib_cdc_v1_0.cdc_sync;
library axi_quad_spi_v3_2;
use axi_quad_spi_v3_2.all;
library unisim;
use unisim.vcomponents.FDRE;
use unisim.vcomponents.FDR;
-------------------------------------------------------------------------------
entity xip_cross_clk_sync is
generic (
C_S_AXI4_DATA_WIDTH : integer;
C_SPI_MEM_ADDR_BITS : integer;
Async_Clk : integer ;
C_NUM_SS_BITS : integer
);
port (
EXT_SPI_CLK : in std_logic;
S_AXI4_ACLK : in std_logic;
S_AXI4_ARESET : in std_logic;
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
Rst_from_axi_cdc_to_spi : in std_logic;
----------------------------
spiXfer_done_cdc_from_spi : in std_logic;
spiXfer_done_cdc_to_axi_1 : out std_logic;
----------------------------
mst_modf_err_cdc_from_spi : in std_logic;
mst_modf_err_cdc_to_axi : out std_logic;
mst_modf_err_cdc_to_axi4 : out std_logic;
----------------------------
one_byte_xfer_cdc_from_axi : in std_logic;
one_byte_xfer_cdc_to_spi : out std_logic;
----------------------
two_byte_xfer_cdc_from_axi : in std_logic;
two_byte_xfer_cdc_to_spi : out std_logic;
----------------------
four_byte_xfer_cdc_from_axi : in std_logic;
four_byte_xfer_cdc_to_spi : out std_logic;
----------------------
Transmit_Addr_cdc_from_axi : in std_logic_vector(C_SPI_MEM_ADDR_BITS-1 downto 0);
Transmit_Addr_cdc_to_spi : out std_logic_vector(C_SPI_MEM_ADDR_BITS-1 downto 0);
----------------------
load_cmd_cdc_from_axi : in std_logic;
load_cmd_cdc_to_spi : out std_logic;
--------------------------
CPOL_cdc_from_axi : in std_logic;
CPOL_cdc_to_spi : out std_logic;
--------------------------
CPHA_cdc_from_axi : in std_logic;
CPHA_cdc_to_spi : out std_logic;
--------------------------
SS_cdc_from_axi : in std_logic_vector((C_NUM_SS_BITS-1) downto 0);
SS_cdc_to_spi : out std_logic_vector((C_NUM_SS_BITS-1) downto 0);
--------------------------
type_of_burst_cdc_from_axi : in std_logic;-- _vector(1 downto 0);
type_of_burst_cdc_to_spi : out std_logic;-- _vector(1 downto 0);
--------------------------
axi_length_cdc_from_axi : in std_logic_vector(7 downto 0);
axi_length_cdc_to_spi : out std_logic_vector(7 downto 0);
--------------------------
dtr_length_cdc_from_axi : in std_logic_vector(7 downto 0);
dtr_length_cdc_to_spi : out std_logic_vector(7 downto 0);
--------------------------
load_axi_data_cdc_from_axi : in std_logic;
load_axi_data_cdc_to_spi : out std_logic;
------------------------------
Rx_FIFO_Full_cdc_from_spi : in std_logic;
Rx_FIFO_Full_cdc_to_axi : out std_logic;
Rx_FIFO_Full_cdc_to_axi4 : out std_logic;
------------------------------
wb_hpm_done_cdc_from_spi : in std_logic;
wb_hpm_done_cdc_to_axi : out std_logic
);
end entity xip_cross_clk_sync;
-------------------------------------------------------------------------------
architecture imp of xip_cross_clk_sync is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
signal size_length_cdc_to_spi_d1 : std_logic_vector(1 downto 0);
signal size_length_cdc_to_spi_d2 : std_logic_vector(1 downto 0);
signal spiXfer_done_d1 : std_logic;
signal spiXfer_done_d2 : std_logic;
signal spiXfer_done_d3 : std_logic;
signal spiXfer_done_cdc_from_spi_int_2 : std_logic;
signal byte_xfer_cdc_from_axi_d1 : std_logic;
signal byte_xfer_cdc_from_axi_d2 : std_logic;
signal hw_xfer_cdc_from_axi_d1 : std_logic;
signal hw_xfer_cdc_from_axi_d2 : std_logic;
signal word_xfer_cdc_from_axi_d1 : std_logic;
signal word_xfer_cdc_from_axi_d2 : std_logic;
signal SS_cdc_from_spi_d1 : std_logic_vector((C_NUM_SS_BITS-1) downto 0);
signal SS_cdc_from_spi_d2 : std_logic_vector((C_NUM_SS_BITS-1) downto 0);
signal mst_modf_err_d1 : std_logic;
signal mst_modf_err_d2 : std_logic;
signal mst_modf_err_d3 : std_logic;
signal mst_modf_err_d4 : std_logic;
signal dtr_length_cdc_from_axi_d1 : std_logic_vector(7 downto 0);
signal dtr_length_cdc_from_axi_d2 : std_logic_vector(7 downto 0);
signal axi_length_cdc_to_spi_d1 : std_logic_vector(7 downto 0);
signal axi_length_cdc_to_spi_d2 : std_logic_vector(7 downto 0);
signal CPOL_cdc_to_spi_d1 : std_logic;
signal CPOL_cdc_to_spi_d2 : std_logic;
signal CPHA_cdc_to_spi_d1 : std_logic;
signal CPHA_cdc_to_spi_d2 : std_logic;
signal load_axi_data_cdc_to_spi_d1 : std_logic;
signal load_axi_data_cdc_to_spi_d2 : std_logic;
signal load_axi_data_cdc_to_spi_d3 : std_logic;
signal Transmit_Addr_cdc_from_axi_d1 : std_logic_vector(C_SPI_MEM_ADDR_BITS-1 downto 0);
signal Transmit_Addr_cdc_from_axi_d2 : std_logic_vector(C_SPI_MEM_ADDR_BITS-1 downto 0);
signal type_of_burst_cdc_to_spi_d1 : std_logic;-- _vector(1 downto 0);
signal type_of_burst_cdc_to_spi_d2 : std_logic;-- _vector(1 downto 0);
signal load_cmd_cdc_from_axi_d1 : std_logic;
signal load_cmd_cdc_from_axi_d2 : std_logic;
signal load_cmd_cdc_from_axi_d3 : std_logic;
signal load_cmd_cdc_from_axi_int_2 : std_logic;
signal rx_fifo_full_d1 : std_logic;
signal rx_fifo_full_d2 : std_logic;
signal rx_fifo_full_d3 : std_logic;
signal rx_fifo_full_d4 : std_logic;
signal ld_axi_data_cdc_from_axi_int_2 : std_logic;
signal wb_hpm_done_cdc_from_spi_d1 : std_logic;
signal wb_hpm_done_cdc_from_spi_d2 : std_logic;
-- attribute ASYNC_REG : string;
-- attribute ASYNC_REG of XFER_DONE_SYNC_SPI2AXI : label is "TRUE";
-- attribute ASYNC_REG of MST_MODF_SYNC_SPI2AXI : label is "TRUE";
-- attribute ASYNC_REG of MST_MODF_SYNC_SPI2AXI4 : label is "TRUE";
-- attribute ASYNC_REG of BYTE_XFER_SYNC_AXI2SPI : label is "TRUE";
-- attribute ASYNC_REG of HW_XFER_SYNC_AXI2SPI : label is "TRUE";
-- attribute ASYNC_REG of WORD_XFER_SYNC_AXI2SPI : label is "TRUE";
-- attribute ASYNC_REG of TYP_OF_XFER_SYNC_AXI2SPI : label is "TRUE";
-- attribute ASYNC_REG of LD_AXI_DATA_SYNC_AXI2SPI : label is "TRUE";
-- attribute ASYNC_REG of LD_CMD_SYNC_AXI2SPI : label is "TRUE";
-- -- attribute ASYNC_REG of TRANSMIT_DATA_SYNC_AXI_2_SPI_1 : label is "TRUE";
-- attribute ASYNC_REG of CPOL_SYNC_AXI2SPI : label is "TRUE";
-- attribute ASYNC_REG of CPHA_SYNC_AXI2SPI : label is "TRUE";
-- attribute ASYNC_REG of Rx_FIFO_Full_SYNC_SPI2AXI : label is "TRUE";
-- attribute ASYNC_REG of Rx_FIFO_Full_SYNC_SPI2AXI4 : label is "TRUE";
-- attribute ASYNC_REG of WB_HPM_DONE_SYNC_SPI2AXI : label is "TRUE";
attribute KEEP : string;
attribute KEEP of SS_cdc_from_spi_d2 : signal is "TRUE";
attribute KEEP of load_axi_data_cdc_to_spi_d3 : signal is "TRUE";
attribute KEEP of load_axi_data_cdc_to_spi_d2 : signal is "TRUE";
attribute KEEP of type_of_burst_cdc_to_spi_d2 : signal is "TRUE";
attribute KEEP of rx_fifo_full_d2 : signal is "TRUE";
attribute KEEP of CPHA_cdc_to_spi_d2 : signal is "TRUE";
attribute KEEP of CPOL_cdc_to_spi_d2 : signal is "TRUE";
attribute KEEP of Transmit_Addr_cdc_from_axi_d2 : signal is "TRUE";
attribute KEEP of load_cmd_cdc_from_axi_d3 : signal is "TRUE";
attribute KEEP of load_cmd_cdc_from_axi_d2 : signal is "TRUE";
attribute KEEP of word_xfer_cdc_from_axi_d2 : signal is "TRUE";
attribute KEEP of hw_xfer_cdc_from_axi_d2 : signal is "TRUE";
attribute KEEP of byte_xfer_cdc_from_axi_d2 : signal is "TRUE";
attribute KEEP of mst_modf_err_d2 : signal is "TRUE";
attribute KEEP of mst_modf_err_d4 : signal is "TRUE";
attribute KEEP of spiXfer_done_d2 : signal is "TRUE";
attribute KEEP of spiXfer_done_d3 : signal is "TRUE";
attribute KEEP of axi_length_cdc_to_spi_d2 : signal is "TRUE";
attribute KEEP of dtr_length_cdc_from_axi_d2 : signal is "TRUE";
constant LOGIC_CHANGE : integer range 0 to 1 := 1;
constant MTBF_STAGES_AXI2S : integer range 0 to 6 := 3 ;
constant MTBF_STAGES_S2AXI : integer range 0 to 6 := 4 ;
-----
begin
LOGIC_GENERATION_FDR : if (Async_Clk = 0) generate
-----
SPI_XFER_DONE_STRETCH_1: process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_from_axi_cdc_to_spi = '1') then
spiXfer_done_cdc_from_spi_int_2 <= '0';
else
spiXfer_done_cdc_from_spi_int_2 <= spiXfer_done_cdc_from_spi xor
spiXfer_done_cdc_from_spi_int_2;
end if;
end if;
end process SPI_XFER_DONE_STRETCH_1;
XFER_DONE_SYNC_SPI2AXI: component FDR
generic map(INIT => '0'
)port map (
Q => spiXfer_done_d1,
C => S_AXI4_ACLK,
D => spiXfer_done_cdc_from_spi_int_2,
R => S_AXI4_ARESET
);
FER_DONE_SYNC_SPI2AXI_1: component FDR
generic map(INIT => '0'
)port map (
Q => spiXfer_done_d2,
C => S_AXI4_ACLK,
D => spiXfer_done_d1,
R => S_AXI4_ARESET
);
FER_DONE_SYNC_SPI2AXI_2: component FDR
generic map(INIT => '0'
)port map (
Q => spiXfer_done_d3,
C => S_AXI4_ACLK,
D => spiXfer_done_d2,
R => S_AXI4_ARESET
);
spiXfer_done_cdc_to_axi_1 <= spiXfer_done_d2 xor spiXfer_done_d3;
-------------------------------------------------------------------------------
MST_MODF_SYNC_SPI2AXI: component FDR
generic map(INIT => '0'
)port map (
Q => mst_modf_err_d1,
C => S_AXI_ACLK,
D => mst_modf_err_cdc_from_spi,
R => S_AXI_ARESETN
);
MST_MODF_SYNC_SPI2AXI_1: component FDR
generic map(INIT => '0'
)port map (
Q => mst_modf_err_d2,
C => S_AXI_ACLK,
D => mst_modf_err_d1,
R => S_AXI_ARESETN
);
mst_modf_err_cdc_to_axi <= mst_modf_err_d2;
-------------------------------------------------------------------------------
MST_MODF_SYNC_SPI2AXI4: component FDR
generic map(INIT => '0'
)port map (
Q => mst_modf_err_d3,
C => S_AXI4_ACLK,
D => mst_modf_err_cdc_from_spi,
R => S_AXI4_ARESET
);
MST_MODF_SYNC_SPI2AXI4_1: component FDR
generic map(INIT => '0'
)port map (
Q => mst_modf_err_d4,
C => S_AXI4_ACLK,
D => mst_modf_err_d3,
R => S_AXI4_ARESET
);
mst_modf_err_cdc_to_axi4 <= mst_modf_err_d4;
-------------------------------------------------------------------------------
BYTE_XFER_SYNC_AXI2SPI: component FDR
generic map(INIT => '0'
)port map (
Q => byte_xfer_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => one_byte_xfer_cdc_from_axi,
R => Rst_from_axi_cdc_to_spi
);
BYTE_XFER_SYNC_AXI2SPI_1: component FDR
generic map(INIT => '0'
)port map (
Q => byte_xfer_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => byte_xfer_cdc_from_axi_d1,
R => Rst_from_axi_cdc_to_spi
);
one_byte_xfer_cdc_to_spi <= byte_xfer_cdc_from_axi_d2;
------------------------------------------------
HW_XFER_SYNC_AXI2SPI: component FDR
generic map(INIT => '0'
)port map (
Q => hw_xfer_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => two_byte_xfer_cdc_from_axi,
R => Rst_from_axi_cdc_to_spi
);
HW_XFER_SYNC_AXI2SPI_1: component FDR
generic map(INIT => '0'
)port map (
Q => hw_xfer_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => hw_xfer_cdc_from_axi_d1,
R => Rst_from_axi_cdc_to_spi
);
two_byte_xfer_cdc_to_spi <= hw_xfer_cdc_from_axi_d2;
------------------------------------------------
WORD_XFER_SYNC_AXI2SPI: component FDR
generic map(INIT => '0'
)port map (
Q => word_xfer_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => four_byte_xfer_cdc_from_axi,
R => Rst_from_axi_cdc_to_spi
);
WORD_XFER_SYNC_AXI2SPI_1: component FDR
generic map(INIT => '0'
)port map (
Q => word_xfer_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => word_xfer_cdc_from_axi_d1,
R => Rst_from_axi_cdc_to_spi
);
four_byte_xfer_cdc_to_spi <= word_xfer_cdc_from_axi_d2;
------------------------------------------------
LD_CMD_cdc_from_AXI_STRETCH: process(S_AXI4_ACLK)is
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1')then
if(S_AXI4_ARESET = '1')then
load_cmd_cdc_from_axi_int_2 <= '0';
else
load_cmd_cdc_from_axi_int_2 <= load_cmd_cdc_from_axi xor load_cmd_cdc_from_axi_int_2;
end if;
end if;
end process LD_CMD_cdc_from_AXI_STRETCH;
-------------------------------------
-- from AXI4 to SPI
LD_CMD_SYNC_AXI2SPI: component FDR
port map (
Q => load_cmd_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => load_cmd_cdc_from_axi_int_2,
R => Rst_from_axi_cdc_to_spi
);
LD_CMD_SYNC_AXI2SPI_1: component FDR
port map (
Q => load_cmd_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => load_cmd_cdc_from_axi_d1,
R => Rst_from_axi_cdc_to_spi
);
LD_CMD_SYNC_AXI2SPI_2: component FDR
port map (
Q => load_cmd_cdc_from_axi_d3,
C => EXT_SPI_CLK,
D => load_cmd_cdc_from_axi_d2,
R => Rst_from_axi_cdc_to_spi
);
load_cmd_cdc_to_spi <= load_cmd_cdc_from_axi_d3 xor
load_cmd_cdc_from_axi_d2;
--------------------------------------------------------------------------
-- from AXI4 to SPI
TRANS_ADDR_SYNC_GEN: for i in C_SPI_MEM_ADDR_BITS-1 downto 0 generate
attribute ASYNC_REG : string;
attribute ASYNC_REG of TRANS_ADDR_SYNC_AXI2SPI_CDC : label is "TRUE";
-----
begin
-----
TRANS_ADDR_SYNC_AXI2SPI_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => Transmit_Addr_cdc_from_axi_d1(i),
C => EXT_SPI_CLK,
D => Transmit_Addr_cdc_from_axi(i),
R => Rst_from_axi_cdc_to_spi
);
TRANS_ADDR_SYNC_AXI2SPI_1: component FDR
generic map(INIT => '0'
)port map (
Q => Transmit_Addr_cdc_from_axi_d2(i),
C => EXT_SPI_CLK,
D => Transmit_Addr_cdc_from_axi_d1(i),
R => Rst_from_axi_cdc_to_spi
);
end generate TRANS_ADDR_SYNC_GEN;
-- Transmit_Addr_cdc_to_spi <= Transmit_Addr_cdc_from_axi_d2; -- 4/19/2013
Transmit_Addr_cdc_to_spi <= Transmit_Addr_cdc_from_axi_d1; -- 4/19/2013
------------------------------------------------
-- from AXI4 Lite to SPI
CPOL_SYNC_AXI2SPI: component FDR
generic map(INIT => '0'
)port map (
Q => CPOL_cdc_to_spi_d1,
C => EXT_SPI_CLK,
D => CPOL_cdc_from_axi,
R => Rst_from_axi_cdc_to_spi
);
CPOL_SYNC_AXI2SPI_1: component FDR
generic map(INIT => '0'
)port map (
Q => CPOL_cdc_to_spi_d2,
C => EXT_SPI_CLK,
D => CPOL_cdc_to_spi_d1,
R => Rst_from_axi_cdc_to_spi
);
CPOL_cdc_to_spi <= CPOL_cdc_to_spi_d2;
------------------------------------------------
-- from AXI4 Lite to SPI
CPHA_SYNC_AXI2SPI: component FDR
generic map(INIT => '0'
)port map (
Q => CPHA_cdc_to_spi_d1,
C => EXT_SPI_CLK,
D => CPHA_cdc_from_axi,
R => Rst_from_axi_cdc_to_spi
);
CPHA_SYNC_AXI2SPI_1: component FDR
generic map(INIT => '0'
)port map (
Q => CPHA_cdc_to_spi_d2,
C => EXT_SPI_CLK,
D => CPHA_cdc_to_spi_d1,
R => Rst_from_axi_cdc_to_spi
);
CPHA_cdc_to_spi <= CPHA_cdc_to_spi_d2;
------------------------------------------------
LD_AXI_DATA_STRETCH: process(S_AXI4_ACLK)is
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1')then
if(S_AXI4_ARESET = '1')then
ld_axi_data_cdc_from_axi_int_2 <= '0';
else
ld_axi_data_cdc_from_axi_int_2 <= load_axi_data_cdc_from_axi xor
ld_axi_data_cdc_from_axi_int_2;
end if;
end if;
end process LD_AXI_DATA_STRETCH;
-------------------------------------
LD_AXI_DATA_SYNC_AXI2SPI: component FDR
generic map(INIT => '0'
)port map (
Q => load_axi_data_cdc_to_spi_d1,
C => EXT_SPI_CLK,
D => ld_axi_data_cdc_from_axi_int_2,
R => Rst_from_axi_cdc_to_spi
);
LD_AXI_DATA_SYNC_AXI2SPI_1: component FDR
generic map(INIT => '0'
)port map (
Q => load_axi_data_cdc_to_spi_d2,
C => EXT_SPI_CLK,
D => load_axi_data_cdc_to_spi_d1,
R => Rst_from_axi_cdc_to_spi
);
LD_AXI_DATA_SYNC_AXI2SPI_2: component FDR
generic map(INIT => '0'
)port map (
Q => load_axi_data_cdc_to_spi_d3,
C => EXT_SPI_CLK,
D => load_axi_data_cdc_to_spi_d2,
R => Rst_from_axi_cdc_to_spi
);
load_axi_data_cdc_to_spi <= load_axi_data_cdc_to_spi_d3 xor load_axi_data_cdc_to_spi_d2;
------------------------------------------------
SS_SYNC_AXI_SPI_GEN: for i in (C_NUM_SS_BITS-1) downto 0 generate
---------------------
attribute ASYNC_REG : string;
attribute ASYNC_REG of SS_SYNC_AXI2SPI_CDC : label is "TRUE";
begin
-----
SS_SYNC_AXI2SPI_CDC: component FDR
generic map(INIT => '1'
)port map (
Q => SS_cdc_from_spi_d1(i),
C => EXT_SPI_CLK,
D => SS_cdc_from_axi(i),
R => Rst_from_axi_cdc_to_spi
);
SS_SYNC_AXI2SPI_1: component FDR
generic map(INIT => '1'
)port map (
Q => SS_cdc_from_spi_d2(i),
C => EXT_SPI_CLK,
D => SS_cdc_from_spi_d1(i),
R => Rst_from_axi_cdc_to_spi
);
end generate SS_SYNC_AXI_SPI_GEN;
SS_cdc_to_spi <= SS_cdc_from_spi_d2;
------------------------------------------------------------------------
TYP_OF_XFER_SYNC_AXI2SPI: component FDR
generic map(INIT => '0'
)port map (
Q => type_of_burst_cdc_to_spi_d1,
C => EXT_SPI_CLK,
D => type_of_burst_cdc_from_axi,
R => Rst_from_axi_cdc_to_spi
);
TYP_OF_XFER_SYNC_AXI2SPI_1: component FDR
generic map(INIT => '0'
)port map (
Q => type_of_burst_cdc_to_spi_d2,
C => EXT_SPI_CLK,
D => type_of_burst_cdc_to_spi_d1,
R => Rst_from_axi_cdc_to_spi
);
--end generate TYP_OF_XFER_GEN;
------------------------------
type_of_burst_cdc_to_spi <= type_of_burst_cdc_to_spi_d2;
------------------------------------------------
AXI_LEN_SYNC_AXI_SPI_GEN: for i in 7 downto 0 generate
---------------------
attribute ASYNC_REG : string;
attribute ASYNC_REG of AXI_LEN_SYNC_AXI2SPI : label is "TRUE";
begin
-----
AXI_LEN_SYNC_AXI2SPI: component FDR
generic map(INIT => '1'
)port map (
Q => axi_length_cdc_to_spi_d1(i),
C => EXT_SPI_CLK,
D => axi_length_cdc_from_axi(i),
R => Rst_from_axi_cdc_to_spi
);
AXI_LEN_SYNC_AXI2SPI_1: component FDR
generic map(INIT => '1'
)port map (
Q => axi_length_cdc_to_spi_d2(i),
C => EXT_SPI_CLK,
D => axi_length_cdc_to_spi_d1(i),
R => Rst_from_axi_cdc_to_spi
);
end generate AXI_LEN_SYNC_AXI_SPI_GEN;
axi_length_cdc_to_spi <= axi_length_cdc_to_spi_d2;
------------------------------------------------------------------------
DTR_LEN_SYNC_AXI_SPI_GEN: for i in 7 downto 0 generate
---------------------
attribute ASYNC_REG : string;
attribute ASYNC_REG of DTR_LEN_SYNC_AXI2SPI : label is "TRUE";
begin
-----
DTR_LEN_SYNC_AXI2SPI: component FDR
generic map(INIT => '1'
)port map (
Q => dtr_length_cdc_from_axi_d1(i),
C => EXT_SPI_CLK,
D => dtr_length_cdc_from_axi(i),
R => Rst_from_axi_cdc_to_spi
);
DTR_LEN_SYNC_AXI2SPI_1: component FDR
generic map(INIT => '1'
)port map (
Q => dtr_length_cdc_from_axi_d2(i),
C => EXT_SPI_CLK,
D => dtr_length_cdc_from_axi_d1(i),
R => Rst_from_axi_cdc_to_spi
);
end generate DTR_LEN_SYNC_AXI_SPI_GEN;
dtr_length_cdc_to_spi <= dtr_length_cdc_from_axi_d2;
------------------------------------------------------------------------
-- from SPI to AXI Lite
Rx_FIFO_Full_SYNC_SPI2AXI: component FDR
generic map(INIT => '0'
)port map (
Q => rx_fifo_full_d1,
C => S_AXI_ACLK,
D => Rx_FIFO_Full_cdc_from_spi,
R => S_AXI_ARESETN
);
Rx_FIFO_Full_SYNC_SPI2AXI_1: component FDR
generic map(INIT => '0'
)port map (
Q => rx_fifo_full_d2,
C => S_AXI_ACLK,
D => rx_fifo_full_d1,
R => S_AXI_ARESETN
);
Rx_FIFO_Full_cdc_to_axi <= rx_fifo_full_d2;
-------------------------------------------------------------------------------
-- from SPI to AXI4
Rx_FIFO_Full_SYNC_SPI2AXI4: component FDR
generic map(INIT => '0'
)port map (
Q => rx_fifo_full_d3,
C => S_AXI4_ACLK,
D => Rx_FIFO_Full_cdc_from_spi,
R => S_AXI4_ARESET
);
Rx_FIFO_Full_SYNC_SPI2AXI4_1: component FDR
generic map(INIT => '0'
)port map (
Q => rx_fifo_full_d4,
C => S_AXI4_ACLK,
D => rx_fifo_full_d3,
R => S_AXI4_ARESET
);
Rx_FIFO_Full_cdc_to_axi4 <= rx_fifo_full_d4;
-------------------------------------------------------------------------------
-- from SPI to AXI4
WB_HPM_DONE_SYNC_SPI2AXI: component FDR
generic map(INIT => '0'
)port map (
Q => wb_hpm_done_cdc_from_spi_d1,
C => S_AXI4_ACLK,
D => wb_hpm_done_cdc_from_spi,
R => S_AXI4_ARESET
);
WB_HPM_DONE_SYNC_SPI2AXI_1: component FDR
generic map(INIT => '0'
)port map (
Q => wb_hpm_done_cdc_from_spi_d2,
C => S_AXI4_ACLK,
D => wb_hpm_done_cdc_from_spi_d1,
R => S_AXI4_ARESET
);
wb_hpm_done_cdc_to_axi <= wb_hpm_done_cdc_from_spi_d2;
-------------------------------------------------------------------------------
end generate LOGIC_GENERATION_FDR;
LOGIC_GENERATION_CDC : if (Async_Clk = 1) generate
-------------------------------------------------------------------------------
SPI_XFER_DONE_STRETCH_1: process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_from_axi_cdc_to_spi = '1') then
spiXfer_done_cdc_from_spi_int_2 <= '0';
--spiXfer_done_d1 <= '0';
else
spiXfer_done_cdc_from_spi_int_2 <= spiXfer_done_cdc_from_spi xor spiXfer_done_cdc_from_spi_int_2;
--spiXfer_done_d1 <= spiXfer_done_cdc_from_spi_int_2;
end if;
end if;
end process SPI_XFER_DONE_STRETCH_1;
XFER_DONE_SYNC_SPI2AXI_CDC: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 2 is ack based level sync
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 1 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_from_axi_cdc_to_spi ,
prmry_in => spiXfer_done_cdc_from_spi_int_2,--spiXfer_done_d1 ,
scndry_aclk => S_AXI4_ACLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => S_AXI4_ARESET ,
scndry_out => spiXfer_done_d2
);
SPI_XFER_DONE_STRETCH_1_CDC: process(S_AXI4_ACLK)is
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK= '1') then
if(S_AXI4_ARESET = '1') then
spiXfer_done_d3 <= '0';
else
spiXfer_done_d3 <= spiXfer_done_d2 ;
end if;
end if;
end process SPI_XFER_DONE_STRETCH_1_CDC;
spiXfer_done_cdc_to_axi_1 <= spiXfer_done_d2 xor spiXfer_done_d3;
-------------------------------------------------------------------------------
MST_MODF_SYNC_SPI2AXI_CDC: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => S_AXI_ACLK ,
prmry_resetn => S_AXI_ARESETN ,
prmry_in => mst_modf_err_cdc_from_spi ,
scndry_aclk => S_AXI_ACLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => S_AXI_ARESETN ,
scndry_out => mst_modf_err_cdc_to_axi
);
-------------------------------------------------------------------------------
MST_MODF_SYNC_SPI2AXI4_CDC: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => S_AXI4_ACLK ,
prmry_resetn => S_AXI4_ARESET ,
prmry_in => mst_modf_err_cdc_from_spi ,
scndry_aclk => S_AXI4_ACLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => S_AXI4_ARESET ,
scndry_out => mst_modf_err_cdc_to_axi4
);
-------------------------------------------------------------------------------
BYTE_XFER_SYNC_AXI2SPI_CDC: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_from_axi_cdc_to_spi ,
prmry_in => one_byte_xfer_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => one_byte_xfer_cdc_to_spi
);
-------------------------------------------------------------------------------
HW_XFER_SYNC_AXI2SPI_CDC: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_from_axi_cdc_to_spi ,
prmry_in => two_byte_xfer_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => two_byte_xfer_cdc_to_spi
);
-------------------------------------------------------------------------------
WORD_XFER_SYNC_AXI2SPI_CDC: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_from_axi_cdc_to_spi ,
prmry_in => four_byte_xfer_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => four_byte_xfer_cdc_to_spi
);
-------------------------------------------------------------------------------
LD_CMD_cdc_from_AXI_STRETCH_CDC: process(S_AXI4_ACLK)is
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1')then
if(S_AXI4_ARESET = '1')then
load_cmd_cdc_from_axi_int_2 <= '0';
--load_cmd_cdc_from_axi_d1 <= '0';
else
load_cmd_cdc_from_axi_int_2 <= load_cmd_cdc_from_axi xor load_cmd_cdc_from_axi_int_2;
--load_cmd_cdc_from_axi_d1 <= load_cmd_cdc_from_axi_int_2;
end if;
end if;
end process LD_CMD_cdc_from_AXI_STRETCH_CDC;
LD_CMD_SYNC_AXI2SPI_CDC: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 2 is ack based level sync
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 1 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => S_AXI4_ACLK ,
prmry_resetn => S_AXI4_ARESET ,
prmry_in => load_cmd_cdc_from_axi_int_2,--load_cmd_cdc_from_axi_d1 ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => load_cmd_cdc_from_axi_d2
);
LD_CMD_cdc_from_AXI_STRETCH: process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_from_axi_cdc_to_spi = '1')then
load_cmd_cdc_from_axi_d3 <= '0';
else
load_cmd_cdc_from_axi_d3 <= load_cmd_cdc_from_axi_d2;
end if;
end if;
end process LD_CMD_cdc_from_AXI_STRETCH;
load_cmd_cdc_to_spi <= load_cmd_cdc_from_axi_d3 xor
load_cmd_cdc_from_axi_d2;
-------------------------------------------------------------------------------
TRANS_ADDR_SYNC_GEN_CDC: for i in C_SPI_MEM_ADDR_BITS-1 downto 0 generate
attribute ASYNC_REG : string;
attribute ASYNC_REG of TRANS_ADDR_SYNC_AXI2SPI_CDC : label is "TRUE";
-----
begin
-----
TRANS_ADDR_SYNC_AXI2SPI_CDC: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1 ,-- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => EXT_SPI_CLK,
prmry_resetn => Rst_from_axi_cdc_to_spi,
prmry_in => Transmit_Addr_cdc_from_axi(i),
scndry_aclk => EXT_SPI_CLK,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi,
scndry_out => Transmit_Addr_cdc_from_axi_d2(i)
);
end generate TRANS_ADDR_SYNC_GEN_CDC;
Transmit_Addr_cdc_to_spi <= Transmit_Addr_cdc_from_axi_d2;
-------------------------------------------------------------------------------
CPOL_SYNC_AXI2SPI_CDC: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_from_axi_cdc_to_spi ,
prmry_in => CPOL_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => CPOL_cdc_to_spi
);
-------------------------------------------------------------------------------
CPHA_SYNC_AXI2SPI_CDC: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_from_axi_cdc_to_spi ,
prmry_in => CPHA_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => CPHA_cdc_to_spi
);
-------------------------------------------------------------------------------
LD_AXI_DATA_STRETCH_CDC: process(S_AXI4_ACLK)is
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1')then
if(S_AXI4_ARESET = '1')then
ld_axi_data_cdc_from_axi_int_2 <= '0';
--load_axi_data_cdc_to_spi_d1 <= '0';
else
ld_axi_data_cdc_from_axi_int_2 <= load_axi_data_cdc_from_axi xor
ld_axi_data_cdc_from_axi_int_2;
-- load_axi_data_cdc_to_spi_d1 <= ld_axi_data_cdc_from_axi_int_2;
end if;
end if;
end process LD_AXI_DATA_STRETCH_CDC;
LD_AXI_DATA_SYNC_AXI2SPI_CDC: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 2 is ack based level sync
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 1 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => S_AXI4_ACLK ,
prmry_resetn => S_AXI4_ARESET ,
prmry_in => ld_axi_data_cdc_from_axi_int_2,--load_axi_data_cdc_to_spi_d1 ,
prmry_vect_in => (others => '0' ),
scndry_aclk => EXT_SPI_CLK ,
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => load_axi_data_cdc_to_spi_d2
);
LD_AXI_DATA_STRETCH: process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_from_axi_cdc_to_spi = '1')then
load_axi_data_cdc_to_spi_d3 <= '0';
else
load_axi_data_cdc_to_spi_d3 <= load_axi_data_cdc_to_spi_d2 ;
end if;
end if;
end process LD_AXI_DATA_STRETCH;
load_axi_data_cdc_to_spi <= load_axi_data_cdc_to_spi_d3 xor load_axi_data_cdc_to_spi_d2;
---------------------------------------------------------------------------------------
SS_SYNC_AXI_SPI_GEN_CDC: for i in (C_NUM_SS_BITS-1) downto 0 generate
---------------------
attribute ASYNC_REG : string;
attribute ASYNC_REG of SS_SYNC_AXI2SPI_CDC : label is "TRUE";
begin
SS_SYNC_AXI2SPI_CDC: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => EXT_SPI_CLK,
prmry_resetn => Rst_from_axi_cdc_to_spi,
prmry_in => SS_cdc_from_axi(i),
scndry_aclk => EXT_SPI_CLK,
scndry_resetn => Rst_from_axi_cdc_to_spi,
prmry_vect_in => (others => '0' ),
scndry_out => SS_cdc_from_spi_d2(i)
);
end generate SS_SYNC_AXI_SPI_GEN_CDC;
SS_cdc_to_spi <= SS_cdc_from_spi_d2;
------------------------------------------------------------------------------------------
TYP_OF_XFER_SYNC_AXI2SPI_CDC: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_from_axi_cdc_to_spi ,
prmry_in => type_of_burst_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => type_of_burst_cdc_to_spi
);
---------------------------------------------------------------------------------------
AXI_LEN_SYNC_AXI_SPI_GEN_CDC: for i in 7 downto 0 generate
---------------------
attribute ASYNC_REG : string;
attribute ASYNC_REG of AXI_LEN_SYNC_AXI2SPI_CDC : label is "TRUE";
begin
-------------
AXI_LEN_SYNC_AXI2SPI_CDC: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => EXT_SPI_CLK,
prmry_resetn => Rst_from_axi_cdc_to_spi,
prmry_in => axi_length_cdc_from_axi(i),
scndry_aclk => EXT_SPI_CLK,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi,
scndry_out => axi_length_cdc_to_spi_d2(i)
);
end generate AXI_LEN_SYNC_AXI_SPI_GEN_CDC;
axi_length_cdc_to_spi <= axi_length_cdc_to_spi_d2;
---------------------------------------------------------------------------------------
DTR_LEN_SYNC_AXI_SPI_GEN_CDC: for i in 7 downto 0 generate
---------------------
attribute ASYNC_REG : string;
attribute ASYNC_REG of DTR_LEN_SYNC_AXI2SPI_CDC : label is "TRUE";
begin
-----
DTR_LEN_SYNC_AXI2SPI_CDC: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => EXT_SPI_CLK,
prmry_resetn => Rst_from_axi_cdc_to_spi,
prmry_in => dtr_length_cdc_from_axi(i),
scndry_aclk => EXT_SPI_CLK,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi,
scndry_out => dtr_length_cdc_from_axi_d2(i)
);
end generate DTR_LEN_SYNC_AXI_SPI_GEN_CDC;
dtr_length_cdc_to_spi <= dtr_length_cdc_from_axi_d2;
------------------------------------------------------------------------
------------------------------------------------------------------------------------------
Rx_FIFO_Full_SYNC_SPI2AXI_CDC: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => S_AXI_ACLK ,
prmry_resetn => S_AXI_ARESETN ,
prmry_in => Rx_FIFO_Full_cdc_from_spi ,
prmry_vect_in => (others => '0' ),
scndry_aclk => S_AXI_ACLK ,
scndry_resetn => S_AXI_ARESETN ,
scndry_out => Rx_FIFO_Full_cdc_to_axi
);
------------------------------------------------------------------------
Rx_FIFO_Full_SYNC_SPI2AXI4_CDC: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => S_AXI4_ACLK ,
prmry_resetn => S_AXI4_ARESET ,
prmry_in => Rx_FIFO_Full_cdc_from_spi ,
prmry_vect_in => (others => '0' ),
scndry_aclk => S_AXI4_ACLK ,
scndry_resetn => S_AXI4_ARESET ,
scndry_out => Rx_FIFO_Full_cdc_to_axi4
);
-------------------------------------------------------------------------------
WB_HPM_DONE_SYNC_SPI2AXI_CDC: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => S_AXI4_ACLK ,
prmry_resetn => S_AXI4_ARESET ,
prmry_in => wb_hpm_done_cdc_from_spi ,
prmry_vect_in => (others => '0' ),
scndry_aclk => S_AXI4_ACLK ,
scndry_resetn => S_AXI4_ARESET ,
scndry_out => wb_hpm_done_cdc_to_axi
);
-------------------------------------------------------------------------------
byte_xfer_cdc_from_axi_d2 <= '0' ;
hw_xfer_cdc_from_axi_d2 <= '0' ;
word_xfer_cdc_from_axi_d2 <= '0' ;
mst_modf_err_d2 <= '0' ;
mst_modf_err_d4 <= '0' ;
CPOL_cdc_to_spi_d2 <= '0' ;
CPHA_cdc_to_spi_d2 <= '0' ;
type_of_burst_cdc_to_spi_d2 <= '0' ;
rx_fifo_full_d2 <= '0' ;
end generate LOGIC_GENERATION_CDC;
end architecture imp;
---------------------
| gpl-2.0 | bfc0c7e26731f2c1ecaba46b0e02e1de | 0.411021 | 3.885385 | false | false | false | false |
dpolad/dlx | DLX_vhd/a.e-REGFILE.vhd | 2 | 2,072 | -- *** a.d-REGFILE.vhd *** --
-- this block is a simple Register File.
-- This has 2 read port and 1 write port with enable signals
-- When reading and writing to the same registers, input data is redirect to the output
-- R0 is hardwired to 0
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
entity dlx_regfile is
generic(
databit: natural := 32;
addrbit: natural := 5
);
port ( Clk: IN std_logic;
Rst: IN std_logic;
ENABLE: IN std_logic;
RD1: IN std_logic;
RD2: IN std_logic;
WR: IN std_logic;
ADD_WR: IN std_logic_vector(addrbit-1 downto 0);
ADD_RD1: IN std_logic_vector(addrbit-1 downto 0);
ADD_RD2: IN std_logic_vector(addrbit-1 downto 0);
DATAIN: IN std_logic_vector(databit-1 downto 0);
OUT1: OUT std_logic_vector(databit-1 downto 0);
OUT2: OUT std_logic_vector(databit-1 downto 0));
end dlx_regfile;
architecture A of dlx_regfile is
-- suggested structures
subtype REG_ADDR is natural range 0 to 31; -- using natural type
type REG_ARRAY is array(REG_ADDR) of std_logic_vector(databit-1 downto 0);
signal REGISTERS : REG_ARRAY;
begin
process(clk)
begin
if(clk = '1' and clk'event) then
if(Rst = '1') then
--reset synchronous behavior
for i in 0 to 31 loop
REGISTERS(i) <= (others => '0');
end loop;
out1<= (others =>'0');
out2<= (others =>'0');
else
--normal behavior
if (wr = '1') then
--write
if to_integer(unsigned(ADD_WR)) /= 0 then
REGISTERS(to_integer(unsigned(ADD_WR))) <= DATAIN;
end if;
end if;
if(enable = '1') then
if(rd1 = '1') then
--read first
if(wr = '1') and (ADD_RD1 = ADD_WR) and to_integer(unsigned(ADD_WR)) /= 0 then
out1 <= DATAIN;
else
out1 <= REGISTERS(to_integer(unsigned(ADD_RD1)));
end if;
end if;
if(rd2 = '1') then
--read second
if(wr = '1') and (ADD_RD2 = ADD_WR) and to_integer(unsigned(ADD_WR)) /= 0 then
out2 <= DATAIN;
else
out2 <= REGISTERS(to_integer(unsigned(ADD_RD2)));
end if;
end if;
end if;
end if;
end if;
end process;
end A;
----
| bsd-2-clause | 486f190a0edbcd5a6eeea6a54108e079 | 0.635135 | 2.781208 | false | false | false | false |
rodrigofegui/UnB | 2017.1/Organização e Arquitetura de Computadores/Trabalhos/Projeto Final/Referências/dec_mem/seven_seg_decoder.vhd | 1 | 1,071 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity seven_seg_decoder is
port(
data: in STD_LOGIC_VECTOR(3 downto 0);
segments: out STD_LOGIC_VECTOR(6 downto 0)
);
end;
architecture seven_seg_decoder_arch of seven_seg_decoder is
begin
process(data)
begin
case data is
when X"0" => segments <= not "0111111";
when X"1" => segments <= not "0000110";
when X"2" => segments <= not "1011011";
when X"3" => segments <= not "1001111";
when X"4" => segments <= not "1100110";
when X"5" => segments <= not "1101101";
when X"6" => segments <= not "1111101";
when X"7" => segments <= not "0000111";
when X"8" => segments <= not "1111111";
when X"9" => segments <= not "1101111";
when X"A" => segments <= not "1110111";
when X"B" => segments <= not "1111100";
when X"C" => segments <= not "0111001";
when X"D" => segments <= not "1011110";
when X"E" => segments <= not "1111001";
when X"F" => segments <= not "1110001";
when others => segments <= not "0000000";
end case;
end process;
end;
| gpl-3.0 | 236d307b949dc4a717f63a41d9e2ed20 | 0.594771 | 3.086455 | false | false | false | false |
jobisoft/jTDC | modules/VFB6/disc16/ADC_LT2433_1_Receiver.vhd | 1 | 4,613 | -------------------------------------------------------------------------
---- ----
---- Company : ELB-Elektroniklaboratorien Bonn UG ----
---- (haftungsbeschränkt) ----
---- ----
-------------------------------------------------------------------------
---- ----
---- Copyright (C) 2015 ELB ----
---- ----
---- This program is free software; you can redistribute it and/or ----
---- modify it under the terms of the GNU General Public License as ----
---- published by the Free Software Foundation; either version 3 of ----
---- the License, or (at your option) any later version. ----
---- ----
---- This program is distributed in the hope that it will be useful, ----
---- but WITHOUT ANY WARRANTY; without even the implied warranty of ----
---- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ----
---- GNU General Public License for more details. ----
---- ----
---- You should have received a copy of the GNU General Public ----
---- License along with this program; if not, see ----
---- <http://www.gnu.org/licenses>. ----
---- ----
-------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
-- Clock High Min / Max / Internal Clock
-- 3,125 ms / 4 us / 57,14 us
-- resulting SPS 0,125 / 97,5 / 6.8
-- samlpe interval 8s / 10ms / 147 ms
-- -> if clock is high for 4 ms, a new packet is to arrive
entity ADC_LT2433_1_Receiver is
Port ( CLK : in STD_LOGIC;
SCLK : in STD_LOGIC; --internal oscillator: SCLK=17,5kHz, external oscillator SCLK=f_EOSC/8=250kHz Maximum, 320 Hz Minimum
SDO : in STD_LOGIC;
Data : out STD_LOGIC_VECTOR (18 downto 0) :="1111110111011101110"; -- in hex 7eeee to indicate that no value was read so far
Data_Update : out STD_LOGIC);
end ADC_LT2433_1_Receiver;
architecture Behavioral of ADC_LT2433_1_Receiver is
signal timeout_counter : unsigned (18 downto 0) := to_unsigned(0,19);
Signal D_SCLK, DD_SCLK, D_SDO, LE_SCLK : STD_LOGIC :='0';
Signal Reset_Packet : STD_LOGIC :='0';
signal bit_counter : unsigned (4 downto 0) := to_unsigned(0,5);
Signal Shift_register : STD_LOGIC_VECTOR (18 downto 0) :=(others=>'0');
Signal SR_Full, DSR_Full : STD_LOGIC :='0';
--signal Data_reg : STD_LOGIC_VECTOR (18 downto 0) :="1111110111011101110"; -- in hex 7eeee to indicate that no value was read so far
begin
Process (CLK) is begin
if rising_edge(CLK) then
D_SCLK<=SCLK;
DD_SCLK<=D_SCLK;
D_SDO<=SDO;
end if;
end process;
process (D_SCLK, DD_SCLK) is begin
if D_SCLK='1' AND DD_SCLK='0' then
LE_SCLK<='1';
else
LE_SCLK<='0';
end if;
end process;
Process (CLK) is begin
if rising_edge(CLK) then
if D_SCLK='0' then
timeout_counter<=to_unsigned(0,19);
Reset_Packet<='0';
elsif timeout_counter = to_unsigned (400000, 19) then-- simulation 400/ synthesis:400000
Reset_Packet<='1';
elsif D_SCLK='1' then
timeout_counter<=timeout_counter+1;
end if;
end if;
end process;
process (CLK) is begin
if rising_edge(CLK) then
if Reset_Packet='1' then
bit_counter<=to_unsigned(0,5);
elsif LE_SCLK='1' then
bit_counter<=bit_counter+1;
Shift_register(0)<=SDO;
Shift_register(18 downto 1)<=Shift_register(17 downto 0);
end if;
if bit_counter=to_unsigned(19,5) then
SR_Full<='1';
else
SR_Full <='0';
end if;
DSR_Full<=SR_Full;
end if;
end process;
Process (CLK) is begin --(SR_Full, DSR_Full, Shift_register, Data) is begin
if rising_edge(CLK) then
if SR_Full='1' and DSR_Full='0' then
Data_Update<='1';
Data<=Shift_register;
else
Data_Update<='0';
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | 3f16926418e91e4c8b45153b4646b26c | 0.528404 | 3.898563 | false | false | false | false |
rodrigofegui/UnB | 2017.1/Organização e Arquitetura de Computadores/Trabalhos/Projeto Final/Referências/dec_mem/dec_mem.vhd | 1 | 1,928 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity dec_mem is
generic(N: integer := 7; M: integer := 32);
port(
SW : in STD_LOGIC_VECTOR(N-1 downto 0);
HEX0 : out STD_LOGIC_VECTOR(6 downto 0);
HEX1 : out STD_LOGIC_VECTOR(6 downto 0);
HEX2 : out STD_LOGIC_VECTOR(6 downto 0);
HEX3 : out STD_LOGIC_VECTOR(6 downto 0);
HEX4 : out STD_LOGIC_VECTOR(6 downto 0);
HEX5 : out STD_LOGIC_VECTOR(6 downto 0);
HEX6 : out STD_LOGIC_VECTOR(6 downto 0);
HEX7 : out STD_LOGIC_VECTOR(6 downto 0)
);
end;
architecture dec_mem_arch of dec_mem is
-- signals
signal clk : STD_LOGIC := '0';
signal din : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal dout : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal we : STD_LOGIC := '0';
begin
clk <= '0';
we <= '0';
din <= (others => '0');
i1 : entity work.memory
generic map(N => N, M => M)
port map (
adr => SW,
clk => clk,
din => din,
dout => dout,
we => we
);
i2 : entity work.seven_seg_decoder
port map (
data => dout(3 downto 0),
segments => HEX0
);
i3 : entity work.seven_seg_decoder
port map (
data => dout(7 downto 4),
segments => HEX1
);
i4 : entity work.seven_seg_decoder
port map (
data => dout(11 downto 8),
segments => HEX2
);
i5 : entity work.seven_seg_decoder
port map (
data => dout(15 downto 12),
segments => HEX3
);
i6 : entity work.seven_seg_decoder
port map (
data => dout(19 downto 16),
segments => HEX4
);
i7 : entity work.seven_seg_decoder
port map (
data => dout(23 downto 20),
segments => HEX5
);
i8 : entity work.seven_seg_decoder
port map (
data => dout(27 downto 24),
segments => HEX6
);
i9 : entity work.seven_seg_decoder
port map (
data => dout(31 downto 28),
segments => HEX7
);
end; | gpl-3.0 | 04413b3561d16fac585d1f39c8d1c39c | 0.569502 | 2.852071 | false | false | false | false |
dpolad/dlx | DLX_synth/a.i.a.a-MULTLOGIC.vhd | 1 | 6,203 | -- MULTIPLIER LOGIC - structural
library ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
ENTITY simple_booth_add_ext IS
generic (N : integer := 8);
PORT(
Clock : in std_logic;
Reset : in std_logic;
sign : in std_logic;
enable : in std_logic;
valid : out std_logic;
A : in std_logic_vector (N-1 downto 0);
B : in std_logic_vector (N-1 downto 0);
A_to_add : out std_logic_vector (2*N-1 downto 0);
B_to_add : out std_logic_vector (2*N-1 downto 0);
sign_to_add : out std_logic;
final_out : out std_logic_vector (2*N-1 downto 0);
ACC_from_add : in std_logic_vector (2*N-1 downto 0)
);
END simple_booth_add_ext;
architecture struct of simple_booth_add_ext is
component booth_encoder
port(
B_in : in std_logic_vector (2 downto 0);
A_out : out std_logic_vector (2 downto 0)
);
end component;
component shift
generic(
N : natural
);
port(
Clock : in std_logic;
ALOAD : in std_logic;
D : in std_logic_vector(N-1 downto 0);
SO : out std_logic );
end component;
component piso_r_2
generic(
N : natural
);
port(
Clock : in std_logic;
ALOAD : in std_logic;
D : in std_logic_vector(N-1 downto 0);
SO : out std_logic_vector(N-1 downto 0) );
end component;
component mux8to1_gen
generic ( M : integer );
port(
A : in std_logic_vector (M-1 downto 0);
B : in std_logic_vector (M-1 downto 0);
C : in std_logic_vector (M-1 downto 0);
D : in std_logic_vector (M-1 downto 0);
E : in std_logic_vector (M-1 downto 0);
F : in std_logic_vector (M-1 downto 0);
G : in std_logic_vector (M-1 downto 0);
H : in std_logic_vector (M-1 downto 0);
S : in std_logic_vector (2 downto 0);
Y : out std_logic_vector (M-1 downto 0)
);
end component;
component ff32_en
generic(
SIZE : integer
);
port(
D : in std_logic_vector(SIZE - 1 downto 0);
Q : out std_logic_vector(SIZE - 1 downto 0);
en : in std_logic;
clk : in std_logic;
rst : in std_logic
);
end component;
component mux21
port (
IN0 : in std_logic_vector(31 downto 0);
IN1 : in std_logic_vector(31 downto 0);
CTRL : in std_logic;
OUT1 : out std_logic_vector(31 downto 0)
);
end component;
type mux_select is array (N/2 downto 0) of std_logic_vector(2 downto 0);
signal tot_select : mux_select;
signal piso_0_in : std_logic_vector(N/2 downto 0);
signal piso_1_in : std_logic_vector(N/2 downto 0);
signal piso_2_in : std_logic_vector(N/2 downto 0);
signal piso_0_out : std_logic;
signal piso_1_out : std_logic;
signal piso_2_out : std_logic;
signal enc_0_in : std_logic_vector(2 downto 0);
signal enc_N2_in : std_logic_vector(2 downto 0);
signal last_bit : std_logic;
signal extend_vector : std_logic_vector(N-1 downto 0);
signal extended_A : std_logic_vector(2*N-1 downto 0);
signal zeros : std_logic_vector(2*N-1 downto 0);
signal reg_enable : std_logic;
signal A_to_mux : std_logic_vector(2*N-1 downto 0);
signal A2_to_mux : std_logic_vector(2*N-1 downto 0);
signal mux_out_to_add : std_logic_vector(2*N-1 downto 0);
signal load : std_logic;
signal input_mux_sel : std_logic_vector(2 downto 0);
signal count : unsigned(4 downto 0);
signal accumulate : std_logic_vector(2*N-1 downto 0);
signal next_accumulate : std_logic_vector(2*N-1 downto 0);
signal triggered : std_logic;
begin
last_bit <= sign and B(N-1);
enc_0_in <= B(1 downto 0)&'0';
enc_N2_in <= last_bit&last_bit&B(N-1);
piso_gen: for i in 0 to N/2 generate
piso_0_in(i) <= tot_select(i)(0);
piso_1_in(i) <= tot_select(i)(1);
piso_2_in(i) <= tot_select(i)(2);
end generate piso_gen;
encod_loop: for i in 0 to N/2 generate
en_level0 : IF i = 0 generate
encod_0 : booth_encoder port map(enc_0_in, tot_select(i));
end generate en_level0;
en_levelN : IF i = N/2 generate
encod_i : booth_encoder port map(enc_N2_in, tot_select(i));
end generate en_levelN;
en_leveli : IF i > 0 and i < N/2 generate
encod_i : booth_encoder port map(B(2*i+1 downto 2*i-1), tot_select(i));
end generate en_leveli;
end generate encod_loop;
piso_0 : shift generic map( N => N/2+1) port map(Clock,load,piso_0_in,piso_0_out);
piso_1 : shift generic map( N => N/2+1) port map(Clock,load,piso_1_in,piso_1_out);
piso_2 : shift generic map( N => N/2+1) port map(Clock,load,piso_2_in,piso_2_out);
extend_vector <= (others => A(N-1) and sign);
extended_A <= extend_vector&A;
zeros <= (others => '0');
A_reg : piso_r_2 generic map( N => 2*N) port map(Clock,load,extended_A,A_to_mux);
A2_to_mux <= A_to_mux (2*N-2 downto 0)&'0';
input_mux_sel(0) <= piso_0_out;
input_mux_sel(1) <= piso_1_out;
input_mux_sel(2) <= piso_2_out;
INPUTMUX: mux21 port map(
IN0 => A_to_mux,
IN1 => A2_to_mux,
CTRL => input_mux_sel(0),
OUT1 => B_to_add);
ACCUMULATOR: ff32_en generic map(
SIZE => N*2
)port map(
D => next_accumulate,
Q => accumulate,
en => reg_enable,
clk => Clock,
rst => Reset);
--on first clock cycle need to always enable accumulator
reg_enable <= input_mux_sel(2) or nor_reduce(std_logic_vector(count) xor "01001");
A_to_add <= accumulate;
sign_to_add <= input_mux_sel(1);
--last output could be either from accumulator or directly from adder
final_out <= accumulate when input_mux_sel(2) = '0' else
ACC_from_add;
--sequential process for count handling
process(Reset,Clock)
begin
if Reset = '1' then
count <= "01001";
else
if Clock = '1' and Clock'event then
if count /= 0 and enable = '1' then
count <= count - 1;
end if;
if count = 0 then
count <= "01001";
end if;
end if;
end if;
end process;
--combinatorial process for signals
process(count,ACC_from_add)
begin
if count = 0 then
valid <= '1';
next_accumulate <= ACC_from_add;
load <= '0';
elsif count = 9 then
valid <= '0';
next_accumulate <= (others => '0');
load <= '1';
else
valid <= '0';
next_accumulate <= ACC_from_add;
load <= '0';
end if;
end process;
end struct;
| bsd-2-clause | ee2363a644762d6f4090d7482e47426a | 0.618733 | 2.543255 | false | false | false | false |
achan1989/SlowWorm | src/control/control.vhd | 1 | 5,306 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 26.08.2016 16:22:30
-- Design Name:
-- Module Name: control - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library SlowWorm;
use SlowWorm.SlowWorm.ALL;
entity control is
Port (
clk : in std_ulogic;
-- Instruction memory.
inst_mem_data : in data_t;
inst_mem_addr : out addr_t;
-- Data memory.
data_mem_data_read : in data_t;
data_mem_data_write : out data_t;
data_mem_addr : out addr_t;
data_mem_we : out std_ulogic;
-- Data stack.
dstack_data_read : in data_t;
dstack_data_write : out data_t;
dstack_push : out std_ulogic;
dstack_pop : out std_ulogic;
-- Return stack.
rstack_data_read : in data_t;
rstack_data_write : out data_t;
rstack_push : out std_ulogic;
rstack_pop : out std_ulogic
);
end control;
architecture Behavioral of control is
type state_t is (Reset, Fetch, Decode, Execute, Halt);
subtype instr_type_t is std_ulogic_vector(2 downto 0);
signal state : state_t := Reset;
signal data_addr, pc : addr_t;
signal instruction : data_t;
constant INSTR_TYPE_IMM_VAL : instr_type_t := "001";
constant INSTR_TYPE_LOGIC : instr_type_t := "011";
constant INSTR_TYPE_CONTROL : instr_type_t := "101";
constant INSTR_TYPE_UCODE : instr_type_t := "111";
begin
main: process (clk) is
-- General stuff used in decode state.
alias call_bit : std_ulogic is instruction(0);
alias instr_type : instr_type_t is instruction(2 downto 0);
variable call_address : addr_t;
variable is_call : boolean;
-- Used for Immediate Value instructions.
alias imm_stack : std_ulogic is instruction(3);
constant DATA_STACK : std_ulogic := '0';
alias imm_val : std_ulogic_vector(11 downto 0) is instruction(15 downto 4);
alias imm_sign_bit : std_ulogic is instruction(instruction'left);
variable imm_val_extended : data_t;
begin
if rising_edge(clk) then
-- Clear any control signals that cause a change of state in other modules.
dstack_push <= '0';
dstack_pop <= '0';
rstack_push <= '0';
rstack_pop <= '0';
data_mem_we <= '0';
case state is
when Reset =>
pc <= TO_UNSIGNED(0, pc'length);
inst_mem_addr <= TO_UNSIGNED(0, inst_mem_addr'length);
state <= Fetch;
-- Preconditions:
-- `inst_mem_addr` is loaded with the correct instruction memory address.
-- Postconditions:
-- `instruction` contains the next instruction to decode.
when Fetch =>
instruction <= inst_mem_data;
pc <= pc + 1;
state <= Decode;
when Decode =>
call_address := DATA_TO_ADDR(instruction(15 downto 0));
is_call := (call_bit = '0');
if is_call then
rstack_push <= '1';
rstack_data_write <= ADDR_TO_DATA(pc);
pc <= call_address;
inst_mem_addr <= call_address;
state <= Fetch;
else
case instr_type is
when INSTR_TYPE_IMM_VAL =>
imm_val_extended(imm_val'range) := imm_val;
imm_val_extended(imm_val_extended'left downto (imm_val'left + 1)) := (imm_val_extended'left downto (imm_val'left + 1) => imm_sign_bit);
if imm_stack = DATA_STACK then
dstack_push <= '1';
dstack_data_write <= imm_val_extended;
else
rstack_push <= '1';
rstack_data_write <= imm_val_extended;
end if;
inst_mem_addr <= pc;
state <= Fetch;
when INSTR_TYPE_LOGIC =>
--TODO. For now this is basically a no-op.
state <= Execute;
when INSTR_TYPE_CONTROL =>
--TODO. For now this is basically a no-op.
state <= Execute;
when INSTR_TYPE_UCODE =>
--TODO.
state <= Halt;
when others =>
-- something fucky has happened.
state <= Halt;
end case;
end if;
when Execute =>
inst_mem_addr <= pc;
state <= Fetch;
null; --TODO
when Halt =>
null;
end case;
end if;
end process;
end Behavioral;
| mit | d6b71f1895bc78b4bdb1b0eb88104e0e | 0.479834 | 4.272142 | false | false | false | false |
dpolad/dlx | DLX_vhd/useless/a-DLX.vhd | 1 | 17,694 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.myTypes.all;
entity DLX is
generic (
IR_SIZE : integer := 32; -- Instruction Register Size
PC_SIZE : integer := 32 -- Program Counter Size
); -- ALU_OPC_SIZE if explicit ALU Op Code Word Size
port (
Clk : in std_logic;
Rst : in std_logic); -- Active Low
end DLX;
-- This architecture is currently not complete
-- it just includes:
-- instruction register (complete)
-- program counter (complete)
-- instruction ram memory (complete)
-- control unit (UNCOMPLETE)
--
architecture dlx_rtl of DLX is
--------------------------------------------------------------------
-- Components Declaration
--------------------------------------------------------------------
--Instruction Ram
component IRAM
-- generic (
-- RAM_DEPTH : integer;
-- I_SIZE : integer);
port (
Rst : in std_logic;
Addr : in std_logic_vector(PC_SIZE - 1 downto 0);
Dout : out std_logic_vector(IR_SIZE - 1 downto 0));
end component;
-- Data Ram (MISSING!You must include it in your final project!)
-- Datapath (MISSING!You must include it in your final project!)
-- REGISTER FILE
component dlx_regfile
generic(
databit : integer := 32;
addrbit : integer := 5
);
port(
Clk : in std_logic;
Rst : in std_logic;
ENABLE : in std_logic;
RD1 : in std_logic;
RD2 : in std_logic;
WR : in std_logic;
ADD_WR : in std_logic_vector(addrbit-1 downto 0);
ADD_RD1 : in std_logic_vector(addrbit-1 downto 0);
ADD_RD2 : in std_logic_vector(addrbit-1 downto 0);
DATAIN : in std_logic_vector(databit-1 downto 0);
OUT1 : out std_logic_vector(databit-1 downto 0);
OUT2 : out std_logic_vector(databit-1 downto 0)
);
end component;
-- Control Unit
component dlx_cu
generic (
MICROCODE_MEM_SIZE : integer := 64; -- Microcode Memory Size
FUNC_SIZE : integer := 11; -- Func Field Size for R-Type Ops
OP_CODE_SIZE : integer := 6; -- Op Code Size
-- ALU_OPC_SIZE : integer := 6; -- ALU Op Code Word Size
IR_SIZE : integer := 32; -- Instruction Register Size
CW_SIZE : integer := 28); -- Control Word Size
port (
Clk : in std_logic; -- Clock
Rst : in std_logic; -- Reset:Active-Low
-- Instruction Register
IR_IN : in std_logic_vector(IR_SIZE - 1 downto 0);
--LATCH ENABLES
IR_LATCH_EN : out std_logic;
PC_LATCH_EN : out std_logic;
NPC_F_LATCH_EN : out std_logic;
JUMP_D_LATCH_EN : out std_logic;
NPC_D_LATCH_EN : out std_logic;
A_LATCH_EN : out std_logic;
B_LATCH_EN : out std_logic;
IMM_LATCH_EN : out std_logic;
RD_D_LATCH_EN : out std_logic;
ALUOUT_LATCH_EN : out std_logic;
B_E_LATCH_EN : out std_logic;
PC8_E_LATCH_EN : out std_logic;
RD_E_LATCH_EN : out std_logic;
OUT_M_LATCH_EN : out std_logic;
RD_M_LATCH_EN : out std_logic;
--MULTIPLEXERS
Sel_PC_D : out std_logic;
Sel_JUMP : out std_logic;
Sel_RD : out std_logic_vector(1 downto 0);
Sel_ALU2 : out std_logic;
Sel_OUT : out std_logic_vector(1 downto 0);
Sel_ext_26_16 : out std_logic;
Sel_ext_sign_unsign : out std_logic;
-- OTHERS
branch : out std_logic;
is_jump : out std_logic;
RF_WE : out std_logic;
RF_RD1 : out std_logic;
RF_RD2 : out std_logic;
DMEM_WE : out std_logic;
DMEM_RE : out std_logic;
ALU_OPCODE : out aluOp
);
end component;
component fakealu
generic (
DATA_SIZE : integer := 32);
port (
IN1 : in std_logic_vector(DATA_SIZE - 1 downto 0);
IN2 : in std_logic_vector(DATA_SIZE - 1 downto 0);
OP : in AluOp;
DOUT : out std_logic_vector(DATA_SIZE - 1 downto 0);
ZEROUT : out std_logic
);
end component;
component ext_16_32
generic (
IN_SIZE : integer := 16;
OUT_SIZE : integer := 32
);
port (
IN1 : in std_logic_vector(IN_SIZE - 1 downto 0);
CTRL: in std_logic; -- when 0 sign extend , when 1 unsigned extend
OUT1 : out std_logic_vector(OUT_SIZE - 1 downto 0)
);
end component;
component sign_ext_16_26_32
generic (
IN_SIZE : integer := 26;
SHRINK_SIZE : integer := 16;
OUT_SIZE : integer := 32
);
port (
IN1 : in std_logic_vector(IN_SIZE - 1 downto 0);
CTRL: in std_logic; -- when 0 extend 16 bits, when 1 extend 26 bits
OUT1 : out std_logic_vector(OUT_SIZE - 1 downto 0)
);
end component;
----------------------------------------------------------------
-- Signals Declaration
----------------------------------------------------------------
-- Instruction Register (IR) and Program Counter (PC) declaration
signal IR : std_logic_vector(IR_SIZE - 1 downto 0);
signal PC : std_logic_vector(PC_SIZE - 1 downto 0);
-- Instruction Ram Bus signals
signal IRam_DOut : std_logic_vector(IR_SIZE - 1 downto 0);
-- Datapath Bus signals
signal PC_BUS : std_logic_vector(PC_SIZE -1 downto 0);
signal RF_WE_i : std_logic;
signal RF_RD1_i : std_logic;
signal RF_RD2_i : std_logic;
--signal RF_RD1_i : std_logic;
signal DMEM_RE_i : std_logic;
signal DMEM_WE_i : std_logic;
-- Data Ram Bus signals
-- REGFILE SIGNALS
signal PC4 : std_logic_vector(31 downto 0);
signal NPC_F : std_logic_vector(31 downto 0);
signal prop_A : std_logic_vector(31 downto 0);
signal prop_B : std_logic_vector(31 downto 0);
signal NPC_D : std_logic_vector(31 downto 0);
signal A : std_logic_vector(31 downto 0);
signal B : std_logic_vector(31 downto 0);
signal RD_D : std_logic_vector(4 downto 0);
signal IMM : std_logic_vector(31 downto 0);
signal ALU_IN_2 : std_logic_vector(31 downto 0);
signal muxed_NPC : std_logic_vector(31 downto 0);
signal PC8 : std_logic_vector(31 downto 0);
signal muxed_RD : std_logic_vector(4 downto 0);
signal prop_ZERO : std_logic;
signal prop_ALUOUT : std_logic_vector(31 downto 0);
signal JUMP_D : std_logic_vector(31 downto 0);
signal JUMP_E : std_logic_vector(31 downto 0);
signal ZERO : std_logic;
signal ALUOUT : std_logic_vector(31 downto 0);
signal B_E : std_logic_vector(31 downto 0);
signal PC8_E : std_logic_vector(31 downto 0);
signal RD_E : std_logic_vector(4 downto 0);
signal branch_i : std_logic := '0';
signal is_jump_i : std_logic;
signal branch_taken : std_logic;
signal prop_DMEMOUT : std_logic_vector(31 downto 0);
signal OUT_M : std_logic_vector(31 downto 0);
signal RD_M : std_logic_vector(4 downto 0);
signal muxed_OUT : std_logic_vector(31 downto 0);
signal muxed_BRANCH: std_logic_vector(31 downto 0);
signal calc_NPC: std_logic_vector(31 downto 0);
signal ext_26_16_out: std_logic_vector(31 downto 0);
signal ext_sign_unsign_out: std_logic_vector(31 downto 0);
--LATCH ENABLES
signal IR_LATCH_EN_i : std_logic := '1';
signal PC_LATCH_EN_i : std_logic := '1';
signal NPC_F_LATCH_EN_i : std_logic := '1';
signal JUMP_D_LATCH_EN_i : std_logic;
signal NPC_D_LATCH_EN_i : std_logic;
signal A_LATCH_EN_i : std_logic;
signal B_LATCH_EN_i : std_logic;
signal IMM_LATCH_EN_i : std_logic;
signal RD_D_LATCH_EN_i : std_logic;
signal JUMP_E_LATCH_EN_i : std_logic;
signal ZERO_LATCH_EN_i : std_logic;
signal ALUOUT_LATCH_EN_i : std_logic;
signal B_E_LATCH_EN_i : std_logic;
signal PC8_E_LATCH_EN_i : std_logic;
signal RD_E_LATCH_EN_i : std_logic;
signal OUT_M_LATCH_EN_i : std_logic;
signal RD_M_LATCH_EN_i : std_logic;
--MULTIPLEXERS
signal Sel_PC_D_i : std_logic;
signal Sel_PC_E : std_logic;
-- signal Sel_PC_M_i : std_logic;
signal Sel_JUMP_i : std_logic;
signal Sel_RD_i : std_logic_vector(1 downto 0);
signal Sel_ALU2_i : std_logic;
signal Sel_OUT_i : std_logic_vector(1 downto 0);
signal Sel_ext_26_16_i : std_logic;
signal Sel_ext_sign_unsign_i : std_logic;
--
signal ALU_OPCODE_i : AluOp;
begin -- DLX
-- This is the input to program counter: currently zero
-- so no uptade of PC happens
-- TO BE REMOVED AS SOON AS THE DATAPATH IS INSERTED!!!!!
-- a proper connection must be made here if more than one
-- instruction must be executed
--PC_BUS <= (others => '0'); -- PC BUS IS AT THE OUTPUT OF THE PC_MUX CONTROLLED BY A SIGNAL DRIVEN BY CU AND RESULT OF BRANCH OPERATION
PC_BUS <= muxed_BRANCH when Sel_PC_D_i = '0' else calc_NPC ;
muxed_BRANCH <= PC4 when Sel_PC_E = '0' else muxed_NPC ;
calc_NPC <= std_logic_vector(unsigned(ext_26_16_out) + unsigned(NPC_F));
PC4 <= std_logic_vector(unsigned(PC) + to_unsigned(4,32));
muxed_NPC <= JUMP_D when Sel_JUMP_i = '0' else A ;
ALU_IN_2 <= B when Sel_ALU2_i = '0' else IMM;
PC8 <= std_logic_vector(unsigned(NPC_D) + to_unsigned(4,32));
muxed_RD <= IR(20 downto 16) when Sel_RD_i = "00" else "11111" when Sel_RD_i = "01" else IR(15 downto 11);
branch_taken <= branch_i and prop_ZERO;
muxed_OUT <= prop_DMEMOUT when Sel_OUT_i = "00" else ALUOUT when Sel_OUT_i = "01" else PC8_E;
Sel_PC_E <= branch_taken or is_jump_i;
-- ***** STAGE 1 ********
-- purpose: Instruction Register Process
-- type : sequential
-- inputs : Clk, Rst, IRam_DOut, IR_LATCH_EN_i
-- outputs: IR_IN_i
IR_P: process (Clk, Rst)
begin -- process IR_P
if Rst = '0' then -- asynchronous reset (active low)
IR <= (others => '0');
elsif Clk'event and Clk = '1' then -- rising clock edge
if (IR_LATCH_EN_i = '1') then
IR <= IRam_DOut;
end if;
end if;
end process IR_P;
-- purpose: NPC4_L1 Process
-- type : sequential
-- inputs : Clk, Rst, PC+4, **SIGNAL FROM CU **
-- outputs: IR_IN_i
NPC_F_P: process (Clk, Rst)
begin -- process IR_P
if Rst = '0' then -- asynchronous reset (active low)
NPC_F <= (others => '0');
elsif Clk'event and Clk = '1' then -- rising clock edge
if (NPC_F_LATCH_EN_i = '1') then
NPC_F <= PC4;
end if;
end if;
end process NPC_F_P;
--***** STAGE 0 ******
-- purpose: Program Counter Process
-- type : sequential
-- inputs : Clk, Rst, PC_BUS
-- outputs: IRam_Addr
PC_P: process (Clk, Rst)
begin -- process PC_P
if Rst = '0' then -- asynchronous reset (active low)
PC <= (others => '0');
elsif Clk'event and Clk = '1' then -- rising clock edge
if (PC_LATCH_EN_i = '1') then
PC <= PC_BUS;
end if;
end if;
end process PC_P;
-- ***** STAGE 2 ********
JUMP_D_P: process (Clk, Rst)
begin -- process IR_P
if Rst = '0' then -- asynchronous reset (active low)
JUMP_D <= (others => '0');
elsif Clk'event and Clk = '1' then -- rising clock edge
if (JUMP_D_LATCH_EN_i = '1') then
JUMP_D <= calc_NPC;
end if;
end if;
end process JUMP_D_P;
NPC_D_P: process (Clk, Rst)
begin -- process IR_P
if Rst = '0' then -- asynchronous reset (active low)
NPC_D <= (others => '0');
elsif Clk'event and Clk = '1' then -- rising clock edge
if (NPC_D_LATCH_EN_i = '1') then
NPC_D <= NPC_F;
end if;
end if;
end process NPC_D_P;
A_P: process (Clk, Rst)
begin -- process IR_P
if Rst = '0' then -- asynchronous reset (active low)
A <= (others => '0');
elsif Clk'event and Clk = '1' then -- rising clock edge
if (A_LATCH_EN_i = '1') then
A <= prop_A;
end if;
end if;
end process A_P;
B_P: process (Clk, Rst)
begin -- process IR_P
if Rst = '0' then -- asynchronous reset (active low)
B <= (others => '0');
elsif Clk'event and Clk = '1' then -- rising clock edge
if (B_LATCH_EN_i = '1') then
B <= prop_B;
end if;
end if;
end process B_P;
RD_D_P: process (Clk, Rst)
begin -- process IR_P
if Rst = '0' then -- asynchronous reset (active low)
RD_D <= (others => '0');
elsif Clk'event and Clk = '1' then -- rising clock edge
if (RD_D_LATCH_EN_i = '1') then
RD_D <= muxed_RD;
end if;
end if;
end process RD_D_P;
IMM_P: process (Clk, Rst)
begin -- process IR_P
if Rst = '0' then -- asynchronous reset (active low)
IMM <= (others => '0');
elsif Clk'event and Clk = '1' then -- rising clock edge
if (IMM_LATCH_EN_i = '1') then
IMM <= ext_sign_unsign_out;
end if;
end if;
end process IMM_P;
-- ***** STAGE 3 ********
ALUOUT_P: process (Clk, Rst)
begin -- process IR_P
if Rst = '0' then -- asynchronous reset (active low)
ALUOUT <= (others => '0');
elsif Clk'event and Clk = '1' then -- rising clock edge
if (ALUOUT_LATCH_EN_i = '1') then
ALUOUT <= prop_ALUOUT;
end if;
end if;
end process ALUOUT_P;
B_E_P: process (Clk, Rst)
begin -- process IR_P
if Rst = '0' then -- asynchronous reset (active low)
B_E <= (others => '0');
elsif Clk'event and Clk = '1' then -- rising clock edge
if (B_E_LATCH_EN_i = '1') then
B_E <= B;
end if;
end if;
end process B_E_P;
PC8_E_P: process (Clk, Rst)
begin -- process IR_P
if Rst = '0' then -- asynchronous reset (active low)
PC8_E <= (others => '0');
elsif Clk'event and Clk = '1' then -- rising clock edge
if (PC8_E_LATCH_EN_i = '1') then
PC8_E <= PC8;
end if;
end if;
end process PC8_E_P;
RD_E_P: process (Clk, Rst)
begin -- process IR_P
if Rst = '0' then -- asynchronous reset (active low)
RD_E <= (others => '0');
elsif Clk'event and Clk = '1' then -- rising clock edge
if (RD_E_LATCH_EN_i = '1') then
RD_E <= RD_D;
end if;
end if;
end process RD_E_P;
-- ***** STAGE 4 ********
OUT_M_P: process (Clk, Rst)
begin -- process IR_P
if Rst = '0' then -- asynchronous reset (active low)
OUT_M <= (others => '0');
elsif Clk'event and Clk = '1' then -- rising clock edge
if (OUT_M_LATCH_EN_i = '1') then
OUT_M <= muxed_OUT;
end if;
end if;
end process OUT_M_P;
RD_M_P: process (Clk, Rst)
begin -- process IR_P
if Rst = '0' then -- asynchronous reset (active low)
RD_M <= (others => '0');
elsif Clk'event and Clk = '1' then -- rising clock edge
if (RD_M_LATCH_EN_i = '1') then
RD_M <= RD_E;
end if;
end if;
end process RD_M_P;
EXT_A_I : sign_ext_16_26_32
port map(
IN1 => IR(25 downto 0),
CTRL=> Sel_ext_26_16_i,
OUT1 => ext_26_16_out
);
EXT_B_I : ext_16_32
port map(
IN1 => IR(15 downto 0),
CTRL=> Sel_ext_sign_unsign_i,
OUT1 => ext_sign_unsign_out
);
-- Control Unit Instantiation
-- **** ADD AND FIX SIGNALS!! ****** --
CU_I: dlx_cu
port map (
Clk => Clk,
Rst => Rst,
IR_IN => IR,
IR_LATCH_EN => IR_LATCH_EN_i,
PC_LATCH_EN => PC_LATCH_EN_I,
NPC_F_LATCH_EN => NPC_F_LATCH_EN_i,
JUMP_D_LATCH_EN => JUMP_D_LATCH_EN_i,
NPC_D_LATCH_EN => NPC_D_LATCH_EN_i,
A_LATCH_EN => A_LATCH_EN_i,
B_LATCH_EN => B_LATCH_EN_i,
IMM_LATCH_EN => IMM_LATCH_EN_i,
RD_D_LATCH_EN => RD_D_LATCH_EN_i,
ALUOUT_LATCH_EN => ALUOUT_LATCH_EN_i,
B_E_LATCH_EN => B_E_LATCH_EN_i,
PC8_E_LATCH_EN => PC8_E_LATCH_EN_i,
RD_E_LATCH_EN => RD_E_LATCH_EN_i,
OUT_M_LATCH_EN => OUT_M_LATCH_EN_i,
RD_M_LATCH_EN => RD_M_LATCH_EN_i,
--MULTIPLEXERS
Sel_PC_D => Sel_PC_D_i,
Sel_JUMP => Sel_JUMP_i,
Sel_RD => Sel_RD_i,
Sel_ALU2 => Sel_ALU2_i,
Sel_OUT => Sel_OUT_i,
Sel_ext_26_16 => Sel_ext_26_16_i,
Sel_ext_sign_unsign => Sel_ext_sign_unsign_i,
-- BRANCH
branch => branch_i,
is_jump => is_jump_i,
RF_WE => RF_WE_i,
RF_RD1 => RF_RD1_i,
RF_RD2 => RF_RD2_i,
DMEM_WE => DMEM_WE_i,
DMEM_RE => DMEM_RE_i,
ALU_OPCODE => ALU_OPCODE_i
);
-- Instruction Ram Instantiation
IRAM_i: IRAM
port map (
Rst => Rst,
Addr => PC,
Dout => IRam_DOut);
-- FAKEALU instantiation
RF_I: dlx_regfile
port map(
Clk => Clk,
Rst => Rst,
ENABLE => '1', -- hardwired 1
RD1 => RF_RD1_i,
RD2 => RF_RD2_i,
WR => RF_WE_i,
ADD_WR => RD_M,
ADD_RD1 => IR(25 downto 21),
ADD_RD2 => IR(20 downto 16),
DATAIN => OUT_M,
OUT1 => prop_A,
OUT2 => prop_B
);
-- REGIFLE instantiation
ALU_I: fakealu
port map(
IN1 => A,
IN2 => ALU_IN_2,
OP => ALU_OPCODE_i,
DOUT => prop_ALUOUT,
ZEROUT => prop_ZERO
);
end dlx_rtl;
| bsd-2-clause | e57f3d364d37d1e01da0da9758bdd6ac | 0.536792 | 3.208923 | false | false | false | false |
dpolad/dlx | DLX_vhd/test_bench/tb_top_level.vhd | 1 | 2,200 |
library IEEE;
use IEEE.std_logic_1164.all;
use WORK.all;
use work.myTypes.all;
entity tb_top_level is
end tb_top_level;
architecture TEST of tb_top_level is
signal Clock : std_logic := '0';
signal Reset : std_logic := '1';
signal IRAM_Addr : std_logic_vector(31 downto 0);
signal IRAM_Dout : std_logic_vector(31 downto 0);
signal DRAM_Addr : std_logic_vector(31 downto 0);
signal DRAM_Dout : std_logic_vector(31 downto 0);
signal DRAM_Din : std_logic_vector(31 downto 0);
signal DRAM_EN : std_logic;
signal DRAM_WR : std_logic;
component top_level
port(
clock : in std_logic;
rst : in std_logic;
IRAM_Addr_o : out std_logic_vector(31 downto 0);
IRAM_Dout_i : in std_logic_vector(31 downto 0);
DRAM_Enable_o : out std_logic;
DRAM_WR_o : out std_logic;
DRAM_Din_o : out std_logic_vector(31 downto 0);
DRAM_Addr_o : out std_logic_vector(31 downto 0);
DRAM_Dout_i : in std_logic_vector(31 downto 0)
);
end component;
component IRAM
port (
Rst : in std_logic;
Addr : in std_logic_vector(31 downto 0);
Dout : out std_logic_vector(31 downto 0)
);
end component;
component DRAM
generic (
RAM_DEPTH : integer := 4096;
I_SIZE : integer := 32);
port (
Clk : in std_logic;
Rst : in std_logic;
Enable : in std_logic;
WR : in std_logic;
Din : in std_logic_vector(31 downto 0);
Addr : in std_logic_vector(31 downto 0);
Dout : out std_logic_vector(31 downto 0)
);
end component;
begin
-- TODO: MOVE THIS SHIT TO THE REAL TB
DUT: top_level port map(
Clock => clock, -- HEREEEEEEEEE
Rst => reset,
IRAM_Addr_o => IRAM_Addr,
IRAM_Dout_i => IRAM_Dout,
DRAM_Enable_o => DRAM_EN,
DRAM_WR_o => DRAM_WR,
DRAM_Din_o => DRAM_Din,
DRAM_Addr_o => DRAM_Addr,
DRAM_Dout_i => DRAM_Dout
);
DMEM: DRAM generic map(
RAM_DEPTH => 4096,
I_SIZE => 32
)
port map(
Clk => clock, -- HEREEEEEEEEE
Rst => reset,
Enable => DRAM_EN,
WR => DRAM_WR,
Din => DRAM_Din,
Addr => DRAM_Addr,
Dout => DRAM_Dout
);
IMEM: IRAM port map(
Rst => Reset,
Addr => IRAM_Addr,
Dout => IRAM_Dout
);
PCLOCK : process(Clock)
begin
Clock <= not(Clock) after 0.5 ns;
end process;
Reset <= '1', '0' after 4 ns;
end TEST;
| bsd-2-clause | 16d3686df12f7bff760b6a845e663056 | 0.641818 | 2.485876 | false | false | false | false |
INTI-CMNB/Lattuino_IP_Core | FPGA/lattuino_1/wb_dev_intercon_package.vhdl | 1 | 4,677 |
library IEEE;
use IEEE.std_logic_1164.all;
package WBDevInterconPkg is
component WBDevIntercon is
port(
-- wishbone master port(s)
-- cpu
cpu_dat_o : out std_logic_vector(7 downto 0);
cpu_ack_o : out std_logic;
cpu_dat_i : in std_logic_vector(7 downto 0);
cpu_we_i : in std_logic;
cpu_adr_i : in std_logic_vector(7 downto 0);
cpu_cyc_i : in std_logic;
cpu_stb_i : in std_logic;
-- wishbone slave port(s)
-- rs2
rs2_dat_i : in std_logic_vector(7 downto 0);
rs2_ack_i : in std_logic;
rs2_dat_o : out std_logic_vector(7 downto 0);
rs2_we_o : out std_logic;
rs2_adr_o : out std_logic_vector(0 downto 0);
rs2_stb_o : out std_logic;
-- ad
ad_dat_i : in std_logic_vector(7 downto 0);
ad_ack_i : in std_logic;
ad_dat_o : out std_logic_vector(7 downto 0);
ad_we_o : out std_logic;
ad_adr_o : out std_logic_vector(0 downto 0);
ad_stb_o : out std_logic;
-- tmr
tmr_dat_i : in std_logic_vector(7 downto 0);
tmr_ack_i : in std_logic;
tmr_dat_o : out std_logic_vector(7 downto 0);
tmr_we_o : out std_logic;
tmr_adr_o : out std_logic_vector(2 downto 0);
tmr_stb_o : out std_logic;
-- t16
t16_dat_i : in std_logic_vector(7 downto 0);
t16_ack_i : in std_logic;
t16_dat_o : out std_logic_vector(7 downto 0);
t16_we_o : out std_logic;
t16_adr_o : out std_logic_vector(0 downto 0);
t16_stb_o : out std_logic;
-- clock and reset
wb_clk_i : in std_logic;
wb_rst_i : in std_logic);
end component WBDevIntercon;
end package WBDevInterconPkg;
-- Instantiation example:
-- library IEEE;
-- use IEEE.std_logic_1164.all;
-- use work.WBDevInterconPkg.all;
--
-- -- signals:
-- -- cpu
-- signal cpu_dati : std_logic_vector(7 downto 0);
-- signal cpu_acki : std_logic;
-- signal cpu_dato : std_logic_vector(7 downto 0);
-- signal cpu_weo : std_logic;
-- signal cpu_adro : std_logic_vector(7 downto 0);
-- signal cpu_cyco : std_logic;
-- signal cpu_stbo : std_logic;
-- -- rs2
-- signal rs2_dato : std_logic_vector(7 downto 0);
-- signal rs2_acko : std_logic;
-- signal rs2_dati : std_logic_vector(7 downto 0);
-- signal rs2_wei : std_logic;
-- signal rs2_adri : std_logic_vector(0 downto 0);
-- signal rs2_stbi : std_logic;
-- -- ad
-- signal ad_dato : std_logic_vector(7 downto 0);
-- signal ad_acko : std_logic;
-- signal ad_dati : std_logic_vector(7 downto 0);
-- signal ad_wei : std_logic;
-- signal ad_adri : std_logic_vector(0 downto 0);
-- signal ad_stbi : std_logic;
-- -- tmr
-- signal tmr_dato : std_logic_vector(7 downto 0);
-- signal tmr_acko : std_logic;
-- signal tmr_dati : std_logic_vector(7 downto 0);
-- signal tmr_wei : std_logic;
-- signal tmr_adri : std_logic_vector(2 downto 0);
-- signal tmr_stbi : std_logic;
-- -- t16
-- signal t16_dato : std_logic_vector(7 downto 0);
-- signal t16_acko : std_logic;
-- signal t16_dati : std_logic_vector(7 downto 0);
-- signal t16_wei : std_logic;
-- signal t16_adri : std_logic_vector(0 downto 0);
-- signal t16_stbi : std_logic;
--
-- intercon: WBDevIntercon
-- port map(
-- -- wishbone master port(s)
-- -- cpu
-- cpu_dat_o => cpu_dati,
-- cpu_ack_o => cpu_acki,
-- cpu_dat_i => cpu_dato,
-- cpu_we_i => cpu_weo,
-- cpu_adr_i => cpu_adro,
-- cpu_cyc_i => cpu_cyco,
-- cpu_stb_i => cpu_stbo,
-- -- wishbone slave port(s)
-- -- rs2
-- rs2_dat_i => rs2_dato,
-- rs2_ack_i => rs2_acko,
-- rs2_dat_o => rs2_dati,
-- rs2_we_o => rs2_wei,
-- rs2_adr_o => rs2_adri,
-- rs2_stb_o => rs2_stbi,
-- -- ad
-- ad_dat_i => ad_dato,
-- ad_ack_i => ad_acko,
-- ad_dat_o => ad_dati,
-- ad_we_o => ad_wei,
-- ad_adr_o => ad_adri,
-- ad_stb_o => ad_stbi,
-- -- tmr
-- tmr_dat_i => tmr_dato,
-- tmr_ack_i => tmr_acko,
-- tmr_dat_o => tmr_dati,
-- tmr_we_o => tmr_wei,
-- tmr_adr_o => tmr_adri,
-- tmr_stb_o => tmr_stbi,
-- -- t16
-- t16_dat_i => t16_dato,
-- t16_ack_i => t16_acko,
-- t16_dat_o => t16_dati,
-- t16_we_o => t16_wei,
-- t16_adr_o => t16_adri,
-- t16_stb_o => t16_stbi,
-- -- clock and reset
-- wb_clk_i => wb_clk_o,
-- wb_rst_i => wb_rst_o);
| gpl-2.0 | 7f764e97d93af2f622104dcbc2634195 | 0.524909 | 2.645362 | false | false | false | false |
MAV-RT-testbed/MAV-testbed | Syma_Flight_Final/Syma_Flight_Final.srcs/sources_1/ipshared/xilinx.com/axi_quad_spi_v3_2/c64e9f22/hdl/src/vhdl/qspi_mode_0_module.vhd | 1 | 92,630 | --
---- SPI Module - entity/architecture pair
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
---- Filename: qspi_mode_0_module.vhd
---- Version: v3.0
---- Description: Serial Peripheral Interface (SPI) Module for interfacing
---- with a 32-bit AXI4 Bus.
----
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg;
use lib_pkg_v1_0.lib_pkg.log2;
library axi_lite_ipif_v3_0;
use axi_lite_ipif_v3_0.axi_lite_ipif;
use axi_lite_ipif_v3_0.ipif_pkg.all;
library unisim;
use unisim.vcomponents.FD;
use unisim.vcomponents.FDRE;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------:
-- C_SCK_RATIO -- 2, 4, 16, 32, , , , 1024, 2048 SPI
-- clock ratio (16*N), where N=1,2,3...
-- C_SPI_NUM_BITS_REG -- Width of SPI Control register
-- in this module
-- C_NUM_SS_BITS -- Total number of SS-bits
-- C_NUM_TRANSFER_BITS -- SPI Serial transfer width.
-- Can be 8, 16 or 32 bit wide
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- SYSTEM
-- Bus2IP_Clk -- Bus to IP clock
-- Soft_Reset_op -- Soft_Reset_op Signal
-- OTHER INTERFACE
-- Slave_MODF_strobe -- Slave mode fault strobe
-- MODF_strobe -- Mode fault strobe
-- SR_3_MODF -- Mode fault error flag
-- SR_5_Tx_Empty -- Transmit Empty
-- Control_Reg -- Control Register
-- Slave_Select_Reg -- Slave Select Register
-- Transmit_Data -- Data Transmit Register Interface
-- Receive_Data -- Data Receive Register Interface
-- SPIXfer_done -- SPI transfer done flag
-- DTR_underrun -- DTR underrun generation signal
-- SPI INTERFACE
-- SCK_I -- SPI Bus Clock Input
-- SCK_O_reg -- SPI Bus Clock Output
-- SCK_T -- SPI Bus Clock 3-state Enable
-- (3-state when high)
-- MISO_I -- Master out,Slave in Input
-- MISO_O -- Master out,Slave in Output
-- MISO_T -- Master out,Slave in 3-state Enable
-- MOSI_I -- Master in,Slave out Input
-- MOSI_O -- Master in,Slave out Output
-- MOSI_T -- Master in,Slave out 3-state Enable
-- SPISEL -- Local SPI slave select active low input
-- has to be initialzed to VCC
-- SS_I -- Input of slave select vector
-- of length N input where there are
-- N SPI devices,but not connected
-- SS_O -- One-hot encoded,active low slave select
-- vector of length N ouput
-- SS_T -- Single 3-state control signal for
-- slave select vector of length N
-- (3-state when high)
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Declaration
-------------------------------------------------------------------------------
entity qspi_mode_0_module is
generic
(
--C_SPI_MODE : integer;
C_SCK_RATIO : integer;
C_NUM_SS_BITS : integer;
C_NUM_TRANSFER_BITS : integer;
C_USE_STARTUP : integer;
C_SPICR_REG_WIDTH : integer;
C_SUB_FAMILY : string;
C_FIFO_EXIST : integer
);
port
(
Bus2IP_Clk : in std_logic;
Soft_Reset_op : in std_logic;
----------------------
-- Control Reg is 10-bit wide
SPICR_0_LOOP : in std_logic;
SPICR_1_SPE : in std_logic;
SPICR_2_MASTER_N_SLV : in std_logic;
SPICR_3_CPOL : in std_logic;
SPICR_4_CPHA : in std_logic;
SPICR_5_TXFIFO_RST : in std_logic;
SPICR_6_RXFIFO_RST : in std_logic;
SPICR_7_SS : in std_logic;
SPICR_8_TR_INHIBIT : in std_logic;
SPICR_9_LSB : in std_logic;
----------------------
SR_3_MODF : in std_logic;
SR_5_Tx_Empty : in std_logic;
Slave_MODF_strobe : out std_logic;
MODF_strobe : out std_logic;
SPIXfer_done_rd_tx_en: out std_logic;
Slave_Select_Reg : in std_logic_vector(0 to (C_NUM_SS_BITS-1));
Transmit_Data : in std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
Receive_Data : out std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
SPIXfer_done : out std_logic;
DTR_underrun : out std_logic;
SPISEL_pulse_op : out std_logic;
SPISEL_d1_reg : out std_logic;
--SPI Interface
SCK_I : in std_logic;
SCK_O_reg : out std_logic;
SCK_T : out std_logic;
MISO_I : in std_logic;
MISO_O : out std_logic;
MISO_T : out std_logic;
MOSI_I : in std_logic;
MOSI_O : out std_logic;
MOSI_T : out std_logic;
SPISEL : in std_logic;
SS_I : in std_logic_vector((C_NUM_SS_BITS-1) downto 0);
SS_O : out std_logic_vector((C_NUM_SS_BITS-1) downto 0);
SS_T : out std_logic;
control_bit_7_8 : in std_logic_vector(0 to 1);
Mst_N_Slv_mode : out std_logic;
Rx_FIFO_Full : in std_logic;
reset_RcFIFO_ptr_to_spi : in std_logic;
DRR_Overrun_reg : out std_logic;
tx_cntr_xfer_done : out std_logic
);
end qspi_mode_0_module;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of qspi_mode_0_module is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Function Declarations
---------------------------------------------------------------------
------------------------
-- spcl_log2 : Performs log2(x) function for value of C_SCK_RATIO > 2
------------------------
function spcl_log2(x : natural) return integer is
variable j : integer := 0;
variable k : integer := 0;
begin
if(C_SCK_RATIO /= 2) then
for i in 0 to 11 loop
if(2**i >= x) then
if(k = 0) then
j := i;
end if;
k := 1;
end if;
end loop;
return j;
else
-- coverage off
return 2;
-- coverage on
end if;
end spcl_log2;
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
if x = 0 then return 0;
else
for j in 0 to 29 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
assert val >= x
report "Function log2 received argument larger" &
" than its capability of 2^30. "
severity failure;
-- synthesis translate_on
return i;
end if;
end function log2;
-------------------------------------------------------------------------------
-- Constant Declarations
------------------------------------------------------------------
constant RESET_ACTIVE : std_logic := '1';
constant COUNT_WIDTH : INTEGER := log2(C_NUM_TRANSFER_BITS)+1;
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal Ratio_Count : std_logic_vector
(0 to (spcl_log2(C_SCK_RATIO))-2);
signal Count : std_logic_vector
(COUNT_WIDTH downto 0)
:= (others => '0');
signal LSB_first : std_logic;
signal Mst_Trans_inhibit : std_logic;
signal Manual_SS_mode : std_logic;
signal CPHA : std_logic;
signal CPOL : std_logic;
signal Mst_N_Slv : std_logic;
signal SPI_En : std_logic;
signal Loop_mode : std_logic;
signal transfer_start : std_logic;
signal transfer_start_d1 : std_logic;
signal transfer_start_pulse : std_logic;
signal SPIXfer_done_int : std_logic;
signal SPIXfer_done_int_d1 : std_logic;
signal SPIXfer_done_int_pulse : std_logic;
signal SPIXfer_done_int_pulse_d1 : std_logic;
signal sck_o_int : std_logic;
signal sck_o_in : std_logic;
signal Count_trigger : std_logic;
signal Count_trigger_d1 : std_logic;
signal Count_trigger_pulse : std_logic;
signal Sync_Set : std_logic;
signal Sync_Reset : std_logic;
signal Serial_Dout : std_logic;
signal Serial_Din : std_logic;
signal Shift_Reg : std_logic_vector
(0 to C_NUM_TRANSFER_BITS-1);
signal SS_Asserted : std_logic;
signal SS_Asserted_1dly : std_logic;
signal Allow_Slave_MODF_Strobe : std_logic;
signal Allow_MODF_Strobe : std_logic;
signal Loading_SR_Reg_int : std_logic;
signal sck_i_d1 : std_logic;
signal spisel_d1 : std_logic;
signal spisel_pulse : std_logic;
signal rising_edge_sck_i : std_logic;
signal falling_edge_sck_i : std_logic;
signal edge_sck_i : std_logic;
signal MODF_strobe_int : std_logic;
signal master_tri_state_en_control: std_logic;
signal slave_tri_state_en_control: std_logic;
-- following signals are added for use in variouos clock ratio modes.
signal sck_d1 : std_logic;
signal sck_d2 : std_logic;
signal sck_rising_edge : std_logic;
signal rx_shft_reg : std_logic_vector(0 to C_NUM_TRANSFER_BITS-1);
signal SPIXfer_done_int_pulse_d2 : std_logic;
signal SPIXfer_done_int_pulse_d3 : std_logic;
-- added synchronization signals for SPISEL and SCK_I
signal SPISEL_sync : std_logic;
signal SCK_I_sync : std_logic;
-- following register are declared for making data path clear in different modes
signal rx_shft_reg_s : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1))
:=(others => '0');
signal rx_shft_reg_mode_0011 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1))
:=(others => '0');
signal rx_shft_reg_mode_0110 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1))
:=(others => '0');
signal sck_fe1 : std_logic;
signal sck_d21 : std_logic:='0';
signal sck_d11 : std_logic:='0';
signal SCK_O_1 : std_logic:='0';
signal receive_Data_int : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1))
:=(others => '0');
signal mosi_i_sync : std_logic;
signal miso_i_sync : std_logic;
signal serial_dout_int : std_logic;
--
attribute IOB : string;
--attribute IOB of SPI_TRISTATE_CONTROL_II : label is "true";
attribute IOB of SPI_TRISTATE_CONTROL_III : label is "false";
--attribute IOB of SPI_TRISTATE_CONTROL_IV : label is "true";
attribute IOB of SPI_TRISTATE_CONTROL_V : label is "false";
--attribute IOB of OTHER_RATIO_GENERATE : label is "true";
--attribute IOB of SCK_I_REG : label is "true";
--attribute IOB of SPISEL_REG : label is "true";
signal Mst_Trans_inhibit_d1, Mst_Trans_inhibit_pulse : std_logic;
signal no_slave_selected : std_logic;
type STATE_TYPE is
(IDLE, -- decode command can be combined here later
TRANSFER_OKAY,
TEMP_TRANSFER_OKAY
);
signal spi_cntrl_ps: STATE_TYPE;
signal spi_cntrl_ns: STATE_TYPE;
signal stop_clock_reg : std_logic;
signal stop_clock : std_logic;
signal Rx_FIFO_Full_reg, DRR_Overrun_reg_int : std_logic;
signal transfer_start_d2 : std_logic;
signal transfer_start_d3 : std_logic;
signal SR_5_Tx_Empty_d1 : std_logic;
signal SR_5_Tx_Empty_pulse: std_logic;
signal SR_5_Tx_comeplete_Empty : std_logic;
signal falling_edge_sck_i_d1, rising_edge_sck_i_d1 : std_logic;
signal spisel_d2 : std_logic;
signal xfer_done_fifo_0 : std_logic;
signal rst_xfer_done_fifo_0 : std_logic;
-------------------------------------------------------------------------------
-- Architecture Starts
-------------------------------------------------------------------------------
begin
--------------------------------------------------
LOCAL_TX_EMPTY_RX_FULL_FIFO_0_GEN: if C_FIFO_EXIST = 0 generate
-----
begin
-----------------------------------------
TX_EMPTY_MODE_0_P: process (Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) or
(transfer_start_pulse = '1') or
(rst_xfer_done_fifo_0 = '1')then
xfer_done_fifo_0 <= '0';
elsif(SPIXfer_done_int_pulse = '1')then
xfer_done_fifo_0 <= '1';
end if;
end if;
end process TX_EMPTY_MODE_0_P;
------------------------------
RX_FULL_CHECK_PROCESS: process(Bus2IP_Clk) is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE)or(reset_RcFIFO_ptr_to_spi = '1') then
Rx_FIFO_Full_reg <= '0';
elsif(SPIXfer_done_int_pulse = '1')then
Rx_FIFO_Full_reg <= '1';
end if;
end if;
end process RX_FULL_CHECK_PROCESS;
-----------------------------------
PS_TO_NS_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
spi_cntrl_ps <= IDLE;
stop_clock_reg <= '0';
else
spi_cntrl_ps <= spi_cntrl_ns;
stop_clock_reg <= stop_clock;
end if;
end if;
end process PS_TO_NS_PROCESS;
-----------------------------
SPI_STATE_MACHINE_P: process(
Mst_N_Slv,
stop_clock_reg,
spi_cntrl_ps,
no_slave_selected,
SR_5_Tx_Empty,
SPIXfer_done_int_pulse,
transfer_start_pulse,
xfer_done_fifo_0
)
begin
stop_clock <= '0';
rst_xfer_done_fifo_0 <= '0';
--------------------------
case spi_cntrl_ps is
--------------------------
when IDLE => if(SR_5_Tx_Empty = '0' and transfer_start_pulse = '1' and Mst_N_Slv = '1') then
stop_clock <= '0';
spi_cntrl_ns <= TRANSFER_OKAY;
else
stop_clock <= SR_5_Tx_Empty;
spi_cntrl_ns <= IDLE;
end if;
-------------------------------------
when TRANSFER_OKAY => if(SR_5_Tx_Empty = '1') then
if(no_slave_selected = '1')then
stop_clock <= '1';
spi_cntrl_ns <= IDLE;
else
spi_cntrl_ns <= TEMP_TRANSFER_OKAY;
end if;
else
spi_cntrl_ns <= TRANSFER_OKAY;
end if;
-------------------------------------
when TEMP_TRANSFER_OKAY => stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
stop_clock <= xfer_done_fifo_0;
if (no_slave_selected = '1')then
spi_cntrl_ns <= IDLE;
--code coverage -- elsif(SPIXfer_done_int_pulse='1')then
--code coverage -- stop_clock <= SR_5_Tx_Empty;
--code coverage -- spi_cntrl_ns <= TEMP_TRANSFER_OKAY;
else
spi_cntrl_ns <= TEMP_TRANSFER_OKAY;
end if;
else
stop_clock <= '0';
rst_xfer_done_fifo_0 <= '1';
spi_cntrl_ns <= TRANSFER_OKAY;
end if;
-------------------------------------
-- coverage off
when others => spi_cntrl_ns <= IDLE;
-- coverage on
-------------------------------------
end case;
--------------------------
end process SPI_STATE_MACHINE_P;
-----------------------------------------------
end generate LOCAL_TX_EMPTY_RX_FULL_FIFO_0_GEN;
-------------------------------------------------------------------------------
LOCAL_TX_EMPTY_FIFO_12_GEN: if C_FIFO_EXIST /= 0 generate
-----
begin
-----
xfer_done_fifo_0 <= '0';
RX_FULL_CHECK_PROCESS: process(Bus2IP_Clk) is
----------------------
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
Rx_FIFO_Full_reg <= '0';
elsif(reset_RcFIFO_ptr_to_spi = '1') or (DRR_Overrun_reg_int = '1') then
Rx_FIFO_Full_reg <= '0';
elsif(SPIXfer_done_int_pulse = '1')and (Rx_FIFO_Full = '1') then
Rx_FIFO_Full_reg <= '1';
end if;
end if;
end process RX_FULL_CHECK_PROCESS;
----------------------------------
PS_TO_NS_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
spi_cntrl_ps <= IDLE;
stop_clock_reg <= '0';
else
spi_cntrl_ps <= spi_cntrl_ns;
stop_clock_reg <= stop_clock;
end if;
end if;
end process PS_TO_NS_PROCESS;
-----------------------------
SPI_STATE_MACHINE_P: process(
Mst_N_Slv ,
stop_clock_reg ,
spi_cntrl_ps ,
no_slave_selected ,
SR_5_Tx_Empty ,
SPIXfer_done_int_pulse ,
transfer_start_pulse ,
SPIXfer_done_int_pulse_d2,
SR_5_Tx_comeplete_Empty,
Loop_mode
)is
-----
begin
-----
stop_clock <= '0';
--rst_xfer_done_fifo_0 <= '0';
--------------------------
case spi_cntrl_ps is
--------------------------
when IDLE => if(SR_5_Tx_Empty = '0' and transfer_start_pulse = '1' and Mst_N_Slv = '1') then
spi_cntrl_ns <= TRANSFER_OKAY;
stop_clock <= '0';
else
stop_clock <= SR_5_Tx_Empty;
spi_cntrl_ns <= IDLE;
end if;
-------------------------------------
when TRANSFER_OKAY => if(SR_5_Tx_Empty = '1') then
--if(no_slave_selected = '1')then
if(SR_5_Tx_comeplete_Empty = '1' and
SPIXfer_done_int_pulse_d2 = '1') then
stop_clock <= '1';
spi_cntrl_ns <= IDLE;
else
spi_cntrl_ns <= TEMP_TRANSFER_OKAY;
end if;
else
spi_cntrl_ns <= TRANSFER_OKAY;
end if;
-------------------------------------
when TEMP_TRANSFER_OKAY => stop_clock <= stop_clock_reg;
--if(SR_5_Tx_Empty='1')then
if(SR_5_Tx_comeplete_Empty='1')then
-- stop_clock <= xfer_done_fifo_0;
if (Loop_mode = '1' and
SPIXfer_done_int_pulse_d2 = '1')then
stop_clock <= '1';
spi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse_d2 = '1')then
stop_clock <= SR_5_Tx_Empty;
spi_cntrl_ns <= TEMP_TRANSFER_OKAY;
elsif(no_slave_selected = '1') then
stop_clock <= '1';
spi_cntrl_ns <= IDLE;
else
spi_cntrl_ns <= TEMP_TRANSFER_OKAY;
end if;
else
--stop_clock <= '0';
--rst_xfer_done_fifo_0 <= '1';
spi_cntrl_ns <= TRANSFER_OKAY;
end if;
-------------------------------------
-- coverage off
when others => spi_cntrl_ns <= IDLE;
-- coverage on
-------------------------------------
end case;
--------------------------
end process SPI_STATE_MACHINE_P;
----------------------------------------
----------------------------------------
end generate LOCAL_TX_EMPTY_FIFO_12_GEN;
-----------------------------------------
SR_5_TX_EMPTY_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
SR_5_Tx_Empty_d1 <= '0';
else
SR_5_Tx_Empty_d1 <= SR_5_Tx_Empty;
end if;
end if;
end process SR_5_TX_EMPTY_PROCESS;
----------------------------------
SR_5_Tx_Empty_pulse <= SR_5_Tx_Empty_d1 and not (SR_5_Tx_Empty);
----------------------------------
-------------------------------------------------------------------------------
-- Combinatorial operations
-------------------------------------------------------------------------------
-----------------------------------------------------------
LSB_first <= SPICR_9_LSB; -- Control_Reg(0);
Mst_Trans_inhibit <= SPICR_8_TR_INHIBIT; -- Control_Reg(1);
Manual_SS_mode <= SPICR_7_SS; -- Control_Reg(2);
CPHA <= SPICR_4_CPHA; -- Control_Reg(5);
CPOL <= SPICR_3_CPOL; -- Control_Reg(6);
Mst_N_Slv <= SPICR_2_MASTER_N_SLV; -- Control_Reg(7);
SPI_En <= SPICR_1_SPE; -- Control_Reg(8);
Loop_mode <= SPICR_0_LOOP; -- Control_Reg(9);
Mst_N_Slv_mode <= SPICR_2_MASTER_N_SLV; -- Control_Reg(7);
-----------------------------------------------------------
MOSI_O <= Serial_Dout;
MISO_O <= Serial_Dout;
Receive_Data <= receive_Data_int;
DRR_Overrun_reg <= DRR_Overrun_reg_int;
DRR_OVERRUN_REG_PROCESS:process(Bus2IP_Clk) is
-----
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
DRR_Overrun_reg_int <= '0';
else
DRR_Overrun_reg_int <= not(DRR_Overrun_reg_int or Soft_Reset_op) and
Rx_FIFO_Full_reg and
SPIXfer_done_int_pulse; --_d2;
end if;
end if;
end process DRR_OVERRUN_REG_PROCESS;
MST_TRANS_INHIBIT_D1_I: component FD
generic map
(
INIT => '1'
)
port map
(
Q => Mst_Trans_inhibit_d1,
C => Bus2IP_Clk,
D => Mst_Trans_inhibit
);
Mst_Trans_inhibit_pulse <= Mst_Trans_inhibit and (not Mst_Trans_inhibit_d1);
-------------------------------------------------------------------------------
--* -------------------------------------------------------------------------------
--* -- MASTER_TRIST_EN_PROCESS : If not master make tristate enabled
--* ----------------------------
master_tri_state_en_control <=
'0' when
(
(control_bit_7_8(0)='1') and -- decides master/slave mode
(control_bit_7_8(1)='1') and -- decide the spi_en
((MODF_strobe_int or SR_3_MODF)='0') and --no mode fault
(Loop_mode = '0')
) else
'1';
--SPI_TRISTATE_CONTROL_II : Tri-state register for SCK_T, ideal state-deactive
SPI_TRISTATE_CONTROL_II: component FD
generic map
(
INIT => '1'
)
port map
(
Q => SCK_T,
C => Bus2IP_Clk,
D => master_tri_state_en_control
);
--SPI_TRISTATE_CONTROL_III: tri-state register for MOSI, ideal state-deactive
SPI_TRISTATE_CONTROL_III: component FD
generic map
(
INIT => '1'
)
port map
(
Q => MOSI_T,
C => Bus2IP_Clk,
D => master_tri_state_en_control
);
--SPI_TRISTATE_CONTROL_IV: tri-state register for SS,ideal state-deactive
SPI_TRISTATE_CONTROL_IV: component FD
generic map
(
INIT => '1'
)
port map
(
Q => SS_T,
C => Bus2IP_Clk,
D => master_tri_state_en_control
);
--* -------------------------------------------------------------------------------
--* -- SLAVE_TRIST_EN_PROCESS : If slave mode, then make tristate enabled
--* ---------------------------
slave_tri_state_en_control <=
'0' when
(
(control_bit_7_8(0)='0') and -- decides master/slave
(control_bit_7_8(1)='1') and -- decide the spi_en
(SPISEL_sync = '0') and
(Loop_mode = '0')
) else
'1';
--SPI_TRISTATE_CONTROL_V: tri-state register for MISO, ideal state-deactive
SPI_TRISTATE_CONTROL_V: component FD
generic map
(
INIT => '1'
)
port map
(
Q => MISO_T,
C => Bus2IP_Clk,
D => slave_tri_state_en_control
);
-------------------------------------------------------------------------------
DTR_COMPLETE_EMPTY_P:process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1')then
if(SR_5_Tx_Empty = '1' and SPIXfer_done_int_pulse = '1')then
SR_5_Tx_comeplete_Empty <= '1';
elsif(SR_5_Tx_Empty = '0')then
SR_5_Tx_comeplete_Empty <= '0';
end if;
end if;
end process DTR_COMPLETE_EMPTY_P;
---------------------------------
DTR_UNDERRUN_FIFO_0_GEN: if C_FIFO_EXIST = 0 generate
begin
-- DTR_UNDERRUN_PROCESS_P : For Generating DTR underrun error
-------------------------
DTR_UNDERRUN_PROCESS_P: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or
(SPISEL_sync = '1') or
(Mst_N_Slv = '1')--master mode
) then
DTR_underrun <= '0';
elsif((Mst_N_Slv = '0') and (SPI_En = '1')) then-- slave mode
if (SR_5_Tx_comeplete_Empty = '1') then
--if(SPIXfer_done_int_pulse_d2 = '1') then
DTR_underrun <= '1';
--end if;
else
DTR_underrun <= '0';
end if;
end if;
end if;
end process DTR_UNDERRUN_PROCESS_P;
-------------------------------------
end generate DTR_UNDERRUN_FIFO_0_GEN;
DTR_UNDERRUN_FIFO_EXIST_GEN: if C_FIFO_EXIST /= 0 generate
begin
-- DTR_UNDERRUN_PROCESS_P : For Generating DTR underrun error
-------------------------
DTR_UNDERRUN_PROCESS_P: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or
(SPISEL_sync = '1') or
(Mst_N_Slv = '1')--master mode
) then
DTR_underrun <= '0';
elsif((Mst_N_Slv = '0') and (SPI_En = '1')) then-- slave mode
if (SR_5_Tx_comeplete_Empty = '1') then
if(SPIXfer_done_int_pulse = '1') then
DTR_underrun <= '1';
end if;
else
DTR_underrun <= '0';
end if;
end if;
end if;
end process DTR_UNDERRUN_PROCESS_P;
-------------------------------------
end generate DTR_UNDERRUN_FIFO_EXIST_GEN;
-------------------------------------------------------------------------------
-- SPISEL_SYNC: first synchronize the incoming signal, this is required is slave
--------------- mode of the core.
SPISEL_REG: component FD
generic map
(
INIT => '1' -- default '1' to make the device in default master mode
)
port map
(
Q => SPISEL_sync,
C => Bus2IP_Clk,
D => SPISEL
);
---- SPISEL_DELAY_1CLK_PROCESS_P : Detect active SCK edge in slave mode
-------------------------------
SPISEL_DELAY_1CLK_PROCESS_P: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
spisel_d1 <= '1';
spisel_d2 <= '1';
else
spisel_d1 <= SPISEL_sync;
spisel_d2 <= spisel_d1;
end if;
end if;
end process SPISEL_DELAY_1CLK_PROCESS_P;
--SPISEL_DELAY_1CLK: component FD
-- generic map
-- (
-- INIT => '1' -- default '1' to make the device in default master mode
-- )
-- port map
-- (
-- Q => spisel_d1,
-- C => Bus2IP_Clk,
-- D => SPISEL_sync
-- );
--SPISEL_DELAY_2CLK: component FD
-- generic map
-- (
-- INIT => '1' -- default '1' to make the device in default master mode
-- )
-- port map
-- (
-- Q => spisel_d2,
-- C => Bus2IP_Clk,
-- D => spisel_d1
-- );
---- spisel pulse generating logic
---- this one clock cycle pulse will be available for data loading into
---- shift register
--spisel_pulse <= (not SPISEL_sync) and spisel_d1;
------------------------------------------------
-- spisel pulse generating logic
-- this one clock cycle pulse will be available for data loading into
-- shift register
spisel_pulse <= (not spisel_d1) and spisel_d2;
-- --------|__________ -- SPISEL
-- ----------|________ -- SPISEL_sync
-- -------------|_____ -- spisel_d1
-- ----------------|___-- spisel_d2
-- _____________|--|__ -- SPISEL_pulse_op
SPISEL_pulse_op <= spisel_pulse;
SPISEL_d1_reg <= spisel_d2;
-------------------------------------------------------------------------------
--SCK_I_SYNC: first synchronize incomming signal
-------------
SCK_I_REG: component FD
generic map
(
INIT => '0'
)
port map
(
Q => SCK_I_sync,
C => Bus2IP_Clk,
D => SCK_I
);
------------------------------------------------------------------
-- SCK_I_DELAY_1CLK_PROCESS : Detect active SCK edge in slave mode on +ve edge
SCK_I_DELAY_1CLK_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
sck_i_d1 <= '0';
else
sck_i_d1 <= SCK_I_sync;
end if;
end if;
end process SCK_I_DELAY_1CLK_PROCESS;
-------------------------------------------------------------------------------
-- RISING_EDGE_CLK_RATIO_4_GEN: to synchronise the incoming clock signal in
-- slave mode in SCK ratio = 4
RISING_EDGE_CLK_RATIO_4_GEN : if C_SCK_RATIO = 4 generate
begin
-- generate a SCK control pulse for rising edge as well as falling edge
rising_edge_sck_i <= SCK_I and (not(SCK_I_sync)) and (not(SPISEL_sync));
falling_edge_sck_i <= (not(SCK_I) and SCK_I_sync) and (not(SPISEL_sync));
end generate RISING_EDGE_CLK_RATIO_4_GEN;
-------------------------------------------------------------------------------
-- RISING_EDGE_CLK_RATIO_OTHERS_GEN: Due to timing crunch, in SCK> 4 mode,
-- the incoming clock signal cant be synchro
-- -nized with internal AXI clock.
-- slave mode operation on SCK_RATIO=2 isn't
-- supported in the core.
RISING_EDGE_CLK_RATIO_OTHERS_GEN: if ((C_SCK_RATIO /= 2) and (C_SCK_RATIO /= 4))
generate
begin
-- generate a SCK control pulse for rising edge as well as falling edge
rising_edge_sck_i <= SCK_I_sync and (not(sck_i_d1)) and (not(SPISEL_sync));
falling_edge_sck_i <= (not(SCK_I_sync) and sck_i_d1) and (not(SPISEL_sync));
end generate RISING_EDGE_CLK_RATIO_OTHERS_GEN;
-------------------------------------------------------------------------------
-- combine rising edge as well as falling edge as a single signal
edge_sck_i <= rising_edge_sck_i or falling_edge_sck_i;
no_slave_selected <= and_reduce(Slave_Select_Reg(0 to (C_NUM_SS_BITS-1)));
-------------------------------------------------------------------------------
-- TRANSFER_START_PROCESS : Generate transfer start signal. When the transfer
-- gets completed, SPI Transfer done strobe pulls
-- transfer_start back to zero.
---------------------------
TRANSFER_START_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE or
(
Mst_N_Slv = '1' and -- If Master Mode
(
SPI_En = '0' or -- enable not asserted or
(SPIXfer_done_int = '1' and SR_5_Tx_Empty = '1') or -- no data in Tx reg/FIFO or
SR_3_MODF = '1' or -- mode fault error
Mst_Trans_inhibit = '1' or -- Do not start if Mst xfer inhibited
stop_clock = '1'
)
) or
(
Mst_N_Slv = '0' and -- If Slave Mode
(
SPI_En = '0' -- enable not asserted or
)
)
)then
transfer_start <= '0';
else
-- Delayed SPIXfer_done_int_pulse to work for synchronous design and to remove
-- asserting of loading_sr_reg in master mode after SR_5_Tx_Empty goes to 1
--if((SPIXfer_done_int_pulse = '1') or
-- (SPIXfer_done_int_pulse_d1 = '1') or
-- (SPIXfer_done_int_pulse_d2='1')) then-- this is added to remove
-- -- glitch at the end of
-- -- transfer in AUTO mode
-- transfer_start <= '0'; -- Set to 0 for at least 1 period
-- else
transfer_start <= '1'; -- Proceed with SPI Transfer
-- end if;
end if;
end if;
end process TRANSFER_START_PROCESS;
-------------------------------------------------------------------------------
-- TRANSFER_START_1CLK_PROCESS : Delay transfer start by 1 clock cycle
--------------------------------
TRANSFER_START_1CLK_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
transfer_start_d1 <= '0';
transfer_start_d2 <= '0';
transfer_start_d3 <= '0';
else
transfer_start_d1 <= transfer_start;
transfer_start_d2 <= transfer_start_d1;
transfer_start_d3 <= transfer_start_d2;
end if;
end if;
end process TRANSFER_START_1CLK_PROCESS;
-- transfer start pulse generating logic
transfer_start_pulse <= transfer_start and (not(transfer_start_d1));
---------------------------------------------------------------------------------
---- TRANSFER_DONE_PROCESS : Generate SPI transfer done signal
----------------------------
--TRANSFER_DONE_PROCESS: process(Bus2IP_Clk)
--begin
-- if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
-- if(Soft_Reset_op = RESET_ACTIVE or transfer_start_pulse = '1' or (and_reduce(Count(COUNT_WIDTH-1 downto (COUNT_WIDTH-COUNT_WIDTH)))='1')) then
-- SPIXfer_done_int <= '0';
-- --elsif (transfer_start_pulse = '1') then
-- -- SPIXfer_done_int <= '0';
-- elsif(and_reduce(Count((COUNT_WIDTH-1) downto (COUNT_WIDTH-COUNT_WIDTH+1))) = '1') then --(Count(COUNT_WIDTH) = '1') then
-- SPIXfer_done_int <= '1';
-- end if;
-- end if;
--end process TRANSFER_DONE_PROCESS;
-------------------------------------------------------------------------------
-- TRANSFER_DONE_1CLK_PROCESS : Delay SPI transfer done signal by 1 clock cycle
-------------------------------
TRANSFER_DONE_1CLK_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
SPIXfer_done_int_d1 <= '0';
else
SPIXfer_done_int_d1 <= SPIXfer_done_int;
end if;
end if;
end process TRANSFER_DONE_1CLK_PROCESS;
--
-- transfer done pulse generating logic
SPIXfer_done_int_pulse <= SPIXfer_done_int and (not(SPIXfer_done_int_d1));
-------------------------------------------------------------------------------
-- TRANSFER_DONE_PULSE_DLY_PROCESS : Delay SPI transfer done pulse by 1 and 2
-- clock cycles
------------------------------------
-- Delay the Done pulse by a further cycle. This is used as the output Rx
-- data strobe when C_SCK_RATIO = 2
TRANSFER_DONE_PULSE_DLY_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
SPIXfer_done_int_pulse_d1 <= '0';
SPIXfer_done_int_pulse_d2 <= '0';
SPIXfer_done_int_pulse_d3 <= '0';
else
SPIXfer_done_int_pulse_d1 <= SPIXfer_done_int_pulse;
SPIXfer_done_int_pulse_d2 <= SPIXfer_done_int_pulse_d1;
SPIXfer_done_int_pulse_d3 <= SPIXfer_done_int_pulse_d2;
end if;
end if;
end process TRANSFER_DONE_PULSE_DLY_PROCESS;
-------------------------------------------------------------------------------
-- RX_DATA_GEN1: Only for C_SCK_RATIO = 2 mode.
----------------
RX_DATA_SCK_RATIO_2_GEN1 : if C_SCK_RATIO = 2 generate
begin
-----
TRANSFER_DONE_8: if C_NUM_TRANSFER_BITS = 8 generate
TRANSFER_DONE_PROCESS_8: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE or transfer_start_pulse = '1' or SPIXfer_done_int = '1') then -- or (and_reduce(Count(COUNT_WIDTH-1 downto (COUNT_WIDTH-COUNT_WIDTH)))='1')) then
SPIXfer_done_int <= '0';
elsif (Count(COUNT_WIDTH-1) = '1' and
Count(COUNT_WIDTH-2) = '1' and
Count(COUNT_WIDTH-3) = '1' and
Count(COUNT_WIDTH-4) = '0') then
SPIXfer_done_int <= '1';
end if;
end if;
end process TRANSFER_DONE_PROCESS_8;
end generate TRANSFER_DONE_8;
TRANSFER_DONE_16: if C_NUM_TRANSFER_BITS = 16 generate
TRANSFER_DONE_PROCESS_16: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE or transfer_start_pulse = '1' or SPIXfer_done_int = '1') then -- or (and_reduce(Count(COUNT_WIDTH-1 downto (COUNT_WIDTH-COUNT_WIDTH)))='1')) then
SPIXfer_done_int <= '0';
elsif (Count(COUNT_WIDTH-1) = '1' and
Count(COUNT_WIDTH-2) = '1' and
Count(COUNT_WIDTH-3) = '1' and
Count(COUNT_WIDTH-4) = '1' and
Count(COUNT_WIDTH-5) = '0') then
SPIXfer_done_int <= '1';
end if;
end if;
end process TRANSFER_DONE_PROCESS_16;
end generate TRANSFER_DONE_16;
TRANSFER_DONE_32: if C_NUM_TRANSFER_BITS = 32 generate
TRANSFER_DONE_PROCESS_32: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE or transfer_start_pulse = '1' or SPIXfer_done_int = '1') then -- or (and_reduce(Count(COUNT_WIDTH-1 downto (COUNT_WIDTH-COUNT_WIDTH)))='1')) then
SPIXfer_done_int <= '0';
elsif (Count(COUNT_WIDTH-1) = '1' and
Count(COUNT_WIDTH-2) = '1' and
Count(COUNT_WIDTH-3) = '1' and
Count(COUNT_WIDTH-4) = '1' and
Count(COUNT_WIDTH-5) = '1' and
Count(COUNT_WIDTH-6) = '0') then
SPIXfer_done_int <= '1';
end if;
end if;
end process TRANSFER_DONE_PROCESS_32;
end generate TRANSFER_DONE_32;
-- This is mux to choose the data register for SPI mode 00,11 and 01,10.
rx_shft_reg <= rx_shft_reg_mode_0011
when ((CPOL = '0' and CPHA = '0') or (CPOL = '1' and CPHA = '1'))
else rx_shft_reg_mode_0110
when ((CPOL = '0' and CPHA = '1') or (CPOL = '1' and CPHA = '0'))
else
(others=>'0');
-- RECEIVE_DATA_STROBE_PROCESS : Strobe data from shift register to receive
-- data register
--------------------------------
-- For a SCK ratio of 2 the Done needs to be delayed by an extra cycle
-- due to the serial input being captured on the falling edge of the PLB
-- clock. this is purely required for dealing with the real SPI slave memories.
RECEIVE_DATA_STROBE_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Loop_mode = '1') then
if(SPIXfer_done_int_pulse_d1 = '1') then
if (LSB_first = '1') then
for i in 0 to C_NUM_TRANSFER_BITS-1 loop
receive_Data_int(i) <= Shift_Reg(C_NUM_TRANSFER_BITS-1-i);
end loop;
else
receive_Data_int <= Shift_Reg;
end if;
end if;
else
if(SPIXfer_done_int_pulse_d2 = '1') then
if (LSB_first = '1') then
for i in 0 to C_NUM_TRANSFER_BITS-1 loop
receive_Data_int(i) <= rx_shft_reg(C_NUM_TRANSFER_BITS-1-i);
end loop;
else
receive_Data_int <= rx_shft_reg;
end if;
end if;
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS;
-- Done strobe delayed to match receive data
SPIXfer_done <= SPIXfer_done_int_pulse_d3;
SPIXfer_done_rd_tx_en <= transfer_start_pulse or SPIXfer_done_int_pulse_d3; -- SPIXfer_done_int_pulse_d1;
tx_cntr_xfer_done <= transfer_start_pulse or SPIXfer_done_int_pulse_d3;
-------------------------------------------------
end generate RX_DATA_SCK_RATIO_2_GEN1;
-------------------------------------------------------------------------------
-- RX_DATA_GEN_OTHER_RATIOS: This logic is for other SCK ratios than
---------------------------- C_SCK_RATIO =2
RX_DATA_GEN_OTHER_SCK_RATIOS : if C_SCK_RATIO /= 2 generate
begin
FIFO_PRESENT_GEN: if C_FIFO_EXIST = 1 generate
-----
begin
-----
-------------------------------------------------------------------------------
-- TRANSFER_DONE_PROCESS : Generate SPI transfer done signal
--------------------------
TRANSFER_DONE_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE or
transfer_start_pulse = '1' or
SPIXfer_done_int = '1') then -- or (and_reduce(Count(COUNT_WIDTH-1 downto (COUNT_WIDTH-COUNT_WIDTH)))='1')) then
SPIXfer_done_int <= '0';
elsif(Mst_N_Slv = '1') and ((CPOL xor CPHA) = '1') and
--and_reduce(Count((COUNT_WIDTH-1) downto (COUNT_WIDTH-COUNT_WIDTH))) ='1'
((and_reduce(Count((COUNT_WIDTH-1) downto 0)) = '1') and (or_reduce(ratio_count) = '0'))
then
SPIXfer_done_int <= '1';
elsif(Mst_N_Slv = '1') and ((CPOL xor CPHA) = '0') and
--and_reduce(Count((COUNT_WIDTH-1) downto (COUNT_WIDTH-COUNT_WIDTH))) ='1'
((and_reduce(Count((COUNT_WIDTH-1) downto 0)) = '1') and (or_reduce(ratio_count) = '0'))
-- ((Count(COUNT_WIDTH) ='1') and (or_reduce(Count((COUNT_WIDTH-1) downto 0)) = '0'))
and
Count_trigger = '1'
then
SPIXfer_done_int <= '1';
elsif--(Mst_N_Slv = '0') and
and_reduce(Count((COUNT_WIDTH-1) downto (COUNT_WIDTH-COUNT_WIDTH+1))) ='1' then
if((CPOL xor CPHA) = '0') and rising_edge_sck_i = '1' then
SPIXfer_done_int <= '1';
elsif((CPOL xor CPHA) = '1') and falling_edge_sck_i = '1' then
SPIXfer_done_int <= '1';
end if;
end if;
end if;
end process TRANSFER_DONE_PROCESS;
-- TRANSFER_DONE_PROCESS: process(Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
-- if(Soft_Reset_op = RESET_ACTIVE or
-- transfer_start_pulse = '1' or
-- SPIXfer_done_int = '1') then -- or (and_reduce(Count(COUNT_WIDTH-1 downto (COUNT_WIDTH-COUNT_WIDTH)))='1')) then
-- SPIXfer_done_int <= '0';
-- elsif(Mst_N_Slv = '1') and
-- --and_reduce(Count((COUNT_WIDTH-1) downto (COUNT_WIDTH-COUNT_WIDTH))) ='1'
-- ((Count(COUNT_WIDTH) ='1') and (or_reduce(Count((COUNT_WIDTH-1) downto 0)) = '0'))
-- and
-- Count_trigger = '1'
-- then
-- SPIXfer_done_int <= '1';
-- elsif--(Mst_N_Slv = '0') and
-- and_reduce(Count((COUNT_WIDTH-1) downto (COUNT_WIDTH-COUNT_WIDTH+1))) ='1' then
-- if((CPOL xor CPHA) = '0') and rising_edge_sck_i = '1' then
-- SPIXfer_done_int <= '1';
-- elsif((CPOL xor CPHA) = '1') and falling_edge_sck_i = '1' then
-- SPIXfer_done_int <= '1';
-- end if;
-- end if;
-- end if;
-- end process TRANSFER_DONE_PROCESS;
end generate FIFO_PRESENT_GEN;
--------------------------------------------------------------
FIFO_ABSENT_GEN: if C_FIFO_EXIST = 0 generate
-----
begin
-----
-------------------------------------------------------------------------------
-- TRANSFER_DONE_PROCESS : Generate SPI transfer done signal
--------------------------
TRANSFER_DONE_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE or
transfer_start_pulse = '1' or
SPIXfer_done_int = '1') then
SPIXfer_done_int <= '0';
elsif(Mst_N_Slv = '1') and
((Count(COUNT_WIDTH) ='1') and (or_reduce(Count((COUNT_WIDTH-1) downto 0)) = '0'))
and
Count_trigger = '1'
then
SPIXfer_done_int <= '1';
elsif--(Mst_N_Slv = '0') and
and_reduce(Count((COUNT_WIDTH-1) downto (COUNT_WIDTH-COUNT_WIDTH+1))) ='1' then
if((CPOL xor CPHA) = '0') and rising_edge_sck_i = '1' then
SPIXfer_done_int <= '1';
elsif((CPOL xor CPHA) = '1') and falling_edge_sck_i = '1' then
SPIXfer_done_int <= '1';
end if;
end if;
end if;
end process TRANSFER_DONE_PROCESS;
end generate FIFO_ABSENT_GEN;
-- This is mux to choose the data register for SPI mode 00,11 and 01,10.
-- the below mux is applicable only for Master mode of SPI.
rx_shft_reg <=
rx_shft_reg_mode_0011
when ((CPOL = '0' and CPHA = '0') or (CPOL = '1' and CPHA = '1'))
else
rx_shft_reg_mode_0110
when ((CPOL = '0' and CPHA = '1') or (CPOL = '1' and CPHA = '0'))
else
(others=>'0');
-- RECEIVE_DATA_STROBE_PROCESS_OTHER_RATIO: the below process if for other
-------------------------------------------- SPI ratios of C_SCK_RATIO >2
-- -- It multiplexes the data stored
-- -- in internal registers in LSB and
-- -- non-LSB modes, in master as well as
-- -- in slave mode.
RECEIVE_DATA_STROBE_PROCESS_OTHER_RATIO: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(SPIXfer_done_int_pulse_d1 = '1') then
if (Mst_N_Slv = '1') then -- in master mode
if (LSB_first = '1') then
for i in 0 to (C_NUM_TRANSFER_BITS-1) loop
receive_Data_int(i) <= rx_shft_reg(C_NUM_TRANSFER_BITS-1-i);
end loop;
else
receive_Data_int <= rx_shft_reg;
end if;
elsif(Mst_N_Slv = '0') then -- in slave mode
if (LSB_first = '1') then
for i in 0 to (C_NUM_TRANSFER_BITS-1) loop
receive_Data_int(i) <= rx_shft_reg_s
(C_NUM_TRANSFER_BITS-1-i);
end loop;
else
receive_Data_int <= rx_shft_reg_s;
end if;
end if;
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS_OTHER_RATIO;
SPIXfer_done <= SPIXfer_done_int_pulse_d2;
SPIXfer_done_rd_tx_en <= transfer_start_pulse or
SPIXfer_done_int_pulse_d2 or
spisel_pulse;
tx_cntr_xfer_done <= transfer_start_pulse or SPIXfer_done_int_pulse_d2;
--------------------------------------------
end generate RX_DATA_GEN_OTHER_SCK_RATIOS;
-------------------------------------------------------------------------------
-- OTHER_RATIO_GENERATE : Logic to be used when C_SCK_RATIO is not equal to 2
-------------------------
OTHER_RATIO_GENERATE: if(C_SCK_RATIO /= 2) generate
--attribute IOB : string;
--attribute IOB of MOSI_I_REG : label is "true";
begin
-----
-------------------------------------------------------------------------------
-- OTHER_RATIO_MISO_I_REG_IOB_GEN: Push the IO1_I register in IOB
-- --------------
-- Only when the targeted family is 7-series or spartan 6
-- ir-respective of C_USE_STARTUP parameter
-- OTHER_RATIO_MISO_I_REG_IOB_GEN: if(C_SUB_FAMILY = "virtex7"
-- or
-- C_SUB_FAMILY = "kintex7"
-- or
-- C_SUB_FAMILY = "artix7"
-- --or
-- --C_SUB_FAMILY = "spartan6"
-- )
-- -- or
-- -- (
-- -- C_USE_STARTUP = 0
-- -- and
-- -- C_SUB_FAMILY = "virtex6"
-- -- )
-- generate
-- -- attribute IOB : string;
-- --attribute IOB of MISO_I_REG : label is "true";
-- -----
-- begin
-----
-- MISO_I_REG: component FD
-- generic map
-- (
-- INIT => '0'
-- )
-- port map
-- (
-- Q => miso_i_sync,
-- C => Bus2IP_Clk,
-- D => MISO_I
-- );
miso_i_sync <= MISO_I;
--end generate OTHER_RATIO_MISO_I_REG_IOB_GEN;
-----------------------------------------------------------------
-- OTHER_RATIO_MISO_I_REG_NO_IOB_GEN: If C_USE_STARTUP is used and family is virtex6, then
-- IO1_I is registered only, but it is not pushed in IOB.
-- this is due to STARTUP block in V6 is having DINSPI interface available for IO1_I.
-- OTHER_RATIO_MISO_I_REG_NO_IOB_GEN: if(C_USE_STARTUP = 1
-- and
-- C_SUB_FAMILY = "virtex6"
-- ) generate
-------
--begin
-------
--MISO_I_REG: component FD
--generic map
-- (
-- INIT => '0'
-- )
--port map
-- (
-- Q => miso_i_sync,
-- C => Bus2IP_Clk,
-- D => MISO_I
-- );
--end generate OTHER_RATIO_MISO_I_REG_NO_IOB_GEN;
-----------------------------------------------------------------
-- MOSI_I_REG: component FD
-- generic map
-- (
-- INIT => '0'
-- )
-- port map
-- (
-- Q => mosi_i_sync,
-- C => Bus2IP_Clk,
-- D => MOSI_I
-- );
mosi_i_sync <= MOSI_I;
------------------------------
LOOP_BACK_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Loop_mode = '0' or Soft_Reset_op = RESET_ACTIVE) then
serial_dout_int <= '0';
elsif(Loop_mode = '1') then
serial_dout_int <= Serial_Dout;
end if;
end if;
end process LOOP_BACK_PROCESS;
------------------------------
-- EXTERNAL_INPUT_OR_LOOP_PROCESS: The logic below provides MUXed input to
-- serial_din input.
EXTERNAL_INPUT_OR_LOOP_PROCESS: process(Loop_mode,
Mst_N_Slv,
mosi_i_sync,
miso_i_sync,
serial_dout_int
)is
-----
begin
-----
if(Mst_N_Slv = '1' )then
if(Loop_mode = '1')then
Serial_Din <= serial_dout_int;
else
Serial_Din <= miso_i_sync;
end if;
else
Serial_Din <= mosi_i_sync;
end if;
end process EXTERNAL_INPUT_OR_LOOP_PROCESS;
-------------------------------------------------------------------------------
-- RATIO_COUNT_PROCESS : Counter which counts from (C_SCK_RATIO/2)-1 down to 0
-- Used for counting the time to control SCK_O_reg generation
-- depending on C_SCK_RATIO
------------------------
RATIO_COUNT_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or (transfer_start = '0')) then
Ratio_Count <= CONV_STD_LOGIC_VECTOR(
((C_SCK_RATIO/2)-1),(spcl_log2(C_SCK_RATIO)-1));
else
Ratio_Count <= Ratio_Count - 1;
if (Ratio_Count = 0) then
Ratio_Count <= CONV_STD_LOGIC_VECTOR(
((C_SCK_RATIO/2)-1),(spcl_log2(C_SCK_RATIO)-1));
end if;
end if;
end if;
end process RATIO_COUNT_PROCESS;
-------------------------------------------------------------------------------
-- COUNT_TRIGGER_GEN_PROCESS : Generate a trigger whenever Ratio_Count reaches
-- zero
------------------------------
COUNT_TRIGGER_GEN_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or (transfer_start = '0')) then
Count_trigger <= '0';
elsif(Ratio_Count = 0) then
Count_trigger <= not Count_trigger;
end if;
end if;
end process COUNT_TRIGGER_GEN_PROCESS;
-------------------------------------------------------------------------------
-- COUNT_TRIGGER_1CLK_PROCESS : Delay cnt_trigger signal by 1 clock cycle
-------------------------------
COUNT_TRIGGER_1CLK_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or (transfer_start = '0')) then
Count_trigger_d1 <= '0';
else
Count_trigger_d1 <= Count_trigger;
end if;
end if;
end process COUNT_TRIGGER_1CLK_PROCESS;
-- generate a trigger pulse for rising edge as well as falling edge
Count_trigger_pulse <= (Count_trigger and (not(Count_trigger_d1))) or
((not(Count_trigger)) and Count_trigger_d1);
-------------------------------------------------------------------------------
-- SCK_CYCLE_COUNT_PROCESS : Counts number of trigger pulses provided. Used for
-- controlling the number of bits to be transfered
-- based on generic C_NUM_TRANSFER_BITS
----------------------------
SCK_CYCLE_COUNT_PROCESS: process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
Count <= (others => '0');
elsif (Mst_N_Slv = '1') then
if (SPIXfer_done_int = '1')or
(transfer_start = '0') or
(xfer_done_fifo_0 = '1') then
Count <= (others => '0');
elsif((Count_trigger_pulse = '1') and (Count(COUNT_WIDTH) = '0')) then
Count <= Count + 1;
-- coverage off
if (Count(COUNT_WIDTH) = '1') then
Count <= (others => '0');
end if;
-- coverage on
end if;
elsif (Mst_N_Slv = '0') then
if ((transfer_start = '0') or (SPISEL_sync = '1')or
(spixfer_done_int = '1')) then
Count <= (others => '0');
elsif (edge_sck_i = '1') then
Count <= Count + 1;
-- coverage off
if (Count(COUNT_WIDTH) = '1') then
Count <= (others => '0');
end if;
-- coverage on
end if;
end if;
end if;
end process SCK_CYCLE_COUNT_PROCESS;
-------------------------------------------------------------------------------
-- SCK_SET_RESET_PROCESS : Sync set/reset toggle flip flop controlled by
-- transfer_start signal
--------------------------
SCK_SET_RESET_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or
(Sync_Reset = '1') or
(Mst_N_Slv='0')
)then
sck_o_int <= '0';
elsif(Sync_Set = '1') then
sck_o_int <= '1';
elsif (transfer_start = '1') then
sck_o_int <= sck_o_int xor Count_trigger_pulse;
end if;
end if;
end process SCK_SET_RESET_PROCESS;
------------------------------------
-- DELAY_CLK: Delay the internal clock for a cycle to generate internal enable
-- -- signal for data register.
-------------
DELAY_CLK: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (Soft_Reset_op = RESET_ACTIVE)then
sck_d1 <= '0';
sck_d2 <= '0';
else
sck_d1 <= sck_o_int;
sck_d2 <= sck_d1;
end if;
end if;
end process DELAY_CLK;
------------------------------------
-- Rising egde pulse for CPHA-CPOL = 00/11 mode
sck_rising_edge <= not(sck_d2) and sck_d1;
-- CAPT_RX_FE_MODE_00_11: The below logic is the date registery process for
------------------------- SPI CPHA-CPOL modes of 00 and 11.
CAPT_RX_FE_MODE_00_11 : process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (Soft_Reset_op = RESET_ACTIVE)then
rx_shft_reg_mode_0011 <= (others => '0');
elsif((sck_rising_edge = '1') and (transfer_start='1')) then
rx_shft_reg_mode_0011<= rx_shft_reg_mode_0011
(1 to (C_NUM_TRANSFER_BITS-1)) & Serial_Din;
end if;
end if;
end process CAPT_RX_FE_MODE_00_11;
--
sck_fe1 <= (not sck_d1) and sck_d2;
-- CAPT_RX_FE_MODE_01_10 : The below logic is the date registery process for
------------------------- SPI CPHA-CPOL modes of 01 and 10.
CAPT_RX_FE_MODE_01_10 : process(Bus2IP_Clk)
begin
--if rising_edge(Bus2IP_Clk) then
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (Soft_Reset_op = RESET_ACTIVE)then
rx_shft_reg_mode_0110 <= (others => '0');
elsif ((sck_fe1 = '1') and (transfer_start = '1')) then
rx_shft_reg_mode_0110 <= rx_shft_reg_mode_0110
(1 to (C_NUM_TRANSFER_BITS-1)) & Serial_Din;
end if;
end if;
end process CAPT_RX_FE_MODE_01_10;
-------------------------------------------------------------------------------
-- CAPTURE_AND_SHIFT_PROCESS : This logic essentially controls the entire
-- capture and shift operation for serial data
------------------------------
CAPTURE_AND_SHIFT_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
Shift_Reg(0) <= '0';
Shift_Reg(1) <= '1';
Shift_Reg(2 to C_NUM_TRANSFER_BITS -1) <= (others => '0');
Serial_Dout <= '1';
elsif((Mst_N_Slv = '1')) then -- and (not(Count(COUNT_WIDTH) = '1'))) then
--if(Loading_SR_Reg_int = '1') then
if(transfer_start_pulse = '1' or SPIXfer_done_int_d1 = '1')then
if(LSB_first = '1') then
for i in 0 to C_NUM_TRANSFER_BITS-1 loop
Shift_Reg(i) <= Transmit_Data
(C_NUM_TRANSFER_BITS-1-i);
end loop;
Serial_Dout <= Transmit_Data(C_NUM_TRANSFER_BITS-1);
else
Shift_Reg <= Transmit_Data;
Serial_Dout <= Transmit_Data(0);
end if;
-- Capture Data on even Count
elsif(--(transfer_start = '1') and
(Count(0) = '0') ) then
Serial_Dout <= Shift_Reg(0);
-- Shift Data on odd Count
elsif(--(transfer_start = '1') and
(Count(0) = '1') and
(Count_trigger_pulse = '1')) then
Shift_Reg <= Shift_Reg
(1 to C_NUM_TRANSFER_BITS -1) & Serial_Din;
end if;
-- below mode is slave mode logic for SPI
elsif(Mst_N_Slv = '0') then
--if((Loading_SR_Reg_int = '1') or (spisel_pulse = '1')) then
--if(transfer_start_pulse = '1' or SPIXfer_done_int_d1 = '1')then
if(SR_5_Tx_Empty_pulse = '1' or SPIXfer_done_int = '1')then
if(LSB_first = '1') then
for i in 0 to C_NUM_TRANSFER_BITS-1 loop
Shift_Reg(i) <= Transmit_Data
(C_NUM_TRANSFER_BITS-1-i);
end loop;
Serial_Dout <= Transmit_Data(C_NUM_TRANSFER_BITS-1);
else
Shift_Reg <= Transmit_Data;
Serial_Dout <= Transmit_Data(0);
end if;
elsif (transfer_start = '1') then
if((CPOL = '0' and CPHA = '0') or
(CPOL = '1' and CPHA = '1')) then
if(rising_edge_sck_i = '1') then
rx_shft_reg_s <= rx_shft_reg_s(1 to
C_NUM_TRANSFER_BITS -1) & Serial_Din;
Shift_Reg <= Shift_Reg(1 to
C_NUM_TRANSFER_BITS -1) & Serial_Din;
--elsif(falling_edge_sck_i = '1') then
--elsif(rising_edge_sck_i_d1 = '1')then
-- Serial_Dout <= Shift_Reg(0);
end if;
Serial_Dout <= Shift_Reg(0);
elsif((CPOL = '0' and CPHA = '1') or
(CPOL = '1' and CPHA = '0')) then
--Serial_Dout <= Shift_Reg(0);
if(falling_edge_sck_i = '1') then
rx_shft_reg_s <= rx_shft_reg_s(1 to
C_NUM_TRANSFER_BITS -1) & Serial_Din;
Shift_Reg <= Shift_Reg(1 to
C_NUM_TRANSFER_BITS -1) & Serial_Din;
--elsif(rising_edge_sck_i = '1') then
--elsif(falling_edge_sck_i_d1 = '1')then
-- Serial_Dout <= Shift_Reg(0);
end if;
Serial_Dout <= Shift_Reg(0);
end if;
end if;
end if;
end if;
end process CAPTURE_AND_SHIFT_PROCESS;
-----
end generate OTHER_RATIO_GENERATE;
-------------------------------------------------------------------------------
-- RATIO_OF_2_GENERATE : Logic to be used when C_SCK_RATIO is equal to 2
------------------------
RATIO_OF_2_GENERATE: if(C_SCK_RATIO = 2) generate
--------------------
begin
-----
-------------------------------------------------------------------------------
-- SCK_CYCLE_COUNT_PROCESS : Counts number of trigger pulses provided. Used for
-- controlling the number of bits to be transfered
-- based on generic C_NUM_TRANSFER_BITS
----------------------------
SCK_CYCLE_COUNT_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or
(transfer_start = '0') or
(SPIXfer_done_int = '1') or
(Mst_N_Slv = '0')) then
Count <= (others => '0');
--elsif (Count(COUNT_WIDTH) = '0') then
-- Count <= Count + 1;
elsif(Count(COUNT_WIDTH) = '0')then
if(CPHA = '0')then
if(CPOL = '0' and transfer_start_d1 = '1')then -- cpol = cpha = 00
Count <= Count + 1;
elsif(transfer_start_d1 = '1') then -- cpol = cpha = 10
Count <= Count + 1;
end if;
else
if(CPOL = '1' and transfer_start_d1 = '1')then -- cpol = cpha = 11
Count <= Count + 1;
elsif(transfer_start_d1 = '1') then-- cpol = cpha = 10
Count <= Count + 1;
end if;
end if;
end if;
end if;
end process SCK_CYCLE_COUNT_PROCESS;
-------------------------------------------------------------------------------
-- SCK_SET_RESET_PROCESS : Sync set/reset toggle flip flop controlled by
-- transfer_start signal
--------------------------
SCK_SET_RESET_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or (Sync_Reset = '1')) then
sck_o_int <= '0';
elsif(Sync_Set = '1') then
sck_o_int <= '1';
elsif (transfer_start = '1') then
sck_o_int <= (not sck_o_int);-- xor Count(COUNT_WIDTH);
end if;
end if;
end process SCK_SET_RESET_PROCESS;
-- CAPT_RX_FE_MODE_00_11: The below logic is to capture data for SPI mode of
--------------------------- 00 and 11.
-- Generate a falling edge pulse from the serial clock. Use this to
-- capture the incoming serial data into a shift register.
-- CAPT_RX_FE_MODE_00_11 : process(Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'event and Bus2IP_Clk = '0') then
-- sck_d1 <= sck_o_int;
-- sck_d2 <= sck_d1;
-- -- if (sck_rising_edge = '1') then
-- if (sck_d1 = '1') then
-- rx_shft_reg_mode_0011 <= rx_shft_reg_mode_0011
-- (1 to (C_NUM_TRANSFER_BITS-1)) & MISO_I;
-- end if;
-- end if;
-- end process CAPT_RX_FE_MODE_00_11;
CAPT_RX_FE_MODE_00_11 : process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
sck_d1 <= sck_o_int;
sck_d2 <= sck_d1;
-- sck_d3 <= sck_d2;
-- if (sck_rising_edge = '1') then
if (sck_d2 = '0') then
rx_shft_reg_mode_0011 <= rx_shft_reg_mode_0011
(1 to (C_NUM_TRANSFER_BITS-1)) & MISO_I;
end if;
end if;
end process CAPT_RX_FE_MODE_00_11;
-- Falling egde pulse
sck_rising_edge <= sck_d2 and not sck_d1;
--
-- CAPT_RX_FE_MODE_01_10: the below logic captures data in SPI 01 or 10 mode.
---------------------------
CAPT_RX_FE_MODE_01_10: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
sck_d11 <= sck_o_in;
sck_d21 <= sck_d11;
if(CPOL = '1' and CPHA = '0') then
if ((sck_d1 = '1') and (transfer_start = '1')) then
rx_shft_reg_mode_0110 <= rx_shft_reg_mode_0110
(1 to (C_NUM_TRANSFER_BITS-1)) & MISO_I;
end if;
elsif((CPOL = '0') and (CPHA = '1')) then
if ((sck_fe1 = '0') and (transfer_start = '1')) then
rx_shft_reg_mode_0110 <= rx_shft_reg_mode_0110
(1 to (C_NUM_TRANSFER_BITS-1)) & MISO_I;
end if;
end if;
end if;
end process CAPT_RX_FE_MODE_01_10;
sck_fe1 <= (not sck_d11) and sck_d21;
-------------------------------------------------------------------------------
-- CAPTURE_AND_SHIFT_PROCESS : This logic essentially controls the entire
-- capture and shift operation for serial data in
------------------------------ master SPI mode only
CAPTURE_AND_SHIFT_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
Shift_Reg(0) <= '0';
Shift_Reg(1) <= '1';
Shift_Reg(2 to C_NUM_TRANSFER_BITS -1) <= (others => '0');
Serial_Dout <= '1';
elsif(Mst_N_Slv = '1') then
--if(Loading_SR_Reg_int = '1') then
if(transfer_start_pulse = '1' or SPIXfer_done_int_d1 = '1') then
if(LSB_first = '1') then
for i in 0 to C_NUM_TRANSFER_BITS-1 loop
Shift_Reg(i) <= Transmit_Data
(C_NUM_TRANSFER_BITS-1-i);
end loop;
Serial_Dout <= Transmit_Data(C_NUM_TRANSFER_BITS-1);
else
Shift_Reg <= Transmit_Data;
Serial_Dout <= Transmit_Data(0);
end if;
elsif(--(transfer_start = '1') and
(Count(0) = '0') -- and
--(Count(COUNT_WIDTH) = '0')
) then -- Shift Data on even
Serial_Dout <= Shift_Reg(0);
elsif(--(transfer_start = '1') and
(Count(0) = '1')-- and
--(Count(COUNT_WIDTH) = '0')
) then -- Capture Data on odd
if(Loop_mode = '1') then -- Loop mode
Shift_Reg <= Shift_Reg(1 to
C_NUM_TRANSFER_BITS -1) & Serial_Dout;
else
Shift_Reg <= Shift_Reg(1 to
C_NUM_TRANSFER_BITS -1) & MISO_I;
end if;
end if;
elsif(Mst_N_Slv = '0') then
-- Added to have consistent default value after reset
--if((Loading_SR_Reg_int = '1') or (spisel_pulse = '1')) then
if(spisel_pulse = '1' or SPIXfer_done_int_d1 = '1') then
Shift_Reg <= (others => '0');
Serial_Dout <= '0';
end if;
end if;
end if;
end process CAPTURE_AND_SHIFT_PROCESS;
-----
end generate RATIO_OF_2_GENERATE;
-------------------------------------------------------------------------------
-- SCK_SET_GEN_PROCESS : Generate SET control for SCK_O_reg
------------------------
SCK_SET_GEN_PROCESS: process(CPOL,CPHA,transfer_start_pulse,
SPIXfer_done_int,
Mst_Trans_inhibit_pulse
)
begin
-- if(transfer_start_pulse = '1') then
--if(Mst_Trans_inhibit_pulse = '1' or SPIXfer_done_int = '1') then
if(transfer_start_pulse = '1' or SPIXfer_done_int = '1') then
Sync_Set <= (CPOL xor CPHA);
else
Sync_Set <= '0';
end if;
end process SCK_SET_GEN_PROCESS;
-------------------------------------------------------------------------------
-- SCK_RESET_GEN_PROCESS : Generate SET control for SCK_O_reg
--------------------------
SCK_RESET_GEN_PROCESS: process(CPOL,
CPHA,
transfer_start_pulse,
SPIXfer_done_int,
Mst_Trans_inhibit_pulse)
begin
--if(transfer_start_pulse = '1') then
--if(Mst_Trans_inhibit_pulse = '1' or SPIXfer_done_int = '1') then
if(transfer_start_pulse = '1' or SPIXfer_done_int = '1') then
Sync_Reset <= not(CPOL xor CPHA);
else
Sync_Reset <= '0';
end if;
end process SCK_RESET_GEN_PROCESS;
-------------------------------------------------------------------------------
-- RATIO_NOT_EQUAL_4_GENERATE : Logic to be used when C_SCK_RATIO is not equal
-- to 4
-------------------------------
RATIO_NOT_EQUAL_4_GENERATE: if(C_SCK_RATIO /= 4) generate
begin
-----
-------------------------------------------------------------------------------
-- SCK_O_SELECT_PROCESS : Select the idle state (CPOL bit) when not transfering
-- data else select the clock for slave device
-------------------------
SCK_O_NQ_4_SELECT_PROCESS: process(sck_o_int,
CPOL,
transfer_start,
transfer_start_d1,
Count(COUNT_WIDTH),
xfer_done_fifo_0
)is
begin
if((transfer_start = '1') and
(transfer_start_d1 = '1') and
(Count(COUNT_WIDTH) = '0')and
(xfer_done_fifo_0 = '0')
) then
sck_o_in <= sck_o_int;
else
sck_o_in <= CPOL;
end if;
end process SCK_O_NQ_4_SELECT_PROCESS;
---------------------------------
SCK_O_NQ_4_NO_STARTUP_USED: if (C_USE_STARTUP = 0) generate
----------------
attribute IOB : string;
attribute IOB of SCK_O_NE_4_FDRE_INST : label is "true";
signal slave_mode : std_logic;
----------------
begin
-----
slave_mode <= not (Mst_N_Slv);
-- FDRE: Single Data Rate D Flip-Flop with Synchronous Reset and
-- Clock Enable (posedge clk).
SCK_O_NE_4_FDRE_INST : component FDRE
generic map (
INIT => '0'
) -- Initial value of register (0 or 1)
port map
(
Q => SCK_O_reg, -- Data output
C => Bus2IP_Clk, -- Clock input
CE => '1', -- Clock enable input
R => slave_mode, -- Synchronous reset input
D => sck_o_in -- Data input
);
end generate SCK_O_NQ_4_NO_STARTUP_USED;
-----------------------------
SCK_O_NQ_4_STARTUP_USED: if (C_USE_STARTUP = 1) generate
-------------
begin
-----
---------------------------------------------------------------------------
-- SCK_O_FINAL_PROCESS : Register the final SCK_O_reg
------------------------
SCK_O_NQ_4_FINAL_PROCESS: process(Bus2IP_Clk)
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
--If Soft_Reset_op or slave Mode.Prevents SCK_O_reg to be generated in slave
if((Soft_Reset_op = RESET_ACTIVE) or
(Mst_N_Slv = '0')
) then
SCK_O_reg <= '0';
else
SCK_O_reg <= sck_o_in;
end if;
end if;
end process SCK_O_NQ_4_FINAL_PROCESS;
-------------------------------------
end generate SCK_O_NQ_4_STARTUP_USED;
-------------------------------------
end generate RATIO_NOT_EQUAL_4_GENERATE;
-------------------------------------------------------------------------------
-- RATIO_OF_4_GENERATE : Logic to be used when C_SCK_RATIO is equal to 4
------------------------
RATIO_OF_4_GENERATE: if(C_SCK_RATIO = 4) generate
begin
-----
-------------------------------------------------------------------------------
-- SCK_O_FINAL_PROCESS : Select the idle state (CPOL bit) when not transfering
-- data else select the clock for slave device
------------------------
-- A work around to reduce one clock cycle for sck_o generation. This would
-- allow for proper shifting of data bits into the slave device.
-- Removing the final stage F/F. Disadvantage of not registering final output
-------------------------------------------------------------------------------
SCK_O_EQ_4_FINAL_PROCESS: process(Mst_N_Slv,
sck_o_int,
CPOL,
transfer_start,
transfer_start_d1,
Count(COUNT_WIDTH),
xfer_done_fifo_0
)is
-----
begin
-----
if((Mst_N_Slv = '1') and
(transfer_start = '1') and
(transfer_start_d1 = '1') and
(Count(COUNT_WIDTH) = '0')and
(xfer_done_fifo_0 = '0')
) then
SCK_O_1 <= sck_o_int;
else
SCK_O_1 <= CPOL and Mst_N_Slv;
end if;
end process SCK_O_EQ_4_FINAL_PROCESS;
-------------------------------------
SCK_O_EQ_4_NO_STARTUP_USED: if (C_USE_STARTUP = 0) generate
----------------
attribute IOB : string;
attribute IOB of SCK_O_EQ_4_FDRE_INST : label is "true";
signal slave_mode : std_logic;
----------------
begin
-----
slave_mode <= not (Mst_N_Slv);
-- FDRE: Single Data Rate D Flip-Flop with Synchronous Reset and
-- Clock Enable (posedge clk).
SCK_O_EQ_4_FDRE_INST : component FDRE
generic map (
INIT => '0'
) -- Initial value of register (0 or 1)
port map
(
Q => SCK_O_reg, -- Data output
C => Bus2IP_Clk, -- Clock input
CE => '1', -- Clock enable input
R => slave_mode, -- Synchronous reset input
D => SCK_O_1 -- Data input
);
end generate SCK_O_EQ_4_NO_STARTUP_USED;
-----------------------------
SCK_O_EQ_4_STARTUP_USED: if (C_USE_STARTUP = 1) generate
-------------
begin
-----
----------------------------------------------------------------------------
-- SCK_RATIO_4_REG_PROCESS : The SCK is registered in SCK RATIO = 4 mode
----------------------------------------------------------------------------
SCK_O_EQ_4_REG_PROCESS: process(Bus2IP_Clk)
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
-- If Soft_Reset_op or slave Mode. Prevents SCK_O_reg to be generated in slave
if((Soft_Reset_op = RESET_ACTIVE) or
(Mst_N_Slv = '0')
) then
SCK_O_reg <= '0';
else
SCK_O_reg <= SCK_O_1;
end if;
end if;
end process SCK_O_EQ_4_REG_PROCESS;
-----------------------------------
end generate SCK_O_EQ_4_STARTUP_USED;
-------------------------------------
end generate RATIO_OF_4_GENERATE;
-------------------------------------------------------------------------------
-- LOADING_FIRST_ELEMENT_PROCESS : Combinatorial process to generate flag
-- when loading first data element in shift
-- register from transmit register/fifo
----------------------------------
LOADING_FIRST_ELEMENT_PROCESS: process(Soft_Reset_op,
SPI_En,Mst_N_Slv,
SS_Asserted,
SS_Asserted_1dly,
SR_3_MODF,
transfer_start_pulse)is
begin
if(Soft_Reset_op = RESET_ACTIVE) then
Loading_SR_Reg_int <= '0'; --Clear flag
elsif(SPI_En = '1' and --Enabled
(
((Mst_N_Slv = '1') and --Master configuration
(SS_Asserted = '1') and
(SS_Asserted_1dly = '0') and
(SR_3_MODF = '0')
) or
((Mst_N_Slv = '0') and --Slave configuration
((transfer_start_pulse = '1'))
)
)
)then
Loading_SR_Reg_int <= '1'; --Set flag
else
Loading_SR_Reg_int <= '0'; --Clear flag
end if;
end process LOADING_FIRST_ELEMENT_PROCESS;
-------------------------------------------------------------------------------
-- SELECT_OUT_PROCESS : This process sets SS active-low, one-hot encoded select
-- bit. Changing SS is premitted during a transfer by
-- hardware, but is to be prevented by software. In Auto
-- mode SS_O reflects value of Slave_Select_Reg only
-- when transfer is in progress, otherwise is SS_O is held
-- high
-----------------------
SELECT_OUT_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
SS_O <= (others => '1');
SS_Asserted <= '0';
SS_Asserted_1dly <= '0';
elsif(transfer_start = '0') or (xfer_done_fifo_0 = '1') then -- Tranfer not in progress
if(Manual_SS_mode = '0') then -- Auto SS assert
SS_O <= (others => '1');
else
for i in C_NUM_SS_BITS-1 downto 0 loop
SS_O(i) <= Slave_Select_Reg(C_NUM_SS_BITS-1-i);
end loop;
end if;
SS_Asserted <= '0';
SS_Asserted_1dly <= '0';
else
for i in C_NUM_SS_BITS-1 downto 0 loop
SS_O(i) <= Slave_Select_Reg(C_NUM_SS_BITS-1-i);
end loop;
SS_Asserted <= '1';
SS_Asserted_1dly <= SS_Asserted;
end if;
end if;
end process SELECT_OUT_PROCESS;
-------------------------------------------------------------------------------
-- MODF_STROBE_PROCESS : Strobe MODF signal when master is addressed as slave
------------------------
MODF_STROBE_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or (SPISEL_sync = '1')) then
MODF_strobe <= '0';
MODF_strobe_int <= '0';
Allow_MODF_Strobe <= '1';
elsif((Mst_N_Slv = '1') and --In Master mode
(SPISEL_sync = '0') and (Allow_MODF_Strobe = '1')) then
MODF_strobe <= '1';
MODF_strobe_int <= '1';
Allow_MODF_Strobe <= '0';
else
MODF_strobe <= '0';
MODF_strobe_int <= '0';
end if;
end if;
end process MODF_STROBE_PROCESS;
-------------------------------------------------------------------------------
-- SLAVE_MODF_STROBE_PROCESS : Strobe MODF signal when slave is addressed
-- but not enabled.
------------------------------
SLAVE_MODF_STROBE_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or (SPISEL_sync = '1')) then
Slave_MODF_strobe <= '0';
Allow_Slave_MODF_Strobe<= '1';
elsif((Mst_N_Slv = '0') and --In Slave mode
(SPI_En = '0') and --but not enabled
(SPISEL_sync = '0') and
(Allow_Slave_MODF_Strobe = '1')
) then
Slave_MODF_strobe <= '1';
Allow_Slave_MODF_Strobe <= '0';
else
Slave_MODF_strobe <= '0';
end if;
end if;
end process SLAVE_MODF_STROBE_PROCESS;
---------------------xxx------------------------------------------------------
end imp;
| gpl-2.0 | b00a7177fe07c600b2a4840c77e30119 | 0.435561 | 4.113963 | false | false | false | false |
dpolad/dlx | DLX_synth/a.i.a-ALU.vhd | 1 | 6,583 | -- real_alu.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.myTypes.all;
entity real_alu is
generic (
DATA_SIZE : integer := 32);
port (
IN1 : in std_logic_vector(DATA_SIZE - 1 downto 0);
IN2 : in std_logic_vector(DATA_SIZE - 1 downto 0);
-- OP : in AluOp;
ALUW_i : in std_logic_vector(12 downto 0);
DOUT : out std_logic_vector(DATA_SIZE - 1 downto 0);
stall_o : out std_logic;
Clock : in std_logic;
Reset : in std_logic
);
end real_alu;
architecture Bhe of real_alu is
component simple_booth_add_ext
generic (N : integer);
port(
Clock : in std_logic;
Reset : in std_logic;
sign : in std_logic;
enable : in std_logic;
valid : out std_logic;
A : in std_logic_vector (N-1 downto 0);
B : in std_logic_vector (N-1 downto 0);
A_to_add : out std_logic_vector (2*N-1 downto 0);
B_to_add : out std_logic_vector (2*N-1 downto 0);
final_out : out std_logic_vector (2*N-1 downto 0);
sign_to_add : out std_logic;
ACC_from_add : in std_logic_vector (2*N-1 downto 0)
);
end component;
component p4add
generic (
N : integer := 32;
logN : integer := 5);
Port (
A : in std_logic_vector(N-1 downto 0);
B : in std_logic_vector(N-1 downto 0);
Cin : in std_logic;
sign : In std_logic;
S : out std_logic_vector(N-1 downto 0);
Cout : out std_logic);
end component;
component comparator
generic (M : integer := 32);
port (
C : in std_logic; -- carry out
V : in std_logic; -- overflow
SUM : in std_logic_vector(M-1 downto 0);
sel : in std_logic_vector(2 downto 0); -- selection
sign : in std_logic; -- 0 unsigned / signed 1
S : out std_logic
);
end component;
component bhe_comparator is
generic (M : integer := 32);
port (
A : in std_logic_vector(M-1 downto 0); -- carry out
B : in std_logic_vector(M-1 downto 0);
sign : in std_logic;
sel : in std_logic_vector(2 downto 0); -- selection
S : out std_logic
);
end component;
component shifter
port(
A : in std_logic_vector(31 downto 0);
B : in std_logic_vector(4 downto 0);
LOGIC_ARITH : in std_logic; -- 1 = logic, 0 = arith
LEFT_RIGHT : in std_logic; -- 1 = left, 0 = right
OUTPUT : out std_logic_vector(31 downto 0)
);
end component;
component logic_unit
generic ( SIZE : integer := 32 );
port (
IN1 : in std_logic_vector(SIZE - 1 downto 0);
IN2 : in std_logic_vector(SIZE - 1 downto 0);
CTRL : in std_logic_vector(1 downto 0); -- need to do only and, or and xor
OUT1 : out std_logic_vector(SIZE - 1 downto 0)
);
end component;
signal sign_to_booth : std_logic;
signal enable_to_booth : std_logic;
signal valid_from_booth : std_logic;
signal A_booth_to_add : std_logic_vector(DATA_SIZE-1 downto 0);
signal B_booth_to_add : std_logic_vector(DATA_SIZE-1 downto 0);
signal sign_booth_to_add : std_logic;
signal sum_out : std_logic_vector(DATA_SIZE-1 downto 0);
signal comp_out : std_logic;
signal shift_out : std_logic_vector(DATA_SIZE-1 downto 0);
signal mult_out : std_logic_vector(DATA_SIZE-1 downto 0);
signal mux_A : std_logic_vector(DATA_SIZE-1 downto 0);
signal mux_B : std_logic_vector(DATA_SIZE-1 downto 0);
signal mux_sign : std_logic;
signal carry_from_adder : std_logic;
signal overflow : std_logic;
signal sign_bit_to_comp : std_logic;
signal out_mux_sel : std_logic_vector(2 downto 0);
signal comp_sel : std_logic_vector(2 downto 0);
signal sign_to_adder : std_logic;
signal left_right : std_logic; -- 1 = logic, 0 = arith
signal logic_arith : std_logic; -- 1 = left, 0 = right
signal lu_ctrl : std_logic_vector(1 downto 0);
signal lu_out : std_logic_vector(DATA_SIZE-1 downto 0);
signal ALU_WORD_TEST :std_logic_vector(12 downto 0);
begin
-- debug signal
ALU_WORD_TEST <= out_mux_sel&left_right&logic_arith&sign_to_adder&lu_ctrl&comp_sel&enable_to_booth&sign_to_booth;
-- signals from decode aluOP
out_mux_sel <= ALUW_i(12 downto 10);
left_right <= ALUW_i(9);
logic_arith <= ALUW_i(8);
sign_to_adder <= ALUW_i(7);
lu_ctrl <= ALUW_i(6 downto 5);
comp_sel <= ALUW_i(4 downto 2);
enable_to_booth <= ALUW_i(1);
sign_to_booth <= ALUW_i(0);
--muxes to adder
mux_A <= IN1 when enable_to_booth = '0' else
A_booth_to_add when enable_to_booth = '1' else
(others => 'X');
mux_B <= IN2 when enable_to_booth = '0' else
B_booth_to_add when enable_to_booth = '1' else
(others => 'X');
mux_sign <= sign_to_adder when enable_to_booth = '0' else
sign_booth_to_add when enable_to_booth = '1' else
'X';
--sign bit calculation
sign_bit_to_comp <= IN1(DATA_SIZE-1) xor IN2(DATA_SIZE-1);
MULT: simple_booth_add_ext
generic map ( N => DATA_SIZE/2)
port Map(
Clock => Clock,
Reset => Reset,
sign => sign_to_booth,
enable => enable_to_booth,
valid => valid_from_booth,
A => IN1(DATA_SIZE/2-1 downto 0),
B => IN2(DATA_SIZE/2-1 downto 0),
A_to_add => A_booth_to_add,
B_to_add => B_booth_to_add,
final_out => mult_out,
sign_to_add => sign_booth_to_add,
ACC_from_add => sum_out
);
ADDER: p4add
generic map (
N => DATA_SIZE,
logN => 5
)
port map (
A => mux_A,
B => mux_B,
Cin => '0',
sign => mux_sign,
S => sum_out,
Cout => carry_from_adder
);
COMP: comparator
generic map ( M => DATA_SIZE)
port map (
C => carry_from_adder,
V => overflow,
SUM => sum_out,
sel => comp_sel,
sign => sign_to_booth,
S => comp_out
);
-- NO MORE USED, IMPROVES SPEED, INCREASES AREA
-- BHE_COMP: bhe_comparator
-- generic map ( M => DATA_SIZE)
-- port map (
-- A => IN1,
-- B => IN2,
-- sel => comp_sel,
-- sign => sign_to_booth,
-- S => comp_out
-- );
SHIFT: shifter
port map(
A => IN1,
B => IN2(4 downto 0),
LOGIC_ARITH => logic_arith,
LEFT_RIGHT => left_right,
OUTPUT => shift_out
);
LU: logic_unit
generic map( SIZE => DATA_SIZE)
port map(
IN1 => IN1,
IN2 => IN2,
CTRL => lu_ctrl,
OUT1 => lu_out
);
-- overflow bit calculation
overflow <= (IN2(DATA_SIZE-1) xnor sum_out(DATA_SIZE-1)) and (IN1(DATA_SIZE-1) xor IN2(DATA_SIZE-1));
-- stalling while booth is in process
stall_o <= enable_to_booth and not(valid_from_booth);
--output mux
DOUT <= sum_out when out_mux_sel = "000" else
lu_out when out_mux_sel = "001" else
shift_out when out_mux_sel = "010" else
"000"&X"0000000"&comp_out when out_mux_sel = "011" else
IN2 when out_mux_sel = "100" else
mult_out when out_mux_sel = "101" else
(others => 'X');
end bhe;
| bsd-2-clause | 086d45dded3061853fb93af475e3c262 | 0.619171 | 2.444486 | false | false | false | false |
manosaloscables/vhdl | circuitos_secuenciales/sram_doble_puerto/sram_dp_tb.vhd | 1 | 3,016 | -- **********************************************
-- * Banco de pruebas para SRAM de doble puerto *
-- **********************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sram_dp_tb is
generic(
DIR_ANCHO : integer:=2;
DATOS_ANCHO: integer:=8
);
end sram_dp_tb;
architecture arq_bp of sram_dp_tb is
constant T: time := 20 ns; -- Período del Reloj
signal clk, we: std_logic;
signal w_dir, r_dir: std_logic_vector(DIR_ANCHO-1 downto 0);
signal d, q: std_logic_vector(DATOS_ANCHO-1 downto 0);
begin
-- =============
-- Instanciación
-- =============
unidad_sram_dp: entity work.sram_dp(arq_dir_reg)
generic map(DIR_ANCHO => DIR_ANCHO,
DATOS_ANCHO => DATOS_ANCHO)
port map(
clk => clk,
we => we,
w_dir => w_dir,
r_dir => r_dir,
d => d,
q => q
);
-- =====
-- Reloj
-- =====
process begin
clk <= '0';
wait for T/2;
clk <= '1';
wait for T/2;
end process;
-- ===============
-- Otros estímulos
-- ===============
process begin
-- Inicialización de la primera dirección en 0
we <= '1'; -- Activar escritura
w_dir <= (others => '0');
r_dir <= (others => '0');
d <= (others => '0');
wait until falling_edge(clk);
-- Escribir en la última dirección (la escritura áun está activada)
w_dir <= (others => '1');
d <= (others => '1'); -- Escribir el valor máximo
wait until falling_edge(clk);
-- Escribir en la tercera dirección (la escritura áun está activada)
w_dir <= "10";
d <= (others => '0');
wait until falling_edge(clk);
-- Leer la última dirección
we <= '0'; -- Desactivar escritura
r_dir <= (others => '1');
d <= "00001111"; -- no debería almacenarse en la dirección w_dir anterior
wait until falling_edge(clk);
-- Leer la tercera dirección
-- (la escritura no está activada)
r_dir <= "10";
wait until falling_edge(clk);
-- Sobrescribir y leer la memoria completa
for i in 0 to 2**DIR_ANCHO-1 loop
we <= '1'; -- Escritura activada
w_dir <= std_logic_vector(to_unsigned(i, DIR_ANCHO));
d <= std_logic_vector(to_unsigned(i+8, DATOS_ANCHO));
r_dir <= std_logic_vector(to_unsigned(i, DIR_ANCHO));
wait until falling_edge(clk);
end loop;
-- Leer toda la memoria
for i in 0 to 2**DIR_ANCHO-1 loop
we <= '0'; -- Escritura desactivada
r_dir <= std_logic_vector(to_unsigned(i, DIR_ANCHO));
-- En w_dir no debería almacenarse d
w_dir <= std_logic_vector(to_unsigned(i, DIR_ANCHO));
d <= std_logic_vector(to_unsigned(i+4, DATOS_ANCHO));
wait until falling_edge(clk);
end loop;
-- ===================
-- Terminar simulación
-- ===================
assert false
report "Simulación Completada"
severity failure;
end process;
end arq_bp;
| gpl-3.0 | 5a2954a4623d17ca8bbfaa3dc1a8e9cb | 0.5334 | 3.348993 | false | false | false | false |
manosaloscables/vhdl | vga/vga_sinc_tb.vhd | 1 | 1,652 | -- ***********************************************************
-- * Banco de prueba para el circuito de sincronización VGA *
-- ***********************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity vga_bp is
end vga_bp;
architecture arq_bp of vga_bp is
constant T: time := 20 ns; -- Periodo del Reloj
signal clk, rst: std_logic; -- Entradas
signal px_tick, video_on, hsinc, vsinc: std_logic; -- Salidas
signal px_x, px_y: std_logic_vector(9 downto 0);
signal sw, rgb, rgb_reg: std_logic_vector(2 downto 0); -- Estímulos
begin
-- Instanciar un circuito de sincronización VGA
unidad_vga_sinc: entity work.vga_sinc(arq)
port map(
clk => clk,
rst => rst,
px_tick => px_tick,
video_on => video_on,
pixel_x => px_x,
pixel_y => px_y,
hsinc => hsinc,
vsinc => vsinc
);
-- Búfer RGB
process(clk, rst) begin
if rst = '0' then
rgb_reg <= (others => '0');
elsif(rising_edge(clk)) then
rgb_reg <= sw;
end if;
end process;
rgb <= rgb_reg when video_on = '1' else "000";
-- Reloj
process begin
clk <= '0';
wait for T/2;
clk <= '1';
wait for T/2;
end process;
-- Reinicio
rst <= '0', '1' after T/2;
-- Otros estímulos
process begin
sw <= "001";
for i in 1 to 1000000 loop
wait until falling_edge(clk);
end loop;
-- Terminar simulación
assert false
report "Simulación Completada"
severity failure;
end process;
end arq_bp;
| gpl-3.0 | 6f4c5ce8114ce919a465f2bf13cb2e57 | 0.520365 | 3.405797 | false | false | false | false |
achan1989/SlowWorm | sim/control/instructions/imm_val_tb.vhd | 1 | 3,416 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 07.09.2016 21:23:57
-- Design Name:
-- Module Name: imm_val_tb - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library SlowWorm;
use SlowWorm.SlowWorm.ALL;
entity imm_val_tb is
end imm_val_tb;
architecture Behavioral of imm_val_tb is
signal clk : std_ulogic;
signal inst_mem_data : data_t;
signal inst_mem_addr : addr_t;
signal data_mem_we : std_ulogic;
signal rstack_data_write : data_t;
signal rstack_push : std_ulogic;
signal rstack_pop : std_ulogic;
signal dstack_data_write : data_t;
signal dstack_push : std_ulogic;
signal dstack_pop : std_ulogic;
constant ClockPeriod : TIME := 50 ns;
constant DATA_STACK : std_ulogic := '0';
constant RETURN_STACK : std_ulogic := '1';
constant IMM_INSTR : std_ulogic_vector (2 downto 0) := "001";
constant IMM_D_427 : data_t := "000110101011" & DATA_STACK & IMM_INSTR;
constant IMM_R_2047 : data_t := "011111111111" & RETURN_STACK & IMM_INSTR;
constant IMM_D_0 : data_t := "000000000000" & DATA_STACK & IMM_INSTR;
constant IMM_D_NEG_1 : data_t := "111111111111" & DATA_STACK & IMM_INSTR;
constant IMM_R_NEG_1000 : data_t := "110000011000" & RETURN_STACK & IMM_INSTR;
constant IMM_R_NEG_2048 : data_t := "100000000000" & RETURN_STACK & IMM_INSTR;
constant HALT : data_t := (others => 'Z');
begin
control: entity work.control port map (
clk => clk,
inst_mem_data => inst_mem_data,
inst_mem_addr => inst_mem_addr,
data_mem_we => data_mem_we,
dstack_data_write => dstack_data_write,
dstack_push => dstack_push,
dstack_pop => dstack_pop,
rstack_data_write => rstack_data_write,
rstack_push => rstack_push,
rstack_pop => rstack_pop,
-- Unused.
rstack_data_read => UNK_DATA,
data_mem_data_read => UNK_DATA,
dstack_data_read => UNK_DATA
);
clock: process begin
clk <= '0';
wait for ClockPeriod;
loop
clk <= not clk;
wait for (ClockPeriod / 2);
end loop;
end process;
stimulus: process begin
-- Should see various positive and negative values being pushed to different stacks.
-- Expect 427 on data.
wait until rising_edge(clk);
inst_mem_data <= IMM_D_427;
-- Expect 2047 on return.
wait until rising_edge(clk);
wait until rising_edge(clk);
inst_mem_data <= IMM_R_2047;
-- Expect 0 on data.
wait until rising_edge(clk);
wait until rising_edge(clk);
inst_mem_data <= IMM_D_0;
-- Expect -1 on data.
wait until rising_edge(clk);
wait until rising_edge(clk);
inst_mem_data <= IMM_D_NEG_1;
-- Expect -1000 on return.
wait until rising_edge(clk);
wait until rising_edge(clk);
inst_mem_data <= IMM_R_NEG_1000;
-- Expect -2048 on return.
wait until rising_edge(clk);
wait until rising_edge(clk);
inst_mem_data <= IMM_R_NEG_2048;
-- Halt.
wait until rising_edge(clk);
wait until rising_edge(clk);
inst_mem_data <= HALT;
wait;
end process;
end Behavioral;
| mit | adfb0fa0634358876d662da5043e4fe3 | 0.602459 | 3.329435 | false | false | false | false |
airabinovich/finalArquitectura | TestDatapathPart1/DatapathPart1/ipcore_dir/instructionROM/simulation/bmg_stim_gen.vhd | 1 | 12,580 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port ROM
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SROM
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SROM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SROM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SROM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST /= '0' ) THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
GENERIC ( C_ROM_SYNTH : INTEGER := 0
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA: OUT STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
DATA_IN : IN STD_LOGIC_VECTOR (31 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
FUNCTION hex_to_std_logic_vector(
hex_str : STRING;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR((hex_str'LENGTH*4)+return_width-1
DOWNTO 0);
BEGIN
tmp := (OTHERS => '0');
FOR i IN 1 TO hex_str'LENGTH LOOP
CASE hex_str((hex_str'LENGTH+1)-i) IS
WHEN '0' => tmp(i*4-1 DOWNTO (i-1)*4) := "0000";
WHEN '1' => tmp(i*4-1 DOWNTO (i-1)*4) := "0001";
WHEN '2' => tmp(i*4-1 DOWNTO (i-1)*4) := "0010";
WHEN '3' => tmp(i*4-1 DOWNTO (i-1)*4) := "0011";
WHEN '4' => tmp(i*4-1 DOWNTO (i-1)*4) := "0100";
WHEN '5' => tmp(i*4-1 DOWNTO (i-1)*4) := "0101";
WHEN '6' => tmp(i*4-1 DOWNTO (i-1)*4) := "0110";
WHEN '7' => tmp(i*4-1 DOWNTO (i-1)*4) := "0111";
WHEN '8' => tmp(i*4-1 DOWNTO (i-1)*4) := "1000";
WHEN '9' => tmp(i*4-1 DOWNTO (i-1)*4) := "1001";
WHEN 'a' | 'A' => tmp(i*4-1 DOWNTO (i-1)*4) := "1010";
WHEN 'b' | 'B' => tmp(i*4-1 DOWNTO (i-1)*4) := "1011";
WHEN 'c' | 'C' => tmp(i*4-1 DOWNTO (i-1)*4) := "1100";
WHEN 'd' | 'D' => tmp(i*4-1 DOWNTO (i-1)*4) := "1101";
WHEN 'e' | 'E' => tmp(i*4-1 DOWNTO (i-1)*4) := "1110";
WHEN 'f' | 'F' => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
WHEN OTHERS => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
END CASE;
END LOOP;
RETURN tmp(return_width-1 DOWNTO 0);
END hex_to_std_logic_vector;
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECK_READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL CHECK_DATA : STD_LOGIC := '0';
SIGNAL CHECK_DATA_R : STD_LOGIC := '0';
SIGNAL CHECK_DATA_2R : STD_LOGIC := '0';
SIGNAL DO_READ_REG: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(31 DOWNTO 0):= hex_to_std_logic_vector("0",32);
BEGIN
SYNTH_COE: IF(C_ROM_SYNTH =0 ) GENERATE
type mem_type is array (255 downto 0) of std_logic_vector(31 downto 0);
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
function char_to_std_logic (
char : in character)
return std_logic is
variable data : std_logic;
begin
if char = '0' then
data := '0';
elsif char = '1' then
data := '1';
elsif char = 'X' then
data := 'X';
else
assert false
report "character which is not '0', '1' or 'X'."
severity warning;
data := 'U';
end if;
return data;
end char_to_std_logic;
impure FUNCTION init_memory( C_USE_DEFAULT_DATA : INTEGER;
C_LOAD_INIT_FILE : INTEGER ;
C_INIT_FILE_NAME : STRING ;
DEFAULT_DATA : STD_LOGIC_VECTOR(31 DOWNTO 0);
width : INTEGER;
depth : INTEGER)
RETURN mem_type IS
VARIABLE init_return : mem_type := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(width-1 DOWNTO 0);
VARIABLE bitline : LINE;
variable bitsgood : boolean := true;
variable bitchar : character;
VARIABLE i : INTEGER;
VARIABLE j : INTEGER;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Block Memory Generator CORE Generator module loading initial data..." SEVERITY NOTE;
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
FOR i IN 0 TO depth-1 LOOP
init_return(i) := DEFAULT_DATA;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, bitline);
-- read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO width-1 LOOP
read(bitline,bitchar,bitsgood);
init_return(i)(width-1-j) := char_to_std_logic(bitchar);
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
constant c_init : mem_type := init_memory(1,
1,
"instructionROM.mif",
DEFAULT_DATA,
32,
256);
constant rom : mem_type := c_init;
BEGIN
EXPECTED_DATA <= rom(conv_integer(unsigned(check_read_addr)));
CHECKER_RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH =>256 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => CHECK_DATA_2R,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => CHECK_READ_ADDR
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R ='1') THEN
IF(EXPECTED_DATA = DATA_IN) THEN
STATUS<='0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- Simulatable ROM
--Synthesizable ROM
SYNTH_CHECKER: IF(C_ROM_SYNTH = 1) GENERATE
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R='1') THEN
IF(DATA_IN=DEFAULT_DATA) THEN
STATUS <= '0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
READ_ADDR_INT(7 DOWNTO 0) <= READ_ADDR(7 DOWNTO 0);
ADDRA <= READ_ADDR_INT ;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 256 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
RD_PROCESS: PROCESS (CLK)
BEGIN
IF (RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_READ <= '0';
ELSE
DO_READ <= '1';
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(0),
CLK =>CLK,
RST=>RST,
D =>DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(I),
CLK =>CLK,
RST=>RST,
D =>DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
CHECK_DATA_REG_1: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_2R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA_R
);
CHECK_DATA_REG: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA
);
END ARCHITECTURE;
| lgpl-2.1 | 3af403b2a281f1f05597cdc31635a97e | 0.547774 | 3.686987 | false | false | false | false |
manosaloscables/vhdl | vga/vga_top.vhd | 1 | 1,189 | -- **************************************************
-- * Circuito de pruebas para la sincronización VGA *
-- **************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity vga_top is
port(
clk , rst : in std_logic;
sw : in std_logic_vector(2 downto 0);
rgb : out std_logic_vector(2 downto 0);
hsinc, vsinc : out std_logic
);
end vga_top;
architecture arq of vga_top is
signal rgb_reg : std_logic_vector(2 downto 0);
signal video_on: std_logic;
begin
-- Instanciar un circuito de sincronización VGA
unidad_vga_sinc: entity work.vga_sinc(arq)
port map(
clk => clk,
rst => rst,
px_tick => open,
video_on => video_on,
pixel_x => open,
pixel_y => open,
hsinc => hsinc,
vsinc => vsinc
);
-- Búfer RGB
process(clk, rst) begin
if rst = '0' then
rgb_reg <= (others => '0');
elsif(rising_edge(clk)) then
rgb_reg <= sw;
end if;
end process;
rgb <= rgb_reg when video_on = '1' else "000";
end arq;
| gpl-3.0 | 44f0a9e8047b8e4d4cd3eca9e472eb1a | 0.488196 | 3.437681 | false | false | false | false |
jmarcelof/Phoenix | NoC/Phoenix_crossbar.vhd | 2 | 1,819 | ----------------------------------------------------------------
-- CROSSBAR
-- --------------
-- DATA_AV ->| |
-- DATA_IN ->| |
-- DATA_ACK <-| |-> TX
-- SENDER ->| |-> DATA_OUT
-- FREE ->| |<- CREDIT_I
-- TAB_IN ->| |
-- TAB_OUT ->| |
-- --------------
----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
use work.NoCPackage.all;
entity Phoenix_crossbar is
port(
data_av: in regNport;
data_in: in arrayNport_regflit;
data_ack: out regNport;
sender: in regNport;
free: in regNport;
tab_in: in arrayNport_reg3;
tab_out: in arrayNport_reg3;
tx: out regNport;
data_out: out arrayNport_regflit;
credit_i: in regNport;
retransmission_i: in regNport;
retransmission_in_buf: out regNport);
end Phoenix_crossbar;
architecture Phoenix_crossbar of Phoenix_crossbar is
begin
MUXS: for i in EAST to LOCAL generate
tx(i) <= data_av(to_integer( unsigned(tab_out(i)))) when free(i) = '0' else '0';
data_out(i) <= data_in(to_integer( unsigned(tab_out(i)))) when free(i) = '0' else (others=>'0');
data_ack(i) <= credit_i(to_integer( unsigned(tab_in(i)))) when data_av(i) = '1' else '0';
retransmission_in_buf(i) <= retransmission_i(to_integer( unsigned(tab_in(i)))) when data_av(i)='1' else '0';
end generate MUXS;
end Phoenix_crossbar;
| lgpl-3.0 | 485151d926b55c046bfa7da6021a0f6a | 0.426608 | 4.033259 | false | false | false | false |
manosaloscables/vhdl | circuitos_secuenciales/archivo_reg/archivo_reg.vhd | 1 | 1,564 | -- ************************
-- * Archivo de Registros *
-- ************************
-- Usa indexado dinámico.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity archivo_reg is
generic(
DIR_ANCHO: integer:=2; -- Número de bits para la dirección
DATOS_ANCHO: integer:=8 -- Número de bits por término
);
port(
clk: in std_logic;
-- Activador de estcritura
wr_en: in std_logic;
-- Dirección de estcritura
w_dir: in std_logic_vector (DIR_ANCHO-1 downto 0);
-- Dirección de lectura
r_dir: in std_logic_vector (DIR_ANCHO-1 downto 0);
-- Datos a escribir
w_datos: in std_logic_vector (DATOS_ANCHO-1 downto 0);
-- Datos a leer
r_datos: out std_logic_vector (DATOS_ANCHO-1 downto 0)
);
end archivo_reg;
architecture arq of archivo_reg is
-- Debe crearse un nuevo tipo de datos ya que un arreglo de dos dimensiones
-- no existe en el paquete de std_logic_1164
type mem_tipo_2d is array (0 to 2**DIR_ANCHO-1) of
std_logic_vector(DATOS_ANCHO-1 downto 0);
signal arreglo_reg: mem_tipo_2d;
begin
process(clk)
begin
if (clk'event and clk='1') then
if wr_en='1' then
-- La siguiente declaración infiere la lógica de decodificaión
arreglo_reg(to_integer(unsigned(w_dir))) <= w_datos;
end if;
end if;
end process;
-- Puerto de lectura
-- La siguiente declaración infiere la lógica de multiplexación
r_datos <= arreglo_reg(to_integer(unsigned(r_dir)));
end arq;
| gpl-3.0 | 091eb329e9a5f603e0eb6fe6ef5983f0 | 0.616368 | 3.224742 | false | false | false | false |
TimingKeepers/gen-ugr-cores | modules/bridges/wbs2axism.vhd | 1 | 5,407 | -------------------------------------------------------------------------------
-- Title : Wishbone slave -> AXI master (stream) bridge
-- Project : Misc
-------------------------------------------------------------------------------
-- File : wb2axism.vhd
-- Author : Miguel Jimenez Lopez
-- Company : UGR
-- Created : 2016-04-13
-- Last update: 2016-04-13
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
--
-- This component is designed to convert the Wishbone write transactions
-- to AXI stream ones.
--
-------------------------------------------------------------------------------
-- TODO:
-------------------------------------------------------------------------------
--
-- Copyright (c) 2016 UGR
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library UNISIM;
use UNISIM.vcomponents.all;
library work;
use work.wishbone_pkg.all;
use work.bridge_pkg.all;
entity wbs2axism is
generic (
g_address_width : integer := 32;
g_data_width : integer := 64
);
port (
-- Clock & Reset (neg)
clk_i : in std_logic;
rst_n_i : in std_logic;
-- WB Slave (memory mapped) interface
s_wb_cyc_i : in std_logic;
s_wb_stb_i : in std_logic;
s_wb_adr_i : in std_logic_vector(g_address_width-1 downto 0);
s_wb_dat_i : in std_logic_vector(g_data_width-1 downto 0);
s_wb_sel_i : in std_logic_vector((g_data_width/8)-1 downto 0);
s_wb_we_i : in std_logic;
s_wb_ack_o : out std_logic;
s_wb_stall_o : out std_logic;
-- AXI Master (streaming) interface
m_axis_tdata_o : out std_logic_vector(g_data_width-1 downto 0);
m_axis_tkeep_o : out std_logic_vector((g_data_width/8)-1 downto 0);
m_axis_tlast_o : out std_logic;
m_axis_tready_i : in std_logic;
m_axis_tvalid_o : out std_logic;
m_axis_tstrb_o : out std_logic_vector((g_data_width/8)-1 downto 0)
);
end wbs2axism;
architecture struct of wbs2axism is
type fsm_state is (IDLE, TX_WORD, TX_STALL);
signal state : fsm_state := IDLE;
begin
-- Bridge FSM
wbs2axim_fsm: process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
state <= IDLE;
else
case state is
when IDLE =>
if s_wb_cyc_i = '1' and s_wb_stb_i = '1' then
state <= TX_WORD;
end if;
when TX_WORD =>
if s_wb_cyc_i = '0' and s_wb_stb_i = '0' then
state <= IDLE;
end if;
if m_axis_tready_i = '0' then
state <= TX_STALL;
end if;
when TX_STALL =>
if m_axis_tready_i = '1' then
state <= TX_WORD;
end if;
when others =>
state <= IDLE;
end case;
end if;
end if;
end process wbs2axim_fsm;
-- Data and tvalid
wbs2axim_data: process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
m_axis_tdata_o <= (others => '0');
m_axis_tvalid_o <= '0';
m_axis_tkeep_o <= (others => '0');
m_axis_tstrb_o <= (others => '0');
else
case state is
when IDLE =>
m_axis_tdata_o <= (others => '0');
m_axis_tvalid_o <= '0';
m_axis_tkeep_o <= (others => '0');
m_axis_tstrb_o <= (others => '0');
when TX_WORD =>
if s_wb_cyc_i = '1' and s_wb_stb_i = '1' then
m_axis_tdata_o <= s_wb_dat_i;
m_axis_tkeep_o <= s_wb_sel_i;
m_axis_tstrb_o <= s_wb_sel_i;
m_axis_tvalid_o <= '1';
else
m_axis_tdata_o <= (others => '0');
m_axis_tvalid_o <= '0';
m_axis_tkeep_o <= (others => '0');
m_axis_tstrb_o <= (others => '0');
end if;
when others =>
end case;
end if;
end if;
end process wbs2axim_data;
-- Logic
wbs2axim_logic: process(state, s_wb_cyc_i, s_wb_stb_i)
begin
case state is
when TX_WORD =>
if s_wb_cyc_i = '1' and s_wb_stb_i = '1' then
s_wb_ack_o <= '1';
s_wb_stall_o <= '0';
else
if s_wb_cyc_i = '0' and s_wb_stb_i = '0' then
m_axis_tlast_o <= '1';
end if;
end if;
when others =>
s_wb_ack_o <= '0';
s_wb_stall_o <= '1';
m_axis_tlast_o <= '0';
end case;
end process wbs2axim_logic;
end struct;
| gpl-2.0 | c41186f4d894f4aefd72544105781184 | 0.491585 | 3.210808 | false | false | false | false |
dpolad/dlx | DLX_synth/a.a.b-ALUCTRL.vhd | 1 | 3,550 | -- alu_ctrl.vhd
library ieee;
use ieee.std_logic_1164.all;
use work.myTypes.all;
entity alu_ctrl is
port (
OP : in AluOp;
ALU_WORD : out std_logic_vector(12 downto 0)
);
end alu_ctrl;
architecture bhe of alu_ctrl is
signal out_mux_sel : std_logic_vector(2 downto 0);
signal left_right : std_logic;
signal logic_arith : std_logic;
signal sign_to_adder : std_logic;
signal lu_ctrl : std_logic_vector(1 downto 0);
signal comp_sel : std_logic_vector(2 downto 0);
signal enable_to_booth : std_logic;
signal sign_to_booth : std_logic;
begin
enable_to_booth <= '1' when OP = MULTS or OP = MULTU else
'0';
ALU_WORD <= out_mux_sel&left_right&logic_arith&sign_to_adder&lu_ctrl&comp_sel&enable_to_booth&sign_to_booth;
-- combinatorial process used to send the right data to components
process(OP)
begin
case OP is
-- when NOP we do a random LU operation, maybe change this into something smarter??
when NOP =>
out_mux_sel <= "100";
sign_to_booth <= '0'; -- useless but avoids errors on simulation
when SLLS =>
out_mux_sel <= "010";
left_right <= '0';
logic_arith <= '0';
when SRLS =>
out_mux_sel <= "010";
left_right <= '1';
logic_arith <= '0';
when SRAS =>
out_mux_sel <= "010";
left_right <= '1';
logic_arith <= '1';
when ADDS =>
sign_to_adder <= '0';
out_mux_sel <= "000";
when ADDUS =>
sign_to_adder <= '0';
out_mux_sel <= "000";
when SUBS =>
sign_to_adder <= '1';
out_mux_sel <= "000";
when SUBUS =>
sign_to_adder <= '1';
out_mux_sel <= "000";
when ANDS =>
lu_ctrl <= "00";
out_mux_sel <= "001";
when ORS =>
lu_ctrl <= "01";
out_mux_sel <= "001";
when XORS =>
lu_ctrl <= "10";
out_mux_sel <= "001";
when SEQS =>
sign_to_adder <= '1';
comp_sel <= "100";
out_mux_sel <= "011";
sign_to_booth <= '0';
when SNES =>
sign_to_adder <= '1';
comp_sel <= "101";
out_mux_sel <= "011";
sign_to_booth <= '0';
when SLTS =>
sign_to_adder <= '1';
comp_sel <= "010";
out_mux_sel <= "011";
sign_to_booth <= '1';
when SGTS =>
sign_to_adder <= '1';
comp_sel <= "000";
out_mux_sel <= "011";
sign_to_booth <= '1';
when SLES =>
sign_to_adder <= '1';
comp_sel <= "011";
out_mux_sel <= "011";
sign_to_booth <= '1';
when SGES =>
sign_to_adder <= '1';
comp_sel <= "001";
out_mux_sel <= "011";
sign_to_booth <= '1';
-- UNIMPLEMENTED OPS
-- when MOVI2SS => DOUT <= (others => '0');
-- when MOVS2IS => DOUT <= (others => '0');
-- when MOVFS => DOUT <= (others => '0');
-- when MOVDS => DOUT <= (others => '0');
-- when MOVFP2IS => DOUT <= (others => '0');
-- when MOVI2FP => DOUT <= (others => '0');
-- when MOVI2TS => DOUT <= (others => '0');
-- when MOVT2IS => DOUT <= (others => '0');
when SLTUS =>
sign_to_adder <= '1';
comp_sel <= "010";
out_mux_sel <= "011";
sign_to_booth <= '0';
when SGTUS =>
sign_to_adder <= '1';
comp_sel <= "000";
out_mux_sel <= "011";
sign_to_booth <= '0';
when SLEUS =>
sign_to_adder <= '1';
comp_sel <= "011";
out_mux_sel <= "011";
sign_to_booth <= '0';
when SGEUS =>
sign_to_adder <= '1';
comp_sel <= "001";
out_mux_sel <= "011";
sign_to_booth <= '0';
when MULTU =>
out_mux_sel <= "101";
sign_to_booth <= '0';
when MULTS =>
out_mux_sel <= "101";
sign_to_booth <= '1';
when others => out_mux_sel <= "000";
end case;
end process;
end bhe;
| bsd-2-clause | 1cf0c6afc21966b5dda60a6c0e53dd07 | 0.53493 | 2.610294 | false | false | false | false |
MAV-RT-testbed/MAV-testbed | Syma_Flight_Final/Syma_Flight_Final.srcs/sources_1/ipshared/xilinx.com/axi_quad_spi_v3_2/c64e9f22/hdl/src/vhdl/qspi_cntrl_reg.vhd | 1 | 18,470 | -------------------------------------------------------------------------------
-- qspi_cntrl_reg.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: qspi_cntrl_reg.vhd
-- Version: v3.0
-- Description: control register module for axi quad spi. This module decides the
-- behavior of the core in master/slave, CPOL/CPHA etc modes.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
library lib_pkg_v1_0;
use lib_pkg_v1_0.all;
use lib_pkg_v1_0.lib_pkg.RESET_ACTIVE;
library unisim;
use unisim.vcomponents.FDRE;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_S_AXI_DATA_WIDTH -- Width of the slave data bus
-- C_SPI_NUM_BITS_REG -- Width of SPI registers
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- SYSTEM
-- Bus2IP_Clk -- Bus to IP clock
-- Soft_Reset_op -- Soft_Reset_op Signal
-- SLAVE ATTACHMENT INTERFACE
-- Wr_ce_reduce_ack_gen -- common write ack generation logic input
-- Bus2IP_SPICR_data -- Data written from the PLB bus
-- Bus2IP_SPICR_WrCE -- Write CE for control register
-- Bus2IP_SPICR_RdCE -- Read CE for control register
-- IP2Bus_SPICR_Data -- Data to be send on the bus
-- SPI MODULE INTERFACE
-- Control_Register_Data -- Data to be send on the bus
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Declaration
-------------------------------------------------------------------------------
entity qspi_cntrl_reg is
generic
(
----------------------------
C_S_AXI_DATA_WIDTH : integer; -- 32 bits
----------------------------
-- Number of bits in register, 10 for control reg - to match old version
C_SPI_NUM_BITS_REG : integer;
----------------------------
C_SPICR_REG_WIDTH : integer;
----------------------------
C_SPI_MODE : integer
----------------------------
);
port
(
Bus2IP_Clk : in std_logic;
Soft_Reset_op : in std_logic;
-- Slave attachment ports
Wr_ce_reduce_ack_gen : in std_logic;
Bus2IP_SPICR_WrCE : in std_logic;
Bus2IP_SPICR_RdCE : in std_logic;
Bus2IP_SPICR_data : in std_logic_vector(0 to (C_S_AXI_DATA_WIDTH-1));
-- SPI module ports
SPICR_0_LOOP : out std_logic;
SPICR_1_SPE : out std_logic;
SPICR_2_MASTER_N_SLV : out std_logic;
SPICR_3_CPOL : out std_logic;
SPICR_4_CPHA : out std_logic;
SPICR_5_TXFIFO_RST : out std_logic;
SPICR_6_RXFIFO_RST : out std_logic;
SPICR_7_SS : out std_logic;
SPICR_8_TR_INHIBIT : out std_logic;
SPICR_9_LSB : out std_logic;
--------------------------
-- to Status Register
SPISR_1_LOOP_Back_Error : out std_logic;
SPISR_2_MSB_Error : out std_logic;
SPISR_3_Slave_Mode_Error : out std_logic;
-- SPISR_4_XIP_Mode_On : out std_logic;
SPISR_4_CPOL_CPHA_Error : out std_logic;
IP2Bus_SPICR_Data : out std_logic_vector(0 to (C_SPICR_REG_WIDTH-1));
Control_bit_7_8 : out std_logic_vector(0 to 1) --(7 to 8)
);
end qspi_cntrl_reg;
-------------------------------------------------------------------------------
-- Architecture
--------------------------------------
architecture imp of qspi_cntrl_reg is
-------------------------------------
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-- Signal Declarations
----------------------
signal SPICR_data_int : std_logic_vector(0 to (C_SPICR_REG_WIDTH-1));
signal SPICR_3_4_Reset : std_logic;
signal Control_bit_7_8_int : std_logic_vector(7 to 8);
signal temp_wr_ce : std_logic;
-----
begin
-----
----------------------------
-- Combinatorial operations
----------------------------
-- Control_Register_Data <= SPICR_data_int;
-------------------------------------------------------
SPICR_0_LOOP <= SPICR_data_int(C_SPICR_REG_WIDTH-1); -- as per the SPICR Fig 3 in DS this bit is @ 0th position
SPICR_1_SPE <= SPICR_data_int(C_SPICR_REG_WIDTH-2); -- as per the SPICR Fig 3 in DS this bit is @ 1st position
SPICR_2_MASTER_N_SLV <= SPICR_data_int(C_SPICR_REG_WIDTH-3); -- as per the SPICR Fig 3 in DS this bit is @ 2nd position
SPICR_3_CPOL <= SPICR_data_int(C_SPICR_REG_WIDTH-4); -- as per the SPICR Fig 3 in DS this bit is @ 3rd position
SPICR_4_CPHA <= SPICR_data_int(C_SPICR_REG_WIDTH-5); -- as per the SPICR Fig 3 in DS this bit is @ 4th position
SPICR_5_TXFIFO_RST <= SPICR_data_int(C_SPICR_REG_WIDTH-6); -- as per the SPICR Fig 3 in DS this bit is @ 5th position
SPICR_6_RXFIFO_RST <= SPICR_data_int(C_SPICR_REG_WIDTH-7); -- as per the SPICR Fig 3 in DS this bit is @ 6th position
SPICR_7_SS <= SPICR_data_int(C_SPICR_REG_WIDTH-8); -- as per the SPICR Fig 3 in DS this bit is @ 7th position
SPICR_8_TR_INHIBIT <= SPICR_data_int(C_SPICR_REG_WIDTH-9); -- as per the SPICR Fig 3 in DS this bit is @ 8th position
SPICR_9_LSB <= SPICR_data_int(C_SPICR_REG_WIDTH-10);-- as per the SPICR Fig 3 in DS this bit is @ 9th position
-------------------------------------------------------
SPISR_DUAL_MODE_STATUS_GEN : if C_SPI_MODE = 1 or C_SPI_MODE = 2 generate
----------------------------
--signal ored_SPICR_7_12 : std_logic;
begin
-----
--ored_SPICR_7_12 <= or_reduce(SPICR_data_int(7 to 12));
-- C_SPICR_REG_WIDTH is of 10 bit wide
SPISR_1_LOOP_Back_Error <= SPICR_data_int(C_SPICR_REG_WIDTH-1);-- 9th bit in present SPICR
SPISR_2_MSB_Error <= SPICR_data_int(C_SPICR_REG_WIDTH-C_SPICR_REG_WIDTH); -- 0th LSB bit in present SPICR
SPISR_3_Slave_Mode_Error <= not SPICR_data_int(C_SPICR_REG_WIDTH-3); -- Mst_n_Slv 7th bit in control register - default is slave mode of operation
SPISR_4_CPOL_CPHA_Error <= SPICR_data_int(C_SPICR_REG_WIDTH-5) xor -- bit 5-CPHA and 6-CPOL in present SPICR
SPICR_data_int(C_SPICR_REG_WIDTH-4);-- CPOL-CPHA = 01 or 10 in control register
end generate SPISR_DUAL_MODE_STATUS_GEN;
----------------------------------------
SPISR_NO_DUAL_MODE_STATUS_GEN : if C_SPI_MODE = 0 generate
-------------------------------
begin
-----
SPISR_1_LOOP_Back_Error <= '0';
SPISR_2_MSB_Error <= '0';
SPISR_3_Slave_Mode_Error <= '0';
SPISR_4_CPOL_CPHA_Error <= '0';
end generate SPISR_NO_DUAL_MODE_STATUS_GEN;
-------------------------------------------
SPICR_REG_RD_GENERATE: for i in 0 to C_SPICR_REG_WIDTH-1 generate
-----
begin
-----
IP2Bus_SPICR_Data(i) <= SPICR_data_int(i) and Bus2IP_SPICR_RdCE;
end generate SPICR_REG_RD_GENERATE;
-----------------------------------
---------------------------------------------------------------
-- Bus2IP Data bit mapping - 0 to 21 - NA
-- 22 23 24 25 26 27 28 29 30 31
--
-- Control Register - 0 to 22 bit mapping
-- 0 1 2 3 4 5 6 7 8 9
-- LSB TRAN MANUAL RX FIFO TX FIFO CPHA CPOL MASTER SPE LOOP
-- INHI SLAVE RST RST
-- '0' '1' '1' '0' '0' '0' '0' '0' '0' '0'
-----------------------------------------------------
-- AXI Data 31 downto 0 |
-- valid bits in AXI start from LSB i.e. 0 |
-- Bus2IP_Data 0 to 31 |
-- **** IMP Starts **** |
-- This is 1 is to 1 mapping with reverse bit order.|
-- **** IMP Ends **** |
-- Bus2IP_Data 0 1 2 3 4 5 6 7 21 22--->31 |
-- Control Bits<-------NA--------> 0---->9 |
-----------------------------------------------------
--SPICR_NO_DUAL_MODE_WR_GEN: if C_SPI_MODE = 0 generate
---------------------------------
--begin
-----
-- SPICR_data_int(0 to 12) <= (others => '0');
--end generate SPICR_NO_DUAL_MODE_WR_GEN;
----------------------------------------------
temp_wr_ce <= wr_ce_reduce_ack_gen and Bus2IP_SPICR_WrCE;
-- -- SPICR_REG_0_PROCESS : Control Register Write Operation for bit 0 - LSB
-- -----------------------------
-- Behavioral Code **
SPICR_REG_0_PROCESS:process(Bus2IP_Clk)
-----
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
SPICR_data_int(0) <= '0';
elsif ((wr_ce_reduce_ack_gen and Bus2IP_SPICR_WrCE)='1') then
SPICR_data_int(0) <=
Bus2IP_SPICR_data(C_S_AXI_DATA_WIDTH-C_SPICR_REG_WIDTH);-- after 100 ps;
end if;
end if;
end process SPICR_REG_0_PROCESS;
--------------------------------
CONTROL_REG_1_2_GENERATE: for i in 1 to 2 generate
------------------------
begin
-----
-- SPICR_REG_1_2_PROCESS : Control Register Write Operation for bit 1_2 - TRAN_INHI and MANUAL_SLAVE
-----------------------------
SPICR_REG_1_2_PROCESS:process(Bus2IP_Clk)
-----
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
SPICR_data_int(i) <= '1';
elsif((wr_ce_reduce_ack_gen and Bus2IP_SPICR_WrCE)='1') then
SPICR_data_int(i) <=
Bus2IP_SPICR_data(C_S_AXI_DATA_WIDTH-C_SPICR_REG_WIDTH+i);-- after 100 ps;
end if;
end if;
end process SPICR_REG_1_2_PROCESS;
----------------------------------
end generate CONTROL_REG_1_2_GENERATE;
--------------------------------------
-- the below reset signal is needed to de-assert the Tx/Rx FIFO reset signals.
SPICR_3_4_Reset <= (not Bus2IP_SPICR_WrCE) or Soft_Reset_op;
-- CONTROL_REG_3_4_GENERATE : Control Register Write Operation for bit 3_4 - Receive FIFO Reset and Transmit FIFO Reset
-----------------------------
CONTROL_REG_3_4_GENERATE: for i in 3 to 4 generate
-----
begin
-----
SPICR_REG_3_4_PROCESS:process(Bus2IP_Clk)
-----
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (SPICR_3_4_Reset = RESET_ACTIVE) then
SPICR_data_int(i) <= '0';
elsif ((wr_ce_reduce_ack_gen and Bus2IP_SPICR_WrCE)='1') then
SPICR_data_int(i) <=
Bus2IP_SPICR_data(C_S_AXI_DATA_WIDTH-C_SPICR_REG_WIDTH+i);-- after 100 ps;
end if;
end if;
end process SPICR_REG_3_4_PROCESS;
----------------------------------
end generate CONTROL_REG_3_4_GENERATE;
--------------------------------------
-- CONTROL_REG_5_9_GENERATE : Control Register Write Operation for bit 5:9 - CPHA, CPOL, MASTER, SPE, LOOP
-----------------------------
CONTROL_REG_5_9_GENERATE: for i in 5 to C_SPICR_REG_WIDTH-1 generate
-----
begin
-----
SPICR_REG_5_9_PROCESS:process(Bus2IP_Clk)
-----
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
SPICR_data_int(i) <= '0';
elsif ((wr_ce_reduce_ack_gen and Bus2IP_SPICR_WrCE)='1') then
SPICR_data_int(i) <=
Bus2IP_SPICR_data(C_S_AXI_DATA_WIDTH-C_SPICR_REG_WIDTH+i);-- after 100 ps;
end if;
end if;
end process SPICR_REG_5_9_PROCESS;
----------------------------------
end generate CONTROL_REG_5_9_GENERATE;
--------------------------------------
--
-- SPICR_REG_78_GENERATE: This logic is newly added to register _T signals
-- ------------------------ in IOB. This logic simplifies the register method
-- for _T in IOB, without affecting functionality.
SPICR_REG_78_GENERATE: for i in 7 to 8 generate
-----
begin
-----
SPI_TRISTATE_CONTROL_I: component FDRE
port map
(
Q => Control_bit_7_8_int(i) ,-- out:
C => Bus2IP_Clk ,--: in
CE => Bus2IP_SPICR_WrCE ,--: in
R => Soft_Reset_op ,-- : in
D => Bus2IP_SPICR_data(C_S_AXI_DATA_WIDTH-C_SPICR_REG_WIDTH+i) --: in
);
end generate SPICR_REG_78_GENERATE;
-----------------------------------
Control_bit_7_8 <= Control_bit_7_8_int;
---------------------------------------
end imp;
--------------------------------------------------------------------------------
| gpl-2.0 | 2f2399909d6c5aeda44da371eb4b9fdb | 0.450677 | 4.288368 | false | false | false | false |
jobisoft/jTDC | modules/VFB6/disc16/Disc16T_ADC_DAC_Controller.vhdl | 1 | 38,606 | -------------------------------------------------------------------------
---- ----
---- Engineer: Christian Honisch ----
---- Company : ELB-Elektroniklaboratorien Bonn UG ----
---- (haftungsbeschränkt) ----
---- ----
---- Description : State machine that controls ADC and DAC on ----
---- Disc16T. Things that are controlled are 2 DACs ----
---- and one ADC (hysteresis dac has to be ----
---- implemented independently). ----
---- ----
-------------------------------------------------------------------------
---- ----
---- Copyright (C) 2015 ELB ----
---- ----
---- This program is free software; you can redistribute it and/or ----
---- modify it under the terms of the GNU General Public License as ----
---- published by the Free Software Foundation; either version 3 of ----
---- the License, or (at your option) any later version. ----
---- ----
---- This program is distributed in the hope that it will be useful, ----
---- but WITHOUT ANY WARRANTY; without even the implied warranty of ----
---- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ----
---- GNU General Public License for more details. ----
---- ----
---- You should have received a copy of the GNU General Public ----
---- License along with this program; if not, see ----
---- <http://www.gnu.org/licenses>. ----
---- ----
-------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------
-- core of design is a state machine with following modes:
-- 1) All thresholds and all hysteresis-set-voltages are measured in a cycle (lowest priority)
-- 2) Write Value into DAC register = set DAC-Voltage (including offset dac)
-- 3) Write certain register in DAC (allows access to all registers)
-- 4) read back dac value (read back written setting)
-- 5) read certain register (allows access to all registers)
-- 6) digitize certain voltage (allows digitizing of voltages not coverd by mode 1. e.g. ref, offsetdac,...)
-------------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Disc16T_ADC_DAC_Controller is
Port ( CLK : in STD_LOGIC; -- system clock
ADC_Frequency : in STD_LOGIC_VECTOR (15 downto 0);
initialize_DACs : in STD_LOGIC;
-- for mode 1: Measured thresholds and measured hysteresis setting voltages (not equal to hysteresis)
THR1, THR2, THR3, THR4, THR5, THR6, THR7, THR8, THR9, THR10, THR11, THR12, THR13, THR14, THR15, THR16 : out STD_LOGIC_VECTOR (15 downto 0):=X"DEAD";
HYS1, HYS2, HYS3, HYS4, HYS5, HYS6, HYS7, HYS8, HYS9, HYS10, HYS11, HYS12, HYS13, HYS14, HYS15, HYS16 : out STD_LOGIC_VECTOR (15 downto 0):=X"DEAD";
DAC1_OFFSETA,DAC1_OFFSETB,DAC2_OFFSETA,DAC2_OFFSETB, DAC1_REFA, DAC1_REFB, DAC2_REFA, DAC2_REFB, DAC_GND : out STD_LOGIC_VECTOR(15 downto 0):=X"DEAD";
Enable_Automatic_Measurement : in STD_LOGIC;
-- for mode 2: write dac register
DAC_Index_W : in STD_LOGIC_VECTOR (4 downto 0); -- 0= broadcast (=all channels), 1...16 =channels, 17..20 = offsetdacs(1a,1b,2a,2b)
DAC_Value_W : in STD_LOGIC_VECTOR (15 downto 0); -- value to be written to dac, 16 bit for compability with 16 bit version of dac.
WE_DAC_Register : in STD_LOGIC; --Write enable
-- for mode 3: write arbitraty register
ARB_W_ADDR : in STD_LOGIC_VECTOR (4 downto 0); -- target address
ARB_W_Value : in STD_LOGIC_Vector (15 downto 0);-- value
ARB_W_WE1,ARB_W_WE2 : in STD_LOGIC; -- write enable for both dacs
-- for mode 4: read DAC register (complementary to mode 2)
DAC_Index_R : in STD_LOGIC_VECTOR (4 downto 0); -- 0...15 =channels, 16..19 = offsetdacs
DAC_Value_R : out STD_LOGIC_VECTOR (15 downto 0):=X"DEAD";-- output
DAC_Index_Read : out STD_LOGIC_VECTOR (4 downto 0):="11110"; -- index from which value was read, initial 1E
RE_DAC_Register : in STD_LOGIC; -- read command
RE_DAC_Reg_Valid : out STD_LOGIC:='0'; -- data valid
-- for mode 5: read arbitrary register (complementary to mode 3)
ARB_R_ADDR : in STD_LOGIC_VECTOR (4 downto 0); -- target address
ARB_R_RD1 : in STD_LOGIC; -- read enable DAC1
ARB_R_RD2 : in STD_LOGIC; -- read enable DAC2, both dacs can be read at the same time
ARB_R_Valid1, ARB_R_Valid2 : out STD_LOGIC :='0'; -- data valid
ARB_R_Read_Addr1, ARB_R_Read_Addr2 : out STD_LOGIC_VECTOR (4 downto 0):="11110"; -- register from which value was read, initial 1E
ARB_R_Value1,ARB_R_Value2 : out STD_LOGIC_VECTOR (15 downto 0):=X"dead";-- value
-- for mode 6: read arbitrary analog channel = RAA
-- replaced by index --RAA_DAC1_Mux, RAA_DAC2_Mux : in STD_LOGIC_VECTOR (4 downto 0);
-- replaced by index --RAA_DAC1_IO, RAA_DAC2_IO : in STD_LOGIC_VECTOR (2 downto 0); -- setting for IO
RAA_WR : in STD_LOGIC; -- write command
RAA_Index: in STD_LOGIC_VECTOR (5 downto 0);-- channel that has to be digitized.
RAA_Value : out STD_LOGIC_VECTOR (15 downto 0):=X"DEAD"; -- measured value
RAA_Valid : out STD_LOGIC :='0'; -- data valid
RAA_read_index : out STD_LOGIC_VECTOR (5 downto 0):="001110"; -- channel which was read -- replaced by index: RAA_DAC1_Mux_V, RAA_DAC2_Mux_V : out STD_LOGIC_VECTOR (4 downto 0); -- mux values which were set, when read command was done
TDAC_ADC_Busy : out STD_LOGIC;
MuteChannelDuringTrhesholdChange : IN STD_LOGIC;
-- SPI DAC and ADC interfaces
--ADC_F0, ADC_CS : out std_logic;
--ADC_CLK, ADC_SDO : in std_logic;
--for hysteresis setting:
HDAC_Data : in STD_LOGIC_VECTOR (7 downto 0);
HDAC_Channel : in STD_LOGIC_VECTOR (4 downto 0);
HDAC_WE : in STD_LOGIC;
HDAC_INIT : in STD_LOGIC;
HDAC_Busy : OUT STD_LOGIC;
--MEZ : INOUT std_logic_vector(79 downto 0) :=(others=>'Z')
--DAC_SCLK, DAC_SDI, DAC_CS : out std_logic_vector(2 downto 1);
--DAC_SDO : in std_logic_vector(2 downto 1);
--DAC_WAKEUP, DAC_LDAC, DAC_CLR : IN std_logic_vector(2 downto 1);
--DAC_RST, DAC_Data_Format : IN std_logic_vector(2 downto 1);
--for ELB_DISC16T in/out
DAC_SDI, DAC_SCLK, DAC_CS : out STD_LOGIC_VECTOR(2 downto 1) :="11";
DAC_SDO : in STD_LOGIC_VECTOR(2 downto 1) :="11";
HDAC_CLK, HDAC_Load, HDAC_SDI : out STD_LOGIC_VECTOR(2 downto 1) :="11";
ADC_SDO, ADC_CLK : in STD_LOGIC;
ADC_F0 : OUT std_logic :='0';
ID_MISO : in STD_LOGIC;
ID_CS : out STD_LOGIC;
ID_CLK, ID_MOSI : out STD_LOGIC;
--signals are not modified by this module, default values
ADC_CS : OUT std_logic :='0';
DAC_WAKEUP : OUT std_logic_vector(2 downto 1):= "00"; -- Low= restore SPI from sleep mode
DAC_LDAC : OUT std_logic_vector(2 downto 1):= "00"; -- Low = DAC-LATCH is transparent
DAC_Data_Format : OUT std_logic_vector(2 downto 1):= "00"; -- Low = straight binary, HIGH= twos complement
DAC_RST : OUT std_logic_vector(2 downto 1):="11"; -- Low = reset dac registers to default value
DAC_CLR : OUT std_logic_vector(2 downto 1):= "11"; -- Low = out connected to AGND, high = buffer amp out
-- new ID readout
DeviceID : OUT STD_LOGIC_VECTOR (47 downto 0);
ReadID : in STD_LOGIC
);
end Disc16T_ADC_DAC_Controller;
architecture Behavioral of Disc16T_ADC_DAC_Controller is
type controller_states is (waiting, -- idle state, accept command
initializing_DACs, -- initialize dac registers
initializing_HDACs, -- initialize hysteresis dacs
next_channel, -- mode1: atomatically digitize data. for this switch to next analog channel
wait_for_spi_done_last, --set_dac_value, -- mode 2: write dac output value
--set_register, -- mode 3: write arbitraty register
read_dac_value, -- mode 4: read dac register value
wait_read_channel_reg_done, -- helpstate for mode 4: wait until datatransfer is finished
read_register, -- mode 5: read arbitrary register
wait_read_reg_done,-- helpstate for mode 5: wait until datatransfer is finished.
switch_to_channel, -- mode 6: switch adc to arbitrary analog channel
wait_for_ADC, -- helpstate for mode 6: wait until adc is avaliable before switching to new channel.
wait_until_dac_finished, -- helpstate for mode 1: wait until switching the muxer is done.
wait_until_dac_finished_ARB -- same for mode 6: wait until switching the muxer is done.
);
signal cont_state : controller_states := waiting;
signal ADC_Busy : STD_LOGIC :='0'; -- flag if adc is digitizing channel right now (if =1 do not switch the analog channels!)
signal ADC_read_now,ADC_read_now_ARB : STD_LOGIC :='0'; -- flag analog mux configuration finished, read adc now.
signal Data_to_skip_found : STD_LOGIC :='0'; -- when the mux has ben configured, the next word from the adc has to be skipped because it is invalid
signal Save_ADC_Data_to_ARB_Register : STD_LOGIC :='0';
constant REF_B : STD_LOGIC_VECTOR (15 downto 0):=X"0010";
constant REF_A : STD_LOGIC_VECTOR (15 downto 0):=X"0020";
constant OFFSET_B : STD_LOGIC_VECTOR (15 downto 0):=X"0050";
constant OFFSET_A : STD_LOGIC_VECTOR (15 downto 0):=X"0060";
constant AIN_0 : STD_LOGIC_VECTOR (15 downto 0):=X"0040";
constant AIN_1 : STD_LOGIC_VECTOR (15 downto 0):=X"0080";
constant DAC_0 : STD_LOGIC_VECTOR (15 downto 0):=X"0100";
constant DAC_1 : STD_LOGIC_VECTOR (15 downto 0):=X"0200";
constant DAC_2 : STD_LOGIC_VECTOR (15 downto 0):=X"0400";
constant DAC_3 : STD_LOGIC_VECTOR (15 downto 0):=X"0800";
constant DAC_4 : STD_LOGIC_VECTOR (15 downto 0):=X"1000";
constant DAC_5 : STD_LOGIC_VECTOR (15 downto 0):=X"2000";
constant DAC_6 : STD_LOGIC_VECTOR (15 downto 0):=X"4000";
constant DAC_7 : STD_LOGIC_VECTOR (15 downto 0):=X"8000";
constant DAC_ADDR_MUX : STD_LOGIC_VECTOR (4 downto 0) :="00001";
constant DAC_ADDR_IO : STD_LOGIC_VECTOR (4 downto 0) :="00010";
constant DAC_ADDR_Broadcast : STD_LOGIC_VECTOR (4 downto 0) :="00111";
constant DAC_ADDR_Config : STD_LOGIC_VECTOR (4 downto 0) :="00000";
constant config_nop : STD_LOGIC_VECTOR (15 downto 0):=X"0020";
constant DISABLE_MUX : STD_LOGIC_VECTOR (15 downto 0):=X"0000";
constant DAC_SPI_CLOCK_DIVIDER : STD_LOGIC_VECTOR (3 downto 0) :="0010";
constant max_dac_index : integer :=20;
function Write_addr_from_DAC_index(index: integer range 0 to max_dac_index) return STD_LOGIC_VECTOR is
begin
case index is
when 0 => return "00111";--broadcast Address
when 1 => return "01000";-- channel 1
when 2 => return "01001";
when 3 => return "01010";
when 4 => return "01011";
when 5 => return "01100";
when 6 => return "01101";
when 7 => return "01110";
when 8 => return "01111";
when 9 => return "01000"; -- same addresses for 9-16 as for 1-8 (same registers in other chip)
when 10 => return "01001";
when 11 => return "01010";
when 12 => return "01011";
when 13 => return "01100";
when 14 => return "01101";
when 15 => return "01110";
when 16 => return "01111";
when 17 => return "00011"; -- offsetdac A
when 18 => return "00100"; -- offsetdac B
when 19 => return "00011"; -- offsetdac A
when 20 => return "00100"; -- offsetdac B
when others => return "00101"; -- reserved register, writing into it has no effect
end case;
end Write_addr_from_DAC_index;
function DAC_Index_for_DAC_1(index: integer range 0 to max_dac_index) return STD_LOGIC is
begin
if index = 0 or index = 1 or index = 2 or index = 3 or index = 4 or index = 5 or index = 6 or index = 7 or index = 8 or index = 17 or index = 18 then
return '1';
else
return '0';
end if;
end DAC_Index_for_DAC_1;
function DAC_Index_for_DAC_2(index: integer range 0 to max_dac_index) return STD_LOGIC is
begin
if index = 0 or index = 9 or index = 10 or index = 11 or index = 12 or index = 13 or index = 14 or index = 15 or index = 16 or index = 19 or index = 20 then
return '1';
else
return '0';
end if;
end DAC_Index_for_DAC_2;
-- funcion to fix bug on prototype pcb
function reverse_bits (input : STD_LOGIC_VECTOR(2 downto 0)) return STD_LOGIC_VECTOR is
begin
return input(0) & input(1) & input (2);
end function;
-- for hdac muxing
function select_data(select_first : STD_LOGIC; in1, in2 : STD_LOGIC_VECTOR) return std_logic_vector is
begin
if select_first='1' then
return in1;
else
return in2;
end if;
end function;
function select_data(select_first : STD_LOGIC; in1, in2 : STD_LOGIC) return STD_LOGIC is
begin
if select_first='1' then
return in1;
else
return in2;
end if;
end function;
constant analog_max_index : integer := 40;
signal current_index : integer range 0 to analog_max_index :=40;
function Mux1_From_Index(a_index: integer range 0 to analog_max_index) return STD_LOGIC_VECTOR is
begin
case a_index is
when 0 => return DAC_0;
when 1 => return DAC_1;
when 2 => return DAC_2;
when 3 => return DAC_3;
when 4 => return DAC_4;
when 5 => return DAC_5;
when 6 => return DAC_6;
when 7 => return DAC_7;
when 16 => return AIN_0;
when 17 => return AIN_0;
when 18 => return AIN_0;
when 19 => return AIN_0;
when 20 => return AIN_0;
when 21 => return AIN_0;
when 22 => return AIN_0;
when 23 => return AIN_0;
when 32 => return OFFSET_A;
when 33 => return OFFSET_B;
when 36 => return REF_A;
when 37 => return REF_B;
when 40 => return AIN_1; -- connection to GND
when others => return DAC_0;-- DISABLE_MUX;
end case;
end Mux1_From_Index;
function Mux2_From_Index(a_index: integer range 0 to analog_max_index) return STD_LOGIC_VECTOR is
begin
case a_index is
when 0 => return AIN_0;
when 1 => return AIN_0;
when 2 => return AIN_0;
when 3 => return AIN_0;
when 4 => return AIN_0;
when 5 => return AIN_0;
when 6 => return AIN_0;
when 7 => return AIN_0;
when 8 => return DAC_0;
when 9 => return DAC_1;
when 10 => return DAC_2;
when 11 => return DAC_3;
when 12 => return DAC_4;
when 13 => return DAC_5;
when 14 => return DAC_6;
when 15 => return DAC_7;
when 16 => return AIN_0;
when 17 => return AIN_0;
when 18 => return AIN_0;
when 19 => return AIN_0;
when 20 => return AIN_0;
when 21 => return AIN_0;
when 22 => return AIN_0;
when 23 => return AIN_0;
when 24 => return AIN_1;
when 25 => return AIN_1;
when 26 => return AIN_1;
when 27 => return AIN_1;
when 28 => return AIN_1;
when 29 => return AIN_1;
when 30 => return AIN_1;
when 31 => return AIN_1;
when 32 => return AIN_0;
when 33 => return AIN_0;
when 34 => return OFFSET_A;
when 35 => return OFFSET_B;
when 36 => return AIN_0;
when 37 => return AIN_0;
when 38 => return REF_A;
when 39 => return REF_B;
when 40 => return AIN_0;
end case;
end Mux2_From_Index;
--- for mode 5 and 4: reading something from the dacs
signal Reading_from_DAC : STD_LOGIC_VECTOR(2 downto 1):="00";--flag if from DAC1/2 is being read
COMPONENT Controller_DAC8218
PORT(
CLK : IN std_logic;
CLK_DIVIDER : IN std_logic_vector(3 downto 0);
SDI : IN std_logic;
SCLK : OUT std_logic;
CS : OUT std_logic;
SDO : OUT std_logic;
ADDR : IN std_logic_vector(4 downto 0);
DATA_Write : IN std_logic_vector(15 downto 0);
WR : IN std_logic;
RD : IN std_logic;
DATA_Read : OUT std_logic_vector(15 downto 0);
busy : OUT std_logic;
Data_Update : OUT std_logic
);
END COMPONENT;
-- glue signals:
signal DAC_WR, DAC_RD, DAC_busy, DAC_data_update : STD_LOGIC_VECTOR(2 downto 1) :="00";
--signal DATA_Read1, DATA_Read2, DATA_Write1, DATA_Write2 : STD_LOGIC_VECTOR (15 downto 0):=X"dead";
signal DAC_Data_Out1, DAC_Data_In1, DAC_Data_Out2, DAC_Data_In2 : STD_LOGIC_VECTOR (15 downto 0):=X"dead";
signal DAC_ADDR1, DAC_ADDR2 : STD_LOGIC_VECTOR(4 downto 0):="11110";
--necessary to write both dacs:
--DAC_ADDR1<=
--DATA_Write1<=
--DAC_ADDR2<=
--DATA_Write2<=
--DAC_WR<="11";
COMPONENT ADC_LT2433_1_Receiver
PORT(
CLK : IN std_logic;
SCLK : IN std_logic;
SDO : IN std_logic;
Data : OUT std_logic_vector(18 downto 0);
Data_Update : OUT std_logic
);
END COMPONENT;
signal ADC_Data_Out : std_logic_vector(18 downto 0);
signal ADC_Data_Update : STD_LOGIC:='0';
--COMPONENT MB88347_Controller
-- PORT(
-- CLK : IN std_logic;
-- CLK_DIV : IN std_logic_vector(7 downto 0);
-- Data : IN std_logic_vector(7 downto 0);
-- Channel : IN std_logic_vector(3 downto 0);
-- WE : IN std_logic;
-- SCLK : OUT std_logic;
-- CS : OUT std_logic;
-- MOSI : OUT std_logic;
-- Busy : OUT std_logic
-- );
-- END COMPONENT;
-- signal HDAC_CLK, HDAC_Load, HDAC_SDI : STD_LOGIC_VECTOR(2 downto 1) :="11";
COMPONENT HDAC_Controller
PORT(
CLK : IN std_logic;
Channel : IN std_logic_vector(4 downto 0);
Data : IN std_logic_vector(11 downto 0);
WE : IN std_logic;
Init : IN std_logic;
Busy : OUT std_logic;
HDAC_CLK : OUT std_logic_vector(2 downto 1);
HDAC_Load : OUT std_logic_vector(2 downto 1);
HDAC_SDI : OUT std_logic_vector(2 downto 1)
);
END COMPONENT;
-- for initialization
--wl 0x100104 11008180 -- configuration register
--wl 0x100100 11aaac -- offsetvoltage for both dacs and both groups
--wl 0x100100 12aaac
--wl 0x100100 13aaac
--wl 0x100100 14aaac
-- result: three write cycles to addresses, both dacs
-- addr 00 data 8180
-- addr 03 data aaac
-- addr 04 data aac
constant number_of_init_commands : integer :=4;
type array_init_data_type is array (0 to number_of_init_commands-1 ) of std_logic_vector(15 downto 0);
constant init_data : array_init_data_type:=(X"8180",X"aaac",X"aaac",X"8800");
type array_init_addr_type is array (0 to number_of_init_commands-1 ) of std_logic_vector(4 downto 0);
constant init_addr : array_init_addr_type:=("00000", "00011","00100", "00111");
signal init_command_index : integer range 0 to number_of_init_commands:=0;
signal init_hdac_counter : integer range 1 to 17:=1;
constant hyst_init_value : STD_LOGIC_VECTOR (7 downto 0) := X"78";
signal hdac_override : STD_LOGIC :='0';
signal HDAC_INT_Data : STD_LOGIC_VECTOR (7 downto 0) :=X"EE";
signal HDAC_INT_addr : STD_LOGIC_VECTOR (4 downto 0) :="11100";
signal HDAC_INT_we : STD_LOGIC_VECTOR (2 downto 1):="00";
--constant adc_clk_divider : integer :=48;
signal counter : integer:=0;-- range 0 to adc_clk_divider :=0;
signal f0 : STD_LOGIC :='0';
--signal ID_MISO : STD_LOGIC;
--signal ID_CS : STD_LOGIC :='1';
--signal ID_CLK, ID_MOSI : STD_LOGIC :='0';
signal HDAC_DATA12 : STD_LOGIC_VECTOR (11 downto 0);
--signal HDAC_INIT : STD_LOGIC;
--signal HDAC_Busy : STD_LOGIC;
------------------------------------------------
--UID
COMPONENT Controller_25AA02E48
PORT(
CLK : IN std_logic;
CLKDivH : IN std_logic_vector(3 downto 0);
CLKDivL : IN std_logic_vector(3 downto 0);
ReadID : IN std_logic;
MISO : IN std_logic;
ID : OUT std_logic_vector(47 downto 0);
SCLK : OUT std_logic;
CS : OUT std_logic;
MOSI : OUT std_logic
);
END COMPONENT;
--Signal DiscID : STD_LOGIC_VECTOR (23 downto 0);
--------- command request processing signals
signal reg_InterfaceBusy,initialize_DACs_request : std_logic :='0';
signal WE_DAC_Register_request : std_logic :='0';
signal RE_DAC_Register_request,ARB_W_WE1_request,ARB_W_WE2_request,ARB_R_RD1_request,ARB_R_RD2_request,RAA_WR_request : std_logic :='0';
signal DAC_Index_W_request, DAC_Index_R_request, ARB_W_ADDR_request, ARB_R_ADDR_request : STD_LOGIC_VECTOR (4 downto 0):=(others=>'0');
signal DAC_Value_W_request, ARB_W_Value_request : STD_LOGIC_VECTOR (15 downto 0):=(others=>'0');
signal RAA_Index_request : STD_LOGIC_VECTOR (5 downto 0):=(others=>'0');
--=======================================================================================================
begin
TDAC_ADC_Busy<=reg_InterfaceBusy; --- interface already received the next command and cannot accept another command right now.
process (CLK) is begin
if rising_edge(CLK) then
if (reg_InterfaceBusy ='0') then
if initialize_DACs = '1' then
initialize_DACs_request<='1';
reg_InterfaceBusy <='1';
elsif WE_DAC_Register='1' then
reg_InterfaceBusy <='1';
WE_DAC_Register_request<='1';
DAC_Index_W_request <= DAC_Index_W;
DAC_Value_W_request <= DAC_Value_W;
elsif RE_DAC_Register='1' then
reg_InterfaceBusy <='1';
RE_DAC_Register_request<='1';
DAC_Index_R_request<=DAC_Index_R;
elsif ARB_W_WE1='1' OR ARB_W_WE2='1' then
reg_InterfaceBusy <='1';
ARB_W_WE1_request<=ARB_W_WE1;
ARB_W_WE2_request<=ARB_W_WE2;
ARB_W_ADDR_request <= ARB_W_ADDR;
ARB_W_Value_request <= ARB_W_Value;
elsif ARB_R_RD1='1' or ARB_R_RD2='1' then
ARB_R_RD1_request<=ARB_R_RD1;
ARB_R_RD2_request<=ARB_R_RD2;
reg_InterfaceBusy <='1';
ARB_R_ADDR_request <=ARB_R_ADDR;
elsif RAA_WR='1' then
reg_InterfaceBusy <='1';
RAA_WR_request<='1';
RAA_Index_request <=RAA_Index;
end if;
else
if cont_state = waiting then -- if state is waiting, command will be processed, request can be cleared.
if WE_DAC_Register_request='1' then
reg_InterfaceBusy<='0';
WE_DAC_Register_request<='0';
end if;
if initialize_DACs_request = '1' then
initialize_DACs_request<='0';
reg_InterfaceBusy <='0';
end if;
if RE_DAC_Register_request='1' then
reg_InterfaceBusy <='0';
RE_DAC_Register_request<='0';
end if;
if ARB_W_WE1_request='1' OR ARB_W_WE2_request='1' then
reg_InterfaceBusy <='0';
ARB_W_WE1_request<='0';
ARB_W_WE2_request<='0';
end if;
if ARB_R_RD1_request='1' or ARB_R_RD2_request='1' then
ARB_R_RD1_request<='0';
ARB_R_RD2_request<='0';
reg_InterfaceBusy <='0';
end if;
if RAA_WR_request='1' then
reg_InterfaceBusy <='0';
RAA_WR_request<='0';
end if;
end if;
end if;
end if;
end process;
process (CLK) is begin
if rising_edge(CLK) then
case cont_state is
when waiting => -- idle state, process command
if initialize_DACs_request='1' then
--if initialize_DACs='1' then
--reg_InterfaceBusy<='0';
--initialize_DACs_request<='0';
cont_state<=initializing_DACs;
init_command_index<=1;
DAC_ADDR1<=init_addr(0);
DAC_ADDR2<=init_addr(0);
DAC_Data_In1<=init_data(0);
DAC_Data_In2<=init_data(0);
DAC_WR<="11";
elsif WE_DAC_Register_request='1' then -- highest priority = writing dac registers
--if WE_DAC_Register='1' then -- highest priority = writing dac registers
cont_state <=wait_for_spi_done_last;
DAC_ADDR1<=Write_addr_from_DAC_index(to_integer(unsigned(DAC_Index_W_request)));
DAC_ADDR2<=Write_addr_from_DAC_index(to_integer(unsigned(DAC_Index_W_request)));
DAC_Data_In1<=DAC_Value_W_request;
DAC_Data_In2<=DAC_Value_W_request;
DAC_WR(1)<=DAC_Index_for_DAC_1(to_integer(unsigned(DAC_Index_W_request)));
DAC_WR(2)<=DAC_Index_for_DAC_2(to_integer(unsigned(DAC_Index_W_request)));
ARB_R_Valid1<=not DAC_Index_for_DAC_1(to_integer(unsigned(DAC_Index_W_request)));
ARB_R_Valid2<=not DAC_Index_for_DAC_2(to_integer(unsigned(DAC_Index_W_request)));
elsif RE_DAC_Register_request='1' then -- mode 4: read dac channel
cont_state <= read_dac_value;
DAC_ADDR1<=Write_addr_from_DAC_index(to_integer(unsigned(DAC_Index_R_request)));
DAC_ADDR2<=Write_addr_from_DAC_index(to_integer(unsigned(DAC_Index_R_request)));
DAC_RD(1)<=DAC_Index_for_DAC_1(to_integer(unsigned(DAC_Index_R_request)));
DAC_RD(2)<=DAC_Index_for_DAC_2(to_integer(unsigned(DAC_Index_R_request)));
RE_DAC_Reg_Valid<='0';
DAC_Index_Read<=DAC_Index_R_request;
Reading_from_Dac(1)<=DAC_Index_for_DAC_1(to_integer(unsigned(DAC_Index_R_request)));
Reading_from_Dac(2)<=DAC_Index_for_DAC_2(to_integer(unsigned(DAC_Index_R_request)));
elsif ARB_W_WE1_request='1' OR ARB_W_WE2_request='1' then -- mode 3: write arbitrary register
cont_state <= wait_for_spi_done_last;--set_register; (changed, because state waits only for DAC transfer to be completed):
DAC_ADDR1<=ARB_W_ADDR_request;
DAC_ADDR2<=ARB_W_ADDR_request;
DAC_Data_In1<=ARB_W_Value_request;
DAC_Data_In2<=ARB_W_Value_request;
DAC_WR(1)<=ARB_W_WE1_request;
DAC_WR(2)<=ARB_W_WE2_request;
ARB_R_Valid1<= not ARB_W_WE1_request;
ARB_R_Valid2<= not ARB_W_WE2_request;
elsif ARB_R_RD1_request='1' or ARB_R_RD2_request='1' then -- mode 5: read arbitrary register
cont_state <= read_register;
-- initiate transfer
DAC_ADDR1<=ARB_R_ADDR_request;
DAC_ADDR2<=ARB_R_ADDR_request;
DAC_RD(1)<=ARB_R_RD1_request;
DAC_RD(2)<=ARB_R_RD2_request;
Reading_from_DAC(1)<=ARB_R_RD1_request;
Reading_from_DAC(2)<=ARB_R_RD2_request;
-- clear dataregisters : (no longer valid)
ARB_R_Valid1<='0';
ARB_R_Read_Addr1<="01110"; -- 0x0E for indication of error
ARB_R_Value1<=X"DEAD";
ARB_R_Valid2<='0';
ARB_R_Read_Addr2<="01110"; -- 0x0E for indication of error
ARB_R_Value2<=X"DEAD";
elsif RAA_WR_request='1' then -- mode 6: read arbitrary analog channel
cont_state <= wait_for_ADC; -- enter helpstate to wait until adc is avalable
RAA_read_index<=RAA_Index_request;
elsif Enable_Automatic_Measurement='1' AND ADC_Busy='0' then -- lowest priority = automatic measurement
cont_state <= next_channel;
-- configure analog mux chain.
-- 1) write DAC Monitor register
-- 2) write DAC IO register, thereby set hysteresis voltage muxer
DAC_ADDR1<=DAC_ADDR_MUX;
DAC_ADDR2<=DAC_ADDR_MUX;
DAC_WR<="11";
if current_index=analog_max_index then
current_index<=0;
DAC_Data_In1<=Mux1_From_Index(0);
DAC_Data_In2<=Mux2_From_Index(0);
else
current_index<=current_index+1;
DAC_Data_In1<=Mux1_From_Index(current_index+1);
DAC_Data_In2<=Mux2_From_Index(current_index+1);
end if;
end if;
when initializing_DACs => -- initializing DACs
DAC_WR<="00";
if dac_busy="00" and init_command_index=number_of_init_commands then
cont_state<=initializing_HDACs;--waiting;
--hdac_override<='1';
--HDAC_INT_Data<=hyst_init_value;
--HDAC_INT_addr<=STD_LOGIC_VECTOR(to_unsigned(init_hdac_counter,5));
--HDAC_INT_we<="11";
--init_hdac_counter<=init_hdac_counter+1;
elsif dac_busy="00" then
--cont_state<=initializing_DACs;
init_command_index<=init_command_index+1;
DAC_ADDR1<=init_addr(init_command_index);
DAC_ADDR2<=init_addr(init_command_index);
DAC_Data_In1<=init_data(init_command_index);
DAC_Data_In2<=init_data(init_command_index);
DAC_WR<="11";
end if;
when initializing_HDACs=>
--HDAC_INT_we<="00";
--if HDAC_Busy="00" AND init_hdac_counter=17 then
cont_state<=waiting;
-- init_hdac_counter<=1;
-- hdac_override<='0';
-- elsif HDAC_Busy="00" and HDAC_INT_we="00" then
-- hdac_override<='1';
-- HDAC_INT_Data<=hyst_init_value;
-- init_hdac_counter<=init_hdac_counter+1;
-- HDAC_INT_addr<=STD_LOGIC_VECTOR(to_unsigned(init_hdac_counter,5));
-- HDAC_INT_we<="11";
-- end if;
when next_channel => -- mode1: atomatically digitize data. for this switch to next analog channel
DAC_WR<="00";
if DAC_busy="00" then
DAC_ADDR1<=DAC_ADDR_IO;
--DAC_Data_In1(12 downto 0)<="0000000000000";
--DAC_Data_In1(15 downto 13)<=reverse_bits(STD_LOGIC_VECTOR(to_unsigned(current_index,3)));-- reversing bits due to bug on prototype pcb...
DAC_Data_In1<=STD_LOGIC_VECTOR(to_unsigned(current_index,3)) & "0000000000000";
DAC_ADDR2<=DAC_ADDR_IO;
DAC_Data_In2<=STD_LOGIC_VECTOR(to_unsigned(current_index,3)) & "0000000000000";
DAC_WR<="11";
cont_state<=wait_until_dac_finished;
end if;
when wait_until_dac_finished =>
DAC_WR<="00";
if DAC_busy="00" then
ADC_read_now<='1';
end if;
if adc_busy ='1' then
cont_state<=waiting;
ADC_read_now<='0';
end if;
when wait_for_spi_done_last => -- mode 2 and 3: write dac output value
DAC_WR<="00";
if DAC_busy="00" then
cont_state<=waiting;
end if;
--when set_register => -- mode 3: write arbitraty register
when read_dac_value => -- mode 4: read dac register value
DAC_RD<="00";
if DAC_busy="00" then
DAC_WR<=Reading_from_DAC; -- write same dac(s) which were prepared for reading
DAC_ADDR1<=DAC_ADDR_Config;
DAC_Data_In1<=config_nop; -- do NOP, so nothing changes during write cycle
DAC_ADDR2<=DAC_ADDR_Config;
DAC_Data_In2<=config_nop; -- do NOP, so nothing changes during write cycle
cont_state<=wait_read_channel_reg_done;
end if;
when wait_read_channel_reg_done=>
DAC_WR<="00";
if DAC_data_update(1)='1' then
RE_DAC_Reg_Valid<='1';
DAC_Value_R<=DAC_Data_Out1;
Reading_from_DAC(1)<='0';
end if;
if DAC_data_update(2)='1' then
RE_DAC_Reg_Valid<='1';
DAC_Value_R<=DAC_Data_Out2;
Reading_from_DAC(2)<='0';
end if;
if Reading_from_DAC="00" then
cont_state<=waiting;
end if;
-- mode 1 end
when read_register => -- mode 5: read arbitrary register
DAC_RD<="00";
if DAC_busy="00" then
DAC_WR<=Reading_from_DAC; -- write same dac(s) which were prepared for reading
DAC_ADDR1<=DAC_ADDR_Config;
DAC_Data_In1<=config_nop; -- do NOP, so nothing changes during write cycle
DAC_ADDR2<=DAC_ADDR_Config;
DAC_Data_In2<=config_nop; -- do NOP, so nothing changes during write cycle
cont_state<=wait_read_reg_done;
end if;
when wait_read_reg_done=>
DAC_WR<="00";
if DAC_data_update(1)='1' then
ARB_R_Valid1<='1';
ARB_R_Read_Addr1<=ARB_R_ADDR;--DAC_ADDR1;
ARB_R_Value1<=DAC_Data_Out1;
Reading_from_DAC(1)<='0';
else
--to be cleared at start of transfer: ARB_R_Valid1<='0';
end if;
if DAC_data_update(2)='1' then
ARB_R_Valid2<='1';
ARB_R_Read_Addr2<=ARB_R_ADDR;--DAC_ADDR2;
ARB_R_Value2<=DAC_Data_Out2;
Reading_from_DAC(2)<='0';
else
--to be cleared at start of transfer: ARB_R_Valid2<='0';
end if;
if Reading_from_DAC="00" then
cont_state<=waiting;
end if;
-- mode 5 end
when wait_for_ADC => -- helpstate for mode 6: wait until adc is avaliable before switching to new channel.
if adc_busy='0' then
cont_state<=switch_to_channel;
DAC_ADDR1<=DAC_ADDR_MUX;
DAC_ADDR2<=DAC_ADDR_MUX;
DAC_WR<="11";
DAC_Data_In1<=Mux1_From_Index(to_integer(unsigned(RAA_Index)));
DAC_Data_In2<=Mux2_From_Index(to_integer(unsigned(RAA_Index)));
end if;
when switch_to_channel => -- mode 6: switch adc to arbitrary analog channel
DAC_WR<="00";
if DAC_busy="00" then
DAC_ADDR1<=DAC_ADDR_IO;
--DAC_Data_In1(12 downto 0)<="0000000000000";
--DAC_Data_In1(15 downto 13)<=reverse_bits(RAA_Index(2 downto 0));-- reversing bits due to bug on prototype pcb...
DAC_Data_In1<= RAA_Index(2 downto 0) & "0000000000000";
DAC_ADDR2<=DAC_ADDR_IO;
DAC_Data_In2<= RAA_Index(2 downto 0) & "0000000000000"; --STD_LOGIC_VECTOR(to_unsigned(current_index,3)) & "0000000000000";
DAC_WR<="11";
cont_state<=wait_until_dac_finished_ARB;
end if;
when wait_until_dac_finished_ARB =>
DAC_WR<="00";
if DAC_busy="00" then
ADC_read_now_ARB<='1';
end if;
if adc_busy ='1' then
cont_state<=waiting;
ADC_read_now_ARB<='0';
end if;
end case;
end if;
end process;
--- process to save ADC data in correct registers.
Process(CLK) is begin
if rising_edge(CLK) then
if RAA_WR='1' then
RAA_Valid<='0'; --if new read command is found: clear valid flag.
end if;
if ADC_busy='0' then
Data_to_skip_found<='0';
if ADC_read_now ='1' OR ADC_read_now_ARB='1' then
ADC_busy<='1';
Save_ADC_Data_to_ARB_Register<=ADC_read_now_ARB; -- save wheather the read cycle is an arbitrary one or an automatic one.
end if;
else
if ADC_Data_Update='1' then -- a new Dataword of the adc is available
if Data_to_skip_found='1' then
--assign data now.
ADC_Busy<='0';
if Save_ADC_Data_to_ARB_Register='1' then
RAA_Value<=ADC_Data_Out(15 downto 0);
RAA_Valid<='1';
else -- save value to according register.
case current_index is
when 0 => THR1<=ADC_Data_Out(15 downto 0);
when 1 => THR2<=ADC_Data_Out(15 downto 0);
when 2 => THR3<=ADC_Data_Out(15 downto 0);
when 3 => THR4<=ADC_Data_Out(15 downto 0);
when 4 => THR5<=ADC_Data_Out(15 downto 0);
when 5 => THR6<=ADC_Data_Out(15 downto 0);
when 6 => THR7<=ADC_Data_Out(15 downto 0);
when 7 => THR8<=ADC_Data_Out(15 downto 0);
when 8 => THR9<=ADC_Data_Out(15 downto 0);
when 9 => THR10<=ADC_Data_Out(15 downto 0);
when 10 => THR11<=ADC_Data_Out(15 downto 0);
when 11 => THR12<=ADC_Data_Out(15 downto 0);
when 12 => THR13<=ADC_Data_Out(15 downto 0);
when 13 => THR14<=ADC_Data_Out(15 downto 0);
when 14 => THR15<=ADC_Data_Out(15 downto 0);
when 15 => THR16<=ADC_Data_Out(15 downto 0);
when 16 => HYS1<=ADC_Data_Out(15 downto 0);
when 17 => HYS2<=ADC_Data_Out(15 downto 0);
when 18 => HYS3<=ADC_Data_Out(15 downto 0);
when 19 => HYS4<=ADC_Data_Out(15 downto 0);
when 20 => HYS5<=ADC_Data_Out(15 downto 0);
when 21 => HYS6<=ADC_Data_Out(15 downto 0);
when 22 => HYS7<=ADC_Data_Out(15 downto 0);
when 23 => HYS8<=ADC_Data_Out(15 downto 0);
when 24 => HYS9<=ADC_Data_Out(15 downto 0);
when 25 => HYS10<=ADC_Data_Out(15 downto 0);
when 26 => HYS11<=ADC_Data_Out(15 downto 0);
when 27 => HYS12<=ADC_Data_Out(15 downto 0);
when 28 => HYS13<=ADC_Data_Out(15 downto 0);
when 29 => HYS14<=ADC_Data_Out(15 downto 0);
when 30 => HYS15<=ADC_Data_Out(15 downto 0);
when 31 => HYS16<=ADC_Data_Out(15 downto 0);
when 32 => DAC1_OFFSETA<=ADC_Data_Out(15 downto 0);
when 33 => DAC1_OFFSETB<=ADC_Data_Out(15 downto 0);
when 34 => DAC2_OFFSETA<=ADC_Data_Out(15 downto 0);
when 35 => DAC2_OFFSETB<=ADC_Data_Out(15 downto 0);
when 36 => DAC1_REFA<=ADC_Data_Out(15 downto 0);
when 37 => DAC1_REFB<=ADC_Data_Out(15 downto 0);
when 38 => DAC2_REFA<=ADC_Data_Out(15 downto 0);
when 39 => DAC2_REFB<=ADC_Data_Out(15 downto 0);
when 40 => DAC_GND<=ADC_Data_Out(15 downto 0);
end case;
end if;
else
Data_to_skip_found<='1';
end if;
end if;
end if;
end if;
end process;
Inst_Controller_DAC8211: Controller_DAC8218 PORT MAP(
CLK => CLK,
SCLK => DAC_SCLK(1),
CS => DAC_CS(1),
SDO => DAC_SDI(1),
SDI => DAC_SDO(1),
ADDR => DAC_ADDR1,
DATA_Read => DAC_Data_Out1,
DATA_Write => DAC_Data_In1,
WR => DAC_WR(1),
RD => DAC_RD(1),
busy => DAC_busy(1),
Data_Update => DAC_data_update(1),
CLK_DIVIDER => DAC_SPI_CLOCK_DIVIDER
);
Inst_Controller_DAC8218_2: Controller_DAC8218 PORT MAP(
CLK => CLK,
SCLK => DAC_SCLK(2),
CS => DAC_CS(2),
SDO => DAC_SDI(2),
SDI => DAC_SDO(2),
ADDR => DAC_ADDR2,
DATA_Read => DAC_Data_Out2,
DATA_Write => DAC_Data_In2,
WR => DAC_WR(2) ,
RD => DAC_RD(2),
busy => DAC_busy(2),
Data_Update => DAC_data_update(2),
CLK_DIVIDER => DAC_SPI_CLOCK_DIVIDER
);
--- allowed frequency range for f0 (adc datasheet)
-- 2,56 kHz ... 2 MHz
-- 19531 .... 25 Zählschritte
process (CLK) is begin
if rising_edge(CLK) then
if ADC_Frequency(15)='1' then -- use internal oscillator in ADC
f0<='0';
else
counter<=counter -1;
if counter =0 then
if to_integer(unsigned (ADC_Frequency)) >19530 then
counter <=19530;
elsif to_integer(unsigned (ADC_Frequency)) < 24 then
counter <= 24;
else
counter<=to_integer(unsigned (ADC_Frequency));
end if;
f0<= not f0;
end if;
end if;
end if;
end process;
ADC_F0 <= f0;
Inst_ADC_LT2433_1_Receiver: ADC_LT2433_1_Receiver PORT MAP(
CLK => CLK,
SCLK => ADC_CLK,
SDO => ADC_SDO,
Data => ADC_Data_Out,
Data_Update => ADC_Data_Update
);
HDAC_DATA12(11 downto 4)<= HDAC_Data;
HDAC_DATA12(3 downto 0) <= "0000";
Inst_HDAC_Controller: HDAC_Controller PORT MAP(
CLK => CLK,
Channel => HDAC_Channel,
Data => HDAC_DATA12,
Busy => HDAC_Busy,
HDAC_CLK => HDAC_CLK,
HDAC_Load => HDAC_Load,
HDAC_SDI => HDAC_SDI,
WE => HDAC_WE,
Init => HDAC_INIT
);
Inst_Controller_25AA02E48: Controller_25AA02E48 PORT MAP(
CLK => CLK,
CLKDivH => X"A",
CLKDivL => X"A",
ReadID => ReadID,
ID => DeviceID,
SCLK => ID_CLK,
CS => ID_CS,
MOSI => ID_MOSI,
MISO => ID_MISO
);
end Behavioral;
| gpl-3.0 | 84f94d577e178978642ab8ec84134639 | 0.604963 | 3.085605 | false | false | false | false |
INTI-CMNB/Lattuino_IP_Core | Work/lattuino_1_bl_4.vhdl | 1 | 11,235 | ------------------------------------------------------------------------------
---- ----
---- Single Port RAM that maps to a Xilinx/Lattice BRAM ----
---- ----
---- This file is part FPGA Libre project http://fpgalibre.sf.net/ ----
---- ----
---- Description: ----
---- This is a program memory for the AVR. It maps to a Xilinx/Lattice ----
---- BRAM. ----
---- This version can be modified by the CPU (i. e. SPM instruction) ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008-2017 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008-2017 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: SinglePortPM(Xilinx) (Entity and architecture) ----
---- File name: pm_s_rw.in.vhdl (template used) ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: work ----
---- Dependencies: IEEE.std_logic_1164 ----
---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ----
---- iCE40 (iCE40HX4K) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
---- iCEcube2.2016.02 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity lattuino_1_blPM_4 is
generic(
WORD_SIZE : integer:=16; -- Word Size
FALL_EDGE : std_logic:='0'; -- Ram clock falling edge
ADDR_W : integer:=13); -- Address Width
port(
clk_i : in std_logic;
addr_i : in std_logic_vector(ADDR_W-1 downto 0);
data_o : out std_logic_vector(WORD_SIZE-1 downto 0);
we_i : in std_logic;
data_i : in std_logic_vector(WORD_SIZE-1 downto 0));
end entity lattuino_1_blPM_4;
architecture Xilinx of lattuino_1_blPM_4 is
constant ROM_SIZE : natural:=2**ADDR_W;
type rom_t is array(natural range 0 to ROM_SIZE-1) of std_logic_vector(WORD_SIZE-1 downto 0);
signal addr_r : std_logic_vector(ADDR_W-1 downto 0);
signal rom : rom_t :=
(
1720 => x"c00e",
1721 => x"c01d",
1722 => x"c01c",
1723 => x"c01b",
1724 => x"c01a",
1725 => x"c019",
1726 => x"c018",
1727 => x"c017",
1728 => x"c016",
1729 => x"c015",
1730 => x"c014",
1731 => x"c013",
1732 => x"c012",
1733 => x"c011",
1734 => x"c010",
1735 => x"2411",
1736 => x"be1f",
1737 => x"e5cf",
1738 => x"e0d1",
1739 => x"bfde",
1740 => x"bfcd",
1741 => x"e020",
1742 => x"e6a0",
1743 => x"e0b0",
1744 => x"c001",
1745 => x"921d",
1746 => x"36a5",
1747 => x"07b2",
1748 => x"f7e1",
1749 => x"d036",
1750 => x"c125",
1751 => x"cfe0",
1752 => x"e081",
1753 => x"bb8f",
1754 => x"e681",
1755 => x"ee93",
1756 => x"e1a6",
1757 => x"e0b0",
1758 => x"99f1",
1759 => x"c00a",
1760 => x"9701",
1761 => x"09a1",
1762 => x"09b1",
1763 => x"9700",
1764 => x"05a1",
1765 => x"05b1",
1766 => x"f7b9",
1767 => x"e0e0",
1768 => x"e0f0",
1769 => x"9509",
1770 => x"ba1f",
1771 => x"b38e",
1772 => x"9508",
1773 => x"e091",
1774 => x"bb9f",
1775 => x"9bf0",
1776 => x"cffe",
1777 => x"ba1f",
1778 => x"bb8e",
1779 => x"e080",
1780 => x"e090",
1781 => x"9508",
1782 => x"dfe1",
1783 => x"3280",
1784 => x"f421",
1785 => x"e184",
1786 => x"dff2",
1787 => x"e180",
1788 => x"cff0",
1789 => x"9508",
1790 => x"93cf",
1791 => x"2fc8",
1792 => x"dfd7",
1793 => x"3280",
1794 => x"f439",
1795 => x"e184",
1796 => x"dfe8",
1797 => x"2f8c",
1798 => x"dfe6",
1799 => x"e180",
1800 => x"91cf",
1801 => x"cfe3",
1802 => x"91cf",
1803 => x"9508",
1804 => x"9abe",
1805 => x"e044",
1806 => x"e450",
1807 => x"e020",
1808 => x"e030",
1809 => x"b388",
1810 => x"2785",
1811 => x"bb88",
1812 => x"01c9",
1813 => x"9701",
1814 => x"f7f1",
1815 => x"5041",
1816 => x"f7c1",
1817 => x"e011",
1818 => x"dfbd",
1819 => x"3380",
1820 => x"f0c9",
1821 => x"3381",
1822 => x"f499",
1823 => x"dfb8",
1824 => x"3280",
1825 => x"f7c1",
1826 => x"e184",
1827 => x"dfc9",
1828 => x"e481",
1829 => x"dfc7",
1830 => x"e586",
1831 => x"dfc5",
1832 => x"e582",
1833 => x"dfc3",
1834 => x"e280",
1835 => x"dfc1",
1836 => x"e489",
1837 => x"dfbf",
1838 => x"e583",
1839 => x"dfbd",
1840 => x"e580",
1841 => x"c0c2",
1842 => x"3480",
1843 => x"f421",
1844 => x"dfa3",
1845 => x"dfa2",
1846 => x"dfbf",
1847 => x"cfe2",
1848 => x"3481",
1849 => x"f469",
1850 => x"df9d",
1851 => x"3880",
1852 => x"f411",
1853 => x"e082",
1854 => x"c029",
1855 => x"3881",
1856 => x"f411",
1857 => x"e081",
1858 => x"c025",
1859 => x"3882",
1860 => x"f511",
1861 => x"e182",
1862 => x"c021",
1863 => x"3482",
1864 => x"f429",
1865 => x"e1c4",
1866 => x"df8d",
1867 => x"50c1",
1868 => x"f7e9",
1869 => x"cfe8",
1870 => x"3485",
1871 => x"f421",
1872 => x"df87",
1873 => x"df86",
1874 => x"df85",
1875 => x"cfe0",
1876 => x"eb90",
1877 => x"0f98",
1878 => x"3093",
1879 => x"f2f0",
1880 => x"3585",
1881 => x"f439",
1882 => x"df7d",
1883 => x"9380",
1884 => x"0063",
1885 => x"df7a",
1886 => x"9380",
1887 => x"0064",
1888 => x"cfd5",
1889 => x"3586",
1890 => x"f439",
1891 => x"df74",
1892 => x"df73",
1893 => x"df72",
1894 => x"df71",
1895 => x"e080",
1896 => x"df95",
1897 => x"cfb0",
1898 => x"3684",
1899 => x"f009",
1900 => x"c039",
1901 => x"df6a",
1902 => x"9380",
1903 => x"0062",
1904 => x"df67",
1905 => x"9380",
1906 => x"0061",
1907 => x"9210",
1908 => x"0060",
1909 => x"df62",
1910 => x"3485",
1911 => x"f419",
1912 => x"9310",
1913 => x"0060",
1914 => x"c00a",
1915 => x"9180",
1916 => x"0063",
1917 => x"9190",
1918 => x"0064",
1919 => x"0f88",
1920 => x"1f99",
1921 => x"9390",
1922 => x"0064",
1923 => x"9380",
1924 => x"0063",
1925 => x"e0c0",
1926 => x"e0d0",
1927 => x"9180",
1928 => x"0061",
1929 => x"9190",
1930 => x"0062",
1931 => x"17c8",
1932 => x"07d9",
1933 => x"f008",
1934 => x"cfa7",
1935 => x"df48",
1936 => x"2f08",
1937 => x"df46",
1938 => x"9190",
1939 => x"0060",
1940 => x"91e0",
1941 => x"0063",
1942 => x"91f0",
1943 => x"0064",
1944 => x"1191",
1945 => x"c005",
1946 => x"921f",
1947 => x"2e00",
1948 => x"2e18",
1949 => x"95e8",
1950 => x"901f",
1951 => x"9632",
1952 => x"93f0",
1953 => x"0064",
1954 => x"93e0",
1955 => x"0063",
1956 => x"9622",
1957 => x"cfe1",
1958 => x"3784",
1959 => x"f009",
1960 => x"c03e",
1961 => x"df2e",
1962 => x"9380",
1963 => x"0062",
1964 => x"df2b",
1965 => x"9380",
1966 => x"0061",
1967 => x"9210",
1968 => x"0060",
1969 => x"df26",
1970 => x"3485",
1971 => x"f419",
1972 => x"9310",
1973 => x"0060",
1974 => x"c00a",
1975 => x"9180",
1976 => x"0063",
1977 => x"9190",
1978 => x"0064",
1979 => x"0f88",
1980 => x"1f99",
1981 => x"9390",
1982 => x"0064",
1983 => x"9380",
1984 => x"0063",
1985 => x"df16",
1986 => x"3280",
1987 => x"f009",
1988 => x"cf55",
1989 => x"e184",
1990 => x"df26",
1991 => x"e0c0",
1992 => x"e0d0",
1993 => x"9180",
1994 => x"0061",
1995 => x"9190",
1996 => x"0062",
1997 => x"17c8",
1998 => x"07d9",
1999 => x"f528",
2000 => x"9180",
2001 => x"0060",
2002 => x"2388",
2003 => x"f011",
2004 => x"e080",
2005 => x"c005",
2006 => x"91e0",
2007 => x"0063",
2008 => x"91f0",
2009 => x"0064",
2010 => x"9184",
2011 => x"df11",
2012 => x"9180",
2013 => x"0063",
2014 => x"9190",
2015 => x"0064",
2016 => x"9601",
2017 => x"9390",
2018 => x"0064",
2019 => x"9380",
2020 => x"0063",
2021 => x"9621",
2022 => x"cfe2",
2023 => x"3785",
2024 => x"f479",
2025 => x"deee",
2026 => x"3280",
2027 => x"f009",
2028 => x"cf2d",
2029 => x"e184",
2030 => x"defe",
2031 => x"e18e",
2032 => x"defc",
2033 => x"e982",
2034 => x"defa",
2035 => x"e086",
2036 => x"def8",
2037 => x"e180",
2038 => x"def6",
2039 => x"cf22",
2040 => x"3786",
2041 => x"f009",
2042 => x"cf1f",
2043 => x"cf6b",
2044 => x"94f8",
2045 => x"cfff",
others => x"0000"
);
begin
use_rising_edge:
if FALL_EDGE='0' generate
do_rom:
process (clk_i)
begin
if rising_edge(clk_i)then
addr_r <= addr_i;
if we_i='1' then
rom(to_integer(unsigned(addr_i))) <= data_i;
end if;
end if;
end process do_rom;
end generate use_rising_edge;
use_falling_edge:
if FALL_EDGE='1' generate
do_rom:
process (clk_i)
begin
if falling_edge(clk_i)then
addr_r <= addr_i;
if we_i='1' then
rom(to_integer(unsigned(addr_i))) <= data_i;
end if;
end if;
end process do_rom;
end generate use_falling_edge;
data_o <= rom(to_integer(unsigned(addr_r)));
end architecture Xilinx; -- Entity: lattuino_1_blPM_4
| gpl-2.0 | a82c129d8bd843ac2f00318c0df293fe | 0.409702 | 2.905353 | false | false | false | false |
dpolad/dlx | DLX_vhd/001-FF32.vhd | 2 | 528 | library ieee;
use ieee. std_logic_1164.all;
use ieee. std_logic_arith.all;
use ieee. std_logic_unsigned.all;
entity ff32 is
generic (
SIZE : integer := 32
);
PORT(
D : in std_logic_vector(SIZE - 1 downto 0);
clk : in std_logic;
rst : in std_logic;
Q : out std_logic_vector(SIZE - 1 downto 0)
);
end ff32;
architecture behavioral of ff32 is
begin
process(clk,rst)
begin
if(rst='1') then
Q <= (others => '0');
else
if(clk='1' and clk'EVENT) then
Q <= D;
end if;
end if;
end process;
end behavioral;
| bsd-2-clause | bbd0991a4fb20e885cc04c6aeb1fe67a | 0.645833 | 2.514286 | false | false | false | false |
jobisoft/jTDC | modules/VFB6/I2C/i2c_master_bit_ctrl.vhd | 1 | 19,430 | ---------------------------------------------------------------------
---- ----
---- WISHBONE revB2 I2C Master Core; bit-controller ----
---- ----
---- ----
---- Author: Richard Herveille ----
---- [email protected] ----
---- www.asics.ws ----
---- ----
---- Downloaded from: http://www.opencores.org/projects/i2c/ ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2000 Richard Herveille ----
---- [email protected] ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
-- CVS Log
--
-- $Id: i2c_master_bit_ctrl.vhd,v 1.17 2009-02-04 20:17:34 rherveille Exp $
--
-- $Date: 2009-02-04 20:17:34 $
-- $Revision: 1.17 $
-- $Author: rherveille $
-- $Locker: $
-- $State: Exp $
--
-- Change History:
-- $Log: not supported by cvs2svn $
-- Revision 1.16 2009/01/20 20:40:36 rherveille
-- Fixed type iscl_oen instead of scl_oen
--
-- Revision 1.15 2009/01/20 10:34:51 rherveille
-- Added SCL clock synchronization logic
-- Fixed slave_wait signal generation
--
-- Revision 1.14 2006/10/11 12:10:13 rherveille
-- Added missing semicolons ';' on endif
--
-- Revision 1.13 2006/10/06 10:48:24 rherveille
-- fixed short scl high pulse after clock stretch
--
-- Revision 1.12 2004/05/07 11:53:31 rherveille
-- Fixed previous fix :) Made a variable vs signal mistake.
--
-- Revision 1.11 2004/05/07 11:04:00 rherveille
-- Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit.
--
-- Revision 1.10 2004/02/27 07:49:43 rherveille
-- Fixed a bug in the arbitration-lost signal generation. VHDL version only.
--
-- Revision 1.9 2003/08/12 14:48:37 rherveille
-- Forgot an 'end if' :-/
--
-- Revision 1.8 2003/08/09 07:01:13 rherveille
-- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
-- Fixed a potential bug in the byte controller's host-acknowledge generation.
--
-- Revision 1.7 2003/02/05 00:06:02 rherveille
-- Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles.
--
-- Revision 1.6 2003/02/01 02:03:06 rherveille
-- Fixed a few 'arbitration lost' bugs. VHDL version only.
--
-- Revision 1.5 2002/12/26 16:05:47 rherveille
-- Core is now a Multimaster I2C controller.
--
-- Revision 1.4 2002/11/30 22:24:37 rherveille
-- Cleaned up code
--
-- Revision 1.3 2002/10/30 18:09:53 rherveille
-- Fixed some reported minor start/stop generation timing issuess.
--
-- Revision 1.2 2002/06/15 07:37:04 rherveille
-- Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.
--
-- Revision 1.1 2001/11/05 12:02:33 rherveille
-- Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
-- Code updated, is now up-to-date to doc. rev.0.4.
-- Added headers.
--
--
-------------------------------------
-- Bit controller section
------------------------------------
--
-- Translate simple commands into SCL/SDA transitions
-- Each command has 5 states, A/B/C/D/idle
--
-- start: SCL ~~~~~~~~~~~~~~\____
-- SDA XX/~~~~~~~\______
-- x | A | B | C | D | i
--
-- repstart SCL ______/~~~~~~~\___
-- SDA __/~~~~~~~\______
-- x | A | B | C | D | i
--
-- stop SCL _______/~~~~~~~~~~~
-- SDA ==\___________/~~~~~
-- x | A | B | C | D | i
--
--- write SCL ______/~~~~~~~\____
-- SDA XXX===============XX
-- x | A | B | C | D | i
--
--- read SCL ______/~~~~~~~\____
-- SDA XXXXXXX=XXXXXXXXXXX
-- x | A | B | C | D | i
--
-- Timing: Normal mode Fast mode
-----------------------------------------------------------------
-- Fscl 100KHz 400KHz
-- Th_scl 4.0us 0.6us High period of SCL
-- Tl_scl 4.7us 1.3us Low period of SCL
-- Tsu:sta 4.7us 0.6us setup time for a repeated start condition
-- Tsu:sto 4.0us 0.6us setup time for a stop conditon
-- Tbuf 4.7us 1.3us Bus free time between a stop and start condition
--
library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity i2c_master_bit_ctrl is
port (
clk : in std_logic;
rst : in std_logic;
nReset : in std_logic;
ena : in std_logic; -- core enable signal
clk_cnt : in std_logic_vector(15 downto 0); -- clock prescale value
cmd : in std_logic_vector(3 downto 0);
cmd_ack : out std_logic; -- command completed
busy : out std_logic; -- i2c bus busy
al : out std_logic; -- arbitration lost
din : in std_logic;
dout : out std_logic;
-- i2c lines
scl_i : in std_logic; -- i2c clock line input
scl_o : out std_logic; -- i2c clock line output
scl_oen : out std_logic; -- i2c clock line output enable, active low
sda_i : in std_logic; -- i2c data line input
sda_o : out std_logic; -- i2c data line output
sda_oen : out std_logic -- i2c data line output enable, active low
);
end entity i2c_master_bit_ctrl;
architecture structural of i2c_master_bit_ctrl is
constant I2C_CMD_NOP : std_logic_vector(3 downto 0) := "0000";
constant I2C_CMD_START : std_logic_vector(3 downto 0) := "0001";
constant I2C_CMD_STOP : std_logic_vector(3 downto 0) := "0010";
constant I2C_CMD_READ : std_logic_vector(3 downto 0) := "0100";
constant I2C_CMD_WRITE : std_logic_vector(3 downto 0) := "1000";
type states is (idle, start_a, start_b, start_c, start_d, start_e,
stop_a, stop_b, stop_c, stop_d, rd_a, rd_b, rd_c, rd_d, wr_a, wr_b, wr_c, wr_d);
signal c_state : states;
signal iscl_oen, isda_oen : std_logic:='1'; -- internal I2C lines
signal sda_chk : std_logic:='0'; -- check SDA status (multi-master arbitration)
signal dscl_oen : std_logic:='0'; -- delayed scl_oen signals
signal sSCL, sSDA : std_logic:='0'; -- synchronized SCL and SDA inputs
signal dSCL, dSDA : std_logic:='0'; -- delayed versions ofsSCL and sSDA
signal clk_en : std_logic:='0'; -- statemachine clock enable
signal scl_sync, slave_wait : std_logic:='0'; -- clock generation signals
signal ial : std_logic:='0'; -- internal arbitration lost signal
-- signal cnt : unsigned(15 downto 0) := clk_cnt; -- clock divider counter (simulation)
signal cnt : std_logic_vector(15 downto 0):=(others=>'0'); -- clock divider counter (synthesis)
begin
-- whenever the slave is not ready it can delay the cycle by pulling SCL low
-- delay scl_oen
process (clk)
begin
if (clk'event and clk = '1') then
dscl_oen <= iscl_oen;
end if;
end process;
-- slave_wait is asserted when master wants to drive SCL high, but the slave (another master) pulls it low
-- slave_wait remains asserted until the slave (other master) releases SCL
process (clk, nReset)
begin
if (nReset = '0') then
slave_wait <= '0';
elsif (clk'event and clk = '1') then
slave_wait <= (iscl_oen and not dscl_oen and not sSCL) or (slave_wait and not sSCL);
end if;
end process;
-- master drives SCL high, but another master pulls it low
-- master start counting down its low cycle now (clock synchronization)
scl_sync <= dSCL and not sSCL and iscl_oen;
-- generate clk enable signal
gen_clken: process(clk, nReset)
begin
if (nReset = '0') then
cnt <= (others => '0');
clk_en <= '1';
elsif (clk'event and clk = '1') then
if (rst = '1') then
cnt <= (others => '0');
clk_en <= '1';
elsif ( (cnt = 0) or (ena = '0') or (scl_sync = '1') ) then
cnt <= "0000000001100011";--to_unsigned (99,16);
clk_en <= '1';
elsif (slave_wait = '1') then
cnt <= cnt;
clk_en <= '0';
else
cnt <= cnt -1;
clk_en <= '0';
end if;
end if;
end process gen_clken;
-- generate bus status controller
bus_status_ctrl: block
signal sta_condition : std_logic; -- start detected
signal sto_condition : std_logic; -- stop detected
signal cmd_stop : std_logic; -- STOP command
signal ibusy : std_logic; -- internal busy signal
begin
-- synchronize SCL and SDA inputs
synch_scl_sda: process(clk, nReset)
begin
if (nReset = '0') then
sSCL <= '1';
sSDA <= '1';
dSCL <= '1';
dSDA <= '1';
elsif (clk'event and clk = '1') then
if (rst = '1') then
sSCL <= '1';
sSDA <= '1';
dSCL <= '1';
dSDA <= '1';
else
sSCL <= scl_i;
sSDA <= sda_i;
dSCL <= sSCL;
dSDA <= sSDA;
end if;
end if;
end process synch_SCL_SDA;
-- detect start condition => detect falling edge on SDA while SCL is high
-- detect stop condition => detect rising edge on SDA while SCL is high
detect_sta_sto: process(clk, nReset)
begin
if (nReset = '0') then
sta_condition <= '0';
sto_condition <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
sta_condition <= '0';
sto_condition <= '0';
else
sta_condition <= (not sSDA and dSDA) and sSCL;
sto_condition <= (sSDA and not dSDA) and sSCL;
end if;
end if;
end process detect_sta_sto;
-- generate i2c-bus busy signal
gen_busy: process(clk, nReset)
begin
if (nReset = '0') then
ibusy <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
ibusy <= '0';
else
ibusy <= (sta_condition or ibusy) and not sto_condition;
end if;
end if;
end process gen_busy;
busy <= ibusy;
-- generate arbitration lost signal
-- aribitration lost when:
-- 1) master drives SDA high, but the i2c bus is low
-- 2) stop detected while not requested (detect during 'idle' state)
gen_al: process(clk, nReset)
begin
if (nReset = '0') then
cmd_stop <= '0';
ial <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
cmd_stop <= '0';
ial <= '0';
else
if (clk_en = '1') then
if (cmd = I2C_CMD_STOP) then
cmd_stop <= '1';
else
cmd_stop <= '0';
end if;
end if;
if (c_state = idle) then
ial <= (sda_chk and not sSDA and isda_oen);
else
ial <= (sda_chk and not sSDA and isda_oen); -- or (sto_condition and not cmd_stop);
end if;
end if;
end if;
end process gen_al;
al <= ial;
-- generate dout signal, store dout on rising edge of SCL
gen_dout: process(clk)
begin
if (clk'event and clk = '1') then
if (sSCL = '1' and dSCL = '0') then
dout <= dSDA;
end if;
end if;
end process gen_dout;
end block bus_status_ctrl;
-- generate statemachine
nxt_state_decoder : process (clk, nReset, c_state, cmd)
begin
if (nReset = '0') then
c_state <= idle;
cmd_ack <= '0';
iscl_oen <= '1';
isda_oen <= '1';
sda_chk <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1' or ial = '1') then
c_state <= idle;
cmd_ack <= '0';
iscl_oen <= '1';
isda_oen <= '1';
sda_chk <= '0';
else
cmd_ack <= '0'; -- default no acknowledge
if (clk_en = '1') then
case (c_state) is
-- idle
when idle =>
case cmd is
when I2C_CMD_START => c_state <= start_a;
when I2C_CMD_STOP => c_state <= stop_a;
when I2C_CMD_WRITE => c_state <= wr_a;
when I2C_CMD_READ => c_state <= rd_a;
when others => c_state <= idle; -- NOP command
end case;
iscl_oen <= iscl_oen; -- keep SCL in same state
isda_oen <= isda_oen; -- keep SDA in same state
sda_chk <= '0'; -- don't check SDA
-- start
when start_a =>
c_state <= start_b;
iscl_oen <= iscl_oen; -- keep SCL in same state (for repeated start)
isda_oen <= '1'; -- set SDA high
sda_chk <= '0'; -- don't check SDA
when start_b =>
c_state <= start_c;
iscl_oen <= '1'; -- set SCL high
isda_oen <= '1'; -- keep SDA high
sda_chk <= '0'; -- don't check SDA
when start_c =>
c_state <= start_d;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '0'; -- set SDA low
sda_chk <= '0'; -- don't check SDA
when start_d =>
c_state <= start_e;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '0'; -- keep SDA low
sda_chk <= '0'; -- don't check SDA
when start_e =>
c_state <= idle;
cmd_ack <= '1'; -- command completed
iscl_oen <= '0'; -- set SCL low
isda_oen <= '0'; -- keep SDA low
sda_chk <= '0'; -- don't check SDA
-- stop
when stop_a =>
c_state <= stop_b;
iscl_oen <= '0'; -- keep SCL low
isda_oen <= '0'; -- set SDA low
sda_chk <= '0'; -- don't check SDA
when stop_b =>
c_state <= stop_c;
iscl_oen <= '1'; -- set SCL high
isda_oen <= '0'; -- keep SDA low
sda_chk <= '0'; -- don't check SDA
when stop_c =>
c_state <= stop_d;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '0'; -- keep SDA low
sda_chk <= '0'; -- don't check SDA
when stop_d =>
c_state <= idle;
cmd_ack <= '1'; -- command completed
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '1'; -- set SDA high
sda_chk <= '0'; -- don't check SDA
-- read
when rd_a =>
c_state <= rd_b;
iscl_oen <= '0'; -- keep SCL low
isda_oen <= '1'; -- tri-state SDA
sda_chk <= '0'; -- don't check SDA
when rd_b =>
c_state <= rd_c;
iscl_oen <= '1'; -- set SCL high
isda_oen <= '1'; -- tri-state SDA
sda_chk <= '0'; -- don't check SDA
when rd_c =>
c_state <= rd_d;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '1'; -- tri-state SDA
sda_chk <= '0'; -- don't check SDA
when rd_d =>
c_state <= idle;
cmd_ack <= '1'; -- command completed
iscl_oen <= '0'; -- set SCL low
isda_oen <= '1'; -- tri-state SDA
sda_chk <= '0'; -- don't check SDA
-- write
when wr_a =>
c_state <= wr_b;
iscl_oen <= '0'; -- keep SCL low
isda_oen <= din; -- set SDA
sda_chk <= '0'; -- don't check SDA (SCL low)
when wr_b =>
c_state <= wr_c;
iscl_oen <= '1'; -- set SCL high
isda_oen <= din; -- keep SDA
sda_chk <= '1'; -- check SDA
when wr_c =>
c_state <= wr_d;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= din; -- keep SDA
sda_chk <= '1'; -- check SDA
when wr_d =>
c_state <= idle;
cmd_ack <= '1'; -- command completed
iscl_oen <= '0'; -- set SCL low
isda_oen <= din; -- keep SDA
sda_chk <= '0'; -- don't check SDA (SCL low)
when others =>
end case;
end if;
end if;
end if;
end process nxt_state_decoder;
-- assign outputs
scl_o <= '0';
scl_oen <= iscl_oen;
sda_o <= '0';
sda_oen <= isda_oen;
end architecture structural;
| gpl-3.0 | daa0f49ccf34de9d1208902da2cd4db2 | 0.463253 | 3.889111 | false | false | false | false |
rodrigofegui/UnB | 2017.1/Organização e Arquitetura de Computadores/Trabalhos/Projeto Final/Codificação/dec_pc.vhd | 2 | 1,944 | --Módulo para definir valor de pc a ser destinado ao display 7 segmentos
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity dec_pc is
generic(N: integer := 7; M: integer := 32);
port(
clk, rst : in std_logic;
SW : in STD_LOGIC_VECTOR(M-1 downto 0);
HEX0 : out STD_LOGIC_VECTOR(6 downto 0);
HEX1 : out STD_LOGIC_VECTOR(6 downto 0);
HEX2 : out STD_LOGIC_VECTOR(6 downto 0);
HEX3 : out STD_LOGIC_VECTOR(6 downto 0);
HEX4 : out STD_LOGIC_VECTOR(6 downto 0);
HEX5 : out STD_LOGIC_VECTOR(6 downto 0);
HEX6 : out STD_LOGIC_VECTOR(6 downto 0);
HEX7 : out STD_LOGIC_VECTOR(6 downto 0)
);
end;
architecture dec_pc_arch of dec_pc is
-- signals
signal dout : STD_LOGIC_VECTOR(31 DOWNTO 0);
begin
i1 : entity work.PC
generic map(DATA_WIDTH => M)
port map (
clk => clk,
rst => rst,
add_in => SW,
add_out => dout
);
i2 : entity work.seven_seg_decoder
port map (
data => dout(3 downto 0),
segments => HEX0
);
i3 : entity work.seven_seg_decoder
port map (
data => dout(7 downto 4),
segments => HEX1
);
i4 : entity work.seven_seg_decoder
port map (
data => dout(11 downto 8),
segments => HEX2
);
i5 : entity work.seven_seg_decoder
port map (
data => dout(15 downto 12),
segments => HEX3
);
i6 : entity work.seven_seg_decoder
port map (
data => dout(19 downto 16),
segments => HEX4
);
i7 : entity work.seven_seg_decoder
port map (
data => dout(23 downto 20),
segments => HEX5
);
i8 : entity work.seven_seg_decoder
port map (
data => dout(27 downto 24),
segments => HEX6
);
i9 : entity work.seven_seg_decoder
port map (
data => dout(31 downto 28),
segments => HEX7
);
end; | gpl-3.0 | 1241ab9cef7ff8b898ca716b6b87f3d8 | 0.560247 | 2.992296 | false | false | false | false |
jobisoft/jTDC | modules/VFB6/mez_lvds_in.vhdl | 1 | 3,917 | -------------------------------------------------------------------------
---- ----
---- Engineer: Ph. Hoffmeister ----
---- Company : ELB-Elektroniklaboratorien Bonn UG ----
---- (haftungsbeschränkt) ----
---- ----
---- Target Devices: ELB_LVDS_INPUT_MEZ v1.0 ----
---- Description : Component for LVDS input adapter ----
---- ----
-------------------------------------------------------------------------
---- ----
---- Copyright (C) 2015 ELB ----
---- ----
---- This program is free software; you can redistribute it and/or ----
---- modify it under the terms of the GNU General Public License as ----
---- published by the Free Software Foundation; either version 3 of ----
---- the License, or (at your option) any later version. ----
---- ----
---- This program is distributed in the hope that it will be useful, ----
---- but WITHOUT ANY WARRANTY; without even the implied warranty of ----
---- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ----
---- GNU General Public License for more details. ----
---- ----
---- You should have received a copy of the GNU General Public ----
---- License along with this program; if not, see ----
---- <http://www.gnu.org/licenses>. ----
---- ----
-------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity mez_lvds_in is
Port ( data : out STD_LOGIC_VECTOR (31 downto 0) := (others => '0');
MEZ : inout STD_LOGIC_VECTOR (73 downto 0));
end mez_lvds_in;
architecture Behavioral of mez_lvds_in is
signal MEZ_buffer : std_logic_vector (73 downto 0);
begin
buffers: for i in 0 to 73 generate
IBUF_MEZ : IBUF generic map ( IOSTANDARD => "LVCMOS33") port map ( I => MEZ(i), O => MEZ_buffer(i) );
end generate buffers;
data (16) <= not MEZ_buffer (1);
data (0) <= not MEZ_buffer (0);
data (17) <= not MEZ_buffer (3);
data (1) <= not MEZ_buffer (2);
data (18) <= not MEZ_buffer (5);
data (2) <= not MEZ_buffer (4);
data (19) <= not MEZ_buffer (7);
data (3) <= not MEZ_buffer (6);
data (20) <= not MEZ_buffer (9);
data (4) <= not MEZ_buffer (8);
data (21) <= not MEZ_buffer (11);
data (5) <= not MEZ_buffer (10);
data (22) <= not MEZ_buffer (13);
data (6) <= not MEZ_buffer (12);
data (23) <= not MEZ_buffer (15);
data (7) <= not MEZ_buffer (14);
data (24) <= not MEZ_buffer (41);
data (8) <= not MEZ_buffer (40);
data (25) <= not MEZ_buffer (43);
data (9) <= not MEZ_buffer (42);
data (26) <= not MEZ_buffer (45);
data (10) <= not MEZ_buffer (44);
data (27) <= not MEZ_buffer (47);
data (11) <= not MEZ_buffer (46);
data (28) <= not MEZ_buffer (49);
data (12) <= not MEZ_buffer (48);
data (29) <= not MEZ_buffer (51);
data (13) <= not MEZ_buffer (50);
data (30) <= not MEZ_buffer (53);
data (14) <= not MEZ_buffer (52);
data (31) <= not MEZ_buffer (55);
data (15) <= not MEZ_buffer (54);
--defined as inputs, simply leave them open
--MEZ(39 downto 16) <= (others=>'0');
--MEZ(73 downto 56) <= (others=>'0');
end Behavioral;
| gpl-3.0 | 720e18da0b289e5476fc332da727a7aa | 0.449323 | 3.859113 | false | false | false | false |
dpolad/dlx | DLX_vhd/useless/boothmul.vhd | 1 | 5,011 | library ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY BOOTHMUL IS
generic (N : integer := 8);
PORT(
A : IN std_logic_vector (N-1 downto 0);
B : IN std_logic_vector (N-1 downto 0);
P : OUT std_logic_vector (2*N-1 downto 0)
);
END BOOTHMUL;
architecture BEHAVIOR of BOOTHMUL is
component booth_encoder
PORT(
B_in : IN std_logic_vector (2 downto 0);
A_out : OUT std_logic_vector (2 downto 0)
);
end component;
component mux8to1_gen
generic ( M : integer := 64);
PORT(
A : IN std_logic_vector (M-1 downto 0);
B : IN std_logic_vector (M-1 downto 0);
C : IN std_logic_vector (M-1 downto 0);
D : IN std_logic_vector (M-1 downto 0);
E : IN std_logic_vector (M-1 downto 0);
F : IN std_logic_vector (M-1 downto 0);
G : IN std_logic_vector (M-1 downto 0);
H : IN std_logic_vector (M-1 downto 0);
S : IN std_logic_vector (2 downto 0);
Y : OUT std_logic_vector (M-1 downto 0)
);
end component;
component RCA
generic (M : integer := 64
);
Port ( A: In std_logic_vector(M-1 downto 0);
B: In std_logic_vector(M-1 downto 0);
S: Out std_logic_vector(M-1 downto 0)
);
end component;
signal b_enc : std_logic_vector(N downto 0);
type mux_select is array (N/2-1 downto 0) of std_logic_vector(2 downto 0);
signal zeros : std_logic_vector (2*N-1 downto 0);
type mux_in is array (4 downto 0) of std_logic_vector (2*N-1 downto 0);
type tot_in is array (N/2-1 downto 0) of mux_in;
type tot_out is array (N/2-1 downto 0) of std_logic_vector (2*N-1 downto 0);
type tot_sum is array (N/2-1 downto 0) of std_logic_vector (2*N-1 downto 0);
signal tot_mux_in : tot_in;
signal tot_mux_out : tot_out;
signal tot_select: mux_select;
signal mux_ini : mux_in;
signal mux_out0 : std_logic_vector (2*N-1 downto 0);
signal mux_outi: std_logic_vector (2*N-1 downto 0);
signal sum : tot_sum;
signal Cin : std_logic;
signal Cout : std_logic;
type not_type is array (N/2-1 downto 0) of std_logic_vector ( 2*N-1 downto 0);
signal notmuxA : not_type;
signal notmux2A : not_type;
BEGIN
b_enc <= B &'0';
zeros <= (others => '0');
Cin <= '0';
encod_loop: for i in 0 to N/2-1 generate
en_level0 : IF i = 0 generate
encod_0 : booth_encoder port map(b_enc(2 downto 0), tot_select(i));
end generate en_level0;
en_leveli : IF i > 0 generate
encod_i : booth_encoder port map(B(2*i+1 downto 2*i-1), tot_select(i));
end generate en_leveli;
end generate encod_loop;
in_mu : for i in 0 to N/2-1 generate
mlevel_0 : IF i = 0 generate
tot_mux_in(i)(0) <= (others => '0' );
tot_mux_in(i)(1)(2*N-1 downto N) <= (others => '0'OR A(N-1));
tot_mux_in(i)(1)(N-1 downto 0) <= A;
notmuxA(i)(2*N-1 downto N) <= (others => '0'OR A(N-1));
notmuxA(i)(N-1 downto 0) <= A;
tot_mux_in(i)(2) <= std_logic_vector(signed(NOT(notmuxA(i))) + 1);
tot_mux_in(i)(3)(2*N-1 downto N+1) <= (others => '0'OR A(N-1));
tot_mux_in(i)(3)(N downto 1) <= A;
tot_mux_in(i)(3)(0 downto 0) <= (others => '0');
notmux2A(i)(2*N-1 downto N+1) <= (others => '0'OR A(N-1));
notmux2A(i)(N downto 1) <= A;
notmux2A(i)(0 downto 0) <= (others => '0');
tot_mux_in(i)(4) <= std_logic_vector(signed(NOT(notmux2A(i))) + 1);
end generate mlevel_0;
mlevel_i : IF i > 0 generate
tot_mux_in(i)(0) <= (others => '0');
tot_mux_in(i)(1)(2*N-1 downto N+2*i) <= (others => '0'OR A(N-1));
tot_mux_in(i)(1)(N+2*i-1 downto 2*i) <= A;
tot_mux_in(i)(1)(2*i-1 downto 0) <= (others => '0');
notmuxA(i)(2*N-1 downto N+2*i) <= (others => '0'OR A(N-1));
notmuxA(i)(N+2*i-1 downto 2*i) <= A;
notmuxA(i)(2*i-1 downto 0) <= (others => '0');
tot_mux_in(i)(2) <= std_logic_vector(signed(NOT(notmuxA(i))) + 1);
tot_mux_in(i)(3)(2*N-1 downto N+1+2*i) <= (others => '0'OR A(N-1));
tot_mux_in(i)(3)(N+2*i downto 2*i+1) <= A;
tot_mux_in(i)(3)(2*i downto 0) <= (others => '0');
notmux2A(i)(2*N-1 downto N+1+2*i) <= (others => '0'OR A(N-1));
notmux2A(i)(N+2*i downto 2*i+1) <= A;
notmux2A(i)(2*i downto 0) <= (others => '0');
tot_mux_in(i)(4) <= std_logic_vector(signed(NOT(notmux2A(i))) + 1);
end generate mlevel_i;
end generate in_mu;
mux_loop: for i in 0 to N/2-1 generate
mux_i : mux8to1_gen
generic map (M => 2*N)
port map (tot_mux_in(i)(0), tot_mux_in(i)(1), tot_mux_in(i)(2), tot_mux_in(i)(3), tot_mux_in(i)(4), zeros, zeros, zeros, tot_select(i), tot_mux_out(i));
end generate mux_loop;
sum_loop: for i in 0 to N/2-1 generate
level_0 : IF i = 0 generate
sum1 : rca
generic map (M => 2*N)
port map(zeros, tot_mux_out(i), sum(i));
end generate level_0;
level_i : IF i > 0 generate
sum_i : rca
generic map (M => 2*N)
port map(sum(i-1), tot_mux_out(i), sum(i));
end generate level_i;
end generate sum_loop;
P <= sum(N/2-1);
end BEHAVIOR;
| bsd-2-clause | a94bc9f1cd512919d902682a41614ae7 | 0.575534 | 2.479466 | false | false | false | false |
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