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rodrigofegui/UnB | 2017.1/Organização e Arquitetura de Computadores/Trabalhos/Projeto Final/Codificação/md.vhd | 2 | 1,016 | --Módulo para memória de dados
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity md is
generic(N: integer := 7; M: integer := 32);
port(
clk: in STD_LOGIC := '0';
we: in STD_LOGIC := '0';
adr: in STD_LOGIC_VECTOR(N-1 downto 0) := (others => '0');
din: in STD_LOGIC_VECTOR(M-1 downto 0) := (others => '0');
dout: out STD_LOGIC_VECTOR(M-1 downto 0)
);
end;
architecture memory_arch of md is
type mem_array is array(0 to (2**N-1)) of STD_LOGIC_VECTOR(M-1 downto 0);
signal mem: mem_array := (
x"00000001",
x"00000002",
x"00000003",
x"00000004",
x"00000005",
others => (others => '0')
);
begin
process(clk) begin
if clk'event and clk='1' then
if we='1' then
mem(to_integer(unsigned(adr))) <= din;
end if;
end if;
end process;
dout <= mem(to_integer(unsigned(adr)));
end; | gpl-3.0 | f29a982c1379d1a7a64b3b3a3ef9a429 | 0.538153 | 2.813559 | false | false | false | false |
MAV-RT-testbed/MAV-testbed | Syma_Flight_Final/Syma_Flight_Final.srcs/sources_1/ipshared/xilinx.com/axi_quad_spi_v3_2/c64e9f22/hdl/src/vhdl/counter_f.vhd | 3 | 10,385 |
-------------------------------------------------------------------------------
-- counter_f - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: counter_f.vhd
--
-- Description: Implements a parameterizable N-bit counter_f
-- Up/Down Counter
-- Count Enable
-- Parallel Load
-- Synchronous Reset
-- The structural implementation has incremental cost
-- of one LUT per bit.
-- Precedence of operations when simultaneous:
-- reset, load, count
--
-- A default inferred-RTL implementation is provided and
-- is used if the user explicitly specifies C_FAMILY=nofamily
-- or ommits C_FAMILY (allowing it to default to nofamily).
-- The default implementation is also used
-- if needed primitives are not available in FPGAs of the
-- type given by C_FAMILY.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.unsigned;
use IEEE.numeric_std."+";
use IEEE.numeric_std."-";
library unisim;
use unisim.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity counter_f is
generic(
C_NUM_BITS : integer := 9;
C_FAMILY : string := "nofamily"
);
port(
Clk : in std_logic;
Rst : in std_logic;
Load_In : in std_logic_vector(C_NUM_BITS - 1 downto 0);
Count_Enable : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Count_Out : out std_logic_vector(C_NUM_BITS - 1 downto 0);
Carry_Out : out std_logic
);
end entity counter_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of counter_f is
---------------------------------------------------------------------
-- Component declarations
---------------------------------------------------------------------
component MUXCY_L is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component MUXCY_L;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
signal icount_out : unsigned(C_NUM_BITS downto 0);
signal icount_out_x : unsigned(C_NUM_BITS downto 0);
signal load_in_x : unsigned(C_NUM_BITS downto 0);
---------------------------------------------------------------------
-- Constant declarations
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------
begin
---------------------------------------------------------------------
-- Generate Inferred code
---------------------------------------------------------------------
--INFERRED_GEN : if USE_INFERRED generate
load_in_x <= unsigned('0' & Load_In);
-- Mask out carry position to retain legacy self-clear on next enable.
-- icount_out_x <= ('0' & icount_out(C_NUM_BITS-1 downto 0)); -- Echeck WA
icount_out_x <= unsigned('0' & std_logic_vector(icount_out(C_NUM_BITS-1 downto 0)));
-----------------------------------------------------------------
-- Process to generate counter with - synchronous reset, load,
-- counter enable, count down / up features.
-----------------------------------------------------------------
CNTR_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
icount_out <= (others => '0');
elsif Count_Load = '1' then
icount_out <= load_in_x;
elsif Count_Down = '1' and Count_Enable = '1' then
icount_out <= icount_out_x - 1;
elsif Count_Enable = '1' then
icount_out <= icount_out_x + 1;
end if;
end if;
end process CNTR_PROC;
Carry_Out <= icount_out(C_NUM_BITS);
Count_Out <= std_logic_vector(icount_out(C_NUM_BITS-1 downto 0));
end architecture imp;
---------------------------------------------------------------
-- End of file counter_f.vhd
---------------------------------------------------------------
| gpl-2.0 | 640d136d11d0632e460503aca0f74eee | 0.398844 | 5.656318 | false | false | false | false |
Hyperion302/omega-cpu | TestBenches/BranchUnitTB.vhdl | 1 | 2,968 | -- This file is part of the Omega CPU Core
-- Copyright 2015 - 2016 Joseph Shetaye
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as
-- published by the Free Software Foundation, either version 3 of the
-- License, or (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library IEEE;
use IEEE.std_logic_1164.all;
use work.Constants.all;
use IEEE.Numeric_std.all;
use std.textio.all;
entity BranchUnitTB is
end BranchUnitTB;
architecture Behaivoral of BranchUnitTB is
component BranchUnit is
port (
Instruction : in Word;
RegisterA : in Word;
RegisterB : in Word;
NewPC : out Word;
CurrentPC : in Word;
OutputReady : out std_logic);
end component BranchUnit;
signal Instruction : Word;
signal RegisterA : Word;
signal RegisterB : Word;
signal NewPC : Word;
signal CurrentPC : Word;
signal OutputReady : std_logic;
begin -- Behaivoral
UUT: entity work.BranchUnit port map (
Instruction => Instruction,
RegisterA => RegisterA,
RegisterB => RegisterB,
NewPC => NewPC,
CurrentPC => CurrentPC,
OutputReady => OutputReady);
file_io:
process is
variable in_line : line;
variable out_line : line;
variable in_vector : bit_vector(31 downto 0) := (others => '0');
variable outputI : integer := 0;
variable Counter : integer := 0;
variable ExpectedNewPC : Word := (others => '0');
begin -- process
while not endfile(input) loop
readline(input, in_line);
if in_line'length = 32 then
read(in_line, in_vector);
case Counter is
when 0 =>
RegisterA <= to_stdlogicvector(in_vector);
Counter := Counter + 1;
when 1 =>
RegisterB <= to_stdlogicvector(in_vector);
Counter := Counter + 1;
when 2 =>
Instruction <= to_stdlogicvector(in_vector);
Counter := Counter + 1;
when 3 =>
CurrentPC <= to_stdlogicvector(in_vector);
Counter := Counter + 1;
when 4 =>
ExpectedNewPC := to_stdlogicvector(in_vector);
wait for 1 ns;
write(out_line, to_bitvector(NewPC));
writeline(output, out_line);
if (NewPC = ExpectedNewPC) then
write(out_line, string'("Passed"));
else
write(out_line, string'("Failed"));
end if;
writeline(output, out_line);
Counter := 0;
when others => null;
end case;
else
writeline(output,in_line);
end if;
end loop;
wait;
end process;
end Behaivoral;
| lgpl-3.0 | 2470a012cc915815c81a8c2deaa8331b | 0.645553 | 3.879739 | false | false | false | false |
MAV-RT-testbed/MAV-testbed | Syma_Flight_Final/Syma_Flight_Final.srcs/sources_1/ipshared/xilinx.com/axi_quad_spi_v3_2/c64e9f22/hdl/src/vhdl/qspi_startup_block.vhd | 1 | 14,909 | -------------------------------------------------------------------------------
-- qspi_startup_block.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: qspi_startup_block.vhd
-- Version: v3.0
-- Description: This module uses the STARTUP primitive based upon the generic.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- Soft_Reset_op signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.conv_std_logic_vector;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
use IEEE.std_logic_misc.all;
-- library unsigned is used for overloading of "=" which allows integer to
-- be compared to std_logic_vector
use ieee.std_logic_unsigned.all;
library unisim;
--use unisim.vcomponents.STARTUP_SPARTAN6;
--use unisim.vcomponents.STARTUP_VIRTEX6;
use unisim.vcomponents.STARTUPE2; -- for 7-series FPGA's
use unisim.vcomponents.STARTUPE3; -- for 8 series FPGA's
------------------------------
entity qspi_startup_block is
generic
(
C_SUB_FAMILY : string ;
---------------------
C_USE_STARTUP : integer ;
---------------------
C_SPI_MODE : integer
---------------------
);
port
(
SCK_O : in std_logic; -- input from the spi_mode_0_module
IO1_I_startup : in std_logic; -- input from the top level port list
IO1_Int : out std_logic;
Bus2IP_Clk : in std_logic;
reset2ip_reset : in std_logic;
CFGCLK : out std_logic; -- FGCLK , -- 1-bit output: Configuration main clock output
CFGMCLK : out std_logic; -- FGMCLK , -- 1-bit output: Configuration internal oscillator clock output
EOS : out std_logic;-- OS , -- 1-bit output: Active high output signal indicating the End Of Startup.
PREQ : out std_logic;-- REQ , -- 1-bit output: PROGRAM request to fabric output
DI : out std_logic_vector(3 downto 0)-- output
);
end entity qspi_startup_block;
------------------------------
architecture imp of qspi_startup_block is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-- 19-11-2012 added below parameter and signals to fix the CR #679609
constant ADD_PIPELINTE : integer := 8;
signal pipe_signal : std_logic_vector(ADD_PIPELINTE-1 downto 0);
signal PREQ_int : std_logic;
signal PACK_int : std_logic;
-----
begin
-----
PREQ_REG_P:process(Bus2IP_Clk)is -- 19-11-2012
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(reset2ip_reset = '1')then
pipe_signal(0) <= '0';
elsif(PREQ_int = '1')then
pipe_signal(0) <= '1';
end if;
end if;
end process PREQ_REG_P;
PIPE_PACK_P:process(Bus2IP_Clk)is -- 19-11-2012
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(reset2ip_reset = '1')then
pipe_signal(ADD_PIPELINTE-1 downto 1) <= (others => '0');
else
pipe_signal(1) <= pipe_signal(0);
pipe_signal(2) <= pipe_signal(1);
pipe_signal(3) <= pipe_signal(2);
pipe_signal(4) <= pipe_signal(3);
pipe_signal(5) <= pipe_signal(4);
pipe_signal(6) <= pipe_signal(5);
pipe_signal(7) <= pipe_signal(6);
-- pipe_signal(8) <= pipe_signal(7);
end if;
end if;
end process PIPE_PACK_P;
PACK_int <= pipe_signal(7); -- 19-11-2012
-- STARTUP_7SERIES_GEN: Logic instantiation of STARTUP primitive in the core.
STARTUP_7SERIES_GEN: if ( -- In 7-series, the start up is allowed in all C_SPI_MODE values.
C_SUB_FAMILY = "virtex7" or
C_SUB_FAMILY = "kintex7" or
(C_SUB_FAMILY = "zynq") or
C_SUB_FAMILY = "artix7"
) and C_USE_STARTUP = 1 generate
-----
begin
-----
ASSERT (
( -- no check for C_SPI_MODE is needed here. On S6 the startup is not supported.
-- (C_SUB_FAMILY = "virtex6") or
(C_SUB_FAMILY = "virtex7") or
(C_SUB_FAMILY = "kintex7") or
(C_SUB_FAMILY = "zynq") or
(C_SUB_FAMILY = "artix7")
)and
(C_USE_STARTUP = 1)
)
REPORT "*** The use of STARTUP primitive is not supported on this targeted device. ***"
SEVERITY error;
-------------------
IO1_Int <= IO1_I_startup;
-------------------
STARTUP2_7SERIES_inst : component STARTUPE2
-----------------------
generic map
(
PROG_USR => "FALSE", -- Activate program event security feature.
SIM_CCLK_FREQ => 0.0 -- Set the Configuration Clock Frequency(ns) for simulation.
)
port map
(
USRCCLKO => SCK_O, -- SRCCLKO , -- 1-bit input: User CCLK input
----------
CFGCLK => CFGCLK, -- FGCLK , -- 1-bit output: Configuration main clock output
CFGMCLK => CFGMCLK, -- FGMCLK , -- 1-bit output: Configuration internal oscillator clock output
EOS => EOS, -- OS , -- 1-bit output: Active high output signal indicating the End Of Startup.
PREQ => PREQ_int, -- REQ , -- 1-bit output: PROGRAM request to fabric output
----------
CLK => '0', -- LK , -- 1-bit input: User start-up clock input
GSR => '0', -- SR , -- 1-bit input: Global Set/Reset input (GSR cannot be used for the port name)
GTS => '0', -- TS , -- 1-bit input: Global 3-state input (GTS cannot be used for the port name)
KEYCLEARB => '0', -- EYCLEARB , -- 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM)
PACK => PACK_int, -- '1', -- ACK , -- 1-bit input: PROGRAM acknowledge input
USRCCLKTS => '0', -- SRCCLKTS , -- 1-bit input: User CCLK 3-state enable input
USRDONEO => '1', -- SRDONEO , -- 1-bit input: User DONE pin output control
USRDONETS => '1' -- SRDONETS -- 1-bit input: User DONE 3-state enable output
);
end generate STARTUP_7SERIES_GEN;
---------------------------------
---STARTUP for 8 series STARTUPE3
---------------------------------
STARTUP_8SERIES_GEN: if ( -- In 8-series, the start up is allowed in all C_SPI_MODE values.
C_SUB_FAMILY = "virtexu" or
C_SUB_FAMILY = "kintexu" or
C_SUB_FAMILY = "artixu"
) and C_USE_STARTUP = 1 generate
-- -----
begin
-- -----
ASSERT (
(
(C_SUB_FAMILY = "virtexu") or
(C_SUB_FAMILY = "kintexu") or
(C_SUB_FAMILY = "artixu")
)and
(C_USE_STARTUP = 1)
)
REPORT "*** The use of STARTUP primitive is not supported on this targeted device. ***"
SEVERITY error;
-------------------
IO1_Int <= IO1_I_startup;
-------------------
STARTUP3_8SERIES_inst : component STARTUPE3
-----------------------
generic map
(
PROG_USR => "FALSE", -- Activate program event security feature.
SIM_CCLK_FREQ => 0.0 -- Set the Configuration Clock Frequency(ns) for simulation.
)
port map
(
USRCCLKO => SCK_O, -- SRCCLKO , -- 1-bit input: User CCLK input
----------
CFGCLK => CFGCLK, -- FGCLK , -- 1-bit output: Configuration main clock output
CFGMCLK => CFGMCLK, -- FGMCLK , -- 1-bit output: Configuration internal oscillator clock output
EOS => EOS, -- OS , -- 1-bit output: Active high output signal indicating the End Of Startup.
PREQ => PREQ_int, -- REQ , -- 1-bit output: PROGRAM request to fabric output
----------
DO => "0000", -- input
DI => DI, -- output
DTS => "0000", -- input
FCSBO => '0', -- input
FCSBTS => '0', -- input
GSR => '0', -- SR , -- 1-bit input: Global Set/Reset input (GSR cannot be used for the port name)
GTS => '0', -- TS , -- 1-bit input: Global 3-state input (GTS cannot be used for the port name)
KEYCLEARB => '0', -- EYCLEARB , -- 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM)
PACK => PACK_int, -- '1', -- ACK , -- 1-bit input: PROGRAM acknowledge input
USRCCLKTS => '0', -- SRCCLKTS , -- 1-bit input: User CCLK 3-state enable input
USRDONEO => '1', -- SRDONEO , -- 1-bit input: User DONE pin output control
USRDONETS => '1' -- SRDONETS -- 1-bit input: User DONE 3-state enable output
);
end generate STARTUP_8SERIES_GEN;
PREQ <= PREQ_int;
end architecture imp;
| gpl-2.0 | cb5bc9eb7e7c7385f4e15719688c2883 | 0.456436 | 4.595869 | false | false | false | false |
SWORDfpga/ComputerOrganizationDesign | labs/lab08/lab08/ipcore_dir/ROM_D/simulation/ROM_D_tb_stim_gen.vhd | 8 | 10,537 | --------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Stimulus Generator For ROM Configuration
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: ROM_D_tb_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For ROM
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.ROM_D_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_ROM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_ROM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_ROM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST /= '0' ) THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.ROM_D_TB_PKG.ALL;
ENTITY ROM_D_TB_STIM_GEN IS
GENERIC ( C_ROM_SYNTH : INTEGER := 0
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
A : OUT STD_LOGIC_VECTOR(10-1 downto 0) := (OTHERS => '0');
DATA_IN : IN STD_LOGIC_VECTOR (31 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END ROM_D_TB_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF ROM_D_TB_STIM_GEN IS
FUNCTION std_logic_vector_len(
hex_str : STD_LOGIC_VECTOR;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR(return_width DOWNTO 0) := (OTHERS => '0');
VARIABLE tmp_z : STD_LOGIC_VECTOR(return_width-(hex_str'LENGTH) DOWNTO 0) := (OTHERS => '0');
BEGIN
tmp := tmp_z & hex_str;
RETURN tmp(return_width-1 DOWNTO 0);
END std_logic_vector_len;
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECK_READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL CHECK_DATA : STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(31 DOWNTO 0):= std_logic_vector_len("0",32);
BEGIN
SYNTH_COE: IF(C_ROM_SYNTH =0 ) GENERATE
type mem_type is array (1023 downto 0) of std_logic_vector(31 downto 0);
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF(input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
function char_to_std_logic (
char : in character)
return std_logic is
variable data : std_logic;
begin
if char = '0' then
data := '0';
elsif char = '1' then
data := '1';
elsif char = 'X' then
data := 'X';
else
assert false
report "character which is not '0', '1' or 'X'."
severity warning;
data := 'U';
end if;
return data;
end char_to_std_logic;
impure FUNCTION init_memory(
C_USE_DEFAULT_DATA : INTEGER;
C_LOAD_INIT_FILE : INTEGER ;
C_INIT_FILE_NAME : STRING ;
DEFAULT_DATA : STD_LOGIC_VECTOR(31 DOWNTO 0);
width : INTEGER;
depth : INTEGER)
RETURN mem_type IS
VARIABLE init_return : mem_type := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(width-1 DOWNTO 0);
VARIABLE bitline : LINE;
variable bitsgood : boolean := true;
variable bitchar : character;
VARIABLE i : INTEGER;
VARIABLE j : INTEGER;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Distributed Memory Generator CORE Generator module loading initial data..." SEVERITY NOTE;
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
FOR i IN 0 TO depth-1 LOOP
init_return(i) := DEFAULT_DATA;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, bitline);
-- read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO width-1 LOOP
read(bitline,bitchar,bitsgood);
init_return(i)(width-1-j) := char_to_std_logic(bitchar);
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
constant c_init : mem_type := init_memory(1,
1,
"ROM_D.mif",
DEFAULT_DATA,
32,
1024);
constant rom : mem_type := c_init;
BEGIN
EXPECTED_DATA <= rom(conv_integer(unsigned(check_read_addr)));
CHECKER_RD_AGEN_INST:ENTITY work.ROM_D_TB_AGEN
GENERIC MAP( C_MAX_DEPTH =>1024 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => CHECK_DATA(2),
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => check_read_addr
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA(2) ='1') THEN
IF(EXPECTED_DATA = DATA_IN) THEN
STATUS<='0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- Simulatable ROM
--Synthesizable ROM
SYNTH_CHECKER: IF(C_ROM_SYNTH = 1) GENERATE
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA(2)='1') THEN
IF(DATA_IN=DEFAULT_DATA) THEN
STATUS <= '0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
READ_ADDR_INT(9 DOWNTO 0) <= READ_ADDR(9 DOWNTO 0);
A <= READ_ADDR_INT ;
CHECK_DATA(0) <= DO_READ;
RD_AGEN_INST:ENTITY work.ROM_D_TB_AGEN
GENERIC MAP( C_MAX_DEPTH => 1024 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
RD_PROCESS: PROCESS (CLK)
BEGIN
IF (RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_READ <= '0';
ELSE
DO_READ <= '1';
END IF;
END IF;
END PROCESS;
BEGIN_EN_REG: FOR I IN 0 TO 2 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_ROM
PORT MAP(
Q => CHECK_DATA(1),
CLK => CLK,
RST => RST,
D => CHECK_DATA(0)
);
END GENERATE DFF_RIGHT;
DFF_CE_OTHERS: IF ((I>0) AND (I<2)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_ROM
PORT MAP(
Q => CHECK_DATA(I+1),
CLK => CLK,
RST => RST,
D => CHECK_DATA(I)
);
END GENERATE DFF_CE_OTHERS;
END GENERATE BEGIN_EN_REG;
END ARCHITECTURE;
| gpl-3.0 | 0ad9358caf48207cae26cfd0f093c58f | 0.591724 | 3.719379 | false | false | false | false |
jmarcelof/Phoenix | NoC/Decoder.vhd | 2 | 3,221 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.Numeric_std.all;
use work.HammingPack16.all;
use work.NoCPackage.all;
entity HAM_DEC is
port
(
data_in : in regflit; -- data input
parity_in : in reghamm; -- parity input
data_out : out regflit; -- data output (corrected data)
parity_out : out reghamm; -- parity output (corrected parity)
credit_out : out std_logic_vector(2 downto 0) -- status output (hamming results status)
);
end HAM_DEC;
architecture HAM_DEC of HAM_DEC is
begin
process(data_in, parity_in)
--overall mod-2 of all bits
variable P0 : Std_logic;
--syndrome
variable Synd : Std_logic_vector(5 downto 1);
begin
--calculate overall parity of all bits---------
P0 := xor_reduce(data_in & parity_in);
----------------------------------------------
--generate each syndrome bit C1 to C4---------------------------
Synd(1) := xor_reduce((data_in and MaskP1) & parity_in(1));
Synd(2) := xor_reduce((data_in and MaskP2) & parity_in(2));
Synd(3) := xor_reduce((data_in and MaskP4) & parity_in(3));
Synd(4) := xor_reduce((data_in and MaskP8) & parity_in(4));
Synd(5) := xor_reduce((data_in and MaskP16) & parity_in(5));
----------------------------------------------------------------
if (Synd = "00000") and (P0 = '0') then --no errors
credit_out <= NE;
data_out <= data_in;
parity_out <= parity_in;
null; --accept default o/p's assigned above
elsif P0 = '1' then --single error (or odd no of errors!)
credit_out <= EC;
data_out <= data_in;
parity_out <= parity_in;
--correct single error
case to_integer(unsigned(Synd)) is
when 0 => parity_out(0) <= not parity_in(0);
when 1 => parity_out(1) <= not parity_in(1);
when 2 => parity_out(2) <= not parity_in(2);
when 3 => data_out(0) <= not data_in(0);
when 4 => parity_out(3) <= not parity_in(3);
when 5 => data_out(1) <= not data_in(1);
when 6 => data_out(2) <= not data_in(2);
when 7 => data_out(3) <= not data_in(3);
when 8 => parity_out(4) <= not parity_in(4);
when 9 => data_out(4) <= not data_in(4);
when 10 => data_out(5) <= not data_in(5);
when 11 => data_out(6) <= not data_in(6);
when 12 => data_out(7) <= not data_in(7);
when 13 => data_out(8) <= not data_in(8);
when 14 => data_out(9) <= not data_in(9);
when 15 => data_out(10) <= not data_in(10);
when 16 => parity_out(5) <= not parity_in(5);
when 17 => data_out(11) <= not data_in(11);
when 18 => data_out(12) <= not data_in(12);
when 19 => data_out(13) <= not data_in(13);
when 20 => data_out(14) <= not data_in(14);
when 21 => data_out(15) <= not data_in(15);
when others => data_out <= "0000000000000000"; parity_out <= "000000";
end case;
elsif (P0 = '0') and (Synd /= "00000") then --double error
credit_out <= ED;
data_out <= "0000000000000000";
parity_out <= "000000";
end if;
end process;
end HAM_DEC; | lgpl-3.0 | ac0283af3752b3c30b6cc46ff922abdf | 0.52344 | 3.211366 | false | false | false | false |
SWORDfpga/ComputerOrganizationDesign | labs/lab08/lab08/ipcore_dir/ROM_D/simulation/ROM_D_tb_synth.vhd | 8 | 6,921 |
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: ROM_D_tb_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.ROM_D_TB_PKG.ALL;
ENTITY ROM_D_tb_synth IS
GENERIC (
C_ROM_SYNTH : INTEGER := 0
);
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ROM_D_tb_synth;
ARCHITECTURE ROM_D_synth_ARCH OF ROM_D_tb_synth IS
COMPONENT ROM_D_exdes
PORT (
SPO : OUT STD_LOGIC_VECTOR(32-1 downto 0);
A : IN STD_LOGIC_VECTOR(10-1-(4*0*boolean'pos(10>4)) downto 0)
:= (OTHERS => '0')
);
END COMPONENT;
CONSTANT STIM_CNT : INTEGER := if_then_else(C_ROM_SYNTH = 0, 8, 22);
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i : STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ADDR: STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDR_R: STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL SPO: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL SPO_R: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
ROM_D_TB_STIM_GEN_INST:ENTITY work.ROM_D_TB_STIM_GEN
GENERIC MAP( C_ROM_SYNTH => C_ROM_SYNTH
)
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
A => ADDR,
DATA_IN => SPO_R,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(STIM_CNT);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(ADDR(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW + 1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
SPO_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
SPO_R <= SPO AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDR_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDR_R <= ADDR AFTER 50 ns;
END IF;
END IF;
END PROCESS;
DMG_PORT: ROM_D_exdes PORT MAP (
SPO => SPO,
A => ADDR_R
);
END ARCHITECTURE;
| gpl-3.0 | 8d67db17a4618553f5a4c6b919a31505 | 0.573617 | 3.757329 | false | false | false | false |
dpolad/dlx | DLX_vhd/a.i.a.b-SHIFTER.vhd | 2 | 2,397 | library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.myTypes.all;
--possibile instructions: sll, slli, srl, srli, sra, srai
--00 SLL SLLI
--01 SRL SRLI
--10 SRA SRAI
entity shifter is
port( A : in std_logic_vector(31 downto 0);
B : in std_logic_vector(4 downto 0);
LOGIC_ARITH : in std_logic; -- 0 = logic, 1 = arith
LEFT_RIGHT : in std_logic; -- 0 = left, 1 = right
OUTPUT : out std_logic_vector(31 downto 0)
);
end shifter;
architecture behavioral of shifter is
begin
SHIFT: process (A, B, LOGIC_ARITH, LEFT_RIGHT ) is
begin
if LEFT_RIGHT = '0' then
if LOGIC_ARITH = '0' then
OUTPUT <= to_StdLogicVector((to_bitvector(A)) sll (conv_integer(B)));
end if;
else
if LOGIC_ARITH = '0' then
OUTPUT <= to_StdLogicVector((to_bitvector(A)) srl (conv_integer(B)));
else
OUTPUT <= to_StdLogicVector((to_bitvector(A)) sra (conv_integer(B)));
end if;
end if;
end process;
end architecture behavioral;
architecture struct of shifter is
component shift_firstLevel is
port(A : in std_logic_vector(31 downto 0);
sel : in std_logic_vector(1 downto 0);
mask00 : out std_logic_vector(38 downto 0);
mask08 : out std_logic_vector(38 downto 0);
mask16 : out std_logic_vector(38 downto 0));
end component;
component shift_secondLevel is
port(sel : in std_logic_vector(1 downto 0);
mask00 : in std_logic_vector(38 downto 0);
mask08 : in std_logic_vector(38 downto 0);
mask16 : in std_logic_vector(38 downto 0);
Y : out std_logic_vector(38 downto 0));
end component;
component shift_thirdLevel is
port(sel : in std_logic_vector(2 downto 0);
A : in std_logic_vector(38 downto 0);
Y : out std_logic_vector(31 downto 0));
end component;
signal m0, m8, m16, y : std_logic_vector(38 downto 0);
signal s3 : std_logic_vector(2 downto 0);
signal sel : std_logic_vector(1 downto 0);
begin
sel <= LOGIC_ARITH&LEFT_RIGHT;
process(sel, s3, B, A)
begin
case sel is
when "00" => s3 <= B(2 downto 0);
when "01" => s3 <= not(B(2 downto 0));
when "11" => s3 <= not(B(2 downto 0));
when others => s3 <= "XXX";
end case;
end process;
IL : shift_firstLevel port map(A, sel, m0, m8, m16);
IIL : shift_secondLevel port map(B(4 downto 3), m0, m8, m16, y);
IIIL : shift_thirdLevel port map(s3, y, OUTPUT);
end struct;
| bsd-2-clause | fc4d9ed9734c9d3512b100f7050117f6 | 0.655403 | 2.870659 | false | false | false | false |
TimingKeepers/gen-ugr-cores | modules/wishbone/wb_i2c_arb/wb_i2c_arbiter.vhd | 1 | 11,159 | -------------------------------------------------------------------------------
-- Title : WB I2C Bus Arbiter
-- Project : White Rabbit Project
-------------------------------------------------------------------------------
-- File : wb_i2c_arbiter.vhd
-- Author : Miguel Jimenez Lopez
-- Company : UGR
-- Created : 2015-08-06
-- Last update: 2015-08-06
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
--
-- This component allows to share a single I2C bus for many masters in a simple
-- way.
--
-------------------------------------------------------------------------------
-- TODO:
-------------------------------------------------------------------------------
--
-- Copyright (c) 2015 UGR
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library UNISIM;
use UNISIM.vcomponents.all;
library work;
use work.i2c_arb_wbgen2_pkg.all;
use work.i2c_arb_pkg.all;
use work.wishbone_pkg.all;
entity wb_i2c_arbiter is
generic (
g_num_inputs : natural range 2 to 32 := 2;
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_enable_bypass_mode : boolean := true;
g_enable_oen : boolean := false
);
port (
-- Clock & Reset
clk_i : in std_logic;
rst_n_i : in std_logic;
-- I2C input buses
input_sda_i : in std_logic_vector(g_num_inputs-1 downto 0);
input_sda_o : out std_logic_vector(g_num_inputs-1 downto 0);
input_sda_oen : in std_logic_vector(g_num_inputs-1 downto 0);
input_scl_i : in std_logic_vector(g_num_inputs-1 downto 0);
input_scl_o : out std_logic_vector(g_num_inputs-1 downto 0);
input_scl_oen : in std_logic_vector(g_num_inputs-1 downto 0);
-- I2C output bus
output_sda_i : in std_logic;
output_sda_o : out std_logic;
output_sda_oen : out std_logic;
output_scl_i : in std_logic;
output_scl_o : out std_logic;
output_scl_oen : out std_logic;
-- WB Slave bus
wb_adr_i : in std_logic_vector(31 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic
);
end wb_i2c_arbiter;
architecture struct of wb_i2c_arbiter is
-- WB signals
signal wb_in : t_wishbone_slave_in;
signal wb_out : t_wishbone_slave_out;
signal regs_out : t_i2c_arb_out_registers := c_i2c_arb_out_registers_init_value;
-- Signals for the Start Condition Detectors
signal start_cond_detect : std_logic_vector(g_num_inputs-1 downto 0);
--signal start_acks : std_logic_vector(g_num_inputs-1 downto 0);
signal start_ack : std_logic;
-- Signals for the Stop Condition Detectors
signal stop_cond_detect : std_logic_vector(g_num_inputs-1 downto 0);
--signal stop_acks : std_logic_vector(g_num_inputs-1 downto 0);
signal stop_ack : std_logic;
-- Signal for the Main process
signal active_input : integer range g_num_inputs-1 downto 0 := 0;
signal active_input_hotone : integer range g_num_inputs-1 downto 0 := 0;
type arb_state is (ARB_IDLE, ARB_WAIT, ARB_BLOCKED, ARB_RELEASED, ARB_BYPASS);
signal arb_st : arb_state := ARB_IDLE;
signal hotone_enable_input : std_logic;
signal redirector_enable_input : std_logic;
-- Debug stuff
-- attribute MARK_DEBUG : string;
-- attribute MARK_DEBUG of wb_in : signal is "TRUE";
-- attribute MARK_DEBUG of wb_out : signal is "TRUE";
-- attribute MARK_DEBUG of regs_out : signal is "TRUE";
-- attribute MARK_DEBUG of start_cond_detect : signal is "TRUE";
-- attribute MARK_DEBUG of start_ack : signal is "TRUE";
-- attribute MARK_DEBUG of stop_cond_detect : signal is "TRUE";
-- attribute MARK_DEBUG of stop_ack : signal is "TRUE";
-- attribute MARK_DEBUG of active_input : signal is "TRUE";
-- attribute MARK_DEBUG of active_input_hotone : signal is "TRUE";
-- attribute MARK_DEBUG of arb_st : signal is "TRUE";
-- attribute MARK_DEBUG of hotone_enable_input : signal is "TRUE";
-- attribute MARK_DEBUG of redirector_enable_input : signal is "TRUE";
begin
-- WB Adapter & Regs
U_Adapter : wb_slave_adapter
generic map (
g_master_use_struct => true,
g_master_mode => CLASSIC,
g_master_granularity => WORD,
g_slave_use_struct => false,
g_slave_mode => g_interface_mode,
g_slave_granularity => g_address_granularity)
port map (
clk_sys_i => clk_i,
rst_n_i => rst_n_i,
master_i => wb_out,
master_o => wb_in,
sl_adr_i => wb_adr_i,
sl_dat_i => wb_dat_i,
sl_sel_i => wb_sel_i,
sl_cyc_i => wb_cyc_i,
sl_stb_i => wb_stb_i,
sl_we_i => wb_we_i,
sl_dat_o => wb_dat_o,
sl_ack_o => wb_ack_o,
sl_stall_o => wb_stall_o);
U_WB_SLAVE : wb_i2c_arb_slave
port map (
rst_n_i => rst_n_i,
clk_sys_i => clk_i,
wb_dat_i => wb_in.dat,
wb_dat_o => wb_out.dat,
wb_cyc_i => wb_in.cyc,
wb_sel_i => wb_in.sel,
wb_stb_i => wb_in.stb,
wb_we_i => wb_in.we,
wb_ack_o => wb_out.ack,
wb_stall_o => wb_out.stall,
regs_o => regs_out
);
-- Start & Stop detectors
ss_detectors : for I in 0 to g_num_inputs-1 generate
ss: i2c_arbiter_ss_detector
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
input_sda_i => input_sda_i(I),
input_scl_i => input_scl_i(I),
start_ack_i => start_ack,
stop_ack_i => stop_ack,
start_state_o => start_cond_detect(I),
stop_state_o => stop_cond_detect(I)
);
end generate ss_detectors;
-- I2C Redirector
I2C_REDIRECTOR: i2c_arbiter_redirector
generic map (
g_num_inputs => g_num_inputs,
g_enable_oen => g_enable_oen
)
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
enable_i => '1',
input_sda_i => input_sda_i,
input_sda_o => input_sda_o,
input_sda_oen => input_sda_oen,
input_scl_i => input_scl_i,
input_scl_o => input_scl_o,
input_scl_oen => input_scl_oen,
output_sda_i => output_sda_i,
output_sda_o => output_sda_o,
output_sda_oen => output_sda_oen,
output_scl_i => output_scl_i,
output_scl_o => output_scl_o,
output_scl_oen => output_scl_oen,
input_enabled_i => redirector_enable_input,
input_idx_enabled_i => active_input
);
-- I2C Hotone decoder
I2C_HOTONE_DEC: i2c_arbiter_hotone_dec
generic map (
g_num_inputs => g_num_inputs
)
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
enable_i => '1',
start_state_i => start_cond_detect,
input_enabled_o => hotone_enable_input,
input_idx_enabled_o => active_input_hotone
);
-- Mux for the I2C Redirector
redirector_enable_input <= '1' when g_enable_bypass_mode and regs_out.cr_bypass_mode_o = '1' else hotone_enable_input;
-- Active_input Reg
active_input_idx_process: process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
active_input <= 0;
elsif arb_st = ARB_WAIT then
if g_enable_bypass_mode and regs_out.cr_bypass_mode_o = '1' then
active_input <= to_integer(signed(regs_out.cr_bypass_src_o));
elsif hotone_enable_input = '1' then
active_input <= active_input_hotone;
end if;
end if;
end if;
end process active_input_idx_process;
-- Start/Stop Ack process
start_stop_ack_process : process(arb_st,stop_cond_detect,active_input)
begin
case arb_st is
when ARB_IDLE =>
stop_ack <= '0';
start_ack <= '0';
when ARB_WAIT =>
stop_ack <= '0';
start_ack <= '0';
when ARB_BLOCKED =>
if stop_cond_detect(active_input) = '1' then
stop_ack <= '1';
start_ack <= '1';
else
stop_ack <= '0';
start_ack <= '0';
end if;
when ARB_RELEASED =>
stop_ack <= '0';
start_ack <= '0';
when ARB_BYPASS =>
stop_ack <= '1';
start_ack <= '1';
when others =>
stop_ack <= '0';
start_ack <= '0';
end case;
end process start_stop_ack_process;
-- FSM process
main_state : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
arb_st <= ARB_IDLE;
else
case arb_st is
when ARB_IDLE =>
arb_st <= ARB_WAIT;
when ARB_WAIT =>
if g_enable_bypass_mode and regs_out.cr_bypass_mode_o = '1' then
arb_st <= ARB_BYPASS;
elsif hotone_enable_input = '1' then
arb_st <= ARB_BLOCKED;
end if;
when ARB_BLOCKED =>
if stop_cond_detect(active_input) = '1' then
arb_st <= ARB_RELEASED;
end if;
when ARB_RELEASED =>
arb_st <= ARB_IDLE;
when ARB_BYPASS =>
if g_enable_bypass_mode and regs_out.cr_bypass_mode_o = '0' then
arb_st <= ARB_RELEASED;
end if;
when others =>
arb_st <= ARB_IDLE;
end case;
end if;
end if;
end process main_state;
end struct;
| gpl-2.0 | a55403260534f74c470c5afbb8d1884c | 0.519401 | 3.379467 | false | false | false | false |
MAV-RT-testbed/MAV-testbed | Syma_Flight_Final/Syma_Flight_Final.srcs/sources_1/ipshared/rcs.ei.tum.de/Syma_Ctrl_core_v1_2/5d78a94c/hdl/Syma_Ctrl_core_v1_1_S01_AXI.vhd | 2 | 19,746 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Syma_Ctrl_Core_v1_1_S01_AXI is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 5
);
port (
-- Users to add ports here
PPM_INPUT : in std_logic;
SAMPLE_CLOCK : in std_logic;
INTR_SINGLE : out std_logic;
INTR_COMPLETE: out std_logic;
-- Debugging:
-- ppm_sample_dbg : inout std_logic_vector (1 downto 0) := "00";
-- counter_dbg : inout unsigned (31 downto 0) := x"00_00_00_00";
-- reg_nr_dbg : inout unsigned (3 downto 0) := "0000";
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write address (issued by master, acceped by Slave)
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type. This signal indicates the
-- privilege and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
S_AXI_AWREADY : out std_logic;
-- Write data (issued by master, acceped by Slave)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the channel
-- is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address (issued by master, acceped by Slave)
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether the
-- transaction is a data access or an instruction access.
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
S_AXI_ARREADY : out std_logic;
-- Read data (issued by slave)
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the
-- read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is
-- signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic
);
end Syma_Ctrl_Core_v1_1_S01_AXI;
architecture arch_imp of Syma_Ctrl_Core_v1_1_S01_AXI is
-- AXI4LITE signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
-- Example-specific design signals
-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
-- ADDR_LSB = 2 for 32 bits (n downto 2)
-- ADDR_LSB = 3 for 64 bits (n downto 3)
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := 2;
------------------------------------------------
---- Signals for user logic register space example
--------------------------------------------------
---- Number of Slave Registers 8
signal slv_reg0 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg1 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg2 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg3 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg4 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg5 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg6 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg7 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg_rden : std_logic;
signal slv_reg_wren : std_logic;
signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal byte_index : integer;
signal ppm_out_cnt_1 : STD_LOGIC_VECTOR (31 downto 0);
signal ppm_out_cnt_2 : STD_LOGIC_VECTOR (31 downto 0);
signal ppm_out_cnt_3 : STD_LOGIC_VECTOR (31 downto 0);
signal ppm_out_cnt_4 : STD_LOGIC_VECTOR (31 downto 0);
signal ppm_out_cnt_5 : STD_LOGIC_VECTOR (31 downto 0);
signal ppm_out_cnt_6 : STD_LOGIC_VECTOR (31 downto 0);
signal ppm_out_cnt_7 : STD_LOGIC_VECTOR (31 downto 0);
signal ppm_out_cnt_8 : STD_LOGIC_VECTOR (31 downto 0);
component ppm_decoder is
Port (
clk : in std_logic;
ppm_in : in STD_LOGIC;
ppm_out_1 : out STD_LOGIC_VECTOR (31 downto 0);
ppm_out_2 : out STD_LOGIC_VECTOR (31 downto 0);
ppm_out_3 : out STD_LOGIC_VECTOR (31 downto 0);
ppm_out_4 : out STD_LOGIC_VECTOR (31 downto 0);
ppm_out_5 : out STD_LOGIC_VECTOR (31 downto 0);
ppm_out_6 : out STD_LOGIC_VECTOR (31 downto 0);
ppm_out_7 : out STD_LOGIC_VECTOR (31 downto 0);
ppm_out_8 : out STD_LOGIC_VECTOR (31 downto 0);
intr_1 : out std_logic := '0';
intr_comp : out std_logic := '0');
-- ppm_sample : inout std_logic_vector (1 downto 0) := "00";
-- counter : inout unsigned (31 downto 0) := x"00_00_00_00";
-- reg_nr : inout unsigned (3 downto 0) := "0000");
end component;
begin
-- I/O Connections assignments
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RVALID <= axi_rvalid;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- slave is ready to accept write address when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_awready <= '1';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1') then
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_wready <= '1';
else
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-- select byte enables of slave registers while writing.
-- These registers are cleared when reset (active low) is applied.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data.
slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
slv_reg4 <= (others => '0');
slv_reg5 <= (others => '0');
slv_reg6 <= (others => '0');
slv_reg7 <= (others => '0');
else
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1') then
case loc_addr is
when b"000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 0
slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 1
slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 2
slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 3
slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 4
slv_reg4(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 5
slv_reg5(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 6
slv_reg6(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 7
slv_reg7(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others =>
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
slv_reg4 <= slv_reg4;
slv_reg5 <= slv_reg5;
slv_reg6 <= slv_reg6;
slv_reg7 <= slv_reg7;
end case;
end if;
end if;
end if;
end process;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_araddr <= (others => '1');
else
if (axi_arready = '0' and S_AXI_ARVALID = '1') then
-- indicates that the slave has acceped the valid read address
axi_arready <= '1';
-- Read Address latching
axi_araddr <= S_AXI_ARADDR;
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
-- Read data is accepted by the master
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and read logic generation
-- Slave register read enable is asserted when valid address is available
-- and the slave is ready to accept the read address.
slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
process (ppm_out_cnt_1, ppm_out_cnt_2, ppm_out_cnt_3, ppm_out_cnt_4, ppm_out_cnt_5, ppm_out_cnt_6, ppm_out_cnt_7, ppm_out_cnt_8, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
-- Address decoding for reading registers
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
case loc_addr is
when b"000" =>
reg_data_out <= ppm_out_cnt_1;
when b"001" =>
reg_data_out <= ppm_out_cnt_2;
when b"010" =>
reg_data_out <= ppm_out_cnt_3;
when b"011" =>
reg_data_out <= ppm_out_cnt_4;
when b"100" =>
reg_data_out <= ppm_out_cnt_5;
when b"101" =>
reg_data_out <= ppm_out_cnt_6;
when b"110" =>
reg_data_out <= ppm_out_cnt_7;
when b"111" =>
reg_data_out <= ppm_out_cnt_8;
when others =>
reg_data_out <= (others => '0');
end case;
end process;
-- Output register or memory read data
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' ) then
axi_rdata <= (others => '0');
else
if (slv_reg_rden = '1') then
-- When there is a valid read address (S_AXI_ARVALID) with
-- acceptance of read address by the slave (axi_arready),
-- output the read dada
-- Read address mux
axi_rdata <= reg_data_out; -- register read data
end if;
end if;
end if;
end process;
-- Add user logic here
ppm_decoder_0 : ppm_decoder
port map (
clk => SAMPLE_CLOCK,
ppm_in => PPM_INPUT,
ppm_out_1 => ppm_out_cnt_1,
ppm_out_2 => ppm_out_cnt_2,
ppm_out_3 => ppm_out_cnt_3,
ppm_out_4 => ppm_out_cnt_4,
ppm_out_5 => ppm_out_cnt_5,
ppm_out_6 => ppm_out_cnt_6,
ppm_out_7 => ppm_out_cnt_7,
ppm_out_8 => ppm_out_cnt_8,
intr_1 => INTR_SINGLE,
intr_comp => INTR_COMPLETE);
--ppm_sample => ppm_sample_dbg,
--counter => counter_dbg,
--reg_nr => reg_nr_dbg);
-- User logic ends
end arch_imp; | gpl-2.0 | ed1b3277cdc71b10aee876eb4ebbf104 | 0.601945 | 3.405657 | false | false | false | false |
Hyperion302/omega-cpu | Core/Control.vhdl | 1 | 12,188 | -- This file is part of the Omega CPU Core
-- Copyright 2015 - 2016 Joseph Shetaye
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as
-- published by the Free Software Foundation, either version 3 of the
-- License, or (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library IEEE;
use IEEE.std_logic_1164.all;
use work.Constants.all;
use IEEE.Numeric_std.all;
entity Control is
port(
CLK : in std_logic;
MemControllerDone : in std_logic;
MemControllerFromRead : in Word;
MemControllerToWrite : out Word;
MemControllerADDR : out Word;
MemControllerEnable : out std_logic;
PortXmit : out Word;
PortRecv : in Word;
PortInstruction : out Word;
PortCPUReady : out std_logic;
PortCPUSending : out std_logic;
PortReady : in std_logic;
PortDone : in std_logic;
PortSending : out std_logic;
IRQ : in std_logic_vector(23 downto 0);
RST : in std_logic;
Instr : out Word;
ProgramCounter : out Word
);
end Control;
architecture Behavioral of Control is
component ALU is
port (
RegisterB : in Word;
RegisterC : in Word;
Instruction : in Word;
RegisterA : out Word;
RegisterD : out Word;
Carry : out std_logic;
OutputReady : out std_logic;
Status : out std_logic_vector(1 downto 0));
end component ALU;
component BranchUnit is
port (
Instruction : in Word;
RegisterA : in Word;
RegisterB : in Word;
NewPC : out Word;
CurrentPC : in Word;
OutputReady : out std_logic);
end component BranchUnit;
component PortController
port (
CLK : in std_logic;
XMit : in word;
Recv : out word;
instruction : in word;
CPUReady : in std_logic;
CPUSending: in std_logic;
PortReady: out std_logic;
Done: out std_logic;
PortSending: out std_logic);
end component;
type MachineState is (Start, WaitForInstrRead,StoreMemOutToInstrR, AdvanceInstr, ALUHandle, ALUSetInstrIn, ALUOutReady, ALUSetOutReg, DecodeOpcode, MemSetInstrIn, MemSetOutReg, SetBranchInputs, ServiceInterrupt, PortSetInstrIn, PortSetOutReg);
type RegisterArray is array(0 to 31) of Word;
signal State : MachineState := Start;
signal registers : RegisterArray := (others => (others => '0'));
signal RegA : Word;
signal RegB : Word;
signal RegC : Word;
signal RegD : Word;
signal RegAOut : Word;
signal RegBOut : Word;
signal RegCOut : Word;
signal RegDOut : Word;
signal ALUStatus : std_logic_vector(1 downto 0);
signal Instr_S : Word := (others => '0');
signal ALUOutputReady : std_logic;
signal BranchNP : Word;
signal BranchOutReady : std_logic;
signal MemControllerEnable_S : std_logic := '0';
signal MemControllerADDR_S : Word := (others => '0');
signal MemControllerToWrite_S : Word := (others => '0');
signal IRQ_S : std_logic_vector(23 downto 0) := (others => '0');
signal ServicingInterrupt : std_logic := '0';
signal PortXMit_s : Word := (others => '0');
signal PortRecv_s : Word := (others => '0');
signal PortCPUReady_s : std_logic := '0';
signal PortCPUSending_s : std_logic := '0';
signal PortReadyPort : std_logic := '0';
signal PortSendingPort : std_logic := '0';
signal PortDone_s : std_logic := '0';
signal Carry : std_logic := '0';
begin -- Behavioral
ALUControl : ALU port map (
RegisterB => RegB,
RegisterA => RegAOut,
RegisterC => RegC,
RegisterD => RegDOut,
Instruction => Instr_S,
OutputReady => ALUOutputReady,
Carry => Carry,
Status => ALUStatus);
BranchUnitControl : BranchUnit port map (
Instruction => Instr_S,
RegisterA => RegA,
RegisterB => RegB,
NewPC => BranchNP,
CurrentPC => Registers(31),
OutputReady => BranchOutReady);
MemControllerEnable <= MemControllerEnable_S;
MemControllerADDR <= MemControllerADDR_S;
MemControllerToWrite <= MemControllerToWrite_S;
PortXMit <= PortXmit_s;
PortRecv_s <= PortRecv;
PortInstruction <= Instr_s;
PortCPUReady <= PortCPUReady_s;
PortCPUSending <= PortCPUSending_s;
PortReadyPort <= PortReady;
PortSending <= PortSendingPort;
ProgramCounter <= registers(31);
process (Registers, Instr_S)
begin -- process
RegA <= Registers(to_integer(unsigned(GetRegisterReferenceA(Instr_S))));
RegB <= Registers(to_integer(unsigned(GetRegisterReferenceB(Instr_S))));
RegC <= Registers(to_integer(unsigned(GetRegisterReferenceC(Instr_S))));
RegD <= Registers(to_integer(unsigned(GetRegisterReferenceD(Instr_S))));
Instr <= Instr_S;
end process;
--process (IRQ)
-- begin -- process
-- IRQ_S <= IRQ_S or IRQ;
-- end process;
StateMachine: process (CLK, RST)
variable ReadValue : integer := 0;
variable ReadValue_D : integer := 0;
variable NextInterrupt : integer := -1;
variable SignExtendedImmediate : std_logic_vector(31 downto 0);
variable ImmediateValue_v : std_logic_vector(15 downto 0);
variable currentOpcode : Opcode;
variable currentOperator : Operator;
begin -- process StateMachine
if RST = '1' then
Registers <= (others => (others => '0'));
State <= Start;
MemControllerEnable_S <= '0';
elsif rising_edge(CLK) then
case State is
when Start =>
if ServicingInterrupt = '0' and IRQ_S /= "000000000000000000000000" then
NextInterrupt := GetIRQ(IRQ_S);
if NextInterrupt /= -1 then
IRQ_S(NextInterrupt) <= '0';
MemControllerADDR_S <= std_logic_vector(unsigned(InterruptTableADDR) + (NextInterrupt * 4));
State <= ServiceInterrupt;
ServicingInterrupt <= '1';
end if;
else
MemControllerADDR_S <= registers(31);
State <= WaitForInstrRead;
end if;
Instr_S <= OpcodeMemory & LoadWord & "00000" & "11111" & "0000000000000000";
MemControllerEnable_S <= '0';
when ServiceInterrupt =>
if MemControllerDone = '1' then
if MemControllerFromRead /= "00000000000000000000000000000000" then
registers(29) <= registers(31);
registers(31) <= MemControllerFromRead;
end if;
State <= Start;
MemControllerEnable_S <= '0';
else
MemControllerEnable_S <= '1';
end if;
when WaitForInstrRead =>
if MemControllerDone = '1' then
Instr_S <= MemControllerFromRead;
registers(31) <= std_logic_vector(unsigned(registers(31)) + 4);
State <= DecodeOpcode;
MemControllerEnable_S <= '0';
else
MemControllerEnable_S <= '1';
end if;
when DecodeOpcode =>
currentOpcode := GetOpcode(Instr_S);
case currentOpcode is
when OpcodeLogical|OpcodeArithmetic|OpcodeShift|OpcodeRelational =>
State <= ALUSetInstrIn;
when OpcodeMemory =>
State <= MemSetInstrIn;
when OpcodeBranch =>
State <= SetBranchInputs;
when OpcodePort =>
State <= PortSetInstrIn;
when others => null;
end case;
if Instr_S = JumpToReg29 then
ServicingInterrupt <= '0';
end if;
MemControllerEnable_S <= '0';
when MemSetInstrIn =>
currentOperator := GetOperator(Instr_S);
case currentOperator is
when LoadByteUnsigned|LoadByteSigned|LoadHalfWordUnsigned|LoadHalfWordSigned|LoadWord =>
--MemControllerADDR_S <= Registers(to_integer(unsigned(GetRegisterReferenceB(Instr_S))));
ImmediateValue_v := GetImmediateValue(Instr_S);
MemControllerADDR_S <= std_logic_vector(to_integer(unsigned(RegB)) + resize(signed(ImmediateValue_v), 32));
if MemControllerDone = '1' then
ReadValue := to_integer(unsigned(GetRegisterReferenceA(Instr_S)));
if ReadValue /= 0 then
Registers(ReadValue) <= MemControllerFromRead;
end if;
State <= Start;
MemControllerEnable_S <= '0';
else
MemControllerEnable_S <= '1';
end if;
when StoreByte|StoreHalfWord|StoreWord =>
--MemControllerADDR_S <= Registers(to_integer(unsigned(GetRegisterReferenceB(Instr_S))));
ImmediateValue_v := GetImmediateValue(Instr_S);
MemControllerADDR_S <= std_logic_vector(to_integer(unsigned(RegB)) + resize(signed(ImmediateValue_v), 32));
MemControllerToWrite_S <= Registers(to_integer(unsigned(GetRegisterReferenceA(Instr_S))));
if MemControllerDone = '1' then
State <= Start;
MemControllerEnable_S <= '0';
else
MemControllerEnable_S <= '1';
end if;
when others => null;
end case;
when PortSetInstrIn =>
currentOperator := GetOperator(Instr_S);
case currentOperator is
when LoadByteUnsigned|LoadByteSigned|LoadHalfWordUnsigned|LoadHalfWordSigned|LoadWord =>
if PortReadyPort = '1' then
ReadValue := to_integer(unsigned(GetRegisterReferenceA(Instr_S)));
if ReadValue /= 0 then
Registers(ReadValue) <= PortRecv_s;
end if;
State <= Start;
PortCPUSending_s <= '0';
PortCPUReady_s <= '0';
else
PortCPUSending_s <= '0';
PortCPUReady_s <= '1';
end if;
when StoreByte|StoreHalfWord|StoreWord =>
if PortDone = '1' then
State <= Start;
PortXMit_s <= (others => '0');
PortCPUSending_s <= '0';
PortCPUReady_s <= '0';
else
PortXMit_s <= Registers(to_integer(unsigned(GetRegisterReferenceA(Instr_S))));
PortCPUSending_s <= '1';
PortCPUReady_s <= '1';
end if;
when others => null;
end case;
when SetBranchInputs =>
if BranchOutReady = '1' then
Registers(31) <= BranchNP;
MemControllerEnable_S <= '0';
State <= Start;
end if;
when ALUSetInstrIn =>
if ALUOutputReady = '1' then
case ALUStatus is
when NormalAOnly =>
ReadValue := to_integer(unsigned(GetRegisterReferenceA(Instr_S)));
if ReadValue /= 0 then
Registers(ReadValue) <= RegAOut;
end if;
Registers(30) <= (0 => Carry, others => '0');
when DivideOverflow =>
-- Fill In!
when NormalAAndD =>
ReadValue := to_integer(unsigned(GetRegisterReferenceA(Instr_S)));
if ReadValue /= 0 then
Registers(ReadValue) <= RegAOut;
end if;
ReadValue_D := to_integer(unsigned(GetRegisterReferenceD(Instr_S)));
if ReadValue_D /= 0 then
Registers(ReadValue_D) <= RegDOut;
end if;
Registers(30) <= (others => '0');
when GenericError =>
-- Fill In!
when others => null;
end case;
end if;
State <= Start;
MemControllerEnable_S <= '0';
when others => null;
end case;
end if;
end process StateMachine;
end Behavioral;
| lgpl-3.0 | 783a1e422ebff8c8a1d6eadba39b3cd1 | 0.587873 | 4.20131 | false | false | false | false |
manosaloscables/vhdl | generador_pixeles/gen_px_tb.vhd | 1 | 1,174 | -- **************************************************************
-- * Banco de prueba para el circuito de generación de píxeles *
-- **************************************************************
library ieee;
use ieee.std_logic_1164.all;
entity gen_px_tb is
end gen_px_tb;
architecture arq_bp of gen_px_tb is
constant T: time := 20 ns; -- Periodo del Reloj
signal clk, rst: std_logic; -- Entradas
signal rgb: std_logic_vector(2 downto 0); -- Salidas
signal hsinc, vsinc: std_logic;
begin
-- Instanciar un circuito de generación de píxeles
unidad_gen_px: entity work.gen_px(arq)
port map(
clk => clk,
rst => rst,
rgb => rgb,
hsinc => hsinc,
vsinc => vsinc
);
-- Reloj
process begin
clk <= '0';
wait for T/2;
clk <= '1';
wait for T/2;
end process;
-- Reinicio
rst <= '0', '1' after T/2;
-- Otros estímulos
process begin
for i in 1 to 1000000 loop
wait until falling_edge(clk);
end loop;
-- Terminar simulación
assert false
report "Simulación Completada"
severity failure;
end process;
end arq_bp; | gpl-3.0 | 81544154f001105f34d49dd40264f587 | 0.525278 | 3.579755 | false | false | false | false |
TimingKeepers/gen-ugr-cores | modules/bridges/tb/wbs2axism_tb.vhd | 1 | 4,955 | -------------------------------------------------------------------------------
-- Title : Testbench for the wb2axism IP core.
-- Project : Misc
-------------------------------------------------------------------------------
-- File : wb2axism_tb.vhd
-- Author : Miguel Jimenez Lopez
-- Company : UGR
-- Created : 2016-04-13
-- Last update: 2016-04-13
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
--
-- It is the testbench for the wb2axism IP core.
--
-------------------------------------------------------------------------------
-- TODO:
-------------------------------------------------------------------------------
--
-- Copyright (c) 2016 UGR
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library UNISIM;
use UNISIM.vcomponents.all;
library work;
use work.wishbone_pkg.all;
use work.bridge_pkg.all;
entity wbs2axism_tb is
end wbs2axism_tb;
architecture struct of wbs2axism_tb is
-- Constants
constant C_CLK_PERIOD : time := 16 ns; -- 62.5 MHz
constant C_ADDRESS_WIDTH : integer := 32;
constant C_DATA_WIDTH : integer := 64;
-- Clock & Reset (neg)
signal clk : std_logic;
signal rst_n : std_logic;
-- WB Slave (memory mapped) interface
signal s_wb_cyc : std_logic;
signal s_wb_stb : std_logic;
signal s_wb_adr : std_logic_vector(C_ADDRESS_WIDTH-1 downto 0);
signal s_wb_dat : std_logic_vector(C_DATA_WIDTH-1 downto 0);
signal s_wb_sel : std_logic_vector((C_DATA_WIDTH/8)-1 downto 0);
signal s_wb_we : std_logic;
signal s_wb_ack : std_logic;
signal s_wb_stall : std_logic;
-- AXI Master (streaming) interface
signal m_axis_tdata : std_logic_vector(C_DATA_WIDTH-1 downto 0);
signal m_axis_tkeep : std_logic_vector((C_DATA_WIDTH/8)-1 downto 0);
signal m_axis_tlast : std_logic;
signal m_axis_tready : std_logic;
signal m_axis_tvalid : std_logic;
signal m_axis_tstrb : std_logic_vector((C_DATA_WIDTH/8)-1 downto 0);
begin
DUT: wbs2axism
generic map(
g_address_width => C_ADDRESS_WIDTH,
g_data_width => C_DATA_WIDTH
)
port map(
-- Clock & Reset (neg)
clk_i => clk,
rst_n_i => rst_n,
-- WB Slave (memory mapped) interface
s_wb_cyc_i => s_wb_cyc,
s_wb_stb_i => s_wb_stb,
s_wb_adr_i => s_wb_adr,
s_wb_dat_i => s_wb_dat,
s_wb_sel_i => s_wb_sel,
s_wb_we_i => s_wb_we,
s_wb_ack_o => s_wb_ack,
s_wb_stall_o => s_wb_stall,
-- AXI Master (streaming) interface
m_axis_tdata_o => m_axis_tdata,
m_axis_tkeep_o => m_axis_tkeep,
m_axis_tlast_o => m_axis_tlast,
m_axis_tready_i => m_axis_tready,
m_axis_tvalid_o => m_axis_tvalid,
m_axis_tstrb_o => m_axis_tstrb
);
clk_process :process
begin
clk <= '0';
wait for C_CLK_PERIOD/2;
clk <= '1';
wait for C_CLK_PERIOD/2;
end process;
data_p : process(clk)
variable cnt : unsigned(C_DATA_WIDTH-1 downto 0) := (others => '0');
begin
if rising_edge(clk) then
if rst_n = '0' then
s_wb_dat <= (others => '0');
cnt := (others => '0');
else
if s_wb_stall = '0' and s_wb_ack = '1' then
cnt := cnt+1;
s_wb_dat <= std_logic_vector(cnt);
end if;
end if;
end if;
end process;
-- Stimulus process
stim_proc: process
begin
rst_n <='0';
wait for 20 ns;
rst_n <='1';
m_axis_tready <= '0';
s_wb_cyc <= '1';
wait for 1 ns;
s_wb_adr <= (others => '0');
s_wb_sel <= (others => '1');
s_wb_we <= '1';
s_wb_stb <= '1';
wait for 3 ns;
m_axis_tready <= '1';
wait for 20 ns;
s_wb_sel <= (others => '0');
wait for 20 ns;
s_wb_sel <= (others => '1');
m_axis_tready <= '0';
wait for 20 ns;
m_axis_tready <= '1';
wait for 300 ns;
s_wb_cyc <= '0';
s_wb_stb <= '0';
wait;
end process;
end struct;
| gpl-2.0 | 6019614dc48fae13d86425d5d3143dab | 0.519879 | 3.196774 | false | false | false | false |
dpolad/dlx | DLX_vhd/a.g-DECODEREGS.vhd | 2 | 2,263 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--use work.myTypes.all;
entity decode_regs is
generic (
SIZE : integer := 32
);
port (
A_i : in std_logic_vector(SIZE - 1 downto 0);
B_i : in std_logic_vector(SIZE - 1 downto 0);
rA_i : in std_logic_vector(4 downto 0);
rB_i : in std_logic_vector(4 downto 0);
rC_i : in std_logic_vector(4 downto 0);
IMM_i : in std_logic_vector(SIZE - 1 downto 0);
ALUW_i : in std_logic_vector(12 downto 0);
A_o : out std_logic_vector(SIZE - 1 downto 0);
B_o : out std_logic_vector(SIZE - 1 downto 0);
rA_o : out std_logic_vector(4 downto 0);
rB_o : out std_logic_vector(4 downto 0);
rC_o : out std_logic_vector(4 downto 0);
IMM_o : out std_logic_vector(SIZE - 1 downto 0);
ALUW_o : out std_logic_vector(12 downto 0);
stall_i : in std_logic;
clk : in std_logic;
rst : in std_logic
);
end decode_regs;
architecture struct of decode_regs is
component ff32_en
generic(
SIZE : integer
);
port(
D : in std_logic_vector(SIZE - 1 downto 0);
Q : out std_logic_vector(SIZE - 1 downto 0);
en : in std_logic;
clk : in std_logic;
rst : in std_logic
);
end component;
signal enable : std_logic;
begin
--enable signal is a signal received from CU that can stop the entire stage of the pipeline
enable <= not stall_i;
-- first operand from RF
A: ff32_en generic map(
SIZE => 32
)port map(
D => A_i,
Q => A_o,
en => enable,
clk => clk,
rst => rst);
-- second operand from RF
B: ff32_en generic map(
SIZE => 32
)port map(
D => B_i,
Q => B_o,
en => enable,
clk => clk,
rst => rst);
-- index of rA
rA: ff32_en generic map(
SIZE => 5
)port map(
D => rA_i,
Q => rA_o,
en => enable,
clk => clk,
rst => rst);
-- index of rB
rB: ff32_en generic map(
SIZE => 5
)port map(
D => rB_i,
Q => rB_o,
en => enable,
clk => clk,
rst => rst);
-- index of rC
rC: ff32_en generic map(
SIZE => 5
)port map(
D => rC_i,
Q => rC_o,
en => enable,
clk => clk,
rst => rst);
-- immediate value
IMM: ff32_en generic map(
SIZE => 32
)port map(
D => IMM_i,
Q => IMM_o,
en => enable,
clk => clk,
rst => rst);
ALUW: ff32_en generic map(
SIZE => 13
)port map(
D => ALUW_i,
Q => ALUW_o,
en => enable,
clk => clk,
rst => rst);
end struct;
| bsd-2-clause | 417f9eff98ffa4dbee93f7d82c878f99 | 0.605833 | 2.274372 | false | false | false | false |
SWORDfpga/ComputerOrganizationDesign | labs/lab12/lab12/ipcore_dir/RAM_B/example_design/RAM_B_prod.vhd | 10 | 10,063 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: RAM_B_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : kintex7
-- C_XDEVICEFAMILY : kintex7
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 0
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : RAM_B.mif
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 32
-- C_READ_WIDTH_A : 32
-- C_WRITE_DEPTH_A : 1024
-- C_READ_DEPTH_A : 1024
-- C_ADDRA_WIDTH : 10
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 32
-- C_READ_WIDTH_B : 32
-- C_WRITE_DEPTH_B : 1024
-- C_READ_DEPTH_B : 1024
-- C_ADDRB_WIDTH : 10
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY RAM_B_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END RAM_B_prod;
ARCHITECTURE xilinx OF RAM_B_prod IS
COMPONENT RAM_B_exdes IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : RAM_B_exdes
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
| gpl-3.0 | 26a1c683cf00dde7108023b358f5164c | 0.491802 | 3.818975 | false | false | false | false |
dpolad/dlx | DLX_vhd/useless/fake_mult.vhd | 1 | 1,064 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fake_mult is
generic (
DATA_SIZE : integer := 32);
port (
IN1 : in std_logic_vector(DATA_SIZE - 1 downto 0);
IN2 : in std_logic_vector(DATA_SIZE - 1 downto 0);
DOUT : out std_logic_vector(DATA_SIZE - 1 downto 0);
stall_o : out std_logic;
enable : in std_logic;
Clock : in std_logic;
Reset : in std_logic
);
end fake_mult;
architecture Bhe of fake_mult is
signal count : unsigned(2 downto 0);
begin
process(enable,Reset,Clock)
begin
if Reset = '1' then
DOUT <= X"00000000";
stall_o <= '0';
count <= "000";
else
if enable = '1' and enable'event then
stall_o <= '1';
count <= "111";
DOUT <= "00000000000000000000000000001000";
end if;
if enable = '1' and Clock = '1' and clock'event then
DOUT <= "00000000000000000000000000000"&std_logic_vector(count);
if count/="000" then
count <= count-1;
end if;
if count = "000" then
stall_o <= '0';
DOUT <= X"11111111";
end if;
end if;
end if;
end process;
end Bhe; | bsd-2-clause | 2078f19f78e9aa7f13ad5ef02f5e3326 | 0.633459 | 2.955556 | false | false | false | false |
TimingKeepers/gen-ugr-cores | modules/wishbone/wb_obp/OBP_pkg.vhd | 1 | 5,719 | -- Title : On Board Programer Package (OBP, WB-debuger simplification)
-- Project : OBP
-------------------------------------------------------------------------------
-- File : obp.vhd
-- Author : Jose Jimenez Montañez, Miguel Jimenez Lopez
-- Company : University of Granada (UGR)
-- Created : 2014-06-12
-- Last update: 2014-06-12
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-- OBP is a HDL module implementing a On Board Programer component that allows
-- to program the LM32 inside the WRPC via USB port. In addition, some debug
-- functions have been added (to read/write WB registers, show the SDB structure, etc).
-------------------------------------------------------------------------------
--
-- Copyright (c) 2014, University of Granada (UGR)
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-06-12 1.0 JJimenez,klyone Created and first version
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.genram_pkg.all;
use work.wishbone_pkg.all;
package obp_pkg is
function f_xwb_dpram_obp(g_size : natural) return t_sdb_device;
function f_xwb_cram_obp(g_size : natural) return t_sdb_device;
function f_secobp_layout(g_size : natural) return t_sdb_record_array;
component OBP is
generic(
g_dpram_initf : string := "obp.ram";
g_dpram_size : integer := 20480/4;
g_cram_size : integer := 20480/4;
g_bridge_sdb : t_sdb_bridge
);
port(
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
enable_obp : in std_logic;
wbs_i : in t_wishbone_slave_in;
wbs_o : out t_wishbone_slave_out;
wbm_i : in t_wishbone_master_in;
wbm_o : out t_wishbone_master_out
);
end component;
constant c_obp_wb_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"000000000000000f", -- I think this is overestimated
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000099",
version => x"00000001",
date => x"20000101", -- UNKNOWN
name => "OBP-WBS ")));
constant c_secobp_sdb_address : t_wishbone_address := x"00030000";
end obp_pkg;
package body obp_pkg is
function f_xwb_dpram_obp(g_size : natural) return t_sdb_device
is
variable result : t_sdb_device;
begin
result.abi_class := x"0001"; -- RAM device
result.abi_ver_major := x"01";
result.abi_ver_minor := x"00";
result.wbd_width := x"7"; -- 32/16/8-bit supported
result.wbd_endian := c_sdb_endian_big;
result.sdb_component.addr_first := (others => '0');
result.sdb_component.addr_last := std_logic_vector(to_unsigned(g_size*4-1, 64));
result.sdb_component.product.vendor_id := x"000000000000CE42"; -- CERN
result.sdb_component.product.device_id := x"66554433";
result.sdb_component.product.version := x"00000001";
result.sdb_component.product.date := x"20120305";
result.sdb_component.product.name := "WB4-BlockRAM OBP ";
return result;
end f_xwb_dpram_obp;
function f_xwb_cram_obp(g_size : natural) return t_sdb_device
is
variable result : t_sdb_device;
begin
result.abi_class := x"0001"; -- RAM device
result.abi_ver_major := x"01";
result.abi_ver_minor := x"00";
result.wbd_width := x"7"; -- 32/16/8-bit supported
result.wbd_endian := c_sdb_endian_big;
result.sdb_component.addr_first := (others => '0');
result.sdb_component.addr_last := std_logic_vector(to_unsigned(g_size*4-1, 64));
result.sdb_component.product.vendor_id := x"000000000000CE42"; -- CERN
result.sdb_component.product.device_id := x"66554432";
result.sdb_component.product.version := x"00000001";
result.sdb_component.product.date := x"20120305";
result.sdb_component.product.name := "WB4-BlockRAM OBP C ";
return result;
end f_xwb_cram_obp;
function f_secobp_layout(g_size : natural) return t_sdb_record_array
is
variable result : t_sdb_record_array(1 downto 0);
begin
result(0) := f_sdb_embed_device(f_xwb_cram_obp(g_size), x"00000000");
result(1) := f_sdb_embed_device(c_obp_wb_sdb, x"00020000");
return result;
end f_secobp_layout;
end obp_pkg;
| gpl-2.0 | 3cf03aef8028d185d275614ed6f0de67 | 0.579224 | 3.536178 | false | false | false | false |
freecores/ternary_adder | vhdl/tb_ternary_adder.vhd | 1 | 3,180 | ---------------------------------------------------------------------------------------------
-- Author: Martin Kumm
-- Contact: [email protected]
-- License: LGPL
-- Date: 04.04.2013
--
-- Description:
-- Testbench for testing a single ternary adder component
---------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all; -- for uniform, trunc functions
entity tb_ternary_adder is
generic(
input_word_size : integer := 15;
subtract_y : boolean := false;
subtract_z : boolean := true;
use_output_ff : boolean := false
);
end tb_ternary_adder;
architecture tb_ternary_adder_arch of tb_ternary_adder is
signal clk, rst : std_logic := '0';
signal x,y,z : std_logic_vector(input_word_size-1 downto 0) := (others => '0');
signal sum : std_logic_vector(input_word_size+1 downto 0) := (others => '0');
signal sum_ref,sum_dut: integer := 0;
begin
dut: entity work.ternary_adder
generic map (
input_word_size => input_word_size,
subtract_y => subtract_y,
subtract_z => subtract_z,
use_output_ff => use_output_ff
)
port map (
clk_i => clk,
rst_i => rst,
x_i => x,
y_i => y,
z_i => z,
sum_o => sum
);
clk <= not clk after 5 ns; -- 100 MHz
rst <= '1', '0' after 5 ns;
process
variable seed1,seed2: positive;
variable rand : real;
variable x_int,y_int,z_int : integer;
begin
uniform(seed1, seed2, rand);
x_int := integer(trunc(rand*real(2**(input_word_size-2)-1)));
uniform(seed1, seed2, rand);
y_int := integer(trunc(rand*real(2**(input_word_size-2)-1)));
uniform(seed1, seed2, rand);
z_int := integer(trunc(rand*real(2**(input_word_size-2)-1)));
x <= std_logic_vector(to_signed(x_int, x'length)); -- rescale, quantize and convert
y <= std_logic_vector(to_signed(y_int, y'length)); -- rescale, quantize and convert
z <= std_logic_vector(to_signed(z_int, z'length)); -- rescale, quantize and convert
wait until clk'event and clk='1';
end process;
process(clk,rst,x,y,z)
variable y_sgn,z_sgn,sum_ref_unsync : integer;
begin
if subtract_y = true then
y_sgn := -1*to_integer(signed(y));
else
y_sgn := to_integer(signed(y));
end if;
if subtract_z = true then
z_sgn := -1*to_integer(signed(z));
else
z_sgn := to_integer(signed(z));
end if;
sum_ref_unsync := to_integer(signed(x)) + y_sgn + z_sgn;
if use_output_ff = false then
sum_ref <= sum_ref_unsync;
else
if clk'event and clk='1' then
sum_ref <= sum_ref_unsync;
end if;
end if;
end process;
process(clk,rst,sum_ref)
begin
end process;
sum_dut <= to_integer(signed(sum));
process
begin
wait for 50 ns;
loop
wait until clk'event and clk='0';
assert (sum_dut = sum_ref) report "Test failure" severity failure;
wait until clk'event and clk='1';
end loop;
end process;
end architecture; | lgpl-3.0 | f964e6decff7fce523bad73cea9bc738 | 0.554403 | 3.333333 | false | false | false | false |
rodrigofegui/UnB | 2017.1/Organização e Arquitetura de Computadores/Trabalhos/Trabalho 3/Codificação/alu/alu_tb.vhd | 1 | 4,715 | --Declaracao de bibliotecas
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY alu_tb IS
generic (DATA_WIDTH : natural := 32); --tamanho de 32 bits para dados de input e output
END alu_tb;
ARCHITECTURE alu_arch OF alu_tb IS
--sinais necessarios para o process do testbench
SIGNAL S_input1 : std_logic_vector(DATA_WIDTH -1 downto 0);
SIGNAL S_input2 : std_logic_vector(DATA_WIDTH -1 downto 0);
SIGNAL S_operation : std_logic_vector(3 downto 0);
SIGNAL S_output : std_logic_vector(DATA_WIDTH -1 downto 0);
SIGNAL S_zero : std_logic;
SIGNAL S_negative : std_logic;
SIGNAL S_carry : std_logic;
SIGNAL S_overflow : std_logic;
COMPONENT alu --declaracao do componente alu(ula) que sera submetida a teste
PORT (
input1, input2 : in std_logic_vector(DATA_WIDTH -1 downto 0);
operation : in std_logic_vector(3 downto 0);
output : out std_logic_vector(DATA_WIDTH -1 downto 0);
zero, negative : out std_logic;
carry, overflow : out std_logic
);
END COMPONENT;
BEGIN
i1 : alu PORT MAP(--mapeamento dos sinais com as portas do componente alu
input1 => S_input1,
input2 => S_input2,
operation => S_operation,
output => S_output,
zero => S_zero,
negative => S_negative,
carry => S_carry,
overflow => S_overflow);
Stimulus : PROCESS --processo de testbench que gera estimulos para os sinais
variable op1,op2 : integer; --variaveis para armazenar valores inteiros para posterior conversao
BEGIN
-- Testar operacoes nao aritmeticas
op1 := 19;
op2 := 13;
--conversao dos inteiros para std_logic_vector
S_input1 <= std_logic_vector(to_signed(op1, S_input1'length));
S_input2 <= std_logic_vector(to_signed(op2, S_input2'length));
--Teste AND
S_operation <= "0000"; wait for 5 ps;
--Teste OR
S_operation <= "0001"; wait for 5 ps;
--Teste SLT
--Primeiro teste resultando SLT = 0 (op1>op2)
S_operation <= "0100"; wait for 5 ps;
--Segundo teste resultando SLT = 1 (op1<op2)
op2 := 53;
S_input2 <= std_logic_vector(to_signed(op2, S_input2'length));
wait for 5 ps;
--Teste NOR
S_operation <= "0101"; wait for 5 ps;
--Teste XOR
S_operation <= "0110"; wait for 5 ps;
-- novos inputs para testar shifts(sll,srl e sra)
S_input1 <= "10100100000000000010000000010011";
S_input2 <= "00000000000000000000000000000101";
--Teste SLL
S_operation <= "0111"; wait for 5 ps;
--Teste SRL
S_operation <= "1000"; wait for 5 ps;
--Teste SRA
S_operation <= "1001"; wait for 5 ps;
-- Testar operacoes aritmeticas (ADD e SUB)
--ADD com resultado positivo
op1 := 19;
op2 := 13;
S_input1 <= std_logic_vector(to_signed(op1, S_input1'length));
S_input2 <= std_logic_vector(to_signed(op2, S_input2'length));
S_operation <= "0010"; wait for 5 ps;
--ADD com resultado zero
op2 := -19;
S_input2 <= std_logic_vector(to_signed(op2, S_input2'length));
wait for 5 ps;
--ADD com resultado negativo
op2 := -30;
S_input2 <= std_logic_vector(to_signed(op2, S_input2'length));
wait for 5 ps;
--ADD com overflow e carry = 1
--caso onde somamos dois numeros negativos e obtemos resultado positivo
op1 := -1073741824;
op2 := -1342177280;
S_input1 <= std_logic_vector(to_signed(op1, S_input1'length));
S_input2 <= std_logic_vector(to_signed(op2, S_input2'length));
wait for 5 ps;
--SUB com resultado positivo
op1 := 19;
op2 := 13;
S_input1 <= std_logic_vector(to_signed(op1, S_input1'length));
S_input2 <= std_logic_vector(to_signed(op2, S_input2'length));
S_operation <= "0011"; wait for 5 ps;
--SUB com resultado zero
op2 := 19;
S_input2 <= std_logic_vector(to_signed(op2, S_input2'length));
wait for 5 ps;
--SUB com resultado negativo
op2 := 30;
S_input2 <= std_logic_vector(to_signed(op2, S_input2'length));
wait for 5 ps;
--SUB com overflow
--caso overflow quando subtraimos numero positivo de um negativo e obtemos resultado positivo
op1 := -536870912;
op2 := 1879048192;
S_input1 <= std_logic_vector(to_signed(op1, S_input1'length));
S_input2 <= std_logic_vector(to_signed(op2, S_input2'length));
wait for 5 ps;
WAIT;
END PROCESS Stimulus; --fim do testbench
END alu_arch; | gpl-3.0 | 8f0df3a302fe707e11153abda23aadfc | 0.600424 | 3.137059 | false | true | false | false |
MAV-RT-testbed/MAV-testbed | Syma_Flight_Final/Syma_Flight_Final.srcs/sources_1/ipshared/xilinx.com/axi_quad_spi_v3_2/c64e9f22/hdl/src/vhdl/cross_clk_sync_fifo_1.vhd | 1 | 93,264 | -------------------------------------------------------------------------------
-- axi_quad_spi.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_quad_spi.vhd
-- Version: v3.0
-- Description: This is the top-level design file for the AXI Quad SPI core.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- History:
-- ~~~~~~
-- SK 19/01/11 -- created v1.00.a version
-- ^^^^^^
-- 1. Created first version of the core.
-- ~~~~~~
-- ~~~~~~
-- SK 12/16/12 -- v3.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.conv_std_logic_vector;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_misc.all;
-- library unsigned is used for overloading of "=" which allows integer to
-- be compared to std_logic_vector
use ieee.std_logic_unsigned.all;
library axi_lite_ipif_v3_0;
use axi_lite_ipif_v3_0.axi_lite_ipif;
use axi_lite_ipif_v3_0.ipif_pkg.all;
library lib_cdc_v1_0;
use lib_cdc_v1_0.cdc_sync;
library axi_quad_spi_v3_2;
use axi_quad_spi_v3_2.all;
library unisim;
use unisim.vcomponents.FDRE;
use unisim.vcomponents.FDR;
-------------------------------------------------------------------------------
entity cross_clk_sync_fifo_1 is
generic (
C_FAMILY : string;
Async_Clk : integer;
C_FIFO_DEPTH : integer;
C_DATA_WIDTH : integer;
--C_AXI4_CLK_PS : integer;
--C_EXT_SPI_CLK_PS : integer;
C_S_AXI_DATA_WIDTH : integer;
C_NUM_TRANSFER_BITS : integer;
--C_AXI_SPI_CLK_EQ_DIFF : integer;
C_NUM_SS_BITS : integer
);
port (
EXT_SPI_CLK : in std_logic;
Bus2IP_Clk : in std_logic;
Soft_Reset_op : in std_logic;
Rst_cdc_to_spi : in std_logic;
----------------------------
SPISR_0_CMD_Error_cdc_from_spi : in std_logic;
SPISR_0_CMD_Error_cdc_to_axi : out std_logic;
----------------------------------------
spisel_d1_reg_cdc_from_spi : in std_logic;
spisel_d1_reg_cdc_to_axi : out std_logic;
----------------------------------------
spisel_pulse_cdc_from_spi : in std_logic;
spisel_pulse_cdc_to_axi : out std_logic;
----------------------------
Mst_N_Slv_mode_cdc_from_spi : in std_logic;
Mst_N_Slv_mode_cdc_to_axi : out std_logic;
----------------------------
slave_MODF_strobe_cdc_from_spi : in std_logic;
slave_MODF_strobe_cdc_to_axi : out std_logic;
----------------------------
modf_strobe_cdc_from_spi : in std_logic;
modf_strobe_cdc_to_axi : out std_logic;
----------------------------
Rx_FIFO_Full_cdc_from_axi : in std_logic;
Rx_FIFO_Full_cdc_to_spi : out std_logic;
----------------------------
reset_RcFIFO_ptr_cdc_from_axi : in std_logic;
reset_RcFIFO_ptr_cdc_to_spi : out std_logic;
----------------------------
Rx_FIFO_Empty_cdc_from_axi : in std_logic;
Rx_FIFO_Empty_cdc_to_spi : out std_logic;
----------------------------
Tx_FIFO_Empty_cdc_from_spi : in std_logic;
Tx_FIFO_Empty_cdc_to_axi : out std_logic;
----------------------------
Tx_FIFO_Empty_SPISR_cdc_from_spi : in std_logic;
Tx_FIFO_Empty_SPISR_cdc_to_axi : out std_logic;
----------------------------
Tx_FIFO_Full_cdc_from_axi : in std_logic;
Tx_FIFO_Full_cdc_to_spi : out std_logic;
----------------------------
spiXfer_done_cdc_from_spi : in std_logic;
spiXfer_done_cdc_to_axi : out std_logic;
----------------------------
dtr_underrun_cdc_from_spi : in std_logic;
dtr_underrun_cdc_to_axi : out std_logic;
----------------------------
SPICR_0_LOOP_cdc_from_axi : in std_logic;
SPICR_0_LOOP_cdc_to_spi : out std_logic;
----------------------------
SPICR_1_SPE_cdc_from_axi : in std_logic;
SPICR_1_SPE_cdc_to_spi : out std_logic;
----------------------------
SPICR_2_MST_N_SLV_cdc_from_axi : in std_logic;
SPICR_2_MST_N_SLV_cdc_to_spi : out std_logic;
----------------------------
SPICR_3_CPOL_cdc_from_axi : in std_logic;
SPICR_3_CPOL_cdc_to_spi : out std_logic;
----------------------------
SPICR_4_CPHA_cdc_from_axi : in std_logic;
SPICR_4_CPHA_cdc_to_spi : out std_logic;
----------------------------
SPICR_5_TXFIFO_cdc_from_axi : in std_logic;
SPICR_5_TXFIFO_cdc_to_spi : out std_logic;
----------------------------
SPICR_6_RXFIFO_RST_cdc_from_axi: in std_logic;
SPICR_6_RXFIFO_RST_cdc_to_spi : out std_logic;
----------------------------
SPICR_7_SS_cdc_from_axi : in std_logic;
SPICR_7_SS_cdc_to_spi : out std_logic;
----------------------------
SPICR_8_TR_INHIBIT_cdc_from_axi: in std_logic;
SPICR_8_TR_INHIBIT_cdc_to_spi : out std_logic;
----------------------------
SPICR_9_LSB_cdc_from_axi : in std_logic;
SPICR_9_LSB_cdc_to_spi : out std_logic;
----------------------------
SPICR_bits_7_8_cdc_from_axi : in std_logic_vector(1 downto 0); -- in std_logic_vector
SPICR_bits_7_8_cdc_to_spi : out std_logic_vector(1 downto 0);
----------------------------
SR_3_modf_cdc_from_axi : in std_logic;
SR_3_modf_cdc_to_spi : out std_logic;
----------------------------
SPISSR_cdc_from_axi : in std_logic_vector(0 to (C_NUM_SS_BITS-1));
SPISSR_cdc_to_spi : out std_logic_vector(0 to (C_NUM_SS_BITS-1));
----------------------------
spiXfer_done_cdc_to_axi_1 : out std_logic;
----------------------------
drr_Overrun_int_cdc_from_spi : in std_logic;
drr_Overrun_int_cdc_to_axi : out std_logic
);
end entity cross_clk_sync_fifo_1;
-------------------------------------------------------------------------------
architecture imp of cross_clk_sync_fifo_1 is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
signal SPISR_0_CMD_Error_cdc_from_spi_d1: std_logic;
signal SPISR_0_CMD_Error_cdc_from_spi_d2: std_logic;
signal spisel_d1_reg_cdc_from_spi_d1 : std_logic;
signal spisel_d1_reg_cdc_from_spi_d2 : std_logic;
signal spisel_pulse_cdc_from_spi_d1 : std_logic;
signal spisel_pulse_cdc_from_spi_d2 : std_logic;
signal spisel_pulse_cdc_from_spi_d3 : std_logic;-- 2/21/2012
signal spisel_pulse_cdc_from_spi_d4 : std_logic;
signal Mst_N_Slv_mode_cdc_from_spi_d1 : std_logic;
signal Mst_N_Slv_mode_cdc_from_spi_d2 : std_logic;
signal slave_MODF_strobe_cdc_from_spi_d1: std_logic;
signal slave_MODF_strobe_cdc_from_spi_d2: std_logic;
signal slave_MODF_strobe_cdc_from_spi_d3: std_logic; -- 2/21/2012
signal Slave_MODF_strobe_cdc_from_spi_int_2 : std_logic;
signal modf_strobe_cdc_from_spi_d1 : std_logic;
signal modf_strobe_cdc_from_spi_d2 : std_logic;
signal modf_strobe_cdc_from_spi_d3 : std_logic;
signal SPICR_6_RXFIFO_RST_cdc_from_axi_d1 : std_logic;
signal SPICR_6_RXFIFO_RST_cdc_from_axi_d2 : std_logic;
signal Rx_FIFO_Full_cdc_from_axi_d1 : std_logic;
signal Rx_FIFO_Full_cdc_from_axi_d2 : std_logic;
signal reset_RcFIFO_ptr_cdc_from_axi_d1 : std_logic;
signal reset_RcFIFO_ptr_cdc_from_axi_d2 : std_logic;
signal Rx_FIFO_Empty_cdc_from_axi_d1 : std_logic;
signal Rx_FIFO_Empty_cdc_from_axi_d2 : std_logic;
signal Tx_FIFO_Empty_cdc_from_spi_d1 : std_logic;
signal Tx_FIFO_Empty_cdc_from_spi_d2 : std_logic;
-- signal Tx_FIFO_Empty_cdc_from_spi_d2 : std_logic_vector(2 downto 0);
signal Tx_FIFO_Full_cdc_from_axi_d1 : std_logic;
signal Tx_FIFO_Full_cdc_from_axi_d2 : std_logic;
signal modf_strobe_cdc_to_axi_d1 : std_logic;
signal modf_strobe_cdc_to_axi_d2 : std_logic;
signal modf_strobe_cdc_from_spi_int_2 : std_logic;
signal spiXfer_done_cdc_from_spi_d1 : std_logic;
signal spiXfer_done_cdc_from_spi_d2 : std_logic;
signal dtr_underrun_cdc_from_spi_d1 : std_logic;
signal dtr_underrun_cdc_from_spi_d2 : std_logic;
signal SPICR_0_LOOP_cdc_from_axi_d1 : std_logic;
signal SPICR_0_LOOP_cdc_from_axi_d2 : std_logic;
signal SPICR_1_SPE_cdc_from_axi_d1 : std_logic;
signal SPICR_1_SPE_cdc_from_axi_d2 : std_logic;
signal SPICR_2_MST_N_SLV_cdc_from_axi_d1 : std_logic;
signal SPICR_2_MST_N_SLV_cdc_from_axi_d2 : std_logic;
signal SPICR_3_CPOL_cdc_from_axi_d1 : std_logic;
signal SPICR_3_CPOL_cdc_from_axi_d2 : std_logic;
signal SPICR_4_CPHA_cdc_from_axi_d1 : std_logic;
signal SPICR_4_CPHA_cdc_from_axi_d2 : std_logic;
signal SPICR_5_TXFIFO_cdc_from_axi_d1 : std_logic;
signal SPICR_5_TXFIFO_cdc_from_axi_d2 : std_logic;
signal SPICR_7_SS_cdc_from_axi_d1 : std_logic;
signal SPICR_7_SS_cdc_from_axi_d2 : std_logic;
signal SPICR_8_TR_INHIBIT_cdc_from_axi_d1 : std_logic;
signal SPICR_8_TR_INHIBIT_cdc_from_axi_d2 : std_logic;
signal SPICR_9_LSB_cdc_from_axi_d1 : std_logic;
signal SPICR_9_LSB_cdc_from_axi_d2 : std_logic;
signal SPICR_bits_7_8_cdc_from_axi_d1 : std_logic_vector(1 downto 0);
signal SPICR_bits_7_8_cdc_from_axi_d2 : std_logic_vector(1 downto 0);
signal SR_3_modf_cdc_from_axi_d1 : std_logic;
signal SR_3_modf_cdc_from_axi_d2 : std_logic;
signal SPISSR_cdc_from_axi_d1 : std_logic_vector(0 to (C_NUM_SS_BITS-1));
signal SPISSR_cdc_from_axi_d2 : std_logic_vector(0 to (C_NUM_SS_BITS-1));
signal rx_fifo_full_int, RST_RX_FF : std_logic;
signal rx_fifo_full_int_2 : std_logic;
signal RST_spiXfer_done_FF : std_logic;
signal spiXfer_done_d1 : std_logic;
signal spiXfer_done_d2, spiXfer_done_d3 : std_logic;
signal spiXfer_done_cdc_from_spi_int_2 : std_logic;
signal spiXfer_done_cdc_from_spi_int : std_logic;
signal Tx_FIFO_Empty_SPISR_cdc_from_spi_d1 : std_logic;
signal Tx_FIFO_Empty_SPISR_cdc_from_spi_d2 : std_logic;
signal reset_RX_FIFO_Rst_pulse : std_logic;
signal SPICR_RX_FIFO_Rst_en_d1 : std_logic;
signal SPICR_RX_FIFO_Rst_en : std_logic;
signal spisel_pulse_cdc_from_spi_int_2 : std_logic;
signal SPISSR_cdc_from_axi_d1_and_reduce : std_logic;
signal drr_Overrun_int_cdc_from_spi_d1 : std_logic;
signal drr_Overrun_int_cdc_from_spi_d2 : std_logic;
signal drr_Overrun_int_cdc_from_spi_d3 : std_logic;
signal drr_Overrun_int_cdc_from_spi_int_2 : std_logic;
signal SPICR_RX_FIFO_Rst_en_d2 : std_logic;
-- signal SPISR_0_CMD_Error_cdc_from_spi_d1: std_logic;
-- signal SPISR_0_CMD_Error_cdc_from_spi_d2: std_logic;
-- signal spisel_d1_reg_cdc_from_spi_d1 : std_logic;
-- signal spisel_d1_reg_cdc_from_spi_d2 : std_logic;
-- signal spisel_pulse_cdc_from_spi_d1 : std_logic;
-- signal spisel_pulse_cdc_from_spi_d2 : std_logic;
-- signal spisel_pulse_cdc_from_spi_d3 : std_logic;-- 2/21/2012
-- signal Mst_N_Slv_mode_cdc_from_spi_d1 : std_logic;
-- signal Mst_N_Slv_mode_cdc_from_spi_d2 : std_logic;
-- signal slave_MODF_strobe_cdc_from_spi_d1: std_logic;
-- signal slave_MODF_strobe_cdc_from_spi_d2: std_logic;
-- signal slave_MODF_strobe_cdc_from_spi_d3: std_logic; -- 2/21/2012
-- signal Slave_MODF_strobe_cdc_from_spi_int_2 : std_logic;
-- signal modf_strobe_cdc_from_spi_d1 : std_logic;
-- signal modf_strobe_cdc_from_spi_d2 : std_logic;
-- signal modf_strobe_cdc_from_spi_d3 : std_logic;
-- signal SPICR_6_RXFIFO_RST_cdc_from_axi_d1 : std_logic;
-- signal SPICR_6_RXFIFO_RST_cdc_from_axi_d2 : std_logic;
-- signal Rx_FIFO_Full_cdc_from_axi_d1 : std_logic;
-- signal Rx_FIFO_Full_cdc_from_axi_d2 : std_logic;
-- signal reset_RcFIFO_ptr_cdc_from_axi_d1 : std_logic;
-- signal reset_RcFIFO_ptr_cdc_from_axi_d2 : std_logic;
-- signal Rx_FIFO_Empty_cdc_from_axi_d1 : std_logic;
-- signal Rx_FIFO_Empty_cdc_from_axi_d2 : std_logic;
-- signal Tx_FIFO_Empty_cdc_from_spi_d1 : std_logic;
-- signal Tx_FIFO_Empty_cdc_from_spi_d2 : std_logic;
-- -- signal Tx_FIFO_Empty_cdc_from_spi_d2 : std_logic_vector(2 downto 0);
-- signal Tx_FIFO_Full_cdc_from_axi_d1 : std_logic;
-- signal Tx_FIFO_Full_cdc_from_axi_d2 : std_logic;
-- signal modf_strobe_cdc_to_axi_d1 : std_logic;
-- signal modf_strobe_cdc_to_axi_d2 : std_logic;
-- signal modf_strobe_cdc_from_spi_int_2 : std_logic;
-- signal spiXfer_done_cdc_from_spi_d1 : std_logic;
-- signal spiXfer_done_cdc_from_spi_d2 : std_logic;
-- signal dtr_underrun_cdc_from_spi_d1 : std_logic;
-- signal dtr_underrun_cdc_from_spi_d2 : std_logic;
-- signal SPICR_0_LOOP_cdc_from_axi_d1 : std_logic;
-- signal SPICR_0_LOOP_cdc_from_axi_d2 : std_logic;
-- signal SPICR_1_SPE_cdc_from_axi_d1 : std_logic;
-- signal SPICR_1_SPE_cdc_from_axi_d2 : std_logic;
-- signal SPICR_2_MST_N_SLV_cdc_from_axi_d1 : std_logic;
-- signal SPICR_2_MST_N_SLV_cdc_from_axi_d2 : std_logic;
-- signal SPICR_3_CPOL_cdc_from_axi_d1 : std_logic;
-- signal SPICR_3_CPOL_cdc_from_axi_d2 : std_logic;
-- signal SPICR_4_CPHA_cdc_from_axi_d1 : std_logic;
-- signal SPICR_4_CPHA_cdc_from_axi_d2 : std_logic;
-- signal SPICR_5_TXFIFO_cdc_from_axi_d1 : std_logic;
-- signal SPICR_5_TXFIFO_cdc_from_axi_d2 : std_logic;
-- signal SPICR_7_SS_cdc_from_axi_d1 : std_logic;
-- signal SPICR_7_SS_cdc_from_axi_d2 : std_logic;
-- signal SPICR_8_TR_INHIBIT_cdc_from_axi_d1 : std_logic;
-- signal SPICR_8_TR_INHIBIT_cdc_from_axi_d2 : std_logic;
-- signal SPICR_9_LSB_cdc_from_axi_d1 : std_logic;
-- signal SPICR_9_LSB_cdc_from_axi_d2 : std_logic;
-- signal SPICR_bits_7_8_cdc_from_axi_d1 : std_logic_vector(1 downto 0);
-- signal SPICR_bits_7_8_cdc_from_axi_d2 : std_logic_vector(1 downto 0);
-- signal SR_3_modf_cdc_from_axi_d1 : std_logic;
-- signal SR_3_modf_cdc_from_axi_d2 : std_logic;
-- signal SPISSR_cdc_from_axi_d1 : std_logic_vector(0 to (C_NUM_SS_BITS-1));
-- signal SPISSR_cdc_from_axi_d2 : std_logic_vector(0 to (C_NUM_SS_BITS-1));
-- signal rx_fifo_full_int, RST_RX_FF : std_logic;
-- signal rx_fifo_full_int_2 : std_logic;
-- signal RST_spiXfer_done_FF : std_logic;
-- signal spiXfer_done_d1 : std_logic;
-- signal spiXfer_done_d2, spiXfer_done_d3 : std_logic;
-- signal spiXfer_done_cdc_from_spi_int_2 : std_logic;
-- signal spiXfer_done_cdc_from_spi_int : std_logic;
-- signal Tx_FIFO_Empty_SPISR_cdc_from_spi_d1 : std_logic;
-- signal Tx_FIFO_Empty_SPISR_cdc_from_spi_d2 : std_logic;
-- signal reset_RX_FIFO_Rst_pulse : std_logic;
-- signal SPICR_RX_FIFO_Rst_en_d1 : std_logic;
-- signal SPICR_RX_FIFO_Rst_en : std_logic;
-- signal spisel_pulse_cdc_from_spi_int_2 : std_logic;
-- signal SPISSR_cdc_from_axi_d1_and_reduce : std_logic;
-- signal drr_Overrun_int_cdc_from_spi_d1 : std_logic;
-- signal drr_Overrun_int_cdc_from_spi_d2 : std_logic;
-- signal drr_Overrun_int_cdc_from_spi_d3 : std_logic;
-- signal drr_Overrun_int_cdc_from_spi_int_2 : std_logic;
--------------------------
-- attribute ASYNC_REG : string;
-- attribute ASYNC_REG of CMD_ERR_S2AX_1_CDC : label is "TRUE";
-- attribute ASYNC_REG of SPISEL_D1_REG_S2AX_1_CDC : label is "TRUE";
-- attribute ASYNC_REG of SPISEL_PULSE_S2AX_1_CDC : label is "TRUE";
-- attribute ASYNC_REG of MST_N_SLV_MODE_S2AX_1_CDC : label is "TRUE";
-- -- attribute ASYNC_REG of SLAVE_MODF_STROBE_SYNC_SPI_2_AXI_1 : label is "TRUE";
-- attribute ASYNC_REG of RX_FIFO_EMPTY_AX2S_1_CDC : label is "TRUE";
-- attribute ASYNC_REG of TX_FIFO_EMPTY_S2AX_1_CDC : label is "TRUE";
-- attribute ASYNC_REG of TX_FIFO_FULL_AX2S_1_CDC : label is "TRUE";
-- attribute ASYNC_REG of SPIXFER_DONE_S2AX_1_CDC : label is "TRUE";
-- attribute ASYNC_REG of RX_FIFO_RST_AX2S_1_CDC : label is "TRUE"; -- 3/25/2013
-- attribute ASYNC_REG of RX_FIFO_FULL_S2AX_1_CDC : label is "TRUE"; -- 3/25/2013
-- attribute ASYNC_REG of SYNC_SPIXFER_DONE_S2AX_1_CDC: label is "TRUE"; -- 3/25/2013
-- attribute ASYNC_REG of DTR_UNDERRUN_S2AX_1_CDC : label is "TRUE"; -- 3/25/2013
-- attribute ASYNC_REG of SPICR_0_LOOP_AX2S_1_CDC : label is "TRUE";
-- attribute ASYNC_REG of SPICR_1_SPE_AX2S_1_CDC : label is "TRUE";
-- attribute ASYNC_REG of SPICR_2_MST_N_SLV_AX2S_1_CDC : label is "TRUE";
-- attribute ASYNC_REG of SPICR_3_CPOL_AX2S_1_CDC : label is "TRUE";
-- attribute ASYNC_REG of SPICR_4_CPHA_AX2S_1_CDC : label is "TRUE";
-- attribute ASYNC_REG of SPICR_5_TXFIFO_AX2S_1_CDC : label is "TRUE";
-- attribute ASYNC_REG of SPICR_6_RXFIFO_RST_AX2S_1_CDC : label is "TRUE";
-- attribute ASYNC_REG of SPICR_7_SS_AX2S_1_CDC : label is "TRUE";
-- attribute ASYNC_REG of SPICR_8_TR_INHIBIT_AX2S_1_CDC : label is "TRUE";
-- attribute ASYNC_REG of SPICR_9_LSB_AX2S_1_CDC : label is "TRUE";
-- attribute ASYNC_REG of SR_3_MODF_AX2S_1_CDC : label is "TRUE";
-- attribute ASYNC_REG of SLV_MODF_STRB_S2AX_1_CDC : label is "TRUE";
-- attribute ASYNC_REG of MODF_STROBE_S2AX_1_CDC : label is "TRUE";
-- attribute ASYNC_REG of TX_EMPT_4_SPISR_S2AX_1_CDC : label is "TRUE";
-- attribute ASYNC_REG of DRR_OVERRUN_S2AX_1_CDC : label is "TRUE"; -- 3/25/2013
attribute KEEP : string;
attribute KEEP of SPISR_0_CMD_Error_cdc_from_spi_d2: signal is "TRUE";
attribute KEEP of spisel_d1_reg_cdc_from_spi_d2: signal is "TRUE";
attribute KEEP of spisel_pulse_cdc_from_spi_d2: signal is "TRUE";
attribute KEEP of spisel_pulse_cdc_from_spi_d1: signal is "TRUE";
attribute KEEP of Mst_N_Slv_mode_cdc_from_spi_d2: signal is "TRUE";
attribute KEEP of Slave_MODF_strobe_cdc_from_spi_d2: signal is "TRUE";
attribute KEEP of Slave_MODF_strobe_cdc_from_spi_d1: signal is "TRUE";
attribute KEEP of modf_strobe_cdc_from_spi_d2 : signal is "TRUE";
attribute KEEP of modf_strobe_cdc_from_spi_d1 : signal is "TRUE";
constant LOGIC_CHANGE : integer range 0 to 1 := 1;
constant MTBF_STAGES_AXI2S : integer range 0 to 6 := 3 ;
constant MTBF_STAGES_S2AXI : integer range 0 to 6 := 4 ;
-----
begin
-----
SPISSR_cdc_from_axi_d1_and_reduce <= and_reduce(SPISSR_cdc_from_axi_d2);
LOGIC_GENERATION_FDR : if (Async_Clk = 0) generate
--==============================================================================
CMD_ERR_S2AX_1_CDC: component FDR
generic map(INIT => '0' -- added on 16th Feb
)port map (
Q => SPISR_0_CMD_Error_cdc_from_spi_d1,
C => Bus2IP_Clk,
D => SPISR_0_CMD_Error_cdc_from_spi,
R => Soft_Reset_op
);
CMD_ERR_S2AX_2: component FDR
generic map(INIT => '0'
)port map (
Q => SPISR_0_CMD_Error_cdc_from_spi_d2,
C => Bus2IP_Clk,
D => SPISR_0_CMD_Error_cdc_from_spi_d1,
R => Soft_Reset_op
);
SPISR_0_CMD_Error_cdc_to_axi <= SPISR_0_CMD_Error_cdc_from_spi_d2;
-----------------------------------------------------------
--==============================================================================
SPISEL_D1_REG_S2AX_1_CDC: component FDR
generic map(INIT => '1'
)port map (
Q => spisel_d1_reg_cdc_from_spi_d1,
C => Bus2IP_Clk,
D => spisel_d1_reg_cdc_from_spi,
R => Soft_Reset_op
);
SPISEL_D1_REG_S2AX_2: component FDR
generic map(INIT => '1'
)port map (
Q => spisel_d1_reg_cdc_from_spi_d2,
C => Bus2IP_Clk,
D => spisel_d1_reg_cdc_from_spi_d1,
R => Soft_Reset_op
);
spisel_d1_reg_cdc_to_axi <= spisel_d1_reg_cdc_from_spi_d2;
-------------------------------------------------
--==============================================================================
SPISEL_PULSE_STRETCH_1: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_cdc_to_spi = '1') then
spisel_pulse_cdc_from_spi_int_2 <= '0';
else
spisel_pulse_cdc_from_spi_int_2 <= --((not SPISSR_cdc_from_axi_d1_and_reduce) and
spisel_pulse_cdc_from_spi xor
spisel_pulse_cdc_from_spi_int_2;
end if;
end if;
end process SPISEL_PULSE_STRETCH_1;
SPISEL_PULSE_S2AX_1_CDC: component FDR
generic map(INIT => '1'
)port map (
Q => spisel_pulse_cdc_from_spi_d1,
C => Bus2IP_Clk,
D => spisel_pulse_cdc_from_spi_int_2, -- spisel_pulse_cdc_from_spi,
R => Soft_Reset_op
);
SPISEL_PULSE_S2AX_2: component FDR
generic map(INIT => '1'
)port map (
Q => spisel_pulse_cdc_from_spi_d2,
C => Bus2IP_Clk,
D => spisel_pulse_cdc_from_spi_d1,
R => Soft_Reset_op
);
SPISEL_PULSE_S2AX_3: component FDR -- 2/21/2012
generic map(INIT => '1'
)port map (
Q => spisel_pulse_cdc_from_spi_d3,
C => Bus2IP_Clk,
D => spisel_pulse_cdc_from_spi_d2,
R => Soft_Reset_op
);
-- spisel_pulse_cdc_to_axi <= spisel_pulse_cdc_from_spi_d2 xor spisel_pulse_cdc_from_spi_d1;
spisel_pulse_cdc_to_axi <= spisel_pulse_cdc_from_spi_d3 xor spisel_pulse_cdc_from_spi_d2; -- 2/21/2012
-----------------------------------------------
--==============================================================================
MST_N_SLV_MODE_S2AX_1_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => Mst_N_Slv_mode_cdc_from_spi_d1,
C => Bus2IP_Clk,
D => Mst_N_Slv_mode_cdc_from_spi,
R => Soft_Reset_op
);
MST_N_SLV_MODE_S2AX_2: component FDR
generic map(INIT => '0'
)port map (
Q => Mst_N_Slv_mode_cdc_from_spi_d2,
C => Bus2IP_Clk,
D => Mst_N_Slv_mode_cdc_from_spi_d1,
R => Soft_Reset_op
);
Mst_N_Slv_mode_cdc_to_axi <= Mst_N_Slv_mode_cdc_from_spi_d2;
---------------------------------------------------
--==============================================================================
SLAVE_MODF_STROBE_STRETCH_1: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_cdc_to_spi = '1') then
Slave_MODF_strobe_cdc_from_spi_int_2 <= '0';
else
Slave_MODF_strobe_cdc_from_spi_int_2 <= Slave_MODF_strobe_cdc_from_spi xor
Slave_MODF_strobe_cdc_from_spi_int_2;
end if;
end if;
end process SLAVE_MODF_STROBE_STRETCH_1;
SLV_MODF_STRB_S2AX_1_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => Slave_MODF_strobe_cdc_from_spi_d1,
C => Bus2IP_Clk,
D => Slave_MODF_strobe_cdc_from_spi_int_2,
R => Soft_Reset_op
);
SLV_MODF_STRB_S2AX_2: component FDR
generic map(INIT => '0'
)port map (
Q => Slave_MODF_strobe_cdc_from_spi_d2,
C => Bus2IP_Clk,
D => Slave_MODF_strobe_cdc_from_spi_d1,
R => Soft_Reset_op
);
SLV_MODF_STRB_S2AX_3: component FDR -- 2/21/2012
generic map(INIT => '0'
)port map (
Q => Slave_MODF_strobe_cdc_from_spi_d3,
C => Bus2IP_Clk,
D => Slave_MODF_strobe_cdc_from_spi_d2,
R => Soft_Reset_op
);
-- Slave_MODF_strobe_cdc_to_axi <= Slave_MODF_strobe_cdc_from_spi_d2 xor Slave_MODF_strobe_cdc_from_spi_d1; --spiXfer_done_cdc_from_spi_d2;
Slave_MODF_strobe_cdc_to_axi <= Slave_MODF_strobe_cdc_from_spi_d3 xor Slave_MODF_strobe_cdc_from_spi_d2;-- 2/21/2012
--==============================================================================
MODF_STROBE_STRETCH_1: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_cdc_to_spi = '1') then
modf_strobe_cdc_from_spi_int_2 <= '0';
else
modf_strobe_cdc_from_spi_int_2 <= modf_strobe_cdc_from_spi xor
modf_strobe_cdc_from_spi_int_2;
end if;
end if;
end process MODF_STROBE_STRETCH_1;
MODF_STROBE_S2AX_1_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => modf_strobe_cdc_from_spi_d1,
C => Bus2IP_Clk,
D => modf_strobe_cdc_from_spi_int_2,
R => Soft_Reset_op
);
MODF_STROBE_S2AX_2: component FDR
generic map(INIT => '0'
)port map (
Q => modf_strobe_cdc_from_spi_d2,
C => Bus2IP_Clk,
D => modf_strobe_cdc_from_spi_d1,
R => Soft_Reset_op
);
MODF_STROBE_S2AX_3: component FDR
generic map(INIT => '0'
)port map (
Q => modf_strobe_cdc_from_spi_d3,
C => Bus2IP_Clk,
D => modf_strobe_cdc_from_spi_d2,
R => Soft_Reset_op
);
-- modf_strobe_cdc_to_axi <= modf_strobe_cdc_from_spi_d2 xor modf_strobe_cdc_from_spi_d1; --spiXfer_done_cdc_from_spi_d2;
modf_strobe_cdc_to_axi <= modf_strobe_cdc_from_spi_d3 xor modf_strobe_cdc_from_spi_d2; -- 2/21/2012
-----------------------------------------------
--==============================================================================
RX_FIFO_EMPTY_AX2S_1_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => Rx_FIFO_Empty_cdc_from_axi_d1,
C => EXT_SPI_CLK, -- Bus2IP_Clk,
D => Rx_FIFO_Empty_cdc_from_axi,
R => Rst_cdc_to_spi -- Soft_Reset_op
);
RX_FIFO_EMPTY_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => Rx_FIFO_Empty_cdc_from_axi_d2,
C => EXT_SPI_CLK, -- Bus2IP_Clk,
D => Rx_FIFO_Empty_cdc_from_axi_d1,
R => Rst_cdc_to_spi -- Soft_Reset_op
);
Rx_FIFO_Empty_cdc_to_spi <= Rx_FIFO_Empty_cdc_from_axi_d2;
-------------------------------------------------
--==============================================================================
TX_FIFO_EMPTY_S2AX_1_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => Tx_FIFO_Empty_cdc_from_spi_d1,
C => Bus2IP_Clk,
D => Tx_FIFO_Empty_cdc_from_spi,
R => Soft_Reset_op
);
TX_FIFO_EMPTY_S2AX_2: component FDR
generic map(INIT => '0'
)port map (
Q => Tx_FIFO_Empty_cdc_from_spi_d2,
C => Bus2IP_Clk,
D => Tx_FIFO_Empty_cdc_from_spi_d1,
R => Soft_Reset_op
);
Tx_FIFO_Empty_cdc_to_axi <= Tx_FIFO_Empty_cdc_from_spi_d2;
-------------------------------------------------
--==============================================================================
TX_EMPT_4_SPISR_S2AX_1_CDC: component FDR
generic map(INIT => '1'
)port map (
Q => Tx_FIFO_Empty_SPISR_cdc_from_spi_d1,
C => Bus2IP_Clk,
D => Tx_FIFO_Empty_SPISR_cdc_from_spi,
R => Soft_Reset_op
);
TX_EMPT_4_SPISR_S2AX_2: component FDR
generic map(INIT => '1'
)port map (
Q => Tx_FIFO_Empty_SPISR_cdc_from_spi_d2,
C => Bus2IP_Clk,
D => Tx_FIFO_Empty_SPISR_cdc_from_spi_d1,
R => Soft_Reset_op
);
Tx_FIFO_Empty_SPISR_cdc_to_axi <= Tx_FIFO_Empty_SPISR_cdc_from_spi_d2;
--==============================================================================
TX_FIFO_FULL_AX2S_1_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => Tx_FIFO_Full_cdc_from_axi_d1,
C => EXT_SPI_CLK, -- Bus2IP_Clk,
D => Tx_FIFO_Full_cdc_from_axi,
R => Rst_cdc_to_spi -- Soft_Reset_op
);
TX_FIFO_FULL_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => Tx_FIFO_Full_cdc_from_axi_d2,
C => EXT_SPI_CLK, -- Bus2IP_Clk,
D => Tx_FIFO_Full_cdc_from_axi_d1,
R => Rst_cdc_to_spi -- Soft_Reset_op
);
Tx_FIFO_Full_cdc_to_spi <= Tx_FIFO_Full_cdc_from_axi_d2;
-----------------------------------------------
--==============================================================================
SPIXFER_DONE_S2AX_1_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => spiXfer_done_cdc_from_spi_d1,
C => Bus2IP_Clk,
D => spiXfer_done_cdc_from_spi,
R => Soft_Reset_op
);
SPIXFER_DONE_S2AX_2: component FDR
generic map(INIT => '0'
)port map (
Q => spiXfer_done_cdc_from_spi_d2,
C => Bus2IP_Clk,
D => spiXfer_done_cdc_from_spi_d1,
R => Soft_Reset_op
);
spiXfer_done_cdc_to_axi <= spiXfer_done_cdc_from_spi_d2;
-----------------------------------------------
SPICR_RX_FIFO_Rst_en <= reset_RcFIFO_ptr_cdc_from_axi xor SPICR_RX_FIFO_Rst_en_d1;
SPICR_RX_FIFO_RST_REG_SPI_DOMAIN_P:process(Bus2IP_Clk)is
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = '1') then -- or reset_RX_FIFO_Rst_pulse = '1')then
SPICR_RX_FIFO_Rst_en_d1 <= '0';
else
SPICR_RX_FIFO_Rst_en_d1 <= SPICR_RX_FIFO_Rst_en;
end if;
end if;
end process SPICR_RX_FIFO_RST_REG_SPI_DOMAIN_P;
-------------------------------------------------
--reset_RcFIFO_ptr_cdc_to_spi <= reset_RcFIFO_ptr_cdc_from_axi_d2;
RX_FIFO_RST_AX2S_1_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => reset_RcFIFO_ptr_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_RX_FIFO_Rst_en_d1,
R => Rst_cdc_to_spi
);
RX_FIFO_RST_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => reset_RcFIFO_ptr_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => reset_RcFIFO_ptr_cdc_from_axi_d1,
R => Rst_cdc_to_spi
);
reset_RcFIFO_ptr_cdc_to_spi <= reset_RcFIFO_ptr_cdc_from_axi_d1 xor
reset_RcFIFO_ptr_cdc_from_axi_d2;
--reset_RcFIFO_ptr_cdc_to_spi <= reset_RcFIFO_ptr_cdc_from_axi_d2;
-----------------------------------------------------------
------------------------------------------
RX_FIFO_FULL_S2AX_1_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => Rx_FIFO_Full_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => Rx_FIFO_Full_cdc_from_axi,
R => Rst_cdc_to_spi
);
RX_FIFO_FULL_S2AX_2: component FDR
generic map(INIT => '0'
)port map (
Q => Rx_FIFO_Full_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => Rx_FIFO_Full_cdc_from_axi_d1,
R => Rst_cdc_to_spi
);
Rx_FIFO_Full_cdc_to_spi <= Rx_FIFO_Full_cdc_from_axi_d2;
------------------------------------------
SPI_XFER_DONE_STRETCH_1: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_cdc_to_spi = '1') then
spiXfer_done_cdc_from_spi_int_2 <= '0';
else
spiXfer_done_cdc_from_spi_int_2 <= spiXfer_done_cdc_from_spi xor
spiXfer_done_cdc_from_spi_int_2;
end if;
end if;
end process SPI_XFER_DONE_STRETCH_1;
SYNC_SPIXFER_DONE_S2AX_1_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => spiXfer_done_d1,
C => Bus2IP_Clk,
D => spiXfer_done_cdc_from_spi_int_2,
R => Soft_Reset_op
);
SYNC_SPIXFER_DONE_S2AX_2: component FDR
generic map(INIT => '0'
)port map (
Q => spiXfer_done_d2,
C => Bus2IP_Clk,
D => spiXfer_done_d1,
R => Soft_Reset_op
);
SYNC_SPIXFER_DONE_S2AX_3: component FDR
generic map(INIT => '0'
)port map (
Q => spiXfer_done_d3,
C => Bus2IP_Clk,
D => spiXfer_done_d2,
R => Soft_Reset_op
);
spiXfer_done_cdc_to_axi_1 <= spiXfer_done_d2 xor spiXfer_done_d3;
-------------------------------------------------------------------------
DTR_UNDERRUN_S2AX_1_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => dtr_underrun_cdc_from_spi_d1,
C => Bus2IP_Clk,
D => dtr_underrun_cdc_from_spi,
R => Soft_Reset_op
);
DTR_UNDERRUN_S2AX_2: component FDR
generic map(INIT => '0'
)port map (
Q => dtr_underrun_cdc_from_spi_d2,
C => Bus2IP_Clk,
D => dtr_underrun_cdc_from_spi_d1,
R => Soft_Reset_op
);
dtr_underrun_cdc_to_axi <= dtr_underrun_cdc_from_spi_d2;
-------------------------------------------------
SPICR_0_LOOP_AX2S_1_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_0_LOOP_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_0_LOOP_cdc_from_axi,
R => Rst_cdc_to_spi
);
SPICR_0_LOOP_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_0_LOOP_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SPICR_0_LOOP_cdc_from_axi_d1,
R => Rst_cdc_to_spi
);
SPICR_0_LOOP_cdc_to_spi <= SPICR_0_LOOP_cdc_from_axi_d2;
-----------------------------------------------
SPICR_1_SPE_AX2S_1_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_1_SPE_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_1_SPE_cdc_from_axi,
R => Rst_cdc_to_spi
);
SPICR_1_SPE_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_1_SPE_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SPICR_1_SPE_cdc_from_axi_d1,
R => Rst_cdc_to_spi
);
SPICR_1_SPE_cdc_to_spi <= SPICR_1_SPE_cdc_from_axi_d2;
---------------------------------------------
SPICR_2_MST_N_SLV_AX2S_1_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_2_MST_N_SLV_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_2_MST_N_SLV_cdc_from_axi,
R => Rst_cdc_to_spi
);
SPICR_2_MST_N_SLV_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_2_MST_N_SLV_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SPICR_2_MST_N_SLV_cdc_from_axi_d1,
R => Rst_cdc_to_spi
);
SPICR_2_MST_N_SLV_cdc_to_spi <= SPICR_2_MST_N_SLV_cdc_from_axi_d2;
---------------------------------------------------------
SPICR_3_CPOL_AX2S_1_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_3_CPOL_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_3_CPOL_cdc_from_axi,
R => Rst_cdc_to_spi
);
SPICR_3_CPOL_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_3_CPOL_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SPICR_3_CPOL_cdc_from_axi_d1,
R => Rst_cdc_to_spi
);
SPICR_3_CPOL_cdc_to_spi <= SPICR_3_CPOL_cdc_from_axi_d2;
-----------------------------------------------
SPICR_4_CPHA_AX2S_1_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_4_CPHA_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_4_CPHA_cdc_from_axi,
R => Rst_cdc_to_spi
);
SPICR_4_CPHA_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_4_CPHA_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SPICR_4_CPHA_cdc_from_axi_d1,
R => Rst_cdc_to_spi
);
SPICR_4_CPHA_cdc_to_spi <= SPICR_4_CPHA_cdc_from_axi_d2;
-----------------------------------------------
SPICR_5_TXFIFO_AX2S_1_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_5_TXFIFO_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_5_TXFIFO_cdc_from_axi,
R => Rst_cdc_to_spi
);
SPICR_5_TXFIFO_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_5_TXFIFO_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SPICR_5_TXFIFO_cdc_from_axi_d1,
R => Rst_cdc_to_spi
);
SPICR_5_TXFIFO_cdc_to_spi <= SPICR_5_TXFIFO_cdc_from_axi_d2;
---------------------------------------------------
SPICR_6_RXFIFO_RST_AX2S_1_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_6_RXFIFO_RST_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_6_RXFIFO_RST_cdc_from_axi,
R => Rst_cdc_to_spi
);
SPICR_6_RXFIFO_RST_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_6_RXFIFO_RST_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SPICR_6_RXFIFO_RST_cdc_from_axi_d1,
R => Rst_cdc_to_spi
);
SPICR_6_RXFIFO_RST_cdc_to_spi <= SPICR_6_RXFIFO_RST_cdc_from_axi_d2;
-----------------------------------------------------------
SPICR_7_SS_AX2S_1_CDC: component FDR
generic map(INIT => '1'
)port map (
Q => SPICR_7_SS_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_7_SS_cdc_from_axi,
R => Rst_cdc_to_spi
);
SPICR_7_SS_AX2S_2: component FDR
generic map(INIT => '1'
)port map (
Q => SPICR_7_SS_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SPICR_7_SS_cdc_from_axi_d1,
R => Rst_cdc_to_spi
);
SPICR_7_SS_cdc_to_spi <= SPICR_7_SS_cdc_from_axi_d2;
-------------------------------------------
SPICR_8_TR_INHIBIT_AX2S_1_CDC: component FDR
generic map(INIT => '1'
)port map (
Q => SPICR_8_TR_INHIBIT_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_8_TR_INHIBIT_cdc_from_axi,
R => Rst_cdc_to_spi
);
SPICR_8_TR_INHIBIT_AX2S_2: component FDR
generic map(INIT => '1'
)port map (
Q => SPICR_8_TR_INHIBIT_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SPICR_8_TR_INHIBIT_cdc_from_axi_d1,
R => Rst_cdc_to_spi
);
SPICR_8_TR_INHIBIT_cdc_to_spi <= SPICR_8_TR_INHIBIT_cdc_from_axi_d2;
-----------------------------------------------------------
SPICR_9_LSB_AX2S_1_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_9_LSB_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_9_LSB_cdc_from_axi,
R => Rst_cdc_to_spi
);
SPICR_9_LSB_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_9_LSB_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SPICR_9_LSB_cdc_from_axi_d1,
R => Rst_cdc_to_spi
);
SPICR_9_LSB_cdc_to_spi <= SPICR_9_LSB_cdc_from_axi_d2;
---------------------------------------------
SPICR_BITS_7_8_SYNC_GEN: for i in 1 downto 0 generate
attribute ASYNC_REG : string;
attribute ASYNC_REG of SPICR_BITS_7_8_AX2S_1_CDC : label is "TRUE";
begin
-----
SPICR_BITS_7_8_AX2S_1_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_bits_7_8_cdc_from_axi_d1(i),
C => EXT_SPI_CLK,
D => SPICR_bits_7_8_cdc_from_axi(i),
R => Rst_cdc_to_spi
);
SPICR_BITS_7_8_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_bits_7_8_cdc_from_axi_d2(i),
C => EXT_SPI_CLK,
D => SPICR_bits_7_8_cdc_from_axi_d1(i),
R => Rst_cdc_to_spi
);
end generate SPICR_BITS_7_8_SYNC_GEN;
-------------------------------------
SPICR_bits_7_8_cdc_to_spi <= SPICR_bits_7_8_cdc_from_axi_d2;
---------------------------------------------------
SR_3_MODF_AX2S_1_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => SR_3_modf_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SR_3_modf_cdc_from_axi,
R => Rst_cdc_to_spi
);
SR_3_MODF_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => SR_3_modf_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SR_3_modf_cdc_from_axi_d1,
R => Rst_cdc_to_spi
);
SR_3_modf_cdc_to_spi <= SR_3_modf_cdc_from_axi_d2;
-----------------------------------------
SPISSR_SYNC_GEN: for i in 0 to C_NUM_SS_BITS-1 generate
attribute ASYNC_REG : string;
attribute ASYNC_REG of SPISSR_AX2S_1_CDC : label is "TRUE";
-----
begin
-----
SPISSR_AX2S_1_CDC: component FDR
generic map(INIT => '1'
)port map (
Q => SPISSR_cdc_from_axi_d1(i),
C => EXT_SPI_CLK,
D => SPISSR_cdc_from_axi(i),
R => Rst_cdc_to_spi
);
SPISSR_SYNC_AXI_2_SPI_2: component FDR
generic map(INIT => '1'
)port map (
Q => SPISSR_cdc_from_axi_d2(i),
C => EXT_SPI_CLK,
D => SPISSR_cdc_from_axi_d1(i),
R => Rst_cdc_to_spi
);
end generate SPISSR_SYNC_GEN;
SPISSR_cdc_to_spi <= SPISSR_cdc_from_axi_d2;
-----------------------------------
DRR_OVERRUN_STRETCH_1: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_cdc_to_spi = '1') then
drr_Overrun_int_cdc_from_spi_int_2 <= '0';
else
drr_Overrun_int_cdc_from_spi_int_2 <= drr_Overrun_int_cdc_from_spi xor
drr_Overrun_int_cdc_from_spi_int_2;
end if;
end if;
end process DRR_OVERRUN_STRETCH_1;
DRR_OVERRUN_S2AX_1_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => drr_Overrun_int_cdc_from_spi_d1,
C => Bus2IP_Clk,
D => drr_Overrun_int_cdc_from_spi_int_2,
R => Soft_Reset_op
);
DRR_OVERRUN_S2AX_2: component FDR
generic map(INIT => '0'
)port map (
Q => drr_Overrun_int_cdc_from_spi_d2,
C => Bus2IP_Clk,
D => drr_Overrun_int_cdc_from_spi_d1,
R => Soft_Reset_op
);
DRR_OVERRUN_S2AX_3: component FDR -- 2/21/2012
generic map(INIT => '0'
)port map (
Q => drr_Overrun_int_cdc_from_spi_d3,
C => Bus2IP_Clk,
D => drr_Overrun_int_cdc_from_spi_d2,
R => Soft_Reset_op
);
--drr_Overrun_int_cdc_to_axi <= drr_Overrun_int_cdc_from_spi_d2 xor drr_Overrun_int_cdc_from_spi_d1;
drr_Overrun_int_cdc_to_axi <= drr_Overrun_int_cdc_from_spi_d3 xor drr_Overrun_int_cdc_from_spi_d2; -- 2/21/2012
end generate LOGIC_GENERATION_FDR ;
LOGIC_GENERATION_CDC : if Async_Clk = 1 generate
--==============================================================================
CMD_ERR_S2AX_1: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SPISR_0_CMD_Error_cdc_from_spi ,
scndry_aclk => Bus2IP_Clk ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Soft_Reset_op ,
scndry_out => SPISR_0_CMD_Error_cdc_to_axi
);
--==============================================================================
SPISEL_D1_REG_S2AX_1: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => spisel_d1_reg_cdc_from_spi ,
scndry_aclk => Bus2IP_Clk ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Soft_Reset_op ,
scndry_out => spisel_d1_reg_cdc_to_axi
);
--==============================================================================
SPISEL_PULSE_STRETCH_1: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_cdc_to_spi = '1') then
spisel_pulse_cdc_from_spi_int_2 <= '0';
else
spisel_pulse_cdc_from_spi_int_2 <= --((not SPISSR_cdc_from_axi_d1_and_reduce) and
spisel_pulse_cdc_from_spi xor
spisel_pulse_cdc_from_spi_int_2;
end if;
end if;
end process SPISEL_PULSE_STRETCH_1;
SPISEL_PULSE_S2AX_1_CDC: component FDR
generic map(INIT => '1'
)port map (
Q => spisel_pulse_cdc_from_spi_d1,
C => Bus2IP_Clk,
D => spisel_pulse_cdc_from_spi_int_2, -- spisel_pulse_cdc_from_spi,
R => Soft_Reset_op
);
SPISEL_PULSE_S2AX_2: component FDR
generic map(INIT => '1'
)port map (
Q => spisel_pulse_cdc_from_spi_d2,
C => Bus2IP_Clk,
D => spisel_pulse_cdc_from_spi_d1,
R => Soft_Reset_op
);
SPISEL_PULSE_S2AX_3: component FDR -- 2/21/2012
generic map(INIT => '1'
)port map (
Q => spisel_pulse_cdc_from_spi_d3,
C => Bus2IP_Clk,
D => spisel_pulse_cdc_from_spi_d2,
R => Soft_Reset_op
);
SPISEL_PULSE_S2AX_4: component FDR -- 2/21/2012
generic map(INIT => '1'
)port map (
Q => spisel_pulse_cdc_from_spi_d4,
C => Bus2IP_Clk,
D => spisel_pulse_cdc_from_spi_d3,
R => Soft_Reset_op
);
-- spisel_pulse_cdc_to_axi <= spisel_pulse_cdc_from_spi_d2 xor spisel_pulse_cdc_from_spi_d1;
spisel_pulse_cdc_to_axi <= spisel_pulse_cdc_from_spi_d3 xor spisel_pulse_cdc_from_spi_d4;
--==============================================================================
MST_N_SLV_MODE_S2AX_1: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_cdc_to_spi ,
prmry_in => Mst_N_Slv_mode_cdc_from_spi ,
scndry_aclk => Bus2IP_Clk ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Soft_Reset_op ,
scndry_out => Mst_N_Slv_mode_cdc_to_axi
);
--==============================================================================
SLAVE_MODF_STROBE_STRETCH_1_CDC: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_cdc_to_spi = '1') then
Slave_MODF_strobe_cdc_from_spi_int_2 <= '0';
--Slave_MODF_strobe_cdc_from_spi_d1 <= '0';
else
Slave_MODF_strobe_cdc_from_spi_int_2 <= Slave_MODF_strobe_cdc_from_spi xor
Slave_MODF_strobe_cdc_from_spi_int_2;
--Slave_MODF_strobe_cdc_from_spi_d1 <= Slave_MODF_strobe_cdc_from_spi_int_2;
end if;
end if;
end process SLAVE_MODF_STROBE_STRETCH_1_CDC;
SLV_MODF_STRB_S2AX_1: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 2 is ack based level sync
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_cdc_to_spi ,
prmry_in => Slave_MODF_strobe_cdc_from_spi_int_2,--Slave_MODF_strobe_cdc_from_spi_d1 ,
scndry_aclk => Bus2IP_Clk ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Soft_Reset_op ,
scndry_out => Slave_MODF_strobe_cdc_from_spi_d2
);
SLAVE_MODF_STROBE_STRETCH_1: process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk= '1') then
Slave_MODF_strobe_cdc_from_spi_d3 <= Slave_MODF_strobe_cdc_from_spi_d2 ;
end if;
end process SLAVE_MODF_STROBE_STRETCH_1;
Slave_MODF_strobe_cdc_to_axi <= Slave_MODF_strobe_cdc_from_spi_d3 xor Slave_MODF_strobe_cdc_from_spi_d2;
--==============================================================================
MODF_STROBE_STRETCH_1_CDC: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_cdc_to_spi = '1') then
modf_strobe_cdc_from_spi_int_2 <= '0';
-- modf_strobe_cdc_from_spi_d1 <= '0';
else
modf_strobe_cdc_from_spi_int_2 <= modf_strobe_cdc_from_spi xor
modf_strobe_cdc_from_spi_int_2;
-- modf_strobe_cdc_from_spi_d1 <= modf_strobe_cdc_from_spi_int_2;
end if;
end if;
end process MODF_STROBE_STRETCH_1_CDC;
MODF_STROBE_S2AX_1: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 2 is ack based level sync
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_cdc_to_spi ,
prmry_in => modf_strobe_cdc_from_spi_int_2,--modf_strobe_cdc_from_spi_d1 ,
scndry_aclk => Bus2IP_Clk ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Soft_Reset_op ,
scndry_out => modf_strobe_cdc_from_spi_d2
);
MODF_STROBE_STRETCH_1: process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk= '1') then
modf_strobe_cdc_from_spi_d3 <= modf_strobe_cdc_from_spi_d2;
end if;
end process MODF_STROBE_STRETCH_1;
modf_strobe_cdc_to_axi <= modf_strobe_cdc_from_spi_d3 xor modf_strobe_cdc_from_spi_d2;
--==============================================================================
RX_FIFO_EMPTY_AX2S_1: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_cdc_to_spi ,
prmry_in => Rx_FIFO_Empty_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_cdc_to_spi ,
scndry_out => Rx_FIFO_Empty_cdc_to_spi
);
--==============================================================================
TX_FIFO_EMPTY_S2AX_1: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => Tx_FIFO_Empty_cdc_from_spi ,
scndry_aclk => Bus2IP_Clk ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Soft_Reset_op ,
scndry_out => Tx_FIFO_Empty_cdc_to_axi
);
--==============================================================================
TX_EMPT_4_SPISR_S2AX_1: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => Tx_FIFO_Empty_SPISR_cdc_from_spi ,
scndry_aclk => Bus2IP_Clk ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Soft_Reset_op ,
scndry_out => Tx_FIFO_Empty_SPISR_cdc_to_axi
);
--==============================================================================
TX_FIFO_FULL_AX2S_1: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => Tx_FIFO_Full_cdc_from_axi ,
scndry_aclk => Bus2IP_Clk ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Soft_Reset_op ,
scndry_out => Tx_FIFO_Full_cdc_to_spi
);
--==============================================================================
SPIXFER_DONE_S2AX_1: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => spiXfer_done_cdc_from_spi ,
scndry_aclk => Bus2IP_Clk ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Soft_Reset_op ,
scndry_out => spiXfer_done_cdc_to_axi
);
--==============================================================================
RX_FIFO_FULL_S2AX_1: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => Rx_FIFO_Full_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_cdc_to_spi ,
scndry_out => Rx_FIFO_Full_cdc_to_spi
);
--==============================================================================
SPI_XFER_DONE_STRETCH_1_CDC: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_cdc_to_spi = '1') then
spiXfer_done_cdc_from_spi_int_2 <= '0';
-- spiXfer_done_d1 <= '0';
else
spiXfer_done_cdc_from_spi_int_2 <= spiXfer_done_cdc_from_spi xor
spiXfer_done_cdc_from_spi_int_2;
-- spiXfer_done_d1 <= spiXfer_done_cdc_from_spi_int_2;
end if;
end if;
end process SPI_XFER_DONE_STRETCH_1_CDC;
SYNC_SPIXFER_DONE_S2AX_1: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 2 is ack based level sync
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_cdc_to_spi ,
prmry_in => spiXfer_done_cdc_from_spi_int_2,--spiXfer_done_cdc_from_spi_int_2,--spiXfer_done_d1 ,
scndry_aclk => Bus2IP_Clk ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Soft_Reset_op ,
scndry_out => spiXfer_done_d2
);
SPI_XFER_DONE_STRETCH_1: process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk= '1') then
spiXfer_done_d3 <= spiXfer_done_d2;
end if;
end process SPI_XFER_DONE_STRETCH_1;
spiXfer_done_cdc_to_axi_1 <= spiXfer_done_d2 xor spiXfer_done_d3;
--==============================================================================
DTR_UNDERRUN_S2AX_1: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => dtr_underrun_cdc_from_spi ,
scndry_aclk => Bus2IP_Clk ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Soft_Reset_op ,
scndry_out => dtr_underrun_cdc_to_axi
);
--==============================================================================
SPICR_0_LOOP_AX2S_1: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_cdc_to_spi ,
prmry_in => SPICR_0_LOOP_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_cdc_to_spi ,
scndry_out => SPICR_0_LOOP_cdc_to_spi
);
--==============================================================================
SPICR_1_SPE_AX2S_1: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_cdc_to_spi ,
prmry_in => SPICR_1_SPE_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_cdc_to_spi ,
scndry_out => SPICR_1_SPE_cdc_to_spi
);
--==============================================================================
SPICR_2_MST_N_SLV_AX2S_1: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SPICR_2_MST_N_SLV_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_cdc_to_spi ,
scndry_out => SPICR_2_MST_N_SLV_cdc_to_spi
);
--==============================================================================
SPICR_3_CPOL_AX2S_1: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SPICR_3_CPOL_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_cdc_to_spi ,
scndry_out => SPICR_3_CPOL_cdc_to_spi
);
--==============================================================================
SPICR_4_CPHA_AX2S_1: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SPICR_4_CPHA_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_cdc_to_spi ,
scndry_out => SPICR_4_CPHA_cdc_to_spi
);
--==============================================================================
SPICR_5_TXFIFO_AX2S_1: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SPICR_5_TXFIFO_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_cdc_to_spi ,
scndry_out => SPICR_5_TXFIFO_cdc_to_spi
);
--==============================================================================
SPICR_6_RXFIFO_RST_AX2S_1: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SPICR_6_RXFIFO_RST_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_cdc_to_spi ,
scndry_out => SPICR_6_RXFIFO_RST_cdc_to_spi
);
--==============================================================================
SPICR_7_SS_AX2S_1: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SPICR_7_SS_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_cdc_to_spi ,
scndry_out => SPICR_7_SS_cdc_to_spi
);
--==============================================================================
SPICR_8_TR_INHIBIT_AX2S_1: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SPICR_8_TR_INHIBIT_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_cdc_to_spi ,
scndry_out => SPICR_8_TR_INHIBIT_cdc_to_spi
);
--==============================================================================
SPICR_9_LSB_AX2S_1: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SPICR_9_LSB_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_cdc_to_spi ,
scndry_out => SPICR_9_LSB_cdc_to_spi
);
--==============================================================================
SR_3_MODF_AX2S_1: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SR_3_modf_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_cdc_to_spi ,
scndry_out => SR_3_modf_cdc_to_spi
);
--==============================================================================
SPISSR_SYNC_GEN_CDC: for i in 0 to C_NUM_SS_BITS-1 generate
attribute ASYNC_REG : string;
attribute ASYNC_REG of SPISSR_AX2S_1_CDC : label is "TRUE";
-----
begin
SPISSR_AX2S_1_CDC: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk,
prmry_resetn => Soft_Reset_op,
prmry_in => SPISSR_cdc_from_axi(i),
scndry_aclk => EXT_SPI_CLK,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_cdc_to_spi,
scndry_out => SPISSR_cdc_from_axi_d2(i)
);
end generate SPISSR_SYNC_GEN_CDC;
SPISSR_cdc_to_spi <= SPISSR_cdc_from_axi_d2;
-----------------------------------
DRR_OVERRUN_STRETCH_1_CDC: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_cdc_to_spi = '1') then
drr_Overrun_int_cdc_from_spi_int_2 <= '0';
-- drr_Overrun_int_cdc_from_spi_d1 <= '0';
else
drr_Overrun_int_cdc_from_spi_int_2 <= drr_Overrun_int_cdc_from_spi xor
drr_Overrun_int_cdc_from_spi_int_2;
--drr_Overrun_int_cdc_from_spi_d1 <= drr_Overrun_int_cdc_from_spi_int_2;
end if;
end if;
end process DRR_OVERRUN_STRETCH_1_CDC;
DRR_OVERRUN_S2AX_1: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 2 is ack based level sync
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_cdc_to_spi ,
prmry_in => drr_Overrun_int_cdc_from_spi_int_2,--drr_Overrun_int_cdc_from_spi_d1 ,
scndry_aclk => Bus2IP_Clk ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Soft_Reset_op ,
scndry_out => drr_Overrun_int_cdc_from_spi_d2
);
DRR_OVERRUN_STRETCH_1: process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk= '1') then
drr_Overrun_int_cdc_from_spi_d3 <= drr_Overrun_int_cdc_from_spi_d2;
end if;
end process DRR_OVERRUN_STRETCH_1;
drr_Overrun_int_cdc_to_axi <= drr_Overrun_int_cdc_from_spi_d3 xor drr_Overrun_int_cdc_from_spi_d2;
-------------------------------------------------------------
SPICR_RX_FIFO_Rst_en <= reset_RcFIFO_ptr_cdc_from_axi xor SPICR_RX_FIFO_Rst_en_d1;
SPICR_RX_FIFO_RST_REG_SPI_DOMAIN_P_CDC:process(Bus2IP_Clk)is
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = '1') then -- or reset_RX_FIFO_Rst_pulse = '1')then
SPICR_RX_FIFO_Rst_en_d1 <= '0';
else
SPICR_RX_FIFO_Rst_en_d1 <= SPICR_RX_FIFO_Rst_en;
end if;
end if;
end process SPICR_RX_FIFO_RST_REG_SPI_DOMAIN_P_CDC;
-------------------------------------------------
RX_FIFO_RST_AX2S_1: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => 1 --AXI to SPI as already 2 stages included
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SPICR_RX_FIFO_Rst_en_d1 ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_cdc_to_spi ,
scndry_out => SPICR_RX_FIFO_Rst_en_d2
);
--reset_RcFIFO_ptr_cdc_to_spi <= reset_RcFIFO_ptr_cdc_from_axi_d2;
RX_FIFO_RST_AX2S_1_CDC_1: component FDR
generic map(INIT => '0'
)port map (
Q => reset_RcFIFO_ptr_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_RX_FIFO_Rst_en_d2,
R => Rst_cdc_to_spi
);
RX_FIFO_RST_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => reset_RcFIFO_ptr_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => reset_RcFIFO_ptr_cdc_from_axi_d1,
R => Rst_cdc_to_spi
);
reset_RcFIFO_ptr_cdc_to_spi <= reset_RcFIFO_ptr_cdc_from_axi_d1 xor
reset_RcFIFO_ptr_cdc_from_axi_d2;
--reset_RcFIFO_ptr_cdc_to_spi <= reset_RcFIFO_ptr_cdc_from_axi_d2;
----------------------------------------------------------------------------------
SPICR_BITS_7_8_SYNC_GEN_CDC: for i in 1 downto 0 generate
attribute ASYNC_REG : string;
attribute ASYNC_REG of SPICR_BITS_7_8_AX2S_1_CDC : label is "TRUE";
begin
-----
SPICR_BITS_7_8_AX2S_1_CDC: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SPICR_bits_7_8_cdc_from_axi(i) ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_cdc_to_spi ,
scndry_out => SPICR_bits_7_8_cdc_from_axi_d2(i)
);
end generate SPICR_BITS_7_8_SYNC_GEN_CDC;
-------------------------------------
SPICR_bits_7_8_cdc_to_spi <= SPICR_bits_7_8_cdc_from_axi_d2;
SPISR_0_CMD_Error_cdc_from_spi_d2 <= '0';
spisel_d1_reg_cdc_from_spi_d2 <= '0';
Mst_N_Slv_mode_cdc_from_spi_d2 <= '0';
slave_MODF_strobe_cdc_from_spi_d1 <= '0';
modf_strobe_cdc_from_spi_d1 <= '0';
end generate LOGIC_GENERATION_CDC ;
end architecture imp;
---------------------
| gpl-2.0 | b3865f5c8085d7afd210e6ed30b3d157 | 0.411413 | 3.811672 | false | false | false | false |
rodrigofegui/UnB | 2017.1/Organização e Arquitetura de Computadores/Trabalhos/Trabalho 3/Codificação/RegBank/RegBank_TB.vhd | 1 | 3,922 | ----------------------------------------------------------------------------------
-- Responsáveis: Danillo Neves
-- Luiz Gustavo
-- Rodrigo Guimarães
-- Ultima mod.: 03/jun/2017
-- Nome do Módulo: TestBench do Banco de Registradores
-- Descrição: TestBench para o Conjunto de registradores com largura de
-- palavra parametrizável e com habilitação
----------------------------------------------------------------------------------
----------------------------------
-- Importando a biblioteca IEEE e especificando o uso dos estados lógicos
-- padrão
----------------------------------
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
----------------------------------
-- Definiçao da entidade
----------------------------------
entity RegBank_TB is
Generic (DATA_WIDTH : natural := 32;
ADDRESS_WIDTH : natural := 5;
AMOUNT_REG : natural := 32);
end RegBank_TB;
----------------------------------
-- Descritivo da operacionalidade da entidade
----------------------------------
architecture RegBank_TB_Op of RegBank_TB is
component RegBank is
Generic (DATA_WIDTH : natural := 32;
ADDRESS_WIDTH : natural := 5;
AMOUNT_REG : natural := 32);
Port (clk, wren : in std_logic;
radd1, radd2 : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
wadd : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
wdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
rdata1, rdata2: out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
type vector_array1 is array (natural range <>) of std_logic_vector(ADDRESS_WIDTH-1 downto 0);
type vector_array2 is array (natural range <>) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal CLK : std_logic := '0';
constant PERIOD : time := 5 ps;
signal WREN : std_logic;
signal RADD1, RADD2 : std_logic_vector(ADDRESS_WIDTH - 1 downto 0);
signal WADD : std_logic_vector(ADDRESS_WIDTH - 1 downto 0);
signal WDATA : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal RDATA1, RDATA2 : std_logic_vector(DATA_WIDTH - 1 downto 0);
begin
CLK <= not CLK after PERIOD;
RB_TB: RegBank port map
(CLK, WREN,
RADD1, RADD2,
WADD,
WDATA,
RDATA1, RDATA2);
teste: process
variable init0 : std_logic := '0';
variable init1 : std_logic_vector(ADDRESS_WIDTH - 1 downto 0) := (others => '0');
variable init2 : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
variable ender : vector_array1(7 downto 0);
variable valor : vector_array2(15 downto 0);
begin
WREN <= init0;
RADD1 <= init1;
RADD2 <= init1;
WADD <= init1;
WDATA <= init2;
RDATA1 <= init2;
RDATA2 <= init2;
ender(0) := "00000";
ender(1) := "11111";
ender(2) := "00110";
ender(3) := "01101";
ender(4) := "00011";
ender(5) := "01010";
ender(6) := "01110";
ender(7) := "00010";
valor(0) := x"00025900";
valor(1) := x"00026797";
valor(2) := x"00092430";
valor(3) := x"00059664";
valor(4) := x"00008572";
valor(5) := x"00004416";
valor(6) := x"00000016";
valor(7) := x"00030581";
valor(8) := x"00006963";
valor(9) := x"00009871";
valor(10) := x"00091257";
valor(11) := x"00082022";
valor(12) := x"00089633";
valor(13) := x"00058236";
valor(14) := x"00052965";
valor(15) := x"00000001";
for var1 in std_logic range '0' to '1' loop
WREN <= var1;
wait for PERIOD;
for var2 in ender'range loop
WADD <= ender(var2);
wait for PERIOD;
for var3 in valor'range loop
WDATA <= valor(var3);
wait for PERIOD;
report "Testando WREN = " & std_logic'image(WREN) severity NOTE;
report "Testando WADD = " & integer'image(to_integer(unsigned(WADD))) & " e WDATA = " & integer'image(to_integer(unsigned(WDATA))) severity NOTE;
end loop;
end loop;
end loop;
wait for PERIOD;
end process teste;
end architecture RegBank_TB_Op; | gpl-3.0 | 0b9a4a1e6a12f2721bd6ffa6ac566641 | 0.574278 | 3.055469 | false | false | false | false |
pkerling/ethernet_mac_test | ethernet_mac_test_tb.vhd | 1 | 4,838 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library ethernet_mac;
use ethernet_mac.framing_common.all;
use ethernet_mac.crc32.all;
entity ethernet_mac_test_tb is
end entity;
architecture behavioral of ethernet_mac_test_tb is
alias logic_vector_t is std_logic_vector;
--Inputs
signal clock_125_i : std_ulogic := '0';
signal mii_tx_clk_i : std_ulogic := '0';
signal mii_rx_clk_i : std_ulogic := '0';
signal mii_rx_er_i : std_ulogic := '0';
signal mii_rx_dv_i : std_ulogic := '0';
signal mii_rxd_i : logic_vector_t(7 downto 0) := (others => '0');
--BiDirs
signal mdio_io : std_ulogic;
--Outputs
signal phy_reset_o : std_ulogic;
signal mdc_o : std_ulogic;
signal mii_tx_er_o : std_ulogic;
signal mii_tx_en_o : std_ulogic;
signal mii_txd_o : logic_vector_t(7 downto 0);
signal gmii_gtx_clk_o : std_ulogic;
signal led_o : logic_vector_t(3 downto 0);
signal user_led_o : std_ulogic;
-- Clock period definitions
constant clock_125_i_period : time := 8 ns;
constant mii_tx_clk_i_period : time := 40 ns;
constant mii_rx_clk_i_period : time := 40 ns;
constant mii_rx_setup : time := 2 ns;
constant mii_rx_hold : time := 0 ns;
constant SPEED_10100 : boolean := FALSE;
type t_memory is array (natural range <>) of logic_vector_t(7 downto 0);
-- ICMP Ping Request
constant test_packet : t_memory := (
x"FF", x"FF", x"FF", x"FF", x"FF", x"FF",
x"54", x"EE", x"75", x"34", x"2a", x"7e",
x"08", x"00",
x"45", x"00", x"00", x"54", x"c0", x"04", x"40", x"00", x"40",
x"01", x"f5", x"4c",
x"c0", x"a8", x"01", x"05",
x"c0", x"a8", x"01", x"01",
x"08", x"00",
x"95", x"80",
x"0c", x"4f", x"00", x"01",
x"b6", x"c4", x"7d", x"55", x"00", x"00", x"00", x"00",
x"5f", x"42", x"04", x"00", x"00", x"00", x"00", x"00",
x"10", x"11", x"12", x"13", x"14", x"15", x"16", x"17", x"18", x"19", x"1a", x"1b",
x"1c", x"1d", x"1e", x"1f", x"20", x"21", x"22", x"23", x"24", x"25", x"26", x"27", x"28",
x"29", x"2a", x"2b", x"2c", x"2d", x"2e", x"2f", x"30", x"31", x"32", x"33", x"34", x"35",
x"36", x"37"
);
begin
-- Instantiate the Unit Under Test (UUT)
uut : entity work.ethernet_mac_test port map(
clock_125_i => clock_125_i,
phy_reset_o => phy_reset_o,
mdc_o => mdc_o,
mdio_io => mdio_io,
mii_tx_clk_i => mii_tx_clk_i,
mii_tx_er_o => mii_tx_er_o,
mii_tx_en_o => mii_tx_en_o,
mii_txd_o => mii_txd_o,
mii_rx_clk_i => mii_rx_clk_i,
mii_rx_er_i => mii_rx_er_i,
mii_rx_dv_i => mii_rx_dv_i,
mii_rxd_i => mii_rxd_i,
gmii_gtx_clk_o => gmii_gtx_clk_o,
led_o => led_o,
user_led_o => user_led_o
);
-- Clock process definitions
clock_125_i_process : process
begin
clock_125_i <= '0';
wait for clock_125_i_period / 2;
clock_125_i <= '1';
wait for clock_125_i_period / 2;
end process;
mii_tx_clk_i_process : process
begin
mii_tx_clk_i <= '0';
wait for mii_tx_clk_i_period / 2;
mii_tx_clk_i <= '1';
wait for mii_tx_clk_i_period / 2;
end process;
-- Stimulus process
stim_proc : process is
procedure mii_put1(
-- lolisim
-- crashes if (others => '0') is used instead of "00000000"
data : in logic_vector_t(7 downto 0) := "00000000";
dv : in std_ulogic := '1';
er : in std_ulogic := '0') is
begin
mii_rx_clk_i <= '0';
mii_rx_dv_i <= dv;
mii_rx_er_i <= er;
mii_rxd_i <= data;
wait for mii_rx_clk_i_period / 2;
mii_rx_clk_i <= '1';
wait for mii_rx_clk_i_period / 2;
end procedure;
procedure mii_put(
data : in logic_vector_t(7 downto 0) := "00000000";
dv : in std_ulogic := '1';
er : in std_ulogic := '0') is
begin
if SPEED_10100 = TRUE then
mii_put1("0000" & data(3 downto 0), dv, er);
mii_put1("0000" & data(7 downto 4), dv, er);
else
mii_put1(data, dv, er);
end if;
end procedure;
procedure mii_toggle is
begin
mii_put(dv => '0', er => '0', data => open);
end procedure;
variable fcs : t_crc32;
begin
wait until phy_reset_o = '1';
wait for clock_125_i_period * 1100;
while TRUE loop
for i in 0 to 10 loop
mii_toggle;
end loop;
mii_put(logic_vector_t(START_FRAME_DELIMITER_DATA));
fcs := (others => '1');
for j in test_packet'range loop
mii_put(test_packet(j));
fcs := update_crc32(fcs, std_ulogic_vector(test_packet(j)));
end loop;
-- for j in 1 to 1000 loop
-- mii_put(x"23");
-- end loop;
for b in 0 to 3 loop
mii_put(logic_vector_t(fcs_output_byte(fcs, b)));
end loop;
while TRUE loop
mii_toggle;
end loop;
end loop;
wait;
end process;
end architecture;
| bsd-3-clause | 5b3dcb937fafa9c7399071045bcac7b5 | 0.553535 | 2.414172 | false | false | false | false |
jmarcelof/Phoenix | NoC/Phoenix_switchcontrol.vhd | 2 | 13,028 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
use work.HammingPack16.all;
use work.NoCPackage.all;
entity SwitchControl is
generic(address : regflit := (others=>'0'));
port(
clock : in std_logic;
reset : in std_logic;
h : in regNport; -- solicitacoes de chaveamento
ack_h : out regNport; -- resposta para as solitacoes de chaveamento
data : in arrayNport_regflit; -- dado do buffer (contem o endereco destino)
c_ctrl : in std_logic; -- indica se foi lido ou criado de um pacote de controle pelo buffer
c_CodControle : in regflit; -- codigo de controle do pacote de controle (terceiro flit do pacote de controle)
c_BuffCtrl : in buffControl; -- linha correspondente a tabela de roteamento lido do pacote de controle que sera escrita na tabela
c_buffTabelaFalhas_in: in row_FaultTable_Nport_Ports;
c_ce : in std_logic; -- chip enable da tabela de roteamento. Indica que sera escrito na tabela de roteamento
c_ceTF_in : in regNport; -- ce (chip enable) para escrever/atualizar a tabela de falhas
c_error_dir: out regNport; -- indica qual direcao/porta de saida o pacote sera encaminhado
c_error_ArrayFind: out ArrayRouterControl; -- indica se terminou de achar uma porta de saida para o pacote conforme a tabela de roteamento
c_tabelaFalhas : out row_FaultTable_Ports; -- tabela de falhas atualizada/final
c_strLinkTst : in regNport; -- (start link test) indica que houve um pacote de controle do tipo TEST_LINKS para testar os links
c_faultTableFDM : in regNPort; -- tabela de falhas gerado pelo teste de links
sender : in regNport;
free : out regNport; -- portas de saida que estao livres
mux_in : out arrayNport_reg3;
mux_out : out arrayNport_reg3;
row_FaultTablePorts_in: in row_FaultTable_Ports; -- linhas a serem escritas na tabela (do FFPM)
write_FaultTable: in regHamm_Nport); -- sinal para indicar escrita na tabela (do FPPM)
end SwitchControl;
architecture RoutingTable of SwitchControl is
type state is (S0,S1,S2,S3,S4,S5);
signal ES, PES: state;
-- sinais do arbitro
signal ask: std_logic := '0';
signal sel,prox: integer range 0 to (NPORT-1) := 0;
signal incoming: reg3 := (others=> '0');
signal header : regflit := (others=> '0');
signal ready, enable : std_logic;
-- sinais do controle
signal indice_dir: integer range 0 to (NPORT-1) := 0;
signal auxfree: regNport := (others=> '0');
signal source: arrayNport_reg3 := (others=> (others=> '0'));
signal sender_ant: regNport := (others=> '0');
signal dir: std_logic_vector(NPORT-1 downto 0):= (others=> '0');
signal requests: regNport := (others=> '0');
-- sinais de controle da tabela
signal find: RouterControl;
signal ceTable: std_logic := '0';
-- sinais de controle de atualizacao da tabela de falhas
signal c_ceTF : std_logic := '0';
signal c_buffTabelaFalhas : row_FaultTable_Ports := (others=>(others=>'0'));
--sinais da Tabela de Falhas
signal tabelaDeFalhas : row_FaultTable_Ports := (others=>(others=>'0'));
signal c_checked: regNPort:= (others=>'0');
signal c_checkedArray: arrayRegNport :=(others=>(others=>'0'));
signal dirBuff : std_logic_vector(NPORT-1 downto 0):= (others=> '0');
signal strLinkTstAll : std_logic := '0';
signal ant_c_ceTF_in: regNPort:= (others=>'0');
signal selectedOutput : integer := 0;
signal isOutputSelected : std_logic;
begin
ask <= '1' when OR_REDUCTION(h) else '0';
incoming <= CONV_VECTOR(sel);
header <= data(to_integer(unsigned(incoming)));
RoundRobinArbiter : entity work.arbiter(RoundRobinArbiter)
generic map(size => requests'length)
port map(
requests => h,
enable => enable,
selectedOutput => prox,
isOutputSelected => ready
);
------------------------------------------------------------
--gravacao da tabela de falhas
------------------------------------------------------------
--registrador para tabela de falhas
process(reset,clock)
begin
if reset='1' then
tabelaDeFalhas <= (others=>(others=>'0'));
elsif clock'event and clock='0' then
ant_c_ceTF_in <= c_ceTF_in;
-- se receber um pacote de controle para escrever/atualizar a tabela, escreve na tabela conforme a tabela recebida no pacote
if c_ceTF='1' then
tabelaDeFalhas <= c_buffTabelaFalhas;
-- se tiver feito o teste dos links, atualiza a tabela de falha conforme o resultado do teste
elsif strLinkTstAll = '1' then
--tabelaDeFalhas <= c_faultTableFDM;
tabelaDeFalhas(EAST)((3*COUNTERS_SIZE+1) downto 3*COUNTERS_SIZE) <= c_faultTableFDM(EAST) & '0';
tabelaDeFalhas(WEST)((3*COUNTERS_SIZE+1) downto 3*COUNTERS_SIZE) <= c_faultTableFDM(WEST) & '0';
tabelaDeFalhas(NORTH)((3*COUNTERS_SIZE+1) downto 3*COUNTERS_SIZE) <= c_faultTableFDM(NORTH) & '0';
tabelaDeFalhas(SOUTH)((3*COUNTERS_SIZE+1) downto 3*COUNTERS_SIZE) <= c_faultTableFDM(SOUTH) & '0';
-- escrita na tabela de falhas pelo FPPM
elsif (unsigned(write_FaultTable) /= 0) then
-- escreve apenas se o sinal de escrit tiver ativo e se o sttus do link tiver uma severidade maior ou igual a contida na tabela
for i in 0 to HAMM_NPORT-1 loop
if (write_FaultTable(i) = '1' and row_FaultTablePorts_in(i)((3*COUNTERS_SIZE+1) downto 3*COUNTERS_SIZE) >= tabelaDeFalhas(i)((3*COUNTERS_SIZE+1) downto 3*COUNTERS_SIZE)) then
tabelaDeFalhas(i) <= row_FaultTablePorts_in(i);
end if;
end loop;
end if;
end if;
end process;
-- '1' se em algum buffer houve o pedido de teste de link (por causa do pacote de controle do tipo TEST_LINKS)
strLinkTstAll <= '1' when OR_REDUCTION(c_strLinkTst) else '0';
-- "merge" das telas recebidas
process(c_ceTF_in)
variable achou: regHamm_Nport := (others=>'0');
begin
for i in 0 to NPORT-1 loop
if (ant_c_ceTF_in(i)='1' and c_ceTF_in(i)='0') then
achou := (others=>'0');
exit;
end if;
end loop;
-- pergunta para cada buffer quais que desejam escrever na tabela e, conforme os que desejam, copia as linhas da tabela do buffer que tiver como falha
for i in 0 to NPORT-1 loop
for j in 0 to HAMM_NPORT-1 loop
if (achou(j)='0' and c_ceTF_in(i)='1' and c_buffTabelaFalhas_in(i)(j)((3*COUNTERS_SIZE+1) downto 3*COUNTERS_SIZE) = "10") then
c_buffTabelaFalhas(j) <= c_buffTabelaFalhas_in(i)(j);
achou(j) := '1';
end if;
end loop;
end loop;
-- pergunta para cada buffer quais que desejam escrever na tabela e, conforme os que desejam, copia as linhas da tabela do buffer que tiver como tendencia de falha
for i in 0 to NPORT-1 loop
for j in 0 to HAMM_NPORT-1 loop
if (achou(j)='0' and c_ceTF_in(i)='1' and c_buffTabelaFalhas_in(i)(j)((3*COUNTERS_SIZE+1) downto 3*COUNTERS_SIZE) = "01") then
c_buffTabelaFalhas(j) <= c_buffTabelaFalhas_in(i)(j);
achou(j) := '1';
end if;
end loop;
end loop;
-- pergunta para cada buffer quais que desejam escrever na tabela e, conforme os que desejam, copia as linhas da tabela do buffer que tiver como sem falha
for i in 0 to NPORT-1 loop
for j in 0 to HAMM_NPORT-1 loop
if (achou(j)='0' and c_ceTF_in(i)='1' and c_buffTabelaFalhas_in(i)(j)((3*COUNTERS_SIZE+1) downto 3*COUNTERS_SIZE) = "00") then
c_buffTabelaFalhas(j) <= c_buffTabelaFalhas_in(i)(j);
achou(j) := '1';
end if;
end loop;
end loop;
end process;
-- '1' se em algum buffer tiver habilita o ce para escrever/atualizar a tabela de falhas
c_ceTF <= '1' when OR_REDUCTION(c_ceTF_in) else '0';
process(clock,reset)
begin
c_error_ArrayFind <= (others=>invalidRegion);
c_error_ArrayFind(sel) <= find;
end process;
c_error_dir <= dir;
c_tabelafalhas <= tabelaDeFalhas;
RoutingMechanism : entity work.routingMechanism
generic map(address => address)
port map(
clock => clock,
reset => reset,
buffCtrl => c_BuffCtrl, -- linha correspondente a tabela de roteamento lido do pacote de controle que sera escrita na tabela
ctrl=> c_Ctrl, -- indica se foi lido ou criado de um pacote de controle pelo buffer
operacao => c_CodControle, -- codigo de controle do pacote de controle (terceiro flit do pacote de controle)
ceT => c_ce, -- chip enable da tabela de roteamento. Indica que sera escrito na tabela de roteamento
oe => ceTable, -- usado para solicitar direcao/porta destino para a tabela de roteamento
dest => header, -- primeiro flit/header do pacote (contem o destino do pacote)
inputPort => sel, -- porta de entrada selecionada pelo arbitro para ser chaveada
outputPort => dir, -- indica qual porta de saida o pacote sera encaminhado
find => find -- indica se terminou de achar uma porta de saida para o pacote conforme a tabela de roteamento
);
FixedPriorityArbiter : entity work.arbiter(FixedPriorityArbiter)
generic map(size => requests'length)
port map(
requests => requests,
enable => '1',
isOutputSelected => isOutputSelected,
selectedOutput => selectedOutput
);
process(reset,clock)
begin
if reset='1' then
ES<=S0;
elsif clock'event and clock='1' then
ES<=PES;
end if;
end process;
process(ES, ask, find, isOutputSelected)
begin
case ES is
when S0 => PES <= S1;
when S1 =>
if ask='1' then
PES <= S2;
else
PES <= S1;
end if;
when S2 => PES <= S3;
when S3 =>
if(find = validRegion)then
if (isOutputSelected = '1') then
PES <= S4;
else
PES <= S1;
end if;
elsif(find = portError)then
PES <= S1;
else
PES <= S3;
end if;
when S4 => PES <= S5;
when S5 => PES <= S1;
end case;
end process;
------------------------------------------------------------------------------------------------------
-- executa as acoes correspondente ao estado atual da maquina de estados
------------------------------------------------------------------------------------------------------
process(clock)
begin
if clock'event and clock='1' then
case ES is
-- Zera variaveis
when S0 =>
ceTable <= '0';
sel <= 0;
ack_h <= (others => '0');
auxfree <= (others=> '1');
sender_ant <= (others=> '0');
mux_out <= (others=>(others=>'0'));
source <= (others=>(others=>'0'));
-- Chegou um header
when S1=>
enable <= ask;
ceTable <= '0';
ack_h <= (others => '0');
-- Seleciona quem tera direito a requisitar roteamento
when S2=>
sel <= prox;
enable <= not ready;
-- Aguarda resposta da Tabela
when S3 =>
if(find = validRegion and isOutputSelected = '1') then
indice_dir <= selectedOutput;
else
ceTable <= '1';
end if;
when S4 =>
source(to_integer(unsigned(incoming))) <= CONV_VECTOR(indice_dir);
mux_out(indice_dir) <= incoming;
auxfree(indice_dir) <= '0';
ack_h(sel) <= '1';
when others =>
ack_h(sel) <= '0';
ceTable <= '0';
end case;
sender_ant <= sender;
for i in EAST to LOCAL loop
if sender(i) = '0' and sender_ant(i) = '1' then
auxfree(to_integer(unsigned(source(i)))) <= '1';
end if;
end loop;
end if;
end process;
mux_in <= source;
free <= auxfree;
requests <= auxfree AND dir;
end RoutingTable;
| lgpl-3.0 | ce8bbe69f05c411a964940e32b24420e | 0.552119 | 4.236748 | false | false | false | false |
jobisoft/jTDC | modules/VFB6/disc16/Controller_DAC8218.vhd | 1 | 5,946 | -------------------------------------------------------------------------
---- ----
---- Company : ELB-Elektroniklaboratorien Bonn UG ----
---- (haftungsbeschränkt) ----
---- ----
-------------------------------------------------------------------------
---- ----
---- Copyright (C) 2015 ELB ----
---- ----
---- This program is free software; you can redistribute it and/or ----
---- modify it under the terms of the GNU General Public License as ----
---- published by the Free Software Foundation; either version 3 of ----
---- the License, or (at your option) any later version. ----
---- ----
---- This program is distributed in the hope that it will be useful, ----
---- but WITHOUT ANY WARRANTY; without even the implied warranty of ----
---- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ----
---- GNU General Public License for more details. ----
---- ----
---- You should have received a copy of the GNU General Public ----
---- License along with this program; if not, see ----
---- <http://www.gnu.org/licenses>. ----
---- ----
-------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Controller_DAC8218 is
Port ( CLK : in STD_LOGIC; -- system clock
SCLK, CS, SDO : out STD_LOGIC :='0'; -- Clock, Chip Select, and data out (to dac)
SDI : in STD_LOGIC; -- data in from DAC
ADDR : in STD_LOGIC_VECTOR (4 downto 0); -- address for read / write
DATA_Read : out STD_LOGIC_VECTOR (15 downto 0):=(others=>'0'); -- Data to read
DATA_Write : in STD_LOGIC_VECTOR (15 downto 0); -- Data to write
WR, RD : in STD_LOGIC; -- commands: write and read.
busy, Data_Update : out STD_LOGIC :='0'; -- indicates if interfaca is being used, data_update indicates end of read cycle / updated data at output port.
CLK_DIVIDER : in STD_LOGIC_VECTOR (3 downto 0)); -- clock prescaler for SCLK
end Controller_DAC8218;
architecture Behavioral of Controller_DAC8218 is
Signal CLK_Div_count : STD_LOGIC_VECTOR (3 downto 0) :="0000";
Signal CE : STD_LOGIC :='0';
-- id read or write command occurs
-- the command is latched
signal reading, writing : STD_LOGIC :='0';
-- also the data to write:
signal data_to_write : STD_LOGIC_VECTOR(15 downto 0):=(others=>'0');
-- and the address:
signal latched_address: STD_LOGIC_Vector (4 downto 0):=(others=>'0');
-- counter for SCLK
Signal SPI_Counter : unsigned (5 downto 0):=to_unsigned(0,6);
-- register for chip select, so it's possible to read back its value.
Signal CS_Register : STD_LOGIC :='1'; -- initiate with 1 due to inverted logic
-- same for SCLK
Signal SCLK_Register: STD_LOGIC:='0';
--Shift register for SPI
Signal ShiftRegister : STD_LOGIC_VECTOR(23 downto 0);
begin
--- genreate clock enable signal. will be used to scale down the internal clock.
--- maximum SCLK is 25MHz for the DAC8218 for VCCO=3V
Generate_Clockenable: process (CLK) is begin
if rising_edge(CLK) then
if CLK_Div_count="0000" then
CE<='1';
CLK_Div_count<=CLK_DIVIDER;
else
CE<='0';
CLK_Div_count<= std_logic_vector (unsigned(CLK_Div_count)-1);
end if;
end if;
end process;
busy<=reading OR Writing or WR or rd;
CS<=CS_Register;
SCLK<=SCLK_Register;
SPI_comm: Process (CLK) is begin
if rising_edge(CLK) then
Data_Update<='0';
if reading='0' and writing='0' then
if WR='1' then
writing<='1';
latched_address<=ADDR;
data_to_write<=DATA_Write;
elsif RD='1' then
reading<='1';
latched_address<=ADDR;
end if;
elsif CE='1' then
if CS_Register='0' then
if SCLK_Register ='0' then -- on rising edge of SCLK
SPI_Counter<=SPI_Counter+1; -- increase count of generated clocks
-- load shift register serially during transfer
ShiftRegister(23 downto 1)<=ShiftRegister(22 downto 0);
ShiftRegister(0) <= SDI;
SDO<=Shiftregister(23);
if SPI_Counter=to_unsigned(24,6) then -- when 24 clocks are generated
CS_Register<='1'; -- finish transfer by disabeling CS (invertet logic)
reading<='0';
writing<='0';
SDO<='0';
--if reading = '1' then -- condition removed, because in the datasheet a write cycle is used to read (read cycle only to initiate)
Data_Update<='1';
DATA_Read(15 downto 1) <= ShiftRegister(14 downto 0);
DATA_Read(0)<=SDI;
--end if;
else
SCLK_Register<=Not SCLK_Register;
end if;
else
SCLK_Register<=Not SCLK_Register;
end if;
elsif reading='1' or writing='1' then
CS_Register<='0';
SPI_Counter<=to_unsigned(0,6);
-- load shift register parallely:
ShiftRegister(23)<=reading; --bit defines if access is read or write, 0=write
ShiftRegister(22 downto 21) <="00"; --bits are always don't care (however a command is 24 bit long)
ShiftRegister(20 downto 16) <= latched_address;
ShiftRegister(15 downto 0) <= data_to_write;
end if;
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | 9d6df21018717a0191237cff7760d8ff | 0.558284 | 4.083104 | false | false | false | false |
TimingKeepers/gen-ugr-cores | modules/wishbone/wb_i2c_arb/i2c_arbiter_ss_detector.vhd | 1 | 4,527 | -------------------------------------------------------------------------------
-- Title : I2C Bus Arbiter Start/Stop detector
-- Project : White Rabbit Project
-------------------------------------------------------------------------------
-- File : i2c_arbiter_ss_detector.vhd
-- Author : Miguel Jimenez Lopez
-- Company : UGR
-- Created : 2015-09-06
-- Last update: 2015-09-06
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
--
-- This component allows to detect the START and STOP condition in a I2C bus.
--
-------------------------------------------------------------------------------
-- TODO:
-------------------------------------------------------------------------------
--
-- Copyright (c) 2015 UGR
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity i2c_arbiter_ss_detector is
port (
-- Clock & Reset
clk_i : in std_logic;
rst_n_i : in std_logic;
-- I2C input buses & ACK
input_sda_i : in std_logic;
input_scl_i : in std_logic;
start_ack_i : in std_logic;
stop_ack_i : in std_logic;
-- Start/Stop outputs
start_state_o : out std_logic;
stop_state_o : out std_logic
);
end i2c_arbiter_ss_detector;
architecture struct of i2c_arbiter_ss_detector is
-- Start FSM signals
type i2c_arb_start_st is (ARB_START_IDLE, ARB_START_WAIT_SDA, ARB_START_DETECTED);
signal arb_start_st : i2c_arb_start_st := ARB_START_IDLE;
-- Stop FSM signals
type i2c_arb_stop_st is (ARB_STOP_IDLE, ARB_STOP_WAIT_SDA, ARB_STOP_DETECTED);
signal arb_stop_st : i2c_arb_stop_st := ARB_STOP_IDLE;
begin
-- Start FSM
start_detector: process(clk_i,rst_n_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
arb_start_st <= ARB_START_IDLE;
start_state_o <= '0';
else
case arb_start_st is
when ARB_START_IDLE =>
start_state_o <= '0';
if input_sda_i = '1' and input_scl_i = '1' then
arb_start_st <= ARB_START_WAIT_SDA;
end if;
when ARB_START_WAIT_SDA =>
if input_scl_i = '1' then
if input_sda_i = '0' then
start_state_o <= '1';
arb_start_st <= ARB_START_DETECTED;
end if;
else
start_state_o <= '0';
arb_start_st <= ARB_START_IDLE;
end if;
when ARB_START_DETECTED =>
if start_ack_i = '1' then
start_state_o <= '0';
arb_start_st <= ARB_START_IDLE;
end if;
when others =>
start_state_o <= '0';
arb_start_st <= ARB_START_IDLE;
end case;
end if;
end if;
end process start_detector;
-- Stop FSM
stop_detector: process(clk_i, rst_n_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
arb_stop_st <= ARB_STOP_IDLE;
stop_state_o <= '0';
else
case arb_stop_st is
when ARB_STOP_IDLE =>
stop_state_o <= '0';
if input_scl_i = '1' and input_sda_i = '0' then
arb_stop_st <= ARB_STOP_WAIT_SDA;
end if;
when ARB_STOP_WAIT_SDA =>
if input_scl_i = '1' then
if input_sda_i = '1' then
stop_state_o <= '1';
arb_stop_st <= ARB_STOP_DETECTED;
end if;
else
stop_state_o <= '0';
arb_stop_st <= ARB_STOP_IDLE;
end if;
when ARB_STOP_DETECTED =>
if stop_ack_i = '1' then
stop_state_o <= '0';
arb_stop_st <= ARB_STOP_IDLE;
end if;
when others =>
stop_state_o <= '0';
arb_stop_st <= ARB_STOP_IDLE;
end case;
end if;
end if;
end process stop_detector;
end struct;
| gpl-2.0 | 52a2d394de870f67cbcdd088732c74fb | 0.534349 | 3.252155 | false | false | false | false |
dpolad/dlx | DLX_vhd/a.i-EXECUTEBLOCK.vhd | 1 | 3,138 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.myTypes.all;
entity execute_block is
generic (
SIZE : integer := 32
);
port (
IMM_i : in std_logic_vector(SIZE - 1 downto 0);
A_i : in std_logic_vector(SIZE - 1 downto 0);
rB_i : in std_logic_vector(4 downto 0);
rC_i : in std_logic_vector(4 downto 0);
MUXED_B_i : in std_logic_vector(SIZE - 1 downto 0);
S_MUX_ALUIN_i : in std_logic;
FW_X_i : in std_logic_vector(SIZE - 1 downto 0);
FW_W_i : in std_logic_vector(SIZE - 1 downto 0);
FW_4_i : in std_logic_vector(SIZE - 1 downto 0);
S_FW_A_i : in std_logic_vector(1 downto 0);
S_FW_B_i : in std_logic_vector(1 downto 0);
muxed_dest : out std_logic_vector(4 downto 0);
muxed_B : out std_logic_vector(SIZE -1 downto 0);
S_MUX_DEST_i : in std_logic_vector(1 downto 0);
OP : in AluOp;
ALUW_i : in std_logic_vector(12 downto 0);
DOUT : out std_logic_vector(SIZE - 1 downto 0);
stall_o : out std_logic;
Clock : in std_logic;
Reset : in std_logic
);
end execute_block;
architecture struct of execute_block is
component mux21
port (
IN0 : in std_logic_vector(SIZE - 1 downto 0);
IN1 : in std_logic_vector(SIZE - 1 downto 0);
CTRL : in std_logic;
OUT1 : out std_logic_vector(SIZE - 1 downto 0)
);
end component;
component mux41
generic (
MUX_SIZE : integer := 5
);
port (
IN0 : in std_logic_vector(MUX_SIZE - 1 downto 0);
IN1 : in std_logic_vector(MUX_SIZE - 1 downto 0);
IN2 : in std_logic_vector(MUX_SIZE - 1 downto 0);
IN3 : in std_logic_vector(MUX_SIZE - 1 downto 0);
CTRL : in std_logic_vector(1 downto 0);
OUT1 : out std_logic_vector(MUX_SIZE - 1 downto 0)
);
end component;
component real_alu
generic (
DATA_SIZE : integer := 32);
port (
IN1 : in std_logic_vector(DATA_SIZE - 1 downto 0);
IN2 : in std_logic_vector(DATA_SIZE - 1 downto 0);
--OP : in AluOp;
ALUW_i : in std_logic_vector(12 downto 0);
DOUT : out std_logic_vector(DATA_SIZE - 1 downto 0);
stall_o : out std_logic;
Clock : in std_logic;
Reset : in std_logic
);
end component;
signal FWB2mux : std_logic_vector(SIZE - 1 downto 0);
signal FWA2alu : std_logic_vector(SIZE - 1 downto 0);
signal FWB2alu : std_logic_vector(SIZE - 1 downto 0);
begin
ALUIN_MUX: mux21 port map(
IN0 => FWB2mux,
IN1 => IMM_i,
CTRL => S_MUX_ALUIN_i,
OUT1 => FWB2alu);
ALU: real_alu generic map (
DATA_SIZE => 32
)
port map (
IN1 => FWA2alu,
IN2 => FWB2alu,
-- OP => OP,
ALUW_i => ALUW_i,
DOUT => DOUT,
stall_o => stall_o,
Clock => Clock,
Reset => Reset
);
MUXDEST: mux41 generic map(
MUX_SIZE => 5
)
port map(
IN0 => "00000", -- THIS VALUE SHOULD NEVER APPEAR!!
IN1 => rC_i,
IN2 => rB_i,
IN3 => "11111",
CTRL => S_MUX_DEST_i,
OUT1 => muxed_dest
);
MUX_FWA: mux41 generic map(
MUX_SIZE => 32
)
port map(
IN0 => A_i,
IN1 => FW_X_i,
IN2 => FW_W_i,
IN3 => FW_4_i,
CTRL => S_FW_A_i,
OUT1 => FWA2alu
);
MUX_FWB: mux41 generic map(
MUX_SIZE => 32
)
port map(
IN0 => MUXED_B_i,
IN1 => FW_X_i,
IN2 => FW_W_i,
IN3 => FW_4_i,
CTRL => S_FW_B_i,
OUT1 => FWB2mux
);
muxed_B <= FWB2mux;
end struct;
| bsd-2-clause | 644be8a6ad9cbe7a21d79e75d34d5eaf | 0.62269 | 2.238231 | false | false | false | false |
jmarcelof/Phoenix | NoC/FPPM_AA00.vhd | 2 | 3,418 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
use work.HammingPack16.all;
use work.NoCPackage.regNport;
entity FPPM is
port
(
clock : in std_logic;
reset_in : in std_logic; -- reset geral da NoC
rx : in regHamm_Nport; -- rx (sinal que indica que estou recebendo transmissao)
statusHamming : in array_statusHamming; -- status (sem erro, erro corrigido, erro detectado) das 4 portas (EAST,WEST,NORTH,SOUTH)
write_FaultTable : out regHamm_Nport; -- sinal para indicar escrita na tabela de falhas
row_FaultTablePorts_out : out row_FaultTable_Ports -- linha a ser escrita na tabela de falhas
);
end FPPM;
architecture FPPM of FPPM is
-- CUIDADO! Os contadores tem apenas COUNTERS_SIZE bits!
constant N: integer range 1 to 31 := 8;
constant M: integer range 1 to 31 := 4;
constant P: integer range 1 to 31 := 30;
constant COUNTER_UPDATE_TABLE: integer := 1; -- numero de flits recebidos necessarios para atualizar a tabela
begin
FPPM_generate: for i in 0 to (HAMM_NPORT-1) generate
begin
process(clock, reset_in)
variable counter_write: integer range 0 to COUNTER_UPDATE_TABLE;
variable reset: std_logic := '0';
variable counter_N, counter_M, counter_P: unsigned((COUNTERS_SIZE-1) downto 0);
variable link_status: unsigned(1 downto 0) := "00";
begin
if (reset_in='1') then
reset := '0';
counter_N := (others=>'0');
counter_M := (others=>'0');
counter_P := (others=>'0');
write_FaultTable(i) <= '0';
row_FaultTablePorts_out(i) <= (others=>'0');
end if;
if (clock'event and clock='1' and rx(i)='1') then
--counter_write := counter_write + 1;
case statusHamming(i) is
when NE =>
counter_N := counter_N + 1;
if (counter_N = N) then
link_status := "00";
reset := '1';
end if;
when EC =>
counter_M := counter_M + 1;
if (counter_M = M) then
link_status := "01";
reset := '1';
end if;
when ED =>
counter_P := counter_P + 1;
if (counter_P = P) then
link_status := "10";
reset := '1';
end if;
when others => null;
end case;
if (reset = '1') then
reset := '0';
counter_N := (others=>'0');
counter_M := (others=>'0');
counter_P := (others=>'0');
end if;
if (counter_write = COUNTER_UPDATE_TABLE) then
--if (false) then
write_FaultTable(i) <= '1';
row_FaultTablePorts_out(i) <= std_logic_vector(link_status & counter_N & counter_M & counter_P);
counter_write := 0;
else
write_FaultTable(i) <= '0';
row_FaultTablePorts_out(i) <= (others=>'0');
end if;
elsif (rx(i)='0') then
write_FaultTable(i) <= '0';
row_FaultTablePorts_out(i) <= (others=>'0');
end if;
end process;
end generate;
end FPPM; | lgpl-3.0 | 303443e4e1d18a273599b89ffc056510 | 0.501463 | 4.083632 | false | false | false | false |
Hyperion302/omega-cpu | Hardware/Open16750/uart_16750.vhdl | 1 | 52,146 | --
-- UART 16750
--
-- Author: Sebastian Witt
-- Date: 29.01.2008
-- Version: 1.5
--
-- History: 1.0 - Initial version
-- 1.1 - THR empty interrupt register connected to RST
-- 1.2 - Registered outputs
-- 1.3 - Automatic flow control
-- 1.4 - De-assert IIR FIFO64 when FIFO is disabled
-- 1.5 - Inverted low active outputs when RST is active
--
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
-- Serial UART
entity uart_16750 is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
BAUDCE : in std_logic; -- Baudrate generator clock enable
CS : in std_logic; -- Chip select
WR : in std_logic; -- Write to UART
RD : in std_logic; -- Read from UART
A : in std_logic_vector(2 downto 0); -- Register select
DIN : in std_logic_vector(7 downto 0); -- Data bus input
DOUT : out std_logic_vector(7 downto 0); -- Data bus output
DDIS : out std_logic; -- Driver disable
INT : out std_logic; -- Interrupt output
OUT1N : out std_logic; -- Output 1
OUT2N : out std_logic; -- Output 2
RCLK : in std_logic; -- Receiver clock (16x baudrate)
BAUDOUTN : out std_logic; -- Baudrate generator output (16x baudrate)
RTSN : out std_logic; -- RTS output
DTRN : out std_logic; -- DTR output
CTSN : in std_logic; -- CTS input
DSRN : in std_logic; -- DSR input
DCDN : in std_logic; -- DCD input
RIN : in std_logic; -- RI input
SIN : in std_logic; -- Receiver input
SOUT : out std_logic -- Transmitter output
);
end uart_16750;
architecture rtl of uart_16750 is
-- UART transmitter
component uart_transmitter is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
TXCLK : in std_logic; -- Transmitter clock (2x baudrate)
TXSTART : in std_logic; -- Start transmitter
CLEAR : in std_logic; -- Clear transmitter state
WLS : in std_logic_vector(1 downto 0); -- Word length select
STB : in std_logic; -- Number of stop bits
PEN : in std_logic; -- Parity enable
EPS : in std_logic; -- Even parity select
SP : in std_logic; -- Stick parity
BC : in std_logic; -- Break control
DIN : in std_logic_vector(7 downto 0); -- Input data
TXFINISHED : out std_logic; -- Transmitter operation finished
SOUT : out std_logic -- Transmitter output
);
end component;
-- UART receiver
component uart_receiver is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
RXCLK : in std_logic; -- Receiver clock (16x baudrate)
RXCLEAR : in std_logic; -- Reset receiver state
WLS : in std_logic_vector(1 downto 0); -- Word length select
STB : in std_logic; -- Number of stop bits
PEN : in std_logic; -- Parity enable
EPS : in std_logic; -- Even parity select
SP : in std_logic; -- Stick parity
SIN : in std_logic; -- Receiver input
PE : out std_logic; -- Parity error
FE : out std_logic; -- Framing error
BI : out std_logic; -- Break interrupt
DOUT : out std_logic_vector(7 downto 0); -- Output data
RXFINISHED : out std_logic -- Receiver operation finished
);
end component;
-- UART interrupt control
component uart_interrupt is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
IER : in std_logic_vector(3 downto 0); -- IER 3:0
LSR : in std_logic_vector(4 downto 0); -- LSR 4:0
THI : in std_logic; -- Transmitter holding register empty interrupt
RDA : in std_logic; -- Receiver data available
CTI : in std_logic; -- Character timeout indication
AFE : in std_logic; -- Automatic flow control enable
MSR : in std_logic_vector(3 downto 0); -- MSR 3:0
IIR : out std_logic_vector(3 downto 0); -- IIR 3:0
INT : out std_logic -- Interrupt
);
end component;
-- UART baudrate generator
component uart_baudgen is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
CE : in std_logic; -- Clock enable
CLEAR : in std_logic; -- Reset generator (synchronization)
DIVIDER : in std_logic_vector(15 downto 0); -- Clock divider
BAUDTICK : out std_logic -- 16xBaudrate tick
);
end component;
-- UART FIFO
component slib_fifo is
generic (
WIDTH : integer := 8; -- FIFO width
SIZE_E : integer := 6 -- FIFO size (2^SIZE_E)
);
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
CLEAR : in std_logic; -- Clear FIFO
WRITE : in std_logic; -- Write to FIFO
READ : in std_logic; -- Read from FIFO
D : in std_logic_vector(WIDTH-1 downto 0); -- FIFO input
Q : out std_logic_vector(WIDTH-1 downto 0); -- FIFO output
EMPTY : out std_logic; -- FIFO is empty
FULL : out std_logic; -- FIFO is full
USAGE : out std_logic_vector(SIZE_E-1 downto 0) -- FIFO usage
);
end component;
-- Edge detect
component slib_edge_detect is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
D : in std_logic; -- Signal input
RE : out std_logic; -- Rising edge detected
FE : out std_logic -- Falling edge detected
);
end component;
-- Input synchronization
component slib_input_sync is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
D : in std_logic; -- Signal input
Q : out std_logic -- Signal output
);
end component;
-- Input filter
component slib_input_filter is
generic (
SIZE : natural := 4 -- Filter width
);
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
CE : in std_logic; -- Clock enable
D : in std_logic; -- Signal input
Q : out std_logic -- Signal output
);
end component;
-- Clock enable generation
component slib_clock_div is
generic (
RATIO : integer := 8 -- Clock divider ratio
);
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
CE : in std_logic; -- Clock enable input
Q : out std_logic -- New clock enable output
);
end component;
-- Global device signals
signal iCSWR : std_logic; -- Chipselect and write
signal iCSRD : std_logic; -- Chipselect and read
signal iWriteFE : std_logic; -- Write falling edge
signal iReadFE : std_logic; -- Read falling edge
signal iWrite : std_logic; -- Write to UART
signal iRead : std_logic; -- Read from UART
signal iA : std_logic_vector(2 downto 0); -- UART register address
signal iDIN : std_logic_vector(7 downto 0); -- UART data input
-- UART registers read/write signals
signal iRBRRead : std_logic; -- Read from RBR
signal iTHRWrite : std_logic; -- Write to THR
signal iDLLWrite : std_logic; -- Write to DLL
signal iDLMWrite : std_logic; -- Write to DLM
signal iIERWrite : std_logic; -- Write to IER
signal iIIRRead : std_logic; -- Read from IIR
signal iFCRWrite : std_logic; -- Write to FCR
signal iLCRWrite : std_logic; -- Write to LCR
signal iMCRWrite : std_logic; -- Write to MCR
signal iLSRRead : std_logic; -- Read from LSR
signal iMSRRead : std_logic; -- Read from MSR
signal iSCRWrite : std_logic; -- Write to SCR
-- UART registers
signal iTSR : std_logic_vector(7 downto 0); -- Transmitter holding register
signal iRBR : std_logic_vector(7 downto 0); -- Receiver buffer register
signal iDLL : std_logic_vector(7 downto 0); -- Divisor latch LSB
signal iDLM : std_logic_vector(7 downto 0); -- Divisor latch MSB
signal iIER : std_logic_vector(7 downto 0); -- Interrupt enable register
signal iIIR : std_logic_vector(7 downto 0); -- Interrupt identification register
signal iFCR : std_logic_vector(7 downto 0); -- FIFO control register
signal iLCR : std_logic_vector(7 downto 0); -- Line control register
signal iMCR : std_logic_vector(7 downto 0); -- Modem control register
signal iLSR : std_logic_vector(7 downto 0); -- Line status register
signal iMSR : std_logic_vector(7 downto 0); -- Modem status register
signal iSCR : std_logic_vector(7 downto 0); -- Scratch register
-- IER register signals
signal iIER_ERBI : std_logic; -- IER: Enable received data available interrupt
signal iIER_ETBEI : std_logic; -- IER: Enable transmitter holding register empty interrupt
signal iIER_ELSI : std_logic; -- IER: Enable receiver line status interrupt
signal iIER_EDSSI : std_logic; -- IER: Enable modem status interrupt
-- IIR register signals
signal iIIR_PI : std_logic; -- IIR: Pending interrupt
signal iIIR_ID0 : std_logic; -- IIR: Interrupt ID0
signal iIIR_ID1 : std_logic; -- IIR: Interrupt ID1
signal iIIR_ID2 : std_logic; -- IIR: Interrupt ID2
signal iIIR_FIFO64 : std_logic; -- IIR: 64 byte FIFO enabled
-- FCR register signals
signal iFCR_FIFOEnable : std_logic; -- FCR: FIFO enable
signal iFCR_RXFIFOReset : std_logic; -- FCR: Receiver FIFO reset
signal iFCR_TXFIFOReset : std_logic; -- FCR: Transmitter FIFO reset
signal iFCR_DMAMode : std_logic; -- FCR: DMA mode select
signal iFCR_FIFO64E : std_logic; -- FCR: 64 byte FIFO enable
signal iFCR_RXTrigger : std_logic_vector(1 downto 0); -- FCR: Receiver trigger
-- LCR register signals
signal iLCR_WLS : std_logic_vector(1 downto 0); -- LCR: Word length select
signal iLCR_STB : std_logic; -- LCR: Number of stop bits
signal iLCR_PEN : std_logic; -- LCR: Parity enable
signal iLCR_EPS : std_logic; -- LCR: Even parity select
signal iLCR_SP : std_logic; -- LCR: Sticky parity
signal iLCR_BC : std_logic; -- LCR: Break control
signal iLCR_DLAB : std_logic; -- LCR: Divisor latch access bit
-- MCR register signals
signal iMCR_DTR : std_logic; -- MCR: Data terminal ready
signal iMCR_RTS : std_logic; -- MCR: Request to send
signal iMCR_OUT1 : std_logic; -- MCR: OUT1
signal iMCR_OUT2 : std_logic; -- MCR: OUT2
signal iMCR_LOOP : std_logic; -- MCR: Loop
signal iMCR_AFE : std_logic; -- MCR: Auto flow control enable
-- LSR register signals
signal iLSR_DR : std_logic; -- LSR: Data ready
signal iLSR_OE : std_logic; -- LSR: Overrun error
signal iLSR_PE : std_logic; -- LSR: Parity error
signal iLSR_FE : std_logic; -- LSR: Framing error
signal iLSR_BI : std_logic; -- LSR: Break Interrupt
signal iLSR_THRE : std_logic; -- LSR: Transmitter holding register empty
signal iLSR_TEMT : std_logic; -- LSR: Transmitter empty
signal iLSR_FIFOERR : std_logic; -- LSR: Error in receiver FIFO
-- MSR register signals
signal iMSR_dCTS : std_logic; -- MSR: Delta CTS
signal iMSR_dDSR : std_logic; -- MSR: Delta DSR
signal iMSR_TERI : std_logic; -- MSR: Trailing edge ring indicator
signal iMSR_dDCD : std_logic; -- MSR: Delta DCD
signal iMSR_CTS : std_logic; -- MSR: CTS
signal iMSR_DSR : std_logic; -- MSR: DSR
signal iMSR_RI : std_logic; -- MSR: RI
signal iMSR_DCD : std_logic; -- MSR: DCD
-- UART MSR signals
signal iCTSNs : std_logic; -- Synchronized CTSN input
signal iDSRNs : std_logic; -- Synchronized DSRN input
signal iDCDNs : std_logic; -- Synchronized DCDN input
signal iRINs : std_logic; -- Synchronized RIN input
signal iCTSn : std_logic; -- Filtered CTSN input
signal iDSRn : std_logic; -- Filtered DSRN input
signal iDCDn : std_logic; -- Filtered DCDN input
signal iRIn : std_logic; -- Filtered RIN input
signal iCTSnRE : std_logic; -- CTSn rising edge
signal iCTSnFE : std_logic; -- CTSn falling edge
signal iDSRnRE : std_logic; -- DSRn rising edge
signal iDSRnFE : std_logic; -- DSRn falling edge
signal iDCDnRE : std_logic; -- DCDn rising edge
signal iDCDnFE : std_logic; -- DCDn falling edge
signal iRInRE : std_logic; -- RIn rising edge
signal iRInFE : std_logic; -- RIn falling edge
-- UART baudrate generation signals
signal iBaudgenDiv : std_logic_vector(15 downto 0); -- Baudrate divider
signal iBaudtick16x : std_logic; -- 16x Baudrate output from baudrate generator
signal iBaudtick2x : std_logic; -- 2x Baudrate for transmitter
signal iRCLK : std_logic; -- 16x Baudrate for receiver
-- UART FIFO signals
signal iTXFIFOClear : std_logic; -- Clear TX FIFO
signal iTXFIFOWrite : std_logic; -- Write to TX FIFO
signal iTXFIFORead : std_logic; -- Read from TX FIFO
signal iTXFIFOEmpty : std_logic; -- TX FIFO is empty
signal iTXFIFOFull : std_logic; -- TX FIFO is full
signal iTXFIFO16Full : std_logic; -- TX FIFO 16 byte mode is full
signal iTXFIFO64Full : std_logic; -- TX FIFO 64 byte mode is full
signal iTXFIFOUsage : std_logic_vector(5 downto 0); -- RX FIFO usage
signal iTXFIFOQ : std_logic_vector(7 downto 0); -- TX FIFO output
signal iRXFIFOClear : std_logic; -- Clear RX FIFO
signal iRXFIFOWrite : std_logic; -- Write to RX FIFO
signal iRXFIFORead : std_logic; -- Read from RX FIFO
signal iRXFIFOEmpty : std_logic; -- RX FIFO is empty
signal iRXFIFOFull : std_logic; -- RX FIFO is full
signal iRXFIFO16Full : std_logic; -- RX FIFO 16 byte mode is full
signal iRXFIFO64Full : std_logic; -- RX FIFO 64 byte mode is full
signal iRXFIFOD : std_logic_vector(10 downto 0); -- RX FIFO input
signal iRXFIFOQ : std_logic_vector(10 downto 0); -- RX FIFO output
signal iRXFIFOUsage : std_logic_vector(5 downto 0); -- RX FIFO usage
signal iRXFIFOTrigger : std_logic; -- FIFO trigger level reached
signal iRXFIFO16Trigger : std_logic; -- FIFO 16 byte mode trigger level reached
signal iRXFIFO64Trigger : std_logic; -- FIFO 64 byte mode trigger level reached
signal iRXFIFOPE : std_logic; -- Parity error from FIFO
signal iRXFIFOFE : std_logic; -- Frame error from FIFO
signal iRXFIFOBI : std_logic; -- Break interrupt from FIFO
-- UART transmitter signals
signal iSOUT : std_logic; -- Transmitter output
signal iTXStart : std_logic; -- Start transmitter
signal iTXClear : std_logic; -- Clear transmitter status
signal iTXFinished : std_logic; -- TX finished, character transmitted
signal iTXRunning : std_logic; -- TX in progress
-- UART receiver signals
signal iSINr : std_logic; -- Synchronized SIN input
signal iSIN : std_logic; -- Receiver input
signal iRXFinished : std_logic; -- RX finished, character received
signal iRXClear : std_logic; -- Clear receiver status
signal iRXData : std_logic_vector(7 downto 0); -- RX data
signal iRXPE : std_logic; -- RX parity error
signal iRXFE : std_logic; -- RX frame error
signal iRXBI : std_logic; -- RX break interrupt
-- UART control signals
signal iFERE : std_logic; -- Frame error detected
signal iPERE : std_logic; -- Parity error detected
signal iBIRE : std_logic; -- Break interrupt detected
signal iFECounter : integer range 0 to 64; -- FIFO error counter
signal iFEIncrement : std_logic; -- FIFO error counter increment
signal iFEDecrement : std_logic; -- FIFO error counter decrement
signal iRDAInterrupt : std_logic; -- Receiver data available interrupt (DA or FIFO trigger level)
signal iTimeoutCount : unsigned(5 downto 0); -- Character timeout counter (FIFO mode)
signal iCharTimeout : std_logic; -- Character timeout indication (FIFO mode)
signal iLSR_THRERE : std_logic; -- LSR THRE rising edge for interrupt generation
signal iTHRInterrupt : std_logic; -- Transmitter holding register empty interrupt
signal iTXEnable : std_logic; -- Transmitter enable signal
signal iRTS : std_logic; -- Internal RTS signal with/without automatic flow control
begin
-- Global device signals
iCSWR <= '1' when CS = '1' and WR = '1' else '0';
iCSRD <= '1' when CS = '1' and RD = '1' else '0';
UART_ED_WRITE: slib_edge_detect port map (CLK => CLK, RST => RST, D => iCSWR, FE => iWriteFE);
UART_ED_READ: slib_edge_detect port map (CLK => CLK, RST => RST, D => iCSRD, FE => iReadFE);
iWrite <= '1' when iWriteFE = '1' else '0';
iRead <= '1' when iReadFE = '1' else '0';
-- UART registers read/write signals
iRBRRead <= '1' when iRead = '1' and iA = "000" and iLCR_DLAB = '0' else '0';
iTHRWrite <= '1' when iWrite = '1' and iA = "000" and iLCR_DLAB = '0' else '0';
iDLLWrite <= '1' when iWrite = '1' and iA = "000" and iLCR_DLAB = '1' else '0';
iDLMWrite <= '1' when iWrite = '1' and iA = "001" and iLCR_DLAB = '1' else '0';
iIERWrite <= '1' when iWrite = '1' and iA = "001" and iLCR_DLAB = '0' else '0';
iIIRRead <= '1' when iRead = '1' and iA = "010" else '0';
iFCRWrite <= '1' when iWrite = '1' and iA = "010" else '0';
iLCRWrite <= '1' when iWrite = '1' and iA = "011" else '0';
iMCRWrite <= '1' when iWrite = '1' and iA = "100" else '0';
iLSRRead <= '1' when iRead = '1' and iA = "101" else '0';
iMSRRead <= '1' when iRead = '1' and iA = "110" else '0';
iSCRWrite <= '1' when iWrite = '1' and iA = "111" else '0';
-- Async. input synchronization
UART_IS_SIN: slib_input_sync port map (CLK, RST, SIN, iSINr);
UART_IS_CTS: slib_input_sync port map (CLK, RST, CTSN, iCTSNs);
UART_IS_DSR: slib_input_sync port map (CLK, RST, DSRN, iDSRNs);
UART_IS_DCD: slib_input_sync port map (CLK, RST, DCDN, iDCDNs);
UART_IS_RI: slib_input_sync port map (CLK, RST, RIN, iRINs);
-- Input filter for UART control signals
UART_IF_CTS: slib_input_filter generic map (SIZE => 2) port map (CLK, RST, iBaudtick2x, iCTSNs, iCTSn);
UART_IF_DSR: slib_input_filter generic map (SIZE => 2) port map (CLK, RST, iBaudtick2x, iDSRNs, iDSRn);
UART_IF_DCD: slib_input_filter generic map (SIZE => 2) port map (CLK, RST, iBaudtick2x, iDCDNs, iDCDn);
UART_IF_RI: slib_input_filter generic map (SIZE => 2) port map (CLK, RST, iBaudtick2x, iRINs, iRIn);
-- Sync. input synchronization
UART_SIS: process (CLK, RST)
begin
if (RST = '1') then
iA <= (others => '0');
iDIN <= (others => '0');
elsif (CLK'event and CLK = '1') then
iA <= A;
iDIN <= DIN;
end if;
end process;
-- Divisor latch register
UART_DLR: process (CLK, RST)
begin
if (RST = '1') then
iDLL <= (others => '0');
iDLM <= (others => '0');
elsif (CLK'event and CLK = '1') then
if (iDLLWrite = '1') then
iDLL <= iDIN;
end if;
if (iDLMWrite = '1') then
iDLM <= iDIN;
end if;
end if;
end process;
-- Interrupt enable register
UART_IER: process (CLK, RST)
begin
if (RST = '1') then
iIER(3 downto 0) <= (others => '0');
elsif (CLK'event and CLK = '1') then
if (iIERWrite = '1') then
iIER(3 downto 0) <= iDIN(3 downto 0);
end if;
end if;
end process;
iIER_ERBI <= iIER(0);
iIER_ETBEI <= iIER(1);
iIER_ELSI <= iIER(2);
iIER_EDSSI <= iIER(3);
iIER(7 downto 4) <= (others => '0');
-- Interrupt control and IIR
UART_IIC: uart_interrupt port map (CLK => CLK,
RST => RST,
IER => iIER(3 downto 0),
LSR => iLSR(4 downto 0),
THI => iTHRInterrupt,
RDA => iRDAInterrupt,
CTI => iCharTimeout,
AFE => iMCR_AFE,
MSR => iMSR(3 downto 0),
IIR => iIIR(3 downto 0),
INT => INT
);
-- THR empty interrupt
UART_IIC_THRE_ED: slib_edge_detect port map (CLK => CLK, RST => RST, D => iLSR_THRE, RE => iLSR_THRERE);
UART_IIC_THREI: process (CLK, RST)
begin
if (RST = '1') then
iTHRInterrupt <= '0';
elsif (CLK'event and CLK = '1') then
if (iLSR_THRERE = '1' or iFCR_TXFIFOReset = '1' or (iIERWrite = '1' and iDIN(1) = '1' and iLSR_THRE = '1')) then
iTHRInterrupt <= '1'; -- Set on THRE, TX FIFO reset (FIFO enable) or ETBEI enable
elsif ((iIIRRead = '1' and iIIR(3 downto 1) = "001") or iTHRWrite = '1') then
iTHRInterrupt <= '0'; -- Clear on IIR read (if source of interrupt) or THR write
end if;
end if;
end process;
iRDAInterrupt <= '1' when (iFCR_FIFOEnable = '0' and iLSR_DR = '1') or
(iFCR_FIFOEnable = '1' and iRXFIFOTrigger = '1') else '0';
iIIR_PI <= iIIR(0);
iIIR_ID0 <= iIIR(1);
iIIR_ID1 <= iIIR(2);
iIIR_ID2 <= iIIR(3);
iIIR_FIFO64 <= iIIR(5);
iIIR(4) <= '0';
iIIR(5) <= iFCR_FIFO64E when iFCR_FIFOEnable = '1' else '0';
iIIR(6) <= iFCR_FIFOEnable;
iIIR(7) <= iFCR_FIFOEnable;
-- Character timeout indication
UART_CTI: process (CLK, RST)
begin
if (RST = '1') then
iTimeoutCount <= (others => '0');
iCharTimeout <= '0';
elsif (CLK'event and CLK = '1') then
if (iRXFIFOEmpty = '1' or iRBRRead = '1' or iRXFIFOWrite = '1') then
iTimeoutCount <= (others => '0');
elsif (iRXFIFOEmpty = '0' and iBaudtick2x = '1' and iTimeoutCount(5) = '0') then
iTimeoutCount <= iTimeoutCount + 1;
end if;
-- Timeout indication
if (iFCR_FIFOEnable = '1') then
if (iRBRRead = '1') then
iCharTimeout <= '0';
elsif (iTimeoutCount(5) = '1') then
iCharTimeout <= '1';
end if;
else
iCharTimeout <= '0';
end if;
end if;
end process;
-- FIFO control register
UART_FCR: process (CLK, RST)
begin
if (RST = '1') then
iFCR_FIFOEnable <= '0';
iFCR_RXFIFOReset <= '0';
iFCR_TXFIFOReset <= '0';
iFCR_DMAMode <= '0';
iFCR_FIFO64E <= '0';
iFCR_RXTrigger <= (others => '0');
elsif (CLK'event and CLK = '1') then
-- FIFO reset pulse only
iFCR_RXFIFOReset <= '0';
iFCR_TXFIFOReset <= '0';
if (iFCRWrite = '1') then
iFCR_FIFOEnable <= iDIN(0);
iFCR_DMAMode <= iDIN(3);
iFCR_RXTrigger <= iDIN(7 downto 6);
if (iLCR_DLAB = '1') then
iFCR_FIFO64E <= iDIN(5);
end if;
-- RX FIFO reset control, reset on FIFO enable/disable
if (iDIN(1) = '1' or (iFCR_FIFOEnable = '0' and iDIN(0) = '1') or (iFCR_FIFOEnable = '1' and iDIN(0) = '0')) then
iFCR_RXFIFOReset <= '1';
end if;
-- TX FIFO reset control, reset on FIFO enable/disable
if (iDIN(2) = '1' or (iFCR_FIFOEnable = '0' and iDIN(0) = '1') or (iFCR_FIFOEnable = '1' and iDIN(0) = '0')) then
iFCR_TXFIFOReset <= '1';
end if;
end if;
end if;
end process;
iFCR(0) <= iFCR_FIFOEnable;
iFCR(1) <= iFCR_RXFIFOReset;
iFCR(2) <= iFCR_TXFIFOReset;
iFCR(3) <= iFCR_DMAMode;
iFCR(4) <= '0';
iFCR(5) <= iFCR_FIFO64E;
iFCR(7 downto 6) <= iFCR_RXTrigger;
-- Line control register
UART_LCR: process (CLK, RST)
begin
if (RST = '1') then
iLCR <= (others => '0');
elsif (CLK'event and CLK = '1') then
if (iLCRWrite = '1') then
iLCR <= iDIN;
end if;
end if;
end process;
iLCR_WLS <= iLCR(1 downto 0);
iLCR_STB <= iLCR(2);
iLCR_PEN <= iLCR(3);
iLCR_EPS <= iLCR(4);
iLCR_SP <= iLCR(5);
iLCR_BC <= iLCR(6);
iLCR_DLAB <= iLCR(7);
-- Modem control register
UART_MCR: process (CLK, RST)
begin
if (RST = '1') then
iMCR(5 downto 0) <= (others => '0');
elsif (CLK'event and CLK = '1') then
if (iMCRWrite = '1') then
iMCR(5 downto 0) <= iDIN(5 downto 0);
end if;
end if;
end process;
iMCR_DTR <= iMCR(0);
iMCR_RTS <= iMCR(1);
iMCR_OUT1 <= iMCR(2);
iMCR_OUT2 <= iMCR(3);
iMCR_LOOP <= iMCR(4);
iMCR_AFE <= iMCR(5);
iMCR(6) <= '0';
iMCR(7) <= '0';
-- Line status register
UART_LSR: process (CLK, RST)
begin
if (RST = '1') then
iLSR_OE <= '0';
iLSR_PE <= '0';
iLSR_FE <= '0';
iLSR_BI <= '0';
iFECounter <= 0;
elsif (CLK'event and CLK = '1') then
-- Overrun error
if ((iFCR_FIFOEnable = '0' and iLSR_DR = '1' and iRXFinished = '1') or
(iFCR_FIFOEnable = '1' and iRXFIFOFull = '1' and iRXFinished = '1')) then
iLSR_OE <= '1';
elsif (iLSRRead = '1') then
iLSR_OE <= '0';
end if;
-- Parity error
if (iPERE = '1') then
iLSR_PE <= '1';
elsif (iLSRRead = '1') then
iLSR_PE <= '0';
end if;
-- Frame error
if (iFERE = '1') then
iLSR_FE <= '1';
elsif (iLSRRead = '1') then
iLSR_FE <= '0';
end if;
-- Break interrupt
if (iBIRE = '1') then
iLSR_BI <= '1';
elsif (iLSRRead = '1') then
iLSR_BI <= '0';
end if;
-- FIFO error
-- Datasheet: Cleared by LSR read when no subsequent errors in FIFO
-- Observed: Cleared when no subsequent errors in FIFO
if (iFECounter /= 0) then
iLSR_FIFOERR <= '1';
--elsif (iLSRRead = '1' and iFECounter = 0 and not (iRXFIFOEmpty = '0' and iRXFIFOQ(10 downto 8) /= "000")) then
elsif (iRXFIFOEmpty = '1' or iRXFIFOQ(10 downto 8) = "000") then
iLSR_FIFOERR <= '0';
end if;
-- FIFO error counter
if (iRXFIFOClear = '1') then
iFECounter <= 0;
else
if (iFEIncrement = '1' and iFEDecrement = '0') then
iFECounter <= iFECounter + 1;
elsif (iFEIncrement = '0' and iFEDecrement = '1') then
iFECounter <= iFECounter - 1;
end if;
end if;
end if;
end process;
iRXFIFOPE <= '1' when iRXFIFOEmpty = '0' and iRXFIFOQ(8) = '1' else '0';
iRXFIFOFE <= '1' when iRXFIFOEmpty = '0' and iRXFIFOQ(9) = '1' else '0';
iRXFIFOBI <= '1' when iRXFIFOEmpty = '0' and iRXFIFOQ(10) = '1' else '0';
UART_PEDET: slib_edge_detect port map (CLK, RST, iRXFIFOPE, iPERE);
UART_FEDET: slib_edge_detect port map (CLK, RST, iRXFIFOFE, iFERE);
UART_BIDET: slib_edge_detect port map (CLK, RST, iRXFIFOBI, iBIRE);
iFEIncrement <= '1' when iRXFIFOWrite = '1' and iRXFIFOD(10 downto 8) /= "000" else '0';
iFEDecrement <= '1' when iFECounter /= 0 and iRXFIFOEmpty = '0' and (iPERE = '1' or iFERE = '1' or iBIRE = '1') else '0';
iLSR(0) <= iLSR_DR;
iLSR(1) <= iLSR_OE;
iLSR(2) <= iLSR_PE;
iLSR(3) <= iLSR_FE;
iLSR(4) <= iLSR_BI;
iLSR(5) <= iLSR_THRE;
iLSR(6) <= iLSR_TEMT;
iLSR(7) <= '1' when iFCR_FIFOEnable = '1' and iLSR_FIFOERR = '1' else '0';
iLSR_DR <= '1' when iRXFIFOEmpty = '0' or iRXFIFOWrite = '1' else '0';
iLSR_THRE <= '1' when iTXFIFOEmpty = '1' else '0';
iLSR_TEMT <= '1' when iTXRunning = '0' and iLSR_THRE = '1' else '0';
-- Modem status register
iMSR_CTS <= '1' when (iMCR_LOOP = '1' and iRTS = '1') or (iMCR_LOOP = '0' and iCTSn = '0') else '0';
iMSR_DSR <= '1' when (iMCR_LOOP = '1' and iMCR_DTR = '1') or (iMCR_LOOP = '0' and iDSRn = '0') else '0';
iMSR_RI <= '1' when (iMCR_LOOP = '1' and iMCR_OUT1 = '1') or (iMCR_LOOP = '0' and iRIn = '0') else '0';
iMSR_DCD <= '1' when (iMCR_LOOP = '1' and iMCR_OUT2 = '1') or (iMCR_LOOP = '0' and iDCDn = '0') else '0';
-- Edge detection for CTS, DSR, DCD and RI
UART_ED_CTS: slib_edge_detect port map (CLK => CLK, RST => RST, D => iMSR_CTS, RE => iCTSnRE, FE => iCTSnFE);
UART_ED_DSR: slib_edge_detect port map (CLK => CLK, RST => RST, D => iMSR_DSR, RE => iDSRnRE, FE => iDSRnFE);
UART_ED_RI: slib_edge_detect port map (CLK => CLK, RST => RST, D => iMSR_RI, RE => iRInRE, FE => iRInFE);
UART_ED_DCD: slib_edge_detect port map (CLK => CLK, RST => RST, D => iMSR_DCD, RE => iDCDnRE, FE => iDCDnFE);
UART_MSR: process (CLK, RST)
begin
if (RST = '1') then
iMSR_dCTS <= '0';
iMSR_dDSR <= '0';
iMSR_TERI <= '0';
iMSR_dDCD <= '0';
elsif (CLK'event and CLK = '1') then
-- Delta CTS
if (iCTSnRE = '1' or iCTSnFE = '1') then
iMSR_dCTS <= '1';
elsif (iMSRRead = '1') then
iMSR_dCTS <= '0';
end if;
-- Delta DSR
if (iDSRnRE = '1' or iDSRnFE = '1') then
iMSR_dDSR <= '1';
elsif (iMSRRead = '1') then
iMSR_dDSR <= '0';
end if;
-- Trailing edge RI
if (iRInFE = '1') then
iMSR_TERI <= '1';
elsif (iMSRRead = '1') then
iMSR_TERI <= '0';
end if;
-- Delta DCD
if (iDCDnRE = '1' or iDCDnFE = '1') then
iMSR_dDCD <= '1';
elsif (iMSRRead = '1') then
iMSR_dDCD <= '0';
end if;
end if;
end process;
iMSR(0) <= iMSR_dCTS;
iMSR(1) <= iMSR_dDSR;
iMSR(2) <= iMSR_TERI;
iMSR(3) <= iMSR_dDCD;
iMSR(4) <= iMSR_CTS;
iMSR(5) <= iMSR_DSR;
iMSR(6) <= iMSR_RI;
iMSR(7) <= iMSR_DCD;
-- Scratch register
UART_SCR: process (CLK, RST)
begin
if (RST = '1') then
iSCR <= (others => '0');
elsif (CLK'event and CLK = '1') then
if (iSCRWrite = '1') then
iSCR <= iDIN;
end if;
end if;
end process;
-- Baudrate generator
iBaudgenDiv <= iDLM & iDLL;
UART_BG16: uart_baudgen port map (CLK => CLK,
RST => RST,
CE => BAUDCE,
CLEAR => '0',
DIVIDER => iBaudgenDiv,
BAUDTICK => iBaudtick16x
);
UART_BG2: slib_clock_div generic map (RATIO => 8)
port map (CLK => CLK,
RST => RST,
CE => iBaudtick16x,
Q => iBaudtick2x
);
UART_RCLK: slib_edge_detect port map (CLK => CLK,
RST => RST,
D => RCLK,
RE => iRCLK
);
-- Transmitter FIFO
UART_TXFF: slib_fifo generic map (WIDTH => 8, SIZE_E => 6)
port map (CLK => CLK,
RST => RST,
CLEAR => iTXFIFOClear,
WRITE => iTXFIFOWrite,
READ => iTXFIFORead,
D => iDIN,
Q => iTXFIFOQ,
EMPTY => iTXFIFOEmpty,
FULL => iTXFIFO64Full,
USAGE => iTXFIFOUsage
);
-- Transmitter FIFO inputs
iTXFIFO16Full <= iTXFIFOUsage(4);
iTXFIFOFull <= iTXFIFO16Full when iFCR_FIFO64E = '0' else iTXFIFO64Full;
iTXFIFOWrite <= '1' when ((iFCR_FIFOEnable = '0' and iTXFIFOEmpty = '1') or (iFCR_FIFOEnable = '1' and iTXFIFOFull = '0')) and iTHRWrite = '1' else '0';
iTXFIFOClear <= '1' when iFCR_TXFIFOReset = '1' else '0';
-- Receiver FIFO
UART_RXFF: slib_fifo generic map (WIDTH => 11, SIZE_E => 6)
port map (CLK => CLK,
RST => RST,
CLEAR => iRXFIFOClear,
WRITE => iRXFIFOWrite,
READ => iRXFIFORead,
D => iRXFIFOD,
Q => iRXFIFOQ,
EMPTY => iRXFIFOEmpty,
FULL => iRXFIFO64Full,
USAGE => iRXFIFOUsage
);
-- Receiver FIFO inputs
iRXFIFORead <= '1' when iRBRRead = '1' else '0';
iRXFIFO16Full <= iRXFIFOUsage(4);
iRXFIFOFull <= iRXFIFO16Full when iFCR_FIFO64E = '0' else iRXFIFO64Full;
-- Receiver FIFO outputs
iRBR <= iRXFIFOQ(7 downto 0);
-- FIFO trigger level: 1, 4, 8, 14
iRXFIFO16Trigger <= '1' when (iFCR_RXTrigger = "00" and iRXFIFOEmpty = '0') or
(iFCR_RXTrigger = "01" and (iRXFIFOUsage(2) = '1' or iRXFIFOUsage(3) = '1')) or
(iFCR_RXTrigger = "10" and iRXFIFOUsage(3) = '1') or
(iFCR_RXTrigger = "11" and iRXFIFOUsage(3) = '1' and iRXFIFOUsage(2) = '1' and iRXFIFOUsage(1) = '1') or
iRXFIFO16Full = '1' else '0';
-- FIFO 64 trigger level: 1, 16, 32, 56
iRXFIFO64Trigger <= '1' when (iFCR_RXTrigger = "00" and iRXFIFOEmpty = '0') or
(iFCR_RXTrigger = "01" and (iRXFIFOUsage(4) = '1' or iRXFIFOUsage(5) = '1')) or
(iFCR_RXTrigger = "10" and iRXFIFOUsage(5) = '1') or
(iFCR_RXTrigger = "11" and iRXFIFOUsage(5) = '1' and iRXFIFOUsage(4) = '1' and iRXFIFOUsage(3) = '1') or
iRXFIFO64Full = '1' else '0';
iRXFIFOTrigger <= iRXFIFO16Trigger when iFCR_FIFO64E = '0' else iRXFIFO64Trigger;
-- Transmitter
UART_TX: uart_transmitter port map (CLK => CLK,
RST => RST,
TXCLK => iBaudtick2x,
TXSTART => iTXStart,
CLEAR => iTXClear,
WLS => iLCR_WLS,
STB => iLCR_STB,
PEN => iLCR_PEN,
EPS => iLCR_EPS,
SP => iLCR_SP,
BC => iLCR_BC,
DIN => iTSR,
TXFINISHED => iTXFinished,
SOUT => iSOUT
);
iTXClear <= '0';
-- Receiver
UART_RX: uart_receiver port map (CLK => CLK,
RST => RST,
RXCLK => iRCLK,
RXCLEAR => iRXClear,
WLS => iLCR_WLS,
STB => iLCR_STB,
PEN => iLCR_PEN,
EPS => iLCR_EPS,
SP => iLCR_SP,
SIN => iSIN,
PE => iRXPE,
FE => iRXFE,
BI => iRXBI,
DOUT => iRXData,
RXFINISHED => iRXFinished
);
iRXClear <= '0';
iSIN <= iSINr when iMCR_LOOP = '0' else iSOUT;
-- Transmitter enable signal
-- TODO: Use iCTSNs instead of iMSR_CTS? Input filter increases delay for Auto-CTS recognition.
iTXEnable <= '1' when iTXFIFOEmpty = '0' and (iMCR_AFE = '0' or (iMCR_AFE = '1' and iMSR_CTS = '1')) else '0';
-- Transmitter process
UART_TXPROC: process (CLK, RST)
type state_type is (IDLE, TXSTART, TXRUN, TXEND);
variable State : state_type;
begin
if (RST = '1') then
State := IDLE;
iTSR <= (others => '0');
iTXStart <= '0';
iTXFIFORead <= '0';
iTXRunning <= '0';
elsif (CLK'event and CLK = '1') then
-- Defaults
iTXStart <= '0';
iTXFIFORead <= '0';
iTXRunning <= '0';
case State is
when IDLE => if (iTXEnable = '1') then
iTXStart <= '1'; -- Start transmitter
State := TXSTART;
else
State := IDLE;
end if;
when TXSTART => iTSR <= iTXFIFOQ;
iTXStart <= '1'; -- Start transmitter
iTXFIFORead <= '1'; -- Increment TX FIFO read counter
State := TXRUN;
when TXRUN => if (iTXFinished = '1') then -- TX finished
State := TXEND;
else
State := TXRUN;
end if;
iTXRunning <= '1';
iTXStart <= '1';
when TXEND => State := IDLE;
when others => State := IDLE;
end case;
end if;
end process;
-- Receiver process
UART_RXPROC: process (CLK, RST)
type state_type is (IDLE, RXSAVE);
variable State : state_type;
begin
if (RST = '1') then
State := IDLE;
iRXFIFOWrite <= '0';
iRXFIFOClear <= '0';
iRXFIFOD <= (others => '0');
elsif (CLK'event and CLK = '1') then
-- Defaults
iRXFIFOWrite <= '0';
iRXFIFOClear <= iFCR_RXFIFOReset;
case State is
when IDLE => if (iRXFinished = '1') then -- Receive finished
iRXFIFOD <= iRXBI & iRXFE & iRXPE & iRXData;
if (iFCR_FIFOEnable = '0') then
iRXFIFOClear <= '1'; -- Non-FIFO mode
end if;
State := RXSAVE;
else
State := IDLE;
end if;
when RXSAVE => if (iFCR_FIFOEnable = '0') then
iRXFIFOWrite <= '1'; -- Non-FIFO mode: Overwrite
elsif (iRXFIFOFull = '0') then
iRXFIFOWrite <= '1'; -- FIFO mode
end if;
State := IDLE;
when others => State := IDLE;
end case;
end if;
end process;
-- Automatic flow control
UART_AFC: process (CLK, RST)
begin
if (RST = '1') then
iRTS <= '0';
elsif (CLK'event and CLK = '1') then
if (iMCR_RTS = '0' or (iMCR_AFE = '1' and iRXFIFOTrigger = '1')) then
-- Deassert when MCR_RTS is not set or AFC is enabled and the RX FIFO trigger level is reached
iRTS <= '0';
elsif (iMCR_RTS = '1' and (iMCR_AFE = '0' or (iMCR_AFE = '1' and iRXFIFOEmpty = '1'))) then
-- Assert when MCR_RTS is set and AFC is disabled or when AFC is enabled and the RX FIFO is empty
iRTS <= '1';
end if;
end if;
end process;
-- Output registers
UART_OUTREGS: process (CLK, RST)
begin
if (RST = '1') then
DDIS <= '1';
BAUDOUTN <= '1';
OUT1N <= '1';
OUT2N <= '1';
RTSN <= '1';
DTRN <= '1';
SOUT <= '1';
elsif (CLK'event and CLK = '1') then
-- Default values
DDIS <= '0';
BAUDOUTN <= '0';
OUT1N <= '0';
OUT2N <= '0';
RTSN <= '0';
DTRN <= '0';
SOUT <= '0';
-- DDIS
if (CS = '0' or RD = '0') then
DDIS <= '1';
end if;
-- BAUDOUTN
if (iBaudtick16x = '0') then
BAUDOUTN <= '1';
end if;
-- OUT1N
if (iMCR_LOOP = '1' or iMCR_OUT1 = '0') then
OUT1N <= '1';
end if;
-- OUT2N
if (iMCR_LOOP = '1' or iMCR_OUT2 = '0') then
OUT2N <= '1';
end if;
-- RTS
if (iMCR_LOOP = '1' or iRTS = '0') then
RTSN <= '1';
end if;
-- DTR
if (iMCR_LOOP = '1' or iMCR_DTR = '0') then
DTRN <= '1';
end if;
-- SOUT
if (iMCR_LOOP = '1' or iSOUT = '1') then
SOUT <= '1';
end if;
end if;
end process;
-- UART data output
UART_DOUT: process (A, iLCR_DLAB, iRBR, iDLL, iDLM, iIER, iIIR, iLCR, iMCR, iLSR, iMSR, iSCR)
begin
case A is
when "000" => if (iLCR_DLAB = '0') then
DOUT <= iRBR;
else
DOUT <= iDLL;
end if;
when "001" => if (iLCR_DLAB = '0') then
DOUT <= iIER;
else
DOUT <= iDLM;
end if;
when "010" => DOUT <= iIIR;
when "011" => DOUT <= iLCR;
when "100" => DOUT <= iMCR;
when "101" => DOUT <= iLSR;
when "110" => DOUT <= iMSR;
when "111" => DOUT <= iSCR;
when others => DOUT <= iRBR;
end case;
end process;
end rtl;
| lgpl-3.0 | 03b879c07c5fa900dec84f346943e271 | 0.426763 | 4.688124 | false | false | false | false |
airabinovich/finalArquitectura | TestDatapathPart1/PipeAndDebug/ipcore_dir/instructionROM/example_design/instructionROM_prod.vhd | 1 | 9,948 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: instructionROM_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan6
-- C_XDEVICEFAMILY : spartan6
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 3
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : instructionROM.mif
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 32
-- C_READ_WIDTH_A : 32
-- C_WRITE_DEPTH_A : 256
-- C_READ_DEPTH_A : 256
-- C_ADDRA_WIDTH : 8
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 32
-- C_READ_WIDTH_B : 32
-- C_WRITE_DEPTH_B : 256
-- C_READ_DEPTH_B : 256
-- C_ADDRB_WIDTH : 8
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY instructionROM_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END instructionROM_prod;
ARCHITECTURE xilinx OF instructionROM_prod IS
COMPONENT instructionROM_exdes IS
PORT (
--Port A
ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : instructionROM_exdes
PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
| lgpl-2.1 | 309400821398a485d43fe6e6b50b8216 | 0.497085 | 3.849845 | false | false | false | false |
airabinovich/finalArquitectura | TestDatapathPart1/DatapathPart1/ipcore_dir/blk_mem_gen_v7_3/simulation/blk_mem_gen_v7_3_synth.vhd | 1 | 6,875 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: blk_mem_gen_v7_3_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY blk_mem_gen_v7_3_synth IS
GENERIC (
C_ROM_SYNTH : INTEGER := 1
);
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE blk_mem_gen_v7_3_synth_ARCH OF blk_mem_gen_v7_3_synth IS
COMPONENT blk_mem_gen_v7_3_exdes
PORT (
--Inputs - Port A
ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL ADDRA: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
GENERIC MAP( C_ROM_SYNTH => C_ROM_SYNTH
)
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(ADDRA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ELSE
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: blk_mem_gen_v7_3_exdes PORT MAP (
--Port A
ADDRA => ADDRA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
| lgpl-2.1 | 19cd187e8ef1bab4dafc22f0cc72dbc1 | 0.580218 | 3.736413 | false | false | false | false |
INTI-CMNB/Lattuino_IP_Core | devices/ad_conv.vhdl | 1 | 9,121 | ------------------------------------------------------------------------------
---- ----
---- WISHBONE A/D Interface ----
---- ----
---- This file is part FPGA Libre project http://fpgalibre.sf.net/ ----
---- ----
---- Description: ----
---- Implements the WISHBONE interface for the A/D (MCP3008). ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Salvador E. Tropea, salvador en inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2017 Salvador E. Tropea <salvador en inti.gob.ar> ----
---- Copyright (c) 2017 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the GPL v2 or newer license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: AD_Conv(RTL) (Entity and architecture) ----
---- File name: ad_conv.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: lattuino ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- SPI.Devices ----
---- Target FPGA: iCE40HX4K-TQ144 ----
---- Language: VHDL ----
---- Wishbone: None ----
---- Synthesis tools: Lattice iCECube2 2016.02.27810 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Wishbone Datasheet ----
---- ----
---- 1 Revision level B.3 ----
---- 2 Type of interface SLAVE ----
---- 3 Defined signal names RST_I => wb_rst_i ----
---- CLK_I => wb_clk_i ----
---- ADR_I => wb_adr_i ----
---- DAT_I => wb_dat_i ----
---- DAT_O => wb_dat_o ----
---- WE_I => wb_we_i ----
---- ACK_O => wb_ack_o ----
---- STB_I => wb_stb_i ----
---- 4 ERR_I Unsupported ----
---- 5 RTY_I Unsupported ----
---- 6 TAGs None ----
---- 7 Port size 8-bit ----
---- 8 Port granularity 8-bit ----
---- 9 Maximum operand size 8-bit ----
---- 10 Data transfer ordering N/A ----
---- 11 Data transfer sequencing Undefined ----
---- 12 Constraints on the CLK_I signal None ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library SPI;
use SPI.Devices.all;
entity AD_Conv is
generic(
DIVIDER : positive:=12;
INTERNAL_CLK : std_logic:='1'; -- not boolean for Verilog compat
ENABLE : std_logic:='1'); -- not boolean for Verilog compat
port(
-- WISHBONE signals
wb_clk_i : in std_logic; -- Clock
wb_rst_i : in std_logic; -- Reset input
wb_adr_i : in std_logic_vector(0 downto 0); -- Adress bus
wb_dat_o : out std_logic_vector(7 downto 0); -- DataOut Bus
wb_dat_i : in std_logic_vector(7 downto 0); -- DataIn Bus
wb_we_i : in std_logic; -- Write Enable
wb_stb_i : in std_logic; -- Strobe
wb_ack_o : out std_logic; -- Acknowledge
-- SPI rate (2x)
-- Note: with 2 MHz spi_ena_i we get 1 MHz SPI clock => 55,6 ks/s
spi_ena_i: in std_logic; -- 2xSPI clock
-- A/D interface
ad_ncs_o : out std_logic; -- SPI /CS
ad_clk_o : out std_logic; -- SPI clock
ad_din_o : out std_logic; -- SPI A/D Din (MOSI)
ad_dout_i: in std_logic); -- SPI A/D Dout (MISO)
end entity AD_Conv;
architecture RTL of AD_Conv is
signal cnt_div_spi : integer range 0 to DIVIDER-1:=0;
signal spi_ena : std_logic;
signal start_r : std_logic;
signal busy_ad : std_logic;
signal busy : std_logic;
signal chn_r : std_logic_vector(2 downto 0);
signal cur_val : std_logic_vector(9 downto 0);
signal wb_dat : std_logic_vector(7 downto 0);
signal ad_ncs : std_logic; -- SPI /CS
signal ad_clk : std_logic; -- SPI clock
signal ad_din : std_logic; -- SPI A/D Din (MOSI)
begin
wb_dat <= cur_val(7 downto 0) when wb_adr_i(0)='0' else
busy&"00000"&cur_val(9 downto 8);
wb_dat_o <= wb_dat when ENABLE='1' else (others => '0');
wb_ack_o <= wb_stb_i;
-- The A/D reads start only when ena_i is 1, so we memorize it
-- until the A/D indicates a conversion with busy_ad
do_start:
process (wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
start_r <= '0';
else
if (wb_stb_i and wb_we_i)='1' then
start_r <= '1';
elsif busy_ad='1' then
start_r <= '0';
end if;
end if;
end if;
end process do_start;
-- The A/D is busy or we have a pending start
busy <= busy_ad or start_r;
do_chn_write:
process (wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if (wb_stb_i and wb_we_i)='1' then
chn_r <= wb_dat_i(2 downto 0);
end if;
end if;
end process do_chn_write;
----------------------
-- SPI clock enable --
----------------------
internal_divider:
if INTERNAL_CLK='1' generate
do_spi_div:
process (wb_clk_i)
begin
if rising_edge(wb_clk_i) then
cnt_div_spi <= cnt_div_spi+1;
if cnt_div_spi=DIVIDER-1 then
cnt_div_spi <= 0;
end if;
end if;
end process do_spi_div;
spi_ena <= '1' when cnt_div_spi=DIVIDER-1 else '0';
end generate internal_divider;
external_divider:
if INTERNAL_CLK/='1' generate
spi_ena <= spi_ena_i;
end generate external_divider;
-------------------
-- A/D interface --
-------------------
the_AD : MCP300x
port map(
-- System
clk_i => wb_clk_i, rst_i => '0',
-- Master interface
start_i => start_r, busy_o => busy_ad, chn_i => chn_r, single_i => '1',
ena_i => spi_ena, eoc_o => open, data_o => cur_val,
-- A/D interface
ad_ncs_o => ad_ncs, ad_clk_o => ad_clk, ad_din_o => ad_din,
ad_dout_i => ad_dout_i);
ad_ncs_o <= ad_ncs when ENABLE='1' else '0';
ad_clk_o <= ad_clk when ENABLE='1' else '0';
ad_din_o <= ad_din when ENABLE='1' else '0';
end architecture RTL; -- Entity: AD_Conv
| gpl-2.0 | af724311c98f58ae70dd4f26d9dd46f6 | 0.338121 | 4.68705 | false | false | false | false |
INTI-CMNB/Lattuino_IP_Core | FPGA/lattuino_1/lattuino_1.vhdl | 1 | 21,514 | ------------------------------------------------------------------------------
---- ----
---- AVR ATtX5 CPU for Lattuino ----
---- ----
---- This file is part FPGA Libre project http://fpgalibre.sf.net/ ----
---- ----
---- Description: ----
---- This module implements the CPU for Lattuino (iCE40HX4K Lattice FPGA ----
---- available in the Kéfir I board). ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008-2017 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008-2017 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the GPL v2 or newer license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: Lattuino_1(FPGA) (Entity and architecture) ----
---- File name: lattuino_1.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: work ----
---- Dependencies: IEEE.std_logic_1164 ----
---- avr.Micros ----
---- miniuart.UART ----
---- CapSense.Devices ----
---- work.WBDevInterconPkg ----
---- work.CPUConfig ----
---- lattice.components ----
---- Target FPGA: iCE40HX4K-TQ144 ----
---- Language: VHDL ----
---- Wishbone: None ----
---- Synthesis tools: Lattice iCECube2 2016.02.27810 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library avr;
use avr.Micros.all;
use avr.Types.all;
library miniuart;
use miniuart.UART.all;
library CapSense;
use CapSense.Devices.all;
library lattice;
use lattice.components.all;
library lattuino;
use lattuino.PrgMems.all;
library work;
use work.WBDevInterconPkg.all;
use work.CPUConfig.all;
entity Lattuino_1 is
port(
CLK : in std_logic; -- CPU clock
RESET_P2 : in std_logic; -- Reset
-- Buil-in LEDs
LED1 : out std_logic;
LED2 : out std_logic;
LED3 : out std_logic;
LED4 : out std_logic;
-- CapSense buttons
BTN1 : inout std_logic;
BTN2 : inout std_logic;
BTN3 : inout std_logic;
BTN4 : inout std_logic;
-- Arduino UNO I/O
ARDU00 : inout std_logic;
ARDU01 : inout std_logic;
ARDU02 : inout std_logic;
ARDU03 : inout std_logic;
ARDU04 : inout std_logic;
ARDU05 : inout std_logic;
ARDU06 : inout std_logic;
ARDU07 : inout std_logic;
ARDU08 : inout std_logic;
ARDU09 : inout std_logic;
ARDU10 : inout std_logic; -- SS
ARDU11 : inout std_logic; -- MOSI
ARDU12 : inout std_logic; -- MISO
ARDU13 : inout std_logic; -- SCK
-- A/D Interface
AD_CS : out std_logic;
AD_Din : out std_logic;
AD_Dout : in std_logic;
AD_Clk : out std_logic;
-- SPI memory
SS_B : out std_logic;
SDO : out std_logic;
SDI : in std_logic;
SCK : out std_logic;
-- ISP SPI
--ISP_RESET : in std_logic;
ISP_SCK : out std_logic;
ISP_MOSI : out std_logic;
ISP_MISO : in std_logic;
-- UART
Milk_RXD : out std_logic; -- to UART Tx
Milk_TXD : in std_logic; -- to UART Rx
Milk_DTR : in std_logic); -- UART DTR
end entity Lattuino_1;
architecture FPGA of Lattuino_1 is
constant BRDIVISOR : natural:=natural(real(F_CLK)/real(BAUD_RATE)/4.0+0.5);
constant CNT_PRESC : natural:=F_CLK/1e6; -- Counter prescaler (1 µs)
constant DEBUG_SPI : boolean:=false;
constant DEBUG_INT : boolean:=false;
signal pc : unsigned(15 downto 0); -- PROM address
signal pcsv : std_logic_vector(ROM_ADDR_W-1 downto 0); -- PROM address
signal inst : std_logic_vector(15 downto 0); -- PROM data
signal inst_w : std_logic_vector(15 downto 0); -- PROM data
signal we : std_logic;
signal rst : std_logic;
signal rst1 : std_logic;
signal rst2 : std_logic:='0';
signal portb_in : std_logic_vector(6 downto 0);
signal portb_out : std_logic_vector(6 downto 0);
signal portb_oe : std_logic_vector(6 downto 0);
signal portd_in : std_logic_vector(7 downto 0);
signal portd_out : std_logic_vector(7 downto 0);
signal portd_oe : std_logic_vector(7 downto 0);
signal btns : std_logic_vector(3 downto 0); -- Capsense buttons
signal discharge : std_logic;
signal rst_btn : std_logic;
signal pin_irq : std_logic_vector(1 downto 0); -- Pin interrupts INT0/1
signal dev_irq : std_logic_vector(2 downto 0); -- Device interrupts
signal dev_ack : std_logic_vector(2 downto 0); -- Device ACK
-- WISHBONE signals:
-- cpu
signal cpu_dati : std_logic_vector(7 downto 0);
signal cpu_acki : std_logic;
signal cpu_dato : std_logic_vector(7 downto 0);
signal cpu_weo : std_logic;
signal cpu_adro : std_logic_vector(7 downto 0);
signal cpu_cyco : std_logic;
signal cpu_stbo : std_logic;
-- rs2
signal rs2_dato : std_logic_vector(7 downto 0);
signal rs2_acko : std_logic;
signal rs2_dati : std_logic_vector(7 downto 0);
signal rs2_wei : std_logic;
signal rs2_adri : std_logic_vector(0 downto 0);
signal rs2_stbi : std_logic;
-- ad
signal ad_dato : std_logic_vector(7 downto 0);
signal ad_acko : std_logic;
signal ad_dati : std_logic_vector(7 downto 0);
signal ad_wei : std_logic;
signal ad_adri : std_logic_vector(0 downto 0);
signal ad_stbi : std_logic;
-- tmr
signal tmr_dato : std_logic_vector(7 downto 0);
signal tmr_acko : std_logic;
signal tmr_dati : std_logic_vector(7 downto 0);
signal tmr_wei : std_logic;
signal tmr_adri : std_logic_vector(2 downto 0);
signal tmr_stbi : std_logic;
-- t16
signal t16_dato : std_logic_vector(7 downto 0);
signal t16_acko : std_logic;
signal t16_dati : std_logic_vector(7 downto 0);
signal t16_wei : std_logic;
signal t16_adri : std_logic_vector(0 downto 0);
signal t16_stbi : std_logic;
signal pwm : std_logic_vector(5 downto 0);
signal pwm_ena : std_logic_vector(5 downto 0);
signal t16_irq : std_logic;
signal t16_ack : std_logic;
signal inttx : std_logic;
signal intrx : std_logic;
signal dtr_r : std_logic;
signal dtr_reset : std_logic;
-- SPI
signal spi_sck : std_logic;
signal mosi : std_logic;
signal miso : std_logic;
signal spi_ena : std_logic; -- The CPU enabled the SPI pins
-- PLL
signal clk_spi : std_logic; -- SPI core clock
signal clk_sys : std_logic; -- CPU clock
signal pll_lock : std_logic;
begin
-----------------------------------------------------------
-- RESET logic --
-- Power-On Reset + External pin + CapSense 4 + UART DTR --
-----------------------------------------------------------
rst1 <= not(RESET_P2);
rst <= rst1 or not(rst2) or rst_btn or dtr_reset;
do_reset:
process (clk_sys)
begin
if rising_edge(clk_sys) then
if rst2='0' and pll_lock='1' then
rst2 <= '1';
end if;
end if;
end process do_reset;
-- The DTR reset is triggered by a falling edge at DTR
do_sample_dtr:
process (clk_sys)
begin
if rising_edge(clk_sys) then
dtr_r <= Milk_DTR;
end if;
end process do_sample_dtr;
dtr_reset <= '1' when dtr_r='1' and Milk_DTR='0' else '0';
rst_btn <= btns(0) when ENABLE_B1_RESET else '0';
-- Built-in LEDs
LED1 <= portb_out(6); -- pin IO14
--LED2 <= '0'; -- pwm(0);
LED2 <= pwm(0);
LED3 <= '0'; -- btns(2);
LED4 <= rst_btn;
-- Arduino IOx pins:
ARDU00 <= portd_out(0) when portd_oe(0)='1' else 'Z';
ARDU01 <= portd_out(1) when portd_oe(1)='1' else 'Z';
ARDU02 <= portd_out(2) when portd_oe(2)='1' else 'Z';
ARDU03 <= 'Z' when portd_oe(3)='0' else
portd_out(3) when pwm_ena(0)='0' or not(ENA_PWM0) else pwm(0);
ARDU04 <= portd_out(4) when portd_oe(4)='1' else 'Z';
ARDU05 <= 'Z' when portd_oe(5)='0' else
portd_out(5) when pwm_ena(1)='0' or not(ENA_PWM1) else pwm(1);
ARDU06 <= 'Z' when portd_oe(6)='0' else
portd_out(6) when pwm_ena(2)='0' or not(ENA_PWM2) else pwm(2);
ARDU07 <= portd_out(7) when portd_oe(7)='1' else 'Z';
ARDU08 <= portb_out(0) when portb_oe(0)='1' else 'Z';
ARDU09 <= 'Z' when portb_oe(1)='0' else
portb_out(1) when pwm_ena(3)='0' or not(ENA_PWM3) else pwm(3);
ARDU10 <= 'Z' when portb_oe(2)='0' else
portb_out(2) when pwm_ena(4)='0' or not(ENA_PWM4) else pwm(4);
ARDU11 <= 'Z' when portb_oe(3)='0' else
portb_out(3) when (pwm_ena(5)='0' or not(ENA_PWM5)) and spi_ena='0' else
mosi when spi_ena='1' else
pwm(5);
ARDU12 <= 'Z' when portb_oe(4)='0' or spi_ena='1' else portb_out(4);
ARDU13 <= 'Z' when portb_oe(5)='0' else
portb_out(5) when spi_ena='0' else
spi_sck;
portd_in(0) <= ARDU00;
portd_in(1) <= ARDU01;
portd_in(2) <= ARDU02;
portd_in(3) <= ARDU03;
portd_in(4) <= ARDU04;
portd_in(5) <= ARDU05;
portd_in(6) <= ARDU06;
portd_in(7) <= ARDU07;
portb_in(0) <= ARDU08;
portb_in(1) <= ARDU09;
portb_in(2) <= ARDU10;
portb_in(3) <= ARDU11;
portb_in(4) <= ARDU12;
portb_in(5) <= ARDU13;
miso <= ARDU12;
-- This is not 100% Arduino, here we fix SPI regardless spi_ena
--ISP_SCK <= spi_sck;
--ARDU12 <= ISP_MISO;
--ISP_MOSI <= mosi;
do_int_pins:
if not(DEBUG_INT) generate
-- INT0/1 pins (PD2 and PD3)
pin_irq(0) <= ARDU02 when ENA_INT0 else '0';
pin_irq(1) <= ARDU03 when ENA_INT1 else '0';
end generate do_int_pins;
do_int_btns:
if DEBUG_INT generate
-- Debug connection to CapSense
pin_irq(0) <= btns(1);
pin_irq(1) <= btns(2);
end generate do_int_btns;
-- Device interrupts
dev_irq(0) <= intrx; -- UART Rx
dev_irq(1) <= inttx; -- UART Tx
dev_irq(2) <= t16_irq; -- 16 bits Timer
t16_ack <= dev_ack(2);
do_debug_spi:
if DEBUG_SPI generate
SS_B <= portb_out(2);
SCK <= spi_sck;
miso <= SDI;
SDO <= mosi;
end generate do_debug_spi;
do_arduino_spi:
if not(DEBUG_SPI) generate
SS_B <= '1'; -- Disable the SPI memory
SCK <= '0';
SDO <= '0';
end generate do_arduino_spi;
micro : ATtX5
generic map(
ENA_WB => '1', ENA_SPM => '1', ENA_PORTB => '1',
ENA_PORTC => '0', ENA_PORTD => '1', PORTB_SIZE => 7,
PORTC_SIZE => 6, PORTD_SIZE => 8, RESET_JUMP => RESET_JUMP,
ENA_IRQ_CTRL => '1', RAM_ADDR_W => RAM_ADDR_W, ENA_SPI => ENABLE_SPI)
port map(
rst_i => rst, clk_i => clk_sys, clk2x_i => clk_spi,
pc_o => pc, inst_i => inst, ena_i => '1', portc_i => open,
portb_i => portb_in, pgm_we_o => we, inst_o => inst_w,
portd_i => portd_in, pin_irq_i => pin_irq, dev_irq_i => dev_irq,
dev_ack_o => dev_ack, portb_o => portb_out, portd_o => portd_out,
portb_oe_o => portb_oe, portd_oe_o => portd_oe,
-- SPI
-- Connected to the SPI memory just for test
spi_ena_o => spi_ena, sclk_o => spi_sck, miso_i => miso, mosi_o => mosi,
-- WISHBONE
wb_adr_o => cpu_adro, wb_dat_o => cpu_dato, wb_dat_i => cpu_dati,
wb_stb_o => cpu_stbo, wb_we_o => cpu_weo, wb_ack_i => cpu_acki,
-- Debug
dbg_stop_i => '0', dbg_rf_fake_i => '0', dbg_rr_data_i => (others => '0'),
dbg_rd_data_i => (others => '0'));
cpu_cyco <= '0';
pcsv <= std_logic_vector(pc(ROM_ADDR_W-1 downto 0));
-- Program memory (1/2/4Kx16) (2/4/8 kiB)
pm_2k:
if ROM_ADDR_W=10 generate
PM_Inst2 : lattuino_1_blPM_2
generic map(
WORD_SIZE => 16, ADDR_W => ROM_ADDR_W)
port map(
clk_i => clk_sys, addr_i => pcsv, data_o => inst,
data_i => inst_w, we_i => we);
end generate pm_2k;
pm_4k:
if ROM_ADDR_W=11 generate
PM_Inst4 : lattuino_1_blPM_4
generic map(
WORD_SIZE => 16, ADDR_W => ROM_ADDR_W)
port map(
clk_i => clk_sys, addr_i => pcsv, data_o => inst,
data_i => inst_w, we_i => we);
end generate pm_4k;
pm_8k:
if ROM_ADDR_W=12 generate
PM_Inst8 : lattuino_1_blPM_8
generic map(
WORD_SIZE => 16, ADDR_W => ROM_ADDR_W)
port map(
clk_i => clk_sys, addr_i => pcsv, data_o => inst,
data_i => inst_w, we_i => we);
end generate pm_8k;
-----------------------
-- WISHBONE Intercon --
-----------------------
intercon: WBDevIntercon
port map(
-- wishbone master port(s)
-- cpu
cpu_dat_o => cpu_dati,
cpu_ack_o => cpu_acki,
cpu_dat_i => cpu_dato,
cpu_we_i => cpu_weo,
cpu_adr_i => cpu_adro,
cpu_cyc_i => cpu_cyco,
cpu_stb_i => cpu_stbo,
-- wishbone slave port(s)
-- rs2
rs2_dat_i => rs2_dato,
rs2_ack_i => rs2_acko,
rs2_dat_o => rs2_dati,
rs2_we_o => rs2_wei,
rs2_adr_o => rs2_adri,
rs2_stb_o => rs2_stbi,
-- ad
ad_dat_i => ad_dato,
ad_ack_i => ad_acko,
ad_dat_o => ad_dati,
ad_we_o => ad_wei,
ad_adr_o => ad_adri,
ad_stb_o => ad_stbi,
-- tmr
tmr_dat_i => tmr_dato,
tmr_ack_i => tmr_acko,
tmr_dat_o => tmr_dati,
tmr_we_o => tmr_wei,
tmr_adr_o => tmr_adri,
tmr_stb_o => tmr_stbi,
-- t16
t16_dat_i => t16_dato,
t16_ack_i => t16_acko,
t16_dat_o => t16_dati,
t16_we_o => t16_wei,
t16_adr_o => t16_adri,
t16_stb_o => t16_stbi,
-- clock and reset
wb_clk_i => clk_sys,
wb_rst_i => rst);
-------------------
-- WISHBONE UART --
-------------------
the_uart : UART_C
generic map(
BRDIVISOR => BRDIVISOR,
WIP_ENABLE => '1',
AUX_ENABLE => '0')
port map(
-- Wishbone signals
wb_clk_i => clk_sys, wb_rst_i => rst, wb_adr_i => rs2_adri,
wb_dat_i => rs2_dati, wb_dat_o => rs2_dato, wb_we_i => rs2_wei,
wb_stb_i => rs2_stbi, wb_ack_o => rs2_acko,
-- Process signals
inttx_o => inttx, intrx_o => intrx, br_clk_i => '1',
txd_pad_o => Milk_RXD, rxd_pad_i => Milk_TXD);
----------------------------
-- WISHBONE time counters --
----------------------------
the_counter : TMCounter
generic map(
CNT_PRESC => CNT_PRESC, ENA_TMR => ENA_TIME_CNT)
port map(
pwm_o => pwm, pwm_e_o => pwm_ena,
-- Wishbone signals
wb_clk_i => clk_sys, wb_rst_i => rst, wb_adr_i => tmr_adri,
wb_dat_o => tmr_dato, wb_stb_i => tmr_stbi, wb_ack_o => tmr_acko,
wb_dat_i => tmr_dati, wb_we_i => tmr_wei);
------------------------------
-- WISHBONE 16 bits counter --
------------------------------
the_tm16bits : TM16bits
generic map(CNT_PRESC => CNT_PRESC, ENA_TMR => ENA_TMR16)
port map(
irq_req_o => t16_irq, irq_ack_i => t16_ack,
-- Wishbone signals
wb_clk_i => clk_sys, wb_rst_i => rst, wb_adr_i => t16_adri,
wb_dat_o => t16_dato, wb_stb_i => t16_stbi, wb_ack_o => t16_acko,
wb_dat_i => t16_dati, wb_we_i => t16_wei);
------------------
-- WISHBONE A/D --
------------------
the_ad : AD_Conv
generic map(ENABLE => ENABLE_AD)
port map(
ad_ncs_o => AD_CS, ad_clk_o => AD_Clk, ad_din_o => AD_Din,
ad_dout_i => AD_Dout, spi_ena_i => '0',
-- Wishbone signals
wb_clk_i => clk_sys, wb_rst_i => rst, wb_adr_i => ad_adri,
wb_dat_o => ad_dato, wb_stb_i => ad_stbi, wb_ack_o => ad_acko,
wb_dat_i => ad_dati, wb_we_i => ad_wei);
----------------------
-- Botones CapSense --
----------------------
CS : CapSense_Sys
generic map (N => 4, FREQUENCY => CNT_PRESC, DIRECT => '0')
port map(
clk_i => clk_sys,
rst_i => '0',
capsense_i(0) => BTN1,
capsense_i(1) => BTN2,
capsense_i(2) => BTN3,
capsense_i(3) => BTN4,
capsense_o => discharge,
buttons_o => btns, debug_o => open);
BTN1 <= '0' when discharge='1' else 'Z';
BTN2 <= '0' when discharge='1' else 'Z';
BTN3 <= '0' when discharge='1' else 'Z';
BTN4 <= '0' when discharge='1' else 'Z';
do_2xSPI:
if ENA_2xSCK generate
-- *************************************************************************
-- PLL: 48 MHz clock from 24 MHz clock
-- *************************************************************************
PLL1 : SB_PLL40_2F_PAD
generic map(
--- Feedback (all defaults)
FEEDBACK_PATH => "SIMPLE",
DELAY_ADJUSTMENT_MODE_FEEDBACK => "FIXED",
-- DELAY_ADJUSTMENT_MODE_RELATIVE => "FIXED",
SHIFTREG_DIV_MODE => "00", -- 0 --> Divide by 4, 1 --> Divide by 7, 3 --> Divide by 5
FDA_FEEDBACK => "0000",
-- FDA_RELATIVE => "0000",
PLLOUT_SELECT_PORTA => "GENCLK",
PLLOUT_SELECT_PORTB => "GENCLK_HALF",
-- Freq. Multiplier (DIVF+1)/((2**DIVQ)*(DIVR+1))=32/16=2
DIVF => "0011111", -- 31
DIVR => "0000",
DIVQ => "100", -- 4
FILTER_RANGE => "010", -- Not documented!
--- Output clock gates (for low power modes)
ENABLE_ICEGATE_PORTA => '0',
ENABLE_ICEGATE_PORTB => '0'
--- Test Mode Parameter
-- TEST_MODE => '0',
-- EXTERNAL_DIVIDE_FACTOR => 1 -- Not Used by model, Added for PLL config GUI
)
port map(
PACKAGEPIN => CLK, -- Clock pin from GBx
PLLOUTCOREA => open, -- Clock A (to logic)
PLLOUTGLOBALA => clk_spi, -- Clock A (to global lines)
PLLOUTCOREB => open, -- Clock B (to logic)
PLLOUTGLOBALB => clk_sys, -- Clock B (to global lines)
EXTFEEDBACK => open, -- External feedback (not used here)
DYNAMICDELAY => open, -- Dynamic delay (not used here)
LOCK => pll_lock, -- PLL is locked
BYPASS => '0', -- Bypass enable
RESETB => '1', -- /Reset
LATCHINPUTVALUE => open, -- Clock gate enable
-- Test Pins (not documented)
SDO => open, SDI => open, SCLK => open);
end generate do_2xSPI;
do_1xSPI:
if not(ENA_2xSCK) generate
clk_spi <= CLK;
clk_sys <= CLK;
pll_lock <= '1';
end generate do_1xSPI;
end architecture FPGA; -- Entity: Lattuino_1
| gpl-2.0 | 1516ceaf5de5a966e59ccbaf38cee97d | 0.45482 | 3.395518 | false | false | false | false |
dpolad/dlx | DLX_vhd/a.i.a.b.b-T2LEVEL2.vhd | 2 | 690 | library ieee;
use ieee.std_logic_1164.all;
use work.myTypes.all;
--00 mask00
--01 mask08
--10 mask16
entity shift_secondLevel is
port(sel : in std_logic_vector(1 downto 0);
mask00 : in std_logic_vector(38 downto 0);
mask08 : in std_logic_vector(38 downto 0);
mask16 : in std_logic_vector(38 downto 0);
Y : out std_logic_vector(38 downto 0));
end shift_secondLevel;
architecture behav of shift_secondLevel is
begin
process(sel, mask00, mask08, mask16)
begin
case sel is
when "00" =>
Y <= mask00;
when "01" =>
Y <= mask08;
when "10" =>
Y <= mask16;
when others => Y <= x"000000000" & "000";
end case;
end process;
end behav;
| bsd-2-clause | dd95a9ab2d87141d4a7e6e6d0591c655 | 0.637681 | 2.804878 | false | false | false | false |
dpolad/dlx | DLX_vhd/a.c-BTB.vhd | 2 | 3,841 | -- *** btb.vhd *** --
-- this block is a simple branch predictor.
-- at each fetch operation, this acts as a LUT to guess the next PC
-- Future improvements: integrate 2bit predictor directly here instead of using a component
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.myTypes.all;
-- BTB number of lines should be correctly evaulated in order to achieve good performance without spending too much area
entity btb is
generic (
N_LINES : integer := PRED_SIZE;
SIZE : integer := 32
);
port (
clock : in std_logic;
reset : in std_logic;
stall_i : in std_logic;
TAG_i : in std_logic_vector(N_LINES - 1 downto 0); -- TAG is taken from the PC ( remove 2 lowest bits)
target_PC_i : in std_logic_vector(SIZE - 1 downto 0); -- correct value from dec stage
was_taken_i : in std_logic; -- correct value from dec stage
predicted_next_PC_o : out std_logic_vector(SIZE - 1 downto 0); -- output to PC
taken_o : out std_logic; -- control to bypass PC_MUX and use prediction
mispredict_o : out std_logic -- 1 when last branch was not correctly predicted
);
end btb;
architecture bhe of btb is
component predictor_2
port (
clock : in std_logic;
reset : in std_logic;
enable : in std_logic;
taken_i : in std_logic;
prediction_o : out std_logic
);
end component;
-- actual BTB memory
type PC_array is array (integer range 0 to 2**N_LINES - 1) of std_logic_vector(SIZE - 1 downto 0);
signal predict_PC : PC_array;
signal taken : std_logic_vector(2**N_LINES-1 downto 0);
signal write_enable : std_logic_vector(2**N_LINES-1 downto 0);
-- help signal
signal last_TAG : std_logic_vector(N_LINES - 1 downto 0);
signal last_TAG_next : std_logic_vector(N_LINES - 1 downto 0);
signal last_PC : std_logic_vector(SIZE -1 downto 0);
signal current_PC_prediction : std_logic_vector(SIZE -1 downto 0);
signal last_taken_next : std_logic;
signal last_taken : std_logic;
signal last_mispredict : std_logic;
signal current_taken : std_logic;
signal current_mispredict : std_logic;
begin
pred: for i in 0 to 2**N_LINES-1 generate
pred_x: predictor_2 port map(clock,reset,write_enable(i),was_taken_i,taken(i));
end generate pred;
process(reset,clock)
begin
if reset = '1' then
-- reset behavior
last_TAG <= (others => '0');
last_mispredict <= '0';
last_PC <= (others => '0');
write_enable <= (others => '0');
for i in 0 to 2**N_LINES-1 loop
predict_PC(i) <= (others => '0');
end loop;
elsif clock = '1' and clock'event then
-- update registers ( when stalled keep the old value )
if stall_i <= '0' then
last_taken <= last_taken_next;
last_TAG <= last_TAG_next;
last_PC <= current_PC_prediction;
-- update even if the prediction is correct
predict_PC(to_integer(unsigned(last_TAG))) <= target_PC_i;
last_mispredict <= current_mispredict;
write_enable <= (others => '0');
write_enable(to_integer(unsigned(last_tag))) <= '1';
else -- is this else really necessary??
last_taken <= last_taken;
last_TAG <= last_TAG;
last_PC <= last_PC;
end if;
end if;
end process;
current_mispredict <= ((or_reduce(target_PC_i xor last_PC) and last_taken) or ( not(last_taken) and was_taken_i)) and (not last_mispredict) ;
mispredict_o <= current_mispredict;
--accesses to memory
current_taken <= taken(to_integer(unsigned(TAG_i)));
current_PC_prediction <= predict_PC(to_integer(unsigned(TAG_i)));
predicted_next_PC_o <= current_PC_prediction;
-- need to have a correct behavior at reset
last_TAG_next <= TAG_i when reset = '0' else
(others => '0');
--taken ( and last_taken_next ) when curret op is valid (found in memory) and prediction is taken
taken_o <= current_taken when reset = '0' else
'0';
last_taken_next <= current_taken;
end bhe;
| bsd-2-clause | 34bf62b1e987246b5aface8e77bf8342 | 0.675345 | 2.86428 | false | false | false | false |
TimingKeepers/gen-ugr-cores | modules/bridges/bridge_pkg.vhd | 1 | 4,621 | -------------------------------------------------------------------------------
-- Title : Bridge package
-- Project : Misc
-------------------------------------------------------------------------------
-- File : bridge_pkg.vhd
-- Author : Miguel Jimenez Lopez
-- Company : UGR
-- Created : 2016-04-13
-- Last update: 2016-04-13
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
--
-- This package contains the bridge IP core developed.
--
-------------------------------------------------------------------------------
-- TODO:
-------------------------------------------------------------------------------
--
-- Copyright (c) 2016 UGR
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.wishbone_pkg.all;
package bridge_pkg is
component wbs2axism
generic (
g_address_width : integer := 32;
g_data_width : integer := 64
);
port (
-- Clock & Reset (neg)
clk_i : in std_logic;
rst_n_i : in std_logic;
-- WB Slave (memory mapped) interface
s_wb_cyc_i : in std_logic;
s_wb_stb_i : in std_logic;
s_wb_adr_i : in std_logic_vector(g_address_width-1 downto 0);
s_wb_dat_i : in std_logic_vector(g_data_width-1 downto 0);
s_wb_sel_i : in std_logic_vector((g_data_width/8)-1 downto 0);
s_wb_we_i : in std_logic;
s_wb_ack_o : out std_logic;
s_wb_stall_o : out std_logic;
-- AXI Master (streaming) interface
m_axis_tdata_o : out std_logic_vector(g_data_width-1 downto 0);
m_axis_tkeep_o : out std_logic_vector((g_data_width/8)-1 downto 0);
m_axis_tlast_o : out std_logic;
m_axis_tready_i : in std_logic;
m_axis_tvalid_o : out std_logic;
m_axis_tstrb_o : out std_logic_vector((g_data_width/8)-1 downto 0)
);
end component;
component wb_axi_bridge is
generic (
G_DATA_WIDTH : integer := 32;
G_ADDR_WIDTH : integer := 32;
G_BURST_WIDTH : integer := 8
);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
--Wishbone ports
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
wb_dat_i : in std_logic_vector(G_DATA_WIDTH-1 downto 0);
wb_adr_i : in std_logic_vector(G_ADDR_WIDTH-1 downto 0);
wb_we_i : in std_logic;
wb_sel_i : in std_logic_vector(G_DATA_WIDTH/8-1 downto 0);
adc_acq_count : in std_logic_vector(31 downto 0);
acq_end_o : out std_logic;
-- Ports of Axi Master Bus Interface M00_AXI
m00_axi_aclk : in std_logic; -- It's not used.
m00_axi_aresetn : in std_logic;
m00_axi_awaddr : out std_logic_vector(G_ADDR_WIDTH-1 downto 0);
m00_axi_awlen : out std_logic_vector(7 downto 0);
m00_axi_awsize : out std_logic_vector(2 downto 0);
m00_axi_awburst : out std_logic_vector(1 downto 0);
m00_axi_awprot : out std_logic_vector(2 downto 0);
m00_axi_awvalid : out std_logic;
m00_axi_awready : in std_logic;
m00_axi_wdata : out std_logic_vector(G_DATA_WIDTH-1 downto 0);
m00_axi_wstrb : out std_logic_vector(G_DATA_WIDTH/8-1 downto 0);
m00_axi_wlast : out std_logic;
m00_axi_wvalid : out std_logic;
m00_axi_wready : in std_logic;
m00_axi_bresp : in std_logic_vector(1 downto 0);
m00_axi_bvalid : in std_logic;
m00_axi_bready : out std_logic);
end component;
end package;
package body bridge_pkg is
end package body;
| gpl-2.0 | 6fbf482a80e18c5775137dbd9aa355c0 | 0.534084 | 3.375457 | false | false | false | false |
achan1989/SlowWorm | src/lib/SlowWorm.vhd | 1 | 3,064 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 28.08.2016 16:05:25
-- Design Name:
-- Module Name: SlowWorm
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
package SlowWorm is
subtype data_t is std_ulogic_vector (15 downto 0);
subtype addr_t is unsigned (15 downto 0);
constant UNK_DATA : data_t := (others => 'U');
constant UNK_ADDR : addr_t := (others => 'U');
subtype alu_op_v_t is std_ulogic_vector (4 downto 0);
type alu_op_e_t is (
-- Logic
OP_NOT_A, OP_NOT_B, OP_A_AND_B, OP_A_NAND_B,
OP_A_OR_B, OP_A_NOR_B, OP_A_XOR_B, OP_A_XNOR_B,
OP_NA_AND_B, OP_NB_AND_A, OP_NA_OR_B, OP_NB_OR_A,
-- Arithmetic
OP_A_PLUS_B, OP_B_MINUS_A, OP_INC_A, OP_INC_B,
OP_DEC_A, OP_DEC_B, OP_LSL_A, OP_LSL_B,
OP_LSR_A, OP_LSR_B, OP_ASR_A, OP_ASR_B,
-- Error
OP_INVALID);
function op_vect_to_enum (signal v : alu_op_v_t) return alu_op_e_t;
function ADDR_TO_DATA(addr : addr_t) return data_t;
function DATA_TO_ADDR(data : data_t) return addr_t;
end package;
package body SlowWorm is
function ADDR_TO_DATA(addr : addr_t) return data_t is begin
return std_ulogic_vector(addr);
end function;
function DATA_TO_ADDR(data : data_t) return addr_t is begin
return unsigned(data);
end function;
function op_vect_to_enum (signal v : alu_op_v_t) return alu_op_e_t is
begin
case v is
-- Logic
when "00000" => return OP_NOT_A;
when "00001" => return OP_NOT_B;
when "00010" => return OP_A_AND_B;
when "00011" => return OP_A_NAND_B;
when "00100" => return OP_A_OR_B;
when "00101" => return OP_A_NOR_B;
when "00110" => return OP_A_XOR_B;
when "00111" => return OP_A_XNOR_B;
when "01000" => return OP_NA_AND_B;
when "01001" => return OP_NB_AND_A;
when "01010" => return OP_NA_OR_B;
when "01011" => return OP_NB_OR_A;
-- Arithmetic
when "10000" => return OP_A_PLUS_B;
when "10001" => return OP_B_MINUS_A;
when "10010" => return OP_INC_A;
when "10011" => return OP_INC_B;
when "10100" => return OP_DEC_A;
when "10101" => return OP_DEC_B;
when "10110" => return OP_LSL_A;
when "10111" => return OP_LSL_B;
when "11000" => return OP_LSR_A;
when "11001" => return OP_LSR_B;
when "11010" => return OP_ASR_A;
when "11011" => return OP_ASR_B;
-- Error
when others => return OP_INVALID;
end case;
end function;
end package body;
| mit | 0b527901d901ba09bc05eb89bfcfa6f2 | 0.515339 | 3.178423 | false | false | false | false |
rodrigofegui/UnB | 2017.1/Organização e Arquitetura de Computadores/Trabalhos/Projeto Final/Codificação/seven_seg_decoder.vhd | 2 | 1,153 | --Módulo para converter um dado para mostrar no display 7 segmentos da placa DE2
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity seven_seg_decoder is
port(
data: in STD_LOGIC_VECTOR(3 downto 0);
segments: out STD_LOGIC_VECTOR(6 downto 0)
);
end;
architecture seven_seg_decoder_arch of seven_seg_decoder is
begin
process(data)
begin
case data is
when X"0" => segments <= not "0111111";
when X"1" => segments <= not "0000110";
when X"2" => segments <= not "1011011";
when X"3" => segments <= not "1001111";
when X"4" => segments <= not "1100110";
when X"5" => segments <= not "1101101";
when X"6" => segments <= not "1111101";
when X"7" => segments <= not "0000111";
when X"8" => segments <= not "1111111";
when X"9" => segments <= not "1101111";
when X"A" => segments <= not "1110111";
when X"B" => segments <= not "1111100";
when X"C" => segments <= not "0111001";
when X"D" => segments <= not "1011110";
when X"E" => segments <= not "1111001";
when X"F" => segments <= not "1110001";
when others => segments <= not "0000000";
end case;
end process;
end;
| gpl-3.0 | 09efdfc3574f9889bb719bcfb231695c | 0.609375 | 3.138965 | false | false | false | false |
dpolad/dlx | DLX_vhd/a.i.a.d-COMPARATOR.vhd | 2 | 1,318 | -- *** comparator.vhd *** --
-- structural comparator as described in prof. Graziano documents
-- extended in order to handle both signed and unsigned comparisons
-- sum is computed outside of the comparator
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
entity comparator is
generic (M : integer := 64);
port (
C : in std_logic; -- carry out
V : in std_logic; -- overflow
SUM : in std_logic_vector(M-1 downto 0);
sel : in std_logic_vector(2 downto 0); -- selection
sign : in std_logic; -- 0 unsigned / signed 1
S : out std_logic
);
end comparator;
architecture BEHAVIORAL of comparator is
signal Z : std_logic;
signal N : std_logic;
signal G : std_logic;
signal GE : std_logic;
signal L : std_logic;
signal LE : std_logic;
signal E : std_logic;
signal NE : std_logic;
begin
Z <= nor_reduce(SUM);
N <= SUM(M-1);
G <= C and (not Z) when sign = '0' else
(N xnor V) and (not Z);
GE <= C when sign = '0' else
N xnor V;
L <= not(C) when sign = '0' else
not(N xnor V);
LE <= not(C) or Z when sign = '0' else
not(N xnor V) or Z;
E <= Z;
NE <= not(Z);
S <= G when sel="000" else
GE when sel="001" else
L when sel="010" else
LE when sel="011" else
E when sel="100" else
NE when sel="101" else
'X';
end BEHAVIORAL;
| bsd-2-clause | 6329a789df0eb19a17f1b1f1f92c4b9a | 0.625948 | 2.589391 | false | false | false | false |
hugofragata/euromillions-keygen-vhdl | counter50.vhd | 1 | 717 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter50 is
port(C, CLR, hold : in std_logic;
Q : out std_logic_vector(5 downto 0));
end counter50;
architecture archi of counter50 is
signal tmp: std_logic_vector(5 downto 0);
begin
process (C, CLR, hold)
begin
if (hold = '0') then
if (CLR='1') then
tmp <= "000000";
elsif (C'event and C='1') then
if (tmp = "110011") then
tmp <= "000001";
else
tmp <= tmp + 1;
end if;
end if;
end if;
end process;
Q <= tmp;
end archi; | mit | 4a391af6ae507c23ebe39dd0a81c6792 | 0.479777 | 3.753927 | false | false | false | false |
dpolad/dlx | DLX_vhd/b-IRAM.vhd | 1 | 1,498 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use std.textio.all;
use ieee.std_logic_textio.all;
-- Instruction memory for DLX
-- Memory filled by a process which reads from a file
-- file name is "test.asm.mem"
entity IRAM is
generic (
RAM_DEPTH : integer := 2048;
I_SIZE : integer := 32);
port (
Rst : in std_logic;
Addr : in std_logic_vector(I_SIZE - 1 downto 0);
Dout : out std_logic_vector(I_SIZE - 1 downto 0)
);
end IRAM;
architecture IRam_Bhe of IRAM is
type RAMtype is array (0 to RAM_DEPTH - 1) of integer;-- std_logic_vector(I_SIZE - 1 downto 0);
signal IRAM_mem : RAMtype;
begin -- IRam_Bhe
Dout <= conv_std_logic_vector(IRAM_mem(conv_integer(unsigned(Addr))/4),I_SIZE);
-- purpose: This process is in charge of filling the Instruction RAM with the firmware
-- type : combinational
-- inputs : Rst
-- outputs: IRAM_mem
FILL_MEM_P: process (Rst)
file mem_fp: text;
variable file_line : line;
variable index : integer := 0;
variable tmp_data_u : std_logic_vector(I_SIZE-1 downto 0);
begin -- process FILL_MEM_P
if (Rst = '1') then
file_open(mem_fp,"DLX_vhd/test_bench/test.asm.mem",READ_MODE);
while (not endfile(mem_fp)) loop
readline(mem_fp,file_line);
hread(file_line,tmp_data_u);
IRAM_mem(index) <= conv_integer(unsigned(tmp_data_u));
index := index + 1;
end loop;
end if;
end process FILL_MEM_P;
end IRam_Bhe;
| bsd-2-clause | ee984ab79e1eecf43157550098fefdb5 | 0.641522 | 3.173729 | false | true | false | false |
jobisoft/jTDC | modules/VFB6/I2C/i2c_interface.vhdl | 1 | 6,509 | -------------------------------------------------------------------------
---- ----
---- Engineer: A. Winnebeck ----
---- Company: ELB-Elektroniklaboratorien Bonn UG ----
---- (haftungsbeschränkt)
---- ----
-------------------------------------------------------------------------
---- ----
---- Copyright (C) 2015 ELB ----
---- ----
---- This program is free software; you can redistribute it and/or ----
---- modify it under the terms of the GNU General Public License as ----
---- published by the Free Software Foundation; either version 3 of ----
---- the License, or (at your option) any later version. ----
---- ----
---- This program is distributed in the hope that it will be useful, ----
---- but WITHOUT ANY WARRANTY; without even the implied warranty of ----
---- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ----
---- GNU General Public License for more details. ----
---- ----
---- You should have received a copy of the GNU General Public ----
---- License along with this program; if not, see ----
---- <http://www.gnu.org/licenses>. ----
---- ----
-------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity i2c_interface is
Port ( databus : inout STD_LOGIC_VECTOR (31 downto 0):=(others=>'Z');
addressbus : in STD_LOGIC_VECTOR (15 downto 0);
writesignal : in STD_LOGIC;
readsignal : in STD_LOGIC;
SCL_General, SDA_General : inout STD_LOGIC :='Z';
CLK : in STD_LOGIC);
end i2c_interface;
architecture Behavioral of i2c_interface is
-----Signals for i2c-------
--inputs
Signal ClockDivide : STD_LOGIC_VECTOR (15 downto 0) :=X"0031"; --register
Signal I2C_Start, I2C_Stop, I2C_Read, I2C_Write, I2C_Send_Ack : STD_LOGIC :='0'; --- kombinatorisches signal
Signal I2C_data_to_send : STD_LOGIC_VECTOR (7 downto 0):=X"00"; -- register
Signal I2C_Reset : STD_LOGIC :='0';
--outputs
signal I2C_Command_Ack : STD_LOGIC:='0'; -- for internal usage
signal I2C_busy,I2C_arb_lost : STD_LOGIC:='0'; -- direkt weitergeben
signal I2C_ack_received, Reg_I2C_ack_received : STD_LOGIC:='0'; --Register geladen bei I2C_Command_Ack
signal I2C_received_data, Reg_I2C_received_data : STD_LOGIC_VECTOR(7 downto 0):=X"00";
-- pins
signal scl_i, scl_o, scl_oen, sda_i, sda_o, sda_oen : STD_LOGIC;
Signal cmd_ack_count : unsigned (31 downto 0):=to_unsigned(0,32);
--- signals for I2C end------------
---- Component declaration ----
COMPONENT i2c_master_byte_ctrl
PORT(
clk : IN std_logic;
rst : IN std_logic;
nReset : IN std_logic;
ena : IN std_logic;
clk_cnt : IN std_logic_vector(15 downto 0);
start : IN std_logic;
stop : IN std_logic;
read : IN std_logic;
write : IN std_logic;
ack_in : IN std_logic;
din : IN std_logic_vector(7 downto 0);
scl_i : IN std_logic;
sda_i : IN std_logic;
cmd_ack : OUT std_logic;
ack_out : OUT std_logic;
i2c_busy : OUT std_logic;
i2c_al : OUT std_logic;
dout : OUT std_logic_vector(7 downto 0);
scl_o : OUT std_logic;
scl_oen : OUT std_logic;
sda_o : OUT std_logic;
sda_oen : OUT std_logic
);
END COMPONENT;
--------------------------------------
begin
process (CLK) is
begin
if rising_edge(CLK) then
if (writesignal = '1') then
case addressbus is
when X"0030" =>
I2C_data_to_send <= databus(7 downto 0);
I2C_Send_Ack <= databus(8);
I2C_Write <= databus(9);
I2C_Read <= databus(10);
I2C_Stop <= databus(11);
I2C_Start <= databus(12);
when X"0040" => I2C_Reset <= '1';
when X"003C" => ClockDivide <= databus(15 downto 0);
when others => NULL;
end case;
else
if (readsignal = '1') then
case addressbus is
when X"0034" =>
databus(10) <= I2C_busy;
databus(9) <= I2C_arb_lost;
databus(8) <= Reg_I2C_ack_received;
databus(7 downto 0) <= Reg_I2C_received_data;
databus(31 downto 11) <= (others=>'0');
when X"0038" =>
databus <= STD_LOGIC_VECTOR(cmd_ack_count);
when X"003C" =>
databus(15 downto 0) <= ClockDivide;
databus(31 downto 16) <=(others=>'0');
when others => databus <= (others=>'Z');
end case;
else
databus <= (others=>'Z');
end if;
I2C_Start<='0';
I2C_Stop<='0';
I2C_Read<='0';
I2C_Write<='0';
I2C_Reset<='0';
end if;
end if;
end process;
--- connection to i2c bus on pcb -----
scl_General <= scl_o when (scl_oen = '0') else 'Z';
sda_General <= sda_o when (sda_oen = '0') else 'Z';
scl_i <= scl_General;
sda_i <= sda_General;
Process (CLK) is
begin
if rising_edge(CLK) then
if (I2C_Reset='1') then
Reg_I2C_received_data <= X"00";
Reg_I2C_ack_received <= '0';
elsif (I2C_Command_Ack='1') then
cmd_ack_count <= cmd_ack_count+1;
Reg_I2C_received_data <= I2C_received_data;
Reg_I2C_ack_received <= I2C_ack_received;
end if;
end if;
end process;
Inst_i2c_master_byte_ctrl: i2c_master_byte_ctrl
PORT MAP(
clk => CLK,
rst => I2C_Reset,
nReset => '1',-- not I2C_Reset,
ena => '1',
clk_cnt => ClockDivide,-- 5x SCL = clk/(clk_cnt+1)
-- start, stop, read, write: synchrone signale, mssen fr befehl einen takt high sein
start => I2C_Start,
stop => I2C_Stop,
read => I2C_Read,
write => I2C_Write,
ack_in => I2C_Send_Ack,
din => I2C_data_to_send,
--outputs:
cmd_ack => I2C_Command_Ack,
ack_out => I2C_ack_received,
i2c_busy => I2C_busy ,
i2c_al => I2C_arb_lost, -- arb lost
dout => I2C_received_data,
-- connection to pin
scl_i => scl_i,
scl_o => scl_o,
scl_oen => scl_oen,
sda_i => sda_i,
sda_o => sda_o,
sda_oen => sda_oen
);
--------------- i2c interface end ----
end Behavioral;
| gpl-3.0 | 60ec708d64ea014ad0660d55d1cdd8f5 | 0.516134 | 3.229777 | false | false | false | false |
MAV-RT-testbed/MAV-testbed | Syma_Flight_Final/Syma_Flight_Final.srcs/sources_1/ipshared/xilinx.com/axi_quad_spi_v3_2/c64e9f22/hdl/src/vhdl/qspi_look_up_logic.vhd | 1 | 72,284 | --
---- qspi_look_up_logic - entity/architecture pair
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
---- Filename: qspi_look_up_logic.vhd
---- Version: v3.0
---- Description: Serial Peripheral Interface (SPI) Module for interfacing
---- with a 32-bit AXI4 Bus.
----
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library lib_pkg_v1_0;
use lib_pkg_v1_0.all;
use lib_pkg_v1_0.lib_pkg.log2;
use lib_pkg_v1_0.lib_pkg.RESET_ACTIVE;
library axi_quad_spi_v3_2;
use axi_quad_spi_v3_2.comp_defs.all;
library dist_mem_gen_v8_0;
use dist_mem_gen_v8_0.all;
-- Library declaration XilinxCoreLib
-- library XilinxCoreLib;
library unisim;
use unisim.vcomponents.FDRE;
-------------------------------------------------------------------------------
entity qspi_look_up_logic is
generic(
C_FAMILY : string;
C_SPI_MODE : integer;
C_SPI_MEMORY : integer;
C_NUM_TRANSFER_BITS : integer
);
port(
EXT_SPI_CLK : in std_logic;
Rst_to_spi : in std_logic;
TXFIFO_RST : in std_logic;
--------------------
DTR_FIFO_Data_Exists: in std_logic;
Data_From_TxFIFO : in std_logic_vector
(0 to (C_NUM_TRANSFER_BITS-1));
pr_state_idle : in std_logic;
--------------------
Data_Dir : out std_logic;
Data_Mode_1 : out std_logic;
Data_Mode_0 : out std_logic;
Data_Phase : out std_logic;
--------------------
Quad_Phase : out std_logic;
--------------------
Addr_Mode_1 : out std_logic;
Addr_Mode_0 : out std_logic;
Addr_Bit : out std_logic;
Addr_Phase : out std_logic;
--------------------
CMD_Mode_1 : out std_logic;
CMD_Mode_0 : out std_logic;
CMD_Error : out std_logic;
---------------------
CMD_decoded : out std_logic
);
end entity qspi_look_up_logic;
-----------------------------
architecture imp of qspi_look_up_logic is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-- constant declaration
constant C_LUT_DWIDTH : integer := 8;
constant C_LUT_DEPTH : integer := 256;
-- function declaration
-- type declaration
-- signal declaration
--Dummy_Output_Signals-----
signal Local_rst : std_logic;
signal Dummy_3 : std_logic;
signal Dummy_2 : std_logic;
signal Dummy_1 : std_logic;
signal Dummy_0 : std_logic;
signal CMD_decoded_int : std_logic;
-----
begin
-----
Local_rst <= TXFIFO_RST or Rst_to_spi;
-- LUT for C_SPI_MODE = 1 start --
-------------------------------------------------------------------------------
-- QSPI_LOOK_UP_MODE_1_MEMORY_0: Dual mode. Mixed memories are supported.
-------------------------------
QSPI_LOOK_UP_MODE_1_MEMORY_0 : if (C_SPI_MODE = 1 and C_SPI_MEMORY = 0) generate
----------------------------
-- constant declaration
constant C_LOOK_UP_TABLE_WIDTH : integer := 11;
-- signal declaration
signal Look_up_op : std_logic_vector(C_LOOK_UP_TABLE_WIDTH-1 downto 0);
signal CMD_decoded_int_d1 : std_logic;
signal DTR_FIFO_Data_Exists_d1 : std_logic;
signal DTR_FIFO_Data_Exists_d2 : std_logic;
signal DTR_FIFO_Data_Exists_d3 : std_logic;
--signal DTR_FIFO_Data_Exists_d4 : std_logic;
---Dummy OUtput signals---------------
signal spo_1 : std_logic_vector(C_LOOK_UP_TABLE_WIDTH-1 downto 0);
signal dpo_1 : std_logic_vector(C_LOOK_UP_TABLE_WIDTH-1 downto 0);
signal qdpo_1 : std_logic_vector(C_LOOK_UP_TABLE_WIDTH-1 downto 0);
signal Store_DTR_FIFO_First_Data : std_logic;
signal Look_up_address : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
-----
begin
----- _________
-- __| -- DTR_FIFO_Data_Exists
-- ______
-- _____| -- DTR_FIFO_Data_Exists_d1
-- __
-- __| |______ -- Store_DTR_FIFO_First_Data
TRFIFO_DATA_EXIST_D1_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if (EXT_SPI_CLK'event and EXT_SPI_CLK='1') then
if (Rst_to_spi = RESET_ACTIVE) then
DTR_FIFO_Data_Exists_d1 <= '0';
DTR_FIFO_Data_Exists_d2 <= '0';
DTR_FIFO_Data_Exists_d3 <= '0';
--DTR_FIFO_Data_Exists_d4 <= '0';
CMD_decoded_int_d1 <= '0';
CMD_decoded_int <= '0';
else
DTR_FIFO_Data_Exists_d1 <= DTR_FIFO_Data_Exists and pr_state_idle;
CMD_decoded_int_d1 <= DTR_FIFO_Data_Exists_d1 and
not DTR_FIFO_Data_Exists_d2;
CMD_decoded_int <= CMD_decoded_int_d1;
--DTR_FIFO_Data_Exists_d2 <= DTR_FIFO_Data_Exists_d1;
--DTR_FIFO_Data_Exists_d3 <= DTR_FIFO_Data_Exists_d2;
--DTR_FIFO_Data_Exists_d4 <= DTR_FIFO_Data_Exists_d3;
--CMD_decoded_int <= DTR_FIFO_Data_Exists_d2 and
-- not(DTR_FIFO_Data_Exists_d3);
end if;
end if;
end process TRFIFO_DATA_EXIST_D1_PROCESS;
-----------------------------------------
CMD_decoded <= CMD_decoded_int;
Store_DTR_FIFO_First_Data <= DTR_FIFO_Data_Exists and
not(DTR_FIFO_Data_Exists_d1) and
Pr_state_idle;
-----------------------------------------
TXFIFO_ADDR_BITS_GENERATE: for i in 0 to (C_NUM_TRANSFER_BITS-1) generate
-----
begin
-----
TXFIFO_FIRST_ENTRY_REG_I: component FDRE
port map
(
Q => Look_up_address(i) ,--: out
C => EXT_SPI_CLK ,--: in
CE => Store_DTR_FIFO_First_Data ,--: in
R => Local_rst ,--: in
D => Data_From_TxFIFO(i) --: in
);
end generate TXFIFO_ADDR_BITS_GENERATE;
---------------------------------------
--C_SPI_MODE_1_MIXED_ROM_I: dist_mem_gen_v6_4
C_SPI_MODE_1_MIXED_ROM_I: entity dist_mem_gen_v8_0.dist_mem_gen_v8_0
-------------------
generic map(
C_HAS_CLK => 1,
C_READ_MIF => 1,
C_HAS_QSPO => 1,
C_ADDR_WIDTH => C_LUT_DWIDTH,
C_WIDTH => C_LOOK_UP_TABLE_WIDTH,
C_FAMILY => C_FAMILY,
C_SYNC_ENABLE => 1,
C_DEPTH => C_LUT_DEPTH,
C_HAS_QSPO_SRST => 1,
C_MEM_INIT_FILE => "mode_1_memory_0_mixed.mif",
C_DEFAULT_DATA => "0",
------------------------
C_HAS_QDPO_CLK => 0,
C_HAS_QDPO_CE => 0,
C_PARSER_TYPE => 1,
C_HAS_D => 0,
C_HAS_SPO => 0,
C_REG_A_D_INPUTS => 0,
C_HAS_WE => 0,
C_PIPELINE_STAGES => 0,
C_HAS_QDPO_RST => 0,
C_REG_DPRA_INPUT => 0,
C_QUALIFY_WE => 0,
C_HAS_QDPO_SRST => 0,
C_HAS_DPRA => 0,
C_QCE_JOINED => 0,
C_MEM_TYPE => 0,
C_HAS_I_CE => 0,
C_HAS_DPO => 0,
-- C_HAS_SPRA => 0, -- removed from dist mem gen
C_HAS_QSPO_CE => 0,
C_HAS_QSPO_RST => 0,
C_HAS_QDPO => 0
-------------------------
)
port map(
a => Look_up_address , -- a, -- in std_logic_vector(7 downto 0)
clk => EXT_SPI_CLK , -- clk, -- in
qspo_srst => Rst_to_spi , -- qspo_srst, -- in
qspo => Look_up_op , -- qspo -- out std_logic_vector(9 downto 0)
d => "00000000000",
dpra => "00000000",
we => '0',
i_ce => '1',
qspo_ce => '1',
qdpo_ce => '1',
qdpo_clk => '0',
qspo_rst => '0',
qdpo_rst => '0',
qdpo_srst => '0',
spo => spo_1,
dpo => dpo_1,
qdpo => qdpo_1
);
-- look up table arrangement is as below
-- 10 9 8 7 6 5 4 3 2 1 0
-- Data_Dir Data Mode_1 Data Mode_0 Data_Phase Addr Mode_1 Addr_Mode_0 Addr_Bit Addr_Ph CMD_Mode_1 CMD Mode_0 CMD_ERROR
-------------
Data_Dir <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 1); -- 10 14
Data_Mode_1 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 2); -- 9 13
Data_Mode_0 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 3); -- 8 12
Data_Phase <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 4); -- 7 11
-------------
Quad_Phase <= '0';
Addr_Mode_1 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 5); -- 6
Addr_Mode_0 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 6); -- 5
Addr_Bit <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 7); -- 4
Addr_Phase <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 8); -- 3
-------------
CMD_Mode_1 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 9); -- 2
CMD_Mode_0 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 10); -- 1
CMD_Error <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - C_LOOK_UP_TABLE_WIDTH)
and CMD_decoded_int; -- 0
-------------
-----------------------------------------
end generate QSPI_LOOK_UP_MODE_1_MEMORY_0;
-----------------------------------------
-------------------------------------------------------------------------------
-- QSPI_LOOK_UP_MODE_1_MEMORY_1: This is Dual mode. Dedicated Winbond memories are supported.
--------------------------------
QSPI_LOOK_UP_MODE_1_MEMORY_1 : if (C_SPI_MODE = 1 and C_SPI_MEMORY = 1) generate
----------------------------
-- constant declaration
constant C_LOOK_UP_TABLE_WIDTH : integer := 11;
-- signal declaration
signal spo_2 : std_logic_vector(C_LOOK_UP_TABLE_WIDTH-1 downto 0);
signal dpo_2 : std_logic_vector(C_LOOK_UP_TABLE_WIDTH-1 downto 0);
signal qdpo_2 : std_logic_vector(C_LOOK_UP_TABLE_WIDTH-1 downto 0);
signal Look_up_op : std_logic_vector(C_LOOK_UP_TABLE_WIDTH-1 downto 0);
signal DTR_FIFO_Data_Exists_d1 : std_logic;
signal DTR_FIFO_Data_Exists_d2 : std_logic;
signal DTR_FIFO_Data_Exists_d3 : std_logic;
signal CMD_decoded_int_d1 : std_logic;
--signal DTR_FIFO_Data_Exists_d4 : std_logic;
signal Store_DTR_FIFO_First_Data : std_logic;
signal Look_up_address : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
-----
begin
----- _________
-- __| -- DTR_FIFO_Data_Exists
-- ______
-- _____| -- DTR_FIFO_Data_Exists_d1
-- __
-- __| |______ -- Store_DTR_FIFO_First_Data
TRFIFO_DATA_EXIST_D1_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if (EXT_SPI_CLK'event and EXT_SPI_CLK='1') then
if (Rst_to_spi = RESET_ACTIVE) then
DTR_FIFO_Data_Exists_d1 <= '0';
DTR_FIFO_Data_Exists_d2 <= '0';
DTR_FIFO_Data_Exists_d3 <= '0';
--DTR_FIFO_Data_Exists_d4 <= '0';
CMD_decoded_int_d1 <= '0';
CMD_decoded_int <= '0';
else
DTR_FIFO_Data_Exists_d1 <= DTR_FIFO_Data_Exists and pr_state_idle;
CMD_decoded_int_d1 <= DTR_FIFO_Data_Exists_d1 and not DTR_FIFO_Data_Exists_d2;
CMD_decoded_int <= CMD_decoded_int_d1;
-- DTR_FIFO_Data_Exists_d2 <= DTR_FIFO_Data_Exists_d1;
-- DTR_FIFO_Data_Exists_d3 <= DTR_FIFO_Data_Exists_d2;
--DTR_FIFO_Data_Exists_d4 <= DTR_FIFO_Data_Exists_d3;
-- CMD_decoded_int <= DTR_FIFO_Data_Exists_d2 and
-- not(DTR_FIFO_Data_Exists_d3);
end if;
end if;
end process TRFIFO_DATA_EXIST_D1_PROCESS;
-----------------------------------------
CMD_decoded <= CMD_decoded_int;
Store_DTR_FIFO_First_Data <= DTR_FIFO_Data_Exists and
not(DTR_FIFO_Data_Exists_d1) and
Pr_state_idle;
-----------------------------------------
TXFIFO_ADDR_BITS_GENERATE: for i in 0 to (C_NUM_TRANSFER_BITS-1) generate
-----
begin
-----
TXFIFO_FIRST_ENTRY_REG_I: component FDRE
port map
(
Q => Look_up_address(i) ,--: out
C => EXT_SPI_CLK ,--: in
CE => Store_DTR_FIFO_First_Data ,--: in
R => Local_rst ,--: in
D => Data_From_TxFIFO(i) --: in
);
end generate TXFIFO_ADDR_BITS_GENERATE;
---------------------------------------
--C_SPI_MODE_1_WB_ROM_I: dist_mem_gen_v6_4
C_SPI_MODE_1_MIXED_ROM_I: entity dist_mem_gen_v8_0.dist_mem_gen_v8_0
-------------------
generic map(
C_HAS_CLK => 1,
C_READ_MIF => 1,
C_HAS_QSPO => 1,
C_ADDR_WIDTH => C_LUT_DWIDTH,
C_WIDTH => C_LOOK_UP_TABLE_WIDTH,
C_FAMILY => C_FAMILY, -- "virtex6",
C_SYNC_ENABLE => 1,
C_DEPTH => C_LUT_DEPTH,
C_HAS_QSPO_SRST => 1,
C_MEM_INIT_FILE => "mode_1_memory_1_wb.mif",
C_DEFAULT_DATA => "0",
------------------------
C_HAS_QDPO_CLK => 0,
C_HAS_QDPO_CE => 0,
C_PARSER_TYPE => 1,
C_HAS_D => 0,
C_HAS_SPO => 0,
C_REG_A_D_INPUTS => 0,
C_HAS_WE => 0,
C_PIPELINE_STAGES => 0,
C_HAS_QDPO_RST => 0,
C_REG_DPRA_INPUT => 0,
C_QUALIFY_WE => 0,
C_HAS_QDPO_SRST => 0,
C_HAS_DPRA => 0,
C_QCE_JOINED => 0,
C_MEM_TYPE => 0,
C_HAS_I_CE => 0,
C_HAS_DPO => 0,
-- C_HAS_SPRA => 0, -- removed from dist mem gen
C_HAS_QSPO_CE => 0,
C_HAS_QSPO_RST => 0,
C_HAS_QDPO => 0
-------------------------
)
port map(
a => Look_up_address , -- a, -- in std_logic_vector(7 downto 0)
clk => EXT_SPI_CLK , -- clk, -- in
qspo_srst => Rst_to_spi , -- qspo_srst, -- in
qspo => Look_up_op , -- qspo -- out std_logic_vector(9 downto 0)
d => "00000000000",
dpra => "00000000",
we => '0',
i_ce => '1',
qspo_ce => '1',
qdpo_ce => '1',
qdpo_clk => '0',
qspo_rst => '0',
qdpo_rst => '0',
qdpo_srst => '0',
spo => spo_2,
dpo => dpo_2,
qdpo => qdpo_2
);
-- look up table arrangement is as below
-- 10 9 8 7 6 5 4 3 2 1 0
-- Data_Dir Data Mode_1 Data Mode_0 Data_Phase Addr_Mode_1 Addr_Mode_0 Addr_Bit Addr_Ph CMD_Mode_1 CMD Mode_0 CMD_ERROR
-------------
Data_Dir <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 1);-- 10 14
Data_Mode_1 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 2);-- 9 13
Data_Mode_0 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 3);-- 8 12
Data_Phase <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 4);-- 7 11
-------------
Quad_Phase <= '0';
Addr_Mode_1 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 5); -- 6
Addr_Mode_0 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 6); -- 5
Addr_Bit <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 7); -- 4
Addr_Phase <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 8); -- 3
-------------
CMD_Mode_1 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 9); -- 2
CMD_Mode_0 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 10); -- 1
CMD_Error <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - C_LOOK_UP_TABLE_WIDTH)
and CMD_decoded_int; -- 0
-------------
-----------------------------------------
end generate QSPI_LOOK_UP_MODE_1_MEMORY_1;
-----------------------------------------
-------------------------------------------------------------------------------
-- QSPI_LOOK_UP_MODE_1_MEMORY_2: This is Dual mode. Dedicated Numonyx memories are supported.
--------------------------------
QSPI_LOOK_UP_MODE_1_MEMORY_2 : if (C_SPI_MODE = 1 and C_SPI_MEMORY = 2) generate
----------------------------
-- constant declaration
constant C_LOOK_UP_TABLE_WIDTH : integer := 11;
-- signal declaration
signal Look_up_op : std_logic_vector(C_LOOK_UP_TABLE_WIDTH-1 downto 0);
signal CMD_decoded_int_d1 : std_logic;
signal DTR_FIFO_Data_Exists_d1 : std_logic;
signal DTR_FIFO_Data_Exists_d2 : std_logic;
signal DTR_FIFO_Data_Exists_d3 : std_logic;
--signal DTR_FIFO_Data_Exists_d4 : std_logic;
signal spo_3 : std_logic_vector(C_LOOK_UP_TABLE_WIDTH-1 downto 0);
signal dpo_3 : std_logic_vector(C_LOOK_UP_TABLE_WIDTH-1 downto 0);
signal qdpo_3 : std_logic_vector(C_LOOK_UP_TABLE_WIDTH-1 downto 0);
signal Store_DTR_FIFO_First_Data : std_logic;
signal Look_up_address : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
-----
begin
----- _________
-- __| -- DTR_FIFO_Data_Exists
-- ______
-- _____| -- DTR_FIFO_Data_Exists_d1
-- __
-- __| |______ -- Store_DTR_FIFO_First_Data
TRFIFO_DATA_EXIST_D1_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if (EXT_SPI_CLK'event and EXT_SPI_CLK='1') then
if (Rst_to_spi = RESET_ACTIVE) then
DTR_FIFO_Data_Exists_d1 <= '0';
DTR_FIFO_Data_Exists_d2 <= '0';
DTR_FIFO_Data_Exists_d3 <= '0';
--DTR_FIFO_Data_Exists_d4 <= '0';
CMD_decoded_int_d1 <= '0';
CMD_decoded_int <= '0';
else
DTR_FIFO_Data_Exists_d1 <= DTR_FIFO_Data_Exists and pr_state_idle;
CMD_decoded_int_d1 <= DTR_FIFO_Data_Exists_d1 and not DTR_FIFO_Data_Exists_d2;
CMD_decoded_int <= CMD_decoded_int_d1;
--DTR_FIFO_Data_Exists_d2 <= DTR_FIFO_Data_Exists_d1;
--DTR_FIFO_Data_Exists_d3 <= DTR_FIFO_Data_Exists_d2;
--DTR_FIFO_Data_Exists_d4 <= DTR_FIFO_Data_Exists_d3;
--CMD_decoded_int <= DTR_FIFO_Data_Exists_d2 and
-- not(DTR_FIFO_Data_Exists_d3);
end if;
end if;
end process TRFIFO_DATA_EXIST_D1_PROCESS;
-----------------------------------------
CMD_decoded <= CMD_decoded_int;
Store_DTR_FIFO_First_Data <= DTR_FIFO_Data_Exists and
not(DTR_FIFO_Data_Exists_d1) and
Pr_state_idle;
-----------------------------------------
TXFIFO_ADDR_BITS_GENERATE: for i in 0 to (C_NUM_TRANSFER_BITS-1) generate
-----
begin
-----
TXFIFO_FIRST_ENTRY_REG_I: component FDRE
port map
(
Q => Look_up_address(i) ,--: out
C => EXT_SPI_CLK ,--: in
CE => Store_DTR_FIFO_First_Data ,--: in
R => Local_rst ,--: in
D => Data_From_TxFIFO(i) --: in
);
end generate TXFIFO_ADDR_BITS_GENERATE;
---------------------------------------
--C_SPI_MODE_1_NM_ROM_I: dist_mem_gen_v6_4
C_SPI_MODE_1_MIXED_ROM_I: entity dist_mem_gen_v8_0.dist_mem_gen_v8_0
-------------------
generic map(
C_HAS_CLK => 1,
C_READ_MIF => 1,
C_HAS_QSPO => 1,
C_ADDR_WIDTH => C_LUT_DWIDTH,
C_WIDTH => C_LOOK_UP_TABLE_WIDTH,
C_FAMILY => C_FAMILY, -- "virtex6",
C_SYNC_ENABLE => 1,
C_DEPTH => C_LUT_DEPTH,
C_HAS_QSPO_SRST => 1,
C_MEM_INIT_FILE => "mode_1_memory_2_nm.mif",
C_DEFAULT_DATA => "0",
------------------------
C_HAS_QDPO_CLK => 0,
C_HAS_QDPO_CE => 0,
C_PARSER_TYPE => 1,
C_HAS_D => 0,
C_HAS_SPO => 0,
C_REG_A_D_INPUTS => 0,
C_HAS_WE => 0,
C_PIPELINE_STAGES => 0,
C_HAS_QDPO_RST => 0,
C_REG_DPRA_INPUT => 0,
C_QUALIFY_WE => 0,
C_HAS_QDPO_SRST => 0,
C_HAS_DPRA => 0,
C_QCE_JOINED => 0,
C_MEM_TYPE => 0,
C_HAS_I_CE => 0,
C_HAS_DPO => 0,
-- C_HAS_SPRA => 0, -- removed from dist mem gen
C_HAS_QSPO_CE => 0,
C_HAS_QSPO_RST => 0,
C_HAS_QDPO => 0
-------------------------
)
port map(
a => Look_up_address , -- a, -- in std_logic_vector(7 downto 0)
clk => EXT_SPI_CLK , -- clk, -- in
qspo_srst => Rst_to_spi , -- qspo_srst, -- in
qspo => Look_up_op , -- qspo -- out std_logic_vector(9 downto 0)
d => "00000000000",
dpra => "00000000",
we => '0',
i_ce => '1',
qspo_ce => '1',
qdpo_ce => '1',
qdpo_clk => '0',
qspo_rst => '0',
qdpo_rst => '0',
qdpo_srst => '0',
spo => spo_3,
dpo => dpo_3,
qdpo => qdpo_3
);
-- look up table arrangement is as below
-- 10 9 8 7 6 5 4 3 2 1 0
-- Data_Dir Data_Mode_1 Data_Mode_0 Data_Phase Addr_Mode_1 Addr_Mode_0 Addr_Bit Addr_Ph CMD_Mode_1 CMD_Mode_0 CMD_ERROR
-------------
Data_Dir <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 1);-- 10 -- 14
Data_Mode_1 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 2);-- 9 13
Data_Mode_0 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 3);-- 8 12
Data_Phase <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 4);-- 7 11
-------------
Quad_Phase <= '0';
Addr_Mode_1 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 5); -- 6
Addr_Mode_0 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 6); -- 5
Addr_Bit <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 7); -- 4
Addr_Phase <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 8); -- 3
-------------
CMD_Mode_1 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 9); -- 2
CMD_Mode_0 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 10); -- 1
CMD_Error <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - C_LOOK_UP_TABLE_WIDTH)
and CMD_decoded_int; -- 0
-------------
-----------------------------------------
end generate QSPI_LOOK_UP_MODE_1_MEMORY_2;
-----------------------------------------
QSPI_LOOK_UP_MODE_1_MEMORY_3 : if (C_SPI_MODE = 1 and C_SPI_MEMORY = 3) generate
----------------------------
-- constant declaration
constant C_LOOK_UP_TABLE_WIDTH : integer := 11;
-- signal declaration
signal Look_up_op : std_logic_vector(C_LOOK_UP_TABLE_WIDTH-1 downto 0);
signal CMD_decoded_int_d1 : std_logic;
signal DTR_FIFO_Data_Exists_d1 : std_logic;
signal DTR_FIFO_Data_Exists_d2 : std_logic;
signal DTR_FIFO_Data_Exists_d3 : std_logic;
--signal DTR_FIFO_Data_Exists_d4 : std_logic;
signal spo_7 : std_logic_vector(C_LOOK_UP_TABLE_WIDTH-1 downto 0);
signal dpo_7 : std_logic_vector(C_LOOK_UP_TABLE_WIDTH-1 downto 0);
signal qdpo_7 : std_logic_vector(C_LOOK_UP_TABLE_WIDTH-1 downto 0);
signal Store_DTR_FIFO_First_Data : std_logic;
signal Look_up_address : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
-----
begin
----- _________
-- __| -- DTR_FIFO_Data_Exists
-- ______
-- _____| -- DTR_FIFO_Data_Exists_d1
-- __
-- __| |______ -- Store_DTR_FIFO_First_Data
TRFIFO_DATA_EXIST_D1_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if (EXT_SPI_CLK'event and EXT_SPI_CLK='1') then
if (Rst_to_spi = RESET_ACTIVE) then
DTR_FIFO_Data_Exists_d1 <= '0';
DTR_FIFO_Data_Exists_d2 <= '0';
DTR_FIFO_Data_Exists_d3 <= '0';
--DTR_FIFO_Data_Exists_d4 <= '0';
CMD_decoded_int_d1 <= '0';
CMD_decoded_int <= '0';
else
DTR_FIFO_Data_Exists_d1 <= DTR_FIFO_Data_Exists and pr_state_idle;
CMD_decoded_int_d1 <= DTR_FIFO_Data_Exists_d1 and not DTR_FIFO_Data_Exists_d2;
CMD_decoded_int <= CMD_decoded_int_d1;
--DTR_FIFO_Data_Exists_d2 <= DTR_FIFO_Data_Exists_d1;
--DTR_FIFO_Data_Exists_d3 <= DTR_FIFO_Data_Exists_d2;
--DTR_FIFO_Data_Exists_d4 <= DTR_FIFO_Data_Exists_d3;
--CMD_decoded_int <= DTR_FIFO_Data_Exists_d2 and
-- not(DTR_FIFO_Data_Exists_d3);
end if;
end if;
end process TRFIFO_DATA_EXIST_D1_PROCESS;
-----------------------------------------
CMD_decoded <= CMD_decoded_int;
Store_DTR_FIFO_First_Data <= DTR_FIFO_Data_Exists and
not(DTR_FIFO_Data_Exists_d1) and
Pr_state_idle;
-----------------------------------------
TXFIFO_ADDR_BITS_GENERATE: for i in 0 to (C_NUM_TRANSFER_BITS-1) generate
-----
begin
-----
TXFIFO_FIRST_ENTRY_REG_I: component FDRE
port map
(
Q => Look_up_address(i) ,--: out
C => EXT_SPI_CLK ,--: in
CE => Store_DTR_FIFO_First_Data ,--: in
R => Local_rst ,--: in
D => Data_From_TxFIFO(i) --: in
);
end generate TXFIFO_ADDR_BITS_GENERATE;
---------------------------------------
--C_SPI_MODE_1_NM_ROM_I: dist_mem_gen_v6_4
C_SPI_MODE_1_MIXED_ROM_I: entity dist_mem_gen_v8_0.dist_mem_gen_v8_0
-------------------
generic map(
C_HAS_CLK => 1,
C_READ_MIF => 1,
C_HAS_QSPO => 1,
C_ADDR_WIDTH => C_LUT_DWIDTH,
C_WIDTH => C_LOOK_UP_TABLE_WIDTH,
C_FAMILY => C_FAMILY, -- "virtex6",
C_SYNC_ENABLE => 1,
C_DEPTH => C_LUT_DEPTH,
C_HAS_QSPO_SRST => 1,
C_MEM_INIT_FILE => "mode_1_memory_3_sp.mif",
C_DEFAULT_DATA => "0",
------------------------
C_HAS_QDPO_CLK => 0,
C_HAS_QDPO_CE => 0,
C_PARSER_TYPE => 1,
C_HAS_D => 0,
C_HAS_SPO => 0,
C_REG_A_D_INPUTS => 0,
C_HAS_WE => 0,
C_PIPELINE_STAGES => 0,
C_HAS_QDPO_RST => 0,
C_REG_DPRA_INPUT => 0,
C_QUALIFY_WE => 0,
C_HAS_QDPO_SRST => 0,
C_HAS_DPRA => 0,
C_QCE_JOINED => 0,
C_MEM_TYPE => 0,
C_HAS_I_CE => 0,
C_HAS_DPO => 0,
-- C_HAS_SPRA => 0, -- removed from dist mem gen
C_HAS_QSPO_CE => 0,
C_HAS_QSPO_RST => 0,
C_HAS_QDPO => 0
-------------------------
)
port map(
a => Look_up_address , -- a, -- in std_logic_vector(7 downto 0)
clk => EXT_SPI_CLK , -- clk, -- in
qspo_srst => Rst_to_spi , -- qspo_srst, -- in
qspo => Look_up_op , -- qspo -- out std_logic_vector(9 downto 0)
d => "00000000000",
dpra => "00000000",
we => '0',
i_ce => '1',
qspo_ce => '1',
qdpo_ce => '1',
qdpo_clk => '0',
qspo_rst => '0',
qdpo_rst => '0',
qdpo_srst => '0',
spo => spo_7,
dpo => dpo_7,
qdpo => qdpo_7
);
-- look up table arrangement is as below
-- 10 9 8 7 6 5 4 3 2 1 0
-- Data_Dir Data_Mode_1 Data_Mode_0 Data_Phase Addr_Mode_1 Addr_Mode_0 Addr_Bit Addr_Ph CMD_Mode_1 CMD_Mode_0 CMD_ERROR
-------------
Data_Dir <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 1);-- 10 -- 14
Data_Mode_1 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 2);-- 9 13
Data_Mode_0 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 3);-- 8 12
Data_Phase <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 4);-- 7 11
-------------
Quad_Phase <= '0';
Addr_Mode_1 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 5); -- 6
Addr_Mode_0 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 6); -- 5
Addr_Bit <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 7); -- 4
Addr_Phase <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 8); -- 3
-------------
CMD_Mode_1 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 9); -- 2
CMD_Mode_0 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 10); -- 1
CMD_Error <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - C_LOOK_UP_TABLE_WIDTH)
and CMD_decoded_int; -- 0
-------------
-----------------------------------------
end generate QSPI_LOOK_UP_MODE_1_MEMORY_3;
-- LUT for C_SPI_MODE = 1 ends --
-- LUT for C_SPI_MODE = 2 starts --
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- QSPI_LOOK_UP_MODE_2_MEMORY_0: This is Dual mode. Mixed mode memories are supported.
--------------------------------
QSPI_LOOK_UP_MODE_2_MEMORY_0 : if (C_SPI_MODE = 2 and C_SPI_MEMORY = 0) generate
----------------------------
-- constant declaration
constant C_LOOK_UP_TABLE_WIDTH : integer := 12;-- quad phase bit is added to support DQ3 = 1 in command phase for NM memories.
-- signal declaration
signal Look_up_op : std_logic_vector(C_LOOK_UP_TABLE_WIDTH-1 downto 0);
signal CMD_decoded_int_d1 : std_logic;
signal DTR_FIFO_Data_Exists_d1 : std_logic;
signal DTR_FIFO_Data_Exists_d2 : std_logic;
signal DTR_FIFO_Data_Exists_d3 : std_logic;
--signal DTR_FIFO_Data_Exists_d4 : std_logic;
signal spo_6 : std_logic_vector(C_LOOK_UP_TABLE_WIDTH-1 downto 0);
signal dpo_6 : std_logic_vector(C_LOOK_UP_TABLE_WIDTH-1 downto 0);
signal qdpo_6 : std_logic_vector(C_LOOK_UP_TABLE_WIDTH-1 downto 0);
signal Store_DTR_FIFO_First_Data : std_logic;
signal Look_up_address : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
-----
begin
----- _________
-- __| -- DTR_FIFO_Data_Exists
-- ______
-- _____| -- DTR_FIFO_Data_Exists_d1
-- __
-- __| |______ -- Store_DTR_FIFO_First_Data
TRFIFO_DATA_EXIST_D1_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if (EXT_SPI_CLK'event and EXT_SPI_CLK='1') then
if (Rst_to_spi = RESET_ACTIVE) then
DTR_FIFO_Data_Exists_d1 <= '0';
DTR_FIFO_Data_Exists_d2 <= '0';
DTR_FIFO_Data_Exists_d3 <= '0';
--DTR_FIFO_Data_Exists_d4 <= '0';
CMD_decoded_int_d1 <= '0';
CMD_decoded_int <= '0';
else
DTR_FIFO_Data_Exists_d1 <= DTR_FIFO_Data_Exists and pr_state_idle;
CMD_decoded_int_d1 <= DTR_FIFO_Data_Exists_d1 and
not DTR_FIFO_Data_Exists_d2 and
Pr_state_idle;
CMD_decoded_int <= CMD_decoded_int_d1;
--DTR_FIFO_Data_Exists_d2 <= DTR_FIFO_Data_Exists_d1;
--DTR_FIFO_Data_Exists_d3 <= DTR_FIFO_Data_Exists_d2;
--DTR_FIFO_Data_Exists_d4 <= DTR_FIFO_Data_Exists_d3;
--CMD_decoded_int <= DTR_FIFO_Data_Exists_d2 and
-- not(DTR_FIFO_Data_Exists_d3) and
-- Pr_state_idle;
end if;
end if;
end process TRFIFO_DATA_EXIST_D1_PROCESS;
-----------------------------------------
CMD_decoded <= CMD_decoded_int;
Store_DTR_FIFO_First_Data <= DTR_FIFO_Data_Exists and
not(DTR_FIFO_Data_Exists_d1) and
Pr_state_idle;
-----------------------------------------
TXFIFO_ADDR_BITS_GENERATE: for i in 0 to (C_NUM_TRANSFER_BITS-1) generate
-----
begin
-----
TXFIFO_FIRST_ENTRY_REG_I: component FDRE
port map
(
Q => Look_up_address(i) ,--: out
C => EXT_SPI_CLK ,--: in
CE => Store_DTR_FIFO_First_Data ,--: in
R => Local_rst ,--: in
D => Data_From_TxFIFO(i) --: in
);
end generate TXFIFO_ADDR_BITS_GENERATE;
---------------------------------------
--C_SPI_MODE_2_MIXED_ROM_I: dist_mem_gen_v6_4
C_SPI_MODE_1_MIXED_ROM_I: entity dist_mem_gen_v8_0.dist_mem_gen_v8_0
-------------------
generic map(
C_HAS_CLK => 1,
C_READ_MIF => 1,
C_HAS_QSPO => 1,
C_ADDR_WIDTH => C_LUT_DWIDTH,
C_WIDTH => C_LOOK_UP_TABLE_WIDTH,
C_FAMILY => C_FAMILY,
C_SYNC_ENABLE => 1,
C_DEPTH => C_LUT_DEPTH,
C_HAS_QSPO_SRST => 1,
C_MEM_INIT_FILE => "mode_2_memory_0_mixed.mif",
C_DEFAULT_DATA => "0",
------------------------
C_HAS_QDPO_CLK => 0,
C_HAS_QDPO_CE => 0,
C_PARSER_TYPE => 1,
C_HAS_D => 0,
C_HAS_SPO => 0,
C_REG_A_D_INPUTS => 0,
C_HAS_WE => 0,
C_PIPELINE_STAGES => 0,
C_HAS_QDPO_RST => 0,
C_REG_DPRA_INPUT => 0,
C_QUALIFY_WE => 0,
C_HAS_QDPO_SRST => 0,
C_HAS_DPRA => 0,
C_QCE_JOINED => 0,
C_MEM_TYPE => 0,
C_HAS_I_CE => 0,
C_HAS_DPO => 0,
-- C_HAS_SPRA => 0, -- removed from dist mem gen core
C_HAS_QSPO_CE => 0,
C_HAS_QSPO_RST => 0,
C_HAS_QDPO => 0
-------------------------
)
port map(
a => Look_up_address , -- a, -- in std_logic_vector(7 downto 0)
clk => EXT_SPI_CLK , -- clk, -- in
qspo_srst => Rst_to_spi , -- qspo_srst, -- in
qspo => Look_up_op , -- qspo -- out std_logic_vector(9 downto 0)
d => "000000000000",
dpra => "00000000",
we => '0',
i_ce => '1',
qspo_ce => '1',
qdpo_ce => '1',
qdpo_clk => '0',
qspo_rst => '0',
qdpo_rst => '0',
qdpo_srst => '0',
spo => spo_6,
dpo => dpo_6,
qdpo => qdpo_6
);
-- look up table arrangement is as below
-- 11 10 9 8 7 6 5 4 3 2 1 0
-- Data_Dir Data Mode_1 Data Mode_0 Data_Phase Quad_Phase Addr_Mode_1 Addr_Mode_0 Addr_Bit Addr_Ph CMD_Mode_1 CMD Mode_0 CMD Error
-------------
Data_Dir <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 1);-- 15
Data_Mode_1 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 2);-- 14
Data_Mode_0 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 3);-- 13
Data_Phase <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 4);-- 12
-------------
Quad_Phase <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 5); -- 7
Addr_Mode_1 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 6);-- 6
Addr_Mode_0 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 7);-- 5
Addr_Bit <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 8);-- 4
Addr_Phase <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 9);-- 3
-------------
CMD_Mode_1 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 10);-- 2
CMD_Mode_0 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 11);-- 1
CMD_Error <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - C_LOOK_UP_TABLE_WIDTH)
and CMD_decoded_int; -- 0
-------------
-----------------------------------------
end generate QSPI_LOOK_UP_MODE_2_MEMORY_0;
-----------------------------------------
-------------------------------------------------------------------------------
-- QSPI_LOOK_UP_MODE_2_MEMORY_1: This is Dual mode. Dedicated Winbond memories are supported.
--------------------------------
QSPI_LOOK_UP_MODE_2_MEMORY_1 : if (C_SPI_MODE = 2 and C_SPI_MEMORY = 1) generate
----------------------------
-- constant declaration
constant C_LOOK_UP_TABLE_WIDTH : integer := 11;
-- signal declaration
signal Look_up_op : std_logic_vector(C_LOOK_UP_TABLE_WIDTH-1 downto 0);
signal CMD_decoded_int_d1 : std_logic;
signal DTR_FIFO_Data_Exists_d1 : std_logic;
signal DTR_FIFO_Data_Exists_d2 : std_logic;
signal DTR_FIFO_Data_Exists_d3 : std_logic;
--signal DTR_FIFO_Data_Exists_d4 : std_logic;
signal spo_4 : std_logic_vector(C_LOOK_UP_TABLE_WIDTH-1 downto 0);
signal dpo_4 : std_logic_vector(C_LOOK_UP_TABLE_WIDTH-1 downto 0);
signal qdpo_4 : std_logic_vector(C_LOOK_UP_TABLE_WIDTH-1 downto 0);
signal Store_DTR_FIFO_First_Data : std_logic;
signal Look_up_address : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
-----
begin
----- _________
-- __| -- DTR_FIFO_Data_Exists
-- ______
-- _____| -- DTR_FIFO_Data_Exists_d1
-- __
-- __| |______ -- Store_DTR_FIFO_First_Data
TRFIFO_DATA_EXIST_D1_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if (EXT_SPI_CLK'event and EXT_SPI_CLK='1') then
if (Rst_to_spi = RESET_ACTIVE) then
DTR_FIFO_Data_Exists_d1 <= '0';
DTR_FIFO_Data_Exists_d2 <= '0';
DTR_FIFO_Data_Exists_d3 <= '0';
--DTR_FIFO_Data_Exists_d4 <= '0';
CMD_decoded_int_d1 <= '0';
CMD_decoded_int <= '0';
else
DTR_FIFO_Data_Exists_d1 <= DTR_FIFO_Data_Exists and pr_state_idle;
CMD_decoded_int_d1 <= DTR_FIFO_Data_Exists_d1 and
not DTR_FIFO_Data_Exists_d2;
CMD_decoded_int <= CMD_decoded_int_d1;
-- DTR_FIFO_Data_Exists_d2 <= DTR_FIFO_Data_Exists_d1;
-- DTR_FIFO_Data_Exists_d3 <= DTR_FIFO_Data_Exists_d2;
-- --DTR_FIFO_Data_Exists_d4 <= DTR_FIFO_Data_Exists_d3;
-- CMD_decoded_int <= DTR_FIFO_Data_Exists_d2 and
-- not(DTR_FIFO_Data_Exists_d3);
end if;
end if;
end process TRFIFO_DATA_EXIST_D1_PROCESS;
-----------------------------------------
CMD_decoded <= CMD_decoded_int;
Store_DTR_FIFO_First_Data <= DTR_FIFO_Data_Exists and
not(DTR_FIFO_Data_Exists_d1) and
Pr_state_idle;
-----------------------------------------
TXFIFO_ADDR_BITS_GENERATE: for i in 0 to (C_NUM_TRANSFER_BITS-1) generate
-----
begin
-----
TXFIFO_FIRST_ENTRY_REG_I: component FDRE
port map
(
Q => Look_up_address(i) ,--: out
C => EXT_SPI_CLK ,--: in
CE => Store_DTR_FIFO_First_Data ,--: in
R => Local_rst ,--: in
D => Data_From_TxFIFO(i) --: in
);
end generate TXFIFO_ADDR_BITS_GENERATE;
---------------------------------------
--C_SPI_MODE_2_WB_ROM_I: dist_mem_gen_v6_4
C_SPI_MODE_1_MIXED_ROM_I: entity dist_mem_gen_v8_0.dist_mem_gen_v8_0
-------------------
generic map(
C_HAS_CLK => 1,
C_READ_MIF => 1,
C_HAS_QSPO => 1,
C_ADDR_WIDTH => C_LUT_DWIDTH,
C_WIDTH => C_LOOK_UP_TABLE_WIDTH,
C_FAMILY => C_FAMILY,
C_SYNC_ENABLE => 1,
C_DEPTH => C_LUT_DEPTH,
C_HAS_QSPO_SRST => 1,
C_MEM_INIT_FILE => "mode_2_memory_1_wb.mif",
C_DEFAULT_DATA => "0",
------------------------
C_HAS_QDPO_CLK => 0,
C_HAS_QDPO_CE => 0,
C_PARSER_TYPE => 1,
C_HAS_D => 0,
C_HAS_SPO => 0,
C_REG_A_D_INPUTS => 0,
C_HAS_WE => 0,
C_PIPELINE_STAGES => 0,
C_HAS_QDPO_RST => 0,
C_REG_DPRA_INPUT => 0,
C_QUALIFY_WE => 0,
C_HAS_QDPO_SRST => 0,
C_HAS_DPRA => 0,
C_QCE_JOINED => 0,
C_MEM_TYPE => 0,
C_HAS_I_CE => 0,
C_HAS_DPO => 0,
-- C_HAS_SPRA => 0, -- removed from dist mem gen core
C_HAS_QSPO_CE => 0,
C_HAS_QSPO_RST => 0,
C_HAS_QDPO => 0
-------------------------
)
port map(
a => Look_up_address , -- a, -- in std_logic_vector(7 downto 0)
clk => EXT_SPI_CLK , -- clk, -- in
qspo_srst => Rst_to_spi , -- qspo_srst, -- in
qspo => Look_up_op , -- qspo -- out std_logic_vector(9 downto 0)
d => "00000000000",
dpra => "00000000",
we => '0',
i_ce => '1',
qspo_ce => '1',
qdpo_ce => '1',
qdpo_clk => '0',
qspo_rst => '0',
qdpo_rst => '0',
qdpo_srst => '0',
spo => spo_4,
dpo => dpo_4,
qdpo => qdpo_4
);
-- look up table arrangement is as below
-- 10 9 8 7 6 5 4 3 2 1 0
-- Data_Dir Data Mode_1 Data Mode_0 Data_Phase Addr Mode_1 Addr_Mode_0 Addr_Bit Addr_Ph CMD_Mode_1 CMD Mode_0 CMD Error
-------------
Data_Dir <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 1);-- 10 -- 14
Data_Mode_1 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 2);-- 9 13
Data_Mode_0 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 3);-- 8 12
Data_Phase <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 4);-- 7 11
-------------
Quad_Phase <= '0';
Addr_Mode_1 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 5); -- 6
Addr_Mode_0 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 6); -- 5
Addr_Bit <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 7); -- 4
Addr_Phase <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 8); -- 3
-------------
CMD_Mode_1 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 9);-- 2
CMD_Mode_0 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 10);-- 1
CMD_Error <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - C_LOOK_UP_TABLE_WIDTH)
and CMD_decoded_int; -- 0
-------------
-- Dummy_Bits <= (Dummy_3 and DTR_FIFO_Data_Exists) &
-- (Dummy_2 and DTR_FIFO_Data_Exists) &
-- (Dummy_1 and DTR_FIFO_Data_Exists) &
-- (Dummy_0 and DTR_FIFO_Data_Exists);
-----------------------------------------
end generate QSPI_LOOK_UP_MODE_2_MEMORY_1;
-----------------------------------------
-------------------------------------------------------------------------------
-- QSPI_LOOK_UP_MODE_2_MEMORY_2: This is Dual mode. Dedicated Numonyx memories are supported.
--------------------------------
QSPI_LOOK_UP_MODE_2_MEMORY_2 : if (C_SPI_MODE = 2 and C_SPI_MEMORY = 2) generate
----------------------------
-- constant declaration
constant C_LOOK_UP_TABLE_WIDTH : integer := 12;-- quad phase bit is added to support DQ3 = 1 in command phase for NM memories.
-- signal declaration
signal Look_up_op : std_logic_vector(C_LOOK_UP_TABLE_WIDTH-1 downto 0);
signal CMD_decoded_int_d1 : std_logic;
signal DTR_FIFO_Data_Exists_d1 : std_logic;
signal DTR_FIFO_Data_Exists_d2 : std_logic;
signal DTR_FIFO_Data_Exists_d3 : std_logic;
--signal DTR_FIFO_Data_Exists_d4 : std_logic;
signal spo_5 : std_logic_vector(C_LOOK_UP_TABLE_WIDTH-1 downto 0);
signal dpo_5 : std_logic_vector(C_LOOK_UP_TABLE_WIDTH-1 downto 0);
signal qdpo_5 : std_logic_vector(C_LOOK_UP_TABLE_WIDTH-1 downto 0);
signal Store_DTR_FIFO_First_Data : std_logic;
signal Look_up_address : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
-----
begin
----- _________
-- __| -- DTR_FIFO_Data_Exists
-- ______
-- _____| -- DTR_FIFO_Data_Exists_d1
-- __
-- __| |______ -- Store_DTR_FIFO_First_Data
TRFIFO_DATA_EXIST_D1_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if (EXT_SPI_CLK'event and EXT_SPI_CLK='1') then
if (Rst_to_spi = RESET_ACTIVE) then
DTR_FIFO_Data_Exists_d1 <= '0';
DTR_FIFO_Data_Exists_d2 <= '0';
DTR_FIFO_Data_Exists_d3 <= '0';
CMD_decoded_int_d1 <= '0';
CMD_decoded_int <= '0';
else
DTR_FIFO_Data_Exists_d1 <= DTR_FIFO_Data_Exists and pr_state_idle;
CMD_decoded_int_d1 <= DTR_FIFO_Data_Exists_d1 and
not DTR_FIFO_Data_Exists_d2 and
Pr_state_idle;
CMD_decoded_int <= CMD_decoded_int_d1;
--DTR_FIFO_Data_Exists_d2 <= DTR_FIFO_Data_Exists_d1;
--DTR_FIFO_Data_Exists_d3 <= DTR_FIFO_Data_Exists_d2;
--CMD_decoded_int <= DTR_FIFO_Data_Exists_d2 and
-- not(DTR_FIFO_Data_Exists_d3) and
-- Pr_state_idle;
end if;
end if;
end process TRFIFO_DATA_EXIST_D1_PROCESS;
-----------------------------------------
CMD_decoded <= CMD_decoded_int;
Store_DTR_FIFO_First_Data <= DTR_FIFO_Data_Exists and
not(DTR_FIFO_Data_Exists_d1) and
Pr_state_idle;
-----------------------------------------
TXFIFO_ADDR_BITS_GENERATE: for i in 0 to (C_NUM_TRANSFER_BITS-1) generate
-----
begin
-----
TXFIFO_FIRST_ENTRY_REG_I: component FDRE
port map
(
Q => Look_up_address(i) ,--: out
C => EXT_SPI_CLK ,--: in
CE => Store_DTR_FIFO_First_Data ,--: in
R => Local_rst ,--: in
D => Data_From_TxFIFO(i) --: in
);
end generate TXFIFO_ADDR_BITS_GENERATE;
---------------------------------------
--C_SPI_MODE_2_NM_ROM_I: dist_mem_gen_v6_4
C_SPI_MODE_1_MIXED_ROM_I: entity dist_mem_gen_v8_0.dist_mem_gen_v8_0
-------------------
generic map(
C_HAS_CLK => 1,
C_READ_MIF => 1,
C_HAS_QSPO => 1,
C_ADDR_WIDTH => C_LUT_DWIDTH,
C_WIDTH => C_LOOK_UP_TABLE_WIDTH,
C_FAMILY => C_FAMILY, -- "virtex6",
C_SYNC_ENABLE => 1,
C_DEPTH => C_LUT_DEPTH,
C_HAS_QSPO_SRST => 1,
C_MEM_INIT_FILE => "mode_2_memory_2_nm.mif",
C_DEFAULT_DATA => "0",
------------------------
C_HAS_QDPO_CLK => 0,
C_HAS_QDPO_CE => 0,
C_PARSER_TYPE => 1,
C_HAS_D => 0,
C_HAS_SPO => 0,
C_REG_A_D_INPUTS => 0,
C_HAS_WE => 0,
C_PIPELINE_STAGES => 0,
C_HAS_QDPO_RST => 0,
C_REG_DPRA_INPUT => 0,
C_QUALIFY_WE => 0,
C_HAS_QDPO_SRST => 0,
C_HAS_DPRA => 0,
C_QCE_JOINED => 0,
C_MEM_TYPE => 0,
C_HAS_I_CE => 0,
C_HAS_DPO => 0,
-- C_HAS_SPRA => 0, -- removed from dist mem gen core
C_HAS_QSPO_CE => 0,
C_HAS_QSPO_RST => 0,
C_HAS_QDPO => 0
-------------------------
)
port map(
a => Look_up_address , -- a, -- in std_logic_vector(7 downto 0)
clk => EXT_SPI_CLK , -- clk, -- in
qspo_srst => Rst_to_spi , -- qspo_srst, -- in
qspo => Look_up_op, -- qspo -- out std_logic_vector(9 downto 0)
d => "000000000000",
dpra => "00000000",
we => '0',
i_ce => '1',
qspo_ce => '1',
qdpo_ce => '1',
qdpo_clk => '0',
qspo_rst => '0',
qdpo_rst => '0',
qdpo_srst => '0',
spo => spo_5,
dpo => dpo_5,
qdpo => qdpo_5
);
-- look up table arrangement is as below
-- 11 10 9 8 7 6 5 4 3 2 1 0
-- Data_Dir Data Mode_1 Data Mode_0 Data_Phase Quad_Phase Addr_Mode_1 Addr_Mode_0 Addr_Bit Addr_Ph CMD_Mode_1 CMD Mode_0 CMD Error
-------------
Data_Dir <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 1);-- 11 -- 15
Data_Mode_1 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 2);-- 10 -- 14
Data_Mode_0 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 3);-- 9 -- 13
Data_Phase <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 4);-- 8 -- 12
-------------
Quad_Phase <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 5); -- 7
Addr_Mode_1 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 6);-- 6
Addr_Mode_0 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 7);-- 5
Addr_Bit <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 8);-- 4
Addr_Phase <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 9);-- 3
-------------
CMD_Mode_1 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 10);-- 2
CMD_Mode_0 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 11);-- 1
CMD_Error <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - C_LOOK_UP_TABLE_WIDTH)
and CMD_decoded_int; -- 0
-------------
-----------------------------------------
end generate QSPI_LOOK_UP_MODE_2_MEMORY_2;
-----------------------------------------
QSPI_LOOK_UP_MODE_2_MEMORY_3 : if (C_SPI_MODE = 2 and C_SPI_MEMORY = 3) generate
----------------------------
-- constant declaration
constant C_LOOK_UP_TABLE_WIDTH : integer := 12;-- quad phase bit is added to support DQ3 = 1 in command phase for NM memories.
-- signal declaration
signal Look_up_op : std_logic_vector(C_LOOK_UP_TABLE_WIDTH-1 downto 0);
signal CMD_decoded_int_d1 : std_logic;
signal DTR_FIFO_Data_Exists_d1 : std_logic;
signal DTR_FIFO_Data_Exists_d2 : std_logic;
signal DTR_FIFO_Data_Exists_d3 : std_logic;
--signal DTR_FIFO_Data_Exists_d4 : std_logic;
signal spo_8 : std_logic_vector(C_LOOK_UP_TABLE_WIDTH-1 downto 0);
signal dpo_8 : std_logic_vector(C_LOOK_UP_TABLE_WIDTH-1 downto 0);
signal qdpo_8 : std_logic_vector(C_LOOK_UP_TABLE_WIDTH-1 downto 0);
signal Store_DTR_FIFO_First_Data : std_logic;
signal Look_up_address : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
-----
begin
----- _________
-- __| -- DTR_FIFO_Data_Exists
-- ______
-- _____| -- DTR_FIFO_Data_Exists_d1
-- __
-- __| |______ -- Store_DTR_FIFO_First_Data
TRFIFO_DATA_EXIST_D1_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if (EXT_SPI_CLK'event and EXT_SPI_CLK='1') then
if (Rst_to_spi = RESET_ACTIVE) then
DTR_FIFO_Data_Exists_d1 <= '0';
DTR_FIFO_Data_Exists_d2 <= '0';
DTR_FIFO_Data_Exists_d3 <= '0';
CMD_decoded_int_d1 <= '0';
CMD_decoded_int <= '0';
else
DTR_FIFO_Data_Exists_d1 <= DTR_FIFO_Data_Exists and pr_state_idle;
CMD_decoded_int_d1 <= DTR_FIFO_Data_Exists_d1 and
not DTR_FIFO_Data_Exists_d2 and
Pr_state_idle;
CMD_decoded_int <= CMD_decoded_int_d1;
--DTR_FIFO_Data_Exists_d2 <= DTR_FIFO_Data_Exists_d1;
--DTR_FIFO_Data_Exists_d3 <= DTR_FIFO_Data_Exists_d2;
--CMD_decoded_int <= DTR_FIFO_Data_Exists_d2 and
-- not(DTR_FIFO_Data_Exists_d3) and
-- Pr_state_idle;
end if;
end if;
end process TRFIFO_DATA_EXIST_D1_PROCESS;
-----------------------------------------
CMD_decoded <= CMD_decoded_int;
Store_DTR_FIFO_First_Data <= DTR_FIFO_Data_Exists and
not(DTR_FIFO_Data_Exists_d1) and
Pr_state_idle;
-----------------------------------------
TXFIFO_ADDR_BITS_GENERATE: for i in 0 to (C_NUM_TRANSFER_BITS-1) generate
-----
begin
-----
TXFIFO_FIRST_ENTRY_REG_I: component FDRE
port map
(
Q => Look_up_address(i) ,--: out
C => EXT_SPI_CLK ,--: in
CE => Store_DTR_FIFO_First_Data ,--: in
R => Local_rst ,--: in
D => Data_From_TxFIFO(i) --: in
);
end generate TXFIFO_ADDR_BITS_GENERATE;
---------------------------------------
--C_SPI_MODE_2_NM_ROM_I: dist_mem_gen_v6_4
C_SPI_MODE_1_MIXED_ROM_I: entity dist_mem_gen_v8_0.dist_mem_gen_v8_0
-------------------
generic map(
C_HAS_CLK => 1,
C_READ_MIF => 1,
C_HAS_QSPO => 1,
C_ADDR_WIDTH => C_LUT_DWIDTH,
C_WIDTH => C_LOOK_UP_TABLE_WIDTH,
C_FAMILY => C_FAMILY, -- "virtex6",
C_SYNC_ENABLE => 1,
C_DEPTH => C_LUT_DEPTH,
C_HAS_QSPO_SRST => 1,
C_MEM_INIT_FILE => "mode_2_memory_3_sp.mif",
C_DEFAULT_DATA => "0",
------------------------
C_HAS_QDPO_CLK => 0,
C_HAS_QDPO_CE => 0,
C_PARSER_TYPE => 1,
C_HAS_D => 0,
C_HAS_SPO => 0,
C_REG_A_D_INPUTS => 0,
C_HAS_WE => 0,
C_PIPELINE_STAGES => 0,
C_HAS_QDPO_RST => 0,
C_REG_DPRA_INPUT => 0,
C_QUALIFY_WE => 0,
C_HAS_QDPO_SRST => 0,
C_HAS_DPRA => 0,
C_QCE_JOINED => 0,
C_MEM_TYPE => 0,
C_HAS_I_CE => 0,
C_HAS_DPO => 0,
-- C_HAS_SPRA => 0, -- removed from dist mem gen core
C_HAS_QSPO_CE => 0,
C_HAS_QSPO_RST => 0,
C_HAS_QDPO => 0
-------------------------
)
port map(
a => Look_up_address , -- a, -- in std_logic_vector(7 downto 0)
clk => EXT_SPI_CLK , -- clk, -- in
qspo_srst => Rst_to_spi , -- qspo_srst, -- in
qspo => Look_up_op, -- qspo -- out std_logic_vector(9 downto 0)
d => "000000000000",
dpra => "00000000",
we => '0',
i_ce => '1',
qspo_ce => '1',
qdpo_ce => '1',
qdpo_clk => '0',
qspo_rst => '0',
qdpo_rst => '0',
qdpo_srst => '0',
spo => spo_8,
dpo => dpo_8,
qdpo => qdpo_8
);
-- look up table arrangement is as below
-- 11 10 9 8 7 6 5 4 3 2 1 0
-- Data_Dir Data Mode_1 Data Mode_0 Data_Phase Quad_Phase Addr_Mode_1 Addr_Mode_0 Addr_Bit Addr_Ph CMD_Mode_1 CMD Mode_0 CMD Error
-------------
Data_Dir <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 1);-- 11 -- 15
Data_Mode_1 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 2);-- 10 -- 14
Data_Mode_0 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 3);-- 9 -- 13
Data_Phase <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 4);-- 8 -- 12
-------------
Quad_Phase <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 5); -- 7
Addr_Mode_1 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 6);-- 6
Addr_Mode_0 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 7);-- 5
Addr_Bit <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 8);-- 4
Addr_Phase <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 9);-- 3
-------------
CMD_Mode_1 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 10);-- 2
CMD_Mode_0 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 11);-- 1
CMD_Error <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - C_LOOK_UP_TABLE_WIDTH)
and CMD_decoded_int; -- 0
-------------
-----------------------------------------
end generate QSPI_LOOK_UP_MODE_2_MEMORY_3;
---------------------
end architecture imp;
---------------------
| gpl-2.0 | a0eb95ee2dc7a9d8ee9231867c76f8d6 | 0.379088 | 3.924852 | false | false | false | false |
TimingKeepers/gen-ugr-cores | modules/wishbone/wb_i2c_arb/i2c_arbiter_redirector.vhd | 1 | 6,129 | -------------------------------------------------------------------------------
-- Title : I2C Bus Arbiter Redirector
-- Project : White Rabbit Project
-------------------------------------------------------------------------------
-- File : i2c_arbiter_redirector.vhd
-- Author : Miguel Jimenez Lopez
-- Company : UGR
-- Created : 2015-08-06
-- Last update: 2015-08-06
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
--
-- This component allows to share a single I2C bus for many masters in a simple
-- way.
--
-------------------------------------------------------------------------------
-- TODO:
-------------------------------------------------------------------------------
--
-- Copyright (c) 2015 UGR
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity i2c_arbiter_redirector is
generic (
g_num_inputs : natural range 2 to 32 := 2;
g_enable_oen : boolean := false
);
port (
-- Clock & Reset
clk_i : in std_logic;
rst_n_i : in std_logic;
enable_i : in std_logic;
-- I2C input buses
input_sda_i : in std_logic_vector(g_num_inputs-1 downto 0);
input_sda_o : out std_logic_vector(g_num_inputs-1 downto 0);
input_sda_oen : in std_logic_vector(g_num_inputs-1 downto 0);
input_scl_i : in std_logic_vector(g_num_inputs-1 downto 0);
input_scl_o : out std_logic_vector(g_num_inputs-1 downto 0);
input_scl_oen : in std_logic_vector(g_num_inputs-1 downto 0);
-- I2C output bus
output_sda_i : in std_logic;
output_sda_o : out std_logic;
output_sda_oen : out std_logic;
output_scl_i : in std_logic;
output_scl_o : out std_logic;
output_scl_oen : out std_logic;
-- Redirector index & enable
input_enabled_i : std_logic;
input_idx_enabled_i : integer range 0 to g_num_inputs-1
);
end i2c_arbiter_redirector;
architecture struct of i2c_arbiter_redirector is
begin
gen_input_logic: for I in 0 to g_num_inputs-1 generate
input_logic: process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
input_sda_o(I) <= '1';
input_scl_o(I) <= '1';
else
if enable_i = '1' and input_enabled_i = '1' then
if I /= input_idx_enabled_i then
input_sda_o(I) <= '1';
input_scl_o(I) <= '1';
else
input_sda_o(I) <= output_sda_i;
input_scl_o(I) <= output_scl_i;
end if;
else
input_sda_o(I) <= '1';
input_scl_o(I) <= '1';
end if;
end if;
end if;
end process input_logic;
end generate gen_input_logic;
output_logic: process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
output_sda_o <= '1';
output_scl_o <= '1';
else
if enable_i = '1' and input_enabled_i = '1' then
output_sda_o <= input_sda_i(input_idx_enabled_i);
output_scl_o <= input_scl_i(input_idx_enabled_i);
else
output_sda_o <= '1';
output_scl_o <= '1';
end if;
end if;
end if;
end process output_logic;
gen_oen_signal: if g_enable_oen generate
output_logic_en : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
output_sda_oen <= '0';
output_scl_oen <= '0';
else
if enable_i = '1' and input_enabled_i = '1' then
output_sda_oen <= input_sda_oen(input_idx_enabled_i);
output_scl_oen <= input_scl_oen(input_idx_enabled_i);
else
output_sda_oen <= '0';
output_scl_oen <= '0';
end if;
end if;
end if;
end process output_logic_en;
end generate gen_oen_signal;
not_gen_oen_signal : if not g_enable_oen generate
output_sda_oen <= '0';
output_scl_oen <= '0';
end generate not_gen_oen_signal;
-- Old tested version
--main: process(clk_i)
--begin
-- if rising_edge(clk_i) then
-- if rst_n_i = '0' then
-- for I in 0 to g_num_inputs-1 loop
-- input_sda_o(I) <= '1';
-- input_scl_o(I) <= '1';
-- end loop;
-- output_sda_o <= '1';
-- output_scl_o <= '1';
-- else
-- if enable_i = '1' and input_enabled_i = '1' then
-- for I in 0 to g_num_inputs-1 loop
-- if I /= input_idx_enabled_i then
-- input_sda_o(I) <= '1';
-- input_scl_o(I) <= '1';
-- else
-- output_sda_o <= input_sda_i(I);
-- output_scl_o <= input_scl_i(I);
-- input_sda_o(I) <= output_sda_i;
-- input_scl_o(I) <= output_scl_i;
-- end if;
-- end loop;
-- else
-- for I in 0 to g_num_inputs-1 loop
-- input_sda_o(I) <= '1';
-- input_scl_o(I) <= '1';
-- end loop;
-- output_sda_o <= '1';
-- output_scl_o <= '1';
-- end if;
-- end if;
-- end if;
--end process main;
end struct;
| gpl-2.0 | 8a42d0bcf13b89885cc72c84a4f85ee3 | 0.500082 | 3.295161 | false | false | false | false |
Hyperion302/omega-cpu | UnitTests/Divider/divider.vhdl | 1 | 1,725 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.Numeric_std.all;
entity Divider is
port (
Enable : in std_logic;
Ready : out std_logic;
CLK : in std_logic;
Overflow : out std_logic;
Divisor : in std_logic_vector(31 downto 0);
Dividend : in std_logic_vector(31 downto 0);
Remainder : out std_logic_vector(31 downto 0);
Quotient : out std_logic_vector(31 downto 0));
end Divider;
architecture Behavioral of Divider is
signal Enable_S : std_logic;
signal Ready_S : std_logic;
signal Overflow_S : std_logic;
signal Divisor_S : std_logic_vector(31 downto 0);
signal Quotient_S : std_logic_vector(31 downto 0);
signal Remainder_S : std_logic_vector(31 downto 0);
signal Dividend_S : std_logic_vector(31 downto 0);
begin
Enable_S <= Enable;
Ready <= Ready_S;
Overflow <= Overflow_S;
Divisor_S <= Divisor;
Quotient <= Quotient_S;
Remainder <= Remainder_S;
Dividend_S <= Dividend;
Divide: process (CLK)
begin -- process Divide
if rising_edge(CLK) then
if Enable_S = '1' then
if Divisor_S = "00000000000000000000000000000000" then
Ready_S <= '1';
Overflow_S <= '1';
Quotient_S <= (others => '0');
Remainder_S <= (others => '0');
else
Quotient_S <= std_logic_vector(unsigned(Dividend_S) / unsigned(Divisor_S));
Remainder_S <= std_logic_vector(unsigned(Dividend_S) rem unsigned(Divisor_S));
Ready_S <= '1';
Overflow_S <= '0';
end if;
else
Ready_S <= '0';
Overflow_S <= '0';
Quotient_S <= (others => '0');
Remainder_S <= (others => '0');
end if;
end if;
end process;
end Behavioral;
| lgpl-3.0 | d2bde1c4c0c2a964b723e97e0abb5b36 | 0.6 | 3.470825 | false | false | false | false |
pkerling/ethernet_mac_test | clock_generator.vhd | 1 | 4,467 | -- This file is part of the ethernet_mac_test project.
--
-- For the full copyright and license information, please read the
-- LICENSE.md file that was distributed with this source code.
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity clock_generator is
port(
reset_i : in std_ulogic;
clock_125_i : in std_ulogic;
clock_125_o : out std_ulogic;
clock_125_inv_o : out std_ulogic;
clock_125_unbuffered_o : out std_ulogic;
clock_50_o : out std_ulogic;
locked_o : out std_ulogic
);
end entity;
architecture spartan of clock_generator is
signal int_clock_125 : std_ulogic;
signal int_clock_125_buffered : std_ulogic;
signal int_clock_125_inv : std_ulogic;
signal int_clock_50 : std_ulogic;
signal clock_feedback : std_ulogic;
begin
clock_125_unbuffered_o <= int_clock_125;
clock_125_o <= int_clock_125_buffered;
BUFIO2FB_inst : BUFIO2FB
generic map(
DIVIDE_BYPASS => TRUE -- Bypass divider (TRUE/FALSE)
)
port map(
O => clock_feedback, -- 1-bit output: Output feedback clock (connect to feedback input of DCM/PLL)
I => int_clock_125_buffered -- 1-bit input: Feedback clock input (connect to input port)
);
clock_125_BUFG_inst : BUFG
port map(
O => int_clock_125_buffered, -- 1-bit output: Clock buffer output
I => int_clock_125 -- 1-bit input: Clock buffer input
);
clock_125_inv_BUFG_inst : BUFG
port map(
O => clock_125_inv_o, -- 1-bit output: Clock buffer output
I => int_clock_125_inv -- 1-bit input: Clock buffer input
);
clock_50_BUFG_inst : BUFG
port map(
O => clock_50_o,
I => int_clock_50
);
-- TODO Remove BUFIO2FB
DCM_SP_inst : DCM_SP
generic map(
CLKDV_DIVIDE => 5.0, -- CLKDV divide value
-- (1.5,2,2.5,3,3.5,4,4.5,5,5.5,6,6.5,7,7.5,8,9,10,11,12,13,14,15,16).
CLKFX_DIVIDE => 5, -- Divide value on CLKFX outputs - D - (1-32)
CLKFX_MULTIPLY => 2, -- Multiply value on CLKFX outputs - M - (2-32)
CLKIN_DIVIDE_BY_2 => FALSE, -- CLKIN divide by two (TRUE/FALSE)
CLKIN_PERIOD => 8.0, -- Input clock period specified in nS
CLKOUT_PHASE_SHIFT => "NONE", -- Output phase shift (NONE, FIXED, VARIABLE)
CLK_FEEDBACK => "1X", -- Feedback source (NONE, 1X, 2X)
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SYSTEM_SYNCHRNOUS or SOURCE_SYNCHRONOUS
DFS_FREQUENCY_MODE => "LOW", -- Unsupported - Do not change value
DLL_FREQUENCY_MODE => "LOW", -- Unsupported - Do not change value
DSS_MODE => "NONE", -- Unsupported - Do not change value
DUTY_CYCLE_CORRECTION => TRUE, -- Unsupported - Do not change value
FACTORY_JF => X"c080", -- Unsupported - Do not change value
PHASE_SHIFT => 0, -- Amount of fixed phase shift (-255 to 255)
STARTUP_WAIT => FALSE -- Delay config DONE until DCM_SP LOCKED (TRUE/FALSE)
)
port map(
CLK0 => int_clock_125, -- 1-bit output: 0 degree clock output
CLK180 => int_clock_125_inv, -- 1-bit output: 180 degree clock output
CLK270 => open, -- 1-bit output: 270 degree clock output
CLK2X => open, -- 1-bit output: 2X clock frequency clock output
CLK2X180 => open, -- 1-bit output: 2X clock frequency, 180 degree clock output
CLK90 => open, -- 1-bit output: 90 degree clock output
CLKDV => open, -- 1-bit output: Divided clock output
CLKFX => int_clock_50, -- 1-bit output: Digital Frequency Synthesizer output (DFS)
CLKFX180 => open, -- 1-bit output: 180 degree CLKFX output
LOCKED => locked_o, -- 1-bit output: DCM_SP Lock Output
PSDONE => open, -- 1-bit output: Phase shift done output
STATUS => open, -- 8-bit output: DCM_SP status output
CLKFB => clock_feedback, -- 1-bit input: Clock feedback input
CLKIN => clock_125_i, -- 1-bit input: Clock input
DSSEN => '0', -- 1-bit input: Unsupported, specify to GND.
PSCLK => '0', -- 1-bit input: Phase shift clock input
PSEN => '0', -- 1-bit input: Phase shift enable
PSINCDEC => '0', -- 1-bit input: Phase shift increment/decrement input
RST => '0' -- 1-bit input: Active high reset input
);
end architecture; | bsd-3-clause | 01b19d91b9cb2b1c2ed6ced1e1a83ff5 | 0.601746 | 3.296679 | false | false | false | false |
dpolad/dlx | DLX_vhd/a.l-MEMREGS.vhd | 1 | 1,100 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--use work.myTypes.all;
entity mem_regs is
generic (
SIZE : integer := 32
);
port (
W_i : in std_logic_vector(SIZE - 1 downto 0);
D3_i : in std_logic_vector(4 downto 0);
W_o : out std_logic_vector(SIZE - 1 downto 0);
D3_o : out std_logic_vector(4 downto 0);
FW_4_o : out std_logic_vector(SIZE - 1 downto 0);
clk : in std_logic;
rst : in std_logic
);
end mem_regs;
architecture Struct of mem_regs is
component ff32
generic(
SIZE : integer
);
port(
D : in std_logic_vector(SIZE - 1 downto 0);
Q : out std_logic_vector(SIZE - 1 downto 0);
clk : in std_logic;
rst : in std_logic
);
end component;
signal W_help : std_logic_vector(SIZE -1 downto 0);
begin
W_o <= W_help;
W: ff32 generic map(
SIZE => 32
)
port map(
D => W_i,
Q => W_help,
clk => clk,
rst => rst
);
FW4: ff32 generic map(
SIZE => 32
)
port map(
D => W_help,
Q => FW_4_o,
clk => clk,
rst => rst
);
D3: ff32 generic map(
SIZE => 5
)
port map(
D => D3_i,
Q => D3_o,
clk => clk,
rst => rst
);
end Struct;
| bsd-2-clause | 17a3d2d2d2545a54cbcfba5b9a4a47ff | 0.602727 | 2.21328 | false | false | false | false |
SWORDfpga/ComputerOrganizationDesign | labs/lab12/lab12/ipcore_dir/RAM_B/simulation/RAM_B_synth.vhd | 12 | 7,867 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: RAM_B_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY RAM_B_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE RAM_B_synth_ARCH OF RAM_B_synth IS
COMPONENT RAM_B_exdes
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 32,
READ_WIDTH => 32 )
PORT MAP (
CLK => CLKA,
RST => RSTA,
EN => CHECKER_EN_R,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RSTA='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECKER_EN AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
WEA => WEA,
CHECK_DATA => CHECKER_EN
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: RAM_B_exdes PORT MAP (
--Port A
WEA => WEA_R,
ADDRA => ADDRA_R,
DINA => DINA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
| gpl-3.0 | 3b67e6f08ea2f6f87a0a34cd2706ce19 | 0.563747 | 3.760516 | false | false | false | false |
SWORDfpga/ComputerOrganizationDesign | labs/lab08/lab08/ipcore_dir/ROM_D/example_design/ROM_D_exdes.vhd | 8 | 3,796 |
--------------------------------------------------------------------------------
--
-- Distributed Memory Generator Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
--
-- Description:
-- This is the actual DMG core wrapper.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity ROM_D_exdes is
PORT (
SPO : OUT STD_LOGIC_VECTOR(32-1 downto 0);
A : IN STD_LOGIC_VECTOR(10-1-(4*0*boolean'pos(10>4)) downto 0)
:= (OTHERS => '0')
);
end ROM_D_exdes;
architecture xilinx of ROM_D_exdes is
component ROM_D is
PORT (
SPO : OUT STD_LOGIC_VECTOR(32-1 downto 0);
A : IN STD_LOGIC_VECTOR(10-1-(4*0*boolean'pos(10>4)) downto 0)
:= (OTHERS => '0')
);
end component;
begin
dmg0 : ROM_D
port map (
SPO => SPO,
A => A
);
end xilinx;
| gpl-3.0 | 425abb5aa8023accdbd62e36f5185e7a | 0.586143 | 4.780856 | false | false | false | false |
Hyperion302/omega-cpu | TestBenches/MemoryController.vhdl | 1 | 4,158 | -- This file is part of the Omega CPU Core
-- Copyright 2015 - 2016 Joseph Shetaye
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as
-- published by the Free Software Foundation, either version 3 of the
-- License, or (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library IEEE;
use IEEE.std_logic_1164.all;
use work.constants.all;
use IEEE.Numeric_std.all;
entity MemoryController is
port (
CLK : in std_logic;
Address : in word;
Enable : in std_logic;
ToWrite : in word;
FromRead : out word;
Instruction : in word;
Reset : in std_logic;
Done : out std_logic);
end MemoryController;
architecture Behavioral of MemoryController is
constant LoadByteUnsigned : Operator := "000";
constant LoadByteSigned : Operator := "001";
constant LoadHalfWordUnsigned : Operator := "010";
constant LoadHalfWordSigned : Operator := "011";
constant LoadWord : Operator := "100";
constant StoreByte : Operator := "101";
constant StoreHalfWord : Operator := "110";
constant StoreWord : Operator := "111";
signal Memory : MemoryArray := (others => (others => '0'));
signal FromRead_S : Word := (others => '0');
begin -- Behavioral
FromRead <= FromRead_S;
process (Enable, Instruction, Address, Reset)
variable currentOperator : Operator;
begin -- process
if Reset = '1' then
Memory <= (others => (others => '0'));
elsif Enable = '1' then
currentOperator := GetOperator(Instruction);
case currentOperator is
when LoadByteUnsigned =>
FromRead_S <= "000000000000000000000000" & Memory(to_integer(unsigned(Address)));
Done <= '1';
when LoadByteSigned =>
FromRead_S <= std_logic_vector(resize(signed(Memory(to_integer(unsigned(Address)))), 32));
Done <= '1';
when LoadHalfWordUnsigned =>
FromRead_S <= "0000000000000000" & Memory(to_integer(unsigned(Address)) + 1) & Memory(to_integer(unsigned(Address)));
Done <= '1';
when LoadHalfWordSigned =>
FromRead_S <= std_logic_vector(
resize(
signed(
Memory(
to_integer(
unsigned(Address)
)
+ 1
)
) &
signed(
Memory(
to_integer(
unsigned(Address)
)
)
),
32
)
);
Done <= '1';
when LoadWord =>
FromRead_S <= Memory(to_integer(unsigned(Address)) + 3) & Memory(to_integer(unsigned(Address)) + 2) & Memory(to_integer(unsigned(Address)) + 1) & Memory(to_integer(unsigned(Address)));
Done <= '1';
when StoreByte =>
Memory(to_integer(unsigned(Address))) <= ToWrite(7 downto 0);
Done <= '1';
when StoreHalfWord =>
Memory(to_integer(unsigned(Address))) <= ToWrite(7 downto 0);
Memory(to_integer(unsigned(Address)) + 1) <= ToWrite(15 downto 8);
Done <= '1';
when StoreWord =>
Memory(to_integer(unsigned(Address))) <= ToWrite(7 downto 0);
Memory(to_integer(unsigned(Address)) + 1) <= ToWrite(15 downto 8);
Memory(to_integer(unsigned(Address)) + 2) <= ToWrite(23 downto 16);
Memory(to_integer(unsigned(Address)) + 3) <= ToWrite(31 downto 24);
Done <= '1';
when others => null;
end case;
else
Done <= '0';
end if;
end process;
end Behavioral;
| lgpl-3.0 | 2042dafd253e7ef51e9ce32dea0e00b9 | 0.572872 | 4.238532 | false | false | false | false |
dpolad/dlx | DLX_vhd/a.i.a.a.b-PISOR2.vhd | 2 | 650 | library ieee;
use ieee.std_logic_1164.all;
entity piso_r_2 is
generic(
N : natural := 8
);
port(
Clock : in std_logic;
ALOAD : in std_logic;
D : in std_logic_vector(N-1 downto 0);
SO : out std_logic_vector(N-1 downto 0)
);
end piso_r_2;
architecture archi of piso_r_2 is
signal tmp: std_logic_vector(N-1 downto 0);
begin
process (Clock)
begin
if (Clock'event and Clock='1') then
if (ALOAD='1') then
tmp <= D;
else
tmp <= tmp(N-3 downto 0) & "00";
end if;
end if;
end process;
SO <= tmp;
end archi;
| bsd-2-clause | aca0e2172240e299af4503fa21f22d4e | 0.516923 | 3.066038 | false | false | false | false |
rodrigofegui/UnB | 2017.1/Organização e Arquitetura de Computadores/Trabalhos/Projeto Final/Codificação/dec_mem.vhd | 2 | 2,000 | --Módulo intermediario para transferir o dados desejado para o módulo do display 7 segmentos
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity dec_mem is
generic(N: integer := 7; M: integer := 32);
port(
clk : in std_logic;
SW : in STD_LOGIC_VECTOR(N-1 downto 0);
HEX0 : out STD_LOGIC_VECTOR(6 downto 0);
HEX1 : out STD_LOGIC_VECTOR(6 downto 0);
HEX2 : out STD_LOGIC_VECTOR(6 downto 0);
HEX3 : out STD_LOGIC_VECTOR(6 downto 0);
HEX4 : out STD_LOGIC_VECTOR(6 downto 0);
HEX5 : out STD_LOGIC_VECTOR(6 downto 0);
HEX6 : out STD_LOGIC_VECTOR(6 downto 0);
HEX7 : out STD_LOGIC_VECTOR(6 downto 0)
);
end;
architecture dec_mem_arch of dec_mem is
-- signals
signal din : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal dout : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal we : STD_LOGIC := '0';
begin
we <= '0';
din <= (others => '0');
i1 : entity work.md
generic map(N => N, M => M)
port map (
adr => SW,
clk => clk,
din => din,
dout => dout,
we => we
);
i2 : entity work.seven_seg_decoder
port map (
data => dout(3 downto 0),
segments => HEX0
);
i3 : entity work.seven_seg_decoder
port map (
data => dout(7 downto 4),
segments => HEX1
);
i4 : entity work.seven_seg_decoder
port map (
data => dout(11 downto 8),
segments => HEX2
);
i5 : entity work.seven_seg_decoder
port map (
data => dout(15 downto 12),
segments => HEX3
);
i6 : entity work.seven_seg_decoder
port map (
data => dout(19 downto 16),
segments => HEX4
);
i7 : entity work.seven_seg_decoder
port map (
data => dout(23 downto 20),
segments => HEX5
);
i8 : entity work.seven_seg_decoder
port map (
data => dout(27 downto 24),
segments => HEX6
);
i9 : entity work.seven_seg_decoder
port map (
data => dout(31 downto 28),
segments => HEX7
);
end; | gpl-3.0 | 9d9395c82ab71b6911338cd517d3eb45 | 0.581582 | 2.878963 | false | false | false | false |
rodrigofegui/UnB | 2017.1/Organização e Arquitetura de Computadores/Trabalhos/Trabalho 3/Codificação/Banco Registradores/Registrador_Nbits.vhd | 1 | 1,336 | ----------------------------------------------------------------------------------
-- Responsáveis: Danillo Neves
-- Luiz Gustavo
-- Rodrigo Guimarães
-- Ultima mod.: 03/jun/2017
-- Nome do Módulo: Registrador
-- Descrição: Registrador com largura de palavra parametrizável
-- e com habilitação
----------------------------------------------------------------------------------
----------------------------------
-- Importando a biblioteca IEEE e especificando o uso dos estados lógicos
-- padrão
----------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
----------------------------------
-- Definiçao da entidade:
-- N - controle da palavra
-- clk - clock
-- D - dado de entrada
-- Q - saida
----------------------------------
entity Registrador_Nbits is
Generic (N : integer := 16);
Port (clk : in std_logic;
D : in std_logic_vector(N - 1 downto 0) := (others => '0');
Q : out std_logic_vector(N - 1 downto 0) := (others => '0'));
end Registrador_Nbits;
----------------------------------
-- Descritivo da operacionalidade da entidade
----------------------------------
architecture Comportamental of Registrador_Nbits is
begin
process (clk)
begin
if rising_edge(clk) then
Q <= D;
end if;
end process;
end architecture Comportamental;
| gpl-3.0 | c80911cce8da8a5df1eb52d7e9379f7c | 0.480755 | 3.742938 | false | false | false | false |
manosaloscables/vhdl | a-intro/ig2.vhd | 1 | 1,793 | -- ********************************
-- Comparador de igualdad de 2 bits
-- ********************************
library ieee;
use ieee.std_logic_1164.all;
-- std_logic_vector es un arreglo de elementos std_logic para señales de más
-- de un bit.
-- Convencionalmente se usa std_logic_vector(N downto 0) en vez de
-- std_logic_vector(0 to N) ya que el bit más significativo (MSB) está en la
-- posición más a la izquierda.
entity ig2 is
port(
a, b: in std_logic_vector(1 downto 0);
aigb: out std_logic
);
end ig2;
architecture arq_sdp of ig2 is
signal p1, p2, p3, p4: std_logic;
begin
-- Suma de productos de los términos
aigb <= p1 or p2 or p3 or p4;
-- Producto de los términos
p1 <= ((not a(1)) and (not b(1))) and
((not a(0)) and (not b(0)));
p2 <= ((not a(1)) and (not b(1))) and (a(0) and b(0));
p3 <= (a(1) and b(1)) and ((not a(0)) and (not b(0)));
p4 <= (a(1) and b(1)) and (a(0) and b(0));
end arq_sdp;
-- Una descripción estructural crea instancias de componentes simples para crear
-- un sistema más complejo.
-- La sintaxis para declarar instancias de componentes es:
-- nombre_unidad: entity nombre_lib.nombre_entidad(nombre_arq)
-- port map(
-- señal_instancia => señal_usada,
-- señal2_instancia => señal2_usada
-- );
architecture arq_est of ig2 is
signal igual1, igual2: std_logic;
begin
-- Instanciar dos comparadores de igualdad de 1-bit
unidad_ig_bit1: entity work.ig1(arq_sdp)
port map(
e1=>a(0),
e2=>b(0),
ig=>igual1
);
unidad_ig_bit2: entity work.ig1(arq_sdp)
port map(e1=>a(1), e2=>b(1), ig=>igual2);
-- a y b son iguales si los bits individuales son iguales
aigb <= igual1 and igual2;
end arq_est; | gpl-3.0 | a008a2fa3f7fbff668df0190c425d1a3 | 0.598089 | 2.945364 | false | false | false | false |
TimingKeepers/gen-ugr-cores | modules/wishbone/wb_i2c_arb/tb/testbench_i2c_arbiter.vhd | 1 | 2,333 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
library work;
use work.i2c_arb_pkg.all;
ENTITY testbench_i2c_arbiter IS
END testbench_i2c_arbiter;
ARCHITECTURE behavior OF testbench_i2c_arbiter IS
signal clk : std_logic := '0';
signal reset : std_logic := '1'; -- low-level active
constant clk_period : time := 16 ns; -- 62.5 MHz
constant c_num_i2c_inputs : integer := 2;
signal input_sda_i : std_logic_vector(c_num_i2c_inputs-1 downto 0);
signal input_sda_o : std_logic_vector(c_num_i2c_inputs-1 downto 0);
signal input_scl_i : std_logic_vector(c_num_i2c_inputs-1 downto 0);
signal input_scl_o : std_logic_vector(c_num_i2c_inputs-1 downto 0);
--signal output_sda_i : std_logic;
signal output_sda_o : std_logic;
--signal output_scl_i : std_logic;
signal output_scl_o : std_logic;
BEGIN
uut: wb_i2c_arbiter
generic map(
g_num_inputs => c_num_i2c_inputs
)
port map (
clk_i => clk,
rst_n_i => reset,
input_sda_i => input_sda_i,
input_sda_o => input_sda_o,
input_scl_i => input_scl_i,
input_scl_o => input_scl_o,
output_sda_i => output_sda_o,
output_sda_o => output_sda_o,
output_scl_i => output_scl_o,
output_scl_o => output_scl_o,
wb_adr_i => (others => '0'),
wb_dat_i => (others => '0'),
wb_dat_o => open,
wb_cyc_i => '0',
wb_sel_i => (others => '0'),
wb_stb_i => '0',
wb_we_i => '0',
wb_ack_o => open,
wb_stall_o => open
);
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
reset <='0'; -- reset!
wait for 3 ns;
reset <='1';
input_sda_i(0) <= '1';
input_scl_i(0) <= '1';
input_sda_i(1) <= '1';
input_scl_i(1) <= '1';
wait for 250 ns;
input_sda_i(0) <= '0';
wait for 250ns;
input_scl_i(0) <= '0';
wait for 250 ns;
input_scl_i(0) <= '1';
wait for 250 ns;
input_scl_i(0) <= '0';
wait for 250 ns;
input_scl_i(0) <= '1';
wait for 250 ns;
input_scl_i(0) <= '0';
wait for 250 ns;
input_scl_i(0) <= '1';
wait for 250 ns;
input_sda_i(0) <= '1';
wait;
end process;
END;
| gpl-2.0 | 9670c25698f0ed29f637cb57c8fb28c3 | 0.552936 | 2.657175 | false | false | false | false |
dpolad/dlx | DLX_vhd/a.a-CU_HW.vhd | 1 | 13,316 | -- *** a.a-CU-HW.vhd *** --
-- this block is describes the control unit.
-- This is a Hardwired control unit
-- Microcode LUT is declared directly here
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use work.myTypes.all;
entity dlx_cu is
generic (
MICROCODE_MEM_SIZE : integer := 64; -- Microcode Memory Size
FUNC_SIZE : integer := 11; -- Func Field Size for R-Type Ops
OP_CODE_SIZE : integer := 6; -- Op Code Size
IR_SIZE : integer := 32; -- Instruction Register Size
CW_SIZE : integer := 13); -- Control Word Size
port (
Clk : in std_logic; -- Clock
Rst : in std_logic; -- Reset: Active-High
IR_IN : in std_logic_vector(IR_SIZE - 1 downto 0); -- Instruction Register
stall_exe_i : in std_logic; -- Stall signal coming from EXE stage
mispredict_i : in std_logic;
D1_i : in std_logic_vector(4 downto 0); -- Destination register of exe stage
D2_i : in std_logic_vector(4 downto 0); -- Destination register of mem stage
S1_LATCH_EN : out std_logic; -- Latch enable of Fetch stage
S2_LATCH_EN : out std_logic; -- Latch enable of Dec stage
S3_LATCH_EN : out std_logic; -- Latch enable of Exe stage
S_MUX_PC_BUS : out std_logic_vector(1 downto 0); -- Control of mux to PC
S_EXT : out std_logic; -- Control of extender
S_EXT_SIGN : out std_logic; -- Control of extender sign
S_EQ_NEQ : out std_logic; -- Control of Comparator
S_MUX_DEST : out std_logic_vector(1 downto 0); -- Control of Destination register
S_MUX_LINK : out std_logic; -- Control of link mux
S_MUX_MEM : out std_logic; -- Control of mux to memory address
S_MEM_W_R : out std_logic; -- Control of mem W/R
S_MEM_EN : out std_logic; -- Control mem enable
S_RF_W_wb : out std_logic; -- Control WB enable
S_RF_W_mem : out std_logic; -- Current op in mem is going to write on wb?
S_RF_W_exe : out std_logic; -- Current op in exe is going to write on wb?
S_MUX_ALUIN : out std_logic; -- Control ALU input ( IMM or B )
stall_exe_o : out std_logic; -- Stall exe stage
stall_dec_o : out std_logic; -- Stall dec stage
stall_fetch_o : out std_logic; -- Stall fetch stage
stall_btb_o : out std_logic; -- Stall btb
was_branch_o : out std_logic; -- Op in decode is a branch or not?
was_jmp_o : out std_logic;
ALU_WORD_o : out std_logic_vector(12 downto 0); -- Opcode to ALU
ALU_OPCODE : out aluOp -- Opcode to ALU
);
end dlx_cu;
architecture dlx_cu_hw of dlx_cu is
-- ***************************
-- *** SIGNAL DECLARATIONS ***
-- ***************************
-- this is the microcode memory, it works as a LUT -> to decode an instruction it's opcode indexes this memory
signal IR_opcode : std_logic_vector(OP_CODE_SIZE -1 downto 0); -- OpCode part of IR
signal IR_func : std_logic_vector(FUNC_SIZE -1 downto 0); -- Func part of IR when Rtype
signal cw_d : std_logic_vector(CW_SIZE - 1 downto 0);
signal cw_from_mem : std_logic_vector(CW_SIZE - 1 downto 0); -- full control word read from cw_mem
-- control word is shifted to the correct stage
signal cw_e : std_logic_vector(CW_SIZE - 1 - 6 downto 0); -- second stage
signal cw_m : std_logic_vector(CW_SIZE - 1 - 9 downto 0); -- third stage
signal cw_w : std_logic_vector(CW_SIZE - 1 - 12 downto 0); -- fourth stage
signal aluOpcode_d : aluOp := NOP; -- ALUOP defined in package -- ! MIGHT NOT BE SYNTHESIZABLE
signal aluOpcode_e : aluOp := NOP; -- shifted ALUOP to feed execute stage -- ! MIGHT NOT BE SYNTHESIZABLE
signal S_MEM_LOAD : std_logic; -- is current op in mem stage a LOAD?
signal S_EXE_LOAD : std_logic; -- is current op in exe stage a LOAD?
-- stall signals from stall unit
signal stall_exe_o_TEMP : std_logic;
signal stall_dec_o_TEMP : std_logic;
signal stall_btb_o_TEMP : std_logic;
signal stall_fetch_o_TEMP : std_logic;
signal bubble_dec : std_logic; -- transform next op in decode into a NOP
signal next_bubble_dec : std_logic;
signal bubble_exe : std_logic; -- transform next op in exe into a NOP
signal next_bubble_exe : std_logic;
-- ********************************
-- *** COMPONENTS DECLARATION ***
-- ********************************
component cw_mem is
generic (
MICROCODE_MEM_SIZE : integer; -- Microcode Memory Size
OP_CODE_SIZE : integer; -- Op Code Size
CW_SIZE : integer -- Control Word Size
);
port (
OPCODE_IN : in std_logic_vector(OP_CODE_SIZE - 1 downto 0); -- Instruction Register
CW_OUT : out std_logic_vector(CW_SIZE - 1 downto 0)
);
end component;
component alu_ctrl is
port (
OP : in AluOp;
BOOTH_STALL : in std_logic;
ALU_WORD : out std_logic_vector(12 downto 0)
);
end component;
-- instantiation of stall_logic block
component stall_logic is
generic (
FUNC_SIZE : integer; -- Func Field Size for R-Type Ops
OP_CODE_SIZE : integer -- Op Code Size
);
port (
-- Instruction Register
OPCODE_i : in std_logic_vector(OP_CODE_SIZE-1 downto 0);
FUNC_i : in std_logic_vector(FUNC_SIZE-1 downto 0);
rA_i : in std_logic_vector(4 downto 0);
rB_i : in std_logic_vector(4 downto 0);
D1_i : in std_logic_vector(4 downto 0); -- taken from output of destination mux in EXE stage
D2_i : in std_logic_vector(4 downto 0);
S_mem_LOAD_i : in std_logic;
S_exe_LOAD_i : in std_logic;
S_exe_WRITE_i : in std_logic;
S_MUX_PC_BUS_i : in std_logic_vector(1 downto 0);
mispredict_i : in std_logic;
bubble_dec_o : out std_logic;
bubble_exe_o : out std_logic;
stall_exe_o : out std_logic;
stall_dec_o : out std_logic;
stall_btb_o : out std_logic;
stall_fetch_o : out std_logic
);
end component;
begin
-- ********************************
-- *** COMPONENTS INSTANTIATION ***
-- ********************************
STALL_L : stall_logic
generic map (
FUNC_SIZE => 11,
OP_CODE_SIZE => 6
)
port map(
-- Instruction Register
OPCODE_i => IR_opcode,
FUNC_i => IR_func,
rA_i => IR_IN(25 downto 21),
rB_i => IR_IN(20 downto 16),
D1_i => D1_i,
D2_i => D2_i,
S_mem_LOAD_i => S_MEM_LOAD,
S_exe_LOAD_i => S_EXE_LOAD,
S_exe_WRITE_i => cw_e(CW_SIZE - 13),
S_MUX_PC_BUS_i => cw_d(CW_SIZE - 1 downto CW_SIZE - 2),
mispredict_i => mispredict_i,
bubble_dec_o => next_bubble_dec,
bubble_exe_o => next_bubble_exe,
stall_exe_o => stall_exe_o_TEMP,
stall_dec_o => stall_dec_o_TEMP,
stall_btb_o => stall_btb_o_TEMP,
stall_fetch_o => stall_fetch_o_TEMP
);
CWM : cw_mem
generic map(
MICROCODE_MEM_SIZE => MICROCODE_MEM_SIZE,
OP_CODE_SIZE => OP_CODE_SIZE,
CW_SIZE => CW_SIZE
)
port map(
OPCODE_IN => IR_opcode,
CW_OUT => cw_from_mem
);
ALU_C: alu_ctrl
port map(
OP => aluopcode_d,
BOOTH_STALL => stall_dec_o_TEMP,
ALU_WORD => ALU_WORD_o
);
-- stall signals for each individual stage of the pipeline
-- an OR is needed cause a stall might come from ALU too
stall_exe_o <= stall_exe_i or stall_exe_o_TEMP;
stall_dec_o <= stall_exe_i or stall_dec_o_TEMP;
stall_fetch_o <= stall_exe_i or stall_fetch_o_TEMP;
stall_btb_o <= stall_exe_i or stall_btb_o_TEMP;
-- split function in OPCODE and FUNC
IR_opcode(5 downto 0) <= IR_IN(31 downto 26);
IR_func(10 downto 0) <= IR_IN(FUNC_SIZE - 1 downto 0);
-- control work is assigned to the word looked up in microcode memory
-- in case of bubble_dec, a NOP cw is fed instead
cw_d <= cw_from_mem when bubble_dec = '0' else "0000000000000";
-- *** ATM THE LATCH ENABLES ARE DOING NOTHING! EVERYTHING IS CONTROLLED BY STALL ***
S1_LATCH_EN <= '1';
S2_LATCH_EN <= '1';
S3_LATCH_EN <= '1';
-- DEC stage control signals
S_MUX_PC_BUS <= cw_d(CW_SIZE - 1 downto CW_SIZE - 2);
S_EXT <= cw_d(CW_SIZE - 3);
S_EXT_SIGN <= cw_d(CW_SIZE - 4);
S_EQ_NEQ <= cw_d(CW_SIZE - 5);
S_MUX_LINK <= cw_d(CW_SIZE - 6);
-- EXE stage control signals
S_MUX_ALUIN <= cw_e(CW_SIZE - 7);
S_MUX_DEST <= cw_e(CW_SIZE - 8 downto CW_SIZE - 9);
-- MEM stage control signals
S_MEM_EN <= cw_m(CW_SIZE - 10);
S_MEM_W_R <= cw_m(CW_SIZE - 11);
S_MUX_MEM <= cw_m(CW_SIZE - 12);
-- WB stage control signals
S_RF_W_wb <= cw_w(CW_SIZE - 13);
-- RF write signal is sent to other stages to compute hazards/forwarding
S_RF_W_mem <= cw_m(CW_SIZE - 13);
S_RF_W_exe <= cw_e(CW_SIZE - 13);
-- is the current op in mem stage a LOAD?
S_MEM_LOAD <= cw_m(CW_SIZE - 10) and (not cw_m(CW_SIZE - 11));
-- is the current op in exe stage a LOAD?
S_EXE_LOAD <= cw_e(CW_SIZE - 10) and (not cw_e(CW_SIZE - 11));
-- is current op in DEC stage a branch?
was_branch_o <= cw_d(CW_SIZE - 1) and cw_d(CW_SIZE - 2);
-- is current op in DEC stage an inconditional jump?
was_jmp_o <= cw_d(CW_SIZE - 1) xor cw_d(CW_SIZE - 2);
ALU_OPCODE <= aluOpcode_e;
-- ********************************
-- *** PROCESSES ***
-- ********************************
-- sequential process to manage and pipeline control words
CW_PIPE: process (Clk, Rst)
begin -- process Clk
if Rst = '1' then -- asynchronous reset (active high)
cw_e <= (others => '0');
cw_m <= (others => '0');
cw_w <= (others => '0');
aluOpcode_e <= NOP;
elsif Clk'event and Clk = '1' then -- rising clock edge
-- update of the bubbe signal
-- bubble means: cancel next operation and make it a nop ( used in case of misprediction or inconditional jumps)
bubble_dec <= next_bubble_dec;
bubble_exe <= next_bubble_exe;
-- EXE stalled
if stall_exe_i = '1' or stall_exe_o_TEMP = '1' then
cw_m <= "0000"; -- NOP instertion
cw_e <= cw_e;
aluOpcode_e <= aluOpcode_e;
-- DEC stalled
elsif stall_dec_o_TEMP = '1' then
cw_e <= "0000000"; -- NOP instertion
cw_m <= cw_e(CW_SIZE - 1 - 9 downto 0);
-- no stall
else
cw_e <= cw_d(CW_SIZE - 1 - 6 downto 0);
cw_m <= cw_e(CW_SIZE - 1 - 9 downto 0);
aluOpcode_e <= aluOpcode_d;
end if;
-- WB cannot be stalled
cw_w <= cw_m(CW_SIZE - 1 - 12 downto 0);
end if;
end process CW_PIPE;
-- combinatorial process to generate ALU OP CODES
ALU_OP_CODE_P : process (IR_opcode, IR_func)
begin
case conv_integer(unsigned(IR_opcode)) is
-- case of R type requires analysis of FUNC
when 0 =>
case conv_integer(unsigned(IR_func)) is
when 4 => aluOpcode_d <= SLLS; -- sll according to instruction set coding
when 6 => aluOpcode_d <= SRLS;
when 7 => aluOpcode_d <= SRAS;
when 32 => aluOpcode_d <= ADDS;
when 33 => aluOpcode_d <= ADDUS;
when 34 => aluOpcode_d <= SUBS;
when 35 => aluOpcode_d <= SUBUS;
when 36 => aluOpcode_d <= ANDS;
when 37 => aluOpcode_d <= ORS;
when 38 => aluOpcode_d <= XORS;
when 40 => aluOpcode_d <= SEQS;
when 41 => aluOpcode_d <= SNES;
when 42 => aluOpcode_d <= SLTS;
when 43 => aluOpcode_d <= SGTS;
when 44 => aluOpcode_d <= SLES;
when 45 => aluOpcode_d <= SGES;
when 48 => aluOpcode_d <= MOVI2SS;
when 49 => aluOpcode_d <= MOVS2IS;
when 50 => aluOpcode_d <= MOVFS;
when 51 => aluOpcode_d <= MOVDS;
when 52 => aluOpcode_d <= MOVFP2IS;
when 53 => aluOpcode_d <= MOVI2FP;
when 54 => aluOpcode_d <= MOVI2TS;
when 55 => aluOpcode_d <= MOVT2IS;
when 58 => aluOpcode_d <= SLTUS;
when 59 => aluOpcode_d <= SGTUS;
when 60 => aluOpcode_d <= SLEUS;
when 61 => aluOpcode_d <= SGEUS;
when others => aluOpcode_d <= NOP; -- might not be synthesizable
end case;
-- type F instruction case -- MULT only at the moment
when 1 =>
case conv_integer(unsigned(IR_func)) is
when 22 => aluOpcode_d <= MULTU;
when 14 => aluOpcode_d <= MULTS;
when others => aluOpcode_d <= NOP; -- might not be synthesizable
end case;
-- I-TYPE instructions
when 2 => aluOpcode_d <= NOP; -- j
when 3 => aluOpcode_d <= NOP; -- jal
when 4 => aluOpcode_d <= NOP; -- beqz
when 5 => aluOpcode_d <= NOP; -- bnez
when 8 => aluOpcode_d <= ADDS; -- addi
when 9 => aluOpcode_d <= ADDUS; -- addui
when 10 => aluOpcode_d <= SUBS; -- subi
when 11 => aluOpcode_d <= SUBUS; -- subui
when 12 => aluOpcode_d <= ANDS; -- andi
when 13 => aluOpcode_d <= ORS; -- ori
when 14 => aluOpcode_d <= XORS; -- xori
when 18 => aluOpcode_d <= NOP; -- jr
when 19 => aluOpcode_d <= NOP; -- jalr
when 20 => aluOpcode_d <= SLLS; -- slli
when 21 => aluOpcode_d <= NOP; -- nop
when 22 => aluOpcode_d <= SRLS; -- srli
when 23 => aluOpcode_d <= SRAS; -- srai
when 24 => aluOpcode_d <= SEQS; -- seqi
when 25 => aluOpcode_d <= SNES; -- snei
when 26 => aluOpcode_d <= SLTS; -- slti
when 27 => aluOpcode_d <= SGTS; -- sgti
when 28 => aluOpcode_d <= SLES; -- slei
when 29 => aluOpcode_d <= SGES; -- sgei
when 35 => aluOpcode_d <= ADDS; -- lw
when 43 => aluOpcode_d <= ADDS; -- sw
when 58 => aluOpcode_d <= SLTUS; -- sltui
when 59 => aluOpcode_d <= SGTUS; -- sgtui
when 60 => aluOpcode_d <= SLEUS; -- sleui
when 61 => aluOpcode_d <= SGEUS; -- sgeui
when others => aluOpcode_d <= NOP; -- might not be synthesizable
end case;
end process ALU_OP_CODE_P;
end dlx_cu_hw;
| bsd-2-clause | a05263f7fe576de37254555d2d8fbcc3 | 0.598753 | 2.817605 | false | false | false | false |
dpolad/dlx | DLX_vhd/007-PISO.vhd | 2 | 625 | library ieee;
use ieee.std_logic_1164.all;
entity shift is
generic(
N : natural := 8
);
port(
Clock : in std_logic;
ALOAD : in std_logic;
D : in std_logic_vector(N-1 downto 0);
SO : out std_logic
);
end shift;
architecture archi of shift is
signal tmp: std_logic_vector(N-1 downto 0);
begin
process (Clock)
begin
if (Clock'event and Clock='1') then
if (ALOAD='1') then
tmp <= D;
else
tmp <= '0'&tmp(N-1 downto 1) ;
end if;
end if;
end process;
SO <= tmp(0);
end archi;
| bsd-2-clause | 0fc04a5fff3e85d07775b598d4f0994d | 0.5088 | 3.188776 | false | false | false | false |
Hyperion302/omega-cpu | TestBenches/CPU_TB.vhdl | 1 | 8,362 | -- This file is part of the Omega CPU Core
-- Copyright 2015 - 2016 Joseph Shetaye
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as
-- published by the Free Software Foundation, either version 3 of the
-- License, or (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library IEEE;
use IEEE.std_logic_1164.all;
use work.Constants.all;
use IEEE.Numeric_std.all;
use std.textio.all;
use work.ghdl_env.all;
entity CPU_TB is
end CPU_TB;
architecture Behavioral of CPU_TB is
component MemoryController is
port (
CLK : in std_logic;
Address : in word;
ToWrite : in word;
FromRead : out word;
Instruction : in word;
Enable : in std_logic;
Reset : in std_logic;
Done : out std_logic);
end component MemoryController;
component PortController is
port (
CLK : in std_logic;
XMit : in Word;
Recv : out Word;
SerialIn : in std_logic;
SerialOut : out std_logic;
instruction : in Word;
CPUReady : in std_logic;
CPUSending: in std_logic;
PortReady: out std_logic;
PortSending: out std_logic;
Done: out std_logic);
end component PortController;
component Control is
port(
CLK : in std_logic;
MemControllerDone : in std_logic;
MemControllerFromRead : in Word;
MemControllerToWrite : out Word;
MemControllerADDR : out Word;
MemControllerEnable : out std_logic;
PortXmit : out Word;
PortRecv : in Word;
PortInstruction : out Word;
PortCPUReady : out std_logic;
PortCPUSending : out std_logic;
PortReady : in std_logic;
PortDone : in std_logic;
PortSending : out std_logic;
IRQ : in std_logic_vector(23 downto 0);
Instr : out Word;
RST : in std_logic);
end component Control;
signal MemControllerDone : std_logic := '0';
signal MemControllerFromRead : Word := (others => '0');
signal MemControllerToWrite : Word := (others => '0');
signal MemControllerADDR : Word := (others => '0');
signal MemControllerEnable : std_logic := '0';
signal Instr : Word := (others => '0');
signal MemoryPassthrough : std_logic := '0';
signal CLK : std_logic := '0';
signal RST : std_logic := '0';
--port
signal PortXmit_s : Word;
signal PortRecv_s : Word;
signal PortInstruction_s : Word;
signal PortCPUReady_s : std_logic;
signal PortCPUSending_s : std_logic;
signal PortReady_s : std_logic;
signal PortDone_s : std_logic;
signal PortSending_s : std_logic;
--mem
signal MemControllerDone_M : std_logic;
signal MemControllerFromRead_M : Word;
signal MemControllerToWrite_M : Word;
signal MemControllerADDR_M : Word;
signal MemControllerReset_M : std_logic := '0';
signal Instr_M : Word;
signal MemControllerEnable_M : std_logic;
signal MemControllerEnable_C : std_logic;
signal MemControllerDone_C : std_logic;
signal MemControllerFromRead_C : Word;
signal MemControllerToWrite_C : Word;
signal MemControllerADDR_C : Word;
signal Instr_C : Word;
begin
MemoryControllerControl : MemoryController port map (
Address => MemControllerADDR_M,
ToWrite => MemControllerToWrite_M,
FromRead => MemControllerFromRead_M,
Enable => MemControllerEnable_M,
Instruction => Instr_M,
Reset => MemControllerReset_M,
Done => MemControllerDone_M,
CLK => CLK);
PortControl : PortController port map (
CLK => CLK,
XMit => PortXMit_s,
Recv => PortRecv_s,
instruction => Instr_C,
CPUReady => PortCPUReady_s,
CPUSending => PortCPUSending_s,
SerialIn => '0',
PortReady => PortReady_s,
Done => PortDone_s,
PortSending => PortSending_s);
ControlTB : Control port map (
CLK => CLK,
MemControllerDone => MemControllerDone_C,
MemControllerFromRead => MemControllerFromRead_C,
MemControllerToWrite => MemControllerToWrite_C,
MemControllerADDR => MemControllerADDR_C,
MemControllerEnable => MemControllerEnable_C,
PortXmit => PortXmit_s,
PortRecv => PortRecv_s,
PortInstruction => PortInstruction_s,
PortCPUReady => PortCPUReady_s,
PortCPUSending => PortCPUSending_s,
PortReady => PortReady_s,
PortDone => PortDone_s,
PortSending => PortSending_s,
IRQ => (others => '0'),
RST => RST,
Instr => Instr_C);
file_io:
process is
file programInput : text is in getenv("PROGRAM");
variable in_line : line;
variable out_line : line;
variable in_vector : bit_vector(31 downto 0) := (others => '0');
variable outputI : integer := 0;
variable Counter : integer := 0;
variable NextWord : Word := (others => '0');
begin -- Behiavioral
while not endfile(programInput) loop
readline(programInput, in_line);
if in_line'length = 32 then
read(in_line, in_vector);
NextWord := to_stdlogicvector(in_vector);
MemControllerToWrite <= std_logic_vector(resize(unsigned(NextWord(7 downto 0)), 32));
Instr <= OpcodeMemory & StoreByte & "00000" & "000000000000000000000";
MemControllerADDR <= std_logic_vector(to_unsigned(Counter, 32));
wait for 1 ns;
MemControllerEnable <= '1';
wait for 1 ns;
MemControllerEnable <= '0';
wait for 1 ns;
MemControllerToWrite <= std_logic_vector(resize(unsigned(NextWord(15 downto 8)), 32));
Instr <= OpcodeMemory & StoreByte & "00000" & "000000000000000000000";
MemControllerADDR <= std_logic_vector(to_unsigned(Counter + 1, 32));
wait for 1 ns;
MemControllerEnable <= '1';
wait for 1 ns;
MemControllerEnable <= '0';
wait for 1 ns;
MemControllerToWrite <= std_logic_vector(resize(unsigned(NextWord(23 downto 16)), 32));
Instr <= OpcodeMemory & StoreByte & "00000" & "000000000000000000000";
MemControllerADDR <= std_logic_vector(to_unsigned(Counter + 2, 32));
wait for 1 ns;
MemControllerEnable <= '1';
wait for 1 ns;
MemControllerEnable <= '0';
wait for 1 ns;
MemControllerToWrite <= std_logic_vector(resize(unsigned(NextWord(31 downto 24)), 32));
Instr <= OpcodeMemory & StoreByte & "00000" & "000000000000000000000";
MemControllerADDR <= std_logic_vector(to_unsigned(Counter + 3, 32));
wait for 1 ns;
MemControllerEnable <= '1';
wait for 1 ns;
MemControllerEnable <= '0';
Counter := Counter + 4;
else
writeline(output,in_line);
end if;
end loop;
wait for 2 ns;
MemoryPassthrough <= '1';
RST <= '1';
wait for 2 ns;
RST <= '0';
loop
wait for 100 ns;
CLK <= '1';
wait for 100 ns;
CLK <= '0';
end loop; -- N
wait;
end process;
Passthrough: process (MemControllerDone,MemControllerFromRead,MemControllerToWrite,MemControllerADDR,Instr,MemControllerEnable_C,MemControllerEnable,MemoryPassthrough,MemControllerADDR_C,Instr_C,MemControllerToWrite_C,MemControllerDone_M,MemControllerFromRead_M) is
begin
if MemoryPassthrough = '1' then
MemControllerADDR_M <= MemControllerADDR_C;
Instr_M <= Instr_C;
MemControllerToWrite_M <= MemControllerToWrite_C;
MemControllerDone_C <= MemControllerDone_M;
MemControllerFromRead_C <= MemControllerFromRead_M;
MemControllerEnable_M <= MemControllerEnable_C;
else
MemControllerADDR_M <= MemControllerADDR;
Instr_M <= Instr;
MemControllerEnable_M <= MemControllerEnable;
MemControllerToWrite_M <= MemControllerToWrite;
MemControllerDone <= MemControllerDone_M;
MemControllerFromRead <= MemControllerFromRead_M;
MemControllerDone_C <= '0';
MemControllerFromRead_C <= (others => '0');
end if;
end process;
end Behavioral;
| lgpl-3.0 | 28204d8412f5812d701ff6186c1a91a0 | 0.649605 | 3.827002 | false | false | false | false |
dpolad/dlx | DLX_synth/a.l-MEMREGS.vhd | 1 | 873 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--use work.myTypes.all;
entity mem_regs is
generic (
SIZE : integer := 32
);
port (
W_i : in std_logic_vector(SIZE - 1 downto 0);
D3_i : in std_logic_vector(4 downto 0);
W_o : out std_logic_vector(SIZE - 1 downto 0);
D3_o : out std_logic_vector(4 downto 0);
clk : in std_logic;
rst : in std_logic
);
end mem_regs;
architecture Struct of mem_regs is
component ff32
generic(
SIZE : integer
);
port(
D : in std_logic_vector(SIZE - 1 downto 0);
Q : out std_logic_vector(SIZE - 1 downto 0);
clk : in std_logic;
rst : in std_logic
);
end component;
begin
W: ff32 generic map(
SIZE => 32
)
port map(
D => W_i,
Q => W_o,
clk => clk,
rst => rst
);
D3: ff32 generic map(
SIZE => 5
)
port map(
D => D3_i,
Q => D3_o,
clk => clk,
rst => rst
);
end Struct;
| bsd-2-clause | 2980335c35981b56d1b811fedc4fa61c | 0.607102 | 2.244216 | false | false | false | false |
jmarcelof/Phoenix | NoC/Phoenix_buffer.vhd | 2 | 40,019 | ---------------------------------------------------------------------------------------
-- BUFFER
-- --------------
-- RX ->| |-> H
-- DATA_IN ->| |<- ACK_H
-- CLOCK_RX ->| |
-- CREDIT_O <-| |-> DATA_AV
-- | |-> DATA
-- | |<- DATA_ACK
-- | |
-- | |
-- | |=> SENDER
-- | | all ports
-- --------------
--
-- Quando o algoritmo de chaveamento resulta no bloqueio dos flits de um pacote,
-- ocorre uma perda de desempenho em toda rede de interconexao, porque os flits sao
-- bloqueados nao somente na chave atual, mas em todas as intermediarias.
-- Para diminuir a perda de desempenho foi adicionada uma fila em cada porta de
-- entrada da chave, reduzindo as chaves afetadas com o bloqueio dos flits de um
-- pacote. E importante observar que quanto maior for o tamanho da fila menor sera o
-- numero de chaves intermediarias afetadas.
-- As filas usadas contem dimensao e largura de flit parametrizaveis, para altera-las
-- modifique as constantes TAM_BUFFER e TAM_FLIT no arquivo "Phoenix_packet.vhd".
-- As filas funcionam como FIFOs circulares. Cada fila possui dois ponteiros: first e
-- last. First aponta para a posicao da fila onde se encontra o flit a ser consumido.
-- Last aponta para a posicao onde deve ser inserido o proximo flit.
---------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
use STD.textio.all;
use work.HammingPack16.all;
use work.NoCPackage.all;
-- interface da Phoenix_buffer
entity Phoenix_buffer is
generic(address : regflit := (others=>'0');
bufLocation: integer := 0);
port(
clock: in std_logic;
reset: in std_logic;
clock_rx: in std_logic;
rx: in std_logic;
data_in: in unsigned((TAM_FLIT-1) downto 0);
credit_o: out std_logic;
h: out std_logic; -- requisicao de chaveamento
c_ctrl: out std_logic; -- indica se foi lido ou criado de um pacote de controle pelo buffer
c_buffCtrlOut:out buffControl; -- linha da tabela de roteamento lida do pacote de controle que sera escrita na tabela de roteamento
c_buffCtrlFalha:out row_FaultTable_Ports; -- tabela de falhas lida do pacote de controle que solicitou escrever/atualizar a tabela
c_codigoCtrl: out regFlit; -- tipo do pacote de controle (leitura do Code). Terceiro flit do pacote de controle
c_chipETable: out std_logic; -- chip enable da tabela de roteamento
c_ceTF_out: out std_logic; -- ce (chip enable) para escrever/atualizar a tabela de falhas
c_error_find: in RouterControl; -- indica se terminou de achar uma porta de saida para o pacote conforme a tabela de roteamento
c_error_dir : in regNport; -- indica qual destino/porta de saida o pacote sera encaminhado
c_tabelaFalhas :in row_FaultTable_Ports; -- tabela de falhas atualizada/final
ack_h: in std_logic; -- resposta da requisicao de chaveamento
data_av: out std_logic;
data: out regflit;
data_ack: in std_logic;
sender: out std_logic;
c_strLinkTst: out std_logic; -- (start link test) indica que houve um pacote de controle do tipo TEST_LINKS para testar os links. Comentario antigo: send to router (testa as falhas)
c_strLinkTstOthers: in std_logic; -- indica se algum vizinho pediu para testar o link
c_strLinkTstNeighbor: in std_logic; -- indica se o vizinho pediu para testar o link
c_strLinkTstAll: in std_logic; -- se algum buffer fez o pedido de teste de links
c_stpLinkTst: in std_logic; -- (stop link test) indica se algum vizinho pediu para testar o link. Gerado pelo FaultDetection
retransmission_in: in std_logic;
retransmission_out: out std_logic;
statusHamming: in reg3);
end Phoenix_buffer;
architecture Phoenix_buffer of Phoenix_buffer is
type fila_out is (S_INIT, S_PAYLOAD, S_SENDHEADER, S_HEADER, S_END, S_END2,C_PAYLOAD,C_SIZE);
signal EA : fila_out;
signal buf: buff := (others=>(others=>'0'));
signal first,last: unsigned((TAM_POINTER-1) downto 0) := (others=>'0');
signal tem_espaco: std_logic := '0';
signal counter_flit: unsigned((TAM_FLIT-1) downto 0) := (others=>'0');
signal eh_controle : std_logic := '0';
signal buffCtrl : buffControl := (others=>(others=>'0')); -- XY | XY | DIR
signal codigoControl : unsigned((TAM_FLIT-1) downto 0):= (others=>'0');
signal buffCtrlFalha : row_FaultTable_Ports := (others=>(others=>'0'));
signal ceTF_out : std_logic := '0';
signal c_error : std_logic := '0'; -- '0' sem erro para o destino, '1' com erro para o destino
signal c_direcao: regNport :=(others=>'0'); -- registrador com a direcao que esta mandando o pacote
signal c_createmessage : std_logic := '0'; -- sinal usado para criar um pacote de controle com a tabela de falhas
signal c_Buffer : regflit := (others=>'0'); -- dado de saida gerado ao criar um pacote de controle (pacote de resposta eh criado quando eh pedido leitura da tabela de falhas)
signal c_strLinkTstLocal : std_logic := '0'; -- sinal do pedido de inicio de teste de links
signal old_tabelaFalhas : regNport :=(others=>'0'); -- antiga tabela e falhas com 1 bit para cada porta. '0' indica sem falha, '1' indica com falha
signal last_retransmission: regflit := (others=>'0');
signal counter_flit_up: unsigned((TAM_FLIT-1) downto 0) := (others=>'0');
signal last_count_rx: regflit := (others=>'0');
signal retransmission_o: std_logic := '0';
signal pkt_size: unsigned((TAM_FLIT-1) downto 0) := (others=>'0');
begin
retransmission_out <= retransmission_o;
old_tabelaFalhas(LOCAL) <= '0';
old_tabelaFalhas(EAST) <= c_tabelafalhas(EAST)(3*COUNTERS_SIZE+1);
old_tabelaFalhas(WEST) <= c_tabelafalhas(WEST)(3*COUNTERS_SIZE+1);
old_tabelaFalhas(NORTH) <= c_tabelafalhas(NORTH)(3*COUNTERS_SIZE+1);
old_tabelaFalhas(SOUTH) <= c_tabelafalhas(SOUTH)(3*COUNTERS_SIZE+1);
-- sinal indica se tem falha no link destino
c_error <= '1' when unsigned(c_direcao and old_tabelafalhas) /= 0 else '0';
-------------------------------------------------------------------------------------------
-- ENTRADA DE DADOS NA FILA
-------------------------------------------------------------------------------------------
-- Verifica se existe espaco na fila para armazenamento de flits.
-- Se existe espaco na fila o sinal tem_espaco_na_fila eh igual a 1.
process(reset, clock_rx)
begin
if reset = '1' then
tem_espaco <= '1';
elsif clock_rx'event and clock_rx = '1' then
if not ((first = x"0" and last = TAM_BUFFER - 1) or (first = last + 1)) then
tem_espaco <= '1';
else
tem_espaco <= '0';
end if;
end if;
end process;
credit_o <= tem_espaco;
-- O ponteiro last eh inicializado com o valor zero quando o reset eh ativado.
-- Quando o sinal rx eh ativado indicando que existe um flit na porta de entrada. Eh
-- verificado se existe espaco na fila para armazena-lo. Se existir espaco na fila o
-- flit recebido eh armazenado na posicao apontada pelo ponteiro last e o mesmo eh
-- incrementado. Quando last atingir o tamanho da fila, ele recebe zero.
process(reset, clock_rx)
variable count: integer;
variable pkt_received: std_logic := '0';
file my_output : TEXT;
variable fstatus: file_open_status := STATUS_ERROR;
variable my_output_line : LINE;
variable count_retx: integer := 0;
variable total_count_retx: unsigned((TAM_FLIT-1) downto 0);
begin
if reset = '1' then
last <= (others=>'0');
count := 0;
last_count_rx <= (others=>'0');
pkt_size <= (others=>'0');
pkt_received := '1';
elsif clock_rx'event and clock_rx = '0' then
if (rx = '0' and pkt_received='1') then
count := 0;
last_count_rx <= (others=>'1');
pkt_received := '0';
pkt_size <= (others=>'0');
count_retx := 0;
end if;
-- se tenho espaco e se tem alguem enviando, armazena, mas
-- nao queremos armazenar os flits recebidos durante o teste de link, entao
-- se meu roteador esta testando os links ou se o link ligado a este buffer esta sendo testando pelo vizinho, irei ignorar os flits durante o teste
-- o buffer local que eh conectado ao link local (assumido que nunca falha) nunca sera testado
if tem_espaco = '1' and rx = '1' and ((c_strLinkTstAll = '0' and c_strLinkTstNeighbor='0') or bufLocation = LOCAL) then
-- se nao deu erro, esta tudo normal. Posso armazenar o flit no buffer e incrementar o ponteiro
if (statusHamming /= ED) then
retransmission_o <= '0';
-- modifica o ultimo flit do pacote para armazenar o numero de retransmissoes
if (count = pkt_size+1 and pkt_size > 0) then
total_count_retx := data_in;
total_count_retx := total_count_retx + count_retx;
buf(to_integer(last)) <= std_logic_vector(total_count_retx);
else
buf(to_integer(last)) <= std_logic_vector(data_in); -- armazena o flit
end if;
if (count = 1) then
pkt_size <= data_in;
end if;
--incrementa o last
if last = TAM_BUFFER - 1 then
last <= (others=>'0');
else
last <= last + 1;
end if;
count := count + 1;
-- detectado erro e nao corrigido. Posso tentar mais uma vez pedindo retransmissao...
else
retransmission_o <= '1';
count_retx := count_retx + 1;
last_count_rx <= std_logic_vector(to_unsigned(count,TAM_FLIT));
end if;
if (count = pkt_size+2 and pkt_size > 0) then
pkt_received := '1';
if (count_retx /= 0) then
if(fstatus /= OPEN_OK) then
file_open(fstatus, my_output,"retransmission_00"&to_hstring(address)&".txt",WRITE_MODE);
end if;
write(my_output_line, "Packet in port "&PORT_NAME(bufLocation)&" received "&integer'image(count_retx)&" flits with double error "&time'image(now));
writeline(my_output, my_output_line);
end if;
else
pkt_received := '0';
end if;
end if;
end if;
end process;
-------------------------------------------------------------------------------------------
-- SAIDA DE DADOS NA FILA
-------------------------------------------------------------------------------------------
-- disponibiliza o dado para transmissao. Se nao estiver criando um pacote de controle, envia normalmente o dado do buffer, caso contrario envia dado criado (c_buffer)
data <= buf(to_integer(first)) when c_createmessage ='0' else c_Buffer;
-- Quando sinal reset eh ativado a maquina de estados avanca para o estado S_INIT.
-- No estado S_INIT os sinais counter_flit (contador de flits do corpo do pacote), h (que
-- indica requisicao de chaveamento) e data_av (que indica a existencia de flit a ser
-- transmitido) sao inicializados com zero. Se existir algum flit na fila, ou seja, os
-- ponteiros first e last apontarem para posicoes diferentes, a maquina de estados avanca
-- para o estado S_HEADER.
-- No estado S_HEADER eh requisitado o chaveamento (h='1'), porque o flit na posicao
-- apontada pelo ponteiro first, quando a maquina encontra-se nesse estado, eh sempre o
-- header do pacote. A maquina permanece neste estado ate que receba a confirmacao do
-- chaveamento (ack_h='1') entao o sinal h recebe o valor zero e a maquina avanca para
-- S_SENDHEADER.
-- Em S_SENDHEADER eh indicado que existe um flit a ser transmitido (data_av='1'). A maquina de
-- estados permanece em S_SENDHEADER ate receber a confirmacao da transmissao (data_ack='1')
-- entao o ponteiro first aponta para o segundo flit do pacote e avanca para o estado S_PAYLOAD.
-- No estado S_PAYLOAD eh indicado que existe um flit a ser transmitido (data_av='1') quando
-- eh recebida a confirmacao da transmissao (data_ack='1') eh verificado qual o valor do sinal
-- counter_flit. Se counter_flit eh igual a um, a maquina avanca para o estado S_INIT. Caso
-- counter_flit seja igual a zero, o sinal counter_flit eh inicializado com o valor do flit, pois
-- este ao numero de flits do corpo do pacote. Caso counter_flit seja diferente de um e de zero
-- o mesmo eh decrementado e a maquina de estados permanece em S_PAYLOAD enviando o proximo flit
-- do pacote.
process(reset, clock)
variable indexFlitCtrl: integer :=0;
variable varControlCom: integer :=1; -- variavel de comando, para fazer as iteracoes
begin
if reset = '1' then
counter_flit <= (others=>'0');
counter_flit_up <= (others=>'0');
h <= '0';
data_av <= '0';
sender <= '0';
first <= (others=>'0');
eh_controle <= '0';
c_chipETable <= '0';
EA <= S_INIT;
elsif clock'event and clock = '1' then
case EA is
when S_INIT =>
c_chipETable <= '0'; -- desabilita escrita na tabela de roteamento
counter_flit <= (others=>'0');
counter_flit_up <= (others=>'0');
data_av <= '0';
eh_controle <= '0';
last_retransmission <= (others=>'0');
-- se existe dados no buffer a serem transmitidos (por causa dos ponteiros first e last diferentes) OU se devo criar um pacote de controle com a tabela de falhas
if first /= last or c_createmessage = '1' then
-- se o primeiro flit do pacote a ser transmitido possui o bit indicando que eh um pacote de controle E se nesse primeiro flit possui o endereco do roteador em que o buffer se encontra
-- OU se devo criar um pacote de controle com a tabela de falhas (este pacote eh criado se for pedido a leitura da tabela de falhas)
if((buf(to_integer(first))(TAM_FLIT-1)='1') and (buf(to_integer(first))((TAM_FLIT-2) downto 0)=address((TAM_FLIT-2) downto 0))) or c_createmessage = '1' then -- PACOTE DE CONTROLE
-- se preciso criar um pacote com a tabela de falhas. Comentario antigo: o pacote de controle pare este roteador
if c_createmessage = '1' then
-- se ultimo pacote de controle recebido foi de leitura da tabela de falhas
if codigoControl = c_RD_FAULT_TAB_STEP1 then
c_Buffer <= '1' & address((TAM_FLIT-2) downto 0); -- entao crio o primeiro flit do pacote que vai conter a tabela de falhas
h <= '1'; -- requisicao de chaveamento (chavear os dados de entrada para a porta de saida atraves da crossbar)
EA <= S_HEADER; -- maquina de estados avanca para o estado S_HEADER
eh_controle <= '1'; -- indica que o pacote lido/criado eh de controle
c_direcao <= "10000"; --direcao para a saida Local
end if;
-- nao irei criar pacote de controle com a tabela de falhas, irei apenas transmitir o pacote do buffer
else
-- incrementa ponteiro first (ponteiro usado para envio)
-- nao preciso tratar erro detectado aqui, pq em ED o flit eh igual a zero, logo nao sera pacote de controle
if first = TAM_BUFFER - 1 then
first <= (others=>'0');
else
first <= first + 1;
end if;
EA <= C_SIZE; -- maquina de estados avanca para o estado S_SIZE (estado onde eh lido o tamanho do pacote)
eh_controle <= '1'; -- indica que o pacote lido/criado eh de controle
c_direcao <= "10000"; -- direcao para o a saida Local
end if;
-- tenho dados para enviar e nao sao de controle (apenas pacote de dados)
else
h <= '1'; -- requisicao de chaveamento (chavear os dados de entrada para a porta de saida atraves da crossbar)
EA <= S_HEADER; -- maquina de estados avanca para o estado S_HEADER
end if;
-- entao nao tenho dados no buffer para enviar nem preciso criar um pacote de controle
else
h <= '0'; -- nao pede/solicita chaveamento pq nao preciso enviar nada
end if;
when S_HEADER =>
-- se terminou de achar uma porta de saida para o pacote conforme a tabela de roteamento
if (c_error_find = validRegion) then
c_direcao <= c_error_dir; -- direcao/porta de saida da tabela de roteamento
end if;
-- atendido/confirmado a requisicao de chaveamento OU se link destino tiver falhar
if ack_h = '1' or c_error = '1' then
EA <= S_SENDHEADER;
h <= '0'; -- nao preciso mais solicitar o chaveamento pq ele foi ja foi atendido :)
data_av <= '1'; -- data available (usado para indicar que exite flit a ser transmitido)
sender <= '1'; -- usado para indicar que esta transmitindo (por este sinal sabemos quando termina a transmissao e a porta destino desocupa)
end if;
when S_SENDHEADER =>
-- se recebeu confirmacao de dado recebido OU o link destino esta com falha
if data_ack = '1' or c_error = '1' then
-- incrementa pointeiro first (usado para transmitir flit) e sinaliza que tem dado disponivel
if c_createmessage = '0' then
-- se receptor nao pediu retransmissao, continua enviando
if (retransmission_in='0') then
EA <= S_PAYLOAD;
if first = TAM_BUFFER - 1 then
first <= (others=>'0');
if last /= 0 then data_av <= '1';
else data_av <= '0';
end if;
else
first <= first + 1;
if first + 1 /= last then data_av <= '1';
else data_av <= '0';
end if;
end if;
-- solicitou reenvio do pacote, logo ponteiro nao sera incrementado e dado sera enviado novamente
else
last_retransmission <= (0=>'1', others=>'0'); -- 1
--assert last_retransmission /= 1 report "sender detectou que nao conseguiu transmitir flit correto. Pacote descartado. Flit "&integer'image(to_integer(last_retransmission));
end if;
-- irei criar um pacote de controle com a tabela de falhas
else
-- se ultimo pacote de controle recebido foi pedido de leitura da tabela de falhas
if codigoControl = c_RD_FAULT_TAB_STEP1 then
counter_flit <= x"000A"; -- 10 flits de payload (code + origem + tabela)
c_Buffer <= x"000A"; -- segundo flit do pacote de controle criado (tamanho de pacote)
EA <= C_PAYLOAD;
indexFlitCtrl := 0;
varControlCom := 10;
end if;
end if;
end if;
when S_PAYLOAD =>
-- se tiver que retransmitir, nao incrementa ponteiro first
if (( data_ack = '1' or c_error = '1') and retransmission_in = '1') then
if (counter_flit = 0) then
last_retransmission <= (1=>'1', others=>'0'); -- 2
--assert last_retransmission /= 2 report "sender detectou que nao conseguiu transmitir flit correto. Pacote descartado. Flit "&integer'image(to_integer(last_retransmission));
else
last_retransmission <= std_logic_vector(counter_flit_up);
--assert last_retransmission /= counter_flit_up report "sender detectou que nao conseguiu transmitir flit correto. Pacote descartado. Flit "&integer'image(to_integer(last_retransmission));
end if;
-- se nao eh o ultimo flit do pacote E se foi confirmado que foi recebido com sucesso o dado transmitido OU o link destino esta com falha. Comentario antigo: confirmacao do envio de um dado que nao eh o tail
elsif counter_flit /= x"1" and ( data_ack = '1' or c_error = '1') then
-- se counter_flit eh zero indica que terei que receber o size do payload
if counter_flit = x"0" then
counter_flit <= unsigned(buf(to_integer(first)));
counter_flit_up <= (1=>'1', others=>'0'); -- 2
else
counter_flit <= counter_flit - 1;
counter_flit_up <= counter_flit_up + 1;
end if;
-- incrementa pointeiro first (usado para transmitir flit) e sinaliza que tem dado disponivel
if first = TAM_BUFFER - 1 then
first <= (others=>'0');
if last /= 0 then
data_av <= '1'; -- (data available)
else
data_av <= '0';
end if;
else
first <= first + 1;
if first + 1 /= last then
data_av <= '1';
else
data_av <= '0';
end if;
end if;
-- se eh o ultimo flit do pacote E se foi confirmado que foi recebido com sucesso o dado transmitido OU o link destino esta com falha. Comentario antigo: confirmacao do envio do tail
elsif counter_flit = x"1" and (data_ack = '1' or c_error = '1') then
-- Incrementa pointeiro de envio. Comentario antigo: retira um dado do buffer
if first = TAM_BUFFER - 1 then
first <= (others=>'0');
else
first <= first + 1;
end if;
data_av <= '0'; -- como o ultimo flit sera enviado, nao tem mais dados disponiveis
sender <= '0'; -- como o ultimo flit sera enviado, nao preciso sinalizar que estou enviando dados
EA <= S_END; -- -- como o ultimo flit sera enviado, posso ir para o estado S_END
-- se tem dado a ser enviado, sinaliza
elsif first /= last then
data_av <= '1'; -- (data available)
end if;
when C_SIZE =>
-- detectou dado na fila (tem dados a serem enviados no buffer) e nao pediu retransmissao
if (first /= last and retransmission_o='0') then
counter_flit <= unsigned(buf(to_integer(first))); -- leitura do segundo flit (tamanho do pacote)
-- incrementa o pointeiro first (pointeiro usado para envio)
if first = TAM_BUFFER - 1 then
first <= (others=>'0');
else
first <= first + 1;
end if;
EA <= C_PAYLOAD;
indexFlitCtrl := 0; -- coloca o indice do flit de controle igual 0 (esse indice eh usado para percorrer os flits de payload de controle). O indice igual a 0 representa o terceito flit do pacote e nele havera o Code (codigo que indica o tipo do pacote de controle)
varControlCom := 1; -- numero de flits no payload usados para processar o pacote de controle
end if;
when C_PAYLOAD =>
c_chipETable <= '0'; -- desabilita escrita na tabela de roteamento
if (first /= last) and indexFlitCtrl /= varControlCom and c_createmessage = '0' and retransmission_o='0' then
if first = TAM_BUFFER - 1 then
first <= (others=>'0');
else
first <= first + 1;
end if;
end if;
-- indice igual a zero, ou seja, primeiro flit do payload do pacote (onde possui o codigo do pacote de controle)
if (indexFlitCtrl = 0 and retransmission_o='0') then
codigoControl <= unsigned(buf(to_integer(first))); -- leitura do tipo do pacote de controle (leitura do Code)
indexFlitCtrl := indexFlitCtrl + 1; -- incrementa o indice do payload que sera lido
counter_flit <= counter_flit - 1; -- decrementa o numero de flits que faltam a ser lidos/processados do pacote
-- define qual o tamanho da variavel de comando (tamanho do payload).
-- Pode ser entendido como o numero de flits no payload usados para processar o pacote de controle
if c_createmessage = '0' then
if to_integer(unsigned(buf(to_integer(first)))) = c_WR_ROUT_TAB then
varControlCom := 5;
elsif to_integer(unsigned(buf(to_integer(first)))) = c_WR_FAULT_TAB then
varControlCom := 9; -- code + tabela
elsif to_integer(unsigned(buf(to_integer(first)))) = c_RD_FAULT_TAB_STEP1 then
varControlCom := 1;
elsif to_integer(unsigned(buf(to_integer(first)))) = c_TEST_LINKS then
varControlCom := 1;
end if;
-- se c_createmessage='1', logo tenho que criar um pacote com a tabela de falhas para o OsPhoenix
else
-- se ultimo pacote de controle recebido foi pedido de leitura da tabela de falhas
if codigoControl = c_RD_FAULT_TAB_STEP1 then
varControlCom := 10; -- code + origem + tabela
codigoControl <= to_unsigned(c_RD_FAULT_TAB_STEP2, TAM_FLIT); -- atualiza codigo com c_RD_FAULT_TAB_STEP2
c_Buffer <= x"0004"; -- terceiro flit do pacote de controle criado que contem o tipo do pacote (code/codigo)
end if;
end if;
-- escrita de linha na tabela de roteamento. Comentario antigo: codigo para atualizar tabela de roteamento.
-- a linha do pacote de roteamento eh divida em 3 flits: o primeiro flit tem o XY do ponto inferior, o segundo flit tem o XY do ponto superior,
-- o terceiro flit contem os 5 bits que indica a direcao/porta de saida dos pacotes conforme a regiao
elsif (codigoControl = c_WR_ROUT_TAB and retransmission_o='0') then
-- terminou de processar todos os flits do pacote de controle
if indexFlitCtrl = 5 then
counter_flit <= counter_flit - 1;
if counter_flit = x"1" then
EA <= S_END;
end if;
c_chipETable <= '1'; -- habilita escrita na tabela de roteamento
indexFlitCtrl := 1;
else
buffCtrl(indexFlitCtrl-1) <= buf(to_integer(first)); -- vai armazenando os dados lido do pacote de controle (o pacote tera uma linha da tabela de roteamento)
if (first /= last) then
if indexFlitCtrl /= 4 then
counter_flit <= counter_flit - 1;
end if;
indexFlitCtrl := indexFlitCtrl + 1;
end if;
c_chipETable <= '0';
end if;
-- escrita na tabela de falhas (irei ler a tabela recebido no pacote de controle). Comentario antigo: codigo para atualizar tabela de portas com falhas
elsif (codigoControl = c_WR_FAULT_TAB and retransmission_o='0') then
case (indexFlitCtrl) is
when 1 => buffCtrlFalha(EAST)((3*COUNTERS_SIZE+1) downto 3*COUNTERS_SIZE) <= buf(to_integer(first))((METADEFLIT+1) downto METADEFLIT); -- leitura dos 2 bits que indicam falha que sera armazenado/atualizado na tabela de falhas
buffCtrlFalha(EAST)((3*COUNTERS_SIZE-1) downto 2*COUNTERS_SIZE) <= buf(to_integer(first))(COUNTERS_SIZE-1 downto 0); -- leitura do contador N
when 2 => buffCtrlFalha(EAST)((2*COUNTERS_SIZE-1) downto COUNTERS_SIZE) <= buf(to_integer(first))((METADEFLIT+COUNTERS_SIZE-1) downto METADEFLIT); -- leitura do contador M
buffCtrlFalha(EAST)((COUNTERS_SIZE-1) downto 0) <= buf(to_integer(first))(COUNTERS_SIZE-1 downto 0); -- leitura do contador P
when 3 => buffCtrlFalha(WEST)((3*COUNTERS_SIZE+1) downto 3*COUNTERS_SIZE) <= buf(to_integer(first))((METADEFLIT+1) downto METADEFLIT); -- leitura dos 2 bits que indicam falha que sera armazenado/atualizado na tabela de falhas
buffCtrlFalha(WEST)((3*COUNTERS_SIZE-1) downto 2*COUNTERS_SIZE) <= buf(to_integer(first))(COUNTERS_SIZE-1 downto 0); -- leitura do contador N
when 4 => buffCtrlFalha(WEST)((2*COUNTERS_SIZE-1) downto COUNTERS_SIZE) <= buf(to_integer(first))((METADEFLIT+COUNTERS_SIZE-1) downto METADEFLIT); -- leitura do contador M
buffCtrlFalha(WEST)((COUNTERS_SIZE-1) downto 0) <= buf(to_integer(first))(COUNTERS_SIZE-1 downto 0); -- leitura do contador P
when 5 => buffCtrlFalha(NORTH)((3*COUNTERS_SIZE+1) downto 3*COUNTERS_SIZE) <= buf(to_integer(first))((METADEFLIT+1) downto METADEFLIT); -- leitura dos 2 bits que indicam falha que sera armazenado/atualizado na tabela de falhas
buffCtrlFalha(NORTH)((3*COUNTERS_SIZE-1) downto 2*COUNTERS_SIZE) <= buf(to_integer(first))(COUNTERS_SIZE-1 downto 0); -- leitura do contador N
when 6 => buffCtrlFalha(NORTH)((2*COUNTERS_SIZE-1) downto COUNTERS_SIZE) <= buf(to_integer(first))((METADEFLIT+COUNTERS_SIZE-1) downto METADEFLIT); -- leitura do contador M
buffCtrlFalha(NORTH)((COUNTERS_SIZE-1) downto 0) <= buf(to_integer(first))(COUNTERS_SIZE-1 downto 0); -- leitura do contador P
when 7 => buffCtrlFalha(SOUTH)((3*COUNTERS_SIZE+1) downto 3*COUNTERS_SIZE) <= buf(to_integer(first))((METADEFLIT+1) downto METADEFLIT); -- leitura dos 2 bits que indicam falha que sera armazenado/atualizado na tabela de falhas
buffCtrlFalha(SOUTH)((3*COUNTERS_SIZE-1) downto 2*COUNTERS_SIZE) <= buf(to_integer(first))(COUNTERS_SIZE-1 downto 0); -- leitura do contador N
when 8 => buffCtrlFalha(SOUTH)((2*COUNTERS_SIZE-1) downto COUNTERS_SIZE) <= buf(to_integer(first))((METADEFLIT+COUNTERS_SIZE-1) downto METADEFLIT); -- leitura do contador M
buffCtrlFalha(SOUTH)((COUNTERS_SIZE-1) downto 0) <= buf(to_integer(first))(COUNTERS_SIZE-1 downto 0); -- leitura do contador P
when others => null;
end case;
if (first /= last) then
indexFlitCtrl := indexFlitCtrl + 1;
counter_flit <= counter_flit - 1;
end if;
-- ultimo flit?
if counter_flit = 0 then
ceTF_out <= '1'; -- habilita ce para escrever/atualizar a tabela de falhas
EA <= S_END;
end if;
-- pedido de leitura da tabela de falhas
elsif codigoControl = c_RD_FAULT_TAB_STEP1 then
--codigo requerindo a tabela de falhas
counter_flit <= counter_flit - 1;
EA <= S_INIT;
-- sinal usado para criar um pacote de controle com a tabela de falhas. Comentario antigo: envia msg para tabela
c_createmessage <= '1';
-- resposta da leitura da tabela de falhas
elsif codigoControl = c_RD_FAULT_TAB_STEP2 then
-- code complement. Comentario antigo: codigo para enviar a msg de falhas para o PE
if (data_ack = '1') then
case (indexFlitCtrl) is
when 1 => c_Buffer <= address; -- neste quarto flit havera o endereco do roteador
when 2 => c_Buffer((TAM_FLIT-1) downto METADEFLIT) <= std_logic_vector(to_unsigned(0,METADEFLIT-2)) & c_TabelaFalhas(EAST)((3*COUNTERS_SIZE+1) downto 3*COUNTERS_SIZE);
c_Buffer((METADEFLIT-1) downto 0) <= std_logic_vector(to_unsigned(0,METADEFLIT-COUNTERS_SIZE)) & c_TabelaFalhas(EAST)((3*COUNTERS_SIZE-1) downto 2*COUNTERS_SIZE);
when 3 => c_Buffer((TAM_FLIT-1) downto METADEFLIT) <= std_logic_vector(to_unsigned(0,METADEFLIT-COUNTERS_SIZE)) & c_TabelaFalhas(EAST)((2*COUNTERS_SIZE-1) downto COUNTERS_SIZE);
c_Buffer((METADEFLIT-1) downto 0) <= std_logic_vector(to_unsigned(0,METADEFLIT-COUNTERS_SIZE)) & c_TabelaFalhas(EAST)((COUNTERS_SIZE-1) downto 0);
when 4 => c_Buffer((TAM_FLIT-1) downto METADEFLIT) <= std_logic_vector(to_unsigned(0,METADEFLIT-2)) & c_TabelaFalhas(WEST)((3*COUNTERS_SIZE+1) downto 3*COUNTERS_SIZE);
c_Buffer((METADEFLIT-1) downto 0) <= std_logic_vector(to_unsigned(0,METADEFLIT-COUNTERS_SIZE)) & c_TabelaFalhas(WEST)((3*COUNTERS_SIZE-1) downto 2*COUNTERS_SIZE);
when 5 => c_Buffer((TAM_FLIT-1) downto METADEFLIT) <= std_logic_vector(to_unsigned(0,METADEFLIT-COUNTERS_SIZE)) & c_TabelaFalhas(WEST)((2*COUNTERS_SIZE-1) downto COUNTERS_SIZE);
c_Buffer((METADEFLIT-1) downto 0) <= std_logic_vector(to_unsigned(0,METADEFLIT-COUNTERS_SIZE)) & c_TabelaFalhas(WEST)((COUNTERS_SIZE-1) downto 0);
when 6 => c_Buffer((TAM_FLIT-1) downto METADEFLIT) <= std_logic_vector(to_unsigned(0,METADEFLIT-2)) & c_TabelaFalhas(NORTH)((3*COUNTERS_SIZE+1) downto 3*COUNTERS_SIZE);
c_Buffer((METADEFLIT-1) downto 0) <= std_logic_vector(to_unsigned(0,METADEFLIT-COUNTERS_SIZE)) & c_TabelaFalhas(NORTH)((3*COUNTERS_SIZE-1) downto 2*COUNTERS_SIZE);
when 7 => c_Buffer((TAM_FLIT-1) downto METADEFLIT) <= std_logic_vector(to_unsigned(0,METADEFLIT-COUNTERS_SIZE)) & c_TabelaFalhas(NORTH)((2*COUNTERS_SIZE-1) downto COUNTERS_SIZE);
c_Buffer((METADEFLIT-1) downto 0) <= std_logic_vector(to_unsigned(0,METADEFLIT-COUNTERS_SIZE)) & c_TabelaFalhas(NORTH)((COUNTERS_SIZE-1) downto 0);
when 8 => c_Buffer((TAM_FLIT-1) downto METADEFLIT) <= std_logic_vector(to_unsigned(0,METADEFLIT-2)) & c_TabelaFalhas(SOUTH)((3*COUNTERS_SIZE+1) downto 3*COUNTERS_SIZE);
c_Buffer((METADEFLIT-1) downto 0) <= std_logic_vector(to_unsigned(0,METADEFLIT-COUNTERS_SIZE)) & c_TabelaFalhas(SOUTH)((3*COUNTERS_SIZE-1) downto 2*COUNTERS_SIZE);
when 9 => c_Buffer((TAM_FLIT-1) downto METADEFLIT) <= std_logic_vector(to_unsigned(0,METADEFLIT-COUNTERS_SIZE)) & c_TabelaFalhas(SOUTH)((2*COUNTERS_SIZE-1) downto COUNTERS_SIZE);
c_Buffer((METADEFLIT-1) downto 0) <= std_logic_vector(to_unsigned(0,METADEFLIT-COUNTERS_SIZE)) & c_TabelaFalhas(SOUTH)((COUNTERS_SIZE-1) downto 0);
when others => null;
end case;
counter_flit <= counter_flit - 1; -- decrementa o numero de payloads que faltam processar
indexFlitCtrl := indexFlitCtrl + 1; -- incrementa o indice do payload
end if;
-- se enviou todos os flits
if counter_flit = x"0" then
c_createmessage <= '0'; -- nao preciso mais sinalizar para criar um pacote, pq ele ja foi criado e enviado :)
data_av <= '0'; -- ja enviei o pacote, entao nao tem mais dados disponiveis
sender <= '0'; -- ja enviei o pacote, nao preciso sinalizar que estou enviando
EA <= S_END;
-- se tem dado a ser enviado, sinalizado que existe dados disponiveis
else
data_av <= '1'; -- (data available)
end if;
-- se o pacote gerado pelo OsPhoenix eh um pacote de controle do tipo TEST_LINKS.
elsif codigoControl = c_TEST_LINKS then
-- pede para verificar os links aos vizinhos caso nenhum vizinho tenha pedido o teste de link. Comentario antigo: codigo para testar falhas e gravar na tabela de falhas do switchControl
-- SE nenhum vizinho pediu o teste de link ENTAO...
if c_strLinkTstOthers = '0' then
c_strLinkTstLocal <= '1'; -- pede para iniciar o teste de links
end if;
-- se terminou o teste de links
if c_stpLinkTst = '1' then
c_strLinkTstLocal <= '0'; -- nao preciso mais pedir para iniciar o teste de link pq ele ja acabou :)
EA <= S_END;
end if;
end if;
when S_END =>
c_chipETable <= '0';
ceTF_out <= '0';
eh_controle <= '0';
data_av <= '0';
c_direcao <= (others=>'0');
indexFlitCtrl := 0;
EA <= S_END2;
when S_END2 => -- estado necessario para permitir a liberacao da porta antes da solicitacao de novo envio
data_av <= '0';
EA <= S_INIT;
end case;
end if;
end process;
------------New Hardware------------
c_ctrl <= eh_controle;
c_buffCtrlOut <= buffCtrl;
c_codigoCtrl <= std_logic_vector(codigoControl);
c_buffCtrlFalha <= buffCtrlFalha;
c_ceTF_out <= ceTF_out;
c_strLinkTst <= c_strLinkTstLocal;
end Phoenix_buffer; | lgpl-3.0 | 69d7faa01fcd659db6babc88bc6169b7 | 0.550189 | 4.485429 | false | false | false | false |
jobisoft/jTDC | modules/VFB6/disc16/Controller_25AA02E48.vhd | 1 | 8,378 | -------------------------------------------------------------------------
---- ----
---- Company : ELB-Elektroniklaboratorien Bonn UG ----
---- (haftungsbeschränkt) ----
---- ----
-------------------------------------------------------------------------
---- ----
---- Copyright (C) 2015 ELB ----
---- ----
---- This program is free software; you can redistribute it and/or ----
---- modify it under the terms of the GNU General Public License as ----
---- published by the Free Software Foundation; either version 3 of ----
---- the License, or (at your option) any later version. ----
---- ----
---- This program is distributed in the hope that it will be useful, ----
---- but WITHOUT ANY WARRANTY; without even the implied warranty of ----
---- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ----
---- GNU General Public License for more details. ----
---- ----
---- You should have received a copy of the GNU General Public ----
---- License along with this program; if not, see ----
---- <http://www.gnu.org/licenses>. ----
---- ----
-------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Controller_25AA02E48 is
Port ( CLK : in STD_LOGIC;
CLKDivH,CLKDivL : in std_logic_vector(3 downto 0);
ReadID : in STD_LOGIC;
ID : out STD_LOGIC_VECTOR (47 downto 0);
SCLK, CS, MOSI : out STD_LOGIC;
MISO : in STD_LOGIC);
end Controller_25AA02E48;
architecture Behavioral of Controller_25AA02E48 is
--Signal BusyRegister : STD_LOGIC :='0';
--Signal DataRegister : STD_LOGIC_VECTOR (11 downto 0) :=(others=>'0');
--signal AddressRegister : STD_LOGIC_VECTOR (4 downto 0) :=(others=>'0');
Signal TransferRegister : STD_LOGIC_VECTOR (6 downto 0) :=(others=>'0'); -- Data and Address to be transfered. Only 15 bit because MSB is applied immidately at WE='1'
Signal ReadRegister : STD_LOGIC_VECTOR(7 downto 0):=X"EE";
Signal SCLKRegister, MOSIRegister : STD_LOGIC :='0'; -- DAC draws less current if pins are low -> when idle pull low.
Signal CSRegister : STD_LOGIC :='0'; -- Chip select high when idle, low for initial read cycle
Signal ClockDivCounter,Final_counter : unsigned (3 downto 0):=to_unsigned(0,4);-- How many CLK-Cycles has already been waited (update SCLK, when counter reached value set in interface), second: counter to release CS
Signal BitCounter : unsigned (4 downto 0):=to_unsigned(0,5); -- How many bits have been transfered?
Signal NCRESCLK : STD_LOGIC; -- Next Clockcycle has Rising Edge on SCLK
Signal NCFESCLK : STD_LOGIC; -- Next Clockcycle has Falling Edge on SCLK
type controller_states is (waiting, -- idle state, accept command
write_instruction_byte, -- write command to chip
write_address, -- write read address
read1, -- read three bytes
read2,
read3,
read4,
read5,
read6,
final_wait_to_CS
);
signal cont_state : controller_states := write_instruction_byte;
Signal ByteToSend : STD_LOGIC_VECTOR (7 downto 0) :=X"03";
Signal ReceivedID : STD_LOGIC_VECTOR (47 downto 0):=X"DEADDEADBEEF";
Signal WE: STD_LOGIC:='1';
Signal BusyRegister : STD_LOGIC:='0';
begin
SCLK<=SCLKRegister;
MOSI<=MOSIRegister;
CS<=CSRegister;
--Busy<=BusyRegister;
ID<=ReceivedID;
GenerateSCLK : Process (CLK) is
begin
if rising_edge(CLK) then
if BusyRegister='0' then -- reset case
ClockDivCounter<=to_unsigned(0,4);
SCLKRegister<='0';
else
ClockDivCounter<=ClockDivCounter+1;
if SCLKRegister='1' then
if CLKDivH = STD_LOGIC_VECTOR (ClockDivCounter) then
SCLKRegister<='0';
ClockDivCounter<=to_unsigned(0,4);
end if;
else
if CLKDivL = STD_LOGIC_VECTOR (ClockDivCounter) then
SCLKRegister<='1';
ClockDivCounter<=to_unsigned(0,4);
end if;
end if;
end if;
end if;
end process;
Process (CLKDivL, ClockDivCounter, SCLKRegister) is begin
if CLKDivL = STD_LOGIC_VECTOR (ClockDivCounter) AND SCLKRegister ='0' then
NCRESCLK<='1';
else
NCRESCLK<='0';
end if;
end Process;
Process (CLKDivH, ClockDivCounter, SCLKRegister) is begin
if CLKDivH = STD_LOGIC_VECTOR (ClockDivCounter) AND SCLKRegister ='1' then
NCFESCLK<='1';
else
NCFESCLK<='0';
end if;
end Process;
Process (CLK) is begin
if rising_edge(CLK) then
if BusyRegister='0' then
if WE='1' then
TransferRegister <= ByteToSend(6 downto 0);
BusyRegister<='1';
--CSRegister<='0';
MOSIRegister <=ByteToSend(7);
end if;
else
if NCFESCLK ='1' then -- on falling edge, bits are transfered-> increase number of transferred bits
BitCounter<=BitCounter+1;
TransferRegister (6 downto 1) <=TransferRegister (5 downto 0);
MOSIRegister <=TransferRegister(6);
ReadRegister(7 downto 1) <=ReadRegister(6 downto 0);
ReadRegister(0)<=MISO;
end if;
if NCRESCLK ='1' then -- on rising edge, change data (should work best because t_setup = t_hold = 2,5 ns)
end if;
if BitCounter = to_unsigned(7,5) AND NCFESCLK ='1' then -- when 16 bits have been transfered, wait until clock to cipselect time is fullfilled (min 10 ns,
--CSRegister<='1';
BusyRegister<='0';
BitCounter <=to_unsigned(0,5);
end if;
end if;
end if;
end process;
Process (CLK) is begin
if rising_Edge(CLK) then
case cont_state is
when waiting =>
WE<='0';
CSRegister<='1';
if ReadID='1' then
CSRegister<='0';
cont_state <= write_instruction_byte;
ByteToSend <= X"03";
WE<='1';
end if;
when write_instruction_byte =>
WE<='0';
if BusyRegister='0' and WE='0' then
cont_state <= write_address;
ByteToSend <= X"FA";
WE<='1';
end if;
when write_address =>
WE<='0';
if BusyRegister='0' and WE='0' then
cont_state <= read1;
ByteToSend <= X"00";
WE<='1';
end if;
when read1 =>
WE<='0';
if BusyRegister='0' and WE='0' then
cont_state <= read2;
ByteToSend <= X"00";
WE<='1';
ReceivedID(47 downto 40)<=ReadRegister;
end if;
when read2 =>
WE<='0';
if BusyRegister='0' and WE='0' then
cont_state <= read3;
--ByteToSend <= X"00";
ReceivedID(39 downto 32)<=ReadRegister;
WE<='1';
end if;
when read3 =>
WE<='0';
if BusyRegister='0' and WE='0' then
cont_state <= read4;
--ByteToSend <= X"00";
ReceivedID(31 downto 24)<=ReadRegister;
WE<='1';
end if;
when read4 =>
WE<='0';
if BusyRegister='0' and WE='0' then
cont_state <= read5;
--ByteToSend <= X"00";
ReceivedID(23 downto 16)<=ReadRegister;
WE<='1';
end if;
when read5 =>
WE<='0';
if BusyRegister='0' and WE='0' then
cont_state <= read6;
--ByteToSend <= X"00";
ReceivedID(15 downto 8)<=ReadRegister;
WE<='1';
end if;
when read6 =>
WE<='0';
if BusyRegister='0' and WE='0' then
cont_state <= final_wait_to_CS;
--ByteToSend <= X"00";
ReceivedID(7 downto 0)<=ReadRegister;
Final_counter<=to_unsigned(0,4);
end if;
when final_wait_to_CS=>
Final_counter<=Final_counter+1;
if CLKDivL = STD_LOGIC_VECTOR(Final_counter) then
cont_state <= waiting;
end if;
when others=> null;
end case;
end if;
end process;
end Behavioral;
| gpl-3.0 | 3812b6992ce558789cb06f8112e5bb77 | 0.563806 | 3.733066 | false | false | false | false |
Hyperion302/omega-cpu | Hardware/Omega/ipcore_dir/UARTClockManager/simulation/UARTClockManager_tb.vhd | 1 | 6,499 | -- file: UARTClockManager_tb.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard demonstration testbench
------------------------------------------------------------------------------
-- This demonstration testbench instantiates the example design for the
-- clocking wizard. Input clocks are toggled, which cause the clocking
-- network to lock and the counters to increment.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
library work;
use work.all;
entity UARTClockManager_tb is
end UARTClockManager_tb;
architecture test of UARTClockManager_tb is
-- Clock to Q delay of 100 ps
constant TCQ : time := 100 ps;
-- timescale is 1ps
constant ONE_NS : time := 1 ns;
-- how many cycles to run
constant COUNT_PHASE : integer := 1024 + 1;
-- we'll be using the period in many locations
constant PER1 : time := 31.250 ns;
-- Declare the input clock signals
signal CLK_IN1 : std_logic := '1';
-- The high bits of the sampling counters
signal COUNT : std_logic_vector(2 downto 1);
-- Status and control signals
signal RESET : std_logic := '0';
signal COUNTER_RESET : std_logic := '0';
-- signal defined to stop mti simulation without severity failure in the report
signal end_of_sim : std_logic := '0';
signal CLK_OUT : std_logic_vector(2 downto 1);
--Freq Check using the M & D values setting and actual Frequency generated
component UARTClockManager_exdes
generic (
TCQ : in time := 100 ps);
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
CLK_OUT : out std_logic_vector(2 downto 1) ;
-- High bits of counters driven by clocks
COUNT : out std_logic_vector(2 downto 1);
-- Status and control signals
RESET : in std_logic
);
end component;
begin
-- Input clock generation
--------------------------------------
process begin
CLK_IN1 <= not CLK_IN1; wait for (PER1/2);
end process;
-- Test sequence
process
procedure simtimeprint is
variable outline : line;
begin
write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
write(outline, NOW/PER1);
write(outline, string'(" ns"));
writeline(output,outline);
end simtimeprint;
procedure simfreqprint (period : time; clk_num : integer) is
variable outputline : LINE;
variable str1 : string(1 to 16);
variable str2 : integer;
variable str3 : string(1 to 2);
variable str4 : integer;
variable str5 : string(1 to 4);
begin
str1 := "Freq of CLK_OUT(";
str2 := clk_num;
str3 := ") ";
str4 := 1000000 ps/period ;
str5 := " MHz" ;
write(outputline, str1 );
write(outputline, str2);
write(outputline, str3);
write(outputline, str4);
write(outputline, str5);
writeline(output, outputline);
end simfreqprint;
begin
RESET <= '1';
wait for (PER1*6);
RESET <= '0';
-- can't probe into hierarchy, wait "some time" for lock
wait for (PER1*2500);
COUNTER_RESET <= '1';
wait for (PER1*20);
COUNTER_RESET <= '0';
wait for (PER1*COUNT_PHASE);
simtimeprint;
end_of_sim <= '1';
wait for 1 ps;
report "Simulation Stopped." severity failure;
wait;
end process;
-- Instantiation of the example design containing the clock
-- network and sampling counters
-----------------------------------------------------------
dut : UARTClockManager_exdes
generic map (
TCQ => TCQ)
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
-- Reset for logic in example design
COUNTER_RESET => COUNTER_RESET,
CLK_OUT => CLK_OUT,
-- High bits of the counters
COUNT => COUNT,
-- Status and control signals
RESET => RESET);
-- Freq Check
end test;
| lgpl-3.0 | 79d38384ddc3931889a30a6a2bdf9bbd | 0.636098 | 4.29544 | false | false | false | false |
MAV-RT-testbed/MAV-testbed | Syma_Flight_Final/Syma_Flight_Final.srcs/sources_1/ipshared/xilinx.com/axi_quad_spi_v3_2/c64e9f22/hdl/src/vhdl/comp_defs.vhd | 1 | 17,824 | --
---- comp_defs - package
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
---- Filename: comp_defs.vhd
---- Version: v3.0
-- Description: Component declarations for all black box netlists generated by
-- running COREGEN when XST elaborated the client core
----
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synopsys translate_off
--library XilinxCoreLib;
--use XilinxCoreLib.all;
-- synopsys translate_on
--library dist_mem_gen_v6_3;
-- use dist_mem_gen_v6_3.all;
--
--library dist_mem_gen_v6_4;
-- use dist_mem_gen_v6_4.all;
library dist_mem_gen_v8_0;
use dist_mem_gen_v8_0.all;
package comp_defs is
--
-- -- component declaration
-- component dist_mem_gen_v6_3
-- -------------------
-- generic(
-- c_has_clk : integer := 1;
-- c_read_mif : integer := 0;
-- c_has_qspo : integer := 0;
-- c_addr_width : integer := 8;
-- c_width : integer := 15;
-- c_family : string := "virtex7"; -- "virtex6";
-- c_sync_enable : integer := 1;
-- c_depth : integer := 256;
-- c_has_qspo_srst : integer := 1;
-- c_mem_init_file : string := "null.mif";
-- c_default_data : string := "0";
-- ------------------------
-- c_has_qdpo_clk : integer := 0;
-- c_has_qdpo_ce : integer := 0;
-- c_parser_type : integer := 1;
-- c_has_d : integer := 0;
-- c_has_spo : integer := 0;
-- c_reg_a_d_inputs : integer := 0;
-- c_has_we : integer := 0;
-- c_pipeline_stages : integer := 0;
-- c_has_qdpo_rst : integer := 0;
-- c_reg_dpra_input : integer := 0;
-- c_qualify_we : integer := 0;
-- c_has_qdpo_srst : integer := 0;
-- c_has_dpra : integer := 0;
-- c_qce_joined : integer := 0;
-- c_mem_type : integer := 0;
-- c_has_i_ce : integer := 0;
-- c_has_dpo : integer := 0;
-- c_has_spra : integer := 0;
-- c_has_qspo_ce : integer := 0;
-- c_has_qspo_rst : integer := 0;
-- c_has_qdpo : integer := 0
-- -------------------------
-- );
-- port(
-- a : in std_logic_vector(c_addr_width-1-(4*c_has_spra*boolean'pos(c_addr_width > 4)) downto 0) := (others => '0');
-- d : in std_logic_vector(c_width-1 downto 0) := (others => '0');
-- dpra : in std_logic_vector(c_addr_width-1 downto 0) := (others => '0');
-- spra : in std_logic_vector(c_addr_width-1 downto 0) := (others => '0');
-- clk : in std_logic := '0';
-- we : in std_logic := '0';
-- i_ce : in std_logic := '1';
-- qspo_ce : in std_logic := '1';
-- qdpo_ce : in std_logic := '1';
-- qdpo_clk : in std_logic := '0';
-- qspo_rst : in std_logic := '0';
-- qdpo_rst : in std_logic := '0';
-- qspo_srst : in std_logic := '0';
-- qdpo_srst : in std_logic := '0';
-- spo : out std_logic_vector(c_width-1 downto 0);
-- dpo : out std_logic_vector(c_width-1 downto 0);
-- qspo : out std_logic_vector(c_width-1 downto 0);
-- qdpo : out std_logic_vector(c_width-1 downto 0)
-- );
-- end component;
--
-- -- The following tells XST that dist_mem_gen_v6_2 is a black box which
-- -- should be generated. The command given by the value of this attribute
-- -- Note the fully qualified SIM (JAVA class) name that forms the
-- -- basis of the core
--
-- --xcc exclude
--
-- -- attribute box_type : string;
-- -- attribute GENERATOR_DEFAULT : string;
-- --
-- -- attribute box_type of dist_mem_gen_v6_3 : component is "black_box";
-- -- attribute GENERATOR_DEFAULT of dist_mem_gen_v6_3 : component is "generatecore com.xilinx.ip.dist_mem_gen_v6_3.dist_mem_gen_v6_3";
-- --xcc include
--
-- -- component declaration for dist_mem_gen_v6_4
-- component dist_mem_gen_v6_4
-- -------------------
-- generic(
-- c_has_clk : integer := 1;
-- c_read_mif : integer := 0;
-- c_has_qspo : integer := 0;
-- c_addr_width : integer := 8;
-- c_width : integer := 15;
-- c_family : string := "virtex7"; -- "virtex6";
-- c_sync_enable : integer := 1;
-- c_depth : integer := 256;
-- c_has_qspo_srst : integer := 1;
-- c_mem_init_file : string := "null.mif";
-- c_default_data : string := "0";
-- ------------------------
-- c_has_qdpo_clk : integer := 0;
-- c_has_qdpo_ce : integer := 0;
-- c_parser_type : integer := 1;
-- c_has_d : integer := 0;
-- c_has_spo : integer := 0;
-- c_reg_a_d_inputs : integer := 0;
-- c_has_we : integer := 0;
-- c_pipeline_stages : integer := 0;
-- c_has_qdpo_rst : integer := 0;
-- c_reg_dpra_input : integer := 0;
-- c_qualify_we : integer := 0;
-- c_has_qdpo_srst : integer := 0;
-- c_has_dpra : integer := 0;
-- c_qce_joined : integer := 0;
-- c_mem_type : integer := 0;
-- c_has_i_ce : integer := 0;
-- c_has_dpo : integer := 0;
-- c_has_spra : integer := 0;
-- c_has_qspo_ce : integer := 0;
-- c_has_qspo_rst : integer := 0;
-- c_has_qdpo : integer := 0
-- -------------------------
-- );
-- port(
-- a : in std_logic_vector(c_addr_width-1-(4*c_has_spra*boolean'pos(c_addr_width > 4)) downto 0) := (others => '0');
-- d : in std_logic_vector(c_width-1 downto 0) := (others => '0');
-- dpra : in std_logic_vector(c_addr_width-1 downto 0) := (others => '0');
-- spra : in std_logic_vector(c_addr_width-1 downto 0) := (others => '0');
-- clk : in std_logic := '0';
-- we : in std_logic := '0';
-- i_ce : in std_logic := '1';
-- qspo_ce : in std_logic := '1';
-- qdpo_ce : in std_logic := '1';
-- qdpo_clk : in std_logic := '0';
-- qspo_rst : in std_logic := '0';
-- qdpo_rst : in std_logic := '0';
-- qspo_srst : in std_logic := '0';
-- qdpo_srst : in std_logic := '0';
-- spo : out std_logic_vector(c_width-1 downto 0);
-- dpo : out std_logic_vector(c_width-1 downto 0);
-- qspo : out std_logic_vector(c_width-1 downto 0);
-- qdpo : out std_logic_vector(c_width-1 downto 0)
-- );
-- end component;
--
-- -- The following tells XST that dist_mem_gen_v6_4 is a black box which
-- -- should be generated. The command given by the value of this attribute
-- -- Note the fully qualified SIM (JAVA class) name that forms the
-- -- basis of the core
--
-- --xcc exclude
--
-- -- attribute box_type of dist_mem_gen_v6_4 : component is "black_box";
-- -- attribute GENERATOR_DEFAULT of dist_mem_gen_v6_4 : component is "generatecore com.xilinx.ip.dist_mem_gen_v6_4.dist_mem_gen_v6_4";
--
-- --xcc include
-- 1/8/2013 added the latest version of dist_mem_gen_v8_0
-- component declaration for dist_mem_gen_v8_0
component dist_mem_gen_v8_0
-------------------
generic(
C_HAS_CLK : integer := 1;
C_READ_MIF : integer := 0;
C_HAS_QSPO : integer := 0;
C_ADDR_WIDTH : integer := 8;
C_WIDTH : integer := 15;
C_FAMILY : string := "virtex7"; -- "virtex6";
C_SYNC_ENABLE : integer := 1;
C_DEPTH : integer := 256;
C_HAS_QSPO_SRST : integer := 1;
C_MEM_INIT_FILE : string := "null.mif";
C_DEFAULT_DATA : string := "0";
------------------------
C_HAS_QDPO_CLK : integer := 0;
C_HAS_QDPO_CE : integer := 0;
C_PARSER_TYPE : integer := 1;
C_HAS_D : integer := 0;
C_HAS_SPO : integer := 0;
C_REG_A_D_INPUTS : integer := 0;
C_HAS_WE : integer := 0;
C_PIPELINE_STAGES : integer := 0;
C_HAS_QDPO_RST : integer := 0;
C_REG_DPRA_INPUT : integer := 0;
C_QUALIFY_WE : integer := 0;
C_HAS_QDPO_SRST : integer := 0;
C_HAS_DPRA : integer := 0;
C_QCE_JOINED : integer := 0;
C_MEM_TYPE : integer := 0;
C_HAS_I_CE : integer := 0;
C_HAS_DPO : integer := 0;
-- C_HAS_SPRA : integer := 0; -- removed from dist mem gen core
C_HAS_QSPO_CE : integer := 0;
C_HAS_QSPO_RST : integer := 0;
C_HAS_QDPO : integer := 0
-------------------------
);
port(
a : in std_logic_vector(c_addr_width-1 downto 0) := (others => '0');
d : in std_logic_vector(c_width-1 downto 0) := (others => '0');
dpra : in std_logic_vector(c_addr_width-1 downto 0) := (others => '0');
-- spra : in std_logic_vector(c_addr_width-1 downto 0) := (others => '0'); -- 2/12/2013
clk : in std_logic := '0';
we : in std_logic := '0';
i_ce : in std_logic := '1';
qspo_ce : in std_logic := '1';
qdpo_ce : in std_logic := '1';
qdpo_clk : in std_logic := '0';
qspo_rst : in std_logic := '0';
qdpo_rst : in std_logic := '0';
qspo_srst : in std_logic := '0';
qdpo_srst : in std_logic := '0';
spo : out std_logic_vector(c_width-1 downto 0);
dpo : out std_logic_vector(c_width-1 downto 0);
qspo : out std_logic_vector(c_width-1 downto 0);
qdpo : out std_logic_vector(c_width-1 downto 0)
);
end component;
-- The following tells XST that dist_mem_gen_v8_0 is a black box which
-- should be generated. The command given by the value of this attribute
-- Note the fully qualified SIM (JAVA class) name that forms the
-- basis of the core
--xcc exclude
-- attribute box_type of dist_mem_gen_v8_0 : component is "black_box";
-- attribute GENERATOR_DEFAULT of dist_mem_gen_v8_0 : component is "generatecore com.xilinx.ip.dist_mem_gen_v8_0.dist_mem_gen_v8_0";
--xcc include
end comp_defs;
| gpl-2.0 | 816efb2dd9032229ca56dc52e7a32130 | 0.395983 | 3.94773 | false | false | false | false |
MAV-RT-testbed/MAV-testbed | Syma_Flight_Final/Syma_Flight_Final.srcs/sources_1/ipshared/rcs.ei.tum.de/Syma_Ctrl_core_v1_2/5d78a94c/hdl/Syma_Ctrl_core_v1_1.vhd | 2 | 14,242 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Syma_Ctrl_core_v1_1 is
generic (
-- Users to add parameters here
-- Determe´ins weather Debug Ports are available
DEBUG : integer := 1;
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Parameters of Axi Slave Bus Interface S00_AXI
C_S00_AXI_DATA_WIDTH : integer := 32;
C_S00_AXI_ADDR_WIDTH : integer := 4;
-- Parameters of Axi Slave Bus Interface S01_AXI
C_S01_AXI_DATA_WIDTH : integer := 32;
C_S01_AXI_ADDR_WIDTH : integer := 5;
-- Parameters of Axi Master Bus Interface M01_AXI
C_M01_AXI_START_DATA_VALUE : std_logic_vector := x"AA000000";
C_M01_AXI_TARGET_SLAVE_BASE_ADDR : std_logic_vector := x"40000000";
C_M01_AXI_ADDR_WIDTH : integer := 32;
C_M01_AXI_DATA_WIDTH : integer := 32;
C_M01_AXI_TRANSACTIONS_NUM : integer := 4
);
port (
-- Users to add ports here
--SPI Init Signal
l_ss_init : out std_logic;
ppm_signal_in : in std_logic;
sample_clk : in std_logic;
ppm_irq_single: out std_logic;
ppm_irq_complete: out std_logic;
-- Debug Ports
d_axi_done : out std_logic;
d_axi_start : out std_logic;
d_axi_data : out std_logic_vector(7 downto 0);
d_axi_addr : out std_logic_vector(7 downto 0);
d_slave_cr : out std_logic_vector(7 downto 0);
d_slave_sr : out std_logic_vector(7 downto 0);
d_slave_flight : out std_logic_vector(31 downto 0);
-- d_ppm_sample : inout std_logic_vector (1 downto 0) := "00";
-- d_counter : inout unsigned (31 downto 0) := x"00_00_00_00";
-- d_reg_nr : inout unsigned (3 downto 0) := "0000";
-- User ports ends
-- Do not modify the ports beyond this line
-- Ports of Axi Slave Bus Interface S00_AXI
s00_axi_aclk : in std_logic;
s00_axi_aresetn : in std_logic;
s00_axi_awaddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_awprot : in std_logic_vector(2 downto 0);
s00_axi_awvalid : in std_logic;
s00_axi_awready : out std_logic;
s00_axi_wdata : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_wstrb : in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0);
s00_axi_wvalid : in std_logic;
s00_axi_wready : out std_logic;
s00_axi_bresp : out std_logic_vector(1 downto 0);
s00_axi_bvalid : out std_logic;
s00_axi_bready : in std_logic;
s00_axi_araddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_arprot : in std_logic_vector(2 downto 0);
s00_axi_arvalid : in std_logic;
s00_axi_arready : out std_logic;
s00_axi_rdata : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_rresp : out std_logic_vector(1 downto 0);
s00_axi_rvalid : out std_logic;
s00_axi_rready : in std_logic;
-- Ports of Axi Slave Bus Interface S01_AXI
s01_axi_aclk : in std_logic;
s01_axi_aresetn : in std_logic;
s01_axi_awaddr : in std_logic_vector(C_S01_AXI_ADDR_WIDTH-1 downto 0);
s01_axi_awprot : in std_logic_vector(2 downto 0);
s01_axi_awvalid : in std_logic;
s01_axi_awready : out std_logic;
s01_axi_wdata : in std_logic_vector(C_S01_AXI_DATA_WIDTH-1 downto 0);
s01_axi_wstrb : in std_logic_vector((C_S01_AXI_DATA_WIDTH/8)-1 downto 0);
s01_axi_wvalid : in std_logic;
s01_axi_wready : out std_logic;
s01_axi_bresp : out std_logic_vector(1 downto 0);
s01_axi_bvalid : out std_logic;
s01_axi_bready : in std_logic;
s01_axi_araddr : in std_logic_vector(C_S01_AXI_ADDR_WIDTH-1 downto 0);
s01_axi_arprot : in std_logic_vector(2 downto 0);
s01_axi_arvalid : in std_logic;
s01_axi_arready : out std_logic;
s01_axi_rdata : out std_logic_vector(C_S01_AXI_DATA_WIDTH-1 downto 0);
s01_axi_rresp : out std_logic_vector(1 downto 0);
s01_axi_rvalid : out std_logic;
s01_axi_rready : in std_logic;
-- Ports of Axi Master Bus Interface M01_AXI
-- m01_axi_init_axi_txn : in std_logic;
-- m01_axi_error : out std_logic;
-- m01_axi_txn_done : out std_logic;
m01_axi_aclk : in std_logic;
m01_axi_aresetn : in std_logic;
m01_axi_awaddr : out std_logic_vector(C_M01_AXI_ADDR_WIDTH-1 downto 0);
m01_axi_awprot : out std_logic_vector(2 downto 0);
m01_axi_awvalid : out std_logic;
m01_axi_awready : in std_logic;
m01_axi_wdata : out std_logic_vector(C_M01_AXI_DATA_WIDTH-1 downto 0);
m01_axi_wstrb : out std_logic_vector(C_M01_AXI_DATA_WIDTH/8-1 downto 0);
m01_axi_wvalid : out std_logic;
m01_axi_wready : in std_logic;
m01_axi_bresp : in std_logic_vector(1 downto 0);
m01_axi_bvalid : in std_logic;
m01_axi_bready : out std_logic;
m01_axi_araddr : out std_logic_vector(C_M01_AXI_ADDR_WIDTH-1 downto 0);
m01_axi_arprot : out std_logic_vector(2 downto 0);
m01_axi_arvalid : out std_logic;
m01_axi_arready : in std_logic;
m01_axi_rdata : in std_logic_vector(C_M01_AXI_DATA_WIDTH-1 downto 0);
m01_axi_rresp : in std_logic_vector(1 downto 0);
m01_axi_rvalid : in std_logic;
m01_axi_rready : out std_logic
);
end Syma_Ctrl_core_v1_1;
architecture arch_imp of Syma_Ctrl_core_v1_1 is
signal m01_axi_init_axi_txn : std_logic;
signal m01_axi_txn_done : std_logic;
signal m01_axi_spi_data : std_logic_vector(7 downto 0);
signal m01_axi_spi_addr : std_logic_vector(7 downto 0);
signal m01_axi_error : std_logic;
signal s00_axi_cr : std_logic_vector(7 downto 0);
signal s00_axi_sr : std_logic_vector(7 downto 0);
signal s00_axi_flight : std_logic_vector(31 downto 0);
-- component declaration
component Syma_Ctrl_core_v1_1_S00_AXI is
generic (
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 4
);
port (
S_AXI_CR : out std_logic_vector(7 downto 0);
S_AXI_SR : in std_logic_vector(7 downto 0);
S_AXI_FLIGHT : out std_logic_vector(31 downto 0);
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic
);
end component Syma_Ctrl_core_v1_1_S00_AXI;
component Syma_Ctrl_core_v1_1_S01_AXI is
generic (
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 5
);
port (
PPM_INPUT : in std_logic;
SAMPLE_CLOCK : in std_logic;
INTR_SINGLE : out std_logic;
INTR_COMPLETE: out std_logic;
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic
);
end component Syma_Ctrl_core_v1_1_S01_AXI;
component Syma_Ctrl_core_v1_1_M01_AXI is
generic (
C_M_START_DATA_VALUE : std_logic_vector := x"AA000000";
C_M_TARGET_SLAVE_BASE_ADDR : std_logic_vector := x"40000000";
C_M_AXI_ADDR_WIDTH : integer := 32;
C_M_AXI_DATA_WIDTH : integer := 32;
C_M_TRANSACTIONS_NUM : integer := 4
);
port (
INIT_AXI_TXN : in std_logic;
ERROR : out std_logic;
TXN_DONE : out std_logic;
M_AXI_ACLK : in std_logic;
M_AXI_ARESETN : in std_logic;
M_AXI_AWADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
M_AXI_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_AWVALID : out std_logic;
M_AXI_AWREADY : in std_logic;
M_AXI_WDATA : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
M_AXI_WSTRB : out std_logic_vector(C_M_AXI_DATA_WIDTH/8-1 downto 0);
M_AXI_WVALID : out std_logic;
M_AXI_WREADY : in std_logic;
M_AXI_BRESP : in std_logic_vector(1 downto 0);
M_AXI_BVALID : in std_logic;
M_AXI_BREADY : out std_logic;
M_AXI_ARADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
M_AXI_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_ARVALID : out std_logic;
M_AXI_ARREADY : in std_logic;
M_AXI_RDATA : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
M_AXI_RRESP : in std_logic_vector(1 downto 0);
M_AXI_RVALID : in std_logic;
M_AXI_RREADY : out std_logic;
M_AXI_SPI_DATA : in std_logic_vector(7 downto 0);
M_AXI_SPI_ADDR : in std_logic_vector(7 downto 0)
);
end component Syma_Ctrl_core_v1_1_M01_AXI;
component spi_timer is
Port (
clk : in std_logic;
axi_done : std_logic;
axi_start : out std_logic;
axi_data : out std_logic_vector (7 downto 0);
axi_addr : out std_logic_vector (7 downto 0);
slave_cr : in std_logic_vector (7 downto 0);
slave_sr : out std_logic_vector (7 downto 0);
slave_flight : in std_logic_vector (31 downto 0);
ss_init : out std_logic := '0'); -- ss init signal needed by transmitter module, logical or with ss in board design
end component;
begin
-- Instantiation of Axi Bus Interface S00_AXI
Syma_Ctrl_core_v1_1_S00_AXI_inst : Syma_Ctrl_core_v1_1_S00_AXI
generic map (
C_S_AXI_DATA_WIDTH => C_S00_AXI_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S00_AXI_ADDR_WIDTH
)
port map (
S_AXI_CR => s00_axi_cr,
S_AXI_SR => s00_axi_sr,
S_AXI_FLIGHT => s00_axi_flight,
S_AXI_ACLK => s00_axi_aclk,
S_AXI_ARESETN => s00_axi_aresetn,
S_AXI_AWADDR => s00_axi_awaddr,
S_AXI_AWPROT => s00_axi_awprot,
S_AXI_AWVALID => s00_axi_awvalid,
S_AXI_AWREADY => s00_axi_awready,
S_AXI_WDATA => s00_axi_wdata,
S_AXI_WSTRB => s00_axi_wstrb,
S_AXI_WVALID => s00_axi_wvalid,
S_AXI_WREADY => s00_axi_wready,
S_AXI_BRESP => s00_axi_bresp,
S_AXI_BVALID => s00_axi_bvalid,
S_AXI_BREADY => s00_axi_bready,
S_AXI_ARADDR => s00_axi_araddr,
S_AXI_ARPROT => s00_axi_arprot,
S_AXI_ARVALID => s00_axi_arvalid,
S_AXI_ARREADY => s00_axi_arready,
S_AXI_RDATA => s00_axi_rdata,
S_AXI_RRESP => s00_axi_rresp,
S_AXI_RVALID => s00_axi_rvalid,
S_AXI_RREADY => s00_axi_rready
);
-- Instantiation of Axi Bus Interface S01_AXI
Syma_Ctrl_core_v1_1_S01_AXI_inst : Syma_Ctrl_core_v1_1_S01_AXI
generic map (
C_S_AXI_DATA_WIDTH => C_S01_AXI_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S01_AXI_ADDR_WIDTH
)
port map (
PPM_INPUT => ppm_signal_in,
SAMPLE_CLOCK => sample_clk,
INTR_SINGLE => ppm_irq_single,
INTR_COMPLETE => ppm_irq_complete,
S_AXI_ACLK => s01_axi_aclk,
S_AXI_ARESETN => s01_axi_aresetn,
S_AXI_AWADDR => s01_axi_awaddr,
S_AXI_AWPROT => s01_axi_awprot,
S_AXI_AWVALID => s01_axi_awvalid,
S_AXI_AWREADY => s01_axi_awready,
S_AXI_WDATA => s01_axi_wdata,
S_AXI_WSTRB => s01_axi_wstrb,
S_AXI_WVALID => s01_axi_wvalid,
S_AXI_WREADY => s01_axi_wready,
S_AXI_BRESP => s01_axi_bresp,
S_AXI_BVALID => s01_axi_bvalid,
S_AXI_BREADY => s01_axi_bready,
S_AXI_ARADDR => s01_axi_araddr,
S_AXI_ARPROT => s01_axi_arprot,
S_AXI_ARVALID => s01_axi_arvalid,
S_AXI_ARREADY => s01_axi_arready,
S_AXI_RDATA => s01_axi_rdata,
S_AXI_RRESP => s01_axi_rresp,
S_AXI_RVALID => s01_axi_rvalid,
S_AXI_RREADY => s01_axi_rready
);
-- Instantiation of Axi Bus Interface M01_AXI
Syma_Ctrl_core_v1_1_M01_AXI_inst : Syma_Ctrl_core_v1_1_M01_AXI
generic map (
C_M_START_DATA_VALUE => C_M01_AXI_START_DATA_VALUE,
C_M_TARGET_SLAVE_BASE_ADDR => C_M01_AXI_TARGET_SLAVE_BASE_ADDR,
C_M_AXI_ADDR_WIDTH => C_M01_AXI_ADDR_WIDTH,
C_M_AXI_DATA_WIDTH => C_M01_AXI_DATA_WIDTH,
C_M_TRANSACTIONS_NUM => C_M01_AXI_TRANSACTIONS_NUM
)
port map (
M_AXI_SPI_DATA => m01_axi_spi_data,
M_AXI_SPI_ADDR => m01_axi_spi_addr,
INIT_AXI_TXN => m01_axi_init_axi_txn,
ERROR => m01_axi_error,
TXN_DONE => m01_axi_txn_done,
M_AXI_ACLK => m01_axi_aclk,
M_AXI_ARESETN => m01_axi_aresetn,
M_AXI_AWADDR => m01_axi_awaddr,
M_AXI_AWPROT => m01_axi_awprot,
M_AXI_AWVALID => m01_axi_awvalid,
M_AXI_AWREADY => m01_axi_awready,
M_AXI_WDATA => m01_axi_wdata,
M_AXI_WSTRB => m01_axi_wstrb,
M_AXI_WVALID => m01_axi_wvalid,
M_AXI_WREADY => m01_axi_wready,
M_AXI_BRESP => m01_axi_bresp,
M_AXI_BVALID => m01_axi_bvalid,
M_AXI_BREADY => m01_axi_bready,
M_AXI_ARADDR => m01_axi_araddr,
M_AXI_ARPROT => m01_axi_arprot,
M_AXI_ARVALID => m01_axi_arvalid,
M_AXI_ARREADY => m01_axi_arready,
M_AXI_RDATA => m01_axi_rdata,
M_AXI_RRESP => m01_axi_rresp,
M_AXI_RVALID => m01_axi_rvalid,
M_AXI_RREADY => m01_axi_rready
);
-- Add user logic here
spi_timer_0 : spi_timer
port map (
clk => m01_axi_aclk,
axi_done => m01_axi_txn_done,
axi_start => m01_axi_init_axi_txn,
axi_data => m01_axi_spi_data,
axi_addr => m01_axi_spi_addr,
slave_cr => s00_axi_cr,
slave_sr => s00_axi_sr,
slave_flight => s00_axi_flight,
ss_init => l_ss_init
);
d_axi_done <= m01_axi_txn_done;
d_axi_start <= m01_axi_init_axi_txn;
d_axi_data <= m01_axi_spi_data;
d_axi_addr <= m01_axi_spi_addr;
d_slave_cr <= s00_axi_cr;
d_slave_sr <= s00_axi_sr;
d_slave_flight <= s00_axi_flight;
-- User logic ends
end arch_imp;
| gpl-2.0 | bcd72e6fa7d003e746db0a589915c5b6 | 0.648971 | 2.420704 | false | false | false | false |
jobisoft/jTDC | modules/register/readonly_register_with_readtrigger.vhdl | 1 | 2,860 | -------------------------------------------------------------------------
---- ----
---- Company: University of Bonn ----
---- Engineer: John Bieling ----
---- ----
-------------------------------------------------------------------------
---- ----
---- Copyright (C) 2015 John Bieling ----
---- ----
---- This program is free software; you can redistribute it and/or ----
---- modify it under the terms of the GNU General Public License as ----
---- published by the Free Software Foundation; either version 3 of ----
---- the License, or (at your option) any later version. ----
---- ----
---- This program is distributed in the hope that it will be useful, ----
---- but WITHOUT ANY WARRANTY; without even the implied warranty of ----
---- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ----
---- GNU General Public License for more details. ----
---- ----
---- You should have received a copy of the GNU General Public ----
---- License along with this program; if not, see ----
---- <http://www.gnu.org/licenses>. ----
---- ----
-------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
use ieee.numeric_std.all;
entity readonly_register_with_readtrigger is
Generic (myaddress: natural := 16#FFFF#);
Port ( databus : out STD_LOGIC_VECTOR (31 downto 0) := (others => '0');
addressbus : in STD_LOGIC_VECTOR (15 downto 0);
readsignal : in STD_LOGIC;
readtrigger : out STD_LOGIC;
CLK : in STD_LOGIC;
registerbits : in STD_LOGIC_VECTOR (31 downto 0));
end readonly_register_with_readtrigger;
architecture Behavioral of readonly_register_with_readtrigger is
begin
process (CLK) begin
if (rising_edge(CLK)) then
if (addressbus = myaddress and readsignal='1') then
databus <= registerbits;
readtrigger <= '1';
else
databus <= (others => 'Z');
readtrigger <= '0';
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | 5077dac2fda30adc64eea3bd3354be86 | 0.446154 | 5.218978 | false | false | false | false |
manosaloscables/vhdl | generador_pixeles/gen_px.vhd | 1 | 2,552 | -- *********************************
-- * Circuito para generar píxeles *
-- *********************************
library ieee;
use ieee.std_logic_1164.all;
entity gen_px is
port(
clk , rst : in std_logic;
rgb : out std_logic_vector(2 downto 0);
hsinc, vsinc : out std_logic
);
end gen_px;
architecture arq of gen_px is
signal px_tick, video_on: std_logic;
signal px_x, px_y: std_logic_vector(9 downto 0);
signal pared_on, bar_on, bola_on: std_logic;
signal pared_rgb, bar_rgb, bola_rgb, rgb_reg, rgb_next:
std_logic_vector(2 downto 0);
begin
-- Instanciar un circuito de sincronización VGA
unidad_vga_sinc: entity work.vga_sinc(arq)
port map(
clk => clk,
rst => rst,
px_tick => px_tick,
video_on => video_on,
pixel_x => px_x,
pixel_y => px_y,
hsinc => hsinc,
vsinc => vsinc
);
-- Instanciar un generador de objetos con pared
unidad_gen_obj: entity work.gen_obj(pared)
port map(
obj_on => pared_on,
pixel_x => px_x,
pixel_y => px_y,
obj_rgb => pared_rgb
);
-- Instanciar un generador de objetos con barra
u2_gen_obj: entity work.gen_obj(barra)
port map(
obj_on => bar_on,
pixel_x => px_x,
pixel_y => px_y,
obj_rgb => bar_rgb
);
-- Instanciar un generador de objetos con bola
u3_gen_obj: entity work.gen_obj(bola)
port map(
obj_on => bola_on,
pixel_x => px_x,
pixel_y => px_y,
obj_rgb => bola_rgb
);
-----------------------------------------
-- Circuito multiplexor de objetos RGB --
-----------------------------------------
-- Revisar las entradas (sensitivy list)
process(video_on, pared_on, bar_on, pared_rgb, bar_rgb) begin
if video_on = '0' then
rgb_next <= "000"; -- Apagado
else
if pared_on = '1' then
rgb_next <= pared_rgb;
elsif bar_on = '1' then
rgb_next <= bar_rgb;
elsif bola_on = '1' then
rgb_next <= bola_rgb;
else
rgb_next <= "111"; -- Fondo blanco
end if;
end if;
end process;
-- Búfer RGB
process(clk, rst) begin
if rst = '0' then
rgb_reg <= (others => '0');
elsif(rising_edge(clk)) then
if px_tick = '1' then
rgb_reg <= rgb_next;
end if;
end if;
end process;
rgb <= rgb_reg;
end arq; | gpl-3.0 | e495bec32cfbcc6492cacbe35f43637c | 0.488035 | 3.31039 | false | false | false | false |
airabinovich/finalArquitectura | TestDatapathPart1/DatapathPart1/ipcore_dir/blk_mem_gen_v7_3/example_design/blk_mem_gen_v7_3_prod.vhd | 1 | 9,962 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: blk_mem_gen_v7_3_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan6
-- C_XDEVICEFAMILY : spartan6
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 3
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : blk_mem_gen_v7_3.mif
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 32
-- C_READ_WIDTH_A : 32
-- C_WRITE_DEPTH_A : 256
-- C_READ_DEPTH_A : 256
-- C_ADDRA_WIDTH : 8
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 32
-- C_READ_WIDTH_B : 32
-- C_WRITE_DEPTH_B : 256
-- C_READ_DEPTH_B : 256
-- C_ADDRB_WIDTH : 8
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY blk_mem_gen_v7_3_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END blk_mem_gen_v7_3_prod;
ARCHITECTURE xilinx OF blk_mem_gen_v7_3_prod IS
COMPONENT blk_mem_gen_v7_3_exdes IS
PORT (
--Port A
ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : blk_mem_gen_v7_3_exdes
PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
| lgpl-2.1 | 52cc5d79b3fd19b8527782af0a21e416 | 0.494981 | 3.773485 | false | false | false | false |
MAV-RT-testbed/MAV-testbed | Syma_Flight_Final/Syma_Flight_Final.srcs/sources_1/ipshared/xilinx.com/axi_quad_spi_v3_2/c64e9f22/hdl/src/vhdl/axi_quad_spi.vhd | 1 | 75,429 | -------------------------------------------------------------------------------
-- axi_quad_spi.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_quad_spi.vhd
-- Version: v3.0
-- Description: This is the top-level design file for the AXI Quad SPI core.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.conv_std_logic_vector;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_misc.all;
-- library unsigned is used for overloading of "=" which allows integer to
-- be compared to std_logic_vector
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.FD;
use unisim.vcomponents.FDRE;
use UNISIM.vcomponents.all;
library axi_lite_ipif_v3_0;
use axi_lite_ipif_v3_0.axi_lite_ipif;
use axi_lite_ipif_v3_0.ipif_pkg.all;
library axi_quad_spi_v3_2;
use axi_quad_spi_v3_2.all;
-------------------------------------------------------------------------------
entity axi_quad_spi is
generic(
-- Async_Clk parameter is added only for Vivado, it is not used in the design, this is
-- NON HDL parameter
Async_Clk : integer := 0;
-- General Parameters
C_FAMILY : string := "virtex7";
C_SUB_FAMILY : string := "virtex7";
C_INSTANCE : string := "axi_quad_spi_inst";
-------------------------
C_SPI_MEM_ADDR_BITS : integer := 24; -- allowed values are 24 or 32 only and used in XIP mode
C_TYPE_OF_AXI4_INTERFACE : integer range 0 to 1 := 0;--default AXI4 Lite Legacy mode
C_XIP_MODE : integer range 0 to 1 := 0;--default NON XIP Mode
--C_AXI4_CLK_PS : integer := 10000;--AXI clock period
--C_EXT_SPI_CLK_PS : integer := 10000;--ext clock period
C_FIFO_DEPTH : integer := 256;-- allowed 0,16,256.
C_SCK_RATIO : integer := 16;--default in legacy mode
C_NUM_SS_BITS : integer range 1 to 32:= 1;
C_NUM_TRANSFER_BITS : integer := 8; -- allowed 8, 16, 32
-------------------------
C_SPI_MODE : integer range 0 to 2 := 0; -- used for differentiating
-- Standard, Dual or Quad mode
-- in Ports as well as internal
-- functionality
C_USE_STARTUP : integer range 0 to 1 := 1; --
C_SPI_MEMORY : integer range 0 to 3 := 1; -- 0 - mixed mode,
-- 1 - winbond,
-- 2 - numonyx
-- 3 - spansion
-- used to differentiate
-- internal look up table
-- for commands.
-------------------------
-- AXI4 Lite Interface Parameters *as max address is 7c, only 7 address bits are used
C_S_AXI_ADDR_WIDTH : integer range 7 to 7 := 7;
C_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32;
-------------------------
--*C_BASEADDR : std_logic_vector := x"FFFFFFFF";
--*C_HIGHADDR : std_logic_vector := x"00000000";
-------------------------
-- AXI4 Full Interface Parameters *as max 24 bits of address are supported on SPI interface, only 24 address bits are used
C_S_AXI4_ADDR_WIDTH : integer ;--range 24 to 24 := 24;
C_S_AXI4_DATA_WIDTH : integer range 32 to 32 := 32;
C_S_AXI4_ID_WIDTH : integer range 1 to 16 := 4 ;
-------------------------
-- To FIX CR# 685366, below lines are added again in RTL (Vivado Requirement), but these parameters are not used in the core RTL
C_S_AXI4_BASEADDR : std_logic_vector := x"FFFFFFFF";
C_S_AXI4_HIGHADDR : std_logic_vector := x"00000000"
-------------------------
);
port(
-- external async clock for SPI interface logic
ext_spi_clk : in std_logic;
-- axi4 lite interface clk and reset signals
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
-- axi4 full interface clk and reset signals
s_axi4_aclk : in std_logic;
s_axi4_aresetn : in std_logic;
-------------------------------
-------------------------------
--*axi4 lite port interface* --
-------------------------------
-------------------------------
-- axi write address channel signals
---------------
s_axi_awaddr : in std_logic_vector (6 downto 0);--((C_S_AXI_ADDR_WIDTH-1) downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
---------------
-- axi write data channel signals
---------------
s_axi_wdata : in std_logic_vector(31 downto 0); -- ((C_S_AXI_DATA_WIDTH-1) downto 0);
s_axi_wstrb : in std_logic_vector(3 downto 0); -- (((C_S_AXI_DATA_WIDTH/8)-1) downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
---------------
-- axi write response channel signals
---------------
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
---------------
-- axi read address channel signals
---------------
s_axi_araddr : in std_logic_vector(6 downto 0); -- ((C_S_AXI_ADDR_WIDTH-1) downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
---------------
-- axi read address channel signals
---------------
s_axi_rdata : out std_logic_vector(31 downto 0); -- ((C_S_AXI_DATA_WIDTH-1) downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
-------------------------------
-------------------------------
--*axi4 full port interface* --
-------------------------------
------------------------------------
-- axi write address Channel Signals
------------------------------------
s_axi4_awid : in std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
s_axi4_awaddr : in std_logic_vector((C_SPI_MEM_ADDR_BITS-1) downto 0); --((C_S_AXI4_ADDR_WIDTH-1) downto 0);
s_axi4_awlen : in std_logic_vector(7 downto 0);
s_axi4_awsize : in std_logic_vector(2 downto 0);
s_axi4_awburst : in std_logic_vector(1 downto 0);
s_axi4_awlock : in std_logic; -- not supported in design
s_axi4_awcache : in std_logic_vector(3 downto 0);-- not supported in design
s_axi4_awprot : in std_logic_vector(2 downto 0);-- not supported in design
s_axi4_awvalid : in std_logic;
s_axi4_awready : out std_logic;
---------------------------------------
-- axi4 full write Data Channel Signals
---------------------------------------
s_axi4_wdata : in std_logic_vector(31 downto 0); -- ((C_S_AXI4_DATA_WIDTH-1)downto 0);
s_axi4_wstrb : in std_logic_vector(3 downto 0); -- (((C_S_AXI4_DATA_WIDTH/8)-1) downto 0);
s_axi4_wlast : in std_logic;
s_axi4_wvalid : in std_logic;
s_axi4_wready : out std_logic;
-------------------------------------------
-- axi4 full write Response Channel Signals
-------------------------------------------
s_axi4_bid : out std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
s_axi4_bresp : out std_logic_vector(1 downto 0);
s_axi4_bvalid : out std_logic;
s_axi4_bready : in std_logic;
-----------------------------------
-- axi read address Channel Signals
-----------------------------------
s_axi4_arid : in std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
s_axi4_araddr : in std_logic_vector((C_SPI_MEM_ADDR_BITS-1) downto 0);--((C_S_AXI4_ADDR_WIDTH-1) downto 0);
s_axi4_arlen : in std_logic_vector(7 downto 0);
s_axi4_arsize : in std_logic_vector(2 downto 0);
s_axi4_arburst : in std_logic_vector(1 downto 0);
s_axi4_arlock : in std_logic; -- not supported in design
s_axi4_arcache : in std_logic_vector(3 downto 0);-- not supported in design
s_axi4_arprot : in std_logic_vector(2 downto 0);-- not supported in design
s_axi4_arvalid : in std_logic;
s_axi4_arready : out std_logic;
--------------------------------
-- axi read data Channel Signals
--------------------------------
s_axi4_rid : out std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
s_axi4_rdata : out std_logic_vector(31 downto 0);--((C_S_AXI4_DATA_WIDTH-1) downto 0);
s_axi4_rresp : out std_logic_vector(1 downto 0);
s_axi4_rlast : out std_logic;
s_axi4_rvalid : out std_logic;
s_axi4_rready : in std_logic;
--------------------------------
-------------------------------
--*SPI port interface * --
-------------------------------
io0_i : in std_logic; -- MOSI signal in standard SPI
io0_o : out std_logic;
io0_t : out std_logic;
-------------------------------
io1_i : in std_logic; -- MISO signal in standard SPI
io1_o : out std_logic;
io1_t : out std_logic;
-----------------
-- quad mode pins
-----------------
io2_i : in std_logic;
io2_o : out std_logic;
io2_t : out std_logic;
---------------
io3_i : in std_logic;
io3_o : out std_logic;
io3_t : out std_logic;
---------------------------------
-- common pins
----------------
spisel : in std_logic;
-----
sck_i : in std_logic;
sck_o : out std_logic;
sck_t : out std_logic;
-----
ss_i : in std_logic_vector((C_NUM_SS_BITS-1) downto 0);
ss_o : out std_logic_vector((C_NUM_SS_BITS-1) downto 0);
ss_t : out std_logic;
------------------------
-- STARTUP INTERFACE
------------------------
cfgclk : out std_logic; -- FGCLK , -- 1-bit output: Configuration main clock output
cfgmclk : out std_logic; -- FGMCLK , -- 1-bit output: Configuration internal oscillator clock output
eos : out std_logic; -- OS , -- 1-bit output: Active high output signal indicating the End Of Startup.
preq : out std_logic; -- REQ , -- 1-bit output: PROGRAM request to fabric output
di : out std_logic_vector(3 downto 0); -- output
----------------------
-- INTERRUPT INTERFACE
----------------------
ip2intc_irpt : out std_logic
---------------------------------
);
-------------------------------
-- Fan-out attributes for XST
attribute MAX_FANOUT : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI4_ACLK : signal is "10000";
attribute MAX_FANOUT of EXT_SPI_CLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute MAX_FANOUT of S_AXI4_ARESETN : signal is "10000";
attribute INITIALVAL : string;
attribute INITIALVAL of SPISEL : signal is "VCC";
-- attribute IOB : string;
-- attribute IOB of io0_t: signal is "FALSE";
-- attribute IOB of io1_t: signal is "FALSE";
-- attribute IOB of io2_t: signal is "FALSE";
-- attribute IOB of io3_t: signal is "FALSE";
-- attribute IOB of io0_o: signal is "FALSE";
-- attribute IOB of io1_o: signal is "FALSE";
-- attribute IOB of io2_o: signal is "FALSE";
-- attribute IOB of io3_o: signal is "FALSE";
-- attribute IOB of io0_i: signal is "TRUE";
-- attribute IOB of io1_i: signal is "TRUE";
-- attribute IOB of io2_i: signal is "TRUE";
-- attribute IOB of io3_i: signal is "TRUE";
-------------------------------
end entity axi_quad_spi;
--------------------------------------------------------------------------------
architecture imp of axi_quad_spi is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
---------------------------------------------------------------------------------
---- constant added for webtalk information
---------------------------------------------------------------------------------
-- constant C_CORE_GENERATION_INFO : string := C_INSTANCE & ",axi_quad_spi,{"
-- & "C_FAMILY = " & C_FAMILY
-- & ",C_SUB_FAMILY = " & C_SUB_FAMILY
-- & ",C_INSTANCE = " & C_INSTANCE
-- & ",C_S_AXI_ADDR_WIDTH = " & integer'image(C_S_AXI_ADDR_WIDTH)
-- & ",C_S_AXI_DATA_WIDTH = " & integer'image(C_S_AXI_DATA_WIDTH)
-- & ",C_S_AXI4_ADDR_WIDTH = " & integer'image(C_S_AXI4_ADDR_WIDTH)
-- & ",C_S_AXI4_DATA_WIDTH = " & integer'image(C_S_AXI4_DATA_WIDTH)
-- & ",C_S_AXI4_ID_WIDTH = " & integer'image(C_S_AXI4_ID_WIDTH)
-- & ",C_FIFO_DEPTH = " & integer'image(C_FIFO_DEPTH)
-- & ",C_SCK_RATIO = " & integer'image(C_SCK_RATIO)
-- & ",C_NUM_SS_BITS = " & integer'image(C_NUM_SS_BITS)
-- & ",C_NUM_TRANSFER_BITS = " & integer'image(C_NUM_TRANSFER_BITS)
-- & ",C_USE_STARTUP = " & integer'image(C_USE_STARTUP)
-- & ",C_SPI_MODE = " & integer'image(C_SPI_MODE)
-- & ",C_SPI_MEMORY = " & integer'image(C_SPI_MEMORY)
-- & ",C_TYPE_OF_AXI4_INTERFACE = " & integer'image(C_TYPE_OF_AXI4_INTERFACE)
-- & ",C_XIP_MODE = " & integer'image(C_XIP_MODE)
-- & "}";
--
-- attribute CORE_GENERATION_INFO : string;
-- attribute CORE_GENERATION_INFO of imp : architecture is C_CORE_GENERATION_INFO;
-------------------------------------------------------------
-------------------------------------------------------------
-- Function Declaration
-------------------------------------------------------------
-- get_fifo_presence - This function returns the 0 or 1 based upon the FIFO Depth.
--
function get_fifo_presence(C_FIFO_DEPTH: integer) return integer is
-----
begin
-----
if(C_FIFO_DEPTH = 0)then
return 0;
else
return 1;
end if;
end function get_fifo_presence;
function get_fifo_depth(C_FIFO_EXIST: integer; C_FIFO_DEPTH : integer) return integer is
-----
begin
-----
if(C_FIFO_EXIST = 1)then
return C_FIFO_DEPTH;
else
return 64; -- to ensure that log2 functions does not become invalid
end if;
end function get_fifo_depth;
------------------------------
function get_fifo_occupancy_count(C_FIFO_DEPTH: integer) return integer is
-----
variable j : integer := 0;
variable k : integer := 0;
-----
begin
-----
if (C_FIFO_DEPTH = 0) then
return 4;
else
for i in 0 to 11 loop
if(2**i >= C_FIFO_DEPTH) then
if(k = 0) then
j := i;
end if;
k := 1;
end if;
end loop;
return j;
end if;
-------
end function get_fifo_occupancy_count;
------------------------------
-- Constant declarations
------------------------------
--------------------- ******************* ------------------------------------
-- Core Parameters
--------------------- ******************* ------------------------------------
--
constant C_FIFO_EXIST : integer := get_fifo_presence(C_FIFO_DEPTH);
constant C_FIFO_DEPTH_UPDATED : integer := get_fifo_depth(C_FIFO_EXIST, C_FIFO_DEPTH);
-- width of control register
constant C_SPICR_REG_WIDTH : integer := 10;-- refer DS
-- width of status register
constant C_SPISR_REG_WIDTH : integer := 11;-- refer DS
-- count the counter width for calculating FIFO occupancy
constant C_OCCUPANCY_NUM_BITS : integer := get_fifo_occupancy_count(C_FIFO_DEPTH_UPDATED);
-- width of spi shift register
constant C_SPI_NUM_BITS_REG : integer := 8;-- this is fixed
constant C_NUM_SPI_REGS : integer := 8;-- this is fixed
constant C_IPISR_IPIER_BITS : integer := 14;-- total 14 interrupts - 0 to 13
--------------------- ******************* ------------------------------------
-- AXI lite parameters
--------------------- ******************* ------------------------------------
constant C_S_AXI_SPI_MIN_SIZE : std_logic_vector(31 downto 0):= X"0000007c";
constant C_USE_WSTRB : integer := 1;
constant C_DPHASE_TIMEOUT : integer := 20;
-- interupt mode
constant IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE(0 to (C_IPISR_IPIER_BITS-1)):=
(
others => INTR_REG_EVENT
-- when C_SPI_MODE = 0
-- Seven interrupts if C_FIFO_DEPTH_UPDATED = 0
-- OR
-- Eight interrupts if C_FIFO_DEPTH_UPDATED = 0 and slave mode
----------------------- OR ---------------------------
-- Nine interrupts if C_FIFO_DEPTH_UPDATED = 16 and slave mode
-- OR
-- Seven interrupts if C_FIFO_DEPTH_UPDATED = 16 and master mode
-- when C_SPI_MODE = 1 or 2
-- Thirteen interrupts if C_FIFO_DEPTH_UPDATED = 16 and master mode
);
constant ZEROES : std_logic_vector(31 downto 0):= X"00000000";
-- this constant is defined as the start of SPI register addresses.
constant C_IP_REG_ADDR_OFFSET : std_logic_vector := X"00000060";
-- Address range array
constant C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
-- interrupt address base & high range
--ZEROES & C_BASEADDR,
--ZEROES & (C_BASEADDR or X"0000003F"),--interrupt address higher range
ZEROES & X"00000000",
ZEROES & X"0000003F",--interrupt address higher range
-- soft reset register base & high addr
--ZEROES & (C_BASEADDR or X"00000040"),
--ZEROES & (C_BASEADDR or X"00000043"),--soft reset register high addr
ZEROES & X"00000040",
-- ZEROES & X"00000043",--soft reset register high addr
ZEROES & X"0000005C",--soft reset register NEW high addr for addressing holes
-- SPI registers Base & High Address
-- Range is 60 to 78 -- for internal registers
--ZEROES & (C_BASEADDR or C_IP_REG_ADDR_OFFSET),
--ZEROES & (C_BASEADDR or C_IP_REG_ADDR_OFFSET or X"00000018")
ZEROES & C_IP_REG_ADDR_OFFSET,
ZEROES & (C_IP_REG_ADDR_OFFSET or X"00000018")
);
-- AXI4 Address range array
constant C_ARD_ADDR_RANGE_ARRAY_AXI4_FULL: SLV64_ARRAY_TYPE :=
(
-- interrupt address base & high range
--*ZEROES & C_S_AXI4_BASEADDR,
--*ZEROES & (C_S_AXI4_BASEADDR or X"0000003F"),--interrupt address higher range
ZEROES & X"00000000",
ZEROES & X"0000003F",--soft reset register high addr
-- soft reset register base & high addr
--*ZEROES & (C_S_AXI4_BASEADDR or X"00000040"),
--*ZEROES & (C_S_AXI4_BASEADDR or X"00000043"),--soft reset register high addr
ZEROES & X"00000040",
-- ZEROES & X"00000043",--soft reset register high addr
ZEROES & X"0000005C",--soft reset register NEW high addr for addressing holes
-- SPI registers Base & High Address
-- Range is 60 to 78 -- for internal registers
ZEROES & (C_IP_REG_ADDR_OFFSET),
ZEROES & (C_IP_REG_ADDR_OFFSET or X"00000018")
);
-- No. of CE's required per address range
constant C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 16 , -- 16 CEs required for interrupt
--1 => 1, -- 1 CE required for soft reset
1 => 8, -- 8 CE required for Addressing Holes in soft reset
2 => C_NUM_SPI_REGS
);
-- no. of Chip Enable Signals
constant C_NUM_CE_SIGNALS : integer := calc_num_ce(C_ARD_NUM_CE_ARRAY);
-- no. of Chip Select Signals
constant C_NUM_CS_SIGNALS : integer := (C_ARD_ADDR_RANGE_ARRAY'LENGTH/2);
-----------------------------
----------------------- ******************* ------------------------------------
---- XIP Mode parameters
----------------------- ******************* ------------------------------------
-- No. of XIP SPI registers
constant C_NUM_XIP_SPI_REGS : integer := 2;-- this is fixed
-- width of XIP control register
constant C_XIP_SPICR_REG_WIDTH: integer := 2;-- refer DS
-- width of XIP status register
constant C_XIP_SPISR_REG_WIDTH: integer := 5;-- refer DS
-- Address range array
constant C_XIP_LITE_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
-- XIP SPI registers Base & High Address
-- Range is 60 to 64 -- for internal registers
--*ZEROES & (C_BASEADDR or C_IP_REG_ADDR_OFFSET),
--*ZEROES & (C_BASEADDR or C_IP_REG_ADDR_OFFSET or X"00000004")
ZEROES & (C_IP_REG_ADDR_OFFSET),
ZEROES & (C_IP_REG_ADDR_OFFSET or X"00000004")
);
-- No. of CE's required per address range
constant C_XIP_LITE_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => C_NUM_XIP_SPI_REGS -- 2 CEs required for XIP lite interface
);
-- no. of Chip Enable Signals
constant C_NUM_XIP_CE_SIGNALS : integer :=
calc_num_ce(C_XIP_LITE_ARD_NUM_CE_ARRAY);
function assign_addr_bits (addr_bits_info : integer) return string is
variable addr_width_24 : integer:= 24;
variable addr_width_32 : integer:= 32;
begin
if addr_bits_info = 24 then -- old logic for 24 bit addressing
return X"00FFFFFF";--addr_width_24;
else
return X"FFFFFFFF";--addr_width_32;
end if;
end function assign_addr_bits;
constant C_XIP_ADDR_OFFSET : std_logic_vector := X"FFFFFFFF";--assign_addr_bits(C_SPI_MEM_ADDR_BITS); -- X"00FFFFFF";
-- XIP Full Interface Address range array
constant C_XIP_FULL_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
-- XIP SPI registers Base & High Address
-- Range is 60 to 64 -- for internal registers
--*ZEROES & (C_S_AXI4_BASEADDR),
--*ZEROES & (C_S_AXI4_BASEADDR or C_24_BIT_ADDR_OFFSET)
ZEROES & X"00000000",
ZEROES & C_XIP_ADDR_OFFSET
);
-- No. of CE's required per address range
constant C_XIP_FULL_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => C_NUM_XIP_SPI_REGS -- 0 CEs required for XIP Full interface
);
---------------------------------------------------------------------------------
constant C_XIP_FIFO_DEPTH : integer := 264;
-------------------------------------------------------------------------------
-- signal declaration
signal bus2ip_clk : std_logic;
signal bus2ip_be_int : std_logic_vector
(((C_S_AXI_DATA_WIDTH/8)-1)downto 0);
signal bus2ip_rdce_int : std_logic_vector
((C_NUM_CE_SIGNALS-1)downto 0);
signal bus2ip_wrce_int : std_logic_vector
((C_NUM_CE_SIGNALS-1)downto 0);
signal bus2ip_data_int : std_logic_vector
((C_S_AXI_DATA_WIDTH-1)downto 0);
signal ip2bus_data_int : std_logic_vector
((C_S_AXI_DATA_WIDTH-1)downto 0 )
:= (others => '0');
signal ip2bus_wrack_int : std_logic := '0';
signal ip2bus_rdack_int : std_logic := '0';
signal ip2bus_error_int : std_logic := '0';
signal bus2ip_reset_int : std_logic;
signal bus2ip_reset_ipif_inverted: std_logic;
-- XIP signals
signal bus2ip_xip_rdce_int: std_logic_vector(0 to C_NUM_XIP_CE_SIGNALS-1);
signal bus2ip_xip_wrce_int: std_logic_vector(0 to C_NUM_XIP_CE_SIGNALS-1);
signal io0_i_sync : std_logic;
signal io1_i_sync : std_logic;
signal io2_i_sync : std_logic;
signal io3_i_sync : std_logic;
signal burst_tr_int : std_logic;
signal rready_int : std_logic;
signal bus2ip_reset_ipif4_inverted : std_logic;
-- attribute IOB : string;
-- attribute IOB of IO0_I_REG : label is "true";
-- attribute IOB of IO1_I_REG : label is "true";
-- attribute IOB of IO2_I_REG : label is "true";
-- attribute IOB of IO3_I_REG : label is "true";
-----
begin
-----
IO0_I_REG: component FD
generic map
(
INIT => '0'
)
port map
(
Q => io0_i_sync,
C => ext_spi_clk,
D => io0_i --MOSI_I
);
IO1_I_REG: component FD
generic map
(
INIT => '0'
)
port map
(
Q => io1_i_sync,
C => ext_spi_clk,
D => io1_i -- MISO_I
);
IO2_I_REG: component FD
generic map
(
INIT => '0'
)
port map
(
Q => io2_i_sync,
C => ext_spi_clk,
D => io2_i
);
-----------------------
IO3_I_REG: component FD
generic map
(
INIT => '0'
)
port map
(
Q => io3_i_sync,
C => ext_spi_clk,
D => io3_i
);
-----------------------
-------------------------------------------------------------------------------
---------------
-- AXI_QUAD_SPI_LEGACY_MODE: This logic is legacy AXI4 Lite interface based design
---------------
QSPI_LEGACY_MD_GEN : if C_TYPE_OF_AXI4_INTERFACE = 0 generate
---------------
begin
-----
AXI_LITE_IPIF_I : entity axi_lite_ipif_v3_0.axi_lite_ipif
generic map
(
----------------------------------------------------
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH ,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
----------------------------------------------------
C_S_AXI_MIN_SIZE => C_S_AXI_SPI_MIN_SIZE ,
C_USE_WSTRB => C_USE_WSTRB ,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT ,
----------------------------------------------------
C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY ,
C_FAMILY => C_FAMILY
----------------------------------------------------
)
port map
(
---------------------------------------------------------
S_AXI_ACLK => s_axi_aclk, -- in
S_AXI_ARESETN => s_axi_aresetn, -- in
---------------------------------------------------------
S_AXI_AWADDR => s_axi_awaddr, -- in
S_AXI_AWVALID => s_axi_awvalid, -- in
S_AXI_AWREADY => s_axi_awready, -- out
S_AXI_WDATA => s_axi_wdata, -- in
S_AXI_WSTRB => s_axi_wstrb, -- in
S_AXI_WVALID => s_axi_wvalid, -- in
S_AXI_WREADY => s_axi_wready, -- out
S_AXI_BRESP => s_axi_bresp, -- out
S_AXI_BVALID => s_axi_bvalid, -- out
S_AXI_BREADY => s_axi_bready, -- in
S_AXI_ARADDR => s_axi_araddr, -- in
S_AXI_ARVALID => s_axi_arvalid, -- in
S_AXI_ARREADY => s_axi_arready, -- out
S_AXI_RDATA => s_axi_rdata, -- out
S_AXI_RRESP => s_axi_rresp, -- out
S_AXI_RVALID => s_axi_rvalid, -- out
S_AXI_RREADY => s_axi_rready, -- in
----------------------------------------------------------
-- IP Interconnect (IPIC) port signals
Bus2IP_Clk => bus2ip_clk, -- out
Bus2IP_Resetn => bus2ip_reset_int, -- out
----------------------------------------------------------
Bus2IP_Addr => open, -- out -- not used signal
Bus2IP_RNW => open, -- out
Bus2IP_BE => bus2ip_be_int, -- out
Bus2IP_CS => open, -- out -- not used signal
Bus2IP_RdCE => bus2ip_rdce_int, -- out -- little endian
Bus2IP_WrCE => bus2ip_wrce_int, -- out -- little endian
Bus2IP_Data => bus2ip_data_int, -- out -- little endian
----------------------------------------------------------
IP2Bus_Data => ip2bus_data_int, -- in -- little endian
IP2Bus_WrAck => ip2bus_wrack_int, -- in
IP2Bus_RdAck => ip2bus_rdack_int, -- in
IP2Bus_Error => ip2bus_error_int -- in
----------------------------------------------------------
);
----------------------
--REG_RST_FRM_IPIF: convert active low to active hig reset to rest of
-- the core.
----------------------
REG_RST_FRM_IPIF: process (S_AXI_ACLK) is
begin
if(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
bus2ip_reset_ipif_inverted <= not(bus2ip_reset_int);
end if;
end process REG_RST_FRM_IPIF;
-- ----------------------------------------------------------------------
-- -- Instansiating the SPI core
-- ----------------------------------------------------------------------
QSPI_CORE_INTERFACE_I : entity axi_quad_spi_v3_2.qspi_core_interface
generic map
(
------------------------------------------------
-- AXI parameters
C_FAMILY => C_FAMILY ,
Async_Clk => Async_Clk ,
C_SUB_FAMILY => C_FAMILY ,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
------------------------------------------------
-- local constants
C_NUM_CE_SIGNALS => C_NUM_CE_SIGNALS ,
------------------------------------------------
-- SPI parameters
--C_AXI4_CLK_PS => C_AXI4_CLK_PS ,
--C_EXT_SPI_CLK_PS => C_EXT_SPI_CLK_PS ,
C_FIFO_DEPTH => C_FIFO_DEPTH_UPDATED ,
C_SCK_RATIO => C_SCK_RATIO ,
C_NUM_SS_BITS => C_NUM_SS_BITS ,
C_NUM_TRANSFER_BITS => C_NUM_TRANSFER_BITS,
C_SPI_MODE => C_SPI_MODE ,
C_USE_STARTUP => C_USE_STARTUP ,
C_SPI_MEMORY => C_SPI_MEMORY ,
C_TYPE_OF_AXI4_INTERFACE => C_TYPE_OF_AXI4_INTERFACE,
------------------------------------------------
-- local constants
C_FIFO_EXIST => C_FIFO_EXIST ,
C_SPI_NUM_BITS_REG => C_SPI_NUM_BITS_REG,
C_OCCUPANCY_NUM_BITS => C_OCCUPANCY_NUM_BITS,
------------------------------------------------
-- local constants
C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY,
------------------------------------------------
-- local constants
C_SPICR_REG_WIDTH => C_SPICR_REG_WIDTH ,
C_SPISR_REG_WIDTH => C_SPISR_REG_WIDTH
)
port map
(
EXT_SPI_CLK => ext_spi_clk, -- in
---------------------------------------------------
-- IP Interconnect (IPIC) port signals
Bus2IP_Clk => bus2ip_clk, -- in
Bus2IP_Reset => bus2ip_reset_ipif_inverted, -- in
---------------------------------------------------
Bus2IP_BE => bus2ip_be_int, -- in vector
-- Bus2IP_CS => bus2ip_cs_int,
Bus2IP_RdCE => bus2ip_rdce_int, -- in vector
Bus2IP_WrCE => bus2ip_wrce_int, -- in vector
Bus2IP_Data => bus2ip_data_int, -- in vector
---------------------------------------------------
IP2Bus_Data => ip2bus_data_int, -- out vector
IP2Bus_WrAck => ip2bus_wrack_int, -- out
IP2Bus_RdAck => ip2bus_rdack_int, -- out
IP2Bus_Error => ip2bus_error_int, -- out
---------------------------------------------------
burst_tr => burst_tr_int,
rready => '0',
WVALID => '0',
---------------------------------------------------
--SPI Ports
IO0_I => io0_i_sync,-- mosi
IO0_O => io0_o,
IO0_T => io0_t,
-----
IO1_I => io1_i_sync,-- miso
IO1_O => io1_o,
IO1_T => io1_t,
-----
IO2_I => io2_i_sync,
IO2_O => io2_o,
IO2_T => io2_t,
-----
IO3_I => io3_i_sync,
IO3_O => io3_o,
IO3_T => io3_t,
-----
SCK_I => sck_i,
SCK_O => sck_o,
SCK_T => sck_t,
-----
SPISEL => spisel,
-----
SS_I => ss_i,
SS_O => ss_o,
SS_T => ss_t,
-----
IP2INTC_Irpt => ip2intc_irpt,
CFGCLK => cfgclk, -- FGCLK , -- 1-bit output: Configuration main clock output
CFGMCLK => cfgmclk, -- FGMCLK , -- 1-bit output: Configuration internal oscillator clock output
EOS => eos, -- OS , -- 1-bit output: Active high output signal indicating the End Of Startup.
PREQ => preq, -- REQ , -- 1-bit output: PROGRAM request to fabric output
DI => di -- output
-----
);
burst_tr_int <= '0';
end generate QSPI_LEGACY_MD_GEN;
------------------------------------------------------------------------------
QSPI_ENHANCED_MD_GEN: if C_TYPE_OF_AXI4_INTERFACE = 1 and C_XIP_MODE = 0 generate
---------------
begin
-----
-- AXI_QUAD_SPI_I: core instance
QSPI_ENHANCED_MD_IPIF_I : entity axi_quad_spi_v3_2.axi_qspi_enhanced_mode
generic map(
-- General Parameters
C_FAMILY => C_FAMILY , -- : string := "virtex7";
C_SUB_FAMILY => C_FAMILY , -- : string := "virtex7";
-------------------------
--C_TYPE_OF_AXI4_INTERFACE => C_TYPE_OF_AXI4_INTERFACE, -- : integer range 0 to 1 := 0;--default AXI4 Lite Legacy mode
--C_XIP_MODE => C_XIP_MODE , -- : integer range 0 to 1 := 0;--default NON XIP Mode
--C_AXI4_CLK_PS => C_AXI4_CLK_PS , -- : integer := 10000;--AXI clock period
--C_EXT_SPI_CLK_PS => C_EXT_SPI_CLK_PS , -- : integer := 10000;--ext clock period
C_FIFO_DEPTH => C_FIFO_DEPTH_UPDATED , -- : integer := 16;-- allowed 0,16,256.
C_SCK_RATIO => C_SCK_RATIO , -- : integer := 16;--default in legacy mode
C_NUM_SS_BITS => C_NUM_SS_BITS , -- : integer range 1 to 32:= 1;
C_NUM_TRANSFER_BITS => C_NUM_TRANSFER_BITS , -- : integer := 8; -- allowed 8, 16, 32
-------------------------
C_SPI_MODE => C_SPI_MODE , -- : integer range 0 to 2 := 0; -- used for differentiating
C_USE_STARTUP => C_USE_STARTUP , -- : integer range 0 to 1 := 1; --
C_SPI_MEMORY => C_SPI_MEMORY , -- : integer range 0 to 2 := 1; -- 0 - mixed mode,
-------------------------
-- AXI4 Full Interface Parameters
C_S_AXI4_ADDR_WIDTH => C_S_AXI4_ADDR_WIDTH , -- : integer range 32 to 32 := 32;
C_S_AXI4_DATA_WIDTH => C_S_AXI4_DATA_WIDTH , -- : integer range 32 to 32 := 32;
C_S_AXI4_ID_WIDTH => C_S_AXI4_ID_WIDTH , -- : integer range 1 to 16 := 4;
-------------------------
--*C_AXI4_BASEADDR => C_S_AXI4_BASEADDR , -- : std_logic_vector := x"FFFFFFFF";
--*C_AXI4_HIGHADDR => C_S_AXI4_HIGHADDR , -- : std_logic_vector := x"00000000"
-------------------------
C_S_AXI_SPI_MIN_SIZE => C_S_AXI_SPI_MIN_SIZE ,
-------------------------
C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY_AXI4_FULL ,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY ,
C_SPI_MEM_ADDR_BITS => C_SPI_MEM_ADDR_BITS -- newly added
)
port map(
-- external async clock for SPI interface logic
EXT_SPI_CLK => ext_spi_clk , -- : in std_logic;
-----------------------------------
S_AXI4_ACLK => s_axi4_aclk , -- : in std_logic;
S_AXI4_ARESETN => s_axi4_aresetn , -- : in std_logic;
-------------------------------
-------------------------------
--*AXI4 Full port interface* --
-------------------------------
------------------------------------
-- AXI Write Address channel signals
------------------------------------
S_AXI4_AWID => s_axi4_awid , -- : in std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_AWADDR => s_axi4_awaddr , -- : in std_logic_vector((C_S_AXI4_ADDR_WIDTH-1) downto 0);
S_AXI4_AWLEN => s_axi4_awlen , -- : in std_logic_vector(7 downto 0);
S_AXI4_AWSIZE => s_axi4_awsize , -- : in std_logic_vector(2 downto 0);
S_AXI4_AWBURST => s_axi4_awburst, -- : in std_logic_vector(1 downto 0);
S_AXI4_AWLOCK => s_axi4_awlock , -- : in std_logic; -- not supported in design
S_AXI4_AWCACHE => s_axi4_awcache, -- : in std_logic_vector(3 downto 0);-- not supported in design
S_AXI4_AWPROT => s_axi4_awprot , -- : in std_logic_vector(2 downto 0);-- not supported in design
S_AXI4_AWVALID => s_axi4_awvalid, -- : in std_logic;
S_AXI4_AWREADY => s_axi4_awready, -- : out std_logic;
---------------------------------------
-- AXI4 Full Write data channel signals
---------------------------------------
S_AXI4_WDATA => s_axi4_wdata , -- : in std_logic_vector((C_S_AXI4_DATA_WIDTH-1)downto 0);
S_AXI4_WSTRB => s_axi4_wstrb , -- : in std_logic_vector(((C_S_AXI4_DATA_WIDTH/8)-1) downto 0);
S_AXI4_WLAST => s_axi4_wlast , -- : in std_logic;
S_AXI4_WVALID => s_axi4_wvalid, -- : in std_logic;
S_AXI4_WREADY => s_axi4_wready, -- : out std_logic;
-------------------------------------------
-- AXI4 Full Write response channel Signals
-------------------------------------------
S_AXI4_BID => s_axi4_bid , -- : out std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_BRESP => s_axi4_bresp , -- : out std_logic_vector(1 downto 0);
S_AXI4_BVALID => s_axi4_bvalid, -- : out std_logic;
S_AXI4_BREADY => s_axi4_bready, -- : in std_logic;
-----------------------------------
-- AXI Read Address channel signals
-----------------------------------
S_AXI4_ARID => s_axi4_arid , -- : in std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_ARADDR => s_axi4_araddr , -- : in std_logic_vector((C_S_AXI4_ADDR_WIDTH-1) downto 0);
S_AXI4_ARLEN => s_axi4_arlen , -- : in std_logic_vector(7 downto 0);
S_AXI4_ARSIZE => s_axi4_arsize , -- : in std_logic_vector(2 downto 0);
S_AXI4_ARBURST => s_axi4_arburst, -- : in std_logic_vector(1 downto 0);
S_AXI4_ARLOCK => s_axi4_arlock , -- : in std_logic; -- not supported in design
S_AXI4_ARCACHE => s_axi4_arcache, -- : in std_logic_vector(3 downto 0);-- not supported in design
S_AXI4_ARPROT => s_axi4_arprot , -- : in std_logic_vector(2 downto 0);-- not supported in design
S_AXI4_ARVALID => s_axi4_arvalid, -- : in std_logic;
S_AXI4_ARREADY => s_axi4_arready, -- : out std_logic;
--------------------------------
-- AXI Read Data Channel signals
--------------------------------
S_AXI4_RID => s_axi4_rid , -- : out std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_RDATA => s_axi4_rdata , -- : out std_logic_vector((C_S_AXI4_DATA_WIDTH-1) downto 0);
S_AXI4_RRESP => s_axi4_rresp , -- : out std_logic_vector(1 downto 0);
S_AXI4_RLAST => s_axi4_rlast , -- : out std_logic;
S_AXI4_RVALID => s_axi4_rvalid, -- : out std_logic;
S_AXI4_RREADY => s_axi4_rready, -- : in std_logic;
----------------------------------------------------------
-- IP Interconnect (IPIC) port signals
Bus2IP_Clk => bus2ip_clk, -- out
Bus2IP_Reset => bus2ip_reset_ipif_inverted , -- out
----------------------------------------------------------
-- Bus2IP_Addr => open, -- out -- not used signal
Bus2IP_RNW => open, -- out
Bus2IP_BE => bus2ip_be_int, -- out
Bus2IP_CS => open, -- out -- not used signal
Bus2IP_RdCE => bus2ip_rdce_int, -- out -- little endian
Bus2IP_WrCE => bus2ip_wrce_int, -- out -- little endian
Bus2IP_Data => bus2ip_data_int, -- out -- little endian
----------------------------------------------------------
IP2Bus_Data => ip2bus_data_int, -- in -- little endian
IP2Bus_WrAck => ip2bus_wrack_int, -- in
IP2Bus_RdAck => ip2bus_rdack_int, -- in
IP2Bus_Error => ip2bus_error_int, -- in
----------------------------------------------------------
burst_tr => burst_tr_int, -- in
rready => rready_int
);
-- ----------------------------------------------------------------------
-- -- Instansiating the SPI core
-- ----------------------------------------------------------------------
QSPI_CORE_INTERFACE_I : entity axi_quad_spi_v3_2.qspi_core_interface
generic map
(
------------------------------------------------
-- AXI parameters
C_FAMILY => C_FAMILY ,
Async_Clk => Async_Clk ,
C_SUB_FAMILY => C_FAMILY ,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
------------------------------------------------
-- local constants
C_NUM_CE_SIGNALS => C_NUM_CE_SIGNALS ,
------------------------------------------------
-- SPI parameters
--C_AXI4_CLK_PS => C_AXI4_CLK_PS ,
--C_EXT_SPI_CLK_PS => C_EXT_SPI_CLK_PS ,
C_FIFO_DEPTH => C_FIFO_DEPTH_UPDATED ,
C_SCK_RATIO => C_SCK_RATIO ,
C_NUM_SS_BITS => C_NUM_SS_BITS ,
C_NUM_TRANSFER_BITS => C_NUM_TRANSFER_BITS,
C_SPI_MODE => C_SPI_MODE ,
C_USE_STARTUP => C_USE_STARTUP ,
C_SPI_MEMORY => C_SPI_MEMORY ,
C_TYPE_OF_AXI4_INTERFACE => C_TYPE_OF_AXI4_INTERFACE,
------------------------------------------------
-- local constants
C_FIFO_EXIST => C_FIFO_EXIST ,
C_SPI_NUM_BITS_REG => C_SPI_NUM_BITS_REG,
C_OCCUPANCY_NUM_BITS => C_OCCUPANCY_NUM_BITS,
------------------------------------------------
-- local constants
C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY,
------------------------------------------------
-- local constants
C_SPICR_REG_WIDTH => C_SPICR_REG_WIDTH ,
C_SPISR_REG_WIDTH => C_SPISR_REG_WIDTH
)
port map
(
EXT_SPI_CLK => EXT_SPI_CLK, -- in
---------------------------------------------------
-- IP Interconnect (IPIC) port signals
Bus2IP_Clk => bus2ip_clk, -- in
Bus2IP_Reset => bus2ip_reset_ipif_inverted, -- in
---------------------------------------------------
Bus2IP_BE => bus2ip_be_int, -- in vector
-- Bus2IP_CS => bus2ip_cs_int,
Bus2IP_RdCE => bus2ip_rdce_int, -- in vector
Bus2IP_WrCE => bus2ip_wrce_int, -- in vector
Bus2IP_Data => bus2ip_data_int, -- in vector
---------------------------------------------------
IP2Bus_Data => ip2bus_data_int, -- out vector
IP2Bus_WrAck => ip2bus_wrack_int, -- out
IP2Bus_RdAck => ip2bus_rdack_int, -- out
IP2Bus_Error => ip2bus_error_int, -- out
---------------------------------------------------
burst_tr => burst_tr_int,
rready => rready_int,
WVALID => S_AXI4_WVALID,
--SPI Ports
IO0_I => io0_i_sync,-- mosi
IO0_O => io0_o,
IO0_T => io0_t,
-----
IO1_I => io1_i_sync,-- miso
IO1_O => io1_o,
IO1_T => io1_t,
-----
IO2_I => io2_i_sync,
IO2_O => io2_o,
IO2_T => io2_t,
-----
IO3_I => io3_i_sync,
IO3_O => io3_o,
IO3_T => io3_t,
-----
SCK_I => sck_i,
SCK_O => sck_o,
SCK_T => sck_t,
-----
SPISEL => spisel,
-----
SS_I => ss_i,
SS_O => ss_o,
SS_T => ss_t,
-----
IP2INTC_Irpt => ip2intc_irpt,
CFGCLK => cfgclk, -- FGCLK , -- 1-bit output: Configuration main clock output
CFGMCLK => cfgmclk, -- FGMCLK , -- 1-bit output: Configuration internal oscillator clock output
EOS => eos, -- OS , -- 1-bit output: Active high output signal indicating the End Of Startup.
PREQ => preq, -- REQ , -- 1-bit output: PROGRAM request to fabric output
DI => di -- output
-----
);
end generate QSPI_ENHANCED_MD_GEN;
--------------------------------------------------------------------------------
-----------------
-- XIP_MODE: This logic is used in XIP mode where AXI4 Lite & AXI4 Full interface
-- used in the design
---------------
XIP_MODE_GEN : if C_TYPE_OF_AXI4_INTERFACE = 1 and C_XIP_MODE = 1 generate
---------------
constant XIPCR : natural := 0; -- at address C_BASEADDR + 60 h
constant XIPSR : natural := 1;
--
signal bus2ip_reset_int : std_logic;
signal bus2ip_clk_int : std_logic;
signal bus2ip_data_int : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal ip2bus_data_int : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal ip2bus_wrack_int : std_logic;
signal ip2bus_rdack_int : std_logic;
signal ip2bus_error_int : std_logic;
signal bus2ip_reset_ipif_inverted: std_logic;
signal IP2Bus_XIPCR_WrAck : std_logic;
signal IP2Bus_XIPCR_RdAck : std_logic;
signal XIPCR_1_CPOL_int : std_logic;
signal XIPCR_0_CPHA_int : std_logic;
signal IP2Bus_XIPCR_Data_int : std_logic_vector((C_XIP_SPICR_REG_WIDTH-1) downto 0);
signal IP2Bus_XIPSR_Data_int : std_logic_vector((C_XIP_SPISR_REG_WIDTH-1) downto 0);
signal TO_XIPSR_AXI_TR_ERR_int : std_logic;
signal TO_XIPSR_mst_modf_err_int : std_logic;
signal TO_XIPSR_axi_rx_full_int : std_logic;
signal TO_XIPSR_axi_rx_empty_int : std_logic;
signal xipsr_cpha_cpol_err_int :std_logic;
signal xipsr_cmd_err_int :std_logic;
signal ip2bus_xipsr_wrack :std_logic;
signal ip2bus_xipsr_rdack :std_logic;
signal xipsr_axi_tr_err_int :std_logic;
signal xipsr_axi_tr_done_int :std_logic;
signal ip2bus_xipsr_rdack_int :std_logic;
signal ip2bus_xipsr_wrack_int :std_logic;
signal MISO_I_int :std_logic;
signal SCK_O_int :std_logic;
signal TO_XIPSR_trans_error_int :std_logic;
signal TO_XIPSR_CPHA_CPOL_ERR_int :std_logic;
signal ip2bus_wrack_core_reg_d1 :std_logic;
signal ip2bus_wrack_core_reg :std_logic;
signal ip2bus_rdack_core_reg_d1 :std_logic;
signal ip2bus_rdack_core_reg_d2 :std_logic;
signal ip2Bus_RdAck_core_reg_d3 :std_logic;
signal Rst_to_spi_int :std_logic;
begin
-----
---- AXI4 Lite interface instance and interface with the port list
AXI_LITE_IPIF_I : entity axi_lite_ipif_v3_0.axi_lite_ipif
generic map
(
----------------------------------------------------
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH ,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
----------------------------------------------------
C_S_AXI_MIN_SIZE => C_S_AXI_SPI_MIN_SIZE ,
C_USE_WSTRB => C_USE_WSTRB ,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT ,
----------------------------------------------------
C_ARD_ADDR_RANGE_ARRAY => C_XIP_LITE_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_XIP_LITE_ARD_NUM_CE_ARRAY ,
C_FAMILY => C_FAMILY
----------------------------------------------------
)
port map
( -- AXI4 Lite interface
---------------------------------------------------------
S_AXI_ACLK => s_axi_aclk, -- in
S_AXI_ARESETN => s_axi_aresetn, -- in
---------------------------------------------------------
S_AXI_AWADDR => s_axi_awaddr, -- in
S_AXI_AWVALID => s_axi_awvalid, -- in
S_AXI_AWREADY => s_axi_awready, -- out
S_AXI_WDATA => s_axi_wdata, -- in
S_AXI_WSTRB => s_axi_wstrb, -- in
S_AXI_WVALID => s_axi_wvalid, -- in
S_AXI_WREADY => s_axi_wready, -- out
S_AXI_BRESP => s_axi_bresp, -- out
S_AXI_BVALID => s_axi_bvalid, -- out
S_AXI_BREADY => s_axi_bready, -- in
S_AXI_ARADDR => s_axi_araddr, -- in
S_AXI_ARVALID => s_axi_arvalid, -- in
S_AXI_ARREADY => s_axi_arready, -- out
S_AXI_RDATA => s_axi_rdata, -- out
S_AXI_RRESP => s_axi_rresp, -- out
S_AXI_RVALID => s_axi_rvalid, -- out
S_AXI_RREADY => s_axi_rready, -- in
----------------------------------------------------------
-- IP Interconnect (IPIC) port signals
Bus2IP_Clk => bus2ip_clk_int , -- out
Bus2IP_Resetn => bus2ip_reset_int, -- out
----------------------------------------------------------
Bus2IP_Addr => open, -- out -- not used signal
Bus2IP_RNW => open, -- out
Bus2IP_BE => open, -- bus2ip_be_int, -- out
Bus2IP_CS => open, -- out -- not used signal
Bus2IP_RdCE => bus2ip_xip_rdce_int, -- out -- little endian
Bus2IP_WrCE => bus2ip_xip_wrce_int, -- out -- little endian
Bus2IP_Data => bus2ip_data_int, -- out -- little endian
----------------------------------------------------------
IP2Bus_Data => ip2bus_data_int, -- in -- little endian
IP2Bus_WrAck => ip2bus_wrack_int, -- in
IP2Bus_RdAck => ip2bus_rdack_int, -- in
IP2Bus_Error => ip2bus_error_int -- in
----------------------------------------------------------
);
--------------------------------------------------------------------------
ip2bus_error_int <= '0'; -- there is no error in this mode
----------------------
--REG_RST_FRM_IPIF: convert active low to active hig reset to rest of
-- the core.
----------------------
REG_RST_FRM_IPIF: process (S_AXI_ACLK) is
begin
if(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
bus2ip_reset_ipif_inverted <= not(S_AXI_ARESETN);
end if;
end process REG_RST_FRM_IPIF;
--------------------------------------------------------------------------
XIP_CR_I : entity axi_quad_spi_v3_2.xip_cntrl_reg
generic map
(
C_XIP_SPICR_REG_WIDTH => C_XIP_SPICR_REG_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
C_SPI_MODE => C_SPI_MODE
)
port map(
Bus2IP_Clk => S_AXI_ACLK, -- : in std_logic;
Soft_Reset_op => bus2ip_reset_ipif_inverted, -- : in std_logic;
------------------------
Bus2IP_XIPCR_WrCE => bus2ip_xip_wrce_int(XIPCR), -- : in std_logic;
Bus2IP_XIPCR_RdCE => bus2ip_xip_rdce_int(XIPCR), -- : in std_logic;
Bus2IP_XIPCR_data => bus2ip_data_int , -- : in std_logic_vector(0 to (C_S_AXI_DATA_WIDTH-1));
------------------------
ip2Bus_RdAck_core => ip2Bus_RdAck_core_reg_d2, -- IP2Bus_XIPCR_WrAck,
ip2Bus_WrAck_core => ip2Bus_WrAck_core_reg, -- IP2Bus_XIPCR_RdAck,
------------------------
--XIPCR_7_0_CMD => XIPCR_7_0_CMD, -- out std_logic_vector;
XIPCR_1_CPOL => XIPCR_1_CPOL_int , -- out std_logic;
XIPCR_0_CPHA => XIPCR_0_CPHA_int , -- out std_logic;
------------------------
IP2Bus_XIPCR_Data => IP2Bus_XIPCR_Data_int, -- out std_logic;
------------------------
TO_XIPSR_CPHA_CPOL_ERR=> TO_XIPSR_CPHA_CPOL_ERR_int -- out std_logic
);
--------------------------------------------------------------------------
REG_WR_ACK_P:process(S_AXI_ACLK)is
begin
-----
if(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if(bus2ip_reset_ipif_inverted = '1')then
ip2Bus_WrAck_core_reg_d1 <= '0';
ip2Bus_WrAck_core_reg <= '0';
else
ip2Bus_WrAck_core_reg_d1 <= bus2ip_xip_wrce_int(XIPCR) or
bus2ip_xip_wrce_int(XIPSR);
ip2Bus_WrAck_core_reg <= (bus2ip_xip_wrce_int(XIPCR) or
bus2ip_xip_wrce_int(XIPSR)) and
(not ip2Bus_WrAck_core_reg_d1);
end if;
end if;
end process REG_WR_ACK_P;
-------------------------
ip2bus_wrack_int <= ip2Bus_WrAck_core_reg;
-------------------------
REG_RD_ACK_P:process(S_AXI_ACLK)is
begin
-----
if(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if(bus2ip_reset_ipif_inverted = '1')then
ip2Bus_RdAck_core_reg_d1 <= '0';
ip2Bus_RdAck_core_reg_d2 <= '0';
ip2Bus_RdAck_core_reg_d3 <= '0';
else
ip2Bus_RdAck_core_reg_d1 <= bus2ip_xip_rdce_int(XIPCR) or
bus2ip_xip_rdce_int(XIPSR);
ip2Bus_RdAck_core_reg_d2 <= (bus2ip_xip_rdce_int(XIPCR) or
bus2ip_xip_rdce_int(XIPSR)) and
(not ip2Bus_RdAck_core_reg_d1);
ip2Bus_RdAck_core_reg_d3 <= ip2Bus_RdAck_core_reg_d2;
end if;
end if;
end process REG_RD_ACK_P;
-------------------------
ip2bus_rdack_int <= ip2Bus_RdAck_core_reg_d3;
-------------------------
REG_IP2BUS_DATA_P:process(S_AXI_ACLK)is
begin
-----
if(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if(bus2ip_reset_ipif_inverted = '1')then
ip2bus_data_int <= (others => '0');
elsif(ip2Bus_RdAck_core_reg_d2 = '1') then
ip2bus_data_int <= ("000000000000000000000000000000" & IP2Bus_XIPCR_Data_int) or
("000000000000000000000000000" & IP2Bus_XIPSR_Data_int);
end if;
end if;
end process REG_IP2BUS_DATA_P;
-------------------------
--------------------------------------------------------------------------
XIP_SR_I : entity axi_quad_spi_v3_2.xip_status_reg
generic map
(
C_XIP_SPISR_REG_WIDTH => C_XIP_SPISR_REG_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH
)
port map(
Bus2IP_Clk => S_AXI_ACLK, -- : in std_logic;
Soft_Reset_op => bus2ip_reset_ipif_inverted, -- : in std_logic;
------------------------
XIPSR_AXI_TR_ERR => TO_XIPSR_AXI_TR_ERR_int, -- : in std_logic;
XIPSR_CPHA_CPOL_ERR => TO_XIPSR_CPHA_CPOL_ERR_int, -- : in std_logic;
XIPSR_MST_MODF_ERR => TO_XIPSR_mst_modf_err_int, -- : in std_logic;
XIPSR_AXI_RX_FULL => TO_XIPSR_axi_rx_full_int, -- : in std_logic;
XIPSR_AXI_RX_EMPTY => TO_XIPSR_axi_rx_empty_int, -- : in std_logic;
------------------------
Bus2IP_XIPSR_WrCE => bus2ip_xip_wrce_int(XIPSR),
Bus2IP_XIPSR_RdCE => bus2ip_xip_rdce_int(XIPSR),
-------------------
IP2Bus_XIPSR_Data => IP2Bus_XIPSR_Data_int ,
ip2Bus_RdAck => ip2Bus_RdAck_core_reg_d3
);
---------------------------------------------------------------------------
--REG_RST4_FRM_IPIF: convert active low to active hig reset to rest of
-- the core.
----------------------
REG_RST4_FRM_IPIF: process (S_AXI4_ACLK) is
begin
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
bus2ip_reset_ipif4_inverted <= not(S_AXI4_ARESETN);
end if;
end process REG_RST4_FRM_IPIF;
-------------------------------------------------------------------------
RESET_SYNC_AXI_SPI_CLK_INST:entity axi_quad_spi_v3_2.reset_sync_module
port map(
EXT_SPI_CLK => EXT_SPI_CLK ,-- in std_logic;
Soft_Reset_frm_axi => bus2ip_reset_ipif4_inverted ,-- in std_logic;
Rst_to_spi => Rst_to_spi_int -- out std_logic;
);
--------------------------------------------------------------------------
AXI_QSPI_XIP_I : entity axi_quad_spi_v3_2.axi_qspi_xip_if
generic map
(
C_FAMILY => C_FAMILY ,
Async_Clk => Async_Clk ,
C_SUB_FAMILY => C_FAMILY ,
-------------------------
--C_TYPE_OF_AXI4_INTERFACE => C_TYPE_OF_AXI4_INTERFACE,
--C_XIP_MODE => C_XIP_MODE ,
--C_AXI4_CLK_PS => C_AXI4_CLK_PS ,
--C_EXT_SPI_CLK_PS => C_EXT_SPI_CLK_PS ,
--C_FIFO_DEPTH => C_FIFO_DEPTH_UPDATED ,
C_SPI_MEM_ADDR_BITS => C_SPI_MEM_ADDR_BITS ,
C_SCK_RATIO => C_SCK_RATIO ,
C_NUM_SS_BITS => C_NUM_SS_BITS ,
C_NUM_TRANSFER_BITS => C_NUM_TRANSFER_BITS ,
-------------------------
C_SPI_MODE => C_SPI_MODE ,
C_USE_STARTUP => C_USE_STARTUP ,
C_SPI_MEMORY => C_SPI_MEMORY ,
-------------------------
-- AXI4 Full Interface Parameters
C_S_AXI4_ADDR_WIDTH => C_S_AXI4_ADDR_WIDTH ,
C_S_AXI4_DATA_WIDTH => C_S_AXI4_DATA_WIDTH ,
C_S_AXI4_ID_WIDTH => C_S_AXI4_ID_WIDTH ,
-------------------------
--*C_AXI4_BASEADDR => C_S_AXI4_BASEADDR ,
--*C_AXI4_HIGHADDR => C_S_AXI4_HIGHADDR ,
-------------------------
--C_XIP_SPICR_REG_WIDTH => C_XIP_SPICR_REG_WIDTH ,
--C_XIP_SPISR_REG_WIDTH => C_XIP_SPISR_REG_WIDTH ,
-------------------------
C_XIP_FULL_ARD_ADDR_RANGE_ARRAY => C_XIP_FULL_ARD_ADDR_RANGE_ARRAY,
C_XIP_FULL_ARD_NUM_CE_ARRAY => C_XIP_FULL_ARD_NUM_CE_ARRAY
)
port map
(
-- external async clock for SPI interface logic
EXT_SPI_CLK => ext_spi_clk , -- : in std_logic;
Rst_to_spi => Rst_to_spi_int,
----------------------------------
S_AXI_ACLK => s_axi_aclk , -- : in std_logic;
S_AXI_ARESETN => bus2ip_reset_ipif_inverted, -- : in std_logic;
----------------------------------
S_AXI4_ACLK => s_axi4_aclk , -- : in std_logic;
S_AXI4_ARESET => bus2ip_reset_ipif4_inverted, -- : in std_logic;
-------------------------------
--*AXI4 Full port interface* --
-------------------------------
------------------------------------
-- AXI Write Address Channel Signals
------------------------------------
S_AXI4_AWID => s_axi4_awid , -- : in std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_AWADDR => s_axi4_awaddr , -- : in std_logic_vector((C_S_AXI4_ADDR_WIDTH-1) downto 0);
S_AXI4_AWLEN => s_axi4_awlen , -- : in std_logic_vector(7 downto 0);
S_AXI4_AWSIZE => s_axi4_awsize , -- : in std_logic_vector(2 downto 0);
S_AXI4_AWBURST => s_axi4_awburst, -- : in std_logic_vector(1 downto 0);
S_AXI4_AWLOCK => s_axi4_awlock , -- : in std_logic; -- not supported in design
S_AXI4_AWCACHE => s_axi4_awcache, -- : in std_logic_vector(3 downto 0);-- not supported in design
S_AXI4_AWPROT => s_axi4_awprot , -- : in std_logic_vector(2 downto 0);-- not supported in design
S_AXI4_AWVALID => s_axi4_awvalid, -- : in std_logic;
S_AXI4_AWREADY => s_axi4_awready, -- : out std_logic;
---------------------------------------
-- AXI4 Full Write data channel Signals
---------------------------------------
S_AXI4_WDATA => s_axi4_wdata , -- : in std_logic_vector((C_S_AXI4_DATA_WIDTH-1)downto 0);
S_AXI4_WSTRB => s_axi4_wstrb , -- : in std_logic_vector(((C_S_AXI4_DATA_WIDTH/8)-1) downto 0);
S_AXI4_WLAST => s_axi4_wlast , -- : in std_logic;
S_AXI4_WVALID => s_axi4_wvalid , -- : in std_logic;
S_AXI4_WREADY => s_axi4_wready , -- : out std_logic;
-------------------------------------------
-- AXI4 Full Write response channel Signals
-------------------------------------------
S_AXI4_BID => s_axi4_bid , -- : out std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_BRESP => s_axi4_bresp , -- : out std_logic_vector(1 downto 0);
S_AXI4_BVALID => s_axi4_bvalid , -- : out std_logic;
S_AXI4_BREADY => s_axi4_bready , -- : in std_logic;
-----------------------------------
-- AXI Read Address channel signals
-----------------------------------
S_AXI4_ARID => s_axi4_arid , -- : in std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_ARADDR => s_axi4_araddr , -- : in std_logic_vector((C_S_AXI4_ADDR_WIDTH-1) downto 0);
S_AXI4_ARLEN => s_axi4_arlen , -- : in std_logic_vector(7 downto 0);
S_AXI4_ARSIZE => s_axi4_arsize , -- : in std_logic_vector(2 downto 0);
S_AXI4_ARBURST => s_axi4_arburst, -- : in std_logic_vector(1 downto 0);
S_AXI4_ARLOCK => s_axi4_arlock , -- : in std_logic; -- not supported in design
S_AXI4_ARCACHE => s_axi4_arcache, -- : in std_logic_vector(3 downto 0);-- not supported in design
S_AXI4_ARPROT => s_axi4_arprot , -- : in std_logic_vector(2 downto 0);-- not supported in design
S_AXI4_ARVALID => s_axi4_arvalid, -- : in std_logic;
S_AXI4_ARREADY => s_axi4_arready, -- : out std_logic;
--------------------------------
-- AXI Read Data Channel signals
--------------------------------
S_AXI4_RID => s_axi4_rid , -- : out std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_RDATA => s_axi4_rdata , -- : out std_logic_vector((C_S_AXI4_DATA_WIDTH-1) downto 0);
S_AXI4_RRESP => s_axi4_rresp , -- : out std_logic_vector(1 downto 0);
S_AXI4_RLAST => s_axi4_rlast , -- : out std_logic;
S_AXI4_RVALID => s_axi4_rvalid, -- : out std_logic;
S_AXI4_RREADY => s_axi4_rready, -- : in std_logic;
--------------------------------
XIPSR_CPHA_CPOL_ERR => TO_XIPSR_CPHA_CPOL_ERR_int , -- in std_logic
-------------------------------
TO_XIPSR_trans_error => TO_XIPSR_AXI_TR_ERR_int , -- out std_logic
TO_XIPSR_mst_modf_err => TO_XIPSR_mst_modf_err_int,
TO_XIPSR_axi_rx_full => TO_XIPSR_axi_rx_full_int ,
TO_XIPSR_axi_rx_empty => TO_XIPSR_axi_rx_empty_int,
-------------------------------
XIPCR_1_CPOL => XIPCR_1_CPOL_int , -- out std_logic;
XIPCR_0_CPHA => XIPCR_0_CPHA_int , -- out std_logic;
--*SPI port interface * --
-------------------------------
IO0_I => io0_i_sync, -- : in std_logic; -- MOSI signal in standard SPI
IO0_O => io0_o, -- : out std_logic;
IO0_T => io0_t, -- : out std_logic;
-------------------------------
IO1_I => MISO_I_int, -- : in std_logic; -- MISO signal in standard SPI
IO1_O => io1_o, -- : out std_logic;
IO1_T => io1_t, -- : out std_logic;
-----------------
-- quad mode pins
-----------------
IO2_I => io2_i_sync, -- : in std_logic;
IO2_O => io2_o, -- : out std_logic;
IO2_T => io2_t, -- : out std_logic;
---------------
IO3_I => io3_i_sync, -- : in std_logic;
IO3_O => io3_o, -- : out std_logic;
IO3_T => io3_t, -- : out std_logic;
---------------------------------
-- common pins
----------------
SPISEL => spisel, -- : in std_logic;
-----
SCK_I => sck_i , -- : in std_logic;
SCK_O_reg => SCK_O_int , -- : out std_logic;
SCK_T => sck_t , -- : out std_logic;
-----
SS_I => ss_i , -- : in std_logic_vector((C_NUM_SS_BITS-1) downto 0);
SS_O => ss_o , -- : out std_logic_vector((C_NUM_SS_BITS-1) downto 0);
SS_T => ss_t -- : out std_logic;
----------------------
);
-- no interrupt from this mode of core
IP2INTC_Irpt <= '0';
-------------------------------------------------------
-------------------------------------------------------
SCK_MISO_NO_STARTUP_USED: if C_USE_STARTUP = 0 generate
-----
begin
-----
SCK_O <= SCK_O_int; -- output from the core
MISO_I_int <= io1_i_sync; -- input to the core
end generate SCK_MISO_NO_STARTUP_USED;
-------------------------------------------------------
SCK_MISO_STARTUP_USED: if C_USE_STARTUP = 1 generate
-----
begin
-----
QSPI_STARTUP_BLOCK_I: entity axi_quad_spi_v3_2.qspi_startup_block
---------------------
generic map
(
C_SUB_FAMILY => C_FAMILY , -- support for V6/V7/K7/A7 families only
-----------------
C_USE_STARTUP => C_USE_STARTUP,
-----------------
C_SPI_MODE => C_SPI_MODE
-----------------
)
port map
(
SCK_O => SCK_O_int, -- : in std_logic; -- input from the qspi_mode_0_module
IO1_I_startup => io1_i_sync, -- : in std_logic; -- input from the top level port list
IO1_Int => MISO_I_int,-- : out std_logic
Bus2IP_Clk => Bus2IP_Clk,
reset2ip_reset => bus2ip_reset_ipif4_inverted,
CFGCLK => cfgclk, -- FGCLK , -- 1-bit output: Configuration main clock output
CFGMCLK => cfgmclk, -- FGMCLK , -- 1-bit output: Configuration internal oscillator clock output
EOS => eos, -- OS , -- 1-bit output: Active high output signal indicating the End Of Startup.
PREQ => preq, -- REQ , -- 1-bit output: PROGRAM request to fabric output
DI => di -- output
);
--------------------
end generate SCK_MISO_STARTUP_USED;
end generate XIP_MODE_GEN;
------------------------------------------------------------------------------
end architecture imp;
------------------------------------------------------------------------------
| gpl-2.0 | 06985f77fabc4c9e9c0d19073b4b564d | 0.435429 | 3.884289 | false | false | false | false |
achan1989/SlowWorm | src/ALU.vhd | 1 | 3,667 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14.09.2016 21:11:45
-- Design Name:
-- Module Name: ALU - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
--
-- Description: Entirely combinational, and all operations are calculated in
-- parallel. The desired output is selected with op_sel. Getting data in and
-- out at the correct time is a responsibility left to other components.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library SlowWorm;
use SlowWorm.SlowWorm.ALL;
entity ALU is
Port (
A : in data_t;
B : in data_t;
op_sel : in alu_op_e_t;
result : out data_t
);
end ALU;
architecture Behavioral of ALU is
-- Logic
signal not_A : data_t;
signal not_B : data_t;
signal A_and_B : data_t;
signal A_nand_B : data_t;
signal A_or_B : data_t;
signal A_nor_B : data_t;
signal A_xor_B : data_t;
signal A_xnor_B : data_t;
signal NA_and_B : data_t;
signal NB_and_A : data_t;
signal NA_or_B : data_t;
signal NB_or_A : data_t;
-- Arithmetic
signal A_plus_B : data_t;
signal B_minus_A : data_t;
signal inc_A : data_t;
signal inc_B : data_t;
signal dec_A : data_t;
signal dec_B : data_t;
signal lsl_A : data_t;
signal lsl_B : data_t;
signal lsr_A : data_t;
signal lsr_B : data_t;
signal asr_A : data_t;
signal asr_B : data_t;
begin
-- Logic
not_A <= not A;
not_B <= not B;
A_and_B <= A and B;
A_nand_B <= A nand B;
A_or_B <= A or B;
A_nor_B <= A nor B;
A_xor_B <= A xor B;
A_xnor_B <= A xnor B;
NA_and_B <= (not A) and B;
NB_and_A <= (not B) and A;
NA_or_B <= (not A) or B;
NB_or_A <= (not B) or A;
-- Arithmetic
A_plus_B <= std_ulogic_vector(unsigned(A) + unsigned(B));
B_minus_A <= std_ulogic_vector(unsigned(B) - unsigned(A));
inc_A <= std_ulogic_vector(unsigned(A) + to_unsigned(1, 8));
inc_B <= std_ulogic_vector(unsigned(B) + to_unsigned(1, 8));
dec_A <= std_ulogic_vector(unsigned(A) - to_unsigned(1, 8));
dec_B <= std_ulogic_vector(unsigned(B) - to_unsigned(1, 8));
lsl_A <= A sll 1;
lsl_B <= B sll 1;
lsr_A <= A srl 1;
lsr_B <= B srl 1;
asr_A <= A sra 1;
asr_B <= B sra 1;
result <= -- Logic
not_A when op_sel = OP_NOT_A else
not_B when op_sel = OP_NOT_B else
A_and_B when op_sel = OP_A_AND_B else
A_nand_B when op_sel = OP_A_NAND_B else
A_or_B when op_sel = OP_A_OR_B else
A_nor_B when op_sel = OP_A_NOR_B else
A_xor_B when op_sel = OP_A_XOR_B else
A_xnor_B when op_sel = OP_A_XNOR_B else
NA_and_B when op_sel = OP_NA_AND_B else
NB_and_A when op_sel = OP_NB_AND_A else
NA_or_B when op_sel = OP_NA_OR_B else
NB_or_A when op_sel = OP_NB_OR_A else
-- Arithmetic
A_plus_B when op_sel = OP_A_PLUS_B else
B_minus_A when op_sel = OP_B_MINUS_A else
inc_A when op_sel = OP_INC_A else
inc_B when op_sel = OP_INC_B else
dec_A when op_sel = OP_DEC_A else
dec_B when op_sel = OP_DEC_B else
lsl_A when op_sel = OP_LSL_A else
lsl_B when op_sel = OP_LSL_B else
lsr_A when op_sel = OP_LSR_A else
lsr_B when op_sel = OP_LSR_B else
asr_A when op_sel = OP_ASR_A else
asr_B when op_sel = OP_ASR_B else
-- Error
(others => 'X');
end Behavioral;
| mit | 3ad792a1d251923061f0a61f40bad280 | 0.545678 | 2.825116 | false | false | false | false |
Hyperion302/omega-cpu | Hardware/Omega/PortController.vhdl | 1 | 5,078 | -- This file is part of the Omega CPU Core
-- Copyright 2015 - 2016 Joseph Shetaye
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as
-- published by the Free Software Foundation, either version 3 of the
-- License, or (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library open16750;
use open16750.UART;
use work.Constants.ALL;
entity PortController is
port (
CLK : in std_logic;
CLK16x : in std_logic;
XMit : in Word;
Recv : out Word;
SerialIn : in std_logic;
SerialOut : out std_logic;
instruction : in Word;
CPUReady : in std_logic;
CPUSending: in std_logic;
PortReady: out std_logic;
PortSending: out std_logic;
Done: out std_logic);
end PortController;
architecture Behavioral of PortController is
component UART is
generic (
word_length : integer range 5 to 8 := 8;
stop_bits : integer range 1 to 2 := 1;
has_parity : boolean := false;
parity_is_even : boolean := false;
baud_divisor : integer range 1 to 65535 := 1);
port (
clk : in std_logic;
rst : in std_logic;
-- This clock should run at 16 times the baud rate.
clk_16x : in std_logic;
serial_out : out std_logic;
serial_in : in std_logic;
din : in std_logic_vector(7 downto 0);
xmit_buffer_ready : out std_logic;
xmit_enable : in std_logic;
was_read : in std_logic;
recv_data_ready : out std_logic;
dout : out std_logic_vector(7 downto 0));
end component UART;
signal recv_s : Word := (others => '0');
signal portReady_s : std_logic := '0';
signal portSending_s : std_logic := '0';
signal done_s : std_logic := '0';
signal rst_s : std_logic := '1';
-- This clock should run at 16 times the baud rate.
signal din_s : std_logic_vector(7 downto 0) := (others => '0');
signal xmit_buffer_ready_s : std_logic;
signal xmit_enable_s : std_logic := '0';
signal was_read_s : std_logic := '0';
signal recv_data_ready_s : std_logic;
signal dout_s : std_logic_vector(7 downto 0);
begin
recv <= recv_s;
portReady <= portReady_s;
portSending <= portSending_s;
done <= done_s;
UART1 : UART generic map (
baud_divisor => 25
) port map (
clk => clk,
rst => rst_s,
clk_16x => CLK16x,
serial_in => serialIn,
serial_out => serialOut,
din => din_s,
xmit_buffer_ready => xmit_buffer_ready_s,
xmit_enable => xmit_enable_s,
was_read => was_read_s,
recv_data_ready => recv_data_ready_s,
dout => dout_s
);
process (clk) begin
if rising_edge(clk) then
if rst_s = '1' then
rst_s <= '0';
end if;
end if;
end process;
process (clk) begin
if rising_edge(clk) then
if GetOpcode(instruction) = OpcodePort and
(GetOperator(instruction) = LoadByteSigned or
GetOperator(instruction) = LoadHalfWordSigned or
GetOperator(instruction) = LoadByteUnsigned or
GetOperator(instruction) = LoadHalfWordUnsigned or
GetOperator(instruction) = LoadWord) and
getRegisterReferenceB(instruction) = "00001" then
if portSending_s = '0' then
portReady_s <= recv_data_ready_s;
if recv_data_ready_s = '1' and CPUReady = '1' then
portSending_s <= '1';
recv_s <= "000000000000000000000000" & dout_s;
was_read_s <= '1';
end if;
elsif portSending_s = '1' then
portSending_s <= '0';
portReady_s <= '0';
was_read_s <= '0';
recv_s <= (others => '0');
end if;
elsif GetOpcode(instruction) = OpcodePort and
(GetOperator(instruction) = StoreByte or
GetOperator(instruction) = StoreHalfWord or
GetOperator(instruction) = StoreWord) and
getRegisterReferenceB(instruction) = "00001" then
if done_s = '0' then
if CPUReady = '1' and xmit_buffer_ready_s = '1' then
din_s <= Xmit(7 downto 0);
done_s <= '1';
xmit_enable_s <= '1';
end if;
elsif done_s = '1' then
din_s <= (others => '0');
done_s <= '0';
xmit_enable_s <= '0';
end if;
end if;
end if;
end process;
end Behavioral;
| lgpl-3.0 | 7fa53ea7c8fc134ac59ee543cc11fd63 | 0.573454 | 3.693091 | false | false | false | false |
jmarcelof/Phoenix | NoC/Table_package.vhd | 2 | 7,751 | library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.NoCPackage.all;
package TablePackage is
constant NREG : integer := 6;
constant MEMORY_SIZE : integer := NREG;
constant NBITS : integer := 4;
constant CELL_SIZE : integer := 2*NPORT+4*NBITS;
subtype cell is std_logic_vector(CELL_SIZE-1 downto 0);
subtype regAddr is std_logic_vector(2*NBITS-1 downto 0);
type memory is array (0 to MEMORY_SIZE-1) of cell;
type tables is array (0 to NROT-1) of memory;
subtype ports is std_logic_vector(NPORT-1 downto 0);
function input_ports(region : cell) return ports;
function output_ports(region : cell) return ports;
function upper_right_x(region : cell) return natural;
function upper_right_y(region : cell) return natural;
function lower_left_x(region : cell) return natural;
function lower_left_y(region : cell) return natural;
function formatted_region(
input_ports : ports;
VertInf : regAddr;
VertSup : regAddr;
output_ports : ports
) return cell;
constant TAB: tables :=(
-- Router 0.0
(("10000000000010000010000100"),
( "10000000100000100010000001"),
("00000000000000000000000000"),
("00000000000000000000000000"),
("00000000000000000000000000"),
("00000000000000000000000000")
),
-- Router 0.1
(("11100000100000100000100001"),
("11001000000100100010000100"),
("10101000000000000000001000"),
("00000000000000000000000000"),
("00000000000000000000000000"),
("00000000000000000000000000")
),
-- Router 0.2
(("10101000000000000000101000"),
("11001000000110100010000100"),
("11100000100000100001000001"),
("00000000000000000000000000"),
("00000000000000000000000000"),
("00000000000000000000000000")
),
-- Router 0.3
(("11100000100110010001100001"),
("11001000001000010010000100"),
("11100001100110100010000001"),
("10101000000000100001001000"),
("00000000000000000000000000"),
("00000000000000000000000000")
),
-- Router 0.4
(("11000000101000010010000001"),
("10000001100000100010001001"),
("10001000000000010001101000"),
("00000000000000000000000000"),
("00000000000000000000000000"),
("00000000000000000000000000")
),
-- Router 1.0
(("10101000000000000000000010"),
("10010000000010001010000100"),
("10010001000000100010000001"),
("00000000000000000000000000"),
("00000000000000000000000000"),
("00000000000000000000000000")
),
-- Router 1.1
(("10111000000000001000001000"),
("11001000000000000000100010"),
("11110001000000100000100001"),
("11001000000100100010000100"),
("00000000000000000000000000"),
("00000000000000000000000000")
),
-- Router 1.2
(("11110001000100010001000001"),
("10111000000000000000001000"),
("11001000000000000010000010"),
("11110001100100100010000001"),
("11001000100110100010000100"),
("10111000100000100000101000")
),
-- Router 1.3
(("11110001000110010001100001"),
("11011000101000010010000100"),
("11110001100110100010000001"),
("11101000000000000010000010"),
("10111000100000100001001000"),
("00000000000000000000000000")
),
-- Router 1.4
(("10001000001000000010000010"),
("10000001100000100010001001"),
("10001000000000010001101000"),
("11010001000000100010000001"),
("00000000000000000000000000"),
("00000000000000000000000000")
),
-- Router 2.0
(("10101000000000001000000010"),
("10010001100000100010000001"),
("10010000000010010010000100"),
("00000000000000000000000000"),
("00000000000000000000000000"),
("00000000000000000000000000")
),
-- Router 2.1
(("10111000000000010000001000"),
("11110001100000100000100001"),
("11001000000000001000100010"),
("11001000000100100010000100"),
("00000000000000000000000000"),
("00000000000000000000000000")
),
-- Router 2.2
(("10111001000000010000101000"),
("10111000000000001000001000"),
("11001000000000001001000010"),
("11110001100000100010000001"),
("11001000000110100010000100"),
("00000000000000000000000000")
),
-- Router 2.3
(("10111000000000001000001000"),
("11001000001000010010000100"),
("11110001100110100010000001"),
("11001000000000001001100010"),
("10111001000000100001001000"),
("00000000000000000000000000")
),
-- Router 2.4
(("10010001000000010001101000"),
("10010001100000100010001000"),
("11000000000000001010000010"),
("00000000000000000000000000"),
("00000000000000000000000000"),
("00000000000000000000000000")
),
-- Router 3.0
(("10101000000000010000000010"),
("10010010000000100010000001"),
("10010000000010011010000100"),
("00000000000000000000000000"),
("00000000000000000000000000"),
("00000000000000000000000000")
),
-- Router 3.1
(("11110010000000100000100001"),
("10111000000000011000001000"),
("11001000000000010000100010"),
("11001000000100100010000100"),
("00000000000000000000000000"),
("00000000000000000000000000")
),
-- Router 3.2
(("11011001100110011010000100"),
("11110010000100100010000001"),
("10111001100000100000101000"),
("11101000000000010010000010"),
("00000000000000000000000000"),
("00000000000000000000000000")
),
-- Router 3.3
(("11011001101000011010000100"),
("11110010000110100010000001"),
("10101000000110010010000010"),
("10101000000000100001001000"),
("00000000000000000000000000"),
("00000000000000000000000000")
),
-- Router 3.4
(("10000001100000011001101000"),
("10000010000000100010000001"),
("10000000000000010010001000"),
("00000000000000000000000000"),
("00000000000000000000000000"),
("00000000000000000000000000")
),
-- Router 4.0
(("10010000000010100010000100"),
("10100000000000011000000010"),
("00000000000000000000000000"),
("00000000000000000000000000"),
("00000000000000000000000000"),
("00000000000000000000000000")
),
-- Router 4.1
(("10110000000000100000001000"),
("11000000000000011000100010"),
("11000000000100100010000100"),
("00000000000000000000000000"),
("00000000000000000000000000"),
("00000000000000000000000000")
),
-- Router 4.2
(("11010010000110100010000100"),
("10110010000000100000101000"),
("11100000000000011010000010"),
("00000000000000000000000000"),
("00000000000000000000000000"),
("00000000000000000000000000")
),
-- Router 4.3
(("11010001101000100010000100"),
("10100000000110011010000010"),
("10100000000000100001001000"),
("00000000000000000000000000"),
("00000000000000000000000000"),
("00000000000000000000000000")
),
-- Router 4.4
(("11000001101000011010000010"),
("10010000000000010010001000"),
("10010001100000100001101000"),
("00000000000000000000000000"),
("00000000000000000000000000"),
("00000000000000000000000000")
)
);
end TablePackage;
package body TablePackage is
function input_ports(region : cell) return ports is
variable result : std_logic_vector(NPORT-1 downto 0);
begin
result := region(CELL_SIZE-1 downto CELL_SIZE-5);
return result;
end input_ports;
function output_ports(region : cell) return ports is
begin
return region(NPORT-1 downto 0);
end output_ports;
function upper_right_x(region : cell) return natural is
begin
return TO_INTEGER(unsigned(region(CELL_SIZE-6-2*NBITS downto CELL_SIZE-5-3*NBITS)));
end upper_right_x;
function upper_right_y(region : cell) return natural is
begin
return TO_INTEGER(unsigned(region(CELL_SIZE-6-3*NBITS downto 5)));
end upper_right_y;
function lower_left_x(region : cell) return natural is
begin
return TO_INTEGER(unsigned(region(CELL_SIZE-6 downto CELL_SIZE-5-NBITS)));
end lower_left_x;
function lower_left_y(region : cell) return natural is
begin
return TO_INTEGER(unsigned(region(CELL_SIZE-6-NBITS downto CELL_SIZE-5-2*NBITS)));
end lower_left_y;
function formatted_region(
input_ports : ports;
VertInf : regAddr;
VertSup : regAddr;
output_ports : ports
) return cell is
variable region : cell;
begin
region(CELL_SIZE-1 downto CELL_SIZE-5) := input_ports;
region(CELL_SIZE-6 downto CELL_SIZE-5-2*NBITS) := VertInf;
region(CELL_SIZE-6-2*NBITS downto NPORT) := VertSup;
region(NPORT-1 downto 0) := output_ports;
return region;
end formatted_region;
end TablePackage;
| lgpl-3.0 | f5a759d123f89112cc46eb56eb5f1bcb | 0.764417 | 4.454598 | false | false | false | false |
rodrigofegui/UnB | 2017.1/Organização e Arquitetura de Computadores/Trabalhos/Projeto Final/Codificação/Uniciclo_tb.vhd | 2 | 1,694 | ----------------------------------------------------------------------------------
-- Organizacao e Arquitetura de Computadores
-- Professor: Marcelo Grandi Mandelli
-- Responsaveis: Danillo Neves
-- Luiz Gustavo
-- Rodrigo Guimaraes
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY Uniciclo_tb IS
generic (
DATA_WIDTH : natural := 32; --32 bits para dados
ADDRESS_WIDTH : natural := 5 --5 bits para endereco
);
END Uniciclo_tb;
ARCHITECTURE Uniciclo_arch OF Uniciclo_tb IS
--declaracao de sinais
SIGNAL clk : std_logic := '1';
SIGNAL SW : std_logic_vector(13 downto 0);
SIGNAL HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7: std_logic_vector(6 downto 0);
COMPONENT Uniciclo --componente que sera testado
port (
clk : in std_logic := '1';
SW : in std_logic_vector(13 downto 0);
HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7: out std_logic_vector(6 downto 0)
);
END COMPONENT;
BEGIN
i1 : Uniciclo
PORT MAP (
clk => clk,
SW => SW,
HEX0 =>HEX0,
HEX1 =>HEX1,
HEX2 =>HEX2,
HEX3 =>HEX3,
HEX4 =>HEX4,
HEX5 =>HEX5,
HEX6 =>HEX6,
HEX7 =>HEX7
);
Clk_process : PROCESS --geracao do clock
variable auxMod : integer;
BEGIN
for op in 0 to 16383 loop
SW <= std_logic_vector(to_signed(op, SW'length));
for i in 0 to 255 loop
clk <= not(clk);
wait for 5 ps;
end loop;
end loop;
END PROCESS Clk_process;
END Uniciclo_arch; --fim do testbench | gpl-3.0 | 19a1244a180c0191ca124c5f2dad8ab5 | 0.533058 | 3.166355 | false | false | false | false |
dpolad/dlx | DLX_vhd/005-MUX41.vhd | 2 | 782 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.myTypes.all;
entity mux41 is
generic (
MUX_SIZE : integer := 32
);
port (
IN0 : in std_logic_vector(MUX_SIZE - 1 downto 0);
IN1 : in std_logic_vector(MUX_SIZE - 1 downto 0);
IN2 : in std_logic_vector(MUX_SIZE - 1 downto 0);
IN3 : in std_logic_vector(MUX_SIZE - 1 downto 0);
CTRL : in std_logic_vector(1 downto 0);
OUT1 : out std_logic_vector(MUX_SIZE - 1 downto 0)
);
end mux41;
architecture bhe of mux41 is
begin
process ( CTRL, IN0, IN1, IN2, IN3)
begin
case CTRL is
when "00" => OUT1 <= IN0;
when "01" => OUT1 <= IN1;
when "10" => OUT1 <= IN2;
when "11" => OUT1 <= IN3;
when others => OUT1 <= (others => 'X'); -- should never appear
end case;
end process;
end bhe;
| bsd-2-clause | 88a1a4bd329f011e0915a971072b0394 | 0.636829 | 2.421053 | false | false | false | false |
TimingKeepers/gen-ugr-cores | modules/wishbone/wb_i2c_arb/i2c_arbiter_hotone_dec.vhd | 1 | 2,879 | -------------------------------------------------------------------------------
-- Title : I2C Bus Arbiter Hotone Decoder
-- Project : White Rabbit Project
-------------------------------------------------------------------------------
-- File : i2c_arbiter_hotone_dec.vhd
-- Author : Miguel Jimenez Lopez
-- Company : UGR
-- Created : 2015-08-06
-- Last update: 2015-08-06
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
--
-- This component allows to share a single I2C bus for many masters in a simple
-- way.
--
-------------------------------------------------------------------------------
-- TODO:
-------------------------------------------------------------------------------
--
-- Copyright (c) 2015 UGR
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity i2c_arbiter_hotone_dec is
generic (
g_num_inputs : natural range 2 to 32 := 2
);
port (
-- Clock & Reset
clk_i : in std_logic;
rst_n_i : in std_logic;
enable_i : in std_logic;
start_state_i : in std_logic_vector(g_num_inputs-1 downto 0);
input_enabled_o : out std_logic;
input_idx_enabled_o : out integer range 0 to g_num_inputs-1
);
end i2c_arbiter_hotone_dec;
architecture struct of i2c_arbiter_hotone_dec is
begin
main: process(clk_i)
variable idx : integer := -1;
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
input_enabled_o <= '0';
input_idx_enabled_o <= 0;
else
if enable_i = '1' then
idx := -1;
for I in g_num_inputs-1 downto 0 loop
if start_state_i(I) = '1' then
idx := I;
end if;
end loop;
if idx = -1 then
input_enabled_o <= '0';
input_idx_enabled_o <= 0;
else
input_enabled_o <= '1';
input_idx_enabled_o <= idx;
end if;
end if;
end if;
end if;
end process main;
end struct;
| gpl-2.0 | b3dc42d9ba8378d60c1f9b2da8c50896 | 0.523446 | 3.719638 | false | false | false | false |
achan1989/SlowWorm | src/cpu.vhd | 1 | 2,163 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 28.08.2016 16:52:51
-- Design Name:
-- Module Name: cpu - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library SlowWorm;
use SlowWorm.SlowWorm.ALL;
entity cpu is
Port (
clk : in std_ulogic;
inst_mem_data : in data_t;
inst_mem_addr : out addr_t;
data_mem_data_r : in data_t;
data_mem_data_w : out data_t;
data_mem_addr : out addr_t;
data_mem_we : out std_ulogic
);
end cpu;
architecture Behavioral of cpu is
signal rstack_push : std_ulogic;
signal rstack_pop : std_ulogic;
signal rstack_data_read : data_t;
signal rstack_data_write : data_t;
signal dstack_push : std_ulogic;
signal dstack_pop : std_ulogic;
signal dstack_data_read : data_t;
signal dstack_data_write : data_t;
begin
control: entity work.control port map (
clk => clk,
inst_mem_data => inst_mem_data,
inst_mem_addr => inst_mem_addr,
data_mem_data_read => data_mem_data_r,
data_mem_data_write =>data_mem_data_w,
data_mem_addr => data_mem_addr,
data_mem_we => data_mem_we,
dstack_data_read => dstack_data_read,
dstack_data_write => dstack_data_write,
dstack_push => dstack_push,
dstack_pop => dstack_pop,
rstack_data_read => rstack_data_read,
rstack_data_write => rstack_data_write,
rstack_push => rstack_push,
rstack_pop => rstack_pop
);
rstack: entity work.stack_256x16 port map (
push => rstack_push,
pop => rstack_pop,
dout => rstack_data_read,
din => rstack_data_write,
clk => clk
);
dstack: entity work.stack_256x16 port map (
push => dstack_push,
pop => dstack_pop,
dout => dstack_data_read,
din => dstack_data_write,
clk => clk
);
end Behavioral;
| mit | 7e4191016a316e62863ea512154743a8 | 0.572816 | 3.194978 | false | false | false | false |
manosaloscables/vhdl | circuitos_secuenciales/ffdr/ffdr_bp.vhd | 1 | 1,274 | -- ******************************************************
-- * Banco de prueba para Flip Flop tipo D con reinicio *
-- ******************************************************
library ieee; use ieee.std_logic_1164.all;
entity ffdr_bp is
end ffdr_bp;
architecture arq_bp of ffdr_bp is
constant T: time := 20 ns; -- Período del reloj
signal clk, rst: std_logic; -- Reloj y reinicio
signal prueba_e: std_logic; -- Entradas
signal prueba_s: std_logic; -- Salida
begin
-- Instanciar la unidad bajo prueba
ubp: entity work.ffdr(arq)
port map(
clk => clk,
rst => rst,
d => prueba_e,
q => prueba_s
);
-- Reloj
process begin
clk <= '0';
wait for T/2;
clk <= '1';
wait for T/2;
end process;
-- Reinicio
rst <= '1', '0' after T/2;
-- Otros estímulos
process begin
for i in 1 to 10 loop -- Esperar 10 transisiones del Flip Flop tipo D
prueba_e <= '0';
wait until falling_edge(clk);
prueba_e <= '1';
wait until falling_edge(clk);
end loop;
-- Terminar la simulación
assert false
report "Simulación Completada"
severity failure;
end process;
end arq_bp;
| gpl-3.0 | 8cd2587d4cff836837ebe3518f6586a1 | 0.505495 | 3.802985 | false | false | false | false |
Hyperion302/omega-cpu | Hardware/Omega/clockManagerTB.vhd | 1 | 2,434 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:32:03 10/01/2016
-- Design Name:
-- Module Name: /home/student1/Documents/Omega/CPU/Hardware/Omega/clockManagerTB.vhd
-- Project Name: Omega
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: UARTClockManager
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY clockManagerTB IS
END clockManagerTB;
ARCHITECTURE behavior OF clockManagerTB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT UARTClockManager
PORT(
CLK_IN1 : IN std_logic;
CLK_OUT1 : OUT std_logic;
CLK_OUT2 : OUT std_logic;
RESET : IN std_logic
);
END COMPONENT;
--Inputs
signal CLK_IN1 : std_logic := '0';
signal RESET : std_logic := '0';
--Outputs
signal CLK_OUT1 : std_logic;
signal CLK_OUT2 : std_logic;
-- Clock period definitions
constant CLK_IN1_period : time := 31.25 ns;
constant CLK_OUT1_period : time := 10 ns;
constant CLK_OUT2_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: UARTClockManager PORT MAP (
CLK_IN1 => CLK_IN1,
CLK_OUT1 => CLK_OUT1,
CLK_OUT2 => CLK_OUT2,
RESET => RESET
);
-- Clock process definitions
CLK_IN1_process :process
begin
CLK_IN1 <= '0';
wait for CLK_IN1_period/2;
CLK_IN1 <= '1';
wait for CLK_IN1_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for CLK_IN1_period*10;
-- insert stimulus here
wait;
end process;
END;
| lgpl-3.0 | f9c8bcfc69d41da59a31ac3ff5003c18 | 0.604355 | 3.779503 | false | true | false | false |
dpolad/dlx | DLX_vhd/a.m-FWLOGIC.vhd | 1 | 3,823 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
--use work.myTypes.all;
entity fw_logic is
port (
clock : in std_logic;
reset : in std_logic;
D1_i : in std_logic_vector(4 downto 0); -- taken from output of destination mux in EXE stage
rAdec_i : in std_logic_vector(4 downto 0); -- taken from IR directly in DEC stage
D2_i : in std_logic_vector(4 downto 0);
D3_i : in std_logic_vector(4 downto 0);
rA_i : in std_logic_vector(4 downto 0);
rB_i : in std_logic_vector(4 downto 0);
S_mem_W : in std_logic; -- will the current instruction in MEM stage write to RF?
S_mem_LOAD : in std_logic; -- is the current instruction in MEM stage a LOAD?
S_wb_W : in std_logic; -- did the current instruction in WB stage write to RF?
S_exe_W : in std_logic; -- will the current instruction in EXE stage write to RF?
S_FWAdec : out std_logic_vector(1 downto 0); -- this signal controls forward of A in DEC stage
S_FWA : out std_logic_vector(1 downto 0);
S_FWB : out std_logic_vector(1 downto 0)
);
end fw_logic;
architecture beh of fw_logic is
component ff32
generic(
SIZE : integer
);
port(
D : in std_logic_vector(SIZE - 1 downto 0);
Q : out std_logic_vector(SIZE - 1 downto 0);
clk : in std_logic;
rst : in std_logic
);
end component;
signal S_FWA_4 : std_logic;
signal S_FWB_4 : std_logic;
signal S_FWAdec_4 : std_logic;
signal S_FWA_wb : std_logic;
signal S_FWB_wb : std_logic;
signal S_FWAdec_wb : std_logic;
signal S_FWA_mem : std_logic;
signal S_FWB_mem : std_logic;
signal S_FWAdec_mem : std_logic;
signal D4 :std_logic_vector(4 downto 0);
signal S_4_W_help :std_logic_vector(0 downto 0);
signal S_4_W :std_logic;
signal S_wb_W_help :std_logic_vector(0 downto 0);
begin
S_wb_W_help(0) <= S_wb_W;
S_4_W <= S_4_W_help(0);
D4REG: ff32 generic map(
SIZE => 5
)
port map(
D => D3_i,
Q => D4,
clk => clock,
rst => reset
);
S4W: ff32 generic map(
SIZE => 1
)
port map(
D => S_wb_W_help,
Q => S_4_W_help,
clk => clock,
rst => reset
);
-- TODO: check forwardability looking at CU control signals, in particular if WE on RF is 1 or 0
-- TODO: add forward to memory input ( ONLY NEEDED IN CASE OF LOAD AND STORE IN THE NEXT CC ) should not
-- cause any STALL, also need to remove stalling when STORE is after LOAD
-- TODO:ADD REGISTERS FOR DOUBLE LOAD FORWARDING
-- is A, B, preA forwardable from wb stage?
S_FWA_wb <= S_wb_W and (not or_reduce(rA_i xor D3_i));
S_FWB_wb <= S_wb_W and (not or_reduce(rB_i xor D3_i));
S_FWAdec_wb <= S_wb_W and (not or_reduce(rAdec_i xor D3_i));
-- is A or B forwardable from mem stage?
-- in this case we are also checking if we are not loading, in that case there is no need to forward
S_FWA_mem <= S_mem_W and (not S_mem_LOAD) and (not or_reduce(rA_i xor D2_i));
S_FWB_mem <= S_mem_W and (not S_mem_LOAD) and (not or_reduce(rB_i xor D2_i));
S_FWAdec_mem <= S_mem_W and (not S_mem_LOAD) and (not or_reduce(rAdec_i xor D2_i));
S_FWA_4 <= S_4_W and (not or_reduce(rA_i xor D4));
S_FWB_4 <= S_4_W and (not or_reduce(rB_i xor D4));
S_FWAdec_4 <= S_4_W and (not or_reduce(rAdec_i xor D4));
--pick up the right forwarding source
S_FWA <= "00" when S_FWA_mem = '0' and S_FWA_wb = '0' and S_FWA_4 = '0' else
"01" when S_FWA_mem = '1' else
"10" when S_FWA_mem = '0' and S_FWA_wb = '1' else
"11" when S_FWA_mem = '0' and S_FWA_wb = '0' and S_FWA_4 = '1';
S_FWB <= "00" when S_FWB_mem = '0' and S_FWB_wb = '0' else
"01" when S_FWB_mem = '1' else
"10" when S_FWB_mem = '0' and S_FWB_wb = '1' else
"11" when S_FWB_mem = '0' and S_FWB_wb = '0' and S_FWB_4 = '1';
S_FWAdec <= "00" when S_FWAdec_mem = '0' and S_FWAdec_wb = '0' else
"01" when S_FWAdec_mem = '1' else
"10" when S_FWAdec_mem = '0' and S_FWAdec_wb = '1' else
"XX";
end beh;
| bsd-2-clause | db249e7d16d6662ca8740b0fddcc300c | 0.642166 | 2.345399 | false | false | false | false |
SWORDfpga/ComputerOrganizationDesign | labs/lab12/lab12/ipcore_dir/RAM_B/simulation/RAM_B_tb.vhd | 12 | 4,304 | --------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: RAM_B_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY RAM_B_tb IS
END ENTITY;
ARCHITECTURE RAM_B_tb_ARCH OF RAM_B_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
RAM_B_synth_inst:ENTITY work.RAM_B_synth
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
| gpl-3.0 | 4126168031b28b19172e3f0d79f26e44 | 0.617565 | 4.627957 | false | false | false | false |
TimingKeepers/gen-ugr-cores | modules/bridges/wb_axiburst_bridge.vhd | 1 | 14,654 | --------------------------------------------------------------------------------
-- Title : Burst-capable wishbone to AXI bridge
-- Project :
-------------------------------------------------------------------------------
-- File : wb_axiburst_bridge.vhd
-- Author : Jose Lopez
-- Company : Universidad de Granada
-- Created : 2016-05-17
-- Last update:
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: custom Wishbone to AXI bridge for zen-fmc-adc project.
-- - 64-bit data width and 256-word-long bursts by default.
-- - AXI4
-- - Wishbone pipelined
-- - No b-channel error control
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-05-17 1.0 joselj Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.genram_pkg.all;
use work.gencores_pkg.all;
entity wb_axiburst_bridge is
generic (
G_DATA_WIDTH : integer := 32;
G_ADDR_WIDTH : integer := 32;
G_BURST_WIDTH : integer := 8
);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
--Wishbone ports
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
wb_dat_i : in std_logic_vector(G_DATA_WIDTH-1 downto 0);
wb_adr_i : in std_logic_vector(G_ADDR_WIDTH-1 downto 0);
wb_we_i : in std_logic;
wb_sel_i : in std_logic_vector(G_DATA_WIDTH/8-1 downto 0);
adc_acq_count : in std_logic_vector(31 downto 0); -- Not essential.
-- Unused at the moment.
-- This port can be used to trigger an irq after the transfer is over:
acq_end_o : out std_logic;
-- Ports of Axi Master Bus Interface M00_AXI
m00_axi_aclk : in std_logic;
m00_axi_aresetn : in std_logic;
m00_axi_awaddr : out std_logic_vector(G_ADDR_WIDTH-1 downto 0);
m00_axi_awlen : out std_logic_vector(7 downto 0);
m00_axi_awsize : out std_logic_vector(2 downto 0);
m00_axi_awburst : out std_logic_vector(1 downto 0);
m00_axi_awprot : out std_logic_vector(2 downto 0);
m00_axi_awvalid : out std_logic;
m00_axi_awready : in std_logic;
m00_axi_wdata : out std_logic_vector(G_DATA_WIDTH-1 downto 0);
m00_axi_wstrb : out std_logic_vector(G_DATA_WIDTH/8-1 downto 0);
m00_axi_wlast : out std_logic;
m00_axi_wvalid : out std_logic;
m00_axi_wready : in std_logic;
m00_axi_bresp : in std_logic_vector(1 downto 0);
m00_axi_bvalid : in std_logic;
m00_axi_bready : out std_logic);
end wb_axiburst_bridge;
architecture behavioral of wb_axiburst_bridge is
type addr_state_type is (idle, set_addr, wait_awready, ongoing_burst);
type data_state_type is (idle, burst_words, burst_end);
constant LAST_WORD_IDX : integer := 255;
signal addr_state : addr_state_type;
signal data_state : data_state_type;
signal total_bursts : std_logic_vector(31 downto 0);
signal beat_count : unsigned(G_BURST_WIDTH-1 downto 0);
signal wready_word_count : unsigned(G_BURST_WIDTH-1 downto 0);
signal burst_count : unsigned(19 downto 0);
signal burst_base_addr : unsigned(G_ADDR_WIDTH - 1 downto 0);
signal irq_delay_counter : unsigned(19 downto 0);
signal m00_axi_awvalid_sig : std_logic;
signal m00_axi_wdata_int : std_logic_vector(G_DATA_WIDTH-1 downto 0);
signal m00_axi_wvalid_int : std_logic;
signal m00_axi_wlast_sig : std_logic;
signal m00_axi_wstrb_int : std_logic_vector(G_DATA_WIDTH/8-1 downto 0);
signal fifo_din : std_logic_vector((G_ADDR_WIDTH + G_DATA_WIDTH + G_DATA_WIDTH/8 + 2)-1 downto 0);
signal fifo_wr : std_logic;
signal fifo_dout : std_logic_vector((G_ADDR_WIDTH + G_DATA_WIDTH + G_DATA_WIDTH/8 + 2)-1 downto 0);
signal fifo_rd : std_logic;
signal fifo_empty : std_logic;
signal fifo_full : std_logic;
signal fifo_count : std_logic_vector(5 downto 0);
signal fifo_almost_full : std_logic;
signal fifo_almost_empty : std_logic;
signal wb_stb_d0 : std_logic;
signal axi_error : std_logic;
signal burst_start_sig : std_logic;
signal burst_start_ack : std_logic;
signal acq_end : std_logic;
signal awvalid_count : unsigned(19 downto 0);
signal wlast_count : unsigned(19 downto 0);
signal bvalid_count : unsigned(19 downto 0);
signal last_burst : std_logic;
signal debugsig0, debugsig1, debugsig2 : std_logic_vector(4 downto 0);
attribute mark_debug : string;
attribute mark_debug of fifo_wr : signal is "true";
attribute mark_debug of fifo_rd : signal is "true";
attribute mark_debug of fifo_count : signal is "true";
attribute mark_debug of fifo_empty : signal is "true";
attribute mark_debug of fifo_full : signal is "true";
attribute mark_debug of fifo_almost_empty : signal is "true";
attribute mark_debug of fifo_almost_full : signal is "true";
attribute mark_debug of beat_count : signal is "true";
attribute mark_debug of wready_word_count : signal is "true";
attribute mark_debug of burst_start_sig : signal is "true";
attribute mark_debug of burst_count : signal is "true";
attribute mark_debug of total_bursts : signal is "true";
attribute mark_debug of axi_error : signal is "true";
attribute mark_debug of debugsig0 : signal is "true";
attribute mark_debug of debugsig1 : signal is "true";
attribute mark_debug of debugsig2 : signal is "true";
attribute mark_debug of awvalid_count : signal is "true";
attribute mark_debug of wlast_count : signal is "true";
attribute mark_debug of bvalid_count : signal is "true";
begin
wb_stall_o <= '0';
ack_gen : process(clk_i)
begin
if(rst_n_i = '0') then
wb_ack_o <= '0';
elsif rising_edge(clk_i) then
if(wb_cyc_i = '1' and wb_stb_i = '1') then
wb_ack_o <= '1';
else
wb_ack_o <= '0';
end if;
end if;
end process ack_gen;
cmp_fifo : generic_sync_fifo
generic map (
g_data_width => G_ADDR_WIDTH + G_DATA_WIDTH + G_DATA_WIDTH/8 + 2,
g_size => 40,
g_show_ahead => false,
g_with_empty => true,
g_with_full => true,
g_with_almost_empty => true,
g_with_almost_full => true,
g_with_count => true,
g_almost_empty_threshold => 15,
g_almost_full_threshold => 20
)
port map(
rst_n_i => rst_n_i,
clk_i => clk_i,
d_i => fifo_din,
we_i => fifo_wr,
q_o => fifo_dout,
rd_i => fifo_rd,
empty_o => fifo_empty,
full_o => fifo_full,
almost_empty_o => fifo_almost_empty,
almost_full_o => fifo_almost_full,
count_o => fifo_count
);
fifo_din <= wb_adr_i & wb_sel_i & wb_cyc_i & wb_stb_i & wb_dat_i;
fifo_wr <= wb_cyc_i and wb_stb_i;
cmp_addr_proc : process(clk_i)
begin
if(rst_n_i = '0') then
-- default values:
elsif(rising_edge(clk_i)) then
wb_stb_d0 <= wb_stb_i;
debugsig0 <= "00000";
case addr_state is
when idle =>
-- default values once again:
acq_end <= '0';
m00_axi_awvalid_sig <= '0';
debugsig0 <= "10001";
if(fifo_empty = '1') then
fifo_rd <= '0';
debugsig0 <= "00001";
end if;
-- if there is a new acq:
if wb_cyc_i = '1' and wb_stb_d0 = '0' and wb_stb_i = '1' then
-- addr comes directly from wishbone for the first burst
burst_base_addr <= unsigned(wb_adr_i);
-- save total_bursts
total_bursts <= adc_acq_count(31 downto 8) & x"00"; -- this is not used.
burst_count <= to_unsigned(0,burst_count'length);
-- goto set_addr
addr_state <= set_addr;
debugsig0 <= "00010";
end if;
when set_addr =>
debugsig0 <= "10000";
if(fifo_rd = '1') then
burst_base_addr <= (burst_base_addr) + to_unsigned(2048,burst_base_addr'length);
debugsig0 <= "00100";
else
debugsig0 <= "00101";
end if;
m00_axi_awvalid_sig <= '1';
m00_axi_awlen <= "11111111"; -- FIXME: this should be customizable
m00_axi_awburst <= "01";
m00_axi_awsize <= "011"; -- FIXME: this should be customizable
burst_count <= burst_count + 1;
addr_state <= wait_awready;
when wait_awready =>
-- we just acknowledge that the addr is successfully set and
-- we wait for ending_burst.
m00_axi_awvalid_sig <= '0';
debugsig0 <= "10010";
if (fifo_almost_empty = '0' and fifo_empty = '0' and fifo_rd = '0') or fifo_full = '1' then
burst_start_sig <= '1';
addr_state <= ongoing_burst;
fifo_rd <= '1';
debugsig0 <= "11111";
end if;
if fifo_rd = '1' then
m00_axi_awvalid_sig <= '0';
addr_state <= ongoing_burst;
debugsig0 <= "01000";
end if;
when ongoing_burst =>
fifo_rd <= '1';
debugsig0 <= "01001";
-- only for the first burst in an acquisition
if burst_start_sig = '1' and burst_start_ack = '0' then
burst_start_sig <= '0';
debugsig0 <= "01010";
end if;
-- when one burst is about to end, we can foresee the first address
-- of the next burst and send it via the address channel so that there
-- are no idle cycles between bursts if there is enough data left.
if ((beat_count = LAST_WORD_IDX-5) and (unsigned(fifo_count) > 4)) then --
addr_state <= set_addr;
debugsig0 <= "01011";
end if;
if(fifo_empty = '1') then
addr_state <= idle;
debugsig0 <= "01100";
acq_end <= '1';
end if;
when others =>
end case;
end if;
end process cmp_addr_proc;
-- For our application we want to make sure that we only write in addresses
-- from 0x10000000 to 0x1fffffff
m00_axi_awaddr <= "0001" & std_logic_vector(burst_base_addr(27 downto 0));
m00_axi_awprot <= "000";
m00_axi_awvalid <= m00_axi_awvalid_sig when m00_axi_awready = '1' else '0';
cmp_data_proc : process(clk_i)
begin
if rst_n_i = '0' then
elsif rising_edge(clk_i) then
-- Make sure that wlast is only high for one cycle.
m00_axi_wlast_sig <= '0';
case data_state is
when idle =>
-- Default values, etc.
debugsig1 <= "00000";
if burst_start_sig = '1' then
burst_start_ack <= '1';
data_state <= burst_words;
beat_count <= to_unsigned(0,beat_count'length);
debugsig1 <= "00001";
end if;
when burst_words =>
m00_axi_wvalid_int <= '0';
-- Acknowledge the start of a new acquisition
if(burst_start_sig = '0' and burst_start_ack = '1') then
burst_start_ack <= '0';
debugsig1 <= "00010";
end if;
if(fifo_rd = '1') then
m00_axi_wdata_int <= fifo_dout(G_DATA_WIDTH - 1 downto 0);
m00_axi_wstrb <= fifo_dout( (fifo_dout'length - G_ADDR_WIDTH - 1) downto (fifo_dout'length - G_ADDR_WIDTH - 8));
m00_axi_wvalid_int <= '1';
beat_count <= beat_count+1;
debugsig1 <= "00011";
elsif fifo_empty = '1' then
m00_axi_wdata_int <= fifo_dout(G_DATA_WIDTH - 1 downto 0);
m00_axi_wstrb <= (others => '0');
m00_axi_wvalid_int <= '1';
beat_count <= beat_count+1;
debugsig1 <= "01000";
last_burst <= '1';
end if;
if(m00_axi_wready = '1') then
wready_word_count <= wready_word_count+1;
end if;
if (beat_count = LAST_WORD_IDX) then
m00_axi_wlast_sig <= '1';
beat_count <= to_unsigned(0, beat_count'length);
debugsig1 <= "00100";
end if;
if ((wready_word_count = LAST_WORD_IDX) and last_burst = '1') then
m00_axi_wvalid_int <= '0';
last_burst <= '0';
data_state <= idle;
debugsig1 <= "00101";
end if;
when burst_end => -- This state has remained useless. We could just remove it. Nobody would tell.
data_state <= idle;
debugsig1 <= "00110";
when others =>
end case;
end if;
end process cmp_data_proc;
m00_axi_wdata <= m00_axi_wdata_int;
m00_axi_wvalid <= m00_axi_wvalid_int;
m00_axi_wlast <= m00_axi_wlast_sig;
-- At this moment axi_error just exists but we the bridge won't react to
-- a bresp error in any way.
cmp_bchan_proc : process(clk_i)
begin
if rst_n_i = '0' then
elsif rising_edge(clk_i) then
if m00_axi_bvalid = '1' then
if(m00_axi_bresp = "00") then
axi_error <= '0';
else
axi_error <= '1';
end if;
end if;
if data_state = burst_words then
m00_axi_bready <= '1';
end if;
if data_state /= burst_words and m00_axi_bvalid = '1' then
m00_axi_bready <= '0';
end if;
end if;
end process cmp_bchan_proc;
-- We don't want to tell Linux that we are done with our acquisition
-- until everything has been written to the DDR. Let's give AXI slave
-- and the memory controller some time to do their thing.
cmp_acq_end_gen : process(clk_i)
begin
if rst_n_i = '0' then
elsif rising_edge(clk_i) then
acq_end_o <= '0';
if(acq_end = '1') then
irq_delay_counter <= to_unsigned(1,20);--burst_count(19 downto 2) & "00";
end if;
if irq_delay_counter > 0 then
irq_delay_counter <= irq_delay_counter + 1;
end if;
--if(irq_delay_counter(19 downto 7) = burst_count(12 downto 0) and (fifo_empty = '1') and (burst_count(11 downto 0) /= x"000") ) then
if irq_delay_counter = 1023 then
acq_end_o <= '1';
irq_delay_counter <= (others => '0');
end if;
end if;
end process cmp_acq_end_gen;
-- At any given point in time (if the bridge is working as it should)
-- the counters of awvalids, wlasts and bvalids must not differ in more than 1.
-- This can be an useful tool for debugging.
cmp_count_bursts_debug : process(clk_i)
begin
if rst_n_i = '0' then
awvalid_count <= (others => '0');
wlast_count <= (others => '0');
bvalid_count <= (others => '0');
elsif rising_edge(clk_i) then
if(m00_axi_awvalid_sig = '1') then
awvalid_count <= awvalid_count + 1;
end if;
if(m00_axi_wlast_sig = '1') then
wlast_count <= wlast_count + 1;
end if;
if(m00_axi_bvalid = '1') then
bvalid_count <= bvalid_count + 1;
end if;
end if;
end process cmp_count_bursts_debug;
end behavioral;
| gpl-2.0 | 1f29f5d4568b1fb8be60c27eacbc9bf3 | 0.579091 | 2.995503 | false | false | false | false |
airabinovich/finalArquitectura | TestDatapathPart1/DatapathPart1/ipcore_dir/instructionROM/example_design/instructionROM_prod.vhd | 1 | 9,948 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: instructionROM_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan6
-- C_XDEVICEFAMILY : spartan6
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 3
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : instructionROM.mif
-- C_USE_DEFAULT_DATA : 1
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 32
-- C_READ_WIDTH_A : 32
-- C_WRITE_DEPTH_A : 256
-- C_READ_DEPTH_A : 256
-- C_ADDRA_WIDTH : 8
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 32
-- C_READ_WIDTH_B : 32
-- C_WRITE_DEPTH_B : 256
-- C_READ_DEPTH_B : 256
-- C_ADDRB_WIDTH : 8
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY instructionROM_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END instructionROM_prod;
ARCHITECTURE xilinx OF instructionROM_prod IS
COMPONENT instructionROM_exdes IS
PORT (
--Port A
ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : instructionROM_exdes
PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
| lgpl-2.1 | 849bda53bd79103ce5a5020d489504e4 | 0.497085 | 3.849845 | false | false | false | false |
airabinovich/finalArquitectura | RAM/ipcore_dir/RAM_ram_bank/simulation/RAM_ram_bank_tb.vhd | 1 | 4,346 | --------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: RAM_ram_bank_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY RAM_ram_bank_tb IS
END ENTITY;
ARCHITECTURE RAM_ram_bank_tb_ARCH OF RAM_ram_bank_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
RAM_ram_bank_synth_inst:ENTITY work.RAM_ram_bank_synth
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
| lgpl-2.1 | 16fa217deac5d0e5587bdb9f88d6e467 | 0.61988 | 4.613588 | false | false | false | false |
manosaloscables/vhdl | circuitos_secuenciales/registro_de_desplazamiento/rddl.vhd | 1 | 1,248 | -- **************************************************
-- Registro de Desplazamiento de funcionamiento libre
-- **************************************************
-- Desplaza una posición el contenido del registro hacia la derecha o izquierda
-- en cada ciclo de reloj.
library ieee;
use ieee.std_logic_1164.all;
entity rddl is
generic(N: integer:=8);
port(
clk, rst: in std_logic;
s: in std_logic; -- Sentido de desplazamiento (derecha o izquierda)
ent_s: in std_logic; -- Entrada serial
sal_s: out std_logic_vector(N-1 downto 0) -- Registro de salida
);
end rddl;
architecture arq of rddl is
signal r_reg, r_sig: std_logic_vector(N-1 downto 0);
begin
-- Registro
process(clk, rst) begin
if(rst='0') then
r_reg <= (others=>'0');
elsif(clk'event and clk='1') then
r_reg <= r_sig;
end if;
end process;
-- Lógica del siguiente estado (desplazar 1 bit)
process(s, ent_s, r_reg) begin
if(s='0') then -- Desplazar a la derecha
r_sig <= ent_s & r_reg(N-1 downto 1);
else -- Desplazar a la izquierda
r_sig <= r_reg(N-1 downto 1) & ent_s;
end if;
end process;
-- Salida
sal_s <= r_reg;
end arq; | gpl-3.0 | e741b83d007b22e8f593a63cdb6ef69c | 0.550562 | 3.340483 | false | false | false | false |
airabinovich/finalArquitectura | RAM/ipcore_dir/RAM_ram_bank/simulation/RAM_ram_bank_synth.vhd | 1 | 7,900 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: RAM_ram_bank_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY RAM_ram_bank_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE RAM_ram_bank_synth_ARCH OF RAM_ram_bank_synth IS
COMPONENT RAM_ram_bank_exdes
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 4,
READ_WIDTH => 4 )
PORT MAP (
CLK => CLKA,
RST => RSTA,
EN => CHECKER_EN_R,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RSTA='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECKER_EN AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
WEA => WEA,
CHECK_DATA => CHECKER_EN
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: RAM_ram_bank_exdes PORT MAP (
--Port A
WEA => WEA_R,
ADDRA => ADDRA_R,
DINA => DINA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
| lgpl-2.1 | 183b322beaca287536dafa13d766e03b | 0.565063 | 3.758325 | false | false | false | false |
manosaloscables/vhdl | circuitos_secuenciales/archivo_reg/archivo_reg_tb.vhd | 1 | 2,522 | -- *********************************************
-- * Banco de prueba para Archivo de Registros *
-- *********************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity archivo_reg_bp is
generic(
DIR_ANCHO: integer:=2; -- Número de bits para la dirección
DATOS_ANCHO: integer:=8 -- Número de bits por término
);
end archivo_reg_bp;
architecture arq_bp of archivo_reg_bp is
constant T: time := 20 ns; -- Período del reloj
signal clk: std_logic; -- Reloj
signal wr_en: std_logic; -- Activador de escritura
signal w_dir: std_logic_vector (DIR_ANCHO-1 downto 0); -- Dirección de estcritura
signal r_dir: std_logic_vector (DIR_ANCHO-1 downto 0); -- Dirección de lectura
signal prueba_e: std_logic_vector (DATOS_ANCHO-1 downto 0); -- Entrada
signal prueba_s: std_logic_vector (DATOS_ANCHO-1 downto 0); -- Salida
begin
-- Instanciar la unidad bajo prueba
ubp: entity work.archivo_reg(arq)
port map(
clk => clk,
wr_en => wr_en,
w_dir => w_dir,
r_dir => r_dir,
w_datos => prueba_e,
r_datos => prueba_s
);
-- Reloj
process begin
clk <= '0';
wait for T/2;
clk <= '1';
wait for T/2;
end process;
-- Otros estímulos
process begin
-- Activar modo de escritura
wr_en <= '1';
-- Escribir en el tercer registro
w_dir <= "10";
prueba_e <= "11111111";
wait until falling_edge(clk);
-- Escribir el mismo valor en el segundo registro
w_dir <= "01";
prueba_e <= "11111111";
wait until falling_edge(clk);
-- Escribir otro valor en el primer registro
w_dir <= "00";
prueba_e <= "00001111";
wait until falling_edge(clk);
-- Escribir otro valor en el cuarto registro
wr_en <= '1';
w_dir <= "11";
prueba_e <= "00000000";
wait until falling_edge(clk);
-- Deshabilitar escribir otro valor en el cuarto registro
wr_en <= '0';
w_dir <= "11";
prueba_e <= "11110000";
wait until falling_edge(clk);
for i in 0 to 2**DIR_ANCHO-1 loop -- Leer el archivo de registros
r_dir <= std_logic_vector(to_unsigned(i,DIR_ANCHO));
wait until falling_edge(clk);
end loop;
-- Terminar la simulación
assert false
report "Simulación Completada"
severity failure;
end process;
end arq_bp;
| gpl-3.0 | a415c3065c1a17987abd287922a5e016 | 0.556701 | 3.517434 | false | false | false | false |
manosaloscables/vhdl | automata_finito/ejemplo_af/ej_af.vhd | 1 | 1,524 | -- **********************************************
-- * Autómata finito (máquina de estado finito) *
-- **********************************************
library ieee;
use ieee.std_logic_1164.all;
entity ej_af is
port(
clk, rst: in std_logic;
a, b: in std_logic;
y0, y1: out std_logic
);
end ej_af;
architecture arq_dos_seg of ej_af is
type tipo_est_ej is (s0, s1, s2); -- Lista (enumera) los valores simbólicos
signal est_reg, est_sig: tipo_est_ej;
begin
-- Registro de estado
process(clk, rst)
begin
if (rst='0') then
est_reg <= s0;
elsif (clk'event and clk='1') then
est_reg <= est_sig;
end if;
end process;
-- Lógica del siguiente estado/salida
process(est_reg, a, b)
begin
est_sig <= est_reg; -- Volver al mismo estado por defecto
y0 <= '0'; -- Por defecto 0
y1 <= '0'; -- Por defecto 0
case est_reg is
when s0 =>
y1 <= '1';
if a='1' then
if b='1' then
est_sig <= s2;
y0 <= '1';
else
est_sig <= s1;
end if;
-- sin else ya que s0 se mantiene para a=0
end if;
when s1 =>
y1 <= '1';
if (a='1') then
est_sig <= s0;
-- sin else ya que s1 se mantiene para a=0
end if;
when s2 =>
est_sig <= s0;
end case;
end process;
end arq_dos_seg; | gpl-3.0 | e18b3f850355040429836bed7e542f93 | 0.442763 | 3.438914 | false | false | false | false |
jobisoft/jTDC | modules/clipper/leading_edge_clipper.vhdl | 1 | 2,574 | -------------------------------------------------------------------------
---- ----
---- Company: University of Bonn ----
---- Engineer: Daniel Hahne & John Bieling ----
---- ----
-------------------------------------------------------------------------
---- ----
---- Copyright (C) 2015 Daniel Hahne & John Bieling ----
---- ----
---- This program is free software; you can redistribute it and/or ----
---- modify it under the terms of the GNU General Public License as ----
---- published by the Free Software Foundation; either version 3 of ----
---- the License, or (at your option) any later version. ----
---- ----
---- This program is distributed in the hope that it will be useful, ----
---- but WITHOUT ANY WARRANTY; without even the implied warranty of ----
---- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ----
---- GNU General Public License for more details. ----
---- ----
---- You should have received a copy of the GNU General Public ----
---- License along with this program; if not, see ----
---- <http://www.gnu.org/licenses>. ----
---- ----
-------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity leading_edge_clipper is
Port ( input : in STD_LOGIC;
CLK : in STD_LOGIC;
output : out STD_LOGIC := '0');
end leading_edge_clipper;
architecture Behavioral of leading_edge_clipper is
signal q1 : STD_LOGIC := '0';
signal q2 : STD_LOGIC := '0';
begin
process (input, CLK) is
begin
if (CLK'event AND CLK = '1') then
q2 <= q1;
q1 <= input;
end if;
end process;
process (CLK, q1, q2) is
begin
if (CLK'event AND CLK = '1') then
output <= q1 AND NOT q2;
end if;
end process;
end Behavioral;
| gpl-3.0 | 70c8752268040d3c68fe4c132e196f04 | 0.431624 | 5.066929 | false | false | false | false |
airabinovich/finalArquitectura | TestDatapathPart1/PipeAndDebug/ipcore_dir/RAM/simulation/bmg_stim_gen.vhd | 2 | 7,736 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port Ram
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SRAM
-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
-- simulation ends
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SRAM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SRAM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SRAM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST ='1') THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
DINA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
WEA : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0');
CHECK_DATA: OUT STD_LOGIC:='0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
CONSTANT DATA_PART_CNT_A: INTEGER:= DIVROUNDUP(32,32);
SIGNAL WRITE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_INT : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_INT : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_WRITE : STD_LOGIC := '0';
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL COUNT_NO : INTEGER :=0;
SIGNAL DO_READ_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
SIGNAL WEA_VCC : STD_LOGIC_VECTOR(3 DOWNTO 0) :=(OTHERS => '1');
SIGNAL WEA_GND : STD_LOGIC_VECTOR(3 DOWNTO 0) :=(OTHERS => '0');
BEGIN
WRITE_ADDR_INT(7 DOWNTO 0) <= WRITE_ADDR(7 DOWNTO 0);
READ_ADDR_INT(7 DOWNTO 0) <= READ_ADDR(7 DOWNTO 0);
ADDRA <= IF_THEN_ELSE(DO_WRITE='1',WRITE_ADDR_INT,READ_ADDR_INT) ;
DINA <= DINA_INT ;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 256
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
WR_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 256 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_WRITE,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR
);
WR_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP (
DATA_GEN_WIDTH => 32,
DOUT_WIDTH => 32,
DATA_PART_CNT => DATA_PART_CNT_A,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => DO_WRITE,
DATA_OUT => DINA_INT
);
WR_RD_PROCESS: PROCESS (CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
ELSIF(COUNT_NO < 4) THEN
DO_WRITE <= '1';
DO_READ <= '0';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO< 8) THEN
DO_WRITE <= '0';
DO_READ <= '1';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO=8) THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(0),
CLK => CLK,
RST => RST,
D => DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(I),
CLK => CLK,
RST => RST,
D => DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
WEA <= IF_THEN_ELSE(DO_WRITE='1', WEA_VCC,WEA_GND) ;
END ARCHITECTURE;
| lgpl-2.1 | 86dc6ea666dcb878dd4bf9453604c3d1 | 0.557653 | 3.762646 | false | false | false | false |
jobisoft/jTDC | modules/VFB6/disc16/DAC088S085_Controller.vhd | 1 | 6,181 | -------------------------------------------------------------------------
---- ----
---- Company : ELB-Elektroniklaboratorien Bonn UG ----
---- (haftungsbeschränkt) ----
---- ----
---- Description : Controller module for DAC088S085, should also ----
---- be compatible with 10 bit and 12 bit version. ----
---- ----
-------------------------------------------------------------------------
---- ----
---- Copyright (C) 2015 ELB ----
---- ----
---- This program is free software; you can redistribute it and/or ----
---- modify it under the terms of the GNU General Public License as ----
---- published by the Free Software Foundation; either version 3 of ----
---- the License, or (at your option) any later version. ----
---- ----
---- This program is distributed in the hope that it will be useful, ----
---- but WITHOUT ANY WARRANTY; without even the implied warranty of ----
---- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ----
---- GNU General Public License for more details. ----
---- ----
---- You should have received a copy of the GNU General Public ----
---- License along with this program; if not, see ----
---- <http://www.gnu.org/licenses>. ----
---- ----
-------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity DAC088S085_Controller is
Port ( CLK : in STD_LOGIC; -- system clock, max 100MHz, chip select timing has to be checked / modified for higher frequencies
CLKDivH,CLKDivL : in STD_LOGIC_VECTOR (3 downto 0); -- seperate dividers for high and low time of clock
WE : in STD_LOGIC; -- syncronous (CLK) write enable, DATA and Address are being latched on WE='1'
Address : in STD_LOGIC_VECTOR (3 downto 0); -- Data Address (identical to transferred address, lookup in datasheet)
Data : in STD_LOGIC_VECTOR (11 downto 0); -- Data to be transferred bits 3...0 =X for 8 bit version
SCLK, SDA, CS : out STD_LOGIC; -- Serial communication Signals
Busy : out STD_LOGIC); -- busy flag: State machine is busy, incoming WE will be ignored
end DAC088S085_Controller;
architecture Behavioral of DAC088S085_Controller is
Signal BusyRegister : STD_LOGIC :='0';
--Signal DataRegister : STD_LOGIC_VECTOR (11 downto 0) :=(others=>'0');
--signal AddressRegister : STD_LOGIC_VECTOR (4 downto 0) :=(others=>'0');
Signal TransferRegister : STD_LOGIC_VECTOR (14 downto 0) :=(others=>'0'); -- Data and Address to be transfered. Only 15 bit because MSB is applied immidately at WE='1'
Signal SCLKRegister, SDARegister : STD_LOGIC :='0'; -- DAC draws less current if pins are low -> when idle pull low.
Signal CSRegister : STD_LOGIC :='1'; -- Chip select high when idle
Signal ClockDivCounter : unsigned (3 downto 0):=to_unsigned(0,4); -- How many bits have been transfered?
Signal BitCounter : unsigned (4 downto 0):=to_unsigned(0,5); -- How many CLK-Cycles has already been waited (update SCLK, when counter reached value set in interface)
Signal NCRESCLK : STD_LOGIC; -- Next Clockcycle has Rising Edge on SCLK
Signal NCFESCLK : STD_LOGIC; -- Next Clockcycle has Falling Edge on SCLK
begin
SCLK<=SCLKRegister;
SDA<=SDARegister;
CS<=CSRegister;
Busy<=BusyRegister;
GenerateSCLK : Process (CLK) is
begin
if rising_edge(CLK) then
if BusyRegister='0' then -- reset case
ClockDivCounter<=to_unsigned(0,4);
SCLKRegister<='1';
else
ClockDivCounter<=ClockDivCounter+1;
if SCLKRegister='1' then
if CLKDivH = STD_LOGIC_VECTOR (ClockDivCounter) then
SCLKRegister<='0';
ClockDivCounter<=to_unsigned(0,4);
end if;
else
if CLKDivL = STD_LOGIC_VECTOR (ClockDivCounter) then
SCLKRegister<='1';
ClockDivCounter<=to_unsigned(0,4);
end if;
end if;
end if;
end if;
end process;
Process (CLKDivL, ClockDivCounter, SCLKRegister) is begin
if CLKDivL = STD_LOGIC_VECTOR (ClockDivCounter) AND SCLKRegister ='0' then
NCRESCLK<='1';
else
NCRESCLK<='0';
end if;
end Process;
Process (CLKDivH, ClockDivCounter, SCLKRegister) is begin
if CLKDivH = STD_LOGIC_VECTOR (ClockDivCounter) AND SCLKRegister ='1' then
NCFESCLK<='1';
else
NCFESCLK<='0';
end if;
end Process;
Process (CLK) is begin
if rising_edge(CLK) then
if BusyRegister='0' then
if WE='1' then
TransferRegister(11 downto 0)<= Data;
TransferRegister(14 downto 12)<= Address (2 downto 0);
BusyRegister<='1';
CSRegister<='0';
SDARegister <=Address(3);
end if;
else
if NCFESCLK ='1' then -- on falling edge, bits are transfered-> increase number of transferred bits
BitCounter<=BitCounter+1;
end if;
if NCRESCLK ='1' then -- on rising edge, change data (should work best because t_setup = t_hold = 2,5 ns)
TransferRegister (14 downto 1) <=TransferRegister (13 downto 0);
SDARegister <=TransferRegister(14);
end if;
if BitCounter = to_unsigned(16,5) AND NCRESCLK ='1' then -- when 16 bits have been transfered, wait until clock to cipselect time is fullfilled (min 10 ns,
CSRegister<='1';
BusyRegister<='0';
BitCounter <=to_unsigned(0,5);
end if;
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | 0ac7d2414cde19a536b5d0c3c16b5773 | 0.578964 | 4.175676 | false | false | false | false |
MAV-RT-testbed/MAV-testbed | Syma_Flight_Final/Syma_Flight_Final.srcs/sources_1/ipshared/xilinx.com/axi_quad_spi_v3_2/c64e9f22/hdl/src/vhdl/qspi_mode_control_logic.vhd | 1 | 176,939 | --
---- qspi_mode_control_logic - entity/architecture pair
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
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-- ** performance, such as life-support or safety devices or *
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-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
---- Filename: qspi_mode_control_logic.vhd
---- Version: v3.0
---- Description: Serial Peripheral Interface (SPI) Module for interfacing
---- with a 32-bit AXI4 Bus.
----
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library lib_pkg_v1_0;
use lib_pkg_v1_0.all;
use lib_pkg_v1_0.lib_pkg.log2;
use lib_pkg_v1_0.lib_pkg.RESET_ACTIVE;
library unisim;
use unisim.vcomponents.FD;
use unisim.vcomponents.FDRE;
-------------------------------------------------------------------------------
entity qspi_mode_control_logic is
generic(
C_SCK_RATIO : integer;
C_NUM_SS_BITS : integer;
C_NUM_TRANSFER_BITS : integer;
C_SPI_MODE : integer;
C_USE_STARTUP : integer;
C_SPI_MEMORY : integer;
C_SUB_FAMILY : string
);
port(
Bus2IP_Clk : in std_logic;
Soft_Reset_op : in std_logic;
--------------------
DTR_FIFO_Data_Exists : in std_logic;
Slave_Select_Reg : in std_logic_vector(0 to (C_NUM_SS_BITS-1));
Transmit_Data : in std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
Receive_Data : out std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
--Data_To_Rx_FIFO_1 : out std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
SPIXfer_done : out std_logic;
SPIXfer_done_Rx_Wr_en: out std_logic;
MODF_strobe : out std_logic;
SPIXfer_done_rd_tx_en: out std_logic;
----------------------
SR_3_MODF : in std_logic;
SR_5_Tx_Empty : in std_logic;
--SR_6_Rx_Full : in std_logic;
--Last_count : in std_logic;
---------------------- from control register
SPICR_0_LOOP : in std_logic;
SPICR_1_SPE : in std_logic;
SPICR_2_MASTER_N_SLV : in std_logic;
SPICR_3_CPOL : in std_logic;
SPICR_4_CPHA : in std_logic;
SPICR_5_TXFIFO_RST : in std_logic;
SPICR_6_RXFIFO_RST : in std_logic;
SPICR_7_SS : in std_logic;
SPICR_8_TR_INHIBIT : in std_logic;
SPICR_9_LSB : in std_logic;
----------------------
---------------------- from look up table
Data_Dir : in std_logic;
Data_Mode_1 : in std_logic;
Data_Mode_0 : in std_logic;
Data_Phase : in std_logic;
----------------------
Quad_Phase : in std_logic;
--Dummy_Bits : in std_logic_vector(3 downto 0);
----------------------
Addr_Mode_1 : in std_logic;
Addr_Mode_0 : in std_logic;
Addr_Bit : in std_logic;
Addr_Phase : in std_logic;
----------------------
CMD_Mode_1 : in std_logic;
CMD_Mode_0 : in std_logic;
CMD_Error : in std_logic;
CMD_decoded : in std_logic;
----------------------
--SPI Interface
SCK_I : in std_logic;
SCK_O_reg : out std_logic;
SCK_T : out std_logic;
IO0_I : in std_logic;
IO0_O : out std_logic; -- MOSI
IO0_T : out std_logic;
IO1_I : in std_logic; -- MISO
IO1_O : out std_logic;
IO1_T : out std_logic;
IO2_I : in std_logic;
IO2_O : out std_logic;
IO2_T : out std_logic;
IO3_I : in std_logic;
IO3_O : out std_logic;
IO3_T : out std_logic;
SPISEL : in std_logic;
SS_I : in std_logic_vector((C_NUM_SS_BITS-1) downto 0);
SS_O : out std_logic_vector((C_NUM_SS_BITS-1) downto 0);
SS_T : out std_logic;
SPISEL_pulse_op : out std_logic;
SPISEL_d1_reg : out std_logic;
Control_bit_7_8 : in std_logic_vector(0 to 1); --(7 to 8)
pr_state_idle : out std_logic;
Rx_FIFO_Full : in std_logic ;
DRR_Overrun_reg : out std_logic;
reset_RcFIFO_ptr_to_spi : in std_logic
);
end entity qspi_mode_control_logic;
----------------------------------
architecture imp of qspi_mode_control_logic is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-- constant declaration
constant RESET_ACTIVE : std_logic := '1';
constant COUNT_WIDTH : INTEGER := log2(C_NUM_TRANSFER_BITS)+1;
-- function declaration
------------------------
-- spcl_log2 : Performs log2(x) function for value of C_SCK_RATIO > 2
------------------------
function spcl_log2(x : natural) return integer is
variable j : integer := 0;
variable k : integer := 0;
begin
if(C_SCK_RATIO /= 2) then
for i in 0 to 11 loop
if(2**i >= x) then
if(k = 0) then
j := i;
end if;
k := 1;
end if;
end loop;
return j;
else
return 2;
end if;
end spcl_log2;
-- type declaration
type STATE_TYPE is
(IDLE, -- decode command can be combined here later
CMD_SEND,
ADDR_SEND,TEMP_ADDR_SEND,
--DUMMY_SEND,
DATA_SEND,TEMP_DATA_SEND,
DATA_RECEIVE,TEMP_DATA_RECEIVE
);
signal qspi_cntrl_ps: STATE_TYPE;
signal qspi_cntrl_ns: STATE_TYPE;
-----------------------------------------
-- signal declaration
signal Ratio_Count : std_logic_vector
(0 to (spcl_log2(C_SCK_RATIO))-2);
signal Count : std_logic_vector(COUNT_WIDTH downto 0);
signal Count_1 : std_logic_vector(COUNT_WIDTH downto 0);
signal LSB_first : std_logic;
signal Mst_Trans_inhibit : std_logic;
signal Manual_SS_mode : std_logic;
signal CPHA : std_logic;
signal CPOL : std_logic;
signal Mst_N_Slv : std_logic;
signal SPI_En : std_logic;
signal Loop_mode : std_logic;
signal transfer_start : std_logic;
signal transfer_start_d1 : std_logic;
signal transfer_start_pulse : std_logic;
signal SPIXfer_done_int : std_logic;
signal SPIXfer_done_int_d1 : std_logic;
signal SPIXfer_done_int_pulse : std_logic;
signal SPIXfer_done_int_pulse_d1 : std_logic;
signal SPIXfer_done_int_pulse_d2 : std_logic;
signal SPIXfer_done_int_pulse_d3 : std_logic;
signal Serial_Dout_0 : std_logic;
signal Serial_Dout_1 : std_logic;
signal Serial_Dout_2 : std_logic;
signal Serial_Dout_3 : std_logic;
signal Serial_Din_0 : std_logic;
signal Serial_Din_1 : std_logic;
signal Serial_Din_2 : std_logic;
signal Serial_Din_3 : std_logic;
signal io2_i_sync : std_logic;
signal io3_i_sync : std_logic;
signal serial_dout_int : std_logic;
signal mosi_i_sync : std_logic;
signal miso_i_sync : std_logic;
signal master_tri_state_en_control : std_logic;
signal IO0_tri_state_en_control : std_logic;
signal IO1_tri_state_en_control : std_logic;
signal IO2_tri_state_en_control : std_logic;
signal IO3_tri_state_en_control : std_logic;
signal SCK_tri_state_en_control : std_logic;
signal SPISEL_sync : std_logic;
signal spisel_d1 : std_logic;
signal spisel_pulse : std_logic;
signal Sync_Set : std_logic;
signal Sync_Reset : std_logic;
signal SS_Asserted : std_logic;
signal SS_Asserted_1dly : std_logic;
signal Allow_MODF_Strobe : std_logic;
signal MODF_strobe_int : std_logic;
signal Load_tx_data_to_shift_reg_int : std_logic;
signal mode_0 : std_logic;
signal mode_1 : std_logic;
signal sck_o_int : std_logic;
signal sck_o_in : std_logic;
signal Shift_Reg : std_logic_vector
(0 to C_NUM_TRANSFER_BITS-1);
signal sck_d1 : std_logic;
signal sck_d2 : std_logic;
signal sck_d3 : std_logic;
signal sck_rising_edge : std_logic;
signal rx_shft_reg : std_logic_vector(0 to C_NUM_TRANSFER_BITS-1);
signal SCK_O_1 : std_logic;-- :='0';
signal receive_Data_int : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
--:=(others => '0');
signal rx_shft_reg_mode_0011 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
--:=(others => '0');
signal Count_trigger : std_logic;
signal Count_trigger_d1 : std_logic;
signal Count_trigger_pulse : std_logic;
signal pr_state_cmd_ph : std_logic;
signal pr_state_addr_ph : std_logic;
signal pr_state_dummy_ph : std_logic;
signal pr_state_data_receive : std_logic;
signal pr_state_non_idle : std_logic;
signal addr_cnt : std_logic_vector(2 downto 0);
signal dummy_cnt : std_logic_vector(3 downto 0);
signal stop_clock : std_logic;
signal IO0_T_control : std_logic;
signal IO1_T_control : std_logic;
signal IO2_T_control : std_logic;
signal IO3_T_control : std_logic;
signal dummy : std_logic;
signal no_slave_selected : std_logic;
signal Data_To_Rx_FIFO_1 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal Data_To_Rx_FIFO_2 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
attribute IOB : string;
attribute IOB of QSPI_SCK_T : label is "true";
--attribute IOB of QSPI_SS_T : label is "true";
attribute IOB of QSPI_IO0_T : label is "false";-- MOSI_T
attribute IOB of QSPI_IO1_T : label is "false";-- MISO_T
--attribute IOB of QSPI_SPISEL : label is "true";-- SPISEL
signal Mst_Trans_inhibit_d1 : std_logic;
signal Mst_Trans_inhibit_pulse : std_logic;
signal stop_clock_reg : std_logic;
signal transfer_start_d2 : std_logic;
signal transfer_start_d3 : std_logic;
signal transfer_start_pulse_11: std_logic;
signal DRR_Overrun_reg_int : std_logic;
signal Rx_FIFO_Full_reg : std_logic;
-----
begin
-----
LSB_first <= SPICR_9_LSB; -- Control_Reg(0);
Mst_Trans_inhibit <= SPICR_8_TR_INHIBIT; -- Control_Reg(1);
Manual_SS_mode <= SPICR_7_SS; -- Control_Reg(2);
CPHA <= SPICR_4_CPHA; -- Control_Reg(5);
CPOL <= SPICR_3_CPOL; -- Control_Reg(6);
Mst_N_Slv <= SPICR_2_MASTER_N_SLV; -- Control_Reg(7);
SPI_En <= SPICR_1_SPE; -- Control_Reg(8);
Loop_mode <= SPICR_0_LOOP; -- Control_Reg(9);
IO0_O <= Serial_Dout_0;
IO1_O <= Serial_Dout_1;
IO2_O <= Serial_Dout_2;
IO3_O <= Serial_Dout_3;
Receive_Data <= receive_Data_int;
DRR_Overrun_reg <= DRR_Overrun_reg_int;
RX_FULL_CHECK_PROCESS: process(Bus2IP_Clk) is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE)or(reset_RcFIFO_ptr_to_spi = '1') then
Rx_FIFO_Full_reg <= '0';
elsif(Rx_FIFO_Full = '1')then
Rx_FIFO_Full_reg <= '1';
end if;
end if;
end process RX_FULL_CHECK_PROCESS;
DRR_OVERRUN_REG_PROCESS:process(Bus2IP_Clk) is
-----
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
DRR_Overrun_reg_int <= '0';
else
DRR_Overrun_reg_int <= not(DRR_Overrun_reg_int or Soft_Reset_op) and
Rx_FIFO_Full_reg and
SPIXfer_done_int_pulse_d2;
end if;
end if;
end process DRR_OVERRUN_REG_PROCESS;
--* -------------------------------------------------------------------------------
--* -- MASTER_TRIST_EN_PROCESS : If not master make tristate enabled
--* ----------------------------
master_tri_state_en_control <=
'0' when
(
(control_bit_7_8(0)='1') and -- decides master/slave mode
(control_bit_7_8(1)='1') and -- decide the spi_en
((MODF_strobe_int or SR_3_MODF)='0')-- no mode fault
) else
'1';
--QSPI_SS_T: tri-state register for SS,ideal state-deactive
QSPI_SS_T: component FD
generic map
(
INIT => '1'
)
port map
(
Q => SS_T,
C => Bus2IP_Clk,
D => master_tri_state_en_control
);
--------------------------------------
--QSPI_SCK_T : Tri-state register for SCK_T, ideal state-deactive
SCK_tri_state_en_control <= '0' when
(
-- (pr_state_non_idle = '1') and -- CR#619275 - this is commented to operate the mode 3 with SW flow
(control_bit_7_8(0)='1') and -- decides master/slave mode
(control_bit_7_8(1)='1') and -- decide the spi_en
((MODF_strobe_int or SR_3_MODF)='0')-- no mode fault
) else
'1';
QSPI_SCK_T: component FD
generic map
(
INIT => '1'
)
port map
(
Q => SCK_T,
C => Bus2IP_Clk,
D => SCK_tri_state_en_control
);
IO0_tri_state_en_control <= '0' when
(
(IO0_T_control = '0') and
(control_bit_7_8(0)='1') and -- decides master/slave mode
(control_bit_7_8(1)='1') and -- decide the spi_en
((MODF_strobe_int or SR_3_MODF)='0')-- no mode fault
) else
'1';
--QSPI_IO0_T: tri-state register for MOSI, ideal state-deactive
QSPI_IO0_T: component FD
generic map
(
INIT => '1'
)
port map
(
Q => IO0_T, -- MOSI_T,
C => Bus2IP_Clk,
D => IO0_tri_state_en_control -- master_tri_state_en_control
);
--------------------------------------
IO1_tri_state_en_control <= '0' when
(
(IO1_T_control = '0') and
(control_bit_7_8(0)='1') and -- decides master/slave mode
(control_bit_7_8(1)='1') and -- decide the spi_en
((MODF_strobe_int or SR_3_MODF)='0')-- no mode fault
) else
'1';
--QSPI_IO0_T: tri-state register for MISO, ideal state-deactive
QSPI_IO1_T: component FD
generic map
(
INIT => '1'
)
port map
(
Q => IO1_T, -- MISO_T,
C => Bus2IP_Clk,
D => IO1_tri_state_en_control
);
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
QSPI_NO_MODE_2_T_CONTROL: if C_SPI_MODE = 1 or C_SPI_MODE = 0 generate
----------------------
begin
-----
--------------------------------------
IO2_tri_state_en_control <= '1';
IO3_tri_state_en_control <= '1';
IO2_T <= '1';
IO3_T <= '1';
--------------------------------------
end generate QSPI_NO_MODE_2_T_CONTROL;
--------------------------------------
-------------------------------------------------------------------------------
QSPI_MODE_2_T_CONTROL: if C_SPI_MODE = 2 generate
----------------------
attribute IOB : string;
attribute IOB of QSPI_IO2_T : label is "false";
attribute IOB of QSPI_IO3_T : label is "false";
begin
-----
--------------------------------------
IO2_tri_state_en_control <= '0' when
(
(IO2_T_control = '0') and
(control_bit_7_8(0)='1') and -- decides master/slave mode
(control_bit_7_8(1)='1') and -- decide the spi_en
((MODF_strobe_int or SR_3_MODF)='0')-- no mode fault
) else
'1';
--QSPI_IO0_T: tri-state register for MOSI, ideal state-deactive
QSPI_IO2_T: component FD
generic map
(
INIT => '1'
)
port map
(
Q => IO2_T, -- MOSI_T,
C => Bus2IP_Clk,
D => IO2_tri_state_en_control -- master_tri_state_en_control
);
--------------------------------------
IO3_tri_state_en_control <= '0' when
(
(IO3_T_control = '0') and
(control_bit_7_8(0)='1') and -- decides master/slave mode
(control_bit_7_8(1)='1') and -- decide the spi_en
((MODF_strobe_int or SR_3_MODF)='0')-- no mode fault
) else
'1';
--QSPI_IO0_T: tri-state register for MISO, ideal state-deactive
QSPI_IO3_T: component FD
generic map
(
INIT => '1'
)
port map
(
Q => IO3_T, -- MISO_T,
C => Bus2IP_Clk,
D => IO3_tri_state_en_control
);
--------------------------------------
end generate QSPI_MODE_2_T_CONTROL;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- QSPI_SPISEL: first synchronize the incoming signal, this is required is slave
--------------- mode of the core.
QSPI_SPISEL: component FD
generic map
(
INIT => '1' -- default '1' to make the device in default master mode
)
port map
(
Q => SPISEL_sync,
C => Bus2IP_Clk,
D => SPISEL
);
-- SPISEL_DELAY_1CLK_PROCESS_P : Detect active SCK edge in slave mode
-----------------------------
SPISEL_DELAY_1CLK_PROCESS_P: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
spisel_d1 <= '1';
else
spisel_d1 <= SPISEL_sync;
end if;
end if;
end process SPISEL_DELAY_1CLK_PROCESS_P;
------------------------------------------------
-- spisel pulse generating logic
-- this one clock cycle pulse will be available for data loading into
-- shift register
spisel_pulse <= (not SPISEL_sync) and spisel_d1;
-- --------|__________ -- SPISEL
-- ----------|________ -- SPISEL_sync
-- -------------|_____ -- spisel_d1
-- __________|--|_____ -- SPISEL_pulse_op
SPISEL_pulse_op <= not SPISEL_sync; -- spisel_pulse;
SPISEL_d1_reg <= spisel_d1;
MST_TRANS_INHIBIT_D1_I: component FD
generic map
(
INIT => '1'
)
port map
(
Q => Mst_Trans_inhibit_d1,
C => Bus2IP_Clk,
D => Mst_Trans_inhibit
);
Mst_Trans_inhibit_pulse <= Mst_Trans_inhibit and (not Mst_Trans_inhibit_d1);
-------------------------------------------------------------------------------
-- SCK_SET_GEN_PROCESS : Generate SET control for SCK_O_reg
------------------------
SCK_SET_GEN_PROCESS: process(CPOL,
CPHA,
SPIXfer_done_int,
transfer_start_pulse,
Mst_Trans_inhibit_pulse) is
-----
begin
-----
--if(SPIXfer_done_int = '1' or transfer_start_pulse = '1') then
if(Mst_Trans_inhibit_pulse = '1' or SPIXfer_done_int = '1') then
Sync_Set <= (CPOL xor CPHA);
else
Sync_Set <= '0';
end if;
end process SCK_SET_GEN_PROCESS;
-------------------------------------------------------------------------------
-- SCK_RESET_GEN_PROCESS : Generate SET control for SCK_O_reg
--------------------------
SCK_RESET_GEN_PROCESS: process(CPOL,
CPHA,
transfer_start_pulse,
SPIXfer_done_int,
Mst_Trans_inhibit_pulse)is
-----
begin
-----
--if(SPIXfer_done_int = '1' or transfer_start_pulse = '1') then
if(Mst_Trans_inhibit_pulse = '1' or SPIXfer_done_int = '1') then
Sync_Reset <= not(CPOL xor CPHA);
else
Sync_Reset <= '0';
end if;
end process SCK_RESET_GEN_PROCESS;
-------------------------------------------------------------------------------
-- SELECT_OUT_PROCESS : This process sets SS active-low, one-hot encoded select
-- bit. Changing SS is premitted during a transfer by
-- hardware, but is to be prevented by software. In Auto
-- mode SS_O reflects value of Slave_Select_Reg only
-- when transfer is in progress, otherwise is SS_O is held
-- high
-----------------------
SELECT_OUT_PROCESS: process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
SS_O <= (others => '1');
SS_Asserted <= '0';
SS_Asserted_1dly <= '0';
elsif(transfer_start = '0') then -- Tranfer not in progress
for i in (C_NUM_SS_BITS-1) downto 0 loop
SS_O(i) <= Slave_Select_Reg(C_NUM_SS_BITS-1-i);
end loop;
SS_Asserted <= '0';
SS_Asserted_1dly <= '0';
else
for i in (C_NUM_SS_BITS-1) downto 0 loop
SS_O(i) <= Slave_Select_Reg(C_NUM_SS_BITS-1-i);
end loop;
SS_Asserted <= '1';
SS_Asserted_1dly <= SS_Asserted;
end if;
end if;
end process SELECT_OUT_PROCESS;
----------------------------
no_slave_selected <= and_reduce(Slave_Select_Reg(0 to (C_NUM_SS_BITS-1)));
-------------------------------------------------------------------------------
-- MODF_STROBE_PROCESS : Strobe MODF signal when master is addressed as slave
------------------------
MODF_STROBE_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or (SPISEL_sync = '1')) then
MODF_strobe <= '0';
MODF_strobe_int <= '0';
Allow_MODF_Strobe <= '1';
elsif((Mst_N_Slv = '1') and --In Master mode
(SPISEL_sync = '0') and
(Allow_MODF_Strobe = '1')
) then
MODF_strobe <= '1';
MODF_strobe_int <= '1';
Allow_MODF_Strobe <= '0';
else
MODF_strobe <= '0';
MODF_strobe_int <= '0';
end if;
end if;
end process MODF_STROBE_PROCESS;
--------------------------------------------------------------------------
-- LOADING_FIRST_ELEMENT_PROCESS : Combinatorial process to generate flag
-- when loading first data element in shift
-- register from transmit register/fifo
----------------------------------
LOADING_FIRST_ELEMENT_PROCESS: process(Soft_Reset_op,
SPI_En,
SS_Asserted,
SS_Asserted_1dly,
SR_3_MODF
)is
-----
begin
-----
if(Soft_Reset_op = RESET_ACTIVE) then
Load_tx_data_to_shift_reg_int <= '0'; --Clear flag
elsif(SPI_En = '1' and --Enabled
(
(--(Mst_N_Slv = '1') and --Master configuration
(SS_Asserted = '1') and
(SS_Asserted_1dly = '0') and
(SR_3_MODF = '0')
)
)
)then
Load_tx_data_to_shift_reg_int <= '1'; --Set flag
else
Load_tx_data_to_shift_reg_int <= '0'; --Clear flag
end if;
end process LOADING_FIRST_ELEMENT_PROCESS;
------------------------------------------
-------------------------------------------------------------------------------
-- TRANSFER_START_PROCESS : Generate transfer start signal. When the transfer
-- gets completed, SPI Transfer done strobe pulls
-- transfer_start back to zero.
---------------------------
TRANSFER_START_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE or
(
(
SPI_En = '0' or -- enable not asserted or
(SPIXfer_done_int = '1' and SR_5_Tx_Empty = '1' and Data_Phase = '0' and Addr_Phase = '0') or -- no data in Tx reg/FIFO or
SR_3_MODF = '1' or -- mode fault error
Mst_Trans_inhibit = '1' or -- Do not start if Mst xfer inhibited
stop_clock = '1' -- core is in Data Receive State and DRR is not full
)
)
)then
transfer_start <= '0';
else
-- Delayed SPIXfer_done_int_pulse to work for synchronous design and to remove
-- asserting of loading_sr_reg in master mode after SR_5_Tx_Empty goes to 1
-- if((SPIXfer_done_int_pulse = '1') -- or
--(SPIXfer_done_int_pulse_d1 = '1')-- or
--(SPIXfer_done_int_pulse_d2='1')
-- ) then-- this is added to remove
-- glitch at the end of
-- transfer in AUTO mode
-- transfer_start <= '0'; -- Set to 0 for at least 1 period
-- else
transfer_start <= '1'; -- Proceed with SPI Transfer
-- end if;
end if;
end if;
end process TRANSFER_START_PROCESS;
--------------------------------
--TRANSFER_START_PROCESS: process(Bus2IP_Clk)is
-------
--begin
-------
-- if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
-- if(Soft_Reset_op = RESET_ACTIVE or
-- (
-- (
-- SPI_En = '0' or -- enable not asserted or
-- (SR_5_Tx_Empty = '1' and Data_Phase = '0' and Addr_Phase = '0') or -- no data in Tx reg/FIFO or
-- SR_3_MODF = '1' or -- mode fault error
-- Mst_Trans_inhibit = '1' or -- Do not start if Mst xfer inhibited
-- stop_clock = '1' -- core is in Data Receive State and DRR is not full
-- )
-- )
-- )then
--
-- transfer_start <= '0';
-- else
---- Delayed SPIXfer_done_int_pulse to work for synchronous design and to remove
---- asserting of loading_sr_reg in master mode after SR_5_Tx_Empty goes to 1
-- if((SPIXfer_done_int_pulse = '1') or
-- (SPIXfer_done_int_pulse_d1 = '1')-- or
-- --(SPIXfer_done_int_pulse_d2='1')
-- ) then-- this is added to remove
-- -- glitch at the end of
-- -- transfer in AUTO mode
-- transfer_start <= '0'; -- Set to 0 for at least 1 period
-- else
-- transfer_start <= '1'; -- Proceed with SPI Transfer
-- end if;
-- end if;
-- end if;
--end process TRANSFER_START_PROCESS;
-------------------------------------
-------------------------------------------------------------------------------
-- TRANSFER_START_1CLK_PROCESS : Delay transfer start by 1 clock cycle
--------------------------------
TRANSFER_START_1CLK_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
transfer_start_d1 <= '0';
transfer_start_d2 <= '0';
transfer_start_d3 <= '0';
else
transfer_start_d1 <= transfer_start;
transfer_start_d2 <= transfer_start_d1;
transfer_start_d3 <= transfer_start_d2;
end if;
end if;
end process TRANSFER_START_1CLK_PROCESS;
-- transfer start pulse generating logic
transfer_start_pulse <= transfer_start and (not(transfer_start_d1));
transfer_start_pulse_11 <= transfer_start_d2 and (not transfer_start_d3);
-------------------------------------------------------------------------------
-- TRANSFER_DONE_1CLK_PROCESS : Delay SPI transfer done signal by 1 clock cycle
-------------------------------
TRANSFER_DONE_1CLK_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
SPIXfer_done_int_d1 <= '0';
else
SPIXfer_done_int_d1 <= SPIXfer_done_int;
end if;
end if;
end process TRANSFER_DONE_1CLK_PROCESS;
--
-- transfer done pulse generating logic
SPIXfer_done_int_pulse <= SPIXfer_done_int and (not(SPIXfer_done_int_d1));
-------------------------------------------------------------------------------
-- TRANSFER_DONE_PULSE_DLY_PROCESS : Delay SPI transfer done pulse by 1 and 2
-- clock cycles
------------------------------------
-- Delay the Done pulse by a further cycle. This is used as the output Rx
-- data strobe when C_SCK_RATIO = 2
TRANSFER_DONE_PULSE_DLY_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
SPIXfer_done_int_pulse_d1 <= '0';
SPIXfer_done_int_pulse_d2 <= '0';
SPIXfer_done_int_pulse_d3 <= '0';
else
SPIXfer_done_int_pulse_d1 <= SPIXfer_done_int_pulse;
SPIXfer_done_int_pulse_d2 <= SPIXfer_done_int_pulse_d1;
SPIXfer_done_int_pulse_d3 <= SPIXfer_done_int_pulse_d2;
end if;
end if;
end process TRANSFER_DONE_PULSE_DLY_PROCESS;
--------------------------------------------
-------------------------------------------------------------------------------
-- RX_DATA_GEN1: Only for C_SCK_RATIO = 2 mode.
----------------
RX_DATA_SCK_RATIO_2_GEN1 : if C_SCK_RATIO = 2 generate
-----
begin
-----
-------------------------------------------------------------------------------
-- TRANSFER_DONE_PROCESS : Generate SPI transfer done signal. This will stop the SPI clock.
--------------------------
TRANSFER_DONE_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE or transfer_start_pulse = '1') then
SPIXfer_done_int <= '0';
--elsif (transfer_start_pulse = '1') then
-- SPIXfer_done_int <= '0';
else
if(mode_1 = '1' and mode_0 = '0')then
SPIXfer_done_int <= Count(1) and
not(Count(0));
elsif(mode_1 = '0' and mode_0 = '1')then
SPIXfer_done_int <= not(Count(0)) and
Count(2) and
Count(1);
else
SPIXfer_done_int <= --Count(COUNT_WIDTH);
Count(COUNT_WIDTH-1) and
Count(COUNT_WIDTH-2) and
Count(COUNT_WIDTH-3) and
not Count(COUNT_WIDTH-4);
end if;
end if;
end if;
end process TRANSFER_DONE_PROCESS;
-- RECEIVE_DATA_STROBE_PROCESS : Strobe data from shift register to receive
-- data register
--------------------------------
-- For a SCK ratio of 2 the Done needs to be delayed by an extra cycle
-- due to the serial input being captured on the falling edge of the PLB
-- clock. this is purely required for dealing with the real SPI slave memories.
RECEIVE_DATA_STROBE_PROCESS: process(Bus2IP_Clk)
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE)then
Data_To_Rx_FIFO_1 <= (others => '0');
receive_Data_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1')then
if(mode_1 = '0' and mode_0 = '0')then -- for Standard transfer
Data_To_Rx_FIFO_1 <= rx_shft_reg_mode_0011
(1 to (C_NUM_TRANSFER_BITS-1)) &
IO1_I ; --MISO_I;
receive_Data_int <= rx_shft_reg_mode_0011
(1 to (C_NUM_TRANSFER_BITS-1)) &
IO1_I ; --MISO_I;
elsif(mode_1 = '0' and mode_0 = '1')then -- for Dual transfer
Data_To_Rx_FIFO_1 <= rx_shft_reg_mode_0011
(2 to (C_NUM_TRANSFER_BITS-1)) &
IO1_I & -- MISO_I - MSB first
IO0_I ; -- MOSI_I
receive_Data_int <= rx_shft_reg_mode_0011
(2 to (C_NUM_TRANSFER_BITS-1)) &
IO1_I & -- MISO_I - MSB first
IO0_I ; -- MOSI_I
elsif(mode_1 = '1' and mode_0 = '0')then -- for Quad transfer
Data_To_Rx_FIFO_1 <= rx_shft_reg_mode_0011
(4 to (C_NUM_TRANSFER_BITS-1)) &
IO3_I & -- MSB first
IO2_I &
IO1_I &
IO0_I ;
receive_Data_int <= rx_shft_reg_mode_0011
(4 to (C_NUM_TRANSFER_BITS-1)) &
IO3_I & -- MSB first
IO2_I &
IO1_I &
IO0_I ;
end if;
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS;
RECEIVE_DATA_STROBE_PROCESS_1: process(Bus2IP_Clk)
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE)then
Data_To_Rx_FIFO_2 <= (others => '0');
elsif(SPIXfer_done_int_pulse_d1 = '1')then
Data_To_Rx_FIFO_2 <= Data_To_Rx_FIFO_1;
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS_1;
--receive_Data_int <= Data_To_Rx_FIFO_2;
-- Done strobe delayed to match receive data
SPIXfer_done <= SPIXfer_done_int_pulse_d3;
-- SPIXfer_done_rd_tx_en <= transfer_start_pulse or SPIXfer_done_int_d1; -- SPIXfer_done_int_pulse_d1;
SPIXfer_done_rd_tx_en <= transfer_start_pulse or SPIXfer_done_int_pulse_d2;
-- SPIXfer_done_rd_tx_en <= SPIXfer_done_int;
-------------------------------------------------
end generate RX_DATA_SCK_RATIO_2_GEN1;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- RATIO_OF_2_GENERATE : Logic to be used when C_SCK_RATIO is equal to 2
------------------------
RATIO_OF_2_GENERATE: if(C_SCK_RATIO = 2) generate
--------------------
begin
-----
-------------------------------------------------------------------------------
-- SCK_CYCLE_COUNT_PROCESS : Counts number of trigger pulses provided. Used for
-- controlling the number of bits to be transfered
-- based on generic C_NUM_TRANSFER_BITS
----------------------------
RATIO_2_SCK_CYCLE_COUNT_PROCESS: process(Bus2IP_Clk)
begin
-- if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
-- if((Soft_Reset_op = RESET_ACTIVE) or
-- (transfer_start_d1 = '0') or
-- --(transfer_start = '0' and SPIXfer_done_int_d1 = '1') or
-- (Mst_N_Slv = '0')
-- )then
--
-- Count <= (others => '0');
-- elsif (Count(COUNT_WIDTH) = '0') then
-- Count <= Count + 1;
-- end if;
-- end if;
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or
(SPIXfer_done_int = '1') or
(transfer_start = '0')
--(transfer_start = '0' and SPIXfer_done_int_d1 = '1') or
--(Mst_N_Slv = '0')
)then
Count <= (others => '0');
elsif (Count(COUNT_WIDTH) = '0') and ((CPOL and CPHA) = '0') then
Count <= Count + 1;
elsif(transfer_start_d2 = '1') and (Count(COUNT_WIDTH) = '0') then
Count <= Count + 1;
end if;
end if;
end process RATIO_2_SCK_CYCLE_COUNT_PROCESS;
------------------------------------
-------------------------------------------------------------------------------
-- SCK_SET_RESET_PROCESS : Sync set/reset toggle flip flop controlled by
-- transfer_start signal
--------------------------
RATIO_2_SCK_SET_RESET_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or (Sync_Reset = '1')) then
sck_o_int <= '0';
elsif(Sync_Set = '1') then
sck_o_int <= '1';
elsif (transfer_start = '1') then
--sck_o_int <= (not sck_o_int) xor Count(COUNT_WIDTH);
sck_o_int <= (not sck_o_int);
end if;
end if;
end process RATIO_2_SCK_SET_RESET_PROCESS;
----------------------------------
-- DELAY_CLK: Delay the internal clock for a cycle to generate internal enable
-- -- signal for data register.
-------------
RATIO_2_DELAY_CLK: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (Soft_Reset_op = RESET_ACTIVE)then
sck_d1 <= '0';
sck_d2 <= '0';
sck_d3 <= '0';
else
sck_d1 <= sck_o_int;
sck_d2 <= sck_d1;
sck_d3 <= sck_d2;
end if;
end if;
end process RATIO_2_DELAY_CLK;
------------------------------------
-- Rising egde pulse
sck_rising_edge <= sck_d2 and (not sck_d1);
-- CAPT_RX_FE_MODE_00_11: The below logic is to capture data for SPI mode of
--------------------------- 00 and 11.
-- Generate a falling edge pulse from the serial clock. Use this to
-- capture the incoming serial data into a shift register.
RATIO_2_CAPT_RX_FE_MODE_00_11 : process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then --SPIXfer_done_int_pulse_d2
if (Soft_Reset_op = RESET_ACTIVE)then
rx_shft_reg_mode_0011 <= (others => '0');
elsif((sck_d3='0') and --(sck_rising_edge = '1') and
(Data_Dir='0') -- data direction = 0 is read mode
)then
-------
if(mode_1 = '0' and mode_0 = '0')then -- for Standard transfer
rx_shft_reg_mode_0011 <= rx_shft_reg_mode_0011
(1 to (C_NUM_TRANSFER_BITS-1)) &
IO1_I ; --MISO_I;
elsif(mode_1 = '0' and mode_0 = '1')then -- for Dual transfer
rx_shft_reg_mode_0011 <= rx_shft_reg_mode_0011
(2 to (C_NUM_TRANSFER_BITS-1)) &
IO1_I & -- MISO_I - MSB first
IO0_I ; -- MOSI_I
elsif(mode_1 = '1' and mode_0 = '0')then -- for Quad transfer
rx_shft_reg_mode_0011 <= rx_shft_reg_mode_0011
(4 to (C_NUM_TRANSFER_BITS-1)) &
IO3_I & -- MSB first
IO2_I &
IO1_I &
IO0_I ;
end if;
-------
else
rx_shft_reg_mode_0011<= rx_shft_reg_mode_0011;
end if;
end if;
end process RATIO_2_CAPT_RX_FE_MODE_00_11;
----------------------------------
RATIO_2_CAP_QSPI_QUAD_MODE_NM_MEM_GEN: if (
(C_SPI_MODE = 2
or
C_SPI_MODE = 1
)and
(C_SPI_MEMORY = 2
)
)generate
--------------------------------------
begin
-----
-------------------------------------------------------------------------------
-- CAPTURE_AND_SHIFT_PROCESS : This logic essentially controls the entire
-- capture and shift operation for serial data in
------------------------------ master SPI mode only
RATIO_2_CAPTURE_AND_SHIFT_PROCESS: process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
Shift_Reg(0 to C_NUM_TRANSFER_BITS -1) <= (others => '0');
Serial_Dout_0 <= '0';-- default values of the IO0_O
Serial_Dout_1 <= '0';
Serial_Dout_2 <= '0';
Serial_Dout_3 <= '0';
elsif(transfer_start = '1') then --(Mst_N_Slv = '1') then
if(transfer_start_pulse = '1' or SPIXfer_done_int_d1 = '1') then --
--if(Load_tx_data_to_shift_reg_int = '1') then
Shift_Reg <= Transmit_Data;
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Transmit_Data(0);
Serial_Dout_3 <= pr_state_cmd_ph and Quad_Phase;-- this is to make the DQ3 bit 1 in quad command transfer mode.
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Transmit_Data(0); -- msb to IO1_O
Serial_Dout_0 <= Transmit_Data(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Transmit_Data(0); -- msb to IO3_O
Serial_Dout_2 <= Transmit_Data(1);
Serial_Dout_1 <= Transmit_Data(2);
Serial_Dout_0 <= Transmit_Data(3);
end if;
elsif(
(Count(0) = '0')
)then -- Shift Data on even
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Shift_Reg(0);
Serial_Dout_3 <= pr_state_cmd_ph and Quad_Phase;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Shift_Reg(0); -- msb to IO1_O
Serial_Dout_0 <= Shift_Reg(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Shift_Reg(0); -- msb to IO3_O
Serial_Dout_2 <= Shift_Reg(1);
Serial_Dout_1 <= Shift_Reg(2);
Serial_Dout_0 <= Shift_Reg(3);
end if;
elsif(
(Count(0) = '1') --and
) then -- Capture Data on odd
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Shift_Reg <= Shift_Reg
(1 to C_NUM_TRANSFER_BITS -1) &
IO1_I ;-- MISO_I;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Shift_Reg <= Shift_Reg
(2 to C_NUM_TRANSFER_BITS -1) &
IO1_I &
IO0_I ;
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Shift_Reg <= Shift_Reg
(4 to C_NUM_TRANSFER_BITS -1) &
IO3_I &
IO2_I &
IO1_I &
IO0_I ;
end if;
end if;
end if;
end if;
end process RATIO_2_CAPTURE_AND_SHIFT_PROCESS;
----------------------------------------------
end generate RATIO_2_CAP_QSPI_QUAD_MODE_NM_MEM_GEN;
RATIO_2_CAP_QSPI_QUAD_MODE_SP_MEM_GEN: if (
(C_SPI_MODE = 2
or
C_SPI_MODE = 1
)and
(
C_SPI_MEMORY = 3)
)generate
--------------------------------------
begin
-----
-------------------------------------------------------------------------------
-- CAPTURE_AND_SHIFT_PROCESS : This logic essentially controls the entire
-- capture and shift operation for serial data in
------------------------------ master SPI mode only
RATIO_2_CAPTURE_AND_SHIFT_PROCESS: process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
Shift_Reg(0 to C_NUM_TRANSFER_BITS -1) <= (others => '0');
Serial_Dout_0 <= '0';-- default values of the IO0_O
Serial_Dout_1 <= '0';
Serial_Dout_2 <= '0';
Serial_Dout_3 <= '0';
elsif(transfer_start = '1') then --(Mst_N_Slv = '1') then
if(transfer_start_pulse = '1' or SPIXfer_done_int_d1 = '1') then --
--if(Load_tx_data_to_shift_reg_int = '1') then
Shift_Reg <= Transmit_Data;
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Transmit_Data(0);
Serial_Dout_3 <= pr_state_cmd_ph and Quad_Phase;-- this is to make the DQ3 bit 1 in quad command transfer mode.
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Transmit_Data(0); -- msb to IO1_O
Serial_Dout_0 <= Transmit_Data(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Transmit_Data(0); -- msb to IO3_O
Serial_Dout_2 <= Transmit_Data(1);
Serial_Dout_1 <= Transmit_Data(2);
Serial_Dout_0 <= Transmit_Data(3);
end if;
elsif(
(Count(0) = '0')
)then -- Shift Data on even
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Shift_Reg(0);
Serial_Dout_3 <= pr_state_cmd_ph and Quad_Phase;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Shift_Reg(0); -- msb to IO1_O
Serial_Dout_0 <= Shift_Reg(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Shift_Reg(0); -- msb to IO3_O
Serial_Dout_2 <= Shift_Reg(1);
Serial_Dout_1 <= Shift_Reg(2);
Serial_Dout_0 <= Shift_Reg(3);
end if;
elsif(
(Count(0) = '1') --and
) then -- Capture Data on odd
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Shift_Reg <= Shift_Reg
(1 to C_NUM_TRANSFER_BITS -1) &
IO1_I ;-- MISO_I;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Shift_Reg <= Shift_Reg
(2 to C_NUM_TRANSFER_BITS -1) &
IO1_I &
IO0_I ;
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Shift_Reg <= Shift_Reg
(4 to C_NUM_TRANSFER_BITS -1) &
IO3_I &
IO2_I &
IO1_I &
IO0_I ;
end if;
end if;
end if;
end if;
end process RATIO_2_CAPTURE_AND_SHIFT_PROCESS;
----------------------------------------------
end generate RATIO_2_CAP_QSPI_QUAD_MODE_SP_MEM_GEN;
RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN: if (
(C_SPI_MODE = 2 and
(C_SPI_MEMORY = 0
or
C_SPI_MEMORY = 1)
)
or
(C_SPI_MODE = 1 and
(C_SPI_MEMORY = 0
or
C_SPI_MEMORY = 1)
)
) generate
-----------------------------------------
begin
-----
-------------------------------------------------------------------------------
-- CAPTURE_AND_SHIFT_PROCESS : This logic essentially controls the entire
-- capture and shift operation for serial data in
------------------------------ master SPI mode only
RATIO_2_CAPTURE_AND_SHIFT_PROCESS: process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
Shift_Reg(0 to C_NUM_TRANSFER_BITS -1) <= (others => '0');
Serial_Dout_0 <= '0';-- default values of the IO0_O
Serial_Dout_1 <= '0';
Serial_Dout_2 <= '0';
Serial_Dout_3 <= '0';
elsif(transfer_start = '1') then --(Mst_N_Slv = '1') then
--if(Load_tx_data_to_shift_reg_int = '1') then
if(transfer_start_pulse = '1' or SPIXfer_done_int_d1 = '1') then --
Shift_Reg <= Transmit_Data;
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Transmit_Data(0);
Serial_Dout_3 <= pr_state_cmd_ph and Quad_Phase;-- this is to make the DQ3 bit 1 in quad command transfer mode.
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Transmit_Data(0); -- msb to IO1_O
Serial_Dout_0 <= Transmit_Data(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Transmit_Data(0); -- msb to IO3_O
Serial_Dout_2 <= Transmit_Data(1);
Serial_Dout_1 <= Transmit_Data(2);
Serial_Dout_0 <= Transmit_Data(3);
end if;
elsif(
(Count(0) = '0') --and
)then -- Shift Data on even
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Shift_Reg(0);
Serial_Dout_3 <= pr_state_cmd_ph and Quad_Phase;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Shift_Reg(0); -- msb to IO1_O
Serial_Dout_0 <= Shift_Reg(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Shift_Reg(0); -- msb to IO3_O
Serial_Dout_2 <= Shift_Reg(1);
Serial_Dout_1 <= Shift_Reg(2);
Serial_Dout_0 <= Shift_Reg(3);
end if;
elsif(
(Count(0) = '1') --and
) then -- Capture Data on odd
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Shift_Reg <= Shift_Reg
(1 to C_NUM_TRANSFER_BITS -1) &
IO1_I;-- MISO_I;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Shift_Reg <= Shift_Reg
(2 to C_NUM_TRANSFER_BITS -1) &
IO1_I &
IO0_I ;
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Shift_Reg <= Shift_Reg
(4 to C_NUM_TRANSFER_BITS -1) &
IO3_I &
IO2_I &
IO1_I &
IO0_I ;
end if;
end if;
end if;
end if;
end process RATIO_2_CAPTURE_AND_SHIFT_PROCESS;
----------------------------------------------
end generate RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN;
------------------------------------------------------
-----
end generate RATIO_OF_2_GENERATE;
---------------------------------
--------==================================================================-----
RX_DATA_GEN_OTHER_SCK_RATIOS : if C_SCK_RATIO /= 2 generate
------------------------------
-----
begin
-----
-------------------------------------------------------------------------------
-- TRANSFER_DONE_PROCESS : Generate SPI transfer done signal. This will stop the SPI clock.
--------------------------
TRANSFER_DONE_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE or transfer_start_pulse = '1') then
SPIXfer_done_int <= '0';
--elsif (transfer_start_pulse = '1') then
-- SPIXfer_done_int <= '0';
else
if(CPHA = '0' and CPOL = '0') then
if(mode_1 = '1' and mode_0 = '0')then -- quad mode
SPIXfer_done_int <= Count(0) and Count(1);
elsif(mode_1 = '0' and mode_0 = '1')then -- for dual mode
SPIXfer_done_int <= Count(2) and
Count(1) and
Count(0);--- and
--(and_reduce(Ratio_Count));-- dual mode
else
SPIXfer_done_int <= Count(COUNT_WIDTH-COUNT_WIDTH+3) and
Count(COUNT_WIDTH-COUNT_WIDTH+2) and
Count(COUNT_WIDTH-COUNT_WIDTH+1) and
Count(COUNT_WIDTH-COUNT_WIDTH);
end if;
else
if(mode_1 = '1' and mode_0 = '0')then -- quad mode
SPIXfer_done_int <= Count(1) and
Count(0);
elsif(mode_1 = '0' and mode_0 = '1')then -- for dual mode
SPIXfer_done_int <= Count(2) and
Count(1) and
Count(0);
else
SPIXfer_done_int <= Count(COUNT_WIDTH-COUNT_WIDTH+3) and
Count(COUNT_WIDTH-COUNT_WIDTH+2) and
Count(COUNT_WIDTH-COUNT_WIDTH+1) and
Count(COUNT_WIDTH-COUNT_WIDTH);
end if;
end if;
end if;
end if;
end process TRANSFER_DONE_PROCESS;
-- RECEIVE_DATA_STROBE_PROCESS_OTHER_RATIO: the below process if for other
-------------------------------------------- SPI ratios of C_SCK_RATIO >2
-- -- It multiplexes the data stored
-- -- in internal registers in LSB and
-- -- non-LSB modes, in master as well as
-- -- in slave mode.
RECEIVE_DATA_STROBE_PROCESS_OTHER_RATIO: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE)then
receive_Data_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d1 = '1')then
receive_Data_int <= rx_shft_reg_mode_0011;
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS_OTHER_RATIO;
SPIXfer_done <= SPIXfer_done_int_pulse_d2;
SPIXfer_done_rd_tx_en <= transfer_start_pulse or SPIXfer_done_int_pulse_d2;
--------------------------------------------
end generate RX_DATA_GEN_OTHER_SCK_RATIOS;
-------------------------------------------------------------------------------
-- OTHER_RATIO_GENERATE : Logic to be used when C_SCK_RATIO is not equal to 2
-------------------------
OTHER_RATIO_GENERATE: if(C_SCK_RATIO /= 2) generate
--attribute IOB : string;
--attribute IOB of IO0_I_REG : label is "true";
-----
begin
-----
-------------------------------------------------------------------------------
IO0_I_REG: component FD
generic map
(
INIT => '0'
)
port map
(
Q => mosi_i_sync,
C => Bus2IP_Clk,
D => IO0_I --MOSI_I
);
-----------------------
-- IO1_I_REG_IOB: Push the IO1_I register in IOB
-- --------------
-- Only when the targeted family is 7-series or spartan 6
-- ir-respective of C_USE_STARTUP parameter
-------------
-- IO1_I_REG_IOB: if (C_SUB_FAMILY = "virtex7"
-- or
-- C_SUB_FAMILY = "kintex7"
-- or
-- C_SUB_FAMILY = "artix7"
-- -- or -- 1/23/2013
-- -- C_SUB_FAMILY = "spartan6" -- 1/23/2013
-- )
-- -- or
-- -- (
-- -- C_USE_STARTUP = 0
-- -- and
-- -- C_SUB_FAMILY = "virtex6"
-- -- )
-- generate
-----
--attribute IOB : string;
--attribute IOB of IO1_I_REG : label is "true";
-----
--begin
-----
IO1_I_REG: component FD
generic map
(
INIT => '0'
)
port map
(
Q => miso_i_sync,
C => Bus2IP_Clk,
D => IO1_I -- MISO_I
);
--end generate IO1_I_REG_IOB;
---------------------------
-- -- IO1_I_REG_NO_IOB: If C_USE_STARTUP is used and family is virtex6, then
-- -- IO1_I is registered only, but it is not pushed in IOB.
-- -- this is due to STARTUP block in V6 is having DINSPI interface available for IO1_I.
-- IO1_I_REG_NO_IOB: if ( C_USE_STARTUP = 1
-- and
-- C_SUB_FAMILY = "virtex6"
-- )generate
-- -----
-- begin
-- -----
-- IO1_I_REG: component FD
-- generic map
-- (
-- INIT => '0'
-- )
-- port map
-- (
-- Q => miso_i_sync,
-- C => Bus2IP_Clk,
-- D => IO1_I -- MISO_I
-- );
-- end generate IO1_I_REG_NO_IOB;
-- ------------------------------
NO_IO_x_I_SYNC_MODE_1_GEN: if C_SPI_MODE = 1 generate
-----
begin
-----
io2_i_sync <= '0';
io3_i_sync <= '0';
end generate NO_IO_x_I_SYNC_MODE_1_GEN;
---------------------------------------
IO_x_I_SYNC_MODE_2_GEN: if C_SPI_MODE = 2 generate
----------------
--attribute IOB : string;
--attribute IOB of IO2_I_REG : label is "true";
--attribute IOB of IO3_I_REG : label is "true";
-----
begin
-----
-----------------------
IO2_I_REG: component FD
generic map
(
INIT => '0'
)
port map
(
Q => io2_i_sync,
C => Bus2IP_Clk,
D => IO2_I
);
-----------------------
IO3_I_REG: component FD
generic map
(
INIT => '0'
)
port map
(
Q => io3_i_sync,
C => Bus2IP_Clk,
D => IO3_I
);
-----------------------
end generate IO_x_I_SYNC_MODE_2_GEN;
------------------------------------
-------------------------------------------------------------------------------
-- RATIO_COUNT_PROCESS : Counter which counts from (C_SCK_RATIO/2)-1 down to 0
-- Used for counting the time to control SCK_O_reg generation
-- depending on C_SCK_RATIO
------------------------
OTHER_RATIO_COUNT_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or (transfer_start = '0')) then
Ratio_Count <= CONV_STD_LOGIC_VECTOR(
((C_SCK_RATIO/2)-1),(spcl_log2(C_SCK_RATIO)-1));
else
Ratio_Count <= Ratio_Count - 1;
if (Ratio_Count = 0) then
Ratio_Count <= CONV_STD_LOGIC_VECTOR(
((C_SCK_RATIO/2)-1),(spcl_log2(C_SCK_RATIO)-1));
end if;
end if;
end if;
end process OTHER_RATIO_COUNT_PROCESS;
--------------------------------
-------------------------------------------------------------------------------
-- COUNT_TRIGGER_GEN_PROCESS : Generate a trigger whenever Ratio_Count reaches
-- zero
------------------------------
OTHER_RATIO_COUNT_TRIGGER_GEN_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or
--(SPIXfer_done_int = '1') or
(transfer_start = '0')
) then
Count_trigger <= '0';
elsif(Ratio_Count = 0) then
Count_trigger <= not Count_trigger;
end if;
end if;
end process OTHER_RATIO_COUNT_TRIGGER_GEN_PROCESS;
--------------------------------------
-------------------------------------------------------------------------------
-- COUNT_TRIGGER_1CLK_PROCESS : Delay cnt_trigger signal by 1 clock cycle
-------------------------------
OTHER_RATIO_COUNT_TRIGGER_1CLK_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or (transfer_start = '0')) then
Count_trigger_d1 <= '0';
else
Count_trigger_d1 <= Count_trigger;
end if;
end if;
end process OTHER_RATIO_COUNT_TRIGGER_1CLK_PROCESS;
-- generate a trigger pulse for rising edge as well as falling edge
Count_trigger_pulse <= (Count_trigger and (not(Count_trigger_d1))) or
((not(Count_trigger)) and Count_trigger_d1);
-------------------------------------------------------------------------------
-- SCK_CYCLE_COUNT_PROCESS : Counts number of trigger pulses provided. Used for
-- controlling the number of bits to be transfered
-- based on generic C_NUM_TRANSFER_BITS
----------------------------
OTHER_RATIO_SCK_CYCLE_COUNT_PROCESS: process(Bus2IP_Clk) is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE)or
(SPIXfer_done_int = '1') or
(transfer_start = '0') then
Count <= (others => '0');
--elsif (transfer_start = '0') then
-- Count <= (others => '0');
elsif (Count_trigger_pulse = '1') and (Count(COUNT_WIDTH) = '0') then
Count <= Count + 1;
end if;
end if;
end process OTHER_RATIO_SCK_CYCLE_COUNT_PROCESS;
------------------------------------
-------------------------------------------------------------------------------
-- SCK_SET_RESET_PROCESS : Sync set/reset toggle flip flop controlled by
-- transfer_start signal
--------------------------
OTHER_RATIO_SCK_SET_RESET_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or
(Sync_Reset = '1')
)then
sck_o_int <= '0';
elsif(Sync_Set = '1') then
sck_o_int <= '1';
elsif (transfer_start = '1') then
sck_o_int <= sck_o_int xor Count_trigger_pulse;
end if;
end if;
end process OTHER_RATIO_SCK_SET_RESET_PROCESS;
----------------------------------
-- DELAY_CLK: Delay the internal clock for a cycle to generate internal enable
-- -- signal for data register.
-------------
OTHER_RATIO_DELAY_CLK: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (Soft_Reset_op = RESET_ACTIVE)then
sck_d1 <= '0';
sck_d2 <= '0';
else
sck_d1 <= sck_o_int;
sck_d2 <= sck_d1;
end if;
end if;
end process OTHER_RATIO_DELAY_CLK;
------------------------------------
-- Rising egde pulse for CPHA-CPOL = 00/11 mode
sck_rising_edge <= not(sck_d2) and sck_d1;
-- CAPT_RX_FE_MODE_00_11: The below logic is the date registery process for
------------------------- SPI CPHA-CPOL modes of 00 and 11.
OTHER_RATIO_CAPT_RX_FE_MODE_00_11 : process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (Soft_Reset_op = RESET_ACTIVE)then
rx_shft_reg_mode_0011 <= (others => '0');
elsif((sck_rising_edge = '1') and
(transfer_start = '1') and
(Data_Dir='0') -- data direction = 0 is read mode
--(pr_state_data_receive = '1')
) then
-------
if(mode_1 = '0' and mode_0 = '0')then -- for Standard transfer
rx_shft_reg_mode_0011<= rx_shft_reg_mode_0011
(1 to (C_NUM_TRANSFER_BITS-1)) &
IO1_I;-- MISO_I
elsif((mode_1 = '0' and mode_0 = '1') -- for Dual transfer
)then
rx_shft_reg_mode_0011<= rx_shft_reg_mode_0011
(2 to (C_NUM_TRANSFER_BITS-1)) &
IO1_I &-- MSB first
IO0_I;
elsif((mode_1 = '1' and mode_0 = '0') -- for Quad transfer
)then
rx_shft_reg_mode_0011<= rx_shft_reg_mode_0011
(4 to (C_NUM_TRANSFER_BITS-1)) &
IO3_I & -- MSB first
IO2_I &
IO1_I &
IO0_I;
end if;
-------
else
rx_shft_reg_mode_0011<= rx_shft_reg_mode_0011;
end if;
end if;
end process OTHER_RATIO_CAPT_RX_FE_MODE_00_11;
---------------------------------------------------------------------
-------------------------------------------------------------------------------
-- CAPTURE_AND_SHIFT_PROCESS : This logic essentially controls the entire
-- capture and shift operation for serial data
------------------------------
OTHER_RATIO_CAP_QSPI_QUAD_MODE_NM_MEM_GEN: if (
(C_SPI_MODE = 2 or
C_SPI_MODE = 1) and
(C_SPI_MEMORY = 2)
)generate
--------------------------------------
begin
-----
OTHER_RATIO_CAPTURE_AND_SHIFT_PROCESS: process(Bus2IP_Clk) is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
Shift_Reg(0 to C_NUM_TRANSFER_BITS -1) <= (others => '0');
Serial_Dout_0 <= '0';-- default values of the IO0_O
Serial_Dout_1 <= '0';
Serial_Dout_2 <= '0';
Serial_Dout_3 <= '0';
else--if(
-- (transfer_start = '1') and (not(Count(COUNT_WIDTH) = '1'))) then
--if(Load_tx_data_to_shift_reg_int = '1') then
if(transfer_start_pulse = '1' or SPIXfer_done_int_d1 = '1') then
Shift_Reg <= Transmit_Data;-- loading trasmit data in SR
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Transmit_Data(0);
Serial_Dout_3 <= pr_state_cmd_ph and Quad_Phase;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Transmit_Data(0); -- msb to IO1_O
Serial_Dout_0 <= Transmit_Data(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Transmit_Data(0); -- msb to IO3_O
Serial_Dout_2 <= Transmit_Data(1);
Serial_Dout_1 <= Transmit_Data(2);
Serial_Dout_0 <= Transmit_Data(3);
end if;
-- Capture Data on even Count
elsif(
(Count(0) = '0')
)then
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Shift_Reg(0);
Serial_Dout_3 <= pr_state_cmd_ph and Quad_Phase;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Shift_Reg(0); -- msb to IO1_O
Serial_Dout_0 <= Shift_Reg(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Shift_Reg(0); -- msb to IO3_O
Serial_Dout_2 <= Shift_Reg(1);
Serial_Dout_1 <= Shift_Reg(2);
Serial_Dout_0 <= Shift_Reg(3);
end if;
-- Shift Data on odd Count
elsif(
(Count(0) = '1') and
(Count_trigger_pulse = '1')
) then
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Shift_Reg <= Shift_Reg
(1 to C_NUM_TRANSFER_BITS -1) & IO1_I;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Shift_Reg <= Shift_Reg
(2 to C_NUM_TRANSFER_BITS -1) & IO1_I
& IO0_I;
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Shift_Reg <= Shift_Reg
(4 to C_NUM_TRANSFER_BITS -1) & IO3_I
& IO2_I
& IO1_I
& IO0_I;
end if;
end if;
end if;
end if;
end process OTHER_RATIO_CAPTURE_AND_SHIFT_PROCESS;
--------------------------------------------------
end generate OTHER_RATIO_CAP_QSPI_QUAD_MODE_NM_MEM_GEN;
-------------------------------------------------------
OTHER_RATIO_CAP_QSPI_QUAD_MODE_SP_MEM_GEN: if (
(C_SPI_MODE = 2 or
C_SPI_MODE = 1) and
(
C_SPI_MEMORY = 3)
)generate
--------------------------------------
begin
-----
OTHER_RATIO_CAPTURE_AND_SHIFT_PROCESS: process(Bus2IP_Clk) is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
Shift_Reg(0 to C_NUM_TRANSFER_BITS -1) <= (others => '0');
Serial_Dout_0 <= '0';-- default values of the IO0_O
Serial_Dout_1 <= '0';
Serial_Dout_2 <= '0';
Serial_Dout_3 <= '0';
else--if(
-- (transfer_start = '1') and (not(Count(COUNT_WIDTH) = '1'))) then
--if(Load_tx_data_to_shift_reg_int = '1') then
if(transfer_start_pulse = '1' or SPIXfer_done_int_d1 = '1') then
Shift_Reg <= Transmit_Data;-- loading trasmit data in SR
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Transmit_Data(0);
Serial_Dout_3 <= pr_state_cmd_ph and Quad_Phase;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Transmit_Data(0); -- msb to IO1_O
Serial_Dout_0 <= Transmit_Data(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Transmit_Data(0); -- msb to IO3_O
Serial_Dout_2 <= Transmit_Data(1);
Serial_Dout_1 <= Transmit_Data(2);
Serial_Dout_0 <= Transmit_Data(3);
end if;
-- Capture Data on even Count
elsif(
(Count(0) = '0')
)then
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Shift_Reg(0);
Serial_Dout_3 <= pr_state_cmd_ph and Quad_Phase;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Shift_Reg(0); -- msb to IO1_O
Serial_Dout_0 <= Shift_Reg(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Shift_Reg(0); -- msb to IO3_O
Serial_Dout_2 <= Shift_Reg(1);
Serial_Dout_1 <= Shift_Reg(2);
Serial_Dout_0 <= Shift_Reg(3);
end if;
-- Shift Data on odd Count
elsif(
(Count(0) = '1') and
(Count_trigger_pulse = '1')
) then
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Shift_Reg <= Shift_Reg
(1 to C_NUM_TRANSFER_BITS -1) & IO1_I;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Shift_Reg <= Shift_Reg
(2 to C_NUM_TRANSFER_BITS -1) & IO1_I
& IO0_I;
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Shift_Reg <= Shift_Reg
(4 to C_NUM_TRANSFER_BITS -1) & IO3_I
& IO2_I
& IO1_I
& IO0_I;
end if;
end if;
end if;
end if;
end process OTHER_RATIO_CAPTURE_AND_SHIFT_PROCESS;
--------------------------------------------------
end generate OTHER_RATIO_CAP_QSPI_QUAD_MODE_SP_MEM_GEN;
-------------------------------------------------------
OTHER_RATIO_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN: if (
(C_SPI_MODE = 2 and
(C_SPI_MEMORY = 0
or
C_SPI_MEMORY = 1)
)
or
(C_SPI_MODE = 1 and
(C_SPI_MEMORY = 0
or
C_SPI_MEMORY = 1)
)
)generate
--------------------------------------
begin
-----
OTHER_RATIO_CAPTURE_AND_SHIFT_PROCESS: process(Bus2IP_Clk) is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
Shift_Reg(0 to C_NUM_TRANSFER_BITS -1) <= (others => '0');
Serial_Dout_0 <= '0';-- default values of the IO0_O
Serial_Dout_1 <= '0';
Serial_Dout_2 <= '0';
Serial_Dout_3 <= '0';
else--if(
-- (transfer_start = '1') and (not(Count(COUNT_WIDTH) = '1'))) then
--if(Load_tx_data_to_shift_reg_int = '1') then
if(transfer_start_pulse = '1' or SPIXfer_done_int_d1 = '1')then
Shift_Reg <= Transmit_Data;-- loading trasmit data in SR
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Transmit_Data(0);
Serial_Dout_3 <= pr_state_cmd_ph and Quad_Phase;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Transmit_Data(0); -- msb to IO1_O
Serial_Dout_0 <= Transmit_Data(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Transmit_Data(0); -- msb to IO3_O
Serial_Dout_2 <= Transmit_Data(1);
Serial_Dout_1 <= Transmit_Data(2);
Serial_Dout_0 <= Transmit_Data(3);
end if;
-- Capture Data on even Count
elsif(
(Count(0) = '0')
)then
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Shift_Reg(0);
Serial_Dout_3 <= pr_state_cmd_ph and Quad_Phase;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Shift_Reg(0); -- msb to IO1_O
Serial_Dout_0 <= Shift_Reg(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Shift_Reg(0); -- msb to IO3_O
Serial_Dout_2 <= Shift_Reg(1);
Serial_Dout_1 <= Shift_Reg(2);
Serial_Dout_0 <= Shift_Reg(3);
end if;
-- Shift Data on odd Count
elsif(
(Count(0) = '1') and
(Count_trigger_pulse = '1')
) then
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Shift_Reg <= Shift_Reg
(1 to C_NUM_TRANSFER_BITS -1) & IO1_I;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Shift_Reg <= Shift_Reg
(2 to C_NUM_TRANSFER_BITS -1) & IO1_I
& IO0_I;
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Shift_Reg <= Shift_Reg
(4 to C_NUM_TRANSFER_BITS -1) & IO3_I
& IO2_I
& IO1_I
& IO0_I;
end if;
end if;
end if;
end if;
end process OTHER_RATIO_CAPTURE_AND_SHIFT_PROCESS;
--------------------------------------------------
end generate OTHER_RATIO_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN;
-------------------------------------------------------
end generate OTHER_RATIO_GENERATE;
----------------------------------
--------------------------------------------------
PS_TO_NS_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
qspi_cntrl_ps <= IDLE;
stop_clock_reg <= '0';
else
qspi_cntrl_ps <= qspi_cntrl_ns;
stop_clock_reg <= stop_clock;
end if;
end if;
end process PS_TO_NS_PROCESS;
-----------------------------
pr_state_data_receive <= '1' when qspi_cntrl_ps = DATA_RECEIVE else
'0';
pr_state_non_idle <= '1' when qspi_cntrl_ps /= IDLE else
'0';
pr_state_idle <= '1' when qspi_cntrl_ps = IDLE else
'0';
pr_state_cmd_ph <= '1' when qspi_cntrl_ps = CMD_SEND else
'0';
--------------------------------
QSPI_DUAL_MODE_MIXED_WB_MEM_GEN: if (C_SPI_MODE = 1 and
(
C_SPI_MEMORY = 0 or
C_SPI_MEMORY = 1
)
)generate
--------------------------------
begin
-----
QSPI_CNTRL_PROCESS: process(
---------------------
CMD_decoded ,
CMD_Mode_1 ,
CMD_Mode_0 ,
CMD_Error ,
---------------------
Addr_Phase ,
Addr_Bit ,
Addr_Mode_1 ,
Addr_Mode_0 ,
---------------------
Data_Phase ,
Data_Dir ,
Data_Mode_1 ,
Data_Mode_0 ,
---------------------
addr_cnt ,
Quad_Phase ,
---------------------
SR_5_Tx_Empty ,
--SR_6_Rx_Full ,
--SPIXfer_done_int_pulse_d2,
SPIXfer_done_int_pulse,
stop_clock_reg,
---------------------
qspi_cntrl_ps ,
no_slave_selected
---------------------
)is
-----
begin
-----
mode_1 <= '0';
mode_0 <= '0';
--------------
IO0_T_control <= '1';
IO1_T_control <= '1';
-------------
stop_clock <= '0';
case qspi_cntrl_ps is
when IDLE => if((CMD_decoded = '1') and
(CMD_Error = '0')-- proceed only when there is no command error
)then
qspi_cntrl_ns <= CMD_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
stop_clock <= '1';
------------------------------------------------
when CMD_SEND => mode_1 <= CMD_Mode_1;
mode_0 <= CMD_Mode_0;
IO0_T_control <= CMD_Mode_0;
IO1_T_control <= (CMD_Mode_1) or (not CMD_Mode_0);
--if(SPIXfer_done_int_pulse_d2 = '1')then
if(SPIXfer_done_int_pulse = '1')then
if(Addr_Phase='1')then
if(SR_5_Tx_Empty = '1') then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
else
qspi_cntrl_ns <= IDLE;
end if;
else
qspi_cntrl_ns <= CMD_SEND;
end if;
------------------------------------------------
when ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);-- (Addr_Mode_1) or(not Addr_Mode_0);
--stop_clock <= not SR_5_Tx_Empty;
if((SR_5_Tx_Empty='1') and
(Data_Phase='0')
)then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
if(
(addr_cnt = "011") and -- 24 bit address
(Addr_Bit='0') and (Data_Phase='1')
)then
IO0_T_control <= '1';
IO1_T_control <= '1';
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
end if;
------------------------------------------------
when TEMP_ADDR_SEND => --if((SPIXfer_done_int_pulse='1')
-- )then
-- if (no_slave_selected = '1')then
-- qspi_cntrl_ns <= IDLE;
-- else
-- stop_clock <= SR_5_Tx_Empty;
-- if(SR_5_Tx_Empty='1')then
-- qspi_cntrl_ns <= TEMP_ADDR_SEND;
-- else
-- qspi_cntrl_ns <= ADDR_SEND;
-- end if;
-- end if;
--else
-- qspi_cntrl_ns <= TEMP_ADDR_SEND;
--end if;
mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);-- (Addr_Mode_1) or(not Addr_Mode_0);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= ADDR_SEND;
end if;
when DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
--stop_clock <= SR_5_Tx_Empty;
--if(no_slave_selected = '1')then
-- qspi_cntrl_ns <= IDLE;
--else
-- qspi_cntrl_ns <= DATA_RECEIVE;
--end if;
if(SR_5_Tx_Empty='1')then
if(no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
------------------------------------------------
when TEMP_DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
else
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
-- coverage off
when others => qspi_cntrl_ns <= IDLE;
------------------------------------------------
-- coverage on
end case;
-------------------------------
end process QSPI_CNTRL_PROCESS;
-------------------------------
pr_state_addr_ph <= '1' when (qspi_cntrl_ps = ADDR_SEND) else
'0';
QSPI_ADDR_CNTR_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(pr_state_addr_ph = '0') then
addr_cnt <= (others => '0');
elsif(pr_state_addr_ph = '1')then
--addr_cnt <= addr_cnt + SPIXfer_done_int_pulse_d2;
addr_cnt <= addr_cnt + SPIXfer_done_int_pulse;
end if;
end if;
end process QSPI_ADDR_CNTR_PROCESS;
-----------------------------------
end generate QSPI_DUAL_MODE_MIXED_WB_MEM_GEN;
------------------------------------------
--------------------------------------------------
QSPI_QUAD_MODE_MIXED_WB_MEM_GEN: if (C_SPI_MODE = 2 and
(C_SPI_MEMORY = 1 or
C_SPI_MEMORY = 0
)
)
generate
-------------------
begin
-----
QSPI_CNTRL_PROCESS: process(
---------------------
CMD_decoded ,
CMD_Error ,
CMD_Mode_1 ,
CMD_Mode_0 ,
---------------------
Addr_Phase ,
Addr_Bit ,
Addr_Mode_1 ,
Addr_Mode_0 ,
---------------------
Data_Phase ,
Data_Dir ,
Data_Mode_1 ,
Data_Mode_0 ,
---------------------
addr_cnt ,
Quad_Phase ,
---------------------
SR_5_Tx_Empty ,
--SR_6_Rx_Full ,
--SPIXfer_done_int_pulse_d2,
SPIXfer_done_int_pulse,
stop_clock_reg,
---------------------
qspi_cntrl_ps ,
no_slave_selected
---------------------
)is
-----
begin
-----
mode_1 <= '0';
mode_0 <= '0';
--------------
IO0_T_control <= '1';
IO1_T_control <= '1';
IO2_T_control <= '1';
IO3_T_control <= '1';
--------------
stop_clock <= '0';
case qspi_cntrl_ps is
when IDLE => if((CMD_decoded = '1') and
(CMD_Error = '0')-- proceed only when there is no command error
)then
qspi_cntrl_ns <= CMD_SEND;
else
qspi_cntrl_ns <= IDLE; -- CMD_DECODE;
end if;
stop_clock <= '1';
------------------------------------------------
when CMD_SEND => mode_1 <= CMD_Mode_1;
mode_0 <= CMD_Mode_0;
IO0_T_control <= CMD_Mode_0;
IO3_T_control <= not Quad_Phase;--
--if(SPIXfer_done_int_pulse_d2 = '1')then
if(SPIXfer_done_int_pulse = '1')then
if(Addr_Phase='1')then
if(SR_5_Tx_Empty = '1') then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
else
qspi_cntrl_ns <= IDLE;
end if;
else
qspi_cntrl_ns <= CMD_SEND;
end if;
------------------------------------------------
when ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);
IO2_T_control <= (not Addr_Mode_1);
IO3_T_control <= (not Addr_Mode_1);
--stop_clock <= SR_5_Tx_Empty;
if((SR_5_Tx_Empty='1') and
(Data_Phase='0')
)then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
if(
(addr_cnt = "011") and -- 24 bit address
(Addr_Bit='0') and(Data_Phase='1')
)then
if((Data_Dir='1'))then
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0'; -- data output
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);-- active only
IO3_T_control <= not (Data_Mode_1);-- active only
qspi_cntrl_ns <= DATA_SEND; -- o/p
else
IO0_T_control <= '1';
IO1_T_control <= '1';
IO2_T_control <= '1';
IO3_T_control <= '1';
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
end if;
-- -- coverage off
-- -- below piece of code is for 32-bit address check, and left for future use
-- elsif(
-- (addr_cnt = "100") and -- 32 bit
-- (Addr_Bit = '1') and (Data_Phase='1')
-- )then
-- if((Data_Dir='1'))then
-- qspi_cntrl_ns <= DATA_SEND; -- o/p
-- else
-- qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
-- end if;
-- -- coverage on
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
end if;
------------------------------------------------
when TEMP_ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);
IO2_T_control <= (not Addr_Mode_1);
IO3_T_control <= (not Addr_Mode_1);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= ADDR_SEND;
end if;
-----------------------------------------------------------------------
when DATA_SEND => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0'; -- data output active only in Dual mode
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);-- active only in quad mode
IO3_T_control <= not (Data_Mode_1);-- active only in quad mode
--stop_clock <= SR_5_Tx_Empty;
if(SR_5_Tx_Empty='1')then
if(no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
else
qspi_cntrl_ns <= DATA_SEND;
end if;
------------------------------------------------
when TEMP_DATA_SEND => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0'; -- data output active only in Dual mode
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);-- active only in quad mode
IO3_T_control <= not (Data_Mode_1);-- active only in quad mode
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_SEND;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_SEND;
end if;
when DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
--stop_clock <= SR_5_Tx_Empty;
if(SR_5_Tx_Empty='1')then
if(no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
------------------------------------------------
when TEMP_DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
else
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
------------------------------------------------
-- coverage off
when others => qspi_cntrl_ns <= IDLE;
------------------------------------------------
-- coverage on
end case;
-------------------------------
end process QSPI_CNTRL_PROCESS;
-------------------------------
pr_state_addr_ph <= '1' when qspi_cntrl_ps = ADDR_SEND else
'0';
QSPI_ADDR_CNTR_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(pr_state_addr_ph = '0') then
addr_cnt <= (others => '0');
elsif(pr_state_addr_ph = '1')then
--addr_cnt <= addr_cnt + SPIXfer_done_int_pulse_d2;
addr_cnt <= addr_cnt + SPIXfer_done_int_pulse;
end if;
end if;
end process QSPI_ADDR_CNTR_PROCESS;
-----------------------------------
------------------------------------------
end generate QSPI_QUAD_MODE_MIXED_WB_MEM_GEN;
------------------------------------------
--------------------------------------------------
QSPI_DUAL_MODE_NM_MEM_GEN: if C_SPI_MODE = 1 and (C_SPI_MEMORY = 2 ) generate
-------------------
begin
-----
QSPI_CNTRL_PROCESS: process(
---------------------
CMD_decoded ,
CMD_Mode_1 ,
CMD_Mode_0 ,
CMD_Error ,
---------------------
Addr_Phase ,
Addr_Bit ,
Addr_Mode_1 ,
Addr_Mode_0 ,
---------------------
Data_Phase ,
Data_Dir ,
Data_Mode_1 ,
Data_Mode_0 ,
---------------------
addr_cnt ,
---------------------
SR_5_Tx_Empty ,
--SR_6_Rx_Full ,
--SPIXfer_done_int_pulse_d2,
SPIXfer_done_int_pulse,
stop_clock_reg,
no_slave_selected ,
---------------------
qspi_cntrl_ps
---------------------
)is
-----
begin
-----
mode_1 <= '0';
mode_0 <= '0';
--------------
IO0_T_control <= '1';
IO1_T_control <= '1';
--------------
stop_clock <= '0';
--------------
case qspi_cntrl_ps is
when IDLE => if((CMD_decoded = '1') and
(CMD_Error = '0')-- proceed only when there is no command error
)then
qspi_cntrl_ns <= CMD_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
stop_clock <= '1';
------------------------------------------------
when CMD_SEND => mode_1 <= CMD_Mode_1;
mode_0 <= CMD_Mode_0;
IO0_T_control <= CMD_Mode_1;
--if(SPIXfer_done_int_pulse_d2 = '1')then
if(SPIXfer_done_int_pulse = '1')then
if(Addr_Phase='1')then
if(SR_5_Tx_Empty = '1') then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
else
qspi_cntrl_ns <= IDLE;
end if;
else
qspi_cntrl_ns <= CMD_SEND;
end if;
------------------------------------------------
when ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0);
--stop_clock <= SR_5_Tx_Empty;
if((SR_5_Tx_Empty='1') and
(Data_Phase='0')
)then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
if(
(addr_cnt = "011") and -- 24 bit address
(Addr_Bit='0') and (Data_Phase='1')
)then
if((Data_Dir='1'))then
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= Data_Mode_1;
IO1_T_control <= not(Data_Mode_0);
qspi_cntrl_ns <= DATA_SEND; -- o/p
else
IO0_T_control <= '1';
IO1_T_control <= '1';
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
end if;
elsif(
(addr_cnt = "100") and -- 32 bit
(Addr_Bit = '1') and (Data_Phase='1')
) then
--if((Data_Dir='1'))then
-- qspi_cntrl_ns <= DATA_SEND; -- o/p
--else
IO0_T_control <= '1';
IO1_T_control <= '1';
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
--end if;
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
end if;
-- ------------------------------------------------
when TEMP_ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);-- (Addr_Mode_1) or(not Addr_Mode_0);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= ADDR_SEND;
end if;
when DATA_SEND => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= Data_Mode_1;
IO1_T_control <= not(Data_Mode_0);
--stop_clock <= SR_5_Tx_Empty;
if(no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
------------------------------------------------
when TEMP_DATA_SEND =>
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= Data_Mode_1;
IO1_T_control <= not(Data_Mode_0);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_SEND;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_SEND;
end if;
when DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
--stop_clock <= SR_5_Tx_Empty;
if(SR_5_Tx_Empty='1')then
if(no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
------------------------------------------------
when TEMP_DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
else
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
-- coverage off
when others => qspi_cntrl_ns <= IDLE;
------------------------------------------------
-- coverage on
end case;
-------------------------------
end process QSPI_CNTRL_PROCESS;
-------------------------------
pr_state_addr_ph <= '1' when qspi_cntrl_ps = ADDR_SEND else
'0';
QSPI_ADDR_CNTR_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(pr_state_addr_ph = '0') then
addr_cnt <= (others => '0');
elsif(pr_state_addr_ph = '1')then
--addr_cnt <= addr_cnt + SPIXfer_done_int_pulse_d2;
addr_cnt <= addr_cnt + SPIXfer_done_int_pulse;
end if;
end if;
end process QSPI_ADDR_CNTR_PROCESS;
-----------------------------------
end generate QSPI_DUAL_MODE_NM_MEM_GEN;
--------------------------------
QSPI_DUAL_MODE_SP_MEM_GEN: if C_SPI_MODE = 1 and (C_SPI_MEMORY = 3) generate
-------------------
begin
-----
QSPI_CNTRL_PROCESS: process(
---------------------
CMD_decoded ,
CMD_Mode_1 ,
CMD_Mode_0 ,
CMD_Error ,
---------------------
Addr_Phase ,
Addr_Bit ,
Addr_Mode_1 ,
Addr_Mode_0 ,
---------------------
Data_Phase ,
Data_Dir ,
Data_Mode_1 ,
Data_Mode_0 ,
---------------------
addr_cnt ,
---------------------
SR_5_Tx_Empty ,
--SR_6_Rx_Full ,
--SPIXfer_done_int_pulse_d2,
SPIXfer_done_int_pulse,
stop_clock_reg,
no_slave_selected ,
---------------------
qspi_cntrl_ps
---------------------
)is
-----
begin
-----
mode_1 <= '0';
mode_0 <= '0';
--------------
IO0_T_control <= '1';
IO1_T_control <= '1';
--------------
stop_clock <= '0';
--------------
case qspi_cntrl_ps is
when IDLE => if((CMD_decoded = '1') and
(CMD_Error = '0')-- proceed only when there is no command error
)then
qspi_cntrl_ns <= CMD_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
stop_clock <= '1';
------------------------------------------------
when CMD_SEND => mode_1 <= CMD_Mode_1;
mode_0 <= CMD_Mode_0;
IO0_T_control <= CMD_Mode_1;
--if(SPIXfer_done_int_pulse_d2 = '1')then
if(SPIXfer_done_int_pulse = '1')then
if(Addr_Phase='1')then
if(SR_5_Tx_Empty = '1') then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
else
qspi_cntrl_ns <= IDLE;
end if;
else
qspi_cntrl_ns <= CMD_SEND;
end if;
------------------------------------------------
when ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0);
--stop_clock <= SR_5_Tx_Empty;
if((SR_5_Tx_Empty='1') and
(Data_Phase='0')
)then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
if(
(addr_cnt = "011") and -- 24 bit address
(Addr_Bit='0') and (Data_Phase='1')
)then
if((Data_Dir='1'))then
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= Data_Mode_1;
IO1_T_control <= not(Data_Mode_0);
qspi_cntrl_ns <= DATA_SEND; -- o/p
else
IO0_T_control <= '1';
IO1_T_control <= '1';
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
end if;
elsif(
(addr_cnt = "100") and -- 32 bit
(Addr_Bit = '1') and (Data_Phase='1')
) then
--if((Data_Dir='1'))then
-- qspi_cntrl_ns <= DATA_SEND; -- o/p
--else
IO0_T_control <= '1';
IO1_T_control <= '1';
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
--end if;
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
end if;
-- ------------------------------------------------
when TEMP_ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);-- (Addr_Mode_1) or(not Addr_Mode_0);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= ADDR_SEND;
end if;
when DATA_SEND => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= Data_Mode_1;
IO1_T_control <= not(Data_Mode_0);
--stop_clock <= SR_5_Tx_Empty;
if(no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
------------------------------------------------
when TEMP_DATA_SEND =>
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= Data_Mode_1;
IO1_T_control <= not(Data_Mode_0);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_SEND;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_SEND;
end if;
when DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
--stop_clock <= SR_5_Tx_Empty;
if(SR_5_Tx_Empty='1')then
if(no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
------------------------------------------------
when TEMP_DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
else
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
-- coverage off
when others => qspi_cntrl_ns <= IDLE;
------------------------------------------------
-- coverage on
end case;
-------------------------------
end process QSPI_CNTRL_PROCESS;
-------------------------------
pr_state_addr_ph <= '1' when qspi_cntrl_ps = ADDR_SEND else
'0';
QSPI_ADDR_CNTR_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(pr_state_addr_ph = '0') then
addr_cnt <= (others => '0');
elsif(pr_state_addr_ph = '1')then
--addr_cnt <= addr_cnt + SPIXfer_done_int_pulse_d2;
addr_cnt <= addr_cnt + SPIXfer_done_int_pulse;
end if;
end if;
end process QSPI_ADDR_CNTR_PROCESS;
-----------------------------------
end generate QSPI_DUAL_MODE_SP_MEM_GEN;
--------------------------------
--------------------------------------------------
QSPI_QUAD_MODE_NM_MEM_GEN: if C_SPI_MODE = 2 and (C_SPI_MEMORY = 2 )generate
-------------------
begin
-----
QSPI_CNTRL_PROCESS: process(
---------------------
CMD_decoded ,
CMD_Mode_1 ,
CMD_Mode_0 ,
CMD_Error ,
---------------------
Addr_Phase ,
Addr_Bit ,
Addr_Mode_1 ,
Addr_Mode_0 ,
---------------------
Data_Phase ,
Data_Dir ,
Data_Mode_1 ,
Data_Mode_0 ,
---------------------
addr_cnt ,
Quad_Phase ,
---------------------
SR_5_Tx_Empty ,
--SPIXfer_done_int_pulse_d2,
SPIXfer_done_int_pulse,
stop_clock_reg,
no_slave_selected ,
---------------------
qspi_cntrl_ps
---------------------
)is
-----
begin
-----
mode_1 <= '0';
mode_0 <= '0';
--------------
IO0_T_control <= '1';
IO1_T_control <= '1';
IO2_T_control <= '1';
IO3_T_control <= '1';
-------------
stop_clock <= '0';
case qspi_cntrl_ps is
when IDLE => if((CMD_decoded = '1') and
(CMD_Error = '0')-- proceed only when there is no command error
)then
qspi_cntrl_ns <= CMD_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
stop_clock <= '1';
------------------------------------------------
when CMD_SEND => mode_1 <= CMD_Mode_1;
mode_0 <= CMD_Mode_0;
IO0_T_control <= CMD_Mode_0;
IO3_T_control <= not Quad_Phase;-- this is due to sending '1' on DQ3 line during command phase for Quad instructions only.
--if(SPIXfer_done_int_pulse_d2 = '1')then
if(SPIXfer_done_int_pulse = '1')then
if(Addr_Phase='1')then
if(SR_5_Tx_Empty = '1') then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
else
qspi_cntrl_ns <= IDLE;
end if;
else
qspi_cntrl_ns <= CMD_SEND;
end if;
------------------------------------------------
when ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);
IO2_T_control <= (not Addr_Mode_1);
IO3_T_control <= (not Addr_Mode_1);
--stop_clock <= SR_5_Tx_Empty;
if((SR_5_Tx_Empty='1') and
(Data_Phase='0')
)then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
if(
(addr_cnt = "011") and -- 24 bit address
(Addr_Bit='0') and
(Data_Phase='1')
)then
if((Data_Dir='1'))then
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0';
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);
IO3_T_control <= not (Data_Mode_1);
qspi_cntrl_ns <= DATA_SEND; -- o/p
else
--mode_1 <= Data_Mode_1;
--mode_0 <= Data_Mode_0;
IO0_T_control <= '1';
IO1_T_control <= '1';
IO2_T_control <= '1';
IO3_T_control <= '1';
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
end if;
elsif(
(addr_cnt = "100") and -- 32 bit
(Addr_Bit = '1') and
(Data_Phase='1')
) then
--if((Data_Dir='1'))then
-- qspi_cntrl_ns <= DATA_SEND; -- o/p
--else
IO0_T_control <= '1';
IO1_T_control <= '1';
IO2_T_control <= '1';
IO3_T_control <= '1';
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
--end if;
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
end if;
-- ------------------------------------------------
when TEMP_ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);
IO2_T_control <= (not Addr_Mode_1);
IO3_T_control <= (not Addr_Mode_1);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= ADDR_SEND;
end if;
when DATA_SEND => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0';
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);
IO3_T_control <= not (Data_Mode_1);
--stop_clock <= SR_5_Tx_Empty;
if(SR_5_Tx_Empty='1')then
if(no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
else
qspi_cntrl_ns <= DATA_SEND;
end if;
------------------------------------------------
when TEMP_DATA_SEND=> mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0';
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);
IO3_T_control <= not (Data_Mode_1);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_SEND;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_SEND;
end if;
when DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
--stop_clock <= SR_5_Tx_Empty;
if(SR_5_Tx_Empty='1')then
if(no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
------------------------------------------------
when TEMP_DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
else
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
------------------------------------------------
-- coverage off
when others => qspi_cntrl_ns <= IDLE; -- CMD_DECODE;
------------------------------------------------
-- coverage on
end case;
-------------------------------
end process QSPI_CNTRL_PROCESS;
-------------------------------
pr_state_addr_ph <= '1' when qspi_cntrl_ps = ADDR_SEND else
'0';
QSPI_ADDR_CNTR_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(pr_state_addr_ph = '0') then
addr_cnt <= (others => '0');
elsif(pr_state_addr_ph = '1')then
--addr_cnt <= addr_cnt + SPIXfer_done_int_pulse_d2;
addr_cnt <= addr_cnt + SPIXfer_done_int_pulse;
end if;
end if;
end process QSPI_ADDR_CNTR_PROCESS;
-----------------------------------
end generate QSPI_QUAD_MODE_NM_MEM_GEN;
---------------------------------------
QSPI_QUAD_MODE_SP_MEM_GEN: if C_SPI_MODE = 2 and (C_SPI_MEMORY = 3)generate
-------------------
begin
-----
QSPI_CNTRL_PROCESS: process(
---------------------
CMD_decoded ,
CMD_Mode_1 ,
CMD_Mode_0 ,
CMD_Error ,
---------------------
Addr_Phase ,
Addr_Bit ,
Addr_Mode_1 ,
Addr_Mode_0 ,
---------------------
Data_Phase ,
Data_Dir ,
Data_Mode_1 ,
Data_Mode_0 ,
---------------------
addr_cnt ,
Quad_Phase ,
---------------------
SR_5_Tx_Empty ,
--SPIXfer_done_int_pulse_d2,
SPIXfer_done_int_pulse,
stop_clock_reg,
no_slave_selected ,
---------------------
qspi_cntrl_ps
---------------------
)is
-----
begin
-----
mode_1 <= '0';
mode_0 <= '0';
--------------
IO0_T_control <= '1';
IO1_T_control <= '1';
IO2_T_control <= '1';
IO3_T_control <= '1';
-------------
stop_clock <= '0';
case qspi_cntrl_ps is
when IDLE => if((CMD_decoded = '1') and
(CMD_Error = '0')-- proceed only when there is no command error
)then
qspi_cntrl_ns <= CMD_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
stop_clock <= '1';
------------------------------------------------
when CMD_SEND => mode_1 <= CMD_Mode_1;
mode_0 <= CMD_Mode_0;
IO0_T_control <= CMD_Mode_0;
IO3_T_control <= not Quad_Phase;-- this is due to sending '1' on DQ3 line during command phase for Quad instructions only.
--if(SPIXfer_done_int_pulse_d2 = '1')then
if(SPIXfer_done_int_pulse = '1')then
if(Addr_Phase='1')then
if(SR_5_Tx_Empty = '1') then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
else
qspi_cntrl_ns <= IDLE;
end if;
else
qspi_cntrl_ns <= CMD_SEND;
end if;
------------------------------------------------
when ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);
IO2_T_control <= (not Addr_Mode_1);
IO3_T_control <= (not Addr_Mode_1);
--stop_clock <= SR_5_Tx_Empty;
if((SR_5_Tx_Empty='1') and
(Data_Phase='0')
)then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
if(
(addr_cnt = "011") and -- 24 bit address
(Addr_Bit='0') and
(Data_Phase='1')
)then
if((Data_Dir='1'))then
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0';
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);
IO3_T_control <= not (Data_Mode_1);
qspi_cntrl_ns <= DATA_SEND; -- o/p
else
--mode_1 <= Data_Mode_1;
--mode_0 <= Data_Mode_0;
IO0_T_control <= '1';
IO1_T_control <= '1';
IO2_T_control <= '1';
IO3_T_control <= '1';
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
end if;
elsif(
(addr_cnt = "100") and -- 32 bit
(Addr_Bit = '1') and
(Data_Phase='1')
) then
if((Data_Dir='1'))then
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0';
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);
IO3_T_control <= not (Data_Mode_1);
qspi_cntrl_ns <= DATA_SEND; -- o/p
else
IO0_T_control <= '1';
IO1_T_control <= '1';
IO2_T_control <= '1';
IO3_T_control <= '1';
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
end if;
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
end if;
-- ------------------------------------------------
when TEMP_ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);
IO2_T_control <= (not Addr_Mode_1);
IO3_T_control <= (not Addr_Mode_1);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= ADDR_SEND;
end if;
when DATA_SEND => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0';
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);
IO3_T_control <= not (Data_Mode_1);
--stop_clock <= SR_5_Tx_Empty;
if(SR_5_Tx_Empty='1')then
if(no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
else
qspi_cntrl_ns <= DATA_SEND;
end if;
------------------------------------------------
when TEMP_DATA_SEND=> mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0';
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);
IO3_T_control <= not (Data_Mode_1);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_SEND;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_SEND;
end if;
when DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
--stop_clock <= SR_5_Tx_Empty;
if(SR_5_Tx_Empty='1')then
if(no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
------------------------------------------------
when TEMP_DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
else
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
------------------------------------------------
-- coverage off
when others => qspi_cntrl_ns <= IDLE; -- CMD_DECODE;
------------------------------------------------
-- coverage on
end case;
-------------------------------
end process QSPI_CNTRL_PROCESS;
-------------------------------
pr_state_addr_ph <= '1' when qspi_cntrl_ps = ADDR_SEND else
'0';
QSPI_ADDR_CNTR_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(pr_state_addr_ph = '0') then
addr_cnt <= (others => '0');
elsif(pr_state_addr_ph = '1')then
--addr_cnt <= addr_cnt + SPIXfer_done_int_pulse_d2;
addr_cnt <= addr_cnt + SPIXfer_done_int_pulse;
end if;
end if;
end process QSPI_ADDR_CNTR_PROCESS;
-----------------------------------
end generate QSPI_QUAD_MODE_SP_MEM_GEN;
---------------------------------------
-------------------------------------------------------------------------------
-- RATIO_NOT_EQUAL_4_GENERATE : Logic to be used when C_SCK_RATIO is not equal
-- to 4
-------------------------------
RATIO_NOT_EQUAL_4_GENERATE: if(C_SCK_RATIO /= 4) generate
-----
begin
-----
SCK_O_NQ_4_NO_STARTUP_USED: if (C_USE_STARTUP = 0) generate
----------------
attribute IOB : string;
attribute IOB of SCK_O_NE_4_FDRE_INST : label is "true";
signal slave_mode : std_logic;
----------------
begin
-----
-------------------------------------------------------------------------------
-- SCK_O_SELECT_PROCESS : Select the idle state (CPOL bit) when not transfering
-- data else select the clock for slave device
-------------------------
SCK_O_NQ_4_SELECT_PROCESS: process(--Mst_N_Slv ,-- in master mode
sck_o_int ,-- value driven on sck_int
CPOL ,-- CPOL mode thr SPICR
transfer_start ,
transfer_start_d1 ,
Count(COUNT_WIDTH),
pr_state_non_idle -- State machine is in Non-idle state
)is
begin
if((transfer_start = '1') and
(transfer_start_d1 = '1') and
--(Count(COUNT_WIDTH) = '0')and
(pr_state_non_idle = '1')
) then
sck_o_in <= sck_o_int;
else
sck_o_in <= CPOL;
end if;
end process SCK_O_NQ_4_SELECT_PROCESS;
---------------------------------
slave_mode <= not (Mst_N_Slv); -- create the reset condition by inverting the mst_n_slv signal. 1 - master mode, 0 - slave mode.
-- FDRE: Single Data Rate D Flip-Flop with Synchronous Reset and
-- Clock Enable (posedge clk). during slave mode no clock should be generated from the core.
SCK_O_NE_4_FDRE_INST : component FDRE
generic map (
INIT => '0'
) -- Initial value of register (’0’ or ’1’)
port map
(
Q => SCK_O_reg, -- Data output
C => Bus2IP_Clk, -- Clock input
CE => '1', -- Clock enable input
R => slave_mode, -- Synchronous reset input
D => sck_o_in -- Data input
);
end generate SCK_O_NQ_4_NO_STARTUP_USED;
-------------------------------
SCK_O_NQ_4_STARTUP_USED: if (C_USE_STARTUP = 1) generate
-------------
begin
-----
-------------------------------------------------------------------------------
-- SCK_O_SELECT_PROCESS : Select the idle state (CPOL bit) when not transfering
-- data else select the clock for slave device
-------------------------
SCK_O_NQ_4_SELECT_PROCESS: process(sck_o_int ,
CPOL ,
transfer_start ,
transfer_start_d1 ,
Count(COUNT_WIDTH)
)is
begin
if((transfer_start = '1') and
(transfer_start_d1 = '1') --and
--(Count(COUNT_WIDTH) = '0')
) then
sck_o_in <= sck_o_int;
else
sck_o_in <= CPOL;
end if;
end process SCK_O_NQ_4_SELECT_PROCESS;
---------------------------------
---------------------------------------------------------------------------
-- SCK_O_FINAL_PROCESS : Register the final SCK_O_reg
------------------------
SCK_O_NQ_4_FINAL_PROCESS: process(Bus2IP_Clk)
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
--If Soft_Reset_op or slave Mode.Prevents SCK_O_reg to be generated in slave
if((Soft_Reset_op = RESET_ACTIVE)
) then
SCK_O_reg <= '0';
elsif((pr_state_non_idle='0') or -- dont allow sck to go out when
(Mst_N_Slv = '0'))then -- SM is in IDLE state or core in slave mode
SCK_O_reg <= '0';
else
SCK_O_reg <= sck_o_in;
end if;
end if;
end process SCK_O_NQ_4_FINAL_PROCESS;
-------------------------------------
end generate SCK_O_NQ_4_STARTUP_USED;
-------------------------------------
end generate RATIO_NOT_EQUAL_4_GENERATE;
-------------------------------------------------------------------------------
-- RATIO_OF_4_GENERATE : Logic to be used when C_SCK_RATIO is equal to 4
------------------------
RATIO_OF_4_GENERATE: if(C_SCK_RATIO = 4) generate
-----
begin
-----
-------------------------------------------------------------------------------
-- SCK_O_FINAL_PROCESS : Select the idle state (CPOL bit) when not transfering
-- data else select the clock for slave device
------------------------
-- A work around to reduce one clock cycle for sck_o generation. This would
-- allow for proper shifting of data bits into the slave device.
-- Removing the final stage F/F. Disadvantage of not registering final output
-------------------------------------------------------------------------------
SCK_O_EQ_4_NO_STARTUP_USED: if (C_USE_STARTUP = 0) generate
----------------
attribute IOB : string;
attribute IOB of SCK_O_EQ_4_FDRE_INST : label is "true";
signal slave_mode : std_logic;
----------------
begin
-----
SCK_O_EQ_4_FINAL_PROCESS: process(Mst_N_Slv ,-- in master mode
sck_o_int ,-- value driven on sck_int
CPOL ,-- CPOL mode thr SPICR
transfer_start ,
transfer_start_d1 ,
Count(COUNT_WIDTH),
pr_state_non_idle -- State machine is in Non-idle state
)is
-----
begin
-----
if(--(Mst_N_Slv = '1') and
(transfer_start = '1') and
(transfer_start_d1 = '1') and
(Count(COUNT_WIDTH) = '0')and
(pr_state_non_idle = '1')
) then
SCK_O_1 <= sck_o_int;
else
SCK_O_1 <= CPOL and Mst_N_Slv;
end if;
end process SCK_O_EQ_4_FINAL_PROCESS;
-------------------------------------
slave_mode <= not (Mst_N_Slv);-- dont allow SPI clock to go out when core is in slave mode.
-- FDRE: Single Data Rate D Flip-Flop with Synchronous Reset and
-- Clock Enable (posedge clk).
SCK_O_EQ_4_FDRE_INST : component FDRE
generic map (
INIT => '0'
) -- Initial value of register (’0’ or ’1’)
port map
(
Q => SCK_O_reg, -- Data output
C => Bus2IP_Clk, -- Clock input
CE => '1', -- Clock enable input
R => slave_mode, -- Synchronous reset input
D => SCK_O_1 -- Data input
);
end generate SCK_O_EQ_4_NO_STARTUP_USED;
-----------------------------
SCK_O_EQ_4_STARTUP_USED: if (C_USE_STARTUP = 1) generate
-------------
begin
-----
SCK_O_EQ_4_FINAL_PROCESS: process(Mst_N_Slv, -- in master mode
sck_o_int, -- value driven on sck_int
CPOL, -- CPOL mode thr SPICR
transfer_start,
transfer_start_d1,
Count(COUNT_WIDTH)
)is
-----
begin
-----
if(--(Mst_N_Slv = '1') and
(transfer_start = '1') and
(transfer_start_d1 = '1') --and
--(Count(COUNT_WIDTH) = '0')--and
--(pr_state_non_idle = '1')
)then
SCK_O_1 <= sck_o_int;
else
SCK_O_1 <= CPOL and Mst_N_Slv;
end if;
end process SCK_O_EQ_4_FINAL_PROCESS;
-------------------------------------
----------------------------------------------------------------------------
-- SCK_RATIO_4_REG_PROCESS : The SCK is registered in SCK RATIO = 4 mode
----------------------------------------------------------------------------
SCK_O_EQ_4_REG_PROCESS: process(Bus2IP_Clk)
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
-- If Soft_Reset_op or slave Mode. Prevents SCK_O_reg to be generated in slave
if((Soft_Reset_op = RESET_ACTIVE)
) then
SCK_O_reg <= '0';
elsif((pr_state_non_idle='0') or -- dont allow sck to go out when
(Mst_N_Slv = '0') -- SM is in IDLE state or core in slave mode
)then
SCK_O_reg <= '0';
else
SCK_O_reg <= SCK_O_1;
end if;
end if;
end process SCK_O_EQ_4_REG_PROCESS;
-----------------------------------
end generate SCK_O_EQ_4_STARTUP_USED;
-------------------------------------
end generate RATIO_OF_4_GENERATE;
---------------------
end architecture imp;
---------------------
| gpl-2.0 | 7dced226bb373eb40e6a9d24d2bb4572 | 0.338678 | 4.867743 | false | false | false | false |
freecores/ternary_adder | vhdl/ternary_adder_xilinx.vhd | 1 | 17,143 | ---------------------------------------------------------------------------------------------
-- Author: Jens Willkomm, Martin Kumm
-- Contact: [email protected], [email protected]
-- License: LGPL
-- Date: 15.03.2013
-- Compatibility: Xilinx FPGAs of Virtex 5-7, Spartan 6 and Series 7 architectures
--
-- Description:
-- Low level implementation of a ternary adder according to U.S. Patent No 7274211
-- from Xilinx, which uses the same no of slices than a two input adder.
-- The output coresponds to sum_o = x_i + y_i + z_i, where the inputs have a word size of
-- 'input_word_size' while the output has a word size of input_word_size+2.
--
-- Flipflops at the outputs can be activated by setting 'use_output_ff' to true.
-- Signed operation is activated by using the 'is_signed' generic.
-- The inputs y_i and z_i can be negated by setting 'subtract_y' or 'subtract_z'
-- to realize sum_o = x_i +/- y_i +/- z_i. The negation requires no extra resources.
---------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ternary_add_sub_prim is
generic(
input_word_size : integer := 10;
subtract_y : boolean := false;
subtract_z : boolean := false;
use_output_ff : boolean := true;
is_signed : boolean := true
);
port(
clk_i : in std_logic;
rst_i : in std_logic;
x_i : in std_logic_vector((input_word_size - 1) downto 0);
y_i : in std_logic_vector((input_word_size - 1) downto 0);
z_i : in std_logic_vector((input_word_size - 1) downto 0);
sum_o : out std_logic_vector((input_word_size + 1) downto 0)
);
end entity;
architecture behavior of ternary_add_sub_prim is
-- this function calculates the initial carry bit for the bbus
function bbus_init
return std_logic is
variable result : std_logic;
begin
result := '0';
if subtract_y or subtract_z then
result := '1';
end if;
return result;
end function;
-- this function calculates the initial carry bit for the carry chain
function cc_init
return std_logic is
variable result : std_logic;
begin
result := '0';
if subtract_y and subtract_z then
result := '1';
end if;
return result;
end function;
component slice_setup
generic(
input_word_size : integer := 4;
use_output_ff : boolean := false;
is_initial_slice : boolean := true;
subtract_y : boolean := false;
subtract_z : boolean := false
);
port(
-- signals for a synchronous circuit
clock : in std_logic;
clock_enable : in std_logic;
clear : in std_logic;
-- the three addends
x_in : in std_logic_vector((input_word_size - 1) downto 0);
y_in : in std_logic_vector((input_word_size - 1) downto 0);
z_in : in std_logic_vector((input_word_size - 1) downto 0);
-- the upper entity is mapping the bbus correctly
-- in initial slice bbus(0) ^= sub / ~add
bbus_in : in std_logic_vector((input_word_size - 1) downto 0);
bbus_out : out std_logic_vector((input_word_size - 1) downto 0);
-- both carrys are for and from the carry chain
-- in the initial slice use carry_in <= '0' always
-- sub/add is done by the bbus(0) from the initial slice
carry_in : in std_logic;
carry_out : out std_logic;
-- the sum of the three addends (x_in + y_in + z_in)
sum_out : out std_logic_vector((input_word_size - 1) downto 0)
);
end component;
-- calculate the needed number of slices
constant num_slices : integer := ((input_word_size + 1) / 4) + 1;
-- defines the initial carry values
-- in the pure addition mode both constants are '0'
-- if one of the input signal is subtracted the carry_bbus is '1'
-- if two input signal are subtracted both constants are '1'
constant carry_bbus : std_logic := bbus_init;
constant carry_cc : std_logic := cc_init;
-- the input addends with sign extention
signal x : std_logic_vector((input_word_size + 1) downto 0);
signal y : std_logic_vector((input_word_size + 1) downto 0);
signal z : std_logic_vector((input_word_size + 1) downto 0);
-- the bbus that is routed around the slice
-- this bbus differs from the one in the xilinx paper,
-- per position the input is bbus(n) and the output is bbus(n + 1)
-- this is because of the sub/~add, which is bbus(0) and all the other
-- bbus signals are scrolled one position up
signal bbus : std_logic_vector(input_word_size + 2 downto 0);
-- the carry from every slice to the next one
-- the last slice gives the carry output for the adder
-- carry(n) is the carry of the carry chain of slice n
signal carry : std_logic_vector((num_slices - 1) downto 0);
begin
-- checking the parameter input_word_size
assert (input_word_size > 0) report "an adder with a bit width of "
& integer'image(input_word_size) & " is not possible." severity failure;
-- adding two bit sign extention to the input addends
extention_signed: if is_signed = true generate
x <= x_i(input_word_size - 1) & x_i(input_word_size - 1) & x_i;
y <= y_i(input_word_size - 1) & y_i(input_word_size - 1) & y_i;
z <= z_i(input_word_size - 1) & z_i(input_word_size - 1) & z_i;
end generate;
extention_unsigned: if is_signed = false generate
x <= '0' & '0' & x_i;
y <= '0' & '0' & y_i;
z <= '0' & '0' & z_i;
end generate;
-- the initial bbus carry signal
bbus(0) <= carry_bbus;
-- generating the slice setups
-- getting all signals into one slice
single_slice: if num_slices = 1 generate
slice_i: slice_setup
generic map(
input_word_size => input_word_size + 2,
use_output_ff => use_output_ff,
is_initial_slice => true,
subtract_y => subtract_y,
subtract_z => subtract_z
)
port map(
clock => clk_i,
clock_enable => '1',
clear => rst_i,
x_in => x,
y_in => y,
z_in => z,
bbus_in => bbus(input_word_size + 1 downto 0),
-- scrolling bbus_out one position up
bbus_out => bbus(input_word_size + 2 downto 1),
carry_in => carry_cc,
carry_out => carry(0),
sum_out => sum_o(input_word_size + 1 downto 0)
);
end generate;
-- make more slices to calculate all signals
multiple_slices: if num_slices > 1 generate
slices: for i in 0 to (num_slices - 1) generate
-- generate the first slice
first_slice: if i = 0 generate
slice_i: slice_setup
generic map(
input_word_size => 4,
use_output_ff => use_output_ff,
is_initial_slice => true,
subtract_y => subtract_y,
subtract_z => subtract_z
)
port map(
clock => clk_i,
clock_enable => '1',
clear => rst_i,
x_in => x(3 downto 0),
y_in => y(3 downto 0),
z_in => z(3 downto 0),
bbus_in => bbus(3 downto 0),
-- scrolling bbus_out one position upwards
bbus_out => bbus(4 downto 1),
carry_in => carry_cc,
carry_out => carry(0),
sum_out => sum_o(3 downto 0)
);
end generate;
-- generate all full slices
full_slice: if i > 0 and i < (num_slices - 1) generate
slice_i: slice_setup
generic map(
input_word_size => 4,
use_output_ff => use_output_ff,
is_initial_slice => false,
subtract_y => subtract_y,
subtract_z => subtract_z
)
port map(
clock => clk_i,
clock_enable => '1',
clear => rst_i,
x_in => x((4 * i) + 3 downto 4 * i),
y_in => y((4 * i) + 3 downto 4 * i),
z_in => z((4 * i) + 3 downto 4 * i),
bbus_in => bbus((4 * i) + 3 downto 4 * i),
-- scrolling bbus_out one position upwards
bbus_out => bbus((4 * i) + 4 downto (4 * i) + 1),
carry_in => carry(i - 1),
carry_out => carry(i),
sum_out => sum_o((4 * i) + 3 downto 4 * i)
);
end generate;
-- generate the last slice
last_slice: if i = (num_slices - 1) generate
slice_i: slice_setup
generic map(
input_word_size => (input_word_size + 2) - (i * 4),
use_output_ff => use_output_ff,
is_initial_slice => false,
subtract_y => subtract_y,
subtract_z => subtract_z
)
port map(
clock => clk_i,
clock_enable => '1',
clear => rst_i,
x_in => x(input_word_size + 1 downto 4 * i),
y_in => y(input_word_size + 1 downto 4 * i),
z_in => z(input_word_size + 1 downto 4 * i),
bbus_in => bbus(input_word_size + 1 downto 4 * i),
-- scrolling bbus_out one position up
bbus_out => bbus(input_word_size + 2 downto (4 * i) + 1),
carry_in => carry(i - 1),
carry_out => carry(i),
sum_out => sum_o(input_word_size + 1 downto 4 * i)
);
end generate;
end generate;
end generate;
end architecture;
--- Definition of the slice_setup component which configures a single slice ---
library unisim;
use unisim.vcomponents.all; -- loading xilinx primitives
library ieee;
use ieee.std_logic_1164.all; -- loading std_logic & std_logic_vector
entity slice_setup is
generic(
input_word_size : integer := 4;
use_output_ff : boolean := false;
is_initial_slice : boolean := true;
subtract_y : boolean := false;
subtract_z : boolean := false
);
port(
-- signals for a synchronous circuit
clock : in std_logic;
clock_enable : in std_logic;
clear : in std_logic;
-- the three addends
x_in : in std_logic_vector((input_word_size - 1) downto 0);
y_in : in std_logic_vector((input_word_size - 1) downto 0);
z_in : in std_logic_vector((input_word_size - 1) downto 0);
-- the upper entity is mapping the bbus correctly
-- in initial slice bbus(0) ^= sub / ~add
bbus_in : in std_logic_vector((input_word_size - 1) downto 0);
bbus_out : out std_logic_vector((input_word_size - 1) downto 0);
-- both carrys are for and from the carry chain
-- in the initial slice use carry_in <= '0' always
-- sub/add is done by the bbus(0) from the initial slice
carry_in : in std_logic;
carry_out : out std_logic;
-- the sum of the three addends (x_in + y_in + z_in)
sum_out : out std_logic_vector((input_word_size - 1) downto 0)
);
end entity;
architecture behavior of slice_setup is
-- this function returns the lut initialization
function get_lut_init
return bit_vector is
-- defines several lut configurations
-- for init calculation see "initializing_primitives.ods"
constant lut_init_no_sub : bit_vector(63 downto 0) := x"3cc3c33cfcc0fcc0";
constant lut_init_sub_y : bit_vector(63 downto 0) := x"c33c3cc3cf0ccf0c";
constant lut_init_sub_z : bit_vector(63 downto 0) := x"c33c3cc3f330f330";
constant lut_init_sub_yz : bit_vector(63 downto 0) := x"3cc3c33c3f033f03";
variable curr_lut : bit_vector(63 downto 0) := lut_init_no_sub;
begin
curr_lut := lut_init_no_sub;
if subtract_y then
curr_lut := lut_init_sub_y;
end if;
if subtract_z then
curr_lut := lut_init_sub_z;
end if;
if subtract_y and subtract_z then
curr_lut := lut_init_sub_yz;
end if;
return curr_lut;
end function;
-- calculate how many bits to fill up with zeros for the carry chain
constant fillup_width : integer := 4 - input_word_size;
-- holds the lut configuration used in this slice
constant current_lut_init : bit_vector := get_lut_init;
-- output o6 of the luts
signal lut_o6 : std_logic_vector((input_word_size - 1) downto 0);
-- the signals for and from the carry chain have to be wrapped into signals
-- with a width of four, to fill them up with zeros and prevent synthesis
-- warnings when doing this in the port map of the carry chain
-- input di of the carry chain (have to be four bits width)
signal cc_di : std_logic_vector(3 downto 0);
-- input s of the carry chain (have to be four bits width)
signal cc_s : std_logic_vector(3 downto 0);
-- output o of the carry chain (have to be four bits width)
signal cc_o : std_logic_vector(3 downto 0);
-- output co of the carry chain (have to be four bits width)
signal cc_co : std_logic_vector(3 downto 0);
begin
-- check the generic parameter
assert (input_word_size > 0 and input_word_size < 5) report "a slice with a bit width of "
& integer'image(input_word_size) & " is not possible." severity failure;
-- prepairing singals for the carry chain
full_slice_assignment: if input_word_size = 4 generate
cc_di <= bbus_in;
cc_s <= lut_o6;
end generate;
last_slice_assignment: if input_word_size < 4 generate
cc_di <= (fillup_width downto 1 => '0') & bbus_in;
cc_s <= (fillup_width downto 1 => '0') & lut_o6;
end generate;
-- creating the lookup tables
luts: for i in 0 to (input_word_size - 1) generate
-- lut6_2 primitive is described in virtex 6 user guide on page 215:
-- http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_3/virtex6_hdl.pdf
lut_bit_i: lut6_2
generic map(
init => current_lut_init
)
-------------------------------------------------------------------
-- table of names and connections
-- user guide us 7,274,211 usage in adder
-- ---------- ------------ --------------
-- i0 in1 gnd
-- i1 in2 z(n)
-- i2 in3 y(n)
-- i3 in4 x(n)
-- i4 in5 bbus(n-1)
-- i5 in6 vdd
-- o5 o5
-- o6 o6
-------------------------------------------------------------------
port map(
i0 => '0',
i1 => z_in(i),
i2 => y_in(i),
i3 => x_in(i),
i4 => bbus_in(i),
i5 => '1',
o5 => bbus_out(i),
o6 => lut_o6(i)
);
end generate;
-- creating the carry chain
-- carry4 primitive is described in virtex 6 user guide on page 108:
-- http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_3/virtex6_hdl.pdf
initial_slice: if is_initial_slice = true generate
init_cc: carry4
-------------------------------------------------------------------
-- table of names and connections
-- user guide usage in adder
-- ---------- --------------
-- co msb is carry out, rest is not connected
-- o sum
-- ci in the initial slice: not connected
-- cyinit in the initial slice: add / ~sub
-- di bbus(n-1)
-- s lut_o6(n)
-------------------------------------------------------------------
port map(
co => cc_co,
o => cc_o,
cyinit => '0',
ci => carry_in,
di => cc_di,
s => cc_s
);
end generate;
further_slice: if is_initial_slice = false generate
further_cc: carry4
-------------------------------------------------------------------
-- table of names and connections
-- user guide usage in adder
-- ---------- --------------
-- co msb is carry out, rest is not connected
-- o sum
-- ci carry from previous slice
-- cyinit in further slices: not connected
-- di bbus(n-1)
-- s lut_o6(n)
-------------------------------------------------------------------
port map(
co => cc_co,
o => cc_o,
cyinit => '0',
ci => carry_in,
di => cc_di,
s => cc_s
);
end generate;
-- connect the last used output of the carry chain to the slice output
carry_out <= cc_co(input_word_size - 1);
-- creating the flip flops
sum_register: if use_output_ff = true generate
ffs: for i in 0 to (input_word_size - 1) generate
ff_i: fdce
generic map(
-- initialize all flip flops with '0'
init => '0'
)
-------------------------------------------------------------------
-- table of names and connections
-- user guide usage in adder
-- ---------- --------------
-- clr clear
-- ce clock_enable, always '1'
-- d cc_o
-- c clock
-- q sum(n)
-------------------------------------------------------------------
port map(
clr => clear,
ce => clock_enable,
d => cc_o(i),
c => clock,
q => sum_out(i)
);
end generate;
end generate;
-- bypassing the flip flops in case of a asynchronous circuit
bypass: if use_output_ff = false generate
sum_out <= cc_o(input_word_size - 1 downto 0);
end generate;
end architecture;
| lgpl-3.0 | 30640040b67b3f4e0e3b1069abfe8156 | 0.549145 | 3.298634 | false | false | false | false |
dpolad/dlx | DLX_vhd/useless/bhe_comparator.vhd | 1 | 1,633 | -- *** bhe_comparator.vhd *** --
-- structural comparator as described in prof. Graziano documents
-- extended in order to handle both signed and unsigned comparisons
-- sum is computed outside of the comparator
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity bhe_comparator is
generic (M : integer := 32);
port (
A : in std_logic_vector(M-1 downto 0); -- carry out
B : in std_logic_vector(M-1 downto 0);
sign : in std_logic;
sel : in std_logic_vector(2 downto 0); -- selection
S : out std_logic
);
end bhe_comparator;
architecture bhe_2 of bhe_comparator is
signal NC : std_logic;
signal Z : std_logic;
signal N : std_logic;
signal G : std_logic;
signal GE : std_logic;
signal L : std_logic;
signal LE : std_logic;
signal E : std_logic;
signal NE : std_logic;
begin
G <= '1' when signed(A) > signed(B) and sign = '1' else
'1' when unsigned(A) > unsigned(B) and sign = '0' else
'0';
GE <= '1' when signed(A) >= signed(B) and sign = '1' else
'1' when unsigned(A) >= unsigned(B) and sign = '0' else
'0';
L <= '1' when signed(A) < signed(B) and sign = '1' else
'1' when unsigned(A) < unsigned(B) and sign = '0' else
'0';
LE <= '1' when signed(A) <= signed(B) and sign = '1' else
'1' when unsigned(A) <= unsigned(B) and sign = '0' else
'0';
E <= '1' when signed(A) = signed(B) else
'0';
NE <= '1' when signed(A) /= signed(B) else
'0';
S <= G when sel="000" else
GE when sel="001" else
L when sel="010" else
LE when sel="011" else
E when sel="100" else
NE when sel="101" else
'X';
end bhe_2;
| bsd-2-clause | 0176165ff3f523fec007af2590299435 | 0.610533 | 2.600318 | false | false | false | false |
dpolad/dlx | DLX_vhd/a.i.a.a-MULTLOGIC.vhd | 1 | 6,173 | library ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
ENTITY simple_booth_add_ext IS
generic (N : integer := 8);
PORT(
Clock : in std_logic;
Reset : in std_logic;
sign : in std_logic;
enable : in std_logic;
valid : out std_logic;
A : in std_logic_vector (N-1 downto 0);
B : in std_logic_vector (N-1 downto 0);
A_to_add : out std_logic_vector (2*N-1 downto 0);
B_to_add : out std_logic_vector (2*N-1 downto 0);
sign_to_add : out std_logic;
final_out : out std_logic_vector (2*N-1 downto 0);
ACC_from_add : in std_logic_vector (2*N-1 downto 0)
);
END simple_booth_add_ext;
architecture struct of simple_booth_add_ext is
component booth_encoder
port(
B_in : in std_logic_vector (2 downto 0);
A_out : out std_logic_vector (2 downto 0)
);
end component;
component shift
generic(
N : natural
);
port(
Clock : in std_logic;
ALOAD : in std_logic;
D : in std_logic_vector(N-1 downto 0);
SO : out std_logic );
end component;
component piso_r_2
generic(
N : natural
);
port(
Clock : in std_logic;
ALOAD : in std_logic;
D : in std_logic_vector(N-1 downto 0);
SO : out std_logic_vector(N-1 downto 0) );
end component;
component mux8to1_gen
generic ( M : integer );
port(
A : in std_logic_vector (M-1 downto 0);
B : in std_logic_vector (M-1 downto 0);
C : in std_logic_vector (M-1 downto 0);
D : in std_logic_vector (M-1 downto 0);
E : in std_logic_vector (M-1 downto 0);
F : in std_logic_vector (M-1 downto 0);
G : in std_logic_vector (M-1 downto 0);
H : in std_logic_vector (M-1 downto 0);
S : in std_logic_vector (2 downto 0);
Y : out std_logic_vector (M-1 downto 0)
);
end component;
component ff32_en
generic(
SIZE : integer
);
port(
D : in std_logic_vector(SIZE - 1 downto 0);
Q : out std_logic_vector(SIZE - 1 downto 0);
en : in std_logic;
clk : in std_logic;
rst : in std_logic
);
end component;
component mux21
port (
IN0 : in std_logic_vector(31 downto 0);
IN1 : in std_logic_vector(31 downto 0);
CTRL : in std_logic;
OUT1 : out std_logic_vector(31 downto 0)
);
end component;
type mux_select is array (N/2 downto 0) of std_logic_vector(2 downto 0);
signal tot_select : mux_select;
signal piso_0_in : std_logic_vector(N/2 downto 0);
signal piso_1_in : std_logic_vector(N/2 downto 0);
signal piso_2_in : std_logic_vector(N/2 downto 0);
signal piso_0_out : std_logic;
signal piso_1_out : std_logic;
signal piso_2_out : std_logic;
signal enc_0_in : std_logic_vector(2 downto 0);
signal enc_N2_in : std_logic_vector(2 downto 0);
signal last_bit : std_logic;
signal extend_vector : std_logic_vector(N-1 downto 0);
signal extended_A : std_logic_vector(2*N-1 downto 0);
signal zeros : std_logic_vector(2*N-1 downto 0);
signal reg_enable : std_logic;
signal A_to_mux : std_logic_vector(2*N-1 downto 0);
signal A2_to_mux : std_logic_vector(2*N-1 downto 0);
signal mux_out_to_add : std_logic_vector(2*N-1 downto 0);
signal load : std_logic;
signal input_mux_sel : std_logic_vector(2 downto 0);
signal count : unsigned(4 downto 0);
signal accumulate : std_logic_vector(2*N-1 downto 0);
signal next_accumulate : std_logic_vector(2*N-1 downto 0);
signal triggered : std_logic;
begin
-- TODO: check if this is correct!
last_bit <= sign and B(N-1);
enc_0_in <= B(1 downto 0)&'0';
enc_N2_in <= last_bit&last_bit&B(N-1);
piso_gen: for i in 0 to N/2 generate
piso_0_in(i) <= tot_select(i)(0);
piso_1_in(i) <= tot_select(i)(1);
piso_2_in(i) <= tot_select(i)(2);
end generate piso_gen;
encod_loop: for i in 0 to N/2 generate
en_level0 : IF i = 0 generate
encod_0 : booth_encoder port map(enc_0_in, tot_select(i));
end generate en_level0;
en_levelN : IF i = N/2 generate
encod_i : booth_encoder port map(enc_N2_in, tot_select(i));
end generate en_levelN;
en_leveli : IF i > 0 and i < N/2 generate
encod_i : booth_encoder port map(B(2*i+1 downto 2*i-1), tot_select(i));
end generate en_leveli;
end generate encod_loop;
piso_0 : shift generic map( N => N/2+1) port map(Clock,load,piso_0_in,piso_0_out);
piso_1 : shift generic map( N => N/2+1) port map(Clock,load,piso_1_in,piso_1_out);
piso_2 : shift generic map( N => N/2+1) port map(Clock,load,piso_2_in,piso_2_out);
extend_vector <= (others => A(N-1) and sign);
extended_A <= extend_vector&A;
zeros <= (others => '0');
A_reg : piso_r_2 generic map( N => 2*N) port map(Clock,load,extended_A,A_to_mux);
A2_to_mux <= A_to_mux (2*N-2 downto 0)&'0';
input_mux_sel(0) <= piso_0_out;
input_mux_sel(1) <= piso_1_out;
input_mux_sel(2) <= piso_2_out;
INPUTMUX: mux21 port map(
IN0 => A_to_mux,
IN1 => A2_to_mux,
CTRL => input_mux_sel(0),
OUT1 => B_to_add);
ACCUMULATOR: ff32_en generic map(
SIZE => N*2
)port map(
D => next_accumulate,
Q => accumulate,
en => reg_enable,
clk => Clock,
rst => Reset);
reg_enable <= input_mux_sel(2) or nor_reduce(std_logic_vector(count) xor "01001");
A_to_add <= accumulate;
sign_to_add <= input_mux_sel(1);
final_out <= accumulate when input_mux_sel(2) = '0' else
ACC_from_add;
process(Reset,Clock)
begin
if Reset = '1' then
count <= "01001";
else
if Clock = '1' and Clock'event then
if count /= 0 and enable = '1' then
count <= count - 1;
end if;
if count = 0 then
count <= "01001";
end if;
end if;
end if;
end process;
--load <= '1' when count = 9 else
-- '0';
--
--next_accumulate <= (others => '0') when count = 9 else
-- ACC_from_add;
--
--valid <= '1' when count = 0 else
-- '0';
process(count,ACC_from_add)
begin
if count = 0 then
valid <= '1';
next_accumulate <= ACC_from_add;
load <= '0';
elsif count = 9 then
valid <= '0';
next_accumulate <= (others => '0');
load <= '1';
else
valid <= '0';
next_accumulate <= ACC_from_add;
load <= '0';
end if;
end process;
end struct;
| bsd-2-clause | 61d40ee6d1607c1a73cf5e5f66d0015a | 0.608618 | 2.485105 | false | false | false | false |
dpolad/dlx | DLX_vhd/a.b-FETCHBLOCK.vhd | 2 | 2,463 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--use work.myTypes.all;
entity fetch_block is
generic (
SIZE : integer := 32
);
port (
branch_target_i : in std_logic_vector(SIZE - 1 downto 0);
sum_addr_i : in std_logic_vector(SIZE - 1 downto 0);
A_i : in std_logic_vector(SIZE - 1 downto 0);
NPC4_i : in std_logic_vector(SIZE - 1 downto 0);
S_MUX_PC_BUS_i : in std_logic_vector(1 downto 0);
PC_o : out std_logic_vector(SIZE - 1 downto 0);
PC4_o : out std_logic_vector(SIZE - 1 downto 0);
PC_BUS_pre_BTB : out std_logic_vector(SIZE - 1 downto 0);
stall_i : in std_logic;
take_prediction_i : in std_logic;
mispredict_i : in std_logic;
predicted_PC : in std_logic_vector(SIZE - 1 downto 0);
clk : in std_logic;
rst : in std_logic
);
end fetch_block;
architecture Struct of fetch_block is
component add4
port(
IN1 : in unsigned(SIZE - 1 downto 0);
OUT1 : out unsigned(SIZE - 1 downto 0)
);
end component;
component ff32_en
port(
D : in std_logic_vector(SIZE - 1 downto 0);
Q : out std_logic_vector(SIZE - 1 downto 0);
en : in std_logic;
clk : in std_logic;
rst : in std_logic
);
end component;
component mux41
port (
IN0 : in std_logic_vector(SIZE - 1 downto 0);
IN1 : in std_logic_vector(SIZE - 1 downto 0);
IN2 : in std_logic_vector(SIZE - 1 downto 0);
IN3 : in std_logic_vector(SIZE - 1 downto 0);
CTRL : in std_logic_vector(1 downto 0);
OUT1 : out std_logic_vector(SIZE - 1 downto 0)
);
end component;
signal PC_help : std_logic_vector(SIZE - 1 downto 0);
signal PC_BUS : std_logic_vector(SIZE - 1 downto 0);
signal TARGET_PC : std_logic_vector(SIZE - 1 downto 0);
signal help_ctrl : std_logic_vector(1 downto 0);
signal PC4_o_uns : unsigned(SIZE - 1 downto 0);
signal en_IR : std_logic;
begin
en_IR <= not stall_i;
PC: ff32_en port map(
D => PC_BUS,
Q => PC_help,
en => en_IR,
clk => clk,
rst => rst);
PCADD: add4 port map(
IN1 => unsigned(PC_help),
OUT1 => PC4_o_uns);
MUXTARGET: mux41 port map(
IN0 => NPC4_i,
IN1 => A_i,
IN2 => sum_addr_i,
IN3 => branch_target_i,
CTRL => S_MUX_PC_BUS_i,
OUT1 => TARGET_PC);
MUXPREDICTION: mux41 port map(
IN0 => std_logic_vector(PC4_o_uns),
IN1 => predicted_PC,
IN2 => TARGET_PC,
IN3 => TARGET_PC,
CTRL => help_ctrl,
OUT1 => PC_BUS);
help_ctrl <= mispredict_i&take_prediction_i;
PC4_o <= std_logic_vector(PC4_o_uns);
PC_o <= PC_help;
PC_BUS_pre_BTB <= TARGET_PC;
end struct;
| bsd-2-clause | b8d65326b9cd295a9294b7ef32abe1d4 | 0.64393 | 2.370549 | false | false | false | false |
arthurbenemann/arduhoop | dev/papilioDUO/sd_passthrought_windDH_to_arduino.vhd | 1 | 354 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity clean is Port (
ARDUINO_RESET : out STD_LOGIC;
A12, SD_CS, SD_MOSI, SD_SCK : out STD_LOGIC;
A10, A11, A13, SD_MISO : in STD_LOGIC);
end clean;
architecture Behavioral of clean is
begin
ARDUINO_RESET <='1';
SD_CS <= A10;
SD_MOSI <= A11;
SD_SCK <= A13;
A12 <= SD_MISO;
end Behavioral;
| gpl-3.0 | 2574c27b862f15ec2a83e6a5ba78f9ba | 0.649718 | 2.546763 | false | false | false | false |
Hyperion302/omega-cpu | Hardware/Omega/ipcore_dir/UARTClockManager/simulation/timing/UARTClockManager_tb.vhd | 1 | 6,635 | -- file: UARTClockManager_tb.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard demonstration testbench
------------------------------------------------------------------------------
-- This demonstration testbench instantiates the example design for the
-- clocking wizard. Input clocks are toggled, which cause the clocking
-- network to lock and the counters to increment.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
library work;
use work.all;
entity UARTClockManager_tb is
end UARTClockManager_tb;
architecture test of UARTClockManager_tb is
-- Clock to Q delay of 100 ps
constant TCQ : time := 100 ps;
-- timescale is 1ps
constant ONE_NS : time := 1 ns;
-- how many cycles to run
constant COUNT_PHASE : integer := 1024 + 1;
-- we'll be using the period in many locations
constant PER1 : time := 31.250 ns;
-- Declare the input clock signals
signal CLK_IN1 : std_logic := '1';
-- The high bits of the sampling counters
signal COUNT : std_logic_vector(2 downto 1);
-- Status and control signals
signal RESET : std_logic := '0';
signal COUNTER_RESET : std_logic := '0';
signal timeout_counter : std_logic_vector (13 downto 0) := (others => '0');
-- signal defined to stop mti simulation without severity failure in the report
signal end_of_sim : std_logic := '0';
signal CLK_OUT : std_logic_vector(2 downto 1);
--Freq Check using the M & D values setting and actual Frequency generated
component UARTClockManager_exdes
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
CLK_OUT : out std_logic_vector(2 downto 1) ;
-- High bits of counters driven by clocks
COUNT : out std_logic_vector(2 downto 1);
-- Status and control signals
RESET : in std_logic
);
end component;
begin
-- Input clock generation
--------------------------------------
process begin
CLK_IN1 <= not CLK_IN1; wait for (PER1/2);
end process;
-- Test sequence
process
procedure simtimeprint is
variable outline : line;
begin
write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
write(outline, NOW/PER1);
write(outline, string'(" ns"));
writeline(output,outline);
end simtimeprint;
procedure simfreqprint (period : time; clk_num : integer) is
variable outputline : LINE;
variable str1 : string(1 to 16);
variable str2 : integer;
variable str3 : string(1 to 2);
variable str4 : integer;
variable str5 : string(1 to 4);
begin
str1 := "Freq of CLK_OUT(";
str2 := clk_num;
str3 := ") ";
str4 := 1000000 ps/period ;
str5 := " MHz" ;
write(outputline, str1 );
write(outputline, str2);
write(outputline, str3);
write(outputline, str4);
write(outputline, str5);
writeline(output, outputline);
end simfreqprint;
begin
report "Timing checks are not valid" severity note;
RESET <= '1';
wait for (PER1*6);
RESET <= '0';
-- can't probe into hierarchy, wait "some time" for lock
wait for (PER1*2500);
wait for (PER1*20);
COUNTER_RESET <= '1';
wait for (PER1*19.5);
COUNTER_RESET <= '0';
wait for (PER1*1);
report "Timing checks are valid" severity note;
wait for (PER1*COUNT_PHASE);
simtimeprint;
end_of_sim <= '1';
wait for 1 ps;
report "Simulation Stopped." severity failure;
wait;
end process;
-- Instantiation of the example design containing the clock
-- network and sampling counters
-----------------------------------------------------------
dut : UARTClockManager_exdes
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
-- Reset for logic in example design
COUNTER_RESET => COUNTER_RESET,
CLK_OUT => CLK_OUT,
-- High bits of the counters
COUNT => COUNT,
-- Status and control signals
RESET => RESET);
-- Freq Check
end test;
| lgpl-3.0 | 50bd186dd17a565984e432ee3d34a84e | 0.640844 | 4.264139 | false | false | false | false |
INTI-CMNB/Lattuino_IP_Core | bootloader/pm_s_rw.in.vhdl | 1 | 5,012 | ------------------------------------------------------------------------------
---- ----
---- Single Port RAM that maps to a Xilinx/Lattice BRAM ----
---- ----
---- This file is part FPGA Libre project http://fpgalibre.sf.net/ ----
---- ----
---- Description: ----
---- This is a program memory for the AVR. It maps to a Xilinx/Lattice ----
---- BRAM. ----
---- This version can be modified by the CPU (i. e. SPM instruction) ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008-2017 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008-2017 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: SinglePortPM(Xilinx) (Entity and architecture) ----
---- File name: pm_s_rw.in.vhdl (template used) ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: work ----
---- Dependencies: IEEE.std_logic_1164 ----
---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ----
---- iCE40 (iCE40HX4K) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
---- iCEcube2.2016.02 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity @entity.txt@ is
generic(
WORD_SIZE : integer:=16; -- Word Size
FALL_EDGE : std_logic:='0'; -- Ram clock falling edge
ADDR_W : integer:=13); -- Address Width
port(
clk_i : in std_logic;
addr_i : in std_logic_vector(ADDR_W-1 downto 0);
data_o : out std_logic_vector(WORD_SIZE-1 downto 0);
we_i : in std_logic;
data_i : in std_logic_vector(WORD_SIZE-1 downto 0));
end entity @entity.txt@;
architecture Xilinx of @entity.txt@ is
constant ROM_SIZE : natural:=2**ADDR_W;
type rom_t is array(natural range 0 to ROM_SIZE-1) of std_logic_vector(WORD_SIZE-1 downto 0);
signal addr_r : std_logic_vector(ADDR_W-1 downto 0);
signal rom : rom_t :=
(
@rom.dat@
);
begin
use_rising_edge:
if FALL_EDGE='0' generate
do_rom:
process (clk_i)
begin
if rising_edge(clk_i)then
addr_r <= addr_i;
if we_i='1' then
rom(to_integer(unsigned(addr_i))) <= data_i;
end if;
end if;
end process do_rom;
end generate use_rising_edge;
use_falling_edge:
if FALL_EDGE='1' generate
do_rom:
process (clk_i)
begin
if falling_edge(clk_i)then
addr_r <= addr_i;
if we_i='1' then
rom(to_integer(unsigned(addr_i))) <= data_i;
end if;
end if;
end process do_rom;
end generate use_falling_edge;
data_o <= rom(to_integer(unsigned(addr_r)));
end architecture Xilinx; -- Entity: @entity.txt@
| gpl-2.0 | 8be348f59d9e56e3f0a37f3b56314756 | 0.328013 | 5.145791 | false | false | false | false |
Hyperion302/omega-cpu | TestBenches/ALU_TB.vhdl | 1 | 3,512 | -- This file is part of the Omega CPU Core
-- Copyright 2015 - 2016 Joseph Shetaye
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as
-- published by the Free Software Foundation, either version 3 of the
-- License, or (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library IEEE;
use IEEE.std_logic_1164.all;
use work.Constants.all;
use IEEE.Numeric_std.all;
use std.textio.all;
entity ALU_TB is
end ALU_TB;
architecture Behavioral of ALU_TB is
component ALU
port (
RegisterB : in Word;
RegisterC : in Word;
Instruction : in Word;
RegisterA : out Word;
RegisterD : out Word;
Carry : out std_logic;
OutputReady : out std_logic);
end component;
signal RegisterB : Word;
signal RegisterC : Word;
signal Instruction : Word;
signal RegisterA : Word;
signal RegisterD : Word;
signal Carry : std_logic;
signal OutputReady : std_logic;
begin -- Behavioral
UUT : entity work.ALU port map (
RegisterB => RegisterB,
RegisterC => RegisterC,
Instruction => Instruction,
RegisterA => RegisterA,
RegisterD => RegisterD,
Carry => Carry,
OutputReady => OutputReady);
file_io:
process is
variable in_line : line;
variable out_line : line;
variable in_vector : bit_vector(31 downto 0) := (others => '0');
variable outputI : integer := 0;
variable Counter : integer := 0;
variable ExpectedCarry : std_logic := '0';
variable ExpectedRegisterA : Word := (others => '0');
variable ExpectedRegisterD : Word := (others => '0');
begin -- process
while not endfile(input) loop
readline(input, in_line);
if in_line'length = 32 then
read(in_line, in_vector);
case Counter is
when 0 =>
RegisterB <= to_stdlogicvector(in_vector);
Counter := Counter + 1;
when 1 =>
RegisterC <= to_stdlogicvector(in_vector);
Counter := Counter + 1;
when 2 =>
Instruction <= to_stdlogicvector(in_vector);
Counter := Counter + 1;
when 3 =>
ExpectedRegisterD := to_stdlogicvector(in_vector);
Counter := Counter + 1;
when 4 =>
ExpectedRegisterA := to_stdlogicvector(in_vector);
Counter := Counter + 1;
when 5 =>
ExpectedCarry := to_stdlogicvector(in_vector)(0);
wait for 1 ns;
write(out_line, to_bitvector(RegisterD));
writeline(output, out_line);
write(out_line, to_bitvector(RegisterA));
writeline(output, out_line);
write(out_line, to_bit(Carry));
writeline(output, out_line);
if (RegisterD = ExpectedRegisterD) and (RegisterA = ExpectedRegisterA) and (Carry = ExpectedCarry) then
write(out_line, string'("Passed"));
else
write(out_line, string'("Failed"));
end if;
writeline(output, out_line);
Counter := 0;
when others => null;
end case;
else
writeline(output,in_line);
end if;
end loop;
wait;
end process;
end Behavioral;
| lgpl-3.0 | 67e07246304c811db0fe6624f3ffec26 | 0.635251 | 3.910913 | false | false | false | false |
MAV-RT-testbed/MAV-testbed | Syma_Flight_Final/Syma_Flight_Final.srcs/sources_1/ipshared/rcs.ei.tum.de/Syma_Ctrl_core_v1_2/5d78a94c/src/ppm_decoder.vhd | 2 | 4,769 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 06/09/2015 10:34:39 AM
-- Design Name:
-- Module Name: ppm_decoder - ppm_decoder_behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ppm_decoder is
Port (
clk : in std_logic;
ppm_in : in STD_LOGIC;
ppm_out_1 : out STD_LOGIC_VECTOR (31 downto 0) := x"00_00_00_00";
ppm_out_2 : out STD_LOGIC_VECTOR (31 downto 0) := x"00_00_00_00";
ppm_out_3 : out STD_LOGIC_VECTOR (31 downto 0) := x"00_00_00_00";
ppm_out_4 : out STD_LOGIC_VECTOR (31 downto 0) := x"00_00_00_00";
ppm_out_5 : out STD_LOGIC_VECTOR (31 downto 0) := x"00_00_00_00";
ppm_out_6 : out STD_LOGIC_VECTOR (31 downto 0) := x"00_00_00_00";
ppm_out_7 : out STD_LOGIC_VECTOR (31 downto 0) := x"00_00_00_00";
ppm_out_8 : out STD_LOGIC_VECTOR (31 downto 0) := x"00_00_00_00";
intr_1 : out std_logic := '0';
intr_comp : out std_logic := '0');
-- ppm_sample : inout std_logic_vector (1 downto 0) := "00";
-- counter : inout unsigned (31 downto 0) := x"00_00_00_00";
-- reg_nr : inout unsigned (3 downto 0) := "0000");
end ppm_decoder;
architecture ppm_decoder_behavioral of ppm_decoder is
signal ppm_sample : std_ulogic_vector (1 downto 0) := "00";
signal counter : unsigned (31 downto 0) := x"00_00_00_00";
signal reg_nr : unsigned (3 downto 0) := "0000";
signal counter_valid : std_logic := '0';
signal reg_nr_last : unsigned (3 downto 0) := "0000";
begin
ppm_edge_detection: process (clk)
begin
if rising_edge(clk) then
ppm_sample(1) <= ppm_sample(0); -- record last ppm signal level in ppm_sample(1)
ppm_sample(0) <= ppm_in; -- record current ppm signal level in ppm_sample(0)
case ppm_sample is
when "11" => -- signal level high, reset counter to "0"
counter <= (others => '0');
counter_valid <= '0';
when "10" => -- falling edge -> start counting
counter <= x"00_00_00_01";
counter_valid <= '0';
when "00" => -- signal level is high -> count until overrun detected
if counter < x"00_03_00_00" then
counter <= counter + 1;
end if;
counter_valid <= '0';
when "01" => -- rising edge -> save counter value to corresponding register, reset on counter "overflow"
if counter = x"00_03_00_00" then
reg_nr <= "0000";
else
reg_nr <= reg_nr + 1;
end if;
counter_valid <= '1'
;
when others =>
ppm_sample <= "11";
counter_valid <= '0';
end case;
end if;
end process;
rigister_write: process (clk)
begin
if rising_edge(clk) and counter_valid = '1' then
case reg_nr is
-- when "0000" =>; in this case an overrun occured and there is no valid value
when "0001" =>
ppm_out_1 <= std_logic_vector(counter);
when "0010" =>
ppm_out_2 <= std_logic_vector(counter);
when "0011" =>
ppm_out_3 <= std_logic_vector(counter);
when "0100" =>
ppm_out_4 <= std_logic_vector(counter);
when "0101" =>
ppm_out_5 <= std_logic_vector(counter);
when "0110" =>
ppm_out_6 <= std_logic_vector(counter);
when "0111" =>
ppm_out_7 <= std_logic_vector(counter);
when "1000" =>
ppm_out_8 <= std_logic_vector(counter);
when others =>
-- the values should be saved when not altered -> latches should be generated
end case;
end if;
end process;
interrupt: process (clk)
begin
if rising_edge(clk) then
if reg_nr /= "0000" and reg_nr /= reg_nr_last then
intr_1 <= '1';
else
intr_1 <= '0';
end if;
if reg_nr = "0000" and reg_nr /= reg_nr_last then
intr_comp <= '1';
else
intr_comp <= '1';
end if;
reg_nr_last <= reg_nr;
end if;
end process; --interrupt
end ppm_decoder_behavioral;
| gpl-2.0 | 0bb52d16a71d64397799beaf4567085c | 0.534284 | 3.548363 | false | false | false | false |
hugofragata/euromillions-keygen-vhdl | eurotop.vhd | 1 | 2,372 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity eurotop is
port(SW : in std_logic_vector(7 downto 0);
CLOCK_50 : in std_logic;
KEY : in std_logic_vector(0 downto 0);
HEX0 : out std_logic_vector(6 downto 0);
HEX1 : out std_logic_vector(6 downto 0);
HEX2 : out std_logic_vector(6 downto 0);
HEX3 : out std_logic_vector(6 downto 0);
HEX4 : out std_logic_vector(6 downto 0);
HEX5 : out std_logic_vector(6 downto 0);
HEX6 : out std_logic_vector(6 downto 0)
LEDR : out std_logic);
end eurotop;
architecture Shell of eurotop is
signal s_num0,s_num1,s_num2,s_num3,s_num4 : std_logic_vector(5 downto 0);
signal s_num0hex, s_num1hex, s_est0hex : std_logic_vector(7 downto 0);
signal s_est0, s_est1 : std_logic_vector(3 downto 0);
begin
num0 : entity work.counter50(archi)
port map(C => CLOCK_50,
CLR => SW(7),
hold => SW(0),
Q => s_num0);
num1 : entity work.counter50(archi)
port map(C => CLOCK_50,
CLR => SW(7),
hold => SW(1),
Q => s_num1);
--------num2 : entity work.counter50(archi)
--------port map(C => CLOCK_50,
---------------- CLR => SW(7),
---------------- hold => SW(2),
---------------- Q => s_num2)
--------num3 : entity work.counter50(archi)
--------port map(C => CLOCK_50,
---------------- CLR => SW(7),
---------------- hold => SW(3),
---------------- Q => s_num3)
--------num4 : entity work.counter50(archi)
--------port map(C => CLOCK_50,
---------------- CLR => SW(7),
---------------- hold => SW(4),
---------------- Q => s_num4)
est0 : entity work.counter11(archi)
port map(C => CLOCK_50,
CLR => SW(7),
hold => SW(5),
Q => s_est0);
--------est1 : entity work.counter11(archi)
--------port map(C => CLOCK_50,
---------------- CLR => SW(7),
---------------- hold => SW(6),
---------------- Q => s_est1)
s_num0hex <= "00" & s_num0;
s_num1hex <= "00" & s_num1;
s_est0hex <= "0000" & s_est0;
hexnum0 : entity work.Bin7SegDecoder(Behavioral)
port map(binInput => s_num0hex,
decOut_n => HEX0,
decOut_n1 => HEX1,
decOut_n2 => HEX2);
hexnum1 : entity work.Bin7SegDecoder(Behavioral)
port map(binInput => s_num1hex,
decOut_n => HEX3,
decOut_n1 => HEX4);
hexnum2 : entity work.Bin7SegDecoder(Behavioral)
port map(binInput => s_est0hex,
decOut_n => HEX5,
decOut_n1 => HEX6);
clkdiv : entity work.
end Shell; | mit | 005ed2209f42a4f81d7eddd904002a01 | 0.549747 | 2.817102 | false | false | false | false |
rodrigofegui/UnB | 2017.1/Organização e Arquitetura de Computadores/Trabalhos/Projeto Final/Codificação/reg_bank.vhd | 2 | 1,844 | --módulo para o banco de registradores
--Bibliotecas
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity reg_bank is --declaracao de entidade
generic (
DATA_WIDTH : natural := 32; --32 bits dos dados
ADDRESS_WIDTH : natural := 5 --5 bits para representar enderecos
);
port (--declaracao de entradas e saidas
clk, wren : in std_logic;
radd1, radd2, radd3, wadd : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
wdata : in std_logic_vector(DATA_WIDTH -1 downto 0);
rdata1, rdata2, rdata3: out std_logic_vector(DATA_WIDTH -1 downto 0)
);
end entity reg_bank;
architecture Behavioral of reg_bank is
type regArray is array(0 to DATA_WIDTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal reg_bank : regArray;-- matriz 32 por 32 dos registradores
begin
escrita: process(clk) --processo para escrita
variable aux: integer;--auxiliar para conversao de tipos
begin
if (clk'event and clk = '1') then--executado na subida do clock
aux := to_integer(unsigned(wadd));
if ((wren = '1') and (aux/= 0)) then --escrita deve estar habilitada e nao pode alterar registrador zero
if ((wadd /= radd1) and (wadd /= radd2)) then --leitura tem precedencia sobre escrita
reg_bank(aux) <= wdata; --registrador armazena o dado
end if;
end if;
end if;
end process;
--rdata1 <= (others=>'0') when to_integer(unsigned(radd1)) = 0 else reg_bank(to_integer(unsigned(radd1))); -- registrador zero sempre contem valor nulo
--rdata2 <= (others=>'0') when to_integer(unsigned(radd2)) = 0 else reg_bank(to_integer(unsigned(radd2)));
rdata1 <= reg_bank(to_integer(unsigned(radd1))); -- registrador zero sempre contem valor nulo
rdata2 <= reg_bank(to_integer(unsigned(radd2)));
rdata3 <= reg_bank(to_integer(unsigned(radd3)));
end Behavioral; | gpl-3.0 | ec8b7b9fcef1f095f10c556a6b0e63df | 0.690011 | 3.111486 | false | false | false | false |
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