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JuanMarcosRamirez/WeightedMedianDisenoLogico | misc/FPGA/otros/loopback/tope_TestBench.vhd | 1 | 6,465 | --------------------------------------------------------------------------
--Autor: Jorge Márquez
--fecha: julio 2008
---------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use std.textio.all;
entity tope_tb is
-- generic(
-- vwidth : INTEGER := 8;
-- order : INTEGER := 5;
-- num_cols : INTEGER := 512;
-- num_rows : INTEGER := 512 );
end tope_tb;
architecture TB_ARCHITECTURE of tope_tb is
component tope_rof512_uart --componente
-- generic( --componente
-- vwidth : INTEGER := 8; --componente
-- order : INTEGER := 5; --componente
-- num_cols : INTEGER := 512; --componente
-- num_rows : INTEGER := 512 ); --componente
Port ( tx_female : out std_logic;
rx_female : in std_logic;
LED : out std_logic_vector(7 downto 0);
RSTn : in std_logic;
clk : in std_logic); --componente
end component; --componente
signal tx_female : std_logic:= '0'; --decl señales
signal rx_female : std_logic:= '0'; --decl señales
signal LED : std_logic_vector(7 downto 0) := "00000000"; --decl señales
signal RSTn : std_logic:= '0'; --decl señales
signal clk : std_logic:= '0'; --decl señales
signal TT : std_logic:= '0';
signal byteindata: std_logic_vector(7 downto 0) := "00000000";
begin
UUT : tope_rof512_uart
port map --portmap
(clk => clk, --portmap
RSTn => RSTn, --portmap
LED => LED, --portmap
rx_female => rx_female, --portmap
tx_female => tx_female ); --portmap
rx_female <= byteindata(0);
read_from_file: process(TT) --read_from_file
variable indata_line: line; --read_from_file
variable indata: integer; --read_from_file
file input_data_file: text open read_mode is "C:\MATLAB701\work\lena512_syp_inicializ.ser"; --read_from_file
begin --read_from_file
if rising_edge(TT) or falling_edge(TT) then --read_from_file
readline(input_data_file,indata_line); --read_from_file
read(indata_line,indata); --read_from_file
byteindata <= conv_std_logic_vector(indata,8); --original: D <= conv_std_logic_vector(indata,8);
-- rx_female <= byteindata(0);
if endfile(input_data_file) then --read_from_file
report "end of file -- looping back to start of file"; --read_from_file
file_close(input_data_file); --read_from_file
file_open(input_data_file,"C:\MATLAB701\work\lena512_syp_inicializ.ser"); --read_from_file
end if; --read_from_file
end if; --read_from_file
end process; --read_from_file
-- write_to_file: process(Clk) --write_to_file
-- variable outdata_line: line; --write_to_file
-- variable outdata: integer:=0; --write_to_file
-- file output_data_file: text open write_mode is "D:\JORGETESIS\proc_HW1lena512_syp.ser"; --write_to_file
-- begin --write_to_file
-- if rising_edge(Clk) then --write_to_file
-- outdata := CONV_INTEGER(tx_female); --write_to_file --original: outdata := CONV_INTEGER(unsigned(Dout));
-- -- if DV = '1' then --write_to_file
-- write(outdata_line,outdata); --write_to_file
-- writeline(output_data_file,outdata_line); --write_to_file
-- -- end if; --write_to_file
-- end if; --write_to_file
-- end process; --write_to_file
clock_gen: process --reloj
begin --reloj
Clk <= '0'; --reloj
wait for 10 ns; --reloj
Clk <= '1'; --reloj
wait for 10 ns; --reloj
end process; --reloj
TT_gen: process --patron de transmisión (8680=~1/115200)
begin --patron de transmisión (8680=~1/115200)
TT <= '0'; --patron de transmisión (8680=~1/115200)
wait for 8680 ns; --patron de transmisión (8680=~1/115200)
TT <= '1'; --patron de transmisión (8680=~1/115200)
wait for 8680 ns; --patron de transmisión (8680=~1/115200)
end process;
reset_gen: process --reset
begin --reset
RSTn <= '0'; --reset
wait for 20 ns; --reset
RSTn <= '1'; --reset
wait; --reset
end process; --reset
end TB_ARCHITECTURE;
configuration TESTBENCH_FOR_tope_rof512_uart of tope_tb is
for TB_ARCHITECTURE
for UUT : tope_rof512_uart
use entity work.tope_rof512_uart(comportamiento);
end for;
end for;
end TESTBENCH_FOR_tope_rof512_uart;
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| gpl-3.0 | d4b16851b84eaf844602390c3c6485b9 | 0.926008 | 1.892372 | false | false | false | false |
estadofinito/biblioteca-vhdl | todos-los-archivos/metronomo_tb.vhd | 2 | 1,541 | library IEEE;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_1164.ALL;
ENTITY metronomo_tb IS
END metronomo_tb;
ARCHITECTURE behavior OF metronomo_tb IS
COMPONENT metronomo
PORT(
clk : in STD_LOGIC; -- Reloj de entrada de 50MHz.
reset : in STD_LOGIC; -- Señal de reset.
btn_inc : in STD_LOGIC; -- Incrementa la cantidad de BPM.
btn_dec : in STD_LOGIC; -- Decrementa la cantidad de BPM.
d7s : out STD_LOGIC_VECTOR(7 downto 0);
MUX : out STD_LOGIC_VECTOR(3 downto 0);
clk_out : out STD_LOGIC -- Reloj de salida.
);
END COMPONENT;
--Inputs
signal clk : STD_LOGIC := '0';
signal reset : STD_LOGIC := '0';
signal btn_inc : STD_LOGIC := '0';
signal btn_dec : STD_LOGIC := '0';
--Outputs
signal d7s : STD_LOGIC_VECTOR(7 downto 0);
signal MUX : STD_LOGIC_VECTOR(3 downto 0);
signal clk_out : std_logic;
-- Clock period definitions
constant clk_period : time := 20 ns;
BEGIN
-- Instancia de la unidad bajo prueba.
uut: metronomo PORT MAP (
clk => clk,
reset => reset,
btn_inc => btn_inc,
btn_dec => btn_dec,
d7s => d7s,
MUX => MUX,
clk_out => clk_out
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Proceso de estmulos.
stim_proc: process
begin
reset <= '1';
btn_dec <= '1';
wait for 100 ns;
reset <= '0';
wait;
end process;
END;
| lgpl-2.1 | 6695696c20e69eb2c1b0b41387333453 | 0.587662 | 3.049505 | false | false | false | false |
estadofinito/biblioteca-vhdl | todos-los-archivos/multiplexor_frecuencias_tb.vhd | 2 | 1,918 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY multiplexor_frecuencias_tb IS
END multiplexor_frecuencias_tb;
ARCHITECTURE behavior OF multiplexor_frecuencias_tb IS
COMPONENT multiplexor_frecuencias
PORT(
clk : IN std_logic;
reset : IN std_logic;
selector : IN std_logic_vector(2 downto 0);
salida : OUT std_logic
);
END COMPONENT;
-- Entradas
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal selector : std_logic_vector(2 downto 0) := (others => '0');
-- Salidas
signal salida : std_logic;
-- Definición de reloj
constant clk_period : time := 20 ns;
BEGIN
-- Instancia de la unidad bajo prueba.
uut: multiplexor_frecuencias PORT MAP (
clk => clk,
reset => reset,
selector => selector,
salida => salida
);
-- Definición del proceso de reloj.
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Proceso de estimulos.
stim_proc: process
begin
-- Esta simulación puede tomar mucho tiempo (debido al tiempo de simulación).
-- Se recomienda ejecutar por tramos o dejar corriendo durante la noche o periodo con baja actividad.
reset <= '1';
wait for 100 ns;
reset <= '0';
-- Inicio de prueba.
selector <= "111"; -- Reloj de 4 Hz (tiempo por ciclo: 250ms)
wait for 5000 ms;
selector <= "110"; -- Reloj de 2 Hz (tiempo por ciclo: 500ms)
wait for 5000 ms;
selector <= "101"; -- Reloj de 1 Hz (tiempo por ciclo: 1s)
wait for 5000 ms;
selector <= "100"; -- Reloj de 0.5 Hz (tiempo por ciclo: 2s)
wait for 5000 ms;
selector <= "011"; -- Reloj de 0.25 Hz (tiempo por ciclo: 4s)
wait for 5000 ms;
selector <= "010"; -- Reloj de 0.125 Hz (tiempo por ciclo: 8s)
wait for 5000 ms;
selector <= "001"; -- Reloj de 0.0625 Hz (tiempo por ciclo: 16s)
wait for 5000 ms;
selector <= "000"; -- Nada
wait for 5000 ms;
wait;
wait;
end process;
END; | lgpl-2.1 | 588d43768a9f4b084f162de207587c90 | 0.661105 | 2.996875 | false | false | false | false |
dummylink/plnk_fpga-stack | Examples/xilinx_microblaze/avnet_lx9/pcores/plb_powerlink_v1_00_a/hdl/vhdl/pdi.vhd | 5 | 54,135 | ------------------------------------------------------------------------------------------------------------------------
-- Process Data Interface (PDI) for
-- POWERLINK Communication Processor (PCP): Avalon
-- Application Processor (AP): Avalon
--
-- Copyright (C) 2010 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2010-06-28 V0.01 zelenkaj First version
-- 2010-08-16 V0.10 zelenkaj Added the possibility for more RPDOs
-- 2010-08-23 V0.11 zelenkaj Added IRQ generation
-- 2010-10-04 V0.12 zelenkaj Changed memory size calculation (e.g. generics must include header size)
-- 2010-10-11 V0.13 zelenkaj Bugfix: PCP can't be producer in any case => added generic
-- 2010-10-25 V0.14 zelenkaj Use one Address Adder per DPR port side (reduces LE usage)
-- 2010-11-08 V0.15 zelenkaj Add 8 bytes to control reg of pdi mapped to dpr
-- 2010-11-23 V0.16 zelenkaj Omitted T/RPDO descriptor sections in DPR
-- Omitted "HEX Words" (e.g. DEADC0DE, C00FFEE) and replaced with ZEROS
-- 2011-03-21 V0.17 zelenkaj clean up
-- 2011-03-28 V0.20 zelenkaj Changed: Structure of Control/Status Register
-- Added: LED
-- Added: Events
-- Added/Changed: Asynchronous buffer 2x Ping-Pong
-- 2011-04-06 V0.21 zelenkaj minor fix: activity is only valid if link is present
-- 2011-04-26 V0.22 zelenkaj generic for clock domain selection
-- area optimization in Status/Control Register
-- 2011-04-28 V0.23 zelenkaj clean up to reduce Quartus II warnings
-- 2011-05-06 V0.24 zelenkaj some naming convention changes
-- 2011-05-09 V0.25 zelenkaj minor change in edge detector and syncs (reset to zero)
-- 2011-06-06 V0.26 zelenkaj status/control register enhanced by 8 bytes
-- 2011-06-10 V0.27 zelenkaj bug fix: if dpr size goes below 2**10, error of dpr address width
-- 2011-06-29 V0.28 zelenkaj bug fix: led control was gone and dpr addr width still buggy
-- 2011-07-25 V0.29 zelenkaj LED gadget and asynchronous buffer optional
-- 2011-08-08 V0.30 zelenkaj LED gadget enhancement -> added 8 general purpose outputs
-- 2011-08-16 V0.31 zelenkaj status/control register enhanced by 8 bytes (again...)
-- 2011-11-21 V0.32 zelenkaj added time synchronization feature
-- 2011-11-28 V0.33 zelenkaj added waitrequest signals
-- 2011-11-29 V0.34 zelenkaj event support is optional
-- 2011-12-20 V0.35 zelenkaj changed 2xbuf switch source to AP
------------------------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
USE ieee.math_real.log2;
USE ieee.math_real.ceil;
USE work.memMap.all; --used for memory mapping (alignment, ...)
entity pdi is
generic (
genOnePdiClkDomain_g : boolean := false;
iPdiRev_g : integer := 0; --for HW/SW match verification (0..65535)
iRpdos_g : integer := 3;
iTpdos_g : integer := 1;
genABuf1_g : boolean := true; --if false iABuf1_g must be set to 0!
genABuf2_g : boolean := true; --if false iABuf2_g must be set to 0!
genLedGadget_g : boolean := false;
genTimeSync_g : boolean := false;
genEvent_g : boolean := false;
--PDO buffer size *3
iTpdoBufSize_g : integer := 100;
iRpdo0BufSize_g : integer := 116; --includes header
iRpdo1BufSize_g : integer := 116; --includes header
iRpdo2BufSize_g : integer := 116; --includes header
--asynchronous buffer size
iABuf1_g : integer := 512; --includes header
iABuf2_g : integer := 512 --includes header
);
port (
pcp_reset : in std_logic;
pcp_clk : in std_logic;
ap_reset : in std_logic;
ap_clk : in std_logic;
-- Avalon Slave Interface for PCP
pcp_chipselect : in std_logic;
pcp_read : in std_logic;
pcp_write : in std_logic;
pcp_byteenable : in std_logic_vector(3 DOWNTO 0);
pcp_address : in std_logic_vector(12 DOWNTO 0);
pcp_writedata : in std_logic_vector(31 DOWNTO 0);
pcp_readdata : out std_logic_vector(31 DOWNTO 0);
pcp_waitrequest : out std_logic;
pcp_irq : in std_logic; --should be connected to the Time Cmp Toggle of openMAC!
-- Avalon Slave Interface for AP
ap_chipselect : in std_logic;
ap_read : in std_logic;
ap_write : in std_logic;
ap_byteenable : in std_logic_vector(3 DOWNTO 0);
ap_address : in std_logic_vector(12 DOWNTO 0);
ap_writedata : in std_logic_vector(31 DOWNTO 0);
ap_readdata : out std_logic_vector(31 DOWNTO 0);
ap_waitrequest : out std_logic;
ap_irq : out std_logic; --Sync Irq to the AP
-- async interrupt
ap_asyncIrq : out std_logic; --Async Irq to the Ap
-- LED
ledsOut : out std_logic_vector(15 downto 0) := (others => '0'); --LEDs: GPO7, ..., GPO0, O1, O0, PA1, PL1, PA0, PL0, E, S
phyLink : in std_logic_vector(1 downto 0); --link: phy1, phy0
phyAct : in std_logic_vector(1 downto 0); --acti: phy1, phy0
--PDI change buffer triggers
rpdo_change_tog : in std_logic_vector(2 downto 0);
tpdo_change_tog : in std_logic
);
end entity pdi;
architecture rtl of pdi is
------------------------------------------------------------------------------------------------------------------------
--types
---for pcp and ap side
type pdiSel_t is
record
pcp : std_logic;
ap : std_logic;
end record;
type pdiTrig_t is
record
pcp : std_logic_vector(3 downto 0);
ap : std_logic_vector(3 downto 0);
end record;
type pdi32Bit_t is
record
pcp : std_logic_vector(31 downto 0);
ap : std_logic_vector(31 downto 0);
end record;
------------------------------------------------------------------------------------------------------------------------
--constants
---memory mapping from outside (e.g. Avalon or SPI)
----max memory span of one space
constant extMaxOneSpan : integer := 2 * 1024; --2kB
constant extLog2MaxOneSpan : integer := integer(ceil(log2(real(extMaxOneSpan))));
----control / status register
constant extCntStReg_c : memoryMapping_t := (16#0000#, 16#98#);
----asynchronous buffers
constant extABuf1Tx_c : memoryMapping_t := (16#0800#, iABuf1_g); --header is included in generic value!
constant extABuf1Rx_c : memoryMapping_t := (16#1000#, iABuf1_g); --header is included in generic value!
constant extABuf2Tx_c : memoryMapping_t := (16#1800#, iABuf2_g); --header is included in generic value!
constant extABuf2Rx_c : memoryMapping_t := (16#2000#, iABuf2_g); --header is included in generic value!
----pdo buffer
constant extTpdoBuf_c : memoryMapping_t := (16#2800#, iTpdoBufSize_g); --header is included in generic value!
constant extRpdo0Buf_c : memoryMapping_t := (16#3000#, iRpdo0BufSize_g); --header is included in generic value!
constant extRpdo1Buf_c : memoryMapping_t := (16#3800#, iRpdo1BufSize_g); --header is included in generic value!
constant extRpdo2Buf_c : memoryMapping_t := (16#4000#, iRpdo2BufSize_g); --header is included in generic value!
---memory mapping inside the PDI's DPR
----control / status register
constant intCntStReg_c : memoryMapping_t := (16#0000#, 22 * 4); --bytes mapped to dpr (dword alignment!!!), note: 4 times a double buffer!
----asynchronous buffers
constant intABuf1Tx_c : memoryMapping_t := (intCntStReg_c.base + intCntStReg_c.span, align32(extABuf1Tx_c.span));
constant intABuf1Rx_c : memoryMapping_t := (intABuf1Tx_c.base + intABuf1Tx_c.span, align32(extABuf1Rx_c.span));
constant intABuf2Tx_c : memoryMapping_t := (intABuf1Rx_c.base + intABuf1Rx_c.span, align32(extABuf2Tx_c.span));
constant intABuf2Rx_c : memoryMapping_t := (intABuf2Tx_c.base + intABuf2Tx_c.span, align32(extABuf2Rx_c.span));
----pdo buffers (triple buffers considered!)
constant intTpdoBuf_c : memoryMapping_t := (intABuf2Rx_c.base + intABuf2Rx_c.span, align32(extTpdoBuf_c.span) *3);
constant intRpdo0Buf_c : memoryMapping_t := (intTpdoBuf_c.base + intTpdoBuf_c.span, align32(extRpdo0Buf_c.span)*3);
constant intRpdo1Buf_c : memoryMapping_t := (intRpdo0Buf_c.base + intRpdo0Buf_c.span, align32(extRpdo1Buf_c.span)*3);
constant intRpdo2Buf_c : memoryMapping_t := (intRpdo1Buf_c.base + intRpdo1Buf_c.span, align32(extRpdo2Buf_c.span)*3);
----obtain dpr size of different configurations
constant dprSize_c : integer := ( intCntStReg_c.span +
intABuf1Tx_c.span +
intABuf1Rx_c.span +
intABuf2Tx_c.span +
intABuf2Rx_c.span +
intTpdoBuf_c.span +
intRpdo0Buf_c.span +
intRpdo1Buf_c.span +
intRpdo2Buf_c.span );
constant dprAddrWidth_c : integer := integer(ceil(log2(real(dprSize_c))));
---other constants
constant magicNumber_c : integer := 16#50435000#;
constant pdiRev_c : integer := iPdiRev_g;
------------------------------------------------------------------------------------------------------------------------
--signals
---dpr
type dprSig_t is
record
addr : std_logic_vector(dprAddrWidth_c-2-1 downto 0); --double word address!
addrOff : std_logic_vector(dprAddrWidth_c-2 downto 0); --double word address!
be : std_logic_vector(3 downto 0);
din : std_logic_vector(31 downto 0);
wr : std_logic;
end record;
type dprPdi_t is
record
pcp : dprSig_t;
ap : dprSig_t;
end record;
----signals to the DPR
signal dpr : dprPdi_t;
signal dprOut : pdi32Bit_t;
----control / status register
signal dprCntStReg_s : dprPdi_t;
----asynchronous buffers
signal dprABuf1Tx_s : dprPdi_t;
signal dprABuf1Rx_s : dprPdi_t;
signal dprABuf2Tx_s : dprPdi_t;
signal dprABuf2Rx_s : dprPdi_t;
----pdo buffers (triple buffers considered!)
signal dprTpdoBuf_s : dprPdi_t := (((others => '0'), (others => '0'), (others => '0'), (others => '0'), '0'),
((others => '0'), (others => '0'), (others => '0'), (others => '0'), '0'));
signal dprRpdo0Buf_s : dprPdi_t := (((others => '0'), (others => '0'), (others => '0'), (others => '0'), '0'),
((others => '0'), (others => '0'), (others => '0'), (others => '0'), '0'));
signal dprRpdo1Buf_s : dprPdi_t := (((others => '0'), (others => '0'), (others => '0'), (others => '0'), '0'),
((others => '0'), (others => '0'), (others => '0'), (others => '0'), '0'));
signal dprRpdo2Buf_s : dprPdi_t := (((others => '0'), (others => '0'), (others => '0'), (others => '0'), '0'),
((others => '0'), (others => '0'), (others => '0'), (others => '0'), '0'));
---chip select
----control / status register
signal selCntStReg_s : pdiSel_t;
----asynchronous buffers
signal selABuf1Tx_s : pdiSel_t;
signal selABuf1Rx_s : pdiSel_t;
signal selABuf2Tx_s : pdiSel_t;
signal selABuf2Rx_s : pdiSel_t;
----pdo buffers (triple buffers considered!)
signal selTpdoBuf_s : pdiSel_t;
signal selRpdo0Buf_s : pdiSel_t;
signal selRpdo1Buf_s : pdiSel_t;
signal selRpdo2Buf_s : pdiSel_t;
---data output
----control / status register
signal outCntStReg_s : pdi32Bit_t;
----asynchronous buffers
signal outABuf1Tx_s : pdi32Bit_t;
signal outABuf1Rx_s : pdi32Bit_t;
signal outABuf2Tx_s : pdi32Bit_t;
signal outABuf2Rx_s : pdi32Bit_t;
----pdo buffers (triple buffers considered!)
signal outTpdoBuf_s : pdi32Bit_t := ((others => '0'), (others => '0'));
signal outRpdo0Buf_s : pdi32Bit_t := ((others => '0'), (others => '0'));
signal outRpdo1Buf_s : pdi32Bit_t := ((others => '0'), (others => '0'));
signal outRpdo2Buf_s : pdi32Bit_t := ((others => '0'), (others => '0'));
---virtual buffer control/state
signal vBufTriggerPdo_s : pdiTrig_t; --tpdo, rpdo2, rpdo1, rpdo0
signal vBufSel_s : pdi32Bit_t := ((others => '1'), (others => '1')); --TXPDO_ACK | RXPDO2_ACK | RXPDO1_ACK | RXPDO0_ACK
---ap irq generation
signal apIrqValue : std_logic_vector(31 downto 0);
signal apIrqControlPcp,
apIrqControlPcp2,
apIrqControlApOut,
apIrqControlApIn : std_logic_vector(15 downto 0);
signal ap_irq_s : std_logic;
---address calulation result
signal pcp_addrRes : std_logic_vector(dprAddrWidth_c-2 downto 0);
signal ap_addrRes : std_logic_vector(dprAddrWidth_c-2 downto 0);
---EVENT stuff
signal pcp_eventSet_s, --pulse to set event
pcp_eventRead : std_logic_vector(15 downto 0);
signal ap_eventAck_p, --pulse to ack event
ap_eventAck : std_logic_vector(15 downto 0);
signal asyncIrqCtrlOut_s,
asyncIrqCtrlIn_s : std_logic_vector(15 downto 0);
signal ap_asyncIrq_s : std_logic; --Async Irq to the Ap
signal phyLink_s,
phyLinkEvent : std_logic_vector(phyLink'range);
--LED stuff
signal pcp_ledForce_s,
pcp_ledSet_s : std_logic_vector(15 downto 0) := (others => '0');
signal ap_ledForce_s,
ap_ledSet_s : std_logic_vector(15 downto 0) := (others => '0');
signal hw_ledForce_s,
hw_ledSet_s : std_logic_vector(15 downto 0) := (others => '0');
--TIME SYNCHRONIZATION
signal pcp_timeSyncDBufSel : std_logic;
signal ap_timeSyncDBufSel : std_logic;
begin
ASSERT NOT(iRpdos_g < 1 or iRpdos_g > 3)
REPORT "Only 1, 2 or 3 Rpdos are supported!"
severity failure;
ASSERT NOT(iTpdos_g /= 1)
REPORT "Only 1 Tpdo is supported!"
severity failure;
------------------------------------------------------------------------------------------------------------------------
-- merge data to pcp/ap
theMerger : block
begin
pcp_readdata <= outCntStReg_s.pcp when selCntStReg_s.pcp = '1' else
outABuf1Tx_s.pcp when selABuf1Tx_s.pcp = '1' else
outABuf1Rx_s.pcp when selABuf1Rx_s.pcp = '1' else
outABuf2Tx_s.pcp when selABuf2Tx_s.pcp = '1' else
outABuf2Rx_s.pcp when selABuf2Rx_s.pcp = '1' else
outTpdoBuf_s.pcp when selTpdoBuf_s.pcp = '1' else
outRpdo0Buf_s.pcp when selRpdo0Buf_s.pcp = '1' else
outRpdo1Buf_s.pcp when selRpdo1Buf_s.pcp = '1' else
outRpdo2Buf_s.pcp when selRpdo2Buf_s.pcp = '1' else
(others => '0');
ap_readdata <= outCntStReg_s.ap when selCntStReg_s.ap = '1' else
outABuf1Tx_s.ap when selABuf1Tx_s.ap = '1' else
outABuf1Rx_s.ap when selABuf1Rx_s.ap = '1' else
outABuf2Tx_s.ap when selABuf2Tx_s.ap = '1' else
outABuf2Rx_s.ap when selABuf2Rx_s.ap = '1' else
outTpdoBuf_s.ap when selTpdoBuf_s.ap = '1' else
outRpdo0Buf_s.ap when selRpdo0Buf_s.ap = '1' else
outRpdo1Buf_s.ap when selRpdo1Buf_s.ap = '1' else
outRpdo2Buf_s.ap when selRpdo2Buf_s.ap = '1' else
(others => '0');
end block;
--
------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------
-- dual ported RAM
theDpr : entity work.pdi_dpr
generic map (
NUM_WORDS => (dprSize_c/4),
LOG2_NUM_WORDS => dprAddrWidth_c-2
)
port map (
address_a => pcp_addrRes(dprAddrWidth_c-2-1 downto 0),
address_b => ap_addrRes(dprAddrWidth_c-2-1 downto 0),
byteena_a => dpr.pcp.be,
byteena_b => dpr.ap.be,
clock_a => pcp_clk,
clock_b => ap_clk,
data_a => dpr.pcp.din,
data_b => dpr.ap.din,
wren_a => dpr.pcp.wr,
wren_b => dpr.ap.wr,
q_a => dprOut.pcp,
q_b => dprOut.ap
);
pcp_addrRes <= '0' & pcp_address(dprAddrWidth_c-2-1 downto 0) + dpr.pcp.addrOff;
dpr.pcp <= dprCntStReg_s.pcp when selCntStReg_s.pcp = '1' else
dprABuf1Tx_s.pcp when selABuf1Tx_s.pcp = '1' else
dprABuf1Rx_s.pcp when selABuf1Rx_s.pcp = '1' else
dprABuf2Tx_s.pcp when selABuf2Tx_s.pcp = '1' else
dprABuf2Rx_s.pcp when selABuf2Rx_s.pcp = '1' else
dprTpdoBuf_s.pcp when selTpdoBuf_s.pcp = '1' else
dprRpdo0Buf_s.pcp when selRpdo0Buf_s.pcp = '1' and iRpdos_g >= 1 else
dprRpdo1Buf_s.pcp when selRpdo1Buf_s.pcp = '1' and iRpdos_g >= 2 else
dprRpdo2Buf_s.pcp when selRpdo2Buf_s.pcp = '1' and iRpdos_g >= 3 else
((others => '0'), (others => '0'), (others => '0'), (others => '0'), '0');
ap_addrRes <= '0' & ap_address(dprAddrWidth_c-2-1 downto 0) + dpr.ap.addrOff;
dpr.ap <= dprCntStReg_s.ap when selCntStReg_s.ap = '1' else
dprABuf1Tx_s.ap when selABuf1Tx_s.ap = '1' else
dprABuf1Rx_s.ap when selABuf1Rx_s.ap = '1' else
dprABuf2Tx_s.ap when selABuf2Tx_s.ap = '1' else
dprABuf2Rx_s.ap when selABuf2Rx_s.ap = '1' else
dprTpdoBuf_s.ap when selTpdoBuf_s.ap = '1' else
dprRpdo0Buf_s.ap when selRpdo0Buf_s.ap = '1' and iRpdos_g >= 1 else
dprRpdo1Buf_s.ap when selRpdo1Buf_s.ap = '1' and iRpdos_g >= 2 else
dprRpdo2Buf_s.ap when selRpdo2Buf_s.ap = '1' and iRpdos_g >= 3 else
((others => '0'), (others => '0'), (others => '0'), (others => '0'), '0');
------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------
-- address decoder to generate select signals for different memory ranges
theAddressDecoder : block
begin
--pcp side
---control / status register
selCntStReg_s.pcp <= pcp_chipselect when (conv_integer(pcp_address)*4 >= extCntStReg_c.base and
(conv_integer(pcp_address)*4 < extCntStReg_c.base + extCntStReg_c.span))
else '0';
---asynchronous buffers
selABuf1Tx_s.pcp <= pcp_chipselect when (conv_integer(pcp_address)*4 >= extABuf1Tx_c.base and
(conv_integer(pcp_address)*4 < extABuf1Tx_c.base + extABuf1Tx_c.span))
else '0';
selABuf1Rx_s.pcp <= pcp_chipselect when (conv_integer(pcp_address)*4 >= extABuf1Rx_c.base and
(conv_integer(pcp_address)*4 < extABuf1Rx_c.base + extABuf1Rx_c.span))
else '0';
selABuf2Tx_s.pcp <= pcp_chipselect when (conv_integer(pcp_address)*4 >= extABuf2Tx_c.base and
(conv_integer(pcp_address)*4 < extABuf2Tx_c.base + extABuf2Tx_c.span))
else '0';
selABuf2Rx_s.pcp <= pcp_chipselect when (conv_integer(pcp_address)*4 >= extABuf2Rx_c.base and
(conv_integer(pcp_address)*4 < extABuf2Rx_c.base + extABuf2Rx_c.span))
else '0';
---pdo buffers (triple buffers considered!)
selTpdoBuf_s.pcp <= pcp_chipselect when (conv_integer(pcp_address)*4 >= extTpdoBuf_c.base and
(conv_integer(pcp_address)*4 < extTpdoBuf_c.base + extTpdoBuf_c.span))
else '0';
selRpdo0Buf_s.pcp <= pcp_chipselect when (conv_integer(pcp_address)*4 >= extRpdo0Buf_c.base and
(conv_integer(pcp_address)*4 < extRpdo0Buf_c.base + extRpdo0Buf_c.span))
else '0';
selRpdo1Buf_s.pcp <= pcp_chipselect when (conv_integer(pcp_address)*4 >= extRpdo1Buf_c.base and
(conv_integer(pcp_address)*4 < extRpdo1Buf_c.base + extRpdo1Buf_c.span))
else '0';
selRpdo2Buf_s.pcp <= pcp_chipselect when (conv_integer(pcp_address)*4 >= extRpdo2Buf_c.base and
(conv_integer(pcp_address)*4 < extRpdo2Buf_c.base + extRpdo2Buf_c.span))
else '0';
--ap side
---control / status register
selCntStReg_s.ap <= ap_chipselect when (conv_integer(ap_address)*4 >= extCntStReg_c.base and
(conv_integer(ap_address)*4 < extCntStReg_c.base + extCntStReg_c.span))
else '0';
---asynchronous buffers
selABuf1Tx_s.ap <= ap_chipselect when (conv_integer(ap_address)*4 >= extABuf1Tx_c.base and
(conv_integer(ap_address)*4 < extABuf1Tx_c.base + extABuf1Tx_c.span))
else '0';
selABuf1Rx_s.ap <= ap_chipselect when (conv_integer(ap_address)*4 >= extABuf1Rx_c.base and
(conv_integer(ap_address)*4 < extABuf1Rx_c.base + extABuf1Rx_c.span))
else '0';
selABuf2Tx_s.ap <= ap_chipselect when (conv_integer(ap_address)*4 >= extABuf2Tx_c.base and
(conv_integer(ap_address)*4 < extABuf2Tx_c.base + extABuf2Tx_c.span))
else '0';
selABuf2Rx_s.ap <= ap_chipselect when (conv_integer(ap_address)*4 >= extABuf2Rx_c.base and
(conv_integer(ap_address)*4 < extABuf2Rx_c.base + extABuf2Rx_c.span))
else '0';
---pdo buffers (triple buffers considered!)
selTpdoBuf_s.ap <= ap_chipselect when (conv_integer(ap_address)*4 >= extTpdoBuf_c.base and
(conv_integer(ap_address)*4 < extTpdoBuf_c.base + extTpdoBuf_c.span))
else '0';
selRpdo0Buf_s.ap <= ap_chipselect when (conv_integer(ap_address)*4 >= extRpdo0Buf_c.base and
(conv_integer(ap_address)*4 < extRpdo0Buf_c.base + extRpdo0Buf_c.span))
else '0';
selRpdo1Buf_s.ap <= ap_chipselect when (conv_integer(ap_address)*4 >= extRpdo1Buf_c.base and
(conv_integer(ap_address)*4 < extRpdo1Buf_c.base + extRpdo1Buf_c.span))
else '0';
selRpdo2Buf_s.ap <= ap_chipselect when (conv_integer(ap_address)*4 >= extRpdo2Buf_c.base and
(conv_integer(ap_address)*4 < extRpdo2Buf_c.base + extRpdo2Buf_c.span))
else '0';
end block theAddressDecoder;
------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------
-- control / status register
theCntrlStatReg4Pcp : entity work.pdiControlStatusReg
generic map (
bIsPcp => true,
iAddrWidth_g => extLog2MaxOneSpan-2,
iBaseDpr_g => 16#8#/4, --base address of content to be mapped to dpr
iSpanDpr_g => intCntStReg_c.span/4, --size of content to be mapped to dpr
iBaseMap2_g => intCntStReg_c.base/4, --base address in dpr
iDprAddrWidth_g => dprCntStReg_s.pcp.addr'length,
iRpdos_g => iRpdos_g,
genLedGadget_g => genLedGadget_g,
genTimeSync_g => genTimeSync_g,
genEvent_g => genEvent_g,
--register content
---constant values
magicNumber => conv_std_logic_vector(magicNumber_c, 32),
pdiRev => conv_std_logic_vector(pdiRev_c, 16),
tPdoBuffer => conv_std_logic_vector(extTpdoBuf_c.base, 16) &
conv_std_logic_vector(extTpdoBuf_c.span, 16),
rPdo0Buffer => conv_std_logic_vector(extRpdo0Buf_c.base, 16) &
conv_std_logic_vector(extRpdo0Buf_c.span, 16),
rPdo1Buffer => conv_std_logic_vector(extRpdo1Buf_c.base, 16) &
conv_std_logic_vector(extRpdo1Buf_c.span, 16),
rPdo2Buffer => conv_std_logic_vector(extRpdo2Buf_c.base, 16) &
conv_std_logic_vector(extRpdo2Buf_c.span, 16),
asyncBuffer1Tx => conv_std_logic_vector(extABuf1Tx_c.base, 16) &
conv_std_logic_vector(extABuf1Tx_c.span, 16),
asyncBuffer1Rx => conv_std_logic_vector(extABuf1Rx_c.base, 16) &
conv_std_logic_vector(extABuf1Rx_c.span, 16),
asyncBuffer2Tx => conv_std_logic_vector(extABuf2Tx_c.base, 16) &
conv_std_logic_vector(extABuf2Tx_c.span, 16),
asyncBuffer2Rx => conv_std_logic_vector(extABuf2Rx_c.base, 16) &
conv_std_logic_vector(extABuf2Rx_c.span, 16)
)
port map (
--memory mapped interface
clk => pcp_clk,
rst => pcp_reset,
sel => selCntStReg_s.pcp,
wr => pcp_write,
rd => pcp_read,
addr => pcp_address(extLog2MaxOneSpan-1-2 downto 0),
be => pcp_byteenable,
din => pcp_writedata,
dout => outCntStReg_s.pcp,
--register content
---virtual buffer control signals
pdoVirtualBufferSel => vBufSel_s.pcp,
tPdoTrigger => vBufTriggerPdo_s.pcp(3),
rPdoTrigger => vBufTriggerPdo_s.pcp(2 downto 0),
---event registers
eventAckIn => pcp_eventRead,
eventAckOut => pcp_eventSet_s,
---async irq (by event)
asyncIrqCtrlIn => (others => '0'), --not for pcp
asyncIrqCtrlOut => open, --not for pcp
---led stuff
ledCnfgIn => pcp_ledForce_s,
ledCnfgOut => pcp_ledForce_s,
ledCtrlIn => pcp_ledSet_s,
ledCtrlOut => pcp_ledSet_s,
---time synchronization
doubleBufSel_out => open, --PCP is the sink
doubleBufSel_in => pcp_timeSyncDBufSel,
timeSyncIrq => '0', --pcp is not interested
--dpr interface (from PCP/AP to DPR)
dprAddrOff => dprCntStReg_s.pcp.addrOff,
dprDin => dprCntStReg_s.pcp.din,
dprDout => dprOut.pcp,
dprBe => dprCntStReg_s.pcp.be,
dprWr => dprCntStReg_s.pcp.wr,
--ap irq generation
apIrqControlOut => apIrqControlPcp,
--SW is blind, thus, use the transferred enable signal from AP!
apIrqControlIn => apIrqControlPcp2,
--hw acc triggering
rpdo_change_tog => rpdo_change_tog,
tpdo_change_tog => tpdo_change_tog
);
--only read 15 bits of the written, the msbit is read from transferred AP bit
apIrqControlPcp2(14 downto 0) <= apIrqControlPcp(14 downto 0);
--transfer the AP's enable signal to PCP, since SW is blind... :)
syncApEnable2Pcp : entity work.sync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
port map (
din => apIrqControlApOut(15),
dout => apIrqControlPcp2(15),
clk => pcp_clk,
rst => pcp_reset
);
--sync double buffer select for time sync to AP if the feature is enabled
-- note: signal toggles on PCP side when NETTIME [seconds] is written
syncDBuf_TimeSync : entity work.sync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
port map (
dout => pcp_timeSyncDBufSel,
din => ap_timeSyncDBufSel,
clk => pcp_clk,
rst => pcp_reset
);
theCntrlStatReg4Ap : entity work.pdiControlStatusReg
generic map (
bIsPcp => false,
iAddrWidth_g => extLog2MaxOneSpan-2,
iBaseDpr_g => 16#8#/4, --base address of content to be mapped to dpr
iSpanDpr_g => intCntStReg_c.span/4, --size of content to be mapped to dpr
iBaseMap2_g => intCntStReg_c.base/4, --base address in dpr
iDprAddrWidth_g => dprCntStReg_s.ap.addr'length,
iRpdos_g => iRpdos_g,
genLedGadget_g => genLedGadget_g,
genTimeSync_g => genTimeSync_g,
genEvent_g => genEvent_g,
--register content
---constant values
magicNumber => conv_std_logic_vector(magicNumber_c, 32),
pdiRev => conv_std_logic_vector(pdiRev_c, 16),
tPdoBuffer => conv_std_logic_vector(extTpdoBuf_c.base, 16) &
conv_std_logic_vector(extTpdoBuf_c.span, 16),
rPdo0Buffer => conv_std_logic_vector(extRpdo0Buf_c.base, 16) &
conv_std_logic_vector(extRpdo0Buf_c.span, 16),
rPdo1Buffer => conv_std_logic_vector(extRpdo1Buf_c.base, 16) &
conv_std_logic_vector(extRpdo1Buf_c.span, 16),
rPdo2Buffer => conv_std_logic_vector(extRpdo2Buf_c.base, 16) &
conv_std_logic_vector(extRpdo2Buf_c.span, 16),
asyncBuffer1Tx => conv_std_logic_vector(extABuf1Tx_c.base, 16) &
conv_std_logic_vector(extABuf1Tx_c.span, 16),
asyncBuffer1Rx => conv_std_logic_vector(extABuf1Rx_c.base, 16) &
conv_std_logic_vector(extABuf1Rx_c.span, 16),
asyncBuffer2Tx => conv_std_logic_vector(extABuf2Tx_c.base, 16) &
conv_std_logic_vector(extABuf2Tx_c.span, 16),
asyncBuffer2Rx => conv_std_logic_vector(extABuf2Rx_c.base, 16) &
conv_std_logic_vector(extABuf2Rx_c.span, 16)
)
port map (
--memory mapped interface
clk => ap_clk,
rst => ap_reset,
sel => selCntStReg_s.ap,
wr => ap_write,
rd => ap_read,
addr => ap_address(extLog2MaxOneSpan-1-2 downto 0),
be => ap_byteenable,
din => ap_writedata,
dout => outCntStReg_s.ap,
--register content
---virtual buffer control signals
pdoVirtualBufferSel => vBufSel_s.ap,
tPdoTrigger => vBufTriggerPdo_s.ap(3),
rPdoTrigger => vBufTriggerPdo_s.ap(2 downto 0),
---event registers
eventAckIn => ap_eventAck,
eventAckOut => ap_eventAck_p,
---async irq (by event)
asyncIrqCtrlIn => asyncIrqCtrlIn_s,
asyncIrqCtrlOut => asyncIrqCtrlOut_s,
---led stuff
ledCnfgIn => ap_ledForce_s,
ledCnfgOut => ap_ledForce_s,
ledCtrlIn => ap_ledSet_s,
ledCtrlOut => ap_ledSet_s,
---time synchronization
doubleBufSel_out => ap_timeSyncDBufSel,
doubleBufSel_in => '0', --AP is the source
timeSyncIrq => ap_irq_s,
--dpr interface (from PCP/AP to DPR)
dprAddrOff => dprCntStReg_s.ap.addrOff,
dprDin => dprCntStReg_s.ap.din,
dprDout => dprOut.ap,
dprBe => dprCntStReg_s.ap.be,
dprWr => dprCntStReg_s.ap.wr,
--ap irq generation
--apIrqValue =>
apIrqControlOut => apIrqControlApOut,
apIrqControlIn => apIrqControlApIn,
rpdo_change_tog => (others => '0'),
tpdo_change_tog => '0'
);
theApIrqGenerator : entity work.apIrqGen
generic map (
genOnePdiClkDomain_g => genOnePdiClkDomain_g
)
port map (
--CLOCK DOMAIN PCP
clkA => pcp_clk,
rstA => pcp_reset,
irqA => pcp_irq,
--preValA => apIrqValue,
enableA => apIrqControlPcp(7),
modeA => apIrqControlPcp(6),
setA => apIrqControlPcp(0),
--CLOCK DOMAIN AP
clkB => ap_clk,
rstB => ap_reset,
ackB => apIrqControlApOut(0),
irqB => ap_irq_s
);
--irq enabled by apIrqControlApOut(15)
ap_irq <= ap_irq_s and apIrqControlApOut(15);
apIrqControlApIn <= apIrqControlApOut(15) & "000" & x"00" & "000" & ap_irq_s;
--the LED stuff
genLedGadget : if genLedGadget_g generate
--first set the hw leds
hw_ledForce_s <= x"00" & "00111100"; --phy1 and 0 act and link
hw_ledSet_s <= x"00" & "00" & (phyAct(1) and phyLink(1)) & phyLink(1) & (phyAct(0) and phyLink(0)) & phyLink(0) & "00";
theLedGadget : entity work.pdiLed
generic map (
iLedWidth_g => ledsOut'length
)
port map (
--src A (lowest priority)
srcAled => hw_ledSet_s(ledsOut'range),
srcAforce => hw_ledForce_s(ledsOut'range),
--src B
srcBled => pcp_ledSet_s(ledsOut'range),
srcBforce => pcp_ledForce_s(ledsOut'range),
--src C (highest priority)
srcCled => ap_ledSet_s(ledsOut'range),
srcCforce => ap_ledForce_s(ledsOut'range),
--led output
ledOut => ledsOut
);
end generate;
genEventComp : if genEvent_g generate
begin
theEventBlock : block
--set here the number of events
constant iSwEvent_c : integer := 1;
constant iHwEvent_c : integer := 2;
signal eventSetA : std_logic_vector(iSwEvent_c-1 downto 0);
signal eventReadA : std_logic_vector(iSwEvent_c+iHwEvent_c-1 downto 0);
signal eventAckB : std_logic_vector(iSwEvent_c+iHwEvent_c-1 downto 0);
signal eventReadB : std_logic_vector(iSwEvent_c+iHwEvent_c-1 downto 0);
begin
--event mapping: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-- in register x x x x x x x x hw hw x x x x x sw
-- in pdiEvent hw hw sw
eventSetA <= pcp_eventSet_s(0 downto 0); --pcp sets sw event (I know, its called generic event, bla...)
pcp_eventRead <= x"00" & eventReadA(iSwEvent_c+iHwEvent_c-1 downto iSwEvent_c) &
"00000" & eventReadA(iSwEvent_c-1 downto 0);
eventAckB <= ap_eventAck_p(7 downto 6) & ap_eventAck_p(0); --ap acks events
ap_eventAck <= x"00" & eventReadB(iSwEvent_c+iHwEvent_c-1 downto iSwEvent_c) &
"00000" & eventReadB(iSwEvent_c-1 downto 0);
theEventStuff : entity work.pdiEvent
--16 bit
-- sw is at bit 0
-- hw is at bit 6 and 7
generic map (
genOnePdiClkDomain_g => genOnePdiClkDomain_g,
iSwEvent_g => 1,
iHwEvent_g => 2
)
port map (
--port A -> PCP
clkA => pcp_clk,
rstA => pcp_reset,
eventSetA => eventSetA,
eventReadA => eventReadA,
--port B -> AP
clkB => ap_clk,
rstB => ap_reset,
eventAckB => eventAckB,
eventReadB => eventReadB,
--hw event set pulse (must be synchronous to clkB!)
hwEventSetPulseB => phyLinkEvent
);
--generate async interrupt
asyncIrq : process(ap_eventAck)
variable tmp : std_logic;
begin
tmp := '0';
for i in ap_eventAck'range loop
tmp := tmp or ap_eventAck(i);
end loop;
ap_asyncIrq_s <= tmp;
end process;
--IRQ is asserted if enabled by AP
ap_asyncIrq <= ap_asyncIrq_s and asyncIrqCtrlOut_s(15);
asyncIrqCtrlIn_s(15) <= asyncIrqCtrlOut_s(15);
asyncIrqCtrlIn_s(14 downto 1) <= (others => '0'); --ignoring the rest
asyncIrqCtrlIn_s(0) <= ap_asyncIrq_s; --AP may poll IRQ level
syncPhyLinkGen : for i in phyLink'range generate
syncPhyLink : entity work.sync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
port map (
din => phyLink(i),
dout => phyLink_s(i),
clk => ap_clk,
rst => ap_reset
);
detPhyLinkEdge : entity work.edgeDet
port map (
din => phyLink_s(i),
rising => open,
falling => phyLinkEvent(i), --if phy link deasserts - EVENT!!!
any => open,
clk => ap_clk,
rst => ap_reset
);
end generate;
end block;
end generate;
------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------
-- asynchronous Buffer 1 Tx
genABuf1Tx : if genABuf1_g generate
theAsyncBuf1Tx4Pcp : entity work.pdiSimpleReg
generic map (
iAddrWidth_g => extLog2MaxOneSpan-2,
iBaseMap2_g => intABuf1Tx_c.base/4,
iDprAddrWidth_g => dprABuf1Tx_s.pcp.addr'length
)
port map (
--memory mapped interface
sel => selABuf1Tx_s.pcp,
wr => pcp_write,
rd => pcp_read,
addr => pcp_address(extLog2MaxOneSpan-1-2 downto 0),
be => pcp_byteenable,
din => pcp_writedata,
dout => outABuf1Tx_s.pcp,
--dpr interface (from PCP/AP to DPR)
dprAddrOff => dprABuf1Tx_s.pcp.addrOff,
dprDin => dprABuf1Tx_s.pcp.din,
dprDout => dprOut.pcp,
dprBe => dprABuf1Tx_s.pcp.be,
dprWr => dprABuf1Tx_s.pcp.wr
);
theAsyncBuf1Tx4Ap : entity work.pdiSimpleReg
generic map (
iAddrWidth_g => extLog2MaxOneSpan-2,
iBaseMap2_g => intABuf1Tx_c.base/4,
iDprAddrWidth_g => dprABuf1Tx_s.ap.addr'length
)
port map (
--memory mapped interface
sel => selABuf1Tx_s.ap,
wr => ap_write,
rd => ap_read,
addr => ap_address(extLog2MaxOneSpan-1-2 downto 0),
be => ap_byteenable,
din => ap_writedata,
dout => outABuf1Tx_s.ap,
--dpr interface (from PCP/AP to DPR)
dprAddrOff => dprABuf1Tx_s.ap.addrOff,
dprDin => dprABuf1Tx_s.ap.din,
dprDout => dprOut.ap,
dprBe => dprABuf1Tx_s.ap.be,
dprWr => dprABuf1Tx_s.ap.wr
);
end generate;
------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------
-- asynchronous Buffer 1 Rx
genABuf1Rx : if genABuf1_g generate
theAsyncBuf1Rx4Pcp : entity work.pdiSimpleReg
generic map (
iAddrWidth_g => extLog2MaxOneSpan-2,
iBaseMap2_g => intABuf1Rx_c.base/4,
iDprAddrWidth_g => dprABuf1Rx_s.pcp.addr'length
)
port map (
--memory mapped interface
sel => selABuf1Rx_s.pcp,
wr => pcp_write,
rd => pcp_read,
addr => pcp_address(extLog2MaxOneSpan-1-2 downto 0),
be => pcp_byteenable,
din => pcp_writedata,
dout => outABuf1Rx_s.pcp,
--dpr interface (from PCP/AP to DPR)
dprAddrOff => dprABuf1Rx_s.pcp.addrOff,
dprDin => dprABuf1Rx_s.pcp.din,
dprDout => dprOut.pcp,
dprBe => dprABuf1Rx_s.pcp.be,
dprWr => dprABuf1Rx_s.pcp.wr
);
theAsyncBuf1Rx4Ap : entity work.pdiSimpleReg
generic map (
iAddrWidth_g => extLog2MaxOneSpan-2,
iBaseMap2_g => intABuf1Rx_c.base/4,
iDprAddrWidth_g => dprABuf1Rx_s.ap.addr'length
)
port map (
--memory mapped interface
sel => selABuf1Rx_s.ap,
wr => ap_write,
rd => ap_read,
addr => ap_address(extLog2MaxOneSpan-1-2 downto 0),
be => ap_byteenable,
din => ap_writedata,
dout => outABuf1Rx_s.ap,
--dpr interface (from PCP/AP to DPR)
dprAddrOff => dprABuf1Rx_s.ap.addrOff,
dprDin => dprABuf1Rx_s.ap.din,
dprDout => dprOut.ap,
dprBe => dprABuf1Rx_s.ap.be,
dprWr => dprABuf1Rx_s.ap.wr
);
end generate;
------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------
-- asynchronous Buffer 2 Tx
genABuf2Tx : if genABuf2_g generate
theAsyncBuf2Tx4Pcp : entity work.pdiSimpleReg
generic map (
iAddrWidth_g => extLog2MaxOneSpan-2,
iBaseMap2_g => intABuf2Tx_c.base/4,
iDprAddrWidth_g => dprABuf2Tx_s.pcp.addr'length
)
port map (
--memory mapped interface
sel => selABuf2Tx_s.pcp,
wr => pcp_write,
rd => pcp_read,
addr => pcp_address(extLog2MaxOneSpan-1-2 downto 0),
be => pcp_byteenable,
din => pcp_writedata,
dout => outABuf2Tx_s.pcp,
--dpr interface (from PCP/AP to DPR)
dprAddrOff => dprABuf2Tx_s.pcp.addrOff,
dprDin => dprABuf2Tx_s.pcp.din,
dprDout => dprOut.pcp,
dprBe => dprABuf2Tx_s.pcp.be,
dprWr => dprABuf2Tx_s.pcp.wr
);
theAsyncBuf2Tx4Ap : entity work.pdiSimpleReg
generic map (
iAddrWidth_g => extLog2MaxOneSpan-2,
iBaseMap2_g => intABuf2Tx_c.base/4,
iDprAddrWidth_g => dprABuf2Tx_s.ap.addr'length
)
port map (
--memory mapped interface
sel => selABuf2Tx_s.ap,
wr => ap_write,
rd => ap_read,
addr => ap_address(extLog2MaxOneSpan-1-2 downto 0),
be => ap_byteenable,
din => ap_writedata,
dout => outABuf2Tx_s.ap,
--dpr interface (from PCP/AP to DPR)
dprAddrOff => dprABuf2Tx_s.ap.addrOff,
dprDin => dprABuf2Tx_s.ap.din,
dprDout => dprOut.ap,
dprBe => dprABuf2Tx_s.ap.be,
dprWr => dprABuf2Tx_s.ap.wr
);
end generate;
------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------
-- asynchronous Buffer 2 Rx
genABuf2Rx : if genABuf2_g generate
theAsyncBuf2Rx4Pcp : entity work.pdiSimpleReg
generic map (
iAddrWidth_g => extLog2MaxOneSpan-2,
iBaseMap2_g => intABuf2Rx_c.base/4,
iDprAddrWidth_g => dprABuf2Rx_s.pcp.addr'length
)
port map (
--memory mapped interface
sel => selABuf2Rx_s.pcp,
wr => pcp_write,
rd => pcp_read,
addr => pcp_address(extLog2MaxOneSpan-1-2 downto 0),
be => pcp_byteenable,
din => pcp_writedata,
dout => outABuf2Rx_s.pcp,
--dpr interface (from PCP/AP to DPR)
dprAddrOff => dprABuf2Rx_s.pcp.addrOff,
dprDin => dprABuf2Rx_s.pcp.din,
dprDout => dprOut.pcp,
dprBe => dprABuf2Rx_s.pcp.be,
dprWr => dprABuf2Rx_s.pcp.wr
);
theAsyncBuf2Rx4Ap : entity work.pdiSimpleReg
generic map (
iAddrWidth_g => extLog2MaxOneSpan-2,
iBaseMap2_g => intABuf2Rx_c.base/4,
iDprAddrWidth_g => dprABuf2Rx_s.ap.addr'length
)
port map (
--memory mapped interface
sel => selABuf2Rx_s.ap,
wr => ap_write,
rd => ap_read,
addr => ap_address(extLog2MaxOneSpan-1-2 downto 0),
be => ap_byteenable,
din => ap_writedata,
dout => outABuf2Rx_s.ap,
--dpr interface (from PCP/AP to DPR)
dprAddrOff => dprABuf2Rx_s.ap.addrOff,
dprDin => dprABuf2Rx_s.ap.din,
dprDout => dprOut.ap,
dprBe => dprABuf2Rx_s.ap.be,
dprWr => dprABuf2Rx_s.ap.wr
);
end generate;
------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------
--TPDO buffer
theTpdoTrippleBuffer : block
signal selVBufPcpOneHot : std_logic_vector(2 downto 0);
signal selVBufApOneHot : std_logic_vector(2 downto 0);
begin
vBufSel_s.pcp(31 downto 24) <= x"00" when selVBufPcpOneHot = "001" else
x"11" when selVBufPcpOneHot = "010" else
x"22" when selVBufPcpOneHot = "100" else
x"FF";
vBufSel_s.ap(31 downto 24) <= x"00" when selVBufApOneHot = "001" else
x"11" when selVBufApOneHot = "010" else
x"22" when selVBufApOneHot = "100" else
x"FF";
dprTpdoBuf_s.pcp.din <= pcp_writedata;
outTpdoBuf_s.pcp <= dprOut.pcp;
dprTpdoBuf_s.pcp.be <= pcp_byteenable;
dprTpdoBuf_s.pcp.wr <= pcp_write;
dprTpdoBuf_s.ap.din <= ap_writedata;
outTpdoBuf_s.ap <= dprOut.ap;
dprTpdoBuf_s.ap.be <= ap_byteenable;
dprTpdoBuf_s.ap.wr <= ap_write;
theTrippleMechanism : entity work.tripleVBufLogic
generic map (
genOnePdiClkDomain_g => genOnePdiClkDomain_g,
--base address of virtual buffers in DPR
iVirtualBufferBase_g => intTpdoBuf_c.base/4, --double word!
--size of one virtual buffer in DPR (must be aligned!!!)
iVirtualBufferSize_g => intTpdoBuf_c.span/3/4, --double word!
--out address width
iOutAddrWidth_g => dprTpdoBuf_s.pcp.addr'length,
--in address width
iInAddrWidth_g => extLog2MaxOneSpan-2,
--ap is producer
bApIsProducer => true
)
port map (
pcpClk => pcp_clk,
pcpReset => pcp_reset,
pcpTrigger => vBufTriggerPdo_s.pcp(3),
pcpOutAddrOff => dprTpdoBuf_s.pcp.addrOff,
pcpOutSelVBuf => selVBufPcpOneHot,
apClk => ap_clk,
apReset => ap_reset,
apTrigger => vBufTriggerPdo_s.ap(3),
apOutAddrOff => dprTpdoBuf_s.ap.addrOff,
apOutSelVBuf => selVBufApOneHot
);
end block;
--
------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------
--RPDO0 buffer
theRpdo0TrippleBuffer : block
signal selVBufPcpOneHot : std_logic_vector(2 downto 0);
signal selVBufApOneHot : std_logic_vector(2 downto 0);
begin
vBufSel_s.pcp(7 downto 0) <= x"00" when selVBufPcpOneHot = "001" else
x"11" when selVBufPcpOneHot = "010" else
x"22" when selVBufPcpOneHot = "100" else
x"FF";
vBufSel_s.ap(7 downto 0) <= x"00" when selVBufApOneHot = "001" else
x"11" when selVBufApOneHot = "010" else
x"22" when selVBufApOneHot = "100" else
x"FF";
dprRpdo0Buf_s.pcp.din <= pcp_writedata;
outRpdo0Buf_s.pcp <= dprOut.pcp;
dprRpdo0Buf_s.pcp.be <= pcp_byteenable;
dprRpdo0Buf_s.pcp.wr <= pcp_write;
dprRpdo0Buf_s.ap.din <= ap_writedata;
outRpdo0Buf_s.ap <= dprOut.ap;
dprRpdo0Buf_s.ap.be <= ap_byteenable;
dprRpdo0Buf_s.ap.wr <= ap_write;
theTrippleMechanism : entity work.tripleVBufLogic
generic map (
genOnePdiClkDomain_g => genOnePdiClkDomain_g,
--base address of virtual buffers in DPR
iVirtualBufferBase_g => intRpdo0Buf_c.base/4, --double word!
--size of one virtual buffer in DPR (must be aligned!!!)
iVirtualBufferSize_g => intRpdo0Buf_c.span/3/4, --double word!
--out address width
iOutAddrWidth_g => dprRpdo0Buf_s.pcp.addr'length,
--in address width
iInAddrWidth_g => extLog2MaxOneSpan-2,
--ap is NOT producer
bApIsProducer => false
)
port map (
pcpClk => pcp_clk,
pcpReset => pcp_reset,
pcpTrigger => vBufTriggerPdo_s.pcp(0),
pcpOutAddrOff => dprRpdo0Buf_s.pcp.addrOff,
pcpOutSelVBuf => selVBufPcpOneHot,
apClk => ap_clk,
apReset => ap_reset,
apTrigger => vBufTriggerPdo_s.ap(0),
apOutAddrOff => dprRpdo0Buf_s.ap.addrOff,
apOutSelVBuf => selVBufApOneHot
);
end block;
--
------------------------------------------------------------------------------------------------------------------------
genRpdo1 : if iRpdos_g >= 2 generate
------------------------------------------------------------------------------------------------------------------------
--RPDO1 buffer
theRpdo1TrippleBuffer : block
signal selVBufPcpOneHot : std_logic_vector(2 downto 0);
signal selVBufApOneHot : std_logic_vector(2 downto 0);
begin
vBufSel_s.pcp(15 downto 8) <= x"00" when selVBufPcpOneHot = "001" else
x"11" when selVBufPcpOneHot = "010" else
x"22" when selVBufPcpOneHot = "100" else
x"FF";
vBufSel_s.ap(15 downto 8) <= x"00" when selVBufApOneHot = "001" else
x"11" when selVBufApOneHot = "010" else
x"22" when selVBufApOneHot = "100" else
x"FF";
dprRpdo1Buf_s.pcp.din <= pcp_writedata;
outRpdo1Buf_s.pcp <= dprOut.pcp;
dprRpdo1Buf_s.pcp.be <= pcp_byteenable;
dprRpdo1Buf_s.pcp.wr <= pcp_write;
dprRpdo1Buf_s.ap.din <= ap_writedata;
outRpdo1Buf_s.ap <= dprOut.ap;
dprRpdo1Buf_s.ap.be <= ap_byteenable;
dprRpdo1Buf_s.ap.wr <= ap_write;
theTrippleMechanism : entity work.tripleVBufLogic
generic map (
genOnePdiClkDomain_g => genOnePdiClkDomain_g,
--base address of virtual buffers in DPR
iVirtualBufferBase_g => intRpdo1Buf_c.base/4, --double word!
--size of one virtual buffer in DPR (must be aligned!!!)
iVirtualBufferSize_g => intRpdo1Buf_c.span/3/4, --double word!
--out address width
iOutAddrWidth_g => dprRpdo1Buf_s.pcp.addr'length,
--in address width
iInAddrWidth_g => extLog2MaxOneSpan-2,
--ap is NOT producer
bApIsProducer => false
)
port map (
pcpClk => pcp_clk,
pcpReset => pcp_reset,
pcpTrigger => vBufTriggerPdo_s.pcp(1),
pcpOutAddrOff => dprRpdo1Buf_s.pcp.addrOff,
pcpOutSelVBuf => selVBufPcpOneHot,
apClk => ap_clk,
apReset => ap_reset,
apTrigger => vBufTriggerPdo_s.ap(1),
apOutAddrOff => dprRpdo1Buf_s.ap.addrOff,
apOutSelVBuf => selVBufApOneHot
);
end block;
--
------------------------------------------------------------------------------------------------------------------------
end generate;
genRpdo2 : if iRpdos_g >= 3 generate
------------------------------------------------------------------------------------------------------------------------
--RPDO2 buffer
theRpdo2TrippleBuffer : block
signal selVBufPcpOneHot : std_logic_vector(2 downto 0);
signal selVBufApOneHot : std_logic_vector(2 downto 0);
begin
vBufSel_s.pcp(23 downto 16) <= x"00" when selVBufPcpOneHot = "001" else
x"11" when selVBufPcpOneHot = "010" else
x"22" when selVBufPcpOneHot = "100" else
x"FF";
vBufSel_s.ap(23 downto 16) <= x"00" when selVBufApOneHot = "001" else
x"11" when selVBufApOneHot = "010" else
x"22" when selVBufApOneHot = "100" else
x"FF";
dprRpdo2Buf_s.pcp.din <= pcp_writedata;
outRpdo2Buf_s.pcp <= dprOut.pcp;
dprRpdo2Buf_s.pcp.be <= pcp_byteenable;
dprRpdo2Buf_s.pcp.wr <= pcp_write;
dprRpdo2Buf_s.ap.din <= ap_writedata;
outRpdo2Buf_s.ap <= dprOut.ap;
dprRpdo2Buf_s.ap.be <= ap_byteenable;
dprRpdo2Buf_s.ap.wr <= ap_write;
theTrippleMechanism : entity work.tripleVBufLogic
generic map (
genOnePdiClkDomain_g => genOnePdiClkDomain_g,
--base address of virtual buffers in DPR
iVirtualBufferBase_g => intRpdo2Buf_c.base/4, --double word!
--size of one virtual buffer in DPR (must be aligned!!!)
iVirtualBufferSize_g => intRpdo2Buf_c.span/3/4, --double word!
--out address width
iOutAddrWidth_g => dprRpdo2Buf_s.pcp.addr'length,
--in address width
iInAddrWidth_g => extLog2MaxOneSpan-2,
--ap is NOT producer
bApIsProducer => false
)
port map (
pcpClk => pcp_clk,
pcpReset => pcp_reset,
pcpTrigger => vBufTriggerPdo_s.pcp(2),
pcpOutAddrOff => dprRpdo2Buf_s.pcp.addrOff,
pcpOutSelVBuf => selVBufPcpOneHot,
apClk => ap_clk,
apReset => ap_reset,
apTrigger => vBufTriggerPdo_s.ap(2),
apOutAddrOff => dprRpdo2Buf_s.ap.addrOff,
apOutSelVBuf => selVBufApOneHot
);
end block;
--
------------------------------------------------------------------------------------------------------------------------
end generate;
------------------------------------------------------------------------------------------------------------------------
-- waitrequest signals
theWaitrequestGenerators : block
signal pcp_wr, pcp_rd, pcp_rd_ack, pcp_wr_ack : std_logic;
signal ap_wr, ap_rd, ap_rd_ack, ap_wr_ack : std_logic;
begin
-- PCP
thePcpWrWaitReqAckGen : entity work.req_ack
generic map (
zero_delay_g => true
)
port map (
clk => pcp_clk,
rst => pcp_reset,
enable => pcp_wr,
ack => pcp_wr_ack
);
thePcpRdWaitReqAckGen : entity work.req_ack
generic map (
ack_delay_g => 2,
zero_delay_g => false
)
port map (
clk => pcp_clk,
rst => pcp_reset,
enable => pcp_rd,
ack => pcp_rd_ack
);
pcp_wr <= pcp_chipselect and pcp_write;
pcp_rd <= pcp_chipselect and pcp_read;
pcp_waitrequest <= not(pcp_rd_ack or pcp_wr_ack);
-- AP
theApWrWaitReqAckGen : entity work.req_ack
generic map (
zero_delay_g => true
)
port map (
clk => ap_clk,
rst => ap_reset,
enable => ap_wr,
ack => ap_wr_ack
);
theApRdWaitReqAckGen : entity work.req_ack
generic map (
ack_delay_g => 2,
zero_delay_g => false
)
port map (
clk => ap_clk,
rst => ap_reset,
enable => ap_rd,
ack => ap_rd_ack
);
ap_wr <= ap_chipselect and ap_write;
ap_rd <= ap_chipselect and ap_read;
ap_waitrequest <= not(ap_rd_ack or ap_wr_ack);
end block;
--
------------------------------------------------------------------------------------------------------------------------
end architecture rtl;
| gpl-2.0 | 5da2998db0013a4cdc719b4d450e4131 | 0.565512 | 3.150498 | false | false | false | false |
JuanMarcosRamirez/WeightedMedianDisenoLogico | misc/FPGA/tope_TestBench.vhd | 2 | 4,769 | --------------------------------------------------------------------------
--Autor: Jorge Márquez
--
-- Este banco de prueba lee los datos
-- seriales de un archivo de texto y
-- los introduce en la entrada rx_female del módulo de recepción
--
-- Este código se encuentra también en la sección de
-- Apéndices del informe de trabajo de grado PROCESAMIENTO DE IMÁGENES DE
-- ANGIOGRAFÍA BIPLANA USANDO UNA TARJETA DE DESARROLLO SPARTAN-3E
--
-- UNIVERSIDAD DE LOS ANDES
-- FACULTAD DE INGENIERÍA
-- ESCUELA DE INGENIERÍA ELÉCTRICA
--
-- Mérida, Septiembre, 2008
--
---------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use std.textio.all;
entity tope_tb is
end tope_tb;
architecture TB_ARCHITECTURE of tope_tb is
component tope_rof512_uart
Port ( tx_female : out std_logic;
rx_female : in std_logic;
LED : out std_logic_vector(7 downto 0);
RSTn : in std_logic;
clk : in std_logic);
end component;
signal tx_female : std_logic:= '0';
signal rx_female : std_logic:= '0';
signal LED : std_logic_vector(7 downto 0) := "00000000";
signal RSTn : std_logic:= '0';
signal clk : std_logic:= '0';
signal TT : std_logic:= '0';
signal byteindata: std_logic_vector(7 downto 0) := "00000000";
begin
UUT : tope_rof512_uart
port map
(clk => clk,
RSTn => RSTn,
LED => LED,
rx_female => rx_female,
tx_female => tx_female );
rx_female <= byteindata(0);
read_from_file: process(TT)
variable indata_line: line;
variable indata: integer;
file input_data_file: text open read_mode is "C:\MATLAB701\work\lena512_syp_inicializ.ser";
begin
if rising_edge(TT) or falling_edge(TT) then
readline(input_data_file,indata_line);
read(indata_line,indata);
byteindata <= conv_std_logic_vector(indata,8);
if endfile(input_data_file) then
report "Finaliza el archivo -- se vuelve a leer desde el principio...";
file_close(input_data_file);
file_open(input_data_file,"C:\MATLAB701\work\lena512_syp_inicializ.ser");
end if;
end if;
end process;
clock_gen: process --reloj
begin --reloj
Clk <= '0'; --reloj
wait for 10 ns; --reloj
Clk <= '1'; --reloj
wait for 10 ns; --reloj
end process; --reloj
TT_gen: process --patron de transmisión (8680=~1/115200)
begin --patron de transmisión (8680=~1/115200)
TT <= '0'; --patron de transmisión (8680=~1/115200)
wait for 8680 ns; --patron de transmisión (8680=~1/115200)
TT <= '1'; --patron de transmisión (8680=~1/115200)
wait for 8680 ns; --patron de transmisión (8680=~1/115200)
end process;
reset_gen: process --reset
begin --reset
RSTn <= '0'; --reset
wait for 20 ns; --reset
RSTn <= '1'; --reset
wait; --reset
end process; --reset
end TB_ARCHITECTURE;
configuration TESTBENCH_FOR_tope_rof512_uart of tope_tb is
for TB_ARCHITECTURE
for UUT : tope_rof512_uart
use entity work.tope_rof512_uart(comportamiento);
end for;
end for;
end TESTBENCH_FOR_tope_rof512_uart;
| gpl-3.0 | 512bb2333524f1ab79225e8d5f3fbc0a | 0.410778 | 4.246661 | false | false | false | false |
DougFirErickson/parallella-hw | fpga/ip/xilinx/fifo_async_103x32/fifo_generator_v12_0/hdl/fifo_generator_v12_0_pkg.vhd | 6 | 138,388 | `protect begin_protected
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 100704)
`protect data_block
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| gpl-3.0 | cf7cda304425fd40a48c95e5982dcdd5 | 0.953912 | 1.812856 | false | false | false | false |
estadofinito/biblioteca-vhdl | todos-los-archivos/servo_pwm_contador_clk64kHz_tb.vhd | 2 | 1,339 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY servo_pwm_contador_clk64kHz_tb IS
END servo_pwm_contador_clk64kHz_tb;
ARCHITECTURE behavior OF servo_pwm_contador_clk64kHz_tb IS
-- Unidad bajo prueba.
COMPONENT servo_pwm_contador_clk64kHz
PORT(
clk : IN std_logic;
reset : IN std_logic;
cnt_up: IN std_logic;
cnt_dn: IN std_logic;
servo : OUT std_logic
);
END COMPONENT;
-- Entradas.
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal cnt_up : std_logic := '0';
signal cnt_dn : std_logic := '0';
-- Salidas.
signal servo : std_logic;
-- Definición del reloj.
constant clk_period : time := 10 ns;
BEGIN
-- Instancia de la unidad bajo prueba.
uut: servo_pwm_contador_clk64kHz PORT MAP (
clk => clk,
reset => reset,
cnt_up => cnt_up,
cnt_dn => cnt_dn,
servo => servo
);
-- Definición del proceso de reloj.
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Procesamiento de estímulos.
proceso_estimulos: process begin
-- Crear condición de reset.
reset <= '1';
wait for 50 ns;
reset <= '0';
-- Esperar poco menos de dos ciclos.
wait for 39 ms;
-- Crear el estímulo.
cnt_up <= '1';
wait for 15 us; -- Tiempo a editar.
--cnt_up <= '0';
wait;
end process;
END; | lgpl-2.1 | 1c1b96d5c67e62f032a587d9c1556559 | 0.64003 | 2.738241 | false | false | false | false |
dummylink/plnk_fpga-stack | Examples/xilinx_microblaze/avnet_lx9/pcores/plb_powerlink_v1_00_a/hdl/vhdl/OpenMAC_cmp.vhd | 5 | 4,720 | -------------------------------------------------------------------------------
--
-- Title : openMAC_cmp
-- Design : plk_mn
--
-------------------------------------------------------------------------------
--
-- File : OpenMAC_cmp.vhd
-- Generated : Wed Jul 27 10:52:27 2011
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2011
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- 2011-07-26 V0.01 zelenkaj First version
-- 2012-01-11 V0.02 mairt moved registers to seperate cmp int and tog int
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity openMAC_cmp is
generic(
mac_time_width_g : integer := 32;
gen2ndCmpTimer_g : boolean := false
);
port(
clk : in std_logic;
rst : in std_logic;
wr : in std_logic;
addr : in std_logic_vector(1 downto 0);
din : in std_logic_vector(31 downto 0);
dout : out std_logic_vector(31 downto 0);
mac_time : in std_logic_vector(mac_time_width_g-1 downto 0);
irq : out std_logic;
toggle : out std_logic
);
end openMAC_cmp;
architecture rtl of openMAC_cmp is
signal cmp_enable, tog_enable : std_logic;
signal cmp_value, tog_value : std_logic_vector(mac_time'range);
signal irq_s, toggle_s : std_logic;
begin
irq <= irq_s;
toggle <= toggle_s;
process(clk, rst)
begin
if rst = '1' then
cmp_enable <= '0'; cmp_value <= (others => '0'); irq_s <= '0';
if gen2ndCmpTimer_g = TRUE then
tog_enable <= '0'; tog_value <= (others => '0'); toggle_s <= '0';
end if;
elsif clk = '1' and clk'event then
--cmp
if cmp_enable = '1' and mac_time = cmp_value then
irq_s <= '1';
end if;
--tog
if tog_enable = '1' and mac_time = tog_value and gen2ndCmpTimer_g = TRUE then
toggle_s <= not toggle_s;
end if;
--memory mapping
if wr = '1' then
case addr is
when "00" =>
cmp_value <= din;
irq_s <= '0';
when "01" =>
cmp_enable <= din(0);
when "10" =>
if gen2ndCmpTimer_g = TRUE then
tog_value <= din;
end if;
when "11" =>
if gen2ndCmpTimer_g = TRUE then
tog_enable <= din(0);
end if;
when others =>
--go and get a coffee...
end case;
end if;
end if;
end process;
dout <=
mac_time when addr = "00" else
x"000000" & "00" & "00" & "00" & irq_s & cmp_enable when addr = "01" else
tog_value when addr = "10" and gen2ndCmpTimer_g = TRUE else
x"000000" & "00" & "00" & "00" & toggle_s & tog_enable when addr = "11" and gen2ndCmpTimer_g = TRUE else
mac_time; --otherwise give me the current time...
end rtl;
| gpl-2.0 | c7b79ead42c97f6f622952765b7c7302 | 0.561653 | 3.567649 | false | false | false | false |
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| gpl-3.0 | 1e89c088e62d002f513595c67b3f4694 | 0.942762 | 1.838637 | false | false | false | false |
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| gpl-3.0 | 7bdcd2bd35d04c20e9fb6fbde9c54a47 | 0.944251 | 1.836292 | false | false | false | false |
rflamino/StellaBlue | core/A6500/src/A6502.vhd | 1 | 1,791 | -- A6500 - 6502 CPU and variants
-- Copyright 2006, 2010 Retromaster
--
-- This file is part of A2601.
--
-- A2601 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License,
-- or any later version.
--
-- A2601 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with A2601. If not, see <http://www.gnu.org/licenses/>.
library ieee;
use ieee.std_logic_1164.all;
use work.types.all;
entity A6502 is
port(clk: in std_logic;
rst: in std_logic;
irq: in std_logic;
nmi: in std_logic;
rdy: in std_logic;
d: inout std_logic_vector(7 downto 0);
ad: out std_logic_vector(15 downto 0);
r: out std_logic);
end A6502;
architecture arch of A6502 is
component A6500 is
port(clk: in std_logic;
rst: in std_logic;
irq: in std_logic;
nmi: in std_logic;
stop: in std_logic;
de: in std_logic;
d: inout std_logic_vector(7 downto 0);
ad: out std_logic_vector(15 downto 0);
r: out std_logic);
end component;
signal stop: std_logic;
signal r_i: std_logic;
signal de: std_logic;
begin
r <= r_i;
stop <= '1' when
(rdy = '0' and r_i = '1')
else '0';
de <= not r_i;
cpu_A6500: A6500
port map(clk, rst, irq, nmi, stop, de, d, ad, r_i);
end arch;
| mit | eeeb675cd1286638e0903d95794066b0 | 0.600782 | 3.491228 | false | false | false | false |
hgunicamp/Mips8B | src_test/tests/simulacoes/test_Mips_Processor-sh.vhdl | 1 | 5,440 | -- Teste geral para a estrutura do Processador Mips8B
Library Ieee;
Use Ieee.Std_Logic_1164.all;
Use Ieee.Numeric_Std.all;
Entity test_processor is
End Entity test_processor;
Architecture test_general of test_processor is
Component Mips8B is
Port(Reset_n: In Std_Logic;
Clock: In Std_Logic;
MAddr: Out Std_Logic_Vector(7 downto 0);
MCmd: Out Std_Logic_Vector(1 downto 0);
MData: Out Std_Logic_Vector(7 downto 0);
SData: In Std_Logic_Vector(7 downto 0);
SCmdAccept: In Std_Logic);
End Component Mips8B;
Type Memory_Array is Array(Natural Range <>) of Std_Logic_Vector(7 downto 0);
Use Work.MIPS8B_Base.ocpIDLE_little;
Use Work.MIPS8B_Base.ocpWR_little;
Use Work.MIPS8B_Base.ocpRD_little;
Use Work.MIPS8B_Base.ocpNULL_little;
Use Work.MIPS8B_Base.ocpDVA_little;
Signal Reset_n: Std_Logic;
Signal Clock: Std_Logic := '0';
Signal Clock_Mem: Std_Logic := '0';
Signal MAddr: Std_Logic_Vector(7 downto 0);
Signal MCmd: Std_Logic_Vector(1 downto 0);
Signal MData: Std_Logic_Vector(7 downto 0);
Signal SData: Std_Logic_Vector(7 downto 0);
Signal SCmdAccept: Std_Logic;
Begin
Reset_n <= '1', '0' after 20 ns, '1' after 40 ns;
Clock <= not Clock after 10 ns;
Clock_Mem <= not Clock_Mem after 15 ns;
Memory: Process
Variable int_SCmdAccept: Std_Logic;
Variable address: Unsigned(7 downto 0);
Variable mem_int: Memory_Array(0 to 255) := (
"00100000", "00000001", "00000000", "10000000",
"00100000", "00000010", "00000000", "10110100",
"00100000", "00000011", "00000000", "01111111",
"00100000", "00000100", "00000000", "11111111",
"00100000", "00000101", "00000000", "00110101",
"00100000", "00000110", "00000000", "01000000",
"00100000", "00000111", "00000000", "01001000",
"01000000", "00100111", "00000000", "01100010",
"01000000", "01100110", "00000000", "01000100",
"01000000", "11000101", "00000000", "00000111",
"01000000", "11100100", "00000000", "01100001",
"01000000", "11100100", "00000000", "01000001",
"01000000", "11000011", "00000000", "00000010",
"01000000", "10100010", "00000000", "01100011",
"01000000", "10000001", "00000000", "00000101",
"01000000", "00100000", "00000000", "01100010",
"01000000", "01100000", "00000000", "01000100",
"01000000", "10100000", "00000000", "00000110",
"01000000", "00000000", "00000000", "01100000",
"01000000", "00100000", "00000000", "01000001",
"01000000", "11100000", "00000000", "00000111",
"01000000", "00100111", "00000000", "01100000",
"01000000", "01000110", "00000000", "01000000",
"01000000", "01100101", "00000000", "00000000",
"01000000", "11100100", "00000000", "01100000",
"01000000", "10000011", "00000000", "01000000",
"01000000", "10100010", "00000000", "00000000",
"01000000", "11000001", "00000000", "01100000",
"01000000", "11100111", "00000000", "01100001",
"01000000", "11000110", "00000000", "01000010",
"01000000", "10100101", "00000000", "00000011",
"01000000", "10000100", "00000000", "01100111",
"01000000", "01100011", "00000000", "01000100",
"01000000", "01000010", "00000000", "00000101",
"01000000", "00100001", "00000000", "01100110",
"01000000", "11100111", "00000000", "01100000",
"01000000", "11000110", "00000000", "01000000",
"01000000", "10100101", "00000000", "00000000",
"01000000", "10000100", "00000000", "01100000",
"01000000", "01100011", "00000000", "01000000",
"01000000", "01000010", "00000000", "00000000",
"01000000", "00100001", "00000000", "01100000",
Others => "00000000");
Begin
Wait Until Clock_Mem'Event and Clock_Mem='1';
Case MCmd is
When ocpWR_little =>
If int_SCmdAccept = ocpNULL_little then
int_SCmdAccept := ocpDVA_little;
address := Unsigned(MAddr);
mem_int(to_integer(address)) := MData;
Else
int_SCmdAccept := ocpNULL_little;
End If;
SData <= "ZZZZZZZZ";
When ocpRD_little =>
If int_SCmdAccept = ocpNULL_little then
int_SCmdAccept := ocpDVA_little;
address := Unsigned(MAddr);
SData <= mem_int(to_integer(address));
Else
int_SCmdAccept := ocpNULL_little;
End If;
When Others =>
int_SCmdAccept := ocpNULL_little;
SData <= "ZZZZZZZZ";
End Case;
SCmdAccept <= int_SCmdAccept;
End Process Memory;
DUV: Mips8B
Port Map( Reset_n => Reset_n,
Clock => Clock,
MAddr => MAddr,
MCmd => MCmd,
MData => MData,
SData => SData,
SCmdAccept => SCmdAccept);
End Architecture test_general;
Configuration general_test of test_processor is
For test_general
For DUV: Mips8B Use Configuration Work.Mips8B_struct_conf;
End For;
End For;
End Configuration general_test;
| unlicense | 912a1d1ae15a89786337791ff9050c95 | 0.56636 | 3.869132 | false | true | false | false |
dummylink/plnk_fpga-stack | Examples/xilinx_microblaze/avnet_lx9/pcores/plb_powerlink_v1_00_a/hdl/vhdl/OpenMAC_DMAFifo_Xilinx.vhd | 2 | 6,786 | -------------------------------------------------------------------------------
--
-- Title : OpenMAC_DMAFifo_Xilinx
-- Design : POWERLINK
--
-------------------------------------------------------------------------------
--
-- File : C:\git\VHDL_IP-Cores\active_hdl\compile\OpenMAC_DMAFifo_Xilinx.vhd
-- Generated : Thu Nov 24 15:08:50 2011
-- From : C:\git\VHDL_IP-Cores\active_hdl\src\OpenMAC_DMAFifo_Xilinx.bde
-- By : Bde2Vhdl ver. 2.6
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2011
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
-- Design unit header --
--
-- This is the toplevel file of the dual clocked DMA FIFO
-- for Xilinx FPGAs.
--
-------------------------------------------------------------------------------
--
-- 2011-10-13 V0.01 mairt First version
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity openMAC_DMAfifo is
generic(
fifo_data_width_g : NATURAL := 16;
fifo_word_size_g : NATURAL := 32;
fifo_word_size_log2_g : NATURAL := 5
);
port(
aclr : in std_logic;
rd_clk : in std_logic;
rd_req : in std_logic;
wr_clk : in std_logic;
wr_req : in std_logic;
wr_data : in std_logic_vector(fifo_data_width_g - 1 downto 0);
rd_empty : out std_logic;
rd_full : out std_logic;
wr_empty : out std_logic;
wr_full : out std_logic;
rd_data : out std_logic_vector(fifo_data_width_g - 1 downto 0);
rd_usedw : out std_logic_vector(fifo_word_size_log2_g - 1 downto 0);
wr_usedw : out std_logic_vector(fifo_word_size_log2_g - 1 downto 0)
);
end openMAC_DMAfifo;
architecture struct of openMAC_DMAfifo is
---- Component declarations -----
component async_fifo_ctrl
generic(
ADDR_WIDTH : natural := 5
);
port (
clkr : in std_logic;
clkw : in std_logic;
rd : in std_logic;
resetr : in std_logic;
resetw : in std_logic;
wr : in std_logic;
r_addr : out std_logic_vector(ADDR_WIDTH-1 downto 0);
r_empty : out std_logic;
r_full : out std_logic;
rd_used_w : out std_logic_vector(ADDR_WIDTH-1 downto 0);
w_addr : out std_logic_vector(ADDR_WIDTH-1 downto 0);
w_empty : out std_logic;
w_full : out std_logic;
wd_used_w : out std_logic_vector(ADDR_WIDTH-1 downto 0)
);
end component;
component dc_dpr
generic(
ADDRWIDTH : integer := 7;
SIZE : integer := 128;
WIDTH : integer := 16
);
port (
addrA : in std_logic_vector(ADDRWIDTH-1 downto 0);
addrB : in std_logic_vector(ADDRWIDTH-1 downto 0);
clkA : in std_logic;
clkB : in std_logic;
diA : in std_logic_vector(WIDTH-1 downto 0);
diB : in std_logic_vector(WIDTH-1 downto 0);
enA : in std_logic;
enB : in std_logic;
weA : in std_logic;
weB : in std_logic;
doA : out std_logic_vector(WIDTH-1 downto 0);
doB : out std_logic_vector(WIDTH-1 downto 0)
);
end component;
---- Signal declarations used on the diagram ----
signal enA : std_logic;
signal enB : std_logic;
signal wea : std_logic;
signal weB : std_logic;
signal wr_full_s : std_logic;
signal diB : std_logic_vector (fifo_data_width_g-1 downto 0);
signal rd_addr : std_logic_vector (fifo_word_size_log2_g-1 downto 0);
signal wr_addr : std_logic_vector (fifo_word_size_log2_g-1 downto 0);
begin
---- User Signal Assignments ----
--assignments
---port a writes only
enA <= wea;
---port b reads only
enB <= rd_req;
weB <= '0';
diB <= (others => '0');
---- Component instantiations ----
THE_FIFO_CONTROL : async_fifo_ctrl
generic map (
ADDR_WIDTH => fifo_word_size_log2_g
)
port map(
clkr => rd_clk,
clkw => wr_clk,
r_addr => rd_addr( fifo_word_size_log2_g-1 downto 0 ),
r_empty => rd_empty,
r_full => rd_full,
rd => rd_req,
rd_used_w => rd_usedw( fifo_word_size_log2_g - 1 downto 0 ),
resetr => aclr,
resetw => aclr,
w_addr => wr_addr( fifo_word_size_log2_g-1 downto 0 ),
w_empty => wr_empty,
w_full => wr_full_s,
wd_used_w => wr_usedw( fifo_word_size_log2_g - 1 downto 0 ),
wr => wr_req
);
THE_FIFO_DPR : dc_dpr
generic map (
ADDRWIDTH => fifo_word_size_log2_g,
SIZE => fifo_word_size_g,
WIDTH => fifo_data_width_g
)
port map(
addrA => wr_addr( fifo_word_size_log2_g-1 downto 0 ),
addrB => rd_addr( fifo_word_size_log2_g-1 downto 0 ),
clkA => wr_clk,
clkB => rd_clk,
diA => wr_data( fifo_data_width_g - 1 downto 0 ),
diB => diB( fifo_data_width_g-1 downto 0 ),
doB => rd_data( fifo_data_width_g - 1 downto 0 ),
enA => enA,
enB => enB,
weA => wea,
weB => weB
);
wea <= not(wr_full_s) and wr_req;
---- Terminal assignment ----
-- Output\buffer terminals
wr_full <= wr_full_s;
end struct;
| gpl-2.0 | c56a3163e3eb08f512ade41149b129ad | 0.578102 | 3.605739 | false | false | false | false |
JuanMarcosRamirez/WeightedMedianDisenoLogico | misc/FPGA/FIFO 512x8/fifo_512x8x/fifo_512x8x_cambiado.vhd | 2 | 5,488 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2007 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file fifo_512x8x.vhd when simulating
-- the core, fifo_512x8x. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY fifo_512x8x IS
port (
din: IN std_logic_VECTOR(7 downto 0);
rd_clk: IN std_logic;
rd_en: IN std_logic;
ainit: IN std_logic;
wr_clk: IN std_logic;
wr_en: IN std_logic;
dout: OUT std_logic_VECTOR(7 downto 0);
empty: OUT std_logic;
full: OUT std_logic;
wr_count: OUT std_logic_VECTOR(8 downto 0));
END fifo_512x8x;
ARCHITECTURE fifo_512x8x_a OF fifo_512x8x IS
-- synthesis translate_off
component wrapped_fifo_512x8x
port (
din: IN std_logic_VECTOR(7 downto 0);
rd_clk: IN std_logic;
rd_en: IN std_logic;
rst: IN std_logic;
wr_clk: IN std_logic;
wr_en: IN std_logic;
dout: OUT std_logic_VECTOR(7 downto 0);
empty: OUT std_logic;
full: OUT std_logic;
wr_data_count: OUT std_logic_VECTOR(8 downto 0));
end component;
-- Configuration specification
for all : wrapped_fifo_512x8x use entity XilinxCoreLib.fifo_generator_v3_3(behavioral)
generic map(
c_rd_freq => 100,
c_wr_response_latency => 1,
c_has_srst => 0,
c_has_rd_data_count => 0,
c_din_width => 8,
c_has_wr_data_count => 1,
c_implementation_type => 2,
c_family => "spartan3",
c_has_wr_rst => 0,
c_wr_freq => 100,
c_underflow_low => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_preload_latency => 1,
c_dout_width => 8,
c_rd_depth => 512,
c_default_value => "BlankString",
c_mif_file_name => "BlankString",
c_has_underflow => 0,
c_has_rd_rst => 0,
c_has_almost_full => 0,
c_has_rst => 1,
c_data_count_width => 9,
c_has_wr_ack => 0,
c_use_ecc => 0,
c_wr_ack_low => 0,
c_common_clock => 0,
c_rd_pntr_width => 9,
c_has_almost_empty => 0,
c_rd_data_count_width => 9,
c_enable_rlocs => 0,
c_wr_pntr_width => 9,
c_overflow_low => 0,
c_prog_empty_type => 0,
c_optimization_mode => 0,
c_wr_data_count_width => 9,
c_preload_regs => 0,
c_dout_rst_val => "0",
c_has_data_count => 0,
c_prog_full_thresh_negate_val => 509,
c_wr_depth => 512,
c_prog_empty_thresh_negate_val => 3,
c_prog_empty_thresh_assert_val => 2,
c_has_valid => 0,
c_init_wr_pntr_val => 0,
c_prog_full_thresh_assert_val => 510,
c_use_fifo16_flags => 0,
c_has_backup => 0,
c_valid_low => 0,
c_prim_fifo_type => "2kx9",
c_count_type => 0,
c_prog_full_type => 0,
c_memory_type => 1);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_fifo_512x8x
port map (
din => din,
rd_clk => rd_clk,
rd_en => rd_en,
rst => ainit,
wr_clk => wr_clk,
wr_en => wr_en,
dout => dout,
empty => empty,
full => full,
wr_data_count => wr_count);
-- synthesis translate_on
END fifo_512x8x_a;
| gpl-3.0 | b528f8331ca31b63a7e4d1a024a3d5d9 | 0.563958 | 3.486658 | false | false | false | false |
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| gpl-3.0 | 8035195b71b03ad61baf39a2449a3be7 | 0.949929 | 1.832966 | false | false | false | false |
steveEECSrubin/usc_projects | ABB/check_sum.vhd | 1 | 4,956 | -- simplest check sum
-- receiver
signal have_seen_start_packet: std_logic := '0';
signal current_check_sum : std_logic_vector(7 downto 0);
signal check_sum_error : std_logic := '0';
signal rx_data_counter : std_logic_vector(7 downto 0) := x"00";
attribute keep : string;
attribute keep of check_sum_error : signal is "true";
attribute keep of rx_data_counter : signal is "true";
-- State registers
process (USER_CLK)
begin
--delayed_rx_data_r <= rx_data_r;
if (USER_CLK 'event and USER_CLK = '1') then
if (RESET = '1') then
begin_r <= '1' after DLY;
start_toggling_r <= '0' after DLY;
have_seen_start_packet <= '0';
--check_sum_error <= '0';
else
begin_r <= next_begin_c after DLY;
start_toggling_r <= start_toggling_c after DLY;
end if;
if (RX_CHAR_IS_K_IN = '0') then -- if it is not BC
--if (RX_CHAR_IS_K = '0') then-- if it is not BC
if (have_seen_start_packet = '0') then -- if we have not detected the start of the packet yet
if(RX_DATA = x"0A") then -- if the data is "0A" - it is start of the packet
rx_data_counter <= x"01";
--MGT_FRAME_CHECK_PACKET_RECEIVED <= '0';
have_seen_start_packet <= '1';
current_check_sum <= x"0A";
check_sum_error <= '0';
end if;
else -- if we have seen the start of the packet - we are currently receiving the packet
if (rx_data_counter >= x"01") and (rx_data_counter < x"07") then
rx_data_counter <= rx_data_counter + x"01";
have_seen_start_packet <= '1';
current_check_sum <= current_check_sum xor RX_DATA;
elsif (rx_data_counter = x"07") then -- when the counter reaches B3 - end of packet, calculate the checksum
rx_data_counter <= rx_data_counter + x"01";
if(check_sum_error = '0') and (RX_DATA /= current_check_sum) then
check_sum_error <= '1';
end if;
have_seen_start_packet <= '1';
--MGT_FRAME_CHECK_PACKET_RECEIVED <= '1';
elsif (rx_data_counter >= x"07") and (rx_data_counter < x"BA") then -- keep the current value for some time
rx_data_counter <= rx_data_counter + x"01";
have_seen_start_packet <= '1';
--MGT_FRAME_CHECK_PACKET_RECEIVED <= '1';
else
rx_data_counter <= x"00";
--MGT_FRAME_CHECK_PACKET_RECEIVED <= '0';
have_seen_start_packet <= '0';
end if;
end if;
end if;
end if;
end process;
-- transmitter
signal tx_d_r : std_logic_vector(7 downto 0);
signal counter : integer := 0;
signal current_check_sum : std_logic_vector(7 downto 0);
signal STATE_i : std_logic_vector(3 downto 0);
--____________________________ Data Generation __________________________________
--Transmit data when send_align_r is de-asserted. Data is right shifted every cycle.
process(USER_CLK)
begin
if(USER_CLK'event and USER_CLK = '1') then
if(RESET = '1') then
tx_d_r <= x"BC" after DLY;
counter <= 0;
STATE_i <= x"0";
elsif (send_align_r = '0') then
if (send_align_r='0') then -- if the data is not special character "BC"
case STATE_i is
when x"0" => --wait for about 2 seconds
if(counter < 500000000) then -- wait for 4 seconds
counter <= counter + 1;
tx_d_r <= shift_reg_r & shift_reg_r;
STATE_i <= x"0";
else -- 4 seconds past
counter <= 0;
STATE_i <= x"3";
tx_d_r <= shift_reg_r & shift_reg_r;
end if;
when x"3" =>
case counter is
when 0 to 9 => tx_d_r <= shift_reg_r & shift_reg_r; counter <= counter + 1; current_check_sum <= x"00";
when 10 => tx_d_r <= x"0A"; counter <= counter + 1; current_check_sum <= x"00";
--when 11 to 191 => tx_d_r <= tx_d_r + x"01"; counter <= counter + 1; tx_charisk_i <= '0'; current_check_sum <= current_check_sum xor tx_d_r;
when 11 to 16 => tx_d_r <= x"5D"; counter <= counter + 1; current_check_sum <= current_check_sum xor tx_d_r;
when 17 => current_check_sum <= current_check_sum xor tx_d_r; tx_d_r <= current_check_sum xor tx_d_r; counter <= counter + 1;
--when 192 => current_check_sum <= current_check_sum xor tx_d_r; tx_d_r <= x"00"; counter <= counter + 1; tx_charisk_i <= '0'; -- screwed up checsum
when 18 to 27 => tx_d_r <= shift_reg_r & shift_reg_r; counter <= counter + 1;
when others => tx_d_r <= shift_reg_r & shift_reg_r; STATE_i <= x"3"; counter <= 0;
end case;
when others => tx_d_r <= shift_reg_r & shift_reg_r; counter <= 0;
end case;
end if;
end if;
end if;
end process;
| mit | d31ed98cdff4104a28763be98ac0051e | 0.532082 | 3.156688 | false | false | false | false |
DougFirErickson/parallella-hw | fpga/ip/xilinx/memory_dp_48x4096/blk_mem_gen_v8_2/hdl/blk_mem_input_block.vhd | 8 | 45,404 | `protect begin_protected
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 31872)
`protect data_block
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| gpl-3.0 | 0b1aa2b7bbb3f27db7d646c3a44a4d31 | 0.948683 | 1.821113 | false | false | false | false |
dummylink/plnk_fpga-stack | Examples/xilinx_microblaze/avnet_lx9/pcores/plb_powerlink_v1_00_a/hdl/vhdl/OpenHUB.vhd | 5 | 6,692 | ------------------------------------------------------------------------------------------------------------------------
-- OpenHUB
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Note: RxDv, RxDat0 and RxDat1 have to be synchron to CLK
-- ReceivePort return currently active Port
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2009-08-07 V0.01 Converted from V3.1 to first official version.
-- 2011-11-28 V0.02 zelenkaj Changed reset level to high-active
------------------------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
ENTITY OpenHUB IS
GENERIC ( Ports : integer := 3 );
PORT ( Rst : IN std_logic;
Clk : IN std_logic;
RxDv : IN std_logic_vector(Ports DOWNTO 1);
RxDat0, RxDat1 : IN std_logic_vector(Ports DOWNTO 1);
TxEn : OUT std_logic_vector(Ports DOWNTO 1);
TxDat0, TxDat1 : OUT std_logic_vector(Ports DOWNTO 1);
internPort : IN integer RANGE 1 TO Ports := 1;
TransmitMask : IN std_logic_vector(Ports DOWNTO 1) := (OTHERS => '1');
ReceivePort : OUT integer RANGE 0 TO Ports
);
END ENTITY OpenHUB;
ARCHITECTURE struct OF OpenHUB IS
SIGNAL RxDvI, RxDvL : std_logic_vector(Ports DOWNTO 0);
SIGNAL RxDatI0, RxDatL0 : std_logic_vector(Ports DOWNTO 0);
SIGNAL RxDatI1, RxDatL1 : std_logic_vector(Ports DOWNTO 0);
SIGNAL TxEnI : std_logic_vector(Ports DOWNTO 0);
SIGNAL TxDatI0 : std_logic_vector(Ports DOWNTO 0);
SIGNAL TxDatI1 : std_logic_vector(Ports DOWNTO 0);
SIGNAL MasterAtCollNumber : integer RANGE 0 TO Ports;
SIGNAL HubActive : boolean;
SIGNAL CollStatus : boolean;
SIGNAL TransmitMask_L : std_logic_vector(Ports DOWNTO 1);
BEGIN
RxDvI(Ports DOWNTO 0) <= RxDv(Ports DOWNTO 1) & '0';
RxDatI0(Ports DOWNTO 0) <= RxDat0(Ports DOWNTO 1) & '0';
RxDatI1(Ports DOWNTO 0) <= RxDat1(Ports DOWNTO 1) & '0';
TxEn(Ports DOWNTO 1) <= TxEnI(Ports DOWNTO 1);
TxDat0(Ports DOWNTO 1) <= TxDatI0(Ports DOWNTO 1);
TxDat1(Ports DOWNTO 1) <= TxDatI1(Ports DOWNTO 1);
do: PROCESS (Rst, Clk)
VARIABLE Active : boolean;
VARIABLE Master : integer RANGE 0 TO Ports;
VARIABLE Master_at_Coll : integer RANGE 0 TO Ports;
VARIABLE Coll : boolean;
VARIABLE RxDvM : std_logic_vector(Ports DOWNTO 0);
BEGIN
IF Rst = '1' THEN
RxDvL <= (OTHERS => '0'); RxDatL0 <= (OTHERS => '0'); RxDatL1 <= (OTHERS => '0');
TxEnI <= (OTHERS => '0'); TxDatI0 <= (OTHERS => '0'); TxDatI1 <= (OTHERS => '0');
Active := false;
Master := 0;
Master_at_Coll := 0;
Coll := false;
TransmitMask_L <= (OTHERS => '1');
ELSIF rising_edge(Clk) THEN
RxDvL <= RxDvI; RxDatL0 <= RxDatI0; RxDatL1 <= RxDatI1;
IF Active = false THEN
IF RxDvL /= 0 THEN
FOR i IN 1 TO Ports LOOP
IF RxDvL(i) = '1' AND (RxDatL0(i) = '1' OR RxDatL1(i) = '1') THEN
Master := i;
Active := true;
EXIT;
END IF;
END LOOP;
END IF;
ELSE
IF RxDvL(Master) = '0' AND RxDvI(Master) = '0' THEN
Master := 0;
END IF;
IF RxDvL = 0 AND RxDvI = 0 THEN
Active := false;
END IF;
END IF;
IF Master = 0 THEN
TxEnI <= (OTHERS => '0'); TxDatI0 <= (OTHERS => '0'); TxDatI1 <= (OTHERS => '0');
-- Overtake new TransmitMask only, when there is no active frame.
TransmitMask_L <= TransmitMask;
ELSE
FOR i IN 1 TO Ports LOOP -- output received frame to every port
IF i /= Master THEN -- but not to the port where it is coming from - "eh kloar!"
-- only send data to active ports (=> TransmitMask is set to '1') or the internal Port (Mac)
IF TransmitMask_L(i) = '1' OR Master = internPort THEN
TxEnI(i) <= '1';
TxDatI0(i) <= RxDatL0(Master);
TxDatI1(i) <= RxDatL1(Master);
END IF;
-- If there is a frame received and another is sent => collision!
IF RxDvL(i) = '1' THEN
Coll := true;
Master_at_Coll := Master;
END IF;
END IF;
END LOOP;
END IF;
IF Coll = true THEN
TxEnI(Master_at_Coll) <= '1'; TxDatI0(Master_at_Coll) <= '1'; TxDatI1(Master_at_Coll) <= '0';
RxDvM := RxDvL;
RxDvM(Master_at_Coll) := '0';
IF RxDvM = 0 THEN
TxEnI(Master_at_Coll) <= '0'; TxDatI0(Master_at_Coll) <= '0'; TxDatI1(Master_at_Coll) <= '0';
Coll := false;
Master_at_Coll := 0;
END IF;
END IF;
END IF;
HubActive <= Active;
MasterAtCollNumber <= Master_at_Coll;
CollStatus <= Coll;
-- Output the Master Port - identifies the port (1...n) which has received the packet.
-- If Master is 0, the Hub is inactive.
ReceivePort <= Master;
END PROCESS do;
END struct;
| gpl-2.0 | dcb79cf2837902d6af7237237bf74cad | 0.592499 | 3.540741 | false | false | false | false |
dummylink/plnk_fpga-stack | Examples/xilinx_microblaze/avnet_lx9/pcores/plb_powerlink_v1_00_a/hdl/vhdl/openMAC_DMAFifo_Xilinx/fifo_read.vhd | 2 | 5,318 | ------------------------------------------------------------------------------------------------------------------------
-- read controller of the fifo
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Note: A general implementation of a asynchronous fifo which is
-- using a dual port ram. This file is the read controler.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2011-09-22 V0.01 mairt first version
-- 2011-10-14 V0.02 zelenkaj element calculation buggy
------------------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fifo_read_ctrl is
generic(N: natural:=4);
port(
clkr, resetr: in std_logic;
w_ptr_in: in std_logic_vector(N downto 0);
rd: in std_logic;
r_empty: out std_logic;
r_full: out std_logic;
r_ptr_out: out std_logic_vector(N downto 0);
r_addr: out std_logic_vector(N-1 downto 0);
r_elements: out std_logic_vector(N-1 downto 0)
);
end fifo_read_ctrl;
architecture gray_arch of fifo_read_ctrl is
signal r_ptr_reg, r_ptr_next: std_logic_vector(N downto 0);
signal w_ptr_reg, w_ptr_next : std_logic_vector(N downto 0) := (others => '0');
signal gray1, bin, bin1: std_logic_vector(N downto 0);
signal raddr_all: std_logic_vector(N-1 downto 0);
signal raddr_msb,waddr_msb: std_logic;
signal empty_flag, full_flag: std_logic;
signal r_elements_wr, r_elements_rd, r_elements_diff : std_logic_vector(N downto 0);
signal r_elements_reg, r_elements_next : std_logic_vector(N-1 downto 0);
begin
-- register
process(clkr,resetr)
begin
if (resetr='1') then
r_ptr_reg <= (others=>'0');
--w_ptr_reg <= (others => '0');
r_elements_reg <= (others => '0');
elsif (clkr'event and clkr='1') then
r_ptr_reg <= r_ptr_next;
--w_ptr_reg <= w_ptr_next;
r_elements_reg <= r_elements_next;
end if;
end process;
-- (N+1)-bit Gray counter
bin <= r_ptr_reg xor ('0' & bin(N downto 1));
bin1 <= std_logic_vector(unsigned(bin) + 1);
gray1 <= bin1 xor ('0' & bin1(N downto 1));
-- update read pointer
r_ptr_next <= gray1 when rd='1' and empty_flag='0' else
r_ptr_reg;
-- save write pointer
w_ptr_next <= w_ptr_in;
-- N-bit Gray counter
raddr_msb <= r_ptr_reg(N) xor r_ptr_reg(N-1);
raddr_all <= raddr_msb & r_ptr_reg(N-2 downto 0);
waddr_msb <= w_ptr_in(N) xor w_ptr_in(N-1);
-- check for FIFO read empty
empty_flag <=
'1' when w_ptr_in(N)=r_ptr_reg(N) and
w_ptr_in(N-2 downto 0)=r_ptr_reg(N-2 downto 0) and
raddr_msb = waddr_msb else
'0';
-- check for FIFO read full
full_flag <=
'1' when w_ptr_in(N)/=r_ptr_reg(N) and
w_ptr_in(N-2 downto 0)=r_ptr_reg(N-2 downto 0) and
raddr_msb = waddr_msb else
'0';
-- convert gray value to bin and obtain difference
r_elements_wr <= bin;
r_elements_rd <= w_ptr_in xor ('0' & r_elements_rd(N downto 1));
r_elements_diff <= std_logic_vector(unsigned(r_elements_rd) - unsigned(r_elements_wr));
r_elements_next <= r_elements_diff(r_elements_next'range);
-- output
r_addr <= raddr_all;
r_ptr_out <= r_ptr_reg;
r_elements <= r_elements_reg;
r_empty <= empty_flag;
r_full <= full_flag;
end gray_arch; | gpl-2.0 | bb574b12ccf692df4861c415e3990f39 | 0.581986 | 3.566734 | false | false | false | false |
DougFirErickson/parallella-hw | fpga/ip/xilinx/memory_dp_48x4096/blk_mem_gen_v8_2/hdl/blk_mem_gen_generic_cstr.vhd | 8 | 136,876 | `protect begin_protected
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`protect end_protected
| gpl-3.0 | 5a5ff5a8501005f54d26bdcbf5b8c134 | 0.953177 | 1.812255 | false | false | false | false |
JuanMarcosRamirez/WeightedMedianDisenoLogico | misc/FPGA/otros/auditoría_imagen_16x16/sort_3x3x.vhd | 1 | 21,250 | library IEEE;
use IEEE.std_logic_1164.all;
entity sort_3x3 is
generic (
vwidth: integer:=8
);
port (
Clk : in std_logic;
RSTn : in std_logic;
w11 : in std_logic_vector((vwidth -1) downto 0);
w12 : in std_logic_vector((vwidth-1) downto 0);
w13 : in std_logic_vector((vwidth -1) downto 0);
w21 : in std_logic_vector((vwidth -1) downto 0);
w22 : in std_logic_vector((vwidth -1) downto 0);
w23 : in std_logic_vector((vwidth -1) downto 0);
w31 : in std_logic_vector((vwidth-1) downto 0);
w32 : in std_logic_vector((vwidth -1) downto 0);
w33 : in std_logic_vector((vwidth -1) downto 0);
DVw : in std_logic;
DVs : out std_logic;
s1 : out std_logic_vector(vwidth -1 downto 0);
s2 : out std_logic_vector(vwidth-1 downto 0);
s3 : out std_logic_vector(vwidth -1 downto 0);
s4 : out std_logic_vector(vwidth -1 downto 0);
s5 : out std_logic_vector(vwidth -1 downto 0);
s6 : out std_logic_vector(vwidth -1 downto 0);
s7 : out std_logic_vector(vwidth -1 downto 0);
s8 : out std_logic_vector(vwidth -1 downto 0);
s9 : out std_logic_vector(vwidth -1 downto 0)
);
end sort_3x3;
architecture sort_3x3 of sort_3x3 is
-- Nivel 1
signal c11_L: std_logic_vector((vwidth -1) downto 0); -- Comp Nivel 1
signal c11_H: std_logic_vector((vwidth-1) downto 0); -- Comp Nivel 1
signal c12_L: std_logic_vector((vwidth -1) downto 0); -- Comp Nivel 1
signal c12_H: std_logic_vector((vwidth -1) downto 0); -- Comp Nivel 1
signal c13_L: std_logic_vector((vwidth -1) downto 0); -- Comp Nivel 1
signal c13_H: std_logic_vector((vwidth -1) downto 0); -- Comp Nivel 1
signal c14_L: std_logic_vector((vwidth -1) downto 0); -- Comp Nivel 1
signal c14_H: std_logic_vector((vwidth -1) downto 0); -- Comp Nivel 1
signal r11: std_logic_vector((vwidth -1) downto 0);
-- Nivel 2
signal c21_L: std_logic_vector((vwidth -1) downto 0); -- Comp Nivel 2
signal c21_H: std_logic_vector((vwidth-1) downto 0); -- Comp Nivel 2
signal c22_L: std_logic_vector((vwidth -1) downto 0); -- Comp Nivel 2
signal c22_H: std_logic_vector((vwidth -1) downto 0); -- Comp Nivel 2
signal c23_L: std_logic_vector((vwidth -1) downto 0); -- Comp Nivel 2
signal c23_H: std_logic_vector((vwidth -1) downto 0); -- Comp Nivel 2
signal c24_L: std_logic_vector((vwidth -1) downto 0); -- Comp Nivel 2
signal c24_H: std_logic_vector((vwidth -1) downto 0); -- Comp Nivel 2
signal r21: std_logic_vector((vwidth -1) downto 0);
-- Nivel 3
signal c31_L: std_logic_vector((vwidth -1) downto 0); -- Comp Nivel 3
signal c31_H: std_logic_vector((vwidth-1) downto 0); -- Comp Nivel 3
signal c32_L: std_logic_vector((vwidth -1) downto 0); -- Comp Nivel 3
signal c32_H: std_logic_vector((vwidth -1) downto 0); -- Comp Nivel 3
signal c33_L: std_logic_vector((vwidth -1) downto 0); -- Comp Nivel 3
signal c33_H: std_logic_vector((vwidth -1) downto 0); -- Comp Nivel 3
signal c34_L: std_logic_vector((vwidth -1) downto 0); -- Comp Nivel 3
signal c34_H: std_logic_vector((vwidth -1) downto 0); -- Comp Nivel 3
signal r31: std_logic_vector((vwidth -1) downto 0);
-- Nivel 4
signal c41_L: std_logic_vector((vwidth -1) downto 0); -- Comp Nivel 4
signal c41_H: std_logic_vector((vwidth-1) downto 0); -- Comp Nivel 4
signal c42_L: std_logic_vector((vwidth -1) downto 0); -- Comp Nivel 4
signal c42_H: std_logic_vector((vwidth -1) downto 0); -- Comp Nivel 4
signal r41: std_logic_vector((vwidth -1) downto 0);
signal r42: std_logic_vector((vwidth -1) downto 0);
signal r43: std_logic_vector((vwidth -1) downto 0);
signal r44: std_logic_vector((vwidth -1) downto 0);
signal r45: std_logic_vector((vwidth -1) downto 0);
-- Nivel 4a
signal c41a_L: std_logic_vector((vwidth -1) downto 0); -- Comp Nivel 4a
signal c41a_H: std_logic_vector((vwidth-1) downto 0); -- Comp Nivel 4a
signal c42a_L: std_logic_vector((vwidth -1) downto 0); -- Comp Nivel 4a
signal c42a_H: std_logic_vector((vwidth -1) downto 0); -- Comp Nivel 4a
signal c43a_L: std_logic_vector((vwidth -1) downto 0); -- Comp Nivel 4a
signal c43a_H: std_logic_vector((vwidth -1) downto 0); -- Comp Nivel 4a
signal r41a: std_logic_vector((vwidth -1) downto 0);
signal r42a: std_logic_vector((vwidth -1) downto 0);
signal r43a: std_logic_vector((vwidth -1) downto 0);
-- Nivel 4b
signal c41b_L: std_logic_vector((vwidth -1) downto 0); -- Comp Nivel 4b
signal c41b_H: std_logic_vector((vwidth-1) downto 0); -- Comp Nivel 4b
signal c42b_L: std_logic_vector((vwidth -1) downto 0); -- Comp Nivel 4b
signal c42b_H: std_logic_vector((vwidth -1) downto 0); -- Comp Nivel 4b
signal r41b: std_logic_vector((vwidth -1) downto 0);
signal r42b: std_logic_vector((vwidth -1) downto 0);
signal r43b: std_logic_vector((vwidth -1) downto 0);
signal r44b: std_logic_vector((vwidth -1) downto 0);
signal r45b: std_logic_vector((vwidth -1) downto 0);
-- Nivel 5
signal c51_L: std_logic_vector((vwidth -1) downto 0); -- Comp Nivel 5
signal c51_H: std_logic_vector((vwidth-1) downto 0); -- Comp Nivel 5
signal c52_L: std_logic_vector((vwidth -1) downto 0); -- Comp Nivel 5
signal c52_H: std_logic_vector((vwidth-1) downto 0); -- Comp Nivel 5
signal r51: std_logic_vector((vwidth -1) downto 0);
signal r52: std_logic_vector((vwidth -1) downto 0);
signal r53: std_logic_vector((vwidth -1) downto 0);
signal r54: std_logic_vector((vwidth -1) downto 0);
signal r55: std_logic_vector((vwidth -1) downto 0);
-- Nivel 6
signal c61_L: std_logic_vector((vwidth -1) downto 0); -- Comp Nivel 6
signal c61_H: std_logic_vector((vwidth-1) downto 0); -- Comp Nivel 6
signal r61: std_logic_vector((vwidth -1) downto 0);
signal r62: std_logic_vector((vwidth -1) downto 0);
signal r63: std_logic_vector((vwidth -1) downto 0);
signal r64: std_logic_vector((vwidth -1) downto 0);
signal r65: std_logic_vector((vwidth -1) downto 0);
signal r66: std_logic_vector((vwidth -1) downto 0);
signal r67: std_logic_vector((vwidth -1) downto 0);
-- Nivel 7
signal c71_L: std_logic_vector((vwidth -1) downto 0); -- Comp Nivel 7
signal c71_H: std_logic_vector((vwidth-1) downto 0); -- Comp Nivel 7
signal r71: std_logic_vector((vwidth -1) downto 0);
signal r72: std_logic_vector((vwidth -1) downto 0);
signal r73: std_logic_vector((vwidth -1) downto 0);
signal r74: std_logic_vector((vwidth -1) downto 0);
signal r75: std_logic_vector((vwidth -1) downto 0);
signal r76: std_logic_vector((vwidth -1) downto 0);
signal r77: std_logic_vector((vwidth -1) downto 0);
-- Nivel 8
signal c81_L: std_logic_vector((vwidth -1) downto 0); -- Comp Nivel 8
signal c81_H: std_logic_vector((vwidth-1) downto 0); -- Comp Nivel 8
signal r81: std_logic_vector((vwidth -1) downto 0);
signal r82: std_logic_vector((vwidth -1) downto 0);
signal r83: std_logic_vector((vwidth -1) downto 0);
signal r84: std_logic_vector((vwidth -1) downto 0);
signal r85: std_logic_vector((vwidth -1) downto 0);
signal r86: std_logic_vector((vwidth -1) downto 0);
signal r87: std_logic_vector((vwidth -1) downto 0);
-- Nivel 9
signal c91_L: std_logic_vector((vwidth -1) downto 0); -- Comp Nivel 9
signal c91_H: std_logic_vector((vwidth-1) downto 0); -- Comp Nivel 9
signal r91: std_logic_vector((vwidth -1) downto 0);
signal r92: std_logic_vector((vwidth -1) downto 0);
signal r93: std_logic_vector((vwidth -1) downto 0);
signal r94: std_logic_vector((vwidth -1) downto 0);
signal r95: std_logic_vector((vwidth -1) downto 0);
signal r96: std_logic_vector((vwidth -1) downto 0);
signal r97: std_logic_vector((vwidth -1) downto 0);
-- Nivel 10
signal c101_L: std_logic_vector((vwidth -1) downto 0); -- Comp Nivel 10
signal c101_H: std_logic_vector((vwidth-1) downto 0); -- Comp Nivel 10
signal r101: std_logic_vector((vwidth -1) downto 0);
signal r102: std_logic_vector((vwidth -1) downto 0);
signal r103: std_logic_vector((vwidth -1) downto 0);
signal r104: std_logic_vector((vwidth -1) downto 0);
signal r105: std_logic_vector((vwidth -1) downto 0);
signal r106: std_logic_vector((vwidth -1) downto 0);
signal r107: std_logic_vector((vwidth -1) downto 0);
-- Nivel 11
signal c111_L: std_logic_vector((vwidth -1) downto 0); -- Comp Nivel 11
signal c111_H: std_logic_vector((vwidth-1) downto 0); -- Comp Nivel 11
signal r111: std_logic_vector((vwidth -1) downto 0);
signal r112: std_logic_vector((vwidth -1) downto 0);
signal r113: std_logic_vector((vwidth -1) downto 0);
signal r114: std_logic_vector((vwidth -1) downto 0);
signal r115: std_logic_vector((vwidth -1) downto 0);
signal r116: std_logic_vector((vwidth -1) downto 0);
signal r117: std_logic_vector((vwidth -1) downto 0);
-- Nivel 12
signal c121_L: std_logic_vector((vwidth -1) downto 0); -- Comp Nivel 12
signal c121_H: std_logic_vector((vwidth-1) downto 0); -- Comp Nivel 12
signal r121: std_logic_vector((vwidth -1) downto 0);
signal r122: std_logic_vector((vwidth -1) downto 0);
signal r123: std_logic_vector((vwidth -1) downto 0);
signal r124: std_logic_vector((vwidth -1) downto 0);
signal r125: std_logic_vector((vwidth -1) downto 0);
signal r126: std_logic_vector((vwidth -1) downto 0);
signal r127: std_logic_vector((vwidth -1) downto 0);
-- Nivel 13
signal r131: std_logic_vector((vwidth -1) downto 0);
signal r132: std_logic_vector((vwidth -1) downto 0);
signal r133: std_logic_vector((vwidth -1) downto 0);
signal r134: std_logic_vector((vwidth -1) downto 0);
signal r135: std_logic_vector((vwidth -1) downto 0);
signal r136: std_logic_vector((vwidth -1) downto 0);
signal r137: std_logic_vector((vwidth -1) downto 0);
signal r138: std_logic_vector((vwidth -1) downto 0);
signal r139: std_logic_vector((vwidth -1) downto 0);
-- signals for DV coordination
signal dddddddddddddddDV: std_logic:='0';--rst
signal ddddddddddddddDV: std_logic:='0';--rst
signal dddddddddddddDV: std_logic:='0';--este es el original --rst
signal ddddddddddddDV: std_logic:='0';
signal dddddddddddDV: std_logic:='0';
signal ddddddddddDV: std_logic:='0';
signal dddddddddDV: std_logic:='0';
signal ddddddddDV: std_logic:='0';
signal dddddddDV: std_logic:='0';
signal ddddddDV: std_logic:='0';
signal dddddDV: std_logic:='0';
signal ddddDV: std_logic:='0';
signal dddDV: std_logic:='0';
signal ddDV: std_logic:='0';
signal dDV: std_logic:='0';
begin
process(Clk,RSTn)
begin
if RSTn = '0' then
--Nivel 1
c11_L <= (others=>'0');
c11_H <= (others=>'0');
c12_L <= (others=>'0');
c12_H <= (others=>'0');
c13_L <= (others=>'0');
c13_H <= (others=>'0');
c14_L <= (others=>'0');
c14_H <= (others=>'0');
r11 <= (others=>'0');
-- Nivel 2
c21_L <= (others=>'0');
c21_H <= (others=>'0');
c22_L <= (others=>'0');
c22_H <= (others=>'0');
c23_L <= (others=>'0');
c23_H <= (others=>'0');
c24_L <= (others=>'0');
c24_H <= (others=>'0');
r21 <= (others=>'0');
-- Nivel 3
c31_L <= (others=>'0');
c31_H <= (others=>'0');
c32_L <= (others=>'0');
c32_H <= (others=>'0');
c33_L <= (others=>'0');
c33_H <= (others=>'0');
c34_L <= (others=>'0');
c34_H <= (others=>'0');
r31 <= (others=>'0');
-- Nivel 4
c41_L <= (others=>'0');
c41_H <= (others=>'0');
c42_L <= (others=>'0');
c42_H <= (others=>'0');
r41 <= (others=>'0');
r42 <= (others=>'0');
r43 <= (others=>'0');
r44 <= (others=>'0');
r45 <= (others=>'0');
-- Nivel 4a
c41a_L <= (others=>'0');
c41a_H <= (others=>'0');
c42a_L <= (others=>'0');
c42a_H <= (others=>'0');
c43a_L <= (others=>'0');
c43a_H <= (others=>'0');
r41a <= (others=>'0');
r42a <= (others=>'0');
r43a <= (others=>'0');
-- Nivel 4b
c41b_L <= (others=>'0');
c41b_H <= (others=>'0');
c42b_L <= (others=>'0');
c42b_H <= (others=>'0');
r41b <= (others=>'0');
r42b <= (others=>'0');
r43b <= (others=>'0');
r44b <= (others=>'0');
r45b <= (others=>'0');
-- Nivel 5
c51_L <= (others=>'0');
c51_H <= (others=>'0');
c52_L <= (others=>'0');
c52_H <= (others=>'0');
r51 <= (others=>'0');
r52 <= (others=>'0');
r53 <= (others=>'0');
r54 <= (others=>'0');
r55 <= (others=>'0');
-- Nivel 6
c61_L <= (others=>'0');
c61_H <= (others=>'0');
r61 <= (others=>'0');
r62 <= (others=>'0');
r63 <= (others=>'0');
r64 <= (others=>'0');
r65 <= (others=>'0');
r66 <= (others=>'0');
r67 <= (others=>'0');
-- Nivel 7
c71_L <= (others=>'0');
c71_H <= (others=>'0');
r71 <= (others=>'0');
r72 <= (others=>'0');
r73 <= (others=>'0');
r74 <= (others=>'0');
r75 <= (others=>'0');
r76 <= (others=>'0');
r77 <= (others=>'0');
-- Nivel 8
c81_L <= (others=>'0');
c81_H <= (others=>'0');
r81 <= (others=>'0');
r82 <= (others=>'0');
r83 <= (others=>'0');
r84 <= (others=>'0');
r85 <= (others=>'0');
r86 <= (others=>'0');
r87 <= (others=>'0');
-- Nivel 9
c91_L <= (others=>'0');
c91_H <= (others=>'0');
r91 <= (others=>'0');
r92 <= (others=>'0');
r93 <= (others=>'0');
r94 <= (others=>'0');
r95 <= (others=>'0');
r96 <= (others=>'0');
r97 <= (others=>'0');
-- Nivel 10
c101_L <= (others=>'0');
c101_H <= (others=>'0');
r101 <= (others=>'0');
r102 <= (others=>'0');
r103 <= (others=>'0');
r104 <= (others=>'0');
r105 <= (others=>'0');
r106 <= (others=>'0');
r107 <= (others=>'0');
-- Nivel 11
c111_L <= (others=>'0');
c111_H <= (others=>'0');
r111 <= (others=>'0');
r112 <= (others=>'0');
r113 <= (others=>'0');
r114 <= (others=>'0');
r115 <= (others=>'0');
r116 <= (others=>'0');
r117 <= (others=>'0');
-- Nivel 12
c121_L <= (others=>'0');
c121_H <= (others=>'0');
r121 <= (others=>'0');
r122 <= (others=>'0');
r123 <= (others=>'0');
r124 <= (others=>'0');
r125 <= (others=>'0');
r126 <= (others=>'0');
r127 <= (others=>'0');
s1 <= (others=>'0');
s2 <= (others=>'0');
s3 <= (others=>'0');
s4 <= (others=>'0');
s5 <= (others=>'0');
s6 <= (others=>'0');
s7 <= (others=>'0');
s8 <= (others=>'0');
s9 <= (others=>'0');
ddddddddddddDV <= '0';
dddddddddddDV <= '0';
ddddddddddDV <= '0';
dddddddddDV <= '0';
ddddddddDV <= '0';
dddddddDV <= '0';
ddddddDV <= '0';
dddddDV <= '0';
ddddDV <= '0';
dddDV <= '0';
ddDV <= '0';
dDV <= '0';
DVs <= '0';
elsif rising_edge(Clk) then
if DVw = '1' then
-- level 1
if w11 < w12 then
c11_L <= w11;
c11_H <= w12;
else
c11_L <= w12;
c11_H <= w11;
end if;
if w13 < w21 then
c12_L <= w13;
c12_H <= w21;
else
c12_L <= w21;
c12_H <= w13;
end if;
if w22 < w23 then
c13_L <= w22;
c13_H <= w23;
else
c13_L <= w23;
c13_H <= w22;
end if;
if w31 < w32 then
c14_L <= w31;
c14_H <= w32;
else
c14_L <= w32;
c14_H <= w31;
end if;
r11 <= w33;
-- level 2
if c11_L < c12_L then
c21_L <= c11_L;
c21_H <= c12_L;
else
c21_L <= c12_L;
c21_H <= c11_L;
end if;
if c11_H < c12_H then
c22_L <= c11_H;
c22_H <= c12_H;
else
c22_L <= c12_H;
c22_H <= c11_H;
end if;
if c13_L < c14_L then
c23_L <= c13_L;
c23_H <= c14_L;
else
c23_L <= c14_L;
c23_H <= c13_L;
end if;
if c13_H < c14_H then
c24_L <= c13_H;
c24_H <= c14_H;
else
c24_L <= c14_H;
c24_H <= c13_H;
end if;
r21 <= r11;
-- level 3
if c21_L < c23_L then
c31_L <= c21_L;
c31_H <= c23_L;
else
c31_L <= c23_L;
c31_H <= c21_L;
end if;
if c21_H < c22_L then
c32_L <= c21_H;
c32_H <= c22_L;
else
c32_L <= c22_L;
c32_H <= c21_H;
end if;
if c23_H < c24_L then
c33_L <= c23_H;
c33_H <= c24_L;
else
c33_L <= c24_L;
c33_H <= c23_H;
end if;
if c22_H < c24_H then
c34_L <= c22_H;
c34_H <= c24_H;
else
c34_L <= c24_H;
c34_H <= c22_H;
end if;
r31 <= r21;
-- level 4
if c32_L < c33_L then
c41_L <= c32_L;
c41_H <= c33_L;
else
c41_L <= c33_L;
c41_H <= c32_L;
end if;
if c32_H < c33_H then
c42_L <= c32_H;
c42_H <= c33_H;
else
c42_L <= c33_H;
c42_H <= c32_H;
end if;
r41 <= r31;
r42 <= c31_L;
r43 <= c31_H;
r44 <= c34_L;
r45 <= c34_H;
-- Nivel 4a
if r43 < c41_L then
c41a_L <= r43;
c41a_H <= c41_L;
else
c41a_L <= c41_L;
c41a_H <= r43;
end if;
if c41_H < c42_L then
c42a_L <= c41_H;
c42a_H <= c42_L;
else
c42a_L <= c42_L;
c42a_H <= c41_H;
end if;
if c42_H < r44 then
c43a_L <= c42_H;
c43a_H <= r44;
else
c43a_L <= r44;
c43a_H <= c42_H;
end if;
r41a <= r41;
r42a <= r42;
r43a <= r45;
-- Nivel 4b
if c41a_H < c42a_L then -- Nivel 4b
c41b_L <= c41a_H; -- Nivel 4b
c41b_H <= c42a_L; -- Nivel 4b
else -- Nivel 4b
c41b_L <= c42a_L; -- Nivel 4b
c41b_H <= c41a_H; -- Nivel 4b
end if; -- Nivel 4b
-- Nivel 4b
if c42a_H < c43a_L then -- Nivel 4b
c42b_L <= c42a_H; -- Nivel 4b
c42b_H <= c43a_L; -- Nivel 4b
else -- Nivel 4b
c42b_L <= c43a_L; -- Nivel 4b
c42b_H <= c42a_H; -- Nivel 4b
end if; -- Nivel 4b
-- Nivel 4b
r41b <= r41a; -- Nivel 4b
r42b <= r42a; -- Nivel 4b
r43b <= c41a_L; -- Nivel 4b
r44b <= c43a_H; -- Nivel 4b
r45b <= r43a; -- Nivel 4b
-- Nivel 5
if r41b < r42b then -- Nivel 5
c51_L <= r41b; -- Nivel 5;
c51_H <= r42b; -- Nivel 5
else -- Nivel 5
c51_L <= r42b; -- Nivel 5
c51_H <= r41b; -- Nivel 5
end if; -- Nivel 5
-- Nivel 5
if c41b_H < c42b_L then -- Nivel 5
c52_L <= c41b_H; -- Nivel 5
c52_H <= c42b_L; -- Nivel 5
else -- Nivel 5
c52_L <= c42b_L; -- Nivel 5
c52_H <= c41b_H; -- Nivel 5
end if; -- Nivel 5
-- Nivel 5
r51 <= r43b; -- Nivel 5
r52 <= c41b_L; -- Nivel 5
r53 <= c42b_H; -- Nivel 5
r54 <= r44b; -- Nivel 5
r55 <= r45b; -- Nivel 5
-- Nivel 6
if r51 < c51_H then
c61_L <= r51;
c61_H <= c51_H;
else
c61_L <= c51_H;
c61_H <= r51;
end if;
r61 <= c51_L;
r62 <= r52;
r63 <= c52_L;
r64 <= c52_H;
r65 <= r53;
r66 <= r54;
r67 <= r55;
-- level 7
if r62 < c61_H then
c71_L <= r62;
c71_H <= c61_H;
else
c71_L <= c61_H;
c71_H <= r62;
end if;
r71 <= r61;
r72 <= c61_L;
r73 <= r63;
r74 <= r64;
r75 <= r65;
r76 <= r66;
r77 <= r67;
-- level 8
if r73 < c71_H then
c81_L <= r73;
c81_H <= c71_H;
else
c81_L <= c71_H;
c81_H <= r73;
end if;
r81 <= r71;
r82 <= r72;
r83 <= c71_L;
r84 <= r74;
r85 <= r75;
r86 <= r76;
r87 <= r77;
-- level 9
if r84 < c81_H then
c91_L <= r84;
c91_H <= c81_H;
else
c91_L <= c81_H;
c91_H <= r84;
end if;
r91 <= r81; -- L
r92 <= r82; -- 2L
r93 <= r83; -- 3L
r94 <= c81_L; -- 4L
r95 <= r85;
r96 <= r86;
r97 <= r87;
-- level 10
if r95 < c91_H then
c101_L <= r95;
c101_H <= c91_H;
else
c101_L <= c91_H;
c101_H <= r95;
end if;
r101 <= r91; -- L
r102 <= r92; -- 2L
r103 <= r93; -- 3L
r104 <= r94; -- 4L
r105 <= c91_L; -- M
r106 <= r96;
r107 <= r97;
-- level 11
if r106 < c101_H then
c111_L <= r106;
c111_H <= c101_H;
else
c111_L <= c101_H;
c111_H <= r106;
end if;
r111 <= r101;
r112 <= r102;
r113 <= r103;
r114 <= r104;
r115 <= r105;
r116 <= c101_L;
r117 <= r107;
-- level 12
if r117 < c111_H then
c121_L <= r117;
c121_H <= c111_H;
else
c121_L <= c111_H;
c121_H <= r117;
end if;
r121 <= r111;
r122 <= r112;
r123 <= r113;
r124 <= r114;
r125 <= r115;
r126 <= r116;
r127 <= c111_L;
s1 <= r121;
s2 <= r122;
s3 <= r123;
s4 <= r124;
s5 <= r125;
s6 <= r126;
s7 <= r127;
s8 <= c121_L;
s9 <= c121_H;
--ddddddddddddddDV <= dddddddddddddddDV;
dddddddddddddDV <= ddddddddddddddDV;
ddddddddddddDV <= dddddddddddddDV;
dddddddddddDV <= ddddddddddddDV;
ddddddddddDV <= dddddddddddDV;
dddddddddDV <= ddddddddddDV;
ddddddddDV <= dddddddddDV;
dddddddDV <= ddddddddDV;
ddddddDV <= dddddddDV;
dddddDV <= ddddddDV;
ddddDV <= dddddDV;
dddDV <= ddddDV;
ddDV <= dddDV;
dDV <= ddDV;
DVs <= dDV;
end if;
if DVw = '1' then
ddddddddddddddDV <= '1';
end if;
end if;
end process;
end sort_3x3;
| gpl-3.0 | 5e8b97ede1f416383dd0b445fef46b6d | 0.541176 | 2.481317 | false | false | false | false |
estadofinito/biblioteca-vhdl | todos-los-archivos/clk_rom.vhd | 2 | 2,788 | ----------------------------------------------------------------------------------
-- Compañía: Estado Finito
-- Ingeniero: Carlos Ramos
--
-- Fecha de creación: 2014/04/24 17:41:30
-- Nombre del módulo: clk_rom - Behavioral
-- Comentarios adicionales:
-- Este divisor de frecuencia toma sus valores de una memoria ROM que contiene
-- los valores de los contadores. Por lo tanto, el rango de frecuencias depende
-- de la ROM.
--
-- Comentarios adicionales:
-- Se puede encontrar más información en la siguiente dirección:
-- http://www.estadofinito.com/metronomo-en-vhdl-2/
--
-- Revisión:
-- Revisión 0.02 - El tiempo en alto es constante, y corresponde a un periodo de
-- 10Hz (el sonido del metrónomo debe tener la misma duración
-- para todas las diversas frecuencias).
-- Dicha frecuencia debe ser mayor a la frecuencia mayor del
-- sistema, F > 512 BPM (u 8.53 Hz).
-- En este caso, la frecuencia o tiempo en alto es de 10Hz.
-- Revisión 0.01 - Archivo creado.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_1164.ALL;
entity clk_rom is
GENERIC (
NBITS : integer := 28 -- Cantidad de bits que tiene cada registro en la ROM.
);
PORT (
clk : in STD_LOGIC; -- Reloj de entrada de 3.125MHz.
reset : in STD_LOGIC;
escala : in STD_LOGIC_VECTOR(NBITS-1 downto 0);
clk_out : out STD_LOGIC -- Reloj de salida, dependiente del valor en memoria.
);
end clk_rom;
architecture Behavioral of clk_rom is
-- Señal utilizada para procesamiento interno de la señal de salida.
signal temporal : STD_LOGIC;
-- Señal que cubre el rango que puede alcanzar la ROM.
signal contador : integer range 0 to (2**(NBITS-4))-1 := 0;
-- Transformación de la escala de entrada a tipo numérico para el uso de operadores aritméticos.
signal escala_num : UNSIGNED(NBITS-1 downto 0) := (others => '0');
begin
-- Actualización de los datos de escala.
escala_num <= UNSIGNED(escala); -- Conversión de vector a número.
-- Procesamiento para el divisor de frecuencia.
divisor_frecuencia: process (clk, reset) begin
if (reset = '1') then
temporal <= '0';
contador <= 0;
elsif rising_edge(clk) then
if (contador = escala_num) then
contador <= 0;
else
if (contador < 312500) then
-- Tiempo de 10Hz en alto.
temporal <= '1';
else
-- Todo lo demás en bajo.
temporal <= '0';
end if;
contador <= contador + 1;
end if;
end if;
end process;
-- Asignación de la señal de salida.
clk_out <= temporal;
end Behavioral; | lgpl-2.1 | ff1825fa54cf7a8e1f5ed8ce00448a29 | 0.601664 | 3.472362 | false | false | false | false |
DougFirErickson/parallella-hw | fpga/ip/xilinx/memory_dp_48x4096/blk_mem_gen_v8_2/hdl/blk_mem_gen_bindec.vhd | 8 | 10,218 | `protect begin_protected
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`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5824)
`protect data_block
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`protect end_protected
| gpl-3.0 | 0fd7b8087cb4f763b4c5c787f9af1372 | 0.924447 | 1.896789 | false | false | false | false |
hgunicamp/Mips8B | src_design/pc_system.vhdl | 1 | 1,677 | Library Ieee;
Use Ieee.Std_logic_1164.all;
Entity PC_System is
Generic(N: Natural := 8);
Port(clock: in Std_Logic;
Reset_n: in Std_Logic;
en_Out_PC: in Std_Logic;
load_PC: in Std_Logic;
inc_PC: in Std_Logic;
in_PC: in Std_Logic_Vector(N-3 downto 0);
out_PC: out Std_Logic_Vector(N-3 downto 0);
address_PC: out Std_Logic_Vector(N-3 downto 0));
End Entity PC_System;
Architecture behave of PC_System is
-- Usando Biblioteca Aritmetica.
Use Ieee.Numeric_Std.all;
Signal PC_Value, next_PC_Value: Unsigned(N-3 downto 0);
Begin
-- Endereco a ser acessado.
address_PC <= Std_Logic_Vector(PC_Value);
-- Processos para atualização do PC
UPDATE_PC_COMB: Process(PC_Value,in_PC,load_PC)
Begin
If load_PC = '1' then
next_PC_Value <= Unsigned(in_PC);
Else
next_PC_Value <= PC_Value + 1;
End If;
End Process UPDATE_PC_COMB;
UPDATE_PC_SYNC: Process
Begin
Wait Until clock'event and clock = '1';
If Reset_n = '0' then
PC_Value <= (Others => '0');
ElsIf load_PC = '1' or inc_PC = '1' then
PC_Value <= next_PC_Value;
End If;
End Process UPDATE_PC_SYNC;
OUT_PC_VALUE: Process(en_Out_PC,PC_Value)
Begin
If en_Out_PC = '1' then
out_PC <= Std_Logic_Vector(PC_Value);
Else
out_PC <= (Others => '0');
End If;
End Process OUT_PC_VALUE;
End Architecture behave;
Configuration PC_System_behave of PC_System is
For behave
End For;
End Configuration PC_System_behave;
| unlicense | 0c49aa02653bf97c92a2af0a5e35d35d | 0.571343 | 3.202677 | false | false | false | false |
DougFirErickson/parallella-hw | fpga/ip/xilinx/memory_dp_48x4096/blk_mem_gen_v8_2/hdl/blk_mem_gen_getinit_pkg.vhd | 8 | 63,345 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 45152)
`protect data_block
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`protect end_protected
| gpl-3.0 | c2fb93a5ca34c7e70c23a3d4b1df9bf5 | 0.951519 | 1.821934 | false | false | false | false |
quicky2000/IP_register | my_register.vhd | 1 | 1,541 | --
-- This file is part of IP_register
-- Copyright (C) 2011 Julien Thevenon ( julien_thevenon at yahoo.fr )
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity my_register is
generic (
size : natural := 1);-- size
port (
clk : in std_logic; -- clock
rst : in std_logic; --rst
input : in std_logic_vector(size - 1 downto 0); -- input
output : out std_logic_vector(size -1 downto 0) -- output
-- input : in std_logic_vector; -- input
-- output : out std_logic_vector -- output
);
end my_register;
architecture behavourial of my_register is
begin -- behavourial
my_register: process(clk,rst)
begin
if rising_edge(clk) then
if rst = '1' then
output <= (others => '0');
else
output <= input;
end if;
end if;
end process;
end behavourial;
| gpl-3.0 | b24d435df644275bfcc03067132709d4 | 0.658014 | 3.704327 | false | false | false | false |
DougFirErickson/parallella-hw | fpga/ip/xilinx/fifo_async_103x32/fifo_generator_v12_0/hdl/common/output_blk.vhd | 6 | 27,163 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 18368)
`protect data_block
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`protect end_protected
| gpl-3.0 | e9aa5bc0317f311aa3a7323207391e3b | 0.945551 | 1.840436 | false | false | false | false |
dummylink/plnk_fpga-stack | Examples/xilinx_microblaze/avnet_lx9/pcores/plb_powerlink_v1_00_a/hdl/vhdl/openMAC_DMAFifo_Xilinx/n_synchronizer.vhd | 2 | 3,577 | ------------------------------------------------------------------------------------------------------------------------
-- n sychronizer of the async fifo
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Note: A general implementation of a asynchronous fifo which is
-- using a dual port ram. This file is the n sychronizer.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2011-09-22 V0.01 mairt first version
-- 2011-10-14 V0.02 zelenkaj add an additional sync stage
-- 2011-11-25 V0.03 mairt omitted reset out
------------------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity synchronizer_g is
generic(N: natural);
port(
clk, reset: in std_logic;
in_async: in std_logic_vector(N-1 downto 0);
out_sync: out std_logic_vector(N-1 downto 0)
);
end synchronizer_g;
architecture two_ff_arch of synchronizer_g is
signal meta_reg, sync_reg, sync_reg1 : std_logic_vector(N-1 downto 0) := (others => '0');
signal meta_next, sync_next, sync_next1 : std_logic_vector(N-1 downto 0) := (others => '0');
begin
-- two registers
process(clk)--,reset)
begin
-- if (reset='1') then
-- meta_reg <= (others=>'0');
-- sync_reg <= (others=>'0');
-- sync_reg1 <= (others => '0');
if (clk'event and clk='1') then
meta_reg <= meta_next;
sync_reg <= sync_next;
sync_reg1 <= sync_next1;
end if;
end process;
-- next-state logic
meta_next <= in_async;
sync_next <= meta_reg;
sync_next1 <= sync_reg;
-- output
out_sync <= sync_reg1;
end two_ff_arch; | gpl-2.0 | 8c9d1fe2269e1c36dcde883c1dd29f95 | 0.573945 | 4.130485 | false | false | false | false |
JuanMarcosRamirez/WeightedMedianDisenoLogico | misc/Adicionales/Programador_StrataFlash_modificado/kcpsm3.vhd | 1 | 65,863 | -- PicoBlaze
--
-- Constant (K) Coded Programmable State Machine for Spartan-3 Devices.
-- Also suitable for use with Virtex-II and Virtex-IIPRO devices.
--
-- Includes additional code for enhanced VHDL simulation.
--
-- Version : 1.30
-- Version Date : 14th June 2004
-- Reasons : Avoid issue caused when ENABLE INTERRUPT is used when interrupts are
-- already enabled when an an interrupt input is applied.
-- Improved design for faster ZERO and CARRY flag logic
--
--
-- Previous Version : 1.20
-- Version Date : 9th July 2003
--
-- Start of design entry : 19th May 2003
--
-- Ken Chapman
-- Xilinx Ltd
-- Benchmark House
-- 203 Brooklands Road
-- Weybridge
-- Surrey KT13 ORH
-- United Kingdom
--
-- [email protected]
--
-- Instruction disassembly concept inspired by the work of Prof. Dr.-Ing. Bernhard Lang.
-- University of Applied Sciences, Osnabrueck, Germany.
--
------------------------------------------------------------------------------------
--
-- NOTICE:
--
-- Copyright Xilinx, Inc. 2003. This code may be contain portions patented by other
-- third parties. By providing this core as one possible implementation of a standard,
-- Xilinx is making no representation that the provided implementation of this standard
-- is free from any claims of infringement by any third party. Xilinx expressly
-- disclaims any warranty with respect to the adequacy of the implementation, including
-- but not limited to any warranty or representation that the implementation is free
-- from claims of any third party. Furthermore, Xilinx is providing this core as a
-- courtesy to you and suggests that you contact all third parties to obtain the
-- necessary rights to use this implementation.
--
------------------------------------------------------------------------------------
--
-- Format of this file.
--
-- This file contains the definition of KCPSM3 as one complete module with sections
-- created using generate loops. This 'flat' approach has been adopted to decrease
-- the time taken to load the module into simulators and the synthesis process.
--
-- The module defines the implementation of the logic using Xilinx primitives.
-- These ensure predictable synthesis results and maximise the density of the implementation.
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
------------------------------------------------------------------------------------
--
-- Library declarations
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
------------------------------------------------------------------------------------
--
-- Main Entity for KCPSM3
--
entity kcpsm3 is
Port ( address : out std_logic_vector(9 downto 0);
instruction : in std_logic_vector(17 downto 0);
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
out_port : out std_logic_vector(7 downto 0);
read_strobe : out std_logic;
in_port : in std_logic_vector(7 downto 0);
interrupt : in std_logic;
interrupt_ack : out std_logic;
reset : in std_logic;
clk : in std_logic);
end kcpsm3;
--
------------------------------------------------------------------------------------
--
-- Start of Main Architecture for KCPSM3
--
architecture low_level_definition of kcpsm3 is
--
------------------------------------------------------------------------------------
--
-- Signals used in KCPSM3
--
------------------------------------------------------------------------------------
--
-- Fundamental control and decode signals
--
signal t_state : std_logic;
signal not_t_state : std_logic;
signal internal_reset : std_logic;
signal reset_delay : std_logic;
signal move_group : std_logic;
signal condition_met : std_logic;
signal normal_count : std_logic;
signal call_type : std_logic;
signal push_or_pop_type : std_logic;
signal valid_to_move : std_logic;
--
-- Flag signals
--
signal flag_type : std_logic;
signal flag_write : std_logic;
signal flag_enable : std_logic;
signal zero_flag : std_logic;
signal sel_shadow_zero : std_logic;
signal low_zero : std_logic;
signal high_zero : std_logic;
signal low_zero_carry : std_logic;
signal high_zero_carry : std_logic;
signal zero_carry : std_logic;
signal zero_fast_route : std_logic;
signal low_parity : std_logic;
signal high_parity : std_logic;
signal parity_carry : std_logic;
signal parity : std_logic;
signal carry_flag : std_logic;
signal sel_parity : std_logic;
signal sel_arith_carry : std_logic;
signal sel_shift_carry : std_logic;
signal sel_shadow_carry : std_logic;
signal sel_carry : std_logic_vector(3 downto 0);
signal carry_fast_route : std_logic;
--
-- Interrupt signals
--
signal active_interrupt : std_logic;
signal int_pulse : std_logic;
signal clean_int : std_logic;
signal shadow_carry : std_logic;
signal shadow_zero : std_logic;
signal int_enable : std_logic;
signal int_update_enable : std_logic;
signal int_enable_value : std_logic;
signal interrupt_ack_internal : std_logic;
--
-- Program Counter signals
--
signal pc : std_logic_vector(9 downto 0);
signal pc_vector : std_logic_vector(9 downto 0);
signal pc_vector_carry : std_logic_vector(8 downto 0);
signal inc_pc_vector : std_logic_vector(9 downto 0);
signal pc_value : std_logic_vector(9 downto 0);
signal pc_value_carry : std_logic_vector(8 downto 0);
signal inc_pc_value : std_logic_vector(9 downto 0);
signal pc_enable : std_logic;
--
-- Data Register signals
--
signal sx : std_logic_vector(7 downto 0);
signal sy : std_logic_vector(7 downto 0);
signal register_type : std_logic;
signal register_write : std_logic;
signal register_enable : std_logic;
signal second_operand : std_logic_vector(7 downto 0);
--
-- Scratch Pad Memory signals
--
signal memory_data : std_logic_vector(7 downto 0);
signal store_data : std_logic_vector(7 downto 0);
signal memory_type : std_logic;
signal memory_write : std_logic;
signal memory_enable : std_logic;
--
-- Stack signals
--
signal stack_pop_data : std_logic_vector(9 downto 0);
signal stack_ram_data : std_logic_vector(9 downto 0);
signal stack_address : std_logic_vector(4 downto 0);
signal half_stack_address : std_logic_vector(4 downto 0);
signal stack_address_carry : std_logic_vector(3 downto 0);
signal next_stack_address : std_logic_vector(4 downto 0);
signal stack_write_enable : std_logic;
signal not_active_interrupt : std_logic;
--
-- ALU signals
--
signal logical_result : std_logic_vector(7 downto 0);
signal logical_value : std_logic_vector(7 downto 0);
signal sel_logical : std_logic;
signal shift_result : std_logic_vector(7 downto 0);
signal shift_value : std_logic_vector(7 downto 0);
signal sel_shift : std_logic;
signal high_shift_in : std_logic;
signal low_shift_in : std_logic;
signal shift_in : std_logic;
signal shift_carry : std_logic;
signal shift_carry_value : std_logic;
signal arith_result : std_logic_vector(7 downto 0);
signal arith_value : std_logic_vector(7 downto 0);
signal half_arith : std_logic_vector(7 downto 0);
signal arith_internal_carry : std_logic_vector(7 downto 0);
signal sel_arith_carry_in : std_logic;
signal arith_carry_in : std_logic;
signal invert_arith_carry : std_logic;
signal arith_carry_out : std_logic;
signal sel_arith : std_logic;
signal arith_carry : std_logic;
--
-- ALU multiplexer signals
--
signal input_fetch_type : std_logic;
signal sel_group : std_logic;
signal alu_group : std_logic_vector(7 downto 0);
signal input_group : std_logic_vector(7 downto 0);
signal alu_result : std_logic_vector(7 downto 0);
--
-- read and write strobes
--
signal io_initial_decode : std_logic;
signal write_active : std_logic;
signal read_active : std_logic;
--
--
------------------------------------------------------------------------------------
--
-- Attributes to define LUT contents during implementation for primitives not
-- contained within generate loops. In each case the information is repeated
-- in the generic map for functional simulation
--
attribute INIT : string;
attribute INIT of t_state_lut : label is "1";
attribute INIT of int_pulse_lut : label is "0080";
attribute INIT of int_update_lut : label is "EAAA";
attribute INIT of int_value_lut : label is "04";
attribute INIT of move_group_lut : label is "7400";
attribute INIT of condition_met_lut : label is "5A3C";
attribute INIT of normal_count_lut : label is "2F";
attribute INIT of call_type_lut : label is "1000";
attribute INIT of push_pop_lut : label is "5400";
attribute INIT of valid_move_lut : label is "D";
attribute INIT of flag_type_lut : label is "41FC";
attribute INIT of flag_enable_lut : label is "8";
attribute INIT of low_zero_lut : label is "0001";
attribute INIT of high_zero_lut : label is "0001";
attribute INIT of sel_shadow_zero_lut : label is "3F";
attribute INIT of low_parity_lut : label is "6996";
attribute INIT of high_parity_lut : label is "6996";
attribute INIT of sel_parity_lut : label is "F3FF";
attribute INIT of sel_arith_carry_lut : label is "F3";
attribute INIT of sel_shift_carry_lut : label is "C";
attribute INIT of sel_shadow_carry_lut : label is "3";
attribute INIT of register_type_lut : label is "0145";
attribute INIT of register_enable_lut : label is "8";
attribute INIT of memory_type_lut : label is "0400";
attribute INIT of memory_enable_lut : label is "8000";
attribute INIT of sel_logical_lut : label is "FFE2";
attribute INIT of low_shift_in_lut : label is "E4";
attribute INIT of high_shift_in_lut : label is "E4";
attribute INIT of shift_carry_lut : label is "E4";
attribute INIT of sel_arith_lut : label is "1F";
attribute INIT of input_fetch_type_lut : label is "0002";
attribute INIT of io_decode_lut : label is "0010";
attribute INIT of write_active_lut : label is "4000";
attribute INIT of read_active_lut : label is "0100";
--
------------------------------------------------------------------------------------
--
-- Start of KCPSM3 circuit description
--
------------------------------------------------------------------------------------
--
begin
--
------------------------------------------------------------------------------------
--
-- Fundamental Control
--
-- Definition of T-state and internal reset
--
------------------------------------------------------------------------------------
--
t_state_lut: LUT1
--synthesis translate_off
generic map (INIT => X"1")
--synthesis translate_on
port map( I0 => t_state,
O => not_t_state );
toggle_flop: FDR
port map ( D => not_t_state,
Q => t_state,
R => internal_reset,
C => clk);
reset_flop1: FDS
port map ( D => '0',
Q => reset_delay,
S => reset,
C => clk);
reset_flop2: FDS
port map ( D => reset_delay,
Q => internal_reset,
S => reset,
C => clk);
--
------------------------------------------------------------------------------------
--
-- Interrupt input logic, Interrupt enable and shadow Flags.
--
-- Captures interrupt input and enables the shadow flags.
-- Decodes instructions which set and reset the interrupt enable flip-flop.
--
------------------------------------------------------------------------------------
--
-- Interrupt capture
int_capture_flop: FDR
port map ( D => interrupt,
Q => clean_int,
R => internal_reset,
C => clk);
int_pulse_lut: LUT4
--synthesis translate_off
generic map (INIT => X"0080")
--synthesis translate_on
port map( I0 => t_state,
I1 => clean_int,
I2 => int_enable,
I3 => active_interrupt,
O => int_pulse );
int_flop: FDR
port map ( D => int_pulse,
Q => active_interrupt,
R => internal_reset,
C => clk);
ack_flop: FD
port map ( D => active_interrupt,
Q => interrupt_ack_internal,
C => clk);
interrupt_ack <= interrupt_ack_internal;
-- Shadow flags
shadow_carry_flop: FDE
port map ( D => carry_flag,
Q => shadow_carry,
CE => active_interrupt,
C => clk);
shadow_zero_flop: FDE
port map ( D => zero_flag,
Q => shadow_zero,
CE => active_interrupt,
C => clk);
-- Decode instructions that set or reset interrupt enable
int_update_lut: LUT4
--synthesis translate_off
generic map (INIT => X"EAAA")
--synthesis translate_on
port map( I0 => active_interrupt,
I1 => instruction(15),
I2 => instruction(16),
I3 => instruction(17),
O => int_update_enable );
int_value_lut: LUT3
--synthesis translate_off
generic map (INIT => X"04")
--synthesis translate_on
port map( I0 => active_interrupt,
I1 => instruction(0),
I2 => interrupt_ack_internal,
O => int_enable_value );
int_enable_flop: FDRE
port map ( D => int_enable_value,
Q => int_enable,
CE => int_update_enable,
R => internal_reset,
C => clk);
--
------------------------------------------------------------------------------------
--
-- Decodes for the control of the program counter and CALL/RETURN stack
--
------------------------------------------------------------------------------------
--
move_group_lut: LUT4
--synthesis translate_off
generic map (INIT => X"7400")
--synthesis translate_on
port map( I0 => instruction(14),
I1 => instruction(15),
I2 => instruction(16),
I3 => instruction(17),
O => move_group );
condition_met_lut: LUT4
--synthesis translate_off
generic map (INIT => X"5A3C")
--synthesis translate_on
port map( I0 => carry_flag,
I1 => zero_flag,
I2 => instruction(10),
I3 => instruction(11),
O => condition_met );
normal_count_lut: LUT3
--synthesis translate_off
generic map (INIT => X"2F")
--synthesis translate_on
port map( I0 => instruction(12),
I1 => condition_met,
I2 => move_group,
O => normal_count );
call_type_lut: LUT4
--synthesis translate_off
generic map (INIT => X"1000")
--synthesis translate_on
port map( I0 => instruction(14),
I1 => instruction(15),
I2 => instruction(16),
I3 => instruction(17),
O => call_type );
push_pop_lut: LUT4
--synthesis translate_off
generic map (INIT => X"5400")
--synthesis translate_on
port map( I0 => instruction(14),
I1 => instruction(15),
I2 => instruction(16),
I3 => instruction(17),
O => push_or_pop_type );
valid_move_lut: LUT2
--synthesis translate_off
generic map (INIT => X"D")
--synthesis translate_on
port map( I0 => instruction(12),
I1 => condition_met,
O => valid_to_move );
--
------------------------------------------------------------------------------------
--
-- The ZERO and CARRY Flags
--
------------------------------------------------------------------------------------
--
-- Enable for flags
flag_type_lut: LUT4
--synthesis translate_off
generic map (INIT => X"41FC")
--synthesis translate_on
port map( I0 => instruction(14),
I1 => instruction(15),
I2 => instruction(16),
I3 => instruction(17),
O => flag_type );
flag_write_flop: FD
port map ( D => flag_type,
Q => flag_write,
C => clk);
flag_enable_lut: LUT2
--synthesis translate_off
generic map (INIT => X"8")
--synthesis translate_on
port map( I0 => t_state,
I1 => flag_write,
O => flag_enable );
-- Zero Flag
low_zero_lut: LUT4
--synthesis translate_off
generic map (INIT => X"0001")
--synthesis translate_on
port map( I0 => alu_result(0),
I1 => alu_result(1),
I2 => alu_result(2),
I3 => alu_result(3),
O => low_zero );
high_zero_lut: LUT4
--synthesis translate_off
generic map (INIT => X"0001")
--synthesis translate_on
port map( I0 => alu_result(4),
I1 => alu_result(5),
I2 => alu_result(6),
I3 => alu_result(7),
O => high_zero );
low_zero_muxcy: MUXCY
port map( DI => '0',
CI => '1',
S => low_zero,
O => low_zero_carry );
high_zero_cymux: MUXCY
port map( DI => '0',
CI => low_zero_carry,
S => high_zero,
O => high_zero_carry );
sel_shadow_zero_lut: LUT3
--synthesis translate_off
generic map (INIT => X"3F")
--synthesis translate_on
port map( I0 => shadow_zero,
I1 => instruction(16),
I2 => instruction(17),
O => sel_shadow_zero );
zero_cymux: MUXCY
port map( DI => shadow_zero,
CI => high_zero_carry,
S => sel_shadow_zero,
O => zero_carry );
zero_xor: XORCY
port map( LI => '0',
CI => zero_carry,
O => zero_fast_route);
zero_flag_flop: FDRE
port map ( D => zero_fast_route,
Q => zero_flag,
CE => flag_enable,
R => internal_reset,
C => clk);
-- Parity detection
low_parity_lut: LUT4
--synthesis translate_off
generic map (INIT => X"6996")
--synthesis translate_on
port map( I0 => logical_result(0),
I1 => logical_result(1),
I2 => logical_result(2),
I3 => logical_result(3),
O => low_parity );
high_parity_lut: LUT4
--synthesis translate_off
generic map (INIT => X"6996")
--synthesis translate_on
port map( I0 => logical_result(4),
I1 => logical_result(5),
I2 => logical_result(6),
I3 => logical_result(7),
O => high_parity );
parity_muxcy: MUXCY
port map( DI => '0',
CI => '1',
S => low_parity,
O => parity_carry );
parity_xor: XORCY
port map( LI => high_parity,
CI => parity_carry,
O => parity);
-- CARRY flag selection
sel_parity_lut: LUT4
--synthesis translate_off
generic map (INIT => X"F3FF")
--synthesis translate_on
port map( I0 => parity,
I1 => instruction(13),
I2 => instruction(15),
I3 => instruction(16),
O => sel_parity );
sel_arith_carry_lut: LUT3
--synthesis translate_off
generic map (INIT => X"F3")
--synthesis translate_on
port map( I0 => arith_carry,
I1 => instruction(16),
I2 => instruction(17),
O => sel_arith_carry );
sel_shift_carry_lut: LUT2
--synthesis translate_off
generic map (INIT => X"C")
--synthesis translate_on
port map( I0 => shift_carry,
I1 => instruction(15),
O => sel_shift_carry );
sel_shadow_carry_lut: LUT2
--synthesis translate_off
generic map (INIT => X"3")
--synthesis translate_on
port map( I0 => shadow_carry,
I1 => instruction(17),
O => sel_shadow_carry );
sel_shadow_muxcy: MUXCY
port map( DI => shadow_carry,
CI => '0',
S => sel_shadow_carry,
O => sel_carry(0) );
sel_shift_muxcy: MUXCY
port map( DI => shift_carry,
CI => sel_carry(0),
S => sel_shift_carry,
O => sel_carry(1) );
sel_arith_muxcy: MUXCY
port map( DI => arith_carry,
CI => sel_carry(1),
S => sel_arith_carry,
O => sel_carry(2) );
sel_parity_muxcy: MUXCY
port map( DI => parity,
CI => sel_carry(2),
S => sel_parity,
O => sel_carry(3) );
carry_xor: XORCY
port map( LI => '0',
CI => sel_carry(3),
O => carry_fast_route);
carry_flag_flop: FDRE
port map ( D => carry_fast_route,
Q => carry_flag,
CE => flag_enable,
R => internal_reset,
C => clk);
--
------------------------------------------------------------------------------------
--
-- The Program Counter
--
-- Definition of a 10-bit counter which can be loaded from two sources
--
------------------------------------------------------------------------------------
--
invert_enable: INV -- Inverter should be implemented in the CE to flip flops
port map( I => t_state,
O => pc_enable);
pc_loop: for i in 0 to 9 generate
--
-- Attribute to define LUT contents during implementation
-- The information is repeated in the generic map for functional simulation
--
attribute INIT : string;
attribute INIT of vector_select_mux : label is "E4";
attribute INIT of value_select_mux : label is "E4";
--
begin
vector_select_mux: LUT3
--synthesis translate_off
generic map (INIT => X"E4")
--synthesis translate_on
port map( I0 => instruction(15),
I1 => instruction(i),
I2 => stack_pop_data(i),
O => pc_vector(i) );
value_select_mux: LUT3
--synthesis translate_off
generic map (INIT => X"E4")
--synthesis translate_on
port map( I0 => normal_count,
I1 => inc_pc_vector(i),
I2 => pc(i),
O => pc_value(i) );
register_bit: FDRSE
port map ( D => inc_pc_value(i),
Q => pc(i),
R => internal_reset,
S => active_interrupt,
CE => pc_enable,
C => clk);
pc_lsb_carry: if i=0 generate
begin
pc_vector_muxcy: MUXCY
port map( DI => '0',
CI => instruction(13),
S => pc_vector(i),
O => pc_vector_carry(i));
pc_vector_xor: XORCY
port map( LI => pc_vector(i),
CI => instruction(13),
O => inc_pc_vector(i));
pc_value_muxcy: MUXCY
port map( DI => '0',
CI => normal_count,
S => pc_value(i),
O => pc_value_carry(i));
pc_value_xor: XORCY
port map( LI => pc_value(i),
CI => normal_count,
O => inc_pc_value(i));
end generate pc_lsb_carry;
pc_mid_carry: if i>0 and i<9 generate
begin
pc_vector_muxcy: MUXCY
port map( DI => '0',
CI => pc_vector_carry(i-1),
S => pc_vector(i),
O => pc_vector_carry(i));
pc_vector_xor: XORCY
port map( LI => pc_vector(i),
CI => pc_vector_carry(i-1),
O => inc_pc_vector(i));
pc_value_muxcy: MUXCY
port map( DI => '0',
CI => pc_value_carry(i-1),
S => pc_value(i),
O => pc_value_carry(i));
pc_value_xor: XORCY
port map( LI => pc_value(i),
CI => pc_value_carry(i-1),
O => inc_pc_value(i));
end generate pc_mid_carry;
pc_msb_carry: if i=9 generate
begin
pc_vector_xor: XORCY
port map( LI => pc_vector(i),
CI => pc_vector_carry(i-1),
O => inc_pc_vector(i));
pc_value_xor: XORCY
port map( LI => pc_value(i),
CI => pc_value_carry(i-1),
O => inc_pc_value(i));
end generate pc_msb_carry;
end generate pc_loop;
address <= pc;
--
------------------------------------------------------------------------------------
--
-- Register Bank and second operand selection.
--
-- Definition of an 8-bit dual port RAM with 16 locations
-- including write enable decode.
--
-- Outputs are assigned to PORT_ID and OUT_PORT.
--
------------------------------------------------------------------------------------
--
-- Forming decode signal
register_type_lut: LUT4
--synthesis translate_off
generic map (INIT => X"0145")
--synthesis translate_on
port map( I0 => active_interrupt,
I1 => instruction(15),
I2 => instruction(16),
I3 => instruction(17),
O => register_type );
register_write_flop: FD
port map ( D => register_type,
Q => register_write,
C => clk);
register_enable_lut: LUT2
--synthesis translate_off
generic map (INIT => X"8")
--synthesis translate_on
port map( I0 => t_state,
I1 => register_write,
O => register_enable );
reg_loop: for i in 0 to 7 generate
--
-- Attribute to define RAM contents during implementation
-- The information is repeated in the generic map for functional simulation
--
attribute INIT : string;
attribute INIT of register_bit : label is "0000";
attribute INIT of operand_select_mux : label is "E4";
--
begin
register_bit: RAM16X1D
--synthesis translate_off
generic map(INIT => X"0000")
--synthesis translate_on
port map ( D => alu_result(i),
WE => register_enable,
WCLK => clk,
A0 => instruction(8),
A1 => instruction(9),
A2 => instruction(10),
A3 => instruction(11),
DPRA0 => instruction(4),
DPRA1 => instruction(5),
DPRA2 => instruction(6),
DPRA3 => instruction(7),
SPO => sx(i),
DPO => sy(i));
operand_select_mux: LUT3
--synthesis translate_off
generic map (INIT => X"E4")
--synthesis translate_on
port map( I0 => instruction(12),
I1 => instruction(i),
I2 => sy(i),
O => second_operand(i) );
end generate reg_loop;
out_port <= sx;
port_id <= second_operand;
--
------------------------------------------------------------------------------------
--
-- Store Memory
--
-- Definition of an 8-bit single port RAM with 64 locations
-- including write enable decode.
--
------------------------------------------------------------------------------------
--
-- Forming decode signal
memory_type_lut: LUT4
--synthesis translate_off
generic map (INIT => X"0400")
--synthesis translate_on
port map( I0 => active_interrupt,
I1 => instruction(15),
I2 => instruction(16),
I3 => instruction(17),
O => memory_type );
memory_write_flop: FD
port map ( D => memory_type,
Q => memory_write,
C => clk);
memory_enable_lut: LUT4
--synthesis translate_off
generic map (INIT => X"8000")
--synthesis translate_on
port map( I0 => t_state,
I1 => instruction(13),
I2 => instruction(14),
I3 => memory_write,
O => memory_enable );
store_loop: for i in 0 to 7 generate
--
-- Attribute to define RAM contents during implementation
-- The information is repeated in the generic map for functional simulation
--
attribute INIT : string;
attribute INIT of memory_bit : label is "0000000000000000";
--
begin
memory_bit: RAM64X1S
--synthesis translate_off
generic map(INIT => X"0000000000000000")
--synthesis translate_on
port map ( D => sx(i),
WE => memory_enable,
WCLK => clk,
A0 => second_operand(0),
A1 => second_operand(1),
A2 => second_operand(2),
A3 => second_operand(3),
A4 => second_operand(4),
A5 => second_operand(5),
O => memory_data(i));
store_flop: FD
port map ( D => memory_data(i),
Q => store_data(i),
C => clk);
end generate store_loop;
--
------------------------------------------------------------------------------------
--
-- Logical operations
--
-- Definition of AND, OR, XOR and LOAD functions which also provides TEST.
-- Includes pipeline stage used to form ALU multiplexer including decode.
--
------------------------------------------------------------------------------------
--
sel_logical_lut: LUT4
--synthesis translate_off
generic map (INIT => X"FFE2")
--synthesis translate_on
port map( I0 => instruction(14),
I1 => instruction(15),
I2 => instruction(16),
I3 => instruction(17),
O => sel_logical );
logical_loop: for i in 0 to 7 generate
--
-- Attribute to define LUT contents during implementation
-- The information is repeated in the generic map for functional simulation
attribute INIT : string;
attribute INIT of logical_lut : label is "6E8A";
--
begin
logical_lut: LUT4
--synthesis translate_off
generic map (INIT => X"6E8A")
--synthesis translate_on
port map( I0 => second_operand(i),
I1 => sx(i),
I2 => instruction(13),
I3 => instruction(14),
O => logical_value(i));
logical_flop: FDR
port map ( D => logical_value(i),
Q => logical_result(i),
R => sel_logical,
C => clk);
end generate logical_loop;
--
--
------------------------------------------------------------------------------------
--
-- Shift and Rotate operations
--
-- Includes pipeline stage used to form ALU multiplexer including decode.
--
------------------------------------------------------------------------------------
--
sel_shift_inv: INV -- Inverter should be implemented in the reset to flip flops
port map( I => instruction(17),
O => sel_shift);
-- Bit to input to shift register
high_shift_in_lut: LUT3
--synthesis translate_off
generic map (INIT => X"E4")
--synthesis translate_on
port map( I0 => instruction(1),
I1 => sx(0),
I2 => instruction(0),
O => high_shift_in );
low_shift_in_lut: LUT3
--synthesis translate_off
generic map (INIT => X"E4")
--synthesis translate_on
port map( I0 => instruction(1),
I1 => carry_flag,
I2 => sx(7),
O => low_shift_in );
shift_in_muxf5: MUXF5
port map( I1 => high_shift_in,
I0 => low_shift_in,
S => instruction(2),
O => shift_in );
-- Forming shift carry signal
shift_carry_lut: LUT3
--synthesis translate_off
generic map (INIT => X"E4")
--synthesis translate_on
port map( I0 => instruction(3),
I1 => sx(7),
I2 => sx(0),
O => shift_carry_value );
pipeline_bit: FD
port map ( D => shift_carry_value,
Q => shift_carry,
C => clk);
shift_loop: for i in 0 to 7 generate
begin
lsb_shift: if i=0 generate
--
-- Attribute to define LUT contents during implementation
-- The information is repeated in the generic map for functional simulation
attribute INIT : string;
attribute INIT of shift_mux_lut : label is "E4";
--
begin
shift_mux_lut: LUT3
--synthesis translate_off
generic map (INIT => X"E4")
--synthesis translate_on
port map( I0 => instruction(3),
I1 => shift_in,
I2 => sx(i+1),
O => shift_value(i) );
end generate lsb_shift;
mid_shift: if i>0 and i<7 generate
--
-- Attribute to define LUT contents during implementation
-- The information is repeated in the generic map for functional simulation
attribute INIT : string;
attribute INIT of shift_mux_lut : label is "E4";
--
begin
shift_mux_lut: LUT3
--synthesis translate_off
generic map (INIT => X"E4")
--synthesis translate_on
port map( I0 => instruction(3),
I1 => sx(i-1),
I2 => sx(i+1),
O => shift_value(i) );
end generate mid_shift;
msb_shift: if i=7 generate
--
-- Attribute to define LUT contents during implementation
-- The information is repeated in the generic map for functional simulation
attribute INIT : string;
attribute INIT of shift_mux_lut : label is "E4";
--
begin
shift_mux_lut: LUT3
--synthesis translate_off
generic map (INIT => X"E4")
--synthesis translate_on
port map( I0 => instruction(3),
I1 => sx(i-1),
I2 => shift_in,
O => shift_value(i) );
end generate msb_shift;
shift_flop: FDR
port map ( D => shift_value(i),
Q => shift_result(i),
R => sel_shift,
C => clk);
end generate shift_loop;
--
------------------------------------------------------------------------------------
--
-- Arithmetic operations
--
-- Definition of ADD, ADDCY, SUB and SUBCY functions which also provides COMPARE.
-- Includes pipeline stage used to form ALU multiplexer including decode.
--
------------------------------------------------------------------------------------
--
sel_arith_lut: LUT3
--synthesis translate_off
generic map (INIT => X"1F")
--synthesis translate_on
port map( I0 => instruction(14),
I1 => instruction(15),
I2 => instruction(16),
O => sel_arith );
arith_loop: for i in 0 to 7 generate
--
-- Attribute to define LUT contents during implementation
-- The information is repeated in the generic map for functional simulation
attribute INIT : string;
attribute INIT of arith_lut : label is "96";
--
begin
lsb_arith: if i=0 generate
--
-- Attribute to define LUT contents during implementation
-- The information is repeated in the generic map for functional simulation
attribute INIT : string;
attribute INIT of arith_carry_in_lut : label is "6C";
--
begin
arith_carry_in_lut: LUT3
--synthesis translate_off
generic map (INIT => X"6C")
--synthesis translate_on
port map( I0 => instruction(13),
I1 => instruction(14),
I2 => carry_flag,
O => sel_arith_carry_in );
arith_carry_in_muxcy: MUXCY
port map( DI => '0',
CI => '1',
S => sel_arith_carry_in,
O => arith_carry_in);
arith_muxcy: MUXCY
port map( DI => sx(i),
CI => arith_carry_in,
S => half_arith(i),
O => arith_internal_carry(i));
arith_xor: XORCY
port map( LI => half_arith(i),
CI => arith_carry_in,
O => arith_value(i));
end generate lsb_arith;
mid_arith: if i>0 and i<7 generate
begin
arith_muxcy: MUXCY
port map( DI => sx(i),
CI => arith_internal_carry(i-1),
S => half_arith(i),
O => arith_internal_carry(i));
arith_xor: XORCY
port map( LI => half_arith(i),
CI => arith_internal_carry(i-1),
O => arith_value(i));
end generate mid_arith;
msb_arith: if i=7 generate
--
-- Attribute to define LUT contents during implementation
-- The information is repeated in the generic map for functional simulation
attribute INIT : string;
attribute INIT of arith_carry_out_lut : label is "2";
--
begin
arith_muxcy: MUXCY
port map( DI => sx(i),
CI => arith_internal_carry(i-1),
S => half_arith(i),
O => arith_internal_carry(i));
arith_xor: XORCY
port map( LI => half_arith(i),
CI => arith_internal_carry(i-1),
O => arith_value(i));
arith_carry_out_lut: LUT1
--synthesis translate_off
generic map (INIT => X"2")
--synthesis translate_on
port map( I0 => instruction(14),
O => invert_arith_carry );
arith_carry_out_xor: XORCY
port map( LI => invert_arith_carry,
CI => arith_internal_carry(i),
O => arith_carry_out);
arith_carry_flop: FDR
port map ( D => arith_carry_out,
Q => arith_carry,
R => sel_arith,
C => clk);
end generate msb_arith;
arith_lut: LUT3
--synthesis translate_off
generic map (INIT => X"96")
--synthesis translate_on
port map( I0 => sx(i),
I1 => second_operand(i),
I2 => instruction(14),
O => half_arith(i));
arith_flop: FDR
port map ( D => arith_value(i),
Q => arith_result(i),
R => sel_arith,
C => clk);
end generate arith_loop;
--
--
------------------------------------------------------------------------------------
--
-- ALU multiplexer
--
------------------------------------------------------------------------------------
--
input_fetch_type_lut: LUT4
--synthesis translate_off
generic map (INIT => X"0002")
--synthesis translate_on
port map( I0 => instruction(14),
I1 => instruction(15),
I2 => instruction(16),
I3 => instruction(17),
O => input_fetch_type );
sel_group_flop: FD
port map ( D => input_fetch_type,
Q => sel_group,
C => clk);
alu_mux_loop: for i in 0 to 7 generate
--
-- Attribute to define LUT contents during implementation
-- The information is repeated in the generic map for functional simulation
attribute INIT : string;
attribute INIT of or_lut : label is "FE";
attribute INIT of mux_lut : label is "E4";
--
begin
or_lut: LUT3
--synthesis translate_off
generic map (INIT => X"FE")
--synthesis translate_on
port map( I0 => logical_result(i),
I1 => arith_result(i),
I2 => shift_result(i),
O => alu_group(i));
mux_lut: LUT3
--synthesis translate_off
generic map (INIT => X"E4")
--synthesis translate_on
port map( I0 => instruction(13),
I1 => in_port(i),
I2 => store_data(i),
O => input_group(i));
shift_in_muxf5: MUXF5
port map( I1 => input_group(i),
I0 => alu_group(i),
S => sel_group,
O => alu_result(i) );
end generate alu_mux_loop;
--
------------------------------------------------------------------------------------
--
-- Read and Write Strobes
--
------------------------------------------------------------------------------------
--
io_decode_lut: LUT4
--synthesis translate_off
generic map (INIT => X"0010")
--synthesis translate_on
port map( I0 => active_interrupt,
I1 => instruction(13),
I2 => instruction(14),
I3 => instruction(16),
O => io_initial_decode );
write_active_lut: LUT4
--synthesis translate_off
generic map (INIT => X"4000")
--synthesis translate_on
port map( I0 => t_state,
I1 => instruction(15),
I2 => instruction(17),
I3 => io_initial_decode,
O => write_active );
write_strobe_flop: FDR
port map ( D => write_active,
Q => write_strobe,
R => internal_reset,
C => clk);
read_active_lut: LUT4
--synthesis translate_off
generic map (INIT => X"0100")
--synthesis translate_on
port map( I0 => t_state,
I1 => instruction(15),
I2 => instruction(17),
I3 => io_initial_decode,
O => read_active );
read_strobe_flop: FDR
port map ( D => read_active,
Q => read_strobe,
R => internal_reset,
C => clk);
--
------------------------------------------------------------------------------------
--
-- Program CALL/RETURN stack
--
-- Provided the counter and memory for a 32 deep stack supporting nested
-- subroutine calls to a depth of 31 levels.
--
------------------------------------------------------------------------------------
--
-- Stack memory is 32 locations of 10-bit single port.
stack_ram_inv: INV -- Inverter should be implemented in the WE to RAM
port map( I => t_state,
O => stack_write_enable);
stack_ram_loop: for i in 0 to 9 generate
--
-- Attribute to define RAM contents during implementation
-- The information is repeated in the generic map for functional simulation
--
attribute INIT : string;
attribute INIT of stack_bit : label is "00000000";
--
begin
stack_bit: RAM32X1S
--synthesis translate_off
generic map(INIT => X"00000000")
--synthesis translate_on
port map ( D => pc(i),
WE => stack_write_enable,
WCLK => clk,
A0 => stack_address(0),
A1 => stack_address(1),
A2 => stack_address(2),
A3 => stack_address(3),
A4 => stack_address(4),
O => stack_ram_data(i));
stack_flop: FD
port map ( D => stack_ram_data(i),
Q => stack_pop_data(i),
C => clk);
end generate stack_ram_loop;
-- Stack address pointer is a 5-bit counter
stack_count_inv: INV -- Inverter should be implemented in the CE to the flip-flops
port map( I => active_interrupt,
O => not_active_interrupt);
stack_count_loop: for i in 0 to 4 generate
begin
register_bit: FDRE
port map ( D => next_stack_address(i),
Q => stack_address(i),
R => internal_reset,
CE => not_active_interrupt,
C => clk);
lsb_stack_count: if i=0 generate
--
-- Attribute to define LUT contents during implementation
-- The information is repeated in the generic map for functional simulation
--
attribute INIT : string;
attribute INIT of count_lut : label is "6555";
--
begin
count_lut: LUT4
--synthesis translate_off
generic map (INIT => X"6555")
--synthesis translate_on
port map( I0 => stack_address(i),
I1 => t_state,
I2 => valid_to_move,
I3 => push_or_pop_type,
O => half_stack_address(i) );
count_muxcy: MUXCY
port map( DI => stack_address(i),
CI => '0',
S => half_stack_address(i),
O => stack_address_carry(i));
count_xor: XORCY
port map( LI => half_stack_address(i),
CI => '0',
O => next_stack_address(i));
end generate lsb_stack_count;
mid_stack_count: if i>0 and i<4 generate
--
-- Attribute to define LUT contents during implementation
-- The information is repeated in the generic map for functional simulation
--
attribute INIT : string;
attribute INIT of count_lut : label is "A999";
--
begin
count_lut: LUT4
--synthesis translate_off
generic map (INIT => X"A999")
--synthesis translate_on
port map( I0 => stack_address(i),
I1 => t_state,
I2 => valid_to_move,
I3 => call_type,
O => half_stack_address(i) );
count_muxcy: MUXCY
port map( DI => stack_address(i),
CI => stack_address_carry(i-1),
S => half_stack_address(i),
O => stack_address_carry(i));
count_xor: XORCY
port map( LI => half_stack_address(i),
CI => stack_address_carry(i-1),
O => next_stack_address(i));
end generate mid_stack_count;
msb_stack_count: if i=4 generate
--
-- Attribute to define LUT contents during implementation
-- The information is repeated in the generic map for functional simulation
--
attribute INIT : string;
attribute INIT of count_lut : label is "A999";
--
begin
count_lut: LUT4
--synthesis translate_off
generic map (INIT => X"A999")
--synthesis translate_on
port map( I0 => stack_address(i),
I1 => t_state,
I2 => valid_to_move,
I3 => call_type,
O => half_stack_address(i) );
count_xor: XORCY
port map( LI => half_stack_address(i),
CI => stack_address_carry(i-1),
O => next_stack_address(i));
end generate msb_stack_count;
end generate stack_count_loop;
--
------------------------------------------------------------------------------------
--
-- End of description for KCPSM3 macro.
--
------------------------------------------------------------------------------------
--
--**********************************************************************************
-- Code for simulation purposes only after this line
--**********************************************************************************
--
------------------------------------------------------------------------------------
--
-- Code for simulation.
--
-- Disassemble the instruction codes to form a text string variable for display.
-- Determine status of reset and flags and present in the form of a text string.
-- Provide a local variables to simulate the contents of each register and scratch
-- pad memory location.
--
------------------------------------------------------------------------------------
--
--All of this section is ignored during synthesis.
--synthesis translate off
simulation: process (clk, instruction)
--
--complete instruction decode
--
variable kcpsm3_opcode : string(1 to 19);
--
--Status of flags and processor
--
variable kcpsm3_status : string(1 to 13):= "NZ, NC, Reset";
--
--contents of each register
--
variable s0_contents : std_logic_vector(7 downto 0):=X"00";
variable s1_contents : std_logic_vector(7 downto 0):=X"00";
variable s2_contents : std_logic_vector(7 downto 0):=X"00";
variable s3_contents : std_logic_vector(7 downto 0):=X"00";
variable s4_contents : std_logic_vector(7 downto 0):=X"00";
variable s5_contents : std_logic_vector(7 downto 0):=X"00";
variable s6_contents : std_logic_vector(7 downto 0):=X"00";
variable s7_contents : std_logic_vector(7 downto 0):=X"00";
variable s8_contents : std_logic_vector(7 downto 0):=X"00";
variable s9_contents : std_logic_vector(7 downto 0):=X"00";
variable sa_contents : std_logic_vector(7 downto 0):=X"00";
variable sb_contents : std_logic_vector(7 downto 0):=X"00";
variable sc_contents : std_logic_vector(7 downto 0):=X"00";
variable sd_contents : std_logic_vector(7 downto 0):=X"00";
variable se_contents : std_logic_vector(7 downto 0):=X"00";
variable sf_contents : std_logic_vector(7 downto 0):=X"00";
--
--contents of each scratch pad memory location
--
variable spm00_contents : std_logic_vector(7 downto 0):=X"00";
variable spm01_contents : std_logic_vector(7 downto 0):=X"00";
variable spm02_contents : std_logic_vector(7 downto 0):=X"00";
variable spm03_contents : std_logic_vector(7 downto 0):=X"00";
variable spm04_contents : std_logic_vector(7 downto 0):=X"00";
variable spm05_contents : std_logic_vector(7 downto 0):=X"00";
variable spm06_contents : std_logic_vector(7 downto 0):=X"00";
variable spm07_contents : std_logic_vector(7 downto 0):=X"00";
variable spm08_contents : std_logic_vector(7 downto 0):=X"00";
variable spm09_contents : std_logic_vector(7 downto 0):=X"00";
variable spm0a_contents : std_logic_vector(7 downto 0):=X"00";
variable spm0b_contents : std_logic_vector(7 downto 0):=X"00";
variable spm0c_contents : std_logic_vector(7 downto 0):=X"00";
variable spm0d_contents : std_logic_vector(7 downto 0):=X"00";
variable spm0e_contents : std_logic_vector(7 downto 0):=X"00";
variable spm0f_contents : std_logic_vector(7 downto 0):=X"00";
variable spm10_contents : std_logic_vector(7 downto 0):=X"00";
variable spm11_contents : std_logic_vector(7 downto 0):=X"00";
variable spm12_contents : std_logic_vector(7 downto 0):=X"00";
variable spm13_contents : std_logic_vector(7 downto 0):=X"00";
variable spm14_contents : std_logic_vector(7 downto 0):=X"00";
variable spm15_contents : std_logic_vector(7 downto 0):=X"00";
variable spm16_contents : std_logic_vector(7 downto 0):=X"00";
variable spm17_contents : std_logic_vector(7 downto 0):=X"00";
variable spm18_contents : std_logic_vector(7 downto 0):=X"00";
variable spm19_contents : std_logic_vector(7 downto 0):=X"00";
variable spm1a_contents : std_logic_vector(7 downto 0):=X"00";
variable spm1b_contents : std_logic_vector(7 downto 0):=X"00";
variable spm1c_contents : std_logic_vector(7 downto 0):=X"00";
variable spm1d_contents : std_logic_vector(7 downto 0):=X"00";
variable spm1e_contents : std_logic_vector(7 downto 0):=X"00";
variable spm1f_contents : std_logic_vector(7 downto 0):=X"00";
variable spm20_contents : std_logic_vector(7 downto 0):=X"00";
variable spm21_contents : std_logic_vector(7 downto 0):=X"00";
variable spm22_contents : std_logic_vector(7 downto 0):=X"00";
variable spm23_contents : std_logic_vector(7 downto 0):=X"00";
variable spm24_contents : std_logic_vector(7 downto 0):=X"00";
variable spm25_contents : std_logic_vector(7 downto 0):=X"00";
variable spm26_contents : std_logic_vector(7 downto 0):=X"00";
variable spm27_contents : std_logic_vector(7 downto 0):=X"00";
variable spm28_contents : std_logic_vector(7 downto 0):=X"00";
variable spm29_contents : std_logic_vector(7 downto 0):=X"00";
variable spm2a_contents : std_logic_vector(7 downto 0):=X"00";
variable spm2b_contents : std_logic_vector(7 downto 0):=X"00";
variable spm2c_contents : std_logic_vector(7 downto 0):=X"00";
variable spm2d_contents : std_logic_vector(7 downto 0):=X"00";
variable spm2e_contents : std_logic_vector(7 downto 0):=X"00";
variable spm2f_contents : std_logic_vector(7 downto 0):=X"00";
variable spm30_contents : std_logic_vector(7 downto 0):=X"00";
variable spm31_contents : std_logic_vector(7 downto 0):=X"00";
variable spm32_contents : std_logic_vector(7 downto 0):=X"00";
variable spm33_contents : std_logic_vector(7 downto 0):=X"00";
variable spm34_contents : std_logic_vector(7 downto 0):=X"00";
variable spm35_contents : std_logic_vector(7 downto 0):=X"00";
variable spm36_contents : std_logic_vector(7 downto 0):=X"00";
variable spm37_contents : std_logic_vector(7 downto 0):=X"00";
variable spm38_contents : std_logic_vector(7 downto 0):=X"00";
variable spm39_contents : std_logic_vector(7 downto 0):=X"00";
variable spm3a_contents : std_logic_vector(7 downto 0):=X"00";
variable spm3b_contents : std_logic_vector(7 downto 0):=X"00";
variable spm3c_contents : std_logic_vector(7 downto 0):=X"00";
variable spm3d_contents : std_logic_vector(7 downto 0):=X"00";
variable spm3e_contents : std_logic_vector(7 downto 0):=X"00";
variable spm3f_contents : std_logic_vector(7 downto 0):=X"00";
--
--temporary variables
--
variable sx_decode : string(1 to 2); --sX register specification
variable sy_decode : string(1 to 2); --sY register specification
variable kk_decode : string(1 to 2); --constant value specification
variable aaa_decode : string(1 to 3); --address specification
--
--------------------------------------------------------------------------------
--
-- Function to convert 4-bit binary nibble to hexadecimal character
--
--------------------------------------------------------------------------------
--
function hexcharacter (nibble: std_logic_vector(3 downto 0))
return character is
variable hex: character;
begin
case nibble is
when "0000" => hex := '0';
when "0001" => hex := '1';
when "0010" => hex := '2';
when "0011" => hex := '3';
when "0100" => hex := '4';
when "0101" => hex := '5';
when "0110" => hex := '6';
when "0111" => hex := '7';
when "1000" => hex := '8';
when "1001" => hex := '9';
when "1010" => hex := 'A';
when "1011" => hex := 'B';
when "1100" => hex := 'C';
when "1101" => hex := 'D';
when "1110" => hex := 'E';
when "1111" => hex := 'F';
when others => hex := 'x';
end case;
return hex;
end hexcharacter;
--
--------------------------------------------------------------------------------
--
begin
-- decode first register
sx_decode(1) := 's';
sx_decode(2) := hexcharacter(instruction(11 downto 8));
-- decode second register
sy_decode(1) := 's';
sy_decode(2) := hexcharacter(instruction(7 downto 4));
-- decode constant value
kk_decode(1) := hexcharacter(instruction(7 downto 4));
kk_decode(2) := hexcharacter(instruction(3 downto 0));
-- address value
aaa_decode(1) := hexcharacter("00" & instruction(9 downto 8));
aaa_decode(2) := hexcharacter(instruction(7 downto 4));
aaa_decode(3) := hexcharacter(instruction(3 downto 0));
-- decode instruction
case instruction(17 downto 12) is
when "000000" => kcpsm3_opcode := "LOAD " & sx_decode & ',' & kk_decode & " ";
when "000001" => kcpsm3_opcode := "LOAD " & sx_decode & ',' & sy_decode & " ";
when "001010" => kcpsm3_opcode := "AND " & sx_decode & ',' & kk_decode & " ";
when "001011" => kcpsm3_opcode := "AND " & sx_decode & ',' & sy_decode & " ";
when "001100" => kcpsm3_opcode := "OR " & sx_decode & ',' & kk_decode & " ";
when "001101" => kcpsm3_opcode := "OR " & sx_decode & ',' & sy_decode & " ";
when "001110" => kcpsm3_opcode := "XOR " & sx_decode & ',' & kk_decode & " ";
when "001111" => kcpsm3_opcode := "XOR " & sx_decode & ',' & sy_decode & " ";
when "010010" => kcpsm3_opcode := "TEST " & sx_decode & ',' & kk_decode & " ";
when "010011" => kcpsm3_opcode := "TEST " & sx_decode & ',' & sy_decode & " ";
when "011000" => kcpsm3_opcode := "ADD " & sx_decode & ',' & kk_decode & " ";
when "011001" => kcpsm3_opcode := "ADD " & sx_decode & ',' & sy_decode & " ";
when "011010" => kcpsm3_opcode := "ADDCY " & sx_decode & ',' & kk_decode & " ";
when "011011" => kcpsm3_opcode := "ADDCY " & sx_decode & ',' & sy_decode & " ";
when "011100" => kcpsm3_opcode := "SUB " & sx_decode & ',' & kk_decode & " ";
when "011101" => kcpsm3_opcode := "SUB " & sx_decode & ',' & sy_decode & " ";
when "011110" => kcpsm3_opcode := "SUBCY " & sx_decode & ',' & kk_decode & " ";
when "011111" => kcpsm3_opcode := "SUBCY " & sx_decode & ',' & sy_decode & " ";
when "010100" => kcpsm3_opcode := "COMPARE " & sx_decode & ',' & kk_decode & " ";
when "010101" => kcpsm3_opcode := "COMPARE " & sx_decode & ',' & sy_decode & " ";
when "100000" =>
case instruction(3 downto 0) is
when "0110" => kcpsm3_opcode := "SL0 " & sx_decode & " ";
when "0111" => kcpsm3_opcode := "SL1 " & sx_decode & " ";
when "0100" => kcpsm3_opcode := "SLX " & sx_decode & " ";
when "0000" => kcpsm3_opcode := "SLA " & sx_decode & " ";
when "0010" => kcpsm3_opcode := "RL " & sx_decode & " ";
when "1110" => kcpsm3_opcode := "SR0 " & sx_decode & " ";
when "1111" => kcpsm3_opcode := "SR1 " & sx_decode & " ";
when "1010" => kcpsm3_opcode := "SRX " & sx_decode & " ";
when "1000" => kcpsm3_opcode := "SRA " & sx_decode & " ";
when "1100" => kcpsm3_opcode := "RR " & sx_decode & " ";
when others => kcpsm3_opcode := "Invalid Instruction";
end case;
when "101100" => kcpsm3_opcode := "OUTPUT " & sx_decode & ',' & kk_decode & " ";
when "101101" => kcpsm3_opcode := "OUTPUT " & sx_decode & ",(" & sy_decode & ") ";
when "000100" => kcpsm3_opcode := "INPUT " & sx_decode & ',' & kk_decode & " ";
when "000101" => kcpsm3_opcode := "INPUT " & sx_decode & ",(" & sy_decode & ") ";
when "101110" => kcpsm3_opcode := "STORE " & sx_decode & ',' & kk_decode & " ";
when "101111" => kcpsm3_opcode := "STORE " & sx_decode & ",(" & sy_decode & ") ";
when "000110" => kcpsm3_opcode := "FETCH " & sx_decode & ',' & kk_decode & " ";
when "000111" => kcpsm3_opcode := "FETCH " & sx_decode & ",(" & sy_decode & ") ";
when "110100" => kcpsm3_opcode := "JUMP " & aaa_decode & " ";
when "110101" =>
case instruction(11 downto 10) is
when "00" => kcpsm3_opcode := "JUMP Z," & aaa_decode & " ";
when "01" => kcpsm3_opcode := "JUMP NZ," & aaa_decode & " ";
when "10" => kcpsm3_opcode := "JUMP C," & aaa_decode & " ";
when "11" => kcpsm3_opcode := "JUMP NC," & aaa_decode & " ";
when others => kcpsm3_opcode := "Invalid Instruction";
end case;
when "110000" => kcpsm3_opcode := "CALL " & aaa_decode & " ";
when "110001" =>
case instruction(11 downto 10) is
when "00" => kcpsm3_opcode := "CALL Z," & aaa_decode & " ";
when "01" => kcpsm3_opcode := "CALL NZ," & aaa_decode & " ";
when "10" => kcpsm3_opcode := "CALL C," & aaa_decode & " ";
when "11" => kcpsm3_opcode := "CALL NC," & aaa_decode & " ";
when others => kcpsm3_opcode := "Invalid Instruction";
end case;
when "101010" => kcpsm3_opcode := "RETURN ";
when "101011" =>
case instruction(11 downto 10) is
when "00" => kcpsm3_opcode := "RETURN Z ";
when "01" => kcpsm3_opcode := "RETURN NZ ";
when "10" => kcpsm3_opcode := "RETURN C ";
when "11" => kcpsm3_opcode := "RETURN NC ";
when others => kcpsm3_opcode := "Invalid Instruction";
end case;
when "111000" =>
case instruction(0) is
when '0' => kcpsm3_opcode := "RETURNI DISABLE ";
when '1' => kcpsm3_opcode := "RETURNI ENABLE ";
when others => kcpsm3_opcode := "Invalid Instruction";
end case;
when "111100" =>
case instruction(0) is
when '0' => kcpsm3_opcode := "DISABLE INTERRUPT ";
when '1' => kcpsm3_opcode := "ENABLE INTERRUPT ";
when others => kcpsm3_opcode := "Invalid Instruction";
end case;
when others => kcpsm3_opcode := "Invalid Instruction";
end case;
if clk'event and clk='1' then
--reset and flag status information
if reset='1' or reset_delay='1' then
kcpsm3_status := "NZ, NC, Reset";
else
kcpsm3_status(7 to 13) := " ";
if flag_enable='1' then
if zero_carry='1' then
kcpsm3_status(1 to 4) := " Z, ";
else
kcpsm3_status(1 to 4) := "NZ, ";
end if;
if sel_carry(3)='1' then
kcpsm3_status(5 to 6) := " C";
else
kcpsm3_status(5 to 6) := "NC";
end if;
end if;
end if;
--simulation of register contents
if register_enable='1' then
case instruction(11 downto 8) is
when "0000" => s0_contents := alu_result;
when "0001" => s1_contents := alu_result;
when "0010" => s2_contents := alu_result;
when "0011" => s3_contents := alu_result;
when "0100" => s4_contents := alu_result;
when "0101" => s5_contents := alu_result;
when "0110" => s6_contents := alu_result;
when "0111" => s7_contents := alu_result;
when "1000" => s8_contents := alu_result;
when "1001" => s9_contents := alu_result;
when "1010" => sa_contents := alu_result;
when "1011" => sb_contents := alu_result;
when "1100" => sc_contents := alu_result;
when "1101" => sd_contents := alu_result;
when "1110" => se_contents := alu_result;
when "1111" => sf_contents := alu_result;
when others => null;
end case;
end if;
--simulation of scratch pad memory contents
if memory_enable='1' then
case second_operand(5 downto 0) is
when "000000" => spm00_contents := sx;
when "000001" => spm01_contents := sx;
when "000010" => spm02_contents := sx;
when "000011" => spm03_contents := sx;
when "000100" => spm04_contents := sx;
when "000101" => spm05_contents := sx;
when "000110" => spm06_contents := sx;
when "000111" => spm07_contents := sx;
when "001000" => spm08_contents := sx;
when "001001" => spm09_contents := sx;
when "001010" => spm0a_contents := sx;
when "001011" => spm0b_contents := sx;
when "001100" => spm0c_contents := sx;
when "001101" => spm0d_contents := sx;
when "001110" => spm0e_contents := sx;
when "001111" => spm0f_contents := sx;
when "010000" => spm10_contents := sx;
when "010001" => spm11_contents := sx;
when "010010" => spm12_contents := sx;
when "010011" => spm13_contents := sx;
when "010100" => spm14_contents := sx;
when "010101" => spm15_contents := sx;
when "010110" => spm16_contents := sx;
when "010111" => spm17_contents := sx;
when "011000" => spm18_contents := sx;
when "011001" => spm19_contents := sx;
when "011010" => spm1a_contents := sx;
when "011011" => spm1b_contents := sx;
when "011100" => spm1c_contents := sx;
when "011101" => spm1d_contents := sx;
when "011110" => spm1e_contents := sx;
when "011111" => spm1f_contents := sx;
when "100000" => spm20_contents := sx;
when "100001" => spm21_contents := sx;
when "100010" => spm22_contents := sx;
when "100011" => spm23_contents := sx;
when "100100" => spm24_contents := sx;
when "100101" => spm25_contents := sx;
when "100110" => spm26_contents := sx;
when "100111" => spm27_contents := sx;
when "101000" => spm28_contents := sx;
when "101001" => spm29_contents := sx;
when "101010" => spm2a_contents := sx;
when "101011" => spm2b_contents := sx;
when "101100" => spm2c_contents := sx;
when "101101" => spm2d_contents := sx;
when "101110" => spm2e_contents := sx;
when "101111" => spm2f_contents := sx;
when "110000" => spm30_contents := sx;
when "110001" => spm31_contents := sx;
when "110010" => spm32_contents := sx;
when "110011" => spm33_contents := sx;
when "110100" => spm34_contents := sx;
when "110101" => spm35_contents := sx;
when "110110" => spm36_contents := sx;
when "110111" => spm37_contents := sx;
when "111000" => spm38_contents := sx;
when "111001" => spm39_contents := sx;
when "111010" => spm3a_contents := sx;
when "111011" => spm3b_contents := sx;
when "111100" => spm3c_contents := sx;
when "111101" => spm3d_contents := sx;
when "111110" => spm3e_contents := sx;
when "111111" => spm3f_contents := sx;
when others => null;
end case;
end if;
end if;
end process simulation;
--synthesis translate on
--
--**********************************************************************************
-- End of simulation code.
--**********************************************************************************
--
--
end low_level_definition;
--
------------------------------------------------------------------------------------
--
-- END OF FILE KCPSM3.VHD
--
------------------------------------------------------------------------------------
| gpl-3.0 | d791f013fd071756d1ec17d0eb4b7531 | 0.519244 | 3.955973 | false | false | false | false |
foresterre/mal | vhdl/core.vhdl | 7 | 25,762 | library STD;
use STD.textio.all;
library WORK;
use WORK.types.all;
use WORK.env.all;
use WORK.reader.all;
use WORK.printer.all;
use WORK.pkg_readline.all;
package core is
procedure eval_native_func(func_sym: inout mal_val_ptr; args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr);
procedure define_core_functions(e: inout env_ptr);
end package core;
package body core is
procedure fn_equal(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable is_equal: boolean;
begin
equal_q(args.seq_val(0), args.seq_val(1), is_equal);
new_boolean(is_equal, result);
end procedure fn_equal;
procedure fn_throw(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
err := args.seq_val(0);
end procedure fn_throw;
procedure fn_nil_q(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
new_boolean(args.seq_val(0).val_type = mal_nil, result);
end procedure fn_nil_q;
procedure fn_true_q(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
new_boolean(args.seq_val(0).val_type = mal_true, result);
end procedure fn_true_q;
procedure fn_false_q(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
new_boolean(args.seq_val(0).val_type = mal_false, result);
end procedure fn_false_q;
procedure fn_string_q(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
new_boolean(args.seq_val(0).val_type = mal_string, result);
end procedure fn_string_q;
procedure fn_symbol(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
new_symbol(args.seq_val(0).string_val, result);
end procedure fn_symbol;
procedure fn_symbol_q(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
new_boolean(args.seq_val(0).val_type = mal_symbol, result);
end procedure fn_symbol_q;
procedure fn_keyword(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
new_keyword(args.seq_val(0).string_val, result);
end procedure fn_keyword;
procedure fn_keyword_q(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
new_boolean(args.seq_val(0).val_type = mal_keyword, result);
end procedure fn_keyword_q;
procedure fn_number_q(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
new_boolean(args.seq_val(0).val_type = mal_number, result);
end procedure fn_number_q;
procedure fn_function_q(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
new_boolean((args.seq_val(0).val_type = mal_fn and not args.seq_val(0).func_val.f_is_macro) or args.seq_val(0).val_type = mal_nativefn, result);
end procedure fn_function_q;
procedure fn_macro_q(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
new_boolean(args.seq_val(0).val_type = mal_fn and args.seq_val(0).func_val.f_is_macro, result);
end procedure fn_macro_q;
procedure fn_pr_str(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable s: line;
begin
pr_seq("", "", " ", args.seq_val, true, s);
new_string(s, result);
end procedure fn_pr_str;
procedure fn_str(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable s: line;
begin
pr_seq("", "", "", args.seq_val, false, s);
new_string(s, result);
end procedure fn_str;
procedure fn_prn(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable s: line;
begin
pr_seq("", "", " ", args.seq_val, true, s);
mal_printline(s.all);
new_nil(result);
end procedure fn_prn;
procedure fn_println(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable s: line;
begin
pr_seq("", "", " ", args.seq_val, false, s);
mal_printline(s.all);
new_nil(result);
end procedure fn_println;
procedure fn_read_string(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable ast: mal_val_ptr;
begin
read_str(args.seq_val(0).string_val.all, ast, err);
if ast = null then
new_nil(result);
else
result := ast;
end if;
end procedure fn_read_string;
procedure fn_readline(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable input_line: line;
variable is_eof: boolean;
begin
mal_readline(args.seq_val(0).string_val.all, is_eof, input_line);
if is_eof then
new_nil(result);
else
new_string(input_line, result);
end if;
end procedure fn_readline;
procedure fn_slurp(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
file f: text;
variable status: file_open_status;
variable save_content, content, one_line: line;
begin
file_open(status, f, external_name => args.seq_val(0).string_val.all, open_kind => read_mode);
if status = open_ok then
content := new string'("");
while not endfile(f) loop
readline(f, one_line);
save_content := content;
content := new string'(save_content.all & one_line.all & LF);
deallocate(save_content);
end loop;
file_close(f);
new_string(content, result);
else
new_string("Error opening file", err);
end if;
end procedure fn_slurp;
procedure fn_lt(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
new_boolean(args.seq_val(0).number_val < args.seq_val(1).number_val, result);
end procedure fn_lt;
procedure fn_lte(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
new_boolean(args.seq_val(0).number_val <= args.seq_val(1).number_val, result);
end procedure fn_lte;
procedure fn_gt(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
new_boolean(args.seq_val(0).number_val > args.seq_val(1).number_val, result);
end procedure fn_gt;
procedure fn_gte(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
new_boolean(args.seq_val(0).number_val >= args.seq_val(1).number_val, result);
end procedure fn_gte;
procedure fn_add(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
new_number(args.seq_val(0).number_val + args.seq_val(1).number_val, result);
end procedure fn_add;
procedure fn_sub(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
new_number(args.seq_val(0).number_val - args.seq_val(1).number_val, result);
end procedure fn_sub;
procedure fn_mul(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
new_number(args.seq_val(0).number_val * args.seq_val(1).number_val, result);
end procedure fn_mul;
procedure fn_div(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
new_number(args.seq_val(0).number_val / args.seq_val(1).number_val, result);
end procedure fn_div;
-- Define physical types (c_seconds64, c_microseconds64) because these are
-- represented as 64-bit words when passed to C functions
type c_seconds64 is range 0 to 1E16
units
c_sec;
end units c_seconds64;
type c_microseconds64 is range 0 to 1E6
units
c_usec;
end units c_microseconds64;
type c_timeval is record
tv_sec: c_seconds64;
tv_usec: c_microseconds64;
end record c_timeval;
-- Leave enough room for two 64-bit words
type c_timezone is record
dummy_1: c_seconds64;
dummy_2: c_seconds64;
end record c_timezone;
function gettimeofday(tv: c_timeval; tz: c_timezone) return integer;
attribute foreign of gettimeofday: function is "VHPIDIRECT gettimeofday";
function gettimeofday(tv: c_timeval; tz: c_timezone) return integer is
begin
assert false severity failure;
end function gettimeofday;
-- Returns the number of milliseconds since last midnight UTC because a
-- standard VHDL integer is 32-bit and therefore cannot hold the number of
-- milliseconds since 1970-01-01.
procedure fn_time_ms(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable tv: c_timeval;
variable dummy: c_timezone;
variable rc: integer;
begin
rc := gettimeofday(tv, dummy);
new_number(((tv.tv_sec / 1 c_sec) mod 86400) * 1000 + (tv.tv_usec / 1000 c_usec), result);
end procedure fn_time_ms;
procedure fn_list(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
result := args;
end procedure fn_list;
procedure fn_list_q(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
new_boolean(args.seq_val(0).val_type = mal_list, result);
end procedure fn_list_q;
procedure fn_vector(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
args.val_type := mal_vector;
result := args;
end procedure fn_vector;
procedure fn_vector_q(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
new_boolean(args.seq_val(0).val_type = mal_vector, result);
end procedure fn_vector_q;
procedure fn_hash_map(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
args.val_type := mal_hashmap;
result := args;
end procedure fn_hash_map;
procedure fn_map_q(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
new_boolean(args.seq_val(0).val_type = mal_hashmap, result);
end procedure fn_map_q;
procedure fn_assoc(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable new_hashmap: mal_val_ptr;
variable i: integer;
begin
hashmap_copy(args.seq_val(0), new_hashmap);
i := 1;
while i < args.seq_val'length loop
hashmap_put(new_hashmap, args.seq_val(i), args.seq_val(i + 1));
i := i + 2;
end loop;
result := new_hashmap;
end procedure fn_assoc;
procedure fn_dissoc(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable new_hashmap: mal_val_ptr;
variable i: integer;
begin
hashmap_copy(args.seq_val(0), new_hashmap);
for i in 1 to args.seq_val'high loop
hashmap_delete(new_hashmap, args.seq_val(i));
end loop;
result := new_hashmap;
end procedure fn_dissoc;
procedure fn_get(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable a0: mal_val_ptr := args.seq_val(0);
variable a1: mal_val_ptr := args.seq_val(1);
variable val: mal_val_ptr;
begin
if a0.val_type = mal_nil then
new_nil(result);
else
hashmap_get(a0, a1, val);
if val = null then
new_nil(result);
else
result := val;
end if;
end if;
end procedure fn_get;
procedure fn_contains_q(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable a0: mal_val_ptr := args.seq_val(0);
variable a1: mal_val_ptr := args.seq_val(1);
variable found: boolean;
begin
hashmap_contains(a0, a1, found);
new_boolean(found, result);
end procedure fn_contains_q;
procedure fn_keys(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable a0: mal_val_ptr := args.seq_val(0);
variable seq: mal_seq_ptr;
begin
seq := new mal_seq(0 to a0.seq_val'length / 2 - 1);
for i in seq'range loop
seq(i) := a0.seq_val(i * 2);
end loop;
new_seq_obj(mal_list, seq, result);
end procedure fn_keys;
procedure fn_vals(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable a0: mal_val_ptr := args.seq_val(0);
variable seq: mal_seq_ptr;
begin
seq := new mal_seq(0 to a0.seq_val'length / 2 - 1);
for i in seq'range loop
seq(i) := a0.seq_val(i * 2 + 1);
end loop;
new_seq_obj(mal_list, seq, result);
end procedure fn_vals;
procedure cons_helper(a0: inout mal_val_ptr; a1: inout mal_val_ptr; result: out mal_val_ptr) is
variable seq: mal_seq_ptr;
begin
seq := new mal_seq(0 to a1.seq_val'length);
seq(0) := a0;
seq(1 to seq'length - 1) := a1.seq_val(0 to a1.seq_val'length - 1);
new_seq_obj(mal_list, seq, result);
end procedure cons_helper;
procedure fn_cons(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable a0: mal_val_ptr := args.seq_val(0);
variable a1: mal_val_ptr := args.seq_val(1);
variable seq: mal_seq_ptr;
begin
cons_helper(a0, a1, result);
end procedure fn_cons;
procedure fn_sequential_q(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
new_boolean(is_sequential_type(args.seq_val(0).val_type), result);
end procedure fn_sequential_q;
procedure fn_concat(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable seq: mal_seq_ptr;
variable i: integer;
begin
seq := new mal_seq(0 to -1);
for i in args.seq_val'range loop
seq := new mal_seq'(seq.all & args.seq_val(i).seq_val.all);
end loop;
new_seq_obj(mal_list, seq, result);
end procedure fn_concat;
procedure fn_nth(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable lst_seq: mal_seq_ptr := args.seq_val(0).seq_val;
variable index: integer := args.seq_val(1).number_val;
begin
if index >= lst_seq'length then
new_string("nth: index out of range", err);
else
result := lst_seq(index);
end if;
end procedure fn_nth;
procedure fn_first(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable a0: mal_val_ptr := args.seq_val(0);
begin
if a0.val_type = mal_nil or a0.seq_val'length = 0 then
new_nil(result);
else
result := a0.seq_val(0);
end if;
end procedure fn_first;
procedure fn_rest(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable a0: mal_val_ptr := args.seq_val(0);
variable seq: mal_seq_ptr;
variable new_list: mal_val_ptr;
begin
if a0.val_type = mal_nil or a0.seq_val'length = 0 then
seq := new mal_seq(0 to -1);
new_seq_obj(mal_list, seq, result);
else
seq_drop_prefix(a0, 1, new_list);
new_list.val_type := mal_list;
result := new_list;
end if;
end procedure fn_rest;
procedure fn_empty_q(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable is_empty: boolean;
begin
case args.seq_val(0).val_type is
when mal_nil => new_boolean(true, result);
when mal_list | mal_vector => new_boolean(args.seq_val(0).seq_val'length = 0, result);
when others => new_string("empty?: invalid argument type", err);
end case;
end procedure fn_empty_q;
procedure fn_count(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable count: integer;
begin
case args.seq_val(0).val_type is
when mal_nil => new_number(0, result);
when mal_list | mal_vector => new_number(args.seq_val(0).seq_val'length, result);
when others => new_string("count: invalid argument type", err);
end case;
end procedure fn_count;
procedure fn_conj(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable a0: mal_val_ptr := args.seq_val(0);
variable r: mal_val_ptr;
variable seq: mal_seq_ptr;
begin
case a0.val_type is
when mal_list =>
r := a0;
for i in 1 to args.seq_val'high loop
cons_helper(args.seq_val(i), r, r);
end loop;
result := r;
when mal_vector =>
seq := new mal_seq(0 to a0.seq_val'length + args.seq_val'length - 2);
seq(0 to a0.seq_val'high) := a0.seq_val(a0.seq_val'range);
seq(a0.seq_val'high + 1 to seq'high) := args.seq_val(1 to args.seq_val'high);
new_seq_obj(mal_vector, seq, result);
when others =>
new_string("conj requires list or vector", err);
end case;
end procedure fn_conj;
procedure fn_seq(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable a0: mal_val_ptr := args.seq_val(0);
variable new_seq: mal_seq_ptr;
begin
case a0.val_type is
when mal_string =>
if a0.string_val'length = 0 then
new_nil(result);
else
new_seq := new mal_seq(0 to a0.string_val'length - 1);
for i in new_seq'range loop
new_string("" & a0.string_val(i + 1), new_seq(i));
end loop;
new_seq_obj(mal_list, new_seq, result);
end if;
when mal_list =>
if a0.seq_val'length = 0 then
new_nil(result);
else
result := a0;
end if;
when mal_vector =>
if a0.seq_val'length = 0 then
new_nil(result);
else
new_seq_obj(mal_list, a0.seq_val, result);
end if;
when mal_nil =>
new_nil(result);
when others =>
new_string("seq requires string or list or vector or nil", err);
end case;
end procedure fn_seq;
procedure fn_meta(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable meta_val: mal_val_ptr;
begin
meta_val := args.seq_val(0).meta_val;
if meta_val = null then
new_nil(result);
else
result := meta_val;
end if;
end procedure fn_meta;
procedure fn_with_meta(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable a0: mal_val_ptr := args.seq_val(0);
begin
result := new mal_val'(val_type => a0.val_type, number_val => a0.number_val, string_val => a0.string_val, seq_val => a0.seq_val, func_val => a0.func_val, meta_val => args.seq_val(1));
end procedure fn_with_meta;
procedure fn_atom(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
new_atom(args.seq_val(0), result);
end procedure fn_atom;
procedure fn_atom_q(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable a0: mal_val_ptr := args.seq_val(0);
begin
new_boolean(a0.val_type = mal_atom, result);
end procedure fn_atom_q;
procedure fn_deref(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable a0: mal_val_ptr := args.seq_val(0);
begin
result := a0.seq_val(0);
end procedure fn_deref;
procedure fn_reset(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable a0: mal_val_ptr := args.seq_val(0);
variable a1: mal_val_ptr := args.seq_val(1);
begin
a0.seq_val(0) := a1;
result := a1;
end procedure fn_reset;
procedure eval_native_func(func_sym: inout mal_val_ptr; args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable f: line;
begin
if func_sym.val_type /= mal_nativefn then
new_string("not a native function!", err);
return;
end if;
f := func_sym.string_val;
if f.all = "=" then fn_equal(args, result, err);
elsif f.all = "throw" then fn_throw(args, result, err);
elsif f.all = "nil?" then fn_nil_q(args, result, err);
elsif f.all = "true?" then fn_true_q(args, result, err);
elsif f.all = "false?" then fn_false_q(args, result, err);
elsif f.all = "string?" then fn_string_q(args, result, err);
elsif f.all = "symbol" then fn_symbol(args, result, err);
elsif f.all = "symbol?" then fn_symbol_q(args, result, err);
elsif f.all = "keyword" then fn_keyword(args, result, err);
elsif f.all = "keyword?" then fn_keyword_q(args, result, err);
elsif f.all = "number?" then fn_number_q(args, result, err);
elsif f.all = "fn?" then fn_function_q(args, result, err);
elsif f.all = "macro?" then fn_macro_q(args, result, err);
elsif f.all = "pr-str" then fn_pr_str(args, result, err);
elsif f.all = "str" then fn_str(args, result, err);
elsif f.all = "prn" then fn_prn(args, result, err);
elsif f.all = "println" then fn_println(args, result, err);
elsif f.all = "read-string" then fn_read_string(args, result, err);
elsif f.all = "readline" then fn_readline(args, result, err);
elsif f.all = "slurp" then fn_slurp(args, result, err);
elsif f.all = "<" then fn_lt(args, result, err);
elsif f.all = "<=" then fn_lte(args, result, err);
elsif f.all = ">" then fn_gt(args, result, err);
elsif f.all = ">=" then fn_gte(args, result, err);
elsif f.all = "+" then fn_add(args, result, err);
elsif f.all = "-" then fn_sub(args, result, err);
elsif f.all = "*" then fn_mul(args, result, err);
elsif f.all = "/" then fn_div(args, result, err);
elsif f.all = "time-ms" then fn_time_ms(args, result, err);
elsif f.all = "list" then fn_list(args, result, err);
elsif f.all = "list?" then fn_list_q(args, result, err);
elsif f.all = "vector" then fn_vector(args, result, err);
elsif f.all = "vector?" then fn_vector_q(args, result, err);
elsif f.all = "hash-map" then fn_hash_map(args, result, err);
elsif f.all = "map?" then fn_map_q(args, result, err);
elsif f.all = "assoc" then fn_assoc(args, result, err);
elsif f.all = "dissoc" then fn_dissoc(args, result, err);
elsif f.all = "get" then fn_get(args, result, err);
elsif f.all = "contains?" then fn_contains_q(args, result, err);
elsif f.all = "keys" then fn_keys(args, result, err);
elsif f.all = "vals" then fn_vals(args, result, err);
elsif f.all = "sequential?" then fn_sequential_q(args, result, err);
elsif f.all = "cons" then fn_cons(args, result, err);
elsif f.all = "concat" then fn_concat(args, result, err);
elsif f.all = "nth" then fn_nth(args, result, err);
elsif f.all = "first" then fn_first(args, result, err);
elsif f.all = "rest" then fn_rest(args, result, err);
elsif f.all = "empty?" then fn_empty_q(args, result, err);
elsif f.all = "count" then fn_count(args, result, err);
elsif f.all = "conj" then fn_conj(args, result, err);
elsif f.all = "seq" then fn_seq(args, result, err);
elsif f.all = "meta" then fn_meta(args, result, err);
elsif f.all = "with-meta" then fn_with_meta(args, result, err);
elsif f.all = "atom" then fn_atom(args, result, err);
elsif f.all = "atom?" then fn_atom_q(args, result, err);
elsif f.all = "deref" then fn_deref(args, result, err);
elsif f.all = "reset!" then fn_reset(args, result, err);
else
result := null;
end if;
end procedure eval_native_func;
procedure define_core_function(e: inout env_ptr; func_name: in string) is
variable sym: mal_val_ptr;
variable fn: mal_val_ptr;
begin
new_symbol(func_name, sym);
new_nativefn(func_name, fn);
env_set(e, sym, fn);
end procedure define_core_function;
procedure define_core_functions(e: inout env_ptr) is
begin
define_core_function(e, "=");
define_core_function(e, "throw");
define_core_function(e, "nil?");
define_core_function(e, "true?");
define_core_function(e, "false?");
define_core_function(e, "string?");
define_core_function(e, "symbol");
define_core_function(e, "symbol?");
define_core_function(e, "keyword");
define_core_function(e, "keyword?");
define_core_function(e, "number?");
define_core_function(e, "fn?");
define_core_function(e, "macro?");
define_core_function(e, "pr-str");
define_core_function(e, "str");
define_core_function(e, "prn");
define_core_function(e, "println");
define_core_function(e, "read-string");
define_core_function(e, "readline");
define_core_function(e, "slurp");
define_core_function(e, "<");
define_core_function(e, "<=");
define_core_function(e, ">");
define_core_function(e, ">=");
define_core_function(e, "+");
define_core_function(e, "-");
define_core_function(e, "*");
define_core_function(e, "/");
define_core_function(e, "time-ms");
define_core_function(e, "list");
define_core_function(e, "list?");
define_core_function(e, "vector");
define_core_function(e, "vector?");
define_core_function(e, "hash-map");
define_core_function(e, "map?");
define_core_function(e, "assoc");
define_core_function(e, "dissoc");
define_core_function(e, "get");
define_core_function(e, "contains?");
define_core_function(e, "keys");
define_core_function(e, "vals");
define_core_function(e, "sequential?");
define_core_function(e, "cons");
define_core_function(e, "concat");
define_core_function(e, "nth");
define_core_function(e, "first");
define_core_function(e, "rest");
define_core_function(e, "empty?");
define_core_function(e, "count");
define_core_function(e, "apply"); -- implemented in the stepN_XXX files
define_core_function(e, "map"); -- implemented in the stepN_XXX files
define_core_function(e, "conj");
define_core_function(e, "seq");
define_core_function(e, "meta");
define_core_function(e, "with-meta");
define_core_function(e, "atom");
define_core_function(e, "atom?");
define_core_function(e, "deref");
define_core_function(e, "reset!");
define_core_function(e, "swap!"); -- implemented in the stepN_XXX files
end procedure define_core_functions;
end package body core;
| mpl-2.0 | 62fa87a0ab1a257f67a5d96af8e496d5 | 0.637062 | 3.012395 | false | false | false | false |
dummylink/plnk_fpga-stack | Examples/xilinx_microblaze/avnet_lx9/pcores/plb_powerlink_v1_00_a/hdl/vhdl/plb_powerlink.vhd | 2 | 92,839 | -------------------------------------------------------------------------------
-- Entity : plb_powerlink
-------------------------------------------------------------------------------
--
-- (c) B&R, 2012
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
-- Design unit header --
--
-- This is the toplevel file for using the POWERLINK IP-Core
-- with Xilinx PLB V4.6.
--
-------------------------------------------------------------------------------
--
-- 2011-09-13 V0.01 zelenkaj First version
-- 2011-11-24 V0.02 mairt added slave interface for pdi pcp and pdi ap
-- 2011-11-26 V0.03 mairt added slave interface for simpleIO
-- 2011-12-02 V0.04 zelenkaj Exchanged IOs with _I, _O and _T
-- 2011-12-06 V0.05 zelenkaj Changed instance names
-- 2011-12-07 V0.06 zelenkaj Fixed address assignments for PDI PCP/AP
-- 2011-12-16 V0.07 mairt added TX/RX burst size feature
-- 2012-01-19 V0.08 zelenkaj Added bus to core clock ration feature
-- 2012-01-26 V0.09 zelenkaj Added number of SMI generic feature
-- 2012-01-16 V0.10 zelenkaj Replace plb_* with ipif_master_handler
-- 2012-01-27 V0.20 zelenkaj Incremented PdiRev
-- 2012-02-01 V0.21 zelenkaj Added attributes and RMII clk out
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.math_real.log2;
use ieee.math_real.ceil;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library plbv46_slave_single_v1_01_a;
use plbv46_slave_single_v1_01_a.plbv46_slave_single;
-- other libraries declarations
library PLBV46_MASTER_BURST_V1_01_A;
library PLBV46_SLAVE_SINGLE_V1_01_A;
entity plb_powerlink is
generic(
-- general
C_GEN_PDI : boolean := false;
C_GEN_PAR_IF : boolean := false;
C_GEN_SPI_IF : boolean := false;
C_GEN_PLB_BUS_IF : boolean := false;
C_GEN_SIMPLE_IO : boolean := false;
-- openMAC
C_MAC_PKT_SIZE : integer := 1024;
C_MAC_PKT_SIZE_LOG2 : integer := 10;
C_MAC_RX_BUFFERS : integer := 16;
C_USE_RMII : boolean := false;
C_TX_INT_PKT : boolean := false;
C_RX_INT_PKT : boolean := false;
C_USE_2ND_PHY : boolean := true;
C_NUM_SMI : integer range 1 to 2 := 2;
--pdi
C_PDI_GEN_ASYNC_BUF_0 : boolean := true;
C_PDI_ASYNC_BUF_0 : integer := 50;
C_PDI_GEN_ASYNC_BUF_1 : boolean := true;
C_PDI_ASYNC_BUF_1 : integer := 50;
C_PDI_GEN_LED : boolean := false;
C_PDI_GEN_TIME_SYNC : boolean := true;
C_PDI_GEN_SECOND_TIMER : boolean := false;
C_PDI_GEN_EVENT : boolean := true;
--global pdi and mac
C_NUM_RPDO : integer := 3;
C_RPDO_0_BUF_SIZE : integer := 100;
C_RPDO_1_BUF_SIZE : integer := 100;
C_RPDO_2_BUF_SIZE : integer := 100;
C_NUM_TPDO : integer := 1;
C_TPDO_BUF_SIZE : integer := 100;
-- pap
C_PAP_DATA_WIDTH : integer := 16;
--C_PAP_BIG_END : boolean := false;
C_PAP_LOW_ACT : boolean := false;
-- spi
C_SPI_CPOL : boolean := false;
C_SPI_CPHA : boolean := false;
--C_SPI_BIG_END : boolean := false;
-- simpleIO
C_PIO_VAL_LENGTH : integer := 50;
-- debug
C_OBSERVER_ENABLE : boolean := false;
-- PDI AP PLB Slave
C_PDI_AP_BASEADDR : std_logic_vector := X"00000000";
C_PDI_AP_HIGHADDR : std_logic_vector := X"000FFFFF";
C_PDI_AP_NUM_MASTERS : INTEGER := 1;
C_PDI_AP_PLB_AWIDTH : INTEGER := 32;
C_PDI_AP_PLB_DWIDTH : INTEGER := 32;
C_PDI_AP_PLB_MID_WIDTH : INTEGER := 1;
C_PDI_AP_PLB_P2P : INTEGER := 0;
C_PDI_AP_PLB_NUM_MASTERS : INTEGER := 1;
C_PDI_AP_PLB_NATIVE_DWIDTH : INTEGER := 32;
C_PDI_AP_PLB_SUPPORT_BURSTS : INTEGER := 0;
-- PDI AP PLB Slave
C_SMP_PCP_BASEADDR : std_logic_vector := X"00000000";
C_SMP_PCP_HIGHADDR : std_logic_vector := X"000FFFFF";
C_SMP_PCP_NUM_MASTERS : INTEGER := 1;
C_SMP_PCP_PLB_AWIDTH : INTEGER := 32;
C_SMP_PCP_PLB_DWIDTH : INTEGER := 32;
C_SMP_PCP_PLB_MID_WIDTH : INTEGER := 1;
C_SMP_PCP_PLB_P2P : INTEGER := 0;
C_SMP_PCP_PLB_NUM_MASTERS : INTEGER := 1;
C_SMP_PCP_PLB_NATIVE_DWIDTH : INTEGER := 32;
C_SMP_PCP_PLB_SUPPORT_BURSTS : INTEGER := 0;
-- PDI PCP PLB Slave
C_PDI_PCP_BASEADDR : std_logic_vector := X"00000000";
C_PDI_PCP_HIGHADDR : std_logic_vector := X"000FFFFF";
C_PDI_PCP_NUM_MASTERS : INTEGER := 1;
C_PDI_PCP_PLB_AWIDTH : INTEGER := 32;
C_PDI_PCP_PLB_DWIDTH : INTEGER := 32;
C_PDI_PCP_PLB_MID_WIDTH : INTEGER := 1;
C_PDI_PCP_PLB_P2P : INTEGER := 0;
C_PDI_PCP_PLB_NUM_MASTERS : INTEGER := 1;
C_PDI_PCP_PLB_NATIVE_DWIDTH : INTEGER := 32;
C_PDI_PCP_PLB_SUPPORT_BURSTS : INTEGER := 0;
-- openMAC CMP PLB Slave
C_MAC_PKT_BASEADDR : std_logic_vector := X"00000000";
C_MAC_PKT_HIGHADDR : std_logic_vector := X"000FFFFF";
C_MAC_PKT_NUM_MASTERS : INTEGER := 1;
C_MAC_PKT_PLB_AWIDTH : INTEGER := 32;
C_MAC_PKT_PLB_DWIDTH : INTEGER := 32;
C_MAC_PKT_PLB_MID_WIDTH : INTEGER := 1;
C_MAC_PKT_PLB_P2P : INTEGER := 0;
C_MAC_PKT_PLB_NUM_MASTERS : INTEGER := 1;
C_MAC_PKT_PLB_NATIVE_DWIDTH : INTEGER := 32;
C_MAC_PKT_PLB_SUPPORT_BURSTS : INTEGER := 0;
-- openMAC DMA PLB Master
C_MAC_DMA_PLB_AWIDTH : INTEGER := 32;
C_MAC_DMA_PLB_DWIDTH : INTEGER := 32;
C_MAC_DMA_PLB_NATIVE_DWIDTH : INTEGER := 32;
C_MAC_DMA_BURST_SIZE_RX : INTEGER := 8; --in bytes
C_MAC_DMA_BURST_SIZE_TX : INTEGER := 8; --in bytes
C_MAC_DMA_FIFO_SIZE_RX : INTEGER := 32; --in bytes
C_MAC_DMA_FIFO_SIZE_TX : INTEGER := 32; --in bytes
-- openMAC REG PLB Slave
C_MAC_REG_BASEADDR : std_logic_vector := X"00000000";
C_MAC_REG_HIGHADDR : std_logic_vector := X"0000FFFF";
C_MAC_CMP_BASEADDR : std_logic_vector := X"00000000";
C_MAC_CMP_HIGHADDR : std_logic_vector := X"0000FFFF";
C_MAC_REG_BUS2CORE_CLK_RATIO : integer := 2;
C_MAC_REG_NUM_MASTERS : INTEGER := 1;
C_MAC_REG_PLB_AWIDTH : INTEGER := 32;
C_MAC_REG_PLB_DWIDTH : INTEGER := 32;
C_MAC_REG_PLB_MID_WIDTH : INTEGER := 1;
C_MAC_REG_PLB_P2P : INTEGER := 0;
C_MAC_REG_PLB_NUM_MASTERS : INTEGER := 1;
C_MAC_REG_PLB_NATIVE_DWIDTH : INTEGER := 32;
C_MAC_REG_PLB_SUPPORT_BURSTS : INTEGER := 0
);
port(
MAC_DMA_Clk : in std_logic;
MAC_DMA_MAddrAck : in std_logic;
MAC_DMA_MBusy : in std_logic;
MAC_DMA_MIRQ : in std_logic;
MAC_DMA_MRdBTerm : in std_logic;
MAC_DMA_MRdDAck : in std_logic;
MAC_DMA_MRdErr : in std_logic;
MAC_DMA_MRearbitrate : in std_logic;
MAC_DMA_MTimeout : in std_logic;
MAC_DMA_MWrBTerm : in std_logic;
MAC_DMA_MWrDAck : in std_logic;
MAC_DMA_MWrErr : in std_logic;
MAC_DMA_Rst : in std_logic;
MAC_PKT_Clk : in std_logic;
MAC_PKT_PAValid : in std_logic;
MAC_PKT_RNW : in std_logic;
MAC_PKT_Rst : in std_logic;
MAC_PKT_SAValid : in std_logic;
MAC_PKT_abort : in std_logic;
MAC_PKT_busLock : in std_logic;
MAC_PKT_lockErr : in std_logic;
MAC_PKT_rdBurst : in std_logic;
MAC_PKT_rdPendReq : in std_logic;
MAC_PKT_rdPrim : in std_logic;
MAC_PKT_wrBurst : in std_logic;
MAC_PKT_wrPendReq : in std_logic;
MAC_PKT_wrPrim : in std_logic;
MAC_REG_Clk : in std_logic;
MAC_REG_PAValid : in std_logic;
MAC_REG_RNW : in std_logic;
MAC_REG_Rst : in std_logic;
MAC_REG_SAValid : in std_logic;
MAC_REG_abort : in std_logic;
MAC_REG_busLock : in std_logic;
MAC_REG_lockErr : in std_logic;
MAC_REG_rdBurst : in std_logic;
MAC_REG_rdPendReq : in std_logic;
MAC_REG_rdPrim : in std_logic;
MAC_REG_wrBurst : in std_logic;
MAC_REG_wrPendReq : in std_logic;
MAC_REG_wrPrim : in std_logic;
PDI_AP_Clk : in std_logic;
PDI_AP_PAValid : in std_logic;
PDI_AP_RNW : in std_logic;
PDI_AP_Rst : in std_logic;
PDI_AP_SAValid : in std_logic;
PDI_AP_abort : in std_logic;
PDI_AP_busLock : in std_logic;
PDI_AP_lockErr : in std_logic;
PDI_AP_rdBurst : in std_logic;
PDI_AP_rdPendReq : in std_logic;
PDI_AP_rdPrim : in std_logic;
PDI_AP_wrBurst : in std_logic;
PDI_AP_wrPendReq : in std_logic;
PDI_AP_wrPrim : in std_logic;
PDI_PCP_Clk : in std_logic;
PDI_PCP_PAValid : in std_logic;
PDI_PCP_RNW : in std_logic;
PDI_PCP_Rst : in std_logic;
PDI_PCP_SAValid : in std_logic;
PDI_PCP_abort : in std_logic;
PDI_PCP_busLock : in std_logic;
PDI_PCP_lockErr : in std_logic;
PDI_PCP_rdBurst : in std_logic;
PDI_PCP_rdPendReq : in std_logic;
PDI_PCP_rdPrim : in std_logic;
PDI_PCP_wrBurst : in std_logic;
PDI_PCP_wrPendReq : in std_logic;
PDI_PCP_wrPrim : in std_logic;
SMP_PCP_Clk : in std_logic;
SMP_PCP_PAValid : in std_logic;
SMP_PCP_RNW : in std_logic;
SMP_PCP_Rst : in std_logic;
SMP_PCP_SAValid : in std_logic;
SMP_PCP_abort : in std_logic;
SMP_PCP_busLock : in std_logic;
SMP_PCP_lockErr : in std_logic;
SMP_PCP_rdBurst : in std_logic;
SMP_PCP_rdPendReq : in std_logic;
SMP_PCP_rdPrim : in std_logic;
SMP_PCP_wrBurst : in std_logic;
SMP_PCP_wrPendReq : in std_logic;
SMP_PCP_wrPrim : in std_logic;
clk100 : in std_logic;
clk50 : in std_logic;
pap_cs : in std_logic;
pap_cs_n : in std_logic;
pap_rd : in std_logic;
pap_rd_n : in std_logic;
pap_wr : in std_logic;
pap_wr_n : in std_logic;
phy0_RxDv : in std_logic;
phy0_RxErr : in std_logic;
phy0_SMIDat_I : in std_logic;
phy0_link : in std_logic;
phy1_RxDv : in std_logic;
phy1_RxErr : in std_logic;
phy1_SMIDat_I : in std_logic;
phy1_link : in std_logic;
phyMii0_RxClk : in std_logic;
phyMii0_RxDv : in std_logic;
phyMii0_RxEr : in std_logic;
phyMii0_TxClk : in std_logic;
phyMii1_RxClk : in std_logic;
phyMii1_RxDv : in std_logic;
phyMii1_RxEr : in std_logic;
phyMii1_TxClk : in std_logic;
phy_SMIDat_I : in std_logic;
spi_clk : in std_logic;
spi_mosi : in std_logic;
spi_sel_n : in std_logic;
MAC_DMA_MRdDBus : in std_logic_vector(0 to C_MAC_DMA_PLB_DWIDTH-1);
MAC_DMA_MRdWdAddr : in std_logic_vector(0 to 3);
MAC_DMA_MSSize : in std_logic_vector(0 to 1);
MAC_PKT_ABus : in std_logic_vector(0 to 31);
MAC_PKT_BE : in std_logic_vector(0 to (C_MAC_PKT_PLB_DWIDTH/8)-1);
MAC_PKT_MSize : in std_logic_vector(0 to 1);
MAC_PKT_TAttribute : in std_logic_vector(0 to 15);
MAC_PKT_UABus : in std_logic_vector(0 to 31);
MAC_PKT_masterID : in std_logic_vector(0 to C_MAC_PKT_PLB_MID_WIDTH-1);
MAC_PKT_rdPendPri : in std_logic_vector(0 to 1);
MAC_PKT_reqPri : in std_logic_vector(0 to 1);
MAC_PKT_size : in std_logic_vector(0 to 3);
MAC_PKT_type : in std_logic_vector(0 to 2);
MAC_PKT_wrDBus : in std_logic_vector(0 to C_MAC_PKT_PLB_DWIDTH-1);
MAC_PKT_wrPendPri : in std_logic_vector(0 to 1);
MAC_REG_ABus : in std_logic_vector(0 to 31);
MAC_REG_BE : in std_logic_vector(0 to (C_MAC_REG_PLB_DWIDTH / 8) - 1);
MAC_REG_MSize : in std_logic_vector(0 to 1);
MAC_REG_TAttribute : in std_logic_vector(0 to 15);
MAC_REG_UABus : in std_logic_vector(0 to 31);
MAC_REG_masterID : in std_logic_vector(0 to C_MAC_REG_PLB_MID_WIDTH - 1);
MAC_REG_rdPendPri : in std_logic_vector(0 to 1);
MAC_REG_reqPri : in std_logic_vector(0 to 1);
MAC_REG_size : in std_logic_vector(0 to 3);
MAC_REG_type : in std_logic_vector(0 to 2);
MAC_REG_wrDBus : in std_logic_vector(0 to C_MAC_REG_PLB_DWIDTH - 1);
MAC_REG_wrPendPri : in std_logic_vector(0 to 1);
PDI_AP_ABus : in std_logic_vector(0 to 31);
PDI_AP_BE : in std_logic_vector(0 to (C_PDI_AP_PLB_DWIDTH/8)-1);
PDI_AP_MSize : in std_logic_vector(0 to 1);
PDI_AP_TAttribute : in std_logic_vector(0 to 15);
PDI_AP_UABus : in std_logic_vector(0 to 31);
PDI_AP_masterID : in std_logic_vector(0 to C_PDI_AP_PLB_MID_WIDTH-1);
PDI_AP_rdPendPri : in std_logic_vector(0 to 1);
PDI_AP_reqPri : in std_logic_vector(0 to 1);
PDI_AP_size : in std_logic_vector(0 to 3);
PDI_AP_type : in std_logic_vector(0 to 2);
PDI_AP_wrDBus : in std_logic_vector(0 to C_PDI_AP_PLB_DWIDTH-1);
PDI_AP_wrPendPri : in std_logic_vector(0 to 1);
PDI_PCP_ABus : in std_logic_vector(0 to 31);
PDI_PCP_BE : in std_logic_vector(0 to (C_PDI_PCP_PLB_DWIDTH/8)-1);
PDI_PCP_MSize : in std_logic_vector(0 to 1);
PDI_PCP_TAttribute : in std_logic_vector(0 to 15);
PDI_PCP_UABus : in std_logic_vector(0 to 31);
PDI_PCP_masterID : in std_logic_vector(0 to C_PDI_PCP_PLB_MID_WIDTH-1);
PDI_PCP_rdPendPri : in std_logic_vector(0 to 1);
PDI_PCP_reqPri : in std_logic_vector(0 to 1);
PDI_PCP_size : in std_logic_vector(0 to 3);
PDI_PCP_type : in std_logic_vector(0 to 2);
PDI_PCP_wrDBus : in std_logic_vector(0 to C_PDI_PCP_PLB_DWIDTH-1);
PDI_PCP_wrPendPri : in std_logic_vector(0 to 1);
SMP_PCP_ABus : in std_logic_vector(0 to 31);
SMP_PCP_BE : in std_logic_vector(0 to (C_SMP_PCP_PLB_DWIDTH/8)-1);
SMP_PCP_MSize : in std_logic_vector(0 to 1);
SMP_PCP_TAttribute : in std_logic_vector(0 to 15);
SMP_PCP_UABus : in std_logic_vector(0 to 31);
SMP_PCP_masterID : in std_logic_vector(0 to C_SMP_PCP_PLB_MID_WIDTH-1);
SMP_PCP_rdPendPri : in std_logic_vector(0 to 1);
SMP_PCP_reqPri : in std_logic_vector(0 to 1);
SMP_PCP_size : in std_logic_vector(0 to 3);
SMP_PCP_type : in std_logic_vector(0 to 2);
SMP_PCP_wrDBus : in std_logic_vector(0 to C_SMP_PCP_PLB_DWIDTH-1);
SMP_PCP_wrPendPri : in std_logic_vector(0 to 1);
pap_addr : in std_logic_vector(15 downto 0);
pap_be : in std_logic_vector(C_PAP_DATA_WIDTH/8-1 downto 0);
pap_be_n : in std_logic_vector(C_PAP_DATA_WIDTH/8-1 downto 0);
pap_data_I : in std_logic_vector(C_PAP_DATA_WIDTH-1 downto 0);
pap_gpio_I : in std_logic_vector(1 downto 0);
phy0_RxDat : in std_logic_vector(1 downto 0);
phy1_RxDat : in std_logic_vector(1 downto 0);
phyMii0_RxDat : in std_logic_vector(3 downto 0);
phyMii1_RxDat : in std_logic_vector(3 downto 0);
pio_pconfig : in std_logic_vector(3 downto 0);
pio_portInLatch : in std_logic_vector(3 downto 0);
pio_portio_I : in std_logic_vector(31 downto 0);
MAC_DMA_RNW : out std_logic;
MAC_DMA_abort : out std_logic;
MAC_DMA_busLock : out std_logic;
MAC_DMA_error : out std_logic;
MAC_DMA_lockErr : out std_logic;
MAC_DMA_rdBurst : out std_logic;
MAC_DMA_request : out std_logic;
MAC_DMA_wrBurst : out std_logic;
MAC_PKT_addrAck : out std_logic;
MAC_PKT_rdBTerm : out std_logic;
MAC_PKT_rdComp : out std_logic;
MAC_PKT_rdDAck : out std_logic;
MAC_PKT_rearbitrate : out std_logic;
MAC_PKT_wait : out std_logic;
MAC_PKT_wrBTerm : out std_logic;
MAC_PKT_wrComp : out std_logic;
MAC_PKT_wrDAck : out std_logic;
MAC_REG_addrAck : out std_logic;
MAC_REG_rdBTerm : out std_logic;
MAC_REG_rdComp : out std_logic;
MAC_REG_rdDAck : out std_logic;
MAC_REG_rearbitrate : out std_logic;
MAC_REG_wait : out std_logic;
MAC_REG_wrBTerm : out std_logic;
MAC_REG_wrComp : out std_logic;
MAC_REG_wrDAck : out std_logic;
PDI_AP_addrAck : out std_logic;
PDI_AP_rdBTerm : out std_logic;
PDI_AP_rdComp : out std_logic;
PDI_AP_rdDAck : out std_logic;
PDI_AP_rearbitrate : out std_logic;
PDI_AP_wait : out std_logic;
PDI_AP_wrBTerm : out std_logic;
PDI_AP_wrComp : out std_logic;
PDI_AP_wrDAck : out std_logic;
PDI_PCP_addrAck : out std_logic;
PDI_PCP_rdBTerm : out std_logic;
PDI_PCP_rdComp : out std_logic;
PDI_PCP_rdDAck : out std_logic;
PDI_PCP_rearbitrate : out std_logic;
PDI_PCP_wait : out std_logic;
PDI_PCP_wrBTerm : out std_logic;
PDI_PCP_wrComp : out std_logic;
PDI_PCP_wrDAck : out std_logic;
SMP_PCP_addrAck : out std_logic;
SMP_PCP_rdBTerm : out std_logic;
SMP_PCP_rdComp : out std_logic;
SMP_PCP_rdDAck : out std_logic;
SMP_PCP_rearbitrate : out std_logic;
SMP_PCP_wait : out std_logic;
SMP_PCP_wrBTerm : out std_logic;
SMP_PCP_wrComp : out std_logic;
SMP_PCP_wrDAck : out std_logic;
ap_asyncIrq : out std_logic;
ap_asyncIrq_n : out std_logic;
ap_syncIrq : out std_logic;
ap_syncIrq_n : out std_logic;
led_error : out std_logic;
led_status : out std_logic;
mac_irq : out std_logic;
pap_ack : out std_logic;
pap_ack_n : out std_logic;
pap_data_T : out std_logic;
phy0_Rst_n : out std_logic;
phy0_SMIClk : out std_logic;
phy0_SMIDat_O : out std_logic;
phy0_SMIDat_T : out std_logic;
phy0_TxEn : out std_logic;
phy0_clk : out std_logic;
phy1_Rst_n : out std_logic;
phy1_SMIClk : out std_logic;
phy1_SMIDat_O : out std_logic;
phy1_SMIDat_T : out std_logic;
phy1_TxEn : out std_logic;
phy1_clk : out std_logic;
phyMii0_TxEn : out std_logic;
phyMii0_TxEr : out std_logic;
phyMii1_TxEn : out std_logic;
phyMii1_TxEr : out std_logic;
phy_Rst_n : out std_logic;
phy_SMIClk : out std_logic;
phy_SMIDat_O : out std_logic;
phy_SMIDat_T : out std_logic;
pio_operational : out std_logic;
spi_miso : out std_logic;
tcp_irq : out std_logic;
MAC_DMA_ABus : out std_logic_vector(0 to 31);
MAC_DMA_BE : out std_logic_vector(0 to (C_MAC_DMA_PLB_DWIDTH/8)-1);
MAC_DMA_MSize : out std_logic_vector(0 to 1);
MAC_DMA_TAttribute : out std_logic_vector(0 to 15);
MAC_DMA_UABus : out std_logic_vector(0 to 31);
MAC_DMA_priority : out std_logic_vector(0 to 1);
MAC_DMA_size : out std_logic_vector(0 to 3);
MAC_DMA_type : out std_logic_vector(0 to 2);
MAC_DMA_wrDBus : out std_logic_vector(0 to C_MAC_DMA_PLB_DWIDTH-1);
MAC_PKT_MBusy : out std_logic_vector(0 to C_MAC_PKT_NUM_MASTERS-1);
MAC_PKT_MIRQ : out std_logic_vector(0 to C_MAC_PKT_NUM_MASTERS-1);
MAC_PKT_MRdErr : out std_logic_vector(0 to C_MAC_PKT_NUM_MASTERS-1);
MAC_PKT_MWrErr : out std_logic_vector(0 to C_MAC_PKT_NUM_MASTERS-1);
MAC_PKT_SSize : out std_logic_vector(0 to 1);
MAC_PKT_rdDBus : out std_logic_vector(0 to C_MAC_PKT_PLB_DWIDTH-1);
MAC_PKT_rdWdAddr : out std_logic_vector(0 to 3);
MAC_REG_MBusy : out std_logic_vector(0 to C_MAC_REG_NUM_MASTERS-1);
MAC_REG_MIRQ : out std_logic_vector(0 to C_MAC_REG_NUM_MASTERS-1);
MAC_REG_MRdErr : out std_logic_vector(0 to C_MAC_REG_NUM_MASTERS-1);
MAC_REG_MWrErr : out std_logic_vector(0 to C_MAC_REG_NUM_MASTERS-1);
MAC_REG_SSize : out std_logic_vector(0 to 1);
MAC_REG_rdDBus : out std_logic_vector(0 to C_MAC_REG_PLB_DWIDTH-1);
MAC_REG_rdWdAddr : out std_logic_vector(0 to 3);
PDI_AP_MBusy : out std_logic_vector(0 to C_PDI_AP_PLB_NUM_MASTERS-1);
PDI_AP_MIRQ : out std_logic_vector(0 to C_PDI_AP_PLB_NUM_MASTERS-1);
PDI_AP_MRdErr : out std_logic_vector(0 to C_PDI_AP_PLB_NUM_MASTERS-1);
PDI_AP_MWrErr : out std_logic_vector(0 to C_PDI_AP_PLB_NUM_MASTERS-1);
PDI_AP_SSize : out std_logic_vector(0 to 1);
PDI_AP_rdDBus : out std_logic_vector(0 to C_PDI_AP_PLB_DWIDTH-1);
PDI_AP_rdWdAddr : out std_logic_vector(0 to 3);
PDI_PCP_MBusy : out std_logic_vector(0 to C_PDI_PCP_NUM_MASTERS-1);
PDI_PCP_MIRQ : out std_logic_vector(0 to C_PDI_PCP_NUM_MASTERS-1);
PDI_PCP_MRdErr : out std_logic_vector(0 to C_PDI_PCP_NUM_MASTERS-1);
PDI_PCP_MWrErr : out std_logic_vector(0 to C_PDI_PCP_NUM_MASTERS-1);
PDI_PCP_SSize : out std_logic_vector(0 to 1);
PDI_PCP_rdDBus : out std_logic_vector(0 to C_PDI_PCP_PLB_DWIDTH-1);
PDI_PCP_rdWdAddr : out std_logic_vector(0 to 3);
SMP_PCP_MBusy : out std_logic_vector(0 to C_SMP_PCP_PLB_NUM_MASTERS-1);
SMP_PCP_MIRQ : out std_logic_vector(0 to C_SMP_PCP_PLB_NUM_MASTERS-1);
SMP_PCP_MRdErr : out std_logic_vector(0 to C_SMP_PCP_PLB_NUM_MASTERS-1);
SMP_PCP_MWrErr : out std_logic_vector(0 to C_SMP_PCP_PLB_NUM_MASTERS-1);
SMP_PCP_SSize : out std_logic_vector(0 to 1);
SMP_PCP_rdDBus : out std_logic_vector(0 to C_SMP_PCP_PLB_DWIDTH-1);
SMP_PCP_rdWdAddr : out std_logic_vector(0 to 3);
led_gpo : out std_logic_vector(7 downto 0);
led_opt : out std_logic_vector(1 downto 0);
led_phyAct : out std_logic_vector(1 downto 0);
led_phyLink : out std_logic_vector(1 downto 0);
pap_data_O : out std_logic_vector(C_PAP_DATA_WIDTH-1 downto 0);
pap_gpio_O : out std_logic_vector(1 downto 0);
pap_gpio_T : out std_logic_vector(1 downto 0);
phy0_TxDat : out std_logic_vector(1 downto 0);
phy1_TxDat : out std_logic_vector(1 downto 0);
phyMii0_TxDat : out std_logic_vector(3 downto 0);
phyMii1_TxDat : out std_logic_vector(3 downto 0);
pio_portOutValid : out std_logic_vector(3 downto 0);
pio_portio_O : out std_logic_vector(31 downto 0);
pio_portio_T : out std_logic_vector(31 downto 0);
test_port : out std_logic_vector(255 downto 0) := (others => '0')
);
-- Entity declarations --
-- Click here to add additional declarations --
attribute SIGIS : string;
-- Entity attributes --
attribute SIGIS of MAC_DMA_Clk : signal is "Clk";
attribute SIGIS of MAC_DMA_Rst : signal is "Rst";
attribute SIGIS of MAC_PKT_Clk : signal is "Clk";
attribute SIGIS of MAC_PKT_Rst : signal is "Rst";
attribute SIGIS of MAC_REG_Clk : signal is "Clk";
attribute SIGIS of MAC_REG_Rst : signal is "Rst";
attribute SIGIS of PDI_AP_Clk : signal is "Clk";
attribute SIGIS of PDI_AP_Rst : signal is "Rst";
attribute SIGIS of PDI_PCP_Clk : signal is "Clk";
attribute SIGIS of PDI_PCP_Rst : signal is "Rst";
attribute SIGIS of SMP_PCP_Clk : signal is "Clk";
attribute SIGIS of SMP_PCP_Rst : signal is "Rst";
attribute SIGIS of clk100 : signal is "Clk";
attribute SIGIS of clk50 : signal is "Clk";
attribute SIGIS of phy0_clk : signal is "Clk";
attribute SIGIS of phy1_clk : signal is "Clk";
end plb_powerlink;
architecture struct of plb_powerlink is
---- Architecture declarations -----
function get_max( a, b : integer) return integer is
begin
if a < b then
return b;
else
return a;
end if;
end get_max;
---- Component declarations -----
component ipif_master_handler
generic(
C_MAC_DMA_IPIF_AWIDTH : integer := 32;
C_MAC_DMA_IPIF_NATIVE_DWIDTH : integer := 32;
dma_highadr_g : integer := 31;
gen_rx_fifo_g : boolean := true;
gen_tx_fifo_g : boolean := true;
m_burstcount_width_g : integer := 4
);
port (
Bus2MAC_DMA_MstRd_d : in std_logic_vector(C_MAC_DMA_IPIF_NATIVE_DWIDTH-1 downto 0);
Bus2MAC_DMA_MstRd_eof_n : in std_logic := '1';
Bus2MAC_DMA_MstRd_rem : in std_logic_vector(C_MAC_DMA_IPIF_NATIVE_DWIDTH/8-1 downto 0);
Bus2MAC_DMA_MstRd_sof_n : in std_logic := '1';
Bus2MAC_DMA_MstRd_src_dsc_n : in std_logic := '1';
Bus2MAC_DMA_MstRd_src_rdy_n : in std_logic := '1';
Bus2MAC_DMA_MstWr_dst_dsc_n : in std_logic := '1';
Bus2MAC_DMA_MstWr_dst_rdy_n : in std_logic := '1';
Bus2MAC_DMA_Mst_CmdAck : in std_logic := '0';
Bus2MAC_DMA_Mst_Cmd_Timeout : in std_logic := '0';
Bus2MAC_DMA_Mst_Cmplt : in std_logic := '0';
Bus2MAC_DMA_Mst_Error : in std_logic := '0';
Bus2MAC_DMA_Mst_Rearbitrate : in std_logic := '0';
MAC_DMA_CLK : in std_logic;
MAC_DMA_Rst : in std_logic;
m_address : in std_logic_vector(dma_highadr_g downto 0);
m_burstcount : in std_logic_vector(m_burstcount_width_g-1 downto 0);
m_burstcounter : in std_logic_vector(m_burstcount_width_g-1 downto 0);
m_byteenable : in std_logic_vector(3 downto 0);
m_read : in std_logic := '0';
m_write : in std_logic := '0';
m_writedata : in std_logic_vector(31 downto 0);
MAC_DMA2Bus_MstRd_Req : out std_logic := '0';
MAC_DMA2Bus_MstRd_dst_dsc_n : out std_logic := '1';
MAC_DMA2Bus_MstRd_dst_rdy_n : out std_logic := '1';
MAC_DMA2Bus_MstWr_Req : out std_logic := '0';
MAC_DMA2Bus_MstWr_d : out std_logic_vector(C_MAC_DMA_IPIF_NATIVE_DWIDTH-1 downto 0);
MAC_DMA2Bus_MstWr_eof_n : out std_logic := '1';
MAC_DMA2Bus_MstWr_rem : out std_logic_vector(C_MAC_DMA_IPIF_NATIVE_DWIDTH/8-1 downto 0);
MAC_DMA2Bus_MstWr_sof_n : out std_logic := '1';
MAC_DMA2Bus_MstWr_src_dsc_n : out std_logic := '1';
MAC_DMA2Bus_MstWr_src_rdy_n : out std_logic := '1';
MAC_DMA2Bus_Mst_Addr : out std_logic_vector(C_MAC_DMA_IPIF_AWIDTH-1 downto 0);
MAC_DMA2Bus_Mst_BE : out std_logic_vector(C_MAC_DMA_IPIF_NATIVE_DWIDTH/8-1 downto 0);
MAC_DMA2Bus_Mst_Length : out std_logic_vector(11 downto 0);
MAC_DMA2Bus_Mst_Lock : out std_logic := '0';
MAC_DMA2Bus_Mst_Reset : out std_logic := '0';
MAC_DMA2Bus_Mst_Type : out std_logic := '0';
m_clk : out std_logic;
m_readdata : out std_logic_vector(31 downto 0);
m_readdatavalid : out std_logic := '0';
m_waitrequest : out std_logic := '1'
);
end component;
component openMAC_16to32conv
generic(
bus_address_width : integer := 10
);
port (
bus_address : in std_logic_vector(bus_address_width-1 downto 0);
bus_byteenable : in std_logic_vector(3 downto 0);
bus_read : in std_logic;
bus_select : in std_logic;
bus_write : in std_logic;
bus_writedata : in std_logic_vector(31 downto 0);
clk : in std_logic;
rst : in std_logic;
s_readdata : in std_logic_vector(15 downto 0);
s_waitrequest : in std_logic;
bus_ack_rd : out std_logic;
bus_ack_wr : out std_logic;
bus_readdata : out std_logic_vector(31 downto 0);
s_address : out std_logic_vector(bus_address_width-1 downto 0);
s_byteenable : out std_logic_vector(1 downto 0);
s_chipselect : out std_logic;
s_read : out std_logic;
s_write : out std_logic;
s_writedata : out std_logic_vector(15 downto 0)
);
end component;
component powerlink
generic(
Simulate : boolean := false;
endian_g : string := "little";
gNumSmi : integer range 1 to 2 := 2;
genABuf1_g : boolean := true;
genABuf2_g : boolean := true;
genEvent_g : boolean := false;
genInternalAp_g : boolean := true;
genIoBuf_g : boolean := true;
genLedGadget_g : boolean := false;
genOnePdiClkDomain_g : boolean := false;
genPdi_g : boolean := true;
genSimpleIO_g : boolean := false;
genSmiIO : boolean := true;
genSpiAp_g : boolean := false;
genTimeSync_g : boolean := false;
gen_dma_observer_g : boolean := true;
iAsyBuf1Size_g : integer := 100;
iAsyBuf2Size_g : integer := 100;
iBufSizeLOG2_g : integer := 10;
iBufSize_g : integer := 1024;
iPdiRev_g : integer := 21930;
iRpdo0BufSize_g : integer := 100;
iRpdo1BufSize_g : integer := 100;
iRpdo2BufSize_g : integer := 100;
iRpdos_g : integer := 3;
iTpdoBufSize_g : integer := 100;
iTpdos_g : integer := 1;
m_burstcount_const_g : boolean := true;
m_burstcount_width_g : integer := 4;
m_data_width_g : integer := 16;
m_rx_burst_size_g : integer := 16;
m_rx_fifo_size_g : integer := 16;
m_tx_burst_size_g : integer := 16;
m_tx_fifo_size_g : integer := 16;
papBigEnd_g : boolean := false;
papDataWidth_g : integer := 8;
papLowAct_g : boolean := false;
pioValLen_g : integer := 50;
spiBigEnd_g : boolean := false;
spiCPHA_g : boolean := false;
spiCPOL_g : boolean := false;
use2ndCmpTimer_g : boolean := true;
use2ndPhy_g : boolean := true;
useIntPacketBuf_g : boolean := true;
useRmii_g : boolean := true;
useRxIntPacketBuf_g : boolean := true
);
port (
ap_address : in std_logic_vector(12 downto 0);
ap_byteenable : in std_logic_vector(3 downto 0);
ap_chipselect : in std_logic;
ap_read : in std_logic;
ap_write : in std_logic;
ap_writedata : in std_logic_vector(31 downto 0);
clk50 : in std_logic;
clkAp : in std_logic;
clkEth : in std_logic;
clkPcp : in std_logic;
m_clk : in std_logic;
m_readdata : in std_logic_vector(m_data_width_g-1 downto 0) := (others => '0');
m_readdatavalid : in std_logic := '0';
m_waitrequest : in std_logic;
mac_address : in std_logic_vector(11 downto 0);
mac_byteenable : in std_logic_vector(1 downto 0);
mac_chipselect : in std_logic;
mac_read : in std_logic;
mac_write : in std_logic;
mac_writedata : in std_logic_vector(15 downto 0);
mbf_address : in std_logic_vector(ibufsizelog2_g-3 downto 0);
mbf_byteenable : in std_logic_vector(3 downto 0);
mbf_chipselect : in std_logic;
mbf_read : in std_logic;
mbf_write : in std_logic;
mbf_writedata : in std_logic_vector(31 downto 0);
pap_addr : in std_logic_vector(15 downto 0);
pap_be : in std_logic_vector(papDataWidth_g/8-1 downto 0);
pap_be_n : in std_logic_vector(papDataWidth_g/8-1 downto 0);
pap_cs : in std_logic;
pap_cs_n : in std_logic;
pap_data_I : in std_logic_vector(papDataWidth_g-1 downto 0) := (others => '0');
pap_gpio_I : in std_logic_vector(1 downto 0) := (others => '0');
pap_rd : in std_logic;
pap_rd_n : in std_logic;
pap_wr : in std_logic;
pap_wr_n : in std_logic;
pcp_address : in std_logic_vector(12 downto 0);
pcp_byteenable : in std_logic_vector(3 downto 0);
pcp_chipselect : in std_logic;
pcp_read : in std_logic;
pcp_write : in std_logic;
pcp_writedata : in std_logic_vector(31 downto 0);
phy0_RxDat : in std_logic_vector(1 downto 0);
phy0_RxDv : in std_logic;
phy0_RxErr : in std_logic;
phy0_SMIDat_I : in std_logic := '1';
phy0_link : in std_logic := '0';
phy1_RxDat : in std_logic_vector(1 downto 0) := (others => '0');
phy1_RxDv : in std_logic;
phy1_RxErr : in std_logic;
phy1_SMIDat_I : in std_logic := '1';
phy1_link : in std_logic := '0';
phyMii0_RxClk : in std_logic;
phyMii0_RxDat : in std_logic_vector(3 downto 0) := (others => '0');
phyMii0_RxDv : in std_logic;
phyMii0_RxEr : in std_logic;
phyMii0_TxClk : in std_logic;
phyMii1_RxClk : in std_logic;
phyMii1_RxDat : in std_logic_vector(3 downto 0) := (others => '0');
phyMii1_RxDv : in std_logic;
phyMii1_RxEr : in std_logic;
phyMii1_TxClk : in std_logic;
phy_SMIDat_I : in std_logic := '1';
pio_pconfig : in std_logic_vector(3 downto 0);
pio_portInLatch : in std_logic_vector(3 downto 0);
pio_portio_I : in std_logic_vector(31 downto 0) := (others => '0');
pkt_clk : in std_logic;
rst : in std_logic;
rstAp : in std_logic;
rstPcp : in std_logic;
smp_address : in std_logic;
smp_byteenable : in std_logic_vector(3 downto 0);
smp_read : in std_logic;
smp_write : in std_logic;
smp_writedata : in std_logic_vector(31 downto 0);
spi_clk : in std_logic;
spi_mosi : in std_logic;
spi_sel_n : in std_logic;
tcp_address : in std_logic_vector(1 downto 0);
tcp_byteenable : in std_logic_vector(3 downto 0);
tcp_chipselect : in std_logic;
tcp_read : in std_logic;
tcp_write : in std_logic;
tcp_writedata : in std_logic_vector(31 downto 0);
ap_asyncIrq : out std_logic := '0';
ap_asyncIrq_n : out std_logic := '1';
ap_irq : out std_logic := '0';
ap_irq_n : out std_logic := '1';
ap_readdata : out std_logic_vector(31 downto 0) := (others => '0');
ap_syncIrq : out std_logic := '0';
ap_syncIrq_n : out std_logic := '1';
ap_waitrequest : out std_logic;
led_error : out std_logic := '0';
led_gpo : out std_logic_vector(7 downto 0) := (others => '0');
led_opt : out std_logic_vector(1 downto 0) := (others => '0');
led_phyAct : out std_logic_vector(1 downto 0) := (others => '0');
led_phyLink : out std_logic_vector(1 downto 0) := (others => '0');
led_status : out std_logic := '0';
m_address : out std_logic_vector(29 downto 0) := (others => '0');
m_burstcount : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_burstcounter : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_byteenable : out std_logic_vector(m_data_width_g/8-1 downto 0) := (others => '0');
m_read : out std_logic := '0';
m_write : out std_logic := '0';
m_writedata : out std_logic_vector(m_data_width_g-1 downto 0) := (others => '0');
mac_irq : out std_logic := '0';
mac_readdata : out std_logic_vector(15 downto 0) := (others => '0');
mac_waitrequest : out std_logic;
mbf_readdata : out std_logic_vector(31 downto 0) := (others => '0');
mbf_waitrequest : out std_logic;
pap_ack : out std_logic := '0';
pap_ack_n : out std_logic := '1';
pap_data_O : out std_logic_vector(papDataWidth_g-1 downto 0);
pap_data_T : out std_logic;
pap_gpio_O : out std_logic_vector(1 downto 0);
pap_gpio_T : out std_logic_vector(1 downto 0);
pcp_readdata : out std_logic_vector(31 downto 0) := (others => '0');
pcp_waitrequest : out std_logic;
phy0_Rst_n : out std_logic := '1';
phy0_SMIClk : out std_logic := '0';
phy0_SMIDat_O : out std_logic;
phy0_SMIDat_T : out std_logic;
phy0_TxDat : out std_logic_vector(1 downto 0) := (others => '0');
phy0_TxEn : out std_logic := '0';
phy1_Rst_n : out std_logic := '1';
phy1_SMIClk : out std_logic := '0';
phy1_SMIDat_O : out std_logic;
phy1_SMIDat_T : out std_logic;
phy1_TxDat : out std_logic_vector(1 downto 0) := (others => '0');
phy1_TxEn : out std_logic := '0';
phyMii0_TxDat : out std_logic_vector(3 downto 0) := (others => '0');
phyMii0_TxEn : out std_logic := '0';
phyMii0_TxEr : out std_logic := '0';
phyMii1_TxDat : out std_logic_vector(3 downto 0) := (others => '0');
phyMii1_TxEn : out std_logic := '0';
phyMii1_TxEr : out std_logic := '0';
phy_Rst_n : out std_logic := '1';
phy_SMIClk : out std_logic := '0';
phy_SMIDat_O : out std_logic;
phy_SMIDat_T : out std_logic;
pio_operational : out std_logic := '0';
pio_portOutValid : out std_logic_vector(3 downto 0) := (others => '0');
pio_portio_O : out std_logic_vector(31 downto 0);
pio_portio_T : out std_logic_vector(31 downto 0);
smp_readdata : out std_logic_vector(31 downto 0) := (others => '0');
smp_waitrequest : out std_logic;
spi_miso : out std_logic := '0';
tcp_irq : out std_logic := '0';
tcp_readdata : out std_logic_vector(31 downto 0) := (others => '0');
tcp_waitrequest : out std_logic;
pap_data : inout std_logic_vector(papDataWidth_g-1 downto 0) := (others => '0');
pap_gpio : inout std_logic_vector(1 downto 0) := (others => '0');
phy0_SMIDat : inout std_logic := '1';
phy1_SMIDat : inout std_logic := '1';
phy_SMIDat : inout std_logic := '1';
pio_portio : inout std_logic_vector(31 downto 0) := (others => '0')
);
end component;
component plbv46_master_burst
generic(
C_FAMILY : string := "virtex5";
C_INHIBIT_CC_BLE_INCLUSION : integer range 0 to 1 := 0;
C_MPLB_AWIDTH : integer range 32 to 36 := 32;
C_MPLB_DWIDTH : integer range 32 to 128 := 32;
C_MPLB_NATIVE_DWIDTH : integer range 32 to 128 := 32;
C_MPLB_SMALLEST_SLAVE : integer range 32 to 128 := 32
);
port (
IP2Bus_MstRd_Req : in std_logic;
IP2Bus_MstRd_dst_dsc_n : in std_logic;
IP2Bus_MstRd_dst_rdy_n : in std_logic;
IP2Bus_MstWr_Req : in std_logic;
IP2Bus_MstWr_d : in std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH-1);
IP2Bus_MstWr_eof_n : in std_logic;
IP2Bus_MstWr_rem : in std_logic_vector(0 to (C_MPLB_NATIVE_DWIDTH/8)-1);
IP2Bus_MstWr_sof_n : in std_logic;
IP2Bus_MstWr_src_dsc_n : in std_logic;
IP2Bus_MstWr_src_rdy_n : in std_logic;
IP2Bus_Mst_Addr : in std_logic_vector(0 to C_MPLB_AWIDTH-1);
IP2Bus_Mst_BE : in std_logic_vector(0 to (C_MPLB_NATIVE_DWIDTH/8)-1);
IP2Bus_Mst_Length : in std_logic_vector(0 to 11);
IP2Bus_Mst_Lock : in std_logic;
IP2Bus_Mst_Reset : in std_logic;
IP2Bus_Mst_Type : in std_logic;
MPLB_Clk : in std_logic;
MPLB_Rst : in std_logic;
PLB_MAddrAck : in std_logic;
PLB_MBusy : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MRdDAck : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to C_MPLB_DWIDTH-1);
PLB_MRdErr : in std_logic;
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRearbitrate : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
PLB_MTimeout : in std_logic;
PLB_MWrBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MWrErr : in std_logic;
Bus2IP_MstRd_d : out std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH-1);
Bus2IP_MstRd_eof_n : out std_logic;
Bus2IP_MstRd_rem : out std_logic_vector(0 to (C_MPLB_NATIVE_DWIDTH/8)-1);
Bus2IP_MstRd_sof_n : out std_logic;
Bus2IP_MstRd_src_dsc_n : out std_logic;
Bus2IP_MstRd_src_rdy_n : out std_logic;
Bus2IP_MstWr_dst_dsc_n : out std_logic;
Bus2IP_MstWr_dst_rdy_n : out std_logic;
Bus2IP_Mst_CmdAck : out std_logic;
Bus2IP_Mst_Cmd_Timeout : out std_logic;
Bus2IP_Mst_Cmplt : out std_logic;
Bus2IP_Mst_Error : out std_logic;
Bus2IP_Mst_Rearbitrate : out std_logic;
MD_Error : out std_logic;
M_ABus : out std_logic_vector(0 to 31);
M_BE : out std_logic_vector(0 to (C_MPLB_DWIDTH/8)-1);
M_MSize : out std_logic_vector(0 to 1);
M_RNW : out std_logic;
M_TAttribute : out std_logic_vector(0 to 15);
M_UABus : out std_logic_vector(0 to 31);
M_abort : out std_logic;
M_busLock : out std_logic;
M_lockErr : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_rdBurst : out std_logic;
M_request : out std_logic;
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_wrBurst : out std_logic;
M_wrDBus : out std_logic_vector(0 to C_MPLB_DWIDTH-1)
);
end component;
component plbv46_slave_single
generic(
C_ARD_ADDR_RANGE_ARRAY : slv64_array_type := (X"0000_0000_7000_0000",X"0000_0000_7000_00FF",X"0000_0000_7000_0100",X"0000_0000_7000_01FF");
C_ARD_NUM_CE_ARRAY : integer_array_type := (1,8);
C_BUS2CORE_CLK_RATIO : integer range 1 to 2 := 1;
C_FAMILY : string := "virtex4";
C_INCLUDE_DPHASE_TIMER : integer range 0 to 1 := 1;
C_SIPIF_DWIDTH : integer range 32 to 32 := 32;
C_SPLB_AWIDTH : integer range 32 to 32 := 32;
C_SPLB_DWIDTH : integer range 32 to 128 := 32;
C_SPLB_MID_WIDTH : integer range 1 to 4 := 2;
C_SPLB_NUM_MASTERS : integer range 1 to 16 := 8;
C_SPLB_P2P : integer range 0 to 1 := 0
);
port (
IP2Bus_Data : in std_logic_vector(0 to C_SIPIF_DWIDTH-1);
IP2Bus_Error : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_WrAck : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_BE : in std_logic_vector(0 to (C_SPLB_DWIDTH/8)-1);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_PAValid : in std_logic;
PLB_RNW : in std_logic;
PLB_SAValid : in std_logic;
PLB_TAttribute : in std_logic_vector(0 to 15);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_lockErr : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
PLB_rdBurst : in std_logic;
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_rdPendReq : in std_logic;
PLB_rdPrim : in std_logic;
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_wrBurst : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_wrPendReq : in std_logic;
PLB_wrPrim : in std_logic;
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
Bus2IP_Addr : out std_logic_vector(0 to C_SPLB_AWIDTH-1);
Bus2IP_BE : out std_logic_vector(0 to (C_SIPIF_DWIDTH/8)-1);
Bus2IP_CS : out std_logic_vector(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
Bus2IP_Clk : out std_logic;
Bus2IP_Data : out std_logic_vector(0 to C_SIPIF_DWIDTH-1);
Bus2IP_RNW : out std_logic;
Bus2IP_RdCE : out std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
Bus2IP_Reset : out std_logic;
Bus2IP_WrCE : out std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_SSize : out std_logic_vector(0 to 1);
Sl_addrAck : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdDAck : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rearbitrate : out std_logic;
Sl_wait : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrDAck : out std_logic
);
end component;
---- Architecture declarations -----
constant C_FAMILY : string := "spartan6";
constant C_ADDR_PAD_ZERO : std_logic_vector(31 downto 0) := (others => '0');
-- openMAC REG PLB Slave
constant C_MAC_REG_BASE : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_MAC_REG_BASEADDR;
constant C_MAC_REG_HIGH : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_MAC_REG_HIGHADDR;
-- openMAC CMP PLB Slave
constant C_MAC_CMP_BASE : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_MAC_CMP_BASEADDR;
constant C_MAC_CMP_HIGH : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_MAC_CMP_HIGHADDR;
-- openMAC PKT PLB Slave
constant C_MAC_PKT_BASE : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_MAC_PKT_BASEADDR;
constant C_MAC_PKT_HIGH : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_MAC_PKT_HIGHADDR;
-- SimpleIO Slave
constant C_SMP_PCP_BASE : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_SMP_PCP_BASEADDR;
constant C_SMP_PCP_HIGH : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_SMP_PCP_HIGHADDR;
-- PDI PCP Slave
constant C_PDI_PCP_BASE : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_PDI_PCP_BASEADDR;
constant C_PDI_PCP_HIGH : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_PDI_PCP_HIGHADDR;
-- AP PCP Slave
constant C_PDI_AP_BASE : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_PDI_AP_BASEADDR;
constant C_PDI_AP_HIGH : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_PDI_AP_HIGHADDR;
-- POWERLINK IP-core
constant C_MAC_PKT_EN : boolean := C_TX_INT_PKT or C_RX_INT_PKT;
constant C_MAC_PKT_RX_EN : boolean := C_RX_INT_PKT;
constant C_DMA_EN : boolean := not C_TX_INT_PKT or not C_RX_INT_PKT;
constant C_PKT_BUF_EN : boolean := C_MAC_PKT_EN;
constant C_M_BURSTCOUNT_WIDTH : integer := integer(ceil(log2(real(get_max(C_MAC_DMA_BURST_SIZE_RX,C_MAC_DMA_BURST_SIZE_TX)/4)))) + 1; --in dwords
constant C_M_FIFO_SIZE_RX : integer := C_MAC_DMA_FIFO_SIZE_RX/4; --in dwords
constant C_M_FIFO_SIZE_TX : integer := C_MAC_DMA_FIFO_SIZE_TX/4; --in dwords
---- Constants -----
constant GND_CONSTANT : std_logic := '0';
---- Signal declarations used on the diagram ----
signal ap_chipselect : std_logic;
signal ap_read : std_logic;
signal ap_waitrequest : std_logic;
signal ap_write : std_logic;
signal Bus2MAC_CMP_Reset : std_logic;
signal Bus2MAC_DMA_MstRd_eof_n : std_logic;
signal Bus2MAC_DMA_MstRd_sof_n : std_logic;
signal Bus2MAC_DMA_MstRd_src_dsc_n : std_logic;
signal Bus2MAC_DMA_MstRd_src_rdy_n : std_logic;
signal Bus2MAC_DMA_MstWr_dst_dsc_n : std_logic;
signal Bus2MAC_DMA_MstWr_dst_rdy_n : std_logic;
signal Bus2MAC_DMA_Mst_CmdAck : std_logic;
signal Bus2MAC_DMA_Mst_Cmd_Timeout : std_logic;
signal Bus2MAC_DMA_Mst_Cmplt : std_logic;
signal Bus2MAC_DMA_Mst_Error : std_logic;
signal Bus2MAC_DMA_Mst_Rearbitrate : std_logic;
signal Bus2MAC_PKT_Clk : std_logic;
signal Bus2MAC_PKT_Reset : std_logic;
signal Bus2MAC_PKT_RNW : std_logic;
signal Bus2MAC_REG_Clk : std_logic;
signal Bus2MAC_REG_Reset : std_logic;
signal Bus2MAC_REG_RNW : std_logic;
signal Bus2MAC_REG_RNW_n : std_logic;
signal Bus2PDI_AP_Clk : std_logic;
signal Bus2PDI_AP_Reset : std_logic;
signal Bus2PDI_AP_RNW : std_logic;
signal Bus2PDI_PCP_Clk : std_logic;
signal Bus2PDI_PCP_Reset : std_logic;
signal Bus2PDI_PCP_RNW : std_logic;
signal Bus2SMP_PCP_Clk : std_logic;
signal Bus2SMP_PCP_Reset : std_logic;
signal Bus2SMP_PCP_RNW : std_logic;
signal clkAp : std_logic;
signal clkPcp : std_logic;
signal GND : std_logic;
signal IP2Bus_Error_s : std_logic;
signal IP2Bus_RrAck_s : std_logic;
signal IP2Bus_WrAck_s : std_logic;
signal mac_chipselect : std_logic;
signal MAC_CMP2Bus_Error : std_logic;
signal MAC_CMP2Bus_RdAck : std_logic;
signal MAC_CMP2Bus_WrAck : std_logic;
signal MAC_DMA2Bus_MstRd_dst_dsc_n : std_logic;
signal MAC_DMA2Bus_MstRd_dst_rdy_n : std_logic;
signal MAC_DMA2Bus_MstRd_Req : std_logic;
signal MAC_DMA2Bus_MstWr_eof_n : std_logic;
signal MAC_DMA2Bus_MstWr_Req : std_logic;
signal MAC_DMA2Bus_MstWr_sof_n : std_logic;
signal MAC_DMA2Bus_MstWr_src_dsc_n : std_logic;
signal MAC_DMA2Bus_MstWr_src_rdy_n : std_logic;
signal MAC_DMA2Bus_Mst_Lock : std_logic;
signal MAC_DMA2Bus_Mst_Reset : std_logic;
signal MAC_DMA2Bus_Mst_Type : std_logic;
signal mac_irq_s : std_logic;
signal MAC_PKT2Bus_Error : std_logic;
signal MAC_PKT2Bus_RdAck : std_logic;
signal MAC_PKT2Bus_WrAck : std_logic;
signal mac_read : std_logic;
signal MAC_REG2Bus_Error : std_logic;
signal MAC_REG2Bus_RdAck : std_logic;
signal MAC_REG2Bus_WrAck : std_logic;
signal mac_waitrequest : std_logic;
signal mac_write : std_logic;
signal mbf_chipselect : std_logic;
signal mbf_read : std_logic;
signal mbf_waitrequest : std_logic;
signal mbf_write : std_logic;
signal m_clk : std_logic;
signal m_read : std_logic;
signal m_readdatavalid : std_logic;
signal m_waitrequest : std_logic;
signal m_write : std_logic;
signal pcp_chipselect : std_logic;
signal pcp_read : std_logic;
signal pcp_waitrequest : std_logic;
signal pcp_write : std_logic;
signal PDI_AP2Bus_Error : std_logic;
signal PDI_AP2Bus_RdAck : std_logic;
signal PDI_AP2Bus_WrAck : std_logic;
signal PDI_PCP2Bus_Error : std_logic;
signal PDI_PCP2Bus_RdAck : std_logic;
signal PDI_PCP2Bus_WrAck : std_logic;
signal pkt_clk : std_logic;
signal rst : std_logic;
signal rstAp : std_logic;
signal rstPcp : std_logic;
signal smp_address : std_logic;
signal smp_chipselect : std_logic;
signal SMP_PCP2Bus_Error : std_logic;
signal SMP_PCP2Bus_RdAck : std_logic;
signal SMP_PCP2Bus_WrAck : std_logic;
signal smp_read : std_logic;
signal smp_waitrequest : std_logic;
signal smp_write : std_logic;
signal tcp_chipselect : std_logic;
signal tcp_irq_s : std_logic;
signal tcp_read : std_logic;
signal tcp_waitrequest : std_logic;
signal tcp_write : std_logic;
signal ap_address : std_logic_vector (12 downto 0);
signal ap_byteenable : std_logic_vector (3 downto 0);
signal ap_readdata : std_logic_vector (31 downto 0);
signal ap_writedata : std_logic_vector (31 downto 0);
signal Bus2MAC_DMA_MstRd_d : std_logic_vector (0 to C_MAC_DMA_PLB_NATIVE_DWIDTH-1);
signal Bus2MAC_DMA_MstRd_rem : std_logic_vector (0 to (C_MAC_DMA_PLB_NATIVE_DWIDTH/8)-1);
signal Bus2MAC_PKT_Addr : std_logic_vector (C_MAC_PKT_PLB_AWIDTH-1 downto 0);
signal Bus2MAC_PKT_BE : std_logic_vector ((C_MAC_PKT_PLB_DWIDTH/8)-1 downto 0);
signal Bus2MAC_PKT_CS : std_logic_vector (0 downto 0);
signal Bus2MAC_PKT_Data : std_logic_vector (C_MAC_PKT_PLB_DWIDTH-1 downto 0);
signal Bus2MAC_REG_Addr : std_logic_vector (C_MAC_REG_PLB_AWIDTH-1 downto 0);
signal Bus2MAC_REG_BE : std_logic_vector ((C_MAC_REG_PLB_DWIDTH/8)-1 downto 0);
signal Bus2MAC_REG_BE_s : std_logic_vector ((C_MAC_REG_PLB_DWIDTH/8)-1 downto 0);
signal Bus2MAC_REG_CS : std_logic_vector (1 downto 0);
signal Bus2MAC_REG_Data : std_logic_vector (C_MAC_REG_PLB_DWIDTH-1 downto 0);
signal Bus2PDI_AP_Addr : std_logic_vector (C_PDI_AP_PLB_AWIDTH-1 downto 0);
signal Bus2PDI_AP_BE : std_logic_vector ((C_PDI_AP_PLB_DWIDTH/8)-1 downto 0);
signal Bus2PDI_AP_CS : std_logic_vector (0 downto 0);
signal Bus2PDI_AP_Data : std_logic_vector (C_PDI_AP_PLB_DWIDTH-1 downto 0);
signal Bus2PDI_PCP_Addr : std_logic_vector (C_PDI_PCP_PLB_AWIDTH-1 downto 0);
signal Bus2PDI_PCP_BE : std_logic_vector ((C_PDI_PCP_PLB_DWIDTH/8)-1 downto 0);
signal Bus2PDI_PCP_CS : std_logic_vector (0 downto 0);
signal Bus2PDI_PCP_Data : std_logic_vector (C_PDI_PCP_PLB_DWIDTH-1 downto 0);
signal Bus2SMP_PCP_Addr : std_logic_vector (C_SMP_PCP_PLB_AWIDTH-1 downto 0);
signal Bus2SMP_PCP_BE : std_logic_vector ((C_SMP_PCP_PLB_DWIDTH/8)-1 downto 0);
signal Bus2SMP_PCP_CS : std_logic_vector (0 downto 0);
signal Bus2SMP_PCP_Data : std_logic_vector (C_SMP_PCP_PLB_DWIDTH-1 downto 0);
signal IP2Bus_Data_s : std_logic_vector (C_MAC_REG_PLB_DWIDTH-1 downto 0);
signal mac_address : std_logic_vector (C_MAC_REG_PLB_AWIDTH-1 downto 0);
signal mac_byteenable : std_logic_vector (1 downto 0);
signal MAC_CMP2Bus_Data : std_logic_vector (C_MAC_REG_PLB_DWIDTH-1 downto 0);
signal MAC_DMA2Bus_MstWr_d : std_logic_vector (0 to C_MAC_DMA_PLB_NATIVE_DWIDTH-1);
signal MAC_DMA2Bus_MstWr_rem : std_logic_vector (0 to (C_MAC_DMA_PLB_NATIVE_DWIDTH/8)-1);
signal MAC_DMA2Bus_Mst_Addr : std_logic_vector (0 to C_MAC_DMA_PLB_AWIDTH-1);
signal MAC_DMA2Bus_Mst_BE : std_logic_vector (0 to (C_MAC_DMA_PLB_NATIVE_DWIDTH/8)-1);
signal MAC_DMA2Bus_Mst_Length : std_logic_vector (0 to 11);
signal MAC_PKT2Bus_Data : std_logic_vector (C_MAC_PKT_PLB_DWIDTH-1 downto 0);
signal mac_readdata : std_logic_vector (15 downto 0);
signal MAC_REG2Bus_Data : std_logic_vector (C_MAC_REG_PLB_DWIDTH-1 downto 0);
signal mac_writedata : std_logic_vector (15 downto 0);
signal mbf_address : std_logic_vector (C_MAC_PKT_SIZE_LOG2-3 downto 0);
signal mbf_byteenable : std_logic_vector (3 downto 0);
signal mbf_readdata : std_logic_vector (31 downto 0);
signal mbf_writedata : std_logic_vector (31 downto 0);
signal m_address : std_logic_vector (31 downto 0) := (others => '0');
signal m_burstcount : std_logic_vector (C_M_BURSTCOUNT_WIDTH-1 downto 0);
signal m_burstcounter : std_logic_vector (C_M_BURSTCOUNT_WIDTH-1 downto 0);
signal m_byteenable : std_logic_vector (3 downto 0);
signal m_readdata : std_logic_vector (31 downto 0);
signal m_writedata : std_logic_vector (31 downto 0);
signal pcp_address : std_logic_vector (12 downto 0);
signal pcp_byteenable : std_logic_vector (3 downto 0);
signal pcp_readdata : std_logic_vector (31 downto 0);
signal pcp_writedata : std_logic_vector (31 downto 0);
signal PDI_AP2Bus_Data : std_logic_vector (C_PDI_AP_PLB_DWIDTH-1 downto 0);
signal PDI_PCP2Bus_Data : std_logic_vector (C_PDI_PCP_PLB_DWIDTH-1 downto 0);
signal smp_byteenable : std_logic_vector (3 downto 0);
signal SMP_PCP2Bus_Data : std_logic_vector (C_SMP_PCP_PLB_DWIDTH-1 downto 0);
signal smp_readdata : std_logic_vector (31 downto 0);
signal smp_writedata : std_logic_vector (31 downto 0);
signal tcp_address : std_logic_vector (1 downto 0);
signal tcp_byteenable : std_logic_vector (3 downto 0);
signal tcp_readdata : std_logic_vector (31 downto 0);
signal tcp_writedata : std_logic_vector (31 downto 0);
begin
---- User Signal Assignments ----
-- connect mac reg with mac cmp or reg output signals
with Bus2MAC_REG_CS select
IP2Bus_Data_s(C_MAC_REG_PLB_DWIDTH-1 downto 0) <= MAC_REG2Bus_Data(C_MAC_REG_PLB_DWIDTH-1 downto 0) when "10",
MAC_CMP2Bus_Data(C_MAC_REG_PLB_DWIDTH-1 downto 0) when "01",
(others => '0') when others;
with Bus2MAC_REG_CS select
IP2Bus_WrAck_s <= MAC_REG2Bus_WrAck when "10",
MAC_CMP2Bus_WrAck when "01",
'0' when others;
with Bus2MAC_REG_CS select
IP2Bus_RrAck_s <= MAC_REG2Bus_RdAck when "10",
MAC_CMP2Bus_RdAck when "01",
'0' when others;
with Bus2MAC_REG_CS select
IP2Bus_Error_s <= MAC_REG2Bus_Error when "10",
MAC_CMP2Bus_Error when "01",
'0' when others;
Bus2MAC_REG_BE_s <= Bus2MAC_REG_BE;
--mac_cmp assignments
---cmp_clk <= Bus2MAC_CMP_Clk;
tcp_writedata <= Bus2MAC_REG_Data;
tcp_read <= Bus2MAC_REG_RNW;
tcp_write <= not Bus2MAC_REG_RNW;
tcp_chipselect <= Bus2MAC_REG_CS(0);
tcp_byteenable <= Bus2MAC_REG_BE;
tcp_address <= Bus2MAC_REG_Addr(3 downto 2);
MAC_CMP2Bus_Data <= tcp_readdata;
MAC_CMP2Bus_RdAck <= tcp_chipselect and tcp_read and not tcp_waitrequest;
MAC_CMP2Bus_WrAck <= tcp_chipselect and tcp_write and not tcp_waitrequest;
MAC_CMP2Bus_Error <= '0';
--mac_pkt assignments
pkt_clk <= Bus2MAC_PKT_Clk;
mbf_writedata <= Bus2MAC_PKT_Data;
-- Bus2MAC_PKT_Data(7 downto 0) & Bus2MAC_PKT_Data(15 downto 8) &
-- Bus2MAC_PKT_Data(23 downto 16) & Bus2MAC_PKT_Data(31 downto 24);
mbf_read <= Bus2MAC_PKT_RNW;
mbf_write <= not Bus2MAC_PKT_RNW;
mbf_chipselect <= Bus2MAC_PKT_CS(0);
mbf_byteenable <= Bus2MAC_PKT_BE;
mbf_address <= Bus2MAC_PKT_Addr(C_MAC_PKT_SIZE_LOG2-1 downto 2);
MAC_PKT2Bus_Data <= mbf_readdata;
-- mbf_readdata(7 downto 0) & mbf_readdata(15 downto 8) &
-- mbf_readdata(23 downto 16) & mbf_readdata(31 downto 24);
MAC_PKT2Bus_RdAck <= mbf_chipselect and mbf_read and not mbf_waitrequest;
MAC_PKT2Bus_WrAck <= mbf_chipselect and mbf_write and not mbf_waitrequest;
MAC_PKT2Bus_Error <= '0';
--test_port
test_port(255 downto 251) <= m_read & m_write & m_waitrequest & m_readdatavalid & MAC_DMA2Bus_Mst_Type;
test_port(244 downto 240) <= MAC_DMA2Bus_MstWr_Req & MAC_DMA2Bus_MstWr_sof_n & MAC_DMA2Bus_MstWr_eof_n & MAC_DMA2Bus_MstWr_src_rdy_n & Bus2MAC_DMA_MstWr_dst_rdy_n;
test_port(234 downto 230) <= MAC_DMA2Bus_MstRd_Req & Bus2MAC_DMA_MstRd_sof_n & Bus2MAC_DMA_MstRd_eof_n & Bus2MAC_DMA_MstRd_src_rdy_n & MAC_DMA2Bus_MstRd_dst_rdy_n;
test_port(142 downto 140) <= Bus2MAC_DMA_Mst_Cmplt & Bus2MAC_DMA_Mst_Error & Bus2MAC_DMA_Mst_Cmd_Timeout;
test_port(MAC_DMA2Bus_Mst_Length'length+120-1 downto 120) <= MAC_DMA2Bus_Mst_Length;
test_port(m_burstcount'length+110-1 downto 110) <= m_burstcount;
test_port(m_burstcounter'length+96-1 downto 96) <= m_burstcounter;
test_port(95 downto 64) <= m_address;
test_port(63 downto 32) <= m_writedata;
test_port(31 downto 0) <= m_readdata;
---- Component instantiations ----
MAC_REG_16to32 : openMAC_16to32conv
generic map (
bus_address_width => C_MAC_REG_PLB_AWIDTH
)
port map(
bus_ack_rd => MAC_REG2Bus_RdAck,
bus_ack_wr => MAC_REG2Bus_WrAck,
bus_address => Bus2MAC_REG_Addr( C_MAC_REG_PLB_AWIDTH-1 downto 0 ),
bus_byteenable => Bus2MAC_REG_BE_s( (C_MAC_REG_PLB_DWIDTH/8)-1 downto 0 ),
bus_read => Bus2MAC_REG_RNW,
bus_readdata => MAC_REG2Bus_Data( C_MAC_REG_PLB_DWIDTH-1 downto 0 ),
bus_select => Bus2MAC_REG_CS(1),
bus_write => Bus2MAC_REG_RNW_n,
bus_writedata => Bus2MAC_REG_Data( C_MAC_REG_PLB_DWIDTH-1 downto 0 ),
clk => clk50,
rst => rst,
s_address => mac_address( C_MAC_REG_PLB_AWIDTH-1 downto 0 ),
s_byteenable => mac_byteenable,
s_chipselect => mac_chipselect,
s_read => mac_read,
s_readdata => mac_readdata,
s_waitrequest => mac_waitrequest,
s_write => mac_write,
s_writedata => mac_writedata
);
MAC_REG_PLB_SINGLE_SLAVE : plbv46_slave_single
generic map (
C_ARD_ADDR_RANGE_ARRAY => (C_MAC_REG_BASE,C_MAC_REG_HIGH,C_MAC_CMP_BASE,C_MAC_CMP_HIGH),
C_ARD_NUM_CE_ARRAY => (1, 1),
C_BUS2CORE_CLK_RATIO => C_MAC_REG_BUS2CORE_CLK_RATIO,
C_FAMILY => C_FAMILY,
C_INCLUDE_DPHASE_TIMER => 0,
C_SIPIF_DWIDTH => C_MAC_REG_PLB_DWIDTH,
C_SPLB_AWIDTH => C_MAC_REG_PLB_AWIDTH,
C_SPLB_DWIDTH => C_MAC_REG_PLB_DWIDTH,
C_SPLB_MID_WIDTH => C_MAC_REG_PLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_MAC_REG_PLB_NUM_MASTERS,
C_SPLB_P2P => C_MAC_REG_PLB_P2P
)
port map(
Bus2IP_Addr => Bus2MAC_REG_Addr( C_MAC_REG_PLB_AWIDTH-1 downto 0 ),
Bus2IP_BE => Bus2MAC_REG_BE( (C_MAC_REG_PLB_DWIDTH/8)-1 downto 0 ),
Bus2IP_CS => Bus2MAC_REG_CS( 1 downto 0 ),
Bus2IP_Clk => Bus2MAC_REG_Clk,
Bus2IP_Data => Bus2MAC_REG_Data( C_MAC_REG_PLB_DWIDTH-1 downto 0 ),
Bus2IP_RNW => Bus2MAC_REG_RNW,
Bus2IP_Reset => Bus2MAC_REG_Reset,
IP2Bus_Data => IP2Bus_Data_s( C_MAC_REG_PLB_DWIDTH-1 downto 0 ),
IP2Bus_Error => IP2Bus_Error_s,
IP2Bus_RdAck => IP2Bus_RrAck_s,
IP2Bus_WrAck => IP2Bus_WrAck_s,
PLB_ABus => MAC_REG_ABus,
PLB_BE => MAC_REG_BE( 0 to (C_MAC_REG_PLB_DWIDTH / 8) - 1 ),
PLB_MSize => MAC_REG_MSize,
PLB_PAValid => MAC_REG_PAValid,
PLB_RNW => MAC_REG_RNW,
PLB_SAValid => MAC_REG_SAValid,
PLB_TAttribute => MAC_REG_TAttribute,
PLB_UABus => MAC_REG_UABus,
PLB_abort => MAC_REG_abort,
PLB_busLock => MAC_REG_busLock,
PLB_lockErr => MAC_REG_lockErr,
PLB_masterID => MAC_REG_masterID( 0 to C_MAC_REG_PLB_MID_WIDTH - 1 ),
PLB_rdBurst => MAC_REG_rdBurst,
PLB_rdPendPri => MAC_REG_rdPendPri,
PLB_rdPendReq => MAC_REG_rdPendReq,
PLB_rdPrim => MAC_REG_rdPrim,
PLB_reqPri => MAC_REG_reqPri,
PLB_size => MAC_REG_size,
PLB_type => MAC_REG_type,
PLB_wrBurst => MAC_REG_wrBurst,
PLB_wrDBus => MAC_REG_wrDBus( 0 to C_MAC_REG_PLB_DWIDTH - 1 ),
PLB_wrPendPri => MAC_REG_wrPendPri,
PLB_wrPendReq => MAC_REG_wrPendReq,
PLB_wrPrim => MAC_REG_wrPrim,
SPLB_Clk => MAC_REG_Clk,
SPLB_Rst => MAC_REG_Rst,
Sl_MBusy => MAC_REG_MBusy( 0 to C_MAC_REG_NUM_MASTERS-1 ),
Sl_MIRQ => MAC_REG_MIRQ( 0 to C_MAC_REG_NUM_MASTERS-1 ),
Sl_MRdErr => MAC_REG_MRdErr( 0 to C_MAC_REG_NUM_MASTERS-1 ),
Sl_MWrErr => MAC_REG_MWrErr( 0 to C_MAC_REG_NUM_MASTERS-1 ),
Sl_SSize => MAC_REG_SSize,
Sl_addrAck => MAC_REG_addrAck,
Sl_rdBTerm => MAC_REG_rdBTerm,
Sl_rdComp => MAC_REG_rdComp,
Sl_rdDAck => MAC_REG_rdDAck,
Sl_rdDBus => MAC_REG_rdDBus( 0 to C_MAC_REG_PLB_DWIDTH-1 ),
Sl_rdWdAddr => MAC_REG_rdWdAddr,
Sl_rearbitrate => MAC_REG_rearbitrate,
Sl_wait => MAC_REG_wait,
Sl_wrBTerm => MAC_REG_wrBTerm,
Sl_wrComp => MAC_REG_wrComp,
Sl_wrDAck => MAC_REG_wrDAck
);
THE_POWERLINK_IP_CORE : powerlink
generic map (
Simulate => false,
endian_g => "big",
gNumSmi => C_NUM_SMI,
genABuf1_g => C_PDI_GEN_ASYNC_BUF_0,
genABuf2_g => C_PDI_GEN_ASYNC_BUF_1,
genEvent_g => C_PDI_GEN_EVENT,
genInternalAp_g => C_GEN_PLB_BUS_IF,
genIoBuf_g => false,
genLedGadget_g => C_PDI_GEN_LED,
genOnePdiClkDomain_g => false,
genPdi_g => C_GEN_PDI,
genSimpleIO_g => C_GEN_SIMPLE_IO,
genSmiIO => false,
genSpiAp_g => C_GEN_SPI_IF,
genTimeSync_g => C_PDI_GEN_TIME_SYNC,
gen_dma_observer_g => C_OBSERVER_ENABLE,
iAsyBuf1Size_g => C_PDI_ASYNC_BUF_0,
iAsyBuf2Size_g => C_PDI_ASYNC_BUF_1,
iBufSizeLOG2_g => C_MAC_PKT_SIZE_LOG2,
iBufSize_g => C_MAC_PKT_SIZE,
iPdiRev_g => 2,
iRpdo0BufSize_g => C_RPDO_0_BUF_SIZE,
iRpdo1BufSize_g => C_RPDO_1_BUF_SIZE,
iRpdo2BufSize_g => C_RPDO_2_BUF_SIZE,
iRpdos_g => C_NUM_RPDO,
iTpdoBufSize_g => C_TPDO_BUF_SIZE,
iTpdos_g => C_NUM_TPDO,
m_burstcount_const_g => true,
m_burstcount_width_g => C_M_BURSTCOUNT_WIDTH,
m_data_width_g => 32,
m_rx_burst_size_g => C_MAC_DMA_BURST_SIZE_RX/4,
m_rx_fifo_size_g => C_M_FIFO_SIZE_RX,
m_tx_burst_size_g => C_MAC_DMA_BURST_SIZE_TX/4,
m_tx_fifo_size_g => C_M_FIFO_SIZE_TX,
papBigEnd_g => false,
papDataWidth_g => C_PAP_DATA_WIDTH,
papLowAct_g => C_PAP_LOW_ACT,
pioValLen_g => C_PIO_VAL_LENGTH,
spiBigEnd_g => false,
spiCPHA_g => C_SPI_CPHA,
spiCPOL_g => C_SPI_CPOL,
use2ndCmpTimer_g => C_PDI_GEN_SECOND_TIMER,
use2ndPhy_g => C_USE_2ND_PHY,
useIntPacketBuf_g => C_MAC_PKT_EN,
useRmii_g => C_USE_RMII,
useRxIntPacketBuf_g => C_MAC_PKT_RX_EN
)
port map(
mac_address(0) => mac_address(0),
mac_address(1) => mac_address(1),
mac_address(2) => mac_address(2),
mac_address(3) => mac_address(3),
mac_address(4) => mac_address(4),
mac_address(5) => mac_address(5),
mac_address(6) => mac_address(6),
mac_address(7) => mac_address(7),
mac_address(8) => mac_address(8),
mac_address(9) => mac_address(9),
mac_address(10) => mac_address(10),
mac_address(11) => mac_address(11),
m_address(0) => m_address(0),
m_address(1) => m_address(1),
m_address(2) => m_address(2),
m_address(3) => m_address(3),
m_address(4) => m_address(4),
m_address(5) => m_address(5),
m_address(6) => m_address(6),
m_address(7) => m_address(7),
m_address(8) => m_address(8),
m_address(9) => m_address(9),
m_address(10) => m_address(10),
m_address(11) => m_address(11),
m_address(12) => m_address(12),
m_address(13) => m_address(13),
m_address(14) => m_address(14),
m_address(15) => m_address(15),
m_address(16) => m_address(16),
m_address(17) => m_address(17),
m_address(18) => m_address(18),
m_address(19) => m_address(19),
m_address(20) => m_address(20),
m_address(21) => m_address(21),
m_address(22) => m_address(22),
m_address(23) => m_address(23),
m_address(24) => m_address(24),
m_address(25) => m_address(25),
m_address(26) => m_address(26),
m_address(27) => m_address(27),
m_address(28) => m_address(28),
m_address(29) => m_address(29),
ap_address => ap_address,
ap_asyncIrq => ap_asyncIrq,
ap_asyncIrq_n => ap_asyncIrq_n,
ap_byteenable => ap_byteenable,
ap_chipselect => ap_chipselect,
ap_read => ap_read,
ap_readdata => ap_readdata,
ap_syncIrq => ap_syncIrq,
ap_syncIrq_n => ap_syncIrq_n,
ap_waitrequest => ap_waitrequest,
ap_write => ap_write,
ap_writedata => ap_writedata,
clk50 => clk50,
clkAp => clkAp,
clkEth => clk100,
clkPcp => clkPcp,
led_error => led_error,
led_gpo => led_gpo,
led_opt => led_opt,
led_phyAct => led_phyAct,
led_phyLink => led_phyLink,
led_status => led_status,
m_burstcount => m_burstcount( C_M_BURSTCOUNT_WIDTH-1 downto 0 ),
m_burstcounter => m_burstcounter( C_M_BURSTCOUNT_WIDTH-1 downto 0 ),
m_byteenable => m_byteenable( 3 downto 0 ),
m_clk => m_clk,
m_read => m_read,
m_readdata => m_readdata( 31 downto 0 ),
m_readdatavalid => m_readdatavalid,
m_waitrequest => m_waitrequest,
m_write => m_write,
m_writedata => m_writedata( 31 downto 0 ),
mac_byteenable => mac_byteenable,
mac_chipselect => mac_chipselect,
mac_irq => mac_irq_s,
mac_read => mac_read,
mac_readdata => mac_readdata,
mac_waitrequest => mac_waitrequest,
mac_write => mac_write,
mac_writedata => mac_writedata,
mbf_address => mbf_address( C_MAC_PKT_SIZE_LOG2-3 downto 0 ),
mbf_byteenable => mbf_byteenable,
mbf_chipselect => mbf_chipselect,
mbf_read => mbf_read,
mbf_readdata => mbf_readdata,
mbf_waitrequest => mbf_waitrequest,
mbf_write => mbf_write,
mbf_writedata => mbf_writedata,
pap_ack => pap_ack,
pap_ack_n => pap_ack_n,
pap_addr => pap_addr,
pap_be => pap_be( C_PAP_DATA_WIDTH/8-1 downto 0 ),
pap_be_n => pap_be_n( C_PAP_DATA_WIDTH/8-1 downto 0 ),
pap_cs => pap_cs,
pap_cs_n => pap_cs_n,
pap_data_I => pap_data_I( C_PAP_DATA_WIDTH-1 downto 0 ),
pap_data_O => pap_data_O( C_PAP_DATA_WIDTH-1 downto 0 ),
pap_data_T => pap_data_T,
pap_gpio_I => pap_gpio_I,
pap_gpio_O => pap_gpio_O,
pap_gpio_T => pap_gpio_T,
pap_rd => pap_rd,
pap_rd_n => pap_rd_n,
pap_wr => pap_wr,
pap_wr_n => pap_wr_n,
pcp_address => pcp_address,
pcp_byteenable => pcp_byteenable,
pcp_chipselect => pcp_chipselect,
pcp_read => pcp_read,
pcp_readdata => pcp_readdata,
pcp_waitrequest => pcp_waitrequest,
pcp_write => pcp_write,
pcp_writedata => pcp_writedata,
phy0_Rst_n => phy0_Rst_n,
phy0_RxDat => phy0_RxDat,
phy0_RxDv => phy0_RxDv,
phy0_RxErr => phy0_RxErr,
phy0_SMIClk => phy0_SMIClk,
phy0_SMIDat_I => phy0_SMIDat_I,
phy0_SMIDat_O => phy0_SMIDat_O,
phy0_SMIDat_T => phy0_SMIDat_T,
phy0_TxDat => phy0_TxDat,
phy0_TxEn => phy0_TxEn,
phy0_link => phy0_link,
phy1_Rst_n => phy1_Rst_n,
phy1_RxDat => phy1_RxDat,
phy1_RxDv => phy1_RxDv,
phy1_RxErr => phy1_RxErr,
phy1_SMIClk => phy1_SMIClk,
phy1_SMIDat_I => phy1_SMIDat_I,
phy1_SMIDat_O => phy1_SMIDat_O,
phy1_SMIDat_T => phy1_SMIDat_T,
phy1_TxDat => phy1_TxDat,
phy1_TxEn => phy1_TxEn,
phy1_link => phy1_link,
phyMii0_RxClk => phyMii0_RxClk,
phyMii0_RxDat => phyMii0_RxDat,
phyMii0_RxDv => phyMii0_RxDv,
phyMii0_RxEr => phyMii0_RxEr,
phyMii0_TxClk => phyMii0_TxClk,
phyMii0_TxDat => phyMii0_TxDat,
phyMii0_TxEn => phyMii0_TxEn,
phyMii0_TxEr => phyMii0_TxEr,
phyMii1_RxClk => phyMii1_RxClk,
phyMii1_RxDat => phyMii1_RxDat,
phyMii1_RxDv => phyMii1_RxDv,
phyMii1_RxEr => phyMii1_RxEr,
phyMii1_TxClk => phyMii1_TxClk,
phyMii1_TxDat => phyMii1_TxDat,
phyMii1_TxEn => phyMii1_TxEn,
phyMii1_TxEr => phyMii1_TxEr,
phy_Rst_n => phy_Rst_n,
phy_SMIClk => phy_SMIClk,
phy_SMIDat_I => phy_SMIDat_I,
phy_SMIDat_O => phy_SMIDat_O,
phy_SMIDat_T => phy_SMIDat_T,
pio_operational => pio_operational,
pio_pconfig => pio_pconfig,
pio_portInLatch => pio_portInLatch,
pio_portOutValid => pio_portOutValid,
pio_portio_I => pio_portio_I,
pio_portio_O => pio_portio_O,
pio_portio_T => pio_portio_T,
pkt_clk => pkt_clk,
rst => rst,
rstAp => rstAp,
rstPcp => rstPcp,
smp_address => smp_address,
smp_byteenable => smp_byteenable,
smp_read => smp_read,
smp_readdata => smp_readdata,
smp_waitrequest => smp_waitrequest,
smp_write => smp_write,
smp_writedata => smp_writedata,
spi_clk => spi_clk,
spi_miso => spi_miso,
spi_mosi => spi_mosi,
spi_sel_n => spi_sel_n,
tcp_address => tcp_address,
tcp_byteenable => tcp_byteenable,
tcp_chipselect => tcp_chipselect,
tcp_irq => tcp_irq_s,
tcp_read => tcp_read,
tcp_readdata => tcp_readdata,
tcp_waitrequest => tcp_waitrequest,
tcp_write => tcp_write,
tcp_writedata => tcp_writedata
);
phy0_clk <= clk50;
rst <= Bus2MAC_REG_Reset or Bus2MAC_CMP_Reset or MAC_DMA_RST or Bus2MAC_PKT_Reset;
Bus2MAC_REG_RNW_n <= not(Bus2MAC_REG_RNW);
phy1_clk <= clk50;
---- Power , ground assignment ----
GND <= GND_CONSTANT;
MAC_REG2Bus_Error <= GND;
---- Terminal assignment ----
-- Output\buffer terminals
mac_irq <= mac_irq_s;
tcp_irq <= tcp_irq_s;
---- Generate statements ----
genMacDmaPlbBurst : if C_DMA_EN = TRUE generate
begin
MAC_DMA_PLB_BURST_MASTER : plbv46_master_burst
generic map (
C_FAMILY => C_FAMILY,
C_INHIBIT_CC_BLE_INCLUSION => 1,
C_MPLB_AWIDTH => C_MAC_DMA_PLB_AWIDTH,
C_MPLB_DWIDTH => C_MAC_DMA_PLB_DWIDTH,
C_MPLB_NATIVE_DWIDTH => C_MAC_DMA_PLB_NATIVE_DWIDTH,
C_MPLB_SMALLEST_SLAVE => 32
)
port map(
Bus2IP_MstRd_d => Bus2MAC_DMA_MstRd_d( 0 to C_MAC_DMA_PLB_NATIVE_DWIDTH-1 ),
Bus2IP_MstRd_eof_n => Bus2MAC_DMA_MstRd_eof_n,
Bus2IP_MstRd_rem => Bus2MAC_DMA_MstRd_rem( 0 to (C_MAC_DMA_PLB_NATIVE_DWIDTH/8)-1 ),
Bus2IP_MstRd_sof_n => Bus2MAC_DMA_MstRd_sof_n,
Bus2IP_MstRd_src_dsc_n => Bus2MAC_DMA_MstRd_src_dsc_n,
Bus2IP_MstRd_src_rdy_n => Bus2MAC_DMA_MstRd_src_rdy_n,
Bus2IP_MstWr_dst_dsc_n => Bus2MAC_DMA_MstWr_dst_dsc_n,
Bus2IP_MstWr_dst_rdy_n => Bus2MAC_DMA_MstWr_dst_rdy_n,
Bus2IP_Mst_CmdAck => Bus2MAC_DMA_Mst_CmdAck,
Bus2IP_Mst_Cmd_Timeout => Bus2MAC_DMA_Mst_Cmd_Timeout,
Bus2IP_Mst_Cmplt => Bus2MAC_DMA_Mst_Cmplt,
Bus2IP_Mst_Error => Bus2MAC_DMA_Mst_Error,
Bus2IP_Mst_Rearbitrate => Bus2MAC_DMA_Mst_Rearbitrate,
IP2Bus_MstRd_Req => MAC_DMA2Bus_MstRd_Req,
IP2Bus_MstRd_dst_dsc_n => MAC_DMA2Bus_MstRd_dst_dsc_n,
IP2Bus_MstRd_dst_rdy_n => MAC_DMA2Bus_MstRd_dst_rdy_n,
IP2Bus_MstWr_Req => MAC_DMA2Bus_MstWr_Req,
IP2Bus_MstWr_d => MAC_DMA2Bus_MstWr_d( 0 to C_MAC_DMA_PLB_NATIVE_DWIDTH-1 ),
IP2Bus_MstWr_eof_n => MAC_DMA2Bus_MstWr_eof_n,
IP2Bus_MstWr_rem => MAC_DMA2Bus_MstWr_rem( 0 to (C_MAC_DMA_PLB_NATIVE_DWIDTH/8)-1 ),
IP2Bus_MstWr_sof_n => MAC_DMA2Bus_MstWr_sof_n,
IP2Bus_MstWr_src_dsc_n => MAC_DMA2Bus_MstWr_src_dsc_n,
IP2Bus_MstWr_src_rdy_n => MAC_DMA2Bus_MstWr_src_rdy_n,
IP2Bus_Mst_Addr => MAC_DMA2Bus_Mst_Addr( 0 to C_MAC_DMA_PLB_AWIDTH-1 ),
IP2Bus_Mst_BE => MAC_DMA2Bus_Mst_BE( 0 to (C_MAC_DMA_PLB_NATIVE_DWIDTH/8)-1 ),
IP2Bus_Mst_Length => MAC_DMA2Bus_Mst_Length,
IP2Bus_Mst_Lock => MAC_DMA2Bus_Mst_Lock,
IP2Bus_Mst_Reset => MAC_DMA2Bus_Mst_Reset,
IP2Bus_Mst_Type => MAC_DMA2Bus_Mst_Type,
MD_Error => MAC_DMA_error,
MPLB_Clk => MAC_DMA_Clk,
MPLB_Rst => MAC_DMA_Rst,
M_ABus => MAC_DMA_ABus,
M_BE => MAC_DMA_BE( 0 to (C_MAC_DMA_PLB_DWIDTH/8)-1 ),
M_MSize => MAC_DMA_MSize,
M_RNW => MAC_DMA_RNW,
M_TAttribute => MAC_DMA_TAttribute,
M_UABus => MAC_DMA_UABus,
M_abort => MAC_DMA_abort,
M_busLock => MAC_DMA_busLock,
M_lockErr => MAC_DMA_lockErr,
M_priority => MAC_DMA_priority,
M_rdBurst => MAC_DMA_rdBurst,
M_request => MAC_DMA_request,
M_size => MAC_DMA_size,
M_type => MAC_DMA_type,
M_wrBurst => MAC_DMA_wrBurst,
M_wrDBus => MAC_DMA_wrDBus( 0 to C_MAC_DMA_PLB_DWIDTH-1 ),
PLB_MAddrAck => MAC_DMA_MAddrAck,
PLB_MBusy => MAC_DMA_MBusy,
PLB_MIRQ => MAC_DMA_MIRQ,
PLB_MRdBTerm => MAC_DMA_MRdBTerm,
PLB_MRdDAck => MAC_DMA_MRdDAck,
PLB_MRdDBus => MAC_DMA_MRdDBus( 0 to C_MAC_DMA_PLB_DWIDTH-1 ),
PLB_MRdErr => MAC_DMA_MRdErr,
PLB_MRdWdAddr => MAC_DMA_MRdWdAddr,
PLB_MRearbitrate => MAC_DMA_MRearbitrate,
PLB_MSSize => MAC_DMA_MSSize,
PLB_MTimeout => MAC_DMA_MTimeout,
PLB_MWrBTerm => MAC_DMA_MWrBTerm,
PLB_MWrDAck => MAC_DMA_MWrDAck,
PLB_MWrErr => MAC_DMA_MWrErr
);
end generate genMacDmaPlbBurst;
genThePlbMaster : if C_DMA_EN = TRUE generate
begin
THE_IPIF_MASTER_HANDLER : ipif_master_handler
generic map (
dma_highadr_g => m_address'high,
gen_rx_fifo_g => not C_RX_INT_PKT,
gen_tx_fifo_g => not C_TX_INT_PKT,
m_burstcount_width_g => C_M_BURSTCOUNT_WIDTH
)
port map(
Bus2MAC_DMA_MstRd_d => Bus2MAC_DMA_MstRd_d( 0 to C_MAC_DMA_PLB_NATIVE_DWIDTH-1 ),
Bus2MAC_DMA_MstRd_eof_n => Bus2MAC_DMA_MstRd_eof_n,
Bus2MAC_DMA_MstRd_rem => Bus2MAC_DMA_MstRd_rem( 0 to (C_MAC_DMA_PLB_NATIVE_DWIDTH/8)-1 ),
Bus2MAC_DMA_MstRd_sof_n => Bus2MAC_DMA_MstRd_sof_n,
Bus2MAC_DMA_MstRd_src_dsc_n => Bus2MAC_DMA_MstRd_src_dsc_n,
Bus2MAC_DMA_MstRd_src_rdy_n => Bus2MAC_DMA_MstRd_src_rdy_n,
Bus2MAC_DMA_MstWr_dst_dsc_n => Bus2MAC_DMA_MstWr_dst_dsc_n,
Bus2MAC_DMA_MstWr_dst_rdy_n => Bus2MAC_DMA_MstWr_dst_rdy_n,
Bus2MAC_DMA_Mst_CmdAck => Bus2MAC_DMA_Mst_CmdAck,
Bus2MAC_DMA_Mst_Cmd_Timeout => Bus2MAC_DMA_Mst_Cmd_Timeout,
Bus2MAC_DMA_Mst_Cmplt => Bus2MAC_DMA_Mst_Cmplt,
Bus2MAC_DMA_Mst_Error => Bus2MAC_DMA_Mst_Error,
Bus2MAC_DMA_Mst_Rearbitrate => Bus2MAC_DMA_Mst_Rearbitrate,
MAC_DMA2Bus_MstRd_Req => MAC_DMA2Bus_MstRd_Req,
MAC_DMA2Bus_MstRd_dst_dsc_n => MAC_DMA2Bus_MstRd_dst_dsc_n,
MAC_DMA2Bus_MstRd_dst_rdy_n => MAC_DMA2Bus_MstRd_dst_rdy_n,
MAC_DMA2Bus_MstWr_Req => MAC_DMA2Bus_MstWr_Req,
MAC_DMA2Bus_MstWr_d => MAC_DMA2Bus_MstWr_d( 0 to C_MAC_DMA_PLB_NATIVE_DWIDTH-1 ),
MAC_DMA2Bus_MstWr_eof_n => MAC_DMA2Bus_MstWr_eof_n,
MAC_DMA2Bus_MstWr_rem => MAC_DMA2Bus_MstWr_rem( 0 to (C_MAC_DMA_PLB_NATIVE_DWIDTH/8)-1 ),
MAC_DMA2Bus_MstWr_sof_n => MAC_DMA2Bus_MstWr_sof_n,
MAC_DMA2Bus_MstWr_src_dsc_n => MAC_DMA2Bus_MstWr_src_dsc_n,
MAC_DMA2Bus_MstWr_src_rdy_n => MAC_DMA2Bus_MstWr_src_rdy_n,
MAC_DMA2Bus_Mst_Addr => MAC_DMA2Bus_Mst_Addr( 0 to C_MAC_DMA_PLB_AWIDTH-1 ),
MAC_DMA2Bus_Mst_BE => MAC_DMA2Bus_Mst_BE( 0 to (C_MAC_DMA_PLB_NATIVE_DWIDTH/8)-1 ),
MAC_DMA2Bus_Mst_Length => MAC_DMA2Bus_Mst_Length,
MAC_DMA2Bus_Mst_Lock => MAC_DMA2Bus_Mst_Lock,
MAC_DMA2Bus_Mst_Reset => MAC_DMA2Bus_Mst_Reset,
MAC_DMA2Bus_Mst_Type => MAC_DMA2Bus_Mst_Type,
MAC_DMA_CLK => MAC_DMA_CLK,
MAC_DMA_Rst => MAC_DMA_Rst,
m_address => m_address( 31 downto 0 ),
m_burstcount => m_burstcount( C_M_BURSTCOUNT_WIDTH-1 downto 0 ),
m_burstcounter => m_burstcounter( C_M_BURSTCOUNT_WIDTH-1 downto 0 ),
m_byteenable => m_byteenable,
m_clk => m_clk,
m_read => m_read,
m_readdata => m_readdata,
m_readdatavalid => m_readdatavalid,
m_waitrequest => m_waitrequest,
m_write => m_write,
m_writedata => m_writedata
);
end generate genThePlbMaster;
genMacPktPLbSingleSlave : if C_PKT_BUF_EN generate
begin
MAC_PKT_PLB_SINGLE_SLAVE : plbv46_slave_single
generic map (
C_ARD_ADDR_RANGE_ARRAY => (C_MAC_PKT_BASE,C_MAC_PKT_HIGH),
C_ARD_NUM_CE_ARRAY => (0 => 1),
C_BUS2CORE_CLK_RATIO => 1,
C_FAMILY => C_FAMILY,
C_INCLUDE_DPHASE_TIMER => 0,
C_SIPIF_DWIDTH => C_MAC_PKT_PLB_DWIDTH,
C_SPLB_AWIDTH => C_MAC_PKT_PLB_AWIDTH,
C_SPLB_DWIDTH => C_MAC_PKT_PLB_DWIDTH,
C_SPLB_MID_WIDTH => C_MAC_PKT_PLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_MAC_PKT_PLB_NUM_MASTERS,
C_SPLB_P2P => C_MAC_PKT_PLB_P2P
)
port map(
Bus2IP_Addr => Bus2MAC_PKT_Addr( C_MAC_PKT_PLB_AWIDTH-1 downto 0 ),
Bus2IP_BE => Bus2MAC_PKT_BE( (C_MAC_PKT_PLB_DWIDTH/8)-1 downto 0 ),
Bus2IP_CS => Bus2MAC_PKT_CS( 0 downto 0 ),
Bus2IP_Clk => Bus2MAC_PKT_Clk,
Bus2IP_Data => Bus2MAC_PKT_Data( C_MAC_PKT_PLB_DWIDTH-1 downto 0 ),
Bus2IP_RNW => Bus2MAC_PKT_RNW,
Bus2IP_Reset => Bus2MAC_PKT_Reset,
IP2Bus_Data => MAC_PKT2Bus_Data( C_MAC_PKT_PLB_DWIDTH-1 downto 0 ),
IP2Bus_Error => MAC_PKT2Bus_Error,
IP2Bus_RdAck => MAC_PKT2Bus_RdAck,
IP2Bus_WrAck => MAC_PKT2Bus_WrAck,
PLB_ABus => MAC_PKT_ABus,
PLB_BE => MAC_PKT_BE( 0 to (C_MAC_PKT_PLB_DWIDTH/8)-1 ),
PLB_MSize => MAC_PKT_MSize,
PLB_PAValid => MAC_PKT_PAValid,
PLB_RNW => MAC_PKT_RNW,
PLB_SAValid => MAC_PKT_SAValid,
PLB_TAttribute => MAC_PKT_TAttribute,
PLB_UABus => MAC_PKT_UABus,
PLB_abort => MAC_PKT_abort,
PLB_busLock => MAC_PKT_busLock,
PLB_lockErr => MAC_PKT_lockErr,
PLB_masterID => MAC_PKT_masterID( 0 to C_MAC_PKT_PLB_MID_WIDTH-1 ),
PLB_rdBurst => MAC_PKT_rdBurst,
PLB_rdPendPri => MAC_PKT_rdPendPri,
PLB_rdPendReq => MAC_PKT_rdPendReq,
PLB_rdPrim => MAC_PKT_rdPrim,
PLB_reqPri => MAC_PKT_reqPri,
PLB_size => MAC_PKT_size,
PLB_type => MAC_PKT_type,
PLB_wrBurst => MAC_PKT_wrBurst,
PLB_wrDBus => MAC_PKT_wrDBus( 0 to C_MAC_PKT_PLB_DWIDTH-1 ),
PLB_wrPendPri => MAC_PKT_wrPendPri,
PLB_wrPendReq => MAC_PKT_wrPendReq,
PLB_wrPrim => MAC_PKT_wrPrim,
SPLB_Clk => MAC_PKT_Clk,
SPLB_Rst => MAC_PKT_Rst,
Sl_MBusy => MAC_PKT_MBusy( 0 to C_MAC_PKT_NUM_MASTERS-1 ),
Sl_MIRQ => MAC_PKT_MIRQ( 0 to C_MAC_PKT_NUM_MASTERS-1 ),
Sl_MRdErr => MAC_PKT_MRdErr( 0 to C_MAC_PKT_NUM_MASTERS-1 ),
Sl_MWrErr => MAC_PKT_MWrErr( 0 to C_MAC_PKT_NUM_MASTERS-1 ),
Sl_SSize => MAC_PKT_SSize,
Sl_addrAck => MAC_PKT_addrAck,
Sl_rdBTerm => MAC_PKT_rdBTerm,
Sl_rdComp => MAC_PKT_rdComp,
Sl_rdDAck => MAC_PKT_rdDAck,
Sl_rdDBus => MAC_PKT_rdDBus( 0 to C_MAC_PKT_PLB_DWIDTH-1 ),
Sl_rdWdAddr => MAC_PKT_rdWdAddr,
Sl_rearbitrate => MAC_PKT_rearbitrate,
Sl_wait => MAC_PKT_wait,
Sl_wrBTerm => MAC_PKT_wrBTerm,
Sl_wrComp => MAC_PKT_wrComp,
Sl_wrDAck => MAC_PKT_wrDAck
);
end generate genMacPktPLbSingleSlave;
genPdiPcp : if (C_GEN_PDI) generate
begin
PDI_PCP_PLB_SINGLE_SLAVE : plbv46_slave_single
generic map (
C_ARD_ADDR_RANGE_ARRAY => (C_PDI_PCP_BASE,C_PDI_PCP_HIGH),
C_ARD_NUM_CE_ARRAY => (0 => 1),
C_BUS2CORE_CLK_RATIO => 1,
C_FAMILY => C_FAMILY,
C_INCLUDE_DPHASE_TIMER => 0,
C_SIPIF_DWIDTH => C_PDI_PCP_PLB_DWIDTH,
C_SPLB_AWIDTH => C_PDI_PCP_PLB_AWIDTH,
C_SPLB_DWIDTH => C_PDI_PCP_PLB_DWIDTH,
C_SPLB_MID_WIDTH => C_PDI_PCP_PLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_PDI_PCP_PLB_NUM_MASTERS,
C_SPLB_P2P => C_PDI_PCP_PLB_P2P
)
port map(
Bus2IP_Addr => Bus2PDI_PCP_Addr( C_PDI_PCP_PLB_AWIDTH-1 downto 0 ),
Bus2IP_BE => Bus2PDI_PCP_BE( (C_PDI_PCP_PLB_DWIDTH/8)-1 downto 0 ),
Bus2IP_CS => Bus2PDI_PCP_CS( 0 downto 0 ),
Bus2IP_Clk => Bus2PDI_PCP_Clk,
Bus2IP_Data => Bus2PDI_PCP_Data( C_PDI_PCP_PLB_DWIDTH-1 downto 0 ),
Bus2IP_RNW => Bus2PDI_PCP_RNW,
Bus2IP_Reset => Bus2PDI_PCP_Reset,
IP2Bus_Data => PDI_PCP2Bus_Data( C_PDI_PCP_PLB_DWIDTH-1 downto 0 ),
IP2Bus_Error => PDI_PCP2Bus_Error,
IP2Bus_RdAck => PDI_PCP2Bus_RdAck,
IP2Bus_WrAck => PDI_PCP2Bus_WrAck,
PLB_ABus => PDI_PCP_ABus,
PLB_BE => PDI_PCP_BE( 0 to (C_PDI_PCP_PLB_DWIDTH/8)-1 ),
PLB_MSize => PDI_PCP_MSize,
PLB_PAValid => PDI_PCP_PAValid,
PLB_RNW => PDI_PCP_RNW,
PLB_SAValid => PDI_PCP_SAValid,
PLB_TAttribute => PDI_PCP_TAttribute,
PLB_UABus => PDI_PCP_UABus,
PLB_abort => PDI_PCP_abort,
PLB_busLock => PDI_PCP_busLock,
PLB_lockErr => PDI_PCP_lockErr,
PLB_masterID => PDI_PCP_masterID( 0 to C_PDI_PCP_PLB_MID_WIDTH-1 ),
PLB_rdBurst => PDI_PCP_rdBurst,
PLB_rdPendPri => PDI_PCP_rdPendPri,
PLB_rdPendReq => PDI_PCP_rdPendReq,
PLB_rdPrim => PDI_PCP_rdPrim,
PLB_reqPri => PDI_PCP_reqPri,
PLB_size => PDI_PCP_size,
PLB_type => PDI_PCP_type,
PLB_wrBurst => PDI_PCP_wrBurst,
PLB_wrDBus => PDI_PCP_wrDBus( 0 to C_PDI_PCP_PLB_DWIDTH-1 ),
PLB_wrPendPri => PDI_PCP_wrPendPri,
PLB_wrPendReq => PDI_PCP_wrPendReq,
PLB_wrPrim => PDI_PCP_wrPrim,
SPLB_Clk => PDI_PCP_Clk,
SPLB_Rst => PDI_PCP_Rst,
Sl_MBusy => PDI_PCP_MBusy( 0 to C_PDI_PCP_NUM_MASTERS-1 ),
Sl_MIRQ => PDI_PCP_MIRQ( 0 to C_PDI_PCP_NUM_MASTERS-1 ),
Sl_MRdErr => PDI_PCP_MRdErr( 0 to C_PDI_PCP_NUM_MASTERS-1 ),
Sl_MWrErr => PDI_PCP_MWrErr( 0 to C_PDI_PCP_NUM_MASTERS-1 ),
Sl_SSize => PDI_PCP_SSize,
Sl_addrAck => PDI_PCP_addrAck,
Sl_rdBTerm => PDI_PCP_rdBTerm,
Sl_rdComp => PDI_PCP_rdComp,
Sl_rdDAck => PDI_PCP_rdDAck,
Sl_rdDBus => PDI_PCP_rdDBus( 0 to C_PDI_PCP_PLB_DWIDTH-1 ),
Sl_rdWdAddr => PDI_PCP_rdWdAddr,
Sl_rearbitrate => PDI_PCP_rearbitrate,
Sl_wait => PDI_PCP_wait,
Sl_wrBTerm => PDI_PCP_wrBTerm,
Sl_wrComp => PDI_PCP_wrComp,
Sl_wrDAck => PDI_PCP_wrDAck
);
end generate genPdiPcp;
genPcpPdiLink : if C_GEN_PDI generate
begin
--pdi_pcp assignments
clkPcp <= Bus2PDI_PCP_Clk;
rstPcp <= Bus2PDI_PCP_Reset;
pcp_writedata <= Bus2PDI_PCP_Data;
-- Bus2MAC_PKT_Data(7 downto 0) & Bus2MAC_PKT_Data(15 downto 8) &
-- Bus2MAC_PKT_Data(23 downto 16) & Bus2MAC_PKT_Data(31 downto 24);
pcp_read <= Bus2PDI_PCP_RNW;
pcp_write <= not Bus2PDI_PCP_RNW;
pcp_chipselect <= Bus2PDI_PCP_CS(0);
pcp_byteenable <= Bus2PDI_PCP_BE;
pcp_address <= Bus2PDI_PCP_Addr(14 downto 2);
PDI_PCP2Bus_Data <= pcp_readdata;
-- mbf_readdata(7 downto 0) & mbf_readdata(15 downto 8) &
-- mbf_readdata(23 downto 16) & mbf_readdata(31 downto 24);
PDI_PCP2Bus_RdAck <= pcp_chipselect and pcp_read and not pcp_waitrequest;
PDI_PCP2Bus_WrAck <= pcp_chipselect and pcp_write and not pcp_waitrequest;
PDI_PCP2Bus_Error <= '0';
end generate genPcpPdiLink;
genPdiAp : if (C_GEN_PLB_BUS_IF) generate
begin
PDI_AP_PLB_SINGLE_SLAVE : plbv46_slave_single
generic map (
C_ARD_ADDR_RANGE_ARRAY => (C_PDI_AP_BASE,C_PDI_AP_HIGH),
C_ARD_NUM_CE_ARRAY => (0 => 1),
C_BUS2CORE_CLK_RATIO => 1,
C_FAMILY => C_FAMILY,
C_INCLUDE_DPHASE_TIMER => 0,
C_SIPIF_DWIDTH => C_PDI_AP_PLB_DWIDTH,
C_SPLB_AWIDTH => C_PDI_AP_PLB_AWIDTH,
C_SPLB_DWIDTH => C_PDI_AP_PLB_DWIDTH,
C_SPLB_MID_WIDTH => C_PDI_AP_PLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_PDI_AP_PLB_NUM_MASTERS,
C_SPLB_P2P => C_PDI_AP_PLB_P2P
)
port map(
Bus2IP_Addr => Bus2PDI_AP_Addr( C_PDI_AP_PLB_AWIDTH-1 downto 0 ),
Bus2IP_BE => Bus2PDI_AP_BE( (C_PDI_AP_PLB_DWIDTH/8)-1 downto 0 ),
Bus2IP_CS => Bus2PDI_AP_CS( 0 downto 0 ),
Bus2IP_Clk => Bus2PDI_AP_Clk,
Bus2IP_Data => Bus2PDI_AP_Data( C_PDI_AP_PLB_DWIDTH-1 downto 0 ),
Bus2IP_RNW => Bus2PDI_AP_RNW,
Bus2IP_Reset => Bus2PDI_AP_Reset,
IP2Bus_Data => PDI_AP2Bus_Data( C_PDI_AP_PLB_DWIDTH-1 downto 0 ),
IP2Bus_Error => PDI_AP2Bus_Error,
IP2Bus_RdAck => PDI_AP2Bus_RdAck,
IP2Bus_WrAck => PDI_AP2Bus_WrAck,
PLB_ABus => PDI_AP_ABus,
PLB_BE => PDI_AP_BE( 0 to (C_PDI_AP_PLB_DWIDTH/8)-1 ),
PLB_MSize => PDI_AP_MSize,
PLB_PAValid => PDI_AP_PAValid,
PLB_RNW => PDI_AP_RNW,
PLB_SAValid => PDI_AP_SAValid,
PLB_TAttribute => PDI_AP_TAttribute,
PLB_UABus => PDI_AP_UABus,
PLB_abort => PDI_AP_abort,
PLB_busLock => PDI_AP_busLock,
PLB_lockErr => PDI_AP_lockErr,
PLB_masterID => PDI_AP_masterID( 0 to C_PDI_AP_PLB_MID_WIDTH-1 ),
PLB_rdBurst => PDI_AP_rdBurst,
PLB_rdPendPri => PDI_AP_rdPendPri,
PLB_rdPendReq => PDI_AP_rdPendReq,
PLB_rdPrim => PDI_AP_rdPrim,
PLB_reqPri => PDI_AP_reqPri,
PLB_size => PDI_AP_size,
PLB_type => PDI_AP_type,
PLB_wrBurst => PDI_AP_wrBurst,
PLB_wrDBus => PDI_AP_wrDBus( 0 to C_PDI_AP_PLB_DWIDTH-1 ),
PLB_wrPendPri => PDI_AP_wrPendPri,
PLB_wrPendReq => PDI_AP_wrPendReq,
PLB_wrPrim => PDI_AP_wrPrim,
SPLB_Clk => PDI_AP_Clk,
SPLB_Rst => PDI_AP_Rst,
Sl_MBusy => PDI_AP_MBusy( 0 to C_PDI_AP_PLB_NUM_MASTERS-1 ),
Sl_MIRQ => PDI_AP_MIRQ( 0 to C_PDI_AP_PLB_NUM_MASTERS-1 ),
Sl_MRdErr => PDI_AP_MRdErr( 0 to C_PDI_AP_PLB_NUM_MASTERS-1 ),
Sl_MWrErr => PDI_AP_MWrErr( 0 to C_PDI_AP_PLB_NUM_MASTERS-1 ),
Sl_SSize => PDI_AP_SSize,
Sl_addrAck => PDI_AP_addrAck,
Sl_rdBTerm => PDI_AP_rdBTerm,
Sl_rdComp => PDI_AP_rdComp,
Sl_rdDAck => PDI_AP_rdDAck,
Sl_rdDBus => PDI_AP_rdDBus( 0 to C_PDI_AP_PLB_DWIDTH-1 ),
Sl_rdWdAddr => PDI_AP_rdWdAddr,
Sl_rearbitrate => PDI_AP_rearbitrate,
Sl_wait => PDI_AP_wait,
Sl_wrBTerm => PDI_AP_wrBTerm,
Sl_wrComp => PDI_AP_wrComp,
Sl_wrDAck => PDI_AP_wrDAck
);
end generate genPdiAp;
genApPdiLink : if C_GEN_PDI generate
begin
--ap_pcp assignments
clkAp <= Bus2PDI_AP_Clk;
rstAp <= Bus2PDI_AP_Reset;
ap_writedata <= Bus2PDI_AP_Data;
-- Bus2MAC_PKT_Data(7 downto 0) & Bus2MAC_PKT_Data(15 downto 8) &
-- Bus2MAC_PKT_Data(23 downto 16) & Bus2MAC_PKT_Data(31 downto 24);
ap_read <= Bus2PDI_AP_RNW;
ap_write <= not Bus2PDI_AP_RNW;
ap_chipselect <= Bus2PDI_AP_CS(0);
ap_byteenable <= Bus2PDI_AP_BE;
ap_address <= Bus2PDI_AP_Addr(14 downto 2);
PDI_AP2Bus_Data <= ap_readdata;
-- mbf_readdata(7 downto 0) & mbf_readdata(15 downto 8) &
-- mbf_readdata(23 downto 16) & mbf_readdata(31 downto 24);
PDI_AP2Bus_RdAck <= ap_chipselect and ap_read and not ap_waitrequest;
PDI_AP2Bus_WrAck <= ap_chipselect and ap_write and not ap_waitrequest;
PDI_AP2Bus_Error <= '0';
end generate genApPdiLink;
genSimpleIoSignals : if C_GEN_SIMPLE_IO generate
begin
--SMP_PCP assignments
clkPcp <= Bus2SMP_PCP_Clk;
rstPcp <= Bus2SMP_PCP_Reset;
smp_writedata <= Bus2SMP_PCP_Data;
smp_read <= Bus2SMP_PCP_RNW and Bus2SMP_PCP_CS(0);
smp_write <= not Bus2SMP_PCP_RNW and Bus2SMP_PCP_CS(0);
smp_chipselect <= Bus2SMP_PCP_CS(0);
smp_byteenable <= Bus2SMP_PCP_BE;
smp_address <= Bus2SMP_PCP_Addr(2);
SMP_PCP2Bus_Data <= smp_readdata;
SMP_PCP2Bus_RdAck <= smp_chipselect and smp_read and not smp_waitrequest;
SMP_PCP2Bus_WrAck <= smp_chipselect and smp_write and not smp_waitrequest;
SMP_PCP2Bus_Error <= '0';
end generate genSimpleIoSignals;
genSmpIo : if (C_GEN_SIMPLE_IO) generate
begin
SMP_IO_PLB_SINGLE_SLAVE : plbv46_slave_single
generic map (
C_ARD_ADDR_RANGE_ARRAY => (C_SMP_PCP_BASE,C_SMP_PCP_HIGH),
C_ARD_NUM_CE_ARRAY => (0 => 1),
C_BUS2CORE_CLK_RATIO => 1,
C_FAMILY => C_FAMILY,
C_INCLUDE_DPHASE_TIMER => 0,
C_SIPIF_DWIDTH => C_SMP_PCP_PLB_DWIDTH,
C_SPLB_AWIDTH => C_SMP_PCP_PLB_AWIDTH,
C_SPLB_DWIDTH => C_SMP_PCP_PLB_DWIDTH,
C_SPLB_MID_WIDTH => C_SMP_PCP_PLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_SMP_PCP_PLB_NUM_MASTERS,
C_SPLB_P2P => C_SMP_PCP_PLB_P2P
)
port map(
Bus2IP_Addr => Bus2SMP_PCP_Addr( C_SMP_PCP_PLB_AWIDTH-1 downto 0 ),
Bus2IP_BE => Bus2SMP_PCP_BE( (C_SMP_PCP_PLB_DWIDTH/8)-1 downto 0 ),
Bus2IP_CS => Bus2SMP_PCP_CS( 0 downto 0 ),
Bus2IP_Clk => Bus2SMP_PCP_Clk,
Bus2IP_Data => Bus2SMP_PCP_Data( C_SMP_PCP_PLB_DWIDTH-1 downto 0 ),
Bus2IP_RNW => Bus2SMP_PCP_RNW,
Bus2IP_Reset => Bus2SMP_PCP_Reset,
IP2Bus_Data => SMP_PCP2Bus_Data( C_SMP_PCP_PLB_DWIDTH-1 downto 0 ),
IP2Bus_Error => SMP_PCP2Bus_Error,
IP2Bus_RdAck => SMP_PCP2Bus_RdAck,
IP2Bus_WrAck => SMP_PCP2Bus_WrAck,
PLB_ABus => SMP_PCP_ABus,
PLB_BE => SMP_PCP_BE( 0 to (C_SMP_PCP_PLB_DWIDTH/8)-1 ),
PLB_MSize => SMP_PCP_MSize,
PLB_PAValid => SMP_PCP_PAValid,
PLB_RNW => SMP_PCP_RNW,
PLB_SAValid => SMP_PCP_SAValid,
PLB_TAttribute => SMP_PCP_TAttribute,
PLB_UABus => SMP_PCP_UABus,
PLB_abort => SMP_PCP_abort,
PLB_busLock => SMP_PCP_busLock,
PLB_lockErr => SMP_PCP_lockErr,
PLB_masterID => SMP_PCP_masterID( 0 to C_SMP_PCP_PLB_MID_WIDTH-1 ),
PLB_rdBurst => SMP_PCP_rdBurst,
PLB_rdPendPri => SMP_PCP_rdPendPri,
PLB_rdPendReq => SMP_PCP_rdPendReq,
PLB_rdPrim => SMP_PCP_rdPrim,
PLB_reqPri => SMP_PCP_reqPri,
PLB_size => SMP_PCP_size,
PLB_type => SMP_PCP_type,
PLB_wrBurst => SMP_PCP_wrBurst,
PLB_wrDBus => SMP_PCP_wrDBus( 0 to C_SMP_PCP_PLB_DWIDTH-1 ),
PLB_wrPendPri => SMP_PCP_wrPendPri,
PLB_wrPendReq => SMP_PCP_wrPendReq,
PLB_wrPrim => SMP_PCP_wrPrim,
SPLB_Clk => SMP_PCP_Clk,
SPLB_Rst => SMP_PCP_Rst,
Sl_MBusy => SMP_PCP_MBusy( 0 to C_SMP_PCP_PLB_NUM_MASTERS-1 ),
Sl_MIRQ => SMP_PCP_MIRQ( 0 to C_SMP_PCP_PLB_NUM_MASTERS-1 ),
Sl_MRdErr => SMP_PCP_MRdErr( 0 to C_SMP_PCP_PLB_NUM_MASTERS-1 ),
Sl_MWrErr => SMP_PCP_MWrErr( 0 to C_SMP_PCP_PLB_NUM_MASTERS-1 ),
Sl_SSize => SMP_PCP_SSize,
Sl_addrAck => SMP_PCP_addrAck,
Sl_rdBTerm => SMP_PCP_rdBTerm,
Sl_rdComp => SMP_PCP_rdComp,
Sl_rdDAck => SMP_PCP_rdDAck,
Sl_rdDBus => SMP_PCP_rdDBus( 0 to C_SMP_PCP_PLB_DWIDTH-1 ),
Sl_rdWdAddr => SMP_PCP_rdWdAddr,
Sl_rearbitrate => SMP_PCP_rearbitrate,
Sl_wait => SMP_PCP_wait,
Sl_wrBTerm => SMP_PCP_wrBTerm,
Sl_wrComp => SMP_PCP_wrComp,
Sl_wrDAck => SMP_PCP_wrDAck
);
end generate genSmpIo;
end struct;
| gpl-2.0 | f99dba5edc46e42ba02228a05e84176c | 0.608236 | 2.995966 | false | false | false | false |
takeshineshiro/fpga_linear_128 | matchfilter_ast.vhd | 1 | 6,827 | -- ================================================================================
-- Legal Notice: Copyright (C) 1991-2006 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera. Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors. No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
-- ================================================================================
--
-- Generated by: FIR Compiler 9.0
-- Generated on: 2015-11-11 15:52:10
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library auk_dspip_lib;
use auk_dspip_lib.auk_dspip_lib_pkg_fir_90.all;
entity matchfilter_ast is
port(
clk : in std_logic;
reset_n : in std_logic;
ast_sink_ready : out std_logic;
ast_source_data : out std_logic_vector (30 -1 downto 0);
ast_sink_data : in std_logic_vector (15 -1 downto 0);
ast_sink_valid : in std_logic;
ast_source_valid : out std_logic;
ast_source_ready : in std_logic;
ast_sink_error : in std_logic_vector (1 downto 0);
ast_source_error : out std_logic_vector (1 downto 0)
);
attribute altera_attribute : string;
attribute altera_attribute of matchfilter_ast:entity is "-name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 10036";
end matchfilter_ast;
-- Warnings Suppression On
-- altera message_off 10036
architecture struct of matchfilter_ast is
signal sink_packet_error : std_logic_vector(1 downto 0);
signal data_in : std_logic_vector(15 -1 downto 0);
signal data_out : std_logic_vector(30 -1 downto 0);
signal core_out : std_logic_vector(30 -1 downto 0);
signal ready : std_logic;
signal reset_fir : std_logic;
signal sink_ready_ctrl : std_logic;
signal sink_stall : std_logic;
signal source_packet_error : std_logic_vector(1 downto 0);
signal source_stall : std_logic;
signal source_valid_ctrl : std_logic;
signal stall : std_logic;
signal valid : std_logic;
signal core_valid : std_logic;
signal enable_in : std_logic;
signal stall_delayed : std_logic;
constant ENABLE_PIPELINE_DEPTH_c : natural := 0;
component matchfilter_st is
port (
rst : in std_logic;
clk : in std_logic;
clk_en : in std_logic;
rdy_to_ld : out std_logic;
done : out std_logic;
data_in : in std_logic_vector(15 - 1 downto 0);
fir_result : out std_logic_vector(30 - 1 downto 0));
end component matchfilter_st;
begin
sink : auk_dspip_avalon_streaming_sink_fir_90
generic map (
WIDTH_g => 15,
PACKET_SIZE_g => 1,
FIFO_DEPTH_g => 7,
FAMILY_g => "Cyclone III",
MEM_TYPE_g => "Auto")
port map (
clk => clk,
reset_n => reset_n,
data => data_in,
sink_ready_ctrl => sink_ready_ctrl,
sink_stall => sink_stall,
packet_error => sink_packet_error,
at_sink_ready => ast_sink_ready,
at_sink_valid => ast_sink_valid,
at_sink_data => ast_sink_data,
at_sink_error => ast_sink_error);
source : auk_dspip_avalon_streaming_source_fir_90
generic map (
WIDTH_g => 30,
packet_size_g => 1)
port map (
clk => clk,
reset_n => reset_n,
data => data_out,
source_valid_ctrl => source_valid_ctrl,
design_stall => stall_delayed,
source_stall => source_stall,
packet_error => source_packet_error,
at_source_ready => ast_source_ready,
at_source_valid => ast_source_valid,
at_source_data => ast_source_data,
at_source_error => ast_source_error);
intf_ctrl : auk_dspip_avalon_streaming_controller_fir_90
port map (
clk => clk,
ready => ready,
reset_n => reset_n,
sink_packet_error => sink_packet_error,
sink_stall => sink_stall,
source_stall => source_stall,
valid => valid,
reset_design => reset_fir,
sink_ready_ctrl => sink_ready_ctrl,
source_packet_error => source_packet_error,
source_valid_ctrl => source_valid_ctrl,
stall => stall);
fircore: matchfilter_st
port map (
rst => reset_fir,
clk => clk,
clk_en => enable_in,
rdy_to_ld => ready,
done => core_valid,
data_in => data_in,
fir_result => core_out);
data_out <= core_out;
valid <= core_valid;
enable_in <= not stall;
no_enable_pipeline: if ENABLE_PIPELINE_DEPTH_c = 0 generate
stall_delayed <= stall;
end generate no_enable_pipeline;
enable_pipeline: if ENABLE_PIPELINE_DEPTH_c > 0 generate
delay_core_enable : process (clk, reset_n)
variable stall_delay : std_logic_vector(ENABLE_PIPELINE_DEPTH_c downto 0);
begin -- process delay_core_enable
if reset_n = '0' then
stall_delay := (others => '0');
elsif rising_edge(clk) then
stall_delay := stall_delay(stall_delay'high-1 downto 0) & stall;
end if;
stall_delayed <= stall_delay(stall_delay'high);
end process delay_core_enable;
end generate enable_pipeline;
end struct;
| mit | b8c4b6de82dd1fbfef346c04a261a240 | 0.60583 | 3.816098 | false | false | false | false |
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`protect end_protected
| gpl-3.0 | 453540348fe4f501487bdc70ff266cea | 0.945846 | 1.827634 | false | false | false | false |
dummylink/plnk_fpga-stack | Examples/xilinx_microblaze/avnet_lx9/pcores/plb_powerlink_v1_00_a/hdl/vhdl/pdi_apIrqGen.vhd | 5 | 4,944 | ------------------------------------------------------------------------------------------------------------------------
-- Process Data Interface (PDI) ap irq generator
--
-- Copyright (C) 2011 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2011-09-14 V0.01 zelenkaj extract from pdi.vhd
------------------------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity apIrqGen is
generic (
genOnePdiClkDomain_g : boolean := false
);
port (
--CLOCK DOMAIN PCP
clkA : in std_logic;
rstA : in std_logic;
irqA : in std_logic; --toggle from MAC
enableA : in std_logic; --APIRQ_CONTROL / IRQ_En
modeA : in std_logic; --APIRQ_CONTROL / IRQ_MODE
setA : in std_logic; --APIRQ_CONTROL / IRQ_SET
--CLOCK DOMAIN AP
clkB : in std_logic;
rstB : in std_logic;
ackB : in std_logic; --APIRQ_CONTROL / IRQ_ACK
irqB : out std_logic
);
end entity apIrqGen;
architecture rtl of apIrqGen is
type fsm_t is (wait4event, setIrq, wait4ack);
signal fsm : fsm_t;
signal enable, mode, irq, toggle, set : std_logic;
begin
--everything is done in clkB domain!
theFsm : process(clkB, rstB)
begin
if rstB = '1' then
irqB <= '0';
fsm <= wait4event;
elsif clkB = '1' and clkB'event then
if enable = '1' then
case fsm is
when wait4event =>
if mode = '0' and set = '1' then
fsm <= setIrq;
elsif mode = '1' and irq = '1' then
fsm <= setIrq;
else
fsm <= wait4event;
end if;
when setIrq =>
irqB <= '1';
fsm <= wait4ack;
when wait4ack =>
if ackB = '1' then
irqB <= '0';
fsm <= wait4event;
else
fsm <= wait4ack;
end if;
end case;
else
irqB <= '0';
fsm <= wait4event;
end if;
end if;
end process;
syncEnable : entity work.sync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
port map (
din => enableA,
dout => enable,
clk => clkB,
rst => rstB
);
syncSet : entity work.slow2fastSync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
port map (
dataSrc => setA,
dataDst => set,
clkSrc => clkA,
rstSrc => rstA,
clkDst => clkB,
rstDst => rstB
);
syncMode : entity work.sync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
port map (
din => modeA,
dout => mode,
clk => clkB,
rst => rstB
);
syncToggle : entity work.sync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
port map (
din => irqA,
dout => toggle,
clk => clkB,
rst => rstB
);
toggleEdgeDet : entity work.edgeDet
port map (
din => toggle,
rising => open,
falling => open,
any => irq,
clk => clkB,
rst => rstB
);
end architecture rtl; | gpl-2.0 | 29996483e16e7c9c37bca5fbcfa7de4c | 0.554005 | 3.673105 | false | false | false | false |
DougFirErickson/parallella-hw | fpga/ip/xilinx/fifo_async_103x32/fifo_generator_v12_0/hdl/fifo_generator_v12_0_defaults.vhd | 6 | 30,145 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 20576)
`protect data_block
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`protect end_protected
| gpl-3.0 | 41cc9572d3ffaedb32644e54b6dbbfa0 | 0.945928 | 1.845424 | false | false | false | false |
hgunicamp/Mips8B | src_design/mips8b_io_system.vhdl | 1 | 4,978 | Library Ieee;
Use Ieee.Std_Logic_1164.all;
Use Work.MIPS8B_Base.all;
Entity MIPS8B_IO_System is
Generic(N: Natural := 8);
Port(clock: in Std_Logic;
Reset_n: in Std_Logic;
-- Controle do endereço fornecido pelo sistema
en_RMem: in Std_Logic;
en_RMem_Inc: in Std_Logic;
crt_Mux_IO: in Std_Logic;
crt_MEM: in MemoryOP;
-- Controle dos Dados de I/O.
en_RData_in: in Std_Logic;
en_RData_out: in Std_Logic;
-- Valores de endereço para transações de I/O.
out_PC: in Std_Logic_Vector(N-3 downto 0);
out_DPath: in Std_Logic_Vector(N-1 downto 0);
in_Data: in Std_Logic_Vector(N-1 downto 0);
-- Registradores para dados de I/O.
RMem: out Std_Logic_Vector(N-1 downto 0);
RData_in: out Std_Logic_Vector(N-1 downto 0);
RData_out: out Std_Logic_Vector(N-1 downto 0);
-- Interface de controle.
Cmd: out Std_Logic_Vector(1 downto 0);
CmdAccept: in Std_Logic;
IO_OK: out Std_Logic);
End Entity MIPS8B_IO_System;
Architecture behave of MIPS8B_IO_System is
Use Ieee.Numeric_Std.all;
-- Sinais para representação do estado.
Signal IO_State, next_IO_State: IOSTD;
-- Sinal para o próximo endereço a ser acessado.
Signal int_RMem, next_RMem: Unsigned(N-1 downto 0);
Begin
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Lógica para o próximo estado.
NEXT_IOS_COMB: Process(crt_MEM,CmdAccept,IO_State)
Variable Temp_next_IO_State: IOSTD;
Begin
Temp_next_IO_State := IO_State;
Case IO_State is
When ioIDLE =>
If crt_MEM = mcREAD then
Temp_next_IO_State := ioREAD;
ElsIf crt_MEM = mcWRITE then
Temp_next_IO_State := ioWRITE;
End If;
When ioREAD|ioWRITE =>
If CmdAccept = ocpDVA_little then
Temp_next_IO_State := ioIO_OK;
End If;
When Others =>
If crt_MEM = mcREAD then
Temp_next_IO_State := ioREAD;
Else
Temp_next_IO_State := ioIDLE;
End If;
End Case;
next_IO_State <= Temp_next_IO_State;
End Process NEXT_IOS_COMB;
---------------------------------------------------------------------------
NEXT_IOS_SYNC: Process
Begin
Wait Until clock'event and clock = '1';
If Reset_n = '0' then
IO_State <= ioIDLE;
Else
IO_State <= next_IO_State;
End If;
End Process NEXT_IOS_SYNC;
---------------------------------------------------------------------------
DECOD_STATE: Process(IO_State)
Variable Temp_Cmd: Std_Logic_Vector(1 downto 0);
Variable Temp_IO_OK: Std_Logic;
Begin
Temp_Cmd := ocpIDLE_little;
Temp_IO_OK := '0';
Case IO_State is
When ioREAD => Temp_Cmd := ocpRD_little;
When ioWRITE => Temp_Cmd := ocpWR_little;
When ioIO_OK => Temp_IO_OK := '1';
When Others =>
End Case;
Cmd <= Temp_Cmd;
IO_OK <= Temp_IO_OK;
End Process DECOD_STATE;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Lógica para o próximo endereço.
RMem <= Std_Logic_Vector(int_RMem);
NEXT_RMEM_COMB: Process(int_RMem,crt_Mux_IO,en_RMem,out_PC,out_DPath)
Variable Temp_next_RMem: Unsigned(N-1 downto 0);
Variable Temp_control: Unsigned(1 downto 0);
Begin
Temp_control := crt_Mux_IO & en_RMem;
Case Temp_control is
When "01" => Temp_next_RMem := Unsigned(out_PC & "00");
When "11" => Temp_next_RMem := Unsigned(out_DPath);
When Others => Temp_next_RMem := int_RMem + 1;
End Case;
next_RMem <= Temp_next_RMem;
End Process NEXT_RMEM_COMB;
---------------------------------------------------------------------------
RCONTROL_SYNC: Process
Begin
Wait Until clock'event and clock = '1';
If en_RMem = '1' or en_RMem_Inc = '1' then
int_RMem <= next_RMem;
End If;
If en_RData_in = '1' and CmdAccept = '1' then
RData_in <= in_Data;
End If;
If en_RData_out = '1' then
RData_out <= out_DPath;
End If;
End Process RCONTROL_SYNC;
---------------------------------------------------------------------------
End Architecture behave;
Configuration MIPS8B_IO_System_behave_conf of MIPS8B_IO_System is
For behave
End For;
End Configuration MIPS8B_IO_System_behave_conf;
| unlicense | 79271991e986adfbe3b1cd3663e312e5 | 0.477946 | 3.752834 | false | false | false | false |
estadofinito/biblioteca-vhdl | todos-los-archivos/servo_pwm_clk64kHz_tb.vhd | 2 | 1,493 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY servo_pwm_clk64kHz_tb IS
END servo_pwm_clk64kHz_tb;
ARCHITECTURE behavior OF servo_pwm_clk64kHz_tb IS
-- Unidad bajo prueba.
COMPONENT servo_pwm_clk64kHz
PORT(
clk : IN std_logic;
reset : IN std_logic;
pos : IN std_logic_vector(6 downto 0);
servo : OUT std_logic
);
END COMPONENT;
-- Entradas.
signal clk : std_logic := '0';
signal reset: std_logic := '0';
signal pos : std_logic_vector(6 downto 0) := (others => '0');
-- Salidas.
signal servo : std_logic;
-- Definición del reloj.
constant clk_period : time := 10 ns;
BEGIN
-- Instancia de la unidad bajo prueba.
uut: servo_pwm_clk64kHz PORT MAP (
clk => clk,
reset => reset,
pos => pos,
servo => servo
);
-- Definición del proceso de reloj.
clk_process :process begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Procesamiento de estímulos.
proceso_estimulos: process begin
reset <= '1';
wait for 50 ns;
reset <= '0';
wait for 50 ns;
pos <= "0000000";
wait for 20 ms;
pos <= "0101000";
wait for 20 ms;
pos <= "1010000";
wait for 20 ms;
pos <= "1111000";
wait for 20 ms;
pos <= "1111111";
wait;
end process;
END; | lgpl-2.1 | a6d92152f0deabd1e6128eba65fa94eb | 0.532215 | 3.69727 | false | false | false | false |
dummylink/plnk_fpga-stack | Examples/xilinx_microblaze/avnet_lx9/pcores/plb_powerlink_v1_00_a/hdl/vhdl/OpenFILTER.vhd | 5 | 15,451 | ------------------------------------------------------------------------------------------------------------------------
-- OpenFILTER
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Note: RxDv and RxDat have to be synchron to Clk
-- The following Conditions are checked:
-- RxDV >163.64µsec HIGH -> invalid
-- RxDV <0.64µsec LOW -> invalid
-- RxDV 4x <5.12µsec HIGH -> invalid
-- RxDV >5.12µsec HIGH -> valid
-- RxErr HIGH -> invalid
-- if invalid deactivation of port, until RxDv and RxErr > 10.24µsec low
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2009-08-07 V0.01 Converted from V1.1 to first official version.
-- 2011-07-23 V0.10 zelenkaj Consideration of RX Error signal and jitter (converted from V2.3)
-- 2011-08-03 V0.11 zelenkaj translated comments
-- 2011-11-18 V0.12 zelenkaj bypass filter by generic
-- 2011-11-28 V0.13 zelenkaj Changed reset level to high-active
------------------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
ENTITY openFILTER is
Generic (
bypassFilter : boolean := false
);
Port ( Rst : in std_logic;
Clk : in std_logic;
nCheckShortFrames : in std_logic := '0'; -- Rx Port von Hub;
RxDvIn : in std_logic;
RxDatIn : in std_logic_vector(1 downto 0);
RxDvOut : out std_logic;
RxDatOut : out std_logic_vector(1 downto 0);
TxEnIn : in std_logic;
TxDatIn : in std_logic_vector(1 downto 0);
TxEnOut : out std_logic;
TxDatOut : out std_logic_vector(1 downto 0);
RxErr : in std_logic := '0'
);
END ENTITY openFILTER;
ARCHITECTURE rtl OF openFILTER IS
type aRxSet is record
RxDv : std_logic;
RxDat: std_logic_vector(1 downto 0);
end record;
type aRxSetArr is array (3 downto 0) of aRxSet;
signal Cnt_Rx_high : std_logic_vector(13 downto 0);
signal Cnt_RxHigh_ToShort : std_logic_vector(1 downto 0);
signal RxHigh_ToShort : std_logic;
signal RxLow_ToShort : std_logic;
signal RxHigh_ToShort_temp : std_logic;
signal RxLow_ToShort_temp : std_logic;
signal RxLowGap_ToShort : std_logic;
signal RxLowGap_ToShort_temp : std_logic;
signal RxDataValidLatch : std_logic;
signal PortIsEnable : std_logic;
signal RxErrOccur : std_logic;
signal RxAnyError : std_logic;
signal RxTxNotActive : std_logic;
signal DisablePort : std_logic;
signal RxDel : aRxSetArr;
BEGIN
disFilter : if bypassFilter generate
begin
RxDvOut <= RxDvIn;
RxDatOut <= RxDatIn;
TxEnOut <= TxEnIn;
TxDatOut <= TxDatIn;
end generate;
enFilter : if not bypassFilter generate
begin
-- IN --
RxDel(0).RxDv <= RxDvIn;
RxDel(0).RxDat <= RxDatIn;
RxDvOut <= RxDel(3).RxDv and PortIsEnable when RxLowGap_ToShort = '1' else
RxDel(1).RxDv and PortIsEnable;
RxDatOut <= RxDel(3).RxDat and (PortIsEnable & PortIsEnable) when RxLowGap_ToShort = '1' else
RxDel(1).RxDat and (PortIsEnable & PortIsEnable);
TxEnOut <= TxEnIn and PortIsEnable;
TxDatOut <= TxDatIn and (PortIsEnable & PortIsEnable);
RxAnyError <= '1' when (Cnt_Rx_high(Cnt_Rx_high'high) = '1') or (RxHigh_ToShort = '1') or (RxLow_ToShort = '1') or (RxErr = '1') or (RxErrOccur = '1') else
'0';
RxTxNotActive <= '1' when (RxDvIn = '0') and (RxDel(1).RxDv = '0') and (RxDel(2).RxDv = '0') and (TxEnIn = '0') and (TxDatIn = "00") else
'0';
-- Port is allowed to be active if RX_DV is not active
PortIsEnable <= '1' when Rst = '1' else
'0' when (RxAnyError = '1') or (DisablePort = '1') else
'1';
do: PROCESS (Rst, Clk)
BEGIN
if Rst = '1' then
Cnt_RxHigh_ToShort <= (others => '0');
RxHigh_ToShort <= '0'; RxHigh_ToShort_temp <= '0';
RxLow_ToShort <= '0'; RxLow_ToShort_temp <= '0';
RxLowGap_ToShort <= '0'; RxLowGap_ToShort_temp <= '0';
RxDel(3 downto 1) <= (others => ('0',"00"));
RxDataValidLatch <= '0';
Cnt_Rx_high <= (others => '0');
RxErrOccur <= '0';
DisablePort <= '0';
elsif rising_edge(Clk) then
RxDel(1) <= RxDel(0);
RxDel(2) <= RxDel(1);
RxDel(3) <= RxDel(2);
RxDataValidLatch <= RxDel(1).RxDv or RxDel(2).RxDv;
if (DisablePort = '0') and (RxAnyError = '1') then DisablePort <= '1';
elsif (DisablePort = '1') and (RxAnyError = '0') and (RxTxNotActive = '1') then DisablePort <= '0';
else DisablePort <= DisablePort;
end if;
----------------------------------------------- Pending Error: Block Port for at least 10.24 usec -----------------------------------------------
if RxErrOccur = '1' then
if RxErr = '1' then -- phy error
Cnt_Rx_high <= (others => '0');
else -- other error
if Cnt_Rx_high(13) = '0' then Cnt_Rx_high <= Cnt_Rx_high + 1; -- wait for 163.84 usec
else RxErrOccur <= '0';
Cnt_Rx_high <= (others => '0');
end if;
end if;
----------------------------------------------- Phy Error -----------------------------------------------
elsif RxErr = '1' then
Cnt_Rx_high <= (others => '0'); -- -> block
RxErrOccur <= '1';
----------------------------------------------- RxDv = 1 -----------------------------------------------
elsif RxDel(1).RxDv = '1' or RxDel(2).RxDv = '1' then
if RxLow_ToShort_temp = '1' then -- if previous Low Phase too short
RxLow_ToShort_temp <= '0'; --> reset temp error
RxLow_ToShort <= '1'; --> set RxLow_ToShort Error !!!
end if;
if RxDataValidLatch = '0' then -- rising_edge of RxDv
Cnt_Rx_high <= (others => '0'); --> reset counter
RxHigh_ToShort_temp <= '1'; --> set temp error
else
if Cnt_Rx_high(13) = '0' then Cnt_Rx_high <= Cnt_Rx_high + 1; end if; -- 163.84 usec (maximum size of frames)
if Cnt_Rx_high(8) = '1' then RxHigh_ToShort_temp <= '0'; end if; -- 5.12 usec (minimum size of frames)
end if; --> reset temp error
----------------------------------------------- RxDv = 0 -----------------------------------------------
elsif RxDel(1).RxDv = '0' or RxDel(2).RxDv = '0' then
if RxDataValidLatch = '1' then -- falling_edge of RxDv
if RxHigh_ToShort_temp = '1' then -- if previous High Phase too short
if Cnt_RxHigh_ToShort /= "11" then Cnt_RxHigh_ToShort <= Cnt_RxHigh_ToShort + 1; --> count Occations
RxHigh_ToShort <= '0'; -- if less than 4 short Frames in a Row -> no error
else RxHigh_ToShort <= '1'; -- else -> RxHigh_ToShort Error !!
end if;
else -- if no error
Cnt_RxHigh_ToShort <= (others => '0'); --> reset Short Frame Counter
RxHigh_ToShort <= '0';
end if;
RxLow_ToShort_temp <= '1'; -- set temp error
RxHigh_ToShort_temp <= '0'; -- reset previous temp error
RxLowGap_ToShort <= '0';
RxLowGap_ToShort_temp <= '1';
Cnt_Rx_high <= "00000000000001"; -- reset Counter (=Low Counter)
else -- no edge
if Cnt_Rx_high(5) = '1' then RxLow_ToShort_temp <= '0'; end if; -- 0.64 usec (minimum size of inter frame gap) -> reset tmp error
if Cnt_Rx_high(9) = '0' then Cnt_Rx_high <= Cnt_Rx_high + 1; -- For 10.24 usec no Frame
else RxHigh_ToShort <= '0'; --> Reset All Errors
RxLow_ToShort <= '0';
end if;
if Cnt_Rx_high(5 downto 1) = "10111" then RxLowGap_ToShort_temp <= '0'; end if; -- 920 ns
if RxLowGap_ToShort_temp = '1' and RxDvIn = '1' then RxLowGap_ToShort <= '1'; end if; -- FrameGap > 940 ns -> Insert 2 Clks Delay to Rx
end if;
end if;
end if;
END PROCESS do;
end generate;
END rtl;
| gpl-2.0 | 191e71199c2e4f64a4364d66b33f959e | 0.354475 | 5.359348 | false | false | false | false |
JuanMarcosRamirez/WeightedMedianDisenoLogico | misc/Adicionales/Programador_StrataFlash_modificado/Ensamblador/ROM_form.vhd | 1 | 12,433 | ROM_form.vhd
Ken Chapman (Xilinx Ltd) July 2003
This is the VHDL template file for the KCPSM3 assembler.
It is used to configure a Spartan-3, Virtex-II or Virtex-IIPRO block RAM to act as
a single port program ROM.
This VHDL file is not valid as input directly into a synthesis or simulation tool.
The assembler will read this template and insert the data required to complete the
definition of program ROM and write it out to a new '.vhd' file associated with the
name of the original '.psm' file being assembled.
This template can be modified to define alternative memory definitions such as dual port.
However, you are responsible for ensuring the template is correct as the assembler does
not perform any checking of the VHDL.
The assembler identifies all text enclosed by {} characters, and replaces these
character strings. All templates should include these {} character strings for
the assembler to work correctly.
****************************************************************************************
This template defines a block RAM configured in 1024 x 18-bit single port mode and
conneceted to act as a single port ROM.
****************************************************************************************
The next line is used to determine where the template actually starts and must exist.
{begin template}
--
-- Definition of a single port ROM for KCPSM3 program defined by {name}.psm
-- and assmbled using KCPSM3 assembler.
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library unisim;
use unisim.vcomponents.all;
--
--
entity {name} is
Port ( address : in std_logic_vector(9 downto 0);
instruction : out std_logic_vector(17 downto 0);
clk : in std_logic);
end {name};
--
architecture low_level_definition of {name} is
--
-- Attributes to define ROM contents during implementation synthesis.
-- The information is repeated in the generic map for functional simulation
--
attribute INIT_00 : string;
attribute INIT_01 : string;
attribute INIT_02 : string;
attribute INIT_03 : string;
attribute INIT_04 : string;
attribute INIT_05 : string;
attribute INIT_06 : string;
attribute INIT_07 : string;
attribute INIT_08 : string;
attribute INIT_09 : string;
attribute INIT_0A : string;
attribute INIT_0B : string;
attribute INIT_0C : string;
attribute INIT_0D : string;
attribute INIT_0E : string;
attribute INIT_0F : string;
attribute INIT_10 : string;
attribute INIT_11 : string;
attribute INIT_12 : string;
attribute INIT_13 : string;
attribute INIT_14 : string;
attribute INIT_15 : string;
attribute INIT_16 : string;
attribute INIT_17 : string;
attribute INIT_18 : string;
attribute INIT_19 : string;
attribute INIT_1A : string;
attribute INIT_1B : string;
attribute INIT_1C : string;
attribute INIT_1D : string;
attribute INIT_1E : string;
attribute INIT_1F : string;
attribute INIT_20 : string;
attribute INIT_21 : string;
attribute INIT_22 : string;
attribute INIT_23 : string;
attribute INIT_24 : string;
attribute INIT_25 : string;
attribute INIT_26 : string;
attribute INIT_27 : string;
attribute INIT_28 : string;
attribute INIT_29 : string;
attribute INIT_2A : string;
attribute INIT_2B : string;
attribute INIT_2C : string;
attribute INIT_2D : string;
attribute INIT_2E : string;
attribute INIT_2F : string;
attribute INIT_30 : string;
attribute INIT_31 : string;
attribute INIT_32 : string;
attribute INIT_33 : string;
attribute INIT_34 : string;
attribute INIT_35 : string;
attribute INIT_36 : string;
attribute INIT_37 : string;
attribute INIT_38 : string;
attribute INIT_39 : string;
attribute INIT_3A : string;
attribute INIT_3B : string;
attribute INIT_3C : string;
attribute INIT_3D : string;
attribute INIT_3E : string;
attribute INIT_3F : string;
attribute INITP_00 : string;
attribute INITP_01 : string;
attribute INITP_02 : string;
attribute INITP_03 : string;
attribute INITP_04 : string;
attribute INITP_05 : string;
attribute INITP_06 : string;
attribute INITP_07 : string;
--
-- Attributes to define ROM contents during implementation synthesis.
--
attribute INIT_00 of ram_1024_x_18 : label is "{INIT_00}";
attribute INIT_01 of ram_1024_x_18 : label is "{INIT_01}";
attribute INIT_02 of ram_1024_x_18 : label is "{INIT_02}";
attribute INIT_03 of ram_1024_x_18 : label is "{INIT_03}";
attribute INIT_04 of ram_1024_x_18 : label is "{INIT_04}";
attribute INIT_05 of ram_1024_x_18 : label is "{INIT_05}";
attribute INIT_06 of ram_1024_x_18 : label is "{INIT_06}";
attribute INIT_07 of ram_1024_x_18 : label is "{INIT_07}";
attribute INIT_08 of ram_1024_x_18 : label is "{INIT_08}";
attribute INIT_09 of ram_1024_x_18 : label is "{INIT_09}";
attribute INIT_0A of ram_1024_x_18 : label is "{INIT_0A}";
attribute INIT_0B of ram_1024_x_18 : label is "{INIT_0B}";
attribute INIT_0C of ram_1024_x_18 : label is "{INIT_0C}";
attribute INIT_0D of ram_1024_x_18 : label is "{INIT_0D}";
attribute INIT_0E of ram_1024_x_18 : label is "{INIT_0E}";
attribute INIT_0F of ram_1024_x_18 : label is "{INIT_0F}";
attribute INIT_10 of ram_1024_x_18 : label is "{INIT_10}";
attribute INIT_11 of ram_1024_x_18 : label is "{INIT_11}";
attribute INIT_12 of ram_1024_x_18 : label is "{INIT_12}";
attribute INIT_13 of ram_1024_x_18 : label is "{INIT_13}";
attribute INIT_14 of ram_1024_x_18 : label is "{INIT_14}";
attribute INIT_15 of ram_1024_x_18 : label is "{INIT_15}";
attribute INIT_16 of ram_1024_x_18 : label is "{INIT_16}";
attribute INIT_17 of ram_1024_x_18 : label is "{INIT_17}";
attribute INIT_18 of ram_1024_x_18 : label is "{INIT_18}";
attribute INIT_19 of ram_1024_x_18 : label is "{INIT_19}";
attribute INIT_1A of ram_1024_x_18 : label is "{INIT_1A}";
attribute INIT_1B of ram_1024_x_18 : label is "{INIT_1B}";
attribute INIT_1C of ram_1024_x_18 : label is "{INIT_1C}";
attribute INIT_1D of ram_1024_x_18 : label is "{INIT_1D}";
attribute INIT_1E of ram_1024_x_18 : label is "{INIT_1E}";
attribute INIT_1F of ram_1024_x_18 : label is "{INIT_1F}";
attribute INIT_20 of ram_1024_x_18 : label is "{INIT_20}";
attribute INIT_21 of ram_1024_x_18 : label is "{INIT_21}";
attribute INIT_22 of ram_1024_x_18 : label is "{INIT_22}";
attribute INIT_23 of ram_1024_x_18 : label is "{INIT_23}";
attribute INIT_24 of ram_1024_x_18 : label is "{INIT_24}";
attribute INIT_25 of ram_1024_x_18 : label is "{INIT_25}";
attribute INIT_26 of ram_1024_x_18 : label is "{INIT_26}";
attribute INIT_27 of ram_1024_x_18 : label is "{INIT_27}";
attribute INIT_28 of ram_1024_x_18 : label is "{INIT_28}";
attribute INIT_29 of ram_1024_x_18 : label is "{INIT_29}";
attribute INIT_2A of ram_1024_x_18 : label is "{INIT_2A}";
attribute INIT_2B of ram_1024_x_18 : label is "{INIT_2B}";
attribute INIT_2C of ram_1024_x_18 : label is "{INIT_2C}";
attribute INIT_2D of ram_1024_x_18 : label is "{INIT_2D}";
attribute INIT_2E of ram_1024_x_18 : label is "{INIT_2E}";
attribute INIT_2F of ram_1024_x_18 : label is "{INIT_2F}";
attribute INIT_30 of ram_1024_x_18 : label is "{INIT_30}";
attribute INIT_31 of ram_1024_x_18 : label is "{INIT_31}";
attribute INIT_32 of ram_1024_x_18 : label is "{INIT_32}";
attribute INIT_33 of ram_1024_x_18 : label is "{INIT_33}";
attribute INIT_34 of ram_1024_x_18 : label is "{INIT_34}";
attribute INIT_35 of ram_1024_x_18 : label is "{INIT_35}";
attribute INIT_36 of ram_1024_x_18 : label is "{INIT_36}";
attribute INIT_37 of ram_1024_x_18 : label is "{INIT_37}";
attribute INIT_38 of ram_1024_x_18 : label is "{INIT_38}";
attribute INIT_39 of ram_1024_x_18 : label is "{INIT_39}";
attribute INIT_3A of ram_1024_x_18 : label is "{INIT_3A}";
attribute INIT_3B of ram_1024_x_18 : label is "{INIT_3B}";
attribute INIT_3C of ram_1024_x_18 : label is "{INIT_3C}";
attribute INIT_3D of ram_1024_x_18 : label is "{INIT_3D}";
attribute INIT_3E of ram_1024_x_18 : label is "{INIT_3E}";
attribute INIT_3F of ram_1024_x_18 : label is "{INIT_3F}";
attribute INITP_00 of ram_1024_x_18 : label is "{INITP_00}";
attribute INITP_01 of ram_1024_x_18 : label is "{INITP_01}";
attribute INITP_02 of ram_1024_x_18 : label is "{INITP_02}";
attribute INITP_03 of ram_1024_x_18 : label is "{INITP_03}";
attribute INITP_04 of ram_1024_x_18 : label is "{INITP_04}";
attribute INITP_05 of ram_1024_x_18 : label is "{INITP_05}";
attribute INITP_06 of ram_1024_x_18 : label is "{INITP_06}";
attribute INITP_07 of ram_1024_x_18 : label is "{INITP_07}";
--
begin
--
--Instantiate the Xilinx primitive for a block RAM
ram_1024_x_18: RAMB16_S18
--synthesis translate_off
--INIT values repeated to define contents for functional simulation
generic map ( INIT_00 => X"{INIT_00}",
INIT_01 => X"{INIT_01}",
INIT_02 => X"{INIT_02}",
INIT_03 => X"{INIT_03}",
INIT_04 => X"{INIT_04}",
INIT_05 => X"{INIT_05}",
INIT_06 => X"{INIT_06}",
INIT_07 => X"{INIT_07}",
INIT_08 => X"{INIT_08}",
INIT_09 => X"{INIT_09}",
INIT_0A => X"{INIT_0A}",
INIT_0B => X"{INIT_0B}",
INIT_0C => X"{INIT_0C}",
INIT_0D => X"{INIT_0D}",
INIT_0E => X"{INIT_0E}",
INIT_0F => X"{INIT_0F}",
INIT_10 => X"{INIT_10}",
INIT_11 => X"{INIT_11}",
INIT_12 => X"{INIT_12}",
INIT_13 => X"{INIT_13}",
INIT_14 => X"{INIT_14}",
INIT_15 => X"{INIT_15}",
INIT_16 => X"{INIT_16}",
INIT_17 => X"{INIT_17}",
INIT_18 => X"{INIT_18}",
INIT_19 => X"{INIT_19}",
INIT_1A => X"{INIT_1A}",
INIT_1B => X"{INIT_1B}",
INIT_1C => X"{INIT_1C}",
INIT_1D => X"{INIT_1D}",
INIT_1E => X"{INIT_1E}",
INIT_1F => X"{INIT_1F}",
INIT_20 => X"{INIT_20}",
INIT_21 => X"{INIT_21}",
INIT_22 => X"{INIT_22}",
INIT_23 => X"{INIT_23}",
INIT_24 => X"{INIT_24}",
INIT_25 => X"{INIT_25}",
INIT_26 => X"{INIT_26}",
INIT_27 => X"{INIT_27}",
INIT_28 => X"{INIT_28}",
INIT_29 => X"{INIT_29}",
INIT_2A => X"{INIT_2A}",
INIT_2B => X"{INIT_2B}",
INIT_2C => X"{INIT_2C}",
INIT_2D => X"{INIT_2D}",
INIT_2E => X"{INIT_2E}",
INIT_2F => X"{INIT_2F}",
INIT_30 => X"{INIT_30}",
INIT_31 => X"{INIT_31}",
INIT_32 => X"{INIT_32}",
INIT_33 => X"{INIT_33}",
INIT_34 => X"{INIT_34}",
INIT_35 => X"{INIT_35}",
INIT_36 => X"{INIT_36}",
INIT_37 => X"{INIT_37}",
INIT_38 => X"{INIT_38}",
INIT_39 => X"{INIT_39}",
INIT_3A => X"{INIT_3A}",
INIT_3B => X"{INIT_3B}",
INIT_3C => X"{INIT_3C}",
INIT_3D => X"{INIT_3D}",
INIT_3E => X"{INIT_3E}",
INIT_3F => X"{INIT_3F}",
INITP_00 => X"{INITP_00}",
INITP_01 => X"{INITP_01}",
INITP_02 => X"{INITP_02}",
INITP_03 => X"{INITP_03}",
INITP_04 => X"{INITP_04}",
INITP_05 => X"{INITP_05}",
INITP_06 => X"{INITP_06}",
INITP_07 => X"{INITP_07}")
--synthesis translate_on
port map( DI => "0000000000000000",
DIP => "00",
EN => '1',
WE => '0',
SSR => '0',
CLK => clk,
ADDR => address,
DO => instruction(15 downto 0),
DOP => instruction(17 downto 16));
--
end low_level_definition;
--
------------------------------------------------------------------------------------
--
-- END OF FILE {name}.vhd
--
------------------------------------------------------------------------------------
| gpl-3.0 | c018abd95db6137017de60dbcfa0ac8d | 0.585699 | 3.271842 | false | false | false | false |
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`protect end_protected
| gpl-3.0 | 1dc27a4f7df887ce0f86de4c5829d2d3 | 0.948183 | 1.833696 | false | false | false | false |
rflamino/StellaBlue | core/A6500/src/A6500.vhd | 1 | 29,169 | -- A6500 - 6502 CPU and variants
-- Copyright 2006, 2010 Retromaster
--
-- This file is part of A2601.
--
-- A2601 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License,
-- or any later version.
--
-- A2601 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with A2601. If not, see <http://www.gnu.org/licenses/>.
library ieee;
use ieee.std_logic_1164.all;
use work.types.all;
entity A6500 is
port(clk: in std_logic;
rst: in std_logic;
irq: in std_logic;
nmi: in std_logic;
stop: in std_logic;
de: in std_logic;
d: inout std_logic_vector(7 downto 0);
ad: out std_logic_vector(15 downto 0);
r: out std_logic;
-- For debugging and running testbenches
a_dbg: out std_logic_vector(7 downto 0);
x_dbg: out std_logic_vector(7 downto 0);
y_dbg: out std_logic_vector(7 downto 0);
s_dbg: out std_logic_vector(7 downto 0);
pcl_dbg: out std_logic_vector(7 downto 0);
pch_dbg: out std_logic_vector(7 downto 0);
adl_dbg: out std_logic_vector(7 downto 0);
adh_dbg: out std_logic_vector(7 downto 0);
p_dbg: out std_logic_vector(7 downto 0));
end A6500;
architecture arch of A6500 is
signal ir: std_logic_vector(7 downto 0);
signal ir_in: std_logic_vector(7 downto 0);
signal ir_load: std_logic;
signal ir_en: std_logic;
signal ir_rst: std_logic;
component reg8 is
port(clk: in std_logic;
rst: in std_logic;
en: in std_logic;
d_in: in std_logic_vector(7 downto 0);
d_out: out std_logic_vector(7 downto 0));
end component;
component fsm is
port(clk: in std_logic;
rst: in std_logic;
en: in std_logic;
abs_0: in std_logic;
abs_xy: in std_logic;
acc: in std_logic;
bpc_d: in std_logic;
bpc_u: in std_logic;
branch: in std_logic;
brk: in std_logic;
c: in std_logic;
imm: in std_logic;
ind_x: in std_logic;
ind_y: in std_logic;
jmp: in std_logic;
jmp_abs: in std_logic;
jsr: in std_logic;
pull: in std_logic;
push: in std_logic;
push_pull: in std_logic;
rmw: in std_logic;
rti: in std_logic;
rts: in std_logic;
simple: in std_logic;
store: in std_logic;
sub: in std_logic;
taken: in std_logic;
zp: in std_logic;
zp_xy: in std_logic;
branch1_s: out std_logic;
branch_pd_s: out std_logic;
branch_pu_s: out std_logic;
data_s: out std_logic;
data2_s: out std_logic;
data_idx_s: out std_logic;
exec_fetch_op_s: out std_logic;
fetch_adh1_s: out std_logic;
fetch_adh2_s: out std_logic;
fetch_op_s: out std_logic;
fetch_op2_s: out std_logic;
fetch_op_pc_s: out std_logic;
fetch_pch_s: out std_logic;
inc_pc_s: out std_logic;
int_vec1_s: out std_logic;
int_vec2_s: out std_logic;
jmp_abs1_s: out std_logic;
jmp_abs2_s: out std_logic;
modify_s: out std_logic;
rm_write_s: out std_logic;
stack_s: out std_logic;
stack_exec_op_s: out std_logic;
stack_p_s: out std_logic;
stack_pch_s: out std_logic;
stack_pcl_s: out std_logic;
stack_pull_s: out std_logic;
zero_s: out std_logic;
zero_idx_s: out std_logic);
end component;
component datapath is
port(clk: in std_logic;
rst: in std_logic;
stop: in std_logic;
de: in std_logic;
d: inout std_logic_vector(7 downto 0);
ad: out std_logic_vector(15 downto 0);
src: in datapath_src;
dst: in datapath_dst;
adr: in datapath_adr;
c_sel: in datapath_flg_ctrl;
z_sel: in datapath_flg_ctrl;
n_sel: in datapath_flg_ctrl;
v_sel: in datapath_flg_ctrl;
i_sel: in datapath_flg_ctrl;
d_sel: in datapath_flg_ctrl;
p_out: out std_logic_vector(7 downto 0);
dl_out: out std_logic_vector(7 downto 0);
c_out: out std_logic;
b_in: in std_logic;
do_sel: in datapath_do_ctrl;
int_vec: in std_logic_vector(15 downto 0);
adh_d: in std_logic;
adh_rst: in std_logic;
pch_d: in std_logic;
pc_incr: in std_logic;
r: in std_logic;
fn: in alu_fn;
a_dbg: out std_logic_vector(7 downto 0);
x_dbg: out std_logic_vector(7 downto 0);
y_dbg: out std_logic_vector(7 downto 0);
s_dbg: out std_logic_vector(7 downto 0);
pcl_dbg: out std_logic_vector(7 downto 0);
pch_dbg: out std_logic_vector(7 downto 0);
adl_dbg: out std_logic_vector(7 downto 0);
adh_dbg: out std_logic_vector(7 downto 0));
end component;
signal abs_0: std_logic;
signal abs_xy: std_logic;
signal acc: std_logic;
signal branch: std_logic;
signal brk: std_logic;
signal c: std_logic;
signal imm: std_logic;
signal ind_x: std_logic;
signal ind_y: std_logic;
signal jmp: std_logic;
signal jmp_abs: std_logic;
signal jsr: std_logic;
signal pull: std_logic;
signal push: std_logic;
signal push_pull: std_logic;
signal rmw: std_logic;
signal rti: std_logic;
signal rts: std_logic;
signal simple: std_logic;
signal store: std_logic;
signal sub: std_logic;
signal taken: std_logic;
signal zp: std_logic;
signal zp_xy: std_logic;
signal branch1: std_logic;
signal branch_pd: std_logic;
signal branch_pu: std_logic;
signal data: std_logic;
signal data2: std_logic;
signal data_idx: std_logic;
signal exec_fetch_op: std_logic;
signal fetch_adh: std_logic;
signal fetch_adh2: std_logic;
signal fetch_op: std_logic;
signal fetch_op2: std_logic;
signal fetch_op_pc: std_logic;
signal fetch_pch: std_logic;
signal inc_pc: std_logic;
signal int_vec1: std_logic;
signal int_vec2: std_logic;
signal jmp_abs1: std_logic;
signal jmp_abs2: std_logic;
signal modify: std_logic;
signal rm_write: std_logic;
signal stack: std_logic;
signal stack_exec_op: std_logic;
signal stack_p: std_logic;
signal stack_pch: std_logic;
signal stack_pcl: std_logic;
signal stack_pull: std_logic;
signal zero: std_logic;
signal zero_idx: std_logic;
signal aaa: std_logic_vector(2 downto 0);
signal bbb: std_logic_vector(2 downto 0);
signal cc: std_logic_vector(1 downto 0);
signal bit_instr: std_logic;
signal b: std_logic;
signal zp_x: std_logic;
signal zp_y: std_logic;
signal abs_x: std_logic;
signal abs_y: std_logic;
signal fn_sel: std_logic_vector(7 downto 0);
signal p_o: std_logic_vector(7 downto 0);
signal dl_o: std_logic_vector(7 downto 0);
signal nz_sel_alu: std_logic;
signal nz_sel_mem: std_logic;
signal src: datapath_src;
signal dst: datapath_dst;
signal adr: datapath_adr;
signal c_sel: datapath_flg_ctrl;
signal z_sel: datapath_flg_ctrl;
signal n_sel: datapath_flg_ctrl;
signal v_sel: datapath_flg_ctrl;
signal i_sel: datapath_flg_ctrl;
signal d_sel: datapath_flg_ctrl;
signal do_sel: datapath_do_ctrl;
signal int_vec: std_logic_vector(15 downto 0);
signal adh_d: std_logic;
signal adh_rst: std_logic;
signal pch_d: std_logic;
signal pc_incr: std_logic;
signal fn: alu_fn;
signal int_vec_sel: std_logic_vector(3 downto 0);
signal rw: std_logic;
signal read: std_logic;
signal fsm_en: std_logic;
signal branch_flg: std_logic;
signal bpc_d: std_logic;
signal bpc_u: std_logic;
signal nmi_old: std_logic := '1';
signal nmi_p: std_logic := '0';
signal nmi_l: std_logic := '0';
signal irq_p: std_logic := '0';
signal res_p: std_logic := '1';
signal intr: std_logic;
begin
a6500_datapath: datapath
port map(clk, rst, stop, de, d, ad, src, dst, adr,
c_sel, z_sel, n_sel, v_sel, i_sel, d_sel,
p_o, dl_o, c, b, do_sel, int_vec, adh_d, adh_rst,
pch_d, pc_incr, read, fn, a_dbg, x_dbg, y_dbg,
s_dbg, pcl_dbg, pch_dbg, adl_dbg, adh_dbg);
a6500_fsm: fsm
port map(clk, rst, fsm_en, abs_0, abs_xy, acc,
bpc_d, bpc_u, branch, brk, c, imm, ind_x,
ind_y, jmp, jmp_abs, jsr, pull, push, push_pull,
rmw, rti, rts, simple, store, sub, taken, zp,
zp_xy, branch1, branch_pd, branch_pu, data,
data2, data_idx, exec_fetch_op, fetch_adh,
fetch_adh2, fetch_op, fetch_op2, fetch_op_pc,
fetch_pch, inc_pc, int_vec1, int_vec2, jmp_abs1,
jmp_abs2, modify, rm_write, stack, stack_exec_op,
stack_p, stack_pch, stack_pcl, stack_pull,
zero, zero_idx);
ir_reg8: reg8 port map(clk, '0', ir_en, ir_in, ir);
ir_in <= "00000000" when ir_rst = '1' else d;
ir_en <= ir_load or ir_rst;
-- Instruction fields
aaa <= ir(7 downto 5);
bbb <= ir(4 downto 2);
cc <= ir(1 downto 0);
ir_load <= (exec_fetch_op or fetch_op or fetch_op_pc or stack_exec_op) and not stop;
--intr <= ir_load and ((nmi_old and not nmi) or (not irq and not p_o(I)));
--intr <= ir_load and (irq_p or nmi_p);
intr <= ir_load and (nmi_l or (not irq and not p_o(I)));
ir_rst <= intr; -- Reset to load BRK opcode.
-- FSM Inputs (Addressing modes)
ind_x <= '1' when (cc = "01") and (bbb = "000") else '0';
zp <= '1' when
(bbb = "001") -- 16/C when cc = 00, undocumented in cc = 11
else '0';
imm <= '1' when
(cc = "01" and bbb = "010") or
(ir = X"A2" or ir = X"A0" or ir = X"C0" or ir = X"E0") -- LDX/LDY/CPY/CPX
else '0';
abs_0 <= '1' when
(bbb = "011" and jmp = '0' and jmp_abs = '0') -- undocumented in cc = 11
else '0';
ind_y <= '1' when
(cc = "01" and bbb = "100")
else '0';
zp_y <= '1' when
(ir = X"96" or ir = X"B6") -- STX/LDX
else '0';
zp_x <= '1' when
(bbb = "101" and zp_y = '0') -- 16/C when cc = 00, undocumented in cc = 11
else '0';
abs_y <= '1' when
(cc = "01" and bbb = "110") or
(ir = X"BE") -- LDX -- STX abs,Y?
else '0';
abs_x <= '1' when
(bbb = "111" and ir /= X"BE") -- not LDX
-- 16/C when cc = 00, C when STX, undocumented in cc = 11
else '0';
acc <= '1' when
(ir = X"0A" or ir = X"2A" or ir = X"4A" or ir = X"6A") -- ASL/ROL/LSR/ROR A
else '0';
zp_xy <= zp_x or zp_y;
abs_xy <= abs_y or abs_x;
-- FSM Inputs (Instruction Classification)
rmw <= '1' when
(cc = "10" and aaa /= "100" and aaa /= "101") -- not STX/LDX
else '0';
store <= '1' when
(aaa = "100") -- Undocumented?
else '0';
simple <= '1' when
((cc = "10" or cc = "00") and
(bbb = "110" or -- SEx/CLx/TYA/TXS/TSX, includes C
(bbb = "010" and aaa(2) = '1'))) -- DEY/TAY/INY/INX/TXA/TAX/DEX/NOP
else '0';
push_pull <= '1' when
(cc = "00") and (aaa(2) = '0') and (bbb = "010")
else '0';
sub <= '1' when
(cc = "00") and (aaa(2) = '0') and (bbb = "000")
else '0';
brk <= '1' when
(ir = "00000000")
else '0';
push <= '1' when
(bbb(1) = '1' and aaa(0) = '0')
else '0';
pull <= '1' when
(bbb(1) = '1' and aaa(0) = '1')
else '0';
jsr <= '1' when
(bbb(1) = '0' and aaa(0) = '1' and aaa(1) = '0')
else '0';
rti <= '1' when
(bbb(1) = '0' and aaa(0) = '0' and aaa(1) = '1')
else '0';
rts <= '1' when
(bbb(1) = '0' and aaa(0) = '1' and aaa(1) = '1')
else '0';
jmp <= '1' when
(ir = X"4C")
else '0';
jmp_abs <= '1' when
(ir = X"6C")
else '0';
branch <= '1' when
(cc = "00" and bbb = "100")
else '0';
bit_instr <= '1' when
(ir = X"24" or ir = X"2C")
else '0';
b <= not (irq_p or nmi_p);
int_vec_sel <= int_vec1 & int_vec2 & nmi_p & res_p;
with (int_vec_sel) select int_vec <=
X"FFFA" when "1010",
X"FFFB" when "0110",
X"FFFC" when "1001",
X"FFFD" when "0101",
X"FFFE" when "1000",
X"FFFF" when "0100",
"----------------" when others;
-- Address Bus control
adr(PCHL) <= '1' when
(exec_fetch_op = '1') or
(fetch_op = '1') or
(fetch_op2 = '1') or
(fetch_adh = '1') or
(stack_exec_op = '1') or
(fetch_pch = '1') or
(branch1 = '1') or
(branch_pd = '1') or
(branch_pu = '1') or
(fetch_op_pc = '1') or
(inc_pc = '1')
else '0';
adr(ADHDL) <= '1' when
(zero = '1')
else '0';
adr(ADHL) <= '1' when
(zero_idx = '1') or
(fetch_adh2 = '1') or
(data2 = '1') or
(modify = '1') or
(rm_write = '1') or
(jmp_abs2 = '1')
else '0';
adr(DLADL) <= '1' when
(data = '1') or
(data_idx = '1') or
(jmp_abs1 = '1')
else '0';
adr(INTVEC) <= '1' when
(int_vec1 = '1') or
(int_vec2 = '1')
else '0';
adr(STAD) <= '1' when
(stack = '1') or
(stack_pull = '1') or
(stack_pcl = '1') or
(stack_pch = '1') or
(stack_p = '1')
else '0';
adh_rst <= '1' when
(fetch_op2 = '1')
else '0';
fsm_en <= not stop;
r <= read;
read <= (stack and not push) or
((not (stack or stack_pcl or stack_pch or stack_p)) and rw) or
((stack_pcl or stack_pch or stack_p) and not (jsr or brk));
rw <= not (((data or data2 or (zero and zp) or (zero_idx and zp_xy)) and store) or modify or rm_write);
pc_incr <= not intr and
(fetch_adh or exec_fetch_op or fetch_op or stack_exec_op or -- Next: fetch_op2
fetch_op_pc or fetch_pch or inc_pc or
(fetch_op2 and not (simple or acc or push_pull or irq_p or nmi_p)));
-- ALU Source
src(A) <= '1' when
(exec_fetch_op = '1' and (
(cc = "01") or
(acc = '1') or
(ir = X"24" or ir = X"2C") or -- BIT
(ir = X"A8" or ir = X"AA"))) or -- TAY/TAX
(zero = '1' and ir = X"85") or -- STA zp
(zero_idx = '1' and ir = X"95") or -- STA zp, X
(data = '1' and cc = "01" and aaa = "100" and abs_xy = '0') or -- STA
(data2 = '1' and cc = "01" and aaa = "100") or -- STA
(stack = '1' and push = '1' and aaa(1) = '1') -- PHA
else '0';
src(X) <= '1' when
(exec_fetch_op = '1' and (
(cc = "10" and aaa = "100") or -- TXA/TXS, includes 16/C/STX
(cc = "00" and aaa = "111" and bbb(2) = '0') or -- CPX/INX
(ir = X"CA"))) or -- DEX
(zero = '1' and (ind_x = '1' or zp_x = '1')) or
(zero = '1' and ir = X"86") or -- -- STX zp
(zero_idx = '1' and ir = X"96") or -- STX zp, Y
(data = '1' and cc = "10" and aaa = "100" and abs_xy = '0') or -- STX
(data2 = '1' and cc = "10" and aaa = "100") or -- STX
(fetch_adh = '1' and abs_x = '1')
else '0';
src(Y) <= '1' when
(exec_fetch_op = '1' and (
(cc = "00" and (aaa = "100" or aaa = "110") and bbb(2) = '0') or -- STY/CPY/INY/DEY, STY imm is C
(ir = X"98"))) or -- TYA
(zero = '1' and zp_y = '1') or
(zero = '1' and ir = X"84") or -- -- STY zp
(zero_idx = '1' and ir = X"94") or -- STY zp, X
(data = '1' and cc = "00" and aaa = "100" and abs_xy = '0') or -- STY
(data2 = '1' and cc = "00" and aaa = "100") or -- STY
(fetch_adh = '1' and abs_y = '1') or
(fetch_adh2 = '1' and ind_y = '1')
else '0';
src(S) <= '1' when
(exec_fetch_op = '1' and ir = X"BA") or -- TSX
(stack_exec_op = '1' and push = '1') or -- PHx
(stack = '1' and push = '0' and jsr = '0') or
(stack_pcl = '1') or
(stack_pch = '1' and (jsr = '1' or brk = '1')) or
(stack_p = '1')
else '0';
src(PCL) <= '1' when
(branch1 = '1')
else '0';
src(PCH) <= '1' when
(branch_pd = '1') or
(branch_pu = '1')
else '0';
src(ADL) <= '1' when
(zero_idx = '1' and ind_x = '1') or
(jmp_abs1 = '1') or
(fetch_pch = '1' and jsr = '1')
else '0';
src(DL) <= '1' when
(exec_fetch_op = '1' and
(cc = "10" and
(aaa /= "100") and -- STX
(bbb /= "010" and bbb /= "100" and bbb /= "110"))) or -- TXS/TSX, unavailable addr. modes (C)
(stack_exec_op = '1' and pull = '1') or
(stack = '1' and jsr = '1') or
(stack_pch = '1' and (rts = '1' or rti = '1')) or
(fetch_pch = '1' and (jmp = '1' or jmp_abs = '1')) or
(jmp_abs2 = '1') or
(rm_write = '1') or
(zero = '1' and ind_y = '1') or
(data_idx = '1') or
(data = '1' and (store = '0' or (store = '1' and abs_xy = '1'))) or
(modify = '1')
else '0';
src(P) <= '1' when
(stack = '1' and push = '1' and aaa(1) = '0') -- PHP
else '0';
-- ALU Destination
dst(A) <= '1' when
(exec_fetch_op = '1' and (
(cc = "01" and aaa /= "110") or -- not CMP -- STA?
(acc = '1') or
(ir = X"98" or ir = X"8A"))) or -- TYA/TXA
(stack_exec_op = '1' and pull = '1' and aaa(1) = '1') -- PLA
else '0';
dst(X) <= '1' when
(exec_fetch_op = '1' and (
(cc = "10" and aaa = "101") or -- LDX/TAX/TSX, C when bbb = 100
(ir = X"E8" or ir = X"CA"))) -- INX/DEX
else '0';
dst(Y) <= '1' when
(exec_fetch_op = '1' and (
(cc = "00" and aaa = "101" and bbb /= "100" and bbb /= "110") or -- LDY/TAY
(ir = X"88" or ir = X"C8"))) -- DEY/INY
else '0';
dst(S) <= '1' when
(exec_fetch_op = '1' and ir = X"9A") or -- TXS
(stack = '1' and push = '0' and jsr = '0') or
(stack_exec_op = '1' and push = '1') or -- PHx
(stack_pcl = '1') or
(stack_pch = '1' and (jsr = '1' or brk = '1')) or
(stack_p = '1')
else '0';
dst(PCL) <= '1' when
(branch1 = '1') or
(jmp_abs2 = '1') or
(fetch_pch = '1' and (jmp = '1' or jsr = '1')) or
(stack_pch = '1' and (rts = '1' or rti = '1')) or
(int_vec2 = '1')
else '0';
dst(PCH) <= '1' when
(branch_pd = '1') or
(branch_pu = '1')
else '0';
pch_d <= '1' when
(int_vec2 = '1') or
(jmp_abs2 = '1') or
(fetch_pch = '1' and jmp_abs = '0') or
(stack_pch = '1' and (rts = '1' or rti = '1'))
else '0';
dst(ADL) <= '1' when
(zero = '1' and not (store = '1' and zp = '1')) or
(zero_idx = '1' and ind_x = '1') or
(stack = '1' and jsr = '1') or
(fetch_pch = '1' and jmp_abs = '1') or
(fetch_adh = '1') or
(fetch_adh2 = '1') or
(jmp_abs1 = '1')
else '0';
dst(ADH) <= '1' when
(data = '1' and (store = '0' or (store = '1' and abs_xy = '1'))) or
(data_idx = '1')
else '0';
dst(DL) <= '1' when
(modify = '1')
else '0';
do_sel(DO_PCH) <= '1' when
(stack_pch = '1') and (jsr = '1' or brk = '1')
else '0';
do_sel(DO_PCL) <= '1' when
(stack_pcl = '1') and (jsr = '1' or brk = '1')
else '0';
do_sel(DO_P) <= '1' when
(stack_p = '1' and brk = '1')
else '0';
do_sel(DO_ALU) <= '1' when
(rw = '0') or (stack = '1' and push = '1')
else '0';
adh_d <= '1' when
(fetch_pch = '1' and jmp_abs = '1')
else '0';
-- ALU Functions
with fn_sel select fn <=
('0' & aaa) when "00000001",
('1' & aaa) when "00000010",
"0110" when "00000100", -- CMP
"1110" when "00001000", -- DEC
"1111" when "00010000", -- INC
"1101" when "00100000", -- ADD
"0101" when "01000000", -- LDx (NOP)
"0100" when "10000000", -- STx (NOP)
"----" when others;
fn_sel(0) <= '1' when
(exec_fetch_op = '1' and (
(cc = "01") or
((cc = "00" or cc = "10") and (aaa = "101") and
not (bbb = "010" or bbb = "100" or bbb = "110")) or -- LDX/LDY, includes 16/C
(bit_instr = '1'))) -- BIT
else '0';
fn_sel(1) <= '1' when
(modify = '1') or
(exec_fetch_op = '1' and acc = '1')
else '0';
fn_sel(2) <= '1' when
(exec_fetch_op = '1' and
(cc = "00") and
(aaa = "110" or aaa = "111") and
(bbb = "000" or bbb = "001" or bbb = "011")) -- CPX/CPY
else '0';
fn_sel(3) <= '1' when
(exec_fetch_op = '1' and (ir = X"CA" or ir = X"88")) or -- DEX/DEY
(stack_exec_op = '1' and push = '1') or
((stack_pcl = '1' or stack_pch = '1' or stack_p = '1') and
(jsr = '1' or brk = '1')) or
(branch_pd = '1')
else '0';
fn_sel(4) <= '1' when
(exec_fetch_op = '1' and (ir = X"E8" or ir = X"C8")) or -- INX/INY
(zero = '1' and ind_y = '1') or
(zero_idx = '1' and ind_x = '1') or
(data_idx = '1') or
((stack = '1' or stack_pcl = '1' or stack_p = '1') and
(rts = '1' or rti = '1' or pull = '1')) or
(jmp_abs1 = '1') or
(branch_pu = '1')
else '0';
fn_sel(5) <= '1' when
(zero = '1' and (ind_x = '1' or zp_xy = '1')) or
(fetch_adh = '1' and abs_xy = '1') or
(fetch_adh2 = '1' and ind_y = '1') or
(branch1 = '1')
else '0';
fn_sel(6) <= '1' when
(fetch_adh = '1' and abs_0 = '1') or
(fetch_adh2 = '1' and ind_x = '1') or
(zero = '1' and zp = '1' and store = '0') or
(data = '1' and (store = '0' or (store = '1' and abs_xy = '1'))) or
(int_vec2 = '1') or
(stack_exec_op = '1' and pull = '1')
else '0';
-- It seems that there are very few cases where we do not care about what the ALU does, if at all.
-- So, the following assigns NOP by default to the ALU. We do not use "when others" because
-- that also takes into account the cases where multiple members of the fn_sel vector are 1.
-- These take care of most transfer instructions.
fn_sel(7) <= not (fn_sel(0) or fn_sel(1) or fn_sel(2) or fn_sel(3) or fn_sel(4) or fn_sel(5) or fn_sel(6));
c_sel(FLG_ALU) <= '1' when
(exec_fetch_op = '1' and (
(cc = "01" and
(aaa = "011" or aaa = "110" or aaa = "111")) or -- ADC/CMP/SBC
(cc = "00" and
(aaa = "110" or aaa = "111") and bbb /= "010" and bbb /= "110") or -- CPX/CPY
(acc = '1'))) or
(modify = '1' and (
(cc = "10") and aaa(2) /= '1')) -- ASL/LSR/ROL/ROR
else '0';
c_sel(FLG_MEM) <= '1' when
(stack_exec_op = '1' and pull = '1' and aaa(1) = '0') or -- PLP
(stack_pcl = '1' and rti = '1')
else '0';
c_sel(FLG_ZERO) <= '1' when
(exec_fetch_op = '1' and ir = X"18") -- CLC
else '0';
c_sel(FLG_ONE) <= '1' when
(exec_fetch_op = '1' and ir = X"38") -- SEC
else '0';
nz_sel_alu <= '1' when
(exec_fetch_op = '1' and (
(cc = "01" and aaa /= "100") or -- not STA
(ir = X"8A" or ir = X"BA" or ir = X"88" or ir = X"98") or -- TXA/TSX/DEY/TYA
(ir = X"AA" or ir = X"A8") or -- TAX/TAY
(cc = "00" and
(aaa = "101" or aaa = "110" or aaa = "111") and -- LDY/CPY/CPX
not (bbb = "100" or bbb = "110")) or -- unavailable modes, includes 16
(cc = "10" and
(aaa = "101") and -- LDX
not (bbb = "010" or bbb = "110")) or
(ir = X"CA") or -- DEX
(acc = '1'))) or
(stack_exec_op = '1' and pull = '1' and aaa(1) = '1') or -- PLA
(modify = '1')
else '0';
nz_sel_mem <= '1' when
(stack_exec_op = '1' and pull = '1' and aaa(1) = '0') or -- PLP
(stack_pcl = '1' and rti = '1')
else '0';
n_sel(FLG_ALU) <= '1' when
(nz_sel_alu = '1')
else '0';
n_sel(FLG_MEM) <= '1' when
(nz_sel_mem = '1' or bit_instr = '1')
else '0';
n_sel(FLG_ZERO) <= '0';
n_sel(FLG_ONE) <= '0';
z_sel(FLG_ALU) <= '1' when
(nz_sel_alu = '1' or bit_instr = '1')
else '0';
z_sel(FLG_MEM) <= '1' when
(nz_sel_mem = '1')
else '0';
z_sel(FLG_ZERO) <= '0';
z_sel(FLG_ONE) <= '0';
v_sel(FLG_ALU) <= '1' when
(exec_fetch_op = '1' and (
(cc = "01" and (aaa = "011" or aaa = "111")))) -- ADC/CMP/SBC
else '0';
v_sel(FLG_MEM) <= '1' when
(stack_exec_op = '1' and pull = '1' and aaa(1) = '0') or -- PLP
(stack_pcl = '1' and rti = '1') or
(ir = X"24" or ir = X"2C") -- BIT
else '0';
v_sel(FLG_ZERO) <= '1' when
(exec_fetch_op = '1' and ir = X"B8") -- CLV
else '0';
v_sel(FLG_ONE) <= '0';
i_sel(FLG_ALU) <= '0';
i_sel(FLG_MEM) <= '1' when
(stack_exec_op = '1' and pull = '1' and aaa(1) = '0') or -- PLP
(stack_pcl = '1' and rti = '1')
else '0';
i_sel(FLG_ZERO) <= '1' when
(exec_fetch_op = '1' and ir = X"58") -- CLI
else '0';
i_sel(FLG_ONE) <= '1' when
(exec_fetch_op = '1' and ir = X"78") or -- SEI
(int_vec2 = '1')
else '0';
d_sel(FLG_ALU) <= '0';
d_sel(FLG_MEM) <= '1' when
(stack_exec_op = '1' and pull = '1' and aaa(1) = '0') or -- PLP
(stack_pcl = '1' and rti = '1')
else '0';
d_sel(FLG_ZERO) <= '1' when
(exec_fetch_op = '1' and ir = X"D8") -- CLD
else '0';
d_sel(FLG_ONE) <= '1' when
(exec_fetch_op = '1' and ir = X"F8") -- SED
else '0';
with ir(7 downto 6) select branch_flg <=
p_o(7) when "00",
p_o(6) when "01",
p_o(0) when "10",
p_o(1) when "11",
'-' when others;
taken <= '1' when
(branch_flg = ir(5))
else '0';
bpc_u <= '1' when
(dl_o(7) = '0' and c = '1')
else '0';
bpc_d <= '1' when
(dl_o(7) = '1' and c = '0')
else '0';
-- Interrupt logic
process(clk, rst, nmi, fetch_op, exec_fetch_op, fetch_op_pc,
stack_exec_op, fetch_op2, nmi_p, irq, p_o)
begin
if (clk = '1' and clk'event) then
if (rst = '1') then
nmi_p <= '0';
irq_p <= '0';
res_p <= '1';
nmi_old <= '1';
nmi_l <= '0';
else
nmi_old <= nmi;
if (nmi_l = '0' and nmi_old = '1' and nmi = '0') then
nmi_l <= '1';
elsif (fetch_op = '1' or
exec_fetch_op = '1' or
fetch_op_pc = '1' or
stack_exec_op = '1')
and (stop = '0') then
nmi_l <= '0';
end if;
if (fetch_op = '1' or
exec_fetch_op = '1' or
fetch_op_pc = '1' or
stack_exec_op = '1')
and (stop = '0') then
-- Next state: fetch_op2
if (nmi_l = '1') then
nmi_p <= '1';
irq_p <= '0';
elsif (irq = '0' and p_o(I) = '0') then
nmi_p <= '0';
irq_p <= '1';
else
nmi_p <= '0';
irq_p <= '0';
end if;
res_p <= '0';
end if;
end if;
end if;
end process;
p_dbg <= p_o;
end arch;
| mit | 180fab8d9841c835633ceabda1892c5f | 0.461312 | 2.950238 | false | false | false | false |
dummylink/plnk_fpga-stack | Examples/xilinx_microblaze/avnet_lx9/pcores/plb_powerlink_v1_00_a/hdl/vhdl/pdi_controlStatusReg.vhd | 5 | 20,582 | ------------------------------------------------------------------------------------------------------------------------
-- Process Data Interface (PDI) status control register
--
-- Copyright (C) 2011 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2011-09-14 V0.01 zelenkaj extract from pdi.vhd
-- 2011-11-21 V0.02 zelenkaj added time synchronization feature
-- added 12 bytes to DPR as reserved
-- 2011-11-29 V0.03 zelenkaj led and event is optional
-- 2011-12-20 V0.04 zelenkaj changed 2xbuf switch source to ap irq
-- 2012-01-26 V0.05 zelenkaj en-/disable double buffer with genTimeSync_g
------------------------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity pdiControlStatusReg is
generic (
bIsPcp : boolean := true;
iAddrWidth_g : integer := 8;
iBaseDpr_g : integer := 16#4#; --base address (in external mapping) of content in dpr
iSpanDpr_g : integer := 12; --span of content in dpr
iBaseMap2_g : integer := 0; --base address in dpr
iDprAddrWidth_g : integer := 11;
iRpdos_g : integer := 3;
genLedGadget_g : boolean := false;
genTimeSync_g : boolean := false;
genEvent_g : boolean := false;
--register content
---constant values
magicNumber : std_Logic_vector(31 downto 0) := (others => '0');
pdiRev : std_logic_vector(15 downto 0) := (others => '0');
tPdoBuffer : std_logic_vector(31 downto 0) := (others => '0');
rPdo0Buffer : std_logic_vector(31 downto 0) := (others => '0');
rPdo1Buffer : std_logic_vector(31 downto 0) := (others => '0');
rPdo2Buffer : std_logic_vector(31 downto 0) := (others => '0');
asyncBuffer1Tx : std_logic_vector(31 downto 0) := (others => '0');
asyncBuffer1Rx : std_logic_vector(31 downto 0) := (others => '0');
asyncBuffer2Tx : std_logic_vector(31 downto 0) := (others => '0');
asyncBuffer2Rx : std_logic_vector(31 downto 0) := (others => '0')
);
port (
--memory mapped interface
clk : in std_logic;
rst : in std_logic;
sel : in std_logic;
wr : in std_logic;
rd : in std_logic;
addr : in std_logic_vector(iAddrWidth_g-1 downto 0);
be : in std_logic_vector(3 downto 0);
din : in std_logic_vector(31 downto 0);
dout : out std_logic_vector(31 downto 0);
--register content
---virtual buffer control signals
rpdo_change_tog : in std_logic_vector(2 downto 0); --change buffer from hw acc
tpdo_change_tog : in std_logic; --change buffer from hw acc
pdoVirtualBufferSel : in std_logic_vector(31 downto 0); --for debugging purpose from SW side
--TXPDO_ACK | RXPDO2_ACK | RXPDO1_ACK | RXPDO0_ACK
tPdoTrigger : out std_logic; --TPDO virtual buffer change trigger
rPdoTrigger : out std_logic_vector(2 downto 0); --RPDOs virtual buffer change triggers
---is used for Irq Generation and should be mapped to apIrqGen
apIrqControlOut : out std_logic_vector(15 downto 0);
apIrqControlIn : in std_logic_vector(15 downto 0);
---event registers
eventAckIn : in std_logic_vector(15 downto 0);
eventAckOut : out std_logic_vector(15 downto 0);
---async irq (by event)
asyncIrqCtrlIn : In std_logic_vector(15 downto 0); --Ap only
asyncIrqCtrlOut : out std_logic_vector(15 downto 0); --Ap only
---led stuff
ledCnfgIn : in std_logic_vector(15 downto 0);
ledCnfgOut : out std_logic_vector(15 downto 0);
ledCtrlIn : in std_logic_vector(15 downto 0);
ledCtrlOut : out std_logic_vector(15 downto 0);
---time synchronization
doubleBufSel_out : out std_logic; --Ap only
doubleBufSel_in : in std_logic := '0'; --Pcp only
timeSyncIrq : in std_logic; --SYNC IRQ to Ap (Ap only)
--dpr interface (from PCP/AP to DPR)
dprAddrOff : out std_logic_vector(iDprAddrWidth_g downto 0);
dprDin : out std_logic_vector(31 downto 0);
dprDout : in std_logic_vector(31 downto 0);
dprBe : out std_logic_vector(3 downto 0);
dprWr : out std_logic
);
end entity pdiControlStatusReg;
architecture rtl of pdiControlStatusReg is
constant c_num_dbuf_dpr : integer := 4; --number of dbuf in DPR (per buffer 4 byte)
signal selDpr : std_logic; --if '1' get/write content from/to dpr
signal nonDprDout : std_logic_vector(31 downto 0);
signal addrRes : std_logic_vector(dprAddrOff'range);
--signal apIrqValue_s : std_logic_vector(31 downto 0); --pcp only
signal virtualBufferSelectTpdo : std_logic_vector(15 downto 0);
signal virtualBufferSelectRpdo0 : std_logic_vector(15 downto 0);
signal virtualBufferSelectRpdo1 : std_logic_vector(15 downto 0);
signal virtualBufferSelectRpdo2 : std_logic_vector(15 downto 0);
--edge detection
signal rpdo_change_tog_l : std_logic_vector(2 downto 0); --change buffer from hw acc
signal tpdo_change_tog_l : std_logic; --change buffer from hw acc
--time synchronization
signal timeSyncIrq_rising : std_logic;
---select signals
signal sel_time_after_sync : std_logic;
signal sel_double_buffer : std_logic;
----double buffered content
signal sel_relative_time_l : std_logic;
signal sel_relative_time_h : std_logic;
signal sel_nettime_nsec : std_logic;
signal sel_nettime_sec : std_logic;
signal sel_time_sync_regs : std_logic;
---time after sync counter
constant c_time_after_sync_cnt_size : integer := 16; --revise code if changed
signal time_after_sync_cnt : std_logic_vector(c_time_after_sync_cnt_size-1 downto 0);
signal time_after_sync_cnt_latch : std_logic_vector(c_time_after_sync_cnt_size/2-1 downto 0);
signal time_after_sync_cnt_next : std_logic_vector(c_time_after_sync_cnt_size-1 downto 0);
signal time_after_sync_cnt_out : std_logic_vector(c_time_after_sync_cnt_size-1 downto 0) := (others => '0');
constant time_after_sync_res : std_logic_vector(32-c_time_after_sync_cnt_size-1 downto 0) := (others => '0');
---address offsets
constant c_addr_time_after_sync : integer := 16#50#;
constant c_addr_relative_time_l : integer := 16#40#;
constant c_addr_relative_time_h : integer := 16#44#;
constant c_addr_nettime_nsec : integer := 16#48#;
constant c_addr_nettime_sec : integer := 16#4C#;
begin
--map to 16bit register
--TXPDO_ACK | RXPDO2_ACK | RXPDO1_ACK | RXPDO0_ACK
virtualBufferSelectRpdo0 <= pdoVirtualBufferSel( 7 downto 0) & pdoVirtualBufferSel( 7 downto 0);
virtualBufferSelectRpdo1 <= pdoVirtualBufferSel(15 downto 8) & pdoVirtualBufferSel(15 downto 8);
virtualBufferSelectRpdo2 <= pdoVirtualBufferSel(23 downto 16) & pdoVirtualBufferSel(23 downto 16);
virtualBufferSelectTpdo <= pdoVirtualBufferSel(31 downto 24) & pdoVirtualBufferSel(31 downto 24);
--generate dpr select signal
selDpr <= sel when (conv_integer(addr) >= iBaseDpr_g AND
conv_integer(addr) < iBaseDpr_g + iSpanDpr_g - c_num_dbuf_dpr)
else '0';
--time sync select content if the double buffer has to be generated (genTimeSync_g)
sel_time_after_sync <= '1' when conv_integer(addr)*4 = c_addr_time_after_sync and genTimeSync_g else '0';
sel_relative_time_l <= '1' when conv_integer(addr)*4 = c_addr_relative_time_l and genTimeSync_g else '0';
sel_relative_time_h <= '1' when conv_integer(addr)*4 = c_addr_relative_time_h and genTimeSync_g else '0';
sel_nettime_nsec <= '1' when conv_integer(addr)*4 = c_addr_nettime_nsec and genTimeSync_g else '0';
sel_nettime_sec <= '1' when conv_integer(addr)*4 = c_addr_nettime_sec and genTimeSync_g else '0';
---or them up...
sel_time_sync_regs <= sel_relative_time_l or sel_relative_time_h or sel_nettime_nsec or sel_nettime_sec;
genTimeSync : if genTimeSync_g generate
begin
--we need a rising edge to do magic
apSyncIrqEdgeDet : entity work.edgedet
port map (
din => timeSyncIrq,
rising => timeSyncIrq_rising,
falling => open,
any => open,
clk => clk,
rst => rst
);
genDoubleBufPcp : if bIsPcp generate
begin
--take the other buffer (Ap has already inverted, see lines below!)
sel_double_buffer <= doubleBufSel_in;
--Pcp has no timer
time_after_sync_cnt_out <= (others => '0');
end generate;
genDoubleBufAp : if not bIsPcp generate
begin
--output the inverted to the PCP
doubleBufSel_out <= not sel_double_buffer;
--switch the double buffer with the sync irq, rising edge of course
process(clk, rst)
begin
if rst = '1' then
sel_double_buffer <= '0';
elsif rising_edge(clk) then
if timeSyncIrq_rising = '1' then --rising edge
sel_double_buffer <= not sel_double_buffer;
end if;
end if;
end process;
end generate;
genTimeAfterSyncCnt : if not bIsPcp generate
constant ZEROS : std_logic_vector(time_after_sync_cnt'range) := (others => '0');
constant ONES : std_logic_vector(time_after_sync_cnt'range) := (others => '1');
begin
--TIME_AFTER_SYNC counter
process(clk, rst)
begin
if rst = '1' then
time_after_sync_cnt <= (others => '0');
elsif clk = '1' and clk'event then
time_after_sync_cnt <= time_after_sync_cnt_next;
--there are some kind of interfaces that read only the half of a word...
-- so store the half that is not read
-- and forward it to the Ap at the next read
if sel = '1' and sel_time_after_sync = '1' and be = "0001" then
time_after_sync_cnt_latch <= time_after_sync_cnt(c_time_after_sync_cnt_size-1 downto c_time_after_sync_cnt_size/2);
end if;
end if;
end process;
time_after_sync_cnt_next <= ZEROS when timeSyncIrq_rising = '1' else --rising edge
time_after_sync_cnt when time_after_sync_cnt = ONES else --saturate
time_after_sync_cnt + 1; --count for your life!
time_after_sync_cnt_out <= time_after_sync_cnt when be(3 downto 2) = "11" or be(1 downto 0) = "11" else
time_after_sync_cnt_latch & time_after_sync_cnt(time_after_sync_cnt_latch'range);
end generate;
end generate;
--assign content depending on selDpr
dprDin <= din;
dprBe <= be;
dprWr <= wr when selDpr = '1' else
'0';
dout <= dprDout when selDpr = '1' else
nonDprDout;
dprAddrOff <= addrRes + 4 when sel_double_buffer = '1' and sel_time_sync_regs = '1' and genTimeSync_g else --select 2nd double buffer
addrRes; --select 1st double buffer or other content
--address conversion
---map external address mapping into dpr
addrRes <= conv_std_logic_vector(iBaseMap2_g - iBaseDpr_g, addrRes'length);
--non dpr read
with conv_integer(addr)*4 select
nonDprDout <= magicNumber when 16#00#,
(x"0000" & pdiRev) when 16#04#,
--STORED IN DPR when 16#08#,
--STORED IN DPR when 16#0C#,
--STORED IN DPR when 16#10#,
--STORED IN DPR when 16#14#,
--STORED IN DPR when 16#18#,
--STORED IN DPR when 16#1C#,
--STORED IN DPR when 16#20#,
--STORED IN DPR when 16#24#,
--STORED IN DPR when 16#28#,
--STORED IN DPR when 16#2C#,
--STORED IN DPR when 16#30#,
--STORED IN DPR when 16#34#, --RESERVED
--STORED IN DPR when 16#38#, --RESERVED
--STORED IN DPR when 16#3C#, --RESERVED
--STORED IN DPR x2 when c_addr_relative_time_l, --RELATIVE_TIME low
--STORED IN DPR x2 when c_addr_relative_time_h, --RELATIVE_TIME high
--STORED IN DPR x2 when c_addr_nettime_nsec, --NETTIME nsec
--STORED IN DPR x2 when c_addr_nettime_sec, --NETTIME sec
(time_after_sync_res &
time_after_sync_cnt_out) when c_addr_time_after_sync, --RES / TIME_AFTER_SYNC
(eventAckIn & asyncIrqCtrlIn) when 16#54#,
tPdoBuffer when 16#58#,
rPdo0Buffer when 16#5C#,
rPdo1Buffer when 16#60#,
rPdo2Buffer when 16#64#,
asyncBuffer1Tx when 16#68#,
asyncBuffer1Rx when 16#6C#,
asyncBuffer2Tx when 16#70#,
asyncBuffer2Rx when 16#74#,
--RESERVED when 16#78#,
--RESERVED when 16#7C#,
(virtualBufferSelectRpdo0 &
virtualBufferSelectTpdo) when 16#80#,
(virtualBufferSelectRpdo2 &
virtualBufferSelectRpdo1) when 16#84#,
(x"0000" & apIrqControlIn) when 16#88#,
--RESERVED when 16#8C#,
--RESERVED when 16#90#,
(ledCnfgIn & ledCtrlIn) when 16#94#,
(others => '0') when others;
--ignored values
asyncIrqCtrlOut(14 downto 1) <= (others => '0');
eventAckOut(15 downto 8) <= (others => '0');
--non dpr write
process(clk, rst)
begin
if rst = '1' then
tPdoTrigger <= '0';
rPdoTrigger <= (others => '0');
--apIrqControlOut <= (others => '0');
if bIsPcp = true then
apIrqControlOut(7) <= '0';
apIrqControlOut(6) <= '0';
end if;
if bIsPcp = false then
apIrqControlOut(15) <= '0';
end if;
apIrqControlOut(0) <= '0';
if genEvent_g then
if bIsPcp = false then
asyncIrqCtrlOut(0) <= '0';
asyncIrqCtrlOut(15) <= '0';
end if;
eventAckOut(7 downto 0) <= (others => '0');
end if;
if genLedGadget_g then
ledCtrlOut(7 downto 0) <= (others => '0');
ledCnfgOut(7 downto 0) <= (others => '0');
end if;
if bIsPcp then
rpdo_change_tog_l <= (others => '0');
tpdo_change_tog_l <= '0';
end if;
elsif clk = '1' and clk'event then
--default assignments
tPdoTrigger <= '0';
rPdoTrigger <= (others => '0');
apIrqControlOut(0) <= '0'; --PCP: set pulse // AP: ack pulse
if genEvent_g then
eventAckOut(7 downto 0) <= (others => '0'); --PCP: set pulse // AP: ack pulse
end if;
if bIsPcp then
--shift register for edge det
rpdo_change_tog_l <= rpdo_change_tog;
tpdo_change_tog_l <= tpdo_change_tog;
--edge detection
---tpdo
if tpdo_change_tog_l /= tpdo_change_tog then
tPdoTrigger <= '1';
end if;
---rpdo
for i in rpdo_change_tog'range loop
if rpdo_change_tog_l(i) /= rpdo_change_tog(i) then
rPdoTrigger(i) <= '1';
end if;
end loop;
end if;
if wr = '1' and sel = '1' and selDpr = '0' then
case conv_integer(addr)*4 is
when 16#00# =>
--RO
when 16#04# =>
--RO
when 16#08# =>
--STORED IN DPR
when 16#0C# =>
--STORED IN DPR
when 16#10# =>
--STORED IN DPR
when 16#14# =>
--STORED IN DPR
when 16#18# =>
--STORED IN DPR
when 16#1C# =>
--STORED IN DPR
when 16#20# =>
--STORED IN DPR
when 16#24# =>
--STORED IN DPR
when 16#28# =>
--STORED IN DPR
when 16#2C# =>
--STORED IN DPR
when 16#30# =>
--STORED IN DPR
when 16#34# =>
--STORED IN DPR RESERVED
when 16#38# =>
--STORED IN DPR RESERVED
when 16#3C# =>
--STORED IN DPR RESERVED
when 16#40# =>
--STORED IN DPR x2
when 16#44# =>
--STORED IN DPR x2
when 16#48# =>
--STORED IN DPR x2
when 16#4C# =>
--STORED IN DPR x2
when c_addr_time_after_sync =>
--RO
when 16#54# =>
--AP ONLY
if genEvent_g then
if be(0) = '1' and bIsPcp = false then
--asyncIrqCtrlOut(7 downto 0) <= din(7 downto 0);
asyncIrqCtrlOut(0) <= din(0); --rest is ignored
end if;
if be(1) = '1' and bIsPcp = false then
--asyncIrqCtrlOut(15 downto 8) <= din(15 downto 8);
asyncIrqCtrlOut(15) <= din(15); --rest is ignored
end if;
if be(2) = '1' then
eventAckOut(7 downto 0) <= din(23 downto 16);
end if;
--ignore higher byte of event ack
-- if be(3) = '1' then
-- eventAckOut(15 downto 8) <= din(31 downto 24);
-- end if;
end if;
when 16#58# =>
--RO
when 16#5C# =>
--RO
when 16#60# =>
--RO
when 16#64# =>
--RO
when 16#68# =>
--RO
when 16#6C# =>
--RO
when 16#70# =>
--RO
when 16#74# =>
--RO
when 16#78# =>
--RESERVED
when 16#7C# =>
--RESERVED
when 16#80# =>
if be(0) = '1' then
tPdoTrigger <= '1';
end if;
if be(1) = '1' then
tPdoTrigger <= '1';
end if;
if be(2) = '1' then
rPdoTrigger(0) <= '1';
end if;
if be(3) = '1' then
rPdoTrigger(0) <= '1';
end if;
when 16#84# =>
if be(0) = '1' then
rPdoTrigger(1) <= '1';
end if;
if be(1) = '1' then
rPdoTrigger(1) <= '1';
end if;
if be(2) = '1' then
rPdoTrigger(2) <= '1';
end if;
if be(3) = '1' then
rPdoTrigger(2) <= '1';
end if;
when 16#88# =>
if be(0) = '1' then
--apIrqControlOut(7 downto 0) <= din(7 downto 0);
if bIsPcp = true then
apIrqControlOut(7) <= din(7);
apIrqControlOut(6) <= din(6);
end if;
apIrqControlOut(0) <= din(0);
end if;
if be(1) = '1' then
--apIrqControlOut(15 downto 8) <= din(15 downto 8);
if bIsPcp = false then
apIrqControlOut(15) <= din(15);
end if;
end if;
when 16#8C# =>
--RESERVED
when 16#90# =>
--RESERVED
when 16#94# =>
if genLedGadget_g then
if be(0) = '1' then
ledCtrlOut(7 downto 0) <= din(7 downto 0);
end if;
if be(1) = '1' then
ledCtrlOut(15 downto 8) <= din(15 downto 8);
end if;
if be(2) = '1' then
ledCnfgOut(7 downto 0) <= din(23 downto 16);
end if;
if be(3) = '1' then
ledCnfgOut(15 downto 8) <= din(31 downto 24);
end if;
end if;
when others =>
end case;
end if;
end if;
end process;
end architecture rtl; | gpl-2.0 | 17eef8fab3bb9f74fb548a0ca0e57d99 | 0.575454 | 3.164514 | false | false | false | false |
dskntIndustry/Hardware | hdl_library/SignalGenerator/SignalGeneratorTB.vhd | 1 | 2,134 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library hdl_library_CommonFunctions;
use hdl_library_CommonFunctions.MathHelpers.all;
library hdl_library_ClockGenerator;
use hdl_library_ClockGenerator.all;
library hdl_library_SignalGenerator;
use hdl_library_SignalGenerator.all;
entity SignalGeneratorTB is
end entity; --SignalGeneratorTB
architecture tb of SignalGeneratorTB is
constant G_CLOCK_FREQUENCY : integer := 100E6;
constant G_CLOCK_DIVIDER : integer := 100;
constant G_SIGNAL_OUTPUT_RESOLUTION : integer := 16;
constant G_SIGNAL_SHAPE_TYPES : integer := 4;
constant SIGNAL_TYPE_SAW : integer := 0;
constant SIGNAL_TYPE_SINE : integer := 1;
constant SIGNAL_TYPE_TRIANGLE : integer := 2;
constant SIGNAL_TYPE_SQUARE : integer := 3;
constant SIGNAL_TYPE_RANDOM : integer := 4;
constant SIGNAL_TYPE_DIRAC : integer := 5;
constant G_CLOCK_COUNTER : integer := 100;
--declarations
signal clock : std_logic := '0';
signal clock_n : std_logic := '0';
signal enable : std_logic := '0';
signal ready : std_logic := '0';
signal clock_divider1 : integer := 1000;
signal clock_output : std_logic := '0';
signal clock_output_n : std_logic := '0';
-- signal signal_shape : std_logic_vector(log2(G_SIGNAL_SHAPE_TYPES) - 1 downto 0);
signal output_signal : std_logic_vector(G_SIGNAL_OUTPUT_RESOLUTION - 1 downto 0);
signal dirac_index : integer := 50;
begin
clock <= not clock after (1 sec / G_CLOCK_FREQUENCY) / 2;
clock_n <= not clock;
enable <= '1' after 100 ns;
dut : entity hdl_library_SignalGenerator.SignalGenerator
generic map
(
G_CLOCK_FREQUENCY => G_CLOCK_FREQUENCY,
G_SIGNAL_OUTPUT_RESOLUTION => G_SIGNAL_OUTPUT_RESOLUTION,
G_CLOCK_COUNTER => G_CLOCK_COUNTER,
G_SIGNAL_SHAPE => SIGNAL_TYPE_DIRAC
)
port map
(
clock => clock,
enable => enable,
output_signal => output_signal,
dirac_index => dirac_index
--ready => ready
);
end architecture; -- tb
| gpl-3.0 | de1f432770918314eb44f859c5814cc0 | 0.6612 | 3.061693 | false | false | false | false |
foresterre/mal | vhdl/env.vhdl | 17 | 2,358 | library STD;
use STD.textio.all;
library WORK;
use WORK.types.all;
package env is
procedure new_env(e: out env_ptr; an_outer: inout env_ptr);
procedure new_env(e: out env_ptr; an_outer: inout env_ptr; binds: inout mal_val_ptr; exprs: inout mal_val_ptr);
procedure env_set(e: inout env_ptr; key: inout mal_val_ptr; val: inout mal_val_ptr);
procedure env_get(e: inout env_ptr; key: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr);
end package env;
package body env is
procedure new_env(e: out env_ptr; an_outer: inout env_ptr) is
variable null_list: mal_val_ptr;
begin
null_list := null;
new_env(e, an_outer, null_list, null_list);
end procedure new_env;
procedure new_env(e: out env_ptr; an_outer: inout env_ptr; binds: inout mal_val_ptr; exprs: inout mal_val_ptr) is
variable the_data, more_exprs: mal_val_ptr;
variable i: integer;
begin
new_empty_hashmap(the_data);
if binds /= null then
for i in binds.seq_val'range loop
if binds.seq_val(i).string_val.all = "&" then
seq_drop_prefix(exprs, i, more_exprs);
hashmap_put(the_data, binds.seq_val(i + 1), more_exprs);
exit;
else
hashmap_put(the_data, binds.seq_val(i), exprs.seq_val(i));
end if;
end loop;
end if;
e := new env_record'(outer => an_outer, data => the_data);
end procedure new_env;
procedure env_set(e: inout env_ptr; key: inout mal_val_ptr; val: inout mal_val_ptr) is
begin
hashmap_put(e.data, key, val);
end procedure env_set;
procedure env_find(e: inout env_ptr; key: inout mal_val_ptr; found_env: out env_ptr) is
variable found: boolean;
begin
hashmap_contains(e.data, key, found);
if found then
found_env := e;
else
if e.outer = null then
found_env := null;
else
env_find(e.outer, key, found_env);
end if;
end if;
end procedure env_find;
procedure env_get(e: inout env_ptr; key: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable found_env: env_ptr;
begin
env_find(e, key, found_env);
if found_env = null then
new_string("'" & key.string_val.all & "' not found", err);
result := null;
return;
end if;
hashmap_get(found_env.data, key, result);
end procedure env_get;
end package body env;
| mpl-2.0 | c6163c672bfdf0317cebedc60e2cb084 | 0.637829 | 3.007653 | false | false | false | false |
dummylink/plnk_fpga-stack | Examples/altera_nios2/EBV_DBC3C40/design_nios2_directIO/altpll_0.vhd | 1 | 16,065 | --altpll_avalon avalon_use_separate_sysclk="NO" CBX_SINGLE_OUTPUT_FILE="ON" CBX_SUBMODULE_USED_PORTS="altpll:clk,locked,inclk" address c0 c1 c2 c3 c4 clk locked phasedone read readdata reset write writedata bandwidth_type="AUTO" clk0_divide_by=1 clk0_duty_cycle=50 clk0_multiply_by=1 clk0_phase_shift="0" clk1_divide_by=1 clk1_duty_cycle=50 clk1_multiply_by=2 clk1_phase_shift="0" clk2_divide_by=2 clk2_duty_cycle=50 clk2_multiply_by=1 clk2_phase_shift="0" clk3_divide_by=1 clk3_duty_cycle=50 clk3_multiply_by=1 clk3_phase_shift="0" clk4_divide_by=1 clk4_duty_cycle=50 clk4_multiply_by=1 clk4_phase_shift="-5000" compensate_clock="CLK0" device_family="CYCLONEIII" inclk0_input_frequency=20000 intended_device_family="Cyclone III" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_USED" port_clk2="PORT_USED" port_clk3="PORT_USED" port_clk4="PORT_USED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" width_clock=5
--VERSION_BEGIN 10.1SP1 cbx_altclkbuf 2011:01:19:21:13:40:SJ cbx_altiobuf_bidir 2011:01:19:21:13:40:SJ cbx_altiobuf_in 2011:01:19:21:13:40:SJ cbx_altiobuf_out 2011:01:19:21:13:40:SJ cbx_altpll 2011:01:19:21:13:40:SJ cbx_altpll_avalon 2011:01:19:21:13:40:SJ cbx_cycloneii 2011:01:19:21:13:40:SJ cbx_lpm_add_sub 2011:01:19:21:13:40:SJ cbx_lpm_compare 2011:01:19:21:13:40:SJ cbx_lpm_decode 2011:01:19:21:13:40:SJ cbx_lpm_mux 2011:01:19:21:13:40:SJ cbx_lpm_shiftreg 2011:01:19:21:13:40:SJ cbx_mgl 2011:01:19:21:15:40:SJ cbx_stratix 2011:01:19:21:13:40:SJ cbx_stratixii 2011:01:19:21:13:40:SJ cbx_stratixiii 2011:01:19:21:13:40:SJ cbx_stratixv 2011:01:19:21:13:40:SJ cbx_util_mgl 2011:01:19:21:13:40:SJ VERSION_END
-- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--altera_std_synchronizer CBX_SINGLE_OUTPUT_FILE="ON" clk din dout reset_n
--VERSION_BEGIN 10.1SP1 cbx_mgl 2011:01:19:21:15:40:SJ cbx_stratixii 2011:01:19:21:13:40:SJ cbx_util_mgl 2011:01:19:21:13:40:SJ VERSION_END
--dffpipe CBX_SINGLE_OUTPUT_FILE="ON" DELAY=3 WIDTH=1 clock clrn d q ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF
--VERSION_BEGIN 10.1SP1 cbx_mgl 2011:01:19:21:15:40:SJ cbx_stratixii 2011:01:19:21:13:40:SJ cbx_util_mgl 2011:01:19:21:13:40:SJ VERSION_END
--synthesis_resources = reg 3
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY altpll_0_dffpipe_l2c IS
PORT
(
clock : IN STD_LOGIC := '0';
clrn : IN STD_LOGIC := '1';
d : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END altpll_0_dffpipe_l2c;
ARCHITECTURE RTL OF altpll_0_dffpipe_l2c IS
ATTRIBUTE synthesis_clearbox : natural;
ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
ATTRIBUTE ALTERA_ATTRIBUTE : string;
ATTRIBUTE ALTERA_ATTRIBUTE OF RTL : ARCHITECTURE IS "AUTO_SHIFT_REGISTER_RECOGNITION=OFF";
SIGNAL dffe4a : STD_LOGIC_VECTOR(0 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL dffe5a : STD_LOGIC_VECTOR(0 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL dffe6a : STD_LOGIC_VECTOR(0 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL wire_dffpipe3_w_lg_sclr34w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL ena : STD_LOGIC;
SIGNAL prn : STD_LOGIC;
SIGNAL sclr : STD_LOGIC;
BEGIN
wire_dffpipe3_w_lg_sclr34w(0) <= NOT sclr;
ena <= '1';
prn <= '1';
q <= dffe6a;
sclr <= '0';
PROCESS (clock, prn, clrn)
BEGIN
IF (prn = '0') THEN dffe4a <= (OTHERS => '1');
ELSIF (clrn = '0') THEN dffe4a <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (ena = '1') THEN dffe4a(0) <= (d(0) AND wire_dffpipe3_w_lg_sclr34w(0));
END IF;
END IF;
END PROCESS;
PROCESS (clock, prn, clrn)
BEGIN
IF (prn = '0') THEN dffe5a <= (OTHERS => '1');
ELSIF (clrn = '0') THEN dffe5a <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (ena = '1') THEN dffe5a(0) <= (dffe4a(0) AND wire_dffpipe3_w_lg_sclr34w(0));
END IF;
END IF;
END PROCESS;
PROCESS (clock, prn, clrn)
BEGIN
IF (prn = '0') THEN dffe6a <= (OTHERS => '1');
ELSIF (clrn = '0') THEN dffe6a <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (ena = '1') THEN dffe6a(0) <= (dffe5a(0) AND wire_dffpipe3_w_lg_sclr34w(0));
END IF;
END IF;
END PROCESS;
END RTL; --altpll_0_dffpipe_l2c
--synthesis_resources = reg 3
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY altpll_0_stdsync_sv6 IS
PORT
(
clk : IN STD_LOGIC;
din : IN STD_LOGIC;
dout : OUT STD_LOGIC;
reset_n : IN STD_LOGIC
);
END altpll_0_stdsync_sv6;
ARCHITECTURE RTL OF altpll_0_stdsync_sv6 IS
ATTRIBUTE synthesis_clearbox : natural;
ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
SIGNAL wire_dffpipe3_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll_0_dffpipe_l2c
PORT
(
clock : IN STD_LOGIC := '0';
clrn : IN STD_LOGIC := '1';
d : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT;
BEGIN
dout <= wire_dffpipe3_q(0);
dffpipe3 : altpll_0_dffpipe_l2c
PORT MAP (
clock => clk,
clrn => reset_n,
d(0) => din,
q => wire_dffpipe3_q
);
END RTL; --altpll_0_stdsync_sv6
--altpll bandwidth_type="AUTO" CBX_SINGLE_OUTPUT_FILE="ON" clk0_divide_by=1 clk0_duty_cycle=50 clk0_multiply_by=1 clk0_phase_shift="0" clk1_divide_by=1 clk1_duty_cycle=50 clk1_multiply_by=2 clk1_phase_shift="0" clk2_divide_by=2 clk2_duty_cycle=50 clk2_multiply_by=1 clk2_phase_shift="0" clk3_divide_by=1 clk3_duty_cycle=50 clk3_multiply_by=1 clk3_phase_shift="0" clk4_divide_by=1 clk4_duty_cycle=50 clk4_multiply_by=1 clk4_phase_shift="-5000" compensate_clock="CLK0" device_family="CYCLONEIII" inclk0_input_frequency=20000 intended_device_family="Cyclone III" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_USED" port_clk2="PORT_USED" port_clk3="PORT_USED" port_clk4="PORT_USED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" width_clock=5 clk inclk locked
--VERSION_BEGIN 10.1SP1 cbx_altclkbuf 2011:01:19:21:13:40:SJ cbx_altiobuf_bidir 2011:01:19:21:13:40:SJ cbx_altiobuf_in 2011:01:19:21:13:40:SJ cbx_altiobuf_out 2011:01:19:21:13:40:SJ cbx_altpll 2011:01:19:21:13:40:SJ cbx_cycloneii 2011:01:19:21:13:40:SJ cbx_lpm_add_sub 2011:01:19:21:13:40:SJ cbx_lpm_compare 2011:01:19:21:13:40:SJ cbx_lpm_decode 2011:01:19:21:13:40:SJ cbx_lpm_mux 2011:01:19:21:13:40:SJ cbx_mgl 2011:01:19:21:15:40:SJ cbx_stratix 2011:01:19:21:13:40:SJ cbx_stratixii 2011:01:19:21:13:40:SJ cbx_stratixiii 2011:01:19:21:13:40:SJ cbx_stratixv 2011:01:19:21:13:40:SJ cbx_util_mgl 2011:01:19:21:13:40:SJ VERSION_END
LIBRARY cycloneiii;
USE cycloneiii.all;
--synthesis_resources = cycloneiii_pll 1
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY altpll_0_altpll_rnt2 IS
PORT
(
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0');
locked : OUT STD_LOGIC
);
END altpll_0_altpll_rnt2;
ARCHITECTURE RTL OF altpll_0_altpll_rnt2 IS
ATTRIBUTE synthesis_clearbox : natural;
ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
SIGNAL wire_pll7_clk : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_pll7_fbout : STD_LOGIC;
SIGNAL wire_pll7_locked : STD_LOGIC;
COMPONENT cycloneiii_pll
GENERIC
(
BANDWIDTH_TYPE : STRING := "auto";
CLK0_DIVIDE_BY : NATURAL := 1;
CLK0_DUTY_CYCLE : NATURAL := 50;
CLK0_MULTIPLY_BY : NATURAL := 0;
CLK0_PHASE_SHIFT : STRING := "UNUSED";
CLK1_DIVIDE_BY : NATURAL := 1;
CLK1_DUTY_CYCLE : NATURAL := 50;
CLK1_MULTIPLY_BY : NATURAL := 0;
CLK1_PHASE_SHIFT : STRING := "UNUSED";
CLK2_DIVIDE_BY : NATURAL := 1;
CLK2_DUTY_CYCLE : NATURAL := 50;
CLK2_MULTIPLY_BY : NATURAL := 0;
CLK2_PHASE_SHIFT : STRING := "UNUSED";
CLK3_DIVIDE_BY : NATURAL := 1;
CLK3_DUTY_CYCLE : NATURAL := 50;
CLK3_MULTIPLY_BY : NATURAL := 0;
CLK3_PHASE_SHIFT : STRING := "UNUSED";
CLK4_DIVIDE_BY : NATURAL := 1;
CLK4_DUTY_CYCLE : NATURAL := 50;
CLK4_MULTIPLY_BY : NATURAL := 0;
CLK4_PHASE_SHIFT : STRING := "UNUSED";
COMPENSATE_CLOCK : STRING := "clk0";
INCLK0_INPUT_FREQUENCY : NATURAL := 0;
OPERATION_MODE : STRING := "normal";
PLL_TYPE : STRING := "auto"
);
PORT
(
clk : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
fbin : IN STD_LOGIC := '0';
fbout : OUT STD_LOGIC;
inclk : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
clk <= ( wire_pll7_clk(4 DOWNTO 0));
locked <= wire_pll7_locked;
pll7 : cycloneiii_pll
GENERIC MAP (
BANDWIDTH_TYPE => "auto",
CLK0_DIVIDE_BY => 1,
CLK0_DUTY_CYCLE => 50,
CLK0_MULTIPLY_BY => 1,
CLK0_PHASE_SHIFT => "0",
CLK1_DIVIDE_BY => 1,
CLK1_DUTY_CYCLE => 50,
CLK1_MULTIPLY_BY => 2,
CLK1_PHASE_SHIFT => "0",
CLK2_DIVIDE_BY => 2,
CLK2_DUTY_CYCLE => 50,
CLK2_MULTIPLY_BY => 1,
CLK2_PHASE_SHIFT => "0",
CLK3_DIVIDE_BY => 1,
CLK3_DUTY_CYCLE => 50,
CLK3_MULTIPLY_BY => 1,
CLK3_PHASE_SHIFT => "0",
CLK4_DIVIDE_BY => 1,
CLK4_DUTY_CYCLE => 50,
CLK4_MULTIPLY_BY => 1,
CLK4_PHASE_SHIFT => "-5000",
COMPENSATE_CLOCK => "clk0",
INCLK0_INPUT_FREQUENCY => 20000,
OPERATION_MODE => "normal",
PLL_TYPE => "auto"
)
PORT MAP (
clk => wire_pll7_clk,
fbin => wire_pll7_fbout,
fbout => wire_pll7_fbout,
inclk => inclk,
locked => wire_pll7_locked
);
END RTL; --altpll_0_altpll_rnt2
--synthesis_resources = cycloneiii_pll 1 reg 5
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY altpll_0 IS
PORT
(
address : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
c0 : OUT STD_LOGIC;
c1 : OUT STD_LOGIC;
c2 : OUT STD_LOGIC;
c3 : OUT STD_LOGIC;
c4 : OUT STD_LOGIC;
clk : IN STD_LOGIC;
locked : OUT STD_LOGIC;
phasedone : OUT STD_LOGIC;
read : IN STD_LOGIC;
readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
reset : IN STD_LOGIC;
write : IN STD_LOGIC;
writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END altpll_0;
ARCHITECTURE RTL OF altpll_0 IS
ATTRIBUTE synthesis_clearbox : natural;
ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
ATTRIBUTE ALTERA_ATTRIBUTE : string;
SIGNAL wire_stdsync2_dout : STD_LOGIC;
SIGNAL wire_stdsync2_reset_n : STD_LOGIC;
SIGNAL wire_sd1_clk : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_sd1_inclk : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_sd1_locked : STD_LOGIC;
SIGNAL pfdena_reg : STD_LOGIC
-- synopsys translate_off
:= '1'
-- synopsys translate_on
;
ATTRIBUTE ALTERA_ATTRIBUTE OF pfdena_reg : SIGNAL IS "POWER_UP_LEVEL=HIGH";
SIGNAL wire_pfdena_reg_ena : STD_LOGIC;
SIGNAL prev_reset : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_w_lg_read17w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read23w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_select_control15w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_select_control21w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_select_status20w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_select_status14w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_reset11w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_address_range1w3w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_select_control15w16w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_select_control21w22w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL w_locked : STD_LOGIC;
SIGNAL w_pfdena : STD_LOGIC;
SIGNAL w_phasedone : STD_LOGIC;
SIGNAL w_pll_areset_in : STD_LOGIC;
SIGNAL w_reset : STD_LOGIC;
SIGNAL w_select_control : STD_LOGIC;
SIGNAL w_select_status : STD_LOGIC;
SIGNAL wire_w_address_range1w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_address_range2w : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll_0_stdsync_sv6
PORT
(
clk : IN STD_LOGIC;
din : IN STD_LOGIC;
dout : OUT STD_LOGIC;
reset_n : IN STD_LOGIC
);
END COMPONENT;
COMPONENT altpll_0_altpll_rnt2
PORT
(
clk : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
wire_w_lg_read17w(0) <= read AND wire_w_lg_w_lg_w_select_control15w16w(0);
wire_w_lg_read23w(0) <= read AND wire_w_lg_w_lg_w_select_control21w22w(0);
wire_w_lg_w_select_control15w(0) <= w_select_control AND w_pfdena;
wire_w_lg_w_select_control21w(0) <= w_select_control AND w_pll_areset_in;
wire_w_lg_w_select_status20w(0) <= w_select_status AND w_locked;
wire_w_lg_w_select_status14w(0) <= w_select_status AND w_phasedone;
wire_w_lg_reset11w(0) <= NOT reset;
wire_w_lg_w_address_range1w3w(0) <= NOT wire_w_address_range1w(0);
wire_w_lg_w_lg_w_select_control15w16w(0) <= wire_w_lg_w_select_control15w(0) OR wire_w_lg_w_select_status14w(0);
wire_w_lg_w_lg_w_select_control21w22w(0) <= wire_w_lg_w_select_control21w(0) OR wire_w_lg_w_select_status20w(0);
c0 <= wire_sd1_clk(0);
c1 <= wire_sd1_clk(1);
c2 <= wire_sd1_clk(2);
c3 <= wire_sd1_clk(3);
c4 <= wire_sd1_clk(4);
locked <= wire_sd1_locked;
phasedone <= '0';
readdata <= ( "000000000000000000000000000000" & wire_w_lg_read17w & wire_w_lg_read23w);
w_locked <= wire_stdsync2_dout;
w_pfdena <= pfdena_reg;
w_phasedone <= '1';
w_pll_areset_in <= prev_reset;
w_reset <= ((write AND w_select_control) AND writedata(0));
w_select_control <= ((NOT address(1)) AND address(0));
w_select_status <= ((NOT address(1)) AND wire_w_lg_w_address_range1w3w(0));
wire_w_address_range1w(0) <= address(0);
wire_w_address_range2w(0) <= address(1);
wire_stdsync2_reset_n <= wire_w_lg_reset11w(0);
stdsync2 : altpll_0_stdsync_sv6
PORT MAP (
clk => clk,
din => wire_sd1_locked,
dout => wire_stdsync2_dout,
reset_n => wire_stdsync2_reset_n
);
wire_sd1_inclk <= ( "0" & clk);
sd1 : altpll_0_altpll_rnt2
PORT MAP (
clk => wire_sd1_clk,
inclk => wire_sd1_inclk,
locked => wire_sd1_locked
);
PROCESS (clk, reset)
BEGIN
IF (reset = '1') THEN pfdena_reg <= '1';
ELSIF (clk = '1' AND clk'event) THEN
IF (wire_pfdena_reg_ena = '1') THEN pfdena_reg <= writedata(1);
END IF;
END IF;
END PROCESS;
wire_pfdena_reg_ena <= (write AND w_select_control);
PROCESS (clk, reset)
BEGIN
IF (reset = '1') THEN prev_reset <= '0';
ELSIF (clk = '1' AND clk'event) THEN prev_reset <= w_reset;
END IF;
END PROCESS;
END RTL; --altpll_0
--VALID FILE
| gpl-2.0 | 916fbfd941121ef8cf8bb9793ef6a856 | 0.662434 | 2.670379 | false | false | false | false |
DougFirErickson/parallella-hw | fpga/ip/xilinx/fifo_async_103x32/fifo_generator_v12_0/hdl/builtin/clk_x_pntrs_builtin.vhd | 6 | 43,418 | `protect begin_protected
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 30400)
`protect data_block
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`protect end_protected
| gpl-3.0 | f991f1538015e5ebc33122e18aa308ce | 0.948547 | 1.824132 | false | false | false | false |
estadofinito/biblioteca-vhdl | modulos/mod011-contador-0-499/contador_up_down_0_499.vhd | 1 | 1,465 | ----------------------------------------------------------------------------------
-- Compaa: Estado Finito
-- Ingeniero: Carlos Ramos
--
-- Fecha de creacin: 2014/05/20 15:32:00
-- Nombre del mdulo: contador_up_down_0_511 - Behavioral
-- Comentarios adicionales:
-- Contador de 9 bits (de 0 a 499), con valor después del reset igual a 59, y
-- con dos entradas: una para marcar incremento y otra para marcar decremento.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_1164.ALL;
entity contador_up_down_0_499 is
PORT(
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
cnt_up : IN STD_LOGIC;
cnt_down: IN STD_LOGIC;
contador: OUT STD_LOGIC_VECTOR(8 DOWNTO 0)
);
end contador_up_down_0_499;
architecture Behavioral of contador_up_down_0_499 is
signal temporal: UNSIGNED(8 DOWNTO 0) := "000111011";
begin
proceso_contador: process (clk, reset, cnt_up, cnt_down) begin
if (reset = '1') then
temporal <= "000111011";
elsif rising_edge(clk) then
if (cnt_up = '1' AND temporal < 499) then
temporal <= temporal + 1;
elsif (cnt_down = '1' AND temporal > 0) then
temporal <= temporal - 1;
end if;
end if;
end process;
contador <= STD_LOGIC_VECTOR(temporal);
end Behavioral; | lgpl-2.1 | 23522c737481380505d97a89b3eb12bf | 0.53347 | 3.792746 | false | false | false | false |
DougFirErickson/parallella-hw | fpga/ip/xilinx/memory_dp_48x4096/blk_mem_gen_v8_2/hdl/blk_mem_axi_write_wrapper.vhd | 8 | 66,283 | `protect begin_protected
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| gpl-3.0 | e6c205071a8e045ba3d22631392d4f4b | 0.9505 | 1.821462 | false | false | false | false |
rflamino/StellaBlue | core/A2601/src/Bench.vhd | 1 | 12,720 | -- A2601 Main Bench
-- Copyright 2006, 2010 Retromaster
--
-- This file is part of A2601.
--
-- A2601 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License,
-- or any later version.
--
-- A2601 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with A2601. If not, see <http://www.gnu.org/licenses/>.
--
library std;
use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
entity bench is
port (verbose: in std_logic);
end bench;
architecture bench of bench is
component A2601 is
port(vid_clk: in std_logic;
rst: in std_logic;
d: inout std_logic_vector(7 downto 0);
a: out std_logic_vector(12 downto 0);
r: out std_logic;
pa: inout std_logic_vector(7 downto 0);
pb: inout std_logic_vector(7 downto 0);
inpt4: in std_logic;
inpt5: in std_logic;
colu: out std_logic_vector(6 downto 0);
csyn: out std_logic;
vsyn: out std_logic;
hsyn: out std_logic;
au0: out std_logic;
au1: out std_logic;
av0: out std_logic_vector(3 downto 0);
av1: out std_logic_vector(3 downto 0);
ph0_out: out std_logic;
ph1_out: out std_logic);
end component;
component ram128x8 is
port(clk: in std_logic;
r: in std_logic;
d_in: in std_logic_vector(7 downto 0);
d_out: out std_logic_vector(7 downto 0);
a: in std_logic_vector(6 downto 0));
end component;
signal vid_clk: std_logic;
signal rst: std_logic;
signal d: std_logic_vector(7 downto 0);
signal a: std_logic_vector(15 downto 0);
signal pa: std_logic_vector(7 downto 0);
signal pb: std_logic_vector(7 downto 0);
signal inpt4: std_logic;
signal inpt5: std_logic;
signal colu: std_logic_vector(6 downto 0);
signal csyn: std_logic;
signal vsyn: std_logic;
signal hsyn: std_logic;
signal au0: std_logic;
signal au1: std_logic;
signal av0: std_logic_vector(3 downto 0);
signal av1: std_logic_vector(3 downto 0);
signal ph0: std_logic;
signal ph1: std_logic;
signal sc_clk: std_logic;
signal sc_r: std_logic;
signal sc_d_in: std_logic_vector(7 downto 0);
signal sc_d_out: std_logic_vector(7 downto 0);
signal sc_a: std_logic_vector(6 downto 0);
subtype bss_type is std_logic_vector(2 downto 0);
constant BANK00: bss_type := "000";
constant BANKF8: bss_type := "001";
constant BANKF6: bss_type := "010";
constant BANKFE: bss_type := "011";
constant BANKE0: bss_type := "100";
constant BANK3F: bss_type := "101";
signal bank: std_logic_vector(3 downto 0) := "0000";
signal tf_bank: std_logic_vector(1 downto 0);
signal e0_bank: std_logic_vector(2 downto 0);
signal e0_bank0: std_logic_vector(2 downto 0) := "000";
signal e0_bank1: std_logic_vector(2 downto 0) := "000";
signal e0_bank2: std_logic_vector(2 downto 0) := "000";
signal bss: bss_type;
signal sc: std_logic;
signal cpu_d: std_logic_vector(7 downto 0);
signal cpu_a: std_logic_vector(12 downto 0);
signal r: std_logic;
constant vid_clk_period: time := 17.5 ns;
--constant vid_clk_period: time := 17.4375 ns;
--constant vid_clk_period: time := 69.75 ns;
--constant clk_period: time := 279.365 ns;
--constant clk_period: time := 279 ns;
constant clk_period: time := 280 ns;
constant aud_period: time := 22.676 us;
procedure print_msg(
constant msg: in string;
constant val: in std_logic_vector(7 downto 0)) is
variable l: line;
begin
write(l, now);
write(l, string'(": "));
write(l, msg);
write(l, string'(": "));
hwrite(l, val);
writeline(output, l);
end print_msg;
procedure print_msg(
constant msg: in string;
constant val: in integer) is
variable l: line;
begin
write(l, now);
write(l, string'(": "));
write(l, msg);
write(l, string'(": "));
write(l, val);
writeline(output, l);
end print_msg;
procedure print_a_d(
constant a: in std_logic_vector(15 downto 0);
constant d: in std_logic_vector(7 downto 0)
) is
variable l: line;
begin
write(l, now);
write(l, string'(" A: "));
hwrite(l, a);
write(l, string'(" D: "));
hwrite(l, d);
writeline(output, l);
end print_a_d;
procedure status_report(
constant msg: in string) is
variable l: line;
begin
write(l, msg);
writeline(output, l);
end status_report;
type rom_array is array(0 to 65535) of std_logic_vector(7 downto 0);
shared variable rom: rom_array;
procedure load_rom(
constant fln: in string) is
file rf: text;
variable status: file_open_status;
variable l: line;
variable i: integer;
variable d: integer;
begin
file_open(status, rf, fln, read_mode);
assert (status = open_ok) report "Cannot open file.";
i := 0;
while not (endfile(rf)) loop
readline(rf, l);
read(l, d);
rom(i) := std_logic_vector(to_unsigned(d, 8));
i := i + 1 ;
end loop;
end procedure load_rom;
procedure write_byte(
file f: text;
constant val: in std_logic_vector(7 downto 0)) is
variable l: line;
begin
write(l, to_integer(unsigned(val)));
writeline(f, l);
end procedure write_byte;
procedure write_vsync(
file f: text) is
variable l: line;
begin
write(l, string'("VSYNC"));
writeline(f, l);
end procedure write_vsync;
begin
test_A2601: A2601
port map(vid_clk, rst, cpu_d, cpu_a, r, pa, pb, inpt4, inpt5, colu, csyn, vsyn, hsyn, au0, au1, av0, av1, ph0, ph1);
sc_ram128x8: ram128x8
port map(sc_clk, sc_r, sc_d_in, sc_d_out, sc_a);
-- This clock is phase shifted so that we can use Xilinx synchronous block RAM.
sc_clk <= not ph1;
sc_r <= '0' when cpu_a(12 downto 7) = "100000" else '1';
sc_d_in <= cpu_d;
sc_a <= cpu_a(6 downto 0);
-- ROM and SC output
process(cpu_a, d, sc_d_out, sc)
begin
if (cpu_a(12 downto 7) = "100001" and sc = '1') then
cpu_d <= sc_d_out;
elsif (cpu_a(12 downto 7) = "100000" and sc = '1') then
cpu_d <= "ZZZZZZZZ";
elsif (cpu_a(12) = '1') then
cpu_d <= d;
else
cpu_d <= "ZZZZZZZZ";
end if;
end process;
with cpu_a(11 downto 10) select e0_bank <=
e0_bank0 when "00",
e0_bank1 when "01",
e0_bank2 when "10",
"111" when "11",
"---" when others;
tf_bank <= bank(1 downto 0) when (cpu_a(11) = '0') else "11";
with bss select a <=
"0000" & cpu_a(11 downto 0) when BANK00,
"000" & bank(0) & cpu_a(11 downto 0) when BANKF8,
"00" & bank(1 downto 0) & cpu_a(11 downto 0) when BANKF6,
"000" & bank(0) & cpu_a(11 downto 0) when BANKFE,
"000" & e0_bank & cpu_a(9 downto 0) when BANKE0,
"000" & tf_bank & cpu_a(10 downto 0) when BANK3F,
"----------------" when others;
bankswch: process(ph0)
begin
if (ph0'event and ph0 = '1') then
if (rst = '1') then
bank <= "0000";
e0_bank0 <= "000";
e0_bank1 <= "000";
e0_bank2 <= "000";
else
case bss is
when BANKF8 =>
if (cpu_a = "1" & X"FF8") then
bank <= "0000";
elsif (cpu_a = "1" & X"FF9") then
bank <= "0001";
end if;
when BANKF6 =>
if (cpu_a = "1" & X"FF6") then
bank <= "0000";
elsif (cpu_a = "1" & X"FF7") then
bank <= "0001";
elsif (cpu_a = "1" & X"FF8") then
bank <= "0010";
elsif (cpu_a = "1" & X"FF9") then
bank <= "0011";
end if;
when BANKFE =>
if (cpu_a = "0" & X"1FE") then
bank <= "0000";
elsif (cpu_a = "1" & X"1FE") then
bank <= "0001";
end if;
when BANKE0 =>
if (cpu_a(12 downto 4) = "1" & X"FE" and cpu_a(3) = '0') then
e0_bank0 <= cpu_a(2 downto 0);
elsif (cpu_a(12 downto 4) = "1" & X"FE" and cpu_a(3) = '1') then
e0_bank1 <= cpu_a(2 downto 0);
elsif (cpu_a(12 downto 4) = "1" & X"FF" and cpu_a(3) = '0') then
e0_bank2 <= cpu_a(2 downto 0);
end if;
when BANK3F =>
--if (cpu_a(12 downto 6) = "0000000") then
if (cpu_a = "0" & X"03F") then
bank(1 downto 0) <= cpu_d(1 downto 0);
end if;
when others =>
null;
end case;
end if;
end if;
end process;
bss <= BANK00;
sc <= '0';
pa <= "11111111";
pb(7 downto 1) <= "1111111";
inpt4 <= '1';
inpt5 <= '1';
rst_sig: process
begin
rst <= '1';
wait for 3 * clk_period / 2;
rst <= '0';
wait;
end process;
vid_clk_sig: process
begin
vid_clk <= '1';
wait for vid_clk_period / 2;
vid_clk <= '0';
wait for vid_clk_period / 2;
end process;
d <= rom(to_integer(unsigned(a)));
video: process
variable i: integer;
variable hcnt: integer;
variable vcnt: integer;
file ff: text;
begin
i := 0;
file_open(ff, "..\video\video.txt", write_mode);
wait for clk_period / 2;
while (true) loop
while (vsyn /= '1') loop
wait for clk_period;
end loop;
while (vsyn /= '0') loop
wait for clk_period;
end loop;
vcnt := 0;
while (vsyn /= '1') loop
if (hsyn = '1') then
if (hcnt /= 0) then
vcnt := vcnt + 1;
end if;
hcnt := 0;
write_byte(ff, X"FF");
else
write_byte(ff, colu & "0");
hcnt := hcnt + 1;
end if;
wait for clk_period;
end loop;
print_msg("Frame", i);
write_vsync(ff);
i := i + 1;
end loop;
file_close(ff);
end process;
audio: process
variable val: unsigned(4 downto 0);
file fa: text;
variable auv0: unsigned(3 downto 0);
variable auv1: unsigned(3 downto 0);
begin
file_open(fa, "..\audio\audio.txt", write_mode);
while (true) loop
val := "00000";
if (au0 = '1') then
val := "0" & unsigned(av0);
end if;
if (au1 = '1') then
val := val + ("0" & unsigned(av1));
end if;
write_byte(fa, std_logic_vector("000" & val));
wait for aud_period;
end loop;
end process;
process
begin
load_rom("..\rom\astrblst.txt");
wait;
end process;
end bench;
| mit | d070037ad776991371d98cabf133f269 | 0.479088 | 3.66465 | false | false | false | false |
richard42/CoCo3FPGA | T65.vhd | 1 | 15,927 | -- ****
-- T65(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 301 more merging
-- Ver 300 Bugfixes by ehenciak added, started tidyup *bust*
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- 65xx compatible microprocessor core
--
-- Version : 0246
--
-- Copyright (c) 2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t65/
--
-- Limitations :
--
-- 65C02 and 65C816 modes are incomplete
-- Undocumented instructions are not supported
-- Some interface signals behaves incorrect
--
-- File history :
--
-- 0246 : First release
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T65_Pack.all;
-- ehenciak 2-23-2005 : Added the enable signal so that one doesn't have to use
-- the ready signal to limit the CPU.
entity T65 is
port(
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65C816
Res_n : in std_logic;
Enable : in std_logic;
Clk : in std_logic;
Rdy : in std_logic;
Abort_n : in std_logic;
IRQ_n : in std_logic;
NMI_n : in std_logic;
SO_n : in std_logic;
R_W_n : out std_logic;
Sync : out std_logic;
EF : out std_logic;
MF : out std_logic;
XF : out std_logic;
ML_n : out std_logic;
VP_n : out std_logic;
VDA : out std_logic;
VPA : out std_logic;
A : out std_logic_vector(23 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0)
);
end T65;
architecture rtl of T65 is
-- Registers
signal ABC, X, Y, D : std_logic_vector(15 downto 0);
signal P, AD, DL : std_logic_vector(7 downto 0) := x"00";
signal BAH : std_logic_vector(7 downto 0);
signal BAL : std_logic_vector(8 downto 0);
signal PBR : std_logic_vector(7 downto 0);
signal DBR : std_logic_vector(7 downto 0);
signal PC : unsigned(15 downto 0);
signal S : unsigned(15 downto 0);
signal EF_i : std_logic;
signal MF_i : std_logic;
signal XF_i : std_logic;
signal IR : std_logic_vector(7 downto 0);
signal MCycle : std_logic_vector(2 downto 0);
signal Mode_r : std_logic_vector(1 downto 0);
signal ALU_Op_r : std_logic_vector(3 downto 0);
signal Write_Data_r : std_logic_vector(2 downto 0);
signal Set_Addr_To_r : std_logic_vector(1 downto 0);
signal PCAdder : unsigned(8 downto 0);
signal RstCycle : std_logic;
signal IRQCycle : std_logic;
signal NMICycle : std_logic;
signal B_o : std_logic;
signal SO_n_o : std_logic;
signal IRQ_n_o : std_logic;
signal NMI_n_o : std_logic;
signal NMIAct : std_logic;
signal Break : std_logic;
-- ALU signals
signal BusA : std_logic_vector(7 downto 0);
signal BusA_r : std_logic_vector(7 downto 0);
signal BusB : std_logic_vector(7 downto 0);
signal ALU_Q : std_logic_vector(7 downto 0);
signal P_Out : std_logic_vector(7 downto 0);
-- Micro code outputs
signal LCycle : std_logic_vector(2 downto 0);
signal ALU_Op : std_logic_vector(3 downto 0);
signal Set_BusA_To : std_logic_vector(2 downto 0);
signal Set_Addr_To : std_logic_vector(1 downto 0);
signal Write_Data : std_logic_vector(2 downto 0);
signal Jump : std_logic_vector(1 downto 0);
signal BAAdd : std_logic_vector(1 downto 0);
signal BreakAtNA : std_logic;
signal ADAdd : std_logic;
signal AddY : std_logic;
signal PCAdd : std_logic;
signal Inc_S : std_logic;
signal Dec_S : std_logic;
signal LDA : std_logic;
signal LDP : std_logic;
signal LDX : std_logic;
signal LDY : std_logic;
signal LDS : std_logic;
signal LDDI : std_logic;
signal LDALU : std_logic;
signal LDAD : std_logic;
signal LDBAL : std_logic;
signal LDBAH : std_logic;
signal SaveP : std_logic;
signal Write : std_logic;
signal really_rdy : std_logic;
signal R_W_n_i : std_logic;
begin
-- ehenciak : gate Rdy with read/write to make an "OK, it's
-- really OK to stop the processor now if Rdy is
-- deasserted" signal
really_rdy <= Rdy or not(R_W_n_i);
-- ehenciak : Drive R_W_n_i off chip.
R_W_n <= R_W_n_i;
Sync <= '1' when MCycle = "000" else '0';
EF <= EF_i;
MF <= MF_i;
XF <= XF_i;
ML_n <= '0' when IR(7 downto 6) /= "10" and IR(2 downto 1) = "11" and MCycle(2 downto 1) /= "00" else '1';
VP_n <= '0' when IRQCycle = '1' and (MCycle = "101" or MCycle = "110") else '1';
VDA <= '1' when Set_Addr_To_r /= "000" else '0'; -- Incorrect !!!!!!!!!!!!
VPA <= '1' when Jump(1) = '0' else '0'; -- Incorrect !!!!!!!!!!!!
mcode : T65_MCode
port map(
Mode => Mode_r,
IR => IR,
MCycle => MCycle,
P => P,
LCycle => LCycle,
ALU_Op => ALU_Op,
Set_BusA_To => Set_BusA_To,
Set_Addr_To => Set_Addr_To,
Write_Data => Write_Data,
Jump => Jump,
BAAdd => BAAdd,
BreakAtNA => BreakAtNA,
ADAdd => ADAdd,
AddY => AddY,
PCAdd => PCAdd,
Inc_S => Inc_S,
Dec_S => Dec_S,
LDA => LDA,
LDP => LDP,
LDX => LDX,
LDY => LDY,
LDS => LDS,
LDDI => LDDI,
LDALU => LDALU,
LDAD => LDAD,
LDBAL => LDBAL,
LDBAH => LDBAH,
SaveP => SaveP,
Write => Write
);
alu : T65_ALU
port map(
Mode => Mode_r,
Op => ALU_Op_r,
BusA => BusA_r,
BusB => BusB,
P_In => P,
P_Out => P_Out,
Q => ALU_Q
);
process (Res_n, Clk)
begin
if Res_n = '0' then
PC <= (others => '0'); -- Program Counter
IR <= "00000000";
S <= (others => '0'); -- Dummy !!!!!!!!!!!!!!!!!!!!!
D <= (others => '0');
PBR <= (others => '0');
DBR <= (others => '0');
Mode_r <= (others => '0');
ALU_Op_r <= "1100";
Write_Data_r <= "000";
Set_Addr_To_r <= "00";
R_W_n_i <= '1';
EF_i <= '1';
MF_i <= '1';
XF_i <= '1';
elsif Clk'event and Clk = '1' then
if (Enable = '1') then
if (really_rdy = '1') then
R_W_n_i <= not Write or RstCycle;
D <= (others => '1'); -- Dummy
PBR <= (others => '1'); -- Dummy
DBR <= (others => '1'); -- Dummy
EF_i <= '0'; -- Dummy
MF_i <= '0'; -- Dummy
XF_i <= '0'; -- Dummy
if MCycle = "000" then
Mode_r <= Mode;
if IRQCycle = '0' and NMICycle = '0' then
PC <= PC + 1;
end if;
if IRQCycle = '1' or NMICycle = '1' then
IR <= "00000000";
else
IR <= DI;
end if;
end if;
ALU_Op_r <= ALU_Op;
Write_Data_r <= Write_Data;
if Break = '1' then
Set_Addr_To_r <= "00";
else
Set_Addr_To_r <= Set_Addr_To;
end if;
if Inc_S = '1' then
S <= S + 1;
end if;
if Dec_S = '1' and RstCycle = '0' then
S <= S - 1;
end if;
if LDS = '1' then
S(7 downto 0) <= unsigned(ALU_Q);
end if;
if IR = "00000000" and MCycle = "001" and IRQCycle = '0' and NMICycle = '0' then
PC <= PC + 1;
end if;
--
-- jump control logic
--
case Jump is
when "01" =>
PC <= PC + 1;
when "10" =>
PC <= unsigned(DI & DL);
when "11" =>
if PCAdder(8) = '1' then
if DL(7) = '0' then
PC(15 downto 8) <= PC(15 downto 8) + 1;
else
PC(15 downto 8) <= PC(15 downto 8) - 1;
end if;
end if;
PC(7 downto 0) <= PCAdder(7 downto 0);
when others => null;
end case;
end if;
end if;
end if;
end process;
PCAdder <= resize(PC(7 downto 0),9) + resize(unsigned(DL(7) & DL),9) when PCAdd = '1'
else "0" & PC(7 downto 0);
process (Clk)
begin
if Clk'event and Clk = '1' then
if (Enable = '1') then
if (really_rdy = '1') then
if MCycle = "000" then
if LDA = '1' then
ABC(7 downto 0) <= ALU_Q;
end if;
if LDX = '1' then
X(7 downto 0) <= ALU_Q;
end if;
if LDY = '1' then
Y(7 downto 0) <= ALU_Q;
end if;
if (LDA or LDX or LDY) = '1' then
P <= P_Out;
end if;
end if;
if SaveP = '1' then
P <= P_Out;
end if;
if LDP = '1' then
P <= ALU_Q;
end if;
if IR(4 downto 0) = "11000" then
case IR(7 downto 5) is
when "000" =>
P(Flag_C) <= '0';
when "001" =>
P(Flag_C) <= '1';
when "010" =>
P(Flag_I) <= '0';
when "011" =>
P(Flag_I) <= '1';
when "101" =>
P(Flag_V) <= '0';
when "110" =>
P(Flag_D) <= '0';
when "111" =>
P(Flag_D) <= '1';
when others =>
end case;
end if;
if IR = "00000000" and MCycle = "011" and RstCycle = '0' and NMICycle = '0' and IRQCycle = '0' then
P(Flag_B) <= '1';
end if;
if IR = "00000000" and MCycle = "100" and RstCycle = '0' and (NMICycle = '1' or IRQCycle = '1') then
P(Flag_I) <= '1';
P(Flag_B) <= B_o;
end if;
if SO_n_o = '1' and SO_n = '0' then
P(Flag_V) <= '1';
end if;
if RstCycle = '1' and Mode_r /= "00" then
P(Flag_1) <= '1';
P(Flag_D) <= '0';
P(Flag_I) <= '1';
end if;
P(Flag_1) <= '1';
B_o <= P(Flag_B);
SO_n_o <= SO_n;
IRQ_n_o <= IRQ_n;
NMI_n_o <= NMI_n;
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------
--
-- Buses
--
---------------------------------------------------------------------------
process (Res_n, Clk)
begin
if Res_n = '0' then
BusA_r <= (others => '0');
BusB <= (others => '0');
AD <= (others => '0');
BAL <= (others => '0');
BAH <= (others => '0');
DL <= (others => '0');
elsif Clk'event and Clk = '1' then
if (Enable = '1') then
if (Rdy = '1') then
BusA_r <= BusA;
BusB <= DI;
case BAAdd is
when "01" =>
-- BA Inc
AD <= std_logic_vector(unsigned(AD) + 1);
BAL <= std_logic_vector(unsigned(BAL) + 1);
when "10" =>
-- BA Add
BAL <= std_logic_vector(resize(unsigned(BAL(7 downto 0)),9) + resize(unsigned(BusA),9));
when "11" =>
-- BA Adj
if BAL(8) = '1' then
BAH <= std_logic_vector(unsigned(BAH) + 1);
end if;
when others =>
end case;
-- ehenciak : modified to use Y register as well (bugfix)
if ADAdd = '1' then
if (AddY = '1') then
AD <= std_logic_vector(unsigned(AD) + unsigned(Y(7 downto 0)));
else
AD <= std_logic_vector(unsigned(AD) + unsigned(X(7 downto 0)));
end if;
end if;
if IR = "00000000" then
BAL <= (others => '1');
BAH <= (others => '1');
if RstCycle = '1' then
BAL(2 downto 0) <= "100";
elsif NMICycle = '1' then
BAL(2 downto 0) <= "010";
else
BAL(2 downto 0) <= "110";
end if;
if Set_addr_To_r = "11" then
BAL(0) <= '1';
end if;
end if;
if LDDI = '1' then
DL <= DI;
end if;
if LDALU = '1' then
DL <= ALU_Q;
end if;
if LDAD = '1' then
AD <= DI;
end if;
if LDBAL = '1' then
BAL(7 downto 0) <= DI;
end if;
if LDBAH = '1' then
BAH <= DI;
end if;
end if;
end if;
end if;
end process;
Break <= (BreakAtNA and not BAL(8)) or (PCAdd and not PCAdder(8));
with Set_BusA_To select
BusA <= DI when "000",
ABC(7 downto 0) when "001",
X(7 downto 0) when "010",
Y(7 downto 0) when "011",
std_logic_vector(S(7 downto 0)) when "100",
P when "101",
(others => '-') when others;
with Set_Addr_To_r select
A <= "0000000000000001" & std_logic_vector(S(7 downto 0)) when "01",
DBR & "00000000" & AD when "10",
"00000000" & BAH & BAL(7 downto 0) when "11",
PBR & std_logic_vector(PC(15 downto 8)) & std_logic_vector(PCAdder(7 downto 0)) when others;
with Write_Data_r select
DO <= DL when "000",
ABC(7 downto 0) when "001",
X(7 downto 0) when "010",
Y(7 downto 0) when "011",
std_logic_vector(S(7 downto 0)) when "100",
P when "101",
std_logic_vector(PC(7 downto 0)) when "110",
std_logic_vector(PC(15 downto 8)) when others;
-------------------------------------------------------------------------
--
-- Main state machine
--
-------------------------------------------------------------------------
process (Res_n, Clk)
begin
if Res_n = '0' then
MCycle <= "001";
RstCycle <= '1';
IRQCycle <= '0';
NMICycle <= '0';
NMIAct <= '0';
elsif Clk'event and Clk = '1' then
if (Enable = '1') then
if (really_rdy = '1') then
if MCycle = LCycle or Break = '1' then
MCycle <= "000";
RstCycle <= '0';
IRQCycle <= '0';
NMICycle <= '0';
if NMIAct = '1' then
NMICycle <= '1';
elsif IRQ_n_o = '0' and P(Flag_I) = '0' then
IRQCycle <= '1';
end if;
else
MCycle <= std_logic_vector(unsigned(MCycle) + 1);
end if;
if NMICycle = '1' then
NMIAct <= '0';
end if;
if NMI_n_o = '1' and NMI_n = '0' then
NMIAct <= '1';
end if;
end if;
end if;
end if;
end process;
end;
| bsd-3-clause | ff1c2e2ec71b07001adcf93c47bc2e19 | 0.50361 | 3.054075 | false | false | false | false |
dskntIndustry/Hardware | hdl_library/SPI/SPI_Slave.vhd | 1 | 3,300 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library hdl_library_CommonFunctions;
use hdl_library_CommonFunctions.MathHelpers.all;
--library hdl_library_CommonFunctions;
--use hdl_library_CommonFunctions.CommonFunctions.all;
entity SPI_Slave is
generic
(
--G_SPI_FREQUENCY : integer;
G_SPI_TRANSACTION_SIZE : integer
);
port
(
clock : in std_logic;
enable : in std_logic;
SCLK : in std_logic;
MISO : out std_logic;
MOSI : in std_logic;
SS_n : in std_logic;
ready : out std_logic
);
end entity; --SPI_Slave
architecture arch of SPI_Slave is
type T_SPI_STATES is (SPI_IDLE, SPI_SERIAL_RECEIVE, SPI_RX_FINISHED);
signal SPI_current_state : T_SPI_STATES := SPI_IDLE;
signal SPI_next_state : T_SPI_STATES;
signal SPI_bit_counter : std_logic_vector(log2(G_SPI_TRANSACTION_SIZE) -1 downto 0) := (others => '0');
signal SPI_previous_bit_counter : std_logic_vector(log2(G_SPI_TRANSACTION_SIZE) -1 downto 0) := (others => '0');
signal SPI_SCLK_bufclock : std_logic := '0';
signal SPI_SCLK_rising : std_logic := '0';
signal SPI_SS_n_bufclock : std_logic := '0';
signal SPI_SS_n_falling : std_logic := '0';
signal counter_enable : std_logic := '0';
signal counter_reset : std_logic := '0';
signal received_data : std_logic_vector(G_SPI_TRANSACTION_SIZE -1 downto 0) := (others => '0');
begin
Delayer:process(clock)
begin
if rising_edge(clock) then
SPI_SS_n_bufclock <= SS_n;
SPI_SCLK_bufclock <= SCLK;
end if;
end process Delayer; -- Delayer
SPI_SS_n_falling <= '1' when SPI_SS_n_bufclock = '1' and SS_n = '0' else '0';
SPI_SCLK_rising <= '1' when SPI_SCLK_bufclock = '0' and SCLK = '1' else '0';
SPI_States_Updater:process(clock)
begin
if rising_edge(clock) then
if SCLK = '1' then
SPI_current_state <= SPI_next_state;
end if;
end if;
end process ; -- SPI_States_Updater
SPI_FSM_logic:process(SPI_current_state, SPI_SS_n_falling, SPI_previous_bit_counter, counter_reset, counter_enable)
begin
ready <= '1';
case(SPI_current_state) is
when SPI_IDLE =>
--counter_reset <= '1';
if SPI_SS_n_falling = '1' then
counter_reset <= '0';
counter_enable <= '1';
SPI_next_state <= SPI_SERIAL_RECEIVE;
end if;
when SPI_SERIAL_RECEIVE =>
ready <= '0';
if SS_n = '1' and SPI_previous_bit_counter = (G_SPI_TRANSACTION_SIZE - 1) then
counter_enable <= '0';
SPI_next_state <= SPI_IDLE;
end if;
--when SPI_RX_FINISHED =>
-- counter_reset <= '1';
-- counter_enable <= '0';
-- SPI_next_state <= SPI_IDLE;
when others => report "Unreachable state" severity failure;
end case;
end process ; -- SPI_FSM_logic
SPI_Counter:process(SCLK)
begin
if rising_edge(SCLK) then
if counter_enable = '1' then
received_data((G_SPI_TRANSACTION_SIZE - 1) - conv_integer(SPI_previous_bit_counter)) <= MOSI;
SPI_bit_counter <= SPI_bit_counter + 1;
SPI_previous_bit_counter <= SPI_bit_counter;
end if;
if counter_reset = '1' then
SPI_bit_counter <= (others => '0');
SPI_previous_bit_counter <= (others => '0');
end if;
end if;
end process SPI_Counter; -- SPI_Counter
end architecture; -- arch | gpl-3.0 | 9c0cd4761ea3aae680a1ddb93832a937 | 0.637576 | 2.770781 | false | false | false | false |
estadofinito/biblioteca-vhdl | todos-los-archivos/contador_reloj.vhd | 3 | 2,130 | ----------------------------------------------------------------------------------
-- Compañía: Estado Finito
-- Ingeniero: Carlos Ramos
--
-- Fecha de creación: 2012/10/26 12:26:23
-- Nombre del módulo: contador_reloj - Behavioral
-- Descripción:
-- Contador para el reloj. Se encarga de recibir una señal de 1/60Hz (1 minuto)
-- y contar el tiempo para mostrar la hora y los minutos.
-- A la salida, entrega los cuatro dígitos correspondientes a HH:mm.
--
-- Revisión:
-- Revisión 0.01 - Archivo creado.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_1164.ALL;
entity contador_reloj is
PORT (
clk : IN STD_LOGIC; --Reloj de 1Hz.
reset: IN STD_LOGIC; --Señal de reset.
H1 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); --Segundo digito de la hora.
H0 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --Primer digito de la hora.
M1 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); --Segundo digito de los minutos.
M0 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) --Primer digito de los minutos.
);
end contador_reloj;
architecture Behavioral of contador_reloj is
signal mm1: UNSIGNED(2 downto 0) := "000" ;
signal mm0: UNSIGNED(3 downto 0) := "0000";
signal hh1: UNSIGNED(2 downto 0) := "000" ;
signal hh0: UNSIGNED(3 downto 0) := "0000";
begin
reloj: process (clk, reset) begin
if reset = '1' then
hh1 <= "000" ;
hh0 <= "0000";
mm1 <= "000" ;
mm0 <= "0000";
elsif rising_edge(clk) then
mm0 <= mm0 + 1;
if mm0 = 9 then
mm1 <= mm1 + 1;
mm0 <= "0000";
end if;
-- Al pasar 59 minutos, contar una hora.
if mm1 = 5 AND mm0 = 9 then
hh0 <= hh0 + 1;
mm1 <= "000";
end if;
if hh0 = 9 then
hh1 <= hh1 + 1;
hh0 <= "0000";
end if;
-- Al pasar 23:59, regresar a 00:00.
if hh1 = 2 AND hh0 = 3 AND mm1 = 5 AND mm0 = 9 then
hh1 <= "000";
hh0 <= "0000";
end if;
end if;
end process;
--Asignación de señales.
H1 <= STD_LOGIC_VECTOR(hh1);
H0 <= STD_LOGIC_VECTOR(hh0);
M1 <= STD_LOGIC_VECTOR(mm1);
M0 <= STD_LOGIC_VECTOR(mm0);
end Behavioral; | lgpl-2.1 | 0d34f49121626fbdbd4d535cb2feb901 | 0.570423 | 2.851406 | false | false | false | false |
dskntIndustry/Hardware | hdl_library/SPI/SPI_SlaveTB.vhd | 1 | 3,285 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library hdl_library_CommonFunctions;
use hdl_library_CommonFunctions.MathHelpers.all;
library hdl_library_CommonFunctions;
use hdl_library_CommonFunctions.CommonFunctions.all;
library hdl_library_ClockGenerator;
use hdl_library_ClockGenerator.all;
entity SPI_SlaveTB is
end entity; --SPI_SlaveTB
architecture tb of SPI_SlaveTB is
constant G_CLOCK_FREQUENCY : integer := 100E6;
constant G_CLOCK_DIVIDER : integer := 100;
constant G_SPI_TRANSACTION_SIZE : integer := 32;
--declarations
signal clock : std_logic := '0';
signal clock_n : std_logic := '0';
signal SCLK : std_logic := '0';
signal MISO : std_logic := '0';
signal MOSI : std_logic := '0';
signal SS_n : std_logic := '0';
signal enable : std_logic := '0';
signal ready : std_logic := '0';
signal clock_divider1 : integer := 1000;
signal clock_output : std_logic := '0';
signal clock_output_n : std_logic := '0';
--signal clock_counter : std_logic_vector(log2(G_CLOCK_FREQUENCY/G_SPI_FREQUENCY) - 1 downto 0) := (others => '0');
signal data : std_logic_vector(G_SPI_TRANSACTION_SIZE -1 downto 0) := X"A0B0C0D0";
begin
clock <= not clock after (1 sec / G_CLOCK_FREQUENCY) / 2;
clock_n <= not clock;
Test:process
begin
SS_n <= '1';
enable <= '1';
wait_until_rising_edges(clock, 1000);
SS_n <= '0';
wait_until_rising_edges(SCLK, G_SPI_TRANSACTION_SIZE);
SS_n <= '1';
wait_until_rising_edges(clock, 1000);
SS_n <= '0';
wait_until_rising_edges(SCLK, G_SPI_TRANSACTION_SIZE);
SS_n <= '1';
wait for 10 us;
report "End of test"
severity FAILURE;
end process; --Test
clock_generator : entity hdl_library_ClockGenerator.ClockGenerator
generic map
(
G_CLOCK_FREQUENCY => G_CLOCK_FREQUENCY,
G_CLOCK_DIVIDER => G_CLOCK_DIVIDER
)
port map
(
clock => clock,
enable => enable,
clock_output => SCLK,
clock_output_n => clock_output_n
);
--SLCK_generator:process(clock)
--begin
-- if rising_edge(clock) then
-- if enable = '1' then
-- clock_counter <= clock_counter + 1;
-- if clock_counter = (G_CLOCK_FREQUENCY/G_SPI_FREQUENCY) -1 then
-- clock_counter <= (others => '0');
-- SCLK <= not SCLK;
-- end if;
-- end if;
-- end if;
--end process SLCK_generator; -- SLCK_generator
MOSI_generator:process(SCLK)
begin
--if rising_edge(clock) then
if enable = '1' then
if rising_edge(SCLK) and SS_n = '0' then
MOSI <= data(data'high);
data <= data(data'high-1 downto 0) & '1';
--data <= data(data'high-1 downto 0) & data(data'high);
end if;
end if;
--end if;
end process MOSI_generator; -- SLCK_generator
dut : entity work.SPI_Slave
generic map
(
-- G_CLOCK_FREQUENCY => G_CLOCK_FREQUENCY,
-- G_BASE_FREQUENCY => G_BASE_FREQUENCY,
-- G_SPI_FREQUENCY => G_SPI_FREQUENCY,
G_SPI_TRANSACTION_SIZE => G_SPI_TRANSACTION_SIZE
)
port map
(
clock => clock,
enable => enable,
SCLK => SCLK,
MISO => MISO,
MOSI => MOSI,
SS_n => SS_n,
ready => ready
);
end architecture; -- tb | gpl-3.0 | e34a29bcafbda4638135613ad258f3ae | 0.614307 | 2.78626 | false | false | false | false |
hgunicamp/Mips8B | src_test/memory_test.vhdl | 1 | 3,820 | -- Teste geral para a estrutura do Processador Mips8B
Library Ieee;
Use Ieee.Std_Logic_1164.all;
Use Ieee.Numeric_Std.all;
Entity memory_test is
Port(Clock_Mem: In Std_Logic;
MAddr: In Std_Logic_Vector(7 downto 0);
MCmd: In Std_Logic_Vector(1 downto 0);
MData: In Std_Logic_Vector(7 downto 0);
SData: Out Std_Logic_Vector(7 downto 0);
SCmdAccept: Out Std_Logic);
End Entity memory_test;
Architecture behave of memory_test is
Type Memory_Array is Array(Natural Range <>) of Std_Logic_Vector(7 downto 0);
Use Work.MIPS8B_Base.ocpIDLE_little;
Use Work.MIPS8B_Base.ocpWR_little;
Use Work.MIPS8B_Base.ocpRD_little;
Use Work.MIPS8B_Base.ocpNULL_little;
Use Work.MIPS8B_Base.ocpDVA_little;
Begin
Memory: Process
Variable int_SCmdAccept: Std_Logic;
Variable address: Unsigned(7 downto 0);
Variable mem_int: Memory_Array(0 to 255) := (
"00100000", "00000001", "00000000", "11001000",
"00100000", "00000010", "00000000", "10001001",
"00100000", "00000011", "00000000", "11001101",
"10100000", "00100010", "00000000", "00000000",
"00100000", "00100001", "00000000", "00000001",
"00100000", "01000010", "00000000", "11101111",
"00010000", "01100001", "00000000", "00000010",
"00010000", "00000000", "00000000", "11111100",
"00000000", "00000000", "00001000", "00100101",
"00100000", "00000110", "00000000", "11001000",
"00100000", "11000111", "00000000", "00000001",
"00100000", "00000101", "00000000", "11001101",
"00010000", "10100111", "00000000", "00001011",
"10000000", "11000011", "00000000", "00000000",
"10000000", "11100100", "00000000", "00000000",
"00000000", "10000011", "00010000", "00101010",
"00010000", "01000000", "00000000", "00000100",
"00100000", "00100001", "00000000", "00000001",
"10100000", "11000100", "00000000", "00000000",
"10100000", "11100011", "00000000", "00000000",
"00000000", "11100000", "00110000", "00100000",
"00100000", "11100111", "00000000", "00000001",
"00010000", "00000000", "00000000", "11110110",
"00010000", "00000001", "00000000", "00000010",
"00010000", "00000000", "00000000", "11110000",
"00100000", "00000011", "00000000", "11001101",
"00100000", "00000001", "00000000", "11001000",
"10000000", "00100010", "00000000", "00000000",
"10100000", "00100010", "00000000", "00000000",
"00100000", "00100001", "00000000", "00000001",
"00010000", "01100001", "00000000", "11111100",
"00010000", "00000000", "00000000", "11111100",
Others => "00000000");
Begin
Wait Until Clock_Mem'Event and Clock_Mem='1';
Case MCmd is
When ocpWR_little =>
If int_SCmdAccept = ocpNULL_little then
int_SCmdAccept := ocpDVA_little;
address := Unsigned(MAddr);
mem_int(to_integer(address)) := MData;
Else
int_SCmdAccept := ocpNULL_little;
End If;
When ocpRD_little =>
If int_SCmdAccept = ocpNULL_little then
int_SCmdAccept := ocpDVA_little;
address := Unsigned(MAddr);
SData <= mem_int(to_integer(address));
Else
int_SCmdAccept := ocpNULL_little;
End If;
When Others =>
int_SCmdAccept := ocpNULL_little;
End Case;
SCmdAccept <= int_SCmdAccept;
End Process Memory;
End Architecture behave;
Configuration general_test of memory_test is
For behave
End For;
End Configuration general_test;
| unlicense | 13ceffbf325f93c6fbfe3a012e6a86db | 0.579581 | 3.893986 | false | true | false | false |
dskntIndustry/Hardware | hdl_library/DSP/Filter/FIR/FIR_Core.vhd | 1 | 2,069 | library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.std_logic_arith.ALL;
use IEEE.std_logic_unsigned.ALL;
library hdl_library_CommonFunctions;
use hdl_library_CommonFunctions.MathHelpers.all;
entity FIR_Core is
generic
(
C_FIR_FILTER_ORDER : integer;
C_DATA_IN_WIDTH : integer;
C_DATA_OUT_WIDTH : integer;
C_COEFF_WIDTH : integer;
C_MULTIPLIER_DELAY : integer;
C_ADDER_DELAY : integer
);
port
(
clock : in std_logic;
enable : in std_logic;
xn : in std_logic_vector(C_DATA_IN_WIDTH - 1 downto 0);
xn_nd : in std_logic;
yn : out std_logic_vector(C_DATA_OUT_WIDTH - 1 downto 0);
yn_valid : out std_logic;
current_coefficient : in std_logic_vector(C_COEFF_WIDTH - 1 downto 0);
current_coefficient_address : out std_logic_vector(log2(C_FIR_FILTER_ORDER) - 1 downto 0)
);
end entity ; -- FIR_Core
architecture arch of FIR_Core is
type T_samples_RAM is array (0 to C_FIR_FILTER_ORDER-1) of std_logic_vector(C_DATA_IN_WIDTH - 1 downto 0);
signal samples_RAM : T_samples_RAM := (others => (others => '0'));
signal product : std_logic_vector((xn'length + current_coefficient'length - 1) downto 0) := (others => '0');
signal sum : std_logic_vector((xn'length - 1) downto 0) := (others => '0');
begin
-- 8 clock cycles latency
signed_multiplier : entity work.signed_multiplier
port map
(
A => X"12345678",
B => X"00000001",
P => product,
CLK => clock
);
-- 8 clock cycles latency
signed_adder : entity work.signed_adder
port map
(
A => X"12345678",
B => X"00000001",
S => sum,
CLK => clock
);
sequencer:process(clock)
begin
if rising_edge(clock) then
if xn_nd = '1' then
shift_samples_RAM : for i in 0 to C_FIR_FILTER_ORDER - 1 loop
samples_RAM(i+1) <= samples_RAM(i);
end loop ; -- shift_samples_RAM
samples_RAM(0) <= xn;
end if;
end if;
end process sequencer; -- sequencer
end architecture ; -- arch
| gpl-3.0 | 62ab47dc839279a76fc835afc8c41841 | 0.609473 | 2.845942 | false | false | false | false |
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| gpl-3.0 | dfd2286a0f32c62c9c98312d0db9811c | 0.93573 | 1.877669 | false | false | false | false |
steveEECSrubin/usc_projects | ABB/DSP_RX_FSM_changed.vhd | 1 | 8,012 | -- ***************************************************************************
-- File Name: DSP_RX_FSM.vhd
-- File Description:
-- This module receives the packet from DSP connected to RocketIO module.
-- The reason why dsp_tx and dsp_rx are different processess is because ideally
-- rocketio incoming data would be coming at slightly different phase/freq clock than onboard clock.
-- Therefore the received data must be read using rx recovered clock.
-- The clock to this module should be eventually be the MGT rx recovered clock.
-- As long as the RX K-Char is high nothing happens. The moment k-Char goes low it indicates
-- that the packet is being received. Ideally the K-char should be low for the entire lenght of
-- received packet. But in this case the DSP is unable send packet in such format instead the K-char
-- goes high and low many time during the length of packet.
-- The incoming packet bytes are immediately stored in BRAM2 one by one every clk cycle
-- Since the lenght of packet is known a timer is used to decide when to stop writing in BRAM2.
-- After that timer the k-char should be always high untill the next packet arrives. Also this avoids
-- interprocess handshake sigals which are suspected to be one of the possible reasons for data corruption.
-- ***************************************************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
entity DSP_RX_FSM is
port
(
--%%%%%%%%%%%%%%%%%%%%% INPUT PORTS %%%%%%%%%%%%%%%%%%%%%%%%%%%%%
USER_CLK : in std_logic;
MASTER : in std_logic;
START_OPERATION : in std_logic;
RECEIVER_READY : in std_logic;
RX1_CHAR_IS_K : in std_logic;
HMB : in std_logic_vector(1 downto 0);
RX1_DATA : in std_logic_vector(7 downto 0);
BRAM2_DOA : in std_logic_vector(7 downto 0);
--%%%%%%%%%%%%%%%%%%%%% OUTPUT PORTS %%%%%%%%%%%%%%%%%%%%%%%%%%%%%
PACKET_RECEIVED : out std_logic;
BRAM2_ENA : out std_logic;
BRAM2_WEA : out std_logic;
BRAM2_DIA : out std_logic_vector(7 downto 0);
BRAM2_ADDRA : out std_logic_vector(11 downto 0);
CHIPSCOPE_DEBUG : out std_logic_vector(9 downto 0)
);
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of DSP_RX_FSM : entity is "v4fx_mgtwizard_v1_7, Coregen v12.1";
end DSP_RX_FSM;
architecture RTL of DSP_RX_FSM is
----*********************************Signal Declarations********************************
signal master_i : std_logic := '0';
signal start_operation_i : std_logic := '0';
signal packet_error_i : std_logic := '0';
signal rx1_char_is_k_i : std_logic := '0';
signal rx1_k_i : std_logic := '0';
signal packet_received_i : std_logic := '0';
signal receiver_ready_i : std_logic := '0';
signal bram2_ena_i : std_logic := '0';
signal bram2_wea_i : std_logic := '0';
signal command_available_i : std_logic := '0';
signal command_checked_i : std_logic := '0';
signal hmb_i : std_logic_vector(1 downto 0) := "00";
signal RX_STATE : std_logic_vector(3 downto 0) := x"0";
signal temp_rx : std_logic_vector(7 downto 0) := x"00";
signal rx1_data_i : std_logic_vector(7 downto 0) := x"00";
signal bram2_doa_i : std_logic_vector(7 downto 0) := x"00";
signal bram2_dia_i : std_logic_vector(7 downto 0) := x"00";
signal bram2_addra_i : std_logic_vector(11 downto 0) := x"000";
signal chipscope_debug_i : std_logic_vector(9 downto 0) := "0000000000";
signal TOKEN_TIMER : integer range 0 to 1023 := 0;
-- added by Steve Rubin
signal current_check_sum : std_logic_vector(7 downto 0);
signal check_sum_error : std_logic := '0';
constant PACKET_LENGTH : integer := 300;
--*********************************Main Body of Code**********************************
------------------------------------------------------
begin
--%%%%%%%%%%% signal connections for INPUT PORTS %%%%%%%%%%%%%%%%%%%%%%%
master_i <= MASTER;
start_operation_i <= START_OPERATION;
rx1_char_is_k_i <= RX1_CHAR_IS_K;
hmb_i <= HMB;
rx1_data_i <= RX1_DATA;
bram2_doa_i <= BRAM2_DOA;
--%%%%%%%%%%% signal connections for OUTPUT PORTS %%%%%%%%%%%%%%%%%%%%%%%
BRAM2_ENA <= bram2_ena_i;
BRAM2_WEA <= bram2_wea_i;
BRAM2_DIA <= bram2_dia_i;
BRAM2_ADDRA <= bram2_addra_i;
CHIPSCOPE_DEBUG <= chipscope_debug_i;
process(USER_CLK)
begin
if (rising_edge(USER_CLK)) then
chipscope_debug_i(0) <= RX_STATE(0);
temp_rx <= rx1_data_i;
rx1_k_i <= rx1_char_is_k_i;
case RX_STATE is
when x"0" => -- state 0
bram2_ena_i <= '0';
bram2_wea_i <= '0';
bram2_dia_i <= x"00";
bram2_addra_i <= x"000";
TOKEN_TIMER <= 0;
-- during power ON this state would wait for start operation but to go high.
-- the initial power on time delay is defined in MMC_top_level module using 3 cascaded counters.
if(start_operation_i = '0')then
RX_STATE <= x"0";
elsif(start_operation_i = '1' and master_i = '0')then
RX_STATE <= x"0";
else -- only go to state 1 if the board is master(meaning connected to DSP)
RX_STATE <= x"1";
end if;
when others => -- state 1
if (rx1_char_is_k_i = '0')
RX_STATE <= x"1";
--/*----------------------------------------------------------------
-- when k-char goes low start timer and enable BRAM2 write and increament address every clk.
if(TOKEN_TIMER = 0 and temp_rx = x"0A")then -- !! WEIRD shoudn't it be rx1_data_i?
TOKEN_TIMER <= TOKEN_TIMER+1;
bram2_ena_i <= '1';
bram2_wea_i <= '1';
bram2_dia_i <= temp_rx; -- !! WEIRD shoudn't it be rx1_data_i?
bram2_addra_i <= bram2_addra_i + x"001";
check_sum_error <= '0';
signal current_check_sum <= x"0A";
elsif(TOKEN_TIMER < PACKET_LENGTH)then
TOKEN_TIMER <= TOKEN_TIMER+1;
bram2_ena_i <= '1';
bram2_wea_i <= '1';
bram2_dia_i <= temp_rx; -- !! WEIRD shoudn't it be rx1_data_i?
bram2_addra_i <= bram2_addra_i + x"001";
check_sum_error <= '0';
current_check_sum <= current_check_sum xor temp_rx;
-- when k_char goes high before timer expires meaning that byte is framing character inserted
-- by DSP and not actual data.therefore disable BRAM2 write for that particular clk cycle.
elsif(TOKEN_TIMER = PACKET_LENGTH)then
TOKEN_TIMER <= TOKEN_TIMER+1;
bram2_ena_i <= '1';
bram2_wea_i <= '0';
bram2_dia_i <= x"00";
bram2_addra_i <= bram2_addra_i;
if(current_check_sum /= temp_rx) then -- !! WEIRD shoudn't it be rx1_data_i?
check_sum_error <= '1';
end if;
-- The received packet lenght is about 300byte or clk cycles
-- after 300 cycles wait(no operation) until clk cycle 800.
-- because during that time dsp_tx module would be using BRAM2 and therefore to prevent
-- any overwriting on BRAM2(because of false triggering on receiving section) it would be better
-- to wait untill BRAM2 is avaiablable again.
-- BRAM2 is available when dsp_tx finishes transmitting packet to DSP
elsif(TOKEN_TIMER >= PACKET_LENGTH and TOKEN_TIMER < 800)then
TOKEN_TIMER <= TOKEN_TIMER+1;
bram2_ena_i <= '0';
bram2_wea_i <= '0';
bram2_dia_i <= x"00";
bram2_addra_i <= x"000";
else -- reset to default in any other condition.
TOKEN_TIMER <= 0;
bram2_ena_i <= '0';
bram2_wea_i <= '0';
bram2_dia_i <= x"00";
bram2_addra_i <= x"000";
check_sum_error <= '1';
end if;
end if;
end case;
end if;
end process;
--
end RTL;
| mit | 23773cc3053702d901f230a404b6d84d | 0.567773 | 3.135812 | false | false | false | false |
DougFirErickson/parallella-hw | fpga/ip/xilinx/fifo_async_103x32/fifo_generator_v12_0/hdl/ramfifo/wr_handshaking_flags.vhd | 6 | 12,657 | `protect begin_protected
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`protect end_protected
| gpl-3.0 | 1da337302ba871cb0750ca8ecd58652a | 0.932132 | 1.890798 | false | false | false | false |
estadofinito/biblioteca-vhdl | todos-los-archivos/contador_up_down_0_499.vhd | 2 | 1,471 | ----------------------------------------------------------------------------------
-- Compañía: Estado Finito
-- Ingeniero: Carlos Ramos
--
-- Fecha de creación: 2014/05/20 15:32:00
-- Nombre del módulo: contador_up_down_0_511 - Behavioral
-- Comentarios adicionales:
-- Contador de 9 bits (de 0 a 499), con valor después del reset igual a 59, y
-- con dos entradas: una para marcar incremento y otra para marcar decremento.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_1164.ALL;
entity contador_up_down_0_499 is
PORT(
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
cnt_up : IN STD_LOGIC;
cnt_down: IN STD_LOGIC;
contador: OUT STD_LOGIC_VECTOR(8 DOWNTO 0)
);
end contador_up_down_0_499;
architecture Behavioral of contador_up_down_0_499 is
signal temporal: UNSIGNED(8 DOWNTO 0) := "000111011";
begin
proceso_contador: process (clk, reset, cnt_up, cnt_down) begin
if (reset = '1') then
temporal <= "000111011";
elsif rising_edge(clk) then
if (cnt_up = '1' AND temporal < 499) then
temporal <= temporal + 1;
elsif (cnt_down = '1' AND temporal > 0) then
temporal <= temporal - 1;
end if;
end if;
end process;
contador <= STD_LOGIC_VECTOR(temporal);
end Behavioral; | lgpl-2.1 | 1e8eccf6fe989961e250a3f701a5370d | 0.535471 | 3.778351 | false | false | false | false |
hgunicamp/Mips8B | src_design/mips8b_components.vhdl | 1 | 5,768 | Library Ieee;
Use Ieee.Std_Logic_1164.all;
Use Work.MIPS8B_Base.all;
Package MIPS8B_Components is
-- Inteface para o PC.
Component PC_System is
Generic(N: Natural := 8);
Port(clock: in Std_Logic;
Reset_n: in Std_Logic;
en_Out_PC: in Std_Logic;
load_PC: in Std_Logic;
inc_PC: in Std_Logic;
in_PC: in Std_Logic_Vector(N-3 downto 0);
out_PC: out Std_Logic_Vector(N-3 downto 0);
address_PC: out Std_Logic_Vector(N-3 downto 0));
End Component;
-- Interface para o sistema de I/O.
Component MIPS8B_IO_System is
Generic(N: Natural := 8);
Port(clock: in Std_Logic;
Reset_n: in Std_Logic;
-- Controle do endereço fornecido pelo sistema
en_RMem: in Std_Logic;
en_RMem_Inc: in Std_Logic;
crt_Mux_IO: in Std_Logic;
crt_MEM: in MemoryOP;
-- Controle dos Dados de I/O.
en_RData_in: in Std_Logic;
en_RData_out: in Std_Logic;
-- Valores de endereço para transações de I/O.
out_PC: in Std_Logic_Vector(N-3 downto 0);
out_DPath: in Std_Logic_Vector(N-1 downto 0);
in_Data: in Std_Logic_Vector(N-1 downto 0);
-- Registradores para dados de I/O.
RMem: out Std_Logic_Vector(N-1 downto 0);
RData_in: out Std_Logic_Vector(N-1 downto 0);
RData_out: out Std_Logic_Vector(N-1 downto 0);
-- Interface de controle.
Cmd: out Std_Logic_Vector(1 downto 0);
CmdAccept: in Std_Logic;
IO_OK: out Std_Logic);
End Component;
-- Interface para o controlador principal.
Component MIPS8B_DP_Control is
Generic(N: Natural := 8;
SH_SIZE: Natural := 3;
RF_ADDR_SIZE: Natural := 3);
Port(clock: in Std_Logic;
Reset_n: in Std_Logic;
IO_OK: in Std_Logic;
eq_Flag: in Std_Logic;
Opcode: in Std_Logic_Vector(4 downto 0);
in_Bus: in Std_Logic_Vector(N-1 downto 0);
-- Controle para o Registrer File.
crt_RFile: out Std_Logic;
en_Raddress_RF: out Std_Logic;
address_RF: out Std_Logic_Vector(RF_ADDR_SIZE-1 downto 0);
-- Controle para os registradores Intermediarios.
en_R1A_ULA: out Std_Logic;
en_R1B_ULA: out Std_Logic;
en_R2_ULA: out Std_Logic;
en_Reg_SH: out Std_Logic;
-- Controle para os multiplexadores.
crt_Mux_ULA: out Std_Logic_Vector(1 downto 0);
crt_Mux_Acc: out Std_Logic;
crt_Mux_RF: out Std_Logic;
-- Controle das unidades funcionais.
crt_ULA: out Std_Logic_Vector(2 downto 0);
crt_SH: out Std_Logic_Vector(1 downto 0);
crt_Acc: out Std_Logic_Vector(1 downto 0);
-- Controle do PC.
en_Out_PC: out Std_Logic;
load_PC: out Std_Logic;
inc_PC: out Std_Logic;
-- Controle para o sistema de IO.
en_ROpcode: out Std_Logic;
en_RMem: out Std_Logic;
en_RMem_Inc: out Std_Logic;
en_RData_in: out Std_Logic;
en_RData_out: out Std_Logic;
crt_Mux_IO: out Std_Logic;
crt_MEM: out MemoryOP;
-- Valor do comprimento do shift.
S_SH: out Std_Logic_Vector(SH_SIZE-1 downto 0);
-- Valor do campo imediato
out_IMM: out Std_Logic_Vector(N-1 downto 0));
End Component;
-- Interface para o Datapath.
Component Mips8B_DataPath is
Generic( N: Natural := 8;
RF_SIZE: Natural := 8;
SH_SIZE: Natural := 3;
RF_ADDR_SIZE: Natural := 3);
Port(clock: in Std_Logic;
-- Controle dos Registradores do Shift Register.
en_Reg_SH: in Std_Logic;
-- Controle para Shifter.
crt_SH: in Std_Logic_Vector(1 downto 0);
S_SH: in Std_Logic_Vector(SH_SIZE-1 downto 0);
-- Controle dos Registradores da ULA.
en_R1A_ULA: in Std_Logic;
en_R1B_ULA: in Std_Logic;
en_R2_ULA: in Std_Logic;
-- Controle para ULA.
crt_ULA: in Std_Logic_Vector(2 downto 0);
crt_Mux_ULA: in Std_Logic_Vector(1 downto 0);
-- Controle para Register File.
crt_RFile: in Std_Logic;
crt_Mux_RF: in Std_Logic;
address_RF: in Std_Logic_Vector(RF_ADDR_SIZE-1 downto 0);
en_Raddress_RF: in Std_logic;
-- Controle para o Acumulador.
crt_Acc: in Std_Logic_Vector(1 downto 0);
crt_Mux_Acc: in Std_Logic;
-- Entradas do Datapath.
in_PC: in Std_Logic_Vector(N-3 downto 0);
in_IMM: in Std_Logic_Vector(N-1 downto 0);
-- Flag de Igualdade de Operandos.
eq_Flag: out Std_Logic;
-- Saida do resultado do Acumulador.
out_Acc: out Std_Logic_Vector(N-1 downto 0));
End Component;
End Package MIPS8B_Components;
| unlicense | f53284c50f0ad12e8d5949c110576588 | 0.485253 | 3.65736 | false | false | false | false |
Monash-2015-Ultrasonic/Logs | Final System Code/SYSTEMV3/Source/IP/FIR/FIR_sim/auk_dspip_lib_pkg_hpfir.vhd | 2 | 23,067 | -- (C) 2001-2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Alex, 02-10-07, this package declaration results in error at built time on a new machine
--
use work.auk_dspip_math_pkg_hpfir.all;
package auk_dspip_lib_pkg_hpfir is
--Component names:
--auk_dspip_atlantic_sink
--auk_dspip_atlantic_source
--auk_dspip_interface_controller
--auk_dspip_avalon_streaming_controller_hpfir
--auk_dspip_avalon_streaming_controller_pe_fir_91
--auk_dspip_avalon_streaming_sink_hpfir
--auk_dspip_avalon_streaming_source_hpfir
--auk_dspip_delay_fir_91
--auk_dspip_fastadd_fir_91
--auk_dspip_fastaddsub_fir_91
--auk_dspip_pipelined_adder_fir_91
--auk_dspip_fast_accumulator_fir_91
--auk_dspip_fifo_pfc_fir_91
--auk_dspip_fpcompiler_alufp
--auk_dspip_fpcompiler_aslf
--auk_dspip_fpcompiler_asrf
--auk_dspip_fpcompiler_castftox
--auk_dspip_fpcompiler_castxtof
--auk_dspip_fpcompiler_clzf
--auk_dspip_fpcompiler_mulfp
--auk_dspip_pfc_fir_91
--auk_dspip_roundsat_fir_91
component auk_dspip_atlantic_sink is
generic(
WIDTH : integer := 16;
PACKET_SIZE : natural := 4;
log2packet_size : integer := 2
);
port(
clk : in std_logic;
reset_n : in std_logic;
----------------- DESIGN SIDE SIGNALS
data_available : out std_logic; --goes high when new data is available
data : out std_logic_vector(WIDTH-1 downto 0);
sink_ready_ctrl : in std_logic; --the controller will tell
--the interface whether
--new input can be accepted.
sink_stall : out std_logic; --needs to stall the design
--if no new data is coming
packet_error : out std_logic_vector (1 downto 0); --this is for SOP and EOP check only.
--when any of these doesn't behave as
--expected, the error is flagged.
send_sop : out std_logic; -- transmit SOP signal to the design.
-- It only transmits the legal SOP.
send_eop : out std_logic; -- transmit EOP signal to the design.
-- It only transmits the legal EOP.
----------------- ATLANTIC SIDE SIGNALS
at_sink_ready : out std_logic; --it will be '1' whenever the
--sink_ready_ctrl signal is high.
at_sink_valid : in std_logic;
at_sink_data : in std_logic_vector(WIDTH-1 downto 0);
at_sink_sop : in std_logic := '0';
at_sink_eop : in std_logic := '0';
at_sink_error : in std_logic_vector(1 downto 0) --it indicates to the data source
--that the SOP and EOP signals
--are not received as expected.
);
end component auk_dspip_atlantic_sink;
component auk_dspip_atlantic_source is
generic(
WIDTH : integer := 16;
packet_size : natural := 4;
LOG2packet_size : integer := 2;
multi_channel : BOOLEAN := TRUE
);
port(
clk : in std_logic;
reset_n : in std_logic;
----------------- DESIGN SIDE SIGNALS
data : in std_logic_vector (WIDTH-1 downto 0);
data_count : in std_logic_vector (LOG2packet_size-1 downto 0) := (others => '0');
source_valid_ctrl : in std_logic; --the controller will tell
--the interface whether
--new input can be accepted.
source_stall : out std_logic; --needs to stall the design
--if no new data is coming
packet_error : in std_logic_vector (1 downto 0);
----------------- ATLANTIC SIDE SIGNALS
at_source_ready : in std_logic;
at_source_valid : out std_logic;
at_source_data : out std_logic_vector (WIDTH-1 downto 0);
at_source_channel : out std_logic_vector (log2packet_size-1 downto 0);
at_source_error : out std_logic_vector (1 downto 0);
at_source_sop : out std_logic;
at_source_eop : out std_logic
);
-- Declarations
end component auk_dspip_atlantic_source;
component auk_dspip_interface_controller IS
PORT(
clk : in std_logic;
reset : IN std_logic;
ready : in std_logic;
sink_packet_error : IN std_logic_vector (1 DOWNTO 0);
sink_stall : IN std_logic;
source_stall : IN std_logic;
valid : IN std_logic;
reset_design : OUT std_logic;
reset_n : OUT std_logic;
sink_ready_ctrl : OUT std_logic;
source_packet_error : OUT std_logic_vector (1 DOWNTO 0);
source_valid_ctrl : OUT std_logic;
stall : OUT std_logic
);
-- Declarations
end component auk_dspip_interface_controller ;
component auk_dspip_avalon_streaming_controller_hpfir is
port(
clk : in std_logic;
--clk_en : in std_logic := '1';
reset_n : in std_logic;
--ready : in std_logic;
sink_packet_error : in std_logic_vector (1 downto 0);
--sink_stall : in std_logic;
source_stall : in std_logic;
valid : in std_logic;
reset_design : out std_logic;
sink_ready_ctrl : out std_logic;
source_packet_error : out std_logic_vector (1 downto 0);
source_valid_ctrl : out std_logic;
stall : out std_logic
);
-- Declarations
end component auk_dspip_avalon_streaming_controller_hpfir;
component auk_dspip_avalon_streaming_controller_pe_fir_91 is
generic (
FIFO_WIDTH_g : natural := 8;
ENABLE_PIPELINE_DEPTH_g : natural := 0; -- this value should match the depth of the enable pipeline in the core
FAMILY_g : string := "Stratix II";
MEM_TYPE_g : string := "Auto"
);
port(
clk : in std_logic;
clk_en : in std_logic := '1';
reset_n : in std_logic;
ready : in std_logic;
sink_packet_error : in std_logic_vector (1 downto 0);
sink_stall : in std_logic;
source_stall : in std_logic;
valid : in std_logic;
reset_design : out std_logic;
sink_ready_ctrl : out std_logic;
source_packet_error : out std_logic_vector (1 downto 0);
source_valid_ctrl : out std_logic;
stall : out std_logic;
data_in : in std_logic_vector(FIFO_WIDTH_g-1 downto 0);
data_out : out std_logic_vector(FIFO_WIDTH_g-1 downto 0);
design_stall : out std_logic
);
-- Declarations
end component auk_dspip_avalon_streaming_controller_pe_fir_91;
component auk_dspip_avalon_streaming_sink_hpfir is
generic(
WIDTH_g : integer := 16;
DATA_WIDTH : integer := 8;
DATA_PORT_COUNT : integer := 3;
PACKET_SIZE_g : natural := 4
--FIFO_DEPTH_g : natural := 5 --if PFC mode is selected, this generic
--is used for passing the poly_factor.
--MIN_DATA_COUNT_g : natural := 2;
--PFC_MODE_g : boolean := false;
--SOP_EOP_CALC_g : boolean := false; -- calculate sop and eop rather than
-- reading value from fifo
--FAMILY_g : string := "Stratix II";
--MEM_TYPE_g : string := "Auto"
);
port(
clk : in std_logic;
reset_n : in std_logic;
----------------- DESIGN SIDE SIGNALS
data : out std_logic_vector(WIDTH_g-1 downto 0);
data_valid : out std_logic_vector(0 downto 0);
sink_ready_ctrl : in std_logic; --the controller will tell
--the interface whether
--new input can be accepted.
--sink_stall : out std_logic; --needs to stall the design
--if no new data is coming
packet_error : out std_logic_vector (1 downto 0); --this is for SOP and EOP check only.
--when any of these doesn't behave as
--expected, the error is flagged.
--send_sop : out std_logic; -- transmit SOP signal to the design.
-- It only transmits the legal SOP.
--send_eop : out std_logic; -- transmit EOP signal to the design.
-- It only transmits the legal EOP.
----------------- ATLANTIC SIDE SIGNALS
at_sink_ready : out std_logic; --it will be '1' whenever the
--sink_ready_ctrl signal is high.
at_sink_valid : in std_logic;
at_sink_data : in std_logic_vector(WIDTH_g-1 downto 0);
at_sink_sop : in std_logic := '0';
at_sink_eop : in std_logic := '0';
at_sink_error : in std_logic_vector(1 downto 0) := "00" --it indicates
--that there is an error in the packet.
);
end component auk_dspip_avalon_streaming_sink_hpfir;
component auk_dspip_avalon_streaming_source_hpfir is
generic(
WIDTH_g : integer := 8;
DATA_WIDTH : integer := 8;
DATA_PORT_COUNT : integer := 1;
PACKET_SIZE_g : natural := 2;
FIFO_DEPTH_g : natural := 0;
HAVE_COUNTER_g : boolean := false;
COUNTER_LIMIT_g : natural := 4;
--MULTI_CHANNEL_g : boolean := true;
USE_PACKETS : integer := 1;
--FAMILY_g : string := "Stratix II";
--MEM_TYPE_g : string := "Auto";
ENABLE_BACKPRESSURE_g : boolean := true
);
port(
clk : in std_logic;
reset_n : in std_logic;
----------------- DESIGN SIDE SIGNALS
data_in : in std_logic_vector (WIDTH_g-1 downto 0);
data_count : in std_logic_vector (log2_ceil_one(PACKET_SIZE_g)-1 downto 0) := (others => '0');
source_valid_ctrl : in std_logic;
source_stall : out std_logic;
packet_error : in std_logic_vector (1 downto 0);
----------------- AVALON_STREAMING SIDE SIGNALS
at_source_ready : in std_logic;
at_source_valid : out std_logic;
at_source_data : out std_logic_vector (WIDTH_g-1 downto 0);
at_source_channel : out std_logic_vector (log2_ceil_one(PACKET_SIZE_g)-1 downto 0);
at_source_error : out std_logic_vector (1 downto 0);
at_source_sop : out std_logic;
at_source_eop : out std_logic
);
-- Declarations
end component auk_dspip_avalon_streaming_source_hpfir;
component auk_dspip_roundsat_hpfir is
generic (
IN_WIDTH_g : natural := 8; -- i/p data width
REM_LSB_BIT_g : natural := 2; -- no. of lsb to be removed
REM_LSB_TYPE_g : string := "Truncation"; -- TRUNCATE/ROUND_UP
REM_MSB_BIT_g : natural := 2; -- no. of msb to be removed
REM_MSB_TYPE_g : string := "Truncation" -- TRUNCATE/SATURATE
);
port (
clk : in std_logic;
reset_n : in std_logic;
enable : in std_logic;
datain : in std_logic_vector(IN_WIDTH_g-1 downto 0);
valid : out std_logic;
dataout : out std_logic_vector(IN_WIDTH_g-REM_LSB_BIT_g-REM_MSB_BIT_g-1 downto 0)
);
end component auk_dspip_roundsat_hpfir;
component auk_dspip_delay_fir_91 is
generic (
WIDTH_g : natural := 8; -- data width
DELAY_g : natural := 8;
-- number of clock cycles the input
-- will be delayed by
MEMORY_TYPE_g : string := "AUTO";
-- possible values are "m4k", "m512",
-- "register", "mram", "auto",
-- "lutram", "M9K", "M144K".
-- Any other string will be interpreted
-- as "auto"
REGISTER_FIRST_g : natural := 1;
-- if "1", the first delay is guaranteed
-- to be in registers
REGISTER_LAST_g : natural := 1); -- if "1", the last delay is guaranteed
-- to be in registers
port (
clk : in std_logic;
reset : in std_logic;
enable : in std_logic; -- global clock enable
datain : in std_logic_vector(WIDTH_g-1 downto 0);
dataout : out std_logic_vector(WIDTH_g-1 downto 0)
);
end component auk_dspip_delay_fir_91;
component auk_dspip_fastadd_fir_91 is
generic (
INWIDTH_g : natural := 18;
LABWIDTH_g : natural := 16);
-- width of lab in selected device ( 10 or 16 in Cyclone,
-- Cylone II, Stratix and Stratix II. Don't know
-- Stratix III yet.
port (
datain1 : in std_logic_vector(INWIDTH_g-1 downto 0);
datain2 : in std_logic_vector(INWIDTH_g-1 downto 0);
clk : in std_logic;
enable : in std_logic;
reset : in std_logic;
dataout : out std_logic_vector(INWIDTH_g downto 0));
end component auk_dspip_fastadd_fir_91;
component auk_dspip_fastaddsub_fir_91 is
generic (
INWIDTH_g : natural := 18;
LABWIDTH_g : natural := 16);
-- width of lab in selected device ( 10 or 16 in Cyclone,
-- Cylone II, Stratix and Stratix II. Don't know
-- Stratix III yet.
port (
datain1 : in std_logic_vector(INWIDTH_g-1 downto 0);
datain2 : in std_logic_vector(INWIDTH_g-1 downto 0);
add_nsub : in std_logic;
clk : in std_logic;
enable : in std_logic;
reset : in std_logic;
dataout : out std_logic_vector(INWIDTH_g downto 0));
end component auk_dspip_fastaddsub_fir_91;
component auk_dspip_pipelined_adder_fir_91 is
generic (
INWIDTH_g : natural := 42;
-- width of lab in selected device ( 10 or 16 in Cyclone,
-- Cylone II, Stratix and Stratix II.
-- Alex : should I use 19 bits for Stratix III?
-- The rational being 10 ALM (2 bits x ALM + the carry chain inside the same LAB for efficiency.
LABWIDTH_g : natural := 38);
port (
datain1 : in std_logic_vector(INWIDTH_g-1 downto 0);
datain2 : in std_logic_vector(INWIDTH_g-1 downto 0);
clk : in std_logic;
enable : in std_logic;
reset : in std_logic;
dataout : out std_logic_vector(INWIDTH_g downto 0));
end component auk_dspip_pipelined_adder_fir_91;
component auk_dspip_fast_accumulator_fir_91 is
generic (
DATA_WIDTH_g : natural := 42;
-- width of lab in selected device ( 10 or 16 in Cyclone,
-- Cylone II, Stratix and Stratix II.
-- for Stratix III is 20 so labwidth should be set to 18.
-- The rational being 10 ALM (2 bits x ALM + the carry chain inside the same LAB for efficiency.
LABWIDTH_g : natural := 38;
NUM_OF_CHANNELS_g : natural := 1;
ACCUM_OUT_WIDTH_g : natural := 48;
ACCUM_MEM_TYPE_g : string := "auto");
port (
reset : in std_logic;
clk : in std_logic;
enb : in std_logic;
add_to_zero : in std_logic;
datai : in std_logic_vector(DATA_WIDTH_g-1 downto 0);
datao : out std_logic_vector(ACCUM_OUT_WIDTH_g-1 downto 0));
end component auk_dspip_fast_accumulator_fir_91;
component auk_dspip_fifo_pfc_fir_91 is
generic (
NUM_CHANNELS_g : integer := 5;
POLY_FACTOR_g : integer := 3;
DATA_WIDTH_g : integer := 16;
ALMOST_FULL_VALUE_g : integer := 2;
RAM_TYPE_g : string := "AUTO";
CALCULATE_USED_WORDS_ONCE : boolean := true
);
port (
datai : in std_logic_vector(DATA_WIDTH_g-1 downto 0);
datao : out std_logic_vector(DATA_WIDTH_g-1 downto 0);
channel_out : out std_logic_vector(log2_ceil(NUM_CHANNELS_g)-1 downto 0);
used_w : out std_logic_vector(log2_ceil(POLY_FACTOR_g * NUM_CHANNELS_g)+1 downto 0);
wrreq : in std_logic;
rdreq : in std_logic;
almost_full : out std_logic;
empty : out std_logic;
sclr : in std_logic;
clk : in std_logic;
reset : in std_logic;
enable : in std_logic
);
end component auk_dspip_fifo_pfc_fir_91;
component auk_dspip_fpcompiler_alufp is
port (
sysclk : in std_logic;
reset : in std_logic;
enable : in std_logic;
addsub : in std_logic;
aa : in std_logic_vector (42 downto 1);
aasat, aazip : in std_logic;
bb : in std_logic_vector (42 downto 1);
bbsat, bbzip : in std_logic;
cc : out std_logic_vector (42 downto 1);
ccsat, cczip : out std_logic
);
end component auk_dspip_fpcompiler_alufp;
component auk_dspip_fpcompiler_aslf is
port (
inbus : in std_logic_vector (32 downto 1);
shift : in std_logic_vector (5 downto 1);
outbus : out std_logic_vector (32 downto 1)
);
end component auk_dspip_fpcompiler_aslf;
component auk_dspip_fpcompiler_asrf is
port (
inbus : in std_logic_vector (32 downto 1);
shift : in std_logic_vector (5 downto 1);
outbus : out std_logic_vector (32 downto 1)
);
end component auk_dspip_fpcompiler_asrf;
component auk_dspip_fpcompiler_castftox is
port (
aa : in std_logic_vector (32 downto 1);
cc : out std_logic_vector (42 downto 1);
ccsat, cczip : out std_logic
);
end component auk_dspip_fpcompiler_castftox;
component auk_dspip_fpcompiler_castxtof is
port (
sysclk : in std_logic;
reset : in std_logic;
enable : in std_logic;
aa : in std_logic_vector (42 downto 1);
aasat, aazip : in std_logic;
cc : out std_logic_vector (32 downto 1)
);
end component auk_dspip_fpcompiler_castxtof;
component auk_dspip_fpcompiler_clzf is
port (
frac : in std_logic_vector (32 downto 1);
count : out std_logic_vector (5 downto 1)
);
end component auk_dspip_fpcompiler_clzf;
component auk_dspip_fpcompiler_mulfp is
port (
sysclk : in std_logic;
reset : in std_logic;
enable : in std_logic;
aa : in std_logic_vector (42 downto 1);
aasat, aazip : in std_logic;
bb : in std_logic_vector (42 downto 1);
bbsat, bbzip : in std_logic;
cc : out std_logic_vector (42 downto 1);
ccsat, cczip : out std_logic
);
end component auk_dspip_fpcompiler_mulfp;
component auk_dspip_pfc_fir_91 is
generic (
NUM_CHANNELS_g : integer := 5;
POLY_FACTOR_g : integer := 3;
DATA_WIDTH_g : integer := 16;
RAM_TYPE_g : string := "AUTO"
);
port (
datai : in std_logic_vector(DATA_WIDTH_g-1 downto 0);
datao : out std_logic_vector(DATA_WIDTH_g-1 downto 0);
channel_out : out std_logic_vector(log2_ceil(NUM_CHANNELS_g)-1 downto 0);
in_valid : in std_logic;
out_valid : out std_logic;
clk : in std_logic;
reset : in std_logic;
enable : in std_logic
);
end component auk_dspip_pfc_fir_91;
component auk_dspip_roundsat_fir_91 is
generic (
IN_WIDTH_g : natural := 8; -- data width
OUT_WIDTH_g : natural := 8; -- data width
ROUNDING_TYPE_g : string := "TRUNCATE_LOW"
);
port (
clk : in std_logic;
reset : in std_logic;
enable : in std_logic; -- global clock enable
datain : in std_logic_vector(IN_WIDTH_g-1 downto 0);
dataout : out std_logic_vector(OUT_WIDTH_g-1 downto 0));
end component auk_dspip_roundsat_fir_91;
component auk_dspip_avalon_streaming_block_source_fir_91 is
generic (
MAX_BLK_g : natural;
DATAWIDTH_g : natural);
port (
clk : in std_logic;
reset : in std_logic;
in_blk : in std_logic_vector(log2_ceil(MAX_BLK_g) downto 0);
in_valid : in std_logic;
source_stall : out std_logic;
in_data : in std_logic_vector(DATAWIDTH_g - 1 downto 0);
source_valid : out std_logic;
source_ready : in std_logic;
source_sop : out std_logic;
source_eop : out std_logic;
source_data : out std_logic_vector(DATAWIDTH_g - 1 downto 0));
end component auk_dspip_avalon_streaming_block_source_fir_91;
component auk_dspip_avalon_streaming_block_sink_fir_91 is
generic (
MAX_BLK_g : natural;
STALL_g : natural;
DATAWIDTH_g : natural;
-- this generic is specific for the FFT.
NUM_STAGES_g : natural);
port (
clk : in std_logic;
reset : in std_logic;
in_blk : in std_logic_vector(log2_ceil(MAX_BLK_g) downto 0);
in_sop : in std_logic;
in_eop : in std_logic;
in_inverse : in std_logic;
sink_valid : in std_logic;
sink_ready : out std_logic;
source_stall : in std_logic;
in_data : in std_logic_vector(DATAWIDTH_g - 1 downto 0);
processing : in std_logic;
in_error : in std_logic_vector(1 downto 0);
out_error : out std_logic_vector(1 downto 0);
out_valid : out std_logic;
out_sop : out std_logic;
out_eop : out std_logic;
out_data : out std_logic_vector(DATAWIDTH_g - 1 downto 0);
curr_blk : out std_logic_vector(log2_ceil(MAX_BLK_g) downto 0);
-- these are specific to the FFT, no effort has been made to optimize!
curr_pwr_2 : out std_logic;
curr_inverse : out std_logic;
curr_input_sel : out std_logic_vector(NUM_STAGES_g - 1 downto 0));
end component auk_dspip_avalon_streaming_block_sink_fir_91;
end package auk_dspip_lib_pkg_hpfir;
| gpl-2.0 | 838a238270a5fbf837fdcfe07030dc9b | 0.561105 | 3.506156 | false | false | false | false |
DougFirErickson/parallella-hw | fpga/ip/xilinx/memory_dp_48x4096/blk_mem_gen_v8_2/hdl/blk_mem_gen_v8_2_pkg.vhd | 8 | 127,668 | `protect begin_protected
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`protect end_protected
| gpl-3.0 | a899d22101ac9aeaafeb2ea0dd828121 | 0.95381 | 1.810688 | false | false | false | false |
dummylink/plnk_fpga-stack | Examples/xilinx_microblaze/avnet_lx9/pcores/plb_powerlink_v1_00_a/hdl/vhdl/lib/slow2fastSync.vhd | 5 | 3,843 | -------------------------------------------------------------------------------
--
-- Title : slow2fastSync
-- Design : POWERLINK
--
-------------------------------------------------------------------------------
--
-- File : C:\my_designs\POWERLINK\src\lib\slow2fastSync.vhd
-- Generated : Tue Aug 9 16:38:41 2011
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2011
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- 2011-08-09 V0.01 zelenkaj First version
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY slow2fastSync IS
GENERIC (
doSync_g : BOOLEAN := TRUE
);
PORT (
dataSrc : IN STD_LOGIC;
dataDst : OUT STD_LOGIC;
clkSrc : IN STD_LOGIC;
rstSrc : IN STD_LOGIC;
clkDst : IN STD_LOGIC;
rstDst : IN STD_LOGIC
);
END ENTITY slow2fastSync;
ARCHITECTURE rtl OF slow2fastSync IS
signal toggle, toggleSync, pulse, dataDst_s : std_logic;
begin
dataDst <= dataDst_s when doSync_g = TRUE else dataSrc;
genSync : IF doSync_g = TRUE GENERATE
firstEdgeDet : entity work.edgeDet
port map (
din => dataSrc,
rising => pulse,
falling => open,
any => open,
clk => clkSrc,
rst => rstSrc
);
process(clkSrc, rstSrc)
begin
if rstSrc = '1' then
toggle <= '0';
elsif clkSrc = '1' and clkSrc'event then
if pulse = '1' then
toggle <= not toggle;
end if;
end if;
end process;
sync : entity work.sync
port map (
din => toggle,
dout => toggleSync,
clk => clkDst,
rst => rstDst
);
secondEdgeDet : entity work.edgeDet
port map (
din => toggleSync,
rising => open,
falling => open,
any => dataDst_s,
clk => clkDst,
rst => rstDst
);
END GENERATE;
END ARCHITECTURE rtl; | gpl-2.0 | 7c0980090b0ebbac5522044d00695ff2 | 0.572209 | 3.905488 | false | false | false | false |
estadofinito/biblioteca-vhdl | todos-los-archivos/clk0_25.vhd | 2 | 1,365 | ----------------------------------------------------------------------------------
-- Compañía: Estado Finito
-- Ingeniero: Carlos Ramos
--
-- Fecha de creación: 2014/04/13 08:27:57
-- Nombre del módulo: clk0_25Hz - Behavioral
-- Comentarios adicionales:
-- Implementación mediante aproximación, a caso con escala ajustada par (de 200000000 a 200000000).
-- La frecuencia fue ajustada al entero más próximo.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity clk0_25Hz is
Port (
clk : in STD_LOGIC; -- Reloj de entrada de 50000000Hz.
reset : in STD_LOGIC;
clk_out : out STD_LOGIC -- Reloj de salida de 0.25Hz.
);
end clk0_25Hz;
architecture Behavioral of clk0_25Hz is
signal temporal: STD_LOGIC;
signal contador: integer range 0 to 99999999 := 0;
begin
divisor_frecuencia: process (clk, reset) begin
if (reset = '1') then
temporal <= '0';
contador <= 0;
elsif rising_edge(clk) then
if (contador = 99999999) then
temporal <= NOT(temporal);
contador <= 0;
else
contador <= contador + 1;
end if;
end if;
end process;
clk_out <= temporal;
end Behavioral; | lgpl-2.1 | f361d213dd075fe4b42193d346821b38 | 0.517216 | 4.038462 | false | false | false | false |
rflamino/StellaBlue | core/A6500/src/Types.vhd | 1 | 3,647 | -- A6500 - 6502 CPU and variants
-- Copyright 2006, 2010 Retromaster
--
-- This file is part of A2601.
--
-- A2601 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License,
-- or any later version.
--
-- A2601 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with A2601. If not, see <http://www.gnu.org/licenses/>.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package types is
-- ALU
constant A: natural := 0;
constant X: natural := 1;
constant Y: natural := 2;
constant S: natural := 3;
constant PCL: natural := 4;
constant PCH: natural := 5;
constant ADL: natural := 6;
constant DL: natural := 7;
constant P: natural := 8;
constant ADH: natural := 8;
-- PC control
constant PC_MEM: natural := 0;
constant PC_ALU: natural := 1;
constant PC_INC: natural := 2;
-- Data Out control
constant DO_ALU: natural := 0;
constant DO_PCH: natural := 1;
constant DO_PCL: natural := 2;
constant DO_P: natural := 3;
-- Address Bus
constant PCHL: natural := 0;
constant ADHDL: natural := 1;
constant ADHL: natural := 2;
constant DLADL: natural := 3;
constant INTVEC: natural := 4;
constant STAD: natural := 5;
-- Flags
constant C: natural := 0;
constant Z: natural := 1;
constant I: natural := 2;
constant D: natural := 3;
constant B: natural := 4;
constant V: natural := 6;
constant N: natural := 7;
-- Flag controls
constant FLG_ALU: natural := 0;
constant FLG_MEM: natural := 1;
constant FLG_ZERO: natural := 2;
constant FLG_ONE: natural := 3;
subtype datapath_src is bit_vector(8 downto 0);
subtype datapath_dst is bit_vector(8 downto 0);
subtype datapath_adr is bit_vector(5 downto 0);
subtype datapath_pc_ctrl is bit_vector(2 downto 0);
subtype datapath_do_ctrl is bit_vector(3 downto 0);
subtype datapath_flg_ctrl is bit_vector(3 downto 0);
subtype alu_fn is std_logic_vector(3 downto 0);
constant flg_ctrl_alu: datapath_flg_ctrl := "0001";
constant flg_ctrl_mem: datapath_flg_ctrl := "0010";
constant flg_ctrl_zero: datapath_flg_ctrl := "0100";
constant flg_ctrl_one: datapath_flg_ctrl := "1000";
constant do_ctrl_alu: datapath_flg_ctrl := "0001";
constant do_ctrl_pch: datapath_flg_ctrl := "0010";
constant do_ctrl_pcl: datapath_flg_ctrl := "0100";
constant do_ctrl_p: datapath_flg_ctrl := "1000";
constant adr_pchl: datapath_adr := "000001";
constant adr_adhdl: datapath_adr := "000010";
constant adr_adhl: datapath_adr := "000100";
constant adr_dladl: datapath_adr := "001000";
constant adr_intvec: datapath_adr := "010000";
constant adr_stad: datapath_adr := "100000";
constant src_a: datapath_src := "000000001";
constant src_x: datapath_src := "000000010";
constant src_y: datapath_src := "000000100";
constant src_s: datapath_src := "000001000";
constant src_pcl: datapath_src := "000010000";
constant src_pch: datapath_src := "000100000";
constant src_adl: datapath_src := "001000000";
constant src_dl: datapath_src := "010000000";
constant src_p: datapath_src := "100000000";
end;
| mit | 6c76a6753a2ccbfbabbed29361704f45 | 0.654236 | 3.565005 | false | false | false | false |
hgunicamp/Mips8B | src_test/test_Mips_Processor.vhdl | 1 | 4,825 | -- Teste geral para a estrutura do Processador Mips8B
Library Ieee;
Use Ieee.Std_Logic_1164.all;
Use Ieee.Numeric_Std.all;
Entity test_processor is
End Entity test_processor;
Architecture test_general of test_processor is
Component Mips8B_Core is
Port(Reset_n: In Std_Logic;
Clock: In Std_Logic;
MAddr: Out Std_Logic_Vector(7 downto 0);
MCmd: Out Std_Logic_Vector(1 downto 0);
MData: Out Std_Logic_Vector(7 downto 0);
SData: In Std_Logic_Vector(7 downto 0);
SCmdAccept: In Std_Logic);
End Component Mips8B_Core;
Type Memory_Array is Array(Natural Range <>) of Std_Logic_Vector(7 downto 0);
Use Work.MIPS8B_Base.ocpIDLE_little;
Use Work.MIPS8B_Base.ocpWR_little;
Use Work.MIPS8B_Base.ocpRD_little;
Use Work.MIPS8B_Base.ocpNULL_little;
Use Work.MIPS8B_Base.ocpDVA_little;
Signal Reset_n: Std_Logic;
Signal Clock: Std_Logic := '0';
Signal Clock_Mem: Std_Logic := '0';
Signal MAddr: Std_Logic_Vector(7 downto 0);
Signal MCmd: Std_Logic_Vector(1 downto 0);
Signal MData: Std_Logic_Vector(7 downto 0);
Signal SData: Std_Logic_Vector(7 downto 0);
Signal SCmdAccept: Std_Logic;
Begin
Reset_n <= '1', '0' after 20 ns, '1' after 40 ns;
Clock <= not Clock after 10 ns;
Clock_Mem <= not Clock_Mem after 15 ns;
Memory: Process
Variable int_SCmdAccept: Std_Logic;
Variable address: Unsigned(7 downto 0);
Variable mem_int: Memory_Array(0 to 255) := (
"00100000", "00000001", "00000000", "11001000",
"00100000", "00000010", "00000000", "10001001",
"00100000", "00000011", "00000000", "11001101",
"10100000", "00100010", "00000000", "00000000",
"00100000", "00100001", "00000000", "00000001",
"00100000", "01000010", "00000000", "11101111",
"00010000", "01100001", "00000000", "00000010",
"00010000", "00000000", "00000000", "11111100",
"00000000", "00000000", "00001000", "00100101",
"00100000", "00000110", "00000000", "11001000",
"00100000", "11000111", "00000000", "00000001",
"00100000", "00000101", "00000000", "11001101",
"00010000", "10100111", "00000000", "00001011",
"10000000", "11000011", "00000000", "00000000",
"10000000", "11100100", "00000000", "00000000",
"00000000", "10000011", "00010000", "00101010",
"00010000", "01000000", "00000000", "00000100",
"00100000", "00100001", "00000000", "00000001",
"10100000", "11000100", "00000000", "00000000",
"10100000", "11100011", "00000000", "00000000",
"00000000", "11100000", "00110000", "00100000",
"00100000", "11100111", "00000000", "00000001",
"00010000", "00000000", "00000000", "11110110",
"00010000", "00000001", "00000000", "00000010",
"00010000", "00000000", "00000000", "11110000",
"00100000", "00000011", "00000000", "11001101",
"00100000", "00000001", "00000000", "11001000",
"10000000", "00100010", "00000000", "00000000",
"10100000", "00100010", "00000000", "00000000",
"00100000", "00100001", "00000000", "00000001",
"00010000", "01100001", "00000000", "11111100",
"00010000", "00000000", "00000000", "11111100",
Others => "00000000");
Begin
Wait Until Clock_Mem'Event and Clock_Mem='1';
Case MCmd is
When ocpWR_little =>
If int_SCmdAccept = ocpNULL_little then
int_SCmdAccept := ocpDVA_little;
address := Unsigned(MAddr);
mem_int(to_integer(address)) := MData;
Else
int_SCmdAccept := ocpNULL_little;
End If;
SData <= "ZZZZZZZZ";
When ocpRD_little =>
If int_SCmdAccept = ocpNULL_little then
int_SCmdAccept := ocpDVA_little;
address := Unsigned(MAddr);
SData <= mem_int(to_integer(address));
Else
int_SCmdAccept := ocpNULL_little;
End If;
When Others =>
int_SCmdAccept := ocpNULL_little;
SData <= "ZZZZZZZZ";
End Case;
SCmdAccept <= int_SCmdAccept;
End Process Memory;
DUV: Mips8B_Core
Port Map( Reset_n => Reset_n,
Clock => Clock,
MAddr => MAddr,
MCmd => MCmd,
MData => MData,
SData => SData,
SCmdAccept => SCmdAccept);
End Architecture test_general;
Configuration general_test of test_processor is
For test_general
For DUV: Mips8B_Core Use Configuration Work.Mips8B_Core_struct_conf;
End For;
End For;
End Configuration general_test;
| unlicense | ca92a0e5dbe5ea1ab3ee8d3955e6523f | 0.576373 | 3.751944 | false | true | false | false |
rflamino/StellaBlue | core/TIA/src/Bench.vhd | 1 | 24,194 | -- TV Interface Adapter (TIA)
-- Copyright 2006, 2010 Retromaster
--
-- This file is part of A2601.
--
-- A2601 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License,
-- or any later version.
--
-- A2601 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with A2601. If not, see <http://www.gnu.org/licenses/>.
--
library std;
use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_signed.all;
use work.TIA_common.all;
entity bench is
end bench;
architecture bench of bench is
component TIA is
port(clk: in std_logic;
rst: in std_logic;
cs: in std_logic;
r: in std_logic;
a: in std_logic_vector(5 downto 0);
d: inout std_logic_vector(7 downto 0);
colu: out std_logic_vector(6 downto 0);
csyn: out std_logic;
hsyn: out std_logic;
vsyn: out std_logic;
rdy: out std_logic;
ph0: out std_logic;
inpt4: in std_logic;
inpt5: in std_logic
);
end component;
signal clk: std_logic;
signal rst: std_logic;
signal cs: std_logic;
signal r: std_logic;
signal a: std_logic_vector(5 downto 0);
signal d: std_logic_vector(7 downto 0);
signal colu: std_logic_vector(6 downto 0);
signal csyn: std_logic;
signal hsyn: std_logic;
signal vsyn: std_logic;
signal rdy: std_logic;
signal ph0: std_logic;
signal inpt4: std_logic;
signal inpt5: std_logic;
constant clk_period: time := 40 ns;
constant ph0_period: time := clk_period * 3;
shared variable pf_grp: std_logic_vector(19 downto 0);
shared variable p0_grp: std_logic_vector(7 downto 0);
shared variable p1_grp: std_logic_vector(7 downto 0);
shared variable bk_colu: std_logic_vector(6 downto 0);
shared variable pf_colu: std_logic_vector(6 downto 0);
shared variable p0_colu: std_logic_vector(6 downto 0);
shared variable p1_colu: std_logic_vector(6 downto 0);
shared variable p0_nusiz: std_logic_vector(2 downto 0);
shared variable p1_nusiz: std_logic_vector(2 downto 0);
shared variable p0_reflect: std_logic;
shared variable p1_reflect: std_logic;
shared variable m0_siz: std_logic_vector(1 downto 0);
shared variable m1_siz: std_logic_vector(1 downto 0);
shared variable m0_en: std_logic;
shared variable m1_en: std_logic;
shared variable bl_siz: std_logic_vector(1 downto 0);
shared variable bl_en: std_logic;
shared variable pf_reflect: std_logic;
shared variable pf_score: std_logic;
shared variable pf_priority: std_logic;
shared variable p0_pos: integer;
shared variable p1_pos: integer;
shared variable m0_pos: integer;
shared variable m1_pos: integer;
shared variable bl_pos: integer;
shared variable p0_pos_new: integer;
shared variable p1_pos_new: integer;
shared variable m0_pos_new: integer;
shared variable m1_pos_new: integer;
shared variable bl_pos_new: integer;
procedure print_msg(
constant msg: in string;
constant val: in std_logic_vector(7 downto 0)) is
variable l: line;
begin
write(l, msg);
write(l, ": ");
hwrite(l, val);
writeline(output, l);
end print_msg;
procedure status_report(
constant msg: in string) is
variable l: line;
begin
write(l, msg);
writeline(output, l);
end status_report;
procedure setup_pf(
signal r: out std_logic;
signal d: out std_logic_vector(7 downto 0);
signal a: out std_logic_vector(5 downto 0);
constant reflect: std_logic;
constant score: std_logic;
constant priority: std_logic;
constant grp: in std_logic_vector(19 downto 0);
constant pfcolu: in std_logic_vector(6 downto 0);
constant bkcolu: in std_logic_vector(6 downto 0)) is
begin
r <= '0';
a <= A_COLUPF;
d(7 downto 1) <= pfcolu;
wait for ph0_period;
pf_colu := pfcolu;
a <= A_COLUBK;
d(7 downto 1) <= bkcolu;
wait for ph0_period;
bk_colu := bkcolu;
a <= A_PF0;
d(7 downto 4) <= grp(3 downto 0);
wait for ph0_period;
a <= A_PF1;
d <= grp(11 downto 4);
wait for ph0_period;
a <= A_PF2;
d <= grp(19 downto 12);
wait for ph0_period;
pf_grp := grp;
a <= A_CTRLPF;
d <= "00" & bl_siz & "0" & priority & score & reflect;
wait for ph0_period;
pf_reflect := reflect;
pf_score := score;
pf_priority := priority;
end procedure setup_pf;
procedure setup_pm0(
signal r: out std_logic;
signal d: out std_logic_vector(7 downto 0);
signal a: out std_logic_vector(5 downto 0);
constant men: in std_logic;
constant reflect: in std_logic;
constant nusiz: in std_logic_vector(2 downto 0);
constant msiz: in std_logic_vector(1 downto 0);
constant grp: in std_logic_vector(7 downto 0);
constant colu: in std_logic_vector(6 downto 0)) is
begin
r <= '0';
a <= A_COLUP0;
d(7 downto 1) <= colu;
wait for ph0_period;
p0_colu := colu;
a <= A_GRP0;
d <= grp;
wait for ph0_period;
p0_grp := grp;
a <= A_VDELP0;
d(0) <= '0';
wait for ph0_period;
a <= A_REFP0;
d <= "0000" & reflect & "000";
wait for ph0_period;
p0_reflect := reflect;
a <= A_NUSIZ0;
d <= "00" & msiz & "0" & nusiz;
wait for ph0_period;
p0_nusiz := nusiz;
m0_siz := msiz;
a <= A_ENAM0;
d(1) <= men;
wait for ph0_period;
m0_en := men;
end procedure setup_pm0;
procedure setup_pm1(
signal r: out std_logic;
signal d: out std_logic_vector(7 downto 0);
signal a: out std_logic_vector(5 downto 0);
constant men: in std_logic;
constant reflect: in std_logic;
constant nusiz: in std_logic_vector(2 downto 0);
constant msiz: in std_logic_vector(1 downto 0);
constant grp: in std_logic_vector(7 downto 0);
constant colu: in std_logic_vector(6 downto 0)) is
begin
r <= '0';
a <= A_COLUP1;
d(7 downto 1) <= colu;
wait for ph0_period;
p1_colu := colu;
a <= A_GRP1;
d <= grp;
wait for ph0_period;
p1_grp := grp;
a <= A_VDELP1;
d(0) <= '0';
wait for ph0_period;
a <= A_REFP1;
d <= "0000" & reflect & "000";
wait for ph0_period;
p1_reflect := reflect;
a <= A_NUSIZ1;
d <= "00" & msiz & "0" & nusiz;
wait for ph0_period;
p1_nusiz := nusiz;
m1_siz := msiz;
a <= A_ENAM1;
d(1) <= men;
wait for ph0_period;
m1_en := men;
end procedure setup_pm1;
procedure setup_bl(
signal r: out std_logic;
signal d: out std_logic_vector(7 downto 0);
signal a: out std_logic_vector(5 downto 0);
constant siz: in std_logic_vector(1 downto 0);
constant enable: in std_logic) is
begin
r <= '0';
a <= A_ENABL;
d(1) <= enable;
wait for ph0_period;
a <= A_CTRLPF;
d <= "00" & siz & "0" & pf_priority & pf_score & pf_reflect;
wait for ph0_period;
bl_siz := siz;
end procedure setup_bl;
procedure setpos_p0(
constant pos: integer) is
begin
p0_pos_new := pos;
end procedure setpos_p0;
procedure setpos_p1(
constant pos: integer) is
begin
p1_pos_new := pos;
end procedure setpos_p1;
procedure setpos_m0(
constant pos: integer) is
begin
m0_pos_new := pos;
end procedure setpos_m0;
procedure setpos_m1(
constant pos: integer) is
begin
m1_pos_new := pos;
end procedure setpos_m1;
procedure wait_hblank(
signal r: out std_logic;
signal a: out std_logic_vector(5 downto 0)) is
begin
r <= '0';
a <= A_WSYNC;
wait for ph0_period;
while rdy = '0' loop
wait for clk_period;
end loop;
end procedure wait_hblank;
function get_pl_pix_adr(
constant scan: integer;
constant pos: integer;
constant nusiz: in std_logic_vector(2 downto 0);
constant reflect: in std_logic)
return integer is
variable result: integer;
begin
result := scan - (pos + 2);
if (nusiz = "101") then
if (result >= 0) then
result := result / 2;
end if;
elsif (nusiz = "111") then
if (result >= 0) then
result := result / 4;
end if;
end if;
if (result >= 0) and (result <= 7) then
if (reflect = '0') then
return 7 - result;
else
return result;
end if;
end if;
if (nusiz = "001") or (nusiz = "011") then
result := scan - (pos + 18);
elsif (nusiz = "010") or (nusiz = "110") then
result := scan - (pos + 35);
elsif (nusiz = "100") then
result := scan - (pos + 68);
end if;
if (result >= 0) and (result <= 7) then
if (reflect = '0') then
return 7 - result;
else
return result;
end if;
end if;
if (nusiz = "011") then
result := scan - (pos + 35);
elsif (nusiz = "110") then
result := scan - (pos + 68);
end if;
if (result >= 0) and (result <= 7) then
if (reflect = '0') then
return 7 - result;
else
return result;
end if;
end if;
return -1;
end function get_pl_pix_adr;
function get_mi_pix_adr(
constant scan: integer;
constant pos: integer;
constant nusiz: in std_logic_vector(2 downto 0);
constant siz: in std_logic_vector(1 downto 0))
return integer is
variable result: integer;
begin
result := scan - (pos + 1);
if (result >= 0) then
case siz is
when "01" => result := result / 2;
when "10" => result := result / 4;
when "11" => result := result / 8;
when others => null;
end case;
end if;
if (result = 0) then
return result;
end if;
if (nusiz = "001") or (nusiz = "011") then
result := scan - (pos + 17);
elsif (nusiz = "010") or (nusiz = "110") then
result := scan - (pos + 34);
elsif (nusiz = "100") then
result := scan - (pos + 67);
else
return -1;
end if;
if (result >= 0) then
case siz is
when "01" => result := result / 2;
when "10" => result := result / 4;
when "11" => result := result / 8;
when others => null;
end case;
end if;
if (result = 0) then
return result;
end if;
if (nusiz = "011") then
result := scan - (pos + 34);
elsif (nusiz = "110") then
result := scan - (pos + 67);
else
return -1;
end if;
if (result >= 0) then
case siz is
when "01" => result := result / 2;
when "10" => result := result / 4;
when "11" => result := result / 8;
when others => null;
end case;
end if;
if (result = 0) then
return result;
end if;
return -1;
end function get_mi_pix_adr;
function get_bl_pix_adr(
constant scan: integer;
constant pos: integer;
constant siz: in std_logic_vector(1 downto 0))
return integer is
variable result: integer;
begin
result := scan - (pos + 1);
if (result >= 0) then
case siz is
when "01" => result := result / 2;
when "10" => result := result / 4;
when "11" => result := result / 8;
when others => null;
end case;
end if;
if (result = 0) then
return result;
end if;
return -1;
end function get_bl_pix_adr;
function get_pf_adr(
constant scan: integer;
constant reflect: std_logic)
return integer is
variable result: integer;
begin
result := scan / 4;
if (result >= 20) then
result := result - 20;
if (reflect = '1') then
result := 19 - result;
end if;
end if;
if (result >= 4) and (result < 12) then
result := (11 - result) + 4;
end if;
return result;
end function get_pf_adr;
procedure test_line(
signal r: out std_logic;
signal cs: out std_logic;
signal a: out std_logic_vector(5 downto 0)) is
variable i: integer;
variable j: integer;
variable ex_colu: std_logic_vector(6 downto 0);
variable p0_adr: integer;
variable p1_adr: integer;
variable m0_adr: integer;
variable m1_adr: integer;
variable pf_adr: integer;
variable bl_adr: integer;
begin
r <= '0';
cs <= '0';
for i in 2 to 68 loop
assert colu = "000000" report "HBLANK failed.";
wait for clk_period;
end loop;
for i in 0 to 159 loop
p0_adr := get_pl_pix_adr(i, p0_pos, p0_nusiz, p0_reflect);
p1_adr := get_pl_pix_adr(i, p1_pos, p1_nusiz, p1_reflect);
m0_adr := get_mi_pix_adr(i, m0_pos, p0_nusiz, m0_siz);
m1_adr := get_mi_pix_adr(i, m1_pos, p1_nusiz, m1_siz);
bl_adr := get_bl_pix_adr(i, bl_pos, bl_siz);
pf_adr := get_pf_adr(i, pf_reflect);
ex_colu := bk_colu;
if (pf_priority = '0') then
if (pf_grp(pf_adr) = '1') or ((bl_adr >= 0) and (bl_en = '1')) then
ex_colu := pf_colu;
end if;
end if;
if (p1_adr >= 0) then
if (p1_grp(p1_adr) = '1') then
ex_colu := p1_colu;
end if;
end if;
if (m1_adr >= 0) and (m1_en = '1') then
ex_colu := p1_colu;
end if;
if (p0_adr >= 0) then
if (p0_grp(p0_adr) = '1') then
ex_colu := p0_colu;
end if;
end if;
if (m0_adr >= 0) and (m0_en = '1') then
ex_colu := p0_colu;
end if;
if (pf_priority = '1') then
if (pf_grp(pf_adr) = '1') or ((bl_adr >= 0) and (bl_en = '1')) then
ex_colu := pf_colu;
end if;
end if;
assert (ex_colu = colu) report "Pixel output failed.";
if not (ex_colu = colu) then
print_msg("Expecting", "0" & ex_colu);
print_msg("Found", "0" & colu);
--print_msg("pf_adr", conv_std_logic_vector(pf_adr, 8));
print_msg("p0_adr", conv_std_logic_vector(p0_adr, 8));
--print_msg("m0_adr", conv_std_logic_vector(m0_adr, 8));
end if;
if (i = p0_pos_new) and not (p0_pos = p0_pos_new) then
cs <= '1';
j := 3;
a <= A_RESP0;
p0_pos := p0_pos_new;
elsif (i = p1_pos_new) and not (p1_pos = p1_pos_new) then
cs <= '1';
j := 3;
a <= A_RESP1;
p1_pos := p1_pos_new;
elsif (i = m0_pos_new) and not (m0_pos = m0_pos_new) then
cs <= '1';
j := 3;
a <= A_RESM0;
m0_pos := m0_pos_new;
elsif (i = m1_pos_new) and not (m1_pos = m1_pos_new) then
cs <= '1';
j := 3;
a <= A_RESM1;
m1_pos := m1_pos_new;
elsif (i = bl_pos_new) and not (bl_pos = bl_pos_new) then
cs <= '1';
j := 3;
a <= A_RESBL;
bl_pos := bl_pos_new;
end if;
if (j > 0) then
j := j - 1;
wait for clk_period;
else
wait for clk_period / 2;
cs <= '0';
wait for clk_period / 2;
end if;
end loop;
cs <= '1';
end procedure test_line;
procedure test_pm(
signal r: out std_logic;
signal cs: out std_logic;
signal d: out std_logic_vector(7 downto 0);
signal a: out std_logic_vector(5 downto 0)) is
variable i, j, k, l, m: integer;
variable nusiz: std_logic_vector(2 downto 0);
variable reflect: std_logic;
variable msiz: std_logic_vector(1 downto 0);
variable men: std_logic;
begin
for m in 0 to 1 loop
for i in 0 to 7 loop
for j in 0 to 1 loop
for k in 0 to 1 loop
for l in 0 to 3 loop
reflect := conv_std_logic_vector(j, 1)(0);
nusiz := conv_std_logic_vector(i, 3);
men := conv_std_logic_vector(k, 1)(0);
msiz := conv_std_logic_vector(l, 2);
-- print_msg("p0_nusiz", "00000" & nusiz);
-- print_msg("p0_reflect", "0000000" & reflect);
-- print_msg("m0_siz", "000000" & msiz);
-- print_msg("m0_en", "0000000" & men);
if (m = 0) then
setup_pm0(r, d, a, men, reflect, nusiz, msiz, "10110110", "1010111");
else
setup_pm1(r, d, a, men, reflect, nusiz, msiz, "11100011", "0101000");
end if;
wait_hblank(r, a);
test_line(r, cs, a);
end loop;
end loop;
end loop;
end loop;
end loop;
end procedure test_pm;
procedure test_hmove(
signal r: out std_logic;
signal cs: out std_logic;
signal d: out std_logic_vector(7 downto 0);
signal a: out std_logic_vector(5 downto 0)) is
variable p0_hmove: std_logic_vector(3 downto 0);
variable p1_hmove: std_logic_vector(3 downto 0);
variable m0_hmove: std_logic_vector(3 downto 0);
variable m1_hmove: std_logic_vector(3 downto 0);
variable bl_hmove: std_logic_vector(3 downto 0);
begin
p0_hmove := "0011";
p1_hmove := "0000";
m0_hmove := "0000";
m1_hmove := "0000";
bl_hmove := "0000";
r <= '0';
a <= A_HMP0;
d <= p0_hmove & "0000";
wait for ph0_period;
a <= A_HMP1;
d <= p1_hmove & "0000";
wait for ph0_period;
a <= A_HMM0;
d <= m0_hmove & "0000";
wait for ph0_period;
a <= A_HMM1;
d <= m1_hmove & "0000";
wait for ph0_period;
a <= A_HMBL;
d <= bl_hmove & "0000";
wait for ph0_period;
wait_hblank(r, a);
a <= A_HMOVE;
wait for ph0_period;
p0_pos := p0_pos + conv_integer(p0_hmove);
p1_pos := p1_pos + conv_integer(p1_hmove);
m0_pos := m0_pos + conv_integer(m0_hmove);
m1_pos := m1_pos + conv_integer(m1_hmove);
bl_pos := bl_pos + conv_integer(bl_hmove);
p0_pos_new := p0_pos;
p1_pos_new := p1_pos;
m0_pos_new := m0_pos;
m1_pos_new := m1_pos;
bl_pos_new := bl_pos;
wait_hblank(r, a);
test_line(r, cs, a);
end procedure test_hmove;
procedure init_tia(
signal rst: out std_logic) is
begin
rst <= '1';
wait for 4 * clk_period;
rst <= '0';
p0_pos := 0;
p1_pos := 0;
m0_pos := 0;
m1_pos := 0;
bl_pos := 0;
p0_pos_new := 0;
p1_pos_new := 0;
m0_pos_new := 0;
m1_pos_new := 0;
bl_pos_new := 0;
bl_en := '0';
end procedure init_tia;
begin
test_TIA: TIA port map(clk, rst, cs, r, a, d, colu, csyn, hsyn, vsyn, rdy, ph0, inpt4, inpt5);
inpt4 <= '1';
inpt5 <= '1';
clk_sig: process
begin
clk <= '1';
wait for clk_period / 2;
clk <= '0';
wait for clk_period / 2;
end process;
process
begin
init_tia(rst);
cs <= '1';
setup_pf(r, d, a, '0', '0', '0', "01010101010101010101", "1111111", "0000000");
setpos_p0(20);
setpos_m0(5);
setpos_p1(40);
setpos_m1(15);
wait_hblank(r, a);
test_line(r, cs, a);
setup_pf(r, d, a, '1', '0', '0', "01010101010101010101", "1111111", "0000000");
wait_hblank(r, a);
test_line(r, cs, a);
status_report("PF Test: Done.");
test_pm(r, cs, d, a);
status_report("PM Test: Done.");
setup_pm0(r, d, a, '0', '0', "000", "00", "10110110", "1010111");
test_hmove(r, cs, d, a);
status_report("HMOVE Test: Done.");
wait;
end process;
end bench;
| mit | c1caa0f2f7923d7a495d0b43c724f752 | 0.450732 | 3.765603 | false | false | false | false |
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| gpl-3.0 | f2465ff5423ba1b1eb85a5b57b83ace7 | 0.948817 | 1.830625 | false | false | false | false |
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| gpl-3.0 | 8644d0fb7c2fbac618e4a54b77cf4ec3 | 0.94989 | 1.837598 | false | false | false | false |
rflamino/StellaBlue | core/A6500/src/cpu65xx_fast.vhd | 2 | 57,279 | -- -----------------------------------------------------------------------
--
-- FPGA 64
--
-- A fully functional commodore 64 implementation in a single FPGA
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2008 by Peter Wendrich ([email protected])
-- http://www.syntiac.com/fpga64.html
-- -----------------------------------------------------------------------
--
-- Table driven, cycle exact 6502/6510 core
--
-- -----------------------------------------------------------------------
library IEEE;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.ALL;
use ieee.numeric_std.ALL;
-- -----------------------------------------------------------------------
-- Store Zp (3) => fetch, cycle2, cycleEnd
-- Store Zp,x (4) => fetch, cycle2, preWrite, cycleEnd
-- Read Zp,x (4) => fetch, cycle2, cycleRead, cycleRead2
-- Rmw Zp,x (6) => fetch, cycle2, cycleRead, cycleRead2, cycleRmw, cycleEnd
-- Store Abs (4) => fetch, cycle2, cycle3, cycleEnd
-- Store Abs,x (5) => fetch, cycle2, cycle3, preWrite, cycleEnd
-- Rts (6) => fetch, cycle2, cycle3, cycleRead, cycleJump, cycleIncrEnd
-- Rti (6) => fetch, cycle2, stack1, stack2, stack3, cycleJump
-- Jsr (6) => fetch, cycle2, .. cycle5, cycle6, cycleJump
-- Jmp abs (-) => fetch, cycle2, .., cycleJump
-- Jmp (ind) (-) => fetch, cycle2, .., cycleJump
-- Brk / irq (6) => fetch, cycle2, stack2, stack3, stack4
-- -----------------------------------------------------------------------
architecture fast of cpu65xx is
-- Statemachine
type cpuCycles is (
opcodeFetch, -- New opcode is read and registers updated
cycle2,
cycle3,
cyclePreIndirect,
cycleIndirect,
cycleBranchTaken,
cycleBranchPage,
cyclePreRead, -- Cycle before read while doing zeropage indexed addressing.
cycleRead, -- Read cycle
cycleRead2, -- Second read cycle after page-boundary crossing.
cycleRmw, -- Calculate ALU output for read-modify-write instr.
cyclePreWrite, -- Cycle before write when doing indexed addressing.
cycleWrite, -- Write cycle for zeropage or absolute addressing.
cycleStack1,
cycleStack2,
cycleStack3,
cycleStack4,
cycleJump, -- Last cycle of Jsr, Jmp. Next fetch address is target addr.
cycleEnd
);
signal theCpuCycle : cpuCycles;
signal nextCpuCycle : cpuCycles;
signal updateRegisters : boolean;
signal processIrq : std_logic;
signal nmiReg: std_logic;
signal nmiEdge: std_logic;
signal irqReg : std_logic; -- Delay IRQ input with one clock cycle.
signal soReg : std_logic; -- SO pin edge detection
-- Opcode decoding
constant opcUpdateA : integer := 0;
constant opcUpdateX : integer := 1;
constant opcUpdateY : integer := 2;
constant opcUpdateS : integer := 3;
constant opcUpdateN : integer := 4;
constant opcUpdateV : integer := 5;
constant opcUpdateD : integer := 6;
constant opcUpdateI : integer := 7;
constant opcUpdateZ : integer := 8;
constant opcUpdateC : integer := 9;
constant opcSecondByte : integer := 10;
constant opcAbsolute : integer := 11;
constant opcZeroPage : integer := 12;
constant opcIndirect : integer := 13;
constant opcStackAddr : integer := 14; -- Push/Pop address
constant opcStackData : integer := 15; -- Push/Pop status/data
constant opcJump : integer := 16;
constant opcBranch : integer := 17;
constant indexX : integer := 18;
constant indexY : integer := 19;
constant opcStackUp : integer := 20;
constant opcWrite : integer := 21;
constant opcRmw : integer := 22;
constant opcIncrAfter : integer := 23; -- Insert extra cycle to increment PC (RTS)
constant opcRti : integer := 24;
constant opcIRQ : integer := 25;
constant opcInA : integer := 26;
constant opcInE : integer := 27;
constant opcInX : integer := 28;
constant opcInY : integer := 29;
constant opcInS : integer := 30;
constant opcInT : integer := 31;
constant opcInH : integer := 32;
constant opcInClear : integer := 33;
constant aluMode1From : integer := 34;
--
constant aluMode1To : integer := 37;
constant aluMode2From : integer := 38;
--
constant aluMode2To : integer := 40;
--
constant opcInCmp : integer := 41;
constant opcInCpx : integer := 42;
constant opcInCpy : integer := 43;
subtype addrDef is unsigned(0 to 15);
--
-- is Interrupt -----------------+
-- instruction is RTI ----------------+|
-- PC++ on last cycle (RTS) ---------------+||
-- RMW --------------+|||
-- Write -------------+||||
-- Pop/Stack up -------------+|||||
-- Branch ---------+ ||||||
-- Jump ----------+| ||||||
-- Push or Pop data -------+|| ||||||
-- Push or Pop addr ------+||| ||||||
-- Indirect -----+|||| ||||||
-- ZeroPage ----+||||| ||||||
-- Absolute ---+|||||| ||||||
-- PC++ on cycle2 --+||||||| ||||||
-- |AZI||JBXY|WM|||
constant immediate : addrDef := "1000000000000000";
constant implied : addrDef := "0000000000000000";
-- Zero page
constant readZp : addrDef := "1010000000000000";
constant writeZp : addrDef := "1010000000010000";
constant rmwZp : addrDef := "1010000000001000";
-- Zero page indexed
constant readZpX : addrDef := "1010000010000000";
constant writeZpX : addrDef := "1010000010010000";
constant rmwZpX : addrDef := "1010000010001000";
constant readZpY : addrDef := "1010000001000000";
constant writeZpY : addrDef := "1010000001010000";
constant rmwZpY : addrDef := "1010000001001000";
-- Zero page indirect
constant readIndX : addrDef := "1001000010000000";
constant writeIndX : addrDef := "1001000010010000";
constant rmwIndX : addrDef := "1001000010001000";
constant readIndY : addrDef := "1001000001000000";
constant writeIndY : addrDef := "1001000001010000";
constant rmwIndY : addrDef := "1001000001001000";
-- |AZI||JBXY|WM||
-- Absolute
constant readAbs : addrDef := "1100000000000000";
constant writeAbs : addrDef := "1100000000010000";
constant rmwAbs : addrDef := "1100000000001000";
constant readAbsX : addrDef := "1100000010000000";
constant writeAbsX : addrDef := "1100000010010000";
constant rmwAbsX : addrDef := "1100000010001000";
constant readAbsY : addrDef := "1100000001000000";
constant writeAbsY : addrDef := "1100000001010000";
constant rmwAbsY : addrDef := "1100000001001000";
-- PHA PHP
constant push : addrDef := "0000010000000000";
-- PLA PLP
constant pop : addrDef := "0000010000100000";
-- Jumps
constant jsr : addrDef := "1000101000000000";
constant jumpAbs : addrDef := "1000001000000000";
constant jumpInd : addrDef := "1100001000000000";
constant relative : addrDef := "1000000100000000";
-- Specials
constant rts : addrDef := "0000101000100100";
constant rti : addrDef := "0000111000100010";
constant brk : addrDef := "1000111000000001";
-- constant : unsigned(0 to 0) := "0";
constant xxxxxxxx : addrDef := "----------0---00";
-- A = accu
-- E = Accu | 0xEE (for ANE, LXA)
-- X = index X
-- Y = index Y
-- S = Stack pointer
-- H = indexH
--
-- AEXYSTHc
constant aluInA : unsigned(0 to 7) := "10000000";
constant aluInE : unsigned(0 to 7) := "01000000";
constant aluInEXT : unsigned(0 to 7) := "01100100";
constant aluInET : unsigned(0 to 7) := "01000100";
constant aluInX : unsigned(0 to 7) := "00100000";
constant aluInXH : unsigned(0 to 7) := "00100010";
constant aluInY : unsigned(0 to 7) := "00010000";
constant aluInYH : unsigned(0 to 7) := "00010010";
constant aluInS : unsigned(0 to 7) := "00001000";
constant aluInT : unsigned(0 to 7) := "00000100";
constant aluInAX : unsigned(0 to 7) := "10100000";
constant aluInAXH : unsigned(0 to 7) := "10100010";
constant aluInAT : unsigned(0 to 7) := "10000100";
constant aluInXT : unsigned(0 to 7) := "00100100";
constant aluInST : unsigned(0 to 7) := "00001100";
constant aluInSet : unsigned(0 to 7) := "00000000";
constant aluInClr : unsigned(0 to 7) := "00000001";
constant aluInXXX : unsigned(0 to 7) := "--------";
-- Most of the aluModes are just like the opcodes.
-- aluModeInp -> input is output. calculate N and Z
-- aluModeCmp -> Compare for CMP, CPX, CPY
-- aluModeFlg -> input to flags needed for PLP, RTI and CLC, SEC, CLV
-- aluModeInc -> for INC but also INX, INY
-- aluModeDec -> for DEC but also DEX, DEY
subtype aluMode1 is unsigned(0 to 3);
subtype aluMode2 is unsigned(0 to 2);
subtype aluMode is unsigned(0 to 9);
-- Logic/Shift ALU
constant aluModeInp : aluMode1 := "0000";
constant aluModeP : aluMode1 := "0001";
constant aluModeInc : aluMode1 := "0010";
constant aluModeDec : aluMode1 := "0011";
constant aluModeFlg : aluMode1 := "0100";
constant aluModeBit : aluMode1 := "0101";
-- 0110
-- 0111
constant aluModeLsr : aluMode1 := "1000";
constant aluModeRor : aluMode1 := "1001";
constant aluModeAsl : aluMode1 := "1010";
constant aluModeRol : aluMode1 := "1011";
-- 1100
-- 1101
-- 1110
constant aluModeAnc : aluMode1 := "1111";
-- Arithmetic ALU
constant aluModePss : aluMode2 := "000";
constant aluModeCmp : aluMode2 := "001";
constant aluModeAdc : aluMode2 := "010";
constant aluModeSbc : aluMode2 := "011";
constant aluModeAnd : aluMode2 := "100";
constant aluModeOra : aluMode2 := "101";
constant aluModeEor : aluMode2 := "110";
constant aluModeArr : aluMode2 := "111";
constant aluInp : aluMode := aluModeInp & aluModePss & "---";
constant aluP : aluMode := aluModeP & aluModePss & "---";
constant aluInc : aluMode := aluModeInc & aluModePss & "---";
constant aluDec : aluMode := aluModeDec & aluModePss & "---";
constant aluFlg : aluMode := aluModeFlg & aluModePss & "---";
constant aluBit : aluMode := aluModeBit & aluModeAnd & "---";
constant aluRor : aluMode := aluModeRor & aluModePss & "---";
constant aluLsr : aluMode := aluModeLsr & aluModePss & "---";
constant aluRol : aluMode := aluModeRol & aluModePss & "---";
constant aluAsl : aluMode := aluModeAsl & aluModePss & "---";
constant aluCmp : aluMode := aluModeInp & aluModeCmp & "100";
constant aluCpx : aluMode := aluModeInp & aluModeCmp & "010";
constant aluCpy : aluMode := aluModeInp & aluModeCmp & "001";
constant aluAdc : aluMode := aluModeInp & aluModeAdc & "---";
constant aluSbc : aluMode := aluModeInp & aluModeSbc & "---";
constant aluAnd : aluMode := aluModeInp & aluModeAnd & "---";
constant aluOra : aluMode := aluModeInp & aluModeOra & "---";
constant aluEor : aluMode := aluModeInp & aluModeEor & "---";
constant aluSlo : aluMode := aluModeAsl & aluModeOra & "---";
constant aluSre : aluMode := aluModeLsr & aluModeEor & "---";
constant aluRra : aluMode := aluModeRor & aluModeAdc & "---";
constant aluRla : aluMode := aluModeRol & aluModeAnd & "---";
constant aluDcp : aluMode := aluModeDec & aluModeCmp & "100";
constant aluIsc : aluMode := aluModeInc & aluModeSbc & "---";
constant aluAnc : aluMode := aluModeAnc & aluModeAnd & "---";
constant aluArr : aluMode := aluModeRor & aluModeArr & "---";
constant aluSbx : aluMode := aluModeInp & aluModeCmp & "110";
constant aluXXX : aluMode := (others => '-');
-- Stack operations. Push/Pop/None
constant stackInc : unsigned(0 to 0) := "0";
constant stackDec : unsigned(0 to 0) := "1";
constant stackXXX : unsigned(0 to 0) := "-";
subtype decodedBitsDef is unsigned(0 to 43);
type opcodeInfoTableDef is array(0 to 255) of decodedBitsDef;
constant opcodeInfoTable : opcodeInfoTableDef := (
-- +------- Update register A
-- |+------ Update register X
-- ||+----- Update register Y
-- |||+---- Update register S
-- |||| +-- Update Flags
-- |||| |
-- |||| _|__
-- |||| / \
-- AXYS NVDIZC addressing aluInput aluMode
"0000" & "000100" & brk & aluInXXX & aluP, -- 00 BRK
"1000" & "100010" & readIndX & aluInT & aluOra, -- 01 ORA (zp,x)
"----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 02 *** JAM ***
"1000" & "100011" & rmwIndX & aluInT & aluSlo, -- 03 iSLO (zp,x)
"0000" & "000000" & readZp & aluInXXX & aluXXX, -- 04 iNOP zp
"1000" & "100010" & readZp & aluInT & aluOra, -- 05 ORA zp
"0000" & "100011" & rmwZp & aluInT & aluAsl, -- 06 ASL zp
"1000" & "100011" & rmwZp & aluInT & aluSlo, -- 07 iSLO zp
"0000" & "000000" & push & aluInXXX & aluP, -- 08 PHP
"1000" & "100010" & immediate & aluInT & aluOra, -- 09 ORA imm
"1000" & "100011" & implied & aluInA & aluAsl, -- 0A ASL accu
"1000" & "100011" & immediate & aluInT & aluAnc, -- 0B iANC imm
"0000" & "000000" & readAbs & aluInXXX & aluXXX, -- 0C iNOP abs
"1000" & "100010" & readAbs & aluInT & aluOra, -- 0D ORA abs
"0000" & "100011" & rmwAbs & aluInT & aluAsl, -- 0E ASL abs
"1000" & "100011" & rmwAbs & aluInT & aluSlo, -- 0F iSLO abs
"0000" & "000000" & relative & aluInXXX & aluXXX, -- 10 BPL
"1000" & "100010" & readIndY & aluInT & aluOra, -- 11 ORA (zp),y
"----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 12 *** JAM ***
"1000" & "100011" & rmwIndY & aluInT & aluSlo, -- 13 iSLO (zp),y
"0000" & "000000" & readZpX & aluInXXX & aluXXX, -- 14 iNOP zp,x
"1000" & "100010" & readZpX & aluInT & aluOra, -- 15 ORA zp,x
"0000" & "100011" & rmwZpX & aluInT & aluAsl, -- 16 ASL zp,x
"1000" & "100011" & rmwZpX & aluInT & aluSlo, -- 17 iSLO zp,x
"0000" & "000001" & implied & aluInClr & aluFlg, -- 18 CLC
"1000" & "100010" & readAbsY & aluInT & aluOra, -- 19 ORA abs,y
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 1A iNOP implied
"1000" & "100011" & rmwAbsY & aluInT & aluSlo, -- 1B iSLO abs,y
"0000" & "000000" & readAbsX & aluInXXX & aluXXX, -- 1C iNOP abs,x
"1000" & "100010" & readAbsX & aluInT & aluOra, -- 1D ORA abs,x
"0000" & "100011" & rmwAbsX & aluInT & aluAsl, -- 1E ASL abs,x
"1000" & "100011" & rmwAbsX & aluInT & aluSlo, -- 1F iSLO abs,x
-- AXYS NVDIZC addressing aluInput aluMode
"0000" & "000000" & jsr & aluInXXX & aluXXX, -- 20 JSR
"1000" & "100010" & readIndX & aluInT & aluAnd, -- 21 AND (zp,x)
"----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 22 *** JAM ***
"1000" & "100011" & rmwIndX & aluInT & aluRla, -- 23 iRLA (zp,x)
"0000" & "110010" & readZp & aluInT & aluBit, -- 24 BIT zp
"1000" & "100010" & readZp & aluInT & aluAnd, -- 25 AND zp
"0000" & "100011" & rmwZp & aluInT & aluRol, -- 26 ROL zp
"1000" & "100011" & rmwZp & aluInT & aluRla, -- 27 iRLA zp
"0000" & "111111" & pop & aluInT & aluFlg, -- 28 PLP
"1000" & "100010" & immediate & aluInT & aluAnd, -- 29 AND imm
"1000" & "100011" & implied & aluInA & aluRol, -- 2A ROL accu
"1000" & "100011" & immediate & aluInT & aluAnc, -- 2B iANC imm
"0000" & "110010" & readAbs & aluInT & aluBit, -- 2C BIT abs
"1000" & "100010" & readAbs & aluInT & aluAnd, -- 2D AND abs
"0000" & "100011" & rmwAbs & aluInT & aluRol, -- 2E ROL abs
"1000" & "100011" & rmwAbs & aluInT & aluRla, -- 2F iRLA abs
"0000" & "000000" & relative & aluInXXX & aluXXX, -- 30 BMI
"1000" & "100010" & readIndY & aluInT & aluAnd, -- 31 AND (zp),y
"----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 32 *** JAM ***
"1000" & "100011" & rmwIndY & aluInT & aluRla, -- 33 iRLA (zp),y
"0000" & "000000" & readZpX & aluInXXX & aluXXX, -- 34 iNOP zp,x
"1000" & "100010" & readZpX & aluInT & aluAnd, -- 35 AND zp,x
"0000" & "100011" & rmwZpX & aluInT & aluRol, -- 36 ROL zp,x
"1000" & "100011" & rmwZpX & aluInT & aluRla, -- 37 iRLA zp,x
"0000" & "000001" & implied & aluInSet & aluFlg, -- 38 SEC
"1000" & "100010" & readAbsY & aluInT & aluAnd, -- 39 AND abs,y
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 3A iNOP implied
"1000" & "100011" & rmwAbsY & aluInT & aluRla, -- 3B iRLA abs,y
"0000" & "000000" & readAbsX & aluInXXX & aluXXX, -- 3C iNOP abs,x
"1000" & "100010" & readAbsX & aluInT & aluAnd, -- 3D AND abs,x
"0000" & "100011" & rmwAbsX & aluInT & aluRol, -- 3E ROL abs,x
"1000" & "100011" & rmwAbsX & aluInT & aluRla, -- 3F iRLA abs,x
-- AXYS NVDIZC addressing aluInput aluMode
"0000" & "111111" & rti & aluInT & aluFlg, -- 40 RTI
"1000" & "100010" & readIndX & aluInT & aluEor, -- 41 EOR (zp,x)
"----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 42 *** JAM ***
"1000" & "100011" & rmwIndX & aluInT & aluSre, -- 43 iSRE (zp,x)
"0000" & "000000" & readZp & aluInXXX & aluXXX, -- 44 iNOP zp
"1000" & "100010" & readZp & aluInT & aluEor, -- 45 EOR zp
"0000" & "100011" & rmwZp & aluInT & aluLsr, -- 46 LSR zp
"1000" & "100011" & rmwZp & aluInT & aluSre, -- 47 iSRE zp
"0000" & "000000" & push & aluInA & aluInp, -- 48 PHA
"1000" & "100010" & immediate & aluInT & aluEor, -- 49 EOR imm
"1000" & "100011" & implied & aluInA & aluLsr, -- 4A LSR accu
"1000" & "100011" & immediate & aluInAT & aluLsr, -- 4B iALR imm
"0000" & "000000" & jumpAbs & aluInXXX & aluXXX, -- 4C JMP abs
"1000" & "100010" & readAbs & aluInT & aluEor, -- 4D EOR abs
"0000" & "100011" & rmwAbs & aluInT & aluLsr, -- 4E LSR abs
"1000" & "100011" & rmwAbs & aluInT & aluSre, -- 4F iSRE abs
"0000" & "000000" & relative & aluInXXX & aluXXX, -- 50 BVC
"1000" & "100010" & readIndY & aluInT & aluEor, -- 51 EOR (zp),y
"----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 52 *** JAM ***
"1000" & "100011" & rmwIndY & aluInT & aluSre, -- 53 iSRE (zp),y
"0000" & "000000" & readZpX & aluInXXX & aluXXX, -- 54 iNOP zp,x
"1000" & "100010" & readZpX & aluInT & aluEor, -- 55 EOR zp,x
"0000" & "100011" & rmwZpX & aluInT & aluLsr, -- 56 LSR zp,x
"1000" & "100011" & rmwZpX & aluInT & aluSre, -- 57 SRE zp,x
"0000" & "000100" & implied & aluInClr & aluXXX, -- 58 CLI
"1000" & "100010" & readAbsY & aluInT & aluEor, -- 59 EOR abs,y
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 5A iNOP implied
"1000" & "100011" & rmwAbsY & aluInT & aluSre, -- 5B iSRE abs,y
"0000" & "000000" & readAbsX & aluInXXX & aluXXX, -- 5C iNOP abs,x
"1000" & "100010" & readAbsX & aluInT & aluEor, -- 5D EOR abs,x
"0000" & "100011" & rmwAbsX & aluInT & aluLsr, -- 5E LSR abs,x
"1000" & "100011" & rmwAbsX & aluInT & aluSre, -- 5F SRE abs,x
-- AXYS NVDIZC addressing aluInput aluMode
"0000" & "000000" & rts & aluInXXX & aluXXX, -- 60 RTS
"1000" & "110011" & readIndX & aluInT & aluAdc, -- 61 ADC (zp,x)
"----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 62 *** JAM ***
"1000" & "110011" & rmwIndX & aluInT & aluRra, -- 63 iRRA (zp,x)
"0000" & "000000" & readZp & aluInXXX & aluXXX, -- 64 iNOP zp
"1000" & "110011" & readZp & aluInT & aluAdc, -- 65 ADC zp
"0000" & "100011" & rmwZp & aluInT & aluRor, -- 66 ROR zp
"1000" & "110011" & rmwZp & aluInT & aluRra, -- 67 iRRA zp
"1000" & "100010" & pop & aluInT & aluInp, -- 68 PLA
"1000" & "110011" & immediate & aluInT & aluAdc, -- 69 ADC imm
"1000" & "100011" & implied & aluInA & aluRor, -- 6A ROR accu
"1000" & "110011" & immediate & aluInAT & aluArr, -- 6B iARR imm
"0000" & "000000" & jumpInd & aluInXXX & aluXXX, -- 6C JMP indirect
"1000" & "110011" & readAbs & aluInT & aluAdc, -- 6D ADC abs
"0000" & "100011" & rmwAbs & aluInT & aluRor, -- 6E ROR abs
"1000" & "110011" & rmwAbs & aluInT & aluRra, -- 6F iRRA abs
"0000" & "000000" & relative & aluInXXX & aluXXX, -- 70 BVS
"1000" & "110011" & readIndY & aluInT & aluAdc, -- 71 ADC (zp),y
"----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 72 *** JAM ***
"1000" & "110011" & rmwIndY & aluInT & aluRra, -- 73 iRRA (zp),y
"0000" & "000000" & readZpX & aluInXXX & aluXXX, -- 74 iNOP zp,x
"1000" & "110011" & readZpX & aluInT & aluAdc, -- 75 ADC zp,x
"0000" & "100011" & rmwZpX & aluInT & aluRor, -- 76 ROR zp,x
"1000" & "110011" & rmwZpX & aluInT & aluRra, -- 77 iRRA zp,x
"0000" & "000100" & implied & aluInSet & aluXXX, -- 78 SEI
"1000" & "110011" & readAbsY & aluInT & aluAdc, -- 79 ADC abs,y
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 7A iNOP implied
"1000" & "110011" & rmwAbsY & aluInT & aluRra, -- 7B iRRA abs,y
"0000" & "000000" & readAbsX & aluInXXX & aluXXX, -- 7C iNOP abs,x
"1000" & "110011" & readAbsX & aluInT & aluAdc, -- 7D ADC abs,x
"0000" & "100011" & rmwAbsX & aluInT & aluRor, -- 7E ROR abs,x
"1000" & "110011" & rmwAbsX & aluInT & aluRra, -- 7F iRRA abs,x
-- AXYS NVDIZC addressing aluInput aluMode
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- 80 iNOP imm
"0000" & "000000" & writeIndX & aluInA & aluInp, -- 81 STA (zp,x)
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- 82 iNOP imm
"0000" & "000000" & writeIndX & aluInAX & aluInp, -- 83 iSAX (zp,x)
"0000" & "000000" & writeZp & aluInY & aluInp, -- 84 STY zp
"0000" & "000000" & writeZp & aluInA & aluInp, -- 85 STA zp
"0000" & "000000" & writeZp & aluInX & aluInp, -- 86 STX zp
"0000" & "000000" & writeZp & aluInAX & aluInp, -- 87 iSAX zp
"0010" & "100010" & implied & aluInY & aluDec, -- 88 DEY
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- 84 iNOP imm
"1000" & "100010" & implied & aluInX & aluInp, -- 8A TXA
"1000" & "100010" & immediate & aluInEXT & aluInp, -- 8B iANE imm
"0000" & "000000" & writeAbs & aluInY & aluInp, -- 8C STY abs
"0000" & "000000" & writeAbs & aluInA & aluInp, -- 8D STA abs
"0000" & "000000" & writeAbs & aluInX & aluInp, -- 8E STX abs
"0000" & "000000" & writeAbs & aluInAX & aluInp, -- 8F iSAX abs
"0000" & "000000" & relative & aluInXXX & aluXXX, -- 90 BCC
"0000" & "000000" & writeIndY & aluInA & aluInp, -- 91 STA (zp),y
"----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 92 *** JAM ***
"0000" & "000000" & writeIndY & aluInAXH & aluInp, -- 93 iAHX (zp),y
"0000" & "000000" & writeZpX & aluInY & aluInp, -- 94 STY zp,x
"0000" & "000000" & writeZpX & aluInA & aluInp, -- 95 STA zp,x
"0000" & "000000" & writeZpY & aluInX & aluInp, -- 96 STX zp,y
"0000" & "000000" & writeZpY & aluInAX & aluInp, -- 97 iSAX zp,y
"1000" & "100010" & implied & aluInY & aluInp, -- 98 TYA
"0000" & "000000" & writeAbsY & aluInA & aluInp, -- 99 STA abs,y
"0001" & "000000" & implied & aluInX & aluInp, -- 9A TXS
"0001" & "000000" & writeAbsY & aluInAXH & aluInp, -- 9B iSHS abs,y
"0000" & "000000" & writeAbsX & aluInYH & aluInp, -- 9C iSHY abs,x
"0000" & "000000" & writeAbsX & aluInA & aluInp, -- 9D STA abs,x
"0000" & "000000" & writeAbsY & aluInXH & aluInp, -- 9E iSHX abs,y
"0000" & "000000" & writeAbsY & aluInAXH & aluInp, -- 9F iAHX abs,y
-- AXYS NVDIZC addressing aluInput aluMode
"0010" & "100010" & immediate & aluInT & aluInp, -- A0 LDY imm
"1000" & "100010" & readIndX & aluInT & aluInp, -- A1 LDA (zp,x)
"0100" & "100010" & immediate & aluInT & aluInp, -- A2 LDX imm
"1100" & "100010" & readIndX & aluInT & aluInp, -- A3 LAX (zp,x)
"0010" & "100010" & readZp & aluInT & aluInp, -- A4 LDY zp
"1000" & "100010" & readZp & aluInT & aluInp, -- A5 LDA zp
"0100" & "100010" & readZp & aluInT & aluInp, -- A6 LDX zp
"1100" & "100010" & readZp & aluInT & aluInp, -- A7 iLAX zp
"0010" & "100010" & implied & aluInA & aluInp, -- A8 TAY
"1000" & "100010" & immediate & aluInT & aluInp, -- A9 LDA imm
"0100" & "100010" & implied & aluInA & aluInp, -- AA TAX
"1100" & "100010" & immediate & aluInET & aluInp, -- AB iLXA imm
"0010" & "100010" & readAbs & aluInT & aluInp, -- AC LDY abs
"1000" & "100010" & readAbs & aluInT & aluInp, -- AD LDA abs
"0100" & "100010" & readAbs & aluInT & aluInp, -- AE LDX abs
"1100" & "100010" & readAbs & aluInT & aluInp, -- AF iLAX abs
"0000" & "000000" & relative & aluInXXX & aluXXX, -- B0 BCS
"1000" & "100010" & readIndY & aluInT & aluInp, -- B1 LDA (zp),y
"----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- B2 *** JAM ***
"1100" & "100010" & readIndY & aluInT & aluInp, -- B3 iLAX (zp),y
"0010" & "100010" & readZpX & aluInT & aluInp, -- B4 LDY zp,x
"1000" & "100010" & readZpX & aluInT & aluInp, -- B5 LDA zp,x
"0100" & "100010" & readZpY & aluInT & aluInp, -- B6 LDX zp,y
"1100" & "100010" & readZpY & aluInT & aluInp, -- B7 iLAX zp,y
"0000" & "010000" & implied & aluInClr & aluFlg, -- B8 CLV
"1000" & "100010" & readAbsY & aluInT & aluInp, -- B9 LDA abs,y
"0100" & "100010" & implied & aluInS & aluInp, -- BA TSX
"1101" & "100010" & readAbsY & aluInST & aluInp, -- BB iLAS abs,y
"0010" & "100010" & readAbsX & aluInT & aluInp, -- BC LDY abs,x
"1000" & "100010" & readAbsX & aluInT & aluInp, -- BD LDA abs,x
"0100" & "100010" & readAbsY & aluInT & aluInp, -- BE LDX abs,y
"1100" & "100010" & readAbsY & aluInT & aluInp, -- BF iLAX abs,y
-- AXYS NVDIZC addressing aluInput aluMode
"0000" & "100011" & immediate & aluInT & aluCpy, -- C0 CPY imm
"0000" & "100011" & readIndX & aluInT & aluCmp, -- C1 CMP (zp,x)
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- C2 iNOP imm
"0000" & "100011" & rmwIndX & aluInT & aluDcp, -- C3 iDCP (zp,x)
"0000" & "100011" & readZp & aluInT & aluCpy, -- C4 CPY zp
"0000" & "100011" & readZp & aluInT & aluCmp, -- C5 CMP zp
"0000" & "100010" & rmwZp & aluInT & aluDec, -- C6 DEC zp
"0000" & "100011" & rmwZp & aluInT & aluDcp, -- C7 iDCP zp
"0010" & "100010" & implied & aluInY & aluInc, -- C8 INY
"0000" & "100011" & immediate & aluInT & aluCmp, -- C9 CMP imm
"0100" & "100010" & implied & aluInX & aluDec, -- CA DEX
"0100" & "100011" & immediate & aluInT & aluSbx, -- CB SBX imm
"0000" & "100011" & readAbs & aluInT & aluCpy, -- CC CPY abs
"0000" & "100011" & readAbs & aluInT & aluCmp, -- CD CMP abs
"0000" & "100010" & rmwAbs & aluInT & aluDec, -- CE DEC abs
"0000" & "100011" & rmwAbs & aluInT & aluDcp, -- CF iDCP abs
"0000" & "000000" & relative & aluInXXX & aluXXX, -- D0 BNE
"0000" & "100011" & readIndY & aluInT & aluCmp, -- D1 CMP (zp),y
"----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- D2 *** JAM ***
"0000" & "100011" & rmwIndY & aluInT & aluDcp, -- D3 iDCP (zp),y
"0000" & "000000" & readZpX & aluInXXX & aluXXX, -- D4 iNOP zp,x
"0000" & "100011" & readZpX & aluInT & aluCmp, -- D5 CMP zp,x
"0000" & "100010" & rmwZpX & aluInT & aluDec, -- D6 DEC zp,x
"0000" & "100011" & rmwZpX & aluInT & aluDcp, -- D7 iDCP zp,x
"0000" & "001000" & implied & aluInClr & aluXXX, -- D8 CLD
"0000" & "100011" & readAbsY & aluInT & aluCmp, -- D9 CMP abs,y
"0000" & "000000" & implied & aluInXXX & aluXXX, -- DA iNOP implied
"0000" & "100011" & rmwAbsY & aluInT & aluDcp, -- DB iDCP abs,y
"0000" & "000000" & readAbsX & aluInXXX & aluXXX, -- DC iNOP abs,x
"0000" & "100011" & readAbsX & aluInT & aluCmp, -- DD CMP abs,x
"0000" & "100010" & rmwAbsX & aluInT & aluDec, -- DE DEC abs,x
"0000" & "100011" & rmwAbsX & aluInT & aluDcp, -- DF iDCP abs,x
-- AXYS NVDIZC addressing aluInput aluMode
"0000" & "100011" & immediate & aluInT & aluCpx, -- E0 CPX imm
"1000" & "110011" & readIndX & aluInT & aluSbc, -- E1 SBC (zp,x)
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- E2 iNOP imm
"1000" & "110011" & rmwIndX & aluInT & aluIsc, -- E3 iISC (zp,x)
"0000" & "100011" & readZp & aluInT & aluCpx, -- E4 CPX zp
"1000" & "110011" & readZp & aluInT & aluSbc, -- E5 SBC zp
"0000" & "100010" & rmwZp & aluInT & aluInc, -- E6 INC zp
"1000" & "110011" & rmwZp & aluInT & aluIsc, -- E7 iISC zp
"0100" & "100010" & implied & aluInX & aluInc, -- E8 INX
"1000" & "110011" & immediate & aluInT & aluSbc, -- E9 SBC imm
"0000" & "000000" & implied & aluInXXX & aluXXX, -- EA NOP
"1000" & "110011" & immediate & aluInT & aluSbc, -- EB SBC imm (illegal opc)
"0000" & "100011" & readAbs & aluInT & aluCpx, -- EC CPX abs
"1000" & "110011" & readAbs & aluInT & aluSbc, -- ED SBC abs
"0000" & "100010" & rmwAbs & aluInT & aluInc, -- EE INC abs
"1000" & "110011" & rmwAbs & aluInT & aluIsc, -- EF iISC abs
"0000" & "000000" & relative & aluInXXX & aluXXX, -- F0 BEQ
"1000" & "110011" & readIndY & aluInT & aluSbc, -- F1 SBC (zp),y
"----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- F2 *** JAM ***
"1000" & "110011" & rmwIndY & aluInT & aluIsc, -- F3 iISC (zp),y
"0000" & "000000" & readZpX & aluInXXX & aluXXX, -- F4 iNOP zp,x
"1000" & "110011" & readZpX & aluInT & aluSbc, -- F5 SBC zp,x
"0000" & "100010" & rmwZpX & aluInT & aluInc, -- F6 INC zp,x
"1000" & "110011" & rmwZpX & aluInT & aluIsc, -- F7 iISC zp,x
"0000" & "001000" & implied & aluInSet & aluXXX, -- F8 SED
"1000" & "110011" & readAbsY & aluInT & aluSbc, -- F9 SBC abs,y
"0000" & "000000" & implied & aluInXXX & aluXXX, -- FA iNOP implied
"1000" & "110011" & rmwAbsY & aluInT & aluIsc, -- FB iISC abs,y
"0000" & "000000" & readAbsX & aluInXXX & aluXXX, -- FC iNOP abs,x
"1000" & "110011" & readAbsX & aluInT & aluSbc, -- FD SBC abs,x
"0000" & "100010" & rmwAbsX & aluInT & aluInc, -- FE INC abs,x
"1000" & "110011" & rmwAbsX & aluInT & aluIsc -- FF iISC abs,x
);
signal opcInfo : decodedBitsDef;
signal nextOpcInfo : decodedBitsDef; -- Next opcode (decoded)
signal nextOpcInfoReg : decodedBitsDef; -- Next opcode (decoded) pipelined
signal theOpcode : unsigned(7 downto 0);
signal nextOpcode : unsigned(7 downto 0);
-- Program counter
signal PC : unsigned(15 downto 0); -- Program counter
-- Address generation
type nextAddrDef is (
nextAddrHold,
nextAddrIncr,
nextAddrIncrL, -- Increment low bits only (zeropage accesses)
nextAddrIncrH, -- Increment high bits only (page-boundary)
nextAddrDecrH, -- Decrement high bits (branch backwards)
nextAddrPc,
nextAddrIrq,
nextAddrReset,
nextAddrAbs,
nextAddrAbsIndexed,
nextAddrZeroPage,
nextAddrZPIndexed,
nextAddrStack,
nextAddrRelative
);
signal nextAddr : nextAddrDef;
signal myAddr : unsigned(15 downto 0);
signal myAddrIncr : unsigned(15 downto 0);
signal myAddrIncrH : unsigned(7 downto 0);
signal myAddrDecrH : unsigned(7 downto 0);
signal theWe : std_logic;
signal irqActive : std_logic;
-- Output register
signal doReg : unsigned(7 downto 0);
-- Buffer register
signal T : unsigned(7 downto 0);
-- General registers
signal A: unsigned(7 downto 0); -- Accumulator
signal X: unsigned(7 downto 0); -- Index X
signal Y: unsigned(7 downto 0); -- Index Y
signal S: unsigned(7 downto 0); -- stack pointer
-- Status register
signal C: std_logic; -- Carry
signal Z: std_logic; -- Zero flag
signal I: std_logic; -- Interrupt flag
signal D: std_logic; -- Decimal mode
signal V: std_logic; -- Overflow
signal N: std_logic; -- Negative
-- ALU
-- ALU input
signal aluInput : unsigned(7 downto 0);
signal aluCmpInput : unsigned(7 downto 0);
-- ALU output
signal aluRegisterOut : unsigned(7 downto 0);
signal aluRmwOut : unsigned(7 downto 0);
signal aluC : std_logic;
signal aluZ : std_logic;
signal aluV : std_logic;
signal aluN : std_logic;
-- Pipeline registers
signal aluInputReg : unsigned(7 downto 0);
signal aluCmpInputReg : unsigned(7 downto 0);
signal aluRmwReg : unsigned(7 downto 0);
signal aluNineReg : unsigned(7 downto 0);
signal aluCReg : std_logic;
signal aluZReg : std_logic;
signal aluVReg : std_logic;
signal aluNReg : std_logic;
-- Indexing
signal indexOut : unsigned(8 downto 0);
begin
processAluInput: process(clk, opcInfo, A, X, Y, T, S)
variable temp : unsigned(7 downto 0);
begin
temp := (others => '1');
if opcInfo(opcInA) = '1' then
temp := temp and A;
end if;
if opcInfo(opcInE) = '1' then
temp := temp and (A or X"EE");
end if;
if opcInfo(opcInX) = '1' then
temp := temp and X;
end if;
if opcInfo(opcInY) = '1' then
temp := temp and Y;
end if;
if opcInfo(opcInS) = '1' then
temp := temp and S;
end if;
if opcInfo(opcInT) = '1' then
temp := temp and T;
end if;
if opcInfo(opcInClear) = '1' then
temp := (others => '0');
end if;
if rising_edge(clk) then
aluInputReg <= temp;
end if;
aluInput <= temp;
if pipelineAluMux then
aluInput <= aluInputReg;
end if;
end process;
processCmpInput: process(clk, opcInfo, A, X, Y)
variable temp : unsigned(7 downto 0);
begin
temp := (others => '1');
if opcInfo(opcInCmp) = '1' then
temp := temp and A;
end if;
if opcInfo(opcInCpx) = '1' then
temp := temp and X;
end if;
if opcInfo(opcInCpy) = '1' then
temp := temp and Y;
end if;
if rising_edge(clk) then
aluCmpInputReg <= temp;
end if;
aluCmpInput <= temp;
if pipelineAluMux then
aluCmpInput <= aluCmpInputReg;
end if;
end process;
-- ALU consists of two parts
-- Read-Modify-Write or index instructions: INC/DEC/ASL/LSR/ROR/ROL
-- Accumulator instructions: ADC, SBC, EOR, AND, EOR, ORA
-- Some instructions are both RMW and accumulator so for most
-- instructions the rmw results are routed through accu alu too.
processAlu: process(clk, opcInfo, aluInput, aluCmpInput, A, T, irqActive, N, V, D, I, Z, C)
variable lowBits: unsigned(5 downto 0);
variable nineBits: unsigned(8 downto 0);
variable rmwBits: unsigned(8 downto 0);
variable varC : std_logic;
variable varZ : std_logic;
variable varV : std_logic;
variable varN : std_logic;
begin
lowBits := (others => '-');
nineBits := (others => '-');
rmwBits := (others => '-');
varV := aluInput(6); -- Default for BIT / PLP / RTI
-- Shift unit
case opcInfo(aluMode1From to aluMode1To) is
when aluModeInp =>
rmwBits := C & aluInput;
when aluModeP =>
rmwBits := C & N & V & '1' & (not irqActive) & D & I & Z & C;
when aluModeInc =>
rmwBits := C & (aluInput + 1);
when aluModeDec =>
rmwBits := C & (aluInput - 1);
when aluModeAsl =>
rmwBits := aluInput & "0";
when aluModeFlg =>
rmwBits := aluInput(0) & aluInput;
when aluModeLsr =>
rmwBits := aluInput(0) & "0" & aluInput(7 downto 1);
when aluModeRol =>
rmwBits := aluInput & C;
when aluModeRoR =>
rmwBits := aluInput(0) & C & aluInput(7 downto 1);
when aluModeAnc =>
rmwBits := (aluInput(7) and A(7)) & aluInput;
when others =>
rmwBits := C & aluInput;
end case;
-- ALU
case opcInfo(aluMode2From to aluMode2To) is
when aluModeAdc =>
lowBits := ("0" & A(3 downto 0) & rmwBits(8)) + ("0" & rmwBits(3 downto 0) & "1");
ninebits := ("0" & A) + ("0" & rmwBits(7 downto 0)) + (B"00000000" & rmwBits(8));
when aluModeSbc =>
lowBits := ("0" & A(3 downto 0) & rmwBits(8)) + ("0" & (not rmwBits(3 downto 0)) & "1");
ninebits := ("0" & A) + ("0" & (not rmwBits(7 downto 0))) + (B"00000000" & rmwBits(8));
when aluModeCmp =>
ninebits := ("0" & aluCmpInput) + ("0" & (not rmwBits(7 downto 0))) + "000000001";
when aluModeAnd =>
ninebits := rmwBits(8) & (A and rmwBits(7 downto 0));
when aluModeEor =>
ninebits := rmwBits(8) & (A xor rmwBits(7 downto 0));
when aluModeOra =>
ninebits := rmwBits(8) & (A or rmwBits(7 downto 0));
when others =>
ninebits := rmwBits;
end case;
if (opcInfo(aluMode1From to aluMode1To) = aluModeFlg) then
varZ := rmwBits(1);
elsif ninebits(7 downto 0) = X"00" then
varZ := '1';
else
varZ := '0';
end if;
case opcInfo(aluMode2From to aluMode2To) is
when aluModeAdc =>
-- decimal mode low bits correction, is done after setting Z flag.
if D = '1' then
if lowBits(5 downto 1) > 9 then
ninebits(3 downto 0) := ninebits(3 downto 0) + 6;
if lowBits(5) = '0' then
ninebits(8 downto 4) := ninebits(8 downto 4) + 1;
end if;
end if;
end if;
when others =>
null;
end case;
if (opcInfo(aluMode1From to aluMode1To) = aluModeBit)
or (opcInfo(aluMode1From to aluMode1To) = aluModeFlg) then
varN := rmwBits(7);
else
varN := nineBits(7);
end if;
varC := ninebits(8);
if opcInfo(aluMode2From to aluMode2To) = aluModeArr then
varC := aluInput(7);
varV := aluInput(7) xor aluInput(6);
end if;
case opcInfo(aluMode2From to aluMode2To) is
when aluModeAdc =>
-- decimal mode high bits correction, is done after setting Z and N flags
varV := (A(7) xor ninebits(7)) and (rmwBits(7) xor ninebits(7));
if D = '1' then
if ninebits(8 downto 4) > 9 then
ninebits(8 downto 4) := ninebits(8 downto 4) + 6;
varC := '1';
end if;
end if;
when aluModeSbc =>
varV := (A(7) xor ninebits(7)) and ((not rmwBits(7)) xor ninebits(7));
if D = '1' then
-- Check for borrow (lower 4 bits)
if lowBits(5) = '0' then
ninebits(3 downto 0) := ninebits(3 downto 0) - 6;
end if;
-- Check for borrow (upper 4 bits)
if ninebits(8) = '0' then
ninebits(8 downto 4) := ninebits(8 downto 4) - 6;
end if;
end if;
when aluModeArr =>
if D = '1' then
if (("0" & aluInput(3 downto 0)) + ("0000" & aluInput(0))) > 5 then
ninebits(3 downto 0) := ninebits(3 downto 0) + 6;
end if;
if (("0" & aluInput(7 downto 4)) + ("0000" & aluInput(4))) > 5 then
ninebits(8 downto 4) := ninebits(8 downto 4) + 6;
varC := '1';
else
varC := '0';
end if;
end if;
when others =>
null;
end case;
if rising_edge(clk) then
aluRmwReg <= rmwBits(7 downto 0);
aluNineReg <= ninebits(7 downto 0);
aluCReg <= varC;
aluZReg <= varZ;
aluVReg <= varV;
aluNReg <= varN;
end if;
aluRmwOut <= rmwBits(7 downto 0);
aluRegisterOut <= ninebits(7 downto 0);
aluC <= varC;
aluZ <= varZ;
aluV <= varV;
aluN <= varN;
if pipelineAluOut then
aluRmwOut <= aluRmwReg;
aluRegisterOut <= aluNineReg;
aluC <= aluCReg;
aluZ <= aluZReg;
aluV <= aluVReg;
aluN <= aluNReg;
end if;
end process;
calcInterrupt: process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
if theCpuCycle = cycleStack4
or reset = '1' then
nmiReg <= '1';
end if;
if nextCpuCycle /= cycleBranchTaken
and nextCpuCycle /= opcodeFetch then
irqReg <= irq_n;
nmiEdge <= nmi_n;
if (nmiEdge = '1') and (nmi_n = '0') then
nmiReg <= '0';
end if;
end if;
-- The 'or opcInfo(opcSetI)' prevents NMI immediately after BRK or IRQ.
-- Presumably this is done in the real 6502/6510 to prevent a double IRQ.
processIrq <= not ((nmiReg and (irqReg or I)) or opcInfo(opcIRQ));
end if;
end if;
end process;
calcNextOpcode: process(clk, di, reset, processIrq)
variable myNextOpcode : unsigned(7 downto 0);
begin
-- Next opcode is read from input unless a reset or IRQ is pending.
myNextOpcode := di;
if reset = '1' then
myNextOpcode := X"4C";
elsif processIrq = '1' then
myNextOpcode := X"00";
end if;
nextOpcode <= myNextOpcode;
end process;
nextOpcInfo <= opcodeInfoTable(to_integer(nextOpcode));
process(clk)
begin
if rising_edge(clk) then
nextOpcInfoReg <= nextOpcInfo;
end if;
end process;
-- Read bits and flags from opcodeInfoTable and store in opcInfo.
-- This info is used to control the execution of the opcode.
calcOpcInfo: process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
if (reset = '1') or (theCpuCycle = opcodeFetch) then
opcInfo <= nextOpcInfo;
if pipelineOpcode then
opcInfo <= nextOpcInfoReg;
end if;
end if;
end if;
end if;
end process;
calcTheOpcode: process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
if theCpuCycle = opcodeFetch then
irqActive <= '0';
if processIrq = '1' then
irqActive <= '1';
end if;
-- Fetch opcode
theOpcode <= nextOpcode;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- State machine
-- -----------------------------------------------------------------------
process(enable, theCpuCycle, opcInfo)
begin
updateRegisters <= false;
if enable = '1' then
if opcInfo(opcRti) = '1' then
if theCpuCycle = cycleRead then
updateRegisters <= true;
end if;
elsif theCpuCycle = opcodeFetch then
updateRegisters <= true;
end if;
end if;
end process;
debugOpcode <= theOpcode;
process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
theCpuCycle <= nextCpuCycle;
end if;
if reset = '1' then
theCpuCycle <= cycle2;
end if;
end if;
end process;
-- Determine the next cpu cycle. After the last cycle we always
-- go to opcodeFetch to get the next opcode.
calcNextCpuCycle: process(theCpuCycle, opcInfo, theOpcode, indexOut, T, N, V, C, Z)
begin
nextCpuCycle <= opcodeFetch;
case theCpuCycle is
when opcodeFetch =>
nextCpuCycle <= cycle2;
when cycle2 =>
if opcInfo(opcBranch) = '1' then
if (N = theOpcode(5) and theOpcode(7 downto 6) = "00")
or (V = theOpcode(5) and theOpcode(7 downto 6) = "01")
or (C = theOpcode(5) and theOpcode(7 downto 6) = "10")
or (Z = theOpcode(5) and theOpcode(7 downto 6) = "11") then
-- Branch condition is true
nextCpuCycle <= cycleBranchTaken;
end if;
elsif (opcInfo(opcStackUp) = '1') then
nextCpuCycle <= cycleStack1;
elsif opcInfo(opcStackAddr) = '1'
and opcInfo(opcStackData) = '1' then
nextCpuCycle <= cycleStack2;
elsif opcInfo(opcStackAddr) = '1' then
nextCpuCycle <= cycleStack1;
elsif opcInfo(opcStackData) = '1' then
nextCpuCycle <= cycleWrite;
elsif opcInfo(opcAbsolute) = '1' then
nextCpuCycle <= cycle3;
elsif opcInfo(opcIndirect) = '1' then
if opcInfo(indexX) = '1' then
nextCpuCycle <= cyclePreIndirect;
else
nextCpuCycle <= cycleIndirect;
end if;
elsif opcInfo(opcZeroPage) = '1' then
if opcInfo(opcWrite) = '1' then
if (opcInfo(indexX) = '1')
or (opcInfo(indexY) = '1') then
nextCpuCycle <= cyclePreWrite;
else
nextCpuCycle <= cycleWrite;
end if;
else
if (opcInfo(indexX) = '1')
or (opcInfo(indexY) = '1') then
nextCpuCycle <= cyclePreRead;
else
nextCpuCycle <= cycleRead2;
end if;
end if;
elsif opcInfo(opcJump) = '1' then
nextCpuCycle <= cycleJump;
end if;
when cycle3 =>
nextCpuCycle <= cycleRead;
if opcInfo(opcWrite) = '1' then
if (opcInfo(indexX) = '1')
or (opcInfo(indexY) = '1') then
nextCpuCycle <= cyclePreWrite;
else
nextCpuCycle <= cycleWrite;
end if;
end if;
if (opcInfo(opcIndirect) = '1')
and (opcInfo(indexX) = '1') then
if opcInfo(opcWrite) = '1' then
nextCpuCycle <= cycleWrite;
else
nextCpuCycle <= cycleRead2;
end if;
end if;
when cyclePreIndirect =>
nextCpuCycle <= cycleIndirect;
when cycleIndirect =>
nextCpuCycle <= cycle3;
when cycleBranchTaken =>
if indexOut(8) /= T(7) then
-- Page boundary crossing during branch.
nextCpuCycle <= cycleBranchPage;
end if;
when cyclePreRead =>
if opcInfo(opcZeroPage) = '1' then
nextCpuCycle <= cycleRead2;
end if;
when cycleRead =>
if opcInfo(opcJump) = '1' then
nextCpuCycle <= cycleJump;
elsif indexOut(8) = '1' then
-- Page boundary crossing while indexed addressing.
nextCpuCycle <= cycleRead2;
elsif opcInfo(opcRmw) = '1' then
nextCpuCycle <= cycleRmw;
if opcInfo(indexX) = '1'
or opcInfo(indexY) = '1' then
-- 6510 needs extra cycle for indexed addressing
-- combined with RMW indexing
nextCpuCycle <= cycleRead2;
end if;
end if;
when cycleRead2 =>
if opcInfo(opcRmw) = '1' then
nextCpuCycle <= cycleRmw;
end if;
when cycleRmw =>
nextCpuCycle <= cycleWrite;
when cyclePreWrite =>
nextCpuCycle <= cycleWrite;
when cycleStack1 =>
nextCpuCycle <= cycleRead;
if opcInfo(opcStackAddr) = '1' then
nextCpuCycle <= cycleStack2;
end if;
when cycleStack2 =>
nextCpuCycle <= cycleStack3;
if opcInfo(opcRti) = '1' then
nextCpuCycle <= cycleRead;
end if;
if opcInfo(opcStackData) = '0'
and opcInfo(opcStackUp) = '1' then
nextCpuCycle <= cycleJump;
end if;
when cycleStack3 =>
nextCpuCycle <= cycleRead;
if opcInfo(opcStackData) = '0'
or opcInfo(opcStackUp) = '1' then
nextCpuCycle <= cycleJump;
elsif opcInfo(opcStackAddr) = '1' then
nextCpuCycle <= cycleStack4;
end if;
when cycleStack4 =>
nextCpuCycle <= cycleRead;
when cycleJump =>
if opcInfo(opcIncrAfter) = '1' then
-- Insert extra cycle
nextCpuCycle <= cycleEnd;
end if;
when others =>
null;
end case;
end process;
-- -----------------------------------------------------------------------
-- T register
-- -----------------------------------------------------------------------
calcT: process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
case theCpuCycle is
when cycle2 =>
T <= di;
when cycleStack1 | cycleStack2 =>
if opcInfo(opcStackUp) = '1' then
-- Read from stack
T <= di;
end if;
when cycleIndirect | cycleRead | cycleRead2 =>
T <= di;
when others =>
null;
end case;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- A register
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateA) = '1' then
A <= aluRegisterOut;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- X register
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateX) = '1' then
X <= aluRegisterOut;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- Y register
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateY) = '1' then
Y <= aluRegisterOut;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- C flag
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateC) = '1' then
C <= aluC;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- Z flag
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateZ) = '1' then
Z <= aluZ;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- I flag
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateI) = '1' then
I <= aluInput(2);
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- D flag
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateD) = '1' then
D <= aluInput(3);
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- V flag
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateV) = '1' then
V <= aluV;
end if;
end if;
if enable = '1' then
if soReg = '1' and so_n = '0' then
V <= '1';
end if;
soReg <= so_n;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- N flag
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateN) = '1' then
N <= aluN;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- Stack pointer
-- -----------------------------------------------------------------------
process(clk)
variable sIncDec : unsigned(7 downto 0);
variable updateFlag : boolean;
begin
if rising_edge(clk) then
if opcInfo(opcStackUp) = '1' then
sIncDec := S + 1;
else
sIncDec := S - 1;
end if;
if enable = '1' then
updateFlag := false;
case nextCpuCycle is
when cycleStack1 =>
if (opcInfo(opcStackUp) = '1')
or (opcInfo(opcStackData) = '1') then
updateFlag := true;
end if;
when cycleStack2 =>
updateFlag := true;
when cycleStack3 =>
updateFlag := true;
when cycleStack4 =>
updateFlag := true;
when cycleRead =>
if opcInfo(opcRti) = '1' then
updateFlag := true;
end if;
when cycleWrite =>
if opcInfo(opcStackData) = '1' then
updateFlag := true;
end if;
when others =>
null;
end case;
if updateFlag then
S <= sIncDec;
end if;
end if;
if updateRegisters then
if opcInfo(opcUpdateS) = '1' then
S <= aluRegisterOut;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- Data out
-- -----------------------------------------------------------------------
--calcDo: process(cpuNo, theCpuCycle, aluOut, PC, T)
calcDo: process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
doReg <= aluRmwOut;
if opcInfo(opcInH) = '1' then
-- For illegal opcodes SHA, SHX, SHY, SHS
doReg <= aluRmwOut and myAddrIncrH;
end if;
case nextCpuCycle is
when cycleStack2 =>
if opcInfo(opcIRQ) = '1'
and irqActive = '0' then
doReg <= myAddrIncr(15 downto 8);
else
doReg <= PC(15 downto 8);
end if;
when cycleStack3 =>
doReg <= PC(7 downto 0);
when cycleRmw =>
-- do <= T; -- Read-modify-write write old value first.
doReg <= di; -- Read-modify-write write old value first.
when others => null;
end case;
end if;
end if;
end process;
do <= doReg;
-- -----------------------------------------------------------------------
-- Write enable
-- -----------------------------------------------------------------------
calcWe: process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
theWe <= '0';
case nextCpuCycle is
when cycleStack1 =>
if opcInfo(opcStackUp) = '0'
and ((opcInfo(opcStackAddr) = '0')
or (opcInfo(opcStackData) = '1')) then
theWe <= '1';
end if;
when cycleStack2 | cycleStack3 | cycleStack4 =>
if opcInfo(opcStackUp) = '0' then
theWe <= '1';
end if;
when cycleRmw =>
theWe <= '1';
when cycleWrite =>
theWe <= '1';
when others =>
null;
end case;
end if;
end if;
end process;
we <= theWe;
-- -----------------------------------------------------------------------
-- Program counter
-- -----------------------------------------------------------------------
calcPC: process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
case theCpuCycle is
when opcodeFetch =>
PC <= myAddr;
when cycle2 =>
if irqActive = '0' then
if opcInfo(opcSecondByte) = '1' then
PC <= myAddrIncr;
else
PC <= myAddr;
end if;
end if;
when cycle3 =>
if opcInfo(opcAbsolute) = '1' then
PC <= myAddrIncr;
end if;
when others =>
null;
end case;
end if;
end if;
end process;
debugPc <= PC;
-- -----------------------------------------------------------------------
-- Address generation
-- -----------------------------------------------------------------------
calcNextAddr: process(theCpuCycle, opcInfo, indexOut, T, reset)
begin
nextAddr <= nextAddrIncr;
case theCpuCycle is
when cycle2 =>
if opcInfo(opcStackAddr) = '1'
or opcInfo(opcStackData) = '1' then
nextAddr <= nextAddrStack;
elsif opcInfo(opcAbsolute) = '1' then
nextAddr <= nextAddrIncr;
elsif opcInfo(opcZeroPage) = '1' then
nextAddr <= nextAddrZeroPage;
elsif opcInfo(opcIndirect) = '1' then
nextAddr <= nextAddrZeroPage;
elsif opcInfo(opcSecondByte) = '1' then
nextAddr <= nextAddrIncr;
else
nextAddr <= nextAddrHold;
end if;
when cycle3 =>
if (opcInfo(opcIndirect) = '1')
and (opcInfo(indexX) = '1') then
nextAddr <= nextAddrAbs;
else
nextAddr <= nextAddrAbsIndexed;
end if;
when cyclePreIndirect =>
nextAddr <= nextAddrZPIndexed;
when cycleIndirect =>
nextAddr <= nextAddrIncrL;
when cycleBranchTaken =>
nextAddr <= nextAddrRelative;
when cycleBranchPage =>
if T(7) = '0' then
nextAddr <= nextAddrIncrH;
else
nextAddr <= nextAddrDecrH;
end if;
when cyclePreRead =>
nextAddr <= nextAddrZPIndexed;
when cycleRead =>
nextAddr <= nextAddrPc;
if opcInfo(opcJump) = '1' then
-- Emulate 6510 bug, jmp(xxFF) fetches from same page.
-- Replace with nextAddrIncr if emulating 65C02 or later cpu.
nextAddr <= nextAddrIncrL;
elsif indexOut(8) = '1' then
nextAddr <= nextAddrIncrH;
elsif opcInfo(opcRmw) = '1' then
nextAddr <= nextAddrHold;
end if;
when cycleRead2 =>
nextAddr <= nextAddrPc;
if opcInfo(opcRmw) = '1' then
nextAddr <= nextAddrHold;
end if;
when cycleRmw =>
nextAddr <= nextAddrHold;
when cyclePreWrite =>
nextAddr <= nextAddrHold;
if opcInfo(opcZeroPage) = '1' then
nextAddr <= nextAddrZPIndexed;
elsif indexOut(8) = '1' then
nextAddr <= nextAddrIncrH;
end if;
when cycleWrite =>
nextAddr <= nextAddrPc;
when cycleStack1 =>
nextAddr <= nextAddrStack;
when cycleStack2 =>
nextAddr <= nextAddrStack;
when cycleStack3 =>
nextAddr <= nextAddrStack;
if opcInfo(opcStackData) = '0' then
nextAddr <= nextAddrPc;
end if;
when cycleStack4 =>
nextAddr <= nextAddrIrq;
when cycleJump =>
nextAddr <= nextAddrAbs;
when others =>
null;
end case;
if reset = '1' then
nextAddr <= nextAddrReset;
end if;
end process;
indexAlu: process(opcInfo, myAddr, T, X, Y)
begin
if opcInfo(indexX) = '1' then
indexOut <= (B"0" & T) + (B"0" & X);
elsif opcInfo(indexY) = '1' then
indexOut <= (B"0" & T) + (B"0" & Y);
elsif opcInfo(opcBranch) = '1' then
indexOut <= (B"0" & T) + (B"0" & myAddr(7 downto 0));
else
indexOut <= B"0" & T;
end if;
end process;
calcAddr: process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
case nextAddr is
when nextAddrIncr => myAddr <= myAddrIncr;
when nextAddrIncrL => myAddr(7 downto 0) <= myAddrIncr(7 downto 0);
when nextAddrIncrH => myAddr(15 downto 8) <= myAddrIncrH;
when nextAddrDecrH => myAddr(15 downto 8) <= myAddrDecrH;
when nextAddrPc => myAddr <= PC;
when nextAddrIrq =>
myAddr <= X"FFFE";
if nmiReg = '0' then
myAddr <= X"FFFA";
end if;
when nextAddrReset => myAddr <= X"FFFC";
when nextAddrAbs => myAddr <= di & T;
when nextAddrAbsIndexed => myAddr <= di & indexOut(7 downto 0);
when nextAddrZeroPage => myAddr <= "00000000" & di;
when nextAddrZPIndexed => myAddr <= "00000000" & indexOut(7 downto 0);
when nextAddrStack => myAddr <= "00000001" & S;
when nextAddrRelative => myAddr(7 downto 0) <= indexOut(7 downto 0);
when others => null;
end case;
end if;
end if;
end process;
myAddrIncr <= myAddr + 1;
myAddrIncrH <= myAddr(15 downto 8) + 1;
myAddrDecrH <= myAddr(15 downto 8) - 1;
addr <= myAddr;
debugA <= A;
debugX <= X;
debugY <= Y;
debugS <= S;
end architecture;
| mit | e2fe6b9d1660735a64b8ac40d66c1a8d | 0.565879 | 3.315141 | false | false | false | false |
dummylink/plnk_fpga-stack | Examples/xilinx_microblaze/avnet_lx9/pcores/plb_powerlink_v1_00_a/hdl/vhdl/OpenMAC_phyAct.vhd | 5 | 4,365 | -------------------------------------------------------------------------------
--
-- Title : OpenMAC_phyAct
-- Design : plk_mn
--
-------------------------------------------------------------------------------
--
-- File : OpenMAC_phyAct.vhd
-- Generated : Wed Jul 27 12:01:32 2011
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2011
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- 2011-07-27 V0.01 zelenkaj First version
--
-------------------------------------------------------------------------------
--{{ Section below this comment is automatically maintained
-- and may be overwritten
--{entity {OpenMAC_phyAct} architecture {rtl}}
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.math_real.log2;
use ieee.math_real.ceil;
entity OpenMAC_phyAct is
generic(
iBlinkFreq_g : integer := 6 -- [Hz]
);
port(
clk : in std_logic;
rst : in std_logic;
tx_en : in std_logic;
rx_dv : in std_logic;
act_led : out std_logic
);
end OpenMAC_phyAct;
--}} End of automatically maintained section
architecture rtl of OpenMAC_phyAct is
constant iMaxCnt : integer := 50e6 / iBlinkFreq_g;
constant iLog2MaxCnt : integer := integer(ceil(log2(real(iMaxCnt))));
signal cnt : std_logic_vector(iLog2MaxCnt-1 downto 0);
signal cnt_tc : std_logic;
signal actTrig : std_logic;
signal actEnable : std_logic;
begin
act_led <= cnt(cnt'high) when actEnable = '1' else '0';
ledCntr : process(clk, rst)
begin
if rst = '1' then
actTrig <= '0';
actEnable <= '0';
elsif clk = '1' and clk'event then
--monoflop, of course no default value!
if actTrig = '1' and cnt_tc = '1' then
--counter overflow and activity within last cycle
actEnable <= '1';
elsif cnt_tc = '1' then
--counter overflow but no activity
actEnable <= '0';
end if;
--monoflop, of course no default value!
if cnt_tc = '1' then
--count cycle over, reset trigger
actTrig <= '0';
elsif tx_en = '1' or rx_dv = '1' then
--activity within cycle
actTrig <= '1';
end if;
end if;
end process;
theFreeRunCnt : process(clk, rst)
begin
if rst = '1' then
cnt <= (others => '0');
elsif clk = '1' and clk'event then
--nice, it may count for ever!
cnt <= cnt - 1;
end if;
end process;
cnt_tc <= '1' when cnt = 0 else '0'; --"counter overflow"
end rtl;
| gpl-2.0 | 5ece634095f503bc06a5b795b7ed0984 | 0.587171 | 3.677338 | false | false | false | false |
SebastianCallh/copter-modern | copter_modern.vhd | 1 | 8,799 | --------------------------------------------------------------------------------
-- VGA lab
-- Anders Nilsson
-- 16-dec-2015
-- Version 1.0
-- library declaration
library IEEE;
use IEEE.STD_LOGIC_1164.ALL; -- basic IEEE library
use IEEE.NUMERIC_STD.ALL; -- IEEE library for the unsigned type
-- and various arithmetic operations
-- entity
entity copter_modern is
port ( clk : in std_logic; -- system clock
rst : in std_logic; -- reset
seg : out std_logic_vector(7 downto 0); --7-segment display
an : out std_logic_vector(3 downto 0);
Hsync : out std_logic; -- horizontal sync
Vsync : out std_logic; -- vertical sync
vgaRed : out std_logic_vector(2 downto 0); -- VGA red
vgaGreen : out std_logic_vector(2 downto 0); -- VGA green
vgaBlue : out std_logic_vector(2 downto 1); -- VGA blue
PS2KeyboardCLK : in std_logic; -- PS2 clock
PS2KeyboardData : in std_logic; -- PS2 data
keypress : out std_logic); -- input flag
end copter_modern;
-- architecture
architecture Behavioral of copter_modern is
-- PS2 keyboard encoder component
component KBD_ENC
port ( clk : in std_logic; -- system clock
rst : in std_logic; -- reset signal
PS2KeyboardCLK : in std_logic; -- PS2 clock
PS2KeyboardData : in std_logic; -- PS2 data
input : out std_logic);
end component;
-- VGA motor component
component VGA_MOTOR
port ( clk : in std_logic; -- system clock
rst : in std_logic; -- reset
vgaRed : out std_logic_vector(2 downto 0); -- VGA red
vgaGreen : out std_logic_vector(2 downto 0); -- VGA green
vgaBlue : out std_logic_vector(2 downto 1); -- VGA blue
Hsync : out std_logic; -- horizontal sync
Vsync : out std_logic; -- vertical sync
player_x : in integer;
player_y : in integer;
collision : out std_logic;
new_column : out std_logic;
gap : in integer;
height : in integer;
terrain_change : out std_logic;
speed : in integer);
end component;
-- CPU
component CPU
port ( clk : in std_logic; -- systen clock
collision : in std_logic;
reset : in std_logic;
player_x : out integer;
player_y : out integer;
input : in std_logic; -- keypress input
new_column : in std_logic;
gap : out integer;
height : out integer;
terrain_change : in std_logic;
speed : out integer;
score : out std_logic_vector(15 downto 0));
end component;
-- intermediate signals between VGA_MOTOR and CPU
signal player_x_s : integer; -- players pixel-x
signal player_y_s : integer; -- players pixel-y
signal collision : std_logic; -- collision interrupt flag
signal input_local : std_logic; -- input (from KBD_ENC to CPU)
signal new_column : std_logic; -- flag for computing next column
signal gap_s : integer;
signal height_s : integer;
signal terrain_change_s : std_logic;
signal speed_s : integer;
signal seg_cnt : unsigned(15 downto 0) := (others => '0');
signal points : std_logic_vector(15 downto 0) := "0000000100100011";
signal points_prev : std_logic_vector(15 downto 0);
signal segments : std_logic_vector(7 downto 0) := (others => '0');
signal seg_val : std_logic_vector(3 downto 0) := (others => '0');
signal seg_dis : std_logic_vector(3 downto 0) := (others => '0');
constant POINTS_LATENCY : integer := 300000000;
signal points_counter : integer;
signal point_wait : std_logic := '0';
begin
keypress <= input_local;
-- keyboard encoder component connection
KE : KBD_ENC port map(clk=>clk,
rst=>rst,
PS2KeyboardCLK=>PS2KeyboardCLK,
PS2KeyboardData=>PS2KeyboardData,
input=>input_local);
-- VGA motor component connection
VM : VGA_MOTOR port map(clk=>clk,
rst=>rst,
vgaRed=>vgaRed,
vgaGreen=>vgaGreen,
vgaBlue=>vgaBlue,
player_x=>player_x_s,
player_y=>player_y_s,
collision=>collision,
Hsync=>Hsync,
Vsync=>Vsync,
new_column=>new_column,
gap=>gap_s,
height=>height_s,
terrain_change=>terrain_change_s,
speed=>speed_s);
-- CPU connector
CP : CPU port map(clk=>clk,
collision=>collision,
reset=>rst,
player_x=>player_x_s,
player_y=>player_y_s,
input=>input_local,
new_column=>new_column,
gap=>gap_s,
height=>height_s,
terrain_change=>terrain_change_s,
speed=>speed_s,
score=>points);
--7-seg point counter
process(clk) --16-bit counter
begin
if rising_edge(clk) then
if seg_cnt = "1111111111111111" then
seg_cnt <= (others => '0');
else
seg_cnt <= (seg_cnt + 1);
end if;
end if;
end process;
with seg_cnt(15 downto 14) select seg_val <=
points_prev(15 downto 12) when "00",
points_prev(11 downto 8) when "01",
points_prev(7 downto 4) when "10",
points_prev(3 downto 0) when others;
process(clk)
begin
if rising_edge(clk) then
case seg_val is
when "0000" => segments <= "11000000";
when "0001" => segments <= "11111001";
when "0010" => segments <= "10100100";
when "0011" => segments <= "10110000";
when "0100" => segments <= "10011001";
when "0101" => segments <= "10010010";
when "0110" => segments <= "10000010";
when "0111" => segments <= "11111000";
when "1000" => segments <= "10000000";
when "1001" => segments <= "10010000";
when "1010" => segments <= "10001001";
when "1011" => segments <= "11100001";
when "1100" => segments <= "10110001";
when "1101" => segments <= "11000011";
when "1110" => segments <= "10110001";
when others => segments <= "10111001";
end case;
case seg_cnt(15 downto 14) is
when "00" => seg_dis <= "0111";
when "01" => seg_dis <= "1011";
when "10" => seg_dis <= "1101";
when others => seg_dis <= "1110";
end case;
end if;
end process;
seg <= segments;
an <= seg_dis;
-- Show points on display for a short while after collision
process(clk)
begin
if rising_edge(clk) then
-- If collision, stop updating the points
if collision = '1' then
point_wait <= '1';
points_counter <= 0;
-- If waited, reset points_counter and allow showing current points
elsif points_counter > POINTS_LATENCY then
points_counter <= 0;
point_wait <= '0';
-- While waiting, keep counting up until points_counter reaches POINTS_LATENCY
elsif point_wait = '1' then
points_counter <= points_counter + 1;
-- If not waiting, make sure points_prev is updated to show points
else
points_prev <= points;
end if;
end if;
end process;
end Behavioral;
| mit | f75dddedfb205792b80d309643d8c363 | 0.465394 | 4.51926 | false | false | false | false |
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`protect end_protected
| gpl-3.0 | 07af93b87f449791bb3ebbdf4f60449a | 0.946917 | 1.838514 | false | false | false | false |
estadofinito/biblioteca-vhdl | todos-los-archivos/clk0_5Hz.vhd | 2 | 1,360 | ----------------------------------------------------------------------------------
-- Compañía: Estado Finito
-- Ingeniero: Carlos Ramos
--
-- Fecha de creación: 2014/04/13 08:26:07
-- Nombre del módulo: clk0_5Hz - Behavioral
-- Comentarios adicionales:
-- Implementación mediante aproximación, a caso con escala ajustada par (de 100000000 a 100000000).
-- La frecuencia fue ajustada al entero más próximo.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity clk0_5Hz is
Port (
clk : in STD_LOGIC; -- Reloj de entrada de 50000000Hz.
reset : in STD_LOGIC;
clk_out : out STD_LOGIC -- Reloj de salida de 0.5Hz.
);
end clk0_5Hz;
architecture Behavioral of clk0_5Hz is
signal temporal: STD_LOGIC;
signal contador: integer range 0 to 49999999 := 0;
begin
divisor_frecuencia: process (clk, reset) begin
if (reset = '1') then
temporal <= '0';
contador <= 0;
elsif rising_edge(clk) then
if (contador = 49999999) then
temporal <= NOT(temporal);
contador <= 0;
else
contador <= contador + 1;
end if;
end if;
end process;
clk_out <= temporal;
end Behavioral; | lgpl-2.1 | 039a198a58a4890c95a2838754acf8ca | 0.515441 | 4.023669 | false | false | false | false |
DougFirErickson/parallella-hw | fpga/ip/xilinx/fifo_async_103x32/fifo_generator_v12_0/hdl/builtin/fifo_generator_v12_0_comps_builtin.vhd | 6 | 32,006 | `protect begin_protected
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`protect end_protected
| gpl-3.0 | 13a6b46c88af9f54755aa443234a9740 | 0.946323 | 1.842284 | false | false | false | false |
DougFirErickson/parallella-hw | fpga/ip/xilinx/fifo_async_103x16/fifo_async_103x16_funcsim.vhdl | 2 | 235,213 | -- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.3.1 (lin64) Build 1056140 Thu Oct 30 16:30:39 MDT 2014
-- Date : Wed Apr 8 20:38:45 2015
-- Host : parallella running 64-bit Ubuntu 14.04.2 LTS
-- Command : write_vhdl -force -mode funcsim
-- /home/aolofsson/Work_all/parallella-hw/fpga/vivado/junk/junk.srcs/sources_1/ip/fifo_async_103x16/fifo_async_103x16_funcsim.vhdl
-- Design : fifo_async_103x16
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x16_dmem is
port (
Q : out STD_LOGIC_VECTOR ( 102 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC;
I1 : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_clk : in STD_LOGIC;
I2 : in STD_LOGIC_VECTOR ( 0 to 0 );
din : in STD_LOGIC_VECTOR ( 102 downto 0 );
ADDRA : in STD_LOGIC_VECTOR ( 3 downto 0 );
O3 : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x16_dmem : entity is "dmem";
end fifo_async_103x16_dmem;
architecture STRUCTURE of fifo_async_103x16_dmem is
signal p_0_out : STD_LOGIC_VECTOR ( 102 downto 0 );
signal NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_102_102_DOA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_RAM_reg_0_15_102_102_DOB_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_102_102_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_102_102_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_36_41_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_42_47_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_48_53_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_54_59_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_60_65_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_66_71_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_72_77_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_78_83_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_84_89_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_90_95_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_96_101_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
RAM_reg_0_15_0_5: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => ADDRA(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => ADDRA(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => ADDRA(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => O3(3 downto 0),
DIA(1 downto 0) => din(1 downto 0),
DIB(1 downto 0) => din(3 downto 2),
DIC(1 downto 0) => din(5 downto 4),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(1 downto 0),
DOB(1 downto 0) => p_0_out(3 downto 2),
DOC(1 downto 0) => p_0_out(5 downto 4),
DOD(1 downto 0) => NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => I2(0)
);
RAM_reg_0_15_102_102: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => ADDRA(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => ADDRA(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => ADDRA(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => O3(3 downto 0),
DIA(1) => '0',
DIA(0) => din(102),
DIB(1) => '0',
DIB(0) => '0',
DIC(1) => '0',
DIC(0) => '0',
DID(1) => '0',
DID(0) => '0',
DOA(1) => NLW_RAM_reg_0_15_102_102_DOA_UNCONNECTED(1),
DOA(0) => p_0_out(102),
DOB(1 downto 0) => NLW_RAM_reg_0_15_102_102_DOB_UNCONNECTED(1 downto 0),
DOC(1 downto 0) => NLW_RAM_reg_0_15_102_102_DOC_UNCONNECTED(1 downto 0),
DOD(1 downto 0) => NLW_RAM_reg_0_15_102_102_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => I2(0)
);
RAM_reg_0_15_12_17: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => ADDRA(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => ADDRA(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => ADDRA(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => O3(3 downto 0),
DIA(1 downto 0) => din(13 downto 12),
DIB(1 downto 0) => din(15 downto 14),
DIC(1 downto 0) => din(17 downto 16),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(13 downto 12),
DOB(1 downto 0) => p_0_out(15 downto 14),
DOC(1 downto 0) => p_0_out(17 downto 16),
DOD(1 downto 0) => NLW_RAM_reg_0_15_12_17_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => I2(0)
);
RAM_reg_0_15_18_23: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => ADDRA(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => ADDRA(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => ADDRA(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => O3(3 downto 0),
DIA(1 downto 0) => din(19 downto 18),
DIB(1 downto 0) => din(21 downto 20),
DIC(1 downto 0) => din(23 downto 22),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(19 downto 18),
DOB(1 downto 0) => p_0_out(21 downto 20),
DOC(1 downto 0) => p_0_out(23 downto 22),
DOD(1 downto 0) => NLW_RAM_reg_0_15_18_23_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => I2(0)
);
RAM_reg_0_15_24_29: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => ADDRA(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => ADDRA(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => ADDRA(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => O3(3 downto 0),
DIA(1 downto 0) => din(25 downto 24),
DIB(1 downto 0) => din(27 downto 26),
DIC(1 downto 0) => din(29 downto 28),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(25 downto 24),
DOB(1 downto 0) => p_0_out(27 downto 26),
DOC(1 downto 0) => p_0_out(29 downto 28),
DOD(1 downto 0) => NLW_RAM_reg_0_15_24_29_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => I2(0)
);
RAM_reg_0_15_30_35: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => ADDRA(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => ADDRA(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => ADDRA(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => O3(3 downto 0),
DIA(1 downto 0) => din(31 downto 30),
DIB(1 downto 0) => din(33 downto 32),
DIC(1 downto 0) => din(35 downto 34),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(31 downto 30),
DOB(1 downto 0) => p_0_out(33 downto 32),
DOC(1 downto 0) => p_0_out(35 downto 34),
DOD(1 downto 0) => NLW_RAM_reg_0_15_30_35_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => I2(0)
);
RAM_reg_0_15_36_41: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => ADDRA(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => ADDRA(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => ADDRA(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => O3(3 downto 0),
DIA(1 downto 0) => din(37 downto 36),
DIB(1 downto 0) => din(39 downto 38),
DIC(1 downto 0) => din(41 downto 40),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(37 downto 36),
DOB(1 downto 0) => p_0_out(39 downto 38),
DOC(1 downto 0) => p_0_out(41 downto 40),
DOD(1 downto 0) => NLW_RAM_reg_0_15_36_41_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => I2(0)
);
RAM_reg_0_15_42_47: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => ADDRA(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => ADDRA(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => ADDRA(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => O3(3 downto 0),
DIA(1 downto 0) => din(43 downto 42),
DIB(1 downto 0) => din(45 downto 44),
DIC(1 downto 0) => din(47 downto 46),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(43 downto 42),
DOB(1 downto 0) => p_0_out(45 downto 44),
DOC(1 downto 0) => p_0_out(47 downto 46),
DOD(1 downto 0) => NLW_RAM_reg_0_15_42_47_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => I2(0)
);
RAM_reg_0_15_48_53: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => ADDRA(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => ADDRA(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => ADDRA(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => O3(3 downto 0),
DIA(1 downto 0) => din(49 downto 48),
DIB(1 downto 0) => din(51 downto 50),
DIC(1 downto 0) => din(53 downto 52),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(49 downto 48),
DOB(1 downto 0) => p_0_out(51 downto 50),
DOC(1 downto 0) => p_0_out(53 downto 52),
DOD(1 downto 0) => NLW_RAM_reg_0_15_48_53_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => I2(0)
);
RAM_reg_0_15_54_59: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => ADDRA(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => ADDRA(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => ADDRA(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => O3(3 downto 0),
DIA(1 downto 0) => din(55 downto 54),
DIB(1 downto 0) => din(57 downto 56),
DIC(1 downto 0) => din(59 downto 58),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(55 downto 54),
DOB(1 downto 0) => p_0_out(57 downto 56),
DOC(1 downto 0) => p_0_out(59 downto 58),
DOD(1 downto 0) => NLW_RAM_reg_0_15_54_59_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => I2(0)
);
RAM_reg_0_15_60_65: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => ADDRA(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => ADDRA(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => ADDRA(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => O3(3 downto 0),
DIA(1 downto 0) => din(61 downto 60),
DIB(1 downto 0) => din(63 downto 62),
DIC(1 downto 0) => din(65 downto 64),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(61 downto 60),
DOB(1 downto 0) => p_0_out(63 downto 62),
DOC(1 downto 0) => p_0_out(65 downto 64),
DOD(1 downto 0) => NLW_RAM_reg_0_15_60_65_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => I2(0)
);
RAM_reg_0_15_66_71: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => ADDRA(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => ADDRA(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => ADDRA(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => O3(3 downto 0),
DIA(1 downto 0) => din(67 downto 66),
DIB(1 downto 0) => din(69 downto 68),
DIC(1 downto 0) => din(71 downto 70),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(67 downto 66),
DOB(1 downto 0) => p_0_out(69 downto 68),
DOC(1 downto 0) => p_0_out(71 downto 70),
DOD(1 downto 0) => NLW_RAM_reg_0_15_66_71_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => I2(0)
);
RAM_reg_0_15_6_11: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => ADDRA(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => ADDRA(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => ADDRA(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => O3(3 downto 0),
DIA(1 downto 0) => din(7 downto 6),
DIB(1 downto 0) => din(9 downto 8),
DIC(1 downto 0) => din(11 downto 10),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(7 downto 6),
DOB(1 downto 0) => p_0_out(9 downto 8),
DOC(1 downto 0) => p_0_out(11 downto 10),
DOD(1 downto 0) => NLW_RAM_reg_0_15_6_11_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => I2(0)
);
RAM_reg_0_15_72_77: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => ADDRA(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => ADDRA(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => ADDRA(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => O3(3 downto 0),
DIA(1 downto 0) => din(73 downto 72),
DIB(1 downto 0) => din(75 downto 74),
DIC(1 downto 0) => din(77 downto 76),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(73 downto 72),
DOB(1 downto 0) => p_0_out(75 downto 74),
DOC(1 downto 0) => p_0_out(77 downto 76),
DOD(1 downto 0) => NLW_RAM_reg_0_15_72_77_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => I2(0)
);
RAM_reg_0_15_78_83: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => ADDRA(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => ADDRA(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => ADDRA(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => O3(3 downto 0),
DIA(1 downto 0) => din(79 downto 78),
DIB(1 downto 0) => din(81 downto 80),
DIC(1 downto 0) => din(83 downto 82),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(79 downto 78),
DOB(1 downto 0) => p_0_out(81 downto 80),
DOC(1 downto 0) => p_0_out(83 downto 82),
DOD(1 downto 0) => NLW_RAM_reg_0_15_78_83_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => I2(0)
);
RAM_reg_0_15_84_89: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => ADDRA(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => ADDRA(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => ADDRA(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => O3(3 downto 0),
DIA(1 downto 0) => din(85 downto 84),
DIB(1 downto 0) => din(87 downto 86),
DIC(1 downto 0) => din(89 downto 88),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(85 downto 84),
DOB(1 downto 0) => p_0_out(87 downto 86),
DOC(1 downto 0) => p_0_out(89 downto 88),
DOD(1 downto 0) => NLW_RAM_reg_0_15_84_89_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => I2(0)
);
RAM_reg_0_15_90_95: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => ADDRA(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => ADDRA(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => ADDRA(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => O3(3 downto 0),
DIA(1 downto 0) => din(91 downto 90),
DIB(1 downto 0) => din(93 downto 92),
DIC(1 downto 0) => din(95 downto 94),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(91 downto 90),
DOB(1 downto 0) => p_0_out(93 downto 92),
DOC(1 downto 0) => p_0_out(95 downto 94),
DOD(1 downto 0) => NLW_RAM_reg_0_15_90_95_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => I2(0)
);
RAM_reg_0_15_96_101: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => ADDRA(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => ADDRA(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => ADDRA(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => O3(3 downto 0),
DIA(1 downto 0) => din(97 downto 96),
DIB(1 downto 0) => din(99 downto 98),
DIC(1 downto 0) => din(101 downto 100),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(97 downto 96),
DOB(1 downto 0) => p_0_out(99 downto 98),
DOC(1 downto 0) => p_0_out(101 downto 100),
DOD(1 downto 0) => NLW_RAM_reg_0_15_96_101_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => I2(0)
);
\gpr1.dout_i_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(0),
Q => Q(0)
);
\gpr1.dout_i_reg[100]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(100),
Q => Q(100)
);
\gpr1.dout_i_reg[101]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(101),
Q => Q(101)
);
\gpr1.dout_i_reg[102]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(102),
Q => Q(102)
);
\gpr1.dout_i_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(10),
Q => Q(10)
);
\gpr1.dout_i_reg[11]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(11),
Q => Q(11)
);
\gpr1.dout_i_reg[12]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(12),
Q => Q(12)
);
\gpr1.dout_i_reg[13]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(13),
Q => Q(13)
);
\gpr1.dout_i_reg[14]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(14),
Q => Q(14)
);
\gpr1.dout_i_reg[15]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(15),
Q => Q(15)
);
\gpr1.dout_i_reg[16]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(16),
Q => Q(16)
);
\gpr1.dout_i_reg[17]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(17),
Q => Q(17)
);
\gpr1.dout_i_reg[18]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(18),
Q => Q(18)
);
\gpr1.dout_i_reg[19]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(19),
Q => Q(19)
);
\gpr1.dout_i_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(1),
Q => Q(1)
);
\gpr1.dout_i_reg[20]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(20),
Q => Q(20)
);
\gpr1.dout_i_reg[21]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(21),
Q => Q(21)
);
\gpr1.dout_i_reg[22]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(22),
Q => Q(22)
);
\gpr1.dout_i_reg[23]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(23),
Q => Q(23)
);
\gpr1.dout_i_reg[24]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(24),
Q => Q(24)
);
\gpr1.dout_i_reg[25]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(25),
Q => Q(25)
);
\gpr1.dout_i_reg[26]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(26),
Q => Q(26)
);
\gpr1.dout_i_reg[27]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(27),
Q => Q(27)
);
\gpr1.dout_i_reg[28]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(28),
Q => Q(28)
);
\gpr1.dout_i_reg[29]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(29),
Q => Q(29)
);
\gpr1.dout_i_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(2),
Q => Q(2)
);
\gpr1.dout_i_reg[30]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(30),
Q => Q(30)
);
\gpr1.dout_i_reg[31]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(31),
Q => Q(31)
);
\gpr1.dout_i_reg[32]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(32),
Q => Q(32)
);
\gpr1.dout_i_reg[33]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(33),
Q => Q(33)
);
\gpr1.dout_i_reg[34]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(34),
Q => Q(34)
);
\gpr1.dout_i_reg[35]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(35),
Q => Q(35)
);
\gpr1.dout_i_reg[36]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(36),
Q => Q(36)
);
\gpr1.dout_i_reg[37]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(37),
Q => Q(37)
);
\gpr1.dout_i_reg[38]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(38),
Q => Q(38)
);
\gpr1.dout_i_reg[39]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(39),
Q => Q(39)
);
\gpr1.dout_i_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(3),
Q => Q(3)
);
\gpr1.dout_i_reg[40]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(40),
Q => Q(40)
);
\gpr1.dout_i_reg[41]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(41),
Q => Q(41)
);
\gpr1.dout_i_reg[42]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(42),
Q => Q(42)
);
\gpr1.dout_i_reg[43]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(43),
Q => Q(43)
);
\gpr1.dout_i_reg[44]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(44),
Q => Q(44)
);
\gpr1.dout_i_reg[45]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(45),
Q => Q(45)
);
\gpr1.dout_i_reg[46]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(46),
Q => Q(46)
);
\gpr1.dout_i_reg[47]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(47),
Q => Q(47)
);
\gpr1.dout_i_reg[48]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(48),
Q => Q(48)
);
\gpr1.dout_i_reg[49]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(49),
Q => Q(49)
);
\gpr1.dout_i_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(4),
Q => Q(4)
);
\gpr1.dout_i_reg[50]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(50),
Q => Q(50)
);
\gpr1.dout_i_reg[51]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(51),
Q => Q(51)
);
\gpr1.dout_i_reg[52]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(52),
Q => Q(52)
);
\gpr1.dout_i_reg[53]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(53),
Q => Q(53)
);
\gpr1.dout_i_reg[54]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(54),
Q => Q(54)
);
\gpr1.dout_i_reg[55]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(55),
Q => Q(55)
);
\gpr1.dout_i_reg[56]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(56),
Q => Q(56)
);
\gpr1.dout_i_reg[57]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(57),
Q => Q(57)
);
\gpr1.dout_i_reg[58]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(58),
Q => Q(58)
);
\gpr1.dout_i_reg[59]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(59),
Q => Q(59)
);
\gpr1.dout_i_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(5),
Q => Q(5)
);
\gpr1.dout_i_reg[60]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(60),
Q => Q(60)
);
\gpr1.dout_i_reg[61]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(61),
Q => Q(61)
);
\gpr1.dout_i_reg[62]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(62),
Q => Q(62)
);
\gpr1.dout_i_reg[63]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(63),
Q => Q(63)
);
\gpr1.dout_i_reg[64]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(64),
Q => Q(64)
);
\gpr1.dout_i_reg[65]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(65),
Q => Q(65)
);
\gpr1.dout_i_reg[66]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(66),
Q => Q(66)
);
\gpr1.dout_i_reg[67]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(67),
Q => Q(67)
);
\gpr1.dout_i_reg[68]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(68),
Q => Q(68)
);
\gpr1.dout_i_reg[69]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(69),
Q => Q(69)
);
\gpr1.dout_i_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(6),
Q => Q(6)
);
\gpr1.dout_i_reg[70]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(70),
Q => Q(70)
);
\gpr1.dout_i_reg[71]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(71),
Q => Q(71)
);
\gpr1.dout_i_reg[72]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(72),
Q => Q(72)
);
\gpr1.dout_i_reg[73]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(73),
Q => Q(73)
);
\gpr1.dout_i_reg[74]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(74),
Q => Q(74)
);
\gpr1.dout_i_reg[75]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(75),
Q => Q(75)
);
\gpr1.dout_i_reg[76]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(76),
Q => Q(76)
);
\gpr1.dout_i_reg[77]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(77),
Q => Q(77)
);
\gpr1.dout_i_reg[78]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(78),
Q => Q(78)
);
\gpr1.dout_i_reg[79]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(79),
Q => Q(79)
);
\gpr1.dout_i_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(7),
Q => Q(7)
);
\gpr1.dout_i_reg[80]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(80),
Q => Q(80)
);
\gpr1.dout_i_reg[81]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(81),
Q => Q(81)
);
\gpr1.dout_i_reg[82]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(82),
Q => Q(82)
);
\gpr1.dout_i_reg[83]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(83),
Q => Q(83)
);
\gpr1.dout_i_reg[84]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(84),
Q => Q(84)
);
\gpr1.dout_i_reg[85]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(85),
Q => Q(85)
);
\gpr1.dout_i_reg[86]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(86),
Q => Q(86)
);
\gpr1.dout_i_reg[87]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(87),
Q => Q(87)
);
\gpr1.dout_i_reg[88]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(88),
Q => Q(88)
);
\gpr1.dout_i_reg[89]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(89),
Q => Q(89)
);
\gpr1.dout_i_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(8),
Q => Q(8)
);
\gpr1.dout_i_reg[90]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(90),
Q => Q(90)
);
\gpr1.dout_i_reg[91]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(91),
Q => Q(91)
);
\gpr1.dout_i_reg[92]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(92),
Q => Q(92)
);
\gpr1.dout_i_reg[93]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(93),
Q => Q(93)
);
\gpr1.dout_i_reg[94]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(94),
Q => Q(94)
);
\gpr1.dout_i_reg[95]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(95),
Q => Q(95)
);
\gpr1.dout_i_reg[96]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(96),
Q => Q(96)
);
\gpr1.dout_i_reg[97]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(97),
Q => Q(97)
);
\gpr1.dout_i_reg[98]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(98),
Q => Q(98)
);
\gpr1.dout_i_reg[99]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(99),
Q => Q(99)
);
\gpr1.dout_i_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(9),
Q => Q(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x16_rd_bin_cntr is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
O1 : out STD_LOGIC;
I6 : out STD_LOGIC_VECTOR ( 3 downto 0 );
O2 : out STD_LOGIC_VECTOR ( 2 downto 0 );
I1 : in STD_LOGIC;
I2 : in STD_LOGIC;
O3 : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC;
I3 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x16_rd_bin_cntr : entity is "rd_bin_cntr";
end fifo_async_103x16_rd_bin_cntr;
architecture STRUCTURE of fifo_async_103x16_rd_bin_cntr is
signal \^i6\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^o2\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal n_0_ram_empty_fb_i_i_2 : STD_LOGIC;
signal n_0_ram_empty_fb_i_i_3 : STD_LOGIC;
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[2]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of ram_empty_fb_i_i_2 : label is "soft_lutpair9";
attribute SOFT_HLUTNM of ram_empty_fb_i_i_3 : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \rd_pntr_gc[0]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \rd_pntr_gc[2]_i_1\ : label is "soft_lutpair9";
begin
I6(3 downto 0) <= \^i6\(3 downto 0);
O2(2 downto 0) <= \^o2\(2 downto 0);
Q(3 downto 0) <= \^q\(3 downto 0);
\gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \plusOp__0\(0)
);
\gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \plusOp__0\(1)
);
\gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
O => \plusOp__0\(2)
);
\gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
O => \plusOp__0\(3)
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I3(0),
D => \^q\(0),
Q => \^o2\(0)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I3(0),
D => \^q\(1),
Q => \^o2\(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I3(0),
D => \^q\(2),
Q => \^o2\(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I3(0),
D => \^q\(3),
Q => \^i6\(3)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => E(0),
D => \plusOp__0\(0),
PRE => I3(0),
Q => \^q\(0)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I3(0),
D => \plusOp__0\(1),
Q => \^q\(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I3(0),
D => \plusOp__0\(2),
Q => \^q\(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I3(0),
D => \plusOp__0\(3),
Q => \^q\(3)
);
ram_empty_fb_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => n_0_ram_empty_fb_i_i_2,
I1 => n_0_ram_empty_fb_i_i_3,
I2 => I1,
I3 => I2,
O => O1
);
ram_empty_fb_i_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^o2\(2),
I1 => O3(2),
I2 => \^i6\(3),
I3 => O3(3),
O => n_0_ram_empty_fb_i_i_2
);
ram_empty_fb_i_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^o2\(0),
I1 => O3(0),
I2 => \^o2\(1),
I3 => O3(1),
O => n_0_ram_empty_fb_i_i_3
);
\rd_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^o2\(0),
I1 => \^o2\(1),
O => \^i6\(0)
);
\rd_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^o2\(1),
I1 => \^o2\(2),
O => \^i6\(1)
);
\rd_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^o2\(2),
I1 => \^i6\(3),
O => \^i6\(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x16_rd_fwft is
port (
empty : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
O1 : out STD_LOGIC;
O2 : out STD_LOGIC_VECTOR ( 0 to 0 );
O4 : out STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_en : in STD_LOGIC;
p_18_out : in STD_LOGIC;
O3 : in STD_LOGIC_VECTOR ( 0 to 0 );
I1 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x16_rd_fwft : entity is "rd_fwft";
end fifo_async_103x16_rd_fwft;
architecture STRUCTURE of fifo_async_103x16_rd_fwft is
signal curr_fwft_state : STD_LOGIC_VECTOR ( 0 to 0 );
signal empty_fwft_fb : STD_LOGIC;
signal empty_fwft_i0 : STD_LOGIC;
signal \n_0_gpregsm1.curr_fwft_state_reg[1]\ : STD_LOGIC;
signal next_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of empty_fwft_fb_reg : label is "no";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of empty_fwft_i_i_1 : label is "soft_lutpair4";
attribute equivalent_register_removal of empty_fwft_i_reg : label is "no";
attribute SOFT_HLUTNM of \gc0.count_d1[3]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \goreg_dm.dout_i[102]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gpr1.dout_i[102]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gpregsm1.curr_fwft_state[0]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gpregsm1.curr_fwft_state[1]_i_1\ : label is "soft_lutpair5";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[0]\ : label is "no";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[1]\ : label is "no";
begin
empty_fwft_fb_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => empty_fwft_i0,
PRE => Q(0),
Q => empty_fwft_fb
);
empty_fwft_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F540"
)
port map (
I0 => \n_0_gpregsm1.curr_fwft_state_reg[1]\,
I1 => rd_en,
I2 => curr_fwft_state(0),
I3 => empty_fwft_fb,
O => empty_fwft_i0
);
empty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => empty_fwft_i0,
PRE => Q(0),
Q => empty
);
\gc0.count_d1[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00DF"
)
port map (
I0 => \n_0_gpregsm1.curr_fwft_state_reg[1]\,
I1 => rd_en,
I2 => curr_fwft_state(0),
I3 => p_18_out,
O => O2(0)
);
\goreg_dm.dout_i[102]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D0"
)
port map (
I0 => curr_fwft_state(0),
I1 => rd_en,
I2 => \n_0_gpregsm1.curr_fwft_state_reg[1]\,
O => E(0)
);
\gpr1.dout_i[102]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00DF"
)
port map (
I0 => \n_0_gpregsm1.curr_fwft_state_reg[1]\,
I1 => rd_en,
I2 => curr_fwft_state(0),
I3 => p_18_out,
O => O4(0)
);
\gpregsm1.curr_fwft_state[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AE"
)
port map (
I0 => \n_0_gpregsm1.curr_fwft_state_reg[1]\,
I1 => curr_fwft_state(0),
I2 => rd_en,
O => next_fwft_state(0)
);
\gpregsm1.curr_fwft_state[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20FF"
)
port map (
I0 => \n_0_gpregsm1.curr_fwft_state_reg[1]\,
I1 => rd_en,
I2 => curr_fwft_state(0),
I3 => p_18_out,
O => next_fwft_state(1)
);
\gpregsm1.curr_fwft_state_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => Q(0),
D => next_fwft_state(0),
Q => curr_fwft_state(0)
);
\gpregsm1.curr_fwft_state_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => Q(0),
D => next_fwft_state(1),
Q => \n_0_gpregsm1.curr_fwft_state_reg[1]\
);
ram_empty_fb_i_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"00DF0000000000DF"
)
port map (
I0 => \n_0_gpregsm1.curr_fwft_state_reg[1]\,
I1 => rd_en,
I2 => curr_fwft_state(0),
I3 => p_18_out,
I4 => O3(0),
I5 => I1(0),
O => O1
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x16_rd_status_flags_as is
port (
p_18_out : out STD_LOGIC;
I1 : in STD_LOGIC;
rd_clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x16_rd_status_flags_as : entity is "rd_status_flags_as";
end fifo_async_103x16_rd_status_flags_as;
architecture STRUCTURE of fifo_async_103x16_rd_status_flags_as is
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
begin
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => I1,
PRE => Q(0),
Q => p_18_out
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x16_reset_blk_ramfifo is
port (
rst_d2 : out STD_LOGIC;
rst_full_gen_i : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
O1 : out STD_LOGIC_VECTOR ( 1 downto 0 );
wr_clk : in STD_LOGIC;
rst : in STD_LOGIC;
rd_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x16_reset_blk_ramfifo : entity is "reset_blk_ramfifo";
end fifo_async_103x16_reset_blk_ramfifo;
architecture STRUCTURE of fifo_async_103x16_reset_blk_ramfifo is
signal \n_0_ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\ : STD_LOGIC;
signal \n_0_ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1\ : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_asreg_d1 : STD_LOGIC;
signal rd_rst_asreg_d2 : STD_LOGIC;
signal rst_d1 : STD_LOGIC;
signal \^rst_d2\ : STD_LOGIC;
signal rst_d3 : STD_LOGIC;
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_asreg_d1 : STD_LOGIC;
signal wr_rst_asreg_d2 : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute msgon : string;
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg\ : label is std.standard.true;
attribute msgon of \ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg\ : label is "true";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.rd_rst_asreg_d2_reg\ : label is std.standard.true;
attribute msgon of \ngwrdrst.grst.g7serrst.rd_rst_asreg_d2_reg\ : label is "true";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\ : label is std.standard.true;
attribute msgon of \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\ : label is "true";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg\ : label is std.standard.true;
attribute msgon of \ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg\ : label is "true";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.wr_rst_asreg_d2_reg\ : label is std.standard.true;
attribute msgon of \ngwrdrst.grst.g7serrst.wr_rst_asreg_d2_reg\ : label is "true";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\ : label is std.standard.true;
attribute msgon of \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\ : label is "true";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
begin
rst_d2 <= \^rst_d2\;
\grstd1.grst_full.grst_f.RST_FULL_GEN_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => rst,
D => rst_d3,
Q => rst_full_gen_i
);
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => rst_d1,
PRE => rst,
Q => \^rst_d2\
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => \^rst_d2\,
PRE => rst,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => rd_rst_asreg,
Q => rd_rst_asreg_d1,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_d2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => rd_rst_asreg_d1,
Q => rd_rst_asreg_d2,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
port map (
C => rd_clk,
CE => rd_rst_asreg_d1,
D => '0',
PRE => rst,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_rst_asreg,
I1 => rd_rst_asreg_d2,
O => \n_0_ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => \n_0_ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\,
Q => Q(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => \n_0_ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\,
Q => Q(1)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => \n_0_ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\,
Q => Q(2)
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => wr_rst_asreg,
Q => wr_rst_asreg_d1,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_d2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => wr_rst_asreg_d1,
Q => wr_rst_asreg_d2,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
port map (
C => wr_clk,
CE => wr_rst_asreg_d1,
D => '0',
PRE => rst,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_rst_asreg,
I1 => wr_rst_asreg_d2,
O => \n_0_ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1\
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => \n_0_ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1\,
Q => O1(0)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => \n_0_ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1\,
Q => O1(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x16_synchronizer_ff is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
I1 : in STD_LOGIC_VECTOR ( 3 downto 0 );
rd_clk : in STD_LOGIC;
I5 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x16_synchronizer_ff : entity is "synchronizer_ff";
end fifo_async_103x16_synchronizer_ff;
architecture STRUCTURE of fifo_async_103x16_synchronizer_ff is
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \Q_reg_reg[0]\ : label is std.standard.true;
attribute msgon : string;
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[1]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[2]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[3]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I5(0),
D => I1(0),
Q => Q(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I5(0),
D => I1(1),
Q => Q(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I5(0),
D => I1(2),
Q => Q(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I5(0),
D => I1(3),
Q => Q(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x16_synchronizer_ff_0 is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
I1 : in STD_LOGIC_VECTOR ( 3 downto 0 );
wr_clk : in STD_LOGIC;
I4 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x16_synchronizer_ff_0 : entity is "synchronizer_ff";
end fifo_async_103x16_synchronizer_ff_0;
architecture STRUCTURE of fifo_async_103x16_synchronizer_ff_0 is
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \Q_reg_reg[0]\ : label is std.standard.true;
attribute msgon : string;
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[1]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[2]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[3]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I4(0),
D => I1(0),
Q => Q(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I4(0),
D => I1(1),
Q => Q(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I4(0),
D => I1(2),
Q => Q(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I4(0),
D => I1(3),
Q => Q(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x16_synchronizer_ff_1 is
port (
p_0_in : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
rd_clk : in STD_LOGIC;
I5 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x16_synchronizer_ff_1 : entity is "synchronizer_ff";
end fifo_async_103x16_synchronizer_ff_1;
architecture STRUCTURE of fifo_async_103x16_synchronizer_ff_1 is
signal \n_0_Q_reg_reg[0]\ : STD_LOGIC;
signal \n_0_Q_reg_reg[1]\ : STD_LOGIC;
signal \n_0_Q_reg_reg[2]\ : STD_LOGIC;
signal \^p_0_in\ : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \Q_reg_reg[0]\ : label is std.standard.true;
attribute msgon : string;
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[1]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[2]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[3]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[3]\ : label is "true";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \wr_pntr_bin[0]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \wr_pntr_bin[1]_i_1\ : label is "soft_lutpair0";
begin
p_0_in(3 downto 0) <= \^p_0_in\(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I5(0),
D => D(0),
Q => \n_0_Q_reg_reg[0]\
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I5(0),
D => D(1),
Q => \n_0_Q_reg_reg[1]\
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I5(0),
D => D(2),
Q => \n_0_Q_reg_reg[2]\
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I5(0),
D => D(3),
Q => \^p_0_in\(3)
);
\wr_pntr_bin[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \n_0_Q_reg_reg[1]\,
I1 => \n_0_Q_reg_reg[0]\,
I2 => \^p_0_in\(3),
I3 => \n_0_Q_reg_reg[2]\,
O => \^p_0_in\(0)
);
\wr_pntr_bin[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \n_0_Q_reg_reg[2]\,
I1 => \n_0_Q_reg_reg[1]\,
I2 => \^p_0_in\(3),
O => \^p_0_in\(1)
);
\wr_pntr_bin[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \n_0_Q_reg_reg[2]\,
I1 => \^p_0_in\(3),
O => \^p_0_in\(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x16_synchronizer_ff_2 is
port (
Q : out STD_LOGIC_VECTOR ( 0 to 0 );
O1 : out STD_LOGIC_VECTOR ( 2 downto 0 );
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
wr_clk : in STD_LOGIC;
I4 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x16_synchronizer_ff_2 : entity is "synchronizer_ff";
end fifo_async_103x16_synchronizer_ff_2;
architecture STRUCTURE of fifo_async_103x16_synchronizer_ff_2 is
signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \n_0_Q_reg_reg[0]\ : STD_LOGIC;
signal \n_0_Q_reg_reg[1]\ : STD_LOGIC;
signal \n_0_Q_reg_reg[2]\ : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \Q_reg_reg[0]\ : label is std.standard.true;
attribute msgon : string;
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[1]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[2]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[3]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[3]\ : label is "true";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \rd_pntr_bin[0]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \rd_pntr_bin[1]_i_1\ : label is "soft_lutpair1";
begin
Q(0) <= \^q\(0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I4(0),
D => D(0),
Q => \n_0_Q_reg_reg[0]\
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I4(0),
D => D(1),
Q => \n_0_Q_reg_reg[1]\
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I4(0),
D => D(2),
Q => \n_0_Q_reg_reg[2]\
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I4(0),
D => D(3),
Q => \^q\(0)
);
\rd_pntr_bin[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \n_0_Q_reg_reg[1]\,
I1 => \n_0_Q_reg_reg[0]\,
I2 => \^q\(0),
I3 => \n_0_Q_reg_reg[2]\,
O => O1(0)
);
\rd_pntr_bin[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \n_0_Q_reg_reg[2]\,
I1 => \n_0_Q_reg_reg[1]\,
I2 => \^q\(0),
O => O1(1)
);
\rd_pntr_bin[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \n_0_Q_reg_reg[2]\,
I1 => \^q\(0),
O => O1(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x16_wr_bin_cntr is
port (
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
O2 : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 1 downto 0 );
ram_full_i : out STD_LOGIC;
O3 : out STD_LOGIC_VECTOR ( 3 downto 0 );
wr_en : in STD_LOGIC;
p_1_out : in STD_LOGIC;
O1 : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
I1 : in STD_LOGIC;
I2 : in STD_LOGIC;
rst_full_gen_i : in STD_LOGIC;
wr_clk : in STD_LOGIC;
I3 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x16_wr_bin_cntr : entity is "wr_bin_cntr";
end fifo_async_103x16_wr_bin_cntr;
architecture STRUCTURE of fifo_async_103x16_wr_bin_cntr is
signal \^o2\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \n_0_gdiff.diff_pntr_pad[4]_i_2\ : STD_LOGIC;
signal \n_0_gdiff.diff_pntr_pad[4]_i_3\ : STD_LOGIC;
signal n_0_ram_full_i_i_2 : STD_LOGIC;
signal n_0_ram_full_i_i_3 : STD_LOGIC;
signal p_8_out : STD_LOGIC_VECTOR ( 3 to 3 );
signal \plusOp__1\ : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gdiff.diff_pntr_pad[4]_i_2\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \gic0.gc0.count[2]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \gic0.gc0.count[3]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of ram_full_i_i_2 : label is "soft_lutpair11";
begin
O2(3 downto 0) <= \^o2\(3 downto 0);
Q(2 downto 0) <= \^q\(2 downto 0);
\gdiff.diff_pntr_pad[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9699999966669699"
)
port map (
I0 => \^q\(1),
I1 => O1(1),
I2 => p_1_out,
I3 => wr_en,
I4 => \^q\(0),
I5 => O1(0),
O => D(0)
);
\gdiff.diff_pntr_pad[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9999669969996669"
)
port map (
I0 => p_8_out(3),
I1 => O1(3),
I2 => \n_0_gdiff.diff_pntr_pad[4]_i_2\,
I3 => \^q\(2),
I4 => O1(2),
I5 => \n_0_gdiff.diff_pntr_pad[4]_i_3\,
O => D(1)
);
\gdiff.diff_pntr_pad[4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^q\(1),
I1 => O1(1),
O => \n_0_gdiff.diff_pntr_pad[4]_i_2\
);
\gdiff.diff_pntr_pad[4]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD0DFF0F0000DD0D"
)
port map (
I0 => wr_en,
I1 => p_1_out,
I2 => \^q\(1),
I3 => O1(1),
I4 => \^q\(0),
I5 => O1(0),
O => \n_0_gdiff.diff_pntr_pad[4]_i_3\
);
\gic0.gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^o2\(0),
O => \plusOp__1\(0)
);
\gic0.gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^o2\(0),
I1 => \^o2\(1),
O => \plusOp__1\(1)
);
\gic0.gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \^o2\(2),
I1 => \^o2\(1),
I2 => \^o2\(0),
O => \plusOp__1\(2)
);
\gic0.gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \^o2\(3),
I1 => \^o2\(0),
I2 => \^o2\(1),
I3 => \^o2\(2),
O => \plusOp__1\(3)
);
\gic0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => E(0),
D => \^o2\(0),
PRE => I3(0),
Q => \^q\(0)
);
\gic0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => I3(0),
D => \^o2\(1),
Q => \^q\(1)
);
\gic0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => I3(0),
D => \^o2\(2),
Q => \^q\(2)
);
\gic0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => I3(0),
D => \^o2\(3),
Q => p_8_out(3)
);
\gic0.gc0.count_d2_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => I3(0),
D => \^q\(0),
Q => O3(0)
);
\gic0.gc0.count_d2_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => I3(0),
D => \^q\(1),
Q => O3(1)
);
\gic0.gc0.count_d2_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => I3(0),
D => \^q\(2),
Q => O3(2)
);
\gic0.gc0.count_d2_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => I3(0),
D => p_8_out(3),
Q => O3(3)
);
\gic0.gc0.count_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => I3(0),
D => \plusOp__1\(0),
Q => \^o2\(0)
);
\gic0.gc0.count_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => E(0),
D => \plusOp__1\(1),
PRE => I3(0),
Q => \^o2\(1)
);
\gic0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => I3(0),
D => \plusOp__1\(2),
Q => \^o2\(2)
);
\gic0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => I3(0),
D => \plusOp__1\(3),
Q => \^o2\(3)
);
ram_full_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000111111F1"
)
port map (
I0 => n_0_ram_full_i_i_2,
I1 => n_0_ram_full_i_i_3,
I2 => E(0),
I3 => I1,
I4 => I2,
I5 => rst_full_gen_i,
O => ram_full_i
);
ram_full_i_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => \^q\(1),
I1 => O1(1),
I2 => \^q\(2),
I3 => O1(2),
O => n_0_ram_full_i_i_2
);
ram_full_i_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => p_8_out(3),
I1 => O1(3),
I2 => O1(0),
I3 => \^q\(0),
O => n_0_ram_full_i_i_3
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x16_wr_pf_as is
port (
prog_full : out STD_LOGIC;
wr_clk : in STD_LOGIC;
rst_d2 : in STD_LOGIC;
rst_full_gen_i : in STD_LOGIC;
p_1_out : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 2 downto 0 );
I3 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x16_wr_pf_as : entity is "wr_pf_as";
end fifo_async_103x16_wr_pf_as;
architecture STRUCTURE of fifo_async_103x16_wr_pf_as is
signal diff_pntr : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \n_0_gpf1.prog_full_i_i_1\ : STD_LOGIC;
signal \^prog_full\ : STD_LOGIC;
begin
prog_full <= \^prog_full\;
\gdiff.diff_pntr_pad_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I3(0),
D => D(0),
Q => diff_pntr(1)
);
\gdiff.diff_pntr_pad_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I3(0),
D => D(1),
Q => diff_pntr(2)
);
\gdiff.diff_pntr_pad_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I3(0),
D => D(2),
Q => diff_pntr(3)
);
\gpf1.prog_full_i_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00FF00E0000000E0"
)
port map (
I0 => diff_pntr(1),
I1 => diff_pntr(2),
I2 => diff_pntr(3),
I3 => rst_full_gen_i,
I4 => p_1_out,
I5 => \^prog_full\,
O => \n_0_gpf1.prog_full_i_i_1\
);
\gpf1.prog_full_i_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => \n_0_gpf1.prog_full_i_i_1\,
PRE => rst_d2,
Q => \^prog_full\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x16_wr_status_flags_as is
port (
full : out STD_LOGIC;
p_1_out : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_full_i : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rst_d2 : in STD_LOGIC;
wr_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x16_wr_status_flags_as : entity is "wr_status_flags_as";
end fifo_async_103x16_wr_status_flags_as;
architecture STRUCTURE of fifo_async_103x16_wr_status_flags_as is
signal \^p_1_out\ : STD_LOGIC;
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
p_1_out <= \^p_1_out\;
\gic0.gc0.count_d1[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => \^p_1_out\,
O => E(0)
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => ram_full_i,
PRE => rst_d2,
Q => \^p_1_out\
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => ram_full_i,
PRE => rst_d2,
Q => full
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x16_clk_x_pntrs is
port (
D : out STD_LOGIC_VECTOR ( 0 to 0 );
O1 : out STD_LOGIC_VECTOR ( 3 downto 0 );
O2 : out STD_LOGIC;
O3 : out STD_LOGIC_VECTOR ( 3 downto 0 );
O4 : out STD_LOGIC;
O5 : out STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
I1 : in STD_LOGIC_VECTOR ( 2 downto 0 );
I2 : in STD_LOGIC_VECTOR ( 3 downto 0 );
I3 : in STD_LOGIC_VECTOR ( 3 downto 0 );
wr_clk : in STD_LOGIC;
I4 : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC;
I5 : in STD_LOGIC_VECTOR ( 0 to 0 );
I6 : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x16_clk_x_pntrs : entity is "clk_x_pntrs";
end fifo_async_103x16_clk_x_pntrs;
architecture STRUCTURE of fifo_async_103x16_clk_x_pntrs is
signal \^o1\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^o3\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \n_0_gdiff.diff_pntr_pad[3]_i_2\ : STD_LOGIC;
signal \n_0_gsync_stage[1].rd_stg_inst\ : STD_LOGIC;
signal \n_0_gsync_stage[1].wr_stg_inst\ : STD_LOGIC;
signal \n_0_gsync_stage[2].wr_stg_inst\ : STD_LOGIC;
signal \n_1_gsync_stage[1].rd_stg_inst\ : STD_LOGIC;
signal \n_1_gsync_stage[1].wr_stg_inst\ : STD_LOGIC;
signal \n_1_gsync_stage[2].wr_stg_inst\ : STD_LOGIC;
signal \n_2_gsync_stage[1].rd_stg_inst\ : STD_LOGIC;
signal \n_2_gsync_stage[1].wr_stg_inst\ : STD_LOGIC;
signal \n_2_gsync_stage[2].wr_stg_inst\ : STD_LOGIC;
signal \n_3_gsync_stage[1].rd_stg_inst\ : STD_LOGIC;
signal \n_3_gsync_stage[1].wr_stg_inst\ : STD_LOGIC;
signal \n_3_gsync_stage[2].wr_stg_inst\ : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_0_in2_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rd_pntr_gc : STD_LOGIC_VECTOR ( 3 downto 0 );
signal wr_pntr_gc : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gdiff.diff_pntr_pad[3]_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of ram_full_i_i_5 : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \wr_pntr_gc[0]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \wr_pntr_gc[1]_i_1\ : label is "soft_lutpair3";
begin
O1(3 downto 0) <= \^o1\(3 downto 0);
O3(3 downto 0) <= \^o3\(3 downto 0);
\gdiff.diff_pntr_pad[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9A5959599A9A9A59"
)
port map (
I0 => \n_0_gdiff.diff_pntr_pad[3]_i_2\,
I1 => Q(1),
I2 => \^o1\(1),
I3 => E(0),
I4 => Q(0),
I5 => \^o1\(0),
O => D(0)
);
\gdiff.diff_pntr_pad[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^o1\(2),
I1 => Q(2),
O => \n_0_gdiff.diff_pntr_pad[3]_i_2\
);
\gsync_stage[1].rd_stg_inst\: entity work.fifo_async_103x16_synchronizer_ff
port map (
I1(3 downto 0) => wr_pntr_gc(3 downto 0),
I5(0) => I5(0),
Q(3) => \n_0_gsync_stage[1].rd_stg_inst\,
Q(2) => \n_1_gsync_stage[1].rd_stg_inst\,
Q(1) => \n_2_gsync_stage[1].rd_stg_inst\,
Q(0) => \n_3_gsync_stage[1].rd_stg_inst\,
rd_clk => rd_clk
);
\gsync_stage[1].wr_stg_inst\: entity work.fifo_async_103x16_synchronizer_ff_0
port map (
I1(3 downto 0) => rd_pntr_gc(3 downto 0),
I4(0) => I4(0),
Q(3) => \n_0_gsync_stage[1].wr_stg_inst\,
Q(2) => \n_1_gsync_stage[1].wr_stg_inst\,
Q(1) => \n_2_gsync_stage[1].wr_stg_inst\,
Q(0) => \n_3_gsync_stage[1].wr_stg_inst\,
wr_clk => wr_clk
);
\gsync_stage[2].rd_stg_inst\: entity work.fifo_async_103x16_synchronizer_ff_1
port map (
D(3) => \n_0_gsync_stage[1].rd_stg_inst\,
D(2) => \n_1_gsync_stage[1].rd_stg_inst\,
D(1) => \n_2_gsync_stage[1].rd_stg_inst\,
D(0) => \n_3_gsync_stage[1].rd_stg_inst\,
I5(0) => I5(0),
p_0_in(3 downto 0) => p_0_in(3 downto 0),
rd_clk => rd_clk
);
\gsync_stage[2].wr_stg_inst\: entity work.fifo_async_103x16_synchronizer_ff_2
port map (
D(3) => \n_0_gsync_stage[1].wr_stg_inst\,
D(2) => \n_1_gsync_stage[1].wr_stg_inst\,
D(1) => \n_2_gsync_stage[1].wr_stg_inst\,
D(0) => \n_3_gsync_stage[1].wr_stg_inst\,
I4(0) => I4(0),
O1(2) => \n_1_gsync_stage[2].wr_stg_inst\,
O1(1) => \n_2_gsync_stage[2].wr_stg_inst\,
O1(0) => \n_3_gsync_stage[2].wr_stg_inst\,
Q(0) => \n_0_gsync_stage[2].wr_stg_inst\,
wr_clk => wr_clk
);
ram_empty_fb_i_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^o3\(2),
I1 => I1(2),
I2 => \^o3\(1),
I3 => I1(1),
I4 => I1(0),
I5 => \^o3\(0),
O => O2
);
ram_full_i_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => \^o1\(1),
I1 => I2(1),
I2 => \^o1\(0),
I3 => I2(0),
O => O4
);
ram_full_i_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => \^o1\(3),
I1 => I2(3),
I2 => \^o1\(2),
I3 => I2(2),
O => O5
);
\rd_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I4(0),
D => \n_3_gsync_stage[2].wr_stg_inst\,
Q => \^o1\(0)
);
\rd_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I4(0),
D => \n_2_gsync_stage[2].wr_stg_inst\,
Q => \^o1\(1)
);
\rd_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I4(0),
D => \n_1_gsync_stage[2].wr_stg_inst\,
Q => \^o1\(2)
);
\rd_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I4(0),
D => \n_0_gsync_stage[2].wr_stg_inst\,
Q => \^o1\(3)
);
\rd_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I5(0),
D => I6(0),
Q => rd_pntr_gc(0)
);
\rd_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I5(0),
D => I6(1),
Q => rd_pntr_gc(1)
);
\rd_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I5(0),
D => I6(2),
Q => rd_pntr_gc(2)
);
\rd_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I5(0),
D => I6(3),
Q => rd_pntr_gc(3)
);
\wr_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I5(0),
D => p_0_in(0),
Q => \^o3\(0)
);
\wr_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I5(0),
D => p_0_in(1),
Q => \^o3\(1)
);
\wr_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I5(0),
D => p_0_in(2),
Q => \^o3\(2)
);
\wr_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I5(0),
D => p_0_in(3),
Q => \^o3\(3)
);
\wr_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => I3(0),
I1 => I3(1),
O => p_0_in2_out(0)
);
\wr_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => I3(1),
I1 => I3(2),
O => p_0_in2_out(1)
);
\wr_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => I3(2),
I1 => I3(3),
O => p_0_in2_out(2)
);
\wr_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I4(0),
D => p_0_in2_out(0),
Q => wr_pntr_gc(0)
);
\wr_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I4(0),
D => p_0_in2_out(1),
Q => wr_pntr_gc(1)
);
\wr_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I4(0),
D => p_0_in2_out(2),
Q => wr_pntr_gc(2)
);
\wr_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I4(0),
D => I3(3),
Q => wr_pntr_gc(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x16_memory is
port (
dout : out STD_LOGIC_VECTOR ( 102 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_clk : in STD_LOGIC;
I1 : in STD_LOGIC_VECTOR ( 0 to 0 );
din : in STD_LOGIC_VECTOR ( 102 downto 0 );
ADDRA : in STD_LOGIC_VECTOR ( 3 downto 0 );
O3 : in STD_LOGIC_VECTOR ( 3 downto 0 );
I2 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x16_memory : entity is "memory";
end fifo_async_103x16_memory;
architecture STRUCTURE of fifo_async_103x16_memory is
signal p_0_out : STD_LOGIC_VECTOR ( 102 downto 0 );
begin
\gdm.dm\: entity work.fifo_async_103x16_dmem
port map (
ADDRA(3 downto 0) => ADDRA(3 downto 0),
E(0) => E(0),
I1(0) => Q(0),
I2(0) => I1(0),
O3(3 downto 0) => O3(3 downto 0),
Q(102 downto 0) => p_0_out(102 downto 0),
din(102 downto 0) => din(102 downto 0),
rd_clk => rd_clk,
wr_clk => wr_clk
);
\goreg_dm.dout_i_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(0),
Q => dout(0)
);
\goreg_dm.dout_i_reg[100]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(100),
Q => dout(100)
);
\goreg_dm.dout_i_reg[101]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(101),
Q => dout(101)
);
\goreg_dm.dout_i_reg[102]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(102),
Q => dout(102)
);
\goreg_dm.dout_i_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(10),
Q => dout(10)
);
\goreg_dm.dout_i_reg[11]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(11),
Q => dout(11)
);
\goreg_dm.dout_i_reg[12]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(12),
Q => dout(12)
);
\goreg_dm.dout_i_reg[13]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(13),
Q => dout(13)
);
\goreg_dm.dout_i_reg[14]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(14),
Q => dout(14)
);
\goreg_dm.dout_i_reg[15]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(15),
Q => dout(15)
);
\goreg_dm.dout_i_reg[16]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(16),
Q => dout(16)
);
\goreg_dm.dout_i_reg[17]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(17),
Q => dout(17)
);
\goreg_dm.dout_i_reg[18]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(18),
Q => dout(18)
);
\goreg_dm.dout_i_reg[19]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(19),
Q => dout(19)
);
\goreg_dm.dout_i_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(1),
Q => dout(1)
);
\goreg_dm.dout_i_reg[20]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(20),
Q => dout(20)
);
\goreg_dm.dout_i_reg[21]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(21),
Q => dout(21)
);
\goreg_dm.dout_i_reg[22]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(22),
Q => dout(22)
);
\goreg_dm.dout_i_reg[23]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(23),
Q => dout(23)
);
\goreg_dm.dout_i_reg[24]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(24),
Q => dout(24)
);
\goreg_dm.dout_i_reg[25]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(25),
Q => dout(25)
);
\goreg_dm.dout_i_reg[26]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(26),
Q => dout(26)
);
\goreg_dm.dout_i_reg[27]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(27),
Q => dout(27)
);
\goreg_dm.dout_i_reg[28]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(28),
Q => dout(28)
);
\goreg_dm.dout_i_reg[29]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(29),
Q => dout(29)
);
\goreg_dm.dout_i_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(2),
Q => dout(2)
);
\goreg_dm.dout_i_reg[30]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(30),
Q => dout(30)
);
\goreg_dm.dout_i_reg[31]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(31),
Q => dout(31)
);
\goreg_dm.dout_i_reg[32]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(32),
Q => dout(32)
);
\goreg_dm.dout_i_reg[33]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(33),
Q => dout(33)
);
\goreg_dm.dout_i_reg[34]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(34),
Q => dout(34)
);
\goreg_dm.dout_i_reg[35]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(35),
Q => dout(35)
);
\goreg_dm.dout_i_reg[36]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(36),
Q => dout(36)
);
\goreg_dm.dout_i_reg[37]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(37),
Q => dout(37)
);
\goreg_dm.dout_i_reg[38]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(38),
Q => dout(38)
);
\goreg_dm.dout_i_reg[39]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(39),
Q => dout(39)
);
\goreg_dm.dout_i_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(3),
Q => dout(3)
);
\goreg_dm.dout_i_reg[40]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(40),
Q => dout(40)
);
\goreg_dm.dout_i_reg[41]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(41),
Q => dout(41)
);
\goreg_dm.dout_i_reg[42]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(42),
Q => dout(42)
);
\goreg_dm.dout_i_reg[43]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(43),
Q => dout(43)
);
\goreg_dm.dout_i_reg[44]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(44),
Q => dout(44)
);
\goreg_dm.dout_i_reg[45]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(45),
Q => dout(45)
);
\goreg_dm.dout_i_reg[46]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(46),
Q => dout(46)
);
\goreg_dm.dout_i_reg[47]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(47),
Q => dout(47)
);
\goreg_dm.dout_i_reg[48]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(48),
Q => dout(48)
);
\goreg_dm.dout_i_reg[49]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(49),
Q => dout(49)
);
\goreg_dm.dout_i_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(4),
Q => dout(4)
);
\goreg_dm.dout_i_reg[50]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(50),
Q => dout(50)
);
\goreg_dm.dout_i_reg[51]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(51),
Q => dout(51)
);
\goreg_dm.dout_i_reg[52]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(52),
Q => dout(52)
);
\goreg_dm.dout_i_reg[53]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(53),
Q => dout(53)
);
\goreg_dm.dout_i_reg[54]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(54),
Q => dout(54)
);
\goreg_dm.dout_i_reg[55]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(55),
Q => dout(55)
);
\goreg_dm.dout_i_reg[56]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(56),
Q => dout(56)
);
\goreg_dm.dout_i_reg[57]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(57),
Q => dout(57)
);
\goreg_dm.dout_i_reg[58]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(58),
Q => dout(58)
);
\goreg_dm.dout_i_reg[59]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(59),
Q => dout(59)
);
\goreg_dm.dout_i_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(5),
Q => dout(5)
);
\goreg_dm.dout_i_reg[60]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(60),
Q => dout(60)
);
\goreg_dm.dout_i_reg[61]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(61),
Q => dout(61)
);
\goreg_dm.dout_i_reg[62]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(62),
Q => dout(62)
);
\goreg_dm.dout_i_reg[63]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(63),
Q => dout(63)
);
\goreg_dm.dout_i_reg[64]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(64),
Q => dout(64)
);
\goreg_dm.dout_i_reg[65]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(65),
Q => dout(65)
);
\goreg_dm.dout_i_reg[66]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(66),
Q => dout(66)
);
\goreg_dm.dout_i_reg[67]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(67),
Q => dout(67)
);
\goreg_dm.dout_i_reg[68]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(68),
Q => dout(68)
);
\goreg_dm.dout_i_reg[69]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(69),
Q => dout(69)
);
\goreg_dm.dout_i_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(6),
Q => dout(6)
);
\goreg_dm.dout_i_reg[70]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(70),
Q => dout(70)
);
\goreg_dm.dout_i_reg[71]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(71),
Q => dout(71)
);
\goreg_dm.dout_i_reg[72]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(72),
Q => dout(72)
);
\goreg_dm.dout_i_reg[73]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(73),
Q => dout(73)
);
\goreg_dm.dout_i_reg[74]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(74),
Q => dout(74)
);
\goreg_dm.dout_i_reg[75]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(75),
Q => dout(75)
);
\goreg_dm.dout_i_reg[76]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(76),
Q => dout(76)
);
\goreg_dm.dout_i_reg[77]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(77),
Q => dout(77)
);
\goreg_dm.dout_i_reg[78]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(78),
Q => dout(78)
);
\goreg_dm.dout_i_reg[79]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(79),
Q => dout(79)
);
\goreg_dm.dout_i_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(7),
Q => dout(7)
);
\goreg_dm.dout_i_reg[80]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(80),
Q => dout(80)
);
\goreg_dm.dout_i_reg[81]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(81),
Q => dout(81)
);
\goreg_dm.dout_i_reg[82]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(82),
Q => dout(82)
);
\goreg_dm.dout_i_reg[83]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(83),
Q => dout(83)
);
\goreg_dm.dout_i_reg[84]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(84),
Q => dout(84)
);
\goreg_dm.dout_i_reg[85]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(85),
Q => dout(85)
);
\goreg_dm.dout_i_reg[86]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(86),
Q => dout(86)
);
\goreg_dm.dout_i_reg[87]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(87),
Q => dout(87)
);
\goreg_dm.dout_i_reg[88]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(88),
Q => dout(88)
);
\goreg_dm.dout_i_reg[89]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(89),
Q => dout(89)
);
\goreg_dm.dout_i_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(8),
Q => dout(8)
);
\goreg_dm.dout_i_reg[90]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(90),
Q => dout(90)
);
\goreg_dm.dout_i_reg[91]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(91),
Q => dout(91)
);
\goreg_dm.dout_i_reg[92]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(92),
Q => dout(92)
);
\goreg_dm.dout_i_reg[93]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(93),
Q => dout(93)
);
\goreg_dm.dout_i_reg[94]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(94),
Q => dout(94)
);
\goreg_dm.dout_i_reg[95]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(95),
Q => dout(95)
);
\goreg_dm.dout_i_reg[96]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(96),
Q => dout(96)
);
\goreg_dm.dout_i_reg[97]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(97),
Q => dout(97)
);
\goreg_dm.dout_i_reg[98]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(98),
Q => dout(98)
);
\goreg_dm.dout_i_reg[99]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(99),
Q => dout(99)
);
\goreg_dm.dout_i_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(9),
Q => dout(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x16_rd_logic is
port (
empty : out STD_LOGIC;
O1 : out STD_LOGIC_VECTOR ( 2 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
O2 : out STD_LOGIC_VECTOR ( 0 to 0 );
I6 : out STD_LOGIC_VECTOR ( 3 downto 0 );
O4 : out STD_LOGIC_VECTOR ( 2 downto 0 );
rd_clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_en : in STD_LOGIC;
I1 : in STD_LOGIC;
O3 : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x16_rd_logic : entity is "rd_logic";
end fifo_async_103x16_rd_logic;
architecture STRUCTURE of fifo_async_103x16_rd_logic is
signal \n_2_gr1.rfwft\ : STD_LOGIC;
signal n_4_rpntr : STD_LOGIC;
signal p_14_out : STD_LOGIC;
signal p_18_out : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 3 to 3 );
begin
\gr1.rfwft\: entity work.fifo_async_103x16_rd_fwft
port map (
E(0) => E(0),
I1(0) => rd_pntr_plus1(3),
O1 => \n_2_gr1.rfwft\,
O2(0) => p_14_out,
O3(0) => O3(3),
O4(0) => O2(0),
Q(0) => Q(0),
empty => empty,
p_18_out => p_18_out,
rd_clk => rd_clk,
rd_en => rd_en
);
\gras.rsts\: entity work.fifo_async_103x16_rd_status_flags_as
port map (
I1 => n_4_rpntr,
Q(0) => Q(0),
p_18_out => p_18_out,
rd_clk => rd_clk
);
rpntr: entity work.fifo_async_103x16_rd_bin_cntr
port map (
E(0) => p_14_out,
I1 => I1,
I2 => \n_2_gr1.rfwft\,
I3(0) => Q(0),
I6(3 downto 0) => I6(3 downto 0),
O1 => n_4_rpntr,
O2(2 downto 0) => O4(2 downto 0),
O3(3 downto 0) => O3(3 downto 0),
Q(3) => rd_pntr_plus1(3),
Q(2 downto 0) => O1(2 downto 0),
rd_clk => rd_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x16_wr_logic is
port (
full : out STD_LOGIC;
prog_full : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
O2 : out STD_LOGIC_VECTOR ( 3 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
O3 : out STD_LOGIC_VECTOR ( 3 downto 0 );
wr_clk : in STD_LOGIC;
rst_d2 : in STD_LOGIC;
wr_en : in STD_LOGIC;
O1 : in STD_LOGIC_VECTOR ( 3 downto 0 );
I1 : in STD_LOGIC;
I2 : in STD_LOGIC;
rst_full_gen_i : in STD_LOGIC;
I3 : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x16_wr_logic : entity is "wr_logic";
end fifo_async_103x16_wr_logic;
architecture STRUCTURE of fifo_async_103x16_wr_logic is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal p_1_out : STD_LOGIC;
signal plusOp : STD_LOGIC_VECTOR ( 4 downto 2 );
signal ram_full_i : STD_LOGIC;
begin
E(0) <= \^e\(0);
\gwas.gpf.wrpf\: entity work.fifo_async_103x16_wr_pf_as
port map (
D(2) => plusOp(4),
D(1) => D(0),
D(0) => plusOp(2),
I3(0) => I3(0),
p_1_out => p_1_out,
prog_full => prog_full,
rst_d2 => rst_d2,
rst_full_gen_i => rst_full_gen_i,
wr_clk => wr_clk
);
\gwas.wsts\: entity work.fifo_async_103x16_wr_status_flags_as
port map (
E(0) => \^e\(0),
full => full,
p_1_out => p_1_out,
ram_full_i => ram_full_i,
rst_d2 => rst_d2,
wr_clk => wr_clk,
wr_en => wr_en
);
wpntr: entity work.fifo_async_103x16_wr_bin_cntr
port map (
D(1) => plusOp(4),
D(0) => plusOp(2),
E(0) => \^e\(0),
I1 => I1,
I2 => I2,
I3(0) => I3(0),
O1(3 downto 0) => O1(3 downto 0),
O2(3 downto 0) => O2(3 downto 0),
O3(3 downto 0) => O3(3 downto 0),
Q(2 downto 0) => Q(2 downto 0),
p_1_out => p_1_out,
ram_full_i => ram_full_i,
rst_full_gen_i => rst_full_gen_i,
wr_clk => wr_clk,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x16_fifo_generator_ramfifo is
port (
dout : out STD_LOGIC_VECTOR ( 102 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
prog_full : out STD_LOGIC;
wr_en : in STD_LOGIC;
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 102 downto 0 );
rd_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x16_fifo_generator_ramfifo : entity is "fifo_generator_ramfifo";
end fifo_async_103x16_fifo_generator_ramfifo;
architecture STRUCTURE of fifo_async_103x16_fifo_generator_ramfifo is
signal RD_RST : STD_LOGIC;
signal \^rst\ : STD_LOGIC;
signal WR_RST : STD_LOGIC;
signal \n_0_gntv_or_sync_fifo.gcx.clkx\ : STD_LOGIC;
signal \n_10_gntv_or_sync_fifo.gcx.clkx\ : STD_LOGIC;
signal \n_11_gntv_or_sync_fifo.gcx.clkx\ : STD_LOGIC;
signal n_2_rstblk : STD_LOGIC;
signal \n_5_gntv_or_sync_fifo.gcx.clkx\ : STD_LOGIC;
signal \n_7_gntv_or_sync_fifo.gl0.rd\ : STD_LOGIC;
signal \n_8_gntv_or_sync_fifo.gl0.rd\ : STD_LOGIC;
signal \n_9_gntv_or_sync_fifo.gl0.rd\ : STD_LOGIC;
signal p_0_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_15_out : STD_LOGIC;
signal p_1_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_20_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_3_out : STD_LOGIC;
signal p_8_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_9_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ram_rd_en_i : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rd_rst_i : STD_LOGIC_VECTOR ( 0 to 0 );
signal rst_d2 : STD_LOGIC;
signal rst_full_gen_i : STD_LOGIC;
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
\gntv_or_sync_fifo.gcx.clkx\: entity work.fifo_async_103x16_clk_x_pntrs
port map (
D(0) => \n_0_gntv_or_sync_fifo.gcx.clkx\,
E(0) => p_3_out,
I1(2 downto 0) => rd_pntr_plus1(2 downto 0),
I2(3 downto 0) => wr_pntr_plus2(3 downto 0),
I3(3 downto 0) => p_9_out(3 downto 0),
I4(0) => \^rst\,
I5(0) => RD_RST,
I6(3) => p_20_out(3),
I6(2) => \n_7_gntv_or_sync_fifo.gl0.rd\,
I6(1) => \n_8_gntv_or_sync_fifo.gl0.rd\,
I6(0) => \n_9_gntv_or_sync_fifo.gl0.rd\,
O1(3 downto 0) => p_0_out(3 downto 0),
O2 => \n_5_gntv_or_sync_fifo.gcx.clkx\,
O3(3 downto 0) => p_1_out(3 downto 0),
O4 => \n_10_gntv_or_sync_fifo.gcx.clkx\,
O5 => \n_11_gntv_or_sync_fifo.gcx.clkx\,
Q(2 downto 0) => p_8_out(2 downto 0),
rd_clk => rd_clk,
wr_clk => wr_clk
);
\gntv_or_sync_fifo.gl0.rd\: entity work.fifo_async_103x16_rd_logic
port map (
E(0) => p_15_out,
I1 => \n_5_gntv_or_sync_fifo.gcx.clkx\,
I6(3) => p_20_out(3),
I6(2) => \n_7_gntv_or_sync_fifo.gl0.rd\,
I6(1) => \n_8_gntv_or_sync_fifo.gl0.rd\,
I6(0) => \n_9_gntv_or_sync_fifo.gl0.rd\,
O1(2 downto 0) => rd_pntr_plus1(2 downto 0),
O2(0) => ram_rd_en_i,
O3(3 downto 0) => p_1_out(3 downto 0),
O4(2 downto 0) => p_20_out(2 downto 0),
Q(0) => n_2_rstblk,
empty => empty,
rd_clk => rd_clk,
rd_en => rd_en
);
\gntv_or_sync_fifo.gl0.wr\: entity work.fifo_async_103x16_wr_logic
port map (
D(0) => \n_0_gntv_or_sync_fifo.gcx.clkx\,
E(0) => p_3_out,
I1 => \n_10_gntv_or_sync_fifo.gcx.clkx\,
I2 => \n_11_gntv_or_sync_fifo.gcx.clkx\,
I3(0) => WR_RST,
O1(3 downto 0) => p_0_out(3 downto 0),
O2(3 downto 0) => wr_pntr_plus2(3 downto 0),
O3(3 downto 0) => p_9_out(3 downto 0),
Q(2 downto 0) => p_8_out(2 downto 0),
full => full,
prog_full => prog_full,
rst_d2 => rst_d2,
rst_full_gen_i => rst_full_gen_i,
wr_clk => wr_clk,
wr_en => wr_en
);
\gntv_or_sync_fifo.mem\: entity work.fifo_async_103x16_memory
port map (
ADDRA(3 downto 0) => p_20_out(3 downto 0),
E(0) => ram_rd_en_i,
I1(0) => p_3_out,
I2(0) => p_15_out,
O3(3 downto 0) => p_9_out(3 downto 0),
Q(0) => rd_rst_i(0),
din(102 downto 0) => din(102 downto 0),
dout(102 downto 0) => dout(102 downto 0),
rd_clk => rd_clk,
wr_clk => wr_clk
);
rstblk: entity work.fifo_async_103x16_reset_blk_ramfifo
port map (
O1(1) => WR_RST,
O1(0) => \^rst\,
Q(2) => n_2_rstblk,
Q(1) => RD_RST,
Q(0) => rd_rst_i(0),
rd_clk => rd_clk,
rst => rst,
rst_d2 => rst_d2,
rst_full_gen_i => rst_full_gen_i,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x16_fifo_generator_top is
port (
dout : out STD_LOGIC_VECTOR ( 102 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
prog_full : out STD_LOGIC;
wr_en : in STD_LOGIC;
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 102 downto 0 );
rd_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x16_fifo_generator_top : entity is "fifo_generator_top";
end fifo_async_103x16_fifo_generator_top;
architecture STRUCTURE of fifo_async_103x16_fifo_generator_top is
begin
\grf.rf\: entity work.fifo_async_103x16_fifo_generator_ramfifo
port map (
din(102 downto 0) => din(102 downto 0),
dout(102 downto 0) => dout(102 downto 0),
empty => empty,
full => full,
prog_full => prog_full,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x16_fifo_generator_v12_0_synth is
port (
dout : out STD_LOGIC_VECTOR ( 102 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
prog_full : out STD_LOGIC;
wr_en : in STD_LOGIC;
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 102 downto 0 );
rd_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x16_fifo_generator_v12_0_synth : entity is "fifo_generator_v12_0_synth";
end fifo_async_103x16_fifo_generator_v12_0_synth;
architecture STRUCTURE of fifo_async_103x16_fifo_generator_v12_0_synth is
begin
\gconvfifo.rf\: entity work.fifo_async_103x16_fifo_generator_top
port map (
din(102 downto 0) => din(102 downto 0),
dout(102 downto 0) => dout(102 downto 0),
empty => empty,
full => full,
prog_full => prog_full,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ is
port (
backup : in STD_LOGIC;
backup_marker : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
srst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 102 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 3 downto 0 );
prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 3 downto 0 );
prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 3 downto 0 );
prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 3 downto 0 );
int_clk : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
injectsbiterr : in STD_LOGIC;
sleep : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 102 downto 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
wr_ack : out STD_LOGIC;
overflow : out STD_LOGIC;
empty : out STD_LOGIC;
almost_empty : out STD_LOGIC;
valid : out STD_LOGIC;
underflow : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 3 downto 0 );
rd_data_count : out STD_LOGIC_VECTOR ( 3 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 3 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
m_aclk_en : in STD_LOGIC;
s_aclk_en : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_tstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tlast : in STD_LOGIC;
s_axis_tid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tdest : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_tstrb : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tlast : out STD_LOGIC;
m_axis_tid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tdest : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_injectsbiterr : in STD_LOGIC;
axi_aw_injectdbiterr : in STD_LOGIC;
axi_aw_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_sbiterr : out STD_LOGIC;
axi_aw_dbiterr : out STD_LOGIC;
axi_aw_overflow : out STD_LOGIC;
axi_aw_underflow : out STD_LOGIC;
axi_aw_prog_full : out STD_LOGIC;
axi_aw_prog_empty : out STD_LOGIC;
axi_w_injectsbiterr : in STD_LOGIC;
axi_w_injectdbiterr : in STD_LOGIC;
axi_w_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_sbiterr : out STD_LOGIC;
axi_w_dbiterr : out STD_LOGIC;
axi_w_overflow : out STD_LOGIC;
axi_w_underflow : out STD_LOGIC;
axi_w_prog_full : out STD_LOGIC;
axi_w_prog_empty : out STD_LOGIC;
axi_b_injectsbiterr : in STD_LOGIC;
axi_b_injectdbiterr : in STD_LOGIC;
axi_b_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_sbiterr : out STD_LOGIC;
axi_b_dbiterr : out STD_LOGIC;
axi_b_overflow : out STD_LOGIC;
axi_b_underflow : out STD_LOGIC;
axi_b_prog_full : out STD_LOGIC;
axi_b_prog_empty : out STD_LOGIC;
axi_ar_injectsbiterr : in STD_LOGIC;
axi_ar_injectdbiterr : in STD_LOGIC;
axi_ar_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_sbiterr : out STD_LOGIC;
axi_ar_dbiterr : out STD_LOGIC;
axi_ar_overflow : out STD_LOGIC;
axi_ar_underflow : out STD_LOGIC;
axi_ar_prog_full : out STD_LOGIC;
axi_ar_prog_empty : out STD_LOGIC;
axi_r_injectsbiterr : in STD_LOGIC;
axi_r_injectdbiterr : in STD_LOGIC;
axi_r_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_sbiterr : out STD_LOGIC;
axi_r_dbiterr : out STD_LOGIC;
axi_r_overflow : out STD_LOGIC;
axi_r_underflow : out STD_LOGIC;
axi_r_prog_full : out STD_LOGIC;
axi_r_prog_empty : out STD_LOGIC;
axis_injectsbiterr : in STD_LOGIC;
axis_injectdbiterr : in STD_LOGIC;
axis_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_sbiterr : out STD_LOGIC;
axis_dbiterr : out STD_LOGIC;
axis_overflow : out STD_LOGIC;
axis_underflow : out STD_LOGIC;
axis_prog_full : out STD_LOGIC;
axis_prog_empty : out STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is "fifo_generator_v12_0";
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 4;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 103;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 103;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is "zynq";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 2;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 2;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is "BlankString";
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is "512x72";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 4;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 5;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 12;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 11;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 4;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 16;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 4;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 4;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 2;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 32;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 64;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 8;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 4;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is "1kx18";
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 32;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 2;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 64;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 16;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1024;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1024;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 4;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 10;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 10;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1023;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 1022;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ : entity is 0;
end \fifo_async_103x16_fifo_generator_v12_0__parameterized0\;
architecture STRUCTURE of \fifo_async_103x16_fifo_generator_v12_0__parameterized0\ is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
almost_empty <= \<const0>\;
almost_full <= \<const0>\;
axi_ar_data_count(4) <= \<const0>\;
axi_ar_data_count(3) <= \<const0>\;
axi_ar_data_count(2) <= \<const0>\;
axi_ar_data_count(1) <= \<const0>\;
axi_ar_data_count(0) <= \<const0>\;
axi_ar_dbiterr <= \<const0>\;
axi_ar_overflow <= \<const0>\;
axi_ar_prog_empty <= \<const1>\;
axi_ar_prog_full <= \<const0>\;
axi_ar_rd_data_count(4) <= \<const0>\;
axi_ar_rd_data_count(3) <= \<const0>\;
axi_ar_rd_data_count(2) <= \<const0>\;
axi_ar_rd_data_count(1) <= \<const0>\;
axi_ar_rd_data_count(0) <= \<const0>\;
axi_ar_sbiterr <= \<const0>\;
axi_ar_underflow <= \<const0>\;
axi_ar_wr_data_count(4) <= \<const0>\;
axi_ar_wr_data_count(3) <= \<const0>\;
axi_ar_wr_data_count(2) <= \<const0>\;
axi_ar_wr_data_count(1) <= \<const0>\;
axi_ar_wr_data_count(0) <= \<const0>\;
axi_aw_data_count(4) <= \<const0>\;
axi_aw_data_count(3) <= \<const0>\;
axi_aw_data_count(2) <= \<const0>\;
axi_aw_data_count(1) <= \<const0>\;
axi_aw_data_count(0) <= \<const0>\;
axi_aw_dbiterr <= \<const0>\;
axi_aw_overflow <= \<const0>\;
axi_aw_prog_empty <= \<const1>\;
axi_aw_prog_full <= \<const0>\;
axi_aw_rd_data_count(4) <= \<const0>\;
axi_aw_rd_data_count(3) <= \<const0>\;
axi_aw_rd_data_count(2) <= \<const0>\;
axi_aw_rd_data_count(1) <= \<const0>\;
axi_aw_rd_data_count(0) <= \<const0>\;
axi_aw_sbiterr <= \<const0>\;
axi_aw_underflow <= \<const0>\;
axi_aw_wr_data_count(4) <= \<const0>\;
axi_aw_wr_data_count(3) <= \<const0>\;
axi_aw_wr_data_count(2) <= \<const0>\;
axi_aw_wr_data_count(1) <= \<const0>\;
axi_aw_wr_data_count(0) <= \<const0>\;
axi_b_data_count(4) <= \<const0>\;
axi_b_data_count(3) <= \<const0>\;
axi_b_data_count(2) <= \<const0>\;
axi_b_data_count(1) <= \<const0>\;
axi_b_data_count(0) <= \<const0>\;
axi_b_dbiterr <= \<const0>\;
axi_b_overflow <= \<const0>\;
axi_b_prog_empty <= \<const1>\;
axi_b_prog_full <= \<const0>\;
axi_b_rd_data_count(4) <= \<const0>\;
axi_b_rd_data_count(3) <= \<const0>\;
axi_b_rd_data_count(2) <= \<const0>\;
axi_b_rd_data_count(1) <= \<const0>\;
axi_b_rd_data_count(0) <= \<const0>\;
axi_b_sbiterr <= \<const0>\;
axi_b_underflow <= \<const0>\;
axi_b_wr_data_count(4) <= \<const0>\;
axi_b_wr_data_count(3) <= \<const0>\;
axi_b_wr_data_count(2) <= \<const0>\;
axi_b_wr_data_count(1) <= \<const0>\;
axi_b_wr_data_count(0) <= \<const0>\;
axi_r_data_count(10) <= \<const0>\;
axi_r_data_count(9) <= \<const0>\;
axi_r_data_count(8) <= \<const0>\;
axi_r_data_count(7) <= \<const0>\;
axi_r_data_count(6) <= \<const0>\;
axi_r_data_count(5) <= \<const0>\;
axi_r_data_count(4) <= \<const0>\;
axi_r_data_count(3) <= \<const0>\;
axi_r_data_count(2) <= \<const0>\;
axi_r_data_count(1) <= \<const0>\;
axi_r_data_count(0) <= \<const0>\;
axi_r_dbiterr <= \<const0>\;
axi_r_overflow <= \<const0>\;
axi_r_prog_empty <= \<const1>\;
axi_r_prog_full <= \<const0>\;
axi_r_rd_data_count(10) <= \<const0>\;
axi_r_rd_data_count(9) <= \<const0>\;
axi_r_rd_data_count(8) <= \<const0>\;
axi_r_rd_data_count(7) <= \<const0>\;
axi_r_rd_data_count(6) <= \<const0>\;
axi_r_rd_data_count(5) <= \<const0>\;
axi_r_rd_data_count(4) <= \<const0>\;
axi_r_rd_data_count(3) <= \<const0>\;
axi_r_rd_data_count(2) <= \<const0>\;
axi_r_rd_data_count(1) <= \<const0>\;
axi_r_rd_data_count(0) <= \<const0>\;
axi_r_sbiterr <= \<const0>\;
axi_r_underflow <= \<const0>\;
axi_r_wr_data_count(10) <= \<const0>\;
axi_r_wr_data_count(9) <= \<const0>\;
axi_r_wr_data_count(8) <= \<const0>\;
axi_r_wr_data_count(7) <= \<const0>\;
axi_r_wr_data_count(6) <= \<const0>\;
axi_r_wr_data_count(5) <= \<const0>\;
axi_r_wr_data_count(4) <= \<const0>\;
axi_r_wr_data_count(3) <= \<const0>\;
axi_r_wr_data_count(2) <= \<const0>\;
axi_r_wr_data_count(1) <= \<const0>\;
axi_r_wr_data_count(0) <= \<const0>\;
axi_w_data_count(10) <= \<const0>\;
axi_w_data_count(9) <= \<const0>\;
axi_w_data_count(8) <= \<const0>\;
axi_w_data_count(7) <= \<const0>\;
axi_w_data_count(6) <= \<const0>\;
axi_w_data_count(5) <= \<const0>\;
axi_w_data_count(4) <= \<const0>\;
axi_w_data_count(3) <= \<const0>\;
axi_w_data_count(2) <= \<const0>\;
axi_w_data_count(1) <= \<const0>\;
axi_w_data_count(0) <= \<const0>\;
axi_w_dbiterr <= \<const0>\;
axi_w_overflow <= \<const0>\;
axi_w_prog_empty <= \<const1>\;
axi_w_prog_full <= \<const0>\;
axi_w_rd_data_count(10) <= \<const0>\;
axi_w_rd_data_count(9) <= \<const0>\;
axi_w_rd_data_count(8) <= \<const0>\;
axi_w_rd_data_count(7) <= \<const0>\;
axi_w_rd_data_count(6) <= \<const0>\;
axi_w_rd_data_count(5) <= \<const0>\;
axi_w_rd_data_count(4) <= \<const0>\;
axi_w_rd_data_count(3) <= \<const0>\;
axi_w_rd_data_count(2) <= \<const0>\;
axi_w_rd_data_count(1) <= \<const0>\;
axi_w_rd_data_count(0) <= \<const0>\;
axi_w_sbiterr <= \<const0>\;
axi_w_underflow <= \<const0>\;
axi_w_wr_data_count(10) <= \<const0>\;
axi_w_wr_data_count(9) <= \<const0>\;
axi_w_wr_data_count(8) <= \<const0>\;
axi_w_wr_data_count(7) <= \<const0>\;
axi_w_wr_data_count(6) <= \<const0>\;
axi_w_wr_data_count(5) <= \<const0>\;
axi_w_wr_data_count(4) <= \<const0>\;
axi_w_wr_data_count(3) <= \<const0>\;
axi_w_wr_data_count(2) <= \<const0>\;
axi_w_wr_data_count(1) <= \<const0>\;
axi_w_wr_data_count(0) <= \<const0>\;
axis_data_count(10) <= \<const0>\;
axis_data_count(9) <= \<const0>\;
axis_data_count(8) <= \<const0>\;
axis_data_count(7) <= \<const0>\;
axis_data_count(6) <= \<const0>\;
axis_data_count(5) <= \<const0>\;
axis_data_count(4) <= \<const0>\;
axis_data_count(3) <= \<const0>\;
axis_data_count(2) <= \<const0>\;
axis_data_count(1) <= \<const0>\;
axis_data_count(0) <= \<const0>\;
axis_dbiterr <= \<const0>\;
axis_overflow <= \<const0>\;
axis_prog_empty <= \<const1>\;
axis_prog_full <= \<const0>\;
axis_rd_data_count(10) <= \<const0>\;
axis_rd_data_count(9) <= \<const0>\;
axis_rd_data_count(8) <= \<const0>\;
axis_rd_data_count(7) <= \<const0>\;
axis_rd_data_count(6) <= \<const0>\;
axis_rd_data_count(5) <= \<const0>\;
axis_rd_data_count(4) <= \<const0>\;
axis_rd_data_count(3) <= \<const0>\;
axis_rd_data_count(2) <= \<const0>\;
axis_rd_data_count(1) <= \<const0>\;
axis_rd_data_count(0) <= \<const0>\;
axis_sbiterr <= \<const0>\;
axis_underflow <= \<const0>\;
axis_wr_data_count(10) <= \<const0>\;
axis_wr_data_count(9) <= \<const0>\;
axis_wr_data_count(8) <= \<const0>\;
axis_wr_data_count(7) <= \<const0>\;
axis_wr_data_count(6) <= \<const0>\;
axis_wr_data_count(5) <= \<const0>\;
axis_wr_data_count(4) <= \<const0>\;
axis_wr_data_count(3) <= \<const0>\;
axis_wr_data_count(2) <= \<const0>\;
axis_wr_data_count(1) <= \<const0>\;
axis_wr_data_count(0) <= \<const0>\;
data_count(3) <= \<const0>\;
data_count(2) <= \<const0>\;
data_count(1) <= \<const0>\;
data_count(0) <= \<const0>\;
dbiterr <= \<const0>\;
m_axi_araddr(31) <= \<const0>\;
m_axi_araddr(30) <= \<const0>\;
m_axi_araddr(29) <= \<const0>\;
m_axi_araddr(28) <= \<const0>\;
m_axi_araddr(27) <= \<const0>\;
m_axi_araddr(26) <= \<const0>\;
m_axi_araddr(25) <= \<const0>\;
m_axi_araddr(24) <= \<const0>\;
m_axi_araddr(23) <= \<const0>\;
m_axi_araddr(22) <= \<const0>\;
m_axi_araddr(21) <= \<const0>\;
m_axi_araddr(20) <= \<const0>\;
m_axi_araddr(19) <= \<const0>\;
m_axi_araddr(18) <= \<const0>\;
m_axi_araddr(17) <= \<const0>\;
m_axi_araddr(16) <= \<const0>\;
m_axi_araddr(15) <= \<const0>\;
m_axi_araddr(14) <= \<const0>\;
m_axi_araddr(13) <= \<const0>\;
m_axi_araddr(12) <= \<const0>\;
m_axi_araddr(11) <= \<const0>\;
m_axi_araddr(10) <= \<const0>\;
m_axi_araddr(9) <= \<const0>\;
m_axi_araddr(8) <= \<const0>\;
m_axi_araddr(7) <= \<const0>\;
m_axi_araddr(6) <= \<const0>\;
m_axi_araddr(5) <= \<const0>\;
m_axi_araddr(4) <= \<const0>\;
m_axi_araddr(3) <= \<const0>\;
m_axi_araddr(2) <= \<const0>\;
m_axi_araddr(1) <= \<const0>\;
m_axi_araddr(0) <= \<const0>\;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const0>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arprot(2) <= \<const0>\;
m_axi_arprot(1) <= \<const0>\;
m_axi_arprot(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const0>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_arvalid <= \<const0>\;
m_axi_awaddr(31) <= \<const0>\;
m_axi_awaddr(30) <= \<const0>\;
m_axi_awaddr(29) <= \<const0>\;
m_axi_awaddr(28) <= \<const0>\;
m_axi_awaddr(27) <= \<const0>\;
m_axi_awaddr(26) <= \<const0>\;
m_axi_awaddr(25) <= \<const0>\;
m_axi_awaddr(24) <= \<const0>\;
m_axi_awaddr(23) <= \<const0>\;
m_axi_awaddr(22) <= \<const0>\;
m_axi_awaddr(21) <= \<const0>\;
m_axi_awaddr(20) <= \<const0>\;
m_axi_awaddr(19) <= \<const0>\;
m_axi_awaddr(18) <= \<const0>\;
m_axi_awaddr(17) <= \<const0>\;
m_axi_awaddr(16) <= \<const0>\;
m_axi_awaddr(15) <= \<const0>\;
m_axi_awaddr(14) <= \<const0>\;
m_axi_awaddr(13) <= \<const0>\;
m_axi_awaddr(12) <= \<const0>\;
m_axi_awaddr(11) <= \<const0>\;
m_axi_awaddr(10) <= \<const0>\;
m_axi_awaddr(9) <= \<const0>\;
m_axi_awaddr(8) <= \<const0>\;
m_axi_awaddr(7) <= \<const0>\;
m_axi_awaddr(6) <= \<const0>\;
m_axi_awaddr(5) <= \<const0>\;
m_axi_awaddr(4) <= \<const0>\;
m_axi_awaddr(3) <= \<const0>\;
m_axi_awaddr(2) <= \<const0>\;
m_axi_awaddr(1) <= \<const0>\;
m_axi_awaddr(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const0>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awprot(2) <= \<const0>\;
m_axi_awprot(1) <= \<const0>\;
m_axi_awprot(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const0>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_awvalid <= \<const0>\;
m_axi_bready <= \<const0>\;
m_axi_rready <= \<const0>\;
m_axi_wdata(63) <= \<const0>\;
m_axi_wdata(62) <= \<const0>\;
m_axi_wdata(61) <= \<const0>\;
m_axi_wdata(60) <= \<const0>\;
m_axi_wdata(59) <= \<const0>\;
m_axi_wdata(58) <= \<const0>\;
m_axi_wdata(57) <= \<const0>\;
m_axi_wdata(56) <= \<const0>\;
m_axi_wdata(55) <= \<const0>\;
m_axi_wdata(54) <= \<const0>\;
m_axi_wdata(53) <= \<const0>\;
m_axi_wdata(52) <= \<const0>\;
m_axi_wdata(51) <= \<const0>\;
m_axi_wdata(50) <= \<const0>\;
m_axi_wdata(49) <= \<const0>\;
m_axi_wdata(48) <= \<const0>\;
m_axi_wdata(47) <= \<const0>\;
m_axi_wdata(46) <= \<const0>\;
m_axi_wdata(45) <= \<const0>\;
m_axi_wdata(44) <= \<const0>\;
m_axi_wdata(43) <= \<const0>\;
m_axi_wdata(42) <= \<const0>\;
m_axi_wdata(41) <= \<const0>\;
m_axi_wdata(40) <= \<const0>\;
m_axi_wdata(39) <= \<const0>\;
m_axi_wdata(38) <= \<const0>\;
m_axi_wdata(37) <= \<const0>\;
m_axi_wdata(36) <= \<const0>\;
m_axi_wdata(35) <= \<const0>\;
m_axi_wdata(34) <= \<const0>\;
m_axi_wdata(33) <= \<const0>\;
m_axi_wdata(32) <= \<const0>\;
m_axi_wdata(31) <= \<const0>\;
m_axi_wdata(30) <= \<const0>\;
m_axi_wdata(29) <= \<const0>\;
m_axi_wdata(28) <= \<const0>\;
m_axi_wdata(27) <= \<const0>\;
m_axi_wdata(26) <= \<const0>\;
m_axi_wdata(25) <= \<const0>\;
m_axi_wdata(24) <= \<const0>\;
m_axi_wdata(23) <= \<const0>\;
m_axi_wdata(22) <= \<const0>\;
m_axi_wdata(21) <= \<const0>\;
m_axi_wdata(20) <= \<const0>\;
m_axi_wdata(19) <= \<const0>\;
m_axi_wdata(18) <= \<const0>\;
m_axi_wdata(17) <= \<const0>\;
m_axi_wdata(16) <= \<const0>\;
m_axi_wdata(15) <= \<const0>\;
m_axi_wdata(14) <= \<const0>\;
m_axi_wdata(13) <= \<const0>\;
m_axi_wdata(12) <= \<const0>\;
m_axi_wdata(11) <= \<const0>\;
m_axi_wdata(10) <= \<const0>\;
m_axi_wdata(9) <= \<const0>\;
m_axi_wdata(8) <= \<const0>\;
m_axi_wdata(7) <= \<const0>\;
m_axi_wdata(6) <= \<const0>\;
m_axi_wdata(5) <= \<const0>\;
m_axi_wdata(4) <= \<const0>\;
m_axi_wdata(3) <= \<const0>\;
m_axi_wdata(2) <= \<const0>\;
m_axi_wdata(1) <= \<const0>\;
m_axi_wdata(0) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const0>\;
m_axi_wstrb(7) <= \<const0>\;
m_axi_wstrb(6) <= \<const0>\;
m_axi_wstrb(5) <= \<const0>\;
m_axi_wstrb(4) <= \<const0>\;
m_axi_wstrb(3) <= \<const0>\;
m_axi_wstrb(2) <= \<const0>\;
m_axi_wstrb(1) <= \<const0>\;
m_axi_wstrb(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \<const0>\;
m_axis_tdata(7) <= \<const0>\;
m_axis_tdata(6) <= \<const0>\;
m_axis_tdata(5) <= \<const0>\;
m_axis_tdata(4) <= \<const0>\;
m_axis_tdata(3) <= \<const0>\;
m_axis_tdata(2) <= \<const0>\;
m_axis_tdata(1) <= \<const0>\;
m_axis_tdata(0) <= \<const0>\;
m_axis_tdest(0) <= \<const0>\;
m_axis_tid(0) <= \<const0>\;
m_axis_tkeep(0) <= \<const0>\;
m_axis_tlast <= \<const0>\;
m_axis_tstrb(0) <= \<const0>\;
m_axis_tuser(3) <= \<const0>\;
m_axis_tuser(2) <= \<const0>\;
m_axis_tuser(1) <= \<const0>\;
m_axis_tuser(0) <= \<const0>\;
m_axis_tvalid <= \<const0>\;
overflow <= \<const0>\;
prog_empty <= \<const0>\;
rd_data_count(3) <= \<const0>\;
rd_data_count(2) <= \<const0>\;
rd_data_count(1) <= \<const0>\;
rd_data_count(0) <= \<const0>\;
rd_rst_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_rdata(63) <= \<const0>\;
s_axi_rdata(62) <= \<const0>\;
s_axi_rdata(61) <= \<const0>\;
s_axi_rdata(60) <= \<const0>\;
s_axi_rdata(59) <= \<const0>\;
s_axi_rdata(58) <= \<const0>\;
s_axi_rdata(57) <= \<const0>\;
s_axi_rdata(56) <= \<const0>\;
s_axi_rdata(55) <= \<const0>\;
s_axi_rdata(54) <= \<const0>\;
s_axi_rdata(53) <= \<const0>\;
s_axi_rdata(52) <= \<const0>\;
s_axi_rdata(51) <= \<const0>\;
s_axi_rdata(50) <= \<const0>\;
s_axi_rdata(49) <= \<const0>\;
s_axi_rdata(48) <= \<const0>\;
s_axi_rdata(47) <= \<const0>\;
s_axi_rdata(46) <= \<const0>\;
s_axi_rdata(45) <= \<const0>\;
s_axi_rdata(44) <= \<const0>\;
s_axi_rdata(43) <= \<const0>\;
s_axi_rdata(42) <= \<const0>\;
s_axi_rdata(41) <= \<const0>\;
s_axi_rdata(40) <= \<const0>\;
s_axi_rdata(39) <= \<const0>\;
s_axi_rdata(38) <= \<const0>\;
s_axi_rdata(37) <= \<const0>\;
s_axi_rdata(36) <= \<const0>\;
s_axi_rdata(35) <= \<const0>\;
s_axi_rdata(34) <= \<const0>\;
s_axi_rdata(33) <= \<const0>\;
s_axi_rdata(32) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_wready <= \<const0>\;
s_axis_tready <= \<const0>\;
sbiterr <= \<const0>\;
underflow <= \<const0>\;
valid <= \<const0>\;
wr_ack <= \<const0>\;
wr_data_count(3) <= \<const0>\;
wr_data_count(2) <= \<const0>\;
wr_data_count(1) <= \<const0>\;
wr_data_count(0) <= \<const0>\;
wr_rst_busy <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
inst_fifo_gen: entity work.fifo_async_103x16_fifo_generator_v12_0_synth
port map (
din(102 downto 0) => din(102 downto 0),
dout(102 downto 0) => dout(102 downto 0),
empty => empty,
full => full,
prog_full => prog_full,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x16 is
port (
rst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 102 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 102 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC;
prog_full : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of fifo_async_103x16 : entity is true;
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of fifo_async_103x16 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of fifo_async_103x16 : entity is "fifo_generator_v12_0,Vivado 2014.3.1";
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of fifo_async_103x16 : entity is "fifo_async_103x16,fifo_generator_v12_0,{}";
attribute core_generation_info : string;
attribute core_generation_info of fifo_async_103x16 : entity is "fifo_async_103x16,fifo_generator_v12_0,{x_ipProduct=Vivado 2014.3.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=12.0,x_ipCoreRevision=2,x_ipLanguage=VERILOG,C_COMMON_CLOCK=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=4,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=103,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=103,C_ENABLE_RLOCS=0,C_FAMILY=zynq,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=2,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=2,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=0,C_PRELOAD_REGS=1,C_PRIM_FIFO_TYPE=512x72,C_PROG_EMPTY_THRESH_ASSERT_VAL=4,C_PROG_EMPTY_THRESH_NEGATE_VAL=5,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=12,C_PROG_FULL_THRESH_NEGATE_VAL=11,C_PROG_FULL_TYPE=1,C_RD_DATA_COUNT_WIDTH=4,C_RD_DEPTH=16,C_RD_FREQ=1,C_RD_PNTR_WIDTH=4,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=4,C_WR_DEPTH=16,C_WR_FREQ=1,C_WR_PNTR_WIDTH=4,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
end fifo_async_103x16;
architecture STRUCTURE of fifo_async_103x16 is
signal NLW_U0_almost_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_almost_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_arvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_awvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_bready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_rready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rd_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_valid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_ack_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_r_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of U0 : label is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of U0 : label is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of U0 : label is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of U0 : label is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of U0 : label is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of U0 : label is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of U0 : label is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of U0 : label is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of U0 : label is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of U0 : label is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of U0 : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of U0 : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of U0 : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of U0 : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of U0 : label is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of U0 : label is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of U0 : label is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of U0 : label is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of U0 : label is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of U0 : label is 0;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of U0 : label is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of U0 : label is 4;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of U0 : label is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of U0 : label is 103;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of U0 : label is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of U0 : label is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of U0 : label is 32;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of U0 : label is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of U0 : label is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of U0 : label is 103;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of U0 : label is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of U0 : label is 1;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of U0 : label is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of U0 : label is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of U0 : label is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of U0 : label is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of U0 : label is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of U0 : label is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of U0 : label is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of U0 : label is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of U0 : label is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of U0 : label is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of U0 : label is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of U0 : label is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of U0 : label is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of U0 : label is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of U0 : label is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of U0 : label is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of U0 : label is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of U0 : label is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of U0 : label is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of U0 : label is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of U0 : label is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of U0 : label is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of U0 : label is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of U0 : label is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of U0 : label is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of U0 : label is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of U0 : label is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of U0 : label is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of U0 : label is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of U0 : label is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of U0 : label is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of U0 : label is 2;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of U0 : label is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of U0 : label is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of U0 : label is 2;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of U0 : label is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of U0 : label is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of U0 : label is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of U0 : label is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of U0 : label is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of U0 : label is 0;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of U0 : label is 1;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of U0 : label is "512x72";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of U0 : label is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of U0 : label is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of U0 : label is 4;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of U0 : label is 5;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of U0 : label is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of U0 : label is 12;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of U0 : label is 11;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of U0 : label is 1;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of U0 : label is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of U0 : label is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of U0 : label is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of U0 : label is 4;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of U0 : label is 16;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of U0 : label is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of U0 : label is 4;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of U0 : label is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of U0 : label is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of U0 : label is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of U0 : label is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of U0 : label is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of U0 : label is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of U0 : label is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of U0 : label is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of U0 : label is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of U0 : label is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of U0 : label is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of U0 : label is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of U0 : label is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of U0 : label is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of U0 : label is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of U0 : label is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of U0 : label is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of U0 : label is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of U0 : label is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of U0 : label is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of U0 : label is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of U0 : label is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of U0 : label is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of U0 : label is 4;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of U0 : label is 16;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of U0 : label is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of U0 : label is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of U0 : label is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of U0 : label is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of U0 : label is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of U0 : label is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of U0 : label is 1;
begin
U0: entity work.\fifo_async_103x16_fifo_generator_v12_0__parameterized0\
port map (
almost_empty => NLW_U0_almost_empty_UNCONNECTED,
almost_full => NLW_U0_almost_full_UNCONNECTED,
axi_ar_data_count(4 downto 0) => NLW_U0_axi_ar_data_count_UNCONNECTED(4 downto 0),
axi_ar_dbiterr => NLW_U0_axi_ar_dbiterr_UNCONNECTED,
axi_ar_injectdbiterr => '0',
axi_ar_injectsbiterr => '0',
axi_ar_overflow => NLW_U0_axi_ar_overflow_UNCONNECTED,
axi_ar_prog_empty => NLW_U0_axi_ar_prog_empty_UNCONNECTED,
axi_ar_prog_empty_thresh(3) => '0',
axi_ar_prog_empty_thresh(2) => '0',
axi_ar_prog_empty_thresh(1) => '0',
axi_ar_prog_empty_thresh(0) => '0',
axi_ar_prog_full => NLW_U0_axi_ar_prog_full_UNCONNECTED,
axi_ar_prog_full_thresh(3) => '0',
axi_ar_prog_full_thresh(2) => '0',
axi_ar_prog_full_thresh(1) => '0',
axi_ar_prog_full_thresh(0) => '0',
axi_ar_rd_data_count(4 downto 0) => NLW_U0_axi_ar_rd_data_count_UNCONNECTED(4 downto 0),
axi_ar_sbiterr => NLW_U0_axi_ar_sbiterr_UNCONNECTED,
axi_ar_underflow => NLW_U0_axi_ar_underflow_UNCONNECTED,
axi_ar_wr_data_count(4 downto 0) => NLW_U0_axi_ar_wr_data_count_UNCONNECTED(4 downto 0),
axi_aw_data_count(4 downto 0) => NLW_U0_axi_aw_data_count_UNCONNECTED(4 downto 0),
axi_aw_dbiterr => NLW_U0_axi_aw_dbiterr_UNCONNECTED,
axi_aw_injectdbiterr => '0',
axi_aw_injectsbiterr => '0',
axi_aw_overflow => NLW_U0_axi_aw_overflow_UNCONNECTED,
axi_aw_prog_empty => NLW_U0_axi_aw_prog_empty_UNCONNECTED,
axi_aw_prog_empty_thresh(3) => '0',
axi_aw_prog_empty_thresh(2) => '0',
axi_aw_prog_empty_thresh(1) => '0',
axi_aw_prog_empty_thresh(0) => '0',
axi_aw_prog_full => NLW_U0_axi_aw_prog_full_UNCONNECTED,
axi_aw_prog_full_thresh(3) => '0',
axi_aw_prog_full_thresh(2) => '0',
axi_aw_prog_full_thresh(1) => '0',
axi_aw_prog_full_thresh(0) => '0',
axi_aw_rd_data_count(4 downto 0) => NLW_U0_axi_aw_rd_data_count_UNCONNECTED(4 downto 0),
axi_aw_sbiterr => NLW_U0_axi_aw_sbiterr_UNCONNECTED,
axi_aw_underflow => NLW_U0_axi_aw_underflow_UNCONNECTED,
axi_aw_wr_data_count(4 downto 0) => NLW_U0_axi_aw_wr_data_count_UNCONNECTED(4 downto 0),
axi_b_data_count(4 downto 0) => NLW_U0_axi_b_data_count_UNCONNECTED(4 downto 0),
axi_b_dbiterr => NLW_U0_axi_b_dbiterr_UNCONNECTED,
axi_b_injectdbiterr => '0',
axi_b_injectsbiterr => '0',
axi_b_overflow => NLW_U0_axi_b_overflow_UNCONNECTED,
axi_b_prog_empty => NLW_U0_axi_b_prog_empty_UNCONNECTED,
axi_b_prog_empty_thresh(3) => '0',
axi_b_prog_empty_thresh(2) => '0',
axi_b_prog_empty_thresh(1) => '0',
axi_b_prog_empty_thresh(0) => '0',
axi_b_prog_full => NLW_U0_axi_b_prog_full_UNCONNECTED,
axi_b_prog_full_thresh(3) => '0',
axi_b_prog_full_thresh(2) => '0',
axi_b_prog_full_thresh(1) => '0',
axi_b_prog_full_thresh(0) => '0',
axi_b_rd_data_count(4 downto 0) => NLW_U0_axi_b_rd_data_count_UNCONNECTED(4 downto 0),
axi_b_sbiterr => NLW_U0_axi_b_sbiterr_UNCONNECTED,
axi_b_underflow => NLW_U0_axi_b_underflow_UNCONNECTED,
axi_b_wr_data_count(4 downto 0) => NLW_U0_axi_b_wr_data_count_UNCONNECTED(4 downto 0),
axi_r_data_count(10 downto 0) => NLW_U0_axi_r_data_count_UNCONNECTED(10 downto 0),
axi_r_dbiterr => NLW_U0_axi_r_dbiterr_UNCONNECTED,
axi_r_injectdbiterr => '0',
axi_r_injectsbiterr => '0',
axi_r_overflow => NLW_U0_axi_r_overflow_UNCONNECTED,
axi_r_prog_empty => NLW_U0_axi_r_prog_empty_UNCONNECTED,
axi_r_prog_empty_thresh(9) => '0',
axi_r_prog_empty_thresh(8) => '0',
axi_r_prog_empty_thresh(7) => '0',
axi_r_prog_empty_thresh(6) => '0',
axi_r_prog_empty_thresh(5) => '0',
axi_r_prog_empty_thresh(4) => '0',
axi_r_prog_empty_thresh(3) => '0',
axi_r_prog_empty_thresh(2) => '0',
axi_r_prog_empty_thresh(1) => '0',
axi_r_prog_empty_thresh(0) => '0',
axi_r_prog_full => NLW_U0_axi_r_prog_full_UNCONNECTED,
axi_r_prog_full_thresh(9) => '0',
axi_r_prog_full_thresh(8) => '0',
axi_r_prog_full_thresh(7) => '0',
axi_r_prog_full_thresh(6) => '0',
axi_r_prog_full_thresh(5) => '0',
axi_r_prog_full_thresh(4) => '0',
axi_r_prog_full_thresh(3) => '0',
axi_r_prog_full_thresh(2) => '0',
axi_r_prog_full_thresh(1) => '0',
axi_r_prog_full_thresh(0) => '0',
axi_r_rd_data_count(10 downto 0) => NLW_U0_axi_r_rd_data_count_UNCONNECTED(10 downto 0),
axi_r_sbiterr => NLW_U0_axi_r_sbiterr_UNCONNECTED,
axi_r_underflow => NLW_U0_axi_r_underflow_UNCONNECTED,
axi_r_wr_data_count(10 downto 0) => NLW_U0_axi_r_wr_data_count_UNCONNECTED(10 downto 0),
axi_w_data_count(10 downto 0) => NLW_U0_axi_w_data_count_UNCONNECTED(10 downto 0),
axi_w_dbiterr => NLW_U0_axi_w_dbiterr_UNCONNECTED,
axi_w_injectdbiterr => '0',
axi_w_injectsbiterr => '0',
axi_w_overflow => NLW_U0_axi_w_overflow_UNCONNECTED,
axi_w_prog_empty => NLW_U0_axi_w_prog_empty_UNCONNECTED,
axi_w_prog_empty_thresh(9) => '0',
axi_w_prog_empty_thresh(8) => '0',
axi_w_prog_empty_thresh(7) => '0',
axi_w_prog_empty_thresh(6) => '0',
axi_w_prog_empty_thresh(5) => '0',
axi_w_prog_empty_thresh(4) => '0',
axi_w_prog_empty_thresh(3) => '0',
axi_w_prog_empty_thresh(2) => '0',
axi_w_prog_empty_thresh(1) => '0',
axi_w_prog_empty_thresh(0) => '0',
axi_w_prog_full => NLW_U0_axi_w_prog_full_UNCONNECTED,
axi_w_prog_full_thresh(9) => '0',
axi_w_prog_full_thresh(8) => '0',
axi_w_prog_full_thresh(7) => '0',
axi_w_prog_full_thresh(6) => '0',
axi_w_prog_full_thresh(5) => '0',
axi_w_prog_full_thresh(4) => '0',
axi_w_prog_full_thresh(3) => '0',
axi_w_prog_full_thresh(2) => '0',
axi_w_prog_full_thresh(1) => '0',
axi_w_prog_full_thresh(0) => '0',
axi_w_rd_data_count(10 downto 0) => NLW_U0_axi_w_rd_data_count_UNCONNECTED(10 downto 0),
axi_w_sbiterr => NLW_U0_axi_w_sbiterr_UNCONNECTED,
axi_w_underflow => NLW_U0_axi_w_underflow_UNCONNECTED,
axi_w_wr_data_count(10 downto 0) => NLW_U0_axi_w_wr_data_count_UNCONNECTED(10 downto 0),
axis_data_count(10 downto 0) => NLW_U0_axis_data_count_UNCONNECTED(10 downto 0),
axis_dbiterr => NLW_U0_axis_dbiterr_UNCONNECTED,
axis_injectdbiterr => '0',
axis_injectsbiterr => '0',
axis_overflow => NLW_U0_axis_overflow_UNCONNECTED,
axis_prog_empty => NLW_U0_axis_prog_empty_UNCONNECTED,
axis_prog_empty_thresh(9) => '0',
axis_prog_empty_thresh(8) => '0',
axis_prog_empty_thresh(7) => '0',
axis_prog_empty_thresh(6) => '0',
axis_prog_empty_thresh(5) => '0',
axis_prog_empty_thresh(4) => '0',
axis_prog_empty_thresh(3) => '0',
axis_prog_empty_thresh(2) => '0',
axis_prog_empty_thresh(1) => '0',
axis_prog_empty_thresh(0) => '0',
axis_prog_full => NLW_U0_axis_prog_full_UNCONNECTED,
axis_prog_full_thresh(9) => '0',
axis_prog_full_thresh(8) => '0',
axis_prog_full_thresh(7) => '0',
axis_prog_full_thresh(6) => '0',
axis_prog_full_thresh(5) => '0',
axis_prog_full_thresh(4) => '0',
axis_prog_full_thresh(3) => '0',
axis_prog_full_thresh(2) => '0',
axis_prog_full_thresh(1) => '0',
axis_prog_full_thresh(0) => '0',
axis_rd_data_count(10 downto 0) => NLW_U0_axis_rd_data_count_UNCONNECTED(10 downto 0),
axis_sbiterr => NLW_U0_axis_sbiterr_UNCONNECTED,
axis_underflow => NLW_U0_axis_underflow_UNCONNECTED,
axis_wr_data_count(10 downto 0) => NLW_U0_axis_wr_data_count_UNCONNECTED(10 downto 0),
backup => '0',
backup_marker => '0',
clk => '0',
data_count(3 downto 0) => NLW_U0_data_count_UNCONNECTED(3 downto 0),
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
din(102 downto 0) => din(102 downto 0),
dout(102 downto 0) => dout(102 downto 0),
empty => empty,
full => full,
injectdbiterr => '0',
injectsbiterr => '0',
int_clk => '0',
m_aclk => '0',
m_aclk_en => '0',
m_axi_araddr(31 downto 0) => NLW_U0_m_axi_araddr_UNCONNECTED(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_U0_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_U0_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(0) => NLW_U0_m_axi_arid_UNCONNECTED(0),
m_axi_arlen(7 downto 0) => NLW_U0_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_U0_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => NLW_U0_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_U0_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => '0',
m_axi_arregion(3 downto 0) => NLW_U0_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_U0_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_U0_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => NLW_U0_m_axi_arvalid_UNCONNECTED,
m_axi_awaddr(31 downto 0) => NLW_U0_m_axi_awaddr_UNCONNECTED(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_U0_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_U0_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(0) => NLW_U0_m_axi_awid_UNCONNECTED(0),
m_axi_awlen(7 downto 0) => NLW_U0_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_U0_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => NLW_U0_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_U0_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => '0',
m_axi_awregion(3 downto 0) => NLW_U0_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_U0_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_U0_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => NLW_U0_m_axi_awvalid_UNCONNECTED,
m_axi_bid(0) => '0',
m_axi_bready => NLW_U0_m_axi_bready_UNCONNECTED,
m_axi_bresp(1) => '0',
m_axi_bresp(0) => '0',
m_axi_buser(0) => '0',
m_axi_bvalid => '0',
m_axi_rdata(63) => '0',
m_axi_rdata(62) => '0',
m_axi_rdata(61) => '0',
m_axi_rdata(60) => '0',
m_axi_rdata(59) => '0',
m_axi_rdata(58) => '0',
m_axi_rdata(57) => '0',
m_axi_rdata(56) => '0',
m_axi_rdata(55) => '0',
m_axi_rdata(54) => '0',
m_axi_rdata(53) => '0',
m_axi_rdata(52) => '0',
m_axi_rdata(51) => '0',
m_axi_rdata(50) => '0',
m_axi_rdata(49) => '0',
m_axi_rdata(48) => '0',
m_axi_rdata(47) => '0',
m_axi_rdata(46) => '0',
m_axi_rdata(45) => '0',
m_axi_rdata(44) => '0',
m_axi_rdata(43) => '0',
m_axi_rdata(42) => '0',
m_axi_rdata(41) => '0',
m_axi_rdata(40) => '0',
m_axi_rdata(39) => '0',
m_axi_rdata(38) => '0',
m_axi_rdata(37) => '0',
m_axi_rdata(36) => '0',
m_axi_rdata(35) => '0',
m_axi_rdata(34) => '0',
m_axi_rdata(33) => '0',
m_axi_rdata(32) => '0',
m_axi_rdata(31) => '0',
m_axi_rdata(30) => '0',
m_axi_rdata(29) => '0',
m_axi_rdata(28) => '0',
m_axi_rdata(27) => '0',
m_axi_rdata(26) => '0',
m_axi_rdata(25) => '0',
m_axi_rdata(24) => '0',
m_axi_rdata(23) => '0',
m_axi_rdata(22) => '0',
m_axi_rdata(21) => '0',
m_axi_rdata(20) => '0',
m_axi_rdata(19) => '0',
m_axi_rdata(18) => '0',
m_axi_rdata(17) => '0',
m_axi_rdata(16) => '0',
m_axi_rdata(15) => '0',
m_axi_rdata(14) => '0',
m_axi_rdata(13) => '0',
m_axi_rdata(12) => '0',
m_axi_rdata(11) => '0',
m_axi_rdata(10) => '0',
m_axi_rdata(9) => '0',
m_axi_rdata(8) => '0',
m_axi_rdata(7) => '0',
m_axi_rdata(6) => '0',
m_axi_rdata(5) => '0',
m_axi_rdata(4) => '0',
m_axi_rdata(3) => '0',
m_axi_rdata(2) => '0',
m_axi_rdata(1) => '0',
m_axi_rdata(0) => '0',
m_axi_rid(0) => '0',
m_axi_rlast => '0',
m_axi_rready => NLW_U0_m_axi_rready_UNCONNECTED,
m_axi_rresp(1) => '0',
m_axi_rresp(0) => '0',
m_axi_ruser(0) => '0',
m_axi_rvalid => '0',
m_axi_wdata(63 downto 0) => NLW_U0_m_axi_wdata_UNCONNECTED(63 downto 0),
m_axi_wid(0) => NLW_U0_m_axi_wid_UNCONNECTED(0),
m_axi_wlast => NLW_U0_m_axi_wlast_UNCONNECTED,
m_axi_wready => '0',
m_axi_wstrb(7 downto 0) => NLW_U0_m_axi_wstrb_UNCONNECTED(7 downto 0),
m_axi_wuser(0) => NLW_U0_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => NLW_U0_m_axi_wvalid_UNCONNECTED,
m_axis_tdata(7 downto 0) => NLW_U0_m_axis_tdata_UNCONNECTED(7 downto 0),
m_axis_tdest(0) => NLW_U0_m_axis_tdest_UNCONNECTED(0),
m_axis_tid(0) => NLW_U0_m_axis_tid_UNCONNECTED(0),
m_axis_tkeep(0) => NLW_U0_m_axis_tkeep_UNCONNECTED(0),
m_axis_tlast => NLW_U0_m_axis_tlast_UNCONNECTED,
m_axis_tready => '0',
m_axis_tstrb(0) => NLW_U0_m_axis_tstrb_UNCONNECTED(0),
m_axis_tuser(3 downto 0) => NLW_U0_m_axis_tuser_UNCONNECTED(3 downto 0),
m_axis_tvalid => NLW_U0_m_axis_tvalid_UNCONNECTED,
overflow => NLW_U0_overflow_UNCONNECTED,
prog_empty => NLW_U0_prog_empty_UNCONNECTED,
prog_empty_thresh(3) => '0',
prog_empty_thresh(2) => '0',
prog_empty_thresh(1) => '0',
prog_empty_thresh(0) => '0',
prog_empty_thresh_assert(3) => '0',
prog_empty_thresh_assert(2) => '0',
prog_empty_thresh_assert(1) => '0',
prog_empty_thresh_assert(0) => '0',
prog_empty_thresh_negate(3) => '0',
prog_empty_thresh_negate(2) => '0',
prog_empty_thresh_negate(1) => '0',
prog_empty_thresh_negate(0) => '0',
prog_full => prog_full,
prog_full_thresh(3) => '0',
prog_full_thresh(2) => '0',
prog_full_thresh(1) => '0',
prog_full_thresh(0) => '0',
prog_full_thresh_assert(3) => '0',
prog_full_thresh_assert(2) => '0',
prog_full_thresh_assert(1) => '0',
prog_full_thresh_assert(0) => '0',
prog_full_thresh_negate(3) => '0',
prog_full_thresh_negate(2) => '0',
prog_full_thresh_negate(1) => '0',
prog_full_thresh_negate(0) => '0',
rd_clk => rd_clk,
rd_data_count(3 downto 0) => NLW_U0_rd_data_count_UNCONNECTED(3 downto 0),
rd_en => rd_en,
rd_rst => '0',
rd_rst_busy => NLW_U0_rd_rst_busy_UNCONNECTED,
rst => rst,
s_aclk => '0',
s_aclk_en => '0',
s_aresetn => '0',
s_axi_araddr(31) => '0',
s_axi_araddr(30) => '0',
s_axi_araddr(29) => '0',
s_axi_araddr(28) => '0',
s_axi_araddr(27) => '0',
s_axi_araddr(26) => '0',
s_axi_araddr(25) => '0',
s_axi_araddr(24) => '0',
s_axi_araddr(23) => '0',
s_axi_araddr(22) => '0',
s_axi_araddr(21) => '0',
s_axi_araddr(20) => '0',
s_axi_araddr(19) => '0',
s_axi_araddr(18) => '0',
s_axi_araddr(17) => '0',
s_axi_araddr(16) => '0',
s_axi_araddr(15) => '0',
s_axi_araddr(14) => '0',
s_axi_araddr(13) => '0',
s_axi_araddr(12) => '0',
s_axi_araddr(11) => '0',
s_axi_araddr(10) => '0',
s_axi_araddr(9) => '0',
s_axi_araddr(8) => '0',
s_axi_araddr(7) => '0',
s_axi_araddr(6) => '0',
s_axi_araddr(5) => '0',
s_axi_araddr(4) => '0',
s_axi_araddr(3) => '0',
s_axi_araddr(2) => '0',
s_axi_araddr(1) => '0',
s_axi_araddr(0) => '0',
s_axi_arburst(1) => '0',
s_axi_arburst(0) => '0',
s_axi_arcache(3) => '0',
s_axi_arcache(2) => '0',
s_axi_arcache(1) => '0',
s_axi_arcache(0) => '0',
s_axi_arid(0) => '0',
s_axi_arlen(7) => '0',
s_axi_arlen(6) => '0',
s_axi_arlen(5) => '0',
s_axi_arlen(4) => '0',
s_axi_arlen(3) => '0',
s_axi_arlen(2) => '0',
s_axi_arlen(1) => '0',
s_axi_arlen(0) => '0',
s_axi_arlock(0) => '0',
s_axi_arprot(2) => '0',
s_axi_arprot(1) => '0',
s_axi_arprot(0) => '0',
s_axi_arqos(3) => '0',
s_axi_arqos(2) => '0',
s_axi_arqos(1) => '0',
s_axi_arqos(0) => '0',
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arregion(3) => '0',
s_axi_arregion(2) => '0',
s_axi_arregion(1) => '0',
s_axi_arregion(0) => '0',
s_axi_arsize(2) => '0',
s_axi_arsize(1) => '0',
s_axi_arsize(0) => '0',
s_axi_aruser(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31) => '0',
s_axi_awaddr(30) => '0',
s_axi_awaddr(29) => '0',
s_axi_awaddr(28) => '0',
s_axi_awaddr(27) => '0',
s_axi_awaddr(26) => '0',
s_axi_awaddr(25) => '0',
s_axi_awaddr(24) => '0',
s_axi_awaddr(23) => '0',
s_axi_awaddr(22) => '0',
s_axi_awaddr(21) => '0',
s_axi_awaddr(20) => '0',
s_axi_awaddr(19) => '0',
s_axi_awaddr(18) => '0',
s_axi_awaddr(17) => '0',
s_axi_awaddr(16) => '0',
s_axi_awaddr(15) => '0',
s_axi_awaddr(14) => '0',
s_axi_awaddr(13) => '0',
s_axi_awaddr(12) => '0',
s_axi_awaddr(11) => '0',
s_axi_awaddr(10) => '0',
s_axi_awaddr(9) => '0',
s_axi_awaddr(8) => '0',
s_axi_awaddr(7) => '0',
s_axi_awaddr(6) => '0',
s_axi_awaddr(5) => '0',
s_axi_awaddr(4) => '0',
s_axi_awaddr(3) => '0',
s_axi_awaddr(2) => '0',
s_axi_awaddr(1) => '0',
s_axi_awaddr(0) => '0',
s_axi_awburst(1) => '0',
s_axi_awburst(0) => '0',
s_axi_awcache(3) => '0',
s_axi_awcache(2) => '0',
s_axi_awcache(1) => '0',
s_axi_awcache(0) => '0',
s_axi_awid(0) => '0',
s_axi_awlen(7) => '0',
s_axi_awlen(6) => '0',
s_axi_awlen(5) => '0',
s_axi_awlen(4) => '0',
s_axi_awlen(3) => '0',
s_axi_awlen(2) => '0',
s_axi_awlen(1) => '0',
s_axi_awlen(0) => '0',
s_axi_awlock(0) => '0',
s_axi_awprot(2) => '0',
s_axi_awprot(1) => '0',
s_axi_awprot(0) => '0',
s_axi_awqos(3) => '0',
s_axi_awqos(2) => '0',
s_axi_awqos(1) => '0',
s_axi_awqos(0) => '0',
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awregion(3) => '0',
s_axi_awregion(2) => '0',
s_axi_awregion(1) => '0',
s_axi_awregion(0) => '0',
s_axi_awsize(2) => '0',
s_axi_awsize(1) => '0',
s_axi_awsize(0) => '0',
s_axi_awuser(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(0) => NLW_U0_s_axi_bid_UNCONNECTED(0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_buser(0) => NLW_U0_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
s_axi_rid(0) => NLW_U0_s_axi_rid_UNCONNECTED(0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_ruser(0) => NLW_U0_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_wdata(63) => '0',
s_axi_wdata(62) => '0',
s_axi_wdata(61) => '0',
s_axi_wdata(60) => '0',
s_axi_wdata(59) => '0',
s_axi_wdata(58) => '0',
s_axi_wdata(57) => '0',
s_axi_wdata(56) => '0',
s_axi_wdata(55) => '0',
s_axi_wdata(54) => '0',
s_axi_wdata(53) => '0',
s_axi_wdata(52) => '0',
s_axi_wdata(51) => '0',
s_axi_wdata(50) => '0',
s_axi_wdata(49) => '0',
s_axi_wdata(48) => '0',
s_axi_wdata(47) => '0',
s_axi_wdata(46) => '0',
s_axi_wdata(45) => '0',
s_axi_wdata(44) => '0',
s_axi_wdata(43) => '0',
s_axi_wdata(42) => '0',
s_axi_wdata(41) => '0',
s_axi_wdata(40) => '0',
s_axi_wdata(39) => '0',
s_axi_wdata(38) => '0',
s_axi_wdata(37) => '0',
s_axi_wdata(36) => '0',
s_axi_wdata(35) => '0',
s_axi_wdata(34) => '0',
s_axi_wdata(33) => '0',
s_axi_wdata(32) => '0',
s_axi_wdata(31) => '0',
s_axi_wdata(30) => '0',
s_axi_wdata(29) => '0',
s_axi_wdata(28) => '0',
s_axi_wdata(27) => '0',
s_axi_wdata(26) => '0',
s_axi_wdata(25) => '0',
s_axi_wdata(24) => '0',
s_axi_wdata(23) => '0',
s_axi_wdata(22) => '0',
s_axi_wdata(21) => '0',
s_axi_wdata(20) => '0',
s_axi_wdata(19) => '0',
s_axi_wdata(18) => '0',
s_axi_wdata(17) => '0',
s_axi_wdata(16) => '0',
s_axi_wdata(15) => '0',
s_axi_wdata(14) => '0',
s_axi_wdata(13) => '0',
s_axi_wdata(12) => '0',
s_axi_wdata(11) => '0',
s_axi_wdata(10) => '0',
s_axi_wdata(9) => '0',
s_axi_wdata(8) => '0',
s_axi_wdata(7) => '0',
s_axi_wdata(6) => '0',
s_axi_wdata(5) => '0',
s_axi_wdata(4) => '0',
s_axi_wdata(3) => '0',
s_axi_wdata(2) => '0',
s_axi_wdata(1) => '0',
s_axi_wdata(0) => '0',
s_axi_wid(0) => '0',
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(7) => '0',
s_axi_wstrb(6) => '0',
s_axi_wstrb(5) => '0',
s_axi_wstrb(4) => '0',
s_axi_wstrb(3) => '0',
s_axi_wstrb(2) => '0',
s_axi_wstrb(1) => '0',
s_axi_wstrb(0) => '0',
s_axi_wuser(0) => '0',
s_axi_wvalid => '0',
s_axis_tdata(7) => '0',
s_axis_tdata(6) => '0',
s_axis_tdata(5) => '0',
s_axis_tdata(4) => '0',
s_axis_tdata(3) => '0',
s_axis_tdata(2) => '0',
s_axis_tdata(1) => '0',
s_axis_tdata(0) => '0',
s_axis_tdest(0) => '0',
s_axis_tid(0) => '0',
s_axis_tkeep(0) => '0',
s_axis_tlast => '0',
s_axis_tready => NLW_U0_s_axis_tready_UNCONNECTED,
s_axis_tstrb(0) => '0',
s_axis_tuser(3) => '0',
s_axis_tuser(2) => '0',
s_axis_tuser(1) => '0',
s_axis_tuser(0) => '0',
s_axis_tvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
sleep => '0',
srst => '0',
underflow => NLW_U0_underflow_UNCONNECTED,
valid => NLW_U0_valid_UNCONNECTED,
wr_ack => NLW_U0_wr_ack_UNCONNECTED,
wr_clk => wr_clk,
wr_data_count(3 downto 0) => NLW_U0_wr_data_count_UNCONNECTED(3 downto 0),
wr_en => wr_en,
wr_rst => '0',
wr_rst_busy => NLW_U0_wr_rst_busy_UNCONNECTED
);
end STRUCTURE;
| gpl-3.0 | d983ad4f3667187bb0ccbbc80d75ce8f | 0.572808 | 2.759291 | false | false | false | false |
rflamino/StellaBlue | core/TIA/src/TIA.vhd | 1 | 45,101 | -- TV Interface Adapter (TIA)
-- Copyright 2006, 2010 Retromaster
--
-- This file is part of A2601.
--
-- A2601 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License,
-- or any later version.
--
-- A2601 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with A2601. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
entity lfsr6 is
port(clk: in std_logic;
prst: in std_logic;
cnt: in std_logic;
o: out std_logic_vector(5 downto 0)
);
end lfsr6;
architecture arch of lfsr6 is
signal d: std_logic_vector(5 downto 0);
signal prst_l: std_logic := '1';
begin
o <= d;
process(clk, prst)
begin
if (clk'event and clk = '1') then
if (prst = '1' and prst_l = '0') then
prst_l <= '1';
elsif (cnt = '1') then
prst_l <= '0';
end if;
end if;
if (clk'event and clk = '1') then
if (cnt = '1') then
if (prst_l = '1') then
d <= "000000";
else
d <= (d(0) xnor d(1)) & d(5 downto 1);
end if;
end if;
end if;
end process;
end arch;
library ieee;
use ieee.std_logic_1164.all;
entity cntr2 is
port(clk: in std_logic;
rst: in std_logic;
en: in std_logic;
o: out std_logic_vector(1 downto 0)
);
end cntr2;
architecture arch of cntr2 is
signal d: std_logic_vector(1 downto 0) := "00";
begin
o <= d;
process(clk, rst)
begin
-- if (rst = '1') then
-- d <= "00";
if (clk'event and clk = '1') then
if (rst = '1') then
d <= "00";
elsif (en = '1') then
case d is
when "00" => d <= "10";
when "10" => d <= "11";
when "11" => d <= "01";
when "01" => d <= "00";
when others => null;
end case;
end if;
end if;
end process;
end arch;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cntr3 is
port(clk: in std_logic;
rst: in std_logic;
en: in std_logic;
o: out std_logic_vector(2 downto 0)
);
end cntr3;
architecture arch of cntr3 is
signal d: unsigned(2 downto 0) := "000";
begin
o <= std_logic_vector(d);
process(clk, rst)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
d <= "000";
elsif (en = '1') then
d <= d + 1;
end if;
end if;
end process;
end arch;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.TIA_common.all;
entity audio is
port(clk: in std_logic;
cnt: in std_logic;
freq: in std_logic_vector(4 downto 0);
ctrl: in std_logic_vector(3 downto 0);
ao: out std_logic
);
end audio;
architecture arch of audio is
signal dvdr: unsigned(4 downto 0) := "00000";
signal sr4: std_logic_vector(3 downto 0) := "0000";
signal sr5: std_logic_vector(4 downto 0) := "00000";
signal sr5_tap: std_logic;
signal sr4_in: std_logic;
signal sr5_in: std_logic;
signal sr4_cnt: std_logic;
signal sr5_cnt: std_logic;
begin
process(clk)
begin
if (clk'event and clk = '1') then
if (cnt = '1') then
if (sr4_cnt = '1') then
sr4 <= sr4_in & sr4(3 downto 1);
end if;
if (sr5_cnt = '1') then
sr5 <= sr5_in & sr5(4 downto 1);
end if;
if (dvdr = unsigned(freq)) then
dvdr <= "00000";
else
dvdr <= dvdr + 1;
end if;
end if;
end if;
end process;
sr5_in <= '1' when
(ctrl = "0000") or
(sr5_tap = '1') or
(sr5 = "00000" and (ctrl(0) = '1' or ctrl(1) = '1' or sr4 = "1111"))
else '0';
sr4_in <= '1' when
(ctrl = "0000") or
(ctrl(3 downto 2) = "00" and (sr4 = "1111" or ((sr4(1) xnor sr4(0)) = '1'))) or
(ctrl(3 downto 2) = "11" and (sr4(3 downto 1) = "101" or sr4(1) = '0')) or
(ctrl(3 downto 2) = "01" and sr4(3) = '0') or
(ctrl(3 downto 2) = "10" and sr5(0) = '1')
else '0';
sr5_tap <= sr5(0) xor sr4(0) when (ctrl(1 downto 0) = "00") else sr5(0) xor sr5(3);
sr5_cnt <= '1' when (dvdr = unsigned(freq)) else '0'; -- CHECKME
sr4_cnt <= '1' when
(dvdr = unsigned(freq) and (
(ctrl(1 downto 0) = "10" and sr5(4 downto 1) = "0001") or
(ctrl(1 downto 0) = "11" and sr5(0) = '1') or
(ctrl(1) = '0')))
else '0';
ao <= sr4(0);
end arch;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity player is
port(clk: in std_logic;
prst: in std_logic;
count: in std_logic;
nusiz: in std_logic_vector(2 downto 0);
reflect: in std_logic;
grpnew: in std_logic_vector(7 downto 0);
grpold: in std_logic_vector(7 downto 0);
vdel: in std_logic;
pix: out std_logic
);
end player;
architecture arch of player is
component cntr2 is
port(clk: in std_logic;
rst: in std_logic;
en: in std_logic;
o: out std_logic_vector(1 downto 0)
);
end component;
component cntr3 is
port(clk: in std_logic;
rst: in std_logic;
en: in std_logic;
o: out std_logic_vector(2 downto 0)
);
end component;
component lfsr6 is
port(clk: in std_logic;
prst: in std_logic;
cnt: in std_logic;
o: out std_logic_vector(5 downto 0)
);
end component;
signal lfsr_out: std_logic_vector(5 downto 0);
signal lfsr_rst: std_logic;
signal lfsr_cnt: std_logic;
signal cntr_out: std_logic_vector(1 downto 0);
signal cntr_rst: std_logic;
signal cntr_en: std_logic;
signal scan_out: std_logic_vector(2 downto 0);
signal scan_clk: std_logic := '0';
signal scan_en: std_logic := '0';
signal scan_cnt: std_logic;
signal start: std_logic := '0';
signal scan_adr: std_logic_vector(2 downto 0);
signal pix_sel: std_logic_vector(1 downto 0);
signal ph0: std_logic;
signal ph1: std_logic;
signal ph1_edge: std_logic;
begin
lfsr: lfsr6 port map(clk, lfsr_rst, lfsr_cnt, lfsr_out);
cntr: cntr2 port map(clk, cntr_rst, cntr_en, cntr_out);
scan: cntr3 port map(clk, '0', scan_cnt, scan_out);
ph0 <= '1' when (cntr_out = "00") else '0';
ph1_edge <= '1' when (cntr_out = "10") else '0';
ph1 <= '1' when (cntr_out = "11") else '0';
cntr_rst <= prst;
cntr_en <= count;
lfsr_rst <= '1' when (lfsr_out = "101101") or (lfsr_out = "111111") or (prst = '1') else '0';
lfsr_cnt <= '1' when (ph1_edge = '1') and (count = '1') else '0';
process(clk, count)
begin
if (clk'event and clk = '1' and count = '1') then
if (ph1_edge = '1') then
if (lfsr_out = "101101") or
((lfsr_out = "111000") and ((nusiz = "001") or (nusiz = "011"))) or
((lfsr_out = "101111") and ((nusiz = "011") or (nusiz = "010") or (nusiz = "110"))) or
((lfsr_out = "111001") and ((nusiz = "100") or (nusiz = "110"))) then
start <= '1';
else
start <= '0';
end if;
end if;
end if;
end process;
process(clk, scan_clk, start, scan_out, count)
begin
if (clk'event and clk = '1' and count = '1') then
if (scan_clk = '1') then
if (start = '1') then
scan_en <= '1';
elsif (scan_out = "111") then
scan_en <= '0';
end if;
end if;
end if;
end process;
process (clk, ph0, ph1, count)
begin
if (clk'event and clk = '1' and count = '1') then
if (nusiz = "111") then
scan_clk <= ph1;
elsif (nusiz = "101") then
scan_clk <= ph0 or ph1;
else
scan_clk <= '1';
end if;
end if;
end process;
scan_adr <= scan_out when reflect = '1' else not scan_out;
scan_cnt <= scan_en and scan_clk and count;
pix_sel <= scan_en & vdel;
with pix_sel select pix <=
grpnew(to_integer(unsigned(scan_adr))) when "10",
grpold(to_integer(unsigned(scan_adr))) when "11",
'0' when others;
end arch;
library ieee;
use ieee.std_logic_1164.all;
entity missile is
port(clk: in std_logic;
prst: in std_logic;
count: in std_logic;
enable: in std_logic;
nusiz: in std_logic_vector(2 downto 0);
size: in std_logic_vector(1 downto 0);
pix: out std_logic
);
end missile;
architecture arch of missile is
component cntr2 is
port(clk: in std_logic;
rst: in std_logic;
en: in std_logic;
o: out std_logic_vector(1 downto 0)
);
end component;
component lfsr6 is
port(clk: in std_logic;
prst: in std_logic;
cnt: in std_logic;
o: out std_logic_vector(5 downto 0)
);
end component;
signal lfsr_out: std_logic_vector(5 downto 0);
signal lfsr_rst: std_logic;
signal lfsr_cnt: std_logic;
signal cntr_out: std_logic_vector(1 downto 0);
signal cntr_rst: std_logic;
signal cntr_en: std_logic;
signal start1: std_logic := '0';
signal start2: std_logic := '0';
signal ph1: std_logic;
signal ph1_edge: std_logic;
begin
lfsr: lfsr6 port map(clk, lfsr_rst, lfsr_cnt, lfsr_out);
cntr: cntr2 port map(clk, cntr_rst, cntr_en, cntr_out);
ph1_edge <= '1' when (cntr_out = "10") else '0';
ph1 <= '1' when (cntr_out = "11") else '0';
cntr_rst <= prst;
cntr_en <= count;
lfsr_rst <= '1' when (lfsr_out = "101101") or (lfsr_out = "111111") or (prst = '1') else '0';
lfsr_cnt <= '1' when (ph1_edge = '1') and (count = '1') else '0';
process(clk)
begin
if (clk'event and clk = '1') then
if (ph1_edge = '1') then
if (lfsr_out = "101101") or
((lfsr_out = "111000") and ((nusiz = "001") or (nusiz = "011"))) or
((lfsr_out = "101111") and ((nusiz = "011") or (nusiz = "010") or (nusiz = "110"))) or
((lfsr_out = "111001") and ((nusiz = "100") or (nusiz = "110"))) then
start1 <= '1';
else
start1 <= '0';
end if;
start2 <= start1;
end if;
end if;
end process;
pix <= '1' when
(enable = '1' and (
(start1 = '1' and (
(size(1) = '1') or
(ph1 = '1') or
(cntr_out(0) = '1' and size(0) = '1'))) or
(start2 = '1' and size = "11")))
else '0';
end arch;
-- XYZ
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity paddle is
port(clk: in std_logic;
value: in std_logic_vector(7 downto 0);
rst: in std_logic;
o: out std_logic
);
end paddle;
architecture arch of paddle is
begin
process(clk, rst)
variable cnt: integer range 0 to 190;
begin
if( rst = '1' ) then
-- map -128..127 -> 190..0
cnt := to_integer(96 + signed(value)/2 + signed(value)/4);
elsif (clk'event and clk = '1') then
if(cnt /= 190) then
cnt := cnt + 1;
end if;
end if;
-- return 1 if counter has "discharged"
if(cnt = 190) then
o <= '1';
else
o <= '0';
end if;
end process;
end arch;
library ieee;
use ieee.std_logic_1164.all;
entity ball is
port(clk: in std_logic;
prst: in std_logic;
count: in std_logic;
ennew: in std_logic;
enold: in std_logic;
vdel: in std_logic;
size: in std_logic_vector(1 downto 0);
pix: out std_logic
);
end ball;
architecture arch of ball is
component cntr2 is
port(clk: in std_logic;
rst: in std_logic;
en: in std_logic;
o: out std_logic_vector(1 downto 0)
);
end component;
component lfsr6 is
port(clk: in std_logic;
prst: in std_logic;
cnt: in std_logic;
o: out std_logic_vector(5 downto 0)
);
end component;
signal lfsr_out: std_logic_vector(5 downto 0);
signal lfsr_rst: std_logic;
signal lfsr_cnt: std_logic;
signal cntr_out: std_logic_vector(1 downto 0);
signal cntr_rst: std_logic;
signal cntr_en: std_logic;
signal start1: std_logic := '0';
signal start2: std_logic := '0';
signal ph1: std_logic;
signal ph1_edge: std_logic;
begin
lfsr: lfsr6 port map(clk, lfsr_rst, lfsr_cnt, lfsr_out);
cntr: cntr2 port map(clk, cntr_rst, cntr_en, cntr_out);
ph1_edge <= '1' when (cntr_out = "10") else '0';
ph1 <= '1' when (cntr_out = "11") else '0';
cntr_rst <= prst;
cntr_en <= count;
lfsr_rst <= '1' when (lfsr_out = "101101") or (lfsr_out = "111111") or (prst = '1') else '0';
lfsr_cnt <= '1' when (ph1_edge = '1') and (count = '1') else '0';
process(clk)
begin
if (clk'event and clk = '1') then
if (ph1_edge = '1') then
if (lfsr_out = "101101") or (prst = '1') then
start1 <= '1';
else
start1 <= '0';
end if;
start2 <= start1;
end if;
end if;
end process;
pix <= '1' when
((ennew = '1' and vdel = '0') or (enold = '1' and vdel = '1')) and (
(start1 = '1' and (
(size(1) = '1') or
(ph1 = '1') or
(cntr_out(0) = '1' and size(0) = '1'))) or
(start2 = '1' and size = "11"))
else '0';
end arch;
library ieee;
use ieee.std_logic_1164.all;
entity mux20 is
port(i: in std_logic_vector(19 downto 0);
a: in std_logic_vector(4 downto 0);
o: out std_logic
);
end mux20;
architecture arch of mux20 is
begin
with a select o <=
i(0) when "00000",
i(1) when "00001",
i(2) when "00010",
i(3) when "00011",
i(11) when "00100",
i(10) when "00101",
i(9) when "00110",
i(8) when "00111",
i(7) when "01000",
i(6) when "01001",
i(5) when "01010",
i(4) when "01011",
i(12) when "01100",
i(13) when "01101",
i(14) when "01110",
i(15) when "01111",
i(16) when "10000",
i(17) when "10001",
i(18) when "10010",
i(19) when "10011",
'-' when others;
end arch;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.TIA_common.all;
use work.TIA_NTSCLookups.all;
entity TIA is
port(vid_clk: in std_logic;
cs: in std_logic;
r: in std_logic;
a: in std_logic_vector(5 downto 0);
d: inout std_logic_vector(7 downto 0);
colu: out std_logic_vector(6 downto 0);
csyn: out std_logic;
hsyn: out std_logic;
vsyn: out std_logic;
rgbx2: out std_logic_vector(23 downto 0);
cv: out std_logic_vector(7 downto 0) := "00000000";
rdy: out std_logic;
ph0: out std_logic;
ph1: out std_logic;
au0: out std_logic;
au1: out std_logic;
av0: out std_logic_vector(3 downto 0);
av1: out std_logic_vector(3 downto 0);
paddle_0: in std_logic_vector(7 downto 0);
paddle_1: in std_logic_vector(7 downto 0);
paddle_2: in std_logic_vector(7 downto 0);
paddle_3: in std_logic_vector(7 downto 0);
paddle_ena: in std_logic;
inpt4: in std_logic;
inpt5: in std_logic;
pal: in std_logic := '0'
);
end TIA;
architecture arch of TIA is
-- COMPONENT VGA_SCANDBL
-- PORT(
-- I : IN std_logic_vector(6 downto 0);
-- I_HSYNC : IN std_logic;
-- I_VSYNC : IN std_logic;
-- CLK : IN std_logic;
-- CLK_X2 : IN std_logic;
-- O : OUT std_logic_vector(6 downto 0);
-- O_HSYNC : OUT std_logic;
-- O_VSYNC : OUT std_logic
-- );
-- END COMPONENT;
--
-- COMPONENT VGAColorTable
-- PORT(
-- clk : IN std_logic;
-- lum : IN std_logic_vector(3 downto 0);
-- hue : IN std_logic_vector(3 downto 0);
-- mode : IN std_logic_vector(1 downto 0);
-- outColor : OUT std_logic_vector(23 downto 0)
-- );
-- END COMPONENT;
component cntr2 is
port(clk: in std_logic;
rst: in std_logic;
en: in std_logic;
o: out std_logic_vector(1 downto 0)
);
end component;
component lfsr6 is
port(clk: in std_logic;
prst: in std_logic;
cnt: in std_logic;
o: out std_logic_vector(5 downto 0)
);
end component;
component audio is
port(clk: in std_logic;
cnt: in std_logic;
freq: in std_logic_vector(4 downto 0);
ctrl: in std_logic_vector(3 downto 0);
ao: out std_logic
);
end component;
component player is
port(clk: in std_logic;
prst: in std_logic;
count: in std_logic;
nusiz: in std_logic_vector(2 downto 0);
reflect: in std_logic;
grpnew: in std_logic_vector(7 downto 0);
grpold: in std_logic_vector(7 downto 0);
vdel: in std_logic;
pix: out std_logic
);
end component;
component missile is
port(clk: in std_logic;
prst: in std_logic;
count: in std_logic;
enable: in std_logic;
nusiz: in std_logic_vector(2 downto 0);
size: in std_logic_vector(1 downto 0);
pix: out std_logic
);
end component;
component ball is
port(clk: in std_logic;
prst: in std_logic;
count: in std_logic;
ennew: in std_logic;
enold: in std_logic;
vdel: in std_logic;
size: in std_logic_vector(1 downto 0);
pix: out std_logic
);
end component;
component mux20 is
port(i: in std_logic_vector(19 downto 0);
a: in std_logic_vector(4 downto 0);
o: out std_logic
);
end component;
component paddle is
port(clk: in std_logic;
value: in std_logic_vector(7 downto 0);
rst: in std_logic;
o: out std_logic
);
end component;
signal h_lfsr_out: std_logic_vector(5 downto 0);
signal h_lfsr_rst: std_logic;
signal h_lfsr_cnt: std_logic;
signal h_cntr_out: std_logic_vector(1 downto 0);
signal h_cntr_rst: std_logic;
signal hsync: std_logic := '0';
signal cburst: std_logic := '0';
signal hblank: std_logic := '1';
signal hmove: std_logic := '0';
signal hmove_set: std_logic;
signal hmove_cntr: unsigned(3 downto 0) := "1111";
signal hmove_cntr_sl: std_logic_vector(3 downto 0);
signal p0_rst: std_logic;
signal p0_nusiz: std_logic_vector(2 downto 0) := "000";
signal p0_reflect: std_logic;
signal p0_grpnew: std_logic_vector(7 downto 0);
signal p0_grpold: std_logic_vector(7 downto 0);
signal p0_vdel: std_logic := '0';
signal p0_pix: std_logic;
signal p0_colu: std_logic_vector(6 downto 0) := "0000000";
signal p0_hmove: std_logic_vector(3 downto 0);
signal p0_count: std_logic;
signal p0_ec: std_logic := '0';
signal p1_rst: std_logic;
signal p1_nusiz: std_logic_vector(2 downto 0) := "000";
signal p1_reflect: std_logic;
signal p1_grpnew: std_logic_vector(7 downto 0);
signal p1_grpold: std_logic_vector(7 downto 0);
signal p1_vdel: std_logic := '0';
signal p1_pix: std_logic;
signal p1_colu: std_logic_vector(6 downto 0) := "0000000";
signal p1_hmove: std_logic_vector(3 downto 0);
signal p1_count: std_logic;
signal p1_ec: std_logic := '0';
signal m0_rst: std_logic;
signal m0_enable: std_logic;
signal m0_size: std_logic_vector(1 downto 0) := "00";
signal m0_pix: std_logic;
signal m0_hmove: std_logic_vector(3 downto 0);
signal m0_count: std_logic;
signal m0_ec: std_logic := '0';
signal m1_rst: std_logic;
signal m1_enable: std_logic;
signal m1_size: std_logic_vector(1 downto 0) := "00";
signal m1_pix: std_logic;
signal m1_hmove: std_logic_vector(3 downto 0);
signal m1_count: std_logic;
signal m1_ec: std_logic := '0';
signal bl_rst: std_logic;
signal bl_ennew: std_logic;
signal bl_enold: std_logic;
signal bl_vdel: std_logic := '0';
signal bl_size: std_logic_vector(1 downto 0);
signal bl_pix: std_logic;
signal bl_hmove: std_logic_vector(3 downto 0);
signal bl_count: std_logic;
signal bl_ec: std_logic := '0';
signal pf_gr: std_logic_vector(19 downto 0);
signal pf_adr: unsigned(4 downto 0) := "00000";
signal pf_pix: std_logic;
signal pf_mux_out: std_logic;
signal pf_reflect: std_logic;
signal pf_score: std_logic;
signal pf_priority: std_logic := '0';
signal pf_colu: std_logic_vector(6 downto 0) := "0000000";
signal bk_colu: std_logic_vector(6 downto 0) := "0000000";
signal a0_freq: std_logic_vector(4 downto 0);
signal a0_ctrl: std_logic_vector(3 downto 0);
signal a0_vol: std_logic_vector(3 downto 0) := "0000";
signal a1_freq: std_logic_vector(4 downto 0);
signal a1_ctrl: std_logic_vector(3 downto 0);
signal a1_vol: std_logic_vector(3 downto 0) := "0000";
signal wsync: std_logic := '0';
signal vsync: std_logic := '0';
signal vblank: std_logic := '0';
signal center: std_logic := '0';
signal pf_cnt: std_logic := '0';
signal cx: std_logic_vector(14 downto 0) := "000000000000000";
signal cx_clr: std_logic;
signal clk_dvdr: std_logic_vector(1 downto 0) := "01";
signal phi0: std_logic := '0';
signal phi1: std_logic := '1';
signal inpt45_len: std_logic := '0';
signal inpt45_rst: std_logic;
signal inpt4_l: std_logic := '1';
signal inpt5_l: std_logic := '1';
signal au_cnt: std_logic;
signal sec_dl: std_logic_vector(1 downto 0) := "00";
signal sec: std_logic;
signal hh0: std_logic;
signal hh0_edge: std_logic;
signal hh1: std_logic;
signal hh1_edge: std_logic;
signal clk, clkx2: std_logic;
signal sync: std_logic;
signal blank: std_logic;
signal int_colu: std_logic_vector(6 downto 0) := "0000000";
signal lum_lu: unsigned(7 downto 0);
signal col_lut_idx: std_logic_vector(7 downto 0);
signal col_lu: unsigned(7 downto 0);
signal vid_clk_dvdr: unsigned(3 downto 0) := "0000";
signal vga_colu: std_logic_vector(6 downto 0);
signal inpt03_chg: std_logic;
signal inpt0: std_logic;
signal inpt1: std_logic;
signal inpt2: std_logic;
signal inpt3: std_logic;
begin
paddle0: paddle port map(hsync, paddle_0, inpt03_chg, inpt0);
paddle1: paddle port map(hsync, paddle_1, inpt03_chg, inpt1);
paddle2: paddle port map(hsync, paddle_2, inpt03_chg, inpt2);
paddle3: paddle port map(hsync, paddle_3, inpt03_chg, inpt3);
h_cntr: cntr2 port map(clk, h_cntr_rst, '1', h_cntr_out);
lfsr: lfsr6 port map(clk, h_lfsr_rst, h_lfsr_cnt, h_lfsr_out);
pf_mux: mux20 port map(pf_gr, std_logic_vector(pf_adr), pf_mux_out);
hh0_edge <= '1' when (h_cntr_out = "01") else '0';
hh0 <= '1' when (h_cntr_out = "00") else '0';
hh1_edge <= '1' when (h_cntr_out = "10") else '0';
hh1 <= '1' when (h_cntr_out = "11") else '0';
aud0: audio port map(clk, au_cnt, a0_freq, a0_ctrl, au0);
aud1: audio port map(clk, au_cnt, a1_freq, a1_ctrl, au1);
av0 <= a0_vol;
av1 <= a1_vol;
au_cnt <= '1' when (h_lfsr_out = "110111" or h_lfsr_out = "101100") and (h_lfsr_cnt = '1') else '0';
h_lfsr_rst <= '1' when (h_lfsr_out = "010100") else '0';
h_lfsr_cnt <= '1' when (hh1_edge = '1') else '0';
h_cntr_rst <= '1' when (r = '0') and (cs = '1') and (a = A_RSYNC) else '0';
h_decode: process(clk, h_lfsr_out)
begin
if (clk'event and clk = '1') then
if (hh1_edge = '1') then
case h_lfsr_out is
when "111100" =>
hsync <= '1';
when "110111" =>
hsync <= '0';
cburst <= '1';
when "001111" =>
cburst <= '0';
when "111001" =>
pf_cnt <= '1';
when "011100" =>
hblank <= hmove;
when "010111" =>
hblank <= '0';
when "101001" =>
center <= '0';
when "010100" =>
hblank <= '1';
pf_cnt <= '0';
when "011000" =>
center <= '1';
when others => null;
end case;
end if;
end if;
end process;
process(clk)
begin
if (clk'event and clk = '1') then
if (h_lfsr_out = "010111") and (hh1_edge = '1') then
hmove <= '0';
elsif (hmove_set = '1') then
hmove <= '1';
end if;
end if;
end process;
process(clk)
begin
if (clk'event and clk = '1') then
if (h_lfsr_out = "000000" and hh1_edge = '1') then
wsync <= '0';
elsif (r = '0') and (cs = '1') and (a = A_WSYNC) then
wsync <= '1';
end if;
end if;
end process;
csyn <= (vsync nand hsync) and (vsync or hsync);
-- vsyn <= vsync;
-- hsyn <= hsync;
rdy <= '0' when (wsync = '1') else '1';
p0: player
port map(clk, p0_rst, p0_count, p0_nusiz, p0_reflect,
p0_grpnew, p0_grpold, p0_vdel, p0_pix);
p1: player
port map(clk, p1_rst, p1_count, p1_nusiz, p1_reflect,
p1_grpnew, p1_grpold, p1_vdel, p1_pix);
m0: missile
port map(clk, m0_rst, m0_count, m0_enable, p0_nusiz, m0_size, m0_pix);
m1: missile
port map(clk, m1_rst, m1_count, m1_enable, p1_nusiz, m1_size, m1_pix);
bl: ball
port map(clk, bl_rst, bl_count, bl_ennew, bl_enold, bl_vdel, bl_size, bl_pix);
pf_output: process(clk, h_lfsr_cnt)
begin
if (clk'event and clk = '1') then
if (h_lfsr_cnt = '1') then
if (pf_cnt = '1') then
if (pf_adr = "10011") and (center = '0') and (pf_reflect = '0') then
pf_adr <= "00000";
elsif (pf_reflect = '1') and (center = '1') and not (pf_adr = "00000") then
pf_adr <= pf_adr - 1;
elsif not (pf_adr = "10011") then
pf_adr <= pf_adr + 1;
end if;
else
pf_adr <= "00000";
end if;
pf_pix <= pf_mux_out;
end if;
end if;
end process;
p0_rst <= '1' when (r = '0') and (cs = '1') and (a = A_RESP0) and (phi0 = '0') else '0';
p1_rst <= '1' when (r = '0') and (cs = '1') and (a = A_RESP1) and (phi0 = '0') else '0';
m0_rst <= '1' when (r = '0') and (cs = '1') and (a = A_RESM0) and (phi0 = '0') else '0';
m1_rst <= '1' when (r = '0') and (cs = '1') and (a = A_RESM1) and (phi0 = '0') else '0';
bl_rst <= '1' when (r = '0') and (cs = '1') and (a = A_RESBL) and (phi0 = '0') else '0';
p0_count <= '1' when (hblank = '0') or (p0_ec = '1' and hh0 = '1') else '0';
p1_count <= '1' when (hblank = '0') or (p1_ec = '1' and hh0 = '1') else '0';
m0_count <= '1' when (hblank = '0') or (m0_ec = '1' and hh0 = '1') else '0';
m1_count <= '1' when (hblank = '0') or (m1_ec = '1' and hh0 = '1') else '0';
bl_count <= '1' when (hblank = '0') or (bl_ec = '1' and hh0 = '1') else '0';
hmove_set <= '1' when (a = A_HMOVE) and (r = '0') and (cs = '1') else '0';
cx_clr <= '1' when (a = A_CXCLR) and (r = '0') and (cs = '1') else '0';
inpt45_rst <= '1' when (a = A_VBLANK) and (r = '0') and (cs = '1') else '0';
process(clk, phi1, a, d, r, cs, cx, inpt45_len, inpt4_l, inpt4, inpt5_l, inpt5)
begin
if (r = '1') and (cs = '1') then
d(5 downto 0) <= "000000";
case a(3 downto 0) is
when A_CXM0P =>
d(7 downto 6) <= cx(1 downto 0);
when A_CXM1P =>
d(7 downto 6) <= cx(3 downto 2);
when A_CXP0FB =>
d(7 downto 6) <= cx(5 downto 4);
when A_CXP1FB =>
d(7 downto 6) <= cx(7 downto 6);
when A_CXM0FB =>
d(7 downto 6) <= cx(9 downto 8);
when A_CXM1FB =>
d(7 downto 6) <= cx(11 downto 10);
when A_CXBLPF =>
d(7) <= cx(12);
d(6) <= 'Z';
when A_CXPPMM =>
d(7 downto 6) <= cx(14 downto 13);
when A_INPT0 =>
if(paddle_ena = '1') then
d(7) <= inpt0;
else
d(7) <= '1';
end if;
d(6) <= '0';
when A_INPT1 =>
if(paddle_ena = '1') then
d(7) <= inpt1;
else
d(7) <= '1';
end if;
d(6) <= '0';
when A_INPT2 =>
if(paddle_ena = '1') then
d(7) <= inpt2;
else
d(7) <= '1';
end if;
d(6) <= '0';
when A_INPT3 =>
if(paddle_ena = '1') then
d(7) <= inpt3;
else
d(7) <= '1';
end if;
d(6) <= '0';
when A_INPT4 =>
if (inpt45_len = '1') then
d(7) <= inpt4_l;
else
d(7) <= inpt4;
end if;
--d(6) <= 'Z';
d(6) <= '0';
when A_INPT5 =>
if (inpt45_len = '1') then
d(7) <= inpt5_l;
else
d(7) <= inpt5;
end if;
--d(6) <= 'Z';
d(6) <= '0';
when others =>
d(7 downto 6) <= "--";
end case;
else
d <= "ZZZZZZZZ";
end if;
if (phi1'event and phi1 = '0') then
if (r = '0') and (cs = '1') then
case a is
when A_VSYNC =>
vsync <= d(1);
when A_VBLANK =>
inpt03_chg <= d(7);
inpt45_len <= d(6);
vblank <= d(1);
when A_PF0 =>
pf_gr(3 downto 0) <= d(7 downto 4);
when A_PF1 =>
pf_gr(11 downto 4) <= d;
when A_PF2 =>
pf_gr(19 downto 12) <= d;
when A_CTRLPF =>
pf_reflect <= d(0);
pf_score <= d(1);
pf_priority <= d(2);
bl_size <= d(5 downto 4);
when A_NUSIZ0 =>
p0_nusiz <= d(2 downto 0);
m0_size <= d(5 downto 4);
when A_NUSIZ1 =>
p1_nusiz <= d(2 downto 0);
m1_size <= d(5 downto 4);
when A_HMCLR =>
p0_hmove <= "0000";
p1_hmove <= "0000";
m0_hmove <= "0000";
m1_hmove <= "0000";
bl_hmove <= "0000";
when A_HMP0 =>
p0_hmove <= d(7 downto 4);
when A_HMP1 =>
p1_hmove <= d(7 downto 4);
when A_HMM0 =>
m0_hmove <= d(7 downto 4);
when A_HMM1 =>
m1_hmove <= d(7 downto 4);
when A_HMBL =>
bl_hmove <= d(7 downto 4);
when A_ENAM0 =>
m0_enable <= d(1);
when A_ENAM1 =>
m1_enable <= d(1);
when A_ENABL =>
bl_enold <= bl_ennew;
bl_ennew <= d(1);
when A_GRP0 =>
p1_grpold <= p1_grpnew;
p0_grpnew <= d;
when A_GRP1 =>
p0_grpold <= p0_grpnew;
p1_grpnew <= d;
when A_REFP0 =>
p0_reflect <= d(3);
when A_REFP1 =>
p1_reflect <= d(3);
when A_VDELP0 =>
p0_vdel <= d(0);
when A_VDELP1 =>
p1_vdel <= d(0);
when A_VDELBL =>
bl_vdel <= d(0);
when A_COLUP0 =>
p0_colu <= d(7 downto 1);
when A_COLUP1 =>
p1_colu <= d(7 downto 1);
when A_COLUPF =>
pf_colu <= d(7 downto 1);
when A_COLUBK =>
bk_colu <= d(7 downto 1);
when A_AUDF0 =>
a0_freq <= d(4 downto 0);
when A_AUDF1 =>
a1_freq <= d(4 downto 0);
when A_AUDC0 =>
a0_ctrl <= d(3 downto 0);
when A_AUDC1 =>
a1_ctrl <= d(3 downto 0);
when A_AUDV0 =>
a0_vol <= d(3 downto 0);
when A_AUDV1 =>
a1_vol <= d(3 downto 0);
when others => null;
end case;
end if;
end if;
end process;
output: process(
clk, hblank, pf_priority, p0_pix, p1_pix, m0_pix, m1_pix,
bl_pix, pf_pix, p0_colu, p1_colu, pf_colu, bk_colu)
begin
if (clk = '1' and clk'event) then
if (hblank = '1' or vblank = '1') then
int_colu <= "0000000";
elsif (pf_priority = '0') then
if (p0_pix = '1' or m0_pix = '1') then
int_colu <= p0_colu;
elsif (p1_pix = '1' or m1_pix = '1') then
int_colu <= p1_colu;
elsif (pf_pix = '1' or bl_pix = '1') then
int_colu <= pf_colu;
else
-- int_colu <= "0110010";
int_colu <= bk_colu;
end if;
else
if (pf_pix = '1' or bl_pix = '1') then
int_colu <= pf_colu;
elsif (p0_pix = '1' or m0_pix = '1') then
int_colu <= p0_colu;
elsif (p1_pix = '1' or m1_pix = '1') then
int_colu <= p1_colu;
else
-- int_colu <= "0110010";
int_colu <= bk_colu;
end if;
end if;
end if;
end process;
colu <= int_colu;
sec_delay: process(clk, r)
begin
if (clk'event and clk = '1') then
if (hmove_set = '1') then
sec_dl(1) <= '1';
elsif (sec = '1') then
sec_dl(1) <= '0';
end if;
if (hh0_edge = '1') then
sec_dl(0) <= sec_dl(1);
elsif (hh1_edge = '1') then
sec <= sec_dl(0);
end if;
end if;
end process;
hmove_cntr_sl <= std_logic_vector(hmove_cntr);
motion: process(clk, r, hmove_set)
begin
if (clk'event and clk = '1') then
if (hh1_edge = '1') then
if (sec = '1') then
hmove_cntr <= hmove_cntr + 1;
end if;
if (p0_hmove(3) /= hmove_cntr(3)) and
(p0_hmove(2 downto 0) = hmove_cntr_sl(2 downto 0)) then
p0_ec <= '0';
elsif (sec = '1') then
p0_ec <= '1';
end if;
if (p1_hmove(3) /= hmove_cntr(3)) and
(p1_hmove(2 downto 0) = hmove_cntr_sl(2 downto 0)) then
p1_ec <= '0';
elsif (sec = '1') then
p1_ec <= '1';
end if;
if (m0_hmove(3) /= hmove_cntr(3)) and
(m0_hmove(2 downto 0) = hmove_cntr_sl(2 downto 0)) then
m0_ec <= '0';
elsif (sec = '1') then
m0_ec <= '1';
end if;
if (m1_hmove(3) /= hmove_cntr(3)) and
(m1_hmove(2 downto 0) = hmove_cntr_sl(2 downto 0)) then
m1_ec <= '0';
elsif (sec = '1') then
m1_ec <= '1';
end if;
if (bl_hmove(3) /= hmove_cntr(3)) and
(bl_hmove(2 downto 0) = hmove_cntr_sl(2 downto 0)) then
bl_ec <= '0';
elsif (sec = '1') then
bl_ec <= '1';
end if;
if not (hmove_cntr = "0000") then
hmove_cntr <= hmove_cntr + 1;
end if;
end if;
end if;
end process;
collision: process(clk, cx_clr)
begin
if (clk'event and clk = '1') then
if (cx_clr = '1') then
cx <= "000000000000000";
else
if (m0_pix = '1' and p0_pix = '1') then
cx(0) <= '1';
end if;
if (m0_pix = '1' and p1_pix = '1') then
cx(1) <= '1';
end if;
if (m1_pix = '1' and p1_pix = '1') then
cx(2) <= '1';
end if;
if (m1_pix = '1' and p0_pix = '1') then
cx(3) <= '1';
end if;
if (bl_pix = '1' and p0_pix = '1') then
cx(4) <= '1';
end if;
if (pf_pix = '1' and p0_pix = '1') then
cx(5) <= '1';
end if;
if (bl_pix = '1' and p1_pix = '1') then
cx(6) <= '1';
end if;
if (pf_pix = '1' and p1_pix = '1') then
cx(7) <= '1';
end if;
if (bl_pix = '1' and m0_pix = '1') then
cx(8) <= '1';
end if;
if (pf_pix = '1' and m0_pix = '1') then
cx(9) <= '1';
end if;
if (bl_pix = '1' and m1_pix = '1') then
cx(10) <= '1';
end if;
if (pf_pix = '1' and m1_pix = '1') then
cx(11) <= '1';
end if;
if (pf_pix = '1' and bl_pix = '1') then
cx(12) <= '1';
end if;
if (m0_pix = '1' and m1_pix = '1') then
cx(13) <= '1';
end if;
if (p0_pix = '1' and p1_pix = '1') then
cx(14) <= '1';
end if;
end if;
end if;
end process;
ph0 <= phi0;
ph1 <= phi1;
process(clk)
begin
if (clk'event and clk = '1') then
if (h_lfsr_out = "010100" and hh1_edge = '1') then
clk_dvdr <= "01";
phi0 <= '0';
phi1 <= '0';
else
case clk_dvdr is
when "00" =>
clk_dvdr <= "01";
phi0 <= '0';
phi1 <= '1';
when "01" =>
clk_dvdr <= "11";
phi0 <= '0';
phi1 <= '0';
when "11" =>
clk_dvdr <= "00";
phi0 <= '1';
phi1 <= '1';
when others =>
null;
end case;
end if;
end if;
end process;
process(clk, inpt45_rst, inpt45_len, inpt4, inpt5)
begin
if (clk'event and clk = '1') then
if (inpt45_rst = '1') then
inpt4_l <= '1';
inpt5_l <= '1';
elsif (inpt45_len = '1') then
if (inpt4 = '0') then
inpt4_l <= '0';
end if;
if (inpt5 = '0') then
inpt5_l <= '0';
end if;
end if;
end if;
end process;
sync <= hsync xor vsync;
blank <= hblank or vblank;
process(vid_clk, vid_clk_dvdr)
begin
if (vid_clk'event and vid_clk = '1') then
vid_clk_dvdr <= vid_clk_dvdr + 1;
end if;
end process;
clk <= vid_clk_dvdr(3);
clkx2 <= vid_clk_dvdr(2);
-- Inst_VGA_SCANDBL: VGA_SCANDBL PORT MAP(
-- I => int_colu,
-- I_HSYNC => hsync,
-- I_VSYNC => vsync,
-- O => vga_colu,
-- O_HSYNC => hsyn,
-- O_VSYNC => vsyn,
-- CLK => clk,
-- CLK_X2 => clkx2
-- );
-- Inst_VGAColorTable: VGAColorTable PORT MAP(
-- clk => clkx2,
-- lum => '0' & vga_colu(2 downto 0),
-- hue => vga_colu(6 downto 3),
-- mode => '0' & pal, -- 00 = NTSC, 01 = PAL
-- outColor => rgbx2
-- );
-- O_VIDEO_R(3 downto 1) <= video_r_x2;
-- O_VIDEO_G(3 downto 1) <= video_g_x2;
-- O_VIDEO_B(3 downto 2) <= video_b_x2;
-- O_HSYNC <= hsync_x2;
-- O_VSYNC <= vsyn;
col_lut_idx <=
"0001" & (not vid_clk_dvdr(3)) & vid_clk_dvdr(2) & vid_clk_dvdr(1) & vid_clk_dvdr(0) when (cburst = '1') else
int_colu(6 downto 3) & (not vid_clk_dvdr(3)) & vid_clk_dvdr(2) & vid_clk_dvdr(1) & vid_clk_dvdr(0);
col_lu <= col_lut(to_integer(unsigned(col_lut_idx)));
lum_lu <= lum_lut(to_integer(unsigned(int_colu(2 downto 0))));
-- Composite video output
process(vid_clk)
begin
if (vid_clk'event and vid_clk = '1') then
if (sync = '1') then
cv <= std_logic_vector(sync_level);
elsif (cburst = '1') then
cv <= std_logic_vector(blank_level + col_lu);
elsif (blank = '1') then
cv <= std_logic_vector(blank_level);
else
cv <= std_logic_vector(lum_lu + col_lu);
end if;
end if;
end process;
end arch;
| mit | 8214851878fad97c1c9f2634683457b0 | 0.441831 | 3.373551 | false | false | false | false |
JuanMarcosRamirez/WeightedMedianDisenoLogico | misc/RS232/Rs232 RefProj/SourceFiles/RS232RefComp.vhd | 3 | 11,032 | ------------------------------------------------------------------------
-- RS232RefCom.vhd
------------------------------------------------------------------------
-- Author: Dan Pederson
-- Copyright 2004 Digilent, Inc.
------------------------------------------------------------------------
-- Description: This file defines a UART which tranfers data from
-- serial form to parallel form and vice versa.
------------------------------------------------------------------------
-- Revision History:
-- 07/15/04 (Created) DanP
-- 02/25/08 (Created) ClaudiaG: made use of the baudDivide constant
-- in the Clock Dividing Processes
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Rs232RefComp is
Port (
TXD : out std_logic := '1';
RXD : in std_logic;
CLK : in std_logic; --Master Clock = 50MHz
DBIN : in std_logic_vector (7 downto 0); --Data Bus in
DBOUT : out std_logic_vector (7 downto 0); --Data Bus out
RDA : inout std_logic; --Read Data Available
TBE : inout std_logic := '1'; --Transfer Bus Empty
RD : in std_logic; --Read Strobe
WR : in std_logic; --Write Strobe
PE : out std_logic; --Parity Error Flag
FE : out std_logic; --Frame Error Flag
OE : out std_logic; --Overwrite Error Flag
RST : in std_logic := '0'); --Master Reset
end Rs232RefComp;
architecture Behavioral of Rs232RefComp is
------------------------------------------------------------------------
-- Component Declarations
------------------------------------------------------------------------
------------------------------------------------------------------------
-- Local Type Declarations
------------------------------------------------------------------------
--Receive state machine
type rstate is (
strIdle, --Idle state
strEightDelay, --Delays for 8 clock cycles
strGetData, --Shifts in the 8 data bits, and checks parity
strCheckStop --Sets framing error flag if Stop bit is wrong
);
type tstate is (
sttIdle, --Idle state
sttTransfer, --Move data into shift register
sttShift --Shift out data
);
type TBEstate is (
stbeIdle,
stbeSetTBE,
stbeWaitLoad,
stbeWaitWrite
);
------------------------------------------------------------------------
-- Signal Declarations
------------------------------------------------------------------------
constant baudDivide : std_logic_vector(7 downto 0) := "10100011"; --Baud Rate dividor, set now for a rate of 9600.
--Found by dividing 50MHz by 9600 and 16.
signal rdReg : std_logic_vector(7 downto 0) := "00000000"; --Receive holding register
signal rdSReg : std_logic_vector(9 downto 0) := "1111111111"; --Receive shift register
signal tfReg : std_logic_vector(7 downto 0); --Transfer holding register
signal tfSReg : std_logic_vector(10 downto 0) := "11111111111"; --Transfer shift register
signal clkDiv : std_logic_vector(8 downto 0) := "000000000"; --used for rClk
signal rClkDiv : std_logic_vector(3 downto 0) := "0000"; --used for tClk
signal ctr : std_logic_vector(3 downto 0) := "0000"; --used for delay times
signal tfCtr : std_logic_vector(3 downto 0) := "0000"; --used to delay in transfer
signal rClk : std_logic := '0'; --Receiving Clock
signal tClk : std_logic; --Transfering Clock
signal dataCtr : std_logic_vector(3 downto 0) := "0000"; --Counts the number of read data bits
signal parError: std_logic; --Parity error bit
signal frameError: std_logic; --Frame error bit
signal CE : std_logic; --Clock enable for the latch
signal ctRst : std_logic := '0';
signal load : std_logic := '0';
signal shift : std_logic := '0';
signal par : std_logic;
signal tClkRST : std_logic := '0';
signal rShift : std_logic := '0';
signal dataRST : std_logic := '0';
signal dataIncr: std_logic := '0';
signal strCur : rstate := strIdle; --Current state in the Receive state machine
signal strNext : rstate; --Next state in the Receive state machine
signal sttCur : tstate := sttIdle; --Current state in the Transfer state machine
signal sttNext : tstate; --Next state in the Transfer staet machine
signal stbeCur : TBEstate := stbeIdle;
signal stbeNext: TBEstate;
------------------------------------------------------------------------
-- Module Implementation
------------------------------------------------------------------------
begin
frameError <= not rdSReg(9);
parError <= not ( rdSReg(8) xor (((rdSReg(0) xor rdSReg(1)) xor (rdSReg(2) xor rdSReg(3))) xor ((rdSReg(4) xor rdSReg(5)) xor (rdSReg(6) xor rdSReg(7)))) );
DBOUT <= rdReg;
tfReg <= DBIN;
par <= not ( ((tfReg(0) xor tfReg(1)) xor (tfReg(2) xor tfReg(3))) xor ((tfReg(4) xor tfReg(5)) xor (tfReg(6) xor tfReg(7))) );
--Clock Dividing Functions--
process (CLK, clkDiv) --set up clock divide for rClk
begin
if (Clk = '1' and Clk'event) then
if (clkDiv = baudDivide) then
clkDiv <= "000000000";
else
clkDiv <= clkDiv +1;
end if;
end if;
end process;
process (clkDiv, rClk, CLK) --Define rClk
begin
if CLK = '1' and CLK'Event then
if clkDiv = baudDivide then
rClk <= not rClk;
else
rClk <= rClk;
end if;
end if;
end process;
process (rClk) --set up clock divide for tClk
begin
if (rClk = '1' and rClk'event) then
rClkDiv <= rClkDiv +1;
end if;
end process;
tClk <= rClkDiv(3); --define tClk
process (rClk, ctRst) --set up a counter based on rClk
begin
if rClk = '1' and rClk'Event then
if ctRst = '1' then
ctr <= "0000";
else
ctr <= ctr +1;
end if;
end if;
end process;
process (tClk, tClkRST) --set up a counter based on tClk
begin
if (tClk = '1' and tClk'event) then
if tClkRST = '1' then
tfCtr <= "0000";
else
tfCtr <= tfCtr +1;
end if;
end if;
end process;
--This process controls the error flags--
process (rClk, RST, RD, CE)
begin
if RD = '1' or RST = '1' then
FE <= '0';
OE <= '0';
RDA <= '0';
PE <= '0';
elsif rClk = '1' and rClk'event then
if CE = '1' then
FE <= frameError;
OE <= RDA;
RDA <= '1';
PE <= parError;
rdReg(7 downto 0) <= rdSReg (7 downto 0);
end if;
end if;
end process;
--This process controls the receiving shift register--
process (rClk, rShift)
begin
if rClk = '1' and rClk'Event then
if rShift = '1' then
rdSReg <= (RXD & rdSReg(9 downto 1));
end if;
end if;
end process;
--This process controls the dataCtr to keep track of shifted values--
process (rClk, dataRST)
begin
if (rClk = '1' and rClk'event) then
if dataRST = '1' then
dataCtr <= "0000";
elsif dataIncr = '1' then
dataCtr <= dataCtr +1;
end if;
end if;
end process;
--Receiving State Machine--
process (rClk, RST)
begin
if rClk = '1' and rClk'Event then
if RST = '1' then
strCur <= strIdle;
else
strCur <= strNext;
end if;
end if;
end process;
--This process generates the sequence of steps needed receive the data
process (strCur, ctr, RXD, dataCtr, rdSReg, rdReg, RDA)
begin
case strCur is
when strIdle =>
dataIncr <= '0';
rShift <= '0';
dataRst <= '0';
CE <= '0';
if RXD = '0' then
ctRst <= '1';
strNext <= strEightDelay;
else
ctRst <= '0';
strNext <= strIdle;
end if;
when strEightDelay =>
dataIncr <= '0';
rShift <= '0';
CE <= '0';
if ctr(2 downto 0) = "111" then
ctRst <= '1';
dataRST <= '1';
strNext <= strGetData;
else
ctRst <= '0';
dataRST <= '0';
strNext <= strEightDelay;
end if;
when strGetData =>
CE <= '0';
dataRst <= '0';
if ctr(3 downto 0) = "1111" then
ctRst <= '1';
dataIncr <= '1';
rShift <= '1';
else
ctRst <= '0';
dataIncr <= '0';
rShift <= '0';
end if;
if dataCtr = "1010" then
strNext <= strCheckStop;
else
strNext <= strGetData;
end if;
when strCheckStop =>
dataIncr <= '0';
rShift <= '0';
dataRst <= '0';
ctRst <= '0';
CE <= '1';
strNext <= strIdle;
end case;
end process;
--TBE State Machine--
process (CLK, RST)
begin
if CLK = '1' and CLK'Event then
if RST = '1' then
stbeCur <= stbeIdle;
else
stbeCur <= stbeNext;
end if;
end if;
end process;
--This process gererates the sequence of events needed to control the TBE flag--
process (stbeCur, CLK, WR, DBIN, load)
begin
case stbeCur is
when stbeIdle =>
TBE <= '1';
if WR = '1' then
stbeNext <= stbeSetTBE;
else
stbeNext <= stbeIdle;
end if;
when stbeSetTBE =>
TBE <= '0';
if load = '1' then
stbeNext <= stbeWaitLoad;
else
stbeNext <= stbeSetTBE;
end if;
when stbeWaitLoad =>
if load = '0' then
stbeNext <= stbeWaitWrite;
else
stbeNext <= stbeWaitLoad;
end if;
when stbeWaitWrite =>
if WR = '0' then
stbeNext <= stbeIdle;
else
stbeNext <= stbeWaitWrite;
end if;
end case;
end process;
--This process loads and shifts out the transfer shift register--
process (load, shift, tClk, tfSReg)
begin
TXD <= tfsReg(0);
if tClk = '1' and tClk'Event then
if load = '1' then
tfSReg (10 downto 0) <= ('1' & par & tfReg(7 downto 0) &'0');
end if;
if shift = '1' then
tfSReg (10 downto 0) <= ('1' & tfSReg(10 downto 1));
end if;
end if;
end process;
-- Transfer State Machine--
process (tClk, RST)
begin
if (tClk = '1' and tClk'Event) then
if RST = '1' then
sttCur <= sttIdle;
else
sttCur <= sttNext;
end if;
end if;
end process;
-- This process generates the sequence of steps needed transfer the data--
process (sttCur, tfCtr, tfReg, TBE, tclk)
begin
case sttCur is
when sttIdle =>
tClkRST <= '0';
shift <= '0';
load <= '0';
if TBE = '1' then
sttNext <= sttIdle;
else
sttNext <= sttTransfer;
end if;
when sttTransfer =>
shift <= '0';
load <= '1';
tClkRST <= '1';
sttNext <= sttShift;
when sttShift =>
shift <= '1';
load <= '0';
tClkRST <= '0';
if tfCtr = "1100" then
sttNext <= sttIdle;
else
sttNext <= sttShift;
end if;
end case;
end process;
end Behavioral; | gpl-3.0 | c209a799770d9ac0ab6cc05c2e8b5015 | 0.534445 | 3.145709 | false | false | false | false |
estadofinito/biblioteca-vhdl | todos-los-archivos/siete_segmentos.vhd | 4 | 3,225 | ----------------------------------------------------------------------------------
-- Compañía: Estado Finito
-- Ingeniero: Carlos Ramos
--
-- Fecha de creación: 2012/07/29 12:56:33
-- Nombre del módulo: siete_segmentos - Behavioral
-- Descripción:
-- Decodificador de seis bits a siete segmentos. Se incluyen los números del 0
-- al 9, las letras de la A a la Z, y otros signos de puntuación utilizados.
-- Comentarios adicionales:
-- Se puede encontrar más información en la siguiente dirección:
-- http://www.estadofinito.com/siete-segmentos-y-vhdl/
-- Revisión:
-- Revisión 0.01 - Archivo creado.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity siete_segmentos is
PORT (
entrada: IN STD_LOGIC_VECTOR(5 downto 0);
salida : OUT STD_LOGIC_VECTOR(7 downto 0)
);
end siete_segmentos;
architecture Behavioral of siete_segmentos is
begin
visualizador: process (entrada) begin
case entrada is
when "000000" => salida <= x"C0"; -- 0
when "000001" => salida <= x"F9"; -- 1
when "000010" => salida <= x"A4"; -- 2
when "000011" => salida <= x"B0"; -- 3
when "000100" => salida <= x"99"; -- 4
when "000101" => salida <= x"92"; -- 5
when "000110" => salida <= x"82"; -- 6
when "000111" => salida <= x"F8"; -- 7
when "001000" => salida <= x"80"; -- 8
when "001001" => salida <= x"98"; -- 9
when "001010" => salida <= x"88"; -- A
when "001011" => salida <= x"83"; -- B
when "001100" => salida <= x"C6"; -- C
when "001101" => salida <= x"A1"; -- D
when "001110" => salida <= x"86"; -- E
when "001111" => salida <= x"8E"; -- F
when "010000" => salida <= x"90"; -- G
when "010001" => salida <= x"89"; -- H
when "010010" => salida <= x"E6"; -- I
when "010011" => salida <= x"E1"; -- J
when "010100" => salida <= x"85"; -- K
when "010101" => salida <= x"C7"; -- L
when "010110" => salida <= x"C8"; -- M
when "010111" => salida <= x"AB"; -- N
when "011000" => salida <= x"C0"; -- O
when "011001" => salida <= x"8C"; -- P
when "011010" => salida <= x"98"; -- Q
when "011011" => salida <= x"AF"; -- R
when "011100" => salida <= x"92"; -- S
when "011101" => salida <= x"87"; -- T
when "011110" => salida <= x"E3"; -- U
when "011111" => salida <= x"C1"; -- V
when "100000" => salida <= x"E2"; -- W
when "100001" => salida <= x"8F"; -- X
when "100010" => salida <= x"91"; -- Y
when "100011" => salida <= x"B6"; -- Z
when "100100" => salida <= x"BF"; -- -
when "100101" => salida <= x"F7"; -- _
when "100110" => salida <= x"7F"; -- .
when others => salida <= x"FF"; -- Nada
end case;
end process;
end Behavioral; | lgpl-2.1 | 7a03fb019439c8b573b5811ae08ae6a2 | 0.454404 | 3.458558 | false | false | false | false |
dummylink/plnk_fpga-stack | Examples/xilinx_microblaze/avnet_lx9/pcores/plb_powerlink_v1_00_a/hdl/vhdl/pdi_spi.vhd | 5 | 11,210 | ------------------------------------------------------------------------------------------------------------------------
-- Parallel port (8/16bit) for PDI
--
-- Copyright (C) 2010 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2010-08-31 V0.01 zelenkaj First version
-- 2010-11-23 V0.02 zelenkaj Added write/read sequence feature (WRSQ and RDSQ)
-- 2010-11-29 V0.03 zelenkaj Added endian generic
-- 2011-01-10 V0.04 zelenkaj Added wake up feature
-- 2011-02-28 V0.05 zelenkaj Added inversion of wake up command
------------------------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity pdi_spi is
generic (
spiSize_g : integer := 8;
cpol_g : boolean := false;
cpha_g : boolean := false;
spiBigEnd_g : boolean := false
);
port (
-- SPI
spi_clk : in std_logic;
spi_sel : in std_logic;
spi_miso : out std_logic;
spi_mosi : in std_logic;
-- clock for AP side
ap_reset : in std_logic;
ap_clk : in std_logic;
-- Avalon Slave Interface for AP
ap_chipselect : out std_logic;
ap_read : out std_logic;
ap_write : out std_logic;
ap_byteenable : out std_logic_vector(3 DOWNTO 0);
ap_address : out std_logic_vector(12 DOWNTO 0);
ap_writedata : out std_logic_vector(31 DOWNTO 0);
ap_readdata : in std_logic_vector(31 DOWNTO 0)
);
end entity pdi_spi;
architecture rtl of pdi_spi is
--wake up command
constant cmdWakeUp : std_logic_vector(7 downto 0) := x"03"; --0b00000011
constant cmdWakeUp1 : std_logic_vector(7 downto 0) := x"0A"; --0b00001010
constant cmdWakeUp2 : std_logic_vector(7 downto 0) := x"0C"; --0b00001100
constant cmdWakeUp3 : std_logic_vector(7 downto 0) := x"0F"; --0b00001111
--spi frame constants
constant cmdHighaddr_c : std_logic_vector(2 downto 0) := "100";
constant cmdMidaddr_c : std_logic_vector(2 downto 0) := "101";
constant cmdWr_c : std_logic_vector(2 downto 0) := "110";
constant cmdRd_c : std_logic_vector(2 downto 0) := "111";
constant cmdWRSQ_c : std_logic_vector(2 downto 0) := "001";
constant cmdRDSQ_c : std_logic_vector(2 downto 0) := "010";
constant cmdLowaddr_c : std_logic_vector(2 downto 0) := "011";
constant cmdIdle_c : std_logic_vector(2 downto 0) := "000";
--pdi_spi control signals
type fsm_t is (reset, reset1, reset2, reset3, idle, decode, waitwr, waitrd, wr, rd);
signal fsm : fsm_t;
signal addrReg : std_logic_vector(ap_address'left+2 downto 0);
signal cmd : std_logic_vector(2 downto 0);
signal highPriorLoad : std_logic;
signal highPriorLoadVal : std_logic_vector(spiSize_g-1 downto 0);
--spi core signals
signal clk : std_logic;
signal rst : std_logic;
signal din : std_logic_vector(spiSize_g-1 downto 0);
signal load : std_logic;
signal dout : std_logic_vector(spiSize_g-1 downto 0);
signal valid : std_logic;
--
signal ap_byteenable_s : std_logic_vector(ap_byteenable'range);
begin
clk <= ap_clk;
rst <= ap_reset;
ap_chipselect <= '1' when fsm = wr or fsm = rd or fsm = waitrd else '0';
ap_write <= '1' when fsm = wr else '0';
ap_read <= '1' when fsm = waitrd or fsm = rd else '0';
ap_address <= addrReg(addrReg'left downto 2);
ap_byteenable <= ap_byteenable_s;
ap_byteenable_s <= --little endian
"0001" when addrReg(1 downto 0) = "00" and spiBigEnd_g = false else
"0010" when addrReg(1 downto 0) = "01" and spiBigEnd_g = false else
"0100" when addrReg(1 downto 0) = "10" and spiBigEnd_g = false else
"1000" when addrReg(1 downto 0) = "11" and spiBigEnd_g = false else
--big endian
"0001" when addrReg(1 downto 0) = "11" and spiBigEnd_g = true else
"0010" when addrReg(1 downto 0) = "10" and spiBigEnd_g = true else
"0100" when addrReg(1 downto 0) = "01" and spiBigEnd_g = true else
"1000" when addrReg(1 downto 0) = "00" and spiBigEnd_g = true else
"0000";
ap_writedata <= (dout & dout & dout & dout);
din <= highPriorLoadVal when highPriorLoad = '1' else --load value that was just received
ap_readdata( 7 downto 0) when ap_byteenable_s = "0001" else
ap_readdata(15 downto 8) when ap_byteenable_s = "0010" else
ap_readdata(23 downto 16) when ap_byteenable_s = "0100" else
ap_readdata(31 downto 24) when ap_byteenable_s = "1000" else
(others => '0');
load <= '1' when highPriorLoad = '1' else --load value that was just received
'1' when fsm = rd else --load data from pdi to spi shift register
'0';
cmd <= dout(dout'left downto dout'left-2); --get cmd pattern
highPriorLoadVal <= not dout; --create inverse of received pattern
thePdiSpiFsm : process(clk, rst)
variable timeout : integer range 0 to 3;
variable writes : integer range 0 to 32;
variable reads : integer range 0 to 32;
begin
if rst = '1' then
fsm <= reset;
timeout := 0;
writes := 0; reads := 0;
addrReg <= (others => '0');
highPriorLoad <= '0';
elsif clk = '1' and clk'event then
--default assignment
highPriorLoad <= '0';
case fsm is
when reset =>
fsm <= reset;
if valid = '1' then
--load inverse pattern of received pattern
highPriorLoad <= '1';
if dout = cmdWakeUp then
--wake up command (1/4) received
fsm <= reset1;
else
--wake up command not decoded correctly
fsm <= reset;
end if;
end if;
when reset1 =>
fsm <= reset1;
if valid = '1' then
--load inverse pattern of received pattern
highPriorLoad <= '1';
if dout = cmdWakeUp1 then
--wake up command (2/4) sequence was correctly decoded!
fsm <= reset2;
else
--wake up command not decoded correctly
fsm <= reset;
end if;
end if;
when reset2 =>
fsm <= reset2;
if valid = '1' then
--load inverse pattern of received pattern
highPriorLoad <= '1';
if dout = cmdWakeUp2 then
--wake up command (3/4) sequence was correctly decoded!
fsm <= reset3;
else
--wake up command not decoded correctly
fsm <= reset;
end if;
end if;
when reset3 =>
fsm <= reset3;
if valid = '1' then
--load inverse pattern of received pattern
highPriorLoad <= '1';
if dout = cmdWakeUp3 then
--wake up command (4/4) sequence was correctly decoded!
fsm <= idle;
else
--wake up command not decoded correctly
fsm <= reset;
end if;
end if;
when idle =>
if writes /= 0 then
fsm <= waitwr;
elsif reads /= 0 and valid = '1' then
fsm <= waitrd;
elsif valid = '1' then
fsm <= decode;
else
fsm <= idle;
end if;
when decode =>
fsm <= idle; --default
case cmd is
when cmdHighaddr_c =>
addrReg(addrReg'left downto addrReg'left-4) <= dout(spiSize_g-4 downto 0);
when cmdMidaddr_c =>
addrReg(addrReg'left-5 downto addrReg'left-9) <= dout(spiSize_g-4 downto 0);
when cmdLowaddr_c =>
addrReg(addrReg'left-10 downto 0) <= dout(spiSize_g-4 downto 0);
when cmdWr_c =>
addrReg(addrReg'left-10 downto 0) <= dout(spiSize_g-4 downto 0);
fsm <= waitwr;
writes := 1;
when cmdRd_c =>
addrReg(addrReg'left-10 downto 0) <= dout(spiSize_g-4 downto 0);
fsm <= waitrd;
reads := 1;
when cmdWRSQ_c =>
fsm <= waitwr;
writes := conv_integer(dout(spiSize_g-4 downto 0)) + 1; --BYTES byte are written
when cmdRDSQ_c =>
fsm <= waitrd;
reads := conv_integer(dout(spiSize_g-4 downto 0)) + 1; --BYTES byte are read
when cmdIdle_c =>
--don't interpret the command, inverse pattern and goto idle
when others =>
--error, goto idle
end case;
when waitwr =>
--wait for data from spi master
if valid = '1' then
fsm <= wr;
else
fsm <= waitwr;
end if;
when waitrd =>
--spi master wants to read
--wait for dpr to read
if timeout = 3 then
fsm <= rd;
timeout := 0;
else
timeout := timeout + 1;
fsm <= waitrd;
end if;
when wr =>
fsm <= idle;
writes := writes - 1;
addrReg <= addrReg + 1;
when rd =>
fsm <= idle;
reads := reads - 1;
addrReg <= addrReg + 1;
end case;
end if;
end process;
theSpiCore : entity work.spi
generic map (
frameSize_g => spiSize_g,
cpol_g => cpol_g,
cpha_g => cpha_g
)
port map (
-- Control Interface
clk => clk,
rst => rst,
din => din,
load => load,
dout => dout,
valid => valid,
-- SPI
sck => spi_clk,
ss => spi_sel,
miso => spi_miso,
mosi => spi_mosi
);
end architecture rtl;
| gpl-2.0 | dcc04a19d6f897bd0f6453548f8110be | 0.570562 | 3.368389 | false | false | false | false |
DougFirErickson/parallella-hw | fpga/ip/xilinx/fifo_async_103x32/fifo_generator_v12_0/hdl/builtin/builtin_extdepth_v6.vhd | 6 | 50,137 | `protect begin_protected
`protect version = 1
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| gpl-3.0 | 17c04f97ddf00ffaa98b8f8936ae6783 | 0.949857 | 1.822766 | false | false | false | false |
dskntIndustry/Hardware | hdl_library/ClockGenerator/ClockGenerator.vhd | 1 | 1,866 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--library hdl_library_CommonFunctions;
--use hdl_library_CommonFunctions.CommonFunctions.all;
library hdl_library_CommonFunctions;
use hdl_library_CommonFunctions.MathHelpers.all;
entity ClockGenerator is
generic
(
G_CLOCK_FREQUENCY : integer;
G_CLOCK_DIVIDER : integer
);
port
(
clock : in std_logic;
enable : in std_logic;
clock_output : out std_logic;
clock_output_n : out std_logic
);
end entity; --ClockGenerator
architecture arch of ClockGenerator is
signal i_counter : std_logic_vector(log2(G_CLOCK_DIVIDER) downto 0) := (others => '0');
signal i_clock_output : std_logic := '0';
signal i_index : integer := 0;
begin
PowerOF2: if (isPow2(G_CLOCK_DIVIDER) = true) and (G_CLOCK_FREQUENCY/G_CLOCK_DIVIDER > 1) generate
--i_index <= log2(G_CLOCK_FREQUENCY/G_CLOCK_DIVIDER);
pow2_divider:process(clock)
begin
if rising_edge(clock) then
if enable = '1' then
i_counter <= i_counter + 1;
else
i_clock_output <= '0';
end if;
i_clock_output <= i_counter(log2(G_CLOCK_DIVIDER));
end if;
end process pow2_divider;
end generate PowerOF2;
clock_output <= i_clock_output;
clock_output_n <= not i_clock_output;
NotPowerOF2: if (isPow2(G_CLOCK_DIVIDER) = false) and (G_CLOCK_FREQUENCY/G_CLOCK_DIVIDER > 1) generate
clock_counter:process(clock)
begin
if rising_edge(clock) then
if enable = '1' then
i_counter <= i_counter + 1;
if i_counter = (G_CLOCK_DIVIDER) - 1 then
i_clock_output <= not i_clock_output;
i_counter <= (others => '0');
end if;
else
i_clock_output <= '0';
end if;
end if;
end process clock_counter; -- clock_counter
end generate NotPowerOF2;
end architecture; -- arch | gpl-3.0 | 402f3ea1baf3c81028c94b0e6e057ada | 0.6597 | 2.875193 | false | false | false | false |
DougFirErickson/parallella-hw | fpga/ip/xilinx/fifo_async_103x32/fifo_generator_v12_0/hdl/ramfifo/axi_reg_slice.vhd | 6 | 17,522 | `protect begin_protected
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 11232)
`protect data_block
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`protect end_protected
| gpl-3.0 | ba26135c77f4653b09117a1a2a8e5ae3 | 0.93745 | 1.851828 | false | false | false | false |
JuanMarcosRamirez/WeightedMedianDisenoLogico | misc/FPGA/otros/auditoría_imagen_16x16/ro_filt_3x3.vhd | 1 | 6,254 | -------------------------------------------------------------- ------------
-- filename: ro_filt_3x3.vhd
-- author: Tony Nelson
-- date: 12/21/99
--
-- detail: 3x3 Rank Order Filter. Generic order sets filter order.
-- order: integer:= 5 is a Median Filter.
--
-- auditoria
----------------------------------- ----------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity ro_filt_3x3 is
generic (
vwidth: integer:=8;
order: integer:=5;
num_cols: integer:=16;
num_rows: integer:=16
);
port (
Clk : in std_logic;
RSTn : in std_logic;
D : in std_logic_vector(vwidth-1 downto 0);
Dout : out std_logic_vector(vwidth -1 downto 0);
DV : out std_logic;
FColPos : out integer;
FRowPos : out integer
);
end ro_filt_3x3;
architecture ro_filt_3x3 of ro_filt_3x3 is
component sort_3x3
generic (
vwidth: integer:=8
);
port (
Clk : in std_logic;
RSTn : in std_logic;
w11 : in std_logic_vector((vwidth -1) downto 0);
w12 : in std_logic_vector((vwidth -1) downto 0);
w13 : in std_logic_vector((vwidth -1) downto 0);
w21 : in std_logic_vector((vwidth-1) downto 0);
w22 : in std_logic_vector((vwidth -1) downto 0);
w23 : in std_logic_vector((vwidth -1) downto 0);
w31 : in std_logic_vector((vwidth -1) downto 0);
w32 : in std_logic_vector((vwidth -1) downto 0);
w33 : in std_logic_vector((vwidth-1) downto 0);
DVw : in std_logic;
DVs : out std_logic;
s1 : out std_logic_vector(vwidth -1 downto 0);
s2 : out std_logic_vector(vwidth -1 downto 0);
s3 : out std_logic_vector(vwidth -1 downto 0);
s4 : out std_logic_vector(vwidth-1 downto 0);
s5 : out std_logic_vector(vwidth -1 downto 0);
s6 : out std_logic_vector(vwidth -1 downto 0);
s7 : out std_logic_vector(vwidth -1 downto 0);
s8 : out std_logic_vector(vwidth -1 downto 0);
s9 : out std_logic_vector(vwidth -1 downto 0)
);
end component sort_3x3;
signal w11: std_logic_vector((vwidth -1) downto 0);
signal w12: std_logic_vector((vwidth -1) downto 0);
signal w13: std_logic_vector((vwidth -1) downto 0);
signal w21: std_logic_vector((vwidth -1) downto 0);
signal w22: std_logic_vector((vwidth-1) downto 0);
signal w23: std_logic_vector((vwidth -1) downto 0);
signal w31: std_logic_vector((vwidth -1) downto 0);
signal w32: std_logic_vector((vwidth -1) downto 0);
signal w33: std_logic_vector((vwidth -1) downto 0);
signal DVw: std_logic;
signal DVs: std_logic;
signal s1: std_logic_vector(vwidth -1 downto 0);
signal s2: std_logic_vector(vwidth -1 downto 0);
signal s3: std_logic_vector(vwidth -1 downto 0);
signal s4: std_logic_vector(vwidth -1 downto 0);
signal s5: std_logic_vector(vwidth-1 downto 0);
signal s6: std_logic_vector(vwidth -1 downto 0);
signal s7: std_logic_vector(vwidth -1 downto 0);
signal s8: std_logic_vector(vwidth -1 downto 0);
signal s9: std_logic_vector(vwidth -1 downto 0);
component window_3x3
generic (
vwidth: integer:=8
);
port (
Clk : in std_logic;
RSTn : in std_logic;
D : in std_logic_vector(vwidth-1 downto 0);
w11 : out std_logic_vector(vwidth -1 downto 0);
w12 : out std_logic_vector(vwidth -1 downto 0);
w13 : out std_logic_vector(vwidth-1 downto 0);
w21 : out std_logic_vector(vwidth -1 downto 0);
w22 : out std_logic_vector(vwidth -1 downto 0);
w23 : out std_logic_vector(vwidth -1 downto 0);
w31 : out std_logic_vector(vwidth -1 downto 0);
w32 : out std_logic_vector(vwidth-1 downto 0);
w33 : out std_logic_vector(vwidth -1 downto 0);
DV : out std_logic:='0'
);
end component window_3x3;
component rc_counter
generic (
num_cols: integer:=16;
num_rows: integer:=16
);
port (
Clk : in std_logic;
RSTn : in std_logic;
En : in std_logic;
ColPos : out integer;
RowPos : out integer
);
end component rc_counter;
signal ColPos: integer:=0;
signal RowPos: integer:=0;
signal ColPos_c: integer:=0; -- corrected positions
signal RowPos_c: integer:=0;
signal rt1: integer:=0;
signal rt2: integer:=0;
signal rt3: integer:=0;
signal rt4: integer:=0;
signal rt5: integer:=0;
signal rt6: integer:=0;
signal rt7: integer:=0;
signal rt8: integer:=0;
signal rt9: integer:=0;
signal rt10: integer:=0;
signal rt11: integer:=0;
signal rt12: integer:=0;
signal rt13: integer:=0;
signal rt14: integer:=0;
signal rt15: integer:=0;
signal rt16: integer:=0;
signal flag: std_logic:='0';
begin
sort_3x3x: sort_3x3
generic map (
vwidth => 8
)
port map (
Clk => Clk,
RSTn => RSTn,
w11 => w11,
w12 => w12,
w13 => w13,
w21 => w21,
w22 => w22,
w23 => w23,
w31 => w31,
w32 => w32,
w33 => w33,
DVw => DVw,
DVs => DVs,
s1 => s1,
s2 => s2,
s3 => s3,
s4 => s4,
s5 => s5,
s6 => s6,
s7 => s7,
s8 => s8,
s9 => s9
);
window_3x3x: window_3x3
generic map (
vwidth => 8
)
port map (
Clk => Clk,
RSTn => RSTn,
D => D,
w11 => w11,
w12 => w12,
w13 => w13,
w21 => w21,
w22 => w22,
w23 => w23,
w31 => w31,
w32 => w32,
w33 => w33,
DV => DVw
);
rc_counterx: rc_counter
generic map (
num_cols => 16,
num_rows => 16
)
port map (
Clk => Clk,
RSTn => RSTn,
En => RSTn,
ColPos => ColPos,
RowPos => RowPos
);
FColPos <= ColPos;
FRowPos <= RowPos;
ro_filt_proc: process(RSTn,Clk)
begin
if RSTn = '0' then
ColPos_c <= 0;
rt1 <= 0;
rt2 <= 0;
rt3 <= 0;
rt4 <= 0;
rt5 <= 0;
rt6 <= 0;
rt7 <= 0;
rt8 <= 0;
rt9 <= 0;
rt10 <= 0;
rt11 <= 0;
rt12 <= 0;
rt13 <= 0;
rt14 <= 0;
rt15 <= 0;
rt16 <= 0;
RowPos_c <= 0;
Dout <= (others=>'0');
DV <= '0';
flag <= '0';
elsif rising_edge(Clk) then
-- counter correction
ColPos_c <= ((ColPos-17) mod 16);-- ojo aquí antes era 512 --ojo con el 17);
rt1 <= ((RowPos-1) mod 16);-- ojo aquí antes era 512);
rt2 <= rt1;
rt3 <= rt2;
rt4 <= rt3;
rt5 <= rt4;
rt6 <= rt5;
rt7 <= rt6;
rt8 <= rt7;
rt9 <= rt8;
rt10 <= rt9;
rt11 <= rt10;
rt12 <= rt11;
rt13 <= rt12;
rt14 <= rt13;
rt15 <= rt14;
rt16 <= rt15;
RowPos_c <= rt16;
-- screen edge detection
if (ColPos_c = num_cols-1) or (RowPos_c = num_rows-1) or (ColPos_c
= num_cols-2) or (RowPos_c = 0) then
Dout <= (others=>'0');
else
if order = 1 then
Dout <= s1;
elsif order = 2 then
Dout <= s2;
elsif order = 3 then
Dout <= s3;
elsif order = 4 then
Dout <= s4;
elsif order = 5 then
Dout <= s5;
elsif order = 6 then
Dout <= s6;
elsif order = 7 then
Dout <= s7;
elsif order = 8 then
Dout <= s8;
elsif order = 9 then
Dout <= s9;
end if;
end if;
if ColPos >= 1 and RowPos >= 2 then -- antes eran 17 y 1(por que 1???)
DV <= '1';
flag <= '1';
elsif flag = '1' then
DV <= '1';
else
DV <= '0';
end if;
end if;
end process;
end ro_filt_3x3;
| gpl-3.0 | 156a9f2c22a6ef417facddb8af9875ed | 0.642149 | 2.519742 | false | false | false | false |
takeshineshiro/fpga_linear_128 | lf_ast.vhd | 3 | 6,763 | -- ================================================================================
-- Legal Notice: Copyright (C) 1991-2006 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera. Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors. No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
-- ================================================================================
--
-- Generated by: FIR Compiler 9.0
-- Generated on: 2014-8-27 12:51:35
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library auk_dspip_lib;
use auk_dspip_lib.auk_dspip_lib_pkg_fir_90.all;
entity lf_ast is
port(
clk : in std_logic;
reset_n : in std_logic;
ast_sink_ready : out std_logic;
ast_source_data : out std_logic_vector (31 -1 downto 0);
ast_sink_data : in std_logic_vector (15 -1 downto 0);
ast_sink_valid : in std_logic;
ast_source_valid : out std_logic;
ast_source_ready : in std_logic;
ast_sink_error : in std_logic_vector (1 downto 0);
ast_source_error : out std_logic_vector (1 downto 0)
);
attribute altera_attribute : string;
attribute altera_attribute of lf_ast:entity is "-name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 10036";
end lf_ast;
-- Warnings Suppression On
-- altera message_off 10036
architecture struct of lf_ast is
signal sink_packet_error : std_logic_vector(1 downto 0);
signal data_in : std_logic_vector(15 -1 downto 0);
signal data_out : std_logic_vector(31 -1 downto 0);
signal core_out : std_logic_vector(31 -1 downto 0);
signal ready : std_logic;
signal reset_fir : std_logic;
signal sink_ready_ctrl : std_logic;
signal sink_stall : std_logic;
signal source_packet_error : std_logic_vector(1 downto 0);
signal source_stall : std_logic;
signal source_valid_ctrl : std_logic;
signal stall : std_logic;
signal valid : std_logic;
signal core_valid : std_logic;
signal enable_in : std_logic;
signal stall_delayed : std_logic;
constant ENABLE_PIPELINE_DEPTH_c : natural := 0;
component lf_st is
port (
rst : in std_logic;
clk : in std_logic;
clk_en : in std_logic;
rdy_to_ld : out std_logic;
done : out std_logic;
data_in : in std_logic_vector(15 - 1 downto 0);
fir_result : out std_logic_vector(31 - 1 downto 0));
end component lf_st;
begin
sink : auk_dspip_avalon_streaming_sink_fir_90
generic map (
WIDTH_g => 15,
PACKET_SIZE_g => 1,
FIFO_DEPTH_g => 7,
FAMILY_g => "Cyclone III",
MEM_TYPE_g => "Auto")
port map (
clk => clk,
reset_n => reset_n,
data => data_in,
sink_ready_ctrl => sink_ready_ctrl,
sink_stall => sink_stall,
packet_error => sink_packet_error,
at_sink_ready => ast_sink_ready,
at_sink_valid => ast_sink_valid,
at_sink_data => ast_sink_data,
at_sink_error => ast_sink_error);
source : auk_dspip_avalon_streaming_source_fir_90
generic map (
WIDTH_g => 31,
packet_size_g => 1)
port map (
clk => clk,
reset_n => reset_n,
data => data_out,
source_valid_ctrl => source_valid_ctrl,
design_stall => stall_delayed,
source_stall => source_stall,
packet_error => source_packet_error,
at_source_ready => ast_source_ready,
at_source_valid => ast_source_valid,
at_source_data => ast_source_data,
at_source_error => ast_source_error);
intf_ctrl : auk_dspip_avalon_streaming_controller_fir_90
port map (
clk => clk,
ready => ready,
reset_n => reset_n,
sink_packet_error => sink_packet_error,
sink_stall => sink_stall,
source_stall => source_stall,
valid => valid,
reset_design => reset_fir,
sink_ready_ctrl => sink_ready_ctrl,
source_packet_error => source_packet_error,
source_valid_ctrl => source_valid_ctrl,
stall => stall);
fircore: lf_st
port map (
rst => reset_fir,
clk => clk,
clk_en => enable_in,
rdy_to_ld => ready,
done => core_valid,
data_in => data_in,
fir_result => core_out);
data_out <= core_out;
valid <= core_valid;
enable_in <= not stall;
no_enable_pipeline: if ENABLE_PIPELINE_DEPTH_c = 0 generate
stall_delayed <= stall;
end generate no_enable_pipeline;
enable_pipeline: if ENABLE_PIPELINE_DEPTH_c > 0 generate
delay_core_enable : process (clk, reset_n)
variable stall_delay : std_logic_vector(ENABLE_PIPELINE_DEPTH_c downto 0);
begin -- process delay_core_enable
if reset_n = '0' then
stall_delay := (others => '0');
elsif rising_edge(clk) then
stall_delay := stall_delay(stall_delay'high-1 downto 0) & stall;
end if;
stall_delayed <= stall_delay(stall_delay'high);
end process delay_core_enable;
end generate enable_pipeline;
end struct;
| mit | 3bf650dafaefb110445e9099bd48a535 | 0.6021 | 3.795174 | false | false | false | false |
dskntIndustry/Hardware | hdl_library/ClockGenerator/ClockGeneratorTB.vhd | 1 | 1,165 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library hdl_library_CommonFunctions;
use hdl_library_CommonFunctions.CommonFunctions.all;
entity ClockGeneratorTB is
end entity; --ClockGenerator
architecture tb of ClockGeneratorTB is
constant G_CLOCK_FREQUENCY : integer := 512;
constant G_BASE_FREQUENCY : integer := 12E6;
constant G_CLOCK_DIVIDER : integer := 10;
signal clock : std_logic := '0';
signal clock_n : std_logic := '0';
signal enable : std_logic := '0';
signal clock_output : std_logic := '0';
signal clock_output_n : std_logic := '0';
begin
clock <= not clock after (1 sec / G_CLOCK_FREQUENCY) / 2;
clock_n <= not clock;
--Test:process
--begin
enable <= '1';
--end process; --Test
dut : entity work.ClockGenerator
generic map
(
G_CLOCK_FREQUENCY => G_CLOCK_FREQUENCY,
G_CLOCK_DIVIDER => G_CLOCK_DIVIDER
)
port map
(
clock => clock,
enable => enable,
-- module clock output
clock_output => clock_output,
clock_output_n => clock_output_n
);
end architecture; -- tb | gpl-3.0 | 0202cf9a74c3c6e262c3d6806d985bb8 | 0.64206 | 3.025974 | false | false | false | false |
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4mfE3/c=
`protect end_protected
| gpl-3.0 | f5ea18fa2419e32ae00f51a36c71769a | 0.951871 | 1.810414 | false | false | false | false |
Monash-2015-Ultrasonic/Logs | Final System Code/SYSTEMV3/Source/IP/FIR/FIR_sim/auk_dspip_avalon_streaming_source_hpfir.vhd | 2 | 19,165 | -- (C) 2001-2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-------------------------------------------------------------------------
-------------------------------------------------------------------------
--
-- Revision Control Information
--
-- $Revision: #1 $
-- $Date: 2009/07/29 $
-- Author : Boon Hong Oh
--
-- Project : Avalon_streaming II Source Interface with ready_latency=0
--
-- Description :
--
-- This interface is capable of handling single or multi channel streams as
-- well as blocks of data. The at_source_sop and at_source_eop are generated as
-- described in the Avalon_streaming II specification. The at_source_error output is a 2-
-- bit signal that complies with the PFC error format (by Kent Orthner).
--
-- 00: no error
-- 01: missing sop
-- 10: missing eop
-- 11: unexpected eop
-- other types of errors also marked as 11. Any error signal is accompanied
-- by at_sink_eop flagged high.
--
-- When packet_size is greater than one, this interface expects the main design
-- to supply the count of data starting from 1 to the packet_size. When it
-- receives the valid flag together with the data_count=1, it starts pumping
-- out data by flagging the at_source_sop and at_source_valid both high.
--
-- When the data_count=packet_size, the at_source_eop is flagged high together
-- with at_source_valid. THERE IS NO ERROR CHECKING FOR THE data_count signal.
--
-- If the receiver is not ready to accept any data, the interface flags the source_
-- stall signal high to tell the design to stall. It is the designers
-- responsibility to use this signal properly. In some design, the stall signal
-- needs to stall all of the design so that no new data can be accepted (as in
-- FIR), in other cases (i.e. a FIFO built on a dual port RAM),the input can
-- still accept new data although it cannot send any output.
--
-- ALTERA Confidential and Proprietary
-- Copyright 2006 (c) Altera Corporation
-- All rights reserved
--
-------------------------------------------------------------------------
-------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
use work.auk_dspip_math_pkg_hpfir.all;
entity auk_dspip_avalon_streaming_source_hpfir is
generic(
WIDTH_g : integer := 8; -- DATA_PORT_COUNT * DATA_WIDTH
DATA_WIDTH : integer := 8;
DATA_PORT_COUNT : integer := 1;
PACKET_SIZE_g : natural := 2;
FIFO_DEPTH_g : natural := 0;
HAVE_COUNTER_g : boolean := false;
COUNTER_LIMIT_g : natural := 4;
--MULTI_CHANNEL_g : boolean := true;
USE_PACKETS : integer := 1;
--FAMILY_g : string := "Stratix II";
--MEM_TYPE_g : string := "Auto";
ENABLE_BACKPRESSURE_g : boolean := true
);
port(
clk : in std_logic;
reset_n : in std_logic;
----------------- DESIGN SIDE SIGNALS
data_in : in std_logic_vector (WIDTH_g-1 downto 0);
data_count : in std_logic_vector (log2_ceil_one(PACKET_SIZE_g)-1 downto 0) := (others => '0');
source_valid_ctrl : in std_logic;
source_stall : out std_logic;
packet_error : in std_logic_vector (1 downto 0);
----------------- AVALON_STREAMING SIDE SIGNALS
at_source_ready : in std_logic;
at_source_valid : out std_logic;
at_source_data : out std_logic_vector (WIDTH_g-1 downto 0);
at_source_channel : out std_logic_vector (log2_ceil_one(PACKET_SIZE_g)-1 downto 0);
at_source_error : out std_logic_vector (1 downto 0);
at_source_sop : out std_logic;
at_source_eop : out std_logic
);
-- Declarations
end auk_dspip_avalon_streaming_source_hpfir;
-- hds interface_end
architecture rtl of auk_dspip_avalon_streaming_source_hpfir is
--constant FIFO_HINT_c : string := "RAM_BLOCK_TYPE="& MEM_TYPE_g;
constant FIFO_DEPTH_c : natural := FIFO_DEPTH_g;
constant LOG2PACKET_SIZE_c : natural := log2_ceil_one(PACKET_SIZE_g);
constant MIN_DATA_COUNT_g : natural := 2;
type STATE_TYPE_t is (start, sop, run1, st_err, end1); --wait1, stall,
signal source_state : STATE_TYPE_t;
signal source_next_state : STATE_TYPE_t;
signal packet_error0 : std_logic;
signal at_source_error_int : std_logic_vector(1 downto 0);
signal at_source_sop_int : std_logic := '0';
signal at_source_eop_int : std_logic := '0';
signal count_finished : boolean := false;
signal count_started : boolean := false;
signal at_source_valid_s : std_logic;
signal data_valid : std_logic;
signal data_out : std_logic_vector(WIDTH_g-1 downto 0);
signal fifo_count : std_logic_vector(DATA_PORT_COUNT*log2_ceil(FIFO_DEPTH_g)-1 downto 0);
signal fifo_empty : std_logic_vector(DATA_PORT_COUNT-1 downto 0); -- multichan, multiinout
signal fifo_alm_empty : std_logic_vector(DATA_PORT_COUNT-1 downto 0);
signal fifo_alm_full : std_logic_vector(DATA_PORT_COUNT-1 downto 0);
signal fifo_full : std_logic_vector(DATA_PORT_COUNT-1 downto 0);
signal clear_fifo : std_logic;
signal fifo_rdreq : std_logic;
signal fifo_rdreq_d : std_logic;
signal fifo_wrreq : std_logic;
signal fifo_empty_d : std_logic;
signal reset_design_int : std_logic;
signal channel_out : std_logic_vector(log2_ceil_one(PACKET_SIZE_g)-1 downto 0) := (others => '0');
signal fifo_sop_in : std_logic := '0';
signal fifo_eop_in : std_logic := '0';
signal fifo_error_in : std_logic_vector(1 downto 0);
signal at_source_sop_s : std_logic := '0';
signal at_source_eop_s : std_logic := '0';
signal at_source_error_s : std_logic_vector(1 downto 0);
signal in_ready : std_logic;
component altera_avalon_sc_fifo is
generic(
SYMBOLS_PER_BEAT : integer := 1;
BITS_PER_SYMBOL : integer := 8;
FIFO_DEPTH : integer := 16;
CHANNEL_WIDTH : integer := 2;
ERROR_WIDTH : integer := 2;
--EMPTY_LATENCY : integer := 0;
USE_PACKETS : integer := 0
);
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal in_channel : IN STD_LOGIC_VECTOR (log2_ceil_one(PACKET_SIZE_g)-1 DOWNTO 0);
signal in_data : IN STD_LOGIC_VECTOR (DATA_WIDTH*DATA_PORT_COUNT-1 DOWNTO 0);
signal in_error : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal in_endofpacket : IN STD_LOGIC;
signal in_startofpacket : IN STD_LOGIC;
signal in_valid : IN STD_LOGIC;
signal out_ready : IN STD_LOGIC;
signal reset : IN STD_LOGIC;
signal in_empty : IN STD_LOGIC_VECTOR (log2_ceil_one(DATA_PORT_COUNT)-1 DOWNTO 0);
signal csr_address : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal csr_write : IN STD_LOGIC;
signal csr_read : IN STD_LOGIC;
signal csr_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
-- outputs:
signal in_ready : OUT STD_LOGIC;
signal out_channel : OUT STD_LOGIC_VECTOR (log2_ceil_one(PACKET_SIZE_g)-1 DOWNTO 0);
signal out_data : OUT STD_LOGIC_VECTOR (DATA_WIDTH*DATA_PORT_COUNT-1 DOWNTO 0);
signal out_error : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal out_endofpacket : OUT STD_LOGIC;
signal out_startofpacket : OUT STD_LOGIC;
signal out_valid : OUT STD_LOGIC;
signal out_empty : OUT STD_LOGIC_VECTOR (log2_ceil_one(DATA_PORT_COUNT)-1 DOWNTO 0)
);
end component altera_avalon_sc_fifo;
begin
single_channel : if USE_PACKETS = 0 generate
at_source_sop_int <= '0';
at_source_eop_int <= '0';
packet_error0 <= packet_error(0);
at_source_error_int(1) <= '0';
at_source_error_int(0) <= packet_error0;
end generate single_channel;
packet_multi : if USE_PACKETS = 1 generate
packet_error0 <= packet_error(1) or packet_error(0);
counter_no : if HAVE_COUNTER_g = false generate
signal data_counter : unsigned(LOG2PACKET_SIZE_c-1 downto 0);
begin
count_finished <= true when data_counter = to_unsigned(PACKET_SIZE_g-1, LOG2PACKET_SIZE_c) else
false;
data_counter <= unsigned(data_count);
count_started <= true when data_counter = 0 else
false;
end generate counter_no;
counter_yes : if HAVE_COUNTER_g = true generate
signal data_counter : unsigned(log2_ceil(COUNTER_LIMIT_g)-1 downto 0);
begin
count_finished <= true when data_counter = to_unsigned(COUNTER_LIMIT_g-1, log2_ceil(COUNTER_LIMIT_g)) else
false;
count_started <= true when data_counter = 0 else
false;
packet_counter : process (clk, reset_n)
begin -- process packet_counter
if reset_n = '0' then
data_counter <= (others => '0');
elsif rising_edge(clk) then
if source_state = start and source_next_state = sop then
data_counter <= --(others => '0'); --
data_counter +1;
elsif data_valid = '1' and at_source_ready = '1' and (data_counter < COUNTER_LIMIT_g-1) then
data_counter <= data_counter +1;
elsif count_finished = true then
data_counter <= (others => '0');
end if;
end if;
end process packet_counter;
end generate counter_yes;
source_comb_update : process (--at_source_ready,
count_finished, count_started,
packet_error, packet_error0, source_state,
--at_source_valid_s
in_ready,
source_valid_ctrl)
begin -- process source_comb_update
case source_state is
when start =>
if packet_error0 = '1' then
source_next_state <= st_err;
at_source_error_int <= packet_error;
at_source_sop_int <= '0';
at_source_eop_int <= '1';
else
at_source_eop_int <= '0';
at_source_error_int <= "00";
if source_valid_ctrl = '1' and count_started = true then --and at_source_ready='1' then
source_next_state <= sop;
at_source_sop_int <= '1';
else
source_next_state <= start;
at_source_sop_int <= '0';
end if;
end if;
when sop =>
if packet_error0 = '1' then
source_next_state <= st_err;
at_source_error_int <= packet_error;
at_source_sop_int <= '0';
at_source_eop_int <= '1';
else
at_source_error_int <= "00";
at_source_eop_int <= '0';
--if source_valid_ctrl = '1' and at_source_ready = '1' and count_finished = false then
if source_valid_ctrl = '1' and in_ready = '1' and count_finished = false then
if PACKET_SIZE_g > 2 then
source_next_state <= run1;
else
source_next_state <= end1;
end if;
at_source_sop_int <= '0';
--elsif (at_source_ready = '1' and source_valid_ctrl = '1' and count_finished = true) or
elsif (in_ready = '1' and source_valid_ctrl = '1' and count_finished = true) or
(source_valid_ctrl = '0' and count_finished = true) then --valid_ctrl_int = '1' and
source_next_state <= end1;
at_source_error_int <= "00";
at_source_eop_int <= '1';
at_source_sop_int <= '0';
else
source_next_state <= sop;
at_source_sop_int <= '1';
end if;
end if;
when run1 =>
at_source_sop_int <= '0';
if packet_error0 = '1' then
source_next_state <= st_err;
at_source_error_int <= packet_error;
at_source_eop_int <= '1';
else
--if (at_source_ready = '1' and source_valid_ctrl = '1' and count_finished = true) or
if (in_ready = '1' and source_valid_ctrl = '1' and count_finished = true) or
(source_valid_ctrl = '0' and count_finished = true) then --valid_ctrl_int = '1' and
source_next_state <= end1;
at_source_error_int <= "00";
at_source_eop_int <= '1';
else
source_next_state <= run1;
at_source_error_int <= "00";
at_source_eop_int <= '0';
end if;
end if;
when end1 =>
if packet_error0 = '1' then
source_next_state <= st_err;
at_source_error_int <= packet_error;
at_source_sop_int <= '0';
at_source_eop_int <= '1';
else
at_source_error_int <= "00";
--if source_valid_ctrl = '1' and count_started = true and at_source_ready = '1' then
if source_valid_ctrl = '1' and count_started = true and in_ready = '1' then
source_next_state <= sop;
at_source_sop_int <= '1';
at_source_eop_int <= '0';
--elsif source_valid_ctrl = '1' and at_source_ready = '1' then
elsif source_valid_ctrl = '1' and in_ready = '1' then
source_next_state <= start;
at_source_sop_int <= '0';
at_source_eop_int <= '0';
else
source_next_state <= end1;
at_source_sop_int <= '0';
at_source_eop_int <= '1';
end if;
end if;
when st_err =>
at_source_sop_int <= '0';
at_source_eop_int <= '0';
if packet_error0 = '1' then
source_next_state <= st_err;
at_source_error_int <= packet_error;
else
source_next_state <= start;
at_source_error_int <= "00";
end if;
when others =>
source_next_state <= st_err;
at_source_sop_int <= '0';
at_source_eop_int <= '1';
at_source_error_int <= "11";
end case;
end process source_comb_update;
source_state_update : process (clk, reset_n)
begin -- process
if reset_n = '0' then
source_state <= start;
elsif clk'event and clk = '1' then
source_state <= source_next_state;
end if;
end process source_state_update;
end generate packet_multi;
at_source_sop <= at_source_sop_s;
at_source_eop <= at_source_eop_s;
at_source_error <= at_source_error_s;
channel_info_exists : if USE_PACKETS = 1 generate
at_source_channel <= channel_out;
end generate channel_info_exists;
no_channel_info : if USE_PACKETS = 0 generate
at_source_channel <= (others => '0');
end generate no_channel_info;
at_source_data <= data_out;
at_source_valid <= data_valid;
backpressure_support: if ENABLE_BACKPRESSURE_g = true generate
reset_design_int <= not reset_n;
--source_stall <= not(in_ready);
source_stall <= not(at_source_ready);
fifo_sop_in <= '0' when USE_PACKETS = 0 else
at_source_sop_int;
fifo_eop_in <= '0' when USE_PACKETS = 0 else
at_source_eop_int;
fifo_error_in <= "00" when USE_PACKETS = 0 else
at_source_error_int;
scfifo : altera_avalon_sc_fifo
generic map (
SYMBOLS_PER_BEAT => DATA_PORT_COUNT,
BITS_PER_SYMBOL => DATA_WIDTH,
FIFO_DEPTH => FIFO_DEPTH_c,
CHANNEL_WIDTH => log2_ceil_one(PACKET_SIZE_g),
ERROR_WIDTH => 2,
--EMPTY_LATENCY => 1,
USE_PACKETS => USE_PACKETS)
port map (
clk => clk,
reset => reset_design_int,
in_ready => in_ready,
--in_data => fifo_datain(((0*DATA_WIDTH)+DATA_WIDTH-1) downto (0*DATA_WIDTH)),
in_data => data_in,
in_valid => source_valid_ctrl,
in_error => fifo_error_in,
in_channel => data_count,
in_startofpacket => fifo_sop_in,
in_endofpacket => fifo_eop_in,
in_empty => (others => '0'),
csr_address => (others => '0'),
csr_write => '0',
csr_read => '0',
csr_writedata => (others => '0'),
out_ready => at_source_ready,
--out_data => fifo_dataout(((0*DATA_WIDTH)+DATA_WIDTH-1) downto (0*DATA_WIDTH)),
out_data => data_out,
out_valid => data_valid,
out_error => at_source_error_s,
out_channel => channel_out,
out_startofpacket => at_source_sop_s,
out_endofpacket => at_source_eop_s,
out_empty => open);
end generate backpressure_support;
backpressure_no_support: if ENABLE_BACKPRESSURE_g = false generate
in_ready <= '1';
source_stall <= '0';
output_registers : process (clk, reset_n)
begin
if reset_n = '0' then
channel_out <= (others => '0');
data_out <= (others => '0');
data_valid <= '0';
at_source_error_s <= "00";
at_source_sop_s <= '0';
at_source_eop_s <= '0';
elsif rising_edge(clk) then
channel_out <= data_count;
data_out <= data_in;
data_valid <= source_valid_ctrl;
at_source_error_s <= at_source_error_int;
at_source_sop_s <= at_source_sop_int;
at_source_eop_s <= at_source_eop_int;
end if;
end process output_registers;
end generate backpressure_no_support;
end rtl;
| gpl-2.0 | c5854b6cd18b36b6fc5fdca60c35ba50 | 0.544013 | 3.750489 | false | false | false | false |
estadofinito/biblioteca-vhdl | todos-los-archivos/clk1Hz.vhd | 3 | 1,395 | ----------------------------------------------------------------------------------
-- Compañía: Estado Finito
-- Ingeniero: Carlos Ramos
--
-- Fecha de creación: 2012/10/26 09:35:12
-- Nombre del módulo: clk1Hz - Behavioral
-- Descripción:
-- Divisor de frecuencia implementado con contadores. Este divisor de frecuencia
-- reduce la escala en un factor de 25000000 veces. En este caso, la frecuencia se
-- reduce de 50MHz de entrada a 1Hz a la salida.
--
-- Revisión:
-- Revisión 0.01 - Archivo creado.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity clk1Hz is
Port (
entrada: in STD_LOGIC;
reset : in STD_LOGIC;
salida : out STD_LOGIC
);
end clk1Hz;
architecture Behavioral of clk1Hz is
signal temporal: STD_LOGIC;
signal contador: integer range 0 to 24999999 := 0;
begin
divisor_frecuencia: process (reset, entrada) begin
if (reset = '1') then
temporal <= '0';
contador <= 0;
elsif rising_edge(entrada) then
if (contador = 24999999) then
temporal <= NOT(temporal);
contador <= 0;
else
contador <= contador+1;
end if;
end if;
end process;
salida <= temporal;
end Behavioral; | lgpl-2.1 | 4effd1b6e59449b3b6a01f1426037f79 | 0.525216 | 4.168168 | false | false | false | false |
dummylink/plnk_fpga-stack | Examples/xilinx_microblaze/avnet_lx9/pcores/plb_powerlink_v1_00_a/hdl/vhdl/OpenMAC_DPR_Xilinx.vhd | 2 | 11,805 | ------------------------------------------------------------------------------------------------------------------------
-- OpenMAC - DPR for Xilinx FPGA
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2009-08-07 V0.01 zelenkaj Converted to official version.
-- 2011-10-12 V0.10 zelenkaj Implementation is based on UG687 (v13.2)
------------------------------------------------------------------------------------------------------------------------
--
-- dual clocked DPRAM for XILINX SPARTAN 6 --
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity dc_dpr is
generic (
WIDTH : integer := 16;
SIZE : integer := 128;
ADDRWIDTH : integer := 7
);
port (
clkA : in std_logic;
clkB : in std_logic;
enA : in std_logic;
enB : in std_logic;
weA : in std_logic;
weB : in std_logic;
addrA : in std_logic_vector(ADDRWIDTH-1 downto 0);
addrB : in std_logic_vector(ADDRWIDTH-1 downto 0);
diA : in std_logic_vector(WIDTH-1 downto 0);
diB : in std_logic_vector(WIDTH-1 downto 0);
doA : out std_logic_vector(WIDTH-1 downto 0);
doB : out std_logic_vector(WIDTH-1 downto 0)
);
end dc_dpr;
architecture xilinx of dc_dpr is
function log2 (val: INTEGER) return natural is
variable res : natural;
begin
for i in 0 to 31 loop
if (val <= (2**i)) then
res := i;
exit;
end if;
end loop;
return res;
end function Log2;
type ramType is array (0 to SIZE-1) of std_logic_vector(WIDTH-1 downto 0);
shared variable ram : ramType := (others => (others => '0'));
signal readA : std_logic_vector(WIDTH-1 downto 0):= (others => '0');
signal readB : std_logic_vector(WIDTH-1 downto 0):= (others => '0');
begin
process (clkA)
begin
if rising_edge(clkA) then
if enA = '1' then
if weA = '1' then
ram(conv_integer(addrA)) := diA;
end if;
readA <= ram(conv_integer(addrA));
end if;
end if;
end process;
doA <= readA;
process (clkB)
begin
if rising_edge(clkB) then
if enB = '1' then
if weB = '1' then
ram(conv_integer(addrB)) := diB;
end if;
readB <= ram(conv_integer(addrB));
end if;
end if;
end process;
doB <= readB;
end xilinx;
-- dual clocked DPRAM with byte enables for XILINX SPARTAN 6 --
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity dc_dpr_be is
generic (
WIDTH : integer := 16;
SIZE : integer := 128;
ADDRWIDTH : integer := 7
);
port (
clkA : in std_logic;
clkB : in std_logic;
enA : in std_logic;
enB : in std_logic;
weA : in std_logic;
weB : in std_logic;
beA : in std_logic_vector(WIDTH/8-1 downto 0);
beB : in std_logic_vector(WIDTH/8-1 downto 0);
addrA : in std_logic_vector(ADDRWIDTH-1 downto 0);
addrB : in std_logic_vector(ADDRWIDTH-1 downto 0);
diA : in std_logic_vector(WIDTH-1 downto 0);
diB : in std_logic_vector(WIDTH-1 downto 0);
doA : out std_logic_vector(WIDTH-1 downto 0);
doB : out std_logic_vector(WIDTH-1 downto 0)
);
end dc_dpr_be;
architecture xilinx of dc_dpr_be is
function log2 (val: INTEGER) return natural is
variable res : natural;
begin
for i in 0 to 31 loop
if (val <= (2**i)) then
res := i;
exit;
end if;
end loop;
return res;
end function Log2;
type ramType is array (0 to SIZE-1) of std_logic_vector(WIDTH-1 downto 0);
shared variable ram : ramType := (others => (others => '0'));
constant BYTE : integer := 8;
signal readA : std_logic_vector(WIDTH-1 downto 0):= (others => '0');
signal readB : std_logic_vector(WIDTH-1 downto 0):= (others => '0');
begin
process (clkA)
begin
if rising_edge(clkA) then
if enA = '1' then
if weA = '1' then
for i in beA'range loop
if beA(i) = '1' then
ram(conv_integer(addrA))((i+1)*BYTE-1 downto i*BYTE) := diA((i+1)*BYTE-1 downto i*BYTE);
end if;
end loop;
end if;
readA <= ram(conv_integer(addrA));
end if;
end if;
end process;
doA <= readA;
process (clkB)
begin
if rising_edge(clkB) then
if enB = '1' then
if weB = '1' then
for i in beB'range loop
if beB(i) = '1' then
ram(conv_integer(addrB))((i+1)*BYTE-1 downto i*BYTE) := diB((i+1)*BYTE-1 downto i*BYTE);
end if;
end loop;
end if;
readB <= ram(conv_integer(addrB));
end if;
end if;
end process;
doB <= readB;
end xilinx;
-- dual clocked DPRAM with 16x16 --
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity Dpr_16_16 is
generic(Simulate : in boolean);
port (
ClkA, ClkB : in std_logic;
WeA, WeB : in std_logic := '0';
EnA, EnB : in std_logic := '1';
BeA : in std_logic_vector ( 1 downto 0) := "11";
AddrA : in std_logic_vector ( 7 downto 0);
DiA : in std_logic_vector (15 downto 0) := (others => '0');
DoA : out std_logic_vector(15 downto 0);
BeB : in std_logic_vector ( 1 downto 0) := "11";
AddrB : in std_logic_vector ( 7 downto 0);
DiB : in std_logic_vector (15 downto 0) := (others => '0');
DoB : out std_logic_vector(15 downto 0)
);
end Dpr_16_16;
architecture struct of Dpr_16_16 is
begin
dpr_packet: entity work.dc_dpr_be
generic map (
WIDTH => 16,
SIZE => 2**AddrA'length,
ADDRWIDTH => AddrA'length
)
port map (
clkA => ClkA, clkB => ClkB,
enA => EnA, enB => EnB,
addrA => AddrA, addrB => AddrB,
diA => DiA, diB => DiB,
doA => DoA, doB => DoB,
weA => WeA, weB => WeB,
beA => BeA, beB => BeB
);
end struct;
-- dual clocked DPRAM with 16x32 --
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity Dpr_16_32 is
generic(Simulate : in boolean);
port (
ClkA, ClkB : in std_logic;
WeA : in std_logic := '0';
EnA, EnB : in std_logic := '1';
AddrA : in std_logic_vector ( 7 downto 0);
DiA : in std_logic_vector (15 downto 0) := (others => '0');
BeA : in std_logic_vector ( 1 downto 0) := "11";
AddrB : in std_logic_vector ( 6 downto 0);
DoB : out std_logic_vector(31 downto 0)
);
end Dpr_16_32;
architecture struct of Dpr_16_32 is
signal addra_s : std_logic_vector(AddrB'range);
signal dia_s : std_logic_vector(DoB'range);
signal bea_s : std_logic_vector(DoB'length/8-1 downto 0);
begin
dpr_packet: entity work.dc_dpr_be
generic map (
WIDTH => 32,
SIZE => 2**AddrB'length,
ADDRWIDTH => AddrB'length
)
port map (
clkA => ClkA, clkB => ClkB,
enA => EnA, enB => EnB,
addrA => addra_s, addrB => AddrB,
diA => dia_s, diB => (others => '0'),
doA => open, doB => DoB,
weA => weA, weB => '0',
beA => bea_s, beB => (others => '1')
);
addra_s <= AddrA(AddrA'left downto 1);
dia_s <= DiA & DiA;
bea_s(3) <= BeA(1) and AddrA(0);
bea_s(2) <= BeA(0) and AddrA(0);
bea_s(1) <= BeA(1) and not AddrA(0);
bea_s(0) <= BeA(0) and not AddrA(0);
end struct;
-- dual clocked DPRAM with 32x32 for packets --
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY OpenMAC_DPRpackets IS
GENERIC
(
memSizeLOG2_g : integer := 10;
memSize_g : integer := 1024
);
PORT
(
address_a : IN STD_LOGIC_VECTOR (memSizeLOG2_g-2 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (memSizeLOG2_g-3 DOWNTO 0);
byteena_a : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '1');
byteena_b : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '1');
clock_a : IN STD_LOGIC := '1';
clock_b : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
rden_a : IN STD_LOGIC := '1';
rden_b : IN STD_LOGIC := '1';
wren_a : IN STD_LOGIC := '0';
wren_b : IN STD_LOGIC := '0';
q_a : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END OpenMAC_DPRpackets;
architecture struct of OpenMAC_DPRpackets is
signal address_a_s : std_logic_vector(address_b'range);
signal bea : std_logic_vector(byteena_b'range);
signal q_a_s, q_b_s, data_a_s : std_logic_vector(q_b'range);
signal q_a_s1 : std_logic_vector(q_a'range);
begin
dpr_packet: entity work.dc_dpr_be
generic map (
WIDTH => 32,
SIZE => memSize_g/4,
ADDRWIDTH => memSizeLOG2_g-2
)
port map (
clkA => clock_a, clkB => clock_b,
enA => '1', enB => '1',
addrA => address_a_s, addrB => address_b,
diA => data_a_s, diB => data_b,
doA => q_a_s, doB => q_b_s,
weA => wren_a, weB => wren_b,
beA => bea, beB => byteena_b
);
address_a_s <= address_a(address_a'left downto 1);
bea(3) <= byteena_a(1) and address_a(0);
bea(2) <= byteena_a(0) and address_a(0);
bea(1) <= byteena_a(1) and not address_a(0);
bea(0) <= byteena_a(0) and not address_a(0);
data_a_s <= data_a & data_a;
q_a_s1 <= q_a_s(q_a'length*2-1 downto q_a'length) when address_a(0) = '1' else
q_a_s(q_a'range);
--sync outputs
process(clock_a)
begin
if rising_edge(clock_a) then
q_a <= q_a_s1;
end if;
end process;
process(clock_b)
begin
if rising_edge(clock_b) then
q_b <= q_b_s;
end if;
end process;
end struct;
| gpl-2.0 | dc1b309a4574137012441731d693561e | 0.564168 | 2.985584 | false | false | false | false |
quicky2000/IP_register | delay_register.vhd | 1 | 2,147 | --
-- This file is part of IP_register
-- Copyright (C) 2011 Julien Thevenon ( julien_thevenon at yahoo.fr )
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity delay_register is
generic (
width : positive ;
delay : natural := 1); -- delay
port (
clk : in std_logic; -- clock
rst : in std_logic; --rst
input : in std_logic_vector(width - 1 downto 0); -- input
output : out std_logic_vector(width - 1 downto 0)); -- output
end delay_register;
architecture behavourial of delay_register is
-- signal delayed_output : std_logic_vector(delay downto 0) := (others => '0'); -- delayed output
type buffer_t is array (0 to delay) of std_logic_vector(width - 1 downto 0);
signal delayed_output : buffer_t := (others => (others => '0')); -- delayed output
begin -- behavourial
delayed_output(0) <= input;
delay_non_zero : if delay > 0 generate
delay_loop: for i in 0 to delay -1 generate
inst: entity work.my_register
generic map (
size => width
)
port map (
clk => clk,
rst => rst,
input => delayed_output(i),
output => delayed_output(i+1));
end generate delay_loop;
output <= delayed_output(delay);
end generate delay_non_zero;
delay_zero: if delay = 0 generate
output <= input;
end generate delay_zero;
end behavourial;
| gpl-3.0 | 08cc2f2db0ab450ea947ee10baa8f1f7 | 0.631579 | 3.875451 | false | false | false | false |
rflamino/StellaBlue | core/debouncevdhl.vhd | 1 | 1,002 | library IEEE;
use IEEE.std_logic_1164.ALL;
use ieee.std_logic_unsigned.all;
entity debouncevhdl is
Port (
Clock : in std_logic;
Reset : in std_logic;
ClockEn : in std_logic;
Din : in std_logic;
Dout : out std_logic
);
end debouncevhdl;
architecture Behavioral of debouncevhdl is
signal Sync_InSr : std_logic_vector(2 downto 0);
signal Cntr : std_logic_vector(7 downto 0);
begin
process(Clock, Reset)
begin
if (Reset = '1') then
Dout <= '0';
Cntr <= (Others => '0');
Sync_InSr <= (Others => '0');
elsif (Clock'event and Clock = '1') then
Sync_InSr <= Sync_InSr(1 downto 0) & Din;
if (ClockEn = '1') then
if (Sync_InSr(2 downto 1) = "00") then
if (Cntr /= x"00") then
Cntr <= Cntr - 1;
end if;
elsif (Sync_InSr(2 downto 1) = "11") then
if (Cntr /= x"FF") then
Cntr <= Cntr + 1;
end if;
end if;
if (Cntr = x"FF") then
Dout <= '1';
elsif (Cntr = x"00") then
Dout <= '0';
end if;
end if;
end if;
end process;
end Behavioral;
| mit | 1df79a75e39f4747941b9da86585904d | 0.603792 | 2.474074 | false | false | false | false |
takeshineshiro/fpga_linear_128 | tb_lf.vhd | 2 | 8,634 | -- ================================================================================
-- Legal Notice: Copyright (C) 1991-2006 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera. Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors. No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
-- ================================================================================
--
-- Generated by: FIR Compiler 9.0
-- Generated on: 2014-8-27 12:51:35
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
entity tb_lf is
--START MEGAWIZARD INSERT CONSTANTS
constant FIR_INPUT_FILE_c : string := "lf_input.txt";
constant FIR_OUTPUT_FILE_c : string := "lf_output.txt";
constant NUM_OF_CHANNELS_c : natural := 1;
constant DATA_WIDTH_c : natural := 15;
constant CHANNEL_OUT_WIDTH_c : natural := 0;
constant OUT_WIDTH_c : natural := 31;
constant COEF_SET_ADDRESS_WIDTH_c : natural := 0;
constant COEF_RELOAD_BIT_WIDTH_c : natural := 13;
--END MEGAWIZARD INSERT CONSTANTS
end entity tb_lf;
--library work;
--library auk_dspip_lib;
-------------------------------------------------------------------------------
architecture rtl of tb_lf is
signal ast_sink_data : std_logic_vector (DATA_WIDTH_c-1 downto 0) := (others => '0');
signal ast_source_data : std_logic_vector (OUT_WIDTH_c-1 downto 0);
signal ast_sink_error : std_logic_vector (1 downto 0) := (others => '0');
signal ast_source_error : std_logic_vector (1 downto 0);
signal ast_sink_valid : std_logic := '0';
signal ast_source_valid : std_logic;
signal ast_source_ready : std_logic := '0';
signal clk : std_logic := '0';
signal reset_testbench : std_logic := '0';
signal reset_design : std_logic;
signal eof : std_logic;
signal ast_sink_ready : std_logic;
signal start : std_logic;
signal cnt : natural range 0 to NUM_OF_CHANNELS_c;
constant tclk : time := 10 ns;
constant time_lapse_max : time := 60 us;
signal time_lapse : time;
begin
DUT : entity work.lf
port map (
clk => clk,
reset_n => reset_design,
ast_sink_ready => ast_sink_ready,
ast_sink_data => ast_sink_data,
ast_source_data => ast_source_data,
ast_sink_valid => ast_sink_valid,
ast_source_valid => ast_source_valid,
ast_source_ready => ast_source_ready,
ast_sink_error => ast_sink_error,
ast_source_error => ast_source_error);
-- for example purposes, the ready signal is always asserted.
ast_source_ready <= '1';
-- no input error
ast_sink_error <= (others => '0');
-- start valid for first cycle to indicate that the file reading should start.
start_p : process (clk, reset_testbench)
begin
if reset_testbench = '0' then
start <= '1';
elsif rising_edge(clk) then
if ast_sink_valid = '1' and ast_sink_ready = '1' then
start <= '0';
end if;
end if;
end process start_p;
-----------------------------------------------------------------------------------------------
-- Read input data from file
-----------------------------------------------------------------------------------------------
source_model : process(clk) is
file in_file : text open read_mode is FIR_INPUT_FILE_c;
variable data_in : integer;
variable indata : line;
begin
if rising_edge(clk) then
if(reset_testbench = '0') then
ast_sink_data <= std_logic_vector(to_signed(0, DATA_WIDTH_c)) after tclk/4;
ast_sink_valid <= '0' after tclk/4;
eof <= '0';
else
if not endfile(in_file) and (eof = '0') then
eof <= '0';
if((ast_sink_valid = '1' and ast_sink_ready = '1') or
(start = '1'and not (ast_sink_valid = '1' and ast_sink_ready = '0'))) then
readline(in_file, indata);
read(indata, data_in);
ast_sink_valid <= '1' after tclk/4;
ast_sink_data <= std_logic_vector(to_signed(data_in, DATA_WIDTH_c)) after tclk/4;
else
ast_sink_valid <= '1' after tclk/4;
ast_sink_data <= ast_sink_data after tclk/4;
end if;
else
eof <= '1';
ast_sink_valid <= '0' after tclk/4;
ast_sink_data <= std_logic_vector(to_signed(0, DATA_WIDTH_c)) after tclk/4;
end if;
end if;
end if;
end process source_model;
---------------------------------------------------------------------------------------------
-- Write FIR output to file
---------------------------------------------------------------------------------------------
sink_model : process(clk) is
file ro_file : text open write_mode is FIR_OUTPUT_FILE_c;
variable rdata : line;
variable data_r : integer;
begin
if rising_edge(clk) then
if(ast_source_valid = '1' and ast_source_ready = '1') then
data_r := to_integer(signed(ast_source_data));
write(rdata, data_r);
writeline(ro_file, rdata);
end if;
end if;
end process sink_model;
-------------------------------------------------------------------------------
-- clock generator
-------------------------------------------------------------------------------
clkgen : process
begin -- process clkgen
if eof = '1' then
clk <= '0';
assert FALSE
report "NOTE: Stimuli ended" severity note;
wait;
elsif time_lapse >= time_lapse_max then
clk <= '0';
assert FALSE
report "ERROR: Reached time_lapse_max without activity, probably simulation is stuck!" severity Error;
wait;
else
clk <= '0';
wait for tclk/2;
clk <= '1';
wait for tclk/2;
end if;
end process clkgen;
monitor_toggling_activity : process(clk, reset_testbench,
ast_source_data, ast_source_valid)
begin
if reset_testbench = '0' then
time_lapse <= 0 ns;
elsif ast_source_data'event or ast_source_valid'event then
time_lapse <= 0 ns;
elsif rising_edge(clk) then
if time_lapse < time_lapse_max then
time_lapse <= time_lapse + tclk;
end if;
end if;
end process monitor_toggling_activity;
-------------------------------------------------------------------------------
-- reset generator
-------------------------------------------------------------------------------
reset_testbench_gen : process
begin -- process resetgen
reset_testbench <= '1';
wait for tclk/4;
reset_testbench <= '0';
wait for tclk*2;
reset_testbench <= '1';
wait;
end process reset_testbench_gen;
reset_design_gen : process
begin -- process resetgen
reset_design <= '1';
wait for tclk/4;
reset_design <= '0';
wait for tclk*2;
reset_design <= '1';
wait for tclk*80;
reset_design <= '1';
wait for tclk*47*2;
reset_design <= '1';
wait;
end process reset_design_gen;
-------------------------------------------------------------------------------
-- control signals
-------------------------------------------------------------------------------
end architecture rtl;
| mit | 1e0045062a296146e2dbfd7b1f30b0a9 | 0.533241 | 4.189229 | false | false | false | false |
dummylink/plnk_fpga-stack | Examples/xilinx_microblaze/avnet_lx9/pcores/plb_powerlink_v1_00_a/hdl/vhdl/openMAC_16to32conv.vhd | 5 | 6,620 | -------------------------------------------------------------------------------
--
-- Title : openMAC_16to32conv
-- Design : POWERLINK
--
-------------------------------------------------------------------------------
--
-- File : openMAC_16to32conv.vhd
-- Generated : Mon Sep 12 15:35:37 2011
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2011
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- This is a 32-to-16 bit converter which is necessary for e.g. Xilinx PLB.
-- The component has to be connected to openMAC_Ethernet or powerlink.
-- NOT use this directly with openMAC!
--
-------------------------------------------------------------------------------
-- 2011-09-12 V0.01 zelenkaj Initial creation
-- 2011-10-10 V0.02 zelenkaj Split bus ack into wr/rd and bug fix
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
entity openMAC_16to32conv is
generic(
bus_address_width : integer := 10
);
port(
clk : in std_logic;
rst : in std_logic;
--port from 32bit bus
bus_select : in std_logic;
bus_write : in std_logic;
bus_read : in std_logic;
bus_byteenable : in std_logic_vector(3 downto 0);
bus_writedata : in std_logic_vector(31 downto 0);
bus_readdata : out std_logic_vector(31 downto 0);
bus_address : in std_logic_vector(bus_address_width-1 downto 0);
bus_ack_wr : out std_logic;
bus_ack_rd : out std_logic;
--port to openMAC_Ethernet
s_chipselect : out std_logic;
s_write : out std_logic;
s_read : out std_logic;
s_address : out std_logic_vector(bus_address_width-1 downto 0);
s_byteenable : out std_logic_vector(1 downto 0);
s_waitrequest : in std_logic;
s_readdata : in std_logic_vector(15 downto 0);
s_writedata : out std_logic_vector(15 downto 0)
);
end openMAC_16to32conv;
architecture rtl of openMAC_16to32conv is
-- types
type fsm_t is (idle, doAccess);
type bus_access_t is (none, dword, word);
-- fsm
signal fsm, fsm_next : fsm_t;
signal bus_access : bus_access_t;
-- cnt
signal cnt, cnt_next, cnt_load_val : std_logic_vector(1 downto 0);
signal cnt_load, cnt_dec, cnt_zero : std_logic;
signal bus_ack : std_logic;
-- word register
signal word_reg, word_reg_next : std_logic_vector(15 downto 0);
begin
process(clk, rst)
begin
if rst = '1' then
cnt <= (others => '0');
fsm <= idle;
word_reg <= (others => '0');
elsif clk = '1' and clk'event then
cnt <= cnt_next;
fsm <= fsm_next;
word_reg <= word_reg_next;
end if;
end process;
word_reg_next <= s_readdata when bus_access = dword and cnt = 2 and s_waitrequest = '0' else
word_reg;
s_chipselect <= bus_select; --not cnt_zero;
s_write <= bus_write and bus_select;
s_read <= bus_read and bus_select;
cnt_dec <= (not s_waitrequest) and bus_select;
bus_readdata <= word_reg & s_readdata when bus_access = dword else
s_readdata & s_readdata;
bus_ack <= '1' when cnt = 1 and s_waitrequest = '0' and bus_access = dword else
'1' when s_waitrequest = '0' and bus_access = word else
'0';
bus_ack_wr <= bus_ack and bus_write;
bus_ack_rd <= bus_ack and bus_read;
s_address(bus_address_width-1 downto 1) <= '0' & bus_address(bus_address_width-1 downto 2);
--word address set to +0 when first dword access or word access with selected word/byte
s_address(0) <= '0' when bus_access = dword and cnt = 2 else --first word of dword access
'1' when bus_access = dword and cnt = 1 else
bus_address(1);
s_byteenable <= "11" when bus_access = dword else
bus_byteenable(3 downto 2) or bus_byteenable(1 downto 0);
s_writedata <= bus_writedata(31 downto 16) when bus_access = dword and cnt = 2 else
bus_writedata(15 downto 0) when bus_access = dword and cnt = 1 else
bus_writedata(31 downto 16) when bus_address(1) = '0' else
bus_writedata(15 downto 0); --when bus_address(1) = '1' else
--fsm
bus_access <= none when bus_select /= '1' else
dword when bus_byteenable = "1111" else
word;
fsm_next <= doAccess when fsm = idle and cnt_zero = '1' and bus_access = dword else
idle when fsm = doAccess and cnt_zero = '1' and bus_access = none else
fsm;
--if dword, access twice, otherwise (byte, word) access once
cnt_load_val <= "10" when bus_byteenable = "1111" and bus_read = '1' else "01";
cnt_load <= '1' when fsm_next = doAccess and fsm = idle else '0';
--counter
cnt_next <= cnt_load_val when cnt_load = '1' else
cnt - 1 when cnt_dec = '1' and bus_access = dword else
cnt;
cnt_zero <= '1' when cnt = 0 else '0';
end rtl;
| gpl-2.0 | 2479333ef46b41a6b9e371f3b04ac286 | 0.610121 | 3.437175 | false | false | false | false |
dskntIndustry/Hardware | hdl_library/DSP/Filter/FIR/FIR_CoreTB.vhd | 1 | 2,865 | library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.std_logic_arith.ALL;
use IEEE.std_logic_unsigned.ALL;
library hdl_library_CommonFunctions;
use hdl_library_CommonFunctions.MathHelpers.all;
use hdl_library_CommonFunctions.CommonFunctions.all;
library hdl_library_ClockGenerator;
use hdl_library_ClockGenerator.all;
library hdl_library_DSP_Filter_FIR;
use hdl_library_DSP_Filter_FIR.all;
entity FIR_CoreTB is
end entity; --FIR_CoreTB
architecture arch of FIR_CoreTB is
constant G_CLOCK_FREQUENCY : integer := 100E6;
constant C_FIR_FILTER_ORDER : integer := 16;
constant C_DATA_IN_WIDTH : integer := 32;
constant C_DATA_OUT_WIDTH : integer := 32;
constant C_COEFF_WIDTH : integer := 32;
constant C_MULTIPLIER_DELAY : integer := 8;
constant C_ADDER_DELAY : integer := 8;
signal clock : std_logic := '0';
signal clock_n : std_logic := '0';
signal enable : std_logic := '0';
type T_COEFF_ROM is array(0 to C_FIR_FILTER_ORDER - 1) of std_logic_vector(C_COEFF_WIDTH - 1 downto 0);
signal coeff_ROM : T_COEFF_ROM := (others => (others => '0'));
signal xn : std_logic_vector(C_DATA_IN_WIDTH - 1 downto 0) := (others => '0');
signal xn_nd : std_logic := '0';
signal yn : std_logic_vector(C_DATA_OUT_WIDTH - 1 downto 0) := (others => '0');
signal yn_valid : std_logic := '0';
signal current_coefficient : std_logic_vector(C_COEFF_WIDTH - 1 downto 0) := (others => '0');
signal current_coefficient_address : std_logic_vector(log2(C_FIR_FILTER_ORDER) - 1 downto 0) := (others => '0');
--signal xn : std_logic_vector(C_DATA_IN_WIDTH - 1 downto 0) := (others => '0');
begin
clock <= not clock after (1 sec / G_CLOCK_FREQUENCY) / 2;
clock_n <= not clock;
enable <= '1' after 100 ns;
gen_valid_pulse:process
begin
xn_nd <= '0';
wait_until_rising_edges(clock, 1000);
xn_nd <= '1';
wait_until_rising_edges(clock, 1);
end process; --gen_valid_pulse
dut : entity hdl_library_DSP_Filter_FIR.FIR_Core
generic map
(
C_FIR_FILTER_ORDER => C_FIR_FILTER_ORDER,
C_DATA_IN_WIDTH => C_DATA_IN_WIDTH,
C_DATA_OUT_WIDTH => C_DATA_OUT_WIDTH,
C_COEFF_WIDTH => C_COEFF_WIDTH,
C_MULTIPLIER_DELAY => C_MULTIPLIER_DELAY,
C_ADDER_DELAY => C_ADDER_DELAY
)
port map
(
clock => clock,
enable => enable,
xn => xn,
xn_nd => xn_nd,
yn => yn,
yn_valid => yn_valid,
current_coefficient => current_coefficient,
current_coefficient_address => current_coefficient_address
--ready => ready
);
dataGenerator:process(clock)
begin
if rising_edge(clock) then
if xn_nd = '1' then
xn <= xn + 1;
end if;
end if;
end process dataGenerator; -- dataGenerator
end architecture; -- arch | gpl-3.0 | e8039e0b9766388c84339cd169c95297 | 0.620942 | 2.845084 | false | false | false | false |
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`protect end_protected
| gpl-3.0 | 57e98698113ed0a363ed98add2bedb1f | 0.924654 | 1.90559 | false | false | false | false |
dummylink/plnk_fpga-stack | Examples/xilinx_microblaze/avnet_lx9/pcores/plb_powerlink_v1_00_a/hdl/vhdl/portio_cnt.vhd | 5 | 3,520 | ------------------------------------------------------------------------------------------------------------------------
-- Simple Port I/O valid pulse counter
--
-- Copyright (C) 2010 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2011-09-14 V0.01 zelenkaj Extract from portio.vhd
------------------------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity portio_cnt is
generic (
maxVal : integer := 50 --clock ticks of pcp_clk
);
port (
clk : in std_logic;
rst : in std_logic;
pulse : in std_logic;
valid : out std_logic
);
end entity portio_cnt;
architecture rtl of portio_cnt is
signal cnt : integer range 0 to maxVal-2;
signal tc, en : std_logic;
begin
genCnter : if maxVal > 1 generate
tc <= '1' when cnt = maxVal-2 else '0';
valid <= en or pulse;
counter : process(clk, rst)
begin
if rst = '1' then
cnt <= 0;
elsif clk = '1' and clk'event then
if tc = '1' then
cnt <= 0;
elsif en = '1' then
cnt <= cnt + 1;
else
cnt <= 0;
end if;
end if;
end process;
enGen : process(clk, rst)
begin
if rst = '1' then
en <= '0';
elsif clk = '1' and clk'event then
if pulse = '1' then
en <= '1';
elsif tc = '1' then
en <= '0';
end if;
end if;
end process;
end generate;
genSimple : if maxVal = 1 generate
valid <= pulse;
end generate;
end architecture rtl; | gpl-2.0 | 2fa8f56da7d2273a1ba51cdfb7bcfc72 | 0.559659 | 3.972912 | false | false | false | false |
richard42/CoCo3FPGA | T65_MCode.vhd | 1 | 25,837 | -- ****
-- T65(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 301 Jump timing fixed
-- Ver 300 Bugfixes by ehenciak added
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- 65xx compatible microprocessor core
--
-- Version : 0246 + fix
--
-- Copyright (c) 2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t65/
--
-- Limitations :
--
-- 65C02
-- supported : inc, dec, phx, plx, phy, ply
-- missing : bra, ora, lda, cmp, sbc, tsb*2, trb*2, stz*2, bit*2, wai, stp, jmp, bbr*8, bbs*8
--
-- File history :
--
-- 0246 : First release
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T65_Pack.all;
entity T65_MCode is
port(
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816
IR : in std_logic_vector(7 downto 0);
MCycle : in std_logic_vector(2 downto 0);
P : in std_logic_vector(7 downto 0);
LCycle : out std_logic_vector(2 downto 0);
ALU_Op : out std_logic_vector(3 downto 0);
Set_BusA_To : out std_logic_vector(2 downto 0); -- DI,A,X,Y,S,P
Set_Addr_To : out std_logic_vector(1 downto 0); -- PC Adder,S,AD,BA
Write_Data : out std_logic_vector(2 downto 0); -- DL,A,X,Y,S,P,PCL,PCH
Jump : out std_logic_vector(1 downto 0); -- PC,++,DIDL,Rel
BAAdd : out std_logic_vector(1 downto 0); -- None,DB Inc,BA Add,BA Adj
BreakAtNA : out std_logic;
ADAdd : out std_logic;
AddY : out std_logic;
PCAdd : out std_logic;
Inc_S : out std_logic;
Dec_S : out std_logic;
LDA : out std_logic;
LDP : out std_logic;
LDX : out std_logic;
LDY : out std_logic;
LDS : out std_logic;
LDDI : out std_logic;
LDALU : out std_logic;
LDAD : out std_logic;
LDBAL : out std_logic;
LDBAH : out std_logic;
SaveP : out std_logic;
Write : out std_logic
);
end T65_MCode;
architecture rtl of T65_MCode is
signal Branch : std_logic;
begin
with IR(7 downto 5) select
Branch <= not P(Flag_N) when "000",
P(Flag_N) when "001",
not P(Flag_V) when "010",
P(Flag_V) when "011",
not P(Flag_C) when "100",
P(Flag_C) when "101",
not P(Flag_Z) when "110",
P(Flag_Z) when others;
process (IR, MCycle, P, Branch, Mode)
begin
LCycle <= "001";
Set_BusA_To <= "001"; -- A
Set_Addr_To <= (others => '0');
Write_Data <= (others => '0');
Jump <= (others => '0');
BAAdd <= "00";
BreakAtNA <= '0';
ADAdd <= '0';
PCAdd <= '0';
Inc_S <= '0';
Dec_S <= '0';
LDA <= '0';
LDP <= '0';
LDX <= '0';
LDY <= '0';
LDS <= '0';
LDDI <= '0';
LDALU <= '0';
LDAD <= '0';
LDBAL <= '0';
LDBAH <= '0';
SaveP <= '0';
Write <= '0';
AddY <= '0';
case IR(7 downto 5) is
when "100" =>
--{{{
case IR(1 downto 0) is
when "00" =>
Set_BusA_To <= "011"; -- Y
Write_Data <= "011"; -- Y
when "10" =>
Set_BusA_To <= "010"; -- X
Write_Data <= "010"; -- X
when others =>
Write_Data <= "001"; -- A
end case;
--}}}
when "101" =>
--{{{
case IR(1 downto 0) is
when "00" =>
if IR(4) /= '1' or IR(2) /= '0' then
LDY <= '1';
end if;
when "10" =>
LDX <= '1';
when others =>
LDA <= '1';
end case;
Set_BusA_To <= "000"; -- DI
--}}}
when "110" =>
--{{{
case IR(1 downto 0) is
when "00" =>
if IR(4) = '0' then
LDY <= '1';
end if;
Set_BusA_To <= "011"; -- Y
when others =>
Set_BusA_To <= "001"; -- A
end case;
--}}}
when "111" =>
--{{{
case IR(1 downto 0) is
when "00" =>
if IR(4) = '0' then
LDX <= '1';
end if;
Set_BusA_To <= "010"; -- X
when others =>
Set_BusA_To <= "001"; -- A
end case;
--}}}
when others =>
end case;
if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then
Set_BusA_To <= "000"; -- DI
end if;
case IR(4 downto 0) is
when "00000" | "01000" | "01010" | "11000" | "11010" =>
--{{{
-- Implied
case IR is
when "00000000" =>
-- BRK
LCycle <= "110";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= "01"; -- S
Write_Data <= "111"; -- PCH
Write <= '1';
when 2 =>
Dec_S <= '1';
Set_Addr_To <= "01"; -- S
Write_Data <= "110"; -- PCL
Write <= '1';
when 3 =>
Dec_S <= '1';
Set_Addr_To <= "01"; -- S
Write_Data <= "101"; -- P
Write <= '1';
when 4 =>
Dec_S <= '1';
Set_Addr_To <= "11"; -- BA
when 5 =>
LDDI <= '1';
Set_Addr_To <= "11"; -- BA
when 6 =>
Jump <= "10"; -- DIDL
when others =>
end case;
when "00100000" =>
-- JSR
LCycle <= "101";
case to_integer(unsigned(MCycle)) is
when 1 =>
Jump <= "01";
LDDI <= '1';
Set_Addr_To <= "01"; -- S
when 2 =>
Set_Addr_To <= "01"; -- S
Write_Data <= "111"; -- PCH
Write <= '1';
when 3 =>
Dec_S <= '1';
Set_Addr_To <= "01"; -- S
Write_Data <= "110"; -- PCL
Write <= '1';
when 4 =>
Dec_S <= '1';
when 5 =>
Jump <= "10"; -- DIDL
when others =>
end case;
when "01000000" =>
-- RTI
LCycle <= "101";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= "01"; -- S
when 2 =>
Inc_S <= '1';
Set_Addr_To <= "01"; -- S
when 3 =>
Inc_S <= '1';
Set_Addr_To <= "01"; -- S
Set_BusA_To <= "000"; -- DI
when 4 =>
LDP <= '1';
Inc_S <= '1';
LDDI <= '1';
Set_Addr_To <= "01"; -- S
when 5 =>
Jump <= "10"; -- DIDL
when others =>
end case;
when "01100000" =>
-- RTS
LCycle <= "101";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= "01"; -- S
when 2 =>
Inc_S <= '1';
Set_Addr_To <= "01"; -- S
when 3 =>
Inc_S <= '1';
LDDI <= '1';
Set_Addr_To <= "01"; -- S
when 4 =>
Jump <= "10"; -- DIDL
when 5 =>
Jump <= "01";
when others =>
end case;
when "00001000" | "01001000" | "01011010" | "11011010" =>
-- PHP, PHA, PHY*, PHX*
LCycle <= "010";
if Mode = "00" and IR(1) = '1' then
LCycle <= "001";
end if;
case to_integer(unsigned(MCycle)) is
when 1 =>
case IR(7 downto 4) is
when "0000" =>
Write_Data <= "101"; -- P
when "0100" =>
Write_Data <= "001"; -- A
when "0101" =>
Write_Data <= "011"; -- Y
when "1101" =>
Write_Data <= "010"; -- X
when others =>
end case;
Write <= '1';
Set_Addr_To <= "01"; -- S
when 2 =>
Dec_S <= '1';
when others =>
end case;
when "00101000" | "01101000" | "01111010" | "11111010" =>
-- PLP, PLA, PLY*, PLX*
LCycle <= "011";
if Mode = "00" and IR(1) = '1' then
LCycle <= "001";
end if;
case IR(7 downto 4) is
when "0010" =>
LDP <= '1';
when "0110" =>
LDA <= '1';
when "0111" =>
if Mode /= "00" then
LDY <= '1';
end if;
when "1111" =>
if Mode /= "00" then
LDX <= '1';
end if;
when others =>
end case;
case to_integer(unsigned(MCycle)) is
when 0 =>
SaveP <= '1';
when 1 =>
Set_Addr_To <= "01"; -- S
when 2 =>
Inc_S <= '1';
Set_Addr_To <= "01"; -- S
when 3 =>
Set_BusA_To <= "000"; -- DI
when others =>
end case;
when "10100000" | "11000000" | "11100000" =>
-- LDY, CPY, CPX
-- Immediate
case to_integer(unsigned(MCycle)) is
when 0 =>
when 1 =>
Jump <= "01";
when others =>
end case;
when "10001000" =>
-- DEY
LDY <= '1';
case to_integer(unsigned(MCycle)) is
when 0 =>
when 1 =>
Set_BusA_To <= "011"; -- Y
when others =>
end case;
when "11001010" =>
-- DEX
LDX <= '1';
case to_integer(unsigned(MCycle)) is
when 0 =>
when 1 =>
Set_BusA_To <= "010"; -- X
when others =>
end case;
when "00011010" | "00111010" =>
-- INC*, DEC*
if Mode /= "00" then
LDA <= '1'; -- A
end if;
case to_integer(unsigned(MCycle)) is
when 0 =>
when 1 =>
Set_BusA_To <= "100"; -- S
when others =>
end case;
when "00001010" | "00101010" | "01001010" | "01101010" =>
-- ASL, ROL, LSR, ROR
LDA <= '1'; -- A
Set_BusA_To <= "001"; -- A
case to_integer(unsigned(MCycle)) is
when 0 =>
when 1 =>
when others =>
end case;
when "10001010" | "10011000" =>
-- TYA, TXA
LDA <= '1'; -- A
case to_integer(unsigned(MCycle)) is
when 0 =>
when 1 =>
when others =>
end case;
when "10101010" | "10101000" =>
-- TAX, TAY
case to_integer(unsigned(MCycle)) is
when 0 =>
when 1 =>
Set_BusA_To <= "001"; -- A
when others =>
end case;
when "10011010" =>
-- TXS
case to_integer(unsigned(MCycle)) is
when 0 =>
LDS <= '1';
when 1 =>
when others =>
end case;
when "10111010" =>
-- TSX
LDX <= '1';
case to_integer(unsigned(MCycle)) is
when 0 =>
when 1 =>
Set_BusA_To <= "100"; -- S
when others =>
end case;
-- when "00011000" | "00111000" | "01011000" | "01111000" | "10111000" | "11011000" | "11111000" | "11001000" | "11101000" =>
-- -- CLC, SEC, CLI, SEI, CLV, CLD, SED, INY, INX
-- case to_integer(unsigned(MCycle)) is
-- when 1 =>
-- when others =>
-- end case;
when others =>
case to_integer(unsigned(MCycle)) is
when 0 =>
when others =>
end case;
end case;
--}}}
when "00001" | "00011" =>
--{{{
-- Zero Page Indexed Indirect (d,x)
LCycle <= "101";
if IR(7 downto 6) /= "10" then
LDA <= '1';
end if;
case to_integer(unsigned(MCycle)) is
when 0 =>
when 1 =>
Jump <= "01";
LDAD <= '1';
Set_Addr_To <= "10"; -- AD
when 2 =>
ADAdd <= '1';
Set_Addr_To <= "10"; -- AD
when 3 =>
BAAdd <= "01"; -- DB Inc
LDBAL <= '1';
Set_Addr_To <= "10"; -- AD
when 4 =>
LDBAH <= '1';
if IR(7 downto 5) = "100" then
Write <= '1';
end if;
Set_Addr_To <= "11"; -- BA
when 5 =>
when others =>
end case;
--}}}
when "01001" | "01011" =>
--{{{
-- Immediate
LDA <= '1';
case to_integer(unsigned(MCycle)) is
when 0 =>
when 1 =>
Jump <= "01";
when others =>
end case;
--}}}
when "00010" | "10010" =>
--{{{
-- Immediate, KIL
LDX <= '1';
case to_integer(unsigned(MCycle)) is
when 0 =>
when 1 =>
if IR = "10100010" then
-- LDX
Jump <= "01";
else
-- KIL !!!!!!!!!!!!!!!!!!!!!!!!!!!!!
end if;
when others =>
end case;
--}}}
when "00100" =>
--{{{
-- Zero Page
LCycle <= "010";
case to_integer(unsigned(MCycle)) is
when 0 =>
if IR(7 downto 5) = "001" then
SaveP <= '1';
end if;
when 1 =>
Jump <= "01";
LDAD <= '1';
if IR(7 downto 5) = "100" then
Write <= '1';
end if;
Set_Addr_To <= "10"; -- AD
when 2 =>
when others =>
end case;
--}}}
when "00101" | "00110" | "00111" =>
--{{{
-- Zero Page
if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then
-- Read-Modify-Write
LCycle <= "100";
case to_integer(unsigned(MCycle)) is
when 1 =>
Jump <= "01";
LDAD <= '1';
Set_Addr_To <= "10"; -- AD
when 2 =>
LDDI <= '1';
Write <= '1';
Set_Addr_To <= "10"; -- AD
when 3 =>
LDALU <= '1';
SaveP <= '1';
Write <= '1';
Set_Addr_To <= "10"; -- AD
when 4 =>
when others =>
end case;
else
LCycle <= "010";
if IR(7 downto 6) /= "10" then
LDA <= '1';
end if;
case to_integer(unsigned(MCycle)) is
when 0 =>
when 1 =>
Jump <= "01";
LDAD <= '1';
if IR(7 downto 5) = "100" then
Write <= '1';
end if;
Set_Addr_To <= "10"; -- AD
when 2 =>
when others =>
end case;
end if;
--}}}
when "01100" =>
--{{{
-- Absolute
if IR(7 downto 6) = "01" and IR(4 downto 0) = "01100" then
-- JMP
if IR(5) = '0' then
--LCycle <= "011";
LCycle <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Jump <= "01";
LDDI <= '1';
when 2 =>
Jump <= "10"; -- DIDL
when others =>
end case;
else
LCycle <= "101";
case to_integer(unsigned(MCycle)) is
when 2 =>
Jump <= "01";
LDDI <= '1';
LDBAL <= '1';
when 3 =>
LDBAH <= '1';
if Mode /= "00" then
Jump <= "10"; -- DIDL
end if;
if Mode = "00" then
Set_Addr_To <= "11"; -- BA
end if;
when 4 =>
LDDI <= '1';
if Mode = "00" then
Set_Addr_To <= "11"; -- BA
BAAdd <= "01"; -- DB Inc
else
Jump <= "01";
end if;
when 5 =>
Jump <= "10"; -- DIDL
when others =>
end case;
end if;
else
LCycle <= "011";
case to_integer(unsigned(MCycle)) is
when 0 =>
if IR(7 downto 5) = "001" then
SaveP <= '1';
end if;
when 1 =>
Jump <= "01";
LDBAL <= '1';
when 2 =>
Jump <= "01";
LDBAH <= '1';
if IR(7 downto 5) = "100" then
Write <= '1';
end if;
Set_Addr_To <= "11"; -- BA
when 3 =>
when others =>
end case;
end if;
--}}}
when "01101" | "01110" | "01111" =>
--{{{
-- Absolute
if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then
-- Read-Modify-Write
LCycle <= "101";
case to_integer(unsigned(MCycle)) is
when 1 =>
Jump <= "01";
LDBAL <= '1';
when 2 =>
Jump <= "01";
LDBAH <= '1';
Set_Addr_To <= "11"; -- BA
when 3 =>
LDDI <= '1';
Write <= '1';
Set_Addr_To <= "11"; -- BA
when 4 =>
Write <= '1';
LDALU <= '1';
SaveP <= '1';
Set_Addr_To <= "11"; -- BA
when 5 =>
SaveP <= '0'; -- MIKEJ was 1
when others =>
end case;
else
LCycle <= "011";
if IR(7 downto 6) /= "10" then
LDA <= '1';
end if;
case to_integer(unsigned(MCycle)) is
when 0 =>
when 1 =>
Jump <= "01";
LDBAL <= '1';
when 2 =>
Jump <= "01";
LDBAH <= '1';
if IR(7 downto 5) = "100" then
Write <= '1';
end if;
Set_Addr_To <= "11"; -- BA
when 3 =>
when others =>
end case;
end if;
--}}}
when "10000" =>
--{{{
-- Relative
-- This circuit dictates when the last
-- microcycle occurs for the branch depending on
-- whether or not the branch is taken and if a page
-- is crossed...
if (Branch = '1') then
LCycle <= "011"; -- We're done @ T3 if branching...upper
-- level logic will stop at T2 if no page cross
-- (See the Break signal)
else
LCycle <= "001";
end if;
-- This decodes the current microcycle and takes the
-- proper course of action...
case to_integer(unsigned(MCycle)) is
-- On the T1 microcycle, increment the program counter
-- and instruct the upper level logic to fetch the offset
-- from the Din bus and store it in the data latches. This
-- will be the last microcycle if the branch isn't taken.
when 1 =>
Jump <= "01"; -- Increments the PC by one (PC will now be PC+2)
-- from microcycle T0.
LDDI <= '1'; -- Tells logic in top level (T65.vhd) to route
-- the Din bus to the memory data latch (DL)
-- so that the branch offset is fetched.
-- In microcycle T2, tell the logic in the top level to
-- add the offset. If the most significant byte of the
-- program counter (i.e. the current "page") does not need
-- updating, we are done here...the Break signal at the
-- T65.vhd level takes care of that...
when 2 =>
Jump <= "11"; -- Tell the PC Jump logic to use relative mode.
PCAdd <= '1'; -- This tells the PC adder to update itself with
-- the current offset recently fetched from
-- memory.
-- The following is microcycle T3 :
-- The program counter should be completely updated
-- on this cycle after the page cross is detected.
-- We don't need to do anything here...
when 3 =>
when others => null; -- Do nothing.
end case;
--}}}
when "10001" | "10011" =>
--{{{
-- Zero Page Indirect Indexed (d),y
LCycle <= "101";
if IR(7 downto 6) /= "10" then
LDA <= '1';
end if;
case to_integer(unsigned(MCycle)) is
when 0 =>
when 1 =>
Jump <= "01";
LDAD <= '1';
Set_Addr_To <= "10"; -- AD
when 2 =>
LDBAL <= '1';
BAAdd <= "01"; -- DB Inc
Set_Addr_To <= "10"; -- AD
when 3 =>
Set_BusA_To <= "011"; -- Y
BAAdd <= "10"; -- BA Add
LDBAH <= '1';
Set_Addr_To <= "11"; -- BA
when 4 =>
BAAdd <= "11"; -- BA Adj
if IR(7 downto 5) = "100" then
Write <= '1';
else
BreakAtNA <= '1';
end if;
Set_Addr_To <= "11"; -- BA
when 5 =>
when others =>
end case;
--}}}
when "10100" | "10101" | "10110" | "10111" =>
--{{{
-- Zero Page, X
if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then
-- Read-Modify-Write
LCycle <= "101";
case to_integer(unsigned(MCycle)) is
when 1 =>
Jump <= "01";
LDAD <= '1';
Set_Addr_To <= "10"; -- AD
when 2 =>
ADAdd <= '1';
Set_Addr_To <= "10"; -- AD
when 3 =>
LDDI <= '1';
Write <= '1';
Set_Addr_To <= "10"; -- AD
when 4 =>
LDALU <= '1';
SaveP <= '1';
Write <= '1';
Set_Addr_To <= "10"; -- AD
when 5 =>
when others =>
end case;
else
LCycle <= "011";
if IR(7 downto 6) /= "10" then
LDA <= '1';
end if;
case to_integer(unsigned(MCycle)) is
when 0 =>
when 1 =>
Jump <= "01";
LDAD <= '1';
Set_Addr_To <= "10"; -- AD
when 2 =>
ADAdd <= '1';
-- Added this check for Y reg. use...
if (IR(3 downto 0) = "0110") then
AddY <= '1';
end if;
if IR(7 downto 5) = "100" then
Write <= '1';
end if;
Set_Addr_To <= "10"; -- AD
when 3 => null;
when others =>
end case;
end if;
--}}}
when "11001" | "11011" =>
--{{{
-- Absolute Y
LCycle <= "100";
if IR(7 downto 6) /= "10" then
LDA <= '1';
end if;
case to_integer(unsigned(MCycle)) is
when 0 =>
when 1 =>
Jump <= "01";
LDBAL <= '1';
when 2 =>
Jump <= "01";
Set_BusA_To <= "011"; -- Y
BAAdd <= "10"; -- BA Add
LDBAH <= '1';
Set_Addr_To <= "11"; -- BA
when 3 =>
BAAdd <= "11"; -- BA adj
if IR(7 downto 5) = "100" then
Write <= '1';
else
BreakAtNA <= '1';
end if;
Set_Addr_To <= "11"; -- BA
when 4 =>
when others =>
end case;
--}}}
when "11100" | "11101" | "11110" | "11111" =>
--{{{
-- Absolute X
if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then
-- Read-Modify-Write
LCycle <= "110";
case to_integer(unsigned(MCycle)) is
when 1 =>
Jump <= "01";
LDBAL <= '1';
when 2 =>
Jump <= "01";
Set_BusA_To <= "010"; -- X
BAAdd <= "10"; -- BA Add
LDBAH <= '1';
Set_Addr_To <= "11"; -- BA
when 3 =>
BAAdd <= "11"; -- BA adj
Set_Addr_To <= "11"; -- BA
when 4 =>
LDDI <= '1';
Write <= '1';
Set_Addr_To <= "11"; -- BA
when 5 =>
LDALU <= '1';
SaveP <= '1';
Write <= '1';
Set_Addr_To <= "11"; -- BA
when 6 =>
when others =>
end case;
else
LCycle <= "100";
if IR(7 downto 6) /= "10" then
LDA <= '1';
end if;
case to_integer(unsigned(MCycle)) is
when 0 =>
when 1 =>
Jump <= "01";
LDBAL <= '1';
when 2 =>
Jump <= "01";
-- mikej
-- special case 0xBE which uses Y reg as index!!
if (IR = "10111110") then
Set_BusA_To <= "011"; -- Y
else
Set_BusA_To <= "010"; -- X
end if;
BAAdd <= "10"; -- BA Add
LDBAH <= '1';
Set_Addr_To <= "11"; -- BA
when 3 =>
BAAdd <= "11"; -- BA adj
if IR(7 downto 5) = "100" then
Write <= '1';
else
BreakAtNA <= '1';
end if;
Set_Addr_To <= "11"; -- BA
when 4 =>
when others =>
end case;
end if;
--}}}
when others =>
end case;
end process;
process (IR, MCycle)
begin
-- ORA, AND, EOR, ADC, NOP, LD, CMP, SBC
-- ASL, ROL, LSR, ROR, BIT, LD, DEC, INC
case IR(1 downto 0) is
when "00" =>
--{{{
case IR(4 downto 2) is
when "000" | "001" | "011" =>
case IR(7 downto 5) is
when "110" | "111" =>
-- CP
ALU_Op <= "0110";
when "101" =>
-- LD
ALU_Op <= "0101";
when "001" =>
-- BIT
ALU_Op <= "1100";
when others =>
-- NOP/ST
ALU_Op <= "0100";
end case;
when "010" =>
case IR(7 downto 5) is
when "111" | "110" =>
-- IN
ALU_Op <= "1111";
when "100" =>
-- DEY
ALU_Op <= "1110";
when others =>
-- LD
ALU_Op <= "1101";
end case;
when "110" =>
case IR(7 downto 5) is
when "100" =>
-- TYA
ALU_Op <= "1101";
when others =>
ALU_Op <= "----";
end case;
when others =>
case IR(7 downto 5) is
when "101" =>
-- LD
ALU_Op <= "1101";
when others =>
ALU_Op <= "0100";
end case;
end case;
--}}}
when "01" => -- OR
--{{{
ALU_Op(3) <= '0';
ALU_Op(2 downto 0) <= IR(7 downto 5);
--}}}
when "10" =>
--{{{
ALU_Op(3) <= '1';
ALU_Op(2 downto 0) <= IR(7 downto 5);
case IR(7 downto 5) is
when "000" =>
if IR(4 downto 2) = "110" then
-- INC
ALU_Op <= "1111";
end if;
when "001" =>
if IR(4 downto 2) = "110" then
-- DEC
ALU_Op <= "1110";
end if;
when "100" =>
if IR(4 downto 2) = "010" then
-- TXA
ALU_Op <= "0101";
else
ALU_Op <= "0100";
end if;
when others =>
end case;
--}}}
when others =>
--{{{
case IR(7 downto 5) is
when "100" =>
ALU_Op <= "0100";
when others =>
if MCycle = "000" then
ALU_Op(3) <= '0';
ALU_Op(2 downto 0) <= IR(7 downto 5);
else
ALU_Op(3) <= '1';
ALU_Op(2 downto 0) <= IR(7 downto 5);
end if;
end case;
--}}}
end case;
end process;
end;
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`protect end_protected
| gpl-3.0 | 9509fdb226cd38f945b1fe0d296f0d8d | 0.950555 | 1.829536 | false | false | false | false |
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