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FinnK/lems2hdl | work/N3_pointCellCondBased/ISIM_output/reverseRateh1.vhdl | 1 | 11,069 |
---------------------------------------------------------------------
-- Standard Library bits
---------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- For Modelsim
--use ieee.fixed_pkg.all;
--use ieee.fixed_float_types.ALL;
-- For ISE
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use ieee_proposed.fixed_float_types.ALL;
use IEEE.numeric_std.all;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Entity Description
---------------------------------------------------------------------
entity reverseRateh1 is
Port (
clk : in STD_LOGIC; --SYSTEM CLOCK, THIS ITSELF DOES NOT SIGNIFY TIME STEPS - AKA A SINGLE TIMESTEP MAY TAKE MANY CLOCK CYCLES
init_model : in STD_LOGIC; --SYNCHRONOUS RESET
step_once_go : in STD_LOGIC; --signals to the neuron from the core that a time step is to be simulated
component_done : out STD_LOGIC;
requirement_voltage_v : in sfixed (2 downto -22);
param_per_time_rate : in sfixed (18 downto -2);
param_voltage_midpoint : in sfixed (2 downto -22);
param_voltage_scale : in sfixed (2 downto -22);
param_voltage_inv_scale_inv : in sfixed (22 downto -2);
exposure_per_time_r : out sfixed (18 downto -2);
derivedvariable_per_time_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_r_in : in sfixed (18 downto -2);
sysparam_time_timestep : in sfixed (-6 downto -22);
sysparam_time_simtime : in sfixed (6 downto -22)
);
end reverseRateh1;
---------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-- Architecture Begins
-------------------------------------------------------------------------------------------
architecture RTL of reverseRateh1 is
signal COUNT : unsigned(2 downto 0) := "000";
signal childrenCombined_Component_done_single_shot_fired : STD_LOGIC := '0';
signal childrenCombined_Component_done_single_shot : STD_LOGIC := '0';
signal childrenCombined_Component_done : STD_LOGIC := '0';
signal Component_done_int : STD_LOGIC := '0';
signal subprocess_der_int_pre_ready : STD_LOGIC := '0';
signal subprocess_der_int_ready : STD_LOGIC := '0';
signal subprocess_der_ready : STD_LOGIC := '0';
signal subprocess_dyn_int_pre_ready : STD_LOGIC := '0';
signal subprocess_dyn_int_ready : STD_LOGIC := '0';
signal subprocess_dyn_ready : STD_LOGIC := '0';
signal subprocess_model_ready : STD_LOGIC := '1';
signal subprocess_all_ready_shotdone : STD_LOGIC := '1';
signal subprocess_all_ready_shot : STD_LOGIC := '0';
signal subprocess_all_ready : STD_LOGIC := '0';signal pre_exp_r_exponential_result1 : sfixed(18 downto -13);
signal pre_exp_r_exponential_result1_next : sfixed(18 downto -13);
signal exp_r_exponential_result1 : sfixed(18 downto -13);
Component ParamExp is
generic(
BIT_TOP : integer := 20;
BIT_BOTTOM : integer := -20);
port(
clk : In Std_logic;
init_model : In Std_logic;
Start : In Std_logic;
Done : Out Std_logic;
X : In sfixed(BIT_TOP downto BIT_BOTTOM);
Output : Out sfixed(BIT_TOP downto BIT_BOTTOM)
);
end Component;
component delayDone is
generic(
Steps : integer := 10);
port(
clk : In Std_logic;
init_model : In Std_logic;
Start : In Std_logic;
Done : Out Std_logic
);
end component;
---------------------------------------------------------------------
-- Derived Variables and parameters
---------------------------------------------------------------------
signal DerivedVariable_per_time_r : sfixed (18 downto -2) := to_sfixed(0.0 ,18,-2);
signal DerivedVariable_per_time_r_next : sfixed (18 downto -2) := to_sfixed(0.0 ,18,-2);
---------------------------------------------------------------------
---------------------------------------------------------------------
-- EDState internal Variables
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Output Port internal Variables
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Child Components
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Begin Internal Processes
---------------------------------------------------------------------
begin
---------------------------------------------------------------------
-- Child EDComponent Instantiations and corresponding internal variables
---------------------------------------------------------------------
derived_variable_pre_process_comb :process ( sysparam_time_timestep, param_voltage_midpoint, param_voltage_scale, requirement_voltage_v , param_per_time_rate,param_voltage_inv_scale_inv,exp_r_exponential_result1 )
begin
pre_exp_r_exponential_result1_next <= resize( ( to_sfixed ( 0 ,0 , -1 ) - ( requirement_voltage_v - param_voltage_midpoint ) * param_voltage_inv_scale_inv ) ,18,-13);
end process derived_variable_pre_process_comb;
derived_variable_pre_process_syn :process ( clk, init_model )
begin
if (clk'EVENT AND clk = '1') then
if init_model = '1' then
pre_exp_r_exponential_result1 <= to_sfixed(0,18,-13);
else
if subprocess_all_ready_shot = '1' then
pre_exp_r_exponential_result1 <= pre_exp_r_exponential_result1_next;
end if;
end if;
end if;
subprocess_der_int_pre_ready <= '1';
end process derived_variable_pre_process_syn;
ParamExp_r_exponential_result1 : ParamExp
generic map(
BIT_TOP => 18,
BIT_BOTTOM => -13
)
port map ( clk => clk,
init_model => init_model,
Start => step_once_go,
Done => subprocess_der_int_ready,
X => pre_exp_r_exponential_result1 ,
Output => exp_r_exponential_result1
);
derived_variable_process_comb :process ( sysparam_time_timestep, param_voltage_midpoint, param_voltage_scale, requirement_voltage_v , param_per_time_rate,param_voltage_inv_scale_inv,exp_r_exponential_result1 )
begin
derivedvariable_per_time_r_next <= resize(( param_per_time_rate / ( to_sfixed ( 1 ,1 , -1 ) + exp_r_exponential_result1 ) ),18,-2);
end process derived_variable_process_comb;
uut_delayDone_derivedvariable_reverseRateh1 : delayDone GENERIC MAP(
Steps => 2
)
PORT MAP(
clk => clk,
init_model => init_model,
Start => step_once_go,
Done => subprocess_der_ready
);
derived_variable_process_syn :process ( clk,init_model )
begin
if clk'event and clk = '1' then
if subprocess_all_ready_shot = '1' then
derivedvariable_per_time_r <= derivedvariable_per_time_r_next;
end if;
end if;
end process derived_variable_process_syn;
---------------------------------------------------------------------
dynamics_pre_process_comb :process ( sysparam_time_timestep )
begin
end process dynamics_pre_process_comb;
dynamics_pre_process_syn :process ( clk, init_model )
begin
subprocess_dyn_int_pre_ready <= '1';
end process dynamics_pre_process_syn;
--No dynamics with complex equations found
subprocess_dyn_int_ready <= '1';
state_variable_process_dynamics_comb :process (sysparam_time_timestep)
begin
subprocess_dyn_ready <= '1';
end process state_variable_process_dynamics_comb;
state_variable_process_dynamics_syn :process (CLK,init_model)
begin
if clk'event and clk = '1' then
if subprocess_all_ready_shot = '1' then
end if;
end if;
end process state_variable_process_dynamics_syn;
------------------------------------------------------------------------------------------------------
-- EDState Variable Drivers
------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign state variables to exposures
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign state variables to output state variables
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign derived variables to exposures
---------------------------------------------------------------------
exposure_per_time_r <= derivedvariable_per_time_r_in;derivedvariable_per_time_r_out <= derivedvariable_per_time_r;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Subprocess ready process
---------------------------------------------------------------------
subprocess_all_ready_process: process(step_once_go,subprocess_der_int_ready,subprocess_der_int_pre_ready,subprocess_der_ready,subprocess_dyn_int_pre_ready,subprocess_dyn_int_ready,subprocess_dyn_ready,subprocess_model_ready)
begin
if step_once_go = '0' and subprocess_der_int_ready = '1' and subprocess_der_int_pre_ready = '1'and subprocess_der_ready ='1' and subprocess_dyn_int_ready = '1' and subprocess_dyn_int_pre_ready = '1' and subprocess_dyn_ready = '1' and subprocess_model_ready = '1' then
subprocess_all_ready <= '1';
else
subprocess_all_ready <= '0';
end if;
end process subprocess_all_ready_process;
subprocess_all_ready_shot_process : process(clk)
begin
if rising_edge(clk) then
if (init_model='1') then
subprocess_all_ready_shot <= '0';
subprocess_all_ready_shotdone <= '1';
else
if subprocess_all_ready = '1' and subprocess_all_ready_shotdone = '0' then
subprocess_all_ready_shot <= '1';
subprocess_all_ready_shotdone <= '1';
elsif subprocess_all_ready_shot = '1' then
subprocess_all_ready_shot <= '0';
elsif subprocess_all_ready = '0' then
subprocess_all_ready_shot <= '0';
subprocess_all_ready_shotdone <= '0';
end if;
end if;
end if;
end process subprocess_all_ready_shot_process;
---------------------------------------------------------------------
count_proc:process(clk)
begin
if (clk'EVENT AND clk = '1') then
if init_model = '1' then COUNT <= "001";
component_done_int <= '1';
else if step_once_go = '1' then
COUNT <= "000";
component_done_int <= '0';
elsif COUNT = "001" then
component_done_int <= '1';
elsif subprocess_all_ready_shot = '1' then
COUNT <= COUNT + 1;
component_done_int <= '0';
end if;
end if;
end if;
end process count_proc;
component_done <= component_done_int;
end RTL;
| lgpl-3.0 | 1fee4687fbe88b187b93ba58e8546316 | 0.510886 | 4.014871 | false | false | false | false |
sergev/vak-opensource | hardware/dlx/dlx_bus_monitor-behaviour.vhdl | 1 | 5,425 | --------------------------------------------------------------------------
--
-- Copyright (C) 1993, Peter J. Ashenden
-- Mail: Dept. Computer Science
-- University of Adelaide, SA 5005, Australia
-- e-mail: [email protected]
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 1, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
--------------------------------------------------------------------------
--
-- $RCSfile: dlx_bus_monitor-behaviour.vhdl,v $ $Revision: 2.1 $ $Date: 1993/10/31 22:36:40 $
--
--------------------------------------------------------------------------
--
-- Behavioural architecture of DLX bus monitor
--
use std.textio.all,
work.dlx_instr.all,
work.images.image_hex;
architecture behaviour of dlx_bus_monitor is
begin
monitor : if enable generate
enabled_monitor : process
variable write_command, instr_fetch : boolean;
variable L : line;
begin
monitor_loop : loop
--
-- wait for a command, valid on leading edge of phi2
--
wait until phi2 = '1' and mem_enable = '1';
--
-- capture the command information
--
write_command := write_enable = '1';
instr_fetch := ifetch = '1';
write(L, tag);
write(L, string'(": "));
if write_command then
write(L, string'("D-write to "));
elsif instr_fetch then
write(L, string'("I-fetch from "));
else
write(L, string'("D-read from "));
end if;
write(L, image_hex(a));
if verbose then
case width is
when width_word =>
write(L, string'(", word"));
when width_halfword =>
write(L, string'(", halfword"));
when width_byte =>
write(L, string'(", byte"));
end case;
if burst = '1' then
write(L, string'(", burst "));
else
write(L, string'(", single "));
end if;
writeline(output, L);
else
if not instr_fetch then
write(L, string'(", data"));
else
writeline(output, L);
end if;
end if;
--
burst_loop : loop
if write_command then
if verbose then
write(L, tag);
write(L, string'(": Write data "));
write(L, image_hex(d));
writeline(output, L);
else
write(L, ' ');
write(L, image_hex(d));
end if;
end if;
-- wait for the response from memory
loop
wait until phi2 = '0';
if reset = '1' then
exit monitor_loop;
end if;
exit when ready = '1';
end loop;
if write_command then
if verbose then
write(L, tag);
write(L, string'(": Ready"));
writeline(output, L);
end if;
elsif instr_fetch then
if verbose then
write(L, tag);
write(L, string'(": Ready, instruction "));
write(L, image_hex(d));
write(L, string'(" [ "));
write_instr(L, d);
write(L, string'(" ]"));
writeline(output, L);
else -- brief instruction fetch
write(L, tag);
write(L, string'(": "));
write(L, image_hex(d));
write(L, string'(" [ "));
write_instr(L, d);
write(L, string'(" ]"));
writeline(output, L);
end if;
else -- data fetch
if verbose then
write(L, tag);
write(L, string'(": Ready, data "));
write(L, image_hex(d));
writeline(output, L);
else -- brief data fetch
write(L, ' ');
write(L, image_hex(d));
end if;
end if;
exit burst_loop when burst = '0';
end loop burst_loop;
--
if not verbose and not instr_fetch then
writeline(output, L);
end if;
end loop monitor_loop;
--
-- get here when reset is asserted
--
assert reset = '1'
report "reset code reached with reset = '0'" severity error;
write(L, string'("DLX_bus_monitor: Reset"));
writeline(output, L);
wait until phi2 = '0' and reset = '0';
write(L, string'("DLX_bus_monitor: End Reset"));
writeline(output, L);
--
-- process monitor now starts again from beginning
--
end process enabled_monitor;
end generate;
end behaviour;
| apache-2.0 | ad8cd2f57925e7026bdaa3131e033931 | 0.476313 | 4.446721 | false | false | false | false |
paulino/digilentinc-peripherals | bench/port_display32_dig_tb.vhd | 1 | 2,268 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11.03.2015 09:34:55
-- Design Name:
-- Module Name: port_display32_dig_tb - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.digilent_peripherals_pk.all;
entity port_display32_dig_tb is
end port_display32_dig_tb;
architecture Behavioral of port_display32_dig_tb is
signal clk,w,enable,dp_out,reset : std_logic;
signal byte_sel : std_logic_vector(1 downto 0);
signal digit_in : std_logic_vector(7 downto 0);
signal dp_in : std_logic_vector(1 downto 0);
signal seg_out : std_logic_vector(6 downto 0);
signal an_out : std_logic_vector(7 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
begin
-- Display, 8 bits are written from switches
u_display : port_display32_dig port map (
clk => clk,
w => w,
enable => enable,
byte_sel => byte_sel,
digit_in => digit_in,
dp_in => dp_in,
seg_out => seg_out,
dp_out => dp_out,
an_out => an_out,
reset => reset
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
enable <= '0';
w <= '0';
reset <= '1';
wait for clk_period*5;
reset <= '0';
wait until rising_edge(clk);
digit_in <= x"F0";
dp_in <= "01";
byte_sel <= "00";
w <= '1';
enable <= '1';
wait until rising_edge(clk);
digit_in <= x"E0";
dp_in <= "10";
byte_sel <= "01";
wait until rising_edge(clk);
digit_in <= x"D0";
dp_in <= "11";
byte_sel <= "10";
wait until rising_edge(clk);
digit_in <= x"70";
dp_in <= "11";
byte_sel <= "11";
wait until rising_edge(clk);
enable <= '0';
w <= '0';
wait for 1000 ms;
end process;
end Behavioral;
| apache-2.0 | 328c8a1ded44e221db2f1cfd26ee8f4e | 0.529541 | 3.286957 | false | false | false | false |
s-kostyuk/course_project_csch | final_processor/multiplexor.vhd | 1 | 466 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity mx is
generic(
N: integer := 4
);
port(
A: in std_logic_vector(N-1 downto 0);
D: in std_logic_vector(2**N-1 downto 0);
En: in std_logic;
Q: out std_logic
);
end entity;
architecture mx of mx is
signal index: integer := 0;
begin
index <= conv_integer(A);
Q <= d(index) when En = '0'
else '0';
end architecture; | mit | c47e5e6ce859fdbc1a6c62ee3d97cfc4 | 0.628755 | 2.588889 | false | false | false | false |
Rookfighter/fft-spartan6 | fft/delay_vec.vhd | 1 | 1,573 | -- delay_vec.vhd
--
-- Created on: 08 Jun 2017
-- Author: Fabian Meyer
--
-- Component that delays an input vector by
-- a given amount of cycles.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity delay_vec is
generic(RSTDEF: std_logic := '0';
DATALEN: natural := 8;
DELAYLEN: natural := 8);
port(rst: in std_logic; -- reset, RSTDEF active
clk: in std_logic; -- clock, rising edge
swrst: in std_logic; -- software reset, RSTDEF active
en: in std_logic; -- enable, high active
din: in std_logic_vector(DATALEN-1 downto 0); -- data in
dout: out std_logic_vector(DATALEN-1 downto 0)); -- data out
end entity;
architecture behavioral of delay_vec is
-- vector through which signal is chained
type del_dat is array(DELAYLEN-1 downto 0) of std_logic_vector(DATALEN-1 downto 0);
constant ZERODAT: std_logic_vector(DATALEN-1 downto 0) := (others => '0');
signal dvec: del_dat := (others => ZERODAT);
begin
dout <= dvec(DELAYLEN-1);
process(rst, clk)
begin
if rst = RSTDEF then
dvec <= (others => ZERODAT);
elsif rising_edge(clk) then
if swrst = RSTDEF then
dvec <= (others => ZERODAT);
elsif en = '1' then
dvec <= dvec(DELAYLEN-2 downto 0) & din;
end if;
end if;
end process;
end architecture;
| mit | bad7eaa423c64fa70db1ca98ccdcb1e0 | 0.544819 | 3.727488 | false | false | false | false |
Kalycito-open-automation/openPOWERLINK_V2_old_25-06-2014 | hardware/ipcore/common/openmac/src/phyMgmt-rtl-ea.vhd | 2 | 9,376 | -------------------------------------------------------------------------------
--! @file phyMgmt-rtl-ea.vhd
--
--! @brief OpenMAC phy management module
--
--! @details This is the openMAC phy management module to configure the connected
--! phys via SMI (= serial management interface).
-------------------------------------------------------------------------------
--
-- (c) B&R, 2013
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
--! use global library
use work.global.all;
entity phyMgmt is
port (
--! Reset
iRst : in std_logic;
--! Clock
iClk : in std_logic;
--! Address (word addresses)
iAddress : in std_logic_vector(3 downto 1);
--! Select
iSelect : in std_logic;
--! Byteenale (low-active)
inByteenable : in std_logic_vector(1 downto 0);
--! Write (low-active)
inWrite : in std_logic;
--! Writedata
iWritedata : in std_logic_vector(15 downto 0);
--! Readdata
oReaddata : out std_logic_vector(15 downto 0);
--! SMI Clock
oSmiClk : out std_logic;
--! SMI data input
iSmiDataIn : in std_logic;
--! SMI data output
oSmiDataOut : out std_logic;
--! SMI data output enable
oSmiDataOutEnable : out std_logic;
--! Phy reset (low-active)
onPhyReset : out std_logic
);
end entity phyMgmt;
architecture rtl of phyMgmt is
--! This is the shift register to serialize write and read data.
signal shift_reg : std_logic_vector(31 downto 0);
--! This is the generated SMI clock.
signal smiClk : std_logic;
--! This is the clock divider vector to generate smiClk.
signal clkDivider : std_logic_vector(4 downto 0);
--! This alias triggers shifting the shift register.
alias doShift : std_logic is clkDivider(clkDivider'high);
--! This is the bit counter for serializing.
signal bit_cnt : std_logic_vector(2 downto 0);
--! This is the byte counter for serializing.
signal byte_cnt : std_logic_vector(2 downto 0);
--! This flag signalizes activity.
signal runActive : std_logic;
--! This flag signalizes a busy shift register.
signal shiftBusy : std_logic;
--! This signal is used to control the phy reset (low active).
signal nPhyReset : std_logic;
--! This is the internal SMI data output.
signal smiDataOut : std_logic;
--! This is the internal SMI data output enable.
signal smiDataOutEnable : std_logic;
begin
---------------------------------------------------------------------------
-- Assign outputs
---------------------------------------------------------------------------
oSmiClk <= smiClk;
oSmiDataOut <= smiDataOut;
oSmiDataOutEnable <= smiDataOutEnable;
onPhyReset <= nPhyReset;
--! This process assigns the readdata vector.
ASSIGN_READDATA : process (
nPhyReset,
shiftBusy,
shift_reg,
iAddress
)
begin
-- default is zero
oReaddata <= (others => cInactivated);
if iAddress(1) = cInactivated then
oReaddata(7) <= nPhyReset;
oReaddata(0) <= shiftBusy;
else
oReaddata <= shift_reg(15 downto 0);
end if;
end process ASSIGN_READDATA;
--! This process generates the SMI signals and assigns memory mapped writes.
doSMI : process (iRst, iClk)
begin
if iRst = cActivated then
smiClk <= cInactivated;
runActive <= cInactivated;
shiftBusy <= cInactivated;
smiDataOutEnable <= cActivated;
smiDataOut <= cActivated;
nPhyReset <= cnActivated;
bit_cnt <= (others => cInactivated);
byte_cnt <= (others => cInactivated);
shift_reg <= x"0000abcd";
clkDivider <= (others => cInactivated);
elsif rising_edge(iClk) then
if doShift = cActivated then
clkDivider <= std_logic_vector(to_unsigned(8, clkDivider'length) + 1);
smiClk <= not smiClk;
else
clkDivider <= std_logic_vector(unsigned(clkDivider) - 1);
end if;
if (iSelect = cActivated and inWrite = cnActivated and shiftBusy = cInactivated and
iAddress(2) = cActivated and inByteenable(0) = cnActivated) then
nPhyReset <= iWritedata(7);
end if;
if (iSelect = cActivated and inWrite = cnActivated and shiftBusy = cInactivated and
iAddress(2) = cInactivated) then
if iAddress(1) = cInactivated then
if inByteenable(1) = cnActivated then
shift_reg(31 downto 24) <= iWritedata(15 downto 8);
end if;
if inByteenable(0) = cnActivated then
shift_reg(23 downto 16) <= iWritedata(7 downto 0);
shiftBusy <= cActivated;
end if;
else
if inByteenable(1) = cnActivated then
shift_reg(15 downto 8) <= iWritedata(15 downto 8);
end if;
if inByteenable(0) = cnActivated then
shift_reg(7 downto 0) <= iWritedata(7 downto 0);
end if;
end if;
else
if doShift = cActivated and smiClk = cActivated then
if runActive = cInactivated and shiftBusy = cActivated then
runActive <= cActivated;
byte_cnt <= "111";
bit_cnt <= "111";
else
if byte_cnt(2) = cInactivated and shiftBusy = cActivated then
smiDataOut <= shift_reg(31);
shift_reg <= shift_reg(30 downto 0) & iSmiDataIn;
end if;
bit_cnt <= std_logic_vector(unsigned(bit_cnt) - 1);
if bit_cnt = std_logic_vector(to_unsigned(0, bit_cnt'length)) then
byte_cnt <= std_logic_vector(unsigned(byte_cnt) - 1);
if byte_cnt = std_logic_vector(to_unsigned(0, byte_cnt'length)) then
shiftBusy <= cInactivated;
runActive <= cInactivated;
end if;
end if;
if (byte_cnt = std_logic_vector(to_unsigned(2, byte_cnt'length)) and
bit_cnt = std_logic_vector(to_unsigned(1, bit_cnt'length)) and
shift_reg(31) = cInactivated) then
smiDataOutEnable <= cInactivated;
end if;
end if;
if shiftBusy = cInactivated or runActive = cInactivated then
smiDataOut <= cActivated;
smiDataOutEnable <= cActivated;
end if;
end if;
end if;
end if;
end process doSMI;
end rtl; | gpl-2.0 | 815170dff92c02c940d6cc943695124c | 0.522824 | 5.035446 | false | false | false | false |
hoglet67/AtomGodilVideo | src/Top.vhd | 1 | 10,808 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:42:09 02/09/2013
-- Design Name:
-- Module Name: Top - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Top is
port (
-- Standard 6847 signals
--
-- expept DA which is now input only
-- except nRP which re-purposed as a nWR
CLK : in std_logic;
DD : inout std_logic_vector (7 downto 0);
DA : in std_logic_vector (12 downto 0);
CHB : out std_logic;
OA : out std_logic;
OB : out std_logic;
nMS : in std_logic;
CSS : in std_logic;
nHS : out std_logic;
nFS : out std_logic;
nWR : in std_logic; -- Was nRP
AG : in std_logic;
AS : in std_logic;
INV : in std_logic;
INTEXT : in std_logic;
GM : in std_logic_vector (2 downto 0);
Y : out std_logic;
-- 5 bit VGA Output
R : out std_logic_vector (0 downto 0);
G : out std_logic_vector (1 downto 0);
B : out std_logic_vector (0 downto 0);
HSYNC : out std_logic;
VSYNC : out std_logic;
-- 1 bit AUDIO Output
AUDIO : out std_logic;
-- Other GODIL specific pins
clock49 : in std_logic;
nRST : in std_logic;
nBXXX : in std_logic;
-- Jumpers
-- Enables VGA Signals on PL4
nPL4 : in std_logic;
-- Moves SID from 9FE0 to BDC0
nSIDD : in std_logic;
-- Active low version of the SID Select Signal for disabling the external bus buffers
-- nSIDSEL : out std_logic;
-- PS/2 Mouse
PS2_CLK : inout std_logic;
PS2_DATA : inout std_logic;
-- UART
uart_TxD : out std_logic;
uart_RxD : in std_logic;
--LEDs
led8 : out std_logic
);
end Top;
architecture BEHAVIORAL of Top is
-- clock32 is the main clock
signal clock32 : std_logic;
-- clock25 is a full speed VGA clock
signal clock25 : std_logic;
-- clock15 is just used between two DCMs
signal clock15 : std_logic;
-- clock59 is just used between two DCMs
signal clock59 : std_logic;
-- Reset signal (active high)
signal reset : std_logic;
-- Reset signal to 6847 (active high), not currently used
signal reset_vid : std_logic;
-- pipelined versions of the address/data/write signals
signal nWR1 : std_logic;
signal nWR2 : std_logic;
signal nMS1 : std_logic;
signal nMS2 : std_logic;
signal nWRMS1 : std_logic;
signal nWRMS2 : std_logic;
signal nBXXX1 : std_logic;
signal nBXXX2 : std_logic;
signal DA1 : std_logic_vector (12 downto 0);
signal DA2 : std_logic_vector (12 downto 0);
signal DD1 : std_logic_vector (7 downto 0);
signal DD2 : std_logic_vector (7 downto 0);
signal DD3 : std_logic_vector (7 downto 0);
signal ram_we : std_logic;
signal addr : std_logic_vector (12 downto 0);
signal din : std_logic_vector (7 downto 0);
-- Dout back to the Atom, that is either VRAM or SID
signal dout : std_logic_vector (7 downto 0);
-- SID sigmals
signal sid_cs : std_logic;
signal sid_we : std_logic;
signal sid_audio : std_logic;
-- UART sigmals
signal uart_cs : std_logic;
signal uart_we : std_logic;
-- Atom extension register signals
signal reg_cs : std_logic;
signal reg_we : std_logic;
signal final_red : std_logic;
signal final_green1 : std_logic;
signal final_green0 : std_logic;
signal final_blue : std_logic;
signal final_vsync : std_logic;
signal final_hsync : std_logic;
signal final_char_a : std_logic_vector (10 downto 0);
signal locked1 : std_logic;
signal locked2 : std_logic;
signal locked3 : std_logic;
signal locked4 : std_logic;
begin
reset <= not nRST;
reset_vid <= '0';
-- Currently set at 49.152 * (31/26) * (3/7) = 25.1161318637MHz
Inst_DCM1 : entity work.DCM1
port map (
CLKIN_IN => clock49,
RST => '0',
CLK0_OUT => clock59,
CLK0_OUT1 => open,
CLK2X_OUT => open,
LOCKED => locked1
);
Inst_DCM2 : entity work.DCM2
port map (
CLKIN_IN => clock59,
RST => not locked1,
CLK0_OUT => clock25,
CLK0_OUT1 => open,
CLK2X_OUT => open,
LOCKED => locked2
);
Inst_DCM3 : entity work.DCMSID0
port map (
CLKIN_IN => clock49,
RST => '0',
CLK0_OUT => clock15,
CLK0_OUT1 => open,
CLK2X_OUT => open,
LOCKED => locked3
);
Inst_DCM4 : entity work.DCMSID1
port map (
CLKIN_IN => clock15,
RST => not locked3,
CLK0_OUT => clock32,
CLK0_OUT1 => open,
CLK2X_OUT => open,
LOCKED => locked4
);
led8 <= not (locked1 and locked2 and locked3 and locked4);
Inst_AtomGodilVideo : entity work.AtomGodilVideo
generic map (
CImplGraphicsExt => true,
CImplSoftChar => true,
CImplSID => true,
CImplVGA80x40 => true,
CImplHWScrolling => true,
CImplMouse => true,
CImplUart => true,
CImplDoubleVideo => true,
MainClockSpeed => 32000000,
DefaultBaud => 115200
)
port map (
clock_vga => clock25,
clock_main => clock32,
clock_sid_32Mhz => clock32,
clock_sid_dac => clock49,
reset => reset,
reset_vid => reset_vid,
din => din,
dout => dout,
addr => addr,
CSS => CSS,
AG => AG,
GM => GM,
nFS => nFS,
ram_we => ram_we,
reg_cs => reg_cs,
reg_we => reg_we,
sid_cs => sid_cs,
sid_we => sid_we,
sid_audio => sid_audio,
sid_audio_d => open,
PS2_CLK => PS2_CLK,
PS2_DATA => PS2_DATA,
uart_cs => uart_cs,
uart_we => uart_we,
uart_RxD => uart_RxD,
uart_TxD => uart_TxD,
uart_escape => open,
uart_break => open,
final_red => final_red,
final_green1 => final_green1,
final_green0 => final_green0,
final_blue => final_blue,
final_vsync => final_vsync,
final_hsync => final_hsync,
charSet => '0'
);
-- Pipelined version of address/data/write signals
process (clock32)
begin
if rising_edge(clock32) then
nBXXX2 <= nBXXX1;
nBXXX1 <= nBXXX;
nMS2 <= nMS1;
nMS1 <= nMS;
nWRMS2 <= nWRMS1;
nWRMS1 <= nWR or nMS;
nWR2 <= nWR1;
nWR1 <= nWR;
DD3 <= DD2;
DD2 <= DD1;
DD1 <= DD;
DA2 <= DA1;
DA1 <= DA;
end if;
end process;
-- Signals driving the VRAM
-- Write just before the rising edge of nWR
ram_we <= '1' when (nWRMS1 = '1' and nWRMS2 = '0' and nBXXX2 = '1') else '0';
din <= DD3;
addr <= DA2;
-- Signals driving the internal registers
-- When nSIDD=0 the registers are mapped to BDE0-BDFF
-- When nSIDD=1 the registers are mapped to 9FE0-9FFF
reg_cs <= '1' when (nSIDD = '1' and nMS2 = '0' and DA2(12 downto 5) = "11111111") or
(nSIDD = '0' and nBXXX2 = '0' and DA2(11 downto 5) = "1101111")
else '0';
reg_we <= '1' when (nSIDD = '1' and nWRMS1 = '1' and nWRMS2 = '0') or
(nSIDD = '0' and nWR1 = '1' and nWR2 = '0')
else '0';
-- Signals driving the SID
-- When nSIDD=0 the SID is mapped to BDC0-BDDF
-- When nSIDD=1 the SID is mapped to 9FC0-9FDF
sid_cs <= '1' when (nSIDD = '1' and nMS2 = '0' and DA2(12 downto 5) = "11111110") or
(nSIDD = '0' and nBXXX2 = '0' and DA2(11 downto 5) = "1101110")
else '0';
sid_we <= '1' when (nSIDD = '1' and nWRMS1 = '1' and nWRMS2 = '0') or
(nSIDD = '0' and nWR1 = '1' and nWR2 = '0')
else '0';
-- Signals driving the UART
-- When nSIDD=0 the UART is mapped to BDB0-BDBF
-- When nSIDD=1 the UART is mapped to 9FB0-9FBF
uart_cs <= '1' when (nSIDD = '1' and nMS2 = '0' and DA2(12 downto 4) = "111111011") or
(nSIDD = '0' and nBXXX2 = '0' and DA2(11 downto 4) = "11011011")
else '0';
uart_we <= '1' when (nSIDD = '1' and nWRMS1 = '1' and nWRMS2 = '0') or
(nSIDD = '0' and nWR1 = '1' and nWR2 = '0')
else '0';
AUDIO <= sid_audio;
-- Output the SID Select Signal so it can be used to disable the bus buffers
-- TODO: this looks incorrect
-- nSIDSEL <= not sid_cs;
-- Tri-state data back to the Atom
DD <= dout when (nMS = '0' and nWR = '1') else (others => 'Z');
-- 1/1/1 Bit RGB Video to PL4 Connectors
OA <= final_red when nPL4 = '0' else '0';
CHB <= final_green1 when nPL4 = '0' else '0';
OB <= final_blue when nPL4 = '0' else '0';
nHS <= final_hsync when nPL4 = '0' else '0';
Y <= final_vsync when nPL4 = '0' else '0';
-- 1/2/1 Bit RGB Video to GODIL Test Connector
R(0) <= final_red;
G(1) <= final_green1;
G(0) <= final_green0;
B(0) <= final_blue;
VSYNC <= final_vsync;
HSYNC <= final_hsync;
end BEHAVIORAL;
| apache-2.0 | ad019918c42d5823a5609005b721869e | 0.495559 | 3.588313 | false | false | false | false |
sergev/vak-opensource | hardware/vhd2vl/examples/generate.vhd | 1 | 1,350 | LIBRARY IEEE;
USE IEEE.std_logic_1164.all, IEEE.std_logic_arith.all, IEEE.std_logic_unsigned.all;
entity gen is generic(
bus_width : integer := 15;
TOP_GP2 : integer:= 0
);
port(
sysclk, reset, wrb : in std_logic;
din : in std_logic_vector(bus_width downto 0);
rdout: out std_logic_vector(bus_width downto 0)
);
end gen;
architecture rtl of gen is
component wbit1 -- register bit default 1
port(
clk : in std_logic;
wrb : in std_logic;
reset : in std_logic;
enb : in std_logic;
din : in std_logic;
dout : out std_logic);
end component;
signal regSelect : std_logic_vector(bus_width * 2 downto 0);
begin
-----------------------------------------------------
-- Reg : GP 2
-- Active : 32
-- Type : RW
-----------------------------------------------------
reg_gp2 : for bitnum in 0 to bus_width generate
wbit1_inst : wbit1
PORT MAP(
clk => sysclk,
wrb => wrb,
reset => reset,
enb => regSelect(TOP_GP2),
din => din(bitnum),
dout => rdout(bitnum)
);
end generate;
process(sysclk) begin
if sysclk'event and sysclk = '1' then
regSelect(1) <= '1';
end if;
end process;
end rtl;
| apache-2.0 | ab671bc4868398acb23a7ea98df5539b | 0.494815 | 3.678474 | false | false | false | false |
Wynjones1/VHDL-Build | example/blinky/top.vhd | 1 | 1,118 | library IEEE;
use IEEE.numeric_std.all;
use IEEE.std_logic_1164.all;
entity top is
port( clk : in std_logic;
reset : in std_logic;
led : out std_logic);
end top;
architecture rtl of top is
component clk_gen is
generic( CLOCK_SPEED : integer := 50_000_000;
REQUIRED_HZ : integer := 1);
port( clk : in std_logic;
reset : in std_logic;
clk_out : out std_logic);
end component;
constant CLK_HZ : integer := 50_000_000;
signal hz_clk : std_logic;
signal led_s : std_logic;
begin
gen_1hz_clk : clk_gen
generic map (REQUIRED_HZ => CLK_HZ / 2)
port map (clk, reset, hz_clk);
combinatoral:
process(led_s)
begin
led <= led_s;
end process;
sequential:
process(hz_clk, reset)
begin
if reset = '1' then
led_s <= '0';
elsif rising_edge(hz_clk) then
if led_s = '1' then
led_s <= '0';
else
led_s <= '1';
end if;
end if;
end process;
end rtl;
| mit | 9c77d464952b0aab8b4e7a24e9ffd43b | 0.506261 | 3.482866 | false | false | false | false |
rccoder/CU-MicroProgram | code/CU_tb.vhd | 1 | 2,553 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:47:05 06/16/2015
-- Design Name:
-- Module Name: C:/project10/CU_tb.vhd
-- Project Name: project10
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: CU
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY CU_tb IS
END CU_tb;
ARCHITECTURE behavior OF CU_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT CU
PORT(
clk : IN std_logic;
op_code : IN std_logic_vector(4 downto 0);
ctrl_signal : OUT std_logic_vector(17 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal op_code : std_logic_vector(4 downto 0) := (others => '0');
--Outputs
signal ctrl_signal : std_logic_vector(17 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: CU PORT MAP (
clk => clk,
op_code => op_code,
ctrl_signal => ctrl_signal
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
op_code<="00000";
wait for 40 ns;
op_code<="00010";
wait for 40 ns;
op_code<="00011";
wait for 40 ns;
op_code<="00100";
wait for 40 ns;
op_code<="00101";
wait for 40 ns;
op_code<="00110";
wait for 40 ns;
op_code<="00111";
wait for 60 ns;
op_code<="01001";
wait for 60 ns;
op_code<="01011";
wait for 60 ns;
op_code<="01101";
wait for 40 ns;
op_code<="01111";
wait for 40 ns;
op_code<="00000";
-- insert stimulus here
wait;
end process;
END;
| mit | 6957442005ee412b06f8ad41f65ec907 | 0.585977 | 3.605932 | false | true | false | false |
hoglet67/AtomGodilVideo | src/pointer/Pointer.vhd | 2 | 4,735 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity Pointer is
port (
CLK : in std_logic;
PO : in std_logic;
PS : in std_logic_vector (4 downto 0);
X : in std_logic_vector (7 downto 0);
Y : in std_logic_vector (7 downto 0);
ADDR : in std_logic_vector (12 downto 0);
DIN : in std_logic_vector (7 downto 0);
DOUT : out std_logic_vector (7 downto 0)
);
end Pointer;
architecture Behavioral of Pointer is
signal xrel : std_logic_vector (5 downto 0);
signal yrel : std_logic_vector (7 downto 0);
signal addrb : std_logic_vector (7 downto 0);
signal black : std_logic_vector (7 downto 0);
signal white : std_logic_vector (7 downto 0);
signal sblack : std_logic_vector (15 downto 0);
signal swhite : std_logic_vector (15 downto 0);
COMPONENT PointerRamBlack
PORT(
clka : IN std_logic;
wea : IN std_logic;
addra : IN std_logic_vector(7 downto 0);
dina : IN std_logic_vector(7 downto 0);
clkb : IN std_logic;
web : IN std_logic;
addrb : IN std_logic_vector(7 downto 0);
dinb : IN std_logic_vector(7 downto 0);
douta : OUT std_logic_vector(7 downto 0);
doutb : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
COMPONENT PointerRamWhite
PORT(
clka : IN std_logic;
wea : IN std_logic;
addra : IN std_logic_vector(7 downto 0);
dina : IN std_logic_vector(7 downto 0);
clkb : IN std_logic;
web : IN std_logic;
addrb : IN std_logic_vector(7 downto 0);
dinb : IN std_logic_vector(7 downto 0);
douta : OUT std_logic_vector(7 downto 0);
doutb : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
begin
xrel <= ('1' & ADDR(4 downto 0)) - ('0' & X(7 downto 3));
yrel <= ADDR(12 downto 5) - Y;
addrb <= PS & yrel(2 downto 0);
Inst_PointerRamBlack: PointerRamBlack PORT MAP(
clka => CLK,
wea => '0',
addra => (others => '0'),
dina => (others => '0'),
douta => open,
clkb => CLK,
web => '0',
addrb => addrb,
dinb => (others => '0'),
doutb => black
);
Inst_PointerRamWhite: PointerRamWhite PORT MAP(
clka => CLK,
wea => '0',
addra => (others => '0'),
dina => (others => '0'),
douta => open,
clkb => CLK,
web => '0',
addrb => addrb,
dinb => (others => '0'),
doutb => white
);
-- process(yrel)
-- begin
-- case yrel(2 downto 0) is
-- when "000" =>
-- black <= "11111111";
-- white <= "00000000";
-- when "001" =>
-- black <= "10000010";
-- white <= "01111100";
-- when "010" =>
-- black <= "10000100";
-- white <= "01111000";
-- when "011" =>
-- black <= "10000100";
-- white <= "01111000";
-- when "100" =>
-- black <= "10000010";
-- white <= "01111100";
-- when "101" =>
-- black <= "10110001";
-- white <= "01001110";
-- when "110" =>
-- black <= "11001010";
-- white <= "00000100";
-- when others =>
-- black <= "10000100";
-- white <= "00000000";
-- end case;
-- end process;
process(X, white, black)
begin
case X(2 downto 0) is
when "000" =>
swhite <= white & "00000000";
sblack <= black & "00000000";
when "001" =>
swhite <= "0" & white & "0000000";
sblack <= "0" & black & "0000000";
when "010" =>
swhite <= "00" & white & "000000";
sblack <= "00" & black & "000000";
when "011" =>
swhite <= "000" & white & "00000";
sblack <= "000" & black & "00000";
when "100" =>
swhite <= "0000" & white & "0000";
sblack <= "0000" & black & "0000";
when "101" =>
swhite <= "00000" & white & "000";
sblack <= "00000" & black & "000";
when "110" =>
swhite <= "000000" & white & "00";
sblack <= "000000" & black & "00";
when others =>
swhite <= "0000000" & white & "0";
sblack <= "0000000" & black & "0";
end case;
end process;
dout <= (din and (sblack(15 downto 8) xor "11111111")) or swhite(15 downto 8) when PO = '1' and xrel = 32 and yrel < 8 else
(din and (sblack(7 downto 0) xor "11111111")) or swhite(7 downto 0) when PO = '1' and xrel = 33 and yrel < 8 else
din;
end Behavioral;
| apache-2.0 | 907b6209a57dfe38c7b8bc57621d9f30 | 0.491024 | 3.358156 | false | false | false | false |
Koheron/zynq-sdk | fpga/cores/vhdl_counter_v1_0/vhdl_counter.vhd | 2 | 685 |
-- from http://www.asic-world.com/code/vhdl/counter.vhd
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity vhdl_counter is
port(
clk: in std_logic;
reset: in std_logic;
enable: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end vhdl_counter;
architecture behav of vhdl_counter is
signal pre_count: std_logic_vector(3 downto 0);
begin
process(clk, enable, reset)
begin
if reset = '1' then
pre_count <= "0000";
elsif (clk='1' and clk'event) then
if enable = '1' then
pre_count <= pre_count + "1";
end if;
end if;
end process;
count <= pre_count;
end behav; | mit | 4b9915d8e1da0c62ff364b8e4152c52c | 0.626277 | 3.127854 | false | false | false | false |
bangonkali/quartus-sockit | soc_system/synthesis/submodules/alt_vipvfr131_common_pulling_width_adapter.vhd | 2 | 5,362 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use work.alt_vipvfr131_common_package.all;
entity alt_vipvfr131_common_pulling_width_adapter is
generic (
-- all cusp function units have these
NAME : string := "";
OPTIMIZED : integer := OPTIMIZED_ON;
FAMILY : integer := FAMILY_STRATIX;
-- configuring the input and output widths
IN_WIDTH : integer := 16;
OUT_WIDTH : integer := 16
);
port (
-- cusp system clock, reset
clock : in std_logic;
reset : in std_logic;
-- interface to cusp
ena : in std_logic := '1';
-- input side
input_data : in std_logic_vector(IN_WIDTH - 1 downto 0) := (others => '0');
need_input : out std_logic;
-- output port
output_data : out std_logic_vector(OUT_WIDTH - 1 downto 0) := (others => '0');
pull : in std_logic;
pull_en : in std_logic;
discard : in std_logic;
discard_en : in std_logic
);
end entity;
architecture rtl of alt_vipvfr131_common_pulling_width_adapter is
-- the number of output words which will fit (wholly) into an input word
constant N : integer := IN_WIDTH / OUT_WIDTH;
-- enough buffers to store N output words
type buffers_type is array(integer range <>) of std_logic_vector(OUT_WIDTH - 1 downto 0);
signal buffers : buffers_type(N - 1 downto 0);
-- a counter counts how many output words we can serve without pulling from the input
signal outputs_waiting : std_logic_vector(N - 1 downto 0);
signal perform_pull : std_logic;
signal perform_pull_delay0 : std_logic;
signal perform_pull_delay1 : std_logic;
signal perform_discard : std_logic;
signal perform_discard_delay0 : std_logic;
signal perform_discard_delay1 : std_logic;
signal outputs_waiting_delay0 : std_logic;
signal outputs_waiting_delay1 : std_logic;
begin
-- check validity of inputs
assert OUT_WIDTH <= IN_WIDTH
report "Currently only narrowing output adapters are supported"
severity ERROR;
-- always output buffer zero
output_data <= buffers(0);
-- input_en is derived combinationally, but only very simply
need_input <= pull and pull_en and outputs_waiting(0);
perform_pull <= pull and pull_en;
perform_discard <= discard and discard_en;
-- every time pull is triggered the counter rotates round and:
-- if there are no words stored, input is pulled and captured
-- if there are words stored, the stored words are shifted
-- either way there should be a new word in buffers(0) on the next cycle
-- discard en just causes any outputs waiting to be discarded
respond_triggers : process (clock, reset)
begin
if reset = '1' then
buffers <= (others => (others => '0'));
outputs_waiting(0) <= '1';
outputs_waiting(N - 1 downto 1) <= (others => '0');
perform_pull_delay0 <= '0';
perform_pull_delay1 <= '0';
perform_discard_delay0 <= '0';
perform_discard_delay1 <= '0';
outputs_waiting_delay0 <= '0';
outputs_waiting_delay1 <= '0';
elsif clock'EVENT and clock = '1' then
if ena = '1' then
if perform_pull = '1' then
-- either way, rotate outputs waiting around to decrease the number of
-- outputs waiting, or replace 0 with MAX
outputs_waiting <= outputs_waiting(0) & outputs_waiting(N - 1 downto 1);
elsif perform_discard = '1' then
-- discard causes what is effectively a reset
outputs_waiting(0) <= '1';
outputs_waiting(N - 1 downto 1) <= (others => '0');
end if;
-- delay the control signals by the latency of the read (2 cycles)
perform_pull_delay0 <= perform_pull;
perform_pull_delay1 <= perform_pull_delay0;
perform_discard_delay0 <= perform_discard;
perform_discard_delay1 <= perform_discard_delay0;
outputs_waiting_delay0 <= outputs_waiting(0);
outputs_waiting_delay1 <= outputs_waiting_delay0;
if perform_pull_delay1 = '1' then
if outputs_waiting_delay1 = '1' then
-- currently no outputs waiting, so this output request will
-- have to be serviced by passing a request for a whole new
-- input word to the input port
-- driving need_input high is dealt with combinationally, so
-- all that needs to be done here is capture the resulting
-- output
-- THE ASSUMPTION IS THAT WHATEVER IS DRIVING THE INPUT HAS
-- A TRIGGER TO DATA DELAY OF ZERO
for i in 0 to N - 1 loop
buffers(i) <= input_data((i + 1) * OUT_WIDTH - 1 downto i * OUT_WIDTH);
end loop;
else
-- currently have outputs waiting, so just shift the buffers
-- around to prepare output for the next clock cycle
for i in 0 to N - 2 loop
buffers(i) <= buffers(i + 1);
end loop;
end if;
elsif perform_discard_delay1 = '1' then
-- discard causes what is effectively a reset
buffers <= (others => (others => '0'));
end if;
end if;
end if;
end process;
end architecture rtl;
| mit | f3506383de8cc9a3e43464c2e33d9975 | 0.607423 | 3.808239 | false | false | false | false |
FinnK/lems2hdl | work/N3_pointCellCondBased/ISIM_output/ParamPow.vhdl | 2 | 2,117 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- For Modelsim
--use ieee.fixed_pkg.all;
--use ieee.fixed_float_types.ALL;
-- For ISE
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use ieee_proposed.fixed_float_types.ALL;
use IEEE.numeric_std.all;
entity ParamPow is
generic(
BIT_TOP : integer := 20;
BIT_BOTTOM : integer := -20);
port(
clk : In Std_logic;
init_model : in STD_LOGIC; --signal to all components to go into their init state
Start : In Std_logic;
Done : Out Std_logic;
A : In sfixed(BIT_TOP downto BIT_BOTTOM);
X : In sfixed(BIT_TOP downto BIT_BOTTOM);
Output : Out sfixed(BIT_TOP downto BIT_BOTTOM)
);
end ParamPow;
architecture RTL of ParamPow is
signal output_internal : sfixed(BIT_TOP downto BIT_BOTTOM);
signal output_internal_next : sfixed(BIT_TOP downto BIT_BOTTOM);
signal count : sfixed(BIT_TOP downto BIT_BOTTOM);
signal count_next : sfixed(BIT_TOP downto BIT_BOTTOM);
signal done_next : std_logic;
begin
process(A,start,init_model,count,X,output_internal,init_model)
variable Sel : integer;
begin
output_internal_next <= output_internal;
count_next <= count;
done_next <= '0';
if init_model = '1' then
output_internal_next <= to_sfixed(0,BIT_TOP, BIT_BOTTOM);
count_next <= to_sfixed(1,BIT_TOP, BIT_BOTTOM);
done_next <= '1';
else
if start = '1' then
output_internal_next <= A;
count_next <= to_sfixed(1,BIT_TOP, BIT_BOTTOM);
done_next <= '0';
else
if To_slv ( resize (count - X ,BIT_TOP, BIT_BOTTOM))(BIT_TOP-BIT_BOTTOM) = '1' then
count_next <= resize (count + to_sfixed(1,1,0) ,BIT_TOP, BIT_BOTTOM);
output_internal_next <= resize (output_internal * A,BIT_TOP, BIT_BOTTOM);
done_next <= '0';
else
output_internal_next <= output_internal;
count_next <= count;
done_next <= '1';
end if;
end if;
end if;
end process;
process(clk)
variable Sel : integer;
begin
if clk'event and clk = '1' then
output_internal <= output_internal_next;
count <= count_next;
Done <= done_next;
end if;
end process;
Output <= output_internal;
end RTL;
| lgpl-3.0 | 88c1ff734a222d829c6cd216227022e8 | 0.663675 | 2.868564 | false | false | false | false |
JuanMarcosRamirez/WeightedMedianDisenoLogico | misc/FPGA/window_3x3_x.vhd | 3 | 12,483 | --------------------------------------------------------------------------
-- Autor: Jorge Márquez
-- Archivo adaptado para la generación de ventanas de 3x3 píxeles para
-- imágenes de tamaño 512x512. El funcionamiento que se expone con detalle
-- en el capítulo 2 del informe.
--
-- Este código se encuentra también en la sección de
-- Apéndices del informe de trabajo de grado PROCESAMIENTO DE IMÁGENES DE
-- ANGIOGRAFÍA BIPLANA USANDO UNA TARJETA DE DESARROLLO SPARTAN-3E
--
-- UNIVERSIDAD DE LOS ANDES
-- FACULTAD DE INGENIERÍA
-- ESCUELA DE INGENIERÍA ELÉCTRICA
--
-- Mérida, Septiembre, 2008
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity window_3x3 is
generic (
vwidth: integer:=8
);
port (
Clk : in std_logic;
RSTn : in std_logic;
D : in std_logic_vector(vwidth-1 downto 0);
w11 : out std_logic_vector(vwidth -1 downto 0);
w12 : out std_logic_vector(vwidth -1 downto 0);
w13 : out std_logic_vector(vwidth -1 downto 0);
w21 : out std_logic_vector(vwidth -1 downto 0);
w22 : out std_logic_vector(vwidth -1 downto 0);
w23 : out std_logic_vector(vwidth -1 downto 0);
w31 : out std_logic_vector(vwidth -1 downto 0);
w32 : out std_logic_vector(vwidth -1 downto 0);
w33 : out std_logic_vector(vwidth -1 downto 0);
DV : out std_logic:='0'
);
end window_3x3;
architecture window_3x3 of window_3x3 is
component fifo_512x8x
port (
din : IN std_logic_VECTOR(7 downto 0);
wr_en : IN std_logic;
wr_clk : IN std_logic;
rd_en : IN std_logic;
rd_clk : IN std_logic;
rst : IN std_logic;
dout : OUT std_logic_VECTOR(7 downto 0);
full : OUT std_logic;
empty : OUT std_logic;
wr_data_count: OUT std_logic_VECTOR(8 downto 0));
end component;
signal a00 : std_logic_vector(vwidth-1 downto 0);
signal a11 : std_logic_vector(vwidth-1 downto 0);
signal a12 : std_logic_vector(vwidth-1 downto 0);
signal a13 : std_logic_vector(vwidth-1 downto 0);
signal a21 : std_logic_vector(vwidth-1 downto 0);
signal a22 : std_logic_vector(vwidth-1 downto 0);
signal a23 : std_logic_vector(vwidth-1 downto 0);
signal a31 : std_logic_vector(vwidth-1 downto 0);
signal a32 : std_logic_vector(vwidth-1 downto 0);
signal a33 : std_logic_vector(vwidth-1 downto 0);
--fifoa signals
signal clear : std_logic;
signal wrreqa : std_logic:='1';
signal rdreqa : std_logic:='0';
signal ofulla : std_logic;
signal oemptya : std_logic;
signal ofifoa : std_logic_vector(vwidth-1 downto 0);
signal ousedwa : std_logic_VECTOR(8 downto 0);
--fifob signals
signal wrreqb : std_logic:='0';
signal rdreqb : std_logic:='0';
signal ofullb : std_logic;
signal oemptyb : std_logic;
signal ofifob : std_logic_vector(vwidth-1 downto 0);
signal ousedwb : std_logic_VECTOR(8 downto 0);
signal dwrreqb: std_logic:='0';
-- signals for DV coordination
signal dddddddDV: std_logic :='0';
signal ddddddDV: std_logic:='0';
signal dddddDV: std_logic:='0';
signal ddddDV: std_logic:='0';
signal dddDV: std_logic:='0';
signal ddDV: std_logic:='0';
signal dDV: std_logic:='0';
signal ousedwa_temp: integer:=0;
signal ousedwb_temp: integer:=0;
begin
fifoa: fifo_512x8x
port map ( -- port map fifo a
din => a13, -- port map fifo a
wr_en => wrreqa, -- port map fifo a
wr_clk => Clk, -- port map fifo a
rd_en => rdreqa, -- port map fifo a
rd_clk => Clk, -- port map fifo a
rst => clear, -- port map fifo a
dout => ofifoa, -- port map fifo a
full => ofulla, -- port map fifo a
empty => oemptya, -- port map fifo a
wr_data_count => ousedwa -- port map fifo a
); -- port map fifo a
fifob: fifo_512x8x
port map ( -- port map fifo b
din => a23, -- port map fifo b
wr_en => wrreqb, -- port map fifo b
wr_clk => Clk, -- port map fifo b
rd_en => rdreqb, -- port map fifo b
rd_clk => Clk, -- port map fifo b
rst => clear, -- port map fifo b
dout => ofifob, -- port map fifo b
full => ofullb, -- port map fifo b
empty => oemptyb, -- port map fifo b
wr_data_count => ousedwb -- port map fifo b
); -- port map fifo b
clear <= not(RSTn);
clock: process(Clk,RSTn)
begin --clock
if RSTn = '0' then --clock
a11 <= (others=>'0'); --clock
a12 <= (others=>'0'); --clock
a13 <= (others=>'0'); --clock
a21 <= (others=>'0'); --clock
a22 <= (others=>'0'); --clock
a23 <= (others=>'0'); --clock
a31 <= (others=>'0'); --clock
a32 <= (others=>'0'); --clock
a33 <= (others=>'0'); --clock
w11 <= (others=>'0'); --clock
w12 <= (others=>'0'); --clock
w13 <= (others=>'0'); --clock
w21 <= (others=>'0'); --clock
w22 <= (others=>'0'); --clock
w23 <= (others=>'0'); --clock
w31 <= (others=>'0'); --clock
w32 <= (others=>'0'); --clock
w33 <= (others=>'0'); --clock
wrreqa <= '0'; --clock
wrreqb <= '0'; --clock
-- dddddddDV <= '0'; -- 7 ds --clock
ddddddDV <= '0'; --clock
dddddDV <= '0'; --clock
ddddDV <= '0'; --clock
dddDV <= '0'; --clock
ddDV <= '0'; --clock
dDV <= '0'; --clock
DV <= '0'; --clock
elsif rising_edge(Clk) then --clock
--clock
a00 <= D; --clock
--clock
a11 <= a00; --clock
w11 <= a00; --clock
--clock
--clock
w12 <= a11; --clock
a12 <= a11; --clock
--clock
w13 <= a12; --clock
a13 <= a12; --clock
--clock
--clock
w21 <= ofifoa; --clock
a21 <= ofifoa; --clock
--clock
w22 <= a21; --clock
a22 <= a21; --clock
--clock
w23 <= a22; --clock
a23 <= a22; --clock
--clock
w31 <= ofifob; --clock
a31 <= ofifob; --clock
--clock
w32 <= a31; --clock
a32 <= a31; --clock
--clock
w33 <= a32; --clock
a33 <= a32; --clock
--clock
wrreqa <= '1'; --clock
wrreqb <= dwrreqb; --clock
--clock
ddddddDV <= dddddddDV; --04/06/08 --clock
dddddDV <= ddddddDV; --clock
ddddDV <= dddddDV; --clock
dddDV <= ddddDV; --clock
ddDV <= dddDV; --clock
dDV <= ddDV; --clock
DV <= dDV; --clock
end if; --clock
end process; --clock
req: process(Clk) -- req
begin -- req
if rising_edge(Clk) then -- req
if ousedwa = "111111010" then -- req
rdreqa <= '1'; -- req
dwrreqb <= '1'; -- req
end if; -- req
if ousedwb = "111111010" then -- req
rdreqb <= '1'; -- req
dddddddDV <= '1'; --04/06/08 ds -- req
end if; -- req
end if; -- req
end process; -- req
end window_3x3;
| gpl-3.0 | 3f064be78b2bc64077ffa73a60d06bec | 0.303933 | 4.943762 | false | false | false | false |
viccuad/fpga-lunarLanderGame | lunarLander.vhd | 1 | 60,653 |
library IEEE;
library UNISIM;
use UNISIM.vcomponents.all;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- juego original de atari lunar lander en: http://my.ign.com/atari/lunar-lander
entity lunarLander is
port (
ps2Clk: IN std_logic;
ps2Data: IN std_logic;
clk: IN std_logic;
reset: IN std_logic; --reset activo a baja!
modoSiloIN: IN std_logic;
hSync: OUT std_logic;
Vsync: OUT std_logic;
segs: OUT std_logic_vector (6 downto 0);
R: OUT std_logic_vector (2 downto 0); -- alconversor D/A
G: OUT std_logic_vector (2 downto 0); -- alconversor D/A
B: OUT std_logic_vector (2 downto 0) -- alconversor D/A
);
end lunar-lander;
architecture Behavioral of lunarLander is
component ps2KeyboardInterface
port ( clk: IN std_logic;
rst: IN std_logic;
ps2Clk: IN std_logic;
ps2Data: IN std_logic;
data: OUT std_logic_vector (7 DOWNTO 0);
newData: OUT std_logic;
newDataAck: IN std_logic
);
end component;
--seniales estados
type fsmEstados is (pulsadas, despulsadas);
signal estadoTeclado: fsmEstados;
type fsmEstados2 is (iniciando, jugando, parado, reseteo);
signal estadoJuego: fsmEstados2;
type fsmEstados3 is (generaAleatOBase, guardaPixelVer, pintarCol);
signal estadoGenMundo: fsmEstados3;
--señales PS2
signal newData, newDataAck: std_logic;
signal scancode: std_logic_vector (7 downto 0);
--señales VGA
signal senialHSync, senialVSync: std_logic;
signal finPixelCont: std_logic;
signal cuentaPixelCont: std_logic_vector (10 downto 0);
signal cuentaLineCont: std_logic_vector (9 downto 0);
signal comp1, comp2, comp3, comp4, comp5, comp6: std_logic;
signal Rnave,Rmundo,Rbase,R_ml,R_l,R_r,R_mr,Rvel,Rfuego,Rfuel,Rboom: std_logic_vector (2 downto 0);
signal Gnave,Gmundo,Gbase,G_ml,G_l,G_r,G_mr,Gvel,Gfuego,Gfuel,Gboom: std_logic_vector (2 downto 0);
signal Bnave,Bmundo,Bbase,B_ml,B_l,B_r,B_mr,Bvel,Bfuego,Bfuel,Bboom: std_logic_vector (2 downto 0);
--seniales registro lsfr
signal D,Q: std_logic_vector (14 downto 0);
signal puertaAND: std_logic_vector (0 downto 0);
--señales mundo
signal pixelMundoHor, pixelNaveHor: std_logic_vector (7 downto 0); --153 pixeles (10011001)
signal pixelMundoVer, pixelNaveVer,pixelAnteriorVer: std_logic_vector (6 downto 0); --102 pixeles
signal regBaseDificil1,regBaseDificil2,regBaseFacil: std_logic_vector (6 downto 0);
signal contMod3: std_logic_vector(1 downto 0);
signal clContMod3,generarBases: std_logic;
--señales nave
signal haAterrizado,BiestableHaAterrizado: std_logic;
signal posNave: std_logic_vector (14 downto 0); --pixelNaveHor catenado pixelNaveVer
signal cuentaVelVertical, cuentaVelHorizontal: std_logic_vector (6 downto 0);
signal muyLentoVertical,lentoVertical,rapidoVertical,muyRapidoVertical: std_logic;
signal muyLentoHorizontal,lentoHorizontal,rapidoHorizontal,muyRapidoHorizontal: std_logic;
signal movNave: std_logic_vector (2 downto 0); -- 000 = no se mueve , 001 = arriba , 010 = abajo , 011 = izquierda, 100 = derecha
signal moverNave: std_logic;
--señales juego
signal teclaSPC,teclaW,teclaS,teclaA,teclaD: std_logic;
signal clTeclaSPC,clTeclaW,clTeclaS,clTeclaA,clTeclaD: std_logic;
signal ldTeclaSPC,ldTeclaW,ldTeclaS,ldTeclaA,ldTeclaD: std_logic;
signal cuentaMuyRapido: STD_LOGIC_VECTOR(20 downto 0);
signal cuentaRapido: STD_LOGIC_VECTOR(21 downto 0);
signal cuentaLento: STD_LOGIC_VECTOR(22 downto 0);
signal cuentaMuyLento: STD_LOGIC_VECTOR(23 downto 0);
signal cuentaGasolina: STD_LOGIC_VECTOR(30 downto 0);
signal finCuentaMuyRapido,finCuentaRapido,finCuentaLento,finCuentaMuyLento,finCuentaGasolina: STD_LOGIC;
signal cuentaContBarrido: std_logic_vector(14 downto 0);
signal finCuentaBarrido,enableContBarrido,hayColision: std_logic;
signal finGenerarMundo: std_logic;
signal ModoSilo: std_logic;
--seniales memorias
signal DOAmundoMenosSig,DOAmundoMasSig,DOBmundoMenosSig,DOBmundoMasSig: std_logic_vector(0 downto 0);
signal selPixelPantalla: std_logic_vector (14 downto 0); -- pixeles logicos hor (120) concatenado con pixeles logicos ver (153): cuentaPixelCont(10 downto 3)++cuentaLineCont(8 downto 2)
signal selPixelMundo: std_logic_vector (14 downto 0); --pixelMundoHor catenado pixelMundoVer
signal WEBmenosSig,WEBmasSig,senialWEB,senialWEA: std_logic;
signal DIB,DOBmundo,DOAmundo: std_logic_vector(0 downto 0);
signal senialADDRA: std_logic_vector(13 downto 0);
--señales de depuracion
signal st : std_logic_vector (2 downto 0);
begin
--entradas:
modoSilo <= modoSiloIN;
--------------------------- RAM ------------------------------------------------
selPixelMundo(14 downto 7) <= pixelMundoHor;
selPixelMundo(6 downto 0) <= pixelMundoVer;
selPixelPantalla(14 downto 7) <= cuentaPixelCont(10 downto 3);
selPixelPantalla(6 downto 0) <= cuentaLineCont(8 downto 2);
--http://www.xilinx.com/itp/xilinx10/books/docs/spartan3_hdl/spartan3_hdl.pdf
memMenosSignif: RAMB16_S1_S1
generic map(
WRITE_MODE_B => "READ_FIRST"
)
port map (
DOA => DOAmundoMenosSig, -- Port A 1-bit Data Output
DOB => DOBmundoMenosSig, -- Port B 2-bit Data Output
ADDRA => senialADDRA, -- Port A 14-bit Address Input
ADDRB => selPixelMundo(13 downto 0), -- Port B 14-bit Address Input
CLKA => clk, -- Port A Clock
CLKB => clk, -- Port B Clock
DIA => "0", -- Port A 1-bit Data Input
DIB => DIB, -- Port B 1-bit Data Input --pintamos azul
ENA => '1', -- Port A RAM Enable Input
ENB => '1', -- PortB RAM Enable Input
SSRA => '0', -- Port A Synchronous Set/Reset Input
SSRB => '0', -- Port B Synchronous Set/Reset Input
WEA => senialWEA, -- Port A Write Enable Input
WEB => WEBmenosSig -- Port B Write Enable Input
);
memMasSignif: RAMB16_S1_S1
generic map(
WRITE_MODE_B => "READ_FIRST"
)
port map (
DOA => DOAmundoMasSig, -- Port A 1-bit Data Output
DOB => DOBmundoMasSig, -- Port B 1-bit Data Output
ADDRA => senialADDRA, -- Port A 14-bit Address Input
ADDRB => selPixelMundo(13 downto 0), -- Port B 14-bit Address Input
CLKA => clk, -- Port A Clock
CLKB => clk, -- Port B Clock
DIA => "0", -- Port A 1-bit Data Input
DIB => DIB, -- Port B 1-bit Data Input --pintamos azul
ENA => '1', -- Port A RAM Enable Input
ENB => '1', -- PortB RAM Enable Input
SSRA => '0', -- Port A Synchronous Set/Reset Input
SSRB => '0', -- Port B Synchronous Set/Reset Input
WEA => senialWEA, -- Port A Write Enable Input
WEB => WEBmasSig -- Port B Write Enable Input
);
interfazPS2: ps2KeyboardInterface port map (
rst => reset,
clk => clk,
ps2Clk => ps2Clk,
ps2Data => ps2Data,
data => scancode,
newData => newData,
newDataAck => newDataAck
);
--multiplexores
WEBmenosSig <= senialWEB when (selPixelMundo(14) = '0') else '0';
WEBmasSig <= senialWEB when (selPixelMundo(14) = '1') else '0';
DOBmundo <= DOBmundoMenosSig when (selPixelMundo(14) = '0') else DOBmundoMasSig;
DOAmundo <= DOAmundoMenosSig when (selPixelPantalla(14) = '0') else DOAmundoMasSig;
senialADDRA <= selPixelPantalla(13 downto 0) when (enableContBarrido = '0') else cuentaContBarrido(13 downto 0);
----------------------- PANTALLA -----------------------------------------------
hSync <= senialHSync;
vSync <= senialVSync;
pantalla: process(clk, reset,cuentaPixelCont,cuentaLineCont,Rnave,Rmundo,Gnave,Gmundo,
Bnave,Bmundo,Rbase,Gbase,Bbase,Rvel,Gvel,Bvel,Rfuego,Gfuego,Bfuego,
Rfuel,Gfuel,Bfuel,Rboom,Gboom,Bboom,teclaW,cuentaMuyLento,teclaA,teclaD)
begin
--cont mod 1589 (pixelCont para sincronismo horizontal)
if (cuentaPixelCont = "11000110100") then
finPixelCont <= '1';
else
finPixelCont <= '0';
end if;
if(reset = '0')then
cuentaPixelCont <= (others => '0');
finPixelCont <= '0';
elsif(clk'event and clk = '1') then
if (cuentaPixelCont /= "11000110100") then --1588
cuentaPixelCont <= cuentaPixelCont + '1';
elsif (cuentaPixelCont = "11000110100") then
cuentaPixelCont <= (others => '0');
end if;
end if;
--cont mod 528 (lineCont para sincronismo vertical)
if(reset = '0')then
cuentaLineCont <= (others => '0');
elsif(clk'event and clk = '1') then
if (finPixelCont = '1' and cuentaLineCont /= "1000001111") then --527
cuentaLineCont <= cuentaLineCont + '1';
elsif (finPixelCont = '1' and cuentaLineCont = "1000001111") then
cuentaLineCont <= (others => '0');
end if;
end if;
--comparaciones para pintar dentro de los limites
if (cuentaPixelCont > 1257) then comp1 <= '1'; else comp1 <= '0'; end if;
if (cuentaPixelCont > 1304) then comp2 <= '1'; else comp2 <= '0'; end if;
if (cuentaPixelCont <= 1493) then comp3 <= '1'; else comp3 <= '0'; end if;
if (cuentaLineCont > 479) then comp4 <= '1'; else comp4 <= '0'; end if;
if (cuentaLineCont > 493) then comp5 <= '1'; else comp5 <= '0'; end if;
if (cuentaLineCont <= 495) then comp6 <= '1'; else comp6 <= '0'; end if;
senialHSync <= comp2 nand comp3;
senialVSync <= comp5 nand comp6;
if (senialHSync = '0' or senialVSync = '0') then --no pinta
R <= "000";
G <= "000";
B <= "000";
else --pintamos lo que tengamos que pintar
R(2) <= ( (not (comp1 or comp4)) and (Rnave(2) or Rmundo(2) or Rbase(2) or Rvel(2) or Rfuego(2) or Rfuel(2) or Rboom(2)) );
R(1) <= ( (not (comp1 or comp4)) and (Rnave(1) or Rmundo(1) or Rbase(1) or Rvel(1) or Rfuego(1) or Rfuel(1) or Rboom(1)) );
R(0) <= ( (not (comp1 or comp4)) and (Rnave(0) or Rmundo(0) or Rbase(0) or Rvel(0) or Rfuego(0) or Rfuel(0) or Rboom(0)) );
G(2) <= ( (not (comp1 or comp4)) and (Gnave(2) or Gmundo(2) or Gbase(2) or Gvel(2) or Gfuego(2) or Gfuel(2) or Gboom(2)) );
G(1) <= ( (not (comp1 or comp4)) and (Gnave(1) or Gmundo(1) or Gbase(1) or Gvel(1) or Gfuego(1) or Gfuel(1) or Gboom(1)) );
G(0) <= ( (not (comp1 or comp4)) and (Gnave(0) or Gmundo(0) or Gbase(0) or Gvel(0) or Gfuego(0) or Gfuel(0) or Gboom(0)) );
B(2) <= ( (not (comp1 or comp4)) and (Bnave(2) or Bmundo(2) or Bbase(2) or Bvel(2) or Bfuego(2) or Bfuel(2) or Bboom(2)) );
B(1) <= ( (not (comp1 or comp4)) and (Bnave(1) or Bmundo(1) or Bbase(1) or Bvel(1) or Bfuego(1) or Bfuel(1) or Bboom(1)) );
B(0) <= ( (not (comp1 or comp4)) and (Bnave(0) or Bmundo(0) or Bbase(0) or Bvel(0) or Bfuego(0) or Bfuel(0) or Bboom(0)) );
end if;
end process;
------------------ PINTAR JUEGO ------------------------------------------------
-- vertical: 479 limite de pixeles visibles
-- 120 pixeles -> 479 x= (479*1)/120 = 3.99 = aprox 4
-- 1 pixeles -> x
-- horizontal: 1257 limite de pixeles visibles
-- 153 pixeles -> 1257 x= (1257*1)/153 = 8.21 = aprox 8
-- 1 pixeles -> x
pintarNave: process(cuentaLineCont,cuentaPixelCont,pixelNaveVer,pixelNaveHor)
begin
-- inicializacion
Rnave <= "000";
Gnave <= "000";
Bnave <= "000";
--pintar
if ( (cuentaLineCont(9 downto 2) = pixelNaveVer-3 or cuentaLineCont(9 downto 2) = pixelNaveVer-1)
and (cuentaPixelCont(10 downto 3) = pixelNaveHor) ) then
Rnave <= "000";
Gnave <= "110";
Bnave <= "000";
end if;
if ((cuentaLineCont(9 downto 2) = pixelNaveVer-2)
and (cuentaPixelCont(10 downto 3) = pixelNaveHor)) then
Rnave <= "000";
Gnave <= "000";
Bnave <= "110";
end if;
if (((cuentaLineCont(9 downto 2) = pixelNaveVer) or (cuentaLineCont(9 downto 2) = pixelNaveVer-2))
and (cuentaPixelCont(10 downto 3) = pixelNaveHor-1 )) then
Rnave <= "000";
Gnave <= "110";
Bnave <= "000";
end if;
if (((cuentaLineCont(9 downto 2) = pixelNaveVer) or (cuentaLineCont(9 downto 2) = pixelNaveVer-2))
and (cuentaPixelCont(10 downto 3) = pixelNaveHor+1 )) then
Rnave <= "000";
Gnave <= "110";
Bnave <= "000";
end if;
end process pintarNave;
pintarFuego: process(cuentaLineCont,cuentaPixelCont,pixelNaveVer,pixelNaveHor,
teclaW,cuentaMuyLento,teclaA,teclaD,cuentaGasolina,moverNave)
begin
-- inicializacion
Rfuego <= "000";
Gfuego <= "000";
Bfuego <= "000";
if (cuentaGasolina(30 downto 24) /= "0000000" and moverNave = '1') then
if (teclaW = '1' and cuentaMuyLento(20 downto 20) = "1") then
--pintar amarillo:abajo
if ( cuentaLineCont(9 downto 2) = pixelNaveVer and cuentaPixelCont(10 downto 3) = pixelNaveHor) then
Rfuego <= "111";
Gfuego <= "111";
Bfuego <= "000";
end if;
--pintar amarillo:abajo
if (cuentaLineCont(9 downto 2) = pixelNaveVer+1 and cuentaPixelCont(10 downto 3) = pixelNaveHor) then
Rfuego <= "111";
Gfuego <= "111";
Bfuego <= "000";
end if;
--pintar rojo:abajo
if (((cuentaLineCont(9 downto 2) = pixelNaveVer+1))
and ((cuentaPixelCont(10 downto 3) = pixelNaveHor+1 ) or (cuentaPixelCont(10 downto 3) = pixelNaveHor-1 ))) then
Rfuego <= "111";
Gfuego <= "000";
Bfuego <= "000";
end if;
if (cuentaLineCont(9 downto 2) = pixelNaveVer+2 and cuentaPixelCont(10 downto 3) = pixelNaveHor) then
Rfuego <= "111";
Gfuego <= "000";
Bfuego <= "000";
end if;
end if;
--pintar fuego lateral a la derecha (voy a la izquierda), he apretado izq
if (teclaA = '1' and cuentaMuyLento(20 downto 20) = "1") then
if (cuentaLineCont(9 downto 2) = pixelNaveVer-2 and cuentaPixelCont(10 downto 3) = pixelNaveHor+2) then
Rfuego <= "111";
Gfuego <= "000";
Bfuego <= "000";
end if;
end if;
--pintar fuego lateral a la izquierda (voy a la derecha) he apretado der
if (teclaD = '1' and cuentaMuyLento(20 downto 20) = "1") then
if (cuentaLineCont(9 downto 2) = pixelNaveVer-2 and cuentaPixelCont(10 downto 3) = pixelNaveHor-2) then
Rfuego <= "111";
Gfuego <= "000";
Bfuego <= "000";
end if;
end if;
end if;
end process pintarFuego;
pintarMundo: process(DOAmundo)
begin
-- inicializacion
Rmundo <= "000";
Gmundo <= "000";
Bmundo <= "000";
--pintar
if (DOAmundo = "1") then
Rmundo <= "011";
Gmundo <= "011";
Bmundo <= "011";
end if;
end process pintarMundo;
pintarBases: process(cuentaLineCont,cuentaPixelCont,DOAmundo,regBaseDificil1,
regBaseDificil2,regBaseFacil,modoSilo)
begin
-- inicializacion
Rbase <= "000";
Gbase <= "000";
Bbase <= "000";
--pintar baseDificil1
if (DOAmundo = "1" and
(cuentaPixelCont(10 downto 3) >= regBaseDificil1 and
cuentaPixelCont(10 downto 3) <= regBaseDificil1 +4) ) then
if (modoSilo = '1') then
Rbase <= "000";
Gbase <= "000";
Bbase <= "100";
else
--pintar lineas
if ( cuentaLineCont(9 downto 2) <= 105 and
(cuentaPixelCont(10 downto 3) = regBaseDificil1 or
cuentaPixelCont(10 downto 3) = regBaseDificil1 + 4) )then
Rbase <= "111";
Gbase <= "111";
Bbase <= "111";
end if;
--F de fuel
if ( cuentaLineCont(9 downto 2) >= 110 and cuentaLineCont(9 downto 2) <= 113 and
cuentaPixelCont(10 downto 3) = regBaseDificil1 +1) then
Rbase <= "111";
Gbase <= "111";
Bbase <= "111";
end if;
if ( (cuentaLineCont(9 downto 2) = 110 or cuentaLineCont(9 downto 2) = 112) and
cuentaPixelCont(10 downto 3) = regBaseDificil1 + 2) then
Rbase <= "111";
Gbase <= "111";
Bbase <= "111";
end if;
end if;
end if;
--pintar baseDificil2
if (DOAmundo = "1" and
(cuentaPixelCont(10 downto 3) >= regBaseDificil2 and
cuentaPixelCont(10 downto 3) <= regBaseDificil2 +4) ) then
if (modoSilo = '1') then
Rbase <= "000";
Gbase <= "000";
Bbase <= "100";
else
--pintar lineas
if ( cuentaLineCont(9 downto 2) <= 105 and
(cuentaPixelCont(10 downto 3) = regBaseDificil2 or
cuentaPixelCont(10 downto 3) = regBaseDificil2 + 4) )then
Rbase <= "111";
Gbase <= "111";
Bbase <= "111";
end if;
--F de fuel
if ( cuentaLineCont(9 downto 2) >= 110 and cuentaLineCont(9 downto 2) <= 113 and
cuentaPixelCont(10 downto 3) = regBaseDificil2 +1) then
Rbase <= "111";
Gbase <= "111";
Bbase <= "111";
end if;
if ( (cuentaLineCont(9 downto 2) = 110 or cuentaLineCont(9 downto 2) = 112) and
cuentaPixelCont(10 downto 3) = regBaseDificil2 + 2) then
Rbase <= "111";
Gbase <= "111";
Bbase <= "111";
end if;
end if;
end if;
--pintar base facil
if (DOAmundo = "1" and
(cuentaPixelCont(10 downto 3) >= regBaseFacil and
cuentaPixelCont(10 downto 3) <= regBaseFacil +8) ) then
if (modoSilo = '1') then
Rbase <= "100";
Gbase <= "000";
Bbase <= "000";
else
--pintar lineas
if ( cuentaLineCont(9 downto 2) <= 105 and
(cuentaPixelCont(10 downto 3) = regBaseFacil or
cuentaPixelCont(10 downto 3) = regBaseFacil + 8) )then
Rbase <= "111";
Gbase <= "111";
Bbase <= "111";
end if;
--F de fuel
if ( cuentaLineCont(9 downto 2) >= 110 and cuentaLineCont(9 downto 2) <= 113 and
cuentaPixelCont(10 downto 3) = regBaseFacil + 3) then
Rbase <= "111";
Gbase <= "111";
Bbase <= "111";
end if;
if ( (cuentaLineCont(9 downto 2) = 110 or cuentaLineCont(9 downto 2) = 112) and
cuentaPixelCont(10 downto 3) = regBaseFacil + 4) then
Rbase <= "111";
Gbase <= "111";
Bbase <= "111";
end if;
end if;
end if;
end process pintarBases;
pintarBoom: process(estadoJuego,cuentaLineCont,cuentaPixelCont)
begin
-- inicializacion
Rboom <= "000";
Gboom <= "000";
Bboom <= "000";
--pintar boom!
if (estadoJuego = parado) then
--pintar B
if ( (cuentaLineCont(9 downto 2) >= 36 and cuentaLineCont(9 downto 2) <= 40) and
(cuentaPixelCont(10 downto 3) = 66 or cuentaPixelCont(10 downto 3) = 68)) then
Rboom <= "111";
Gboom <= "111";
Bboom <= "111";
end if;
if ((cuentaLineCont(9 downto 2) = 36 or
cuentaLineCont(9 downto 2) = 38 or cuentaLineCont(9 downto 2) = 40 ) and
cuentaPixelCont(10 downto 3) = 67 ) then
Rboom <= "111";
Gboom <= "111";
Bboom <= "111";
end if;
--pintar primera O
if ( (cuentaLineCont(9 downto 2) >= 36 and cuentaLineCont(9 downto 2) <= 40) and
(cuentaPixelCont(10 downto 3) = 70 or cuentaPixelCont(10 downto 3) = 72)) then
Rboom <= "111";
Gboom <= "111";
Bboom <= "111";
end if;
if ( (cuentaLineCont(9 downto 2) = 36 or cuentaLineCont(9 downto 2) = 40) and
cuentaPixelCont(10 downto 3) = 71) then
Rboom <= "111";
Gboom <= "111";
Bboom <= "111";
end if;
--pintar segunda O
if ( (cuentaLineCont(9 downto 2) >= 36 and cuentaLineCont(9 downto 2) <= 40) and
(cuentaPixelCont(10 downto 3) = 74 or cuentaPixelCont(10 downto 3) = 76)) then
Rboom <= "111";
Gboom <= "111";
Bboom <= "111";
end if;
if ( (cuentaLineCont(9 downto 2) = 36 or cuentaLineCont(9 downto 2) = 40) and
cuentaPixelCont(10 downto 3) = 75) then
Rboom <= "111";
Gboom <= "111";
Bboom <= "111";
end if;
--pintar M
if ( (cuentaLineCont(9 downto 2) >= 36 and cuentaLineCont(9 downto 2) <= 40) and
(cuentaPixelCont(10 downto 3) = 78 or cuentaPixelCont(10 downto 3) = 82)) then
Rboom <= "111";
Gboom <= "111";
Bboom <= "111";
end if;
if ( (cuentaLineCont(9 downto 2) = 37) and
(cuentaPixelCont(10 downto 3) = 79 or cuentaPixelCont(10 downto 3) = 81)) then
Rboom <= "111";
Gboom <= "111";
Bboom <= "111";
end if;
if ( (cuentaLineCont(9 downto 2) = 38) and
cuentaPixelCont(10 downto 3) = 80) then
Rboom <= "111";
Gboom <= "111";
Bboom <= "111";
end if;
--pintar '!'
if ( ((cuentaLineCont(9 downto 2) >= 36 and cuentaLineCont(9 downto 2) <= 38) or
cuentaLineCont(9 downto 2) = 40 ) and
(cuentaPixelCont(10 downto 3) = 85)) then
Rboom <= "111";
Gboom <= "111";
Bboom <= "111";
end if;
end if;
end process pintarBoom;
Rvel(2) <= (R_ml(2) or R_l(2) or R_r(2) or R_mr(2));
Rvel(1) <= (R_ml(1) or R_l(1) or R_r(1) or R_mr(1));
Rvel(0) <= (R_ml(0) or R_l(0) or R_r(0) or R_mr(0));
Gvel(2) <= (G_ml(2) or G_l(2) or G_r(2) or G_mr(2));
Gvel(1) <= (G_ml(1) or G_l(1) or G_r(1) or G_mr(1));
Gvel(0) <= (G_ml(0) or G_l(0) or G_r(0) or G_mr(0));
Bvel(2) <= (B_ml(2) or B_l(2) or B_r(2) or B_mr(2));
Bvel(1) <= (B_ml(1) or B_l(1) or B_r(1) or B_mr(1));
Bvel(0) <= (B_ml(0) or B_l(0) or B_r(0) or B_mr(0));
pintarVelMuyLento: process(cuentaLineCont,cuentaPixelCont,cuentaVelVertical,cuentaVelHorizontal,
muyLentoVertical,lentoVertical,rapidoVertical,muyRapidoVertical,
muyLentoHorizontal,lentoHorizontal,rapidoHorizontal,muyRapidoHorizontal)
begin
-- inicializacion
R_ml <= "000";
G_ml <= "000";
B_ml <= "000";
--inicializar a gris:
if ((cuentaLineCont(9 downto 2) >= 4 and cuentaLineCont(9 downto 2) <= 6)
and (cuentaPixelCont(10 downto 3) >= 144 and cuentaPixelCont(10 downto 3) <= 146)) then
if ((cuentaLineCont(9 downto 2) /= 5) and (cuentaPixelCont(10 downto 3) /= 145)) then
R_ml <= "001";
G_ml <= "001";
B_ml <= "001";
end if;
end if;
if (cuentaVelHorizontal >= 0 and cuentaVelHorizontal < 64) then --hor izq
--pintar pixel muyLento
if (muyLentoHorizontal = '1' or lentoHorizontal = '1' or rapidoHorizontal = '1' or muyRapidoHorizontal = '1') then
if ((cuentaLineCont(9 downto 2) = 5) and (cuentaPixelCont(10 downto 3) = 144) ) then
R_ml <= "000";
G_ml <= "111";
B_ml <= "000";
end if;
end if;
else -- hor derecha
--pintar pixel muyLento
if (muyLentoHorizontal = '1' or lentoHorizontal = '1' or rapidoHorizontal = '1' or muyRapidoHorizontal = '1') then
if ((cuentaLineCont(9 downto 2) = 5) and (cuentaPixelCont(10 downto 3) = 146) ) then
R_ml <= "000";
G_ml <= "111";
B_ml <= "000";
end if;
end if;
end if;
if (cuentaVelVertical >= 0 and cuentaVelVertical < 64) then --ver subir
--pintar pixel muyLento
if (muyLentoVertical = '1' or lentoVertical = '1' or rapidoVertical = '1' or muyRapidoVertical = '1') then
if ((cuentaLineCont(9 downto 2) = 4) and (cuentaPixelCont(10 downto 3) = 145) ) then
R_ml <= "000";
G_ml <= "111";
B_ml <= "000";
end if;
end if;
else -- ver abajo
--pintar pixel muyLento
if (muyLentoVertical = '1' or lentoVertical = '1' or rapidoVertical = '1' or muyRapidoVertical = '1') then
if ((cuentaLineCont(9 downto 2) = 6) and (cuentaPixelCont(10 downto 3) = 145) ) then
R_ml <= "000";
G_ml <= "111";
B_ml <= "000";
end if;
end if;
end if;
end process pintarVelMuyLento;
pintarVelLento: process(cuentaLineCont,cuentaPixelCont,cuentaVelVertical,cuentaVelHorizontal,
muyLentoVertical,lentoVertical,rapidoVertical,muyRapidoVertical,
muyLentoHorizontal,lentoHorizontal,rapidoHorizontal,muyRapidoHorizontal)
begin
-- inicializacion
R_l <= "000";
G_l <= "000";
B_l <= "000";
--inicializar a gris:
if ((cuentaLineCont(9 downto 2) >= 3 and cuentaLineCont(9 downto 2) <= 7)
and (cuentaPixelCont(10 downto 3) >= 143 and cuentaPixelCont(10 downto 3) <= 147)) then
if ((cuentaLineCont(9 downto 2) /= 5) and (cuentaPixelCont(10 downto 3) /= 145)) then
R_l <= "011";
G_l <= "011";
B_l <= "011";
end if;
end if;
if (cuentaVelHorizontal >= 0 and cuentaVelHorizontal < 64) then --hor izq
--pintar pixel Lento
if (lentoHorizontal = '1' or rapidoHorizontal = '1' or muyRapidoHorizontal = '1') then
if ((cuentaLineCont(9 downto 2) = 5) and (cuentaPixelCont(10 downto 3) = 143) ) then
R_l <= "111";
G_l <= "111";
B_l <= "000";
end if;
end if;
else -- hor derecha
--pintar pixel Lento
if (lentoHorizontal = '1' or rapidoHorizontal = '1' or muyRapidoHorizontal = '1') then
if ((cuentaLineCont(9 downto 2) = 5) and (cuentaPixelCont(10 downto 3) = 147) ) then
R_l <= "111";
G_l <= "111";
B_l <= "000";
end if;
end if;
end if;
if (cuentaVelVertical >= 0 and cuentaVelVertical < 64) then --ver subir
--pintar pixel Lento
if (lentoVertical = '1' or rapidoVertical = '1' or muyRapidoVertical = '1') then
if ((cuentaLineCont(9 downto 2) = 3) and (cuentaPixelCont(10 downto 3) = 145) ) then
R_l <= "111";
G_l <= "111";
B_l <= "000";
end if;
end if;
else -- ver abajo
--pintar pixel Lento
if (lentoVertical = '1' or rapidoVertical = '1' or muyRapidoVertical = '1') then
if ((cuentaLineCont(9 downto 2) = 7) and (cuentaPixelCont(10 downto 3) = 145) ) then
R_l <= "111";
G_l <= "111";
B_l <= "000";
end if;
end if;
end if;
end process pintarVelLento;
pintarVelRapido: process(cuentaLineCont,cuentaPixelCont,cuentaVelVertical,cuentaVelHorizontal,
muyLentoVertical,lentoVertical,rapidoVertical,muyRapidoVertical,
muyLentoHorizontal,lentoHorizontal,rapidoHorizontal,muyRapidoHorizontal)
begin
-- inicializacion
R_r <= "000";
G_r <= "000";
B_r <= "000";
--inicializar a gris:
if ((cuentaLineCont(9 downto 2) >= 2 and cuentaLineCont(9 downto 2) <= 8)
and (cuentaPixelCont(10 downto 3) >= 142 and cuentaPixelCont(10 downto 3) <= 148)) then
if ((cuentaLineCont(9 downto 2) /= 5) and (cuentaPixelCont(10 downto 3) /= 145)) then
R_r <= "010";
G_r <= "010";
B_r <= "010";
end if;
end if;
if (cuentaVelHorizontal >= 0 and cuentaVelHorizontal < 64) then --hor izq
--pintar pixel
if (rapidoHorizontal = '1' or muyRapidoHorizontal = '1') then
if ((cuentaLineCont(9 downto 2) = 5) and (cuentaPixelCont(10 downto 3) = 142) ) then
R_r <= "111";
G_r <= "011";
B_r <= "000";
end if;
end if;
else -- hor derecha
--pintar pixel
if (rapidoHorizontal = '1' or muyRapidoHorizontal = '1') then
if ((cuentaLineCont(9 downto 2) = 5) and (cuentaPixelCont(10 downto 3) = 148) ) then
R_r <= "111";
G_r <= "011";
B_r <= "000";
end if;
end if;
end if;
if (cuentaVelVertical >= 0 and cuentaVelVertical < 64) then --ver subir
--pintar pixel
if (rapidoVertical = '1' or muyRapidoVertical = '1') then
if ((cuentaLineCont(9 downto 2) = 2) and (cuentaPixelCont(10 downto 3) = 145) ) then
R_r <= "111";
G_r <= "011";
B_r <= "000";
end if;
end if;
else -- ver abajo
--pintar pixel
if (rapidoVertical = '1' or muyRapidoVertical = '1') then
if ((cuentaLineCont(9 downto 2) = 8) and (cuentaPixelCont(10 downto 3) = 145) ) then
R_r <= "111";
G_r <= "011";
B_r <= "000";
end if;
end if;
end if;
end process pintarVelRapido;
pintarVelMuyRapido: process(cuentaLineCont,cuentaPixelCont,cuentaVelVertical,cuentaVelHorizontal,
muyLentoVertical,lentoVertical,rapidoVertical,muyRapidoVertical,
muyLentoHorizontal,lentoHorizontal,rapidoHorizontal,muyRapidoHorizontal)
begin
-- inicializacion
R_mr <= "000";
G_mr <= "000";
B_mr <= "000";
--inicializar a gris:
if ((cuentaLineCont(9 downto 2) >= 1 and cuentaLineCont(9 downto 2) <= 9)
and (cuentaPixelCont(10 downto 3) >= 141 and cuentaPixelCont(10 downto 3) <= 149)) then
if ((cuentaLineCont(9 downto 2) /= 5) and (cuentaPixelCont(10 downto 3) /= 145)) then
R_mr <= "000";
G_mr <= "000";
B_mr <= "000";
end if;
end if;
if (cuentaVelHorizontal >= 0 and cuentaVelHorizontal < 64) then --hor izq
--pintar pixel
if (muyRapidoHorizontal = '1') then
if ((cuentaLineCont(9 downto 2) = 5) and (cuentaPixelCont(10 downto 3) = 141) ) then
R_mr <= "111";
G_mr <= "000";
B_mr <= "000";
end if;
end if;
else -- hor derecha
--pintar pixel muyLento
if (muyRapidoHorizontal = '1') then
if ((cuentaLineCont(9 downto 2) = 5) and (cuentaPixelCont(10 downto 3) = 149) ) then
R_mr <= "111";
G_mr <= "000";
B_mr <= "000";
end if;
end if;
end if;
if (cuentaVelVertical >= 0 and cuentaVelVertical < 64) then --ver subir
--pintar pixel muyLento
if (muyRapidoVertical = '1') then
if ((cuentaLineCont(9 downto 2) = 1) and (cuentaPixelCont(10 downto 3) = 145) ) then
R_mr <= "111";
G_mr <= "000";
B_mr <= "000";
end if;
end if;
else -- ver abajo
--pintar pixel muyLento
if (muyRapidoVertical = '1') then
if ((cuentaLineCont(9 downto 2) = 9) and (cuentaPixelCont(10 downto 3) = 145) ) then
R_mr <= "111";
G_mr <= "000";
B_mr <= "000";
end if;
end if;
end if;
end process pintarVelMuyRapido;
pintarGasolina: process(cuentaLineCont,cuentaPixelCont,cuentaGasolina)
begin
-- inicializacion
Rfuel <= "000";
Gfuel <= "000";
Bfuel <= "000";
--linea gris:
if ( cuentaLineCont(9 downto 2) = 7 and
cuentaPixelCont(10 downto 3) >= 116 and cuentaPixelCont(10 downto 3) <= 127) then
Rfuel <= "111";
Gfuel <= "111";
Bfuel <= "111";
end if;
--F de fuel
if ( cuentaLineCont(9 downto 2) >= 4 and cuentaLineCont(9 downto 2) <= 7 and
cuentaPixelCont(10 downto 3) = 112) then
Rfuel <= "111";
Gfuel <= "111";
Bfuel <= "111";
end if;
if ( (cuentaLineCont(9 downto 2) = 4 or cuentaLineCont(9 downto 2) = 6) and
cuentaPixelCont(10 downto 3) = 113) then
Rfuel <= "111";
Gfuel <= "111";
Bfuel <= "111";
end if;
--lineas rojas
if ( cuentaLineCont(9 downto 2) >= 4 and cuentaLineCont(9 downto 2) <= 6 and
cuentaPixelCont(10 downto 3) = 116 and
(cuentaGasolina(30 downto 24) > "0000000" and cuentaGasolina(30 downto 24) <= "1110111")) then
Rfuel <= "111";
Gfuel <= "000";
Bfuel <= "000";
end if;
if ( cuentaLineCont(9 downto 2) >= 4 and cuentaLineCont(9 downto 2) <= 6 and
cuentaPixelCont(10 downto 3) = 117 and
(cuentaGasolina(30 downto 24) > "0001010" and cuentaGasolina(30 downto 24) <= "1110111")) then
Rfuel <= "111";
Gfuel <= "000";
Bfuel <= "000";
end if;
if ( cuentaLineCont(9 downto 2) >= 4 and cuentaLineCont(9 downto 2) <= 6 and
cuentaPixelCont(10 downto 3) = 118 and
(cuentaGasolina(30 downto 24) > "0010100" and cuentaGasolina(30 downto 24) <= "1110111")) then
Rfuel <= "111";
Gfuel <= "000";
Bfuel <= "000";
end if;
--lineas naranjas
if ( cuentaLineCont(9 downto 2) >= 4 and cuentaLineCont(9 downto 2) <= 6 and
cuentaPixelCont(10 downto 3) = 119 and
(cuentaGasolina(30 downto 24) > "0011110" and cuentaGasolina(30 downto 24) <= "1110111")) then
Rfuel <= "111";
Gfuel <= "011";
Bfuel <= "000";
end if;
if ( cuentaLineCont(9 downto 2) >= 4 and cuentaLineCont(9 downto 2) <= 6 and
cuentaPixelCont(10 downto 3) = 120 and
(cuentaGasolina(30 downto 24) > "0101000" and cuentaGasolina(30 downto 24) <= "1110111")) then
Rfuel <= "111";
Gfuel <= "011";
Bfuel <= "000";
end if;
if ( cuentaLineCont(9 downto 2) >= 4 and cuentaLineCont(9 downto 2) <= 6 and
cuentaPixelCont(10 downto 3) = 121 and
(cuentaGasolina(30 downto 24) > "0110010" and cuentaGasolina(30 downto 24) <= "1110111")) then
Rfuel <= "111";
Gfuel <= "011";
Bfuel <= "000";
end if;
--lineas amarillas
if ( cuentaLineCont(9 downto 2) >= 4 and cuentaLineCont(9 downto 2) <= 6 and
cuentaPixelCont(10 downto 3) = 122 and
(cuentaGasolina(30 downto 24) > "0111100" and cuentaGasolina(30 downto 24) <= "1110111")) then
Rfuel <= "111";
Gfuel <= "111";
Bfuel <= "000";
end if;
if ( cuentaLineCont(9 downto 2) >= 4 and cuentaLineCont(9 downto 2) <= 6 and
cuentaPixelCont(10 downto 3) = 123 and
(cuentaGasolina(30 downto 24) > "1000110" and cuentaGasolina(30 downto 24) <= "1110111")) then
Rfuel <= "111";
Gfuel <= "111";
Bfuel <= "000";
end if;
if ( cuentaLineCont(9 downto 2) >= 4 and cuentaLineCont(9 downto 2) <= 6 and
cuentaPixelCont(10 downto 3) = 124 and
(cuentaGasolina(30 downto 24) > "1010000" and cuentaGasolina(30 downto 24) <= "1110111")) then
Rfuel <= "111";
Gfuel <= "111";
Bfuel <= "000";
end if;
--lineas verdes
if ( cuentaLineCont(9 downto 2) >= 4 and cuentaLineCont(9 downto 2) <= 6 and
cuentaPixelCont(10 downto 3) = 125 and
(cuentaGasolina(30 downto 24) > "1011010" and cuentaGasolina(30 downto 24) <= "1110111")) then
Rfuel <= "000";
Gfuel <= "111";
Bfuel <= "000";
end if;
if ( cuentaLineCont(9 downto 2) >= 4 and cuentaLineCont(9 downto 2) <= 6 and
cuentaPixelCont(10 downto 3) = 126 and
(cuentaGasolina(30 downto 24) > "1100100" and cuentaGasolina(30 downto 24) <= "1110111")) then
Rfuel <= "000";
Gfuel <= "111";
Bfuel <= "000";
end if;
if ( cuentaLineCont(9 downto 2) >= 4 and cuentaLineCont(9 downto 2) <= 6 and
cuentaPixelCont(10 downto 3) = 127 and
(cuentaGasolina(30 downto 24) > "1101110" and cuentaGasolina(30 downto 24) <= "1110111") ) then
Rfuel <= "000";
Gfuel <= "111";
Bfuel <= "000";
end if;
end process pintarGasolina;
--#################### CONTROL JUEGO #########################################--
contadorMuyRapido: process(reset,clk,cuentaMuyRapido) --contador mod 2.000.000 (de 0 a 1.999.999)
begin
if (cuentaMuyRapido = "111101000010001111111") then
finCuentaMuyRapido <= '1';
else
finCuentaMuyRapido <= '0';
end if;
if(reset = '0')then
cuentaMuyRapido <= (others => '0');
finCuentaMuyRapido <= '0';
elsif(clk'event and clk = '1') then
if (cuentaMuyRapido /= "111101000010001111111") then
cuentaMuyRapido <= cuentaMuyRapido + 1;
elsif (cuentaMuyRapido = "111101000010001111111") then
cuentaMuyRapido <= (others => '0');
end if;
end if;
end process contadorMuyRapido;
contadorRapido: process(reset,clk,cuentaRapido) --contador mod 4.000.000 (de 0 a 3.999.999)
begin
if (cuentaRapido = "1111010000100011111111") then
finCuentaRapido <= '1';
else
finCuentaRapido <= '0';
end if;
if(reset = '0')then
cuentaRapido <= (others => '0');
finCuentaRapido <= '0';
elsif(clk'event and clk = '1') then
if (cuentaRapido /= "1111010000100011111111") then
cuentaRapido <= cuentaRapido + 1;
elsif (cuentaRapido = "1111010000100011111111") then
cuentaRapido <= (others => '0');
end if;
end if;
end process contadorRapido;
contadorLento: process(reset,clk,cuentaLento) --contador mod 8.000.000 (de 0 a 7.999.999)
begin
if (cuentaLento = "11110100001000111111111") then
finCuentaLento <= '1';
else
finCuentaLento <= '0';
end if;
if(reset = '0')then
cuentaLento <= (others => '0');
finCuentaLento <= '0';
elsif(clk'event and clk = '1') then
if (cuentaLento /= "11110100001000111111111") then
cuentaLento <= cuentaLento + 1;
elsif (cuentaLento = "11110100001000111111111") then
cuentaLento <= (others => '0');
end if;
end if;
end process contadorLento;
contadorMuyLento: process(reset,clk,cuentaMuyLento) --contador mod 16.000.000 (de 0 a 15.999.999)
begin
if (cuentaMuyLento = "11110100001000111111111111") then
finCuentaMuyLento <= '1';
else
finCuentaMuyLento <= '0';
end if;
if(reset = '0')then
cuentaMuyLento <= (others => '0');
finCuentaMuyLento <= '0';
elsif(clk'event and clk = '1') then
if (cuentaMuyLento /= "11110100001000111111111111") then
cuentaMuyLento <= cuentaMuyLento + 1;
elsif (cuentaMuyLento = "11110100001000111111111111") then
cuentaMuyLento <= (others => '0');
end if;
end if;
end process contadorMuyLento;
contadorGasolina: process(reset,clk,cuentaGasolina,teclaSPC,haAterrizado) --contador mod 32.000.000 (de 0 a 31.999.999)
begin
if (cuentaGasolina = "0000000000000000000000000000") then
finCuentaGasolina <= '1';
else
finCuentaGasolina <= '0';
end if;
if(reset = '0')then
cuentaGasolina <= "1111010000100011111111111111111";
finCuentaGasolina <= '0';
elsif(clk'event and clk = '1') then
if (cuentaGasolina /= "0000000000000000000000000000") then
cuentaGasolina <= cuentaGasolina - 1;
end if;
if (modoSilo = '0') then
if (haAterrizado = '1' and cuentaGasolina(30 downto 24) < "1101110") then --recarga gasolina
cuentaGasolina <= cuentaGasolina +20;
end if;
else
if (pixelNaveVer = "1110111" and cuentaGasolina(30 downto 24) < "1101110") then --recarga gasolina
cuentaGasolina <= cuentaGasolina +20;
end if;
end if;
if (teclaSPC = '1') then
cuentaGasolina <= "1111010000100011111111111111111";
end if;
end if;
end process contadorGasolina;
contVelVertical: process(reset,clk,cuentaVelVertical,finCuentaLento,teclaSPC,
movNave,moverNave) --contador mod
begin
-- de 0 a 63, sube (para subir hay que restar)
-- de 64 a 127, baja (para bajar hay que sumar)
if(reset = '0')then
cuentaVelVertical <= "1000110"; --70: cae a poca velocidad
elsif(clk'event and clk = '1') then
if (finCuentaLento = '1' ) then--and moverNave = '1') then
--127: con el bit mas sig, si es 0 el resto de bits seran la vel de caida; lo mismo para la de subida cuando bit mas sig igual 1
--hay gravedad:
if ((haAterrizado = '0' or hayColision = '0') and cuentaVelVertical <= "1111101") then
cuentaVelVertical <= cuentaVelVertical +2;
end if;
if (haAterrizado = '1') then
cuentaVelVertical <= "1000000"; --no tiene velocidad de caida
end if;
if (movNave = "001") then --nave hacia arriba
if (cuentaVelVertical >= "0000100") then --4
cuentaVelVertical <= cuentaVelVertical - 4;
end if;
if (haAterrizado = '1') then --hemos aterrizado, si encendemos motores despegamos fuerte
cuentaVelVertical <= "0001111";
end if;
end if;
end if;
end if;
--generacion de velocidad
muyLentoVertical <= '0';
lentoVertical <= '0';
rapidoVertical <= '0';
muyRapidoVertical <= '0';
if ((cuentaVelVertical >= 0 and cuentaVelVertical < 15) or --subiendo muy rapido
(cuentaVelVertical >= 109 and cuentaVelVertical <= 127)) then --bajando muy rapido
muyRapidoVertical <= '1';
elsif ((cuentaVelVertical >=15 and cuentaVelVertical < 30) or --subiendo rapido
(cuentaVelVertical >= 94 and cuentaVelVertical < 109)) then --bajando rapido
rapidoVertical <= '1';
elsif ((cuentaVelVertical >= 30 and cuentaVelVertical < 45) or --subiendo lento
(cuentaVelVertical >= 79 and cuentaVelVertical < 94)) then --bajando lento
lentoVertical <= '1';
elsif ((cuentaVelVertical >= 45 and cuentaVelVertical < 64) or --subiendo muy lento
(cuentaVelVertical >= 64 and cuentaVelVertical <= 79)) then --bajando muy lento
muyLentoVertical <= '1';
end if;
if (teclaSPC = '1') then
cuentaVelVertical <= "1000110"; --70: cae a poca velocidad
end if;
end process contVelVertical;
contVelHorizontal: process(reset,clk,cuentaVelHorizontal,finCuentaLento,teclaSPC,
movNave,moverNave) --contador mod
begin
-- de 0 a 63, izquierda (para ir izquierda hay que restar)
-- de 64 a 127, derecha (para ir derecha hay que sumar)
if(reset = '0')then
cuentaVelHorizontal <= "1000110"; --70: cae a poca velocidad
elsif(clk'event and clk = '1') then
if (finCuentaLento = '1' and moverNave = '1') then
--127: con el bit mas sig, si es 0 el resto de bits seran la vel de izquiera; lo mismo para la derecha cuando bit mas sig igual 1
--si usamos los motores, cambiamos la velocidad
if (movNave = "100") then --nave hacia derecha
if (cuentaVelHorizontal < "1111011") then --123
cuentaVelHorizontal <= cuentaVelHorizontal + 4;
end if;
end if;
if (movNave = "011") then --nave hacia la izquierda
if (cuentaVelHorizontal >= "0000100") then --4
cuentaVelHorizontal <= cuentaVelHorizontal - 4;
end if;
end if;
end if;
end if;
--generacion de velocidad
muyLentoHorizontal <= '0';
lentoHorizontal <= '0';
rapidoHorizontal <= '0';
muyRapidoHorizontal <= '0';
if ((cuentaVelHorizontal >= 0 and cuentaVelHorizontal < 15) or --izq muy rapido
(cuentaVelHorizontal >= 109 and cuentaVelHorizontal <= 127)) then --der muy rapido
muyRapidoHorizontal <= '1';
elsif ((cuentaVelHorizontal >=15 and cuentaVelHorizontal < 30) or --izq rapido
(cuentaVelHorizontal >= 94 and cuentaVelHorizontal < 109)) then --der rapido
rapidoHorizontal <= '1';
elsif ((cuentaVelHorizontal >= 30 and cuentaVelHorizontal < 45) or --izq lento
(cuentaVelHorizontal >= 79 and cuentaVelHorizontal < 94)) then --der lento
lentoHorizontal <= '1';
elsif ((cuentaVelHorizontal >= 45 and cuentaVelHorizontal < 64) or --izq muy lento
(cuentaVelHorizontal >= 64 and cuentaVelHorizontal <= 79)) then --der muy lento
muyLentoHorizontal <= '1';
end if;
if (teclaSPC = '1') then
cuentaVelHorizontal <= "1000110"; --70: cae a poca velocidad
end if;
end process contVelHorizontal;
nave: process(clk,reset,moverNave,finCuentaLento,pixelNaveHor,pixelNaveVer,movNave,
cuentaVelVertical,cuentaVelHorizontal,muyLentoHorizontal,
lentoHorizontal,rapidoHorizontal,muyRapidoHorizontal,muyLentoVertical,
lentoVertical,rapidoVertical,muyRapidoVertical)
begin
posNave(14 downto 7) <= pixelNaveHor;
posNave(6 downto 0) <= pixelNaveVer;
--vertical: cont mod 102 y horizontal: cont mod 153
if (reset = '0')then --pos inicial coche1
pixelNaveVer <= "0001000"; --en 9
pixelNaveHor <= "00000011"; --en 3
elsif (clk'event and clk = '1' and moverNave = '1') then
--movimiento de la nave vertical
if (cuentaVelVertical < "1000000") then --64 limite: va hacia arriba
if (pixelNaveVer >= "0000001") then
if (muyLentoVertical = '1') then
if (finCuentaMuyLento = '1') then
if (pixelNaveVer-1 /= "0000000") then pixelNaveVer <= pixelNaveVer - 1; end if;
end if;
elsif (lentoVertical = '1') then
if (finCuentaLento = '1') then
if (pixelNaveVer-1 /= "0000000") then pixelNaveVer <= pixelNaveVer - 1; end if;
end if;
elsif (rapidoVertical = '1') then
if (finCuentaRapido = '1') then
if (pixelNaveVer-1 /= "0000000") then pixelNaveVer <= pixelNaveVer - 1; end if;
end if;
elsif (muyRapidoVertical = '1') then
if (finCuentaMuyRapido = '1') then
if (pixelNaveVer-1 /= "0000000") then pixelNaveVer <= pixelNaveVer - 1; end if;
end if;
end if;
end if;
elsif (cuentaVelVertical >= "1000000") then --va hacia abajo
if (pixelNaveVer < "1110111") then
if (muyLentoVertical = '1') then
if (finCuentaMuyLento = '1') then
if (pixelNaveVer-1 /= "1110111") then pixelNaveVer <= pixelNaveVer + 1; end if;
end if;
elsif (lentoVertical = '1') then
if (finCuentaLento = '1') then
if (pixelNaveVer-1 /= "1110111") then pixelNaveVer <= pixelNaveVer + 1; end if;
end if;
elsif (rapidoVertical = '1') then
if (finCuentaRapido = '1') then
if (pixelNaveVer-1 /= "1110111") then pixelNaveVer <= pixelNaveVer + 1; end if;
end if;
elsif (muyRapidoVertical = '1') then
if (finCuentaMuyRapido = '1') then
if (pixelNaveVer-1 /= "1110111") then pixelNaveVer <= pixelNaveVer + 1; end if;
end if;
end if;
end if;
end if;
--movimiento de la nave horizontal
if (cuentaVelHorizontal <"1000000") then --va hacia la izq
if (muyLentoHorizontal = '1') then
if (finCuentaMuyLento = '1') then
if (pixelNaveHor-1 /= "00000000") then pixelNaveHor <= pixelNaveHor - 1; end if;
end if;
elsif (lentoHorizontal = '1') then
if (finCuentaLento = '1') then
if (pixelNaveHor-1 /= "00000000") then pixelNaveHor <= pixelNaveHor - 1; end if;
end if;
elsif (rapidoHorizontal = '1') then
if (finCuentaRapido = '1') then
if (pixelNaveHor-1 /= "00000000") then pixelNaveHor <= pixelNaveHor - 1; end if;
end if;
elsif (muyRapidoHorizontal = '1') then
if (finCuentaMuyRapido = '1') then
if (pixelNaveHor-1 /= "00000000") then pixelNaveHor <= pixelNaveHor - 1; end if;
end if;
end if;
elsif (cuentaVelHorizontal >= "1000000") then --va hacia la der
if (muyLentoHorizontal = '1') then
if (finCuentaMuyLento = '1') then
if (pixelNaveHor-1 /= "10011000") then pixelNaveHor <= pixelNaveHor + 1; end if;
end if;
elsif (lentoHorizontal = '1') then
if (finCuentaLento = '1') then
if (pixelNaveHor-1 /= "10011000") then pixelNaveHor <= pixelNaveHor + 1; end if;
end if;
elsif (rapidoHorizontal = '1') then
if (finCuentaRapido = '1') then
if (pixelNaveHor-1 /= "10011000") then pixelNaveHor <= pixelNaveHor + 1; end if;
end if;
elsif (muyRapidoHorizontal = '1') then
if (finCuentaMuyRapido = '1') then
if (pixelNaveHor-1 /= "10011000") then pixelNaveHor <= pixelNaveHor + 1; end if;
end if;
end if;
end if;
if (teclaSPC = '1') then
pixelNaveVer <= "0001000"; --en 9
pixelNaveHor <= "00000011"; --en 3
end if;
end if;
end process nave;
asigMovNave: process(teclaA,teclaW,teclaS,teclaD,cuentaGasolina)
begin
movNave <= "000";
if (cuentaGasolina(30 downto 24) /= "0000000") then --si queda gasolina, enciendes motores
if (teclaW = '1') then movNave <= "001"; end if;
if (teclaS = '1') then movNave <= "010"; end if;
if (teclaA = '1') then movNave <= "011"; end if;
if (teclaD = '1') then movNave <= "100"; end if;
end if;
end process asigMovNave;
generacionBases: process(clk,reset,Q,contMod3,generarBases,clContMod3,selPixelMundo,
selPixelPantalla)
begin
if (reset = '0') then
regBaseDificil1 <= "0000000";
regBaseDificil2 <= "0000000";
regBaseFacil <= "0000000";
contMod3 <= "00";
elsif (clk'event and clk = '1') then
if (generarBases = '1' and contMod3 /= "11") then
case contMod3 is
when "00" => regBaseDificil1 <= Q(6 downto 0); --7 bits porque 100="1100100". A la dir base de nuestras bases vamos a sumar un num aleatorio
when "01" => regBaseDificil2 <= Q(6 downto 0);
when "10" => regBaseFacil <= Q(6 downto 0);
when others => null;
end case;
contMod3 <= contMod3 + 1;
end if;
if (clContMod3 = '1') then
contMod3 <= "00";
end if;
end if;
end process generacionBases;
colision: process(DOAmundo,posNave,selPixelPantalla,pixelNaveHor,regBaseDificil1,
regBaseDificil2,regBaseFacil,muyRapidoVertical,modoSilo)
begin
hayColision <= '0';
BiestablehaAterrizado <= '0';
if ((DOAmundo = "1" and posNave = selPixelPantalla) and not
((pixelNaveHor >= regBaseDificil1 and pixelNaveHor < regBaseDificil1 +5) or --en baseDificil1
(pixelNaveHor >= regBaseDificil2 and pixelNaveHor < regBaseDificil2 +5) or --en baseDificil2
(pixelNaveHor >= regBaseFacil and pixelNaveHor < regBaseFacil +9) --en baseFacil
)) then
hayColision <= '1';
end if;
if ((DOAmundo = "1" and modoSilo = '0' and
(posNave(14 downto 7) = selPixelPantalla(14 downto 7)) and --posicion de la nave
(posNave(6 downto 0) = selPixelPantalla(6 downto 0))
) and
((pixelNaveHor >= regBaseDificil1 and pixelNaveHor < regBaseDificil1 +5) or --en baseDificil1
(pixelNaveHor >= regBaseDificil2 and pixelNaveHor < regBaseDificil2 +5) or --en baseDificil2
(pixelNaveHor >= regBaseFacil and pixelNaveHor < regBaseFacil +9) --en baseFacil
)) then --si estamos donde la base
if (muyRapidoVertical = '0') then --no voy muy rapido hacia abajo
BiestablehaAterrizado <= '1';
else
hayColision <= '1';
end if;
end if;
end process colision;
biestable_D_haAterrizado: process(reset,clk,BiestablehaAterrizado,movNave) --con este biestableD conseguimos que continue el juego si ha aterrizado
begin
if(reset = '0')then
haAterrizado <= '0';
elsif(clk'event and clk = '1' ) then
if (teclaSPC = '1') then
haAterrizado <= '0';
end if;
if (posNave = selPixelPantalla) then
haAterrizado <= BiestablehaAterrizado;
end if;
end if;
end process biestable_D_haAterrizado;
--maquina de estados de la generacion de mundo -------------------------------------------------
controladorFSMgeneracionMundo: process (clk, reset, estadoJuego, pixelMundoVer)
begin
if(reset = '0') then
estadoGenMundo <= generaAleatOBase;
elsif (clk'event and clk = '1' and estadoJuego = iniciando) then
estadoGenMundo <= generaAleatOBase; -- estado por defecto, puede ser sobreescrito luego
case estadoGenMundo is
when generaAleatOBase =>
estadoGenMundo <= guardaPixelVer;
when guardaPixelVer =>
estadoGenMundo <= pintarCol;
when pintarCol =>
estadoGenMundo <= pintarCol;
if (pixelMundoVer = "1111000") then --ver 120
estadoGenMundo <= generaAleatOBase;
end if;
end case;
end if;
end process controladorFSMgeneracionMundo;
generadorMealyFSMgeneracionMundo: process (clk,reset,pixelMundoHor,pixelMundoVer,regBaseDificil1,regBaseDificil2,
regBaseFacil,pixelAnteriorVer,Q,estadoGenMundo)
begin
pixelMundoVer <= pixelMundoVer;
pixelMundoHor <= pixelMundoHor;
pixelAnteriorVer <= pixelAnteriorVer;
if (reset = '0') then
pixelMundoVer <= "1011010"; --90
pixelAnteriorVer <= "1011010"; --90
pixelMundoHor <= "00000000";
finGenerarMundo <= '0';
elsif (clk'event and clk = '1') then
case estadoGenMundo is
when generaAleatOBase =>
finGenerarMundo <= '0';
--si es base
if ((pixelMundoHor >= regBaseDificil1 and pixelMundoHor < regBaseDificil1 +5) or
(pixelMundoHor >= regBaseDificil2 and pixelMundoHor < regBaseDificil2 +5) or
(pixelMundoHor >= regBaseFacil and pixelMundoHor < regBaseFacil +9 ) ) then
pixelAnteriorVer <= pixelAnteriorVer;
--no es base
--sube y baja aleatoriamente dependiendo de unos valores fijados
-- 0 <= Q <= 32767 (num de pixeles fisicos) 1/4 = 8191 2/4 = 16383 3/4 = 24573
elsif (Q>=0 and Q <= 8191) then
pixelAnteriorVer <= pixelAnteriorVer - 2;
if (pixelAnteriorVer <= "0100111") then pixelAnteriorVer <= "0100111"; end if; --0100111=pixel logico 39 (el mundo no podrá subir más alla del tercio de la pantalla, para que entre la nave)
elsif (Q>8191 and Q <= 16383) then
pixelAnteriorVer <= pixelAnteriorVer - 1;
if (pixelAnteriorVer <= "0100111") then pixelAnteriorVer <= "0100111"; end if; --0100111=pixel logico 39
elsif (Q>16383 and Q <= 24573) then
pixelAnteriorVer <= pixelAnteriorVer + 2;
if (pixelAnteriorVer >= "1101110") then pixelAnteriorVer <= "1101110"; end if; --1101110=pixel logico 110 (el mundo no podrá bajar más alla del pixel 110 de la pantalla, para que se vea)
elsif (Q>24573 and Q <= 32767) then
pixelAnteriorVer <= pixelAnteriorVer + 1;
if (pixelAnteriorVer >= "1101110") then pixelAnteriorVer <= "1101110"; end if; --1101110=pixel logico 110
end if;
when guardaPixelVer =>
pixelMundoVer <= pixelAnteriorVer;
when pintarCol =>
if (pixelMundoVer /= "1111000") then --ver 120: si es distinto me pintas la columna
pixelMundoVer <= pixelMundoVer + 1;
elsif (pixelMundoVer = "1111000" and pixelMundoHor /= "10011001") then --ver 120 / hor 153: pasar a siguiente columna
pixelMundoHor <= pixelMundoHor + 1;
elsif (pixelMundoVer = "1111000" and pixelMundoHor = "10011001") then --ver 120 / hor 153: acabo de generar mundo, reinicio tambien para la sig vez
finGenerarMundo <= '1';
pixelMundoVer <= "1011010"; --90
pixelAnteriorVer <= "1011010"; --90
pixelMundoHor <= "00000000";
end if;
when others =>
pixelMundoHor <= pixelMundoHor;
pixelMundoVer <= pixelMundoVer;
pixelAnteriorVer <= pixelAnteriorVer;
end case;
end if;
end process generadorMealyFSMgeneracionMundo;
--------------------------------------------------------------------------------
--maquina de estados con registros de flags para el teclado---------------------
controladorFSMteclado: process (clk, reset, newData, scancode)
begin
if(reset = '0') then
estadoTeclado <= pulsadas;
elsif (clk'event and clk = '1') then
estadoTeclado <= pulsadas; -- estado por defecto, puede ser sobreescrito luego
case estadoTeclado is
when pulsadas =>
estadoTeclado <= pulsadas;
if (newData = '1' and scancode = "11110000") then --11110000: F0
estadoTeclado <= despulsadas;
end if;
when despulsadas =>
estadoTeclado <= despulsadas;
if (newData = '1') then
estadoTeclado <= pulsadas;
end if;
end case;
end if;
end process controladorFSMteclado;
generadorMealyFSMteclado: process (newDataAck, scancode, estadoTeclado, newData)
begin
newDataAck <= '0';
clTeclaW <= '0';
clTeclaS <= '0';
clTeclaA <= '0';
clTeclaD <= '0';
clTeclaSPC <= '0';
ldTeclaW <= '0';
ldTeclaS <= '0';
ldTeclaA <= '0';
ldTeclaD <= '0';
ldTeclaSPC <= '0';
case estadoTeclado is
when pulsadas =>
if (newData = '1') then --11110000: F0
case scancode is --registros de flags:
when "00011101" => ldTeclaW <= '1'; clTeclaW <= '0'; --W=1D
when "00011011" => ldTeclaS <= '1'; clTeclaS <= '0'; --S=1B
when "00011100" => ldTeclaA <= '1'; clTeclaA <= '0'; --A=1C
when "00100011" => ldTeclaD <= '1'; clTeclaD <= '0'; --D=23
when "00101001" => ldTeclaSPC <= '1'; clTeclaSPC <= '0'; --SPC=29
when others => null;
end case;
newDataAck <= '1';
end if;
when despulsadas =>
if (newData = '1') then
case scancode is --registros de flags:
when "00011101" => ldTeclaW <= '0'; clTeclaW <= '1'; --W=1D
when "00011011" => ldTeclaS <= '0'; clTeclaS <= '1'; --S=1B
when "00011100" => ldTeclaA <= '0'; clTeclaA <= '1'; --A=1C
when "00100011" => ldTeclaD <= '0'; clTeclaD <= '1'; --D=23
when "00101001" => ldTeclaSPC <= '0'; clTeclaSPC <= '1'; --SPC=29
when others => null;
end case;
newDataAck <= '1';
end if;
when others => null;
end case;
end process generadorMealyFSMteclado;
biestableDteclaSPC: process(reset,clk,ldTeclaSPC,clTeclaSPC)
begin
if(reset = '0')then
teclaSPC <= '0';
elsif(clk'event and clk = '1' ) then
if (clTeclaSPC = '1') then
teclaSPC <= '0';
elsif (ldTeclaSPC = '1') then
teclaSPC <= '1';
end if;
end if;
end process biestableDteclaSPC;
biestableDteclaW: process(reset,clk,ldTeclaW,clTeclaW)
begin
if(reset = '0')then
teclaW <= '0';
elsif(clk'event and clk = '1' ) then
if (clTeclaW = '1') then
teclaW <= '0';
elsif (ldTeclaW = '1') then
teclaW <= '1';
end if;
end if;
end process biestableDteclaW;
biestableDteclaS: process(reset,clk,ldTeclaS,clTeclaS)
begin
if(reset = '0')then
teclaS <= '0';
elsif(clk'event and clk = '1' ) then
if (clTeclaS = '1') then
teclaS <= '0';
elsif (ldTeclaS = '1') then
teclaS <= '1';
end if;
end if;
end process biestableDteclaS;
biestableDteclaA: process(reset,clk,ldTeclaA,clTeclaA)
begin
if(reset = '0')then
teclaA <= '0';
elsif(clk'event and clk = '1' ) then
if (clTeclaA = '1') then
teclaA <= '0';
elsif (ldTeclaA = '1') then
teclaA <= '1';
end if;
end if;
end process biestableDteclaA;
biestableDteclaD: process(reset,clk,ldTeclaD,clTeclaD)
begin
if(reset = '0')then
teclaD <= '0';
elsif(clk'event and clk = '1' ) then
if (clTeclaD = '1') then
teclaD <= '0';
elsif (ldTeclaD = '1') then
teclaD <= '1';
end if;
end if;
end process biestableDteclaD;
--maquina de estados del juego -------------------------------------------------
controladorFSMjuego: process (clk, reset, finGenerarMundo, finCuentaBarrido,
hayColision, teclaSPC)
begin
if(reset = '0') then
estadoJuego <= iniciando;
elsif (clk'event and clk = '1') then
estadoJuego <= iniciando; -- estado por defecto, puede ser sobreescrito luego
case estadoJuego is
when iniciando =>
estadoJuego <= iniciando;
if (finGenerarMundo = '1') then
estadoJuego <= jugando;
end if;
when jugando =>
estadoJuego <= jugando;
if (hayColision = '1') then
estadoJuego <= parado;
end if;
if (teclaSPC = '1') then
estadoJuego <= reseteo;
end if;
when parado =>
estadoJuego <= parado;
if (teclaSPC = '1') then
estadoJuego <= reseteo;
end if;
when reseteo =>
estadoJuego <= reseteo;
if (finCuentaBarrido = '1') then
estadoJuego <= iniciando;
end if;
end case;
end if;
end process controladorFSMjuego;
generadorMooreJuego: process (estadoJuego)
begin
--memorias
senialWEA <= '0';
senialWEB <= '0';
DIB <= "1";
enableContBarrido <= '0';
--juego:generar
clContMod3 <= '1';
generarBases <= '0';
--juego:estado
moverNave <= '0';
st <= "000";
case estadoJuego is
when iniciando =>
-- escribo por puerto B
--memorias
senialWEA <= '0';
senialWEB <= '1';
DIB <= "1";
enableContBarrido <= '0';
--juego:generar
clContMod3 <= '0';
generarBases <= '1';
--juego:estado
moverNave <= '0';
st <= "000";
when jugando =>
-- leo por puerto A, escribo por puerto B
--memorias
senialWEA <= '0';
senialWEB <= '0';
DIB <= "0";
enableContBarrido <= '0';--resetea contBarrido
--juego:generar
clContMod3 <= '0';
generarBases <= '0';
--juego:estado
moverNave <= '1';
st <= "001";
when parado =>
--memorias
senialWEA <= '0';
senialWEB <= '0';
DIB <= "0";
enableContBarrido <= '0'; --resetea contBarrido
--juego:generar
clContMod3 <= '0'; --no se toca, se necesitan los reg para calcular colisiones
generarBases <= '0';
--juego:estado
moverNave <= '0';
st <= "010";
when reseteo =>
-- reseteo por puerto A
--memorias
senialWEA <= '1';
senialWEB <= '0';
DIB <= "0";
enableContBarrido <= '1';
--juego:generar
clContMod3 <= '1'; --para que en iniciando se vuelvan a generar las bases
generarBases <= '0';
--juego:estado
moverNave <= '0';
st <= "011";
when others => null;
end case;
end process generadorMooreJuego;
conversor7seg: process(st)
begin
case st is
--gfedcba
when "000" => segs <= "0111111";
when "001" => segs <= "0000110";
when "010" => segs <= "1011011";
when "011" => segs <= "1001111";
when OTHERS => segs <= "1111001"; -- error
end case;
end process;
--------------------------------------------------------------------------------
--contador para limpiar la ram
contBarrido: process(reset,clk,cuentaContBarrido,enableContBarrido) --contador mod 2^15=32768 (120 x 153 pixeles)
begin
if (cuentaContBarrido = "111111111111111") then --32768 "111111111111111") then --70000 10001000101110000
finCuentaBarrido <= '1';
else
finCuentaBarrido <= '0';
end if;
if(reset = '0')then
cuentaContBarrido <= (others => '0');
finCuentaBarrido <= '0';
elsif(clk'event and clk = '1') then
if(enableContBarrido = '1') then
if (cuentaContBarrido /= "111111111111111") then --32768 "111111111111111") then
cuentaContBarrido <= cuentaContBarrido + 1;
end if;
elsif (enableContBarrido = '0') then
cuentaContBarrido <= (others => '0');
end if;
end if;
end process contBarrido;
--------------------------------------------------------------------------------
-- lsfr para la generacion aleatoria
lsfr: process(reset,clk,D,Q)
begin
--conexiones entre biestables
D(14 downto 1) <= Q(13 downto 0); --D(X) es Q(X-1)
--entrada de D1
puertaAND <= (Q(14 downto 14) and Q(13 downto 13) and Q(12 downto 12) and
Q(11 downto 11) and Q(10 downto 10) and Q(9 downto 9) and
Q(8 downto 8) and Q(7 downto 7) and Q(6 downto 6) and
Q(5 downto 5) and Q(4 downto 4) and Q(3 downto 3) and
Q(2 downto 2) and Q(1 downto 1) and Q(0 downto 0));
D(0 downto 0) <= ( (not (Q(14 downto 14) xor Q(13 downto 13)))
xor (puertaAND or puertaAND) );
if(reset = '0')then
Q(14 downto 0) <= (others => '0');
elsif(clk'event and clk = '1' ) then
Q <= D;
end if;
end process lsfr;
end Behavioral;
| gpl-3.0 | f21e6b71b4a2f216cba72f83c94a743f | 0.626152 | 2.95724 | false | false | false | false |
estadofinito/biblioteca-vhdl | todos-los-archivos/clk5Hz.vhd | 2 | 1,262 | ----------------------------------------------------------------------------------
-- Compañía: Estado Finito
-- Ingeniero: Carlos Ramos
--
-- Fecha de creación: 2014/05/21 19:24:22
-- Nombre del módulo: clk5Hz - Behavioral
-- Comentarios adicionales:
-- Implementación de forma exacta, a caso con escala par.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity clk5Hz is
Port (
clk : in STD_LOGIC; -- Reloj de entrada de 50000000Hz.
reset : in STD_LOGIC;
clk_out : out STD_LOGIC -- Reloj de salida de 5Hz.
);
end clk5Hz;
architecture Behavioral of clk5Hz is
signal temporal: STD_LOGIC;
signal contador: integer range 0 to 4999999 := 0;
begin
divisor_frecuencia: process (clk, reset) begin
if (reset = '1') then
temporal <= '0';
contador <= 0;
elsif rising_edge(clk) then
if (contador = 4999999) then
temporal <= NOT(temporal);
contador <= 0;
else
contador <= contador + 1;
end if;
end if;
end process;
clk_out <= temporal;
end Behavioral; | lgpl-2.1 | fbc5103f3ee00d1b06043ccbd66a1a78 | 0.490851 | 4.17608 | false | false | false | false |
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| gpl-3.0 | fa8e1cf676788b56a76fa965e59bb6ed | 0.917064 | 1.921117 | false | false | false | false |
hgunicamp/Mips8B | src_test/tests/simulacoes/test_Mips_Processor-somavet.vhdl | 1 | 4,096 | -- Teste geral para a estrutura do Processador Mips8B
Library Ieee;
Use Ieee.Std_Logic_1164.all;
Use Ieee.Numeric_Std.all;
Entity test_processor is
End Entity test_processor;
Architecture test_general of test_processor is
Component Mips8B is
Port(Reset_n: In Std_Logic;
Clock: In Std_Logic;
MAddr: Out Std_Logic_Vector(7 downto 0);
MCmd: Out Std_Logic_Vector(1 downto 0);
MData: Out Std_Logic_Vector(7 downto 0);
SData: In Std_Logic_Vector(7 downto 0);
SCmdAccept: In Std_Logic);
End Component Mips8B;
Type Memory_Array is Array(Natural Range <>) of Std_Logic_Vector(7 downto 0);
Use Work.MIPS8B_Base.ocpIDLE_little;
Use Work.MIPS8B_Base.ocpWR_little;
Use Work.MIPS8B_Base.ocpRD_little;
Use Work.MIPS8B_Base.ocpNULL_little;
Use Work.MIPS8B_Base.ocpDVA_little;
Signal Reset_n: Std_Logic;
Signal Clock: Std_Logic := '0';
Signal Clock_Mem: Std_Logic := '0';
Signal MAddr: Std_Logic_Vector(7 downto 0);
Signal MCmd: Std_Logic_Vector(1 downto 0);
Signal MData: Std_Logic_Vector(7 downto 0);
Signal SData: Std_Logic_Vector(7 downto 0);
Signal SCmdAccept: Std_Logic;
Begin
Reset_n <= '1', '0' after 20 ns, '1' after 40 ns;
Clock <= not Clock after 10 ns;
Clock_Mem <= not Clock_Mem after 15 ns;
Memory: Process
Variable int_SCmdAccept: Std_Logic;
Variable address: Unsigned(7 downto 0);
Variable mem_int: Memory_Array(0 to 255) := (
"00100000", "00000001", "00000000", "11110100",
"00100000", "00000010", "00000000", "11111100",
"00100000", "00000011", "00000000", "11111100",
"10100000", "00100010", "00000000", "00000000",
"00100000", "00100001", "00000000", "00000001",
"00100000", "01000010", "00000000", "00000001",
"00010000", "01100001", "00000000", "00000010",
"00010000", "00000000", "00000000", "11111100",
"00100000", "00000001", "00000000", "11110100",
"00100000", "00000010", "00000000", "11111000",
"00100000", "00000011", "00000000", "11111100",
"00000000", "00000000", "00111000", "00100001",
"10000000", "00100100", "00000000", "00000000",
"10000000", "01000101", "00000000", "00000000",
"00000000", "10000101", "00110000", "00100000",
"10100000", "01100110", "00000000", "00000000",
"00100000", "00100001", "00000000", "00000001",
"00100000", "01000010", "00000000", "00000001",
"00100000", "01100011", "00000000", "00000001",
"00010000", "11100011", "00000000", "00000010",
"00010000", "00000000", "00000000", "11111000",
Others => "00000000");
Begin
Wait Until Clock_Mem'Event and Clock_Mem='1';
Case MCmd is
When ocpWR_little =>
If int_SCmdAccept = ocpNULL_little then
int_SCmdAccept := ocpDVA_little;
address := Unsigned(MAddr);
mem_int(to_integer(address)) := MData;
Else
int_SCmdAccept := ocpNULL_little;
End If;
SData <= "ZZZZZZZZ";
When ocpRD_little =>
If int_SCmdAccept = ocpNULL_little then
int_SCmdAccept := ocpDVA_little;
address := Unsigned(MAddr);
SData <= mem_int(to_integer(address));
Else
int_SCmdAccept := ocpNULL_little;
End If;
When Others =>
int_SCmdAccept := ocpNULL_little;
SData <= "ZZZZZZZZ";
End Case;
SCmdAccept <= int_SCmdAccept;
End Process Memory;
DUV: Mips8B
Port Map( Reset_n => Reset_n,
Clock => Clock,
MAddr => MAddr,
MCmd => MCmd,
MData => MData,
SData => SData,
SCmdAccept => SCmdAccept);
End Architecture test_general;
Configuration general_test of test_processor is
For test_general
For DUV: Mips8B Use Configuration Work.Mips8B_struct_conf;
End For;
End For;
End Configuration general_test;
| unlicense | 4659c9b41ae4439a56eb687b31d6f07b | 0.588135 | 3.615181 | false | true | false | false |
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`protect end_protected
| gpl-3.0 | 6121026a3ddb35f4d032245003a2929b | 0.953557 | 1.808746 | false | false | false | false |
rflamino/StellaBlue | core/TIA/src/Common.vhd | 1 | 3,436 | -- TV Interface Adapter (TIA)
-- Copyright 2006, 2010 Retromaster
--
-- This file is part of A2601.
--
-- A2601 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License,
-- or any later version.
--
-- A2601 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with A2601. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package TIA_common is
subtype w_adr is std_logic_vector(5 downto 0);
constant A_VSYNC: w_adr := "000000";
constant A_VBLANK: w_adr := "000001";
constant A_WSYNC: w_adr := "000010";
constant A_RSYNC: w_adr := "000011";
constant A_NUSIZ0: w_adr := "000100";
constant A_NUSIZ1: w_adr := "000101";
constant A_COLUP0: w_adr := "000110";
constant A_COLUP1: w_adr := "000111";
constant A_COLUPF: w_adr := "001000";
constant A_COLUBK: w_adr := "001001";
constant A_CTRLPF: w_adr := "001010";
constant A_REFP0: w_adr := "001011";
constant A_REFP1: w_adr := "001100";
constant A_PF0: w_adr := "001101";
constant A_PF1: w_adr := "001110";
constant A_PF2: w_adr := "001111";
constant A_RESP0: w_adr := "010000";
constant A_RESP1: w_adr := "010001";
constant A_RESM0: w_adr := "010010";
constant A_RESM1: w_adr := "010011";
constant A_RESBL: w_adr := "010100";
constant A_AUDC0: w_adr := "010101";
constant A_AUDC1: w_adr := "010110";
constant A_AUDF0: w_adr := "010111";
constant A_AUDF1: w_adr := "011000";
constant A_AUDV0: w_adr := "011001";
constant A_AUDV1: w_adr := "011010";
constant A_GRP0: w_adr := "011011";
constant A_GRP1: w_adr := "011100";
constant A_ENAM0: w_adr := "011101";
constant A_ENAM1: w_adr := "011110";
constant A_ENABL: w_adr := "011111";
constant A_HMP0: w_adr := "100000";
constant A_HMP1: w_adr := "100001";
constant A_HMM0: w_adr := "100010";
constant A_HMM1: w_adr := "100011";
constant A_HMBL: w_adr := "100100";
constant A_VDELP0: w_adr := "100101";
constant A_VDELP1: w_adr := "100110";
constant A_VDELBL: w_adr := "100111";
constant A_RESMP0: w_adr := "101000";
constant A_RESMP1: w_adr := "101001";
constant A_HMOVE: w_adr := "101010";
constant A_HMCLR: w_adr := "101011";
constant A_CXCLR: w_adr := "101100";
subtype r_adr is std_logic_vector(3 downto 0);
constant A_CXM0P: r_adr := "0000";
constant A_CXM1P: r_adr := "0001";
constant A_CXP0FB: r_adr := "0010";
constant A_CXP1FB: r_adr := "0011";
constant A_CXM0FB: r_adr := "0100";
constant A_CXM1FB: r_adr := "0101";
constant A_CXBLPF: r_adr := "0110";
constant A_CXPPMM: r_adr := "0111";
constant A_INPT0: r_adr := "1000";
constant A_INPT1: r_adr := "1001";
constant A_INPT2: r_adr := "1010";
constant A_INPT3: r_adr := "1011";
constant A_INPT4: r_adr := "1100";
constant A_INPT5: r_adr := "1101";
end TIA_common;
package body TIA_common is
end TIA_common;
| mit | 47cd96300b31147ddecf1a7ac77339bf | 0.613213 | 2.902027 | false | false | false | false |
dskntIndustry/Hardware | hdl_library/Cores/multiplier/signed/signed_multiplier.vhd | 1 | 4,248 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2017 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file signed_multiplier.vhd when simulating
-- the core, signed_multiplier. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY signed_multiplier IS
PORT (
clk : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
p : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END signed_multiplier;
ARCHITECTURE signed_multiplier_a OF signed_multiplier IS
-- synthesis translate_off
COMPONENT wrapped_signed_multiplier
PORT (
clk : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
p : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_signed_multiplier USE ENTITY XilinxCoreLib.mult_gen_v11_2(behavioral)
GENERIC MAP (
c_a_type => 0,
c_a_width => 32,
c_b_type => 0,
c_b_value => "10000001",
c_b_width => 32,
c_ccm_imp => 0,
c_ce_overrides_sclr => 0,
c_has_ce => 0,
c_has_sclr => 0,
c_has_zero_detect => 0,
c_latency => 8,
c_model_type => 0,
c_mult_type => 1,
c_optimize_goal => 1,
c_out_high => 63,
c_out_low => 0,
c_round_output => 0,
c_round_pt => 0,
c_verbosity => 0,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_signed_multiplier
PORT MAP (
clk => clk,
a => a,
b => b,
p => p
);
-- synthesis translate_on
END signed_multiplier_a;
| gpl-3.0 | cc518b7e8d4c991008de8d8da6b695e6 | 0.543785 | 4.683572 | false | false | false | false |
dummylink/plnk_fpga-stack | Examples/xilinx_microblaze/avnet_lx9/pcores/plb_powerlink_v1_00_a/hdl/vhdl/OpenMAC.vhd | 5 | 49,609 | ------------------------------------------------------------------------------------------------------------------------
-- OpenMAC
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Note: Used DPR is specific to Altera/Xilinx. Use one of the following files:
-- OpenMAC_DPR_Altera.vhd
-- OpenMAC_DPR_Xilinx.vhd
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- V0.00-0.30 First generation.
-- 2009-08-07 V0.31 Converted to official version.
-- 2010-04-12 V0.40 zelenkaj Added Auto-Response Delay functionality (TxDel)
-- 2010-06-28 V0.41 zelenkaj Bug Fix: exit sDel if Tx_Off, set Tx_Del_Run without Ipg consideration
-- 2010-08-02 V0.42 zelenkaj Added Timer triggered TX functionality (TxSyncOn)
-- 2011-01-25 V0.43 zelenkaj Changed IPG preload value from 900ns to 960ns
-- 2011-11-28 V0.44 zelenkaj Changed reset level to high-active
-- Clean up
-- Added Dma qualifiers (Rd/Wr done)
-- 2011-12-02 V0.45 zelenkaj Added Dma Request Overflow
-- 2011-12-05 V0.46 zelenkaj Minor change of constants (logic level)
-- 2011-12-23 V0.47 zelenkaj Improvement of Dma Request Overflow determination
------------------------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY OpenMAC IS
GENERIC( HighAdr : IN integer := 16;
Timer : IN boolean := false;
TxSyncOn : IN boolean := false;
TxDel : IN boolean := false;
Simulate : IN boolean := false
);
PORT ( Rst, Clk : IN std_logic;
-- Processor
s_nWr, Sel_Ram, Sel_Cont : IN std_logic := '0';
S_nBe : IN std_logic_vector( 1 DOWNTO 0);
S_Adr : IN std_logic_vector(10 DOWNTO 1);
S_Din : IN std_logic_vector(15 DOWNTO 0);
S_Dout : OUT std_logic_vector(15 DOWNTO 0);
nTx_Int, nRx_Int : OUT std_logic;
nTx_BegInt : OUT std_logic;
-- DMA
Dma_Rd_Done : OUT std_logic;
Dma_Wr_Done : OUT std_logic;
Dma_Req, Dma_Rw : OUT std_logic;
Dma_Ack : IN std_logic;
Dma_Req_Overflow : OUT std_logic;
Dma_Addr : OUT std_logic_vector(HighAdr DOWNTO 1);
Dma_Dout : OUT std_logic_vector(15 DOWNTO 0);
Dma_Din : IN std_logic_vector(15 DOWNTO 0);
-- RMII
rRx_Dat : IN std_logic_vector( 1 DOWNTO 0);
rCrs_Dv : IN std_logic;
rTx_Dat : OUT std_logic_vector( 1 DOWNTO 0);
rTx_En : OUT std_logic;
Hub_Rx : IN std_logic_vector( 1 DOWNTO 0) := "00";
Mac_Zeit : OUT std_logic_vector(31 DOWNTO 0)
);
END ENTITY OpenMAC;
ARCHITECTURE struct OF OpenMAC IS
CONSTANT cInactivated : std_logic := '0';
CONSTANT cActivated : std_logic := '1';
SIGNAL Rx_Dv : std_logic;
SIGNAL R_Req : std_logic;
SIGNAL Auto_Desc : std_logic_vector( 3 DOWNTO 0);
SIGNAL Zeit : std_logic_vector(31 DOWNTO 0);
SIGNAL Tx_Dma_Req, Rx_Dma_Req : std_logic;
SIGNAL Tx_Dma_Ack, Rx_Dma_Ack : std_logic;
SIGNAL Tx_Dma_Req_Overflow : std_logic;
SIGNAL Rx_Dma_Req_Overflow : std_logic;
SIGNAL Tx_Ram_Dat, Rx_Ram_Dat : std_logic_vector(15 DOWNTO 0);
SIGNAL Tx_Reg, Rx_Reg : std_logic_vector(15 DOWNTO 0);
SIGNAL Dma_Tx_Addr, Dma_Rx_Addr : std_logic_vector(Dma_Addr'RANGE);
SIGNAL Tx_Col : std_logic;
SIGNAL Sel_Tx_Ram, Sel_Tx_Reg : std_logic;
SIGNAL Tx_LatchH, Tx_LatchL : std_logic_vector( 7 DOWNTO 0);
BEGIN
S_Dout <= Tx_Ram_Dat WHEN Sel_Ram = '1' AND Sel_Tx_Ram = '1' ELSE
Rx_Ram_Dat WHEN Sel_Ram = '1' ELSE
Tx_Reg WHEN Sel_Cont = '1' AND Sel_Tx_Reg = '1' ELSE
Rx_Reg;
Mac_Zeit <= Zeit;
Dma_Req_Overflow <= Tx_Dma_Req_Overflow or Rx_Dma_Req_Overflow;
b_Dma: BLOCK
SIGNAL Rx_Dma, Tx_Dma : std_logic;
BEGIN
Dma_Req <= '1' WHEN (Tx_Dma_Req = '1' AND Tx_Dma_Ack = '0') OR Rx_Dma_Req = '1' ELSE '0';
Dma_Rw <= '1' WHEN (Rx_Dma = '0' AND Tx_Dma_Req = '1' AND Tx_Dma_Ack = '0') OR Tx_Dma = '1' ELSE '0';
Dma_Addr <= Dma_Tx_Addr WHEN (Rx_Dma = '0' AND Tx_Dma_Req = '1' AND Tx_Dma_Ack = '0') OR Tx_Dma = '1' ELSE Dma_Rx_Addr;
Rx_Dma_Ack <= '1' WHEN Rx_Dma = '1' AND Dma_Ack = '1' ELSE '0';
pDmaArb: PROCESS( Clk, Rst ) IS
BEGIN
IF Rst = '1' THEN
Rx_Dma <= '0'; Tx_Dma <= '0'; Tx_Dma_Ack <= '0';
Tx_LatchH <= (OTHERS => '0'); Tx_LatchL <= (OTHERS => '0');
Zeit <= (OTHERS => '0');
ELSIF rising_edge( Clk ) THEN
IF Timer THEN
Zeit <= Zeit + 1;
END IF;
Sel_Tx_Ram <= s_Adr(8);
Sel_Tx_Reg <= NOT s_Adr(3);
IF Dma_Ack = '0' THEN
IF Rx_Dma = '0' AND Tx_Dma_Req = '1' AND Tx_Dma_Ack = '0' THEN Tx_Dma <= '1';
ELSIF Tx_Dma = '0' AND Rx_Dma_Req = '1' THEN Rx_Dma <= '1';
END IF;
ELSE
IF Rx_Dma = '1' AND Tx_Dma_Req = '1' AND Tx_Dma_Ack = '0' THEN Tx_Dma <= '1'; Rx_Dma <= '0';
ELSIF Tx_Dma = '1' AND Rx_Dma_Req = '1' THEN Tx_Dma <= '0'; Rx_Dma <= '1';
ELSE Tx_Dma <= '0'; Rx_Dma <= '0';
END IF;
END IF;
IF Tx_Dma = '1' AND Dma_Ack = '1' THEN Tx_Dma_Ack <= '1';
ELSE Tx_Dma_Ack <= '0';
END IF;
IF Tx_Dma_Ack = '1' THEN Tx_LatchH <= Dma_Din(15 DOWNTO 8);
Tx_LatchL <= Dma_Din( 7 DOWNTO 0);
END IF;
END IF;
END PROCESS pDmaArb;
END BLOCK b_Dma;
b_Full_Tx: BLOCK
TYPE MACTX_TYPE IS ( R_Idl, R_Bop, R_Pre, R_Txd, R_Crc, R_Col, R_Jam );
SIGNAL Sm_Tx : MACTX_TYPE;
SIGNAL Start_Tx, ClrCol, Tx_On : std_logic;
SIGNAL Dibl_Cnt : std_logic_vector( 1 DOWNTO 0);
SIGNAL F_End, Was_Col, Block_Col : std_logic;
SIGNAL Ipg_Cnt, Tx_Timer : std_logic_vector( 7 DOWNTO 0);
ALIAS Ipg : std_logic IS Ipg_Cnt(7);
ALIAS Tx_Time : std_logic IS Tx_Timer(7);
SIGNAL Tx_Ipg : std_logic_vector( 5 DOWNTO 0);
SIGNAL Tx_Count : std_logic_vector(11 DOWNTO 0);
SIGNAL Tx_En, F_Val, Tx_Half : std_logic;
SIGNAL Tx_Sr, F_TxB : std_logic_vector( 7 DOWNTO 0);
SIGNAL Crc : std_logic_vector(31 DOWNTO 0);
SIGNAL CrcDin, Tx_Dat : std_logic_vector( 1 DOWNTO 0);
SIGNAL Col_Cnt : std_logic_vector( 3 DOWNTO 0);
SIGNAL Auto_Coll : std_logic;
SIGNAL Rnd_Num : std_logic_vector( 9 DOWNTO 0);
SIGNAL Retry_Cnt : std_logic_vector( 9 DOWNTO 0);
SIGNAL Max_Retry : std_logic_vector( 3 DOWNTO 0);
BEGIN
rTx_En <= Tx_En;
rTx_Dat <= Tx_Dat;
pTxSm: PROCESS ( Clk, Rst ) IS
BEGIN
IF Rst = '1' THEN
Sm_Tx <= R_Idl;
ELSIF rising_edge( Clk ) THEN
IF Sm_Tx = R_Idl OR Sm_Tx = R_Bop OR Dibl_Cnt = "11" THEN
CASE Sm_Tx IS
WHEN R_Idl => IF Start_Tx = '1'
AND (Tx_Half = '0' OR Rx_Dv = '0')
AND Ipg = '0' THEN Sm_Tx <= R_Bop; END IF;
WHEN R_Bop => Sm_Tx <= R_Pre;
WHEN R_Pre => IF Tx_Time = '1' THEN Sm_Tx <= R_Txd; END IF;
WHEN R_Txd => IF Was_Col = '1' THEN Sm_Tx <= R_Col;
ELSIF Tx_Count = 0 THEN Sm_Tx <= R_Crc; END IF;
WHEN R_Col => Sm_Tx <= R_Jam;
WHEN R_Jam => IF Tx_Time = '1' THEN Sm_Tx <= R_Idl;
END IF;
WHEN R_Crc => IF Was_Col = '1' THEN Sm_Tx <= R_Col;
ELSIF Tx_Time = '1' THEN Sm_Tx <= R_Idl; END IF;
WHEN OTHERS => NULL;
END CASE;
END IF;
END IF;
END PROCESS pTxSm;
pTxCtl: PROCESS ( Clk, Rst ) IS
VARIABLE Preload : std_logic_vector(Tx_Timer'RANGE);
VARIABLE Load : std_logic;
BEGIN
IF Rst = '1' THEN
Tx_Dat <= "00"; Tx_En <= '0'; Dibl_Cnt <= "00"; F_End <= '0'; F_Val <= '0'; Tx_Col <= '0'; Was_Col <= '0'; Block_Col <= '0';
Ipg_Cnt <= (OTHERS => '0'); Tx_Timer <= (OTHERS => '0'); Tx_Sr <= (OTHERS => '0');
ELSIF rising_edge( Clk ) THEN
IF Sm_Tx = R_Bop THEN Dibl_Cnt <= "00";
ELSE Dibl_Cnt <= Dibl_Cnt + 1;
END IF;
IF Tx_En = '1' THEN Ipg_Cnt <= "1" & conv_std_logic_vector( 44, 7);
ELSIF Rx_Dv = '1' AND Tx_Half = '1' THEN Ipg_Cnt <= "10" & Tx_Ipg;
ELSIF Ipg = '1' THEN Ipg_Cnt <= Ipg_Cnt - 1;
END IF;
IF Dibl_Cnt = "11" AND Sm_Tx = R_Crc AND Tx_Time = '1' THEN F_End <= '1';
ELSIF Dibl_Cnt = "11" AND Sm_Tx = R_Col THEN
IF Col_Cnt = (Max_Retry - 1) THEN F_End <= '1';
ELSIF Col_Cnt < x"E" THEN Tx_Col <= '1';
ELSE F_End <= '1';
END IF;
ELSE F_End <= '0';
Tx_Col <= '0';
END IF;
IF Tx_Half = '1' AND Rx_Dv = '1'
AND (Sm_Tx = R_Pre OR Sm_Tx = R_Txd) THEN Was_Col <= '1';
ELSIF Sm_Tx = R_Col THEN Was_Col <= '0';
END IF;
IF Sm_Tx = R_Col THEN Block_Col <= '1';
ELSIF Auto_Coll = '1' THEN Block_Col <= '0';
ELSIF Retry_Cnt = 0 THEN Block_Col <= '0';
END IF;
IF Dibl_Cnt = "10" AND Sm_Tx = R_Pre AND Tx_Time = '1' THEN F_Val <= '1';
ELSIF Dibl_Cnt = "10" AND Sm_Tx = R_Txd THEN F_Val <= '1';
ELSE F_Val <= '0';
END IF;
Load := '0';
IF Sm_Tx = R_Bop THEN Preload := x"06"; Load := '1';
ELSIF Sm_Tx = R_Txd THEN Preload := x"02"; Load := '1';
ELSIF Sm_Tx = R_Col THEN Preload := x"01"; Load := '1';
ELSIF Tx_Time = '1' THEN Preload := x"3e"; Load := '1';
END IF;
IF Dibl_Cnt = "11" OR Sm_Tx = R_Bop THEN
IF Load = '1' THEN Tx_Timer <= Preload;
ELSE Tx_Timer <= Tx_Timer - 1;
END IF;
END IF;
IF F_Val = '1' THEN Tx_Sr <= F_TxB;
ELSE Tx_Sr <= "00" & Tx_Sr(7 DOWNTO 2);
END IF;
IF Sm_Tx = R_Pre THEN Tx_En <= '1';
ELSIF Sm_Tx = R_Idl OR (Sm_Tx = R_Jam AND Tx_Time = '1') THEN Tx_En <= '0';
END IF;
IF Sm_Tx = R_Pre AND Tx_Time = '1' AND Dibl_Cnt = "11" THEN Tx_Dat <= "11";
ELSIF Sm_Tx = R_Pre THEN Tx_Dat <= "01";
ELSIF Sm_Tx = R_Txd THEN Tx_Dat <= CrcDin;
ELSIF Sm_Tx = R_Crc THEN Tx_Dat <= NOT Crc(30) & NOT Crc(31);
ELSIF Sm_Tx = R_Col OR Sm_Tx = R_Jam THEN Tx_Dat <= "11";
ELSE Tx_Dat <= "00";
END IF;
END IF;
END PROCESS pTxCtl;
pBackDel: PROCESS ( Clk, Rst ) IS
BEGIN
IF Rst = '1' THEN
Rnd_Num <= (OTHERS => '0');
Col_Cnt <= (OTHERS => '0');
Retry_Cnt <= (OTHERS => '0');
ELSIF rising_edge( Clk ) THEN
Rnd_Num <= Rnd_Num(8 DOWNTO 0) & (Rnd_Num(9) XOR NOT Rnd_Num(2));
IF ClrCol = '1' THEN Col_Cnt <= x"0";
ELSIF Dibl_Cnt = "11" AND Sm_Tx = R_Col THEN Col_Cnt <= Col_Cnt + 1;
END IF;
IF Dibl_Cnt = "11" THEN
IF Tx_On = '0' OR Auto_Coll = '1' THEN Retry_Cnt <= (OTHERS => '0');
ELSIF Sm_Tx = R_Col THEN
FOR i IN 0 TO 9 LOOP
IF Col_Cnt >= i THEN Retry_Cnt(i) <= Rnd_Num(i);
ELSE Retry_Cnt(i) <= '0';
END IF;
END LOOP;
ELSIF Sm_Tx /= R_Jam AND Tx_Time = '1' AND Retry_Cnt /= 0 THEN Retry_Cnt <= Retry_Cnt - 1;
END IF;
END IF;
END IF;
END PROCESS pBackDel;
CrcDin <= Tx_Sr(1 DOWNTO 0);
Calc: PROCESS ( Clk, Crc, CrcDin ) IS
VARIABLE H : std_logic_vector(1 DOWNTO 0);
BEGIN
H(0) := Crc(31) XOR CrcDin(0);
H(1) := Crc(30) XOR CrcDin(1);
IF rising_edge( Clk ) THEN
IF Sm_Tx = R_Pre THEN Crc <= x"FFFFFFFF";
ELSIF Sm_Tx = R_Crc THEN Crc <= Crc(29 DOWNTO 0) & "00";
ELSE
Crc( 0) <= H(1);
Crc( 1) <= H(0) XOR H(1);
Crc( 2) <= Crc( 0) XOR H(0) XOR H(1);
Crc( 3) <= Crc( 1) XOR H(0) ;
Crc( 4) <= Crc( 2) XOR H(1);
Crc( 5) <= Crc( 3) XOR H(0) XOR H(1);
Crc( 6) <= Crc( 4) XOR H(0) ;
Crc( 7) <= Crc( 5) XOR H(1);
Crc( 8) <= Crc( 6) XOR H(0) XOR H(1);
Crc( 9) <= Crc( 7) XOR H(0) ;
Crc(10) <= Crc( 8) XOR H(1);
Crc(11) <= Crc( 9) XOR H(0) XOR H(1);
Crc(12) <= Crc(10) XOR H(0) XOR H(1);
Crc(13) <= Crc(11) XOR H(0) ;
Crc(14) <= Crc(12) ;
Crc(15) <= Crc(13) ;
Crc(16) <= Crc(14) XOR H(1);
Crc(17) <= Crc(15) XOR H(0) ;
Crc(18) <= Crc(16) ;
Crc(19) <= Crc(17) ;
Crc(20) <= Crc(18) ;
Crc(21) <= Crc(19) ;
Crc(22) <= Crc(20) XOR H(1);
Crc(23) <= Crc(21) XOR H(0) XOR H(1);
Crc(24) <= Crc(22) XOR H(0) ;
Crc(25) <= Crc(23) ;
Crc(26) <= Crc(24) XOR H(1);
Crc(27) <= Crc(25) XOR H(0) ;
Crc(28) <= Crc(26) ;
Crc(29) <= Crc(27) ;
Crc(30) <= Crc(28) ;
Crc(31) <= Crc(29) ;
END IF;
END IF;
END PROCESS Calc;
bTxDesc: BLOCK
TYPE sDESC IS (sIdle, sLen, sTimL, sTimH, sAdrH, sAdrL, sBegL, sBegH, sDel, sData, sStat, sColl );
SIGNAL Dsm, Tx_Dsm_Next : sDESC;
SIGNAL DescRam_Out, DescRam_In : std_logic_vector(15 DOWNTO 0);
ALIAS TX_LEN : std_logic_vector(11 DOWNTO 0) IS DescRam_Out(11 DOWNTO 0);
ALIAS TX_OWN : std_logic IS DescRam_Out( 8);
ALIAS TX_LAST : std_logic IS DescRam_Out( 9);
ALIAS TX_READY : std_logic IS DescRam_Out(10);
ALIAS TX_BEGDEL : std_logic IS DescRam_Out(12);
ALIAS TX_BEGON : std_logic IS DescRam_Out(13);
ALIAS TX_TIME : std_logic IS DescRam_Out(14);
ALIAS TX_RETRY : std_logic_vector( 3 DOWNTO 0) IS DescRam_Out(3 DOWNTO 0);
SIGNAL Ram_Be : std_logic_vector( 1 DOWNTO 0);
SIGNAL Ram_Wr, Desc_We : std_logic;
SIGNAL Desc_Addr : std_logic_vector( 7 DOWNTO 0);
SIGNAL DescIdx : std_logic_vector( 2 DOWNTO 0);
SIGNAL Last_Desc : std_logic;
SIGNAL ZeitL : std_logic_vector(15 DOWNTO 0);
SIGNAL Tx_Ie, Tx_Wait : std_logic;
SIGNAL Tx_BegInt, Tx_BegSet, Tx_Early : std_logic;
SIGNAL Tx_Del : std_logic;
SIGNAL Ext_Tx, Ext_Ack : std_logic;
SIGNAL Tx_Desc, Tx_Desc_One, Ext_Desc : std_logic_vector( 3 DOWNTO 0);
SIGNAL Tx_Icnt : std_logic_vector( 4 DOWNTO 0);
SIGNAL Tx_SoftInt : std_logic;
SIGNAL Sel_TxH, Sel_TxL, H_Byte : std_logic;
SIGNAL Tx_Buf : std_logic_vector( 7 DOWNTO 0);
SIGNAL Tx_Idle, TxInt, Tx_Beg, Tx_Sync : std_logic;
SIGNAL Tx_Ident : std_logic_vector( 1 DOWNTO 0);
SIGNAL Tx_Cmp_High : std_logic_vector(15 downto 0);
SIGNAL Start_TxS : std_logic;
SIGNAL Tx_Dma_Out : std_logic;
SIGNAL Tx_Del_Cnt : std_logic_vector(32 downto 0);
ALIAS Tx_Del_End : std_logic is Tx_Del_Cnt(Tx_Del_Cnt'high);
SIGNAL Tx_Del_Run : std_logic;
signal Tx_Done : std_logic;
BEGIN
Dma_Rd_Done <= Tx_Done;
Tx_Done <= '1' when Dsm = sStat or Dsm = sColl else '0';
--Read request overflows...
-- * before preamble ends
-- * during transfer before every 8th cycle (halfx) or 4th cycle (fullx)
-- * after exiting crc state (data feteched by dma is not used since crc is calc in hw)
Tx_Dma_Req_Overflow <= '1' when Dibl_Cnt = "01" and Sm_Tx = R_Pre and Tx_Timer(7) = '1' else
'1' when Dibl_Cnt = "10" and Sm_Tx = R_Txd and H_Byte = '0' else
'1' when Dibl_Cnt = "10" and Sm_Tx = R_Crc and Tx_Timer(7) = '1' else
'0';
Ram_Wr <= '1' WHEN s_nWr = '0' AND Sel_Ram = '1' AND s_Adr(10) = '1' ELSE '0';
Ram_Be(1) <= '1' WHEN s_nWr = '1' OR s_nBE(1) = '0' ELSE '0';
Ram_Be(0) <= '1' WHEN s_nWr = '1' OR s_nBE(0) = '0' ELSE '0';
DescIdx <= "000" WHEN Desc_We = '0' AND Tx_Dsm_Next = sIdle ELSE
"000" WHEN Desc_We = '1' AND Dsm = sIdle ELSE
"001" WHEN Desc_We = '0' AND Tx_Dsm_Next = sLen ELSE
"001" WHEN Desc_We = '1' AND Dsm = sLen ELSE
"010" WHEN Desc_We = '0' AND Tx_Dsm_Next = sAdrH ELSE
"010" WHEN Desc_We = '1' AND Dsm = sAdrH ELSE
"011" WHEN Desc_We = '0' AND Tx_Dsm_Next = sAdrL ELSE
"011" WHEN Desc_We = '1' AND Dsm = sAdrL ELSE
"100" WHEN Desc_We = '0' AND Tx_Dsm_Next = sBegH ELSE
"100" WHEN Desc_We = '1' AND Dsm = sBegH ELSE
"101" WHEN Desc_We = '0' AND Tx_Dsm_Next = sBegL ELSE
"101" WHEN Desc_We = '1' AND Dsm = sBegL ELSE
"110" WHEN Desc_We = '0' AND Tx_Dsm_Next = sTimH ELSE
"110" WHEN Desc_We = '1' AND Dsm = sTimH ELSE
"111" WHEN Desc_We = '0' AND Tx_Dsm_Next = sTimL ELSE
"111" WHEN Desc_We = '1' AND Dsm = sTimL ELSE
"111" WHEN Desc_We = '0' AND Tx_Dsm_Next = sData ELSE
"111" WHEN Desc_We = '1' AND Dsm = sData ELSE
"000";
Desc_We <= '1' WHEN Dsm = sTimL OR Dsm = sTimH OR Dsm = sStat ELSE '0';
Desc_Addr <= '1' & Tx_Desc & DescIdx WHEN Ext_Tx = '0' ELSE
'1' & Ext_Desc & DescIdx;
gTxTime: IF Timer GENERATE
DescRam_In <= Zeit(31 DOWNTO 16) WHEN Dsm = sTimH ELSE
ZeitL WHEN Dsm = sTimL ELSE
x"000" & "01" & Tx_Ident WHEN Dsm = sBegL ELSE
Tx_Dma_Out & Tx_Sync & "00" & "0100" & "00" & "0" & "0" & Col_Cnt;
END GENERATE;
gnTxTime: IF NOT Timer GENERATE
DescRam_In <= x"000" & "01" & Tx_Ident WHEN Dsm = sBegL ELSE
Tx_Dma_Out & Tx_Sync & "00" & "0100" & "00" & "0" & "0" & Col_Cnt;
END GENERATE;
RamH: ENTITY work.Dpr_16_16
GENERIC MAP(Simulate => Simulate)
PORT MAP ( CLKA => Clk, CLKB => Clk,
EnA => cActivated, Enb => cActivated,
BEA => Ram_Be,
WEA => Ram_Wr, WEB => Desc_We,
ADDRA => s_Adr(8 DOWNTO 1), ADDRB => Desc_Addr,
DIA => s_Din, DIB => DescRam_In,
DOA => Tx_Ram_Dat, DOB => DescRam_Out
);
ASSERT NOT( TxSyncOn AND NOT Timer )
REPORT "TxSyncOn needs Timer!"
severity failure;
pTxSm: PROCESS( Rst, Clk, Dsm,
Tx_On, TX_OWN, Retry_Cnt, Ext_Tx, Tx_Wait,
Tx_Sync, Sm_Tx, F_End, Tx_Col, Ext_Ack, Tx_Del, Tx_Beg )
BEGIN
Tx_Dsm_Next <= Dsm;
CASE Dsm IS
WHEN sIdle => IF Tx_On = '1' AND TX_OWN = '1' AND Retry_Cnt = 0 THEN
IF (Ext_Tx = '1' AND Ext_Ack = '0') OR Tx_Wait = '0' THEN
Tx_Dsm_Next <= sLen;
END IF;
END IF;
WHEN sLen => IF Tx_Sync = '0' THEN Tx_Dsm_Next <= sAdrH;
ELSE Tx_Dsm_Next <= sBegH;
END IF;
WHEN sBegH => Tx_Dsm_Next <= sBegL;
WHEN sBegL => IF Tx_On = '0' THEN Tx_Dsm_Next <= sIdle;
ELSIF Tx_Sync = '0' THEN
if Tx_Del = '1' then Tx_Dsm_Next <= sDel;
elsIF Sm_Tx = R_Pre THEN
Tx_Dsm_Next <= sTimH;
END IF;
ELSIF Tx_Beg = '1' THEN Tx_Dsm_Next <= sAdrH;
END IF;
WHEN sDel => IF Tx_On = '0' THEN Tx_Dsm_Next <= sIdle; --avoid FSM hang
ELSIF Tx_Del_End = '1' THEN Tx_Dsm_Next <= sTimH;
END IF;
WHEN sAdrH => Tx_Dsm_Next <= sAdrL;
WHEN sAdrL => IF Tx_On = '0' THEN Tx_Dsm_Next <= sIdle;
elsif Tx_Del = '1' then Tx_Dsm_Next <= sBegH;
ELSIF Tx_Sync = '0' THEN Tx_Dsm_Next <= sBegL;
ELSIF Sm_Tx = R_Bop THEN Tx_Dsm_Next <= sTimH;
END IF;
WHEN sTimH => Tx_Dsm_Next <= sTimL;
WHEN sTimL => Tx_Dsm_Next <= sData;
WHEN sData => IF F_End = '1' THEN Tx_Dsm_Next <= sStat;
ELSIF Tx_Col = '1' THEN Tx_Dsm_Next <= sColl;
END IF;
WHEN sStat => Tx_Dsm_Next <= sIdle;
WHEN sColl => if sm_tx = r_idl then
if Tx_Sync = '1' then Tx_Dsm_Next <= sStat;
else Tx_Dsm_Next <= sIdle;
end if;
end if;
WHEN OTHERS =>
END CASE;
IF Rst = '1' THEN Dsm <= sIdle;
ELSIF rising_edge( Clk ) THEN Dsm <= Tx_Dsm_Next;
END IF;
END PROCESS pTxSm;
pTxControl: PROCESS( Rst, Clk )
BEGIN
IF Rst = '1' THEN
Last_Desc <= '0'; Start_TxS <= '0'; Tx_Dma_Req <= '0'; H_Byte <= '0';
Tx_Beg <= '0'; Tx_BegSet <= '0'; Tx_Early <= '0'; Auto_Coll <= '0'; Tx_Dma_Out <= '0';
Ext_Tx <= '0'; Ext_Ack <= '0'; ClrCol <= '0'; Ext_Desc <= (OTHERS => '0'); Tx_Sync <= '0'; Max_Retry <= (others => '0');
ZeitL <= (OTHERS => '0'); Tx_Count <= (OTHERS => '0'); Tx_Ident <= "00";
Dma_Tx_Addr <= (OTHERS => '0'); Tx_Cmp_High <= (others => '0');
Tx_Del_Run <= '0';
Tx_Del <= '0'; Tx_Del_Cnt <= (others => '0');
ELSIF rising_edge( Clk ) THEN
IF TxSyncOn = true THEN
IF Tx_Sync = '1' AND Dsm = sBegL AND (Tx_Cmp_High & DescRam_Out) = Zeit THEN Tx_Beg <= '1';
ELSE Tx_Beg <= '0';
END IF;
END IF;
IF Dsm = sStat AND Desc_We = '1' THEN ClrCol <= '1';
ELSE ClrCol <= '0';
END IF;
IF Timer THEN
IF Dsm = sTimH THEN ZeitL <= Zeit(15 DOWNTO 0);
END IF;
END IF;
IF Ext_Ack = '0' AND R_Req = '1' THEN Ext_Desc <= Auto_Desc;
Ext_Ack <= '1';
ELSIF Ext_Tx = '1' OR Tx_On = '0' THEN Ext_Ack <= '0';
END IF;
IF Dsm = sIdle AND Ext_Ack = '1' THEN Ext_Tx <= '1';
ELSIF Dsm = sStat OR Tx_Col = '1' OR Tx_On = '0' THEN Ext_Tx <= '0';
END IF;
IF (F_End = '1' OR Tx_On = '0'
OR (Tx_Col = '1' AND Ext_Tx = '1' )
OR dsm = sColl ) THEN Start_TxS <= '0';
Auto_Coll <= Auto_Coll OR (Tx_Col AND Ext_Tx);
ELSIF Dsm = sAdrH and Tx_Del = '0' THEN Start_TxS <= '1';
ELSIF Dsm = sDel and Tx_Del_End = '1' THEN Start_TxS <= '1';
ELSIF Sm_Tx = R_Idl THEN Auto_Coll <= '0';
END IF;
IF Dsm = sIdle THEN Last_Desc <= TX_LAST;
END IF;
IF Dsm = sLen THEN Tx_Count <= TX_LEN;
ELSIF F_Val = '1' THEN Tx_Count <= Tx_Count - 1;
END IF;
IF Dsm = sBegH THEN Tx_Cmp_High <= DescRam_Out;
END IF;
IF Dsm = sIdle AND Tx_On = '1' AND TX_OWN = '1' AND Retry_Cnt = 0 THEN
IF Ext_Tx = '1' OR Tx_Wait = '0' THEN
IF TxSyncOn THEN Tx_Sync <= TX_TIME;
ELSE Tx_Sync <= '0';
END IF;
Max_Retry <= TX_RETRY;
Tx_Early <= TX_BEGON;
IF TxDel = true THEN Tx_Del <= TX_BEGDEL;
END IF;
END IF;
ELSIF Dsm = sTimH THEN Tx_BegSet <= Tx_Early;
ELSIF Dsm = sTimL THEN Tx_BegSet <= '0';
ELSIF Dsm = sIdle THEN Tx_Del <= '0';
END IF;
if TxDel = true and Tx_Del = '1' then
if Dsm = sBegH then Tx_Del_Cnt(Tx_Del_Cnt'high) <= '0';
Tx_Del_Cnt(31 downto 16) <= DescRam_Out;
elsif Dsm = sBegL then Tx_Del_Cnt(15 downto 0) <= DescRam_Out;
elsif Dsm = sDel and Tx_Del_Run = '1' then Tx_Del_Cnt <= Tx_Del_Cnt - 1;
end if;
if Tx_Del_Run = '0' and Dsm = sDel then Tx_Del_Run <= '1'; --don't consider Ipg
elsif Tx_Del_End = '1' then Tx_Del_Run <= '0';
end if;
end if;
IF Dsm = sAdrL THEN Dma_Tx_Addr(15 DOWNTO 1) <= DescRam_Out(15 DOWNTO 1);
ELSIF Tx_Dma_Ack = '1' THEN Dma_Tx_Addr(15 DOWNTO 1) <= Dma_Tx_Addr(15 DOWNTO 1) + 1;
END IF;
IF Dsm = sAdrH THEN
Dma_Tx_Addr(Dma_Addr'high DOWNTO 16) <= DescRam_Out(Dma_Addr'high-16 DOWNTO 0);
Tx_Ident <= DescRam_Out(15 DOWNTO 14);
ELSIF Tx_Dma_Ack = '1' AND Dma_Tx_Addr(15 DOWNTO 1) = x"FFF" & "111" THEN
Dma_Tx_Addr(Dma_Addr'high DOWNTO 16) <= Dma_Tx_Addr(Dma_Addr'high DOWNTO 16) + 1;
END IF;
IF DSM = sAdrL
OR (F_Val = '1' AND H_Byte = '0') THEN Tx_Dma_Req <= '1' AFTER 0 nS;
ELSIF Tx_Dma_Ack = '1' THEN Tx_Dma_Req <= '0';
END IF;
IF Sm_Tx = R_Bop THEN H_Byte <= '0';
ELSIF F_Val = '1' THEN H_Byte <= NOT H_Byte;
END IF;
IF F_Val = '1' THEN Tx_Buf <= Tx_LatchL;
END IF;
if H_Byte = '0' and F_Val = '1' and Tx_Dma_Req = '1' then Tx_Dma_Out <= '1';
elsif Sm_Tx = R_Bop then Tx_Dma_Out <= '0';
end if;
END IF;
END PROCESS pTxControl;
Start_Tx <= '1' WHEN Start_TxS = '1' AND Block_Col = '0' ELSE
'1' WHEN not TxDel and not TxSyncOn and R_Req = '1' ELSE
'0';
F_TxB <= Tx_LatchH WHEN H_Byte = '0' ELSE
Tx_Buf;
nTx_Int <= '1' WHEN (Tx_Icnt = 0 AND Tx_SoftInt = '0') OR Tx_Ie = '0' ELSE '0';
Tx_Idle <= '1' WHEN Sm_Tx = R_Idl AND Dsm = sIdle ELSE '0';
Tx_Reg(15 DOWNTO 4) <= Tx_Ie & Tx_SoftInt & Tx_Half & Tx_Wait & (Tx_Icnt(4) OR Tx_Icnt(3)) & Tx_Icnt(2 DOWNTO 0)
& Tx_On & Tx_BegInt & Tx_Idle & "0" ;
Tx_Reg( 3 DOWNTO 0) <= Tx_Desc;
Sel_TxH <= '1' WHEN s_nWr = '0' AND Sel_Cont = '1' AND s_Adr(3) = '0' AND Ram_Be(1) = '1' ELSE '0';
Sel_TxL <= '1' WHEN s_nWr = '0' AND Sel_Cont = '1' AND s_Adr(3) = '0' AND Ram_Be(0) = '1' ELSE '0';
Tx_Desc <= Tx_Desc_One;
Tx_SoftInt <= '0';
pTxRegs: PROCESS( Rst, Clk )
BEGIN
IF Rst = '1' THEN
Tx_On <= '0'; Tx_Ie <= '0'; Tx_Half <= '0'; Tx_Wait <= '0'; nTx_BegInt <= '0';
Tx_Desc_One <= (OTHERS => '0');
Tx_Icnt <= (OTHERS => '0'); TxInt <= '0'; Tx_BegInt <= '0';
Tx_Ipg <= conv_std_logic_vector( 42, 6);
ELSIF rising_edge( Clk ) THEN
IF Sel_TxL = '1' THEN
IF s_Adr(2 DOWNTO 1) = "00" THEN Tx_On <= S_Din( 7);
ELSIF s_Adr(2 DOWNTO 1) = "01" AND S_Din( 7) = '1' THEN Tx_On <= '1';
ELSIF s_Adr(2 DOWNTO 1) = "10" AND S_Din( 7) = '1' THEN Tx_On <= '0';
END IF;
END IF;
IF Tx_BegSet = '1' AND Tx_Ie = '1' THEN Tx_BegInt <= '1';
ELSIF Sel_TxL = '1' AND s_Adr(2 DOWNTO 1) = "01" AND S_Din( 6) = '1' THEN Tx_BegInt <= '1';
ELSIF Sel_TxL = '1' AND s_Adr(2 DOWNTO 1) = "10" AND S_Din( 6) = '1' THEN Tx_BegInt <= '0';
END IF;
nTx_BegInt <= NOT Tx_BegInt;
IF Sel_TxL = '1' AND s_Adr(2 DOWNTO 1) = "11" THEN Tx_Desc_One <= S_Din( 3 DOWNTO 0);
ELSIF Dsm = sStat AND Ext_Tx = '0' THEN
IF Last_Desc = '1' THEN Tx_Desc_One <= x"0";
ELSE Tx_Desc_One <= Tx_Desc + 1;
END IF;
END IF;
IF Sel_TxH = '1' THEN
IF s_Adr(2 DOWNTO 1) = "00" THEN Tx_Ie <= S_Din(15);
ELSIF s_Adr(2 DOWNTO 1) = "01" AND S_Din(15) = '1' THEN Tx_Ie <= '1';
ELSIF s_Adr(2 DOWNTO 1) = "10" AND S_Din(15) = '1' THEN Tx_Ie <= '0';
END IF;
END IF;
IF Sel_TxH = '1' THEN
IF s_Adr(2 DOWNTO 1) = "00" THEN Tx_Half <= S_Din(13);
ELSIF s_Adr(2 DOWNTO 1) = "01" AND S_Din(13) = '1' THEN Tx_Half <= '1';
ELSIF s_Adr(2 DOWNTO 1) = "10" AND S_Din(13) = '1' THEN Tx_Half <= '0';
END IF;
END IF;
IF Sel_TxH = '1' THEN
IF s_Adr(2 DOWNTO 1) = "00" THEN Tx_Wait <= S_Din(12);
ELSIF s_Adr(2 DOWNTO 1) = "01" AND S_Din(12) = '1' THEN Tx_Wait <= '1';
ELSIF s_Adr(2 DOWNTO 1) = "10" AND S_Din(12) = '1' THEN Tx_Wait <= '0';
END IF;
END IF;
IF Sel_TxH = '1' THEN
IF s_Adr(2 DOWNTO 1) = "11" AND S_Din(14) = '1' THEN Tx_Ipg <= S_Din(13 DOWNTO 8);
END IF;
END IF;
IF Tx_Ie = '1' AND Dsm = sStat AND Desc_We = '1' THEN TxInt <= '1';
ELSE TxInt <= '0';
END IF;
IF Sel_TxH = '1' AND s_Adr(2 DOWNTO 1) = "10" AND S_Din(8) = '1'
AND Tx_Icnt /= 0 THEN Tx_Icnt <= Tx_Icnt - NOT TxInt;
ELSIF TxInt = '1' AND Tx_Icnt /= "11111" THEN Tx_Icnt <= Tx_Icnt + 1;
END IF;
END IF;
END PROCESS pTxRegs;
END BLOCK bTxDesc;
END BLOCK b_Full_Tx;
b_Full_Rx: BLOCK
TYPE MACRX_TYPE IS ( R_Idl, R_Sof, R_Rxd );
SIGNAL Sm_Rx : MACRX_TYPE;
SIGNAL Rx_Dat, Rx_DatL : std_logic_vector( 1 DOWNTO 0);
SIGNAL Tx_Timer : std_logic_vector( 7 DOWNTO 0);
SIGNAL Dibl_Cnt : std_logic_vector( 1 DOWNTO 0);
SIGNAL Crc, nCrc : std_logic_vector(31 DOWNTO 0);
SIGNAL CrcDin : std_logic_vector( 1 DOWNTO 0);
SIGNAL F_Err, P_Err, N_Err, A_Err : std_logic;
SIGNAL F_End, F_Val, Rx_Beg : std_logic;
SIGNAL Rx_Sr : std_logic_vector( 7 DOWNTO 0);
SIGNAL nCrc_Ok, Crc_Ok : std_logic;
SIGNAL WrDescStat : std_logic;
SIGNAL PreCount : std_logic_vector( 4 DOWNTO 0);
SIGNAL PreBeg, PreErr : std_logic;
SIGNAL Rx_DvL : std_logic;
SIGNAL Diag : std_logic;
BEGIN
Rx_Beg <= '1' WHEN Rx_Dv = '1' AND Sm_Rx = R_SOF AND Rx_Dat = "11" ELSE '0';
nCrc_Ok <= '1' WHEN nCrc = x"C704DD7B" ELSE '0';
rxsm: PROCESS ( Clk, Rst ) IS
BEGIN
IF Rst = '1' THEN
Sm_Rx <= R_Idl;
ELSIF rising_edge( Clk ) THEN
IF Sm_Rx = R_Idl OR Sm_Rx = R_Rxd OR Sm_Rx = R_Sof OR Dibl_Cnt = "11" THEN
CASE Sm_Rx IS
WHEN R_Idl => IF Rx_Dv = '1' THEN Sm_Rx <= R_Sof; END IF;
WHEN R_Sof => IF Rx_Dat = "11" THEN Sm_Rx <= R_Rxd;
ELSIF Rx_Dv = '0' THEN Sm_Rx <= R_Idl; END IF;
WHEN R_Rxd => IF Rx_Dv = '0' THEN Sm_Rx <= R_Idl; END IF;
WHEN OTHERS => NULL;
END CASE;
END IF;
END IF;
END PROCESS rxsm;
pRxCtl: PROCESS ( Clk, Rst ) IS
VARIABLE Preload : std_logic_vector(Tx_Timer'RANGE);
VARIABLE Load : std_logic;
BEGIN
IF Rst = '1' THEN
Rx_DatL <= "00"; Rx_Dat <= "00"; Rx_Dv <= '0'; Dibl_Cnt <= "00"; PreCount <= (OTHERS => '0');
F_End <= '0'; F_Err <= '0'; F_Val <= '0'; Crc_Ok <= '0';
A_Err <= '0'; N_Err <= '0'; P_Err <= '0'; PreBeg <= '0'; PreErr <= '0';
ELSIF rising_edge( Clk ) THEN
Rx_DatL <= rRx_Dat;
Rx_Dat <= Rx_DatL;
IF Rx_Dv = '0' AND rCrs_Dv = '1' THEN Rx_Dv <= '1';
ELSIF Rx_Dv = '1' AND rCrs_Dv = '0' AND Dibl_Cnt(0) = '1' THEN Rx_Dv <= '0';
END IF;
IF Rx_Beg = '1' THEN Dibl_Cnt <= "00";
ELSE Dibl_Cnt <= Dibl_Cnt + 1;
END IF;
Crc_Ok <= nCrc_Ok;
IF (Sm_Rx = R_Rxd AND Rx_Dv = '0') THEN F_End <= '1';
F_Err <= NOT Crc_Ok;
ELSE F_End <= '0';
END IF;
IF Dibl_Cnt = "11" AND Sm_Rx = R_Rxd THEN F_Val <= '1';
ELSE F_Val <= '0';
END IF;
IF WrDescStat = '1' THEN A_Err <= '0';
ELSIF F_End = '1' AND Dibl_Cnt /= 1 THEN A_Err <= '1';
END IF;
IF Rx_Dv = '0' OR Rx_Dat(0) = '0' THEN PreCount <= (OTHERS => '1');
ELSE PreCount <= PreCount - 1;
END IF;
IF Rx_Dv = '0' THEN PreBeg <= '0';
ELSIF Rx_Dat = "01" THEN PreBeg <= '1';
END IF;
IF WrDescStat = '1' THEN N_Err <= '0';
ELSIF Sm_Rx = R_Sof AND Rx_Dv = '0' THEN N_Err <= '1';
END IF;
IF Rx_DvL = '0' THEN PreErr <= '0';
ELSIF PreBeg = '0' AND (Rx_Dat = "10" OR Rx_Dat = "11") THEN PreErr <= '1';
ELSIF PreBeg = '1' AND (Rx_Dat = "10" OR Rx_Dat = "00") THEN PreErr <= '1';
END IF;
IF WrDescStat = '1' THEN P_Err <= '0';
ELSIF Rx_Beg = '1' AND PreErr = '1' THEN P_Err <= '1';
ELSIF Rx_Beg = '1' AND PreCount /= 0 THEN P_Err <= '1';
END IF;
Rx_Sr <= Rx_Dat(1) & Rx_Dat(0) & Rx_Sr(7 DOWNTO 2);
Rx_DvL <= Rx_Dv;
END IF;
END PROCESS pRxCtl;
CrcDin <= Rx_Dat;
Calc: PROCESS ( Clk, Crc, nCrc, CrcDin, Sm_Rx ) IS
VARIABLE H : std_logic_vector(1 DOWNTO 0);
BEGIN
H(0) := Crc(31) XOR CrcDin(0);
H(1) := Crc(30) XOR CrcDin(1);
IF Sm_Rx = R_Sof THEN nCrc <= x"FFFFFFFF";
ELSE
nCrc( 0) <= H(1);
nCrc( 1) <= H(0) XOR H(1);
nCrc( 2) <= Crc( 0) XOR H(0) XOR H(1);
nCrc( 3) <= Crc( 1) XOR H(0) ;
nCrc( 4) <= Crc( 2) XOR H(1);
nCrc( 5) <= Crc( 3) XOR H(0) XOR H(1);
nCrc( 6) <= Crc( 4) XOR H(0) ;
nCrc( 7) <= Crc( 5) XOR H(1);
nCrc( 8) <= Crc( 6) XOR H(0) XOR H(1);
nCrc( 9) <= Crc( 7) XOR H(0) ;
nCrc(10) <= Crc( 8) XOR H(1);
nCrc(11) <= Crc( 9) XOR H(0) XOR H(1);
nCrc(12) <= Crc(10) XOR H(0) XOR H(1);
nCrc(13) <= Crc(11) XOR H(0) ;
nCrc(14) <= Crc(12) ;
nCrc(15) <= Crc(13) ;
nCrc(16) <= Crc(14) XOR H(1);
nCrc(17) <= Crc(15) XOR H(0) ;
nCrc(18) <= Crc(16) ;
nCrc(19) <= Crc(17) ;
nCrc(20) <= Crc(18) ;
nCrc(21) <= Crc(19) ;
nCrc(22) <= Crc(20) XOR H(1);
nCrc(23) <= Crc(21) XOR H(0) XOR H(1);
nCrc(24) <= Crc(22) XOR H(0) ;
nCrc(25) <= Crc(23) ;
nCrc(26) <= Crc(24) XOR H(1);
nCrc(27) <= Crc(25) XOR H(0) ;
nCrc(28) <= Crc(26) ;
nCrc(29) <= Crc(27) ;
nCrc(30) <= Crc(28) ;
nCrc(31) <= Crc(29) ;
END IF;
IF rising_edge( Clk ) THEN
Crc <= nCrc;
END IF;
END PROCESS Calc;
bRxDesc: BLOCK
TYPE sDESC IS (sIdle, sLen, sTimL, sTimH, sAdrH, sAdrL, sData, sOdd, sStat, sLenW );
SIGNAL Dsm, Rx_Dsm_Next : sDESC;
SIGNAL Rx_Buf, Rx_LatchH, Rx_LatchL : std_logic_vector( 7 DOWNTO 0);
SIGNAL Rx_Ovr : std_logic;
SIGNAL DescRam_Out, DescRam_In : std_logic_vector(15 DOWNTO 0);
ALIAS RX_LEN : std_logic_vector(11 DOWNTO 0) IS DescRam_Out(11 DOWNTO 0);
ALIAS RX_OWN : std_logic IS DescRam_Out( 8);
ALIAS RX_LAST : std_logic IS DescRam_Out( 9);
SIGNAL Ram_Be : std_logic_vector( 1 DOWNTO 0);
SIGNAL Ram_Wr, Desc_We : std_logic;
SIGNAL Desc_Addr : std_logic_vector( 7 DOWNTO 0);
SIGNAL ZeitL : std_logic_vector(15 DOWNTO 0);
SIGNAL Rx_On, Rx_Ie, Sel_RxH, Sel_RxL : std_logic;
SIGNAL Rx_Desc, Match_Desc : std_logic_vector( 3 DOWNTO 0);
SIGNAL Rx_Icnt : std_logic_vector( 4 DOWNTO 0);
SIGNAL Rx_Lost, Last_Desc, Answer_Tx : std_logic;
SIGNAL DescIdx : std_logic_vector( 2 DOWNTO 0);
SIGNAL Rx_Count, Rx_Limit : std_logic_vector(11 DOWNTO 0);
SIGNAL Match, Filt_Cmp : std_logic;
SIGNAL Rx_Idle, RxInt : std_logic;
SIGNAL Hub_Rx_L : std_logic_vector( 1 DOWNTO 0);
SIGNAL Rx_Dma_Out : std_logic;
signal Rx_Done : std_logic;
BEGIN
Rx_Done <= '1' when Dsm /= sIdle and Rx_Dsm_Next = sIdle else '0';
Dma_Wr_Done <= Rx_Done;
Rx_Dma_Req_Overflow <= '1' when Dsm = sOdd and Rx_Ovr = '0' else
'1' when Dsm = sData and Rx_Ovr = '0' and F_Val = '1' and Rx_Count(0) = '1' and RX_Count > 1 else
'1' when Rx_Done = '1' else
'0';
WrDescStat <= '1' WHEN Dsm = sStat ELSE '0';
Ram_Wr <= '1' WHEN s_nWr = '0' AND Sel_Ram = '1' AND s_Adr(10) = '1' ELSE '0';
Ram_Be(1) <= '1' WHEN s_nWr = '1' OR s_nBE(1) = '0' ELSE '0';
Ram_Be(0) <= '1' WHEN s_nWr = '1' OR s_nBE(0) = '0' ELSE '0';
DescIdx <= "001" WHEN Desc_We = '0' AND (Rx_Dsm_Next = sLen OR Rx_Dsm_Next = sLenW) ELSE
"001" WHEN Desc_We = '1' AND (Dsm = sLen OR Dsm = sLenW) ELSE
"010" WHEN Desc_We = '0' AND Rx_Dsm_Next = sAdrH ELSE
"010" WHEN Desc_We = '1' AND Dsm = sAdrH ELSE
"011" WHEN Desc_We = '0' AND Rx_Dsm_Next = sAdrL ELSE
"011" WHEN Desc_We = '1' AND Dsm = sAdrL ELSE
"110" WHEN Desc_We = '0' AND Rx_Dsm_Next = sTimH ELSE
"110" WHEN Desc_We = '1' AND Dsm = sTimH ELSE
"111" WHEN Desc_We = '0' AND Rx_Dsm_Next = sTimL ELSE
"111" WHEN Desc_We = '1' AND Dsm = sTimL ELSE
"000";
Desc_We <= '1' WHEN Dsm = sTimL OR Dsm = sTimH ELSE
'1' WHEN (Dsm = sLenW OR Dsm = sStat) AND Match = '1' ELSE '0';
Desc_Addr <= "0" & Rx_Desc & DescIdx;
gRxTime: IF timer GENERATE
DescRam_In <= Zeit(31 DOWNTO 16) WHEN Dsm = sTimH ELSE
ZeitL WHEN Dsm = sTimL ELSE
x"0" & Rx_Count WHEN Dsm = sLenW ELSE
Rx_Dma_Out & '0' & "0" & A_Err & Hub_Rx_L & "00" & Match_Desc & N_Err & P_Err & Rx_Ovr & F_Err;
END GENERATE;
ngRxTime: IF NOT timer GENERATE
DescRam_In <= x"0" & Rx_Count WHEN Dsm = sLenW ELSE
Rx_Dma_Out & '0' & "0" & A_Err & Hub_Rx_L & "00" & Match_Desc & N_Err & P_Err & Rx_Ovr & F_Err;
END GENERATE;
RxRam: ENTITY work.Dpr_16_16
GENERIC MAP(Simulate => Simulate)
PORT MAP ( CLKA => Clk, CLKB => Clk,
EnA => cActivated, Enb => cActivated,
BEA => Ram_Be,
WEA => Ram_Wr, WEB => Desc_We,
ADDRA => s_Adr(8 DOWNTO 1), ADDRB => Desc_Addr,
DIA => s_Din, DIB => DescRam_In,
DOA => Rx_Ram_Dat, DOB => DescRam_Out
);
pRxSm: PROCESS( Rst, Clk, Dsm,
Rx_Beg, Rx_On, RX_OWN, F_End, F_Err, Diag, Rx_Count )
BEGIN
Rx_Dsm_Next <= Dsm;
CASE Dsm IS
WHEN sIdle => IF Rx_Beg = '1' AND Rx_On = '1' AND RX_OWN = '1' THEN
Rx_Dsm_Next <= sLen;
END IF;
WHEN sLen => Rx_Dsm_Next <= sAdrH;
WHEN sAdrH => Rx_Dsm_Next <= sAdrL;
WHEN sAdrL => Rx_Dsm_Next <= sTimH;
WHEN sTimH => Rx_Dsm_Next <= sTimL;
WHEN sTimL => Rx_Dsm_Next <= sData;
WHEN sData => IF F_End = '1' THEN
IF F_Err = '0'
OR Diag = '1' THEN Rx_Dsm_Next <= sStat;
ELSE Rx_Dsm_Next <= sIdle;
END IF;
END IF;
WHEN sStat => Rx_Dsm_Next <= sLenW;
WHEN sLenW => IF Rx_Count(0) = '0' THEN
Rx_Dsm_Next <= sIdle;
ELSE Rx_Dsm_Next <= sOdd;
END IF;
WHEN sOdd => Rx_Dsm_Next <= sIdle;
WHEN OTHERS =>
END CASE;
IF Rst = '1' THEN Dsm <= sIdle;
ELSIF rising_edge( Clk ) THEN Dsm <= Rx_Dsm_Next;
END IF;
END PROCESS pRxSm;
pRxControl: PROCESS( Rst, Clk )
BEGIN
IF Rst = '1' THEN
Rx_Ovr <= '0'; Rx_Dma_Req <= '0'; Last_Desc <= '0'; Rx_Dma_Out <= '0';
Rx_Count <= (OTHERS => '0');
Rx_Buf <= (OTHERS => '0'); Rx_LatchL <= (OTHERS => '0'); Rx_LatchH <= (OTHERS => '0');
Dma_Rx_Addr <= (OTHERS => '0');
ELSIF rising_edge( Clk ) THEN
IF Timer THEN
IF Dsm = sTimH THEN ZeitL <= Zeit(15 DOWNTO 0);
END IF;
END IF;
IF Dsm = sIdle THEN Rx_Count <= (OTHERS => '0');
Last_Desc <= RX_LAST;
ELSIF F_Val = '1' THEN Rx_Count <= Rx_Count + 1;
END IF;
IF Dsm = sLen THEN Rx_Limit <= RX_LEN;
Hub_Rx_L <= Hub_Rx;
END IF;
IF F_Val = '1' THEN Rx_Buf <= Rx_Sr;
END IF;
IF (F_Val = '1' AND Rx_Count(0) = '1') OR Dsm = sStat THEN Rx_LatchH <= Rx_Buf;
Rx_LatchL <= Rx_Sr;
IF Rx_Dma_Req = '1' AND Sm_Rx /= R_Idl THEN Rx_Dma_Out <= '1';
END IF;
ELSIF Dsm = sLen THEN Rx_Dma_Out <= '0';
END IF;
IF Dsm = sLen THEN Rx_Ovr <= '0';
ELSIF F_Val = '1' AND Rx_Limit = Rx_Count THEN Rx_Ovr <= '1';
END IF;
IF Dsm = sAdrL THEN Dma_Rx_Addr(15 DOWNTO 1) <= DescRam_Out(15 DOWNTO 1);
ELSIF Rx_Dma_Ack = '1' THEN Dma_Rx_Addr(15 DOWNTO 1) <= Dma_Rx_Addr(15 DOWNTO 1) + 1;
END IF;
IF Dsm = sAdrH THEN
Dma_Rx_Addr(Dma_Addr'high DOWNTO 16) <= DescRam_Out(Dma_Addr'high-16 DOWNTO 0);
ELSIF Rx_Dma_Ack = '1' AND Dma_Rx_Addr(15 DOWNTO 1) = x"FFF" & "111" THEN
Dma_Rx_Addr(Dma_Addr'high DOWNTO 16) <= Dma_Rx_Addr(Dma_Addr'high DOWNTO 16) + 1;
END IF;
IF Filt_Cmp = '0' AND Match ='0' THEN Rx_Dma_Req <= '0';
ELSIF (Dsm = sOdd AND Rx_Ovr = '0')
OR (Dsm = sData AND Rx_Ovr = '0' AND F_Val = '1' AND Rx_Count(0) = '1') THEN Rx_Dma_Req <= '1' AFTER 101 nS;
ELSIF Rx_Dma_Ack = '1' THEN Rx_Dma_Req <= '0';
END IF;
END IF;
END PROCESS pRxControl;
Dma_Dout <= Rx_LatchH & Rx_LatchL;
nRx_Int <= '1' WHEN Rx_Icnt = 0 OR Rx_Ie = '0' ELSE '0';
Rx_Idle <= '1' WHEN Sm_Rx = R_Idl ELSE '0';
Rx_Reg(15 DOWNTO 4) <= Rx_Ie & '0' & "0" & '0' & (Rx_Icnt(4) OR Rx_Icnt(3)) & Rx_Icnt(2 DOWNTO 0)
& Rx_On & "0" & Rx_Idle & Rx_Lost;
Rx_Reg( 3 DOWNTO 0) <= Rx_Desc;
bFilter: BLOCK
SIGNAL Ram_Addr : std_logic_vector( 7 DOWNTO 0);
SIGNAL Ram_BeH, Ram_BeL : std_logic_vector( 1 DOWNTO 0);
SIGNAL Ram_Wr : std_logic;
SIGNAL Filter_Addr : std_logic_vector( 6 DOWNTO 0);
SIGNAL Filter_Out_H, Filter_Out_L : std_logic_vector(31 DOWNTO 0);
ALIAS DIRON_0 : std_logic IS Filter_Out_H( 11);
ALIAS DIRON_1 : std_logic IS Filter_Out_H( 27);
ALIAS DIRON_2 : std_logic IS Filter_Out_L( 11);
ALIAS DIRON_3 : std_logic IS Filter_Out_L( 27);
ALIAS TX_0 : std_logic IS Filter_Out_H( 7);
ALIAS TX_1 : std_logic IS Filter_Out_H(23);
ALIAS TX_2 : std_logic IS Filter_Out_L( 7);
ALIAS TX_3 : std_logic IS Filter_Out_L(23);
ALIAS ON_0 : std_logic IS Filter_Out_H( 6);
ALIAS ON_1 : std_logic IS Filter_Out_H(22);
ALIAS ON_2 : std_logic IS Filter_Out_L( 6);
ALIAS ON_3 : std_logic IS Filter_Out_L(22);
ALIAS DESC_0 : std_logic_vector( 3 DOWNTO 0) IS Filter_Out_H( 3 DOWNTO 0);
ALIAS DESC_1 : std_logic_vector( 3 DOWNTO 0) IS Filter_Out_H(19 DOWNTO 16);
ALIAS DESC_2 : std_logic_vector( 3 DOWNTO 0) IS Filter_Out_L( 3 DOWNTO 0);
ALIAS DESC_3 : std_logic_vector( 3 DOWNTO 0) IS Filter_Out_L(19 DOWNTO 16);
SIGNAL Byte_Cnt : std_logic_vector( 4 DOWNTO 0) := (OTHERS => '0');
SIGNAL Erg0, Erg1, Erg2, Erg3 : std_logic_vector( 7 DOWNTO 0);
SIGNAL Mat_Reg : std_logic_vector(15 DOWNTO 0);
SIGNAL Filt_Idx : std_logic_vector( 1 DOWNTO 0);
SIGNAL Mat_Sel : std_logic_vector( 3 DOWNTO 0);
SIGNAL M_Prio : std_logic_vector( 2 DOWNTO 0);
ALIAS Found : std_logic IS M_Prio(2);
BEGIN
Ram_Addr <= s_Adr(9 DOWNTO 8) & s_Adr(5 DOWNTO 1) & s_Adr(6);
Ram_Wr <= '1' WHEN s_nWr = '0' AND Sel_Ram = '1' AND s_Adr(10) = '0' ELSE '0';
Ram_BeH(1) <= '1' WHEN s_nWr = '1' OR (s_nBE(1) = '0' AND s_Adr( 7) = '0') ELSE '0';
Ram_BeH(0) <= '1' WHEN s_nWr = '1' OR (s_nBE(0) = '0' AND s_Adr( 7) = '0') ELSE '0';
Ram_BeL(1) <= '1' WHEN s_nWr = '1' OR (s_nBE(1) = '0' AND s_Adr( 7) = '1') ELSE '0';
Ram_BeL(0) <= '1' WHEN s_nWr = '1' OR (s_nBE(0) = '0' AND s_Adr( 7) = '1') ELSE '0';
Filter_Addr <= Dibl_Cnt & Byte_Cnt;
FiltRamH: ENTITY work.Dpr_16_32
GENERIC MAP(Simulate => Simulate)
PORT MAP ( CLKA => Clk, CLKB => Clk,
EnA => cActivated, EnB => cActivated,
BEA => Ram_BeH,
WEA => Ram_Wr,
ADDRA => Ram_Addr, ADDRB => Filter_Addr,
DIA => s_Din, DOB => Filter_Out_H
);
FiltRamL: ENTITY work.Dpr_16_32
GENERIC MAP(Simulate => Simulate)
PORT MAP ( CLKA => Clk, CLKB => Clk,
EnA => cActivated, EnB => cActivated,
BEA => Ram_BeL,
WEA => Ram_Wr,
ADDRA => Ram_Addr, ADDRB => Filter_Addr,
DIA => s_Din, DOB => Filter_Out_L
);
Erg0 <= (Rx_Buf XOR Filter_Out_H( 7 DOWNTO 0)) AND Filter_Out_H(15 DOWNTO 8);
Erg1 <= (Rx_Buf XOR Filter_Out_H(23 DOWNTO 16)) AND Filter_Out_H(31 DOWNTO 24);
Erg2 <= (Rx_Buf XOR Filter_Out_L( 7 DOWNTO 0)) AND Filter_Out_L(15 DOWNTO 8);
Erg3 <= (Rx_Buf XOR Filter_Out_L(23 DOWNTO 16)) AND Filter_Out_L(31 DOWNTO 24);
genMatSel: FOR i IN 0 TO 3 GENERATE
Mat_Sel(i) <= Mat_Reg( 0 + i) WHEN Filt_Idx = "00" ELSE
Mat_Reg( 4 + i) WHEN Filt_Idx = "01" ELSE
Mat_Reg( 8 + i) WHEN Filt_Idx = "10" ELSE
Mat_Reg(12 + i); -- WHEN Filt_Idx = "11";
END GENERATE;
M_Prio <= "000" WHEN Filt_Cmp = '0' OR Match = '1' ELSE
"100" WHEN Mat_Sel(0) = '1' AND On_0 = '1' AND (DIRON_0 = '0') ELSE
"101" WHEN Mat_Sel(1) = '1' AND On_1 = '1' AND (DIRON_1 = '0') ELSE
"110" WHEN Mat_Sel(2) = '1' AND On_2 = '1' AND (DIRON_2 = '0') ELSE
"111" WHEN Mat_Sel(3) = '1' AND On_3 = '1' AND (DIRON_3 = '0') ELSE
"000";
pFilter: PROCESS( Rst, Clk )
BEGIN
IF Rst = '1' THEN
Filt_Idx <= "00"; Match <= '0';
Filt_Cmp <= '0'; Mat_Reg <= (OTHERS => '0'); Byte_Cnt <= (OTHERS =>'0');
Match_Desc <= (OTHERS => '0');Auto_Desc <= (OTHERS =>'0'); Answer_Tx <= '0';
ELSIF rising_edge( Clk ) THEN
Filt_Idx <= Dibl_Cnt;
IF Dibl_Cnt = "11" AND Rx_Count(5) = '0' THEN Byte_Cnt <= Rx_Count(Byte_Cnt'RANGE);
END IF;
IF Dsm = sTiml THEN Filt_Cmp <= '1';
ELSIF Rx_Dv = '0' OR (F_Val = '1' AND Rx_Count(5) = '1') THEN Filt_Cmp <= '0';
END IF;
IF Dsm = sTimL THEN Mat_Reg <= (OTHERS => '1');
ELSE
FOR i IN 0 TO 3 LOOP
IF Erg0 /= 0 AND conv_integer(Filt_Idx) = i THEN Mat_Reg(4*i + 0) <= '0'; END IF;
IF Erg1 /= 0 AND conv_integer(Filt_Idx) = i THEN Mat_Reg(4*i + 1) <= '0'; END IF;
IF Erg2 /= 0 AND conv_integer(Filt_Idx) = i THEN Mat_Reg(4*i + 2) <= '0'; END IF;
IF Erg3 /= 0 AND conv_integer(Filt_Idx) = i THEN Mat_Reg(4*i + 3) <= '0'; END IF;
END LOOP;
END IF;
IF Dsm = sTimL THEN Match <= '0';
ELSIF Found = '1' THEN Match <= '1'; Match_Desc <= Filt_Idx & M_Prio(1 DOWNTO 0);
IF M_Prio(1 DOWNTO 0) = "00" THEN Answer_Tx <= TX_0; Auto_Desc <= DESC_0;
ELSIF M_Prio(1 DOWNTO 0) = "01" THEN Answer_Tx <= TX_1; Auto_Desc <= DESC_1;
ELSIF M_Prio(1 DOWNTO 0) = "10" THEN Answer_Tx <= TX_2; Auto_Desc <= DESC_2;
ELSIF M_Prio(1 DOWNTO 0) = "11" THEN Answer_Tx <= TX_3; Auto_Desc <= DESC_3;
END IF;
ELSIF F_End = '1' THEN Answer_Tx <= '0';
END IF;
END IF;
END PROCESS pFilter;
R_Req <= Answer_Tx WHEN F_End = '1' AND F_Err = '0' ELSE '0';
END BLOCK bFilter;
Sel_RxH <= '1' WHEN s_nWr = '0' AND Sel_Cont = '1' AND s_Adr(3) = '1' AND s_nBe(1) = '0' ELSE '0';
Sel_RxL <= '1' WHEN s_nWr = '0' AND Sel_Cont = '1' AND s_Adr(3) = '1' AND s_nBe(0) = '0' ELSE '0';
pRxRegs: PROCESS( Rst, Clk )
BEGIN
IF Rst = '1' THEN
Rx_Desc <= (OTHERS => '0'); Rx_On <= '0';
Rx_Ie <= '0'; Rx_Lost <= '0'; Rx_Icnt <= (OTHERS => '0'); RxInt <= '0'; Diag <= '0';
ELSIF rising_edge( Clk ) THEN
IF Sel_RxH = '1' THEN
IF s_Adr(2 DOWNTO 1) = "00" THEN Rx_Ie <= S_Din(15);
ELSIF s_Adr(2 DOWNTO 1) = "01" AND S_Din(15) = '1' THEN Rx_Ie <= '1';
ELSIF s_Adr(2 DOWNTO 1) = "10" AND S_Din(15) = '1' THEN Rx_Ie <= '0';
END IF;
END IF;
IF Sel_RxH = '1' THEN
IF s_Adr(2 DOWNTO 1) = "00" THEN Diag <= S_Din(12);
ELSIF s_Adr(2 DOWNTO 1) = "01" AND S_Din(12) = '1' THEN Diag <= '1';
ELSIF s_Adr(2 DOWNTO 1) = "10" AND S_Din(12) = '1' THEN Diag <= '0';
END IF;
END IF;
IF Sel_RxL = '1' THEN
IF s_Adr(2 DOWNTO 1) = "00" THEN Rx_On <= S_Din( 7);
ELSIF s_Adr(2 DOWNTO 1) = "01" AND S_Din( 7) = '1' THEN Rx_On <= '1';
ELSIF s_Adr(2 DOWNTO 1) = "10" AND S_Din( 7) = '1' THEN Rx_On <= '0';
END IF;
END IF;
IF Rx_Beg = '1' AND (RX_OWN = '0' OR Rx_On = '0') THEN Rx_Lost <= '1';
ELSIF Sel_RxL = '1' AND s_Adr(2 DOWNTO 1) = "10" AND S_Din( 4) = '1' THEN Rx_Lost <= '0';
END IF;
IF Sel_RxL = '1' AND s_Adr(2 DOWNTO 1) = "11" THEN Rx_Desc <= S_Din( 3 DOWNTO 0);
ELSIF Dsm = sLenW AND Desc_We = '1' THEN
IF Last_Desc = '1' THEN Rx_Desc <= x"0";
ELSE Rx_Desc <= Rx_Desc + 1;
END IF;
END IF;
IF Rx_Ie = '1' AND Desc_We = '1' AND Dsm = sStat THEN RxInt <= '1';
ELSE RxInt <= '0';
END IF;
IF Sel_RxH = '1' AND s_Adr(2 DOWNTO 1) = "10" AND S_Din(8) = '1'
AND Rx_Icnt /= 0 THEN Rx_Icnt <= Rx_Icnt - NOT RxInt;
ELSIF RxInt = '1' AND Rx_Icnt /= "11111" THEN Rx_Icnt <= Rx_Icnt + 1;
END IF;
END IF;
END PROCESS pRxRegs;
END BLOCK bRxDesc;
END BLOCK b_Full_Rx;
END ARCHITECTURE struct; | gpl-2.0 | 339d5f5a80ad768ac42a6f565274e17f | 0.512649 | 2.518223 | false | false | false | false |
DougFirErickson/parallella-hw | fpga/ip/xilinx/fifo_async_103x16/synth/fifo_async_103x16.vhd | 2 | 38,595 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:12.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v12_0;
USE fifo_generator_v12_0.fifo_generator_v12_0;
ENTITY fifo_async_103x16 IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(102 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(102 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
prog_full : OUT STD_LOGIC
);
END fifo_async_103x16;
ARCHITECTURE fifo_async_103x16_arch OF fifo_async_103x16 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF fifo_async_103x16_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v12_0 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(102 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(102 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v12_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF fifo_async_103x16_arch: ARCHITECTURE IS "fifo_generator_v12_0,Vivado 2014.3.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF fifo_async_103x16_arch : ARCHITECTURE IS "fifo_async_103x16,fifo_generator_v12_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF fifo_async_103x16_arch: ARCHITECTURE IS "fifo_async_103x16,fifo_generator_v12_0,{x_ipProduct=Vivado 2014.3.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=12.0,x_ipCoreRevision=2,x_ipLanguage=VERILOG,C_COMMON_CLOCK=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=4,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=103,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=103,C_ENABLE_RLOCS=0,C_FAMILY=zynq,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=2,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=2,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=0,C_PRELOAD_REGS=1,C_PRIM_FIFO_TYPE=512x72,C_PROG_EMPTY_THRESH_ASSERT_VAL=4,C_PROG_EMPTY_THRESH_NEGATE_VAL=5,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=12,C_PROG_FULL_THRESH_NEGATE_VAL=11,C_PROG_FULL_TYPE=1,C_RD_DATA_COUNT_WIDTH=4,C_RD_DEPTH=16,C_RD_FREQ=1,C_RD_PNTR_WIDTH=4,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=4,C_WR_DEPTH=16,C_WR_FREQ=1,C_WR_PNTR_WIDTH=4,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
BEGIN
U0 : fifo_generator_v12_0
GENERIC MAP (
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 4,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 103,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 103,
C_ENABLE_RLOCS => 0,
C_FAMILY => "zynq",
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 2,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 2,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 0,
C_PRELOAD_REGS => 1,
C_PRIM_FIFO_TYPE => "512x72",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 4,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 5,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 12,
C_PROG_FULL_THRESH_NEGATE_VAL => 11,
C_PROG_FULL_TYPE => 1,
C_RD_DATA_COUNT_WIDTH => 4,
C_RD_DEPTH => 16,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 4,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 4,
C_WR_DEPTH => 16,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 4,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => '0',
rst => rst,
srst => '0',
wr_clk => wr_clk,
wr_rst => '0',
rd_clk => rd_clk,
rd_rst => '0',
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
empty => empty,
prog_full => prog_full,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END fifo_async_103x16_arch;
| gpl-3.0 | cf95e30e93d12b50b15284060417abec | 0.628061 | 2.91371 | false | false | false | false |
DougFirErickson/parallella-hw | fpga/ip/xilinx/memory_dp_48x4096/blk_mem_gen_v8_2/hdl/blk_mem_gen_mux.vhd | 8 | 97,172 | `protect begin_protected
`protect version = 1
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
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S2QILamQk8fZg6aWFopq0OYI4Hdv/rIu+A==
`protect end_protected
| gpl-3.0 | 4d074822875f8dbdd4590fa4a7536781 | 0.953351 | 1.811795 | false | false | false | false |
Monash-2015-Ultrasonic/Logs | Final System Code/SYSTEMV3/Source/IP/FIR/FIR/FIR_0002_ast.vhd | 1 | 9,974 | -- (C) 2001-2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.auk_dspip_lib_pkg_hpfir.all;
use work.auk_dspip_math_pkg_hpfir.all;
entity FIR_0002_ast is
generic (
INWIDTH : integer := 13;
FULL_WIDTH : integer := 30;
BANKINWIDTH : integer := 3;
REM_LSB_BIT_g : integer := 0;
REM_LSB_TYPE_g : string := "Truncation";
REM_MSB_BIT_g : integer := 0;
REM_MSB_TYPE_g : string := "Truncation";
PHYSCHANIN : integer := 1;
PHYSCHANOUT : integer := 1;
CHANSPERPHYIN : natural := 1;
CHANSPERPHYOUT : natural := 1;
OUTPUTFIFODEPTH : integer := 8;
USE_PACKETS : integer := 0;
ENABLE_BACKPRESSURE : boolean := false;
LOG2_CHANSPERPHYOUT : natural := log2_ceil_one(1);
NUMCHANS : integer := 1;
DEVICE_FAMILY : string := "Cyclone II"
);
port(
clk : in std_logic;
reset_n : in std_logic;
ast_sink_ready : out std_logic;
ast_source_data : out std_logic_vector((FULL_WIDTH - REM_LSB_BIT_g - REM_MSB_BIT_g) * PHYSCHANOUT - 1 downto 0);
ast_sink_data : in std_logic_vector( (INWIDTH + BANKINWIDTH) * PHYSCHANIN - 1 downto 0);
ast_sink_valid : in std_logic;
ast_source_valid : out std_logic;
ast_source_ready : in std_logic;
ast_source_eop : out std_logic;
ast_source_sop : out std_logic;
ast_source_channel : out std_logic_vector (LOG2_CHANSPERPHYOUT - 1 downto 0);
ast_sink_eop : in std_logic;
ast_sink_sop : in std_logic;
ast_sink_error : in std_logic_vector (1 downto 0);
ast_source_error : out std_logic_vector (1 downto 0)
);
attribute altera_attribute : string;
attribute altera_attribute of FIR_0002_ast:entity is "-name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 10036";
end FIR_0002_ast;
-- Warnings Suppression On
-- altera message_off 10036
architecture struct of FIR_0002_ast is
constant OUTWIDTH : integer := FULL_WIDTH - REM_LSB_BIT_g - REM_MSB_BIT_g;
signal channel_out : std_logic_vector(LOG2_CHANSPERPHYOUT - 1 downto 0);
signal core_channel_out : std_logic_vector(2 -1 downto 0);
signal at_source_channel : std_logic_vector(2 -1 downto 0);
signal sink_packet_error : std_logic_vector(1 downto 0);
signal data_in : std_logic_vector((INWIDTH + BANKINWIDTH) * PHYSCHANIN - 1 downto 0);
signal data_valid : std_logic_vector(0 downto 0);
signal data_out : std_logic_vector(OUTWIDTH * PHYSCHANOUT -1 downto 0);
signal reset_fir : std_logic;
signal sink_ready_ctrl : std_logic;
signal source_packet_error : std_logic_vector(1 downto 0);
signal source_stall : std_logic;
signal source_valid_ctrl : std_logic;
signal stall : std_logic;
signal valid : std_logic;
signal core_valid : std_logic;
signal enable_in : std_logic_vector(0 downto 0);
signal outp_out : std_logic_vector(OUTWIDTH * PHYSCHANOUT - 1 downto 0);
signal outp_blk_valid : std_logic_vector(PHYSCHANOUT - 1 downto 0);
signal core_out : std_logic_vector(FULL_WIDTH * PHYSCHANOUT - 1 downto 0);
signal core_out_valid : std_logic_vector(0 downto 0);
signal core_out_channel : std_logic_vector(7 downto 0);
signal core_out_channel_0 : std_logic_vector(7 downto 0);
component FIR_0002_rtl is
port (
xIn_v : in std_logic_vector(0 downto 0);
xIn_c : in std_logic_vector(7 downto 0);
xIn_0 : in std_logic_vector(13 - 1 downto 0);
bankIn_0 : in std_logic_vector(3 - 1 downto 0);
xOut_v : out std_logic_vector(0 downto 0);
xOut_c : out std_logic_vector(7 downto 0);
xOut_0 : out std_logic_vector(30 - 1 downto 0);
clk : in std_logic;
areset : in std_logic
);
end component FIR_0002_rtl;
begin
sink : auk_dspip_avalon_streaming_sink_hpfir
generic map (
WIDTH_g => (INWIDTH + BANKINWIDTH) * PHYSCHANIN,
DATA_WIDTH => (INWIDTH + BANKINWIDTH),
DATA_PORT_COUNT => PHYSCHANIN,
PACKET_SIZE_g => CHANSPERPHYIN)
port map (
clk => clk,
reset_n => reset_n,
data => data_in,
data_valid => data_valid,
sink_ready_ctrl => sink_ready_ctrl,
packet_error => sink_packet_error,
at_sink_ready => ast_sink_ready,
at_sink_valid => ast_sink_valid,
at_sink_data => ast_sink_data,
at_sink_sop => ast_sink_sop,
at_sink_eop => ast_sink_eop,
at_sink_error => ast_sink_error);
source : auk_dspip_avalon_streaming_source_hpfir
generic map (
WIDTH_g => OUTWIDTH * PHYSCHANOUT,
DATA_WIDTH => OUTWIDTH,
DATA_PORT_COUNT => PHYSCHANOUT,
FIFO_DEPTH_g => OUTPUTFIFODEPTH,
USE_PACKETS => USE_PACKETS,
HAVE_COUNTER_g => false,
PACKET_SIZE_g => CHANSPERPHYOUT,
COUNTER_LIMIT_g => CHANSPERPHYOUT,
ENABLE_BACKPRESSURE_g => ENABLE_BACKPRESSURE)
port map (
clk => clk,
reset_n => reset_n,
data_in => data_out,
data_count => channel_out,
source_valid_ctrl => source_valid_ctrl,
source_stall => source_stall,
packet_error => source_packet_error,
at_source_ready => ast_source_ready,
at_source_valid => ast_source_valid,
at_source_data => ast_source_data,
at_source_channel => ast_source_channel,
at_source_sop => ast_source_sop,
at_source_eop => ast_source_eop,
at_source_error => ast_source_error);
intf_ctrl : auk_dspip_avalon_streaming_controller_hpfir
port map (
clk => clk,
reset_n => reset_n,
sink_packet_error => sink_packet_error,
source_stall => source_stall,
valid => valid,
reset_design => reset_fir,
sink_ready_ctrl => sink_ready_ctrl,
source_packet_error => source_packet_error,
source_valid_ctrl => source_valid_ctrl,
stall => stall);
hpfircore: FIR_0002_rtl
port map (
xIn_v => data_valid,
xIn_c => "00000000",
xIn_0 => data_in((3 + 13) * 0 + 13 - 1 downto (3 + 13) * 0),
bankIn_0 => data_in((3 + 13) * 0 + (3 + 13) - 1 downto (3 + 13) * 0 + 13),
xOut_v => core_out_valid,
xOut_c => core_out_channel,
xOut_0 => core_out(30 * 0 + 30 - 1 downto 30 * 0),
clk => clk,
areset => reset_fir
);
gen_outp_blk : for i in PHYSCHANOUT-1 downto 0 generate
begin
outp_blk : auk_dspip_roundsat_hpfir
generic map (
IN_WIDTH_g => FULL_WIDTH ,
REM_LSB_BIT_g => REM_LSB_BIT_g ,
REM_LSB_TYPE_g => REM_LSB_TYPE_g ,
REM_MSB_BIT_g => REM_MSB_BIT_g ,
REM_MSB_TYPE_g => REM_MSB_TYPE_g
)
port map (
clk => clk,
reset_n => reset_n,
enable => core_out_valid(0),
datain => core_out(((i*FULL_WIDTH)+FULL_WIDTH-1) downto (i*FULL_WIDTH)),
valid => outp_blk_valid(i),
dataout => outp_out(((i*OUTWIDTH)+OUTWIDTH-1) downto (i*OUTWIDTH))
);
end generate gen_outp_blk;
multi_data_out: for m in PHYSCHANOUT-1 downto 0 generate
data_out(((m*OUTWIDTH)+OUTWIDTH-1) downto (m*OUTWIDTH)) <= outp_out(((m*OUTWIDTH)+OUTWIDTH-1) downto (m*OUTWIDTH));
end generate multi_data_out;
channel_pipe_lsb: if REM_LSB_TYPE_g = "Rounding" and REM_LSB_BIT_g > 0 generate
begin
out_lsb_p : process (clk, reset_n)
begin
if reset_n = '0' then
core_out_channel_0 <= (others => '0');
elsif rising_edge(clk) then
core_out_channel_0 <= core_out_channel;
end if;
end process out_lsb_p;
end generate channel_pipe_lsb;
channel_wire_lsb: if REM_LSB_TYPE_g = "Truncation" or REM_LSB_BIT_g = 0 generate
begin
core_out_channel_0 <= core_out_channel;
end generate channel_wire_lsb;
channel_pipe_msb: if REM_MSB_TYPE_g = "Saturating" and REM_MSB_BIT_g > 0 generate
begin
out_p : process (clk, reset_n)
begin
if reset_n = '0' then
channel_out <= (others => '0');
elsif rising_edge(clk) then
channel_out <= core_out_channel_0(LOG2_CHANSPERPHYOUT-1 downto 0);
end if;
end process out_p;
end generate channel_pipe_msb;
channel_wire_msb: if REM_MSB_TYPE_g = "Truncation" or REM_MSB_BIT_g = 0 generate
begin
channel_out <= core_out_channel_0(LOG2_CHANSPERPHYOUT-1 downto 0);
end generate channel_wire_msb;
valid <= outp_blk_valid(0);
enable_in(0) <= not stall;
end struct;
| gpl-2.0 | a808051d012227fd6442844e8e40aa0a | 0.591037 | 3.363912 | false | false | false | false |
Monash-2015-Ultrasonic/Logs | Final System Code/SYSTEMV3/Source/IP/FIR/FIR_sim/auk_dspip_avalon_streaming_controller_hpfir.vhd | 2 | 3,129 | -- (C) 2001-2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-------------------------------------------------------------------------
-------------------------------------------------------------------------
--
-- $Revision: #1 $
-- $Date: 2009/07/29 $
-- Author : Boon Hong Oh
--
-- Project : Avalon Streaming Wrapper for HP FIR
--
-- Description :
--
-- This file is the Interface controller for the Avalon Streaming Wrapper.
-- The control signals between sink, core, and source modules are communicated
-- via the controller. The stall output is used as the core enable signal in
-- the wrapper.
--
-- ALTERA Confidential and Proprietary
-- Copyright 2006 (c) Altera Corporation
-- All rights reserved
--
-------------------------------------------------------------------------
-------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity auk_dspip_avalon_streaming_controller_hpfir is
port(
clk : in std_logic;
--clk_en : in std_logic := '1';
reset_n : in std_logic;
--ready : in std_logic;
sink_packet_error : in std_logic_vector (1 downto 0);
--sink_stall : in std_logic;
source_stall : in std_logic;
valid : in std_logic;
reset_design : out std_logic;
sink_ready_ctrl : out std_logic;
source_packet_error : out std_logic_vector (1 downto 0) := (others => '0');
source_valid_ctrl : out std_logic;
stall : out std_logic
);
-- Declarations
end auk_dspip_avalon_streaming_controller_hpfir;
-- hds interface_end
architecture struct of auk_dspip_avalon_streaming_controller_hpfir is
-- signal stall_int : std_logic;
-- signal stall_reg : std_logic;
-- attribute maxfan : integer;
-- attribute maxfan of stall_reg : signal is 500;
begin
reset_design <= not reset_n;
--should not stop sending data to source module when the sink module is stalled
--should only stop sending when the source module is stalled
--Disable the FIR core when backpressure
stall <= source_stall;
source_valid_ctrl <= valid;
-- Sink FIFO and FIR core are disabled at the same time
sink_ready_ctrl <= not(source_stall);
source_packet_error <= sink_packet_error;
end struct;
| gpl-2.0 | d7bb6e831c476243938e8b74870d1b30 | 0.614893 | 4.268759 | false | false | false | false |
estadofinito/biblioteca-vhdl | todos-los-archivos/clk0_125.vhd | 2 | 1,372 | ----------------------------------------------------------------------------------
-- Compañía: Estado Finito
-- Ingeniero: Carlos Ramos
--
-- Fecha de creación: 2014/04/13 08:28:48
-- Nombre del módulo: clk0_125Hz - Behavioral
-- Comentarios adicionales:
-- Implementación mediante aproximación, a caso con escala ajustada par (de 400000000 a 400000000).
-- La frecuencia fue ajustada al entero más próximo.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity clk0_125Hz is
Port (
clk : in STD_LOGIC; -- Reloj de entrada de 50000000Hz.
reset : in STD_LOGIC;
clk_out : out STD_LOGIC -- Reloj de salida de 0.125Hz.
);
end clk0_125Hz;
architecture Behavioral of clk0_125Hz is
signal temporal: STD_LOGIC;
signal contador: integer range 0 to 199999999 := 0;
begin
divisor_frecuencia: process (clk, reset) begin
if (reset = '1') then
temporal <= '0';
contador <= 0;
elsif rising_edge(clk) then
if (contador = 199999999) then
temporal <= NOT(temporal);
contador <= 0;
else
contador <= contador + 1;
end if;
end if;
end process;
clk_out <= temporal;
end Behavioral; | lgpl-2.1 | d6648f922574958964c0f64d80588cbd | 0.519679 | 4.035294 | false | false | false | false |
Monash-2015-Ultrasonic/Logs | Final System Code/SYSTEMV3/Source/IP/FIR/FIR/FIR_0002.vhd | 1 | 1,727 | library IEEE;
use IEEE.std_logic_1164.all;
entity FIR_0002 is
port (
clk : in STD_LOGIC;
reset_n : in STD_LOGIC;
ast_sink_data : in STD_LOGIC_VECTOR((3 + 13) * 1 - 1 downto 0);
ast_sink_valid : in STD_LOGIC;
ast_sink_error : in STD_LOGIC_VECTOR(1 downto 0);
ast_source_data : out STD_LOGIC_VECTOR(30 * 1 - 1 downto 0);
ast_source_valid : out STD_LOGIC;
ast_source_error : out STD_LOGIC_VECTOR(1 downto 0)
);
end FIR_0002;
architecture syn of FIR_0002 is
component FIR_0002_ast
port (
clk : in STD_LOGIC;
reset_n : in STD_LOGIC;
ast_sink_data : in STD_LOGIC_VECTOR((3 + 13) * 1 - 1 downto 0);
ast_sink_valid : in STD_LOGIC;
ast_sink_ready : out STD_LOGIC;
ast_sink_sop : in STD_LOGIC;
ast_sink_eop : in STD_LOGIC;
ast_sink_error : in STD_LOGIC_VECTOR(1 downto 0);
ast_source_data : out STD_LOGIC_VECTOR(30 * 1 - 1 downto 0);
ast_source_ready : in STD_LOGIC;
ast_source_valid : out STD_LOGIC;
ast_source_sop : out STD_LOGIC;
ast_source_eop : out STD_LOGIC;
ast_source_channel : out STD_LOGIC_VECTOR(1 - 1 downto 0);
ast_source_error : out STD_LOGIC_VECTOR(1 downto 0)
);
end component;
begin
FIR_0002_ast_inst : FIR_0002_ast
port map (
clk => clk,
reset_n => reset_n,
ast_sink_data => ast_sink_data,
ast_source_data => ast_source_data,
ast_sink_valid => ast_sink_valid,
ast_sink_ready => open,
ast_source_ready => '1',
ast_source_valid => ast_source_valid,
ast_sink_sop => '0',
ast_sink_eop => '0',
ast_sink_error => ast_sink_error,
ast_source_sop => open,
ast_source_eop => open,
ast_source_channel => open,
ast_source_error => ast_source_error
);
end syn;
| gpl-2.0 | d3e9c4ab95410d16438f98689048b1ea | 0.623625 | 2.952137 | false | false | false | false |
dummylink/plnk_fpga-stack | Examples/xilinx_microblaze/avnet_lx9/pcores/plb_powerlink_v1_00_a/hdl/vhdl/openMAC_DMAmaster/plb_master_handler.vhd | 2 | 10,873 | -------------------------------------------------------------------------------
--
-- Title : plb_master_handler
-- Design : POWERLINK
--
-------------------------------------------------------------------------------
--
-- File : c:\my_designs\POWERLINK\src\plb_master_handler.vhd
-- Generated : Mon Nov 7 13:17:30 2011
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2011
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- 2011-08-03 V0.01 zelenkaj First version
-- 2011-12-01 V0.02 zelenkaj Fixed read transfer error (dst_rdy_n earlier)
-- 2011-12-05 V0.03 zelenkaj Avoid preset of FFs
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity plb_master_handler is
generic(
gen_rx_fifo_g : boolean := true;
gen_tx_fifo_g : boolean := true;
dma_highadr_g : integer := 31;
C_MAC_DMA_PLB_NATIVE_DWIDTH : integer := 32;
C_MAC_DMA_PLB_AWIDTH : integer := 32;
m_burstcount_width_g : integer := 4
);
port(
MAC_DMA_CLK : in std_logic;
MAC_DMA_Rst : in std_logic;
Bus2MAC_DMA_Mst_CmdAck : in std_logic := '0';
Bus2MAC_DMA_Mst_Cmplt : in std_logic := '0';
Bus2MAC_DMA_Mst_Error : in std_logic := '0';
Bus2MAC_DMA_Mst_Rearbitrate : in std_logic := '0';
Bus2MAC_DMA_Mst_Cmd_Timeout : in std_logic := '0';
Bus2MAC_DMA_MstRd_d : in std_logic_vector(C_MAC_DMA_PLB_NATIVE_DWIDTH-1 downto 0);
Bus2MAC_DMA_MstRd_rem : in std_logic_vector(C_MAC_DMA_PLB_NATIVE_DWIDTH/8-1 downto 0);
Bus2MAC_DMA_MstRd_sof_n : in std_logic := '1';
Bus2MAC_DMA_MstRd_eof_n : in std_logic := '1';
Bus2MAC_DMA_MstRd_src_rdy_n : in std_logic := '1';
Bus2MAC_DMA_MstRd_src_dsc_n : in std_logic := '1';
Bus2MAC_DMA_MstWr_dst_rdy_n : in std_logic := '1';
Bus2MAC_DMA_MstWr_dst_dsc_n : in std_logic := '1';
MAC_DMA2Bus_MstRd_Req : out std_logic := '0';
MAC_DMA2Bus_MstWr_Req : out std_logic := '0';
MAC_DMA2Bus_Mst_Type : out std_logic := '0';
MAC_DMA2Bus_Mst_Addr : out std_logic_vector(C_MAC_DMA_PLB_AWIDTH-1 downto 0);
MAC_DMA2Bus_Mst_Length : out std_logic_vector(11 downto 0);
MAC_DMA2Bus_Mst_BE : out std_logic_vector(C_MAC_DMA_PLB_NATIVE_DWIDTH/8-1 downto 0);
MAC_DMA2Bus_Mst_Lock : out std_logic := '0';
MAC_DMA2Bus_Mst_Reset : out std_logic := '0';
MAC_DMA2Bus_MstRd_dst_rdy_n : out std_logic := '1';
MAC_DMA2Bus_MstRd_dst_dsc_n : out std_logic := '1';
MAC_DMA2Bus_MstWr_d : out std_logic_vector(C_MAC_DMA_PLB_NATIVE_DWIDTH-1 downto 0);
MAC_DMA2Bus_MstWr_rem : out std_logic_vector(C_MAC_DMA_PLB_NATIVE_DWIDTH/8-1 downto 0);
MAC_DMA2Bus_MstWr_sof_n : out std_logic := '1';
MAC_DMA2Bus_MstWr_eof_n : out std_logic := '1';
MAC_DMA2Bus_MstWr_src_rdy_n : out std_logic := '1';
MAC_DMA2Bus_MstWr_src_dsc_n : out std_logic := '1';
m_read : in std_logic := '0';
m_write : in std_logic := '0';
m_byteenable : in std_logic_vector(3 downto 0);
m_address : in std_logic_vector(dma_highadr_g downto 0);
m_writedata : in std_logic_vector(31 downto 0);
m_burstcount : in std_logic_vector(m_burstcount_width_g-1 downto 0);
m_burstcounter : in std_logic_vector(m_burstcount_width_g-1 downto 0);
m_readdata : out std_logic_vector(31 downto 0);
m_waitrequest : out std_logic := '1';
m_readdatavalid : out std_logic := '0';
m_clk : out std_logic
);
end plb_master_handler;
architecture plb_master_handler of plb_master_handler is
signal clk, rst : std_logic;
--signals for requesting transfers
signal m_write_s, m_read_s, m_wrd_en_n : std_logic;
signal m_write_l, m_read_l : std_logic;
signal m_write_rise, m_read_rise : std_logic;
signal m_write_fall, m_read_fall : std_logic;
signal mst_write_req, mst_write_req_next : std_logic;
signal mst_read_req, mst_read_req_next : std_logic;
--what if master wants to req new transfer, but previous is not yet completed (= no Mst_Cmplt pulse!!!)
signal mst_done : std_logic;
--signals for the transfer
type tran_t is (idle, sof, tran, eof, seof, wait4cmplt); --seof = start/end of frame (single beat)
signal wr_tran, wr_tran_next : tran_t;
signal rd_tran : tran_t;
--avoid preset of FFs
signal MAC_DMA2Bus_MstRd_dst_rdy : std_logic;
begin
--some assignments..
m_clk <= MAC_DMA_CLK;
clk <= MAC_DMA_CLK;
rst <= MAC_DMA_Rst;
mst_done <= Bus2MAC_DMA_Mst_Cmplt;
m_write_s <= m_write and not m_wrd_en_n; --NOTE: write/read enable is low-active!
m_read_s <= m_read and not m_wrd_en_n; --NOTE: write/read enable is low-active!
--reserved
MAC_DMA2Bus_Mst_Lock <= '0';
MAC_DMA2Bus_Mst_Reset <= '0';
--delay some signals..
del_proc : process(clk, rst)
begin
if rst = '1' then
m_write_l <= '0'; m_read_l <= '0';
m_wrd_en_n <= '0'; --is low-active to avoid preset of FF
elsif rising_edge(clk) then
m_write_l <= m_write_s; m_read_l <= m_read_s;
if mst_done = '1' then
m_wrd_en_n <= '0';
elsif m_write_fall = '1' or m_read_fall = '1' then
m_wrd_en_n <= '1'; --write/read done, wait for Mst_Cmplt
end if;
end if;
end process;
--generate pulse if write/read is asserted
m_write_rise <= '1' when m_write_l = '0' and m_write_s = '1' else '0';
m_read_rise <= '1' when m_read_l = '0' and m_read_s = '1' else '0';
m_write_fall <= '1' when m_write_l = '1' and m_write_s = '0' else '0';
m_read_fall <= '1' when m_read_l = '1' and m_read_s = '0' else '0';
--generate req qualifiers
req_proc : process(clk, rst)
begin
if rst = '1' then
mst_write_req <= '0'; mst_read_req <= '0';
MAC_DMA2Bus_MstRd_dst_rdy <= '0';
elsif rising_edge(clk) then
mst_write_req <= mst_write_req_next; mst_read_req <= mst_read_req_next;
if m_read_s = '1' then
MAC_DMA2Bus_MstRd_dst_rdy <= '1';
elsif rd_tran = eof and Bus2MAC_DMA_MstRd_src_rdy_n = '0' then
MAC_DMA2Bus_MstRd_dst_rdy <= '0';
end if;
end if;
end process;
MAC_DMA2Bus_MstRd_dst_rdy_n <= not MAC_DMA2Bus_MstRd_dst_rdy;
mst_write_req_next <= '0' when mst_write_req = '1' and Bus2MAC_DMA_Mst_CmdAck = '1' else
'1' when mst_write_req = '0' and m_write_rise = '1' else
mst_write_req;
mst_read_req_next <= '0' when mst_read_req = '1' and Bus2MAC_DMA_Mst_CmdAck = '1' else
'1' when mst_read_req = '0' and m_read_rise = '1' else
mst_read_req;
MAC_DMA2Bus_MstRd_Req <= mst_read_req;
MAC_DMA2Bus_MstWr_Req <= mst_write_req;
MAC_DMA2Bus_Mst_Type <= '0' when m_burstcount < 2 else --single beat
mst_read_req or mst_write_req; --we are talking about bursts..
--assign address, byteenable and burst size
MAC_DMA2Bus_Mst_Addr <= m_address;
MAC_DMA2Bus_Mst_BE <= "1111";
MAC_DMA2Bus_Mst_Length <= conv_std_logic_vector(conv_integer(m_burstcount),
MAC_DMA2Bus_Mst_Length'length - 2) & "00"; -- dword x 4 = byte
--write/read link
wrd_proc : process(clk, rst)
begin
if rst = '1' then
wr_tran <= idle;
elsif rising_edge(clk) then
wr_tran <= wr_tran_next;
end if;
end process;
--generate fsm for write and read transfers
wr_tran_next <=
seof when wr_tran = idle and mst_write_req_next = '1' and (m_burstcount <= 1 or m_burstcount'length = 1) else
sof when wr_tran = idle and mst_write_req_next = '1' and m_burstcount'length > 1 else
eof when wr_tran = sof and Bus2MAC_DMA_MstWr_dst_rdy_n = '0' and m_burstcount = 2 and m_burstcount'length > 1 else
tran when wr_tran = sof and Bus2MAC_DMA_MstWr_dst_rdy_n = '0' and m_burstcount'length > 1 else
eof when wr_tran = tran and m_burstcounter <= 2 and Bus2MAC_DMA_MstWr_dst_rdy_n = '0' and m_burstcount'length > 1 else
wait4cmplt when (wr_tran = eof or wr_tran = seof) and Bus2MAC_DMA_MstWr_dst_rdy_n = '0' else
idle when wr_tran = wait4cmplt and mst_done = '1' else
wr_tran;
rd_tran <=
seof when Bus2MAC_DMA_MstRd_sof_n = '0' and Bus2MAC_DMA_MstRd_eof_n = '0' else
sof when Bus2MAC_DMA_MstRd_sof_n = '0' else
eof when Bus2MAC_DMA_MstRd_eof_n = '0' else
tran when Bus2MAC_DMA_MstRd_src_rdy_n = '0' else
idle;
--set write qualifiers
MAC_DMA2Bus_MstWr_sof_n <= '0' when wr_tran = sof or wr_tran = seof else '1';
MAC_DMA2Bus_MstWr_eof_n <= '0' when wr_tran = eof or wr_tran = seof else '1';
MAC_DMA2Bus_MstWr_src_rdy_n <= '0' when wr_tran /= idle and wr_tran /= wait4cmplt else '1';
MAC_DMA2Bus_MstWr_src_dsc_n <= '1'; --no support
MAC_DMA2Bus_MstWr_rem <= (others => '0'); --no support
--set read qualifiers
MAC_DMA2Bus_MstRd_dst_dsc_n <= '1'; --no support
--connect ipif with avalon
m_waitrequest <= --waitrequest if not ready or no write active
not m_write when Bus2MAC_DMA_MstWr_dst_rdy_n = '0' else
not m_read when mst_read_req = '1' and Bus2MAC_DMA_Mst_CmdAck = '1' else '1';
m_readdatavalid <= not Bus2MAC_DMA_MstRd_src_rdy_n;
MAC_DMA2Bus_MstWr_d <= m_writedata;
m_readdata <= Bus2MAC_DMA_MstRd_d;
end plb_master_handler;
| gpl-2.0 | c5a5730ba038a0f23c5424090a727561 | 0.622459 | 2.860563 | false | false | false | false |
Monash-2015-Ultrasonic/Logs | Final System Code/SYSTEMV3/Source/IP/FIR/FIR_sim/FIR_ast.vhd | 1 | 9,939 | -- (C) 2001-2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.auk_dspip_lib_pkg_hpfir.all;
use work.auk_dspip_math_pkg_hpfir.all;
entity FIR_ast is
generic (
INWIDTH : integer := 13;
FULL_WIDTH : integer := 30;
BANKINWIDTH : integer := 3;
REM_LSB_BIT_g : integer := 0;
REM_LSB_TYPE_g : string := "Truncation";
REM_MSB_BIT_g : integer := 0;
REM_MSB_TYPE_g : string := "Truncation";
PHYSCHANIN : integer := 1;
PHYSCHANOUT : integer := 1;
CHANSPERPHYIN : natural := 1;
CHANSPERPHYOUT : natural := 1;
OUTPUTFIFODEPTH : integer := 8;
USE_PACKETS : integer := 0;
ENABLE_BACKPRESSURE : boolean := false;
LOG2_CHANSPERPHYOUT : natural := log2_ceil_one(1);
NUMCHANS : integer := 1;
DEVICE_FAMILY : string := "Cyclone II"
);
port(
clk : in std_logic;
reset_n : in std_logic;
ast_sink_ready : out std_logic;
ast_source_data : out std_logic_vector((FULL_WIDTH - REM_LSB_BIT_g - REM_MSB_BIT_g) * PHYSCHANOUT - 1 downto 0);
ast_sink_data : in std_logic_vector( (INWIDTH + BANKINWIDTH) * PHYSCHANIN - 1 downto 0);
ast_sink_valid : in std_logic;
ast_source_valid : out std_logic;
ast_source_ready : in std_logic;
ast_source_eop : out std_logic;
ast_source_sop : out std_logic;
ast_source_channel : out std_logic_vector (LOG2_CHANSPERPHYOUT - 1 downto 0);
ast_sink_eop : in std_logic;
ast_sink_sop : in std_logic;
ast_sink_error : in std_logic_vector (1 downto 0);
ast_source_error : out std_logic_vector (1 downto 0)
);
attribute altera_attribute : string;
attribute altera_attribute of FIR_ast:entity is "-name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 10036";
end FIR_ast;
-- Warnings Suppression On
-- altera message_off 10036
architecture struct of FIR_ast is
constant OUTWIDTH : integer := FULL_WIDTH - REM_LSB_BIT_g - REM_MSB_BIT_g;
signal channel_out : std_logic_vector(LOG2_CHANSPERPHYOUT - 1 downto 0);
signal core_channel_out : std_logic_vector(2 -1 downto 0);
signal at_source_channel : std_logic_vector(2 -1 downto 0);
signal sink_packet_error : std_logic_vector(1 downto 0);
signal data_in : std_logic_vector((INWIDTH + BANKINWIDTH) * PHYSCHANIN - 1 downto 0);
signal data_valid : std_logic_vector(0 downto 0);
signal data_out : std_logic_vector(OUTWIDTH * PHYSCHANOUT -1 downto 0);
signal reset_fir : std_logic;
signal sink_ready_ctrl : std_logic;
signal source_packet_error : std_logic_vector(1 downto 0);
signal source_stall : std_logic;
signal source_valid_ctrl : std_logic;
signal stall : std_logic;
signal valid : std_logic;
signal core_valid : std_logic;
signal enable_in : std_logic_vector(0 downto 0);
signal outp_out : std_logic_vector(OUTWIDTH * PHYSCHANOUT - 1 downto 0);
signal outp_blk_valid : std_logic_vector(PHYSCHANOUT - 1 downto 0);
signal core_out : std_logic_vector(FULL_WIDTH * PHYSCHANOUT - 1 downto 0);
signal core_out_valid : std_logic_vector(0 downto 0);
signal core_out_channel : std_logic_vector(7 downto 0);
signal core_out_channel_0 : std_logic_vector(7 downto 0);
component FIR_rtl is
port (
xIn_v : in std_logic_vector(0 downto 0);
xIn_c : in std_logic_vector(7 downto 0);
xIn_0 : in std_logic_vector(13 - 1 downto 0);
bankIn_0 : in std_logic_vector(3 - 1 downto 0);
xOut_v : out std_logic_vector(0 downto 0);
xOut_c : out std_logic_vector(7 downto 0);
xOut_0 : out std_logic_vector(30 - 1 downto 0);
clk : in std_logic;
areset : in std_logic
);
end component FIR_rtl;
begin
sink : auk_dspip_avalon_streaming_sink_hpfir
generic map (
WIDTH_g => (INWIDTH + BANKINWIDTH) * PHYSCHANIN,
DATA_WIDTH => (INWIDTH + BANKINWIDTH),
DATA_PORT_COUNT => PHYSCHANIN,
PACKET_SIZE_g => CHANSPERPHYIN)
port map (
clk => clk,
reset_n => reset_n,
data => data_in,
data_valid => data_valid,
sink_ready_ctrl => sink_ready_ctrl,
packet_error => sink_packet_error,
at_sink_ready => ast_sink_ready,
at_sink_valid => ast_sink_valid,
at_sink_data => ast_sink_data,
at_sink_sop => ast_sink_sop,
at_sink_eop => ast_sink_eop,
at_sink_error => ast_sink_error);
source : auk_dspip_avalon_streaming_source_hpfir
generic map (
WIDTH_g => OUTWIDTH * PHYSCHANOUT,
DATA_WIDTH => OUTWIDTH,
DATA_PORT_COUNT => PHYSCHANOUT,
FIFO_DEPTH_g => OUTPUTFIFODEPTH,
USE_PACKETS => USE_PACKETS,
HAVE_COUNTER_g => false,
PACKET_SIZE_g => CHANSPERPHYOUT,
COUNTER_LIMIT_g => CHANSPERPHYOUT,
ENABLE_BACKPRESSURE_g => ENABLE_BACKPRESSURE)
port map (
clk => clk,
reset_n => reset_n,
data_in => data_out,
data_count => channel_out,
source_valid_ctrl => source_valid_ctrl,
source_stall => source_stall,
packet_error => source_packet_error,
at_source_ready => ast_source_ready,
at_source_valid => ast_source_valid,
at_source_data => ast_source_data,
at_source_channel => ast_source_channel,
at_source_sop => ast_source_sop,
at_source_eop => ast_source_eop,
at_source_error => ast_source_error);
intf_ctrl : auk_dspip_avalon_streaming_controller_hpfir
port map (
clk => clk,
reset_n => reset_n,
sink_packet_error => sink_packet_error,
source_stall => source_stall,
valid => valid,
reset_design => reset_fir,
sink_ready_ctrl => sink_ready_ctrl,
source_packet_error => source_packet_error,
source_valid_ctrl => source_valid_ctrl,
stall => stall);
hpfircore: FIR_rtl
port map (
xIn_v => data_valid,
xIn_c => "00000000",
xIn_0 => data_in((3 + 13) * 0 + 13 - 1 downto (3 + 13) * 0),
bankIn_0 => data_in((3 + 13) * 0 + (3 + 13) - 1 downto (3 + 13) * 0 + 13),
xOut_v => core_out_valid,
xOut_c => core_out_channel,
xOut_0 => core_out(30 * 0 + 30 - 1 downto 30 * 0),
clk => clk,
areset => reset_fir
);
gen_outp_blk : for i in PHYSCHANOUT-1 downto 0 generate
begin
outp_blk : auk_dspip_roundsat_hpfir
generic map (
IN_WIDTH_g => FULL_WIDTH ,
REM_LSB_BIT_g => REM_LSB_BIT_g ,
REM_LSB_TYPE_g => REM_LSB_TYPE_g ,
REM_MSB_BIT_g => REM_MSB_BIT_g ,
REM_MSB_TYPE_g => REM_MSB_TYPE_g
)
port map (
clk => clk,
reset_n => reset_n,
enable => core_out_valid(0),
datain => core_out(((i*FULL_WIDTH)+FULL_WIDTH-1) downto (i*FULL_WIDTH)),
valid => outp_blk_valid(i),
dataout => outp_out(((i*OUTWIDTH)+OUTWIDTH-1) downto (i*OUTWIDTH))
);
end generate gen_outp_blk;
multi_data_out: for m in PHYSCHANOUT-1 downto 0 generate
data_out(((m*OUTWIDTH)+OUTWIDTH-1) downto (m*OUTWIDTH)) <= outp_out(((m*OUTWIDTH)+OUTWIDTH-1) downto (m*OUTWIDTH));
end generate multi_data_out;
channel_pipe_lsb: if REM_LSB_TYPE_g = "Rounding" and REM_LSB_BIT_g > 0 generate
begin
out_lsb_p : process (clk, reset_n)
begin
if reset_n = '0' then
core_out_channel_0 <= (others => '0');
elsif rising_edge(clk) then
core_out_channel_0 <= core_out_channel;
end if;
end process out_lsb_p;
end generate channel_pipe_lsb;
channel_wire_lsb: if REM_LSB_TYPE_g = "Truncation" or REM_LSB_BIT_g = 0 generate
begin
core_out_channel_0 <= core_out_channel;
end generate channel_wire_lsb;
channel_pipe_msb: if REM_MSB_TYPE_g = "Saturating" and REM_MSB_BIT_g > 0 generate
begin
out_p : process (clk, reset_n)
begin
if reset_n = '0' then
channel_out <= (others => '0');
elsif rising_edge(clk) then
channel_out <= core_out_channel_0(LOG2_CHANSPERPHYOUT-1 downto 0);
end if;
end process out_p;
end generate channel_pipe_msb;
channel_wire_msb: if REM_MSB_TYPE_g = "Truncation" or REM_MSB_BIT_g = 0 generate
begin
channel_out <= core_out_channel_0(LOG2_CHANSPERPHYOUT-1 downto 0);
end generate channel_wire_msb;
valid <= outp_blk_valid(0);
enable_in(0) <= not stall;
end struct;
| gpl-2.0 | 2f4b5ef0f41119eddbcfcfec72c717e2 | 0.590301 | 3.368011 | false | false | false | false |
DougFirErickson/parallella-hw | fpga/ip/xilinx/memory_dp_48x4096/synth/memory_dp_48x4096.vhd | 1 | 14,189 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY memory_dp_48x4096 IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
clkb : IN STD_LOGIC;
enb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
);
END memory_dp_48x4096;
ARCHITECTURE memory_dp_48x4096_arch OF memory_dp_48x4096 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF memory_dp_48x4096_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
sleep : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF memory_dp_48x4096_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2014.3.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF memory_dp_48x4096_arch : ARCHITECTURE IS "memory_dp_48x4096,blk_mem_gen_v8_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF memory_dp_48x4096_arch: ARCHITECTURE IS "memory_dp_48x4096,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2014.3.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=2,x_ipLanguage=VERILOG,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=8,C_ALGORITHM=0,C_PRIM_TYPE=3,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=memory_dp_48x4096.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=1,C_WEA_WIDTH=6,C_WRITE_MODE_A=NO_CHANGE,C_WRITE_WIDTH_A=48,C_READ_WIDTH_A=48,C_WRITE_DEPTH_A=4096,C_READ_DEPTH_A=4096,C_ADDRA_WIDTH=12,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=1,C_HAS_REGCEB=0,C_USE_BYTE_WEB=1,C_WEB_WIDTH=6,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=48,C_READ_WIDTH_B=48,C_WRITE_DEPTH_B=4096,C_READ_DEPTH_B=4096,C_ADDRB_WIDTH=12,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=6,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 27.3621 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF enb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 1,
C_BYTE_SIZE => 8,
C_ALGORITHM => 0,
C_PRIM_TYPE => 3,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "memory_dp_48x4096.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 1,
C_WEA_WIDTH => 6,
C_WRITE_MODE_A => "NO_CHANGE",
C_WRITE_WIDTH_A => 48,
C_READ_WIDTH_A => 48,
C_WRITE_DEPTH_A => 4096,
C_READ_DEPTH_A => 4096,
C_ADDRA_WIDTH => 12,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 1,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 1,
C_WEB_WIDTH => 6,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 48,
C_READ_WIDTH_B => 48,
C_WRITE_DEPTH_B => 4096,
C_READ_DEPTH_B => 4096,
C_ADDRB_WIDTH => 12,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "6",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 27.3621 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
rstb => '0',
enb => enb,
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
addrb => addrb,
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 48)),
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 48)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END memory_dp_48x4096_arch;
| gpl-3.0 | 8a6236feecd0305940f28268fa419773 | 0.633519 | 3.037029 | false | false | false | false |
DougFirErickson/parallella-hw | fpga/ip/xilinx/fifo_async_103x32/fifo_generator_v12_0/hdl/ramfifo/rd_status_flags_sshft.vhd | 6 | 19,232 | `protect begin_protected
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12496)
`protect data_block
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| gpl-3.0 | f58b3535a454110224aaa6e7943f065a | 0.938852 | 1.841969 | false | false | false | false |
dskntIndustry/Hardware | platform_specific/mimas/hdl/MimasTop.vhd | 1 | 1,115 | library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.std_logic_arith.ALL;
use IEEE.std_logic_unsigned.ALL;
library hdl_library_ClockGenerator;
use hdl_library_ClockGenerator.all;
entity MimasTop is
port
(
clock : in std_logic;
status_led : out std_logic;
top_clock_output : out std_logic
);
end entity; --MimasTop
architecture arch of MimasTop is
constant G_CLOCK_FREQUENCY : integer := 512;
constant G_BASE_FREQUENCY : integer := 12E6;
constant G_CLOCK_DIVIDER : integer := 10;
signal enable : std_logic := '1';
signal clock_output : std_logic := '0';
signal clock_output_n : std_logic := '0';
begin
status_led <= '1';
clock_generator : entity hdl_library_ClockGenerator.ClockGenerator
generic map
(
G_CLOCK_FREQUENCY => G_CLOCK_FREQUENCY,
G_CLOCK_DIVIDER => G_CLOCK_DIVIDER
)
port map
(
clock => clock,
enable => enable,
-- module clock output
clock_output => clock_output,
clock_output_n => clock_output_n
);
top_clock_output <= clock_output;
end architecture; -- arch
| gpl-3.0 | 047bbaac3aaa6e5ed756c6d859607c2d | 0.639462 | 2.934211 | false | false | false | false |
DougFirErickson/parallella-hw | fpga/ip/xilinx/memory_dp_48x4096/blk_mem_gen_v8_2/hdl/blk_mem_gen_ecc_decoder.vhd | 8 | 24,873 | `protect begin_protected
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`protect end_protected
| gpl-3.0 | 5a8b34c31bce41b899ce7fd37ae54a6d | 0.942387 | 1.846822 | false | false | false | false |
dskntIndustry/Hardware | hdl_library/SPI/SPI_MasterTB.vhd | 1 | 1,100 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SPI_MasterTB is
end entity; --SPI_MasterTB
architecture tb of SPI_MasterTB is
constant G_CLOCK_FREQUENCY : integer := 100E6;
constant G_CLOCK_DIVIDER : integer := 100;
constant G_SPI_TRANSACTION_SIZE : integer := 32;
--declarations
signal clock : std_logic := '0';
signal clock_n : std_logic := '0';
signal enable : std_logic := '0';
signal clock_divider1 : integer := 1000;
signal clock_output1 : std_logic := '0';
begin
clock <= not clock after (1 sec / G_CLOCK_FREQUENCY) / 2;
clock_n <= not clock;
Test:process
begin
wait for 100 ns;
enable <= '1';
wait for 10 us;
enable <= '0';
wait for 1 ms;
end process; --Test
dut : entity work.SPI_Master
generic map
(
G_CLOCK_FREQUENCY => G_CLOCK_FREQUENCY,
G_SPI_FREQUENCY => G_SPI_FREQUENCY,
G_SPI_TRANSACTION_SIZE => G_SPI_TRANSACTION_SIZE
)
port map
(
clock => clock,
enable => enable
);
end architecture; -- tb | gpl-3.0 | 4262b95fc47b126360df154378dc61d7 | 0.626364 | 2.894737 | false | false | false | false |
JuanMarcosRamirez/WeightedMedianDisenoLogico | misc/RS232/Rs232 RefProj/SourceFiles/DataCntrl.vhd | 3 | 9,205 | -------------------------------------------------------------------------
-- main.vhd
-------------------------------------------------------------------------
-- Author: Dan Pederson
-- Copyright 2004 Digilent, Inc.
-------------------------------------------------------------------------
-- Description: This file tests the included UART component by
-- sending data in serial form through the UART to
-- change it to parallel form, and then sending the
-- resultant data back through the UART to determine if
-- the signal is corrupted or not. When the serial
-- information is converted into parallel information,
-- the data byte is displayed on the 8 LEDs on the
-- system board.
--
-- NOTE: Not all mapped signals are used in this test.
-- The signals were mapped to ease the modification of
-- test program.
-------------------------------------------------------------------------
-- Revision History:
-- 07/30/04 (DanP) Created
-- 05/26/05 (DanP) Modified for Pegasus board/Updated commenting style
-- 06/07/05 (DanP) LED scancode display added
-------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-------------------------------------------------------------------------
--
--Title: Main entity
--
--Inputs: 3 : RXD
-- CLK
-- RST
--
--Outputs: 1 : TXD
-- LEDS
--
--Description: This describes the main entity that tests the included
-- UART component. The LEDS signals are used to
-- display the data byte on the LEDs, so it is set equal to
-- the dbOutSig. Technically, the dbOutSig is the scan code
-- backwards, which explains why the LEDs are mapped
-- backwards to the dbOutSig.
--
-------------------------------------------------------------------------
entity DataCntrl is
Port ( TXD : out std_logic := '1';
RXD : in std_logic := '1';
CLK : in std_logic;
LEDS : out std_logic_vector(7 downto 0) := "11111111";
RST : in std_logic := '0');
end DataCntrl;
architecture Behavioral of DataCntrl is
-------------------------------------------------------------------------
-- Local Component, Type, and Signal declarations.
-------------------------------------------------------------------------
-------------------------------------------------------------------------
--
--Title: Component Declarations
--
--Description: This component is the UART that is to be tested.
-- The UART code can be found in the included
-- RS232RefComp.vhd file.
--
-------------------------------------------------------------------------
component RS232RefComp
Port ( TXD : out std_logic := '1';
RXD : in std_logic;
CLK : in std_logic;
DBIN : in std_logic_vector (7 downto 0);
DBOUT : out std_logic_vector (7 downto 0);
RDA : inout std_logic;
TBE : inout std_logic := '1';
RD : in std_logic;
WR : in std_logic;
PE : out std_logic;
FE : out std_logic;
OE : out std_logic;
RST : in std_logic := '0');
end component;
-------------------------------------------------------------------------
--
--Title: Type Declarations
--
--Description: There is one state machine used in this program, called
-- the mainState state machine. This state machine controls
-- the flow of data around the UART; allowing for data to be
-- changed from serial to parallel, and then back to serial.
--
-------------------------------------------------------------------------
type mainState is (
stReceive,
stSend);
-------------------------------------------------------------------------
--
--Title: Local Signal Declarations
--
--Description: The signals used by this entity are described below:
--
-- -dbInSig : This signal is the parallel data input
-- for the UART
-- -dbOutSig : This signal is the parallel data output
-- for the UART
-- -rdaSig : This signal will get the RDA signal from
-- the UART
-- -tbeSig : This signal will get the TBE signal from
-- the UART
-- -rdSig : This signal is the RD signal for the UART
-- -wrSig : This signal is the WR signal for the UART
-- -peSig : This signal will get the PE signal from
-- the UART
-- -feSig : This signal will get the FE signal from
-- the UART
-- -oeSig : This signal will get the OE signal from
-- the UART
--
-- The following signals are used by the main state machine
-- for state control:
--
-- -stCur, stNext
--
-------------------------------------------------------------------------
signal dbInSig : std_logic_vector(7 downto 0);
signal dbOutSig : std_logic_vector(7 downto 0);
signal rdaSig : std_logic;
signal tbeSig : std_logic;
signal rdSig : std_logic;
signal wrSig : std_logic;
signal peSig : std_logic;
signal feSig : std_logic;
signal oeSig : std_logic;
signal stCur : mainState := stReceive;
signal stNext : mainState;
------------------------------------------------------------------------
-- Module Implementation
------------------------------------------------------------------------
begin
------------------------------------------------------------------------
--
--Title: LED definitions
--
--Description: This series of definitions allows the scan code to be
-- displayed on the LEDs on the FPGA system board. Because the
-- dbOutSig is the scan code backwards, the LEDs must be
-- defined backwards from the dbOutSig.
--
------------------------------------------------------------------------
LEDS(7) <= dbOutSig(0);
LEDS(6) <= dbOutSig(1);
LEDS(5) <= dbOutSig(2);
LEDS(4) <= dbOutSig(3);
LEDS(3) <= dbOutSig(4);
LEDS(2) <= dbOutSig(5);
LEDS(1) <= dbOutSig(6);
LEDS(0) <= dbOutSig(7);
-------------------------------------------------------------------------
--
--Title: RS232RefComp map
--
--Description: This maps the signals and ports in main to the
-- RS232RefComp. The TXD, RXD, CLK, and RST of main are
-- directly tied to the TXD, RXD, CLK, and RST of the
-- RS232RefComp. The remaining RS232RefComp ports are
-- mapped to internal signals in main.
--
-------------------------------------------------------------------------
UART: RS232RefComp port map ( TXD => TXD,
RXD => RXD,
CLK => CLK,
DBIN => dbInSig,
DBOUT => dbOutSig,
RDA => rdaSig,
TBE => tbeSig,
RD => rdSig,
WR => wrSig,
PE => peSig,
FE => feSig,
OE => oeSig,
RST => RST);
-------------------------------------------------------------------------
--
--Title: Main State Machine controller
--
--Description: This process takes care of the Main state machine
-- movement. It causes the next state to be evaluated on
-- each rising edge of CLK. If the RST signal is strobed,
-- the state is changed to the default starting state, which
-- is stReceive.
--
-------------------------------------------------------------------------
process (CLK, RST)
begin
if (CLK = '1' and CLK'Event) then
if RST = '1' then
stCur <= stReceive;
else
stCur <= stNext;
end if;
end if;
end process;
-------------------------------------------------------------------------
--
--Title: Main State Machine
--
--Description: This process defines the next state logic for the Main
-- state machine. The main state machine controls the data
-- flow for this testing program in order to send and
-- receive data.
--
-------------------------------------------------------------------------
process (stCur, rdaSig, dboutsig)
begin
case stCur is
-------------------------------------------------------------------------
--
--Title: stReceive state
--
--Description: This state waits for the UART to receive data. While in
-- this state, the rdSig and wrSig are held low to keep the
-- UART from transmitting any data. Once the rdaSig is set
-- high, data has been received, and is safe to transmit. At
-- this time, the stSend state is loaded, and the dbOutSig
-- is copied to the dbInSig in order to transmit the newly
-- acquired parallel information.
--
-------------------------------------------------------------------------
when stReceive =>
rdSig <= '0';
wrSig <= '0';
if rdaSig = '1' then
dbInSig <= dbOutSig;
stNext <= stSend;
else
stNext <= stReceive;
end if;
-------------------------------------------------------------------------
--
--Title: stSend state
--
--Description: This state tells the UART to send the parallel
-- information found in dbInSig. It does this by strobing
-- both the rdSig and wrSig signals high. Once these
-- signals have been strobed high, the stReceive state is
-- loaded.
--
-------------------------------------------------------------------------
when stSend =>
rdSig <= '1';
wrSig <= '1';
stNext <= stReceive;
end case;
end process;
end Behavioral; | gpl-3.0 | a1788ea627c3ddbc7262e0b0d0e86a06 | 0.484954 | 3.84182 | false | false | false | false |
DougFirErickson/parallella-hw | fpga/ip/xilinx/memory_dp_48x4096/blk_mem_gen_v8_2/hdl/blk_mem_min_area_pkg.vhd | 8 | 20,310 | `protect begin_protected
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| gpl-3.0 | 49002a8997fb5dead6bc6a3040b68c14 | 0.941654 | 1.854795 | false | false | false | false |
rflamino/StellaBlue | core/A2601Master.vhd | 1 | 7,663 | -- A2601 Top Level Entity (ROM stored in on-chip RAM)
-- Copyright 2006, 2010 Retromaster
--
-- This file is part of A2601.
--
-- A2601 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License,
-- or any later version.
--
-- A2601 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with A2601. If not, see <http://www.gnu.org/licenses/>.
--
-- This top level entity supports a single cartridge ROM stored in FPGA built-in
-- memory (such as Xilinx Spartan BlockRAM). To generate the required cart_rom
-- entity, use bin2vhdl.py found in the util directory.
--
-- For more information, see the A2601 Rev B Board Schematics and project
-- website at <http://retromaster.wordpress.org/a2601>.
-- 9 pin d-sub joystick pinout:
-- pin 1: up
-- pin 2: down
-- pin 3: left
-- pin 4: right
-- pin 6: fire
-- Atari 2600, 6532 ports:
-- PA0: right joystick, up
-- PA1: right joystick, down
-- PA2: right joystick, left
-- PA3: right joystick, right
-- PA4: left joystick, up
-- PA5: left joystick, down
-- PA6: left joystick, left
-- PA7: left joystick, right
-- PB0: start
-- PB1: select
-- PB3: B/W, color
-- PB6: left difficulty
-- PB7: right difficulty
-- Atari 2600, TIA input:
-- I5: right joystick, fire
-- I6: left joystick, fire
library std;
use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity A2601Master is
port (vid_clk: in std_logic;
pa_in: in std_logic_vector(7 downto 0);
pb_in: in std_logic_vector(7 downto 0);
inpt0_in: in std_logic;
inpt1_in: in std_logic;
inpt2_in: in std_logic;
inpt3_in: in std_logic;
inpt4_in: in std_logic;
inpt5_in: in std_logic;
d_in: in std_logic_vector(7 downto 0);
a_out: out std_logic_vector(12 downto 0);
cv: out std_logic_vector(7 downto 0);
vsyn: out std_logic;
hsyn: out std_logic;
au: out std_logic_vector(4 downto 0);
dump_pin:out std_logic;
res: in std_logic);
end A2601Master;
architecture arch of A2601Master is
component A2601 is
port(vid_clk: in std_logic;
rst: in std_logic;
d: inout std_logic_vector(7 downto 0);
a: out std_logic_vector(12 downto 0);
r: out std_logic;
pa: inout std_logic_vector(7 downto 0);
pb: inout std_logic_vector(7 downto 0);
paddle_0: in std_logic_vector(7 downto 0);
paddle_1: in std_logic_vector(7 downto 0);
paddle_2: in std_logic_vector(7 downto 0);
paddle_3: in std_logic_vector(7 downto 0);
paddle_ena: in std_logic;
inpt4: in std_logic;
inpt5: in std_logic;
colu: out std_logic_vector(6 downto 0);
csyn: out std_logic;
vsyn: out std_logic;
hsyn: out std_logic;
rgbx2: out std_logic_vector(23 downto 0);
cv: out std_logic_vector(7 downto 0);
au0: out std_logic;
au1: out std_logic;
av0: out std_logic_vector(3 downto 0);
av1: out std_logic_vector(3 downto 0);
ph0_out: out std_logic;
ph1_out: out std_logic;
pal: in std_logic);
end component;
component debounce is
GENERIC(
NDELAY : INTEGER := 10000;
NBITS : INTEGER := 20
);
Port (
reset : in std_logic;
clk : in std_logic;
noisy : in std_logic;
clean : out std_logic
);
end component;
signal clk : std_logic;
signal noisy : std_logic;
signal clean : std_logic;
signal dbounce_pb: std_logic_vector(1 downto 0) := "00";
--signal vid_clk: std_logic;
signal cpu_d: std_logic_vector(7 downto 0);
--signal d: std_logic_vector(7 downto 0);
signal cpu_a: std_logic_vector(12 downto 0);
--signal a: std_logic_vector(12 downto 0);
signal cpu_r: std_logic;
signal pa: std_logic_vector(7 downto 0);
signal pb: std_logic_vector(7 downto 0);
signal paddle_0: std_logic_vector(7 downto 0);
signal paddle_1: std_logic_vector(7 downto 0);
signal paddle_2: std_logic_vector(7 downto 0);
signal paddle_3: std_logic_vector(7 downto 0);
signal inpt4: std_logic;
signal inpt5: std_logic;
signal colu: std_logic_vector(6 downto 0);
signal csyn: std_logic;
signal au0: std_logic;
signal au1: std_logic;
signal av0: std_logic_vector(3 downto 0);
signal av1: std_logic_vector(3 downto 0);
signal auv0: unsigned(4 downto 0);
signal auv1: unsigned(4 downto 0);
-- signal rst: std_logic;
signal rst: std_logic := '1';
signal sys_clk_dvdr: unsigned(4 downto 0) := "00000";
signal ph0: std_logic;
signal ph1: std_logic;
signal pal: std_logic := '0'; -- NTSC
begin
-- ms_A2601: A2601
-- port map(vid_clk, rst, cpu_d, cpu_a, cpu_r,pa, pb,paddle_0, paddle_1, paddle_2, paddle_3, paddle_ena,inpt4, inpt5, open, open, vsyn, hsyn, rgbx2, cv,au0, au1, av0, av1, ph0, ph1, pal);
ms_A2601: A2601
port map(vid_clk, rst, cpu_d, cpu_a, cpu_r,pa, pb,paddle_0, paddle_1, paddle_2, paddle_3, '0' ,inpt4, inpt5, open, open, vsyn, hsyn, open, cv,au0, au1, av0, av1, ph0, ph1, pal);
a_out <= cpu_a;
process(cpu_a,d_in)
begin
if (cpu_a(12) = '1') then
cpu_d <= d_in;
else
cpu_d <= "ZZZZZZZZ";
end if;
end process;
--dump_pin <= ph0;
-- inpt0 <= inpt0_in;
-- inpt1 <= inpt1_in;
-- inpt2 <= inpt2_in;
-- inpt3 <= inpt3_in;
inpt4 <= inpt4_in;
--inpt5 <= inpt5_in;
inpt5 <= '1';
-- Atari 2600, 6532 ports:
-- PA0: right joystick, up
-- PA1: right joystick, down
-- PA2: right joystick, left
-- PA3: right joystick, right
-- PA4: left joystick, up
-- PA5: left joystick, down
-- PA6: left joystick, left
-- PA7: left joystick, right
-- PB0: start
-- PB1: select
-- PB3: B/W, color
-- PB6: left difficulty
-- PB7: right difficulty
pa(7 downto 4) <= pa_in(7 downto 4); -- left joystick
pa(3 downto 0) <= "1111"; -- right joystick
pb(7 downto 6) <= pb_in(7 downto 6); -- PB6: left difficulty ; PB7: right difficulty
pb(5 downto 4) <= "00";
pb(3) <= pb_in(3); -- B/W
pb(2) <= '0';
-- pb(1) <= pb_in(1); -- select
-- pb(0) <= pb_in(0); -- start
ms_dbounce0: debounce port map( res,vid_clk ,pb_in(0),pb(0));
ms_dbounce1: debounce port map( res,vid_clk ,pb_in(1),pb(1));
auv0 <= ("0" & unsigned(av0)) when (au0 = '1') else "00000";
auv1 <= ("0" & unsigned(av1)) when (au1 = '1') else "00000";
au <= std_logic_vector(auv0 + auv1);
process(vid_clk, sys_clk_dvdr)
begin
if (vid_clk'event and vid_clk = '1') then
sys_clk_dvdr <= sys_clk_dvdr + 1;
if (sys_clk_dvdr = "11101") then
rst <= '0';
end if;
end if;
end process;
-- process(vid_clk, sys_clk_dvdr,res)
-- begin
-- if (vid_clk'event and vid_clk = '1' ) then
--
-- if (res = '1') then
-- rst <= '1';
-- else
-- sys_clk_dvdr <= sys_clk_dvdr + 1;
-- end if;
--
-- if (sys_clk_dvdr = "100") then
-- rst <= '0';
-- sys_clk_dvdr <= "000";
-- end if;
--
-- end if;
--
--
-- end process;
end arch;
| mit | f13f4dcc85898913e788df8c1786aa7b | 0.590239 | 2.925926 | false | false | false | false |
SebastianCallh/copter-modern | copter_modern_tb.vhd | 1 | 845 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity copter_modern_tb is
end copter_modern_tb;
architecture Behavioral of copter_modern_tb is
component copter_modern
Port (clk : in std_logic;
rst : in std_logic;
PS2KeyboardCLK : in std_logic;
PS2KeyboardData : in std_logic
);
end component;
-- Testsignaler
signal clk : std_logic;
signal rst : std_logic;
signal PS2KeyboardCLK : std_logic;
signal PS2KeyboardData : std_logic;
begin
main: copter_modern port map(clk => clk,
rst => rst,
PS2KeyboardCLK => PS2KeyboardCLK,
PS2KeyboardData => PS2KeyboardData);
-- Klocksignal 100MHz
clk <= not clk after 5 ns;
end;
| mit | 28bfffd3605db1e83be2b887dd4ed5a7 | 0.604734 | 3.626609 | false | false | false | false |
estadofinito/biblioteca-vhdl | todos-los-archivos/bin2bcd9.vhd | 4 | 1,877 | ----------------------------------------------------------------------------------
-- Compañía: Estado Finito
-- Ingeniero: Carlos Ramos
--
-- Fecha de creación: 2014/04/24 23:21:40
-- Nombre del módulo: bin2bcd9 - Behavioral
-- Comentarios adicionales:
-- Este componente se encarga de transformar un número binario de nueve bits
-- a tres dígitos en código BCD.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity bin2bcd9 is
GENERIC(
NBITS : integer := 9; -- Cantidad de bits del número binario.
NSALIDA: integer := 11 -- Cantidad de bits de salida en formato BCD.
);
PORT(
num_bin: in STD_LOGIC_VECTOR(NBITS-1 downto 0);
num_bcd: out STD_LOGIC_VECTOR(NSALIDA-1 downto 0)
);
end bin2bcd9;
architecture Behavioral of bin2bcd9 is
begin
proceso_bcd: process(num_bin)
variable z: STD_LOGIC_VECTOR(NBITS+NSALIDA-1 downto 0);
begin
-- Inicialización de datos en cero.
z := (others => '0');
-- Se realizan los primeros tres corrimientos.
z(NBITS+2 downto 3) := num_bin;
-- Ciclo para las iteraciones restantes.
for i in 0 to NBITS-4 loop
-- Unidades (4 bits).
if z(NBITS+3 downto NBITS) > 4 then
z(NBITS+3 downto NBITS) := z(NBITS+3 downto NBITS) + 3;
end if;
-- Decenas (4 bits).
if z(NBITS+7 downto NBITS+4) > 4 then
z(NBITS+7 downto NBITS+4) := z(NBITS+7 downto NBITS+4) + 3;
end if;
-- Centenas (3 bits).
if z(NBITS+10 downto NBITS+8) > 4 then
z(NBITS+10 downto NBITS+8) := z(NBITS+10 downto NBITS+8) + 3;
end if;
-- Corrimiento a la izquierda.
z(NBITS+NSALIDA-1 downto 1) := z(NBITS+NSALIDA-2 downto 0);
end loop;
-- Pasando datos de variable Z, correspondiente a BCD.
num_bcd <= z(NBITS+NSALIDA-1 downto NBITS);
end process;
end Behavioral; | lgpl-2.1 | ed9478d593633cce1483bfe30aa327e3 | 0.607885 | 3.037217 | false | false | false | false |
JuanMarcosRamirez/WeightedMedianDisenoLogico | misc/FPGA/otros/loopback/led.vhd | 1 | 8,628 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity tope_rof512_uart is --Entidad
Port ( --17/05/08 cambio I tx_female : out std_logic; --Entidad
LED : out std_logic_vector(7 downto 0);
rx_female : in std_logic; --Entidad
RSTn : in std_logic; --Entidad
clk : in std_logic); --Entidad
end tope_rof512_uart; --Entidad
architecture Comportamiento of tope_rof512_uart is-----------------Arquitectura
--17/05/08 cambio I component uart_tx_plus --comp uart_tx_plus
--17/05/08 cambio I Port ( data_in : in std_logic_vector(7 downto 0);--comp uart_tx_plus
--17/05/08 cambio I write_buffer : in std_logic; --comp uart_tx_plus
--17/05/08 cambio I reset_buffer : in std_logic; --comp uart_tx_plus
--17/05/08 cambio I en_16_x_baud : in std_logic; --comp uart_tx_plus
--17/05/08 cambio I serial_out : out std_logic; --comp uart_tx_plus
--17/05/08 cambio I buffer_data_present : out std_logic; --comp uart_tx_plus
--17/05/08 cambio I buffer_full : out std_logic; --comp uart_tx_plus
--17/05/08 cambio I buffer_half_full : out std_logic; --comp uart_tx_plus
--17/05/08 cambio I clk : in std_logic); --comp uart_tx_plus
--17/05/08 cambio I end component;
component uart_rx --comp uart_rx
Port ( serial_in : in std_logic; --comp uart_rx
data_out : out std_logic_vector(7 downto 0); --comp uart_rx
read_buffer : in std_logic; --comp uart_rx
reset_buffer : in std_logic; --comp uart_rx
en_16_x_baud : in std_logic; --comp uart_rx
buffer_data_present : out std_logic; --comp uart_rx
buffer_full : out std_logic; --comp uart_rx
buffer_half_full : out std_logic; --comp uart_rx
clk : in std_logic); --comp uart_rx
end component; --comp uart_rx
signal cambio : std_logic :='0';
signal Dfilt : std_logic_vector(7 downto 0);
signal interrupt : std_logic :='0'; --señales
signal interrupt_ack : std_logic; --señales
--señales
--señales
signal baud_count : integer range 0 to 26 :=0; --señales
signal en_16_x_baud : std_logic; --señales
signal write_to_uart : std_logic; --señales
signal tx_data_present : std_logic; --señales
signal tx_full : std_logic; --señales
signal tx_half_full : std_logic; --señales
signal read_from_uart : std_logic :='0'; --señales
signal rx_data : std_logic_vector(7 downto 0); --señales
signal rx_data_present : std_logic; --señales
signal rx_full : std_logic; --señales
signal rx_half_full : std_logic; --señales
--señales
signal previous_rx_half_full : std_logic; --señales
signal rx_half_full_event : std_logic; --señales
begin --------------------------------------------- Comienzo de procesos y portmaps
interrupt_control: process(clk) --Control de transmisión
begin --Control de transmisión
if clk'event and clk='1' then --Control de transmisión
--Control de transmisión
-- detect change in state of the 'rx_half_full' flag. --Control de transmisión
previous_rx_half_full <= rx_half_full; --Control de transmisión
rx_half_full_event <= previous_rx_half_full xor rx_half_full;--Control de transmisión
--Control de transmisión
-- processor interrupt waits for an acknowledgement --Control de transmisión
if interrupt_ack='1' then --Control de transmisión
interrupt <= '0'; --Control de transmisión
elsif rx_half_full_event='1' then --Control de transmisión
interrupt <= '1'; --Control de transmisión
else --Control de transmisión
interrupt <= interrupt; --Control de transmisión
end if; --Control de transmisión
--Control de transmisión
end if; --Control de transmisión
end process interrupt_control; --Control de transmisión
--17/05/08 cambio I transmit: uart_tx_plus
--17/05/08 cambio I port map ( data_in => rx_data,
--17/05/08 cambio I write_buffer => rx_data_present,
--17/05/08 cambio I reset_buffer => '0',
--17/05/08 cambio I en_16_x_baud => en_16_x_baud,
--17/05/08 cambio I serial_out => tx_female,
--17/05/08 cambio I buffer_data_present => tx_data_present,--Pruebo: desconectado
--17/05/08 cambio I buffer_full => tx_full, --Pruebo: desconectado
--17/05/08 cambio I buffer_half_full => tx_half_full, --Pruebo: desconectado
--17/05/08 cambio I clk => clk );
--17/05/08 cambio I
receive: uart_rx
port map ( serial_in => rx_female,
data_out => rx_data,
read_buffer => read_from_uart, -- Atención:fijar read_from_uart (indica lectura en el macro)
reset_buffer => '0',
en_16_x_baud => en_16_x_baud,
buffer_data_present => rx_data_present,--Pruebo: desconectado
buffer_full => rx_full, --Pruebo: desconectado
buffer_half_full => rx_half_full, --Pruebo: desconectado
clk => clk );
LED(7) <= cambio;
LED(6) <= rx_data(6);
LED(5) <= rx_data(5);
LED(4) <= rx_data(4);
LED(3) <= rx_data(3);
LED(2) <= rx_data(2);
LED(1) <= rx_data(1);
LED(0) <= rx_data(0);
toggle: process(rx_data_present)
begin
if rx_data_present'event and rx_data_present='1' then
if cambio='0' then
cambio <= '1';
else
cambio <= '0';
end if;
else
end if;
end process toggle;
baud_timer: process(clk) --Generación de en_16_x_baud
begin --Generación de en_16_x_baud
if clk'event and clk='1' then --Generación de en_16_x_baud
if baud_count=26 then --Generación de en_16_x_baud
baud_count <= 0; --Generación de en_16_x_baud
en_16_x_baud <= '1'; --Generación de en_16_x_baud
else --Generación de en_16_x_baud
baud_count <= baud_count + 1; --Generación de en_16_x_baud
en_16_x_baud <= '0'; --Generación de en_16_x_baud
end if; --Generación de en_16_x_baud
end if; --Generación de en_16_x_baud
end process baud_timer; --Generación de en_16_x_baud
inicio: process(rx_female)
begin
if rx_female'event and rx_female='0' then
read_from_uart <= '1';
else
end if;
end process inicio;
end Comportamiento;
| gpl-3.0 | 1e18da2f666541bc1811f14992a76684 | 0.450278 | 4.138129 | false | false | false | false |
DougFirErickson/parallella-hw | fpga/ip/xilinx/fifo_async_103x32/fifo_generator_v12_0/hdl/common/shft_ram.vhd | 6 | 17,157 | `protect begin_protected
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| gpl-3.0 | 0d56633eb67b89b09e840b49dacfe676 | 0.937343 | 1.859233 | false | false | false | false |
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| gpl-3.0 | 5a563ae5800243c634a07eff5bcf085e | 0.947153 | 1.84333 | false | false | false | false |
estadofinito/biblioteca-vhdl | todos-los-archivos/siete_segmentos_mux.vhd | 4 | 2,535 | ----------------------------------------------------------------------------------
-- Compañía: Estado Finito
-- Ingeniero: Carlos Ramos
--
-- Fecha de creación: 2012/07/30 12:15:56
-- Nombre del módulo: siete_segmentos_mux - Behavioral
-- Descripción:
-- Multiplexor (de frecuencia) para mostrar un valor diferente en cada uno de
-- los visualizadores de siete segmentos. Esto se logra activando solamente un
-- visualizador a la vez y mandar el dato correspondiente. Si la frecuencia es
-- mayor a 16Hz por visualizador, no habrá parpadeo perceptible.
-- Diseñado para Basys2 de Digilent.
-- Comentarios adicionales:
-- Se puede encontrar más información en la siguiente dirección:
-- http://www.estadofinito.com/multiplexores-siete-segmentos/
-- Revisión:
-- Revisión 0.01 - Archivo creado.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity siete_segmentos_mux is
PORT (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
D0 : IN STD_LOGIC_VECTOR(5 downto 0); --Primer dígito.
D1 : IN STD_LOGIC_VECTOR(5 downto 0); --Segundo dígito.
D2 : IN STD_LOGIC_VECTOR(5 downto 0); --Tercer dígito.
D3 : IN STD_LOGIC_VECTOR(5 downto 0); --Cuarto dígito.
salida: OUT STD_LOGIC_VECTOR(5 downto 0); --Salida del multiplexor (valor a desplegar).
MUX : OUT STD_LOGIC_VECTOR(3 downto 0) --Valor que define cual dígito se va a mostrar.
);
end siete_segmentos_mux;
architecture Behavioral of siete_segmentos_mux is
type estados is (rst, v0, v1, v2, v3);
signal estado : estados;
begin
visualizadores: process (reset, clk) begin
if (reset = '1') then
estado <= rst;
MUX <= x"F";
salida <= "111111";
elsif rising_edge(clk) then
case estado is
when v0 =>
salida <= D3;
MUX <= "1110";
estado <= v1;
when v1 =>
salida <= D2;
MUX <= "1101";
estado <= v2;
when v2 =>
salida <= D1;
MUX <= "1011";
estado <= v3;
when others =>
salida <= D0;
MUX <= "0111";
estado <= v0;
end case;
end if;
end process;
end Behavioral; | lgpl-2.1 | c89211b5a2900893a5e32c04c51475bf | 0.511517 | 3.856049 | false | false | false | false |
DougFirErickson/parallella-hw | fpga/ip/xilinx/fifo_async_103x32/fifo_async_103x32_funcsim.vhdl | 1 | 241,259 | -- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.3.1 (lin64) Build 1056140 Thu Oct 30 16:30:39 MDT 2014
-- Date : Wed Apr 8 23:17:41 2015
-- Host : parallella running 64-bit Ubuntu 14.04.2 LTS
-- Command : write_vhdl -force -mode funcsim
-- /home/aolofsson/Work_all/parallella-hw/fpga/ip/xilinx/fifo_async_103x32/fifo_async_103x32_funcsim.vhdl
-- Design : fifo_async_103x32
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x32_dmem is
port (
Q : out STD_LOGIC_VECTOR ( 102 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC;
I1 : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_clk : in STD_LOGIC;
I2 : in STD_LOGIC_VECTOR ( 0 to 0 );
din : in STD_LOGIC_VECTOR ( 102 downto 0 );
O2 : in STD_LOGIC_VECTOR ( 4 downto 0 );
O1 : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x32_dmem : entity is "dmem";
end fifo_async_103x32_dmem;
architecture STRUCTURE of fifo_async_103x32_dmem is
signal p_0_out : STD_LOGIC_VECTOR ( 102 downto 0 );
signal NLW_RAM_reg_0_31_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_102_102_DOA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_RAM_reg_0_31_102_102_DOB_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_102_102_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_102_102_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_36_41_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_42_47_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_48_53_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_54_59_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_60_65_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_66_71_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_72_77_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_78_83_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_84_89_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_90_95_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_96_101_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
RAM_reg_0_31_0_5: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => O2(4 downto 0),
ADDRB(4 downto 0) => O2(4 downto 0),
ADDRC(4 downto 0) => O2(4 downto 0),
ADDRD(4 downto 0) => O1(4 downto 0),
DIA(1 downto 0) => din(1 downto 0),
DIB(1 downto 0) => din(3 downto 2),
DIC(1 downto 0) => din(5 downto 4),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(1 downto 0),
DOB(1 downto 0) => p_0_out(3 downto 2),
DOC(1 downto 0) => p_0_out(5 downto 4),
DOD(1 downto 0) => NLW_RAM_reg_0_31_0_5_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => I2(0)
);
RAM_reg_0_31_102_102: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => O2(4 downto 0),
ADDRB(4 downto 0) => O2(4 downto 0),
ADDRC(4 downto 0) => O2(4 downto 0),
ADDRD(4 downto 0) => O1(4 downto 0),
DIA(1) => '0',
DIA(0) => din(102),
DIB(1) => '0',
DIB(0) => '0',
DIC(1) => '0',
DIC(0) => '0',
DID(1) => '0',
DID(0) => '0',
DOA(1) => NLW_RAM_reg_0_31_102_102_DOA_UNCONNECTED(1),
DOA(0) => p_0_out(102),
DOB(1 downto 0) => NLW_RAM_reg_0_31_102_102_DOB_UNCONNECTED(1 downto 0),
DOC(1 downto 0) => NLW_RAM_reg_0_31_102_102_DOC_UNCONNECTED(1 downto 0),
DOD(1 downto 0) => NLW_RAM_reg_0_31_102_102_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => I2(0)
);
RAM_reg_0_31_12_17: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => O2(4 downto 0),
ADDRB(4 downto 0) => O2(4 downto 0),
ADDRC(4 downto 0) => O2(4 downto 0),
ADDRD(4 downto 0) => O1(4 downto 0),
DIA(1 downto 0) => din(13 downto 12),
DIB(1 downto 0) => din(15 downto 14),
DIC(1 downto 0) => din(17 downto 16),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(13 downto 12),
DOB(1 downto 0) => p_0_out(15 downto 14),
DOC(1 downto 0) => p_0_out(17 downto 16),
DOD(1 downto 0) => NLW_RAM_reg_0_31_12_17_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => I2(0)
);
RAM_reg_0_31_18_23: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => O2(4 downto 0),
ADDRB(4 downto 0) => O2(4 downto 0),
ADDRC(4 downto 0) => O2(4 downto 0),
ADDRD(4 downto 0) => O1(4 downto 0),
DIA(1 downto 0) => din(19 downto 18),
DIB(1 downto 0) => din(21 downto 20),
DIC(1 downto 0) => din(23 downto 22),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(19 downto 18),
DOB(1 downto 0) => p_0_out(21 downto 20),
DOC(1 downto 0) => p_0_out(23 downto 22),
DOD(1 downto 0) => NLW_RAM_reg_0_31_18_23_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => I2(0)
);
RAM_reg_0_31_24_29: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => O2(4 downto 0),
ADDRB(4 downto 0) => O2(4 downto 0),
ADDRC(4 downto 0) => O2(4 downto 0),
ADDRD(4 downto 0) => O1(4 downto 0),
DIA(1 downto 0) => din(25 downto 24),
DIB(1 downto 0) => din(27 downto 26),
DIC(1 downto 0) => din(29 downto 28),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(25 downto 24),
DOB(1 downto 0) => p_0_out(27 downto 26),
DOC(1 downto 0) => p_0_out(29 downto 28),
DOD(1 downto 0) => NLW_RAM_reg_0_31_24_29_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => I2(0)
);
RAM_reg_0_31_30_35: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => O2(4 downto 0),
ADDRB(4 downto 0) => O2(4 downto 0),
ADDRC(4 downto 0) => O2(4 downto 0),
ADDRD(4 downto 0) => O1(4 downto 0),
DIA(1 downto 0) => din(31 downto 30),
DIB(1 downto 0) => din(33 downto 32),
DIC(1 downto 0) => din(35 downto 34),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(31 downto 30),
DOB(1 downto 0) => p_0_out(33 downto 32),
DOC(1 downto 0) => p_0_out(35 downto 34),
DOD(1 downto 0) => NLW_RAM_reg_0_31_30_35_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => I2(0)
);
RAM_reg_0_31_36_41: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => O2(4 downto 0),
ADDRB(4 downto 0) => O2(4 downto 0),
ADDRC(4 downto 0) => O2(4 downto 0),
ADDRD(4 downto 0) => O1(4 downto 0),
DIA(1 downto 0) => din(37 downto 36),
DIB(1 downto 0) => din(39 downto 38),
DIC(1 downto 0) => din(41 downto 40),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(37 downto 36),
DOB(1 downto 0) => p_0_out(39 downto 38),
DOC(1 downto 0) => p_0_out(41 downto 40),
DOD(1 downto 0) => NLW_RAM_reg_0_31_36_41_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => I2(0)
);
RAM_reg_0_31_42_47: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => O2(4 downto 0),
ADDRB(4 downto 0) => O2(4 downto 0),
ADDRC(4 downto 0) => O2(4 downto 0),
ADDRD(4 downto 0) => O1(4 downto 0),
DIA(1 downto 0) => din(43 downto 42),
DIB(1 downto 0) => din(45 downto 44),
DIC(1 downto 0) => din(47 downto 46),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(43 downto 42),
DOB(1 downto 0) => p_0_out(45 downto 44),
DOC(1 downto 0) => p_0_out(47 downto 46),
DOD(1 downto 0) => NLW_RAM_reg_0_31_42_47_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => I2(0)
);
RAM_reg_0_31_48_53: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => O2(4 downto 0),
ADDRB(4 downto 0) => O2(4 downto 0),
ADDRC(4 downto 0) => O2(4 downto 0),
ADDRD(4 downto 0) => O1(4 downto 0),
DIA(1 downto 0) => din(49 downto 48),
DIB(1 downto 0) => din(51 downto 50),
DIC(1 downto 0) => din(53 downto 52),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(49 downto 48),
DOB(1 downto 0) => p_0_out(51 downto 50),
DOC(1 downto 0) => p_0_out(53 downto 52),
DOD(1 downto 0) => NLW_RAM_reg_0_31_48_53_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => I2(0)
);
RAM_reg_0_31_54_59: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => O2(4 downto 0),
ADDRB(4 downto 0) => O2(4 downto 0),
ADDRC(4 downto 0) => O2(4 downto 0),
ADDRD(4 downto 0) => O1(4 downto 0),
DIA(1 downto 0) => din(55 downto 54),
DIB(1 downto 0) => din(57 downto 56),
DIC(1 downto 0) => din(59 downto 58),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(55 downto 54),
DOB(1 downto 0) => p_0_out(57 downto 56),
DOC(1 downto 0) => p_0_out(59 downto 58),
DOD(1 downto 0) => NLW_RAM_reg_0_31_54_59_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => I2(0)
);
RAM_reg_0_31_60_65: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => O2(4 downto 0),
ADDRB(4 downto 0) => O2(4 downto 0),
ADDRC(4 downto 0) => O2(4 downto 0),
ADDRD(4 downto 0) => O1(4 downto 0),
DIA(1 downto 0) => din(61 downto 60),
DIB(1 downto 0) => din(63 downto 62),
DIC(1 downto 0) => din(65 downto 64),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(61 downto 60),
DOB(1 downto 0) => p_0_out(63 downto 62),
DOC(1 downto 0) => p_0_out(65 downto 64),
DOD(1 downto 0) => NLW_RAM_reg_0_31_60_65_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => I2(0)
);
RAM_reg_0_31_66_71: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => O2(4 downto 0),
ADDRB(4 downto 0) => O2(4 downto 0),
ADDRC(4 downto 0) => O2(4 downto 0),
ADDRD(4 downto 0) => O1(4 downto 0),
DIA(1 downto 0) => din(67 downto 66),
DIB(1 downto 0) => din(69 downto 68),
DIC(1 downto 0) => din(71 downto 70),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(67 downto 66),
DOB(1 downto 0) => p_0_out(69 downto 68),
DOC(1 downto 0) => p_0_out(71 downto 70),
DOD(1 downto 0) => NLW_RAM_reg_0_31_66_71_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => I2(0)
);
RAM_reg_0_31_6_11: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => O2(4 downto 0),
ADDRB(4 downto 0) => O2(4 downto 0),
ADDRC(4 downto 0) => O2(4 downto 0),
ADDRD(4 downto 0) => O1(4 downto 0),
DIA(1 downto 0) => din(7 downto 6),
DIB(1 downto 0) => din(9 downto 8),
DIC(1 downto 0) => din(11 downto 10),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(7 downto 6),
DOB(1 downto 0) => p_0_out(9 downto 8),
DOC(1 downto 0) => p_0_out(11 downto 10),
DOD(1 downto 0) => NLW_RAM_reg_0_31_6_11_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => I2(0)
);
RAM_reg_0_31_72_77: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => O2(4 downto 0),
ADDRB(4 downto 0) => O2(4 downto 0),
ADDRC(4 downto 0) => O2(4 downto 0),
ADDRD(4 downto 0) => O1(4 downto 0),
DIA(1 downto 0) => din(73 downto 72),
DIB(1 downto 0) => din(75 downto 74),
DIC(1 downto 0) => din(77 downto 76),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(73 downto 72),
DOB(1 downto 0) => p_0_out(75 downto 74),
DOC(1 downto 0) => p_0_out(77 downto 76),
DOD(1 downto 0) => NLW_RAM_reg_0_31_72_77_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => I2(0)
);
RAM_reg_0_31_78_83: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => O2(4 downto 0),
ADDRB(4 downto 0) => O2(4 downto 0),
ADDRC(4 downto 0) => O2(4 downto 0),
ADDRD(4 downto 0) => O1(4 downto 0),
DIA(1 downto 0) => din(79 downto 78),
DIB(1 downto 0) => din(81 downto 80),
DIC(1 downto 0) => din(83 downto 82),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(79 downto 78),
DOB(1 downto 0) => p_0_out(81 downto 80),
DOC(1 downto 0) => p_0_out(83 downto 82),
DOD(1 downto 0) => NLW_RAM_reg_0_31_78_83_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => I2(0)
);
RAM_reg_0_31_84_89: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => O2(4 downto 0),
ADDRB(4 downto 0) => O2(4 downto 0),
ADDRC(4 downto 0) => O2(4 downto 0),
ADDRD(4 downto 0) => O1(4 downto 0),
DIA(1 downto 0) => din(85 downto 84),
DIB(1 downto 0) => din(87 downto 86),
DIC(1 downto 0) => din(89 downto 88),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(85 downto 84),
DOB(1 downto 0) => p_0_out(87 downto 86),
DOC(1 downto 0) => p_0_out(89 downto 88),
DOD(1 downto 0) => NLW_RAM_reg_0_31_84_89_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => I2(0)
);
RAM_reg_0_31_90_95: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => O2(4 downto 0),
ADDRB(4 downto 0) => O2(4 downto 0),
ADDRC(4 downto 0) => O2(4 downto 0),
ADDRD(4 downto 0) => O1(4 downto 0),
DIA(1 downto 0) => din(91 downto 90),
DIB(1 downto 0) => din(93 downto 92),
DIC(1 downto 0) => din(95 downto 94),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(91 downto 90),
DOB(1 downto 0) => p_0_out(93 downto 92),
DOC(1 downto 0) => p_0_out(95 downto 94),
DOD(1 downto 0) => NLW_RAM_reg_0_31_90_95_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => I2(0)
);
RAM_reg_0_31_96_101: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => O2(4 downto 0),
ADDRB(4 downto 0) => O2(4 downto 0),
ADDRC(4 downto 0) => O2(4 downto 0),
ADDRD(4 downto 0) => O1(4 downto 0),
DIA(1 downto 0) => din(97 downto 96),
DIB(1 downto 0) => din(99 downto 98),
DIC(1 downto 0) => din(101 downto 100),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(97 downto 96),
DOB(1 downto 0) => p_0_out(99 downto 98),
DOC(1 downto 0) => p_0_out(101 downto 100),
DOD(1 downto 0) => NLW_RAM_reg_0_31_96_101_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => I2(0)
);
\gpr1.dout_i_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(0),
Q => Q(0)
);
\gpr1.dout_i_reg[100]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(100),
Q => Q(100)
);
\gpr1.dout_i_reg[101]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(101),
Q => Q(101)
);
\gpr1.dout_i_reg[102]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(102),
Q => Q(102)
);
\gpr1.dout_i_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(10),
Q => Q(10)
);
\gpr1.dout_i_reg[11]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(11),
Q => Q(11)
);
\gpr1.dout_i_reg[12]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(12),
Q => Q(12)
);
\gpr1.dout_i_reg[13]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(13),
Q => Q(13)
);
\gpr1.dout_i_reg[14]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(14),
Q => Q(14)
);
\gpr1.dout_i_reg[15]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(15),
Q => Q(15)
);
\gpr1.dout_i_reg[16]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(16),
Q => Q(16)
);
\gpr1.dout_i_reg[17]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(17),
Q => Q(17)
);
\gpr1.dout_i_reg[18]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(18),
Q => Q(18)
);
\gpr1.dout_i_reg[19]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(19),
Q => Q(19)
);
\gpr1.dout_i_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(1),
Q => Q(1)
);
\gpr1.dout_i_reg[20]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(20),
Q => Q(20)
);
\gpr1.dout_i_reg[21]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(21),
Q => Q(21)
);
\gpr1.dout_i_reg[22]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(22),
Q => Q(22)
);
\gpr1.dout_i_reg[23]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(23),
Q => Q(23)
);
\gpr1.dout_i_reg[24]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(24),
Q => Q(24)
);
\gpr1.dout_i_reg[25]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(25),
Q => Q(25)
);
\gpr1.dout_i_reg[26]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(26),
Q => Q(26)
);
\gpr1.dout_i_reg[27]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(27),
Q => Q(27)
);
\gpr1.dout_i_reg[28]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(28),
Q => Q(28)
);
\gpr1.dout_i_reg[29]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(29),
Q => Q(29)
);
\gpr1.dout_i_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(2),
Q => Q(2)
);
\gpr1.dout_i_reg[30]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(30),
Q => Q(30)
);
\gpr1.dout_i_reg[31]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(31),
Q => Q(31)
);
\gpr1.dout_i_reg[32]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(32),
Q => Q(32)
);
\gpr1.dout_i_reg[33]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(33),
Q => Q(33)
);
\gpr1.dout_i_reg[34]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(34),
Q => Q(34)
);
\gpr1.dout_i_reg[35]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(35),
Q => Q(35)
);
\gpr1.dout_i_reg[36]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(36),
Q => Q(36)
);
\gpr1.dout_i_reg[37]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(37),
Q => Q(37)
);
\gpr1.dout_i_reg[38]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(38),
Q => Q(38)
);
\gpr1.dout_i_reg[39]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(39),
Q => Q(39)
);
\gpr1.dout_i_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(3),
Q => Q(3)
);
\gpr1.dout_i_reg[40]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(40),
Q => Q(40)
);
\gpr1.dout_i_reg[41]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(41),
Q => Q(41)
);
\gpr1.dout_i_reg[42]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(42),
Q => Q(42)
);
\gpr1.dout_i_reg[43]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(43),
Q => Q(43)
);
\gpr1.dout_i_reg[44]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(44),
Q => Q(44)
);
\gpr1.dout_i_reg[45]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(45),
Q => Q(45)
);
\gpr1.dout_i_reg[46]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(46),
Q => Q(46)
);
\gpr1.dout_i_reg[47]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(47),
Q => Q(47)
);
\gpr1.dout_i_reg[48]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(48),
Q => Q(48)
);
\gpr1.dout_i_reg[49]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(49),
Q => Q(49)
);
\gpr1.dout_i_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(4),
Q => Q(4)
);
\gpr1.dout_i_reg[50]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(50),
Q => Q(50)
);
\gpr1.dout_i_reg[51]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(51),
Q => Q(51)
);
\gpr1.dout_i_reg[52]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(52),
Q => Q(52)
);
\gpr1.dout_i_reg[53]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(53),
Q => Q(53)
);
\gpr1.dout_i_reg[54]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(54),
Q => Q(54)
);
\gpr1.dout_i_reg[55]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(55),
Q => Q(55)
);
\gpr1.dout_i_reg[56]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(56),
Q => Q(56)
);
\gpr1.dout_i_reg[57]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(57),
Q => Q(57)
);
\gpr1.dout_i_reg[58]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(58),
Q => Q(58)
);
\gpr1.dout_i_reg[59]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(59),
Q => Q(59)
);
\gpr1.dout_i_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(5),
Q => Q(5)
);
\gpr1.dout_i_reg[60]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(60),
Q => Q(60)
);
\gpr1.dout_i_reg[61]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(61),
Q => Q(61)
);
\gpr1.dout_i_reg[62]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(62),
Q => Q(62)
);
\gpr1.dout_i_reg[63]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(63),
Q => Q(63)
);
\gpr1.dout_i_reg[64]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(64),
Q => Q(64)
);
\gpr1.dout_i_reg[65]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(65),
Q => Q(65)
);
\gpr1.dout_i_reg[66]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(66),
Q => Q(66)
);
\gpr1.dout_i_reg[67]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(67),
Q => Q(67)
);
\gpr1.dout_i_reg[68]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(68),
Q => Q(68)
);
\gpr1.dout_i_reg[69]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(69),
Q => Q(69)
);
\gpr1.dout_i_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(6),
Q => Q(6)
);
\gpr1.dout_i_reg[70]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(70),
Q => Q(70)
);
\gpr1.dout_i_reg[71]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(71),
Q => Q(71)
);
\gpr1.dout_i_reg[72]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(72),
Q => Q(72)
);
\gpr1.dout_i_reg[73]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(73),
Q => Q(73)
);
\gpr1.dout_i_reg[74]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(74),
Q => Q(74)
);
\gpr1.dout_i_reg[75]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(75),
Q => Q(75)
);
\gpr1.dout_i_reg[76]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(76),
Q => Q(76)
);
\gpr1.dout_i_reg[77]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(77),
Q => Q(77)
);
\gpr1.dout_i_reg[78]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(78),
Q => Q(78)
);
\gpr1.dout_i_reg[79]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(79),
Q => Q(79)
);
\gpr1.dout_i_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(7),
Q => Q(7)
);
\gpr1.dout_i_reg[80]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(80),
Q => Q(80)
);
\gpr1.dout_i_reg[81]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(81),
Q => Q(81)
);
\gpr1.dout_i_reg[82]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(82),
Q => Q(82)
);
\gpr1.dout_i_reg[83]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(83),
Q => Q(83)
);
\gpr1.dout_i_reg[84]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(84),
Q => Q(84)
);
\gpr1.dout_i_reg[85]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(85),
Q => Q(85)
);
\gpr1.dout_i_reg[86]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(86),
Q => Q(86)
);
\gpr1.dout_i_reg[87]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(87),
Q => Q(87)
);
\gpr1.dout_i_reg[88]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(88),
Q => Q(88)
);
\gpr1.dout_i_reg[89]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(89),
Q => Q(89)
);
\gpr1.dout_i_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(8),
Q => Q(8)
);
\gpr1.dout_i_reg[90]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(90),
Q => Q(90)
);
\gpr1.dout_i_reg[91]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(91),
Q => Q(91)
);
\gpr1.dout_i_reg[92]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(92),
Q => Q(92)
);
\gpr1.dout_i_reg[93]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(93),
Q => Q(93)
);
\gpr1.dout_i_reg[94]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(94),
Q => Q(94)
);
\gpr1.dout_i_reg[95]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(95),
Q => Q(95)
);
\gpr1.dout_i_reg[96]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(96),
Q => Q(96)
);
\gpr1.dout_i_reg[97]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(97),
Q => Q(97)
);
\gpr1.dout_i_reg[98]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(98),
Q => Q(98)
);
\gpr1.dout_i_reg[99]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(99),
Q => Q(99)
);
\gpr1.dout_i_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(9),
Q => Q(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x32_rd_bin_cntr is
port (
Q : out STD_LOGIC_VECTOR ( 0 to 0 );
O1 : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
O2 : out STD_LOGIC_VECTOR ( 4 downto 0 );
I1 : in STD_LOGIC_VECTOR ( 3 downto 0 );
I2 : in STD_LOGIC;
I3 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC;
I4 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x32_rd_bin_cntr : entity is "rd_bin_cntr";
end fifo_async_103x32_rd_bin_cntr;
architecture STRUCTURE of fifo_async_103x32_rd_bin_cntr is
signal \^o2\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal n_0_ram_empty_fb_i_i_2 : STD_LOGIC;
signal n_0_ram_empty_fb_i_i_4 : STD_LOGIC;
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 4 downto 1 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[1]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \gc0.count[2]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \gc0.count[4]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of ram_empty_fb_i_i_4 : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \rd_pntr_gc[1]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \rd_pntr_gc[2]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \rd_pntr_gc[3]_i_1\ : label is "soft_lutpair10";
begin
O2(4 downto 0) <= \^o2\(4 downto 0);
Q(0) <= \^q\(0);
\gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \plusOp__0\(0)
);
\gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => rd_pntr_plus1(1),
O => \plusOp__0\(1)
);
\gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => rd_pntr_plus1(1),
I1 => \^q\(0),
I2 => rd_pntr_plus1(2),
O => \plusOp__0\(2)
);
\gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => rd_pntr_plus1(2),
I1 => \^q\(0),
I2 => rd_pntr_plus1(1),
I3 => rd_pntr_plus1(3),
O => \plusOp__0\(3)
);
\gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => rd_pntr_plus1(3),
I1 => rd_pntr_plus1(1),
I2 => \^q\(0),
I3 => rd_pntr_plus1(2),
I4 => rd_pntr_plus1(4),
O => \plusOp__0\(4)
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I4(0),
D => \^q\(0),
Q => \^o2\(0)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I4(0),
D => rd_pntr_plus1(1),
Q => \^o2\(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I4(0),
D => rd_pntr_plus1(2),
Q => \^o2\(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I4(0),
D => rd_pntr_plus1(3),
Q => \^o2\(3)
);
\gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I4(0),
D => rd_pntr_plus1(4),
Q => \^o2\(4)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => E(0),
D => \plusOp__0\(0),
PRE => I4(0),
Q => \^q\(0)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I4(0),
D => \plusOp__0\(1),
Q => rd_pntr_plus1(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I4(0),
D => \plusOp__0\(2),
Q => rd_pntr_plus1(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I4(0),
D => \plusOp__0\(3),
Q => rd_pntr_plus1(3)
);
\gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I4(0),
D => \plusOp__0\(4),
Q => rd_pntr_plus1(4)
);
ram_empty_fb_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF800880088008"
)
port map (
I0 => n_0_ram_empty_fb_i_i_2,
I1 => I2,
I2 => I1(3),
I3 => rd_pntr_plus1(4),
I4 => n_0_ram_empty_fb_i_i_4,
I5 => I3,
O => O1
);
ram_empty_fb_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => rd_pntr_plus1(2),
I1 => I1(1),
I2 => I1(0),
I3 => rd_pntr_plus1(1),
I4 => I1(2),
I5 => rd_pntr_plus1(3),
O => n_0_ram_empty_fb_i_i_2
);
ram_empty_fb_i_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^o2\(3),
I1 => I1(2),
I2 => \^o2\(4),
I3 => I1(3),
O => n_0_ram_empty_fb_i_i_4
);
\rd_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^o2\(0),
I1 => \^o2\(1),
O => D(0)
);
\rd_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^o2\(1),
I1 => \^o2\(2),
O => D(1)
);
\rd_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^o2\(2),
I1 => \^o2\(3),
O => D(2)
);
\rd_pntr_gc[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^o2\(3),
I1 => \^o2\(4),
O => D(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x32_rd_fwft is
port (
empty : out STD_LOGIC;
O1 : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
O2 : out STD_LOGIC_VECTOR ( 0 to 0 );
O3 : out STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
I1 : in STD_LOGIC_VECTOR ( 0 to 0 );
I2 : in STD_LOGIC_VECTOR ( 0 to 0 );
p_18_out : in STD_LOGIC;
rd_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x32_rd_fwft : entity is "rd_fwft";
end fifo_async_103x32_rd_fwft;
architecture STRUCTURE of fifo_async_103x32_rd_fwft is
signal curr_fwft_state : STD_LOGIC_VECTOR ( 0 to 0 );
signal empty_fwft_fb : STD_LOGIC;
signal empty_fwft_i0 : STD_LOGIC;
signal \n_0_gpregsm1.curr_fwft_state_reg[1]\ : STD_LOGIC;
signal next_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of empty_fwft_fb_reg : label is "no";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of empty_fwft_i_i_1 : label is "soft_lutpair8";
attribute equivalent_register_removal of empty_fwft_i_reg : label is "no";
attribute SOFT_HLUTNM of \gc0.count_d1[4]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \goreg_dm.dout_i[102]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gpr1.dout_i[102]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gpregsm1.curr_fwft_state[0]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \gpregsm1.curr_fwft_state[1]_i_1\ : label is "soft_lutpair6";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[0]\ : label is "no";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[1]\ : label is "no";
begin
empty_fwft_fb_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => empty_fwft_i0,
PRE => Q(0),
Q => empty_fwft_fb
);
empty_fwft_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F540"
)
port map (
I0 => \n_0_gpregsm1.curr_fwft_state_reg[1]\,
I1 => rd_en,
I2 => curr_fwft_state(0),
I3 => empty_fwft_fb,
O => empty_fwft_i0
);
empty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => empty_fwft_i0,
PRE => Q(0),
Q => empty
);
\gc0.count_d1[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00DF"
)
port map (
I0 => \n_0_gpregsm1.curr_fwft_state_reg[1]\,
I1 => rd_en,
I2 => curr_fwft_state(0),
I3 => p_18_out,
O => O2(0)
);
\goreg_dm.dout_i[102]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D0"
)
port map (
I0 => curr_fwft_state(0),
I1 => rd_en,
I2 => \n_0_gpregsm1.curr_fwft_state_reg[1]\,
O => E(0)
);
\gpr1.dout_i[102]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00DF"
)
port map (
I0 => \n_0_gpregsm1.curr_fwft_state_reg[1]\,
I1 => rd_en,
I2 => curr_fwft_state(0),
I3 => p_18_out,
O => O3(0)
);
\gpregsm1.curr_fwft_state[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AE"
)
port map (
I0 => \n_0_gpregsm1.curr_fwft_state_reg[1]\,
I1 => curr_fwft_state(0),
I2 => rd_en,
O => next_fwft_state(0)
);
\gpregsm1.curr_fwft_state[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20FF"
)
port map (
I0 => \n_0_gpregsm1.curr_fwft_state_reg[1]\,
I1 => rd_en,
I2 => curr_fwft_state(0),
I3 => p_18_out,
O => next_fwft_state(1)
);
\gpregsm1.curr_fwft_state_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => Q(0),
D => next_fwft_state(0),
Q => curr_fwft_state(0)
);
\gpregsm1.curr_fwft_state_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => Q(0),
D => next_fwft_state(1),
Q => \n_0_gpregsm1.curr_fwft_state_reg[1]\
);
ram_empty_fb_i_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0909000909090909"
)
port map (
I0 => I1(0),
I1 => I2(0),
I2 => p_18_out,
I3 => curr_fwft_state(0),
I4 => rd_en,
I5 => \n_0_gpregsm1.curr_fwft_state_reg[1]\,
O => O1
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x32_rd_status_flags_as is
port (
p_18_out : out STD_LOGIC;
I1 : in STD_LOGIC;
rd_clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x32_rd_status_flags_as : entity is "rd_status_flags_as";
end fifo_async_103x32_rd_status_flags_as;
architecture STRUCTURE of fifo_async_103x32_rd_status_flags_as is
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
begin
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => I1,
PRE => Q(0),
Q => p_18_out
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x32_reset_blk_ramfifo is
port (
rst_d2 : out STD_LOGIC;
rst_full_gen_i : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
O1 : out STD_LOGIC_VECTOR ( 1 downto 0 );
wr_clk : in STD_LOGIC;
rst : in STD_LOGIC;
rd_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x32_reset_blk_ramfifo : entity is "reset_blk_ramfifo";
end fifo_async_103x32_reset_blk_ramfifo;
architecture STRUCTURE of fifo_async_103x32_reset_blk_ramfifo is
signal \n_0_ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\ : STD_LOGIC;
signal \n_0_ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1\ : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_asreg_d1 : STD_LOGIC;
signal rd_rst_asreg_d2 : STD_LOGIC;
signal rst_d1 : STD_LOGIC;
signal \^rst_d2\ : STD_LOGIC;
signal rst_d3 : STD_LOGIC;
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_asreg_d1 : STD_LOGIC;
signal wr_rst_asreg_d2 : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute msgon : string;
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg\ : label is std.standard.true;
attribute msgon of \ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg\ : label is "true";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.rd_rst_asreg_d2_reg\ : label is std.standard.true;
attribute msgon of \ngwrdrst.grst.g7serrst.rd_rst_asreg_d2_reg\ : label is "true";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\ : label is std.standard.true;
attribute msgon of \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\ : label is "true";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg\ : label is std.standard.true;
attribute msgon of \ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg\ : label is "true";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.wr_rst_asreg_d2_reg\ : label is std.standard.true;
attribute msgon of \ngwrdrst.grst.g7serrst.wr_rst_asreg_d2_reg\ : label is "true";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\ : label is std.standard.true;
attribute msgon of \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\ : label is "true";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
begin
rst_d2 <= \^rst_d2\;
\grstd1.grst_full.grst_f.RST_FULL_GEN_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => rst,
D => rst_d3,
Q => rst_full_gen_i
);
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => rst_d1,
PRE => rst,
Q => \^rst_d2\
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => \^rst_d2\,
PRE => rst,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => rd_rst_asreg,
Q => rd_rst_asreg_d1,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_d2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => rd_rst_asreg_d1,
Q => rd_rst_asreg_d2,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
port map (
C => rd_clk,
CE => rd_rst_asreg_d1,
D => '0',
PRE => rst,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_rst_asreg,
I1 => rd_rst_asreg_d2,
O => \n_0_ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => \n_0_ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\,
Q => Q(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => \n_0_ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\,
Q => Q(1)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => \n_0_ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\,
Q => Q(2)
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => wr_rst_asreg,
Q => wr_rst_asreg_d1,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_d2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => wr_rst_asreg_d1,
Q => wr_rst_asreg_d2,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
port map (
C => wr_clk,
CE => wr_rst_asreg_d1,
D => '0',
PRE => rst,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_rst_asreg,
I1 => wr_rst_asreg_d2,
O => \n_0_ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1\
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => \n_0_ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1\,
Q => O1(0)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => \n_0_ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1\,
Q => O1(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x32_synchronizer_ff is
port (
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
I1 : in STD_LOGIC_VECTOR ( 4 downto 0 );
rd_clk : in STD_LOGIC;
I5 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x32_synchronizer_ff : entity is "synchronizer_ff";
end fifo_async_103x32_synchronizer_ff;
architecture STRUCTURE of fifo_async_103x32_synchronizer_ff is
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \Q_reg_reg[0]\ : label is std.standard.true;
attribute msgon : string;
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[1]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[2]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[3]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[3]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[4]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[4]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I5(0),
D => I1(0),
Q => Q(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I5(0),
D => I1(1),
Q => Q(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I5(0),
D => I1(2),
Q => Q(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I5(0),
D => I1(3),
Q => Q(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I5(0),
D => I1(4),
Q => Q(4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x32_synchronizer_ff_0 is
port (
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
I1 : in STD_LOGIC_VECTOR ( 4 downto 0 );
wr_clk : in STD_LOGIC;
I4 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x32_synchronizer_ff_0 : entity is "synchronizer_ff";
end fifo_async_103x32_synchronizer_ff_0;
architecture STRUCTURE of fifo_async_103x32_synchronizer_ff_0 is
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \Q_reg_reg[0]\ : label is std.standard.true;
attribute msgon : string;
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[1]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[2]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[3]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[3]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[4]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[4]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I4(0),
D => I1(0),
Q => Q(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I4(0),
D => I1(1),
Q => Q(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I4(0),
D => I1(2),
Q => Q(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I4(0),
D => I1(3),
Q => Q(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I4(0),
D => I1(4),
Q => Q(4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x32_synchronizer_ff_1 is
port (
p_0_in : out STD_LOGIC_VECTOR ( 4 downto 0 );
D : in STD_LOGIC_VECTOR ( 4 downto 0 );
rd_clk : in STD_LOGIC;
I5 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x32_synchronizer_ff_1 : entity is "synchronizer_ff";
end fifo_async_103x32_synchronizer_ff_1;
architecture STRUCTURE of fifo_async_103x32_synchronizer_ff_1 is
signal \n_0_Q_reg_reg[0]\ : STD_LOGIC;
signal \n_0_Q_reg_reg[1]\ : STD_LOGIC;
signal \n_0_Q_reg_reg[2]\ : STD_LOGIC;
signal \n_0_Q_reg_reg[3]\ : STD_LOGIC;
signal \^p_0_in\ : STD_LOGIC_VECTOR ( 4 downto 0 );
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \Q_reg_reg[0]\ : label is std.standard.true;
attribute msgon : string;
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[1]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[2]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[3]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[3]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[4]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[4]\ : label is "true";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \wr_pntr_bin[0]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \wr_pntr_bin[1]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \wr_pntr_bin[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \wr_pntr_bin[3]_i_1\ : label is "soft_lutpair1";
begin
p_0_in(4 downto 0) <= \^p_0_in\(4 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I5(0),
D => D(0),
Q => \n_0_Q_reg_reg[0]\
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I5(0),
D => D(1),
Q => \n_0_Q_reg_reg[1]\
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I5(0),
D => D(2),
Q => \n_0_Q_reg_reg[2]\
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I5(0),
D => D(3),
Q => \n_0_Q_reg_reg[3]\
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I5(0),
D => D(4),
Q => \^p_0_in\(4)
);
\wr_pntr_bin[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => \n_0_Q_reg_reg[2]\,
I1 => \n_0_Q_reg_reg[0]\,
I2 => \n_0_Q_reg_reg[1]\,
I3 => \^p_0_in\(4),
I4 => \n_0_Q_reg_reg[3]\,
O => \^p_0_in\(0)
);
\wr_pntr_bin[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \n_0_Q_reg_reg[2]\,
I1 => \n_0_Q_reg_reg[1]\,
I2 => \^p_0_in\(4),
I3 => \n_0_Q_reg_reg[3]\,
O => \^p_0_in\(1)
);
\wr_pntr_bin[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \n_0_Q_reg_reg[3]\,
I1 => \n_0_Q_reg_reg[2]\,
I2 => \^p_0_in\(4),
O => \^p_0_in\(2)
);
\wr_pntr_bin[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \n_0_Q_reg_reg[3]\,
I1 => \^p_0_in\(4),
O => \^p_0_in\(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x32_synchronizer_ff_2 is
port (
Q : out STD_LOGIC_VECTOR ( 0 to 0 );
O1 : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : in STD_LOGIC_VECTOR ( 4 downto 0 );
wr_clk : in STD_LOGIC;
I4 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x32_synchronizer_ff_2 : entity is "synchronizer_ff";
end fifo_async_103x32_synchronizer_ff_2;
architecture STRUCTURE of fifo_async_103x32_synchronizer_ff_2 is
signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \n_0_Q_reg_reg[0]\ : STD_LOGIC;
signal \n_0_Q_reg_reg[1]\ : STD_LOGIC;
signal \n_0_Q_reg_reg[2]\ : STD_LOGIC;
signal \n_0_Q_reg_reg[3]\ : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \Q_reg_reg[0]\ : label is std.standard.true;
attribute msgon : string;
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[1]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[2]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[3]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[3]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[4]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[4]\ : label is "true";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \rd_pntr_bin[0]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \rd_pntr_bin[1]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \rd_pntr_bin[2]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \rd_pntr_bin[3]_i_1\ : label is "soft_lutpair3";
begin
Q(0) <= \^q\(0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I4(0),
D => D(0),
Q => \n_0_Q_reg_reg[0]\
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I4(0),
D => D(1),
Q => \n_0_Q_reg_reg[1]\
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I4(0),
D => D(2),
Q => \n_0_Q_reg_reg[2]\
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I4(0),
D => D(3),
Q => \n_0_Q_reg_reg[3]\
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I4(0),
D => D(4),
Q => \^q\(0)
);
\rd_pntr_bin[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => \n_0_Q_reg_reg[2]\,
I1 => \n_0_Q_reg_reg[0]\,
I2 => \n_0_Q_reg_reg[1]\,
I3 => \^q\(0),
I4 => \n_0_Q_reg_reg[3]\,
O => O1(0)
);
\rd_pntr_bin[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \n_0_Q_reg_reg[2]\,
I1 => \n_0_Q_reg_reg[1]\,
I2 => \^q\(0),
I3 => \n_0_Q_reg_reg[3]\,
O => O1(1)
);
\rd_pntr_bin[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \n_0_Q_reg_reg[3]\,
I1 => \n_0_Q_reg_reg[2]\,
I2 => \^q\(0),
O => O1(2)
);
\rd_pntr_bin[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \n_0_Q_reg_reg[3]\,
I1 => \^q\(0),
O => O1(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x32_wr_bin_cntr is
port (
O1 : out STD_LOGIC;
O2 : out STD_LOGIC_VECTOR ( 1 downto 0 );
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
S : out STD_LOGIC_VECTOR ( 2 downto 0 );
O4 : out STD_LOGIC_VECTOR ( 3 downto 0 );
O5 : out STD_LOGIC_VECTOR ( 4 downto 0 );
rst_full_gen_i : in STD_LOGIC;
I1 : in STD_LOGIC;
I2 : in STD_LOGIC;
O3 : in STD_LOGIC_VECTOR ( 4 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_clk : in STD_LOGIC;
I3 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x32_wr_bin_cntr : entity is "wr_bin_cntr";
end fifo_async_103x32_wr_bin_cntr;
architecture STRUCTURE of fifo_async_103x32_wr_bin_cntr is
signal \^o4\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal n_0_ram_full_i_i_2 : STD_LOGIC;
signal n_0_ram_full_i_i_5 : STD_LOGIC;
signal p_8_out : STD_LOGIC_VECTOR ( 4 to 4 );
signal \plusOp__1\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gic0.gc0.count[0]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \gic0.gc0.count[2]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \gic0.gc0.count[3]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \gic0.gc0.count[4]_i_1\ : label is "soft_lutpair13";
begin
O4(3 downto 0) <= \^o4\(3 downto 0);
Q(3 downto 0) <= \^q\(3 downto 0);
\gdiff.diff_pntr_pad[3]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(2),
I1 => O3(2),
O => S(2)
);
\gdiff.diff_pntr_pad[3]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(1),
I1 => O3(1),
O => S(1)
);
\gdiff.diff_pntr_pad[3]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(0),
I1 => O3(0),
O => S(0)
);
\gdiff.diff_pntr_pad[5]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_8_out(4),
I1 => O3(4),
O => O2(1)
);
\gdiff.diff_pntr_pad[5]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(3),
I1 => O3(3),
O => O2(0)
);
\gic0.gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^o4\(0),
O => \plusOp__1\(0)
);
\gic0.gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^o4\(0),
I1 => \^o4\(1),
O => \plusOp__1\(1)
);
\gic0.gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^o4\(0),
I1 => \^o4\(1),
I2 => \^o4\(2),
O => \plusOp__1\(2)
);
\gic0.gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => wr_pntr_plus2(3),
I1 => \^o4\(0),
I2 => \^o4\(1),
I3 => \^o4\(2),
O => \plusOp__1\(3)
);
\gic0.gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \^o4\(3),
I1 => \^o4\(2),
I2 => \^o4\(1),
I3 => \^o4\(0),
I4 => wr_pntr_plus2(3),
O => \plusOp__1\(4)
);
\gic0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => E(0),
D => \^o4\(0),
PRE => I3(0),
Q => \^q\(0)
);
\gic0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => I3(0),
D => \^o4\(1),
Q => \^q\(1)
);
\gic0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => I3(0),
D => \^o4\(2),
Q => \^q\(2)
);
\gic0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => I3(0),
D => wr_pntr_plus2(3),
Q => \^q\(3)
);
\gic0.gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => I3(0),
D => \^o4\(3),
Q => p_8_out(4)
);
\gic0.gc0.count_d2_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => I3(0),
D => \^q\(0),
Q => O5(0)
);
\gic0.gc0.count_d2_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => I3(0),
D => \^q\(1),
Q => O5(1)
);
\gic0.gc0.count_d2_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => I3(0),
D => \^q\(2),
Q => O5(2)
);
\gic0.gc0.count_d2_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => I3(0),
D => \^q\(3),
Q => O5(3)
);
\gic0.gc0.count_d2_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => I3(0),
D => p_8_out(4),
Q => O5(4)
);
\gic0.gc0.count_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => I3(0),
D => \plusOp__1\(0),
Q => \^o4\(0)
);
\gic0.gc0.count_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => E(0),
D => \plusOp__1\(1),
PRE => I3(0),
Q => \^o4\(1)
);
\gic0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => I3(0),
D => \plusOp__1\(2),
Q => \^o4\(2)
);
\gic0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => I3(0),
D => \plusOp__1\(3),
Q => wr_pntr_plus2(3)
);
\gic0.gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => I3(0),
D => \plusOp__1\(4),
Q => \^o4\(3)
);
ram_full_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"4445444444444445"
)
port map (
I0 => rst_full_gen_i,
I1 => n_0_ram_full_i_i_2,
I2 => I1,
I3 => I2,
I4 => wr_pntr_plus2(3),
I5 => O3(3),
O => O1
);
ram_full_i_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"00009009"
)
port map (
I0 => \^q\(2),
I1 => O3(2),
I2 => \^q\(3),
I3 => O3(3),
I4 => n_0_ram_full_i_i_5,
O => n_0_ram_full_i_i_2
);
ram_full_i_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"6FF6FFFFFFFF6FF6"
)
port map (
I0 => \^q\(1),
I1 => O3(1),
I2 => \^q\(0),
I3 => O3(0),
I4 => O3(4),
I5 => p_8_out(4),
O => n_0_ram_full_i_i_5
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x32_wr_pf_as is
port (
prog_full : out STD_LOGIC;
wr_clk : in STD_LOGIC;
rst_d2 : in STD_LOGIC;
rst_full_gen_i : in STD_LOGIC;
p_1_out : in STD_LOGIC;
I2 : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_pntr_plus1_pad : in STD_LOGIC_VECTOR ( 4 downto 0 );
S : in STD_LOGIC_VECTOR ( 2 downto 0 );
I1 : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x32_wr_pf_as : entity is "wr_pf_as";
end fifo_async_103x32_wr_pf_as;
architecture STRUCTURE of fifo_async_103x32_wr_pf_as is
signal diff_pntr : STD_LOGIC_VECTOR ( 4 downto 1 );
signal \n_0_gdiff.diff_pntr_pad_reg[3]_i_1\ : STD_LOGIC;
signal \n_0_gpf1.prog_full_i_i_1\ : STD_LOGIC;
signal \n_0_gpf1.prog_full_i_i_2\ : STD_LOGIC;
signal \n_1_gdiff.diff_pntr_pad_reg[3]_i_1\ : STD_LOGIC;
signal \n_2_gdiff.diff_pntr_pad_reg[3]_i_1\ : STD_LOGIC;
signal \n_3_gdiff.diff_pntr_pad_reg[3]_i_1\ : STD_LOGIC;
signal \n_3_gdiff.diff_pntr_pad_reg[5]_i_1\ : STD_LOGIC;
signal plusOp : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \^prog_full\ : STD_LOGIC;
signal \NLW_gdiff.diff_pntr_pad_reg[5]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gdiff.diff_pntr_pad_reg[5]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
begin
prog_full <= \^prog_full\;
\gdiff.diff_pntr_pad_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I2(0),
D => plusOp(2),
Q => diff_pntr(1)
);
\gdiff.diff_pntr_pad_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I2(0),
D => plusOp(3),
Q => diff_pntr(2)
);
\gdiff.diff_pntr_pad_reg[3]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \n_0_gdiff.diff_pntr_pad_reg[3]_i_1\,
CO(2) => \n_1_gdiff.diff_pntr_pad_reg[3]_i_1\,
CO(1) => \n_2_gdiff.diff_pntr_pad_reg[3]_i_1\,
CO(0) => \n_3_gdiff.diff_pntr_pad_reg[3]_i_1\,
CYINIT => '0',
DI(3 downto 0) => wr_pntr_plus1_pad(3 downto 0),
O(3 downto 0) => plusOp(3 downto 0),
S(3 downto 1) => S(2 downto 0),
S(0) => '0'
);
\gdiff.diff_pntr_pad_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I2(0),
D => plusOp(4),
Q => diff_pntr(3)
);
\gdiff.diff_pntr_pad_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I2(0),
D => plusOp(5),
Q => diff_pntr(4)
);
\gdiff.diff_pntr_pad_reg[5]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \n_0_gdiff.diff_pntr_pad_reg[3]_i_1\,
CO(3 downto 1) => \NLW_gdiff.diff_pntr_pad_reg[5]_i_1_CO_UNCONNECTED\(3 downto 1),
CO(0) => \n_3_gdiff.diff_pntr_pad_reg[5]_i_1\,
CYINIT => '0',
DI(3) => '0',
DI(2) => '0',
DI(1) => '0',
DI(0) => wr_pntr_plus1_pad(4),
O(3 downto 2) => \NLW_gdiff.diff_pntr_pad_reg[5]_i_1_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => plusOp(5 downto 4),
S(3) => '0',
S(2) => '0',
S(1 downto 0) => I1(1 downto 0)
);
\gpf1.prog_full_i_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => \n_0_gpf1.prog_full_i_i_2\,
I1 => rst_full_gen_i,
I2 => p_1_out,
I3 => \^prog_full\,
O => \n_0_gpf1.prog_full_i_i_1\
);
\gpf1.prog_full_i_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"54444444"
)
port map (
I0 => rst_full_gen_i,
I1 => diff_pntr(4),
I2 => diff_pntr(3),
I3 => diff_pntr(1),
I4 => diff_pntr(2),
O => \n_0_gpf1.prog_full_i_i_2\
);
\gpf1.prog_full_i_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => \n_0_gpf1.prog_full_i_i_1\,
PRE => rst_d2,
Q => \^prog_full\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x32_wr_status_flags_as is
port (
full : out STD_LOGIC;
p_1_out : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
O1 : out STD_LOGIC;
wr_pntr_plus1_pad : out STD_LOGIC_VECTOR ( 0 to 0 );
I1 : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rst_d2 : in STD_LOGIC;
wr_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x32_wr_status_flags_as : entity is "wr_status_flags_as";
end fifo_async_103x32_wr_status_flags_as;
architecture STRUCTURE of fifo_async_103x32_wr_status_flags_as is
signal \^p_1_out\ : STD_LOGIC;
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
p_1_out <= \^p_1_out\;
\gdiff.diff_pntr_pad[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => \^p_1_out\,
O => wr_pntr_plus1_pad(0)
);
\gic0.gc0.count_d1[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => \^p_1_out\,
O => E(0)
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => I1,
PRE => rst_d2,
Q => \^p_1_out\
);
ram_full_i_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^p_1_out\,
I1 => wr_en,
O => O1
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => I1,
PRE => rst_d2,
Q => full
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x32_clk_x_pntrs is
port (
O1 : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
O2 : out STD_LOGIC;
O3 : out STD_LOGIC_VECTOR ( 4 downto 0 );
I1 : in STD_LOGIC_VECTOR ( 3 downto 0 );
I2 : in STD_LOGIC_VECTOR ( 3 downto 0 );
I3 : in STD_LOGIC_VECTOR ( 4 downto 0 );
wr_clk : in STD_LOGIC;
I4 : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC;
I5 : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x32_clk_x_pntrs : entity is "clk_x_pntrs";
end fifo_async_103x32_clk_x_pntrs;
architecture STRUCTURE of fifo_async_103x32_clk_x_pntrs is
signal \^o3\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \n_0_gsync_stage[1].rd_stg_inst\ : STD_LOGIC;
signal \n_0_gsync_stage[1].wr_stg_inst\ : STD_LOGIC;
signal \n_0_gsync_stage[2].wr_stg_inst\ : STD_LOGIC;
signal n_0_ram_full_i_i_6 : STD_LOGIC;
signal \n_1_gsync_stage[1].rd_stg_inst\ : STD_LOGIC;
signal \n_1_gsync_stage[1].wr_stg_inst\ : STD_LOGIC;
signal \n_1_gsync_stage[2].wr_stg_inst\ : STD_LOGIC;
signal \n_2_gsync_stage[1].rd_stg_inst\ : STD_LOGIC;
signal \n_2_gsync_stage[1].wr_stg_inst\ : STD_LOGIC;
signal \n_2_gsync_stage[2].wr_stg_inst\ : STD_LOGIC;
signal \n_3_gsync_stage[1].rd_stg_inst\ : STD_LOGIC;
signal \n_3_gsync_stage[1].wr_stg_inst\ : STD_LOGIC;
signal \n_3_gsync_stage[2].wr_stg_inst\ : STD_LOGIC;
signal \n_4_gsync_stage[1].rd_stg_inst\ : STD_LOGIC;
signal \n_4_gsync_stage[1].wr_stg_inst\ : STD_LOGIC;
signal \n_4_gsync_stage[2].wr_stg_inst\ : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 4 downto 0 );
signal p_0_in3_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal rd_pntr_gc : STD_LOGIC_VECTOR ( 4 downto 0 );
signal wr_pntr_gc : STD_LOGIC_VECTOR ( 4 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \wr_pntr_gc[0]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \wr_pntr_gc[1]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \wr_pntr_gc[2]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \wr_pntr_gc[3]_i_1\ : label is "soft_lutpair5";
begin
O3(4 downto 0) <= \^o3\(4 downto 0);
Q(4 downto 0) <= \^q\(4 downto 0);
\gsync_stage[1].rd_stg_inst\: entity work.fifo_async_103x32_synchronizer_ff
port map (
I1(4 downto 0) => wr_pntr_gc(4 downto 0),
I5(0) => I5(0),
Q(4) => \n_0_gsync_stage[1].rd_stg_inst\,
Q(3) => \n_1_gsync_stage[1].rd_stg_inst\,
Q(2) => \n_2_gsync_stage[1].rd_stg_inst\,
Q(1) => \n_3_gsync_stage[1].rd_stg_inst\,
Q(0) => \n_4_gsync_stage[1].rd_stg_inst\,
rd_clk => rd_clk
);
\gsync_stage[1].wr_stg_inst\: entity work.fifo_async_103x32_synchronizer_ff_0
port map (
I1(4 downto 0) => rd_pntr_gc(4 downto 0),
I4(0) => I4(0),
Q(4) => \n_0_gsync_stage[1].wr_stg_inst\,
Q(3) => \n_1_gsync_stage[1].wr_stg_inst\,
Q(2) => \n_2_gsync_stage[1].wr_stg_inst\,
Q(1) => \n_3_gsync_stage[1].wr_stg_inst\,
Q(0) => \n_4_gsync_stage[1].wr_stg_inst\,
wr_clk => wr_clk
);
\gsync_stage[2].rd_stg_inst\: entity work.fifo_async_103x32_synchronizer_ff_1
port map (
D(4) => \n_0_gsync_stage[1].rd_stg_inst\,
D(3) => \n_1_gsync_stage[1].rd_stg_inst\,
D(2) => \n_2_gsync_stage[1].rd_stg_inst\,
D(1) => \n_3_gsync_stage[1].rd_stg_inst\,
D(0) => \n_4_gsync_stage[1].rd_stg_inst\,
I5(0) => I5(0),
p_0_in(4 downto 0) => p_0_in(4 downto 0),
rd_clk => rd_clk
);
\gsync_stage[2].wr_stg_inst\: entity work.fifo_async_103x32_synchronizer_ff_2
port map (
D(4) => \n_0_gsync_stage[1].wr_stg_inst\,
D(3) => \n_1_gsync_stage[1].wr_stg_inst\,
D(2) => \n_2_gsync_stage[1].wr_stg_inst\,
D(1) => \n_3_gsync_stage[1].wr_stg_inst\,
D(0) => \n_4_gsync_stage[1].wr_stg_inst\,
I4(0) => I4(0),
O1(3) => \n_1_gsync_stage[2].wr_stg_inst\,
O1(2) => \n_2_gsync_stage[2].wr_stg_inst\,
O1(1) => \n_3_gsync_stage[2].wr_stg_inst\,
O1(0) => \n_4_gsync_stage[2].wr_stg_inst\,
Q(0) => \n_0_gsync_stage[2].wr_stg_inst\,
wr_clk => wr_clk
);
ram_empty_fb_i_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^q\(2),
I1 => I1(2),
I2 => \^q\(1),
I3 => I1(1),
I4 => I1(0),
I5 => \^q\(0),
O => O1
);
ram_full_i_i_4: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF6FF6"
)
port map (
I0 => I2(0),
I1 => \^o3\(0),
I2 => I2(1),
I3 => \^o3\(1),
I4 => n_0_ram_full_i_i_6,
O => O2
);
ram_full_i_i_6: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => \^o3\(2),
I1 => I2(2),
I2 => \^o3\(4),
I3 => I2(3),
O => n_0_ram_full_i_i_6
);
\rd_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I4(0),
D => \n_4_gsync_stage[2].wr_stg_inst\,
Q => \^o3\(0)
);
\rd_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I4(0),
D => \n_3_gsync_stage[2].wr_stg_inst\,
Q => \^o3\(1)
);
\rd_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I4(0),
D => \n_2_gsync_stage[2].wr_stg_inst\,
Q => \^o3\(2)
);
\rd_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I4(0),
D => \n_1_gsync_stage[2].wr_stg_inst\,
Q => \^o3\(3)
);
\rd_pntr_bin_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I4(0),
D => \n_0_gsync_stage[2].wr_stg_inst\,
Q => \^o3\(4)
);
\rd_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I5(0),
D => D(0),
Q => rd_pntr_gc(0)
);
\rd_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I5(0),
D => D(1),
Q => rd_pntr_gc(1)
);
\rd_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I5(0),
D => D(2),
Q => rd_pntr_gc(2)
);
\rd_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I5(0),
D => D(3),
Q => rd_pntr_gc(3)
);
\rd_pntr_gc_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I5(0),
D => I1(3),
Q => rd_pntr_gc(4)
);
\wr_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I5(0),
D => p_0_in(0),
Q => \^q\(0)
);
\wr_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I5(0),
D => p_0_in(1),
Q => \^q\(1)
);
\wr_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I5(0),
D => p_0_in(2),
Q => \^q\(2)
);
\wr_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I5(0),
D => p_0_in(3),
Q => \^q\(3)
);
\wr_pntr_bin_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I5(0),
D => p_0_in(4),
Q => \^q\(4)
);
\wr_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => I3(0),
I1 => I3(1),
O => p_0_in3_out(0)
);
\wr_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => I3(1),
I1 => I3(2),
O => p_0_in3_out(1)
);
\wr_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => I3(2),
I1 => I3(3),
O => p_0_in3_out(2)
);
\wr_pntr_gc[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => I3(3),
I1 => I3(4),
O => p_0_in3_out(3)
);
\wr_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I4(0),
D => p_0_in3_out(0),
Q => wr_pntr_gc(0)
);
\wr_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I4(0),
D => p_0_in3_out(1),
Q => wr_pntr_gc(1)
);
\wr_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I4(0),
D => p_0_in3_out(2),
Q => wr_pntr_gc(2)
);
\wr_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I4(0),
D => p_0_in3_out(3),
Q => wr_pntr_gc(3)
);
\wr_pntr_gc_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I4(0),
D => I3(4),
Q => wr_pntr_gc(4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x32_memory is
port (
dout : out STD_LOGIC_VECTOR ( 102 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_clk : in STD_LOGIC;
I1 : in STD_LOGIC_VECTOR ( 0 to 0 );
din : in STD_LOGIC_VECTOR ( 102 downto 0 );
O2 : in STD_LOGIC_VECTOR ( 4 downto 0 );
O1 : in STD_LOGIC_VECTOR ( 4 downto 0 );
I2 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x32_memory : entity is "memory";
end fifo_async_103x32_memory;
architecture STRUCTURE of fifo_async_103x32_memory is
signal p_0_out : STD_LOGIC_VECTOR ( 102 downto 0 );
begin
\gdm.dm\: entity work.fifo_async_103x32_dmem
port map (
E(0) => E(0),
I1(0) => Q(0),
I2(0) => I1(0),
O1(4 downto 0) => O1(4 downto 0),
O2(4 downto 0) => O2(4 downto 0),
Q(102 downto 0) => p_0_out(102 downto 0),
din(102 downto 0) => din(102 downto 0),
rd_clk => rd_clk,
wr_clk => wr_clk
);
\goreg_dm.dout_i_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(0),
Q => dout(0)
);
\goreg_dm.dout_i_reg[100]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(100),
Q => dout(100)
);
\goreg_dm.dout_i_reg[101]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(101),
Q => dout(101)
);
\goreg_dm.dout_i_reg[102]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(102),
Q => dout(102)
);
\goreg_dm.dout_i_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(10),
Q => dout(10)
);
\goreg_dm.dout_i_reg[11]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(11),
Q => dout(11)
);
\goreg_dm.dout_i_reg[12]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(12),
Q => dout(12)
);
\goreg_dm.dout_i_reg[13]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(13),
Q => dout(13)
);
\goreg_dm.dout_i_reg[14]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(14),
Q => dout(14)
);
\goreg_dm.dout_i_reg[15]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(15),
Q => dout(15)
);
\goreg_dm.dout_i_reg[16]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(16),
Q => dout(16)
);
\goreg_dm.dout_i_reg[17]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(17),
Q => dout(17)
);
\goreg_dm.dout_i_reg[18]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(18),
Q => dout(18)
);
\goreg_dm.dout_i_reg[19]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(19),
Q => dout(19)
);
\goreg_dm.dout_i_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(1),
Q => dout(1)
);
\goreg_dm.dout_i_reg[20]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(20),
Q => dout(20)
);
\goreg_dm.dout_i_reg[21]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(21),
Q => dout(21)
);
\goreg_dm.dout_i_reg[22]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(22),
Q => dout(22)
);
\goreg_dm.dout_i_reg[23]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(23),
Q => dout(23)
);
\goreg_dm.dout_i_reg[24]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(24),
Q => dout(24)
);
\goreg_dm.dout_i_reg[25]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(25),
Q => dout(25)
);
\goreg_dm.dout_i_reg[26]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(26),
Q => dout(26)
);
\goreg_dm.dout_i_reg[27]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(27),
Q => dout(27)
);
\goreg_dm.dout_i_reg[28]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(28),
Q => dout(28)
);
\goreg_dm.dout_i_reg[29]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(29),
Q => dout(29)
);
\goreg_dm.dout_i_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(2),
Q => dout(2)
);
\goreg_dm.dout_i_reg[30]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(30),
Q => dout(30)
);
\goreg_dm.dout_i_reg[31]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(31),
Q => dout(31)
);
\goreg_dm.dout_i_reg[32]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(32),
Q => dout(32)
);
\goreg_dm.dout_i_reg[33]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(33),
Q => dout(33)
);
\goreg_dm.dout_i_reg[34]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(34),
Q => dout(34)
);
\goreg_dm.dout_i_reg[35]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(35),
Q => dout(35)
);
\goreg_dm.dout_i_reg[36]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(36),
Q => dout(36)
);
\goreg_dm.dout_i_reg[37]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(37),
Q => dout(37)
);
\goreg_dm.dout_i_reg[38]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(38),
Q => dout(38)
);
\goreg_dm.dout_i_reg[39]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(39),
Q => dout(39)
);
\goreg_dm.dout_i_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(3),
Q => dout(3)
);
\goreg_dm.dout_i_reg[40]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(40),
Q => dout(40)
);
\goreg_dm.dout_i_reg[41]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(41),
Q => dout(41)
);
\goreg_dm.dout_i_reg[42]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(42),
Q => dout(42)
);
\goreg_dm.dout_i_reg[43]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(43),
Q => dout(43)
);
\goreg_dm.dout_i_reg[44]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(44),
Q => dout(44)
);
\goreg_dm.dout_i_reg[45]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(45),
Q => dout(45)
);
\goreg_dm.dout_i_reg[46]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(46),
Q => dout(46)
);
\goreg_dm.dout_i_reg[47]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(47),
Q => dout(47)
);
\goreg_dm.dout_i_reg[48]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(48),
Q => dout(48)
);
\goreg_dm.dout_i_reg[49]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(49),
Q => dout(49)
);
\goreg_dm.dout_i_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(4),
Q => dout(4)
);
\goreg_dm.dout_i_reg[50]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(50),
Q => dout(50)
);
\goreg_dm.dout_i_reg[51]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(51),
Q => dout(51)
);
\goreg_dm.dout_i_reg[52]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(52),
Q => dout(52)
);
\goreg_dm.dout_i_reg[53]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(53),
Q => dout(53)
);
\goreg_dm.dout_i_reg[54]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(54),
Q => dout(54)
);
\goreg_dm.dout_i_reg[55]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(55),
Q => dout(55)
);
\goreg_dm.dout_i_reg[56]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(56),
Q => dout(56)
);
\goreg_dm.dout_i_reg[57]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(57),
Q => dout(57)
);
\goreg_dm.dout_i_reg[58]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(58),
Q => dout(58)
);
\goreg_dm.dout_i_reg[59]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(59),
Q => dout(59)
);
\goreg_dm.dout_i_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(5),
Q => dout(5)
);
\goreg_dm.dout_i_reg[60]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(60),
Q => dout(60)
);
\goreg_dm.dout_i_reg[61]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(61),
Q => dout(61)
);
\goreg_dm.dout_i_reg[62]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(62),
Q => dout(62)
);
\goreg_dm.dout_i_reg[63]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(63),
Q => dout(63)
);
\goreg_dm.dout_i_reg[64]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(64),
Q => dout(64)
);
\goreg_dm.dout_i_reg[65]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(65),
Q => dout(65)
);
\goreg_dm.dout_i_reg[66]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(66),
Q => dout(66)
);
\goreg_dm.dout_i_reg[67]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(67),
Q => dout(67)
);
\goreg_dm.dout_i_reg[68]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(68),
Q => dout(68)
);
\goreg_dm.dout_i_reg[69]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(69),
Q => dout(69)
);
\goreg_dm.dout_i_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(6),
Q => dout(6)
);
\goreg_dm.dout_i_reg[70]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(70),
Q => dout(70)
);
\goreg_dm.dout_i_reg[71]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(71),
Q => dout(71)
);
\goreg_dm.dout_i_reg[72]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(72),
Q => dout(72)
);
\goreg_dm.dout_i_reg[73]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(73),
Q => dout(73)
);
\goreg_dm.dout_i_reg[74]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(74),
Q => dout(74)
);
\goreg_dm.dout_i_reg[75]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(75),
Q => dout(75)
);
\goreg_dm.dout_i_reg[76]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(76),
Q => dout(76)
);
\goreg_dm.dout_i_reg[77]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(77),
Q => dout(77)
);
\goreg_dm.dout_i_reg[78]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(78),
Q => dout(78)
);
\goreg_dm.dout_i_reg[79]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(79),
Q => dout(79)
);
\goreg_dm.dout_i_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(7),
Q => dout(7)
);
\goreg_dm.dout_i_reg[80]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(80),
Q => dout(80)
);
\goreg_dm.dout_i_reg[81]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(81),
Q => dout(81)
);
\goreg_dm.dout_i_reg[82]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(82),
Q => dout(82)
);
\goreg_dm.dout_i_reg[83]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(83),
Q => dout(83)
);
\goreg_dm.dout_i_reg[84]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(84),
Q => dout(84)
);
\goreg_dm.dout_i_reg[85]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(85),
Q => dout(85)
);
\goreg_dm.dout_i_reg[86]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(86),
Q => dout(86)
);
\goreg_dm.dout_i_reg[87]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(87),
Q => dout(87)
);
\goreg_dm.dout_i_reg[88]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(88),
Q => dout(88)
);
\goreg_dm.dout_i_reg[89]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(89),
Q => dout(89)
);
\goreg_dm.dout_i_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(8),
Q => dout(8)
);
\goreg_dm.dout_i_reg[90]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(90),
Q => dout(90)
);
\goreg_dm.dout_i_reg[91]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(91),
Q => dout(91)
);
\goreg_dm.dout_i_reg[92]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(92),
Q => dout(92)
);
\goreg_dm.dout_i_reg[93]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(93),
Q => dout(93)
);
\goreg_dm.dout_i_reg[94]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(94),
Q => dout(94)
);
\goreg_dm.dout_i_reg[95]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(95),
Q => dout(95)
);
\goreg_dm.dout_i_reg[96]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(96),
Q => dout(96)
);
\goreg_dm.dout_i_reg[97]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(97),
Q => dout(97)
);
\goreg_dm.dout_i_reg[98]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(98),
Q => dout(98)
);
\goreg_dm.dout_i_reg[99]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(99),
Q => dout(99)
);
\goreg_dm.dout_i_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(9),
Q => dout(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x32_rd_logic is
port (
empty : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
O1 : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
O2 : out STD_LOGIC_VECTOR ( 4 downto 0 );
rd_clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
I1 : in STD_LOGIC_VECTOR ( 4 downto 0 );
rd_en : in STD_LOGIC;
I2 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x32_rd_logic : entity is "rd_logic";
end fifo_async_103x32_rd_logic;
architecture STRUCTURE of fifo_async_103x32_rd_logic is
signal \n_1_gr1.rfwft\ : STD_LOGIC;
signal n_1_rpntr : STD_LOGIC;
signal p_14_out : STD_LOGIC;
signal p_18_out : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 0 to 0 );
begin
\gr1.rfwft\: entity work.fifo_async_103x32_rd_fwft
port map (
E(0) => E(0),
I1(0) => rd_pntr_plus1(0),
I2(0) => I1(0),
O1 => \n_1_gr1.rfwft\,
O2(0) => p_14_out,
O3(0) => O1(0),
Q(0) => Q(0),
empty => empty,
p_18_out => p_18_out,
rd_clk => rd_clk,
rd_en => rd_en
);
\gras.rsts\: entity work.fifo_async_103x32_rd_status_flags_as
port map (
I1 => n_1_rpntr,
Q(0) => Q(0),
p_18_out => p_18_out,
rd_clk => rd_clk
);
rpntr: entity work.fifo_async_103x32_rd_bin_cntr
port map (
D(3 downto 0) => D(3 downto 0),
E(0) => p_14_out,
I1(3 downto 0) => I1(4 downto 1),
I2 => \n_1_gr1.rfwft\,
I3 => I2,
I4(0) => Q(0),
O1 => n_1_rpntr,
O2(4 downto 0) => O2(4 downto 0),
Q(0) => rd_pntr_plus1(0),
rd_clk => rd_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x32_wr_logic is
port (
full : out STD_LOGIC;
prog_full : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
O1 : out STD_LOGIC_VECTOR ( 4 downto 0 );
wr_clk : in STD_LOGIC;
rst_d2 : in STD_LOGIC;
rst_full_gen_i : in STD_LOGIC;
I1 : in STD_LOGIC;
O3 : in STD_LOGIC_VECTOR ( 4 downto 0 );
wr_en : in STD_LOGIC;
I2 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x32_wr_logic : entity is "wr_logic";
end fifo_async_103x32_wr_logic;
architecture STRUCTURE of fifo_async_103x32_wr_logic is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal n_0_wpntr : STD_LOGIC;
signal n_1_wpntr : STD_LOGIC;
signal n_2_wpntr : STD_LOGIC;
signal \n_3_gwas.wsts\ : STD_LOGIC;
signal \n_4_gwas.wsts\ : STD_LOGIC;
signal n_7_wpntr : STD_LOGIC;
signal n_8_wpntr : STD_LOGIC;
signal n_9_wpntr : STD_LOGIC;
signal p_1_out : STD_LOGIC;
signal p_8_out : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
E(0) <= \^e\(0);
\gwas.gpf.wrpf\: entity work.fifo_async_103x32_wr_pf_as
port map (
I1(1) => n_1_wpntr,
I1(0) => n_2_wpntr,
I2(0) => I2(0),
S(2) => n_7_wpntr,
S(1) => n_8_wpntr,
S(0) => n_9_wpntr,
p_1_out => p_1_out,
prog_full => prog_full,
rst_d2 => rst_d2,
rst_full_gen_i => rst_full_gen_i,
wr_clk => wr_clk,
wr_pntr_plus1_pad(4 downto 1) => p_8_out(3 downto 0),
wr_pntr_plus1_pad(0) => \n_4_gwas.wsts\
);
\gwas.wsts\: entity work.fifo_async_103x32_wr_status_flags_as
port map (
E(0) => \^e\(0),
I1 => n_0_wpntr,
O1 => \n_3_gwas.wsts\,
full => full,
p_1_out => p_1_out,
rst_d2 => rst_d2,
wr_clk => wr_clk,
wr_en => wr_en,
wr_pntr_plus1_pad(0) => \n_4_gwas.wsts\
);
wpntr: entity work.fifo_async_103x32_wr_bin_cntr
port map (
E(0) => \^e\(0),
I1 => \n_3_gwas.wsts\,
I2 => I1,
I3(0) => I2(0),
O1 => n_0_wpntr,
O2(1) => n_1_wpntr,
O2(0) => n_2_wpntr,
O3(4 downto 0) => O3(4 downto 0),
O4(3 downto 0) => Q(3 downto 0),
O5(4 downto 0) => O1(4 downto 0),
Q(3 downto 0) => p_8_out(3 downto 0),
S(2) => n_7_wpntr,
S(1) => n_8_wpntr,
S(0) => n_9_wpntr,
rst_full_gen_i => rst_full_gen_i,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x32_fifo_generator_ramfifo is
port (
dout : out STD_LOGIC_VECTOR ( 102 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
prog_full : out STD_LOGIC;
rd_en : in STD_LOGIC;
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 102 downto 0 );
wr_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x32_fifo_generator_ramfifo : entity is "fifo_generator_ramfifo";
end fifo_async_103x32_fifo_generator_ramfifo;
architecture STRUCTURE of fifo_async_103x32_fifo_generator_ramfifo is
signal RD_RST : STD_LOGIC;
signal \^rst\ : STD_LOGIC;
signal WR_RST : STD_LOGIC;
signal \n_0_gntv_or_sync_fifo.gcx.clkx\ : STD_LOGIC;
signal n_2_rstblk : STD_LOGIC;
signal \n_3_gntv_or_sync_fifo.gl0.rd\ : STD_LOGIC;
signal \n_4_gntv_or_sync_fifo.gl0.rd\ : STD_LOGIC;
signal \n_5_gntv_or_sync_fifo.gl0.rd\ : STD_LOGIC;
signal \n_6_gntv_or_sync_fifo.gcx.clkx\ : STD_LOGIC;
signal \n_6_gntv_or_sync_fifo.gl0.rd\ : STD_LOGIC;
signal p_0_out : STD_LOGIC_VECTOR ( 4 downto 0 );
signal p_15_out : STD_LOGIC;
signal p_1_out : STD_LOGIC_VECTOR ( 4 downto 0 );
signal p_20_out : STD_LOGIC_VECTOR ( 4 downto 0 );
signal p_3_out : STD_LOGIC;
signal p_9_out : STD_LOGIC_VECTOR ( 4 downto 0 );
signal ram_rd_en_i : STD_LOGIC;
signal rd_rst_i : STD_LOGIC_VECTOR ( 0 to 0 );
signal rst_d2 : STD_LOGIC;
signal rst_full_gen_i : STD_LOGIC;
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 4 downto 0 );
begin
\gntv_or_sync_fifo.gcx.clkx\: entity work.fifo_async_103x32_clk_x_pntrs
port map (
D(3) => \n_3_gntv_or_sync_fifo.gl0.rd\,
D(2) => \n_4_gntv_or_sync_fifo.gl0.rd\,
D(1) => \n_5_gntv_or_sync_fifo.gl0.rd\,
D(0) => \n_6_gntv_or_sync_fifo.gl0.rd\,
I1(3) => p_20_out(4),
I1(2 downto 0) => p_20_out(2 downto 0),
I2(3) => wr_pntr_plus2(4),
I2(2 downto 0) => wr_pntr_plus2(2 downto 0),
I3(4 downto 0) => p_9_out(4 downto 0),
I4(0) => \^rst\,
I5(0) => RD_RST,
O1 => \n_0_gntv_or_sync_fifo.gcx.clkx\,
O2 => \n_6_gntv_or_sync_fifo.gcx.clkx\,
O3(4 downto 0) => p_0_out(4 downto 0),
Q(4 downto 0) => p_1_out(4 downto 0),
rd_clk => rd_clk,
wr_clk => wr_clk
);
\gntv_or_sync_fifo.gl0.rd\: entity work.fifo_async_103x32_rd_logic
port map (
D(3) => \n_3_gntv_or_sync_fifo.gl0.rd\,
D(2) => \n_4_gntv_or_sync_fifo.gl0.rd\,
D(1) => \n_5_gntv_or_sync_fifo.gl0.rd\,
D(0) => \n_6_gntv_or_sync_fifo.gl0.rd\,
E(0) => p_15_out,
I1(4 downto 0) => p_1_out(4 downto 0),
I2 => \n_0_gntv_or_sync_fifo.gcx.clkx\,
O1(0) => ram_rd_en_i,
O2(4 downto 0) => p_20_out(4 downto 0),
Q(0) => n_2_rstblk,
empty => empty,
rd_clk => rd_clk,
rd_en => rd_en
);
\gntv_or_sync_fifo.gl0.wr\: entity work.fifo_async_103x32_wr_logic
port map (
E(0) => p_3_out,
I1 => \n_6_gntv_or_sync_fifo.gcx.clkx\,
I2(0) => WR_RST,
O1(4 downto 0) => p_9_out(4 downto 0),
O3(4 downto 0) => p_0_out(4 downto 0),
Q(3) => wr_pntr_plus2(4),
Q(2 downto 0) => wr_pntr_plus2(2 downto 0),
full => full,
prog_full => prog_full,
rst_d2 => rst_d2,
rst_full_gen_i => rst_full_gen_i,
wr_clk => wr_clk,
wr_en => wr_en
);
\gntv_or_sync_fifo.mem\: entity work.fifo_async_103x32_memory
port map (
E(0) => ram_rd_en_i,
I1(0) => p_3_out,
I2(0) => p_15_out,
O1(4 downto 0) => p_9_out(4 downto 0),
O2(4 downto 0) => p_20_out(4 downto 0),
Q(0) => rd_rst_i(0),
din(102 downto 0) => din(102 downto 0),
dout(102 downto 0) => dout(102 downto 0),
rd_clk => rd_clk,
wr_clk => wr_clk
);
rstblk: entity work.fifo_async_103x32_reset_blk_ramfifo
port map (
O1(1) => WR_RST,
O1(0) => \^rst\,
Q(2) => n_2_rstblk,
Q(1) => RD_RST,
Q(0) => rd_rst_i(0),
rd_clk => rd_clk,
rst => rst,
rst_d2 => rst_d2,
rst_full_gen_i => rst_full_gen_i,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x32_fifo_generator_top is
port (
dout : out STD_LOGIC_VECTOR ( 102 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
prog_full : out STD_LOGIC;
rd_en : in STD_LOGIC;
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 102 downto 0 );
wr_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x32_fifo_generator_top : entity is "fifo_generator_top";
end fifo_async_103x32_fifo_generator_top;
architecture STRUCTURE of fifo_async_103x32_fifo_generator_top is
begin
\grf.rf\: entity work.fifo_async_103x32_fifo_generator_ramfifo
port map (
din(102 downto 0) => din(102 downto 0),
dout(102 downto 0) => dout(102 downto 0),
empty => empty,
full => full,
prog_full => prog_full,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x32_fifo_generator_v12_0_synth is
port (
dout : out STD_LOGIC_VECTOR ( 102 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
prog_full : out STD_LOGIC;
rd_en : in STD_LOGIC;
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 102 downto 0 );
wr_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x32_fifo_generator_v12_0_synth : entity is "fifo_generator_v12_0_synth";
end fifo_async_103x32_fifo_generator_v12_0_synth;
architecture STRUCTURE of fifo_async_103x32_fifo_generator_v12_0_synth is
begin
\gconvfifo.rf\: entity work.fifo_async_103x32_fifo_generator_top
port map (
din(102 downto 0) => din(102 downto 0),
dout(102 downto 0) => dout(102 downto 0),
empty => empty,
full => full,
prog_full => prog_full,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ is
port (
backup : in STD_LOGIC;
backup_marker : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
srst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 102 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
prog_empty_thresh : in STD_LOGIC_VECTOR ( 4 downto 0 );
prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 4 downto 0 );
prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 4 downto 0 );
prog_full_thresh : in STD_LOGIC_VECTOR ( 4 downto 0 );
prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 4 downto 0 );
prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 4 downto 0 );
int_clk : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
injectsbiterr : in STD_LOGIC;
sleep : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 102 downto 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
wr_ack : out STD_LOGIC;
overflow : out STD_LOGIC;
empty : out STD_LOGIC;
almost_empty : out STD_LOGIC;
valid : out STD_LOGIC;
underflow : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
m_aclk_en : in STD_LOGIC;
s_aclk_en : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_tstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tlast : in STD_LOGIC;
s_axis_tid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tdest : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_tstrb : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tlast : out STD_LOGIC;
m_axis_tid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tdest : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_injectsbiterr : in STD_LOGIC;
axi_aw_injectdbiterr : in STD_LOGIC;
axi_aw_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_sbiterr : out STD_LOGIC;
axi_aw_dbiterr : out STD_LOGIC;
axi_aw_overflow : out STD_LOGIC;
axi_aw_underflow : out STD_LOGIC;
axi_aw_prog_full : out STD_LOGIC;
axi_aw_prog_empty : out STD_LOGIC;
axi_w_injectsbiterr : in STD_LOGIC;
axi_w_injectdbiterr : in STD_LOGIC;
axi_w_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_sbiterr : out STD_LOGIC;
axi_w_dbiterr : out STD_LOGIC;
axi_w_overflow : out STD_LOGIC;
axi_w_underflow : out STD_LOGIC;
axi_w_prog_full : out STD_LOGIC;
axi_w_prog_empty : out STD_LOGIC;
axi_b_injectsbiterr : in STD_LOGIC;
axi_b_injectdbiterr : in STD_LOGIC;
axi_b_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_sbiterr : out STD_LOGIC;
axi_b_dbiterr : out STD_LOGIC;
axi_b_overflow : out STD_LOGIC;
axi_b_underflow : out STD_LOGIC;
axi_b_prog_full : out STD_LOGIC;
axi_b_prog_empty : out STD_LOGIC;
axi_ar_injectsbiterr : in STD_LOGIC;
axi_ar_injectdbiterr : in STD_LOGIC;
axi_ar_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_sbiterr : out STD_LOGIC;
axi_ar_dbiterr : out STD_LOGIC;
axi_ar_overflow : out STD_LOGIC;
axi_ar_underflow : out STD_LOGIC;
axi_ar_prog_full : out STD_LOGIC;
axi_ar_prog_empty : out STD_LOGIC;
axi_r_injectsbiterr : in STD_LOGIC;
axi_r_injectdbiterr : in STD_LOGIC;
axi_r_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_sbiterr : out STD_LOGIC;
axi_r_dbiterr : out STD_LOGIC;
axi_r_overflow : out STD_LOGIC;
axi_r_underflow : out STD_LOGIC;
axi_r_prog_full : out STD_LOGIC;
axi_r_prog_empty : out STD_LOGIC;
axis_injectsbiterr : in STD_LOGIC;
axis_injectdbiterr : in STD_LOGIC;
axis_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_sbiterr : out STD_LOGIC;
axis_dbiterr : out STD_LOGIC;
axis_overflow : out STD_LOGIC;
axis_underflow : out STD_LOGIC;
axis_prog_full : out STD_LOGIC;
axis_prog_empty : out STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is "fifo_generator_v12_0";
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 5;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 103;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 103;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is "zynq";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 2;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 2;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is "BlankString";
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is "512x72";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 4;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 5;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 16;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 15;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 5;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 32;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 5;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 5;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 32;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 5;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 2;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 32;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 64;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 8;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 4;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is "1kx18";
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 32;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 2;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 64;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 16;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1024;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1024;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 4;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 10;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 10;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1023;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1022;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
end \fifo_async_103x32_fifo_generator_v12_0__parameterized0\;
architecture STRUCTURE of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
almost_empty <= \<const0>\;
almost_full <= \<const0>\;
axi_ar_data_count(4) <= \<const0>\;
axi_ar_data_count(3) <= \<const0>\;
axi_ar_data_count(2) <= \<const0>\;
axi_ar_data_count(1) <= \<const0>\;
axi_ar_data_count(0) <= \<const0>\;
axi_ar_dbiterr <= \<const0>\;
axi_ar_overflow <= \<const0>\;
axi_ar_prog_empty <= \<const1>\;
axi_ar_prog_full <= \<const0>\;
axi_ar_rd_data_count(4) <= \<const0>\;
axi_ar_rd_data_count(3) <= \<const0>\;
axi_ar_rd_data_count(2) <= \<const0>\;
axi_ar_rd_data_count(1) <= \<const0>\;
axi_ar_rd_data_count(0) <= \<const0>\;
axi_ar_sbiterr <= \<const0>\;
axi_ar_underflow <= \<const0>\;
axi_ar_wr_data_count(4) <= \<const0>\;
axi_ar_wr_data_count(3) <= \<const0>\;
axi_ar_wr_data_count(2) <= \<const0>\;
axi_ar_wr_data_count(1) <= \<const0>\;
axi_ar_wr_data_count(0) <= \<const0>\;
axi_aw_data_count(4) <= \<const0>\;
axi_aw_data_count(3) <= \<const0>\;
axi_aw_data_count(2) <= \<const0>\;
axi_aw_data_count(1) <= \<const0>\;
axi_aw_data_count(0) <= \<const0>\;
axi_aw_dbiterr <= \<const0>\;
axi_aw_overflow <= \<const0>\;
axi_aw_prog_empty <= \<const1>\;
axi_aw_prog_full <= \<const0>\;
axi_aw_rd_data_count(4) <= \<const0>\;
axi_aw_rd_data_count(3) <= \<const0>\;
axi_aw_rd_data_count(2) <= \<const0>\;
axi_aw_rd_data_count(1) <= \<const0>\;
axi_aw_rd_data_count(0) <= \<const0>\;
axi_aw_sbiterr <= \<const0>\;
axi_aw_underflow <= \<const0>\;
axi_aw_wr_data_count(4) <= \<const0>\;
axi_aw_wr_data_count(3) <= \<const0>\;
axi_aw_wr_data_count(2) <= \<const0>\;
axi_aw_wr_data_count(1) <= \<const0>\;
axi_aw_wr_data_count(0) <= \<const0>\;
axi_b_data_count(4) <= \<const0>\;
axi_b_data_count(3) <= \<const0>\;
axi_b_data_count(2) <= \<const0>\;
axi_b_data_count(1) <= \<const0>\;
axi_b_data_count(0) <= \<const0>\;
axi_b_dbiterr <= \<const0>\;
axi_b_overflow <= \<const0>\;
axi_b_prog_empty <= \<const1>\;
axi_b_prog_full <= \<const0>\;
axi_b_rd_data_count(4) <= \<const0>\;
axi_b_rd_data_count(3) <= \<const0>\;
axi_b_rd_data_count(2) <= \<const0>\;
axi_b_rd_data_count(1) <= \<const0>\;
axi_b_rd_data_count(0) <= \<const0>\;
axi_b_sbiterr <= \<const0>\;
axi_b_underflow <= \<const0>\;
axi_b_wr_data_count(4) <= \<const0>\;
axi_b_wr_data_count(3) <= \<const0>\;
axi_b_wr_data_count(2) <= \<const0>\;
axi_b_wr_data_count(1) <= \<const0>\;
axi_b_wr_data_count(0) <= \<const0>\;
axi_r_data_count(10) <= \<const0>\;
axi_r_data_count(9) <= \<const0>\;
axi_r_data_count(8) <= \<const0>\;
axi_r_data_count(7) <= \<const0>\;
axi_r_data_count(6) <= \<const0>\;
axi_r_data_count(5) <= \<const0>\;
axi_r_data_count(4) <= \<const0>\;
axi_r_data_count(3) <= \<const0>\;
axi_r_data_count(2) <= \<const0>\;
axi_r_data_count(1) <= \<const0>\;
axi_r_data_count(0) <= \<const0>\;
axi_r_dbiterr <= \<const0>\;
axi_r_overflow <= \<const0>\;
axi_r_prog_empty <= \<const1>\;
axi_r_prog_full <= \<const0>\;
axi_r_rd_data_count(10) <= \<const0>\;
axi_r_rd_data_count(9) <= \<const0>\;
axi_r_rd_data_count(8) <= \<const0>\;
axi_r_rd_data_count(7) <= \<const0>\;
axi_r_rd_data_count(6) <= \<const0>\;
axi_r_rd_data_count(5) <= \<const0>\;
axi_r_rd_data_count(4) <= \<const0>\;
axi_r_rd_data_count(3) <= \<const0>\;
axi_r_rd_data_count(2) <= \<const0>\;
axi_r_rd_data_count(1) <= \<const0>\;
axi_r_rd_data_count(0) <= \<const0>\;
axi_r_sbiterr <= \<const0>\;
axi_r_underflow <= \<const0>\;
axi_r_wr_data_count(10) <= \<const0>\;
axi_r_wr_data_count(9) <= \<const0>\;
axi_r_wr_data_count(8) <= \<const0>\;
axi_r_wr_data_count(7) <= \<const0>\;
axi_r_wr_data_count(6) <= \<const0>\;
axi_r_wr_data_count(5) <= \<const0>\;
axi_r_wr_data_count(4) <= \<const0>\;
axi_r_wr_data_count(3) <= \<const0>\;
axi_r_wr_data_count(2) <= \<const0>\;
axi_r_wr_data_count(1) <= \<const0>\;
axi_r_wr_data_count(0) <= \<const0>\;
axi_w_data_count(10) <= \<const0>\;
axi_w_data_count(9) <= \<const0>\;
axi_w_data_count(8) <= \<const0>\;
axi_w_data_count(7) <= \<const0>\;
axi_w_data_count(6) <= \<const0>\;
axi_w_data_count(5) <= \<const0>\;
axi_w_data_count(4) <= \<const0>\;
axi_w_data_count(3) <= \<const0>\;
axi_w_data_count(2) <= \<const0>\;
axi_w_data_count(1) <= \<const0>\;
axi_w_data_count(0) <= \<const0>\;
axi_w_dbiterr <= \<const0>\;
axi_w_overflow <= \<const0>\;
axi_w_prog_empty <= \<const1>\;
axi_w_prog_full <= \<const0>\;
axi_w_rd_data_count(10) <= \<const0>\;
axi_w_rd_data_count(9) <= \<const0>\;
axi_w_rd_data_count(8) <= \<const0>\;
axi_w_rd_data_count(7) <= \<const0>\;
axi_w_rd_data_count(6) <= \<const0>\;
axi_w_rd_data_count(5) <= \<const0>\;
axi_w_rd_data_count(4) <= \<const0>\;
axi_w_rd_data_count(3) <= \<const0>\;
axi_w_rd_data_count(2) <= \<const0>\;
axi_w_rd_data_count(1) <= \<const0>\;
axi_w_rd_data_count(0) <= \<const0>\;
axi_w_sbiterr <= \<const0>\;
axi_w_underflow <= \<const0>\;
axi_w_wr_data_count(10) <= \<const0>\;
axi_w_wr_data_count(9) <= \<const0>\;
axi_w_wr_data_count(8) <= \<const0>\;
axi_w_wr_data_count(7) <= \<const0>\;
axi_w_wr_data_count(6) <= \<const0>\;
axi_w_wr_data_count(5) <= \<const0>\;
axi_w_wr_data_count(4) <= \<const0>\;
axi_w_wr_data_count(3) <= \<const0>\;
axi_w_wr_data_count(2) <= \<const0>\;
axi_w_wr_data_count(1) <= \<const0>\;
axi_w_wr_data_count(0) <= \<const0>\;
axis_data_count(10) <= \<const0>\;
axis_data_count(9) <= \<const0>\;
axis_data_count(8) <= \<const0>\;
axis_data_count(7) <= \<const0>\;
axis_data_count(6) <= \<const0>\;
axis_data_count(5) <= \<const0>\;
axis_data_count(4) <= \<const0>\;
axis_data_count(3) <= \<const0>\;
axis_data_count(2) <= \<const0>\;
axis_data_count(1) <= \<const0>\;
axis_data_count(0) <= \<const0>\;
axis_dbiterr <= \<const0>\;
axis_overflow <= \<const0>\;
axis_prog_empty <= \<const1>\;
axis_prog_full <= \<const0>\;
axis_rd_data_count(10) <= \<const0>\;
axis_rd_data_count(9) <= \<const0>\;
axis_rd_data_count(8) <= \<const0>\;
axis_rd_data_count(7) <= \<const0>\;
axis_rd_data_count(6) <= \<const0>\;
axis_rd_data_count(5) <= \<const0>\;
axis_rd_data_count(4) <= \<const0>\;
axis_rd_data_count(3) <= \<const0>\;
axis_rd_data_count(2) <= \<const0>\;
axis_rd_data_count(1) <= \<const0>\;
axis_rd_data_count(0) <= \<const0>\;
axis_sbiterr <= \<const0>\;
axis_underflow <= \<const0>\;
axis_wr_data_count(10) <= \<const0>\;
axis_wr_data_count(9) <= \<const0>\;
axis_wr_data_count(8) <= \<const0>\;
axis_wr_data_count(7) <= \<const0>\;
axis_wr_data_count(6) <= \<const0>\;
axis_wr_data_count(5) <= \<const0>\;
axis_wr_data_count(4) <= \<const0>\;
axis_wr_data_count(3) <= \<const0>\;
axis_wr_data_count(2) <= \<const0>\;
axis_wr_data_count(1) <= \<const0>\;
axis_wr_data_count(0) <= \<const0>\;
data_count(4) <= \<const0>\;
data_count(3) <= \<const0>\;
data_count(2) <= \<const0>\;
data_count(1) <= \<const0>\;
data_count(0) <= \<const0>\;
dbiterr <= \<const0>\;
m_axi_araddr(31) <= \<const0>\;
m_axi_araddr(30) <= \<const0>\;
m_axi_araddr(29) <= \<const0>\;
m_axi_araddr(28) <= \<const0>\;
m_axi_araddr(27) <= \<const0>\;
m_axi_araddr(26) <= \<const0>\;
m_axi_araddr(25) <= \<const0>\;
m_axi_araddr(24) <= \<const0>\;
m_axi_araddr(23) <= \<const0>\;
m_axi_araddr(22) <= \<const0>\;
m_axi_araddr(21) <= \<const0>\;
m_axi_araddr(20) <= \<const0>\;
m_axi_araddr(19) <= \<const0>\;
m_axi_araddr(18) <= \<const0>\;
m_axi_araddr(17) <= \<const0>\;
m_axi_araddr(16) <= \<const0>\;
m_axi_araddr(15) <= \<const0>\;
m_axi_araddr(14) <= \<const0>\;
m_axi_araddr(13) <= \<const0>\;
m_axi_araddr(12) <= \<const0>\;
m_axi_araddr(11) <= \<const0>\;
m_axi_araddr(10) <= \<const0>\;
m_axi_araddr(9) <= \<const0>\;
m_axi_araddr(8) <= \<const0>\;
m_axi_araddr(7) <= \<const0>\;
m_axi_araddr(6) <= \<const0>\;
m_axi_araddr(5) <= \<const0>\;
m_axi_araddr(4) <= \<const0>\;
m_axi_araddr(3) <= \<const0>\;
m_axi_araddr(2) <= \<const0>\;
m_axi_araddr(1) <= \<const0>\;
m_axi_araddr(0) <= \<const0>\;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const0>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arprot(2) <= \<const0>\;
m_axi_arprot(1) <= \<const0>\;
m_axi_arprot(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const0>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_arvalid <= \<const0>\;
m_axi_awaddr(31) <= \<const0>\;
m_axi_awaddr(30) <= \<const0>\;
m_axi_awaddr(29) <= \<const0>\;
m_axi_awaddr(28) <= \<const0>\;
m_axi_awaddr(27) <= \<const0>\;
m_axi_awaddr(26) <= \<const0>\;
m_axi_awaddr(25) <= \<const0>\;
m_axi_awaddr(24) <= \<const0>\;
m_axi_awaddr(23) <= \<const0>\;
m_axi_awaddr(22) <= \<const0>\;
m_axi_awaddr(21) <= \<const0>\;
m_axi_awaddr(20) <= \<const0>\;
m_axi_awaddr(19) <= \<const0>\;
m_axi_awaddr(18) <= \<const0>\;
m_axi_awaddr(17) <= \<const0>\;
m_axi_awaddr(16) <= \<const0>\;
m_axi_awaddr(15) <= \<const0>\;
m_axi_awaddr(14) <= \<const0>\;
m_axi_awaddr(13) <= \<const0>\;
m_axi_awaddr(12) <= \<const0>\;
m_axi_awaddr(11) <= \<const0>\;
m_axi_awaddr(10) <= \<const0>\;
m_axi_awaddr(9) <= \<const0>\;
m_axi_awaddr(8) <= \<const0>\;
m_axi_awaddr(7) <= \<const0>\;
m_axi_awaddr(6) <= \<const0>\;
m_axi_awaddr(5) <= \<const0>\;
m_axi_awaddr(4) <= \<const0>\;
m_axi_awaddr(3) <= \<const0>\;
m_axi_awaddr(2) <= \<const0>\;
m_axi_awaddr(1) <= \<const0>\;
m_axi_awaddr(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const0>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awprot(2) <= \<const0>\;
m_axi_awprot(1) <= \<const0>\;
m_axi_awprot(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const0>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_awvalid <= \<const0>\;
m_axi_bready <= \<const0>\;
m_axi_rready <= \<const0>\;
m_axi_wdata(63) <= \<const0>\;
m_axi_wdata(62) <= \<const0>\;
m_axi_wdata(61) <= \<const0>\;
m_axi_wdata(60) <= \<const0>\;
m_axi_wdata(59) <= \<const0>\;
m_axi_wdata(58) <= \<const0>\;
m_axi_wdata(57) <= \<const0>\;
m_axi_wdata(56) <= \<const0>\;
m_axi_wdata(55) <= \<const0>\;
m_axi_wdata(54) <= \<const0>\;
m_axi_wdata(53) <= \<const0>\;
m_axi_wdata(52) <= \<const0>\;
m_axi_wdata(51) <= \<const0>\;
m_axi_wdata(50) <= \<const0>\;
m_axi_wdata(49) <= \<const0>\;
m_axi_wdata(48) <= \<const0>\;
m_axi_wdata(47) <= \<const0>\;
m_axi_wdata(46) <= \<const0>\;
m_axi_wdata(45) <= \<const0>\;
m_axi_wdata(44) <= \<const0>\;
m_axi_wdata(43) <= \<const0>\;
m_axi_wdata(42) <= \<const0>\;
m_axi_wdata(41) <= \<const0>\;
m_axi_wdata(40) <= \<const0>\;
m_axi_wdata(39) <= \<const0>\;
m_axi_wdata(38) <= \<const0>\;
m_axi_wdata(37) <= \<const0>\;
m_axi_wdata(36) <= \<const0>\;
m_axi_wdata(35) <= \<const0>\;
m_axi_wdata(34) <= \<const0>\;
m_axi_wdata(33) <= \<const0>\;
m_axi_wdata(32) <= \<const0>\;
m_axi_wdata(31) <= \<const0>\;
m_axi_wdata(30) <= \<const0>\;
m_axi_wdata(29) <= \<const0>\;
m_axi_wdata(28) <= \<const0>\;
m_axi_wdata(27) <= \<const0>\;
m_axi_wdata(26) <= \<const0>\;
m_axi_wdata(25) <= \<const0>\;
m_axi_wdata(24) <= \<const0>\;
m_axi_wdata(23) <= \<const0>\;
m_axi_wdata(22) <= \<const0>\;
m_axi_wdata(21) <= \<const0>\;
m_axi_wdata(20) <= \<const0>\;
m_axi_wdata(19) <= \<const0>\;
m_axi_wdata(18) <= \<const0>\;
m_axi_wdata(17) <= \<const0>\;
m_axi_wdata(16) <= \<const0>\;
m_axi_wdata(15) <= \<const0>\;
m_axi_wdata(14) <= \<const0>\;
m_axi_wdata(13) <= \<const0>\;
m_axi_wdata(12) <= \<const0>\;
m_axi_wdata(11) <= \<const0>\;
m_axi_wdata(10) <= \<const0>\;
m_axi_wdata(9) <= \<const0>\;
m_axi_wdata(8) <= \<const0>\;
m_axi_wdata(7) <= \<const0>\;
m_axi_wdata(6) <= \<const0>\;
m_axi_wdata(5) <= \<const0>\;
m_axi_wdata(4) <= \<const0>\;
m_axi_wdata(3) <= \<const0>\;
m_axi_wdata(2) <= \<const0>\;
m_axi_wdata(1) <= \<const0>\;
m_axi_wdata(0) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const0>\;
m_axi_wstrb(7) <= \<const0>\;
m_axi_wstrb(6) <= \<const0>\;
m_axi_wstrb(5) <= \<const0>\;
m_axi_wstrb(4) <= \<const0>\;
m_axi_wstrb(3) <= \<const0>\;
m_axi_wstrb(2) <= \<const0>\;
m_axi_wstrb(1) <= \<const0>\;
m_axi_wstrb(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \<const0>\;
m_axis_tdata(7) <= \<const0>\;
m_axis_tdata(6) <= \<const0>\;
m_axis_tdata(5) <= \<const0>\;
m_axis_tdata(4) <= \<const0>\;
m_axis_tdata(3) <= \<const0>\;
m_axis_tdata(2) <= \<const0>\;
m_axis_tdata(1) <= \<const0>\;
m_axis_tdata(0) <= \<const0>\;
m_axis_tdest(0) <= \<const0>\;
m_axis_tid(0) <= \<const0>\;
m_axis_tkeep(0) <= \<const0>\;
m_axis_tlast <= \<const0>\;
m_axis_tstrb(0) <= \<const0>\;
m_axis_tuser(3) <= \<const0>\;
m_axis_tuser(2) <= \<const0>\;
m_axis_tuser(1) <= \<const0>\;
m_axis_tuser(0) <= \<const0>\;
m_axis_tvalid <= \<const0>\;
overflow <= \<const0>\;
prog_empty <= \<const0>\;
rd_data_count(4) <= \<const0>\;
rd_data_count(3) <= \<const0>\;
rd_data_count(2) <= \<const0>\;
rd_data_count(1) <= \<const0>\;
rd_data_count(0) <= \<const0>\;
rd_rst_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_rdata(63) <= \<const0>\;
s_axi_rdata(62) <= \<const0>\;
s_axi_rdata(61) <= \<const0>\;
s_axi_rdata(60) <= \<const0>\;
s_axi_rdata(59) <= \<const0>\;
s_axi_rdata(58) <= \<const0>\;
s_axi_rdata(57) <= \<const0>\;
s_axi_rdata(56) <= \<const0>\;
s_axi_rdata(55) <= \<const0>\;
s_axi_rdata(54) <= \<const0>\;
s_axi_rdata(53) <= \<const0>\;
s_axi_rdata(52) <= \<const0>\;
s_axi_rdata(51) <= \<const0>\;
s_axi_rdata(50) <= \<const0>\;
s_axi_rdata(49) <= \<const0>\;
s_axi_rdata(48) <= \<const0>\;
s_axi_rdata(47) <= \<const0>\;
s_axi_rdata(46) <= \<const0>\;
s_axi_rdata(45) <= \<const0>\;
s_axi_rdata(44) <= \<const0>\;
s_axi_rdata(43) <= \<const0>\;
s_axi_rdata(42) <= \<const0>\;
s_axi_rdata(41) <= \<const0>\;
s_axi_rdata(40) <= \<const0>\;
s_axi_rdata(39) <= \<const0>\;
s_axi_rdata(38) <= \<const0>\;
s_axi_rdata(37) <= \<const0>\;
s_axi_rdata(36) <= \<const0>\;
s_axi_rdata(35) <= \<const0>\;
s_axi_rdata(34) <= \<const0>\;
s_axi_rdata(33) <= \<const0>\;
s_axi_rdata(32) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_wready <= \<const0>\;
s_axis_tready <= \<const0>\;
sbiterr <= \<const0>\;
underflow <= \<const0>\;
valid <= \<const0>\;
wr_ack <= \<const0>\;
wr_data_count(4) <= \<const0>\;
wr_data_count(3) <= \<const0>\;
wr_data_count(2) <= \<const0>\;
wr_data_count(1) <= \<const0>\;
wr_data_count(0) <= \<const0>\;
wr_rst_busy <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
inst_fifo_gen: entity work.fifo_async_103x32_fifo_generator_v12_0_synth
port map (
din(102 downto 0) => din(102 downto 0),
dout(102 downto 0) => dout(102 downto 0),
empty => empty,
full => full,
prog_full => prog_full,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x32 is
port (
rst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 102 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 102 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC;
prog_full : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of fifo_async_103x32 : entity is true;
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of fifo_async_103x32 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of fifo_async_103x32 : entity is "fifo_generator_v12_0,Vivado 2014.3.1";
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of fifo_async_103x32 : entity is "fifo_async_103x32,fifo_generator_v12_0,{}";
attribute core_generation_info : string;
attribute core_generation_info of fifo_async_103x32 : entity is "fifo_async_103x32,fifo_generator_v12_0,{x_ipProduct=Vivado 2014.3.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=12.0,x_ipCoreRevision=2,x_ipLanguage=VERILOG,C_COMMON_CLOCK=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=5,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=103,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=103,C_ENABLE_RLOCS=0,C_FAMILY=zynq,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=2,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=2,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=0,C_PRELOAD_REGS=1,C_PRIM_FIFO_TYPE=512x72,C_PROG_EMPTY_THRESH_ASSERT_VAL=4,C_PROG_EMPTY_THRESH_NEGATE_VAL=5,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=16,C_PROG_FULL_THRESH_NEGATE_VAL=15,C_PROG_FULL_TYPE=1,C_RD_DATA_COUNT_WIDTH=5,C_RD_DEPTH=32,C_RD_FREQ=1,C_RD_PNTR_WIDTH=5,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=5,C_WR_DEPTH=32,C_WR_FREQ=1,C_WR_PNTR_WIDTH=5,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
end fifo_async_103x32;
architecture STRUCTURE of fifo_async_103x32 is
signal NLW_U0_almost_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_almost_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_arvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_awvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_bready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_rready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rd_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_valid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_ack_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_r_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of U0 : label is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of U0 : label is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of U0 : label is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of U0 : label is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of U0 : label is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of U0 : label is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of U0 : label is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of U0 : label is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of U0 : label is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of U0 : label is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of U0 : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of U0 : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of U0 : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of U0 : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of U0 : label is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of U0 : label is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of U0 : label is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of U0 : label is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of U0 : label is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of U0 : label is 0;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of U0 : label is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of U0 : label is 5;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of U0 : label is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of U0 : label is 103;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of U0 : label is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of U0 : label is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of U0 : label is 32;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of U0 : label is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of U0 : label is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of U0 : label is 103;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of U0 : label is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of U0 : label is 1;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of U0 : label is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of U0 : label is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of U0 : label is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of U0 : label is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of U0 : label is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of U0 : label is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of U0 : label is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of U0 : label is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of U0 : label is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of U0 : label is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of U0 : label is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of U0 : label is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of U0 : label is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of U0 : label is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of U0 : label is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of U0 : label is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of U0 : label is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of U0 : label is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of U0 : label is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of U0 : label is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of U0 : label is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of U0 : label is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of U0 : label is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of U0 : label is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of U0 : label is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of U0 : label is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of U0 : label is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of U0 : label is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of U0 : label is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of U0 : label is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of U0 : label is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of U0 : label is 2;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of U0 : label is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of U0 : label is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of U0 : label is 2;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of U0 : label is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of U0 : label is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of U0 : label is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of U0 : label is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of U0 : label is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of U0 : label is 0;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of U0 : label is 1;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of U0 : label is "512x72";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of U0 : label is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of U0 : label is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of U0 : label is 4;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of U0 : label is 5;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of U0 : label is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of U0 : label is 16;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of U0 : label is 15;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of U0 : label is 1;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of U0 : label is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of U0 : label is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of U0 : label is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of U0 : label is 5;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of U0 : label is 32;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of U0 : label is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of U0 : label is 5;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of U0 : label is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of U0 : label is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of U0 : label is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of U0 : label is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of U0 : label is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of U0 : label is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of U0 : label is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of U0 : label is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of U0 : label is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of U0 : label is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of U0 : label is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of U0 : label is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of U0 : label is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of U0 : label is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of U0 : label is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of U0 : label is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of U0 : label is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of U0 : label is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of U0 : label is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of U0 : label is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of U0 : label is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of U0 : label is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of U0 : label is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of U0 : label is 5;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of U0 : label is 32;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of U0 : label is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of U0 : label is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of U0 : label is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of U0 : label is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of U0 : label is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of U0 : label is 5;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of U0 : label is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of U0 : label is 1;
begin
U0: entity work.\fifo_async_103x32_fifo_generator_v12_0__parameterized0\
port map (
almost_empty => NLW_U0_almost_empty_UNCONNECTED,
almost_full => NLW_U0_almost_full_UNCONNECTED,
axi_ar_data_count(4 downto 0) => NLW_U0_axi_ar_data_count_UNCONNECTED(4 downto 0),
axi_ar_dbiterr => NLW_U0_axi_ar_dbiterr_UNCONNECTED,
axi_ar_injectdbiterr => '0',
axi_ar_injectsbiterr => '0',
axi_ar_overflow => NLW_U0_axi_ar_overflow_UNCONNECTED,
axi_ar_prog_empty => NLW_U0_axi_ar_prog_empty_UNCONNECTED,
axi_ar_prog_empty_thresh(3) => '0',
axi_ar_prog_empty_thresh(2) => '0',
axi_ar_prog_empty_thresh(1) => '0',
axi_ar_prog_empty_thresh(0) => '0',
axi_ar_prog_full => NLW_U0_axi_ar_prog_full_UNCONNECTED,
axi_ar_prog_full_thresh(3) => '0',
axi_ar_prog_full_thresh(2) => '0',
axi_ar_prog_full_thresh(1) => '0',
axi_ar_prog_full_thresh(0) => '0',
axi_ar_rd_data_count(4 downto 0) => NLW_U0_axi_ar_rd_data_count_UNCONNECTED(4 downto 0),
axi_ar_sbiterr => NLW_U0_axi_ar_sbiterr_UNCONNECTED,
axi_ar_underflow => NLW_U0_axi_ar_underflow_UNCONNECTED,
axi_ar_wr_data_count(4 downto 0) => NLW_U0_axi_ar_wr_data_count_UNCONNECTED(4 downto 0),
axi_aw_data_count(4 downto 0) => NLW_U0_axi_aw_data_count_UNCONNECTED(4 downto 0),
axi_aw_dbiterr => NLW_U0_axi_aw_dbiterr_UNCONNECTED,
axi_aw_injectdbiterr => '0',
axi_aw_injectsbiterr => '0',
axi_aw_overflow => NLW_U0_axi_aw_overflow_UNCONNECTED,
axi_aw_prog_empty => NLW_U0_axi_aw_prog_empty_UNCONNECTED,
axi_aw_prog_empty_thresh(3) => '0',
axi_aw_prog_empty_thresh(2) => '0',
axi_aw_prog_empty_thresh(1) => '0',
axi_aw_prog_empty_thresh(0) => '0',
axi_aw_prog_full => NLW_U0_axi_aw_prog_full_UNCONNECTED,
axi_aw_prog_full_thresh(3) => '0',
axi_aw_prog_full_thresh(2) => '0',
axi_aw_prog_full_thresh(1) => '0',
axi_aw_prog_full_thresh(0) => '0',
axi_aw_rd_data_count(4 downto 0) => NLW_U0_axi_aw_rd_data_count_UNCONNECTED(4 downto 0),
axi_aw_sbiterr => NLW_U0_axi_aw_sbiterr_UNCONNECTED,
axi_aw_underflow => NLW_U0_axi_aw_underflow_UNCONNECTED,
axi_aw_wr_data_count(4 downto 0) => NLW_U0_axi_aw_wr_data_count_UNCONNECTED(4 downto 0),
axi_b_data_count(4 downto 0) => NLW_U0_axi_b_data_count_UNCONNECTED(4 downto 0),
axi_b_dbiterr => NLW_U0_axi_b_dbiterr_UNCONNECTED,
axi_b_injectdbiterr => '0',
axi_b_injectsbiterr => '0',
axi_b_overflow => NLW_U0_axi_b_overflow_UNCONNECTED,
axi_b_prog_empty => NLW_U0_axi_b_prog_empty_UNCONNECTED,
axi_b_prog_empty_thresh(3) => '0',
axi_b_prog_empty_thresh(2) => '0',
axi_b_prog_empty_thresh(1) => '0',
axi_b_prog_empty_thresh(0) => '0',
axi_b_prog_full => NLW_U0_axi_b_prog_full_UNCONNECTED,
axi_b_prog_full_thresh(3) => '0',
axi_b_prog_full_thresh(2) => '0',
axi_b_prog_full_thresh(1) => '0',
axi_b_prog_full_thresh(0) => '0',
axi_b_rd_data_count(4 downto 0) => NLW_U0_axi_b_rd_data_count_UNCONNECTED(4 downto 0),
axi_b_sbiterr => NLW_U0_axi_b_sbiterr_UNCONNECTED,
axi_b_underflow => NLW_U0_axi_b_underflow_UNCONNECTED,
axi_b_wr_data_count(4 downto 0) => NLW_U0_axi_b_wr_data_count_UNCONNECTED(4 downto 0),
axi_r_data_count(10 downto 0) => NLW_U0_axi_r_data_count_UNCONNECTED(10 downto 0),
axi_r_dbiterr => NLW_U0_axi_r_dbiterr_UNCONNECTED,
axi_r_injectdbiterr => '0',
axi_r_injectsbiterr => '0',
axi_r_overflow => NLW_U0_axi_r_overflow_UNCONNECTED,
axi_r_prog_empty => NLW_U0_axi_r_prog_empty_UNCONNECTED,
axi_r_prog_empty_thresh(9) => '0',
axi_r_prog_empty_thresh(8) => '0',
axi_r_prog_empty_thresh(7) => '0',
axi_r_prog_empty_thresh(6) => '0',
axi_r_prog_empty_thresh(5) => '0',
axi_r_prog_empty_thresh(4) => '0',
axi_r_prog_empty_thresh(3) => '0',
axi_r_prog_empty_thresh(2) => '0',
axi_r_prog_empty_thresh(1) => '0',
axi_r_prog_empty_thresh(0) => '0',
axi_r_prog_full => NLW_U0_axi_r_prog_full_UNCONNECTED,
axi_r_prog_full_thresh(9) => '0',
axi_r_prog_full_thresh(8) => '0',
axi_r_prog_full_thresh(7) => '0',
axi_r_prog_full_thresh(6) => '0',
axi_r_prog_full_thresh(5) => '0',
axi_r_prog_full_thresh(4) => '0',
axi_r_prog_full_thresh(3) => '0',
axi_r_prog_full_thresh(2) => '0',
axi_r_prog_full_thresh(1) => '0',
axi_r_prog_full_thresh(0) => '0',
axi_r_rd_data_count(10 downto 0) => NLW_U0_axi_r_rd_data_count_UNCONNECTED(10 downto 0),
axi_r_sbiterr => NLW_U0_axi_r_sbiterr_UNCONNECTED,
axi_r_underflow => NLW_U0_axi_r_underflow_UNCONNECTED,
axi_r_wr_data_count(10 downto 0) => NLW_U0_axi_r_wr_data_count_UNCONNECTED(10 downto 0),
axi_w_data_count(10 downto 0) => NLW_U0_axi_w_data_count_UNCONNECTED(10 downto 0),
axi_w_dbiterr => NLW_U0_axi_w_dbiterr_UNCONNECTED,
axi_w_injectdbiterr => '0',
axi_w_injectsbiterr => '0',
axi_w_overflow => NLW_U0_axi_w_overflow_UNCONNECTED,
axi_w_prog_empty => NLW_U0_axi_w_prog_empty_UNCONNECTED,
axi_w_prog_empty_thresh(9) => '0',
axi_w_prog_empty_thresh(8) => '0',
axi_w_prog_empty_thresh(7) => '0',
axi_w_prog_empty_thresh(6) => '0',
axi_w_prog_empty_thresh(5) => '0',
axi_w_prog_empty_thresh(4) => '0',
axi_w_prog_empty_thresh(3) => '0',
axi_w_prog_empty_thresh(2) => '0',
axi_w_prog_empty_thresh(1) => '0',
axi_w_prog_empty_thresh(0) => '0',
axi_w_prog_full => NLW_U0_axi_w_prog_full_UNCONNECTED,
axi_w_prog_full_thresh(9) => '0',
axi_w_prog_full_thresh(8) => '0',
axi_w_prog_full_thresh(7) => '0',
axi_w_prog_full_thresh(6) => '0',
axi_w_prog_full_thresh(5) => '0',
axi_w_prog_full_thresh(4) => '0',
axi_w_prog_full_thresh(3) => '0',
axi_w_prog_full_thresh(2) => '0',
axi_w_prog_full_thresh(1) => '0',
axi_w_prog_full_thresh(0) => '0',
axi_w_rd_data_count(10 downto 0) => NLW_U0_axi_w_rd_data_count_UNCONNECTED(10 downto 0),
axi_w_sbiterr => NLW_U0_axi_w_sbiterr_UNCONNECTED,
axi_w_underflow => NLW_U0_axi_w_underflow_UNCONNECTED,
axi_w_wr_data_count(10 downto 0) => NLW_U0_axi_w_wr_data_count_UNCONNECTED(10 downto 0),
axis_data_count(10 downto 0) => NLW_U0_axis_data_count_UNCONNECTED(10 downto 0),
axis_dbiterr => NLW_U0_axis_dbiterr_UNCONNECTED,
axis_injectdbiterr => '0',
axis_injectsbiterr => '0',
axis_overflow => NLW_U0_axis_overflow_UNCONNECTED,
axis_prog_empty => NLW_U0_axis_prog_empty_UNCONNECTED,
axis_prog_empty_thresh(9) => '0',
axis_prog_empty_thresh(8) => '0',
axis_prog_empty_thresh(7) => '0',
axis_prog_empty_thresh(6) => '0',
axis_prog_empty_thresh(5) => '0',
axis_prog_empty_thresh(4) => '0',
axis_prog_empty_thresh(3) => '0',
axis_prog_empty_thresh(2) => '0',
axis_prog_empty_thresh(1) => '0',
axis_prog_empty_thresh(0) => '0',
axis_prog_full => NLW_U0_axis_prog_full_UNCONNECTED,
axis_prog_full_thresh(9) => '0',
axis_prog_full_thresh(8) => '0',
axis_prog_full_thresh(7) => '0',
axis_prog_full_thresh(6) => '0',
axis_prog_full_thresh(5) => '0',
axis_prog_full_thresh(4) => '0',
axis_prog_full_thresh(3) => '0',
axis_prog_full_thresh(2) => '0',
axis_prog_full_thresh(1) => '0',
axis_prog_full_thresh(0) => '0',
axis_rd_data_count(10 downto 0) => NLW_U0_axis_rd_data_count_UNCONNECTED(10 downto 0),
axis_sbiterr => NLW_U0_axis_sbiterr_UNCONNECTED,
axis_underflow => NLW_U0_axis_underflow_UNCONNECTED,
axis_wr_data_count(10 downto 0) => NLW_U0_axis_wr_data_count_UNCONNECTED(10 downto 0),
backup => '0',
backup_marker => '0',
clk => '0',
data_count(4 downto 0) => NLW_U0_data_count_UNCONNECTED(4 downto 0),
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
din(102 downto 0) => din(102 downto 0),
dout(102 downto 0) => dout(102 downto 0),
empty => empty,
full => full,
injectdbiterr => '0',
injectsbiterr => '0',
int_clk => '0',
m_aclk => '0',
m_aclk_en => '0',
m_axi_araddr(31 downto 0) => NLW_U0_m_axi_araddr_UNCONNECTED(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_U0_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_U0_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(0) => NLW_U0_m_axi_arid_UNCONNECTED(0),
m_axi_arlen(7 downto 0) => NLW_U0_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_U0_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => NLW_U0_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_U0_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => '0',
m_axi_arregion(3 downto 0) => NLW_U0_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_U0_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_U0_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => NLW_U0_m_axi_arvalid_UNCONNECTED,
m_axi_awaddr(31 downto 0) => NLW_U0_m_axi_awaddr_UNCONNECTED(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_U0_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_U0_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(0) => NLW_U0_m_axi_awid_UNCONNECTED(0),
m_axi_awlen(7 downto 0) => NLW_U0_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_U0_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => NLW_U0_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_U0_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => '0',
m_axi_awregion(3 downto 0) => NLW_U0_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_U0_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_U0_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => NLW_U0_m_axi_awvalid_UNCONNECTED,
m_axi_bid(0) => '0',
m_axi_bready => NLW_U0_m_axi_bready_UNCONNECTED,
m_axi_bresp(1) => '0',
m_axi_bresp(0) => '0',
m_axi_buser(0) => '0',
m_axi_bvalid => '0',
m_axi_rdata(63) => '0',
m_axi_rdata(62) => '0',
m_axi_rdata(61) => '0',
m_axi_rdata(60) => '0',
m_axi_rdata(59) => '0',
m_axi_rdata(58) => '0',
m_axi_rdata(57) => '0',
m_axi_rdata(56) => '0',
m_axi_rdata(55) => '0',
m_axi_rdata(54) => '0',
m_axi_rdata(53) => '0',
m_axi_rdata(52) => '0',
m_axi_rdata(51) => '0',
m_axi_rdata(50) => '0',
m_axi_rdata(49) => '0',
m_axi_rdata(48) => '0',
m_axi_rdata(47) => '0',
m_axi_rdata(46) => '0',
m_axi_rdata(45) => '0',
m_axi_rdata(44) => '0',
m_axi_rdata(43) => '0',
m_axi_rdata(42) => '0',
m_axi_rdata(41) => '0',
m_axi_rdata(40) => '0',
m_axi_rdata(39) => '0',
m_axi_rdata(38) => '0',
m_axi_rdata(37) => '0',
m_axi_rdata(36) => '0',
m_axi_rdata(35) => '0',
m_axi_rdata(34) => '0',
m_axi_rdata(33) => '0',
m_axi_rdata(32) => '0',
m_axi_rdata(31) => '0',
m_axi_rdata(30) => '0',
m_axi_rdata(29) => '0',
m_axi_rdata(28) => '0',
m_axi_rdata(27) => '0',
m_axi_rdata(26) => '0',
m_axi_rdata(25) => '0',
m_axi_rdata(24) => '0',
m_axi_rdata(23) => '0',
m_axi_rdata(22) => '0',
m_axi_rdata(21) => '0',
m_axi_rdata(20) => '0',
m_axi_rdata(19) => '0',
m_axi_rdata(18) => '0',
m_axi_rdata(17) => '0',
m_axi_rdata(16) => '0',
m_axi_rdata(15) => '0',
m_axi_rdata(14) => '0',
m_axi_rdata(13) => '0',
m_axi_rdata(12) => '0',
m_axi_rdata(11) => '0',
m_axi_rdata(10) => '0',
m_axi_rdata(9) => '0',
m_axi_rdata(8) => '0',
m_axi_rdata(7) => '0',
m_axi_rdata(6) => '0',
m_axi_rdata(5) => '0',
m_axi_rdata(4) => '0',
m_axi_rdata(3) => '0',
m_axi_rdata(2) => '0',
m_axi_rdata(1) => '0',
m_axi_rdata(0) => '0',
m_axi_rid(0) => '0',
m_axi_rlast => '0',
m_axi_rready => NLW_U0_m_axi_rready_UNCONNECTED,
m_axi_rresp(1) => '0',
m_axi_rresp(0) => '0',
m_axi_ruser(0) => '0',
m_axi_rvalid => '0',
m_axi_wdata(63 downto 0) => NLW_U0_m_axi_wdata_UNCONNECTED(63 downto 0),
m_axi_wid(0) => NLW_U0_m_axi_wid_UNCONNECTED(0),
m_axi_wlast => NLW_U0_m_axi_wlast_UNCONNECTED,
m_axi_wready => '0',
m_axi_wstrb(7 downto 0) => NLW_U0_m_axi_wstrb_UNCONNECTED(7 downto 0),
m_axi_wuser(0) => NLW_U0_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => NLW_U0_m_axi_wvalid_UNCONNECTED,
m_axis_tdata(7 downto 0) => NLW_U0_m_axis_tdata_UNCONNECTED(7 downto 0),
m_axis_tdest(0) => NLW_U0_m_axis_tdest_UNCONNECTED(0),
m_axis_tid(0) => NLW_U0_m_axis_tid_UNCONNECTED(0),
m_axis_tkeep(0) => NLW_U0_m_axis_tkeep_UNCONNECTED(0),
m_axis_tlast => NLW_U0_m_axis_tlast_UNCONNECTED,
m_axis_tready => '0',
m_axis_tstrb(0) => NLW_U0_m_axis_tstrb_UNCONNECTED(0),
m_axis_tuser(3 downto 0) => NLW_U0_m_axis_tuser_UNCONNECTED(3 downto 0),
m_axis_tvalid => NLW_U0_m_axis_tvalid_UNCONNECTED,
overflow => NLW_U0_overflow_UNCONNECTED,
prog_empty => NLW_U0_prog_empty_UNCONNECTED,
prog_empty_thresh(4) => '0',
prog_empty_thresh(3) => '0',
prog_empty_thresh(2) => '0',
prog_empty_thresh(1) => '0',
prog_empty_thresh(0) => '0',
prog_empty_thresh_assert(4) => '0',
prog_empty_thresh_assert(3) => '0',
prog_empty_thresh_assert(2) => '0',
prog_empty_thresh_assert(1) => '0',
prog_empty_thresh_assert(0) => '0',
prog_empty_thresh_negate(4) => '0',
prog_empty_thresh_negate(3) => '0',
prog_empty_thresh_negate(2) => '0',
prog_empty_thresh_negate(1) => '0',
prog_empty_thresh_negate(0) => '0',
prog_full => prog_full,
prog_full_thresh(4) => '0',
prog_full_thresh(3) => '0',
prog_full_thresh(2) => '0',
prog_full_thresh(1) => '0',
prog_full_thresh(0) => '0',
prog_full_thresh_assert(4) => '0',
prog_full_thresh_assert(3) => '0',
prog_full_thresh_assert(2) => '0',
prog_full_thresh_assert(1) => '0',
prog_full_thresh_assert(0) => '0',
prog_full_thresh_negate(4) => '0',
prog_full_thresh_negate(3) => '0',
prog_full_thresh_negate(2) => '0',
prog_full_thresh_negate(1) => '0',
prog_full_thresh_negate(0) => '0',
rd_clk => rd_clk,
rd_data_count(4 downto 0) => NLW_U0_rd_data_count_UNCONNECTED(4 downto 0),
rd_en => rd_en,
rd_rst => '0',
rd_rst_busy => NLW_U0_rd_rst_busy_UNCONNECTED,
rst => rst,
s_aclk => '0',
s_aclk_en => '0',
s_aresetn => '0',
s_axi_araddr(31) => '0',
s_axi_araddr(30) => '0',
s_axi_araddr(29) => '0',
s_axi_araddr(28) => '0',
s_axi_araddr(27) => '0',
s_axi_araddr(26) => '0',
s_axi_araddr(25) => '0',
s_axi_araddr(24) => '0',
s_axi_araddr(23) => '0',
s_axi_araddr(22) => '0',
s_axi_araddr(21) => '0',
s_axi_araddr(20) => '0',
s_axi_araddr(19) => '0',
s_axi_araddr(18) => '0',
s_axi_araddr(17) => '0',
s_axi_araddr(16) => '0',
s_axi_araddr(15) => '0',
s_axi_araddr(14) => '0',
s_axi_araddr(13) => '0',
s_axi_araddr(12) => '0',
s_axi_araddr(11) => '0',
s_axi_araddr(10) => '0',
s_axi_araddr(9) => '0',
s_axi_araddr(8) => '0',
s_axi_araddr(7) => '0',
s_axi_araddr(6) => '0',
s_axi_araddr(5) => '0',
s_axi_araddr(4) => '0',
s_axi_araddr(3) => '0',
s_axi_araddr(2) => '0',
s_axi_araddr(1) => '0',
s_axi_araddr(0) => '0',
s_axi_arburst(1) => '0',
s_axi_arburst(0) => '0',
s_axi_arcache(3) => '0',
s_axi_arcache(2) => '0',
s_axi_arcache(1) => '0',
s_axi_arcache(0) => '0',
s_axi_arid(0) => '0',
s_axi_arlen(7) => '0',
s_axi_arlen(6) => '0',
s_axi_arlen(5) => '0',
s_axi_arlen(4) => '0',
s_axi_arlen(3) => '0',
s_axi_arlen(2) => '0',
s_axi_arlen(1) => '0',
s_axi_arlen(0) => '0',
s_axi_arlock(0) => '0',
s_axi_arprot(2) => '0',
s_axi_arprot(1) => '0',
s_axi_arprot(0) => '0',
s_axi_arqos(3) => '0',
s_axi_arqos(2) => '0',
s_axi_arqos(1) => '0',
s_axi_arqos(0) => '0',
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arregion(3) => '0',
s_axi_arregion(2) => '0',
s_axi_arregion(1) => '0',
s_axi_arregion(0) => '0',
s_axi_arsize(2) => '0',
s_axi_arsize(1) => '0',
s_axi_arsize(0) => '0',
s_axi_aruser(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31) => '0',
s_axi_awaddr(30) => '0',
s_axi_awaddr(29) => '0',
s_axi_awaddr(28) => '0',
s_axi_awaddr(27) => '0',
s_axi_awaddr(26) => '0',
s_axi_awaddr(25) => '0',
s_axi_awaddr(24) => '0',
s_axi_awaddr(23) => '0',
s_axi_awaddr(22) => '0',
s_axi_awaddr(21) => '0',
s_axi_awaddr(20) => '0',
s_axi_awaddr(19) => '0',
s_axi_awaddr(18) => '0',
s_axi_awaddr(17) => '0',
s_axi_awaddr(16) => '0',
s_axi_awaddr(15) => '0',
s_axi_awaddr(14) => '0',
s_axi_awaddr(13) => '0',
s_axi_awaddr(12) => '0',
s_axi_awaddr(11) => '0',
s_axi_awaddr(10) => '0',
s_axi_awaddr(9) => '0',
s_axi_awaddr(8) => '0',
s_axi_awaddr(7) => '0',
s_axi_awaddr(6) => '0',
s_axi_awaddr(5) => '0',
s_axi_awaddr(4) => '0',
s_axi_awaddr(3) => '0',
s_axi_awaddr(2) => '0',
s_axi_awaddr(1) => '0',
s_axi_awaddr(0) => '0',
s_axi_awburst(1) => '0',
s_axi_awburst(0) => '0',
s_axi_awcache(3) => '0',
s_axi_awcache(2) => '0',
s_axi_awcache(1) => '0',
s_axi_awcache(0) => '0',
s_axi_awid(0) => '0',
s_axi_awlen(7) => '0',
s_axi_awlen(6) => '0',
s_axi_awlen(5) => '0',
s_axi_awlen(4) => '0',
s_axi_awlen(3) => '0',
s_axi_awlen(2) => '0',
s_axi_awlen(1) => '0',
s_axi_awlen(0) => '0',
s_axi_awlock(0) => '0',
s_axi_awprot(2) => '0',
s_axi_awprot(1) => '0',
s_axi_awprot(0) => '0',
s_axi_awqos(3) => '0',
s_axi_awqos(2) => '0',
s_axi_awqos(1) => '0',
s_axi_awqos(0) => '0',
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awregion(3) => '0',
s_axi_awregion(2) => '0',
s_axi_awregion(1) => '0',
s_axi_awregion(0) => '0',
s_axi_awsize(2) => '0',
s_axi_awsize(1) => '0',
s_axi_awsize(0) => '0',
s_axi_awuser(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(0) => NLW_U0_s_axi_bid_UNCONNECTED(0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_buser(0) => NLW_U0_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
s_axi_rid(0) => NLW_U0_s_axi_rid_UNCONNECTED(0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_ruser(0) => NLW_U0_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_wdata(63) => '0',
s_axi_wdata(62) => '0',
s_axi_wdata(61) => '0',
s_axi_wdata(60) => '0',
s_axi_wdata(59) => '0',
s_axi_wdata(58) => '0',
s_axi_wdata(57) => '0',
s_axi_wdata(56) => '0',
s_axi_wdata(55) => '0',
s_axi_wdata(54) => '0',
s_axi_wdata(53) => '0',
s_axi_wdata(52) => '0',
s_axi_wdata(51) => '0',
s_axi_wdata(50) => '0',
s_axi_wdata(49) => '0',
s_axi_wdata(48) => '0',
s_axi_wdata(47) => '0',
s_axi_wdata(46) => '0',
s_axi_wdata(45) => '0',
s_axi_wdata(44) => '0',
s_axi_wdata(43) => '0',
s_axi_wdata(42) => '0',
s_axi_wdata(41) => '0',
s_axi_wdata(40) => '0',
s_axi_wdata(39) => '0',
s_axi_wdata(38) => '0',
s_axi_wdata(37) => '0',
s_axi_wdata(36) => '0',
s_axi_wdata(35) => '0',
s_axi_wdata(34) => '0',
s_axi_wdata(33) => '0',
s_axi_wdata(32) => '0',
s_axi_wdata(31) => '0',
s_axi_wdata(30) => '0',
s_axi_wdata(29) => '0',
s_axi_wdata(28) => '0',
s_axi_wdata(27) => '0',
s_axi_wdata(26) => '0',
s_axi_wdata(25) => '0',
s_axi_wdata(24) => '0',
s_axi_wdata(23) => '0',
s_axi_wdata(22) => '0',
s_axi_wdata(21) => '0',
s_axi_wdata(20) => '0',
s_axi_wdata(19) => '0',
s_axi_wdata(18) => '0',
s_axi_wdata(17) => '0',
s_axi_wdata(16) => '0',
s_axi_wdata(15) => '0',
s_axi_wdata(14) => '0',
s_axi_wdata(13) => '0',
s_axi_wdata(12) => '0',
s_axi_wdata(11) => '0',
s_axi_wdata(10) => '0',
s_axi_wdata(9) => '0',
s_axi_wdata(8) => '0',
s_axi_wdata(7) => '0',
s_axi_wdata(6) => '0',
s_axi_wdata(5) => '0',
s_axi_wdata(4) => '0',
s_axi_wdata(3) => '0',
s_axi_wdata(2) => '0',
s_axi_wdata(1) => '0',
s_axi_wdata(0) => '0',
s_axi_wid(0) => '0',
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(7) => '0',
s_axi_wstrb(6) => '0',
s_axi_wstrb(5) => '0',
s_axi_wstrb(4) => '0',
s_axi_wstrb(3) => '0',
s_axi_wstrb(2) => '0',
s_axi_wstrb(1) => '0',
s_axi_wstrb(0) => '0',
s_axi_wuser(0) => '0',
s_axi_wvalid => '0',
s_axis_tdata(7) => '0',
s_axis_tdata(6) => '0',
s_axis_tdata(5) => '0',
s_axis_tdata(4) => '0',
s_axis_tdata(3) => '0',
s_axis_tdata(2) => '0',
s_axis_tdata(1) => '0',
s_axis_tdata(0) => '0',
s_axis_tdest(0) => '0',
s_axis_tid(0) => '0',
s_axis_tkeep(0) => '0',
s_axis_tlast => '0',
s_axis_tready => NLW_U0_s_axis_tready_UNCONNECTED,
s_axis_tstrb(0) => '0',
s_axis_tuser(3) => '0',
s_axis_tuser(2) => '0',
s_axis_tuser(1) => '0',
s_axis_tuser(0) => '0',
s_axis_tvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
sleep => '0',
srst => '0',
underflow => NLW_U0_underflow_UNCONNECTED,
valid => NLW_U0_valid_UNCONNECTED,
wr_ack => NLW_U0_wr_ack_UNCONNECTED,
wr_clk => wr_clk,
wr_data_count(4 downto 0) => NLW_U0_wr_data_count_UNCONNECTED(4 downto 0),
wr_en => wr_en,
wr_rst => '0',
wr_rst_busy => NLW_U0_wr_rst_busy_UNCONNECTED
);
end STRUCTURE;
| gpl-3.0 | f4b6350bbaadd13ff4a45db71765ee51 | 0.571871 | 2.749735 | false | false | false | false |
JuanMarcosRamirez/WeightedMedianDisenoLogico | misc/FPGA/rc_counter.vhd | 3 | 1,352 | --------------------------------------------------------------------------
-- Autor original: Antony Nelson.
-- Modificaciones de esta versión: Jorge Márquez
--
-- Esta rutina contiene las modificaciones indicadas en la sección de
-- Anexos del informe de trabajo de grado PROCESAMIENTO DE IMÁGENES DE
-- ANGIOGRAFÍA BIPLANA USANDO UNA TARJETA DE DESARROLLO SPARTAN-3E
--
-- UNIVERSIDAD DE LOS ANDES
-- FACULTAD DE INGENIERÍA
-- ESCUELA DE INGENIERÍA ELÉCTRICA
--
-- Mérida, Septiembre, 2008
--
------------------------------------------- --------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity rc_counter is
generic (
num_cols: integer:=512;
num_rows: integer:=512
);
port (
Clk : in std_logic;
RSTn : in std_logic;
En : in std_logic;
ColPos : out integer;
RowPos : out integer
);
end rc_counter;
architecture rc_counter of rc_counter is
begin
process(RSTn,Clk,En)
variable ColPos_var: integer:=0;
variable RowPos_var: integer:=0;
begin
if RSTn = '0' then
ColPos_var := -1;
ColPos <= 0;
RowPos_var := 0;
RowPos <= 0;
elsif rising_edge(Clk) then
if En = '1' then
ColPos_var := ColPos_var +1;
if ColPos_var = num_cols then
RowPos_var := RowPos_var +1;
ColPos_var := 0;
if RowPos_var = num_rows then
RowPos_var := 0;
end if;
end if;
ColPos <= ColPos_var;
RowPos <= RowPos_var;
end if;
end if;
end process;
end rc_counter;
| gpl-3.0 | f230207b0d329f7854079aa726ae8213 | 0.636095 | 2.888889 | false | false | false | false |
Monash-2015-Ultrasonic/Logs | Final System Code/SYSTEMV3/Source/IP/FIR/FIR_sim/auk_dspip_avalon_streaming_sink_hpfir.vhd | 2 | 21,225 | -- (C) 2001-2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-------------------------------------------------------------------------
-------------------------------------------------------------------------
--
-- Revision Control Information
--
-- $Revision: #1 $
-- $Date: 2009/07/29 $
-- Author : Boon Hong Oh
--
-- Project : Atlantic II Sink Interface with ready_latency=0
--
-- Description :
--
-- This interface is capable of handling single or multi channel streams as
-- well as blocks of data. The at_sink_sop and at_sink_eop must be fed as
-- described in the Atlantic II specification. The at_sink_error input is a 2-
-- bit signal that complies with the PFC error format (by Kent Orthner). The
-- error checking is extensively done, however the resulting information is
-- still mapped on the available 3 error states as shown below.
-- 00: no error
-- 01: missing sop
-- 10: missing eop
-- 11: unexpected eop
-- other types of errors also marked as 11.
--
-- ALTERA Confidential and Proprietary
-- Copyright 2006 (c) Altera Corporation
-- All rights reserved
--
-------------------------------------------------------------------------
-------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use work.auk_dspip_lib_pkg_hpfir.all;
use work.auk_dspip_math_pkg_hpfir.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
entity auk_dspip_avalon_streaming_sink_hpfir is
generic(
WIDTH_g : integer := 24; -- DATA_PORT_COUNT * DATA_WIDTH
DATA_WIDTH : integer := 8;
DATA_PORT_COUNT : integer := 3;
PACKET_SIZE_g : natural := 2
--FIFO_DEPTH_g : natural := 8 --if PFC mode is selected, this generic
--is used for passing the poly_factor.
--MIN_DATA_COUNT_g : natural := 2;
--PFC_MODE_g : boolean := false;
--SOP_EOP_CALC_g : boolean := false; -- calculate sop and eop rather than
-- reading value from fifo
--FAMILY_g : string := "Stratix II";
--MEM_TYPE_g : string := "Auto"
);
port(
clk : in std_logic;
reset_n : in std_logic;
----------------- DESIGN SIDE SIGNALS
data : out std_logic_vector(WIDTH_g-1 downto 0);
data_valid : out std_logic_vector(0 downto 0);
sink_ready_ctrl : in std_logic; --the controller will tell
--the interface whether
--new input can be accepted.
--sink_stall : out std_logic; --needs to stall the design
--if no new data is coming
packet_error : out std_logic_vector (1 downto 0); --this is for SOP and EOP check only.
--when any of these doesn't behave as
--expected, the error is flagged.
--send_sop : out std_logic; -- transmit SOP signal to the design.
-- It only transmits the legal SOP.
--send_eop : out std_logic; -- transmit EOP signal to the design.
-- It only transmits the legal EOP.
----------------- ATLANTIC SIDE SIGNALS
at_sink_ready : out std_logic; --it will be '1' whenever the
--sink_ready_ctrl signal is high.
at_sink_valid : in std_logic;
at_sink_data : in std_logic_vector(WIDTH_g-1 downto 0);
at_sink_sop : in std_logic := '0';
at_sink_eop : in std_logic := '0';
at_sink_error : in std_logic_vector(1 downto 0) := "00" --it indicates
--that there is an error in the packet.
);
end auk_dspip_avalon_streaming_sink_hpfir;
-- hds interface_end
architecture rtl of auk_dspip_avalon_streaming_sink_hpfir is
type STATE_TYPE_t is (start, stall, run1, st_err, end1); -- stall,run_once,wait1,
type OUT_STATE_TYPE_t is (normal, empty_and_not_ready, empty_and_ready);
constant LOG2PACKET_SIZE_c : natural := log2_ceil_one(PACKET_SIZE_g);
signal sink_state : STATE_TYPE_t;
signal sink_next_state : STATE_TYPE_t;
signal reset_count : std_logic;
signal count_enable : std_logic;
signal count : unsigned(LOG2PACKET_SIZE_c -1 downto 0);
signal count_finished : boolean;
signal at_sink_error_int : std_logic;
signal packet_error_int : std_logic_vector (1 downto 0);
signal packet_error_s : std_logic_vector(1 downto 0);
signal at_sink_ready_s : std_logic;
--signal reset : std_logic;
signal max_reached : boolean; -- flag to show counter has reached max value
-- component altera_avalon_sc_fifo is
-- generic(
-- SYMBOLS_PER_BEAT : integer := 1;
-- BITS_PER_SYMBOL : integer := 8;
-- FIFO_DEPTH : integer := 16;
-- CHANNEL_WIDTH : integer := 0;
-- ERROR_WIDTH : integer := 0;
-- USE_PACKETS : integer := 0
-- );
-- port (
-- -- inputs:
-- signal clk : IN STD_LOGIC;
-- signal in_data : IN STD_LOGIC_VECTOR (DATA_WIDTH*DATA_PORT_COUNT-1 DOWNTO 0);
-- signal in_valid : IN STD_LOGIC;
-- signal in_startofpacket : IN STD_LOGIC;
-- signal in_endofpacket : IN STD_LOGIC;
-- signal out_ready : IN STD_LOGIC;
-- signal reset : IN STD_LOGIC;
--
-- signal in_empty : IN STD_LOGIC_VECTOR (log2_ceil_one(DATA_PORT_COUNT)-1 DOWNTO 0);
-- signal in_error : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
-- signal in_channel : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
--
-- signal csr_address : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
-- signal csr_write : IN STD_LOGIC;
-- signal csr_read : IN STD_LOGIC;
-- signal csr_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
--
-- -- outputs:
-- signal in_ready : OUT STD_LOGIC;
-- signal out_data : OUT STD_LOGIC_VECTOR (DATA_WIDTH*DATA_PORT_COUNT-1 DOWNTO 0);
-- signal out_valid : OUT STD_LOGIC;
--
-- signal out_empty : OUT STD_LOGIC_VECTOR (log2_ceil_one(DATA_PORT_COUNT)-1 DOWNTO 0);
-- signal out_error : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
-- signal out_channel : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
-- );
-- end component altera_avalon_sc_fifo;
begin
valid_generate_single : if PACKET_SIZE_g = 1 generate
signal packet_error0 : std_logic;
begin
at_sink_error_int <= at_sink_error(0) when at_sink_valid = '1' else
'0';
packet_error_int <= '0' & packet_error0;
packet_error0 <= '0' when at_sink_error_int = '0' and sink_next_state /= st_err else
'1';
sink_comb_update_1 : process (sink_state, at_sink_valid, at_sink_error_int, at_sink_ready_s)
begin -- process sink_comb_update_1
case sink_state is
when start =>
--fifo_wrreq <= '0';
if at_sink_error_int = '1' then
sink_next_state <= st_err;
else
if at_sink_ready_s = '0' and at_sink_valid = '0' then
sink_next_state <= start;
elsif at_sink_ready_s = '0' and at_sink_valid = '1' then
sink_next_state <= start;
elsif at_sink_ready_s = '1' and at_sink_valid = '0' then
sink_next_state <= stall;
elsif at_sink_ready_s = '1' and at_sink_valid = '1' then
sink_next_state <= run1;
else
sink_next_state <= st_err;
end if;
end if;
when stall =>
--fifo_wrreq <= '0';
if at_sink_error_int = '1' then
sink_next_state <= st_err;
else
if at_sink_ready_s = '0' and at_sink_valid = '0' then
sink_next_state <= start;
elsif at_sink_ready_s = '0' and at_sink_valid = '1' then
sink_next_state <= start;
elsif at_sink_ready_s = '1' and at_sink_valid = '0' then
sink_next_state <= stall;
elsif at_sink_ready_s = '1' and at_sink_valid = '1' then
sink_next_state <= run1;
else
sink_next_state <= st_err;
end if;
end if;
when run1 =>
--fifo_wrreq <= '1';
if at_sink_error_int = '1' then
sink_next_state <= st_err;
else
if at_sink_ready_s = '0' and at_sink_valid = '0' then
sink_next_state <= start;
elsif at_sink_ready_s = '0' and at_sink_valid = '1' then
sink_next_state <= start;
elsif at_sink_ready_s = '1' and at_sink_valid = '0' then
sink_next_state <= stall;
elsif at_sink_ready_s = '1' and at_sink_valid = '1' then
sink_next_state <= run1;
else
sink_next_state <= st_err;
end if;
end if;
when st_err =>
--fifo_wrreq <= '0';
if at_sink_error_int = '1' then
sink_next_state <= st_err;
else
if at_sink_ready_s = '0' and at_sink_valid = '0' then
sink_next_state <= start;
elsif at_sink_ready_s = '0' and at_sink_valid = '1' then
sink_next_state <= start;
elsif at_sink_ready_s = '1' and at_sink_valid = '0' then
sink_next_state <= stall;
elsif at_sink_ready_s = '1' and at_sink_valid = '1' then
sink_next_state <= run1;
else
sink_next_state <= st_err;
end if;
end if;
when others =>
sink_next_state <= st_err;
--fifo_wrreq <= '0';
end case;
end process sink_comb_update_1;
end generate valid_generate_single;
valid_generate_mult : if PACKET_SIZE_g > 1 generate
at_sink_error_int <= at_sink_error(1) or at_sink_error(0) when at_sink_valid = '1' else
'0';
count_enable <= '1' when (sink_next_state = run1 or sink_next_state = end1) else --
--or sink_next_state = run_once) else
'0';
reset_count <= '1' when sink_next_state = st_err else
'0';
sink_comb_update_2 : process (sink_state, at_sink_ready_s, at_sink_valid,
at_sink_error, at_sink_error_int, at_sink_sop,
at_sink_eop, count, count_finished)
begin -- process sink_comb_update_2
case sink_state is
when start =>
--fifo_wrreq <= '0';
if at_sink_error_int = '1' then
sink_next_state <= st_err;
packet_error_int <= at_sink_error;
else
if at_sink_ready_s = '1' and at_sink_valid = '1' and at_sink_sop = '1' then
sink_next_state <= run1;
packet_error_int <= "00";
elsif (at_sink_ready_s = '1' and at_sink_valid = '1' and at_sink_sop = '0') then
sink_next_state <= st_err;
packet_error_int <= "01";
else
sink_next_state <= start;
packet_error_int <= "00";
end if;
end if;
when run1 =>
--fifo_wrreq <= '1';
if at_sink_error_int = '1' then
sink_next_state <= st_err;
packet_error_int <= at_sink_error;
elsif at_sink_sop = '1' and at_sink_valid = '1' then
sink_next_state <= st_err;
packet_error_int <= "01";
elsif (count_finished = false and at_sink_eop = '1' and at_sink_valid = '1') then
sink_next_state <= st_err;
packet_error_int <= "11";
else
if at_sink_eop = '0' and count_finished = false and at_sink_valid = '1' and at_sink_ready_s = '1' then
sink_next_state <= run1;
packet_error_int <= "00";
elsif at_sink_eop = '1' and count_finished = true and at_sink_valid = '1' and at_sink_ready_s = '1' then
sink_next_state <= end1;
packet_error_int <= "00";
elsif (count_finished = true and at_sink_valid = '0' and at_sink_ready_s = '1') or
(at_sink_valid = '0' and at_sink_ready_s = '1') then
sink_next_state <= stall;
packet_error_int <= "00";
elsif (count_finished = true and at_sink_ready_s = '0') or (at_sink_eop = '0' and at_sink_ready_s = '0') then
sink_next_state <= stall; --wait1;
packet_error_int <= "00";
elsif (count_finished = true and at_sink_eop = '0' and at_sink_valid = '1' and at_sink_ready_s = '1') then
sink_next_state <= st_err;
packet_error_int <= "10";
else
sink_next_state <= st_err;
packet_error_int <= "11";
end if;
end if;
when stall =>
--fifo_wrreq <= '0';
if at_sink_error_int = '1' then
sink_next_state <= st_err;
packet_error_int <= at_sink_error;
elsif at_sink_sop = '1' and at_sink_valid = '1' then
sink_next_state <= st_err;
packet_error_int <= "01";
elsif (count_finished = false and at_sink_eop = '1' and at_sink_valid = '1') then
sink_next_state <= st_err;
packet_error_int <= "11";
else
if at_sink_eop = '0' and count_finished = false and at_sink_valid = '1' and at_sink_ready_s = '1' then --and at_sink_ready_int = '1' then
sink_next_state <= run1;
packet_error_int <= "00";
elsif at_sink_eop = '1' and count_finished = true and at_sink_valid = '1' and at_sink_ready_s = '1' then
sink_next_state <= end1;
packet_error_int <= "00";
elsif (count_finished = true and at_sink_valid = '0') or -- and at_sink_ready_s = '1') or
(at_sink_valid = '0' and at_sink_ready_s = '1') then
sink_next_state <= stall;
packet_error_int <= "00";
elsif (count_finished = true and at_sink_ready_s = '0') or (at_sink_eop = '0' and at_sink_ready_s = '0') then
sink_next_state <= stall; --wait1;
packet_error_int <= "00";
elsif (count_finished = true and at_sink_eop = '0' and at_sink_valid = '1' and at_sink_ready_s = '1') then
sink_next_state <= st_err;
packet_error_int <= "10";
else
sink_next_state <= st_err;
packet_error_int <= "11";
end if;
end if;
when end1 =>
--fifo_wrreq <= '1';
if at_sink_error_int = '1' then
sink_next_state <= st_err;
packet_error_int <= at_sink_error;
else
if at_sink_ready_s = '1' and at_sink_valid = '1' and at_sink_sop = '1' then
sink_next_state <= run1;
packet_error_int <= "00";
elsif (at_sink_valid = '1' and at_sink_sop = '0') then
sink_next_state <= st_err;
packet_error_int <= "01";
else
sink_next_state <= start;
packet_error_int <= "00";
end if;
end if;
when st_err =>
--fifo_wrreq <= '0';
if at_sink_error_int = '1' then
sink_next_state <= st_err;
packet_error_int <= at_sink_error;
else
if at_sink_ready_s = '1' and at_sink_valid = '1' and at_sink_sop = '1' then
sink_next_state <= run1;
packet_error_int <= "00";
elsif (at_sink_ready_s = '1' and at_sink_valid = '1' and at_sink_sop = '0') then
sink_next_state <= st_err;
packet_error_int <= "01";
else
sink_next_state <= start;
packet_error_int <= "00";
end if;
end if;
when others => null;
end case;
end process sink_comb_update_2;
counter : process (clk, reset_n)
begin -- process counter
if reset_n = '0' then
count <= (others => '0');
max_reached <= false;
elsif clk'event and clk = '1' then -- rising clock edge
if reset_count = '1' then
count <= (others => '0');
else
if count_enable = '1' then
if count = PACKET_SIZE_g-2 then
max_reached <= true;
else
max_reached <= false;
end if;
if max_reached = false then
count <= count + 1;
else
count <= (others => '0');
end if;
end if;
end if;
end if;
end process counter;
count_finished <= max_reached;
end generate valid_generate_mult;
sink_input_update : process (clk, reset_n)
begin -- process
if reset_n = '0' then
sink_state <= start;
elsif clk'event and clk = '1' then
sink_state <= sink_next_state;
end if;
end process sink_input_update;
-- sink_output_update : process (clk, reset_n)
-- begin -- process
-- if reset_n = '0' then
-- sink_out_state <= normal;
-- elsif clk'event and clk = '1' then
-- sink_out_state <= sink_out_next_state;
-- end if;
-- end process sink_output_update;
error_register : process (clk, reset_n)
begin -- process
if reset_n = '0' then
packet_error_s <= "00";
elsif clk'event and clk = '1' then
packet_error_s <= packet_error_int;
end if;
end process;
packet_error <= packet_error_s;
-----------------------------------------------------------------------------
-- This was included because the vho simulations of fifo produce 'X' in
-- reset whcih means that for the FFT, alll outputs go to X when sop = X
-----------------------------------------------------------------------------
--gen_calc_sop: if SOP_EOP_CALC_g = true generate
--
-- -- generate sop and eop separate
-- out_cnt_p : process (clk, reset)
-- begin -- process out_cnt_p
-- if reset = '1' then
-- fifo_rdreq_d <= '0';
-- out_cnt <= 0;
-- elsif rising_edge(clk) then
-- fifo_rdreq_d <= fifo_rdreq;
-- if fifo_rdreq = '1' then
-- if out_cnt < PACKET_SIZE_g - 1 then
-- out_cnt <= out_cnt + 1;
-- else
-- out_cnt <= 0;
-- end if;
-- end if;
-- end if;
-- end process out_cnt_p;
--
-- send_sop_eop_p : process (clk, reset)
-- begin -- process send_sop_eop_p
-- if reset = '1' then
-- send_sop_s <= '0';
-- send_eop_s <= '0';
-- elsif rising_edge(clk) then
-- if fifo_rdreq = '1' and sink_ready_ctrl = '1' then
-- send_sop_s <= '0';
-- send_eop_s <= '0';
-- if out_cnt = 0 then
-- send_sop_s <= '1';
-- end if;
-- if out_cnt = PACKET_SIZE_g - 1 then
-- send_eop_s <= '1';
-- end if;
-- end if;
-- end if;
-- end process send_sop_eop_p;
--
-- end generate gen_calc_sop;
--reset <= not reset_n;
at_sink_ready <= at_sink_ready_s;
at_sink_ready_s <= sink_ready_ctrl;
data <= at_sink_data;
data_valid(0) <= at_sink_valid;
-- sink_scfifo : altera_avalon_sc_fifo
-- generic map (
-- SYMBOLS_PER_BEAT => DATA_PORT_COUNT,
-- BITS_PER_SYMBOL => DATA_WIDTH,
-- FIFO_DEPTH => FIFO_DEPTH_g,
-- CHANNEL_WIDTH => 0,
-- ERROR_WIDTH => 0,
-- USE_PACKETS => 0)
-- port map (
-- clk => clk,
-- reset => reset,
-- in_ready => at_sink_ready_s,
-- in_data => at_sink_data,
-- in_valid => at_sink_valid,
-- in_startofpacket => '0',
-- in_endofpacket => '0',
-- out_ready => sink_ready_ctrl,
-- out_data => data,
-- out_valid => data_valid(0),
-- in_empty => (others => '0'),
-- in_error => (others => '0'),
-- in_channel => (others => '0'),
-- csr_address => (others => '0'),
-- csr_write => '0',
-- csr_read => '0',
-- csr_writedata => (others => '0'),
-- out_empty => open,
-- out_error => open,
-- out_channel => open);
end rtl;
| gpl-2.0 | 2b6bcf79db2e6fe47ed12ed2dea4a563 | 0.509305 | 3.519317 | false | false | false | false |
steveEECSrubin/usc_projects | ABB/DSP_RX_FSM.vhd | 1 | 7,116 | -- ***************************************************************************
-- File Name: DSP_RX_FSM.vhd
-- File Description:
-- This module receives the packet from DSP connected to RocketIO module.
-- The reason why dsp_tx and dsp_rx are different processess is because ideally
-- rocketio incoming data would be coming at slightly different phase/freq clock than onboard clock.
-- Therefore the received data must be read using rx recovered clock.
-- The clock to this module should be eventually be the MGT rx recovered clock.
-- As long as the RX K-Char is high nothing happens. The moment k-Char goes low it indicates
-- that the packet is being received. Ideally the K-char should be low for the entire lenght of
-- received packet. But in this case the DSP is unable send packet in such format instead the K-char
-- goes high and low many time during the length of packet.
-- The incoming packet bytes are immediately stored in BRAM2 one by one every clk cycle
-- Since the lenght of packet is known a timer is used to decide when to stop writing in BRAM2.
-- After that timer the k-char should be always high untill the next packet arrives. Also this avoids
-- interprocess handshake sigals which are suspected to be one of the possible reasons for data corruption.
-- ***************************************************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
entity DSP_RX_FSM is
port
(
--%%%%%%%%%%%%%%%%%%%%% INPUT PORTS %%%%%%%%%%%%%%%%%%%%%%%%%%%%%
USER_CLK : in std_logic;
MASTER : in std_logic;
START_OPERATION : in std_logic;
RECEIVER_READY : in std_logic;
RX1_CHAR_IS_K : in std_logic;
HMB : in std_logic_vector(1 downto 0);
RX1_DATA : in std_logic_vector(7 downto 0);
BRAM2_DOA : in std_logic_vector(7 downto 0);
--%%%%%%%%%%%%%%%%%%%%% OUTPUT PORTS %%%%%%%%%%%%%%%%%%%%%%%%%%%%%
PACKET_RECEIVED : out std_logic;
BRAM2_ENA : out std_logic;
BRAM2_WEA : out std_logic;
BRAM2_DIA : out std_logic_vector(7 downto 0);
BRAM2_ADDRA : out std_logic_vector(11 downto 0);
CHIPSCOPE_DEBUG : out std_logic_vector(9 downto 0)
);
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of DSP_RX_FSM : entity is "v4fx_mgtwizard_v1_7, Coregen v12.1";
end DSP_RX_FSM;
architecture RTL of DSP_RX_FSM is
----*********************************Signal Declarations********************************
signal master_i : std_logic := '0';
signal start_operation_i : std_logic := '0';
signal packet_error_i : std_logic := '0';
signal rx1_char_is_k_i : std_logic := '0';
signal rx1_k_i : std_logic := '0';
signal packet_received_i : std_logic := '0';
signal receiver_ready_i : std_logic := '0';
signal bram2_ena_i : std_logic := '0';
signal bram2_wea_i : std_logic := '0';
signal command_available_i : std_logic := '0';
signal command_checked_i : std_logic := '0';
signal hmb_i : std_logic_vector(1 downto 0) := "00";
signal RX_STATE : std_logic_vector(3 downto 0) := x"0";
signal temp_rx : std_logic_vector(7 downto 0) := x"00";
signal rx1_data_i : std_logic_vector(7 downto 0) := x"00";
signal bram2_doa_i : std_logic_vector(7 downto 0) := x"00";
signal bram2_dia_i : std_logic_vector(7 downto 0) := x"00";
signal bram2_addra_i : std_logic_vector(11 downto 0) := x"000";
signal chipscope_debug_i : std_logic_vector(9 downto 0) := "0000000000";
signal TOKEN_TIMER : integer range 0 to 1023 := 0;
--*********************************Main Body of Code**********************************
------------------------------------------------------
begin
--%%%%%%%%%%% signal connections for INPUT PORTS %%%%%%%%%%%%%%%%%%%%%%%
master_i <= MASTER;
start_operation_i <= START_OPERATION;
rx1_char_is_k_i <= RX1_CHAR_IS_K;
hmb_i <= HMB;
rx1_data_i <= RX1_DATA;
bram2_doa_i <= BRAM2_DOA;
--%%%%%%%%%%% signal connections for OUTPUT PORTS %%%%%%%%%%%%%%%%%%%%%%%
BRAM2_ENA <= bram2_ena_i;
BRAM2_WEA <= bram2_wea_i;
BRAM2_DIA <= bram2_dia_i;
BRAM2_ADDRA <= bram2_addra_i;
CHIPSCOPE_DEBUG <= chipscope_debug_i;
process(USER_CLK)
begin
if (rising_edge(USER_CLK)) then
chipscope_debug_i(0) <= RX_STATE(0);
temp_rx <= rx1_data_i;
rx1_k_i <= rx1_char_is_k_i;
case RX_STATE is
when x"0" => -- state 0
bram2_ena_i <= '0';
bram2_wea_i <= '0';
bram2_dia_i <= x"00";
bram2_addra_i <= x"000";
TOKEN_TIMER <= 0;
-- during power ON this state would wait for start operation but to go high.
-- the initial power on time delay is defined in MMC_top_level module using 3 cascaded counters.
if(start_operation_i = '0')then
RX_STATE <= x"0";
elsif(start_operation_i = '1' and master_i = '0')then
RX_STATE <= x"0";
else -- only go to state 1 if the board is master(meaning connected to DSP)
RX_STATE <= x"1";
end if;
when others => -- state 1
RX_STATE <= x"1";
--/*----------------------------------------------------------------
-- when k-char goes low start timer and enable BRAM2 write and increament address every clk.
if(rx1_k_i = '0' and TOKEN_TIMER < 300)then
TOKEN_TIMER <= TOKEN_TIMER+1;
bram2_ena_i <= '1';
bram2_wea_i <= '1';
bram2_dia_i <= temp_rx;
bram2_addra_i <= bram2_addra_i + x"001";
-- when k_char goes high before timer expires meaning that byte is framing character inserted
-- by DSP and not actual data.therefore disable BRAM2 write for that particular clk cycle.
elsif(rx1_k_i = '1' and (TOKEN_TIMER > 0 and TOKEN_TIMER < 300))then
TOKEN_TIMER <= TOKEN_TIMER+1;
bram2_ena_i <= '1';
bram2_wea_i <= '0';
bram2_dia_i <= x"00";
bram2_addra_i <= bram2_addra_i;
-- The received packet lenght is about 300byte or clk cycles
-- after 300 cycles wait(no operation) until clk cycle 800.
-- because during that time dsp_tx module would be using BRAM2 and therefore to prevent
-- any overwriting on BRAM2(because of false triggering on receiving section) it would be better
-- to wait untill BRAM2 is avaiablable again.
-- BRAM2 is available when dsp_tx finishes transmitting packet to DSP
elsif(TOKEN_TIMER >= 300 and TOKEN_TIMER < 800)then
TOKEN_TIMER <= TOKEN_TIMER+1;
bram2_ena_i <= '0';
bram2_wea_i <= '0';
bram2_dia_i <= x"00";
bram2_addra_i <= x"000";
else -- reset to default in any other condition.
TOKEN_TIMER <= 0;
bram2_ena_i <= '0';
bram2_wea_i <= '0';
bram2_dia_i <= x"00";
bram2_addra_i <= x"000";
end if;
end case;
end if;
end process;
--
end RTL;
| mit | a027acef12448eb5593ced2793f4d58f | 0.569983 | 3.193896 | false | false | false | false |
JuanMarcosRamirez/WeightedMedianDisenoLogico | misc/RS232/RS232 RefComp/SourceFiles/RS232RefComp.vhd | 2 | 11,024 | ------------------------------------------------------------------------
-- RS232RefCom.vhd
------------------------------------------------------------------------
-- Author: Dan Pederson
-- Copyright 2004 Digilent, Inc.
------------------------------------------------------------------------
-- Description: This file defines a UART which tranfers data from
-- serial form to parallel form and vice versa.
------------------------------------------------------------------------
-- Revision History:
-- 07/15/04 (Created) DanP
-- 02/25/08 (Created) ClaudiaG: made use of the baudDivide constant
-- in the Clock Dividing Processes
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Rs232RefComp is
Port (
TXD : out std_logic := '1';
RXD : in std_logic;
CLK : in std_logic; --Master Clock
DBIN : in std_logic_vector (7 downto 0); --Data Bus in
DBOUT : out std_logic_vector (7 downto 0); --Data Bus out
RDA : inout std_logic; --Read Data Available
TBE : inout std_logic := '1'; --Transfer Bus Empty
RD : in std_logic; --Read Strobe
WR : in std_logic; --Write Strobe
PE : out std_logic; --Parity Error Flag
FE : out std_logic; --Frame Error Flag
OE : out std_logic; --Overwrite Error Flag
RST : in std_logic := '0'); --Master Reset
end Rs232RefComp;
architecture Behavioral of Rs232RefComp is
------------------------------------------------------------------------
-- Component Declarations
------------------------------------------------------------------------
------------------------------------------------------------------------
-- Local Type Declarations
------------------------------------------------------------------------
--Receive state machine
type rstate is (
strIdle, --Idle state
strEightDelay, --Delays for 8 clock cycles
strGetData, --Shifts in the 8 data bits, and checks parity
strCheckStop --Sets framing error flag if Stop bit is wrong
);
type tstate is (
sttIdle, --Idle state
sttTransfer, --Move data into shift register
sttShift --Shift out data
);
type TBEstate is (
stbeIdle,
stbeSetTBE,
stbeWaitLoad,
stbeWaitWrite
);
------------------------------------------------------------------------
-- Signal Declarations
------------------------------------------------------------------------
constant baudDivide : std_logic_vector(7 downto 0) := "10100011"; --Baud Rate dividor, set now for a rate of 9600.
--Found by dividing 50MHz by 9600 and 16.
signal rdReg : std_logic_vector(7 downto 0) := "00000000"; --Receive holding register
signal rdSReg : std_logic_vector(9 downto 0) := "1111111111"; --Receive shift register
signal tfReg : std_logic_vector(7 downto 0); --Transfer holding register
signal tfSReg : std_logic_vector(10 downto 0) := "11111111111"; --Transfer shift register
signal clkDiv : std_logic_vector(8 downto 0) := "000000000"; --used for rClk
signal rClkDiv : std_logic_vector(3 downto 0) := "0000"; --used for tClk
signal ctr : std_logic_vector(3 downto 0) := "0000"; --used for delay times
signal tfCtr : std_logic_vector(3 downto 0) := "0000"; --used to delay in transfer
signal rClk : std_logic := '0'; --Receiving Clock
signal tClk : std_logic; --Transfering Clock
signal dataCtr : std_logic_vector(3 downto 0) := "0000"; --Counts the number of read data bits
signal parError: std_logic; --Parity error bit
signal frameError: std_logic; --Frame error bit
signal CE : std_logic; --Clock enable for the latch
signal ctRst : std_logic := '0';
signal load : std_logic := '0';
signal shift : std_logic := '0';
signal par : std_logic;
signal tClkRST : std_logic := '0';
signal rShift : std_logic := '0';
signal dataRST : std_logic := '0';
signal dataIncr: std_logic := '0';
signal strCur : rstate := strIdle; --Current state in the Receive state machine
signal strNext : rstate; --Next state in the Receive state machine
signal sttCur : tstate := sttIdle; --Current state in the Transfer state machine
signal sttNext : tstate; --Next state in the Transfer staet machine
signal stbeCur : TBEstate := stbeIdle;
signal stbeNext: TBEstate;
------------------------------------------------------------------------
-- Module Implementation
------------------------------------------------------------------------
begin
frameError <= not rdSReg(9);
parError <= not ( rdSReg(8) xor (((rdSReg(0) xor rdSReg(1)) xor (rdSReg(2) xor rdSReg(3))) xor ((rdSReg(4) xor rdSReg(5)) xor (rdSReg(6) xor rdSReg(7)))) );
DBOUT <= rdReg;
tfReg <= DBIN;
par <= not ( ((tfReg(0) xor tfReg(1)) xor (tfReg(2) xor tfReg(3))) xor ((tfReg(4) xor tfReg(5)) xor (tfReg(6) xor tfReg(7))) );
--Clock Dividing Functions--
process (CLK, clkDiv) --set up clock divide for rClk
begin
if (Clk = '1' and Clk'event) then
if (clkDiv = baudDivide) then
clkDiv <= "000000000";
else
clkDiv <= clkDiv +1;
end if;
end if;
end process;
process (clkDiv, rClk, CLK) --Define rClk
begin
if CLK = '1' and CLK'Event then
if clkDiv = baudDivide then
rClk <= not rClk;
else
rClk <= rClk;
end if;
end if;
end process;
process (rClk) --set up clock divide for tClk
begin
if (rClk = '1' and rClk'event) then
rClkDiv <= rClkDiv +1;
end if;
end process;
tClk <= rClkDiv(3); --define tClk
process (rClk, ctRst) --set up a counter based on rClk
begin
if rClk = '1' and rClk'Event then
if ctRst = '1' then
ctr <= "0000";
else
ctr <= ctr +1;
end if;
end if;
end process;
process (tClk, tClkRST) --set up a counter based on tClk
begin
if (tClk = '1' and tClk'event) then
if tClkRST = '1' then
tfCtr <= "0000";
else
tfCtr <= tfCtr +1;
end if;
end if;
end process;
--This process controls the error flags--
process (rClk, RST, RD, CE)
begin
if RD = '1' or RST = '1' then
FE <= '0';
OE <= '0';
RDA <= '0';
PE <= '0';
elsif rClk = '1' and rClk'event then
if CE = '1' then
FE <= frameError;
OE <= RDA;
RDA <= '1';
PE <= parError;
rdReg(7 downto 0) <= rdSReg (7 downto 0);
end if;
end if;
end process;
--This process controls the receiving shift register--
process (rClk, rShift)
begin
if rClk = '1' and rClk'Event then
if rShift = '1' then
rdSReg <= (RXD & rdSReg(9 downto 1));
end if;
end if;
end process;
--This process controls the dataCtr to keep track of shifted values--
process (rClk, dataRST)
begin
if (rClk = '1' and rClk'event) then
if dataRST = '1' then
dataCtr <= "0000";
elsif dataIncr = '1' then
dataCtr <= dataCtr +1;
end if;
end if;
end process;
--Receiving State Machine--
process (rClk, RST)
begin
if rClk = '1' and rClk'Event then
if RST = '1' then
strCur <= strIdle;
else
strCur <= strNext;
end if;
end if;
end process;
--This process generates the sequence of steps needed receive the data
process (strCur, ctr, RXD, dataCtr, rdSReg, rdReg, RDA)
begin
case strCur is
when strIdle =>
dataIncr <= '0';
rShift <= '0';
dataRst <= '0';
CE <= '0';
if RXD = '0' then
ctRst <= '1';
strNext <= strEightDelay;
else
ctRst <= '0';
strNext <= strIdle;
end if;
when strEightDelay =>
dataIncr <= '0';
rShift <= '0';
CE <= '0';
if ctr(2 downto 0) = "111" then
ctRst <= '1';
dataRST <= '1';
strNext <= strGetData;
else
ctRst <= '0';
dataRST <= '0';
strNext <= strEightDelay;
end if;
when strGetData =>
CE <= '0';
dataRst <= '0';
if ctr(3 downto 0) = "1111" then
ctRst <= '1';
dataIncr <= '1';
rShift <= '1';
else
ctRst <= '0';
dataIncr <= '0';
rShift <= '0';
end if;
if dataCtr = "1010" then
strNext <= strCheckStop;
else
strNext <= strGetData;
end if;
when strCheckStop =>
dataIncr <= '0';
rShift <= '0';
dataRst <= '0';
ctRst <= '0';
CE <= '1';
strNext <= strIdle;
end case;
end process;
--TBE State Machine--
process (CLK, RST)
begin
if CLK = '1' and CLK'Event then
if RST = '1' then
stbeCur <= stbeIdle;
else
stbeCur <= stbeNext;
end if;
end if;
end process;
--This process gererates the sequence of events needed to control the TBE flag--
process (stbeCur, CLK, WR, DBIN, load)
begin
case stbeCur is
when stbeIdle =>
TBE <= '1';
if WR = '1' then
stbeNext <= stbeSetTBE;
else
stbeNext <= stbeIdle;
end if;
when stbeSetTBE =>
TBE <= '0';
if load = '1' then
stbeNext <= stbeWaitLoad;
else
stbeNext <= stbeSetTBE;
end if;
when stbeWaitLoad =>
if load = '0' then
stbeNext <= stbeWaitWrite;
else
stbeNext <= stbeWaitLoad;
end if;
when stbeWaitWrite =>
if WR = '0' then
stbeNext <= stbeIdle;
else
stbeNext <= stbeWaitWrite;
end if;
end case;
end process;
--This process loads and shifts out the transfer shift register--
process (load, shift, tClk, tfSReg)
begin
TXD <= tfsReg(0);
if tClk = '1' and tClk'Event then
if load = '1' then
tfSReg (10 downto 0) <= ('1' & par & tfReg(7 downto 0) &'0');
end if;
if shift = '1' then
tfSReg (10 downto 0) <= ('1' & tfSReg(10 downto 1));
end if;
end if;
end process;
-- Transfer State Machine--
process (tClk, RST)
begin
if (tClk = '1' and tClk'Event) then
if RST = '1' then
sttCur <= sttIdle;
else
sttCur <= sttNext;
end if;
end if;
end process;
-- This process generates the sequence of steps needed transfer the data--
process (sttCur, tfCtr, tfReg, TBE, tclk)
begin
case sttCur is
when sttIdle =>
tClkRST <= '0';
shift <= '0';
load <= '0';
if TBE = '1' then
sttNext <= sttIdle;
else
sttNext <= sttTransfer;
end if;
when sttTransfer =>
shift <= '0';
load <= '1';
tClkRST <= '1';
sttNext <= sttShift;
when sttShift =>
shift <= '1';
load <= '0';
tClkRST <= '0';
if tfCtr = "1100" then
sttNext <= sttIdle;
else
sttNext <= sttShift;
end if;
end case;
end process;
end Behavioral; | gpl-3.0 | 0bb14e7754056ca14f5b66f3fa5b6490 | 0.53438 | 3.146119 | false | false | false | false |
DougFirErickson/parallella-hw | fpga/ip/xilinx/fifo_async_103x32/fifo_generator_v12_0/hdl/common/shft_wrapper.vhd | 6 | 13,889 | `protect begin_protected
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| gpl-3.0 | 6cf849e0ba4617fc56d5b60ed9fedf2b | 0.935561 | 1.877399 | false | false | false | false |
JuanMarcosRamirez/WeightedMedianDisenoLogico | misc/FPGA/otros/auditoría_imagen_16x16/tope_TestBench.vhd | 1 | 6,658 | --------------------------------------------------------------------------
--Autor: Jorge Márquez
--fecha: julio 2008
---------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use std.textio.all;
entity tope_tb is
-- generic(
-- vwidth : INTEGER := 8;
-- order : INTEGER := 5;
-- num_cols : INTEGER := 512;
-- num_rows : INTEGER := 512 );
end tope_tb;
architecture TB_ARCHITECTURE of tope_tb is
component tope_rof512_uart --componente
-- generic( --componente
-- vwidth : INTEGER := 8; --componente
-- order : INTEGER := 5; --componente
-- num_cols : INTEGER := 512; --componente
-- num_rows : INTEGER := 512 ); --componente
Port ( tx_female : out std_logic;
rx_female : in std_logic;
slides_SW : in std_logic_vector(3 downto 0);
LED : out std_logic_vector(7 downto 0);
RSTn : in std_logic;
clk : in std_logic); --componente
end component; --componente
signal slides_SW : std_logic_vector(3 downto 0);
signal tx_female : std_logic:= '0'; --decl señales
signal rx_female : std_logic:= '0'; --decl señales
signal LED : std_logic_vector(7 downto 0) := "00000000"; --decl señales
signal RSTn : std_logic:= '0'; --decl señales
signal clk : std_logic:= '0'; --decl señales
signal TT : std_logic:= '0';
signal byteindata: std_logic_vector(7 downto 0) := "00000000";
begin
UUT : tope_rof512_uart
port map --portmap
(clk => clk, --portmap
RSTn => RSTn, --portmap
LED => LED, --portmap
slides_SW => slides_SW,
rx_female => rx_female, --portmap
tx_female => tx_female ); --portmap
rx_female <= byteindata(0);
read_from_file: process(TT) --read_from_file
variable indata_line: line; --read_from_file
variable indata: integer; --read_from_file
file input_data_file: text open read_mode is "C:\MATLAB701\work\lenasyp16x16.ser"; --read_from_file
begin --read_from_file
if rising_edge(TT) or falling_edge(TT) then --read_from_file
readline(input_data_file,indata_line); --read_from_file
read(indata_line,indata); --read_from_file
byteindata <= conv_std_logic_vector(indata,8); --original: D <= conv_std_logic_vector(indata,8);
-- rx_female <= byteindata(0);
if endfile(input_data_file) then --read_from_file
report "end of file -- looping back to start of file"; --read_from_file
file_close(input_data_file); --read_from_file
file_open(input_data_file,"C:\MATLAB701\work\lenasyp16x16.ser"); --read_from_file
end if; --read_from_file
end if; --read_from_file
end process; --read_from_file
-- write_to_file: process(Clk) --write_to_file
-- variable outdata_line: line; --write_to_file
-- variable outdata: integer:=0; --write_to_file
-- file output_data_file: text open write_mode is "D:\JORGETESIS\proc_HW1lena512_syp.ser"; --write_to_file
-- begin --write_to_file
-- if rising_edge(Clk) then --write_to_file
-- outdata := CONV_INTEGER(tx_female); --write_to_file --original: outdata := CONV_INTEGER(unsigned(Dout));
-- -- if DV = '1' then --write_to_file
-- write(outdata_line,outdata); --write_to_file
-- writeline(output_data_file,outdata_line); --write_to_file
-- -- end if; --write_to_file
-- end if; --write_to_file
-- end process; --write_to_file
clock_gen: process --reloj
begin --reloj
Clk <= '0'; --reloj
wait for 10 ns; --reloj
Clk <= '1'; --reloj
wait for 10 ns; --reloj
end process; --reloj
TT_gen: process --patron de transmisión (8680=~1/115200)
begin --patron de transmisión (8680=~1/115200)
TT <= '0'; --patron de transmisión (8680=~1/115200)
wait for 8680 ns; --patron de transmisión (8680=~1/115200)
TT <= '1'; --patron de transmisión (8680=~1/115200)
wait for 8680 ns; --patron de transmisión (8680=~1/115200)
end process;
reset_gen: process --reset
begin --reset
RSTn <= '0'; --reset
wait for 20 ns; --reset
RSTn <= '1'; --reset
wait; --reset
end process; --reset
slides_SW(0)<= '1';
slides_SW(1)<= '1';
slides_SW(2)<= '0';
slides_SW(3)<= '1';
end TB_ARCHITECTURE;
configuration TESTBENCH_FOR_tope_rof512_uart of tope_tb is
for TB_ARCHITECTURE
for UUT : tope_rof512_uart
use entity work.tope_rof512_uart(comportamiento);
end for;
end for;
end TESTBENCH_FOR_tope_rof512_uart;
| gpl-3.0 | 5697360537317b5689308d94b2cd4a5d | 0.408081 | 4.145704 | false | false | false | false |
DougFirErickson/parallella-hw | fpga/ip/xilinx/fifo_async_103x32/fifo_generator_v12_0/hdl/ramfifo/rd_status_flags_as.vhd | 6 | 15,251 | `protect begin_protected
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`protect end_protected
| gpl-3.0 | 280597e2acb1fc0c0ba52df26b06bdfa | 0.934365 | 1.865338 | false | false | false | false |
SebastianCallh/copter-modern | cpu.vhd | 1 | 31,000 | --CPU
-- library declaration
library IEEE;
use IEEE.STD_LOGIC_1164.ALL; -- basic IEEE library
use IEEE.NUMERIC_STD.ALL; -- IEEE library for the unsigned type
entity CPU is
port ( clk : in std_logic; -- Systen clock
collision : in std_logic;
reset : in std_logic;
player_x : out integer;
player_y : out integer;
input : in std_logic;
new_column : in std_logic;
gap : out integer := 60;
height : out integer := 0;
terrain_change : in std_logic;
speed : out integer;
score : out std_logic_vector(15 downto 0));
end CPU;
architecture Behavioral of CPU is
-- Signals that connect to the bus (and the bus itself)
signal data_bus : std_logic_vector(15 downto 0);
signal pc : std_logic_vector(15 downto 0) := x"0012";
signal asr : std_logic_vector(15 downto 0);
signal alu_input : signed(15 downto 0);
signal alu_res : std_logic_vector(15 downto 0);
signal res : std_logic_vector(15 downto 0);
signal ir : std_logic_vector(31 downto 0);
signal pmem_asr : std_logic_vector(15 downto 0);
signal pmem_res : std_logic_vector(15 downto 0);
-- Registers
signal reg1 : std_logic_vector(15 downto 0) := "0000000000000011";
signal reg2 : std_logic_vector(15 downto 0) := "0000000000000001";
signal reg3 : std_logic_vector(15 downto 0);
signal reg4 : std_logic_vector(15 downto 0);
-- Micro
signal micro_instr : std_logic_vector(23 downto 0);
signal micro_pc : std_logic_vector(7 downto 0) := "00000000";
-- Interrupt alerts
signal terrain_prev : std_logic;
signal terrain_alert : std_logic;
signal input_prev : std_logic;
signal press_alert : std_logic;
signal release_alert : std_logic;
signal collision_prev : std_logic;
signal collision_alert : std_logic;
signal reset_prev : std_logic;
signal reset_alert : std_logic;
signal input_release : std_logic;
-- Move player signals
signal player_upd_alert : std_logic;
signal player_upd_counter : integer := 0;
-- Interrupt states saved
signal intr_pc : std_logic_vector(15 downto 0);
signal intr_res : std_logic_vector(15 downto 0);
signal intr_alu_res : std_logic_vector(15 downto 0);
signal intr_z : std_logic;
signal intr_c : std_logic;
signal intr_n : std_logic;
signal intr_o : std_logic;
signal intr_enable : std_logic := '0';
-- ALU signals
signal alu_add : std_logic_vector(16 downto 0);
signal alu_sub : std_logic_vector(16 downto 0);
signal alu_not : std_logic_vector(15 downto 0);
signal alu_and : std_logic_vector(15 downto 0);
signal alu_or : std_logic_vector(15 downto 0);
signal alu_xor : std_logic_vector(15 downto 0);
--ran_gen signals
signal ran_nr : std_logic_vector(31 downto 0) := (others => '0');
signal ran_bit : std_logic;
-- Initial value for new_ran is seed
signal new_ran : std_logic_vector(31 downto 0) := "10101010001010110010110001010010";
-- Flags
signal n_flag : std_logic;
signal z_flag : std_logic;
signal o_flag : std_logic;
signal c_flag : std_logic;
-- Constants (Variables)
signal x_pos : std_logic_vector(15 downto 0) := x"0004";
signal y_pos : std_logic_vector(15 downto 0) := x"0005";
signal height_pos : std_logic_vector(15 downto 0) := x"0007";
signal gap_pos : std_logic_vector(15 downto 0) := x"0008";
signal player_upd : std_logic_vector(15 downto 0) := x"000C";
signal press_pos : std_logic_vector(15 downto 0) := x"000D";
signal release_pos : std_logic_vector(15 downto 0) := x"000E";
signal speed_pos : std_logic_vector(15 downto 0) := x"0011";
signal speed_internal : integer := 1000;
signal player_speed : integer;
-- Progress signals
signal progress : unsigned(15 downto 0) := (others => '0');
signal progress_counter : integer := 0; -- updates progress every second
signal PROGRESS_LATENCY : integer := 10000000; -- 1/10th second (if clock at 100MHz)
-- Score signals
signal score_counter : integer := 0;
signal SCORE_LATENCY : integer := 10000000; -- 1/10th second (if clock at 100MHz)
-- Score counters
signal ones : unsigned(3 downto 0) := (others => '0');
signal tens : unsigned(3 downto 0) := (others => '0');
signal hundreds : unsigned(3 downto 0) := (others => '0');
signal thousands : unsigned(3 downto 0) := (others => '0');
-- Alias
alias TO_BUS : std_logic_vector(3 downto 0) is micro_instr(23 downto 20); -- to bus
alias FROM_BUS : std_logic_vector(3 downto 0) is micro_instr(19 downto 16); -- from bus
alias P_BIT : std_logic is micro_instr(15); -- p bit
alias ALU_OP : std_logic_vector(2 downto 0) is micro_instr(14 downto 12); -- alu_op
alias SEQ : std_logic_vector(3 downto 0) is micro_instr(11 downto 8); -- seq
alias MICRO_ADR : std_logic_vector(7 downto 0) is micro_instr(7 downto 0); -- micro address
alias FETCH_NEXT : std_logic is ir(21);
alias OP_CODE : std_logic_vector(7 downto 0) is ir(31 downto 24);
-- Interrupt vectors
constant COLLISION_INTERRUPT_VECTOR : std_logic_vector(15 downto 0) := x"0000";
constant TERRAIN_CHANGE_INTERRUPT_VECTOR : std_logic_vector(15 downto 0) := x"0001";
constant RESET_INTERRUPT_VECTOR : std_logic_vector(15 downto 0) := x"0002";
-- Player update frequency
constant PLAYER_UPDATE_LATENCY : integer := 1400000; -- same as offset for now
constant ZERO : std_logic_vector(15 downto 0) := x"0000";
constant ONE : std_logic_vector(15 downto 0) := x"0001";
-- PMEM (Max is 65535 for 16 bit addresses)
type ram_t is array (0 to 4096) of std_logic_vector(15 downto 0);
signal pmem : ram_t := (
-- The processed assembly code is pasted here
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"3420",
x"0000",
x"1620",
x"010d",
x"3420",
x"0001",
x"1620",
x"00f5",
x"3420",
x"0002",
x"1620",
x"010d",
x"3420",
x"0004",
x"1620",
x"0096",
x"3420",
x"0005",
x"1620",
x"00c8",
x"3420",
x"0007",
x"1620",
x"000f",
x"3420",
x"0008",
x"1620",
x"001e",
x"3420",
x"0006",
x"1620",
x"0001",
x"3420",
x"0010",
x"1620",
x"0000",
x"3420",
x"0011",
x"1620",
x"01f4",
x"4500",
x"4000",
x"3420",
x"000c",
x"3620",
x"0001",
x"1F20",
x"0070",
x"3D20",
x"000a",
x"1F20",
x"004a",
x"3320",
x"003e",
x"4420",
x"0000",
x"3420",
x"0013",
x"1720",
x"0001",
x"3420",
x"0011",
x"3620",
x"012c",
x"2320",
x"005a",
x"3420",
x"0011",
x"1B20",
x"000a",
x"3420",
x"0013",
x"3620",
x"000a",
x"2120",
x"003e",
x"3420",
x"0013",
x"1620",
x"0000",
x"3420",
x"0008",
x"3620",
x"0010",
x"2320",
x"003e",
x"3420",
x"0008",
x"1B20",
x"0001",
x"3320",
x"003e",
x"3420",
x"000c",
x"1620",
x"0000",
x"3420",
x"000d",
x"3620",
x"0000",
x"1F20",
x"008a",
x"3420",
x"000e",
x"3620",
x"0000",
x"1F20",
x"00a6",
x"3420",
x"000d",
x"1620",
x"0000",
x"3420",
x"000e",
x"1620",
x"0000",
x"3320",
x"003e",
x"3420",
x"0005",
x"3620",
x"01c2",
x"3920",
x"003e",
x"3420",
x"0010",
x"3620",
x"0005",
x"2120",
x"00c2",
x"3420",
x"0010",
x"1620",
x"0000",
x"3420",
x"0006",
x"3620",
x"0003",
x"1F20",
x"00c2",
x"3420",
x"0006",
x"1720",
x"0001",
x"3320",
x"00c2",
x"3420",
x"0005",
x"3620",
x"0003",
x"2320",
x"003e",
x"3420",
x"0010",
x"3620",
x"0005",
x"2120",
x"00c2",
x"3420",
x"0010",
x"1620",
x"0000",
x"3420",
x"0006",
x"3620",
x"fffd",
x"1F20",
x"00c2",
x"3420",
x"0006",
x"1B20",
x"0001",
x"3320",
x"00c2",
x"3420",
x"0010",
x"1720",
x"0001",
x"3420",
x"0005",
x"1760",
x"0006",
x"3420",
x"000c",
x"1620",
x"0000",
x"4500",
x"3320",
x"003e",
x"3420",
x"0007",
x"3620",
x"0001",
x"1F20",
x"0147",
x"3420",
x"0007",
x"1B20",
x"0001",
x"4500",
x"3B00",
x"3320",
x"003e",
x"3420",
x"0009",
x"1660",
x"0007",
x"3420",
x"0009",
x"1760",
x"0008",
x"3420",
x"0009",
x"3620",
x"003a",
x"3920",
x"014c",
x"3420",
x"0007",
x"1720",
x"0001",
x"4500",
x"3B00",
x"3320",
x"003e",
x"3520",
x"000a",
x"3420",
x"000a",
x"2720",
x"0003",
x"3420",
x"000a",
x"1760",
x"0012",
x"3420",
x"000a",
x"3620",
x"0002",
x"2320",
x"00d1",
x"3420",
x"000a",
x"3620",
x"0003",
x"3920",
x"00df",
x"3320",
x"0146",
x"3420",
x"0003",
x"1620",
x"0001",
x"3420",
x"0007",
x"1620",
x"0000",
x"3420",
x"0008",
x"1620",
x"0041",
x"4500",
x"3420",
x"000a",
x"1620",
x"ffff",
x"3420",
x"000a",
x"3620",
x"0000",
x"1F20",
x"012a",
x"3420",
x"000a",
x"1B20",
x"0001",
x"3320",
x"011e",
x"3420",
x"0008",
x"1620",
x"001e",
x"3420",
x"0007",
x"1620",
x"000f",
x"3420",
x"0005",
x"1620",
x"0014",
x"3420",
x"0011",
x"1620",
x"01f4",
x"4500",
x"3B00",
x"3320",
x"003e",
x"3420",
x"0003",
x"1620",
x"0001",
x"3420",
x"0005",
x"1620",
x"00c8",
x"3B00",
x"3420",
x"0012",
x"1620",
x"0001",
x"3B00",
x"3420",
x"0012",
x"1620",
x"0000",
x"3B00",
x"3320",
x"003e",
x"FF00",
others => "0000000000000000");
-- micro-MEM (Max is 255 for 8 bit addresses)
type micro_mem_t is array (0 to 255) of std_logic_vector(23 downto 0);
signal micro_mem : micro_mem_t := (
-- Here are all the micro programs
"000000000000111101000001", -- check for interrupts, ASR <= PC
"000100100000000000000000", -- asr <= pc
"001100000000000000000000", -- fetch instruction (only 16 bits)
"001101100000000000000000", -- and check for 32 bit instruction
"000000001000100000010100", -- if 32 bit fetch next 16, else goto OP
"000100101000000000000000", -- asr <= pc, pc++
"001100000000000000000000", -- fetch pmem(asr)
"001101110000000000000000", -- ir(15 downto 0) <= pmem(asr)
"000000000000001000000000", -- 08:check adress mod
"001100000000000000000000", -- 09:ABSOLUTE fetch pmem(asr)
"001100100000000100000000", -- asr <= pmem(asr)
"001100000000000000000000", -- 0B:DIRECT fetch pmem(asr)
"001100100000000000000000", -- asr <= pmem(asr)
"001100000000000000000000", -- fetch pmem(asr)
"001100100000000100000000", -- asr <= pmem(asr)
"001100000000000000000000", -- 0F:INDIRECT fetch pmem(asr)
"001100100000000000000000", -- asr <= pmem(asr)
"001100000000000000000000", -- fetch pmem(asr)
"001100100000000000000000", -- asr <= pmem(asr)
"001100000000000000000000", -- fetch pmem(asr)
"001100100000000100000000", -- asr <= pmem(asr)
"000000000000000100000000", -- 15:OP micro_pc <= OP
"001011000000001100000000", -- 16:mv pmem(res) <= asr
"110000000000000000000000", -- 17:add fetch pmem(res)
"110001000000000000000000", -- alu_res <= pmem(res)
"001000000001000000000000", -- alu_res += asr
"010011000000001100000000", -- pmem(res) <= alu_res
"110000000000000000000000", -- 1B:sub fetch pmem(res)
"110001000000000000000000", -- alu_res <= pmem(res)
"001000000010000000000000", -- alu_res -= asr
"010011000000001100000000", -- pmem(res) <= alu_res
"000000000000010100000000", -- 1F:beq if z = 0: u_pc <= 0
"001000010000001100000000", -- PC <= asr
"000000000000011100000000", -- 21:bne if z = 1: u_pc <= 0
"001000010000001100000000", -- PC <= asr
"000000000000100100000000", -- 23:bn if n = 0: u_pc <= 0
"001000010000001100000000", -- PC <= asr
"001000000011000000000000", -- 25:not alu_res <= not asr
"010011000000001100000000", -- pmem(res) <= alu_res
"110000000000000000000000", -- 27:and fetch pmem(res)
"110001000000000000000000", -- alu_res <= pmem(res)
"001000000100000000000000", -- alu_res <= alu_res and asr
"010011000000001100000000", -- pmem(res) <= alu_res
"110000000000000000000000", -- 2B:or fetch pmem(res)
"110001000000000000000000", -- alu_res <= pmem(res)
"001000000101000000000000", -- alu_res <= alu_res or asr
"010011000000001100000000", -- pmem(res) <= alu_res
"110000000000000000000000", -- 2F:xor fetch pmem(res)
"110001000000000000000000", -- alu_res <= pmem(res)
"001000000110000000000000", -- alu_res = alu_res xor asr
"010011000000001100000000", -- pmem(res) <= alu_res
"001000010000001100000000", -- 33:jmp PC <= asr
"001001010000001100000000", -- 34:res res <= asr (load res)
"110100110000001100000000", -- 35:ran pmem(asr) <= rand_nr
"110000000000000000000000", -- 36:cmp fetch pmem(res)
"110001000000000000000000", -- alu_res <= pmem(res)
"001000000010001100000000", -- alu_res <= alu_res - asr
"000000000000011000000000", -- 39:bp if n = 1: u_pc <= 0
"001000010000001100000000", -- PC <= asr
"000000000000101000000000", -- 3B:rfi (return from interrupt)
"000000000000001100000000", -- micro_pc <= 0
"111000000000000000000000", -- 3D:pcmp fetch progress
"111001000000000000000000", -- alu_res <= progress
"001000000010001100000000", -- alu_res <= alu_res - asr
"000000000000110000000000", -- 40:eint enable interrupts
"000100100000000000000000", -- 41:intr asr <= pc
"001100000000000000000000", -- fetch pmem(asr)
"001100010000010000000001", -- pc <= pmem(asr), micro_pc <= 1
"001011100000000000000000", -- 44:lprg progress <= asr
-- NOTE: place all new micro programs above upd, in case update needs to...update
"000000000000000000000001", -- 45:upd player_x <= pmem(x_pos)
"000000000000000000000010", -- player_y <= pmem(y_pos)
"000000000000000000000011", -- height <= pmem(height_pos)
"000000000000000000000100", -- gap <= pmem(gap_pos)
"000000000000000000000101", -- speed <= pmem(speed_pos)
"000000000000001100000000", -- micro_pc <= 0
others => "000000000000000000000000");
-- ROM (mod) (Includes all 4 mods, need to be updated with correct micro-addresses)
type mod_rom_t is array (0 to 3) of std_logic_vector(7 downto 0);
constant mod_rom : mod_rom_t := (x"09", x"0B", x"0F", x"00");
begin -- Behavioral
-- fetching micro_instr
micro_instr <= micro_mem(to_integer(unsigned(micro_pc)));
-- Speed
speed <= speed_internal;
-- Score
score(15 downto 12) <= std_logic_vector(thousands);
score(11 downto 8) <= std_logic_vector(hundreds);
score(7 downto 4) <= std_logic_vector(tens);
score(3 downto 0) <= std_logic_vector(ones);
-- Update
process(clk)
begin
if rising_edge(clk) then
-- Put the information from pmem on the correct signals
-- (this makes sure vga_motor and pic_mem has the correct information
-- for drawing on the screen)
if micro_instr = "000000000000000000000001" then
player_x <= to_integer(unsigned(pmem(to_integer(unsigned(x_pos)))));
elsif micro_instr = "000000000000000000000010" then
player_y <= to_integer(unsigned(pmem(to_integer(unsigned(y_pos)))));
elsif micro_instr = "000000000000000000000011" then
height <= to_integer(unsigned(pmem(to_integer(unsigned(height_pos)))));
elsif micro_instr = "000000000000000000000100" then
gap <= to_integer(unsigned(pmem(to_integer(unsigned(gap_pos)))));
elsif micro_instr = "000000000000000000000101" then
speed_internal <= to_integer(unsigned(pmem(to_integer(unsigned(speed_pos)))));
end if;
end if;
end process;
-- pc
process(clk)
begin
if rising_edge(clk) then
-- pc to bus
if FROM_BUS = "0001" then
pc <= data_bus;
-- pc++
elsif P_BIT = '1' then
pc <= std_logic_vector(unsigned(pc) + 1);
-- Handle interrupts
elsif SEQ = "1111" and intr_enable = '1' then
-- Store important information to be returned after the interrupt
intr_pc <= pc;
intr_res <= res;
intr_alu_res <= alu_res;
intr_z <= z_flag;
intr_n <= n_flag;
intr_o <= o_flag;
intr_c <= c_flag;
-- Set pc to the correct interrupt vector and disables interrupts
-- (interrupts are enabled after the specific interrupt code has been run)
if reset_alert = '1' then
intr_enable <= '0';
reset_alert <= '0';
pc <= RESET_INTERRUPT_VECTOR;
elsif collision_alert = '1' then
intr_enable <= '0';
collision_alert <= '0';
pc <= COLLISION_INTERRUPT_VECTOR;
elsif terrain_alert = '1' then
intr_enable <= '0';
terrain_alert <= '0';
pc <= TERRAIN_CHANGE_INTERRUPT_VECTOR;
end if;
-- Return from interrupt: enable interrupts and restore pc
elsif SEQ = "1010" then
intr_enable <= '1';
pc <= intr_pc;
-- Enable interrupts
elsif SEQ = "1100" then
intr_enable <= '1';
end if;
-- Check if the terrain needs to update
if terrain_change = '1' and terrain_prev = '0' then
terrain_alert <= '1';
end if;
-- Check if there has been a collision
if collision = '1' and collision_prev = '0' then
collision_alert <= '1';
end if;
-- Check if the reset button has been pressed
if reset = '1' and reset_prev = '0' then
reset_alert <= '1';
end if;
-- Keep track of previous
terrain_prev <= terrain_change;
collision_prev <= collision;
reset_prev <= reset;
end if;
end process;
-- asr
process(clk)
begin
if rising_edge(clk) then
-- from bus to asr
if FROM_BUS = "0010" then
asr <= data_bus;
end if;
end if;
end process;
-- pmem
process(clk)
begin
if rising_edge(clk) then
-- from bus to pmem(asr)
if FROM_BUS = "0011" then
pmem(to_integer(unsigned(asr))) <= data_bus;
-- from bus to pmem(res)
elsif FROM_BUS = "1100" then
pmem(to_integer(unsigned(res))) <= data_bus;
-- from pmem(asr) to pmem_asr (can be put on bus next clock cycle)
elsif TO_BUS = "0011" then
pmem_asr <= pmem(to_integer(unsigned(asr)));
-- from pmem(res) to pmem_res (can be put on bus next clock cycle)
elsif TO_BUS = "1100" then
pmem_res <= pmem(to_integer(unsigned(res)));
-- Write to memory if the player position needs to update
elsif player_upd_alert = '1' then
player_upd_alert <= '0';
pmem(to_integer(unsigned(player_upd))) <= ONE;
-- Write to memory if the spacebar has been released
elsif release_alert = '1' then
release_alert <= '0';
pmem(to_integer(unsigned(release_pos))) <= ONE;
-- Write to memory if the spacebar has been pressed
elsif press_alert = '1' then
press_alert <= '0';
pmem(to_integer(unsigned(press_pos))) <= ONE;
end if;
-- Creates a delay (based on speed) which decides when the player position
-- should update
if player_upd_counter >= player_speed then
player_upd_alert <= '1';
player_upd_counter <= 0;
else
player_upd_counter <= player_upd_counter + 1;
end if;
-- Check if the spacebar has been pressed
if input = '1' and input_prev = '0' then
press_alert <= '1';
end if;
-- Check if the spacebar has been released
if input = '0' and input_prev = '1' then
release_alert <= '1';
end if;
input_prev <= input;
end if;
end process;
-- Makes sure that the player speed gets faster as speed increases,
-- but not as fast as the terrain speed increases
player_speed <= (speed_internal*1000) + ((1000-speed_internal)*900);
-- progress
process(clk)
begin
if rising_edge(clk) then
-- bus to progress, reset progress_counter
if FROM_BUS = "1110" then
progress <= unsigned(data_bus);
progress_counter <= 0;
-- Increases progress every second (on a 100MHz clock)
elsif progress_counter = PROGRESS_LATENCY then
progress <= progress + 1;
progress_counter <= 0;
else
progress_counter <= progress_counter + 1;
end if;
end if;
end process;
-- score
process(clk)
begin
if rising_edge(clk) then
-- Reset score if there is a collision or if the game is reset
if reset = '1' or collision = '1' then
thousands <= (others => '0');
hundreds <= (others => '0');
tens <= (others => '0');
ones <= (others => '0');
score_counter <= 0;
-- Keep counting score up every 1/10th of a second
elsif score_counter = SCORE_LATENCY then
score_counter <= 0;
if ones = "1001" then
if tens = "1001" then
if hundreds = "1001" then
-- resets score if score is 9999
if thousands = "1001" then
thousands <= (others => '0');
hundreds <= (others => '0');
tens <= (others => '0');
ones <= (others => '0');
else
thousands <= thousands + 1;
hundreds <= (others => '0');
tens <= (others => '0');
ones <= (others => '0');
end if;
else
hundreds <= hundreds + 1;
tens <= (others => '0');
ones <= (others => '0');
end if;
else
tens <= tens + 1;
ones <= (others => '0');
end if;
else
ones <= ones + 1;
end if;
else
score_counter <= score_counter + 1;
end if;
end if;
end process;
-- res
process(clk)
begin
if rising_edge(clk) then
-- from bus to res
if FROM_BUS = "0101" then
res <= data_bus;
-- Return from interrupt: restore res
elsif SEQ = "1010" then
res <= intr_res;
end if;
end if;
end process;
-- from bus to ir
process(clk)
begin
if rising_edge(clk) then
-- from bus to ir(31->16)
if FROM_BUS = "0110" then
ir(31 downto 16) <= data_bus;
-- from bus to ir(15->0)
elsif FROM_BUS = "0111" then
ir(15 downto 0) <= data_bus;
end if;
end if;
end process;
-- from bus to reg1
process(clk)
begin
if rising_edge(clk) then
if FROM_BUS = "1000" then
reg1 <= data_bus;
end if;
end if;
end process;
-- from bus to reg2
process(clk)
begin
if rising_edge(clk) then
if FROM_BUS = "1001" then
reg2 <= data_bus;
end if;
end if;
end process;
-- from bus to reg3
process(clk)
begin
if rising_edge(clk) then
if FROM_BUS = "1010" then
reg3 <= data_bus;
end if;
end if;
end process;
-- from bus to reg4
process(clk)
begin
if rising_edge(clk) then
if FROM_BUS = "1011" then
reg4 <= data_bus;
end if;
end if;
end process;
-- Moving data TO the bus
with TO_BUS select
data_bus <= pc when "0001",
asr when "0010",
pmem_asr when "0011",
alu_res when "0100",
res when "0101",
ir(31 downto 16) when "0110",
ir(15 downto 0) when "0111",
reg1 when "1000",
reg2 when "1001",
reg3 when "1010",
reg4 when "1011",
pmem_res when "1100",
ran_nr(31 downto 16) when "1101",
std_logic_vector(progress) when "1110",
data_bus when others;
-- micro_pc
process(clk)
begin
if rising_edge(clk) then
if SEQ = "0000" then -- micro_pc += 1
micro_pc <= std_logic_vector(unsigned(micro_pc) + 1);
elsif SEQ = "0001" then -- micro_pc = op
micro_pc <= ir(31 downto 24);
elsif SEQ = "0010" then --micro_pc = mod
micro_pc <= mod_rom(to_integer(unsigned(ir(23 downto 22))));
elsif SEQ = "0011" then --micro_pc = 0
micro_pc <= "00000000";
elsif SEQ = "0100" then -- jmp
micro_pc <= MICRO_ADR;
elsif SEQ = "0101" then --jmp if Z = 1 --BEQ--
if z_flag = '0' then
micro_pc <= MICRO_ADR;
else
micro_pc <= std_logic_vector(unsigned(micro_pc) + 1);
end if;
elsif SEQ = "0110" then --jmp if N = 0 --BP--
if n_flag = '1' then
micro_pc <= MICRO_ADR;
else
micro_pc <= std_logic_vector(unsigned(micro_pc) + 1);
end if;
elsif SEQ = "0111" then --jmp if Z = 0 --BNE--
if z_flag = '1' then
micro_pc <= MICRO_ADR;
else
micro_pc <= std_logic_vector(unsigned(micro_pc) + 1);
end if;
elsif SEQ = "1000" then --check for 16 bit inst
if FETCH_NEXT = '0' then
micro_pc <= MICRO_ADR;
else
micro_pc <= std_logic_vector(unsigned(micro_pc) + 1);
end if;
elsif SEQ = "1001" then --jmp if N = 1 --BN--
if n_flag = '0' then
micro_pc <= MICRO_ADR;
else
micro_pc <= std_logic_vector(unsigned(micro_pc) + 1);
end if;
-- Jump to the interrupt micro program if there's an interrupt and
-- interrupts are enabled
elsif SEQ = "1111" then
if intr_enable = '1' then
if (reset_alert = '1') or (collision_alert = '1') or (terrain_alert = '1') then
micro_pc <= MICRO_ADR;
else
micro_pc <= std_logic_vector(unsigned(micro_pc) + 1);
end if;
else
micro_pc <= std_logic_vector(unsigned(micro_pc) + 1);
end if;
-- Fetch new instruction when returning from interrupt
elsif SEQ = "1100" then
micro_pc <= MICRO_ADR; -- MICRO_ADR will be 0
elsif SEQ = "1010" then
micro_pc <= std_logic_vector(unsigned(micro_pc) + 1);
else
micro_pc <= micro_pc;
end if;
end if;
end process;
-- alu combinatorics
alu_add <= std_logic_vector(signed(alu_res(15) & alu_res) + signed(data_bus(15) & data_bus));
alu_sub <= std_logic_vector(signed(alu_res(15) & alu_res) - signed(data_bus(15) & data_bus));
alu_not <= not data_bus;
alu_and <= alu_res and data_bus;
alu_or <= alu_res or data_bus;
alu_xor <= alu_res xor data_bus;
-- alu_res
process(clk)
begin
if rising_edge(clk) then
case ALU_OP is
when "001" => -- ADD
alu_res <= alu_add(15 downto 0);
if alu_add = "00000000000000000" then -- z_flag
z_flag <= '1';
else
z_flag <= '0';
end if;
n_flag <= alu_add(15); -- n_flag
c_flag <= alu_add(16); -- c_flag
if alu_res(15) = data_bus(15) then -- o_flag
if alu_res(15) = '0' and data_bus(15) = '0' and alu_add(15) = '1' then
o_flag <= '1';
elsif alu_res(15) = '1' and data_bus(15) = '1' and alu_add(15) = '0' then
o_flag <= '1';
else
o_flag <= '0';
end if;
else
o_flag <= '0';
end if;
when "010" => -- SUB
alu_res <= alu_sub(15 downto 0);
if alu_sub = "00000000000000000" then -- z_flag
z_flag <= '1';
else
z_flag <= '0';
end if;
n_flag <= alu_sub(15); -- n_flag
c_flag <= '0'; -- c_flag (no meaning when subtracting)
if alu_res(15) /= data_bus(15) then -- o_flag
if (alu_res(15) = '0' and data_bus(15) = '1' and alu_sub(15) = '1') then
o_flag <= '1';
elsif alu_res(15) = '1' and data_bus(15) = '0' and alu_sub(15) = '0' then
o_flag <= '1';
else
o_flag <= '0';
end if;
else
o_flag <= '0';
end if;
when "011" =>
alu_res <= alu_not; --NOT
if alu_not = "0000000000000000" then -- z_flag
z_flag <= '1';
else
z_flag <= '0';
end if;
when "100" =>
alu_res <= alu_and; --AND
if alu_and = "0000000000000000" then -- z_flag
z_flag <= '1';
else
z_flag <= '0';
end if;
n_flag <= alu_and(15);
o_flag <= '0';
c_flag <= '0';
when "101" =>
alu_res <= alu_or; --OR
if alu_or = "0000000000000000" then -- z_flag
z_flag <= '1';
else
z_flag <= '0';
end if;
n_flag <= alu_or(15);
o_flag <= '0';
c_flag <= '0';
when "110" =>
alu_res <= alu_xor; --XOR
if alu_xor = "0000000000000000" then -- z_flag
z_flag <= '1';
else
z_flag <= '0';
end if;
n_flag <= alu_xor(15);
o_flag <= '0';
c_flag <= '0';
when others =>
if FROM_BUS = "0100" then
alu_res <= data_bus;
-- Return from interrupt: restore all flags and alu_res
elsif SEQ = "1010" then
alu_res <= intr_alu_res;
z_flag <= intr_z;
n_flag <= intr_n;
o_flag <= intr_o;
c_flag <= intr_c;
else
alu_res <= alu_res;
end if;
n_flag <= n_flag;
o_flag <= o_flag;
c_flag <= c_flag;
z_flag <= z_flag;
end case;
end if;
end process;
--ran_gen
ran_bit <= new_ran(31) xor new_ran(29) xor new_ran(25) xor new_ran(24);
ran_nr <= new_ran;
process(clk)
begin
if rising_edge(clk) then
new_ran(31 downto 1) <= new_ran(30 downto 0);
new_ran(0) <= ran_bit;
end if;
end process;
end Behavioral;
| mit | 1f5f9d8f83ff49f29c1e3289cdb3c3b4 | 0.539161 | 3.392799 | false | false | false | false |
JuanMarcosRamirez/WeightedMedianDisenoLogico | misc/FPGA/otros/loopback/tope_rof512_uart.vhd | 1 | 8,195 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity tope_rof512_uart is --Entidad
Port ( tx_female : out std_logic; --Entidad
LED : out std_logic_vector(7 downto 0);
rx_female : in std_logic; --Entidad
RSTn : in std_logic; --Entidad
clk : in std_logic); --Entidad
end tope_rof512_uart; --Entidad
architecture Comportamiento of tope_rof512_uart is
component uart_tx_plus --comp uart_tx_plus
Port ( data_in : in std_logic_vector(7 downto 0);--comp uart_tx_plus
write_buffer : in std_logic; --comp uart_tx_plus
reset_buffer : in std_logic; --comp uart_tx_plus
en_16_x_baud : in std_logic; --comp uart_tx_plus
serial_out : out std_logic; --comp uart_tx_plus
buffer_data_present : out std_logic; --comp uart_tx_plus
buffer_full : out std_logic; --comp uart_tx_plus
buffer_half_full : out std_logic; --comp uart_tx_plus
clk : in std_logic); --comp uart_tx_plus
end component;
component uart_rx --comp uart_rx
Port ( serial_in : in std_logic; --comp uart_rx
data_out : out std_logic_vector(7 downto 0); --comp uart_rx
read_buffer : in std_logic; --comp uart_rx
reset_buffer : in std_logic; --comp uart_rx
en_16_x_baud : in std_logic; --comp uart_rx
buffer_data_present : out std_logic; --comp uart_rx
buffer_full : out std_logic; --comp uart_rx
buffer_half_full : out std_logic; --comp uart_rx
clk : in std_logic); --comp uart_rx
end component; --comp uart_rx
signal cambio : std_logic :='0';
signal Dfilt : std_logic_vector(7 downto 0);
signal interrupt : std_logic :='0'; --señales
signal interrupt_ack : std_logic; --señales
--señales
--señales
signal baud_count : integer range 0 to 26 :=0; --señales
signal en_16_x_baud : std_logic; --señales
signal write_to_uart : std_logic; --señales
signal tx_data_present : std_logic; --señales
signal tx_full : std_logic; --señales
signal tx_half_full : std_logic; --señales
signal read_from_uart : std_logic :='0'; --señales
signal rx_data : std_logic_vector(7 downto 0); --señales
signal rx_data_present : std_logic; --señales
signal rx_full : std_logic; --señales
signal rx_half_full : std_logic; --señales
--señales
signal previous_rx_half_full : std_logic; --señales
signal rx_half_full_event : std_logic; --señales
begin --------------------------------------------- Comienzo de procesos arquitectura y portmaps
interrupt_control: process(clk) --Control de transmisión
begin --Control de transmisión
if clk'event and clk='1' then --Control de transmisión
--Control de transmisión
-- detect change in state of the 'rx_half_full' flag. --Control de transmisión
previous_rx_half_full <= rx_half_full; --Control de transmisión
rx_half_full_event <= previous_rx_half_full xor rx_half_full;--Control de transmisión
--Control de transmisión
-- processor interrupt waits for an acknowledgement --Control de transmisión
if interrupt_ack='1' then --Control de transmisión
interrupt <= '0'; --Control de transmisión
elsif rx_half_full_event='1' then --Control de transmisión
interrupt <= '1'; --Control de transmisión
else --Control de transmisión
interrupt <= interrupt; --Control de transmisión
end if; --Control de transmisión
--Control de transmisión
end if; --Control de transmisión
end process interrupt_control; --Control de transmisión
transmit: uart_tx_plus
port map ( data_in => rx_data,
write_buffer => rx_data_present,
reset_buffer => '0',
en_16_x_baud => en_16_x_baud,
serial_out => tx_female,
buffer_data_present => tx_data_present,--Pruebo: desconectado
buffer_full => tx_full, --Pruebo: desconectado
buffer_half_full => tx_half_full, --Pruebo: desconectado
clk => clk );
receive: uart_rx
port map ( serial_in => rx_female,
data_out => rx_data,
read_buffer => read_from_uart, -- Atención:fijar read_from_uart (indica lectura en el macro)
reset_buffer => '0',
en_16_x_baud => en_16_x_baud,
buffer_data_present => rx_data_present,--Pruebo: desconectado
buffer_full => rx_full, --Pruebo: desconectado
buffer_half_full => rx_half_full, --Pruebo: desconectado
clk => clk );
LED(7) <= cambio;
LED(6) <= rx_data(6);
LED(5) <= rx_data(5);
LED(4) <= rx_data(4);
LED(3) <= rx_data(3);
LED(2) <= rx_data(2);
LED(1) <= rx_data(1);
LED(0) <= rx_data(0);
toggle: process(rx_data_present)
begin
if rx_data_present'event and rx_data_present='1' then
if cambio='0' then
cambio <= '1';
else
cambio <= '0';
end if;
else
end if;
end process toggle;
baud_timer: process(clk) --Generación de en_16_x_baud
begin --Generación de en_16_x_baud
if clk'event and clk='1' then --Generación de en_16_x_baud
if baud_count=26 then --Generación de en_16_x_baud
baud_count <= 0; --Generación de en_16_x_baud
en_16_x_baud <= '1'; --Generación de en_16_x_baud
else --Generación de en_16_x_baud
baud_count <= baud_count + 1; --Generación de en_16_x_baud
en_16_x_baud <= '0'; --Generación de en_16_x_baud
end if; --Generación de en_16_x_baud
end if; --Generación de en_16_x_baud
end process baud_timer; --Generación de en_16_x_baud
inicio: process(rx_female)
begin
if rx_female'event and rx_female='0' then
read_from_uart <= '1';
else
end if;
end process inicio;
end Comportamiento;
| gpl-3.0 | 4acf7106b088bc76a86013e99376fc59 | 0.437584 | 4.380011 | false | false | false | false |
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| gpl-3.0 | f5cf052711a52a7edec353593afd6c34 | 0.931392 | 1.897604 | false | false | false | false |
rflamino/StellaBlue | core/A2601/src/A2601Flash.vhd | 1 | 12,157 | -- A2601 Top Level Entity (Rev B Board with Flash Memory)
-- Copyright 2006, 2010 Retromaster
--
-- This file is part of A2601.
--
-- A2601 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License,
-- or any later version.
--
-- A2601 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with A2601. If not, see <http://www.gnu.org/licenses/>.
--
-- This top level entity supports many bankswitching schemes and multiple
-- game ROMs stored in on-board Flash memory. ROM properties are stored in
-- FPGA built-in SRAM (see CartTable entity). To generate the CartTable, use
-- multirom.py in util directory.,
--
-- This top level entity accepts user input from a MegaDrive/Genesis Joypad.
-- Pin names starting with p_ designate joypad input/outputs.
--
-- For more information, see the A2601 Rev B Board Schematics and project
-- website at <http://retromaster.wordpress.org/a2601>.
library std;
use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity A2601Flash is
port (clk: in std_logic;
d: in std_logic_vector(7 downto 0);
a: out std_logic_vector(18 downto 0);
oe: out std_logic;
we: out std_logic;
cv: out std_logic_vector(7 downto 0);
au: out std_logic_vector(4 downto 0);
p_l: in std_logic;
p_r: in std_logic;
p_a: in std_logic;
p_u: in std_logic;
p_d: in std_logic;
p_s: in std_logic;
p_bs: out std_logic);
end A2601Flash;
architecture arch of A2601Flash is
component a2601_dcm is
port(clkin_in: in std_logic;
rst_in: in std_logic;
clkfx_out: out std_logic;
clkin_ibufg_out: out std_logic);
end component;
component A2601 is
port(vid_clk: in std_logic;
rst: in std_logic;
d: inout std_logic_vector(7 downto 0);
a: out std_logic_vector(12 downto 0);
r: out std_logic;
pa: inout std_logic_vector(7 downto 0);
pb: inout std_logic_vector(7 downto 0);
inpt4: in std_logic;
inpt5: in std_logic;
colu: out std_logic_vector(6 downto 0);
csyn: out std_logic;
vsyn: out std_logic;
hsyn: out std_logic;
cv: out std_logic_vector(7 downto 0);
au0: out std_logic;
au1: out std_logic;
av0: out std_logic_vector(3 downto 0);
av1: out std_logic_vector(3 downto 0);
ph0_out: out std_logic;
ph1_out: out std_logic);
end component;
component ram128x8 is
port(clk: in std_logic;
r: in std_logic;
d_in: in std_logic_vector(7 downto 0);
d_out: out std_logic_vector(7 downto 0);
a: in std_logic_vector(6 downto 0));
end component;
component CartTable is
port(clk: in std_logic;
d: out std_logic_vector(10 downto 0);
c: out std_logic_vector(6 downto 0);
a: in std_logic_vector(6 downto 0));
end component;
signal vid_clk: std_logic;
signal pa: std_logic_vector(7 downto 0) := "11111111";
signal pb: std_logic_vector(7 downto 0) := "11111111";
signal inpt4: std_logic := '1';
signal inpt5: std_logic := '1';
signal colu: std_logic_vector(6 downto 0);
signal csyn: std_logic;
signal vsyn: std_logic;
signal hsyn: std_logic;
signal au0: std_logic;
signal au1: std_logic;
signal av0: std_logic_vector(3 downto 0);
signal av1: std_logic_vector(3 downto 0);
signal auv0: unsigned(4 downto 0);
signal auv1: unsigned(4 downto 0);
signal rst: std_logic := '1';
signal rst_cntr: unsigned(7 downto 0) := "00000000";
signal ph0: std_logic;
signal ph1: std_logic;
signal sc_clk: std_logic;
signal sc_r: std_logic;
signal sc_d_in: std_logic_vector(7 downto 0);
signal sc_d_out: std_logic_vector(7 downto 0);
signal sc_a: std_logic_vector(6 downto 0);
subtype bss_type is std_logic_vector(2 downto 0);
constant BANK00: bss_type := "000";
constant BANKF8: bss_type := "001";
constant BANKF6: bss_type := "010";
constant BANKFE: bss_type := "011";
constant BANKE0: bss_type := "100";
constant BANK3F: bss_type := "101";
signal bank: std_logic_vector(3 downto 0) := "0000";
signal tf_bank: std_logic_vector(1 downto 0);
signal e0_bank: std_logic_vector(2 downto 0);
signal e0_bank0: std_logic_vector(2 downto 0) := "000";
signal e0_bank1: std_logic_vector(2 downto 0) := "000";
signal e0_bank2: std_logic_vector(2 downto 0) := "000";
signal bss: bss_type;
signal sc: std_logic;
signal cpu_a: std_logic_vector(12 downto 0);
signal cpu_d: std_logic_vector(7 downto 0);
signal cpu_r: std_logic;
signal cart_info: std_logic_vector(10 downto 0) := "00000000000";
signal cart_cntr: unsigned(6 downto 0) := "0000000";
signal cart_max: std_logic_vector(6 downto 0);
signal cart_vect: std_logic_vector(6 downto 0) := "0000000";
signal cart_next: std_logic;
signal cart_prev: std_logic;
signal cart_swch: std_logic := '0';
signal cart_next_l: std_logic;
signal cart_prev_l: std_logic;
signal gsel: std_logic;
signal p_fn: std_logic;
signal res: std_logic;
signal sel: std_logic;
signal ctrl_cntr: unsigned(3 downto 0);
begin
brd_a2601_dcm: a2601_dcm
port map(clk, '0', vid_clk, open);
brd_A2601: A2601
port map(vid_clk, rst, cpu_d, cpu_a, cpu_r, pa, pb, inpt4, inpt5, colu, csyn, vsyn, hsyn, cv, au0, au1, av0, av1, ph0, ph1);
brd_CartTable: CartTable
port map(ph0, cart_info, cart_max, std_logic_vector(cart_cntr));
auv0 <= ("0" & unsigned(av0)) when (au0 = '1') else "00000";
auv1 <= ("0" & unsigned(av1)) when (au1 = '1') else "00000";
au <= std_logic_vector(auv0 + auv1);
process(ph0)
begin
if (ph0'event and ph0 = '1') then
rst_cntr <= rst_cntr + 1;
if (rst_cntr = "11111111") then
if (cart_next_l = '0') and (cart_next = '1') then
if (cart_cntr = unsigned(cart_max)) then
cart_cntr <= "0000000";
else
cart_cntr <= cart_cntr + 1;
end if;
rst <= '1';
cart_next_l <= '1';
cart_prev_l <= '1';
elsif (cart_prev_l = '0') and (cart_prev = '1') then
if (cart_cntr = "0000000") then
cart_cntr <= unsigned(cart_max);
else
cart_cntr <= cart_cntr - 1;
end if;
rst <= '1';
cart_next_l <= '1';
cart_prev_l <= '1';
else
cart_next_l <= cart_next;
cart_prev_l <= cart_prev;
end if;
elsif (rst_cntr = "10000000") then
rst <= '0';
end if;
end if;
end process;
oe <= '0';
we <= '1';
-- Controller inputs sampling
p_bs <= ctrl_cntr(3);
-- Only one controller port supported.
pa(3 downto 0) <= "1111";
inpt5 <= '1';
process(ph0)
begin
if (ph0'event and ph0 = '1') then
ctrl_cntr <= ctrl_cntr + 1;
if (ctrl_cntr = "1111") then -- p_bs
p_fn <= p_a;
pb(0) <= p_s;
elsif (ctrl_cntr = "0111") then
pa(7 downto 4) <= p_r & p_l & p_d & p_u;
inpt4 <= p_a;
gsel <= p_s;
end if;
pb(7) <= pa(7) or p_fn;
pb(6) <= pa(6) or p_fn;
pb(1) <= pa(4) or p_fn;
pb(3) <= pa(5) or p_fn;
end if;
end process;
pb(5) <= '1';
pb(4) <= '1';
pb(2) <= '1';
sc_ram128x8: ram128x8
port map(sc_clk, sc_r, sc_d_in, sc_d_out, sc_a);
-- This clock is phase shifted so that we can use Xilinx synchronous block RAM.
sc_clk <= not ph1;
sc_r <= '0' when cpu_a(12 downto 7) = "100000" else '1';
sc_d_in <= cpu_d;
sc_a <= cpu_a(6 downto 0);
-- ROM and SC output
process(cpu_a, d, sc_d_out, sc)
begin
if (cpu_a(12 downto 7) = "100001" and sc = '1') then
cpu_d <= sc_d_out;
elsif (cpu_a(12 downto 7) = "100000" and sc = '1') then
cpu_d <= "ZZZZZZZZ";
elsif (cpu_a(12) = '1') then
cpu_d <= d;
else
cpu_d <= "ZZZZZZZZ";
end if;
end process;
with cpu_a(11 downto 10) select e0_bank <=
e0_bank0 when "00",
e0_bank1 when "01",
e0_bank2 when "10",
"111" when "11",
"---" when others;
tf_bank <= bank(1 downto 0) when (cpu_a(11) = '0') else "11";
with bss select a <=
cart_vect & cpu_a(11 downto 0) when BANK00,
cart_vect(6 downto 1) & bank(0) & cpu_a(11 downto 0) when BANKF8,
cart_vect(6 downto 2) & bank(1 downto 0) & cpu_a(11 downto 0) when BANKF6,
cart_vect(6 downto 1) & bank(0) & cpu_a(11 downto 0) when BANKFE,
cart_vect(6 downto 1) & e0_bank & cpu_a(9 downto 0) when BANKE0,
cart_vect(6 downto 1) & tf_bank & cpu_a(10 downto 0) when BANK3F,
"-------------------" when others;
bankswch: process(ph0)
begin
if (ph0'event and ph0 = '1') then
if (rst = '1') then
bank <= "0000";
e0_bank0 <= "000";
e0_bank1 <= "000";
e0_bank2 <= "000";
else
case bss is
when BANKF8 =>
if (cpu_a = "1" & X"FF8") then
bank <= "0000";
elsif (cpu_a = "1" & X"FF9") then
bank <= "0001";
end if;
when BANKF6 =>
if (cpu_a = "1" & X"FF6") then
bank <= "0000";
elsif (cpu_a = "1" & X"FF7") then
bank <= "0001";
elsif (cpu_a = "1" & X"FF8") then
bank <= "0010";
elsif (cpu_a = "1" & X"FF9") then
bank <= "0011";
end if;
when BANKFE =>
if (cpu_a = "0" & X"1FE") then
bank <= "0000";
elsif (cpu_a = "1" & X"1FE") then
bank <= "0001";
end if;
when BANKE0 =>
if (cpu_a(12 downto 4) = "1" & X"FE" and cpu_a(3) = '0') then
e0_bank0 <= cpu_a(2 downto 0);
elsif (cpu_a(12 downto 4) = "1" & X"FE" and cpu_a(3) = '1') then
e0_bank1 <= cpu_a(2 downto 0);
elsif (cpu_a(12 downto 4) = "1" & X"FF" and cpu_a(3) = '0') then
e0_bank2 <= cpu_a(2 downto 0);
end if;
when BANK3F =>
--if (cpu_a(12 downto 6) = "0000000") then
if (cpu_a = "0" & X"03F") then
bank(1 downto 0) <= cpu_d(1 downto 0);
end if;
when others =>
null;
end case;
end if;
end if;
end process;
bss <= cart_info(3 downto 1);
sc <= cart_info(0);
cart_vect <= cart_info(10 downto 4);
cart_next <= (not pa(7)) and (not gsel);
cart_prev <= (not pa(6)) and (not gsel);
end arch;
| mit | 5a24768c13b49624eb106ee557f35187 | 0.505799 | 3.384465 | false | false | false | false |
rflamino/StellaBlue | core/A2601/src/altpll0.vhd | 1 | 14,834 | -- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: altpll0.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY altpll0 IS
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC
);
END altpll0;
ARCHITECTURE SYN OF altpll0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire4_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING
);
PORT (
areset : IN STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire4_bv(0 DOWNTO 0) <= "0";
sub_wire4 <= To_stdlogicvector(sub_wire4_bv);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
sub_wire2 <= inclk0;
sub_wire3 <= sub_wire4(0 DOWNTO 0) & sub_wire2;
altpll_component : altpll
GENERIC MAP (
clk0_divide_by => 1,
clk0_duty_cycle => 50,
clk0_multiply_by => 4,
clk0_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 69842,
intended_device_family => "Cyclone II",
lpm_hint => "CBX_MODULE_PREFIX=altpll0",
lpm_type => "altpll",
operation_mode => "NORMAL",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_USED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_UNUSED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_UNUSED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED"
)
PORT MAP (
areset => areset,
inclk => sub_wire3,
clk => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "57.271999"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "14.318"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "4"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "57.27200000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll0.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "4"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "69842"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
-- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
| mit | d85cfc0715ff96873e46f246faf75116 | 0.700081 | 3.366773 | false | false | false | false |
DougFirErickson/parallella-hw | fpga/ip/xilinx/fifo_async_103x32/fifo_generator_v12_0/hdl/ramfifo/wr_logic_pkt_fifo.vhd | 6 | 31,831 | `protect begin_protected
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`protect end_protected
| gpl-3.0 | 31dfd90e137a821cdc5c5149ceb0f41f | 0.946059 | 1.838561 | false | false | false | false |
dummylink/plnk_fpga-stack | Examples/xilinx_microblaze/avnet_lx9/pcores/plb_powerlink_v1_00_a/hdl/vhdl/lib/addr_decoder.vhd | 5 | 3,225 | -------------------------------------------------------------------------------
--
-- Title : addr_decoder
-- Design : plk_mn
--
-------------------------------------------------------------------------------
--
-- File : C:\my_designs\PLK_MN\plk_mn\src\lib\addr_decoder.vhd
-- Generated : Wed Jul 27 09:39:25 2011
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2011
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- 2011-07-26 V0.01 zelenkaj First version
--
-------------------------------------------------------------------------------
--{{ Section below this comment is automatically maintained
-- and may be overwritten
--{entity {addr_decoder} architecture {rtl}}
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity addr_decoder is
generic(
addrWidth_g : integer := 32;
baseaddr_g : integer := 16#1000#;
highaddr_g : integer := 16#1FFF#
);
port(
selin : in std_logic;
addr : in std_logic_vector(addrWidth_g-1 downto 0);
selout : out std_logic
);
end addr_decoder;
--}} End of automatically maintained section
architecture rtl of addr_decoder is
begin
selout <= selin when addr >= conv_std_logic_vector(baseaddr_g, addr'length) and addr <= conv_std_logic_vector(highaddr_g, addr'length) else '0';
end rtl;
| gpl-2.0 | 4ac628d8a5f7781c6df9e377ae05ebcd | 0.595659 | 4.145244 | false | false | false | false |
JuanMarcosRamirez/WeightedMedianDisenoLogico | misc/FPGA/uart_tx_plus.vhd | 5 | 5,336 | -- UART Transmitter with integral 16 byte FIFO buffer
--
-- 8 bit, no parity, 1 stop bit
--
-- Special version made 2nd November 2005 in which the data_present signal
-- was brough out as well as the half and full status signals.
--
-- Version : 1.00
-- Version Date : 14th October 2002
--
-- Start of design entry : 14th October 2002
--
-- Ken Chapman
-- Xilinx Ltd
-- Benchmark House
-- 203 Brooklands Road
-- Weybridge
-- Surrey KT13 ORH
-- United Kingdom
--
-- [email protected]
--
------------------------------------------------------------------------------------
--
-- NOTICE:
--
-- Copyright Xilinx, Inc. 2002. This code may be contain portions patented by other
-- third parties. By providing this core as one possible implementation of a standard,
-- Xilinx is making no representation that the provided implementation of this standard
-- is free from any claims of infringement by any third party. Xilinx expressly
-- disclaims any warranty with respect to the adequacy of the implementation, including
-- but not limited to any warranty or representation that the implementation is free
-- from claims of any third party. Futhermore, Xilinx is providing this core as a
-- courtesy to you and suggests that you contact all third parties to obtain the
-- necessary rights to use this implementation.
--
------------------------------------------------------------------------------------
--
-- Library declarations
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
------------------------------------------------------------------------------------
--
-- Main Entity for uart_tx_plus
--
entity uart_tx_plus is
Port ( data_in : in std_logic_vector(7 downto 0);
write_buffer : in std_logic;
reset_buffer : in std_logic;
en_16_x_baud : in std_logic;
serial_out : out std_logic;
buffer_data_present : out std_logic;
buffer_full : out std_logic;
buffer_half_full : out std_logic;
clk : in std_logic);
end uart_tx_plus;
--
------------------------------------------------------------------------------------
--
-- Start of Main Architecture for uart_tx_plus
--
architecture macro_level_definition of uart_tx_plus is
--
------------------------------------------------------------------------------------
--
-- Components used in uart_tx_plus and defined in subsequent entities.
--
------------------------------------------------------------------------------------
--
-- Constant (K) Compact UART Transmitter
--
component kcuart_tx
Port ( data_in : in std_logic_vector(7 downto 0);
send_character : in std_logic;
en_16_x_baud : in std_logic;
serial_out : out std_logic;
Tx_complete : out std_logic;
clk : in std_logic);
end component;
--
-- 'Bucket Brigade' FIFO
--
component bbfifo_16x8
Port ( data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
reset : in std_logic;
write : in std_logic;
read : in std_logic;
full : out std_logic;
half_full : out std_logic;
data_present : out std_logic;
clk : in std_logic);
end component;
--
------------------------------------------------------------------------------------
--
-- Signals used in uart_tx_plus
--
------------------------------------------------------------------------------------
--
signal fifo_data_out : std_logic_vector(7 downto 0);
signal fifo_data_present : std_logic;
signal fifo_read : std_logic;
--
------------------------------------------------------------------------------------
--
-- Start of UART_TX circuit description
--
------------------------------------------------------------------------------------
--
begin
-- 8 to 1 multiplexer to convert parallel data to serial
kcuart: kcuart_tx
port map ( data_in => fifo_data_out,
send_character => fifo_data_present,
en_16_x_baud => en_16_x_baud,
serial_out => serial_out,
Tx_complete => fifo_read,
clk => clk);
buf: bbfifo_16x8
port map ( data_in => data_in,
data_out => fifo_data_out,
reset => reset_buffer,
write => write_buffer,
read => fifo_read,
full => buffer_full,
half_full => buffer_half_full,
data_present => fifo_data_present,
clk => clk);
buffer_data_present <= fifo_data_present;
end macro_level_definition;
------------------------------------------------------------------------------------
--
-- END OF FILE uart_tx_plus.vhd
--
------------------------------------------------------------------------------------
| gpl-3.0 | f1dda3fe3c500b029259e351392019c6 | 0.479385 | 4.738899 | false | false | false | false |
estadofinito/biblioteca-vhdl | todos-los-archivos/siete_segmentos_4bits_mux.vhd | 4 | 1,612 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity siete_segmentos_4bits_mux is
PORT (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
D0 : IN STD_LOGIC_VECTOR(3 downto 0); --Primer digito.
D1 : IN STD_LOGIC_VECTOR(3 downto 0); --Segundo digito.
D2 : IN STD_LOGIC_VECTOR(3 downto 0); --Tercer digito.
D3 : IN STD_LOGIC_VECTOR(3 downto 0); --Cuarto digito.
salida: OUT STD_LOGIC_VECTOR(3 downto 0); --Salida del multiplexor (valor a desplegar).
MUX : OUT STD_LOGIC_VECTOR(3 downto 0) --Valor que define cual digito se va a mostrar.
);
end siete_segmentos_4bits_mux;
architecture Behavioral of siete_segmentos_4bits_mux is
type estados is (rst, v0, v1, v2, v3);
signal estado : estados;
begin
visualizadores: process (reset, clk) begin
if (reset = '1') then
estado <= rst;
MUX <= x"F";
salida <= "1111";
elsif rising_edge(clk) then
case estado is
when v0 =>
salida <= D3;
MUX <= "1110";
estado <= v1;
when v1 =>
salida <= D2;
MUX <= "1101";
estado <= v2;
when v2 =>
salida <= D1;
MUX <= "1011";
estado <= v3;
when others =>
salida <= D0;
MUX <= "0111";
estado <= v0;
end case;
end if;
end process;
end Behavioral;
| lgpl-2.1 | 2e58c15778524583d8104546ec659c31 | 0.470223 | 3.903148 | false | false | false | false |
DougFirErickson/parallella-hw | fpga/ip/xilinx/fifo_async_103x32/fifo_generator_v12_0/hdl/ramfifo/rd_fwft.vhd | 6 | 38,466 | `protect begin_protected
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 26736)
`protect data_block
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| gpl-3.0 | 17679d92caf283aeb4ead473312cbf51 | 0.947694 | 1.832151 | false | false | false | false |
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`protect end_protected
| gpl-3.0 | f499a49be3560f4fd7bb4e59d746ac5c | 0.953317 | 1.818304 | false | false | false | false |
JuanMarcosRamirez/WeightedMedianDisenoLogico | misc/FPGA/otros/auditoría_imagen_16x16/window_3x3_x.vhd | 1 | 10,204 | --------------------------------------------------------------------------
--
-- Autor: Jorge Márquez
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity window_3x3 is
generic (
vwidth: integer:=8
);
port (
Clk : in std_logic;
RSTn : in std_logic;
D : in std_logic_vector(vwidth-1 downto 0);
w11 : out std_logic_vector(vwidth -1 downto 0);
w12 : out std_logic_vector(vwidth -1 downto 0);
w13 : out std_logic_vector(vwidth -1 downto 0);
w21 : out std_logic_vector(vwidth -1 downto 0);
w22 : out std_logic_vector(vwidth -1 downto 0);
w23 : out std_logic_vector(vwidth -1 downto 0);
w31 : out std_logic_vector(vwidth -1 downto 0);
w32 : out std_logic_vector(vwidth -1 downto 0);
w33 : out std_logic_vector(vwidth -1 downto 0);
DV : out std_logic:='0'
);
end window_3x3;
architecture window_3x3 of window_3x3 is
component fifo_16x8x
port (
din : IN std_logic_VECTOR(7 downto 0);
wr_en : IN std_logic;
wr_clk : IN std_logic;
rd_en : IN std_logic;
rd_clk : IN std_logic;
rst : IN std_logic;
dout : OUT std_logic_VECTOR(7 downto 0);
full : OUT std_logic;
empty : OUT std_logic;
wr_data_count: OUT std_logic_VECTOR(3 downto 0));
end component;
signal a00 : std_logic_vector(vwidth-1 downto 0);
signal a11 : std_logic_vector(vwidth-1 downto 0);
signal a12 : std_logic_vector(vwidth-1 downto 0);
signal a13 : std_logic_vector(vwidth-1 downto 0);
signal a21 : std_logic_vector(vwidth-1 downto 0);
signal a22 : std_logic_vector(vwidth-1 downto 0);
signal a23 : std_logic_vector(vwidth-1 downto 0);
signal a31 : std_logic_vector(vwidth-1 downto 0);
signal a32 : std_logic_vector(vwidth-1 downto 0);
signal a33 : std_logic_vector(vwidth-1 downto 0);
--fifoa signals
signal clear : std_logic;
signal wrreqa : std_logic:='1';
signal rdreqa : std_logic:='0';
signal ofulla : std_logic;
signal oemptya : std_logic;
signal ofifoa : std_logic_vector(vwidth-1 downto 0);
signal ousedwa : std_logic_VECTOR(3 downto 0);
--fifob signals
signal wrreqb : std_logic:='0';
signal rdreqb : std_logic:='0';
signal ofullb : std_logic;
signal oemptyb : std_logic;
signal ofifob : std_logic_vector(vwidth-1 downto 0);
signal ousedwb : std_logic_VECTOR(3 downto 0);
signal dwrreqb: std_logic:='0';
-- signals for DV coordination
signal dddddddddDV: std_logic:='0';--:='0'; --9ds
signal ddddddddDV: std_logic:='0'; --8ds -- Señales
signal dddddddDV: std_logic :='0'; --04/06/08 7 ds funciona al pelo! -- Señales
signal ddddddDV: std_logic:='0';
signal dddddDV: std_logic:='0';
signal ddddDV: std_logic:='0';
signal dddDV: std_logic:='0';
signal ddDV: std_logic:='0';
signal dDV: std_logic:='0';
signal ousedwa_temp: integer:=0;
signal ousedwb_temp: integer:=0;
begin
fifoa: fifo_16x8x
port map (
din => a13,
wr_en => wrreqa,
wr_clk => Clk,
rd_en => rdreqa,
rd_clk => Clk,
rst => clear,
dout => ofifoa,
full => ofulla,
empty => oemptya,
wr_data_count => ousedwa
);
fifob: fifo_16x8x
port map (
din => a23,
wr_en => wrreqb,
wr_clk => Clk,
rd_en => rdreqb,
rd_clk => Clk,
rst => clear,
dout => ofifob,
full => ofullb,
empty => oemptyb,
wr_data_count => ousedwb
);
clear <= not(RSTn);
clock: process(Clk,RSTn)
begin
if RSTn = '0' then
a11 <= (others=>'0');
a12 <= (others=>'0');
a13 <= (others=>'0');
a21 <= (others=>'0');
a22 <= (others=>'0');
a23 <= (others=>'0');
a31 <= (others=>'0');
a32 <= (others=>'0');
a33 <= (others=>'0');
w11 <= (others=>'0');
w12 <= (others=>'0');
w13 <= (others=>'0');
w21 <= (others=>'0');
w22 <= (others=>'0');
w23 <= (others=>'0');
w31 <= (others=>'0');
w32 <= (others=>'0');
w33 <= (others=>'0');
wrreqa <= '0';
wrreqb <= '0';
-- dddddddddDV <= '0'; --9 ds
-- ddddddddDV <= '0'; -- 8 ds
-- dddddddDV <= '0'; -- 7 ds
ddddddDV <= '0';
dddddDV <= '0';
ddddDV <= '0';
dddDV <= '0';
ddDV <= '0';
dDV <= '0';
DV <= '0';
elsif rising_edge(Clk) then
a00 <= D;
a11 <= a00;
w11 <= a00;
w12 <= a11;
a12 <= a11;
w13 <= a12;
a13 <= a12;
w21 <= ofifoa;
a21 <= ofifoa;
w22 <= a21;
a22 <= a21;
w23 <= a22;
a23 <= a22;
w31 <= ofifob;
a31 <= ofifob;
w32 <= a31;
a32 <= a31;
w33 <= a32;
a33 <= a32;
wrreqa <= '1';
wrreqb <= dwrreqb;
ddddddDV <= dddddddDV; --04/06/08
dddddDV <= ddddddDV;
ddddDV <= dddddDV;
dddDV <= ddddDV;
ddDV <= dddDV;
dDV <= ddDV;
DV <= dDV;
end if;
end process;
req: process(Clk)
begin
if rising_edge(Clk) then
if ousedwa = "1010" then
rdreqa <= '1';
dwrreqb <= '1';
end if;
if ousedwb = "1010" then
rdreqb <= '1';
dddddddDV <= '1'; --04/06/08 ds
end if;
end if;
end process;
end window_3x3;
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| gpl-3.0 | 9cf46de3d96a56ca2ea32b187f94e6f7 | 0.943043 | 1.849265 | false | false | false | false |
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`protect end_protected
| gpl-3.0 | 42bb6f391849bda1aa0ebdf122757688 | 0.936581 | 1.852054 | false | false | false | false |
dummylink/plnk_fpga-stack | Examples/xilinx_microblaze/avnet_lx9/pcores/plb_powerlink_v1_00_a/hdl/vhdl/openMAC_DMAFifo_Xilinx/fifo_write.vhd | 2 | 5,316 | ------------------------------------------------------------------------------------------------------------------------
-- write controller of the fifo
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Note: A general implementation of a asynchronous fifo which is
-- using a dual port ram. This file is the write controler.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2011-09-22 V0.01 mairt first version
-- 2011-10-14 V0.02 zelenkaj element calculation buggy
------------------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fifo_write_ctrl is
generic(N: natural:=4);
port(
clkw, resetw: in std_logic;
wr: in std_logic;
r_ptr_in: in std_logic_vector(N downto 0);
w_full: out std_logic;
w_empty: out std_logic;
w_ptr_out: out std_logic_vector(N downto 0);
w_addr: out std_logic_vector(N-1 downto 0);
w_elements: out std_logic_vector(N-1 downto 0)
);
end fifo_write_ctrl;
architecture gray_arch of fifo_write_ctrl is
signal w_ptr_reg, w_ptr_next: std_logic_vector(N downto 0);
signal r_ptr_reg, r_ptr_next : std_logic_vector(N downto 0) := (others => '0');
signal gray1, bin, bin1: std_logic_vector(N downto 0);
signal waddr_all: std_logic_vector(N-1 downto 0);
signal waddr_msb, raddr_msb: std_logic;
signal full_flag, empty_flag: std_logic;
signal w_elements_wr, w_elements_rd, w_elements_diff : std_logic_vector(N downto 0);
signal w_elements_reg, w_elements_next : std_logic_vector(N-1 downto 0);
begin
-- register
process(clkw,resetw)
begin
if (resetw='1') then
w_ptr_reg <= (others=>'0');
--r_ptr_reg <= (others => '0');
w_elements_reg <= (others => '0');
elsif (clkw'event and clkw='1') then
w_ptr_reg <= w_ptr_next;
--r_ptr_reg <= r_ptr_next;
w_elements_reg <= w_elements_next;
end if;
end process;
-- (N+1)-bit Gray counter
bin <= w_ptr_reg xor ('0' & bin(N downto 1));
bin1 <= std_logic_vector(unsigned(bin) + 1);
gray1 <= bin1 xor ('0' & bin1(N downto 1));
-- update write pointer
w_ptr_next <= gray1 when wr='1' and full_flag='0' else
w_ptr_reg;
-- save read pointer
r_ptr_next <= r_ptr_in;
-- N-bit Gray counter
waddr_msb <= w_ptr_reg(N) xor w_ptr_reg(N-1);
waddr_all <= waddr_msb & w_ptr_reg(N-2 downto 0);
-- check for FIFO full and empty
raddr_msb <= r_ptr_in(N) xor r_ptr_in(N-1);
full_flag <=
'1' when r_ptr_in(N) /=w_ptr_reg(N) and
r_ptr_in(N-2 downto 0)=w_ptr_reg(N-2 downto 0) and
raddr_msb = waddr_msb else
'0';
empty_flag <=
'1' when r_ptr_in(N) =w_ptr_reg(N) and
r_ptr_in(N-2 downto 0)=w_ptr_reg(N-2 downto 0) and
raddr_msb = waddr_msb else
'0';
-- convert gray value to bin and obtain difference
w_elements_wr <= bin;
w_elements_rd <= r_ptr_in xor ('0' & w_elements_rd(N downto 1));
w_elements_diff <= std_logic_vector(unsigned(w_elements_wr) - unsigned(w_elements_rd));
w_elements_next <= w_elements_diff(w_elements_next'range);
-- output
w_addr <= waddr_all;
w_ptr_out <= w_ptr_reg;
w_elements <= w_elements_reg;
w_full <= full_flag;
w_empty <= empty_flag;
end gray_arch; | gpl-2.0 | 039d3e7116ec5c5dab71bc8fc49a572d | 0.579759 | 3.587045 | false | false | false | false |
DougFirErickson/parallella-hw | fpga/ip/xilinx/fifo_async_103x32/fifo_generator_v12_0/hdl/ramfifo/rd_status_flags_ss.vhd | 6 | 20,269 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13264)
`protect data_block
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`protect end_protected
| gpl-3.0 | afa201c8a113de2111d52236402ca203 | 0.940056 | 1.856476 | false | false | false | false |
hgunicamp/Mips8B | src_test/tests/simulacoes/test_Mips_Processor-add.vhdl | 1 | 5,824 | -- Teste geral para a estrutura do Processador Mips8B
Library Ieee;
Use Ieee.Std_Logic_1164.all;
Use Ieee.Numeric_Std.all;
Entity test_processor is
End Entity test_processor;
Architecture test_general of test_processor is
Component Mips8B is
Port(Reset_n: In Std_Logic;
Clock: In Std_Logic;
MAddr: Out Std_Logic_Vector(7 downto 0);
MCmd: Out Std_Logic_Vector(1 downto 0);
MData: Out Std_Logic_Vector(7 downto 0);
SData: In Std_Logic_Vector(7 downto 0);
SCmdAccept: In Std_Logic);
End Component Mips8B;
Type Memory_Array is Array(Natural Range <>) of Std_Logic_Vector(7 downto 0);
Use Work.MIPS8B_Base.ocpIDLE_little;
Use Work.MIPS8B_Base.ocpWR_little;
Use Work.MIPS8B_Base.ocpRD_little;
Use Work.MIPS8B_Base.ocpNULL_little;
Use Work.MIPS8B_Base.ocpDVA_little;
Signal Reset_n: Std_Logic;
Signal Clock: Std_Logic := '0';
Signal Clock_Mem: Std_Logic := '0';
Signal MAddr: Std_Logic_Vector(7 downto 0);
Signal MCmd: Std_Logic_Vector(1 downto 0);
Signal MData: Std_Logic_Vector(7 downto 0);
Signal SData: Std_Logic_Vector(7 downto 0);
Signal SCmdAccept: Std_Logic;
Begin
Reset_n <= '1', '0' after 20 ns, '1' after 40 ns;
Clock <= not Clock after 10 ns;
Clock_Mem <= not Clock_Mem after 15 ns;
Memory: Process
Variable int_SCmdAccept: Std_Logic;
Variable address: Unsigned(7 downto 0);
Variable mem_int: Memory_Array(0 to 255) := (
"00100000", "00000001", "00000000", "10000000",
"00100000", "00000010", "00000000", "10110100",
"00100000", "00000011", "00000000", "01111111",
"00100000", "00000100", "00000000", "11111111",
"00100000", "00000101", "00000000", "00110101",
"00100000", "00000110", "00000000", "01000000",
"00100000", "00000111", "00000000", "01001000",
"00000000", "00100010", "00111000", "00100000",
"00000000", "01100100", "00110000", "00100000",
"00000000", "11000111", "00101000", "00100000",
"00000000", "11100001", "00100000", "00100000",
"00000000", "11000010", "00011000", "00100000",
"00000000", "10100011", "00010000", "00100000",
"00000000", "10000101", "00001000", "00100000",
"00000000", "00100010", "00000000", "00100000",
"00000000", "01100100", "00000000", "00100000",
"00000000", "10100110", "00000000", "00100000",
"00000000", "00000000", "00000000", "00100000",
"00000000", "00100001", "00000000", "00100000",
"00000000", "11100111", "00000000", "00100000",
"00000000", "00100000", "00111000", "00100000",
"00000000", "01000000", "00110000", "00100000",
"00000000", "01100000", "00101000", "00100000",
"00000000", "11100000", "00100000", "00100000",
"00000000", "10000000", "00011000", "00100000",
"00000000", "10100000", "00010000", "00100000",
"00000000", "11000000", "00001000", "00100000",
"00000000", "11100001", "00111000", "00100000",
"00000000", "11000010", "00110000", "00100000",
"00000000", "10100011", "00101000", "00100000",
"00000000", "10000111", "00100000", "00100000",
"00000000", "01100100", "00011000", "00100000",
"00000000", "01000101", "00010000", "00100000",
"00000000", "00100110", "00001000", "00100000",
"00000000", "11100000", "00111000", "00100000",
"00000000", "11000000", "00110000", "00100000",
"00000000", "10100000", "00101000", "00100000",
"00000000", "10000000", "00100000", "00100000",
"00000000", "01100000", "00011000", "00100000",
"00000000", "01000000", "00010000", "00100000",
"00000000", "00100000", "00001000", "00100000",
"00000000", "00000000", "00111000", "00100000",
"00000000", "00000000", "00110000", "00100000",
"00000000", "00000000", "00101000", "00100000",
"00000000", "00000000", "00100000", "00100000",
"00000000", "00000000", "00011000", "00100000",
"00000000", "00000000", "00010000", "00100000",
"00000000", "00000000", "00001000", "00100000",
Others => "00000000");
Begin
Wait Until Clock_Mem'Event and Clock_Mem='1';
Case MCmd is
When ocpWR_little =>
If int_SCmdAccept = ocpNULL_little then
int_SCmdAccept := ocpDVA_little;
address := Unsigned(MAddr);
mem_int(to_integer(address)) := MData;
Else
int_SCmdAccept := ocpNULL_little;
End If;
SData <= "ZZZZZZZZ";
When ocpRD_little =>
If int_SCmdAccept = ocpNULL_little then
int_SCmdAccept := ocpDVA_little;
address := Unsigned(MAddr);
SData <= mem_int(to_integer(address));
Else
int_SCmdAccept := ocpNULL_little;
End If;
When Others =>
int_SCmdAccept := ocpNULL_little;
SData <= "ZZZZZZZZ";
End Case;
SCmdAccept <= int_SCmdAccept;
End Process Memory;
DUV: Mips8B
Port Map( Reset_n => Reset_n,
Clock => Clock,
MAddr => MAddr,
MCmd => MCmd,
MData => MData,
SData => SData,
SCmdAccept => SCmdAccept);
End Architecture test_general;
Configuration general_test of test_processor is
For test_general
For DUV: Mips8B Use Configuration Work.Mips8B_struct_conf;
End For;
End For;
End Configuration general_test;
| unlicense | 4cbc02fb341fab911dc15f4ca7c4ae51 | 0.561985 | 3.924528 | false | true | false | false |
DougFirErickson/parallella-hw | fpga/ip/xilinx/fifo_async_103x32/fifo_generator_v12_0/hdl/ramfifo/rd_dc_as.vhd | 6 | 10,777 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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| gpl-3.0 | f6f1cff4a3c0032476261b5d76fc590a | 0.925582 | 1.91523 | false | false | false | false |
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`protect end_protected
| gpl-3.0 | d8f91d74f54f9c97cd2785fb0b920060 | 0.953786 | 1.81626 | false | false | false | false |
dskntIndustry/Hardware | hdl_library/CommonFunctions/MathHelpers.vhd | 1 | 3,248 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
package MathHelpers is
function log2(A : integer) return integer;
function isPow2(A : integer) return boolean;
function max(A, B : integer) return integer;
function max(A, B : std_logic_vector) return std_logic_vector;
function min(A, B : integer) return integer;
function min(A, B : std_logic_vector) return std_logic_vector;
function abs_std_logic_vector(arg: std_logic_vector) return std_logic_vector;
end package MathHelpers;
package body MathHelpers is
function log2(A : integer) return integer is
begin
for I in 1 to 30 loop
if (2**I >= A) then
return(I);
end if;
end loop;
return(30);
end function log2;
-------------------------------------------------------------------------------
-- return true if an integer nuber is a power of 2
function isPow2(x : integer) return boolean is
begin
-- Works for up to 32 bit integers
if
x = 1 or x = 2 or x = 4 or x = 8 or x = 16 or x = 32 or
x = 64 or x = 128 or x = 256 or x = 512 or x = 1024 or
x = 2048 or x = 4096 or x = 8192 or x = 16384 or
x = 32768 or x = 65536 or x = 131072 or x = 262144 or
x = 524288 or x = 1048576 or x = 2097152 or
x = 4194304 or x = 8388608 or x = 16777216 or
x = 33554432 or x = 67108864 or x = 134217728 or
x = 268435456 or x = 536870912 or x = 1073741824
then
report "Argument is a power of 2" severity NOTE;
return true;
else
report "Argument is not a power of 2" severity NOTE;
return false;
end if;
end function isPow2;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
function max(A, B : integer) return integer is
begin
if B > A then
return B;
end if;
return A;
end function max;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
function max(A, B : std_logic_vector) return std_logic_vector is
begin
if B > A then
return B;
end if;
return A;
end function max;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
function min(A, B : integer) return integer is
begin
if B > A then
return A;
end if;
return B;
end function min;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
function min(A, B : std_logic_vector) return std_logic_vector is
begin
if B > A then
return A;
end if;
return B;
end function min;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
function abs_std_logic_vector(arg: std_logic_vector) return std_logic_vector is
variable Result: signed(arg'length-1 downto 0);
begin
Result := signed(arg);
if Result(Result'left) = '1' then
Result := -Result;
end if;
return std_logic_vector(Result);
end function;
end package body MathHelpers; | gpl-3.0 | 4effd57e7dc69e45efb1d5fbd5855dde | 0.492611 | 3.875895 | false | false | false | false |
dummylink/plnk_fpga-stack | Examples/xilinx_microblaze/avnet_lx9/pcores/plb_powerlink_v1_00_a/hdl/vhdl/lib/req_ack.vhd | 5 | 3,613 | -------------------------------------------------------------------------------
--
-- Title : req_ack
-- Design : plk_mn
--
-------------------------------------------------------------------------------
--
-- File : C:\my_designs\PLK_MN\plk_mn\src\lib\req_ack.vhd
-- Generated : Mon Aug 1 15:58:57 2011
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2011
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- 2011-08-01 V0.01 zelenkaj First version
-- 2011-11-30 V0.02 zelenkaj removed enable at ack output
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
USE ieee.math_real.log2;
USE ieee.math_real.ceil;
entity req_ack is
generic(
ack_delay_g : integer := 1;
zero_delay_g : boolean := false
);
port(
clk : in std_logic;
rst : in std_logic;
enable : in std_logic;
ack : out std_logic
);
end req_ack;
architecture rtl of req_ack is
constant iMaxCnt : integer := ack_delay_g;
constant iMaxCntLog2 : integer := integer(ceil(log2(real(iMaxCnt))));
signal cnt, cnt_next : std_logic_vector(iMaxCntLog2 downto 0);
signal cnt_tc : std_logic;
begin
genDelay : if zero_delay_g = false generate
theCnter : process(clk, rst)
begin
if rst = '1' then
cnt <= (others => '0');
elsif clk = '1' and clk'event then
cnt <= cnt_next;
end if;
end process;
cnt_next <= cnt + 1 when enable = '1' and cnt_tc /= '1' else (others => '0');
cnt_tc <= '1' when cnt = iMaxCnt else '0';
ack <= cnt_tc;
end generate;
genNoDelay : if zero_delay_g = true generate
ack <= enable;
end generate;
end rtl;
| gpl-2.0 | 8241e3d48c7fe007e33f42f34c6bbf44 | 0.586216 | 3.751817 | false | false | false | false |
Monash-2015-Ultrasonic/Logs | Final System Code/SYSTEMV3/Source/IP/FIR/FIR_sim/FIR_tb.vhd | 1 | 15,775 | -- ================================================================================
-- Legal Notice: Copyright (C) 1991-2009 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera. Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors. No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
-- ================================================================================
--
-- Generated by: FIR Compiler II 13.0
-- Generated on: 10/21/2015 00:24:41
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
entity FIR_tb is
--START MEGAWIZARD INSERT CONSTANTS
constant FIR_INPUT_FILE_c : string := "FIR_input.txt";
constant FIR_OUTPUT_FILE_c : string := "FIR_output.txt";
constant PHYSCHANIN_c : natural := 1;
constant PHYSCHANOUT_c : natural := 1;
constant INWIDTH_c : natural := 13;
constant OUTWIDTH_c : natural := 30;
constant BANKINWIDTH_c : natural := 3;
constant BANKCOUNT_c : natural := 5;
constant DATA_WIDTH_c : natural := (INWIDTH_c+BANKINWIDTH_c) * PHYSCHANIN_c;
constant OUT_WIDTH_c : natural := OUTWIDTH_c * PHYSCHANOUT_c;
constant NUM_OF_CHANNELS_c : natural := 1;
constant CHANSPERPHYIN_c : natural := 1;
constant CHANSPERPHYOUT_c : natural := 1;
constant LOG2_CHANSPERPHYOUT_c : natural := 1;
constant TDM_FACTOR_c : natural := 257;
constant INVERSE_TDM_FACTOR_c : natural := 1;
constant INVALID_CYCLES_c : natural := 256;
constant INTERP_FACTOR_c : natural := 1;
constant TOTAL_INCHANS_ALLOWED : natural := PHYSCHANIN_c * CHANSPERPHYIN_c;
constant TOTAL_OUTCHANS_ALLOWED : natural := PHYSCHANOUT_c * CHANSPERPHYOUT_c;
constant NUM_OF_TAPS_c : natural := 65;
constant TOTAL_EFF_COEF_c : natural := 325;
constant COEFF_BIT_WIDTH_c : natural := 10;
constant COEFF_BUS_DATA_WIDTH_c : natural := 16;
--END MEGAWIZARD INSERT CONSTANTS
end entity FIR_tb;
--library work;
--library auk_dspip_lib;
-------------------------------------------------------------------------------
architecture rtl of FIR_tb is
signal ast_sink_data : std_logic_vector (DATA_WIDTH_c-1 downto 0) := (others => '0');
signal ast_source_data : std_logic_vector (OUT_WIDTH_c-1 downto 0);
signal ast_sink_error : std_logic_vector (1 downto 0) := (others => '0');
signal ast_source_error : std_logic_vector (1 downto 0);
signal ast_sink_valid : std_logic := '0';
signal ast_source_valid : std_logic;
signal ast_source_ready : std_logic := '0';
signal clk : std_logic := '0';
signal reset_testbench : std_logic := '1';
signal reset_design : std_logic;
signal eof : std_logic;
signal sink_completed : std_logic := '0';
signal ast_sink_ready : std_logic;
signal cnt : natural range 0 to CHANSPERPHYIN_c;
signal push_counter : natural range 0 to CHANSPERPHYIN_c :=0;
constant tclk : time := 10 ns;
constant time_lapse_max : time := 60 us;
signal time_lapse : time;
signal valid_cycles : std_logic := '1';
function div_ceil(a : natural; b : natural) return natural is
variable res : natural := a/b;
begin
if res*b /= a then
res := res +1;
end if;
return res;
end div_ceil;
begin
DUT : entity work.FIR
port map (
clk => clk,
reset_n => reset_design,
ast_sink_data => ast_sink_data,
ast_source_data => ast_source_data,
ast_sink_valid => ast_sink_valid,
ast_source_valid => ast_source_valid,
ast_sink_error => ast_sink_error,
ast_source_error => ast_source_error);
-- for example purposes, the ready signal is always asserted.
ast_source_ready <= '1';
ast_sink_ready <= '1';
-- no input error
ast_sink_error <= (others => '0');
-----------------------------------------------------------------------------------------------
-- Read input data from file
-----------------------------------------------------------------------------------------------
source_model : process(clk) is
file in_file : text open read_mode is FIR_INPUT_FILE_c;
variable data_in : integer;
variable bank_in : integer;
variable indata : line;
variable read_data_completed: integer;
variable q, j, j_temp : integer := 0 ;
variable realInChansCount : integer ;
variable totalInChansCount : integer ;
variable idle_cyles : integer := 0 ;
type In_2D is array (PHYSCHANIN_c-1 downto 0, CHANSPERPHYIN_c-1 downto 0) of integer;
variable arrayIn : In_2D;
variable arrayBank : In_2D;
--Debug
variable my_line : line;
begin
if rising_edge(clk) then
if(reset_testbench = '0') then
ast_sink_data <= std_logic_vector(to_signed(0, DATA_WIDTH_c)) after tclk/4;
ast_sink_valid <= '0' after tclk/4;
eof <= '0';
realInChansCount := NUM_OF_CHANNELS_c * INVERSE_TDM_FACTOR_c;
totalInChansCount := TOTAL_INCHANS_ALLOWED;
else
if (sink_completed='0' or eof='0') then
eof <= '0';
if( valid_cycles = '1' and ast_sink_ready = '1') then
if not endfile(in_file) then
if (push_counter=0) then
q := 0;
for k in 0 to PHYSCHANIN_c-1 loop
-- Super-Sample Rate
if (k /= 0) then
j := j + INVERSE_TDM_FACTOR_c;
if (j > PHYSCHANIN_c - 1) then
j_temp := j_temp + 1;
j := j_temp;
end if;
else
j := k;
end if;
for i in 0 to CHANSPERPHYIN_c-1 loop
totalInChansCount := totalInChansCount - 1;
if (realInChansCount > 0) then
realInChansCount := realInChansCount - 1;
readline(in_file, indata);
read(indata, data_in);
arrayIn(j,i) := data_in;
if (BANKINWIDTH_c > 0) then
read(indata, bank_in);
arrayBank(j,i) := bank_in;
end if;
ast_sink_valid <= '1' after tclk/4;
--Debug
write(my_line, string'(" j = "));
write(my_line, j);
write(my_line, string'(" i = "));
write(my_line, i);
write(my_line, string'(" Array content = "));
write(my_line, arrayIn(j,i));
writeline(output, my_line);
end if;
end loop;
if (totalInChansCount = 0) then
realInChansCount := NUM_OF_CHANNELS_c * INVERSE_TDM_FACTOR_c;
totalInChansCount := TOTAL_INCHANS_ALLOWED;
end if;
end loop;
j_temp := 0;
sink_completed <= '0';
read_data_completed := 1;
end if;
else
eof <='1';
end if;
-- Reorder the input format
-- Expected input format by FIR Compiler II
-- ..., <C2>, <C1>, <C0>, -->
-- ..., <C5>, <C4>, <C3>, -->
-- ..., <C8>, <C7>, <C6>, -->
if (read_data_completed = 1) then
for p in 0 to PHYSCHANIN_c-1 loop
--Debug
write(my_line, string'(" Push input = "));
write(my_line,arrayIn(p,q));
writeline(output, my_line); -- write to display
ast_sink_data(p*(INWIDTH_c+BANKINWIDTH_c)+INWIDTH_c-1 downto (INWIDTH_c+BANKINWIDTH_c)*p) <= std_logic_vector(to_signed(arrayIn(p,q), INWIDTH_c)) after tclk/4;
if (BANKINWIDTH_c > 0) then
ast_sink_data(p*(INWIDTH_c+BANKINWIDTH_c)+(INWIDTH_c+BANKINWIDTH_c)-1 downto (INWIDTH_c+BANKINWIDTH_c)*p+INWIDTH_c) <= std_logic_vector(to_signed(arrayBank(p,q), BANKINWIDTH_c)) after tclk/4;
end if;
end loop;
if ( q < CHANSPERPHYIN_c ) then
q := q + 1;
else
q := 0;
end if;
if ( push_counter < CHANSPERPHYIN_c-1 ) then
push_counter <= push_counter + 1;
else
push_counter <= 0;
read_data_completed := 0;
sink_completed <= '1';
--start invalid cycles if needed
if ( idle_cyles < INVALID_CYCLES_c ) then
valid_cycles <= '0' ;
end if;
end if;
end if;
-- End Reordering and sinking data
else
if ( idle_cyles < INVALID_CYCLES_c ) then
ast_sink_valid <= '0' after tclk/4;
idle_cyles := idle_cyles + 1;
if ( idle_cyles = INVALID_CYCLES_c ) then
valid_cycles <= '1' ;
idle_cyles := 0;
end if;
end if;
ast_sink_data <= ast_sink_data after tclk/4;
end if;
else
eof <= '1';
ast_sink_valid <= '0' after tclk/4;
ast_sink_data <= std_logic_vector(to_signed(0, DATA_WIDTH_c)) after tclk/4;
end if;
end if;
end if;
end process source_model;
---------------------------------------------------------------------------------------------
-- Write FIR output to file
---------------------------------------------------------------------------------------------
sink_model : process(clk) is
file ro_file : text open write_mode is FIR_OUTPUT_FILE_c;
variable rdata : line;
variable y,z,z_temp : integer :=0;
variable realOutChansCount : natural := NUM_OF_CHANNELS_c * INVERSE_TDM_FACTOR_c;
variable totalOutChansCount : natural := TOTAL_OUTCHANS_ALLOWED;
type Out_2D is array (CHANSPERPHYOUT_c-1 downto 0, PHYSCHANOUT_c-1 downto 0) of integer;
variable arrayOut : Out_2D;
begin
if rising_edge(clk) then
if(ast_source_valid = '1' and ast_source_ready = '1') then
-- Expected output format from FIR Compiler II
--> <C0>, <C1>, <C2>, ...
--> <C3>, <C4>, <C5>, ...
--> <C6>, <C7>, <C8>, ...
for x in 0 to PHYSCHANOUT_c-1 loop
-- Super-Sample Rate or Interpolation with TDM = 1
-- only interpolation factor is needed for super-sample rate test
if ( PHYSCHANOUT_c > NUM_OF_CHANNELS_c ) then
if (x /= 0) then
z := z + INVERSE_TDM_FACTOR_c * div_ceil(INTERP_FACTOR_c,TDM_FACTOR_c);
if (z > PHYSCHANOUT_c-1) then
z_temp := z_temp + 1;
z := z_temp;
end if;
end if;
else
z := x;
end if;
arrayOut(y,x) := to_integer(signed(ast_source_data(z*OUTWIDTH_c+OUTWIDTH_c-1 downto OUTWIDTH_c*z)));
end loop;
if (y < CHANSPERPHYOUT_c - 1) then
y := y + 1;
else
y := 0;
z := 0;
z_temp := 0;
for n in 0 to PHYSCHANOUT_c-1 loop
for m in 0 to CHANSPERPHYOUT_c-1 loop
totalOutChansCount := totalOutChansCount - 1;
if (realOutChansCount > 0) then
if (NUM_OF_CHANNELS_c > PHYSCHANOUT_c) then
realOutChansCount := realOutChansCount - 1;
end if;
write(rdata, arrayOut(m,n));
writeline(ro_file, rdata);
end if;
end loop;
end loop;
end if;
if (totalOutChansCount = 0) then
realOutChansCount := NUM_OF_CHANNELS_c * INVERSE_TDM_FACTOR_c;
totalOutChansCount := TOTAL_OUTCHANS_ALLOWED;
end if;
end if;
end if;
end process sink_model;
-------------------------------------------------------------------------------
-- clock generator
-------------------------------------------------------------------------------
clkgen : process
begin -- process clkgen
if eof = '1' and sink_completed = '1' and ast_source_valid = '0' then
clk <= '0';
assert FALSE
report "NOTE: Stimuli ended" severity note;
wait;
elsif time_lapse >= time_lapse_max then
clk <= '0';
assert FALSE
report "ERROR: Reached time_lapse_max without activity, probably simulation is stuck!" severity Error;
wait;
else
clk <= '0';
wait for tclk/2;
clk <= '1';
wait for tclk/2;
end if;
end process clkgen;
monitor_toggling_activity : process(clk, reset_testbench,
ast_source_data, ast_source_valid)
begin
if reset_testbench = '0' then
time_lapse <= 0 ns;
elsif ast_source_data'event or ast_source_valid'event then
time_lapse <= 0 ns;
elsif rising_edge(clk) then
if time_lapse < time_lapse_max then
time_lapse <= time_lapse + tclk;
end if;
end if;
end process monitor_toggling_activity;
-------------------------------------------------------------------------------
-- reset generator
-------------------------------------------------------------------------------
reset_testbench_gen : process
begin -- process resetgen
reset_testbench <= '1';
wait for tclk/4;
reset_testbench <= '0';
wait for tclk*2;
reset_testbench <= '1';
wait;
end process reset_testbench_gen;
reset_design_gen : process
begin -- process resetgen
reset_design <= '1';
wait for tclk/4;
reset_design <= '0';
wait for tclk*2;
reset_design <= '1';
wait for tclk*80;
reset_design <= '1';
wait for tclk*65*2;
reset_design <= '1';
wait;
end process reset_design_gen;
end architecture rtl;
| gpl-2.0 | 206f4765e024b2fdbc1c4ad57acb0e82 | 0.500222 | 4.052145 | false | false | false | false |
estadofinito/biblioteca-vhdl | todos-los-archivos/metronomo.vhd | 2 | 3,685 | ----------------------------------------------------------------------------------
-- Compañía: Estado Finito
-- Ingeniero: Carlos Ramos
--
-- Fecha de creación: 2014/04/24 18:34:19
-- Nombre del módulo: metronomo - Behavioral
-- Comentarios adicionales:
-- Este divisor de frecuencia toma sus valores de una memoria ROM que contiene
-- los valores de los contadores. Por lo tanto, el rango de frecuencias depende
-- de la ROM.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity metronomo is
PORT (
clk : in STD_LOGIC; -- Reloj de entrada de 50MHz.
reset : in STD_LOGIC; -- Señal de reset.
btn_inc : in STD_LOGIC; -- Incrementa la cantidad de BPM.
btn_dec : in STD_LOGIC; -- Decrementa la cantidad de BPM.
d7s : out STD_LOGIC_VECTOR(7 downto 0);
MUX : out STD_LOGIC_VECTOR(3 downto 0);
clk_out : out STD_LOGIC -- Reloj de salida.
);
end metronomo;
architecture Behavioral of metronomo is
-- Señal para comunicación entre ROM y divisor con ROM.
signal escala: STD_LOGIC_VECTOR(27 downto 0);
-- Señal para el reloj de 3.125MHz (como entrada a divisor con ROM).
signal clk3M125: STD_LOGIC := '0';
-- Señal para el reloj de 5Hz (como entrada al contador).
signal clk5Hz: STD_LOGIC := '0';
-- Bit para habilitar, o no, la lectura de la ROM.
signal rom_en: STD_LOGIC := '0';
-- Señal para almacenar la dirección a leer de la ROM.
signal direccion: STD_LOGIC_VECTOR(8 downto 0);
-- Señal para almacenar la cantidad de BPM.
signal bpm: STD_LOGIC_VECTOR(8 downto 0);
-- Señal para pasar un número binario a BCD.
signal num_bcd: STD_LOGIC_VECTOR(10 downto 0);
-- Dígitos BCD para ser mostrados como siete segmentos.
signal D0, D1, D2, D3: STD_LOGIC_VECTOR(3 downto 0);
begin
-- Reloj de 3.125MHz, que será la entrada para el divisor
-- de frecuencia implementado con la ROM.
clk3M125Hz_i: entity work.clk3M125Hz(Behavioral)
PORT MAP(clk, reset, clk3M125);
-- Reloj de 200Hz, que será la entrada al contador (para evitar un
-- conteo súper rápido que no se ve).
clk5Hz_i: entity work.clk5Hz(Behavioral)
PORT MAP(clk, reset, clk5Hz);
-- Contador de 0 a 499, con valor inicial en 59 (equivalente en
-- este sistema a 60BPM), que apunta a la dirección ROM.
contador_dir_i: entity work.contador_up_down_0_499(Behavioral)
PORT MAP(clk5Hz, reset, btn_inc, btn_dec, direccion);
-- Divisor de frecuencia que entrega una salida de 1 a 512
-- pulsos por minuto, según la dirección de la ROM.
-- En general: BPM = DIRECCION + 1.
clk_rom_i: entity work.clk_rom(Behavioral)
PORT MAP(clk3M125, reset, escala, clk_out);
rom512_28b_i: entity work.rom512_28b(Behavioral)
PORT MAP(clk, rom_en, direccion, escala);
-- Convertidor de binario a BCD a siete segmentos.
-- Se encarga de recibir la cantidad de BPM en binario,
-- convertirla a tres dígitos en BCD, y enviar esos datos
-- a los visualizadores de siete segmentos.
bin2bcd9_i: entity bin2bcd9(Behavioral)
PORT MAP(bpm, num_bcd);
d7s_i: entity work.siete_segmentos_4bits_completo(Behavioral)
PORT MAP(clk, reset, D0, D1, D2, D3, d7s, MUX);
-- La cantidad de BPM es igual a la dirección más uno.
bpm <= direccion + 1;
-- La ROM está habilitada siempre y cuando no esté en reset.
rom_en <= NOT reset;
-- Se asignan las señales que representarán los datos en siete segmentos.
D3 <= "0000";
D2 <= "0" & num_bcd(10 downto 8);
D1 <= num_bcd(7 downto 4);
D0 <= num_bcd(3 downto 0);
end Behavioral; | lgpl-2.1 | ad793927d507620962952c4f7c4762c3 | 0.646608 | 3.261374 | false | false | false | false |
hgunicamp/Mips8B | src_design/mips8b_datapath.vhdl | 1 | 7,624 | Library Ieee;
Use Ieee.Std_Logic_1164.all;
Entity Mips8B_DataPath is
Generic( N: Natural := 8;
RF_SIZE: Natural := 8;
SH_SIZE: Natural := 3;
RF_ADDR_SIZE: Natural := 3);
Port(clock: in Std_Logic;
-- Controle dos Registradores do Shift Register.
en_Reg_SH: in Std_Logic;
-- Controle para Shifter.
crt_SH: in Std_Logic_Vector(1 downto 0);
S_SH: in Std_Logic_Vector(SH_SIZE-1 downto 0);
-- Controle dos Registradores da ULA.
en_R1A_ULA: in Std_Logic;
en_R1B_ULA: in Std_Logic;
en_R2_ULA: in Std_Logic;
-- Controle para ULA.
crt_ULA: in Std_Logic_Vector(2 downto 0);
crt_Mux_ULA: in Std_Logic_Vector(1 downto 0);
-- Controle para Register File.
crt_RFile: in Std_Logic;
crt_Mux_RF: in Std_Logic;
address_RF: in Std_Logic_Vector(RF_ADDR_SIZE-1 downto 0);
en_Raddress_RF: in Std_logic;
-- Controle para o Acumulador.
crt_Acc: in Std_Logic_Vector(1 downto 0);
crt_Mux_Acc: in Std_Logic;
-- Entradas do Datapath.
in_PC: in Std_Logic_Vector(N-3 downto 0);
in_IMM: in Std_Logic_Vector(N-1 downto 0);
-- Flag de Igualdade de Operandos.
eq_Flag: out Std_Logic;
-- Saida do resultado do Acumulador.
out_Acc: out Std_Logic_Vector(N-1 downto 0));
End Entity Mips8B_DataPath;
Architecture behave of Mips8B_DataPath is
Use Ieee.Numeric_Std.all;
Use Work.MIPS8B_Base.all;
type mem_type is Array(Natural Range <>) of Std_Logic_Vector(N-1 downto 0);
-- Repesentacao do Register File
Signal RFile_Mem: mem_type(1 to RF_SIZE-1);
Signal Raddress_RF: Std_Logic_Vector(RF_ADDR_SIZE-1 downto 0);
Signal out_RF: Std_Logic_Vector(N-1 downto 0);
-- Representacao das saidas dos multiplexadores.
Signal mux_R2A_ULA, mux_R2B_ULA: Std_Logic_Vector(N-1 downto 0);
Signal mux_RF, mux_Acc: Std_Logic_Vector(N-1 downto 0);
-- Saida do Acumulador
Signal int_out_Acc: Std_Logic_Vector(N-1 downto 0);
-- Registradores para os operandos na ULA e no Shifter.
Signal R1A_ULA, R1B_ULA: Std_Logic_Vector(N-1 downto 0);
Signal R2A_ULA, R2B_ULA: Std_Logic_Vector(N-1 downto 0);
Signal RCRT_ULA: Std_Logic_Vector(2 downto 0);
Signal RD_SH: Std_Logic_Vector(N-1 downto 0);
Signal RS_SH: Std_Logic_Vector(SH_SIZE-1 downto 0);
Signal RCRT_SH: Std_Logic_Vector(1 downto 0);
-- Resulatdos da ULA e do Shifter.
Signal res_ULA, res_SH: Std_Logic_Vector(N-1 downto 0);
Signal Flags: Std_Logic_Vector(1 downto 0);
Begin
-- Saida do Acumulador para fora do Datapath
out_Acc <= int_out_Acc;
-- Flag de Igualdade.
eq_Flag <= Flags(1);
---------------------------------------------------------------------------
-- Controle dos multiplexadores.
With crt_Mux_ULA(1) select
mux_R2A_ULA <= R1A_ULA when '0',
"00" & in_PC when others;
With crt_Mux_ULA(0) select
mux_R2B_ULA <= R1B_ULA when '0',
in_IMM when others;
With crt_Mux_Acc select
mux_Acc <= res_ULA when '0',
res_SH when others;
With crt_Mux_RF select
mux_RF <= int_out_Acc when '0',
in_IMM when others;
---------------------------------------------------------------------------
-- Representalcao do Register File.
RFILE_PROCESS: Process(clock,crt_RFile,Raddress_RF,RFile_Mem,mux_RF)
Begin
If clock'event and clock ='1' then
If Raddress_RF /= R0 and crt_RFile = '1' then
RFile_Mem(to_integer(to_01(Unsigned(Raddress_RF),'1'))) <= mux_RF;
End If;
End If;
If Raddress_RF /= R0 then
out_RF <= RFile_Mem(to_integer(to_01(Unsigned(Raddress_RF),'1')));
Else
out_RF <= (Others => '0');
End If;
End Process RFILE_PROCESS;
---------------------------------------------------------------------------
-- Processo responsavel pela controle dos registradores intermediarios.
MIPS8B_Regs: Process
Begin
Wait Until clock'Event and clock = '1';
If en_Raddress_RF = '1' then
Raddress_RF <= address_RF;
End If;
If en_R1A_ULA = '1' then
R1A_ULA <= out_RF;
End If;
If en_R1B_ULA = '1' then
R1B_ULA <= out_RF;
End If;
If en_R2_ULA = '1' then
R2A_ULA <= mux_R2A_ULA;
R2B_ULA <= mux_R2B_ULA;
RCRT_ULA <= crt_ULA;
End If;
If en_Reg_SH = '1' then
RD_SH <= R1A_ULA;
RS_SH <= S_SH;
RCRT_SH <= crt_SH;
End If;
End Process MIPS8B_Regs;
---------------------------------------------------------------------------
-- Processo responsavel pelas operacoes logicas e aritmeticas
MIPS8B_ULA: Process(R2A_ULA,R2B_ULA,RCRT_ULA,R1A_ULA,R1B_ULA)
Variable TempA, TempB, TempResult: Signed(N downto 0);
Begin
-- Copiando as entradas para execucao das operacoes aritmeticas
TempA := Signed(R2A_ULA(N-1) & R2A_ULA);
TempB := Signed(R2B_ULA(N-1) & R2B_ULA);
-- Realizando a operacao aritimetica
Case RCRT_ULA is
When uSUB =>
TempResult := TempA - TempB;
When uAND =>
TempResult := TempA and TempB;
When uOR =>
TempResult := TempA or TempB;
When Others =>
TempResult := TempA + TempB;
End Case;
-- Levando os resultados para Saida
res_ULA <= Std_Logic_Vector(TempResult(N-1 downto 0));
-- Flag para resultado negativo.
Flags(0) <= TempResult(N);
-- Flag para igualdade.
If R1A_ULA = R1B_ULA then
Flags(1) <= '1';
Else
Flags(1) <= '0';
End If;
End Process MIPS8B_ULA;
---------------------------------------------------------------------------
-- Processo responsavel pelas operacoes de Shifter
MIPS8B_SHIFTER: Process(RD_SH,RS_SH,RCRT_SH)
Begin
Case RCRT_SH is
When sRAR =>
res_SH <= Std_Logic_Vector(SHIFT_RIGHT(Signed(RD_SH),to_integer(Unsigned(RS_SH))));
When sRLL =>
res_SH <= Std_Logic_Vector(SHIFT_RIGHT(Unsigned(RD_SH),to_integer(Unsigned(RS_SH))));
When Others =>
res_SH <= Std_Logic_Vector(SHIFT_LEFT(Signed(RD_SH),to_integer(Unsigned(RS_SH))));
End Case;
End Process MIPS8B_SHIFTER;
---------------------------------------------------------------------------
-- Processo responsavel pelas operacoes no Acumulador
Acc: Process
Variable Temp: Std_Logic_Vector(N-1 downto 0);
Begin
Wait Until clock'Event and clock = '1';
Case crt_Acc is
When AccPar =>
int_out_Acc <= mux_Acc;
When AccFlag =>
Temp := (Others => '0');
If Flags ="01" then -- Comparacao resultou em Menor
Temp(0) := '1';
End If;
int_out_Acc <= Temp;
When Others =>
End Case;
End Process Acc;
End Architecture behave;
Configuration Mips8B_DataPath_behave_conf of Mips8B_DataPath is
For behave
End For;
End Configuration Mips8B_DataPath_behave_conf;
| unlicense | 9114860850cd3144aa3d782de3db4e57 | 0.519019 | 3.552656 | false | false | false | false |
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 7392)
`protect data_block
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`protect end_protected
| gpl-3.0 | 6c9836c9d2215af58460e1f4ac847a33 | 0.931322 | 1.873462 | false | false | false | false |
dummylink/plnk_fpga-stack | Examples/xilinx_microblaze/avnet_lx9/pcores/plb_powerlink_v1_00_a/hdl/vhdl/pdi_tripleVBufLogic.vhd | 5 | 12,460 | ------------------------------------------------------------------------------------------------------------------------
-- Triple Buffer Control Logic
--
-- Copyright (C) 2010 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2010-08-16 V0.01 zelenkaj First version
-- 2010-10-11 V0.02 zelenkaj Bugfix: PCP can't be producer in any case => added generic
-- 2010-10-25 V0.03 zelenkaj Use one Address Adder per DPR port side (reduces LE usage)
-- 2011-04-26 V0.04 zelenkaj generic for clock domain selection
-- 2011-12-13 V0.05 zelenkaj Added constants for one hot code
-- Reduced clkXing to two signals (one hot -> bin -> one hot)
------------------------------------------------------------------------------------------------------------------------
-- This logic implements the virtual triple buffers, by selecting the appropriate address offset
-- The output address offset has to be added to the input address.
-- The trigger signal switches to the next available buffer. The switch mechanism is implemented in the
-- PCP's clock domain. Thus the switch over on the PCP side is performed without delay. An AP switch over crosses
-- from AP to PCP clock domain (2x pcpClk) and back from PCP to AP (2x apClk).
------------------------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY tripleVBufLogic IS
GENERIC(
genOnePdiClkDomain_g : boolean := false;
--base address of virtual buffers in DPR
iVirtualBufferBase_g : INTEGER := 0;
--size of one virtual buffer in DPR (must be aligned!!!)
iVirtualBufferSize_g : INTEGER := 1024;
--out address width
iOutAddrWidth_g : INTEGER := 13;
--in address width
iInAddrWidth_g : INTEGER := 11;
--ap is producer
bApIsProducer : BOOLEAN := FALSE
);
PORT (
pcpClk : IN STD_LOGIC;
pcpReset : IN STD_LOGIC;
pcpTrigger : IN STD_LOGIC; --trigger virtual buffer change
--pcpInAddr : IN STD_LOGIC_VECTOR(iInAddrWidth_g-1 DOWNTO 0);
pcpOutAddrOff : OUT STD_LOGIC_VECTOR(iOutAddrWidth_g DOWNTO 0);
pcpOutSelVBuf : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); --selected virtual buffer (one-hot coded)
apClk : IN STD_LOGIC;
apReset : IN STD_LOGIC;
apTrigger : IN STD_LOGIC; --trigger virtual buffer change
--apInAddr : IN STD_LOGIC_VECTOR(iInAddrWidth_g-1 DOWNTO 0);
apOutAddrOff : OUT STD_LOGIC_VECTOR(iOutAddrWidth_g DOWNTO 0);
apOutSelVBuf : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) --selected virtual buffer (one-hot coded)
);
END ENTITY tripleVBufLogic;
ARCHITECTURE rtl OF tripleVBufLogic IS
--constants
---virtual buffer base address
CONSTANT iVirtualBufferBase0_c : INTEGER := 0*iVirtualBufferSize_g + iVirtualBufferBase_g;
CONSTANT iVirtualBufferBase1_c : INTEGER := 1*iVirtualBufferSize_g + iVirtualBufferBase_g;
CONSTANT iVirtualBufferBase2_c : INTEGER := 2*iVirtualBufferSize_g + iVirtualBufferBase_g;
---one hot code
constant cOneHotVirtualBuffer0 : std_logic_vector(2 downto 0) := "001";
constant cOneHotVirtualBuffer1 : std_logic_vector(2 downto 0) := "010";
constant cOneHotVirtualBuffer2 : std_logic_vector(2 downto 0) := "100";
---triple buffer mechanism
----initial states
CONSTANT initialValid_c : STD_LOGIC_VECTOR(2 DOWNTO 0) := cOneHotVirtualBuffer0;
CONSTANT initialLocked_c : STD_LOGIC_VECTOR(2 DOWNTO 0) := cOneHotVirtualBuffer1;
CONSTANT initialCurrent_c : STD_LOGIC_VECTOR(2 DOWNTO 0) := cOneHotVirtualBuffer2;
--signals
---PCP and AP selected virtual buffer
SIGNAL pcpSelVBuf_s : STD_LOGIC_VECTOR(2 DOWNTO 0); --selected virtual buffer by producer
SIGNAL apSelVBuf_s : STD_LOGIC_VECTOR(2 DOWNTO 0); --selected virtual buffer by consumer
SIGNAL lockedVBuf_s : STD_LOGIC_VECTOR(2 DOWNTO 0); --locked virtual buffer in producer clk domain
BEGIN
pcpOutSelVBuf <= pcpSelVBuf_s;
apOutSelVBuf <= apSelVBuf_s;
theAddrCalcer : BLOCK
--depending on the selected virtual buffer (???SelVBuf_s), the output address is calculated (???OutAddr)
-- ???SelVBuf_s | ???OutAddr
-- -------------------------
-- "001" | ???InAddr + iVirtualBufferBase0_c
-- "010" | ???InAddr + iVirtualBufferBase1_c
-- "100" | ???InAddr + iVirtualBufferBase2_c
SIGNAL pcpAddrOffset, apAddrOffset: STD_LOGIC_VECTOR(iOutAddrWidth_g DOWNTO 0);
--SIGNAL pcpSum, apSum : STD_LOGIC_VECTOR(iOutAddrWidth_g DOWNTO 0);
BEGIN
--select address offset
pcpAddrOffset <= CONV_STD_LOGIC_VECTOR(iVirtualBufferBase0_c, pcpAddrOffset'LENGTH) WHEN pcpSelVBuf_s = cOneHotVirtualBuffer0 ELSE
CONV_STD_LOGIC_VECTOR(iVirtualBufferBase1_c, pcpAddrOffset'LENGTH) WHEN pcpSelVBuf_s = cOneHotVirtualBuffer1 ELSE
CONV_STD_LOGIC_VECTOR(iVirtualBufferBase2_c, pcpAddrOffset'LENGTH) WHEN pcpSelVBuf_s = cOneHotVirtualBuffer2 ELSE
(OTHERS => '0');
pcpOutAddrOff <= pcpAddrOffset;
--calculate address for dpr, leading zero is a sign!
--pcpSum <= ('0' & conv_std_logic_vector(conv_integer(pcpInAddr), iOutAddrWidth_g-1)) + ('0' & pcpAddrOffset);
--pcpOutAddr <= pcpSum(pcpOutAddr'RANGE);
--select address offset
apAddrOffset <= CONV_STD_LOGIC_VECTOR(iVirtualBufferBase0_c, apAddrOffset'LENGTH) WHEN apSelVBuf_s = cOneHotVirtualBuffer0 ELSE
CONV_STD_LOGIC_VECTOR(iVirtualBufferBase1_c, apAddrOffset'LENGTH) WHEN apSelVBuf_s = cOneHotVirtualBuffer1 ELSE
CONV_STD_LOGIC_VECTOR(iVirtualBufferBase2_c, apAddrOffset'LENGTH) WHEN apSelVBuf_s = cOneHotVirtualBuffer2 ELSE
(OTHERS => '0');
apOutAddrOff <= apAddrOffset;
--calculate address for dpr, leading zero is a sign!
--apSum <= ('0' & conv_std_logic_vector(conv_integer(apInAddr), iOutAddrWidth_g-1)) + ('0' & apAddrOffset);
--apOutAddr <= apSum(apOutAddr'RANGE);
END BLOCK theAddrCalcer;
theLockSync : block
constant cBinLockWidth : integer := 2;
constant cBinLock0 : std_logic_vector(cBinLockWidth-1 downto 0) := "01";
constant cBinLock1 : std_logic_vector(cBinLockWidth-1 downto 0) := "11";
constant cBinLock2 : std_logic_vector(cBinLockWidth-1 downto 0) := "10";
signal binLockedVBuf : std_logic_vector(cBinLockWidth-1 downto 0);
signal binApSelVBuf : std_logic_vector(cBinLockWidth-1 downto 0);
begin
--conSelVBuf_s is in the PCP clock domain, thus the lockedVBuf_s signal must be
-- synchronized from PCP clock- to AP clock domain!
--In addition the one hot approach is transformed to save one line
binLockedVBuf <= cBinLock0 when lockedVBuf_s = cOneHotVirtualBuffer0 else
cBinLock1 when lockedVBuf_s = cOneHotVirtualBuffer1 else
cBinLock2;
apSelVBuf_s <= cOneHotVirtualBuffer0 when binApSelVBuf = cBinLock0 else
cOneHotVirtualBuffer1 when binApSelVBuf = cBinLock1 else
cOneHotVirtualBuffer2;
vectorSync : FOR i in cBinLockWidth-1 DOWNTO 0 GENERATE
theLockedSync : ENTITY work.sync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
PORT MAP
(
din => binLockedVBuf(i),
dout => binApSelVBuf(i),
clk => apClk,
rst => apReset
);
END GENERATE;
end block;
theTripleBufferLogic : BLOCK
--The PCP triggers with triggerA and sets buffers to valid.
--The AP triggers with triggerB and locks buffers for reading.
SIGNAL clk, rst : STD_LOGIC;
SIGNAL triggerA : STD_LOGIC;
SIGNAL triggerB, triggerB_s : STD_LOGIC; --triggerB is in AP clock domain!
SIGNAL toggleB, toggleBsync : STD_LOGIC; --toggleB is toggled by AP and synced to PCP
SIGNAL toggleEdge : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL locked : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL currentA : STD_LOGIC_VECTOR(2 DOWNTO 0); --current selected buffer by PCP
-- SIGNAL valid : STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
--triple buffer logic is implemented in PCP clock domain!
clk <= pcpClk;
rst <= pcpReset;
--triggerA is the producer's trigger
triggerA <= pcpTrigger when bApIsProducer = false else triggerB_s;
--conTrigger pulse is in AP clock domain, thus different clock rates will produce more or less pulses!
---thus a toggling signal crosses the clock domain
genToggleB : PROCESS(apClk, apReset)
BEGIN
IF apReset = '1' THEN
toggleB <= '0';
ELSIF apClk = '1' AND apClk'EVENT THEN --CAUTION: AP clock is used!
IF apTrigger = '1' THEN
toggleB <= not toggleB;
END IF;
END IF;
END PROCESS genToggleB;
theToggleSync : ENTITY work.sync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
PORT MAP
(
din => toggleB,
dout => toggleBsync,
clk => clk,
rst => rst
);
toggleShiftReg: PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
toggleEdge <= (OTHERS => '0');
ELSIF clk = '1' AND clk'event THEN
--shift register
toggleEdge <= toggleEdge(0) & toggleBsync;
END IF;
END PROCESS toggleShiftReg;
triggerB_s <= toggleEdge(1) xor toggleEdge(0);
--triggerB is the consumer's trigger
triggerB <= triggerB_s when bApIsProducer = false else pcpTrigger;
--currentA is set by PCP (currently used buffer by PCP)
pcpSelVBuf_s <= currentA when bApIsProducer = false else locked;
--locked virtual buffer in PCP clock domain
lockedVBuf_s <= locked when bApIsProducer = false else currentA;
tripleBufMechanism : PROCESS(clk, rst)
VARIABLE valid_v : STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
IF rst = '1' THEN
--initial state:
---buffer "001" is valid
valid_v := initialValid_c;
---buffer "010" is locked
locked <= initialLocked_c;
---buffer "100" is currently used by PCP
currentA <= initialCurrent_c;
ELSIF clk = '1' AND clk'EVENT THEN
IF triggerA = '1' THEN
--PCP triggers buffer change
---set valid to current selected buffer
---search for free buffer (not locked and valid)
valid_v := currentA;
--free buffer search ex.:
-- locked "001"
-- valid "010"
-- ============
-- free "100"
currentA <= not locked and not valid_v;
END IF;
IF triggerB = '1' THEN
--AP triggers buffer change
---change AP to valid buffer
locked <= valid_v;
END IF;
END IF;
END PROCESS tripleBufMechanism;
END BLOCK theTripleBufferLogic;
END ARCHITECTURE rtl;
| gpl-2.0 | b0a9fe8ecaa3590b4e94191f28a2f7fb | 0.649679 | 3.64221 | false | false | false | false |
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`protect end_protected
| gpl-3.0 | 35e6eb16e265cc915050b867f2d76b04 | 0.937614 | 1.873702 | false | false | false | false |
estadofinito/biblioteca-vhdl | todos-los-archivos/bin2bcd9_tb.vhd | 2 | 1,525 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY bin2bcd9_tb IS
END bin2bcd9_tb;
ARCHITECTURE behavior OF bin2bcd9_tb IS
-- Declaración del componente de la unidad bajo prueba.
COMPONENT bin2bcd9
PORT(
num_bin : IN std_logic_vector(8 downto 0);
num_bcd : OUT std_logic_vector(10 downto 0)
);
END COMPONENT;
-- Entradas.
signal clk : std_logic := '0';
signal num_bin : std_logic_vector(8 downto 0) := (others => '0');
-- Salidas.
signal num_bcd : std_logic_vector(10 downto 0);
-- Definición de los relojes.
constant clk_period : time := 20 ns;
BEGIN
-- Instancia de la unidad bajo prueba.
uut: bin2bcd9 PORT MAP (
num_bin => num_bin,
num_bcd => num_bcd
);
-- Definición del proceso de reloj.
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Proceso de estímulos.
stim_proc: process
begin
wait for 100 ns;
num_bin <= "000000001"; -- 1, 000 0000 0001
wait for 10 ms;
num_bin <= "000000010"; -- 2, 000 0000 0010
wait for 10 ms;
num_bin <= "000000100"; -- 4, 000 0000 0100
wait for 10 ms;
num_bin <= "000001000"; -- 8, 000 0000 1000
wait for 10 ms;
num_bin <= "000010000"; -- 16, 000 0001 0110
wait for 10 ms;
num_bin <= "000100000"; -- 32, 000 0011 0010
wait for 10 ms;
num_bin <= "001000000"; -- 64, 000 0110 0100
wait for 10 ms;
num_bin <= "010000000"; -- 128, 001 0010 1000
wait for 10 ms;
num_bin <= "100000000"; -- 256, 010 0101 0110
wait;
end process;
END; | lgpl-2.1 | 7cd7044901954ca6c7c1c1dbdc0f4f4a | 0.639344 | 2.824074 | false | false | false | false |
rflamino/StellaBlue | core/A6532/src/A6532.vhd | 1 | 7,554 | -- A6532 RAM-I/O-Timer (RIOT)
-- Copyright 2006, 2010 Retromaster
--
-- This file is part of A2601.
--
-- A2601 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License,
-- or any later version.
--
-- A2601 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with A2601. If not, see <http://www.gnu.org/licenses/>.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ram128x8 is
port(clk: in std_logic;
r: in std_logic;
d_in: in std_logic_vector(7 downto 0);
d_out: out std_logic_vector(7 downto 0);
a: in std_logic_vector(6 downto 0));
end ram128x8;
architecture arch of ram128x8 is
type ram_type is array (0 to 127) of
std_logic_vector(7 downto 0);
signal ram: ram_type;
begin
process (clk, r, a)
begin
if (clk'event and clk = '1') then
if (r = '1') then
d_out <= ram(to_integer(unsigned(a)));
else
ram(to_integer(unsigned(a))) <= d_in;
end if;
end if;
end process;
end arch;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity A6532 is
port(clk: in std_logic;
r: in std_logic;
rs: in std_logic;
cs: in std_logic;
irq: out std_logic;
d: inout std_logic_vector(7 downto 0) := "ZZZZZZZZ";
pa: inout std_logic_vector(7 downto 0);
pb: inout std_logic_vector(7 downto 0);
pa7: in std_logic;
a: in std_logic_vector(6 downto 0));
end A6532;
architecture arch of A6532 is
component ram128x8 is
port(clk: in std_logic;
r: in std_logic;
d_in: in std_logic_vector(7 downto 0);
d_out: out std_logic_vector(7 downto 0);
a: in std_logic_vector(6 downto 0));
end component;
signal pa_reg: std_logic_vector(7 downto 0) := "00000000";
signal pb_reg: std_logic_vector(7 downto 0) := "00000000";
signal pa_ddr: std_logic_vector(7 downto 0) := "00000000";
signal pb_ddr: std_logic_vector(7 downto 0) := "00000000";
signal pa_in: std_logic_vector(7 downto 0);
signal pb_in: std_logic_vector(7 downto 0);
signal timer: std_logic_vector(7 downto 0) := "00000000";
signal timer_write: std_logic;
signal timer_read: std_logic;
signal timer_intr: std_logic := '0';
signal timer_intvl: std_logic_vector(1 downto 0) := "11";
signal timer_dvdr: std_logic_vector(10 downto 0) := "00000000001";
signal timer_inc: std_logic;
signal timer_irq_en: std_logic := '0';
signal edge_pol: std_logic := '0';
signal edge_irq_en: std_logic := '0';
signal edge_intr_lo: std_logic := '0';
signal edge_intr_hi: std_logic := '0';
signal edge_intr: std_logic;
signal intr_read: std_logic;
signal ram_d_out: std_logic_vector(7 downto 0);
signal ram_r: std_logic;
signal clk2: std_logic;
begin
-- This clock is phase shifted so that we can use Xilinx synchronous block RAM.
clk2 <= not clk;
io: for i in 0 to 7 generate
-- TEMPORARY FIX
--pa(i) <= pa_reg(i) when pa_ddr(i) = '1' else 'Z';
--pb(i) <= pb_reg(i) when pb_ddr(i) = '1' else 'Z';
pa(i) <= 'Z';
pb(i) <= 'Z';
pa_in(i) <= pa(i);
pb_in(i) <= pb(i) when pb_ddr(i) = '0' else pb_reg(i);
end generate;
ram: ram128x8 port map(clk2, ram_r, d, ram_d_out, a);
ram_r <= (not rs and r) or rs or not cs;
timer_write <= (not r) and rs and a(2) and a(4) and cs;
timer_read <= r and rs and a(2) and (not a(0)) and cs;
intr_read <= r and rs and a(0) and a(2) and cs;
irq <= not ((timer_intr and timer_irq_en) or (edge_intr and edge_irq_en));
edge_intr <= edge_intr_lo when edge_pol = '0' else edge_intr_hi;
process(clk, cs, r, rs, a, ram_d_out, pa_in, pa_ddr, pb_in, pb_ddr, timer, timer_intr, edge_intr)
begin
if r = '1' then
if (cs = '0') then
d <= "ZZZZZZZZ";
elsif rs = '0' then
d <= ram_d_out;
elsif a(2) = '0' then
case a(1 downto 0) is
when "00" =>
d <= pa_in;
when "01" =>
d <= pa_ddr;
when "10" =>
d <= pb_in;
when "11" =>
d <= pb_ddr;
when others =>
null;
end case;
elsif a(0) = '0' then
d <= timer;
elsif a(0) = '1' then
d <= timer_intr & edge_intr & "000000";
else
d <= "--------";
end if;
else
d <= "ZZZZZZZZ";
if (clk'event and clk = '1' and cs = '1') then
if (rs = '1') then
if a(2) = '0' then
case a(1 downto 0) is
when "00" =>
pa_reg <= d;
when "01" =>
pa_ddr <= d;
when "10" =>
pb_reg <= d;
when "11" =>
pb_ddr <= d;
when others =>
null;
end case;
elsif a(4) = '0' then
edge_pol <= a(0);
edge_irq_en <= a(1);
end if;
end if;
end if;
end if;
end process;
process(pa7, intr_read)
begin
if (intr_read = '1') then
edge_intr_lo <= '0';
elsif (pa7'event and pa7 = '1') then
edge_intr_lo <= '1';
end if;
if (intr_read = '1') then
edge_intr_hi <= '0';
elsif (pa7'event and pa7 = '0') then
edge_intr_hi <= '1';
end if;
end process;
with timer_intvl select timer_inc <=
timer_dvdr(0) when "00",
timer_dvdr(3) when "01",
timer_dvdr(6) when "10",
timer_dvdr(10) when "11",
'-' when others;
process(clk)
begin
if (clk'event and clk = '1') then
if (timer_inc = '1') then
timer_dvdr <= "00000000001";
else
timer_dvdr <= timer_dvdr + 1;
end if;
if (timer_write = '1') then
timer <= d;
timer_intvl <= a(1 downto 0);
timer_irq_en <= a(3);
timer_dvdr <= "00000000001";
elsif (timer_intr = '0') then
timer <= timer - timer_inc;
elsif (not (timer = X"00")) then
timer <= timer - 1;
end if;
if (timer = X"00" and timer_inc = '1' and timer_intr = '0' and timer_write = '0') then
timer_intr <= '1';
elsif (timer_read = '1' or timer_write = '1') then
timer_intr <= '0';
end if;
end if;
end process;
end arch;
| mit | 3df89889655a612b6c75de24e3168a1d | 0.486497 | 3.513488 | false | false | false | false |
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| gpl-3.0 | 074462d2c329b0aaf5944fbf354b5491 | 0.920922 | 1.909573 | false | false | false | false |
Monash-2015-Ultrasonic/Logs | Final System Code/SYSTEMV3/Source/IP/FIR/FIR_sim/FIR.vhd | 1 | 1,697 | library IEEE;
use IEEE.std_logic_1164.all;
entity FIR is
port (
clk : in STD_LOGIC;
reset_n : in STD_LOGIC;
ast_sink_data : in STD_LOGIC_VECTOR((3 + 13) * 1 - 1 downto 0);
ast_sink_valid : in STD_LOGIC;
ast_sink_error : in STD_LOGIC_VECTOR(1 downto 0);
ast_source_data : out STD_LOGIC_VECTOR(30 * 1 - 1 downto 0);
ast_source_valid : out STD_LOGIC;
ast_source_error : out STD_LOGIC_VECTOR(1 downto 0)
);
end FIR;
architecture syn of FIR is
component FIR_ast
port (
clk : in STD_LOGIC;
reset_n : in STD_LOGIC;
ast_sink_data : in STD_LOGIC_VECTOR((3 + 13) * 1 - 1 downto 0);
ast_sink_valid : in STD_LOGIC;
ast_sink_ready : out STD_LOGIC;
ast_sink_sop : in STD_LOGIC;
ast_sink_eop : in STD_LOGIC;
ast_sink_error : in STD_LOGIC_VECTOR(1 downto 0);
ast_source_data : out STD_LOGIC_VECTOR(30 * 1 - 1 downto 0);
ast_source_ready : in STD_LOGIC;
ast_source_valid : out STD_LOGIC;
ast_source_sop : out STD_LOGIC;
ast_source_eop : out STD_LOGIC;
ast_source_channel : out STD_LOGIC_VECTOR(1 - 1 downto 0);
ast_source_error : out STD_LOGIC_VECTOR(1 downto 0)
);
end component;
begin
FIR_ast_inst : FIR_ast
port map (
clk => clk,
reset_n => reset_n,
ast_sink_data => ast_sink_data,
ast_source_data => ast_source_data,
ast_sink_valid => ast_sink_valid,
ast_sink_ready => open,
ast_source_ready => '1',
ast_source_valid => ast_source_valid,
ast_sink_sop => '0',
ast_sink_eop => '0',
ast_sink_error => ast_sink_error,
ast_source_sop => open,
ast_source_eop => open,
ast_source_channel => open,
ast_source_error => ast_source_error
);
end syn;
| gpl-2.0 | f55afb396878a46ed52ac417661013ca | 0.620507 | 2.961606 | false | false | false | false |
dummylink/plnk_fpga-stack | Examples/xilinx_microblaze/avnet_lx9/pcores/plb_powerlink_v1_00_a/hdl/vhdl/plb_slave.vhd | 5 | 3,186 | -------------------------------------------------------------------------------
--
-- Title : No Title
-- Design : POWERLINK
-- Author : ATSALZ137
-- Company : Bernecker + Rainer
--
-------------------------------------------------------------------------------
--
-- File : C:\mairt\workspace\VHDL_IP-Cores_mairt\active_hdl\compile\plb_slave.vhd
-- Generated : Mon Dec 5 16:05:26 2011
-- From : C:\mairt\workspace\VHDL_IP-Cores_mairt\active_hdl\src\template\plb_slave.bde
-- By : Bde2Vhdl ver. 2.6
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------
-- Design unit header --
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.STD_LOGIC_UNSIGNED.all;
entity plb_slave is
generic(
C_SLAVE_BASEADDR : INTEGER := 0;
C_SLAVE_HIGHADDR : INTEGER := 0;
C_SLAVE_NUM_MASTERS : INTEGER := 1;
C_SLAVE_PLB_AWIDTH : INTEGER := 32;
C_SLAVE_PLB_DWIDTH : INTEGER := 32;
C_SLAVE_PLB_MID_WIDTH : INTEGER := 1
);
port(
SLAVE_Clk : in STD_LOGIC;
SLAVE_PAValid : in STD_LOGIC;
SLAVE_RNW : in STD_LOGIC;
SLAVE_Rst : in STD_LOGIC;
SLAVE_SAValid : in STD_LOGIC;
SLAVE_abort : in STD_LOGIC;
SLAVE_busLock : in STD_LOGIC;
SLAVE_compress : in STD_LOGIC;
SLAVE_guarded : in STD_LOGIC;
SLAVE_lockErr : in STD_LOGIC;
SLAVE_ordered : in STD_LOGIC;
SLAVE_pendReq : in STD_LOGIC;
SLAVE_rdBurst : in STD_LOGIC;
SLAVE_rdPrim : in STD_LOGIC;
SLAVE_wrBurst : in STD_LOGIC;
SLAVE_wrPrim : in STD_LOGIC;
SLAVE_ABus : in STD_LOGIC_VECTOR(C_SLAVE_PLB_AWIDTH - 1 downto 0);
SLAVE_BE : in STD_LOGIC_VECTOR((C_SLAVE_PLB_DWIDTH / 8) - 1 downto 0);
SLAVE_MSize : in STD_LOGIC_VECTOR(1 downto 0);
SLAVE_masterID : in STD_LOGIC_VECTOR(C_SLAVE_PLB_MID_WIDTH - 1 downto 0);
SLAVE_pendPri : in STD_LOGIC_VECTOR(1 downto 0);
SLAVE_reqPri : in STD_LOGIC_VECTOR(1 downto 0);
SLAVE_size : in STD_LOGIC_VECTOR(3 downto 0);
SLAVE_type : in STD_LOGIC_VECTOR(2 downto 0);
SLAVE_wrDBus : in STD_LOGIC_VECTOR(C_SLAVE_PLB_DWIDTH - 1 downto 0);
SLAVE_addrAck : out STD_LOGIC;
SLAVE_rdBTerm : out STD_LOGIC;
SLAVE_rdComp : out STD_LOGIC;
SLAVE_rdDAck : out STD_LOGIC;
SLAVE_rearbitrate : out STD_LOGIC;
SLAVE_wait : out STD_LOGIC;
SLAVE_wrBTerm : out STD_LOGIC;
SLAVE_wrComp : out STD_LOGIC;
SLAVE_wrDAck : out STD_LOGIC;
SLAVE_MBusy : out STD_LOGIC_VECTOR(C_SLAVE_NUM_MASTERS - 1 downto 0);
SLAVE_MErr : out STD_LOGIC_VECTOR(C_SLAVE_NUM_MASTERS - 1 downto 0);
SLAVE_SSize : out STD_LOGIC_VECTOR(1 downto 0);
SLAVE_rdDBus : out STD_LOGIC_VECTOR(C_SLAVE_PLB_DWIDTH - 1 downto 0);
SLAVE_rdWdAddr : out STD_LOGIC_VECTOR(3 downto 0)
);
end plb_slave;
architecture template of plb_slave is
begin
end template;
| gpl-2.0 | 9ea832df2e6e890aaf552dc3d39c87db | 0.535154 | 3.65367 | false | false | false | false |
estadofinito/biblioteca-vhdl | todos-los-archivos/mux8a1.vhd | 2 | 606 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux8a1 is
PORT (
entrada : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
selector: IN STD_LOGIC_VECTOR(2 DOWNTO 0);
salida : OUT STD_LOGIC
);
end mux8a1;
architecture Behavioral of mux8a1 is
begin
salida <= entrada(0) when (selector = "000") else
entrada(1) when (selector = "001") else
entrada(2) when (selector = "010") else
entrada(3) when (selector = "011") else
entrada(4) when (selector = "100") else
entrada(5) when (selector = "101") else
entrada(6) when (selector = "110") else
entrada(7);
end Behavioral; | lgpl-2.1 | 9cb0f43cdd32cad5a39ce2bb2941ceb9 | 0.648515 | 3.139896 | false | false | false | false |
estadofinito/biblioteca-vhdl | todos-los-archivos/clk4Hz.vhd | 2 | 1,252 | ----------------------------------------------------------------------------------
-- Compañía: Estado Finito
-- Ingeniero: Carlos Ramos
--
-- Fecha de creación: 2014/04/13 08:21:52
-- Nombre del módulo: clk4Hz - Behavioral
-- Comentarios adicionales:
-- Implementación de forma exacta, a caso con escala par.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity clk4Hz is
Port (
clk : in STD_LOGIC; -- Reloj de entrada de 50MHz.
reset : in STD_LOGIC;
clk_out : out STD_LOGIC -- Reloj de salida de 4Hz.
);
end clk4Hz;
architecture Behavioral of clk4Hz is
signal temporal: STD_LOGIC;
signal contador: integer range 0 to 6249999 := 0;
begin
divisor_frecuencia: process (clk, reset) begin
if (reset = '1') then
temporal <= '0';
contador <= 0;
elsif rising_edge(clk) then
if (contador = 6249999) then
temporal <= NOT(temporal);
contador <= 0;
else
contador <= contador + 1;
end if;
end if;
end process;
clk_out <= temporal;
end Behavioral; | lgpl-2.1 | 8077b1506be2ed0230b9bf20bfc1d957 | 0.488818 | 4.159468 | false | false | false | false |
DougFirErickson/parallella-hw | fpga/ip/xilinx/memory_dp_48x4096/blk_mem_gen_v8_2/hdl/blk_mem_output_block.vhd | 8 | 17,242 | `protect begin_protected
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IZGtWJ453fWmZNJ36/59WWGOcoJRtKYUwmwO9ZQy/jGWE5Ei3PxMLjd+82+nZB9oYp/I73YrVAXv
jZfQlKnmGJHvv4zWRxFM2B5rUgdJMFQ=
`protect end_protected
| gpl-3.0 | a5ed52dd4d5c8210ff570622b07e1a20 | 0.936724 | 1.851589 | false | false | false | false |
JuanMarcosRamirez/WeightedMedianDisenoLogico | misc/FPGA/otros/auditoría_imagen_16x16/fifo_16x8x.vhd | 1 | 5,480 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2007 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file fifo_16x8x.vhd when simulating
-- the core, fifo_16x8x. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY fifo_16x8x IS
port (
din: IN std_logic_VECTOR(7 downto 0);
rd_clk: IN std_logic;
rd_en: IN std_logic;
rst: IN std_logic;
wr_clk: IN std_logic;
wr_en: IN std_logic;
dout: OUT std_logic_VECTOR(7 downto 0);
empty: OUT std_logic;
full: OUT std_logic;
wr_data_count: OUT std_logic_VECTOR(3 downto 0));
END fifo_16x8x;
ARCHITECTURE fifo_16x8x_a OF fifo_16x8x IS
-- synthesis translate_off
component wrapped_fifo_16x8x
port (
din: IN std_logic_VECTOR(7 downto 0);
rd_clk: IN std_logic;
rd_en: IN std_logic;
rst: IN std_logic;
wr_clk: IN std_logic;
wr_en: IN std_logic;
dout: OUT std_logic_VECTOR(7 downto 0);
empty: OUT std_logic;
full: OUT std_logic;
wr_data_count: OUT std_logic_VECTOR(3 downto 0));
end component;
-- Configuration specification
for all : wrapped_fifo_16x8x use entity XilinxCoreLib.fifo_generator_v3_3(behavioral)
generic map(
c_rd_freq => 100,
c_wr_response_latency => 1,
c_has_srst => 0,
c_has_rd_data_count => 0,
c_din_width => 8,
c_has_wr_data_count => 1,
c_implementation_type => 2,
c_family => "spartan3",
c_has_wr_rst => 0,
c_wr_freq => 100,
c_underflow_low => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_preload_latency => 1,
c_dout_width => 8,
c_rd_depth => 16,
c_default_value => "BlankString",
c_mif_file_name => "BlankString",
c_has_underflow => 0,
c_has_rd_rst => 0,
c_has_almost_full => 0,
c_has_rst => 1,
c_data_count_width => 4,
c_has_wr_ack => 0,
c_use_ecc => 0,
c_wr_ack_low => 0,
c_common_clock => 0,
c_rd_pntr_width => 4,
c_has_almost_empty => 0,
c_rd_data_count_width => 4,
c_enable_rlocs => 0,
c_wr_pntr_width => 4,
c_overflow_low => 0,
c_prog_empty_type => 0,
c_optimization_mode => 0,
c_wr_data_count_width => 4,
c_preload_regs => 0,
c_dout_rst_val => "0",
c_has_data_count => 0,
c_prog_full_thresh_negate_val => 13,
c_wr_depth => 16,
c_prog_empty_thresh_negate_val => 3,
c_prog_empty_thresh_assert_val => 2,
c_has_valid => 0,
c_init_wr_pntr_val => 0,
c_prog_full_thresh_assert_val => 14,
c_use_fifo16_flags => 0,
c_has_backup => 0,
c_valid_low => 0,
c_prim_fifo_type => "2kx9",
c_count_type => 0,
c_prog_full_type => 0,
c_memory_type => 1);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_fifo_16x8x
port map (
din => din,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_en => wr_en,
dout => dout,
empty => empty,
full => full,
wr_data_count => wr_data_count);
-- synthesis translate_on
END fifo_16x8x_a;
| gpl-3.0 | 0f77716873721efce40d0effccd190be | 0.562956 | 3.474952 | false | false | false | false |
estadofinito/biblioteca-vhdl | todos-los-archivos/reloj.vhd | 2 | 2,426 | ----------------------------------------------------------------------------------
-- Compañía: Estado Finito
-- Ingeniero: Carlos Ramos
--
-- Fecha de creación: 2012/10/26 21:01:42
-- Nombre del módulo: reloj - Behavioral
-- Descripción:
-- Une el contador del reloj con los divisores de frecuencia y el controlador
-- de siete segmentos completo para mostrar la hora en una tarjeta Basys2.
-- Comentarios adicionales:
-- Se puede encontrar más información en la siguiente dirección:
-- http://www.estadofinito.com/reloj-digital/
-- Revisión:
-- Revisión 0.01 - Archivo creado.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity reloj is
PORT(
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
salida: OUT STD_LOGIC_VECTOR(7 downto 0);
MUX : OUT STD_LOGIC_VECTOR(3 downto 0)
);
end reloj;
architecture Behavioral of reloj is
COMPONENT clk1Hz IS
PORT (
entrada: IN STD_LOGIC;
reset : IN STD_LOGIC;
salida : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT contador_reloj IS
PORT (
clk : IN STD_LOGIC;
reset: IN STD_LOGIC;
H1 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
H0 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M1 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M0 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT;
COMPONENT siete_segmentos_completo IS
PORT (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
D0 : IN STD_LOGIC_VECTOR(5 downto 0);
D1 : IN STD_LOGIC_VECTOR(5 downto 0);
D2 : IN STD_LOGIC_VECTOR(5 downto 0);
D3 : IN STD_LOGIC_VECTOR(5 downto 0);
salida: OUT STD_LOGIC_VECTOR(7 downto 0);
MUX : OUT STD_LOGIC_VECTOR(3 downto 0)
);
END COMPONENT;
signal clk_out : STD_LOGIC := '0';
signal HH1, MM1: STD_LOGIC_VECTOR(2 downto 0);
signal HH0, MM0: STD_LOGIC_VECTOR(3 downto 0);
signal pHH1, pHH0, pMM1, pMM0: STD_LOGIC_VECTOR(5 downto 0);
begin
--PORT MAPs necesarios para habilitar el reloj.
clk_i: clk1Hz PORT MAP(clk, reset, clk_out);
cnt_i: contador_reloj PORT MAP(clk_out, reset, HH1, HH0, MM1, MM0);
seg_i: siete_segmentos_completo PORT MAP(clk, reset, pMM0, pMM1, pHH0, pHH1, salida, MUX);
--Padding de las señales del contador para siete segmentos.
pHH1 <= "000" & HH1;
pHH0 <= "00" & HH0;
pMM1 <= "000" & MM1;
pMM0 <= "00" & MM0;
end Behavioral; | lgpl-2.1 | 9d76d6d9cfea1c8e91d647731cf43262 | 0.603462 | 2.962149 | false | false | false | false |
steveEECSrubin/usc_projects | ABB/predefined_sequence.vhd | 1 | 4,172 | -- predefined sequence
-- receiver
entity FRAME_CHECK is
port
(
-- User Interface
RX_DATA : in std_logic_vector(7 downto 0);
RX_CHAR_IS_K_IN : in std_logic;
-- System Interface
USER_CLK : in std_logic;
RESET : in std_logic;
ERROR_COUNT : out std_logic_vector(7 downto 0)
);
--...
signal error : std_logic := '0';
signal STATE_i : std_logic_vector(3 downto 0);
attribute keep: string;
attribute keep of error : signal is "true";
attribute keep of rx_data_r : signal is "true";
--...
--We count the total number of errors we detect. By keeping a count we make it less likely that we will miss
--errors we did not directly observe. This counter must be reset when it reaches its max value
process(USER_CLK)
begin
if(USER_CLK'event and USER_CLK = '1') then
if(start_toggling_r = '0') then
error_count_r <= (others=>'0') after DLY;
elsif(error_detected_r='1') then
error_count_r <= error_count_r + 1 after DLY;
end if;
end if;
if (USER_CLK 'event and USER_CLK = '1') then
if (RX_CHAR_IS_K_IN = '0') then -- if it is not BC
if ((RX_DATA /= x"AA") and (RX_DATA /= x"55") and (RX_DATA /= x"0F") and (RX_DATA /= x"F0") and (RX_DATA /= x"CC") and (RX_DATA /= x"33") and (RX_DATA /= x"BC") and (RX_DATA /= x"F7")) then
error <= '1';
else
error <= '0';
end if;
end if;
end if;
end process;
-- transmitter
signal STATE_i : std_logic_vector(3 downto 0);
signal counter : std_logic_vector(31 downto 0);
--______________________________ Transmit Data __________________________________
--Assign TX_DATA to data register or align char based on the value
TX_DATA <= tx_d_r when (send_align_r='0') else
align_char_c;
TX_CHARISK <= tied_to_ground_i when (send_align_r='0') else
control_bits_c;
--Transmit data when send_align_r is de-asserted. Data is right shifted every cycle.
process(USER_CLK)
begin
if(USER_CLK'event and USER_CLK = '1') then
if(RESET = '1') then
tx_d_r <= x"BC" after DLY;
counter <= x"00000000";
STATE_i <= x"0";
elsif (send_align_r = '0') then
if (STATE_i = x"0") then
STATE_i <= x"1";
tx_d_r <= x"F0";
else
case counter is
when x"00000000" => tx_d_r <= x"AA"; counter <= counter + x"00000001";
when x"00000001" => tx_d_r <= x"55"; counter <= counter + x"00000001";
when x"00000002" => tx_d_r <= x"0F"; counter <= counter + x"00000001";
when x"00000003" => tx_d_r <= x"CC"; counter <= counter + x"00000001";
when x"00000004" => tx_d_r <= x"F7"; counter <= counter + x"00000001";
when x"00000005" => tx_d_r <= x"F7"; counter <= counter + x"00000001";
when x"00000006" => tx_d_r <= x"33"; counter <= counter + x"00000001";
when x"00000007" => tx_d_r <= x"AA"; counter <= counter + x"00000001";
when x"00000008" => tx_d_r <= x"55"; counter <= counter + x"00000001";
when x"00000009" => tx_d_r <= x"0F"; counter <= counter + x"00000001";
when x"0000000A" => tx_d_r <= x"CC"; counter <= counter + x"00000001";
when x"0000000B" => tx_d_r <= x"F7"; counter <= counter + x"00000001";
when x"0000000C" => tx_d_r <= x"F7"; counter <= counter + x"00000001";
when x"0000000D" => tx_d_r <= x"33"; counter <= counter + x"00000001";
when others => tx_d_r <= x"F0"; counter <= x"00000000"; STATE_i <= x"0";
end case;
end if;
end if;
end if;
end process;
| mit | 8247bec8e16ea8fef13fc69c85492edb | 0.477709 | 3.602763 | false | false | false | false |
dummylink/plnk_fpga-stack | Examples/xilinx_microblaze/avnet_lx9/pcores/plb_powerlink_v1_00_a/hdl/vhdl/pdi_par.vhd | 5 | 13,482 | ------------------------------------------------------------------------------------------------------------------------
-- Parallel port (8/16bit) for PDI
--
-- Copyright (C) 2010 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2010-08-31 V0.01 zelenkaj First version
-- 2010-10-18 V0.02 zelenkaj added selection Big/Little Endian
-- use bidirectional data bus
-- 2010-11-15 V0.03 zelenkaj bug fix for 16bit parallel interface
-- 2010-11-23 V0.04 zelenkaj added 2 GPIO pins driving "00"
-- 2010-11-29 V0.05 zelenkaj full endianness consideration
-- 2011-03-21 V0.06 zelenkaj clean up
-- 2011-04-04 V0.10 zelenkaj change of concept
-- 2011-12-02 V0.11 zelenkaj Added I, O and T instead of IO ports
------------------------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity pdi_par is
generic (
papDataWidth_g : integer := 8;
--16bit data is big endian if true
papBigEnd_g : boolean := false;
papGenIoBuf_g : boolean := true
);
port (
-- 8/16bit parallel
pap_cs : in std_logic;
pap_rd : in std_logic;
pap_wr : in std_logic;
pap_be : in std_logic_vector(papDataWidth_g/8-1 downto 0);
pap_addr : in std_logic_vector(15 downto 0);
pap_data : inout std_logic_vector(papDataWidth_g-1 downto 0);
pap_data_I : in std_logic_vector(papDataWidth_g-1 downto 0) := (others => '0');
pap_data_O : out std_logic_vector(papDataWidth_g-1 downto 0);
pap_data_T : out std_logic;
pap_ack : out std_logic;
-- clock for AP side
ap_reset : in std_logic;
ap_clk : in std_logic;
-- Avalon Slave Interface for AP
ap_chipselect : out std_logic;
ap_read : out std_logic;
ap_write : out std_logic;
ap_byteenable : out std_logic_vector(3 DOWNTO 0);
ap_address : out std_logic_vector(12 DOWNTO 0);
ap_writedata : out std_logic_vector(31 DOWNTO 0);
ap_readdata : in std_logic_vector(31 DOWNTO 0);
-- GPIO
pap_gpio : inout std_logic_vector(1 downto 0);
pap_gpio_I : in std_logic_vector(1 downto 0) := (others => '0');
pap_gpio_O : out std_logic_vector(1 downto 0);
pap_gpio_T : out std_logic_vector(1 downto 0)
);
end entity pdi_par;
architecture rtl of pdi_par is
signal ap_byteenable_s : std_logic_vector(ap_byteenable'range);
signal ap_write_s : std_logic;
signal pap_gpiooe_s : std_logic_vector(pap_gpio'range);
--signals being sync'd to ap_clk
signal pap_wrdata_s : std_logic_vector(pap_data'range);
signal pap_wrdata_ss : std_logic_vector(pap_data'range);
signal pap_rddata_s : std_logic_vector(pap_data'range);
signal pap_rddata_ss : std_logic_vector(pap_data'range);
signal pap_addr_s : std_logic_vector(pap_addr'range);
signal pap_cs_s : std_logic;
signal pap_rd_s : std_logic; --and with cs
signal pap_wr_s : std_logic; --and with cs
signal pap_be_s : std_logic_vector(pap_be'range);
--write register
signal writeRegister : std_logic_vector(pap_data'range);
--data tri state buffer
signal pap_doe_s : std_logic;
signal tsb_cnt, tsb_cnt_next : std_logic_vector(1 downto 0);
begin
--reserved for further features not yet defined
genIoGpBuf : if papGenIoBuf_g generate
begin
pap_gpio <= "00" when pap_gpiooe_s = "11" else (others => 'Z');
end generate;
pap_gpiooe_s <= (others => '1');
pap_gpio_O <= "00";
pap_gpio_T <= not pap_gpiooe_s; --'1' = In, '0' = Out
-------------------------------------------------------------------------------------
-- tri-state buffer
genIoDatBuf : if papGenIoBuf_g generate
begin
pap_data <= pap_rddata_s when pap_doe_s = '1' else (others => 'Z');
end generate;
pap_data_O <= pap_rddata_s;
pap_data_T <= not pap_doe_s; --'1' = In, '0' = Out
-- write data register
-- latches data at falling edge of pap_wr if pap_cs is set
theWrDataReg : process(pap_wr, ap_reset)
begin
if ap_reset = '1' then
writeRegister <= (others => '0');
elsif pap_wr = '0' and pap_wr'event then
if pap_cs = '1' then
if papGenIoBuf_g then
writeRegister <= pap_data;
else
writeRegister <= pap_data_I;
end if;
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------
ap_address <= pap_addr_s(ap_address'left+2 downto 2);
-------------------------------------------------------------------------------------
-- generate write and read strobes and chipselect
-- note: pap_cs_s is already and'd with pap_rd_s and pap_wr_s
--falling edge latches write data, sync'd write strobe falls too
wrEdgeDet : entity work.edgeDet
port map (
din => pap_wr_s,
rising => open,
falling => ap_write_s,
any => open,
clk => ap_clk,
rst => ap_reset
);
ap_write <= ap_write_s;
--use the timeout counter highest bit
ap_read <= pap_rd_s;
ap_chipselect <= pap_cs_s;
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- generate ack signal
pap_ack <= pap_doe_s or ap_write_s;
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- generate output enable signal for tri state buffer (with timeout)
pap_doe_s <= tsb_cnt(tsb_cnt'left) and pap_rd_s;
triStatBufCnt : process(ap_clk, ap_reset)
begin
if ap_reset = '1' then
tsb_cnt <= (others => '0');
elsif ap_clk = '1' and ap_clk'event then
tsb_cnt <= tsb_cnt_next;
end if;
end process;
tsb_cnt_next <= tsb_cnt when pap_doe_s = '1' else
tsb_cnt + 1 when pap_rd_s = '1' else
(others => '0');
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- generate 8 or 16 bit signals
gen8bitSigs : if papDataWidth_g = 8 generate
ap_byteenable_s <= --little endian
"0001" when pap_addr_s(1 downto 0) = "00" and papBigEnd_g = false else
"0010" when pap_addr_s(1 downto 0) = "01" and papBigEnd_g = false else
"0100" when pap_addr_s(1 downto 0) = "10" and papBigEnd_g = false else
"1000" when pap_addr_s(1 downto 0) = "11" and papBigEnd_g = false else
--big endian
"0001" when pap_addr_s(1 downto 0) = "11" and papBigEnd_g = true else
"0010" when pap_addr_s(1 downto 0) = "10" and papBigEnd_g = true else
"0100" when pap_addr_s(1 downto 0) = "01" and papBigEnd_g = true else
"1000" when pap_addr_s(1 downto 0) = "00" and papBigEnd_g = true else
(others => '0');
ap_byteenable <= ap_byteenable_s;
ap_writedata <= pap_wrdata_s & pap_wrdata_s & pap_wrdata_s & pap_wrdata_s;
pap_rddata_s <= ap_readdata( 7 downto 0) when ap_byteenable_s = "0001" else
ap_readdata(15 downto 8) when ap_byteenable_s = "0010" else
ap_readdata(23 downto 16) when ap_byteenable_s = "0100" else
ap_readdata(31 downto 24) when ap_byteenable_s = "1000" else
(others => '0');
end generate gen8bitSigs;
genBeSigs16bit : if papDataWidth_g = 16 generate
ap_byteenable_s <= --little endian
"0001" when pap_addr_s(1 downto 1) = "0" and pap_be_s = "01" and papBigEnd_g = false else
"0010" when pap_addr_s(1 downto 1) = "0" and pap_be_s = "10" and papBigEnd_g = false else
"0011" when pap_addr_s(1 downto 1) = "0" and pap_be_s = "11" and papBigEnd_g = false else
"0100" when pap_addr_s(1 downto 1) = "1" and pap_be_s = "01" and papBigEnd_g = false else
"1000" when pap_addr_s(1 downto 1) = "1" and pap_be_s = "10" and papBigEnd_g = false else
"1100" when pap_addr_s(1 downto 1) = "1" and pap_be_s = "11" and papBigEnd_g = false else
--big endian
"0001" when pap_addr_s(1 downto 1) = "1" and pap_be_s = "10" and papBigEnd_g = true else
"0010" when pap_addr_s(1 downto 1) = "1" and pap_be_s = "01" and papBigEnd_g = true else
"0011" when pap_addr_s(1 downto 1) = "1" and pap_be_s = "00" and papBigEnd_g = true else
"0100" when pap_addr_s(1 downto 1) = "0" and pap_be_s = "10" and papBigEnd_g = true else
"1000" when pap_addr_s(1 downto 1) = "0" and pap_be_s = "01" and papBigEnd_g = true else
"1100" when pap_addr_s(1 downto 1) = "0" and pap_be_s = "00" and papBigEnd_g = true else
(others => '0');
ap_byteenable <= ap_byteenable_s;
pap_wrdata_ss <= pap_wrdata_s when papBigEnd_g = false else
pap_wrdata_s(7 downto 0) & pap_wrdata_s(15 downto 8);
ap_writedata <= pap_wrdata_ss & pap_wrdata_ss;
pap_rddata_ss <= ap_readdata( 7 downto 0) & ap_readdata( 7 downto 0) when ap_byteenable_s = "0001" else
ap_readdata(15 downto 8) & ap_readdata(15 downto 8) when ap_byteenable_s = "0010" else
ap_readdata(15 downto 0) when ap_byteenable_s = "0011" else
ap_readdata(23 downto 16) & ap_readdata(23 downto 16) when ap_byteenable_s = "0100" else
ap_readdata(31 downto 24) & ap_readdata(31 downto 24) when ap_byteenable_s = "1000" else
ap_readdata(31 downto 16) when ap_byteenable_s = "1100" else
(others => '0');
pap_rddata_s <= pap_rddata_ss when papBigEnd_g = false else
pap_rddata_ss(7 downto 0) & pap_rddata_ss(15 downto 8);
end generate genBeSigs16bit;
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
--sync those signals
syncAddrGen : for i in pap_addr'range generate
syncAddr : entity work.sync
port map (
din => pap_addr(i),
dout => pap_addr_s(i),
clk => ap_clk,
rst => ap_reset
);
end generate;
syncBeGen : for i in pap_be'range generate
syncBe : entity work.sync
port map (
din => pap_be(i),
dout => pap_be_s(i),
clk => ap_clk,
rst => ap_reset
);
end generate;
syncWrRegGen : for i in writeRegister'range generate
syncWrReg : entity work.sync
port map (
din => writeRegister(i),
dout => pap_wrdata_s(i),
clk => ap_clk,
rst => ap_reset
);
end generate;
theMagicBlock : block
signal pap_rd_tmp, pap_wr_tmp, pap_cs_tmp : std_logic;
begin
syncCs : entity work.sync
port map (
din => pap_cs,
dout => pap_cs_tmp,
clk => ap_clk,
rst => ap_reset
);
pap_cs_s <= pap_cs_tmp;
syncRd : entity work.sync
port map (
din => pap_rd,
dout => pap_rd_tmp,
clk => ap_clk,
rst => ap_reset
);
pap_rd_s <= pap_rd_tmp and pap_cs_tmp;
syncWr : entity work.sync
port map (
din => pap_wr,
dout => pap_wr_tmp,
clk => ap_clk,
rst => ap_reset
);
pap_wr_s <= pap_wr_tmp and pap_cs_tmp;
end block;
--
-------------------------------------------------------------------------------------
end architecture rtl;
| gpl-2.0 | bbb35f0f2514279d73e8d64e7ed20cd2 | 0.540795 | 3.297945 | false | false | false | false |
dummylink/plnk_fpga-stack | Examples/xilinx_microblaze/avnet_lx9/pcores/plb_powerlink_v1_00_a/hdl/vhdl/pdi_dpr_Xilinx.vhd | 2 | 3,683 | ------------------------------------------------------------------------------------------------------------------------
-- Process Data Interface (PDI) DPR for Xilinx
--
-- Copyright (C) 2011 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2011-11-17 V0.01 zelenkaj First version
-- 2011-12-06 V0.02 zelenkaj Uses openMAC DPR implementation
------------------------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY pdi_dpr IS
GENERIC
(
NUM_WORDS : INTEGER := 1024;
LOG2_NUM_WORDS : INTEGER := 10
);
PORT
(
address_a : IN STD_LOGIC_VECTOR (LOG2_NUM_WORDS-1 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (LOG2_NUM_WORDS-1 DOWNTO 0);
byteena_a : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '1');
byteena_b : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '1');
clock_a : IN STD_LOGIC := '1';
clock_b : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
wren_a : IN STD_LOGIC := '0';
wren_b : IN STD_LOGIC := '0';
q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END pdi_dpr;
architecture struct of pdi_dpr is
constant cActivated : std_logic := '1';
begin
abuseMacDpr : entity work.dc_dpr_be
generic map (
WIDTH => data_a'length,
SIZE => NUM_WORDS,
ADDRWIDTH => LOG2_NUM_WORDS
)
port map (
clkA => clock_a, clkB => clock_b,
enA => cActivated, enB => cActivated,
addrA => address_a, addrB => address_b,
diA => data_a, diB => data_b,
doA => q_a, doB => q_b,
weA => wren_a, weB => wren_b,
beA => byteena_a, beB => byteena_b
);
end architecture struct;
| gpl-2.0 | a12634111c109d5d5b4d98dbafdc3f96 | 0.573174 | 3.727733 | false | false | false | false |
DougFirErickson/parallella-hw | fpga/ip/xilinx/fifo_async_103x32/fifo_generator_v12_0/hdl/ramfifo/bram_sync_reg.vhd | 6 | 7,904 | `protect begin_protected
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| gpl-3.0 | 18254ac97ec4f5f4aa9122a09dfd4b44 | 0.918269 | 1.927335 | false | false | false | false |
JuanMarcosRamirez/WeightedMedianDisenoLogico | misc/FPGA/otros/auditoría_imagen_16x16/rc_counter.vhd | 1 | 1,039 | --------------------------------------------------------------------------
-- filename: rc_counter.vhd-- author: Tony Nelson-- date: 12/22/99---- detail: row/column counter---- limits: none------------------------------------------- --------------------------------
library IEEE;use IEEE.std_logic_1164.all;
entity rc_counter is
generic (
num_cols: integer:=16;
num_rows: integer:=16
);
port (
Clk : in std_logic;
RSTn : in std_logic;
En : in std_logic;
ColPos : out integer;
RowPos : out integer
);
end rc_counter;
architecture rc_counter of rc_counter is
begin
process(RSTn,Clk,En)
variable ColPos_var: integer:=0;
variable RowPos_var: integer:=0;
begin
if RSTn = '0' then
ColPos_var := -1;
ColPos <= 0;
RowPos_var := 0;
RowPos <= 0;
elsif rising_edge(Clk) then
if En = '1' then
ColPos_var := ColPos_var +1;
if ColPos_var = num_cols then
RowPos_var := RowPos_var +1;
ColPos_var := 0;
if RowPos_var = num_rows then
RowPos_var := 0;
end if;
end if;
ColPos <= ColPos_var;
RowPos <= RowPos_var;
end if;
end if;
end process;
end rc_counter;
| gpl-3.0 | bccbd9dd5304641a035e386f5c3d8469 | 0.590953 | 3.073964 | false | false | false | false |
dummylink/plnk_fpga-stack | Examples/xilinx_microblaze/avnet_lx9/pcores/plb_powerlink_v1_00_a/hdl/vhdl/OpenMAC_rmii2mii.vhd | 5 | 9,192 | ------------------------------------------------------------------------------------------------------------------------
-- RMII to MII converter
-- ex: openMAC - openHUB - RMII2MII - MII PHY
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Note: Used DPR is specific to Altera/Xilinx. Use one of the following files:
-- OpenMAC_DPR_Altera.vhd
-- OpenMAC_DPR_Xilinx.vhd
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2010-09-13 V0.01 first version
-- 2010-11-15 V0.02 bug fix: increased size of rx fifo, because of errors with marvel 88e1111 mii phy
-- 2010-11-30 V0.03 bug fix: in case of no link some phys confuse tx fifo during tx => aclr fifo
-- 2011-05-06 V0.10 bug fix: use the RX_ER signal, it has important meaning!
-- 2011-07-23 V0.11 forward RxErr to RMII
-- 2011-10-13 V0.20 abuse openMAC_DMAFifo for the converter to use it in Altera/Xilinx easily
-- 2011-11-07 V0.21 increased fifo word size to be on the save side
-- 2011-11-18 V0.22 forward of RxErr not necessary
------------------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity rmii2mii is
port (
clk50 : in std_logic; --used by RMII as well!!!
rst : in std_logic;
--RMII (MAC)
rTxEn : in std_logic;
rTxDat : in std_logic_vector(1 downto 0);
rRxDv : out std_logic;
rRxDat : out std_logic_vector(1 downto 0);
rRxEr : out std_logic;
--MII (PHY)
mTxEn : out std_logic;
mTxDat : out std_logic_vector(3 downto 0);
mTxClk : in std_logic;
mRxDv : in std_logic;
mRxEr : in std_logic;
mRxDat : in std_logic_vector(3 downto 0);
mRxClk : in std_logic
);
end rmii2mii;
architecture rtl of rmii2mii is
constant DIBIT_SIZE : integer := 2;
constant NIBBLE_SIZE : integer := 4;
begin
TX_BLOCK : block
--fifo size must not be larger than 2**5
constant FIFO_NIBBLES_LOG2 : integer := 5;
signal fifo_half, fifo_full, fifo_empty, fifo_valid, fifo_wrempty : std_logic;
signal fifo_wr, fifo_rd : std_logic;
signal fifo_din : std_logic_vector(NIBBLE_SIZE-1 downto 0);
signal fifo_dout : std_logic_vector(NIBBLE_SIZE-1 downto 0);
signal fifo_rdUsedWord : std_logic_vector (FIFO_NIBBLES_LOG2-1 downto 0);
signal fifo_wrUsedWord : std_logic_vector (FIFO_NIBBLES_LOG2-1 downto 0);
--necessary for clr fifo
signal aclr, rTxEn_l : std_logic;
--convert dibits to nibble
signal sel_dibit : std_logic;
signal fifo_din_reg : std_logic_vector(rTxDat'range);
begin
fifo_din <= rTxDat & fifo_din_reg;
fifo_wr <= sel_dibit;
--convert dibits to nibble (to fit to fifo)
process(clk50, rst)
begin
if rst = '1' then
sel_dibit <= '0';
fifo_din_reg <= (others => '0');
elsif clk50 = '1' and clk50'event then
if rTxEn = '1' then
sel_dibit <= not sel_dibit;
if sel_dibit = '0' then
fifo_din_reg <= rTxDat;
end if;
else
sel_dibit <= '0';
end if;
end if;
end process;
mTxDat <= fifo_dout; --brauch ma net... when fifo_valid = '1' else (others => '0');
mTxEn <= fifo_valid;
fifo_half <= fifo_rdUsedWord(fifo_rdUsedWord'left);
process(mTxClk, rst)
begin
if rst = '1' then
fifo_rd <= '0';
fifo_valid <= '0';
elsif mTxClk = '1' and mTxClk'event then
if fifo_rd = '0' and fifo_half = '1' then
fifo_rd <= '1';
elsif fifo_rd = '1' and fifo_empty = '1' then
fifo_rd <= '0';
end if;
if fifo_rd = '1' and fifo_rdUsedWord > conv_std_logic_vector(1, fifo_rdUsedWord'length) then
fifo_valid <= '1';
else
fifo_valid <= '0';
end if;
end if;
end process;
--abuse openMAC's DMA FIFO
theRMII2MII_TXFifo : entity work.openMAC_DMAfifo
generic map (
fifo_data_width_g => NIBBLE_SIZE,
fifo_word_size_g => 2**FIFO_NIBBLES_LOG2,
fifo_word_size_log2_g => FIFO_NIBBLES_LOG2
)
port map (
aclr => aclr,
rd_clk => mTxClk,
wr_clk => clk50,
--read port
rd_req => fifo_rd,
rd_data => fifo_dout,
rd_empty => fifo_empty,
rd_full => open,
rd_usedw => fifo_rdUsedWord,
--write port
wr_req => fifo_wr,
wr_data => fifo_din,
wr_empty => fifo_wrempty,
wr_full => fifo_full,
wr_usedw => fifo_wrUsedWord
);
--sync Mii Tx En (=fifo_valid) to wr clk
process(clk50, rst)
begin
if rst = '1' then
aclr <= '1'; --reset fifo
rTxEn_l <= '0';
elsif clk50 = '1' and clk50'event then
rTxEn_l <= rTxEn;
aclr <= '0'; --default
--clear the full fifo after TX on RMII side is done
if fifo_full = '1' and rTxEn_l = '1' and rTxEn = '0' then
aclr <= '1';
end if;
end if;
end process;
end block;
RX_BLOCK : block
--fifo size must not be larger than 2**5
constant FIFO_NIBBLES_LOG2 : integer := 5;
signal fifo_half, fifo_full, fifo_empty, fifo_valid : std_logic;
signal fifo_wr, fifo_rd : std_logic;
signal fifo_din : std_logic_vector(NIBBLE_SIZE-1 downto 0);
signal fifo_dout : std_logic_vector(NIBBLE_SIZE-1 downto 0);
signal fifo_rdUsedWord : std_logic_vector(FIFO_NIBBLES_LOG2-1 downto 0);
signal fifo_wrUsedWord : std_logic_vector(FIFO_NIBBLES_LOG2-1 downto 0);
--convert nibble to dibits
signal sel_dibit : std_logic;
signal fifo_rd_s : std_logic;
begin
fifo_din <= mRxDat;
fifo_wr <= mRxDv and not mRxEr;
rRxDat <= fifo_dout(fifo_dout'right+1 downto 0) when sel_dibit = '1' else
fifo_dout(fifo_dout'left downto fifo_dout'left-1);
rRxDv <= fifo_valid;
fifo_rd <= fifo_rd_s and not sel_dibit;
process(clk50, rst)
begin
if rst = '1' then
sel_dibit <= '0';
elsif clk50 = '1' and clk50'event then
if fifo_rd_s = '1' or fifo_valid = '1' then
sel_dibit <= not sel_dibit;
else
sel_dibit <= '0';
end if;
end if;
end process;
fifo_half <= fifo_rdUsedWord(fifo_rdUsedWord'left);
rRxEr <= '0';
process(clk50, rst)
begin
if rst = '1' then
fifo_rd_s <= '0';
fifo_valid <= '0';
elsif clk50 = '1' and clk50'event then
if fifo_rd_s = '0' and fifo_half = '1' then
fifo_rd_s <= '1';
elsif fifo_rd_s = '1' and fifo_empty = '1' then
fifo_rd_s <= '0';
end if;
if fifo_rd_s = '1' then
fifo_valid <= '1';
else
fifo_valid <= '0';
end if;
end if;
end process;
--abuse openMAC's DMA FIFO
theMII2RMII_RXFifo : entity work.openMAC_DMAfifo
generic map (
fifo_data_width_g => NIBBLE_SIZE,
fifo_word_size_g => 2**FIFO_NIBBLES_LOG2,
fifo_word_size_log2_g => FIFO_NIBBLES_LOG2
)
port map (
aclr => rst,
rd_clk => clk50,
wr_clk => mRxClk,
--read port
rd_req => fifo_rd,
rd_data => fifo_dout,
rd_empty => fifo_empty,
rd_full => open,
rd_usedw => fifo_rdUsedWord,
--write port
wr_req => fifo_wr,
wr_data => fifo_din,
wr_empty => open,
wr_full => fifo_full,
wr_usedw => fifo_wrUsedWord
);
end block;
end rtl;
| gpl-2.0 | 1b037ff75a5df4fe181d9499dfd7dac2 | 0.582463 | 3.149024 | false | false | false | false |
hgunicamp/Mips8B | src_test/tests/simulacoes/test_Mips_Processor-slt2.vhdl | 1 | 5,312 | -- Teste geral para a estrutura do Processador Mips8B
Library Ieee;
Use Ieee.Std_Logic_1164.all;
Use Ieee.Numeric_Std.all;
Entity test_processor is
End Entity test_processor;
Architecture test_general of test_processor is
Component Mips8B is
Port(Reset_n: In Std_Logic;
Clock: In Std_Logic;
MAddr: Out Std_Logic_Vector(7 downto 0);
MCmd: Out Std_Logic_Vector(1 downto 0);
MData: Out Std_Logic_Vector(7 downto 0);
SData: In Std_Logic_Vector(7 downto 0);
SCmdAccept: In Std_Logic);
End Component Mips8B;
Type Memory_Array is Array(Natural Range <>) of Std_Logic_Vector(7 downto 0);
Use Work.MIPS8B_Base.ocpIDLE_little;
Use Work.MIPS8B_Base.ocpWR_little;
Use Work.MIPS8B_Base.ocpRD_little;
Use Work.MIPS8B_Base.ocpNULL_little;
Use Work.MIPS8B_Base.ocpDVA_little;
Signal Reset_n: Std_Logic;
Signal Clock: Std_Logic := '0';
Signal Clock_Mem: Std_Logic := '0';
Signal MAddr: Std_Logic_Vector(7 downto 0);
Signal MCmd: Std_Logic_Vector(1 downto 0);
Signal MData: Std_Logic_Vector(7 downto 0);
Signal SData: Std_Logic_Vector(7 downto 0);
Signal SCmdAccept: Std_Logic;
Begin
Reset_n <= '1', '0' after 20 ns, '1' after 40 ns;
Clock <= not Clock after 10 ns;
Clock_Mem <= not Clock_Mem after 15 ns;
Memory: Process
Variable int_SCmdAccept: Std_Logic;
Variable address: Unsigned(7 downto 0);
Variable mem_int: Memory_Array(0 to 255) := (
"00100000", "00000001", "00000000", "01111111",
"00100000", "00000010", "00000000", "11111111",
"00100000", "00000011", "00000000", "10000000",
"00100000", "00000100", "00000000", "00000000",
"00100000", "00000101", "00000000", "11111100",
"00100000", "00000110", "00000000", "00000001",
"00100000", "00000111", "00000000", "00010001",
"00000000", "00000111", "00111000", "00101010",
"00000000", "11000000", "00110000", "00101010",
"00000000", "00000101", "00101000", "00101010",
"00000000", "10000000", "00100000", "00101010",
"00000000", "00000011", "00011000", "00101010",
"00000000", "01000000", "00010000", "00101010",
"00000000", "00000010", "00001000", "00101010",
"00100000", "00000001", "00000000", "10000000",
"00100000", "00000010", "00000000", "10000001",
"00100000", "00000011", "00000000", "01111111",
"00100000", "00000100", "00000000", "01111110",
"00000000", "01000001", "00101000", "00101010",
"00000000", "00100010", "00110000", "00101010",
"00000000", "01000011", "00111000", "00101010",
"00000000", "01100010", "00101000", "00101010",
"00000000", "10000011", "00110000", "00101010",
"00000000", "01100100", "00111000", "00101010",
"00000000", "01100001", "00101000", "00101010",
"00000000", "00100011", "00110000", "00101010",
"00100000", "00000100", "00000000", "00000010",
"00100000", "00000101", "00000000", "00000001",
"00100000", "00000110", "00000000", "11111111",
"00100000", "00000111", "00000000", "11111110",
"00000000", "10000101", "00001000", "00101010",
"00000000", "10100100", "00010000", "00101010",
"00000000", "10100110", "00011000", "00101010",
"00000000", "11000101", "00001000", "00101010",
"00000000", "11000111", "00010000", "00101010",
"00000000", "11100110", "00011000", "00101010",
"00000000", "11000100", "00001000", "00101010",
"00000000", "10000110", "00010000", "00101010",
"00000000", "11100101", "00011000", "00101010",
"00000000", "10100111", "00001000", "00101010",
Others => "00000000");
Begin
Wait Until Clock_Mem'Event and Clock_Mem='1';
Case MCmd is
When ocpWR_little =>
If int_SCmdAccept = ocpNULL_little then
int_SCmdAccept := ocpDVA_little;
address := Unsigned(MAddr);
mem_int(to_integer(address)) := MData;
Else
int_SCmdAccept := ocpNULL_little;
End If;
SData <= "ZZZZZZZZ";
When ocpRD_little =>
If int_SCmdAccept = ocpNULL_little then
int_SCmdAccept := ocpDVA_little;
address := Unsigned(MAddr);
SData <= mem_int(to_integer(address));
Else
int_SCmdAccept := ocpNULL_little;
End If;
When Others =>
int_SCmdAccept := ocpNULL_little;
SData <= "ZZZZZZZZ";
End Case;
SCmdAccept <= int_SCmdAccept;
End Process Memory;
DUV: Mips8B
Port Map( Reset_n => Reset_n,
Clock => Clock,
MAddr => MAddr,
MCmd => MCmd,
MData => MData,
SData => SData,
SCmdAccept => SCmdAccept);
End Architecture test_general;
Configuration general_test of test_processor is
For test_general
For DUV: Mips8B Use Configuration Work.Mips8B_struct_conf;
End For;
End For;
End Configuration general_test;
| unlicense | 8378a05de53e795564a04efd4f5e7955 | 0.567959 | 3.849275 | false | true | false | false |
dummylink/plnk_fpga-stack | Examples/xilinx_microblaze/avnet_lx9/pcores/plb_powerlink_v1_00_a/hdl/vhdl/openMAC_DMAmaster.vhd | 5 | 20,401 | -------------------------------------------------------------------------------
--
-- Title : openMAC_DMAmaster
-- Design : POWERLINK
--
-------------------------------------------------------------------------------
--
-- File : C:\git\VHDL_IP-Cores\active_hdl\compile\openMAC_DMAmaster.vhd
-- Generated : Mon Dec 5 07:44:35 2011
-- From : C:\git\VHDL_IP-Cores\active_hdl\src\openMAC_DMAmaster.bde
-- By : Bde2Vhdl ver. 2.6
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2011
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
-- Design unit header --
--
-- This is the toplevel of the openMAC DMA master component.
-- It introduces a generic master device applying burst transfers for
-- RX and TX packet data transfers via a common bus.
--
-------------------------------------------------------------------------------
--
-- 2011-08-03 V0.01 zelenkaj First version
-- 2011-10-13 V0.02 zelenkaj changed names of instances
-- 2011-11-28 V0.03 zelenkaj Added DMA observer
-- 2011-11-29 V0.04 zelenkaj Changed clkXing of Dma Addr
-- 2011-11-30 V0.05 zelenkaj Added generic for DMA observer
-- 2011-12-02 V0.06 zelenkaj Added Dma Req Overflow
-- 2011-12-05 V0.07 zelenkaj Reduced Dma Req overflow
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.math_real.log2;
use ieee.math_real.ceil;
entity openMAC_DMAmaster is
generic(
simulate : boolean := false;
dma_highadr_g : integer := 31;
gen_tx_fifo_g : boolean := true;
gen_rx_fifo_g : boolean := true;
m_burstcount_width_g : integer := 4;
m_burstcount_const_g : boolean := true;
m_tx_burst_size_g : integer := 16;
m_rx_burst_size_g : integer := 16;
tx_fifo_word_size_g : integer := 32;
rx_fifo_word_size_g : integer := 32;
fifo_data_width_g : integer := 16;
endian_g : string := "little";
gen_dma_observer_g : boolean := true
);
port(
dma_clk : in std_logic;
dma_req_overflow : in std_logic;
dma_req_rd : in std_logic;
dma_req_wr : in std_logic;
m_clk : in std_logic;
m_readdatavalid : in std_logic;
m_waitrequest : in std_logic;
mac_rx_off : in std_logic;
mac_tx_off : in std_logic;
rst : in std_logic;
dma_addr : in std_logic_vector(dma_highadr_g downto 1);
dma_dout : in std_logic_vector(15 downto 0);
m_readdata : in std_logic_vector(fifo_data_width_g-1 downto 0);
dma_ack_rd : out std_logic;
dma_ack_wr : out std_logic;
dma_rd_err : out std_logic;
dma_wr_err : out std_logic;
m_read : out std_logic;
m_write : out std_logic;
dma_din : out std_logic_vector(15 downto 0);
m_address : out std_logic_vector(dma_highadr_g downto 0);
m_burstcount : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_burstcounter : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_byteenable : out std_logic_vector(fifo_data_width_g/8-1 downto 0);
m_writedata : out std_logic_vector(fifo_data_width_g-1 downto 0)
);
end openMAC_DMAmaster;
architecture strct of openMAC_DMAmaster is
---- Component declarations -----
component dma_handler
generic(
dma_highadr_g : integer := 31;
gen_dma_observer_g : boolean := true;
gen_rx_fifo_g : boolean := true;
gen_tx_fifo_g : boolean := true;
rx_fifo_word_size_log2_g : natural := 5;
tx_fifo_word_size_log2_g : natural := 5
);
port (
dma_addr : in std_logic_vector(dma_highadr_g downto 1);
dma_clk : in std_logic;
dma_req_overflow : in std_logic;
dma_req_rd : in std_logic;
dma_req_wr : in std_logic;
mac_rx_off : in std_logic;
mac_tx_off : in std_logic;
rst : in std_logic;
rx_wr_clk : in std_logic;
rx_wr_empty : in std_logic;
rx_wr_full : in std_logic;
rx_wr_usedw : in std_logic_vector(rx_fifo_word_size_log2_g-1 downto 0);
tx_rd_clk : in std_logic;
tx_rd_empty : in std_logic;
tx_rd_full : in std_logic;
tx_rd_usedw : in std_logic_vector(tx_fifo_word_size_log2_g-1 downto 0);
dma_ack_rd : out std_logic;
dma_ack_wr : out std_logic;
dma_addr_out : out std_logic_vector(dma_highadr_g downto 1);
dma_new_addr_rd : out std_logic;
dma_new_addr_wr : out std_logic;
dma_rd_err : out std_logic;
dma_wr_err : out std_logic;
rx_aclr : out std_logic;
rx_wr_req : out std_logic;
tx_rd_req : out std_logic
);
end component;
component master_handler
generic(
dma_highadr_g : integer := 31;
fifo_data_width_g : integer := 16;
gen_rx_fifo_g : boolean := true;
gen_tx_fifo_g : boolean := true;
m_burst_wr_const_g : boolean := true;
m_burstcount_width_g : integer := 4;
m_rx_burst_size_g : integer := 16;
m_tx_burst_size_g : integer := 16;
rx_fifo_word_size_log2_g : natural := 5;
tx_fifo_word_size_log2_g : natural := 5
);
port (
dma_addr_in : in std_logic_vector(dma_highadr_g downto 1);
dma_new_addr_rd : in std_logic;
dma_new_addr_wr : in std_logic;
m_clk : in std_logic;
m_readdatavalid : in std_logic;
m_waitrequest : in std_logic;
mac_rx_off : in std_logic;
mac_tx_off : in std_logic;
rst : in std_logic;
rx_rd_clk : in std_logic;
rx_rd_empty : in std_logic;
rx_rd_full : in std_logic;
rx_rd_usedw : in std_logic_vector(rx_fifo_word_size_log2_g-1 downto 0);
tx_wr_clk : in std_logic;
tx_wr_empty : in std_logic;
tx_wr_full : in std_logic;
tx_wr_usedw : in std_logic_vector(tx_fifo_word_size_log2_g-1 downto 0);
m_address : out std_logic_vector(dma_highadr_g downto 0);
m_burstcount : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_burstcounter : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_byteenable : out std_logic_vector(fifo_data_width_g/8-1 downto 0);
m_read : out std_logic;
m_write : out std_logic;
rx_rd_req : out std_logic;
tx_aclr : out std_logic;
tx_wr_req : out std_logic
);
end component;
component OpenMAC_DMAFifo
generic(
fifo_data_width_g : natural := 16;
fifo_word_size_g : natural := 32;
fifo_word_size_log2_g : natural := 5
);
port (
aclr : in std_logic;
rd_clk : in std_logic;
rd_req : in std_logic;
wr_clk : in std_logic;
wr_data : in std_logic_vector(fifo_data_width_g-1 downto 0);
wr_req : in std_logic;
rd_data : out std_logic_vector(fifo_data_width_g-1 downto 0);
rd_empty : out std_logic;
rd_full : out std_logic;
rd_usedw : out std_logic_vector(fifo_word_size_log2_g-1 downto 0);
wr_empty : out std_logic;
wr_full : out std_logic;
wr_usedw : out std_logic_vector(fifo_word_size_log2_g-1 downto 0)
);
end component;
component slow2fastSync
generic(
doSync_g : boolean := TRUE
);
port (
clkDst : in std_logic;
clkSrc : in std_logic;
dataSrc : in std_logic;
rstDst : in std_logic;
rstSrc : in std_logic;
dataDst : out std_logic
);
end component;
---- Architecture declarations -----
--constants
constant tx_fifo_word_size_c : natural := natural(tx_fifo_word_size_g);
constant tx_fifo_word_size_log2_c : natural := natural(ceil(log2(real(tx_fifo_word_size_c))));
constant rx_fifo_word_size_c : natural := natural(rx_fifo_word_size_g);
constant rx_fifo_word_size_log2_c : natural := natural(ceil(log2(real(rx_fifo_word_size_c))));
---- Signal declarations used on the diagram ----
signal dma_new_addr_rd : std_logic;
signal dma_new_addr_wr : std_logic;
signal m_dma_new_addr_rd : std_logic;
signal m_dma_new_addr_wr : std_logic;
signal m_mac_rx_off : std_logic;
signal m_mac_tx_off : std_logic;
signal rx_aclr : std_logic;
signal rx_rd_clk : std_logic;
signal rx_rd_empty : std_logic;
signal rx_rd_full : std_logic;
signal rx_rd_req : std_logic;
signal rx_wr_clk : std_logic;
signal rx_wr_empty : std_logic;
signal rx_wr_full : std_logic;
signal rx_wr_req : std_logic;
signal rx_wr_req_s : std_logic;
signal tx_aclr : std_logic;
signal tx_rd_clk : std_logic;
signal tx_rd_empty : std_logic;
signal tx_rd_full : std_logic;
signal tx_rd_req : std_logic;
signal tx_rd_req_s : std_logic;
signal tx_rd_sel_word : std_logic;
signal tx_wr_clk : std_logic;
signal tx_wr_empty : std_logic;
signal tx_wr_full : std_logic;
signal tx_wr_req : std_logic;
signal dma_addr_trans : std_logic_vector (dma_highadr_g downto 1);
signal rd_data : std_logic_vector (fifo_data_width_g-1 downto 0);
signal rx_rd_usedw : std_logic_vector (rx_fifo_word_size_log2_c-1 downto 0);
signal rx_wr_usedw : std_logic_vector (rx_fifo_word_size_log2_c-1 downto 0);
signal tx_rd_usedw : std_logic_vector (tx_fifo_word_size_log2_c-1 downto 0);
signal tx_wr_usedw : std_logic_vector (tx_fifo_word_size_log2_c-1 downto 0);
signal wr_data : std_logic_vector (fifo_data_width_g-1 downto 0);
signal wr_data_s : std_logic_vector (fifo_data_width_g/2-1 downto 0);
begin
---- Component instantiations ----
THE_DMA_HANDLER : dma_handler
generic map (
dma_highadr_g => dma_highadr_g,
gen_dma_observer_g => gen_dma_observer_g,
gen_rx_fifo_g => gen_rx_fifo_g,
gen_tx_fifo_g => gen_tx_fifo_g,
rx_fifo_word_size_log2_g => rx_fifo_word_size_log2_c,
tx_fifo_word_size_log2_g => tx_fifo_word_size_log2_c
)
port map(
dma_ack_rd => dma_ack_rd,
dma_ack_wr => dma_ack_wr,
dma_addr => dma_addr( dma_highadr_g downto 1 ),
dma_addr_out => dma_addr_trans( dma_highadr_g downto 1 ),
dma_clk => dma_clk,
dma_new_addr_rd => dma_new_addr_rd,
dma_new_addr_wr => dma_new_addr_wr,
dma_rd_err => dma_rd_err,
dma_req_overflow => dma_req_overflow,
dma_req_rd => dma_req_rd,
dma_req_wr => dma_req_wr,
dma_wr_err => dma_wr_err,
mac_rx_off => mac_rx_off,
mac_tx_off => mac_tx_off,
rst => rst,
rx_aclr => rx_aclr,
rx_wr_clk => rx_wr_clk,
rx_wr_empty => rx_wr_empty,
rx_wr_full => rx_wr_full,
rx_wr_req => rx_wr_req,
rx_wr_usedw => rx_wr_usedw( rx_fifo_word_size_log2_c-1 downto 0 ),
tx_rd_clk => tx_rd_clk,
tx_rd_empty => tx_rd_empty,
tx_rd_full => tx_rd_full,
tx_rd_req => tx_rd_req,
tx_rd_usedw => tx_rd_usedw( tx_fifo_word_size_log2_c-1 downto 0 )
);
THE_MASTER_HANDLER : master_handler
generic map (
dma_highadr_g => dma_highadr_g,
fifo_data_width_g => fifo_data_width_g,
gen_rx_fifo_g => gen_rx_fifo_g,
gen_tx_fifo_g => gen_tx_fifo_g,
m_burst_wr_const_g => m_burstcount_const_g,
m_burstcount_width_g => m_burstcount_width_g,
m_rx_burst_size_g => m_rx_burst_size_g,
m_tx_burst_size_g => m_tx_burst_size_g,
rx_fifo_word_size_log2_g => rx_fifo_word_size_log2_c,
tx_fifo_word_size_log2_g => tx_fifo_word_size_log2_c
)
port map(
dma_addr_in => dma_addr_trans( dma_highadr_g downto 1 ),
dma_new_addr_rd => m_dma_new_addr_rd,
dma_new_addr_wr => m_dma_new_addr_wr,
m_address => m_address( dma_highadr_g downto 0 ),
m_burstcount => m_burstcount( m_burstcount_width_g-1 downto 0 ),
m_burstcounter => m_burstcounter( m_burstcount_width_g-1 downto 0 ),
m_byteenable => m_byteenable( fifo_data_width_g/8-1 downto 0 ),
m_clk => m_clk,
m_read => m_read,
m_readdatavalid => m_readdatavalid,
m_waitrequest => m_waitrequest,
m_write => m_write,
mac_rx_off => m_mac_rx_off,
mac_tx_off => m_mac_tx_off,
rst => rst,
rx_rd_clk => rx_rd_clk,
rx_rd_empty => rx_rd_empty,
rx_rd_full => rx_rd_full,
rx_rd_req => rx_rd_req,
rx_rd_usedw => rx_rd_usedw( rx_fifo_word_size_log2_c-1 downto 0 ),
tx_aclr => tx_aclr,
tx_wr_clk => tx_wr_clk,
tx_wr_empty => tx_wr_empty,
tx_wr_full => tx_wr_full,
tx_wr_req => tx_wr_req,
tx_wr_usedw => tx_wr_usedw( tx_fifo_word_size_log2_c-1 downto 0 )
);
rx_rd_clk <= m_clk;
tx_rd_clk <= dma_clk;
rx_wr_clk <= dma_clk;
tx_wr_clk <= m_clk;
sync1 : slow2fastSync
port map(
clkDst => m_clk,
clkSrc => dma_clk,
dataDst => m_mac_tx_off,
dataSrc => mac_tx_off,
rstDst => rst,
rstSrc => rst
);
sync2 : slow2fastSync
port map(
clkDst => m_clk,
clkSrc => dma_clk,
dataDst => m_mac_rx_off,
dataSrc => mac_rx_off,
rstDst => rst,
rstSrc => rst
);
---- Generate statements ----
gen16bitFifo : if fifo_data_width_g = 16 generate
begin
txFifoGen : if gen_tx_fifo_g generate
begin
TX_FIFO_16 : OpenMAC_DMAFifo
generic map (
fifo_data_width_g => fifo_data_width_g,
fifo_word_size_g => tx_fifo_word_size_c,
fifo_word_size_log2_g => tx_fifo_word_size_log2_c
)
port map(
aclr => tx_aclr,
rd_clk => tx_rd_clk,
rd_data => rd_data( fifo_data_width_g-1 downto 0 ),
rd_empty => tx_rd_empty,
rd_full => tx_rd_full,
rd_req => tx_rd_req,
rd_usedw => tx_rd_usedw( tx_fifo_word_size_log2_c-1 downto 0 ),
wr_clk => tx_wr_clk,
wr_data => m_readdata( fifo_data_width_g-1 downto 0 ),
wr_empty => tx_wr_empty,
wr_full => tx_wr_full,
wr_req => tx_wr_req,
wr_usedw => tx_wr_usedw( tx_fifo_word_size_log2_c-1 downto 0 )
);
end generate txFifoGen;
rxFifoGen : if gen_rx_fifo_g generate
begin
RX_FIFO_16 : OpenMAC_DMAFifo
generic map (
fifo_data_width_g => fifo_data_width_g,
fifo_word_size_g => rx_fifo_word_size_c,
fifo_word_size_log2_g => rx_fifo_word_size_log2_c
)
port map(
aclr => rx_aclr,
rd_clk => rx_rd_clk,
rd_data => m_writedata( fifo_data_width_g-1 downto 0 ),
rd_empty => rx_rd_empty,
rd_full => rx_rd_full,
rd_req => rx_rd_req,
rd_usedw => rx_rd_usedw( rx_fifo_word_size_log2_c-1 downto 0 ),
wr_clk => rx_wr_clk,
wr_data => wr_data( fifo_data_width_g-1 downto 0 ),
wr_empty => rx_wr_empty,
wr_full => rx_wr_full,
wr_req => rx_wr_req,
wr_usedw => rx_wr_usedw( rx_fifo_word_size_log2_c-1 downto 0 )
);
end generate rxFifoGen;
--endian conversion
wr_data <= dma_dout(7 downto 0) & dma_dout(15 downto 8) when endian_g = "little" else
dma_dout;
dma_din <= rd_data(7 downto 0) & rd_data(15 downto 8) when endian_g = "little" else
rd_data;
end generate gen16bitFifo;
genRxAddrSync : if gen_rx_fifo_g generate
begin
sync4 : slow2fastSync
port map(
clkDst => m_clk,
clkSrc => dma_clk,
dataDst => m_dma_new_addr_wr,
dataSrc => dma_new_addr_wr,
rstDst => rst,
rstSrc => rst
);
end generate genRxAddrSync;
genTxAddrSync : if gen_tx_fifo_g generate
begin
sync5 : slow2fastSync
port map(
clkDst => m_clk,
clkSrc => dma_clk,
dataDst => m_dma_new_addr_rd,
dataSrc => dma_new_addr_rd,
rstDst => rst,
rstSrc => rst
);
end generate genTxAddrSync;
gen32bitFifo : if fifo_data_width_g = 32 generate
begin
txFifoGen32 : if gen_tx_fifo_g generate
begin
TX_FIFO_32 : OpenMAC_DMAFifo
generic map (
fifo_data_width_g => fifo_data_width_g,
fifo_word_size_g => tx_fifo_word_size_c,
fifo_word_size_log2_g => tx_fifo_word_size_log2_c
)
port map(
aclr => tx_aclr,
rd_clk => tx_rd_clk,
rd_data => rd_data( fifo_data_width_g-1 downto 0 ),
rd_empty => tx_rd_empty,
rd_full => tx_rd_full,
rd_req => tx_rd_req_s,
rd_usedw => tx_rd_usedw( tx_fifo_word_size_log2_c-1 downto 0 ),
wr_clk => tx_wr_clk,
wr_data => m_readdata( fifo_data_width_g-1 downto 0 ),
wr_empty => tx_wr_empty,
wr_full => tx_wr_full,
wr_req => tx_wr_req,
wr_usedw => tx_wr_usedw( tx_fifo_word_size_log2_c-1 downto 0 )
);
tx_rd_proc :
process (tx_rd_clk, rst)
begin
if rst = '1' then
tx_rd_sel_word <= '0';
elsif rising_edge(tx_rd_clk) then
if mac_tx_off = '1' then
tx_rd_sel_word <= '0';
elsif tx_rd_req = '1' then
if tx_rd_sel_word = '0' then
tx_rd_sel_word <= '1';
else
tx_rd_sel_word <= '0';
end if;
end if;
end if;
end process;
tx_rd_req_s <= tx_rd_req when tx_rd_sel_word = '0' else '0';
dma_din <= rd_data(31 downto 16) when tx_rd_sel_word = '1' else
rd_data(15 downto 0);
end generate txFifoGen32;
rxFifoGen32 : if gen_rx_fifo_g generate
begin
RX_FIFO_32 : OpenMAC_DMAFifo
generic map (
fifo_data_width_g => fifo_data_width_g,
fifo_word_size_g => rx_fifo_word_size_c,
fifo_word_size_log2_g => rx_fifo_word_size_log2_c
)
port map(
aclr => rx_aclr,
rd_clk => rx_rd_clk,
rd_data => m_writedata( fifo_data_width_g-1 downto 0 ),
rd_empty => rx_rd_empty,
rd_full => rx_rd_full,
rd_req => rx_rd_req,
rd_usedw => rx_rd_usedw( rx_fifo_word_size_log2_c-1 downto 0 ),
wr_clk => rx_wr_clk,
wr_data => wr_data( fifo_data_width_g-1 downto 0 ),
wr_empty => rx_wr_empty,
wr_full => rx_wr_full,
wr_req => rx_wr_req_s,
wr_usedw => rx_wr_usedw( rx_fifo_word_size_log2_c-1 downto 0 )
);
rx_wr_proc :
process (rx_wr_clk, rst)
variable toggle : std_logic;
begin
if rst = '1' then
wr_data_s <= (others => '0');
toggle := '0';
rx_wr_req_s <= '0';
elsif rising_edge(rx_wr_clk) then
rx_wr_req_s <= '0';
if mac_rx_off = '1' then
toggle := '0';
elsif rx_wr_req = '1' then
if toggle = '0' then
--capture data
wr_data_s <= dma_dout;
toggle := '1';
else
rx_wr_req_s <= '1';
toggle := '0';
end if;
end if;
end if;
end process;
wr_data <= wr_data_s & dma_dout;
end generate rxFifoGen32;
end generate gen32bitFifo;
end strct;
| gpl-2.0 | 4da5d7d301ef1972e3896a95a0ac0033 | 0.575413 | 3.079396 | false | false | false | false |
dummylink/plnk_fpga-stack | Examples/altera_nios2/TERASIC_DE2-115/design_nios2_directIO/POWERLINK/src/OpenMAC_DMAFifo_Altera.vhd | 3 | 6,936 | ------------------------------------------------------------------------------------------------------------------------
-- OpenMAC DMA FIFO
--
-- Copyright (C) 2011 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2011-06-06 V0.01 added generic and export fifo word vector
-- 2011-08-03 V0.10 changed to dual clocked fifo (DCFIFO)
------------------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library altera_mf;
use altera_mf.all;
entity openMAC_DMAfifo is
generic (
fifo_data_width_g : natural := 16;
fifo_word_size_g : natural := 32;
fifo_word_size_log2_g : natural := 5
);
port
(
aclr : in std_logic;
rd_clk : in std_logic;
wr_clk : in std_logic;
--read port
rd_req : in std_logic;
rd_data : out std_logic_vector(fifo_data_width_g-1 downto 0);
rd_empty : out std_logic;
rd_full : out std_logic;
rd_usedw : out std_logic_vector(fifo_word_size_log2_g-1 downto 0);
--write port
wr_req : in std_logic;
wr_data : in std_logic_vector(fifo_data_width_g-1 downto 0);
wr_empty : out std_logic;
wr_full : out std_logic;
wr_usedw : out std_logic_vector(fifo_word_size_log2_g-1 downto 0)
);
end openmac_dmafifo;
architecture struct of openMAC_DMAfifo is
component dcfifo
generic (
lpm_width : natural; --width of data and q ports (input/output)
lpm_widthu : natural; --width of wrusedw and rdusedw
lpm_numwords : natural; --depth of fifo
lpm_showahead : string; --fifo showahead off/on (rdreq works as req/ack)
lpm_type : string; --SCFIFO or DCFIFO (single/dual clocked)
overflow_checking : string; --protection circuit for wrreq
underflow_checking : string; --protection circuit for rdreq
rdsync_delaypipe : natural; --number of sync from wr to rd
wrsync_delaypipe : natural; --number of sync from rd to wr
use_eab : string; --construct fifo as LE/RAM (off/on)
write_aclr_synch : string; --sync async. clear to wr clk (avoids race cond.)
intended_device_family : string --specifies the intended device for functional simulation
);
port (
wrclk : in std_logic; --clock for wr port
rdclk : in std_logic; --clock for rd port
data : in std_logic_vector(fifo_data_width_g-1 downto 0); --data to be written
wrreq : in std_logic; --write request
rdreq : in std_logic; --read request
aclr : in std_logic; --asynchronous clear fifo
q : out std_logic_vector(fifo_data_width_g-1 downto 0); --read data
wrfull : out std_logic; --fifo is full on wr port
rdfull : out std_logic; --fifo is full on rd port
wrempty : out std_logic; --fifo is empty on wr port
rdempty : out std_logic; --fifo is empty on rd port
wrusedw : out std_logic_vector(fifo_word_size_log2_g-1 downto 0); --number of words stored on wr port
rdusedw : out std_logic_vector(fifo_word_size_log2_g-1 downto 0) --number of words stored on rd port
);
end component;
constant fifo_useRam_c : string := "ON";
constant fifo_words_c : natural := fifo_word_size_g; --e.g. 32
constant fifo_usedw_c : natural := fifo_word_size_log2_g; --e.g. log2(32) = 5
--constant fifo_rd_usedw_c : natural := 5;
--constant fifo_wr_usedw_c : natural := 5;
constant fifo_data_width_c : natural := fifo_data_width_g;
--constant fifo_rd_data_width_c : natural := 16;
--constant fifo_wr_data_width_c : natural := 16;
begin
dcfifo_inst : dcfifo
generic map (
lpm_width => fifo_data_width_c, --width of data and q ports (input/output)
lpm_widthu => fifo_usedw_c, --width of wrusedw and rdusedw
lpm_numwords => fifo_words_c, --depth of fifo
lpm_showahead => "OFF", --fifo showahead off/on (rdreq works as req/ack)
lpm_type => "DCFIFO", --SCFIFO or DCFIFO (single/dual clocked)
overflow_checking => "ON", --protection circuit for wrreq
underflow_checking => "ON", --protection circuit for rdreq
rdsync_delaypipe => 4, --number of sync from wr to rd
wrsync_delaypipe => 4, --number of sync from rd to wr
use_eab => fifo_useRam_c, --construct fifo as LE/RAM (off/on)
write_aclr_synch => "ON", --sync async. clear to wr clk (avoids race cond.)
intended_device_family => "Cyclone IV" --specifies the intended device for functional simulation
)
port map (
wrclk => wr_clk, --clock for wr port
rdclk => rd_clk, --clock for rd port
data => wr_data, --data to be written
wrreq => wr_req, --write request
rdreq => rd_req, --read request
aclr => aclr, --asynchronous clear fifo
q => rd_data, --read data
wrfull => wr_full, --fifo is full on wr port
rdfull => rd_full, --fifo is full on rd port
wrempty => wr_empty, --fifo is empty on wr port
rdempty => rd_empty, --fifo is empty on rd port
wrusedw => wr_usedw, --number of words stored on wr port
rdusedw => rd_usedw --number of words stored on rd port
);
end struct;
| gpl-2.0 | 0eeebbff7a0c272a7554f277d589eb9e | 0.620675 | 3.480181 | false | false | false | false |
hgunicamp/Mips8B | src_design/mips8b_core.vhdl | 1 | 8,835 | Library Ieee;
Use Ieee.Std_Logic_1164.all;
Entity Mips8B_Core is
Port(Reset_n: in Std_Logic;
Clock: in Std_Logic;
MAddr: out Std_Logic_Vector(7 downto 0);
MCmd: out Std_Logic_Vector(1 downto 0);
MData: out Std_Logic_Vector(7 downto 0);
SData: in Std_Logic_Vector(7 downto 0);
SCmdAccept: in Std_Logic);
End Entity Mips8B_Core;
Architecture struct of Mips8B_Core is
-- Interfaces dos componentes internos.
Use Work.MIPS8B_Components.all;
-- Importando biblioteca de tipos básicos.
Use Work.MIPS8B_Base.all;
-- Conexões para o PC.
Signal en_Out_PC: Std_Logic;
Signal load_PC: Std_Logic;
Signal inc_PC: Std_Logic;
Signal out_PC: Std_Logic_Vector(5 downto 0);
Signal address_PC: Std_Logic_Vector(5 downto 0);
-- Interface para o sistema de I/O.
-- Controle do endereço fornecido pelo sistema
Signal en_RMem: Std_Logic;
Signal en_RMem_Inc: Std_Logic;
Signal crt_Mux_IO: Std_Logic;
Signal crt_MEM: MemoryOP;
-- Controle dos Dados de I/O.
Signal en_RData_in: Std_Logic;
Signal en_RData_out: Std_Logic;
-- Registradores para dados de I/O.
Signal RData_in: Std_Logic_Vector(7 downto 0);
-- Interface para o controlador principal.
Signal IO_OK: Std_Logic;
Signal eq_Flag: Std_Logic;
Signal en_ROpcode: Std_Logic;
Signal Opcode: Std_Logic_Vector(4 downto 0);
-- Controle para o Registrer File.
Signal crt_RFile: Std_Logic;
Signal en_Raddress_RF: Std_Logic;
Signal address_RF: Std_Logic_Vector(2 downto 0);
-- Controle para os registradores Intermediarios.
Signal en_R1A_ULA: Std_Logic;
Signal en_R1B_ULA: Std_Logic;
Signal en_R2_ULA: Std_Logic;
Signal en_Reg_SH: Std_Logic;
-- Controle para os multiplexadores.
Signal crt_Mux_ULA: Std_Logic_Vector(1 downto 0);
Signal crt_Mux_Acc: Std_Logic;
Signal crt_Mux_RF: Std_Logic;
-- Controle das unidades funcionais.
Signal crt_ULA: Std_Logic_Vector(2 downto 0);
Signal crt_SH: Std_Logic_Vector(1 downto 0);
Signal crt_Acc: Std_Logic_Vector(1 downto 0);
-- Valor do comprimento do shift.
Signal S_SH: Std_Logic_Vector(2 downto 0);
-- Valor do campo imediato
Signal out_IMM: Std_Logic_Vector(7 downto 0);
-- Saida do resultado do Acumulador.
Signal out_Acc: Std_Logic_Vector(7 downto 0);
Begin
---------------------------------------------------------------------------
-- Processo para registrar o opcode da instrução corrente.
OPCode_PROC: Process
Begin
Wait Until Clock'event and Clock = '1';
If en_ROpcode = '1' then
Opcode <= RData_in(7 downto 3);
End If;
End Process OPCode_PROC;
---------------------------------------------------------------------------
-- Instância de PC.
PC_Unity: PC_System
Generic Map(N => 8)
Port Map(clock => Clock,
Reset_n => Reset_n,
en_Out_PC => en_Out_PC,
load_PC => load_PC,
inc_PC => inc_PC,
in_PC => out_Acc(5 downto 0),
out_PC => out_PC,
address_PC => address_PC);
---------------------------------------------------------------------------
-- Instância do sistema de I/O.
IO_System: MIPS8B_IO_System
Generic Map(N => 8)
Port Map(clock => Clock,
Reset_n => Reset_n,
-- Controle do endereço fornecido pelo sistema
en_RMem => en_RMem,
en_RMem_Inc => en_RMem_Inc,
crt_Mux_IO => crt_Mux_IO,
crt_MEM => crt_MEM,
-- Controle dos Dados de I/O.
en_RData_in => en_RData_in,
en_RData_out => en_RData_out,
-- Valores de endereço para transações de I/O.
out_PC => address_PC,
out_DPath => out_Acc,
in_Data => SData,
-- Registradores para dados de I/O.
RMem => MAddr,
RData_in => RData_in,
RData_out => MData,
-- Interface de controle.
Cmd => MCmd,
CmdAccept => SCmdAccept,
IO_OK => IO_OK);
---------------------------------------------------------------------------
-- Instância do controlador principal.
Main_Control: MIPS8B_DP_Control
Generic Map(N => 8,
SH_SIZE => 3,
RF_ADDR_SIZE => 3)
Port Map(clock => Clock,
Reset_n => Reset_n,
IO_OK => IO_OK,
eq_Flag => eq_Flag,
Opcode => Opcode,
in_Bus => RData_in,
-- Controle para o Registrer File.
crt_RFile => crt_RFile,
en_Raddress_RF => en_Raddress_RF,
address_RF => address_RF,
-- Controle para os registradores Intermediarios.
en_R1A_ULA => en_R1A_ULA,
en_R1B_ULA => en_R1B_ULA,
en_R2_ULA => en_R2_ULA,
en_Reg_SH => en_Reg_SH,
-- Controle para os multiplexadores.
crt_Mux_ULA => crt_Mux_ULA,
crt_Mux_Acc => crt_Mux_Acc,
crt_Mux_RF => crt_Mux_RF,
-- Controle das unidades funcionais.
crt_ULA => crt_ULA,
crt_SH => crt_SH,
crt_Acc => crt_Acc,
-- Controle do PC.
en_Out_PC => en_Out_PC,
load_PC => load_PC,
inc_PC => inc_PC,
-- Controle para o sistema de IO.
en_ROpcode => en_ROpcode,
en_RMem => en_RMem,
en_RMem_Inc => en_RMem_Inc,
en_RData_in => en_RData_in,
en_RData_out => en_RData_out,
crt_Mux_IO => crt_Mux_IO,
crt_MEM => crt_MEM,
-- Valor do comprimento do shift.
S_SH => S_SH,
-- Valor do campo imediato
out_IMM => out_IMM);
---------------------------------------------------------------------------
-- Instância do Datapath.
DPATH: Mips8B_DataPath
Generic Map( N => 8,
RF_SIZE => 8,
SH_SIZE => 3,
RF_ADDR_SIZE => 3)
Port Map(clock => Clock,
-- Controle dos Registradores do Shift Register.
en_Reg_SH => en_Reg_SH,
-- Controle para Shifter.
crt_SH => crt_SH,
S_SH => S_SH,
-- Controle dos Registradores da ULA.
en_R1A_ULA => en_R1A_ULA,
en_R1B_ULA => en_R1B_ULA,
en_R2_ULA => en_R2_ULA,
-- Controle para ULA.
crt_ULA => crt_ULA,
crt_Mux_ULA => crt_Mux_ULA,
-- Controle para Register File.
crt_RFile => crt_RFile,
crt_Mux_RF => crt_Mux_RF,
address_RF => address_RF,
en_Raddress_RF => en_Raddress_RF,
-- Controle para o Acumulador.
crt_Acc => crt_Acc,
crt_Mux_Acc => crt_Mux_Acc,
-- Entradas do Datapath.
in_PC => out_PC,
in_IMM => out_IMM,
-- Flag de Igualdade de Operandos.
eq_Flag => eq_Flag,
-- Saida do resultado do Acumulador.
out_Acc => out_Acc);
End Architecture struct;
Configuration Mips8B_Core_struct_conf of Mips8B_Core is
For struct
For PC_Unity: PC_System Use Entity Work.PC_System(behave);
End For;
For IO_System: MIPS8B_IO_System Use Entity Work.MIPS8B_IO_System(behave);
End For;
For Main_Control: MIPS8B_DP_Control Use Entity Work.MIPS8B_DP_Control(behave);
End For;
For DPATH: Mips8B_DataPath Use Entity Work.Mips8B_DataPath(behave);
End For;
End For;
End Configuration Mips8B_Core_struct_conf;
| unlicense | 5e68931263161780186bd927366124ac | 0.453412 | 3.855769 | false | false | false | false |
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