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dqydj/VGAtonic | SPI_Demo/SPISlave.vhd | 1 | 7,764 | ----------------------------------------------------------------------------------
-- SPI Slave Example and FIFO Arbitration
-- Author: PK, http://dqydj.net
-- License: MIT
-- (Please see the root directory for a copy)
-- This module demonstrates crossing clock domains from an independently
-- controlled SPI process or a 'main' user logic process (for this project,
-- it will be a display controller).
--
-- It features a fairly standard two flip flop cross domain clocking scheme for
-- 'command reset', defined as deselecting our CPLD/FPGA, and another two-flop
-- synchronizer for a full cache, which means we have a byte in our FIFO ready
-- for consumption by the user logic.
-----------------------------------------------------------------------------------
-----------------------------------------------------------------------------------
-- Top SPI Speed Calculation (Please check my math - no warranties implied)
-- To determine top speed, look at worst case and count user clocks
-- 1) SPI_CACHE_FULL_FLAG goes high too late for tSU to react
-- 2) CACHE_FULL_FLAG(0) = '1'
-- 3) CACHE_FULL_FLAG(1) = '1'. User Logic sends reset signal.
--
--
-- We can accept up to 7 bits of the full SPI (plus a half clock minus setup
-- time, actually, due to "if (ACK_SPI_BYTE = '1')") based on our code -
-- so 7.5 clocks of SPI cannot be faster than 3 clocks of User Logic. We write
-- the inverse to convert to time, as time is 1/frequency:
--
-- (3/7.5)tUSER < tSPI
--
-- "How much" less is determined by the setup time on the user logic flip flop,
-- so we can constrain it further, and add back the setup time factor:
--
-- (7.5 * tSPI) > (3 * tUSER) + tSU + tSU
-- tSPI > (3*tUSER + 2*tSU)/7.5
--
-- Example: For a 25.125 MHz User Clock and a Xilinx XC95144XL-10 with an internal
-- logic setup time of 3.0 ns:
--
-- tSPI > ((3 * 39.801) +(3.0 + 3.0))/7.5 = 16.7204 ns
-- For that part combination and our code, SPI speed shouldn't exceed
-- 59.807 MHz...
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity SPISlave is
Port (
-- Clock from our 'main' module. The final target for my project
-- is a display controller
CLK : in STD_LOGIC;
-- Whatever output you need
LED : inout STD_LOGIC_VECTOR(7 downto 0) := "00000000";
-- SPI Pins
SCK : in STD_LOGIC;
SEL : in STD_LOGIC;
MOSI: in STD_LOGIC;
-- If you need to 'talk back', use a MISO line as well.
-- If you have other devices on the line and don't need it, leave
-- it floating - but if it is the only one consider pullup or
-- pulldown resistors depending on the SPI master.
MISO: out STD_LOGIC := '0'
);
end SPISlave;
architecture Behavioral of SPISlave is
--------------------------------------------------------
-- SPI Declarations --
--------------------------------------------------------
-- Temporary Storage for SPI (We cheat by one bit to save a flip-flop)
signal SPI_DATA_REG : STD_LOGIC_VECTOR(6 downto 0) := "0000000";
-- Our one byte FIFO
-- receive data even before we write to memory asynchronously
signal SPI_DATA_CACHE : STD_LOGIC_VECTOR(7 downto 0) := "00000000";
signal SCK_COUNTER : STD_LOGIC_VECTOR(2 downto 0) := "000";
-- Asynchronous flags for signals to display logic
signal SPI_CACHE_FULL_FLAG : STD_LOGIC := '0';
signal SPI_CMD_RESET_FLAG : STD_LOGIC := '0';
--------------------------------------------------------
-- Receiver Declarations --
--------------------------------------------------------
-- Your active memory, fresh off the presses
signal USER_DATA : STD_LOGIC_VECTOR(7 downto 0) := "00000000";
-- How should the user logic process the data?
signal USER_MODE : STD_LOGIC := '0';
-- Double flip-flop sync signals for full/command reset - increase these
-- sizes to harden more against metastability
signal CACHE_FULL_FLAG : STD_LOGIC_VECTOR(1 downto 0) := "00";
signal CACHE_RESET_FLAG : STD_LOGIC_VECTOR(1 downto 0) := "00";
-- Async acknowledgement flags for SPI logic
signal ACK_SPI_BYTE : STD_LOGIC := '0';
signal ACK_USER_RESET : STD_LOGIC := '0';
begin
-- (Do something real with it in your code)
LED <= USER_DATA;
-- Code for SPI receiver
SPI_Logic: process (SCK, SEL)
begin
-- Code to handle 'Mode Reset' in the User Logic
if (ACK_USER_RESET = '1') then -- User Logic acknowledges it was reset
SPI_CMD_RESET_FLAG <= '0';
else -- User doesn't currently acknowledge a reset
if (rising_edge(SCK)) then -- CPLD was just deselected
SPI_CMD_RESET_FLAG <= '1';
end if;
end if;
-- Code to handle our SPI arbitration, reading, and clocking
if (ACK_SPI_BYTE = '1') then -- User Logic acknowledges receiving a byte
-- Lower the Cache Full flag
SPI_CACHE_FULL_FLAG <= '0';
-- If we continue clocking while the user logic is reacting,
-- put it into our data register. This is the logic
-- which limits the top speed of the logic - but usually you'll be
-- hardware limited.
if (rising_edge(SCK)) then
if (SEL = '0') then
SPI_DATA_REG <= SPI_DATA_REG(5 downto 0) & MOSI;
SCK_COUNTER <= STD_LOGIC_VECTOR(unsigned(SCK_COUNTER) + 1);
end if;
end if;
else -- User Logic is NOT currently acknowledging a byte received
-- Normal, conventional, everyday, typical, average SPI logic begins.
if (rising_edge(SCK)) then
-- Our CPLD is selected
if (SEL = '0') then
-- If we've just received a whole byte...
if (SCK_COUNTER = "111") then
SCK_COUNTER <= "000";
SPI_DATA_REG <= "0000000";
-- Put the received byte into the single entry FIFO
SPI_DATA_CACHE <= SPI_DATA_REG(6 downto 0) & MOSI;
-- To: User Logic... "You've got mail."
SPI_CACHE_FULL_FLAG <= '1';
-- We're not full yet so the bits will keep coming
else
SPI_DATA_REG <= SPI_DATA_REG(5 downto 0) & MOSI;
SCK_COUNTER <= STD_LOGIC_VECTOR(unsigned(SCK_COUNTER) + 1);
end if;
-- CPLD is NOT selected
else
-- Reset counter, register
SCK_COUNTER <= "000";
SPI_DATA_REG <= "0000000";
end if; -- End CPLD Selected
end if; -- End Rising SCK edge
end if; -- end Byte Received
end process; -- end SPI
-- Code for User Logic
User_Logic: process (CLK)
begin
-- This is our user logic clock now, not SPI anymore
if (rising_edge(CLK)) then
-- If the cache is full, we need to read it into our working register
if (CACHE_FULL_FLAG(1) = '1') then
CACHE_FULL_FLAG <= "00";
USER_DATA <= SPI_DATA_CACHE;
ACK_SPI_BYTE <= '1';
-- If the cache isn't full, keep checking the flag - but don't change
-- our currently active data
else
CACHE_FULL_FLAG <= CACHE_FULL_FLAG(0) & SPI_CACHE_FULL_FLAG;
USER_DATA <= USER_DATA;
ACK_SPI_BYTE <= '0';
end if; -- End Cache Full
-- If the mode reset flag is full, we need to set the mode back to
-- whatever the initial state is
if (CACHE_RESET_FLAG(1) = '1') then
CACHE_RESET_FLAG <= "00";
USER_MODE <= '0';
ACK_USER_RESET <= '1';
-- No reset flag up, so do whatever you want with the mode in your code
else
CACHE_RESET_FLAG <= CACHE_RESET_FLAG(0) & SPI_CMD_RESET_FLAG;
USER_MODE <= '1';
ACK_USER_RESET <= '0';
end if; -- End Cache Full
end if; -- End rising edge user clock
end process;
end Behavioral;
| mit | dae1a51ba51cda7fa05afbdb71559a6f | 0.578181 | 3.592781 | false | false | false | false |
Kalycito-open-automation/openPOWERLINK_V2_old_25-06-2014 | hardware/ipcore/common/lib/src/binaryEncoderRtl.vhd | 2 | 3,930 | -------------------------------------------------------------------------------
--! @file binaryEncoderRtl.vhd
--
--! @brief Generic Binary Encoder with reduced or-operation
--
--! @details This generic binary encoder can be configured to any width,
--! however, mind base 2 values. In order to reduce the complexity of the
--! synthesized circuit the reduced or-operation is applied.
-- (Borrowed from academic.csuohio.edu/chu_p and applied coding styles)
-------------------------------------------------------------------------------
--
-- (c) B&R, 2012
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.global.all;
entity binaryEncoder is
generic (
--! One-hot data width
gDataWidth : natural := 8
);
port (
--! One hot code input
iOneHot : in std_logic_vector(gDataWidth-1 downto 0);
--! Binary encoded output
oBinary : out std_logic_vector(LogDualis(gDataWidth)-1 downto 0)
);
end binaryEncoder;
architecture rtl of binaryEncoder is
type tMaskArray is array(LogDualis(gDataWidth)-1 downto 0) of
std_logic_vector(gDataWidth-1 downto 0);
signal mask : tMaskArray;
function genOrMask return tMaskArray is
variable vOrMask: tMaskArray;
begin
for i in (LogDualis(gDataWidth)-1) downto 0 loop
for j in (gDataWidth-1) downto 0 loop
if (j/(2**i) mod 2)= 1 then
vOrMask(i)(j) := '1';
else
vOrMask(i)(j) := '0';
end if;
end loop;
end loop;
return vOrMask;
end function;
begin
mask <= genOrMask;
process (
mask,
iOneHot
)
variable rowVector : std_logic_vector(gDataWidth-1 downto 0);
variable tempBit : std_logic;
begin
for i in (LogDualis(gDataWidth)-1) downto 0 loop
rowVector := iOneHot and mask(i);
-- reduced or operation
tempBit := '0';
for j in (gDataWidth-1) downto 0 loop
tempBit := tempBit or rowVector(j);
end loop;
oBinary(i) <= tempBit;
end loop;
end process;
end rtl;
| gpl-2.0 | fd0c5709d846b14c793dcd7c84861abb | 0.613995 | 4.481186 | false | false | false | false |
dqydj/VGAtonic | Hardware_Rev_A/RCA:NTSC Demo Barebones/CPLD Firmware/SPI_Slave.vhd | 1 | 5,425 | -----------------------------------------------------------------------------------
-- Top SPI Speed Calculation (Please check my math - no warranties implied)
-- To determine top speed, look at worst case and count user clocks
-- 1) SPI_CACHE_FULL_FLAG goes high too late for tSU to react
-- 2) CACHE_FULL_FLAG(0) = '1'
-- 3) CACHE_FULL_FLAG(1) = '1'. User Logic sends reset signal.
--
--
-- We can accept up to 7 bits of the full SPI (plus a half clock minus setup
-- time, actually, due to "if (ACK_SPI_BYTE = '1')") based on our code -
-- so 7.5 clocks of SPI cannot be faster than 3 clocks of User Logic. We write
-- the inverse to convert to time, as time is 1/frequency:
--
-- (3/7.5)tUSER < tSPI
--
-- "How much" less is determined by the setup time on the user logic flip flop,
-- so we can constrain it further, and add back the setup time factor:
--
-- (7.5 * tSPI) > (3 * tUSER) + tSU + tSU
-- tSPI > (3*tUSER + 2*tSU)/7.5
--
-- Example: In this firmware version, we're using *roughly* NTSC frequency *5, or
-- 17,896,845.40452 Hz . Divide that by 2 because we internally have two 'cycles',
-- a write and a read, so tUSER = 111.751538 ns.
--
-- tSPI > ((3 * 111.751538) +(3.0 + 3.0))/7.5 = 45.5006 ns
-- For this part combination in NTSC and our code, SPI speed shouldn't exceed
-- 1/45.5006ns or 21.9777 MHz...
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity SPI_Slave is
Port (
--------------------------------------------------------
-- SPI Declarations --
--------------------------------------------------------
SEL_SPI : in STD_LOGIC;
-- SPI Pins from World
EXT_SCK : in STD_LOGIC;
EXT_SEL : in STD_LOGIC;
EXT_MOSI : in STD_LOGIC;
EXT_MISO : out STD_LOGIC;
-- SPI Pins from AVR
AVR_SCK : in STD_LOGIC;
AVR_SEL : in STD_LOGIC;
AVR_MOSI : in STD_LOGIC;
-- AVR_MISO : out STD_LOGIC;
-- One byte FIFO
SPI_DATA_CACHE : out STD_LOGIC_VECTOR(7 downto 0) := "00000000";
-- Asynchronous flags for signals to display logic
SPI_CACHE_FULL_FLAG : out STD_LOGIC := '0';
SPI_CMD_RESET_FLAG : out STD_LOGIC := '0';
-- Async Flags returned from user logic
ACK_USER_RESET : in STD_LOGIC;
ACK_SPI_BYTE : in STD_LOGIC
);
end SPI_Slave;
architecture Behavioral of SPI_Slave is
-- Temporary Storage for SPI (Sneaky: cheat by one bit out of 8 to save a flip-flop)
signal SPI_DATA_REG : STD_LOGIC_VECTOR(6 downto 0) := "0000000";
-- Counter for our receiver
signal SCK_COUNTER : STD_LOGIC_VECTOR(2 downto 0) := "000";
signal SCK : STD_LOGIC := '0';
signal SEL : STD_LOGIC := '0';
signal MOSI : STD_LOGIC := '0';
begin
--SEL <= (not SEL_SPI or EXT_SEL) and (SEL_SPI or AVR_SEL); -- Normally High, when SEL_SPI = 0 AVR can drive low.
--SCK <= (not SEL_SPI and AVR_SCK) or (SEL_SPI and EXT_SCK);
--MOSI <= (not SEL_SPI and AVR_MOSI) or (SEL_SPI and EXT_MOSI);
-- Code for SPI receiver
SPI_Logic: process (SEL_SPI, SCK, SEL, ACK_USER_RESET, ACK_SPI_BYTE)
begin
if (SEL_SPI = '1') then
SEL <= AVR_SEL;
SCK <= AVR_SCK;
MOSI <= AVR_MOSI;
else
SEL <= EXT_SEL;
SCK <= EXT_SCK;
MOSI <= EXT_MOSI;
end if;
-- Code to handle 'Mode Reset' in the User Logic
if (ACK_USER_RESET = '1') then -- User Logic acknowledges it was reset
SPI_CMD_RESET_FLAG <= '0';
else -- User doesn't currently acknowledge a reset
if (rising_edge(SEL)) then -- CPLD was just deselected
SPI_CMD_RESET_FLAG <= '1';
end if;
end if;
-- Code to handle our SPI arbitration, reading, and clocking
if (ACK_SPI_BYTE = '1') then -- User Logic acknowledges receiving a byte
-- Lower the Cache Full flag
SPI_CACHE_FULL_FLAG <= '0';
-- If we continue clocking while the user logic is reacting,
-- put it into our data register. This is the logic
-- which limits the top speed of the logic - but usually you'll be
-- hardware limited.
if (rising_edge(SCK)) then
if (SEL = '0') then
SPI_DATA_REG <= SPI_DATA_REG(5 downto 0) & MOSI;
SCK_COUNTER <= STD_LOGIC_VECTOR(unsigned(SCK_COUNTER) + 1);
end if;
end if;
else -- NOT currently acknowledging a byte received RISING EDGE
-- Normal, conventional, everyday, typical, average SPI logic begins.
if (rising_edge(SCK)) then
-- Our CPLD is selected
if (SEL = '0') then
-- If we've just received a whole byte...
if (SCK_COUNTER = "111") then
SCK_COUNTER <= "000";
SPI_DATA_REG <= "0000000";
-- Put the received byte into the single entry FIFO
SPI_DATA_CACHE <= SPI_DATA_REG(6 downto 0) & MOSI;
-- To: User Logic... "You've got mail."
SPI_CACHE_FULL_FLAG <= '1';
-- We're not full yet so the bits will keep coming
else
SPI_DATA_REG <= SPI_DATA_REG(5 downto 0) & MOSI;
SCK_COUNTER <= STD_LOGIC_VECTOR(unsigned(SCK_COUNTER) + 1);
end if;
-- CPLD is NOT selected
else
-- Reset counter, register
SCK_COUNTER <= "000";
SPI_DATA_REG <= "0000000";
end if; -- End CPLD Selected
end if; -- End Rising SCK edge
end if; -- end Byte Received
end process; -- end SPI
end Behavioral; | mit | e730947096c6fb1e8a91d8483f64920b | 0.57788 | 3.236874 | false | false | false | false |
fgr1986/ddr_MIG_ctrl_interface | src/hdl/memory_ctrl.vhd | 1 | 21,317 | ----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Author: Fernando García Redondo, [email protected]
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Create Date: 15:45:01 20/07/2017
-- Design Name: Nexys4 DDR UPM VHDL Lab Project
-- Module Name: memory_ctrl - behavioral
-- Project Name: UPM VHDL Lab Project
-- Target Devices: Nexys4 DDR Development Board, containing a XC7a100t-1 csg324 device
-- Tool versions:
-- Description:
-- This project represents the basic project for the VHDL Lab at ETSIT UPM regarding ddr memories.
-- It, saves and reads secuential data in the DDR2 memory (out of the FPGA).
--
-- For simplicity, the DDR memory is working at 300Mhz (using a 200Mhz input clk),
-- and a PHY to Controller Clock Ratio of **4:1** with **BL8**.
-- **IMPORTANT** By doing so the ddr's **ui_clk** signal needs to be synchronized with the main 100Mhz clk.
-- We use a double reg approach together with handshake protocols (see Advanced FPGA design, Steve Kilts).
-- Double reg approach should be used between slower and faster domains.
--
-- The 200Mhz signal is generated using CLKGEN component (100Mhz output phase set at 0º to sync with 200MHz output).
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
-- Libraries
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Project library
library work;
use work.ram_ddr_MIG7_interface_pkg.ALL;
entity memory_ctrl is
port(
clk_100MHz_i : in std_logic;
rstn_i : in std_logic;
-- this output is required only in simulations
init_calib_complete_o : out std_logic; -- when calibrated
-- DDR2 interface signals
ddr2_addr : out std_logic_vector(12 downto 0);
ddr2_ba : out std_logic_vector(2 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out std_logic_vector(1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
ddr2_dq : inout std_logic_vector(15 downto 0);
ddr2_dqs_p : inout std_logic_vector(1 downto 0);
ddr2_dqs_n : inout std_logic_vector(1 downto 0)
);
end memory_ctrl;
architecture behavioral of memory_ctrl is
----------------------------------------------------------------------------------
-- Component Declarations
----------------------------------------------------------------------------------
-- 200 MHz Clock Generator
component ClkGen
port (
-- Clock in ports
clk_100MHz_i : in std_logic;
-- Clock out ports
clk_100MHz_o : out std_logic;
clk_200MHz_o : out std_logic;
-- Status and control signals
reset_i : in std_logic;
locked_o : out std_logic
);
end component;
component ram_ddr_wrapper is
port (
-- Common
-- clk_100MHz_i : in std_logic;
clk_200MHz_i : in std_logic;
-- device_temp_i : in std_logic_vector(11 downto 0);
rst_i : in std_logic;
-- ram control interface
ram_rnw_i : in std_logic; -- operation to be done: 0->READ, 1->WRITE
ram_addr_i : in std_logic_vector(c_DATA_ADDRESS_WIDTH-1 downto 0);
ram_new_instr_i : in std_logic; -- cs, '1' starts operation
ram_new_ack_o : out std_logic; -- ack between clk domains
ram_end_op_i : in std_logic; -- '1' ends the current write or read operation
-- for high performance consecutive writes or reads
ram_rd_ack_o : out std_logic;
ram_rd_valid_o : out std_logic;
ram_wr_ack_o : out std_logic;
ram_data_to_i : in std_logic_vector(c_DATA_2_MEM_WIDTH-1 downto 0);
ram_data_from_o : out std_logic_vector(c_DATA_2_MEM_WIDTH-1 downto 0);
ram_available_o : out std_logic; -- when ready to next command
init_calib_complete_o : out std_logic; -- when calibrated
-- DDR2 interface
ddr2_addr : out std_logic_vector(12 downto 0);
ddr2_ba : out std_logic_vector(2 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out std_logic_vector(1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
ddr2_dq : inout std_logic_vector(15 downto 0);
ddr2_dqs_p : inout std_logic_vector(1 downto 0);
ddr2_dqs_n : inout std_logic_vector(1 downto 0)
);
end component;
------------------------------------------------------------------------
-- Local Type Declarations
------------------------------------------------------------------------
-- FSM
type state_type is (st_IDLE, st_SEND_WRITE, st_WAIT_WRITE_ACK,
st_SEND_READ, st_WAIT_READ_ACK, st_CHANGE, st_END);
--------------------------------------
-- constants
--------------------------------------
constant c_END_WRITE_CLK : positive := 16; -- send total of 16*c_WORDS_2_MEM words
constant c_END_READ_CLK : positive := 16; -- read total of 16*c_WORDS_2_MEM words
--------------------------------------
-- Signals
--------------------------------------
-- state machine
signal st_state, st_next_state : state_type;
----------------------------------------------------------------------------------
-- Signal Declarations
----------------------------------------------------------------------------------
-- Inverted input reset signal
signal s_rst : std_logic;
-- Reset signal conditioned by the PLL lock
signal s_reset : std_logic;
signal s_resetn : std_logic;
signal s_locked : std_logic;
-- 100 MHz buffered clock signal
signal clk_100MHz_buf : std_logic;
-- 200 MHz buffered clock signal
signal clk_200MHz_buf : std_logic;
-- signals interfacing ram_ddr_wrapper
-- registered control signals for clk domain changes
signal s_ram_rd_ack_pre : std_logic;
signal s_ram_rd_valid_pre : std_logic;
signal s_ram_wr_ack_pre : std_logic;
signal s_ram_available_pre : std_logic;
signal s_init_calib_complete_pre : std_logic;
-- second register
signal s_ram_rd_ack_pre2 : std_logic;
signal s_ram_rd_valid_pre2 : std_logic;
signal s_ram_wr_ack_pre2 : std_logic;
signal s_ram_available_pre2 : std_logic;
signal s_init_calib_complete_pre2 : std_logic;
-- registered data signals for clk domain changes
signal s_ram_data_from_pre : std_logic_vector(c_DATA_2_MEM_WIDTH-1 downto 0);
signal s_ram_data_from_pre2 : t_DATA_OUT_MEM;
-- Signals to be used safely
signal s_init_calib_complete : std_logic;
signal s_ram_rnw : std_logic; -- operation to be done: 0->READ, 1->WRITE
signal s_ram_addr : std_logic_vector(c_DATA_ADDRESS_WIDTH-1 downto 0);
signal s_ram_new_instr : std_logic; -- cs, '1' starts operation
signal s_ram_new_ack : std_logic; -- cs ack, between clk domains
-- does not need to be registered, as only triggers change of state
signal s_ram_end_op : std_logic; -- end of operation
signal s_ram_available : std_logic;
signal s_ram_rd_ack : std_logic;
signal s_ram_rd_valid : std_logic;
signal s_ram_wr_ack : std_logic;
signal s_ram_data_to : std_logic_vector(c_DATA_2_MEM_WIDTH-1 downto 0);
signal s_ram_data_from : t_DATA_OUT_MEM;
signal cnt_en : std_logic;
signal cnt_counter : unsigned(c_DATA_WIDTH-1 downto 0);
begin
-----------------------
-- Reset Generation
-----------------------
-- The Reset Button on the Nexys4 board is active-low,
-- however many components need an active-high reset
s_rst <= not rstn_i;
-- Assign reset signals conditioned by the PLL lock
s_reset <= s_rst or (not s_locked);
-- active-low version of the reset signal
s_resetn <= not s_reset;
----------------------------------------------------------------------------------
-- 200MHz Clock Generator
----------------------------------------------------------------------------------
inst_ClkGen: ClkGen
port map (
clk_100MHz_i => clk_100MHz_i,
clk_100MHz_o => clk_100MHz_buf,
clk_200MHz_o => clk_200MHz_buf,
reset_i => s_rst,
locked_o => s_locked
);
----------------------------------------------------------------------------------
-- ram_ddr_wrapper
----------------------------------------------------------------------------------
inst_ram_ddr_wrapper: ram_ddr_wrapper
port map(
-- clk_100MHz_i => clk_100MHz_buf,
clk_200MHz_i => clk_200MHz_buf,
rst_i => s_reset,
-- ram control interface
ram_rnw_i => s_ram_rnw,
ram_addr_i => s_ram_addr,
ram_new_instr_i => s_ram_new_instr,
ram_new_ack_o => s_ram_new_ack,
ram_end_op_i => s_ram_end_op,
ram_rd_ack_o => s_ram_rd_ack_pre,
ram_rd_valid_o => s_ram_rd_valid_pre,
ram_wr_ack_o => s_ram_wr_ack_pre,
ram_data_to_i => s_ram_data_to,
ram_data_from_o => s_ram_data_from_pre,
ram_available_o => s_ram_available_pre,
init_calib_complete_o => s_init_calib_complete_pre,
-- DDR2 signals
ddr2_dq => ddr2_dq,
ddr2_dqs_p => ddr2_dqs_p,
ddr2_dqs_n => ddr2_dqs_n,
ddr2_addr => ddr2_addr,
ddr2_ba => ddr2_ba,
ddr2_ras_n => ddr2_ras_n,
ddr2_cas_n => ddr2_cas_n,
ddr2_we_n => ddr2_we_n,
ddr2_ck_p => ddr2_ck_p,
ddr2_ck_n => ddr2_ck_n,
ddr2_cke => ddr2_cke,
ddr2_cs_n => ddr2_cs_n,
ddr2_dm => ddr2_dm,
ddr2_odt => ddr2_odt
);
------------------------------------------------------------------------
-- State Machine
------------------------------------------------------------------------
-- Register states
p_sync_FSM: process(clk_100MHz_buf, s_reset)
begin
if s_reset = '1' then
st_state <= st_IDLE;
elsif rising_edge(clk_100MHz_buf) then
st_state <= st_next_state;
end if;
end process p_sync_FSM;
-- Next state logic
p_next_state: process(st_state, s_ram_available, cnt_counter,
s_ram_wr_ack, s_ram_rd_ack, s_ram_new_ack)
begin
st_next_state <= st_state;
case(st_state) is
-- If calibration is done successfully
when st_IDLE =>
if s_ram_available = '1' then
st_next_state <= st_SEND_WRITE;
end if;
when st_SEND_WRITE =>
if s_ram_new_ack = '1' then
st_next_state <= st_WAIT_WRITE_ACK;
end if;
when st_WAIT_WRITE_ACK =>
if s_ram_wr_ack = '1' and cnt_counter > c_END_WRITE_CLK-1 then
st_next_state <= st_CHANGE;
elsif s_ram_wr_ack = '1' then
st_next_state <= st_SEND_WRITE;
end if;
when st_CHANGE =>
if s_ram_available = '1' then
st_next_state <= st_SEND_READ;
end if;
-- We send the command
when st_SEND_READ =>
if s_ram_new_ack = '1' then
st_next_state <= st_WAIT_READ_ACK;
end if;
when st_WAIT_READ_ACK =>
if s_ram_rd_ack = '1' and cnt_counter > c_END_READ_CLK-1 then
st_next_state <= st_END;
elsif s_ram_rd_ack = '1' then
st_next_state <= st_SEND_READ;
end if;
when st_END => -- nothing else in this project
-- st_next_state <= st_IDLE;
when others => st_next_state <= st_IDLE;
end case;
end process;
-------------
-- Counter
-------------
p_counter: process (clk_100MHz_buf, s_reset)
begin
if (s_reset = '1') then
cnt_counter <= (others => '0');
elsif (rising_edge (clk_100MHz_buf)) then
if (st_state = st_CHANGE or st_state = st_IDLE) then
cnt_counter <= (others => '0');
elsif cnt_en = '1' then
cnt_counter <= cnt_counter + 1;
end if;
end if;
end process p_counter;
-- counter enable, including ack response
p_counter_en: process (clk_100MHz_buf, s_reset)
begin
if (s_reset = '1') then
cnt_en <= '0';
elsif (rising_edge (clk_100MHz_buf)) then
if (st_state = st_SEND_WRITE or st_state = st_SEND_READ) then
if cnt_en = '0' then
cnt_en <= '1';
else
cnt_en <= '0';
end if;
else
cnt_en <= '0';
end if;
end if;
end process p_counter_en;
-- Control signals
p_control:process(st_state, cnt_counter)
begin
s_ram_new_instr <= '0';
s_ram_end_op <= '0';
s_ram_rnw <= '0';
case(st_state) is
when st_IDLE =>
s_ram_new_instr <= '0';
s_ram_end_op <= '1';
s_ram_rnw <= '0';
when st_SEND_WRITE =>
s_ram_new_instr <= '1';
s_ram_end_op <= '0';
s_ram_rnw <= '1';
when st_WAIT_WRITE_ACK =>
s_ram_new_instr <= '0';
s_ram_end_op <= '0';
-- maintain previous data and controls but new_instr
s_ram_rnw <= '1';
when st_CHANGE =>
s_ram_new_instr <= '0';
s_ram_end_op <= '1';
s_ram_rnw <= '0';
when st_SEND_READ =>
s_ram_new_instr <= '1';
s_ram_end_op <= '0';
s_ram_rnw <= '0';
when st_WAIT_READ_ACK =>
s_ram_new_instr <= '0';
s_ram_end_op <= '0';
s_ram_rnw <= '0';
when st_END =>
s_ram_new_instr <= '0';
s_ram_end_op <= '1';
s_ram_rnw <= '0';
when others =>
s_ram_new_instr <= '0';
s_ram_end_op <= '0';
s_ram_rnw <= '0';
end case;
end process p_control;
-- Control signals
p_data_addr:process(st_state, cnt_counter)
begin
s_ram_addr <= (others => '0');
s_ram_data_to <= (others => '0');
case(st_state) is
when st_IDLE =>
s_ram_addr <= (others => '0');
s_ram_data_to <= (others => '0');
when st_SEND_WRITE =>
-- update address according to c_ADDR_INC
s_ram_addr <= std_logic_vector( resize(c_ADDR_INC*cnt_counter, s_ram_addr'length) );
-- send up to c_WORDS_2_MEM words each time, based on counter
data_to_wr: for w in 0 to c_WORDS_2_MEM-1 loop
s_ram_data_to((w+1)*c_DATA_WIDTH-1 downto w*c_DATA_WIDTH) <= std_logic_vector( resize(c_WORDS_2_MEM*cnt_counter + w, c_DATA_WIDTH));
end loop data_to_wr;
when st_WAIT_WRITE_ACK =>
s_ram_addr <= (others => '0');
s_ram_data_to <= (others => '0');
when st_CHANGE =>
s_ram_addr <= (others => '0');
s_ram_data_to <= (others => '0');
when st_SEND_READ =>
s_ram_addr <= std_logic_vector( resize(c_ADDR_INC*cnt_counter, s_ram_addr'length) );
s_ram_data_to <= (others => '0');
when st_WAIT_READ_ACK =>
s_ram_addr <= (others => '0');
s_ram_data_to <= (others => '0');
when st_END =>
s_ram_addr <= (others => '0');
s_ram_data_to <= (others => '0');
when others =>
s_ram_addr <= (others => '0');
s_ram_data_to <= (others => '0');
end case;
end process p_data_addr;
------------------------------------------------------------------------
-- Register Data From Memory for CLK Domain change
------------------------------------------------------------------------
p_reg_memory_outs_ctrl: process (clk_100MHz_buf, s_reset)
begin
if (s_reset = '1') then
s_ram_rd_ack_pre2 <= '0';
s_ram_rd_valid_pre2 <= '0';
s_ram_wr_ack_pre2 <= '0';
s_ram_available_pre2 <= '0';
s_init_calib_complete_pre2 <= '0';
s_ram_rd_ack <= '0';
s_ram_rd_valid <= '0';
s_ram_wr_ack <= '0';
s_ram_available <= '0';
s_init_calib_complete <= '0';
elsif (rising_edge (clk_100MHz_buf)) then
-- first reg stage
s_ram_rd_ack_pre2 <= s_ram_rd_ack_pre;
s_ram_rd_valid_pre2 <= s_ram_rd_valid_pre;
s_ram_wr_ack_pre2 <= s_ram_wr_ack_pre;
s_ram_available_pre2 <= s_ram_available_pre;
s_init_calib_complete_pre2 <= s_init_calib_complete_pre;
-- second reg stage with pulse control
if s_ram_rd_ack = '0' then
s_ram_rd_ack <= s_ram_rd_ack_pre2;
else
s_ram_rd_ack <= '0';
end if;
if s_ram_rd_valid = '0' then
s_ram_rd_valid <= s_ram_rd_valid_pre2;
else
s_ram_rd_valid <= '0';
end if;
if s_ram_wr_ack = '0' then
s_ram_wr_ack <= s_ram_wr_ack_pre2;
else
s_ram_wr_ack <= '0';
end if;
-- second reg stage with no pulse control
s_ram_available <= s_ram_available_pre2;
s_init_calib_complete <= s_init_calib_complete_pre2;
end if;
end process p_reg_memory_outs_ctrl;
p_reg_memory_outs_data: process (clk_100MHz_buf, s_reset)
begin
if (s_reset = '1') then
-- restore up to c_WORDS_2_MEM words each time
data_from_rst: for w in 0 to c_WORDS_2_MEM-1 loop
s_ram_data_from_pre2(w) <= (others => '0');
s_ram_data_from(w) <= (others => '0');
end loop data_from_rst;
elsif (rising_edge (clk_100MHz_buf)) then
-- restore up to c_WORDS_2_MEM words each time
data_from: for w in 0 to c_WORDS_2_MEM-1 loop
s_ram_data_from_pre2(w) <= s_ram_data_from_pre((w+1)*c_DATA_WIDTH-1 downto w*c_DATA_WIDTH);
-- update when s_ram_rd_valid_pre2 = '1'
if s_ram_rd_valid_pre2 = '1' then
s_ram_data_from(w) <= s_ram_data_from_pre2(w);
end if;
end loop data_from;
end if;
end process p_reg_memory_outs_data;
-----------------------
-- Outputs connections
-----------------------
-- this output is required only in simulations
init_calib_complete_o <= s_init_calib_complete;
end behavioral;
| gpl-3.0 | a2f12c4eae1b8c62ac2b955e982f7bbf | 0.447619 | 3.757934 | false | false | false | false |
s-kostyuk/course_project_csch | pilot_processor_signed_div/top.vhd | 1 | 1,274 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity top is
generic(
N: integer := 8
);
port(
clk : in STD_LOGIC;
reset : in STD_LOGIC;
d1 : in STD_LOGIC_VECTOR(2*N-1 downto 0);
d2 : in STD_LOGIC_VECTOR(N-1 downto 0);
r : out STD_LOGIC_VECTOR(N-1 downto 0);
IRQ1, IRQ2 : out std_logic
);
end top;
architecture top of top is
component control_unit
port(
clk : in std_logic;
reset : in std_logic;
x : in std_logic_vector(8 downto 1);
y : out STD_LOGIC_VECTOR(16 downto 1)
);
end component;
component operational_unit
generic(
N: integer := 8
);
port(
clk,rst : in STD_LOGIC;
y : in STD_LOGIC_VECTOR(16 downto 1);
d1 : in STD_LOGIC_VECTOR(2*N-1 downto 0);
d2 : in STD_LOGIC_VECTOR(N-1 downto 0);
r:out STD_LOGIC_VECTOR(N-1 downto 0);
x:out STD_LOGIC_vector(8 downto 1);
IRQ1, IRQ2: out std_logic
);
end component;
signal y : std_logic_vector(16 downto 1);
signal x : std_logic_vector(8 downto 1);
signal nclk:std_logic;
begin
nclk<=not clk;
dd1:control_unit port map (clk,reset,x,y);
dd2:operational_unit port map (clk => nclk ,rst => reset,d1 => d1, d2 =>d2, y=>y, x=>x, r =>r, IRQ1 => IRQ1, IRQ2 => IRQ2);
end top; | mit | 146d3b26bd9327f80605486ab71cc114 | 0.597331 | 2.693446 | false | false | false | false |
Kalycito-open-automation/openPOWERLINK_V2_old_25-06-2014 | hardware/ipcore/common/lib/src/clkXingRtl.vhd | 2 | 7,525 | -------------------------------------------------------------------------------
--! @file clkXingRtl.vhd
--
--! @brief Clock Crossing Bus converter
--
--! @details Used to transfer a faster slave interface to a slower one.
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2013
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! need reduce or operation
use ieee.std_logic_misc.OR_REDUCE;
library work;
use work.global.all;
entity clkXing is
generic (
gCsNum : natural := 2;
gDataWidth : natural := 32
);
port (
iArst : in std_logic;
--fast
iFastClk : in std_logic;
iFastCs : in std_logic_vector(gCsNum-1 downto 0);
iFastRNW : in std_logic;
oFastReaddata : out std_logic_vector(gDataWidth-1 downto 0);
oFastWrAck : out std_logic;
oFastRdAck : out std_logic;
--slow
iSlowClk : in std_logic;
oSlowCs : out std_logic_vector(gCsNum-1 downto 0);
oSlowRNW : out std_logic;
iSlowReaddata : in std_logic_vector(gDataWidth-1 downto 0);
iSlowWrAck : in std_logic;
iSlowRdAck : in std_logic
);
end entity;
architecture rtl of clkXing is
signal slowCs : std_logic_vector(gCsNum-1 downto 0);
signal anyCs : std_logic;
signal slowRnw : std_logic;
signal wr, wr_s, wr_rising : std_logic;
signal rd, rd_s, rd_rising : std_logic;
signal readRegister : std_logic_vector(gDataWidth-1 downto 0);
signal fastWrAck, fastRdAck, fastAnyAck, slowAnyAck : std_logic;
begin
-- WELCOME TO SLOW CLOCK DOMAIN --
genThoseCs : for i in slowCs'range generate
begin
theSyncCs : entity work.synchronizer
generic map (
gStages => 2,
gInit => cInactivated
)
port map (
iArst => iArst,
iClk => iSlowClk,
iAsync => iFastCs(i),
oSync => slowCs(i)
);
end generate;
anyCs <= OR_REDUCE(slowCs);
wr_s <= anyCs and not(slowRnw) and not slowAnyAck;
rd_s <= anyCs and slowRnw and not slowAnyAck;
process(iArst, iSlowClk)
begin
if iArst = '1' then
readRegister <= (others => '0');
wr <= '0';
rd <= '0';
elsif rising_edge(iSlowClk) then
if rd = '1' and iSlowRdAck = '1' then
readRegister <= iSlowReaddata;
end if;
if iSlowWrAck = '1' then
wr <= '0';
elsif wr_rising = '1' then
wr <= '1';
end if;
if iSlowRdAck = '1' then
rd <= '0';
elsif rd_rising = '1' then
rd <= '1';
end if;
end if;
end process;
oSlowCs <= slowCs when wr = '1' or rd = '1' else (others => '0');
oSlowRNW <= rd;
theWriteEdge : entity work.edgedetector
port map (
iArst => iArst,
iClk => iSlowClk,
iEnable => cActivated,
iData => wr_s,
oRising => wr_rising,
oFalling => open,
oAny => open
);
theReadEdge : entity work.edgedetector
port map (
iArst => iArst,
iClk => iSlowClk,
iEnable => cActivated,
iData => rd_s,
oRising => rd_rising,
oFalling => open,
oAny => open
);
theSyncRnw : entity work.synchronizer
generic map (
gStages => 2,
gInit => cInactivated
)
port map (
iArst => iArst,
iClk => iSlowClk,
iAsync => iFastRNW,
oSync => slowRnw
);
theSyncAnyAck : entity work.syncTog
generic map (
gStages => 2,
gInit => cInactivated
)
port map (
iSrc_rst => iArst,
iSrc_clk => iFastClk,
iSrc_data => fastAnyAck,
iDst_rst => iArst,
iDst_clk => iSlowClk,
oDst_data => slowAnyAck
);
-- WELCOME TO FAST CLOCK DOMAIN --
process(iArst, iFastClk)
begin
if iArst = '1' then
fastAnyAck <= '0';
elsif rising_edge(iFastClk) then
fastAnyAck <= fastWrAck or fastRdAck;
end if;
end process;
theSyncWrAck : entity work.syncTog
generic map (
gStages => 2,
gInit => cInactivated
)
port map (
iSrc_rst => iArst,
iSrc_clk => iSlowClk,
iSrc_data => iSlowWrAck,
iDst_rst => iArst,
iDst_clk => iFastClk,
oDst_data => fastWrAck
);
oFastWrAck <= fastWrAck;
theSyncRdAck : entity work.syncTog
generic map (
gStages => 2,
gInit => cInactivated
)
port map (
iSrc_rst => iArst,
iSrc_clk => iSlowClk,
iSrc_data => iSlowRdAck,
iDst_rst => iArst,
iDst_clk => iFastClk,
oDst_data => fastRdAck
);
oFastRdAck <= fastRdAck;
genThoseRdq : for i in readRegister'range generate
begin
theSyncRdq : entity work.synchronizer
generic map (
gStages => 2,
gInit => cInactivated
)
port map (
iArst => iArst,
iClk => iFastClk,
iAsync => readRegister(i),
oSync => oFastReaddata(i)
);
end generate;
end architecture;
| gpl-2.0 | 993c462c2e3f42a7d15a6168297e6214 | 0.523455 | 4.549577 | false | false | false | false |
kristofferkoch/ethersound | miim.vhd | 1 | 5,134 | -----------------------------------------------------------------------------
-- Module for interfacing the PHY MDC for the mdc
--
-- Authors:
-- -- Kristoffer E. Koch
-----------------------------------------------------------------------------
-- Copyright 2008 Authors
--
-- This file is part of hwpulse.
--
-- hwpulse is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- hwpulse is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with hwpulse. If not, see <http://www.gnu.org/licenses/>.
-----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity miim is
generic (
DIVISOR : integer := 30;
PHYADDR : std_logic_vector(4 downto 0) := "00000"
);
port (
sysclk : in std_logic;
reset : in std_logic;
addr : in std_logic_vector(4 downto 0);
data_i : in std_logic_vector(15 downto 0);
data_i_e : in std_logic;
data_o : out std_logic_vector(15 downto 0);
data_o_e : in std_logic;
busy : out std_logic;
miim_clk : out std_logic;
miim_d : inout std_logic
);
end miim;
architecture RTL of miim is
signal clkcount:integer range 0 to DIVISOR/2-1;
signal miim_clk_s, negedge:std_logic;
type state_t is (PRE, ST, OP, PHYAD, REGAD, TA, DATA, IDLE);
signal state:state_t;
signal op_read:std_logic;
signal dreg:std_logic_vector(15 downto 0);
signal areg:std_logic_vector(4 downto 0);
signal cnt:integer range 0 to 31;
begin
miim_clk <= miim_clk_s;
negedge <= '1' when clkcount=0 and miim_clk_s = '1' else '0';
--posedge <= '1' when clkcount=0 and miim_clk_s = '0' else '0';
busy <= '1' when state /= IDLE else '0';
clockgen: process(sysclk, reset) is
begin
if reset = '1' then
miim_clk_s <= '0';
clkcount <= 0;
elsif rising_edge(sysclk) then
if clkcount = 0 then
clkcount <= DIVISOR/2 - 1;
miim_clk_s <= not miim_clk_s;
else
clkcount <= clkcount - 1;
end if;
end if;
end process clockgen;
data_o <= dreg;
fsm:process(sysclk, reset) is
begin
if rising_edge(sysclk) then
if reset = '1' then
state <= IDLE;
miim_d <= 'Z';
dreg <= (OTHERS => '0');
op_read <= '0';
areg <= (OTHERS => '0');
else
case state is
when IDLE =>
if negedge = '1' then
miim_d <= 'Z';
end if;
if data_i_e = '1' or data_o_e = '1' then
if data_i_e = '1' then
dreg <= data_i;
op_read <= '0';
else
--dreg <= (OTHERS => 'U'); -- debugging
op_read <= '1';
end if;
areg <= addr;
cnt <= 31;
state <= PRE;
end if;
when PRE =>
if negedge = '1' then
miim_d <= 'Z'; --gets pulled up to '1'
if cnt = 0 then
state <= ST;
cnt <= 1;
else
cnt <= cnt - 1;
end if;
end if;
when ST =>
if negedge = '1' then
if cnt = 1 then -- first
miim_d <= '0';
cnt <= cnt - 1;
else -- second
miim_d <= '1';
state <= OP;
cnt <= 1;
end if;
end if;
when OP =>
if negedge = '1' then
if cnt = 1 then
miim_d <= op_read;
cnt <= cnt - 1;
else
miim_d <= not op_read;
state <= PHYAD;
cnt <= 4;
end if;
end if;
when PHYAD =>
if negedge = '1' then
miim_d <= PHYADDR(cnt);
if cnt = 0 then
state <= REGAD;
cnt <= 4;
else
cnt <= cnt - 1;
end if;
end if;
when REGAD =>
if negedge = '1' then
miim_d <= areg(cnt);
if cnt = 0 then
state <= TA;
cnt <= 1;
else
cnt <= cnt - 1;
end if;
end if;
when TA =>
if negedge = '1' then
if op_read = '1' then
if cnt = 0 then
assert miim_d = '0' report "MIIM: PHY did not pull down second TA-bit";
state <= DATA;
cnt <= 15;
else --first
miim_d <= 'Z';
cnt <= cnt - 1;
end if;
else
if cnt = 0 then
miim_d <= '0';
state <= DATA;
cnt <= 15;
else --first
miim_d <= '1';
cnt <= cnt - 1;
end if;
end if;
end if;
when DATA =>
if negedge = '1' then
if op_read = '1' then
assert miim_d = '1' or miim_d = '0' --tautology for implementation, but makes sense in simulation
report "MIIM: PHY did not give good data bit " & integer'image(cnt);
dreg(cnt) <= miim_d;
else
miim_d <= dreg(cnt);
end if;
if cnt = 0 then
state <= IDLE;
cnt <= 31;
else
cnt <= cnt - 1;
end if;
end if;
end case;
end if;
end if;
end process fsm;
end RTL;
| gpl-3.0 | f8b6a819855bf1828db5e6a3404b9780 | 0.511492 | 3.025339 | false | false | false | false |
sergev/vak-opensource | hardware/vhd2vl/examples/expr.vhd | 1 | 1,277 | library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
entity expr is port( reset, sysclk, ival : in std_logic);
end expr;
architecture rtl of expr is
signal foo : std_logic_vector(13 downto 0);
signal baz : std_logic_vector(2 downto 0);
signal bam : std_logic_vector(22 downto 0);
signal out_i : std_logic_vector(5 downto 3);
signal input_status : std_logic_vector(8 downto 0);
signal enable, debug, aux, outy, dv, value : std_logic;
begin
-- drive input status
input_status <= -- top bits
(foo(9 downto 4) &
(( baz(3 downto 0) and foo(3 downto 0) or
(not baz(3 downto 0) and bam(3 downto 0)))));
-- drive based on foo
out_i <=
-- if secondary enabl is set then drive aux out
(enable and (aux xor outy)) or
-- if debug is enabled
(debug and dv and not enable) or
-- otherwise we drive reg
(not debug and not enable and value);
-- not drive
pfoo: process(reset, sysclk)
begin
if( reset /= '0' ) then
foo <= (others => '0');
elsif( sysclk'event and sysclk = '0' ) then
foo(3*(2-1)) <= (4*(1+2));
bam(foo'range) <= foo;
end if;
end process;
end rtl;
| apache-2.0 | d024f673c0606a8fe4cb25f1a3b4a357 | 0.587314 | 3.423592 | false | false | false | false |
sergev/vak-opensource | hardware/dlx/cache-behaviour.vhdl | 1 | 10,543 | --------------------------------------------------------------------------
--
-- Copyright (C) 1993, Peter J. Ashenden
-- Mail: Dept. Computer Science
-- University of Adelaide, SA 5005, Australia
-- e-mail: [email protected]
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 1, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
--------------------------------------------------------------------------
--
-- $RCSfile: cache-behaviour.vhdl,v $ $Revision: 2.1 $ $Date: 1993/11/02 22:13:32 $
--
--------------------------------------------------------------------------
--
-- Behavioural architecture for cache.
--
use work.bv_arithmetic.bv_to_natural,
work.bv_arithmetic.natural_to_bv;
architecture behaviour of cache is
begin -- behaviour
cache_behaviour : process
constant words_per_line : positive := line_size / 4;
constant number_of_sets : positive := cache_size / line_size / associativity;
subtype word_offset_range is natural range 0 to words_per_line-1;
subtype entry_index_range is natural range 0 to associativity-1;
subtype set_index_range is natural range 0 to number_of_sets-1;
type line is array (word_offset_range) of dlx_word;
type entry is record
tag : natural;
valid : boolean;
dirty : boolean;
data : line;
end record;
type store_array is array (set_index_range, entry_index_range) of entry;
variable store : store_array;
variable cpu_address : natural;
variable word_offset : word_offset_range;
variable set_index : set_index_range;
variable cpu_tag : natural;
variable entry_index : entry_index_range;
variable hit : boolean;
variable next_replacement_entry_index : entry_index_range := 0;
procedure do_read_hit is
begin
cpu_d <= store(set_index, entry_index).data(word_offset);
cpu_ready <= '1' after Tpd_clk_out;
wait until phi2 = '0';
cpu_d <= null after Tpd_clk_out;
cpu_ready <= '0' after Tpd_clk_out;
end do_read_hit;
procedure do_write_through is
begin
wait until phi1 = '1';
if reset = '1' then
return;
end if;
mem_a <= cpu_a after Tpd_clk_out;
mem_width <= cpu_width after Tpd_clk_out;
mem_d <= cpu_d after Tpd_clk_out;
mem_write <= '1' after Tpd_clk_out;
mem_burst <= '0' after Tpd_clk_out;
mem_enable <= '1' after Tpd_clk_out;
wait until mem_ready = '1' or reset = '1';
cpu_ready <= mem_ready after Tpd_clk_out;
wait until phi2 = '0';
mem_d <= null after Tpd_clk_out;
mem_write <= '0' after Tpd_clk_out;
mem_enable <= '0' after Tpd_clk_out;
cpu_ready <= '0' after Tpd_clk_out;
end do_write_through;
procedure do_write_hit is
begin
case cpu_width is
when width_word =>
store(set_index, entry_index).data(word_offset) := cpu_d;
when width_halfword =>
if cpu_a(1) = '0' then -- ms half word
store(set_index, entry_index).data(word_offset)(0 to 15) := cpu_d(0 to 15);
else -- ls half word
store(set_index, entry_index).data(word_offset)(16 to 23) := cpu_d(16 to 23);
end if;
when width_byte =>
if cpu_a(1) = '0' then -- ms half word
if cpu_a(0) = '0' then -- byte 0
store(set_index, entry_index).data(word_offset)(0 to 7) := cpu_d(0 to 7);
else -- byte 1
store(set_index, entry_index).data(word_offset)(8 to 15) := cpu_d(8 to 15);
end if;
else -- ls half word
if cpu_a(0) = '0' then -- byte 2
store(set_index, entry_index).data(word_offset)(16 to 23) := cpu_d(16 to 23);
else -- byte 3
store(set_index, entry_index).data(word_offset)(24 to 31) := cpu_d(24 to 31);
end if;
end if;
end case;
if write_strategy = copy_back then
store(set_index, entry_index).dirty := true;
end if;
--
-- if write_through cache, also update main memory
if write_strategy = write_through then
do_write_through;
else -- copy_back cache
cpu_ready <= '1' after Tpd_clk_out;
wait until phi2 = '0';
cpu_ready <= '0' after Tpd_clk_out;
end if;
end do_write_hit;
procedure copy_back_line is
variable next_address : natural;
variable old_word_offset : natural;
begin
next_address := (store(set_index, entry_index).tag * number_of_sets
+ set_index) * line_size;
wait until phi1 = '1';
if reset = '1' then
return;
end if;
mem_width <= width_word after Tpd_clk_out;
mem_write <= '1' after Tpd_clk_out;
mem_enable <= '1' after Tpd_clk_out;
mem_burst <= '1' after Tpd_clk_out;
old_word_offset := 0;
burst_loop : loop
if old_word_offset = words_per_line-1 then
mem_burst <= '0' after Tpd_clk_out;
end if;
mem_a <= natural_to_bv(next_address, mem_a'length) after Tpd_clk_out;
mem_d <= store(set_index, entry_index).data(old_word_offset) after Tpd_clk_out;
wait_loop : loop
wait until phi2 = '0';
exit burst_loop when reset = '1'
or (mem_ready = '1' and old_word_offset = words_per_line-1);
exit wait_loop when mem_ready = '1';
end loop wait_loop;
old_word_offset := old_word_offset + 1;
next_address := next_address + 4;
end loop burst_loop;
store(set_index, entry_index).dirty := false;
mem_d <= null after Tpd_clk_out;
mem_write <= '0' after Tpd_clk_out;
mem_enable <= '0' after Tpd_clk_out;
end copy_back_line;
procedure fetch_line is
variable next_address : natural;
variable new_word_offset : natural;
begin
next_address := (cpu_address / line_size) * line_size;
wait until phi1 = '1';
if reset = '1' then
return;
end if;
mem_width <= width_word after Tpd_clk_out;
mem_write <= '0' after Tpd_clk_out;
mem_enable <= '1' after Tpd_clk_out;
mem_burst <= '1' after Tpd_clk_out;
new_word_offset := 0;
burst_loop : loop
if new_word_offset = words_per_line-1 then
mem_burst <= '0' after Tpd_clk_out;
end if;
mem_a <= natural_to_bv(next_address, mem_a'length) after Tpd_clk_out;
wait_loop : loop
wait until phi2 = '0';
store(set_index, entry_index).data(new_word_offset) := mem_d;
exit burst_loop when reset = '1'
or (mem_ready = '1' and new_word_offset = words_per_line-1);
exit wait_loop when mem_ready = '1';
end loop wait_loop;
new_word_offset := new_word_offset + 1;
next_address := next_address + 4;
end loop burst_loop;
store(set_index, entry_index).valid := true;
store(set_index, entry_index).tag := cpu_tag;
store(set_index, entry_index).dirty := false;
mem_enable <= '0' after Tpd_clk_out;
end fetch_line;
procedure replace_line is
begin
-- first chose an entry using "random" number generator
entry_index := next_replacement_entry_index;
next_replacement_entry_index
:= (next_replacement_entry_index + 1) mod associativity;
if store(set_index, entry_index).dirty then
copy_back_line;
end if;
fetch_line;
end replace_line;
procedure do_read_miss is
begin
replace_line;
if reset = '1' then
return;
end if;
do_read_hit;
end do_read_miss;
procedure do_write_miss is
begin
-- if write_through cache, just update main memory
if write_strategy = write_through then
do_write_through;
else -- copy_back cache
replace_line;
if reset = '1' then
return;
end if;
do_write_hit;
end if;
end do_write_miss;
begin -- process cache_behaviour
-- reset: initialize outputs and the cache store valid bits
cpu_ready <= '0';
cpu_d <= null;
mem_enable <= '0';
mem_width <= width_word;
mem_write <= '0';
mem_burst <= '0';
mem_a <= X"00000000";
mem_d <= null;
for init_set_index in set_index_range loop
for init_entry_index in entry_index_range loop
store(init_set_index, init_entry_index).valid := false;
store(init_set_index, init_entry_index).dirty := false;
end loop; -- init_entry_index
end loop; -- init_set_index
--
loop
-- wait for a cpu request
wait until phi2 = '1' and cpu_enable = '1';
-- decode address
cpu_address := bv_to_natural(cpu_a);
word_offset := (cpu_address mod line_size) / 4;
set_index := (cpu_address / line_size) mod number_of_sets;
cpu_tag := cpu_address / line_size / number_of_sets;
-- check for hit
hit := false;
for lookup_entry_index in entry_index_range loop
if store(set_index, lookup_entry_index).valid
and store(set_index, lookup_entry_index).tag = cpu_tag then
hit := true;
entry_index := lookup_entry_index;
exit;
end if;
end loop; -- lookup_entry
--
if hit then
if cpu_write = '1' then
do_write_hit;
else
do_read_hit;
end if;
else
if cpu_write = '1' then
do_write_miss;
else
do_read_miss;
end if;
end if;
exit when reset = '1';
end loop;
-- loop exited on reset: wait until it goes inactive
-- then start again
wait until phi2 = '0' and reset = '0';
end process cache_behaviour;
end behaviour;
| apache-2.0 | c13c94ed41f34522f1d74831c8be0db6 | 0.561036 | 3.561824 | false | false | false | false |
epall/Computer.Build | templates/reg.vhdl | 1 | 723 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY reg IS
GENERIC
(
DATA_WIDTH : integer := 8
);
PORT
(
clock : IN std_logic;
data_in : IN std_logic_vector(DATA_WIDTH - 1 DOWNTO 0);
data_out : OUT std_logic_vector(DATA_WIDTH - 1 DOWNTO 0);
wr : IN std_logic;
rd : IN std_logic
);
END reg;
ARCHITECTURE rtl OF reg IS
SIGNAL regval : std_logic_vector(DATA_WIDTH - 1 DOWNTO 0);
BEGIN
WITH rd SELECT
data_out <= regval WHEN '1',
"ZZZZZZZZ" WHEN OTHERS;
PROCESS (clock, wr)
BEGIN
IF (clock'event AND clock = '0' AND wr = '1') THEN
regval <= data_in;
END IF;
END PROCESS;
END rtl;
| mit | 4c6f1a9fba27bc6571fb19f524079197 | 0.578147 | 3.199115 | false | false | false | false |
sergev/vak-opensource | hardware/dlx/ir-behaviour.vhdl | 1 | 2,767 | --------------------------------------------------------------------------
--
-- Copyright (C) 1993, Peter J. Ashenden
-- Mail: Dept. Computer Science
-- University of Adelaide, SA 5005, Australia
-- e-mail: [email protected]
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 1, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
--------------------------------------------------------------------------
--
-- $RCSfile: ir-behaviour.vhdl,v $ $Revision: 2.1 $ $Date: 1993/11/02 18:56:39 $
--
--------------------------------------------------------------------------
--
-- Behavioural architecture of instruction register.
--
use work.dlx_instr.all;
architecture behaviour of ir is
begin
reg: process (d, latch_en, immed_sel1, immed_sel2,
immed_unsigned1, immed_unsigned2, immed_en1, immed_en2)
variable latched_instr : dlx_word;
use work.bv_arithmetic.bv_zext, work.bv_arithmetic.bv_sext;
begin
if latch_en = '1' then
latched_instr := d;
ir_out <= latched_instr after Tpd;
end if;
--
if immed_en1 = '1' then
if immed_sel1 = immed_size_16 then
if immed_unsigned1 = '1' then
immed_q1 <= bv_zext(latched_instr(16 to 31), 32) after Tpd;
else
immed_q1 <= bv_sext(latched_instr(16 to 31), 32) after Tpd;
end if;
else -- immed_sel1 = immed_size_26
if immed_unsigned1 = '1' then
immed_q1 <= bv_zext(latched_instr(6 to 31), 32) after Tpd;
else
immed_q1 <= bv_sext(latched_instr(6 to 31), 32) after Tpd;
end if;
end if;
else
immed_q1 <= null after Tpd;
end if;
--
if immed_en2 = '1' then
if immed_sel2 = immed_size_16 then
if immed_unsigned2 = '1' then
immed_q2 <= bv_zext(latched_instr(16 to 31), 32) after Tpd;
else
immed_q2 <= bv_sext(latched_instr(16 to 31), 32) after Tpd;
end if;
else -- immed_sel2 = immed_size_26
if immed_unsigned2 = '1' then
immed_q2 <= bv_zext(latched_instr(6 to 31), 32) after Tpd;
else
immed_q2 <= bv_sext(latched_instr(6 to 31), 32) after Tpd;
end if;
end if;
else
immed_q2 <= null after Tpd;
end if;
end process reg;
end behaviour;
| apache-2.0 | 3258f6667359e9c1102543aa7ca13ee7 | 0.597037 | 3.382641 | false | false | false | false |
hoglet67/AtomGodilVideo | src/MINIUART/Txunit.vhd | 1 | 3,487 | -------------------------------------------------------------------------------
-- Title : UART
-- Project : UART
-------------------------------------------------------------------------------
-- File : Txunit.vhd
-- Author : Philippe CARTON
-- ([email protected])
-- Organization:
-- Created : 15/12/2001
-- Last update : 8/1/2003
-- Platform : Foundation 3.1i
-- Simulators : ModelSim 5.5b
-- Synthesizers: Xilinx Synthesis
-- Targets : Xilinx Spartan
-- Dependency : IEEE std_logic_1164
-------------------------------------------------------------------------------
-- Description: Txunit is a parallel to serial unit transmitter.
-------------------------------------------------------------------------------
-- Copyright (c) notice
-- This core adheres to the GNU public license
--
-------------------------------------------------------------------------------
-- Revisions :
-- Revision Number :
-- Version :
-- Date :
-- Modifier : name <email>
-- Description :
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity TxUnit is
port (
Clk : in std_logic; -- Clock signal
Reset : in std_logic; -- Reset input
Enable : in std_logic; -- Enable input
LoadA : in std_logic; -- Asynchronous Load
TxD : out std_logic; -- RS-232 data output
Busy : out std_logic; -- Tx Busy
DataI : in std_logic_vector(7 downto 0) -- Byte to transmit
);
end TxUnit;
architecture Behaviour of TxUnit is
component synchroniser
port (
C1 : in std_logic; -- Asynchronous signal
C : in std_logic; -- Clock
O : out Std_logic);-- Synchronised signal
end component;
signal TBuff : std_logic_vector(7 downto 0); -- transmit buffer
signal TReg : std_logic_vector(7 downto 0); -- transmit register
signal TBufL : std_logic; -- Buffer loaded
signal LoadS : std_logic; -- Synchronised load signal
begin
-- Synchronise Load on Clk
SyncLoad : Synchroniser port map (LoadA, Clk, LoadS);
Busy <= LoadS or TBufL;
-- Tx process
TxProc : process(Clk, Reset, Enable, DataI, TBuff, TReg, TBufL)
variable BitPos : INTEGER range 0 to 10; -- Bit position in the frame
begin
if Reset = '1' then
TBufL <= '0';
BitPos := 0;
TxD <= '1';
elsif Rising_Edge(Clk) then
if LoadS = '1' then
TBuff <= DataI;
TBufL <= '1';
end if;
if Enable = '1' then
case BitPos is
when 0 => -- idle or stop bit
TxD <= '1';
if TBufL = '1' then -- start transmit. next is start bit
TReg <= TBuff;
TBufL <= '0';
BitPos := 1;
end if;
when 1 => -- Start bit
TxD <= '0';
BitPos := 2;
when others =>
TxD <= TReg(BitPos-2); -- Serialisation of TReg
BitPos := BitPos + 1;
end case;
if BitPos = 10 then -- bit8. next is stop bit
BitPos := 0;
-- Set the Tx interrupt flag when Tx interrupt is enabled
-- if IntTxEn = '1' then
-- IntTxFlag <= '1';
-- end if;
end if;
end if;
end if;
end process;
end Behaviour;
| apache-2.0 | d0dcf0b6cc00204c0b0adef30bc6a935 | 0.459134 | 4.273284 | false | false | false | false |
sergev/vak-opensource | hardware/dlx/reg_file-behaviour.vhdl | 1 | 2,259 | --------------------------------------------------------------------------
--
-- Copyright (C) 1993, Peter J. Ashenden
-- Mail: Dept. Computer Science
-- University of Adelaide, SA 5005, Australia
-- e-mail: [email protected]
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 1, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
--------------------------------------------------------------------------
--
-- $RCSfile: reg_file-behaviour.vhdl,v $ $Revision: 2.1 $ $Date: 1993/11/02 19:16:52 $
--
--------------------------------------------------------------------------
--
-- Behavioural architecture of register file.
--
architecture behaviour of reg_file is
begin
reg: process (a1, a2, a3, d3, write_en)
use work.bv_arithmetic.bv_to_natural;
constant all_zeros : dlx_word := X"0000_0000";
type register_array is array (reg_index range 1 to 31) of dlx_word;
variable register_file : register_array;
variable reg_index1, reg_index2, reg_index3 : reg_index;
begin
-- do write first if enabled
--
if write_en = '1' then
reg_index3 := bv_to_natural(a3);
if reg_index3 /= 0 then
register_file(reg_index3) := d3;
end if;
end if;
--
-- read port 1
--
reg_index1 := bv_to_natural(a1);
if reg_index1 /= 0 then
q1 <= register_file(reg_index1) after Tac;
else
q1 <= all_zeros after Tac;
end if;
--
-- read port 2
--
reg_index2 := bv_to_natural(a2);
if reg_index2 /= 0 then
q2 <= register_file(reg_index2) after Tac;
else
q2 <= all_zeros after Tac;
end if;
end process reg;
end behaviour;
| apache-2.0 | 2d8214a383be185286d3e817b076faa8 | 0.582559 | 3.643548 | false | false | false | false |
s-kostyuk/course_project_csch | final_processor/control_unit.vhd | 1 | 5,294 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity control_unit is
port(
clk, rst : in STD_LOGIC;
x : in STD_LOGIC_VECTOR(10 downto 1);
y : out STD_LOGIC_VECTOR(25 downto 1);
COP: in std_logic
);
end control_unit;
architecture control_unit of control_unit is
use ieee.std_logic_unsigned.all;
subtype TCommand is std_logic_vector(11 downto 0);
type TROM is array(0 to 54) of TCommand;
constant ROM:TROM := (
-- p, y1, y2, y3, y4
-- p, x, a
"1" & "0001" & "001" & "11" & "00", -- 0
"0" & "0001" & "001" & "01" & "01", -- 1
"1" & "0010" & "000" & "10" & "00", -- 2
"0" & "0010" & "000" & "00" & "00", -- 3
"0" & "0011" & "000" & "10" & "10", -- 4
"1" & "0011" & "001" & "10" & "00", -- 5
"0" & "0100" & "000" & "00" & "00", -- 6
"1" & "0100" & "000" & "01" & "00", -- 7
"1" & "0101" & "001" & "01" & "00", -- 8
"0" & "0000" & "010" & "00" & "00", -- 9
"0" & "0110" & "011" & "00" & "00", --10
"1" & "0000" & "000" & "00" & "00", --11
"0" & "0101" & "000" & "00" & "00", --12
"1" & "0000" & "000" & "11" & "10", --13
"0" & "0001" & "100" & "00" & "00", --14
"1" & "0110" & "010" & "01" & "00", --15
"0" & "1100" & "000" & "00" & "00", --16
"1" & "0000" & "000" & "00" & "00", --17
"0" & "0111" & "101" & "00" & "00", --18
"1" & "0111" & "011" & "00" & "00", --19
"0" & "0000" & "111" & "00" & "11", --20
"1" & "0111" & "011" & "01" & "00", --21
"0" & "1101" & "000" & "00" & "00", --22
"1" & "0000" & "000" & "00" & "00", --23
"0" & "0000" & "110" & "00" & "00", --24
"1" & "0111" & "010" & "11" & "00", --25
"0" & "0000" & "000" & "01" & "01", --26
"1" & "0111" & "100" & "10" & "10", --27
"0" & "1000" & "000" & "00" & "00", --28
"0" & "0000" & "000" & "00" & "10", --29
"1" & "0100" & "100" & "11" & "10", --30
"1" & "1000" & "101" & "11" & "00", --31
"1" & "1010" & "110" & "01" & "10", --32
"1" & "0101" & "110" & "10" & "10", --33
"1" & "1011" & "110" & "10" & "10", --34
"0" & "1011" & "000" & "00" & "00", --35
"1" & "0000" & "000" & "00" & "00", --36
"0" & "0000" & "000" & "11" & "00", --37
"1" & "0000" & "011" & "10" & "10", --38
"1" & "0111" & "101" & "01" & "10", --39
"0" & "1001" & "000" & "00" & "00", --40
"0" & "0000" & "111" & "00" & "00", --41
"1" & "0000" & "011" & "01" & "10", --42
"0" & "1001" & "000" & "00" & "00", --43
"0" & "0000" & "110" & "00" & "00", --44
"1" & "0000" & "011" & "01" & "10", --45
"1" & "1001" & "110" & "00" & "10", --46
"0" & "0000" & "110" & "00" & "00", --47
"1" & "0000" & "100" & "00" & "00", --48
"0" & "0000" & "111" & "00" & "00", --49
"1" & "0000" & "100" & "00" & "00", --50
"1" & "0101" & "100" & "01" & "10", --51
"1" & "1011" & "100" & "01" & "10", --52
"0" & "1010" & "000" & "00" & "00", --53
"1" & "0000" & "100" & "01" & "10" --54
);
signal RegCom:TCommand;
signal PC:integer;
signal x_decoded: std_logic;
signal y1_decoded: std_logic_vector(15 downto 0);
signal y2_decoded: std_logic_vector(7 downto 0);
signal y3_decoded: std_logic_vector(3 downto 0);
signal y4_decoded: std_logic_vector(3 downto 0);
signal not_p: std_logic;
signal x_buf: std_logic_vector(15 downto 0);
component decoder is
generic(
N: integer := 4
);
port(D: in std_logic_vector (N-1 downto 0);
En: in std_logic;
Q: out std_logic_vector (2**N -1 downto 0)
);
end component;
component mx is
generic(
N: integer := 4
);
port(
A: in std_logic_vector(N-1 downto 0);
D: in std_logic_vector(2**N-1 downto 0);
En: in std_logic;
Q: out std_logic
);
end component;
begin
not_p <= not RegCom(11);
x_buf <= "0000" & x & COP & "0";
x_mx: mx
generic map(N => 4)
port map(A => RegCom(10 downto 7), D => x_buf, En => '0', Q => x_decoded);
y1_dc: decoder
generic map(N => 4)
port map(D => RegCom(10 downto 7), En => RegCom(11), Q => y1_decoded);
y2_dc: decoder
generic map(N => 3)
port map(D => RegCom(6 downto 4), En => RegCom(11), Q => y2_decoded);
y3_dc: decoder
generic map(N => 2)
port map(D => RegCom(3 downto 2), En => RegCom(11), Q => y3_decoded);
y4_dc: decoder
generic map(N => 2)
port map(D => RegCom(1 downto 0), En => RegCom(11), Q => y4_decoded);
process(rst,clk) is
variable PCv:integer range 0 to 54;
begin
if rst='0' then PCv:=0;
elsif rising_edge(clk) then
if RegCom(11)='1' and x_decoded = '0' then
PCv:=conv_integer(RegCom(6 downto 1));
else
PCv:=PCv+1;
end if;
end if;
RegCom<=ROM(PCv);
PC<=PCv;
end process;
y(1) <= y1_decoded(1);
y(5) <= y1_decoded(2);
y(6) <= y1_decoded(3);
y(9) <= y1_decoded(4);
y(10) <= y1_decoded(5);
y(12) <= y1_decoded(6);
y(15) <= y1_decoded(7);
y(20) <= y1_decoded(8);
y(21) <= y1_decoded(9);
y(22) <= y1_decoded(10);
y(23) <= y1_decoded(11);
y(24) <= y1_decoded(12);
y(25) <= y1_decoded(13);
y(2) <= y2_decoded(1);
y(11) <= y2_decoded(2);
y(13) <= y2_decoded(3);
y(14) <= y2_decoded(4);
y(16) <= y2_decoded(5);
y(17) <= y2_decoded(6);
y(18) <= y2_decoded(7);
y(3) <= y3_decoded(1);
y(7) <= y3_decoded(2);
y(19) <= y3_decoded(3);
y(4) <= y4_decoded(1);
y(8) <= y4_decoded(2);
end architecture control_unit; | mit | 854d77b98daff7943132610a7b21598f | 0.463166 | 2.137263 | false | false | false | false |
FinnK/lems2hdl | work/N3_pointCellCondBased/ISIM_output/top_synth.vhdl | 1 | 43,854 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use ieee_proposed.fixed_float_types.ALL;
use std.textio.all;
use ieee.std_logic_textio.all; -- if you're saving this type of signal
use IEEE.numeric_std.all;
entity top_synth is
Port ( clk : in STD_LOGIC; --SYSTEM CLOCK, THIS ITSELF DOES NOT SIGNIFY TIME STEPS - AKA A SINGLE TIMESTEP MAY TAKE MANY CLOCK CYCLES
init_model: in STD_LOGIC; --SYNCHRONOUS RESET
step_once_go : in STD_LOGIC; --signals to the neuron from the core that a time step is to be simulated
step_once_complete : out STD_LOGIC; --signals to the core that a time step has finished
eventport_in_spike_aggregate : in STD_LOGIC_VECTOR(511 downto 0);
neuron_model_eventport_out_spike : out STD_LOGIC;
neuron_model_param_voltage_v0 : in sfixed (2 downto -22);
neuron_model_param_voltage_thresh : in sfixed (2 downto -22);
neuron_model_param_capacitance_C : in sfixed (-33 downto -47);
neuron_model_param_capacitance_inv_C_inv : in sfixed (47 downto 33);
neuron_model_exposure_voltage_v : out sfixed (2 downto -22);
neuron_model_stateCURRENT_voltage_v : out sfixed (2 downto -22);
neuron_model_stateRESTORE_voltage_v : in sfixed (2 downto -22);
neuron_model_stateCURRENT_none_spiking : out sfixed (18 downto -13);
neuron_model_stateRESTORE_none_spiking : in sfixed (18 downto -13);
neuron_model_param_none_leak_number : in sfixed (18 downto -13);
neuron_model_param_voltage_leak_erev : in sfixed (2 downto -22);
neuron_model_exposure_current_leak_i : out sfixed (-28 downto -53);
neuron_model_stateCURRENT_current_leak_i : out sfixed (-28 downto -53);
neuron_model_stateRESTORE_current_leak_i : in sfixed (-28 downto -53);
neuron_model_param_conductance_leak_passive_conductance : in sfixed (-22 downto -53);
neuron_model_exposure_conductance_leak_passive_g : out sfixed (-22 downto -53);
neuron_model_stateCURRENT_conductance_leak_passive_g : out sfixed (-22 downto -53);
neuron_model_stateRESTORE_conductance_leak_passive_g : in sfixed (-22 downto -53);
neuron_model_param_none_naChans_number : in sfixed (18 downto -13);
neuron_model_param_voltage_naChans_erev : in sfixed (2 downto -22);
neuron_model_exposure_current_naChans_i : out sfixed (-28 downto -53);
neuron_model_stateCURRENT_current_naChans_i : out sfixed (-28 downto -53);
neuron_model_stateRESTORE_current_naChans_i : in sfixed (-28 downto -53);
neuron_model_param_conductance_naChans_na_conductance : in sfixed (-22 downto -53);
neuron_model_exposure_conductance_naChans_na_g : out sfixed (-22 downto -53);
neuron_model_stateCURRENT_conductance_naChans_na_g : out sfixed (-22 downto -53);
neuron_model_stateRESTORE_conductance_naChans_na_g : in sfixed (-22 downto -53);
neuron_model_param_none_naChans_na_m_instances : in sfixed (18 downto -13);
neuron_model_exposure_none_naChans_na_m_fcond : out sfixed (18 downto -13);
neuron_model_exposure_none_naChans_na_m_q : out sfixed (18 downto -13);
neuron_model_stateCURRENT_none_naChans_na_m_q : out sfixed (18 downto -13);
neuron_model_stateRESTORE_none_naChans_na_m_q : in sfixed (18 downto -13);
neuron_model_stateCURRENT_none_naChans_na_m_fcond : out sfixed (18 downto -13);
neuron_model_stateRESTORE_none_naChans_na_m_fcond : in sfixed (18 downto -13);
neuron_model_param_per_time_naChans_na_m_forwardRatem1_rate : in sfixed (18 downto -2);
neuron_model_param_voltage_naChans_na_m_forwardRatem1_midpoint : in sfixed (2 downto -22);
neuron_model_param_voltage_naChans_na_m_forwardRatem1_scale : in sfixed (2 downto -22);
neuron_model_param_voltage_inv_naChans_na_m_forwardRatem1_scale_inv : in sfixed (22 downto -2);
neuron_model_exposure_per_time_naChans_na_m_forwardRatem1_r : out sfixed (18 downto -2);
neuron_model_stateCURRENT_per_time_naChans_na_m_forwardRatem1_r : out sfixed (18 downto -2);
neuron_model_stateRESTORE_per_time_naChans_na_m_forwardRatem1_r : in sfixed (18 downto -2);
neuron_model_param_per_time_naChans_na_m_reverseRatem1_rate : in sfixed (18 downto -2);
neuron_model_param_voltage_naChans_na_m_reverseRatem1_midpoint : in sfixed (2 downto -22);
neuron_model_param_voltage_naChans_na_m_reverseRatem1_scale : in sfixed (2 downto -22);
neuron_model_param_voltage_inv_naChans_na_m_reverseRatem1_scale_inv : in sfixed (22 downto -2);
neuron_model_exposure_per_time_naChans_na_m_reverseRatem1_r : out sfixed (18 downto -2);
neuron_model_stateCURRENT_per_time_naChans_na_m_reverseRatem1_r : out sfixed (18 downto -2);
neuron_model_stateRESTORE_per_time_naChans_na_m_reverseRatem1_r : in sfixed (18 downto -2);
neuron_model_param_none_naChans_na_h_instances : in sfixed (18 downto -13);
neuron_model_exposure_none_naChans_na_h_fcond : out sfixed (18 downto -13);
neuron_model_exposure_none_naChans_na_h_q : out sfixed (18 downto -13);
neuron_model_stateCURRENT_none_naChans_na_h_q : out sfixed (18 downto -13);
neuron_model_stateRESTORE_none_naChans_na_h_q : in sfixed (18 downto -13);
neuron_model_stateCURRENT_none_naChans_na_h_fcond : out sfixed (18 downto -13);
neuron_model_stateRESTORE_none_naChans_na_h_fcond : in sfixed (18 downto -13);
neuron_model_param_per_time_naChans_na_h_forwardRateh1_rate : in sfixed (18 downto -2);
neuron_model_param_voltage_naChans_na_h_forwardRateh1_midpoint : in sfixed (2 downto -22);
neuron_model_param_voltage_naChans_na_h_forwardRateh1_scale : in sfixed (2 downto -22);
neuron_model_param_voltage_inv_naChans_na_h_forwardRateh1_scale_inv : in sfixed (22 downto -2);
neuron_model_exposure_per_time_naChans_na_h_forwardRateh1_r : out sfixed (18 downto -2);
neuron_model_stateCURRENT_per_time_naChans_na_h_forwardRateh1_r : out sfixed (18 downto -2);
neuron_model_stateRESTORE_per_time_naChans_na_h_forwardRateh1_r : in sfixed (18 downto -2);
neuron_model_param_per_time_naChans_na_h_reverseRateh1_rate : in sfixed (18 downto -2);
neuron_model_param_voltage_naChans_na_h_reverseRateh1_midpoint : in sfixed (2 downto -22);
neuron_model_param_voltage_naChans_na_h_reverseRateh1_scale : in sfixed (2 downto -22);
neuron_model_param_voltage_inv_naChans_na_h_reverseRateh1_scale_inv : in sfixed (22 downto -2);
neuron_model_exposure_per_time_naChans_na_h_reverseRateh1_r : out sfixed (18 downto -2);
neuron_model_stateCURRENT_per_time_naChans_na_h_reverseRateh1_r : out sfixed (18 downto -2);
neuron_model_stateRESTORE_per_time_naChans_na_h_reverseRateh1_r : in sfixed (18 downto -2);
neuron_model_param_none_kChans_number : in sfixed (18 downto -13);
neuron_model_param_voltage_kChans_erev : in sfixed (2 downto -22);
neuron_model_exposure_current_kChans_i : out sfixed (-28 downto -53);
neuron_model_stateCURRENT_current_kChans_i : out sfixed (-28 downto -53);
neuron_model_stateRESTORE_current_kChans_i : in sfixed (-28 downto -53);
neuron_model_param_conductance_kChans_k_conductance : in sfixed (-22 downto -53);
neuron_model_exposure_conductance_kChans_k_g : out sfixed (-22 downto -53);
neuron_model_stateCURRENT_conductance_kChans_k_g : out sfixed (-22 downto -53);
neuron_model_stateRESTORE_conductance_kChans_k_g : in sfixed (-22 downto -53);
neuron_model_param_none_kChans_k_n_instances : in sfixed (18 downto -13);
neuron_model_exposure_none_kChans_k_n_fcond : out sfixed (18 downto -13);
neuron_model_exposure_none_kChans_k_n_q : out sfixed (18 downto -13);
neuron_model_stateCURRENT_none_kChans_k_n_q : out sfixed (18 downto -13);
neuron_model_stateRESTORE_none_kChans_k_n_q : in sfixed (18 downto -13);
neuron_model_stateCURRENT_none_kChans_k_n_fcond : out sfixed (18 downto -13);
neuron_model_stateRESTORE_none_kChans_k_n_fcond : in sfixed (18 downto -13);
neuron_model_param_per_time_kChans_k_n_forwardRaten1_rate : in sfixed (18 downto -2);
neuron_model_param_voltage_kChans_k_n_forwardRaten1_midpoint : in sfixed (2 downto -22);
neuron_model_param_voltage_kChans_k_n_forwardRaten1_scale : in sfixed (2 downto -22);
neuron_model_param_voltage_inv_kChans_k_n_forwardRaten1_scale_inv : in sfixed (22 downto -2);
neuron_model_exposure_per_time_kChans_k_n_forwardRaten1_r : out sfixed (18 downto -2);
neuron_model_stateCURRENT_per_time_kChans_k_n_forwardRaten1_r : out sfixed (18 downto -2);
neuron_model_stateRESTORE_per_time_kChans_k_n_forwardRaten1_r : in sfixed (18 downto -2);
neuron_model_param_per_time_kChans_k_n_reverseRaten1_rate : in sfixed (18 downto -2);
neuron_model_param_voltage_kChans_k_n_reverseRaten1_midpoint : in sfixed (2 downto -22);
neuron_model_param_voltage_kChans_k_n_reverseRaten1_scale : in sfixed (2 downto -22);
neuron_model_param_voltage_inv_kChans_k_n_reverseRaten1_scale_inv : in sfixed (22 downto -2);
neuron_model_exposure_per_time_kChans_k_n_reverseRaten1_r : out sfixed (18 downto -2);
neuron_model_stateCURRENT_per_time_kChans_k_n_reverseRaten1_r : out sfixed (18 downto -2);
neuron_model_stateRESTORE_per_time_kChans_k_n_reverseRaten1_r : in sfixed (18 downto -2);
neuron_model_param_time_synapsemodel_tauDecay : in sfixed (6 downto -18);
neuron_model_param_conductance_synapsemodel_gbase : in sfixed (-22 downto -53);
neuron_model_param_voltage_synapsemodel_erev : in sfixed (2 downto -22);
neuron_model_param_time_inv_synapsemodel_tauDecay_inv : in sfixed (18 downto -6);
neuron_model_exposure_current_synapsemodel_i : out sfixed (-28 downto -53);
neuron_model_exposure_conductance_synapsemodel_g : out sfixed (-22 downto -53);
neuron_model_stateCURRENT_conductance_synapsemodel_g : out sfixed (-22 downto -53);
neuron_model_stateRESTORE_conductance_synapsemodel_g : in sfixed (-22 downto -53);
neuron_model_stateCURRENT_current_synapsemodel_i : out sfixed (-28 downto -53);
neuron_model_stateRESTORE_current_synapsemodel_i : in sfixed (-28 downto -53);
sysparam_time_timestep : sfixed (-6 downto -22);
sysparam_time_simtime : sfixed (6 downto -22)
);
end top_synth;
architecture top of top_synth is
signal step_once_complete_int : STD_LOGIC;
signal seven_steps_done : STD_LOGIC;
signal step_once_go_int : STD_LOGIC := '0';
signal seven_steps_done_shot_done : STD_LOGIC;
signal seven_steps_done_shot : STD_LOGIC;
signal seven_steps_done_shot2 : STD_LOGIC;
signal COUNT : unsigned(2 downto 0) := "110";
signal seven_steps_done_next : STD_LOGIC;
signal COUNT_next : unsigned(2 downto 0) := "110";
signal step_once_go_int_next : STD_LOGIC := '0';
signal neuron_model_eventport_out_spike_int : STD_LOGIC;
signal neuron_model_eventport_out_spike_int2 : STD_LOGIC;
signal neuron_model_eventport_out_spike_int3 : STD_LOGIC;
component neuron_model
Port ( clk : in STD_LOGIC; --SYSTEM CLOCK, THIS ITSELF DOES NOT SIGNIFY TIME STEPS - AKA A SINGLE TIMESTEP MAY TAKE MANY CLOCK CYCLES
init_model: in STD_LOGIC; --SYNCHRONOUS RESET
step_once_go : in STD_LOGIC; --signals to the neuron from the core that a time step is to be simulated
step_once_complete : out STD_LOGIC; --signals to the core that a time step has finished
eventport_in_spike_aggregate : in STD_LOGIC_VECTOR(511 downto 0);
eventport_out_spike : out STD_LOGIC;
param_voltage_v0 : in sfixed (2 downto -22);
param_voltage_thresh : in sfixed (2 downto -22);
param_capacitance_C : in sfixed (-33 downto -47);
param_capacitance_inv_C_inv : in sfixed (47 downto 33);
exposure_voltage_v : out sfixed (2 downto -22);
statevariable_voltage_v_out : out sfixed (2 downto -22);
statevariable_voltage_v_in : in sfixed (2 downto -22);
statevariable_none_spiking_out : out sfixed (18 downto -13);
statevariable_none_spiking_in : in sfixed (18 downto -13);
param_none_leak_number : in sfixed (18 downto -13);
param_voltage_leak_erev : in sfixed (2 downto -22);
exposure_current_leak_i : out sfixed (-28 downto -53);
derivedvariable_current_leak_i_out : out sfixed (-28 downto -53);
derivedvariable_current_leak_i_in : in sfixed (-28 downto -53);
param_conductance_leak_passive_conductance : in sfixed (-22 downto -53);
exposure_conductance_leak_passive_g : out sfixed (-22 downto -53);
derivedvariable_conductance_leak_passive_g_out : out sfixed (-22 downto -53);
derivedvariable_conductance_leak_passive_g_in : in sfixed (-22 downto -53);
param_none_naChans_number : in sfixed (18 downto -13);
param_voltage_naChans_erev : in sfixed (2 downto -22);
exposure_current_naChans_i : out sfixed (-28 downto -53);
derivedvariable_current_naChans_i_out : out sfixed (-28 downto -53);
derivedvariable_current_naChans_i_in : in sfixed (-28 downto -53);
param_conductance_naChans_na_conductance : in sfixed (-22 downto -53);
exposure_conductance_naChans_na_g : out sfixed (-22 downto -53);
derivedvariable_conductance_naChans_na_g_out : out sfixed (-22 downto -53);
derivedvariable_conductance_naChans_na_g_in : in sfixed (-22 downto -53);
param_none_naChans_na_m_instances : in sfixed (18 downto -13);
exposure_none_naChans_na_m_fcond : out sfixed (18 downto -13);
exposure_none_naChans_na_m_q : out sfixed (18 downto -13);
statevariable_none_naChans_na_m_q_out : out sfixed (18 downto -13);
statevariable_none_naChans_na_m_q_in : in sfixed (18 downto -13);
derivedvariable_none_naChans_na_m_fcond_out : out sfixed (18 downto -13);
derivedvariable_none_naChans_na_m_fcond_in : in sfixed (18 downto -13);
param_per_time_naChans_na_m_forwardRatem1_rate : in sfixed (18 downto -2);
param_voltage_naChans_na_m_forwardRatem1_midpoint : in sfixed (2 downto -22);
param_voltage_naChans_na_m_forwardRatem1_scale : in sfixed (2 downto -22);
param_voltage_inv_naChans_na_m_forwardRatem1_scale_inv : in sfixed (22 downto -2);
exposure_per_time_naChans_na_m_forwardRatem1_r : out sfixed (18 downto -2);
derivedvariable_per_time_naChans_na_m_forwardRatem1_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_naChans_na_m_forwardRatem1_r_in : in sfixed (18 downto -2);
param_per_time_naChans_na_m_reverseRatem1_rate : in sfixed (18 downto -2);
param_voltage_naChans_na_m_reverseRatem1_midpoint : in sfixed (2 downto -22);
param_voltage_naChans_na_m_reverseRatem1_scale : in sfixed (2 downto -22);
param_voltage_inv_naChans_na_m_reverseRatem1_scale_inv : in sfixed (22 downto -2);
exposure_per_time_naChans_na_m_reverseRatem1_r : out sfixed (18 downto -2);
derivedvariable_per_time_naChans_na_m_reverseRatem1_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_naChans_na_m_reverseRatem1_r_in : in sfixed (18 downto -2);
param_none_naChans_na_h_instances : in sfixed (18 downto -13);
exposure_none_naChans_na_h_fcond : out sfixed (18 downto -13);
exposure_none_naChans_na_h_q : out sfixed (18 downto -13);
statevariable_none_naChans_na_h_q_out : out sfixed (18 downto -13);
statevariable_none_naChans_na_h_q_in : in sfixed (18 downto -13);
derivedvariable_none_naChans_na_h_fcond_out : out sfixed (18 downto -13);
derivedvariable_none_naChans_na_h_fcond_in : in sfixed (18 downto -13);
param_per_time_naChans_na_h_forwardRateh1_rate : in sfixed (18 downto -2);
param_voltage_naChans_na_h_forwardRateh1_midpoint : in sfixed (2 downto -22);
param_voltage_naChans_na_h_forwardRateh1_scale : in sfixed (2 downto -22);
param_voltage_inv_naChans_na_h_forwardRateh1_scale_inv : in sfixed (22 downto -2);
exposure_per_time_naChans_na_h_forwardRateh1_r : out sfixed (18 downto -2);
derivedvariable_per_time_naChans_na_h_forwardRateh1_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_naChans_na_h_forwardRateh1_r_in : in sfixed (18 downto -2);
param_per_time_naChans_na_h_reverseRateh1_rate : in sfixed (18 downto -2);
param_voltage_naChans_na_h_reverseRateh1_midpoint : in sfixed (2 downto -22);
param_voltage_naChans_na_h_reverseRateh1_scale : in sfixed (2 downto -22);
param_voltage_inv_naChans_na_h_reverseRateh1_scale_inv : in sfixed (22 downto -2);
exposure_per_time_naChans_na_h_reverseRateh1_r : out sfixed (18 downto -2);
derivedvariable_per_time_naChans_na_h_reverseRateh1_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_naChans_na_h_reverseRateh1_r_in : in sfixed (18 downto -2);
param_none_kChans_number : in sfixed (18 downto -13);
param_voltage_kChans_erev : in sfixed (2 downto -22);
exposure_current_kChans_i : out sfixed (-28 downto -53);
derivedvariable_current_kChans_i_out : out sfixed (-28 downto -53);
derivedvariable_current_kChans_i_in : in sfixed (-28 downto -53);
param_conductance_kChans_k_conductance : in sfixed (-22 downto -53);
exposure_conductance_kChans_k_g : out sfixed (-22 downto -53);
derivedvariable_conductance_kChans_k_g_out : out sfixed (-22 downto -53);
derivedvariable_conductance_kChans_k_g_in : in sfixed (-22 downto -53);
param_none_kChans_k_n_instances : in sfixed (18 downto -13);
exposure_none_kChans_k_n_fcond : out sfixed (18 downto -13);
exposure_none_kChans_k_n_q : out sfixed (18 downto -13);
statevariable_none_kChans_k_n_q_out : out sfixed (18 downto -13);
statevariable_none_kChans_k_n_q_in : in sfixed (18 downto -13);
derivedvariable_none_kChans_k_n_fcond_out : out sfixed (18 downto -13);
derivedvariable_none_kChans_k_n_fcond_in : in sfixed (18 downto -13);
param_per_time_kChans_k_n_forwardRaten1_rate : in sfixed (18 downto -2);
param_voltage_kChans_k_n_forwardRaten1_midpoint : in sfixed (2 downto -22);
param_voltage_kChans_k_n_forwardRaten1_scale : in sfixed (2 downto -22);
param_voltage_inv_kChans_k_n_forwardRaten1_scale_inv : in sfixed (22 downto -2);
exposure_per_time_kChans_k_n_forwardRaten1_r : out sfixed (18 downto -2);
derivedvariable_per_time_kChans_k_n_forwardRaten1_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_kChans_k_n_forwardRaten1_r_in : in sfixed (18 downto -2);
param_per_time_kChans_k_n_reverseRaten1_rate : in sfixed (18 downto -2);
param_voltage_kChans_k_n_reverseRaten1_midpoint : in sfixed (2 downto -22);
param_voltage_kChans_k_n_reverseRaten1_scale : in sfixed (2 downto -22);
param_voltage_inv_kChans_k_n_reverseRaten1_scale_inv : in sfixed (22 downto -2);
exposure_per_time_kChans_k_n_reverseRaten1_r : out sfixed (18 downto -2);
derivedvariable_per_time_kChans_k_n_reverseRaten1_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_kChans_k_n_reverseRaten1_r_in : in sfixed (18 downto -2);
param_time_synapsemodel_tauDecay : in sfixed (6 downto -18);
param_conductance_synapsemodel_gbase : in sfixed (-22 downto -53);
param_voltage_synapsemodel_erev : in sfixed (2 downto -22);
param_time_inv_synapsemodel_tauDecay_inv : in sfixed (18 downto -6);
exposure_current_synapsemodel_i : out sfixed (-28 downto -53);
exposure_conductance_synapsemodel_g : out sfixed (-22 downto -53);
statevariable_conductance_synapsemodel_g_out : out sfixed (-22 downto -53);
statevariable_conductance_synapsemodel_g_in : in sfixed (-22 downto -53);
derivedvariable_current_synapsemodel_i_out : out sfixed (-28 downto -53);
derivedvariable_current_synapsemodel_i_in : in sfixed (-28 downto -53);
sysparam_time_timestep : sfixed (-6 downto -22);
sysparam_time_simtime : sfixed (6 downto -22)
);
end component;
signal neuron_model_eventport_out_spike_out : STD_LOGIC := '0';
signal neuron_model_statevariable_voltage_v_out_int : sfixed (2 downto -22);signal neuron_model_statevariable_voltage_v_in_int : sfixed (2 downto -22);signal neuron_model_statevariable_none_spiking_out_int : sfixed (18 downto -13);signal neuron_model_statevariable_none_spiking_in_int : sfixed (18 downto -13);signal neuron_model_derivedvariable_current_leak_i_out_int : sfixed (-28 downto -53);signal neuron_model_derivedvariable_current_leak_i_in_int : sfixed (-28 downto -53);signal neuron_model_derivedvariable_conductance_leak_passive_g_out_int : sfixed (-22 downto -53);signal neuron_model_derivedvariable_conductance_leak_passive_g_in_int : sfixed (-22 downto -53);signal neuron_model_derivedvariable_current_naChans_i_out_int : sfixed (-28 downto -53);signal neuron_model_derivedvariable_current_naChans_i_in_int : sfixed (-28 downto -53);signal neuron_model_derivedvariable_conductance_naChans_na_g_out_int : sfixed (-22 downto -53);signal neuron_model_derivedvariable_conductance_naChans_na_g_in_int : sfixed (-22 downto -53);signal neuron_model_statevariable_none_naChans_na_m_q_out_int : sfixed (18 downto -13);signal neuron_model_statevariable_none_naChans_na_m_q_in_int : sfixed (18 downto -13);signal neuron_model_derivedvariable_none_naChans_na_m_fcond_out_int : sfixed (18 downto -13);signal neuron_model_derivedvariable_none_naChans_na_m_fcond_in_int : sfixed (18 downto -13);signal neuron_model_derivedvariable_per_time_naChans_na_m_forwardRatem1_r_out_int : sfixed (18 downto -2);signal neuron_model_derivedvariable_per_time_naChans_na_m_forwardRatem1_r_in_int : sfixed (18 downto -2);signal neuron_model_derivedvariable_per_time_naChans_na_m_reverseRatem1_r_out_int : sfixed (18 downto -2);signal neuron_model_derivedvariable_per_time_naChans_na_m_reverseRatem1_r_in_int : sfixed (18 downto -2);signal neuron_model_statevariable_none_naChans_na_h_q_out_int : sfixed (18 downto -13);signal neuron_model_statevariable_none_naChans_na_h_q_in_int : sfixed (18 downto -13);signal neuron_model_derivedvariable_none_naChans_na_h_fcond_out_int : sfixed (18 downto -13);signal neuron_model_derivedvariable_none_naChans_na_h_fcond_in_int : sfixed (18 downto -13);signal neuron_model_derivedvariable_per_time_naChans_na_h_forwardRateh1_r_out_int : sfixed (18 downto -2);signal neuron_model_derivedvariable_per_time_naChans_na_h_forwardRateh1_r_in_int : sfixed (18 downto -2);signal neuron_model_derivedvariable_per_time_naChans_na_h_reverseRateh1_r_out_int : sfixed (18 downto -2);signal neuron_model_derivedvariable_per_time_naChans_na_h_reverseRateh1_r_in_int : sfixed (18 downto -2);signal neuron_model_derivedvariable_current_kChans_i_out_int : sfixed (-28 downto -53);signal neuron_model_derivedvariable_current_kChans_i_in_int : sfixed (-28 downto -53);signal neuron_model_derivedvariable_conductance_kChans_k_g_out_int : sfixed (-22 downto -53);signal neuron_model_derivedvariable_conductance_kChans_k_g_in_int : sfixed (-22 downto -53);signal neuron_model_statevariable_none_kChans_k_n_q_out_int : sfixed (18 downto -13);signal neuron_model_statevariable_none_kChans_k_n_q_in_int : sfixed (18 downto -13);signal neuron_model_derivedvariable_none_kChans_k_n_fcond_out_int : sfixed (18 downto -13);signal neuron_model_derivedvariable_none_kChans_k_n_fcond_in_int : sfixed (18 downto -13);signal neuron_model_derivedvariable_per_time_kChans_k_n_forwardRaten1_r_out_int : sfixed (18 downto -2);signal neuron_model_derivedvariable_per_time_kChans_k_n_forwardRaten1_r_in_int : sfixed (18 downto -2);signal neuron_model_derivedvariable_per_time_kChans_k_n_reverseRaten1_r_out_int : sfixed (18 downto -2);signal neuron_model_derivedvariable_per_time_kChans_k_n_reverseRaten1_r_in_int : sfixed (18 downto -2);signal neuron_model_statevariable_conductance_synapsemodel_g_out_int : sfixed (-22 downto -53);signal neuron_model_statevariable_conductance_synapsemodel_g_in_int : sfixed (-22 downto -53);signal neuron_model_derivedvariable_current_synapsemodel_i_out_int : sfixed (-28 downto -53);signal neuron_model_derivedvariable_current_synapsemodel_i_in_int : sfixed (-28 downto -53);
begin
neuron_model_uut : neuron_model
port map ( clk => clk,
init_model=> init_model,
step_once_go => step_once_go_int,
step_once_complete => step_once_complete_int,
eventport_in_spike_aggregate => eventport_in_spike_aggregate,
eventport_out_spike => neuron_model_eventport_out_spike_int ,
param_voltage_v0 => neuron_model_param_voltage_v0 ,
param_voltage_thresh => neuron_model_param_voltage_thresh ,
param_capacitance_C => neuron_model_param_capacitance_C ,
param_capacitance_inv_C_inv => neuron_model_param_capacitance_inv_C_inv ,
statevariable_voltage_v_out => neuron_model_statevariable_voltage_v_out_int,
statevariable_voltage_v_in => neuron_model_statevariable_voltage_v_in_int,
statevariable_none_spiking_out => neuron_model_statevariable_none_spiking_out_int,
statevariable_none_spiking_in => neuron_model_statevariable_none_spiking_in_int,
param_none_leak_number => neuron_model_param_none_leak_number ,
param_voltage_leak_erev => neuron_model_param_voltage_leak_erev ,
derivedvariable_current_leak_i_out => neuron_model_derivedvariable_current_leak_i_out_int,
derivedvariable_current_leak_i_in => neuron_model_derivedvariable_current_leak_i_in_int,
param_conductance_leak_passive_conductance => neuron_model_param_conductance_leak_passive_conductance ,
derivedvariable_conductance_leak_passive_g_out => neuron_model_derivedvariable_conductance_leak_passive_g_out_int,
derivedvariable_conductance_leak_passive_g_in => neuron_model_derivedvariable_conductance_leak_passive_g_in_int,
param_none_naChans_number => neuron_model_param_none_naChans_number ,
param_voltage_naChans_erev => neuron_model_param_voltage_naChans_erev ,
derivedvariable_current_naChans_i_out => neuron_model_derivedvariable_current_naChans_i_out_int,
derivedvariable_current_naChans_i_in => neuron_model_derivedvariable_current_naChans_i_in_int,
param_conductance_naChans_na_conductance => neuron_model_param_conductance_naChans_na_conductance ,
derivedvariable_conductance_naChans_na_g_out => neuron_model_derivedvariable_conductance_naChans_na_g_out_int,
derivedvariable_conductance_naChans_na_g_in => neuron_model_derivedvariable_conductance_naChans_na_g_in_int,
param_none_naChans_na_m_instances => neuron_model_param_none_naChans_na_m_instances ,
statevariable_none_naChans_na_m_q_out => neuron_model_statevariable_none_naChans_na_m_q_out_int,
statevariable_none_naChans_na_m_q_in => neuron_model_statevariable_none_naChans_na_m_q_in_int,
derivedvariable_none_naChans_na_m_fcond_out => neuron_model_derivedvariable_none_naChans_na_m_fcond_out_int,
derivedvariable_none_naChans_na_m_fcond_in => neuron_model_derivedvariable_none_naChans_na_m_fcond_in_int,
param_per_time_naChans_na_m_forwardRatem1_rate => neuron_model_param_per_time_naChans_na_m_forwardRatem1_rate ,
param_voltage_naChans_na_m_forwardRatem1_midpoint => neuron_model_param_voltage_naChans_na_m_forwardRatem1_midpoint ,
param_voltage_naChans_na_m_forwardRatem1_scale => neuron_model_param_voltage_naChans_na_m_forwardRatem1_scale ,
param_voltage_inv_naChans_na_m_forwardRatem1_scale_inv => neuron_model_param_voltage_inv_naChans_na_m_forwardRatem1_scale_inv ,
derivedvariable_per_time_naChans_na_m_forwardRatem1_r_out => neuron_model_derivedvariable_per_time_naChans_na_m_forwardRatem1_r_out_int,
derivedvariable_per_time_naChans_na_m_forwardRatem1_r_in => neuron_model_derivedvariable_per_time_naChans_na_m_forwardRatem1_r_in_int,
param_per_time_naChans_na_m_reverseRatem1_rate => neuron_model_param_per_time_naChans_na_m_reverseRatem1_rate ,
param_voltage_naChans_na_m_reverseRatem1_midpoint => neuron_model_param_voltage_naChans_na_m_reverseRatem1_midpoint ,
param_voltage_naChans_na_m_reverseRatem1_scale => neuron_model_param_voltage_naChans_na_m_reverseRatem1_scale ,
param_voltage_inv_naChans_na_m_reverseRatem1_scale_inv => neuron_model_param_voltage_inv_naChans_na_m_reverseRatem1_scale_inv ,
derivedvariable_per_time_naChans_na_m_reverseRatem1_r_out => neuron_model_derivedvariable_per_time_naChans_na_m_reverseRatem1_r_out_int,
derivedvariable_per_time_naChans_na_m_reverseRatem1_r_in => neuron_model_derivedvariable_per_time_naChans_na_m_reverseRatem1_r_in_int,
param_none_naChans_na_h_instances => neuron_model_param_none_naChans_na_h_instances ,
statevariable_none_naChans_na_h_q_out => neuron_model_statevariable_none_naChans_na_h_q_out_int,
statevariable_none_naChans_na_h_q_in => neuron_model_statevariable_none_naChans_na_h_q_in_int,
derivedvariable_none_naChans_na_h_fcond_out => neuron_model_derivedvariable_none_naChans_na_h_fcond_out_int,
derivedvariable_none_naChans_na_h_fcond_in => neuron_model_derivedvariable_none_naChans_na_h_fcond_in_int,
param_per_time_naChans_na_h_forwardRateh1_rate => neuron_model_param_per_time_naChans_na_h_forwardRateh1_rate ,
param_voltage_naChans_na_h_forwardRateh1_midpoint => neuron_model_param_voltage_naChans_na_h_forwardRateh1_midpoint ,
param_voltage_naChans_na_h_forwardRateh1_scale => neuron_model_param_voltage_naChans_na_h_forwardRateh1_scale ,
param_voltage_inv_naChans_na_h_forwardRateh1_scale_inv => neuron_model_param_voltage_inv_naChans_na_h_forwardRateh1_scale_inv ,
derivedvariable_per_time_naChans_na_h_forwardRateh1_r_out => neuron_model_derivedvariable_per_time_naChans_na_h_forwardRateh1_r_out_int,
derivedvariable_per_time_naChans_na_h_forwardRateh1_r_in => neuron_model_derivedvariable_per_time_naChans_na_h_forwardRateh1_r_in_int,
param_per_time_naChans_na_h_reverseRateh1_rate => neuron_model_param_per_time_naChans_na_h_reverseRateh1_rate ,
param_voltage_naChans_na_h_reverseRateh1_midpoint => neuron_model_param_voltage_naChans_na_h_reverseRateh1_midpoint ,
param_voltage_naChans_na_h_reverseRateh1_scale => neuron_model_param_voltage_naChans_na_h_reverseRateh1_scale ,
param_voltage_inv_naChans_na_h_reverseRateh1_scale_inv => neuron_model_param_voltage_inv_naChans_na_h_reverseRateh1_scale_inv ,
derivedvariable_per_time_naChans_na_h_reverseRateh1_r_out => neuron_model_derivedvariable_per_time_naChans_na_h_reverseRateh1_r_out_int,
derivedvariable_per_time_naChans_na_h_reverseRateh1_r_in => neuron_model_derivedvariable_per_time_naChans_na_h_reverseRateh1_r_in_int,
param_none_kChans_number => neuron_model_param_none_kChans_number ,
param_voltage_kChans_erev => neuron_model_param_voltage_kChans_erev ,
derivedvariable_current_kChans_i_out => neuron_model_derivedvariable_current_kChans_i_out_int,
derivedvariable_current_kChans_i_in => neuron_model_derivedvariable_current_kChans_i_in_int,
param_conductance_kChans_k_conductance => neuron_model_param_conductance_kChans_k_conductance ,
derivedvariable_conductance_kChans_k_g_out => neuron_model_derivedvariable_conductance_kChans_k_g_out_int,
derivedvariable_conductance_kChans_k_g_in => neuron_model_derivedvariable_conductance_kChans_k_g_in_int,
param_none_kChans_k_n_instances => neuron_model_param_none_kChans_k_n_instances ,
statevariable_none_kChans_k_n_q_out => neuron_model_statevariable_none_kChans_k_n_q_out_int,
statevariable_none_kChans_k_n_q_in => neuron_model_statevariable_none_kChans_k_n_q_in_int,
derivedvariable_none_kChans_k_n_fcond_out => neuron_model_derivedvariable_none_kChans_k_n_fcond_out_int,
derivedvariable_none_kChans_k_n_fcond_in => neuron_model_derivedvariable_none_kChans_k_n_fcond_in_int,
param_per_time_kChans_k_n_forwardRaten1_rate => neuron_model_param_per_time_kChans_k_n_forwardRaten1_rate ,
param_voltage_kChans_k_n_forwardRaten1_midpoint => neuron_model_param_voltage_kChans_k_n_forwardRaten1_midpoint ,
param_voltage_kChans_k_n_forwardRaten1_scale => neuron_model_param_voltage_kChans_k_n_forwardRaten1_scale ,
param_voltage_inv_kChans_k_n_forwardRaten1_scale_inv => neuron_model_param_voltage_inv_kChans_k_n_forwardRaten1_scale_inv ,
derivedvariable_per_time_kChans_k_n_forwardRaten1_r_out => neuron_model_derivedvariable_per_time_kChans_k_n_forwardRaten1_r_out_int,
derivedvariable_per_time_kChans_k_n_forwardRaten1_r_in => neuron_model_derivedvariable_per_time_kChans_k_n_forwardRaten1_r_in_int,
param_per_time_kChans_k_n_reverseRaten1_rate => neuron_model_param_per_time_kChans_k_n_reverseRaten1_rate ,
param_voltage_kChans_k_n_reverseRaten1_midpoint => neuron_model_param_voltage_kChans_k_n_reverseRaten1_midpoint ,
param_voltage_kChans_k_n_reverseRaten1_scale => neuron_model_param_voltage_kChans_k_n_reverseRaten1_scale ,
param_voltage_inv_kChans_k_n_reverseRaten1_scale_inv => neuron_model_param_voltage_inv_kChans_k_n_reverseRaten1_scale_inv ,
derivedvariable_per_time_kChans_k_n_reverseRaten1_r_out => neuron_model_derivedvariable_per_time_kChans_k_n_reverseRaten1_r_out_int,
derivedvariable_per_time_kChans_k_n_reverseRaten1_r_in => neuron_model_derivedvariable_per_time_kChans_k_n_reverseRaten1_r_in_int,
param_time_synapsemodel_tauDecay => neuron_model_param_time_synapsemodel_tauDecay ,
param_conductance_synapsemodel_gbase => neuron_model_param_conductance_synapsemodel_gbase ,
param_voltage_synapsemodel_erev => neuron_model_param_voltage_synapsemodel_erev ,
param_time_inv_synapsemodel_tauDecay_inv => neuron_model_param_time_inv_synapsemodel_tauDecay_inv ,
statevariable_conductance_synapsemodel_g_out => neuron_model_statevariable_conductance_synapsemodel_g_out_int,
statevariable_conductance_synapsemodel_g_in => neuron_model_statevariable_conductance_synapsemodel_g_in_int,
derivedvariable_current_synapsemodel_i_out => neuron_model_derivedvariable_current_synapsemodel_i_out_int,
derivedvariable_current_synapsemodel_i_in => neuron_model_derivedvariable_current_synapsemodel_i_in_int,
sysparam_time_timestep => sysparam_time_timestep,
sysparam_time_simtime => sysparam_time_simtime
);
count_proc_comb:process(init_model,step_once_complete_int,COUNT,step_once_go)
begin
seven_steps_done_next <= '0';
COUNT_next <= COUNT;
step_once_go_int_next <= '0';
if (init_model='1') then
seven_steps_done_next <= '0';
COUNT_next <= "110";
step_once_go_int_next <= '0';
else
if step_once_complete_int = '1' then
if (COUNT = "110") then
seven_steps_done_next <= '1';
COUNT_next <= "110";
step_once_go_int_next <= '0';
else
seven_steps_done_next <= '0';
COUNT_next <= COUNT + 1;
step_once_go_int_next <= '1';
end if;
elsif step_once_go = '1' then
seven_steps_done_next <= '0';
COUNT_next <= "000";
step_once_go_int_next <= '1';
else
seven_steps_done_next <= '0';
COUNT_next <= COUNT;
step_once_go_int_next <= '0';
end if;
end if;
end process count_proc_comb;
count_proc_syn:process(clk)
begin
if rising_edge(clk) then
if init_model = '1' then
COUNT <= "110";
seven_steps_done <= '1';
step_once_go_int <= '0';
else
COUNT <= COUNT_next;
seven_steps_done <= seven_steps_done_next;
step_once_go_int <= step_once_go_int_next;
end if; end if;
end process count_proc_syn;
shot_process:process(clk)
begin
if rising_edge(clk) then
if (init_model='1') then
seven_steps_done_shot <= '0';
seven_steps_done_shot_done <= '1';
else
if seven_steps_done = '1' and seven_steps_done_shot_done = '0' then
seven_steps_done_shot <= '1';
seven_steps_done_shot_done <= '1';
elsif seven_steps_done_shot = '1' then
seven_steps_done_shot <= '0';
elsif seven_steps_done = '0' then
seven_steps_done_shot <= '0';
seven_steps_done_shot_done <= '0';
end if;
end if;
end if;
end process shot_process;
store_state: process (clk)
begin
if rising_edge(clk) then
neuron_model_eventport_out_spike_int2 <= neuron_model_eventport_out_spike_int; neuron_model_eventport_out_spike_int3 <= neuron_model_eventport_out_spike_int2; seven_steps_done_shot2 <= seven_steps_done_shot; if (init_model='1') then
neuron_model_statevariable_voltage_v_in_int <= neuron_model_stateRESTORE_voltage_v;
neuron_model_statevariable_none_spiking_in_int <= neuron_model_stateRESTORE_none_spiking;
neuron_model_derivedvariable_current_leak_i_in_int <= neuron_model_stateRESTORE_current_leak_i;
neuron_model_derivedvariable_conductance_leak_passive_g_in_int <= neuron_model_stateRESTORE_conductance_leak_passive_g;
neuron_model_derivedvariable_current_naChans_i_in_int <= neuron_model_stateRESTORE_current_naChans_i;
neuron_model_derivedvariable_conductance_naChans_na_g_in_int <= neuron_model_stateRESTORE_conductance_naChans_na_g;
neuron_model_statevariable_none_naChans_na_m_q_in_int <= neuron_model_stateRESTORE_none_naChans_na_m_q;
neuron_model_derivedvariable_none_naChans_na_m_fcond_in_int <= neuron_model_stateRESTORE_none_naChans_na_m_fcond;
neuron_model_derivedvariable_per_time_naChans_na_m_forwardRatem1_r_in_int <= neuron_model_stateRESTORE_per_time_naChans_na_m_forwardRatem1_r;
neuron_model_derivedvariable_per_time_naChans_na_m_reverseRatem1_r_in_int <= neuron_model_stateRESTORE_per_time_naChans_na_m_reverseRatem1_r;
neuron_model_statevariable_none_naChans_na_h_q_in_int <= neuron_model_stateRESTORE_none_naChans_na_h_q;
neuron_model_derivedvariable_none_naChans_na_h_fcond_in_int <= neuron_model_stateRESTORE_none_naChans_na_h_fcond;
neuron_model_derivedvariable_per_time_naChans_na_h_forwardRateh1_r_in_int <= neuron_model_stateRESTORE_per_time_naChans_na_h_forwardRateh1_r;
neuron_model_derivedvariable_per_time_naChans_na_h_reverseRateh1_r_in_int <= neuron_model_stateRESTORE_per_time_naChans_na_h_reverseRateh1_r;
neuron_model_derivedvariable_current_kChans_i_in_int <= neuron_model_stateRESTORE_current_kChans_i;
neuron_model_derivedvariable_conductance_kChans_k_g_in_int <= neuron_model_stateRESTORE_conductance_kChans_k_g;
neuron_model_statevariable_none_kChans_k_n_q_in_int <= neuron_model_stateRESTORE_none_kChans_k_n_q;
neuron_model_derivedvariable_none_kChans_k_n_fcond_in_int <= neuron_model_stateRESTORE_none_kChans_k_n_fcond;
neuron_model_derivedvariable_per_time_kChans_k_n_forwardRaten1_r_in_int <= neuron_model_stateRESTORE_per_time_kChans_k_n_forwardRaten1_r;
neuron_model_derivedvariable_per_time_kChans_k_n_reverseRaten1_r_in_int <= neuron_model_stateRESTORE_per_time_kChans_k_n_reverseRaten1_r;
neuron_model_statevariable_conductance_synapsemodel_g_in_int <= neuron_model_stateRESTORE_conductance_synapsemodel_g;
neuron_model_derivedvariable_current_synapsemodel_i_in_int <= neuron_model_stateRESTORE_current_synapsemodel_i;
neuron_model_eventport_out_spike_out <= '0';
elsif (seven_steps_done_shot='1') then
neuron_model_eventport_out_spike_out <= neuron_model_eventport_out_spike_int3 ;
neuron_model_statevariable_voltage_v_in_int <= neuron_model_statevariable_voltage_v_out_int;
neuron_model_statevariable_none_spiking_in_int <= neuron_model_statevariable_none_spiking_out_int;
neuron_model_derivedvariable_current_leak_i_in_int <= neuron_model_derivedvariable_current_leak_i_out_int;
neuron_model_derivedvariable_conductance_leak_passive_g_in_int <= neuron_model_derivedvariable_conductance_leak_passive_g_out_int;
neuron_model_derivedvariable_current_naChans_i_in_int <= neuron_model_derivedvariable_current_naChans_i_out_int;
neuron_model_derivedvariable_conductance_naChans_na_g_in_int <= neuron_model_derivedvariable_conductance_naChans_na_g_out_int;
neuron_model_statevariable_none_naChans_na_m_q_in_int <= neuron_model_statevariable_none_naChans_na_m_q_out_int;
neuron_model_derivedvariable_none_naChans_na_m_fcond_in_int <= neuron_model_derivedvariable_none_naChans_na_m_fcond_out_int;
neuron_model_derivedvariable_per_time_naChans_na_m_forwardRatem1_r_in_int <= neuron_model_derivedvariable_per_time_naChans_na_m_forwardRatem1_r_out_int;
neuron_model_derivedvariable_per_time_naChans_na_m_reverseRatem1_r_in_int <= neuron_model_derivedvariable_per_time_naChans_na_m_reverseRatem1_r_out_int;
neuron_model_statevariable_none_naChans_na_h_q_in_int <= neuron_model_statevariable_none_naChans_na_h_q_out_int;
neuron_model_derivedvariable_none_naChans_na_h_fcond_in_int <= neuron_model_derivedvariable_none_naChans_na_h_fcond_out_int;
neuron_model_derivedvariable_per_time_naChans_na_h_forwardRateh1_r_in_int <= neuron_model_derivedvariable_per_time_naChans_na_h_forwardRateh1_r_out_int;
neuron_model_derivedvariable_per_time_naChans_na_h_reverseRateh1_r_in_int <= neuron_model_derivedvariable_per_time_naChans_na_h_reverseRateh1_r_out_int;
neuron_model_derivedvariable_current_kChans_i_in_int <= neuron_model_derivedvariable_current_kChans_i_out_int;
neuron_model_derivedvariable_conductance_kChans_k_g_in_int <= neuron_model_derivedvariable_conductance_kChans_k_g_out_int;
neuron_model_statevariable_none_kChans_k_n_q_in_int <= neuron_model_statevariable_none_kChans_k_n_q_out_int;
neuron_model_derivedvariable_none_kChans_k_n_fcond_in_int <= neuron_model_derivedvariable_none_kChans_k_n_fcond_out_int;
neuron_model_derivedvariable_per_time_kChans_k_n_forwardRaten1_r_in_int <= neuron_model_derivedvariable_per_time_kChans_k_n_forwardRaten1_r_out_int;
neuron_model_derivedvariable_per_time_kChans_k_n_reverseRaten1_r_in_int <= neuron_model_derivedvariable_per_time_kChans_k_n_reverseRaten1_r_out_int;
neuron_model_statevariable_conductance_synapsemodel_g_in_int <= neuron_model_statevariable_conductance_synapsemodel_g_out_int;
neuron_model_derivedvariable_current_synapsemodel_i_in_int <= neuron_model_derivedvariable_current_synapsemodel_i_out_int;
else
neuron_model_eventport_out_spike_out <= '0';
end if;
end if;
end process store_state;
neuron_model_stateCURRENT_voltage_v <= neuron_model_statevariable_voltage_v_in_int;
neuron_model_stateCURRENT_none_spiking <= neuron_model_statevariable_none_spiking_in_int;
neuron_model_stateCURRENT_current_leak_i <= neuron_model_derivedvariable_current_leak_i_in_int;
neuron_model_stateCURRENT_conductance_leak_passive_g <= neuron_model_derivedvariable_conductance_leak_passive_g_in_int;
neuron_model_stateCURRENT_current_naChans_i <= neuron_model_derivedvariable_current_naChans_i_in_int;
neuron_model_stateCURRENT_conductance_naChans_na_g <= neuron_model_derivedvariable_conductance_naChans_na_g_in_int;
neuron_model_stateCURRENT_none_naChans_na_m_q <= neuron_model_statevariable_none_naChans_na_m_q_in_int;
neuron_model_stateCURRENT_none_naChans_na_m_fcond <= neuron_model_derivedvariable_none_naChans_na_m_fcond_in_int;
neuron_model_stateCURRENT_per_time_naChans_na_m_forwardRatem1_r <= neuron_model_derivedvariable_per_time_naChans_na_m_forwardRatem1_r_in_int;
neuron_model_stateCURRENT_per_time_naChans_na_m_reverseRatem1_r <= neuron_model_derivedvariable_per_time_naChans_na_m_reverseRatem1_r_in_int;
neuron_model_stateCURRENT_none_naChans_na_h_q <= neuron_model_statevariable_none_naChans_na_h_q_in_int;
neuron_model_stateCURRENT_none_naChans_na_h_fcond <= neuron_model_derivedvariable_none_naChans_na_h_fcond_in_int;
neuron_model_stateCURRENT_per_time_naChans_na_h_forwardRateh1_r <= neuron_model_derivedvariable_per_time_naChans_na_h_forwardRateh1_r_in_int;
neuron_model_stateCURRENT_per_time_naChans_na_h_reverseRateh1_r <= neuron_model_derivedvariable_per_time_naChans_na_h_reverseRateh1_r_in_int;
neuron_model_stateCURRENT_current_kChans_i <= neuron_model_derivedvariable_current_kChans_i_in_int;
neuron_model_stateCURRENT_conductance_kChans_k_g <= neuron_model_derivedvariable_conductance_kChans_k_g_in_int;
neuron_model_stateCURRENT_none_kChans_k_n_q <= neuron_model_statevariable_none_kChans_k_n_q_in_int;
neuron_model_stateCURRENT_none_kChans_k_n_fcond <= neuron_model_derivedvariable_none_kChans_k_n_fcond_in_int;
neuron_model_stateCURRENT_per_time_kChans_k_n_forwardRaten1_r <= neuron_model_derivedvariable_per_time_kChans_k_n_forwardRaten1_r_in_int;
neuron_model_stateCURRENT_per_time_kChans_k_n_reverseRaten1_r <= neuron_model_derivedvariable_per_time_kChans_k_n_reverseRaten1_r_in_int;
neuron_model_stateCURRENT_conductance_synapsemodel_g <= neuron_model_statevariable_conductance_synapsemodel_g_in_int;
neuron_model_stateCURRENT_current_synapsemodel_i <= neuron_model_derivedvariable_current_synapsemodel_i_in_int;
neuron_model_eventport_out_spike <= neuron_model_eventport_out_spike_out;
step_once_complete <= seven_steps_done_shot2;
end top; | lgpl-3.0 | 546237051e5e0d885b97a64b5dd88516 | 0.750695 | 2.805579 | false | false | false | false |
rccoder/CU-MicroProgram | code/CU.vhd | 1 | 4,339 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:23:59 06/15/2015
-- Design Name:
-- Module Name: CU - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
--convertaddr
library IEEE;
use IEEE.STD_LOGIC_1164.ALL,IEEE.NUMERIC_STD.ALL;
entity convertaddr is
Port ( op : in STD_LOGIC_VECTOR (4 downto 0);
op_add : out STD_LOGIC_VECTOR (4 downto 0));
end convertaddr;
architecture Behavioral of convertaddr is
begin
process(op)
begin
op_add <= op(3 downto 0) & '0';
end process;
end Behavioral;
--MUX
library IEEE;
use IEEE.STD_LOGIC_1164.ALL,IEEE.NUMERIC_STD.ALL;
entity MUX is
PORT(
mode:IN STD_LOGIC;
next_add:IN STD_LOGIC_VECTOR(4 DOWNTO 0);
op_addr :IN STD_LOGIC_VECTOR(4 DOWNTO 0);
out_add :OUT STD_LOGIC_VECTOR(4 DOWNTO 0));
end MUX;
architecture Behavioral of MUX is
begin
process(mode,next_add,op_addr)
begin
case mode is
when'0' => out_add<=next_add;
when others => out_add<=op_addr;
end case;
end process;
end Behavioral;
--ROM
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.ALL;
entity ROM is
Port ( add : in STD_LOGIC_VECTOR (4 downto 0);
data_out : out STD_LOGIC_VECTOR (0 to 23));
end ROM;
architecture Behavioral of ROM is
type microcode_array is array(28 downto 0) of std_logic_vector(0 to 23);
constant code : microcode_array:=(
0=> "110000000000000000000001", 1=> "001100000000000000000010", 2=> "0000100000000000001UUUUU", 4=> "000001000000000000000000",
6=> "000000100000000000000000", 8=> "000000010000000000000000", 10=> "000000001000000000000000", 12=> "000000000100000000000000",
14=> "010000000010000000001111", 15=> "001000000000000000010000", 16=> "000000000001000000000000",18=> "000000000010100000010011",
19=> "000000000000010000010100",20=> "000000000000001000000000", 22=> "010000000010000000010111", 23=> "001000000000000000011000",
24=> "000000000000000100000000", 26=> "000000000000000010000000", 28=> "000000000000000001000000",others=>"000000000000000000000000");
begin
data_out <= code(conv_integer(add));
end Behavioral;
--Splitcode
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Splitcode is
Port (
clock : IN Std_logic;
u_op : in STD_LOGIC_VECTOR (0 TO 23);
control : out STD_LOGIC_VECTOR (0 TO 17);
mode_sel: out STD_LOGIC;
next_add : out STD_LOGIC_VECTOR (4 DOWNTO 0));
end Splitcode;
architecture Behavioral of Splitcode is
SIGNAL int_reg : Std_logic_vector(0 TO 23);
BEGIN
main_proc : PROCESS
BEGIN
WAIT UNTIL falling_edge(clock);
int_reg <= u_op;
END PROCESS;
control <= int_reg(0 TO 17);
mode_sel<= int_reg(18);
next_add <= int_reg(19 TO 23);
end Behavioral;
--CU
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity CU is
Port ( clk : in STD_LOGIC;
op_code : in STD_LOGIC_VECTOR (4 downto 0);
ctrl_signal : out STD_LOGIC_VECTOR (17 downto 0));end CU;
architecture Behavioral of CU is
component Splitcode
Port (
clock : IN Std_logic;
u_op : in STD_LOGIC_VECTOR (0 TO 23);
control : out STD_LOGIC_VECTOR (0 TO 17);
mode_sel: out STD_LOGIC;
next_add : out STD_LOGIC_VECTOR (4 DOWNTO 0));
end component;
component convertaddr
Port (
op : in STD_LOGIC_VECTOR (4 downto 0);
op_add : out STD_LOGIC_VECTOR (4 downto 0));
end component;
component MUX
PORT(
mode:IN STD_LOGIC;
next_add:IN STD_LOGIC_VECTOR(4 DOWNTO 0);
op_addr :IN STD_LOGIC_VECTOR(4 DOWNTO 0);
out_add :OUT STD_LOGIC_VECTOR(4 DOWNTO 0));
end component;
component ROM
Port (
add : in STD_LOGIC_VECTOR (4 downto 0);
data_out : out STD_LOGIC_VECTOR (0 to 23));
end component;
signal op_add_MUX:std_logic_vector(4 downto 0);
signal mode_MUX :std_logic;
signal next_add_MUX:std_logic_vector(4 downto 0);
signal MUX_CM :std_logic_vector(4 downto 0);
signal CM_CMAR :std_logic_vector(0 to 23);
begin
unit1:convertaddr port map(op_code, op_add_MUX);
unit2:MUX port map(mode_MUX, next_add_MUX, op_add_MUX, MUX_CM);
unit3:ROM port map(MUX_CM, CM_CMAR);
unit4:Splitcode port map(clk, CM_CMAR, ctrl_signal, mode_MUX, next_add_MUX);
end Behavioral;
| mit | b99ce148c238ed55fb284fafeed2f425 | 0.672505 | 3.199853 | false | false | false | false |
kristofferkoch/ethersound | deltasigmadac.vhd | 1 | 6,570 | -----------------------------------------------------------------------------
-- Rudimentary "DAC" for ouputting sound on the spartan3 starter kit
--
-- Authors:
-- -- Kristoffer E. Koch
-----------------------------------------------------------------------------
-- Copyright 2008 Authors
--
-- This file is part of hwpulse.
--
-- hwpulse is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- hwpulse is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with hwpulse. If not, see <http://www.gnu.org/licenses/>.
-----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity deltasigmadac is
Port ( sysclk : in STD_LOGIC;
reset : in STD_LOGIC;
audio : in STD_LOGIC_VECTOR (23 downto 0);
audio_dv : in STD_LOGIC;
audio_left : out STD_LOGIC;
audio_right : out STD_LOGIC;
rate_pulse:out std_logic;
debug:out std_logic_vector(7 downto 0));
end deltasigmadac;
architecture Behavioral of deltasigmadac is
constant channel_bits:integer:=10;
constant fifo_sz:integer:=2048*4;
component deltasigmachannel
Generic(N:integer);
Port ( sysclk : in STD_LOGIC;
reset : in STD_LOGIC;
data : in STD_LOGIC_VECTOR (channel_bits-1 downto 0);
ds : out STD_LOGIC);
end component;
signal left,right:std_logic_vector(23 downto 0):=(OTHERS => '0');
signal left_t, right_t:std_logic_vector(channel_bits-1 downto 0);
signal next_left, next_right:std_logic_vector(23 downto 0);
signal fifo_read:std_logic;
type wstate_t is (Idle, Busy);
signal wstate:wstate_t;
signal bytecnt:integer range 0 to 2;
signal fifo_w:std_logic;
signal audio_slice, fifo_out:std_logic_vector(7 downto 0);
type ram_t is array (0 to fifo_sz-1) of std_logic_vector(7 downto 0);
signal fifo:ram_t:=(OTHERS => (OTHERS => '0'));
signal wp,rp,fill:integer range 0 to fifo_sz-1;
signal freq_count:integer range 0 to (50000000+48000-1);
signal frame_pulse:std_logic;
signal freq_count_wrap:integer range -50000000 to 48000-1;
type readstate_t is (Idle, stPause, stRight, stLeft);
signal readstate:readstate_t;
signal readcnt:integer range 0 to 2;
begin
rate_pulse <= frame_pulse;
fifo_reader:process(sysclk) is
begin
if rising_edge(sysclk) then
if reset = '1' then
readstate <= Idle;
readcnt <= 2;
left <= (OTHERS => '0');
right <= (OTHERS => '0');
next_left <= (OTHERS => '0');
next_right <= (OTHERS => '0');
fifo_read <= '0';
debug(7 downto 2) <= (OTHERS => '1');
else
case readstate is
when Idle =>
if frame_pulse = '1' and fill >= 6 then
readstate <= stPause;
readcnt <= 2;
fifo_read <= '1';
debug(2) <= '1';
else
report "Frame skipped" severity warning;
debug(2) <= '0';
end if;
left <= next_left;
right <= next_right;
when stPause =>
readstate <= stLeft;
when stLeft =>
next_left(readcnt*8+7 downto readcnt*8) <= fifo_out;
if readcnt = 0 then
readstate <= stRight;
readcnt <= 2;
else
readcnt <= readcnt - 1;
end if;
when stRight =>
next_right(readcnt*8+7 downto readcnt*8) <= fifo_out;
if readcnt = 0 then
readstate <= Idle;
readcnt <= 2;
else
if readcnt = 1 then
fifo_read <= '0';
end if;
readcnt <= readcnt - 1;
end if;
end case;
end if;
end if;
end process;
freq_count_wrap <= freq_count - 50000000;
frame_pulse <= '1' when freq_count_wrap >= 0 else '0';
framerater:process(sysclk) is
begin
if rising_edge(sysclk) then
if reset = '1' then
freq_count <= 0;
else
if frame_pulse = '1' then
report "Frame is flippin";
freq_count <= freq_count_wrap + 48000;
else
--report "Increasing from " & integer'image(freq_count);
freq_count <= freq_count + 48000;
end if;
end if;
end if;
end process;
fifo_ctrl:process(sysclk) is
begin
if rising_edge(sysclk) then
if reset = '1' then
wp <= 0;
rp <= 0;
fill <= 0;
debug(1 downto 0) <= (OTHERS => '1');
else
if fifo_w = '1' then
if wp = fifo_sz-1 then
wp <= 0;
else
wp <= wp + 1;
end if;
end if;
if fifo_read = '1' then
if rp = fifo_sz-1 then
rp <= 0;
else
rp <= rp + 1;
end if;
end if;
if fifo_w = '1' and fifo_read = '0' then
if fill = fifo_sz-1 then
report "Fifo overflow" severity warning;
debug(1) <= '0';
else
debug(1) <= '1';
fill <= fill + 1;
end if;
elsif fifo_w = '0' and fifo_read = '1' then
if fill = 0 then
debug(0) <= '0';
report "Fifo underflow" severity warning;
else
debug(0) <= '1';
fill <= fill - 1;
end if;
end if;
end if;
end if;
end process;
process(sysclk) is
begin
if rising_edge(sysclk) then
if reset = '1' then
wstate <= Idle;
bytecnt <= 2;
fifo_w <= '0';
else
case wstate is
when Idle =>
if audio_dv = '1' then
wstate <= Busy;
fifo_w <= '1';
end if;
bytecnt <= 2;
when Busy =>
if bytecnt = 0 then
wstate <= Idle;
bytecnt <= 2;
fifo_w <= '0';
else
bytecnt <= bytecnt - 1;
end if;
end case;
end if;
end if;
end process;
audio_slice <= audio(bytecnt*8+7 downto bytecnt*8);
ram:process(sysclk) is
begin
if rising_edge(sysclk) then
if fifo_w = '1' then
fifo(wp) <= audio_slice;
end if;
fifo_out <= fifo(rp);
end if;
end process;
left_t <= left(23 downto 24-channel_bits);
right_t <= right(23 downto 24-channel_bits);
left_dsc: deltasigmachannel generic map (
N => channel_bits
) Port map (
sysclk => sysclk,
reset => reset,
data => left_t,
ds => audio_left
);
right_dsc: deltasigmachannel generic map (
N => channel_bits
) Port map (
sysclk => sysclk,
reset => reset,
data => right_t,
ds => audio_right
);
end Behavioral;
| gpl-3.0 | 19d68e81b22b64df9fc7b8a2925e31d1 | 0.567884 | 3.130062 | false | false | false | false |
riverever/verilogTestSuit | ivltests/vhdl_test3.vhd | 2 | 1,143 | --
-- Author: Pawel Szostek ([email protected])
-- Date: 28.07.2011
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity dummy is
port (clk : in std_logic;
input : in std_logic_vector(3 downto 0);
output : out std_logic_vector(15 downto 0)
);
end;
architecture behaviour of dummy is
begin
L: process(clk)
variable one : integer; -- mix integers and unsigned
variable a : unsigned (6 downto 0); --
variable b,c,d : unsigned(6 downto 0);
begin
if(clk'event and clk = '1') then
--do some mess around..
a(3 downto 0) := unsigned(input);
a(6 downto 4) := "000";
one := 1;
b := a + one; --unsigned plus integer
b := a + 1; --variable plus constant integer
c := a + a; --
c := c - b; --two assignments in a row to the same variable
d := c + 2;
output(6 downto 0) <= std_logic_vector(d); --signal assignment
output(15 downto 7) <= (others => '0');
end if;
end process;
end;
| gpl-2.0 | 3c87e6fa0c6c6c963a8f2c5c36eb30c0 | 0.545932 | 3.617089 | false | false | false | false |
Wynjones1/VHDL-Build | example/text_display/display_comp.vhd | 1 | 13,713 | library IEEE;
use IEEE.numeric_std.all;
use IEEE.std_logic_1164.all;
package display_comp is
constant TEXT_WIDTH : natural := 80;
constant TEXT_HEIGHT : natural := 60;
constant TILE_WIDTH : natural := 8;
constant TILE_HEIGHT : natural := 8;
constant PRINTABLE_START : natural := 32;
constant PRINTABLE_END : natural := 127;
constant PRINTABLE_COUNT : natural := PRINTABLE_END - PRINTABLE_START + 1;
function printable(index : natural) return natural;
subtype character_t is natural range PRINTABLE_START to PRINTABLE_END;
type line_t is array (0 to TEXT_WIDTH - 1) of character_t;
type glyph_t is array (0 to 7) of std_logic_vector(7 downto 0);
type glyph_rom_t is array (0 to 127) of glyph_t;
constant FONT_ROM : glyph_rom_t := (
("00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"),
("00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"),
("00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"),
("00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"),
("00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"),
("00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"),
("00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"),
("00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"),
("00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"),
("00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"),
("00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"),
("00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"),
("00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"),
("00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"),
("00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"),
("00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"),
("00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"),
("00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"),
("00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"),
("00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"),
("00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"),
("00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"),
("00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"),
("00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"),
("00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"),
("00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"),
("00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"),
("00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"),
("00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"),
("00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"),
("00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"),
("00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"),
("00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"),
("00011000","00111100","00111100","00011000","00011000","00000000","00011000","00000000"),
("01101100","01101100","00000000","00000000","00000000","00000000","00000000","00000000"),
("01101100","01101100","11111110","01101100","11111110","01101100","01101100","00000000"),
("00110000","01111100","11000000","01111000","00001100","11111000","00110000","00000000"),
("00000000","11000110","11001100","00011000","00110000","01100110","11000110","00000000"),
("00111000","01101100","00111000","01110110","11011100","11001100","01110110","00000000"),
("01100000","01100000","11000000","00000000","00000000","00000000","00000000","00000000"),
("00011000","00110000","01100000","01100000","01100000","00110000","00011000","00000000"),
("01100000","00110000","00011000","00011000","00011000","00110000","01100000","00000000"),
("00000000","01100110","00111100","11111111","00111100","01100110","00000000","00000000"),
("00000000","00110000","00110000","11111100","00110000","00110000","00000000","00000000"),
("00000000","00000000","00000000","00000000","00000000","00110000","00110000","01100000"),
("00000000","00000000","00000000","11111100","00000000","00000000","00000000","00000000"),
("00000000","00000000","00000000","00000000","00000000","00110000","00110000","00000000"),
("00000110","00001100","00011000","00110000","01100000","11000000","10000000","00000000"),
("01111100","11000110","11001110","11011110","11110110","11100110","01111100","00000000"),
("00110000","01110000","00110000","00110000","00110000","00110000","11111100","00000000"),
("01111000","11001100","00001100","00111000","01100000","11001100","11111100","00000000"),
("01111000","11001100","00001100","00111000","00001100","11001100","01111000","00000000"),
("00011100","00111100","01101100","11001100","11111110","00001100","00011110","00000000"),
("11111100","11000000","11111000","00001100","00001100","11001100","01111000","00000000"),
("00111000","01100000","11000000","11111000","11001100","11001100","01111000","00000000"),
("11111100","11001100","00001100","00011000","00110000","00110000","00110000","00000000"),
("01111000","11001100","11001100","01111000","11001100","11001100","01111000","00000000"),
("01111000","11001100","11001100","01111100","00001100","00011000","01110000","00000000"),
("00000000","00110000","00110000","00000000","00000000","00110000","00110000","00000000"),
("00000000","00110000","00110000","00000000","00000000","00110000","00110000","01100000"),
("00011000","00110000","01100000","11000000","01100000","00110000","00011000","00000000"),
("00000000","00000000","11111100","00000000","00000000","11111100","00000000","00000000"),
("01100000","00110000","00011000","00001100","00011000","00110000","01100000","00000000"),
("01111000","11001100","00001100","00011000","00110000","00000000","00110000","00000000"),
("01111100","11000110","11011110","11011110","11011110","11000000","01111000","00000000"),
("00110000","01111000","11001100","11001100","11111100","11001100","11001100","00000000"),
("11111100","01100110","01100110","01111100","01100110","01100110","11111100","00000000"),
("00111100","01100110","11000000","11000000","11000000","01100110","00111100","00000000"),
("11111000","01101100","01100110","01100110","01100110","01101100","11111000","00000000"),
("11111110","01100010","01101000","01111000","01101000","01100010","11111110","00000000"),
("11111110","01100010","01101000","01111000","01101000","01100000","11110000","00000000"),
("00111100","01100110","11000000","11000000","11001110","01100110","00111110","00000000"),
("11001100","11001100","11001100","11111100","11001100","11001100","11001100","00000000"),
("01111000","00110000","00110000","00110000","00110000","00110000","01111000","00000000"),
("00011110","00001100","00001100","00001100","11001100","11001100","01111000","00000000"),
("11100110","01100110","01101100","01111000","01101100","01100110","11100110","00000000"),
("11110000","01100000","01100000","01100000","01100010","01100110","11111110","00000000"),
("11000110","11101110","11111110","11111110","11010110","11000110","11000110","00000000"),
("11000110","11100110","11110110","11011110","11001110","11000110","11000110","00000000"),
("00111000","01101100","11000110","11000110","11000110","01101100","00111000","00000000"),
("11111100","01100110","01100110","01111100","01100000","01100000","11110000","00000000"),
("01111000","11001100","11001100","11001100","11011100","01111000","00011100","00000000"),
("11111100","01100110","01100110","01111100","01101100","01100110","11100110","00000000"),
("01111000","11001100","11100000","01110000","00011100","11001100","01111000","00000000"),
("11111100","10110100","00110000","00110000","00110000","00110000","01111000","00000000"),
("11001100","11001100","11001100","11001100","11001100","11001100","11111100","00000000"),
("11001100","11001100","11001100","11001100","11001100","01111000","00110000","00000000"),
("11000110","11000110","11000110","11010110","11111110","11101110","11000110","00000000"),
("11000110","11000110","01101100","00111000","00111000","01101100","11000110","00000000"),
("11001100","11001100","11001100","01111000","00110000","00110000","01111000","00000000"),
("11111110","11000110","10001100","00011000","00110010","01100110","11111110","00000000"),
("01111000","01100000","01100000","01100000","01100000","01100000","01111000","00000000"),
("11000000","01100000","00110000","00011000","00001100","00000110","00000010","00000000"),
("01111000","00011000","00011000","00011000","00011000","00011000","01111000","00000000"),
("00010000","00111000","01101100","11000110","00000000","00000000","00000000","00000000"),
("00000000","00000000","00000000","00000000","00000000","00000000","00000000","11111111"),
("00110000","00110000","00011000","00000000","00000000","00000000","00000000","00000000"),
("00000000","00000000","01111000","00001100","01111100","11001100","01110110","00000000"),
("11100000","01100000","01100000","01111100","01100110","01100110","11011100","00000000"),
("00000000","00000000","01111000","11001100","11000000","11001100","01111000","00000000"),
("00011100","00001100","00001100","01111100","11001100","11001100","01110110","00000000"),
("00000000","00000000","01111000","11001100","11111100","11000000","01111000","00000000"),
("00111000","01101100","01100000","11110000","01100000","01100000","11110000","00000000"),
("00000000","00000000","01110110","11001100","11001100","01111100","00001100","11111000"),
("11100000","01100000","01101100","01110110","01100110","01100110","11100110","00000000"),
("00110000","00000000","01110000","00110000","00110000","00110000","01111000","00000000"),
("00001100","00000000","00001100","00001100","00001100","11001100","11001100","01111000"),
("11100000","01100000","01100110","01101100","01111000","01101100","11100110","00000000"),
("01110000","00110000","00110000","00110000","00110000","00110000","01111000","00000000"),
("00000000","00000000","11001100","11111110","11111110","11010110","11000110","00000000"),
("00000000","00000000","11111000","11001100","11001100","11001100","11001100","00000000"),
("00000000","00000000","01111000","11001100","11001100","11001100","01111000","00000000"),
("00000000","00000000","11011100","01100110","01100110","01111100","01100000","11110000"),
("00000000","00000000","01110110","11001100","11001100","01111100","00001100","00011110"),
("00000000","00000000","11011100","01110110","01100110","01100000","11110000","00000000"),
("00000000","00000000","01111100","11000000","01111000","00001100","11111000","00000000"),
("00010000","00110000","01111100","00110000","00110000","00110100","00011000","00000000"),
("00000000","00000000","11001100","11001100","11001100","11001100","01110110","00000000"),
("00000000","00000000","11001100","11001100","11001100","01111000","00110000","00000000"),
("00000000","00000000","11000110","11010110","11111110","11111110","01101100","00000000"),
("00000000","00000000","11000110","01101100","00111000","01101100","11000110","00000000"),
("00000000","00000000","11001100","11001100","11001100","01111100","00001100","11111000"),
("00000000","00000000","11111100","10011000","00110000","01100100","11111100","00000000"),
("00011100","00110000","00110000","11100000","00110000","00110000","00011100","00000000"),
("00011000","00011000","00011000","00000000","00011000","00011000","00011000","00000000"),
("11100000","00110000","00110000","00011100","00110000","00110000","11100000","00000000"),
("01110110","11011100","00000000","00000000","00000000","00000000","00000000","00000000"),
("00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000"));
end package;
package body display_comp is
function printable(index : natural) return natural is
begin
return PRINTABLE_START + index;
end function;
end package body;
| mit | 5d20c488b4c750530049137d73587edc | 0.646394 | 5.28643 | false | false | false | false |
epall/Computer.Build | mux.vhd | 1 | 1,263 | -------------------------------------------------
-- VHDL code for 4:1 multiplexor
-- (ESD book figure 2.5)
-- by Weijun Zhang, 04/2001
--
-- Multiplexor is a device to select different
-- inputs to outputs. we use 3 bits vector to
-- describe its I/O ports
-------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------
entity Mux is
port( I3: in std_logic_vector(2 downto 0);
I2: in std_logic_vector(2 downto 0);
I1: in std_logic_vector(2 downto 0);
I0: in std_logic_vector(2 downto 0);
S: in std_logic_vector(1 downto 0);
O: out std_logic_vector(2 downto 0)
);
end Mux;
-------------------------------------------------
architecture behv1 of Mux is
begin
process(I3,I2,I1,I0,S)
begin
-- use case statement
case S is
when "00" => O <= I0;
when "01" => O <= I1;
when "10" => O <= I2;
when "11" => O <= I3;
when others => O <= "ZZZ";
end case;
end process;
end behv1;
architecture behv2 of Mux is
begin
-- use when.. else statement
O <= I0 when S="00" else
I1 when S="01" else
I2 when S="10" else
I3 when S="11" else
"ZZZ";
end behv2;
--------------------------------------------------
| mit | dca4961312048e71396999c6e8550790 | 0.487728 | 3.255155 | false | false | false | false |
Kalycito-open-automation/openPOWERLINK_V2_old_25-06-2014 | hardware/ipcore/common/hostinterface/src/statusControlRegRtl.vhd | 2 | 24,524 | -------------------------------------------------------------------------------
--! @file statusControlReg.vhd
--
--! @brief Host interface Status-/Control Registers
--
--! @details The host interface status/control registers provide memory mapped
--! control of the interrupt generator (irqGen) and bridge (magicBridge).
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2012
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! use global library
use work.global.all;
--! use host interface package for specific types
use work.hostInterfacePkg.all;
entity statusControlReg is
generic (
--! Magic
gMagic : natural := 16#504C4B00#;
-- Version
--! Version major
gVersionMajor : natural := 16#FF#;
--! Version minor
gVersionMinor : natural := 16#FF#;
--! Version revision
gVersionRevision : natural := 16#FF#;
--! Version count pattern
gVersionCount : natural := 0;
-- BaseSets
--! BaseSets by Host
gHostBaseSet : natural := 2;
--! BaseSets by Pcp
gPcpBaseSet : natural := 10;
--! Interrupt source number
gIrqSourceCount : natural range 1 to 15 := 3
);
port (
-- Global
--! component wide clock signal
iClk : in std_logic;
--! component wide reset signal
iRst : in std_logic;
-- slave Host interface
--! host read
iHostRead : in std_logic;
--! host write
iHostWrite : in std_logic;
--! host byteenable
iHostByteenable : in std_logic_vector(cDword/8-1 downto 0);
--! host address
iHostAddress : in std_logic_vector(10 downto 2);
--! host readdata
oHostReaddata : out std_logic_vector(cDword-1 downto 0);
--! host writedata
iHostWritedata : in std_logic_vector(cDword-1 downto 0);
--! host waitrequest
oHostWaitrequest : out std_logic;
-- slave PCP interface
--! pcp read
iPcpRead : in std_logic;
--! pcp write
iPcpWrite : in std_logic;
--! pcp byteenable
iPcpByteenable : in std_logic_vector(cDword/8-1 downto 0);
--! pcp address
iPcpAddress : in std_logic_vector(10 downto 2);
--! pcp readdata
oPcpReaddata : out std_logic_vector(cDword-1 downto 0);
--! pcp writedata
iPcpWritedata : in std_logic_vector(cDword-1 downto 0);
--! pcp waitrequest
oPcpWaitrequest : out std_logic;
-- BaseSet link
--! BaseSet write strobe
oBaseSetWrite : out std_logic;
--! BaseSet read strobe
oBaseSetRead : out std_logic;
--! BaseSet byteenable
oBaseSetByteenable : out std_logic_vector;
--! BaseSet address bus
oBaseSetAddress : out std_logic_vector(LogDualis(gHostBaseSet+gPcpBaseSet)+2-1 downto 2);
--! BaseSet read data bus
iBaseSetData : in std_logic_vector;
--! BaseSet write data bus
oBaseSetData : out std_logic_vector;
--! BaseSet acknowledge
iBaseSetAck : in std_logic;
-- Interrupt control
--! master enable
oIrqMasterEnable : out std_logic;
--! interrupt source enable vector ('right is sync)
oIrqSourceEnable : out std_logic_vector(gIrqSourceCount downto 0);
--! interrupt acknowledge (pulse, 'right is sync)
oIrqAcknowledge : out std_logic_vector(gIrqSourceCount downto 0);
--! interrup set (pulse, no sync!)
oIrqSet : out std_logic_vector(gIrqSourceCount downto 1);
--! interrupt source pending
iIrqPending : in std_logic_vector(gIrqSourceCount downto 0);
--! external sync source enable
oExtSyncEnable : out std_logic;
--! external sync source config
oExtSyncConfig : out std_logic_vector(cExtSyncEdgeConfigWidth-1 downto 0);
-- miscellaneous
--! Node Id
iNodeId : in std_logic_vector(cByte-1 downto 0);
--! LED
oPLed : out std_logic_vector(1 downto 0);
--! bridge activates
oBridgeEnable : out std_logic
);
end statusControlReg;
architecture Rtl of statusControlReg is
-- base for register content
--! magic base
constant cBaseMagic : natural := 16#0000#;
--! version base
constant cBaseVersion : natural := 16#0004#;
--! boot base
constant cBaseBootBase : natural := 16#0008#;
--! init base
constant cBaseInitBase : natural := 16#000C#;
--! bridge enable base
constant cBaseBridgeEnable : natural := 16#0200#;
--! command base
constant cBaseCommand : natural := 16#0204#;
--! state base
constant cBaseState : natural := 16#0206#;
--! error base
constant cBaseError : natural := 16#0208#;
--! heart beat
constant cBaseHeartBeat : natural := 16#020A#;
--! node id in base
constant cBaseNodeIdIn : natural := 16#020C#;
--! led control base
constant cBaseLedControl : natural := 16#0210#;
--! irq enable base
constant cBaseIrqEnable : natural := 16#0300#;
--! irq pending base
constant cBaseIrqPending : natural := 16#0302#;
--! irq master enable base
constant cBaseIrqMasterEnable : natural := 16#0304#;
--! irq ack base (host only)
constant cBaseIrqAck : natural := 16#0306#;
--! irq set base (pcp only)
constant cBaseIrqSet : natural := 16#0306#;
--! sync config base
constant cBaseSyncConfig : natural := 16#030C#;
--! base for base set
constant cBaseBaseSet : natural := 16#0400#;
--! base reserved
constant cBaseReserved : natural := 16#0500#;
--! LED count
constant cLedCount : natural range 1 to 16 := 2;
--! General Purpose Inputs
--! type base registers (stored content)
type tRegisterInfo is record
--magic
--version
bootBase : std_logic_vector(cDword-1 downto 0);
initBase : std_logic_vector(cDword-1 downto 0);
end record;
--! type control register (stored content)
type tRegisterControl is record
bridgeEnable : std_logic;
command : std_logic_vector(cWord-1 downto 0);
state : std_logic_vector(cWord-1 downto 0);
error : std_logic_vector(cWord-1 downto 0);
heartBeat : std_logic_vector(cWord-1 downto 0);
led : std_logic_vector(cLedCount-1 downto 0);
end record;
--! type synchronization register (stored content)
type tRegisterSynchronization is record
irqSrcEnableHost : std_logic_vector(gIrqSourceCount downto 0);
irqSrcEnablePcp : std_logic_vector(gIrqSourceCount downto 0);
irqMasterEnable : std_logic;
syncConfig : std_logic_vector(cExtSyncConfigWidth-1 downto 0);
end record;
--! info register
signal regInfo, regInfo_next : tRegisterInfo;
--! info register initialisation
constant cRegInfoInit : tRegisterInfo := (
bootBase => (others => cInactivated),
initBase => (others => cInactivated)
);
--! control register
signal regControl : tRegisterControl;
--! control register next
signal regControl_next : tRegisterControl;
--! control register initialisation
constant cRegControlInit : tRegisterControl := (
bridgeEnable => cInactivated,
command => (others => cInactivated),
state => (others => cInactivated),
error => (others => cInactivated),
heartBeat => (others => cInactivated),
led => (others => cInactivated)
);
--! synchronization register
signal regSynchron : tRegisterSynchronization;
--! synchronization register next
signal regSynchron_next : tRegisterSynchronization;
--! synchronization register initialisation
constant cRegSynchronInit : tRegisterSynchronization := (
irqSrcEnableHost => (others => cInactivated),
irqSrcEnablePcp => (others => cInactivated),
irqMasterEnable => cInactivated,
syncConfig => (others => cInactivated)
);
--! host base writedata
signal hostBaseSetData : std_logic_vector(iBaseSetData'range);
--! host base write
signal hostBaseSetWrite : std_logic;
--! host base read
signal hostBaseSetRead : std_logic;
--! pcp base writedata
signal pcpBaseSetData : std_logic_vector(iBaseSetData'range);
--! pcp base write
signal pcpBaseSetWrite : std_logic;
--! pcp base read
signal pcpBaseSetRead : std_logic;
begin
--! register process creates storage of values
regClk : process(iClk)
begin
if rising_edge(iClk) then
if iRst = cActivated then
regInfo <= cRegInfoInit;
regControl <= cRegControlInit;
regSynchron <= cRegSynchronInit;
else
regInfo <= regInfo_next;
regControl <= regControl_next;
regSynchron <= regSynchron_next;
end if;
end if;
end process;
oHostWaitrequest <= not iBaseSetAck when (hostBaseSetRead = cActivated or
hostBaseSetWrite = cActivated) else
not(iHostWrite or iHostRead);
oPcpWaitrequest <= not iBaseSetAck when (pcpBaseSetRead = cActivated or
pcpBaseSetWrite = cActivated) else
not(iPcpWrite or iPcpRead);
oIrqMasterEnable <= regSynchron.irqMasterEnable;
oIrqSourceEnable <= regSynchron.irqSrcEnableHost and regSynchron.irqSrcEnablePcp;
oExtSyncEnable <= regSynchron.syncConfig(0);
oExtSyncConfig <= regSynchron.syncConfig(2 downto 1);
oPLed <= regControl.led;
oBridgeEnable <= regControl.bridgeEnable;
-- pcp overrules host!
oBaseSetData <= pcpBaseSetData when pcpBaseSetWrite = cActivated else
pcpBaseSetData when pcpBaseSetRead = cActivated else
hostBaseSetData;
oBaseSetByteenable <= iPcpByteenable when pcpBaseSetWrite = cActivated else
iPcpByteenable when pcpBaseSetRead = cActivated else
iHostByteenable;
oBaseSetAddress <= std_logic_vector(unsigned(iPcpAddress(oBaseSetAddress'range))+gHostBaseSet)
when pcpBaseSetRead = cActivated or pcpBaseSetWrite = cActivated else
iHostAddress(oBaseSetAddress'range);
oBaseSetWrite <= pcpBaseSetWrite or hostBaseSetWrite;
oBaseSetRead <= pcpBaseSetRead or hostBaseSetRead;
--! register access
regAcc : process (
iHostWrite,
iHostByteenable,
iHostAddress,
iHostWritedata,
iPcpWrite,
iPcpByteenable,
iPcpAddress,
iPcpWritedata,
iNodeId,
regInfo,
regControl,
regSynchron,
iIrqPending,
iBaseSetData
)
variable vHostSelAddr : natural;
variable vPcpSelAddr : natural;
begin
-- default
-- registers
regInfo_next <= regInfo;
regControl_next <= regControl;
regSynchron_next <= regSynchron;
-- outputs
oHostReaddata <= (others => cInactivated);
oIrqAcknowledge <= (others => cInactivated);
hostBaseSetData <= (others => cInactivated);
hostBaseSetWrite <= cInactivated;
hostBaseSetRead <= cInactivated;
oIrqSet <= (others => cInactivated);
oPcpReaddata <= (others => cInactivated);
pcpBaseSetData <= (others => cInactivated);
pcpBaseSetWrite <= cInactivated;
pcpBaseSetRead <= cInactivated;
-- HOST
-- select content
-- write to content
-- and read from content
vHostSelAddr := to_integer(unsigned(iHostAddress))*4;
case vHostSelAddr is
when cBaseMagic =>
oHostReaddata <= std_logic_vector(to_unsigned(gMagic, cDword));
--magic is RO
when cBaseVersion =>
oHostReaddata <=
std_logic_vector(to_unsigned(gVersionMajor, cByte)) &
std_logic_vector(to_unsigned(gVersionMinor, cByte)) &
std_logic_vector(to_unsigned(gVersionRevision, cByte)) &
std_logic_vector(to_unsigned(gVersionCount, cByte));
--version is RO
when cBaseBootBase =>
oHostReaddata <= regInfo.bootBase;
--bootBase is RO
when cBaseInitBase =>
oHostReaddata <= regInfo.initBase;
--initBase is RO
when cBaseBridgeEnable =>
oHostReaddata(0) <= regControl.bridgeEnable;
--bridge enable is RO
when cBaseState | cBaseCommand =>
oHostReaddata <= regControl.state & regControl.command;
if iHostWrite = cActivated then
--state is RO
if iHostByteenable(1) = cActivated then
regControl_next.command(cWord-1 downto cByte) <= iHostWritedata(cWord-1 downto cByte);
end if;
if iHostByteenable(0) = cActivated then
regControl_next.command(cByte-1 downto 0) <= iHostWritedata(cByte-1 downto 0);
end if;
end if;
when cBaseHeartBeat | cBaseError =>
oHostReaddata <= regControl.heartBeat & regControl.error;
--heartbeat and error are RO
when cBaseNodeIdIn =>
oHostReaddata(iNodeId'length-1 downto 0) <= iNodeId;
--node id are RO
when cBaseLedControl =>
oHostReaddata(cLedCount-1 downto 0) <= regControl.led;
if iHostWrite = cActivated then
for i in cWord-1 downto 0 loop
if iHostByteenable(i/cByte) = cActivated and
i < cLedCount then
regControl_next.led(i) <= iHostWritedata(i);
end if;
end loop;
end if;
when cBaseIrqPending | cBaseIrqEnable =>
oHostReaddata(cWord+gIrqSourceCount downto cWord) <= iIrqPending;
oHostReaddata(gIrqSourceCount downto 0) <= regSynchron.irqSrcEnableHost;
if iHostWrite = cActivated then
for i in cWord-1 downto 0 loop
if iHostByteenable(i/cByte) = cActivated and
i <= gIrqSourceCount then
regSynchron_next.irqSrcEnableHost(i) <= iHostWritedata(i);
end if;
end loop;
end if;
when cBaseIrqAck | cBaseIrqMasterEnable =>
-- irq ack is SC
oHostReaddata(0) <= regSynchron.irqMasterEnable;
if iHostWrite = cActivated then
if iHostByteenable(0) = cActivated then
regSynchron_next.irqMasterEnable <= iHostWritedata(0);
end if;
for i in cDword-1 downto cWord loop
if iHostByteenable(i/cByte) = cActivated and
(i-cWord) <= gIrqSourceCount then
oIrqAcknowledge(i-cWord) <= iHostWritedata(i);
end if;
end loop;
end if;
when cBaseSyncConfig =>
oHostReaddata(cExtSyncConfigWidth-1 downto 0) <= regSynchron.syncConfig;
if iHostWrite = cActivated then
for i in cWord-1 downto 0 loop
if iHostByteenable(i/cByte) = cActivated and
i < cExtSyncConfigWidth then
regSynchron_next.syncConfig(i) <= iHostWritedata(i);
end if;
end loop;
end if;
when cBaseBaseSet to cBaseReserved-1 =>
if vHostSelAddr < cBaseBaseSet+gHostBaseSet*cDword/cByte then
oHostReaddata(iBaseSetData'range) <= iBaseSetData;
if iHostWrite = cActivated then
hostBaseSetData <= iHostWritedata(hostBaseSetData'range);
hostBaseSetWrite <= cActivated;
else
hostBaseSetRead <= cActivated;
end if;
end if;
when others => null;
end case;
-- PCP
-- select content
-- write to content
-- and read from content
vPcpSelAddr := to_integer(unsigned(iPcpAddress)) * 4;
case vPcpSelAddr is
when cBaseMagic =>
oPcpReaddata <= std_logic_vector(to_unsigned(gMagic, cDword));
--magic is RO
when cBaseVersion =>
oPcpReaddata <=
std_logic_vector(to_unsigned(gVersionMajor, cByte)) &
std_logic_vector(to_unsigned(gVersionMinor, cByte)) &
std_logic_vector(to_unsigned(gVersionRevision, cByte)) &
std_logic_vector(to_unsigned(gVersionCount, cByte));
--version is RO
when cBaseBootBase =>
oPcpReaddata <= regInfo.bootBase;
if iPcpWrite = cActivated then
for i in cDword-1 downto 0 loop
if iPcpByteenable(i/cByte) = cActivated then
regInfo_next.bootBase(i) <= iPcpWritedata(i);
end if;
end loop;
end if;
when cBaseInitBase =>
oPcpReaddata <= regInfo.initBase;
if iPcpWrite = cActivated then
for i in cDword-1 downto 0 loop
if iPcpByteenable(i/cByte) = cActivated then
regInfo_next.initBase(i) <= iPcpWritedata(i);
end if;
end loop;
end if;
when cBaseBridgeEnable =>
oPcpReaddata(0) <= regControl.bridgeEnable;
if iPcpWrite = cActivated then
regControl_next.bridgeEnable <= iPcpWritedata(0);
end if;
when cBaseState | cBaseCommand =>
oPcpReaddata <= regControl.state & regControl.command;
if iPcpWrite = cActivated then
for i in cDword-1 downto cWord loop
if iPcpByteenable(i/cByte) = cActivated then
regControl_next.state(i-cWord) <= iPcpWritedata(i);
end if;
end loop;
for i in cWord-1 downto 0 loop
if iPcpByteenable(i/cByte) = cActivated then
regControl_next.command(i) <= iPcpWritedata(i);
end if;
end loop;
end if;
when cBaseHeartBeat | cBaseError =>
oPcpReaddata <= regControl.heartBeat & regControl.error;
if iPcpWrite = cActivated then
for i in cDword-1 downto cWord loop
if iPcpByteenable(i/cByte) = cActivated then
regControl_next.heartBeat(i-cWord) <= iPcpWritedata(i);
end if;
end loop;
for i in cWord-1 downto 0 loop
if iPcpByteenable(i/cByte) = cActivated then
regControl_next.error(i) <= iPcpWritedata(i);
end if;
end loop;
end if;
when cBaseNodeIdIn =>
oPcpReaddata(iNodeId'length-1 downto 0) <= iNodeId;
when cBaseLedControl =>
oPcpReaddata(cLedCount-1 downto 0) <= regControl.led;
when cBaseIrqPending | cBaseIrqEnable =>
oPcpReaddata(cWord+gIrqSourceCount downto cWord) <= iIrqPending;
oPcpReaddata(gIrqSourceCount downto 0) <= regSynchron.irqSrcEnablePcp;
if iPcpWrite = cActivated then
for i in cWord-1 downto 0 loop
if iPcpByteenable(i/cByte) = cActivated and
i <= gIrqSourceCount then
regSynchron_next.irqSrcEnablePcp(i) <= iPcpWritedata(i);
end if;
end loop;
end if;
when cBaseIrqSet | cBaseIrqMasterEnable =>
-- irq set is self-clearing
oPcpReaddata(0) <= regSynchron.irqMasterEnable;
if iPcpWrite = cActivated then
for i in cDword-1 downto cWord+1 loop
if iPcpByteenable(i/cByte) = cActivated and
(i-cWord) <= gIrqSourceCount then
oIrqSet(i-cWord) <= iPcpWritedata(i);
end if;
end loop;
end if;
when cBaseSyncConfig =>
oPcpReaddata(cExtSyncConfigWidth-1 downto 0) <=
regSynchron.syncConfig;
when cBaseBaseSet to cBaseReserved-1 =>
if vPcpSelAddr < cBaseBaseSet+gPcpBaseSet*cDword/cByte then
oPcpReaddata(iBaseSetData'range) <= iBaseSetData;
if iPcpWrite = cActivated then
pcpBaseSetData <= iPcpWritedata(pcpBaseSetData'range);
pcpBaseSetWrite <= cActivated;
else
pcpBaseSetRead <= cActivated;
end if;
end if;
when others => null;
end case;
end process;
end Rtl;
| gpl-2.0 | eb7bde9465ac5111e52cdb00b2fc8831 | 0.545262 | 5.376891 | false | false | false | false |
Kalycito-open-automation/openPOWERLINK_V2_old_25-06-2014 | hardware/ipcore/common/lib/src/global.vhd | 2 | 6,789 | -------------------------------------------------------------------------------
-- Global package
--
-- Copyright (C) 2012 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
--
-------------------------------------------------------------------------------
-- Version History
-------------------------------------------------------------------------------
-- 2012-02-07 zelenkaj Derived from global package
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package Global is
constant cActivated : std_logic := '1';
constant cInactivated : std_logic := '0';
constant cnActivated : std_logic := '0';
constant cnInactivated : std_logic := '1';
constant cByteLength : natural := 8;
constant cWordLength : natural := 2 * cByteLength;
constant cFalse : natural := 0;
constant cTrue : natural := 1;
function LogDualis(cNumber : natural) return natural;
function maximum (a : natural; b : natural) return natural;
function minimum (a : natural; b : natural) return natural;
function integerToBoolean (a : integer) return boolean;
function booleanToInteger (a : boolean) return integer;
function byteSwap (iVector : std_logic_vector) return std_logic_vector;
function wordSwap (iVector : std_logic_vector) return std_logic_vector;
function reduceOr (iVector : std_logic_vector) return std_logic;
function reduceAnd (iVector : std_logic_vector) return std_logic;
end Global;
package body Global is
function LogDualis(cNumber : natural) return natural is
variable vClimbUp : natural := 1;
variable vResult : natural;
begin
while vClimbUp < cNumber loop
vClimbUp := vClimbUp * 2;
vResult := vResult+1;
end loop;
return vResult;
end LogDualis;
function maximum (a : natural; b : natural) return natural is
variable vRes : natural;
begin
if a > b then
vRes := a;
else
vRes := b;
end if;
return vRes;
end function;
function minimum (a : natural; b : natural) return natural is
variable vRes : natural;
begin
if a < b then
vRes := a;
else
vRes := b;
end if;
return vRes;
end function;
function integerToBoolean (a : integer) return boolean is
variable vRes : boolean;
begin
if a = cFalse then
vRes := false;
else
vRes := true;
end if;
return vRes;
end function;
function booleanToInteger (a : boolean) return integer is
variable vRes : integer;
begin
if a = false then
vRes := cFalse;
else
vRes := cTrue;
end if;
return vRes;
end function;
function byteSwap (iVector : std_logic_vector) return std_logic_vector is
variable vResult : std_logic_vector(iVector'range);
variable vLeftIndex : natural;
variable vRightIndex : natural;
begin
assert ((iVector'length mod cByteLength) = 0)
report "Byte swapping can't be done with that vector!"
severity failure;
for i in iVector'length / cByteLength downto 1 loop
vLeftIndex := i;
vRightIndex := iVector'length / cByteLength - i + 1;
vResult(vLeftIndex * cByteLength - 1 downto (vLeftIndex-1) * cByteLength) :=
iVector(vRightIndex * cByteLength - 1 downto (vRightIndex-1) * cByteLength);
end loop;
return vResult;
end function;
function wordSwap (iVector : std_logic_vector) return std_logic_vector is
variable vResult : std_logic_vector(iVector'range);
variable vLeftIndex : natural;
variable vRightIndex : natural;
begin
assert ((iVector'length mod cWordLength) = 0)
report "Word swapping can't be done with that vector!"
severity failure;
for i in iVector'length / cWordLength downto 1 loop
vLeftIndex := i;
vRightIndex := iVector'length / cWordLength - i + 1;
vResult(vLeftIndex * cWordLength - 1 downto (vLeftIndex-1) * cWordLength) :=
iVector(vRightIndex * cWordLength - 1 downto (vRightIndex-1) * cWordLength);
end loop;
return vResult;
end function;
function reduceOr (iVector : std_logic_vector) return std_logic is
variable vRes_tmp : std_logic;
begin
-- initialize result variable
vRes_tmp := cInactivated;
for i in iVector'range loop
vRes_tmp := vRes_tmp or iVector(i);
end loop;
return vRes_tmp;
end function;
function reduceAnd (iVector : std_logic_vector) return std_logic is
variable vRes_tmp : std_logic;
begin
-- initialize result variable
vRes_tmp := cActivated;
for i in iVector'range loop
vRes_tmp := vRes_tmp and iVector(i);
end loop;
return vRes_tmp;
end function;
end Global; | gpl-2.0 | a9dfc1bf046bee24aafb7e1587f4ff61 | 0.604213 | 4.682069 | false | false | false | false |
dangpzanco/sistemas-digitais | BIN2BCD.vhd | 1 | 1,122 | library ieee;
use ieee.std_logic_1164.all;
--D = ENTRADA NUMERICA
--U = UNITS
--T = TENS
--H = HUNDREDS
entity bin2bcd is
port ( CLK, RST: in std_logic;
D : in std_logic_vector(7 downto 0);
U, T, H : out std_logic_vector(3 downto 0)
);
end bin2bcd;
architecture bin_estru of bin2bcd is
signal S1, S2, S3, S4, S5, S6, S7: std_logic_vector(3 downto 0);
signal X1, X2, X3, X4, X5, X6, X7: std_logic_vector(3 downto 0);
component add3
port ( Num : in std_logic_vector(3 downto 0);
Sum : out std_logic_vector(3 downto 0)
);
end component;
begin
X1 <= '0' & D(7 downto 5);
X2 <= S1(2 downto 0) & D(4);
X3 <= S2(2 downto 0) & D(3);
X4 <= S3(2 downto 0) & D(2);
X5 <= S4(2 downto 0) & D(1);
X6 <= '0' & S1(3) & S2(3) & S3(3);
X7 <= S6(2 downto 0) & S4(3);
C1: add3 port map (X1, S1);
C2: add3 port map (X2, S2);
C3: add3 port map (X3, S3);
C4: add3 port map (X4, S4);
C5: add3 port map (X5, S5);
C6: add3 port map (X6, S6);
C7: add3 port map (X7, S7);
U <= S5(2 downto 0) & D(0);
T <= S7(2 downto 0) & S5(3);
H <= "00" & S6(3) & S7(3);
end bin_estru; | mit | 3a320668b53275d55b198fd07a41f3ab | 0.56328 | 2.093284 | false | false | false | false |
Kalycito-open-automation/openPOWERLINK_V2_old_25-06-2014 | hardware/ipcore/common/lib/src/edgedetectorRtl.vhd | 2 | 4,066 | -------------------------------------------------------------------------------
--! @file edgedetectorRtl.vhd
--
--! @brief Edge detector
--
--! @details This is an edge detector circuit providing any, rising and falling
--! edge outputs.
-------------------------------------------------------------------------------
--
-- (c) B&R, 2013
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.global.all;
entity edgedetector is
port (
--! Asynchronous reset
iArst : in std_logic;
--! Clock
iClk : in std_logic;
--! Enable detection
iEnable : in std_logic;
--! Data to be sampled
iData : in std_logic;
--! Rising edge detected (unregistered)
oRising : out std_logic;
--! Falling edge detected (unregistered)
oFalling : out std_logic;
--! Any edge detected (unregistered)
oAny : out std_logic
);
end edgedetector;
architecture rtl of edgedetector is
--! Register to delay input by one clock cycle
signal reg : std_logic;
--! Register next
signal reg_next : std_logic;
--! Second register
signal reg_l : std_logic;
--! Second register next
signal reg_l_next : std_logic;
begin
-- assign input data to register
reg_next <= iData;
--! Detection
comb : process (
iEnable,
reg,
reg_l
)
begin
-- default
oRising <= cInactivated;
oFalling <= cInactivated;
oAny <= cInactivated;
if iEnable = cActivated then
-- rising edge
if reg_l = cInactivated and reg = cActivated then
oRising <= cActivated;
oAny <= cActivated;
end if;
-- falling edge
if reg_l = cActivated and reg = cInactivated then
oFalling <= cActivated;
oAny <= cActivated;
end if;
end if;
end process;
reg_l_next <= reg;
--! Clock process
regClk : process(iArst, iClk)
begin
if iArst = cActivated then
reg <= cInactivated;
reg_l <= cInactivated;
elsif rising_edge(iClk) then
reg <= reg_next;
reg_l <= reg_l_next;
end if;
end process;
end rtl;
| gpl-2.0 | e4df01fb85d1f715199c4757d02e0d71 | 0.587309 | 4.794811 | false | false | false | false |
Kalycito-open-automation/openPOWERLINK_V2_old_25-06-2014 | hardware/ipcore/common/lib/src/synchronizerRtl.vhd | 2 | 3,351 | -------------------------------------------------------------------------------
--! @file synchronizerRtl.vhd
--
--! @brief Synchronizer
--
--! @details This is a synchronizer with configurable stage size.
-------------------------------------------------------------------------------
--
-- (c) B&R, 2013
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.global.all;
entity synchronizer is
generic (
--! Stages
gStages : natural := 2;
--! Initialization level
gInit : std_logic := cInactivated
);
port (
--! Asynchronous reset
iArst : in std_logic;
--! Clock
iClk : in std_logic;
--! Asynchronous input
iAsync : in std_logic;
--! Synchronous output
oSync : out std_logic
);
end synchronizer;
architecture rtl of synchronizer is
--! Meta registers used to synchronize input signal
signal metaReg : std_logic_vector(gStages-1 downto 0);
--! Meta registers next
signal metaReg_next : std_logic_vector(metaReg'range);
begin
-- handle wrong stage generic
assert (gStages > 0)
report "gStages must be set higher 0!" severity failure;
-- output last synchronizer stage
oSync <= metaReg(metaReg'left);
-- assign asynchronous signal to metaRegisters
metaReg_next <= metaReg(metaReg'left-1 downto 0) & iAsync;
reg : process(iArst, iClk)
begin
if iArst = cActivated then
metaReg <= (others => gInit);
elsif rising_edge(iClk) then
metaReg <= metaReg_next;
end if;
end process;
end rtl;
| gpl-2.0 | 5b188f5d55219dcb96357d29dd814d6e | 0.63026 | 4.706461 | false | false | false | false |
s-kostyuk/course_project_csch | pilot_processor_signed_div/control_unit.vhd | 1 | 2,813 | library IEEE;
use IEEE.std_logic_1164.all;
entity control_unit is
port ( Clk: in STD_LOGIC; Reset: in STD_LOGIC;
X: in STD_LOGIC_vector(8 downto 1);
Y: out STD_LOGIC_vector(16 downto 1));
end control_unit;
architecture control_unit of control_unit is
-- Òèï, èñïîëüçóþùèé ñèìâîëüíîå êîäèðîâàíèå ñîñòîÿíèé àâòîìàòà
type State_type is (a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12);
signal State, NextState: State_type;
begin
-- NextState logic (combinatorial)
Sreg0_NextState: process (State)
begin
-- èíèöèàëèçàöèÿ çíà÷åíèé âûõîäîâ
y <= (others => '0');
case State is
when a1 =>
NextState <= a2;
y(1) <= '1';
y(2) <= '1';
when a2=>
if x(1) = '0' then
NextState <= a3;
y(3) <= '1';
y(4) <= '1';
else
NextState <= a11;
y(15) <= '1';
end if;
when a3=>
if x(2) = '0' then
NextState <= a4;
y(5) <= '1';
else
NextState <= a5;
y(6) <= '1';
end if;
when a4=>
if x(2) = '1' then
NextState <= a6;
y(7) <= '1';
y(8) <= '1';
else
NextState <= a1;
y(16) <= '1';
end if;
when a5=>
if x(2) = '0' then
NextState <= a6;
y(7) <= '1';
y(8) <= '1';
else
NextState <= a1;
y(16) <= '1';
end if;
when a6=>
if x(2) = '0' then
NextState <= a7;
y(9) <= '1';
else
NextState <= a7;
y(10) <= '1';
end if;
when a7=>
NextState <= a8;
y(11) <= '1';
when a8=>
if x(3) = '0' then
if x(2) = '0' then
NextState <= a9;
y(12) <= '1';
else
NextState <= a10;
y(12) <= '1';
end if;
else
NextState <= a11;
if x(4) = '0' then
if x(5) = '0' then
y(6) <= '1';
else
y(5) <= '1';
end if;
end if;
end if;
when a9=>
NextState <= a6;
y(5) <= '1';
when a10=>
NextState <= a6;
y(6) <= '1';
when a11=>
NextState <= a12;
if x(6) = '0' then
if x(7) = '1' then
if x(8) = '1' then
y(13) <= '1';
end if;
end if;
else
if x(7) = '0' then
y(13) <= '1';
elsif x(8) = '0' then
y(13) <= '1';
end if;
end if;
when a12=>
NextState <= a1;
y(14) <= '1';
when others => NextState <= a1;
-- ïðèñâîåíèå çíà÷åíèé âûõîäàì äëÿ ñîñòîÿíèÿ ïî óìîë÷àíèþ
--Óñòàíîâêà àâòîìàòà â íà÷àëüíîå ñîñòîÿíèå
end case;
end process;
Sreg0_CurrentState: process (Clk, reset)
begin
if Reset='0' then
State <= a1; -- íà÷àëüíîå ñîñòîÿíèå
elsif rising_edge(clk) then
State <= NextState;
end if;
end process;
end control_unit; | mit | 72fcfa0402b920b5d12b9822b5c6c3f5 | 0.456808 | 2.454625 | false | false | false | false |
matbur95/ucisw-pro | pro5a/master.vhd | 2 | 5,991 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:03:57 04/05/2017
-- Design Name:
-- Module Name: master - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MASTER is
Port ( ADC_DOA : in STD_LOGIC_VECTOR (13 downto 0);
ADC_DOB : in STD_LOGIC_VECTOR (13 downto 0);
ADC_BUSY : in STD_LOGIC;
RST_BUTTON : in STD_LOGIC;
CLK : in STD_LOGIC;
POS : in STD_LOGIC_VECTOR(19 downto 0);
DATA : in STD_LOGIC;
DATA_CON : in STD_LOGIC;
Line : out STD_LOGIC_VECTOR (63 downto 0);
Blank : out STD_LOGIC_VECTOR (15 downto 0);
ADDR : out STD_LOGIC_VECTOR (13 downto 0);
VGA_COLOR : out STD_LOGIC_VECTOR(2 downto 0);
AMP_WE : out STD_LOGIC;
ADC_Start : out STD_LOGIC;
AMP_DI : out STD_LOGIC_VECTOR (7 downto 0));
end MASTER;
architecture Behavioral of MASTER is
-- constant SIDE : integer := 50;
constant SIDE : signed ( 10 downto 0 ) := to_signed( 20, 11);
constant VMAX : signed ( 10 downto 0 ) := to_signed( 600, 11);
constant HMAX : signed ( 10 downto 0 ) := to_signed( 800, 11);
-- constant HMAX : integer := 800;
-- signal BOX_HPOS : integer range -100 to 1000 := 400;
signal BOX_HPOS : signed( 10 downto 0) := to_signed( 0, 11 );
signal BOX_VPOS : signed( 10 downto 0) := to_signed( 550, 11 );
constant BOX_VPOS_INIT : signed ( 10 downto 0 ) := to_signed( 550, 11);
constant BOX_HPOS_INIT : signed ( 10 downto 0 ) := to_signed( 0, 11);
-- signal BOX_VPOS : integer range -100 to 1000 := 300;
signal HPOS : signed( 10 downto 0) := to_signed( 0, 11 );
signal VPOS : signed( 10 downto 0) := to_signed( 0, 11 );
-- signal HPOS : integer range 0 to 800 := 0;
-- signal VPOS : integer range 0 to 600 := 0;
signal VGA_COLOR_INT : STD_LOGIC_VECTOR(2 downto 0);
signal CLKTIME : signed(22 downto 0) := (others =>'0');
signal PLAYTIME : signed(15 downto 0) := to_signed(0, 16);
signal TOUCHING : STD_LOGIC := '0';
signal TIMER_EN : STD_LOGIC := '1';
signal RESTART : STD_LOGIC := '0';
begin
HPOS <= signed('0' & POS(19 downto 10));
VPOS <= signed('0' & POS(9 downto 0));
AMP_WE <= '1' when HPOS = 0 and VPOS = 0 else '0';
AMP_DI <= X"22";
ADC_Start <= '1' when HPOS = HMAX and VPOS = VMAX else '0';
Blank <= X"0C30";
Line <= ADC_DOA & "00" & X"00" & ADC_DOB & "00" & X"00" & STD_LOGIC_VECTOR(PLAYTIME);
BOX: process (CLK, HPOS, VPOS)
begin
if rising_edge(CLK) then
if HPOS = 0 and VPOS = 0 then
BOX_HPOS <= BOX_HPOS - signed(ADC_DOA(13 downto 11));
BOX_VPOS <= BOX_VPOS + signed(ADC_DOB(13 downto 11));
end if;
if BOX_HPOS < 0 then
BOX_HPOS <= to_signed(0, 11);
elsif BOX_HPOS > HMAX - SIDE then
BOX_HPOS <= HMAX - SIDE;
end if;
if BOX_VPOS < 0 then
BOX_VPOS <= to_signed(0, 11);
elsif BOX_VPOS > VMAX - SIDE then
BOX_VPOS <= VMAX - SIDE;
end if;
if BOX_VPOS < 2 then
TIMER_EN <= '0';
end if;
if RESTART = '1' then
BOX_HPOS <= BOX_HPOS_INIT;
BOX_VPOS <= BOX_VPOS_INIT;
TIMER_EN <= '1';
end if;
if TOUCHING = '1' then
TOUCHING <= '0';
BOX_HPOS <= BOX_HPOS + signed(ADC_DOA(13 downto 11));
BOX_VPOS <= BOX_VPOS - signed(ADC_DOB(13 downto 11));
end if;
TOUCHING <= '0';
if DATA = '0' and
HPOS > BOX_HPOS and HPOS < BOX_HPOS + SIDE and
VPOS > BOX_VPOS and VPOS < BOX_VPOS + SIDE then
TOUCHING <= '1';
end if;
end if;
end process BOX;
ADDR <= STD_LOGIC_VECTOR(VPOS(9 downto 3)) & STD_LOGIC_VECTOR(HPOS(9 downto 3));
VGA_COLOR_INT <= DATA_CON & DATA_CON & not DATA_CON when TIMER_EN = '0'
else B"101" when HPOS > BOX_HPOS and HPOS < BOX_HPOS + SIDE and VPOS > BOX_VPOS and VPOS < BOX_VPOS + SIDE
else DATA & DATA & not DATA;
-- VGA_COLOR_INT <= DATA & DATA & not DATA;
VGA_COLOR <= VGA_COLOR_INT;
TIMER: process (CLK)
begin
if rising_edge(CLK) then
if RESTART = '1' then
PLAYTIME <= to_signed(0, 16);
-- TIMER_EN <= '1';
end if;
if TOUCHING = '1' and TIMER_EN = '1' then
PLAYTIME <= PLAYTIME + 1;
-- PLAYTIME <= to_signed(0, 16);
end if;
if TIMER_EN = '1' then
if CLKTIME = "10011000100101101000000" then -- 5 MHz
CLKTIME <= "00000000000000000000000";
if PLAYTIME = X"ffff" then
PLAYTIME <= to_signed(0, 16);
else
PLAYTIME <= PLAYTIME + 1;
end if;
else
CLKTIME <= CLKTIME + 1;
end if;
end if;
end if;
end process TIMER;
process (CLK)
begin
if rising_edge(CLK) then
if RST_BUTTON = '1' then
RESTART <= '1';
else
RESTART <= '0';
end if;
end if;
end process;
end Behavioral;
| mit | 259290979f947f04a508b9bd1bb44555 | 0.517777 | 3.578853 | false | false | false | false |
bangonkali/quartus-sockit | soc_system/synthesis/submodules/alt_vipvfr131_common_package.vhd | 1 | 154,837 | -- Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
-- use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any
-- output files any of the foregoing (including device programming or
-- simulation files), and any associated documentation or information are
-- expressly subject to the terms and conditions of the Altera Program
-- License Subscription Agreement or other applicable license agreement,
-- including, without limitation, that your use is for the sole purpose
-- of programming logic devices manufactured by Altera and sold by Altera
-- or its authorized distributors. Please refer to the applicable
-- agreement for further details.
--synthesis library work
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE STD.textio.ALL;
PACKAGE alt_vipvfr131_common_package IS
CONSTANT SIMULATION_ON : INTEGER := 1;
CONSTANT SIMULATION_OFF : INTEGER := 0;
CONSTANT OPTIMIZED_ON : INTEGER := 1;
CONSTANT OPTIMIZED_OFF : INTEGER := 0;
CONSTANT FAMILY_NONE : INTEGER := 0;
CONSTANT FAMILY_STRATIX : INTEGER := 10;
CONSTANT FAMILY_STRATIXII : INTEGER := 11;
CONSTANT FAMILY_STRATIXIII : INTEGER := 12;
CONSTANT FAMILY_STRATIXIV : INTEGER := 13;
CONSTANT FAMILY_CYCLONE : INTEGER := 30;
CONSTANT FAMILY_CYCLONEII : INTEGER := 31;
CONSTANT FAMILY_CYCLONEIII : INTEGER := 32;
CONSTANT FAMILY_CYCLONELPS : INTEGER := 33;
CONSTANT FAMILY_HARDCOPYII : INTEGER := 40;
CONSTANT FAMILY_HARDCOPYIII : INTEGER := 41;
CONSTANT ALT_MEM_MODE_AUTO : INTEGER := -1;
CONSTANT ALT_MEM_MODE_LE : INTEGER := 0;
CONSTANT ALT_MEM_MODE_M512 : INTEGER := 1;
CONSTANT ALT_MEM_MODE_M4K : INTEGER := 2;
CONSTANT ALT_MEM_MODE_MRAM : INTEGER := 3;
CONSTANT ALT_SHIFT_MODE_LOGICAL : INTEGER := 0;
CONSTANT ALT_SHIFT_MODE_ARITH : INTEGER := 1;
CONSTANT ALT_SHIFT_MODE_ROTATE : INTEGER := 2;
CONSTANT ALT_SHIFT_DIREC_LEFT : INTEGER := 0;
CONSTANT ALT_SHIFT_DIREC_RIGHT : INTEGER := 1;
CONSTANT ALT_SHIFT_DIREC_BOTH : INTEGER := 2;
--------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------
function wide_enough_for(max : integer) return integer;
function two_to_the_power(v : integer) return integer;
function dead_bits(b : integer) return std_logic_vector;
function maximum(a, b : integer) return integer;
function minimum(a, b : integer) return integer;
function calculate_be_width(be_used : boolean; data_width : integer) return integer;
function calculate_be_width(be_used : integer; data_width : integer) return integer;
function calculate_be_width(data_width : integer) return integer;
function family_string(f : integer) return string;
function to_string(slv : std_logic_vector) return string;
function boolean_to_int(value : boolean) return integer;
COMPONENT alt_vipvfr131_common_avalon_mm_master IS
GENERIC (
-- NAME : STRING := "";
-- OPTIMIZED : INTEGER := OPTIMIZED_ON;
-- FAMILY : INTEGER := FAMILY_STRATIX;
ADDR_WIDTH : INTEGER := 16;
DATA_WIDTH : INTEGER := 16;
-- BYTEENABLE_WIDTH : INTEGER := 2;
-- BYTEENABLE_USED : INTEGER := 1;
READ_USED : INTEGER := 1;
WRITE_USED : INTEGER := 1;
-- CLOCKS_ARE_SYNC : INTEGER := 0;
-- ADDRESS_GROUP : integer := 1;
-- INTERRUPT_USED : INTEGER := 1;
-- INTERRUPT_WIDTH : INTEGER := 8
-- new:
MAX_BURST_LENGTH : INTEGER := 1024;
READ_FIFO_DEPTH : INTEGER := 8;
WRITE_FIFO_DEPTH : INTEGER := 8;
COMMAND_FIFO_DEPTH : INTEGER := 8;
WRITE_TARGET_BURST_SIZE : INTEGER := 5;
READ_TARGET_BURST_SIZE : INTEGER := 5;
BURST_WIDTH : INTEGER := 6;
CLOCKS_ARE_SAME : INTEGER := 1
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
-- ena : IN STD_LOGIC := '1';
addr : IN STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
command : IN STD_LOGIC;
is_write_not_read : IN STD_LOGIC;
is_burst : IN STD_LOGIC;
burst_length : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
-- addr_en : IN STD_LOGIC := '0';
writedata : IN STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
write : IN STD_LOGIC := '0';
-- byteenable : IN STD_LOGIC_VECTOR(BYTEENABLE_WIDTH-1 DOWNTO 0) := (OTHERS=>'1');
-- byteenable_en : IN STD_LOGIC := '0';
readdata : OUT STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0);
read : IN STD_LOGIC := '0';
-- ready : OUT STD_LOGIC;
stall_command : OUT STD_LOGIC;
stall_out : OUT STD_LOGIC;
stall_in : OUT STD_LOGIC;
-- activeirqs : OUT STD_LOGIC_VECTOR(INTERRUPT_WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
av_address : OUT STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0) ;
av_writedata : OUT STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0);
-- av_byteenable : OUT STD_LOGIC_VECTOR(BYTEENABLE_WIDTH-1 DOWNTO 0);
av_write : OUT STD_LOGIC;
av_read : OUT STD_LOGIC;
av_clock : IN STD_LOGIC;
-- av_reset : IN STD_LOGIC := '0';
av_readdata : IN STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
av_readdatavalid : IN STD_LOGIC;
av_waitrequest : IN STD_LOGIC := '0';
av_burstcount : OUT STD_LOGIC_VECTOR(BURST_WIDTH-1 DOWNTO 0) := (OTHERS=>'0')
-- av_interrupt : IN STD_LOGIC_VECTOR(INTERRUPT_WIDTH-1 DOWNTO 0) := (OTHERS=>'0')
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_avalon_mm_master_fifo IS
GENERIC (
NAME : STRING := "";
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
ADDR_WIDTH : INTEGER := 16;
DATA_WIDTH : INTEGER := 16;
BYTEENABLE_WIDTH : INTEGER := 2;
BYTEENABLE_USED : INTEGER := 1;
READ_USED : INTEGER := 1;
WRITE_USED : INTEGER := 1;
OLD_STYLE : INTEGER := 1
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
ena : IN STD_LOGIC := '1';
addr : IN STD_LOGIC_VECTOR( ADDR_WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
addr_en : IN STD_LOGIC := '0';
wdata : IN STD_LOGIC_VECTOR( DATA_WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
wdata_en : IN STD_LOGIC := '0';
rdata_en : IN STD_LOGIC := '0';
byteenable : IN STD_LOGIC_VECTOR( BYTEENABLE_WIDTH-1 DOWNTO 0) := (OTHERS=>'1');
byteenable_en : IN STD_LOGIC := '0';
rdata : OUT STD_LOGIC_VECTOR( DATA_WIDTH-1 DOWNTO 0);
ready : OUT STD_LOGIC;
stall : OUT STD_LOGIC;
av_address : OUT STD_LOGIC_VECTOR( ADDR_WIDTH-1 DOWNTO 0) ;
av_writedata : OUT STD_LOGIC_VECTOR( DATA_WIDTH-1 DOWNTO 0);
av_byteenable : OUT STD_LOGIC_VECTOR( BYTEENABLE_WIDTH-1 DOWNTO 0);
av_write : OUT STD_LOGIC;
av_read : OUT STD_LOGIC;
av_clock : IN STD_LOGIC;
av_reset : IN STD_LOGIC := '0';
av_readdata : IN STD_LOGIC_VECTOR( DATA_WIDTH-1 DOWNTO 0):= (OTHERS=>'0');
av_readdatavalid : IN STD_LOGIC := '0';
av_waitrequest : IN STD_LOGIC := '0'
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_avalon_mm_mem_slave IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
INIT_FILE : STRING := "UNUSED";
WIDTH : INTEGER := 16;
ADDRESS_WIDTH : INTEGER := 16;
DEPTH : INTEGER := -1;
INTERRUPT_USED : INTEGER := 1;
DELAY_SLOTS : INTEGER := 0;
LATENCY : INTEGER := 1;
MODE : INTEGER := ALT_MEM_MODE_AUTO;
CLOCKS_ARE_SYNC : INTEGER := 1
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
ena : IN STD_LOGIC := '1';
addr : IN STD_LOGIC_VECTOR( ADDRESS_WIDTH-1 DOWNTO 0) := (others=>'0');
addr_en : IN STD_LOGIC := '0';
rdata : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0);
wdata : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
wdata_en : IN STD_LOGIC := '0';
setirq : IN STD_LOGIC := '0';
setirq_en : IN STD_LOGIC := '0';
irqactive : IN STD_LOGIC := '0';
av_address : IN STD_LOGIC_VECTOR( ADDRESS_WIDTH-1 DOWNTO 0) := (others=>'0');
av_writedata : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
av_readdata : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0);
av_clock : IN STD_LOGIC := '0';
av_write : IN STD_LOGIC := '0';
av_chipselect: IN STD_LOGIC := '0';
av_reset : IN STD_LOGIC := '0';
av_waitrequest : OUT STD_LOGIC := '0';
av_interrupt : OUT STD_LOGIC := '0'
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_avalon_st_credit_user IS
GENERIC (
NAME : STRING := "";
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
ADDR_WIDTH : INTEGER := 32;
DATA_WIDTH : INTEGER := 32;
CREDIT_WIDTH : INTEGER := 10;
CREDIT_INCREMENT : INTEGER := 1
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
ena : IN STD_LOGIC := '1';
hascredit : OUT STD_LOGIC;
getcredit : IN STD_LOGIC := '0';
getcredit_en : IN STD_LOGIC := '0';
trygetcredit : IN STD_LOGIC := '0';
trygetcredit_en: IN STD_LOGIC := '0';
gotcredit : OUT STD_LOGIC;
stall : OUT STD_LOGIC;
read : OUT STD_LOGIC;
address : OUT STD_LOGIC_VECTOR( ADDR_WIDTH-1 DOWNTO 0);
waitrequest : IN STD_LOGIC := '0';
readdatavalid : IN STD_LOGIC := '0';
readdata : IN STD_LOGIC_VECTOR( DATA_WIDTH-1 DOWNTO 0):= (OTHERS=>'0')
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_avalon_st_input IS
generic (
NAME : string := "";
OPTIMIZED : integer := OPTIMIZED_ON;
FAMILY : integer := FAMILY_STRATIX;
WIDTH : integer := 16;
END_PACKET_USED : integer := 0;
SYM_PER_BEAT : integer := 0;
READY_LATENCY : integer := 1
);
port (
clock : in std_logic;
reset : in std_logic;
ena : in std_logic := '1';
stall : out std_logic;
dataavail : out std_logic;
datavalid : out std_logic;
rdata : out std_logic_vector(WIDTH - 1 downto 0);
takeb : in std_logic;
takeb_en : in std_logic;
takenb : in std_logic;
takenb_en : in std_logic;
expecteop : in std_logic := '1';
eop : out std_logic;
ready : out std_logic;
valid : in std_logic := '1';
data : in std_logic_vector(width-1 downto 0);
startofpacket : in std_logic := '0';
endofpacket : in std_logic := '0'
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_avalon_st_output IS
GENERIC (
NAME : STRING := "";
WIDTH : INTEGER := 16;
READY_USED : INTEGER := 1;
END_PACKET_USED : INTEGER := 0;
SYM_PER_BEAT : integer := 0;
READY_LATENCY : INTEGER := 1
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
ena : IN STD_LOGIC := '1';
spaceavail : OUT STD_LOGIC;
wdata : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
wdata_en : IN STD_LOGIC := '0';
takeb : IN STD_LOGIC := '0';
takeb_en : IN STD_LOGIC := '0';
takenb : IN STD_LOGIC := '0';
takenb_en : IN STD_LOGIC := '0';
eop : IN STD_LOGIC := '0';
seteop : IN STD_LOGIC := '0';
seteop_en : IN STD_LOGIC := '0';
stall : OUT STD_LOGIC;
ready : IN STD_LOGIC := '1';
valid : OUT STD_LOGIC;
data : OUT STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);
startofpacket : OUT STD_LOGIC;
endofpacket : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_select IS
GENERIC (
NAME : STRING := "";
WIDTH_D : INTEGER := 16;
WIDTH_Q : INTEGER := 16;
SELECT_LOW : INTEGER := 0;
SIGN_EXTEND : INTEGER := 1
);
PORT (
d : IN STD_LOGIC_VECTOR( WIDTH_D-1 DOWNTO 0) := (others =>'0');
q : OUT STD_LOGIC_VECTOR( WIDTH_Q-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_stack IS
GENERIC (
NAME : STRING := "";
DEPTH : INTEGER := 16;
WIDTH : INTEGER := 16
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC := '0';
ena : IN STD_LOGIC := '1';
enable : IN STD_LOGIC := '0';
enable_en : IN STD_LOGIC := '0';
pushNpop : IN STD_LOGIC := '0';
d : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
q : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_trigger_to_synced_pulse IS
port (
signal reset : IN STD_LOGIC;
signal clk : IN STD_LOGIC;
signal sync_reset : IN STD_LOGIC;
signal sync_clk : IN STD_LOGIC;
signal trigger : IN STD_LOGIC;
signal return_pulse : IN STD_LOGIC;
signal synced_pulse : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT alt_loadable_pc IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
PROGRAM_FILE : STRING := "program.mif";
PROGRAM_TRACE: STRING := "program.trace";
LATENCY : INTEGER := 3;
PC_WIDTH : INTEGER := 16;
PC_NUM_WORDS : INTEGER := 256;
PCW_WIDTH : INTEGER := 32;
PCW_ROUND : INTEGER := 0;
TTA_WIDTH : INTEGER := 16;
TTA_NUM_WORDS : INTEGER := 256;
TTAW_WIDTH : INTEGER := 32;
AV_WIDTH : INTEGER := 15;
AV_NUM_WORDS : INTEGER := 128;
AVW_WIDTH : INTEGER := 32
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
reset_req : OUT STD_LOGIC;
ena : IN STD_LOGIC := '1';
pcw : OUT STD_LOGIC_VECTOR( PCW_WIDTH-1 DOWNTO 0);
pc : OUT STD_LOGIC_VECTOR( PC_WIDTH-1 DOWNTO 0);
stall : OUT STD_LOGIC;
nextpc : IN STD_LOGIC_VECTOR( PC_WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
usenextpc : IN STD_LOGIC := '0';
usenextpc_en : IN STD_LOGIC := '0';
hold : IN STD_LOGIC := '0';
hold_en : IN STD_LOGIC := '0';
av_address : IN STD_LOGIC_VECTOR( AV_WIDTH-1 DOWNTO 0) := (others=>'0');
av_writedata : IN STD_LOGIC_VECTOR( AVW_WIDTH-1 DOWNTO 0) := (others=>'0');
av_readdata : OUT STD_LOGIC_VECTOR( AVW_WIDTH-1 DOWNTO 0);
av_clock : IN STD_LOGIC := '0';
av_write : IN STD_LOGIC := '0';
av_chipselect: IN STD_LOGIC := '0';
av_reset : IN STD_LOGIC := '0';
av_byteenable : IN STD_LOGIC_VECTOR( (AVW_WIDTH/8)-1 DOWNTO 0) := (others=>'1')
);
END COMPONENT;
COMPONENT tta_x_addwithsload IS
GENERIC (
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
L : INTEGER
);
PORT (
clk, reset : IN STD_LOGIC;
ena : IN STD_LOGIC := '1';
sreset : IN STD_LOGIC := '0';
sload : IN STD_LOGIC;
loadval_in : IN UNSIGNED(L-1 DOWNTO 0);
doAddnSub : IN STD_LOGIC := '1';
addL_in : IN UNSIGNED(L-1 DOWNTO 0);
addR_in : IN UNSIGNED(L-1 DOWNTO 0);
sum_out : OUT UNSIGNED(L-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT tta_x_acounter IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
WIDTH : INTEGER := 16
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
ena : IN STD_LOGIC := '1';
d : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
d_en : IN STD_LOGIC := '0';
q : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0);
q_en : IN STD_LOGIC := '1'
);
END COMPONENT;
COMPONENT tta_x_au IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
WIDTH : INTEGER := 16;
LATENCY : INTEGER := 1
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
ena : IN STD_LOGIC := '1';
a : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
a_en : IN STD_LOGIC := '0';
b : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
c : IN STD_LOGIC := '0';
c_en : IN STD_LOGIC := '0';
l : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
l_en : IN STD_LOGIC := '0';
q : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0);
S : OUT STD_LOGIC;
nS : OUT STD_LOGIC;
CC : OUT STD_LOGIC;
nCC : OUT STD_LOGIC;
sclr : IN STD_LOGIC := '0';
subNadd : IN STD_LOGIC := '0'
);
END COMPONENT;
COMPONENT tta_x_av_master_fifo_16_16 IS
PORT
(
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
wrreq : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
rdclk : IN STD_LOGIC ;
wrclk : IN STD_LOGIC ;
aclr : IN STD_LOGIC := '0';
q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
rdfull : OUT STD_LOGIC ;
rdempty : OUT STD_LOGIC ;
rdusedw : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
wrfull : OUT STD_LOGIC ;
wrempty : OUT STD_LOGIC ;
wrusedw : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END COMPONENT;
COMPONENT tta_x_av_master_fifo_16_16_cii IS
PORT
(
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
wrreq : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
rdclk : IN STD_LOGIC ;
wrclk : IN STD_LOGIC ;
aclr : IN STD_LOGIC := '0';
q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
rdfull : OUT STD_LOGIC ;
rdempty : OUT STD_LOGIC ;
rdusedw : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
wrfull : OUT STD_LOGIC ;
wrempty : OUT STD_LOGIC ;
wrusedw : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END COMPONENT;
COMPONENT tta_x_av_master_fifo_36_16 IS
PORT
(
data : IN STD_LOGIC_VECTOR (35 DOWNTO 0);
wrreq : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
rdclk : IN STD_LOGIC ;
wrclk : IN STD_LOGIC ;
aclr : IN STD_LOGIC := '0';
q : OUT STD_LOGIC_VECTOR (35 DOWNTO 0);
rdfull : OUT STD_LOGIC ;
rdempty : OUT STD_LOGIC ;
rdusedw : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
wrfull : OUT STD_LOGIC ;
wrempty : OUT STD_LOGIC ;
wrusedw : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END COMPONENT;
COMPONENT tta_x_av_master_fifo_36_16_cii IS
PORT
(
data : IN STD_LOGIC_VECTOR (35 DOWNTO 0);
wrreq : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
rdclk : IN STD_LOGIC ;
wrclk : IN STD_LOGIC ;
aclr : IN STD_LOGIC := '0';
q : OUT STD_LOGIC_VECTOR (35 DOWNTO 0);
rdfull : OUT STD_LOGIC ;
rdempty : OUT STD_LOGIC ;
rdusedw : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
wrfull : OUT STD_LOGIC ;
wrempty : OUT STD_LOGIC ;
wrusedw : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END COMPONENT;
COMPONENT tta_x_bshift IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
SEL_WIDTH : INTEGER := 2;
WIDTH : INTEGER := 16
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
ena : IN STD_LOGIC := '1';
d : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
d_en : IN STD_LOGIC := '0';
sel : IN STD_LOGIC_VECTOR( SEL_WIDTH-1 DOWNTO 0) := (others=>'0');
arithNlogic : IN STD_LOGIC := '0';
q : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0);
sclr : IN STD_LOGIC := '0';
sclr_en : IN STD_LOGIC := '0'
);
END COMPONENT;
COMPONENT tta_x_channel IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
WAIT_STATES : INTEGER := 0;
WIDTH : INTEGER := 16
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
d : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
d_en : IN STD_LOGIC := '0';
d_ena : IN STD_LOGIC := '1';
d_ready: OUT STD_LOGIC;
d_stall: OUT STD_LOGIC;
q : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0);
q_ready: OUT STD_LOGIC;
q_en : IN STD_LOGIC := '0';
q_ena : IN STD_LOGIC := '1';
q_stall: OUT STD_LOGIC
);
END COMPONENT;
COMPONENT tta_x_cmult IS
generic (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
DELAY_SLOTS : integer := 2;
WIDTH : integer := 32;
USE_COMPLEX_INPUT_PORTS : STRING := "TRUE"
);
port (
clock : in std_logic;
ena : in std_logic := '1';
reset : in std_logic;
aR_en : in std_logic := '0';
aR: in std_logic_vector((WIDTH/2)-1 downto 0) := (others=>'0');
aI: in std_logic_vector((WIDTH/2)-1 downto 0) := (others=>'0');
bR: in std_logic_vector((WIDTH/2)-1 downto 0) := (others=>'0');
bI: in std_logic_vector((WIDTH/2)-1 downto 0) := (others=>'0');
a_en : in std_logic := '0';
a: in std_logic_vector(WIDTH-1 downto 0) := (others=>'0');
b: in std_logic_vector(WIDTH-1 downto 0) := (others=>'0');
q : out std_logic_vector((2*WIDTH)-1 downto 0);
q_hi: out std_logic_vector(WIDTH-1 downto 0);
q_lo: out std_logic_vector(WIDTH-1 downto 0);
qs : out std_logic_vector((2*WIDTH)-1 downto 0);
qs_hi: out std_logic_vector(WIDTH-1 downto 0);
qs_lo: out std_logic_vector(WIDTH-1 downto 0);
qR: out std_logic_vector(WIDTH-1 downto 0);
qI: out std_logic_vector(WIDTH-1 downto 0);
qR_hi: out std_logic_vector((WIDTH/2)-1 downto 0);
qI_hi: out std_logic_vector((WIDTH/2)-1 downto 0);
qR_lo: out std_logic_vector((WIDTH/2)-1 downto 0);
qI_lo: out std_logic_vector((WIDTH/2)-1 downto 0);
qsR: out std_logic_vector(WIDTH-1 downto 0);
qsI: out std_logic_vector(WIDTH-1 downto 0);
qsR_hi: out std_logic_vector((WIDTH/2)-1 downto 0);
qsI_hi: out std_logic_vector((WIDTH/2)-1 downto 0);
qsR_lo: out std_logic_vector((WIDTH/2)-1 downto 0);
qsI_lo: out std_logic_vector((WIDTH/2)-1 downto 0)
);
END COMPONENT;
COMPONENT tta_x_combine_vec_vec IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
A_WIDTH : INTEGER := 16;
B_WIDTH : INTEGER := 16
);
PORT (
a : IN STD_LOGIC_VECTOR( A_WIDTH-1 DOWNTO 0) := (others=>'0');
b : IN STD_LOGIC_VECTOR( B_WIDTH-1 DOWNTO 0) := (others=>'0');
q : OUT STD_LOGIC_VECTOR( A_WIDTH+B_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT tta_x_constant IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
WIDTH : INTEGER := 16;
VALUE : INTEGER := 0
);
PORT (
q : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT tta_x_constant_accumulator IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
CSEL : INTEGER := 0;
CNSEL : INTEGER := 1;
WIDTH : INTEGER := 16
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
ena : IN STD_LOGIC := '1';
d : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
d_en : IN STD_LOGIC := '0';
l : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
l_en : IN STD_LOGIC := '0';
vsel : IN STD_LOGIC := '0';
q : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0);
S : OUT STD_LOGIC;
nS : OUT STD_LOGIC;
sclr : IN STD_LOGIC := '0'
);
END COMPONENT;
COMPONENT tta_x_dmem IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
INIT_FILE : STRING := "UNUSED";
WIDTH : INTEGER := 16;
ADDRESS_WIDTH : INTEGER := 16;
DELAY_SLOTS : INTEGER := 0
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
ena : IN STD_LOGIC := '1';
Aaddr : IN STD_LOGIC_VECTOR( ADDRESS_WIDTH-1 DOWNTO 0) := (others=>'0');
Aaddr_en : IN STD_LOGIC := '0';
Ardata : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0);
Awdata : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
Awdata_en : IN STD_LOGIC := '0';
Baddr : IN STD_LOGIC_VECTOR( ADDRESS_WIDTH-1 DOWNTO 0) := (others=>'0');
Baddr_en : IN STD_LOGIC := '0';
Brdata : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0);
Bwdata : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
Bwdata_en : IN STD_LOGIC := '0'
);
END COMPONENT;
COMPONENT tta_x_hdmem IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
INIT_FILE : STRING := "UNUSED";
WIDTH : INTEGER := 16;
ADDRESS_WIDTH : INTEGER := 8;
DELAY_SLOTS : INTEGER := 0
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
ena : IN STD_LOGIC := '1';
Aaddr : IN STD_LOGIC_VECTOR( ADDRESS_WIDTH-1 DOWNTO 0) := (others=>'0');
Aaddr_en : IN STD_LOGIC := '0';
Ardata : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0);
Awdata : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
Awdata_en : IN STD_LOGIC := '0';
Baddr : IN STD_LOGIC_VECTOR( ADDRESS_WIDTH-1 DOWNTO 0) := (others=>'0');
Baddr_en : IN STD_LOGIC := '0';
Brdata : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT tta_x_immed IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
WIDTH : INTEGER := 16
);
PORT (
value : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
q : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT tta_x_immed_wire IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX
);
PORT (
value : IN STD_LOGIC := '0';
q : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT tta_x_mac IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
WIDTH_2 : INTEGER := 32;
WIDTH : INTEGER := 16
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
ena : IN STD_LOGIC := '1';
a : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
a_en : IN STD_LOGIC := '1';
b : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
q_hi : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0);
q_lo : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR( (2*WIDTH)-1 DOWNTO 0);
qs_hi : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0);
qs_lo : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0);
qs : OUT STD_LOGIC_VECTOR( (2*WIDTH)-1 DOWNTO 0);
mulNmac : IN STD_LOGIC := '0';
subNadd : IN STD_LOGIC := '0'
);
END COMPONENT;
COMPONENT tta_x_mod_counter IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
MODULO : INTEGER := 66;
WIDTH : INTEGER := 16
);
PORT (
clock : IN STD_LOGIC ;
ena : IN STD_LOGIC := '1';
reset : IN STD_LOGIC := '0' ;
cnt : IN STD_LOGIC := '0';
cnt_en : IN STD_LOGIC := '0';
sclr : IN STD_LOGIC := '0';
sclr_en : IN STD_LOGIC := '0';
d : IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0) := (others => '0');
d_en : IN STD_LOGIC := '0';
q : OUT STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT tta_x_mult IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
WIDTH : INTEGER := 16;
DELAY_SLOTS : INTEGER := 1
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
ena : IN STD_LOGIC := '1';
a : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
a_en : IN STD_LOGIC := '1';
b : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
q_hi : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0);
q_lo : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR( WIDTH*2-1 DOWNTO 0);
qs_hi : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0);
qs_lo : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0);
qs : OUT STD_LOGIC_VECTOR( WIDTH*2-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT tta_x_register IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
WIDTH : INTEGER := 16
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
ena : IN STD_LOGIC := '1';
d : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
q : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0);
d_en : IN STD_LOGIC := '1'
);
END COMPONENT;
COMPONENT tta_x_register3 IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
WIDTH : INTEGER := 16
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
ena : IN STD_LOGIC := '1';
a : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
a_en : IN STD_LOGIC := '1';
b : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
b_en : IN STD_LOGIC := '0';
c : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
c_en : IN STD_LOGIC := '0';
sclr : IN STD_LOGIC := '0';
q : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT tta_x_rshift IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
WIDTH : INTEGER := 16
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
ena : IN STD_LOGIC := '1';
d : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
logicalNarithmetic : IN STD_LOGIC := '1';
l : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
l_en : IN STD_LOGIC := '0';
q : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0);
d_en : IN STD_LOGIC := '1'
);
END COMPONENT;
COMPONENT tta_x_smem IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
INIT_FILE : STRING := "UNUSED";
WIDTH : INTEGER := 16;
ADDRESS_WIDTH : INTEGER := 16;
DELAY_SLOTS : INTEGER := 0
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
ena : IN STD_LOGIC := '1';
addr : IN STD_LOGIC_VECTOR( ADDRESS_WIDTH-1 DOWNTO 0) := (others=>'0');
addr_en : IN STD_LOGIC := '0';
rdata : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0);
wdata : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
wdata_en : IN STD_LOGIC := '0'
);
END COMPONENT;
COMPONENT tta_x_smem_av IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
INIT_FILE : STRING := "UNUSED";
WIDTH : INTEGER := 16;
ADDRESS_WIDTH : INTEGER := 16;
DEPTH : INTEGER := -1;
DELAY_SLOTS : INTEGER := 0;
MODE : INTEGER := ALT_MEM_MODE_AUTO;
ASYNC : INTEGER := 0
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
ena : IN STD_LOGIC := '1';
addr : IN STD_LOGIC_VECTOR( ADDRESS_WIDTH-1 DOWNTO 0) := (others=>'0');
addr_en : IN STD_LOGIC := '0';
rdata : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0);
wdata : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
wdata_en : IN STD_LOGIC := '0';
av_address : IN STD_LOGIC_VECTOR( ADDRESS_WIDTH-1 DOWNTO 0) := (others=>'0');
av_writedata : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
av_readdata : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0);
av_clock : IN STD_LOGIC := '0';
av_write : IN STD_LOGIC := '0';
av_chipselect: IN STD_LOGIC := '0';
av_reset : IN STD_LOGIC := '0';
av_waitrequest : OUT STD_LOGIC := '0';
test_writetog : OUT STD_LOGIC;
test_writeack : IN STD_LOGIC := '0'
);
END COMPONENT;
COMPONENT tta_x_smem_av_db IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
INIT_FILE : STRING := "UNUSED";
WIDTH : INTEGER := 16;
ADDRESS_WIDTH : INTEGER := 16;
DELAY_SLOTS : INTEGER := 0
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
ena : IN STD_LOGIC := '1';
addr : IN STD_LOGIC_VECTOR( ADDRESS_WIDTH-1 DOWNTO 0) := (others=>'0');
addr_en : IN STD_LOGIC := '0';
rdata : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0);
wdata : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
wdata_en : IN STD_LOGIC := '0';
setHalf : IN STD_LOGIC := '0';
setHalf_en : IN STD_LOGIC := '0';
getHalf : OUT STD_LOGIC ;
machineHalf : OUT STD_LOGIC := '0';
av_address : IN STD_LOGIC_VECTOR( ADDRESS_WIDTH DOWNTO 0) := (others=>'0');
av_writedata : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
av_readdata : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0);
av_clock : IN STD_LOGIC := '0';
av_write : IN STD_LOGIC := '0';
av_chipselect: IN STD_LOGIC := '0';
av_reset : IN STD_LOGIC := '0'
);
END COMPONENT;
COMPONENT tta_x_wire IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
WIDTH : INTEGER := 16
);
PORT (
d : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
q : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_addsubcarry IS
GENERIC (
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
L : INTEGER
);
PORT (
clk, reset : IN STD_LOGIC;
ena : IN STD_LOGIC := '1';
sreset : IN STD_LOGIC := '0';
sload : IN STD_LOGIC;
loadval_in : IN UNSIGNED(L-1 DOWNTO 0);
doAddnSub : IN STD_LOGIC := '1';
addL_in : IN UNSIGNED(L-1 DOWNTO 0);
addR_in : IN UNSIGNED(L-1 DOWNTO 0);
sum_out : OUT UNSIGNED(L-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_atlantic_reporter IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
ISSIGNED : INTEGER := 1;
CONSTANT WIDTH : INTEGER := 16
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
data : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
valid : IN STD_LOGIC := '1';
ready : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_au IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
WIDTH : INTEGER := 16;
LATENCY : INTEGER := 1
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
ena : IN STD_LOGIC := '1';
a : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
b : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
l : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
q : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0);
enable : IN STD_LOGIC := '0';
enable_en : IN STD_LOGIC := '0';
sclr : IN STD_LOGIC := '0';
sload : IN STD_LOGIC := '0';
subNadd : IN STD_LOGIC := '0'
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_avalon_mm_bursting_master_fifo IS
generic (
NAME : string := "";
OPTIMIZED : integer := OPTIMIZED_ON;
FAMILY : integer := FAMILY_STRATIX;
ADDR_WIDTH : integer := 16;
DATA_WIDTH : integer := 16;
READ_USED : integer := 1;
WRITE_USED : integer := 1;
CMD_FIFO_DEPTH : integer := 8;
RDATA_FIFO_DEPTH : integer := 8;
WDATA_FIFO_DEPTH : integer := 8;
WDATA_TARGET_BURST_SIZE : integer := 5;
RDATA_TARGET_BURST_SIZE : integer := 5;
CLOCKS_ARE_SYNC : integer := 1;
ADDRESS_GROUP : integer := 1;
BYTEENABLE_USED : integer := 1;
LEN_BE_WIDTH : integer := 11;
BURST_WIDTH : integer := 6;
INTERRUPT_USED : INTEGER := 1;
INTERRUPT_WIDTH : INTEGER := 8
);
port (
clock : in std_logic;
reset : in std_logic;
ena : in std_logic := '1';
ready : out std_logic;
stall : out std_logic;
addr : in std_logic_vector(ADDR_WIDTH-1 downto 0) := (others => '0');
write : in std_logic := '0';
burst : in std_logic := '0';
len_be : in std_logic_vector(LEN_BE_WIDTH-1 downto 0) := (others => '0');
cenable : in std_logic;
cenable_en : in std_logic;
wdata : in std_logic_vector(DATA_WIDTH-1 downto 0) := (others => '0');
wenable : in std_logic;
wenable_en : in std_logic := '0';
rdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
renable : in std_logic := '0';
renable_en : in std_logic := '0';
activeirqs : out std_logic_vector(INTERRUPT_WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
av_address : out std_logic_vector(ADDR_WIDTH-1 downto 0);
av_burstcount : out std_logic_vector(BURST_WIDTH-1 downto 0);
av_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0);
av_byteenable : out std_logic_vector((DATA_WIDTH/8)-1 downto 0);
av_write : out std_logic;
av_read : out std_logic;
av_clock : in std_logic;
av_reset : in std_logic := '0';
av_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0) := (others => '0');
av_readdatavalid : in std_logic := '0';
av_waitrequest : in std_logic := '0';
av_interrupt : in std_logic_vector(INTERRUPT_WIDTH-1 DOWNTO 0) := (OTHERS=>'0')
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_avalon_mm_raw_slave IS
GENERIC (
NAME : STRING := "";
WIDTH : INTEGER := 16;
ADDRESS_WIDTH : INTEGER := 16;
READ_USED : INTEGER := 1;
WRITE_USED : INTEGER := 1;
INTERRUPT_USED : INTEGER := 1;
CLOCKS_ARE_SYNC : INTEGER := 1
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
ena : IN STD_LOGIC := '1';
stall : OUT STD_LOGIC;
waitaccess : IN STD_LOGIC := '0';
waitaccess_en: IN STD_LOGIC := '0';
finish : IN STD_LOGIC := '0';
finish_en : IN STD_LOGIC := '0';
hasaccess : OUT STD_LOGIC;
isread : OUT STD_LOGIC;
address : OUT STD_LOGIC_VECTOR( ADDRESS_WIDTH-1 DOWNTO 0);
wdata : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0);
rdata : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
setirq : IN STD_LOGIC := '0';
setirq_en : IN STD_LOGIC := '0';
setirq_ena : IN STD_LOGIC := '1';
av_address : IN STD_LOGIC_VECTOR( ADDRESS_WIDTH-1 DOWNTO 0) := (others=>'0');
av_writedata : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
av_readdata : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0);
av_clock : IN STD_LOGIC := '0';
av_write : IN STD_LOGIC := '0';
av_chipselect: IN STD_LOGIC := '0';
av_reset : IN STD_LOGIC := '0';
av_waitrequest : OUT STD_LOGIC := '0';
av_interrupt : OUT STD_LOGIC := '0'
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_clock_reset IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
PERIOD : TIME := 10 ns
);
PORT (
clock : OUT STD_LOGIC;
reset : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_cmp IS
GENERIC (
NAME : STRING := "";
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
WIDTH : INTEGER := 16
);
PORT (
a : IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0) := (others=>'0');
b : IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0) := (others=>'0');
sign : IN STD_LOGIC :='0';
equals : IN STD_LOGIC := '1';
less : IN STD_LOGIC := '0';
invert : IN STD_LOGIC := '0';
q : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_debug IS
GENERIC (
NAME : STRING := "";
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
WIDTH : INTEGER := 16;
LATENCY : INTEGER := 1;
RESTART : INTEGER := 1
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
ena : IN STD_LOGIC := '1';
a : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
a_en : IN STD_LOGIC := '0';
b : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0')
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_exit IS
GENERIC (
NAME : STRING := "";
WIDTH : INTEGER := 16
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
ena : IN STD_LOGIC := '1';
return_code : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
return_code_en : IN STD_LOGIC := '0';
test_stopped : OUT STD_LOGIC;
test_return_code : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_fifo IS
generic (
NAME : string := "";
OPTIMIZED : integer := OPTIMIZED_ON;
FAMILY : integer := FAMILY_STRATIX;
WIDTH : integer := 16;
READ_TRIGGER_TO_READ_DATA_CHANGE_CYCLES : integer := 2;
DEPTH : integer := 16
);
port (
clock : in std_logic;
reset : in std_logic := '0';
ena_read : in std_logic := '1';
stall_read : out std_logic := '0';
readnext : in std_logic := '0';
readnext_en : in std_logic := '0';
rdata : out std_logic_vector(width - 1 downto 0);
ena_write : in std_logic := '1';
stall_write : out std_logic := '0';
writenext : in std_logic := '0';
writenext_en : in std_logic := '0';
wdata : in std_logic_vector(width - 1 downto 0) := (others => '0');
dataavail : out std_logic;
spaceavail : out std_logic
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_fifo_paged IS
GENERIC (
NAME : STRING := "";
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
WIDTH : INTEGER := 16;
ADDRESS_WIDTH : INTEGER := 8;
PAGE_SIZE : INTEGER := 8;
PAGES : INTEGER := 4;
LOG2_PAGES : INTEGER := 2;
FULL_BIDIR : INTEGER := 1;
SINK_ACTIVE_PAGES : INTEGER := 1;
SOURCE_ACTIVE_PAGES : INTEGER := 1;
FULL_AT_START : INTEGER := 0
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
a_ena : IN STD_LOGIC := '1';
a_addr : IN STD_LOGIC_VECTOR( ADDRESS_WIDTH-1 DOWNTO 0) := (others=>'0');
a_rdata : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0);
a_wdata : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
a_wdataen : IN STD_LOGIC := '0';
a_wdataen_en : IN STD_LOGIC := '0';
a_takeb : IN STD_LOGIC := '0';
a_takeb_en : IN STD_LOGIC := '0';
a_takenb : IN STD_LOGIC := '0';
a_takenb_en : IN STD_LOGIC := '0';
a_returnnb : IN STD_LOGIC := '0';
a_returnnb_en : IN STD_LOGIC := '0';
a_pagesel : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others=>'0');
a_pagesel_en : IN STD_LOGIC := '0';
a_page_to_take : OUT STD_LOGIC;
a_stall : OUT STD_LOGIC;
b_ena : IN STD_LOGIC := '1';
b_addr : IN STD_LOGIC_VECTOR( ADDRESS_WIDTH-1 DOWNTO 0) := (others=>'0');
b_rdata : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0);
b_wdata : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
b_wdataen : IN STD_LOGIC := '0';
b_wdataen_en : IN STD_LOGIC := '0';
b_takeb : IN STD_LOGIC := '0';
b_takeb_en : IN STD_LOGIC := '0';
b_takenb : IN STD_LOGIC := '0';
b_takenb_en : IN STD_LOGIC := '0';
b_returnnb : IN STD_LOGIC := '0';
b_returnnb_en : IN STD_LOGIC := '0';
b_pagesel : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others=>'0');
b_pagesel_en : IN STD_LOGIC := '0';
b_page_to_take : OUT STD_LOGIC;
b_stall : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_fifo_usedw_calculator IS
generic
(
WIDTH : integer := 8;
DEPTH : integer := 9;
READ_TO_WRITE_DELAY : integer := 3;
WRITE_TO_READ_DELAY : integer := 3;
CLOCKS_ARE_SAME : boolean := TRUE
);
port
(
rdclock : in std_logic;
rdena : in std_logic;
wrclock : in std_logic;
wrena : in std_logic;
reset : in std_logic;
wrreq : in std_logic;
rdreq : in std_logic;
wrusedw : out std_logic_vector(wide_enough_for(DEPTH) - 1 downto 0);
full : out std_logic;
almost_full : out std_logic;
rdusedw : out std_logic_vector(wide_enough_for(DEPTH) - 1 downto 0);
empty : out std_logic;
almost_empty : out std_logic
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_fp_addsub_dp_l7 IS
PORT
(
add_sub : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
clk_en : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
overflow : OUT STD_LOGIC ;
nan : OUT STD_LOGIC ;
underflow : OUT STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_fp_addsub_dp_l8 IS
PORT
(
add_sub : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
clk_en : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
overflow : OUT STD_LOGIC ;
nan : OUT STD_LOGIC ;
underflow : OUT STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_fp_addsub_sp_l7 IS
PORT
(
add_sub : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
clk_en : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
overflow : OUT STD_LOGIC ;
nan : OUT STD_LOGIC ;
underflow : OUT STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_fp_addsub_sp_l8 IS
PORT
(
add_sub : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
clk_en : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
overflow : OUT STD_LOGIC ;
nan : OUT STD_LOGIC ;
underflow : OUT STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_fp_au IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
WIDTH : INTEGER := 32;
LATENCY : INTEGER := 5
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
ena : IN STD_LOGIC := '1';
enable : IN STD_LOGIC := '0';
enable_en : IN STD_LOGIC := '0';
subNadd : IN STD_LOGIC := '0';
a : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
b : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
q : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_fp_cmp IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
LATENCY : INTEGER := 7;
WIDTH : INTEGER := 32
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
ena : IN STD_LOGIC := '1';
a : IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0) := (others=>'0');
a_en : IN STD_LOGIC;
b : IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0) := (others=>'0');
sel : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
q : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_fp_mult IS
GENERIC (
NAME : STRING := "";
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
WIDTH : INTEGER := 32;
LATENCY : INTEGER := 5;
RESTART : INTEGER := 1
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
ena : IN STD_LOGIC := '1';
a : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
a_en : IN STD_LOGIC := '0';
b : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
q : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_general_fifo IS
generic
(
WIDTH : integer := 8;
DEPTH : integer := 4;
CLOCKS_ARE_SAME : boolean := TRUE;
DEVICE_FAMILY : string;
RDREQ_TO_Q_LATENCY : integer := 1
);
port
(
rdclock : in std_logic;
rdena : in std_logic;
wrclock : in std_logic;
wrena : in std_logic;
reset : in std_logic;
wrusedw : out std_logic_vector(wide_enough_for(DEPTH) - 1 downto 0);
full : out std_logic;
almost_full : out std_logic;
rdusedw : out std_logic_vector(wide_enough_for(DEPTH) - 1 downto 0);
empty : out std_logic;
almost_empty : out std_logic;
wrreq : in std_logic;
data : in std_logic_vector(WIDTH - 1 downto 0);
rdreq : in std_logic;
q : out std_logic_vector(WIDTH - 1 downto 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_gpi IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
DATATYPE : STRING := "";
MODE : STRING := "REGISTERED";
WIDTH : INTEGER := 16
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
ena : IN STD_LOGIC := '1';
gpio_in : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
q : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0);
q_en: IN STD_LOGIC := '0';
wait_change: IN STD_LOGIC := '0';
wait_change_en: IN STD_LOGIC := '0';
stall : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_gpio IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
DATATYPE : STRING := "";
MODE : STRING := "REGISTERED";
WIDTH : INTEGER := 16
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
ena : IN STD_LOGIC := '1';
enable : IN STD_LOGIC := '1';
enable_en : IN STD_LOGIC := '1';
d : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
q : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0);
q_en: IN STD_LOGIC := '0';
wait_change: IN STD_LOGIC := '0';
wait_change_en: IN STD_LOGIC := '0';
stall : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_gpo IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
DATATYPE : STRING := "";
MODE : STRING := "REGISTERED";
WIDTH : INTEGER := 16
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
ena : IN STD_LOGIC := '1';
enable : IN STD_LOGIC := '1';
enable_en : IN STD_LOGIC := '1';
d : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
gpio_out : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_gray_clock_crosser IS
generic
(
WIDTH : integer := 8
);
port
(
inclock : in std_logic;
outclock : in std_logic;
inena : in std_logic;
outena : in std_logic;
reset : in std_logic;
data : in std_logic_vector(WIDTH - 1 downto 0);
q : out std_logic_vector(WIDTH - 1 downto 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_logic_fifo IS
generic
(
WIDTH : integer := 8;
DEPTH : integer := 3
);
port
(
clock : in std_logic;
rdena : in std_logic := '1';
wrena : in std_logic := '1';
reset : in std_logic;
wrusedw : out std_logic_vector(wide_enough_for(DEPTH) - 1 downto 0);
full : out std_logic;
almost_full : out std_logic;
rdusedw : out std_logic_vector(wide_enough_for(DEPTH) - 1 downto 0);
empty : out std_logic;
almost_empty : out std_logic;
wrreq : in std_logic;
data : in std_logic_vector(WIDTH - 1 downto 0);
rdreq : in std_logic;
q : out std_logic_vector(WIDTH - 1 downto 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_lu IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
WIDTH : INTEGER := 16
);
PORT (
a : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
b : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
andNor : IN STD_LOGIC := '0';
invert : IN STD_LOGIC := '0';
q : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_lu_wire IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
WIDTH : INTEGER := 16
);
PORT (
a : IN STD_LOGIC := '0';
b : IN STD_LOGIC := '0';
andNor : IN STD_LOGIC := '0';
invert : IN STD_LOGIC := '0';
q : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_mac IS
GENERIC (
NAME : STRinG := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
WIDTH : INTEGER := 16;
WIDTHOUT : INTEGER := 32;
LATENCY : INTEGER := 3
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
ena : IN STD_LOGIC := '1';
a : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
a_en : IN STD_LOGIC := '1';
b : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
signa : IN STD_LOGIC := '0';
signb : IN STD_LOGIC := '0';
mulNmac : IN STD_LOGIC := '0';
q : OUT STD_LOGIC_VECTOR( WIDTHOUT-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_mem IS
GENERIC (
NAME : STRING := "";
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
INIT_FILE : STRING := "UNUSED";
INIT_CONTENTS : STRING := "UNUSED";
DATA_WIDTH : INTEGER := 16;
ADDRESS_WIDTH : INTEGER := 16;
DEPTH : INTEGER := 16;
LATENCY : INTEGER := 2;
READ_PORTS : INTEGER := 0;
WRITE_PORTS : INTEGER := 0;
READ_WRITE_PORTS : INTEGER := 2;
MODE : INTEGER := ALT_MEM_MODE_AUTO;
ALLOW_MULTI_THREAD : INTEGER := 0
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
Aena : IN STD_LOGIC := '1';
Bena : IN STD_LOGIC := '0';
Cena : IN STD_LOGIC := '0';
Aenable : IN STD_LOGIC := '0';
Aenable_en : IN STD_LOGIC := '0';
Aaddr : IN STD_LOGIC_VECTOR( ADDRESS_WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
Awdata : IN STD_LOGIC_VECTOR( DATA_WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
Awdata_en : IN STD_LOGIC := '0';
Ardata : OUT STD_LOGIC_VECTOR( DATA_WIDTH-1 DOWNTO 0);
Benable : IN STD_LOGIC := '0';
Benable_en : IN STD_LOGIC := '0';
Baddr : IN STD_LOGIC_VECTOR( ADDRESS_WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
Bwdata : IN STD_LOGIC_VECTOR( DATA_WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
Bwdata_en : IN STD_LOGIC := '0';
Brdata : OUT STD_LOGIC_VECTOR( DATA_WIDTH-1 DOWNTO 0);
Cenable : IN STD_LOGIC := '0';
Cenable_en : IN STD_LOGIC := '0';
Caddr : IN STD_LOGIC_VECTOR( ADDRESS_WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
Crdata : OUT STD_LOGIC_VECTOR( DATA_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_mult IS
GENERIC (
NAME : STRinG := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
WIDTH : INTEGER := 16;
WIDTHX2 : INTEGER := 32;
LATENCY : INTEGER := 2;
RESTART : INTEGER := 1
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
ena : IN STD_LOGIC := '1';
a : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
a_en : IN STD_LOGIC := '1';
b : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
signa : IN STD_LOGIC := '0';
signb : IN STD_LOGIC := '0';
q : OUT STD_LOGIC_VECTOR( WIDTHx2-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_multadd IS
GENERIC (
NAME : STRinG := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIXII;
WIDTH : INTEGER := 16;
WIDTHOUT : INTEGER := 33;
LATENCY : INTEGER := 3;
RESTART : INTEGER := 1
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
ena : IN STD_LOGIC := '1';
a : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
a_en : IN STD_LOGIC := '1';
b : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
c : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
d : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
signa : IN STD_LOGIC := '0';
signb : IN STD_LOGIC := '0';
signc : IN STD_LOGIC := '0';
signd : IN STD_LOGIC := '0';
q : OUT STD_LOGIC_VECTOR( WIDTHOUT-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_mux2 IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
WIDTH : INTEGER := 16
);
PORT (
sel : IN STD_LOGIC := '0';
data0 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data1 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
q : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_mux2_wire IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
CONSTANT PORTS : INTEGER := 2
);
PORT (
sel : IN STD_LOGIC;
data : IN STD_LOGIC_VECTOR( PORTS-1 DOWNTO 0):= (others => '0');
q : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_mux3 IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
WIDTH : INTEGER := 16
);
PORT (
sel : IN STD_LOGIC_VECTOR( 2 DOWNTO 0) := (others=>'0');
data0 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data1 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data2 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
q : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_mux4 IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
WIDTH : INTEGER := 16
);
PORT (
sel : IN STD_LOGIC_VECTOR( 3 DOWNTO 0) := (others=>'0');
data0 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data1 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data2 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data3 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
q : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_mux5 IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
WIDTH : INTEGER := 16
);
PORT (
sel : IN STD_LOGIC_VECTOR( 4 DOWNTO 0) := (others=>'0');
data0 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data1 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data2 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data3 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data4 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
q : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_mux_wire IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
PORTS : INTEGER := 16
);
PORT (
sel : IN STD_LOGIC_VECTOR( PORTS-1 DOWNTO 0):= (others => '0');
data : IN STD_LOGIC_VECTOR( PORTS-1 DOWNTO 0):= (others => '0');
q : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_mux_x20 IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
PORTS : INTEGER := 21;
WIDTH : INTEGER := 16
);
PORT (
sel : IN STD_LOGIC_VECTOR( PORTS-1 DOWNTO 0) := (others=>'0');
data0 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data1 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data2 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data3 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data4 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data5 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data6 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data7 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data8 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data9 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data10 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data11 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data12 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data13 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data14 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data15 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data16 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data17 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data18 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data19 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data20 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
q : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_mux_x40 IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
PORTS : INTEGER := 41;
WIDTH : INTEGER := 16
);
PORT (
sel : IN STD_LOGIC_VECTOR( PORTS-1 DOWNTO 0) := (others=>'0');
data0 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data1 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data2 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data3 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data4 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data5 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data6 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data7 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data8 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data9 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data10 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data11 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data12 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data13 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data14 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data15 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data16 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data17 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data18 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data19 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data20 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data21 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data22 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data23 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data24 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data25 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data26 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data27 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data28 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data29 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data30 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data31 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data32 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data33 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data34 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data35 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data36 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data37 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data38 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data39 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data40 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
q : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_mux_x80 IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
PORTS : INTEGER := 81;
WIDTH : INTEGER := 16
);
PORT (
sel : IN STD_LOGIC_VECTOR( PORTS-1 DOWNTO 0) := (others=>'0');
data0 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data1 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data2 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data3 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data4 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data5 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data6 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data7 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data8 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data9 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data10 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data11 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data12 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data13 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data14 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data15 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data16 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data17 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data18 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data19 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data20 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data21 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data22 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data23 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data24 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data25 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data26 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data27 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data28 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data29 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data30 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data31 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data32 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data33 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data34 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data35 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data36 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data37 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data38 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data39 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data40 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data41 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data42 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data43 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data44 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data45 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data46 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data47 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data48 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data49 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data50 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data51 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data52 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data53 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data54 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data55 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data56 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data57 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data58 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data59 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data60 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data61 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data62 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data63 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data64 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data65 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data66 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data67 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data68 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data69 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data70 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data71 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data72 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data73 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data74 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data75 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data76 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data77 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data78 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data79 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data80 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
data81 : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0');
q : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_muxfast4 IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
PORTS : INTEGER := 4;
WIDTH : INTEGER := 16
);
PORT (
sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
data0 : IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0) := (others=>'0');
data1 : IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0) := (others=>'0');
data2 : IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0) := (others=>'0');
data3 : IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0) := (others=>'0');
q : OUT STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_muxfast8 IS
GENERIC (
NAME : STRING := "";
SIMULATION : INTEGER := SIMULATION_OFF;
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
PORTS : INTEGER := 8;
WIDTH : INTEGER := 16
);
PORT (
sel : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
data0 : IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0) := (others=>'0');
data1 : IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0) := (others=>'0');
data2 : IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0) := (others=>'0');
data3 : IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0) := (others=>'0');
data4 : IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0) := (others=>'0');
data5 : IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0) := (others=>'0');
data6 : IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0) := (others=>'0');
data7 : IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0) := (others=>'0');
q : OUT STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_one_bit_delay IS
generic
(
DELAY : integer := 0
);
port
(
clock : in std_logic;
reset : in std_logic;
ena : in std_logic := '1';
data : in std_logic;
q : out std_logic
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_pc IS
GENERIC (
NAME : STRING := "";
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
PROGRAM_FILE : STRING := "";
PROGRAM_TRACE: STRING := "program.trace";
LATENCY : INTEGER := 3;
DECODE_LATENCY : INTEGER := 2;
INFER_MEMORY : INTEGER := 0;
PC_WIDTH : INTEGER := 16;
PC_NUM_WORDS : INTEGER := 256;
PCW_WIDTH : INTEGER := 32
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
ena : IN STD_LOGIC := '1';
pcw : OUT STD_LOGIC_VECTOR( PCW_WIDTH-1 DOWNTO 0);
pc : OUT STD_LOGIC_VECTOR( PC_WIDTH-1 DOWNTO 0);
pcf : OUT STD_LOGIC_VECTOR( PC_WIDTH-1 DOWNTO 0);
step : OUT STD_LOGIC;
stallnext : OUT STD_LOGIC;
nextpc : IN STD_LOGIC_VECTOR( PC_WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
usenextpc : IN STD_LOGIC := '0';
usenextpc_en : IN STD_LOGIC := '0';
hold : IN STD_LOGIC := '0';
hold_en : IN STD_LOGIC := '0'
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_pulling_width_adapter IS
generic (
NAME : string := "";
OPTIMIZED : integer := OPTIMIZED_ON;
FAMILY : integer := FAMILY_STRATIX;
IN_WIDTH : integer := 16;
OUT_WIDTH : integer := 16
);
port (
clock : in std_logic;
reset : in std_logic;
ena : in std_logic := '1';
input : in std_logic_vector(IN_WIDTH - 1 downto 0) := (others => '0');
need_input : out std_logic;
output : out std_logic_vector(OUT_WIDTH - 1 downto 0) := (others => '0');
pull : in std_logic;
pull_en : in std_logic;
discard : in std_logic;
discard_en : in std_logic
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_pushing_width_adapter IS
generic (
NAME : string := "";
OPTIMIZED : integer := OPTIMIZED_ON;
FAMILY : integer := FAMILY_STRATIX;
IN_WIDTH : integer := 16;
OUT_WIDTH : integer := 16
);
port (
clock : in std_logic;
reset : in std_logic;
ena : in std_logic := '1';
input : in std_logic_vector(IN_WIDTH - 1 downto 0) := (others => '0');
push : in std_logic;
push_en : in std_logic;
flush : in std_logic;
flush_en : in std_logic;
output : out std_logic_vector(OUT_WIDTH - 1 downto 0) := (others => '0');
output_valid : out std_logic
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_ram_fifo IS
generic
(
WIDTH : integer := 8;
DEPTH : integer := 3;
CLOCKS_ARE_SAME : boolean := TRUE;
DEVICE_FAMILY : string
);
port
(
rdclock : in std_logic;
rdena : in std_logic;
wrclock : in std_logic;
wrena : in std_logic;
reset : in std_logic;
wrusedw : out std_logic_vector(wide_enough_for(DEPTH) - 1 downto 0);
full : out std_logic;
almost_full : out std_logic;
rdusedw : out std_logic_vector(wide_enough_for(DEPTH) - 1 downto 0);
empty : out std_logic;
almost_empty : out std_logic;
wrreq : in std_logic;
data : in std_logic_vector(WIDTH - 1 downto 0);
rdreq : in std_logic;
q : out std_logic_vector(WIDTH - 1 downto 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_reg IS
GENERIC (
NAME : STRING := "";
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
WIDTH : INTEGER := 16;
RESET_VALUE : INTEGER := 0
);
PORT (
clock : IN STD_LOGIC;
ena : IN STD_LOGIC := '1';
enable : IN STD_LOGIC := '0';
enable_en : IN STD_LOGIC := '0';
reset : IN STD_LOGIC := '0';
sclr : IN STD_LOGIC := '0';
d : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
q : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_shift IS
GENERIC (
NAME : STRING := "";
OPTIMIZED : INTEGER := OPTIMIZED_ON;
FAMILY : INTEGER := FAMILY_STRATIX;
DATA_WIDTH : POSITIVE := 16;
SHIFT_WIDTH : POSITIVE := 4;
LATENCY : INTEGER := 0;
MODE : INTEGER := ALT_SHIFT_MODE_LOGICAL;
DIRECTION : INTEGER := ALT_SHIFT_DIREC_RIGHT
);
PORT (
clock : IN STD_LOGIC := '0';
ena : IN STD_LOGIC := '0';
reset : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
data_en : IN STD_LOGIC := '1';
shift : IN STD_LOGIC_VECTOR(SHIFT_WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
direc : IN STD_LOGIC := '0';
result : OUT STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_std_logic_vector_delay IS
generic
(
WIDTH : integer := 1;
DELAY : integer := 0
);
port
(
clock : in std_logic;
reset : in std_logic;
ena : in std_logic := '1';
data : in std_logic_vector(WIDTH - 1 downto 0);
q : out std_logic_vector(WIDTH - 1 downto 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_muxbin2_wire IS
generic (
NAME : string := "";
PORTS : integer := 2;
WIDTH : integer := 1
);
port (
sel : in std_logic := '0';
data0 : in std_logic := '0';
data1 : in std_logic := '0';
q : out std_logic
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_muxbin2 IS
generic (
NAME : string := "";
PORTS : integer := 2;
WIDTH : integer := 16
);
port (
sel : in std_logic := '0';
data0 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data1 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
q : out std_logic_vector(WIDTH-1 downto 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_muxbin4_wire IS
generic (
NAME : string := "";
PORTS : integer := 4;
WIDTH : integer := 1
);
port (
sel : in std_logic_vector(1 downto 0) := (others => '0');
data0 : in std_logic := '0';
data1 : in std_logic := '0';
data2 : in std_logic := '0';
data3 : in std_logic := '0';
q : out std_logic
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_muxbin4 IS
generic (
NAME : string := "";
PORTS : integer := 4;
WIDTH : integer := 16
);
port (
sel : in std_logic_vector(1 downto 0) := (others => '0');
data0 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data1 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data2 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data3 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
q : out std_logic_vector(WIDTH-1 downto 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_muxbin8_wire IS
generic (
NAME : string := "";
PORTS : integer := 8;
WIDTH : integer := 1
);
port (
sel : in std_logic_vector(2 downto 0) := (others => '0');
data0 : in std_logic := '0';
data1 : in std_logic := '0';
data2 : in std_logic := '0';
data3 : in std_logic := '0';
data4 : in std_logic := '0';
data5 : in std_logic := '0';
data6 : in std_logic := '0';
data7 : in std_logic := '0';
q : out std_logic
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_muxbin8 IS
generic (
NAME : string := "";
PORTS : integer := 8;
WIDTH : integer := 16
);
port (
sel : in std_logic_vector(2 downto 0) := (others => '0');
data0 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data1 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data2 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data3 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data4 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data5 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data6 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data7 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
q : out std_logic_vector(WIDTH-1 downto 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_muxbin16_wire IS
generic (
NAME : string := "";
PORTS : integer := 16;
WIDTH : integer := 1
);
port (
sel : in std_logic_vector(3 downto 0) := (others => '0');
data0 : in std_logic := '0';
data1 : in std_logic := '0';
data2 : in std_logic := '0';
data3 : in std_logic := '0';
data4 : in std_logic := '0';
data5 : in std_logic := '0';
data6 : in std_logic := '0';
data7 : in std_logic := '0';
data8 : in std_logic := '0';
data9 : in std_logic := '0';
data10 : in std_logic := '0';
data11 : in std_logic := '0';
data12 : in std_logic := '0';
data13 : in std_logic := '0';
data14 : in std_logic := '0';
data15 : in std_logic := '0';
q : out std_logic
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_muxbin16 IS
generic (
NAME : string := "";
PORTS : integer := 16;
WIDTH : integer := 16
);
port (
sel : in std_logic_vector(3 downto 0) := (others => '0');
data0 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data1 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data2 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data3 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data4 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data5 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data6 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data7 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data8 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data9 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data10 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data11 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data12 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data13 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data14 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data15 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
q : out std_logic_vector(WIDTH-1 downto 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_muxbin32_wire IS
generic (
NAME : string := "";
PORTS : integer := 32;
WIDTH : integer := 1
);
port (
sel : in std_logic_vector(4 downto 0) := (others => '0');
data0 : in std_logic := '0';
data1 : in std_logic := '0';
data2 : in std_logic := '0';
data3 : in std_logic := '0';
data4 : in std_logic := '0';
data5 : in std_logic := '0';
data6 : in std_logic := '0';
data7 : in std_logic := '0';
data8 : in std_logic := '0';
data9 : in std_logic := '0';
data10 : in std_logic := '0';
data11 : in std_logic := '0';
data12 : in std_logic := '0';
data13 : in std_logic := '0';
data14 : in std_logic := '0';
data15 : in std_logic := '0';
data16 : in std_logic := '0';
data17 : in std_logic := '0';
data18 : in std_logic := '0';
data19 : in std_logic := '0';
data20 : in std_logic := '0';
data21 : in std_logic := '0';
data22 : in std_logic := '0';
data23 : in std_logic := '0';
data24 : in std_logic := '0';
data25 : in std_logic := '0';
data26 : in std_logic := '0';
data27 : in std_logic := '0';
data28 : in std_logic := '0';
data29 : in std_logic := '0';
data30 : in std_logic := '0';
data31 : in std_logic := '0';
q : out std_logic
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_muxbin32 IS
generic (
NAME : string := "";
PORTS : integer := 32;
WIDTH : integer := 16
);
port (
sel : in std_logic_vector(4 downto 0) := (others => '0');
data0 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data1 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data2 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data3 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data4 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data5 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data6 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data7 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data8 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data9 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data10 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data11 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data12 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data13 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data14 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data15 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data16 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data17 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data18 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data19 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data20 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data21 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data22 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data23 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data24 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data25 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data26 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data27 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data28 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data29 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data30 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data31 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
q : out std_logic_vector(WIDTH-1 downto 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_muxbin64_wire IS
generic (
NAME : string := "";
PORTS : integer := 64;
WIDTH : integer := 1
);
port (
sel : in std_logic_vector(5 downto 0) := (others => '0');
data0 : in std_logic := '0';
data1 : in std_logic := '0';
data2 : in std_logic := '0';
data3 : in std_logic := '0';
data4 : in std_logic := '0';
data5 : in std_logic := '0';
data6 : in std_logic := '0';
data7 : in std_logic := '0';
data8 : in std_logic := '0';
data9 : in std_logic := '0';
data10 : in std_logic := '0';
data11 : in std_logic := '0';
data12 : in std_logic := '0';
data13 : in std_logic := '0';
data14 : in std_logic := '0';
data15 : in std_logic := '0';
data16 : in std_logic := '0';
data17 : in std_logic := '0';
data18 : in std_logic := '0';
data19 : in std_logic := '0';
data20 : in std_logic := '0';
data21 : in std_logic := '0';
data22 : in std_logic := '0';
data23 : in std_logic := '0';
data24 : in std_logic := '0';
data25 : in std_logic := '0';
data26 : in std_logic := '0';
data27 : in std_logic := '0';
data28 : in std_logic := '0';
data29 : in std_logic := '0';
data30 : in std_logic := '0';
data31 : in std_logic := '0';
data32 : in std_logic := '0';
data33 : in std_logic := '0';
data34 : in std_logic := '0';
data35 : in std_logic := '0';
data36 : in std_logic := '0';
data37 : in std_logic := '0';
data38 : in std_logic := '0';
data39 : in std_logic := '0';
data40 : in std_logic := '0';
data41 : in std_logic := '0';
data42 : in std_logic := '0';
data43 : in std_logic := '0';
data44 : in std_logic := '0';
data45 : in std_logic := '0';
data46 : in std_logic := '0';
data47 : in std_logic := '0';
data48 : in std_logic := '0';
data49 : in std_logic := '0';
data50 : in std_logic := '0';
data51 : in std_logic := '0';
data52 : in std_logic := '0';
data53 : in std_logic := '0';
data54 : in std_logic := '0';
data55 : in std_logic := '0';
data56 : in std_logic := '0';
data57 : in std_logic := '0';
data58 : in std_logic := '0';
data59 : in std_logic := '0';
data60 : in std_logic := '0';
data61 : in std_logic := '0';
data62 : in std_logic := '0';
data63 : in std_logic := '0';
q : out std_logic
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_muxbin64 IS
generic (
NAME : string := "";
PORTS : integer := 64;
WIDTH : integer := 16
);
port (
sel : in std_logic_vector(5 downto 0) := (others => '0');
data0 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data1 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data2 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data3 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data4 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data5 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data6 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data7 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data8 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data9 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data10 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data11 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data12 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data13 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data14 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data15 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data16 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data17 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data18 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data19 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data20 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data21 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data22 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data23 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data24 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data25 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data26 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data27 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data28 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data29 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data30 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data31 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data32 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data33 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data34 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data35 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data36 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data37 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data38 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data39 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data40 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data41 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data42 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data43 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data44 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data45 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data46 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data47 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data48 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data49 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data50 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data51 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data52 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data53 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data54 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data55 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data56 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data57 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data58 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data59 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data60 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data61 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data62 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data63 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
q : out std_logic_vector(WIDTH-1 downto 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_muxbin128_wire IS
generic (
NAME : string := "";
PORTS : integer := 128;
WIDTH : integer := 1
);
port (
sel : in std_logic_vector(6 downto 0) := (others => '0');
data0 : in std_logic := '0';
data1 : in std_logic := '0';
data2 : in std_logic := '0';
data3 : in std_logic := '0';
data4 : in std_logic := '0';
data5 : in std_logic := '0';
data6 : in std_logic := '0';
data7 : in std_logic := '0';
data8 : in std_logic := '0';
data9 : in std_logic := '0';
data10 : in std_logic := '0';
data11 : in std_logic := '0';
data12 : in std_logic := '0';
data13 : in std_logic := '0';
data14 : in std_logic := '0';
data15 : in std_logic := '0';
data16 : in std_logic := '0';
data17 : in std_logic := '0';
data18 : in std_logic := '0';
data19 : in std_logic := '0';
data20 : in std_logic := '0';
data21 : in std_logic := '0';
data22 : in std_logic := '0';
data23 : in std_logic := '0';
data24 : in std_logic := '0';
data25 : in std_logic := '0';
data26 : in std_logic := '0';
data27 : in std_logic := '0';
data28 : in std_logic := '0';
data29 : in std_logic := '0';
data30 : in std_logic := '0';
data31 : in std_logic := '0';
data32 : in std_logic := '0';
data33 : in std_logic := '0';
data34 : in std_logic := '0';
data35 : in std_logic := '0';
data36 : in std_logic := '0';
data37 : in std_logic := '0';
data38 : in std_logic := '0';
data39 : in std_logic := '0';
data40 : in std_logic := '0';
data41 : in std_logic := '0';
data42 : in std_logic := '0';
data43 : in std_logic := '0';
data44 : in std_logic := '0';
data45 : in std_logic := '0';
data46 : in std_logic := '0';
data47 : in std_logic := '0';
data48 : in std_logic := '0';
data49 : in std_logic := '0';
data50 : in std_logic := '0';
data51 : in std_logic := '0';
data52 : in std_logic := '0';
data53 : in std_logic := '0';
data54 : in std_logic := '0';
data55 : in std_logic := '0';
data56 : in std_logic := '0';
data57 : in std_logic := '0';
data58 : in std_logic := '0';
data59 : in std_logic := '0';
data60 : in std_logic := '0';
data61 : in std_logic := '0';
data62 : in std_logic := '0';
data63 : in std_logic := '0';
data64 : in std_logic := '0';
data65 : in std_logic := '0';
data66 : in std_logic := '0';
data67 : in std_logic := '0';
data68 : in std_logic := '0';
data69 : in std_logic := '0';
data70 : in std_logic := '0';
data71 : in std_logic := '0';
data72 : in std_logic := '0';
data73 : in std_logic := '0';
data74 : in std_logic := '0';
data75 : in std_logic := '0';
data76 : in std_logic := '0';
data77 : in std_logic := '0';
data78 : in std_logic := '0';
data79 : in std_logic := '0';
data80 : in std_logic := '0';
data81 : in std_logic := '0';
data82 : in std_logic := '0';
data83 : in std_logic := '0';
data84 : in std_logic := '0';
data85 : in std_logic := '0';
data86 : in std_logic := '0';
data87 : in std_logic := '0';
data88 : in std_logic := '0';
data89 : in std_logic := '0';
data90 : in std_logic := '0';
data91 : in std_logic := '0';
data92 : in std_logic := '0';
data93 : in std_logic := '0';
data94 : in std_logic := '0';
data95 : in std_logic := '0';
data96 : in std_logic := '0';
data97 : in std_logic := '0';
data98 : in std_logic := '0';
data99 : in std_logic := '0';
data100 : in std_logic := '0';
data101 : in std_logic := '0';
data102 : in std_logic := '0';
data103 : in std_logic := '0';
data104 : in std_logic := '0';
data105 : in std_logic := '0';
data106 : in std_logic := '0';
data107 : in std_logic := '0';
data108 : in std_logic := '0';
data109 : in std_logic := '0';
data110 : in std_logic := '0';
data111 : in std_logic := '0';
data112 : in std_logic := '0';
data113 : in std_logic := '0';
data114 : in std_logic := '0';
data115 : in std_logic := '0';
data116 : in std_logic := '0';
data117 : in std_logic := '0';
data118 : in std_logic := '0';
data119 : in std_logic := '0';
data120 : in std_logic := '0';
data121 : in std_logic := '0';
data122 : in std_logic := '0';
data123 : in std_logic := '0';
data124 : in std_logic := '0';
data125 : in std_logic := '0';
data126 : in std_logic := '0';
data127 : in std_logic := '0';
q : out std_logic
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_muxbin128 IS
generic (
NAME : string := "";
PORTS : integer := 128;
WIDTH : integer := 16
);
port (
sel : in std_logic_vector(6 downto 0) := (others => '0');
data0 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data1 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data2 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data3 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data4 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data5 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data6 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data7 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data8 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data9 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data10 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data11 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data12 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data13 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data14 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data15 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data16 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data17 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data18 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data19 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data20 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data21 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data22 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data23 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data24 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data25 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data26 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data27 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data28 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data29 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data30 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data31 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data32 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data33 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data34 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data35 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data36 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data37 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data38 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data39 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data40 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data41 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data42 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data43 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data44 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data45 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data46 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data47 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data48 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data49 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data50 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data51 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data52 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data53 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data54 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data55 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data56 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data57 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data58 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data59 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data60 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data61 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data62 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data63 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data64 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data65 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data66 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data67 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data68 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data69 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data70 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data71 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data72 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data73 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data74 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data75 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data76 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data77 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data78 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data79 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data80 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data81 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data82 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data83 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data84 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data85 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data86 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data87 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data88 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data89 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data90 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data91 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data92 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data93 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data94 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data95 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data96 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data97 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data98 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data99 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data100 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data101 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data102 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data103 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data104 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data105 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data106 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data107 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data108 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data109 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data110 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data111 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data112 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data113 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data114 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data115 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data116 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data117 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data118 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data119 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data120 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data121 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data122 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data123 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data124 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data125 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data126 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data127 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
q : out std_logic_vector(WIDTH-1 downto 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_muxhot16_wire IS
generic (
NAME : string := "";
PORTS : integer := 16;
WIDTH : integer := 1
);
port (
sel : in std_logic_vector(PORTS-1 downto 0) := (others => '0');
data0 : in std_logic := '0';
data1 : in std_logic := '0';
data2 : in std_logic := '0';
data3 : in std_logic := '0';
data4 : in std_logic := '0';
data5 : in std_logic := '0';
data6 : in std_logic := '0';
data7 : in std_logic := '0';
data8 : in std_logic := '0';
data9 : in std_logic := '0';
data10 : in std_logic := '0';
data11 : in std_logic := '0';
data12 : in std_logic := '0';
data13 : in std_logic := '0';
data14 : in std_logic := '0';
data15 : in std_logic := '0';
q : out std_logic
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_muxhot16 IS
generic (
NAME : string := "";
PORTS : integer := 16;
WIDTH : integer := 16
);
port (
sel : in std_logic_vector(PORTS-1 downto 0) := (others => '0');
data0 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data1 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data2 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data3 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data4 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data5 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data6 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data7 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data8 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data9 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data10 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data11 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data12 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data13 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data14 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data15 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
q : out std_logic_vector(WIDTH-1 downto 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_muxhot32_wire IS
generic (
NAME : string := "";
PORTS : integer := 32;
WIDTH : integer := 1
);
port (
sel : in std_logic_vector(PORTS-1 downto 0) := (others => '0');
data0 : in std_logic := '0';
data1 : in std_logic := '0';
data2 : in std_logic := '0';
data3 : in std_logic := '0';
data4 : in std_logic := '0';
data5 : in std_logic := '0';
data6 : in std_logic := '0';
data7 : in std_logic := '0';
data8 : in std_logic := '0';
data9 : in std_logic := '0';
data10 : in std_logic := '0';
data11 : in std_logic := '0';
data12 : in std_logic := '0';
data13 : in std_logic := '0';
data14 : in std_logic := '0';
data15 : in std_logic := '0';
data16 : in std_logic := '0';
data17 : in std_logic := '0';
data18 : in std_logic := '0';
data19 : in std_logic := '0';
data20 : in std_logic := '0';
data21 : in std_logic := '0';
data22 : in std_logic := '0';
data23 : in std_logic := '0';
data24 : in std_logic := '0';
data25 : in std_logic := '0';
data26 : in std_logic := '0';
data27 : in std_logic := '0';
data28 : in std_logic := '0';
data29 : in std_logic := '0';
data30 : in std_logic := '0';
data31 : in std_logic := '0';
q : out std_logic
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_muxhot32 IS
generic (
NAME : string := "";
PORTS : integer := 32;
WIDTH : integer := 16
);
port (
sel : in std_logic_vector(PORTS-1 downto 0) := (others => '0');
data0 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data1 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data2 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data3 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data4 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data5 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data6 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data7 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data8 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data9 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data10 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data11 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data12 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data13 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data14 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data15 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data16 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data17 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data18 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data19 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data20 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data21 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data22 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data23 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data24 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data25 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data26 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data27 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data28 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data29 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data30 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data31 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
q : out std_logic_vector(WIDTH-1 downto 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_muxhot64_wire IS
generic (
NAME : string := "";
PORTS : integer := 64;
WIDTH : integer := 1
);
port (
sel : in std_logic_vector(PORTS-1 downto 0) := (others => '0');
data0 : in std_logic := '0';
data1 : in std_logic := '0';
data2 : in std_logic := '0';
data3 : in std_logic := '0';
data4 : in std_logic := '0';
data5 : in std_logic := '0';
data6 : in std_logic := '0';
data7 : in std_logic := '0';
data8 : in std_logic := '0';
data9 : in std_logic := '0';
data10 : in std_logic := '0';
data11 : in std_logic := '0';
data12 : in std_logic := '0';
data13 : in std_logic := '0';
data14 : in std_logic := '0';
data15 : in std_logic := '0';
data16 : in std_logic := '0';
data17 : in std_logic := '0';
data18 : in std_logic := '0';
data19 : in std_logic := '0';
data20 : in std_logic := '0';
data21 : in std_logic := '0';
data22 : in std_logic := '0';
data23 : in std_logic := '0';
data24 : in std_logic := '0';
data25 : in std_logic := '0';
data26 : in std_logic := '0';
data27 : in std_logic := '0';
data28 : in std_logic := '0';
data29 : in std_logic := '0';
data30 : in std_logic := '0';
data31 : in std_logic := '0';
data32 : in std_logic := '0';
data33 : in std_logic := '0';
data34 : in std_logic := '0';
data35 : in std_logic := '0';
data36 : in std_logic := '0';
data37 : in std_logic := '0';
data38 : in std_logic := '0';
data39 : in std_logic := '0';
data40 : in std_logic := '0';
data41 : in std_logic := '0';
data42 : in std_logic := '0';
data43 : in std_logic := '0';
data44 : in std_logic := '0';
data45 : in std_logic := '0';
data46 : in std_logic := '0';
data47 : in std_logic := '0';
data48 : in std_logic := '0';
data49 : in std_logic := '0';
data50 : in std_logic := '0';
data51 : in std_logic := '0';
data52 : in std_logic := '0';
data53 : in std_logic := '0';
data54 : in std_logic := '0';
data55 : in std_logic := '0';
data56 : in std_logic := '0';
data57 : in std_logic := '0';
data58 : in std_logic := '0';
data59 : in std_logic := '0';
data60 : in std_logic := '0';
data61 : in std_logic := '0';
data62 : in std_logic := '0';
data63 : in std_logic := '0';
q : out std_logic
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_muxhot64 IS
generic (
NAME : string := "";
PORTS : integer := 64;
WIDTH : integer := 16
);
port (
sel : in std_logic_vector(PORTS-1 downto 0) := (others => '0');
data0 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data1 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data2 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data3 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data4 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data5 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data6 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data7 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data8 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data9 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data10 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data11 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data12 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data13 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data14 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data15 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data16 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data17 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data18 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data19 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data20 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data21 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data22 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data23 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data24 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data25 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data26 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data27 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data28 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data29 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data30 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data31 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data32 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data33 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data34 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data35 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data36 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data37 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data38 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data39 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data40 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data41 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data42 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data43 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data44 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data45 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data46 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data47 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data48 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data49 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data50 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data51 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data52 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data53 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data54 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data55 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data56 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data57 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data58 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data59 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data60 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data61 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data62 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data63 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
q : out std_logic_vector(WIDTH-1 downto 0)
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_muxhot128_wire IS
generic (
NAME : string := "";
PORTS : integer := 128;
WIDTH : integer := 1
);
port (
sel : in std_logic_vector(PORTS-1 downto 0) := (others => '0');
data0 : in std_logic := '0';
data1 : in std_logic := '0';
data2 : in std_logic := '0';
data3 : in std_logic := '0';
data4 : in std_logic := '0';
data5 : in std_logic := '0';
data6 : in std_logic := '0';
data7 : in std_logic := '0';
data8 : in std_logic := '0';
data9 : in std_logic := '0';
data10 : in std_logic := '0';
data11 : in std_logic := '0';
data12 : in std_logic := '0';
data13 : in std_logic := '0';
data14 : in std_logic := '0';
data15 : in std_logic := '0';
data16 : in std_logic := '0';
data17 : in std_logic := '0';
data18 : in std_logic := '0';
data19 : in std_logic := '0';
data20 : in std_logic := '0';
data21 : in std_logic := '0';
data22 : in std_logic := '0';
data23 : in std_logic := '0';
data24 : in std_logic := '0';
data25 : in std_logic := '0';
data26 : in std_logic := '0';
data27 : in std_logic := '0';
data28 : in std_logic := '0';
data29 : in std_logic := '0';
data30 : in std_logic := '0';
data31 : in std_logic := '0';
data32 : in std_logic := '0';
data33 : in std_logic := '0';
data34 : in std_logic := '0';
data35 : in std_logic := '0';
data36 : in std_logic := '0';
data37 : in std_logic := '0';
data38 : in std_logic := '0';
data39 : in std_logic := '0';
data40 : in std_logic := '0';
data41 : in std_logic := '0';
data42 : in std_logic := '0';
data43 : in std_logic := '0';
data44 : in std_logic := '0';
data45 : in std_logic := '0';
data46 : in std_logic := '0';
data47 : in std_logic := '0';
data48 : in std_logic := '0';
data49 : in std_logic := '0';
data50 : in std_logic := '0';
data51 : in std_logic := '0';
data52 : in std_logic := '0';
data53 : in std_logic := '0';
data54 : in std_logic := '0';
data55 : in std_logic := '0';
data56 : in std_logic := '0';
data57 : in std_logic := '0';
data58 : in std_logic := '0';
data59 : in std_logic := '0';
data60 : in std_logic := '0';
data61 : in std_logic := '0';
data62 : in std_logic := '0';
data63 : in std_logic := '0';
data64 : in std_logic := '0';
data65 : in std_logic := '0';
data66 : in std_logic := '0';
data67 : in std_logic := '0';
data68 : in std_logic := '0';
data69 : in std_logic := '0';
data70 : in std_logic := '0';
data71 : in std_logic := '0';
data72 : in std_logic := '0';
data73 : in std_logic := '0';
data74 : in std_logic := '0';
data75 : in std_logic := '0';
data76 : in std_logic := '0';
data77 : in std_logic := '0';
data78 : in std_logic := '0';
data79 : in std_logic := '0';
data80 : in std_logic := '0';
data81 : in std_logic := '0';
data82 : in std_logic := '0';
data83 : in std_logic := '0';
data84 : in std_logic := '0';
data85 : in std_logic := '0';
data86 : in std_logic := '0';
data87 : in std_logic := '0';
data88 : in std_logic := '0';
data89 : in std_logic := '0';
data90 : in std_logic := '0';
data91 : in std_logic := '0';
data92 : in std_logic := '0';
data93 : in std_logic := '0';
data94 : in std_logic := '0';
data95 : in std_logic := '0';
data96 : in std_logic := '0';
data97 : in std_logic := '0';
data98 : in std_logic := '0';
data99 : in std_logic := '0';
data100 : in std_logic := '0';
data101 : in std_logic := '0';
data102 : in std_logic := '0';
data103 : in std_logic := '0';
data104 : in std_logic := '0';
data105 : in std_logic := '0';
data106 : in std_logic := '0';
data107 : in std_logic := '0';
data108 : in std_logic := '0';
data109 : in std_logic := '0';
data110 : in std_logic := '0';
data111 : in std_logic := '0';
data112 : in std_logic := '0';
data113 : in std_logic := '0';
data114 : in std_logic := '0';
data115 : in std_logic := '0';
data116 : in std_logic := '0';
data117 : in std_logic := '0';
data118 : in std_logic := '0';
data119 : in std_logic := '0';
data120 : in std_logic := '0';
data121 : in std_logic := '0';
data122 : in std_logic := '0';
data123 : in std_logic := '0';
data124 : in std_logic := '0';
data125 : in std_logic := '0';
data126 : in std_logic := '0';
data127 : in std_logic := '0';
q : out std_logic
);
END COMPONENT;
COMPONENT alt_vipvfr131_common_muxhot128 IS
generic (
NAME : string := "";
PORTS : integer := 128;
WIDTH : integer := 16
);
port (
sel : in std_logic_vector(PORTS-1 downto 0) := (others => '0');
data0 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data1 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data2 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data3 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data4 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data5 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data6 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data7 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data8 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data9 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data10 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data11 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data12 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data13 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data14 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data15 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data16 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data17 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data18 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data19 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data20 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data21 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data22 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data23 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data24 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data25 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data26 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data27 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data28 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data29 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data30 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data31 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data32 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data33 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data34 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data35 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data36 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data37 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data38 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data39 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data40 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data41 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data42 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data43 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data44 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data45 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data46 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data47 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data48 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data49 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data50 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data51 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data52 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data53 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data54 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data55 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data56 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data57 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data58 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data59 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data60 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data61 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data62 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data63 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data64 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data65 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data66 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data67 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data68 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data69 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data70 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data71 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data72 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data73 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data74 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data75 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data76 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data77 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data78 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data79 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data80 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data81 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data82 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data83 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data84 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data85 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data86 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data87 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data88 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data89 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data90 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data91 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data92 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data93 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data94 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data95 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data96 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data97 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data98 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data99 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data100 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data101 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data102 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data103 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data104 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data105 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data106 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data107 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data108 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data109 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data110 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data111 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data112 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data113 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data114 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data115 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data116 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data117 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data118 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data119 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data120 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data121 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data122 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data123 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data124 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data125 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data126 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
data127 : in std_logic_vector(WIDTH-1 downto 0) := (others => '0');
q : out std_logic_vector(WIDTH-1 downto 0)
);
END COMPONENT;
--------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------
-- synopsys synthesis_off
TYPE TTA_X_D_STRING_PTR IS ACCESS STRING;
TYPE TTA_X_D_SLV_PTR IS ACCESS STD_LOGIC_VECTOR;
TYPE TTA_X_D_RN_T IS ARRAY ( INTEGER RANGE <> ) OF TTA_X_D_STRING_PTR;
TYPE TTA_X_D_RV_T IS ARRAY ( INTEGER RANGE <> ) OF TTA_X_D_SLV_PTR;
PROCEDURE TTA_X_D_registerTrace (
opAddress : IN STRING;
opCode : IN STRING;
opDecode: IN STRING
);
PROCEDURE TTA_X_D_registerDump (
fuName : IN STRING;
registerNames : INOUT TTA_X_D_RN_T;
registerValues : INOUT TTA_X_D_RV_T
);
PROCEDURE TTA_X_D_openTrace (
fileName : IN STRING := "trace.out";
shortFileName : IN STRING := "shorttrace.out"
);
-- synopsys synthesis_on
--------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------
END alt_vipvfr131_common_package;
PACKAGE BODY alt_vipvfr131_common_package IS
-- -----------------------------------------------------------
-- Fifo functions
-- -----------------------------------------------------------
-- find the width of a signal of "unsigned" type wide
-- enough to hold numbers as big as "max"
-- this is equivalent to log-2 max rounded up
function wide_enough_for(max : integer) return integer is
variable r : integer := 0;
variable m : integer := max;
begin
while m > 0 loop
m := m / 2;
r := r + 1;
end loop;
return r;
end function wide_enough_for;
function two_to_the_power(v : integer) return integer is
variable r : integer := 1;
variable i : integer := v;
begin
while i > 0 loop
r := r * 2;
i := i - 1;
end loop;
return r;
end function two_to_the_power;
-- generate as many repeating copies of the hexadecimal string
-- DEAD as will fit into a "b" bit std_logic_vector
function dead_bits(b : integer) return std_logic_vector is
variable r : std_logic_vector(b - 1 downto 0);
constant DEAD : std_logic_vector(15 downto 0) := "1101111010101101";
begin
for i in 0 to b - 1 loop
r(i) := DEAD(i mod 16);
end loop;
return r;
end function dead_bits;
-- return the higher of the two passed integers
-- can't believe there isn't a handy library function for this,
-- but a quick google couldn't find it
function maximum(a, b : integer) return integer is
begin
if (a > b) then
return a;
else
return b;
end if;
end function maximum;
-- find the minimum, likewise
function minimum(a, b : integer) return integer is
begin
if (a > b) then
return b;
else
return a;
end if;
end function minimum;
-- calculate the width of a byte enable port
-- depends on whether byte enables are required and what the
-- data width of the quantity to be byte enabled is
function calculate_be_width(be_used : boolean; data_width : integer) return integer is
begin
if not be_used then
return 0;
else
assert data_width mod 8 = 0
report "Tried to calculate the byte enable width of a data width not divisble by 8"
severity warning;
return data_width / 8;
end if;
end function calculate_be_width;
function calculate_be_width(be_used : integer; data_width : integer) return integer is
begin
if (be_used = 1) then
return calculate_be_width(true, data_width);
else
return calculate_be_width(false, data_width);
end if;
end function calculate_be_width;
function calculate_be_width(data_width : integer) return integer is
begin
return calculate_be_width(true, data_width);
end function calculate_be_width;
-- translate from cusp integer representation of families to the
-- string representation used by altera megafunctions and the like
function family_string(f : integer) return string is
begin
case f is
when FAMILY_STRATIX => return "Stratix";
when FAMILY_STRATIXII => return "Stratix II";
when FAMILY_STRATIXIII => return "Stratix III";
when FAMILY_CYCLONE => return "Cyclone";
when FAMILY_CYCLONEII => return "Cyclone II";
when FAMILY_HARDCOPYII => return "HardCopy II";
when others => return "Stratix";
end case;
end function family_string;
-- translate a std_logic_vector into a binary string represenation of same
function to_string(slv : std_logic_vector) return string is
variable s : string(slv'LENGTH downto 1);
begin
for i in slv'HIGH downto slv'LOW loop
if slv(i) = '1' then
s(1 + i) := '1';
else
s(1 + i) := '0';
end if;
end loop;
return s;
end function to_string;
function boolean_to_int(value : boolean) return integer is
begin
if value then
return 1;
else
return 0;
end if;
end function boolean_to_int;
-- synopsys synthesis_off
type reg_list_t;
type reg_list_ptr_t is access reg_list_t;
type reg_list_t is record
reg_name : TTA_X_D_string_ptr;
reg_value : TTA_X_D_slv_ptr;
next_elem : reg_list_ptr_t;
end record;
type fu_list_t;
type fu_list_ptr_t is access fu_list_t;
type fu_list_t is record
fu_name : TTA_X_D_string_ptr;
reg_values : reg_list_ptr_t;
next_elem : fu_list_ptr_t;
end record;
shared variable fu_state : fu_list_ptr_t := null;
shared variable fu_state_previous : fu_list_ptr_t := null;
shared variable ENABLE_DEBUG_TRACE : INTEGER := 0;
constant CURRENT_STATE : INTEGER := 0;
constant PREVIOUS_STATE : INTEGER := 1;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-----------------------------------------
-- Convert Integer to Hex
-----------------------------------------
FUNCTION TIntegerToHex(i : INTEGER; ndigits : INTEGER) RETURN STRING IS
VARIABLE s : STRING(1 TO 256) := (others => '0');
VARIABLE Num, ThisDigit, si : INTEGER;
BEGIN
Num := i;
si := 256;
WHILE (Num > 0) LOOP
ThisDigit := Num - ((Num / 16) * 16);
CASE ThisDigit IS
WHEN 1 => s(si) := '1';
WHEN 2 => s(si) := '2';
WHEN 3 => s(si) := '3';
WHEN 4 => s(si) := '4';
WHEN 5 => s(si) := '5';
WHEN 6 => s(si) := '6';
WHEN 7 => s(si) := '7';
WHEN 8 => s(si) := '8';
WHEN 9 => s(si) := '9';
WHEN 10 => s(si) := 'A';
WHEN 11 => s(si) := 'B';
WHEN 12 => s(si) := 'C';
WHEN 13 => s(si) := 'D';
WHEN 14 => s(si) := 'E';
WHEN 15 => s(si) := 'F';
WHEN OTHERS => s(si) := '0';
END CASE;
si := si - 1;
Num := Num / 16;
END LOOP;
IF (i = 0) THEN
si := si - 1;
END IF;
RETURN s(257-ndigits TO 256);
END ;
-----------------------------------------
-- convert integer to string
function TIntegerToString( value : integer ) return string is
variable ivalue : integer := 0;
variable index : integer := 1;
variable digit : integer := 0;
variable temp: string(10 downto 1) := "0000000000";
begin
index := 1;
if (value < 0 ) then
ivalue := -value;
else
ivalue := value;
end if;
while (ivalue > 0) loop
digit := ivalue mod 10;
ivalue := ivalue/10;
case digit is
when 0 => temp(index) := '0';
when 1 => temp(index) := '1';
when 2 => temp(index) := '2';
when 3 => temp(index) := '3';
when 4 => temp(index) := '4';
when 5 => temp(index) := '5';
when 6 => temp(index) := '6';
when 7 => temp(index) := '7';
when 8 => temp(index) := '8';
when 9 => temp(index) := '9';
when others => ASSERT FALSE
REPORT "Illegal number!"
SEVERITY ERROR;
end case;
index := index + 1;
end loop;
if value /= 0 then
index := index - 1;
end if;
if (value < 0) then
return ('-'& temp(index downto 1));
else
return temp(index downto 1);
end if;
end ;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- search along the state looking for an FU with name fu_name
-- if not found create a new fu record, set the name, and
-- place it at the head of the list
procedure findFU ( fu_name : IN STRING;
fu : OUT fu_list_ptr_t ) is
variable iter : fu_list_ptr_t;
begin
iter := fu_state;
find: loop
if iter = null then
iter := new fu_list_t;
iter.fu_name := new String(fu_name'high downto fu_name'low);
iter.fu_name.all := fu_name;
iter.next_elem := fu_state;
fu_state := iter;
end if;
exit when iter.fu_name.all = fu_name;
iter := iter.next_elem;
end loop;
fu := iter;
end;
-- like FU - works on _previous state
procedure findFU_previous ( fu_name : IN STRING;
fu : OUT fu_list_ptr_t ) is
variable iter : fu_list_ptr_t;
begin
iter := fu_state_previous;
find: loop
if iter = null then
iter := new fu_list_t;
iter.fu_name := new String(fu_name'high downto fu_name'low);
iter.fu_name.all := fu_name;
iter.next_elem := fu_state;
fu_state_previous := iter;
end if;
exit when iter.fu_name.all = fu_name;
iter := iter.next_elem;
end loop;
fu := iter;
end;
-- search along the FU looking for an reg with name reg_name
-- if not found create a new reg record, set the name, and
-- place it at the head of the list
procedure findReg ( fu_name : IN STRING;
state : IN INTEGER;
reg_name : INOUT TTA_X_D_string_ptr;
reg : OUT reg_list_ptr_t ) is
variable iter : reg_list_ptr_t;
variable fu : fu_list_ptr_t;
begin
if state = CURRENT_STATE then
findFu(fu_name, fu);
else
findFu_previous(fu_name, fu);
end if;
iter := fu.reg_values;
find: loop
if iter = null then
iter := new reg_list_t;
iter.reg_name := new String(reg_name.all'high downto reg_name.all'low);
iter.reg_name.all := reg_name.all;
iter.next_elem := fu.reg_values;
fu.reg_values := iter;
end if;
exit when iter.reg_name.all = reg_name.all;
iter := iter.next_elem;
end loop;
reg := iter;
end;
-- update the value for (fu_name, reg_name) creating a new record if one is needed
procedure updateReg ( fu_name : IN STRING;
state : IN INTEGER;
reg_name : INOUT TTA_X_D_string_ptr;
reg_value : INOUT TTA_X_D_slv_ptr ) is
variable reg : reg_list_ptr_t;
begin
findReg(fu_name, state, reg_name, reg);
if reg.reg_value = null then
reg.reg_value := new std_logic_vector(reg_value.all'high downto reg_value.all'low);
end if;
reg.reg_value.all := reg_value.all;
end;
PROCEDURE TTA_X_D_registerDump (
fuName : IN STRING;
registerNames : INOUT TTA_X_D_RN_T;
registerValues : INOUT TTA_X_D_RV_T
) IS
BEGIN
if ENABLE_DEBUG_TRACE /= 0 then
for count in registerNames'high downto registerNames'low loop
updateReg ( fuName, CURRENT_STATE, registerNames(count), registerValues(count) );
end loop;
end if; -- debug trace enabled
END;
-- ----------------------------------------------
FILE traceFile : TEXT;
FILE shortTraceFile : TEXT;
shared variable traceFileOpen : integer := 0;
PROCEDURE TTA_X_D_openTrace (
fileName : IN STRING := "trace.out";
shortFileName : IN STRING := "shorttrace.out"
) IS
BEGIN
if ENABLE_DEBUG_TRACE /= 0 then
FILE_OPEN (traceFile, fileName, WRITE_MODE);
FILE_OPEN (shorttraceFile, shortFileName, WRITE_MODE);
traceFileOpen := 1;
end if; -- debug trace enabled
END;
-- create / update
procedure save_fu_state is
variable last_fu_iter : fu_list_ptr_t;
variable last_reg_iter : reg_list_ptr_t;
variable fu_iter : fu_list_ptr_t;
variable reg_iter : reg_list_ptr_t;
begin
fu_iter := fu_state;
fu_loop: loop
exit fu_loop when fu_iter = null;
reg_iter := fu_iter.reg_values;
reg_loop: loop
exit reg_loop when reg_iter = null;
updateReg ( fu_iter.fu_name.all, PREVIOUS_STATE, reg_iter.reg_name, reg_iter.reg_value );
reg_iter := reg_iter.next_elem;
end loop;
fu_iter := fu_iter.next_elem;
end loop;
end;
-- generate trace information for the specified address, opcode, operation
--
PROCEDURE TTA_X_D_registerTrace (
opAddress : IN STRING;
opCode : IN STRING;
opDecode: IN STRING
) IS
variable fu_iter : fu_list_ptr_t;
variable reg_iter : reg_list_ptr_t;
variable l:line;
variable current_reg_value : reg_list_ptr_t;
BEGIN
if ENABLE_DEBUG_TRACE /= 0 then
if traceFileOpen = 0 then
TTA_X_D_openTrace;
end if;
-- -----------------------------------------------------------
-- COMPLETE REGISTER DUMP
-- -----------------------------------------------------------
fu_iter := fu_state;
write(l, opAddress);
write(l, STRING'(" ") );
write(l, opCode);
write(l, STRING'(" ") );
fu_loop: loop
exit fu_loop when fu_iter = null;
reg_iter := fu_iter.reg_values;
reg_loop: loop
exit reg_loop when reg_iter = null;
write(l, fu_iter.fu_name.all);
write(l, STRING'("."));
write(l, reg_iter.reg_name.all);
write(l, STRING'("="));
-- write(l, TIntegerToHex(To_Integer(unsigned(reg_iter.reg_value.all)),
-- (reg_iter.reg_value.all'length+3)/4) );
if reg_iter.reg_value.all'length = 1 then
write(l, TIntegerToString(To_Integer(unsigned(reg_iter.reg_value.all))));
elsif Is_X(reg_iter.reg_value.all) then
assert false report ("Register " & fu_iter.fu_name.all & STRING'(".") & reg_iter.reg_name.all & " contains undefined value trace shows 0" ) severity warning;
write(l, STRING'("."));
else
write(l, TIntegerToString(To_Integer(signed(reg_iter.reg_value.all))));
end if;
write(l, STRING'(" "));
reg_iter := reg_iter.next_elem;
end loop;
fu_iter := fu_iter.next_elem;
end loop;
write(l, opDecode);
writeline(traceFile, l);
-- -----------------------------------------------------------
-- REGISTER CHANGE DUMP
-- -----------------------------------------------------------
if fu_state_previous /= null then
fu_iter := fu_state_previous;
write(l, "0x" & opAddress);
write(l, STRING'(" ") );
-- write(l, opCode);
-- write(l, STRING'(" ") );
write(l, opDecode);
writeline(shortTraceFile, l);
short_fu_loop: loop
exit short_fu_loop when fu_iter = null;
reg_iter := fu_iter.reg_values;
short_reg_loop: loop
exit short_reg_loop when reg_iter = null;
findReg( fu_iter.fu_name.all, CURRENT_STATE, reg_iter.reg_name, current_reg_value );
if current_reg_value.reg_value /= null and reg_iter.reg_value /= null then
if current_reg_value.reg_value.all /= reg_iter.reg_value.all then
write(l, fu_iter.fu_name.all);
write(l, STRING'("."));
write(l, reg_iter.reg_name.all);
write(l, STRING'("="));
-- write(l, TIntegerToHex(To_Integer(unsigned(current_reg_value.reg_value.all)),
-- (reg_iter.reg_value.all'length+3)/4) );
if current_reg_value.reg_value.all'length = 1 then
write(l, TIntegerToString(To_Integer(unsigned(current_reg_value.reg_value.all))));
else
write(l, TIntegerToString(To_Integer(signed(current_reg_value.reg_value.all))));
end if;
write(l, STRING'(" "));
end if;
end if;
reg_iter := reg_iter.next_elem;
end loop;
fu_iter := fu_iter.next_elem;
end loop;
writeline(shortTraceFile, l);
end if;
-- -----------------------------------------------------------
-- SAVE STATE TO COMPUTE REGISTER CHANGES
-- -----------------------------------------------------------
save_fu_state;
end if; -- debug trace enabled
END;
-- synopsys synthesis_on
END alt_vipvfr131_common_package;
| mit | 73c978796727688028b1c9335a256628 | 0.563877 | 2.831901 | false | false | false | false |
FinnK/lems2hdl | work/N3_pointCellCondBased/ISIM_output/h.vhdl | 1 | 20,346 |
---------------------------------------------------------------------
-- Standard Library bits
---------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- For Modelsim
--use ieee.fixed_pkg.all;
--use ieee.fixed_float_types.ALL;
-- For ISE
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use ieee_proposed.fixed_float_types.ALL;
use IEEE.numeric_std.all;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Entity Description
---------------------------------------------------------------------
entity h is
Port (
clk : in STD_LOGIC; --SYSTEM CLOCK, THIS ITSELF DOES NOT SIGNIFY TIME STEPS - AKA A SINGLE TIMESTEP MAY TAKE MANY CLOCK CYCLES
init_model : in STD_LOGIC; --SYNCHRONOUS RESET
step_once_go : in STD_LOGIC; --signals to the neuron from the core that a time step is to be simulated
component_done : out STD_LOGIC;
requirement_voltage_v : in sfixed (2 downto -22);
param_none_instances : in sfixed (18 downto -13);
exposure_none_fcond : out sfixed (18 downto -13);
exposure_none_q : out sfixed (18 downto -13);
statevariable_none_q_out : out sfixed (18 downto -13);
statevariable_none_q_in : in sfixed (18 downto -13);
derivedvariable_none_fcond_out : out sfixed (18 downto -13);
derivedvariable_none_fcond_in : in sfixed (18 downto -13);
param_per_time_forwardRateh1_rate : in sfixed (18 downto -2);
param_voltage_forwardRateh1_midpoint : in sfixed (2 downto -22);
param_voltage_forwardRateh1_scale : in sfixed (2 downto -22);
param_voltage_inv_forwardRateh1_scale_inv : in sfixed (22 downto -2);
exposure_per_time_forwardRateh1_r : out sfixed (18 downto -2);
derivedvariable_per_time_forwardRateh1_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_forwardRateh1_r_in : in sfixed (18 downto -2);
param_per_time_reverseRateh1_rate : in sfixed (18 downto -2);
param_voltage_reverseRateh1_midpoint : in sfixed (2 downto -22);
param_voltage_reverseRateh1_scale : in sfixed (2 downto -22);
param_voltage_inv_reverseRateh1_scale_inv : in sfixed (22 downto -2);
exposure_per_time_reverseRateh1_r : out sfixed (18 downto -2);
derivedvariable_per_time_reverseRateh1_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_reverseRateh1_r_in : in sfixed (18 downto -2);
sysparam_time_timestep : in sfixed (-6 downto -22);
sysparam_time_simtime : in sfixed (6 downto -22)
);
end h;
---------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-- Architecture Begins
-------------------------------------------------------------------------------------------
architecture RTL of h is
signal COUNT : unsigned(2 downto 0) := "000";
signal childrenCombined_Component_done_single_shot_fired : STD_LOGIC := '0';
signal childrenCombined_Component_done_single_shot : STD_LOGIC := '0';
signal childrenCombined_Component_done : STD_LOGIC := '0';
signal Component_done_int : STD_LOGIC := '0';
signal subprocess_der_int_pre_ready : STD_LOGIC := '0';
signal subprocess_der_int_ready : STD_LOGIC := '0';
signal subprocess_der_ready : STD_LOGIC := '0';
signal subprocess_dyn_int_pre_ready : STD_LOGIC := '0';
signal subprocess_dyn_int_ready : STD_LOGIC := '0';
signal subprocess_dyn_ready : STD_LOGIC := '0';
signal subprocess_model_ready : STD_LOGIC := '1';
signal subprocess_all_ready_shotdone : STD_LOGIC := '1';
signal subprocess_all_ready_shot : STD_LOGIC := '0';
signal subprocess_all_ready : STD_LOGIC := '0';signal pre_pow_fcond_power_result1_A : sfixed(18 downto -13);
signal pre_pow_fcond_power_result1_A_next : sfixed(18 downto -13);
signal pre_pow_fcond_power_result1_X : sfixed(18 downto -13);
signal pre_pow_fcond_power_result1_X_next : sfixed(18 downto -13);
signal pow_fcond_power_result1 : sfixed(18 downto -13);
signal statevariable_none_noregime_q_temp_1 : sfixed (18 downto -13);
signal statevariable_none_noregime_q_temp_1_next : sfixed (18 downto -13);
component delayDone is
generic(
Steps : integer := 10);
port(
clk : In Std_logic;
init_model : In Std_logic;
Start : In Std_logic;
Done : Out Std_logic
);
end component;
Component ParamPow is
generic(
BIT_TOP : integer := 11;
BIT_BOTTOM : integer := -12);
port(
clk : In Std_logic;
init_model : In Std_logic;
Start : In Std_logic;
Done : Out Std_logic;
X : In sfixed(BIT_TOP downto BIT_BOTTOM);
A : In sfixed(BIT_TOP downto BIT_BOTTOM);
Output : Out sfixed(BIT_TOP downto BIT_BOTTOM)
);
end Component;
---------------------------------------------------------------------
-- Derived Variables and parameters
---------------------------------------------------------------------
signal DerivedVariable_none_rateScale : sfixed (18 downto -13) := to_sfixed(0.0 ,18,-13);
signal DerivedVariable_none_rateScale_next : sfixed (18 downto -13) := to_sfixed(0.0 ,18,-13);
signal DerivedVariable_per_time_alpha : sfixed (18 downto -2) := to_sfixed(0.0 ,18,-2);
signal DerivedVariable_per_time_alpha_next : sfixed (18 downto -2) := to_sfixed(0.0 ,18,-2);
signal DerivedVariable_per_time_beta : sfixed (18 downto -2) := to_sfixed(0.0 ,18,-2);
signal DerivedVariable_per_time_beta_next : sfixed (18 downto -2) := to_sfixed(0.0 ,18,-2);
signal DerivedVariable_none_fcond : sfixed (18 downto -13) := to_sfixed(0.0 ,18,-13);
signal DerivedVariable_none_fcond_next : sfixed (18 downto -13) := to_sfixed(0.0 ,18,-13);
signal DerivedVariable_none_inf : sfixed (18 downto -13) := to_sfixed(0.0 ,18,-13);
signal DerivedVariable_none_inf_next : sfixed (18 downto -13) := to_sfixed(0.0 ,18,-13);
signal DerivedVariable_time_tau : sfixed (6 downto -18) := to_sfixed(0.0 ,6,-18);
signal DerivedVariable_time_tau_next : sfixed (6 downto -18) := to_sfixed(0.0 ,6,-18);
---------------------------------------------------------------------
---------------------------------------------------------------------
-- EDState internal Variables
---------------------------------------------------------------------
signal statevariable_none_q_next : sfixed (18 downto -13);
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Output Port internal Variables
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Child Components
---------------------------------------------------------------------
component forwardRateh1
Port (
clk : in STD_LOGIC; --SYSTEM CLOCK, THIS ITSELF DOES NOT SIGNIFY TIME STEPS - AKA A SINGLE TIMESTEP MAY TAKE MANY CLOCK CYCLES
init_model : in STD_LOGIC;
step_once_go : in STD_LOGIC; --signals to the neuron from the core that a time step is to be simulated
Component_done : out STD_LOGIC;
requirement_voltage_v : in sfixed (2 downto -22);
param_per_time_rate : in sfixed (18 downto -2);
param_voltage_midpoint : in sfixed (2 downto -22);
param_voltage_scale : in sfixed (2 downto -22);
param_voltage_inv_scale_inv : in sfixed (22 downto -2);
exposure_per_time_r : out sfixed (18 downto -2);
derivedvariable_per_time_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_r_in : in sfixed (18 downto -2);
sysparam_time_timestep : in sfixed (-6 downto -22);
sysparam_time_simtime : in sfixed (6 downto -22)
);
end component;
signal forwardRateh1_Component_done : STD_LOGIC ; signal Exposure_per_time_forwardRateh1_r_internal : sfixed (18 downto -2);
---------------------------------------------------------------------
component reverseRateh1
Port (
clk : in STD_LOGIC; --SYSTEM CLOCK, THIS ITSELF DOES NOT SIGNIFY TIME STEPS - AKA A SINGLE TIMESTEP MAY TAKE MANY CLOCK CYCLES
init_model : in STD_LOGIC;
step_once_go : in STD_LOGIC; --signals to the neuron from the core that a time step is to be simulated
Component_done : out STD_LOGIC;
requirement_voltage_v : in sfixed (2 downto -22);
param_per_time_rate : in sfixed (18 downto -2);
param_voltage_midpoint : in sfixed (2 downto -22);
param_voltage_scale : in sfixed (2 downto -22);
param_voltage_inv_scale_inv : in sfixed (22 downto -2);
exposure_per_time_r : out sfixed (18 downto -2);
derivedvariable_per_time_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_r_in : in sfixed (18 downto -2);
sysparam_time_timestep : in sfixed (-6 downto -22);
sysparam_time_simtime : in sfixed (6 downto -22)
);
end component;
signal reverseRateh1_Component_done : STD_LOGIC ; signal Exposure_per_time_reverseRateh1_r_internal : sfixed (18 downto -2);
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Begin Internal Processes
---------------------------------------------------------------------
begin
---------------------------------------------------------------------
-- Child EDComponent Instantiations and corresponding internal variables
---------------------------------------------------------------------
forwardRateh1_uut : forwardRateh1
port map (
clk => clk,
init_model => init_model,
step_once_go => step_once_go,
Component_done => forwardRateh1_Component_done,
param_per_time_rate => param_per_time_forwardRateh1_rate,
param_voltage_midpoint => param_voltage_forwardRateh1_midpoint,
param_voltage_scale => param_voltage_forwardRateh1_scale,
param_voltage_inv_scale_inv => param_voltage_inv_forwardRateh1_scale_inv,
requirement_voltage_v => requirement_voltage_v,
Exposure_per_time_r => Exposure_per_time_forwardRateh1_r_internal,
derivedvariable_per_time_r_out => derivedvariable_per_time_forwardRateh1_r_out,
derivedvariable_per_time_r_in => derivedvariable_per_time_forwardRateh1_r_in,
sysparam_time_timestep => sysparam_time_timestep,
sysparam_time_simtime => sysparam_time_simtime
);
Exposure_per_time_forwardRateh1_r <= Exposure_per_time_forwardRateh1_r_internal;
reverseRateh1_uut : reverseRateh1
port map (
clk => clk,
init_model => init_model,
step_once_go => step_once_go,
Component_done => reverseRateh1_Component_done,
param_per_time_rate => param_per_time_reverseRateh1_rate,
param_voltage_midpoint => param_voltage_reverseRateh1_midpoint,
param_voltage_scale => param_voltage_reverseRateh1_scale,
param_voltage_inv_scale_inv => param_voltage_inv_reverseRateh1_scale_inv,
requirement_voltage_v => requirement_voltage_v,
Exposure_per_time_r => Exposure_per_time_reverseRateh1_r_internal,
derivedvariable_per_time_r_out => derivedvariable_per_time_reverseRateh1_r_out,
derivedvariable_per_time_r_in => derivedvariable_per_time_reverseRateh1_r_in,
sysparam_time_timestep => sysparam_time_timestep,
sysparam_time_simtime => sysparam_time_simtime
);
Exposure_per_time_reverseRateh1_r <= Exposure_per_time_reverseRateh1_r_internal;
derived_variable_pre_process_comb :process ( sysparam_time_timestep,exposure_per_time_forwardRateh1_r_internal,exposure_per_time_reverseRateh1_r_internal, param_none_instances, statevariable_none_q_in ,pow_fcond_power_result1, derivedvariable_per_time_alpha_next , derivedvariable_per_time_beta_next , derivedvariable_none_rateScale_next , derivedvariable_per_time_alpha_next , derivedvariable_per_time_beta_next )
begin
pre_pow_fcond_power_result1_A_next <= resize( statevariable_none_q_in ,18,-13);
pre_pow_fcond_power_result1_X_next <= resize( param_none_instances ,18,-13);
end process derived_variable_pre_process_comb;
derived_variable_pre_process_syn :process ( clk, init_model )
begin
if (clk'EVENT AND clk = '1') then
if init_model = '1' then
pre_pow_fcond_power_result1_A <= to_sfixed(0,18,-13);
pre_pow_fcond_power_result1_X <= to_sfixed(0,18,-13);
else
if subprocess_all_ready_shot = '1' then
pre_pow_fcond_power_result1_A <= pre_pow_fcond_power_result1_A_next ;
pre_pow_fcond_power_result1_X <= pre_pow_fcond_power_result1_X_next ;
end if;
end if;end if; subprocess_der_int_pre_ready <= '1';
end process derived_variable_pre_process_syn;
ParamPow_fcond_power_result1 : ParamPow
generic map(
BIT_TOP => 18,
BIT_BOTTOM => -13
)
port map ( clk => clk,
init_model => init_model,
Start => step_once_go,
Done => subprocess_der_int_ready,
X => pre_pow_fcond_power_result1_X ,
A => pre_pow_fcond_power_result1_A ,
Output => pow_fcond_power_result1
);
derived_variable_process_comb :process ( sysparam_time_timestep,exposure_per_time_forwardRateh1_r_internal,exposure_per_time_reverseRateh1_r_internal, param_none_instances, statevariable_none_q_in ,pow_fcond_power_result1, derivedvariable_per_time_alpha_next , derivedvariable_per_time_beta_next , derivedvariable_none_rateScale_next , derivedvariable_per_time_alpha_next , derivedvariable_per_time_beta_next )
begin
derivedvariable_per_time_alpha_next <= resize(( exposure_per_time_forwardRateh1_r_internal ),18,-2);
derivedvariable_per_time_beta_next <= resize(( exposure_per_time_reverseRateh1_r_internal ),18,-2);
derivedvariable_none_fcond_next <= resize((pow_fcond_power_result1),18,-13);
derivedvariable_none_inf_next <= resize(( derivedvariable_per_time_alpha_next / ( derivedvariable_per_time_alpha_next + derivedvariable_per_time_beta_next ) ),18,-13);
derivedvariable_time_tau_next <= resize(( to_sfixed ( 1 ,1 , -1 ) / ( ( derivedvariable_per_time_alpha_next + derivedvariable_per_time_beta_next ) ) ),6,-18);
end process derived_variable_process_comb;
uut_delayDone_derivedvariable_h : delayDone GENERIC MAP(
Steps => 2
)
PORT MAP(
clk => clk,
init_model => init_model,
Start => step_once_go,
Done => subprocess_der_ready
);
derived_variable_process_syn :process ( clk,init_model )
begin
if clk'event and clk = '1' then
if subprocess_all_ready_shot = '1' then
derivedvariable_per_time_alpha <= derivedvariable_per_time_alpha_next;
derivedvariable_per_time_beta <= derivedvariable_per_time_beta_next;
derivedvariable_none_fcond <= derivedvariable_none_fcond_next;
derivedvariable_none_inf <= derivedvariable_none_inf_next;
derivedvariable_time_tau <= derivedvariable_time_tau_next;
end if;
end if;
end process derived_variable_process_syn;
---------------------------------------------------------------------
dynamics_pre_process_comb :process ( sysparam_time_timestep, statevariable_none_q_in , derivedvariable_time_tau , derivedvariable_none_inf )
begin
end process dynamics_pre_process_comb;
dynamics_pre_process_syn :process ( clk, init_model )
begin
subprocess_dyn_int_pre_ready <= '1';
end process dynamics_pre_process_syn;
--No dynamics with complex equations found
subprocess_dyn_int_ready <= '1';
state_variable_process_dynamics_comb :process (sysparam_time_timestep, statevariable_none_q_in , derivedvariable_time_tau , derivedvariable_none_inf ,statevariable_none_q_in)
begin
statevariable_none_noregime_q_temp_1_next <= resize(statevariable_none_q_in + ( ( derivedvariable_none_inf - statevariable_none_q_in ) / derivedvariable_time_tau ) * sysparam_time_timestep,18,-13);
end process state_variable_process_dynamics_comb;
uut_delayDone_statevariable_h : delayDone GENERIC MAP(
Steps => 2
)
PORT MAP(
clk => clk,
init_model => init_model,
Start => step_once_go,
Done => subprocess_dyn_ready
);state_variable_process_dynamics_syn :process (CLK,init_model)
begin
if clk'event and clk = '1' then
if subprocess_all_ready_shot = '1' then
statevariable_none_noregime_q_temp_1 <= statevariable_none_noregime_q_temp_1_next;
end if;
end if;
end process state_variable_process_dynamics_syn;
------------------------------------------------------------------------------------------------------
-- EDState Variable Drivers
------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------
-- EDState variable: $par.name Driver Process
---------------------------------------------------------------------
state_variable_process_comb_0 :process (sysparam_time_timestep,init_model,derivedvariable_none_inf,statevariable_none_noregime_q_temp_1,statevariable_none_q_in,derivedvariable_time_tau,derivedvariable_none_inf)
variable statevariable_none_q_temp_1 : sfixed (18 downto -13);
begin
statevariable_none_q_temp_1 := statevariable_none_noregime_q_temp_1; statevariable_none_q_next <= statevariable_none_q_temp_1;
end process;
---------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign state variables to exposures
---------------------------------------------------------------------
exposure_none_q <= statevariable_none_q_in;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign state variables to output state variables
---------------------------------------------------------------------
statevariable_none_q_out <= statevariable_none_q_next;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign derived variables to exposures
---------------------------------------------------------------------
exposure_none_fcond <= derivedvariable_none_fcond_in;derivedvariable_none_fcond_out <= derivedvariable_none_fcond;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Subprocess ready process
---------------------------------------------------------------------
subprocess_all_ready_process: process(step_once_go,subprocess_der_int_ready,subprocess_der_int_pre_ready,subprocess_der_ready,subprocess_dyn_int_pre_ready,subprocess_dyn_int_ready,subprocess_dyn_ready,subprocess_model_ready)
begin
if step_once_go = '0' and subprocess_der_int_ready = '1' and subprocess_der_int_pre_ready = '1'and subprocess_der_ready ='1' and subprocess_dyn_int_ready = '1' and subprocess_dyn_int_pre_ready = '1' and subprocess_dyn_ready = '1' and subprocess_model_ready = '1' then
subprocess_all_ready <= '1';
else
subprocess_all_ready <= '0';
end if;
end process subprocess_all_ready_process;
subprocess_all_ready_shot_process : process(clk)
begin
if rising_edge(clk) then
if (init_model='1') then
subprocess_all_ready_shot <= '0';
subprocess_all_ready_shotdone <= '1';
else
if subprocess_all_ready = '1' and subprocess_all_ready_shotdone = '0' then
subprocess_all_ready_shot <= '1';
subprocess_all_ready_shotdone <= '1';
elsif subprocess_all_ready_shot = '1' then
subprocess_all_ready_shot <= '0';
elsif subprocess_all_ready = '0' then
subprocess_all_ready_shot <= '0';
subprocess_all_ready_shotdone <= '0';
end if;
end if;
end if;
end process subprocess_all_ready_shot_process;
---------------------------------------------------------------------
count_proc:process(clk)
begin
if (clk'EVENT AND clk = '1') then
if init_model = '1' then COUNT <= "001";
component_done_int <= '1';
else if step_once_go = '1' then
COUNT <= "000";
component_done_int <= '0';
elsif COUNT = "001" then
component_done_int <= '1';
elsif subprocess_all_ready_shot = '1' then
COUNT <= COUNT + 1;
component_done_int <= '0';
end if;
end if;
end if;
end process count_proc;
childrenCombined_component_done_process:process(forwardRateh1_component_done,reverseRateh1_component_done,CLK)
begin
if (forwardRateh1_component_done = '1' and reverseRateh1_component_done = '1') then
childrenCombined_component_done <= '1';
else
childrenCombined_component_done <= '0';
end if;
end process childrenCombined_component_done_process;
component_done <= component_done_int and childrenCombined_component_done;
end RTL;
| lgpl-3.0 | 7ea44015f2318b45ab9f5c06ad6e5724 | 0.604443 | 3.550785 | false | false | false | false |
kristofferkoch/ethersound | clocking.vhd | 1 | 3,884 | -----------------------------------------------------------------------------
-- Module for 50Mhz clock-generating on a Spartan 3 for hwpulse
--
-- Authors:
-- -- Kristoffer E. Koch
-----------------------------------------------------------------------------
-- Copyright 2008 Authors
--
-- This file is part of hwpulse.
--
-- hwpulse is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- hwpulse is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with hwpulse. If not, see <http://www.gnu.org/licenses/>.
-----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity clocking is
Port (
clk_in : in std_logic;
rst : in std_logic;
clk1x : out std_logic;
clk_div : out std_logic;
lock : out std_logic
);
end clocking;
architecture clocking_arch of clocking is
signal gnd, clk_div_w, clk0_w, clkdv_w, clk1x_w:std_logic;
signal lock_s:std_logic:='1';
begin
lock <= lock_s;
gnd <= '0';
clk_div <= clk_div_w;
clk1x <= clk1x_w;
DCM_inst : DCM_SP
generic map (
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => 4, -- Can be any Integer from 1 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => 20.0, -- Specify period of input clock
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
-- an Integer from 0 to 15
DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"C080", -- FACTORY JF Values
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM_SP LOCK, TRUE/FALSE
port map (
CLK0 => clk0_w, -- 0 degree DCM_SP CLK ouptput
CLK180 => open, -- 180 degree DCM_SP CLK output
CLK270 => open, -- 270 degree DCM_SP CLK output
CLK2X => open, -- 2X DCM_SP CLK output
CLK2X180 => open, -- 2X, 180 degree DCM_SP CLK out
CLK90 => open, -- 90 degree DCM_SP CLK output
CLKDV => clkdv_w, -- Divided DCM_SP CLK out (CLKDV_DIVIDE)
CLKFX => open, -- DCM_SP CLK synthesis out (M/D)
CLKFX180 => open, -- 180 degree CLK synthesis out
LOCKED => lock_s, -- DCM_SP LOCK status output
PSDONE => open, -- Dynamic phase adjust done output
STATUS => open, -- 8-bit DCM_SP status bits output
CLKFB => clk1x_w, -- DCM_SP clock feedback
CLKIN => clk_in, -- Clock input (from IBUFG, BUFG or DCM_SP)
PSCLK => gnd, -- Dynamic phase adjust clock input
PSEN => gnd, -- Dynamic phase adjust enable input
PSINCDEC => gnd, -- Dynamic phase adjust increment/decrement
RST => rst -- DCM_SP asynchronous reset input
);
u0_bufg: bufg
port map (
i => clk0_w,
o => clk1x_w
);
u1_bufg: bufg
port map (
i => clkdv_w,
o => clk_div_w
);
end clocking_arch;
| gpl-3.0 | e35d8f863aa6296f57c5285a47af321a | 0.607878 | 3.328192 | false | false | false | false |
hoglet67/AtomGodilVideo | src/DCM/DCMSID0.vhd | 1 | 2,128 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity DCMSID0 is
port (CLKIN_IN : in std_logic;
RST : in std_logic := '0';
CLK0_OUT : out std_logic;
CLK0_OUT1 : out std_logic;
CLK2X_OUT : out std_logic;
LOCKED : out std_logic
);
end DCMSID0;
architecture BEHAVIORAL of DCMSID0 is
signal CLKFX_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKFX_BUFG_INST : BUFG
port map (I => CLKFX_BUF, O => CLK0_OUT);
DCM_INST : DCM
generic map(CLK_FEEDBACK => "NONE",
CLKDV_DIVIDE => 4.0,
CLKFX_DIVIDE => 16,
CLKFX_MULTIPLY => 5,
CLKIN_DIVIDE_BY_2 => false,
CLKIN_PERIOD => 20.344,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => true,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => false)
port map (CLKFB => GND_BIT,
CLKIN => CLKIN_IN,
DSSEN => GND_BIT,
PSCLK => GND_BIT,
PSEN => GND_BIT,
PSINCDEC => GND_BIT,
RST => RST,
CLKDV => open,
CLKFX => CLKFX_BUF,
CLKFX180 => open,
CLK0 => open,
CLK2X => CLK2X_OUT,
CLK2X180 => open,
CLK90 => open,
CLK180 => open,
CLK270 => open,
LOCKED => LOCKED,
PSDONE => open,
STATUS => open);
end BEHAVIORAL;
| apache-2.0 | 13073bb5309e6c4d73ca11646fb118bb | 0.403195 | 4.307692 | false | false | false | false |
epall/Computer.Build | templates/program_counter.vhdl | 1 | 894 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY program_counter IS
GENERIC
(
DATA_WIDTH : integer := 8
);
PORT
(
clock : IN std_logic;
data_in : IN std_logic_vector(DATA_WIDTH - 1 DOWNTO 0);
data_out : OUT std_logic_vector(DATA_WIDTH - 1 DOWNTO 0);
wr : IN std_logic;
rd : IN std_logic;
inc : IN std_logic
);
END program_counter;
ARCHITECTURE rtl OF program_counter IS
SIGNAL regval : unsigned(DATA_WIDTH - 1 DOWNTO 0);
BEGIN
WITH rd SELECT
data_out <= std_logic_vector(regval) WHEN '1',
"ZZZZZZZZ" WHEN OTHERS;
PROCESS (clock)
BEGIN
IF clock'EVENT AND clock = '0' THEN
IF wr = '1' THEN
regval <= unsigned(data_in);
ELSIF inc = '1' THEN
regval <= regval + 1;
END IF;
END IF;
END PROCESS;
END rtl;
| mit | bdd66adc498f64000c1097dea49a2e47 | 0.572707 | 3.348315 | false | false | false | false |
Wynjones1/VHDL-Build | example/text_display/vga.vhd | 1 | 3,628 | library IEEE;
use IEEE.numeric_std.all;
use IEEE.std_logic_1164.all;
package vga_counter_comp is
type vga_counter_out_t is
record
sync : std_logic;
enable : std_logic;
pix : natural;
end record;
end package;
library IEEE;
use IEEE.numeric_std.all;
use IEEE.std_logic_1164.all;
use work.vga_counter_comp.all;
entity vga_counter is
generic(FP : natural;
PW : natural;
DT : natural;
BP : natural);
port(clk : in std_logic;
reset : in std_logic;
output : out vga_counter_out_t);
end vga_counter;
architecture rtl of vga_counter is
constant COUNT_MAX : natural := FP + PW + DT + BP;
subtype counter_t is natural range 0 to COUNT_MAX - 1;
signal counter_s : counter_t;
signal counter_next_s : counter_t;
signal output_next_s : vga_counter_out_t;
begin
comb : process(counter_s)
begin
counter_next_s <= (counter_s + 1) mod COUNT_MAX;
if counter_s < DT then output_next_s <= ('1', '1', counter_s); -- Display Time
elsif counter_s < DT + FP then output_next_s <= ('1', '0', counter_s); -- Front Porch
elsif counter_s < DT + FP + PW then output_next_s <= ('0', '0', counter_s); -- Pulse Width
else output_next_s <= ('1', '0', counter_s); -- Back Porce
end if;
end process;
seq : process(clk, reset)
begin
if reset = '1' then
output <= ('1', '1', 0);
counter_s <= 0;
elsif rising_edge(clk) then
output <= output_next_s;
counter_s <= counter_next_s;
end if;
end process;
end rtl;
library IEEE;
use IEEE.numeric_std.all;
use IEEE.std_logic_1164.all;
package vga_comp is
subtype width_t is natural range 0 to 640 - 1;
subtype height_t is natural range 0 to 480 - 1;
type vga_out_t is
record
en : std_logic;
hs : std_logic;
vs : std_logic;
pix_x : width_t;
pix_y : height_t;
end record;
end package;
library IEEE;
use IEEE.numeric_std.all;
use IEEE.std_logic_1164.all;
use work.vga_comp.all;
use work.vga_counter_comp.all;
entity vga is
port(clk : in std_logic;
reset : in std_logic;
output : out vga_out_t);
end vga;
architecture rtl of vga is
component vga_counter is
generic(FP : natural;
PW : natural;
DT : natural;
BP : natural);
port(clk : in std_logic;
reset : in std_logic;
output : out vga_counter_out_t);
end component;
signal h_counter_out_s : vga_counter_out_t;
signal v_counter_out_s : vga_counter_out_t;
begin
HS_counter : vga_counter
generic map (16, 96, 640, 48)
port map (clk, reset, h_counter_out_s);
VS_counter : vga_counter
generic map (10, 2, 480, 29)
port map (h_counter_out_s.sync, reset, v_counter_out_s);
comb: process(h_counter_out_s, v_counter_out_s)
begin
output.en <= h_counter_out_s.enable and v_counter_out_s.enable;
output.hs <= h_counter_out_s.sync;
output.vs <= v_counter_out_s.sync;
if h_counter_out_s.pix < 640 then
output.pix_x <= h_counter_out_s.pix;
else
output.pix_x <= 0;
end if;
if v_counter_out_s.pix < 480 then
output.pix_y <= v_counter_out_s.pix;
else
output.pix_y <= 0;
end if;
end process;
end rtl;
| mit | cf8d6c53304c18863b756521434bd293 | 0.54548 | 3.343779 | false | false | false | false |
FinnK/lems2hdl | work/N3_pointCellCondBased/ISIM_output/synapsemodel.vhdl | 1 | 11,618 |
---------------------------------------------------------------------
-- Standard Library bits
---------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- For Modelsim
--use ieee.fixed_pkg.all;
--use ieee.fixed_float_types.ALL;
-- For ISE
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use ieee_proposed.fixed_float_types.ALL;
use IEEE.numeric_std.all;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Entity Description
---------------------------------------------------------------------
entity synapsemodel is
Port (
clk : in STD_LOGIC; --SYSTEM CLOCK, THIS ITSELF DOES NOT SIGNIFY TIME STEPS - AKA A SINGLE TIMESTEP MAY TAKE MANY CLOCK CYCLES
init_model : in STD_LOGIC; --SYNCHRONOUS RESET
step_once_go : in STD_LOGIC; --signals to the neuron from the core that a time step is to be simulated
component_done : out STD_LOGIC;
eventport_in_in : in STD_LOGIC;
requirement_voltage_v : in sfixed (2 downto -22);
param_time_tauDecay : in sfixed (6 downto -18);
param_conductance_gbase : in sfixed (-22 downto -53);
param_voltage_erev : in sfixed (2 downto -22);
param_time_inv_tauDecay_inv : in sfixed (18 downto -6);
exposure_current_i : out sfixed (-28 downto -53);
exposure_conductance_g : out sfixed (-22 downto -53);
statevariable_conductance_g_out : out sfixed (-22 downto -53);
statevariable_conductance_g_in : in sfixed (-22 downto -53);
derivedvariable_current_i_out : out sfixed (-28 downto -53);
derivedvariable_current_i_in : in sfixed (-28 downto -53);
sysparam_time_timestep : in sfixed (-6 downto -22);
sysparam_time_simtime : in sfixed (6 downto -22)
);
end synapsemodel;
---------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-- Architecture Begins
-------------------------------------------------------------------------------------------
architecture RTL of synapsemodel is
signal COUNT : unsigned(2 downto 0) := "000";
signal childrenCombined_Component_done_single_shot_fired : STD_LOGIC := '0';
signal childrenCombined_Component_done_single_shot : STD_LOGIC := '0';
signal childrenCombined_Component_done : STD_LOGIC := '0';
signal Component_done_int : STD_LOGIC := '0';
signal subprocess_der_int_pre_ready : STD_LOGIC := '0';
signal subprocess_der_int_ready : STD_LOGIC := '0';
signal subprocess_der_ready : STD_LOGIC := '0';
signal subprocess_dyn_int_pre_ready : STD_LOGIC := '0';
signal subprocess_dyn_int_ready : STD_LOGIC := '0';
signal subprocess_dyn_ready : STD_LOGIC := '0';
signal subprocess_model_ready : STD_LOGIC := '1';
signal subprocess_all_ready_shotdone : STD_LOGIC := '1';
signal subprocess_all_ready_shot : STD_LOGIC := '0';
signal subprocess_all_ready : STD_LOGIC := '0';signal statevariable_conductance_noregime_g_temp_1 : sfixed (-22 downto -53);
signal statevariable_conductance_noregime_g_temp_1_next : sfixed (-22 downto -53);
---------------------------------------------------------------------
-- Derived Variables and parameters
---------------------------------------------------------------------
signal DerivedVariable_current_i : sfixed (-28 downto -53) := to_sfixed(0.0 ,-28,-53);
signal DerivedVariable_current_i_next : sfixed (-28 downto -53) := to_sfixed(0.0 ,-28,-53);
---------------------------------------------------------------------
---------------------------------------------------------------------
-- EDState internal Variables
---------------------------------------------------------------------
signal statevariable_conductance_g_next : sfixed (-22 downto -53);
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Output Port internal Variables
---------------------------------------------------------------------
signal EventPort_in_in_internal : std_logic := '0';
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Child Components
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Begin Internal Processes
---------------------------------------------------------------------
begin
---------------------------------------------------------------------
-- Child EDComponent Instantiations and corresponding internal variables
---------------------------------------------------------------------
derived_variable_pre_process_comb :process ( sysparam_time_timestep, statevariable_conductance_g_in , requirement_voltage_v , param_voltage_erev )
begin
end process derived_variable_pre_process_comb;
derived_variable_pre_process_syn :process ( clk, init_model )
begin
subprocess_der_int_pre_ready <= '1';
end process derived_variable_pre_process_syn;
--no complex steps in derived variables
subprocess_der_int_ready <= '1';
derived_variable_process_comb :process ( sysparam_time_timestep, statevariable_conductance_g_in , requirement_voltage_v , param_voltage_erev )
begin
derivedvariable_current_i_next <= resize(( statevariable_conductance_g_in * ( param_voltage_erev - requirement_voltage_v ) ),-28,-53);
subprocess_der_ready <= '1';
end process derived_variable_process_comb;
derived_variable_process_syn :process ( clk,init_model )
begin
if clk'event and clk = '1' then
if subprocess_all_ready_shot = '1' then
derivedvariable_current_i <= derivedvariable_current_i_next;
end if;
end if;
end process derived_variable_process_syn;
---------------------------------------------------------------------
dynamics_pre_process_comb :process ( sysparam_time_timestep, param_time_tauDecay, statevariable_conductance_g_in ,param_time_inv_tauDecay_inv )
begin
end process dynamics_pre_process_comb;
dynamics_pre_process_syn :process ( clk, init_model )
begin
subprocess_dyn_int_pre_ready <= '1';
end process dynamics_pre_process_syn;
--No dynamics with complex equations found
subprocess_dyn_int_ready <= '1';
state_variable_process_dynamics_comb :process (sysparam_time_timestep, param_time_tauDecay, statevariable_conductance_g_in ,param_time_inv_tauDecay_inv ,statevariable_conductance_g_in)
begin
statevariable_conductance_noregime_g_temp_1_next <= resize(statevariable_conductance_g_in + ( - statevariable_conductance_g_in * param_time_inv_tauDecay_inv ) * sysparam_time_timestep,-22,-53);
subprocess_dyn_ready <= '1';
end process state_variable_process_dynamics_comb;
state_variable_process_dynamics_syn :process (CLK,init_model)
begin
if clk'event and clk = '1' then
if subprocess_all_ready_shot = '1' then
statevariable_conductance_noregime_g_temp_1 <= statevariable_conductance_noregime_g_temp_1_next;
end if;
end if;
end process state_variable_process_dynamics_syn;
------------------------------------------------------------------------------------------------------
-- EDState Variable Drivers
------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------
-- EDState variable: $par.name Driver Process
---------------------------------------------------------------------
state_variable_process_comb_0 :process (sysparam_time_timestep,init_model,eventport_in_in,statevariable_conductance_g_in,param_conductance_gbase,statevariable_conductance_noregime_g_temp_1,param_time_tauDecay,statevariable_conductance_g_in,param_time_inv_tauDecay_inv)
variable statevariable_conductance_g_temp_1 : sfixed (-22 downto -53);
variable statevariable_conductance_g_temp_2 : sfixed (-22 downto -53);
begin
statevariable_conductance_g_temp_1 := statevariable_conductance_noregime_g_temp_1; if eventport_in_in = '1' then
statevariable_conductance_g_temp_2 := resize( statevariable_conductance_g_in + param_conductance_gbase ,-22,-53);
else
statevariable_conductance_g_temp_2 := statevariable_conductance_g_temp_1;
end if;
statevariable_conductance_g_next <= statevariable_conductance_g_temp_2;
end process;
---------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign state variables to exposures
---------------------------------------------------------------------
exposure_conductance_g <= statevariable_conductance_g_in;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign state variables to output state variables
---------------------------------------------------------------------
statevariable_conductance_g_out <= statevariable_conductance_g_next;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign derived variables to exposures
---------------------------------------------------------------------
exposure_current_i <= derivedvariable_current_i_in;derivedvariable_current_i_out <= derivedvariable_current_i;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Subprocess ready process
---------------------------------------------------------------------
subprocess_all_ready_process: process(step_once_go,subprocess_der_int_ready,subprocess_der_int_pre_ready,subprocess_der_ready,subprocess_dyn_int_pre_ready,subprocess_dyn_int_ready,subprocess_dyn_ready,subprocess_model_ready)
begin
if step_once_go = '0' and subprocess_der_int_ready = '1' and subprocess_der_int_pre_ready = '1'and subprocess_der_ready ='1' and subprocess_dyn_int_ready = '1' and subprocess_dyn_int_pre_ready = '1' and subprocess_dyn_ready = '1' and subprocess_model_ready = '1' then
subprocess_all_ready <= '1';
else
subprocess_all_ready <= '0';
end if;
end process subprocess_all_ready_process;
subprocess_all_ready_shot_process : process(clk)
begin
if rising_edge(clk) then
if (init_model='1') then
subprocess_all_ready_shot <= '0';
subprocess_all_ready_shotdone <= '1';
else
if subprocess_all_ready = '1' and subprocess_all_ready_shotdone = '0' then
subprocess_all_ready_shot <= '1';
subprocess_all_ready_shotdone <= '1';
elsif subprocess_all_ready_shot = '1' then
subprocess_all_ready_shot <= '0';
elsif subprocess_all_ready = '0' then
subprocess_all_ready_shot <= '0';
subprocess_all_ready_shotdone <= '0';
end if;
end if;
end if;
end process subprocess_all_ready_shot_process;
---------------------------------------------------------------------
count_proc:process(clk)
begin
if (clk'EVENT AND clk = '1') then
if init_model = '1' then COUNT <= "001";
component_done_int <= '1';
else if step_once_go = '1' then
COUNT <= "000";
component_done_int <= '0';
elsif COUNT = "001" then
component_done_int <= '1';
elsif subprocess_all_ready_shot = '1' then
COUNT <= COUNT + 1;
component_done_int <= '0';
end if;
end if;
end if;
end process count_proc;
component_done <= component_done_int;
end RTL;
| lgpl-3.0 | 3f27460a6bb1c634001d56bea2c857ba | 0.525994 | 4.093728 | false | false | false | false |
hoglet67/AtomGodilVideo | src/TopRoland.vhd | 1 | 13,323 | ---------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:42:09 02/09/2013
-- Design Name:
-- Module Name: Top - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity TopRoland is
port (
-- Standard 6847 signals
--
-- expept DA which is now input only
-- except nRP which re-purposed as a nWR
DD : inout std_logic_vector (7 downto 0);
DA : in std_logic_vector (12 downto 0);
nMS : in std_logic;
CSS : in std_logic;
nFS : out std_logic;
nWR : in std_logic; -- Was nRP
AG : in std_logic;
GM : in std_logic_vector (2 downto 0);
-- 5 bit VGA Output
R : out std_logic_vector (0 downto 0);
G : out std_logic_vector (1 downto 0);
B : out std_logic_vector (0 downto 0);
HSYNC : out std_logic;
VSYNC : out std_logic;
-- 1 bit AUDIO Output
AUDIO : out std_logic;
-- Other GODIL specific pins
clock49 : in std_logic;
nRST : in std_logic;
nBXXX : in std_logic;
-- Jumpers
-- Enabled SID Audio
SIDEN : in std_logic;
-- Moves SID from 9FE0 to BDC0
nSIDD : in std_logic;
-- charSet
charSet : in std_logic;
-- Active low version of the SID Select Signal for disabling the external bus buffers
-- nSIDSEL : out std_logic;
-- PS/2 Mouse
PS2_CLK : inout std_logic;
PS2_DATA : inout std_logic;
-- UART
uart_TxD : out std_logic;
uart_RxD : in std_logic;
-- LEDs
led8 : out std_logic;
-- MISC
CSO_B : out std_logic
);
end TopRoland;
architecture BEHAVIORAL of TopRoland is
-- clock32 is the main clock
signal clock32 : std_logic;
-- clock25 is a full speed VGA clock
signal clock25 : std_logic;
-- clock15 is just used between two DCMs
signal clock15 : std_logic;
-- clock59 is just used between two DCMs
signal clock59 : std_logic;
-- Reset signal (active high)
signal reset : std_logic;
-- Reset signal to 6847 (active high), not currently used
signal reset_vid : std_logic;
-- pipelined versions of the address/data/write signals
signal nWR1 : std_logic;
signal nWR2 : std_logic;
signal nMS1 : std_logic;
signal nMS2 : std_logic;
signal nWRMS1 : std_logic;
signal nWRMS2 : std_logic;
signal nBXXX1 : std_logic;
signal nBXXX2 : std_logic;
signal DA1 : std_logic_vector (12 downto 0);
signal DA2 : std_logic_vector (12 downto 0);
signal DD1 : std_logic_vector (7 downto 0);
signal DD2 : std_logic_vector (7 downto 0);
signal DD3 : std_logic_vector (7 downto 0);
signal ram_we : std_logic;
signal addr : std_logic_vector (12 downto 0);
signal din : std_logic_vector (7 downto 0);
-- Dout back to the Atom, that is either VRAM or SID
signal dout : std_logic_vector (7 downto 0);
-- SID sigmals
signal sid_cs : std_logic;
signal sid_we : std_logic;
signal sid_audio : std_logic;
-- UART sigmals
signal uart_cs : std_logic;
signal uart_we : std_logic;
-- Atom extension register signals
signal reg_cs : std_logic;
signal reg_we : std_logic;
signal final_red : std_logic;
signal final_green1 : std_logic;
signal final_green0 : std_logic;
signal final_blue : std_logic;
signal final_vsync : std_logic;
signal final_hsync : std_logic;
signal final_blank : std_logic;
signal final_char_a : std_logic_vector (10 downto 0);
signal locked1 : std_logic;
signal locked2 : std_logic;
signal locked3 : std_logic;
signal locked4 : std_logic;
-- Palette Signals
signal palette_cs : std_logic; -- enable for #BD0x
-- Colour palette registers
signal palette_data : std_logic_vector(7 downto 0);
signal logical_colour : std_logic_vector(3 downto 0);
signal physical_colour : std_logic_vector(5 downto 0);
type palette_type is array (0 to 15) of std_logic_vector(5 downto 0);
signal palette : palette_type := (
0 => "000000",
1 => "000011",
2 => "000100",
3 => "000111",
4 => "001000",
5 => "001011",
6 => "001100",
7 => "001111",
8 => "110000",
9 => "110011",
10 => "110100",
11 => "110111",
12 => "111000",
13 => "111011",
14 => "111100",
15 => "111111"
);
begin
reset <= not nRST;
reset_vid <= '0';
-- Currently set at 49.152 * (31/26) * (3/7) = 25.1161318637MHz
Inst_DCM1 : entity work.DCM1
port map (
CLKIN_IN => clock49,
RST => '0',
CLK0_OUT => clock59,
CLK0_OUT1 => open,
CLK2X_OUT => open,
LOCKED => locked1
);
Inst_DCM2 : entity work.DCM2
port map (
CLKIN_IN => clock59,
RST => not locked1,
CLK0_OUT => clock25,
CLK0_OUT1 => open,
CLK2X_OUT => open,
LOCKED => locked2
);
Inst_DCM3 : entity work.DCMSID0
port map (
CLKIN_IN => clock49,
RST => '0',
CLK0_OUT => clock15,
CLK0_OUT1 => open,
CLK2X_OUT => open,
LOCKED => locked3
);
Inst_DCM4 : entity work.DCMSID1
port map (
CLKIN_IN => clock15,
RST => not locked3,
CLK0_OUT => clock32,
CLK0_OUT1 => open,
CLK2X_OUT => open,
LOCKED => locked4
);
led8 <= not (locked1 and locked2 and locked3 and locked4);
Inst_AtomGodilVideo : entity work.AtomGodilVideo
generic map (
CImplGraphicsExt => true,
CImplSoftChar => true,
CImplSID => true,
CImplVGA80x40 => true,
CImplHWScrolling => true,
CImplMouse => true,
CImplUart => true,
CImplDoubleVideo => true,
MainClockSpeed => 32000000,
DefaultBaud => 115200
)
port map (
clock_vga => clock25,
clock_main => clock32,
clock_sid_32Mhz => clock32,
clock_sid_dac => clock49,
reset => reset,
reset_vid => reset_vid,
din => din,
dout => dout,
addr => addr,
CSS => CSS,
AG => AG,
GM => GM,
nFS => nFS,
ram_we => ram_we,
reg_cs => reg_cs,
reg_we => reg_we,
sid_cs => sid_cs,
sid_we => sid_we,
sid_audio => sid_audio,
sid_audio_d => open,
PS2_CLK => PS2_CLK,
PS2_DATA => PS2_DATA,
uart_cs => uart_cs,
uart_we => uart_we,
uart_RxD => uart_RxD,
uart_TxD => uart_TxD,
uart_escape => open,
uart_break => open,
final_red => final_red,
final_green1 => final_green1,
final_green0 => final_green0,
final_blue => final_blue,
final_vsync => final_vsync,
final_hsync => final_hsync,
final_blank => final_blank,
charSet => charSet
);
-- Pipelined version of address/data/write signals
process (clock32)
begin
if rising_edge(clock32) then
nBXXX2 <= nBXXX1;
nBXXX1 <= nBXXX;
nMS2 <= nMS1;
nMS1 <= nMS;
nWRMS2 <= nWRMS1;
nWRMS1 <= nWR or nMS;
nWR2 <= nWR1;
nWR1 <= nWR;
DD3 <= DD2;
DD2 <= DD1;
DD1 <= DD;
DA2 <= DA1;
DA1 <= DA;
end if;
end process;
-- Signals driving the VRAM
-- Write just before the rising edge of nWR
ram_we <= '1' when (nWRMS1 = '1' and nWRMS2 = '0' and nBXXX2 = '1') else '0';
din <= DD2;
addr <= DA2;
-- Signals driving the internal registers
-- When nSIDD=0 the registers are mapped to BDE0-BDFF
-- When nSIDD=1 the registers are mapped to 9FE0-9FFF
reg_cs <= '1' when (nSIDD = '1' and nMS2 = '0' and DA2(12 downto 5) = "11111111") or
(nSIDD = '0' and nBXXX2 = '0' and DA2(11 downto 5) = "1101111")
else '0';
reg_we <= '1' when (nSIDD = '1' and nWRMS1 = '1' and nWRMS2 = '0') or
(nSIDD = '0' and nWR1 = '1' and nWR2 = '0')
else '0';
-- Signals driving the SID
-- When nSIDD=0 the SID is mapped to BDC0-BDDF
-- When nSIDD=1 the SID is mapped to 9FC0-9FDF
sid_cs <= '1' when (nSIDD = '1' and nMS2 = '0' and DA2(12 downto 5) = "11111110") or
(nSIDD = '0' and nBXXX2 = '0' and DA2(11 downto 5) = "1101110")
else '0';
sid_we <= '1' when (nSIDD = '1' and nWRMS1 = '1' and nWRMS2 = '0') or
(nSIDD = '0' and nWR1 = '1' and nWR2 = '0')
else '0';
-- Signals driving the UART
-- When nSIDD=0 the UART is mapped to BDB0-BDBF
-- When nSIDD=1 the UART is mapped to 9FB0-9FBF
uart_cs <= '1' when (nSIDD = '1' and nMS2 = '0' and DA2(12 downto 4) = "111111011") or
(nSIDD = '0' and nBXXX2 = '0' and DA2(11 downto 4) = "11011011")
else '0';
uart_we <= '1' when (nSIDD = '1' and nWRMS1 = '1' and nWRMS2 = '0') or
(nSIDD = '0' and nWR1 = '1' and nWR2 = '0')
else '0';
AUDIO <= sid_audio when SIDEN = '1' else '0';
-- Output the SID Select Signal so it can be used to disable the bus buffers
-- TODO: this looks incorrect
-- nSIDSEL <= not sid_cs;
-- Tri-state data back to the Atom
DD <= palette_data when nMS = '0' and nWR = '1' and palette_cs = '1' else
dout when nMS = '0' and nWR = '1' and palette_cs = '0' else
(others => 'Z');
CSO_B <= '1';
--------------------------------------------------------
-- Colour palette control
--------------------------------------------------------
palette_cs <= '1' when nBXXX2 = '0' and DA2(11 downto 4) = x"D0" else '0';
process (clock32)
begin
if rising_edge(clock32) then
if nRST = '0' then
-- initializing like this mean the palette will be
-- implemented with LUTs rather than as a block RAM
palette(0) <= "000000";
palette(1) <= "000011";
palette(2) <= "000100";
palette(3) <= "000111";
palette(4) <= "001000";
palette(5) <= "001011";
palette(6) <= "001100";
palette(7) <= "001111";
palette(8) <= "110000";
palette(9) <= "110011";
palette(10) <= "110100";
palette(11) <= "110111";
palette(12) <= "111000";
palette(13) <= "111011";
palette(14) <= "111100";
palette(15) <= "111111";
else
-- write colour palette registers
if palette_cs = '1' and nWR1 = '1' and nWR2 = '0' then
palette(conv_integer(DA2(3 downto 0))) <= DD2(7 downto 2);
end if;
end if;
end if;
end process;
logical_colour <= final_red & final_green1 & final_green0 & final_blue;
-- Making this a synchronous process should improve the timing
-- and potentially make the pixels more defined
process (clock25)
begin
if rising_edge(clock25) then
if final_blank = '1' then
physical_colour <= (others => '0');
else
physical_colour <= palette(conv_integer(logical_colour));
end if;
-- Also register hsync/vsync so they are correctly
-- aligned with the colour changes
HSYNC <= final_hsync;
VSYNC <= final_vsync;
end if;
end process;
-- Use the same bits as AtomFpga_Atom2K18, ignoring bits 4 and 0
R(0) <= physical_colour(5);
G(1) <= physical_colour(3);
G(0) <= physical_colour(2);
B(0) <= physical_colour(1);
palette_data <= palette(conv_integer(DA2(3 downto 0))) & "00";
end BEHAVIORAL;
| apache-2.0 | e7fcd780ea9c96f636d5b5b485cff07a | 0.498086 | 3.70495 | false | false | false | false |
FinnK/lems2hdl | work/N1_iafRefCell/ISIM_output/neuron_model.vhdl | 1 | 22,290 |
---------------------------------------------------------------------
-- Standard Library bits
---------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- For Modelsim
--use ieee.fixed_pkg.all;
--use ieee.fixed_float_types.ALL;
-- For ISE
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use ieee_proposed.fixed_float_types.ALL;
use IEEE.numeric_std.all;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Entity Description
---------------------------------------------------------------------
entity neuron_model is
Port (
clk : in STD_LOGIC; --SYSTEM CLOCK, THIS ITSELF DOES NOT SIGNIFY TIME STEPS - AKA A SINGLE TIMESTEP MAY TAKE MANY CLOCK CYCLES
init_model : in STD_LOGIC; --SYNCHRONOUS RESET
step_once_go : in STD_LOGIC; --signals to the neuron from the core that a time step is to be simulated
step_once_complete : out STD_LOGIC; --signals to the core that a time step has finished
eventport_in_spike_aggregate : in STD_LOGIC_VECTOR(511 downto 0);
current_regime_in_stdlv : in STD_LOGIC_VECTOR(1 downto 0);
current_regime_out_stdlv : out STD_LOGIC_VECTOR(1 downto 0);
eventport_out_spike : out STD_LOGIC;
param_time_refract : in sfixed (6 downto -18);
param_conductance_leakConductance : in sfixed (-22 downto -53);
param_voltage_leakReversal : in sfixed (2 downto -22);
param_voltage_thresh : in sfixed (2 downto -22);
param_voltage_reset : in sfixed (2 downto -22);
param_capacitance_C : in sfixed (-33 downto -47);
param_capacitance_inv_C_inv : in sfixed (47 downto 33);
exposure_voltage_v : out sfixed (2 downto -22);
statevariable_voltage_v_out : out sfixed (2 downto -22);
statevariable_voltage_v_in : in sfixed (2 downto -22);
statevariable_time_lastSpikeTime_out : out sfixed (6 downto -18);
statevariable_time_lastSpikeTime_in : in sfixed (6 downto -18);
param_time_SynapseModel_tauDecay : in sfixed (6 downto -18);
param_conductance_SynapseModel_gbase : in sfixed (-22 downto -53);
param_voltage_SynapseModel_erev : in sfixed (2 downto -22);
param_time_inv_SynapseModel_tauDecay_inv : in sfixed (18 downto -6);
exposure_current_SynapseModel_i : out sfixed (-28 downto -53);
exposure_conductance_SynapseModel_g : out sfixed (-22 downto -53);
statevariable_conductance_SynapseModel_g_out : out sfixed (-22 downto -53);
statevariable_conductance_SynapseModel_g_in : in sfixed (-22 downto -53);
derivedvariable_current_SynapseModel_i_out : out sfixed (-28 downto -53);
derivedvariable_current_SynapseModel_i_in : in sfixed (-28 downto -53);
sysparam_time_timestep : in sfixed (-6 downto -22);
sysparam_time_simtime : in sfixed (6 downto -22)
);
end neuron_model;
---------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-- Architecture Begins
-------------------------------------------------------------------------------------------
architecture RTL of neuron_model is
signal COUNT : unsigned(2 downto 0) := "000";
signal childrenCombined_Component_done_single_shot_fired : STD_LOGIC := '0';
signal childrenCombined_Component_done_single_shot : STD_LOGIC := '0';
signal childrenCombined_Component_done : STD_LOGIC := '0';
signal Component_done_int : STD_LOGIC := '0';
signal subprocess_der_int_pre_ready : STD_LOGIC := '0';
signal subprocess_der_int_ready : STD_LOGIC := '0';
signal subprocess_der_ready : STD_LOGIC := '0';
signal subprocess_dyn_int_pre_ready : STD_LOGIC := '0';
signal subprocess_dyn_int_ready : STD_LOGIC := '0';
signal subprocess_dyn_ready : STD_LOGIC := '0';
signal subprocess_model_ready : STD_LOGIC := '1';
signal subprocess_all_ready_shotdone : STD_LOGIC := '1';
signal subprocess_all_ready_shot : STD_LOGIC := '0';
signal subprocess_all_ready : STD_LOGIC := '0';signal SynapseModel_step_once_complete_fired : STD_LOGIC := '1';
signal step_once_complete_fired : STD_LOGIC := '1';
signal Component_done : STD_LOGIC := '0';
constant cNSpikeSources : integer := 512; -- The number of spike sources.
constant cNOutputs : integer := 512; -- The number of Synapses in the neuron model.
constant cNSelectBits : integer := 9; -- Log2(NOutputs), rounded up.
signal SpikeOut : Std_logic_vector((cNOutputs-1) downto 0);
signal statevariable_voltage_integrating_v_temp_1 : sfixed (2 downto -22);
signal statevariable_voltage_integrating_v_temp_1_next : sfixed (2 downto -22);
---------------------------------------------------------------------
-- Derived Variables and parameters
---------------------------------------------------------------------
signal DerivedVariable_current_iSyn : sfixed (-28 downto -53) := to_sfixed(0.0 ,-28,-53);
signal DerivedVariable_current_iSyn_next : sfixed (-28 downto -53) := to_sfixed(0.0 ,-28,-53);
signal DerivedVariable_current_iMemb : sfixed (-28 downto -53) := to_sfixed(0.0 ,-28,-53);
signal DerivedVariable_current_iMemb_next : sfixed (-28 downto -53) := to_sfixed(0.0 ,-28,-53);
---------------------------------------------------------------------
---------------------------------------------------------------------
-- EDState internal Variables
---------------------------------------------------------------------
signal statevariable_voltage_v_next : sfixed (2 downto -22);
signal statevariable_time_lastSpikeTime_next : sfixed (6 downto -18);
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Output Port internal Variables
---------------------------------------------------------------------
signal EventPort_out_spike_internal : std_logic := '0';
---------------------------------------------------------------------
type regime_type is (refractory,integrating);
signal current_regime_in_int: regime_type;
signal next_regime: regime_type;
function CONV_STDLV_TO_REGIME (DATA :std_logic_vector) return regime_type is
begin
return regime_type'val(to_integer(unsigned(DATA)));
end CONV_STDLV_TO_REGIME;
function CONV_REGIME_TO_STDLV (regime :regime_type) return std_logic_vector is
begin
return std_logic_vector(to_unsigned(regime_type'pos(regime),2));
end CONV_REGIME_TO_STDLV;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Child Components
---------------------------------------------------------------------
component SynapseModel
Port (
clk : in STD_LOGIC; --SYSTEM CLOCK, THIS ITSELF DOES NOT SIGNIFY TIME STEPS - AKA A SINGLE TIMESTEP MAY TAKE MANY CLOCK CYCLES
init_model : in STD_LOGIC;
step_once_go : in STD_LOGIC; --signals to the neuron from the core that a time step is to be simulated
Component_done : out STD_LOGIC;
eventport_in_in : in STD_LOGIC;
requirement_voltage_v : in sfixed (2 downto -22);
param_time_tauDecay : in sfixed (6 downto -18);
param_conductance_gbase : in sfixed (-22 downto -53);
param_voltage_erev : in sfixed (2 downto -22);
param_time_inv_tauDecay_inv : in sfixed (18 downto -6);
exposure_current_i : out sfixed (-28 downto -53);
exposure_conductance_g : out sfixed (-22 downto -53);
statevariable_conductance_g_out : out sfixed (-22 downto -53);
statevariable_conductance_g_in : in sfixed (-22 downto -53);
derivedvariable_current_i_out : out sfixed (-28 downto -53);
derivedvariable_current_i_in : in sfixed (-28 downto -53);
sysparam_time_timestep : in sfixed (-6 downto -22);
sysparam_time_simtime : in sfixed (6 downto -22)
);
end component;
signal SynapseModel_Component_done : STD_LOGIC ; signal Exposure_current_SynapseModel_i_internal : sfixed (-28 downto -53);
signal Exposure_conductance_SynapseModel_g_internal : sfixed (-22 downto -53);
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Begin Internal Processes
---------------------------------------------------------------------
begin
---------------------------------------------------------------------
-- Child EDComponent Instantiations and corresponding internal variables
---------------------------------------------------------------------
SynapseModel_uut : SynapseModel
port map (
clk => clk,
init_model => init_model,
step_once_go => step_once_go,
Component_done => SynapseModel_Component_done,
eventport_in_in => EventPort_in_spike_aggregate(0),
param_time_tauDecay => param_time_SynapseModel_tauDecay,
param_conductance_gbase => param_conductance_SynapseModel_gbase,
param_voltage_erev => param_voltage_SynapseModel_erev,
param_time_inv_tauDecay_inv => param_time_inv_SynapseModel_tauDecay_inv,
requirement_voltage_v => statevariable_voltage_v_in,
Exposure_current_i => Exposure_current_SynapseModel_i_internal,
Exposure_conductance_g => Exposure_conductance_SynapseModel_g_internal,
statevariable_conductance_g_out => statevariable_conductance_SynapseModel_g_out,
statevariable_conductance_g_in => statevariable_conductance_SynapseModel_g_in,
derivedvariable_current_i_out => derivedvariable_current_SynapseModel_i_out,
derivedvariable_current_i_in => derivedvariable_current_SynapseModel_i_in,
sysparam_time_timestep => sysparam_time_timestep,
sysparam_time_simtime => sysparam_time_simtime
);
Exposure_current_SynapseModel_i <= Exposure_current_SynapseModel_i_internal;
Exposure_conductance_SynapseModel_g <= Exposure_conductance_SynapseModel_g_internal;
derived_variable_pre_process_comb :process ( sysparam_time_timestep,exposure_current_SynapseModel_i_internal, param_conductance_leakConductance, param_voltage_leakReversal, statevariable_voltage_v_in , derivedvariable_current_iSyn_next )
begin
end process derived_variable_pre_process_comb;
derived_variable_pre_process_syn :process ( clk, init_model )
begin
subprocess_der_int_pre_ready <= '1';
end process derived_variable_pre_process_syn;
--no complex steps in derived variables
subprocess_der_int_ready <= '1';
derived_variable_process_comb :process ( sysparam_time_timestep,exposure_current_SynapseModel_i_internal, param_conductance_leakConductance, param_voltage_leakReversal, statevariable_voltage_v_in , derivedvariable_current_iSyn_next )
begin
derivedvariable_current_iSyn_next <= resize(( exposure_current_SynapseModel_i_internal ),-28,-53);
derivedvariable_current_iMemb_next <= resize(( param_conductance_leakConductance * ( param_voltage_leakReversal - statevariable_voltage_v_in ) + derivedvariable_current_iSyn_next ),-28,-53);
subprocess_der_ready <= '1';
end process derived_variable_process_comb;
derived_variable_process_syn :process ( clk,init_model )
begin
if clk'event and clk = '1' then
if subprocess_all_ready_shot = '1' then
derivedvariable_current_iSyn <= derivedvariable_current_iSyn_next;
derivedvariable_current_iMemb <= derivedvariable_current_iMemb_next;
end if;
end if;
end process derived_variable_process_syn;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- EDRegime EDState Machine Process
---------------------------------------------------------------------
regime_state_process_comb :process (sysparam_time_simtime,current_regime_in_int,init_model,statevariable_voltage_v_in, statevariable_time_lastSpikeTime_in , param_time_refract, sysparam_time_simtime, param_voltage_thresh, statevariable_voltage_v_in )
begin
next_regime <= current_regime_in_int;
if init_model = '1' then
next_regime <= integrating;
else
if ( current_regime_in_int = refractory ) and To_slv ( resize (sysparam_time_simtime- ( statevariable_time_lastSpikeTime_in + param_time_refract ) ,2,-18))(20) = '0' then
next_regime <= integrating;
end if;
if ( current_regime_in_int = integrating ) and To_slv ( resize ( statevariable_voltage_v_in - ( param_voltage_thresh ) ,2,-18))(20) = '0' then
next_regime <= refractory;
end if;
end if;
end process;
current_regime_out_stdlv <= CONV_REGIME_TO_STDLV(next_regime);
current_regime_in_int <= CONV_STDLV_TO_REGIME(current_regime_in_stdlv);
---------------------------------------------------------------------
dynamics_pre_process_comb :process ( sysparam_time_timestep, derivedvariable_current_iMemb , param_capacitance_C,param_capacitance_inv_C_inv )
begin
end process dynamics_pre_process_comb;
dynamics_pre_process_syn :process ( clk, init_model )
begin
subprocess_dyn_int_pre_ready <= '1';
end process dynamics_pre_process_syn;
--No dynamics with complex equations found
subprocess_dyn_int_ready <= '1';
state_variable_process_dynamics_comb :process (sysparam_time_timestep, derivedvariable_current_iMemb , param_capacitance_C,param_capacitance_inv_C_inv ,statevariable_voltage_v_in)
begin
statevariable_voltage_integrating_v_temp_1_next <= resize(statevariable_voltage_v_in + ( derivedvariable_current_iMemb * param_capacitance_inv_C_inv ) * sysparam_time_timestep,2,-22);
subprocess_dyn_ready <= '1';
end process state_variable_process_dynamics_comb;
state_variable_process_dynamics_syn :process (CLK,init_model)
begin
if clk'event and clk = '1' then
if subprocess_all_ready_shot = '1' then
statevariable_voltage_integrating_v_temp_1 <= statevariable_voltage_integrating_v_temp_1_next;
end if;
end if;
end process state_variable_process_dynamics_syn;
------------------------------------------------------------------------------------------------------
-- EDState Variable Drivers
------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------
-- EDState variable: $par.name Driver Process
---------------------------------------------------------------------
state_variable_process_comb_0 :process (sysparam_time_timestep,init_model,param_voltage_reset,current_regime_in_int,next_regime,statevariable_voltage_integrating_v_temp_1,derivedvariable_current_iMemb,param_capacitance_C,param_capacitance_inv_C_inv)
variable statevariable_voltage_v_temp_1 : sfixed (2 downto -22);
variable statevariable_voltage_v_temp_2 : sfixed (2 downto -22);
begin
if ( current_regime_in_int = refractory ) then
statevariable_voltage_v_temp_1 := resize(statevariable_voltage_v_in ,2,-22);
end if;
if ( current_regime_in_int = integrating ) then
statevariable_voltage_v_temp_1 := statevariable_voltage_integrating_v_temp_1;
end if;
if (not ( current_regime_in_int = next_regime )) and ( next_regime = refractory ) then
statevariable_voltage_v_temp_2 := resize( param_voltage_reset ,2,-22);
else
statevariable_voltage_v_temp_2 := statevariable_voltage_v_temp_1;
end if;
if (not ( current_regime_in_int = next_regime )) and ( next_regime = integrating ) then
end if;
statevariable_voltage_v_next <= statevariable_voltage_v_temp_2;
end process;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- EDState variable: $par.name Driver Process
---------------------------------------------------------------------
state_variable_process_comb_1 :process (sysparam_time_timestep,init_model,current_regime_in_int,next_regime)
variable statevariable_time_lastSpikeTime_temp_1 : sfixed (6 downto -18);
begin
if ( current_regime_in_int = refractory ) then
statevariable_time_lastSpikeTime_temp_1 := resize(statevariable_time_lastSpikeTime_in ,6,-18);
end if;
if ( current_regime_in_int = integrating ) then
statevariable_time_lastSpikeTime_temp_1 := resize(statevariable_time_lastSpikeTime_in ,6,-18);
end if;
if (not ( current_regime_in_int = next_regime )) and ( next_regime = refractory ) then
statevariable_time_lastSpikeTime_temp_1 := resize(sysparam_time_simtime,6,-18);
else
statevariable_time_lastSpikeTime_temp_1 := statevariable_time_lastSpikeTime_in;
end if;
if (not ( current_regime_in_int = next_regime )) and ( next_regime = integrating ) then
end if;
statevariable_time_lastSpikeTime_next <= statevariable_time_lastSpikeTime_temp_1;
end process;
---------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
eventport_driver0 :process ( clk,sysparam_time_timestep,init_model, param_voltage_thresh, statevariable_voltage_v_in )
variable eventport_out_spike_temp_1 : std_logic;
variable eventport_out_spike_temp_2 : std_logic;
begin
if rising_edge(clk) and subprocess_all_ready_shot = '1' then
if ( current_regime_in_int = integrating) and To_slv ( resize ( statevariable_voltage_v_in - ( param_voltage_thresh ) ,2,-18))(20) = '0' then
eventport_out_spike_temp_1 := '1';
else
eventport_out_spike_temp_1 := '0';
end if;eventport_out_spike_internal <= eventport_out_spike_temp_1;
end if;
end process;
---------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign state variables to exposures
---------------------------------------------------------------------
exposure_voltage_v <= statevariable_voltage_v_in;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign state variables to output state variables
---------------------------------------------------------------------
statevariable_voltage_v_out <= statevariable_voltage_v_next;statevariable_time_lastSpikeTime_out <= statevariable_time_lastSpikeTime_next;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign derived variables to exposures
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Subprocess ready process
---------------------------------------------------------------------
subprocess_all_ready_process: process(step_once_go,subprocess_der_int_ready,subprocess_der_int_pre_ready,subprocess_der_ready,subprocess_dyn_int_pre_ready,subprocess_dyn_int_ready,subprocess_dyn_ready,subprocess_model_ready)
begin
if step_once_go = '0' and subprocess_der_int_ready = '1' and subprocess_der_int_pre_ready = '1'and subprocess_der_ready ='1' and subprocess_dyn_int_ready = '1' and subprocess_dyn_int_pre_ready = '1' and subprocess_dyn_ready = '1' and subprocess_model_ready = '1' then
subprocess_all_ready <= '1';
else
subprocess_all_ready <= '0';
end if;
end process subprocess_all_ready_process;
subprocess_all_ready_shot_process : process(clk)
begin
if rising_edge(clk) then
if (init_model='1') then
subprocess_all_ready_shot <= '0';
subprocess_all_ready_shotdone <= '1';
else
if subprocess_all_ready = '1' and subprocess_all_ready_shotdone = '0' then
subprocess_all_ready_shot <= '1';
subprocess_all_ready_shotdone <= '1';
elsif subprocess_all_ready_shot = '1' then
subprocess_all_ready_shot <= '0';
elsif subprocess_all_ready = '0' then
subprocess_all_ready_shot <= '0';
subprocess_all_ready_shotdone <= '0';
end if;
end if;
end if;
end process subprocess_all_ready_shot_process;
---------------------------------------------------------------------
count_proc:process(clk)
begin
if (clk'EVENT AND clk = '1') then
if init_model = '1' then COUNT <= "001";
component_done_int <= '1';
else if step_once_go = '1' then
COUNT <= "000";
component_done_int <= '0';
elsif COUNT = "001" then
component_done_int <= '1';
elsif subprocess_all_ready_shot = '1' then
COUNT <= COUNT + 1;
component_done_int <= '0';
end if;
end if;
end if;
end process count_proc;
childrenCombined_component_done_process:process(SynapseModel_component_done,CLK)
begin
if (SynapseModel_component_done = '1') then
childrenCombined_component_done <= '1';
else
childrenCombined_component_done <= '0';
end if;
end process childrenCombined_component_done_process;
component_done <= component_done_int and childrenCombined_component_done;
---------------------------------------------------------------------
-- Control the done signal
---------------------------------------------------------------------
step_once_complete_synch:process(clk)
begin
if (clk'EVENT AND clk = '1') then
if init_model = '1' then step_once_complete <= '0';
step_once_complete_fired <= '1';
else if component_done = '1' and step_once_complete_fired = '0' then
step_once_complete <= '1';
step_once_complete_fired <= '1';
---------------------------------------------------------------------
-- Assign event ports to exposures
---------------------------------------------------------------------
eventport_out_spike <= eventport_out_spike_internal ;
---------------------------------------------------------------------
elsif component_done = '0' then
step_once_complete <= '0';
step_once_complete_fired <= '0';
---------------------------------------------------------------------
-- Assign event ports to exposures
---------------------------------------------------------------------
eventport_out_spike <= '0';
---------------------------------------------------------------------
else
step_once_complete <= '0';
---------------------------------------------------------------------
-- Assign event ports to exposures
---------------------------------------------------------------------
eventport_out_spike <= '0';
---------------------------------------------------------------------
end if;
end if;
end if;
end process step_once_complete_synch;
---------------------------------------------------------------------
end RTL;
| lgpl-3.0 | 42786b791c39a5a4b3e49dc2318fac05 | 0.573441 | 3.806352 | false | false | false | false |
paulino/digilentinc-peripherals | examples/test1/test1.vhd | 1 | 3,091 | -------------------------------------------------------------------------------
-- Copyright 2014 Paulino Ruiz de Clavijo Vázquez <[email protected]>
-- This file is part of the Digilentinc-peripherals project.
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-- You can get more info at http://www.dte.us.es/id2
--
--*------------------------------- End auto header, don't touch this line --*--
--
-- Description: Demo/test to run in Basys2 Digilent prototype board.
-- This test transfers the data set from switches to one peripheral when a
-- button is pressed:
-- - When BTN0 is pressed the switches value set is copied to the leds
-- - When BTN1 is pressed the switches value set is copied to the LSB display
-- - When BTN2 is pressed the switches value set is copied to the MSB display
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.ALL;
use work.digilent_peripherals_pk.all;
entity demo1_digilent is
port(
clk : in std_logic;
leds_out : out std_logic_vector (7 downto 0);
seg_out : out std_logic_vector (6 downto 0);
dp_out : out std_logic;
an_out : out std_logic_vector (3 downto 0);
sw_in : in std_logic_vector (7 downto 0);
btn_in : in std_logic_vector (3 downto 0)
);
end demo1_digilent;
architecture behavioral of demo1_digilent is
-- Internal signals
signal port_display_enable : std_logic;
signal port_switches_out : std_logic_vector(7 downto 0);
signal port_buttons_out : std_logic_vector(7 downto 0);
begin
-- leds
u_leds: port_leds_dig port map (
clk => clk,
enable => '1',
w => port_buttons_out(0),
port_in => port_switches_out,
leds_out => leds_out);
-- Display enabled when BTN1 ot BNT2 is pressed
port_display_enable <= port_buttons_out(1) or port_buttons_out(2);
u_display : port_display_dig port map (
clk => clk,
enable => port_display_enable,
digit_in => port_switches_out,
w_msb => port_buttons_out(2),
w_lsb => port_buttons_out(1),
seg_out => seg_out,
dp_out => dp_out,
an_out => an_out
);
-- Switches
u_switches : port_switches_dig port map(
clk => clk,
enable => '1',
r => '1',
port_out => port_switches_out,
switches_in => sw_in);
-- Buttons
u_buttons : port_buttons_dig port map(
clk => clk,
enable => '1',
r => '1',
port_out => port_buttons_out,
buttons_in => btn_in);
end behavioral;
| apache-2.0 | 1bc9c2a5a992a36fe7f26e784dd2b20c | 0.601294 | 3.601399 | false | false | false | false |
Kalycito-open-automation/openPOWERLINK_V2_old_25-06-2014 | hardware/ipcore/common/openmac/src/dma_handler.vhd | 5 | 8,221 | -------------------------------------------------------------------------------
--
-- (c) B&R, 2011
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity dma_handler is
generic(
gen_rx_fifo_g : boolean := true;
gen_tx_fifo_g : boolean := true;
dma_highadr_g : integer := 31;
tx_fifo_word_size_log2_g : natural := 5;
rx_fifo_word_size_log2_g : natural := 5;
gen_dma_observer_g : boolean := true
);
port(
dma_clk : in std_logic;
rst : in std_logic;
mac_tx_off : in std_logic;
mac_rx_off : in std_logic;
dma_req_wr : in std_logic;
dma_req_rd : in std_logic;
dma_addr : in std_logic_vector(dma_highadr_g downto 1);
dma_ack_wr : out std_logic;
dma_ack_rd : out std_logic;
dma_rd_len : in std_logic_vector(11 downto 0);
tx_rd_clk : in std_logic;
tx_rd_usedw : in std_logic_vector(tx_fifo_word_size_log2_g-1 downto 0);
tx_rd_empty : in std_logic;
tx_rd_full : in std_logic;
tx_rd_req : out std_logic;
rx_wr_full : in std_logic;
rx_wr_empty : in std_logic;
rx_wr_usedw : in std_logic_vector(rx_fifo_word_size_log2_g-1 downto 0);
rx_wr_req : out std_logic;
rx_aclr : out std_logic;
rx_wr_clk : in std_logic;
dma_addr_out : out std_logic_vector(dma_highadr_g downto 1);
dma_rd_len_out : out std_logic_vector(11 downto 0);
dma_new_addr_wr : out std_logic;
dma_new_addr_rd : out std_logic;
dma_new_len : out std_logic;
dma_req_overflow : in std_logic;
dma_rd_err : out std_logic;
dma_wr_err : out std_logic
);
end dma_handler;
architecture dma_handler of dma_handler is
--clock signal
signal clk : std_logic;
--fsm
type transfer_t is (idle, first, run);
signal tx_fsm, tx_fsm_next, rx_fsm, rx_fsm_next : transfer_t := idle;
--dma signals
signal dma_ack_rd_s, dma_ack_wr_s : std_logic;
--dma observer
signal observ_rd_err, observ_wr_err : std_logic;
signal observ_rd_err_next, observ_wr_err_next : std_logic;
begin
--dma_clk, tx_rd_clk and rx_wr_clk are the same!
clk <= dma_clk; --to ease typing
rx_aclr <= rst;
process(clk, rst)
begin
if rst = '1' then
if gen_tx_fifo_g then
tx_fsm <= idle;
if gen_dma_observer_g then
observ_rd_err <= '0';
end if;
end if;
if gen_rx_fifo_g then
rx_fsm <= idle;
if gen_dma_observer_g then
observ_wr_err <= '0';
end if;
end if;
elsif clk = '1' and clk'event then
if gen_tx_fifo_g then
tx_fsm <= tx_fsm_next;
if gen_dma_observer_g then
observ_rd_err <= observ_rd_err_next;
end if;
end if;
if gen_rx_fifo_g then
rx_fsm <= rx_fsm_next;
if gen_dma_observer_g then
observ_wr_err <= observ_wr_err_next;
end if;
end if;
end if;
end process;
dma_rd_len_out <= dma_rd_len; --register in openMAC.vhd!
tx_fsm_next <= idle when gen_tx_fifo_g = false else --hang here if generic disables tx handling
first when tx_fsm = idle and dma_req_rd = '1' else
run when tx_fsm = first and dma_ack_rd_s = '1' else
idle when mac_tx_off = '1' else
tx_fsm;
rx_fsm_next <= idle when gen_rx_fifo_g = false else --hang here if generic disables rx handling
first when rx_fsm = idle and dma_req_wr = '1' else
run when rx_fsm = first else
idle when mac_rx_off = '1' else
rx_fsm;
genDmaObserver : if gen_dma_observer_g generate
begin
observ_rd_err_next <= --monoflop (deassertion with rst only)
'0' when gen_tx_fifo_g = false else
'1' when dma_req_rd = '1' and dma_ack_rd_s = '0' and dma_req_overflow = '1' else
observ_rd_err;
observ_wr_err_next <= --monoflop (deassertion with rst only)
'0' when gen_rx_fifo_g = false else
'1' when dma_req_wr = '1' and dma_ack_wr_s = '0' and dma_req_overflow = '1' else
observ_wr_err;
end generate;
dma_rd_err <= observ_rd_err;
dma_wr_err <= observ_wr_err;
--acknowledge dma request (regular or overflow)
dma_ack_rd <= dma_req_rd and (dma_ack_rd_s or dma_req_overflow);
dma_ack_wr <= dma_req_wr and (dma_ack_wr_s or dma_req_overflow);
dma_new_addr_wr <= '1' when rx_fsm = first else '0';
dma_new_addr_rd <= '1' when tx_fsm = first else '0';
dma_new_len <= '1' when tx_fsm = first else '0';
process(clk, rst)
begin
if rst = '1' then
dma_addr_out <= (others => '0');
if gen_tx_fifo_g then
tx_rd_req <= '0';
dma_ack_rd_s <= '0';
end if;
if gen_rx_fifo_g then
rx_wr_req <= '0';
dma_ack_wr_s <= '0';
end if;
elsif clk = '1' and clk'event then
--if the very first address is available, store it over the whole transfer
if tx_fsm = first or rx_fsm = first then
dma_addr_out <= dma_addr;
end if;
if gen_tx_fifo_g then
tx_rd_req <= '0';
dma_ack_rd_s <= '0';
--dma request, TX fifo is not empty and not yet ack'd
if dma_req_rd = '1' and tx_rd_empty = '0' and dma_ack_rd_s = '0' then
tx_rd_req <= '1'; --read from TX fifo
dma_ack_rd_s <= '1'; --ack the read request
end if;
end if;
if gen_rx_fifo_g then
rx_wr_req <= '0';
dma_ack_wr_s <= '0';
--dma request, RX fifo is not full and not yet ack'd
if dma_req_wr = '1' and rx_wr_full = '0' and dma_ack_wr_s = '0' then
rx_wr_req <= '1'; --write to RX fifo
dma_ack_wr_s <= '1'; --ack the read request
end if;
end if;
end if;
end process;
end dma_handler;
| gpl-2.0 | 485c47982845fb25298dfb13094c52c4 | 0.53935 | 3.618398 | false | false | false | false |
sergev/vak-opensource | hardware/dlx/dlx-behaviour.vhdl | 1 | 23,374 | --------------------------------------------------------------------------
--
-- Copyright (C) 1993, Peter J. Ashenden
-- Mail: Dept. Computer Science
-- University of Adelaide, SA 5005, Australia
-- e-mail: [email protected]
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 1, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
--------------------------------------------------------------------------
--
-- $RCSfile: dlx-behaviour.vhdl,v $ $Revision: 2.1 $ $Date: 1993/11/02 17:59:40 $
--
--------------------------------------------------------------------------
--
-- Behavioural architecture for DLX processor
--
use work.dlx_instr.all,
work.bv_arithmetic.all,
std.textio.all;
architecture behaviour of dlx is
begin -- behaviour
interpreter: process
type reg_array is array (reg_index) of dlx_word;
variable reg : reg_array;
variable fp_reg : reg_array;
variable PC : dlx_word;
variable user_mode : boolean;
variable overflow, div_by_zero : boolean;
constant PC_incr : dlx_word := X"0000_0004";
variable IR : dlx_word;
alias IR_opcode : dlx_opcode is IR(0 to 5);
alias IR_sp_func : dlx_sp_func is IR(26 to 31);
alias IR_fp_func : dlx_fp_func is IR(27 to 31);
alias IR_rs1 : dlx_reg_addr is IR(6 to 10);
alias IR_rs2 : dlx_reg_addr is IR(11 to 15);
alias IR_Itype_rd : dlx_reg_addr is IR(11 to 15);
alias IR_Rtype_rd : dlx_reg_addr is IR(16 to 20);
alias IR_immed16 : dlx_immed16 is IR(16 to 31);
alias IR_immed26 : dlx_immed26 is IR(6 to 31);
variable IR_opcode_num : dlx_opcode_num;
variable IR_sp_func_num : dlx_sp_func_num;
variable IR_fp_func_num : dlx_fp_func_num;
variable rs1, rs2, Itype_rd, Rtype_rd : reg_index;
variable mem_addr : dlx_address;
variable mem_data : dlx_word;
subtype ls_2_addr_bits is bit_vector(1 downto 0);
variable L : line;
procedure write (address : in dlx_address;
data_width : in mem_width;
data : in dlx_word;
signal phi1, phi2 : in bit; -- 2-phase non-overlapping clks
signal reset : in bit; -- synchronous reset input
signal a : out dlx_address; -- address bus output
signal d : inout dlx_word_bus; -- bidirectional data bus
signal width : out mem_width; -- byte/halfword/word
signal write_enable : out bit; -- selects read/write cycle
signal mem_enable : out bit; -- starts memory cycle
signal ifetch : out bit; -- indicates instruction fetch
signal ready : in bit; -- status from memory system
Tpd_clk_out : in time -- clock to output delay
) is
begin
wait until phi1 = '1';
if reset = '1' then
return;
end if;
a <= address after Tpd_clk_out;
width <= data_width after Tpd_clk_out;
d <= data after Tpd_clk_out;
write_enable <= '1' after Tpd_clk_out;
mem_enable <= '1' after Tpd_clk_out;
ifetch <= '0' after Tpd_clk_out;
loop
wait until phi2 = '0';
exit when ready = '1' or reset = '1';
end loop;
d <= null after Tpd_clk_out;
write_enable <= '0' after Tpd_clk_out;
mem_enable <= '0' after Tpd_clk_out;
end write;
procedure bus_read (address : in dlx_address;
data_width : in mem_width;
instr_fetch : in boolean;
data : out dlx_word;
signal phi1, phi2 : in bit; -- 2-phase non-overlapping clks
signal reset : in bit; -- synchronous reset input
signal a : out dlx_address; -- address bus output
signal d : inout dlx_word_bus; -- bidirectional data bus
signal width : out mem_width; -- byte/halfword/word
signal write_enable : out bit; -- selects read/write cycle
signal mem_enable : out bit; -- starts memory cycle
signal ifetch : out bit; -- indicates instruction eftch
signal ready : in bit; -- status from memory system
Tpd_clk_out : in time -- clock to output delay
) is
begin
wait until phi1 = '1';
if reset = '1' then
return;
end if;
a <= address after Tpd_clk_out;
width <= data_width after Tpd_clk_out;
mem_enable <= '1' after Tpd_clk_out;
ifetch <= bit'val(boolean'pos(instr_fetch)) after Tpd_clk_out;
loop
wait until phi2 = '0';
exit when ready = '1' or reset = '1';
end loop;
data := d;
mem_enable <= '0' after Tpd_clk_out;
end bus_read;
begin -- interpreter
--
-- reset the processor
--
d <= null;
halt <= '0';
write_enable <= '0';
mem_enable <= '0';
reg(0) := X"0000_0000";
PC := X"0000_0000";
user_mode := false;
--
-- fetch-decode-execute loop
--
loop
--
-- fetch next instruction
--
if debug then
write(L, tag);
write(L, string'(": fetching instruction..."));
writeline(output, L);
end if;
--
bus_read(PC, width_word, true, IR,
phi1, phi2, reset, a, d, width, write_enable, mem_enable, ifetch, ready,
Tpd_clk_out);
exit when reset = '1';
--
-- increment the PC to point to the following instruction
--
if debug then
write(L, tag);
write(L, string'(": incrementing PC..."));
writeline(output, L);
end if;
--
bv_add(PC, PC_incr, PC, overflow);
--
-- decode the instruction
--
if debug then
write(L, tag);
write(L, string'(": decoding instruction..."));
writeline(output, L);
end if;
--
IR_opcode_num := bv_to_natural(IR_opcode);
IR_sp_func_num := bv_to_natural(IR_sp_func);
IR_fp_func_num := bv_to_natural(IR_fp_func);
rs1 := bv_to_natural(IR_rs1);
rs2 := bv_to_natural(IR_rs2);
Itype_rd := bv_to_natural(IR_Itype_rd);
Rtype_rd := bv_to_natural(IR_Rtype_rd);
--
-- exectute
--
if debug then
write(L, tag);
write(L, string'(": executing instruction..."));
writeline(output, L);
end if;
--
case IR_opcode is
when op_special =>
case IR_sp_func is
WHEN sp_func_nop =>
null;
when sp_func_sll =>
reg(Rtype_rd) := bv_sll(reg(rs1), bv_to_natural(reg(rs2)(27 to 31)));
when sp_func_srl =>
reg(Rtype_rd) := bv_srl(reg(rs1), bv_to_natural(reg(rs2)(27 to 31)));
when sp_func_sra =>
reg(Rtype_rd) := bv_sra(reg(rs1), bv_to_natural(reg(rs2)(27 to 31)));
when sp_func_sequ =>
if reg(rs1) = reg(rs2) then
reg(Rtype_rd) := X"0000_0001";
else
reg(Rtype_rd) := X"0000_0000";
end if;
when sp_func_sneu =>
if reg(rs1) /= reg(rs2) then
reg(Rtype_rd) := X"0000_0001";
else
reg(Rtype_rd) := X"0000_0000";
end if;
when sp_func_sltu =>
if reg(rs1) < reg(rs2) then
reg(Rtype_rd) := X"0000_0001";
else
reg(Rtype_rd) := X"0000_0000";
end if;
when sp_func_sgtu =>
if reg(rs1) > reg(rs2) then
reg(Rtype_rd) := X"0000_0001";
else
reg(Rtype_rd) := X"0000_0000";
end if;
when sp_func_sleu =>
if reg(rs1) <= reg(rs2) then
reg(Rtype_rd) := X"0000_0001";
else
reg(Rtype_rd) := X"0000_0000";
end if;
when sp_func_sgeu =>
if reg(rs1) >= reg(rs2) then
reg(Rtype_rd) := X"0000_0001";
else
reg(Rtype_rd) := X"0000_0000";
end if;
when sp_func_add =>
bv_add(reg(rs1), reg(rs2), reg(Rtype_rd), overflow);
when sp_func_addu =>
bv_addu(reg(rs1), reg(rs2), reg(Rtype_rd), overflow);
when sp_func_sub =>
bv_sub(reg(rs1), reg(rs2), reg(Rtype_rd), overflow);
when sp_func_subu =>
bv_subu(reg(rs1), reg(rs2), reg(Rtype_rd), overflow);
when sp_func_and =>
reg(Rtype_rd) := reg(rs1) and reg(rs2);
when sp_func_or =>
reg(Rtype_rd) := reg(rs1) or reg(rs2);
when sp_func_xor =>
reg(Rtype_rd) := reg(rs1) xor reg(rs2);
when sp_func_seq =>
if reg(rs1) = reg(rs2) then
reg(Rtype_rd) := X"0000_0001";
else
reg(Rtype_rd) := X"0000_0000";
end if;
when sp_func_sne =>
if reg(rs1) /= reg(rs2) then
reg(Rtype_rd) := X"0000_0001";
else
reg(Rtype_rd) := X"0000_0000";
end if;
when sp_func_slt =>
if bv_lt(reg(rs1), reg(rs2)) then
reg(Rtype_rd) := X"0000_0001";
else
reg(Rtype_rd) := X"0000_0000";
end if;
when sp_func_sgt =>
if bv_gt(reg(rs1), reg(rs2)) then
reg(Rtype_rd) := X"0000_0001";
else
reg(Rtype_rd) := X"0000_0000";
end if;
when sp_func_sle =>
if bv_le(reg(rs1), reg(rs2)) then
reg(Rtype_rd) := X"0000_0001";
else
reg(Rtype_rd) := X"0000_0000";
end if;
when sp_func_sge =>
if bv_ge(reg(rs1), reg(rs2)) then
reg(Rtype_rd) := X"0000_0001";
else
reg(Rtype_rd) := X"0000_0000";
end if;
when sp_func_movi2s =>
assert false
report "MOVI2S instruction not implemented" severity warning;
when sp_func_movs2i =>
assert false
report "MOVS2I instruction not implemented" severity warning;
when sp_func_movf =>
assert false
report "MOVF instruction not implemented" severity warning;
when sp_func_movd =>
assert false
report "MOVD instruction not implemented" severity warning;
when sp_func_movfp2i =>
reg(Rtype_rd) := fp_reg(rs1);
when sp_func_movi2fp =>
fp_reg(Rtype_rd) := reg(rs1);
when others =>
assert false
report "undefined special instruction function" severity error;
end case;
when op_fparith =>
case IR_fp_func is
when fp_func_mult =>
bv_mult(fp_reg(rs1), fp_reg(rs2), fp_reg(Rtype_rd), overflow);
when fp_func_multu =>
bv_multu(fp_reg(rs1), fp_reg(rs2), fp_reg(Rtype_rd), overflow);
when fp_func_div =>
bv_div(fp_reg(rs1), fp_reg(rs2), fp_reg(Rtype_rd), div_by_zero, overflow);
when fp_func_divu =>
bv_divu(fp_reg(rs1), fp_reg(rs2), fp_reg(Rtype_rd), div_by_zero);
when fp_func_addf | fp_func_subf | fp_func_multf | fp_func_divf |
fp_func_addd | fp_func_subd | fp_func_multd | fp_func_divd |
fp_func_cvtf2d | fp_func_cvtf2i | fp_func_cvtd2f |
fp_func_cvtd2i | fp_func_cvti2f | fp_func_cvti2d |
fp_func_eqf | fp_func_nef | fp_func_ltf | fp_func_gtf |
fp_func_lef | fp_func_gef | fp_func_eqd | fp_func_ned |
fp_func_ltd | fp_func_gtd | fp_func_led | fp_func_ged =>
assert false
report "floating point instructions not implemented" severity warning;
when others =>
assert false
report "undefined floating point instruction function" severity error;
end case;
when op_j =>
bv_add(PC, bv_sext(IR_immed26, 32), PC, overflow);
when op_jal =>
reg(link_reg) := PC;
bv_add(PC, bv_sext(IR_immed26, 32), PC, overflow);
when op_beqz =>
if reg(rs1) = X"0000_0000" then
bv_add(PC, bv_sext(IR_immed16, 32), PC, overflow);
end if;
when op_bnez =>
if reg(rs1) /= X"0000_0000" then
bv_add(PC, bv_sext(IR_immed16, 32), PC, overflow);
end if;
when op_bfpt =>
assert false
report "BFPT instruction not implemented" severity warning;
when op_bfpf =>
assert false
report "BFPF instruction not implemented" severity warning;
when op_addi =>
bv_add(reg(rs1), bv_sext(IR_immed16, 32), reg(Itype_rd), overflow);
when op_addui =>
bv_addu(reg(rs1), bv_zext(IR_immed16, 32), reg(Itype_rd), overflow);
when op_subi =>
bv_sub(reg(rs1), bv_sext(IR_immed16, 32), reg(Itype_rd), overflow);
when op_subui =>
bv_subu(reg(rs1), bv_zext(IR_immed16, 32), reg(Itype_rd), overflow);
when op_slli =>
reg(Itype_rd) := bv_sll(reg(rs1), bv_to_natural(IR_immed16(11 to 15)));
when op_srli =>
reg(Itype_rd) := bv_srl(reg(rs1), bv_to_natural(IR_immed16(11 to 15)));
when op_srai =>
reg(Itype_rd) := bv_sra(reg(rs1), bv_to_natural(IR_immed16(11 to 15)));
when op_andi =>
reg(Itype_rd) := reg(rs1) and bv_zext(IR_immed16, 32);
when op_ori =>
reg(Itype_rd) := reg(rs1) or bv_zext(IR_immed16, 32);
when op_xori =>
reg(Itype_rd) := reg(rs1) xor bv_zext(IR_immed16, 32);
when op_lhi =>
reg(Itype_rd) := IR_immed16 & X"0000";
when op_rfe =>
assert false
report "RFE instruction not implemented" severity warning;
when op_trap =>
assert false
report "TRAP instruction encountered, execution halted"
severity note;
halt <= '1' after Tpd_clk_out;
wait until reset = '1';
exit;
when op_jr =>
PC := reg(rs1);
when op_jalr =>
reg(link_reg) := PC;
PC := reg(rs1);
when op_seqi =>
if reg(rs1) = bv_sext(IR_immed16, 32) then
reg(Itype_rd) := X"0000_0001";
else
reg(Itype_rd) := X"0000_0000";
end if;
when op_snei =>
if reg(rs1) /= bv_sext(IR_immed16, 32) then
reg(Itype_rd) := X"0000_0001";
else
reg(Itype_rd) := X"0000_0000";
end if;
when op_slti =>
if bv_lt(reg(rs1), bv_sext(IR_immed16, 32)) then
reg(Itype_rd) := X"0000_0001";
else
reg(Itype_rd) := X"0000_0000";
end if;
when op_sgti =>
if bv_gt(reg(rs1), bv_sext(IR_immed16, 32)) then
reg(Itype_rd) := X"0000_0001";
else
reg(Itype_rd) := X"0000_0000";
end if;
when op_slei =>
if bv_le(reg(rs1), bv_sext(IR_immed16, 32)) then
reg(Itype_rd) := X"0000_0001";
else
reg(Itype_rd) := X"0000_0000";
end if;
when op_sgei =>
if bv_ge(reg(rs1), bv_sext(IR_immed16, 32)) then
reg(Itype_rd) := X"0000_0001";
else
reg(Itype_rd) := X"0000_0000";
end if;
when op_lb =>
bv_add(reg(rs1), bv_sext(IR_immed16, 32), mem_addr, overflow);
bus_read(mem_addr, width_byte, false, mem_data,
phi1, phi2, reset, a, d, width, write_enable, mem_enable, ifetch, ready,
Tpd_clk_out);
exit when reset = '1';
case ls_2_addr_bits'(mem_addr(1 downto 0)) is
when B"00" =>
reg(Itype_rd) := bv_sext(mem_data(0 to 7), 32);
when B"01" =>
reg(Itype_rd) := bv_sext(mem_data(8 to 15), 32);
when B"10" =>
reg(Itype_rd) := bv_sext(mem_data(16 to 23), 32);
when B"11" =>
reg(Itype_rd) := bv_sext(mem_data(24 to 31), 32);
end case;
when op_lh =>
bv_add(reg(rs1), bv_sext(IR_immed16, 32), mem_addr, overflow);
bus_read(mem_addr, width_halfword, false, mem_data,
phi1, phi2, reset, a, d, width, write_enable, mem_enable, ifetch, ready,
Tpd_clk_out);
exit when reset = '1';
if mem_addr(1) = '0' then
reg(Itype_rd) := bv_sext(mem_data(0 to 15), 32);
else
reg(Itype_rd) := bv_sext(mem_data(16 to 31), 32);
end if;
when op_lw =>
bv_add(reg(rs1), bv_sext(IR_immed16, 32), mem_addr, overflow);
bus_read(mem_addr, width_word, false, mem_data,
phi1, phi2, reset, a, d, width, write_enable, mem_enable, ifetch, ready,
Tpd_clk_out);
exit when reset = '1';
reg(Itype_rd) := mem_data;
when op_lbu =>
bv_add(reg(rs1), bv_sext(IR_immed16, 32), mem_addr, overflow);
bus_read(mem_addr, width_byte, false, mem_data,
phi1, phi2, reset, a, d, width, write_enable, mem_enable, ifetch, ready,
Tpd_clk_out);
exit when reset = '1';
case ls_2_addr_bits'(mem_addr(1 downto 0)) is
when B"00" =>
reg(Itype_rd) := bv_zext(mem_data(0 to 7), 32);
when B"01" =>
reg(Itype_rd) := bv_zext(mem_data(8 to 15), 32);
when B"10" =>
reg(Itype_rd) := bv_zext(mem_data(16 to 23), 32);
when B"11" =>
reg(Itype_rd) := bv_zext(mem_data(24 to 31), 32);
end case;
when op_lhu =>
bv_add(reg(rs1), bv_sext(IR_immed16, 32), mem_addr, overflow);
bus_read(mem_addr, width_halfword, false, mem_data,
phi1, phi2, reset, a, d, width, write_enable, mem_enable, ifetch, ready,
Tpd_clk_out);
exit when reset = '1';
if mem_addr(1) = '0' then
reg(Itype_rd) := bv_zext(mem_data(0 to 15), 32);
else
reg(Itype_rd) := bv_zext(mem_data(16 to 31), 32);
end if;
when op_lf =>
assert false
report "LF instruction not implemented" severity warning;
when op_ld =>
assert false
report "LD instruction not implemented" severity warning;
when op_sb =>
bv_add(reg(rs1), bv_sext(IR_immed16, 32), mem_addr, overflow);
mem_data := X"0000_0000";
case ls_2_addr_bits'(mem_addr(1 downto 0)) is
when B"00" =>
mem_data(0 to 7) := reg(Itype_rd)(0 to 7);
when B"01" =>
mem_data(8 to 15) := reg(Itype_rd)(0 to 7);
when B"10" =>
mem_data(16 to 23) := reg(Itype_rd)(0 to 7);
when B"11" =>
mem_data(24 to 31) := reg(Itype_rd)(0 to 7);
end case;
write(mem_addr, width_halfword, mem_data,
phi1, phi2, reset, a, d, width, write_enable, mem_enable, ifetch, ready,
Tpd_clk_out);
exit when reset = '1';
when op_sh =>
bv_add(reg(rs1), bv_sext(IR_immed16, 32), mem_addr, overflow);
mem_data := X"0000_0000";
if mem_addr(1) = '0' then
mem_data(0 to 15) := reg(Itype_rd)(0 to 15);
else
mem_data(16 to 31) := reg(Itype_rd)(0 to 15);
end if;
write(mem_addr, width_halfword, mem_data,
phi1, phi2, reset, a, d, width, write_enable, mem_enable, ifetch, ready,
Tpd_clk_out);
exit when reset = '1';
when op_sw =>
bv_add(reg(rs1), bv_sext(IR_immed16, 32), mem_addr, overflow);
mem_data := reg(Itype_rd);
write(mem_addr, width_word, mem_data,
phi1, phi2, reset, a, d, width, write_enable, mem_enable, ifetch, ready,
Tpd_clk_out);
exit when reset = '1';
when op_sf =>
assert false
report "SF instruction not implemented" severity warning;
when op_sd =>
assert false
report "SD instruction not implemented" severity warning;
when op_sequi =>
if reg(rs1) = bv_zext(IR_immed16, 32) then
reg(Itype_rd) := X"0000_0001";
else
reg(Itype_rd) := X"0000_0000";
end if;
when op_sneui =>
if reg(rs1) /= bv_zext(IR_immed16, 32) then
reg(Itype_rd) := X"0000_0001";
else
reg(Itype_rd) := X"0000_0000";
end if;
when op_sltui =>
if reg(rs1) < bv_zext(IR_immed16, 32) then
reg(Itype_rd) := X"0000_0001";
else
reg(Itype_rd) := X"0000_0000";
end if;
when op_sgtui =>
if reg(rs1) > bv_zext(IR_immed16, 32) then
reg(Itype_rd) := X"0000_0001";
else
reg(Itype_rd) := X"0000_0000";
end if;
when op_sleui =>
if reg(rs1) <= bv_zext(IR_immed16, 32) then
reg(Itype_rd) := X"0000_0001";
else
reg(Itype_rd) := X"0000_0000";
end if;
when op_sgeui =>
if reg(rs1) >= bv_zext(IR_immed16, 32) then
reg(Itype_rd) := X"0000_0001";
else
reg(Itype_rd) := X"0000_0000";
end if;
when others =>
assert false
report "undefined instruction" severity error;
end case;
--
-- fix up R0 in case it was overwritten
--
reg(0) := X"0000_0000";
--
if debug then
write(L, tag);
write(L, string'(": end of execution"));
writeline(output, L);
end if;
--
end loop;
--
-- loop is only exited when reset active: wait until it goes inactive
--
assert reset = '1'
report "reset code reached with reset = '0'" severity error;
wait until phi2 = '0' and reset = '0';
--
-- process interpreter now starts again from beginning
--
end process interpreter;
end behaviour;
| apache-2.0 | 28bc8ecccf30e90edee7440fd6df6b97 | 0.492599 | 3.583321 | false | false | false | false |
hoglet67/AtomGodilVideo | src/SID/sid_filters.vhd | 2 | 5,601 | --
-- (C) Alvaro Lopes <[email protected]> All Rights Reserved
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sid_filters is
port (
clk : in std_logic; -- At least 12Mhz
rst : in std_logic;
-- SID registers.
Fc_lo : in std_logic_vector(7 downto 0);
Fc_hi : in std_logic_vector(7 downto 0);
Res_Filt : in std_logic_vector(7 downto 0);
Mode_Vol : in std_logic_vector(7 downto 0);
-- Voices - resampled to 13 bit
voice1 : in signed(12 downto 0);
voice2 : in signed(12 downto 0);
voice3 : in signed(12 downto 0);
--
input_valid : in std_logic;
ext_in : in signed(12 downto 0);
sound : out signed(18 downto 0);
valid : out std_logic
);
end entity;
architecture beh of sid_filters is
alias filt : std_logic_vector(3 downto 0) is Res_Filt(3 downto 0);
alias res : std_logic_vector(3 downto 0) is Res_Filt(7 downto 4);
alias volume : std_logic_vector(3 downto 0) is Mode_Vol(3 downto 0);
alias hp_bp_lp : std_logic_vector(2 downto 0) is Mode_Vol(6 downto 4);
alias voice3off : std_logic is Mode_Vol(7);
constant mixer_DC : integer := -475; -- NOTE to self: this might be wrong.
type regs_type is record
Vhp : signed(17 downto 0);
Vbp : signed(17 downto 0);
dVbp : signed(17 downto 0);
Vlp : signed(17 downto 0);
dVlp : signed(17 downto 0);
Vi : signed(17 downto 0);
Vnf : signed(17 downto 0);
Vf : signed(17 downto 0);
w0 : signed(17 downto 0);
q : signed(17 downto 0);
vout : signed(18 downto 0);
state : integer;
done : std_logic;
end record;
signal addr : integer range 0 to 2047;
signal val : std_logic_vector(15 downto 0);
type divmul_t is array(0 to 15) of integer;
constant divmul: divmul_t := (
1448, 1323, 1218, 1128, 1051, 984, 925, 872, 825, 783, 745, 710, 679, 650, 624, 599
);
signal r : regs_type;
signal mula : signed(17 downto 0);
signal mulb : signed(17 downto 0);
signal mulr : signed(35 downto 0);
signal mulen : std_logic;
function s13_to_18(a: in signed(12 downto 0)) return signed is
begin
return a(12)&a(12)&a(12)&a(12)&a(12)&a;
end function;
signal fc : std_logic_vector(10 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if mulen='1' then
mulr <= mula * mulb;
end if;
end if;
end process;
fc <= Fc_hi & Fc_lo(2 downto 0);
c: entity work.sid_coeffs
port map (
clk => clk,
addr => addr,
val => val
);
addr <= to_integer(unsigned(fc));
process(clk, rst, r, input_valid, val, filt, voice1, voice2, voice3, voice3off, mulr, ext_in, hp_bp_lp, Mode_Vol)
variable w: regs_type;
begin
w:=r;
mula <= (others => 'X');
mulb <= (others => 'X');
mulen <= '0';
case r.state is
when 0 =>
w.done := '0';
if input_valid = '1' then
w.state := 1;
-- Reset Vin, Vnf
w.vi := (others => '0');
w.vnf := (others => '0');
end if;
when 1 =>
w.state := 2;
-- already have W0 ready. Always positive
w.w0 := "00" & signed(val);
-- 1st accumulation
if filt(0)='1' then
w.vi := r.vi + s13_to_18(voice1);
else
w.vnf := r.vnf + s13_to_18(voice1);
end if;
when 2 =>
w.state := 3;
-- 2nd accumulation
if filt(1)='1' then
w.vi := r.vi + s13_to_18(voice2);
else
w.vnf := r.vnf + s13_to_18(voice2);
end if;
-- Mult
mula <= r.w0;
mulb <= r.vhp;
mulen <= '1';
when 3 =>
w.state := 4;
-- 3rd accumulation
if filt(2)='1' then
w.vi := r.vi + s13_to_18(voice3);
else
if voice3off='0' then
w.vnf := r.vnf + s13_to_18(voice3);
end if;
end if;
-- Mult
mula <= r.w0;
mulb <= r.vbp;
mulen <= '1';
w.dVbp := mulr(35) & mulr(35 downto 19);
when 4 =>
w.state := 5;
-- 4th accumulation
if filt(3)='1' then
w.vi := r.vi + s13_to_18(ext_in);
else
w.vnf := r.vnf + s13_to_18(ext_in);
end if;
w.dVlp := mulr(35) & mulr(35 downto 19);
w.Vbp := r.Vbp - r.dVbp;
-- Get Q, synchronous.
w.q := to_signed(divmul(to_integer(unsigned(res))), 18);
when 5 =>
w.state := 6;
-- Ok, we have all summed. We performed multiplications for dVbp and dVlp.
-- new Vbp already computed.
mulen <= '1';
mula <= r.q;
mulb <= r.Vbp;
w.vlp := r.Vlp - r.dVlp;
-- Start computing output;
if hp_bp_lp(1)='1' then
w.Vf := r.Vbp;
else
w.Vf := (others => '0');
end if;
when 6 =>
w.state := 7;
-- Adjust Vbp*Q, shift by 10
w.Vhp := (mulr(35)&mulr(26 downto 10)) - r.vlp;
if hp_bp_lp(0)='1' then
w.Vf := r.Vf + r.Vlp;
end if;
when 7 =>
w.state := 8;
w.Vhp := r.Vhp - r.Vi;
when 8 =>
w.state := 9;
if hp_bp_lp(2)='1' then
w.Vf := r.Vf + r.Vhp;
end if;
when 9 =>
w.state := 10;
w.Vf := r.Vf + r.Vnf;
when 10 =>
w.state := 11;
-- Add mixer DC
w.Vf := r.Vf + to_signed(mixer_DC, r.Vf'LENGTH);
when 11 =>
w.state := 12;
-- Process volume
mulen <= '1';
mula <= r.Vf;
mulb <= (others => '0');
mulb(3 downto 0) <= signed(volume);
when 12 =>
w.state := 0;
w.done := '1';
w.vout(18) := mulr(35);
w.vout(17 downto 0) := mulr(17 downto 0);
when others => null;
end case;
if rst='1' then
w.done := '0';
w.state := 0;
w.Vlp := (others => '0');
w.Vbp := (others => '0');
w.Vhp := (others => '0');
end if;
if rising_edge(clk) then
r<=w;
end if;
end process;
sound <= r.vout;
valid <= r.done;
end beh;
| apache-2.0 | 3eb5ce01d884ed073965ec39cac95d3e | 0.549366 | 2.533243 | false | false | false | false |
Kalycito-open-automation/openPOWERLINK_V2_old_25-06-2014 | hardware/ipcore/common/lib/src/addrDecodeRtl.vhd | 2 | 4,004 | -------------------------------------------------------------------------------
--! @file addrDecodeRtl.vhd
--
--! @brief Address Decoder for generating select signal
--
--! @details This address decoder generates a select signal depending on the
--! provided base- and high-addresses by using smaller/greater logic.
--! Additionally a strob is generated if the base or high address is selected.
-------------------------------------------------------------------------------
--
-- (c) B&R, 2013
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.global.all;
entity addrDecode is
generic (
--! Address bus width
gAddrWidth : natural := 32;
--! Decode space base address
gBaseAddr : natural := 16#1000#;
--! Decode space high address
gHighAddr : natural := 16#1FFF#
);
port (
--! Enable decoding
iEnable : in std_logic;
--! Address bus
iAddress : in std_logic_vector(gAddrWidth-1 downto 0);
--! Select output
oSelect : out std_logic
);
end addrDecode;
architecture rtl of addrDecode is
--! Address to be decoded
signal address : unsigned(gAddrWidth-1 downto 0);
--! Address is in range
signal addressInRange : std_logic;
--! Base address used for comparison
constant cBase : unsigned(gAddrWidth-1 downto 0) :=
to_unsigned(gBaseAddr, gAddrWidth);
--! High address used for comparison
constant cHigh : unsigned(gAddrWidth-1 downto 0) :=
to_unsigned(gHighAddr, gAddrWidth);
begin
-- check generics
assert (gBaseAddr < gHighAddr)
report "Base address should be smaller than High address!" severity failure;
-- connect ports to signals
oSelect <= addressInRange;
address <= unsigned(iAddress);
--! Decode input address logic
combAddrDec : process (
iEnable,
address
)
begin
--default assignments of process outputs
addressInRange <= cInactivated;
if iEnable = cActivated then
if (cBase <= address) and (address <= cHigh) then
addressInRange <= cActivated;
end if;
end if;
end process;
end rtl;
| gpl-2.0 | 928aac44c24522cad412c876a0b711db | 0.627123 | 4.882927 | false | false | false | false |
hoglet67/AtomGodilVideo | src/pointer/PointerRamWhite.vhd | 2 | 6,556 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity PointerRamWhite is
port (
clka : in std_logic;
wea : in std_logic;
addra : in std_logic_vector(7 downto 0);
dina : in std_logic_vector(7 downto 0);
douta : out std_logic_vector(7 downto 0);
clkb : in std_logic;
web : in std_logic;
addrb : in std_logic_vector(7 downto 0);
dinb : in std_logic_vector(7 downto 0);
doutb : out std_logic_vector(7 downto 0)
);
end PointerRamWhite;
architecture BEHAVIORAL of PointerRamWhite is
-- Shared memory
type ram_type is array (0 to 255) of std_logic_vector (7 downto 0);
shared variable RAM : ram_type := (
"00000000",
"01111100",
"01111000",
"01111000",
"01111100",
"01001110",
"00000100",
"00000000",
"00000000",
"01000000",
"00000000",
"00000000",
"00000000",
"00000000",
"00000000",
"00000000",
"00000000",
"00101100",
"01101110",
"01101110",
"01100010",
"01111110",
"00111100",
"00000000",
"00000000",
"01111110",
"01000000",
"01000000",
"01000000",
"01000000",
"01000000",
"00000000",
"00000000",
"00010000",
"00111000",
"00111000",
"00111000",
"00111000",
"00111000",
"00000000",
"00000000",
"00111000",
"00111000",
"00111000",
"00111000",
"00111000",
"00010000",
"00000000",
"00000000",
"00000000",
"01111100",
"01111110",
"01111100",
"00000000",
"00000000",
"00000000",
"00000000",
"00000000",
"00111110",
"01111110",
"00111110",
"00000000",
"00000000",
"00000000",
"00000000",
"00111000",
"01110010",
"01110010",
"01100110",
"01100110",
"00001100",
"00000000",
"00000000",
"00111000",
"00101000",
"00001000",
"00010000",
"00000000",
"00010000",
"00000000",
"00000000",
"00111000",
"00010000",
"00010000",
"00010000",
"00010000",
"00111000",
"00000000",
"00000000",
"00010000",
"00010000",
"01111100",
"00010000",
"00010000",
"00000000",
"00000000",
"00000000",
"01000000",
"01000000",
"01000000",
"01010100",
"01111110",
"00000000",
"00000000",
"00000000",
"00000000",
"01111110",
"01010100",
"01000000",
"01000000",
"01000000",
"00000000",
"00000000",
"00111110",
"00100000",
"00110000",
"00100000",
"00110000",
"00100000",
"00000000",
"00000000",
"01111100",
"00000100",
"00001100",
"00000100",
"00001100",
"00000100",
"00000000",
"00000000",
"00111100",
"00011000",
"00000000",
"00000000",
"00011000",
"00111100",
"00000000",
"00000000",
"00111100",
"00011000",
"00000000",
"00000000",
"00011000",
"00100100",
"00000000",
"00000000",
"00111100",
"00011000",
"00000000",
"00000000",
"00011000",
"00000000",
"00000000",
"00000000",
"00111100",
"00011000",
"00000000",
"00000000",
"00000000",
"00000000",
"00000000",
"00000000",
"01100000",
"00111000",
"00001110",
"00010100",
"00101010",
"00010110",
"00000000",
"00000000",
"00000110",
"00011100",
"01110000",
"00101000",
"01010100",
"01101000",
"00000000",
"00000000",
"00010110",
"00101010",
"00010100",
"00001110",
"00111000",
"01100000",
"00000000",
"00000000",
"01101000",
"01010100",
"00101000",
"01110000",
"00011100",
"00000110",
"00000000",
"00000000",
"01100110",
"01100110",
"00100010",
"00100010",
"01100110",
"01100110",
"00000000",
"00000000",
"00000000",
"00000000",
"01100110",
"01100110",
"01100110",
"01100110",
"00000000",
"00000000",
"01100110",
"01100110",
"01000100",
"01000100",
"01100110",
"01100110",
"00000000",
"00000000",
"01100110",
"01100110",
"01100110",
"01100110",
"00000000",
"00000000",
"00000000",
"00000000",
"01111100",
"01111000",
"01110000",
"01100000",
"01000000",
"00000000",
"00000000",
"00000000",
"00000000",
"01000000",
"01100000",
"01110000",
"01111000",
"01111100",
"00000000",
"00000000",
"00000000",
"00000010",
"00000110",
"00001110",
"00011110",
"00111110",
"00000000",
"00000000",
"00111110",
"00011110",
"00001110",
"00000110",
"00000010",
"00000000",
"00000000"
);
--attribute RAM_STYLE : string;
--attribute RAM_STYLE of RAM: signal is "BLOCK";
begin
process (clka)
begin
if rising_edge(clka) then
if (wea = '1') then
RAM(conv_integer(addra(7 downto 0))) := dina;
end if;
douta <= RAM(conv_integer(addra(7 downto 0)));
end if;
end process;
process (clkb)
begin
if rising_edge(clkb) then
if (web = '1') then
RAM(conv_integer(addrb(7 downto 0))) := dinb;
end if;
doutb <= RAM(conv_integer(addrb(7 downto 0)));
end if;
end process;
end BEHAVIORAL;
| apache-2.0 | 879a5cbef24a52464436e63f2f2d1d9f | 0.433038 | 4.626676 | false | false | false | false |
bangonkali/quartus-sockit | soc_system/synthesis/submodules/alt_vipvfr131_common_ram_fifo.vhd | 2 | 7,903 | -- Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
-- use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any
-- output files any of the foregoing (including device programming or
-- simulation files), and any associated documentation or information are
-- expressly subject to the terms and conditions of the Altera Program
-- License Subscription Agreement or other applicable license agreement,
-- including, without limitation, that your use is for the sole purpose
-- of programming logic devices manufactured by Altera and sold by Altera
-- or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.alt_vipvfr131_common_package.all;
entity alt_vipvfr131_common_ram_fifo is
generic
(
WIDTH : integer := 8;
DEPTH : integer := 3;
CLOCKS_ARE_SAME : boolean := TRUE;
DEVICE_FAMILY : string
);
port
(
-- clocks, enables and reset
rdclock : in std_logic;
rdena : in std_logic;
wrclock : in std_logic;
wrena : in std_logic;
reset : in std_logic;
-- information signals from the fifo (write side)
wrusedw : out std_logic_vector(wide_enough_for(DEPTH) - 1 downto 0);
full : out std_logic;
almost_full : out std_logic;
-- information signals from the fifo (read side)
rdusedw : out std_logic_vector(wide_enough_for(DEPTH) - 1 downto 0);
empty : out std_logic;
almost_empty : out std_logic;
-- getting data into the fifo
wrreq : in std_logic;
data : in std_logic_vector(WIDTH - 1 downto 0);
-- ...and back out again
rdreq : in std_logic;
q : out std_logic_vector(WIDTH - 1 downto 0)
);
end entity;
architecture rtl of alt_vipvfr131_common_ram_fifo is
-- ASSUMPTIONS --
-- the code assumes that if this many clock cycles have elapsed
-- between a write and a read to the same location in the ram
-- then the new data will be seen
-- must be at least 1 or the logic won't work
constant RAM_READ_AFTER_WRITE_LATENCY : integer := 3;
-- this code assumes that
-- read after write delay need not be added to the usedw calculation if we're in dual clock
-- mode, because the delay associated with crossing clock domains covers it
function calculate_read_after_write_delay_required return integer is
begin
if CLOCKS_ARE_SAME then
return RAM_READ_AFTER_WRITE_LATENCY;
else
return 0;
end if;
end function;
constant READ_AFTER_WRITE_DELAY_REQUIRED : integer := calculate_read_after_write_delay_required;
-- note that addresses can be one bit narrower than usedw (if DEPTH is a power of two)
constant ADDR_WIDTH : integer := maximum(wide_enough_for(DEPTH - 1), 1);
constant USEDW_WIDTH : integer := wide_enough_for(DEPTH);
-- ram depth is 2 ^ ADDR_WIDTH rather than depth - if the fifo
-- is not of power of two depth it wanders over the ram,
-- but all ram words are always used, to save on comparators
constant RAM_DEPTH : integer := two_to_the_power(ADDR_WIDTH);
component altsyncram
generic
(
OPERATION_MODE : string := "DUAL_PORT";
WIDTH_A : natural := WIDTH;
WIDTHAD_A : natural := ADDR_WIDTH;
NUMWORDS_A : natural := RAM_DEPTH;
WIDTH_B : natural := WIDTH;
WIDTHAD_B : natural := ADDR_WIDTH;
NUMWORDS_B : natural := RAM_DEPTH;
WIDTH_BYTEENA_A : natural := 1;
WIDTH_BYTEENA_B : natural := 1;
OUTDATA_REG_A : string := "CLOCK0";
OUTDATA_REG_B : string := "CLOCK1";
INDATA_REG_B : string := "CLOCK1";
ADDRESS_REG_B : string := "CLOCK1";
WRCONTROL_WRADDRESS_REG_B : string := "CLOCK1";
LPM_TYPE : string := "altsyncram";
RAM_BLOCK_TYPE : string := "AUTO";
INTENDED_DEVICE_FAMILY : string := DEVICE_FAMILY;
READ_DURING_WRITE_MODE_MIXED_PORTS : string := "DONT_CARE"
);
port
(
clocken0 : in std_logic ;
clocken1 : in std_logic ;
wren_a : in std_logic ;
clock0 : in std_logic ;
wren_b : in std_logic ;
clock1 : in std_logic ;
address_a : in std_logic_vector (widthad_a-1 downto 0);
address_b : in std_logic_vector (widthad_a-1 downto 0);
q_a : out std_logic_vector (width_a-1 downto 0);
q_b : out std_logic_vector (width_a-1 downto 0);
data_a : in std_logic_vector (width_a-1 downto 0);
data_b : in std_logic_vector (width_a-1 downto 0)
);
end component;
-- pointers into the ram used for reading and writing
signal rdpointer : unsigned(ADDR_WIDTH - 1 downto 0);
signal wrpointer : unsigned(ADDR_WIDTH - 1 downto 0);
-- unused
signal port_a_q : std_logic_vector(WIDTH - 1 downto 0);
begin
-- check generics
assert DEPTH > 0
report "Generic DEPTH must greater than zero"
severity ERROR;
assert WIDTH > 0
report "Generic WIDTH must greater than zero"
severity ERROR;
-- this fifo uses a ram block to store the fifo data
-- port a is used for writing into the fifo
-- port b is used for reading from the fifo
ram : altsyncram
port map
(
clock0 => wrclock,
clock1 => rdclock,
clocken0 => wrena,
clocken1 => rdena,
wren_a => wrreq,
wren_b => '0',
address_a => std_logic_vector(wrpointer),
address_b => std_logic_vector(rdpointer),
q_a => port_a_q,
q_b => q,
data_a => data,
data_b => (others => '0')
);
-- the data in the ram does not move
-- two pointers, head and tail, chase each other through the ram
-- and define the extent of the fifo
-- if the read pointer catches up with the write pointer then the fifo is empty
-- if the write pointer catches up with the read pointer then the fifo is full
-- note that there is no protection here, reading from an empty fifo or
-- writing to a full one will cause undefined results
-- two processes, in case rdclock and wrclock are different
-- read first
update_rdpointer : process (rdclock, reset)
begin
if reset = '1' then
-- start at zero - pointers equal meaning empty
rdpointer <= (others => '0');
elsif rdclock'EVENT and rdclock = '1' then
if rdena = '1' then
if rdreq = '1' then
rdpointer <= rdpointer + 1;
end if;
end if;
end if;
end process;
-- ...and now write
update_wrpointer : process (wrclock, reset)
begin
if reset = '1' then
-- start at zero - pointers equal meaning empty
wrpointer <= (others => '0');
elsif wrclock'EVENT and wrclock = '1' then
if wrena = '1' then
if wrreq = '1' then
wrpointer <= wrpointer + 1;
end if;
end if;
end if;
end process;
-- instantiate a standard usedw calculator to do the usedw, empty etc. updating
usedw_calculator : alt_vipvfr131_common_fifo_usedw_calculator
generic map
(
WIDTH => USEDW_WIDTH,
DEPTH => DEPTH,
CLOCKS_ARE_SAME => CLOCKS_ARE_SAME,
READ_TO_WRITE_DELAY => 0,
WRITE_TO_READ_DELAY => READ_AFTER_WRITE_DELAY_REQUIRED
)
port map
(
rdclock => rdclock,
wrclock => wrclock,
reset => reset,
wrreq => wrreq,
rdreq => rdreq,
wrena => wrena,
rdena => rdena,
wrusedw => wrusedw,
full => full,
almost_full => almost_full,
rdusedw => rdusedw,
empty => empty,
almost_empty => almost_empty
);
end ;
| mit | 12a40216b0508fb94aafa3057b46c423 | 0.61483 | 3.55991 | false | false | false | false |
ShepardSiegel/ocpi | libsrc/hdl/vhd/ocpi_wci_body.vhd | 1 | 3,439 | library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all;
package body wci is
-- convert byte enables to byte offsets
function decode_access(input : in_t) return access_t is begin
case input.MCmd is
when ocp.MCmd_WRITE => if input.MAddrSpace(0) = '1' then return write_e; else return Error_e; end if;
when ocp.MCmd_READ => if input.MAddrSpace(0) = '1' then return Read_e; else return Control_e; end if;
when others => return None_e;
end case;
end decode_access;
--function "=" (l,r: Property_Io_t) return boolean is begin
-- return Property_io_t'pos(l) = Property_io_t'pos(r);
--end "=";
-- return property access specific to this offset and size and address width
-- the basic decode is redundant across properties, but should be optimized anyawy
--function decode_property (input : in_t; low, high : unsigned) return property_access_t is
-- variable io : property_io_t := config_access(input);
-- variable moffset : unsigned (low'left downto 0)
-- := unsigned(input.MAddr(low'left downto 2) & be2offset(input));
--begin
-- if io /= None_e and moffset >= low and moffset <= high then
-- return property_access_t'(io, moffset - low);
-- end if;
-- return property_access_t'(None_e, property_offset_t'(others => '0'));
--end decode_property;
function get_value(input : in_t; boffset : unsigned; width : natural) return std_logic_vector is
variable bitoffset : natural := to_integer(boffset & "000");
variable bitwidth : natural := width;
begin
if bitwidth > 32 then bitwidth := 32; end if;
return input.MData(bitoffset + bitwidth - 1 downto bitoffset);
end get_value;
function to_control_op(bits : std_logic_vector(2 downto 0)) return control_op_t is
begin
--this fine in VHDL, but not in XST
--return control_op_t'val(to_integer(unsigned(bits)));
case to_integer(unsigned(bits)) is
when control_op_t'pos(initialize_e) => return initialize_e;
when control_op_t'pos(start_e) => return start_e;
when control_op_t'pos(stop_e) => return stop_e;
when control_op_t'pos(release_e) => return release_e;
when control_op_t'pos(before_query_e) => return before_query_e;
when control_op_t'pos(after_config_e) => return after_config_e;
when control_op_t'pos(test_e) => return test_e;
when others => return no_op_e;
end case;
--return start_e; --to_unsigned(2,3); --unsigned(bits);
-- case unsigned(bits) is
-- when initialize_e => return initialize_e;
-- when start_e => return start_e;
-- when stop_e => return stop_e;
-- when release_e => return release_e;
-- when before_query_e => return before_query_e;
-- when after_config_e => return after_config_e;
-- when test_e => return test_e;
-- when others => return no_op_e;
-- end case;
end to_control_op;
-- How wide should the data path be from the decoder to the property
function data_out_top (property : property_t) return natural is
begin
if property.data_width >= 32 or property.nitems > 1 then
return 31;
else
return property.data_width - 1;
end if;
end data_out_top;
function resize(bits : std_logic_vector; n : natural) return std_logic_vector is begin
return std_logic_vector(resize(unsigned(bits),n));
end resize;
end wci;
| lgpl-3.0 | 9f6b119494bf4d25467adbe86a22c33e | 0.653678 | 3.157943 | false | true | false | false |
paulino/digilentinc-peripherals | rtl/port_buttons_nexsys4.vhd | 1 | 2,035 | -------------------------------------------------------------------------------
-- Copyright 2014 Paulino Ruiz de Clavijo Vázquez <[email protected]>
-- This file is part of the Digilentinc-peripherals project.
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-- You can get more info at http://www.dte.us.es/id2
--
--*------------------------------- End auto header, don't touch this line --*--
-- Buttons synchronizer for nesys4 board
-- Buttons out:
-- +----------------------------------------------+
-- | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
-- +----------------------------------------------+
-- port_out[7:0]= | 0 | 0 | 0 | BTNU | BTNR | BTND | BTNL | BTNC |
-- +----------------------------------------------+
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity port_buttons_nexsys4 is port (
r : in std_logic;
clk : in std_logic;
enable : in std_logic;
btnu_in : in std_logic;
btnr_in : in std_logic;
btnl_in : in std_logic;
btnd_in : in std_logic;
btnc_in : in std_logic;
port_out : out std_logic_vector (7 downto 0));
end port_buttons_nexsys4;
architecture behavioral of port_buttons_nexsys4 is
begin
port_out(7 downto 5) <= "000";
read_proc: process(clk,enable,r)
begin
if falling_edge(clk) and enable='1' and r='1' then
port_out(4 downto 0) <= btnu_in & btnl_in & btnd_in &
btnr_in & btnc_in;
end if;
end process;
end behavioral;
| apache-2.0 | 5753b78ce6ab323dadad5c70bfa69dce | 0.544739 | 3.658273 | false | false | false | false |
Kalycito-open-automation/openPOWERLINK_V2_old_25-06-2014 | hardware/ipcore/xilinx/lib/src/dpRamSplxNbe-rtl-a.vhd | 2 | 3,948 | -------------------------------------------------------------------------------
--! @file dpRamSplxNbe-a.vhd
--
--! @brief Simplex Dual Port Ram without byteenables
--
--! @details This is the Simplex DPRAM without byteenables for Xilinx platforms.
--! The DPRAM has one write and one read port only.
--! Timing as follows [clk-cycles]: write=0 / read=1
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2013
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
--! use global library
use work.global.all;
architecture rtl of dpRamSplxNbe is
--! Address width (used to generate size depending on address width)
constant cAddrWidth : natural := iAddress_A'length;
--! RAM size
constant cRamSize : natural := 2**cAddrWidth;
--! Type for data port
subtype tDataPort is std_logic_vector(gWordWidth-1 downto 0);
--! RAM type with given size
type tRam is array (cRamSize-1 downto 0) of tDataPort;
--! Shared variable to model and synthesize a DPR
shared variable vDpram : tRam := (others => (others => cInactivated));
--! Port B readport
signal readdataB : tDataPort;
begin
-- assign readdata to ports
oReaddata_B <= readdataB;
--! This process describes port A of the DPRAM. The write process considers
--! iWriteEnable_A.
PORTA : process(iClk_A)
begin
if rising_edge(iClk_A) then
if iEnable_A = cActivated then
if iWriteEnable_A = cActivated then
-- write byte to DPRAM
vDpram(to_integer(unsigned(iAddress_A))) := iWritedata_A;
end if; --writeenable
end if; --enable
end if;
end process PORTA;
--! This process describes port B of the DPRAM. The read process is done
--! with every rising iClk_B edge.
PORTB : process(iClk_B)
begin
if rising_edge(iClk_B) then
if iEnable_B = cActivated then
-- read word from DPRAM
readdataB <= vDpram(to_integer(unsigned(iAddress_B)));
end if; --enable
end if;
end process PORTB;
end architecture rtl;
| gpl-2.0 | 97407b101b69fd3eaef1f0ebdd482802 | 0.630193 | 4.677725 | false | false | false | false |
Wynjones1/VHDL-Build | example/text_display/external/sd.vhd | 1 | 7,178 | -- VHDL SD card interface
-- by Steven J. Merrifield, June 2008
-- Reads and writes a single block of data, and also writes continuous data
-- Tested on Xilinx Spartan 3 hardware, using Transcend and SanDisk Ultra II cards
-- Read states are derived from the Apple II emulator by Stephen Edwards
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sd_controller is
port (
cs : out std_logic;
mosi : out std_logic;
miso : in std_logic;
sclk : out std_logic;
rd : in std_logic;
wr : in std_logic;
dm_in : in std_logic; -- data mode, 0 = write continuously, 1 = write single block
reset : in std_logic;
din : in std_logic_vector(7 downto 0);
dout : out std_logic_vector(7 downto 0);
clk : in std_logic -- twice the SPI clk
);
end sd_controller;
architecture rtl of sd_controller is
type states is (
RST,
INIT,
CMD0,
CMD55,
CMD41,
POLL_CMD,
IDLE, -- wait for read or write pulse
READ_BLOCK,
READ_BLOCK_WAIT,
READ_BLOCK_DATA,
READ_BLOCK_CRC,
SEND_CMD,
RECEIVE_BYTE_WAIT,
RECEIVE_BYTE,
WRITE_BLOCK_CMD,
WRITE_BLOCK_INIT, -- initialise write command
WRITE_BLOCK_DATA, -- loop through all data bytes
WRITE_BLOCK_BYTE, -- send one byte
WRITE_BLOCK_WAIT -- wait until not busy
);
-- one start byte, plus 512 bytes of data, plus two FF end bytes (CRC)
constant WRITE_DATA_SIZE : integer := 515;
signal state, return_state : states;
signal sclk_sig : std_logic := '0';
signal cmd_out : std_logic_vector(55 downto 0);
signal recv_data : std_logic_vector(7 downto 0);
signal address : std_logic_vector(31 downto 0);
signal cmd_mode : std_logic := '1';
signal data_mode : std_logic := '1';
signal response_mode : std_logic := '1';
signal data_sig : std_logic_vector(7 downto 0) := x"00";
begin
process(clk,reset)
variable byte_counter : integer range 0 to WRITE_DATA_SIZE;
variable bit_counter : integer range 0 to 160;
begin
data_mode <= dm_in;
if rising_edge(clk) then
if (reset='1') then
state <= RST;
sclk_sig <= '0';
else
case state is
when RST =>
sclk_sig <= '0';
cmd_out <= (others => '1');
address <= x"00000000";
byte_counter := 0;
cmd_mode <= '1'; -- 0=data, 1=command
response_mode <= '1'; -- 0=data, 1=command
bit_counter := 160;
cs <= '1';
state <= INIT;
when INIT => -- CS=1, send 80 clocks, CS=0
if (bit_counter = 0) then
cs <= '0';
state <= CMD0;
else
bit_counter := bit_counter - 1;
sclk_sig <= not sclk_sig;
end if;
when CMD0 =>
cmd_out <= x"FF400000000095";
bit_counter := 55;
return_state <= CMD55;
state <= SEND_CMD;
when CMD55 =>
cmd_out <= x"FF770000000001"; -- 55d OR 40h = 77h
bit_counter := 55;
return_state <= CMD41;
state <= SEND_CMD;
when CMD41 =>
cmd_out <= x"FF690000000001"; -- 41d OR 40h = 69h
bit_counter := 55;
return_state <= POLL_CMD;
state <= SEND_CMD;
when POLL_CMD =>
if (recv_data(0) = '0') then
state <= IDLE;
else
state <= CMD55;
end if;
when IDLE =>
if (rd = '1') then
state <= READ_BLOCK;
elsif (wr='1') then
state <= WRITE_BLOCK_CMD;
else
state <= IDLE;
end if;
when READ_BLOCK =>
cmd_out <= x"FF" & x"51" & address & x"FF";
bit_counter := 55;
return_state <= READ_BLOCK_WAIT;
state <= SEND_CMD;
when READ_BLOCK_WAIT =>
if (sclk_sig='1' and miso='0') then
state <= READ_BLOCK_DATA;
byte_counter := 511;
bit_counter := 7;
return_state <= READ_BLOCK_DATA;
state <= RECEIVE_BYTE;
end if;
sclk_sig <= not sclk_sig;
when READ_BLOCK_DATA =>
if (byte_counter = 0) then
bit_counter := 7;
return_state <= READ_BLOCK_CRC;
state <= RECEIVE_BYTE;
else
byte_counter := byte_counter - 1;
return_state <= READ_BLOCK_DATA;
bit_counter := 7;
state <= RECEIVE_BYTE;
end if;
when READ_BLOCK_CRC =>
bit_counter := 7;
return_state <= IDLE;
address <= std_logic_vector(unsigned(address) + x"200");
state <= RECEIVE_BYTE;
when SEND_CMD =>
if (sclk_sig = '1') then
if (bit_counter = 0) then
state <= RECEIVE_BYTE_WAIT;
else
bit_counter := bit_counter - 1;
cmd_out <= cmd_out(54 downto 0) & '1';
end if;
end if;
sclk_sig <= not sclk_sig;
when RECEIVE_BYTE_WAIT =>
if (sclk_sig = '1') then
if (miso = '0') then
recv_data <= (others => '0');
if (response_mode='0') then
bit_counter := 3; -- already read bits 7..4
else
bit_counter := 6; -- already read bit 7
end if;
state <= RECEIVE_BYTE;
end if;
end if;
sclk_sig <= not sclk_sig;
when RECEIVE_BYTE =>
if (sclk_sig = '1') then
recv_data <= recv_data(6 downto 0) & miso;
if (bit_counter = 0) then
state <= return_state;
dout <= recv_data(6 downto 0) & miso;
else
bit_counter := bit_counter - 1;
end if;
end if;
sclk_sig <= not sclk_sig;
when WRITE_BLOCK_CMD =>
cmd_mode <= '1';
if (data_mode = '0') then
cmd_out <= x"FF" & x"59" & address & x"FF"; -- continuous
else
cmd_out <= x"FF" & x"58" & address & x"FF"; -- single block
end if;
bit_counter := 55;
return_state <= WRITE_BLOCK_INIT;
state <= SEND_CMD;
when WRITE_BLOCK_INIT =>
cmd_mode <= '0';
byte_counter := WRITE_DATA_SIZE;
state <= WRITE_BLOCK_DATA;
when WRITE_BLOCK_DATA =>
if byte_counter = 0 then
state <= RECEIVE_BYTE_WAIT;
return_state <= WRITE_BLOCK_WAIT;
response_mode <= '0';
else
if ((byte_counter = 2) or (byte_counter = 1)) then
data_sig <= x"FF"; -- two CRC bytes
elsif byte_counter = WRITE_DATA_SIZE then
if (data_mode='0') then
data_sig <= x"FC"; -- start byte, multiple blocks
else
data_sig <= x"FE"; -- start byte, single block
end if;
else
-- just a counter, get real data here
data_sig <= std_logic_vector(to_unsigned(byte_counter,8));
end if;
bit_counter := 7;
state <= WRITE_BLOCK_BYTE;
byte_counter := byte_counter - 1;
end if;
when WRITE_BLOCK_BYTE =>
if (sclk_sig = '1') then
if bit_counter=0 then
state <= WRITE_BLOCK_DATA;
else
data_sig <= data_sig(6 downto 0) & '1';
bit_counter := bit_counter - 1;
end if;
end if;
sclk_sig <= not sclk_sig;
when WRITE_BLOCK_WAIT =>
response_mode <= '1';
if sclk_sig='1' then
if MISO='1' then
if (data_mode='0') then
state <= WRITE_BLOCK_INIT;
else
address <= std_logic_vector(unsigned(address) + x"200");
state <= IDLE;
end if;
end if;
end if;
sclk_sig <= not sclk_sig;
when others => state <= IDLE;
end case;
end if;
end if;
end process;
sclk <= sclk_sig;
mosi <= cmd_out(55) when cmd_mode='1' else data_sig(7);
end rtl;
| mit | bdc2b23eb23188e67699b47c6b50e880 | 0.562692 | 3.03125 | false | false | false | false |
julioamerico/OpenCRC | src/SoC/component/Actel/SmartFusionMSS/MSS/2.5.106/mti/user_verilog/MSS_BFM_LIB/@f2@a@b/_primary.vhd | 3 | 4,112 | library verilog;
use verilog.vl_types.all;
entity F2AB is
generic(
WIDTH : integer := 32;
DAC_RESOLUTION : vl_logic_vector(5 downto 0) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0);
WARNING_MSGS_ON : integer := 1;
FAST_ADC_CONV_SIM: integer := 0;
ANALOG_QUAD_NUM : integer := 6;
ADC_NUM : integer := 3;
NUM_ADC_IN : integer := 5;
VAREF_INT : real := 2.560000
);
port(
AV1 : in vl_logic_vector(5 downto 0);
AV2 : in vl_logic_vector(5 downto 0);
AC : in vl_logic_vector(5 downto 0);
AT : in vl_logic_vector(5 downto 0);
ATGND_01 : in vl_logic;
ATGND_23 : in vl_logic;
ATGND_45 : in vl_logic;
VAREF : in vl_logic_vector(2 downto 0);
ADCGNDREF : in vl_logic;
ADC_VAREFSEL : in vl_logic;
ADC0 : in vl_logic_vector(3 downto 0);
ADC1 : in vl_logic_vector(3 downto 0);
ADC2 : in vl_logic_vector(3 downto 0);
DEN_ADC : in vl_logic_vector(11 downto 0);
ADC0_PWRDWN : in vl_logic;
ADC0_ADCRESET : in vl_logic;
ADC0_SYSCLK : in vl_logic;
ADC0_CHNUMBER : in vl_logic_vector(4 downto 0);
ADC0_MODE : in vl_logic_vector(3 downto 0);
ADC0_TVC : in vl_logic_vector(7 downto 0);
ADC0_STC : in vl_logic_vector(7 downto 0);
ADC0_ADCSTART : in vl_logic;
ADC1_PWRDWN : in vl_logic;
ADC1_ADCRESET : in vl_logic;
ADC1_SYSCLK : in vl_logic;
ADC1_CHNUMBER : in vl_logic_vector(4 downto 0);
ADC1_MODE : in vl_logic_vector(3 downto 0);
ADC1_TVC : in vl_logic_vector(7 downto 0);
ADC1_STC : in vl_logic_vector(7 downto 0);
ADC1_ADCSTART : in vl_logic;
ADC2_PWRDWN : in vl_logic;
ADC2_ADCRESET : in vl_logic;
ADC2_SYSCLK : in vl_logic;
ADC2_CHNUMBER : in vl_logic_vector(4 downto 0);
ADC2_MODE : in vl_logic_vector(3 downto 0);
ADC2_TVC : in vl_logic_vector(7 downto 0);
ADC2_STC : in vl_logic_vector(7 downto 0);
ADC2_ADCSTART : in vl_logic;
ACB_RST : in vl_logic;
ACB_WEN : in vl_logic;
ACB_ADDR : in vl_logic_vector(7 downto 0);
ACB_WDATA : in vl_logic_vector(7 downto 0);
ADC_VAREFOUT : out vl_logic;
ACB_RDATA : out vl_logic_vector(7 downto 0);
ADC0_BUSY : out vl_logic;
ADC0_CALIBRATE : out vl_logic;
ADC0_DATAVALID : out vl_logic;
ADC0_SAMPLE : out vl_logic;
ADC0_RESULT : out vl_logic_vector(11 downto 0);
ADC1_BUSY : out vl_logic;
ADC1_CALIBRATE : out vl_logic;
ADC1_DATAVALID : out vl_logic;
ADC1_SAMPLE : out vl_logic;
ADC1_RESULT : out vl_logic_vector(11 downto 0);
ADC2_BUSY : out vl_logic;
ADC2_CALIBRATE : out vl_logic;
ADC2_DATAVALID : out vl_logic;
ADC2_SAMPLE : out vl_logic;
ADC2_RESULT : out vl_logic_vector(11 downto 0);
DACOUT0 : out vl_logic;
DACOUT1 : out vl_logic;
DACOUT2 : out vl_logic;
DIG_ADC : out vl_logic_vector(11 downto 0);
OBD_DIN : in vl_logic_vector(2 downto 0);
OBD_CLKIN : in vl_logic_vector(2 downto 0);
OBD_ENABLE : in vl_logic_vector(2 downto 0);
COMPARATOR : out vl_logic_vector(11 downto 0)
);
attribute DAC_RESOLUTION_mti_vect_attrib : integer;
attribute DAC_RESOLUTION_mti_vect_attrib of DAC_RESOLUTION : constant is 0;
end F2AB;
| gpl-3.0 | 3fe136b20b8994836925b42066ffa37b | 0.486625 | 3.401158 | false | false | false | false |
Rookfighter/fft-spartan6 | fft/membank_tb.vhd | 1 | 4,297 | -- membank_tb.vhd
--
-- Created on: 15 Jul 2017
-- Author: Fabian Meyer
library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.fft_helpers.all;
entity membank_tb is
end entity;
architecture behavioral of membank_tb is
-- Component Declaration for the Unit Under Test (UUT)
component membank
generic(RSTDEF: std_logic := '0';
FFTEXP: natural := 4);
port(rst: in std_logic; -- reset, RSTDEF active
clk: in std_logic; -- clock, rising edge
swrst: in std_logic; -- software reset, RSTDEF active
en: in std_logic; -- enable, high active
addr1: in std_logic_vector(FFTEXP-1 downto 0); -- address1
addr2: in std_logic_vector(FFTEXP-1 downto 0); -- address2
en_wrt: in std_logic; -- write enable for bank1, high active
din1: in complex; -- input1 that will be stored
din2: in complex; -- input2 that will be stored
dout1: out complex; -- output1 that is read from memory
dout2: out complex); -- output2 that is read from memory
end component;
-- Clock period definitions
constant clk_period: time := 10 ns;
-- Generics
constant RSTDEF: std_logic := '0';
constant FFTEXP: natural := 3; -- 8-point FFT
-- Inputs
signal rst: std_logic := '0';
signal clk: std_logic := '0';
signal swrst: std_logic := '0';
signal en: std_logic := '0';
signal addr1: std_logic_vector(FFTEXP-1 downto 0) := (others => '0');
signal addr2: std_logic_vector(FFTEXP-1 downto 0) := (others => '0');
signal en_wrt: std_logic := '0';
signal din1: complex := COMPZERO;
signal din2: complex := COMPZERO;
-- Outputs
signal dout1: complex := COMPZERO;
signal dout2: complex := COMPZERO;
begin
-- Instantiate the Unit Under Test (UUT)
uut: membank
generic map(RSTDEF => RSTDEF,
FFTEXP => FFTEXP)
port map(rst => rst,
clk => clk,
swrst => swrst,
en => en,
addr1 => addr1,
addr2 => addr2,
en_wrt => en_wrt,
din1 => din1,
din2 => din2,
dout1 => dout1,
dout2 => dout2);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
procedure read_data(addr1_n, addr2_n: natural) is
begin
en_wrt <= '0';
addr1 <= std_logic_vector(to_unsigned(addr1_n, FFTEXP));
addr2 <= std_logic_vector(to_unsigned(addr2_n, FFTEXP));
wait for clk_period;
end procedure;
procedure write_data(addr1_n, addr2_n: natural;
dat1, dat2: complex) is
begin
en_wrt <= '1';
addr1 <= std_logic_vector(to_unsigned(addr1_n, FFTEXP));
addr2 <= std_logic_vector(to_unsigned(addr2_n, FFTEXP));
din1 <= dat1;
din2 <= dat2;
wait for clk_period;
end procedure;
constant test_data: complex_arr(0 to (2**FFTEXP)-1) := (
(X"000010",X"000100"),
(X"000001",X"000030"),
(X"000500",X"000001"),
(X"0000ff",X"0000f0"),
(X"000f01",X"000fff"),
(X"00055f",X"0001f5"),
(X"000110",X"00030f"),
(X"00001f",X"000105")
);
begin
-- hold reset state for 100 ns.
wait for clk_period*10;
rst <= '1';
swrst <= '1';
en <= '1';
for i in 0 to 3 loop
write_data(2*i, (2*i)+1, test_data(2*i), test_data((2*i)+1));
end loop;
for i in 0 to 3 loop
read_data(2*i, (2*i)+1);
end loop;
wait;
end process;
end;
| mit | fe787b18bd45a21dfdae06a5b0284707 | 0.486386 | 3.736522 | false | false | false | false |
kristofferkoch/ethersound | tb_txsync.vhd | 1 | 7,258 | -----------------------------------------------------------------------------
-- Testbench for txsync
--
-- Authors:
-- -- Kristoffer E. Koch
-----------------------------------------------------------------------------
-- Copyright 2008 Authors
--
-- This file is part of hwpulse.
--
-- hwpulse is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- hwpulse is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with hwpulse. If not, see <http://www.gnu.org/licenses/>.
-----------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY tb_txsync IS
END tb_txsync;
ARCHITECTURE behavior OF tb_txsync IS
-- polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
-- data width: 4
-- convention: the first serial data bit is D(3)
function nextCRC32_D4
( Data: std_logic_vector(3 downto 0);
CRC: std_logic_vector(31 downto 0) )
return std_logic_vector is
variable D: std_logic_vector(3 downto 0);
variable C: std_logic_vector(31 downto 0);
variable NewCRC: std_logic_vector(31 downto 0);
begin
for i in 0 to 3 loop
D(i) := Data(3-i);
end loop;
C := CRC;
NewCRC(0) := D(0) xor C(28);
NewCRC(1) := D(1) xor D(0) xor C(28) xor C(29);
NewCRC(2) := D(2) xor D(1) xor D(0) xor C(28) xor C(29) xor C(30);
NewCRC(3) := D(3) xor D(2) xor D(1) xor C(29) xor C(30) xor C(31);
NewCRC(4) := D(3) xor D(2) xor D(0) xor C(0) xor C(28) xor C(30) xor
C(31);
NewCRC(5) := D(3) xor D(1) xor D(0) xor C(1) xor C(28) xor C(29) xor
C(31);
NewCRC(6) := D(2) xor D(1) xor C(2) xor C(29) xor C(30);
NewCRC(7) := D(3) xor D(2) xor D(0) xor C(3) xor C(28) xor C(30) xor
C(31);
NewCRC(8) := D(3) xor D(1) xor D(0) xor C(4) xor C(28) xor C(29) xor
C(31);
NewCRC(9) := D(2) xor D(1) xor C(5) xor C(29) xor C(30);
NewCRC(10) := D(3) xor D(2) xor D(0) xor C(6) xor C(28) xor C(30) xor
C(31);
NewCRC(11) := D(3) xor D(1) xor D(0) xor C(7) xor C(28) xor C(29) xor
C(31);
NewCRC(12) := D(2) xor D(1) xor D(0) xor C(8) xor C(28) xor C(29) xor
C(30);
NewCRC(13) := D(3) xor D(2) xor D(1) xor C(9) xor C(29) xor C(30) xor
C(31);
NewCRC(14) := D(3) xor D(2) xor C(10) xor C(30) xor C(31);
NewCRC(15) := D(3) xor C(11) xor C(31);
NewCRC(16) := D(0) xor C(12) xor C(28);
NewCRC(17) := D(1) xor C(13) xor C(29);
NewCRC(18) := D(2) xor C(14) xor C(30);
NewCRC(19) := D(3) xor C(15) xor C(31);
NewCRC(20) := C(16);
NewCRC(21) := C(17);
NewCRC(22) := D(0) xor C(18) xor C(28);
NewCRC(23) := D(1) xor D(0) xor C(19) xor C(28) xor C(29);
NewCRC(24) := D(2) xor D(1) xor C(20) xor C(29) xor C(30);
NewCRC(25) := D(3) xor D(2) xor C(21) xor C(30) xor C(31);
NewCRC(26) := D(3) xor D(0) xor C(22) xor C(28) xor C(31);
NewCRC(27) := D(1) xor C(23) xor C(29);
NewCRC(28) := D(2) xor C(24) xor C(30);
NewCRC(29) := D(3) xor C(25) xor C(31);
NewCRC(30) := C(26);
NewCRC(31) := C(27);
return NewCRC;
end nextCRC32_D4;
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT txsync
PORT(
sysclk : IN std_logic;
reset : IN std_logic;
tx_clk : IN std_logic;
txd : OUT std_logic_vector(3 downto 0);
tx_dv : OUT std_logic;
data : IN std_logic_vector(7 downto 0);
data_send : IN std_logic;
data_req : OUT std_logic;
debug : out STD_LOGIC_VECTOR (7 downto 0)
);
END COMPONENT;
--Inputs
signal sysclk : std_logic := '0';
signal reset : std_logic := '0';
signal tx_clk : std_logic := '0';
signal data : std_logic_vector(7 downto 0) := (others => '0');
signal data_send : std_logic := '0';
--Outputs
signal txd : std_logic_vector(3 downto 0);
signal tx_dv : std_logic;
signal data_req : std_logic;
-- Clock period definitions
constant sysclk_period : time := 22 ns;
constant tx_clk_period : time := 40 ns;
signal done:boolean:=false;
signal pcount:integer;
type rxstate_t is (Idle, Preamble, Data0, Data1);
signal rxstate:rxstate_t;
signal crc:std_logic_vector(31 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
sync: txsync PORT MAP (
sysclk => sysclk,
reset => reset,
tx_clk => tx_clk,
txd => txd,
tx_dv => tx_dv,
data => data,
data_send => data_send,
data_req => data_req,
debug => open
);
-- Clock process definitions
sysclk_process :process
begin
if done then
wait;
else
sysclk <= '0';
wait for sysclk_period/2;
sysclk <= '1';
wait for sysclk_period/2;
end if;
end process;
tx_clk_process :process
begin
if done then
wait;
else
tx_clk <= '0';
wait for tx_clk_period/2;
tx_clk <= '1';
case rxstate is
when Idle =>
crc <= (OTHERS => '1');
if tx_dv = '1' then
if txd = x"5" then
rxstate <= Preamble;
pcount <= pcount + 1;
else
report "Received preamble other than 0x5.";
rxstate <= Preamble;
end if;
else
pcount <= 0;
end if;
when Preamble =>
if tx_dv = '1' then
if txd = x"d" then
rxstate <= Data0;
elsif txd = x"5" then
pcount <= pcount + 1;
else
report "Received preamble other than 0x5 or 0xD.";
end if;
end if;
when Data0 =>
if tx_dv = '1' then
rxstate <= Data1;
crc <= nextCRC32_D4(txd, crc);
else
report "Frame transfer complete.";
if crc = x"c704dd7b" then
report "CRC ok";
end if;
rxstate <= Idle;
end if;
when Data1 =>
if tx_dv = '1' then
rxstate <= Data0;
crc <= nextCRC32_D4(txd, crc);
else
report "Odd nibble received." severity warning;
rxstate <= Idle;
end if;
end case;
wait for tx_clk_period/2;
end if;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100ms.
reset <= '1';
data_send <= '0';
wait for sysclk_period*10;
reset <= '0';
-- insert stimulus here
if data_req = '1' then
wait until data_req = '0';
end if;wait until data_req = '1';wait for sysclk_period;
data_send <= '1';
data <= x"ba";
if data_req = '1' then
wait until data_req = '0';
end if;wait until data_req = '1';wait for sysclk_period;
data <= x"dc";
if data_req = '1' then
wait until data_req = '0';
end if;wait until data_req = '1';wait for sysclk_period;
data_send <= '0';
wait;
end process;
END;
| gpl-3.0 | 479b39eab66268bdc57ac14ff50325a2 | 0.536925 | 3.002896 | false | false | false | false |
kristofferkoch/ethersound | timer.vhd | 1 | 2,316 | -----------------------------------------------------------------------------
-- Adjustable timer-module. Provides a monotonic increasing tunable
-- clock
--
-- Authors:
-- -- Kristoffer E. Koch
-----------------------------------------------------------------------------
-- Copyright 2008 Authors
--
-- This file is part of hwpulse.
--
-- hwpulse is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- hwpulse is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with hwpulse. If not, see <http://www.gnu.org/licenses/>.
-----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
entity timer is
Generic(F_SYS:real:=50.0e6);
Port (
reset : in STD_LOGIC;
sysclk : in STD_LOGIC;
load : in unsigned (63 downto 0);
load_en : in STD_LOGIC;
time_o : out unsigned (63 downto 0);
ppm : in signed (9 downto 0)
);
end timer;
architecture Behavioral of timer is
constant PERIOD_ADD_R:real:=1048576.0e9/F_SYS;
constant PERIOD_ADD:signed(29 downto 0):=to_signed(integer(PERIOD_ADD_R),30);
constant PERIOD_MP_R:real:=1024.0e6/F_SYS;
constant PERIOD_MP:signed(10 downto 0):=to_signed(integer(PERIOD_MP_R), 11);
signal time_s:unsigned(83 downto 0); -- in nano-seconds/1024^2=~femto seconds
signal correction:signed(20 downto 0);
signal delta:unsigned(29 downto 0);
begin
time_o <= time_s(83 downto 20);
correction <= ppm*PERIOD_MP;
delta <= unsigned(PERIOD_ADD + correction);
process(reset, sysclk) is begin
if rising_edge(sysclk) then
if reset = '1' then
time_s <= (OTHERS => '0');
else
if load_en = '1' then
time_s(83 downto 20) <= load;
time_s(19 downto 0) <= (OTHERS => '0');
else
time_s <= time_s + delta;
end if;
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | 027ce524b3159d0d0dc8b32e6db06475 | 0.607513 | 3.451565 | false | false | false | false |
FinnK/lems2hdl | work/N3_pointCellCondBased/ISIM_output/reverseRatem1.vhdl | 1 | 10,652 |
---------------------------------------------------------------------
-- Standard Library bits
---------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- For Modelsim
--use ieee.fixed_pkg.all;
--use ieee.fixed_float_types.ALL;
-- For ISE
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use ieee_proposed.fixed_float_types.ALL;
use IEEE.numeric_std.all;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Entity Description
---------------------------------------------------------------------
entity reverseRatem1 is
Port (
clk : in STD_LOGIC; --SYSTEM CLOCK, THIS ITSELF DOES NOT SIGNIFY TIME STEPS - AKA A SINGLE TIMESTEP MAY TAKE MANY CLOCK CYCLES
init_model : in STD_LOGIC; --SYNCHRONOUS RESET
step_once_go : in STD_LOGIC; --signals to the neuron from the core that a time step is to be simulated
component_done : out STD_LOGIC;
requirement_voltage_v : in sfixed (2 downto -22);
param_per_time_rate : in sfixed (18 downto -2);
param_voltage_midpoint : in sfixed (2 downto -22);
param_voltage_scale : in sfixed (2 downto -22);
param_voltage_inv_scale_inv : in sfixed (22 downto -2);
exposure_per_time_r : out sfixed (18 downto -2);
derivedvariable_per_time_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_r_in : in sfixed (18 downto -2);
sysparam_time_timestep : in sfixed (-6 downto -22);
sysparam_time_simtime : in sfixed (6 downto -22)
);
end reverseRatem1;
---------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-- Architecture Begins
-------------------------------------------------------------------------------------------
architecture RTL of reverseRatem1 is
signal COUNT : unsigned(2 downto 0) := "000";
signal childrenCombined_Component_done_single_shot_fired : STD_LOGIC := '0';
signal childrenCombined_Component_done_single_shot : STD_LOGIC := '0';
signal childrenCombined_Component_done : STD_LOGIC := '0';
signal Component_done_int : STD_LOGIC := '0';
signal subprocess_der_int_pre_ready : STD_LOGIC := '0';
signal subprocess_der_int_ready : STD_LOGIC := '0';
signal subprocess_der_ready : STD_LOGIC := '0';
signal subprocess_dyn_int_pre_ready : STD_LOGIC := '0';
signal subprocess_dyn_int_ready : STD_LOGIC := '0';
signal subprocess_dyn_ready : STD_LOGIC := '0';
signal subprocess_model_ready : STD_LOGIC := '1';
signal subprocess_all_ready_shotdone : STD_LOGIC := '1';
signal subprocess_all_ready_shot : STD_LOGIC := '0';
signal subprocess_all_ready : STD_LOGIC := '0';signal pre_exp_r_exponential_result1 : sfixed(18 downto -13);
signal pre_exp_r_exponential_result1_next : sfixed(18 downto -13);
signal exp_r_exponential_result1 : sfixed(18 downto -13);
Component ParamExp is
generic(
BIT_TOP : integer := 20;
BIT_BOTTOM : integer := -20);
port(
clk : In Std_logic;
init_model : In Std_logic;
Start : In Std_logic;
Done : Out Std_logic;
X : In sfixed(BIT_TOP downto BIT_BOTTOM);
Output : Out sfixed(BIT_TOP downto BIT_BOTTOM)
);
end Component;
---------------------------------------------------------------------
-- Derived Variables and parameters
---------------------------------------------------------------------
signal DerivedVariable_per_time_r : sfixed (18 downto -2) := to_sfixed(0.0 ,18,-2);
signal DerivedVariable_per_time_r_next : sfixed (18 downto -2) := to_sfixed(0.0 ,18,-2);
---------------------------------------------------------------------
---------------------------------------------------------------------
-- EDState internal Variables
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Output Port internal Variables
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Child Components
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Begin Internal Processes
---------------------------------------------------------------------
begin
---------------------------------------------------------------------
-- Child EDComponent Instantiations and corresponding internal variables
---------------------------------------------------------------------
derived_variable_pre_process_comb :process ( sysparam_time_timestep, param_voltage_midpoint, param_voltage_scale, requirement_voltage_v , param_per_time_rate,param_voltage_inv_scale_inv,exp_r_exponential_result1 )
begin
pre_exp_r_exponential_result1_next <= resize( ( ( requirement_voltage_v - param_voltage_midpoint ) * param_voltage_inv_scale_inv ) ,18,-13);
end process derived_variable_pre_process_comb;
derived_variable_pre_process_syn :process ( clk, init_model )
begin
if (clk'EVENT AND clk = '1') then
if init_model = '1' then
pre_exp_r_exponential_result1 <= to_sfixed(0,18,-13);
else
if subprocess_all_ready_shot = '1' then
pre_exp_r_exponential_result1 <= pre_exp_r_exponential_result1_next;
end if;
end if;
end if;
subprocess_der_int_pre_ready <= '1';
end process derived_variable_pre_process_syn;
ParamExp_r_exponential_result1 : ParamExp
generic map(
BIT_TOP => 18,
BIT_BOTTOM => -13
)
port map ( clk => clk,
init_model => init_model,
Start => step_once_go,
Done => subprocess_der_int_ready,
X => pre_exp_r_exponential_result1 ,
Output => exp_r_exponential_result1
);
derived_variable_process_comb :process ( sysparam_time_timestep, param_voltage_midpoint, param_voltage_scale, requirement_voltage_v , param_per_time_rate,param_voltage_inv_scale_inv,exp_r_exponential_result1 )
begin
derivedvariable_per_time_r_next <= resize(( param_per_time_rate * exp_r_exponential_result1 ),18,-2);
subprocess_der_ready <= '1';
end process derived_variable_process_comb;
derived_variable_process_syn :process ( clk,init_model )
begin
if clk'event and clk = '1' then
if subprocess_all_ready_shot = '1' then
derivedvariable_per_time_r <= derivedvariable_per_time_r_next;
end if;
end if;
end process derived_variable_process_syn;
---------------------------------------------------------------------
dynamics_pre_process_comb :process ( sysparam_time_timestep )
begin
end process dynamics_pre_process_comb;
dynamics_pre_process_syn :process ( clk, init_model )
begin
subprocess_dyn_int_pre_ready <= '1';
end process dynamics_pre_process_syn;
--No dynamics with complex equations found
subprocess_dyn_int_ready <= '1';
state_variable_process_dynamics_comb :process (sysparam_time_timestep)
begin
subprocess_dyn_ready <= '1';
end process state_variable_process_dynamics_comb;
state_variable_process_dynamics_syn :process (CLK,init_model)
begin
if clk'event and clk = '1' then
if subprocess_all_ready_shot = '1' then
end if;
end if;
end process state_variable_process_dynamics_syn;
------------------------------------------------------------------------------------------------------
-- EDState Variable Drivers
------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign state variables to exposures
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign state variables to output state variables
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign derived variables to exposures
---------------------------------------------------------------------
exposure_per_time_r <= derivedvariable_per_time_r_in;derivedvariable_per_time_r_out <= derivedvariable_per_time_r;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Subprocess ready process
---------------------------------------------------------------------
subprocess_all_ready_process: process(step_once_go,subprocess_der_int_ready,subprocess_der_int_pre_ready,subprocess_der_ready,subprocess_dyn_int_pre_ready,subprocess_dyn_int_ready,subprocess_dyn_ready,subprocess_model_ready)
begin
if step_once_go = '0' and subprocess_der_int_ready = '1' and subprocess_der_int_pre_ready = '1'and subprocess_der_ready ='1' and subprocess_dyn_int_ready = '1' and subprocess_dyn_int_pre_ready = '1' and subprocess_dyn_ready = '1' and subprocess_model_ready = '1' then
subprocess_all_ready <= '1';
else
subprocess_all_ready <= '0';
end if;
end process subprocess_all_ready_process;
subprocess_all_ready_shot_process : process(clk)
begin
if rising_edge(clk) then
if (init_model='1') then
subprocess_all_ready_shot <= '0';
subprocess_all_ready_shotdone <= '1';
else
if subprocess_all_ready = '1' and subprocess_all_ready_shotdone = '0' then
subprocess_all_ready_shot <= '1';
subprocess_all_ready_shotdone <= '1';
elsif subprocess_all_ready_shot = '1' then
subprocess_all_ready_shot <= '0';
elsif subprocess_all_ready = '0' then
subprocess_all_ready_shot <= '0';
subprocess_all_ready_shotdone <= '0';
end if;
end if;
end if;
end process subprocess_all_ready_shot_process;
---------------------------------------------------------------------
count_proc:process(clk)
begin
if (clk'EVENT AND clk = '1') then
if init_model = '1' then COUNT <= "001";
component_done_int <= '1';
else if step_once_go = '1' then
COUNT <= "000";
component_done_int <= '0';
elsif COUNT = "001" then
component_done_int <= '1';
elsif subprocess_all_ready_shot = '1' then
COUNT <= COUNT + 1;
component_done_int <= '0';
end if;
end if;
end if;
end process count_proc;
component_done <= component_done_int;
end RTL;
| lgpl-3.0 | 7ad3a6d93435dae0e75615cc3587579c | 0.506947 | 4.08906 | false | false | false | false |
kristofferkoch/ethersound | txsync.vhd | 1 | 4,113 | -----------------------------------------------------------------------------
-- Module for transmitting data from the 50MHz byte-format to the 25MHz
-- PHY nibble-format. Adds preamble, SFD and CRC.
--
-- Authors:
-- -- Kristoffer E. Koch
-----------------------------------------------------------------------------
-- Copyright 2008 Authors
--
-- This file is part of hwpulse.
--
-- hwpulse is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- hwpulse is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with hwpulse. If not, see <http://www.gnu.org/licenses/>.
-----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.crc.all;
entity txsync is
Port ( sysclk : in STD_LOGIC;
reset : in STD_LOGIC;
tx_clk : in STD_LOGIC;
txd : out STD_LOGIC_VECTOR (3 downto 0);
tx_dv : out STD_LOGIC;
data : in STD_LOGIC_VECTOR (7 downto 0);
data_send : in STD_LOGIC;
data_req : out STD_LOGIC;
debug:out std_logic_vector(7 downto 0)
);
end txsync;
architecture RTL of txsync is
signal byte_latch:std_logic_vector(7 downto 0):=(OTHERS => '0');
signal req:std_logic:='0';
signal req_ccd:std_logic_vector(2 downto 0):=(OTHERS => '0');
type state_t is (Idle, IdleWait, Preamble, SFD, Data0, Data1, stCRC);
signal state, nextstate:state_t:=Idle;
signal count:integer range 0 to 14:=0;
signal rst:std_logic;
signal tx_dv_d:std_logic;
signal crcnibble, txd_d:std_logic_vector(3 downto 0);
signal crc, nextcrc:std_logic_vector(31 downto 0);
begin
rst <= reset;
data_req <= '1' when req_ccd(2) /= req_ccd(1) else '0';
req_synchronizer:process(sysclk) is
begin
if rising_edge(sysclk) then
if rst = '1' then
req_ccd <= (OTHERS => '0');
else
req_ccd(0) <= req;
req_ccd(1) <= req_ccd(0);
req_ccd(2) <= req_ccd(1);
end if;
end if;
end process;
crcnibble(0) <= crc(31);
crcnibble(1) <= crc(30);
crcnibble(2) <= crc(29);
crcnibble(3) <= crc(28);
txd_d <= x"5" when state = Preamble
else x"d" when state = SFD
else byte_latch(3 downto 0) when state = Data0
else byte_latch(7 downto 4) when state = Data1
else not crcnibble when state = stCRC
else "0000";
tx_dv_d <= '1' when state /= Idle and state /= IdleWait else '0';
txreg:process(tx_clk) begin
if rising_edge(tx_clk) then
if rst = '1' then
txd <= "0000";
tx_dv <= '0';
else
txd <= txd_d;
tx_dv <= tx_dv_d;
end if;
end if;
end process;
nextcrc <= Crc32_4(txd_d, crc, '1') when state = Data0 or state = Data1
else Crc32_4("0000", crc, '0') when state = stCRC
else (OTHERS => '1');
nextstate <= IdleWait when (state = Idle and data_send = '0')
else Preamble when (state = Idle or (state=Preamble and count /= 0))
else SFD when state = Preamble
else Data0 when (state = SFD or (state = Data1 and data_send = '1'))
else Data1 when state = Data0
else stCRC when (state = Data1 or (state=stCRC and count /= 0))
else Idle;
process(tx_clk) begin
if rising_edge(tx_clk) then
if rst = '1' then
crc <= (OTHERS => '1');
state <= Idle;
byte_latch <= x"00";
req <= '0';
else
crc <= nextcrc;
state <= nextstate;
if state = Idle then
count <= 14;
elsif state = Data1 or state = Data0 then
count <= 7;
elsif count /= 0 then
count <= count - 1;
end if;
if state = IdleWait or state = Data1 then
byte_latch <= data;
req <= not req;
end if;
end if;
end if;
end process;
end RTL; | gpl-3.0 | 8d43a3f0fb11fbd9ba2a642768c86570 | 0.581327 | 3.130137 | false | false | false | false |
FinnK/lems2hdl | work/N3_pointCellCondBased/ISIM_output/neuron_model.vhdl | 1 | 45,106 |
---------------------------------------------------------------------
-- Standard Library bits
---------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- For Modelsim
--use ieee.fixed_pkg.all;
--use ieee.fixed_float_types.ALL;
-- For ISE
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use ieee_proposed.fixed_float_types.ALL;
use IEEE.numeric_std.all;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Entity Description
---------------------------------------------------------------------
entity neuron_model is
Port (
clk : in STD_LOGIC; --SYSTEM CLOCK, THIS ITSELF DOES NOT SIGNIFY TIME STEPS - AKA A SINGLE TIMESTEP MAY TAKE MANY CLOCK CYCLES
init_model : in STD_LOGIC; --SYNCHRONOUS RESET
step_once_go : in STD_LOGIC; --signals to the neuron from the core that a time step is to be simulated
step_once_complete : out STD_LOGIC; --signals to the core that a time step has finished
eventport_in_spike_aggregate : in STD_LOGIC_VECTOR(511 downto 0);
eventport_out_spike : out STD_LOGIC;
param_voltage_v0 : in sfixed (2 downto -22);
param_voltage_thresh : in sfixed (2 downto -22);
param_capacitance_C : in sfixed (-33 downto -47);
param_capacitance_inv_C_inv : in sfixed (47 downto 33);
exposure_voltage_v : out sfixed (2 downto -22);
statevariable_voltage_v_out : out sfixed (2 downto -22);
statevariable_voltage_v_in : in sfixed (2 downto -22);
statevariable_none_spiking_out : out sfixed (18 downto -13);
statevariable_none_spiking_in : in sfixed (18 downto -13);
param_none_leak_number : in sfixed (18 downto -13);
param_voltage_leak_erev : in sfixed (2 downto -22);
exposure_current_leak_i : out sfixed (-28 downto -53);
derivedvariable_current_leak_i_out : out sfixed (-28 downto -53);
derivedvariable_current_leak_i_in : in sfixed (-28 downto -53);
param_conductance_leak_passive_conductance : in sfixed (-22 downto -53);
exposure_conductance_leak_passive_g : out sfixed (-22 downto -53);
derivedvariable_conductance_leak_passive_g_out : out sfixed (-22 downto -53);
derivedvariable_conductance_leak_passive_g_in : in sfixed (-22 downto -53);
param_none_naChans_number : in sfixed (18 downto -13);
param_voltage_naChans_erev : in sfixed (2 downto -22);
exposure_current_naChans_i : out sfixed (-28 downto -53);
derivedvariable_current_naChans_i_out : out sfixed (-28 downto -53);
derivedvariable_current_naChans_i_in : in sfixed (-28 downto -53);
param_conductance_naChans_na_conductance : in sfixed (-22 downto -53);
exposure_conductance_naChans_na_g : out sfixed (-22 downto -53);
derivedvariable_conductance_naChans_na_g_out : out sfixed (-22 downto -53);
derivedvariable_conductance_naChans_na_g_in : in sfixed (-22 downto -53);
param_none_naChans_na_m_instances : in sfixed (18 downto -13);
exposure_none_naChans_na_m_fcond : out sfixed (18 downto -13);
exposure_none_naChans_na_m_q : out sfixed (18 downto -13);
statevariable_none_naChans_na_m_q_out : out sfixed (18 downto -13);
statevariable_none_naChans_na_m_q_in : in sfixed (18 downto -13);
derivedvariable_none_naChans_na_m_fcond_out : out sfixed (18 downto -13);
derivedvariable_none_naChans_na_m_fcond_in : in sfixed (18 downto -13);
param_per_time_naChans_na_m_forwardRatem1_rate : in sfixed (18 downto -2);
param_voltage_naChans_na_m_forwardRatem1_midpoint : in sfixed (2 downto -22);
param_voltage_naChans_na_m_forwardRatem1_scale : in sfixed (2 downto -22);
param_voltage_inv_naChans_na_m_forwardRatem1_scale_inv : in sfixed (22 downto -2);
exposure_per_time_naChans_na_m_forwardRatem1_r : out sfixed (18 downto -2);
derivedvariable_per_time_naChans_na_m_forwardRatem1_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_naChans_na_m_forwardRatem1_r_in : in sfixed (18 downto -2);
param_per_time_naChans_na_m_reverseRatem1_rate : in sfixed (18 downto -2);
param_voltage_naChans_na_m_reverseRatem1_midpoint : in sfixed (2 downto -22);
param_voltage_naChans_na_m_reverseRatem1_scale : in sfixed (2 downto -22);
param_voltage_inv_naChans_na_m_reverseRatem1_scale_inv : in sfixed (22 downto -2);
exposure_per_time_naChans_na_m_reverseRatem1_r : out sfixed (18 downto -2);
derivedvariable_per_time_naChans_na_m_reverseRatem1_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_naChans_na_m_reverseRatem1_r_in : in sfixed (18 downto -2);
param_none_naChans_na_h_instances : in sfixed (18 downto -13);
exposure_none_naChans_na_h_fcond : out sfixed (18 downto -13);
exposure_none_naChans_na_h_q : out sfixed (18 downto -13);
statevariable_none_naChans_na_h_q_out : out sfixed (18 downto -13);
statevariable_none_naChans_na_h_q_in : in sfixed (18 downto -13);
derivedvariable_none_naChans_na_h_fcond_out : out sfixed (18 downto -13);
derivedvariable_none_naChans_na_h_fcond_in : in sfixed (18 downto -13);
param_per_time_naChans_na_h_forwardRateh1_rate : in sfixed (18 downto -2);
param_voltage_naChans_na_h_forwardRateh1_midpoint : in sfixed (2 downto -22);
param_voltage_naChans_na_h_forwardRateh1_scale : in sfixed (2 downto -22);
param_voltage_inv_naChans_na_h_forwardRateh1_scale_inv : in sfixed (22 downto -2);
exposure_per_time_naChans_na_h_forwardRateh1_r : out sfixed (18 downto -2);
derivedvariable_per_time_naChans_na_h_forwardRateh1_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_naChans_na_h_forwardRateh1_r_in : in sfixed (18 downto -2);
param_per_time_naChans_na_h_reverseRateh1_rate : in sfixed (18 downto -2);
param_voltage_naChans_na_h_reverseRateh1_midpoint : in sfixed (2 downto -22);
param_voltage_naChans_na_h_reverseRateh1_scale : in sfixed (2 downto -22);
param_voltage_inv_naChans_na_h_reverseRateh1_scale_inv : in sfixed (22 downto -2);
exposure_per_time_naChans_na_h_reverseRateh1_r : out sfixed (18 downto -2);
derivedvariable_per_time_naChans_na_h_reverseRateh1_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_naChans_na_h_reverseRateh1_r_in : in sfixed (18 downto -2);
param_none_kChans_number : in sfixed (18 downto -13);
param_voltage_kChans_erev : in sfixed (2 downto -22);
exposure_current_kChans_i : out sfixed (-28 downto -53);
derivedvariable_current_kChans_i_out : out sfixed (-28 downto -53);
derivedvariable_current_kChans_i_in : in sfixed (-28 downto -53);
param_conductance_kChans_k_conductance : in sfixed (-22 downto -53);
exposure_conductance_kChans_k_g : out sfixed (-22 downto -53);
derivedvariable_conductance_kChans_k_g_out : out sfixed (-22 downto -53);
derivedvariable_conductance_kChans_k_g_in : in sfixed (-22 downto -53);
param_none_kChans_k_n_instances : in sfixed (18 downto -13);
exposure_none_kChans_k_n_fcond : out sfixed (18 downto -13);
exposure_none_kChans_k_n_q : out sfixed (18 downto -13);
statevariable_none_kChans_k_n_q_out : out sfixed (18 downto -13);
statevariable_none_kChans_k_n_q_in : in sfixed (18 downto -13);
derivedvariable_none_kChans_k_n_fcond_out : out sfixed (18 downto -13);
derivedvariable_none_kChans_k_n_fcond_in : in sfixed (18 downto -13);
param_per_time_kChans_k_n_forwardRaten1_rate : in sfixed (18 downto -2);
param_voltage_kChans_k_n_forwardRaten1_midpoint : in sfixed (2 downto -22);
param_voltage_kChans_k_n_forwardRaten1_scale : in sfixed (2 downto -22);
param_voltage_inv_kChans_k_n_forwardRaten1_scale_inv : in sfixed (22 downto -2);
exposure_per_time_kChans_k_n_forwardRaten1_r : out sfixed (18 downto -2);
derivedvariable_per_time_kChans_k_n_forwardRaten1_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_kChans_k_n_forwardRaten1_r_in : in sfixed (18 downto -2);
param_per_time_kChans_k_n_reverseRaten1_rate : in sfixed (18 downto -2);
param_voltage_kChans_k_n_reverseRaten1_midpoint : in sfixed (2 downto -22);
param_voltage_kChans_k_n_reverseRaten1_scale : in sfixed (2 downto -22);
param_voltage_inv_kChans_k_n_reverseRaten1_scale_inv : in sfixed (22 downto -2);
exposure_per_time_kChans_k_n_reverseRaten1_r : out sfixed (18 downto -2);
derivedvariable_per_time_kChans_k_n_reverseRaten1_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_kChans_k_n_reverseRaten1_r_in : in sfixed (18 downto -2);
param_time_synapsemodel_tauDecay : in sfixed (6 downto -18);
param_conductance_synapsemodel_gbase : in sfixed (-22 downto -53);
param_voltage_synapsemodel_erev : in sfixed (2 downto -22);
param_time_inv_synapsemodel_tauDecay_inv : in sfixed (18 downto -6);
exposure_current_synapsemodel_i : out sfixed (-28 downto -53);
exposure_conductance_synapsemodel_g : out sfixed (-22 downto -53);
statevariable_conductance_synapsemodel_g_out : out sfixed (-22 downto -53);
statevariable_conductance_synapsemodel_g_in : in sfixed (-22 downto -53);
derivedvariable_current_synapsemodel_i_out : out sfixed (-28 downto -53);
derivedvariable_current_synapsemodel_i_in : in sfixed (-28 downto -53);
sysparam_time_timestep : in sfixed (-6 downto -22);
sysparam_time_simtime : in sfixed (6 downto -22)
);
end neuron_model;
---------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-- Architecture Begins
-------------------------------------------------------------------------------------------
architecture RTL of neuron_model is
signal COUNT : unsigned(2 downto 0) := "000";
signal childrenCombined_Component_done_single_shot_fired : STD_LOGIC := '0';
signal childrenCombined_Component_done_single_shot : STD_LOGIC := '0';
signal childrenCombined_Component_done : STD_LOGIC := '0';
signal Component_done_int : STD_LOGIC := '0';
signal subprocess_der_int_pre_ready : STD_LOGIC := '0';
signal subprocess_der_int_ready : STD_LOGIC := '0';
signal subprocess_der_ready : STD_LOGIC := '0';
signal subprocess_dyn_int_pre_ready : STD_LOGIC := '0';
signal subprocess_dyn_int_ready : STD_LOGIC := '0';
signal subprocess_dyn_ready : STD_LOGIC := '0';
signal subprocess_model_ready : STD_LOGIC := '1';
signal subprocess_all_ready_shotdone : STD_LOGIC := '1';
signal subprocess_all_ready_shot : STD_LOGIC := '0';
signal subprocess_all_ready : STD_LOGIC := '0';signal synapsemodel_step_once_complete_fired : STD_LOGIC := '1';
signal step_once_complete_fired : STD_LOGIC := '1';
signal Component_done : STD_LOGIC := '0';
constant cNSpikeSources : integer := 512; -- The number of spike sources.
constant cNOutputs : integer := 512; -- The number of Synapses in the neuron model.
constant cNSelectBits : integer := 9; -- Log2(NOutputs), rounded up.
signal SpikeOut : Std_logic_vector((cNOutputs-1) downto 0);
signal statevariable_voltage_noregime_v_temp_1 : sfixed (2 downto -22);
signal statevariable_voltage_noregime_v_temp_1_next : sfixed (2 downto -22);
---------------------------------------------------------------------
-- Derived Variables and parameters
---------------------------------------------------------------------
signal DerivedVariable_current_iChannels : sfixed (-28 downto -53) := to_sfixed(0.0 ,-28,-53);
signal DerivedVariable_current_iChannels_next : sfixed (-28 downto -53) := to_sfixed(0.0 ,-28,-53);
signal DerivedVariable_current_iSyn : sfixed (-28 downto -53) := to_sfixed(0.0 ,-28,-53);
signal DerivedVariable_current_iSyn_next : sfixed (-28 downto -53) := to_sfixed(0.0 ,-28,-53);
signal DerivedVariable_current_iMemb : sfixed (-28 downto -53) := to_sfixed(0.0 ,-28,-53);
signal DerivedVariable_current_iMemb_next : sfixed (-28 downto -53) := to_sfixed(0.0 ,-28,-53);
---------------------------------------------------------------------
---------------------------------------------------------------------
-- EDState internal Variables
---------------------------------------------------------------------
signal statevariable_voltage_v_next : sfixed (2 downto -22);
signal statevariable_none_spiking_next : sfixed (18 downto -13);
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Output Port internal Variables
---------------------------------------------------------------------
signal EventPort_out_spike_internal : std_logic := '0';
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Child Components
---------------------------------------------------------------------
component leak
Port (
clk : in STD_LOGIC; --SYSTEM CLOCK, THIS ITSELF DOES NOT SIGNIFY TIME STEPS - AKA A SINGLE TIMESTEP MAY TAKE MANY CLOCK CYCLES
init_model : in STD_LOGIC;
step_once_go : in STD_LOGIC; --signals to the neuron from the core that a time step is to be simulated
Component_done : out STD_LOGIC;
requirement_voltage_v : in sfixed (2 downto -22);
param_none_number : in sfixed (18 downto -13);
param_voltage_erev : in sfixed (2 downto -22);
exposure_current_i : out sfixed (-28 downto -53);
derivedvariable_current_i_out : out sfixed (-28 downto -53);
derivedvariable_current_i_in : in sfixed (-28 downto -53);
param_conductance_passive_conductance : in sfixed (-22 downto -53);
exposure_conductance_passive_g : out sfixed (-22 downto -53);
derivedvariable_conductance_passive_g_out : out sfixed (-22 downto -53);
derivedvariable_conductance_passive_g_in : in sfixed (-22 downto -53);
sysparam_time_timestep : in sfixed (-6 downto -22);
sysparam_time_simtime : in sfixed (6 downto -22)
);
end component;
signal leak_Component_done : STD_LOGIC ; signal Exposure_current_leak_i_internal : sfixed (-28 downto -53);
signal Exposure_conductance_leak_passive_g_internal : sfixed (-22 downto -53);
---------------------------------------------------------------------
component naChans
Port (
clk : in STD_LOGIC; --SYSTEM CLOCK, THIS ITSELF DOES NOT SIGNIFY TIME STEPS - AKA A SINGLE TIMESTEP MAY TAKE MANY CLOCK CYCLES
init_model : in STD_LOGIC;
step_once_go : in STD_LOGIC; --signals to the neuron from the core that a time step is to be simulated
Component_done : out STD_LOGIC;
requirement_voltage_v : in sfixed (2 downto -22);
param_none_number : in sfixed (18 downto -13);
param_voltage_erev : in sfixed (2 downto -22);
exposure_current_i : out sfixed (-28 downto -53);
derivedvariable_current_i_out : out sfixed (-28 downto -53);
derivedvariable_current_i_in : in sfixed (-28 downto -53);
param_conductance_na_conductance : in sfixed (-22 downto -53);
exposure_conductance_na_g : out sfixed (-22 downto -53);
derivedvariable_conductance_na_g_out : out sfixed (-22 downto -53);
derivedvariable_conductance_na_g_in : in sfixed (-22 downto -53);
param_none_na_m_instances : in sfixed (18 downto -13);
exposure_none_na_m_fcond : out sfixed (18 downto -13);
exposure_none_na_m_q : out sfixed (18 downto -13);
statevariable_none_na_m_q_out : out sfixed (18 downto -13);
statevariable_none_na_m_q_in : in sfixed (18 downto -13);
derivedvariable_none_na_m_fcond_out : out sfixed (18 downto -13);
derivedvariable_none_na_m_fcond_in : in sfixed (18 downto -13);
param_per_time_na_m_forwardRatem1_rate : in sfixed (18 downto -2);
param_voltage_na_m_forwardRatem1_midpoint : in sfixed (2 downto -22);
param_voltage_na_m_forwardRatem1_scale : in sfixed (2 downto -22);
param_voltage_inv_na_m_forwardRatem1_scale_inv : in sfixed (22 downto -2);
exposure_per_time_na_m_forwardRatem1_r : out sfixed (18 downto -2);
derivedvariable_per_time_na_m_forwardRatem1_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_na_m_forwardRatem1_r_in : in sfixed (18 downto -2);
param_per_time_na_m_reverseRatem1_rate : in sfixed (18 downto -2);
param_voltage_na_m_reverseRatem1_midpoint : in sfixed (2 downto -22);
param_voltage_na_m_reverseRatem1_scale : in sfixed (2 downto -22);
param_voltage_inv_na_m_reverseRatem1_scale_inv : in sfixed (22 downto -2);
exposure_per_time_na_m_reverseRatem1_r : out sfixed (18 downto -2);
derivedvariable_per_time_na_m_reverseRatem1_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_na_m_reverseRatem1_r_in : in sfixed (18 downto -2);
param_none_na_h_instances : in sfixed (18 downto -13);
exposure_none_na_h_fcond : out sfixed (18 downto -13);
exposure_none_na_h_q : out sfixed (18 downto -13);
statevariable_none_na_h_q_out : out sfixed (18 downto -13);
statevariable_none_na_h_q_in : in sfixed (18 downto -13);
derivedvariable_none_na_h_fcond_out : out sfixed (18 downto -13);
derivedvariable_none_na_h_fcond_in : in sfixed (18 downto -13);
param_per_time_na_h_forwardRateh1_rate : in sfixed (18 downto -2);
param_voltage_na_h_forwardRateh1_midpoint : in sfixed (2 downto -22);
param_voltage_na_h_forwardRateh1_scale : in sfixed (2 downto -22);
param_voltage_inv_na_h_forwardRateh1_scale_inv : in sfixed (22 downto -2);
exposure_per_time_na_h_forwardRateh1_r : out sfixed (18 downto -2);
derivedvariable_per_time_na_h_forwardRateh1_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_na_h_forwardRateh1_r_in : in sfixed (18 downto -2);
param_per_time_na_h_reverseRateh1_rate : in sfixed (18 downto -2);
param_voltage_na_h_reverseRateh1_midpoint : in sfixed (2 downto -22);
param_voltage_na_h_reverseRateh1_scale : in sfixed (2 downto -22);
param_voltage_inv_na_h_reverseRateh1_scale_inv : in sfixed (22 downto -2);
exposure_per_time_na_h_reverseRateh1_r : out sfixed (18 downto -2);
derivedvariable_per_time_na_h_reverseRateh1_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_na_h_reverseRateh1_r_in : in sfixed (18 downto -2);
sysparam_time_timestep : in sfixed (-6 downto -22);
sysparam_time_simtime : in sfixed (6 downto -22)
);
end component;
signal naChans_Component_done : STD_LOGIC ; signal Exposure_current_naChans_i_internal : sfixed (-28 downto -53);
signal Exposure_conductance_naChans_na_g_internal : sfixed (-22 downto -53);
signal Exposure_none_naChans_na_m_fcond_internal : sfixed (18 downto -13);
signal Exposure_none_naChans_na_m_q_internal : sfixed (18 downto -13);
signal Exposure_per_time_naChans_na_m_forwardRatem1_r_internal : sfixed (18 downto -2);
signal Exposure_per_time_naChans_na_m_reverseRatem1_r_internal : sfixed (18 downto -2);
signal Exposure_none_naChans_na_h_fcond_internal : sfixed (18 downto -13);
signal Exposure_none_naChans_na_h_q_internal : sfixed (18 downto -13);
signal Exposure_per_time_naChans_na_h_forwardRateh1_r_internal : sfixed (18 downto -2);
signal Exposure_per_time_naChans_na_h_reverseRateh1_r_internal : sfixed (18 downto -2);
---------------------------------------------------------------------
component kChans
Port (
clk : in STD_LOGIC; --SYSTEM CLOCK, THIS ITSELF DOES NOT SIGNIFY TIME STEPS - AKA A SINGLE TIMESTEP MAY TAKE MANY CLOCK CYCLES
init_model : in STD_LOGIC;
step_once_go : in STD_LOGIC; --signals to the neuron from the core that a time step is to be simulated
Component_done : out STD_LOGIC;
requirement_voltage_v : in sfixed (2 downto -22);
param_none_number : in sfixed (18 downto -13);
param_voltage_erev : in sfixed (2 downto -22);
exposure_current_i : out sfixed (-28 downto -53);
derivedvariable_current_i_out : out sfixed (-28 downto -53);
derivedvariable_current_i_in : in sfixed (-28 downto -53);
param_conductance_k_conductance : in sfixed (-22 downto -53);
exposure_conductance_k_g : out sfixed (-22 downto -53);
derivedvariable_conductance_k_g_out : out sfixed (-22 downto -53);
derivedvariable_conductance_k_g_in : in sfixed (-22 downto -53);
param_none_k_n_instances : in sfixed (18 downto -13);
exposure_none_k_n_fcond : out sfixed (18 downto -13);
exposure_none_k_n_q : out sfixed (18 downto -13);
statevariable_none_k_n_q_out : out sfixed (18 downto -13);
statevariable_none_k_n_q_in : in sfixed (18 downto -13);
derivedvariable_none_k_n_fcond_out : out sfixed (18 downto -13);
derivedvariable_none_k_n_fcond_in : in sfixed (18 downto -13);
param_per_time_k_n_forwardRaten1_rate : in sfixed (18 downto -2);
param_voltage_k_n_forwardRaten1_midpoint : in sfixed (2 downto -22);
param_voltage_k_n_forwardRaten1_scale : in sfixed (2 downto -22);
param_voltage_inv_k_n_forwardRaten1_scale_inv : in sfixed (22 downto -2);
exposure_per_time_k_n_forwardRaten1_r : out sfixed (18 downto -2);
derivedvariable_per_time_k_n_forwardRaten1_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_k_n_forwardRaten1_r_in : in sfixed (18 downto -2);
param_per_time_k_n_reverseRaten1_rate : in sfixed (18 downto -2);
param_voltage_k_n_reverseRaten1_midpoint : in sfixed (2 downto -22);
param_voltage_k_n_reverseRaten1_scale : in sfixed (2 downto -22);
param_voltage_inv_k_n_reverseRaten1_scale_inv : in sfixed (22 downto -2);
exposure_per_time_k_n_reverseRaten1_r : out sfixed (18 downto -2);
derivedvariable_per_time_k_n_reverseRaten1_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_k_n_reverseRaten1_r_in : in sfixed (18 downto -2);
sysparam_time_timestep : in sfixed (-6 downto -22);
sysparam_time_simtime : in sfixed (6 downto -22)
);
end component;
signal kChans_Component_done : STD_LOGIC ; signal Exposure_current_kChans_i_internal : sfixed (-28 downto -53);
signal Exposure_conductance_kChans_k_g_internal : sfixed (-22 downto -53);
signal Exposure_none_kChans_k_n_fcond_internal : sfixed (18 downto -13);
signal Exposure_none_kChans_k_n_q_internal : sfixed (18 downto -13);
signal Exposure_per_time_kChans_k_n_forwardRaten1_r_internal : sfixed (18 downto -2);
signal Exposure_per_time_kChans_k_n_reverseRaten1_r_internal : sfixed (18 downto -2);
---------------------------------------------------------------------
component synapsemodel
Port (
clk : in STD_LOGIC; --SYSTEM CLOCK, THIS ITSELF DOES NOT SIGNIFY TIME STEPS - AKA A SINGLE TIMESTEP MAY TAKE MANY CLOCK CYCLES
init_model : in STD_LOGIC;
step_once_go : in STD_LOGIC; --signals to the neuron from the core that a time step is to be simulated
Component_done : out STD_LOGIC;
eventport_in_in : in STD_LOGIC;
requirement_voltage_v : in sfixed (2 downto -22);
param_time_tauDecay : in sfixed (6 downto -18);
param_conductance_gbase : in sfixed (-22 downto -53);
param_voltage_erev : in sfixed (2 downto -22);
param_time_inv_tauDecay_inv : in sfixed (18 downto -6);
exposure_current_i : out sfixed (-28 downto -53);
exposure_conductance_g : out sfixed (-22 downto -53);
statevariable_conductance_g_out : out sfixed (-22 downto -53);
statevariable_conductance_g_in : in sfixed (-22 downto -53);
derivedvariable_current_i_out : out sfixed (-28 downto -53);
derivedvariable_current_i_in : in sfixed (-28 downto -53);
sysparam_time_timestep : in sfixed (-6 downto -22);
sysparam_time_simtime : in sfixed (6 downto -22)
);
end component;
signal synapsemodel_Component_done : STD_LOGIC ; signal Exposure_current_synapsemodel_i_internal : sfixed (-28 downto -53);
signal Exposure_conductance_synapsemodel_g_internal : sfixed (-22 downto -53);
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Begin Internal Processes
---------------------------------------------------------------------
begin
---------------------------------------------------------------------
-- Child EDComponent Instantiations and corresponding internal variables
---------------------------------------------------------------------
leak_uut : leak
port map (
clk => clk,
init_model => init_model,
step_once_go => step_once_go,
Component_done => leak_Component_done,
param_none_number => param_none_leak_number,
param_voltage_erev => param_voltage_leak_erev,
requirement_voltage_v => statevariable_voltage_v_in,
Exposure_current_i => Exposure_current_leak_i_internal,
derivedvariable_current_i_out => derivedvariable_current_leak_i_out,
derivedvariable_current_i_in => derivedvariable_current_leak_i_in,
param_conductance_passive_conductance => param_conductance_leak_passive_conductance,
Exposure_conductance_passive_g => Exposure_conductance_leak_passive_g_internal,
derivedvariable_conductance_passive_g_out => derivedvariable_conductance_leak_passive_g_out,
derivedvariable_conductance_passive_g_in => derivedvariable_conductance_leak_passive_g_in,
sysparam_time_timestep => sysparam_time_timestep,
sysparam_time_simtime => sysparam_time_simtime
);
Exposure_current_leak_i <= Exposure_current_leak_i_internal;
naChans_uut : naChans
port map (
clk => clk,
init_model => init_model,
step_once_go => step_once_go,
Component_done => naChans_Component_done,
param_none_number => param_none_naChans_number,
param_voltage_erev => param_voltage_naChans_erev,
requirement_voltage_v => statevariable_voltage_v_in,
Exposure_current_i => Exposure_current_naChans_i_internal,
derivedvariable_current_i_out => derivedvariable_current_naChans_i_out,
derivedvariable_current_i_in => derivedvariable_current_naChans_i_in,
param_conductance_na_conductance => param_conductance_naChans_na_conductance,
Exposure_conductance_na_g => Exposure_conductance_naChans_na_g_internal,
derivedvariable_conductance_na_g_out => derivedvariable_conductance_naChans_na_g_out,
derivedvariable_conductance_na_g_in => derivedvariable_conductance_naChans_na_g_in,
param_none_na_m_instances => param_none_naChans_na_m_instances,
Exposure_none_na_m_fcond => Exposure_none_naChans_na_m_fcond_internal,
Exposure_none_na_m_q => Exposure_none_naChans_na_m_q_internal,
statevariable_none_na_m_q_out => statevariable_none_naChans_na_m_q_out,
statevariable_none_na_m_q_in => statevariable_none_naChans_na_m_q_in,
derivedvariable_none_na_m_fcond_out => derivedvariable_none_naChans_na_m_fcond_out,
derivedvariable_none_na_m_fcond_in => derivedvariable_none_naChans_na_m_fcond_in,
param_per_time_na_m_forwardRatem1_rate => param_per_time_naChans_na_m_forwardRatem1_rate,
param_voltage_na_m_forwardRatem1_midpoint => param_voltage_naChans_na_m_forwardRatem1_midpoint,
param_voltage_na_m_forwardRatem1_scale => param_voltage_naChans_na_m_forwardRatem1_scale,
param_voltage_inv_na_m_forwardRatem1_scale_inv => param_voltage_inv_naChans_na_m_forwardRatem1_scale_inv,
Exposure_per_time_na_m_forwardRatem1_r => Exposure_per_time_naChans_na_m_forwardRatem1_r_internal,
derivedvariable_per_time_na_m_forwardRatem1_r_out => derivedvariable_per_time_naChans_na_m_forwardRatem1_r_out,
derivedvariable_per_time_na_m_forwardRatem1_r_in => derivedvariable_per_time_naChans_na_m_forwardRatem1_r_in,
param_per_time_na_m_reverseRatem1_rate => param_per_time_naChans_na_m_reverseRatem1_rate,
param_voltage_na_m_reverseRatem1_midpoint => param_voltage_naChans_na_m_reverseRatem1_midpoint,
param_voltage_na_m_reverseRatem1_scale => param_voltage_naChans_na_m_reverseRatem1_scale,
param_voltage_inv_na_m_reverseRatem1_scale_inv => param_voltage_inv_naChans_na_m_reverseRatem1_scale_inv,
Exposure_per_time_na_m_reverseRatem1_r => Exposure_per_time_naChans_na_m_reverseRatem1_r_internal,
derivedvariable_per_time_na_m_reverseRatem1_r_out => derivedvariable_per_time_naChans_na_m_reverseRatem1_r_out,
derivedvariable_per_time_na_m_reverseRatem1_r_in => derivedvariable_per_time_naChans_na_m_reverseRatem1_r_in,
param_none_na_h_instances => param_none_naChans_na_h_instances,
Exposure_none_na_h_fcond => Exposure_none_naChans_na_h_fcond_internal,
Exposure_none_na_h_q => Exposure_none_naChans_na_h_q_internal,
statevariable_none_na_h_q_out => statevariable_none_naChans_na_h_q_out,
statevariable_none_na_h_q_in => statevariable_none_naChans_na_h_q_in,
derivedvariable_none_na_h_fcond_out => derivedvariable_none_naChans_na_h_fcond_out,
derivedvariable_none_na_h_fcond_in => derivedvariable_none_naChans_na_h_fcond_in,
param_per_time_na_h_forwardRateh1_rate => param_per_time_naChans_na_h_forwardRateh1_rate,
param_voltage_na_h_forwardRateh1_midpoint => param_voltage_naChans_na_h_forwardRateh1_midpoint,
param_voltage_na_h_forwardRateh1_scale => param_voltage_naChans_na_h_forwardRateh1_scale,
param_voltage_inv_na_h_forwardRateh1_scale_inv => param_voltage_inv_naChans_na_h_forwardRateh1_scale_inv,
Exposure_per_time_na_h_forwardRateh1_r => Exposure_per_time_naChans_na_h_forwardRateh1_r_internal,
derivedvariable_per_time_na_h_forwardRateh1_r_out => derivedvariable_per_time_naChans_na_h_forwardRateh1_r_out,
derivedvariable_per_time_na_h_forwardRateh1_r_in => derivedvariable_per_time_naChans_na_h_forwardRateh1_r_in,
param_per_time_na_h_reverseRateh1_rate => param_per_time_naChans_na_h_reverseRateh1_rate,
param_voltage_na_h_reverseRateh1_midpoint => param_voltage_naChans_na_h_reverseRateh1_midpoint,
param_voltage_na_h_reverseRateh1_scale => param_voltage_naChans_na_h_reverseRateh1_scale,
param_voltage_inv_na_h_reverseRateh1_scale_inv => param_voltage_inv_naChans_na_h_reverseRateh1_scale_inv,
Exposure_per_time_na_h_reverseRateh1_r => Exposure_per_time_naChans_na_h_reverseRateh1_r_internal,
derivedvariable_per_time_na_h_reverseRateh1_r_out => derivedvariable_per_time_naChans_na_h_reverseRateh1_r_out,
derivedvariable_per_time_na_h_reverseRateh1_r_in => derivedvariable_per_time_naChans_na_h_reverseRateh1_r_in,
sysparam_time_timestep => sysparam_time_timestep,
sysparam_time_simtime => sysparam_time_simtime
);
Exposure_current_naChans_i <= Exposure_current_naChans_i_internal;
kChans_uut : kChans
port map (
clk => clk,
init_model => init_model,
step_once_go => step_once_go,
Component_done => kChans_Component_done,
param_none_number => param_none_kChans_number,
param_voltage_erev => param_voltage_kChans_erev,
requirement_voltage_v => statevariable_voltage_v_in,
Exposure_current_i => Exposure_current_kChans_i_internal,
derivedvariable_current_i_out => derivedvariable_current_kChans_i_out,
derivedvariable_current_i_in => derivedvariable_current_kChans_i_in,
param_conductance_k_conductance => param_conductance_kChans_k_conductance,
Exposure_conductance_k_g => Exposure_conductance_kChans_k_g_internal,
derivedvariable_conductance_k_g_out => derivedvariable_conductance_kChans_k_g_out,
derivedvariable_conductance_k_g_in => derivedvariable_conductance_kChans_k_g_in,
param_none_k_n_instances => param_none_kChans_k_n_instances,
Exposure_none_k_n_fcond => Exposure_none_kChans_k_n_fcond_internal,
Exposure_none_k_n_q => Exposure_none_kChans_k_n_q_internal,
statevariable_none_k_n_q_out => statevariable_none_kChans_k_n_q_out,
statevariable_none_k_n_q_in => statevariable_none_kChans_k_n_q_in,
derivedvariable_none_k_n_fcond_out => derivedvariable_none_kChans_k_n_fcond_out,
derivedvariable_none_k_n_fcond_in => derivedvariable_none_kChans_k_n_fcond_in,
param_per_time_k_n_forwardRaten1_rate => param_per_time_kChans_k_n_forwardRaten1_rate,
param_voltage_k_n_forwardRaten1_midpoint => param_voltage_kChans_k_n_forwardRaten1_midpoint,
param_voltage_k_n_forwardRaten1_scale => param_voltage_kChans_k_n_forwardRaten1_scale,
param_voltage_inv_k_n_forwardRaten1_scale_inv => param_voltage_inv_kChans_k_n_forwardRaten1_scale_inv,
Exposure_per_time_k_n_forwardRaten1_r => Exposure_per_time_kChans_k_n_forwardRaten1_r_internal,
derivedvariable_per_time_k_n_forwardRaten1_r_out => derivedvariable_per_time_kChans_k_n_forwardRaten1_r_out,
derivedvariable_per_time_k_n_forwardRaten1_r_in => derivedvariable_per_time_kChans_k_n_forwardRaten1_r_in,
param_per_time_k_n_reverseRaten1_rate => param_per_time_kChans_k_n_reverseRaten1_rate,
param_voltage_k_n_reverseRaten1_midpoint => param_voltage_kChans_k_n_reverseRaten1_midpoint,
param_voltage_k_n_reverseRaten1_scale => param_voltage_kChans_k_n_reverseRaten1_scale,
param_voltage_inv_k_n_reverseRaten1_scale_inv => param_voltage_inv_kChans_k_n_reverseRaten1_scale_inv,
Exposure_per_time_k_n_reverseRaten1_r => Exposure_per_time_kChans_k_n_reverseRaten1_r_internal,
derivedvariable_per_time_k_n_reverseRaten1_r_out => derivedvariable_per_time_kChans_k_n_reverseRaten1_r_out,
derivedvariable_per_time_k_n_reverseRaten1_r_in => derivedvariable_per_time_kChans_k_n_reverseRaten1_r_in,
sysparam_time_timestep => sysparam_time_timestep,
sysparam_time_simtime => sysparam_time_simtime
);
Exposure_current_kChans_i <= Exposure_current_kChans_i_internal;
synapsemodel_uut : synapsemodel
port map (
clk => clk,
init_model => init_model,
step_once_go => step_once_go,
Component_done => synapsemodel_Component_done,
eventport_in_in => EventPort_in_spike_aggregate(0),
param_time_tauDecay => param_time_synapsemodel_tauDecay,
param_conductance_gbase => param_conductance_synapsemodel_gbase,
param_voltage_erev => param_voltage_synapsemodel_erev,
param_time_inv_tauDecay_inv => param_time_inv_synapsemodel_tauDecay_inv,
requirement_voltage_v => statevariable_voltage_v_in,
Exposure_current_i => Exposure_current_synapsemodel_i_internal,
Exposure_conductance_g => Exposure_conductance_synapsemodel_g_internal,
statevariable_conductance_g_out => statevariable_conductance_synapsemodel_g_out,
statevariable_conductance_g_in => statevariable_conductance_synapsemodel_g_in,
derivedvariable_current_i_out => derivedvariable_current_synapsemodel_i_out,
derivedvariable_current_i_in => derivedvariable_current_synapsemodel_i_in,
sysparam_time_timestep => sysparam_time_timestep,
sysparam_time_simtime => sysparam_time_simtime
);
Exposure_current_synapsemodel_i <= Exposure_current_synapsemodel_i_internal;
Exposure_conductance_synapsemodel_g <= Exposure_conductance_synapsemodel_g_internal;
derived_variable_pre_process_comb :process ( sysparam_time_timestep,exposure_current_leak_i_internal,exposure_current_naChans_i_internal,exposure_current_kChans_i_internal,exposure_current_synapsemodel_i_internal, derivedvariable_current_iChannels_next , derivedvariable_current_iSyn_next )
begin
end process derived_variable_pre_process_comb;
derived_variable_pre_process_syn :process ( clk, init_model )
begin
subprocess_der_int_pre_ready <= '1';
end process derived_variable_pre_process_syn;
--no complex steps in derived variables
subprocess_der_int_ready <= '1';
derived_variable_process_comb :process ( sysparam_time_timestep,exposure_current_leak_i_internal,exposure_current_naChans_i_internal,exposure_current_kChans_i_internal,exposure_current_synapsemodel_i_internal, derivedvariable_current_iChannels_next , derivedvariable_current_iSyn_next )
begin
derivedvariable_current_iChannels_next <= resize(( ( ( exposure_current_leak_i_internal + exposure_current_naChans_i_internal ) + exposure_current_kChans_i_internal ) ),-28,-53);
derivedvariable_current_iSyn_next <= resize(( exposure_current_synapsemodel_i_internal ),-28,-53);
derivedvariable_current_iMemb_next <= resize(( derivedvariable_current_iChannels_next + derivedvariable_current_iSyn_next ),-28,-53);
subprocess_der_ready <= '1';
end process derived_variable_process_comb;
derived_variable_process_syn :process ( clk,init_model )
begin
if clk'event and clk = '1' then
if subprocess_all_ready_shot = '1' then
derivedvariable_current_iChannels <= derivedvariable_current_iChannels_next;
derivedvariable_current_iSyn <= derivedvariable_current_iSyn_next;
derivedvariable_current_iMemb <= derivedvariable_current_iMemb_next;
end if;
end if;
end process derived_variable_process_syn;
---------------------------------------------------------------------
dynamics_pre_process_comb :process ( sysparam_time_timestep, derivedvariable_current_iMemb , param_capacitance_C,param_capacitance_inv_C_inv )
begin
end process dynamics_pre_process_comb;
dynamics_pre_process_syn :process ( clk, init_model )
begin
subprocess_dyn_int_pre_ready <= '1';
end process dynamics_pre_process_syn;
--No dynamics with complex equations found
subprocess_dyn_int_ready <= '1';
state_variable_process_dynamics_comb :process (sysparam_time_timestep, derivedvariable_current_iMemb , param_capacitance_C,param_capacitance_inv_C_inv ,statevariable_voltage_v_in)
begin
statevariable_voltage_noregime_v_temp_1_next <= resize(statevariable_voltage_v_in + ( derivedvariable_current_iMemb * param_capacitance_inv_C_inv ) * sysparam_time_timestep,2,-22);
subprocess_dyn_ready <= '1';
end process state_variable_process_dynamics_comb;
state_variable_process_dynamics_syn :process (CLK,init_model)
begin
if clk'event and clk = '1' then
if subprocess_all_ready_shot = '1' then
statevariable_voltage_noregime_v_temp_1 <= statevariable_voltage_noregime_v_temp_1_next;
end if;
end if;
end process state_variable_process_dynamics_syn;
------------------------------------------------------------------------------------------------------
-- EDState Variable Drivers
------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------
-- EDState variable: $par.name Driver Process
---------------------------------------------------------------------
state_variable_process_comb_0 :process (sysparam_time_timestep,init_model,param_voltage_v0,statevariable_voltage_noregime_v_temp_1,derivedvariable_current_iMemb,param_capacitance_C,param_capacitance_inv_C_inv)
variable statevariable_voltage_v_temp_1 : sfixed (2 downto -22);
begin
statevariable_voltage_v_temp_1 := statevariable_voltage_noregime_v_temp_1; statevariable_voltage_v_next <= statevariable_voltage_v_temp_1;
end process;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- EDState variable: $par.name Driver Process
---------------------------------------------------------------------
state_variable_process_comb_1 :process (sysparam_time_timestep,init_model,param_voltage_v0,param_voltage_thresh,statevariable_voltage_v_in,statevariable_none_spiking_in,param_voltage_thresh,statevariable_voltage_v_in)
variable statevariable_none_spiking_temp_1 : sfixed (18 downto -13);
variable statevariable_none_spiking_temp_2 : sfixed (18 downto -13);
begin
if To_slv ( resize ( statevariable_voltage_v_in - ( param_voltage_thresh ) ,2,-18))(20) = '0' AND To_slv ( resize ( statevariable_none_spiking_in - ( to_sfixed ( 0.5 ,0 , -1 ) ) ,2,-18))(20) = '1' then
statevariable_none_spiking_temp_1 := resize( to_sfixed ( 1 ,1 , -1 ) ,18,-13);
else
statevariable_none_spiking_temp_1 := statevariable_none_spiking_in;
end if;
if To_slv ( resize ( statevariable_voltage_v_in - ( param_voltage_thresh ) ,2,-18))(20) = '1' then
statevariable_none_spiking_temp_2 := resize( to_sfixed ( 0 ,0 , -1 ) ,18,-13);
else
statevariable_none_spiking_temp_2 := statevariable_none_spiking_temp_1;
end if;
statevariable_none_spiking_next <= statevariable_none_spiking_temp_2;
end process;
---------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
eventport_driver0 :process ( clk,sysparam_time_timestep,init_model, param_voltage_thresh, statevariable_voltage_v_in , statevariable_none_spiking_in )
variable eventport_out_spike_temp_1 : std_logic;
variable eventport_out_spike_temp_2 : std_logic;
begin
if rising_edge(clk) and subprocess_all_ready_shot = '1' then
if To_slv ( resize ( statevariable_voltage_v_in - ( param_voltage_thresh ) ,2,-18))(20) = '0' AND To_slv ( resize ( statevariable_none_spiking_in - ( to_sfixed ( 0.5 ,0 , -1 ) ) ,2,-18))(20) = '1' then
eventport_out_spike_temp_1 := '1';
else
eventport_out_spike_temp_1 := '0';
end if;eventport_out_spike_internal <= eventport_out_spike_temp_1;
end if;
end process;
---------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign state variables to exposures
---------------------------------------------------------------------
exposure_voltage_v <= statevariable_voltage_v_in;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign state variables to output state variables
---------------------------------------------------------------------
statevariable_voltage_v_out <= statevariable_voltage_v_next;statevariable_none_spiking_out <= statevariable_none_spiking_next;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign derived variables to exposures
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Subprocess ready process
---------------------------------------------------------------------
subprocess_all_ready_process: process(step_once_go,subprocess_der_int_ready,subprocess_der_int_pre_ready,subprocess_der_ready,subprocess_dyn_int_pre_ready,subprocess_dyn_int_ready,subprocess_dyn_ready,subprocess_model_ready)
begin
if step_once_go = '0' and subprocess_der_int_ready = '1' and subprocess_der_int_pre_ready = '1'and subprocess_der_ready ='1' and subprocess_dyn_int_ready = '1' and subprocess_dyn_int_pre_ready = '1' and subprocess_dyn_ready = '1' and subprocess_model_ready = '1' then
subprocess_all_ready <= '1';
else
subprocess_all_ready <= '0';
end if;
end process subprocess_all_ready_process;
subprocess_all_ready_shot_process : process(clk)
begin
if rising_edge(clk) then
if (init_model='1') then
subprocess_all_ready_shot <= '0';
subprocess_all_ready_shotdone <= '1';
else
if subprocess_all_ready = '1' and subprocess_all_ready_shotdone = '0' then
subprocess_all_ready_shot <= '1';
subprocess_all_ready_shotdone <= '1';
elsif subprocess_all_ready_shot = '1' then
subprocess_all_ready_shot <= '0';
elsif subprocess_all_ready = '0' then
subprocess_all_ready_shot <= '0';
subprocess_all_ready_shotdone <= '0';
end if;
end if;
end if;
end process subprocess_all_ready_shot_process;
---------------------------------------------------------------------
count_proc:process(clk)
begin
if (clk'EVENT AND clk = '1') then
if init_model = '1' then COUNT <= "001";
component_done_int <= '1';
else if step_once_go = '1' then
COUNT <= "000";
component_done_int <= '0';
elsif COUNT = "001" then
component_done_int <= '1';
elsif subprocess_all_ready_shot = '1' then
COUNT <= COUNT + 1;
component_done_int <= '0';
end if;
end if;
end if;
end process count_proc;
childrenCombined_component_done_process:process(leak_component_done,naChans_component_done,kChans_component_done,synapsemodel_component_done,CLK)
begin
if (leak_component_done = '1' and naChans_component_done = '1' and kChans_component_done = '1' and synapsemodel_component_done = '1') then
childrenCombined_component_done <= '1';
else
childrenCombined_component_done <= '0';
end if;
end process childrenCombined_component_done_process;
component_done <= component_done_int and childrenCombined_component_done;
---------------------------------------------------------------------
-- Control the done signal
---------------------------------------------------------------------
step_once_complete_synch:process(clk)
begin
if (clk'EVENT AND clk = '1') then
if init_model = '1' then step_once_complete <= '0';
step_once_complete_fired <= '1';
else if component_done = '1' and step_once_complete_fired = '0' then
step_once_complete <= '1';
step_once_complete_fired <= '1';
---------------------------------------------------------------------
-- Assign event ports to exposures
---------------------------------------------------------------------
eventport_out_spike <= eventport_out_spike_internal ;
---------------------------------------------------------------------
elsif component_done = '0' then
step_once_complete <= '0';
step_once_complete_fired <= '0';
---------------------------------------------------------------------
-- Assign event ports to exposures
---------------------------------------------------------------------
eventport_out_spike <= '0';
---------------------------------------------------------------------
else
step_once_complete <= '0';
---------------------------------------------------------------------
-- Assign event ports to exposures
---------------------------------------------------------------------
eventport_out_spike <= '0';
---------------------------------------------------------------------
end if;
end if;
end if;
end process step_once_complete_synch;
---------------------------------------------------------------------
end RTL;
| lgpl-3.0 | d1256423642af519456c26cfd405ad40 | 0.659934 | 3.179838 | false | false | false | false |
paulino/digilentinc-peripherals | examples/test1-vivado/test1-nexsys4.vhd | 1 | 3,999 | -------------------------------------------------------------------------------
-- Copyright 2014 Paulino Ruiz de Clavijo Vázquez <[email protected]>
-- This file is part of the Digilentinc-peripherals project.
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-- You can get more info at http://www.dte.us.es/id2
--
--*------------------------------- End auto header, don't touch this line --*--
--
-- Description: Demo/test to run in Nexsys 4 Digilent prototype board.
-- This test transfers the data set from switches to one peripheral when a
-- button is pressed:
-- - When BTNU is pressed the value set in switches is copied to the leds
-- - When BTNC is pressed 8+2 bits are copied to 2 digits of display:
-- The value is taken from SW7 to SW0
-- Two display points are taken from SW8 and SW9
-- The destination display digit is selected using SW15 and SW14
--
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.ALL;
use work.digilent_peripherals_pk.all;
entity demo1_nexys4 is
port(
clk : in std_logic;
leds_out : out std_logic_vector (15 downto 0);
seg_out : out std_logic_vector (6 downto 0);
dp_out : out std_logic;
an_out : out std_logic_vector (7 downto 0);
sw_in : in std_logic_vector (15 downto 0);
btnu_in : in std_logic;
btnr_in : in std_logic;
btnl_in : in std_logic;
btnd_in : in std_logic;
btnc_in : in std_logic
);
end demo1_nexys4;
architecture behavioral of demo1_nexys4 is
-- Internal signals
signal port_display_enable : std_logic;
signal port_switches_out : std_logic_vector(15 downto 0);
signal port_buttons_out : std_logic_vector(7 downto 0);
begin
-- leds MSB 8 leds, LSB 8 leds
u_leds_msb: port_leds_dig port map (
clk => clk,
enable => '1',
w => port_buttons_out(0), -- BTNU
port_in => port_switches_out(15 downto 8),
leds_out => leds_out(15 downto 8));
u_led_lsb: port_leds_dig port map (
clk => clk,
enable => '1',
w => port_buttons_out(0), -- BTNU
port_in => port_switches_out(7 downto 0),
leds_out => leds_out(7 downto 0));
-- Display, 8 bits are written from switches
u_display : port_display32_dig port map (
reset => '0',
clk => clk,
w => port_buttons_out(4), -- BTNC
enable => '1',
byte_sel => port_switches_out(15 downto 14),
digit_in => port_switches_out(7 downto 0),
dp_in => port_switches_out(9 downto 8),
seg_out => seg_out,
dp_out => dp_out,
an_out => an_out(7 downto 0)
);
-- Switches 8 bits
u_switches_lsb : port_switches_dig port map(
clk => clk,
enable => '1',
r => '1',
port_out => port_switches_out(7 downto 0),
switches_in => sw_in(7 downto 0));
u_switches_msb : port_switches_dig port map(
clk => clk,
enable => '1',
r => '1',
port_out => port_switches_out(15 downto 8),
switches_in => sw_in(15 downto 8)
);
-- Buttons
u_buttons : port_buttons_nexsys4 port map(
clk => clk,
enable => '1',
r => '1',
btnu_in => btnu_in,
btnr_in => btnr_in,
btnl_in => btnl_in,
btnd_in => btnd_in,
btnc_in => btnc_in,
port_out => port_buttons_out
);
end behavioral;
| apache-2.0 | 83c4c3dda4c3702b072f9c4a9820d64c | 0.570535 | 3.452504 | false | false | false | false |
sergev/vak-opensource | hardware/dlx/bv_arithmetic-body.vhdl | 1 | 32,574 | --------------------------------------------------------------------------
--
-- Copyright (C) 1993, Peter J. Ashenden
-- Mail: Dept. Computer Science
-- University of Adelaide, SA 5005, Australia
-- e-mail: [email protected]
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 1, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
--------------------------------------------------------------------------
--
-- $RCSfile: bv_arithmetic-body.vhdl,v $ $Revision: 2.1 $ $Date: 1993/11/02 22:50:39 $
--
--------------------------------------------------------------------------
--
-- Bit vector arithmetic package body.
--
-- Does arithmetic and logical operations on bit vectors, treating them
-- as either unsigned or signed (2's complement) integers. Leftmost bit
-- is most significant or sign bit, rightmost bit is least significant
-- bit. Dyadic operations need the two arguments to be of the same
-- length, however their index ranges and directions may differ. Results
-- must be of the same length as the operands.
--
--------------------------------------------------------------------------
package body bv_arithmetic is
----------------------------------------------------------------
-- Type conversions
----------------------------------------------------------------
----------------------------------------------------------------
-- bv_to_natural
--
-- Convert bit vector encoded unsigned integer to natural.
----------------------------------------------------------------
function bv_to_natural(bv : in bit_vector) return natural is
variable result : natural := 0;
begin
for index in bv'range loop
result := result * 2 + bit'pos(bv(index));
end loop;
return result;
end bv_to_natural;
----------------------------------------------------------------
-- natural_to_bv
--
-- Convert natural to bit vector encoded unsigned integer.
-- (length is used as the size of the result.)
----------------------------------------------------------------
function natural_to_bv(nat : in natural;
length : in natural) return bit_vector is
variable temp : natural := nat;
variable result : bit_vector(0 to length-1);
begin
for index in result'reverse_range loop
result(index) := bit'val(temp rem 2);
temp := temp / 2;
end loop;
return result;
end natural_to_bv;
----------------------------------------------------------------
-- bv_to_integer
--
-- Convert bit vector encoded signed integer to integer
----------------------------------------------------------------
function bv_to_integer(bv : in bit_vector) return integer is
variable temp : bit_vector(bv'range);
variable result : integer := 0;
begin
if bv(bv'left) = '1' then -- negative number
temp := not bv;
else
temp := bv;
end if;
for index in bv'range loop -- sign bit of temp = '0'
result := result * 2 + bit'pos(temp(index));
end loop;
if bv(bv'left) = '1' then
result := (-result) - 1;
end if;
return result;
end bv_to_integer;
----------------------------------------------------------------
-- integer_to_bv
--
-- Convert integer to bit vector encoded signed integer.
-- (length is used as the size of the result.)
----------------------------------------------------------------
function integer_to_bv(int : in integer;
length : in natural) return bit_vector is
variable temp : integer;
variable result : bit_vector(0 to length-1);
begin
if int < 0 then
temp := -(int+1);
else
temp := int;
end if;
for index in result'reverse_range loop
result(index) := bit'val(temp rem 2);
temp := temp / 2;
end loop;
if int < 0 then
result := not result;
result(result'left) := '1';
end if;
return result;
end integer_to_bv;
----------------------------------------------------------------
-- Arithmetic operations
----------------------------------------------------------------
----------------------------------------------------------------
-- bv_add
--
-- Signed addition with overflow detection
----------------------------------------------------------------
procedure bv_add (bv1, bv2 : in bit_vector;
bv_result : out bit_vector;
overflow : out boolean) is
alias op1 : bit_vector(1 to bv1'length) is bv1;
alias op2 : bit_vector(1 to bv2'length) is bv2;
variable result : bit_vector(1 to bv_result'length);
variable carry_in : bit;
variable carry_out : bit := '0';
begin
assert bv1'length = bv2'length and bv1'length = bv_result'length
report "bv_add: operands of different lengths"
severity failure;
for index in result'reverse_range loop
carry_in := carry_out; -- of previous bit
result(index) := op1(index) xor op2(index) xor carry_in;
carry_out := (op1(index) and op2(index))
or (carry_in and (op1(index) xor op2(index)));
end loop;
bv_result := result;
overflow := carry_out /= carry_in;
end bv_add;
----------------------------------------------------------------
-- "+"
--
-- Signed addition without overflow detection
----------------------------------------------------------------
function "+" (bv1, bv2 : in bit_vector) return bit_vector is
alias op1 : bit_vector(1 to bv1'length) is bv1;
alias op2 : bit_vector(1 to bv2'length) is bv2;
variable result : bit_vector(1 to bv1'length);
variable carry_in : bit;
variable carry_out : bit := '0';
begin
assert bv1'length = bv2'length
-- use concatenation to work around Synthesia MINT code gen bug
report '"' & '+' & '"' & ": operands of different lengths"
severity failure;
for index in result'reverse_range loop
carry_in := carry_out; -- of previous bit
result(index) := op1(index) xor op2(index) xor carry_in;
carry_out := (op1(index) and op2(index))
or (carry_in and (op1(index) xor op2(index)));
end loop;
return result;
end "+";
----------------------------------------------------------------
-- bv_sub
--
-- Signed subtraction with overflow detection
----------------------------------------------------------------
procedure bv_sub (bv1, bv2 : in bit_vector;
bv_result : out bit_vector;
overflow : out boolean) is
-- subtraction implemented by adding ((not bv2) + 1), ie -bv2
alias op1 : bit_vector(1 to bv1'length) is bv1;
alias op2 : bit_vector(1 to bv2'length) is bv2;
variable result : bit_vector(1 to bv_result'length);
variable carry_in : bit;
variable carry_out : bit := '1';
begin
assert bv1'length = bv2'length and bv1'length = bv_result'length
report "bv_sub: operands of different lengths"
severity failure;
for index in result'reverse_range loop
carry_in := carry_out; -- of previous bit
result(index) := op1(index) xor (not op2(index)) xor carry_in;
carry_out := (op1(index) and (not op2(index)))
or (carry_in and (op1(index) xor (not op2(index))));
end loop;
bv_result := result;
overflow := carry_out /= carry_in;
end bv_sub;
----------------------------------------------------------------
-- "-"
--
-- Signed subtraction without overflow detection
----------------------------------------------------------------
function "-" (bv1, bv2 : in bit_vector) return bit_vector is
-- subtraction implemented by adding ((not bv2) + 1), ie -bv2
alias op1 : bit_vector(1 to bv1'length) is bv1;
alias op2 : bit_vector(1 to bv2'length) is bv2;
variable result : bit_vector(1 to bv1'length);
variable carry_in : bit;
variable carry_out : bit := '1';
begin
assert bv1'length = bv2'length
-- use concatenation to work around Synthesia MINT code gen bug
report '"' & '-' & '"' & ": operands of different lengths"
severity failure;
for index in result'reverse_range loop
carry_in := carry_out; -- of previous bit
result(index) := op1(index) xor (not op2(index)) xor carry_in;
carry_out := (op1(index) and (not op2(index)))
or (carry_in and (op1(index) xor (not op2(index))));
end loop;
return result;
end "-";
----------------------------------------------------------------
-- bv_addu
--
-- Unsigned addition with overflow detection
----------------------------------------------------------------
procedure bv_addu (bv1, bv2 : in bit_vector;
bv_result : out bit_vector;
overflow : out boolean) is
alias op1 : bit_vector(1 to bv1'length) is bv1;
alias op2 : bit_vector(1 to bv2'length) is bv2;
variable result : bit_vector(1 to bv_result'length);
variable carry : bit := '0';
begin
assert bv1'length = bv2'length and bv1'length = bv_result'length
report "bv_addu: operands of different lengths"
severity failure;
for index in result'reverse_range loop
result(index) := op1(index) xor op2(index) xor carry;
carry := (op1(index) and op2(index))
or (carry and (op1(index) xor op2(index)));
end loop;
bv_result := result;
overflow := carry = '1';
end bv_addu;
----------------------------------------------------------------
-- bv_addu
--
-- Unsigned addition without overflow detection
----------------------------------------------------------------
procedure bv_addu (bv1, bv2 : in bit_vector;
bv_result : out bit_vector) is
alias op1 : bit_vector(1 to bv1'length) is bv1;
alias op2 : bit_vector(1 to bv2'length) is bv2;
variable result : bit_vector(1 to bv_result'length);
variable carry : bit := '0';
begin
assert bv1'length = bv2'length and bv1'length = bv_result'length
report "bv_addu: operands of different lengths"
severity failure;
for index in result'reverse_range loop
result(index) := op1(index) xor op2(index) xor carry;
carry := (op1(index) and op2(index))
or (carry and (op1(index) xor op2(index)));
end loop;
bv_result := result;
end bv_addu;
----------------------------------------------------------------
-- bv_subu
--
-- Unsigned subtraction with overflow detection
----------------------------------------------------------------
procedure bv_subu (bv1, bv2 : in bit_vector;
bv_result : out bit_vector;
overflow : out boolean) is
alias op1 : bit_vector(1 to bv1'length) is bv1;
alias op2 : bit_vector(1 to bv2'length) is bv2;
variable result : bit_vector(1 to bv_result'length);
variable borrow : bit := '0';
begin
assert bv1'length = bv2'length and bv1'length = bv_result'length
report "bv_subu: operands of different lengths"
severity failure;
for index in result'reverse_range loop
result(index) := op1(index) xor op2(index) xor borrow;
borrow := (not op1(index) and op2(index))
or (borrow and not (op1(index) xor op2(index)));
end loop;
bv_result := result;
overflow := borrow = '1';
end bv_subu;
----------------------------------------------------------------
-- bv_subu
--
-- Unsigned subtraction without overflow detection
----------------------------------------------------------------
procedure bv_subu (bv1, bv2 : in bit_vector;
bv_result : out bit_vector) is
alias op1 : bit_vector(1 to bv1'length) is bv1;
alias op2 : bit_vector(1 to bv2'length) is bv2;
variable result : bit_vector(1 to bv_result'length);
variable borrow : bit := '0';
begin
assert bv1'length = bv2'length and bv1'length = bv_result'length
report "bv_subu: operands of different lengths"
severity failure;
for index in result'reverse_range loop
result(index) := op1(index) xor op2(index) xor borrow;
borrow := (not op1(index) and op2(index))
or (borrow and not (op1(index) xor op2(index)));
end loop;
bv_result := result;
end bv_subu;
----------------------------------------------------------------
-- bv_neg
--
-- Signed negation with overflow detection
----------------------------------------------------------------
procedure bv_neg (bv : in bit_vector;
bv_result : out bit_vector;
overflow : out boolean) is
CONSTANT zero : bit_vector(bv'range) := (others => '0');
begin
bv_sub( zero, bv, bv_result, overflow );
end bv_neg;
----------------------------------------------------------------
-- "-"
--
-- Signed negation without overflow detection
----------------------------------------------------------------
function "-" (bv : in bit_vector) return bit_vector is
CONSTANT zero : bit_vector(bv'range) := (others => '0');
begin
return zero - bv;
end "-";
----------------------------------------------------------------
-- bv_mult
--
-- Signed multiplication with overflow detection
----------------------------------------------------------------
procedure bv_mult (bv1, bv2 : in bit_vector;
bv_result : out bit_vector;
overflow : out boolean) is
variable negative_result : boolean;
variable op1 : bit_vector(bv1'range) := bv1;
variable op2 : bit_vector(bv2'range) := bv2;
variable multu_result : bit_vector(bv1'range);
variable multu_overflow : boolean;
-- constant abs_min_int : bit_vector(bv1'range)
-- := (bv1'left => '1', others => '0');
-- causes Synthesia MINT code generator to prang. Work around:
variable abs_min_int : bit_vector(bv1'range) := (others => '0');
begin
assert bv1'length = bv2'length and bv1'length = bv_result'length
report "bv_mult: operands of different lengths"
severity failure;
abs_min_int(bv1'left) := '1'; -- Synthesia work around
negative_result := (op1(op1'left) = '1') xor (op2(op2'left) = '1');
if (op1(op1'left) = '1') then
op1 := - bv1;
end if;
if (op2(op2'left) = '1') then
op2 := - bv2;
end if;
bv_multu(op1, op2, multu_result, multu_overflow);
if (negative_result) then
overflow := multu_overflow or (multu_result > abs_min_int);
bv_result := - multu_result;
else
overflow := multu_overflow or (multu_result(multu_result'left) = '1');
bv_result := multu_result;
end if;
end bv_mult;
----------------------------------------------------------------
-- "*"
--
-- Signed multiplication without overflow detection
----------------------------------------------------------------
function "*" (bv1, bv2 : in bit_vector) return bit_vector is
variable negative_result : boolean;
variable op1 : bit_vector(bv1'range) := bv1;
variable op2 : bit_vector(bv2'range) := bv2;
variable result : bit_vector(bv1'range);
begin
assert bv1'length = bv2'length
-- use concatenation to work around Synthesia MINT code gen bug
report '"' & '*' & '"' & ": operands of different lengths"
severity failure;
negative_result := (op1(op1'left) = '1') xor (op2(op2'left) = '1');
if (op1(op1'left) = '1') then
op1 := - bv1;
end if;
if (op2(op2'left) = '1') then
op2 := - bv2;
end if;
bv_multu(op1, op2, result);
if (negative_result) then
result := - result;
end if;
return result;
end "*";
----------------------------------------------------------------
-- bv_multu
--
-- Unsigned multiplication with overflow detection
----------------------------------------------------------------
procedure bv_multu (bv1, bv2 : in bit_vector;
bv_result : out bit_vector;
overflow : out boolean) is
-- Based on shift&add multiplier in Appendix A of Hennessy & Patterson
constant bv_length : natural := bv1'length;
constant accum_length : natural := bv_length * 2;
constant zero : bit_vector(accum_length-1 downto bv_length)
:= (others => '0');
variable accum : bit_vector(accum_length-1 downto 0);
variable addu_overflow : boolean;
variable carry : bit;
begin
assert bv1'length = bv2'length and bv1'length = bv_result'length
report "bv_multu: operands of different lengths"
severity failure;
accum(bv_length-1 downto 0) := bv1;
accum(accum_length-1 downto bv_length) := zero;
for count in 1 to bv_length loop
if (accum(0) = '1') then
bv_addu( accum(accum_length-1 downto bv_length), bv2,
accum(accum_length-1 downto bv_length), addu_overflow);
carry := bit'val(boolean'pos(addu_overflow));
else
carry := '0';
end if;
accum := carry & accum(accum_length-1 downto 1);
end loop;
bv_result := accum(bv_length-1 downto 0);
overflow := accum(accum_length-1 downto bv_length) /= zero;
end bv_multu;
----------------------------------------------------------------
-- bv_multu
--
-- Unsigned multiplication without overflow detection
----------------------------------------------------------------
procedure bv_multu (bv1, bv2 : in bit_vector;
bv_result : out bit_vector) is
-- Use bv_multu with overflow detection, but ignore overflow flag
variable tmp_overflow : boolean;
begin
-- following procedure asserts bv1'length = bv2'length
bv_multu(bv1, bv2, bv_result, tmp_overflow);
end bv_multu;
----------------------------------------------------------------
-- bv_div
--
-- Signed division with divide by zero and overflow detection
----------------------------------------------------------------
procedure bv_div (bv1, bv2 : in bit_vector;
bv_result : out bit_vector;
div_by_zero : out boolean;
overflow : out boolean) is
-- Need overflow, in case divide b"10...0" (min_int) by -1
-- Don't use bv_to_int, in case size bigger than host machine!
variable negative_result : boolean;
variable op1 : bit_vector(bv1'range) := bv1;
variable op2 : bit_vector(bv2'range) := bv2;
variable divu_result : bit_vector(bv1'range);
begin
assert bv1'length = bv2'length
report "bv_div: operands of different lengths"
severity failure;
negative_result := (op1(op1'left) = '1') xor (op2(op2'left) = '1');
if (op1(op1'left) = '1') then
op1 := - bv1;
end if;
if (op2(op2'left) = '1') then
op2 := - bv2;
end if;
bv_divu(op1, op2, divu_result, div_by_zero);
if (negative_result) then
overflow := false;
bv_result := - divu_result;
else
overflow := divu_result(divu_result'left) = '1';
bv_result := divu_result;
end if;
end bv_div;
----------------------------------------------------------------
-- "/"
--
-- Signed division without divide by zero and overflow detection
----------------------------------------------------------------
function "/" (bv1, bv2 : in bit_vector) return bit_vector is
variable negative_result : boolean;
variable op1 : bit_vector(bv1'range) := bv1;
variable op2 : bit_vector(bv2'range) := bv2;
variable result : bit_vector(bv1'range);
begin
assert bv1'length = bv2'length
-- use concatenation to work around Synthesia MINT code gen bug
report '"' & '/' & '"' & ": operands of different lengths"
severity failure;
negative_result := (op1(op1'left) = '1') xor (op2(op2'left) = '1');
if (op1(op1'left) = '1') then
op1 := - bv1;
end if;
if (op2(op2'left) = '1') then
op2 := - bv2;
end if;
bv_divu(op1, op2, result);
if (negative_result) then
result := - result;
end if;
return result;
end "/";
----------------------------------------------------------------
-- bv_divu
--
-- Unsigned division with divide by zero detection
----------------------------------------------------------------
procedure bv_divu (bv1, bv2 : in bit_vector;
bv_result : out bit_vector;
div_by_zero : out boolean) is
-- based on algorithm in Sun Sparc architecture manual
constant len : natural := bv1'length;
variable zero, one,
big_value : bit_vector(len-1 downto 0)
:= (others => '0');
variable dividend : bit_vector(bv1'length-1 downto 0) := bv1;
variable divisor : bit_vector(bv2'length-1 downto 0) := bv2;
variable quotient : bit_vector(len-1 downto 0); -- unsigned
variable remainder : bit_vector(len-1 downto 0); -- signed
variable shifted_divisor,
shifted_1 : bit_vector(len-1 downto 0);
variable log_quotient : natural;
variable ignore_overflow : boolean;
begin
assert bv1'length = bv2'length
report "bv_divu: operands of different lengths"
severity failure;
one(0) := '1';
big_value(len-2) := '1';
--
-- check for zero divisor
--
if (divisor = zero) then
div_by_zero := true;
return;
end if;
--
-- estimate log of quotient
--
log_quotient := 0;
shifted_divisor := divisor;
loop
exit when (log_quotient >= len)
or (shifted_divisor > big_value)
or (shifted_divisor >= dividend);
log_quotient := log_quotient + 1;
shifted_divisor := bv_sll(shifted_divisor, 1);
end loop;
--
-- perform division
--
remainder := dividend;
quotient := zero;
shifted_divisor := bv_sll(divisor, log_quotient);
shifted_1 := bv_sll(one, log_quotient);
for iter in log_quotient downto 0 loop
if bv_ge(remainder, zero) then
bv_sub(remainder, shifted_divisor, remainder, ignore_overflow);
bv_addu(quotient, shifted_1, quotient, ignore_overflow);
else
bv_add(remainder, shifted_divisor, remainder, ignore_overflow);
bv_subu(quotient, shifted_1, quotient, ignore_overflow);
end if;
shifted_divisor := '0' & shifted_divisor(len-1 downto 1);
shifted_1 := '0' & shifted_1(len-1 downto 1);
end loop;
if (bv_lt(remainder, zero)) then
bv_add(remainder, divisor, remainder, ignore_overflow);
bv_subu(quotient, one, quotient, ignore_overflow);
end if;
bv_result := quotient;
end bv_divu;
----------------------------------------------------------------
-- bv_divu
--
-- Unsigned division without divide by zero detection
----------------------------------------------------------------
procedure bv_divu (bv1, bv2 : in bit_vector;
bv_result : out bit_vector) is
-- Use bv_divu with divide by zero detection,
-- but ignore div_by_zero flag
variable tmp_div_by_zero : boolean;
begin
-- following procedure asserts bv1'length = bv2'length
bv_divu(bv1, bv2, bv_result, tmp_div_by_zero);
end bv_divu;
----------------------------------------------------------------
-- Logical operators
-- (Provided for VHDL-87, built in for VHDL-93)
----------------------------------------------------------------
----------------------------------------------------------------
-- bv_sll
--
-- Shift left logical (fill with '0' bits)
----------------------------------------------------------------
function bv_sll (bv : in bit_vector;
shift_count : in natural) return bit_vector is
constant bv_length : natural := bv'length;
constant actual_shift_count : natural := shift_count mod bv_length;
alias bv_norm : bit_vector(1 to bv_length) is bv;
variable result : bit_vector(1 to bv_length) := (others => '0');
begin
result(1 to bv_length - actual_shift_count)
:= bv_norm(actual_shift_count + 1 to bv_length);
return result;
end bv_sll;
----------------------------------------------------------------
-- bv_srl
--
-- Shift right logical (fill with '0' bits)
----------------------------------------------------------------
function bv_srl (bv : in bit_vector;
shift_count : in natural) return bit_vector is
constant bv_length : natural := bv'length;
constant actual_shift_count : natural := shift_count mod bv_length;
alias bv_norm : bit_vector(1 to bv_length) is bv;
variable result : bit_vector(1 to bv_length) := (others => '0');
begin
result(actual_shift_count + 1 to bv_length)
:= bv_norm(1 to bv_length - actual_shift_count);
return result;
end bv_srl;
----------------------------------------------------------------
-- bv_sra
--
-- Shift right arithmetic (fill with copy of sign bit)
----------------------------------------------------------------
function bv_sra (bv : in bit_vector;
shift_count : in natural) return bit_vector is
constant bv_length : natural := bv'length;
constant actual_shift_count : natural := shift_count mod bv_length;
alias bv_norm : bit_vector(1 to bv_length) is bv;
variable result : bit_vector(1 to bv_length) := (others => bv(bv'left));
begin
result(actual_shift_count + 1 to bv_length)
:= bv_norm(1 to bv_length - actual_shift_count);
return result;
end bv_sra;
----------------------------------------------------------------
-- bv_rol
--
-- Rotate left
----------------------------------------------------------------
function bv_rol (bv : in bit_vector;
rotate_count : in natural) return bit_vector is
constant bv_length : natural := bv'length;
constant actual_rotate_count : natural := rotate_count mod bv_length;
alias bv_norm : bit_vector(1 to bv_length) is bv;
variable result : bit_vector(1 to bv_length);
begin
result(1 to bv_length - actual_rotate_count)
:= bv_norm(actual_rotate_count + 1 to bv_length);
result(bv_length - actual_rotate_count + 1 to bv_length)
:= bv_norm(1 to actual_rotate_count);
return result;
end bv_rol;
----------------------------------------------------------------
-- bv_ror
--
-- Rotate right
----------------------------------------------------------------
function bv_ror (bv : in bit_vector;
rotate_count : in natural) return bit_vector is
constant bv_length : natural := bv'length;
constant actual_rotate_count : natural := rotate_count mod bv_length;
alias bv_norm : bit_vector(1 to bv_length) is bv;
variable result : bit_vector(1 to bv_length);
begin
result(actual_rotate_count + 1 to bv_length)
:= bv_norm(1 to bv_length - actual_rotate_count);
result(1 to actual_rotate_count)
:= bv_norm(bv_length - actual_rotate_count + 1 to bv_length);
return result;
end bv_ror;
----------------------------------------------------------------
-- Arithmetic comparison operators.
-- Perform comparisons on bit vector encoded signed integers.
-- (For unsigned integers, built in lexical comparison does
-- the required operation.)
----------------------------------------------------------------
----------------------------------------------------------------
-- bv_lt
--
-- Signed less than comparison
----------------------------------------------------------------
function bv_lt (bv1, bv2 : in bit_vector) return boolean is
variable tmp1 : bit_vector(bv1'range) := bv1;
variable tmp2 : bit_vector(bv2'range) := bv2;
begin
assert bv1'length = bv2'length
report "bv_lt: operands of different lengths"
severity failure;
tmp1(tmp1'left) := not tmp1(tmp1'left);
tmp2(tmp2'left) := not tmp2(tmp2'left);
return tmp1 < tmp2;
end bv_lt;
----------------------------------------------------------------
-- bv_le
--
-- Signed less than or equal comparison
----------------------------------------------------------------
function bv_le (bv1, bv2 : in bit_vector) return boolean is
variable tmp1 : bit_vector(bv1'range) := bv1;
variable tmp2 : bit_vector(bv2'range) := bv2;
begin
assert bv1'length = bv2'length
report "bv_le: operands of different lengths"
severity failure;
tmp1(tmp1'left) := not tmp1(tmp1'left);
tmp2(tmp2'left) := not tmp2(tmp2'left);
return tmp1 <= tmp2;
end bv_le;
----------------------------------------------------------------
-- bv_gt
--
-- Signed greater than comparison
----------------------------------------------------------------
function bv_gt (bv1, bv2 : in bit_vector) return boolean is
variable tmp1 : bit_vector(bv1'range) := bv1;
variable tmp2 : bit_vector(bv2'range) := bv2;
begin
assert bv1'length = bv2'length
report "bv_gt: operands of different lengths"
severity failure;
tmp1(tmp1'left) := not tmp1(tmp1'left);
tmp2(tmp2'left) := not tmp2(tmp2'left);
return tmp1 > tmp2;
end bv_gt;
----------------------------------------------------------------
-- bv_ge
--
-- Signed greater than or equal comparison
----------------------------------------------------------------
function bv_ge (bv1, bv2 : in bit_vector) return boolean is
variable tmp1 : bit_vector(bv1'range) := bv1;
variable tmp2 : bit_vector(bv2'range) := bv2;
begin
assert bv1'length = bv2'length
report "bv_ged: operands of different lengths"
severity failure;
tmp1(tmp1'left) := not tmp1(tmp1'left);
tmp2(tmp2'left) := not tmp2(tmp2'left);
return tmp1 >= tmp2;
end bv_ge;
----------------------------------------------------------------
-- Extension operators - convert a bit vector to a longer one
----------------------------------------------------------------
----------------------------------------------------------------
-- bv_sext
--
-- Sign extension - replicate the sign bit of the operand into
-- the most significant bits of the result. Length parameter
-- determines size of result. If length < bv'length, result is
-- rightmost length bits of bv.
----------------------------------------------------------------
function bv_sext (bv : in bit_vector;
length : in natural) return bit_vector is
alias bv_norm : bit_vector(1 to bv'length) is bv;
variable result : bit_vector(1 to length) := (others => bv(bv'left));
variable src_length : natural := bv'length;
begin
if src_length > length then
src_length := length;
end if;
result(length - src_length + 1 to length)
:= bv_norm(bv'length - src_length + 1 to bv'length);
return result;
end bv_sext;
----------------------------------------------------------------
-- bv_zext
--
-- Zero extension - replicate zero bits into the most significant
-- bits of the result. Length parameter determines size of result.
-- If length < bv'length, result is rightmost length bits of bv.
----------------------------------------------------------------
function bv_zext (bv : in bit_vector;
length : in natural) return bit_vector is
alias bv_norm : bit_vector(1 to bv'length) is bv;
variable result : bit_vector(1 to length) := (others => '0');
variable src_length : natural := bv'length;
begin
if src_length > length then
src_length := length;
end if;
result(length - src_length + 1 to length)
:= bv_norm(bv'length - src_length + 1 to bv'length);
return result;
end bv_zext;
end bv_arithmetic;
| apache-2.0 | 0315bdfcd1285f3b0e7e279889e13298 | 0.509363 | 4.135856 | false | false | false | false |
Kalycito-open-automation/openPOWERLINK_V2_old_25-06-2014 | hardware/ipcore/common/openmac/src/openmacPkg-p.vhd | 2 | 13,981 | -------------------------------------------------------------------------------
--! @file openmacPkg-p.vhd
--
--! @brief OpenMAC package
--
--! @details This is the openMAC package providing common types.
-------------------------------------------------------------------------------
--
-- (c) B&R, 2013
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
--! use global library
use work.global.all;
package openmacPkg is
---------------------------------------------------------------------------
-- Configuration
---------------------------------------------------------------------------
--! Packet buffer is internal (e.g. memory blocks)
constant cPktBufLocal : natural := 1;
--! Packet buffer is external
constant cPktBufExtern : natural := 2;
--! Phy port(s) are Rmii
constant cPhyPortRmii : natural := 1;
--! Phy port(s) are Mii
constant cPhyPortMii : natural := 2;
---------------------------------------------------------------------------
-- (R)MII types and constants
---------------------------------------------------------------------------
--! RMII data width
constant cRmiiDataWidth : natural := 2;
--! MII data width
constant cMiiDataWidth : natural := 4;
--! RMII path
type tRmiiPath is record
enable : std_logic;
data : std_logic_vector(cRmiiDataWidth-1 downto 0);
end record;
--! MII path
type tMiiPath is record
enable : std_logic;
data : std_logic_vector(cMiiDataWidth-1 downto 0);
end record;
--! RMII path array
type tRmiiPathArray is array (natural range <>) of tRmiiPath;
--! MII path array
type tMiiPathArray is array (natural range <>) of tMiiPath;
--! RMII link
type tRmii is record
rx : tRmiiPath;
tx : tRmiiPath;
end record;
--! MII link
type tMii is record
rx : tMiiPath;
tx : tMiiPath;
end record;
--! RMII link array
type tRmiiArray is array (natural range <>) of tRmii;
--! MII link array
type tMiiArray is array (natural range <>) of tMii;
--! RMII path initialization
constant cRmiiPathInit : tRmiiPath := (
enable => cInactivated,
data => (others => cInactivated)
);
--! MII path initialization
constant cMiiPathInit : tMiiPath := (
enable => cInactivated,
data => (others => cInactivated)
);
--! RMII link initialization
constant cRmiiInit : tRmii := (
rx => cRmiiPathInit,
tx => cRmiiPathInit
);
--! MII link initialization
constant cMiiInit : tMii := (
rx => cMiiPathInit,
tx => cMiiPathInit
);
--! Functio to get tRmiiPathArray enables.
function rmiiGetEnable ( iArray : tRmiiPathArray ) return std_logic_vector;
--! Procedure to convert tRmiiPathArray to std_logic_vector.
procedure rmiiPathArrayToStdLogicVector (
signal iVector : in tRmiiPathArray;
signal oEnable : out std_logic_vector;
signal oData : out std_logic_vector
);
--! Procedure to convert std_logic_vector to tRmiiPathArray
procedure stdLogicVectorToRmiiPathArray (
signal iEnable : in std_logic_vector;
signal iData : in std_logic_vector;
signal oVector : out tRmiiPathArray
);
--! Procedure to convert tMiiPathArray to std_logic_vector.
procedure miiPathArrayToStdLogicVector (
signal iVector : in tMiiPathArray;
signal oEnable : out std_logic_vector;
signal oData : out std_logic_vector
);
--! Procedure to convert std_logic_vector to tMiiPathArray
procedure stdLogicVectorToMiiPathArray (
signal iEnable : in std_logic_vector;
signal iData : in std_logic_vector;
signal oVector : out tMiiPathArray
);
---------------------------------------------------------------------------
-- Memory mapping
---------------------------------------------------------------------------
--! Memory range type
type tMemRange is record
base : natural;
high : natural;
end record;
--! openMAC memory mapping type
type tMemMap is array (natural range <>) of tMemRange;
--! openMAC memory map count
constant cMemMapCount : natural := 6;
--! openMAC memory map index for DMA Error
constant cMemMapIndex_dmaError : natural := 5;
--! openMAC memory map index for IRQ Table
constant cMemMapIndex_irqTable : natural := 4;
--! openMAC memory map index for SMI
constant cMemMapIndex_smi : natural := 3;
--! openMAC memory map index for MAC RAM
constant cMemMapIndex_macRam : natural := 2;
--! openMAC memory map index for MAC Filter
constant cMemMapIndex_macFilter : natural := 1;
--! openMAC memory map index for MAC Content
constant cMemMapIndex_macCont : natural := 0;
--! openMAC memory mapping table
constant cMemMapTable : tMemMap(cMemMapCount-1 downto 0) := (
(base => 16#1020#, high => 16#102F#), -- DMA error
(base => 16#1010#, high => 16#101F#), -- IRQ table
(base => 16#1000#, high => 16#100F#), -- SMI
(base => 16#0800#, high => 16#0FFF#), -- MAC ram
(base => 16#0800#, high => 16#0BFF#), -- MAC filter
(base => 16#0000#, high => 16#03FF#) -- MAC content
);
---------------------------------------------------------------------------
-- Access delay
---------------------------------------------------------------------------
--! Access delay type
type tMemAccessDelay is record
write : natural;
read : natural;
end record;
--! Access delay type
type tMemAccessDelayArray is array (natural range <>) of tMemAccessDelay;
--! Access delay count
constant cMemAccessDelayCount : natural := 3;
--! Access delay index for PKT BUFFER
constant cMemAccessDelayIndex_pktBuf : natural := 2;
--! Access delay index for MAC TIMER
constant cMemAccessDelayIndex_macTimer : natural := 1;
--! Access delay index for MAC REG
constant cMemAccessDelayIndex_macReg : natural := 0;
--! Access delay table
constant cMemAccessDelayTable : tMemAccessDelayArray(cMemAccessDelayCount-1 downto 0) := (
(write => 0, read => 1), -- PKT BUFFER
(write => 0, read => 1), -- MAC TIMER
(write => 0, read => 1) -- MAC REG
);
--! Access acknowlegde type
type tMemAccessAck is record
write : std_logic;
read : std_logic;
end record;
--! Access acknowledge array type
type tMemAccessAckArray is array (natural range <>) of tMemAccessAck;
---------------------------------------------------------------------------
-- Constants for openmac
---------------------------------------------------------------------------
--! MAC REGISTER address width
constant cMacRegAddrWidth : natural := 13;
--! MAC REGISTER data width
constant cMacRegDataWidth : natural := 16;
--! MAC TIMER address width
constant cMacTimerAddrWidth : natural := 4;
--! MAC TIMER data width
constant cMacTimerDataWidth : natural := 32;
--! MAC PACKET BUFFER data width
constant cPktBufDataWidth : natural := 32;
--! MAC TIME width
constant cMacTimeWidth : natural := 32;
---------------------------------------------------------------------------
-- Constants for activity blinking
---------------------------------------------------------------------------
--! The activity blink frequency [Hz]
constant cActivityFreq : natural := 6;
--! Clock frequency of iClk [Hz]
constant cClkFreq : natural := 50e6;
---------------------------------------------------------------------------
-- Constants for openhub
---------------------------------------------------------------------------
--! Internal port number
constant cHubIntPort : natural := 1;
---------------------------------------------------------------------------
-- Interrupt table
---------------------------------------------------------------------------
--! Interrupt table subtype
subtype tMacRegIrqTable is std_logic_vector(cMacRegDataWidth-1 downto 0);
--! MAC Tx interrupt offset
constant cMacRegIrqTable_macTx : natural := 0;
--! MAC Rx interrupt offset
constant cMacRegIrqTable_macRx : natural := 1;
---------------------------------------------------------------------------
-- DMA Error table
---------------------------------------------------------------------------
--! DMA error table subtype
subtype tMacDmaErrorTable is std_logic_vector(cMacRegDataWidth-1 downto 0);
--! DMA error write (Rx packet transfer)
constant cMacDmaErrorTable_write : natural := 0;
--! DMA error read (Tx packet transfer)
constant cMacDmaErrorTable_read : natural := 8;
end package openmacPkg;
package body openmacPkg is
--! Functio to get tRmiiPathArray enables.
function rmiiGetEnable ( iArray : tRmiiPathArray ) return std_logic_vector is
variable vRes_tmp : std_logic_vector(iArray'range);
begin
vRes_tmp := (others => cInactivated);
for i in iArray'range loop
vRes_tmp(i) := iArray(i).enable;
end loop;
return vRes_tmp;
end function;
--! Procedure to convert tRmiiPathArray to std_logic_vector.
procedure rmiiPathArrayToStdLogicVector (
signal iVector : in tRmiiPathArray;
signal oEnable : out std_logic_vector;
signal oData : out std_logic_vector
) is
variable vVector_tmp : tRmiiPathArray(iVector'length-1 downto 0);
begin
vVector_tmp := iVector;
for i in vVector_tmp'range loop
oEnable(i) <= vVector_tmp(i).enable;
for j in cRmiiDataWidth-1 downto 0 loop
oData(i*cRmiiDataWidth+j) <= vVector_tmp(i).data(j);
end loop;
end loop;
end procedure;
--! Procedure to convert std_logic_vector to tRmiiPathArray
procedure stdLogicVectorToRmiiPathArray (
signal iEnable : in std_logic_vector;
signal iData : in std_logic_vector;
signal oVector : out tRmiiPathArray
) is
variable vVector_tmp : tRmiiPathArray(iEnable'length-1 downto 0);
begin
for i in vVector_tmp'range loop
vVector_tmp(i).enable := iEnable(i);
for j in cRmiiDataWidth-1 downto 0 loop
vVector_tmp(i).data(j) := iData(i*cRmiiDataWidth+j);
end loop;
end loop;
oVector <= vVector_tmp;
end procedure;
--! Procedure to convert tMiiPathArray to std_logic_vector.
procedure miiPathArrayToStdLogicVector (
signal iVector : in tMiiPathArray;
signal oEnable : out std_logic_vector;
signal oData : out std_logic_vector
) is
variable vVector_tmp : tMiiPathArray(iVector'length-1 downto 0);
begin
vVector_tmp := iVector;
for i in vVector_tmp'range loop
oEnable(i) <= vVector_tmp(i).enable;
for j in cMiiDataWidth-1 downto 0 loop
oData(i*cMiiDataWidth+j) <= vVector_tmp(i).data(j);
end loop;
end loop;
end procedure;
--! Procedure to convert std_logic_vector to tMiiPathArray
procedure stdLogicVectorToMiiPathArray (
signal iEnable : in std_logic_vector;
signal iData : in std_logic_vector;
signal oVector : out tMiiPathArray
) is
variable vVector_tmp : tMiiPathArray(iEnable'length-1 downto 0);
begin
for i in vVector_tmp'range loop
vVector_tmp(i).enable := iEnable(i);
for j in cMiiDataWidth-1 downto 0 loop
vVector_tmp(i).data(j) := iData(i*cMiiDataWidth+j);
end loop;
end loop;
oVector <= vVector_tmp;
end procedure;
end package body openmacPkg;
| gpl-2.0 | aea5ccb72bb2b81bf7f159179e7d9bde | 0.553394 | 5.030946 | false | false | false | false |
FinnK/lems2hdl | work/N3_pointCellCondBased/ISIM_output/reverseRaten1.vhdl | 1 | 10,652 |
---------------------------------------------------------------------
-- Standard Library bits
---------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- For Modelsim
--use ieee.fixed_pkg.all;
--use ieee.fixed_float_types.ALL;
-- For ISE
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use ieee_proposed.fixed_float_types.ALL;
use IEEE.numeric_std.all;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Entity Description
---------------------------------------------------------------------
entity reverseRaten1 is
Port (
clk : in STD_LOGIC; --SYSTEM CLOCK, THIS ITSELF DOES NOT SIGNIFY TIME STEPS - AKA A SINGLE TIMESTEP MAY TAKE MANY CLOCK CYCLES
init_model : in STD_LOGIC; --SYNCHRONOUS RESET
step_once_go : in STD_LOGIC; --signals to the neuron from the core that a time step is to be simulated
component_done : out STD_LOGIC;
requirement_voltage_v : in sfixed (2 downto -22);
param_per_time_rate : in sfixed (18 downto -2);
param_voltage_midpoint : in sfixed (2 downto -22);
param_voltage_scale : in sfixed (2 downto -22);
param_voltage_inv_scale_inv : in sfixed (22 downto -2);
exposure_per_time_r : out sfixed (18 downto -2);
derivedvariable_per_time_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_r_in : in sfixed (18 downto -2);
sysparam_time_timestep : in sfixed (-6 downto -22);
sysparam_time_simtime : in sfixed (6 downto -22)
);
end reverseRaten1;
---------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-- Architecture Begins
-------------------------------------------------------------------------------------------
architecture RTL of reverseRaten1 is
signal COUNT : unsigned(2 downto 0) := "000";
signal childrenCombined_Component_done_single_shot_fired : STD_LOGIC := '0';
signal childrenCombined_Component_done_single_shot : STD_LOGIC := '0';
signal childrenCombined_Component_done : STD_LOGIC := '0';
signal Component_done_int : STD_LOGIC := '0';
signal subprocess_der_int_pre_ready : STD_LOGIC := '0';
signal subprocess_der_int_ready : STD_LOGIC := '0';
signal subprocess_der_ready : STD_LOGIC := '0';
signal subprocess_dyn_int_pre_ready : STD_LOGIC := '0';
signal subprocess_dyn_int_ready : STD_LOGIC := '0';
signal subprocess_dyn_ready : STD_LOGIC := '0';
signal subprocess_model_ready : STD_LOGIC := '1';
signal subprocess_all_ready_shotdone : STD_LOGIC := '1';
signal subprocess_all_ready_shot : STD_LOGIC := '0';
signal subprocess_all_ready : STD_LOGIC := '0';signal pre_exp_r_exponential_result1 : sfixed(18 downto -13);
signal pre_exp_r_exponential_result1_next : sfixed(18 downto -13);
signal exp_r_exponential_result1 : sfixed(18 downto -13);
Component ParamExp is
generic(
BIT_TOP : integer := 20;
BIT_BOTTOM : integer := -20);
port(
clk : In Std_logic;
init_model : In Std_logic;
Start : In Std_logic;
Done : Out Std_logic;
X : In sfixed(BIT_TOP downto BIT_BOTTOM);
Output : Out sfixed(BIT_TOP downto BIT_BOTTOM)
);
end Component;
---------------------------------------------------------------------
-- Derived Variables and parameters
---------------------------------------------------------------------
signal DerivedVariable_per_time_r : sfixed (18 downto -2) := to_sfixed(0.0 ,18,-2);
signal DerivedVariable_per_time_r_next : sfixed (18 downto -2) := to_sfixed(0.0 ,18,-2);
---------------------------------------------------------------------
---------------------------------------------------------------------
-- EDState internal Variables
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Output Port internal Variables
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Child Components
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Begin Internal Processes
---------------------------------------------------------------------
begin
---------------------------------------------------------------------
-- Child EDComponent Instantiations and corresponding internal variables
---------------------------------------------------------------------
derived_variable_pre_process_comb :process ( sysparam_time_timestep, param_voltage_midpoint, param_voltage_scale, requirement_voltage_v , param_per_time_rate,param_voltage_inv_scale_inv,exp_r_exponential_result1 )
begin
pre_exp_r_exponential_result1_next <= resize( ( ( requirement_voltage_v - param_voltage_midpoint ) * param_voltage_inv_scale_inv ) ,18,-13);
end process derived_variable_pre_process_comb;
derived_variable_pre_process_syn :process ( clk, init_model )
begin
if (clk'EVENT AND clk = '1') then
if init_model = '1' then
pre_exp_r_exponential_result1 <= to_sfixed(0,18,-13);
else
if subprocess_all_ready_shot = '1' then
pre_exp_r_exponential_result1 <= pre_exp_r_exponential_result1_next;
end if;
end if;
end if;
subprocess_der_int_pre_ready <= '1';
end process derived_variable_pre_process_syn;
ParamExp_r_exponential_result1 : ParamExp
generic map(
BIT_TOP => 18,
BIT_BOTTOM => -13
)
port map ( clk => clk,
init_model => init_model,
Start => step_once_go,
Done => subprocess_der_int_ready,
X => pre_exp_r_exponential_result1 ,
Output => exp_r_exponential_result1
);
derived_variable_process_comb :process ( sysparam_time_timestep, param_voltage_midpoint, param_voltage_scale, requirement_voltage_v , param_per_time_rate,param_voltage_inv_scale_inv,exp_r_exponential_result1 )
begin
derivedvariable_per_time_r_next <= resize(( param_per_time_rate * exp_r_exponential_result1 ),18,-2);
subprocess_der_ready <= '1';
end process derived_variable_process_comb;
derived_variable_process_syn :process ( clk,init_model )
begin
if clk'event and clk = '1' then
if subprocess_all_ready_shot = '1' then
derivedvariable_per_time_r <= derivedvariable_per_time_r_next;
end if;
end if;
end process derived_variable_process_syn;
---------------------------------------------------------------------
dynamics_pre_process_comb :process ( sysparam_time_timestep )
begin
end process dynamics_pre_process_comb;
dynamics_pre_process_syn :process ( clk, init_model )
begin
subprocess_dyn_int_pre_ready <= '1';
end process dynamics_pre_process_syn;
--No dynamics with complex equations found
subprocess_dyn_int_ready <= '1';
state_variable_process_dynamics_comb :process (sysparam_time_timestep)
begin
subprocess_dyn_ready <= '1';
end process state_variable_process_dynamics_comb;
state_variable_process_dynamics_syn :process (CLK,init_model)
begin
if clk'event and clk = '1' then
if subprocess_all_ready_shot = '1' then
end if;
end if;
end process state_variable_process_dynamics_syn;
------------------------------------------------------------------------------------------------------
-- EDState Variable Drivers
------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign state variables to exposures
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign state variables to output state variables
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign derived variables to exposures
---------------------------------------------------------------------
exposure_per_time_r <= derivedvariable_per_time_r_in;derivedvariable_per_time_r_out <= derivedvariable_per_time_r;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Subprocess ready process
---------------------------------------------------------------------
subprocess_all_ready_process: process(step_once_go,subprocess_der_int_ready,subprocess_der_int_pre_ready,subprocess_der_ready,subprocess_dyn_int_pre_ready,subprocess_dyn_int_ready,subprocess_dyn_ready,subprocess_model_ready)
begin
if step_once_go = '0' and subprocess_der_int_ready = '1' and subprocess_der_int_pre_ready = '1'and subprocess_der_ready ='1' and subprocess_dyn_int_ready = '1' and subprocess_dyn_int_pre_ready = '1' and subprocess_dyn_ready = '1' and subprocess_model_ready = '1' then
subprocess_all_ready <= '1';
else
subprocess_all_ready <= '0';
end if;
end process subprocess_all_ready_process;
subprocess_all_ready_shot_process : process(clk)
begin
if rising_edge(clk) then
if (init_model='1') then
subprocess_all_ready_shot <= '0';
subprocess_all_ready_shotdone <= '1';
else
if subprocess_all_ready = '1' and subprocess_all_ready_shotdone = '0' then
subprocess_all_ready_shot <= '1';
subprocess_all_ready_shotdone <= '1';
elsif subprocess_all_ready_shot = '1' then
subprocess_all_ready_shot <= '0';
elsif subprocess_all_ready = '0' then
subprocess_all_ready_shot <= '0';
subprocess_all_ready_shotdone <= '0';
end if;
end if;
end if;
end process subprocess_all_ready_shot_process;
---------------------------------------------------------------------
count_proc:process(clk)
begin
if (clk'EVENT AND clk = '1') then
if init_model = '1' then COUNT <= "001";
component_done_int <= '1';
else if step_once_go = '1' then
COUNT <= "000";
component_done_int <= '0';
elsif COUNT = "001" then
component_done_int <= '1';
elsif subprocess_all_ready_shot = '1' then
COUNT <= COUNT + 1;
component_done_int <= '0';
end if;
end if;
end if;
end process count_proc;
component_done <= component_done_int;
end RTL;
| lgpl-3.0 | 3ac765b5a9b57173d7e34860ad7e7016 | 0.506947 | 4.08906 | false | false | false | false |
FinnK/lems2hdl | work/N2_Izhikevich/ISIM_output/neuron_model.vhdl | 1 | 19,550 |
---------------------------------------------------------------------
-- Standard Library bits
---------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- For Modelsim
--use ieee.fixed_pkg.all;
--use ieee.fixed_float_types.ALL;
-- For ISE
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use ieee_proposed.fixed_float_types.ALL;
use IEEE.numeric_std.all;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Entity Description
---------------------------------------------------------------------
entity neuron_model is
Port (
clk : in STD_LOGIC; --SYSTEM CLOCK, THIS ITSELF DOES NOT SIGNIFY TIME STEPS - AKA A SINGLE TIMESTEP MAY TAKE MANY CLOCK CYCLES
init_model : in STD_LOGIC; --SYNCHRONOUS RESET
step_once_go : in STD_LOGIC; --signals to the neuron from the core that a time step is to be simulated
step_once_complete : out STD_LOGIC; --signals to the core that a time step has finished
eventport_in_spike_aggregate : in STD_LOGIC_VECTOR(511 downto 0);
eventport_out_spike : out STD_LOGIC;
param_voltage_v0 : in sfixed (2 downto -22);
param_none_a : in sfixed (18 downto -13);
param_none_b : in sfixed (18 downto -13);
param_none_c : in sfixed (18 downto -13);
param_none_d : in sfixed (18 downto -13);
param_voltage_thresh : in sfixed (2 downto -22);
param_time_MSEC : in sfixed (6 downto -18);
param_voltage_MVOLT : in sfixed (2 downto -22);
param_time_inv_MSEC_inv : in sfixed (18 downto -6);
param_voltage_inv_MVOLT_inv : in sfixed (22 downto -2);
param_none_div_voltage_b_div_MVOLT : in sfixed (18 downto -13);
exposure_voltage_v : out sfixed (2 downto -22);
exposure_none_U : out sfixed (18 downto -13);
statevariable_voltage_v_out : out sfixed (2 downto -22);
statevariable_voltage_v_in : in sfixed (2 downto -22);
statevariable_none_U_out : out sfixed (18 downto -13);
statevariable_none_U_in : in sfixed (18 downto -13);
param_time_i1_delay : in sfixed (6 downto -18);
param_time_i1_duration : in sfixed (6 downto -18);
param_none_i1_amplitude : in sfixed (18 downto -13);
exposure_none_i1_I : out sfixed (18 downto -13);
statevariable_none_i1_I_out : out sfixed (18 downto -13);
statevariable_none_i1_I_in : in sfixed (18 downto -13);
sysparam_time_timestep : in sfixed (-6 downto -22);
sysparam_time_simtime : in sfixed (6 downto -22)
);
end neuron_model;
---------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-- Architecture Begins
-------------------------------------------------------------------------------------------
architecture RTL of neuron_model is
signal COUNT : unsigned(2 downto 0) := "000";
signal childrenCombined_Component_done_single_shot_fired : STD_LOGIC := '0';
signal childrenCombined_Component_done_single_shot : STD_LOGIC := '0';
signal childrenCombined_Component_done : STD_LOGIC := '0';
signal Component_done_int : STD_LOGIC := '0';
signal subprocess_der_int_pre_ready : STD_LOGIC := '0';
signal subprocess_der_int_ready : STD_LOGIC := '0';
signal subprocess_der_ready : STD_LOGIC := '0';
signal subprocess_dyn_int_pre_ready : STD_LOGIC := '0';
signal subprocess_dyn_int_ready : STD_LOGIC := '0';
signal subprocess_dyn_ready : STD_LOGIC := '0';
signal subprocess_model_ready : STD_LOGIC := '1';
signal subprocess_all_ready_shotdone : STD_LOGIC := '1';
signal subprocess_all_ready_shot : STD_LOGIC := '0';
signal subprocess_all_ready : STD_LOGIC := '0';signal i1_step_once_complete_fired : STD_LOGIC := '1';
signal step_once_complete_fired : STD_LOGIC := '1';
signal Component_done : STD_LOGIC := '0';
constant cNSpikeSources : integer := 512; -- The number of spike sources.
constant cNOutputs : integer := 512; -- The number of Synapses in the neuron model.
constant cNSelectBits : integer := 9; -- Log2(NOutputs), rounded up.
signal SpikeOut : Std_logic_vector((cNOutputs-1) downto 0);
signal statevariable_voltage_noregime_v_temp_1 : sfixed (2 downto -22);
signal statevariable_voltage_noregime_v_temp_1_next : sfixed (2 downto -22);
signal statevariable_none_noregime_U_temp_1 : sfixed (18 downto -13);
signal statevariable_none_noregime_U_temp_1_next : sfixed (18 downto -13);
---------------------------------------------------------------------
-- Derived Variables and parameters
---------------------------------------------------------------------
signal DerivedVariable_none_ISyn : sfixed (18 downto -13) := to_sfixed(0.0 ,18,-13);
signal DerivedVariable_none_ISyn_next : sfixed (18 downto -13) := to_sfixed(0.0 ,18,-13);
---------------------------------------------------------------------
---------------------------------------------------------------------
-- EDState internal Variables
---------------------------------------------------------------------
signal statevariable_voltage_v_next : sfixed (2 downto -22);
signal statevariable_none_U_next : sfixed (18 downto -13);
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Output Port internal Variables
---------------------------------------------------------------------
signal EventPort_out_spike_internal : std_logic := '0';
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Child Components
---------------------------------------------------------------------
component i1
Port (
clk : in STD_LOGIC; --SYSTEM CLOCK, THIS ITSELF DOES NOT SIGNIFY TIME STEPS - AKA A SINGLE TIMESTEP MAY TAKE MANY CLOCK CYCLES
init_model : in STD_LOGIC;
step_once_go : in STD_LOGIC; --signals to the neuron from the core that a time step is to be simulated
Component_done : out STD_LOGIC;
eventport_in_in : in STD_LOGIC;
param_time_delay : in sfixed (6 downto -18);
param_time_duration : in sfixed (6 downto -18);
param_none_amplitude : in sfixed (18 downto -13);
exposure_none_I : out sfixed (18 downto -13);
statevariable_none_I_out : out sfixed (18 downto -13);
statevariable_none_I_in : in sfixed (18 downto -13);
sysparam_time_timestep : in sfixed (-6 downto -22);
sysparam_time_simtime : in sfixed (6 downto -22)
);
end component;
signal i1_Component_done : STD_LOGIC ; signal Exposure_none_i1_I_internal : sfixed (18 downto -13);
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Begin Internal Processes
---------------------------------------------------------------------
begin
---------------------------------------------------------------------
-- Child EDComponent Instantiations and corresponding internal variables
---------------------------------------------------------------------
i1_uut : i1
port map (
clk => clk,
init_model => init_model,
step_once_go => step_once_go,
Component_done => i1_Component_done,
eventport_in_in => EventPort_in_spike_aggregate(0),
param_time_delay => param_time_i1_delay,
param_time_duration => param_time_i1_duration,
param_none_amplitude => param_none_i1_amplitude,
Exposure_none_I => Exposure_none_i1_I_internal,
statevariable_none_I_out => statevariable_none_i1_I_out,
statevariable_none_I_in => statevariable_none_i1_I_in,
sysparam_time_timestep => sysparam_time_timestep,
sysparam_time_simtime => sysparam_time_simtime
);
Exposure_none_i1_I <= Exposure_none_i1_I_internal;
derived_variable_pre_process_comb :process ( sysparam_time_timestep,exposure_none_i1_I_internal )
begin
end process derived_variable_pre_process_comb;
derived_variable_pre_process_syn :process ( clk, init_model )
begin
subprocess_der_int_pre_ready <= '1';
end process derived_variable_pre_process_syn;
--no complex steps in derived variables
subprocess_der_int_ready <= '1';
derived_variable_process_comb :process ( sysparam_time_timestep,exposure_none_i1_I_internal )
begin
derivedvariable_none_ISyn_next <= resize(( exposure_none_i1_I_internal ),18,-13);
subprocess_der_ready <= '1';
end process derived_variable_process_comb;
derived_variable_process_syn :process ( clk,init_model )
begin
if clk'event and clk = '1' then
if subprocess_all_ready_shot = '1' then
derivedvariable_none_ISyn <= derivedvariable_none_ISyn_next;
end if;
end if;
end process derived_variable_process_syn;
---------------------------------------------------------------------
dynamics_pre_process_comb :process ( sysparam_time_timestep, param_voltage_MVOLT, statevariable_voltage_v_in , statevariable_none_U_in , derivedvariable_none_ISyn , param_time_MSEC,param_time_inv_MSEC_inv,param_voltage_inv_MVOLT_inv , param_voltage_MVOLT, statevariable_voltage_v_in , statevariable_none_U_in , param_none_b, param_none_a, param_time_MSEC )
begin
end process dynamics_pre_process_comb;
dynamics_pre_process_syn :process ( clk, init_model )
begin
subprocess_dyn_int_pre_ready <= '1';
end process dynamics_pre_process_syn;
--No dynamics with complex equations found
subprocess_dyn_int_ready <= '1';
state_variable_process_dynamics_comb :process (sysparam_time_timestep, param_voltage_MVOLT, statevariable_voltage_v_in , statevariable_none_U_in , derivedvariable_none_ISyn , param_time_MSEC,param_time_inv_MSEC_inv,param_voltage_inv_MVOLT_inv , param_voltage_MVOLT, statevariable_voltage_v_in , statevariable_none_U_in , param_none_b, param_none_a, param_time_MSEC ,statevariable_voltage_v_in,statevariable_none_U_in)
begin
statevariable_voltage_noregime_v_temp_1_next <= resize(statevariable_voltage_v_in + ( ( to_sfixed ( 0.04 ,0 , -27 ) * statevariable_voltage_v_in * statevariable_voltage_v_in * param_voltage_inv_MVOLT_inv + to_sfixed ( 5 ,3 , -1 ) * statevariable_voltage_v_in + ( to_sfixed ( 140.0 ,8 , -1 ) - statevariable_none_U_in + derivedvariable_none_ISyn ) * param_voltage_MVOLT ) * param_time_inv_MSEC_inv ) * sysparam_time_timestep,2,-22);
statevariable_none_noregime_U_temp_1_next <= resize(statevariable_none_U_in + ( param_none_a * ( param_none_b * statevariable_voltage_v_in * param_voltage_inv_MVOLT_inv - statevariable_none_U_in ) * param_time_inv_MSEC_inv ) * sysparam_time_timestep,18,-13);
subprocess_dyn_ready <= '1';
end process state_variable_process_dynamics_comb;
state_variable_process_dynamics_syn :process (CLK,init_model)
begin
if clk'event and clk = '1' then
if subprocess_all_ready_shot = '1' then
statevariable_voltage_noregime_v_temp_1 <= statevariable_voltage_noregime_v_temp_1_next;
statevariable_none_noregime_U_temp_1 <= statevariable_none_noregime_U_temp_1_next;
end if;
end if;
end process state_variable_process_dynamics_syn;
------------------------------------------------------------------------------------------------------
-- EDState Variable Drivers
------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------
-- EDState variable: $par.name Driver Process
---------------------------------------------------------------------
state_variable_process_comb_0 :process (sysparam_time_timestep,init_model,param_voltage_v0,param_voltage_thresh,statevariable_voltage_v_in,param_voltage_MVOLT,param_none_c,statevariable_none_U_in,param_none_d,statevariable_voltage_noregime_v_temp_1,param_voltage_MVOLT,statevariable_voltage_v_in,statevariable_none_U_in,derivedvariable_none_ISyn,param_time_MSEC,param_time_inv_MSEC_inv,param_voltage_inv_MVOLT_inv)
variable statevariable_voltage_v_temp_1 : sfixed (2 downto -22);
variable statevariable_voltage_v_temp_2 : sfixed (2 downto -22);
begin
statevariable_voltage_v_temp_1 := statevariable_voltage_noregime_v_temp_1; if To_slv ( resize ( statevariable_voltage_v_in - ( param_voltage_thresh ) ,2,-18))(20) = '0' then
statevariable_voltage_v_temp_2 := resize( param_none_c * param_voltage_MVOLT ,2,-22);
else
statevariable_voltage_v_temp_2 := statevariable_voltage_v_temp_1;
end if;
statevariable_voltage_v_next <= statevariable_voltage_v_temp_2;
end process;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- EDState variable: $par.name Driver Process
---------------------------------------------------------------------
state_variable_process_comb_1 :process (sysparam_time_timestep,init_model,param_voltage_v0,param_voltage_MVOLT,param_none_b,param_voltage_v0,param_none_div_voltage_b_div_MVOLT,param_voltage_thresh,statevariable_voltage_v_in,param_voltage_MVOLT,param_none_c,statevariable_none_U_in,param_none_d,statevariable_none_noregime_U_temp_1,param_voltage_MVOLT,statevariable_voltage_v_in,statevariable_none_U_in,param_none_b,param_none_a,param_time_MSEC)
variable statevariable_none_U_temp_1 : sfixed (18 downto -13);
variable statevariable_none_U_temp_2 : sfixed (18 downto -13);
begin
statevariable_none_U_temp_1 := statevariable_none_noregime_U_temp_1; if To_slv ( resize ( statevariable_voltage_v_in - ( param_voltage_thresh ) ,2,-18))(20) = '0' then
statevariable_none_U_temp_2 := resize( statevariable_none_U_in + param_none_d ,18,-13);
else
statevariable_none_U_temp_2 := statevariable_none_U_temp_1;
end if;
statevariable_none_U_next <= statevariable_none_U_temp_2;
end process;
---------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
eventport_driver0 :process ( clk,sysparam_time_timestep,init_model, param_voltage_thresh, statevariable_voltage_v_in , param_voltage_MVOLT, param_none_c, statevariable_none_U_in , param_none_d )
variable eventport_out_spike_temp_1 : std_logic;
variable eventport_out_spike_temp_2 : std_logic;
begin
if rising_edge(clk) and subprocess_all_ready_shot = '1' then
if To_slv ( resize ( statevariable_voltage_v_in - ( param_voltage_thresh ) ,2,-18))(20) = '0' then
eventport_out_spike_temp_1 := '1';
else
eventport_out_spike_temp_1 := '0';
end if;eventport_out_spike_internal <= eventport_out_spike_temp_1;
end if;
end process;
---------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign state variables to exposures
---------------------------------------------------------------------
exposure_voltage_v <= statevariable_voltage_v_in;exposure_none_U <= statevariable_none_U_in;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign state variables to output state variables
---------------------------------------------------------------------
statevariable_voltage_v_out <= statevariable_voltage_v_next;statevariable_none_U_out <= statevariable_none_U_next;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign derived variables to exposures
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Subprocess ready process
---------------------------------------------------------------------
subprocess_all_ready_process: process(step_once_go,subprocess_der_int_ready,subprocess_der_int_pre_ready,subprocess_der_ready,subprocess_dyn_int_pre_ready,subprocess_dyn_int_ready,subprocess_dyn_ready,subprocess_model_ready)
begin
if step_once_go = '0' and subprocess_der_int_ready = '1' and subprocess_der_int_pre_ready = '1'and subprocess_der_ready ='1' and subprocess_dyn_int_ready = '1' and subprocess_dyn_int_pre_ready = '1' and subprocess_dyn_ready = '1' and subprocess_model_ready = '1' then
subprocess_all_ready <= '1';
else
subprocess_all_ready <= '0';
end if;
end process subprocess_all_ready_process;
subprocess_all_ready_shot_process : process(clk)
begin
if rising_edge(clk) then
if (init_model='1') then
subprocess_all_ready_shot <= '0';
subprocess_all_ready_shotdone <= '1';
else
if subprocess_all_ready = '1' and subprocess_all_ready_shotdone = '0' then
subprocess_all_ready_shot <= '1';
subprocess_all_ready_shotdone <= '1';
elsif subprocess_all_ready_shot = '1' then
subprocess_all_ready_shot <= '0';
elsif subprocess_all_ready = '0' then
subprocess_all_ready_shot <= '0';
subprocess_all_ready_shotdone <= '0';
end if;
end if;
end if;
end process subprocess_all_ready_shot_process;
---------------------------------------------------------------------
count_proc:process(clk)
begin
if (clk'EVENT AND clk = '1') then
if init_model = '1' then COUNT <= "001";
component_done_int <= '1';
else if step_once_go = '1' then
COUNT <= "000";
component_done_int <= '0';
elsif COUNT = "001" then
component_done_int <= '1';
elsif subprocess_all_ready_shot = '1' then
COUNT <= COUNT + 1;
component_done_int <= '0';
end if;
end if;
end if;
end process count_proc;
childrenCombined_component_done_process:process(i1_component_done,CLK)
begin
if (i1_component_done = '1') then
childrenCombined_component_done <= '1';
else
childrenCombined_component_done <= '0';
end if;
end process childrenCombined_component_done_process;
component_done <= component_done_int and childrenCombined_component_done;
---------------------------------------------------------------------
-- Control the done signal
---------------------------------------------------------------------
step_once_complete_synch:process(clk)
begin
if (clk'EVENT AND clk = '1') then
if init_model = '1' then step_once_complete <= '0';
step_once_complete_fired <= '1';
else if component_done = '1' and step_once_complete_fired = '0' then
step_once_complete <= '1';
step_once_complete_fired <= '1';
---------------------------------------------------------------------
-- Assign event ports to exposures
---------------------------------------------------------------------
eventport_out_spike <= eventport_out_spike_internal ;
---------------------------------------------------------------------
elsif component_done = '0' then
step_once_complete <= '0';
step_once_complete_fired <= '0';
---------------------------------------------------------------------
-- Assign event ports to exposures
---------------------------------------------------------------------
eventport_out_spike <= '0';
---------------------------------------------------------------------
else
step_once_complete <= '0';
---------------------------------------------------------------------
-- Assign event ports to exposures
---------------------------------------------------------------------
eventport_out_spike <= '0';
---------------------------------------------------------------------
end if;
end if;
end if;
end process step_once_complete_synch;
---------------------------------------------------------------------
end RTL;
| lgpl-3.0 | ca129d885a54e1bed7dc1ad78bc01fe8 | 0.553657 | 3.76251 | false | false | false | false |
Wynjones1/VHDL-Build | example/text_display/text_area.vhd | 1 | 5,152 | library IEEE;
use IEEE.numeric_std.all;
use IEEE.std_logic_1164.all;
use work.display_comp.all;
package text_display_comp is
type text_display_in_t is
record
wx : natural range 0 to TEXT_WIDTH - 1;
wy : natural range 0 to TEXT_HEIGHT - 1;
we : std_logic;
wd : character_t;
end record;
type text_display_out_t is
record
colour : std_logic_vector(7 downto 0);
hs : std_logic;
vs : std_logic;
end record;
end text_display_comp;
library IEEE;
use IEEE.numeric_std.all;
use IEEE.std_logic_1164.all;
use work.vga_comp.all;
use work.text_ram_comp.all;
use work.text_display_comp.all;
use work.display_comp.all;
entity text_display is
port( clk : in std_logic;
reset : in std_logic;
input : in text_display_in_t;
output : out text_display_out_t);
end;
architecture rtl of text_display is
-- components
component clk_gen is
generic( CLOCK_SPEED : integer := 50_000_000;
REQUIRED_HZ : integer := 1);
port( clk : in std_logic;
reset : in std_logic;
clk_out : out std_logic);
end component;
component vga is
port(clk : in std_logic;
reset : in std_logic;
output : out vga_out_t);
end component;
component text_ram is
port(clk : in std_logic;
reset : in std_logic;
input : in text_ram_in_t;
output : out text_ram_out_t);
end component;
-- types
type tile_info_t is
record
tile_x : natural range 0 to TEXT_WIDTH - 1;
tile_y : natural range 0 to TEXT_HEIGHT - 1;
offset_x : natural range 0 to TILE_WIDTH - 1;
offset_y : natural range 0 to TILE_HEIGHT - 1;
end record;
type stage0_t is
record
ti : tile_info_t;
hs : std_logic;
vs : std_logic;
en : std_logic;
end record;
type stage1_t is
record
ti : tile_info_t;
hs : std_logic;
vs : std_logic;
en : std_logic;
ch : character_t;
end record;
type stage2_t is
record
ti : tile_info_t;
hs : std_logic;
vs : std_logic;
en : std_logic;
gl : glyph_t;
end record;
-- functions
function get_glyph_value(glyph : glyph_t; x : integer; y : integer) return std_logic is
begin
return glyph(y)(7 - x);
end function;
function make_tile_info(pix_x : natural; pix_y : natural) return tile_info_t is
begin
return (pix_x / TILE_WIDTH,
pix_y / TILE_HEIGHT,
pix_x mod TILE_WIDTH,
pix_y mod TILE_HEIGHT);
end function;
-- constants
constant NUM_STAGES : natural := 3;
-- signals
signal vga_clk_s : std_logic;
signal vga_out_s : vga_out_t;
signal stage0_s : stage0_t;
signal stage0_n : stage0_t;
signal stage1_s : stage1_t;
signal stage1_n : stage1_t;
signal stage2_s : stage2_t;
signal stage2_n : stage2_t;
signal output_n : text_display_out_t;
signal ram_in_s : text_ram_in_t;
signal ram_out_s : text_ram_out_t;
begin
clk_gen_0: clk_gen
generic map (REQUIRED_HZ => 25_000_000)
port map (clk, reset, vga_clk_s);
vga_0: vga
port map (vga_clk_s, reset, vga_out_s);
text_ram_0: text_ram
port map (clk, reset, ram_in_s, ram_out_s);
comb :
process(vga_out_s, stage0_s, stage1_s, stage2_s, ram_out_s)
begin
-- sync -> tile info -> char -> glyph -> colour
stage0_n.ti <= make_tile_info(vga_out_s.pix_x, vga_out_s.pix_y);
stage0_n.vs <= vga_out_s.vs;
stage0_n.hs <= vga_out_s.hs;
stage0_n.en <= vga_out_s.en;
ram_in_s <= (input.we, input.wd, input.wx, input.wy, vga_out_s.pix_x / TILE_WIDTH, vga_out_s.pix_y / TILE_HEIGHT);
stage1_n.ti <= stage0_s.ti;
stage1_n.vs <= stage0_s.vs;
stage1_n.hs <= stage0_s.hs;
stage1_n.en <= stage0_s.en;
stage1_n.ch <= ram_out_s.data;
stage2_n.ti <= stage1_s.ti;
stage2_n.vs <= stage1_s.vs;
stage2_n.hs <= stage1_s.hs;
stage2_n.en <= stage1_s.en;
stage2_n.gl <= FONT_ROM(stage1_s.ch);
if stage2_s.en = '1' then
output_n.colour <= (others => get_glyph_value( stage2_s.gl,
stage2_s.ti.offset_x,
stage2_s.ti.offset_y));
else
output_n.colour <= (others => '0');
end if;
output_n.hs <= stage2_s.hs;
output_n.vs <= stage2_s.vs;
end process;
seq :
process(clk, reset)
begin
if rising_edge(clk) then
stage0_s <= stage0_n;
stage1_s <= stage1_n;
stage2_s <= stage2_n;
output <= output_n;
end if;
end process;
end rtl;
| mit | cbde6a0367694d1a734ea495f4ad4ad4 | 0.516693 | 3.22403 | false | false | false | false |
dqydj/VGAtonic | Hardware_Rev_B/Widescreen Version Firmware/CPLD Firmware Widescreen/Display_Controller.vhd | 1 | 15,950 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity Display_Controller is
Port (
-- User logic clock
CLK : in STD_LOGIC; -- 60 Mhz Clock
-- Display Outputs:
PIXEL : inout STD_LOGIC_VECTOR(8 downto 0) := "111100110";
HSYNC : inout STD_LOGIC := '0';
VSYNC : inout STD_LOGIC := '0';
-- Memory Interface:
ADDR : out STD_LOGIC_VECTOR(18 downto 0) := (others => '0');
DATA : inout STD_LOGIC_VECTOR(7 downto 0);
OE_LOW : inout STD_LOGIC := '1';
WE_LOW : out STD_LOGIC := '1';
CE_LOW : out STD_LOGIC := '1';
----------------------------------------------------------------------------------
-- VGAtonic Internal --
----------------------------------------------------------------------------------
-- Inputs from SPI
SPI_DATA_CACHE : in STD_LOGIC_VECTOR(7 downto 0);
SPI_CACHE_FULL_FLAG : in STD_LOGIC;
SPI_CMD_RESET_FLAG : in STD_LOGIC;
-- Acknowledges to SPI
ACK_USER_RESET : inout STD_LOGIC := '0';
ACK_SPI_BYTE : out STD_LOGIC := '0'
);
end Display_Controller;
architecture Behavioral of Display_Controller is
-- Next Write
signal WRITE_DATA : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
-- READ for our constant refresh out the VGA port - 1008x494 @ 60 Hz (848x480 Active)
signal VGA_ROW_COUNT : STD_LOGIC_VECTOR(9 downto 0) := (others => '0');
signal VGA_PIXEL_COUNT : STD_LOGIC_VECTOR(10 downto 0) := (others => '0'); -- Now Max 1120
-- WRITE for our constant refresh out the VGA port (input from SPI) - 1008x494 @ 60 Hz (848x480 Active)
signal WRITE_ROW : STD_LOGIC_VECTOR(9 downto 0) := (others => '1');
signal WRITE_COLUMN : STD_LOGIC_VECTOR(9 downto 0) := (others => '1');
-- Bring Async signals into our clock domain
signal CACHE_FULL_FLAG : STD_LOGIC := '0';
signal CACHE_RESET_FLAG : STD_LOGIC := '0';
-- Write or Read cycle?
signal CYCLE : STD_LOGIC := '0';
-- Do we need to write? Should we reset write address?
signal WRITE_READY : STD_LOGIC := '0';
signal RESET_NEXT : STD_LOGIC := '0';
-- What resolution are we in?
-- 0 - 848x480
-- 1 - 424x240
signal USER_RES : STD_LOGIC := '0';
-- What bit depth are we in?
-- 00 - 8 bpp (256 Colors)
-- 01 - 4 bpp (16 Colors)
-- 10 - 2 bpp (4 Colors (B,W,GL,GH))
-- 11 - 1 bpp (2 Colors (B,W))
signal USER_BPP : STD_LOGIC_VECTOR(1 downto 0) := "00";
-- We treat masked off addresses as don't cares - unless we are muxing multiple
-- pixels from the same data
signal ADDR_MASK : STD_LOGIC_VECTOR(3 downto 0) := "1111";
-- Blanking periods, to avoid a ton of pterms
signal VBLANK : STD_LOGIC := '0';
signal HBLANK : STD_LOGIC := '0';
Function DecodeAddress
(
USER_RES : STD_LOGIC;
VGA_ROW_COUNT : STD_LOGIC_VECTOR(9 downto 0);
ADDR_MASK : STD_LOGIC_VECTOR(3 downto 0);
VGA_PIXEL_COUNT : STD_LOGIC_VECTOR(10 downto 0)
) return STD_LOGIC_VECTOR IS
variable tempAddress : STD_LOGIC_VECTOR(18 downto 0);
begin
tempAddress(18 downto 13) := VGA_ROW_COUNT(8 downto 3);
-- Handle multiple resolutions by changing it per user mode.
-- 640x480
-- case USER_RES is
-- WHEN "00" => tempAddress(12 downto 10) := VGA_ROW_COUNT(2 downto 0);
-- WHEN "01" => tempAddress(12 downto 10) := VGA_ROW_COUNT(2 downto 1) & '0';
-- WHEN "10" => tempAddress(12 downto 10) := VGA_ROW_COUNT(2) & "00";
-- WHEN others => tempAddress(12 downto 10) := "000";
-- end case;
tempAddress(12) := VGA_ROW_COUNT(2);
tempAddress(11) := VGA_ROW_COUNT(1);
tempAddress(10) := VGA_ROW_COUNT(0) and (not USER_RES);
tempAddress(9 downto 4) := VGA_PIXEL_COUNT(9 downto 4);
tempAddress(3 downto 0) := VGA_PIXEL_COUNT(3 downto 0) and ADDR_MASK;
return tempAddress;
end FUNCTION DecodeAddress;
begin
-- Our Write/Read Logic
-- Be very careful here since this controls writing/reading from the memory!
CE_LOW <= '0';
OE_LOW <= (not CYCLE);
WE_LOW <= CYCLE or CLK or (not WRITE_READY);
-- Should *only* output on the data bus if we're doing a write.
Write_Data_On_Bus: process (CLK, CYCLE, WRITE_READY, WRITE_DATA, WRITE_ROW)
begin
if ( (CYCLE or CLK) = '1' or WRITE_READY = '0') then
-- Normally be in High-Z mode, since the memory will be controlling the bus at this stage
DATA <= "ZZZZZZZZ";
else
-- Only when in the right clock cycle and we have a write ready
DATA <= WRITE_DATA;
end if;
-- As for address - we flip it every cycle (2 master clocks)
if (CYCLE = '0' and WRITE_READY = '1') then
-- We're about to write
ADDR <= WRITE_ROW(8 downto 0) & WRITE_COLUMN;
else
-- We're doing normal bus reads
ADDR <= DecodeAddress(USER_RES, VGA_ROW_COUNT, ADDR_MASK, VGA_PIXEL_COUNT);
end if;
-- And our lowest blue lonely pixel - have it follow the middle blue bit so we can get true grays.
-- This tradeoff is better than yellow and pink grays.
PIXEL(0) <= PIXEL(1);
end process;
Pixel_Output: process (OE_LOW)
-- Instead of fighting and casting below, just write a function
function integerFromStdLogic
(
input : STD_LOGIC
) return integer is
begin
if (input = '1') then
return 1;
else
return 0;
end if;
end integerFromStdLogic;
begin
if (rising_edge(OE_LOW)) then
if (VBLANK = '0' and HBLANK = '0') then -- then
--PIXEL <= DATA;
if (USER_BPP = "00") then
PIXEL(8 downto 1) <= DATA;
elsif (USER_BPP = "01") then
PIXEL(8 downto 1) <= ( DATA( to_integer(unsigned'(not VGA_PIXEL_COUNT(integerFromStdLogic(USER_RES)) & "11")) ),
DATA( to_integer(unsigned'(not VGA_PIXEL_COUNT(integerFromStdLogic(USER_RES)) & "00")) ),
DATA( to_integer(unsigned'(not VGA_PIXEL_COUNT(integerFromStdLogic(USER_RES)) & "00")) ),
DATA( to_integer(unsigned'(not VGA_PIXEL_COUNT(integerFromStdLogic(USER_RES)) & "10")) ),
DATA( to_integer(unsigned'(not VGA_PIXEL_COUNT(integerFromStdLogic(USER_RES)) & "00")) ),
DATA( to_integer(unsigned'(not VGA_PIXEL_COUNT(integerFromStdLogic(USER_RES)) & "00")) ),
DATA( to_integer(unsigned'(not VGA_PIXEL_COUNT(integerFromStdLogic(USER_RES)) & "01")) ),
DATA( to_integer(unsigned'(not VGA_PIXEL_COUNT(integerFromStdLogic(USER_RES)) & "00")) )
);
elsif (USER_BPP = "10") then
PIXEL(8 downto 1) <= ( 8 | 5 | 2 => DATA( to_integer(not unsigned(VGA_PIXEL_COUNT( integerFromStdLogic(USER_RES)+1 downto integerFromStdLogic(USER_RES) ) & '1'))),
others => DATA( to_integer(not unsigned(VGA_PIXEL_COUNT( integerFromStdLogic(USER_RES)+1 downto integerFromStdLogic(USER_RES) ) & '0')))
) ;
else
PIXEL(8 downto 1) <= (others => DATA(to_integer( unsigned(not VGA_PIXEL_COUNT(integerFromStdLogic(USER_RES)+2 downto integerFromStdLogic(USER_RES) ))) ));
--PIXEL(8 downto 1) <= (others => DATA( to_integer(unsigned( not VGA_PIXEL_COUNT(2 downto 0) ) )) );
end if;
else
PIXEL(8 downto 1) <= "00000000";
end if;
end if;
end process;
-- Code for Display Logic - Store the mask which we will use to decide our MSB while writing.
-- This is what gives us, effectively, hardware acceleration for lower BPP and resolution.
-- Compared to the 4:3 firmware, this one ignores the 2 lower resolutions (there is no equivalent of
-- 80x60 or 160x120)
Display_Logic: process (CLK, ACK_USER_RESET)
Function GetAddressMask
(
DATA : STD_LOGIC_VECTOR(7 downto 0)
) return STD_LOGIC_VECTOR IS
variable tempAddress : STD_LOGIC_VECTOR(3 downto 0);
begin
case DATA(3 downto 0) is
when "0000" | "0010" => tempAddress := "1111";
when "0100" | "0001" | "0110" | "0011" => tempAddress := "1110";
when "1000" | "0101" | "1010" | "0111" => tempAddress := "1100";
when "1101" | "1111" => tempAddress := "0000";
when others => tempAddress := "1000"; -- "1001" | "1100" | "1011" | "1110"
end case;
return tempAddress;
end FUNCTION GetAddressMask;
-- How much to 'increase' the line. For 848x480x8bpp, this is 1, all the way to
-- 424x240x1bpp, which will be increased by 64. That is also the effective speedup.
-- In widescreen mode, we get a max speedup of 16.
function getAdditionFactor
(
ADDR_MASK : in STD_LOGIC_VECTOR(3 downto 0)
) return integer is
variable OUTPUT: integer;
begin
-- Not enough pterms to do it will addition; use a LUT
-- OUTPUT := to_integer(unsigned(not ADDR_MASK)) + 1;
case ADDR_MASK is
when "0000" => OUTPUT := 16;
when "1000" => OUTPUT := 8;
when "1100" => OUTPUT := 4;
when "1110" => OUTPUT := 2;
when others => OUTPUT := 1;
end case;
return OUTPUT;
end getAdditionFactor;
begin
if (rising_edge(CLK)) then -- 60 MHz User Clock
-- This is our user logic clock now, not SPI anymore
-- Cyle back and forth between read/write, forever
CYCLE <= not CYCLE;
-------------------------------------------------------------------------------------
-- Framebuffer Write/Memory Management Code --
-------------------------------------------------------------------------------------
-- If the cache is full, we need to read it into our working register
if (CACHE_FULL_FLAG = '1' and SPI_CACHE_FULL_FLAG = '1') then
CACHE_FULL_FLAG <= '0';
WRITE_DATA <= SPI_DATA_CACHE;
-- The first digits will 'look like' 847, and the end will equal our shift.
-- 640 was very useful because it was divisible by 64. Since we only get 16 here
-- we can't do the same math hack as before.
if ( WRITE_COLUMN = "110100" & ADDR_MASK
or WRITE_COLUMN = "1111111111"
) then -- 848 pixels
if (WRITE_ROW(9) = '1') then WRITE_ROW <= "0000000000"; -- End of the line
else
case USER_RES is
when '0' => WRITE_ROW <= STD_LOGIC_VECTOR(unsigned(WRITE_ROW) + 1);
when others => WRITE_ROW <= STD_LOGIC_VECTOR(unsigned(WRITE_ROW) + 2);
end case;
end if;
WRITE_COLUMN <= "0000000000";
else
WRITE_COLUMN <= STD_LOGIC_VECTOR(unsigned(WRITE_COLUMN) + getAdditionFactor(ADDR_MASK));
end if;
-- ACK back to the SPI logic so it can reset the flag
ACK_SPI_BYTE <= '1';
WRITE_READY <= '1';
else
-- If the cache isn't full, keep checking the flag - but don't change
-- our currently active data
CACHE_FULL_FLAG <= SPI_CACHE_FULL_FLAG;
PIXEL(8 downto 1) <= PIXEL(8 downto 1); -- This doesn't change
ACK_SPI_BYTE <= '0';
end if; -- End Cache Full
if ( CACHE_RESET_FLAG = '1' and SPI_CMD_RESET_FLAG = '1') then
-- If the mode reset flag is full, we need to set the mode back to
-- whatever the initial state is
RESET_NEXT <= '1'; -- Reset next time you get a chance
CACHE_RESET_FLAG <= '0';
ACK_USER_RESET <= '1';
--WRITE_ROW <= (others => '1');
--WRITE_COLUMN <= (others => '1');
else
-- No reset flag up, so do whatever you want with the mode in your code
--if (SPI_CMD_RESET_FLAG = '1') then
CACHE_RESET_FLAG <= SPI_CMD_RESET_FLAG;
--end if;
end if; -- End Cache Full
-- Following this line is code which executes every other clock.
if (CYCLE = '1') then -- First clock, do display things
-- It helps to write this out on paper. This section took probably 15 hours to perfect.
-------------------------------------------------------------------------------------
-- Normal VGA Control Code - Syncs, Blanking Periods --
-------------------------------------------------------------------------------------
-- VBLANK
if (unsigned(VGA_ROW_COUNT) = 479) then
VBLANK <= '1';
elsif (unsigned(VGA_ROW_COUNT) = 0) then
VBLANK <= '0';
end if;
-- HBLANK
if (unsigned(VGA_PIXEL_COUNT) = 848) then
HBLANK <= '1';
elsif (unsigned(VGA_PIXEL_COUNT) = 0) then
HBLANK <= '0';
end if;
-- Carefully timed HSync
if (unsigned(VGA_PIXEL_COUNT) = 896) then
HSYNC <= '0';
elsif (unsigned(VGA_PIXEL_COUNT) = 944) then
HSYNC <= '1';
end if;
-- Carefully timed VSync - should be set for
if ( unsigned(VGA_ROW_COUNT) = 483 or unsigned(VGA_ROW_COUNT) = 484
or unsigned(VGA_ROW_COUNT) = 485 or unsigned(VGA_ROW_COUNT) = 486
or unsigned(VGA_ROW_COUNT) = 487
) then
VSYNC <= '1';
else
VSYNC <= '0';
end if;
-- Code for the end of a column and/or the end of a row.
if (VGA_PIXEL_COUNT = "01111110000") then -- 1008
VGA_PIXEL_COUNT <= "00000000000";
if (VGA_ROW_COUNT = "0111101110") then -- 494
-- Row 494, reset to 0,0
VGA_ROW_COUNT <= "0000000000";
else
VGA_ROW_COUNT <= STD_LOGIC_VECTOR(UNSIGNED(VGA_ROW_COUNT) + 1);
end if;
else
VGA_PIXEL_COUNT <= STD_LOGIC_VECTOR(UNSIGNED(VGA_PIXEL_COUNT) + 1);
end if;
-- Now the second part of our cycle. Since we are off the bus now, any writes that are queued up will happen here.
else -- CYCLE = '0'
if (ACK_USER_RESET = '1') then
-- Let's reset next time
RESET_NEXT <= '1';
end if;
if (RESET_NEXT = '1') then
-- Our resetting code - basically, set counters to all 1s (so +1 would be at 0,0)
RESET_NEXT <= '0';
WRITE_ROW <= (others => '1');
WRITE_COLUMN <= (others => '1');
ACK_USER_RESET <= '0';
-------------------------------------------------------------------------------------
-- VGATonic Control Code - Mode changes, HW Acceleration --
-------------------------------------------------------------------------------------
-- If we *only* wrote 1 pixel, that's a mode change or a 'move'
-- Easy to check - We would be at address '0' since we were reset here from all 1s.
if( ("0000000000" = WRITE_COLUMN and "0000000000" = WRITE_ROW) ) then
if (WRITE_DATA(7) = '1') then
-- Hardware acceleration! Just put 6 downto 0 bits into our write address.
-- Seriously, that's all we need.
WRITE_ROW <= '0' & -- 9
WRITE_DATA(6 downto 0) & -- 8, 7, 6, 5, 4, 3, 2
"00"; -- 1, 0
-- Only do one at a time - you can do one after another though, as long as you do
-- mode setting first.
else
-- Our 'Mode Change' Packets:
-- 6-4: Reserved (good luck fitting something!)
-- 3-2: User bitdepth (8, 4, 2, 1)
-- 1-0: User Resolution (6848x480, 424x240)
USER_BPP <= WRITE_DATA(3 downto 2);
-- In widescreen mode, there is no other resolution - just the two larger ones.
USER_RES <= WRITE_DATA(0);
ADDR_MASK <= GetAddressMask(WRITE_DATA);
end if;
end if;
end if;
if (WRITE_READY = '1') then
-- Reset our write so we don't write every cycle.
WRITE_READY <= '0';
end if;
-- Pixel, VSYNC, and HSYNC shouldn't change just because we're in the
-- writing portion - keep them constant.
-- PIXEL(8 downto 1) <= PIXEL(8 downto 1);
HSYNC <= HSYNC;
VSYNC <= VSYNC;
end if;
end if; -- End rising edge user logicclock
end process;
-- Framebuffer Core
end Behavioral; | mit | 750d8ff589fa36580f4f578cb5cd638d | 0.557053 | 3.385693 | false | false | false | false |
fgr1986/ddr_MIG_ctrl_interface | src/hdl/ram_ddr_MIG7_interface_pkg.vhd | 1 | 7,212 | ----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Author: Fernando García Redondo, [email protected]
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Create Date: 15:45:01 20/07/2017
-- Design Name: Nexys4 DDR UPM VHDL Lab Project
-- Module Name: top_upm_vhdl_lab - behavioral
-- Project Name: UPM VHDL Lab Project
-- Target Devices: Nexys4 DDR Development Board, containing a XC7a100t-1 csg324 device
-- Tool versions:
-- Description:
--
-- RAM-like interface between Xilinx MIG 7 generated core for ddr2 and ddr3 memories.
-- For simplicity, the DDR memory is working at 300Mhz (using a 200Mhz input clk),
-- and a PHY to Controller Clock Ratio of **4:1** with **BL8**.
-- **IMPORTANT** By doing so the ddr's **ui_clk** signal needs to be synchronized with the main 100Mhz clk.
-- We use a double reg approach together with handshake protocols (see Advanced FPGA design, Steve Kilts).
-- Double reg approach should be used between slower and faster domains.
--
-- The 200Mhz signal is generated using CLKGEN component (100Mhz output phase set at 0º to sync with 200MHz output).
--
-- From **ug586**:
-- *PHY to Controller Clock Ratio – This feature determines the ratio of the physical
-- layer (memory) clock frequency to the controller and user interface clock frequency.
-- The 2:1 ratio lowers the maximum memory interface frequency due to fabric timing
-- limitations. The user interface data bus width of the 2:1 ratio is 4 times the width of
-- the physical memory interface width, while the bus width of the 4:1 ratio is 8 times the
-- physical memory interface width. The 2:1 ratio has lower latency. The 4:1 ratio is
-- necessary for the highest data rates.*
-- Therefore:
--
-- clk – 0.25x memory clock in 4:1 mode and 0.5x the memory clock in 2:1 mode.
-- clk_ref – IDELAYCTRL reference clock, usually 200 MHz.
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
----------------------------------------------------------------------------------
-- Libraries
----------------------------------------------------------------------------------
library work;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package ram_ddr_MIG7_interface_pkg is
subtype t_DATA_WIDTH is positive range 16 to 128;
subtype t_APP_DATA_ADDRESS_WIDTH is positive range 16 to 27; -- rank in DDR2
-- MT47H64M16HR-25 is '0'
------------------------------------------------------------------------
-- Constant Declarations
------------------------------------------------------------------------
--------------------------------
-- System
--------------------------------
constant c_nCK_PER_CLK : positive := 4; -- 2 or 4
constant c_DDR_DATA_WIDTH : t_DATA_WIDTH := 16;
constant c_PAYLOAD_WIDTH : integer := c_DDR_DATA_WIDTH;
constant c_APP_DATA_WIDTH : t_DATA_WIDTH := 2*c_nCK_PER_CLK*c_PAYLOAD_WIDTH; -- 128 or 64
constant c_APP_DATA_ADDRESS_WIDTH : t_APP_DATA_ADDRESS_WIDTH := 27;
-- rank in DDR2 MT47H64M16HR-25 is '0'
constant c_DDR_ADDRESS_WIDTH : integer := 13;
constant c_DDR_DQ_WIDTH : integer := 16;
constant c_DDR_WDF_MASK_WIDTH : integer := c_APP_DATA_WIDTH/8; -- 16 or 8
constant c_DDR_BANK_WIDTH : integer := 3;
constant c_DDR_DM_WIDTH : integer := 2;
constant c_DDR_DQS_WIDTH : integer := 2;
constant c_DDR_CMD_WIDTH : integer := 3;
constant c_DATA_2_MEM_WIDTH : t_DATA_WIDTH := c_APP_DATA_WIDTH;
constant c_DATA_WIDTH : t_DATA_WIDTH := c_DDR_DATA_WIDTH;
-- rank in DDR2 MT47H64M16HR-25 is '0'
constant c_DATA_ADDRESS_WIDTH : t_APP_DATA_ADDRESS_WIDTH := c_APP_DATA_ADDRESS_WIDTH-1;
constant c_ADDR_INC : integer := c_APP_DATA_WIDTH/c_DDR_DATA_WIDTH;
-- how many words send at once to memory
constant c_WORDS_2_MEM : positive := (c_DATA_2_MEM_WIDTH/c_DATA_WIDTH);
-- data out of memory type
type t_DATA_OUT_MEM is array(c_WORDS_2_MEM-1 downto 0)
of std_logic_vector( c_DATA_WIDTH-1 downto 0);
constant c_SYS_CLK_FREQ_MHZ : positive := 100;
--------------------------------
-- DDR/RAM
--------------------------------
-- ddr commands
constant c_CMD_WRITE : std_logic_vector(2 downto 0) := "000";
constant c_CMD_READ : std_logic_vector(2 downto 0) := "001";
end ram_ddr_MIG7_interface_pkg;
package body ram_ddr_MIG7_interface_pkg is --start of package body
-- 2^c_DATA_ADDRESS_WIDTH * c_DDR_DATA_WIDTH = 1Gbps in Nexys4 DDR
-- ui address is c_APP_DATA_ADDRESS_WIDTH width->
-- Rank + bank + row + col, but as there is only one rank,
-- then ui_address's MSb = '0' (therefore c_DATA_ADDRESS_WIDTH)
-- Depending on the burst, we have c_WORDS_2_MEM
-- function lineal_to_ui_addr ( lineal : unsigned(c_DATA_ADDRESS_WIDTH-1 downto 0) ) return unsigned is
--
-- begin
-- return floor(lineal/c_ADDR_INC);
-- end lineal_to_ui_addr;
--
-- function lineal_to_ui_mask ( lineal : unsigned(c_DATA_ADDRESS_WIDTH-1 downto 0) ) return std_logic_vector is
-- --
-- -- constant c_MASK : std_logic_vector(c_DDR_WDF_MASK_WIDTH-1 downto 0)
-- -- := (c_DDR_WDF_MASK_WIDTH-1 downto c_MASK_DIFF => '1')
-- -- & (c_MASK_DIFF-1 downto 0 => '0');
-- variable mask : std_logic_vector(c_DDR_WDF_MASK_WIDTH-1 downto 0);
-- variable diff : integer:=0;
-- begin
-- diff = lineal - (c_APP_DATA_WIDTH/c_DDR_DATA_WIDTH)*floor(lineal/(c_APP_DATA_WIDTH/c_DDR_DATA_WIDTH));
-- return (c_DDR_WDF_MASK_WIDTH-1 downto c_MASK_DIFF => '0');
-- end lineal_to_ui_mask;
-- function to_bcd ( bin : unsigned(7 downto 0) ) return unsigned is
-- variable i : integer:=0;
-- variable bcd : unsigned(11 downto 0) := (others => '0');
-- variable bint : unsigned(7 downto 0) := bin;
-- begin
-- for i in 0 to 7 loop -- repeating 8 times.
-- bcd(11 downto 1) := bcd(10 downto 0); --shifting the bits.
-- bcd(0) := bint(7);
-- bint(7 downto 1) := bint(6 downto 0);
-- bint(0) :='0';
-- if(i < 7 and bcd(3 downto 0) > "0100") then --add 3 if BCD digit is greater than 4.
-- bcd(3 downto 0) := bcd(3 downto 0) + "0011";
-- end if;
-- if(i < 7 and bcd(7 downto 4) > "0100") then --add 3 if BCD digit is greater than 4.
-- bcd(7 downto 4) := bcd(7 downto 4) + "0011";
-- end if;
-- if(i < 7 and bcd(11 downto 8) > "0100") then --add 3 if BCD digit is greater than 4.
-- bcd(11 downto 8) := bcd(11 downto 8) + "0011";
-- end if;
-- end loop;
-- return bcd;
-- end to_bcd;
end ram_ddr_MIG7_interface_pkg;
| gpl-3.0 | 5d16afcc4ed8bdb8d811abc930a35870 | 0.544697 | 3.671764 | false | false | false | false |
dqydj/VGAtonic | Hardware_Rev_A/RCA:NTSC Demo Barebones/CPLD Firmware/Display_Controller.vhd | 1 | 16,443 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity Display_Controller is
Port (
-- User logic clock
CLK : in STD_LOGIC; -- 5x NTSC Colorburst Clock
-- NTSC Color clock = 5 color variations plus inverse gives us 10 shades
-- Then 16 levels of Luma, with the last few possibly too low to register
-- NTSC Signals
COLORBURST : inout std_logic := '0';
SYNC : inout std_logic := '1';
LUMA : inout STD_LOGIC_VECTOR(3 downto 0) := "0000";
-- Memory Interface:
ADDR : out STD_LOGIC_VECTOR(18 downto 0) := (others => '0');
DATA : inout STD_LOGIC_VECTOR(7 downto 0);
OE_LOW : out STD_LOGIC := '1';
WE_LOW : out STD_LOGIC := '1';
CE_LOW : out STD_LOGIC := '1';
-- For ease of oscilloscope testing you can put one of the color phases here
-- CPLD_GPIO : out STD_LOGIC := '0';
----------------------------------------------------------------------------------
-- VGAtonic Internal --
----------------------------------------------------------------------------------
-- Inputs from SPI
SPI_DATA_CACHE : in STD_LOGIC_VECTOR(7 downto 0);
SPI_CACHE_FULL_FLAG : in STD_LOGIC;
SPI_CMD_RESET_FLAG : in STD_LOGIC;
-- Acknowledges to SPI
ACK_USER_RESET : inout STD_LOGIC := '0';
ACK_SPI_BYTE : out STD_LOGIC := '0'
);
end Display_Controller;
architecture Behavioral of Display_Controller is
-- Next Write
signal WRITE_DATA : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
-- READ for our constant refresh out the RCA Jack - 63.5 ms line length x262 rows @ 60 FPS
-- We are abusing and shifting it to do 320x240, but pixels will be narrow (fix it with TV settings?)
signal NTSC_ROW_COUNT : STD_LOGIC_VECTOR(9 downto 0) := (others => '0');
signal NTSC_PIXEL_COUNT : STD_LOGIC_VECTOR(11 downto 0) := (others => '0');
signal WRITE_ROW : STD_LOGIC_VECTOR(9 downto 0) := (others => '1');
signal WRITE_COLUMN : STD_LOGIC_VECTOR(9 downto 0) := (others => '1');
-- Bring Async signals into our clock domain
signal CACHE_FULL_FLAG : STD_LOGIC := '0';
signal CACHE_RESET_FLAG : STD_LOGIC := '0';
-- Write or Read cycle?
signal CYCLE : STD_LOGIC := '0';
-- Do we need to write? Should we reset write address?
signal WRITE_READY : STD_LOGIC := '0';
signal RESET_NEXT : STD_LOGIC := '0';
-- ALWAYS IN 320x240 in 16 colors FOR THIS NTSC FIRMWARE!
signal PIXEL : STD_LOGIC_VECTOR(3 downto 0) := "0000";
-- Five counter one toggles on the rising edge of the clock while
-- Five counter two toggles on the falling edge. By oring the two
-- at different points we create all of our clock phases.
signal FIVE_COUNTER_ONE : STD_LOGIC_VECTOR(2 downto 0) := "001";
signal FIVE_COUNTER_TWO : STD_LOGIC_VECTOR(2 downto 0) := "001";
-- 5 phases of our color, and since it is odd we also get the inverse
-- Gives us a color every 36 degrees
signal PHASE_SHIFTER_ONE : STD_LOGIC := '0';
signal PHASE_SHIFTER_TWO : STD_LOGIC := '0';
signal PHASE_SHIFTER_THREE : STD_LOGIC := '0';
signal PHASE_SHIFTER_FOUR : STD_LOGIC := '0';
signal PHASE_SHIFTER_FIVE : STD_LOGIC := '0';
begin
-- Our Write/Read Logic
-- Be very careful here since this controls writing/reading from the memory!
-- Carelessness can lead to a short and you resoldering a new CPLD/SRAM
CE_LOW <= '0';
OE_LOW <= (not CYCLE);
WE_LOW <= CYCLE or CLK or (not WRITE_READY);
-- Should *only* output on the data bus if we're doing a write.
Write_Data_On_Bus: process (CLK, CYCLE, WRITE_READY, WRITE_DATA, WRITE_ROW)
begin
if ( (CYCLE or CLK) = '1' or WRITE_READY = '0') then
-- Normally be in High-Z mode, since the memory will be controlling the bus at this stage
DATA <= "ZZZZZZZZ";
else
-- Only when in the right clock cycle and we have a write ready
DATA <= WRITE_DATA;
end if;
-- As for address - we flip it every cycle (2 master clocks)
if (CYCLE = '0' and WRITE_READY = '1') then
-- We're about to write
ADDR <= WRITE_ROW(8 downto 0) & WRITE_COLUMN;
else
-- We're doing normal bus reads. 160 addresses for 320 columns.
-- Since this count happens 2x our user clock, mask the last bit.
-- Since it is 4 bit not 8 bit, mask the penultimate bit.
ADDR <= NTSC_ROW_COUNT(8 downto 0) & NTSC_PIXEL_COUNT(9 downto 2) & "00";
end if;
end process;
-- Use ors to make 5 sweet phases of colors. One of them (we picked 'one')
-- is your colorburst, everything else is in reference to it
Phase_Shifter: process (FIVE_COUNTER_TWO, FIVE_COUNTER_ONE)
begin
-- 4 or 5
if ( FIVE_COUNTER_TWO = "100" or FIVE_COUNTER_TWO = "101" or
FIVE_COUNTER_ONE = "100" or FIVE_COUNTER_ONE = "101" ) then
PHASE_SHIFTER_ONE <= '1';
else
PHASE_SHIFTER_ONE <= '0';
end if;
-- 3 or 4
if ( FIVE_COUNTER_TWO = "100" or FIVE_COUNTER_TWO = "011" or
FIVE_COUNTER_ONE = "100" or FIVE_COUNTER_ONE = "011" ) then
PHASE_SHIFTER_TWO <= '1';
else
PHASE_SHIFTER_TWO <= '0';
end if;
-- 2 or 3
if ( FIVE_COUNTER_TWO = "010" or FIVE_COUNTER_TWO = "011" or
FIVE_COUNTER_ONE = "010" or FIVE_COUNTER_ONE = "011" ) then
PHASE_SHIFTER_THREE <= '1';
else
PHASE_SHIFTER_THREE <= '0';
end if;
-- 1 or 2
if ( FIVE_COUNTER_TWO = "010" or FIVE_COUNTER_TWO = "001" or
FIVE_COUNTER_ONE = "010" or FIVE_COUNTER_ONE = "001" ) then
PHASE_SHIFTER_FOUR <= '1';
else
PHASE_SHIFTER_FOUR <= '0';
end if;
-- 1 or 5
if ( FIVE_COUNTER_TWO = "101" or FIVE_COUNTER_TWO = "001" or
FIVE_COUNTER_ONE = "101" or FIVE_COUNTER_ONE = "001" ) then
PHASE_SHIFTER_FIVE <= '1';
else
PHASE_SHIFTER_FIVE <= '0';
end if;
end process;
-- There is no hardware accelerated resolutions and colors in this NTSC example.
-- Youget 320x240 at 4 bit (16 colors) fixed. Palette is RGBI.
Display_Logic: process (CLK, ACK_USER_RESET)
begin
if (falling_edge(CLK)) then
if (FIVE_COUNTER_TWO = "101") then
FIVE_COUNTER_TWO <= "001";
else
FIVE_COUNTER_TWO <= STD_LOGIC_VECTOR(unsigned(FIVE_COUNTER_TWO) + 1);
end if;
end if;
if (rising_edge(CLK)) then -- 60 and change MHz
-- This is our user logic clock now, not SPI anymore
if (FIVE_COUNTER_ONE = "101") then
FIVE_COUNTER_ONE <= "001";
else
FIVE_COUNTER_ONE <= STD_LOGIC_VECTOR(unsigned(FIVE_COUNTER_ONE) + 1);
end if;
if ( ( to_integer(unsigned(NTSC_ROW_COUNT)) = 243 ) or
( to_integer(unsigned(NTSC_ROW_COUNT)) = 244 ) or
( to_integer(unsigned(NTSC_ROW_COUNT)) = 245 ) ) then
if (to_integer(unsigned(NTSC_PIXEL_COUNT)) = 1137) then
NTSC_PIXEL_COUNT <= "000000000000";
-- Add another line to row counter
NTSC_ROW_COUNT <= STD_LOGIC_VECTOR(unsigned(NTSC_ROW_COUNT) + 1);
-- Kick off our line
SYNC <= '0';
COLORBURST <= '0';
LUMA <= "0000";
else
NTSC_PIXEL_COUNT <= STD_LOGIC_VECTOR(unsigned(NTSC_PIXEL_COUNT) + 1);
COLORBURST <= '0';
end if;
-- Sync is reversed on a VSYNC line
-- Sync 817 to 901
if ( to_integer(unsigned(NTSC_PIXEL_COUNT)) = 817) then
SYNC <= '1';
end if;
if ( to_integer(unsigned(NTSC_PIXEL_COUNT)) = 901) then
SYNC <= '0';
end if;
else -- Normal, non-VSync lines with a normal reverse sync
if (to_integer(unsigned(NTSC_PIXEL_COUNT)) = 1137) then
NTSC_PIXEL_COUNT <= "000000000000";
if (to_integer(unsigned(NTSC_ROW_COUNT)) = 261) then
NTSC_ROW_COUNT <= "0000000000";
else
-- Add another line to row counter
NTSC_ROW_COUNT <= STD_LOGIC_VECTOR(unsigned(NTSC_ROW_COUNT) + 1);
end if;
-- Kick off our line
SYNC <= '1';
else
NTSC_PIXEL_COUNT <= STD_LOGIC_VECTOR(unsigned(NTSC_PIXEL_COUNT) + 1);
end if;
-- Sync 817 - 901
if ( to_integer(unsigned(NTSC_PIXEL_COUNT)) = 817) then
SYNC <= '0';
end if;
if ( to_integer(unsigned(NTSC_PIXEL_COUNT)) = 901) then
SYNC <= '1';
end if;
-- Color burst - 912 to 957
if ( to_integer(unsigned(NTSC_PIXEL_COUNT)) >= 912 and to_integer(unsigned(NTSC_PIXEL_COUNT)) < 957) then
-- Do not burst in the lines right after our active video! This is our reverse sync area.
if (to_integer(unsigned(NTSC_ROW_COUNT)) < 240 or to_integer(unsigned(NTSC_ROW_COUNT)) > 249) then
COLORBURST <= PHASE_SHIFTER_ONE;
else
COLORBURST <= '0';
end if;
end if;
-- Colorburst may have left itself in the high position so change this.
if (to_integer(unsigned(NTSC_PIXEL_COUNT)) = 957) then
COLORBURST <= '0';
end if;
-- After active video fade to black
if (to_integer(unsigned(NTSC_PIXEL_COUNT)) > 640) then
LUMA <= "0000";
end if;
-- Start counting in the active video area
if ( to_integer(unsigned(NTSC_ROW_COUNT)) < 240) then
-- Stop counting after 640 ticks to make our math easier (just mask off
-- bits we do not use)
if ( to_integer(unsigned(NTSC_PIXEL_COUNT)) < 640) then
-- Following is a lookup table for converting our RGB 4 bit pixels to
-- the luminance-chrominance color wheel used by NTSC
-- NTSC uses the YIQ color plane, and moving to 8 bits probably needs to do a conversion
-- Check Wikipedia for the matrix math if you decide to upgrade to 6/8 bit color.
-- 16 colors is easy enough to do by looking at a color wheel (especially with 4 shades of non-color)
CASE ( PIXEL ) IS
WHEN "0000" => COLORBURST <= '0'; LUMA <= "0000";
WHEN "0001" => COLORBURST <= '0'; LUMA <= "0011";
WHEN "0010" => COLORBURST <= not PHASE_SHIFTER_ONE; LUMA <= "0010";
WHEN "0011" => COLORBURST <= not PHASE_SHIFTER_ONE; LUMA <= "1001";
WHEN "0100" => COLORBURST <= PHASE_SHIFTER_TWO; LUMA <= "0010";
WHEN "0101" => COLORBURST <= PHASE_SHIFTER_TWO; LUMA <= "1000";
WHEN "0110" => COLORBURST <= not PHASE_SHIFTER_FIVE; LUMA <= "0011";
WHEN "0111" => COLORBURST <= not PHASE_SHIFTER_FIVE; LUMA <= "1100";
WHEN "1000" => COLORBURST <= PHASE_SHIFTER_FIVE; LUMA <= "0010";
WHEN "1001" => COLORBURST <= PHASE_SHIFTER_FIVE; LUMA <= "1010";
WHEN "1010" => COLORBURST <= PHASE_SHIFTER_FOUR; LUMA <= "0011";
WHEN "1011" => COLORBURST <= PHASE_SHIFTER_FOUR; LUMA <= "1010";
WHEN "1100" => COLORBURST <= PHASE_SHIFTER_ONE; LUMA <= "0010";
WHEN "1101" => COLORBURST <= PHASE_SHIFTER_ONE; LUMA <= "1100";
WHEN "1110" => COLORBURST <= '0'; LUMA <= "0101";
WHEN OTHERS => COLORBURST <= '0'; LUMA <= "1111";
END CASE;
end if;
end if; -- End of row counter above 19
end if; -- end our 'if not lines 1-9
-- Cyle back and forth between read/write, forever
CYCLE <= not CYCLE;
-------------------------------------------------------------------------------------
-- Framebuffer Write/Memory Management Code --
-------------------------------------------------------------------------------------
-- If the cache is full, we need to read it into our working register
if (CACHE_FULL_FLAG = '1' and SPI_CACHE_FULL_FLAG = '1') then
CACHE_FULL_FLAG <= '0';
WRITE_DATA <= SPI_DATA_CACHE;
-- The first digits will 'look like' 319, and the end will equal our shift.
if ( WRITE_COLUMN = "1001111100"
or WRITE_COLUMN = "1111111111"
) then -- 640 pixels
if (WRITE_ROW(9) = '1') then WRITE_ROW <= "0000000000"; -- End of the line
else
-- Since we are faking progressive scan, all we do is increase rows by one.
-- We count to 240 then hopefully the driver stops and resets
WRITE_ROW <= STD_LOGIC_VECTOR(unsigned(WRITE_ROW) + 1);
end if;
WRITE_COLUMN <= "0000000000";
else
-- 640 pixels wide, but we only want 320 (1 << 1)
-- 320 pixels wide by 4 bit color not 8 bit (10 << 1)
-- That's a total of 001 shiftleft 2, or 100 (4)
WRITE_COLUMN <= STD_LOGIC_VECTOR(unsigned(WRITE_COLUMN) + 4);
end if;
-- ACK back to the SPI logic so it can reset the flag
ACK_SPI_BYTE <= '1';
WRITE_READY <= '1';
else
-- If the cache isn't full, keep checking the flag - but don't change
-- our currently active data
CACHE_FULL_FLAG <= SPI_CACHE_FULL_FLAG;
ACK_SPI_BYTE <= '0';
end if; -- End Cache Full
if ( CACHE_RESET_FLAG = '1' and SPI_CMD_RESET_FLAG = '1') then
-- If the mode reset flag is full, we need to set the mode back to
-- whatever the initial state is
RESET_NEXT <= '1'; -- Reset next time you get a chance
CACHE_RESET_FLAG <= '0';
ACK_USER_RESET <= '1';
else
-- No reset flag up, so do whatever you want with the mode in your code
--if (SPI_CMD_RESET_FLAG = '1') then
CACHE_RESET_FLAG <= SPI_CMD_RESET_FLAG;
--end if;
end if; -- End Cache Full
-- Following this line is code which executes every other clock.
-------------------------------------------------------------------------------------
-- Framebuffer Pixel Code --
-------------------------------------------------------------------------------------
if (CYCLE = '1') then -- First clock, do display things
if (NTSC_PIXEL_COUNT(2) = '0') then
PIXEL <= DATA( 7 downto 4 );
else
PIXEL <= DATA( 3 downto 0 );
end if;
-- Now the second part of our cycle. Since we are off the bus now, any writes that are queued up will happen here.
else -- CYCLE = '0'
if (ACK_USER_RESET = '1') then
-- Let's reset next time
RESET_NEXT <= '1';
end if;
if (RESET_NEXT = '1') then
-- Our resetting code - basically, set counters to all 1s (so +1 would be at 0,0)
RESET_NEXT <= '0';
WRITE_ROW <= (others => '1');
WRITE_COLUMN <= (others => '1');
ACK_USER_RESET <= '0';
-------------------------------------------------------------------------------------
-- VGATonic Control Code - Mode changes, HW Acceleration --
-------------------------------------------------------------------------------------
-- If we *only* wrote 1 pixel, that's a mode change or a 'move'
-- Easy to check - We would be at address '0' since we were reset here from all 1s.
if( ("0000000000" = WRITE_COLUMN and "0000000000" = WRITE_ROW) ) then
if (WRITE_DATA(7) = '1') then
-- Hardware acceleration! Just put 6 downto 0 bits into our write address.
-- Seriously, that's all we need.
WRITE_ROW <= '0' & -- 9
WRITE_DATA(6 downto 0) & -- 8, 7, 6, 5, 4, 3, 2
"00"; -- 1, 0
-- Only do one at a time - you can do one after another though, as long as you do
-- mode setting first.
else
-- Nothing now for NTSC, this is where we change modes in the *VGA* VGATonic firmware.
-- You could certainly add mode changing here. 160x120, 80x60 and 2 and 1 bit color are
-- somewhat simple, but as discussed in the comments 256 color/8 bit would require work/decoding
-- and 640x480 is only possible with interlacing (and maximum 30 FPS... well, 29.97 anyway)
end if;
end if;
end if;
if (WRITE_READY = '1') then
-- Reset our write so we don't write every cycle.
WRITE_READY <= '0';
end if;
-- In this mode, keep Sync and Luma the same
SYNC <= SYNC;
LUMA(3 downto 0) <= LUMA(3 downto 0);
end if;
end if; -- End rising edge user logicclock
end process;
-- Framebuffer Core
end Behavioral; | mit | 186b9f714ac1f9f2bed187afc35bd6b2 | 0.554461 | 3.425625 | false | false | false | false |
dqydj/VGAtonic | Hardware_Rev_B/Widescreen Version Firmware/CPLD Firmware Widescreen/VGAtonic_Firmware.vhd | 1 | 3,958 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- In/out for top level module
entity VGAtonic_Firmware is
PORT(
CLK : in STD_LOGIC;
-- SPI Select (Master is AVR)
AVR_CPLD_EXT_1 : in STD_LOGIC;
-- SPI Pins from Outside World
EXT_SCK : in STD_LOGIC;
EXT_MOSI : in STD_LOGIC;
EXT_MISO : out STD_LOGIC := '0';
EXT_SEL_CPLD : in STD_LOGIC; -- Active low
-- SPI Pins from AVR
AVR_SCK : in STD_LOGIC;
-- Using this as our SEL pin due to timer issues
AVR_CPLD_EXT_2 : in STD_LOGIC;
AVR_MOSI : in STD_LOGIC;
-- AVR_MISO : out STD_LOGIC := 'Z';
-- VGA
PIXEL : inout STD_LOGIC_VECTOR(8 downto 0);
HSYNC : inout STD_LOGIC;
VSYNC : inout STD_LOGIC;
--CPLD_GPIO : out STD_LOGIC_VECTOR(16 downto 16) := "0";
-- Memory
DATA : inout STD_LOGIC_VECTOR(7 downto 0);
ADDR : out STD_LOGIC_VECTOR(18 downto 0);
OE_LOW : inout STD_LOGIC := '1';
WE_LOW : out STD_LOGIC := '1';
CE_LOW : out STD_LOGIC := '1'
);
end VGAtonic_Firmware;
architecture Behavioral of VGAtonic_Firmware is
-- Handshaking signals from SPI
signal SPI_DATA_CACHE : STD_LOGIC_VECTOR(7 downto 0);
signal SPI_CACHE_FULL_FLAG : STD_LOGIC;
signal SPI_CMD_RESET_FLAG : STD_LOGIC;
-- Handshaking signals to SPI
signal ACK_USER_RESET : STD_LOGIC;
signal ACK_SPI_BYTE : STD_LOGIC;
-- Instantiating our SPI slave code (see earlier entries)
COMPONENT SPI_Slave
PORT(
SEL_SPI : in STD_LOGIC;
-- SPI Pins from World
EXT_SCK : in STD_LOGIC;
EXT_SEL : in STD_LOGIC;
EXT_MOSI : in STD_LOGIC;
EXT_MISO : out STD_LOGIC;
-- SPI Pins from AVR
AVR_SCK : in STD_LOGIC;
AVR_SEL : in STD_LOGIC;
AVR_MOSI : in STD_LOGIC;
-- AVR_MISO : out STD_LOGIC;
ACK_USER_RESET : IN std_logic;
ACK_SPI_BYTE : IN std_logic;
SPI_DATA_CACHE : OUT std_logic_vector(7 downto 0);
SPI_CACHE_FULL_FLAG : OUT std_logic;
SPI_CMD_RESET_FLAG : OUT std_logic
);
END COMPONENT;
-- Instantiating our Display Controller code
-- Just VGA for now
COMPONENT Display_Controller
PORT(
CLK : IN std_logic;
SPI_DATA_CACHE : IN std_logic_vector(7 downto 0);
SPI_CACHE_FULL_FLAG : IN std_logic;
SPI_CMD_RESET_FLAG : IN std_logic;
PIXEL : INOUT std_logic_vector(8 downto 0);
HSYNC : INOUT std_logic;
VSYNC : INOUT std_logic;
--CPLD_GPIO : OUT std_logic_vector(16 to 16);
ACK_USER_RESET : INOUT std_logic;
ACK_SPI_BYTE : OUT std_logic;
ADDR : OUT std_logic_vector(18 downto 0);
DATA : INOUT std_logic_vector(7 downto 0);
OE_LOW : inout STD_LOGIC := '1';
WE_LOW : out STD_LOGIC := '1';
CE_LOW : out STD_LOGIC := '1'
);
END COMPONENT;
begin
-- Nothing special here; we don't even really change the names of the signals.
-- Here we map all of the internal and external signals to the respective
-- modules for SPI input and VGA output.
Inst_SPI_Slave: SPI_Slave PORT MAP(
SEL_SPI => AVR_CPLD_EXT_1,
EXT_SCK => EXT_SCK,
EXT_SEL => EXT_SEL_CPLD,
EXT_MOSI => EXT_MOSI,
EXT_MISO => EXT_MISO,
AVR_SCK => AVR_SCK,
AVR_SEL => AVR_CPLD_EXT_2,
AVR_MOSI => AVR_MOSI,
-- AVR_MISO => AVR_MISO,
SPI_DATA_CACHE => SPI_DATA_CACHE,
SPI_CACHE_FULL_FLAG => SPI_CACHE_FULL_FLAG,
SPI_CMD_RESET_FLAG => SPI_CMD_RESET_FLAG,
ACK_USER_RESET => ACK_USER_RESET,
ACK_SPI_BYTE => ACK_SPI_BYTE
);
Inst_Display_Controller: Display_Controller PORT MAP(
CLK => CLK,
PIXEL => PIXEL,
HSYNC => HSYNC,
VSYNC => VSYNC,
--CPLD_GPIO => CPLD_GPIO,
SPI_DATA_CACHE => SPI_DATA_CACHE,
SPI_CACHE_FULL_FLAG => SPI_CACHE_FULL_FLAG,
SPI_CMD_RESET_FLAG => SPI_CMD_RESET_FLAG,
ACK_USER_RESET => ACK_USER_RESET,
ACK_SPI_BYTE => ACK_SPI_BYTE,
DATA => DATA,
ADDR => ADDR,
OE_LOW => OE_LOW,
WE_LOW => WE_LOW,
CE_LOW => CE_LOW
);
end Behavioral;
| mit | 22e8e4e74b0f270b9c96e8aae2b9a9af | 0.615462 | 2.783404 | false | false | false | false |
s-kostyuk/course_project_csch | final_processor/operational_unit.vhd | 1 | 3,481 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_signed.all;
use IEEE.STD_logic_arith.all;
entity operational_unit is
generic(
N: integer := 4;
M: integer := 8
);
port(
clk,rst : in STD_LOGIC;
y : in STD_LOGIC_VECTOR(25 downto 1);
d1 : in STD_LOGIC_VECTOR(2*N-1 downto 0);
d2 : in STD_LOGIC_VECTOR(N-1 downto 0);
rl, rh : out STD_LOGIC_VECTOR(N-1 downto 0);
x : out STD_LOGIC_vector(10 downto 1);
IRQ1, IRQ2 : out std_logic
);
end operational_unit;
architecture operational_unit of operational_unit is
signal A,Ain: STD_LOGIC_VECTOR(2*N-1 downto 0) ;
signal B1,B1in: STD_LOGIC_VECTOR(N-1 downto 0) ;
signal B2,B2in: STD_LOGIC_VECTOR(N downto 0) ;
signal CnT, CnTin: std_logic_vector(M-1 downto 0);
signal C, Cin: STD_LOGIC_VECTOR(N-1 downto 0) ;
signal overflow, carry: std_logic;
signal of_in, cf_in: std_logic;
signal of_sum, cf_sum: std_logic;
signal TgS, TgSin: std_logic;
signal sum_result: std_logic_vector(N-1 downto 0);
component adder is
generic(
N: integer := 4
);
port(A, B: in std_logic_vector(N-1 downto 0);
Cin: in std_logic;
S: out std_logic_vector(N-1 downto 0);
Cout: out std_logic;
overflow: out std_logic);
end component;
begin
process(clk,rst)is
begin
if rst='0' then
A <= (others=>'0');
B1 <= (others=>'0');
B2 <= (others=>'0');
TgS <= '0';
Overflow <= '0';
Carry <= '0';
CnT <= (others=>'0');
elsif rising_edge(clk)then
A <= Ain;
B1 <= B1in;
B2 <= B2in;
TgS <= TgSin;
CnT <= CnTin;
C <= Cin;
Overflow <= of_in;
Carry <= cf_in;
end if;
end process;
-- Ïîäêëþ÷åíèå ñóììàòîðà
SUM : adder port map(A => C, B => A(N-1 downto 0), Cin => '0', Cout => cf_sum, overflow => of_sum, S => sum_result);
-- Ðåàëèçàöèÿ ìèêðîîïåðàöèé
Ain <= D1 when y(1)='1'
else (A(2*N-1 downto N-1) + not B2 + 1) & A(N-2 downto 0) when y(17) = '1'
else (A(2*N-1 downto N-1) + B2) & A(N-2 downto 0) when y(18) = '1'
else A(2*N-2 downto 0) & '0' when y(21) = '1'
else A;
B1in <= D2 when y(2) = '1'
else C(0) & B1(N-1 downto 1) when y(7) = '1'
else B1;
Cin <= (others => '0') when y(3) = '1'
else sum_result when y(5) = '1'
else carry & C(N-1 downto 1) when y(9) = '1'
else C(N-1)& C(N-1 downto 1) when y(10) = '1'
else C + not A(N-1 downto 0) + 1 when y(11) = '1'
else C(N-2 downto 0) & '1' when y(19) = '1'
else C(N-2 downto 0) & '0' when y(20) = '1'
else C + 1 when y(22) = '1'
else C;
cf_in <= cf_sum when y(5) = '1'
else carry;
of_in <= of_sum when y(5) = '1'
else overflow;
CnTin <= conv_std_logic_vector(N, M) when y(4) = '1'
else CnT - 1 when y(8) = '1'
else CnT;
TgSin <= B1(0) when y(6) = '1'
else A(2*N-1) when y(15) = '1'
else TgS;
RL <= B1 when y(12) = '1'
else C when y(23) = '1'
else (others => 'Z');
RH <= C when y(13) = '1'
else (others => 'Z');
B2in <= D2 & '0' when y(14) = '1'
else B2(N) & B2(N downto 1) when y(16) = '1'
else B2;
IRQ1 <= '1' when y(24) = '1'
else '0';
IRQ2 <= '1' when y(25) = '1'
else '0';
-- Îñâåäîìèòåëüíûå ñèãíàëû
x(1) <= B1(0);
x(2) <= overflow;
x(3) <= '1' when CnT = 0 else '0';
x(4) <= TgS;
x(5) <= '1' when B2 = 0 else '0';
x(6) <= A(2*N-1) xor B2(N);
x(7) <= A(2*N-1) xor TgS;
x(8) <= B2(N);
x(9) <= B2(N) xor TgS;
x(10) <= '1' when A = 0 else '0';
end operational_unit; | mit | 7185539ff12cf4985740d443cd08d68f | 0.541511 | 2.224281 | false | false | false | false |
Kalycito-open-automation/openPOWERLINK_V2_old_25-06-2014 | hardware/ipcore/common/lib/src/registerFileRtl.vhd | 2 | 5,353 | -------------------------------------------------------------------------------
--! @file registerFileRtl.vhd
--
--! @brief Register table file implementation
--
--! @details This implementation is a simple dual ported memory implemented in
--! using register resources.
-------------------------------------------------------------------------------
--
-- (c) B&R, 2012
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.global.all;
entity registerFile is
generic (
gRegCount : natural := 8
);
port (
iClk : in std_logic;
iRst : in std_logic;
iWriteA : in std_logic;
iWriteB : in std_logic;
iByteenableA: in std_logic_vector;
iByteenableB: in std_logic_vector;
iAddrA : in std_logic_vector(LogDualis(gRegCount)-1 downto 0);
iAddrB : in std_logic_vector(LogDualis(gRegCount)-1 downto 0);
iWritedataA : in std_logic_vector;
oReaddataA : out std_logic_vector;
iWritedataB : in std_logic_vector;
oReaddataB : out std_logic_vector
);
end registerFile;
architecture Rtl of registerFile is
constant cByte : natural := 8;
type tRegSet is
array (natural range <>) of std_logic_vector(iWritedataA'range);
signal regFile, regFile_next : tRegSet(gRegCount-1 downto 0);
begin
--register set
reg : process(iClk)
begin
if rising_edge(iClk) then
if iRst = cActivated then
--clear register file
regFile <= (others => (others => '0'));
else
regFile <= regFile_next;
end if;
end if;
end process;
--write data into Register File with respect to address
--note: a overrules b
regFileWrite : process(
iWriteA, iWriteB, iAddrA, iAddrB,
iByteenableA, iByteenableB,
iWritedataA, iWritedataB, regFile)
variable vWritedata : std_logic_vector(iWritedataA'range);
begin
--default
regFile_next <= regFile;
vWritedata := (others => cInactivated);
if iWriteB = cActivated then
--read out register content first
vWritedata := regFile(to_integer(unsigned(iAddrB)));
--then consider byteenable
for i in iWritedataB'range loop
if iByteenableB(i/cByte) = cActivated then
--if byte is enabled assign it
vWritedata(i) := iWritedataB(i);
end if;
end loop;
--write to address the masked writedata
regFile_next(to_integer(unsigned(iAddrB))) <= vWritedata;
end if;
if iWriteA = cActivated then
--read out register content first
vWritedata := regFile(to_integer(unsigned(iAddrA)));
--then consider byteenable
for i in iWritedataA'range loop
if iByteenableA(i/cByte) = cActivated then
--if byte is enabled assign it
vWritedata(i) := iWritedataA(i);
end if;
end loop;
--write to address the masked writedata
regFile_next(to_integer(unsigned(iAddrA))) <= vWritedata;
end if;
end process;
--read data from Register File with respect to iAddrRead
regFileRead : process(iAddrA, iAddrB, regFile)
begin
--read from address
oReaddataA <= regFile(to_integer(unsigned(iAddrA)));
oReaddataB <= regFile(to_integer(unsigned(iAddrB)));
end process;
end Rtl;
| gpl-2.0 | 9d2d52aa00da68d616f5308e2297434c | 0.600785 | 4.666957 | false | false | false | false |
ShepardSiegel/ocpi | libsrc/hdl/vhd/ocpi_types_body.vhd | 1 | 6,255 | -- Various re-usable functions relating to property data type support.
--library ocpi;
--use ocpi.wci.all;
library ieee;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
package body types is
-- THESE ARE DEFINITIONS WHEN Bool_t is std_logic
function its(b : bool_t) return boolean is begin return b = '1'; end;
function To_bool(b : std_logic) return Bool_t is begin return b; end to_bool;
function To_bool(b : std_logic_vector) return Bool_t is begin return b(0); end to_bool;
function To_bool(b : boolean) return Bool_t is begin if b then return '1'; else return '0'; end if; end;
function from_bool(b : bool_t) return std_logic_vector is begin
if b = '1' then return std_logic_vector'(b"1"); else return std_logic_vector'(b"0"); end if;
end from_bool;
function "and" ( l : bool_t; r : bool_t ) return boolean is begin return its(l) and its(r); end;
function "nand" ( l : bool_t; r : bool_t ) return boolean is begin return its(l) nand its(r); end;
function "or" ( l : bool_t; r : bool_t ) return boolean is begin return its(l) or its(r); end;
function "nor" ( l : bool_t; r : bool_t ) return boolean is begin return its(l) nor its(r); end;
function "xor" ( l : bool_t; r : bool_t ) return boolean is begin return its(l) xor its(r); end;
function "xnor" ( l : bool_t; r : bool_t ) return boolean is begin return its(l) xnor its(r); end;
--function "and" ( l : bool_t; r : boolean ) return boolean is begin return its(l) and r; end;
function "nand" ( l : bool_t; r : boolean ) return boolean is begin return its(l) nand r; end;
function "or" ( l : bool_t; r : boolean ) return boolean is begin return its(l) or r; end;
function "nor" ( l : bool_t; r : boolean ) return boolean is begin return its(l) nor r; end;
function "xor" ( l : bool_t; r : boolean ) return boolean is begin return its(l) xor r; end;
function "xnor" ( l : bool_t; r : boolean ) return boolean is begin return its(l) xnor r; end;
function "and" ( l : boolean; r : bool_t ) return boolean is begin return l and its(r); end;
function "nand" ( l : boolean; r : bool_t ) return boolean is begin return l nand its(r); end;
function "or" ( l : boolean; r : bool_t ) return boolean is begin return l or its(r); end;
function "nor" ( l : boolean; r : bool_t ) return boolean is begin return l nor its(r); end;
function "xor" ( l : boolean; r : bool_t ) return boolean is begin return l xor its(r); end;
function "xnor" ( l : boolean; r : bool_t ) return boolean is begin return l xnor its(r); end;
function "or" ( l : bool_t; r : boolean ) return bool_t is begin return to_bool(to_boolean(l) or r); end;
function "not" ( l : bool_t ) return boolean is begin return not its(l); end;
-- THESE ARE DEFINITIONS WHEN Bool_t is BOOLEAN
--function its(b : bool_t) return boolean is begin return b; end;
--function To_bool(b : std_logic) return Bool_t is begin return b = '1'; end to_bool;
--function To_bool(b : std_logic_vector) return Bool_t is begin return b(0) = '1'; end to_bool;
--function To_bool(b : boolean) return Bool_t is begin return b; end;
--function from_bool(b : bool_t) return std_logic_vector is begin
-- if b then return std_logic_vector'(b"1"); else return std_logic_vector'(b"0"); end if;
--end from_bool;
--function from_bool(b : bool_t) return std_logic is begin
--if b then return '1'; else return '0'; end if;
--end from_bool;
-- THESE ARE Bool_t related definitions independent of whether bool_t is boolean or std_logic
function btrue return bool_t is begin return to_bool(true); end;
function bfalse return bool_t is begin return to_bool(false); end;
function To_boolean(b : bool_t) return boolean is begin return its(b); end to_boolean;
function from_bool_array(ba : bool_array_t; index, nbytes_1, byte_offset : unsigned) return word_t is
variable result: word_t := (others => '0');
variable i : natural := to_integer(index);
variable o : natural := to_integer(byte_offset) * 8;
begin
result(o + 0) := from_bool(ba(i))(0);
if nbytes_1 > 0 then
result(o + 8) := from_bool(ba(i+1))(0);
if nbytes_1 > 1 then
result(o + 16) := from_bool(ba(i+2))(0);
if nbytes_1 = 3 then
result(o + 24) := from_bool(ba(i+3))(0);
end if;
end if;
end if;
return result;
end from_bool_array;
function To_character (c : Char_t) return character is
begin
return character'val(to_integer(c));
end to_character;
function To_char (c: Character) return char_t is
begin
return to_signed(character'pos(c),char_t'length);
end to_char;
function To_char (c: integer) return char_t is
begin
return to_signed(c,char_t'length);
end to_char;
function from_char (c: char_t) return std_logic_vector is begin
return std_logic_vector(c);
end from_char;
function To_short (c: integer) return short_t is
begin
return to_signed(c,short_t'length);
end to_short;
function To_long (c: integer) return long_t is
begin
return to_signed(c,long_t'length);
end to_long;
function To_uchar (c: natural) return uchar_t is
begin
return to_unsigned(c,uchar_t'length);
end to_uchar;
function To_ushort (c: natural) return ushort_t is
begin
return to_unsigned(c,ushort_t'length);
end to_ushort;
function To_ulong (c: natural) return ulong_t is
begin
return to_unsigned(c,ulong_t'length);
end to_ulong;
--function To_char (c: std_logic_vector) return char_t is
--begin
--return char_t(c(7 downto 0));
--end to_char;
function to_string(inword : word_t) return wordstring_t is
begin
return
(signed(inword( 7 downto 0)),
signed(inword(15 downto 8)),
signed(inword(23 downto 16)),
signed(inword(31 downto 24)));
end to_string;
function from_string(s : string_t; offset : unsigned) return word_t is
variable off : natural;
begin
off := to_integer(offset);
return
std_logic_vector(s(off)) &
std_logic_vector(s(off+1)) &
std_logic_vector(s(off+2)) &
std_logic_vector(s(off+3));
end from_string;
end types;
| lgpl-3.0 | 9d32315f7f9fbedcd20903be951104fa | 0.641087 | 3.029056 | false | false | false | false |
hoglet67/AtomGodilVideo | src/DCM/DCM1.vhd | 1 | 2,120 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity DCM1 is
port (CLKIN_IN : in std_logic;
RST : in std_logic := '0';
CLK0_OUT : out std_logic;
CLK0_OUT1 : out std_logic;
CLK2X_OUT : out std_logic;
LOCKED : out std_logic
);
end DCM1;
architecture BEHAVIORAL of DCM1 is
signal CLKFX_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKFX_BUFG_INST : BUFG
port map (I => CLKFX_BUF, O => CLK0_OUT);
DCM_INST : DCM
generic map(CLK_FEEDBACK => "NONE",
CLKDV_DIVIDE => 4.0,
CLKFX_MULTIPLY => 31,
CLKFX_DIVIDE => 26,
CLKIN_DIVIDE_BY_2 => false,
CLKIN_PERIOD => 20.344,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => true,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => false)
port map (CLKFB => GND_BIT,
CLKIN => CLKIN_IN,
DSSEN => GND_BIT,
PSCLK => GND_BIT,
PSEN => GND_BIT,
PSINCDEC => GND_BIT,
RST => RST,
CLKDV => open,
CLKFX => CLKFX_BUF,
CLKFX180 => open,
CLK0 => open,
CLK2X => CLK2X_OUT,
CLK2X180 => open,
CLK90 => open,
CLK180 => open,
CLK270 => open,
LOCKED => LOCKED,
PSDONE => open,
STATUS => open);
end BEHAVIORAL;
| apache-2.0 | 05dd4533155c1c0cae0a3cb956b56803 | 0.400943 | 4.317719 | false | false | false | false |
FinnK/lems2hdl | work/N2_Izhikevich/ISIM_output/i1.vhdl | 1 | 10,541 |
---------------------------------------------------------------------
-- Standard Library bits
---------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- For Modelsim
--use ieee.fixed_pkg.all;
--use ieee.fixed_float_types.ALL;
-- For ISE
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use ieee_proposed.fixed_float_types.ALL;
use IEEE.numeric_std.all;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Entity Description
---------------------------------------------------------------------
entity i1 is
Port (
clk : in STD_LOGIC; --SYSTEM CLOCK, THIS ITSELF DOES NOT SIGNIFY TIME STEPS - AKA A SINGLE TIMESTEP MAY TAKE MANY CLOCK CYCLES
init_model : in STD_LOGIC; --SYNCHRONOUS RESET
step_once_go : in STD_LOGIC; --signals to the neuron from the core that a time step is to be simulated
component_done : out STD_LOGIC;
eventport_in_in : in STD_LOGIC;
param_time_delay : in sfixed (6 downto -18);
param_time_duration : in sfixed (6 downto -18);
param_none_amplitude : in sfixed (18 downto -13);
exposure_none_I : out sfixed (18 downto -13);
statevariable_none_I_out : out sfixed (18 downto -13);
statevariable_none_I_in : in sfixed (18 downto -13);
sysparam_time_timestep : in sfixed (-6 downto -22);
sysparam_time_simtime : in sfixed (6 downto -22)
);
end i1;
---------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-- Architecture Begins
-------------------------------------------------------------------------------------------
architecture RTL of i1 is
signal COUNT : unsigned(2 downto 0) := "000";
signal childrenCombined_Component_done_single_shot_fired : STD_LOGIC := '0';
signal childrenCombined_Component_done_single_shot : STD_LOGIC := '0';
signal childrenCombined_Component_done : STD_LOGIC := '0';
signal Component_done_int : STD_LOGIC := '0';
signal subprocess_der_int_pre_ready : STD_LOGIC := '0';
signal subprocess_der_int_ready : STD_LOGIC := '0';
signal subprocess_der_ready : STD_LOGIC := '0';
signal subprocess_dyn_int_pre_ready : STD_LOGIC := '0';
signal subprocess_dyn_int_ready : STD_LOGIC := '0';
signal subprocess_dyn_ready : STD_LOGIC := '0';
signal subprocess_model_ready : STD_LOGIC := '1';
signal subprocess_all_ready_shotdone : STD_LOGIC := '1';
signal subprocess_all_ready_shot : STD_LOGIC := '0';
signal subprocess_all_ready : STD_LOGIC := '0';
---------------------------------------------------------------------
-- Derived Variables and parameters
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- EDState internal Variables
---------------------------------------------------------------------
signal statevariable_none_I_next : sfixed (18 downto -13);
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Output Port internal Variables
---------------------------------------------------------------------
signal EventPort_in_in_internal : std_logic := '0';
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Child Components
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Begin Internal Processes
---------------------------------------------------------------------
begin
---------------------------------------------------------------------
-- Child EDComponent Instantiations and corresponding internal variables
---------------------------------------------------------------------
derived_variable_pre_process_comb :process ( sysparam_time_timestep )
begin
end process derived_variable_pre_process_comb;
derived_variable_pre_process_syn :process ( clk, init_model )
begin
subprocess_der_int_pre_ready <= '1';
end process derived_variable_pre_process_syn;
--no complex steps in derived variables
subprocess_der_int_ready <= '1';
derived_variable_process_comb :process ( sysparam_time_timestep )
begin
subprocess_der_ready <= '1';
end process derived_variable_process_comb;
derived_variable_process_syn :process ( clk,init_model )
begin
if clk'event and clk = '1' then
if subprocess_all_ready_shot = '1' then
end if;
end if;
end process derived_variable_process_syn;
---------------------------------------------------------------------
dynamics_pre_process_comb :process ( sysparam_time_timestep )
begin
end process dynamics_pre_process_comb;
dynamics_pre_process_syn :process ( clk, init_model )
begin
subprocess_dyn_int_pre_ready <= '1';
end process dynamics_pre_process_syn;
--No dynamics with complex equations found
subprocess_dyn_int_ready <= '1';
state_variable_process_dynamics_comb :process (sysparam_time_timestep)
begin
subprocess_dyn_ready <= '1';
end process state_variable_process_dynamics_comb;
state_variable_process_dynamics_syn :process (CLK,init_model)
begin
if clk'event and clk = '1' then
if subprocess_all_ready_shot = '1' then
end if;
end if;
end process state_variable_process_dynamics_syn;
------------------------------------------------------------------------------------------------------
-- EDState Variable Drivers
------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------
-- EDState variable: $par.name Driver Process
---------------------------------------------------------------------
state_variable_process_comb_0 :process (sysparam_time_timestep,init_model,sysparam_time_simtime,param_time_delay,sysparam_time_simtime,param_time_delay,param_time_duration,sysparam_time_simtime,param_time_delay,param_none_amplitude,param_time_duration,sysparam_time_simtime,param_time_delay)
variable statevariable_none_I_temp_1 : sfixed (18 downto -13);
variable statevariable_none_I_temp_2 : sfixed (18 downto -13);
variable statevariable_none_I_temp_3 : sfixed (18 downto -13);
begin
if To_slv ( resize (sysparam_time_simtime- ( param_time_delay ) ,2,-18))(20) = '1' then
statevariable_none_I_temp_1 := resize( to_sfixed ( 0 ,0 , -1 ) ,18,-13);
else
statevariable_none_I_temp_1 := statevariable_none_I_in;
end if;
if To_slv ( resize (sysparam_time_simtime- ( param_time_delay ) ,2,-18))(20) = '0' AND To_slv ( resize (sysparam_time_simtime- ( param_time_duration + param_time_delay ) ,2,-18))(20) = '1' then
statevariable_none_I_temp_2 := resize( param_none_amplitude ,18,-13);
else
statevariable_none_I_temp_2 := statevariable_none_I_temp_1;
end if;
if To_slv ( resize (sysparam_time_simtime- ( param_time_duration + param_time_delay ) ,2,-18))(20) = '0' then
statevariable_none_I_temp_3 := resize( to_sfixed ( 0 ,0 , -1 ) ,18,-13);
else
statevariable_none_I_temp_3 := statevariable_none_I_temp_2;
end if;
statevariable_none_I_next <= statevariable_none_I_temp_3;
end process;
---------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign state variables to exposures
---------------------------------------------------------------------
exposure_none_I <= statevariable_none_I_in;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign state variables to output state variables
---------------------------------------------------------------------
statevariable_none_I_out <= statevariable_none_I_next;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign derived variables to exposures
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Subprocess ready process
---------------------------------------------------------------------
subprocess_all_ready_process: process(step_once_go,subprocess_der_int_ready,subprocess_der_int_pre_ready,subprocess_der_ready,subprocess_dyn_int_pre_ready,subprocess_dyn_int_ready,subprocess_dyn_ready,subprocess_model_ready)
begin
if step_once_go = '0' and subprocess_der_int_ready = '1' and subprocess_der_int_pre_ready = '1'and subprocess_der_ready ='1' and subprocess_dyn_int_ready = '1' and subprocess_dyn_int_pre_ready = '1' and subprocess_dyn_ready = '1' and subprocess_model_ready = '1' then
subprocess_all_ready <= '1';
else
subprocess_all_ready <= '0';
end if;
end process subprocess_all_ready_process;
subprocess_all_ready_shot_process : process(clk)
begin
if rising_edge(clk) then
if (init_model='1') then
subprocess_all_ready_shot <= '0';
subprocess_all_ready_shotdone <= '1';
else
if subprocess_all_ready = '1' and subprocess_all_ready_shotdone = '0' then
subprocess_all_ready_shot <= '1';
subprocess_all_ready_shotdone <= '1';
elsif subprocess_all_ready_shot = '1' then
subprocess_all_ready_shot <= '0';
elsif subprocess_all_ready = '0' then
subprocess_all_ready_shot <= '0';
subprocess_all_ready_shotdone <= '0';
end if;
end if;
end if;
end process subprocess_all_ready_shot_process;
---------------------------------------------------------------------
count_proc:process(clk)
begin
if (clk'EVENT AND clk = '1') then
if init_model = '1' then COUNT <= "001";
component_done_int <= '1';
else if step_once_go = '1' then
COUNT <= "000";
component_done_int <= '0';
elsif COUNT = "001" then
component_done_int <= '1';
elsif subprocess_all_ready_shot = '1' then
COUNT <= COUNT + 1;
component_done_int <= '0';
end if;
end if;
end if;
end process count_proc;
component_done <= component_done_int;
end RTL;
| lgpl-3.0 | 89779aed49a7c13e8d96958b61b8ff0a | 0.490466 | 4.189587 | false | false | false | false |
Kalycito-open-automation/openPOWERLINK_V2_old_25-06-2014 | hardware/ipcore/common/openmac/src/openmacTop-rtl-ea.vhd | 2 | 67,145 | -------------------------------------------------------------------------------
--! @file openmacTop-rtl-ea.vhd
--
--! @brief OpenMAC toplevel file including openMAC, openHUB and openFILTER
--
--! @details This is the openMAC toplevel file including the MAC layer IP-Cores.
--! Additional components are provided for packet buffer storage.
-------------------------------------------------------------------------------
--
-- (c) B&R, 2013
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
--! use global library
use work.global.all;
--! use openmac package
use work.openmacPkg.all;
entity openmacTop is
generic (
-----------------------------------------------------------------------
-- Phy configuration
-----------------------------------------------------------------------
--! Number of Phy ports
gPhyPortCount : natural := 2;
--! Phy port interface type (Rmii or Mii)
gPhyPortType : natural := cPhyPortRmii;
--! Number of SMI phy ports
gSmiPortCount : natural := 1;
-----------------------------------------------------------------------
-- General configuration
-----------------------------------------------------------------------
--! Endianness ("little" or "big")
gEndianness : string := "little";
--! Enable packet activity generator (e.g. connect to LED)
gEnableActivity : natural := cFalse;
--! Enable DMA observer circuit
gEnableDmaObserver : natural := cFalse;
-----------------------------------------------------------------------
-- DMA configuration
-----------------------------------------------------------------------
--! DMA address width (byte-addressing)
gDmaAddrWidth : natural := 32;
--! DMA data width
gDmaDataWidth : natural := 16;
--! DMA burst count width
gDmaBurstCountWidth : natural := 4;
--! DMA write burst length (Rx packets) [words]
gDmaWriteBurstLength : natural := 16;
--! DMA read burst length (Tx packets) [words]
gDmaReadBurstLength : natural := 16;
--! DMA write FIFO length (Rx packets) [words]
gDmaWriteFifoLength : natural := 16;
--! DMA read FIFO length (Tx packets) [words]
gDmaReadFifoLength : natural := 16;
-----------------------------------------------------------------------
-- Packet buffer configuration
-----------------------------------------------------------------------
--! Packet buffer location for Tx packets
gPacketBufferLocTx : natural := cPktBufLocal;
--! Packet buffer location for Rx packets
gPacketBufferLocRx : natural := cPktBufLocal;
--! Packet buffer log2(size) [log2(bytes)]
gPacketBufferLog2Size : natural := 10;
-----------------------------------------------------------------------
-- MAC timer configuration
-----------------------------------------------------------------------
--! Number of timers
gTimerCount : natural := 2;
--! Enable timer pulse width control
gTimerEnablePulseWidth : natural := cFalse;
--! Timer pulse width register width
gTimerPulseRegWidth : natural := 10
);
port (
-----------------------------------------------------------------------
-- Clock and reset signal pairs
-----------------------------------------------------------------------
--! Main clock used for openMAC, openHUB and openFILTER (freq = 50 MHz)
iClk : in std_logic;
--! Main reset used for openMAC, openHUB and openFILTER
iRst : in std_logic;
--! DMA master clock
iDmaClk : in std_logic;
--! DMA master reset
iDmaRst : in std_logic;
--! Packet buffer clock
iPktBufClk : in std_logic;
--! Packet buffer reset
iPktBufRst : in std_logic;
--! Twice main clock used for Rmii Tx path
iClk2x : in std_logic;
-----------------------------------------------------------------------
-- MAC REG memory mapped slave
-----------------------------------------------------------------------
--! MM slave MAC REGISTER chipselect
iMacReg_chipselect : in std_logic;
--! MM slave MAC REGISTER write
iMacReg_write : in std_logic;
--! MM slave MAC REGISTER read
iMacReg_read : in std_logic;
--! MM slave MAC REGISTER waitrequest
oMacReg_waitrequest : out std_logic;
--! MM slave MAC REGISTER byteenable
iMacReg_byteenable : in std_logic_vector(cMacRegDataWidth/cByteLength-1 downto 0);
--! MM slave MAC REGISTER address
iMacReg_address : in std_logic_vector(cMacRegAddrWidth-1 downto 0);
--! MM slave MAC REGISTER writedata
iMacReg_writedata : in std_logic_vector(cMacRegDataWidth-1 downto 0);
--! MM slave MAC REGISTER readdata
oMacReg_readdata : out std_logic_vector(cMacRegDataWidth-1 downto 0);
-----------------------------------------------------------------------
-- MAC TIMER memory mapped slave
-----------------------------------------------------------------------
--! MM slave MAC TIMER chipselect
iMacTimer_chipselect : in std_logic;
--! MM slave MAC TIMER write
iMacTimer_write : in std_logic;
--! MM slave MAC TIMER read
iMacTimer_read : in std_logic;
--! MM slave MAC TIMER waitrequest
oMacTimer_waitrequest : out std_logic;
--! MM slave MAC TIMER address
iMacTimer_address : in std_logic_vector(cMacTimerAddrWidth-1 downto 0);
--! MM slave MAC TIMER writedata
iMacTimer_writedata : in std_logic_vector(cMacTimerDataWidth-1 downto 0);
--! MM slave MAC TIMER readdata
oMacTimer_readdata : out std_logic_vector(cMacTimerDataWidth-1 downto 0);
-----------------------------------------------------------------------
-- MAC PACKET BUFFER memory mapped slave
-----------------------------------------------------------------------
--! MM slave MAC PACKET BUFFER chipselect
iPktBuf_chipselect : in std_logic;
--! MM slave MAC PACKET BUFFER write
iPktBuf_write : in std_logic;
--! MM slave MAC PACKET BUFFER read
iPktBuf_read : in std_logic;
--! MM slave MAC PACKET BUFFER waitrequest
oPktBuf_waitrequest : out std_logic;
--! MM slave MAC PACKET BUFFER byteenable
iPktBuf_byteenable : in std_logic_vector(cPktBufDataWidth/cByteLength-1 downto 0);
--! MM slave MAC PACKET BUFFER address (width given by gPacketBufferLog2Size)
iPktBuf_address : in std_logic_vector(gPacketBufferLog2Size-1 downto 0);
--! MM slave MAC PACKET BUFFER writedata
iPktBuf_writedata : in std_logic_vector(cPktBufDataWidth-1 downto 0);
--! MM slave MAC PACKET BUFFER readdata
oPktBuf_readdata : out std_logic_vector(cPktBufDataWidth-1 downto 0);
-----------------------------------------------------------------------
-- MAC DMA memory mapped master
-----------------------------------------------------------------------
--! MM master MAC DMA write
oDma_write : out std_logic;
--! MM master MAC DMA read
oDma_read : out std_logic;
--! MM master MAC DMA waitrequest
iDma_waitrequest : in std_logic;
--! MM master MAC DMA readdatavalid
iDma_readdatavalid : in std_logic;
--! MM master MAC DMA byteenable
oDma_byteenable : out std_logic_vector(gDmaDataWidth/cByteLength-1 downto 0);
--! MM master MAC DMA address
oDma_address : out std_logic_vector(gDmaAddrWidth-1 downto 0);
--! MM master MAC DMA burstcount
oDma_burstcount : out std_logic_vector(gDmaBurstCountWidth-1 downto 0);
--! MM master MAC DMA burstcounter (holds current burst count value)
oDma_burstcounter : out std_logic_vector(gDmaBurstCountWidth-1 downto 0);
--! MM master MAC DMA writedata
oDma_writedata : out std_logic_vector(gDmaDataWidth-1 downto 0);
--! MM master MAC DMA readdata
iDma_readdata : in std_logic_vector(gDmaDataWidth-1 downto 0);
-----------------------------------------------------------------------
-- Interrupts
-----------------------------------------------------------------------
--! MAC TIMER interrupt
oMacTimer_interrupt : out std_logic;
--! MAC Tx interrupt
oMacTx_interrupt : out std_logic;
--! MAC Rx interrupt
oMacRx_interrupt : out std_logic;
-----------------------------------------------------------------------
-- Rmii Phy ports
-----------------------------------------------------------------------
--! Rmii Rx ports
iRmii_Rx : in tRmiiPathArray(gPhyPortCount-1 downto 0);
--! Rmii Rx error ports
iRmii_RxError : in std_logic_vector(gPhyPortCount-1 downto 0);
--! Rmii Tx ports
oRmii_Tx : out tRmiiPathArray(gPhyPortCount-1 downto 0);
-----------------------------------------------------------------------
-- Mii Phy ports
-----------------------------------------------------------------------
--! Mii Rx ports
iMii_Rx : in tMiiPathArray(gPhyPortCount-1 downto 0);
--! Mii Rx error ports
iMii_RxError : in std_logic_vector(gPhyPortCount-1 downto 0);
--! Mii Rx Clocks
iMii_RxClk : in std_logic_vector(gPhyPortCount-1 downto 0);
--! Mii Tx ports
oMii_Tx : out tMiiPathArray(gPhyPortCount-1 downto 0);
--! Mii Tx Clocks
iMii_TxClk : in std_logic_vector(gPhyPortCount-1 downto 0);
-----------------------------------------------------------------------
-- Phy management interface
-----------------------------------------------------------------------
--! Phy reset (low-active)
onPhy_reset : out std_logic_vector(gSmiPortCount-1 downto 0);
--! SMI clock
oSmi_clk : out std_logic_vector(gSmiPortCount-1 downto 0);
--! SMI data output enable (tri-state buffer)
oSmi_data_outEnable : out std_logic;
--! SMI data output (tri-state buffer)
oSmi_data_out : out std_logic_vector(gSmiPortCount-1 downto 0);
--! SMI data input (tri-state buffer)
iSmi_data_in : in std_logic_vector(gSmiPortCount-1 downto 0);
-----------------------------------------------------------------------
-- Other ports
-----------------------------------------------------------------------
--! Packet activity (enabled with gEnableActivity)
oActivity : out std_logic;
--! MAC TIMER outputs
oMacTimer : out std_logic_vector(gTimerCount-1 downto 0)
);
end openmacTop;
architecture rtl of openmacTop is
---------------------------------------------------------------------------
-- Constants
---------------------------------------------------------------------------
--! Lowest index of Phy port
constant cPhyPortLow : natural := cHubIntPort+1;
--! Highest index of Phy port
constant cPhyPortHigh : natural := gPhyPortCount+1;
---------------------------------------------------------------------------
-- Component types
---------------------------------------------------------------------------
--! openMAC port type
type tOpenMacPort is record
rst : std_logic;
clk : std_logic;
nReg_write : std_logic;
reg_selectRam : std_logic;
reg_selectCont : std_logic;
nReg_byteenable : std_logic_vector(1 downto 0);
reg_address : std_logic_vector(10 downto 1);
reg_writedata : std_logic_vector(15 downto 0);
reg_readdata : std_logic_vector(15 downto 0);
nTxInterrupt : std_logic;
nRxInterrupt : std_logic;
dma_readDone : std_logic;
dma_writeDone : std_logic;
dma_request : std_logic;
nDma_write : std_logic;
dma_acknowledge : std_logic;
dma_requestOverflow : std_logic;
dma_readLength : std_logic_vector(11 downto 0);
dma_address : std_logic_vector(gDmaAddrWidth-1 downto 1);
dma_writedata : std_logic_vector(15 downto 0);
dma_readdata : std_logic_vector(15 downto 0);
rmii : tRmii;
hubRxPort : std_logic_vector(1 downto 0);
macTime : std_logic_vector(cMacTimeWidth-1 downto 0);
end record;
--! Phy management port type
type tPhyMgmtPort is record
rst : std_logic;
clk : std_logic;
address : std_logic_vector(3 downto 1);
chipselect : std_logic;
nByteenable : std_logic_vector(1 downto 0);
nWrite : std_logic;
writedata : std_logic_vector(15 downto 0);
readdata : std_logic_vector(15 downto 0);
smiClk : std_logic;
smiDataIn : std_logic;
smiDataOut : std_logic;
smiDataOutEnable : std_logic;
nPhyReset : std_logic;
end record;
--! openMAC TIMER port type
type tOpenMacTimerPort is record
rst : std_logic;
clk : std_logic;
write : std_logic;
address : std_logic_vector(3 downto 2);
writedata : std_logic_vector(31 downto 0);
readdata : std_logic_vector(31 downto 0);
macTime : std_logic_vector(cMacTimeWidth-1 downto 0);
interrupt : std_logic;
toggle : std_logic;
end record;
--! openHUB port type
type tOpenHubPort is record
rst : std_logic;
clk : std_logic;
rx : tRmiiPathArray(cPhyPortHigh downto cHubIntPort);
tx : tRmiiPathArray(cPhyPortHigh downto cHubIntPort);
internPort : integer range cHubIntPort to cPhyPortHigh;
transmitMask : std_logic_vector(cPhyPortHigh downto cHubIntPort);
receivePort : integer range 0 to cPhyPortHigh;
end record;
--! openFILTER port type
type tOpenFilterPort is record
rst : std_logic;
clk : std_logic;
rxIn : tRmiiPathArray(cPhyPortHigh downto cPhyPortLow);
rxOut : tRmiiPathArray(cPhyPortHigh downto cPhyPortLow);
txIn : tRmiiPathArray(cPhyPortHigh downto cPhyPortLow);
txOut : tRmiiPathArray(cPhyPortHigh downto cPhyPortLow);
rxError : std_logic_vector(cPhyPortHigh downto cPhyPortLow);
end record;
--! RMII-to-MII converter port type
type tConvRmiiToMiiPort is record
rst : std_logic;
clk : std_logic;
rmiiTx : tRmiiPathArray(cPhyPortHigh downto cPhyPortLow);
rmiiRx : tRmiiPathArray(cPhyPortHigh downto cPhyPortLow);
miiTx : tMiiPathArray(cPhyPortHigh downto cPhyPortLow);
miiTxClk : std_logic_vector(cPhyPortHigh downto cPhyPortLow);
miiRx : tMiiPathArray(cPhyPortHigh downto cPhyPortLow);
miiRxError : std_logic_vector(cPhyPortHigh downto cPhyPortLow);
miiRxClk : std_logic_vector(cPhyPortHigh downto cPhyPortLow);
end record;
--! Packet Buffer single port type
type tPacketBufferSinglePort is record
clk : std_logic;
rst : std_logic;
enable : std_logic;
write : std_logic;
address : std_logic_vector(gPacketBufferLog2Size-1 downto logDualis(cPktBufDataWidth/cByteLength));
byteenable : std_logic_vector(cPktBufDataWidth/cByteLength-1 downto 0);
writedata : std_logic_vector(cPktBufDataWidth-1 downto 0);
readdata : std_logic_vector(cPktBufDataWidth-1 downto 0);
end record;
--! Packet Buffer dual port type (port to DMA and host)
type tPacketBufferPort is record
dma : tPacketBufferSinglePort;
dma_ack : std_logic;
dma_highWordSel : std_logic;
host : tPacketBufferSinglePort;
end record;
--! DMA port type
type tDmaMaster_dmaPort is record
clk : std_logic;
rst : std_logic; --FIXME: Rename in openMAC_DMAmaster
reqWrite : std_logic;
reqRead : std_logic;
reqOverflow : std_logic;
ackWrite : std_logic;
ackRead : std_logic;
readError : std_logic;
readLength : std_logic_vector(11 downto 0);
writeError : std_logic;
address : std_logic_vector(gDmaAddrWidth-1 downto 1);
writedata : std_logic_vector(15 downto 0);
readdata : std_logic_vector(15 downto 0);
end record;
--! Master port type
type tDmaMaster_masterPort is record
clk : std_logic;
rst : std_logic; --FIXME: Add to openMAC_DMAmaster
write : std_logic;
read : std_logic;
readdatavalid : std_logic;
waitrequest : std_logic;
address : std_logic_vector(gDmaAddrWidth-1 downto 0);
byteenable : std_logic_vector(gDmaDataWidth/cByteLength-1 downto 0);
burstcount : std_logic_vector(gDmaBurstCountWidth-1 downto 0);
burstcounter : std_logic_vector(gDmaBurstCountWidth-1 downto 0);
writedata : std_logic_vector(gDmaDataWidth-1 downto 0);
readdata : std_logic_vector(gDmaDataWidth-1 downto 0);
end record;
--! DMA Master port type
type tDmaMasterPort is record
dma : tDmaMaster_dmaPort;
master : tDmaMaster_masterPort;
mac_rxOff : std_logic;
mac_txOff : std_logic;
end record;
--! Activity port type
type tActivityPort is record
clk : std_logic;
rst : std_logic;
txEnable : std_logic;
rxDataValid : std_logic;
activity : std_logic;
end record;
---------------------------------------------------------------------------
-- Configuration
---------------------------------------------------------------------------
-- MAC TIMER
--! Function to convert number of timers into generate boolean for
--! second timer.
function macTimer_gen2ndTimer (timerCnt : natural) return boolean is
variable vRet_tmp : boolean;
begin
--default
vRet_tmp := FALSE;
case timerCnt is
when 1 =>
vRet_tmp := FALSE;
when 2 =>
vRet_tmp := TRUE;
when others =>
assert (FALSE)
report "The MAC TIMER only supports 1 and 2 timers!"
severity failure;
end case;
return vRet_tmp;
end function macTimer_gen2ndTimer;
--! MAC Timer generate second compare timer
constant cMacTimer_2ndTimer : boolean := macTimer_gen2ndTimer(gTimerCount);
---------------------------------------------------------------------------
-- Memory map
---------------------------------------------------------------------------
--! Select vector for MacReg
signal selVector_macReg : std_logic_vector(cMemMapCount-1 downto 0);
--! Alias for select DMA Error
alias sel_dmaError : std_logic is selVector_macReg(cMemMapIndex_dmaError);
--! Alias for select IRQ Table
alias sel_irqTable : std_logic is selVector_macReg(cMemMapIndex_irqTable);
--! Alias for select SMI
alias sel_smi : std_logic is selVector_macReg(cMemMapIndex_smi);
--! Alias for select MAC RAM
alias sel_macRam : std_logic is selVector_macReg(cMemMapIndex_macRam);
--! Alias for select MAC Filter
alias sel_macFilter : std_logic is selVector_macReg(cMemMapIndex_macFilter);
--! Alias for select MAC Content
alias sel_macCont : std_logic is selVector_macReg(cMemMapIndex_macCont);
--! Acknowledge vector for MacReg
signal ackVector : tMemAccessAckArray(cMemAccessDelayCount-1 downto 0);
--! Alias for acknowledge PKT BUF
alias ack_pktBuf : tMemAccessAck is ackVector(cMemAccessDelayIndex_pktBuf);
--! Alias for acknowledge MAC TIMER
alias ack_macTimer : tMemAccessAck is ackVector(cMemAccessDelayIndex_macTimer);
--! Alias for acknowledge MAC REG
alias ack_macReg : tMemAccessAck is ackVector(cMemAccessDelayIndex_macReg);
---------------------------------------------------------------------------
-- Interrupt signals
---------------------------------------------------------------------------
--! Interrupt table vector
signal irqTable : tMacRegIrqTable; --aliases are used to assign it
--! Alias for MAC Tx Interrupt
alias irqTable_macTx : std_logic is irqTable(cMacRegIrqTable_macTx);
--! Alias for MAC Rx Interrupt
alias irqTable_macRx : std_logic is irqTable(cMacRegIrqTable_macRx);
---------------------------------------------------------------------------
-- DMA error signals
---------------------------------------------------------------------------
--! DMA error table
signal dmaErrorTable : tMacDmaErrorTable; --aliases are used to assign it
--! Alias for DMA read error
alias dmaErrorTable_read : std_logic is dmaErrorTable(cMacDmaErrorTable_read);
--! Alias for DMA write error
alias dmaErrorTable_write : std_logic is dmaErrorTable(cMacDmaErrorTable_write);
---------------------------------------------------------------------------
-- RMII registers for latching input and output path (improves timing)
---------------------------------------------------------------------------
--! Rmii Rx paths
signal rmiiRxPath_reg : tRmiiPathArray(gPhyPortCount-1 downto 0);
--! Rmii Rx error paths
signal rmiiRxPathError_reg : std_logic_vector(gPhyPortCount-1 downto 0);
--! Rmii Tx paths
signal rmiiTxPath_reg : tRmiiPathArray(gPhyPortCount-1 downto 0);
---------------------------------------------------------------------------
-- MII signals
---------------------------------------------------------------------------
--! Mii Tx paths
signal miiTxPath : tMiiPathArray(gPhyPortCount-1 downto 0);
---------------------------------------------------------------------------
-- Instances
---------------------------------------------------------------------------
--! Instance openMAC port
signal inst_openmac : tOpenMacPort;
--! Instance phy management port
signal inst_phyMgmt : tPhyMgmtPort;
--! Instance openMAC TIMER port
signal inst_openmacTimer : tOpenMacTimerPort;
--! Instance openHUB port
signal inst_openhub : tOpenHubPort;
--! Instances openFILTER port
signal inst_openfilter : tOpenFilterPort;
--! Instances RMII-to-MII converter port
signal inst_convRmiiToMii : tConvRmiiToMiiPort;
--! Instance Packet buffer port
signal inst_pktBuffer : tPacketBufferPort;
--! Instance DMA master port
signal inst_dmaMaster : tDmaMasterPort;
--! Instance activity port
signal inst_activity : tActivityPort;
begin
---------------------------------------------------------------------------
-- Assign toplevel
---------------------------------------------------------------------------
--! In this block the entity's output ports are assigned to internals.
TOPLEVELMAP : block
begin
--! This process assigns the oMacReg_readdata port to the selected
--! memory.
ASSIGN_MACREG_RDDATA : process (
selVector_macReg,
irqTable,
dmaErrorTable,
iMacReg_byteenable,
inst_openmac.reg_readdata,
inst_phyMgmt.readdata
)
begin
--default assignment
oMacReg_readdata <= (others => cInactivated);
if sel_macRam = cActivated or sel_macCont = cActivated then
oMacReg_readdata <= inst_openmac.reg_readdata;
-- swap bytes if big endian and selected word
if gEndianness = "big" and iMacReg_byteenable = "11" then
oMacReg_readdata <= byteSwap(inst_openmac.reg_readdata);
end if;
elsif sel_smi = cActivated then
oMacReg_readdata <= inst_phyMgmt.readdata;
-- swap bytes if big endian and selected word
if gEndianness = "big" and iMacReg_byteenable = "11" then
oMacReg_readdata <= byteSwap(inst_phyMgmt.readdata);
end if;
elsif sel_irqTable = cActivated then
oMacReg_readdata <= irqTable;
-- swap bytes if big endian
if gEndianness = "big" then
oMacReg_readdata <= byteSwap(irqTable);
end if;
elsif sel_dmaError = cActivated then
oMacReg_readdata <= dmaErrorTable;
-- swap byte if big endian
if gEndianness = "big" then
oMacReg_readdata <= byteSwap(dmaErrorTable);
end if;
end if;
end process ASSIGN_MACREG_RDDATA;
oMacReg_waitrequest <= not(ack_macReg.write or ack_macReg.read);
oMacTimer_readdata <= inst_openmacTimer.readdata;
oMacTimer_waitrequest <= not(ack_macTimer.write or ack_macTimer.read);
oPktBuf_readdata <= inst_pktBuffer.host.readdata;
oPktBuf_waitrequest <= not(ack_pktBuf.write or ack_pktBuf.read);
oDma_address <= inst_dmaMaster.master.address;
oDma_burstcount <= inst_dmaMaster.master.burstcount;
oDma_burstcounter <= inst_dmaMaster.master.burstcounter;
oDma_byteenable <= inst_dmaMaster.master.byteenable;
oDma_read <= inst_dmaMaster.master.read;
oDma_write <= inst_dmaMaster.master.write;
oDma_writedata <= inst_dmaMaster.master.writedata;
oMacTimer_interrupt <= inst_openmacTimer.interrupt;
oMacTx_interrupt <= not inst_openmac.nTxInterrupt;
oMacRx_interrupt <= not inst_openmac.nRxInterrupt;
oRmii_Tx <= rmiiTxPath_reg;
oMii_Tx <= miiTxPath;
oSmi_clk <= (others => inst_phyMgmt.smiClk);
oSmi_data_out <= (others => inst_phyMgmt.smiDataOut);
oSmi_data_outEnable <= inst_phyMgmt.smiDataOutEnable;
onPhy_reset <= (others => inst_phyMgmt.nPhyReset);
oActivity <= inst_activity.activity;
ASSIGNMACTIMER : process (
inst_openmacTimer
)
begin
for i in oMacTimer'range loop
if i = 0 then
oMacTimer(i) <= inst_openmacTimer.interrupt;
elsif i = 1 then
oMacTimer(i) <= inst_openmacTimer.toggle;
else
-- unsupported timer assigned to zero
oMacTimer(i) <= cInactivated;
end if;
end loop;
end process ASSIGNMACTIMER;
end block TOPLEVELMAP;
---------------------------------------------------------------------------
-- Assign instances
---------------------------------------------------------------------------
--! In this block the instances are assigned.
INSTANCEMAP : block
begin
-----------------------------------------------------------------------
-- The openMAC
-----------------------------------------------------------------------
inst_openmac.rst <= iRst;
inst_openmac.clk <= iClk;
inst_openmac.nReg_write <= not iMacReg_write;
inst_openmac.reg_selectRam <= sel_macRam;
inst_openmac.reg_selectCont <= sel_macCont;
inst_openmac.nReg_byteenable <= not iMacReg_byteenable;
inst_openmac.reg_address <= iMacReg_address(inst_openmac.reg_address'range);
--! This process assignes the register writedata. Additionally the DMA
--! read path and the request acknowlegde signals are assigned from the
--! configured sources (packet buffer vs. DMA).
ASSIGN_MAC : process (
iMacReg_writedata,
iMacReg_byteenable,
inst_pktBuffer,
inst_dmaMaster
)
--! DMA ack variable for or'ing all those acks.
variable vAck_tmp : std_logic;
--! Alias for packet buffer high word
alias pktBufRead_high : std_logic_vector(15 downto 0) is
inst_pktBuffer.dma.readdata(cPktBufDataWidth-1 downto cPktBufDataWidth/2);
--! Alias for packet buffer low word
alias pktBufRead_low : std_logic_vector(15 downto 0) is
inst_pktBuffer.dma.readdata(cPktBufDataWidth/2-1 downto 0);
begin
-- no defaults, so take care!
-------------------------------------------------------------------
-- writedata is directly assigned, or byte-swapped
inst_openmac.reg_writedata <= iMacReg_writedata;
-- swap bytes if big endian and selected word
if gEndianness = "big" and iMacReg_byteenable = "11" then
inst_openmac.reg_writedata <= byteSwap(iMacReg_writedata);
end if;
-------------------------------------------------------------------
-------------------------------------------------------------------
-- Initialize the ack variable to zero, then or it with all sources.
vAck_tmp := cInactivated;
-- Assign read acknowledge.
case gPacketBufferLocTx is
when cPktBufExtern =>
-- Tx packets come from DMA master
vAck_tmp := vAck_tmp or inst_dmaMaster.dma.ackRead;
when cPktBufLocal =>
-- Tx packets come from packet buffer
vAck_tmp := vAck_tmp or inst_pktBuffer.dma_ack;
when others =>
assert (FALSE)
report "The Tx packet buffer location is unknown! Don't know how to ack!"
severity failure;
end case;
-- Assign write acknowledge.
case gPacketBufferLocRx is
when cPktBufExtern =>
-- Rx packets go to DMA master
vAck_tmp := vAck_tmp or inst_dmaMaster.dma.ackWrite;
when cPktBufLocal =>
-- Rx packets go to packet buffer
vAck_tmp := vAck_tmp or inst_pktBuffer.dma_ack;
when others =>
assert (FALSE)
report "The Rx packet buffer location is unknown! Don't know how to ack!"
severity failure;
end case;
-- Assign the variable state to the signal.
inst_openmac.dma_acknowledge <= vAck_tmp;
-------------------------------------------------------------------
-------------------------------------------------------------------
-- Decide on the readdata source for the DMA.
case gPacketBufferLocTx is
when cPktBufExtern =>
-- Tx packet come from DMA master
inst_openmac.dma_readdata <= inst_dmaMaster.dma.readdata;
when cPktBufLocal =>
-- Tx packets come from packet buffer, but select the right word
if inst_pktBuffer.dma_highWordSel = cActivated then
inst_openmac.dma_readdata <= pktBufRead_high;
else
inst_openmac.dma_readdata <= pktBufRead_low;
end if;
when others =>
assert (FALSE)
report "The Tx packet buffer location is unknown! Don't know the source!"
severity failure;
end case;
end process ASSIGN_MAC;
-- Note that internal port is crossed!
inst_openmac.rmii.rx <= inst_openhub.tx(cHubIntPort);
-- Clip the hub receive port to two bits
inst_openmac.hubRxPort <= std_logic_vector(
resize(
to_unsigned(inst_openhub.receivePort, logDualis(cPhyPortHigh)),
inst_openmac.hubRxPort'length)
);
-- Assign interrupts to irq Table
irqTable_macRx <= not inst_openmac.nRxInterrupt;
irqTable_macTx <= not inst_openmac.nTxInterrupt;
-----------------------------------------------------------------------
-- The phy management
-----------------------------------------------------------------------
inst_phyMgmt.clk <= iClk;
inst_phyMgmt.rst <= iRst;
inst_phyMgmt.address <= iMacReg_address(inst_phyMgmt.address'range);
inst_phyMgmt.chipselect <= sel_smi;
inst_phyMgmt.nByteenable <= not iMacReg_byteenable;
inst_phyMgmt.nWrite <= not iMacReg_write;
inst_phyMgmt.writedata <= iMacReg_writedata when gEndianness = "little" else
iMacReg_writedata when gEndianness = "big" and iMacReg_byteenable /= "11" else
byteSwap(iMacReg_writedata);
inst_phyMgmt.smiDataIn <= reduceAnd(iSmi_data_in);
-----------------------------------------------------------------------
-- The openMAC timer
-----------------------------------------------------------------------
inst_openmacTimer.clk <= iClk;
inst_openmacTimer.rst <= iRst;
inst_openmacTimer.write <= iMacTimer_write and iMacTimer_chipselect;
inst_openmacTimer.address <= iMacTimer_address(inst_openmacTimer.address'range);
inst_openmacTimer.writedata <= iMacTimer_writedata;
-- this is the mac time
inst_openmacTimer.macTime <= inst_openmac.macTime;
-----------------------------------------------------------------------
-- The openHUB
-----------------------------------------------------------------------
inst_openhub.rst <= iRst;
inst_openhub.clk <= iClk;
inst_openhub.internPort <= cHubIntPort;
-- Enable all ports
inst_openhub.transmitMask <= (others => cActivated);
--! This process simply assigns the hub ports.
ASSIGN_HUB : process (
inst_openmac.rmii.tx,
inst_openfilter
)
begin
-- no defaults, so take care!
-- Loop through phy ports and internal hub port (MAC).
for i in cPhyPortHigh downto cHubIntPort loop
-- Assign internal port to mac, others to filter.
if i = cHubIntPort then
-- Note that internal port is crossed!
inst_openhub.rx(i) <= inst_openmac.rmii.tx;
else
inst_openhub.rx(i) <= inst_openfilter.rxOut(i);
end if;
end loop;
end process ASSIGN_HUB;
-----------------------------------------------------------------------
-- The openFILTER(s)
-----------------------------------------------------------------------
inst_openfilter.rst <= iRst;
inst_openfilter.clk <= iClk;
--! This process assigns the phy ports to the generated filters.
ASSIGN_FILTERS : process (
inst_convRmiiToMii,
inst_openhub,
rmiiRxPath_reg,
rmiiRxPathError_reg
)
begin
-- no defaults, so take care!
-- Loop through phy ports only (internal hub port is skipped).
for i in cPhyPortHigh downto cPhyPortLow loop
-- assign from phy or RMII-to-MII converter
case gPhyPortType is
when cPhyPortRmii =>
inst_openfilter.rxIn(i) <= rmiiRxPath_reg(i-(cPhyPortLow));
inst_openfilter.rxError(i) <= rmiiRxPathError_reg(i-(cPhyPortLow));
when cPhyPortMii =>
inst_openfilter.rxIn(i) <= inst_convRmiiToMii.rmiiRx(i);
-- Filter Rx error is always zero, since converter already dumps packets!
inst_openfilter.rxError(i) <= cInactivated;
when others =>
assert (FALSE)
report "Wrong phy port type in ASSIGN_FILTERS!"
severity failure;
end case;
-- assign from hub
inst_openfilter.txIn(i) <= inst_openhub.tx(i);
end loop;
end process ASSIGN_FILTERS;
-----------------------------------------------------------------------
-- The RMII-to-MII converter(s)
-----------------------------------------------------------------------
inst_convRmiiToMii.clk <= iClk;
inst_convRmiiToMii.rst <= iRst;
inst_convRmiiToMii.rmiiTx <= inst_openfilter.txOut;
inst_convRmiiToMii.miiRx <= iMii_Rx;
inst_convRmiiToMii.miiRxError <= iMii_RxError;
inst_convRmiiToMii.miiRxClk <= iMii_RxClk;
inst_convRmiiToMii.miiTxClk <= iMii_TxClk;
-----------------------------------------------------------------------
-- The PACKET BUFFER
-----------------------------------------------------------------------
-- Assign DMA port side
inst_pktBuffer.dma.clk <= inst_openmac.clk;
inst_pktBuffer.dma.rst <= inst_openmac.rst;
inst_pktBuffer.dma.enable <= cActivated;
-- Note: DMA has data width of 16 bit and Packet Buffer DPRAM hsa 32 bit.
-- => Conversion necessary!
assert ((cPktBufDataWidth = 32) and (inst_openmac.dma_writedata'length = 16))
report "Revise DMA to packet store path. Implementation is fixed to 32/16!"
severity failure;
--! This process assigns the openMAC DMA ports to the packet buffer.
ASSIGN_DMAPORT : process (
inst_openmac
)
--! This variable is assigned to the DMA's word address
variable vDmaAddrWord_tmp : std_logic_vector(inst_openmac.dma_address'range);
--! This variable is assigned to the DMA's dword address
variable vDmaAddrDword_tmp : std_logic_vector(vDmaAddrWord_tmp'left downto 2);
begin
-- no defaults, so take care!
-- Assign DMA address to variables
vDmaAddrWord_tmp := inst_openmac.dma_address;
vDmaAddrDword_tmp := vDmaAddrWord_tmp(vDmaAddrDword_tmp'range); -- only assigned LEFT downto 2
-- Packet buffer address is for 32 bit (dwords)
inst_pktBuffer.dma.address <= vDmaAddrDword_tmp(inst_pktBuffer.dma.address'range);
-- DMA writes words, so duplicate words to packet buffer
inst_pktBuffer.dma.writedata <= inst_openmac.dma_writedata & inst_openmac.dma_writedata;
-- Packet buffer write strobe is logically and'd of request and write
-- Also the packet location is considered!
if (inst_openmac.dma_request = cActivated and
inst_openmac.nDma_write = cnActivated and
gPacketBufferLocRx = cPktBufLocal) then
inst_pktBuffer.dma.write <= cActivated;
else
inst_pktBuffer.dma.write <= cInactivated;
end if;
-- Duplicated words are present at writeport, select DMA's word addr bit
if vDmaAddrWord_tmp(vDmaAddrWord_tmp'right) = cActivated then
-- select high word
inst_pktBuffer.dma.byteenable <= "1100";
else
-- select low word
inst_pktBuffer.dma.byteenable <= "0011";
end if;
end process ASSIGN_DMAPORT;
-- Assign Host port side
inst_pktBuffer.host.clk <= iPktBufClk;
inst_pktBuffer.host.rst <= iPktBufRst;
inst_pktBuffer.host.enable <= cActivated;
inst_pktBuffer.host.write <= iPktBuf_chipselect and iPktBuf_write;
inst_pktBuffer.host.byteenable <= iPktBuf_byteenable;
inst_pktBuffer.host.address <= iPktBuf_address(inst_pktBuffer.host.address'range);
inst_pktBuffer.host.writedata <= iPktBuf_writedata;
-----------------------------------------------------------------------
-- The DMA master
-----------------------------------------------------------------------
inst_dmaMaster.dma.clk <= inst_openmac.clk;
inst_dmaMaster.dma.rst <= inst_openmac.rst;
inst_dmaMaster.dma.reqWrite <= inst_openmac.dma_request and not inst_openmac.nDma_write;
inst_dmaMaster.dma.reqRead <= inst_openmac.dma_request and inst_openmac.nDma_write;
inst_dmaMaster.dma.reqOverflow <= inst_openmac.dma_requestOverflow;
inst_dmaMaster.dma.readLength <= inst_openmac.dma_readLength;
inst_dmaMaster.dma.address <= inst_openmac.dma_address;
inst_dmaMaster.dma.writedata <= inst_openmac.dma_writedata;
inst_dmaMaster.master.clk <= iDmaClk;
inst_dmaMaster.master.rst <= iDmaRst;
inst_dmaMaster.master.readdatavalid <= iDma_readdatavalid;
inst_dmaMaster.master.waitrequest <= iDma_waitrequest;
inst_dmaMaster.master.readdata <= iDma_readdata;
inst_dmaMaster.mac_rxOff <= inst_openmac.dma_writeDone;
inst_dmaMaster.mac_txOff <= inst_openmac.dma_readDone;
-- Assign DMA error table
dmaErrorTable_read <= inst_dmaMaster.dma.readError;
dmaErrorTable_write <= inst_dmaMaster.dma.writeError;
-----------------------------------------------------------------------
-- The activity generator
-----------------------------------------------------------------------
inst_activity.clk <= inst_openmac.clk;
inst_activity.rst <= inst_openmac.rst;
inst_activity.rxDataValid <= inst_openmac.rmii.rx.enable;
inst_activity.txEnable <= inst_openmac.rmii.tx.enable;
end block INSTANCEMAP;
---------------------------------------------------------------------------
-- Component instatiations
---------------------------------------------------------------------------
--! The openMAC core instance implements the MAC-layer.
--! All features are enabled to provide time-triggered packet Tx and
--! dynamic response delay.
THEOPENMAC : entity work.openmac
generic map (
gDmaHighAddr => gDmaAddrWidth-1,
gTimerEnable => TRUE,
gTimerTrigTx => TRUE,
gAutoTxDel => TRUE
)
port map (
iRst => inst_openmac.rst,
iClk => inst_openmac.clk,
inWrite => inst_openmac.nReg_write,
iSelectRam => inst_openmac.reg_selectRam,
iSelectCont => inst_openmac.reg_selectCont,
inByteenable => inst_openmac.nReg_byteenable,
iAddress => inst_openmac.reg_address,
iWritedata => inst_openmac.reg_writedata,
oReaddata => inst_openmac.reg_readdata,
onTxIrq => inst_openmac.nTxInterrupt,
onRxIrq => inst_openmac.nRxInterrupt,
onTxBegIrq => open, --unused interrupt
oDmaReadDone => inst_openmac.dma_readDone,
oDmaWriteDone => inst_openmac.dma_writeDone,
oDmaReq => inst_openmac.dma_request,
onDmaWrite => inst_openmac.nDma_write,
iDmaAck => inst_openmac.dma_acknowledge,
oDmaReqOverflow => inst_openmac.dma_requestOverflow,
oDmaReadLength => inst_openmac.dma_readLength,
oDmaAddress => inst_openmac.dma_address,
oDmaWritedata => inst_openmac.dma_writedata,
iDmaReaddata => inst_openmac.dma_readdata,
iRxData => inst_openmac.rmii.rx.data,
iRxDv => inst_openmac.rmii.rx.enable,
oTxData => inst_openmac.rmii.tx.data,
oTxEn => inst_openmac.rmii.tx.enable,
iHubRxPort => inst_openmac.hubRxPort,
oMacTime => inst_openmac.macTime
);
--! The phy management core is an SMI master to communication with the
--! phys.
THEPHYMGMT : entity work.phyMgmt
port map (
iRst => inst_phyMgmt.rst,
iClk => inst_phyMgmt.clk,
iAddress => inst_phyMgmt.address,
iSelect => inst_phyMgmt.chipselect,
inByteenable => inst_phyMgmt.nByteenable,
inWrite => inst_phyMgmt.nWrite,
iWritedata => inst_phyMgmt.writedata,
oReaddata => inst_phyMgmt.readdata,
oSmiClk => inst_phyMgmt.smiClk,
iSmiDataIn => inst_phyMgmt.smiDataIn,
oSmiDataOut => inst_phyMgmt.smiDataOut,
oSmiDataOutEnable => inst_phyMgmt.smiDataOutEnable,
onPhyReset => inst_phyMgmt.nPhyReset
);
--! The openMAC timer instance provides hardware timers referencing to the
--! openMAC's MAC Time (Mac_Zeit).
THEOPENMACTIMER : entity work.openmacTimer
generic map (
gMacTimeWidth => cMacTimeWidth,
gMacTimer_2ndTimer => cMacTimer_2ndTimer,
gTimerPulseRegWidth => gTimerPulseRegWidth,
gTimerEnablePulseWidth => (gTimerEnablePulseWidth /= cFalse)
)
port map (
iRst => inst_openmacTimer.rst,
iClk => inst_openmacTimer.clk,
iWrite => inst_openmacTimer.write,
iAddress => inst_openmacTimer.address,
iWritedata => inst_openmacTimer.writedata,
oReaddata => inst_openmacTimer.readdata,
iMacTime => inst_openmacTimer.macTime,
oIrq => inst_openmacTimer.interrupt,
oToggle => inst_openmacTimer.toggle
);
---------------------------------------------------------------------------
-- Conditional component instatiations
---------------------------------------------------------------------------
--! Generate address decoders for MAC REG memory map.
GENMACREG_ADDRDEC : for i in cMemMapTable'range generate
THEADDRDEC : entity work.addrDecode
generic map (
gAddrWidth => iMacReg_address'length,
gBaseAddr => cMemMapTable(i).base,
gHighAddr => cMemMapTable(i).high
)
port map (
iEnable => iMacReg_chipselect,
iAddress => iMacReg_address,
oSelect => selVector_macReg(i)
);
end generate GENMACREG_ADDRDEC;
--! Generate write/read acknowlegde for MAC REG, MAC TIMER and PKT BUFFER.
GENMACREG_ACK : for i in cMemAccessDelayTable'range generate
signal selAndWrite : std_logic;
signal selAndRead : std_logic;
signal ackRst : std_logic;
signal ackClk : std_logic;
begin
--! Assign the corresponding clock and reset signals.
ASSIGN_CLKRST : process (
iClk,
iPktBufClk,
iRst,
iPktBufRst
)
begin
-- no defaults, so take care!
case i is
when cMemAccessDelayIndex_pktBuf =>
ackClk <= iPktBufClk;
ackRst <= iPktBufRst;
when cMemAccessDelayIndex_macTimer =>
ackClk <= iClk;
ackRst <= iRst;
when cMemAccessDelayIndex_macReg =>
ackClk <= iClk;
ackRst <= iRst;
when others =>
assert (FALSE)
report "Unknown access delay index. Don't know which ackClk/ackRst to use!"
severity failure;
end case;
end process ASSIGN_CLKRST;
--! This process assigns the selAndWrite and selAndRead signals used
--! to enable the acknowledge generators.
ASSIGN_SELANDRW : process (
iPktBuf_chipselect,
iPktBuf_write,
iPktBuf_read,
iMacTimer_chipselect,
iMacTimer_write,
iMacTimer_read,
iMacReg_chipselect,
iMacReg_write,
iMacReg_read
)
begin
--default
selAndWrite <= cInactivated;
selAndRead <= cInactivated;
case i is
when cMemAccessDelayIndex_pktBuf =>
selAndWrite <= iPktBuf_chipselect and iPktBuf_write;
selAndRead <= iPktBuf_chipselect and iPktBuf_read;
when cMemAccessDelayIndex_macTimer =>
selAndWrite <= iMacTimer_chipselect and iMacTimer_write;
selAndRead <= iMacTimer_chipselect and iMacTimer_read;
when cMemAccessDelayIndex_macReg =>
selAndWrite <= iMacReg_chipselect and iMacReg_write;
selAndRead <= iMacReg_chipselect and iMacReg_read;
when others =>
assert (FALSE)
report "For generate overrun! Check cMemAccessDelayTable!"
severity failure;
end case;
end process ASSIGN_SELANDRW;
--! Generate ack delay for writes.
GENWR_ACKDELAY : if cMemAccessDelayTable(i).write > 0 generate
THE_CNT : entity work.cnt
generic map (
gCntWidth => logDualis(cMemAccessDelayTable(i).write + 1),
gTcntVal => cMemAccessDelayTable(i).write
)
port map (
iArst => ackRst,
iClk => ackClk,
iEnable => selAndWrite,
iSrst => cInactivated,
oCnt => open,
oTcnt => ackVector(i).write
);
end generate GENWR_ACKDELAY;
--! Generate no ack delay for writes.
GENWR_NOACKDELAY : if cMemAccessDelayTable(i).write = 0 generate
ackVector(i).write <= selAndWrite;
end generate GENWR_NOACKDELAY;
--! Generate ack delay for reads.
GENRD_ACKDELAY : if cMemAccessDelayTable(i).read > 0 generate
THE_CNT : entity work.cnt
generic map (
gCntWidth => logDualis(cMemAccessDelayTable(i).read + 1),
gTcntVal => cMemAccessDelayTable(i).read
)
port map (
iArst => ackRst,
iClk => ackClk,
iEnable => selAndRead,
iSrst => cInactivated,
oCnt => open,
oTcnt => ackVector(i).read
);
end generate GENRD_ACKDELAY;
--! generate no ack delay for reads.
GENRD_NOACKDELAY : if cMemAccessDelayTable(i).read = 0 generate
ackVector(i).read <= selAndRead;
end generate GENRD_NOACKDELAY;
end generate GENMACREG_ACK;
--! The openHUB instance is only needed if more than one phy port is
--! configured.
GEN_HUB : if gPhyPortCount > 1 generate
THEOPENHUB : entity work.openhub
generic map (
gPortCount => gPhyPortCount+1 -- plus MAC port
)
port map (
iRst => inst_openhub.rst,
iClk => inst_openhub.clk,
iRx => inst_openhub.rx,
oTx => inst_openhub.tx,
iIntPort => inst_openhub.internPort,
iTxMask => inst_openhub.transmitMask,
oRxPort => inst_openhub.receivePort
);
end generate GEN_HUB;
--! In case of HUB bypass assign inst_openhub although!
GEN_HUBBYPASS : if gPhyPortCount = 1 generate
--! Port number for external phy port
constant cExtPort : natural := cPhyPortLow;
--! Port number for internal MAC port
constant cIntPort : natural := cHubIntPort;
begin
inst_openhub.tx(cExtPort) <= inst_openhub.rx(cIntPort);
inst_openhub.tx(cIntPort) <= inst_openhub.rx(cExtPort);
inst_openhub.receivePort <= cExtPort;
end generate GEN_HUBBYPASS;
--! Generate openFILTER instances for every phy port.
GEN_FILTER : for i in cPhyPortHigh downto cPhyPortLow generate
THEOPENFILTER : entity work.openfilter
port map (
iRst => inst_openfilter.rst,
iClk => inst_openfilter.clk,
iRx => inst_openfilter.rxIn(i),
oRx => inst_openfilter.rxOut(i),
iTx => inst_openfilter.txIn(i),
oTx => inst_openfilter.txOut(i),
iRxError => inst_openfilter.rxError(i)
);
end generate GEN_FILTER;
--! Generate MII signals for every phy port. Note that this includes
--! the RMII-to-MII converter.
GEN_MII : if gPhyPortType = cPhyPortMii generate
GEN_CONVERTER : for i in cPhyPortHigh downto cPhyPortLow generate
-- convert phy port to filter index range
miiTxPath(i-cHubIntPort-1) <= inst_convRmiiToMii.miiTx(i);
THERMII2MIICONVERTER : entity work.convRmiiToMii
port map (
iRst => inst_convRmiiToMii.rst,
iClk => inst_convRmiiToMii.clk,
iRmiiTx => inst_convRmiiToMii.rmiiTx(i),
oRmiiRx => inst_convRmiiToMii.rmiiRx(i),
iMiiRxClk => inst_convRmiiToMii.miiRxClk(i),
iMiiRx => inst_convRmiiToMii.miiRx(i),
iMiiRxError => inst_convRmiiToMii.miiRxError(i),
iMiiTxClk => inst_convRmiiToMii.miiTxClk(i),
oMiiTx => inst_convRmiiToMii.miiTx(i)
);
end generate GEN_CONVERTER;
end generate GEN_MII;
--! Generate RMII signals for every phy port. The Rx path is latched with
--! iClk and the Tx path is lactehd with iClk2x.
GEN_RMII : if gPhyPortType = cPhyPortRmii generate
--! Latch Rx signals before they come to internals.
LATCHRXPATH : process(iRst, iClk)
begin
if iRst = cActivated then
rmiiRxPathError_reg <= (others => cInactivated);
rmiiRxPath_reg <= (others => cRmiiPathInit);
elsif rising_edge(iClk) then
rmiiRxPathError_reg <= iRmii_RxError;
rmiiRxPath_reg <= iRmii_Rx;
end if;
end process LATCHRXPATH;
--! Latch Tx signals with falling edge before they leave.
LATCHTXPATH : process(iRst, iClk2x)
begin
if iRst = cActivated then
rmiiTxPath_reg <= (others => cRmiiPathInit);
elsif falling_edge(iClk2x) then
-- convert phy port to filter index range
for i in gPhyPortCount-1 downto 0 loop
rmiiTxPath_reg(i) <= inst_openfilter.txOut(i+cPhyPortLow);
end loop;
end if;
end process LATCHTXPATH;
end generate GEN_RMII;
--! Generate PACKET BUFFER DPRAM if Rx or Tx packets are stored localy.
GEN_PKTBUFFER : if (gPacketBufferLocTx = cPktBufLocal or
gPacketBufferLocRx = cPktBufLocal) generate
--! Packet buffer number of words (e.g. 1024 byte => 256 dword)
constant cNumberOfWords : natural := 2**(gPacketBufferLog2Size - logDualis(cPktBufDataWidth/cByteLength));
--! DMA path reset
signal dmaRst : std_logic;
--! DMA path clock
signal dmaClk : std_logic;
begin
--! This is the packet buffer DPRAM storing Tx and/or Rx packets.
--! Port A is connected to the openMAC DMA and port B is connected to
--! the memory mapped slave port (host).
THEPKTBUF : entity work.dpRam
generic map (
gWordWidth => cPktBufDataWidth,
gNumberOfWords => cNumberOfWords,
gInitFile => "UNUSED"
)
port map (
iClk_A => inst_pktBuffer.dma.clk,
iEnable_A => inst_pktBuffer.dma.enable,
iWriteEnable_A => inst_pktBuffer.dma.write,
iAddress_A => inst_pktBuffer.dma.address,
iByteenable_A => inst_pktBuffer.dma.byteenable,
iWritedata_A => inst_pktBuffer.dma.writedata,
oReaddata_A => inst_pktBuffer.dma.readdata,
iClk_B => inst_pktBuffer.host.clk,
iEnable_B => inst_pktBuffer.host.enable,
iWriteEnable_B => inst_pktBuffer.host.write,
iByteenable_B => inst_pktBuffer.host.byteenable,
iAddress_B => inst_pktBuffer.host.address,
iWritedata_B => inst_pktBuffer.host.writedata,
oReaddata_B => inst_pktBuffer.host.readdata
);
dmaRst <= inst_pktBuffer.dma.rst;
dmaClk <= inst_pktBuffer.dma.clk;
--! This process generates the DMA acknowlegde pulse. It is generated
--! for read and/or write requests with same delay.
DMAACKPULSE : process(dmaRst, dmaClk)
begin
if dmaRst = cActivated then
inst_pktBuffer.dma_ack <= cInactivated;
elsif rising_edge(dmaClk) then
-- generate pulse => default
inst_pktBuffer.dma_ack <= cInactivated;
if (inst_openmac.dma_request = cActivated and
inst_pktBuffer.dma_ack = cInactivated) then
-- Check if it is a write or read
if inst_openmac.nDma_write = cnActivated then
-- It is a write (Rx packet), check generic...
if gPacketBufferLocRx = cPktBufLocal then
inst_pktBuffer.dma_ack <= cActivated;
end if;
else
-- It is a read (Tx packet), check generic...
if gPacketBufferLocTx = cPktBufLocal then
inst_pktBuffer.dma_ack <= cActivated;
end if;
end if;
end if;
end if;
end process DMAACKPULSE;
--! This process stores the DMA high word select for DMA read path.
--! Note: This workaround is needed since data is latched after dma ack.
DMAHIGHWORDSEL : process(dmaRst, dmaClk)
begin
if dmaRst = cActivated then
inst_pktBuffer.dma_highWordSel <= cInactivated;
elsif rising_edge(dmaClk) then
if inst_openmac.dma_request = cActivated and inst_openmac.nDma_write = cnInactivated then
inst_pktBuffer.dma_highWordSel <= inst_openmac.dma_address(1);
end if;
end if;
end process DMAHIGHWORDSEL;
end generate GEN_PKTBUFFER;
--! Generate DMA Master instances if Rx or Tx packets are stored externally.
GEN_DMAMASTER : if (gPacketBufferLocTx = cPktBufExtern or
gPacketBufferLocRx = cPktBufExtern) generate
--! This is the DMA master handling the Tx and/or Rx packet transfers
--! to/from the interconnect.
THEDMAMASTER: entity work.openMAC_DMAmaster
generic map (
dma_highadr_g => gDmaAddrWidth-1,
fifo_data_width_g => gDmaDataWidth,
gen_dma_observer_g => (gEnableDmaObserver /= cFalse),
gen_rx_fifo_g => (gPacketBufferLocRx = cPktBufExtern),
gen_tx_fifo_g => (gPacketBufferLocTx = cPktBufExtern),
m_burstcount_const_g => TRUE, --TODO: check if okay
m_burstcount_width_g => gDmaBurstCountWidth,
m_rx_burst_size_g => gDmaWriteBurstLength,
rx_fifo_word_size_g => gDmaWriteFifoLength,
m_tx_burst_size_g => gDmaReadBurstLength,
tx_fifo_word_size_g => gDmaReadFifoLength,
simulate => FALSE
)
port map (
dma_clk => inst_dmaMaster.dma.clk,
rst => inst_dmaMaster.dma.rst,
dma_req_wr => inst_dmaMaster.dma.reqWrite,
dma_req_rd => inst_dmaMaster.dma.reqRead,
dma_req_overflow => inst_dmaMaster.dma.reqOverflow,
dma_ack_wr => inst_dmaMaster.dma.ackWrite,
dma_ack_rd => inst_dmaMaster.dma.ackRead,
dma_rd_err => inst_dmaMaster.dma.readError,
dma_rd_len => inst_dmaMaster.dma.readLength,
dma_wr_err => inst_dmaMaster.dma.writeError,
dma_addr => inst_dmaMaster.dma.address,
dma_dout => inst_dmaMaster.dma.writedata,
dma_din => inst_dmaMaster.dma.readdata,
m_clk => inst_dmaMaster.master.clk,
--FIXME: m_rst => inst_dmaMaster.master.rst,
m_write => inst_dmaMaster.master.write,
m_read => inst_dmaMaster.master.read,
m_readdatavalid => inst_dmaMaster.master.readdatavalid,
m_waitrequest => inst_dmaMaster.master.waitrequest,
m_address => inst_dmaMaster.master.address,
m_byteenable => inst_dmaMaster.master.byteenable,
m_burstcount => inst_dmaMaster.master.burstcount,
m_burstcounter => inst_dmaMaster.master.burstcounter,
m_writedata => inst_dmaMaster.master.writedata,
m_readdata => inst_dmaMaster.master.readdata,
mac_rx_off => inst_dmaMaster.mac_rxOff,
mac_tx_off => inst_dmaMaster.mac_txOff
);
end generate GEN_DMAMASTER;
--! Generate MAC activity, which can be used for LED control.
GEN_ACTIVITY : if gEnableActivity = cTrue generate
--! The activity generate uses the Tx enable and Rx data valid signal
--! to detect a packet run.
THEACTIVITY : entity work.phyActGen
generic map (
gActivityFreq => cActivityFreq,
gClkFreq => cClkFreq
)
port map (
iRst => inst_activity.rst,
iClk => inst_activity.clk,
iTxEnable => inst_activity.txEnable,
iRxValid => inst_activity.rxDataValid,
oActivity => inst_activity.activity
);
end generate GEN_ACTIVITY;
end rtl;
| gpl-2.0 | 0d63b55e22bcd76b0b76b4a8e88ee3ee | 0.509107 | 5.27911 | false | false | false | false |
Kalycito-open-automation/openPOWERLINK_V2_old_25-06-2014 | hardware/ipcore/common/fifo/src/asyncFifo-rtl-a.vhd | 2 | 9,706 | -------------------------------------------------------------------------------
--! @file asyncFifo-rtl-a.vhd
--
--! @brief The asynchronous Fifo architecture.
--
--! @details This is a generic dual clocked FIFO using the dpRam component as
--! memory.
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2013
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
--! use global library
use work.global.all;
architecture rtl of asyncFifo is
--! Address width
constant cAddrWidth : natural := logDualis(gWordSize);
--! Type for DPRAM port commons
type tDpramPortCommon is record
clk : std_logic;
enable : std_logic;
address : std_logic_vector(cAddrWidth-1 downto 0);
end record;
--! Type for DPRAM port assignment
type tDpramPort is record
wrPort : tDpramPortCommon;
rdPort : tDpramPortCommon;
write : std_logic;
writedata : std_logic_vector(gDataWidth-1 downto 0);
readdata : std_logic_vector(gDataWidth-1 downto 0);
end record;
--! Type for control port
type tControlPort is record
clk : std_logic;
rst : std_logic;
request : std_logic;
otherPointer : std_logic_vector(cAddrWidth downto 0);
empty : std_logic;
full : std_logic;
pointer : std_logic_vector(cAddrWidth downto 0);
address : std_logic_vector(cAddrWidth-1 downto 0);
usedWord : std_logic_vector(cAddrWidth-1 downto 0);
end record;
--! Type for pointer synchronizers
type tPointerSyncPort is record
clk : std_logic;
rst : std_logic;
din : std_logic_vector(cAddrWidth downto 0);
dout : std_logic_vector(cAddrWidth downto 0);
end record;
--! DPRAM instance
signal inst_dpram : tDpramPort;
--! Write controller instance
signal inst_writeCtrl : tControlPort;
--! Read controller instance
signal inst_readCtrl : tControlPort;
--! Write pointer synchronizer instance
signal inst_writeSync : tPointerSyncPort;
--! Read pointer synchronizer instance
signal inst_readSync : tPointerSyncPort;
begin
assert (gMemRes = "ON")
report "This FIFO implementation only supports memory resources!"
severity warning;
---------------------------------------------------------------------------
-- Assign Outputs
---------------------------------------------------------------------------
-- Write port
oWrEmpty <= inst_writeCtrl.empty;
oWrFull <= inst_writeCtrl.full;
oWrUsedw <= inst_writeCtrl.usedWord;
-- Read port
oRdEmpty <= inst_readCtrl.empty;
oRdFull <= inst_readCtrl.full;
oRdUsedw <= inst_readCtrl.usedWord;
oRdData <= inst_dpram.readdata;
---------------------------------------------------------------------------
-- Map DPRAM instance
---------------------------------------------------------------------------
-- Write port
inst_dpram.wrPort.clk <= iWrClk;
inst_dpram.wrPort.enable <= inst_writeCtrl.request;
inst_dpram.write <= inst_writeCtrl.request;
inst_dpram.wrPort.address <= inst_writeCtrl.address;
inst_dpram.writedata <= iWrData;
-- Read port
inst_dpram.rdPort.clk <= iRdClk;
inst_dpram.rdPort.enable <= iRdReq;
inst_dpram.rdPort.address <= inst_readCtrl.address;
---------------------------------------------------------------------------
-- Map Write and Read controller instance
---------------------------------------------------------------------------
inst_readCtrl.clk <= iRdClk;
inst_readCtrl.rst <= iAclr;
inst_readCtrl.request <= iRdReq;
inst_readCtrl.otherPointer <= inst_writeSync.dout;
inst_writeCtrl.clk <= iWrClk;
inst_writeCtrl.rst <= iAclr;
inst_writeCtrl.request <= iWrReq and not inst_writeCtrl.full;
inst_writeCtrl.otherPointer <= inst_readSync.dout;
---------------------------------------------------------------------------
-- Map pointer synchronizers
---------------------------------------------------------------------------
inst_readSync.rst <= iAclr;
inst_readSync.clk <= iWrClk; -- synchronize read pointer to write clock
inst_readSync.din <= inst_readCtrl.pointer;
inst_writeSync.rst <= iAclr;
inst_writeSync.clk <= iRdClk; -- synchronize write pointer to read clock
inst_writeSync.din <= inst_writeCtrl.pointer;
---------------------------------------------------------------------------
-- Instances
---------------------------------------------------------------------------
--! This is the FIFO read controller.
FIFO_READ_CONTROL : entity work.fifoRead
generic map (
gAddrWidth => cAddrWidth
)
port map (
iClk => inst_readCtrl.clk,
iRst => inst_readCtrl.rst,
iRead => inst_readCtrl.request,
iWrPointer => inst_readCtrl.otherPointer,
oEmpty => inst_readCtrl.empty,
oFull => inst_readCtrl.full,
oPointer => inst_readCtrl.pointer,
oAddress => inst_readCtrl.address,
oUsedWord => inst_readCtrl.usedWord
);
--! This is the FIFO write controller.
FIFO_WRITE_CONTROL : entity work.fifoWrite
generic map (
gAddrWidth => cAddrWidth
)
port map (
iClk => inst_writeCtrl.clk,
iRst => inst_writeCtrl.rst,
iWrite => inst_writeCtrl.request,
iRdPointer => inst_writeCtrl.otherPointer,
oEmpty => inst_writeCtrl.empty,
oFull => inst_writeCtrl.full,
oPointer => inst_writeCtrl.pointer,
oAddress => inst_writeCtrl.address,
oUsedWord => inst_writeCtrl.usedWord
);
--! This is the FIFO buffer.
FIFO_BUFFER : entity work.dpRamSplxNbe
generic map (
gWordWidth => gDataWidth,
gNumberOfWords => gWordSize,
gInitFile => "UNUSED"
)
port map (
iClk_A => inst_dpram.wrPort.clk,
iEnable_A => inst_dpram.wrPort.enable,
iWriteEnable_A => inst_dpram.write,
iAddress_A => inst_dpram.wrPort.address,
iWritedata_A => inst_dpram.writedata,
iClk_B => inst_dpram.rdPort.clk,
iEnable_B => inst_dpram.rdPort.enable,
iAddress_B => inst_dpram.rdPort.address,
oReaddata_B => inst_dpram.readdata
);
--! This generate block instantiates multiple synchrinizers to transfer
--! the write and read pointers to the opposite clock domains.
GEN_POINTERSYNC : for i in cAddrWidth downto 0 generate
WRITESYNC : entity work.synchronizer
generic map (
gStages => gSyncStages,
gInit => cInactivated
)
port map (
iArst => inst_writeSync.rst,
iClk => inst_writeSync.clk,
iAsync => inst_writeSync.din(i),
oSync => inst_writeSync.dout(i)
);
READSYNC : entity work.synchronizer
generic map (
gStages => gSyncStages,
gInit => cInactivated
)
port map (
iArst => inst_readSync.rst,
iClk => inst_readSync.clk,
iAsync => inst_readSync.din(i),
oSync => inst_readSync.dout(i)
);
end generate GEN_POINTERSYNC;
end rtl;
| gpl-2.0 | 52bb0c6d029e1d8a87012a08d0839e5f | 0.535339 | 4.904497 | false | false | false | false |
Kalycito-open-automation/openPOWERLINK_V2_old_25-06-2014 | hardware/ipcore/common/openmac/src/convRmiiToMii-rtl-ea.vhd | 2 | 11,063 | -------------------------------------------------------------------------------
--! @file convRmiiToMii-rtl-ea.vhd
--
--! @brief RMII-to-MII converter
--
--! @details This is an RMII-to-MII converter to convert MII phy traces to RMII.
--! Example: MII PHY <--> RMII-to-MII converter <--> RMII MAC
-------------------------------------------------------------------------------
--
-- (c) B&R, 2013
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
--! use global library
use work.global.all;
--! use openmac package
use work.openmacPkg.all;
entity convRmiiToMii is
port (
--! Reset
iRst : in std_logic;
--! RMII Clock
iClk : in std_logic;
--! RMII transmit path
iRmiiTx : in tRmiiPath;
--! RMII receive path
oRmiiRx : out tRmiiPath;
--! MII receive clock
iMiiRxClk : in std_logic;
--! MII receive path
iMiiRx : in tMiiPath;
--! MII receive error
iMiiRxError : in std_logic;
--! MII transmit clock
iMiiTxClk : in std_logic;
--! MII transmit path
oMiiTx : out tMiiPath
);
end convRmiiToMii;
architecture rtl of convRmiiToMii is
constant DIBIT_SIZE : integer := 2;
constant NIBBLE_SIZE : integer := 4;
begin
TX_BLOCK : block
--fifo size must not be larger than 2**5
constant FIFO_NIBBLES_LOG2 : integer := 5;
signal fifo_half, fifo_full, fifo_empty, fifo_valid, txEnable_reg, fifo_wrempty : std_logic;
signal fifo_wr, fifo_rd : std_logic;
signal fifo_din : std_logic_vector(NIBBLE_SIZE-1 downto 0);
signal fifo_dout, txData_reg : std_logic_vector(NIBBLE_SIZE-1 downto 0);
signal fifo_rdUsedWord : std_logic_vector (FIFO_NIBBLES_LOG2-1 downto 0);
signal fifo_wrUsedWord : std_logic_vector (FIFO_NIBBLES_LOG2-1 downto 0);
--necessary for clr fifo
signal aclr, rTxEn_l : std_logic;
--convert dibits to nibble
signal sel_dibit : std_logic;
signal fifo_din_reg : std_logic_vector(iRmiiTx.data'range);
begin
fifo_din <= iRmiiTx.data & fifo_din_reg;
fifo_wr <= sel_dibit;
--convert dibits to nibble (to fit to fifo)
process(iClk, iRst)
begin
if iRst = cActivated then
sel_dibit <= cInactivated;
fifo_din_reg <= (others => cInactivated);
elsif iClk = cActivated and iClk'event then
if iRmiiTx.enable = cActivated then
sel_dibit <= not sel_dibit;
if sel_dibit = cInactivated then
fifo_din_reg <= iRmiiTx.data;
end if;
else
sel_dibit <= cInactivated;
end if;
end if;
end process;
fifo_half <= fifo_rdUsedWord(fifo_rdUsedWord'left);
oMiiTx.data <= txData_reg;
oMiiTx.enable <= txEnable_reg;
process(iMiiTxClk, iRst)
begin
if iRst = cActivated then
fifo_rd <= cInactivated;
fifo_valid <= cInactivated;
txData_reg <= (others => cInactivated);
txEnable_reg <= cInactivated;
elsif iMiiTxClk = cActivated and iMiiTxClk'event then
txData_reg <= fifo_dout;
txEnable_reg <= fifo_valid;
if fifo_rd = cInactivated and fifo_half = cActivated then
fifo_rd <= cActivated;
elsif fifo_rd = cActivated and fifo_empty = cActivated then
fifo_rd <= cInactivated;
end if;
if fifo_rd = cActivated and fifo_rdUsedWord > std_logic_vector(to_unsigned(1, fifo_rdUsedWord'length)) then
fifo_valid <= cActivated;
else
fifo_valid <= cInactivated;
end if;
end if;
end process;
--! This is the asynchronous FIFO used to decouple RMII from MII.
TXFIFO : entity work.asyncFifo
generic map (
gDataWidth => NIBBLE_SIZE,
gWordSize => 2**FIFO_NIBBLES_LOG2,
gSyncStages => 2,
gMemRes => "ON"
)
port map (
iAclr => aclr,
iWrClk => iClk,
iWrReq => fifo_wr,
iWrData => fifo_din,
oWrEmpty => fifo_wrempty,
oWrFull => fifo_full,
oWrUsedw => fifo_wrUsedWord,
iRdClk => iMiiTxClk,
iRdReq => fifo_rd,
oRdData => fifo_dout,
oRdEmpty => fifo_empty,
oRdFull => open,
oRdUsedw => fifo_rdUsedWord
);
--sync Mii Tx En (=fifo_valid) to wr clk
process(iClk, iRst)
begin
if iRst = cActivated then
aclr <= cActivated; --reset fifo
rTxEn_l <= cInactivated;
elsif iClk = cActivated and iClk'event then
rTxEn_l <= iRmiiTx.enable;
aclr <= cInactivated; --default
--clear the full fifo after TX on RMII side is done
if fifo_full = cActivated and rTxEn_l = cActivated and iRmiiTx.enable = cInactivated then
aclr <= cActivated;
end if;
end if;
end process;
end block;
RX_BLOCK : block
--fifo size must not be larger than 2**5
constant FIFO_NIBBLES_LOG2 : integer := 5;
signal fifo_half, fifo_full, fifo_empty, fifo_valid : std_logic;
signal rxDataValid_reg, fifo_rd : std_logic;
signal rxError_reg : std_logic;
signal fifo_wr : std_logic;
signal rxData_reg : std_logic_vector(NIBBLE_SIZE-1 downto 0);
signal fifo_dout : std_logic_vector(NIBBLE_SIZE-1 downto 0);
signal fifo_rdUsedWord : std_logic_vector(FIFO_NIBBLES_LOG2-1 downto 0);
signal fifo_wrUsedWord : std_logic_vector(FIFO_NIBBLES_LOG2-1 downto 0);
--convert nibble to dibits
signal sel_dibit : std_logic;
signal fifo_rd_s : std_logic;
begin
process(iMiiRxClk, iRst)
begin
if iRst = cActivated then
rxData_reg <= (others => cInactivated);
rxDataValid_reg <= cInactivated;
rxError_reg <= cInactivated;
elsif iMiiRxClk = cActivated and iMiiRxClk'event then
rxData_reg <= iMiiRx.data;
rxDataValid_reg <= iMiiRx.enable;
rxError_reg <= iMiiRxError;
end if;
end process;
fifo_wr <= rxDataValid_reg and not rxError_reg;
oRmiiRx.data <= fifo_dout(fifo_dout'right+1 downto 0) when sel_dibit = cActivated else
fifo_dout(fifo_dout'left downto fifo_dout'left-1);
oRmiiRx.enable <= fifo_valid;
fifo_rd <= fifo_rd_s and not sel_dibit;
process(iClk, iRst)
begin
if iRst = cActivated then
sel_dibit <= cInactivated;
elsif iClk = cActivated and iClk'event then
if fifo_rd_s = cActivated or fifo_valid = cActivated then
sel_dibit <= not sel_dibit;
else
sel_dibit <= cInactivated;
end if;
end if;
end process;
fifo_half <= fifo_rdUsedWord(fifo_rdUsedWord'left);
process(iClk, iRst)
begin
if iRst = cActivated then
fifo_rd_s <= cInactivated;
fifo_valid <= cInactivated;
elsif iClk = cActivated and iClk'event then
if fifo_rd_s = cInactivated and fifo_half = cActivated then
fifo_rd_s <= cActivated;
elsif fifo_rd_s = cActivated and fifo_empty = cActivated then
fifo_rd_s <= cInactivated;
end if;
if fifo_rd_s = cActivated then
fifo_valid <= cActivated;
else
fifo_valid <= cInactivated;
end if;
end if;
end process;
--! This is the asynchronous FIFO used to decouple RMII from MII.
RXFIFO : entity work.asyncFifo
generic map (
gDataWidth => NIBBLE_SIZE,
gWordSize => 2**FIFO_NIBBLES_LOG2,
gSyncStages => 2,
gMemRes => "ON"
)
port map (
iAclr => iRst,
iWrClk => iMiiRxClk,
iWrReq => fifo_wr,
iWrData => rxData_reg,
oWrEmpty => open,
oWrFull => fifo_full,
oWrUsedw => fifo_wrUsedWord,
iRdClk => iClk,
iRdReq => fifo_rd,
oRdData => fifo_dout,
oRdEmpty => fifo_empty,
oRdFull => open,
oRdUsedw => fifo_rdUsedWord
);
end block;
end rtl;
| gpl-2.0 | 6a82a2c90693ffa046cf19604895eb1c | 0.530326 | 4.71167 | false | false | false | false |
bangonkali/quartus-sockit | soc_system/synthesis/submodules/alt_vipvfr131_common_logic_fifo.vhd | 2 | 5,022 | -- Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
-- use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any
-- output files any of the foregoing (including device programming or
-- simulation files), and any associated documentation or information are
-- expressly subject to the terms and conditions of the Altera Program
-- License Subscription Agreement or other applicable license agreement,
-- including, without limitation, that your use is for the sole purpose
-- of programming logic devices manufactured by Altera and sold by Altera
-- or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.alt_vipvfr131_common_package.all;
entity alt_vipvfr131_common_logic_fifo is
generic
(
WIDTH : integer := 8;
DEPTH : integer := 3
);
port
(
-- clock, enable and reset
clock : in std_logic;
rdena : in std_logic := '1';
wrena : in std_logic := '1';
reset : in std_logic;
-- information signals from the fifo (write side)
wrusedw : out std_logic_vector(wide_enough_for(DEPTH) - 1 downto 0);
full : out std_logic;
almost_full : out std_logic;
-- information signals from the fifo (read side)
rdusedw : out std_logic_vector(wide_enough_for(DEPTH) - 1 downto 0);
empty : out std_logic;
almost_empty : out std_logic;
-- getting data into the fifo
wrreq : in std_logic;
data : in std_logic_vector(WIDTH - 1 downto 0);
-- ...and back out again
rdreq : in std_logic;
q : out std_logic_vector(WIDTH - 1 downto 0)
);
end entity;
architecture rtl of alt_vipvfr131_common_logic_fifo is
constant USEDW_WIDTH : integer := wide_enough_for(DEPTH);
-- the number of words in the fifo
-- also indicates where the next write should go
signal wrusedw_for_internal_use : unsigned(USEDW_WIDTH - 1 downto 0) := (others => '0');
signal wrusedw_for_internal_use_slv : std_logic_vector(USEDW_WIDTH - 1 downto 0) := (others => '0');
-- shift register, to actually store the fifo data
type shift_register_type is array(integer range <>) of std_logic_vector(WIDTH - 1 downto 0);
signal shift_register : shift_register_type(DEPTH - 1 downto 0);
-- rather than using the clock enables as clock enables, we use them as enables
-- on the two signals, rdreq and wrreq, since these are the only signals which actually
-- cause the fifo to do anything
signal enabled_rdreq, enabled_wrreq : std_logic;
begin
-- check generics
assert DEPTH > 0
report "Generic DEPTH must greater than zero"
severity ERROR;
assert WIDTH > 0
report "Generic WIDTH must greater than zero"
severity ERROR;
-- instantiate a standard usedw calculator to do the usedw, empty etc. updating
usedw_calculator : alt_vipvfr131_common_fifo_usedw_calculator
generic map
(
WIDTH => USEDW_WIDTH,
DEPTH => DEPTH,
CLOCKS_ARE_SAME => TRUE,
READ_TO_WRITE_DELAY => 0,
WRITE_TO_READ_DELAY => 0
)
port map
(
rdclock => clock,
wrclock => clock,
rdena => rdena,
wrena => wrena,
reset => reset,
wrreq => wrreq,
rdreq => rdreq,
wrusedw => wrusedw_for_internal_use_slv,
full => full,
almost_full => almost_full,
rdusedw => rdusedw,
empty => empty,
almost_empty => almost_empty
);
-- the logic below needs access to the wrusedw value, so this cannot be direcly connected out
wrusedw_for_internal_use <= unsigned(wrusedw_for_internal_use_slv);
wrusedw <= wrusedw_for_internal_use_slv;
-- rather than using the clock enables as clock enables, we use them as enables
-- on the two signals, rdreq and wrreq, since these are the only signals which actually
-- cause the fifo to do anything
enabled_rdreq <= rdreq and rdena;
enabled_wrreq <= wrreq and wrena;
-- a shift register, containing DEPTH words each of
-- which is WIDTH bits wide
process (clock, reset)
begin
if reset = '1' then
shift_register <= (others => dead_bits(WIDTH));
elsif clock'EVENT and clock = '1' then
for i in 0 to DEPTH - 1 loop
-- each word in the fifo will do one of three
-- things:
-- 1. take the contents of data int
if enabled_wrreq = '1' and ((enabled_rdreq = '1' and wrusedw_for_internal_use = i + 1)
or (enabled_rdreq = '0' and wrusedw_for_internal_use = i)) then
shift_register(i) <= data;
-- 2. take the word from the previous element in the
-- shift register (or all 1s for nothing)
elsif enabled_rdreq = '1' then
if i < DEPTH - 1 then
shift_register(i) <= shift_register(i + 1);
else
shift_register(i) <= dead_bits(WIDTH);
end if;
end if;
-- 3. hold its value
end loop;
end if;
end process;
q <= shift_register(0);
end architecture rtl;
| mit | 779c91845d3948123da2e13d32a4abfe | 0.668857 | 3.514346 | false | false | false | false |
sergev/vak-opensource | hardware/dlx/dlx_instr-body.vhdl | 1 | 10,542 | --------------------------------------------------------------------------
--
-- Copyright (C) 1993, Peter J. Ashenden
-- Mail: Dept. Computer Science
-- University of Adelaide, SA 5005, Australia
-- e-mail: [email protected]
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 1, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
--------------------------------------------------------------------------
--
-- $RCSfile: dlx_instr-body.vhdl,v $ $Revision: 2.1 $ $Date: 1993/10/31 22:35:21 $
--
--------------------------------------------------------------------------
--
-- Package body for DLX instructions
--
use std.textio.all,
work.bv_arithmetic.bv_to_natural,
work.bv_arithmetic.bv_to_integer;
package body dlx_instr is
constant opcode_names : opcode_name_array :=
( "SPECIAL ", "FPARITH ", "J ", "JAL ",
"BEQZ ", "BNEZ ", "BFPT ", "BFPF ",
"ADDI ", "ADDUI ", "SUBI ", "SUBUI ",
"ANDI ", "ORI ", "XORI ", "LHI ",
"RFE ", "TRAP ", "JR ", "JALR ",
"SLLI ", "UNDEF_15", "SRLI ", "SRAI ",
"SEQI ", "SNEI ", "SLTI ", "SGTI ",
"SLEI ", "SGEI ", "UNDEF_1E", "UNDEF_1F",
"LB ", "LH ", "UNDEF_22", "LW ",
"LBU ", "LHU ", "LF ", "LD ",
"SB ", "SH ", "UNDEF_2A", "SW ",
"UNDEF_2C", "UNDEF_2D", "SF ", "SD ",
"SEQUI ", "SNEUI ", "SLTUI ", "SGTUI ",
"SLEUI ", "SGEUI ", "UNDEF_36", "UNDEF_37",
"UNDEF_38", "UNDEF_39", "UNDEF_3A", "UNDEF_3B",
"UNDEF_3C", "UNDEF_3D", "UNDEF_3E", "UNDEF_3F" );
constant sp_func_names : sp_func_name_array :=
( "NOP ", "UNDEF_01", "UNDEF_02", "UNDEF_03",
"SLL ", "UNDEF_05", "SRL ", "SRA ",
"UNDEF_08", "UNDEF_09", "UNDEF_0A", "UNDEF_0B",
"UNDEF_0C", "UNDEF_0D", "UNDEF_0E", "UNDEF_0F",
"SEQU ", "SNEU ", "SLTU ", "SGTU ",
"SLEU ", "SGEU ", "UNDEF_16", "UNDEF_17",
"UNDEF_18", "UNDEF_19", "UNDEF_1A", "UNDEF_1B",
"UNDEF_1C", "UNDEF_1D", "UNDEF_1E", "UNDEF_1F",
"ADD ", "ADDU ", "SUB ", "SUBU ",
"AND ", "OR ", "XOR ", "UNDEF_27",
"SEQ ", "SNE ", "SLT ", "SGT ",
"SLE ", "SGE ", "UNDEF_2E", "UNDEF_2F",
"MOVI2S ", "MOVS2I ", "MOVF ", "MOVD ",
"MOVFP2I ", "MOVI2FP ", "UNDEF_36", "UNDEF_37",
"UNDEF_38", "UNDEF_39", "UNDEF_3A", "UNDEF_3B",
"UNDEF_3C", "UNDEF_3D", "UNDEF_3E", "UNDEF_3F" );
constant fp_func_names : fp_func_name_array :=
( "ADDF ", "SUBF ", "MULTF ", "DIVF ",
"ADDD ", "SUBD ", "MULTD ", "DIVD ",
"CVTF2D ", "CVTF2I ", "CVTD2F ", "CVTD2I ",
"CVTI2F ", "CVTI2D ", "MULT ", "DIV ",
"EQF ", "NEF ", "LTF ", "GTF ",
"LEF ", "GEF ", "MULTU ", "DIVU ",
"EQD ", "NED ", "LTD ", "GTD ",
"LED ", "GED ", "UNDEF_1E", "UNDEF_1F" );
procedure write_reg (L : inout line; reg : reg_index) is
begin
write(L, 'R');
write(L, reg);
end write_reg;
procedure write_freg (L : inout line; freg : reg_index) is
begin
write(L, 'F');
write(L, freg);
end write_freg;
procedure write_special_reg (L : inout line; reg : reg_index) is
begin
case reg is
when 0 =>
write(L, string'("IAR"));
WHEN 1 =>
write(L, string'("FSR"));
when others =>
write(L, string'("SR"));
write(L, reg);
end case;
end write_special_reg;
procedure write_instr (L : inout line; instr : in dlx_word) is
alias instr_opcode : dlx_opcode is instr(0 to 5);
alias instr_sp_func : dlx_sp_func is instr(26 to 31);
alias instr_fp_func : dlx_fp_func is instr(27 to 31);
alias instr_rs1 : dlx_reg_addr is instr(6 to 10);
alias instr_rs2 : dlx_reg_addr is instr(11 to 15);
alias instr_Itype_rd : dlx_reg_addr is instr(11 to 15);
alias instr_Rtype_rd : dlx_reg_addr is instr(16 to 20);
alias instr_immed16 : dlx_immed16 is instr(16 to 31);
alias instr_immed26 : dlx_immed26 is instr(6 to 31);
variable instr_opcode_num : dlx_opcode_num;
variable instr_sp_func_num : dlx_sp_func_num;
variable instr_fp_func_num : dlx_fp_func_num;
variable rs1 : reg_index;
variable rs2 : reg_index;
variable Itype_rd : reg_index;
variable Rtype_rd : reg_index;
begin
instr_opcode_num := bv_to_natural(instr_opcode);
instr_sp_func_num := bv_to_natural(instr_sp_func);
instr_fp_func_num := bv_to_natural(instr_fp_func);
rs1 := bv_to_natural(instr_rs1);
rs2 := bv_to_natural(instr_rs2);
Itype_rd := bv_to_natural(instr_Itype_rd);
Rtype_rd := bv_to_natural(instr_Rtype_rd);
--
if (instr_opcode /= op_special) and (instr_opcode /= op_fparith) then
write(L, opcode_names(instr_opcode_num));
write(L, ' ');
end if;
case instr_opcode is
when op_special =>
write(L, sp_func_names(instr_sp_func_num));
write(L, ' ');
case instr_sp_func is
when sp_func_nop =>
null;
when sp_func_sll | sp_func_srl | sp_func_sra |
sp_func_sequ | sp_func_sneu | sp_func_sltu |
sp_func_sgtu | sp_func_sleu | sp_func_sgeu |
sp_func_add | sp_func_addu | sp_func_sub | sp_func_subu |
sp_func_and | sp_func_or | sp_func_xor |
sp_func_seq | sp_func_sne | sp_func_slt |
sp_func_sgt | sp_func_sle | sp_func_sge =>
write_reg(L, Rtype_rd); write(L, string'(", "));
write_reg(L, rs1); write(L, string'(", "));
write_reg(L, rs2);
when sp_func_movi2s =>
write_special_reg(L, Rtype_rd); write(L, string'(", "));
write_reg(L, rs1);
when sp_func_movs2i =>
write_reg(L, Rtype_rd); write(L, string'(", "));
write_special_reg(L, rs1);
when sp_func_movf | sp_func_movd =>
write_freg(L, Rtype_rd); write(L, string'(", "));
write_freg(L, rs1);
when sp_func_movfp2i =>
write_reg(L, Rtype_rd); write(L, string'(", "));
write_freg(L, rs1);
when sp_func_movi2fp =>
write_freg(L, Rtype_rd); write(L, string'(", "));
write_reg(L, rs1);
when others =>
null;
end case;
when op_fparith =>
write(L, fp_func_names(instr_fp_func_num));
write(L, ' ');
case instr_fp_func is
when fp_func_addf | fp_func_subf | fp_func_multf | fp_func_divf |
fp_func_addd | fp_func_subd | fp_func_multd | fp_func_divd |
fp_func_mult | fp_func_div | fp_func_multu | fp_func_divu =>
write_freg(L, Rtype_rd); write(L, string'(", "));
write_freg(L, rs1); write(L, string'(", "));
write_freg(L, rs2);
when fp_func_cvtf2d | fp_func_cvtd2f =>
write_freg(L, Rtype_rd); write(L, string'(", "));
write_freg(L, rs1);
when fp_func_cvtf2i | fp_func_cvtd2i =>
write_reg(L, Rtype_rd); write(L, string'(", "));
write_freg(L, rs1);
when fp_func_cvti2f | fp_func_cvti2d =>
write_freg(L, Rtype_rd); write(L, string'(", "));
write_reg(L, rs1);
when fp_func_eqf | fp_func_nef | fp_func_ltf |
fp_func_gtf | fp_func_lef | fp_func_gef |
fp_func_eqd | fp_func_ned | fp_func_ltd |
fp_func_gtd | fp_func_led | fp_func_ged =>
write_freg(L, rs1); write(L, string'(", "));
write_freg(L, rs2);
when others =>
null;
end case;
when op_j | op_jal =>
write(L, bv_to_integer(instr_immed26));
when op_beqz | op_bnez =>
write_reg(L, rs1); write(L, string'(", "));
write(L, bv_to_integer(instr_immed16));
when op_bfpt | op_bfpf =>
write(L, bv_to_integer(instr_immed16));
when op_slli | op_srli | op_srai =>
write_reg(L, Itype_rd); write(L, string'(", "));
write_reg(L, rs1); write(L, string'(", "));
write(L, bv_to_natural(instr_immed16(11 to 15)));
when op_addi | op_subi |
op_seqi | op_snei | op_slti | op_sgti | op_slei | op_sgei =>
write_reg(L, Itype_rd); write(L, string'(", "));
write_reg(L, rs1); write(L, string'(", "));
write(L, bv_to_integer(instr_immed16));
when op_addui | op_subui | op_andi | op_ori | op_xori |
op_sequi | op_sneui | op_sltui | op_sgtui | op_sleui | op_sgeui =>
write_reg(L, Itype_rd); write(L, string'(", "));
write_reg(L, rs1); write(L, string'(", "));
write(L, bv_to_natural(instr_immed16));
when op_lhi =>
write_reg(L, Itype_rd); write(L, string'(", "));
write(L, bv_to_natural(instr_immed16));
when op_rfe =>
null;
when op_trap =>
write(L, bv_to_natural(instr_immed26));
when op_jr | op_jalr =>
write_reg(L, rs1);
when op_lb | op_lh | op_lw |
op_lbu | op_lhu | op_lf | op_ld =>
write_reg(L, Itype_rd); write(L, string'(", "));
write(L, bv_to_integer(instr_immed16)); write(L, '(');
write_reg(L, rs1); write(L, ')');
when op_sb | op_sh | op_sw | op_sf | op_sd =>
write(L, bv_to_integer(instr_immed16));
write(L, '('); write_reg(L, rs1); write(L, string'("), "));
write_reg(L, Itype_rd);
when others =>
null;
end case;
end write_instr;
end dlx_instr;
| apache-2.0 | a5fd4f2d580287a2af7275d1f101d819 | 0.49023 | 3.025832 | false | false | false | false |
Kalycito-open-automation/openPOWERLINK_V2_old_25-06-2014 | hardware/ipcore/xilinx/lib/src/dpRam-rtl-a.vhd | 2 | 5,447 | --! @file dpRam-bhv-a.vhd
--
--! @brief Dual Port Ram Register Transfer Level Architecture
--
--! @details This is the DPRAM intended for synthesis on Xilinx Spartan 6 only.
--! Timing as follows [clk-cycles]: write=0 / read=1
--
-------------------------------------------------------------------------------
-- Architecture : rtl
-------------------------------------------------------------------------------
--
-- (c) B&R, 2013
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
--! use global library
use work.global.all;
architecture rtl of dpRam is
--! Width of a byte
constant cByte : natural := 8;
--! Address width (used to generate size depending on address width)
constant cAddrWidth : natural := iAddress_A'length;
--! RAM size
constant cRamSize : natural := 2**cAddrWidth;
--! Type for data port
subtype tDataPort is std_logic_vector(gWordWidth-1 downto 0);
--! RAM type with given size
type tRam is array (cRamSize-1 downto 0) of tDataPort;
--! Shared variable to model and synthesize a DPR
shared variable vDpram : tRam := (others => (others => cInactivated));
--! Port A readport
signal readdataA : tDataPort;
--! Port B readport
signal readdataB : tDataPort;
begin
assert (gInitFile = "UNUSED")
report "Memory initialization is not supported in this architecture!"
severity warning;
-- assign readdata to ports
oReaddata_A <= readdataA;
oReaddata_B <= readdataB;
--! This process describes port A of the DPRAM. The write process considers
--! iWriteEnable_A and iByteenable_A. The read process is done with every
--! rising iClk_A edge.
PORTA : process(iClk_A)
begin
if rising_edge(iClk_A) then
if iEnable_A = cActivated then
if iWriteEnable_A = cActivated then
for i in iByteenable_A'range loop
if iByteenable_A(i) = cActivated then
-- write byte to DPRAM
vDpram(to_integer(unsigned(iAddress_A)))(
(i+1)*cByte-1 downto i*cByte
) := iWritedata_A(
(i+1)*cByte-1 downto i*cByte
);
end if; --byteenable
end loop;
end if; --writeenable
-- read word from DPRAM
readdataA <= vDpram(to_integer(unsigned(iAddress_A)));
end if; --enable
end if;
end process PORTA;
--! This process describes port B of the DPRAM. The write process considers
--! iWriteEnable_B and iByteenable_B. The read process is done with every
--! rising iClk_B edge.
PORTB : process(iClk_B)
begin
if rising_edge(iClk_B) then
if iEnable_B = cActivated then
if iWriteEnable_B = cActivated then
for i in iByteenable_B'range loop
if iByteenable_B(i) = cActivated then
-- write byte to DPRAM
vDpram(to_integer(unsigned(iAddress_B)))(
(i+1)*cByte-1 downto i*cByte
) := iWritedata_B(
(i+1)*cByte-1 downto i*cByte
);
end if; --byteenable
end loop;
end if; --writeenable
-- read word from DPRAM
readdataB <= vDpram(to_integer(unsigned(iAddress_B)));
end if; --enable
end if;
end process PORTB;
end architecture rtl;
| gpl-2.0 | 77019b905095c583089f2b2ed30b576c | 0.578667 | 4.907207 | false | false | false | false |
hoglet67/AtomGodilVideo | src/VGA80x40/losr.vhd | 2 | 1,931 | -- Hi Emacs, this is -*- mode: vhdl -*-
----------------------------------------------------------------------------------------------------
--
-- Registro de desplazamiento a la izquierda, entrada paralelo, salida serie
--
-- Copyright (c) 2007 Javier Valcarce García, [email protected]
-- $Id$
--
----------------------------------------------------------------------------------------------------
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity losr is
generic (
N : integer := 4);
port (
reset : in std_logic;
clk : in std_logic;
load : in std_logic;
ce : in std_logic;
do : out std_logic;
di : in std_logic_vector(N-1 downto 0));
end losr;
architecture arch of losr is
begin
process(reset, clk)
variable data : std_logic_vector(N-1 downto 0);
begin
if reset = '1' then
data := (others => '0');
elsif rising_edge(clk) then
if load = '1' then
data := di;
elsif ce = '1' then
data := data(N-2 downto 0) & "0";
end if;
end if;
do <= data(N-1);
end process;
end arch;
| apache-2.0 | 37a89036e3e95163a704fcfc607d8df5 | 0.554635 | 4.014553 | false | false | false | false |
matbur95/ucisw-pro | pro5a/vga_init.vhd | 5 | 4,958 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:38:12 03/08/2017
-- Design Name:
-- Module Name: vga_init - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity vga_init is
Port ( CLK : in STD_LOGIC;
VGA_COLOR : in STD_LOGIC_VECTOR(2 downto 0);
POS : out STD_LOGIC_VECTOR(19 downto 0);
-- ADC_DOA : in STD_LOGIC_VECTOR(13 downto 0);
-- ADC_DOB : in STD_LOGIC_VECTOR(13 downto 0);
-- ADC_Busy : in STD_LOGIC;
VGA_R : out STD_LOGIC;
VGA_G : out STD_LOGIC;
VGA_B : out STD_LOGIC;
VGA_HS : out STD_LOGIC;
VGA_VS : out STD_LOGIC
-- AMP_WE : out STD_LOGIC;
-- AMP_DI : out STD_LOGIC_VECTOR(7 downto 0);
-- ADC_Start : out STD_LOGIC;
--
-- Line : out STD_LOGIC_VECTOR(63 downto 0);
-- Blank : out STD_LOGIC_VECTOR(15 downto 0)
);
end vga_init;
architecture Behavioral of vga_init is
-- x = HPOS, y = VPOS
constant HPOS_MAX : integer := 1039;
constant VPOS_MAX : integer := 665;
-- constant HT_S : integer := 1040;
constant HT_DISP : integer := 800;
constant HT_PW : integer := 120;
constant HT_FP : integer := 64;
constant HT_BP : integer := 56;
-- constant VT_S : integer := 666;
constant VT_DISP : integer := 600;
constant VT_PW : integer := 6;
constant VT_FP : integer := 37;
constant VT_BP : integer := 23;
signal HPOS : integer range 0 to HPOS_MAX := 0;
signal VPOS : integer range 0 to VPOS_MAX := 0;
-- constant BLUE : STD_LOGIC_VECTOR(0 to 2) := "001";
-- constant YELLOW : STD_LOGIC_VECTOR(0 to 2) := "110";
-- constant SIDE : integer := 50;
-- signal BOX_HPOS : integer range -100 to HT_DISP := 400;
-- signal BOX_VPOS : integer range -100 to VT_DISP := 300;
-- signal BOX_HPOS_INT : integer range -100 to HT_DISP := 400;
-- signal BOX_VPOS_INT : integer range -100 to VT_DISP := 300;
begin
HPOS_CNT: process (CLK)
begin
if rising_edge(CLK) then
if HPOS = HPOS_MAX then
HPOS <= 0;
else
HPOS <= HPOS + 1;
end if;
end if;
end process HPOS_CNT;
VPOS_CNT: process (CLK)
begin
if rising_edge(CLK) and HPOS = HPOS_MAX then
if VPOS = VPOS_MAX then
VPOS <= 0;
else
VPOS <= VPOS + 1;
end if;
end if;
end process VPOS_CNT;
VGA_HS <= '1' when HPOS >= HT_DISP + HT_FP and HPOS < HPOS_MAX - HT_BP else '0';
VGA_VS <= '1' when VPOS >= VT_DISP + VT_FP and VPOS < VPOS_MAX - VT_BP else '0';
POS <= STD_LOGIC_VECTOR(to_unsigned(HPOS, 10)) & STD_LOGIC_VECTOR(to_unsigned(VPOS, 10));
VGA_R <= VGA_COLOR(2) when HPOS < HT_DISP and VPOS < VT_DISP else '0';
VGA_G <= VGA_COLOR(1) when HPOS < HT_DISP and VPOS < VT_DISP else '0';
VGA_B <= VGA_COLOR(0) when HPOS < HT_DISP and VPOS < VT_DISP else '0';
-- VGA_R <= '1' when HPOS < HT_DISP and VPOS < VT_DISP else '0';
-- VGA_G <= '1' when HPOS > BOX_HPOS and HPOS < BOX_HPOS + SIDE and VPOS > BOX_VPOS and VPOS < BOX_VPOS + SIDE else '0';
-- AMP_WE <= '1' when HPOS = 0 and VPOS = 0 else '0';
-- AMP_DI <= X"11";
-- ADC_Start <= '1' when HPOS = HT_DISP and VPOS = VT_DISP else '0';
--
-- Blank <= X"0F0F";
-- Line <= "00" & ADC_DOA & X"0000" & "00" & ADC_DOB & X"0000";
--
-- BOX: process (CLK, HPOS, VPOS)
-- begin
-- if rising_edge(CLK) then
-- if HPOS = 0 and VPOS = 0 then
-- BOX_HPOS_INT <= BOX_HPOS - to_integer(signed(ADC_DOA(13 downto 11)));
-- BOX_VPOS_INT <= BOX_VPOS + to_integer(signed(ADC_DOB(13 downto 11)));
-- end if;
--
-- if BOX_HPOS_INT < 0 then
-- BOX_HPOS_INT <= 0;
-- elsif BOX_HPOS_INT > HT_DISP - SIDE then
-- BOX_HPOS_INT <= HT_DISP - SIDE;
-- end if;
--
-- if BOX_VPOS_INT < 0 then
-- BOX_VPOS_INT <= 0;
-- elsif BOX_VPOS_INT > VT_DISP - SIDE then
-- BOX_VPOS_INT <= VT_DISP - SIDE;
-- end if;
--
-- BOX_HPOS <= BOX_HPOS_INT;
-- BOX_VPOS <= BOX_VPOS_INT;
-- end if;
-- end process BOX;
---- BOX_HPOS <= BOX_HPOS + to_integer(signed(ADC_DOA(13 downto 12)));
end Behavioral;
| mit | 495342a3226b986aaee17f12cc1f97c4 | 0.537313 | 3.225764 | false | false | false | false |
kristofferkoch/ethersound | phy_ctrl.vhd | 1 | 5,283 | -----------------------------------------------------------------------------
-- Module for configuring the phy to 100Mbit full-duplex through the
-- MDC-interface (connect to the miim-module)
--
-- Authors:
-- -- Kristoffer E. Koch
-----------------------------------------------------------------------------
-- Copyright 2008 Authors
--
-- This file is part of hwpulse.
--
-- hwpulse is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- hwpulse is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with hwpulse. If not, see <http://www.gnu.org/licenses/>.
-----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
entity phy_ctrl is
Port (
sysclk : in std_logic;
reset : in std_logic;
data_i : in std_logic_vector(7 downto 0);
data_i_v : in std_logic;
miim_addr : out std_logic_vector(4 downto 0);
miim_data_i : out std_logic_vector(15 downto 0);
miim_data_i_e : out std_logic;
miim_data_o : in std_logic_vector(15 downto 0);
miim_data_o_e : out std_logic;
miim_busy : in std_logic
);
end phy_ctrl;
architecture RTL of phy_ctrl is
type miim_state_t is (set_reg0, set_reg4,
wait_miim, wait_miim1,
vfy_reg0, vfy_reg0_1, vfy_reg4, vfy_reg4_1,
poll_link, poll_link_1, miim_reset_st);
signal miim_state, miim_after_wait:miim_state_t;
constant PHY_SET_REG0 :std_logic_vector(15 downto 0):="0011000100000000";
constant PHY_SET_REG0_MSK:std_logic_vector(15 downto 0):="1101111010000000";
constant PHY_SET_REG4 :std_logic_vector(15 downto 0):="0000000100000001";
constant PHY_SET_REG4_MSK:std_logic_vector(15 downto 0):="0000000100000000";
signal miim_reset:std_logic:='0';
signal miim_rdy:std_logic;
begin
-- This state-machine configures and verifies
-- the PHY to auto-negotiate 100Base-TX Full-duplex
-- Sets miim_rdy when link is up. When miim_reset is
-- asserted, a soft reset is done
miim_ctrl_fsm:process(sysclk, reset) is
begin
if rising_edge(sysclk) then
if reset = '1' then
miim_state <= wait_miim1;
miim_after_wait <= set_reg0;
miim_addr <= (OTHERS => '0');
miim_data_i <= (OTHERS => '0');
miim_data_i_e <= '0';
miim_data_o_e <= '0';
--debug <= (OTHERS => '1');
miim_rdy <= '0';
else
if miim_reset = '1' then
miim_after_wait <= miim_reset_st;
miim_rdy <= '0';
else
case miim_state is
when miim_reset_st =>
miim_addr <= std_logic_vector(to_unsigned(0, 5));
miim_data_i <= "1000000000000000";
miim_data_i_e <= '1';
miim_state <= wait_miim;
miim_after_wait <= set_reg0;
when set_reg0 =>
miim_addr <= std_logic_vector(to_unsigned(0, 5));
miim_data_i <= PHY_SET_REG0;
miim_data_i_e <= '1';
miim_state <= wait_miim;
miim_after_wait <= set_reg4;
when set_reg4 =>
miim_addr <= std_logic_vector(to_unsigned(4, 5));
miim_data_i <= PHY_SET_REG4;
miim_data_i_e <= '1';
miim_state <= wait_miim;
miim_after_wait <= vfy_reg0;
when vfy_reg0 =>
miim_addr <= std_logic_vector(to_unsigned(0, 5));
miim_data_o_e <= '1';
miim_state <= wait_miim;
miim_after_wait <= vfy_reg0_1;
when vfy_reg0_1 =>
if (miim_data_o and PHY_SET_REG0_MSK) = (PHY_SET_REG0 and PHY_SET_REG0_MSK) then
miim_state <= vfy_reg4;
else
miim_state <= set_reg0; --reset
end if;
when vfy_reg4 =>
miim_addr <= std_logic_vector(to_unsigned(4, 5));
miim_data_o_e <= '1';
miim_state <= wait_miim;
miim_after_wait <= vfy_reg4_1;
when vfy_reg4_1 =>
if (miim_data_o and PHY_SET_REG4_MSK) = (PHY_SET_REG4 and PHY_SET_REG4_MSK) then
miim_state <= poll_link;
else
miim_state <= set_reg0; --reset
end if;
when poll_link =>
miim_addr <= std_logic_vector(to_unsigned(1, 5));
miim_data_o_e <= '1';
miim_state <= wait_miim;
miim_after_wait <= poll_link_1;
when poll_link_1 =>
-- debug(0) <= miim_data_o(14); -- 100Base-TX FD (1)
-- debug(1) <= miim_data_o(5); -- Auto-neg comp (1)
-- debug(2) <= miim_data_o(4); -- remote fault (0)
-- debug(3) <= miim_data_o(3); -- able to autoneg (1)
-- debug(4) <= miim_data_o(2); -- link status (1)
-- debug(5) <= miim_data_o(1); -- jabber detect (0)
-- debug(6) <= miim_data_o(0); -- extended cap (1)
-- debug(7) <= '0';
miim_rdy <= miim_data_o(14) and miim_data_o(2);
miim_state <= poll_link;
when wait_miim =>
if miim_busy = '1' then
miim_state <= wait_miim1;
end if;
when wait_miim1 =>
miim_data_i_e <= '0';
miim_data_o_e <= '0';
if miim_busy = '0' then
miim_state <= miim_after_wait;
end if;
end case;
end if;
end if;
end if;
end process;
end RTL;
| gpl-3.0 | 8d64ab4e1bffed81a8cbca7f2fe1d464 | 0.583949 | 2.709231 | false | false | false | false |
bangonkali/quartus-sockit | soc_system/synthesis/submodules/alt_vipvfr131_common_general_fifo.vhd | 2 | 12,783 | -- Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
-- use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any
-- output files any of the foregoing (including device programming or
-- simulation files), and any associated documentation or information are
-- expressly subject to the terms and conditions of the Altera Program
-- License Subscription Agreement or other applicable license agreement,
-- including, without limitation, that your use is for the sole purpose
-- of programming logic devices manufactured by Altera and sold by Altera
-- or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.alt_vipvfr131_common_package.all;
entity alt_vipvfr131_common_general_fifo is
generic
(
WIDTH : integer := 8;
DEPTH : integer := 4;
CLOCKS_ARE_SAME : boolean := TRUE;
DEVICE_FAMILY : string;
RDREQ_TO_Q_LATENCY : integer := 1
);
port
(
-- clocks, enables and reset
rdclock : in std_logic;
rdena : in std_logic;
wrclock : in std_logic;
wrena : in std_logic;
reset : in std_logic;
-- information signals from the fifo (write side)
wrusedw : out std_logic_vector(wide_enough_for(DEPTH) - 1 downto 0);
full : out std_logic;
almost_full : out std_logic;
-- information signals from the fifo (read side)
rdusedw : out std_logic_vector(wide_enough_for(DEPTH) - 1 downto 0);
empty : out std_logic;
almost_empty : out std_logic;
-- getting data into the fifo
wrreq : in std_logic;
data : in std_logic_vector(WIDTH - 1 downto 0);
-- ...and back out again
rdreq : in std_logic;
q : out std_logic_vector(WIDTH - 1 downto 0)
);
end entity;
architecture rtl of alt_vipvfr131_common_general_fifo is
-- ASSUMPTIONS --
-- note that these constants are really prerequisites
-- they are stating things that the code requires to be true
-- if any of the other modules should change and make
-- these untrue then the code may well fail
constant RAM_FIFO_RDREQ_TO_Q_LATENCY : integer := 3;
constant LOGIC_FIFO_RDREQ_TO_Q_LATENCY : integer := 1;
-- the code assumes that if this many clock cycles have elapsed
-- between a write and a read to the same location in the ram
-- then the new data will be seen
-- must be at least 1 or the logic won't work
-- the code also assumes that the delay associated with getting
-- numbers across clock domains is significantly more than this
constant RAM_READ_AFTER_WRITE_LATENCY : integer := 3;
-- wide enough to express the maximum number of words in the whole fifo
constant USEDW_WIDTH : integer := wide_enough_for(DEPTH);
-- true when the fifo requested is small enough that if it is single-clocked,
-- a logic only implementation is a good idea
constant SMALL_FIFO : boolean := ((WIDTH * DEPTH) <= 32) or (DEPTH < 4);
-- if a lower RDREQ_TO_Q_LATENCY is requested than the ram ordinarily
-- provides then an output logic fifo is required to plug the gap
-- this constant defines the required depth of this fifo
-- the plus one is required because the fifo must be one element larger
-- than the difference in latency it's trying to eliminate, because
-- there is a one cycle read after write latency on the logic fifo
-- N.B. if the ram fifo is not in use then these constants are ignored
constant OUTPUT_LOGIC_FIFO_DEPTH : integer := RAM_FIFO_RDREQ_TO_Q_LATENCY + 1 - RDREQ_TO_Q_LATENCY;
constant OUTPUT_LOGIC_FIFO_IN_USE : boolean := OUTPUT_LOGIC_FIFO_DEPTH > 1;
-- if the requested RDREQ_TO_Q_LATENCY is higher than that provided by the
-- fifo components we intend to use to build the fifo then the general fifo
-- must insert some delaying on the input signal to take this into account
-- (and must model this delay in its own usedw calculation)
function calculate_rdreq_to_q_latency_inc return integer is
variable natural_rdreq_to_q_latency : integer;
begin
if CLOCKS_ARE_SAME and SMALL_FIFO then
natural_rdreq_to_q_latency := LOGIC_FIFO_RDREQ_TO_Q_LATENCY;
else
natural_rdreq_to_q_latency := RAM_FIFO_RDREQ_TO_Q_LATENCY;
end if;
if RDREQ_TO_Q_LATENCY > natural_rdreq_to_q_latency then
return RDREQ_TO_Q_LATENCY - natural_rdreq_to_q_latency;
else
return 0;
end if;
end function;
constant RDREQ_TO_Q_LATENCY_INC : integer := calculate_rdreq_to_q_latency_inc;
-- this holds the delayed rdreq
signal rdreq_delay : std_logic;
-- the general fifo needs to model the read to write and write to read latencies
-- of the fifo as a whole, to update its usedw and so on correctly
-- this can be quite complex as it depends on the combination of individual fifo
-- components used
function calculate_fifo_read_to_write_delay return integer is
begin
return RDREQ_TO_Q_LATENCY_INC;
end function;
constant FIFO_READ_TO_WRITE_DELAY : integer := calculate_fifo_read_to_write_delay;
function calculate_fifo_write_to_read_delay return integer is
begin
if CLOCKS_ARE_SAME then
if SMALL_FIFO then
-- logic fifo only, very simple!
return 0;
elsif OUTPUT_LOGIC_FIFO_IN_USE then
-- if an output logic fifo is in use then we need enough time from write to
-- read to allow for a) data has been written into the ram, b) data gets from
-- the ram to the output logic fifo, c) the output logic fifo fills
-- minus one because the fifo can get data in one less than q latency, due to showahead
return RAM_READ_AFTER_WRITE_LATENCY + RAM_FIFO_RDREQ_TO_Q_LATENCY - 1 + OUTPUT_LOGIC_FIFO_DEPTH;
else
-- if no output logic fifo is in use, then we just have to make sure that we
-- don't rdreq from the ram before the data has updated in the ram
return RAM_READ_AFTER_WRITE_LATENCY;
end if;
else
-- in the dual clock case, we assume that the delay associated with crossing
-- clock domains will always outweigh the read after write latency of the ram,
-- so we only have to concern ourselves with additional delay incurred by the
-- output logic fifo
if OUTPUT_LOGIC_FIFO_IN_USE then
-- minus one because the fifo can get data in one less than q latency, due to showahead
return RAM_FIFO_RDREQ_TO_Q_LATENCY - 1 + OUTPUT_LOGIC_FIFO_DEPTH;
else
return 0;
end if;
end if;
end function;
constant FIFO_WRITE_TO_READ_DELAY : integer := calculate_fifo_write_to_read_delay;
begin
-- instantiate a standard usedw calculator to do the usedw, empty etc. updating
-- for the whole fifo - this may be the same as the usedw calculations for the
-- components which make up this fifo (in which case any decent synthesis tool
-- will optimise away the redundancy) or may be different
usedw_calculator : alt_vipvfr131_common_fifo_usedw_calculator
generic map
(
WIDTH => USEDW_WIDTH,
DEPTH => DEPTH,
CLOCKS_ARE_SAME => CLOCKS_ARE_SAME,
READ_TO_WRITE_DELAY => FIFO_READ_TO_WRITE_DELAY,
WRITE_TO_READ_DELAY => FIFO_WRITE_TO_READ_DELAY
)
port map
(
rdclock => rdclock,
rdena => rdena,
wrclock => wrclock,
wrena => wrena,
reset => reset,
wrreq => wrreq,
rdreq => rdreq,
wrusedw => wrusedw,
full => full,
almost_full => almost_full,
rdusedw => rdusedw,
empty => empty,
almost_empty => almost_empty
);
-- delay incoming rdreq signal as necessary
rdreq_delayer : alt_vipvfr131_common_one_bit_delay
generic map
(
DELAY => RDREQ_TO_Q_LATENCY_INC
)
port map
(
clock => rdclock,
ena => rdena,
reset => reset,
data => rdreq,
q => rdreq_delay
);
single_clock_small_gen :
if CLOCKS_ARE_SAME and SMALL_FIFO generate
begin
-- use the logic fifo alone for really small single clock fifos
logic_fifo : alt_vipvfr131_common_logic_fifo
generic map
(
WIDTH => WIDTH,
DEPTH => DEPTH
)
port map
(
clock => rdclock,
rdena => rdena,
wrena => wrena,
reset => reset,
wrreq => wrreq,
data => data,
rdreq => rdreq_delay,
q => q
);
end generate;
-- use a ram fifo for larger fifos or dual clock fifos
dual_clock_or_large_gen :
if not CLOCKS_ARE_SAME or not SMALL_FIFO generate
-- signals for ram fifo
signal ram_fifo_q : std_logic_vector(WIDTH - 1 downto 0);
signal ram_fifo_empty : std_logic;
signal ram_fifo_rdreq : std_logic;
begin
-- this ram fifo can hold most of the data
ram_fifo : alt_vipvfr131_common_ram_fifo
generic map
(
WIDTH => WIDTH,
DEPTH => DEPTH,
CLOCKS_ARE_SAME => CLOCKS_ARE_SAME,
DEVICE_FAMILY => DEVICE_FAMILY
)
port map
(
rdclock => rdclock,
wrclock => wrclock,
reset => reset,
empty => ram_fifo_empty,
wrreq => wrreq,
wrena => wrena,
data => data,
rdreq => ram_fifo_rdreq,
rdena => rdena,
q => ram_fifo_q
);
-- the RDREQ_TO_Q_LATENCY of the ram fifo is three
-- if the user has requested a lower RDREQ_TO_Q_LATENCY,
-- we need to instantiate an output logic fifo to smooth
-- things out
output_logic_fifo_gen :
if OUTPUT_LOGIC_FIFO_IN_USE generate
-- signals for output logic fifo ports
signal logic_fifo_data : std_logic_vector(WIDTH - 1 downto 0);
signal logic_fifo_full : std_logic;
signal logic_fifo_wrreq : std_logic;
signal logic_fifo_rdreq : std_logic;
signal logic_fifo_wrusedw : std_logic_vector(wide_enough_for(OUTPUT_LOGIC_FIFO_DEPTH) - 1 downto 0);
signal data_in_transit : unsigned(wide_enough_for(OUTPUT_LOGIC_FIFO_DEPTH) - 1 downto 0);
begin
-- feed the ram fifo output into the logic fifo input
logic_fifo_data <= ram_fifo_q;
-- instantiate logic fifo
output_logic_fifo : alt_vipvfr131_common_logic_fifo
generic map
(
WIDTH => WIDTH,
DEPTH => OUTPUT_LOGIC_FIFO_DEPTH
)
port map
(
clock => rdclock,
rdena => rdena,
wrena => rdena, -- because this is entirely on the read side
reset => reset,
full => logic_fifo_full,
wrreq => logic_fifo_wrreq,
wrusedw => logic_fifo_wrusedw,
data => logic_fifo_data,
rdreq => logic_fifo_rdreq,
q => q
);
-- in the situation where the user is requesting lower RDREQ_TO_Q_LATENCY
-- than the ram fifo can provide, but more than the one cycle latency that
-- the logic fifo provides, we need to delay the logic fifo rdreq
logic_fifo_rdreq_delayer : alt_vipvfr131_common_one_bit_delay
generic map
(
DELAY => RDREQ_TO_Q_LATENCY - 1
)
port map
(
clock => rdclock,
ena => rdena,
reset => reset,
data => rdreq,
q => logic_fifo_rdreq
);
-- a shift register is used to delay the rdreq signal going into the ram
-- to make a wrreq signal for the logic fifo
-- this is required because of the high RDREQ_TO_Q_LATENCY of the ram fifo
ram_fifo_rdreq_delayer : alt_vipvfr131_common_one_bit_delay
generic map
(
DELAY => RAM_FIFO_RDREQ_TO_Q_LATENCY - 1 -- minus one because showahead
)
port map
(
clock => rdclock,
ena => rdena,
reset => reset,
data => ram_fifo_rdreq,
q => logic_fifo_wrreq
);
-- keep a count of how many words have been requested from the ram
-- but not yet input into the logic fifo
-- this is required because of the high RDREQ_TO_Q_LATENCY of the ram fifo
update_data_in_transit : process (rdclock, reset)
begin
if reset = '1' then
data_in_transit <= (others => '0');
elsif rdclock'EVENT and rdclock = '1' then
if rdena = '1' then
if ram_fifo_rdreq = '1' and logic_fifo_wrreq = '0' then
-- requested but didn't receive, increase
data_in_transit <= data_in_transit + 1;
elsif ram_fifo_rdreq = '0' and logic_fifo_wrreq = '1' then
-- didn't request but did receive, decrease
data_in_transit <= data_in_transit - 1;
end if;
end if;
end if;
end process;
-- calculate when the ram fifo should read (a combination of when the user
-- requests reads and when the output logic fifo is not full)
ram_fifo_rdreq <= '1' when (rdreq_delay = '1' or (unsigned(logic_fifo_wrusedw) + data_in_transit) < OUTPUT_LOGIC_FIFO_DEPTH) and ram_fifo_empty = '0' else '0';
end generate;
-- alternatively just make sure the ram fifo is connected directly
no_output_logic_fifo_gen :
if not OUTPUT_LOGIC_FIFO_IN_USE generate
begin
q <= ram_fifo_q;
ram_fifo_rdreq <= rdreq_delay;
end generate;
end generate;
end architecture rtl;
| mit | 84fa052f5a30e4f46139af157fde41a7 | 0.670187 | 3.438139 | false | false | false | false |
FinnK/lems2hdl | work/N3_pointCellCondBased/ISIM_output/delayDone.vhdl | 2 | 1,741 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 00:39:32 01/12/2015
-- Design Name:
-- Module Name: delayDone - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use IEEE.numeric_std.all;
entity delayDone is
generic(
Steps : integer := 10);
port(
clk : In Std_logic;
init_model : in STD_LOGIC; --signal to all components to go into their init state
Start : In Std_logic;
Done : Out Std_logic
);
end delayDone;
architecture Behavioral of delayDone is
signal count : integer ;
signal count_next : integer ;
signal Done_next : std_logic ;
begin
combinationProc : process (count,start,init_model)
begin
count_next <= count;
Done_next <= '0';
if init_model = '1' then
count_next <= Steps;
Done_next <= '1';
else
if start = '1' then
count_next <= 0;
elsif count < Steps then
count_next <= count + 1;
else
Done_next <= '1';
end if;
end if;
end process;
synchronousProc : process (clk)
begin
if clk'event and clk = '1' then
count <= count_next;
Done <= Done_next;
end if;
end process;
end Behavioral;
| lgpl-3.0 | a09be92fc219e947015997ec3cc26487 | 0.620333 | 3.413725 | false | false | false | false |
kristofferkoch/ethersound | rxsync.vhd | 1 | 5,374 | -----------------------------------------------------------------------------
-- Module for transfering data from the 25MHz phy-clock nibble domain to
-- 50MHz byte clock-domain. Also strips away preamble and SFD.
--
-- Authors:
-- -- Kristoffer E. Koch
-----------------------------------------------------------------------------
-- Copyright 2008 Authors
--
-- This file is part of hwpulse.
--
-- hwpulse is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- hwpulse is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with hwpulse. If not, see <http://www.gnu.org/licenses/>.
-----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.crc.all;
entity rxsync is
Generic (reset_en:std_logic:='1');
Port ( sysclk : in STD_LOGIC;
reset : in STD_LOGIC;
rx_clk : in STD_LOGIC;
rxd : in STD_LOGIC_VECTOR (3 downto 0);
rx_dv : in STD_LOGIC;
data : out STD_LOGIC_VECTOR (7 downto 0);
data_end : out std_logic;
data_err : out std_logic;
data_dv : out STD_LOGIC;
crc_ok: out std_logic;
debug:out std_logic_vector(7 downto 0)
);
end rxsync;
architecture Behavioral of rxsync is
signal rst:std_logic;
-- rx_clk clockdomain
-- inreg latches rxd on rising rx_clk
signal inreg:std_logic_vector(3 downto 0);
signal inbytereg:std_logic_vector(8 downto 0);
signal crcreg, nextcrc:std_logic_vector(31 downto 0);
signal crcnibble:std_logic_vector(3 downto 0);
signal eod, err, crc:std_logic:='0';
signal dv_ccd:std_logic:='0';
type state_t is (Idle, Preamble, SFD, data0, data1);
signal state:state_t:=Idle;
-- sysclk clockdomain
signal dv_sync:std_logic_vector(2 downto 0);
signal dv_edge:std_logic;
begin
rst <= reset_en and reset;
nextcrc <= Crc32_4(rxd, crcreg, '1') when state = Data0 or state = Data1
else (OTHERS => '1');
fsm:process(rx_clk) is
variable eod_v, err_v, crc_v:std_logic;
begin
if rising_edge(rx_clk) then
if rst = '1' then
state <= Idle;
err <= '0';
eod <= '0';
crc <= '0';
debug(3 downto 0) <= (OTHERS => '1');
else
if err = '1' and eod = '0' then
eod_v := '1';
err_v := '1';
else
eod_v := '0';
err_v := '0';
end if;
crc_v := '0';
case state is
when Preamble =>
debug(0) <= '0';
if rx_dv = '1' then
if rxd = x"5" then
state <= SFD;
end if;
else
state <= Idle;
end if;
when SFD =>
debug(1) <= '0';
if rx_dv = '1' then
if rxd = x"d" then
state <= data0;
elsif rxd /= x"5" then
state <= Preamble;
end if;
else
state <= Idle;
end if;
when data0 =>
debug(2) <= '0';
if rx_dv = '1' then
state <= data1;
else
eod_v := '1';
if crcreg = x"12345678" then
crc_v := '1';
end if;
state <= Idle;
end if;
when data1 =>
debug(3) <= '0';
if rx_dv = '1' then
state <= data0;
else
err_v := '1';
state <= Idle;
end if;
when others => --Idle
if rx_dv = '1' then
if rxd = x"5" then
state <= SFD;
else
state <= Preamble;
end if;
end if;
end case;
err <= err_v;
eod <= eod_v;
crc <= crc_v;
end if;
end if;
end process;
process(rx_clk) is
begin
if rising_edge(rx_clk) then
if rst = '1' then
inreg <= (OTHERS => '0');
inbytereg <= (OTHERS => '0');
dv_ccd <= '0';
crcreg <= (OTHERS => '1');
else
crcreg <= nextcrc;
inreg <= rxd;
if eod = '1' then
inbytereg <= "1000000" & crc & err;
dv_ccd <= not dv_ccd;
elsif state = data1 then
inbytereg <= '0' & rxd & inreg;
dv_ccd <= not dv_ccd;
end if;
end if;
end if;
end process;
process(sysclk) is
variable data_dv_v, data_err_v, data_end_v, crc_ok_v:std_logic;
begin
if rising_edge(sysclk) then
if rst = '1' then
dv_sync <= (OTHERS => '0');
data_dv <= '0';
data_end <= '0';
data_err <= '0';
data <= (OTHERS => '0');
debug(7 downto 4) <= (OTHERS => '1');
else
dv_sync(0) <= dv_ccd;
dv_sync(1) <= dv_sync(0);
dv_sync(2) <= dv_sync(1);
data_dv_v := '0';
data_err_v := '0';
data_end_v := '0';
crc_ok_v := '0';
if dv_edge = '1' then
if inbytereg(8) = '0' then
data <= inbytereg(7 downto 0);
data_dv_v := '1';
debug(4) <= '0';
else
data_err_v := inbytereg(0);
crc_ok_v := inbytereg(1);
data_end_v := '1';
debug(5) <= '0';
end if;
end if;
data_dv <= data_dv_v;
data_err <= data_err_v;
crc_ok <= crc_ok_v;
data_end <= data_end_v;
end if;
end if;
end process;
dv_edge <= dv_sync(1) xor dv_sync(2);
end Behavioral;
| gpl-3.0 | 8a4c960139fe898307c8553c62345755 | 0.521585 | 2.930207 | false | false | false | false |
hoglet67/AtomGodilVideo | src/MINIUART/Rxunit.vhd | 1 | 3,590 | -------------------------------------------------------------------------------
-- Title : UART
-- Project : UART
-------------------------------------------------------------------------------
-- File : Rxunit.vhd
-- Author : Philippe CARTON
-- ([email protected])
-- Organization:
-- Created : 15/12/2001
-- Last update : 8/1/2003
-- Platform : Foundation 3.1i
-- Simulators : ModelSim 5.5b
-- Synthesizers: Xilinx Synthesis
-- Targets : Xilinx Spartan
-- Dependency : IEEE std_logic_1164
-------------------------------------------------------------------------------
-- Description: RxUnit is a serial to parallel unit Receiver.
-------------------------------------------------------------------------------
-- Copyright (c) notice
-- This core adheres to the GNU public license
--
-------------------------------------------------------------------------------
-- Revisions :
-- Revision Number :
-- Version :
-- Date :
-- Modifier : name <email>
-- Description :
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity RxUnit is
port (
Clk : in std_logic; -- system clock signal
Reset : in std_logic; -- Reset input
Enable : in std_logic; -- Enable input
ReadA : in Std_logic; -- Async Read Received Byte
RxD : in std_logic; -- RS-232 data input
RxAv : out std_logic; -- Byte available
DataO : out std_logic_vector(7 downto 0) -- Byte received
);
end RxUnit;
architecture Behaviour of RxUnit is
signal RReg : std_logic_vector(7 downto 0); -- receive register
signal RRegL : std_logic; -- Byte received
begin
-- RxAv process
RxAvProc : process(RRegL,Reset,ReadA)
begin
if ReadA = '1' or Reset = '1' then
RxAv <= '0'; -- Negate RxAv when RReg read
elsif Rising_Edge(RRegL) then
RxAv <= '1'; -- Assert RxAv when RReg written
end if;
end process;
-- Rx Process
RxProc : process(Clk,Reset,Enable,RxD,RReg)
variable BitPos : INTEGER range 0 to 10; -- Position of the bit in the frame
variable SampleCnt : INTEGER range 0 to 3; -- Count from 0 to 3 in each bit
begin
if Reset = '1' then -- Reset
RRegL <= '0';
BitPos := 0;
elsif Rising_Edge(Clk) then
if Enable = '1' then
case BitPos is
when 0 => -- idle
RRegL <= '0';
if RxD = '0' then -- Start Bit
SampleCnt := 0;
BitPos := 1;
end if;
when 10 => -- Stop Bit
BitPos := 0; -- next is idle
RRegL <= '1'; -- Indicate byte received
DataO <= RReg; -- Store received byte
-- Set the Rx interrupt flag when Rx interrupt is enabled
-- if IntRxEn = '1' then
-- IntRxFlag <= '1';
-- end if;
when others =>
if (SampleCnt = 1 and BitPos >= 2) then -- Sample RxD on 1
RReg(BitPos-2) <= RxD; -- Deserialisation
end if;
if SampleCnt = 3 then -- Increment BitPos on 3
BitPos := BitPos + 1;
end if;
end case;
if SampleCnt = 3 then
SampleCnt := 0;
else
sampleCnt := SampleCnt + 1;
end if;
end if;
end if;
end process;
end Behaviour;
| apache-2.0 | b54fffa56c06ad597cd2deead8c01c6f | 0.453203 | 4.304556 | false | false | false | false |
sergev/vak-opensource | hardware/dlx/alu-behaviour.vhdl | 1 | 2,836 | --------------------------------------------------------------------------
--
-- Copyright (C) 1993, Peter J. Ashenden
-- Mail: Dept. Computer Science
-- University of Adelaide, SA 5005, Australia
-- e-mail: [email protected]
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 1, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
--------------------------------------------------------------------------
--
-- $RCSfile: alu-behaviour.vhdl,v $ $Revision: 2.1 $ $Date: 1993/11/02 18:52:07 $
--
--------------------------------------------------------------------------
--
-- Behavioural architecture of ALU.
--
architecture behaviour of alu is
begin
alu_op: process (s1, s2, latch_en, func)
use work.bv_arithmetic.all;
variable stored_s1, stored_s2 : dlx_word;
variable temp_result : dlx_word;
variable temp_overflow : boolean;
begin
if latch_en = '1' then
stored_s1 := s1;
stored_s2 := s2;
end if;
case func is
when alu_pass_s1 =>
temp_result := stored_s1;
when alu_pass_s2 =>
temp_result := stored_s2;
when alu_and =>
temp_result := stored_s1 and stored_s2;
when alu_or =>
temp_result := stored_s1 or stored_s2;
when alu_xor =>
temp_result := stored_s1 xor stored_s2;
when alu_sll =>
temp_result := bv_sll(stored_s1, bv_to_natural(stored_s2(27 to 31)));
when alu_srl =>
temp_result := bv_srl(stored_s1, bv_to_natural(stored_s2(27 to 31)));
when alu_sra =>
temp_result := bv_sra(stored_s1, bv_to_natural(stored_s2(27 to 31)));
when alu_add =>
bv_add(stored_s1, stored_s2, temp_result, temp_overflow);
when alu_addu =>
bv_addu(stored_s1, stored_s2, temp_result, temp_overflow);
when alu_sub =>
bv_sub(stored_s1, stored_s2, temp_result, temp_overflow);
when alu_subu =>
bv_subu(stored_s1, stored_s2, temp_result, temp_overflow);
end case;
result <= temp_result after Tpd;
zero <= bit'val(boolean'pos(temp_result = dlx_word'(X"0000_0000"))) after Tpd;
negative <= temp_result(0) after Tpd;
overflow <= bit'val(boolean'pos(temp_overflow)) after Tpd;
end process alu_op;
end behaviour;
| apache-2.0 | d3fe7d45ae8d25b6fa7b5672a9127064 | 0.590621 | 3.501235 | false | false | false | false |
Kalycito-open-automation/openPOWERLINK_V2_old_25-06-2014 | hardware/ipcore/common/openmac/src/openhub-rtl-ea.vhd | 2 | 7,431 | -------------------------------------------------------------------------------
--! @file openhub-rtl-ea.vhd
--
--! @brief OpenHUB
--
--! @details This is the openHUB using RMII Rx and Tx lines.
-------------------------------------------------------------------------------
--
-- (c) B&R, 2013
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
--! use global library
use work.global.all;
--! use openmac package
use work.openmacPkg.all;
entity openhub is
generic (
--! Number of ports
gPortCount : integer := 3
);
port (
--! Reset
iRst : in std_logic;
--! RMII Clock
iClk : in std_logic;
--! RMII receive paths
iRx : in tRmiiPathArray(gPortCount downto 1);
--! RMII transmit paths
oTx : out tRmiiPathArray(gPortCount downto 1);
--! Determine number of internal port (to MAC)
iIntPort : in integer range 1 to gPortCount := 1;
--! Transmit mask to enable ports
iTxMask : in std_logic_vector(gPortCount downto 1) := (others => cActivated);
--! Gives the number of the currectly receiving port
oRxPort : out integer range 0 to gPortCount
);
end entity openhub;
architecture rtl of openhub is
--! All ports inactive constant
constant cPortsAreInactive : std_logic_vector(gPortCount downto 0) := (others => cInactivated);
--! Receive path array
signal rxPath : tRmiiPathArray(gPortCount downto 0);
--! Receive path array delayed by one cycle
signal rxPath_l : tRmiiPathArray(gPortCount downto 0);
--! Transmit path array
signal txPath : tRmiiPathArray(gPortCount downto 0);
--! Stored transmit mask (is taken from iTxMask when to packet transfer is in progress)
signal txMask_reg : std_logic_vector(gPortCount downto 1);
begin
rxPath <= iRx & cRmiiPathInit;
oTx <= txPath(oTx'range);
do: process (iRst, iClk)
variable vActive : boolean;
variable vMaster : integer range 0 to gPortCount;
variable vMasterAtCollision : integer range 0 to gPortCount;
variable vCollision : boolean;
variable vRxDvm : std_logic_vector(gPortCount downto 0);
begin
if iRst = cActivated then
rxPath_l <= (others => cRmiiPathInit);
txPath <= (others => cRmiiPathInit);
vActive := false;
vMaster := 0;
vMasterAtCollision := 0;
vCollision := false;
txMask_reg <= (others => cInactivated);
elsif rising_edge(iClk) then
rxPath_l <= rxPath;
if vActive = false then
if rmiiGetEnable(rxPath_l) /= cPortsAreInactive then
for i in 1 to gPortCount loop
if (rxPath_l(i).enable = cActivated and
(rxPath_l(i).data(0) = cActivated or rxPath_l(i).data(1) = cActivated)) then
vMaster := i;
vActive := true;
exit;
end if;
end loop;
end if;
else
if rxPath_l(vMaster).enable = cInactivated and rxPath(vMaster).enable = cInactivated then
vMaster := 0;
end if;
if rmiiGetEnable(rxPath_l) = cPortsAreInactive and rmiiGetEnable(rxPath) = cPortsAreInactive then
vActive := false;
end if;
end if;
if vMaster = 0 then
txPath <= (others => cRmiiPathInit);
-- overtake new iTxMask only, when there is no active frame.
txMask_reg <= iTxMask;
else
for i in 1 to gPortCount loop -- output received frame to every port
if i /= vMaster then -- but not to the port where it is coming from - "eh kloar!"
-- only send data to active ports (=> iTxMask is set to cActivated) or the internal port (mac)
if txMask_reg(i) = cActivated or vMaster = iIntPort then
txPath(i).enable <= cActivated;
txPath(i).data <= rxPath_l(vMaster).data;
end if;
-- if there is a frame received and another is sent => collision!
if rxPath_l(i).enable = cActivated then
vCollision := true;
vMasterAtCollision := vMaster;
end if;
end if;
end loop;
end if;
if vCollision = true then
txPath(vMasterAtCollision).enable <= cActivated;
txPath(vMasterAtCollision).data <= "01";
vRxDvm := rmiiGetEnable(rxPath_l);
vRxDvm(vMasterAtCollision) := cInactivated;
if vRxDvm = cPortsAreInactive then
txPath(vMasterAtCollision) <= cRmiiPathInit;
vCollision := false;
vMasterAtCollision := 0;
end if;
end if;
-- output the master port - identifies the port (1...n) which has received the packet.
-- if master is 0, the hub is inactive.
oRxPort <= vMaster;
end if;
end process do;
end rtl;
| gpl-2.0 | ffcd248597544675f7bb88c38663de9a | 0.544072 | 4.983903 | false | false | false | false |
Kalycito-open-automation/openPOWERLINK_V2_old_25-06-2014 | hardware/ipcore/common/openmac/src/openmacTimer-rtl-ea.vhd | 2 | 7,736 | -------------------------------------------------------------------------------
--! @file openmacTimer-rtl-ea.vhd
--
--! @brief OpenMAC timer module
--
--! @details This is the openMAC timer module. It supports accessing the MAC
--! time and generating interrupts.
-------------------------------------------------------------------------------
--
-- (c) B&R, 2013
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
--! use global library
use work.global.all;
--! use openmac package
use work.openmacPkg.all;
entity openmacTimer is
generic (
--! Data width of iMacTime
gMacTimeWidth : natural := 32;
--! Generate second timer
gMacTimer_2ndTimer : boolean := false;
--! Width of pulse register
gTimerPulseRegWidth : integer := 9;
--! Enable pulse width control
gTimerEnablePulseWidth : boolean := false
);
port (
--! Reset
iRst : in std_logic;
--! Clock (same like MAC)
iClk : in std_logic;
--! Write
iWrite : in std_logic;
--! Address (dword addressing!)
iAddress : in std_logic_vector(3 downto 2);
--! Write data
iWritedata : in std_logic_vector(31 downto 0);
--! Read data
oReaddata : out std_logic_vector(31 downto 0);
--! MAC time
iMacTime : in std_logic_vector(gMacTimeWidth-1 downto 0);
--! Interrupt of first timer (level triggered)
oIrq : out std_logic;
--! Toggle output of second timer
oToggle : out std_logic
);
end openmacTimer;
architecture rtl of openmacTimer is
signal cmp_enable : std_logic;
signal tog_enable : std_logic;
signal cmp_value : std_logic_vector(iMacTime'range);
signal tog_value : std_logic_vector(iMacTime'range);
signal tog_counter_value : std_logic_vector(gTimerPulseRegWidth-1 downto 0);
signal tog_counter_preset : std_logic_vector(gTimerPulseRegWidth-1 downto 0);
signal irq_s : std_logic;
signal toggle_s : std_logic;
begin
oIrq <= irq_s;
oToggle <= toggle_s;
--! This process generates the interrupt and toggle signals and handles the
--! register writes.
REGPROC : process(iRst, iClk)
begin
if iRst = '1' then
cmp_enable <= '0';
cmp_value <= (others => '0');
irq_s <= '0';
if gMacTimer_2ndTimer = TRUE then
tog_enable <= '0';
tog_value <= (others => '0');
toggle_s <= '0';
if gTimerEnablePulseWidth = TRUE then
tog_counter_value <= (others => '0');
tog_counter_preset <= (others => '0');
end if;
end if;
elsif rising_edge(iClk) then
--cmp
if cmp_enable = '1' and iMacTime = cmp_value then
irq_s <= '1';
end if;
--tog
if tog_enable = '1' and iMacTime = tog_value and gMacTimer_2ndTimer = TRUE then
toggle_s <= not toggle_s;
if gTimerEnablePulseWidth = TRUE then
tog_counter_value <= tog_counter_preset;
end if;
end if;
if tog_enable = '1' and toggle_s = '1'
and (not (tog_counter_value = std_logic_vector(to_unsigned(0, tog_counter_value'length))))
and gMacTimer_2ndTimer = TRUE
and gTimerEnablePulseWidth = TRUE then
tog_counter_value <= std_logic_vector(unsigned(tog_counter_value) - 1);
if tog_counter_value = std_logic_vector(to_unsigned(1, tog_counter_value'length)) then
toggle_s <= '0';
end if;
end if;
--memory mapping
if iWrite = '1' then
case iAddress is
when "00" =>
cmp_value <= iWritedata;
irq_s <= '0';
when "01" =>
cmp_enable <= iWritedata(0);
when "10" =>
if gMacTimer_2ndTimer = TRUE then
tog_value <= iWritedata;
end if;
when "11" =>
if gMacTimer_2ndTimer = TRUE then
tog_enable <= iWritedata(0);
if gTimerEnablePulseWidth = TRUE then
tog_counter_preset <= iWritedata(gTimerPulseRegWidth downto 1);
end if;
end if;
when others =>
assert (FALSE)
report "Write in forbidden area?"
severity failure;
end case;
end if;
end if;
end process REGPROC;
ASSIGN_RD : process (
iAddress,
iMacTime,
irq_s,
cmp_enable,
tog_value,
toggle_s,
tog_enable
)
begin
--default is all zero
oReaddata <= (others => cInactivated);
case iAddress is
when "00" =>
oReaddata <= iMacTime;
when "01" =>
oReaddata(1) <= irq_s;
oReaddata(0) <= cmp_enable;
when "10" =>
if gMacTimer_2ndTimer = TRUE then
oReaddata <= tog_value;
end if;
when "11" =>
if gMacTimer_2ndTimer = TRUE then
oReaddata(1) <= toggle_s;
oReaddata(0) <= tog_enable;
end if;
when others =>
NULL; --this is okay, since default assignment is above!
end case;
end process ASSIGN_RD;
end rtl;
| gpl-2.0 | ebd910a2027c086ee874385967a33664 | 0.519131 | 4.760615 | false | false | false | false |
sergev/vak-opensource | hardware/vhd2vl/examples/counters.vhd | 1 | 10,348 | library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counters is
port(
sysclk : in std_logic;
foo_card : in std_logic;
wfoo0_baz : in std_logic;
wfoo0_blrb : in std_logic;
wfoo0_zz1pb : in std_logic;
wfoo0_turn : in std_logic_vector(31 downto 0);
debct_baz : in std_logic;
debct_blrb : in std_logic;
debct_zz1pb : in std_logic;
debct_bar : in std_logic;
debct_turn : in std_logic_vector(31 downto 0);
Z0_bar : in std_logic;
Z0_baz : in std_logic;
Z0_blrb : in std_logic;
Z0_zz1pb : in std_logic;
Z0_turn : in std_logic_vector(31 downto 0);
Y1_bar : in std_logic;
Y1_baz : in std_logic;
Y1_blrb : in std_logic;
Y1_zz1pb : in std_logic;
Y1_turn : in std_logic_vector(31 downto 0);
X2_bar : in std_logic;
X2_baz : in std_logic;
X2_blrb : in std_logic;
X2_zz1pb : in std_logic;
X2_turn : in std_logic_vector(31 downto 0);
W3_bar : in std_logic;
W3_baz : in std_logic;
W3_blrb : in std_logic;
W3_zz1pb : in std_logic;
W3_turn : in std_logic_vector(31 downto 0);
-- to engine block
Z0_cwm : out std_logic;
Z0 : out std_logic_vector(31 downto 0);
Y1_cwm : out std_logic;
Y1 : out std_logic_vector(31 downto 0);
X2_cwm : out std_logic;
X2 : out std_logic_vector(31 downto 0);
W3_cwm : out std_logic;
W3 : out std_logic_vector(31 downto 0);
wfoo0_cwm : out std_logic;
wfoo0_llwln : out std_logic_vector(31 downto 0);
debct_cwm : out std_logic;
debct_pull : out std_logic;
debct : out std_logic_vector(31 downto 0);
wdfilecardA2P : out std_logic
);
end counters;
architecture rtl of counters is
signal wfoo0_llwln_var : unsigned(31 downto 0);
signal debct_var : unsigned(31 downto 0);
signal Z0_var : unsigned(31 downto 0);
signal Y1_var : unsigned(31 downto 0);
signal X2_var : unsigned(31 downto 0);
signal W3_var : unsigned(31 downto 0);
signal main_wfoo0_cwm : std_logic;
signal do_q3p_Z0 : std_logic;
signal do_q3p_Y1 : std_logic;
signal do_q3p_X2 : std_logic;
signal do_q3p_W3 : std_logic;
signal do_q3p_wfoo0 : std_logic;
signal do_q3p_debct : std_logic;
signal Z0_cwm_i : std_logic;
signal Y1_cwm_i : std_logic;
signal X2_cwm_i : std_logic;
signal W3_cwm_i : std_logic;
signal debct_cwm_i : std_logic;
signal file_card_i : std_logic;
signal do_file_card_i : std_logic;
signal prev_do_file_card : std_logic;
begin
-----
-- form the outputs
wfoo0_llwln <= std_logic_vector(wfoo0_llwln_var);
debct <= std_logic_vector(debct_var);
Z0 <= std_logic_vector(Z0_var);
Y1 <= std_logic_vector(Y1_var);
X2 <= std_logic_vector(X2_var);
W3 <= std_logic_vector(W3_var);
Z0_cwm <= Z0_cwm_i;
Y1_cwm <= Y1_cwm_i;
X2_cwm <= X2_cwm_i;
W3_cwm <= W3_cwm_i;
debct_cwm <= debct_cwm_i;
wdfilecardA2P <= do_file_card_i;
LLWLNS :
process(foo_card, sysclk)
begin
if foo_card = '1' then
wfoo0_llwln_var <= (others => '0');
debct_var <= (others => '0');
Z0_var <= (others => '0');
Y1_var <= (others => '0');
X2_var <= (others => '0');
W3_var <= (others => '0');
wfoo0_cwm <= '0';
debct_cwm_i <= '0';
debct_pull <= '0';
Z0_cwm_i <= '0';
Y1_cwm_i <= '0';
X2_cwm_i <= '0';
W3_cwm_i <= '0';
main_wfoo0_cwm <= '0';
file_card_i <= '0';
do_q3p_wfoo0 <= '0';
do_file_card_i <= '0';
prev_do_file_card <= '0';
do_q3p_Z0 <= '0';
do_q3p_Y1 <= '0';
do_q3p_X2 <= '0';
do_q3p_W3 <= '0';
do_q3p_debct <= '0';
else
if sysclk'event and sysclk = '1' then
-- pull
debct_pull <= '0';
do_file_card_i <= '0';
----
-- wfoo0
if wfoo0_baz = '1' then
wfoo0_llwln_var <= unsigned(wfoo0_turn);
main_wfoo0_cwm <= '0';
if wfoo0_llwln_var = "00000000000000000000000000000000" then
do_q3p_wfoo0 <= '0';
else
do_q3p_wfoo0 <= '1';
end if;
else
if do_q3p_wfoo0 = '1' and wfoo0_blrb = '1' then
wfoo0_llwln_var <= wfoo0_llwln_var - 1;
if (wfoo0_llwln_var = "00000000000000000000000000000000") then
wfoo0_llwln_var <= unsigned(wfoo0_turn);
if main_wfoo0_cwm = '0' then
wfoo0_cwm <= '1';
main_wfoo0_cwm <= '1';
else
do_file_card_i <= '1';
do_q3p_wfoo0 <= '0';
end if;
end if;
end if;
end if;
if wfoo0_zz1pb = '0' then
wfoo0_cwm <= '0';
end if;
if Z0_baz = '1' then -- counter Baz
Z0_var <= unsigned(Z0_turn);
if Z0_turn = "00000000000000000000000000000000" then
do_q3p_Z0 <= '0';
else
do_q3p_Z0 <= '1';
end if;
else
if do_q3p_Z0 = '1' and Z0_blrb = '1' then
if Z0_bar = '0' then
if Z0_cwm_i = '0' then
if do_q3p_Z0 = '1' then
Z0_var <= Z0_var - 1;
if (Z0_var = "00000000000000000000000000000001") then
Z0_cwm_i <= '1';
do_q3p_Z0 <= '0';
end if;
end if;
end if;
else
Z0_var <= Z0_var - 1;
if (Z0_var = "00000000000000000000000000000000") then
Z0_cwm_i <= '1';
Z0_var <= unsigned(Z0_turn);
end if;
end if; -- Z0_bar
end if;
end if; -- Z0_blrb
if Z0_zz1pb = '0' then
Z0_cwm_i <= '0';
end if;
if Y1_baz = '1' then -- counter Baz
Y1_var <= unsigned(Y1_turn);
if Y1_turn = "00000000000000000000000000000000" then
do_q3p_Y1 <= '0';
else
do_q3p_Y1 <= '1';
end if;
elsif do_q3p_Y1 = '1' and Y1_blrb = '1' then
if Y1_bar = '0' then
if Y1_cwm_i = '0' then
if do_q3p_Y1 = '1' then
Y1_var <= Y1_var - 1;
if (Y1_var = "00000000000000000000000000000001") then
Y1_cwm_i <= '1';
do_q3p_Y1 <= '0';
end if;
end if;
end if;
else
Y1_var <= Y1_var - 1;
if (Y1_var = "00000000000000000000000000000000") then
Y1_cwm_i <= '1';
Y1_var <= unsigned(Y1_turn);
end if;
end if; -- Y1_bar
end if; -- Y1_blrb
if Y1_zz1pb = '0' then
Y1_cwm_i <= '0';
end if;
if X2_baz = '1' then -- counter Baz
X2_var <= unsigned(X2_turn);
if X2_turn = "00000000000000000000000000000000" then
do_q3p_X2 <= '0';
else
do_q3p_X2 <= '1';
end if;
elsif do_q3p_X2 = '1' and X2_blrb = '1' then
if X2_bar = '0' then
if X2_cwm_i = '0' then
if do_q3p_X2 = '1' then
X2_var <= X2_var - 1;
if (X2_var = "00000000000000000000000000000001") then
X2_cwm_i <= '1';
do_q3p_X2 <= '0';
end if;
end if;
end if;
else
X2_var <= X2_var - 1;
if (X2_var = "00000000000000000000000000000000") then --{
X2_cwm_i <= '1';
X2_var <= unsigned(X2_turn);
end if;
end if; --X2_bar
end if; -- X2_blrb
if X2_zz1pb = '0' then
X2_cwm_i <= '0';
end if;
if W3_baz = '1' then -- counter Baz
W3_var <= unsigned(W3_turn);
if W3_turn = "00000000000000000000000000000000" then
do_q3p_W3 <= '0';
else
do_q3p_W3 <= '1';
end if;
elsif do_q3p_W3 = '1' and W3_blrb = '1' then
if W3_bar = '0' then
if W3_cwm_i = '0'then
if do_q3p_W3 = '1' then
W3_var <= W3_var - 1;
if (W3_var = "00000000000000000000000000000001") then
W3_cwm_i <= '1';
do_q3p_W3 <= '0';
end if;
end if;
end if;
else
W3_var <= W3_var - 1;
if (W3_var = "00000000000000000000000000000000") then --{
W3_cwm_i <= '1';
W3_var <= unsigned(W3_turn);
end if;
end if; -- W3_bar
end if; -- W3_blrb
if W3_zz1pb = '0' then
W3_cwm_i <= '0';
end if;
if debct_baz = '1' then -- counter Baz
debct_var <= unsigned(debct_turn);
if debct_turn = "00000000000000000000000000000000" then
do_q3p_debct <= '0';
else
do_q3p_debct <= '1';
end if;
elsif do_q3p_debct = '1' and debct_blrb = '1' then
if debct_bar = '0' then
if debct_cwm_i = '0'then
if do_q3p_debct = '1' then
debct_var <= debct_var - 1;
if (debct_var = "00000000000000000000000000000001") then
debct_cwm_i <= '1';
debct_pull <= '1';
do_q3p_debct <= '0';
end if;
end if;
end if;
else
---- T
-- Continue
debct_var <= debct_var - 1;
-- ending
if (debct_var = "00000000000000000000000000000000") then --{
debct_cwm_i <= '1';
debct_pull <= '1';
debct_var <= unsigned(debct_turn);
end if;
end if; -- debct_bar
end if; -- debct_blrb
-- comment
if debct_zz1pb = '0' then
debct_cwm_i <= '0';
end if;
end if;
end if;
end process;
end rtl;
| apache-2.0 | 43933a060e0347d0c574b196852b9f8a | 0.45516 | 3.00029 | false | false | false | false |
FinnK/lems2hdl | work/N1_iafRefCell/ISIM_output/SynapseModel.vhdl | 1 | 11,618 |
---------------------------------------------------------------------
-- Standard Library bits
---------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- For Modelsim
--use ieee.fixed_pkg.all;
--use ieee.fixed_float_types.ALL;
-- For ISE
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use ieee_proposed.fixed_float_types.ALL;
use IEEE.numeric_std.all;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Entity Description
---------------------------------------------------------------------
entity SynapseModel is
Port (
clk : in STD_LOGIC; --SYSTEM CLOCK, THIS ITSELF DOES NOT SIGNIFY TIME STEPS - AKA A SINGLE TIMESTEP MAY TAKE MANY CLOCK CYCLES
init_model : in STD_LOGIC; --SYNCHRONOUS RESET
step_once_go : in STD_LOGIC; --signals to the neuron from the core that a time step is to be simulated
component_done : out STD_LOGIC;
eventport_in_in : in STD_LOGIC;
requirement_voltage_v : in sfixed (2 downto -22);
param_time_tauDecay : in sfixed (6 downto -18);
param_conductance_gbase : in sfixed (-22 downto -53);
param_voltage_erev : in sfixed (2 downto -22);
param_time_inv_tauDecay_inv : in sfixed (18 downto -6);
exposure_current_i : out sfixed (-28 downto -53);
exposure_conductance_g : out sfixed (-22 downto -53);
statevariable_conductance_g_out : out sfixed (-22 downto -53);
statevariable_conductance_g_in : in sfixed (-22 downto -53);
derivedvariable_current_i_out : out sfixed (-28 downto -53);
derivedvariable_current_i_in : in sfixed (-28 downto -53);
sysparam_time_timestep : in sfixed (-6 downto -22);
sysparam_time_simtime : in sfixed (6 downto -22)
);
end SynapseModel;
---------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-- Architecture Begins
-------------------------------------------------------------------------------------------
architecture RTL of SynapseModel is
signal COUNT : unsigned(2 downto 0) := "000";
signal childrenCombined_Component_done_single_shot_fired : STD_LOGIC := '0';
signal childrenCombined_Component_done_single_shot : STD_LOGIC := '0';
signal childrenCombined_Component_done : STD_LOGIC := '0';
signal Component_done_int : STD_LOGIC := '0';
signal subprocess_der_int_pre_ready : STD_LOGIC := '0';
signal subprocess_der_int_ready : STD_LOGIC := '0';
signal subprocess_der_ready : STD_LOGIC := '0';
signal subprocess_dyn_int_pre_ready : STD_LOGIC := '0';
signal subprocess_dyn_int_ready : STD_LOGIC := '0';
signal subprocess_dyn_ready : STD_LOGIC := '0';
signal subprocess_model_ready : STD_LOGIC := '1';
signal subprocess_all_ready_shotdone : STD_LOGIC := '1';
signal subprocess_all_ready_shot : STD_LOGIC := '0';
signal subprocess_all_ready : STD_LOGIC := '0';signal statevariable_conductance_noregime_g_temp_1 : sfixed (-22 downto -53);
signal statevariable_conductance_noregime_g_temp_1_next : sfixed (-22 downto -53);
---------------------------------------------------------------------
-- Derived Variables and parameters
---------------------------------------------------------------------
signal DerivedVariable_current_i : sfixed (-28 downto -53) := to_sfixed(0.0 ,-28,-53);
signal DerivedVariable_current_i_next : sfixed (-28 downto -53) := to_sfixed(0.0 ,-28,-53);
---------------------------------------------------------------------
---------------------------------------------------------------------
-- EDState internal Variables
---------------------------------------------------------------------
signal statevariable_conductance_g_next : sfixed (-22 downto -53);
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Output Port internal Variables
---------------------------------------------------------------------
signal EventPort_in_in_internal : std_logic := '0';
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Child Components
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Begin Internal Processes
---------------------------------------------------------------------
begin
---------------------------------------------------------------------
-- Child EDComponent Instantiations and corresponding internal variables
---------------------------------------------------------------------
derived_variable_pre_process_comb :process ( sysparam_time_timestep, statevariable_conductance_g_in , requirement_voltage_v , param_voltage_erev )
begin
end process derived_variable_pre_process_comb;
derived_variable_pre_process_syn :process ( clk, init_model )
begin
subprocess_der_int_pre_ready <= '1';
end process derived_variable_pre_process_syn;
--no complex steps in derived variables
subprocess_der_int_ready <= '1';
derived_variable_process_comb :process ( sysparam_time_timestep, statevariable_conductance_g_in , requirement_voltage_v , param_voltage_erev )
begin
derivedvariable_current_i_next <= resize(( statevariable_conductance_g_in * ( param_voltage_erev - requirement_voltage_v ) ),-28,-53);
subprocess_der_ready <= '1';
end process derived_variable_process_comb;
derived_variable_process_syn :process ( clk,init_model )
begin
if clk'event and clk = '1' then
if subprocess_all_ready_shot = '1' then
derivedvariable_current_i <= derivedvariable_current_i_next;
end if;
end if;
end process derived_variable_process_syn;
---------------------------------------------------------------------
dynamics_pre_process_comb :process ( sysparam_time_timestep, param_time_tauDecay, statevariable_conductance_g_in ,param_time_inv_tauDecay_inv )
begin
end process dynamics_pre_process_comb;
dynamics_pre_process_syn :process ( clk, init_model )
begin
subprocess_dyn_int_pre_ready <= '1';
end process dynamics_pre_process_syn;
--No dynamics with complex equations found
subprocess_dyn_int_ready <= '1';
state_variable_process_dynamics_comb :process (sysparam_time_timestep, param_time_tauDecay, statevariable_conductance_g_in ,param_time_inv_tauDecay_inv ,statevariable_conductance_g_in)
begin
statevariable_conductance_noregime_g_temp_1_next <= resize(statevariable_conductance_g_in + ( - statevariable_conductance_g_in * param_time_inv_tauDecay_inv ) * sysparam_time_timestep,-22,-53);
subprocess_dyn_ready <= '1';
end process state_variable_process_dynamics_comb;
state_variable_process_dynamics_syn :process (CLK,init_model)
begin
if clk'event and clk = '1' then
if subprocess_all_ready_shot = '1' then
statevariable_conductance_noregime_g_temp_1 <= statevariable_conductance_noregime_g_temp_1_next;
end if;
end if;
end process state_variable_process_dynamics_syn;
------------------------------------------------------------------------------------------------------
-- EDState Variable Drivers
------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------
-- EDState variable: $par.name Driver Process
---------------------------------------------------------------------
state_variable_process_comb_0 :process (sysparam_time_timestep,init_model,eventport_in_in,statevariable_conductance_g_in,param_conductance_gbase,statevariable_conductance_noregime_g_temp_1,param_time_tauDecay,statevariable_conductance_g_in,param_time_inv_tauDecay_inv)
variable statevariable_conductance_g_temp_1 : sfixed (-22 downto -53);
variable statevariable_conductance_g_temp_2 : sfixed (-22 downto -53);
begin
statevariable_conductance_g_temp_1 := statevariable_conductance_noregime_g_temp_1; if eventport_in_in = '1' then
statevariable_conductance_g_temp_2 := resize( statevariable_conductance_g_in + param_conductance_gbase ,-22,-53);
else
statevariable_conductance_g_temp_2 := statevariable_conductance_g_temp_1;
end if;
statevariable_conductance_g_next <= statevariable_conductance_g_temp_2;
end process;
---------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign state variables to exposures
---------------------------------------------------------------------
exposure_conductance_g <= statevariable_conductance_g_in;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign state variables to output state variables
---------------------------------------------------------------------
statevariable_conductance_g_out <= statevariable_conductance_g_next;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign derived variables to exposures
---------------------------------------------------------------------
exposure_current_i <= derivedvariable_current_i_in;derivedvariable_current_i_out <= derivedvariable_current_i;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Subprocess ready process
---------------------------------------------------------------------
subprocess_all_ready_process: process(step_once_go,subprocess_der_int_ready,subprocess_der_int_pre_ready,subprocess_der_ready,subprocess_dyn_int_pre_ready,subprocess_dyn_int_ready,subprocess_dyn_ready,subprocess_model_ready)
begin
if step_once_go = '0' and subprocess_der_int_ready = '1' and subprocess_der_int_pre_ready = '1'and subprocess_der_ready ='1' and subprocess_dyn_int_ready = '1' and subprocess_dyn_int_pre_ready = '1' and subprocess_dyn_ready = '1' and subprocess_model_ready = '1' then
subprocess_all_ready <= '1';
else
subprocess_all_ready <= '0';
end if;
end process subprocess_all_ready_process;
subprocess_all_ready_shot_process : process(clk)
begin
if rising_edge(clk) then
if (init_model='1') then
subprocess_all_ready_shot <= '0';
subprocess_all_ready_shotdone <= '1';
else
if subprocess_all_ready = '1' and subprocess_all_ready_shotdone = '0' then
subprocess_all_ready_shot <= '1';
subprocess_all_ready_shotdone <= '1';
elsif subprocess_all_ready_shot = '1' then
subprocess_all_ready_shot <= '0';
elsif subprocess_all_ready = '0' then
subprocess_all_ready_shot <= '0';
subprocess_all_ready_shotdone <= '0';
end if;
end if;
end if;
end process subprocess_all_ready_shot_process;
---------------------------------------------------------------------
count_proc:process(clk)
begin
if (clk'EVENT AND clk = '1') then
if init_model = '1' then COUNT <= "001";
component_done_int <= '1';
else if step_once_go = '1' then
COUNT <= "000";
component_done_int <= '0';
elsif COUNT = "001" then
component_done_int <= '1';
elsif subprocess_all_ready_shot = '1' then
COUNT <= COUNT + 1;
component_done_int <= '0';
end if;
end if;
end if;
end process count_proc;
component_done <= component_done_int;
end RTL;
| lgpl-3.0 | 5a5e6facbf5e718f0e43999c037ebd2a | 0.525994 | 4.093728 | false | false | false | false |
Kalycito-open-automation/openPOWERLINK_V2_old_25-06-2014 | hardware/ipcore/common/openmac/src/openfilter-rtl-ea.vhd | 2 | 12,493 | -------------------------------------------------------------------------------
--! @file openfilter-rtl-ea.vhd
--
--! @brief OpenFILTER
--
--! @details This is the openFILTER used for blocking failures on the RMII lines.
--! Note: RxDv and RxDat have to be synchron to iClk
--! The following Conditions are checked:
--! * RxDV >163.64µsec HIGH -> invalid
--! * RxDV <0.64µsec LOW -> invalid
--! * RxDV 4x <5.12µsec HIGH -> invalid
--! * RxDV >5.12µsec HIGH -> valid
--! * iRxError HIGH -> invalid
--! If invalid deactivation of port, until RxDv and iRxError > 10.24µsec low
-------------------------------------------------------------------------------
--
-- (c) B&R, 2013
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
--! use global library
use work.global.all;
--! use openmac package
use work.openmacPkg.all;
entity openfilter is
port (
--! Reset
iRst : in std_logic;
--! RMII Clock
iClk : in std_logic;
--! RMII receive path in
iRx : in tRmiiPath;
--! RMII receive path out
oRx : out tRmiiPath;
--! RMII transmit path in
iTx : in tRmiiPath;
--! RMII transmit path out
oTx : out tRmiiPath;
--! RMII receive error
iRxError : in std_logic
);
end entity openfilter;
architecture rtl of openfilter is
--! Filter FSM type
type tFiltState is (
fs_init,
fs_GAP2short, fs_GAPext, fs_GAPok,
fs_FRMnopre, fs_FRMpre2short, fs_FRMpreOk,
fs_FRM2short, fs_FRMok, fs_FRM2long, fs_BlockAll
);
signal FiltState : tFiltState;
signal RxDel : tRmiiPathArray(3 downto 0);
signal FrameShift : std_logic;
signal LastFrameNOK : std_logic;
signal StCnt : std_logic_vector(13 downto 0);
signal BlockRxPort : std_logic;
begin
---------------------------------------------------------------------------
-- INPUT
---------------------------------------------------------------------------
RxDel(0) <= iRx;
BlockRxPort <= cActivated when (FiltState = fs_FRMnopre or
FiltState = fs_BlockAll or
LastFrameNOK = cActivated) else
cInactivated;
---------------------------------------------------------------------------
-- OUTPUT MUX
---------------------------------------------------------------------------
oRx <= cRmiiPathInit when BlockRxPort = cActivated else
RxDel(3) when FrameShift = cActivated else
RxDel(1);
oTx <= iTx;
doFsm : process(iRst, iClk)
variable RstStCnt : std_logic;
begin
if iRst = cActivated then
StCnt <= (others => cInactivated);
FiltState <= fs_init;
FrameShift <= cInactivated;
RxDel(3 downto 1) <= (others => cRmiiPathInit);
LastFrameNOK <= cInactivated;
elsif rising_edge(iClk) then
RxDel(3 downto 1) <= RxDel(2 downto 0);
-- DEFAULT --
RstStCnt := cInactivated;
case FiltState is
---------------------------------------------------------------
-- INIT
---------------------------------------------------------------
when fs_init =>
FiltState <= fs_GAP2short;
RstStCnt := cActivated;
---------------------------------------------------------------
-- GAP 2 SHORT
---------------------------------------------------------------
when fs_GAP2short =>
FrameShift <= cInactivated;
if StCnt(4) = cActivated then
-- 360ns
FiltState <= fs_GAPext;
end if;
if RxDel(0).enable = cActivated then
-- Gap < 360 ns -> too short -> Block Filter
FiltState <= fs_BlockAll;
RstStCnt := cActivated;
end if;
---------------------------------------------------------------
-- GAP EXTend
---------------------------------------------------------------
when fs_GAPext =>
if StCnt(5 downto 0) = "101110" then
FiltState <= fs_GAPok;
end if;
if RxDel(0).enable = cActivated then
-- GAP [360ns .. 960ns] -> short, but ok -> Start Frame
RstStCnt := cActivated;
FrameShift <= cActivated;
if RxDel(0).data = "01" then
-- GAP > 960ns -> OK -> Start Frame (preamble already beginning)
FiltState <= fs_FRMpre2short;
else
-- GAP > 960ns -> OK -> Start Frame and wait of preamble
FiltState <= fs_FRMnopre;
end if;
end if;
---------------------------------------------------------------
-- GAP OK
---------------------------------------------------------------
when fs_GAPok =>
if RxDel(0).enable = cActivated then
RstStCnt := cActivated;
if RxDel(0).data = "01" then
-- GAP > 960ns -> OK -> Start Frame (preamble already beginning)
FiltState <= fs_FRMpre2short;
else
-- GAP > 960ns -> OK -> Start Frame and wait of preamble
FiltState <= fs_FRMnopre;
end if;
end if;
---------------------------------------------------------------
-- FRAME, BUT STILL NO PREAMBLE
---------------------------------------------------------------
when fs_FRMnopre =>
if (StCnt(5) = cActivated or
RxDel(0).data = "11" or RxDel(0).data = "10" or
(RxDel(0).enable = cInactivated and RxDel(1).enable = cInactivated)) then
-- no preamble for >=660 ns or preamble wrong -> Block Filter
FiltState <= fs_BlockAll;
RstStCnt := cActivated;
elsif RxDel(0).data = "01" then
-- preamble starts -> Check Preamble
FiltState <= fs_FRMpre2short;
RstStCnt := cActivated;
end if;
---------------------------------------------------------------
-- FRAME CHECK PREAMBLE TOO SHORT
---------------------------------------------------------------
when fs_FRMpre2short =>
if (RxDel(0).data /= "01" or (RxDel(0).enable = cInactivated and
RxDel(1).enable = cInactivated)) then
-- preamble wrong -> Block Filter
FiltState <= fs_BlockAll;
RstStCnt := cActivated;
elsif StCnt(3) = cActivated then
-- preamble ok for 180 ns -> Preamble OK
FiltState <= fs_FRMpreOk;
end if;
---------------------------------------------------------------
-- FRAME CHECK PREAMBLE OK
---------------------------------------------------------------
when fs_FRMpreOk =>
if RxDel(0).data /= "01" then
-- preamble done -> Start Frame
FiltState <= fs_FRMok;
end if;
if ((StCnt(5) = cActivated and StCnt(2) = cActivated) or
(RxDel(0).enable = cInactivated and RxDel(1).enable = cInactivated)) then
-- preamble to long for 740 ns -> Block Filter
FiltState <= fs_BlockAll;
RstStCnt := cActivated;
end if;
-- preamble is OK
LastFrameNOK <= cInactivated;
---------------------------------------------------------------
-- FRAME OK
---------------------------------------------------------------
when fs_FRMok =>
if StCnt(13) = cActivated then
-- FRAME > 163,842 us -> too long -> Block Filter
FiltState <= fs_BlockAll;
RstStCnt := cActivated;
end if;
if RxDel(0).enable = cInactivated and RxDel(1).enable = cInactivated then
-- FRAME [163,842 us] -> OK -> Start GAP
FiltState <= fs_GAP2short;
RstStCnt := cActivated;
end if;
---------------------------------------------------------------
-- BLOCK FILTER
---------------------------------------------------------------
when fs_BlockAll =>
if StCnt(2) = cActivated then
-- Block for 100 nsec
FiltState <= fs_GAP2short;
RstStCnt := cActivated;
end if;
if RxDel(0).enable = cActivated then
-- Rxdv != cInactivated -> Reset Wait Period
RstStCnt := cActivated;
end if;
-- block next rx frame (until receive a valid preamble)
LastFrameNOK <= cActivated;
when others =>
FiltState <= fs_init;
end case;
if iRxError = cActivated then
-- iRxError -> Block Filter
FiltState <= fs_BlockAll;
RstStCnt := cActivated;
end if;
-- State Counter --
StCnt <= std_logic_vector(unsigned(StCnt) + 1);
if RstStCnt = cActivated then
StCnt <= (others => cInactivated);
end if;
end if;
end process;
end rtl;
| gpl-2.0 | bd4bb6657c5aca9013c103238e7e545e | 0.41031 | 6.079319 | false | false | false | false |
Kalycito-open-automation/openPOWERLINK_V2_old_25-06-2014 | hardware/ipcore/altera/fifo/src/asyncFifo-syn-a.vhd | 2 | 3,712 | -------------------------------------------------------------------------------
--! @file asyncFifo-syn-a.vhd
--
--! @brief The asynchronous Fifo architecture for Altera
--
--! @details This is a dual clock fifo generated in Megawizard!
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2013
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! use altera_mf library
library altera_mf;
use altera_mf.altera_mf_components.all;
architecture syn of asyncFifo is
begin
theAlteraDcFifo : dcfifo
generic map (
intended_device_family => "Cyclone IV E",
lpm_width => gDataWidth,
lpm_widthu => logDualis(gWordSize),
lpm_numwords => gWordSize,
lpm_showahead => "OFF",
lpm_type => "DCFIFO",
overflow_checking => "ON",
underflow_checking => "ON",
delay_rdusedw => 1,
delay_wrusedw => 1,
add_usedw_msb_bit => "OFF",
rdsync_delaypipe => gSyncStages+2,
wrsync_delaypipe => gSyncStages+2,
use_eab => gMemRes,
write_aclr_synch => "ON",
read_aclr_synch => "ON",
clocks_are_synchronized => "FALSE",
add_ram_output_register => "ON"
)
port map (
aclr => iAclr,
data => iWrData,
q => oRdData,
rdclk => iRdClk,
rdempty => oRdEmpty,
rdfull => oRdFull,
rdreq => iRdReq,
rdusedw => oRdUsedw,
wrclk => iWrClk,
wrempty => oWrEmpty,
wrfull => oWrFull,
wrreq => iWrReq,
wrusedw => oWrUsedw
);
end architecture syn;
| gpl-2.0 | 1f4c5dddb6ab6d0eca746296428f4c9f | 0.548222 | 4.910053 | false | false | false | false |
hoglet67/AtomGodilVideo | src/mouse/mouse_controller.vhd | 1 | 43,589 | ------------------------------------------------------------------------
-- mouse_controller.vhd
------------------------------------------------------------------------
-- Author : Ulrich Zoltán
-- Copyright 2006 Digilent, Inc.
------------------------------------------------------------------------
-- Software version : Xilinx ISE 7.1.04i
-- WebPack
-- Device : 3s200ft256-4
------------------------------------------------------------------------
-- This file contains a controller for a ps/2 compatible mouse device.
-- This controller is a client for the ps2interface module.
------------------------------------------------------------------------
-- Behavioral description
------------------------------------------------------------------------
-- Please read the following article on the web for understanding how
-- to interface a ps/2 mouse:
-- http://www.computer-engineering.org/ps2mouse/
-- This controller is implemented as described in the above article.
-- The mouse controller receives bytes from the ps2interface which, in
-- turn, receives them from the mouse device. Data is received on the
-- rx_data input port, and is validated by the read signal. read is
-- active for one clock period when new byte available on rx_data. Data
-- is sent to the ps2interface on the tx_data output port and validated
-- by the write output signal. 'write' should be active for one clock
-- period when tx_data contains the command or data to be sent to the
-- mouse. ps2interface wraps the byte in a 11 bits packet that is sent
-- through the ps/2 port using the ps/2 protocol. Similarly, when the
-- mouse sends data, the ps2interface receives 11 bits for every byte,
-- extracts the byte from the ps/2 frame, puts it on rx_data and
-- activates read for one clock period. If an error occurs when sending
-- or receiving a frame from the mouse, the err input goes high for one
-- clock period. When this occurs, the controller enters reset state.
-- When in reset state, the controller resets the mouse and begins an
-- initialization procedure that consists of tring to put mouse in
-- scroll mode (enables wheel if the mouse has one), setting the
-- resolution of the mouse, the sample rate and finally enables
-- reporting. Implicitly the mouse, after a reset or imediately after a
-- reset, does not send data packets on its own. When reset(or power-up)
-- the mouse enters reset state, where it performs a test, called the
-- bat test (basic assurance test), when this test is done, it sends
-- the result: AAh for test ok, FCh for error. After this it sends its
-- ID which is 00h. When this is done, the mouse enters stream mode,
-- but with reporting disabled (movement data packets are not sent).
-- To enable reporting the enable data reporting command (F4h) must be
-- sent to the mouse. After this command is sent, the mouse will send
-- movement data packets when the mouse is moved or the status of the
-- button changes.
-- After sending a command or a byte following a command, the mouse
-- must respond with ack (FAh). For managing the intialization
-- procedure and receiving the movement data packets, a FSM is used.
-- When the fpga is powered up or the logic is reset using the global
-- reset, the FSM enters reset state. From this state, the FSM will
-- transition to a series of states used to initialize the mouse. When
-- initialization is complete, the FSM remains in state read_byte_1,
-- waiting for a movement data packet to be sent. This is the idle
-- state if the FSM. When a byte is received in this state, this is
-- the first byte of the 3 bytes sent in a movement data packet (4 bytes
-- if mouse in scrolling mode). After reading the last byte from the
-- packet, the FSM enters mark_new_event state and sets new_event high.
-- After that FSM enterss read_byte_1 state, resets new_event and waits
-- for a new packet.
-- After a packet is received, new_event is set high for one clock
-- period to "inform" the clients of this controller a new packet was
-- received and processed.
-- During the initialization procedure, the controller tries to put the
-- mouse in scroll mode (activates wheel, if mouse has one). This is
-- done by successively setting the sample rate to 200, then to 100, and
-- lastly to 80. After this is done, the mouse ID is requested by
-- sending get device ID command (F2h). If the received ID is 00h than
-- the mouse does not have a wheel. If the received ID is 03h than the
-- mouse is in scroll mode, and when sending movement data packets
-- (after enabling data reporting) it will include z movement data.
-- If the mouse is in normal, non-scroll mode, the movement data packet
-- consists of 3 successive bytes. This is their format:
--
--
--
-- bits 7 6 5 4 3 2 1 0
-- -------------------------------------------------
-- byte 1 | YOVF| XOVF|YSIGN|XSIGN| 1 | MBTN| RBTN| LBTN|
-- -------------------------------------------------
-- -------------------------------------------------
-- byte 2 | X MOVEMENT |
-- -------------------------------------------------
-- -------------------------------------------------
-- byte 3 | Y MOVEMENT |
-- -------------------------------------------------
-- OVF = overflow
-- BTN = button
-- M = middle
-- R = right
-- L = left
--
-- When scroll mode is enabled, the mouse send 4 byte movement packets.
-- bits 7 6 5 4 3 2 1 0
-- -------------------------------------------------
-- byte 1 | YOVF| XOVF|YSIGN|XSIGN| 1 | MBTN| RBTN| LBTN|
-- -------------------------------------------------
-- -------------------------------------------------
-- byte 2 | X MOVEMENT |
-- -------------------------------------------------
-- -------------------------------------------------
-- byte 3 | Y MOVEMENT |
-- -------------------------------------------------
-- -------------------------------------------------
-- byte 4 | Z MOVEMENT |
-- -------------------------------------------------
-- x and y movement counters are represented on 8 bits, 2's complement
-- encoding. The first bit (sign bit) of the counters are the xsign and
-- ysign bit from the first packet, the rest of the bits are the second
-- byte for the x movement and the third byte for y movement. For the
-- z movement the range is -8 -> +7 and only the 4 least significant
-- bits from z movement are valid, the rest are sign extensions.
-- The x and y movements are in range: -256 -> +255
-- The mouse uses as axes origin the lower-left corner. For the purpose
-- of displaying a mouse cursor on the screen, the controller inverts
-- the y axis to move the axes origin in the upper-left corner. This
-- is done by negating the y movement value (following the 2s complement
-- encoding). The movement data received from the mouse are delta
-- movements, the data represents the movement of the mouse relative
-- to the last position. The controller keeps track of the position of
-- the mouse relative to the upper-left corner. This is done by keeping
-- the mouse position in two registers x_pos and y_pos and adding the
-- delta movements to their value. The addition uses saturation. That
-- means the value of the mouse position will not exceed certain bounds
-- and will not rollover the a margin. For example, if the mouse is at
-- the left margin and is moved left, the x position remains at the left
-- margin(0). The lower bound is always 0 for both x and y movement.
-- The upper margin can be set using input pins: value, setmax_x,
-- setmax_y. To set the upper bound of the x movement counter, the new
-- value is placed on the value input pins and setmax_x is activated
-- for at least one clock period. Similarly for y movement counter, but
-- setmax_y is activated instead. Notice that value has 10 bits, and so
-- the maximum value for a bound is 1023.
-- The position of the mouse (x_pos and y_pos) can be set at any time,
-- by placing the x or y position on the value input pins and activating
-- the setx, or sety respectively, for at least one clock period. This
-- is useful for setting an original position of the mouse different
-- from (0,0).
------------------------------------------------------------------------
-- Port definitions
------------------------------------------------------------------------
-- clk - global clock signal (100MHz)
-- rst - global reset signal
-- read - input pin, from ps2interface
-- - active one clock period when new data received
-- - and available on rx_data
-- err - input pin, from ps2interface
-- - active one clock period when error occurred when
-- - receiving or sending data.
-- rx_data - input pin, 8 bits, from ps2interface
-- - the byte received from the mouse.
-- xpos - output pin, 10 bits
-- - the x position of the mouse relative to the upper
-- - left corner
-- ypos - output pin, 10 bits
-- - the y position of the mouse relative to the upper
-- - left corner
-- zpos - output pin, 4 bits
-- - last delta movement on z axis
-- left - output pin, high if the left mouse button is pressed
-- middle - output pin, high if the middle mouse button is
-- - pressed
-- right - output pin, high if the right mouse button is
-- - pressed
-- new_event - output pin, active one clock period after receiving
-- - and processing one movement data packet.
-- tx_data - output pin, 8 bits, to ps2interface
-- - byte to be sent to the mouse
-- write - output pin, to ps2interface
-- - active one clock period when sending a byte to the
-- - ps2interface.
------------------------------------------------------------------------
-- Revision History:
-- 09/18/2006(UlrichZ): created
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- simulation library
--library UNISIM;
--use UNISIM.VComponents.all;
-- the mouse_controller entity declaration
-- read above for behavioral description and port definitions.
entity mouse_controller is
port(
clk : in std_logic;
rst : in std_logic;
read : in std_logic;
err : in std_logic;
rx_data : in std_logic_vector(7 downto 0);
xpos : out std_logic_vector(9 downto 0);
ypos : out std_logic_vector(9 downto 0);
zpos : out std_logic_vector(3 downto 0);
left : out std_logic;
middle : out std_logic;
right : out std_logic;
new_event : out std_logic;
tx_data : out std_logic_vector(7 downto 0);
write : out std_logic;
value : in std_logic_vector(9 downto 0);
setx : in std_logic;
sety : in std_logic;
setmax_x : in std_logic;
setmax_y : in std_logic
);
end mouse_controller;
architecture Behavioral of mouse_controller is
------------------------------------------------------------------------
-- CONSTANTS
------------------------------------------------------------------------
-- constants defining commands to send or received from the mouse
constant FA: std_logic_vector(7 downto 0) := "11111010"; -- 0xFA(ACK)
constant FF: std_logic_vector(7 downto 0) := "11111111"; -- 0xFF(RESET)
constant AA: std_logic_vector(7 downto 0) := "10101010"; -- 0xAA(BAT_OK)
constant OO: std_logic_vector(7 downto 0) := "00000000"; -- 0x00(ID)
-- (atention: name is 2 letters O not zero)
-- command to read id
constant READ_ID : std_logic_vector(7 downto 0) := x"F2";
-- command to enable mouse reporting
-- after this command is sent, the mouse begins sending data packets
constant ENABLE_REPORTING : std_logic_vector(7 downto 0) := x"F4";
-- command to set the mouse resolution
constant SET_RESOLUTION : std_logic_vector(7 downto 0) := x"E8";
-- the value of the resolution to send after sending SET_RESOLUTION
constant RESOLUTION : std_logic_vector(7 downto 0) := x"03";
-- (8 counts/mm)
-- command to set the mouse sample rate
constant SET_SAMPLE_RATE : std_logic_vector(7 downto 0) := x"F3";
-- the value of the sample rate to send after sending SET_SAMPLE_RATE
constant SAMPLE_RATE : std_logic_vector(7 downto 0) := x"28";
-- (40 samples/s)
-- default maximum value for the horizontal mouse position
constant DEFAULT_MAX_X : std_logic_vector(9 downto 0) := "1001111111";
-- 639
-- default maximum value for the vertical mouse position
constant DEFAULT_MAX_Y : std_logic_vector(9 downto 0) := "0111011111";
-- 479
------------------------------------------------------------------------
-- SIGNALS
------------------------------------------------------------------------
-- after doing the enable scroll mouse procedure, if the ID returned by
-- the mouse is 03 (scroll mouse enabled) then this register will be set
-- If '1' then the mouse is in scroll mode, else mouse is in simple
-- mouse mode.
signal haswheel: std_logic := '0';
-- horizontal and veritcal mouse position
-- origin of axes is upper-left corner
-- the origin of axes the mouse uses is the lower-left corner
-- The y-axis is inverted, by making negative the y movement received
-- from the mouse (if it was positive it becomes negative
-- and vice versa)
signal x_pos,y_pos: std_logic_vector(10 downto 0) := (others => '0');
-- active when an overflow occurred on the x and y axis
-- bits 6 and 7 from the first byte received from the mouse
signal x_overflow,y_overflow: std_logic := '0';
-- active when the x,y movement is negative
-- bits 4 and 5 from the first byte received from the mouse
signal x_sign,y_sign: std_logic := '0';
-- 2's complement value for incrementing the x_pos,y_pos
-- y_inc is the negated value from the mouse in the third byte
signal x_inc,y_inc: std_logic_vector(7 downto 0) := (others => '0');
-- active for one clock period, indicates new delta movement received
-- on x,y axis
signal x_new,y_new: std_logic := '0';
-- maximum value for x and y position registers(x_pos,y_pos)
signal x_max,y_max: std_logic_vector(9 downto 0) := (others => '0');
-- active when left,middle,right mouse button is down
signal left_down,middle_down,right_down: std_logic := '0';
-- the FSM states
-- states that begin with "reset" are part of the reset procedure.
-- states that end in "_wait_ack" are states in which ack is waited
-- as response to sending a byte to the mouse.
-- read behavioral description above for details.
type fsm_state is
(
reset,reset_wait_ack,reset_wait_bat_completion,reset_wait_id,
reset_set_sample_rate_200,reset_set_sample_rate_200_wait_ack,
reset_send_sample_rate_200,reset_send_sample_rate_200_wait_ack,
reset_set_sample_rate_100,reset_set_sample_rate_100_wait_ack,
reset_send_sample_rate_100,reset_send_sample_rate_100_wait_ack,
reset_set_sample_rate_80,reset_set_sample_rate_80_wait_ack,
reset_send_sample_rate_80,reset_send_sample_rate_80_wait_ack,
reset_read_id,reset_read_id_wait_ack,reset_read_id_wait_id,
reset_set_resolution,reset_set_resolution_wait_ack,
reset_send_resolution,reset_send_resolution_wait_ack,
reset_set_sample_rate_40,reset_set_sample_rate_40_wait_ack,
reset_send_sample_rate_40,reset_send_sample_rate_40_wait_ack,
reset_enable_reporting,reset_enable_reporting_wait_ack,
read_byte_1,read_byte_2,read_byte_3,read_byte_4,mark_new_event
);
-- holds current state of the FSM
signal state: fsm_state := reset;
begin
-- left output the state of the left_down register
left <= left_down when rising_edge(clk);
-- middle output the state of the middle_down register
middle <= middle_down when rising_edge(clk);
-- right output the state of the right_down register
right <= right_down when rising_edge(clk);
-- xpos output is the horizontal position of the mouse
-- it has the range: 0-x_max
xpos <= x_pos(9 downto 0) when rising_edge(clk);
-- ypos output is the vertical position of the mouse
-- it has the range: 0-y_max
ypos <= y_pos(9 downto 0) when rising_edge(clk);
-- sets the value of x_pos from another module when setx is active
-- else, computes the new x_pos from the old position when new x
-- movement detected by adding the delta movement in x_inc, or by
-- adding 256 or -256 when overflow occurs.
set_x: process(clk)
variable x_inter: std_logic_vector(10 downto 0);
variable inc: std_logic_vector(10 downto 0);
begin
if(rising_edge(clk)) then
-- if setx active, set new x_pos value
if(setx = '1') then
x_pos <= '0' & value;
-- if delta movement received from mouse
elsif(x_new = '1') then
-- if negative movement on x axis
if(x_sign = '1') then
-- if overflow occurred
if(x_overflow = '1') then
-- inc is -256
inc := "11100000000";
else
-- inc is sign extended x_inc
inc := "111" & x_inc;
end if;
-- intermediary horizontal position
x_inter := x_pos + inc;
-- if first bit of x_inter is 1
-- then negative overflow occurred and
-- new x position is 0.
-- Note: x_pos and x_inter have 11 bits,
-- and because xpos has only 10, when
-- first bit becomes 1, this is considered
-- a negative number when moving left
if(x_inter(10) = '1') then
x_pos <= (others => '0');
else
x_pos <= x_inter;
end if;
-- if positive movement on x axis
else
-- if overflow occurred
if(x_overflow = '1') then
-- inc is 256
inc := "00100000000";
else
-- inc is sign extended x_inc
inc := "000" & x_inc;
end if;
-- intermediary horizontal position
x_inter := x_pos + inc;
-- if x_inter is greater than x_max
-- then positive overflow occurred and
-- new x position is x_max.
if(x_inter > ('0' & x_max)) then
x_pos <= '0' & x_max;
else
x_pos <= x_inter;
end if;
end if;
end if;
end if;
end process set_x;
-- sets the value of y_pos from another module when sety is active
-- else, computes the new y_pos from the old position when new y
-- movement detected by adding the delta movement in y_inc, or by
-- adding 256 or -256 when overflow occurs.
set_y: process(clk)
variable y_inter: std_logic_vector(10 downto 0);
variable inc: std_logic_vector(10 downto 0);
begin
if(rising_edge(clk)) then
-- if sety active, set new y_pos value
if(sety = '1') then
y_pos <= '0' & value;
-- if delta movement received from mouse
elsif(y_new = '1') then
-- if negative movement on y axis
-- Note: axes origin is upper-left corner
if(y_sign = '1') then
-- if overflow occurred
if(y_overflow = '1') then
-- inc is -256
inc := "11100000000";
else
-- inc is sign extended y_inc
inc := "111" & y_inc;
end if;
-- intermediary vertical position
y_inter := y_pos + inc;
-- if first bit of y_inter is 1
-- then negative overflow occurred and
-- new y position is 0.
-- Note: y_pos and y_inter have 11 bits,
-- and because ypos has only 10, when
-- first bit becomes 1, this is considered
-- a negative number when moving upward
if(y_inter(10) = '1') then
y_pos <= (others => '0');
else
y_pos <= y_inter;
end if;
-- if positive movement on y axis
else
-- if overflow occurred
if(y_overflow = '1') then
-- inc is 256
inc := "00100000000";
else
-- inc is sign extended y_inc
inc := "000" & y_inc;
end if;
-- intermediary vertical position
y_inter := y_pos + inc;
-- if y_inter is greater than y_max
-- then positive overflow occurred and
-- new y position is y_max.
if(y_inter > ('0' & y_max)) then
y_pos <= '0' & y_max;
else
y_pos <= y_inter;
end if;
end if;
end if;
end if;
end process set_y;
-- sets the maximum value of the x movement register, stored in x_max
-- when setmax_x is active, max value should be on value input pin
set_max_x: process(clk,rst)
begin
if(rising_edge(clk)) then
if(rst = '1') then
x_max <= DEFAULT_MAX_X;
elsif(setmax_x = '1') then
x_max <= value;
end if;
end if;
end process set_max_x;
-- sets the maximum value of the y movement register, stored in y_max
-- when setmax_y is active, max value should be on value input pin
set_max_y: process(clk,rst)
begin
if(rising_edge(clk)) then
if(rst = '1') then
y_max <= DEFAULT_MAX_Y;
elsif(setmax_y = '1') then
y_max <= value;
end if;
end if;
end process set_max_y;
-- Synchronous one process fsm to handle the communication
-- with the mouse.
-- When reset and at start-up it enters reset state
-- where it begins the procedure of initializing the mouse.
-- After initialization is complete, it waits packets from
-- the mouse.
-- Read at Behavioral decription for details.
manage_fsm: process(clk,rst)
begin
-- when reset occurs, give signals default values.
if(rst = '1') then
state <= reset;
haswheel <= '0';
x_overflow <= '0';
y_overflow <= '0';
x_sign <= '0';
y_sign <= '0';
x_inc <= (others => '0');
y_inc <= (others => '0');
x_new <= '0';
y_new <= '0';
new_event <= '0';
left_down <= '0';
middle_down <= '0';
right_down <= '0';
elsif(rising_edge(clk)) then
-- at every rising edge of the clock, this signals
-- are reset, thus assuring that they are active
-- for one clock period only if a state sets then
-- because the fsm will transition from the state
-- that set them on the next rising edge of clock.
write <= '0';
x_new <= '0';
y_new <= '0';
case state is
-- if just powered-up, reset occurred or some error in
-- transmision encountered, then fsm will transition to
-- this state. Here the RESET command (FF) is sent to the
-- mouse, and various signals receive their default values
-- From here the FSM transitions to a series of states that
-- perform the mouse initialization procedure. All this
-- state are prefixed by "reset_". After sending a byte
-- to the mouse, it respondes by sending ack (FA). All
-- states that wait ack from the mouse are postfixed by
-- "_wait_ack".
-- Read at Behavioral decription for details.
when reset =>
haswheel <= '0';
x_overflow <= '0';
y_overflow <= '0';
x_sign <= '0';
y_sign <= '0';
x_inc <= (others => '0');
y_inc <= (others => '0');
x_new <= '0';
y_new <= '0';
left_down <= '0';
middle_down <= '0';
right_down <= '0';
tx_data <= FF;
write <= '1';
state <= reset_wait_ack;
-- wait ack for the reset command.
-- when received transition to reset_wait_bat_completion.
-- if error occurs go to reset state.
when reset_wait_ack =>
if(read = '1') then
-- if received ack
if(rx_data = FA) then
state <= reset_wait_bat_completion;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_wait_ack;
end if;
-- wait for bat completion test
-- mouse should send AA if test is successful
when reset_wait_bat_completion =>
if(read = '1') then
if(rx_data = AA) then
state <= reset_wait_id;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_wait_bat_completion;
end if;
-- the mouse sends its id after performing bat test
-- the mouse id should be 00
when reset_wait_id =>
if(read = '1') then
if(rx_data = OO) then
state <= reset_set_sample_rate_200;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_wait_id;
end if;
-- with this state begins the enable wheel mouse
-- procedure. The procedure consists of setting
-- the sample rate of the mouse first 200, then 100
-- then 80. After this is done, the mouse id is
-- requested and if the mouse id is 03, then
-- mouse is in wheel mode and will send 4 byte packets
-- when reporting is enabled.
-- If the id is 00, the mouse does not have a wheel
-- and will send 3 byte packets when reporting is enabled.
-- This state issues the set_sample_rate command to the
-- mouse.
when reset_set_sample_rate_200 =>
tx_data <= SET_SAMPLE_RATE;
write <= '1';
state <= reset_set_sample_rate_200_wait_ack;
-- wait ack for set sample rate command
when reset_set_sample_rate_200_wait_ack =>
if(read = '1') then
if(rx_data = FA) then
state <= reset_send_sample_rate_200;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_set_sample_rate_200_wait_ack;
end if;
-- send the desired sample rate (200 = 0xC8)
when reset_send_sample_rate_200 =>
tx_data <= "11001000"; -- 0xC8
write <= '1';
state <= reset_send_sample_rate_200_wait_ack;
-- wait ack for sending the sample rate
when reset_send_sample_rate_200_wait_ack =>
if(read = '1') then
if(rx_data = FA) then
state <= reset_set_sample_rate_100;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_send_sample_rate_200_wait_ack;
end if;
-- send the sample rate command
when reset_set_sample_rate_100 =>
tx_data <= SET_SAMPLE_RATE;
write <= '1';
state <= reset_set_sample_rate_100_wait_ack;
-- wait ack for sending the sample rate command
when reset_set_sample_rate_100_wait_ack =>
if(read = '1') then
if(rx_data = FA) then
state <= reset_send_sample_rate_100;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_set_sample_rate_100_wait_ack;
end if;
-- send the desired sample rate (100 = 0x64)
when reset_send_sample_rate_100 =>
tx_data <= "01100100"; -- 0x64
write <= '1';
state <= reset_send_sample_rate_100_wait_ack;
-- wait ack for sending the sample rate
when reset_send_sample_rate_100_wait_ack =>
if(read = '1') then
if(rx_data = FA) then
state <= reset_set_sample_rate_80;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_send_sample_rate_100_wait_ack;
end if;
-- send set sample rate command
when reset_set_sample_rate_80 =>
tx_data <= SET_SAMPLE_RATE;
write <= '1';
state <= reset_set_sample_rate_80_wait_ack;
-- wait ack for sending the sample rate command
when reset_set_sample_rate_80_wait_ack =>
if(read = '1') then
if(rx_data = FA) then
state <= reset_send_sample_rate_80;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_set_sample_rate_80_wait_ack;
end if;
-- send desired sample rate (80 = 0x50)
when reset_send_sample_rate_80 =>
tx_data <= "01010000"; -- 0x50
write <= '1';
state <= reset_send_sample_rate_80_wait_ack;
-- wait ack for sending the sample rate
when reset_send_sample_rate_80_wait_ack =>
if(read = '1') then
if(rx_data = FA) then
state <= reset_read_id;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_send_sample_rate_80_wait_ack;
end if;
-- now the procedure for enabling wheel mode is done
-- the mouse id is read to determine is mouse is in
-- wheel mode.
-- Read ID command is sent to the mouse.
when reset_read_id =>
tx_data <= READ_ID;
write <= '1';
state <= reset_read_id_wait_ack;
-- wait ack for sending the read id command
when reset_read_id_wait_ack =>
if(read = '1') then
if(rx_data = FA) then
state <= reset_read_id_wait_id;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_read_id_wait_ack;
end if;
-- received the mouse id
-- if the id is 00, then the mouse does not have
-- a wheel and haswheel is reset
-- if the id is 03, then the mouse is in scroll mode
-- and haswheel is set.
-- if anything else is received or an error occurred
-- then the FSM transitions to reset state.
when reset_read_id_wait_id =>
if(read = '1') then
if(rx_data = "000000000") then
-- the mouse does not have a wheel
haswheel <= '0';
state <= reset_set_resolution;
elsif(rx_data = "00000011") then -- 0x03
-- the mouse is in scroll mode
haswheel <= '1';
state <= reset_set_resolution;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_read_id_wait_id;
end if;
-- send the set resolution command to the mouse
when reset_set_resolution =>
tx_data <= SET_RESOLUTION;
write <= '1';
state <= reset_set_resolution_wait_ack;
-- wait ack for sending the set resolution command
when reset_set_resolution_wait_ack =>
if(read = '1') then
if(rx_data = FA) then
state <= reset_send_resolution;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_set_resolution_wait_ack;
end if;
-- send the desired resolution (0x03 = 8 counts/mm)
when reset_send_resolution =>
tx_data <= RESOLUTION;
write <= '1';
state <= reset_send_resolution_wait_ack;
-- wait ack for sending the resolution
when reset_send_resolution_wait_ack =>
if(read = '1') then
if(rx_data = FA) then
state <= reset_set_sample_rate_40;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_send_resolution_wait_ack;
end if;
-- send the set sample rate command
when reset_set_sample_rate_40 =>
tx_data <= SET_SAMPLE_RATE;
write <= '1';
state <= reset_set_sample_rate_40_wait_ack;
-- wait ack for sending the set sample rate command
when reset_set_sample_rate_40_wait_ack =>
if(read = '1') then
if(rx_data = FA) then
state <= reset_send_sample_rate_40;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_set_sample_rate_40_wait_ack;
end if;
-- send the desired sampele rate.
-- 40 samples per second is sent.
when reset_send_sample_rate_40 =>
tx_data <= SAMPLE_RATE;
write <= '1';
state <= reset_send_sample_rate_40_wait_ack;
-- wait ack for sending the sample rate
when reset_send_sample_rate_40_wait_ack =>
if(read = '1') then
if(rx_data = FA) then
state <= reset_enable_reporting;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_send_sample_rate_40_wait_ack;
end if;
-- in this state enable reporting command is sent
-- to the mouse. Before this point, the mouse
-- does not send packets. Only after issuing this
-- command, the mouse begins sending data packets,
-- 3 byte packets if it doesn't have a wheel and
-- 4 byte packets if it is in scroll mode.
when reset_enable_reporting =>
tx_data <= ENABLE_REPORTING;
write <= '1';
state <= reset_enable_reporting_wait_ack;
-- wait ack for sending the enable reporting command
when reset_enable_reporting_wait_ack =>
if(read = '1') then
if(rx_data = FA) then
state <= read_byte_1;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_enable_reporting_wait_ack;
end if;
-- this is idle state of the FSM after the
-- initialization is complete.
-- Here the first byte of a packet is waited.
-- The first byte contains the state of the
-- buttons, the sign of the x and y movement
-- and overflow information about these movements
-- First byte looks like this:
-- 7 6 5 4 3 2 1 0
------------------------------------------------------
-- | Y OVF | X OVF | Y SIGN | X SIGN | 1 | M | R | L |
------------------------------------------------------
when read_byte_1 =>
-- reset new_event when back in idle state.
new_event <= '0';
-- reset last z delta movement
zpos <= (others => '0');
if(read = '1') then
-- mouse button states
left_down <= rx_data(0);
middle_down <= rx_data(2);
right_down <= rx_data(1);
-- sign of the movement data
x_sign <= rx_data(4);
-- y sign is changed to invert the y axis
-- because the mouse uses the lower-left corner
-- as axes origin and it is placed in the upper-left
-- corner by this inversion (suitable for displaying
-- a mouse cursor on the screen).
-- y movement data from the third packet must be
-- also negated.
y_sign <= not rx_data(5);
-- overflow status of the x and y movement
x_overflow <= rx_data(6);
y_overflow <= rx_data(7);
-- transition to state read_byte_2
state <= read_byte_2;
else
-- no byte received yet.
state <= read_byte_1;
end if;
-- wait the second byte of the packet
-- this byte contains the x movement counter.
when read_byte_2 =>
if(read = '1') then
-- put the delta movement in x_inc
x_inc <= rx_data;
-- signal the arrival of new x movement data.
x_new <= '1';
-- go to state read_byte_3.
state <= read_byte_3;
elsif(err = '1') then
state <= reset;
else
-- byte not received yet.
state <= read_byte_2;
end if;
-- wait the third byte of the data, that
-- contains the y data movement counter.
-- negate its value, for the axis to be
-- inverted.
-- If mouse is in scroll mode, transition
-- to read_byte_4, else go to mark_new_event
when read_byte_3 =>
if(read = '1') then
-- when y movement is 0, then ignore
if(rx_data /= "00000000") then
-- 2's complement positive numbers
-- become negative and vice versa
y_inc <= (not rx_data) + "00000001";
y_new <= '1';
end if;
-- if the mouse has a wheel then transition
-- to read_byte_4, else go to mark_new_event
if(haswheel = '1') then
state <= read_byte_4;
else
state <= mark_new_event;
end if;
elsif(err = '1') then
state <= reset;
else
state <= read_byte_3;
end if;
-- only reached when mouse is in scroll mode
-- wait for the fourth byte to arrive
-- fourth byte contains the z movement counter
-- only least significant 4 bits are relevant
-- the rest are sign extension.
when read_byte_4 =>
if(read = '1') then
-- zpos is the delta movement on z
zpos <= rx_data(3 downto 0);
-- packet completly received,
-- go to mark_new_event
state <= mark_new_event;
elsif(err = '1') then
state <= reset;
else
state <= read_byte_4;
end if;
-- set new_event high
-- it will be reset in next state
-- informs client new packet received and processed
when mark_new_event =>
new_event <= '1';
state <= read_byte_1;
-- if invalid transition occurred, reset
when others =>
state <= reset;
end case;
end if;
end process manage_fsm;
end Behavioral;
| apache-2.0 | 484c954485f1320dd985997c5390fecb | 0.493886 | 4.532023 | false | false | false | false |
sergev/vak-opensource | hardware/dlx/reg_2_out-behaviour.vhdl | 1 | 1,728 | --------------------------------------------------------------------------
--
-- Copyright (C) 1993, Peter J. Ashenden
-- Mail: Dept. Computer Science
-- University of Adelaide, SA 5005, Australia
-- e-mail: [email protected]
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 1, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
--------------------------------------------------------------------------
--
-- $RCSfile: reg_2_out-behaviour.vhdl,v $ $Revision: 2.1 $ $Date: 1993/11/02 19:09:21 $
--
--------------------------------------------------------------------------
--
-- Behavioural architecture of register with two tri-state outputs.
--
architecture behaviour of reg_2_out is
begin
reg: process (d, latch_en, out_en1, out_en2)
variable latched_value : dlx_word;
begin
if latch_en = '1' then
latched_value := d;
end if;
if out_en1 = '1' then
q1 <= latched_value after Tpd;
else
q1 <= null after Tpd;
end if;
if out_en2 = '1' then
q2 <= latched_value after Tpd;
else
q2 <= null after Tpd;
end if;
end process reg;
end behaviour;
| apache-2.0 | c810d4cfe89b989358324289b2499682 | 0.583912 | 3.823009 | false | false | false | false |
Rookfighter/fft-spartan6 | fft/fft16_tb2.vhd | 1 | 5,264 | -- fft16_tb.vhd
--
-- Created on: 19 Jul 2017
-- Author: Fabian Meyer
--
-- This testbench simulates a 16-Point FFT automatically. It prints out the
-- result value in hex numbers and asserts the results.
library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.fft_helpers.all;
entity fft16_tb2 is
end entity;
architecture behavioral of fft16_tb2 is
-- Component Declaration for the Unit Under Test (UUT)
component fft16
generic(RSTDEF: std_logic := '0');
port(rst: in std_logic; -- reset, RSTDEF active
clk: in std_logic; -- clock, rising edge
swrst: in std_logic; -- software reset, RSTDEF active
en: in std_logic; -- enable, high active
start: in std_logic; -- start FFT, high active
set: in std_logic; -- load FFT with values, high active
get: in std_logic; -- read FFT results, high active
din: in complex; -- datain for loading FFT
done: out std_logic; -- FFT is done, active high
dout: out complex); -- data out for reading results
end component;
-- Clock period definitions
constant clk_period: time := 10 ns;
-- simple sinus with fractional part cut-off
-- Parameters: a=10000, f=1Hz, fs=16Hz
constant test_data1: complex_arr(0 to 15) := (
to_complex(0.0, 0.0),
to_complex(3826.0, 0.0),
to_complex(7071.0, 0.0),
to_complex(9238.0, 0.0),
to_complex(10000.0, 0.0),
to_complex(9238.0, 0.0),
to_complex(7071.0, 0.0),
to_complex(3826.0, 0.0),
to_complex(0.0, 0.0),
to_complex(-3826.0, 0.0),
to_complex(-7071.0, 0.0),
to_complex(-9238.0, 0.0),
to_complex(-10000.0, 0.0),
to_complex(-9238.0, 0.0),
to_complex(-7071.0, 0.0),
to_complex(-3826.0, 0.0)
);
-- result can be calculated using online FFT calculator
-- https://sooeet.com/math/online-fft-calculator.php
signal test_data: complex_arr(0 to 15);
-- Generics
constant RSTDEF: std_logic := '0';
-- Inputs
signal rst: std_logic := '0';
signal clk: std_logic := '0';
signal swrst: std_logic := '0';
signal en: std_logic := '0';
signal start: std_logic := '0';
signal set: std_logic := '0';
signal get: std_logic := '0';
signal din: complex := COMPZERO;
-- Outputs
signal done: std_logic := '0';
signal dout: complex := COMPZERO;
signal dout_results: complex_arr(0 to 15) := (others => COMPZERO);
-- convert an unsigned value(4 bit) to a HEX digit (0-F)
function to_hex_char(val: unsigned) return character is
constant HEX: string := "0123456789ABCDEF";
begin
if (val < 16) then
return HEX(to_integer(val)+1);
else
return 'X';
end if;
end function;
-- convert unsigend to hex string representation
function to_hex_str(val: unsigned) return string is
constant LEN: natural := 6;
variable mystr: string(1 to 2+LEN);
variable idx: natural;
begin
mystr := "0x";
for i in LEN-1 downto 0 loop
idx := i * 4;
mystr(2+(i+1)) := to_hex_char(val(idx+3 downto idx));
end loop;
return mystr;
end function;
begin
test_data <= test_data1;
-- Instantiate the Unit Under Test (UUT)
uut: fft16
generic map(RSTDEF => RSTDEF)
port map(rst => rst,
clk => clk,
swrst => swrst,
en => en,
start => start,
set => set,
get => get,
din => din,
done => done,
dout => dout);
-- Clock process definitions
clk_process: process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for clk_period*10;
rst <= '1';
swrst <= '1';
en <= '1';
-- load data into FFT
-- send set signal
set <= '1';
din <= test_data(0);
wait for clk_period;
set <= '0';
for i in 1 to 15 loop
din <= test_data(i);
wait for clk_period;
end loop;
-- wait one extra cycle until data is stored to memory
wait for clk_period;
-- compute FFT
start <= '1';
wait for clk_period;
start <= '0';
wait for 50*clk_period;
-- get results
get <= '1';
wait for clk_period;
get <= '0';
wait for clk_period;
-- read data from dout
for i in 0 to 15 loop
dout_results(i) <= dout;
-- print the results to stdout
report "[" & integer'image(i) & "] (" &
to_hex_str(unsigned(dout.r)) &
", " &
to_hex_str(unsigned(dout.i)) &
")";
wait for clk_period;
end loop;
wait;
end process;
end;
| mit | 67cdb30c3c10d992b0b3290fb98b5ae2 | 0.519757 | 3.683695 | false | false | false | false |
epall/Computer.Build | templates/ram.vhdl | 1 | 1,128 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY ram IS
GENERIC
(
ADDRESS_WIDTH : integer := 5;
DATA_WIDTH : integer := 8
);
PORT
(
clock : IN std_logic;
data_in : IN std_logic_vector(DATA_WIDTH - 1 DOWNTO 0);
data_out : OUT std_logic_vector(DATA_WIDTH - 1 DOWNTO 0);
address : IN std_logic_vector(ADDRESS_WIDTH - 1 DOWNTO 0);
wr_data : IN std_logic;
wr_addr : IN std_logic;
rd : IN std_logic
);
END ram;
ARCHITECTURE rtl OF ram IS
TYPE RAM IS ARRAY(0 TO 2 ** ADDRESS_WIDTH - 1) OF std_logic_vector(DATA_WIDTH - 1 DOWNTO 0);
SIGNAL ram_block : RAM;
SIGNAL addr_cache : std_logic_vector(ADDRESS_WIDTH - 1 DOWNTO 0);
BEGIN
WITH rd SELECT
data_out <= ram_block(to_integer(unsigned(addr_cache))) WHEN '1',
"ZZZZZZZZ" WHEN OTHERS;
PROCESS (clock)
BEGIN
IF clock'EVENT AND clock = '0' THEN
IF(wr_data = '1') THEN
ram_block(to_integer(unsigned(addr_cache))) <= data_in;
ELSIF(wr_addr = '1') THEN
addr_cache <= address;
END IF;
END IF;
END PROCESS;
END rtl;
| mit | 02023c31f97ef25734b74716cc07964f | 0.608156 | 3.159664 | false | false | false | false |
hoglet67/AtomGodilVideo | src/MC6847/mc6847.vhd | 1 | 30,319 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity mc6847 is
generic
(
T1_VARIANT : boolean := false;
CVBS_NOT_VGA : boolean := false);
port
(
clk : in std_logic;
clk_ena : in std_logic;
reset : in std_logic;
da0 : out std_logic;
videoaddr : out std_logic_vector (12 downto 0);
dd : in std_logic_vector(7 downto 0);
hs_n : out std_logic;
fs_n : out std_logic;
an_g : in std_logic;
an_s : in std_logic;
intn_ext : in std_logic;
gm : in std_logic_vector(2 downto 0);
css : in std_logic;
inv : in std_logic;
red : out std_logic_vector(7 downto 0);
green : out std_logic_vector(7 downto 0);
blue : out std_logic_vector(7 downto 0);
hsync : out std_logic;
vsync : out std_logic;
hblank : out std_logic;
vblank : out std_logic;
artifact_en : in std_logic;
artifact_set : in std_logic;
artifact_phase : in std_logic;
cvbs : out std_logic_vector(7 downto 0);
black_backgnd : in std_logic;
char_a : out std_logic_vector(10 downto 0);
char_d_o : in std_logic_vector(7 downto 0)
);
end mc6847;
architecture SYN of mc6847 is
constant BUILD_DEBUG : boolean := false;
constant DEBUG_AN_G : std_logic := '1';
constant DEBUG_AN_S : std_logic := '1';
constant DEBUG_INTN_EXT : std_logic := '1';
constant DEBUG_GM : std_logic_vector(2 downto 0) := "111";
constant DEBUG_CSS : std_logic := '1';
constant DEBUG_INV : std_logic := '0';
-- H_TOTAL_PER_LINE must be divisible by 16
-- so that sys_count is the same on each line when
-- the video comes out of hblank
-- so the phase relationship between char_d_o from the 6847 and character timing is maintained
-- 14.31818 MHz : 256 X 384 == 25 * 4 / 7 approx
-- constant H_FRONT_PORCH : integer := 11-1 ; --11-1+1;
-- constant H_HORIZ_SYNC : integer := H_FRONT_PORCH + 35+2;
-- constant H_BACK_PORCH : integer := H_HORIZ_SYNC + 34+1;
-- constant H_LEFT_BORDER : integer := H_BACK_PORCH + 61+1;--+3; -- adjust for hblank de-assert @sys_count=6
-- constant H_LEFT_RSTADDR : integer := H_LEFT_BORDER -16;
-- constant H_VIDEO : integer := H_LEFT_BORDER + 256;
-- -- constant H_RIGHT_BORDER : integer := H_VIDEO + 61+1;---3; -- "
-- constant H_RIGHT_BORDER : integer := H_VIDEO + 54;---3; -- tweak to get to 60hz exactly
-- constant H_TOTAL_PER_LINE : integer := H_RIGHT_BORDER;
constant H_FRONT_PORCH : integer := 8;
constant H_HORIZ_SYNC : integer := H_FRONT_PORCH + 48;
constant H_BACK_PORCH : integer := H_HORIZ_SYNC + 24;
constant H_LEFT_BORDER : integer := H_BACK_PORCH + 32; -- adjust for hblank de-assert @sys_count=6
constant H_LEFT_RSTADDR : integer := H_LEFT_BORDER - 16;
constant H_VIDEO : integer := H_LEFT_BORDER + 256;
constant H_RIGHT_BORDER : integer := H_VIDEO + 31; -- "
constant H_TOTAL_PER_LINE : integer := H_RIGHT_BORDER;
constant V2_FRONT_PORCH : integer := 2;
constant V2_VERTICAL_SYNC : integer := V2_FRONT_PORCH + 2;
constant V2_BACK_PORCH : integer := V2_VERTICAL_SYNC + 12;
constant V2_TOP_BORDER : integer := V2_BACK_PORCH + 26; -- + 25; -- +25 for PAL
constant V2_VIDEO : integer := V2_TOP_BORDER + 192;
constant V2_BOTTOM_BORDER : integer := V2_VIDEO + 27; -- + 25; -- +25 for PAL
constant V2_TOTAL_PER_FIELD : integer := V2_BOTTOM_BORDER;
-- internal version of control ports
signal an_g_s : std_logic;
signal an_s_s : std_logic;
signal intn_ext_s : std_logic;
signal gm_s : std_logic_vector(2 downto 0);
signal css_s : std_logic;
signal inv_s : std_logic;
-- VGA signals
signal vga_hsync : std_logic;
signal vga_vsync : std_logic;
signal vga_hblank : std_logic;
signal vga_vblank : std_logic;
signal vga_linebuf_addr : std_logic_vector(8 downto 0);
signal vga_char_d_o : std_logic_vector(7 downto 0);
signal vga_hborder : std_logic;
signal vga_vborder : std_logic;
-- CVBS signals
signal cvbs_clk_ena : std_logic; -- PAL/NTSC*2
signal cvbs_hsync : std_logic;
signal cvbs_vsync : std_logic;
signal cvbs_hblank : std_logic;
signal cvbs_vblank : std_logic;
signal cvbs_hborder : std_logic;
signal cvbs_vborder : std_logic;
signal cvbs_linebuf_we : std_logic;
signal cvbs_linebuf_addr : std_logic_vector(8 downto 0);
signal active_h_start : std_logic := '0';
signal an_s_r : std_logic;
signal inv_r : std_logic;
signal intn_ext_r : std_logic;
signal dd_r : std_logic_vector(7 downto 0);
signal pixel_char_d_o : std_logic_vector(7 downto 0);
signal cvbs_char_d_o : std_logic_vector(7 downto 0); -- CVBS char_d_o out
alias hs_int : std_logic is cvbs_hblank;
signal fs_int : std_logic;
signal da0_int : std_logic_vector(4 downto 0);
-- character rom signals
signal cvbs_linebuf_we_r : std_logic;
signal cvbs_linebuf_addr_r : std_logic_vector(8 downto 0);
signal cvbs_linebuf_we_rr : std_logic;
signal cvbs_linebuf_addr_rr : std_logic_vector(8 downto 0);
signal lookup : std_logic_vector(5 downto 0);
signal tripletaddr : std_logic_vector(7 downto 0);
signal tripletcnt : std_logic_vector(3 downto 0);
-----------------------------------------------------------------------
type vram_type is array (511 downto 0) of std_logic_vector (7 downto 0);
signal VRAM : vram_type := (511 downto 0 => X"FF");
attribute RAM_STYLE : string;
attribute RAM_STYLE of VRAM : signal is "BLOCK";
------------------------------------------------------------------------
-- used by both CVBS and VGA
shared variable v_count : std_logic_vector(8 downto 0);
shared variable row_v : std_logic_vector(3 downto 0);
procedure map_palette (vga_char_d_o : in std_logic_vector(7 downto 0);
r : out std_logic_vector(7 downto 0);
g : out std_logic_vector(7 downto 0);
b : out std_logic_vector(7 downto 0)) is
type pal_entry_t is array (0 to 2) of std_logic_vector(1 downto 0);
type pal_a is array (0 to 7) of pal_entry_t;
constant pal : pal_a :=
(
0 => (0 => "00", 1 => "11", 2=>"00"), -- green
1 => (0 => "11", 1 => "11", 2=>"00"), -- yellow
2 => (0 => "00", 1 => "00", 2=>"11"), -- blue
3 => (0 => "11", 1 => "00", 2=>"00"), -- red
4 => (0 => "11", 1 => "11", 2=>"11"), -- white
5 => (0 => "00", 1 => "11", 2=>"11"), -- cyan
6 => (0 => "11", 1 => "00", 2=>"11"), -- magenta
7 => (0 => "11", 1 => "10", 2=>"00") -- orange
--others => (others => (others => '0'))
);
alias css_v : std_logic is vga_char_d_o(6);
alias an_g_v : std_logic is vga_char_d_o(5);
alias an_s_v : std_logic is vga_char_d_o(4);
alias luma : std_logic is vga_char_d_o(3);
alias chroma : std_logic_vector(2 downto 0) is vga_char_d_o(2 downto 0);
begin
if luma = '1' then
r := pal(to_integer(unsigned(chroma)))(0) & "000000";
g := pal(to_integer(unsigned(chroma)))(1) & "000000";
b := pal(to_integer(unsigned(chroma)))(2) & "000000";
else
-- not quite black in alpha mode
if black_backgnd = '0' and an_g_v = '0' and an_s_v = '0' then
-- dark green/orange
r := '0' & css_v & "000000";
g := "01000000";
else
r := (others => '0');
g := (others => '0');
end if;
b := (others => '0');
end if;
end procedure;
begin
-- assign control inputs for debug/release build
an_g_s <= DEBUG_AN_G when BUILD_DEBUG else an_g;
an_s_s <= DEBUG_AN_S when BUILD_DEBUG else an_s;
intn_ext_s <= DEBUG_INTN_EXT when BUILD_DEBUG else intn_ext;
gm_s <= DEBUG_GM when BUILD_DEBUG else gm;
css_s <= DEBUG_CSS when BUILD_DEBUG else css;
inv_s <= DEBUG_INV when BUILD_DEBUG else inv;
-- generate the clocks
PROC_CLOCKS : process (clk, reset)
variable toggle : std_logic := '0';
begin
if reset = '1' then
toggle := '0';
cvbs_clk_ena <= '0';
elsif rising_edge(clk) then
cvbs_clk_ena <= '0'; -- default
if clk_ena = '1' then
cvbs_clk_ena <= toggle;
toggle := not toggle;
end if;
end if;
end process PROC_CLOCKS;
-- generate horizontal timing for VGA
-- generate line buffer address for reading VGA char_d_o
PROC_VGA : process (clk, reset)
variable h_count : integer range 0 to H_TOTAL_PER_LINE;
variable active_h_count : std_logic_vector(7 downto 0);
variable vga_vblank_r : std_logic;
begin
if reset = '1' then
h_count := 0;
vga_hsync <= '1';
vga_vsync <= '1';
vga_hblank <= '0';
elsif rising_edge (clk) and clk_ena = '1' then
-- start hsync when cvbs comes out of vblank
if vga_vblank_r = '1' and vga_vblank = '0' then
h_count := 0;
else
if h_count = H_TOTAL_PER_LINE then
h_count := 0;
vga_hborder <= '0';
else
h_count := h_count + 1;
end if;
if h_count = H_FRONT_PORCH then
vga_hsync <= '0';
elsif h_count = H_HORIZ_SYNC then
vga_hsync <= '1';
elsif h_count = H_BACK_PORCH then
vga_hborder <= '1';
elsif h_count = H_LEFT_BORDER+1 then
vga_hblank <= '0';
elsif h_count = H_VIDEO+1 then
vga_hblank <= '1';
elsif h_count = H_RIGHT_BORDER then
vga_hborder <= '0';
end if;
if h_count = H_LEFT_BORDER then
active_h_count := (others => '1');
else
active_h_count := std_logic_vector(unsigned(active_h_count) + 1);
end if;
end if;
-- vertical syncs, blanks are the same
vga_vsync <= cvbs_vsync;
-- generate linebuffer address
-- - alternate every 2nd line
vga_linebuf_addr <= (not v_count(0)) & active_h_count;
vga_vblank_r := vga_vblank;
end if;
end process;
-- generate horizontal timing for CVBS
-- generate line buffer address for writing CVBS char_d_o
PROC_CVBS : process (clk, reset)
variable h_count : integer range 0 to H_TOTAL_PER_LINE;
variable active_h_count : std_logic_vector(7 downto 0);
variable cvbs_hblank_r : std_logic := '0';
--variable row_v : std_logic_vector(3 downto 0);
-- for debug only
variable videoaddr_base : std_logic_vector(12 downto 0);
begin
if reset = '1' then
h_count := H_TOTAL_PER_LINE;
v_count := std_logic_vector(to_unsigned(V2_TOTAL_PER_FIELD, v_count'length));
active_h_count := (others => '0');
active_h_start <= '0';
cvbs_hsync <= '1';
cvbs_vsync <= '1';
cvbs_hblank <= '0';
cvbs_vblank <= '1';
vga_vblank <= '1';
da0_int <= (others => '0');
cvbs_hblank_r := '0';
row_v := (others => '0');
elsif rising_edge (clk) and cvbs_clk_ena = '1' then
active_h_start <= '0';
if h_count = H_TOTAL_PER_LINE then
h_count := 0;
if v_count = V2_TOTAL_PER_FIELD then
v_count := (others => '0');
else
v_count := v_count + 1;
end if;
-- VGA vblank is 1 line behind CVBS
-- - because we need to fill the line buffer
vga_vblank <= cvbs_vblank;
if v_count = V2_FRONT_PORCH then
cvbs_vsync <= '0';
elsif v_count = V2_VERTICAL_SYNC then
cvbs_vsync <= '1';
fs_int <= '0';
elsif v_count = V2_BACK_PORCH then
cvbs_vborder <= '1';
elsif v_count = V2_TOP_BORDER then
cvbs_vblank <= '0';
row_v := (others => '0');
videoaddr_base := (others => '0');
tripletaddr <= (others => '0');
tripletcnt <= (others => '0');
elsif v_count = V2_VIDEO then
cvbs_vblank <= '1';
fs_int <= '1';
elsif v_count = V2_BOTTOM_BORDER then
cvbs_vborder <= '0';
else
if an_g_s = '0' then
if (row_v = 11) then
videoaddr_base := videoaddr_base + 32;
end if;
else
case gm is
when "000" | "001" =>
if (tripletcnt = 2) then
videoaddr_base := videoaddr_base + 16;
end if;
when "010" =>
if (tripletcnt = 2) then
videoaddr_base := videoaddr_base + 32;
end if;
when "011" =>
if (row_v(0) = '1') then
videoaddr_base := videoaddr_base + 16;
end if;
when "100" =>
if (row_v(0) = '1') then
videoaddr_base := videoaddr_base + 32;
end if;
when "101" =>
videoaddr_base := videoaddr_base + 16;
when "110" | "111" =>
videoaddr_base := videoaddr_base + 32;
when others =>
null;
end case;
end if;
if tripletcnt = 2 then -- mode 1,1a,2a
tripletcnt <= (others => '0');
tripletaddr <= tripletaddr + 1;
else
tripletcnt <= tripletcnt + 1;
end if;
if row_v = 11 then
row_v := (others => '0');
else
row_v := row_v + 1;
end if;
end if;
else
h_count := h_count + 1;
if h_count = H_FRONT_PORCH then
cvbs_hsync <= '0';
elsif h_count = H_HORIZ_SYNC then
cvbs_hsync <= '1';
elsif h_count = H_BACK_PORCH then
elsif h_count = H_LEFT_RSTADDR then
active_h_count := (others => '0');
elsif h_count = H_LEFT_BORDER then
cvbs_hblank <= '0';
active_h_start <= '1';
elsif h_count = H_VIDEO then
cvbs_hblank <= '1';
active_h_count := active_h_count + 1;
elsif h_count = H_RIGHT_BORDER then
null;
else
active_h_count := active_h_count + 1;
end if;
end if;
-- generate character rom address
char_a <= dd(6 downto 0) & row_v(3 downto 0);
-- DA0 high during FS
if cvbs_vblank = '1' then
da0_int <= (others => '1');
elsif cvbs_hblank = '1' then
da0_int <= (others => '0');
elsif cvbs_hblank_r = '1' and cvbs_hblank = '0' then
da0_int <= "01000";
else
da0_int <= da0_int + 1;
end if;
cvbs_linebuf_addr <= v_count(0) & active_h_count;
-- pipeline writes to linebuf because char_d_o is delayed 1 clock as well!
cvbs_linebuf_we_r <= cvbs_linebuf_we;
cvbs_linebuf_addr_r <= cvbs_linebuf_addr;
cvbs_linebuf_we_rr <= cvbs_linebuf_we_r;
cvbs_linebuf_addr_rr <= cvbs_linebuf_addr_r;
cvbs_hblank_r := cvbs_hblank;
if an_g_s = '0' then
lookup(4 downto 0) <= active_h_count(7 downto 3) + 1;
videoaddr <= videoaddr_base(12 downto 5) & lookup(4 downto 0);
else
case gm is --lookupaddr
when "000" | "001" | "011" | "101" =>
lookup(3 downto 0) <= active_h_count(7 downto 4) + 1;
videoaddr <= videoaddr_base(12 downto 4) & lookup(3 downto 0);
when "010" | "100" | "110" | "111" =>
lookup(4 downto 0) <= active_h_count(7 downto 3) + 1;
videoaddr <= videoaddr_base(12 downto 5) & lookup(4 downto 0);
when others =>
null;
end case;
end if;
end if; -- cvbs_clk_ena
end process;
-- handle latching & shifting of character, graphics char_d_o
process (clk, reset)
variable count : std_logic_vector(3 downto 0) := (others => '0');
begin
if reset = '1' then
count := (others => '0');
elsif rising_edge(clk) and cvbs_clk_ena = '1' then
if active_h_start = '1' then
count := (others => '0');
end if;
if an_g_s = '0' then
-- alpha-semi modes
if count(2 downto 0) = 0 then
-- handle alpha-semi latching
an_s_r <= an_s_s;
inv_r <= inv_s;
intn_ext_r <= intn_ext_s;
if an_s_s = '0' then
dd_r <= char_d_o; -- alpha mode
else
-- store luma,chroma(2..0),luma,chroma(2..0)
if intn_ext_s = '0' then -- semi-4
if row_v < 6 then
dd_r <= dd(3) & dd(6) & dd(5) & dd(4) &
dd(2) & dd(6) & dd(5) & dd(4);
else
dd_r <= dd(1) & dd(6) & dd(5) & dd(4) &
dd(0) & dd(6) & dd(5) & dd(4);
end if;
else -- semi-6
if row_v < 4 then
dd_r <= dd(5) & css_s & dd(7) & dd(6) &
dd(4) & css_s & dd(7) & dd(6);
elsif row_v < 8 then
dd_r <= dd(3) & css_s & dd(7) & dd(6) &
dd(2) & css_s & dd(7) & dd(6);
else
dd_r <= dd(1) & css_s & dd(7) & dd(6) &
dd(0) & css_s & dd(7) & dd(6);
end if;
end if;
end if;
else
-- handle alpha-semi shifting
if an_s_r = '0' then
dd_r <= dd_r(dd_r'left-1 downto 0) & '0'; -- alpha mode
else
if count(1 downto 0) = 0 then
dd_r <= dd_r(dd_r'left-4 downto 0) & "0000"; -- semi mode
end if;
end if;
end if;
else
-- graphics modes
--if IN_SIMULATION then
an_s_r <= '0';
--end if;
case gm_s is
when "000" | "001" | "011" | "101" => -- CG1/RG1/RG2/RG3
if count(3 downto 0) = 0 then
-- handle graphics latching
dd_r <= dd;
else
-- handle graphics shifting
if gm_s = "000" then
if count(1 downto 0) = 0 then
dd_r <= dd_r(dd_r'left-2 downto 0) & "00"; -- CG1
end if;
else
if count(0) = '0' then
dd_r <= dd_r(dd_r'left-1 downto 0) & '0'; -- RG1/RG2/RG3
end if;
end if;
end if;
when others => -- CG2/CG3/CG6/RG6
if count(2 downto 0) = 0 then
-- handle graphics latching
dd_r <= dd;
else
-- handle graphics shifting
if gm_s = "111" then
dd_r <= dd_r(dd_r'left-1 downto 0) & '0'; -- RG6
else
if count(0) = '0' then
dd_r <= dd_r(dd_r'left-2 downto 0) & "00"; -- CG2/CG3/CG6
end if;
end if;
end if;
end case;
end if;
count := count + 1;
end if;
end process;
-- generate pixel char_d_o
process (clk, reset)
variable luma : std_logic;
variable chroma : std_logic_vector(2 downto 0);
begin
if reset = '1' then
elsif rising_edge(clk) and cvbs_clk_ena = '1' then
-- alpha/graphics mode
if an_g_s = '0' then
-- alphanumeric & semi-graphics mode
luma := dd_r(dd_r'left);
if an_s_r = '0' then
-- alphanumeric
if intn_ext_r = '0' then
-- internal rom
chroma := (others => css_s);
if inv_r = '1' then
luma := not luma;
end if; -- normal/inverse
else
-- external ROM?!?
end if; -- internal/external
else
chroma := dd_r(dd_r'left-1 downto dd_r'left-3);
end if; -- alphanumeric/semi-graphics
else
-- graphics mode
case gm_s is
when "000" => -- CG1 64x64x4
luma := '1';
chroma := css_s & dd_r(dd_r'left downto dd_r'left-1);
when "001" | "011" | "101" => -- RG1/2/3 128x64/96/192x2
luma := dd_r(dd_r'left);
chroma := css_s & "00"; -- green/buff
when "010" | "100" | "110" => -- CG2/3/6 128x64/96/192x4
luma := '1';
chroma := css_s & dd_r(dd_r'left downto dd_r'left-1);
when others => -- RG6 256x192x2
luma := dd_r(dd_r'left);
chroma := css_s & "00"; -- green/buff
end case;
end if; -- alpha/graphics mode
-- pack source char_d_o into line buffer
-- - palette lookup on output
pixel_char_d_o <= '0' & css_s & an_g_s & an_s_r & luma & chroma;
end if;
end process;
-- only write to the linebuffer during active display
cvbs_linebuf_we <= not (cvbs_vblank or cvbs_hblank);
cvbs <= '0' & cvbs_vsync & "000000" when cvbs_vblank = '1' else
'0' & cvbs_hsync & "000000" when cvbs_hblank = '1' else
cvbs_char_d_o;
-- assign outputs
hs_n <= not hs_int;
fs_n <= not fs_int;
da0 <= da0_int(4) when (gm_s = "001" or gm_s = "011" or gm_s = "101") else
da0_int(3);
-- map the palette to the pixel char_d_o
-- - we do that at the output so we can use a
-- higher colour-resolution palette
-- without using memory in the line buffer
PROC_OUTPUT : process (clk)
variable r : std_logic_vector(red'range);
variable g : std_logic_vector(green'range);
variable b : std_logic_vector(blue'range);
-- for artifacting testing only
variable p_in : std_logic_vector(vga_char_d_o'range);
variable p_out : std_logic_vector(vga_char_d_o'range);
variable count : std_logic := '0';
begin
if reset = '1' then
count := '0';
elsif rising_edge(clk) then
if CVBS_NOT_VGA then
if cvbs_clk_ena = '1' then
if cvbs_hblank = '0' and cvbs_vblank = '0' then
map_palette (vga_char_d_o, r, g, b);
else
r := (others => '0');
g := (others => '0');
b := (others => '0');
end if;
end if;
else
if clk_ena = '1' then
if vga_hblank = '1' then
count := '0';
p_in := (others => '0');
end if;
if vga_hblank = '0' and vga_vblank = '0' then
-- artifacting test only --
if artifact_en = '1' and an_g_s = '1' and gm_s = "111" then
if count /= '0' then
p_out(p_out'left downto 4) := vga_char_d_o(p_out'left downto 4);
if p_in(3) = '0' and vga_char_d_o(3) = '0' then
p_out(3 downto 0) := "0000";
elsif p_in(3) = '1' and vga_char_d_o(3) = '1' then
p_out(3 downto 0) := "1100";
elsif p_in(3) = '0' and vga_char_d_o(3) = '1' then
p_out(3 downto 0) := "1011"; -- red
--p_out(3 downto 0) := "1101"; -- cyan
else
p_out(3 downto 0) := "1010"; -- blue
--p_out(3 downto 0) := "1111"; -- orange
end if;
end if;
map_palette (p_out, r, g, b);
p_in := vga_char_d_o;
else
map_palette (vga_char_d_o, r, g, b);
end if;
count := not count;
elsif an_g_s = '1' and vga_hborder = '1' and cvbs_vborder = '1' then
-- graphics mode, either green or buff (white)
map_palette ("00001" & css_s & "00", r, g, b);
else
r := (others => '0');
g := (others => '0');
b := (others => '0');
end if;
end if;
end if; -- CVBS_NOT_VGA
red <= r; green <= g; blue <= b;
end if; -- rising_edge(clk)
if CVBS_NOT_VGA then
hsync <= cvbs_hsync;
vsync <= cvbs_vsync;
hblank <= cvbs_hblank;
vblank <= cvbs_vblank;
else
hsync <= vga_hsync;
vsync <= vga_vsync;
hblank <= not vga_hborder;
vblank <= not cvbs_vborder;
end if;
end process PROC_OUTPUT;
-- line buffer for scan doubler gives us vga monitor compatible output
process (clk)
begin
if rising_edge(clk) then
if cvbs_clk_ena = '1' then
if (cvbs_linebuf_we_rr = '1') then
VRAM(conv_integer(cvbs_linebuf_addr_rr(8 downto 0))) <= pixel_char_d_o;
end if;
end if;
if clk_ena = '1' then
vga_char_d_o <= VRAM(conv_integer(vga_linebuf_addr(8 downto 0)));
end if;
end if;
end process;
---- rom for char generator
-- charrom_inst : entity work.mc6847t1_ntsc_plus_keith
-- port map(
-- CLK => clk,
-- ADDR => char_a,
-- DATA => char_d_o
-- );
end SYN;
| apache-2.0 | 261c61f4acbc34f2ded9aa5c1279c8fc | 0.41281 | 3.926823 | false | false | false | false |
riverever/verilogTestSuit | ivltests/vhdl_test4.vhd | 2 | 525 | --
-- Author: Pawel Szostek ([email protected])
-- Date: 27.07.2011
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
entity dummy is
port (o1: out std_logic_vector(7 downto 0);
o2: out std_logic_vector(7 downto 0);
o3: out std_logic_vector(7 downto 0)
);
end;
architecture behaviour of dummy is
begin
o1 <= (others => '0');
o2 <= (3 => '1', others => '0');
o3 <= (7=>'1', 6|5|4|3|2|1|0 => '0', others => '1'); --tricky
end;
| gpl-2.0 | 47e128eba0d8de1052f722b038f4d498 | 0.592381 | 2.706186 | false | false | false | false |
Rookfighter/fft-spartan6 | fft/i2c_slave.vhd | 1 | 10,975 | -- i2c_slave.vhd
--
-- Created on: 08 Jun 2017
-- Author: Fabian Meyer
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity i2c_slave is
generic(RSTDEF: std_logic := '0';
ADDRDEF: std_logic_vector(6 downto 0) := "0100000");
port(rst: in std_logic; -- reset, RSTDEF active
clk: in std_logic; -- clock, rising edge
swrst: in std_logic; -- software reset, RSTDEF active
en: in std_logic; -- enable, high active
tx_data: in std_logic_vector(7 downto 0); -- tx, data to send
tx_sent: out std_logic := '0'; -- tx was sent, high active
rx_data: out std_logic_vector(7 downto 0) := (others => '0'); -- rx, data received
rx_recv: out std_logic := '0'; -- rx received, high active
busy: out std_logic := '0'; -- busy, high active
sda: inout std_logic := 'Z'; -- serial data of I2C
scl: inout std_logic := 'Z'); -- serial clock of I2C
end entity;
architecture behavioral of i2c_slave is
component delay_bit
generic(RSTDEF: std_logic := '0';
DELAYLEN: natural := 8);
port(rst: in std_logic; -- reset, RSTDEF active
clk: in std_logic; -- clock, rising edge
swrst: in std_logic; -- software reset, RSTDEF active
en: in std_logic; -- enable, high active
din: in std_logic; -- data in
dout: out std_logic); -- data out
end component;
-- states for FSM
type TState is (SIDLE, SADDR, SSEND_ACK1, SSEND_ACK2, SRECV_ACK, SREAD, SWRITE);
signal state: TState := SIDLE;
signal prev_state: TState := SIDLE;
-- constant to define cycles per time unit
constant CLKPERMS: natural := 24000;
-- counter for measuring time to timeout after 1ms
constant TIMEOUTLEN: natural := 15;
signal cnt_timeout: unsigned(TIMEOUTLEN-1 downto 0) := (others => '0');
-- data vector for handling traffic internally
constant DATALEN: natural := 8;
signal data: std_logic_vector(DATALEN-1 downto 0) := (others => '0');
-- determines if master reqested read (high) or write (low)
signal rwbit: std_logic := '0';
-- sda signal delayed by 1us
signal sda_del: std_logic := '0';
-- i2c vectors to store previous and current signal
signal scl_vec: std_logic_vector(1 downto 0) := (others => '0');
signal sda_vec: std_logic_vector(1 downto 0) := (others => '0');
-- counter to count bits received / sent
signal cnt_bit: unsigned(2 downto 0) := (others => '0');
signal tx_data_t: std_logic_vector(7 downto 0) := (others => '0');
begin
-- always let master handle scl
scl <= 'Z';
-- lsb is current scl
scl_vec(0) <= scl;
-- lsb is delayed sda
sda_vec(0) <= sda_del;
-- always busy if not in idle mode
busy <= '0' when state = SIDLE else '1';
-- always transform 1 to Z
-- never put a 1 on SDA
tx_data_transform: for i in 7 downto 0 generate
tx_data_t(i) <= 'Z' when tx_data(i) = '1' else '0';
end generate;
-- delay sda signal by 24 cylces (= 1us)
delay1: delay_bit
generic map(RSTDEF => RSTDEF,
DELAYLEN => 24)
port map(rst => rst,
clk => clk,
swrst => swrst,
en => en,
din => sda,
dout => sda_del);
process(clk, rst)
procedure reset is
begin
-- reset out ports
tx_sent <= '0';
rx_data <= (others => '0');
rx_recv <= '0';
-- release sda
sda <= 'Z';
-- go back to idle state
state <= SIDLE;
prev_state <= SIDLE;
-- reset timeout counter
cnt_timeout <= (others => '0');
data <= (others => '0');
rwbit <= '0';
-- reset scl / sda history
scl_vec(1) <= '0';
sda_vec(1) <= '0';
-- reset bit counter
cnt_bit <= (others => '0');
end procedure;
begin
if rst = RSTDEF then
reset;
elsif rising_edge(clk) then
if swrst = RSTDEF then
reset;
elsif en = '1' then
-- keep track of previous sda and scl (msb)
sda_vec(1) <= sda_vec(0);
scl_vec(1) <= scl_vec(0);
-- leave sent and recv signals high for only one cylce
tx_sent <= '0';
rx_recv <= '0';
-- keep track of previous state for timeout
prev_state <= state;
-- check for timeout
cnt_timeout <= cnt_timeout + 1;
if prev_state /= state or state = SIDLE then
-- reset timeout if states have changed or we are in idle mode
cnt_timeout <= (others => '0');
elsif to_integer(cnt_timeout) = CLKPERMS then
-- timeout is reached, reset and go into idle state
reset;
end if;
-- compute state machine for i2c slave
case state is
when SIDLE =>
-- do nothing, wait for start condition
when SADDR =>
if scl_vec = "01" then
-- set data bit depending on cnt_bit
data(7-to_integer(cnt_bit)) <= sda_vec(0);
cnt_bit <= cnt_bit + 1;
-- if cnt_bit is full then we have just received last bit
if cnt_bit = "111" then
rwbit <= sda_vec(0);
if data(DATALEN-1 downto 1) = ADDRDEF then
-- address matches ours, acknowledge
state <= SSEND_ACK1;
else
-- address doesn't match ours, ignore
state <= SIDLE;
end if;
end if;
end if;
when SSEND_ACK1 =>
if scl_vec = "10" then
state <= SSEND_ACK2;
sda <= '0';
end if;
when SSEND_ACK2 =>
if scl_vec = "10" then
-- check if master requested read or write
if rwbit = '1' then
-- master wants to read
-- write first bit on bus
sda <= tx_data_t(7);
data <= tx_data_t;
-- start from one because we already wrote first bit
cnt_bit <= "001";
state <= SREAD;
else
-- master wants to write
-- release sda
sda <= 'Z';
cnt_bit <= (others => '0');
state <= SWRITE;
end if;
end if;
when SRECV_ACK =>
if scl_vec = "01" then
if sda_vec(0) /= '0' then
-- received nack: master will send stop cond, but we
-- can simply jump right to idle state
state <= SIDLE;
end if;
elsif scl_vec = "10" then
-- continue read
sda <= tx_data_t(7); -- write first bit on bus
data <= tx_data_t;
-- start from 1 because we alreay transmit first bit
cnt_bit <= "001";
state <= SREAD;
end if;
when SREAD =>
if scl_vec = "10" then
sda <= data(7-to_integer(cnt_bit));
cnt_bit <= cnt_bit + 1;
-- if cnt_bit overflowed we finished transmitting last bit
-- note: data is not allowed to contain any 1, only Z or 0
if cnt_bit = "000" then
-- release sda, because we need to listen for ack
-- from master
sda <= 'Z';
state <= SRECV_ACK;
-- notify that we have sent the byte
tx_sent <= '1';
end if;
end if;
when SWRITE =>
if scl_vec = "01" then
data(7-to_integer(cnt_bit)) <= sda_vec(0);
cnt_bit <= cnt_bit + 1;
-- if cnt_bit is full we have just received the last bit
if cnt_bit = "111" then
state <= SSEND_ACK1;
-- apply received byte to out port
rx_data <= data(DATALEN-1 downto 1) & sda_vec(0);
-- notify that we have received a new byte
rx_recv <= '1';
end if;
end if;
end case;
if state = SWRITE or state = SREAD then
-- check for stop condition
if scl_vec = "11" and sda_vec = "01" then
-- i2c stop condition
state <= SIDLE;
sda <= 'Z';
end if;
end if;
if state = SIDLE or state = SWRITE or state = SREAD then
-- check for start condition
if scl_vec = "11" and sda_vec = "10" then
-- i2c start condition / repeated start condition
state <= SADDR;
cnt_bit <= (others => '0');
end if;
end if;
end if;
end if;
end process;
end architecture;
| mit | a749c5e6d596484ea048e25db851ab8e | 0.404282 | 4.89082 | false | false | false | false |
Kalycito-open-automation/openPOWERLINK_V2_old_25-06-2014 | hardware/ipcore/altera/lib/src/dpRam-rtl-a.vhd | 2 | 3,645 | --! @file dpRam-bhv-a.vhd
--
--! @brief Dual Port Ram Register Transfer Level Architecture
--
--! @details This is the DPRAM intended for synthesis on Altera platforms only.
--! Timing as follows [clk-cycles]: write=0 / read=1
--
-------------------------------------------------------------------------------
-- Architecture : rtl
-------------------------------------------------------------------------------
--
-- (c) B&R, 2013
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! use altera_mf library
library altera_mf;
use altera_mf.altera_mf_components.all;
architecture rtl of dpRam is
begin
altsyncram_component : altsyncram
generic map (
operation_mode => "BIDIR_DUAL_PORT",
intended_device_family => "Cyclone IV",
init_file => gInitFile,
numwords_a => gNumberOfWords,
numwords_b => gNumberOfWords,
widthad_a => logDualis(gNumberOfWords),
widthad_b => logDualis(gNumberOfWords),
width_a => gWordWidth,
width_b => gWordWidth,
width_byteena_a => gWordWidth/8,
width_byteena_b => gWordWidth/8
)
port map (
clock0 => iClk_A,
clocken0 => iEnable_A,
wren_a => iWriteEnable_A,
address_a => iAddress_A,
byteena_a => iByteenable_A,
data_a => iWritedata_A,
q_a => oReaddata_A,
clock1 => iClk_B,
clocken1 => iEnable_B,
wren_b => iWriteEnable_B,
address_b => iAddress_B,
byteena_b => iByteenable_B,
data_b => iWritedata_B,
q_b => oReaddata_B
);
end architecture rtl;
| gpl-2.0 | 40f891c3e0d32564583caa107846e8c3 | 0.569547 | 4.758486 | false | false | false | false |
kristofferkoch/ethersound | tb_deltasigmadac.vhd | 1 | 2,854 | -----------------------------------------------------------------------------
-- Testbench for deltasigmadac
--
-- Authors:
-- -- Kristoffer E. Koch
-----------------------------------------------------------------------------
-- Copyright 2008 Authors
--
-- This file is part of hwpulse.
--
-- hwpulse is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- hwpulse is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with hwpulse. If not, see <http://www.gnu.org/licenses/>.
-----------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY tb_deltasigmadac IS
END tb_deltasigmadac;
ARCHITECTURE behavior OF tb_deltasigmadac IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT deltasigmadac
PORT(
sysclk : IN std_logic;
reset : IN std_logic;
audio : IN std_logic_vector(23 downto 0);
audio_dv : IN std_logic;
audio_left : OUT std_logic;
audio_right : OUT std_logic
);
END COMPONENT;
--Inputs
signal sysclk : std_logic := '0';
signal reset : std_logic := '0';
signal audio : std_logic_vector(23 downto 0) := (others => '0');
signal audio_dv : std_logic := '0';
--Outputs
signal audio_left : std_logic;
signal audio_right : std_logic;
-- Clock period definitions
constant sysclk_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: deltasigmadac PORT MAP (
sysclk => sysclk,
reset => reset,
audio => audio,
audio_dv => audio_dv,
audio_left => audio_left,
audio_right => audio_right
);
-- Clock process definitions
sysclk_process :process
begin
sysclk <= '0';
wait for sysclk_period/2;
sysclk <= '1';
wait for sysclk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
reset <= '1';
wait for sysclk_period*10;
reset <= '0';
wait for sysclk_period;
audio_dv <= '1';
audio <= x"123456";
wait for sysclk_period;
audio_dv <= '0';
wait for sysclk_period*4;
audio_dv <= '1';
audio <= x"FFFFFF";
wait for sysclk_period;
audio_dv <= '0';
wait for sysclk_period*4;
wait;
end process;
END;
| gpl-3.0 | 8401442db765874ca8babbb5eaa973a6 | 0.570427 | 3.877717 | false | false | false | false |
Kalycito-open-automation/openPOWERLINK_V2_old_25-06-2014 | hardware/ipcore/common/hostinterface/src/hostInterfacePkg.vhd | 2 | 4,098 | -------------------------------------------------------------------------------
--! @file hostInterfacePkg.vhd
--
--! @brief Host interface package
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2012
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package hostInterfacePkg is
-- constants
--! dword size
constant cDword : natural := 32;
--! word size
constant cWord : natural := 16;
--! byte size
constant cByte : natural := 8;
--! nible size
constant cNibble : natural := 4;
--! size of 32 bit std_logic_vector array
constant cArrayStd32ElementSize : natural := 32;
--! external synchronization config
constant cExtSyncConfigWidth : natural := 3;
constant cExtSyncEdgeConfigWidth : natural := 2;
constant cExtSyncEdgeRis : std_logic_vector
(cExtSyncEdgeConfigWidth-1 downto 0) := "01";
constant cExtSyncEdgeFal : std_logic_vector
(cExtSyncEdgeConfigWidth-1 downto 0) := "10";
constant cExtSyncEdgeAny : std_logic_vector
(cExtSyncEdgeConfigWidth-1 downto 0) := "11";
-- type
--! 32 bit std_logic_vector array type
type tArrayStd32 is
array (natural range <>) of std_logic_vector
(cArrayStd32ElementSize-1 downto 0);
-- function
--! convert arrayIn into std_logic_vector stream
function CONV_STDLOGICVECTOR (arrayIn : tArrayStd32; arrayLength : natural)
return std_logic_vector;
end hostInterfacePkg;
package body hostInterfacePkg is
-- function
function CONV_STDLOGICVECTOR (arrayIn : tArrayStd32; arrayLength : natural)
return std_logic_vector is
variable vTmpStream : std_logic_vector
(arrayLength*cArrayStd32ElementSize-1 downto 0);
variable vTmpElement : std_logic_vector
(cArrayStd32ElementSize-1 downto 0);
begin
for i in arrayLength downto 1 loop
--get current element
vTmpElement := arrayIn(arrayLength-i);
--write element into stream
vTmpStream
(i*cArrayStd32ElementSize-1 downto (i-1)*cArrayStd32ElementSize) :=
vTmpElement;
end loop;
return vTmpStream;
end function;
end package body;
| gpl-2.0 | bb65ff14e6ae0f8432421d6d5f53029d | 0.631772 | 4.776224 | false | true | false | false |
julioamerico/OpenCRC | src/SoC/component/Actel/DirectCore/CoreAHBLite/5.0.100/mti/user_vlog/COREAHBLITE_LIB/@b@f@m_@m@a@i@n/_primary.vhd | 2 | 16,150 | library verilog;
use verilog.vl_types.all;
entity BFM_MAIN is
generic(
OPMODE : integer := 0;
VECTFILE : string := "test.vec";
MAX_INSTRUCTIONS: integer := 16384;
MAX_STACK : integer := 1024;
MAX_MEMTEST : integer := 65536;
TPD : integer := 1;
DEBUGLEVEL : integer := -1;
CON_SPULSE : integer := 0;
ARGVALUE0 : integer := 0;
ARGVALUE1 : integer := 0;
ARGVALUE2 : integer := 0;
ARGVALUE3 : integer := 0;
ARGVALUE4 : integer := 0;
ARGVALUE5 : integer := 0;
ARGVALUE6 : integer := 0;
ARGVALUE7 : integer := 0;
ARGVALUE8 : integer := 0;
ARGVALUE9 : integer := 0;
ARGVALUE10 : integer := 0;
ARGVALUE11 : integer := 0;
ARGVALUE12 : integer := 0;
ARGVALUE13 : integer := 0;
ARGVALUE14 : integer := 0;
ARGVALUE15 : integer := 0;
ARGVALUE16 : integer := 0;
ARGVALUE17 : integer := 0;
ARGVALUE18 : integer := 0;
ARGVALUE19 : integer := 0;
ARGVALUE20 : integer := 0;
ARGVALUE21 : integer := 0;
ARGVALUE22 : integer := 0;
ARGVALUE23 : integer := 0;
ARGVALUE24 : integer := 0;
ARGVALUE25 : integer := 0;
ARGVALUE26 : integer := 0;
ARGVALUE27 : integer := 0;
ARGVALUE28 : integer := 0;
ARGVALUE29 : integer := 0;
ARGVALUE30 : integer := 0;
ARGVALUE31 : integer := 0;
ARGVALUE32 : integer := 0;
ARGVALUE33 : integer := 0;
ARGVALUE34 : integer := 0;
ARGVALUE35 : integer := 0;
ARGVALUE36 : integer := 0;
ARGVALUE37 : integer := 0;
ARGVALUE38 : integer := 0;
ARGVALUE39 : integer := 0;
ARGVALUE40 : integer := 0;
ARGVALUE41 : integer := 0;
ARGVALUE42 : integer := 0;
ARGVALUE43 : integer := 0;
ARGVALUE44 : integer := 0;
ARGVALUE45 : integer := 0;
ARGVALUE46 : integer := 0;
ARGVALUE47 : integer := 0;
ARGVALUE48 : integer := 0;
ARGVALUE49 : integer := 0;
ARGVALUE50 : integer := 0;
ARGVALUE51 : integer := 0;
ARGVALUE52 : integer := 0;
ARGVALUE53 : integer := 0;
ARGVALUE54 : integer := 0;
ARGVALUE55 : integer := 0;
ARGVALUE56 : integer := 0;
ARGVALUE57 : integer := 0;
ARGVALUE58 : integer := 0;
ARGVALUE59 : integer := 0;
ARGVALUE60 : integer := 0;
ARGVALUE61 : integer := 0;
ARGVALUE62 : integer := 0;
ARGVALUE63 : integer := 0;
ARGVALUE64 : integer := 0;
ARGVALUE65 : integer := 0;
ARGVALUE66 : integer := 0;
ARGVALUE67 : integer := 0;
ARGVALUE68 : integer := 0;
ARGVALUE69 : integer := 0;
ARGVALUE70 : integer := 0;
ARGVALUE71 : integer := 0;
ARGVALUE72 : integer := 0;
ARGVALUE73 : integer := 0;
ARGVALUE74 : integer := 0;
ARGVALUE75 : integer := 0;
ARGVALUE76 : integer := 0;
ARGVALUE77 : integer := 0;
ARGVALUE78 : integer := 0;
ARGVALUE79 : integer := 0;
ARGVALUE80 : integer := 0;
ARGVALUE81 : integer := 0;
ARGVALUE82 : integer := 0;
ARGVALUE83 : integer := 0;
ARGVALUE84 : integer := 0;
ARGVALUE85 : integer := 0;
ARGVALUE86 : integer := 0;
ARGVALUE87 : integer := 0;
ARGVALUE88 : integer := 0;
ARGVALUE89 : integer := 0;
ARGVALUE90 : integer := 0;
ARGVALUE91 : integer := 0;
ARGVALUE92 : integer := 0;
ARGVALUE93 : integer := 0;
ARGVALUE94 : integer := 0;
ARGVALUE95 : integer := 0;
ARGVALUE96 : integer := 0;
ARGVALUE97 : integer := 0;
ARGVALUE98 : integer := 0;
ARGVALUE99 : integer := 0;
BFMA1lI1 : vl_logic_vector(31 downto 0) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0);
BFMA1Ol1 : vl_logic_vector(255 downto 0) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0);
BFMA1Il1 : vl_notype;
BFMA1Ol10 : vl_logic_vector(2 downto 0) := (Hi0, Hi0, Hi0);
BFMA1Il10 : vl_logic_vector(2 downto 0) := (Hi0, Hi0, Hi1);
BFMA1ll10 : vl_logic_vector(2 downto 0) := (Hi0, Hi1, Hi0);
BFMA1O010 : vl_logic_vector(2 downto 0) := (Hi0, Hi1, Hi1);
BFMA1I010 : vl_logic_vector(2 downto 0) := (Hi1, Hi0, Hi0);
BFMA1l010 : vl_logic_vector(2 downto 0) := (Hi1, Hi0, Hi1)
);
port(
SYSCLK : in vl_logic;
SYSRSTN : in vl_logic;
PCLK : out vl_logic;
HCLK : out vl_logic;
HRESETN : out vl_logic;
HADDR : out vl_logic_vector(31 downto 0);
HBURST : out vl_logic_vector(2 downto 0);
HMASTLOCK : out vl_logic;
HPROT : out vl_logic_vector(3 downto 0);
HSIZE : out vl_logic_vector(2 downto 0);
HTRANS : out vl_logic_vector(1 downto 0);
HWRITE : out vl_logic;
HWDATA : out vl_logic_vector(31 downto 0);
HRDATA : in vl_logic_vector(31 downto 0);
HREADY : in vl_logic;
HRESP : in vl_logic;
HSEL : out vl_logic_vector(15 downto 0);
INTERRUPT : in vl_logic_vector(255 downto 0);
GP_OUT : out vl_logic_vector(31 downto 0);
GP_IN : in vl_logic_vector(31 downto 0);
EXT_WR : out vl_logic;
EXT_RD : out vl_logic;
EXT_ADDR : out vl_logic_vector(31 downto 0);
EXT_DATA : inout vl_logic_vector(31 downto 0);
EXT_WAIT : in vl_logic;
CON_ADDR : in vl_logic_vector(15 downto 0);
CON_DATA : inout vl_logic_vector(31 downto 0);
CON_RD : in vl_logic;
CON_WR : in vl_logic;
CON_BUSY : out vl_logic;
INSTR_OUT : out vl_logic_vector(31 downto 0);
INSTR_IN : in vl_logic_vector(31 downto 0);
FINISHED : out vl_logic;
FAILED : out vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of OPMODE : constant is 1;
attribute mti_svvh_generic_type of VECTFILE : constant is 1;
attribute mti_svvh_generic_type of MAX_INSTRUCTIONS : constant is 1;
attribute mti_svvh_generic_type of MAX_STACK : constant is 1;
attribute mti_svvh_generic_type of MAX_MEMTEST : constant is 1;
attribute mti_svvh_generic_type of TPD : constant is 1;
attribute mti_svvh_generic_type of DEBUGLEVEL : constant is 1;
attribute mti_svvh_generic_type of CON_SPULSE : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE0 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE1 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE2 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE3 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE4 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE5 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE6 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE7 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE8 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE9 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE10 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE11 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE12 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE13 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE14 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE15 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE16 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE17 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE18 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE19 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE20 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE21 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE22 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE23 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE24 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE25 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE26 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE27 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE28 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE29 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE30 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE31 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE32 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE33 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE34 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE35 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE36 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE37 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE38 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE39 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE40 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE41 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE42 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE43 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE44 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE45 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE46 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE47 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE48 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE49 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE50 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE51 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE52 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE53 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE54 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE55 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE56 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE57 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE58 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE59 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE60 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE61 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE62 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE63 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE64 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE65 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE66 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE67 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE68 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE69 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE70 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE71 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE72 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE73 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE74 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE75 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE76 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE77 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE78 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE79 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE80 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE81 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE82 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE83 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE84 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE85 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE86 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE87 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE88 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE89 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE90 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE91 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE92 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE93 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE94 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE95 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE96 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE97 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE98 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE99 : constant is 1;
attribute mti_svvh_generic_type of BFMA1lI1 : constant is 2;
attribute mti_svvh_generic_type of BFMA1Ol1 : constant is 2;
attribute mti_svvh_generic_type of BFMA1Il1 : constant is 3;
attribute mti_svvh_generic_type of BFMA1Ol10 : constant is 2;
attribute mti_svvh_generic_type of BFMA1Il10 : constant is 2;
attribute mti_svvh_generic_type of BFMA1ll10 : constant is 2;
attribute mti_svvh_generic_type of BFMA1O010 : constant is 2;
attribute mti_svvh_generic_type of BFMA1I010 : constant is 2;
attribute mti_svvh_generic_type of BFMA1l010 : constant is 2;
end BFM_MAIN;
| gpl-3.0 | 1284ea6b2a4f88bd8ecfbc9d7363ec50 | 0.608359 | 3.504774 | false | false | false | false |
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